diff --git a/vendor/siemens/motors-ac-3p/1kw/2KJ3601-5EK23-9AP1-Z_D14+K01+K07+L00+M55+N6C+P91_2D_dimension_withFrame_en.pdf b/vendor/siemens/motors-ac-3p/1kw/2KJ3601-5EK23-9AP1-Z_D14+K01+K07+L00+M55+N6C+P91_2D_dimension_withFrame_en.pdf
new file mode 100644
index 000000000..b14403665
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diff --git a/vendor/siemens/motors-ac-3p/1kw/2KJ3601-5EK23-9AP1-Z_D14+K01+K07+L00+M55+N6C+P91_3D_en.stp b/vendor/siemens/motors-ac-3p/1kw/2KJ3601-5EK23-9AP1-Z_D14+K01+K07+L00+M55+N6C+P91_3D_en.stp
new file mode 100644
index 000000000..fabbd5455
--- /dev/null
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+#113=STYLED_ITEM('',(#1980),#1981);
+#114=STYLED_ITEM('',(#1982),#1983);
+#115=STYLED_ITEM('',(#1984),#1985);
+#116=STYLED_ITEM('',(#1986),#1987);
+#117=STYLED_ITEM('',(#1988),#1989);
+#118=STYLED_ITEM('',(#1990),#1991);
+#119=STYLED_ITEM('',(#1992),#1993);
+#120=STYLED_ITEM('',(#1994),#1995);
+#121=STYLED_ITEM('',(#1996),#1997);
+#122=STYLED_ITEM('',(#1998),#1999);
+#123=STYLED_ITEM('',(#2000),#2001);
+#124=STYLED_ITEM('',(#2002),#2003);
+#125=STYLED_ITEM('',(#2004),#2005);
+#126=STYLED_ITEM('',(#2006),#2007);
+#127=STYLED_ITEM('',(#2008),#2009);
+#128=STYLED_ITEM('',(#2010),#2011);
+#129=STYLED_ITEM('',(#2012),#2013);
+#130=STYLED_ITEM('',(#2014),#2015);
+#131=STYLED_ITEM('',(#2016),#2017);
+#132=STYLED_ITEM('',(#2018),#2019);
+#133=STYLED_ITEM('',(#2020),#2021);
+#134=STYLED_ITEM('',(#2022),#2023);
+#135=STYLED_ITEM('',(#2024),#2025);
+#136=STYLED_ITEM('',(#2026),#2027);
+#137=STYLED_ITEM('',(#2028),#2029);
+#138=STYLED_ITEM('',(#2030),#2031);
+#139=STYLED_ITEM('',(#2032),#2033);
+#140=STYLED_ITEM('',(#2034),#2035);
+#141=STYLED_ITEM('',(#2036),#2037);
+#142=STYLED_ITEM('',(#2038),#2039);
+#143=STYLED_ITEM('',(#2040),#2041);
+#144=STYLED_ITEM('',(#2042),#2043);
+#145=STYLED_ITEM('',(#2044),#2045);
+#146=STYLED_ITEM('',(#2046),#2047);
+#147=STYLED_ITEM('',(#2048),#2049);
+#148=STYLED_ITEM('',(#2050),#2051);
+#149=STYLED_ITEM('',(#2052),#2053);
+#150=STYLED_ITEM('',(#2054),#2055);
+#151=STYLED_ITEM('',(#2056),#2057);
+#152=STYLED_ITEM('',(#2058),#2059);
+#153=STYLED_ITEM('',(#2060),#2061);
+#154=STYLED_ITEM('',(#2062),#2063);
+#155=STYLED_ITEM('',(#2064),#2065);
+#156=STYLED_ITEM('',(#2066),#2067);
+#157=STYLED_ITEM('',(#2068),#2069);
+#158=STYLED_ITEM('',(#2070),#2071);
+#159=STYLED_ITEM('',(#2072),#2073);
+#160=STYLED_ITEM('',(#2074),#2075);
+#161=STYLED_ITEM('',(#2076),#2077);
+#162=STYLED_ITEM('',(#2078),#2079);
+#163=STYLED_ITEM('',(#2080),#2081);
+#164=STYLED_ITEM('',(#2082),#2083);
+#165=STYLED_ITEM('',(#2084),#2085);
+#166=STYLED_ITEM('',(#2086),#2087);
+#167=STYLED_ITEM('',(#2088),#2089);
+#168=STYLED_ITEM('',(#2090),#2091);
+#169=STYLED_ITEM('',(#2092),#2093);
+#170=STYLED_ITEM('',(#2094),#2095);
+#171=STYLED_ITEM('',(#2096),#2097);
+#172=STYLED_ITEM('',(#2098),#2099);
+#173=STYLED_ITEM('',(#2100),#2101);
+#174=STYLED_ITEM('',(#2102),#2103);
+#175=STYLED_ITEM('',(#2104),#2105);
+#176=STYLED_ITEM('',(#2106),#2107);
+#177=STYLED_ITEM('',(#2108),#2109);
+#178=STYLED_ITEM('',(#2110),#2111);
+#179=STYLED_ITEM('',(#2112),#2113);
+#180=STYLED_ITEM('',(#2114),#2115);
+#181=STYLED_ITEM('',(#2116),#2117);
+#182=STYLED_ITEM('',(#2118),#2119);
+#183=STYLED_ITEM('',(#2120),#2121);
+#184=STYLED_ITEM('',(#2122),#2123);
+#185=STYLED_ITEM('',(#2124),#2125);
+#186=STYLED_ITEM('',(#2126),#2127);
+#187=STYLED_ITEM('',(#2128),#2129);
+#188=STYLED_ITEM('',(#2130),#2131);
+#189=STYLED_ITEM('',(#2132),#2133);
+#190=STYLED_ITEM('',(#2134),#2135);
+#191=STYLED_ITEM('',(#2136),#2137);
+#192=STYLED_ITEM('',(#2138),#2139);
+#193=STYLED_ITEM('',(#2140),#2141);
+#194=STYLED_ITEM('',(#2142),#2143);
+#195=STYLED_ITEM('',(#2144),#2145);
+#196=STYLED_ITEM('',(#2146),#2147);
+#197=STYLED_ITEM('',(#2148),#2149);
+#198=STYLED_ITEM('',(#2150),#2151);
+#199=STYLED_ITEM('',(#2152),#2153);
+#200=STYLED_ITEM('',(#2154),#2155);
+#201=STYLED_ITEM('',(#2156),#2157);
+#202=STYLED_ITEM('',(#2158),#2159);
+#203=STYLED_ITEM('',(#2160),#2161);
+#204=STYLED_ITEM('',(#2162),#2163);
+#205=STYLED_ITEM('',(#2164),#2165);
+#206=STYLED_ITEM('',(#2166),#2167);
+#207=STYLED_ITEM('',(#2168),#2169);
+#208=STYLED_ITEM('',(#2170),#2171);
+#209=STYLED_ITEM('',(#2172),#2173);
+#210=STYLED_ITEM('',(#2174),#2175);
+#211=STYLED_ITEM('',(#2176),#2177);
+#212=STYLED_ITEM('',(#2178),#2179);
+#213=STYLED_ITEM('',(#2180),#2181);
+#214=STYLED_ITEM('',(#2182),#2183);
+#215=STYLED_ITEM('',(#2184),#2185);
+#216=STYLED_ITEM('',(#2186),#2187);
+#217=STYLED_ITEM('',(#2188),#2189);
+#218=STYLED_ITEM('',(#2190),#2191);
+#219=STYLED_ITEM('',(#2192),#2193);
+#220=STYLED_ITEM('',(#2194),#2195);
+#221=STYLED_ITEM('',(#2196),#2197);
+#222=STYLED_ITEM('',(#2198),#2199);
+#223=STYLED_ITEM('',(#2200),#2201);
+#224=STYLED_ITEM('',(#2202),#2203);
+#225=STYLED_ITEM('',(#2204),#2205);
+#226=STYLED_ITEM('',(#2206),#2207);
+#227=STYLED_ITEM('',(#2208),#2209);
+#228=STYLED_ITEM('',(#2210),#2211);
+#229=STYLED_ITEM('',(#2212),#2213);
+#230=STYLED_ITEM('',(#2214),#2215);
+#231=STYLED_ITEM('',(#2216),#2217);
+#232=STYLED_ITEM('',(#2218),#2219);
+#233=STYLED_ITEM('',(#2220),#2221);
+#234=STYLED_ITEM('',(#2222),#2223);
+#235=STYLED_ITEM('',(#2224),#2225);
+#236=STYLED_ITEM('',(#2226),#2227);
+#237=STYLED_ITEM('',(#2228),#2229);
+#238=STYLED_ITEM('',(#2230),#2231);
+#239=STYLED_ITEM('',(#2232),#2233);
+#240=STYLED_ITEM('',(#2234),#2235);
+#241=STYLED_ITEM('',(#2236),#2237);
+#242=STYLED_ITEM('',(#2238),#2239);
+#243=STYLED_ITEM('',(#2240),#2241);
+#244=STYLED_ITEM('',(#2242),#2243);
+#245=STYLED_ITEM('',(#2244),#2245);
+#246=STYLED_ITEM('',(#2246),#2247);
+#247=STYLED_ITEM('',(#2248),#2249);
+#248=STYLED_ITEM('',(#2250),#2251);
+#249=STYLED_ITEM('',(#2252),#2253);
+#250=STYLED_ITEM('',(#2254),#2255);
+#251=STYLED_ITEM('',(#2256),#2257);
+#252=STYLED_ITEM('',(#2258),#2259);
+#253=STYLED_ITEM('',(#2260),#2261);
+#254=STYLED_ITEM('',(#2262),#2263);
+#255=STYLED_ITEM('',(#2264),#2265);
+#256=STYLED_ITEM('',(#2266),#2267);
+#257=STYLED_ITEM('',(#2268),#2269);
+#258=STYLED_ITEM('',(#2270),#2271);
+#259=STYLED_ITEM('',(#2272),#2273);
+#260=STYLED_ITEM('',(#2274),#2275);
+#261=STYLED_ITEM('',(#2276),#2277);
+#262=STYLED_ITEM('',(#2278),#2279);
+#263=STYLED_ITEM('',(#2280),#2281);
+#264=STYLED_ITEM('',(#2282),#2283);
+#265=STYLED_ITEM('',(#2284),#2285);
+#266=STYLED_ITEM('',(#2286),#2287);
+#267=STYLED_ITEM('',(#2288),#2289);
+#268=STYLED_ITEM('',(#2290),#2291);
+#269=STYLED_ITEM('',(#2292),#2293);
+#270=STYLED_ITEM('',(#2294),#2295);
+#271=STYLED_ITEM('',(#2296),#2297);
+#272=STYLED_ITEM('',(#2298),#2299);
+#273=STYLED_ITEM('',(#2300),#2301);
+#274=STYLED_ITEM('',(#2302),#2303);
+#275=STYLED_ITEM('',(#2304),#2305);
+#276=STYLED_ITEM('',(#2306),#2307);
+#277=STYLED_ITEM('',(#2308),#2309);
+#278=STYLED_ITEM('',(#2310),#2311);
+#279=STYLED_ITEM('',(#2312),#2313);
+#280=STYLED_ITEM('',(#2314),#2315);
+#281=STYLED_ITEM('',(#2316),#2317);
+#282=STYLED_ITEM('',(#2318),#2319);
+#283=STYLED_ITEM('',(#2320),#2321);
+#284=STYLED_ITEM('',(#2322),#2323);
+#285=STYLED_ITEM('',(#2324),#2325);
+#286=STYLED_ITEM('',(#2326),#2327);
+#287=STYLED_ITEM('',(#2328),#2329);
+#288=STYLED_ITEM('',(#2330),#2331);
+#289=STYLED_ITEM('',(#2332),#2333);
+#290=STYLED_ITEM('',(#2334),#2335);
+#291=STYLED_ITEM('',(#2336),#2337);
+#292=STYLED_ITEM('',(#2338),#2339);
+#293=STYLED_ITEM('',(#2340),#2341);
+#294=STYLED_ITEM('',(#2342),#2343);
+#295=STYLED_ITEM('',(#2344),#2345);
+#296=STYLED_ITEM('',(#2346),#2347);
+#297=STYLED_ITEM('',(#2348),#2349);
+#298=STYLED_ITEM('',(#2350),#2351);
+#299=STYLED_ITEM('',(#2352),#2353);
+#300=STYLED_ITEM('',(#2354),#2355);
+#301=STYLED_ITEM('',(#2356),#2357);
+#302=STYLED_ITEM('',(#2358),#2359);
+#303=STYLED_ITEM('',(#2360),#2361);
+#304=STYLED_ITEM('',(#2362),#2363);
+#305=STYLED_ITEM('',(#2364),#2365);
+#306=STYLED_ITEM('',(#2366),#2367);
+#307=STYLED_ITEM('',(#2368),#2369);
+#308=STYLED_ITEM('',(#2370),#2371);
+#309=STYLED_ITEM('',(#2372),#2373);
+#310=STYLED_ITEM('',(#2374),#2375);
+#311=STYLED_ITEM('',(#2376),#2377);
+#312=STYLED_ITEM('',(#2378),#2379);
+#313=STYLED_ITEM('',(#2380),#2381);
+#314=STYLED_ITEM('',(#2382),#2383);
+#315=STYLED_ITEM('',(#2384),#2385);
+#316=STYLED_ITEM('',(#2386),#2387);
+#317=STYLED_ITEM('',(#2388),#2389);
+#318=STYLED_ITEM('',(#2390),#2391);
+#319=STYLED_ITEM('',(#2392),#2393);
+#320=STYLED_ITEM('',(#2394),#2395);
+#321=STYLED_ITEM('',(#2396),#2397);
+#322=STYLED_ITEM('',(#2398),#2399);
+#323=STYLED_ITEM('',(#2400),#2401);
+#324=STYLED_ITEM('',(#2402),#2403);
+#325=STYLED_ITEM('',(#2404),#2405);
+#326=STYLED_ITEM('',(#2406),#2407);
+#327=STYLED_ITEM('',(#2408),#2409);
+#328=STYLED_ITEM('',(#2410),#2411);
+#329=STYLED_ITEM('',(#2412),#2413);
+#330=STYLED_ITEM('',(#2414),#2415);
+#331=STYLED_ITEM('',(#2416),#2417);
+#332=STYLED_ITEM('',(#2418),#2419);
+#333=STYLED_ITEM('',(#2420),#2421);
+#334=STYLED_ITEM('',(#2422),#2423);
+#335=STYLED_ITEM('',(#2424),#2425);
+#336=STYLED_ITEM('',(#2426),#2427);
+#337=STYLED_ITEM('',(#2428),#2429);
+#338=STYLED_ITEM('',(#2430),#2431);
+#339=STYLED_ITEM('',(#2432),#2433);
+#340=STYLED_ITEM('',(#2434),#2435);
+#341=STYLED_ITEM('',(#2436),#2437);
+#342=STYLED_ITEM('',(#2438),#2439);
+#343=STYLED_ITEM('',(#2440),#2441);
+#344=STYLED_ITEM('',(#2442),#2443);
+#345=STYLED_ITEM('',(#2444),#2445);
+#346=STYLED_ITEM('',(#2446),#2447);
+#347=STYLED_ITEM('',(#2448),#2449);
+#348=STYLED_ITEM('',(#2450),#2451);
+#349=STYLED_ITEM('',(#2452),#2453);
+#350=STYLED_ITEM('',(#2454),#2455);
+#351=STYLED_ITEM('',(#2456),#2457);
+#352=STYLED_ITEM('',(#2458),#2459);
+#353=STYLED_ITEM('',(#2460),#2461);
+#354=STYLED_ITEM('',(#2462),#2463);
+#355=STYLED_ITEM('',(#2464),#2465);
+#356=STYLED_ITEM('',(#2466),#2467);
+#357=STYLED_ITEM('',(#2468),#2469);
+#358=STYLED_ITEM('',(#2470),#2471);
+#359=STYLED_ITEM('',(#2472),#2473);
+#360=STYLED_ITEM('',(#2474),#2475);
+#361=STYLED_ITEM('',(#2476),#2477);
+#362=STYLED_ITEM('',(#2478),#2479);
+#363=STYLED_ITEM('',(#2480),#2481);
+#364=STYLED_ITEM('',(#2482),#2483);
+#365=STYLED_ITEM('',(#2484),#2485);
+#366=STYLED_ITEM('',(#2486),#2487);
+#367=STYLED_ITEM('',(#2488),#2489);
+#368=STYLED_ITEM('',(#2490),#2491);
+#369=STYLED_ITEM('',(#2492),#2493);
+#370=STYLED_ITEM('',(#2494),#2495);
+#371=STYLED_ITEM('',(#2496),#2497);
+#372=STYLED_ITEM('',(#2498),#2499);
+#373=STYLED_ITEM('',(#2500),#2501);
+#374=STYLED_ITEM('',(#2502),#2503);
+#375=STYLED_ITEM('',(#2504),#2505);
+#376=STYLED_ITEM('',(#2506),#2507);
+#377=STYLED_ITEM('',(#2508),#2509);
+#378=STYLED_ITEM('',(#2510),#2511);
+#379=STYLED_ITEM('',(#2512),#2513);
+#380=STYLED_ITEM('',(#2514),#2515);
+#381=STYLED_ITEM('',(#2516),#2517);
+#382=STYLED_ITEM('',(#2518),#2519);
+#383=STYLED_ITEM('',(#2520),#2521);
+#384=STYLED_ITEM('',(#2522),#2523);
+#385=STYLED_ITEM('',(#2524),#2525);
+#386=STYLED_ITEM('',(#2526),#2527);
+#387=STYLED_ITEM('',(#2528),#2529);
+#388=STYLED_ITEM('',(#2530),#2531);
+#389=STYLED_ITEM('',(#2532),#2533);
+#390=STYLED_ITEM('',(#2534),#2535);
+#391=STYLED_ITEM('',(#2536),#2537);
+#392=STYLED_ITEM('',(#2538),#2539);
+#393=STYLED_ITEM('',(#2540),#2541);
+#394=STYLED_ITEM('',(#2542),#2543);
+#395=STYLED_ITEM('',(#2544),#2545);
+#396=STYLED_ITEM('',(#2546),#2547);
+#397=STYLED_ITEM('',(#2548),#2549);
+#398=STYLED_ITEM('',(#2550),#2551);
+#399=STYLED_ITEM('',(#2552),#2553);
+#400=STYLED_ITEM('',(#2554),#2555);
+#401=STYLED_ITEM('',(#2556),#2557);
+#402=STYLED_ITEM('',(#2558),#2559);
+#403=STYLED_ITEM('',(#2560),#2561);
+#404=STYLED_ITEM('',(#2562),#2563);
+#405=STYLED_ITEM('',(#2564),#2565);
+#406=STYLED_ITEM('',(#2566),#2567);
+#407=STYLED_ITEM('',(#2568),#2569);
+#408=STYLED_ITEM('',(#2570),#2571);
+#409=STYLED_ITEM('',(#2572),#2573);
+#410=STYLED_ITEM('',(#2574),#2575);
+#411=STYLED_ITEM('',(#2576),#2577);
+#412=STYLED_ITEM('',(#2578),#2579);
+#413=STYLED_ITEM('',(#2580),#2581);
+#414=STYLED_ITEM('',(#2582),#2583);
+#415=STYLED_ITEM('',(#2584),#2585);
+#416=STYLED_ITEM('',(#2586),#2587);
+#417=STYLED_ITEM('',(#2588),#2589);
+#418=STYLED_ITEM('',(#2590),#2591);
+#419=STYLED_ITEM('',(#2592),#2593);
+#420=STYLED_ITEM('',(#2594),#2595);
+#421=STYLED_ITEM('',(#2596),#2597);
+#422=STYLED_ITEM('',(#2598),#2599);
+#423=STYLED_ITEM('',(#2600),#2601);
+#424=STYLED_ITEM('',(#2602),#2603);
+#425=STYLED_ITEM('',(#2604),#2605);
+#426=STYLED_ITEM('',(#2606),#2607);
+#427=STYLED_ITEM('',(#2608),#2609);
+#428=STYLED_ITEM('',(#2610),#2611);
+#429=STYLED_ITEM('',(#2612),#2613);
+#430=STYLED_ITEM('',(#2614),#2615);
+#431=STYLED_ITEM('',(#2616),#2617);
+#432=STYLED_ITEM('',(#2618),#2619);
+#433=STYLED_ITEM('',(#2620),#2621);
+#434=STYLED_ITEM('',(#2622),#2623);
+#435=STYLED_ITEM('',(#2624),#2625);
+#436=STYLED_ITEM('',(#2626),#2627);
+#437=STYLED_ITEM('',(#2628),#2629);
+#438=STYLED_ITEM('',(#2630),#2631);
+#439=STYLED_ITEM('',(#2632),#2633);
+#440=STYLED_ITEM('',(#2634),#2635);
+#441=STYLED_ITEM('',(#2636),#2637);
+#442=STYLED_ITEM('',(#2638),#2639);
+#443=STYLED_ITEM('',(#2640),#2641);
+#444=STYLED_ITEM('',(#2642),#2643);
+#445=STYLED_ITEM('',(#2644),#2645);
+#446=STYLED_ITEM('',(#2646),#2647);
+#447=STYLED_ITEM('',(#2648),#2649);
+#448=STYLED_ITEM('',(#2650),#2651);
+#449=STYLED_ITEM('',(#2652),#2653);
+#450=STYLED_ITEM('',(#2654),#2655);
+#451=STYLED_ITEM('',(#2656),#2657);
+#452=STYLED_ITEM('',(#2658),#2659);
+#453=STYLED_ITEM('',(#2660),#2661);
+#454=STYLED_ITEM('',(#2662),#2663);
+#455=STYLED_ITEM('',(#2664),#2665);
+#456=STYLED_ITEM('',(#2666),#2667);
+#457=STYLED_ITEM('',(#2668),#2669);
+#458=STYLED_ITEM('',(#2670),#2671);
+#459=STYLED_ITEM('',(#2672),#2673);
+#460=STYLED_ITEM('',(#2674),#2675);
+#461=STYLED_ITEM('',(#2676),#2677);
+#462=STYLED_ITEM('',(#2678),#2679);
+#463=STYLED_ITEM('',(#2680),#2681);
+#464=STYLED_ITEM('',(#2682),#2683);
+#465=STYLED_ITEM('',(#2684),#2685);
+#466=STYLED_ITEM('',(#2686),#2687);
+#467=STYLED_ITEM('',(#2688),#2689);
+#468=STYLED_ITEM('',(#2690),#2691);
+#469=STYLED_ITEM('',(#2692),#2693);
+#470=STYLED_ITEM('',(#2694),#2695);
+#471=STYLED_ITEM('',(#2696),#2697);
+#472=STYLED_ITEM('',(#2698),#2699);
+#473=STYLED_ITEM('',(#2700),#2701);
+#474=STYLED_ITEM('',(#2702),#2703);
+#475=STYLED_ITEM('',(#2704),#2705);
+#476=STYLED_ITEM('',(#2706),#2707);
+#477=STYLED_ITEM('',(#2708),#2709);
+#478=STYLED_ITEM('',(#2710),#2711);
+#479=STYLED_ITEM('',(#2712),#2713);
+#480=STYLED_ITEM('',(#2714),#2715);
+#481=STYLED_ITEM('',(#2716),#2717);
+#482=STYLED_ITEM('',(#2718),#2719);
+#483=STYLED_ITEM('',(#2720),#2721);
+#484=STYLED_ITEM('',(#2722),#2723);
+#485=STYLED_ITEM('',(#2724),#2725);
+#486=STYLED_ITEM('',(#2726),#2727);
+#487=STYLED_ITEM('',(#2728),#2729);
+#488=STYLED_ITEM('',(#2730),#2731);
+#489=STYLED_ITEM('',(#2732),#2733);
+#490=STYLED_ITEM('',(#2734),#2735);
+#491=STYLED_ITEM('',(#2736),#2737);
+#492=STYLED_ITEM('',(#2738),#2739);
+#493=STYLED_ITEM('',(#2740),#2741);
+#494=STYLED_ITEM('',(#2742),#2743);
+#495=STYLED_ITEM('',(#2744),#2745);
+#496=STYLED_ITEM('',(#2746),#2747);
+#497=STYLED_ITEM('',(#2748),#2749);
+#498=STYLED_ITEM('',(#2750),#2751);
+#499=STYLED_ITEM('',(#2752),#2753);
+#500=STYLED_ITEM('',(#2754),#2755);
+#501=STYLED_ITEM('',(#2756),#2757);
+#502=STYLED_ITEM('',(#2758),#2759);
+#503=STYLED_ITEM('',(#2760),#2761);
+#504=STYLED_ITEM('',(#2762),#2763);
+#505=STYLED_ITEM('',(#2764),#2765);
+#506=STYLED_ITEM('',(#2766),#2767);
+#507=STYLED_ITEM('',(#2768),#2769);
+#508=STYLED_ITEM('',(#2770),#2771);
+#509=STYLED_ITEM('',(#2772),#2773);
+#510=STYLED_ITEM('',(#2774),#2775);
+#511=STYLED_ITEM('',(#2776),#2777);
+#512=STYLED_ITEM('',(#2778),#2779);
+#513=STYLED_ITEM('',(#2780),#2781);
+#514=STYLED_ITEM('',(#2782),#2783);
+#515=STYLED_ITEM('',(#2784),#2785);
+#516=STYLED_ITEM('',(#2786),#2787);
+#517=STYLED_ITEM('',(#2788),#2789);
+#518=STYLED_ITEM('',(#2790),#2791);
+#519=STYLED_ITEM('',(#2792),#2793);
+#520=STYLED_ITEM('',(#2794),#2795);
+#521=STYLED_ITEM('',(#2796),#2797);
+#522=STYLED_ITEM('',(#2798),#2799);
+#523=STYLED_ITEM('',(#2800),#2801);
+#524=STYLED_ITEM('',(#2802),#2803);
+#525=STYLED_ITEM('',(#2804),#2805);
+#526=STYLED_ITEM('',(#2806),#2807);
+#527=STYLED_ITEM('',(#2808),#2809);
+#528=STYLED_ITEM('',(#2810),#2811);
+#529=STYLED_ITEM('',(#2812),#2813);
+#530=STYLED_ITEM('',(#2814),#2815);
+#531=STYLED_ITEM('',(#2816),#2817);
+#532=STYLED_ITEM('',(#2818),#2819);
+#533=STYLED_ITEM('',(#2820),#2821);
+#534=STYLED_ITEM('',(#2822),#2823);
+#535=STYLED_ITEM('',(#2824),#2825);
+#536=STYLED_ITEM('',(#2826),#2827);
+#537=STYLED_ITEM('',(#2828),#2829);
+#538=STYLED_ITEM('',(#2830),#2831);
+#539=STYLED_ITEM('',(#2832),#2833);
+#540=STYLED_ITEM('',(#2834),#2835);
+#541=STYLED_ITEM('',(#2836),#2837);
+#542=STYLED_ITEM('',(#2838),#2839);
+#543=STYLED_ITEM('',(#2840),#2841);
+#544=STYLED_ITEM('',(#2842),#2843);
+#545=STYLED_ITEM('',(#2844),#2845);
+#546=STYLED_ITEM('',(#2846),#2847);
+#547=STYLED_ITEM('',(#2848),#2849);
+#548=STYLED_ITEM('',(#2850),#2851);
+#549=STYLED_ITEM('',(#2852),#2853);
+#550=STYLED_ITEM('',(#2854),#2855);
+#551=STYLED_ITEM('',(#2856),#2857);
+#552=STYLED_ITEM('',(#2858),#2859);
+#553=STYLED_ITEM('',(#2860),#2861);
+#554=STYLED_ITEM('',(#2862),#2863);
+#555=STYLED_ITEM('',(#2864),#2865);
+#556=STYLED_ITEM('',(#2866),#2867);
+#557=STYLED_ITEM('',(#2868),#2869);
+#558=STYLED_ITEM('',(#2870),#2871);
+#559=STYLED_ITEM('',(#2872),#2873);
+#560=STYLED_ITEM('',(#2874),#2875);
+#561=STYLED_ITEM('',(#2876),#2877);
+#562=STYLED_ITEM('',(#2878),#2879);
+#563=STYLED_ITEM('',(#2880),#2881);
+#564=STYLED_ITEM('',(#2882),#2883);
+#565=STYLED_ITEM('',(#2884),#2885);
+#566=STYLED_ITEM('',(#2886),#2887);
+#567=STYLED_ITEM('',(#2888),#2889);
+#568=STYLED_ITEM('',(#2890),#2891);
+#569=STYLED_ITEM('',(#2892),#2893);
+#570=STYLED_ITEM('',(#2894),#2895);
+#571=STYLED_ITEM('',(#2896),#2897);
+#572=STYLED_ITEM('',(#2898),#2899);
+#573=STYLED_ITEM('',(#2900),#2901);
+#574=STYLED_ITEM('',(#2902),#2903);
+#575=STYLED_ITEM('',(#2904),#2905);
+#576=STYLED_ITEM('',(#2906),#2907);
+#577=STYLED_ITEM('',(#2908),#2909);
+#578=STYLED_ITEM('',(#2910),#2911);
+#579=STYLED_ITEM('',(#2912),#2913);
+#580=STYLED_ITEM('',(#2914),#2915);
+#581=STYLED_ITEM('',(#2916),#2917);
+#582=STYLED_ITEM('',(#2918),#2919);
+#583=STYLED_ITEM('',(#2920),#2921);
+#584=STYLED_ITEM('',(#2922),#2923);
+#585=STYLED_ITEM('',(#2924),#2925);
+#586=STYLED_ITEM('',(#2926),#2927);
+#587=STYLED_ITEM('',(#2928),#2929);
+#588=STYLED_ITEM('',(#2930),#2931);
+#589=STYLED_ITEM('',(#2932),#2933);
+#590=STYLED_ITEM('',(#2934),#2935);
+#591=STYLED_ITEM('',(#2936),#2937);
+#592=STYLED_ITEM('',(#2938),#2939);
+#593=STYLED_ITEM('',(#2940),#2941);
+#594=STYLED_ITEM('',(#2942),#2943);
+#595=STYLED_ITEM('',(#2944),#2945);
+#596=STYLED_ITEM('',(#2946),#2947);
+#597=STYLED_ITEM('',(#2948),#2949);
+#598=STYLED_ITEM('',(#2950),#2951);
+#599=STYLED_ITEM('',(#2952),#2953);
+#600=STYLED_ITEM('',(#2954),#2955);
+#601=STYLED_ITEM('',(#2956),#2957);
+#602=STYLED_ITEM('',(#2958),#2959);
+#603=STYLED_ITEM('',(#2960),#2961);
+#604=STYLED_ITEM('',(#2962),#2963);
+#605=STYLED_ITEM('',(#2964),#2965);
+#606=STYLED_ITEM('',(#2966),#2967);
+#607=STYLED_ITEM('',(#2968),#2969);
+#608=STYLED_ITEM('',(#2970),#2971);
+#609=STYLED_ITEM('',(#2972),#2973);
+#610=STYLED_ITEM('',(#2974),#2975);
+#611=STYLED_ITEM('',(#2976),#2977);
+#612=STYLED_ITEM('',(#2978),#2979);
+#613=STYLED_ITEM('',(#2980),#2981);
+#614=STYLED_ITEM('',(#2982),#2983);
+#615=STYLED_ITEM('',(#2984),#2985);
+#616=STYLED_ITEM('',(#2986),#2987);
+#617=STYLED_ITEM('',(#2988),#2989);
+#618=STYLED_ITEM('',(#2990),#2991);
+#619=STYLED_ITEM('',(#2992),#2993);
+#620=STYLED_ITEM('',(#2994),#2995);
+#621=STYLED_ITEM('',(#2996),#2997);
+#622=STYLED_ITEM('',(#2998),#2999);
+#623=STYLED_ITEM('',(#3000),#3001);
+#624=STYLED_ITEM('',(#3002),#3003);
+#625=STYLED_ITEM('',(#3004),#3005);
+#626=STYLED_ITEM('',(#3006),#3007);
+#627=STYLED_ITEM('',(#3008),#3009);
+#628=STYLED_ITEM('',(#3010),#3011);
+#629=STYLED_ITEM('',(#3012),#3013);
+#630=STYLED_ITEM('',(#3014),#3015);
+#631=STYLED_ITEM('',(#3016),#3017);
+#632=STYLED_ITEM('',(#3018),#3019);
+#633=STYLED_ITEM('',(#3020),#3021);
+#634=STYLED_ITEM('',(#3022),#3023);
+#635=STYLED_ITEM('',(#3024),#3025);
+#636=STYLED_ITEM('',(#3026),#3027);
+#637=STYLED_ITEM('',(#3028),#3029);
+#638=STYLED_ITEM('',(#3030),#3031);
+#639=STYLED_ITEM('',(#3032),#3033);
+#640=STYLED_ITEM('',(#3034),#3035);
+#641=STYLED_ITEM('',(#3036),#3037);
+#642=STYLED_ITEM('',(#3038),#3039);
+#643=STYLED_ITEM('',(#3040),#3041);
+#644=STYLED_ITEM('',(#3042),#3043);
+#645=STYLED_ITEM('',(#3044),#3045);
+#646=STYLED_ITEM('',(#3046),#3047);
+#647=STYLED_ITEM('',(#3048),#3049);
+#648=STYLED_ITEM('',(#3050),#3051);
+#649=STYLED_ITEM('',(#3052),#3053);
+#650=STYLED_ITEM('',(#3054),#3055);
+#651=STYLED_ITEM('',(#3056),#3057);
+#652=STYLED_ITEM('',(#3058),#3059);
+#653=STYLED_ITEM('',(#3060),#3061);
+#654=STYLED_ITEM('',(#3062),#3063);
+#655=STYLED_ITEM('',(#3064),#3065);
+#656=STYLED_ITEM('',(#3066),#3067);
+#657=STYLED_ITEM('',(#3068),#3069);
+#658=STYLED_ITEM('',(#3070),#3071);
+#659=STYLED_ITEM('',(#3072),#3073);
+#660=STYLED_ITEM('',(#3074),#3075);
+#661=STYLED_ITEM('',(#3076),#3077);
+#662=STYLED_ITEM('',(#3078),#3079);
+#663=STYLED_ITEM('',(#3080),#3081);
+#664=STYLED_ITEM('',(#3082),#3083);
+#665=STYLED_ITEM('',(#3084),#3085);
+#666=STYLED_ITEM('',(#3086),#3087);
+#667=STYLED_ITEM('',(#3088),#3089);
+#668=STYLED_ITEM('',(#3090),#3091);
+#669=STYLED_ITEM('',(#3092),#3093);
+#670=STYLED_ITEM('',(#3094),#3095);
+#671=STYLED_ITEM('',(#3096),#3097);
+#672=STYLED_ITEM('',(#3098),#3099);
+#673=STYLED_ITEM('',(#3100),#3101);
+#674=STYLED_ITEM('',(#3102),#3103);
+#675=STYLED_ITEM('',(#3104),#3105);
+#676=STYLED_ITEM('',(#3106),#3107);
+#677=STYLED_ITEM('',(#3108),#3109);
+#678=STYLED_ITEM('',(#3110),#3111);
+#679=STYLED_ITEM('',(#3112),#3113);
+#680=STYLED_ITEM('',(#3114),#3115);
+#681=STYLED_ITEM('',(#3116),#3117);
+#682=STYLED_ITEM('',(#3118),#3119);
+#683=STYLED_ITEM('',(#3120),#3121);
+#684=STYLED_ITEM('',(#3122),#3123);
+#685=STYLED_ITEM('',(#3124),#3125);
+#686=STYLED_ITEM('',(#3126),#3127);
+#687=STYLED_ITEM('',(#3128),#3129);
+#688=STYLED_ITEM('',(#3130),#3131);
+#689=STYLED_ITEM('',(#3132),#3133);
+#690=STYLED_ITEM('',(#3134),#3135);
+#691=STYLED_ITEM('',(#3136),#3137);
+#692=STYLED_ITEM('',(#3138),#3139);
+#693=STYLED_ITEM('',(#3140),#3141);
+#694=STYLED_ITEM('',(#3142),#3143);
+#695=STYLED_ITEM('',(#3144),#3145);
+#696=STYLED_ITEM('',(#3146),#3147);
+#697=STYLED_ITEM('',(#3148),#3149);
+#698=STYLED_ITEM('',(#3150),#3151);
+#699=STYLED_ITEM('',(#3152),#3153);
+#700=STYLED_ITEM('',(#3154),#3155);
+#701=STYLED_ITEM('',(#3156),#1885);
+#702=STYLED_ITEM('',(#3157),#1886);
+#703=STYLED_ITEM('',(#3158),#1887);
+#704=STYLED_ITEM('',(#3159),#3160);
+#705=STYLED_ITEM('',(#3161),#3162);
+#706=STYLED_ITEM('',(#3163),#3164);
+#707=STYLED_ITEM('',(#3165),#3166);
+#708=STYLED_ITEM('',(#3167),#3168);
+#709=STYLED_ITEM('',(#3169),#3170);
+#710=STYLED_ITEM('',(#3171),#3172);
+#711=STYLED_ITEM('',(#3173),#3174);
+#712=STYLED_ITEM('',(#3175),#3176);
+#713=STYLED_ITEM('',(#3177),#3178);
+#714=STYLED_ITEM('',(#3179),#3180);
+#715=STYLED_ITEM('',(#3181),#3182);
+#716=STYLED_ITEM('',(#3183),#3184);
+#717=STYLED_ITEM('',(#3185),#3186);
+#718=STYLED_ITEM('',(#3187),#3188);
+#719=STYLED_ITEM('',(#3189),#3190);
+#720=STYLED_ITEM('',(#3191),#3192);
+#721=STYLED_ITEM('',(#3193),#3194);
+#722=STYLED_ITEM('',(#3195),#3196);
+#723=STYLED_ITEM('',(#3197),#3198);
+#724=STYLED_ITEM('',(#3199),#3200);
+#725=STYLED_ITEM('',(#3201),#3202);
+#726=STYLED_ITEM('',(#3203),#3204);
+#727=STYLED_ITEM('',(#3205),#3206);
+#728=STYLED_ITEM('',(#3207),#3208);
+#729=STYLED_ITEM('',(#3209),#3210);
+#730=STYLED_ITEM('',(#3211),#3212);
+#731=STYLED_ITEM('',(#3213),#3214);
+#732=STYLED_ITEM('',(#3215),#3216);
+#733=STYLED_ITEM('',(#3217),#3218);
+#734=STYLED_ITEM('',(#3219),#1895);
+#735=STYLED_ITEM('',(#3220),#3221);
+#736=STYLED_ITEM('',(#3222),#3223);
+#737=STYLED_ITEM('',(#3224),#3225);
+#738=STYLED_ITEM('',(#3226),#3227);
+#739=STYLED_ITEM('',(#3228),#3229);
+#740=STYLED_ITEM('',(#3230),#3231);
+#741=STYLED_ITEM('',(#3232),#3233);
+#742=STYLED_ITEM('',(#3234),#3235);
+#743=STYLED_ITEM('',(#3236),#3237);
+#744=STYLED_ITEM('',(#3238),#3239);
+#745=STYLED_ITEM('',(#3240),#3241);
+#746=STYLED_ITEM('',(#3242),#3243);
+#747=STYLED_ITEM('',(#3244),#3245);
+#748=STYLED_ITEM('',(#3246),#3247);
+#749=STYLED_ITEM('',(#3248),#3249);
+#750=STYLED_ITEM('',(#3250),#3251);
+#751=STYLED_ITEM('',(#3252),#3253);
+#752=STYLED_ITEM('',(#3254),#3255);
+#753=STYLED_ITEM('',(#3256),#3257);
+#754=STYLED_ITEM('',(#3258),#3259);
+#755=STYLED_ITEM('',(#3260),#3261);
+#756=STYLED_ITEM('',(#3262),#3263);
+#757=STYLED_ITEM('',(#3264),#3265);
+#758=STYLED_ITEM('',(#3266),#3267);
+#759=STYLED_ITEM('',(#3268),#3269);
+#760=STYLED_ITEM('',(#3270),#3271);
+#761=STYLED_ITEM('',(#3272),#3273);
+#762=STYLED_ITEM('',(#3274),#3275);
+#763=STYLED_ITEM('',(#3276),#3277);
+#764=STYLED_ITEM('',(#3278),#3279);
+#765=STYLED_ITEM('',(#3280),#3281);
+#766=STYLED_ITEM('',(#3282),#3283);
+#767=STYLED_ITEM('',(#3284),#3285);
+#768=STYLED_ITEM('',(#3286),#3287);
+#769=STYLED_ITEM('',(#3288),#3289);
+#770=STYLED_ITEM('',(#3290),#3291);
+#771=STYLED_ITEM('',(#3292),#3293);
+#772=STYLED_ITEM('',(#3294),#3295);
+#773=STYLED_ITEM('',(#3296),#3297);
+#774=STYLED_ITEM('',(#3298),#3299);
+#775=STYLED_ITEM('',(#3300),#3301);
+#776=STYLED_ITEM('',(#3302),#3303);
+#777=STYLED_ITEM('',(#3304),#3305);
+#778=STYLED_ITEM('',(#3306),#3307);
+#779=STYLED_ITEM('',(#3308),#3309);
+#780=STYLED_ITEM('',(#3310),#3311);
+#781=STYLED_ITEM('',(#3312),#3313);
+#782=STYLED_ITEM('',(#3314),#3315);
+#783=STYLED_ITEM('',(#3316),#3317);
+#784=STYLED_ITEM('',(#3318),#3319);
+#785=STYLED_ITEM('',(#3320),#3321);
+#786=STYLED_ITEM('',(#3322),#3323);
+#787=STYLED_ITEM('',(#3324),#3325);
+#788=STYLED_ITEM('',(#3326),#3327);
+#789=STYLED_ITEM('',(#3328),#3329);
+#790=STYLED_ITEM('',(#3330),#3331);
+#791=STYLED_ITEM('',(#3332),#3333);
+#792=STYLED_ITEM('',(#3334),#3335);
+#793=STYLED_ITEM('',(#3336),#3337);
+#794=STYLED_ITEM('',(#3338),#3339);
+#795=STYLED_ITEM('',(#3340),#3341);
+#796=STYLED_ITEM('',(#3342),#3343);
+#797=STYLED_ITEM('',(#3344),#3345);
+#798=STYLED_ITEM('',(#3346),#3347);
+#799=STYLED_ITEM('',(#3348),#3349);
+#800=STYLED_ITEM('',(#3350),#3351);
+#801=STYLED_ITEM('',(#3352),#3353);
+#802=STYLED_ITEM('',(#3354),#3355);
+#803=STYLED_ITEM('',(#3356),#3357);
+#804=STYLED_ITEM('',(#3358),#3359);
+#805=STYLED_ITEM('',(#3360),#3361);
+#806=STYLED_ITEM('',(#3362),#3363);
+#807=STYLED_ITEM('',(#3364),#3365);
+#808=STYLED_ITEM('',(#3366),#3367);
+#809=STYLED_ITEM('',(#3368),#3369);
+#810=STYLED_ITEM('',(#3370),#3371);
+#811=STYLED_ITEM('',(#3372),#3373);
+#812=STYLED_ITEM('',(#3374),#3375);
+#813=STYLED_ITEM('',(#3376),#3377);
+#814=STYLED_ITEM('',(#3378),#3379);
+#815=STYLED_ITEM('',(#3380),#3381);
+#816=STYLED_ITEM('',(#3382),#3383);
+#817=STYLED_ITEM('',(#3384),#3385);
+#818=STYLED_ITEM('',(#3386),#3387);
+#819=STYLED_ITEM('',(#3388),#3389);
+#820=STYLED_ITEM('',(#3390),#3391);
+#821=STYLED_ITEM('',(#3392),#3393);
+#822=STYLED_ITEM('',(#3394),#3395);
+#823=STYLED_ITEM('',(#3396),#3397);
+#824=STYLED_ITEM('',(#3398),#3399);
+#825=STYLED_ITEM('',(#3400),#3401);
+#826=STYLED_ITEM('',(#3402),#3403);
+#827=STYLED_ITEM('',(#3404),#3405);
+#828=STYLED_ITEM('',(#3406),#3407);
+#829=STYLED_ITEM('',(#3408),#3409);
+#830=STYLED_ITEM('',(#3410),#3411);
+#831=STYLED_ITEM('',(#3412),#3413);
+#832=STYLED_ITEM('',(#3414),#3415);
+#833=STYLED_ITEM('',(#3416),#3417);
+#834=STYLED_ITEM('',(#3418),#3419);
+#835=STYLED_ITEM('',(#3420),#3421);
+#836=STYLED_ITEM('',(#3422),#3423);
+#837=STYLED_ITEM('',(#3424),#3425);
+#838=STYLED_ITEM('',(#3426),#3427);
+#839=STYLED_ITEM('',(#3428),#3429);
+#840=STYLED_ITEM('',(#3430),#3431);
+#841=STYLED_ITEM('',(#3432),#3433);
+#842=STYLED_ITEM('',(#3434),#3435);
+#843=STYLED_ITEM('',(#3436),#3437);
+#844=STYLED_ITEM('',(#3438),#3439);
+#845=STYLED_ITEM('',(#3440),#3441);
+#846=STYLED_ITEM('',(#3442),#3443);
+#847=STYLED_ITEM('',(#3444),#3445);
+#848=STYLED_ITEM('',(#3446),#3447);
+#849=STYLED_ITEM('',(#3448),#3449);
+#850=STYLED_ITEM('',(#3450),#3451);
+#851=STYLED_ITEM('',(#3452),#3453);
+#852=STYLED_ITEM('',(#3454),#3455);
+#853=STYLED_ITEM('',(#3456),#3457);
+#854=STYLED_ITEM('',(#3458),#3459);
+#855=STYLED_ITEM('',(#3460),#3461);
+#856=STYLED_ITEM('',(#3462),#3463);
+#857=STYLED_ITEM('',(#3464),#3465);
+#858=STYLED_ITEM('',(#3466),#3467);
+#859=STYLED_ITEM('',(#3468),#3469);
+#860=STYLED_ITEM('',(#3470),#3471);
+#861=STYLED_ITEM('',(#3472),#3473);
+#862=STYLED_ITEM('',(#3474),#3475);
+#863=STYLED_ITEM('',(#3476),#3477);
+#864=STYLED_ITEM('',(#3478),#3479);
+#865=STYLED_ITEM('',(#3480),#3481);
+#866=STYLED_ITEM('',(#3482),#3483);
+#867=STYLED_ITEM('',(#3484),#3485);
+#868=STYLED_ITEM('',(#3486),#3487);
+#869=STYLED_ITEM('',(#3488),#3489);
+#870=STYLED_ITEM('',(#3490),#3491);
+#871=STYLED_ITEM('',(#3492),#3493);
+#872=STYLED_ITEM('',(#3494),#3495);
+#873=STYLED_ITEM('',(#3496),#3497);
+#874=STYLED_ITEM('',(#3498),#3499);
+#875=STYLED_ITEM('',(#3500),#3501);
+#876=STYLED_ITEM('',(#3502),#3503);
+#877=STYLED_ITEM('',(#3504),#3505);
+#878=STYLED_ITEM('',(#3506),#3507);
+#879=STYLED_ITEM('',(#3508),#3509);
+#880=STYLED_ITEM('',(#3510),#3511);
+#881=STYLED_ITEM('',(#3512),#3513);
+#882=STYLED_ITEM('',(#3514),#3515);
+#883=STYLED_ITEM('',(#3516),#3517);
+#884=STYLED_ITEM('',(#3518),#3519);
+#885=STYLED_ITEM('',(#3520),#3521);
+#886=STYLED_ITEM('',(#3522),#3523);
+#887=STYLED_ITEM('',(#3524),#3525);
+#888=STYLED_ITEM('',(#3526),#3527);
+#889=STYLED_ITEM('',(#3528),#3529);
+#890=STYLED_ITEM('',(#3530),#3531);
+#891=STYLED_ITEM('',(#3532),#3533);
+#892=STYLED_ITEM('',(#3534),#3535);
+#893=STYLED_ITEM('',(#3536),#3537);
+#894=STYLED_ITEM('',(#3538),#3539);
+#895=STYLED_ITEM('',(#3540),#3541);
+#896=STYLED_ITEM('',(#3542),#3543);
+#897=STYLED_ITEM('',(#3544),#3545);
+#898=STYLED_ITEM('',(#3546),#3547);
+#899=STYLED_ITEM('',(#3548),#3549);
+#900=STYLED_ITEM('',(#3550),#3551);
+#901=STYLED_ITEM('',(#3552),#3553);
+#902=STYLED_ITEM('',(#3554),#3555);
+#903=STYLED_ITEM('',(#3556),#3557);
+#904=STYLED_ITEM('',(#3558),#3559);
+#905=STYLED_ITEM('',(#3560),#3561);
+#906=STYLED_ITEM('',(#3562),#3563);
+#907=STYLED_ITEM('',(#3564),#3565);
+#908=STYLED_ITEM('',(#3566),#3567);
+#909=STYLED_ITEM('',(#3568),#3569);
+#910=STYLED_ITEM('',(#3570),#3571);
+#911=STYLED_ITEM('',(#3572),#3573);
+#912=STYLED_ITEM('',(#3574),#3575);
+#913=STYLED_ITEM('',(#3576),#3577);
+#914=STYLED_ITEM('',(#3578),#3579);
+#915=STYLED_ITEM('',(#3580),#3581);
+#916=STYLED_ITEM('',(#3582),#3583);
+#917=STYLED_ITEM('',(#3584),#3585);
+#918=STYLED_ITEM('',(#3586),#3587);
+#919=STYLED_ITEM('',(#3588),#3589);
+#920=STYLED_ITEM('',(#3590),#3591);
+#921=STYLED_ITEM('',(#3592),#3593);
+#922=STYLED_ITEM('',(#3594),#3595);
+#923=STYLED_ITEM('',(#3596),#3597);
+#924=STYLED_ITEM('',(#3598),#3599);
+#925=STYLED_ITEM('',(#3600),#3601);
+#926=STYLED_ITEM('',(#3602),#3603);
+#927=STYLED_ITEM('',(#3604),#3605);
+#928=STYLED_ITEM('',(#3606),#3607);
+#929=STYLED_ITEM('',(#3608),#3609);
+#930=STYLED_ITEM('',(#3610),#3611);
+#931=STYLED_ITEM('',(#3612),#3613);
+#932=STYLED_ITEM('',(#3614),#3615);
+#933=STYLED_ITEM('',(#3616),#3617);
+#934=STYLED_ITEM('',(#3618),#3619);
+#935=STYLED_ITEM('',(#3620),#3621);
+#936=STYLED_ITEM('',(#3622),#3623);
+#937=STYLED_ITEM('',(#3624),#3625);
+#938=STYLED_ITEM('',(#3626),#3627);
+#939=STYLED_ITEM('',(#3628),#3629);
+#940=STYLED_ITEM('',(#3630),#3631);
+#941=STYLED_ITEM('',(#3632),#3633);
+#942=STYLED_ITEM('',(#3634),#3635);
+#943=STYLED_ITEM('',(#3636),#3637);
+#944=STYLED_ITEM('',(#3638),#3639);
+#945=STYLED_ITEM('',(#3640),#3641);
+#946=STYLED_ITEM('',(#3642),#3643);
+#947=STYLED_ITEM('',(#3644),#3645);
+#948=STYLED_ITEM('',(#3646),#3647);
+#949=STYLED_ITEM('',(#3648),#3649);
+#950=STYLED_ITEM('',(#3650),#3651);
+#951=STYLED_ITEM('',(#3652),#3653);
+#952=STYLED_ITEM('',(#3654),#3655);
+#953=STYLED_ITEM('',(#3656),#3657);
+#954=STYLED_ITEM('',(#3658),#3659);
+#955=STYLED_ITEM('',(#3660),#3661);
+#956=STYLED_ITEM('',(#3662),#3663);
+#957=STYLED_ITEM('',(#3664),#3665);
+#958=STYLED_ITEM('',(#3666),#3667);
+#959=STYLED_ITEM('',(#3668),#3669);
+#960=STYLED_ITEM('',(#3670),#3671);
+#961=STYLED_ITEM('',(#3672),#3673);
+#962=STYLED_ITEM('',(#3674),#3675);
+#963=STYLED_ITEM('',(#3676),#3677);
+#964=STYLED_ITEM('',(#3678),#3679);
+#965=STYLED_ITEM('',(#3680),#3681);
+#966=STYLED_ITEM('',(#3682),#3683);
+#967=STYLED_ITEM('',(#3684),#3685);
+#968=STYLED_ITEM('',(#3686),#3687);
+#969=STYLED_ITEM('',(#3688),#3689);
+#970=STYLED_ITEM('',(#3690),#3691);
+#971=STYLED_ITEM('',(#3692),#3693);
+#972=STYLED_ITEM('',(#3694),#3695);
+#973=STYLED_ITEM('',(#3696),#3697);
+#974=STYLED_ITEM('',(#3698),#3699);
+#975=STYLED_ITEM('',(#3700),#3701);
+#976=STYLED_ITEM('',(#3702),#3703);
+#977=STYLED_ITEM('',(#3704),#3705);
+#978=STYLED_ITEM('',(#3706),#3707);
+#979=STYLED_ITEM('',(#3708),#3709);
+#980=STYLED_ITEM('',(#3710),#3711);
+#981=STYLED_ITEM('',(#3712),#3713);
+#982=STYLED_ITEM('',(#3714),#3715);
+#983=STYLED_ITEM('',(#3716),#3717);
+#984=STYLED_ITEM('',(#3718),#3719);
+#985=STYLED_ITEM('',(#3720),#3721);
+#986=STYLED_ITEM('',(#3722),#3723);
+#987=STYLED_ITEM('',(#3724),#3725);
+#988=STYLED_ITEM('',(#3726),#3727);
+#989=STYLED_ITEM('',(#3728),#3729);
+#990=STYLED_ITEM('',(#3730),#3731);
+#991=STYLED_ITEM('',(#3732),#3733);
+#992=STYLED_ITEM('',(#3734),#3735);
+#993=STYLED_ITEM('',(#3736),#3737);
+#994=STYLED_ITEM('',(#3738),#3739);
+#995=STYLED_ITEM('',(#3740),#3741);
+#996=STYLED_ITEM('',(#3742),#3743);
+#997=STYLED_ITEM('',(#3744),#3745);
+#998=STYLED_ITEM('',(#3746),#3747);
+#999=STYLED_ITEM('',(#3748),#3749);
+#1000=STYLED_ITEM('',(#3750),#3751);
+#1001=STYLED_ITEM('',(#3752),#3753);
+#1002=STYLED_ITEM('',(#3754),#3755);
+#1003=STYLED_ITEM('',(#3756),#3757);
+#1004=STYLED_ITEM('',(#3758),#3759);
+#1005=STYLED_ITEM('',(#3760),#3761);
+#1006=STYLED_ITEM('',(#3762),#3763);
+#1007=STYLED_ITEM('',(#3764),#3765);
+#1008=STYLED_ITEM('',(#3766),#3767);
+#1009=STYLED_ITEM('',(#3768),#3769);
+#1010=STYLED_ITEM('',(#3770),#3771);
+#1011=STYLED_ITEM('',(#3772),#3773);
+#1012=STYLED_ITEM('',(#3774),#3775);
+#1013=STYLED_ITEM('',(#3776),#3777);
+#1014=STYLED_ITEM('',(#3778),#3779);
+#1015=STYLED_ITEM('',(#3780),#3781);
+#1016=STYLED_ITEM('',(#3782),#3783);
+#1017=STYLED_ITEM('',(#3784),#3785);
+#1018=STYLED_ITEM('',(#3786),#3787);
+#1019=STYLED_ITEM('',(#3788),#3789);
+#1020=STYLED_ITEM('',(#3790),#3791);
+#1021=STYLED_ITEM('',(#3792),#3793);
+#1022=STYLED_ITEM('',(#3794),#3795);
+#1023=STYLED_ITEM('',(#3796),#3797);
+#1024=STYLED_ITEM('',(#3798),#3799);
+#1025=STYLED_ITEM('',(#3800),#3801);
+#1026=STYLED_ITEM('',(#3802),#3803);
+#1027=STYLED_ITEM('',(#3804),#3805);
+#1028=STYLED_ITEM('',(#3806),#3807);
+#1029=STYLED_ITEM('',(#3808),#3809);
+#1030=STYLED_ITEM('',(#3810),#3811);
+#1031=STYLED_ITEM('',(#3812),#3813);
+#1032=STYLED_ITEM('',(#3814),#3815);
+#1033=STYLED_ITEM('',(#3816),#3817);
+#1034=STYLED_ITEM('',(#3818),#3819);
+#1035=STYLED_ITEM('',(#3820),#3821);
+#1036=STYLED_ITEM('',(#3822),#3823);
+#1037=STYLED_ITEM('',(#3824),#1903);
+#1038=STYLED_ITEM('',(#3825),#1904);
+#1039=STYLED_ITEM('',(#3826),#1905);
+#1040=STYLED_ITEM('',(#3827),#1906);
+#1041=STYLED_ITEM('',(#3828),#1907);
+#1042=STYLED_ITEM('',(#3829),#3830);
+#1043=STYLED_ITEM('',(#3831),#3832);
+#1044=STYLED_ITEM('',(#3833),#3834);
+#1045=STYLED_ITEM('',(#3835),#3836);
+#1046=STYLED_ITEM('',(#3837),#3838);
+#1047=STYLED_ITEM('',(#3839),#3840);
+#1048=STYLED_ITEM('',(#3841),#3842);
+#1049=STYLED_ITEM('',(#3843),#3844);
+#1050=STYLED_ITEM('',(#3845),#3846);
+#1051=STYLED_ITEM('',(#3847),#3848);
+#1052=STYLED_ITEM('',(#3849),#3850);
+#1053=STYLED_ITEM('',(#3851),#3852);
+#1054=STYLED_ITEM('',(#3853),#3854);
+#1055=STYLED_ITEM('',(#3855),#3856);
+#1056=STYLED_ITEM('',(#3857),#3858);
+#1057=STYLED_ITEM('',(#3859),#3860);
+#1058=STYLED_ITEM('',(#3861),#3862);
+#1059=STYLED_ITEM('',(#3863),#3864);
+#1060=STYLED_ITEM('',(#3865),#3866);
+#1061=STYLED_ITEM('',(#3867),#3868);
+#1062=STYLED_ITEM('',(#3869),#3870);
+#1063=STYLED_ITEM('',(#3871),#3872);
+#1064=STYLED_ITEM('',(#3873),#3874);
+#1065=STYLED_ITEM('',(#3875),#3876);
+#1066=STYLED_ITEM('',(#3877),#3878);
+#1067=STYLED_ITEM('',(#3879),#3880);
+#1068=STYLED_ITEM('',(#3881),#3882);
+#1069=STYLED_ITEM('',(#3883),#3884);
+#1070=STYLED_ITEM('',(#3885),#3886);
+#1071=STYLED_ITEM('',(#3887),#3888);
+#1072=STYLED_ITEM('',(#3889),#3890);
+#1073=STYLED_ITEM('',(#3891),#3892);
+#1074=STYLED_ITEM('',(#3893),#3894);
+#1075=STYLED_ITEM('',(#3895),#3896);
+#1076=STYLED_ITEM('',(#3897),#3898);
+#1077=STYLED_ITEM('',(#3899),#3900);
+#1078=STYLED_ITEM('',(#3901),#3902);
+#1079=STYLED_ITEM('',(#3903),#3904);
+#1080=STYLED_ITEM('',(#3905),#3906);
+#1081=STYLED_ITEM('',(#3907),#3908);
+#1082=STYLED_ITEM('',(#3909),#3910);
+#1083=STYLED_ITEM('',(#3911),#3912);
+#1084=STYLED_ITEM('',(#3913),#3914);
+#1085=STYLED_ITEM('',(#3915),#3916);
+#1086=STYLED_ITEM('',(#3917),#3918);
+#1087=STYLED_ITEM('',(#3919),#3920);
+#1088=STYLED_ITEM('',(#3921),#3922);
+#1089=STYLED_ITEM('',(#3923),#3924);
+#1090=STYLED_ITEM('',(#3925),#3926);
+#1091=STYLED_ITEM('',(#3927),#3928);
+#1092=STYLED_ITEM('',(#3929),#3930);
+#1093=STYLED_ITEM('',(#3931),#3932);
+#1094=STYLED_ITEM('',(#3933),#3934);
+#1095=STYLED_ITEM('',(#3935),#3936);
+#1096=STYLED_ITEM('',(#3937),#3938);
+#1097=STYLED_ITEM('',(#3939),#3940);
+#1098=STYLED_ITEM('',(#3941),#3942);
+#1099=STYLED_ITEM('',(#3943),#3944);
+#1100=STYLED_ITEM('',(#3945),#3946);
+#1101=STYLED_ITEM('',(#3947),#3948);
+#1102=STYLED_ITEM('',(#3949),#3950);
+#1103=STYLED_ITEM('',(#3951),#3952);
+#1104=STYLED_ITEM('',(#3953),#3954);
+#1105=STYLED_ITEM('',(#3955),#3956);
+#1106=STYLED_ITEM('',(#3957),#3958);
+#1107=STYLED_ITEM('',(#3959),#3960);
+#1108=STYLED_ITEM('',(#3961),#3962);
+#1109=STYLED_ITEM('',(#3963),#3964);
+#1110=STYLED_ITEM('',(#3965),#3966);
+#1111=STYLED_ITEM('',(#3967),#3968);
+#1112=STYLED_ITEM('',(#3969),#3970);
+#1113=STYLED_ITEM('',(#3971),#3972);
+#1114=STYLED_ITEM('',(#3973),#3974);
+#1115=STYLED_ITEM('',(#3975),#3976);
+#1116=STYLED_ITEM('',(#3977),#3978);
+#1117=STYLED_ITEM('',(#3979),#3980);
+#1118=STYLED_ITEM('',(#3981),#3982);
+#1119=STYLED_ITEM('',(#3983),#3984);
+#1120=STYLED_ITEM('',(#3985),#3986);
+#1121=STYLED_ITEM('',(#3987),#3988);
+#1122=STYLED_ITEM('',(#3989),#3990);
+#1123=STYLED_ITEM('',(#3991),#3992);
+#1124=STYLED_ITEM('',(#3993),#3994);
+#1125=STYLED_ITEM('',(#3995),#3996);
+#1126=STYLED_ITEM('',(#3997),#3998);
+#1127=STYLED_ITEM('',(#3999),#4000);
+#1128=STYLED_ITEM('',(#4001),#4002);
+#1129=STYLED_ITEM('',(#4003),#4004);
+#1130=STYLED_ITEM('',(#4005),#4006);
+#1131=STYLED_ITEM('',(#4007),#4008);
+#1132=STYLED_ITEM('',(#4009),#4010);
+#1133=STYLED_ITEM('',(#4011),#4012);
+#1134=STYLED_ITEM('',(#4013),#4014);
+#1135=STYLED_ITEM('',(#4015),#4016);
+#1136=STYLED_ITEM('',(#4017),#4018);
+#1137=STYLED_ITEM('',(#4019),#4020);
+#1138=STYLED_ITEM('',(#4021),#4022);
+#1139=STYLED_ITEM('',(#4023),#4024);
+#1140=STYLED_ITEM('',(#4025),#4026);
+#1141=STYLED_ITEM('',(#4027),#4028);
+#1142=STYLED_ITEM('',(#4029),#4030);
+#1143=STYLED_ITEM('',(#4031),#4032);
+#1144=STYLED_ITEM('',(#4033),#4034);
+#1145=STYLED_ITEM('',(#4035),#4036);
+#1146=STYLED_ITEM('',(#4037),#4038);
+#1147=STYLED_ITEM('',(#4039),#4040);
+#1148=STYLED_ITEM('',(#4041),#4042);
+#1149=STYLED_ITEM('',(#4043),#4044);
+#1150=STYLED_ITEM('',(#4045),#4046);
+#1151=STYLED_ITEM('',(#4047),#4048);
+#1152=STYLED_ITEM('',(#4049),#4050);
+#1153=STYLED_ITEM('',(#4051),#4052);
+#1154=STYLED_ITEM('',(#4053),#4054);
+#1155=STYLED_ITEM('',(#4055),#4056);
+#1156=STYLED_ITEM('',(#4057),#4058);
+#1157=STYLED_ITEM('',(#4059),#4060);
+#1158=STYLED_ITEM('',(#4061),#4062);
+#1159=STYLED_ITEM('',(#4063),#4064);
+#1160=STYLED_ITEM('',(#4065),#4066);
+#1161=STYLED_ITEM('',(#4067),#4068);
+#1162=STYLED_ITEM('',(#4069),#4070);
+#1163=STYLED_ITEM('',(#4071),#4072);
+#1164=STYLED_ITEM('',(#4073),#4074);
+#1165=STYLED_ITEM('',(#4075),#4076);
+#1166=STYLED_ITEM('',(#4077),#4078);
+#1167=STYLED_ITEM('',(#4079),#4080);
+#1168=STYLED_ITEM('',(#4081),#4082);
+#1169=STYLED_ITEM('',(#4083),#4084);
+#1170=STYLED_ITEM('',(#4085),#4086);
+#1171=STYLED_ITEM('',(#4087),#4088);
+#1172=STYLED_ITEM('',(#4089),#4090);
+#1173=STYLED_ITEM('',(#4091),#4092);
+#1174=STYLED_ITEM('',(#4093),#4094);
+#1175=STYLED_ITEM('',(#4095),#4096);
+#1176=STYLED_ITEM('',(#4097),#4098);
+#1177=STYLED_ITEM('',(#4099),#4100);
+#1178=STYLED_ITEM('',(#4101),#4102);
+#1179=STYLED_ITEM('',(#4103),#4104);
+#1180=STYLED_ITEM('',(#4105),#4106);
+#1181=STYLED_ITEM('',(#4107),#4108);
+#1182=STYLED_ITEM('',(#4109),#4110);
+#1183=STYLED_ITEM('',(#4111),#4112);
+#1184=STYLED_ITEM('',(#4113),#4114);
+#1185=STYLED_ITEM('',(#4115),#4116);
+#1186=STYLED_ITEM('',(#4117),#4118);
+#1187=STYLED_ITEM('',(#4119),#4120);
+#1188=STYLED_ITEM('',(#4121),#4122);
+#1189=STYLED_ITEM('',(#4123),#4124);
+#1190=STYLED_ITEM('',(#4125),#4126);
+#1191=STYLED_ITEM('',(#4127),#4128);
+#1192=STYLED_ITEM('',(#4129),#4130);
+#1193=STYLED_ITEM('',(#4131),#4132);
+#1194=STYLED_ITEM('',(#4133),#4134);
+#1195=STYLED_ITEM('',(#4135),#4136);
+#1196=STYLED_ITEM('',(#4137),#4138);
+#1197=STYLED_ITEM('',(#4139),#4140);
+#1198=STYLED_ITEM('',(#4141),#4142);
+#1199=STYLED_ITEM('',(#4143),#4144);
+#1200=STYLED_ITEM('',(#4145),#4146);
+#1201=STYLED_ITEM('',(#4147),#4148);
+#1202=STYLED_ITEM('',(#4149),#4150);
+#1203=STYLED_ITEM('',(#4151),#4152);
+#1204=STYLED_ITEM('',(#4153),#4154);
+#1205=STYLED_ITEM('',(#4155),#4156);
+#1206=STYLED_ITEM('',(#4157),#4158);
+#1207=STYLED_ITEM('',(#4159),#4160);
+#1208=STYLED_ITEM('',(#4161),#4162);
+#1209=STYLED_ITEM('',(#4163),#4164);
+#1210=STYLED_ITEM('',(#4165),#4166);
+#1211=STYLED_ITEM('',(#4167),#4168);
+#1212=STYLED_ITEM('',(#4169),#4170);
+#1213=STYLED_ITEM('',(#4171),#4172);
+#1214=STYLED_ITEM('',(#4173),#4174);
+#1215=STYLED_ITEM('',(#4175),#4176);
+#1216=STYLED_ITEM('',(#4177),#4178);
+#1217=STYLED_ITEM('',(#4179),#4180);
+#1218=STYLED_ITEM('',(#4181),#4182);
+#1219=STYLED_ITEM('',(#4183),#4184);
+#1220=STYLED_ITEM('',(#4185),#4186);
+#1221=STYLED_ITEM('',(#4187),#4188);
+#1222=STYLED_ITEM('',(#4189),#4190);
+#1223=STYLED_ITEM('',(#4191),#4192);
+#1224=STYLED_ITEM('',(#4193),#4194);
+#1225=STYLED_ITEM('',(#4195),#4196);
+#1226=STYLED_ITEM('',(#4197),#4198);
+#1227=STYLED_ITEM('',(#4199),#4200);
+#1228=STYLED_ITEM('',(#4201),#4202);
+#1229=STYLED_ITEM('',(#4203),#4204);
+#1230=STYLED_ITEM('',(#4205),#4206);
+#1231=STYLED_ITEM('',(#4207),#4208);
+#1232=STYLED_ITEM('',(#4209),#4210);
+#1233=STYLED_ITEM('',(#4211),#4212);
+#1234=STYLED_ITEM('',(#4213),#4214);
+#1235=STYLED_ITEM('',(#4215),#4216);
+#1236=STYLED_ITEM('',(#4217),#4218);
+#1237=STYLED_ITEM('',(#4219),#4220);
+#1238=STYLED_ITEM('',(#4221),#4222);
+#1239=STYLED_ITEM('',(#4223),#4224);
+#1240=STYLED_ITEM('',(#4225),#4226);
+#1241=STYLED_ITEM('',(#4227),#4228);
+#1242=STYLED_ITEM('',(#4229),#4230);
+#1243=STYLED_ITEM('',(#4231),#4232);
+#1244=STYLED_ITEM('',(#4233),#4234);
+#1245=STYLED_ITEM('',(#4235),#4236);
+#1246=STYLED_ITEM('',(#4237),#4238);
+#1247=STYLED_ITEM('',(#4239),#4240);
+#1248=STYLED_ITEM('',(#4241),#4242);
+#1249=STYLED_ITEM('',(#4243),#4244);
+#1250=STYLED_ITEM('',(#4245),#4246);
+#1251=STYLED_ITEM('',(#4247),#4248);
+#1252=STYLED_ITEM('',(#4249),#4250);
+#1253=STYLED_ITEM('',(#4251),#4252);
+#1254=STYLED_ITEM('',(#4253),#4254);
+#1255=STYLED_ITEM('',(#4255),#1915);
+#1256=STYLED_ITEM('',(#4256),#4257);
+#1257=STYLED_ITEM('',(#4258),#4259);
+#1258=STYLED_ITEM('',(#4260),#4261);
+#1259=STYLED_ITEM('',(#4262),#4263);
+#1260=STYLED_ITEM('',(#4264),#4265);
+#1261=STYLED_ITEM('',(#4266),#4267);
+#1262=STYLED_ITEM('',(#4268),#4269);
+#1263=STYLED_ITEM('',(#4270),#4271);
+#1264=STYLED_ITEM('',(#4272),#4273);
+#1265=STYLED_ITEM('',(#4274),#4275);
+#1266=STYLED_ITEM('',(#4276),#4277);
+#1267=STYLED_ITEM('',(#4278),#4279);
+#1268=STYLED_ITEM('',(#4280),#4281);
+#1269=STYLED_ITEM('',(#4282),#4283);
+#1270=STYLED_ITEM('',(#4284),#4285);
+#1271=STYLED_ITEM('',(#4286),#4287);
+#1272=STYLED_ITEM('',(#4288),#4289);
+#1273=STYLED_ITEM('',(#4290),#4291);
+#1274=STYLED_ITEM('',(#4292),#4293);
+#1275=STYLED_ITEM('',(#4294),#4295);
+#1276=STYLED_ITEM('',(#4296),#4297);
+#1277=STYLED_ITEM('',(#4298),#4299);
+#1278=STYLED_ITEM('',(#4300),#4301);
+#1279=STYLED_ITEM('',(#4302),#4303);
+#1280=STYLED_ITEM('',(#4304),#4305);
+#1281=STYLED_ITEM('',(#4306),#4307);
+#1282=STYLED_ITEM('',(#4308),#4309);
+#1283=STYLED_ITEM('',(#4310),#4311);
+#1284=STYLED_ITEM('',(#4312),#4313);
+#1285=STYLED_ITEM('',(#4314),#4315);
+#1286=STYLED_ITEM('',(#4316),#4317);
+#1287=STYLED_ITEM('',(#4318),#4319);
+#1288=STYLED_ITEM('',(#4320),#4321);
+#1289=STYLED_ITEM('',(#4322),#4323);
+#1290=STYLED_ITEM('',(#4324),#4325);
+#1291=STYLED_ITEM('',(#4326),#4327);
+#1292=STYLED_ITEM('',(#4328),#4329);
+#1293=STYLED_ITEM('',(#4330),#4331);
+#1294=STYLED_ITEM('',(#4332),#4333);
+#1295=STYLED_ITEM('',(#4334),#4335);
+#1296=STYLED_ITEM('',(#4336),#4337);
+#1297=STYLED_ITEM('',(#4338),#4339);
+#1298=STYLED_ITEM('',(#4340),#4341);
+#1299=STYLED_ITEM('',(#4342),#4343);
+#1300=STYLED_ITEM('',(#4344),#4345);
+#1301=STYLED_ITEM('',(#4346),#4347);
+#1302=STYLED_ITEM('',(#4348),#4349);
+#1303=STYLED_ITEM('',(#4350),#4351);
+#1304=STYLED_ITEM('',(#4352),#4353);
+#1305=STYLED_ITEM('',(#4354),#4355);
+#1306=STYLED_ITEM('',(#4356),#4357);
+#1307=STYLED_ITEM('',(#4358),#4359);
+#1308=STYLED_ITEM('',(#4360),#4361);
+#1309=STYLED_ITEM('',(#4362),#4363);
+#1310=STYLED_ITEM('',(#4364),#4365);
+#1311=STYLED_ITEM('',(#4366),#4367);
+#1312=STYLED_ITEM('',(#4368),#4369);
+#1313=STYLED_ITEM('',(#4370),#4371);
+#1314=STYLED_ITEM('',(#4372),#4373);
+#1315=STYLED_ITEM('',(#4374),#4375);
+#1316=STYLED_ITEM('',(#4376),#4377);
+#1317=STYLED_ITEM('',(#4378),#4379);
+#1318=STYLED_ITEM('',(#4380),#4381);
+#1319=STYLED_ITEM('',(#4382),#4383);
+#1320=STYLED_ITEM('',(#4384),#4385);
+#1321=STYLED_ITEM('',(#4386),#4387);
+#1322=STYLED_ITEM('',(#4388),#4389);
+#1323=STYLED_ITEM('',(#4390),#4391);
+#1324=STYLED_ITEM('',(#4392),#4393);
+#1325=STYLED_ITEM('',(#4394),#4395);
+#1326=STYLED_ITEM('',(#4396),#4397);
+#1327=STYLED_ITEM('',(#4398),#4399);
+#1328=STYLED_ITEM('',(#4400),#4401);
+#1329=STYLED_ITEM('',(#4402),#4403);
+#1330=STYLED_ITEM('',(#4404),#4405);
+#1331=STYLED_ITEM('',(#4406),#4407);
+#1332=STYLED_ITEM('',(#4408),#4409);
+#1333=STYLED_ITEM('',(#4410),#4411);
+#1334=STYLED_ITEM('',(#4412),#4413);
+#1335=STYLED_ITEM('',(#4414),#4415);
+#1336=STYLED_ITEM('',(#4416),#4417);
+#1337=STYLED_ITEM('',(#4418),#4419);
+#1338=STYLED_ITEM('',(#4420),#4421);
+#1339=STYLED_ITEM('',(#4422),#4423);
+#1340=STYLED_ITEM('',(#4424),#4425);
+#1341=STYLED_ITEM('',(#4426),#4427);
+#1342=STYLED_ITEM('',(#4428),#4429);
+#1343=STYLED_ITEM('',(#4430),#4431);
+#1344=STYLED_ITEM('',(#4432),#4433);
+#1345=STYLED_ITEM('',(#4434),#4435);
+#1346=STYLED_ITEM('',(#4436),#4437);
+#1347=STYLED_ITEM('',(#4438),#4439);
+#1348=STYLED_ITEM('',(#4440),#4441);
+#1349=STYLED_ITEM('',(#4442),#4443);
+#1350=STYLED_ITEM('',(#4444),#4445);
+#1351=STYLED_ITEM('',(#4446),#4447);
+#1352=STYLED_ITEM('',(#4448),#4449);
+#1353=STYLED_ITEM('',(#4450),#4451);
+#1354=STYLED_ITEM('',(#4452),#4453);
+#1355=STYLED_ITEM('',(#4454),#4455);
+#1356=STYLED_ITEM('',(#4456),#4457);
+#1357=STYLED_ITEM('',(#4458),#4459);
+#1358=STYLED_ITEM('',(#4460),#4461);
+#1359=STYLED_ITEM('',(#4462),#4463);
+#1360=STYLED_ITEM('',(#4464),#4465);
+#1361=STYLED_ITEM('',(#4466),#4467);
+#1362=STYLED_ITEM('',(#4468),#4469);
+#1363=STYLED_ITEM('',(#4470),#4471);
+#1364=STYLED_ITEM('',(#4472),#4473);
+#1365=STYLED_ITEM('',(#4474),#4475);
+#1366=STYLED_ITEM('',(#4476),#4477);
+#1367=STYLED_ITEM('',(#4478),#4479);
+#1368=STYLED_ITEM('',(#4480),#4481);
+#1369=STYLED_ITEM('',(#4482),#4483);
+#1370=STYLED_ITEM('',(#4484),#4485);
+#1371=STYLED_ITEM('',(#4486),#4487);
+#1372=STYLED_ITEM('',(#4488),#4489);
+#1373=STYLED_ITEM('',(#4490),#4491);
+#1374=STYLED_ITEM('',(#4492),#4493);
+#1375=STYLED_ITEM('',(#4494),#4495);
+#1376=STYLED_ITEM('',(#4496),#4497);
+#1377=STYLED_ITEM('',(#4498),#4499);
+#1378=STYLED_ITEM('',(#4500),#4501);
+#1379=STYLED_ITEM('',(#4502),#4503);
+#1380=STYLED_ITEM('',(#4504),#4505);
+#1381=STYLED_ITEM('',(#4506),#4507);
+#1382=STYLED_ITEM('',(#4508),#4509);
+#1383=STYLED_ITEM('',(#4510),#4511);
+#1384=STYLED_ITEM('',(#4512),#4513);
+#1385=STYLED_ITEM('',(#4514),#4515);
+#1386=STYLED_ITEM('',(#4516),#4517);
+#1387=STYLED_ITEM('',(#4518),#4519);
+#1388=STYLED_ITEM('',(#4520),#4521);
+#1389=STYLED_ITEM('',(#4522),#4523);
+#1390=STYLED_ITEM('',(#4524),#4525);
+#1391=STYLED_ITEM('',(#4526),#4527);
+#1392=STYLED_ITEM('',(#4528),#4529);
+#1393=STYLED_ITEM('',(#4530),#4531);
+#1394=STYLED_ITEM('',(#4532),#4533);
+#1395=STYLED_ITEM('',(#4534),#4535);
+#1396=STYLED_ITEM('',(#4536),#4537);
+#1397=STYLED_ITEM('',(#4538),#4539);
+#1398=STYLED_ITEM('',(#4540),#4541);
+#1399=STYLED_ITEM('',(#4542),#4543);
+#1400=STYLED_ITEM('',(#4544),#4545);
+#1401=STYLED_ITEM('',(#4546),#4547);
+#1402=STYLED_ITEM('',(#4548),#4549);
+#1403=STYLED_ITEM('',(#4550),#4551);
+#1404=STYLED_ITEM('',(#4552),#4553);
+#1405=STYLED_ITEM('',(#4554),#4555);
+#1406=STYLED_ITEM('',(#4556),#4557);
+#1407=STYLED_ITEM('',(#4558),#4559);
+#1408=STYLED_ITEM('',(#4560),#4561);
+#1409=STYLED_ITEM('',(#4562),#4563);
+#1410=STYLED_ITEM('',(#4564),#4565);
+#1411=STYLED_ITEM('',(#4566),#4567);
+#1412=STYLED_ITEM('',(#4568),#4569);
+#1413=STYLED_ITEM('',(#4570),#4571);
+#1414=STYLED_ITEM('',(#4572),#4573);
+#1415=STYLED_ITEM('',(#4574),#4575);
+#1416=STYLED_ITEM('',(#4576),#4577);
+#1417=STYLED_ITEM('',(#4578),#4579);
+#1418=STYLED_ITEM('',(#4580),#4581);
+#1419=STYLED_ITEM('',(#4582),#4583);
+#1420=STYLED_ITEM('',(#4584),#4585);
+#1421=STYLED_ITEM('',(#4586),#4587);
+#1422=STYLED_ITEM('',(#4588),#4589);
+#1423=STYLED_ITEM('',(#4590),#4591);
+#1424=STYLED_ITEM('',(#4592),#4593);
+#1425=STYLED_ITEM('',(#4594),#4595);
+#1426=STYLED_ITEM('',(#4596),#4597);
+#1427=STYLED_ITEM('',(#4598),#4599);
+#1428=STYLED_ITEM('',(#4600),#4601);
+#1429=STYLED_ITEM('',(#4602),#4603);
+#1430=STYLED_ITEM('',(#4604),#4605);
+#1431=STYLED_ITEM('',(#4606),#4607);
+#1432=STYLED_ITEM('',(#4608),#4609);
+#1433=STYLED_ITEM('',(#4610),#4611);
+#1434=STYLED_ITEM('',(#4612),#4613);
+#1435=STYLED_ITEM('',(#4614),#4615);
+#1436=STYLED_ITEM('',(#4616),#4617);
+#1437=STYLED_ITEM('',(#4618),#4619);
+#1438=STYLED_ITEM('',(#4620),#4621);
+#1439=STYLED_ITEM('',(#4622),#4623);
+#1440=STYLED_ITEM('',(#4624),#4625);
+#1441=STYLED_ITEM('',(#4626),#4627);
+#1442=STYLED_ITEM('',(#4628),#4629);
+#1443=STYLED_ITEM('',(#4630),#4631);
+#1444=STYLED_ITEM('',(#4632),#4633);
+#1445=STYLED_ITEM('',(#4634),#4635);
+#1446=STYLED_ITEM('',(#4636),#4637);
+#1447=STYLED_ITEM('',(#4638),#4639);
+#1448=STYLED_ITEM('',(#4640),#4641);
+#1449=STYLED_ITEM('',(#4642),#4643);
+#1450=STYLED_ITEM('',(#4644),#4645);
+#1451=STYLED_ITEM('',(#4646),#4647);
+#1452=STYLED_ITEM('',(#4648),#4649);
+#1453=STYLED_ITEM('',(#4650),#4651);
+#1454=STYLED_ITEM('',(#4652),#4653);
+#1455=STYLED_ITEM('',(#4654),#4655);
+#1456=STYLED_ITEM('',(#4656),#4657);
+#1457=STYLED_ITEM('',(#4658),#4659);
+#1458=STYLED_ITEM('',(#4660),#4661);
+#1459=STYLED_ITEM('',(#4662),#4663);
+#1460=STYLED_ITEM('',(#4664),#4665);
+#1461=STYLED_ITEM('',(#4666),#4667);
+#1462=STYLED_ITEM('',(#4668),#4669);
+#1463=STYLED_ITEM('',(#4670),#4671);
+#1464=STYLED_ITEM('',(#4672),#4673);
+#1465=STYLED_ITEM('',(#4674),#4675);
+#1466=STYLED_ITEM('',(#4676),#4677);
+#1467=STYLED_ITEM('',(#4678),#4679);
+#1468=STYLED_ITEM('',(#4680),#4681);
+#1469=STYLED_ITEM('',(#4682),#4683);
+#1470=STYLED_ITEM('',(#4684),#4685);
+#1471=STYLED_ITEM('',(#4686),#4687);
+#1472=STYLED_ITEM('',(#4688),#4689);
+#1473=STYLED_ITEM('',(#4690),#4691);
+#1474=STYLED_ITEM('',(#4692),#4693);
+#1475=STYLED_ITEM('',(#4694),#4695);
+#1476=STYLED_ITEM('',(#4696),#4697);
+#1477=STYLED_ITEM('',(#4698),#4699);
+#1478=STYLED_ITEM('',(#4700),#4701);
+#1479=STYLED_ITEM('',(#4702),#4703);
+#1480=STYLED_ITEM('',(#4704),#4705);
+#1481=STYLED_ITEM('',(#4706),#4707);
+#1482=STYLED_ITEM('',(#4708),#4709);
+#1483=STYLED_ITEM('',(#4710),#4711);
+#1484=STYLED_ITEM('',(#4712),#4713);
+#1485=STYLED_ITEM('',(#4714),#4715);
+#1486=STYLED_ITEM('',(#4716),#4717);
+#1487=STYLED_ITEM('',(#4718),#4719);
+#1488=STYLED_ITEM('',(#4720),#4721);
+#1489=STYLED_ITEM('',(#4722),#4723);
+#1490=STYLED_ITEM('',(#4724),#4725);
+#1491=STYLED_ITEM('',(#4726),#4727);
+#1492=STYLED_ITEM('',(#4728),#4729);
+#1493=STYLED_ITEM('',(#4730),#4731);
+#1494=STYLED_ITEM('',(#4732),#4733);
+#1495=STYLED_ITEM('',(#4734),#4735);
+#1496=STYLED_ITEM('',(#4736),#4737);
+#1497=STYLED_ITEM('',(#4738),#4739);
+#1498=STYLED_ITEM('',(#4740),#4741);
+#1499=STYLED_ITEM('',(#4742),#4743);
+#1500=STYLED_ITEM('',(#4744),#4745);
+#1501=STYLED_ITEM('',(#4746),#4747);
+#1502=STYLED_ITEM('',(#4748),#4749);
+#1503=STYLED_ITEM('',(#4750),#4751);
+#1504=STYLED_ITEM('',(#4752),#4753);
+#1505=STYLED_ITEM('',(#4754),#4755);
+#1506=STYLED_ITEM('',(#4756),#4757);
+#1507=STYLED_ITEM('',(#4758),#4759);
+#1508=STYLED_ITEM('',(#4760),#4761);
+#1509=STYLED_ITEM('',(#4762),#4763);
+#1510=STYLED_ITEM('',(#4764),#4765);
+#1511=STYLED_ITEM('',(#4766),#4767);
+#1512=STYLED_ITEM('',(#4768),#4769);
+#1513=STYLED_ITEM('',(#4770),#4771);
+#1514=STYLED_ITEM('',(#4772),#4773);
+#1515=STYLED_ITEM('',(#4774),#4775);
+#1516=STYLED_ITEM('',(#4776),#4777);
+#1517=STYLED_ITEM('',(#4778),#4779);
+#1518=STYLED_ITEM('',(#4780),#4781);
+#1519=STYLED_ITEM('',(#4782),#4783);
+#1520=STYLED_ITEM('',(#4784),#4785);
+#1521=STYLED_ITEM('',(#4786),#4787);
+#1522=STYLED_ITEM('',(#4788),#4789);
+#1523=STYLED_ITEM('',(#4790),#4791);
+#1524=STYLED_ITEM('',(#4792),#4793);
+#1525=STYLED_ITEM('',(#4794),#4795);
+#1526=STYLED_ITEM('',(#4796),#4797);
+#1527=STYLED_ITEM('',(#4798),#4799);
+#1528=STYLED_ITEM('',(#4800),#4801);
+#1529=STYLED_ITEM('',(#4802),#4803);
+#1530=STYLED_ITEM('',(#4804),#4805);
+#1531=STYLED_ITEM('',(#4806),#4807);
+#1532=STYLED_ITEM('',(#4808),#4809);
+#1533=STYLED_ITEM('',(#4810),#4811);
+#1534=STYLED_ITEM('',(#4812),#4813);
+#1535=STYLED_ITEM('',(#4814),#4815);
+#1536=STYLED_ITEM('',(#4816),#4817);
+#1537=STYLED_ITEM('',(#4818),#4819);
+#1538=STYLED_ITEM('',(#4820),#4821);
+#1539=STYLED_ITEM('',(#4822),#4823);
+#1540=STYLED_ITEM('',(#4824),#4825);
+#1541=STYLED_ITEM('',(#4826),#4827);
+#1542=STYLED_ITEM('',(#4828),#4829);
+#1543=STYLED_ITEM('',(#4830),#4831);
+#1544=STYLED_ITEM('',(#4832),#4833);
+#1545=STYLED_ITEM('',(#4834),#4835);
+#1546=STYLED_ITEM('',(#4836),#4837);
+#1547=STYLED_ITEM('',(#4838),#4839);
+#1548=STYLED_ITEM('',(#4840),#4841);
+#1549=STYLED_ITEM('',(#4842),#4843);
+#1550=STYLED_ITEM('',(#4844),#4845);
+#1551=STYLED_ITEM('',(#4846),#4847);
+#1552=STYLED_ITEM('',(#4848),#4849);
+#1553=STYLED_ITEM('',(#4850),#4851);
+#1554=STYLED_ITEM('',(#4852),#4853);
+#1555=STYLED_ITEM('',(#4854),#4855);
+#1556=STYLED_ITEM('',(#4856),#4857);
+#1557=STYLED_ITEM('',(#4858),#4859);
+#1558=STYLED_ITEM('',(#4860),#4861);
+#1559=STYLED_ITEM('',(#4862),#4863);
+#1560=STYLED_ITEM('',(#4864),#4865);
+#1561=STYLED_ITEM('',(#4866),#4867);
+#1562=STYLED_ITEM('',(#4868),#4869);
+#1563=STYLED_ITEM('',(#4870),#4871);
+#1564=STYLED_ITEM('',(#4872),#4873);
+#1565=STYLED_ITEM('',(#4874),#4875);
+#1566=STYLED_ITEM('',(#4876),#4877);
+#1567=STYLED_ITEM('',(#4878),#4879);
+#1568=STYLED_ITEM('',(#4880),#4881);
+#1569=STYLED_ITEM('',(#4882),#4883);
+#1570=STYLED_ITEM('',(#4884),#4885);
+#1571=STYLED_ITEM('',(#4886),#4887);
+#1572=STYLED_ITEM('',(#4888),#4889);
+#1573=STYLED_ITEM('',(#4890),#4891);
+#1574=STYLED_ITEM('',(#4892),#4893);
+#1575=STYLED_ITEM('',(#4894),#4895);
+#1576=STYLED_ITEM('',(#4896),#4897);
+#1577=STYLED_ITEM('',(#4898),#4899);
+#1578=STYLED_ITEM('',(#4900),#4901);
+#1579=STYLED_ITEM('',(#4902),#4903);
+#1580=STYLED_ITEM('',(#4904),#4905);
+#1581=STYLED_ITEM('',(#4906),#4907);
+#1582=STYLED_ITEM('',(#4908),#4909);
+#1583=STYLED_ITEM('',(#4910),#4911);
+#1584=STYLED_ITEM('',(#4912),#4913);
+#1585=STYLED_ITEM('',(#4914),#4915);
+#1586=STYLED_ITEM('',(#4916),#4917);
+#1587=STYLED_ITEM('',(#4918),#4919);
+#1588=STYLED_ITEM('',(#4920),#4921);
+#1589=STYLED_ITEM('',(#4922),#4923);
+#1590=STYLED_ITEM('',(#4924),#4925);
+#1591=STYLED_ITEM('',(#4926),#4927);
+#1592=STYLED_ITEM('',(#4928),#4929);
+#1593=STYLED_ITEM('',(#4930),#4931);
+#1594=STYLED_ITEM('',(#4932),#4933);
+#1595=STYLED_ITEM('',(#4934),#4935);
+#1596=STYLED_ITEM('',(#4936),#4937);
+#1597=STYLED_ITEM('',(#4938),#4939);
+#1598=STYLED_ITEM('',(#4940),#4941);
+#1599=STYLED_ITEM('',(#4942),#4943);
+#1600=STYLED_ITEM('',(#4944),#4945);
+#1601=STYLED_ITEM('',(#4946),#4947);
+#1602=STYLED_ITEM('',(#4948),#4949);
+#1603=STYLED_ITEM('',(#4950),#4951);
+#1604=STYLED_ITEM('',(#4952),#4953);
+#1605=STYLED_ITEM('',(#4954),#4955);
+#1606=STYLED_ITEM('',(#4956),#4957);
+#1607=STYLED_ITEM('',(#4958),#4959);
+#1608=STYLED_ITEM('',(#4960),#4961);
+#1609=STYLED_ITEM('',(#4962),#4963);
+#1610=STYLED_ITEM('',(#4964),#4965);
+#1611=STYLED_ITEM('',(#4966),#4967);
+#1612=STYLED_ITEM('',(#4968),#4969);
+#1613=STYLED_ITEM('',(#4970),#4971);
+#1614=STYLED_ITEM('',(#4972),#4973);
+#1615=STYLED_ITEM('',(#4974),#4975);
+#1616=STYLED_ITEM('',(#4976),#4977);
+#1617=STYLED_ITEM('',(#4978),#4979);
+#1618=STYLED_ITEM('',(#4980),#4981);
+#1619=STYLED_ITEM('',(#4982),#4983);
+#1620=STYLED_ITEM('',(#4984),#4985);
+#1621=STYLED_ITEM('',(#4986),#4987);
+#1622=STYLED_ITEM('',(#4988),#4989);
+#1623=STYLED_ITEM('',(#4990),#4991);
+#1624=STYLED_ITEM('',(#4992),#4993);
+#1625=STYLED_ITEM('',(#4994),#4995);
+#1626=STYLED_ITEM('',(#4996),#4997);
+#1627=STYLED_ITEM('',(#4998),#4999);
+#1628=STYLED_ITEM('',(#5000),#5001);
+#1629=STYLED_ITEM('',(#5002),#5003);
+#1630=STYLED_ITEM('',(#5004),#5005);
+#1631=STYLED_ITEM('',(#5006),#5007);
+#1632=STYLED_ITEM('',(#5008),#5009);
+#1633=STYLED_ITEM('',(#5010),#5011);
+#1634=STYLED_ITEM('',(#5012),#5013);
+#1635=STYLED_ITEM('',(#5014),#5015);
+#1636=STYLED_ITEM('',(#5016),#5017);
+#1637=STYLED_ITEM('',(#5018),#5019);
+#1638=STYLED_ITEM('',(#5020),#5021);
+#1639=STYLED_ITEM('',(#5022),#5023);
+#1640=STYLED_ITEM('',(#5024),#5025);
+#1641=STYLED_ITEM('',(#5026),#5027);
+#1642=STYLED_ITEM('',(#5028),#5029);
+#1643=STYLED_ITEM('',(#5030),#5031);
+#1644=STYLED_ITEM('',(#5032),#5033);
+#1645=STYLED_ITEM('',(#5034),#5035);
+#1646=STYLED_ITEM('',(#5036),#5037);
+#1647=STYLED_ITEM('',(#5038),#5039);
+#1648=STYLED_ITEM('',(#5040),#5041);
+#1649=STYLED_ITEM('',(#5042),#5043);
+#1650=STYLED_ITEM('',(#5044),#5045);
+#1651=STYLED_ITEM('',(#5046),#5047);
+#1652=STYLED_ITEM('',(#5048),#5049);
+#1653=STYLED_ITEM('',(#5050),#5051);
+#1654=STYLED_ITEM('',(#5052),#5053);
+#1655=STYLED_ITEM('',(#5054),#5055);
+#1656=STYLED_ITEM('',(#5056),#5057);
+#1657=STYLED_ITEM('',(#5058),#5059);
+#1658=STYLED_ITEM('',(#5060),#5061);
+#1659=STYLED_ITEM('',(#5062),#5063);
+#1660=STYLED_ITEM('',(#5064),#5065);
+#1661=STYLED_ITEM('',(#5066),#5067);
+#1662=STYLED_ITEM('',(#5068),#5069);
+#1663=STYLED_ITEM('',(#5070),#5071);
+#1664=STYLED_ITEM('',(#5072),#5073);
+#1665=STYLED_ITEM('',(#5074),#5075);
+#1666=STYLED_ITEM('',(#5076),#5077);
+#1667=STYLED_ITEM('',(#5078),#5079);
+#1668=STYLED_ITEM('',(#5080),#5081);
+#1669=STYLED_ITEM('',(#5082),#5083);
+#1670=STYLED_ITEM('',(#5084),#5085);
+#1671=STYLED_ITEM('',(#5086),#5087);
+#1672=STYLED_ITEM('',(#5088),#5089);
+#1673=STYLED_ITEM('',(#5090),#5091);
+#1674=STYLED_ITEM('',(#5092),#5093);
+#1675=STYLED_ITEM('',(#5094),#5095);
+#1676=STYLED_ITEM('',(#5096),#5097);
+#1677=STYLED_ITEM('',(#5098),#5099);
+#1678=STYLED_ITEM('',(#5100),#5101);
+#1679=STYLED_ITEM('',(#5102),#5103);
+#1680=STYLED_ITEM('',(#5104),#5105);
+#1681=STYLED_ITEM('',(#5106),#5107);
+#1682=STYLED_ITEM('',(#5108),#5109);
+#1683=STYLED_ITEM('',(#5110),#5111);
+#1684=STYLED_ITEM('',(#5112),#5113);
+#1685=STYLED_ITEM('',(#5114),#5115);
+#1686=STYLED_ITEM('',(#5116),#5117);
+#1687=STYLED_ITEM('',(#5118),#5119);
+#1688=STYLED_ITEM('',(#5120),#5121);
+#1689=STYLED_ITEM('',(#5122),#5123);
+#1690=STYLED_ITEM('',(#5124),#5125);
+#1691=STYLED_ITEM('',(#5126),#5127);
+#1692=STYLED_ITEM('',(#5128),#5129);
+#1693=STYLED_ITEM('',(#5130),#5131);
+#1694=STYLED_ITEM('',(#5132),#5133);
+#1695=STYLED_ITEM('',(#5134),#5135);
+#1696=STYLED_ITEM('',(#5136),#5137);
+#1697=STYLED_ITEM('',(#5138),#5139);
+#1698=STYLED_ITEM('',(#5140),#5141);
+#1699=STYLED_ITEM('',(#5142),#5143);
+#1700=STYLED_ITEM('',(#5144),#5145);
+#1701=STYLED_ITEM('',(#5146),#5147);
+#1702=STYLED_ITEM('',(#5148),#5149);
+#1703=STYLED_ITEM('',(#5150),#5151);
+#1704=STYLED_ITEM('',(#5152),#5153);
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+DATA;
+#1=MECHANICAL_DESIGN_GEOMETRIC_PRESENTATION_REPRESENTATION(' ',(#13,#14,#15,#16,#17,#18,#19,#20,#21,#22,#23,#24,#25,#26,#27,#28,#29,#30,#31,#32,#33,#34,#35,#36,#37,#38,#39,#40,#41,#42,#43,#44,#45,#46,#47,#48,#49,#50,#51,#52,#53,#54,#55,#56,#57,#58,#59,#60,#61,#62,#63,#64,#65,#66,#67,#68,#69,#70,#71,#72,#73,#74,#75,#76,#77,#78,#79,#80,#81,#82,#83,#84,#85,#86,#87,#88,#89,#90,#91,#92,#93,#94,#95,#96,#97,#98,#99,#100,#101,#102,#103,#104,#105,#106,#107,#108,#109,#110,#111,#112,#113,#114,#115,#116,#117,#118,#119,#120,#121,#122,#123,#124,#125,#126,#127,#128,#129,#130,#131,#132,#133,#134,#135,#136,#137,#138,#139,#140,#141,#142,#143,#144,#145,#146,#147,#148,#149,#150,#151,#152,#153,#154,#155,#156,#157,#158,#159,#160,#161,#162,#163,#164,#165,#166,#167,#168,#169,#170,#171,#172,#173,#174,#175,#176,#177,#178,#179,#180,#181,#182,#183,#184,#185,#186,#187,#188,#189,#190,#191,#192,#193,#194,#195,#196,#197,#198,#199,#200,#201,#202,#203,#204,#205,#206,#207,#208,#209,#210,#211,#212,#213,#214,#215,#216,#217,#218,#219,#220,#221,#222,#223,#224,#225,#226,#227,#228,#229,#230,#231,#232,#233,#234,#235,#236,#237,#238,#239,#240,#241,#242,#243,#244,#245,#246,#247,#248,#249,#250,#251,#252,#253,#254,#255,#256,#257,#258,#259,#260,#261,#262,#263,#264,#265,#266,#267,#268,#269,#270,#271,#272,#273,#274,#275,#276,#277,#278,#279,#280,#281,#282,#283,#284,#285,#286,#287,#288,#289,#290,#291,#292,#293,#294,#295,#296,#297,#298,#299,#300,#301,#302,#303,#304,#305,#306,#307,#308,#309,#310,#311,#312,#313,#314,#315,#316,#317,#318,#319,#320,#321,#322,#323,#324,#325,#326,#327,#328,#329,#330,#331,#332,#333,#334,#335,#336,#337,#338,#339,#340,#341,#342,#343,#344,#345,#346,#347,#348,#349,#350,#351,#352,#353,#354,#355,#356,#357,#358,#359,#360,#361,#362,#363,#364,#365,#366,#367,#368,#369,#370,#371,#372,#373,#374,#375,#376,#377,#378,#379,#380,#381,#382,#383,#384,#385,#386,#387,#388,#389,#390,#391,#392,#393,#394,#395,#396,#397,#398,#399,#400,#401,#402,#403,#404,#405,#406,#407,#408,#409,#410,#411,#412,#413,#414,#415,#416,#417,#418,#419,#420,#421,#422,#423,#424,#425,#426,#427,#428,#429,#430,#431,#432,#433,#434,#435,#436,#437,#438,#439,#440,#441,#442,#443,#444,#445,#446,#447,#448,#449,#450,#451,#452,#453,#454,#455,#456,#457,#458,#459,#460,#461,#462,#463,#464,#465,#466,#467,#468,#469,#470,#471,#472,#473,#474,#475,#476,#477,#478,#479,#480,#481,#482,#483,#484,#485,#486,#487,#488,#489,#490,#491,#492,#493,#494,#495,#496,#497,#498,#499,#500,#501,#502,#503,#504,#505,#506,#507,#508,#509,#510,#511,#512,#513,#514,#515,#516,#517,#518,#519,#520,#521,#522,#523,#524,#525,#526,#527,#528,#529,#530,#531,#532,#533,#534,#535,#536,#537,#538,#539,#540,#541,#542,#543,#544,#545,#546,#547,#548,#549,#550,#551,#552,#553,#554,#555,#556,#557,#558,#559,#560,#561,#562,#563,#564,#565,#566,#567,#568,#569,#570,#571,#572,#573,#574,#575,#576,#577,#578,#579,#580,#581,#582,#583,#584,#585,#586,#587,#588,#589,#590,#591,#592,#593,#594,#595,#596,#597,#598,#599,#600,#601,#602,#603,#604,#605,#606,#607,#608,#609,#610,#611,#612,#613,#614,#615,#616,#617,#618,#619,#620,#621,#622,#623,#624,#625,#626,#627,#628,#629,#630,#631,#632,#633,#634,#635,#636,#637,#638,#639,#640,#641,#642,#643,#644,#645,#646,#647,#648,#649,#650,#651,#652,#653,#654,#655,#656,#657,#658,#659,#660,#661,#662,#663,#664,#665,#666,#667,#668,#669,#670,#671,#672,#673,#674,#675,#676,#677,#678,#679,#680,#681,#682,#683,#684,#685,#686,#687,#688,#689,#690,#691,#692,#693,#694,#695,#696,#697,#698,#699,#700,#701,#702,#703,#704,#705,#706,#707,#708,#709,#710,#711,#712,#713,#714,#715,#716,#717,#718,#719,#720,#721,#722,#723,#724,#725,#726,#727,#728,#729,#730,#731,#732,#733,#734,#735,#736,#737,#738,#739,#740,#741,#742,#743,#744,#745,#746,#747,#748,#749,#750,#751,#752,#753,#754,#755,#756,#757,#758,#759,#760,#761,#762,#763,#764,#765,#766,#767,#768,#769,#770,#771,#772,#773,#774,#775,#776,#777,#778,#779,#780,#781,#782,#783,#784,#785,#786,#787,#788,#789,#790,#791,#792,#793,#794,#795,#796,#797,#798,#799,#800,#801,#802,#803,#804,#805,#806,#807,#808,#809,#810,#811,#812,#813,#814,#815,#816,#817,#818,#819,#820,#821,#822,#823,#824,#825,#826,#827,#828,#829,#830,#831,#832,#833,#834,#835,#836,#837,#838,#839,#840,#841,#842,#843,#844,#845,#846,#847,#848,#849,#850,#851,#852,#853,#854,#855,#856,#857,#858,#859,#860,#861,#862,#863,#864,#865,#866,#867,#868,#869,#870,#871,#872,#873,#874,#875,#876,#877,#878,#879,#880,#881,#882,#883,#884,#885,#886,#887,#888,#889,#890,#891,#892,#893,#894,#895,#896,#897,#898,#899,#900,#901,#902,#903,#904,#905,#906,#907,#908,#909,#910,#911,#912,#913,#914,#915,#916,#917,#918,#919,#920,#921,#922,#923,#924,#925,#926,#927,#928,#929,#930,#931,#932,#933,#934,#935,#936,#937,#938,#939,#940,#941,#942,#943,#944,#945,#946,#947,#948,#949,#950,#951,#952,#953,#954,#955,#956,#957,#958,#959,#960,#961,#962,#963,#964,#965,#966,#967,#968,#969,#970,#971,#972,#973,#974,#975,#976,#977,#978,#979,#980,#981,#982,#983,#984,#985,#986,#987,#988,#989,#990,#991,#992,#993,#994,#995,#996,#997,#998,#999,#1000,#1001,#1002,#1003,#1004,#1005,#1006,#1007,#1008,#1009,#1010,#1011,#1012,#1013,#1014,#1015,#1016,#1017,#1018,#1019,#1020,#1021,#1022,#1023,#1024,#1025,#1026,#1027,#1028,#1029,#1030,#1031,#1032,#1033,#1034,#1035,#1036,#1037,#1038,#1039,#1040,#1041,#1042,#1043,#1044,#1045,#1046,#1047,#1048,#1049,#1050,#1051,#1052,#1053,#1054,#1055,#1056,#1057,#1058,#1059,#1060,#1061,#1062,#1063,#1064,#1065,#1066,#1067,#1068,#1069,#1070,#1071,#1072,#1073,#1074,#1075),#9);
+#2=PRODUCT_DEFINITION_CONTEXT('',#1076,'design');
+#3=APPLICATION_PROTOCOL_DEFINITION('INTERNATIONAL STANDARD','automotive_design',1994,#1076);
+#4=PRODUCT_CATEGORY_RELATIONSHIP('NONE','NONE',#1077,#1078);
+#5=SHAPE_DEFINITION_REPRESENTATION(#1079,#1080);
+#6=SHAPE_DEFINITION_REPRESENTATION(#1079,#1081);
+#7=SHAPE_DEFINITION_REPRESENTATION(#1079,#1082);
+#8=SHAPE_DEFINITION_REPRESENTATION(#1079,#1083);
+#9= (GEOMETRIC_REPRESENTATION_CONTEXT(3)GLOBAL_UNCERTAINTY_ASSIGNED_CONTEXT((#1086))GLOBAL_UNIT_ASSIGNED_CONTEXT((#1088,#1089,#1090))REPRESENTATION_CONTEXT('NONE','WORKSPACE'));
+#13=STYLED_ITEM('',(#1092),#1093);
+#14=STYLED_ITEM('',(#1094),#1095);
+#15=STYLED_ITEM('',(#1096),#1097);
+#16=STYLED_ITEM('',(#1098),#1099);
+#17=STYLED_ITEM('',(#1100),#1101);
+#18=STYLED_ITEM('',(#1102),#1103);
+#19=STYLED_ITEM('',(#1104),#1105);
+#20=STYLED_ITEM('',(#1106),#1107);
+#21=STYLED_ITEM('',(#1108),#1109);
+#22=STYLED_ITEM('',(#1110),#1111);
+#23=STYLED_ITEM('',(#1112),#1113);
+#24=STYLED_ITEM('',(#1114),#1115);
+#25=STYLED_ITEM('',(#1116),#1117);
+#26=STYLED_ITEM('',(#1118),#1119);
+#27=STYLED_ITEM('',(#1120),#1121);
+#28=STYLED_ITEM('',(#1122),#1123);
+#29=STYLED_ITEM('',(#1124),#1125);
+#30=STYLED_ITEM('',(#1126),#1127);
+#31=STYLED_ITEM('',(#1128),#1129);
+#32=STYLED_ITEM('',(#1130),#1131);
+#33=STYLED_ITEM('',(#1132),#1133);
+#34=STYLED_ITEM('',(#1134),#1135);
+#35=STYLED_ITEM('',(#1136),#1137);
+#36=STYLED_ITEM('',(#1138),#1139);
+#37=STYLED_ITEM('',(#1140),#1141);
+#38=STYLED_ITEM('',(#1142),#1143);
+#39=STYLED_ITEM('',(#1144),#1145);
+#40=STYLED_ITEM('',(#1146),#1147);
+#41=STYLED_ITEM('',(#1148),#1149);
+#42=STYLED_ITEM('',(#1150),#1151);
+#43=STYLED_ITEM('',(#1152),#1153);
+#44=STYLED_ITEM('',(#1154),#1155);
+#45=STYLED_ITEM('',(#1156),#1157);
+#46=STYLED_ITEM('',(#1158),#1159);
+#47=STYLED_ITEM('',(#1160),#1161);
+#48=STYLED_ITEM('',(#1162),#1163);
+#49=STYLED_ITEM('',(#1164),#1165);
+#50=STYLED_ITEM('',(#1166),#1167);
+#51=STYLED_ITEM('',(#1168),#1169);
+#52=STYLED_ITEM('',(#1170),#1171);
+#53=STYLED_ITEM('',(#1172),#1173);
+#54=STYLED_ITEM('',(#1174),#1175);
+#55=STYLED_ITEM('',(#1176),#1177);
+#56=STYLED_ITEM('',(#1178),#1179);
+#57=STYLED_ITEM('',(#1180),#1181);
+#58=STYLED_ITEM('',(#1182),#1183);
+#59=STYLED_ITEM('',(#1184),#1185);
+#60=STYLED_ITEM('',(#1186),#1187);
+#61=STYLED_ITEM('',(#1188),#1189);
+#62=STYLED_ITEM('',(#1190),#1191);
+#63=STYLED_ITEM('',(#1192),#1193);
+#64=STYLED_ITEM('',(#1194),#1195);
+#65=STYLED_ITEM('',(#1196),#1197);
+#66=STYLED_ITEM('',(#1198),#1199);
+#67=STYLED_ITEM('',(#1200),#1201);
+#68=STYLED_ITEM('',(#1202),#1203);
+#69=STYLED_ITEM('',(#1204),#1205);
+#70=STYLED_ITEM('',(#1206),#1207);
+#71=STYLED_ITEM('',(#1208),#1209);
+#72=STYLED_ITEM('',(#1210),#1211);
+#73=STYLED_ITEM('',(#1212),#1213);
+#74=STYLED_ITEM('',(#1214),#1215);
+#75=STYLED_ITEM('',(#1216),#1217);
+#76=STYLED_ITEM('',(#1218),#1219);
+#77=STYLED_ITEM('',(#1220),#1221);
+#78=STYLED_ITEM('',(#1222),#1223);
+#79=STYLED_ITEM('',(#1224),#1225);
+#80=STYLED_ITEM('',(#1226),#1227);
+#81=STYLED_ITEM('',(#1228),#1229);
+#82=STYLED_ITEM('',(#1230),#1231);
+#83=STYLED_ITEM('',(#1232),#1233);
+#84=STYLED_ITEM('',(#1234),#1235);
+#85=STYLED_ITEM('',(#1236),#1237);
+#86=STYLED_ITEM('',(#1238),#1239);
+#87=STYLED_ITEM('',(#1240),#1241);
+#88=STYLED_ITEM('',(#1242),#1243);
+#89=STYLED_ITEM('',(#1244),#1245);
+#90=STYLED_ITEM('',(#1246),#1247);
+#91=STYLED_ITEM('',(#1248),#1249);
+#92=STYLED_ITEM('',(#1250),#1251);
+#93=STYLED_ITEM('',(#1252),#1253);
+#94=STYLED_ITEM('',(#1254),#1255);
+#95=STYLED_ITEM('',(#1256),#1257);
+#96=STYLED_ITEM('',(#1258),#1259);
+#97=STYLED_ITEM('',(#1260),#1261);
+#98=STYLED_ITEM('',(#1262),#1263);
+#99=STYLED_ITEM('',(#1264),#1265);
+#100=STYLED_ITEM('',(#1266),#1267);
+#101=STYLED_ITEM('',(#1268),#1269);
+#102=STYLED_ITEM('',(#1270),#1271);
+#103=STYLED_ITEM('',(#1272),#1273);
+#104=STYLED_ITEM('',(#1274),#1275);
+#105=STYLED_ITEM('',(#1276),#1277);
+#106=STYLED_ITEM('',(#1278),#1279);
+#107=STYLED_ITEM('',(#1280),#1281);
+#108=STYLED_ITEM('',(#1282),#1283);
+#109=STYLED_ITEM('',(#1284),#1285);
+#110=STYLED_ITEM('',(#1286),#1287);
+#111=STYLED_ITEM('',(#1288),#1289);
+#112=STYLED_ITEM('',(#1290),#1291);
+#113=STYLED_ITEM('',(#1292),#1293);
+#114=STYLED_ITEM('',(#1294),#1295);
+#115=STYLED_ITEM('',(#1296),#1297);
+#116=STYLED_ITEM('',(#1298),#1299);
+#117=STYLED_ITEM('',(#1300),#1301);
+#118=STYLED_ITEM('',(#1302),#1303);
+#119=STYLED_ITEM('',(#1304),#1305);
+#120=STYLED_ITEM('',(#1306),#1307);
+#121=STYLED_ITEM('',(#1308),#1309);
+#122=STYLED_ITEM('',(#1310),#1311);
+#123=STYLED_ITEM('',(#1312),#1313);
+#124=STYLED_ITEM('',(#1314),#1315);
+#125=STYLED_ITEM('',(#1316),#1317);
+#126=STYLED_ITEM('',(#1318),#1319);
+#127=STYLED_ITEM('',(#1320),#1321);
+#128=STYLED_ITEM('',(#1322),#1323);
+#129=STYLED_ITEM('',(#1324),#1325);
+#130=STYLED_ITEM('',(#1326),#1327);
+#131=STYLED_ITEM('',(#1328),#1329);
+#132=STYLED_ITEM('',(#1330),#1331);
+#133=STYLED_ITEM('',(#1332),#1333);
+#134=STYLED_ITEM('',(#1334),#1335);
+#135=STYLED_ITEM('',(#1336),#1337);
+#136=STYLED_ITEM('',(#1338),#1339);
+#137=STYLED_ITEM('',(#1340),#1341);
+#138=STYLED_ITEM('',(#1342),#1343);
+#139=STYLED_ITEM('',(#1344),#1345);
+#140=STYLED_ITEM('',(#1346),#1347);
+#141=STYLED_ITEM('',(#1348),#1349);
+#142=STYLED_ITEM('',(#1350),#1351);
+#143=STYLED_ITEM('',(#1352),#1353);
+#144=STYLED_ITEM('',(#1354),#1355);
+#145=STYLED_ITEM('',(#1356),#1357);
+#146=STYLED_ITEM('',(#1358),#1359);
+#147=STYLED_ITEM('',(#1360),#1361);
+#148=STYLED_ITEM('',(#1362),#1363);
+#149=STYLED_ITEM('',(#1364),#1365);
+#150=STYLED_ITEM('',(#1366),#1367);
+#151=STYLED_ITEM('',(#1368),#1369);
+#152=STYLED_ITEM('',(#1370),#1371);
+#153=STYLED_ITEM('',(#1372),#1373);
+#154=STYLED_ITEM('',(#1374),#1375);
+#155=STYLED_ITEM('',(#1376),#1377);
+#156=STYLED_ITEM('',(#1378),#1379);
+#157=STYLED_ITEM('',(#1380),#1381);
+#158=STYLED_ITEM('',(#1382),#1383);
+#159=STYLED_ITEM('',(#1384),#1385);
+#160=STYLED_ITEM('',(#1386),#1387);
+#161=STYLED_ITEM('',(#1388),#1389);
+#162=STYLED_ITEM('',(#1390),#1391);
+#163=STYLED_ITEM('',(#1392),#1393);
+#164=STYLED_ITEM('',(#1394),#1395);
+#165=STYLED_ITEM('',(#1396),#1397);
+#166=STYLED_ITEM('',(#1398),#1399);
+#167=STYLED_ITEM('',(#1400),#1401);
+#168=STYLED_ITEM('',(#1402),#1403);
+#169=STYLED_ITEM('',(#1404),#1405);
+#170=STYLED_ITEM('',(#1406),#1407);
+#171=STYLED_ITEM('',(#1408),#1409);
+#172=STYLED_ITEM('',(#1410),#1411);
+#173=STYLED_ITEM('',(#1412),#1413);
+#174=STYLED_ITEM('',(#1414),#1415);
+#175=STYLED_ITEM('',(#1416),#1417);
+#176=STYLED_ITEM('',(#1418),#1419);
+#177=STYLED_ITEM('',(#1420),#1421);
+#178=STYLED_ITEM('',(#1422),#1423);
+#179=STYLED_ITEM('',(#1424),#1425);
+#180=STYLED_ITEM('',(#1426),#1427);
+#181=STYLED_ITEM('',(#1428),#1429);
+#182=STYLED_ITEM('',(#1430),#1431);
+#183=STYLED_ITEM('',(#1432),#1433);
+#184=STYLED_ITEM('',(#1434),#1435);
+#185=STYLED_ITEM('',(#1436),#1437);
+#186=STYLED_ITEM('',(#1438),#1439);
+#187=STYLED_ITEM('',(#1440),#1441);
+#188=STYLED_ITEM('',(#1442),#1443);
+#189=STYLED_ITEM('',(#1444),#1445);
+#190=STYLED_ITEM('',(#1446),#1447);
+#191=STYLED_ITEM('',(#1448),#1449);
+#192=STYLED_ITEM('',(#1450),#1451);
+#193=STYLED_ITEM('',(#1452),#1453);
+#194=STYLED_ITEM('',(#1454),#1455);
+#195=STYLED_ITEM('',(#1456),#1457);
+#196=STYLED_ITEM('',(#1458),#1459);
+#197=STYLED_ITEM('',(#1460),#1461);
+#198=STYLED_ITEM('',(#1462),#1463);
+#199=STYLED_ITEM('',(#1464),#1465);
+#200=STYLED_ITEM('',(#1466),#1467);
+#201=STYLED_ITEM('',(#1468),#1469);
+#202=STYLED_ITEM('',(#1470),#1471);
+#203=STYLED_ITEM('',(#1472),#1473);
+#204=STYLED_ITEM('',(#1474),#1475);
+#205=STYLED_ITEM('',(#1476),#1477);
+#206=STYLED_ITEM('',(#1478),#1479);
+#207=STYLED_ITEM('',(#1480),#1481);
+#208=STYLED_ITEM('',(#1482),#1483);
+#209=STYLED_ITEM('',(#1484),#1485);
+#210=STYLED_ITEM('',(#1486),#1487);
+#211=STYLED_ITEM('',(#1488),#1489);
+#212=STYLED_ITEM('',(#1490),#1491);
+#213=STYLED_ITEM('',(#1492),#1493);
+#214=STYLED_ITEM('',(#1494),#1495);
+#215=STYLED_ITEM('',(#1496),#1497);
+#216=STYLED_ITEM('',(#1498),#1499);
+#217=STYLED_ITEM('',(#1500),#1501);
+#218=STYLED_ITEM('',(#1502),#1503);
+#219=STYLED_ITEM('',(#1504),#1505);
+#220=STYLED_ITEM('',(#1506),#1507);
+#221=STYLED_ITEM('',(#1508),#1509);
+#222=STYLED_ITEM('',(#1510),#1511);
+#223=STYLED_ITEM('',(#1512),#1513);
+#224=STYLED_ITEM('',(#1514),#1515);
+#225=STYLED_ITEM('',(#1516),#1517);
+#226=STYLED_ITEM('',(#1518),#1519);
+#227=STYLED_ITEM('',(#1520),#1521);
+#228=STYLED_ITEM('',(#1522),#1523);
+#229=STYLED_ITEM('',(#1524),#1525);
+#230=STYLED_ITEM('',(#1526),#1527);
+#231=STYLED_ITEM('',(#1528),#1529);
+#232=STYLED_ITEM('',(#1530),#1531);
+#233=STYLED_ITEM('',(#1532),#1533);
+#234=STYLED_ITEM('',(#1534),#1535);
+#235=STYLED_ITEM('',(#1536),#1537);
+#236=STYLED_ITEM('',(#1538),#1539);
+#237=STYLED_ITEM('',(#1540),#1541);
+#238=STYLED_ITEM('',(#1542),#1543);
+#239=STYLED_ITEM('',(#1544),#1545);
+#240=STYLED_ITEM('',(#1546),#1547);
+#241=STYLED_ITEM('',(#1548),#1549);
+#242=STYLED_ITEM('',(#1550),#1551);
+#243=STYLED_ITEM('',(#1552),#1553);
+#244=STYLED_ITEM('',(#1554),#1555);
+#245=STYLED_ITEM('',(#1556),#1557);
+#246=STYLED_ITEM('',(#1558),#1559);
+#247=STYLED_ITEM('',(#1560),#1561);
+#248=STYLED_ITEM('',(#1562),#1563);
+#249=STYLED_ITEM('',(#1564),#1565);
+#250=STYLED_ITEM('',(#1566),#1567);
+#251=STYLED_ITEM('',(#1568),#1569);
+#252=STYLED_ITEM('',(#1570),#1571);
+#253=STYLED_ITEM('',(#1572),#1573);
+#254=STYLED_ITEM('',(#1574),#1575);
+#255=STYLED_ITEM('',(#1576),#1577);
+#256=STYLED_ITEM('',(#1578),#1579);
+#257=STYLED_ITEM('',(#1580),#1581);
+#258=STYLED_ITEM('',(#1582),#1583);
+#259=STYLED_ITEM('',(#1584),#1585);
+#260=STYLED_ITEM('',(#1586),#1587);
+#261=STYLED_ITEM('',(#1588),#1589);
+#262=STYLED_ITEM('',(#1590),#1591);
+#263=STYLED_ITEM('',(#1592),#1593);
+#264=STYLED_ITEM('',(#1594),#1595);
+#265=STYLED_ITEM('',(#1596),#1597);
+#266=STYLED_ITEM('',(#1598),#1599);
+#267=STYLED_ITEM('',(#1600),#1601);
+#268=STYLED_ITEM('',(#1602),#1603);
+#269=STYLED_ITEM('',(#1604),#1605);
+#270=STYLED_ITEM('',(#1606),#1607);
+#271=STYLED_ITEM('',(#1608),#1609);
+#272=STYLED_ITEM('',(#1610),#1611);
+#273=STYLED_ITEM('',(#1612),#1613);
+#274=STYLED_ITEM('',(#1614),#1615);
+#275=STYLED_ITEM('',(#1616),#1617);
+#276=STYLED_ITEM('',(#1618),#1619);
+#277=STYLED_ITEM('',(#1620),#1621);
+#278=STYLED_ITEM('',(#1622),#1623);
+#279=STYLED_ITEM('',(#1624),#1625);
+#280=STYLED_ITEM('',(#1626),#1627);
+#281=STYLED_ITEM('',(#1628),#1629);
+#282=STYLED_ITEM('',(#1630),#1631);
+#283=STYLED_ITEM('',(#1632),#1633);
+#284=STYLED_ITEM('',(#1634),#1635);
+#285=STYLED_ITEM('',(#1636),#1637);
+#286=STYLED_ITEM('',(#1638),#1639);
+#287=STYLED_ITEM('',(#1640),#1641);
+#288=STYLED_ITEM('',(#1642),#1643);
+#289=STYLED_ITEM('',(#1644),#1645);
+#290=STYLED_ITEM('',(#1646),#1647);
+#291=STYLED_ITEM('',(#1648),#1649);
+#292=STYLED_ITEM('',(#1650),#1651);
+#293=STYLED_ITEM('',(#1652),#1653);
+#294=STYLED_ITEM('',(#1654),#1655);
+#295=STYLED_ITEM('',(#1656),#1657);
+#296=STYLED_ITEM('',(#1658),#1659);
+#297=STYLED_ITEM('',(#1660),#1661);
+#298=STYLED_ITEM('',(#1662),#1663);
+#299=STYLED_ITEM('',(#1664),#1665);
+#300=STYLED_ITEM('',(#1666),#1667);
+#301=STYLED_ITEM('',(#1668),#1669);
+#302=STYLED_ITEM('',(#1670),#1671);
+#303=STYLED_ITEM('',(#1672),#1673);
+#304=STYLED_ITEM('',(#1674),#1675);
+#305=STYLED_ITEM('',(#1676),#1677);
+#306=STYLED_ITEM('',(#1678),#1679);
+#307=STYLED_ITEM('',(#1680),#1681);
+#308=STYLED_ITEM('',(#1682),#1683);
+#309=STYLED_ITEM('',(#1684),#1685);
+#310=STYLED_ITEM('',(#1686),#1687);
+#311=STYLED_ITEM('',(#1688),#1689);
+#312=STYLED_ITEM('',(#1690),#1691);
+#313=STYLED_ITEM('',(#1692),#1693);
+#314=STYLED_ITEM('',(#1694),#1695);
+#315=STYLED_ITEM('',(#1696),#1697);
+#316=STYLED_ITEM('',(#1698),#1699);
+#317=STYLED_ITEM('',(#1700),#1701);
+#318=STYLED_ITEM('',(#1702),#1703);
+#319=STYLED_ITEM('',(#1704),#1705);
+#320=STYLED_ITEM('',(#1706),#1707);
+#321=STYLED_ITEM('',(#1708),#1709);
+#322=STYLED_ITEM('',(#1710),#1711);
+#323=STYLED_ITEM('',(#1712),#1713);
+#324=STYLED_ITEM('',(#1714),#1715);
+#325=STYLED_ITEM('',(#1716),#1717);
+#326=STYLED_ITEM('',(#1718),#1719);
+#327=STYLED_ITEM('',(#1720),#1721);
+#328=STYLED_ITEM('',(#1722),#1723);
+#329=STYLED_ITEM('',(#1724),#1725);
+#330=STYLED_ITEM('',(#1726),#1727);
+#331=STYLED_ITEM('',(#1728),#1729);
+#332=STYLED_ITEM('',(#1730),#1731);
+#333=STYLED_ITEM('',(#1732),#1733);
+#334=STYLED_ITEM('',(#1734),#1735);
+#335=STYLED_ITEM('',(#1736),#1737);
+#336=STYLED_ITEM('',(#1738),#1739);
+#337=STYLED_ITEM('',(#1740),#1741);
+#338=STYLED_ITEM('',(#1742),#1743);
+#339=STYLED_ITEM('',(#1744),#1745);
+#340=STYLED_ITEM('',(#1746),#1747);
+#341=STYLED_ITEM('',(#1748),#1749);
+#342=STYLED_ITEM('',(#1750),#1751);
+#343=STYLED_ITEM('',(#1752),#1753);
+#344=STYLED_ITEM('',(#1754),#1755);
+#345=STYLED_ITEM('',(#1756),#1757);
+#346=STYLED_ITEM('',(#1758),#1759);
+#347=STYLED_ITEM('',(#1760),#1761);
+#348=STYLED_ITEM('',(#1762),#1763);
+#349=STYLED_ITEM('',(#1764),#1765);
+#350=STYLED_ITEM('',(#1766),#1767);
+#351=STYLED_ITEM('',(#1768),#1769);
+#352=STYLED_ITEM('',(#1770),#1771);
+#353=STYLED_ITEM('',(#1772),#1773);
+#354=STYLED_ITEM('',(#1774),#1775);
+#355=STYLED_ITEM('',(#1776),#1777);
+#356=STYLED_ITEM('',(#1778),#1779);
+#357=STYLED_ITEM('',(#1780),#1781);
+#358=STYLED_ITEM('',(#1782),#1783);
+#359=STYLED_ITEM('',(#1784),#1785);
+#360=STYLED_ITEM('',(#1786),#1787);
+#361=STYLED_ITEM('',(#1788),#1789);
+#362=STYLED_ITEM('',(#1790),#1791);
+#363=STYLED_ITEM('',(#1792),#1793);
+#364=STYLED_ITEM('',(#1794),#1795);
+#365=STYLED_ITEM('',(#1796),#1797);
+#366=STYLED_ITEM('',(#1798),#1799);
+#367=STYLED_ITEM('',(#1800),#1801);
+#368=STYLED_ITEM('',(#1802),#1803);
+#369=STYLED_ITEM('',(#1804),#1805);
+#370=STYLED_ITEM('',(#1806),#1807);
+#371=STYLED_ITEM('',(#1808),#1809);
+#372=STYLED_ITEM('',(#1810),#1811);
+#373=STYLED_ITEM('',(#1812),#1813);
+#374=STYLED_ITEM('',(#1814),#1815);
+#375=STYLED_ITEM('',(#1816),#1817);
+#376=STYLED_ITEM('',(#1818),#1819);
+#377=STYLED_ITEM('',(#1820),#1821);
+#378=STYLED_ITEM('',(#1822),#1823);
+#379=STYLED_ITEM('',(#1824),#1825);
+#380=STYLED_ITEM('',(#1826),#1827);
+#381=STYLED_ITEM('',(#1828),#1829);
+#382=STYLED_ITEM('',(#1830),#1831);
+#383=STYLED_ITEM('',(#1832),#1833);
+#384=STYLED_ITEM('',(#1834),#1835);
+#385=STYLED_ITEM('',(#1836),#1837);
+#386=STYLED_ITEM('',(#1838),#1839);
+#387=STYLED_ITEM('',(#1840),#1841);
+#388=STYLED_ITEM('',(#1842),#1843);
+#389=STYLED_ITEM('',(#1844),#1845);
+#390=STYLED_ITEM('',(#1846),#1847);
+#391=STYLED_ITEM('',(#1848),#1849);
+#392=STYLED_ITEM('',(#1850),#1851);
+#393=STYLED_ITEM('',(#1852),#1853);
+#394=STYLED_ITEM('',(#1854),#1855);
+#395=STYLED_ITEM('',(#1856),#1857);
+#396=STYLED_ITEM('',(#1858),#1859);
+#397=STYLED_ITEM('',(#1860),#1861);
+#398=STYLED_ITEM('',(#1862),#1863);
+#399=STYLED_ITEM('',(#1864),#1865);
+#400=STYLED_ITEM('',(#1866),#1867);
+#401=STYLED_ITEM('',(#1868),#1869);
+#402=STYLED_ITEM('',(#1870),#1871);
+#403=STYLED_ITEM('',(#1872),#1873);
+#404=STYLED_ITEM('',(#1874),#1875);
+#405=STYLED_ITEM('',(#1876),#1877);
+#406=STYLED_ITEM('',(#1878),#1879);
+#407=STYLED_ITEM('',(#1880),#1881);
+#408=STYLED_ITEM('',(#1882),#1883);
+#409=STYLED_ITEM('',(#1884),#1885);
+#410=STYLED_ITEM('',(#1886),#1887);
+#411=STYLED_ITEM('',(#1888),#1889);
+#412=STYLED_ITEM('',(#1890),#1891);
+#413=STYLED_ITEM('',(#1892),#1893);
+#414=STYLED_ITEM('',(#1894),#1895);
+#415=STYLED_ITEM('',(#1896),#1897);
+#416=STYLED_ITEM('',(#1898),#1899);
+#417=STYLED_ITEM('',(#1900),#1901);
+#418=STYLED_ITEM('',(#1902),#1903);
+#419=STYLED_ITEM('',(#1904),#1905);
+#420=STYLED_ITEM('',(#1906),#1907);
+#421=STYLED_ITEM('',(#1908),#1909);
+#422=STYLED_ITEM('',(#1910),#1911);
+#423=STYLED_ITEM('',(#1912),#1913);
+#424=STYLED_ITEM('',(#1914),#1915);
+#425=STYLED_ITEM('',(#1916),#1917);
+#426=STYLED_ITEM('',(#1918),#1919);
+#427=STYLED_ITEM('',(#1920),#1921);
+#428=STYLED_ITEM('',(#1922),#1923);
+#429=STYLED_ITEM('',(#1924),#1925);
+#430=STYLED_ITEM('',(#1926),#1927);
+#431=STYLED_ITEM('',(#1928),#1929);
+#432=STYLED_ITEM('',(#1930),#1931);
+#433=STYLED_ITEM('',(#1932),#1933);
+#434=STYLED_ITEM('',(#1934),#1935);
+#435=STYLED_ITEM('',(#1936),#1937);
+#436=STYLED_ITEM('',(#1938),#1939);
+#437=STYLED_ITEM('',(#1940),#1941);
+#438=STYLED_ITEM('',(#1942),#1943);
+#439=STYLED_ITEM('',(#1944),#1945);
+#440=STYLED_ITEM('',(#1946),#1947);
+#441=STYLED_ITEM('',(#1948),#1949);
+#442=STYLED_ITEM('',(#1950),#1951);
+#443=STYLED_ITEM('',(#1952),#1953);
+#444=STYLED_ITEM('',(#1954),#1955);
+#445=STYLED_ITEM('',(#1956),#1957);
+#446=STYLED_ITEM('',(#1958),#1959);
+#447=STYLED_ITEM('',(#1960),#1961);
+#448=STYLED_ITEM('',(#1962),#1963);
+#449=STYLED_ITEM('',(#1964),#1965);
+#450=STYLED_ITEM('',(#1966),#1967);
+#451=STYLED_ITEM('',(#1968),#1969);
+#452=STYLED_ITEM('',(#1970),#1971);
+#453=STYLED_ITEM('',(#1972),#1973);
+#454=STYLED_ITEM('',(#1974),#1975);
+#455=STYLED_ITEM('',(#1976),#1977);
+#456=STYLED_ITEM('',(#1978),#1979);
+#457=STYLED_ITEM('',(#1980),#1981);
+#458=STYLED_ITEM('',(#1982),#1983);
+#459=STYLED_ITEM('',(#1984),#1985);
+#460=STYLED_ITEM('',(#1986),#1987);
+#461=STYLED_ITEM('',(#1988),#1989);
+#462=STYLED_ITEM('',(#1990),#1991);
+#463=STYLED_ITEM('',(#1992),#1993);
+#464=STYLED_ITEM('',(#1994),#1995);
+#465=STYLED_ITEM('',(#1996),#1997);
+#466=STYLED_ITEM('',(#1998),#1999);
+#467=STYLED_ITEM('',(#2000),#2001);
+#468=STYLED_ITEM('',(#2002),#2003);
+#469=STYLED_ITEM('',(#2004),#2005);
+#470=STYLED_ITEM('',(#2006),#2007);
+#471=STYLED_ITEM('',(#2008),#2009);
+#472=STYLED_ITEM('',(#2010),#2011);
+#473=STYLED_ITEM('',(#2012),#2013);
+#474=STYLED_ITEM('',(#2014),#2015);
+#475=STYLED_ITEM('',(#2016),#2017);
+#476=STYLED_ITEM('',(#2018),#2019);
+#477=STYLED_ITEM('',(#2020),#2021);
+#478=STYLED_ITEM('',(#2022),#2023);
+#479=STYLED_ITEM('',(#2024),#2025);
+#480=STYLED_ITEM('',(#2026),#2027);
+#481=STYLED_ITEM('',(#2028),#2029);
+#482=STYLED_ITEM('',(#2030),#2031);
+#483=STYLED_ITEM('',(#2032),#2033);
+#484=STYLED_ITEM('',(#2034),#2035);
+#485=STYLED_ITEM('',(#2036),#2037);
+#486=STYLED_ITEM('',(#2038),#2039);
+#487=STYLED_ITEM('',(#2040),#2041);
+#488=STYLED_ITEM('',(#2042),#2043);
+#489=STYLED_ITEM('',(#2044),#2045);
+#490=STYLED_ITEM('',(#2046),#2047);
+#491=STYLED_ITEM('',(#2048),#2049);
+#492=STYLED_ITEM('',(#2050),#2051);
+#493=STYLED_ITEM('',(#2052),#2053);
+#494=STYLED_ITEM('',(#2054),#2055);
+#495=STYLED_ITEM('',(#2056),#2057);
+#496=STYLED_ITEM('',(#2058),#2059);
+#497=STYLED_ITEM('',(#2060),#2061);
+#498=STYLED_ITEM('',(#2062),#2063);
+#499=STYLED_ITEM('',(#2064),#2065);
+#500=STYLED_ITEM('',(#2066),#2067);
+#501=STYLED_ITEM('',(#2068),#2069);
+#502=STYLED_ITEM('',(#2070),#2071);
+#503=STYLED_ITEM('',(#2072),#2073);
+#504=STYLED_ITEM('',(#2074),#2075);
+#505=STYLED_ITEM('',(#2076),#2077);
+#506=STYLED_ITEM('',(#2078),#2079);
+#507=STYLED_ITEM('',(#2080),#2081);
+#508=STYLED_ITEM('',(#2082),#2083);
+#509=STYLED_ITEM('',(#2084),#2085);
+#510=STYLED_ITEM('',(#2086),#2087);
+#511=STYLED_ITEM('',(#2088),#2089);
+#512=STYLED_ITEM('',(#2090),#2091);
+#513=STYLED_ITEM('',(#2092),#2093);
+#514=STYLED_ITEM('',(#2094),#2095);
+#515=STYLED_ITEM('',(#2096),#2097);
+#516=STYLED_ITEM('',(#2098),#2099);
+#517=STYLED_ITEM('',(#2100),#2101);
+#518=STYLED_ITEM('',(#2102),#2103);
+#519=STYLED_ITEM('',(#2104),#2105);
+#520=STYLED_ITEM('',(#2106),#2107);
+#521=STYLED_ITEM('',(#2108),#2109);
+#522=STYLED_ITEM('',(#2110),#2111);
+#523=STYLED_ITEM('',(#2112),#2113);
+#524=STYLED_ITEM('',(#2114),#2115);
+#525=STYLED_ITEM('',(#2116),#2117);
+#526=STYLED_ITEM('',(#2118),#2119);
+#527=STYLED_ITEM('',(#2120),#2121);
+#528=STYLED_ITEM('',(#2122),#2123);
+#529=STYLED_ITEM('',(#2124),#2125);
+#530=STYLED_ITEM('',(#2126),#2127);
+#531=STYLED_ITEM('',(#2128),#2129);
+#532=STYLED_ITEM('',(#2130),#2131);
+#533=STYLED_ITEM('',(#2132),#2133);
+#534=STYLED_ITEM('',(#2134),#2135);
+#535=STYLED_ITEM('',(#2136),#2137);
+#536=STYLED_ITEM('',(#2138),#2139);
+#537=STYLED_ITEM('',(#2140),#2141);
+#538=STYLED_ITEM('',(#2142),#2143);
+#539=STYLED_ITEM('',(#2144),#2145);
+#540=STYLED_ITEM('',(#2146),#2147);
+#541=STYLED_ITEM('',(#2148),#2149);
+#542=STYLED_ITEM('',(#2150),#2151);
+#543=STYLED_ITEM('',(#2152),#2153);
+#544=STYLED_ITEM('',(#2154),#2155);
+#545=STYLED_ITEM('',(#2156),#2157);
+#546=STYLED_ITEM('',(#2158),#2159);
+#547=STYLED_ITEM('',(#2160),#2161);
+#548=STYLED_ITEM('',(#2162),#2163);
+#549=STYLED_ITEM('',(#2164),#2165);
+#550=STYLED_ITEM('',(#2166),#2167);
+#551=STYLED_ITEM('',(#2168),#2169);
+#552=STYLED_ITEM('',(#2170),#2171);
+#553=STYLED_ITEM('',(#2172),#2173);
+#554=STYLED_ITEM('',(#2174),#2175);
+#555=STYLED_ITEM('',(#2176),#2177);
+#556=STYLED_ITEM('',(#2178),#2179);
+#557=STYLED_ITEM('',(#2180),#2181);
+#558=STYLED_ITEM('',(#2182),#2183);
+#559=STYLED_ITEM('',(#2184),#2185);
+#560=STYLED_ITEM('',(#2186),#2187);
+#561=STYLED_ITEM('',(#2188),#2189);
+#562=STYLED_ITEM('',(#2190),#2191);
+#563=STYLED_ITEM('',(#2192),#2193);
+#564=STYLED_ITEM('',(#2194),#2195);
+#565=STYLED_ITEM('',(#2196),#2197);
+#566=STYLED_ITEM('',(#2198),#2199);
+#567=STYLED_ITEM('',(#2200),#2201);
+#568=STYLED_ITEM('',(#2202),#2203);
+#569=STYLED_ITEM('',(#2204),#2205);
+#570=STYLED_ITEM('',(#2206),#2207);
+#571=STYLED_ITEM('',(#2208),#2209);
+#572=STYLED_ITEM('',(#2210),#2211);
+#573=STYLED_ITEM('',(#2212),#2213);
+#574=STYLED_ITEM('',(#2214),#2215);
+#575=STYLED_ITEM('',(#2216),#2217);
+#576=STYLED_ITEM('',(#2218),#2219);
+#577=STYLED_ITEM('',(#2220),#2221);
+#578=STYLED_ITEM('',(#2222),#2223);
+#579=STYLED_ITEM('',(#2224),#2225);
+#580=STYLED_ITEM('',(#2226),#2227);
+#581=STYLED_ITEM('',(#2228),#2229);
+#582=STYLED_ITEM('',(#2230),#2231);
+#583=STYLED_ITEM('',(#2232),#2233);
+#584=STYLED_ITEM('',(#2234),#2235);
+#585=STYLED_ITEM('',(#2236),#2237);
+#586=STYLED_ITEM('',(#2238),#2239);
+#587=STYLED_ITEM('',(#2240),#2241);
+#588=STYLED_ITEM('',(#2242),#2243);
+#589=STYLED_ITEM('',(#2244),#2245);
+#590=STYLED_ITEM('',(#2246),#2247);
+#591=STYLED_ITEM('',(#2248),#2249);
+#592=STYLED_ITEM('',(#2250),#2251);
+#593=STYLED_ITEM('',(#2252),#2253);
+#594=STYLED_ITEM('',(#2254),#2255);
+#595=STYLED_ITEM('',(#2256),#2257);
+#596=STYLED_ITEM('',(#2258),#2259);
+#597=STYLED_ITEM('',(#2260),#2261);
+#598=STYLED_ITEM('',(#2262),#2263);
+#599=STYLED_ITEM('',(#2264),#2265);
+#600=STYLED_ITEM('',(#2266),#2267);
+#601=STYLED_ITEM('',(#2268),#2269);
+#602=STYLED_ITEM('',(#2270),#2271);
+#603=STYLED_ITEM('',(#2272),#2273);
+#604=STYLED_ITEM('',(#2274),#2275);
+#605=STYLED_ITEM('',(#2276),#2277);
+#606=STYLED_ITEM('',(#2278),#2279);
+#607=STYLED_ITEM('',(#2280),#2281);
+#608=STYLED_ITEM('',(#2282),#2283);
+#609=STYLED_ITEM('',(#2284),#2285);
+#610=STYLED_ITEM('',(#2286),#2287);
+#611=STYLED_ITEM('',(#2288),#2289);
+#612=STYLED_ITEM('',(#2290),#2291);
+#613=STYLED_ITEM('',(#2292),#2293);
+#614=STYLED_ITEM('',(#2294),#2295);
+#615=STYLED_ITEM('',(#2296),#2297);
+#616=STYLED_ITEM('',(#2298),#2299);
+#617=STYLED_ITEM('',(#2300),#2301);
+#618=STYLED_ITEM('',(#2302),#2303);
+#619=STYLED_ITEM('',(#2304),#2305);
+#620=STYLED_ITEM('',(#2306),#2307);
+#621=STYLED_ITEM('',(#2308),#2309);
+#622=STYLED_ITEM('',(#2310),#2311);
+#623=STYLED_ITEM('',(#2312),#2313);
+#624=STYLED_ITEM('',(#2314),#2315);
+#625=STYLED_ITEM('',(#2316),#2317);
+#626=STYLED_ITEM('',(#2318),#2319);
+#627=STYLED_ITEM('',(#2320),#2321);
+#628=STYLED_ITEM('',(#2322),#2323);
+#629=STYLED_ITEM('',(#2324),#2325);
+#630=STYLED_ITEM('',(#2326),#2327);
+#631=STYLED_ITEM('',(#2328),#2329);
+#632=STYLED_ITEM('',(#2330),#2331);
+#633=STYLED_ITEM('',(#2332),#2333);
+#634=STYLED_ITEM('',(#2334),#2335);
+#635=STYLED_ITEM('',(#2336),#2337);
+#636=STYLED_ITEM('',(#2338),#2339);
+#637=STYLED_ITEM('',(#2340),#2341);
+#638=STYLED_ITEM('',(#2342),#2343);
+#639=STYLED_ITEM('',(#2344),#2345);
+#640=STYLED_ITEM('',(#2346),#2347);
+#641=STYLED_ITEM('',(#2348),#2349);
+#642=STYLED_ITEM('',(#2350),#2351);
+#643=STYLED_ITEM('',(#2352),#2353);
+#644=STYLED_ITEM('',(#2354),#2355);
+#645=STYLED_ITEM('',(#2356),#2357);
+#646=STYLED_ITEM('',(#2358),#2359);
+#647=STYLED_ITEM('',(#2360),#2361);
+#648=STYLED_ITEM('',(#2362),#2363);
+#649=STYLED_ITEM('',(#2364),#2365);
+#650=STYLED_ITEM('',(#2366),#2367);
+#651=STYLED_ITEM('',(#2368),#2369);
+#652=STYLED_ITEM('',(#2370),#2371);
+#653=STYLED_ITEM('',(#2372),#2373);
+#654=STYLED_ITEM('',(#2374),#2375);
+#655=STYLED_ITEM('',(#2376),#2377);
+#656=STYLED_ITEM('',(#2378),#2379);
+#657=STYLED_ITEM('',(#2380),#2381);
+#658=STYLED_ITEM('',(#2382),#2383);
+#659=STYLED_ITEM('',(#2384),#2385);
+#660=STYLED_ITEM('',(#2386),#2387);
+#661=STYLED_ITEM('',(#2388),#2389);
+#662=STYLED_ITEM('',(#2390),#2391);
+#663=STYLED_ITEM('',(#2392),#2393);
+#664=STYLED_ITEM('',(#2394),#2395);
+#665=STYLED_ITEM('',(#2396),#2397);
+#666=STYLED_ITEM('',(#2398),#2399);
+#667=STYLED_ITEM('',(#2400),#2401);
+#668=STYLED_ITEM('',(#2402),#2403);
+#669=STYLED_ITEM('',(#2404),#2405);
+#670=STYLED_ITEM('',(#2406),#2407);
+#671=STYLED_ITEM('',(#2408),#2409);
+#672=STYLED_ITEM('',(#2410),#2411);
+#673=STYLED_ITEM('',(#2412),#2413);
+#674=STYLED_ITEM('',(#2414),#2415);
+#675=STYLED_ITEM('',(#2416),#2417);
+#676=STYLED_ITEM('',(#2418),#2419);
+#677=STYLED_ITEM('',(#2420),#2421);
+#678=STYLED_ITEM('',(#2422),#2423);
+#679=STYLED_ITEM('',(#2424),#2425);
+#680=STYLED_ITEM('',(#2426),#2427);
+#681=STYLED_ITEM('',(#2428),#2429);
+#682=STYLED_ITEM('',(#2430),#2431);
+#683=STYLED_ITEM('',(#2432),#2433);
+#684=STYLED_ITEM('',(#2434),#2435);
+#685=STYLED_ITEM('',(#2436),#2437);
+#686=STYLED_ITEM('',(#2438),#2439);
+#687=STYLED_ITEM('',(#2440),#2441);
+#688=STYLED_ITEM('',(#2442),#2443);
+#689=STYLED_ITEM('',(#2444),#2445);
+#690=STYLED_ITEM('',(#2446),#2447);
+#691=STYLED_ITEM('',(#2448),#2449);
+#692=STYLED_ITEM('',(#2450),#2451);
+#693=STYLED_ITEM('',(#2452),#2453);
+#694=STYLED_ITEM('',(#2454),#2455);
+#695=STYLED_ITEM('',(#2456),#2457);
+#696=STYLED_ITEM('',(#2458),#2459);
+#697=STYLED_ITEM('',(#2460),#2461);
+#698=STYLED_ITEM('',(#2462),#2463);
+#699=STYLED_ITEM('',(#2464),#2465);
+#700=STYLED_ITEM('',(#2466),#2467);
+#701=STYLED_ITEM('',(#2468),#2469);
+#702=STYLED_ITEM('',(#2470),#2471);
+#703=STYLED_ITEM('',(#2472),#2473);
+#704=STYLED_ITEM('',(#2474),#2475);
+#705=STYLED_ITEM('',(#2476),#2477);
+#706=STYLED_ITEM('',(#2478),#2479);
+#707=STYLED_ITEM('',(#2480),#2481);
+#708=STYLED_ITEM('',(#2482),#2483);
+#709=STYLED_ITEM('',(#2484),#2485);
+#710=STYLED_ITEM('',(#2486),#2487);
+#711=STYLED_ITEM('',(#2488),#2489);
+#712=STYLED_ITEM('',(#2490),#2491);
+#713=STYLED_ITEM('',(#2492),#2493);
+#714=STYLED_ITEM('',(#2494),#2495);
+#715=STYLED_ITEM('',(#2496),#2497);
+#716=STYLED_ITEM('',(#2498),#2499);
+#717=STYLED_ITEM('',(#2500),#2501);
+#718=STYLED_ITEM('',(#2502),#2503);
+#719=STYLED_ITEM('',(#2504),#2505);
+#720=STYLED_ITEM('',(#2506),#2507);
+#721=STYLED_ITEM('',(#2508),#2509);
+#722=STYLED_ITEM('',(#2510),#2511);
+#723=STYLED_ITEM('',(#2512),#2513);
+#724=STYLED_ITEM('',(#2514),#2515);
+#725=STYLED_ITEM('',(#2516),#2517);
+#726=STYLED_ITEM('',(#2518),#2519);
+#727=STYLED_ITEM('',(#2520),#2521);
+#728=STYLED_ITEM('',(#2522),#2523);
+#729=STYLED_ITEM('',(#2524),#2525);
+#730=STYLED_ITEM('',(#2526),#2527);
+#731=STYLED_ITEM('',(#2528),#2529);
+#732=STYLED_ITEM('',(#2530),#2531);
+#733=STYLED_ITEM('',(#2532),#2533);
+#734=STYLED_ITEM('',(#2534),#2535);
+#735=STYLED_ITEM('',(#2536),#2537);
+#736=STYLED_ITEM('',(#2538),#2539);
+#737=STYLED_ITEM('',(#2540),#2541);
+#738=STYLED_ITEM('',(#2542),#2543);
+#739=STYLED_ITEM('',(#2544),#2545);
+#740=STYLED_ITEM('',(#2546),#2547);
+#741=STYLED_ITEM('',(#2548),#2549);
+#742=STYLED_ITEM('',(#2550),#2551);
+#743=STYLED_ITEM('',(#2552),#2553);
+#744=STYLED_ITEM('',(#2554),#2555);
+#745=STYLED_ITEM('',(#2556),#2557);
+#746=STYLED_ITEM('',(#2558),#2559);
+#747=STYLED_ITEM('',(#2560),#2561);
+#748=STYLED_ITEM('',(#2562),#2563);
+#749=STYLED_ITEM('',(#2564),#2565);
+#750=STYLED_ITEM('',(#2566),#2567);
+#751=STYLED_ITEM('',(#2568),#2569);
+#752=STYLED_ITEM('',(#2570),#2571);
+#753=STYLED_ITEM('',(#2572),#2573);
+#754=STYLED_ITEM('',(#2574),#2575);
+#755=STYLED_ITEM('',(#2576),#2577);
+#756=STYLED_ITEM('',(#2578),#2579);
+#757=STYLED_ITEM('',(#2580),#2581);
+#758=STYLED_ITEM('',(#2582),#2583);
+#759=STYLED_ITEM('',(#2584),#2585);
+#760=STYLED_ITEM('',(#2586),#2587);
+#761=STYLED_ITEM('',(#2588),#2589);
+#762=STYLED_ITEM('',(#2590),#2591);
+#763=STYLED_ITEM('',(#2592),#2593);
+#764=STYLED_ITEM('',(#2594),#2595);
+#765=STYLED_ITEM('',(#2596),#2597);
+#766=STYLED_ITEM('',(#2598),#2599);
+#767=STYLED_ITEM('',(#2600),#2601);
+#768=STYLED_ITEM('',(#2602),#2603);
+#769=STYLED_ITEM('',(#2604),#2605);
+#770=STYLED_ITEM('',(#2606),#2607);
+#771=STYLED_ITEM('',(#2608),#2609);
+#772=STYLED_ITEM('',(#2610),#2611);
+#773=STYLED_ITEM('',(#2612),#2613);
+#774=STYLED_ITEM('',(#2614),#2615);
+#775=STYLED_ITEM('',(#2616),#2617);
+#776=STYLED_ITEM('',(#2618),#2619);
+#777=STYLED_ITEM('',(#2620),#2621);
+#778=STYLED_ITEM('',(#2622),#2623);
+#779=STYLED_ITEM('',(#2624),#2625);
+#780=STYLED_ITEM('',(#2626),#2627);
+#781=STYLED_ITEM('',(#2628),#2629);
+#782=STYLED_ITEM('',(#2630),#2631);
+#783=STYLED_ITEM('',(#2632),#2633);
+#784=STYLED_ITEM('',(#2634),#2635);
+#785=STYLED_ITEM('',(#2636),#2637);
+#786=STYLED_ITEM('',(#2638),#2639);
+#787=STYLED_ITEM('',(#2640),#2641);
+#788=STYLED_ITEM('',(#2642),#2643);
+#789=STYLED_ITEM('',(#2644),#2645);
+#790=STYLED_ITEM('',(#2646),#2647);
+#791=STYLED_ITEM('',(#2648),#2649);
+#792=STYLED_ITEM('',(#2650),#2651);
+#793=STYLED_ITEM('',(#2652),#2653);
+#794=STYLED_ITEM('',(#2654),#2655);
+#795=STYLED_ITEM('',(#2656),#2657);
+#796=STYLED_ITEM('',(#2658),#2659);
+#797=STYLED_ITEM('',(#2660),#2661);
+#798=STYLED_ITEM('',(#2662),#2663);
+#799=STYLED_ITEM('',(#2664),#2665);
+#800=STYLED_ITEM('',(#2666),#2667);
+#801=STYLED_ITEM('',(#2668),#2669);
+#802=STYLED_ITEM('',(#2670),#2671);
+#803=STYLED_ITEM('',(#2672),#2673);
+#804=STYLED_ITEM('',(#2674),#2675);
+#805=STYLED_ITEM('',(#2676),#2677);
+#806=STYLED_ITEM('',(#2678),#2679);
+#807=STYLED_ITEM('',(#2680),#2681);
+#808=STYLED_ITEM('',(#2682),#2683);
+#809=STYLED_ITEM('',(#2684),#2685);
+#810=STYLED_ITEM('',(#2686),#2687);
+#811=STYLED_ITEM('',(#2688),#2689);
+#812=STYLED_ITEM('',(#2690),#2691);
+#813=STYLED_ITEM('',(#2692),#2693);
+#814=STYLED_ITEM('',(#2694),#2695);
+#815=STYLED_ITEM('',(#2696),#2697);
+#816=STYLED_ITEM('',(#2698),#2699);
+#817=STYLED_ITEM('',(#2700),#2701);
+#818=STYLED_ITEM('',(#2702),#2703);
+#819=STYLED_ITEM('',(#2704),#2705);
+#820=STYLED_ITEM('',(#2706),#2707);
+#821=STYLED_ITEM('',(#2708),#2709);
+#822=STYLED_ITEM('',(#2710),#2711);
+#823=STYLED_ITEM('',(#2712),#2713);
+#824=STYLED_ITEM('',(#2714),#2715);
+#825=STYLED_ITEM('',(#2716),#2717);
+#826=STYLED_ITEM('',(#2718),#2719);
+#827=STYLED_ITEM('',(#2720),#2721);
+#828=STYLED_ITEM('',(#2722),#2723);
+#829=STYLED_ITEM('',(#2724),#2725);
+#830=STYLED_ITEM('',(#2726),#2727);
+#831=STYLED_ITEM('',(#2728),#2729);
+#832=STYLED_ITEM('',(#2730),#2731);
+#833=STYLED_ITEM('',(#2732),#2733);
+#834=STYLED_ITEM('',(#2734),#2735);
+#835=STYLED_ITEM('',(#2736),#2737);
+#836=STYLED_ITEM('',(#2738),#2739);
+#837=STYLED_ITEM('',(#2740),#2741);
+#838=STYLED_ITEM('',(#2742),#2743);
+#839=STYLED_ITEM('',(#2744),#2745);
+#840=STYLED_ITEM('',(#2746),#2747);
+#841=STYLED_ITEM('',(#2748),#2749);
+#842=STYLED_ITEM('',(#2750),#2751);
+#843=STYLED_ITEM('',(#2752),#2753);
+#844=STYLED_ITEM('',(#2754),#2755);
+#845=STYLED_ITEM('',(#2756),#2757);
+#846=STYLED_ITEM('',(#2758),#2759);
+#847=STYLED_ITEM('',(#2760),#2761);
+#848=STYLED_ITEM('',(#2762),#2763);
+#849=STYLED_ITEM('',(#2764),#2765);
+#850=STYLED_ITEM('',(#2766),#2767);
+#851=STYLED_ITEM('',(#2768),#2769);
+#852=STYLED_ITEM('',(#2770),#2771);
+#853=STYLED_ITEM('',(#2772),#2773);
+#854=STYLED_ITEM('',(#2774),#2775);
+#855=STYLED_ITEM('',(#2776),#2777);
+#856=STYLED_ITEM('',(#2778),#2779);
+#857=STYLED_ITEM('',(#2780),#2781);
+#858=STYLED_ITEM('',(#2782),#2783);
+#859=STYLED_ITEM('',(#2784),#2785);
+#860=STYLED_ITEM('',(#2786),#2787);
+#861=STYLED_ITEM('',(#2788),#2789);
+#862=STYLED_ITEM('',(#2790),#2791);
+#863=STYLED_ITEM('',(#2792),#2793);
+#864=STYLED_ITEM('',(#2794),#2795);
+#865=STYLED_ITEM('',(#2796),#2797);
+#866=STYLED_ITEM('',(#2798),#2799);
+#867=STYLED_ITEM('',(#2800),#2801);
+#868=STYLED_ITEM('',(#2802),#2803);
+#869=STYLED_ITEM('',(#2804),#2805);
+#870=STYLED_ITEM('',(#2806),#2807);
+#871=STYLED_ITEM('',(#2808),#2809);
+#872=STYLED_ITEM('',(#2810),#2811);
+#873=STYLED_ITEM('',(#2812),#2813);
+#874=STYLED_ITEM('',(#2814),#2815);
+#875=STYLED_ITEM('',(#2816),#2817);
+#876=STYLED_ITEM('',(#2818),#2819);
+#877=STYLED_ITEM('',(#2820),#2821);
+#878=STYLED_ITEM('',(#2822),#2823);
+#879=STYLED_ITEM('',(#2824),#2825);
+#880=STYLED_ITEM('',(#2826),#2827);
+#881=STYLED_ITEM('',(#2828),#2829);
+#882=STYLED_ITEM('',(#2830),#2831);
+#883=STYLED_ITEM('',(#2832),#2833);
+#884=STYLED_ITEM('',(#2834),#2835);
+#885=STYLED_ITEM('',(#2836),#2837);
+#886=STYLED_ITEM('',(#2838),#2839);
+#887=STYLED_ITEM('',(#2840),#2841);
+#888=STYLED_ITEM('',(#2842),#2843);
+#889=STYLED_ITEM('',(#2844),#2845);
+#890=STYLED_ITEM('',(#2846),#2847);
+#891=STYLED_ITEM('',(#2848),#2849);
+#892=STYLED_ITEM('',(#2850),#2851);
+#893=STYLED_ITEM('',(#2852),#2853);
+#894=STYLED_ITEM('',(#2854),#2855);
+#895=STYLED_ITEM('',(#2856),#2857);
+#896=STYLED_ITEM('',(#2858),#2859);
+#897=STYLED_ITEM('',(#2860),#2861);
+#898=STYLED_ITEM('',(#2862),#2863);
+#899=STYLED_ITEM('',(#2864),#2865);
+#900=STYLED_ITEM('',(#2866),#2867);
+#901=STYLED_ITEM('',(#2868),#2869);
+#902=STYLED_ITEM('',(#2870),#2871);
+#903=STYLED_ITEM('',(#2872),#2873);
+#904=STYLED_ITEM('',(#2874),#2875);
+#905=STYLED_ITEM('',(#2876),#2877);
+#906=STYLED_ITEM('',(#2878),#2879);
+#907=STYLED_ITEM('',(#2880),#2881);
+#908=STYLED_ITEM('',(#2882),#2883);
+#909=STYLED_ITEM('',(#2884),#2885);
+#910=STYLED_ITEM('',(#2886),#2887);
+#911=STYLED_ITEM('',(#2888),#2889);
+#912=STYLED_ITEM('',(#2890),#2891);
+#913=STYLED_ITEM('',(#2892),#2893);
+#914=STYLED_ITEM('',(#2894),#2895);
+#915=STYLED_ITEM('',(#2896),#2897);
+#916=STYLED_ITEM('',(#2898),#2899);
+#917=STYLED_ITEM('',(#2900),#2901);
+#918=STYLED_ITEM('',(#2902),#2903);
+#919=STYLED_ITEM('',(#2904),#2905);
+#920=STYLED_ITEM('',(#2906),#2907);
+#921=STYLED_ITEM('',(#2908),#2909);
+#922=STYLED_ITEM('',(#2910),#2911);
+#923=STYLED_ITEM('',(#2912),#2913);
+#924=STYLED_ITEM('',(#2914),#2915);
+#925=STYLED_ITEM('',(#2916),#2917);
+#926=STYLED_ITEM('',(#2918),#2919);
+#927=STYLED_ITEM('',(#2920),#2921);
+#928=STYLED_ITEM('',(#2922),#2923);
+#929=STYLED_ITEM('',(#2924),#2925);
+#930=STYLED_ITEM('',(#2926),#2927);
+#931=STYLED_ITEM('',(#2928),#2929);
+#932=STYLED_ITEM('',(#2930),#2931);
+#933=STYLED_ITEM('',(#2932),#2933);
+#934=STYLED_ITEM('',(#2934),#2935);
+#935=STYLED_ITEM('',(#2936),#2937);
+#936=STYLED_ITEM('',(#2938),#2939);
+#937=STYLED_ITEM('',(#2940),#2941);
+#938=STYLED_ITEM('',(#2942),#2943);
+#939=STYLED_ITEM('',(#2944),#2945);
+#940=STYLED_ITEM('',(#2946),#2947);
+#941=STYLED_ITEM('',(#2948),#2949);
+#942=STYLED_ITEM('',(#2950),#2951);
+#943=STYLED_ITEM('',(#2952),#2953);
+#944=STYLED_ITEM('',(#2954),#2955);
+#945=STYLED_ITEM('',(#2956),#2957);
+#946=STYLED_ITEM('',(#2958),#2959);
+#947=STYLED_ITEM('',(#2960),#2961);
+#948=STYLED_ITEM('',(#2962),#2963);
+#949=STYLED_ITEM('',(#2964),#2965);
+#950=STYLED_ITEM('',(#2966),#2967);
+#951=STYLED_ITEM('',(#2968),#2969);
+#952=STYLED_ITEM('',(#2970),#2971);
+#953=STYLED_ITEM('',(#2972),#2973);
+#954=STYLED_ITEM('',(#2974),#2975);
+#955=STYLED_ITEM('',(#2976),#2977);
+#956=STYLED_ITEM('',(#2978),#2979);
+#957=STYLED_ITEM('',(#2980),#2981);
+#958=STYLED_ITEM('',(#2982),#2983);
+#959=STYLED_ITEM('',(#2984),#2985);
+#960=STYLED_ITEM('',(#2986),#2987);
+#961=STYLED_ITEM('',(#2988),#2989);
+#962=STYLED_ITEM('',(#2990),#2991);
+#963=STYLED_ITEM('',(#2992),#2993);
+#964=STYLED_ITEM('',(#2994),#2995);
+#965=STYLED_ITEM('',(#2996),#2997);
+#966=STYLED_ITEM('',(#2998),#2999);
+#967=STYLED_ITEM('',(#3000),#3001);
+#968=STYLED_ITEM('',(#3002),#3003);
+#969=STYLED_ITEM('',(#3004),#3005);
+#970=STYLED_ITEM('',(#3006),#3007);
+#971=STYLED_ITEM('',(#3008),#3009);
+#972=STYLED_ITEM('',(#3010),#3011);
+#973=STYLED_ITEM('',(#3012),#3013);
+#974=STYLED_ITEM('',(#3014),#3015);
+#975=STYLED_ITEM('',(#3016),#3017);
+#976=STYLED_ITEM('',(#3018),#3019);
+#977=STYLED_ITEM('',(#3020),#3021);
+#978=STYLED_ITEM('',(#3022),#3023);
+#979=STYLED_ITEM('',(#3024),#3025);
+#980=STYLED_ITEM('',(#3026),#3027);
+#981=STYLED_ITEM('',(#3028),#3029);
+#982=STYLED_ITEM('',(#3030),#3031);
+#983=STYLED_ITEM('',(#3032),#3033);
+#984=STYLED_ITEM('',(#3034),#3035);
+#985=STYLED_ITEM('',(#3036),#3037);
+#986=STYLED_ITEM('',(#3038),#3039);
+#987=STYLED_ITEM('',(#3040),#3041);
+#988=STYLED_ITEM('',(#3042),#3043);
+#989=STYLED_ITEM('',(#3044),#3045);
+#990=STYLED_ITEM('',(#3046),#3047);
+#991=STYLED_ITEM('',(#3048),#3049);
+#992=STYLED_ITEM('',(#3050),#3051);
+#993=STYLED_ITEM('',(#3052),#3053);
+#994=STYLED_ITEM('',(#3054),#3055);
+#995=STYLED_ITEM('',(#3056),#3057);
+#996=STYLED_ITEM('',(#3058),#3059);
+#997=STYLED_ITEM('',(#3060),#3061);
+#998=STYLED_ITEM('',(#3062),#3063);
+#999=STYLED_ITEM('',(#3064),#3065);
+#1000=STYLED_ITEM('',(#3066),#3067);
+#1001=STYLED_ITEM('',(#3068),#3069);
+#1002=STYLED_ITEM('',(#3070),#3071);
+#1003=STYLED_ITEM('',(#3072),#3073);
+#1004=STYLED_ITEM('',(#3074),#3075);
+#1005=STYLED_ITEM('',(#3076),#3077);
+#1006=STYLED_ITEM('',(#3078),#3079);
+#1007=STYLED_ITEM('',(#3080),#3081);
+#1008=STYLED_ITEM('',(#3082),#3083);
+#1009=STYLED_ITEM('',(#3084),#3085);
+#1010=STYLED_ITEM('',(#3086),#3087);
+#1011=STYLED_ITEM('',(#3088),#3089);
+#1012=STYLED_ITEM('',(#3090),#3091);
+#1013=STYLED_ITEM('',(#3092),#3093);
+#1014=STYLED_ITEM('',(#3094),#3095);
+#1015=STYLED_ITEM('',(#3096),#3097);
+#1016=STYLED_ITEM('',(#3098),#3099);
+#1017=STYLED_ITEM('',(#3100),#3101);
+#1018=STYLED_ITEM('',(#3102),#3103);
+#1019=STYLED_ITEM('',(#3104),#3105);
+#1020=STYLED_ITEM('',(#3106),#3107);
+#1021=STYLED_ITEM('',(#3108),#3109);
+#1022=STYLED_ITEM('',(#3110),#3111);
+#1023=STYLED_ITEM('',(#3112),#3113);
+#1024=STYLED_ITEM('',(#3114),#3115);
+#1025=STYLED_ITEM('',(#3116),#3117);
+#1026=STYLED_ITEM('',(#3118),#3119);
+#1027=STYLED_ITEM('',(#3120),#3121);
+#1028=STYLED_ITEM('',(#3122),#3123);
+#1029=STYLED_ITEM('',(#3124),#3125);
+#1030=STYLED_ITEM('',(#3126),#3127);
+#1031=STYLED_ITEM('',(#3128),#3129);
+#1032=STYLED_ITEM('',(#3130),#3131);
+#1033=STYLED_ITEM('',(#3132),#3133);
+#1034=STYLED_ITEM('',(#3134),#3135);
+#1035=STYLED_ITEM('',(#3136),#3137);
+#1036=STYLED_ITEM('',(#3138),#3139);
+#1037=STYLED_ITEM('',(#3140),#3141);
+#1038=STYLED_ITEM('',(#3142),#3143);
+#1039=STYLED_ITEM('',(#3144),#3145);
+#1040=STYLED_ITEM('',(#3146),#3147);
+#1041=STYLED_ITEM('',(#3148),#3149);
+#1042=STYLED_ITEM('',(#3150),#3151);
+#1043=STYLED_ITEM('',(#3152),#3153);
+#1044=STYLED_ITEM('',(#3154),#3155);
+#1045=STYLED_ITEM('',(#3156),#3157);
+#1046=STYLED_ITEM('',(#3158),#3159);
+#1047=STYLED_ITEM('',(#3160),#3161);
+#1048=STYLED_ITEM('',(#3162),#3163);
+#1049=STYLED_ITEM('',(#3164),#3165);
+#1050=STYLED_ITEM('',(#3166),#3167);
+#1051=STYLED_ITEM('',(#3168),#3169);
+#1052=STYLED_ITEM('',(#3170),#3171);
+#1053=STYLED_ITEM('',(#3172),#3173);
+#1054=STYLED_ITEM('',(#3174),#3175);
+#1055=STYLED_ITEM('',(#3176),#3177);
+#1056=STYLED_ITEM('',(#3178),#3179);
+#1057=STYLED_ITEM('',(#3180),#3181);
+#1058=STYLED_ITEM('',(#3182),#3183);
+#1059=STYLED_ITEM('',(#3184),#3185);
+#1060=STYLED_ITEM('',(#3186),#3187);
+#1061=STYLED_ITEM('',(#3188),#3189);
+#1062=STYLED_ITEM('',(#3190),#3191);
+#1063=STYLED_ITEM('',(#3192),#3193);
+#1064=STYLED_ITEM('',(#3194),#3195);
+#1065=STYLED_ITEM('',(#3196),#3197);
+#1066=STYLED_ITEM('',(#3198),#3199);
+#1067=STYLED_ITEM('',(#3200),#3201);
+#1068=STYLED_ITEM('',(#3202),#3203);
+#1069=STYLED_ITEM('',(#3204),#3205);
+#1070=STYLED_ITEM('',(#3206),#3207);
+#1071=STYLED_ITEM('',(#3208),#3209);
+#1072=STYLED_ITEM('',(#3210),#3211);
+#1073=STYLED_ITEM('',(#3212),#3213);
+#1074=STYLED_ITEM('',(#3214),#3215);
+#1075=STYLED_ITEM('',(#3216),#3217);
+#1076=APPLICATION_CONTEXT(' ');
+#1077=PRODUCT_CATEGORY('part','NONE');
+#1078=PRODUCT_RELATED_PRODUCT_CATEGORY('detail',' ',(#3218));
+#1079=PRODUCT_DEFINITION_SHAPE('NONE','NONE',#3219);
+#1080=ADVANCED_BREP_SHAPE_REPRESENTATION('1',(#1115,#3220),#9);
+#1081=ADVANCED_BREP_SHAPE_REPRESENTATION('2',(#3189,#3221),#9);
+#1082=ADVANCED_BREP_SHAPE_REPRESENTATION('3',(#3203,#3222),#9);
+#1083=ADVANCED_BREP_SHAPE_REPRESENTATION('4',(#3217,#3223),#9);
+#1086=UNCERTAINTY_MEASURE_WITH_UNIT(LENGTH_MEASURE(1.0E-006),#1088,'','');
+#1088= (CONVERSION_BASED_UNIT('MILLIMETRE',#3226)LENGTH_UNIT()NAMED_UNIT(#3229));
+#1089= (NAMED_UNIT(#3231)PLANE_ANGLE_UNIT()SI_UNIT($,.RADIAN.));
+#1090= (NAMED_UNIT(#3231)SOLID_ANGLE_UNIT()SI_UNIT($,.STERADIAN.));
+#1092=PRESENTATION_STYLE_ASSIGNMENT((#3237));
+#1093=ADVANCED_FACE('',(#3238),#3239,.T.);
+#1094=PRESENTATION_STYLE_ASSIGNMENT((#3240));
+#1095=ADVANCED_FACE('',(#3241),#3242,.T.);
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+#304=STYLED_ITEM('',(#1589),#1590);
+#305=STYLED_ITEM('',(#1591),#1592);
+#306=STYLED_ITEM('',(#1593),#1594);
+#307=STYLED_ITEM('',(#1595),#1596);
+#308=STYLED_ITEM('',(#1597),#1598);
+#309=STYLED_ITEM('',(#1599),#1600);
+#310=STYLED_ITEM('',(#1601),#1602);
+#311=STYLED_ITEM('',(#1603),#1604);
+#312=STYLED_ITEM('',(#1605),#1606);
+#313=STYLED_ITEM('',(#1607),#1608);
+#314=STYLED_ITEM('',(#1609),#1610);
+#315=STYLED_ITEM('',(#1611),#1612);
+#316=STYLED_ITEM('',(#1613),#1614);
+#317=STYLED_ITEM('',(#1615),#1616);
+#318=STYLED_ITEM('',(#1617),#1618);
+#319=STYLED_ITEM('',(#1619),#1620);
+#320=STYLED_ITEM('',(#1621),#1622);
+#321=STYLED_ITEM('',(#1623),#1624);
+#322=STYLED_ITEM('',(#1625),#1626);
+#323=STYLED_ITEM('',(#1627),#1628);
+#324=STYLED_ITEM('',(#1629),#1630);
+#325=STYLED_ITEM('',(#1631),#1632);
+#326=STYLED_ITEM('',(#1633),#1634);
+#327=STYLED_ITEM('',(#1635),#1636);
+#328=STYLED_ITEM('',(#1637),#1638);
+#329=STYLED_ITEM('',(#1639),#1640);
+#330=STYLED_ITEM('',(#1641),#1642);
+#331=STYLED_ITEM('',(#1643),#1644);
+#332=STYLED_ITEM('',(#1645),#1646);
+#333=STYLED_ITEM('',(#1647),#1648);
+#334=STYLED_ITEM('',(#1649),#1650);
+#335=STYLED_ITEM('',(#1651),#1652);
+#336=STYLED_ITEM('',(#1653),#1654);
+#337=STYLED_ITEM('',(#1655),#1656);
+#338=STYLED_ITEM('',(#1657),#1658);
+#339=STYLED_ITEM('',(#1659),#1660);
+#340=STYLED_ITEM('',(#1661),#1662);
+#341=STYLED_ITEM('',(#1663),#1664);
+#342=STYLED_ITEM('',(#1665),#1666);
+#343=STYLED_ITEM('',(#1667),#1668);
+#344=STYLED_ITEM('',(#1669),#1670);
+#345=STYLED_ITEM('',(#1671),#1672);
+#346=STYLED_ITEM('',(#1673),#1674);
+#347=STYLED_ITEM('',(#1675),#1676);
+#348=STYLED_ITEM('',(#1677),#1678);
+#349=STYLED_ITEM('',(#1679),#1680);
+#350=STYLED_ITEM('',(#1681),#1682);
+#351=STYLED_ITEM('',(#1683),#1684);
+#352=STYLED_ITEM('',(#1685),#1686);
+#353=STYLED_ITEM('',(#1687),#1688);
+#354=STYLED_ITEM('',(#1689),#1690);
+#355=STYLED_ITEM('',(#1691),#1692);
+#356=STYLED_ITEM('',(#1693),#1694);
+#357=STYLED_ITEM('',(#1695),#1696);
+#358=STYLED_ITEM('',(#1697),#1698);
+#359=STYLED_ITEM('',(#1699),#1700);
+#360=STYLED_ITEM('',(#1701),#1702);
+#361=STYLED_ITEM('',(#1703),#1704);
+#362=STYLED_ITEM('',(#1705),#1706);
+#363=STYLED_ITEM('',(#1707),#1708);
+#364=STYLED_ITEM('',(#1709),#1710);
+#365=STYLED_ITEM('',(#1711),#1712);
+#366=STYLED_ITEM('',(#1713),#1714);
+#367=STYLED_ITEM('',(#1715),#1716);
+#368=STYLED_ITEM('',(#1717),#1718);
+#369=STYLED_ITEM('',(#1719),#1720);
+#370=STYLED_ITEM('',(#1721),#1722);
+#371=STYLED_ITEM('',(#1723),#1724);
+#372=STYLED_ITEM('',(#1725),#1726);
+#373=STYLED_ITEM('',(#1727),#1728);
+#374=STYLED_ITEM('',(#1729),#1730);
+#375=STYLED_ITEM('',(#1731),#1732);
+#376=STYLED_ITEM('',(#1733),#1734);
+#377=STYLED_ITEM('',(#1735),#1736);
+#378=STYLED_ITEM('',(#1737),#1738);
+#379=STYLED_ITEM('',(#1739),#1740);
+#380=STYLED_ITEM('',(#1741),#1742);
+#381=STYLED_ITEM('',(#1743),#1744);
+#382=STYLED_ITEM('',(#1745),#1746);
+#383=STYLED_ITEM('',(#1747),#1748);
+#384=STYLED_ITEM('',(#1749),#1750);
+#385=STYLED_ITEM('',(#1751),#1752);
+#386=STYLED_ITEM('',(#1753),#1754);
+#387=STYLED_ITEM('',(#1755),#1756);
+#388=STYLED_ITEM('',(#1757),#1758);
+#389=STYLED_ITEM('',(#1759),#1760);
+#390=STYLED_ITEM('',(#1761),#1762);
+#391=STYLED_ITEM('',(#1763),#1764);
+#392=STYLED_ITEM('',(#1765),#1766);
+#393=STYLED_ITEM('',(#1767),#1768);
+#394=STYLED_ITEM('',(#1769),#1770);
+#395=STYLED_ITEM('',(#1771),#1772);
+#396=STYLED_ITEM('',(#1773),#1774);
+#397=STYLED_ITEM('',(#1775),#1776);
+#398=STYLED_ITEM('',(#1777),#1778);
+#399=STYLED_ITEM('',(#1779),#1780);
+#400=STYLED_ITEM('',(#1781),#1782);
+#401=STYLED_ITEM('',(#1783),#1784);
+#402=STYLED_ITEM('',(#1785),#1786);
+#403=STYLED_ITEM('',(#1787),#1788);
+#404=STYLED_ITEM('',(#1789),#1790);
+#405=STYLED_ITEM('',(#1791),#1792);
+#406=STYLED_ITEM('',(#1793),#1794);
+#407=STYLED_ITEM('',(#1795),#1796);
+#408=STYLED_ITEM('',(#1797),#1798);
+#409=STYLED_ITEM('',(#1799),#1800);
+#410=STYLED_ITEM('',(#1801),#1802);
+#411=STYLED_ITEM('',(#1803),#1804);
+#412=STYLED_ITEM('',(#1805),#1806);
+#413=STYLED_ITEM('',(#1807),#1808);
+#414=STYLED_ITEM('',(#1809),#1810);
+#415=STYLED_ITEM('',(#1811),#1812);
+#416=STYLED_ITEM('',(#1813),#1814);
+#417=STYLED_ITEM('',(#1815),#1816);
+#418=STYLED_ITEM('',(#1817),#1818);
+#419=STYLED_ITEM('',(#1819),#1820);
+#420=STYLED_ITEM('',(#1821),#1822);
+#421=STYLED_ITEM('',(#1823),#1824);
+#422=STYLED_ITEM('',(#1825),#1826);
+#423=STYLED_ITEM('',(#1827),#1828);
+#424=STYLED_ITEM('',(#1829),#1830);
+#425=STYLED_ITEM('',(#1831),#1832);
+#426=STYLED_ITEM('',(#1833),#1834);
+#427=STYLED_ITEM('',(#1835),#1836);
+#428=STYLED_ITEM('',(#1837),#1838);
+#429=STYLED_ITEM('',(#1839),#1840);
+#430=STYLED_ITEM('',(#1841),#1842);
+#431=STYLED_ITEM('',(#1843),#1844);
+#432=STYLED_ITEM('',(#1845),#1846);
+#433=STYLED_ITEM('',(#1847),#1848);
+#434=STYLED_ITEM('',(#1849),#1850);
+#435=STYLED_ITEM('',(#1851),#1852);
+#436=STYLED_ITEM('',(#1853),#1854);
+#437=STYLED_ITEM('',(#1855),#1856);
+#438=STYLED_ITEM('',(#1857),#1858);
+#439=STYLED_ITEM('',(#1859),#1860);
+#440=STYLED_ITEM('',(#1861),#1862);
+#441=STYLED_ITEM('',(#1863),#1864);
+#442=STYLED_ITEM('',(#1865),#1866);
+#443=STYLED_ITEM('',(#1867),#1868);
+#444=STYLED_ITEM('',(#1869),#1870);
+#445=STYLED_ITEM('',(#1871),#1872);
+#446=STYLED_ITEM('',(#1873),#1874);
+#447=STYLED_ITEM('',(#1875),#1876);
+#448=STYLED_ITEM('',(#1877),#1878);
+#449=STYLED_ITEM('',(#1879),#1880);
+#450=STYLED_ITEM('',(#1881),#1882);
+#451=STYLED_ITEM('',(#1883),#1884);
+#452=STYLED_ITEM('',(#1885),#1886);
+#453=STYLED_ITEM('',(#1887),#1888);
+#454=STYLED_ITEM('',(#1889),#1890);
+#455=STYLED_ITEM('',(#1891),#1892);
+#456=STYLED_ITEM('',(#1893),#1894);
+#457=STYLED_ITEM('',(#1895),#1896);
+#458=STYLED_ITEM('',(#1897),#1898);
+#459=STYLED_ITEM('',(#1899),#1900);
+#460=STYLED_ITEM('',(#1901),#1902);
+#461=STYLED_ITEM('',(#1903),#1904);
+#462=STYLED_ITEM('',(#1905),#1906);
+#463=STYLED_ITEM('',(#1907),#1908);
+#464=STYLED_ITEM('',(#1909),#1910);
+#465=STYLED_ITEM('',(#1911),#1912);
+#466=STYLED_ITEM('',(#1913),#1914);
+#467=STYLED_ITEM('',(#1915),#1916);
+#468=STYLED_ITEM('',(#1917),#1918);
+#469=STYLED_ITEM('',(#1919),#1920);
+#470=STYLED_ITEM('',(#1921),#1922);
+#471=STYLED_ITEM('',(#1923),#1924);
+#472=STYLED_ITEM('',(#1925),#1926);
+#473=STYLED_ITEM('',(#1927),#1928);
+#474=STYLED_ITEM('',(#1929),#1930);
+#475=STYLED_ITEM('',(#1931),#1932);
+#476=STYLED_ITEM('',(#1933),#1934);
+#477=STYLED_ITEM('',(#1935),#1936);
+#478=STYLED_ITEM('',(#1937),#1938);
+#479=STYLED_ITEM('',(#1939),#1940);
+#480=STYLED_ITEM('',(#1941),#1942);
+#481=STYLED_ITEM('',(#1943),#1944);
+#482=STYLED_ITEM('',(#1945),#1946);
+#483=STYLED_ITEM('',(#1947),#1948);
+#484=STYLED_ITEM('',(#1949),#1950);
+#485=STYLED_ITEM('',(#1951),#1952);
+#486=STYLED_ITEM('',(#1953),#1954);
+#487=STYLED_ITEM('',(#1955),#1956);
+#488=STYLED_ITEM('',(#1957),#1958);
+#489=STYLED_ITEM('',(#1959),#1960);
+#490=STYLED_ITEM('',(#1961),#1962);
+#491=STYLED_ITEM('',(#1963),#1964);
+#492=STYLED_ITEM('',(#1965),#1966);
+#493=STYLED_ITEM('',(#1967),#1968);
+#494=STYLED_ITEM('',(#1969),#1970);
+#495=STYLED_ITEM('',(#1971),#1972);
+#496=STYLED_ITEM('',(#1973),#1974);
+#497=STYLED_ITEM('',(#1975),#1976);
+#498=STYLED_ITEM('',(#1977),#1978);
+#499=STYLED_ITEM('',(#1979),#1980);
+#500=STYLED_ITEM('',(#1981),#1982);
+#501=STYLED_ITEM('',(#1983),#1984);
+#502=STYLED_ITEM('',(#1985),#1986);
+#503=STYLED_ITEM('',(#1987),#1988);
+#504=STYLED_ITEM('',(#1989),#1990);
+#505=STYLED_ITEM('',(#1991),#1992);
+#506=STYLED_ITEM('',(#1993),#1994);
+#507=STYLED_ITEM('',(#1995),#1996);
+#508=STYLED_ITEM('',(#1997),#1998);
+#509=STYLED_ITEM('',(#1999),#2000);
+#510=STYLED_ITEM('',(#2001),#2002);
+#511=STYLED_ITEM('',(#2003),#2004);
+#512=STYLED_ITEM('',(#2005),#2006);
+#513=STYLED_ITEM('',(#2007),#2008);
+#514=STYLED_ITEM('',(#2009),#2010);
+#515=STYLED_ITEM('',(#2011),#2012);
+#516=STYLED_ITEM('',(#2013),#2014);
+#517=STYLED_ITEM('',(#2015),#2016);
+#518=STYLED_ITEM('',(#2017),#2018);
+#519=STYLED_ITEM('',(#2019),#2020);
+#520=STYLED_ITEM('',(#2021),#2022);
+#521=STYLED_ITEM('',(#2023),#2024);
+#522=STYLED_ITEM('',(#2025),#2026);
+#523=STYLED_ITEM('',(#2027),#2028);
+#524=STYLED_ITEM('',(#2029),#2030);
+#525=STYLED_ITEM('',(#2031),#2032);
+#526=STYLED_ITEM('',(#2033),#2034);
+#527=STYLED_ITEM('',(#2035),#2036);
+#528=STYLED_ITEM('',(#2037),#2038);
+#529=STYLED_ITEM('',(#2039),#2040);
+#530=STYLED_ITEM('',(#2041),#2042);
+#531=STYLED_ITEM('',(#2043),#2044);
+#532=STYLED_ITEM('',(#2045),#2046);
+#533=STYLED_ITEM('',(#2047),#2048);
+#534=STYLED_ITEM('',(#2049),#2050);
+#535=STYLED_ITEM('',(#2051),#2052);
+#536=STYLED_ITEM('',(#2053),#2054);
+#537=STYLED_ITEM('',(#2055),#2056);
+#538=STYLED_ITEM('',(#2057),#2058);
+#539=STYLED_ITEM('',(#2059),#2060);
+#540=STYLED_ITEM('',(#2061),#2062);
+#541=STYLED_ITEM('',(#2063),#2064);
+#542=STYLED_ITEM('',(#2065),#2066);
+#543=STYLED_ITEM('',(#2067),#2068);
+#544=STYLED_ITEM('',(#2069),#2070);
+#545=STYLED_ITEM('',(#2071),#2072);
+#546=STYLED_ITEM('',(#2073),#2074);
+#547=STYLED_ITEM('',(#2075),#2076);
+#548=STYLED_ITEM('',(#2077),#2078);
+#549=STYLED_ITEM('',(#2079),#2080);
+#550=STYLED_ITEM('',(#2081),#2082);
+#551=STYLED_ITEM('',(#2083),#2084);
+#552=STYLED_ITEM('',(#2085),#2086);
+#553=STYLED_ITEM('',(#2087),#2088);
+#554=STYLED_ITEM('',(#2089),#2090);
+#555=STYLED_ITEM('',(#2091),#2092);
+#556=STYLED_ITEM('',(#2093),#2094);
+#557=STYLED_ITEM('',(#2095),#2096);
+#558=STYLED_ITEM('',(#2097),#2098);
+#559=STYLED_ITEM('',(#2099),#2100);
+#560=STYLED_ITEM('',(#2101),#2102);
+#561=STYLED_ITEM('',(#2103),#2104);
+#562=STYLED_ITEM('',(#2105),#2106);
+#563=STYLED_ITEM('',(#2107),#2108);
+#564=STYLED_ITEM('',(#2109),#2110);
+#565=STYLED_ITEM('',(#2111),#2112);
+#566=STYLED_ITEM('',(#2113),#2114);
+#567=STYLED_ITEM('',(#2115),#2116);
+#568=STYLED_ITEM('',(#2117),#2118);
+#569=STYLED_ITEM('',(#2119),#2120);
+#570=STYLED_ITEM('',(#2121),#2122);
+#571=STYLED_ITEM('',(#2123),#2124);
+#572=STYLED_ITEM('',(#2125),#2126);
+#573=STYLED_ITEM('',(#2127),#2128);
+#574=STYLED_ITEM('',(#2129),#2130);
+#575=STYLED_ITEM('',(#2131),#2132);
+#576=STYLED_ITEM('',(#2133),#2134);
+#577=STYLED_ITEM('',(#2135),#2136);
+#578=STYLED_ITEM('',(#2137),#2138);
+#579=STYLED_ITEM('',(#2139),#2140);
+#580=STYLED_ITEM('',(#2141),#2142);
+#581=STYLED_ITEM('',(#2143),#2144);
+#582=STYLED_ITEM('',(#2145),#2146);
+#583=STYLED_ITEM('',(#2147),#2148);
+#584=STYLED_ITEM('',(#2149),#2150);
+#585=STYLED_ITEM('',(#2151),#2152);
+#586=STYLED_ITEM('',(#2153),#2154);
+#587=STYLED_ITEM('',(#2155),#2156);
+#588=STYLED_ITEM('',(#2157),#2158);
+#589=STYLED_ITEM('',(#2159),#2160);
+#590=STYLED_ITEM('',(#2161),#2162);
+#591=STYLED_ITEM('',(#2163),#2164);
+#592=STYLED_ITEM('',(#2165),#2166);
+#593=STYLED_ITEM('',(#2167),#2168);
+#594=STYLED_ITEM('',(#2169),#2170);
+#595=STYLED_ITEM('',(#2171),#2172);
+#596=STYLED_ITEM('',(#2173),#2174);
+#597=STYLED_ITEM('',(#2175),#2176);
+#598=STYLED_ITEM('',(#2177),#2178);
+#599=STYLED_ITEM('',(#2179),#2180);
+#600=STYLED_ITEM('',(#2181),#2182);
+#601=STYLED_ITEM('',(#2183),#2184);
+#602=STYLED_ITEM('',(#2185),#2186);
+#603=STYLED_ITEM('',(#2187),#2188);
+#604=STYLED_ITEM('',(#2189),#2190);
+#605=STYLED_ITEM('',(#2191),#2192);
+#606=STYLED_ITEM('',(#2193),#2194);
+#607=STYLED_ITEM('',(#2195),#2196);
+#608=STYLED_ITEM('',(#2197),#2198);
+#609=STYLED_ITEM('',(#2199),#2200);
+#610=STYLED_ITEM('',(#2201),#2202);
+#611=STYLED_ITEM('',(#2203),#1137);
+#612=STYLED_ITEM('',(#2204),#1138);
+#613=STYLED_ITEM('',(#2205),#2206);
+#614=STYLED_ITEM('',(#2207),#2208);
+#615=STYLED_ITEM('',(#2209),#2210);
+#616=STYLED_ITEM('',(#2211),#2212);
+#617=STYLED_ITEM('',(#2213),#2214);
+#618=STYLED_ITEM('',(#2215),#2216);
+#619=STYLED_ITEM('',(#2217),#2218);
+#620=STYLED_ITEM('',(#2219),#2220);
+#621=STYLED_ITEM('',(#2221),#2222);
+#622=STYLED_ITEM('',(#2223),#2224);
+#623=STYLED_ITEM('',(#2225),#2226);
+#624=STYLED_ITEM('',(#2227),#2228);
+#625=STYLED_ITEM('',(#2229),#2230);
+#626=STYLED_ITEM('',(#2231),#2232);
+#627=STYLED_ITEM('',(#2233),#2234);
+#628=STYLED_ITEM('',(#2235),#2236);
+#629=STYLED_ITEM('',(#2237),#2238);
+#630=STYLED_ITEM('',(#2239),#2240);
+#631=STYLED_ITEM('',(#2241),#2242);
+#632=STYLED_ITEM('',(#2243),#2244);
+#633=STYLED_ITEM('',(#2245),#2246);
+#634=STYLED_ITEM('',(#2247),#2248);
+#635=STYLED_ITEM('',(#2249),#2250);
+#636=STYLED_ITEM('',(#2251),#2252);
+#637=STYLED_ITEM('',(#2253),#2254);
+#638=STYLED_ITEM('',(#2255),#2256);
+#639=STYLED_ITEM('',(#2257),#2258);
+#640=STYLED_ITEM('',(#2259),#2260);
+#641=STYLED_ITEM('',(#2261),#2262);
+#642=STYLED_ITEM('',(#2263),#2264);
+#643=STYLED_ITEM('',(#2265),#2266);
+#644=STYLED_ITEM('',(#2267),#2268);
+#645=STYLED_ITEM('',(#2269),#2270);
+#646=STYLED_ITEM('',(#2271),#2272);
+#647=STYLED_ITEM('',(#2273),#2274);
+#648=STYLED_ITEM('',(#2275),#2276);
+#649=STYLED_ITEM('',(#2277),#2278);
+#650=STYLED_ITEM('',(#2279),#2280);
+#651=STYLED_ITEM('',(#2281),#2282);
+#652=STYLED_ITEM('',(#2283),#2284);
+#653=STYLED_ITEM('',(#2285),#2286);
+#654=STYLED_ITEM('',(#2287),#2288);
+#655=STYLED_ITEM('',(#2289),#2290);
+#656=STYLED_ITEM('',(#2291),#2292);
+#657=STYLED_ITEM('',(#2293),#2294);
+#658=STYLED_ITEM('',(#2295),#2296);
+#659=STYLED_ITEM('',(#2297),#2298);
+#660=STYLED_ITEM('',(#2299),#2300);
+#661=STYLED_ITEM('',(#2301),#2302);
+#662=STYLED_ITEM('',(#2303),#2304);
+#663=STYLED_ITEM('',(#2305),#2306);
+#664=STYLED_ITEM('',(#2307),#2308);
+#665=STYLED_ITEM('',(#2309),#2310);
+#666=STYLED_ITEM('',(#2311),#2312);
+#667=STYLED_ITEM('',(#2313),#2314);
+#668=STYLED_ITEM('',(#2315),#2316);
+#669=STYLED_ITEM('',(#2317),#2318);
+#670=STYLED_ITEM('',(#2319),#2320);
+#671=STYLED_ITEM('',(#2321),#2322);
+#672=STYLED_ITEM('',(#2323),#2324);
+#673=STYLED_ITEM('',(#2325),#2326);
+#674=STYLED_ITEM('',(#2327),#2328);
+#675=STYLED_ITEM('',(#2329),#2330);
+#676=STYLED_ITEM('',(#2331),#2332);
+#677=STYLED_ITEM('',(#2333),#2334);
+#678=STYLED_ITEM('',(#2335),#2336);
+#679=STYLED_ITEM('',(#2337),#2338);
+#680=STYLED_ITEM('',(#2339),#2340);
+#681=STYLED_ITEM('',(#2341),#2342);
+#682=STYLED_ITEM('',(#2343),#2344);
+#683=STYLED_ITEM('',(#2345),#2346);
+#684=STYLED_ITEM('',(#2347),#2348);
+#685=STYLED_ITEM('',(#2349),#2350);
+#686=STYLED_ITEM('',(#2351),#2352);
+#687=STYLED_ITEM('',(#2353),#2354);
+#688=STYLED_ITEM('',(#2355),#2356);
+#689=STYLED_ITEM('',(#2357),#2358);
+#690=STYLED_ITEM('',(#2359),#2360);
+#691=STYLED_ITEM('',(#2361),#2362);
+#692=STYLED_ITEM('',(#2363),#2364);
+#693=STYLED_ITEM('',(#2365),#2366);
+#694=STYLED_ITEM('',(#2367),#2368);
+#695=STYLED_ITEM('',(#2369),#2370);
+#696=STYLED_ITEM('',(#2371),#2372);
+#697=STYLED_ITEM('',(#2373),#2374);
+#698=STYLED_ITEM('',(#2375),#2376);
+#699=STYLED_ITEM('',(#2377),#2378);
+#700=STYLED_ITEM('',(#2379),#2380);
+#701=STYLED_ITEM('',(#2381),#2382);
+#702=STYLED_ITEM('',(#2383),#2384);
+#703=STYLED_ITEM('',(#2385),#2386);
+#704=STYLED_ITEM('',(#2387),#2388);
+#705=STYLED_ITEM('',(#2389),#2390);
+#706=STYLED_ITEM('',(#2391),#2392);
+#707=STYLED_ITEM('',(#2393),#2394);
+#708=STYLED_ITEM('',(#2395),#2396);
+#709=STYLED_ITEM('',(#2397),#2398);
+#710=STYLED_ITEM('',(#2399),#2400);
+#711=STYLED_ITEM('',(#2401),#2402);
+#712=STYLED_ITEM('',(#2403),#2404);
+#713=STYLED_ITEM('',(#2405),#2406);
+#714=STYLED_ITEM('',(#2407),#2408);
+#715=STYLED_ITEM('',(#2409),#2410);
+#716=STYLED_ITEM('',(#2411),#2412);
+#717=STYLED_ITEM('',(#2413),#2414);
+#718=STYLED_ITEM('',(#2415),#2416);
+#719=STYLED_ITEM('',(#2417),#2418);
+#720=STYLED_ITEM('',(#2419),#2420);
+#721=STYLED_ITEM('',(#2421),#2422);
+#722=STYLED_ITEM('',(#2423),#2424);
+#723=STYLED_ITEM('',(#2425),#2426);
+#724=STYLED_ITEM('',(#2427),#2428);
+#725=STYLED_ITEM('',(#2429),#2430);
+#726=STYLED_ITEM('',(#2431),#2432);
+#727=STYLED_ITEM('',(#2433),#2434);
+#728=STYLED_ITEM('',(#2435),#2436);
+#729=STYLED_ITEM('',(#2437),#2438);
+#730=STYLED_ITEM('',(#2439),#2440);
+#731=STYLED_ITEM('',(#2441),#2442);
+#732=STYLED_ITEM('',(#2443),#2444);
+#733=STYLED_ITEM('',(#2445),#2446);
+#734=STYLED_ITEM('',(#2447),#2448);
+#735=STYLED_ITEM('',(#2449),#2450);
+#736=STYLED_ITEM('',(#2451),#2452);
+#737=STYLED_ITEM('',(#2453),#2454);
+#738=STYLED_ITEM('',(#2455),#2456);
+#739=STYLED_ITEM('',(#2457),#2458);
+#740=STYLED_ITEM('',(#2459),#2460);
+#741=STYLED_ITEM('',(#2461),#2462);
+#742=STYLED_ITEM('',(#2463),#2464);
+#743=STYLED_ITEM('',(#2465),#2466);
+#744=STYLED_ITEM('',(#2467),#2468);
+#745=STYLED_ITEM('',(#2469),#2470);
+#746=STYLED_ITEM('',(#2471),#2472);
+#747=STYLED_ITEM('',(#2473),#2474);
+#748=STYLED_ITEM('',(#2475),#2476);
+#749=STYLED_ITEM('',(#2477),#2478);
+#750=STYLED_ITEM('',(#2479),#2480);
+#751=STYLED_ITEM('',(#2481),#2482);
+#752=STYLED_ITEM('',(#2483),#2484);
+#753=STYLED_ITEM('',(#2485),#2486);
+#754=STYLED_ITEM('',(#2487),#2488);
+#755=STYLED_ITEM('',(#2489),#2490);
+#756=STYLED_ITEM('',(#2491),#2492);
+#757=STYLED_ITEM('',(#2493),#2494);
+#758=STYLED_ITEM('',(#2495),#2496);
+#759=STYLED_ITEM('',(#2497),#2498);
+#760=STYLED_ITEM('',(#2499),#2500);
+#761=STYLED_ITEM('',(#2501),#2502);
+#762=STYLED_ITEM('',(#2503),#2504);
+#763=STYLED_ITEM('',(#2505),#2506);
+#764=STYLED_ITEM('',(#2507),#2508);
+#765=STYLED_ITEM('',(#2509),#2510);
+#766=STYLED_ITEM('',(#2511),#2512);
+#767=STYLED_ITEM('',(#2513),#2514);
+#768=STYLED_ITEM('',(#2515),#2516);
+#769=STYLED_ITEM('',(#2517),#2518);
+#770=STYLED_ITEM('',(#2519),#2520);
+#771=STYLED_ITEM('',(#2521),#2522);
+#772=STYLED_ITEM('',(#2523),#2524);
+#773=STYLED_ITEM('',(#2525),#2526);
+#774=STYLED_ITEM('',(#2527),#2528);
+#775=STYLED_ITEM('',(#2529),#2530);
+#776=STYLED_ITEM('',(#2531),#2532);
+#777=STYLED_ITEM('',(#2533),#2534);
+#778=STYLED_ITEM('',(#2535),#2536);
+#779=STYLED_ITEM('',(#2537),#2538);
+#780=STYLED_ITEM('',(#2539),#2540);
+#781=STYLED_ITEM('',(#2541),#2542);
+#782=STYLED_ITEM('',(#2543),#2544);
+#783=STYLED_ITEM('',(#2545),#2546);
+#784=STYLED_ITEM('',(#2547),#2548);
+#785=STYLED_ITEM('',(#2549),#2550);
+#786=STYLED_ITEM('',(#2551),#2552);
+#787=STYLED_ITEM('',(#2553),#2554);
+#788=STYLED_ITEM('',(#2555),#2556);
+#789=STYLED_ITEM('',(#2557),#2558);
+#790=STYLED_ITEM('',(#2559),#2560);
+#791=STYLED_ITEM('',(#2561),#2562);
+#792=STYLED_ITEM('',(#2563),#2564);
+#793=STYLED_ITEM('',(#2565),#2566);
+#794=STYLED_ITEM('',(#2567),#2568);
+#795=STYLED_ITEM('',(#2569),#2570);
+#796=STYLED_ITEM('',(#2571),#2572);
+#797=STYLED_ITEM('',(#2573),#2574);
+#798=STYLED_ITEM('',(#2575),#2576);
+#799=STYLED_ITEM('',(#2577),#2578);
+#800=STYLED_ITEM('',(#2579),#2580);
+#801=STYLED_ITEM('',(#2581),#2582);
+#802=STYLED_ITEM('',(#2583),#2584);
+#803=STYLED_ITEM('',(#2585),#2586);
+#804=STYLED_ITEM('',(#2587),#2588);
+#805=STYLED_ITEM('',(#2589),#2590);
+#806=STYLED_ITEM('',(#2591),#2592);
+#807=STYLED_ITEM('',(#2593),#2594);
+#808=STYLED_ITEM('',(#2595),#2596);
+#809=STYLED_ITEM('',(#2597),#2598);
+#810=STYLED_ITEM('',(#2599),#2600);
+#811=STYLED_ITEM('',(#2601),#2602);
+#812=STYLED_ITEM('',(#2603),#2604);
+#813=STYLED_ITEM('',(#2605),#2606);
+#814=STYLED_ITEM('',(#2607),#2608);
+#815=STYLED_ITEM('',(#2609),#2610);
+#816=STYLED_ITEM('',(#2611),#2612);
+#817=STYLED_ITEM('',(#2613),#2614);
+#818=STYLED_ITEM('',(#2615),#2616);
+#819=STYLED_ITEM('',(#2617),#2618);
+#820=STYLED_ITEM('',(#2619),#2620);
+#821=STYLED_ITEM('',(#2621),#2622);
+#822=STYLED_ITEM('',(#2623),#2624);
+#823=STYLED_ITEM('',(#2625),#2626);
+#824=STYLED_ITEM('',(#2627),#2628);
+#825=STYLED_ITEM('',(#2629),#2630);
+#826=STYLED_ITEM('',(#2631),#2632);
+#827=STYLED_ITEM('',(#2633),#2634);
+#828=STYLED_ITEM('',(#2635),#2636);
+#829=STYLED_ITEM('',(#2637),#2638);
+#830=STYLED_ITEM('',(#2639),#2640);
+#831=STYLED_ITEM('',(#2641),#1146);
+#832=STYLED_ITEM('',(#2642),#2643);
+#833=STYLED_ITEM('',(#2644),#2645);
+#834=STYLED_ITEM('',(#2646),#2647);
+#835=STYLED_ITEM('',(#2648),#2649);
+#836=STYLED_ITEM('',(#2650),#2651);
+#837=STYLED_ITEM('',(#2652),#2653);
+#838=STYLED_ITEM('',(#2654),#2655);
+#839=STYLED_ITEM('',(#2656),#2657);
+#840=STYLED_ITEM('',(#2658),#2659);
+#841=STYLED_ITEM('',(#2660),#2661);
+#842=STYLED_ITEM('',(#2662),#2663);
+#843=STYLED_ITEM('',(#2664),#2665);
+#844=STYLED_ITEM('',(#2666),#2667);
+#845=STYLED_ITEM('',(#2668),#2669);
+#846=STYLED_ITEM('',(#2670),#2671);
+#847=STYLED_ITEM('',(#2672),#2673);
+#848=STYLED_ITEM('',(#2674),#2675);
+#849=STYLED_ITEM('',(#2676),#2677);
+#850=STYLED_ITEM('',(#2678),#2679);
+#851=STYLED_ITEM('',(#2680),#2681);
+#852=STYLED_ITEM('',(#2682),#2683);
+#853=STYLED_ITEM('',(#2684),#2685);
+#854=STYLED_ITEM('',(#2686),#2687);
+#855=STYLED_ITEM('',(#2688),#2689);
+#856=STYLED_ITEM('',(#2690),#2691);
+#857=STYLED_ITEM('',(#2692),#2693);
+#858=STYLED_ITEM('',(#2694),#2695);
+#859=STYLED_ITEM('',(#2696),#2697);
+#860=STYLED_ITEM('',(#2698),#2699);
+#861=STYLED_ITEM('',(#2700),#2701);
+#862=STYLED_ITEM('',(#2702),#2703);
+#863=STYLED_ITEM('',(#2704),#2705);
+#864=STYLED_ITEM('',(#2706),#2707);
+#865=STYLED_ITEM('',(#2708),#1154);
+#866=STYLED_ITEM('',(#2709),#2710);
+#867=STYLED_ITEM('',(#2711),#2712);
+#868=STYLED_ITEM('',(#2713),#2714);
+#869=STYLED_ITEM('',(#2715),#2716);
+#870=STYLED_ITEM('',(#2717),#2718);
+#871=STYLED_ITEM('',(#2719),#2720);
+#872=STYLED_ITEM('',(#2721),#2722);
+#873=STYLED_ITEM('',(#2723),#2724);
+#874=STYLED_ITEM('',(#2725),#2726);
+#875=STYLED_ITEM('',(#2727),#2728);
+#876=STYLED_ITEM('',(#2729),#2730);
+#877=STYLED_ITEM('',(#2731),#2732);
+#878=STYLED_ITEM('',(#2733),#2734);
+#879=STYLED_ITEM('',(#2735),#2736);
+#880=STYLED_ITEM('',(#2737),#2738);
+#881=STYLED_ITEM('',(#2739),#2740);
+#882=STYLED_ITEM('',(#2741),#2742);
+#883=STYLED_ITEM('',(#2743),#2744);
+#884=STYLED_ITEM('',(#2745),#2746);
+#885=STYLED_ITEM('',(#2747),#2748);
+#886=STYLED_ITEM('',(#2749),#2750);
+#887=STYLED_ITEM('',(#2751),#2752);
+#888=STYLED_ITEM('',(#2753),#2754);
+#889=STYLED_ITEM('',(#2755),#2756);
+#890=STYLED_ITEM('',(#2757),#2758);
+#891=STYLED_ITEM('',(#2759),#2760);
+#892=STYLED_ITEM('',(#2761),#2762);
+#893=STYLED_ITEM('',(#2763),#2764);
+#894=STYLED_ITEM('',(#2765),#2766);
+#895=STYLED_ITEM('',(#2767),#2768);
+#896=STYLED_ITEM('',(#2769),#2770);
+#897=STYLED_ITEM('',(#2771),#2772);
+#898=STYLED_ITEM('',(#2773),#2774);
+#899=STYLED_ITEM('',(#2775),#2776);
+#900=STYLED_ITEM('',(#2777),#2778);
+#901=STYLED_ITEM('',(#2779),#2780);
+#902=STYLED_ITEM('',(#2781),#2782);
+#903=STYLED_ITEM('',(#2783),#2784);
+#904=STYLED_ITEM('',(#2785),#2786);
+#905=STYLED_ITEM('',(#2787),#2788);
+#906=STYLED_ITEM('',(#2789),#2790);
+#907=STYLED_ITEM('',(#2791),#2792);
+#908=STYLED_ITEM('',(#2793),#2794);
+#909=STYLED_ITEM('',(#2795),#2796);
+#910=STYLED_ITEM('',(#2797),#2798);
+#911=STYLED_ITEM('',(#2799),#2800);
+#912=STYLED_ITEM('',(#2801),#2802);
+#913=STYLED_ITEM('',(#2803),#2804);
+#914=STYLED_ITEM('',(#2805),#2806);
+#915=STYLED_ITEM('',(#2807),#1162);
+#916=STYLED_ITEM('',(#2808),#2809);
+#917=STYLED_ITEM('',(#2810),#2811);
+#918=STYLED_ITEM('',(#2812),#2813);
+#919=STYLED_ITEM('',(#2814),#2815);
+#920=STYLED_ITEM('',(#2816),#2817);
+#921=STYLED_ITEM('',(#2818),#2819);
+#922=STYLED_ITEM('',(#2820),#2821);
+#923=STYLED_ITEM('',(#2822),#2823);
+#924=STYLED_ITEM('',(#2824),#2825);
+#925=STYLED_ITEM('',(#2826),#2827);
+#926=STYLED_ITEM('',(#2828),#2829);
+#927=STYLED_ITEM('',(#2830),#2831);
+#928=STYLED_ITEM('',(#2832),#2833);
+#929=STYLED_ITEM('',(#2834),#2835);
+#930=STYLED_ITEM('',(#2836),#2837);
+#931=STYLED_ITEM('',(#2838),#2839);
+#932=STYLED_ITEM('',(#2840),#2841);
+#933=STYLED_ITEM('',(#2842),#2843);
+#934=STYLED_ITEM('',(#2844),#2845);
+#935=STYLED_ITEM('',(#2846),#2847);
+#936=STYLED_ITEM('',(#2848),#2849);
+#937=STYLED_ITEM('',(#2850),#2851);
+#938=STYLED_ITEM('',(#2852),#2853);
+#939=STYLED_ITEM('',(#2854),#2855);
+#940=STYLED_ITEM('',(#2856),#2857);
+#941=STYLED_ITEM('',(#2858),#2859);
+#942=STYLED_ITEM('',(#2860),#2861);
+#943=STYLED_ITEM('',(#2862),#2863);
+#944=STYLED_ITEM('',(#2864),#2865);
+#945=STYLED_ITEM('',(#2866),#2867);
+#946=STYLED_ITEM('',(#2868),#2869);
+#947=STYLED_ITEM('',(#2870),#2871);
+#948=STYLED_ITEM('',(#2872),#2873);
+#949=STYLED_ITEM('',(#2874),#2875);
+#950=STYLED_ITEM('',(#2876),#2877);
+#951=STYLED_ITEM('',(#2878),#2879);
+#952=STYLED_ITEM('',(#2880),#2881);
+#953=STYLED_ITEM('',(#2882),#2883);
+#954=STYLED_ITEM('',(#2884),#2885);
+#955=STYLED_ITEM('',(#2886),#2887);
+#956=STYLED_ITEM('',(#2888),#2889);
+#957=STYLED_ITEM('',(#2890),#2891);
+#958=STYLED_ITEM('',(#2892),#2893);
+#959=STYLED_ITEM('',(#2894),#2895);
+#960=STYLED_ITEM('',(#2896),#2897);
+#961=STYLED_ITEM('',(#2898),#2899);
+#962=STYLED_ITEM('',(#2900),#2901);
+#963=STYLED_ITEM('',(#2902),#2903);
+#964=STYLED_ITEM('',(#2904),#2905);
+#965=STYLED_ITEM('',(#2906),#2907);
+#966=STYLED_ITEM('',(#2908),#2909);
+#967=STYLED_ITEM('',(#2910),#2911);
+#968=STYLED_ITEM('',(#2912),#2913);
+#969=STYLED_ITEM('',(#2914),#2915);
+#970=STYLED_ITEM('',(#2916),#2917);
+#971=STYLED_ITEM('',(#2918),#2919);
+#972=STYLED_ITEM('',(#2920),#2921);
+#973=STYLED_ITEM('',(#2922),#2923);
+#974=STYLED_ITEM('',(#2924),#2925);
+#975=STYLED_ITEM('',(#2926),#2927);
+#976=STYLED_ITEM('',(#2928),#2929);
+#977=STYLED_ITEM('',(#2930),#2931);
+#978=STYLED_ITEM('',(#2932),#2933);
+#979=STYLED_ITEM('',(#2934),#2935);
+#980=STYLED_ITEM('',(#2936),#2937);
+#981=STYLED_ITEM('',(#2938),#2939);
+#982=STYLED_ITEM('',(#2940),#2941);
+#983=STYLED_ITEM('',(#2942),#2943);
+#984=STYLED_ITEM('',(#2944),#2945);
+#985=STYLED_ITEM('',(#2946),#2947);
+#986=STYLED_ITEM('',(#2948),#2949);
+#987=STYLED_ITEM('',(#2950),#2951);
+#988=STYLED_ITEM('',(#2952),#2953);
+#989=STYLED_ITEM('',(#2954),#2955);
+#990=STYLED_ITEM('',(#2956),#2957);
+#991=STYLED_ITEM('',(#2958),#2959);
+#992=STYLED_ITEM('',(#2960),#2961);
+#993=STYLED_ITEM('',(#2962),#2963);
+#994=STYLED_ITEM('',(#2964),#2965);
+#995=STYLED_ITEM('',(#2966),#2967);
+#996=STYLED_ITEM('',(#2968),#2969);
+#997=STYLED_ITEM('',(#2970),#2971);
+#998=STYLED_ITEM('',(#2972),#2973);
+#999=STYLED_ITEM('',(#2974),#1170);
+#1000=STYLED_ITEM('',(#2975),#2976);
+#1001=STYLED_ITEM('',(#2977),#2978);
+#1002=STYLED_ITEM('',(#2979),#2980);
+#1003=STYLED_ITEM('',(#2981),#2982);
+#1004=STYLED_ITEM('',(#2983),#2984);
+#1005=STYLED_ITEM('',(#2985),#2986);
+#1006=STYLED_ITEM('',(#2987),#2988);
+#1007=STYLED_ITEM('',(#2989),#2990);
+#1008=STYLED_ITEM('',(#2991),#2992);
+#1009=STYLED_ITEM('',(#2993),#2994);
+#1010=STYLED_ITEM('',(#2995),#2996);
+#1011=STYLED_ITEM('',(#2997),#2998);
+#1012=STYLED_ITEM('',(#2999),#3000);
+#1013=STYLED_ITEM('',(#3001),#3002);
+#1014=STYLED_ITEM('',(#3003),#3004);
+#1015=STYLED_ITEM('',(#3005),#3006);
+#1016=STYLED_ITEM('',(#3007),#3008);
+#1017=STYLED_ITEM('',(#3009),#3010);
+#1018=STYLED_ITEM('',(#3011),#3012);
+#1019=STYLED_ITEM('',(#3013),#3014);
+#1020=STYLED_ITEM('',(#3015),#3016);
+#1021=STYLED_ITEM('',(#3017),#3018);
+#1022=STYLED_ITEM('',(#3019),#3020);
+#1023=STYLED_ITEM('',(#3021),#3022);
+#1024=STYLED_ITEM('',(#3023),#3024);
+#1025=STYLED_ITEM('',(#3025),#3026);
+#1026=STYLED_ITEM('',(#3027),#3028);
+#1027=STYLED_ITEM('',(#3029),#3030);
+#1028=STYLED_ITEM('',(#3031),#3032);
+#1029=STYLED_ITEM('',(#3033),#3034);
+#1030=STYLED_ITEM('',(#3035),#3036);
+#1031=STYLED_ITEM('',(#3037),#3038);
+#1032=STYLED_ITEM('',(#3039),#3040);
+#1033=STYLED_ITEM('',(#3041),#3042);
+#1034=STYLED_ITEM('',(#3043),#3044);
+#1035=STYLED_ITEM('',(#3045),#3046);
+#1036=STYLED_ITEM('',(#3047),#3048);
+#1037=STYLED_ITEM('',(#3049),#3050);
+#1038=STYLED_ITEM('',(#3051),#3052);
+#1039=STYLED_ITEM('',(#3053),#3054);
+#1040=STYLED_ITEM('',(#3055),#3056);
+#1041=STYLED_ITEM('',(#3057),#3058);
+#1042=STYLED_ITEM('',(#3059),#3060);
+#1043=STYLED_ITEM('',(#3061),#3062);
+#1044=STYLED_ITEM('',(#3063),#3064);
+#1045=STYLED_ITEM('',(#3065),#3066);
+#1046=STYLED_ITEM('',(#3067),#3068);
+#1047=STYLED_ITEM('',(#3069),#3070);
+#1048=STYLED_ITEM('',(#3071),#3072);
+#1049=STYLED_ITEM('',(#3073),#3074);
+#1050=STYLED_ITEM('',(#3075),#3076);
+#1051=STYLED_ITEM('',(#3077),#3078);
+#1052=STYLED_ITEM('',(#3079),#3080);
+#1053=STYLED_ITEM('',(#3081),#3082);
+#1054=STYLED_ITEM('',(#3083),#3084);
+#1055=STYLED_ITEM('',(#3085),#3086);
+#1056=STYLED_ITEM('',(#3087),#3088);
+#1057=STYLED_ITEM('',(#3089),#3090);
+#1058=STYLED_ITEM('',(#3091),#3092);
+#1059=STYLED_ITEM('',(#3093),#3094);
+#1060=STYLED_ITEM('',(#3095),#3096);
+#1061=STYLED_ITEM('',(#3097),#3098);
+#1062=STYLED_ITEM('',(#3099),#3100);
+#1063=STYLED_ITEM('',(#3101),#3102);
+#1064=STYLED_ITEM('',(#3103),#3104);
+#1065=STYLED_ITEM('',(#3105),#3106);
+#1066=STYLED_ITEM('',(#3107),#3108);
+#1067=STYLED_ITEM('',(#3109),#3110);
+#1068=STYLED_ITEM('',(#3111),#3112);
+#1069=STYLED_ITEM('',(#3113),#3114);
+#1070=STYLED_ITEM('',(#3115),#3116);
+#1071=STYLED_ITEM('',(#3117),#3118);
+#1072=STYLED_ITEM('',(#3119),#3120);
+#1073=STYLED_ITEM('',(#3121),#3122);
+#1074=STYLED_ITEM('',(#3123),#3124);
+#1075=STYLED_ITEM('',(#3125),#3126);
+#1076=STYLED_ITEM('',(#3127),#3128);
+#1077=STYLED_ITEM('',(#3129),#3130);
+#1078=STYLED_ITEM('',(#3131),#3132);
+#1079=STYLED_ITEM('',(#3133),#3134);
+#1080=STYLED_ITEM('',(#3135),#3136);
+#1081=STYLED_ITEM('',(#3137),#3138);
+#1082=STYLED_ITEM('',(#3139),#3140);
+#1083=STYLED_ITEM('',(#3141),#3142);
+#1084=STYLED_ITEM('',(#3143),#3144);
+#1085=STYLED_ITEM('',(#3145),#3146);
+#1086=STYLED_ITEM('',(#3147),#3148);
+#1087=STYLED_ITEM('',(#3149),#3150);
+#1088=STYLED_ITEM('',(#3151),#3152);
+#1089=STYLED_ITEM('',(#3153),#3154);
+#1090=STYLED_ITEM('',(#3155),#3156);
+#1091=STYLED_ITEM('',(#3157),#3158);
+#1092=STYLED_ITEM('',(#3159),#3160);
+#1093=STYLED_ITEM('',(#3161),#3162);
+#1094=STYLED_ITEM('',(#3163),#3164);
+#1095=STYLED_ITEM('',(#3165),#3166);
+#1096=STYLED_ITEM('',(#3167),#3168);
+#1097=STYLED_ITEM('',(#3169),#3170);
+#1098=STYLED_ITEM('',(#3171),#3172);
+#1099=STYLED_ITEM('',(#3173),#3174);
+#1100=STYLED_ITEM('',(#3175),#3176);
+#1101=STYLED_ITEM('',(#3177),#3178);
+#1102=STYLED_ITEM('',(#3179),#3180);
+#1103=STYLED_ITEM('',(#3181),#3182);
+#1104=STYLED_ITEM('',(#3183),#3184);
+#1105=STYLED_ITEM('',(#3185),#3186);
+#1106=STYLED_ITEM('',(#3187),#3188);
+#1107=STYLED_ITEM('',(#3189),#3190);
+#1108=STYLED_ITEM('',(#3191),#3192);
+#1109=STYLED_ITEM('',(#3193),#3194);
+#1110=STYLED_ITEM('',(#3195),#3196);
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--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitignore
@@ -0,0 +1,40 @@
+# Prerequisites
+*.d
+
+# Compiled Object files
+*.slo
+*.lo
+*.o
+*.obj
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+*.dll
+
+# Fortran module files
+*.mod
+*.smod
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
+*.lib
+
+# Executables
+*.exe
+*.out
+*.app
+.vs/
+Release/
+Debug/
+drivers/signinf.cmd
+drivers/verifyinf.cmd
+*.zip
+*.componentinfo.xml
+jlink.*
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab-ci.yml b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab-ci.yml
new file mode 100644
index 000000000..f85ced048
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab-ci.yml
@@ -0,0 +1,30 @@
+stages:
+  - ClearCore
+
+ClearCore:
+  stage: ClearCore
+  script:
+  - cd %USERPROFILE%\AppData\Local\Arduino15\packages\ClearCore
+  - rmdir /S /Q hardware\sam\1.0.1
+  - rmdir /S /Q hardware\sam\1.0.2
+  - rmdir /S /Q hardware\sam\1.0.3
+  - rmdir /S /Q hardware\sam\1.0.4
+  - rmdir /S /Q hardware\sam\1.0.5
+  - rmdir /S /Q hardware\sam\1.0.6
+  - rmdir /S /Q hardware\sam\1.0.7
+  - rmdir /S /Q hardware\sam\1.0.8
+  - rmdir /S /Q hardware\sam\1.0.9
+  - rmdir /S /Q hardware\sam\1.0.10
+  - rmdir /S /Q hardware\sam\1.0.11
+  - rmdir /S /Q hardware\sam\1.0.12
+  - rmdir /S /Q hardware\sam\1.0.13
+  - git clone git@git-server.teknic.com:CustomerPackages/ClearCore_Arduino.git --branch "%CI_COMMIT_REF_NAME%" --single-branch "hardware\sam\1.0.13" || ( git clone git@git-server.teknic.com:CustomerPackages/ClearCore_Arduino.git --branch "develop" --single-branch "hardware\sam\1.0.13" )
+  - git clone git@git-server.teknic.com:CustomerPackages/libClearCore.git --branch "%CI_COMMIT_REF_NAME%" --single-branch "hardware\sam\1.0.13\Teknic\libClearCore" || ( git clone git@git-server.teknic.com:CustomerPackages/libClearCore.git --branch "develop" --single-branch "hardware\sam\1.0.13\Teknic\libClearCore" )
+  - git clone git@git-server.teknic.com:CustomerPackages/same53.git --branch "master" --single-branch "hardware\sam\1.0.13\variants\clearcore\Third Party\SAME53"
+  - git clone git@git-server.teknic.com:CustomerPackages/LwIP.git --branch "master" --single-branch "hardware\sam\1.0.13\Teknic\LwIP"
+  - git clone git@git-server.teknic.com:CustomerPackages/uf2-builder.git --branch "master" --single-branch "hardware\sam\1.0.13\Teknic\Tools\uf2-builder"
+  - cd "hardware\sam\1.0.13"
+  - mkdir TestSketch
+  - echo void setup(){} void loop(){} > TestSketch/TestSketch.ino
+  - atmelstudio.exe ClearCore.atsln /build debug /out output.txt || ( type output.txt & EXIT /B 1 )
+  - python build.py -c -b
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Bug.md b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Bug.md
new file mode 100644
index 000000000..4ac1e9717
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Bug.md
@@ -0,0 +1,32 @@
+**Summary**
+
+(Summarize the bug encountered concisely)
+
+
+**What is the current bug behavior?**
+
+(What actually happens)
+
+
+**What is the expected correct behavior?**
+
+(What you should see instead)
+
+
+**Steps to reproduce**
+
+(How one can reproduce the issue - this is very important)
+
+
+**Example code**
+
+```
+(If possible, please include example code that exhibits the problematic behaviour)
+```
+
+**Relevant logs and/or screenshots**
+
+(Paste any relevant logs)
+
+
+/label ~Bug 
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Discussion.md b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Discussion.md
new file mode 100644
index 000000000..89c5618bd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Discussion.md
@@ -0,0 +1,15 @@
+**Summary**
+
+(Summarize the topic for the discussion)
+
+
+**Who is required to participate?**
+
+
+**What is the estimated time for the discussion?**
+
+
+**Provide any additional details or background information for the discussion**
+
+
+/label ~Discussion
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Feature Request.md b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Feature Request.md
new file mode 100644
index 000000000..23540c153
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Feature Request.md	
@@ -0,0 +1,30 @@
+**Summary**
+
+(Summarize the feature requested concisely)
+
+
+**Who is the requesting Customer?**
+
+	Customer name 	- 
+	Project Name 	-
+	Expected Annual volume -
+
+
+**What is the closest current solution with our products?**
+
+
+**What is the likely project outcome if the feature is not implemented?**
+
+
+**What is the "best" expected solution?**
+
+
+
+
+**Relevant logs and/or screenshots**
+
+(Please attach any relevant screenshots/pictures/documentation describing the desired behavior etc.)
+
+
+
+/label ~Feature Request
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Text Change.md b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Text Change.md
new file mode 100644
index 000000000..7fefa1e17
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitlab/issue_templates/Text Change.md	
@@ -0,0 +1,21 @@
+**Location**
+
+(Where is the location of the intended change?)
+
+
+**What is the error?**
+
+(Specifically state what the problem with the text is whether it's a typo, a grammatical error, a formatting error, or just unclear text descriptions)
+
+
+**Steps to reproduce?**
+
+(If there was any setup to illicit the typo/formatting error/grammatical error, list them)
+
+
+**What is the suggested correction?**
+
+(Specifically state your suggestion to correct the spelling or make the text more clear)
+
+
+/label ~Text Change 
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitmodules b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitmodules
new file mode 100644
index 000000000..274608597
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "Teknic"]
+	path = Teknic
+	url = https://github.com/Teknic-Inc/ClearCore-library.git
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/ClearCore.atsln b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/ClearCore.atsln
new file mode 100644
index 000000000..a3d86bbc4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/ClearCore.atsln
@@ -0,0 +1,49 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCoreArduino", "ClearCoreArduino.cppproj", "{DC06454F-445D-4E8C-A03E-22236431B9DE}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "Teknic\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "Teknic\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "TestSketch", "TestSketch\TestSketch.cppproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+	ProjectSection(ProjectDependencies) = postProject
+		{DC06454F-445D-4E8C-A03E-22236431B9DE} = {DC06454F-445D-4E8C-A03E-22236431B9DE}
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DC06454F-445D-4E8C-A03E-22236431B9DE}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DC06454F-445D-4E8C-A03E-22236431B9DE}.Debug|ARM.Build.0 = Debug|ARM
+		{DC06454F-445D-4E8C-A03E-22236431B9DE}.Release|ARM.ActiveCfg = Release|ARM
+		{DC06454F-445D-4E8C-A03E-22236431B9DE}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/ClearCoreArduino.cppproj b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/ClearCoreArduino.cppproj
new file mode 100644
index 000000000..7bf2b28a3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/ClearCoreArduino.cppproj
@@ -0,0 +1,876 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{dc06454f-445d-4e8c-a03e-22236431b9de}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>ClearCoreArduino</AssemblyName>
+    <Name>ClearCoreArduino</Name>
+    <RootNamespace>ClearCoreArduino</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>1</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data xmlns="">
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.40.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>
+    </avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>2000000</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>2000000</avrtoolinterfaceclock>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>4000000</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+        <JlinkConfigFile>C:\git\clearcore_atmelstudio.git\ClearCoreArduino\jlink.config</JlinkConfigFile>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+    <custom>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>4000000</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>
+        </InterfaceName>
+      </ToolOptions>
+      <ToolType>custom</ToolType>
+      <ToolNumber>
+      </ToolNumber>
+      <ToolName>Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\Teknic\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>False</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>USBCON</Value>
+      <Value>__CLEARCORE__</Value>
+      <Value>USB_CONFIG_POWER=0</Value>
+      <Value>__SAME53N19A__</Value>
+      <Value>ARM_MATH_CM4</Value>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>../cores/arduino</Value>
+      <Value>../cores/arduino/api</Value>
+      <Value>../variants/clearcore</Value>
+      <Value>../variants/clearcore/Third Party/SAME53/CMSIS/Device/Include</Value>
+      <Value>../Teknic/libClearCore/inc</Value>
+      <Value>../Teknic/LwIP/LwIP/port/include</Value>
+      <Value>../Teknic/LwIP/LwIP/src/include</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.optimization.DebugLevel>Default (-g2)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.warnings.ExtraWarnings>True</armgcc.compiler.warnings.ExtraWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>__CLEARCORE__</Value>
+      <Value>USBCON</Value>
+      <Value>USB_CONFIG_POWER=0</Value>
+      <Value>ARM_MATH_CM4</Value>
+      <Value>DEBUG</Value>
+      <Value>__FPU_PRESENT=1</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\cmsis\4.5.0\CMSIS\Include\</Value>
+      <Value>../cores/arduino</Value>
+      <Value>../cores/arduino/api</Value>
+      <Value>../variants/clearcore</Value>
+      <Value>../variants/clearcore/Third Party/SAME53/CMSIS/Device/Include</Value>
+      <Value>../Teknic/libClearCore/inc</Value>
+      <Value>../Teknic/LwIP/LwIP/src/include</Value>
+      <Value>../Teknic/LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.warnings.ExtraWarnings>True</armgcccpp.compiler.warnings.ExtraWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>arm_cortexM4lf_math</Value>
+      <Value>libm</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\cmsis\4.5.0\CMSIS\Include\</Value>
+      <Value>../variants/clearcore/linker_scripts/gcc</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.AssemblerFlags>--fpu=softvfp</armgcccpp.assembler.general.AssemblerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\cmsis\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\cmsis\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>
+    </PostBuildEvent>
+    <OutputFileName>libClearCoreArduino</OutputFileName>
+    <OutputFileExtension>.a</OutputFileExtension>
+    <OutputType>StaticLibrary</OutputType>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
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+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\dsu.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\eic.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\evsys.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\freqm.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\gclk.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\gmac.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\hmatrix.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\i2s.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\icm.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\mclk.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\nvmctrl.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\osc32kctrl.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\oscctrl.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\pac.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\pcc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\pdec.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\pm.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\port.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\pukcc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\qspi.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\ramecc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\rstc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\rtc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sdhc0.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sdhc1.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom0.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom1.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom2.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom3.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom4.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom5.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom6.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\sercom7.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\supc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc0.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc1.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc2.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc3.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc4.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc5.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc6.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tc7.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tcc0.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tcc1.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tcc2.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tcc3.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\tcc4.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\trng.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\usb.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\instance\wdt.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\pio\same53j18a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\pio\same53j19a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\pio\same53j20a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\pio\same53n19a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\pio\same53n20a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\sam.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\same53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\same53j18a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\same53j19a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\same53j20a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\same53n19a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\same53n20a.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\Third Party\SAME53\CMSIS\Device\Include\system_same53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\variant.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="variants\clearcore\variant.h">
+      <SubType>compile</SubType>
+    </Compile>
+  </ItemGroup>
+  <ItemGroup>
+    <None Include="variants\clearcore\linker_scripts\gcc\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="variants\clearcore\linker_scripts\gcc\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\Teknic\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\Teknic\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/README.md b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/README.md
new file mode 100644
index 000000000..cd93cdfad
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/README.md
@@ -0,0 +1,15 @@
+# ClearCore-Arduino-wrapper
+
+This repository contains the source code for the ClearCore Arduino Wrapper, which allows users to interact with a Teknic ClearCore using common Arduino functions.
+
+Instead of interfacing directly to the processor pins, the ClearCore Arduino Wrapper uses the ClearCore libraries and provides an interface to the ClearCore connectors. This leverages all of the ClearCore library features with the ease of programming in the Arduino IDE.
+
+Installation of the ClearCore board within the Arduino IDE should be performed using the Arduino board manager. This repository is intended for building new packages for use with the board manager.
+
+### Installers and Resources
+
+https://www.teknic.com/downloads/
+
+### Example Programs
+
+To help you quickly get started programming your ClearCore application, several ClearCore examples are included. Once you have the Teknic ClearCore selected as the active board, the Arduino File/Examples menu will include examples demonstrating how to use various features of the ClearCore, as well as the standard examples.
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/README.txt b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/README.txt
new file mode 100644
index 000000000..42e30f333
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/README.txt
@@ -0,0 +1,36 @@
+Code Style Tool Guide:
+
+================================================================================
+TL;DR
+    0. (Do this once for your system) Install cppcheck by downloading it from 
+        the interwebs.
+    1. Execute the run_[toolname].bat script from the desired project directory
+       (e.g. ClearCore/run_cppcheck.bat). cppcheck puts its suggestions in 
+       a file called issues.txt. Astyle just makes its changes without getting 
+       your permission.
+
+================================================================================
+Tool Overview:
+
+Astyle:     A syntax formatter that conforms to the C/C++ Style guide. (Yes,
+            it corrects your files for you, so be careful)
+            http://astyle.sourceforge.net/astyle.html
+
+            Astyle edits files to conform to the Software team's coding styles.
+            Its configuration file is in ClearCore/configuration. Astyle's
+            purpose is to make the code for the project look like it was all
+            written by one person. It does not change the meaning (semantics)
+            of what's going on. The extent of its changes is purely cosmetic.
+Cppcheck:   A semantic checker that makes sure you don't do something dumb
+            like plowing off the end of an array, or tickling null pointers.
+            http://cppcheck.sourceforge.net/
+            
+            NOTE: Cppcheck must be installed on your system by by downloading it 
+            from the interwebs. The other application is a standalone exe file.
+
+            Cppcheck doesn't care about how the code is formatted--that's
+            Astyle's job. Cppcheck does not make any changes for you.
+            It simply dumps its suggestions in a file called issues.txt 
+            (in the same directory you execute run_cppcheck.bat from). 
+            
+================================================================================
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/astyle.cfg b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/astyle.cfg
new file mode 100644
index 000000000..394428fe7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/astyle.cfg
@@ -0,0 +1,40 @@
+# Don't make copies of every file in the project
+--suffix=none 
+
+# Brace style
+--style=attach              # "same-line" braces
+--add-braces                # require braces on all blocks even if the contents
+                            # are a single line.
+#--break-one-line-headers    # annihilate things like if (foo) { bar(); }
+--break-closing-braces      # makes a newline between the end of an if
+                            # and its else.
+
+# Sane Indentation options
+# --indent-preproc-block
+--indent-switches
+
+# Pointer operator alignment
+--align-pointer=name        # make pointer ops touch the name-- *foo, &foo, etc.
+--align-reference=name      # make & and -> touch the name
+
+# General operator alignment
+--pad-oper                  # surround math operators with spaces on both sides
+--pad-comma                 # Make sure commas have a trailing space, and no
+                            # leading space.
+--pad-header                # Add a space between if/while/for and (. e.g.:
+                            # while(foo) { ...
+                            # becomes
+                            # while (foo) { ...
+
+# Whitespace options
+--indent=spaces=4           # tabstop = 4 spaces
+--convert-tabs              # substitute 4 spaces for tabs
+# --max-code-length=80        # enforce 80 characters maximum per line
+--break-after-logical       # make it so && or || ends the line if wrapping
+--unpad-paren               # Remove extra spaces around parenthesis
+                            # if ( ( bar() == baz ) ) { ...
+                            # becomes
+                            # if ((bar() == baz)) { ...
+#--break-blocks              # put whitespace lines around if/for/while blocks
+#--delete-empty-lines        # delete empty lines within a function or method
+                            # (except those inserted with break-blocks)
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/cppcheck_rules.xml b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/cppcheck_rules.xml
new file mode 100644
index 000000000..65557e8ee
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/cppcheck_rules.xml
@@ -0,0 +1,176 @@
+<?xml version="1.0"?>
+<!-- all.rule
+     This file contains all of the Teknic Software Team's custom cppcheck
+     rules. The value enclosed in <pattern> tags is a regular expression
+     that matches an undesirable section of the code. cppcheck preprocesses
+     the code before running analysis on it, so there will be no comments,
+     and no preprocessor directives. In addition, all of the cppcheck input is 
+     in a standardized padded format. This file does NOT enforce any concrete
+     syntax formatting rules.
+
+     @author: Cody Burrows -->
+
+
+<!-- Avoid using multiple inheritance, because it makes the code more difficult 
+     to understand. -->
+<rule version="1">
+    <pattern>class [^:]+ : [^{]*,[^{]* {</pattern>
+    <message>
+        <id>multipleInheritance</id>
+        <severity>style</severity>
+        <summary>Multiple Inheritance. Single inheritance is preferred; consider revising. </summary>
+    </message>
+</rule>
+
+<!-- Avoid using private inheritance, because it makes the code more difficult
+     to understand -->
+<rule version="1">
+    <pattern>class [^:]+ : [^{]*(private|protected)[^{]* {</pattern>
+    <message>
+        <id>nonpublicInheritance</id>
+        <severity>style</severity>
+        <summary>Non-public inheritance. Consider including a base class as a member instead.</summary>
+    </message>
+</rule>
+
+<!-- Avoid overloading the && (boolean AND) operator to prevent
+     mass confusion. -->
+<rule version="1">
+    <pattern>\boperator&amp;&amp; \(</pattern>
+    <message>
+        <id>overloadBooleanAnd</id>
+        <severity>error</severity>
+        <summary>Do not overload the &amp;&amp; (boolean AND) operator.</summary>
+    </message>
+</rule>
+
+<!-- Avoid overloading the || (boolean OR) operator to prevent 
+     mass confusion. -->
+<rule version="1">
+    <pattern>\boperator\|\| \(</pattern>
+    <message>
+        <id>overloadBooleanOR</id>
+        <severity>error</severity>
+        <summary>Do not overload the || (boolean OR) operator.</summary>
+    </message>
+</rule>
+
+<!-- Avoid overloading the & (bitwise AND) operator to prevent
+     mass confusion. -->
+<rule version="1">
+    <pattern>\boperator&amp; \(</pattern>
+    <message>
+        <id>overloadBitwiseAnd</id>
+        <severity>error</severity>
+        <summary>Do not overload the &amp; (bitwise AND) operator.</summary>
+    </message>
+</rule>
+
+<!-- Don't make user-defined literals. -->
+<rule version="1">
+    <pattern>\boperator &quot;&quot; [^{]+ {</pattern>
+    <message>
+        <id>userDefinedLiteral</id>
+        <severity>error</severity>
+        <summary>Please do not introduce user-defined literals.</summary>
+    </message>
+</rule>
+
+<!-- Don't overload the comma operator because scary and bad things will
+     happen. -->
+<rule version="1">
+    <pattern>\boperator, \(</pattern>
+    <message>
+        <id>overloadComma</id>
+        <severity>error</severity>
+        <summary>Do not overload the , (comma) operator.</summary>
+    </message>
+</rule>
+
+<!-- Self-explanatory. -->
+<rule version="1">
+    <pattern>\bgoto\b</pattern>
+    <message>
+        <id>usedGoto</id>
+        <severity>error</severity>
+        <summary>Are you kidding me? Do not use goto.</summary>
+    </message>
+</rule>
+
+<!-- Don't use continue unless you're using it in an otherwise empty loop. -->
+<rule version="1">
+    <pattern>(while|for|do)[^{]+{[^{;]+; continue ; }</pattern>
+    <message>
+        <id>continueInNonemptyLoop</id>
+        <severity>style</severity>
+        <summary>Continue statement in non-empty loop. Please only use continue statements for empty loops.</summary>
+    </message>
+</rule>
+
+<!-- Prevent empty while loops that do nothing. For completeness, add a single
+     continue statement. -->
+<rule version="1">
+    <pattern>while \([^{}]+\) { }</pattern>
+    <message>
+        <id>emptyWhile</id>
+        <severity>style</severity>
+        <summary>While loop with empty body. Please add a single continue statement to it.</summary>
+    </message>
+</rule>
+
+<!-- Use stdint.h types to make the size of the data more clear. -->
+<rule version="1">
+    <pattern>\blong\b</pattern>
+    <message>
+        <id>usedLongKeyword</id>
+        <severity>portability</severity>
+        <summary>Used long keyword. Please use types defined in stdint.h such as int32_t, uint64_t, etc.</summary>
+    </message>
+</rule>
+<rule version="1">
+    <pattern>\bshort\b</pattern>
+    <message>
+        <id>usedShortKeyword</id>
+        <severity>portability</severity>
+        <summary>Used short keyword. Please use types defined in stdint.h such as int8_t, uint16_t, etc.</summary>
+    </message>
+</rule>
+<rule version="1">
+    <pattern>\bint\b</pattern>
+    <message>
+        <id>usedIntKeyword</id>
+        <severity>portability</severity>
+        <summary>Used int keyword. Please use types defined in stdint.h such as int8_t, uint16_t, etc.</summary>
+    </message>
+</rule>
+<rule version="1">
+    <pattern>\bsize_t\b</pattern>
+    <message>
+        <id>usedIntKeyword</id>
+        <severity>portability</severity>
+        <summary>Used size_t keyword. Please use types defined in stdint.h such as int8_t, uint16_t, etc.</summary>
+    </message>
+</rule>
+
+<!-- Don't use break unless you're using it to separate switch statements. -->
+<!-- Can create false positives if cppcheck discards some syntax during its preprocessing step -->
+<!-- <rule version="1">
+    <pattern>\b(?!switch\b)\b\w+ \([^{]+\) {[^{]* break [^{]*}</pattern>
+    <message>
+        <id>breakOutsideSwitch</id>
+        <severity>style</severity>
+        <summary>Break used in a context other than a switch statement. Please only use break in switch statements.</summary>
+    </message>
+</rule> -->
+
+<!-- Always include a default case in switch statements. -->
+<!-- Sometimes creates false positives if there are no statements in the default case 
+     due to the preprocessed nature of the data cppcheck looks at -->
+<!-- <rule version="1">
+    <pattern>\bswitch \( [^{ ]+ \) {(?:(?!\bdefault\b).)*?}</pattern>
+    <message>
+        <id>switchMissingDefault</id>
+        <severity>style</severity>
+        <summary>Switch missing default case. Please add one.</summary>
+    </message>
+</rule> -->
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/cppcheck_suppressions.xml b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/cppcheck_suppressions.xml
new file mode 100644
index 000000000..eefb55c82
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/configuration/cppcheck_suppressions.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<suppressions>
+    <!-- It's a library, of course there will be "unused" functions -->
+    <suppress><id>unusedFunction</id></suppress>
+    
+    <!-- Don't show errors for cppcheck being dumb -->
+    <suppress><id>ConfigurationNotChecked</id></suppress>
+    
+    <!-- Don't complain about this -- sometimes the hardware requires this to signal certain events -->
+    <suppress><id>redundantAssignment</id></suppress>
+    <suppress><id>selfAssignment</id></suppress>
+    
+    <!-- Sometimes multiple inheritance IS preferred -->
+    <suppress><id>multipleInheritance</id></suppress>
+    
+    <!-- Arduino's codebase uses an insane amount of longs and ints, isn't worth it to go through and change them all. Comment these out to scan other projects -->
+    <suppress><id>usedLongKeyword</id></suppress>
+    <suppress><id>usedIntKeyword</id></suppress>
+</suppressions>
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/run_astyle.bat b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/run_astyle.bat
new file mode 100644
index 000000000..7d5634b73
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/run_astyle.bat
@@ -0,0 +1,8 @@
+SET version=1.0.12
+
+SET root_teknic="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\Teknic\libClearCore"
+SET root_atmel_examples="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\Teknic\Atmel_Examples"
+SET root_arduino_examples="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\libraries"
+SET root_arduino="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\cores\arduino"
+
+.\tools\AStyle.exe --options=configuration\astyle.cfg -r "%root_teknic%\inc\*.h" "%root_teknic%\src\*.cpp" "%root_teknic%\UnitTests\src\*.cpp" "%root_arduino%\*.h" "%root_arduino%\*.cpp" "%root_arduino_examples%\*.ino" "%root_atmel_examples%\*.cpp"
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/run_cppcheck.bat b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/run_cppcheck.bat
new file mode 100644
index 000000000..c60abba8a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/Style/run_cppcheck.bat
@@ -0,0 +1,28 @@
+SET version=1.0.12
+
+SET src="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\Teknic\libClearCore\src"
+SET inc="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\Teknic\libClearCore\inc"
+SET libClearCore_issues="cppCheck_issues_libClearCore.txt"
+
+SET unitTests="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\Teknic\libClearCore\UnitTests\src"
+SET unitTests_issues="cppCheck_issues_unitTests.txt"
+
+SET examples="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\Teknic\Atmel_Examples"
+SET examples_issues="cppCheck_issues_examples.txt"
+
+SET arduino_src="%LOCALAPPDATA%\Arduino15\packages\ClearCore\hardware\sam\%version%\cores\arduino"
+SET arduino_issues="cppCheck_issues_arduino.txt"
+
+SET cppCheck="C:\Program Files\Cppcheck\cppcheck.exe"
+
+mkdir clearcore_build_dir
+
+%cppCheck% -I "%inc%" --cppcheck-build-dir="clearcore_build_dir" --enable=all --rule-file="configuration\cppcheck_rules.xml" --output-file="%libClearCore_issues%" --suppress-xml="configuration\cppcheck_suppressions.xml" "%src%"
+
+%cppCheck% --cppcheck-build-dir="clearcore_build_dir" --enable=all --rule-file="configuration\cppcheck_rules.xml" --output-file="%unitTests_issues%" --suppress-xml="configuration\cppcheck_suppressions.xml" "%unitTests%"
+
+%cppCheck% --cppcheck-build-dir="clearcore_build_dir" --enable=all --rule-file="configuration\cppcheck_rules.xml" --output-file="%examples_issues%" --suppress-xml="configuration\cppcheck_suppressions.xml" "%examples%"
+
+%cppCheck% --cppcheck-build-dir="clearcore_build_dir" --enable=all --rule-file="configuration\cppcheck_rules.xml" --output-file="%arduino_issues%" --suppress-xml="configuration\cppcheck_suppressions.xml" "%arduino_src%"
+
+rmdir /s /q clearcore_build_dir
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..23d94fce6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/Device_Startup/startup_same53.c
@@ -0,0 +1,504 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/TestSketch.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/TestSketch.cpp
new file mode 100644
index 000000000..3fdb92d4b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/TestSketch.cpp
@@ -0,0 +1,19 @@
+#include "Arduino.h"
+#include "ClearCore.h"
+
+bool outputState = false;
+
+void setup() {
+    // Put your setup code here, it will run once:
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Toggle and write the digital output state.
+    outputState = !outputState;
+    digitalWrite(LED_BUILTIN, outputState);
+
+    // Wait a second, then repeat.
+    delay(1000);
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/TestSketch.cppproj b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/TestSketch.cppproj
new file mode 100644
index 000000000..f1760c304
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/TestSketch/TestSketch.cppproj
@@ -0,0 +1,284 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>TestSketch</AssemblyName>
+    <Name>TestSketch</Name>
+    <RootNamespace>TestSketch</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\Teknic\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.warnings.ExtraWarnings>True</armgcc.compiler.warnings.ExtraWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../Teknic/libClearCore/inc</Value>
+            <Value>../../Teknic/LwIP/LwIP/port/include</Value>
+            <Value>../../Teknic/LwIP/LwIP/src/include</Value>
+            <Value>../../cores/arduino</Value>
+            <Value>../../cores/arduino/api</Value>
+            <Value>../../variants/clearcore</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.warnings.ExtraWarnings>True</armgcccpp.compiler.warnings.ExtraWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>arm_cortexM4lf_math</Value>
+            <Value>libm</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>%24(ProjectDir)\Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\Teknic\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Default (-g2)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.warnings.ExtraWarnings>True</armgcc.compiler.warnings.ExtraWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../Teknic/libClearCore/inc</Value>
+            <Value>../../Teknic/LwIP/LwIP/port/include</Value>
+            <Value>../../Teknic/LwIP/LwIP/src/include</Value>
+            <Value>../../cores/arduino</Value>
+            <Value>../../cores/arduino/api</Value>
+            <Value>../../variants/clearcore</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.warnings.ExtraWarnings>True</armgcccpp.compiler.warnings.ExtraWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>arm_cortexM4lf_math</Value>
+            <Value>libm</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>%24(ProjectDir)\Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\Teknic\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="TestSketch.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\ClearCore-Arduino-wrapper\ClearCoreArduino.cppproj">
+      <Name>ClearCoreArduino</Name>
+      <Project>{dc06454f-445d-4e8c-a03e-22236431b9de}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\Teknic\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\Teknic\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/boards.txt b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/boards.txt
new file mode 100644
index 000000000..2096f4dcb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/boards.txt
@@ -0,0 +1,41 @@
+# See: http://code.google.com/p/arduino/wiki/Platforms
+
+menu.cpu=Processor
+
+##############################################################
+
+clearcore.name=Teknic ClearCore
+clearcore.vid.0=0x2890
+clearcore.pid.0=0x0022
+clearcore.vid.1=0x2890
+clearcore.pid.1=0x8022
+
+clearcore.upload.tool=bossac
+clearcore.upload.protocol=sam-ba
+clearcore.upload.maximum_size=507904
+clearcore.upload.use_1200bps_touch=true
+clearcore.upload.wait_for_upload_port=true
+clearcore.upload.native_usb=true
+clearcore.upload.offset=0x4000
+clearcore.tools.bossac.upload.params.verbose=-i -d -a
+
+clearcore.bootloader.tool=openocd
+clearcore.bootloader.unlock_bits=0x3F
+clearcore.bootloader.lock_bits=0x2F
+
+clearcore.build.mcu=cortex-m4
+clearcore.build.float=hard
+clearcore.build.fpu=fpv4-sp-d16
+clearcore.build.f_cpu=120000000L
+clearcore.build.vid=0x2890
+clearcore.build.pid=0x0022
+clearcore.build.usb_product="Teknic ClearCore"
+clearcore.build.usb_manufacturer="Teknic, Inc."
+clearcore.build.board=ARM_ClearCore
+clearcore.build.core=arduino
+clearcore.build.variant=clearcore
+clearcore.build.extra_flags={build.usb_flags} -lc -DDEBUG 
+clearcore.build.ldscript=linker_scripts/gcc/flash_with_bootloader.ld
+
+##############################################################
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/bootloader-ClearCore-v2.3.1-Teknic.4.bin b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/bootloader-ClearCore-v2.3.1-Teknic.4.bin
new file mode 100644
index 000000000..42ed3f1e7
Binary files /dev/null and b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/bootloader-ClearCore-v2.3.1-Teknic.4.bin differ
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/bootloader-ClearCore-v2.3.1-Teknic.4.elf b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/bootloader-ClearCore-v2.3.1-Teknic.4.elf
new file mode 100644
index 000000000..a0e86072b
Binary files /dev/null and b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/bootloader-ClearCore-v2.3.1-Teknic.4.elf differ
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/update-bootloader-ClearCore-v2.3.1-Teknic.4.uf2 b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/update-bootloader-ClearCore-v2.3.1-Teknic.4.uf2
new file mode 100644
index 000000000..956a9395f
Binary files /dev/null and b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/bootloader/update-bootloader-ClearCore-v2.3.1-Teknic.4.uf2 differ
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Arduino.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Arduino.h
new file mode 100644
index 000000000..825419245
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Arduino.h
@@ -0,0 +1,53 @@
+/*
+  Arduino.h - Main include file for the Arduino SDK
+  Copyright (c) 2014 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef Arduino_h
+#define Arduino_h
+
+#include <sam.h>
+#include <ArduinoAPI.h>
+
+#define clockCyclesPerMicrosecond() (SystemCoreClock / 1000000L)
+#define clockCyclesToMicroseconds(a) (((a) * 1000L) / (SystemCoreClock / 1000L))
+#define microsecondsToClockCycles(a) ((a) * (SystemCoreClock / 1000000L))
+
+#include "WVariant.h"
+#include "delay.h"
+
+typedef enum {
+    AR_INTERNAL,
+    AR_INTVCC0 = 2,     // 1/2 VDDANA
+    AR_INTVCC1 = 3,     // VDDANA
+    AR_EXTERNAL_A = 4,
+    AR_EXTERNAL_B = 5,
+    AR_EXTERNAL_C = 6,
+} eAnalogReference ;
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+void init(void);
+void delay(unsigned long ms);
+void setup(void);
+void loop(void);
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // Arduino_h
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Ethernet.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Ethernet.cpp
new file mode 100644
index 000000000..09a0ce35a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Ethernet.cpp
@@ -0,0 +1,163 @@
+/* Copyright 2018 Paul Stoffregen
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <Arduino.h>
+#include "Ethernet.h"
+#include "EthernetManager.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/dns.h"
+
+namespace ClearCore {
+extern EthernetManager &EthernetMgr;
+}
+
+int EthernetClass::begin(uint8_t *mac) {
+    (void)mac; // Disallow setting the MAC address.
+
+    ClearCore::EthernetMgr.Setup();
+
+    int dhcpSuccess = ClearCore::EthernetMgr.DhcpBegin();
+    if (dhcpSuccess) {
+        const ip_addr_t *dns = dns_getserver(0);
+        ClearCore::EthernetMgr.DnsIp(dns->addr);
+    }
+    return dhcpSuccess;
+}
+
+// Begin functions assume that the DNS server and/or gateway will be on the
+// same network with the provided IP with the last value being 1.
+void EthernetClass::begin(uint8_t *mac, IPAddress ip) {
+    IPAddress dns = IPAddress(ip[0], ip[1], ip[2], 1);
+    begin(mac, ip, dns);
+}
+
+void EthernetClass::begin(uint8_t *mac, IPAddress ip, IPAddress dns) {
+    IPAddress gateway = IPAddress(ip[0], ip[1], ip[2], 1);
+    begin(mac, ip, dns, gateway);
+}
+
+void EthernetClass::begin(uint8_t *mac, IPAddress ip, IPAddress dns,
+                          IPAddress gateway) {
+    IPAddress subnet(255, 255, 255, 0);
+    begin(mac, ip, dns, gateway, subnet);
+}
+
+void EthernetClass::begin(uint8_t *mac, IPAddress ip, IPAddress dns,
+                          IPAddress gateway, IPAddress subnet) {
+    (void)mac; // Disallow setting the MAC address.
+
+    ClearCore::EthernetMgr.Setup();
+
+    ClearCore::EthernetMgr.LocalIp(
+        ClearCore::IpAddress(uint32_t(ip)));
+    ClearCore::EthernetMgr.GatewayIp(
+        ClearCore::IpAddress(uint32_t(gateway)));
+    ClearCore::EthernetMgr.NetmaskIp(
+        ClearCore::IpAddress(uint32_t(subnet)));
+    ClearCore::EthernetMgr.DnsIp(
+        ClearCore::IpAddress(uint32_t(dns)));
+}
+
+void EthernetClass::init(uint8_t sspin) {
+    (void)sspin; // Nothing to implement here.
+}
+
+EthernetLinkStatus EthernetClass::linkStatus() {
+    return ClearCore::EthernetMgr.PhyLinkActive() ? LinkON : LinkOFF;
+}
+
+EthernetHardwareStatus EthernetClass::hardwareStatus() {
+    return EthernetBuiltIn;
+}
+
+int EthernetClass::maintain() {
+    ClearCore::EthernetMgr.Refresh();
+    // lwIP handles all DHCP state changes (renewal, rebind, etc.)
+    // in the background via sys_check_timeouts()
+    return 0;
+}
+
+void EthernetClass::MACAddress(uint8_t *mac_address) {
+    memcpy(mac_address, ClearCore::EthernetMgr.MacAddress(), 6);
+}
+
+IPAddress EthernetClass::localIP() {
+    return IPAddress(uint32_t(ClearCore::EthernetMgr.LocalIp()));
+}
+
+IPAddress EthernetClass::subnetMask() {
+    return IPAddress(uint32_t(ClearCore::EthernetMgr.NetmaskIp()));
+}
+
+IPAddress EthernetClass::gatewayIP() {
+    return IPAddress(uint32_t(ClearCore::EthernetMgr.GatewayIp()));
+}
+
+IPAddress EthernetClass::dnsServerIP() {
+    return IPAddress(uint32_t(ClearCore::EthernetMgr.DnsIp()));
+}
+
+void EthernetClass::setMACAddress(const uint8_t *mac) {
+    (void)mac; // Disallow setting the MAC address.
+}
+
+void EthernetClass::setLocalIP(const IPAddress local_ip) {
+    ClearCore::EthernetMgr.LocalIp(uint32_t(local_ip));
+}
+
+void EthernetClass::setSubnetMask(const IPAddress subnet) {
+    ClearCore::EthernetMgr.NetmaskIp(uint32_t(subnet));
+}
+
+void EthernetClass::setGatewayIP(const IPAddress gateway) {
+    ClearCore::EthernetMgr.GatewayIp(uint32_t(gateway));
+}
+
+void EthernetClass::setDnsServerIP(const IPAddress dns) {
+    ClearCore::EthernetMgr.DnsIp(uint32_t(dns));
+}
+
+void EthernetClass::setRetransmissionTimeout(uint16_t milliseconds) {
+    milliseconds = constrain(milliseconds, 1, 6553);
+    ClearCore::EthernetMgr.RetransmissionTimeout(milliseconds);
+}
+
+void EthernetClass::setRetransmissionCount(uint8_t number) {
+    if (number == 0) {
+        number = 1; // We should try at least once.
+    }
+
+    ClearCore::EthernetMgr.RetransmissionCount(number);
+}
+
+IPAddress EthernetClass::convertIp(ip_addr_t *ip) {
+    IPAddress ipAddr = IPAddress(ip->addr);
+    return ipAddr;
+}
+
+ip_addr_t EthernetClass::convertIp(IPAddress ip) {
+    ip_addr_t ipAddr = {};
+    IP4_ADDR(&ipAddr, ip[0], ip[1], ip[2], ip[3]);
+    return ipAddr;
+}
+
+EthernetClass Ethernet;
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Ethernet.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Ethernet.h
new file mode 100644
index 000000000..82ab29700
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Ethernet.h
@@ -0,0 +1,284 @@
+/* Copyright 2018 Paul Stoffregen
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef ethernet_h_
+#define ethernet_h_
+
+// All symbols exposed to Arduino sketches are contained in this header file
+//
+// Older versions had much of this stuff in EthernetClient.h, EthernetServer.h,
+// and socket.h.  Including headers in different order could cause trouble, so
+// these "friend" classes are now defined in the same header file.  socket.h
+// was removed to avoid possible conflict with the C library header files.
+
+#include <Arduino.h>
+#include "EthernetUdp.h"
+#include "EthernetTcp.h"
+#include "EthernetTcpClient.h"
+#include "EthernetTcpServer.h"
+#include "Client.h"
+#include "Server.h"
+#include "lwip/ip_addr.h"
+
+enum EthernetLinkStatus {
+    Unknown,
+    LinkON,
+    LinkOFF
+};
+
+enum EthernetHardwareStatus {
+    EthernetNoHardware, // No WIZnet hardware...
+    EthernetW5100,
+    EthernetW5200,
+    EthernetW5500,
+    EthernetBuiltIn
+};
+
+class EthernetUDP;
+class EthernetClient;
+class EthernetServer;
+class DhcpClass;
+
+class EthernetClass {
+public:
+    // Initialize the Ethernet shield to use the provided MAC address and
+    // gain the rest of the configuration through DHCP.
+    // Returns 0 if the DHCP configuration failed, and 1 if it succeeded.
+    int begin(uint8_t *mac);
+    int maintain();
+    EthernetLinkStatus linkStatus();
+    EthernetHardwareStatus hardwareStatus();
+
+    // Manual configuration
+    void begin(uint8_t *mac, IPAddress ip);
+    void begin(uint8_t *mac, IPAddress ip, IPAddress dns);
+    void begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway);
+    void begin(uint8_t *mac, IPAddress ip, IPAddress dns, IPAddress gateway,
+               IPAddress subnet);
+    void init(uint8_t sspin);
+
+    void MACAddress(uint8_t *mac_address);
+    IPAddress localIP();
+    IPAddress subnetMask();
+    IPAddress gatewayIP();
+    IPAddress dnsServerIP();
+
+    void setMACAddress(const uint8_t *mac);
+    void setLocalIP(const IPAddress local_ip);
+    void setSubnetMask(const IPAddress subnet);
+    void setGatewayIP(const IPAddress gateway);
+    void setDnsServerIP(const IPAddress dns);
+    void setRetransmissionTimeout(uint16_t milliseconds);
+    void setRetransmissionCount(uint8_t number);
+
+    // Convert an lwIP IP address type to an Arduino IP address type (IPv4).
+    IPAddress convertIp(ip_addr_t *ip);
+
+    // Convert an Arduino IP address type to an lwIP IP address type (IPv4).
+    ip_addr_t convertIp(IPAddress ip);
+
+    friend class EthernetClient;
+    friend class EthernetServer;
+    friend class EthernetUDP;
+};
+
+extern EthernetClass Ethernet;
+
+class EthernetUDP : public UDP {
+public:
+    EthernetUDP();
+    // Initialize the UDP library and network settings.
+    // Start listening on the localPort. Returns 1 if successful,
+    // 0 if there are no sockets available to use.
+    virtual uint8_t begin(uint16_t localPort);
+
+    // initialize, start listening on specified multicast IP address and port.
+    // Returns 1 if successful, 0 on failure.
+    virtual uint8_t beginMulticast(IPAddress, uint16_t) {
+        return 0;
+    }
+
+    // Disconnect from the server. Release any resource being used during the
+    // UDP session.
+    virtual void stop();
+
+    // Sending UDP datagrams
+
+    // Start a connection to write UDP data to the remote connection given by
+    // remoteIp and remotePort. Returns 1 if successful, 0 if there was a
+    // problem resolving the IP or port.
+    virtual int beginPacket(IPAddress remoteIp, uint16_t remotePort);
+    // Use DNS to resolve the given hostname to an IP address then start
+    // a UDP connection.
+    virtual int beginPacket(const char *host, uint16_t remotePort);
+    // Call after writing UDP data to the remote connection with write() to send
+    // the UDP packet started with beginPacket(). Returns 1 if the packet was
+    // sent successfully, 0 if there was an error.
+    virtual int endPacket();
+
+    // Write UDP data to the outgoing packet set up with beginPacket(). The
+    // packet will not be sent until endPacket() is called.
+    // Returns the actual number of bytes written.
+
+    // Write a single byte into the outgoing packet.
+    virtual size_t write(uint8_t);
+    // Write size bytes from the buffer into the outgoing packet.
+    virtual size_t write(const uint8_t *buffer, size_t size);
+
+    using Print::write;
+
+    // Receiving UDP datagrams
+
+    // Check for the presence of a UDP packet and return the size in bytes.
+    // parsePacket() must be called before reading the packet with read().
+    virtual int parsePacket();
+    // The number of bytes available for reading from the buffer.
+    // parsePacket() must be called before calling available().
+    virtual int available();
+
+    // Read UDP data. Returns the number of bytes read.
+    // parsePacket() must be called before read().
+
+    // Read one byte/character from the received packet.
+    virtual int read();
+    // Read up to len bytes from the received packet and put them into buffer.
+    virtual int read(unsigned char *buffer, size_t len);
+    virtual int read(char *buffer, size_t len) {
+        return read((unsigned char *)buffer, len);
+    };
+    // Return the next byte from the current packet without moving on to the
+    // next byte.
+    virtual int peek();
+    // Finish reading the current packet.
+    virtual void flush();
+
+    // The IP address of the remote connection. Must be called after parsePacket().
+    virtual IPAddress remoteIP();
+    // The port of the remote connection. Must be called after parsePacket().
+    virtual uint16_t remotePort();
+
+private:
+    ClearCore::EthernetUdp m_udp;
+};
+
+class EthernetServer : public Server {
+public:
+    // Create a server that listens for incoming connections on the specified port.
+    EthernetServer(uint16_t port = 80);
+
+    // Tell the server to begin listening for incoming connections.
+    virtual void begin();
+
+    // Get a client connected to the server that has data available for reading.
+    // The connection persists; close it by calling stop() on the client.
+    EthernetClient available();
+
+    // Get a client connected to the server. The caller must keep track of the
+    // returned client, since accept() will return it only once.
+    virtual EthernetClient accept();
+
+    // Write data to all the clients connected to a server.
+    virtual size_t write(uint8_t);
+    virtual size_t write(const uint8_t *buf, size_t size);
+
+    // This allows you to use "if (server)" to check if the supplied
+    // EthernetServer server is started and connected.
+    virtual operator bool();
+
+    using Print::write;
+
+private:
+    ClearCore::EthernetTcpServer m_tcpServer;
+};
+
+class EthernetClient : public Client {
+public:
+    // Create a client which can connect to a specified internet IP address
+    // and port (defined via connect()).
+    EthernetClient();
+    EthernetClient(ClearCore::EthernetTcpClient tcpClient);
+
+    // Connects to a specified IP address and port. Supports DNS lookups
+    // when using a domain name.
+    // Return value indicates connection status:
+    //  1: SUCCESS
+    // -1: TIMED_OUT
+    // -2: INVALID_SERVER
+    // -3: TRUNCATED
+    // -4: INVALID_RESPONSE
+    virtual int connect(IPAddress ip, uint16_t port);
+    virtual int connect(const char *host, uint16_t port);
+
+    // Write data to the server the client is connected to.
+    virtual size_t write(uint8_t val);
+    virtual size_t write(const uint8_t *buf, size_t size);
+
+    // Return the number of bytes available for reading (the amount of data that
+    // has been written to the client by the server it is connected to).
+    virtual int available();
+
+    // Read the next byte received from the server the client is connected to.
+    virtual int read();
+    // Read size bytes into the supplied buf from the associated server.
+    virtual int read(uint8_t *buf, size_t size);
+
+    // Wait until all outgoing characters in buffer have been sent.
+    virtual void flush();
+    // Disconnect from the server.
+    virtual void stop();
+    // Return whether the client is connected. (The client is still considered
+    // connected if the connection has been closed but there is still unread
+    // data.)
+    virtual uint8_t connected();
+    // Peek at the first character received from the server.
+    virtual int peek();
+
+    // Return the local port number the client is connected to.
+    virtual uint16_t localPort();
+    // Return the IP address of the client. (Not the server's IP?)
+    virtual IPAddress remoteIP();
+    // Return the remote port number of the server the client is connected to.
+    virtual uint16_t remotePort();
+    // Set the timeout for connect() and stop(), in milliseconds. The initial
+    // value is 1000 ms.
+    virtual void setConnectionTimeout(uint16_t milliseconds);
+
+    virtual operator bool();
+    virtual bool operator==(const bool value) {
+        return bool() == value;
+    }
+    virtual bool operator!=(const bool value) {
+        return bool() != value;
+    }
+    virtual bool operator==(const EthernetClient &);
+    virtual bool operator!=(const EthernetClient &rhs) {
+        return !this->operator==(rhs);
+    };
+
+    friend class EthernetServer;
+
+    using Print::write;
+protected:
+    ClearCore::EthernetTcpClient m_tcpClient;
+    bool m_dnsInitialized;
+};
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetClient.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetClient.cpp
new file mode 100644
index 000000000..21b626d52
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetClient.cpp
@@ -0,0 +1,115 @@
+#include <Ethernet.h>
+#include "EthernetUtils.h"
+#include "IpAddress.h"
+
+EthernetClient::EthernetClient()
+    : m_tcpClient(),
+      m_dnsInitialized(false) {}
+
+EthernetClient::EthernetClient(ClearCore::EthernetTcpClient tcpClient)
+    : m_tcpClient(tcpClient),
+      m_dnsInitialized(false) {}
+
+int EthernetClient::connect(IPAddress ip, uint16_t port) {
+    ClearCore::IpAddress nativeIp = ClearCore::IpAddress(uint32_t(ip));
+    return m_tcpClient.Connect(nativeIp, port) ? 1 : 0;
+}
+
+int EthernetClient::connect(const char *host, uint16_t port) {
+    int result = -1;
+    // Attempt to resolve the host.
+    ip_addr_t remoteIp = {};
+    err_t err = ClearCore::DnsGetHostByName(host, &remoteIp);
+    IPAddress ip = Ethernet.convertIp(&remoteIp);
+
+    switch (err) {
+        case ERR_OK:
+            if (connect(ip, port) == 1) {
+                result = 1; // SUCCESS
+            }
+            else {
+                result = -4; // INVALID_RESPONSE
+            }
+            break;
+        case ERR_INPROGRESS:
+            result = -1; // TIMED_OUT
+            break;
+        case ERR_VAL:
+            result = -2; // INVALID_SERVER
+            break;
+        case ERR_MEM:
+            result = -3; // TRUNCATED
+            break;
+        case ERR_ARG:
+        default:
+            result = -4; // INVALID_RESPONSE
+            break;
+    }
+    return result;
+}
+
+size_t EthernetClient::write(uint8_t c) {
+    return write(&c, 1);
+}
+
+size_t EthernetClient::write(const uint8_t *buffer, size_t size) {
+    return m_tcpClient.Send(buffer, size);
+}
+
+int EthernetClient::available() {
+    return m_tcpClient.BytesAvailable();
+}
+
+int EthernetClient::read() {
+    return m_tcpClient.Read();
+}
+
+int EthernetClient::read(uint8_t *buf, size_t size) {
+    return m_tcpClient.Read(buf, size);
+}
+
+// wait until all outgoing data to the client has been sent
+void EthernetClient::flush() {
+    m_tcpClient.Flush();
+}
+
+void EthernetClient::stop() {
+    m_tcpClient.Close();
+}
+
+// A client is considered connected if the connection has been closed but
+// there is still unread data.
+uint8_t EthernetClient::connected() {
+    if (m_tcpClient.BytesAvailable() > 0 || m_tcpClient.Connected()) {
+        return 1;
+    }
+    return 0;
+}
+
+int EthernetClient::peek() {
+    return m_tcpClient.Peek();
+}
+
+uint16_t EthernetClient::localPort() {
+    return m_tcpClient.LocalPort();
+}
+
+IPAddress EthernetClient::remoteIP() {
+    IPAddress ip = IPAddress(uint32_t(m_tcpClient.RemoteIp()));
+    return ip;
+}
+
+uint16_t EthernetClient::remotePort() {
+    return m_tcpClient.RemotePort();
+}
+
+void EthernetClient::setConnectionTimeout(uint16_t milliseconds) {
+    m_tcpClient.ConnectionTimeout(milliseconds);
+}
+EthernetClient::operator bool() {
+    return m_tcpClient.ConnectionState() != nullptr;
+}
+
+bool EthernetClient::operator==(const EthernetClient &client) {
+    return m_tcpClient == client.m_tcpClient;
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetServer.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetServer.cpp
new file mode 100644
index 000000000..efd26a493
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetServer.cpp
@@ -0,0 +1,31 @@
+#include <Ethernet.h>
+
+EthernetServer::EthernetServer(uint16_t port/* = 80*/) : m_tcpServer(port) {}
+
+void EthernetServer::begin() {
+    m_tcpServer.Begin();
+}
+
+// EthernetServer gives a client only once, regardless of it it has sent data.
+// Then, the user is responsible for keeping track of connected clients.
+EthernetClient EthernetServer::accept() {
+    return EthernetClient(m_tcpServer.Accept());
+}
+
+// EthernetServer manages the clients. A client is only identified and returned
+// when data has been received from the client and is available for reading.
+EthernetClient EthernetServer::available() {
+    return EthernetClient(m_tcpServer.Available());
+}
+
+size_t EthernetServer::write(uint8_t c) {
+    return write(&c, 1);
+}
+
+size_t EthernetServer::write(const uint8_t *buf, size_t size) {
+    return m_tcpServer.Send(buf, size);
+}
+
+EthernetServer::operator bool() {
+    return m_tcpServer.Ready();
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetUDP.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetUDP.cpp
new file mode 100644
index 000000000..777914f50
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/EthernetUDP.cpp
@@ -0,0 +1,78 @@
+#include <Ethernet.h>
+#include "EthernetUdp.h"
+#include "EthernetUtils.h"
+#include "IpAddress.h"
+
+
+EthernetUDP::EthernetUDP(): m_udp() {}
+
+uint8_t EthernetUDP::begin(uint16_t localPort) {
+    return m_udp.Begin(localPort) ? 1 : 0;
+}
+
+void EthernetUDP::stop() {
+    m_udp.End();
+}
+
+int EthernetUDP::beginPacket(IPAddress ip, uint16_t port) {
+    ClearCore::IpAddress nativeIp = ClearCore::IpAddress(uint32_t(ip));
+    return m_udp.Connect(nativeIp, port) ? 1 : 0;
+}
+
+int EthernetUDP::beginPacket(const char *host, uint16_t remotePort) {
+    // Attempt to resolve the host.
+    ip_addr_t remoteIp = {};
+    if (ClearCore::DnsGetHostByName(host, &remoteIp) != ERR_OK) {
+        return 0; // Unable to resolve hostname or timed out.
+    }
+
+    IPAddress ip = Ethernet.convertIp(&remoteIp);
+
+    return beginPacket(ip, remotePort);
+}
+
+int EthernetUDP::endPacket() {
+    return m_udp.PacketSend() ? 1 : 0;
+}
+
+size_t EthernetUDP::write(uint8_t c) {
+    return write(&c, 1);
+}
+
+size_t EthernetUDP::write(const uint8_t *buffer, size_t size) {
+    return m_udp.PacketWrite(buffer, size);
+}
+
+int EthernetUDP::parsePacket() {
+    return m_udp.PacketParse();
+}
+
+int EthernetUDP::available() {
+    return m_udp.BytesAvailable();
+}
+
+int EthernetUDP::read() {
+    unsigned char c;
+    return (read(&c, 1) == 1) ? c : -1;
+}
+
+int EthernetUDP::read(unsigned char *buffer, size_t len) {
+    return m_udp.PacketRead(buffer, len);
+}
+
+int EthernetUDP::peek() {
+    return m_udp.Peek();
+}
+
+void EthernetUDP::flush() {
+    m_udp.PacketFlush();
+}
+
+IPAddress EthernetUDP::remoteIP() {
+    IPAddress ip = IPAddress(uint32_t(m_udp.RemoteIp()));
+    return ip;
+}
+
+uint16_t EthernetUDP::remotePort() {
+    return m_udp.RemotePort();
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Reset.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Reset.cpp
new file mode 100644
index 000000000..39beb0c95
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Reset.cpp
@@ -0,0 +1,100 @@
+/*
+  Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <Arduino.h>
+#include "Reset.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVM_MEMORY ((volatile uint16_t *)0x000000)
+
+#if (ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10610)
+
+extern const uint32_t __text_start__;
+#define APP_START ((volatile uint32_t)(&__text_start__) + 4)
+
+#else
+#define APP_START 0x00002004
+#endif
+
+static inline bool nvmReady(void) {
+    return NVMCTRL->STATUS.bit.READY;
+}
+
+__attribute__((long_call, section(".ramfunc")))
+static void banzai() {
+    // Disable all interrupts
+    __disable_irq();
+
+    // Get a copy of the NVM "user page"
+    uint32_t userspace = *((uint32_t *)NVMCTRL_FUSES_BOOTPROT_ADDR);
+    uint32_t bootsize = NVMCTRL_BLOCK_SIZE *
+                        (15 - ((userspace & NVMCTRL_FUSES_BOOTPROT_Msk)
+                               >> NVMCTRL_FUSES_BOOTPROT_Pos));
+    // Avoid erasing the application if APP_START is < than the minimum
+    // bootloader sizea
+    // This could happen if without_bootloader linker script was chosen
+    if ((APP_START - 4) < bootsize) {
+        goto reset;
+    }
+
+    // Erase application
+    while (!nvmReady()) {
+        continue;
+    }
+    NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+    // Set address to starting address
+    NVMCTRL->ADDR.reg = (APP_START - 4);
+    NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_EB | NVMCTRL_CTRLB_CMDEX_KEY;
+    while (!nvmReady()) {
+        continue;
+    }
+reset:
+    // Reset the device
+    NVIC_SystemReset() ;
+
+    while (true) {
+        continue;
+    }
+}
+
+static int ticks = -1;
+
+void initiateReset(int _ticks) {
+    ticks = _ticks;
+}
+
+void cancelReset() {
+    ticks = -1;
+}
+
+void tickReset() {
+    if (ticks == -1) {
+        return;
+    }
+    ticks--;
+    if (ticks == 0) {
+        banzai();
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Reset.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Reset.h
new file mode 100644
index 000000000..1ddefbf04
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Reset.h
@@ -0,0 +1,31 @@
+/*
+  Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void initiateReset(int ms);
+void tickReset();
+void cancelReset();
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/SERCOM.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/SERCOM.cpp
new file mode 100644
index 000000000..d40f69cc7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/SERCOM.cpp
@@ -0,0 +1,687 @@
+/*
+  Copyright (c) 2014 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "SERCOM.h"
+#include "variant.h"
+
+#ifndef WIRE_RISE_TIME_NANOSECONDS
+// Default rise time in nanoseconds, based on 4.7K ohm pull up resistors
+// you can override this value in your variant if needed
+#define WIRE_RISE_TIME_NANOSECONDS 125
+#endif
+
+SERCOM::SERCOM(Sercom *s) {
+    sercom = s;
+}
+
+/*  =========================
+ *  ====== Sercom UART ======
+ *  =========================
+*/
+void SERCOM::initUART(SercomUartMode mode, SercomUartSampleRate sampleRate,
+                      uint32_t baudrate) {
+    initClockNVIC();
+    resetUART();
+
+    //Setting the CTRLA register
+    sercom->USART.CTRLA.reg =   SERCOM_USART_CTRLA_MODE(mode) |
+                                SERCOM_USART_CTRLA_SAMPR(sampleRate);
+
+    //Setting the Interrupt register
+    sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC | //Rx complete
+                                 SERCOM_USART_INTENSET_ERROR;//All others errors
+
+    if (mode == UART_INT_CLOCK) {
+        uint16_t sampleRateValue;
+
+        if (sampleRate == SAMPLE_RATE_x16) {
+            sampleRateValue = 16;
+        }
+        else {
+            sampleRateValue = 8;
+        }
+
+        // Asynchronous fractional mode (Table 24-2 in datasheet)
+        //   BAUD = fref / (sampleRateValue * fbaud)
+        // (multiply by 8, to calculate fractional piece)
+        uint32_t baudTimes8 = (SystemCoreClock * 8) /
+                              (sampleRateValue * baudrate);
+
+        sercom->USART.BAUD.FRAC.FP   = (baudTimes8 % 8);
+        sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8);
+    }
+}
+void SERCOM::initFrame(SercomUartCharSize charSize,
+                       SercomDataOrder dataOrder, SercomParityMode parityMode,
+                       SercomNumberStopBit nbStopBits) {
+    //Setting the CTRLA register
+    sercom->USART.CTRLA.reg |=
+        SERCOM_USART_CTRLA_FORM((parityMode == SERCOM_NO_PARITY ? 0 : 1)) |
+        dataOrder << SERCOM_USART_CTRLA_DORD_Pos;
+
+    //Setting the CTRLB register
+    sercom->USART.CTRLB.reg |=
+        SERCOM_USART_CTRLB_CHSIZE(charSize) |
+        nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos |
+        (parityMode == SERCOM_NO_PARITY ? 0 : parityMode)
+        << SERCOM_USART_CTRLB_PMODE_Pos; // If no parity use default value
+}
+
+void SERCOM::initPads(SercomUartTXPad txPad, SercomRXPad rxPad) {
+    //Setting the CTRLA register
+    sercom->USART.CTRLA.reg |=  SERCOM_USART_CTRLA_TXPO(txPad) |
+                                SERCOM_USART_CTRLA_RXPO(rxPad);
+
+    // Enable Transceiver and Receiver
+    sercom->USART.CTRLB.reg |=
+        SERCOM_USART_CTRLB_TXEN |
+        SERCOM_USART_CTRLB_RXEN;
+}
+
+void SERCOM::resetUART() {
+    // Start the Software Reset
+    sercom->USART.CTRLA.bit.SWRST = 1 ;
+
+    while (sercom->USART.CTRLA.bit.SWRST || sercom->USART.SYNCBUSY.bit.SWRST) {
+        // Wait for both bits Software Reset from CTRLA and SYNCBUSY coming back
+        // to 0
+        continue;
+    }
+}
+
+void SERCOM::enableUART() {
+    //Setting  the enable bit to 1
+    sercom->USART.CTRLA.bit.ENABLE = 0x1u;
+
+    //Wait for then enable bit from SYNCBUSY is equal to 0;
+    while (sercom->USART.SYNCBUSY.bit.ENABLE) {
+        continue;
+    }
+}
+
+void SERCOM::flushUART() {
+    // Skip checking transmission completion if data register is empty
+    if (isDataRegisterEmptyUART()) {
+        return;
+    }
+
+    // Wait for transmission to complete
+    while (!sercom->USART.INTFLAG.bit.TXC) {
+        continue;
+    }
+}
+
+void SERCOM::clearStatusUART() {
+    //Reset (with 0) the STATUS register
+    sercom->USART.STATUS.reg = SERCOM_USART_STATUS_RESETVALUE;
+}
+
+bool SERCOM::availableDataUART() {
+    //RXC : Receive Complete
+    return sercom->USART.INTFLAG.bit.RXC;
+}
+
+bool SERCOM::isUARTError() {
+    return sercom->USART.INTFLAG.bit.ERROR;
+}
+
+void SERCOM::acknowledgeUARTError() {
+    sercom->USART.INTFLAG.bit.ERROR = 1;
+}
+
+bool SERCOM::isBufferOverflowErrorUART() {
+    //BUFOVF : Buffer Overflow
+    return sercom->USART.STATUS.bit.BUFOVF;
+}
+
+bool SERCOM::isFrameErrorUART() {
+    //FERR : Frame Error
+    return sercom->USART.STATUS.bit.FERR;
+}
+
+void SERCOM::clearFrameErrorUART() {
+    // clear FERR bit writing 1 status bit
+    sercom->USART.STATUS.bit.FERR = 1;
+}
+
+bool SERCOM::isParityErrorUART() {
+    //PERR : Parity Error
+    return sercom->USART.STATUS.bit.PERR;
+}
+
+bool SERCOM::isDataRegisterEmptyUART() {
+    //DRE : Data Register Empty
+    return sercom->USART.INTFLAG.bit.DRE;
+}
+
+uint8_t SERCOM::readDataUART() {
+    return sercom->USART.DATA.bit.DATA;
+}
+
+int SERCOM::writeDataUART(uint8_t data) {
+    // Wait for data register to be empty
+    while (!isDataRegisterEmptyUART()) {
+        continue;
+    }
+
+    //Put data into DATA register
+    sercom->USART.DATA.reg = (uint16_t)data;
+    return 1;
+}
+
+void SERCOM::enableDataRegisterEmptyInterruptUART() {
+    sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+void SERCOM::disableDataRegisterEmptyInterruptUART() {
+    sercom->USART.INTENCLR.reg = SERCOM_USART_INTENCLR_DRE;
+}
+
+/*  =========================
+ *  ====== Sercom SPI =======
+ *  =========================
+*/
+void SERCOM::initSPI(SercomSpiTXPad mosi, SercomRXPad miso,
+                     SercomSpiCharSize charSize, SercomDataOrder dataOrder) {
+    resetSPI();
+    initClockNVIC();
+
+    //Setting the CTRLA register
+    sercom->SPI.CTRLA.bit.MODE = 3;         // SPI master operation
+    sercom->SPI.CTRLA.bit.DOPO = mosi;      // Data out pinout: MOSI
+    sercom->SPI.CTRLA.bit.DIPO = miso;      // Data in pinout: MISO
+    sercom->SPI.CTRLA.bit.DORD = dataOrder; // Data order
+
+    //Setting the CTRLB register
+    sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(charSize) |
+                            SERCOM_SPI_CTRLB_RXEN;  //Active the SPI receiver.
+}
+
+void SERCOM::initSPIClock(SercomSpiClockMode clockMode, uint32_t baudrate) {
+    //Extract data from clockMode
+    int cpha, cpol;
+
+    if ((clockMode & (0x1ul)) == 0) {
+        cpha = 0;
+    }
+    else {
+        cpha = 1;
+    }
+
+    if ((clockMode & (0x2ul)) == 0) {
+        cpol = 0;
+    }
+    else {
+        cpol = 1;
+    }
+
+    //Setting the CTRLA register
+    sercom->SPI.CTRLA.reg |= (cpha << SERCOM_SPI_CTRLA_CPHA_Pos) |
+                             (cpol << SERCOM_SPI_CTRLA_CPOL_Pos);
+
+    //Synchronous arithmetic
+    sercom->SPI.BAUD.reg = calculateBaudrateSynchronous(baudrate);
+}
+
+void SERCOM::resetSPI() {
+    //Setting the Software Reset bit to 1
+    sercom->SPI.CTRLA.bit.SWRST = 1;
+
+    //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
+    while (sercom->SPI.CTRLA.bit.SWRST || sercom->SPI.SYNCBUSY.bit.SWRST) {
+        continue;
+    }
+}
+
+void SERCOM::enableSPI() {
+    //Setting the enable bit to 1
+    sercom->SPI.CTRLA.bit.ENABLE = 1;
+
+    while (sercom->SPI.SYNCBUSY.bit.ENABLE) {
+        //Waiting then enable bit from SYNCBUSY is equal to 0;
+        continue;
+    }
+}
+
+void SERCOM::disableSPI() {
+    while (sercom->SPI.SYNCBUSY.bit.ENABLE) {
+        //Waiting then enable bit from SYNCBUSY is equal to 0;
+        continue;
+    }
+
+    //Setting the enable bit to 0
+    sercom->SPI.CTRLA.bit.ENABLE = 0;
+}
+
+void SERCOM::setDataOrderSPI(SercomDataOrder dataOrder) {
+    //Register enable-protected
+    disableSPI();
+
+    sercom->SPI.CTRLA.bit.DORD = dataOrder;
+
+    enableSPI();
+}
+
+SercomDataOrder SERCOM::getDataOrderSPI() {
+    return (sercom->SPI.CTRLA.bit.DORD ? LSB_FIRST : MSB_FIRST);
+}
+
+void SERCOM::setBaudrateSPI(uint8_t divider) {
+    //Can't divide by 0
+    if (divider == 0) {
+        return;
+    }
+
+    //Register enable-protected
+    disableSPI();
+
+    sercom->SPI.BAUD.reg =
+        calculateBaudrateSynchronous(SERCOM_FREQ_REF / divider);
+
+    enableSPI();
+}
+
+void SERCOM::setClockModeSPI(SercomSpiClockMode clockMode) {
+    int cpha, cpol;
+    if ((clockMode & (0x1ul)) == 0) {
+        cpha = 0;
+    }
+    else {
+        cpha = 1;
+    }
+
+    if ((clockMode & (0x2ul)) == 0) {
+        cpol = 0;
+    }
+    else {
+        cpol = 1;
+    }
+
+    //Register enable-protected
+    disableSPI();
+
+    sercom->SPI.CTRLA.bit.CPOL = cpol;
+    sercom->SPI.CTRLA.bit.CPHA = cpha;
+
+    enableSPI();
+}
+
+uint8_t SERCOM::transferDataSPI(uint8_t data) {
+    sercom->SPI.DATA.bit.DATA = data; // Writing data into Data register
+
+    while (sercom->SPI.INTFLAG.bit.RXC == 0) {
+        // Waiting Complete Reception
+        continue;
+    }
+
+    return sercom->SPI.DATA.bit.DATA;  // Reading data
+}
+
+bool SERCOM::isBufferOverflowErrorSPI() {
+    return sercom->SPI.STATUS.bit.BUFOVF;
+}
+
+bool SERCOM::isDataRegisterEmptySPI() {
+    //DRE : Data Register Empty
+    return sercom->SPI.INTFLAG.bit.DRE;
+}
+
+uint8_t SERCOM::calculateBaudrateSynchronous(uint32_t baudrate) {
+    return SERCOM_FREQ_REF / (2 * baudrate) - 1;
+}
+
+
+/*  =========================
+ *  ====== Sercom WIRE ======
+ *  =========================
+ */
+void SERCOM::resetWIRE() {
+    //I2CM OR I2CS, no matter SWRST is the same bit.
+
+    //Setting the Software bit to 1
+    sercom->I2CM.CTRLA.bit.SWRST = 1;
+
+    //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
+    while (sercom->I2CM.CTRLA.bit.SWRST || sercom->I2CM.SYNCBUSY.bit.SWRST) {
+        continue;
+    }
+}
+
+void SERCOM::enableWIRE() {
+    // I2C Master and Slave modes share the ENABLE bit function.
+
+    // Enable the I2C master mode
+    sercom->I2CM.CTRLA.bit.ENABLE = 1 ;
+
+    while (sercom->I2CM.SYNCBUSY.bit.ENABLE != 0) {
+        // Waiting the enable bit from SYNCBUSY is equal to 0;
+        continue;
+    }
+
+    // Setting bus idle mode
+    sercom->I2CM.STATUS.bit.BUSSTATE = 1 ;
+
+    while (sercom->I2CM.SYNCBUSY.bit.SYSOP != 0) {
+        // Wait the SYSOP bit from SYNCBUSY coming back to 0
+        continue;
+    }
+}
+
+void SERCOM::disableWIRE() {
+    // I2C Master and Slave modes share the ENABLE bit function.
+
+    // Enable the I2C master mode
+    sercom->I2CM.CTRLA.bit.ENABLE = 0 ;
+
+    while (sercom->I2CM.SYNCBUSY.bit.ENABLE != 0) {
+        // Waiting the enable bit from SYNCBUSY is equal to 0;
+        continue;
+    }
+}
+
+void SERCOM::initSlaveWIRE(uint8_t ucAddress, bool enableGeneralCall) {
+    // Initialize the peripheral clock and interruption
+    initClockNVIC() ;
+    resetWIRE() ;
+
+    // Set slave mode
+    sercom->I2CS.CTRLA.bit.MODE = I2C_SLAVE_OPERATION;
+
+                            // 0x7F, select only 7 bits
+    sercom->I2CS.ADDR.reg = SERCOM_I2CS_ADDR_ADDR(ucAddress & 0x7Ful) |
+                            // 0x00, only match exact address
+                            SERCOM_I2CS_ADDR_ADDRMASK(0x00ul);
+    if (enableGeneralCall) {
+        // enable general call (address 0x00)
+        sercom->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+    }
+
+    // Set the interrupt register
+    sercom->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC |   // Stop
+                                SERCOM_I2CS_INTENSET_AMATCH | // Address Match
+                                SERCOM_I2CS_INTENSET_DRDY;    // Data Ready
+
+    while (sercom->I2CM.SYNCBUSY.bit.SYSOP != 0) {
+        // Wait the SYSOP bit from SYNCBUSY to come back to 0
+        continue;
+    }
+}
+
+void SERCOM::initMasterWIRE(uint32_t baudrate) {
+    // Initialize the peripheral clock and interruption
+    initClockNVIC() ;
+
+    resetWIRE() ;
+
+    // Set master mode and enable SCL Clock Stretch mode (stretch after ACK bit)
+    sercom->I2CM.CTRLA.reg =  SERCOM_I2CM_CTRLA_MODE(I2C_MASTER_OPERATION);
+
+    // Synchronous arithmetic baudrate
+    sercom->I2CM.BAUD.bit.BAUD = SystemCoreClock / (2 * baudrate) - 5 -
+                                 (((SystemCoreClock / 1000000) * WIRE_RISE_TIME_NANOSECONDS) /
+                                  (2 * 1000));
+}
+
+void SERCOM::prepareNackBitWIRE(void) {
+    if (isMasterWIRE()) {
+        // Send a NACK
+        sercom->I2CM.CTRLB.bit.ACKACT = 1;
+    }
+    else {
+        sercom->I2CS.CTRLB.bit.ACKACT = 1;
+    }
+}
+
+void SERCOM::prepareAckBitWIRE(void) {
+    if (isMasterWIRE()) {
+        // Send an ACK
+        sercom->I2CM.CTRLB.bit.ACKACT = 0;
+    }
+    else {
+        sercom->I2CS.CTRLB.bit.ACKACT = 0;
+    }
+}
+
+void SERCOM::prepareCommandBitsWire(uint8_t cmd) {
+    if (isMasterWIRE()) {
+        sercom->I2CM.CTRLB.bit.CMD = cmd;
+
+        while (sercom->I2CM.SYNCBUSY.bit.SYSOP) {
+            // Waiting for synchronization
+            continue;
+        }
+    }
+    else {
+        sercom->I2CS.CTRLB.bit.CMD = cmd;
+    }
+}
+
+bool SERCOM::startTransmissionWIRE(uint8_t address,
+                                   SercomWireReadWriteFlag flag) {
+    // 7-bits address + 1-bits R/W
+    address = (address << 0x1ul) | flag;
+
+    // Wait idle or owner bus mode
+    while (!isBusIdleWIRE() && !isBusOwnerWIRE()) {
+        continue;
+    }
+
+    // Send start and address
+    sercom->I2CM.ADDR.bit.ADDR = address;
+
+    // Address Transmitted
+    if (flag == WIRE_WRITE_FLAG) {  // Write mode
+        while (!sercom->I2CM.INTFLAG.bit.MB) {
+            // Wait transmission complete
+            continue;
+        }
+    }
+    else {// Read mode
+        while (!sercom->I2CM.INTFLAG.bit.SB) {
+            // If the slave NACKS the address, the MB bit will be set.
+            // In that case, send a stop condition and return false.
+            if (sercom->I2CM.INTFLAG.bit.MB) {
+                sercom->I2CM.CTRLB.bit.CMD = 3; // Stop condition
+                return false;
+            }
+            // Wait transmission complete
+        }
+    }
+
+    //ACK received (0: ACK, 1: NACK)
+    if (sercom->I2CM.STATUS.bit.RXNACK) {
+        return false;
+    }
+    else {
+        return true;
+    }
+}
+
+bool SERCOM::sendDataMasterWIRE(uint8_t data) {
+    //Send data
+    sercom->I2CM.DATA.bit.DATA = data;
+
+    //Wait transmission successful
+    while (!sercom->I2CM.INTFLAG.bit.MB) {
+
+        // If a bus error occurs, the MB bit may never be set.
+        // Check the bus error bit and bail if it's set.
+        if (sercom->I2CM.STATUS.bit.BUSERR) {
+            return false;
+        }
+    }
+
+    //Problems on line? nack received?
+    if (sercom->I2CM.STATUS.bit.RXNACK) {
+        return false;
+    }
+    else {
+        return true;
+    }
+}
+
+bool SERCOM::sendDataSlaveWIRE(uint8_t data) {
+    //Send data
+    sercom->I2CS.DATA.bit.DATA = data;
+
+    //Problems on line? nack received?
+    if (!sercom->I2CS.INTFLAG.bit.DRDY || sercom->I2CS.STATUS.bit.RXNACK) {
+        return false;
+    }
+    else {
+        return true;
+    }
+}
+
+bool SERCOM::isMasterWIRE(void) {
+    return sercom->I2CS.CTRLA.bit.MODE == I2C_MASTER_OPERATION;
+}
+
+bool SERCOM::isSlaveWIRE(void) {
+    return sercom->I2CS.CTRLA.bit.MODE == I2C_SLAVE_OPERATION;
+}
+
+bool SERCOM::isBusIdleWIRE(void) {
+    return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_IDLE_STATE;
+}
+
+bool SERCOM::isBusOwnerWIRE(void) {
+    return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_OWNER_STATE;
+}
+
+bool SERCOM::isDataReadyWIRE(void) {
+    return sercom->I2CS.INTFLAG.bit.DRDY;
+}
+
+bool SERCOM::isStopDetectedWIRE(void) {
+    return sercom->I2CS.INTFLAG.bit.PREC;
+}
+
+bool SERCOM::isRestartDetectedWIRE(void) {
+    return sercom->I2CS.STATUS.bit.SR;
+}
+
+bool SERCOM::isAddressMatch(void) {
+    return sercom->I2CS.INTFLAG.bit.AMATCH;
+}
+
+bool SERCOM::isMasterReadOperationWIRE(void) {
+    return sercom->I2CS.STATUS.bit.DIR;
+}
+
+bool SERCOM::isRXNackReceivedWIRE(void) {
+    return sercom->I2CM.STATUS.bit.RXNACK;
+}
+
+int SERCOM::availableWIRE(void) {
+    if (isMasterWIRE()) {
+        return sercom->I2CM.INTFLAG.bit.SB;
+    }
+    else {
+        return sercom->I2CS.INTFLAG.bit.DRDY;
+    }
+}
+
+uint8_t SERCOM::readDataWIRE(void) {
+    if (isMasterWIRE()) {
+        while (sercom->I2CM.INTFLAG.bit.SB == 0) {
+            // Waiting complete receive
+            continue;
+        }
+
+        return sercom->I2CM.DATA.bit.DATA ;
+    }
+    else {
+        return sercom->I2CS.DATA.reg ;
+    }
+}
+
+void SERCOM::initClockNVIC(void) {
+    uint8_t clockId = 0;
+    // Dummy init to intercept potential error later
+    IRQn_Type IdNvic = PendSV_IRQn ;
+
+    if (sercom == SERCOM0) {
+        clockId = SERCOM0_GCLK_ID_CORE;
+        IdNvic = SERCOM0_0_IRQn;
+    }
+    else if (sercom == SERCOM1) {
+        clockId = 8;
+        IdNvic = SERCOM1_0_IRQn;
+    }
+    else if (sercom == SERCOM2) {
+        clockId = 23;
+        IdNvic = SERCOM2_0_IRQn;
+    }
+    else if (sercom == SERCOM3) {
+        clockId = 24;
+        IdNvic = SERCOM3_0_IRQn;
+    }
+#if defined(SERCOM4)
+    else if (sercom == SERCOM4) {
+        clockId = 34;
+        IdNvic = SERCOM4_0_IRQn;
+    }
+#endif // SERCOM4
+#if defined(SERCOM5)
+    else if (sercom == SERCOM5) {
+        clockId = 35;
+        IdNvic = SERCOM5_0_IRQn;
+    }
+#endif // SERCOM5
+#if defined(SERCOM6)
+    else if (sercom == SERCOM6) {
+        clockId = 36;
+        IdNvic = SERCOM6_0_IRQn;
+    }
+#endif // SERCOM6
+#if defined(SERCOM7)
+    else if (sercom == SERCOM7) {
+        clockId = 37;
+        IdNvic = SERCOM7_0_IRQn;
+    }
+#endif // SERCOM7
+
+    if (IdNvic == PendSV_IRQn) {
+        // We got a problem here
+        return ;
+    }
+
+    // Setting NVIC
+    NVIC_EnableIRQ((IRQn_Type)(IdNvic +
+                               SERCOM_USART_INTFLAG_DRE_Pos)); /*  Data Register Empty Interrupt */
+    NVIC_SetPriority((IRQn_Type)(IdNvic +
+                                 SERCOM_USART_INTFLAG_DRE_Pos), SERCOM_NVIC_PRIORITY); /* set Priority */
+    NVIC_EnableIRQ((IRQn_Type)(IdNvic +
+                               SERCOM_USART_INTFLAG_RXC_Pos)); /* Receive Complete Interrupt */
+    NVIC_SetPriority((IRQn_Type)(IdNvic +
+                                 SERCOM_USART_INTFLAG_RXC_Pos), SERCOM_NVIC_PRIORITY); /* set Priority */
+    NVIC_EnableIRQ((IRQn_Type)(IdNvic +
+                               SERCOM_USART_INTFLAG_RXS_Pos)); /* Receive Start Interrupt and errors */
+    NVIC_SetPriority((IRQn_Type)(IdNvic +
+                                 SERCOM_USART_INTFLAG_RXS_Pos), SERCOM_NVIC_PRIORITY); /* set Priority */
+
+    //Setting clock, Generic Clock Generator 0 is source
+    GCLK->PCHCTRL[clockId].reg = GCLK_PCHCTRL_GEN_GCLK0 |
+                                 GCLK_PCHCTRL_CHEN ;
+
+    while (GCLK->SYNCBUSY.bit.GENCTRL0) {
+        /* Wait for synchronization */
+        continue;
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/SERCOM.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/SERCOM.h
new file mode 100644
index 000000000..4029c9880
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/SERCOM.h
@@ -0,0 +1,210 @@
+/*
+  Copyright (c) 2014 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _SERCOM_CLASS_
+#define _SERCOM_CLASS_
+
+#include "sam.h"
+
+#define SERCOM_FREQ_REF      48000000
+#ifndef SERCOM_NVIC_PRIORITY
+#define SERCOM_NVIC_PRIORITY ((1 << __NVIC_PRIO_BITS) - 1)
+#endif
+
+typedef enum {
+    UART_EXT_CLOCK = 0,
+    UART_INT_CLOCK = 0x1u
+} SercomUartMode;
+
+typedef enum {
+    SPI_SLAVE_OPERATION = 0x2u,
+    SPI_MASTER_OPERATION = 0x3u
+} SercomSpiMode;
+
+typedef enum {
+    I2C_SLAVE_OPERATION = 0x4u,
+    I2C_MASTER_OPERATION = 0x5u
+} SercomI2CMode;
+
+typedef enum {
+    SERCOM_EVEN_PARITY = 0,
+    SERCOM_ODD_PARITY,
+    SERCOM_NO_PARITY
+} SercomParityMode;
+
+typedef enum {
+    SERCOM_STOP_BIT_1 = 0,
+    SERCOM_STOP_BITS_2
+} SercomNumberStopBit;
+
+typedef enum {
+    MSB_FIRST = 0,
+    LSB_FIRST
+} SercomDataOrder;
+
+typedef enum {
+    UART_CHAR_SIZE_8_BITS = 0,
+    UART_CHAR_SIZE_9_BITS,
+    UART_CHAR_SIZE_5_BITS = 0x5u,
+    UART_CHAR_SIZE_6_BITS,
+    UART_CHAR_SIZE_7_BITS
+} SercomUartCharSize;
+
+typedef enum {
+    SERCOM_RX_PAD_0 = 0,
+    SERCOM_RX_PAD_1,
+    SERCOM_RX_PAD_2,
+    SERCOM_RX_PAD_3
+} SercomRXPad;
+
+typedef enum {
+    UART_TX_PAD_0 = 0x0ul,  // Only for UART
+    UART_TX_PAD_2 = 0x1ul,  // Only for UART
+    // Only for UART with TX on PAD0, RTS on PAD2 and CTS on PAD3
+    UART_TX_RTS_CTS_PAD_0_2_3 = 0x2ul,
+} SercomUartTXPad;
+
+typedef enum {
+    SAMPLE_RATE_x16 = 0x1,  //Fractional
+    SAMPLE_RATE_x8 = 0x3,   //Fractional
+} SercomUartSampleRate;
+
+typedef enum {
+    SERCOM_SPI_MODE_0 = 0,  // CPOL : 0  | CPHA : 0
+    SERCOM_SPI_MODE_1,      // CPOL : 0  | CPHA : 1
+    SERCOM_SPI_MODE_2,      // CPOL : 1  | CPHA : 0
+    SERCOM_SPI_MODE_3       // CPOL : 1  | CPHA : 1
+} SercomSpiClockMode;
+
+typedef enum {
+    SPI_PAD_0_SCK_1 = 0,
+    SPI_PAD_2_SCK_3,
+    SPI_PAD_3_SCK_1,
+    SPI_PAD_0_SCK_3
+} SercomSpiTXPad;
+
+typedef enum {
+    SPI_CHAR_SIZE_8_BITS = 0x0ul,
+    SPI_CHAR_SIZE_9_BITS
+} SercomSpiCharSize;
+
+typedef enum {
+    WIRE_UNKNOWN_STATE = 0x0ul,
+    WIRE_IDLE_STATE,
+    WIRE_OWNER_STATE,
+    WIRE_BUSY_STATE
+} SercomWireBusState;
+
+typedef enum {
+    WIRE_WRITE_FLAG = 0x0ul,
+    WIRE_READ_FLAG
+} SercomWireReadWriteFlag;
+
+typedef enum {
+    WIRE_MASTER_ACT_NO_ACTION = 0,
+    WIRE_MASTER_ACT_REPEAT_START,
+    WIRE_MASTER_ACT_READ,
+    WIRE_MASTER_ACT_STOP
+} SercomMasterCommandWire;
+
+typedef enum {
+    WIRE_MASTER_ACK_ACTION = 0,
+    WIRE_MASTER_NACK_ACTION
+} SercomMasterAckActionWire;
+
+class SERCOM {
+public:
+    SERCOM(Sercom *s) ;
+
+    /* ========== UART ========== */
+    void initUART(SercomUartMode mode, SercomUartSampleRate sampleRate,
+                  uint32_t baudrate = 0);
+    void initFrame(SercomUartCharSize charSize,
+                   SercomDataOrder dataOrder, SercomParityMode parityMode,
+                   SercomNumberStopBit nbStopBits);
+    void initPads(SercomUartTXPad txPad, SercomRXPad rxPad);
+
+    void resetUART(void);
+    void enableUART(void);
+    void flushUART(void);
+    void clearStatusUART(void);
+    bool availableDataUART(void);
+    bool isBufferOverflowErrorUART(void);
+    bool isFrameErrorUART(void);
+    void clearFrameErrorUART(void);
+    bool isParityErrorUART(void);
+    bool isDataRegisterEmptyUART(void);
+    uint8_t readDataUART(void);
+    int writeDataUART(uint8_t data);
+    bool isUARTError();
+    void acknowledgeUARTError();
+    void enableDataRegisterEmptyInterruptUART();
+    void disableDataRegisterEmptyInterruptUART();
+
+    /* ========== SPI ========== */
+    void initSPI(SercomSpiTXPad mosi, SercomRXPad miso,
+                 SercomSpiCharSize charSize, SercomDataOrder dataOrder);
+    void initSPIClock(SercomSpiClockMode clockMode, uint32_t baudrate);
+
+    void resetSPI(void);
+    void enableSPI(void);
+    void disableSPI(void);
+    void setDataOrderSPI(SercomDataOrder dataOrder);
+    SercomDataOrder getDataOrderSPI(void);
+    void setBaudrateSPI(uint8_t divider);
+    void setClockModeSPI(SercomSpiClockMode clockMode);
+    uint8_t transferDataSPI(uint8_t data);
+    bool isBufferOverflowErrorSPI(void);
+    bool isDataRegisterEmptySPI(void);
+    bool isTransmitCompleteSPI(void);
+    bool isReceiveCompleteSPI(void);
+
+    /* ========== WIRE ========== */
+    void initSlaveWIRE(uint8_t address, bool enableGeneralCall = false);
+    void initMasterWIRE(uint32_t baudrate);
+
+    void resetWIRE(void);
+    void enableWIRE(void);
+    void disableWIRE(void);
+    void prepareNackBitWIRE(void);
+    void prepareAckBitWIRE(void);
+    void prepareCommandBitsWire(uint8_t cmd);
+    bool startTransmissionWIRE(uint8_t address, SercomWireReadWriteFlag flag);
+    bool sendDataMasterWIRE(uint8_t data);
+    bool sendDataSlaveWIRE(uint8_t data);
+    bool isMasterWIRE(void);
+    bool isSlaveWIRE(void);
+    bool isBusIdleWIRE(void);
+    bool isBusOwnerWIRE(void);
+    bool isDataReadyWIRE(void);
+    bool isStopDetectedWIRE(void);
+    bool isRestartDetectedWIRE(void);
+    bool isAddressMatch(void);
+    bool isMasterReadOperationWIRE(void);
+    bool isRXNackReceivedWIRE(void);
+    int availableWIRE(void);
+    uint8_t readDataWIRE(void);
+
+private:
+    Sercom *sercom;
+    uint8_t calculateBaudrateSynchronous(uint32_t baudrate);
+    uint32_t division(uint32_t dividend, uint32_t divisor);
+    void initClockNVIC(void);
+};
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Tone.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Tone.cpp
new file mode 100644
index 000000000..0cb0c3cec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Tone.cpp
@@ -0,0 +1,80 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+#include "Arduino.h"
+#include "DigitalInOutHBridge.h"
+#include "SysConnectors.h"
+#include "SysManager.h"
+#include "WVariant.h"
+#include "variant.h"
+#include <Common.h>
+#include <sam.h>
+
+namespace ClearCore {
+extern SysManager SysMgr;
+}
+
+// Board resource controller
+extern const uint32_t SystemCoreClock;
+uint32_t toneMaxFrequency = SystemCoreClock / 2;
+
+void noTone(uint8_t outputPin) {
+    ClearCore::Connector *myConnector =
+        ClearCore::SysMgr.ConnectorByIndex(static_cast<ClearCorePins>(outputPin));
+    // Only playing tones on the H-Bridge connectors
+    if (myConnector->Type() != ClearCore::Connector::H_BRIDGE_TYPE) {
+        return;
+    }
+
+    if (static_cast<ClearCore::DigitalInOutHBridge *>(myConnector)->ToneActiveState()
+            != ClearCore::DigitalInOutHBridge::ToneState::TONE_TIMED) {
+        // Stop the tone on the specified pin
+        static_cast<ClearCore::DigitalInOutHBridge *>(myConnector)->ToneStop();
+    }
+}
+
+void tone(
+    unsigned char outputPin, unsigned int frequency, unsigned long duration) {
+
+    ClearCore::Connector *myConnector =
+        ClearCore::SysMgr.ConnectorByIndex(static_cast<ClearCorePins>(outputPin));
+    // Only playing tones on the H-Bridge connectors
+    if (myConnector->Type() != ClearCore::Connector::H_BRIDGE_TYPE) {
+        return;
+    }
+
+    // Put the pin in tone mode
+    static_cast<ClearCore::DigitalInOutHBridge *>(myConnector)
+        ->Mode(ClearCore::DigitalInOutHBridge::OUTPUT_TONE);
+
+    static_cast<ClearCore::DigitalInOutHBridge *>(myConnector)
+        ->ToneTimed(frequency, duration);
+}
+
+void toneVolume(unsigned char outputPin, float volume) {
+
+    ClearCore::Connector *myConnector =
+        ClearCore::SysMgr.ConnectorByIndex(static_cast<ClearCorePins>(outputPin));
+    // Only playing tones on the H-Bridge connectors
+    if (myConnector->Type() != ClearCore::Connector::H_BRIDGE_TYPE) {
+        return;
+    }
+
+    // Set the tone amplitude for this pin
+    static_cast<ClearCore::DigitalInOutHBridge *>(myConnector)
+        ->ToneAmplitude(static_cast<int16_t>(volume * INT16_MAX));
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Uart.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Uart.cpp
new file mode 100644
index 000000000..51562b96d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Uart.cpp
@@ -0,0 +1,192 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "Uart.h"
+#include "Arduino.h"
+#include "SerialDriver.h"
+#include "SysConnectors.h"
+#include "SysManager.h"
+#include "Common.h"
+
+// Board resource controller
+namespace ClearCore {
+extern SysManager SysMgr;
+}
+
+Uart::Uart(ClearCorePins connectorPin, bool isUsbCon) {
+    m_serial = nullptr;
+    m_serialConnector = nullptr;
+
+    ClearCore::Connector *con =
+        ClearCore::SysMgr.ConnectorByIndex(connectorPin);
+    if (isUsbCon) {
+        ClearCore::SerialUsb *serialUsb =
+            static_cast<ClearCore::SerialUsb *>(con);
+        m_serial = static_cast<ClearCore::ISerial *>(serialUsb);
+    }
+    else {
+        m_serialConnector = static_cast<ClearCore::SerialDriver *>(con);
+        m_serial = static_cast<ClearCore::ISerial *>(m_serialConnector);
+    }
+}
+
+void Uart::begin(unsigned long baudrate) {
+    if (m_serial) {
+        m_serial->PortClose();
+        m_serial->Speed(baudrate);
+        m_serial->PortOpen();
+    }
+}
+
+void Uart::begin(unsigned long baudrate, uint16_t config) {
+    if (m_serial) {
+        m_serial->PortClose();
+        m_serial->Speed(baudrate);
+        m_serial->CharSize(extractCharSize(config));
+        m_serial->Parity(extractParity(config));
+        m_serial->PortOpen();
+        m_serial->StopBits(extractNbStopBit(config));
+    }
+}
+
+void Uart::end() {
+    m_serial->PortClose();
+}
+
+void Uart::flush() {
+    m_serial->WaitForTransmitIdle();
+    m_serial->Flush();
+}
+
+void Uart::flushInput() {
+    m_serial->FlushInput();
+}
+
+int Uart::available() {
+    return m_serial ? m_serial->AvailableForRead() : 0;
+}
+
+int Uart::availableForWrite() {
+    return m_serial ? m_serial->AvailableForWrite() : 0;
+}
+
+int Uart::peek() {
+    return m_serial ? m_serial->CharPeek() : -1;
+}
+
+int Uart::read() {
+    return m_serial ? m_serial->CharGet() : -1;
+}
+
+size_t Uart::write(const uint8_t data) {
+    if (m_serial) {
+        m_serial->SendChar(data);
+        // The serial connector returns nothing, but return that one byte
+        // was written to conform to the arduino standard for write()
+        return 1;
+    }
+
+    return 0;
+}
+
+uint8_t Uart::extractNbStopBit(uint16_t config) {
+    switch (config & SERIAL_STOP_BIT_MASK) {
+        case SERIAL_STOP_BIT_1:
+        default:
+            return 1;
+
+        case SERIAL_STOP_BIT_2:
+            return 2;
+    }
+}
+
+uint8_t Uart::extractCharSize(uint16_t config) {
+    switch (config & SERIAL_DATA_MASK) {
+        case SERIAL_DATA_5:
+            return 5;
+
+        case SERIAL_DATA_6:
+            return 6;
+
+        case SERIAL_DATA_7:
+            return 7;
+
+        case SERIAL_DATA_8:
+        default:
+            return 8;
+    }
+}
+
+ClearCore::ISerial::Parities Uart::extractParity(uint16_t config) {
+    switch (config & SERIAL_PARITY_MASK) {
+        case SERIAL_PARITY_NONE:
+        default:
+            return ClearCore::ISerial::Parities::PARITY_N;
+
+        case SERIAL_PARITY_EVEN:
+            return ClearCore::ISerial::Parities::PARITY_E;
+
+        case SERIAL_PARITY_ODD:
+            return ClearCore::ISerial::Parities::PARITY_O;
+    }
+}
+
+// Get or set TTL on the Serial port
+void Uart::ttl(bool newState) {
+    if (m_serialConnector) {
+        if (newState) {
+            m_serialConnector->Mode(ClearCore::SerialDriver::TTL);
+        }
+        else {
+            m_serialConnector->Mode(ClearCore::SerialDriver::RS232);
+        }
+    }
+}
+bool Uart::ttl() {
+    if (m_serialConnector) {
+        return (m_serialConnector->Mode() == ClearCore::SerialDriver::TTL);
+    }
+    return false;
+}
+
+Uart::operator bool() {
+    if (m_serial) {
+        return (bool) *m_serial;
+    }
+
+    return false;
+}
+
+// Serial Constants for Arduino users
+Uart Serial(CLEARCORE_PIN_USB, true);
+Uart Serial0(CLEARCORE_PIN_COM0);
+Uart Serial1(CLEARCORE_PIN_COM1);
+
+// Weak definitions for the serial event runner and handlers
+// These can be overridden by the user's functions if needed
+void serialEventRun(void) {
+    if (serialEvent && Serial.available()) {
+        serialEvent();
+    }
+    if (serialEvent0 && Serial0.available()) {
+        serialEvent0();
+    }
+    if (serialEvent1 && Serial1.available()) {
+        serialEvent1();
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Uart.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Uart.h
new file mode 100644
index 000000000..e951c65fb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Uart.h
@@ -0,0 +1,60 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "SerialDriver.h"
+#include "SerialUsb.h"
+#include "SysConnectors.h"
+#include "SysManager.h"
+#include "HardwareSerial.h"
+#include "SERCOM.h"
+
+class Uart : public HardwareSerial {
+public:
+    Uart(ClearCorePins connectorPin, bool isUsbCon = false);
+    void begin(unsigned long baudRate);
+    void begin(unsigned long baudrate, uint16_t config);
+    void end();
+    int available();
+    int availableForWrite();
+    int peek();
+    int read();
+    void flush();
+    void flushInput();
+    size_t write(const uint8_t data);
+    void ttl(bool newState);
+    bool ttl();
+    using Print::write; // pull in write(str) and write(buf, size) from Print
+
+    operator bool();
+
+private:
+
+    ClearCore::ISerial *m_serial;
+    ClearCore::SerialDriver *m_serialConnector;
+
+    uint8_t extractNbStopBit(uint16_t config);
+    uint8_t extractCharSize(uint16_t config);
+    ClearCore::ISerial::Parities extractParity(uint16_t config);
+};
+
+
+extern Uart Serial;
+extern Uart Serial0;
+extern Uart Serial1;
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Udp.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Udp.h
new file mode 100644
index 000000000..ba4b7b92f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/Udp.h
@@ -0,0 +1,105 @@
+/*
+ *  Udp.cpp: Library to send/receive UDP packets.
+ *
+ * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray
+ * for mentioning these)
+ * 1) UDP does not guarantee the order in which assembled UDP packets are
+ * received. This might not happen often in practice, but in larger network
+ * topologies, a UDP packet can be received out of sequence.
+ * 2) UDP does not guard against lost packets - so packets *can* disappear
+ * without the sender being aware of it. Again, this may not be a concern in
+ * practice on small local networks.
+ * For more information, see http://www.cafeaulait.org/course/week12/35.html
+ *
+ * MIT License:
+ * Copyright (c) 2008 Bjoern Hartmann
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * bjoern@cs.stanford.edu 12/30/2008
+ */
+
+#ifndef udp_h
+#define udp_h
+
+#include <Stream.h>
+#include <IPAddress.h>
+
+class UDP : public Stream {
+
+public:
+    // initialize, start listening on specified port. Returns 1 if successful, 0
+    // if there are no sockets available to use
+    virtual uint8_t begin(uint16_t) = 0;
+    virtual uint8_t beginMulticast(IPAddress, uint16_t) {
+        // initialize, start listening on specified multicast IP address and
+        // port. Returns 1 if successful, 0 on failure
+        return 0;
+    }
+    virtual void stop() = 0; // Finish with the UDP socket
+
+    // Sending UDP packets
+
+    // Start building up a packet to send to the remote host specific in ip and
+    // port
+    // Returns 1 if successful, 0 if there was a problem with the supplied IP
+    // address or port
+    virtual int beginPacket(IPAddress ip, uint16_t port) = 0;
+    // Start building up a packet to send to the remote host specific in host
+    // and port
+    // Returns 1 if successful, 0 if there was a problem resolving the hostname
+    // or port
+    virtual int beginPacket(const char *host, uint16_t port) = 0;
+    // Finish off this packet and send it
+    // Returns 1 if the packet was sent successfully, 0 if there was an error
+    virtual int endPacket() = 0;
+    // Write a single byte into the packet
+    virtual size_t write(uint8_t) = 0;
+    // Write size bytes from buffer into the packet
+    virtual size_t write(const uint8_t *buffer, size_t size) = 0;
+
+    // Start processing the next available incoming packet
+    // Returns the size of the packet in bytes, or 0 if no packets are available
+    virtual int parsePacket() = 0;
+    // Number of bytes remaining in the current packet
+    virtual int available() = 0;
+    // Read a single byte from the current packet
+    virtual int read() = 0;
+    // Read up to len bytes from the current packet and place them into buffer
+    // Returns the number of bytes read, or 0 if none are available
+    virtual int read(unsigned char *buffer, size_t len) = 0;
+    // Read up to len characters from the current packet and place them into
+    // buffer
+    // Returns the number of characters read, or 0 if none are available
+    virtual int read(char *buffer, size_t len) = 0;
+    // Return the next byte from the current packet without moving on to the
+    // next byte
+    virtual int peek() = 0;
+    virtual void flush() = 0;   // Finish reading the current packet
+
+    // Return the IP address of the host who sent the current incoming packet
+    virtual IPAddress remoteIP() = 0;
+    // Return the port of the host who sent the current incoming packet
+    virtual uint16_t remotePort() = 0;
+protected:
+    uint8_t *rawIPAddress(IPAddress &addr) {
+        return addr.raw_address();
+    };
+};
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/WMath.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/WMath.cpp
new file mode 100644
index 000000000..3100a250b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/WMath.cpp
@@ -0,0 +1,46 @@
+/*
+    Copyright (c) 2014 Arduino.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+extern "C" {
+#include "stdlib.h"
+#include "stdint.h"
+}
+
+void randomSeed(uint32_t dwSeed) {
+    if (dwSeed != 0) {
+        srand(dwSeed);
+    }
+}
+
+long random(long howbig) {
+    if (howbig == 0) {
+        return 0;
+    }
+
+    return rand() % howbig;
+}
+
+long random(long howsmall, long howbig) {
+    if (howsmall >= howbig) {
+        return howsmall;
+    }
+
+    long diff = howbig - howsmall;
+
+    return random(diff) + howsmall;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/WVariant.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/WVariant.h
new file mode 100644
index 000000000..fe83aef4f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/WVariant.h
@@ -0,0 +1,54 @@
+/*
+  Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include <stdint.h>
+#include "sam.h"
+#include "Common.h"
+#include "pins_arduino.h"
+#include "SysConnectors.h"
+#include "SysManager.h"
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_BUILTIN CLEARCORE_PIN_LED
+
+/**
+  PIN Modes
+**/
+typedef enum {
+    CLEARCORE_MODE_INPUT = INPUT, // Match standard name
+    CLEARCORE_MODE_OUTPUT = OUTPUT,
+    CLEARCORE_MODE_ANALOG
+} ClearCorePinModes;
+
+// Parallel version of pinMode to setup ClearCore "connectors" using the
+// connector index.
+void pinModeClearCore(ClearCorePins thePin, PinMode ulMode);
+
+// Mapping of ClearCore pins to interrupts
+pin_size_t digitalPinToInterrupt(pin_size_t pin);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/abi.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/abi.cpp
new file mode 100644
index 000000000..06e1af116
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/abi.cpp
@@ -0,0 +1,41 @@
+/*
+  Copyright (c) 2014 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <stdlib.h>
+
+extern "C" void __cxa_pure_virtual(void) __attribute__((__noreturn__));
+extern "C" void __cxa_deleted_virtual(void) __attribute__((__noreturn__));
+
+extern "C"  {
+    void __cxa_pure_virtual(void) {
+        // We might want to write some diagnostics to uart in this case
+        //std::terminate();
+        while (1) {
+            continue;
+        }
+    }
+
+    void __cxa_deleted_virtual(void) {
+        // We might want to write some diagnostics to uart in this case
+        //std::terminate();
+        while (1) {
+            continue;
+        }
+    }
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/ArduinoAPI.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/ArduinoAPI.h
new file mode 100644
index 000000000..1472c0815
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/ArduinoAPI.h
@@ -0,0 +1,54 @@
+/*
+    Arduino API main include
+    Copyright (c) 2016 Arduino LLC. All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef ARDUINO_API_H
+#define ARDUINO_API_H
+
+// version 1.0.0
+#define ARDUINO_API_VERSION 10000
+
+#include "Binary.h"
+
+#ifdef __cplusplus
+#include "Client.h"
+#include "HardwareI2C.h"
+#include "HardwareSerial.h"
+#include "Interrupts.h"
+#include "IPAddress.h"
+#include "Print.h"
+#include "Printable.h"
+#include "Server.h"
+#include "ArduinoString.h"
+#include "Stream.h"
+#include "Uart.h"
+#include "Udp.h"
+#include "WCharacter.h"
+#endif
+
+/* Standard C library includes */
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <math.h>
+
+// Misc Arduino core functions
+#include "Common.h"
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/ArduinoString.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/ArduinoString.h
new file mode 100644
index 000000000..feb911004
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/ArduinoString.h
@@ -0,0 +1,342 @@
+/*
+    String library for Wiring & Arduino
+    ...mostly rewritten by Paul Stoffregen...
+    Copyright (c) 2009-10 Hernando Barragan.  All right reserved.
+    Copyright 2011, Paul Stoffregen, paul@pjrc.com
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#if defined(__AVR__)
+#include "avr/pgmspace.h"
+#else
+#include "deprecated-avr-comp/avr/pgmspace.h"
+#endif
+
+// When compiling programs with this class, the following gcc parameters
+// dramatically increase performance and memory (RAM) efficiency, typically
+// with little or no increase in code size.
+//     -felide-constructors
+//     -std=c++0x
+
+class __FlashStringHelper;
+#define F(string_literal) (reinterpret_cast<const __FlashStringHelper *>(PSTR(string_literal)))
+
+// An inherited class for holding the result of a concatenation.  These
+// result objects are assumed to be writable by subsequent concatenations.
+class StringSumHelper;
+
+// The string class
+class String {
+    // use a function pointer to allow for "if (s)" without the
+    // complications of an operator bool(). for more information, see:
+    // http://www.artima.com/cppsource/safebool.html
+    typedef void (String::*StringIfHelperType)() const;
+    void StringIfHelper() const {}
+
+public:
+    // constructors
+    // creates a copy of the initial value.
+    // if the initial value is null or invalid, or if memory allocation
+    // fails, the string will be marked as invalid (i.e. "if (s)" will
+    // be false).
+    String(const char *cstr = "");
+    String(const String &str);
+    String(const __FlashStringHelper *str);
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+    String(String &&rval);
+    String(StringSumHelper &&rval);
+#endif
+    explicit String(char c);
+    explicit String(unsigned char, unsigned char base = 10);
+    explicit String(int, unsigned char base = 10);
+    explicit String(unsigned int, unsigned char base = 10);
+    explicit String(long, unsigned char base = 10);
+    explicit String(unsigned long, unsigned char base = 10);
+    explicit String(float, unsigned char decimalPlaces = 2);
+    explicit String(double, unsigned char decimalPlaces = 2);
+    ~String(void);
+
+    // memory management
+    // return true on success, false on failure (in which case, the string
+    // is left unchanged).  reserve(0), if successful, will validate an
+    // invalid string (i.e., "if (s)" will be true afterwards)
+    unsigned char reserve(unsigned int size);
+    inline unsigned int length(void) const {
+        return len;
+    }
+
+    // creates a copy of the assigned value.  if the value is null or
+    // invalid, or if the memory allocation fails, the string will be
+    // marked as invalid ("if (s)" will be false).
+    String &operator = (const String &rhs);
+    String &operator = (const char *cstr);
+    String &operator = (const __FlashStringHelper *str);
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+    String &operator = (String &&rval);
+    String &operator = (StringSumHelper &&rval);
+#endif
+
+    // concatenate (works w/ built-in types)
+
+    // returns true on success, false on failure (in which case, the string
+    // is left unchanged).  if the argument is null or invalid, the
+    // concatenation is considered unsucessful.
+    unsigned char concat(const String &str);
+    unsigned char concat(const char *cstr);
+    unsigned char concat(char c);
+    unsigned char concat(unsigned char c);
+    unsigned char concat(int num);
+    unsigned char concat(unsigned int num);
+    unsigned char concat(long num);
+    unsigned char concat(unsigned long num);
+    unsigned char concat(float num);
+    unsigned char concat(double num);
+    unsigned char concat(const __FlashStringHelper *str);
+
+    // if there's not enough memory for the concatenated value, the string
+    // will be left unchanged (but this isn't signalled in any way)
+    String &operator += (const String &rhs) {
+        concat(rhs);
+        return (*this);
+    }
+    String &operator += (const char *cstr) {
+        concat(cstr);
+        return (*this);
+    }
+    String &operator += (char c) {
+        concat(c);
+        return (*this);
+    }
+    String &operator += (unsigned char num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (int num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (unsigned int num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (long num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (unsigned long num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (float num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (double num) {
+        concat(num);
+        return (*this);
+    }
+    String &operator += (const __FlashStringHelper *str) {
+        concat(str);
+        return (*this);
+    }
+
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, const String &rhs);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, const char *cstr);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, char c);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, unsigned char num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, int num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, unsigned int num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, long num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, unsigned long num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, float num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, double num);
+    friend StringSumHelper &operator +
+    (const StringSumHelper &lhs, const __FlashStringHelper *rhs);
+
+    // comparison (only works w/ Strings and "strings")
+    operator StringIfHelperType() const {
+        return buffer ? &String::StringIfHelper : 0;
+    }
+    int compareTo(const String &s) const;
+    int compareTo(const char *cstr) const;
+    unsigned char equals(const String &s) const;
+    unsigned char equals(const char *cstr) const;
+
+    friend unsigned char operator == (const String &a, const String &b) {
+        return a.equals(b);
+    }
+    friend unsigned char operator == (const String &a, const char   *b) {
+        return a.equals(b);
+    }
+    friend unsigned char operator == (const char   *a, const String &b) {
+        return b == a;
+    }
+    friend unsigned char operator < (const String &a, const String &b) {
+        return a.compareTo(b) < 0;
+    }
+    friend unsigned char operator < (const String &a, const char   *b) {
+        return a.compareTo(b) < 0;
+    }
+    friend unsigned char operator < (const char   *a, const String &b) {
+        return b.compareTo(a) > 0;
+    }
+
+    friend unsigned char operator != (const String &a, const String &b) {
+        return !(a == b);
+    }
+    friend unsigned char operator != (const String &a, const char   *b) {
+        return !(a == b);
+    }
+    friend unsigned char operator != (const char   *a, const String &b) {
+        return !(a == b);
+    }
+    friend unsigned char operator > (const String &a, const String &b) {
+        return b < a;
+    }
+    friend unsigned char operator > (const String &a, const char   *b) {
+        return b < a;
+    }
+    friend unsigned char operator > (const char   *a, const String &b) {
+        return b < a;
+    }
+    friend unsigned char operator <= (const String &a, const String &b) {
+        return !(b < a);
+    }
+    friend unsigned char operator <= (const String &a, const char   *b) {
+        return !(b < a);
+    }
+    friend unsigned char operator <= (const char   *a, const String &b) {
+        return !(b < a);
+    }
+    friend unsigned char operator >= (const String &a, const String &b) {
+        return !(a < b);
+    }
+    friend unsigned char operator >= (const String &a, const char   *b) {
+        return !(a < b);
+    }
+    friend unsigned char operator >= (const char   *a, const String &b) {
+        return !(a < b);
+    }
+
+    unsigned char equalsIgnoreCase(const String &s) const;
+    unsigned char startsWith(const String &prefix) const;
+    unsigned char startsWith(const String &prefix, unsigned int offset) const;
+    unsigned char endsWith(const String &suffix) const;
+
+    // character acccess
+    char charAt(unsigned int index) const;
+    void setCharAt(unsigned int index, char c);
+    char operator [](unsigned int index) const;
+    char &operator [](unsigned int index);
+    void getBytes(unsigned char *buf, unsigned int bufsize,
+                  unsigned int index = 0) const;
+    void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0)const {
+        getBytes((unsigned char *)buf, bufsize, index);
+    }
+    const char *c_str() const {
+        return buffer;
+    }
+    char *begin() {
+        return buffer;
+    }
+    char *end() {
+        return buffer + length();
+    }
+    const char *begin() const {
+        return c_str();
+    }
+    const char *end() const {
+        return c_str() + length();
+    }
+
+    // search
+    int indexOf(char ch) const;
+    int indexOf(char ch, unsigned int fromIndex) const;
+    int indexOf(const String &str) const;
+    int indexOf(const String &str, unsigned int fromIndex) const;
+    int lastIndexOf(char ch) const;
+    int lastIndexOf(char ch, unsigned int fromIndex) const;
+    int lastIndexOf(const String &str) const;
+    int lastIndexOf(const String &str, unsigned int fromIndex) const;
+    String substring(unsigned int beginIndex) const {
+        return substring(beginIndex, len);
+    };
+    String substring(unsigned int beginIndex, unsigned int endIndex) const;
+
+    // modification
+    void replace(char find, char replace);
+    void replace(const String &find, const String &replace);
+    void remove(unsigned int index);
+    void remove(unsigned int index, unsigned int count);
+    void toLowerCase(void);
+    void toUpperCase(void);
+    void trim(void);
+
+    // parsing/conversion
+    long toInt(void) const;
+    float toFloat(void) const;
+    double toDouble(void) const;
+
+protected:
+    char *buffer;           // the actual char array
+    unsigned int capacity;  // the array length minus one (for the '\0')
+    unsigned int len;       // the String length (not counting the '\0')
+
+    void init(void);
+    void invalidate(void);
+    unsigned char changeBuffer(unsigned int maxStrLen);
+    unsigned char concat(const char *cstr, unsigned int length);
+
+    // copy and move
+    String &copy(const char *cstr, unsigned int length);
+    String &copy(const __FlashStringHelper *pstr, unsigned int length);
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+    void move(String &rhs);
+#endif
+};
+
+class StringSumHelper : public String {
+public:
+    StringSumHelper(const String &s) : String(s) {}
+    StringSumHelper(const char *p) : String(p) {}
+    StringSumHelper(char c) : String(c) {}
+    StringSumHelper(unsigned char num) : String(num) {}
+    StringSumHelper(int num) : String(num) {}
+    StringSumHelper(unsigned int num) : String(num) {}
+    StringSumHelper(long num) : String(num) {}
+    StringSumHelper(unsigned long num) : String(num) {}
+    StringSumHelper(float num) : String(num) {}
+    StringSumHelper(double num) : String(num) {}
+};
+
+#endif  // __cplusplus
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Binary.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Binary.h
new file mode 100644
index 000000000..ac0a7c1d4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Binary.h
@@ -0,0 +1,552 @@
+/*
+    binary.h - Definitions for binary constants
+    Deprecated -- use 0b binary literals instead
+    Copyright (c) 2006 David A. Mellis.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef Binary_h
+#define Binary_h
+
+/* If supported, 0b binary literals are preferable to these constants.
+ * In that case, warn the user about these being deprecated (if possible). */
+#if __cplusplus >= 201402L
+    /* C++14 introduces binary literals; C++11 introduces [[deprecated()]] */
+    #define DEPRECATED(x) [[deprecated("use " #x " instead")]]
+#elif __GNUC__ >= 6
+    /*GCC 4.3 supports binary literals; GCC 6 supports __deprecated__ on enums*/
+    #define DEPRECATED(x) __attribute__ ((__deprecated__ ("use " #x " instead")))
+#else
+    /* binary literals not supported, or "deprecated" warning not displayable */
+    #define DEPRECATED(x)
+#endif
+
+enum {
+    B0        DEPRECATED(0b0       ) = 0,
+    B00       DEPRECATED(0b00      ) = 0,
+    B000      DEPRECATED(0b000     ) = 0,
+    B0000     DEPRECATED(0b0000    ) = 0,
+    B00000    DEPRECATED(0b00000   ) = 0,
+    B000000   DEPRECATED(0b000000  ) = 0,
+    B0000000  DEPRECATED(0b0000000 ) = 0,
+    B00000000 DEPRECATED(0b00000000) = 0,
+    B1        DEPRECATED(0b1       ) = 1,
+    B01       DEPRECATED(0b01      ) = 1,
+    B001      DEPRECATED(0b001     ) = 1,
+    B0001     DEPRECATED(0b0001    ) = 1,
+    B00001    DEPRECATED(0b00001   ) = 1,
+    B000001   DEPRECATED(0b000001  ) = 1,
+    B0000001  DEPRECATED(0b0000001 ) = 1,
+    B00000001 DEPRECATED(0b00000001) = 1,
+    B10       DEPRECATED(0b10      ) = 2,
+    B010      DEPRECATED(0b010     ) = 2,
+    B0010     DEPRECATED(0b0010    ) = 2,
+    B00010    DEPRECATED(0b00010   ) = 2,
+    B000010   DEPRECATED(0b000010  ) = 2,
+    B0000010  DEPRECATED(0b0000010 ) = 2,
+    B00000010 DEPRECATED(0b00000010) = 2,
+    B11       DEPRECATED(0b11      ) = 3,
+    B011      DEPRECATED(0b011     ) = 3,
+    B0011     DEPRECATED(0b0011    ) = 3,
+    B00011    DEPRECATED(0b00011   ) = 3,
+    B000011   DEPRECATED(0b000011  ) = 3,
+    B0000011  DEPRECATED(0b0000011 ) = 3,
+    B00000011 DEPRECATED(0b00000011) = 3,
+    B100      DEPRECATED(0b100     ) = 4,
+    B0100     DEPRECATED(0b0100    ) = 4,
+    B00100    DEPRECATED(0b00100   ) = 4,
+    B000100   DEPRECATED(0b000100  ) = 4,
+    B0000100  DEPRECATED(0b0000100 ) = 4,
+    B00000100 DEPRECATED(0b00000100) = 4,
+    B101      DEPRECATED(0b101     ) = 5,
+    B0101     DEPRECATED(0b0101    ) = 5,
+    B00101    DEPRECATED(0b00101   ) = 5,
+    B000101   DEPRECATED(0b000101  ) = 5,
+    B0000101  DEPRECATED(0b0000101 ) = 5,
+    B00000101 DEPRECATED(0b00000101) = 5,
+    B110      DEPRECATED(0b110     ) = 6,
+    B0110     DEPRECATED(0b0110    ) = 6,
+    B00110    DEPRECATED(0b00110   ) = 6,
+    B000110   DEPRECATED(0b000110  ) = 6,
+    B0000110  DEPRECATED(0b0000110 ) = 6,
+    B00000110 DEPRECATED(0b00000110) = 6,
+    B111      DEPRECATED(0b111     ) = 7,
+    B0111     DEPRECATED(0b0111    ) = 7,
+    B00111    DEPRECATED(0b00111   ) = 7,
+    B000111   DEPRECATED(0b000111  ) = 7,
+    B0000111  DEPRECATED(0b0000111 ) = 7,
+    B00000111 DEPRECATED(0b00000111) = 7,
+    B1000     DEPRECATED(0b1000    ) = 8,
+    B01000    DEPRECATED(0b01000   ) = 8,
+    B001000   DEPRECATED(0b001000  ) = 8,
+    B0001000  DEPRECATED(0b0001000 ) = 8,
+    B00001000 DEPRECATED(0b00001000) = 8,
+    B1001     DEPRECATED(0b1001    ) = 9,
+    B01001    DEPRECATED(0b01001   ) = 9,
+    B001001   DEPRECATED(0b001001  ) = 9,
+    B0001001  DEPRECATED(0b0001001 ) = 9,
+    B00001001 DEPRECATED(0b00001001) = 9,
+    B1010     DEPRECATED(0b1010    ) = 10,
+    B01010    DEPRECATED(0b01010   ) = 10,
+    B001010   DEPRECATED(0b001010  ) = 10,
+    B0001010  DEPRECATED(0b0001010 ) = 10,
+    B00001010 DEPRECATED(0b00001010) = 10,
+    B1011     DEPRECATED(0b1011    ) = 11,
+    B01011    DEPRECATED(0b01011   ) = 11,
+    B001011   DEPRECATED(0b001011  ) = 11,
+    B0001011  DEPRECATED(0b0001011 ) = 11,
+    B00001011 DEPRECATED(0b00001011) = 11,
+    B1100     DEPRECATED(0b1100    ) = 12,
+    B01100    DEPRECATED(0b01100   ) = 12,
+    B001100   DEPRECATED(0b001100  ) = 12,
+    B0001100  DEPRECATED(0b0001100 ) = 12,
+    B00001100 DEPRECATED(0b00001100) = 12,
+    B1101     DEPRECATED(0b1101    ) = 13,
+    B01101    DEPRECATED(0b01101   ) = 13,
+    B001101   DEPRECATED(0b001101  ) = 13,
+    B0001101  DEPRECATED(0b0001101 ) = 13,
+    B00001101 DEPRECATED(0b00001101) = 13,
+    B1110     DEPRECATED(0b1110    ) = 14,
+    B01110    DEPRECATED(0b01110   ) = 14,
+    B001110   DEPRECATED(0b001110  ) = 14,
+    B0001110  DEPRECATED(0b0001110 ) = 14,
+    B00001110 DEPRECATED(0b00001110) = 14,
+    B1111     DEPRECATED(0b1111    ) = 15,
+    B01111    DEPRECATED(0b01111   ) = 15,
+    B001111   DEPRECATED(0b001111  ) = 15,
+    B0001111  DEPRECATED(0b0001111 ) = 15,
+    B00001111 DEPRECATED(0b00001111) = 15,
+    B10000    DEPRECATED(0b10000   ) = 16,
+    B010000   DEPRECATED(0b010000  ) = 16,
+    B0010000  DEPRECATED(0b0010000 ) = 16,
+    B00010000 DEPRECATED(0b00010000) = 16,
+    B10001    DEPRECATED(0b10001   ) = 17,
+    B010001   DEPRECATED(0b010001  ) = 17,
+    B0010001  DEPRECATED(0b0010001 ) = 17,
+    B00010001 DEPRECATED(0b00010001) = 17,
+    B10010    DEPRECATED(0b10010   ) = 18,
+    B010010   DEPRECATED(0b010010  ) = 18,
+    B0010010  DEPRECATED(0b0010010 ) = 18,
+    B00010010 DEPRECATED(0b00010010) = 18,
+    B10011    DEPRECATED(0b10011   ) = 19,
+    B010011   DEPRECATED(0b010011  ) = 19,
+    B0010011  DEPRECATED(0b0010011 ) = 19,
+    B00010011 DEPRECATED(0b00010011) = 19,
+    B10100    DEPRECATED(0b10100   ) = 20,
+    B010100   DEPRECATED(0b010100  ) = 20,
+    B0010100  DEPRECATED(0b0010100 ) = 20,
+    B00010100 DEPRECATED(0b00010100) = 20,
+    B10101    DEPRECATED(0b10101   ) = 21,
+    B010101   DEPRECATED(0b010101  ) = 21,
+    B0010101  DEPRECATED(0b0010101 ) = 21,
+    B00010101 DEPRECATED(0b00010101) = 21,
+    B10110    DEPRECATED(0b10110   ) = 22,
+    B010110   DEPRECATED(0b010110  ) = 22,
+    B0010110  DEPRECATED(0b0010110 ) = 22,
+    B00010110 DEPRECATED(0b00010110) = 22,
+    B10111    DEPRECATED(0b10111   ) = 23,
+    B010111   DEPRECATED(0b010111  ) = 23,
+    B0010111  DEPRECATED(0b0010111 ) = 23,
+    B00010111 DEPRECATED(0b00010111) = 23,
+    B11000    DEPRECATED(0b11000   ) = 24,
+    B011000   DEPRECATED(0b011000  ) = 24,
+    B0011000  DEPRECATED(0b0011000 ) = 24,
+    B00011000 DEPRECATED(0b00011000) = 24,
+    B11001    DEPRECATED(0b11001   ) = 25,
+    B011001   DEPRECATED(0b011001  ) = 25,
+    B0011001  DEPRECATED(0b0011001 ) = 25,
+    B00011001 DEPRECATED(0b00011001) = 25,
+    B11010    DEPRECATED(0b11010   ) = 26,
+    B011010   DEPRECATED(0b011010  ) = 26,
+    B0011010  DEPRECATED(0b0011010 ) = 26,
+    B00011010 DEPRECATED(0b00011010) = 26,
+    B11011    DEPRECATED(0b11011   ) = 27,
+    B011011   DEPRECATED(0b011011  ) = 27,
+    B0011011  DEPRECATED(0b0011011 ) = 27,
+    B00011011 DEPRECATED(0b00011011) = 27,
+    B11100    DEPRECATED(0b11100   ) = 28,
+    B011100   DEPRECATED(0b011100  ) = 28,
+    B0011100  DEPRECATED(0b0011100 ) = 28,
+    B00011100 DEPRECATED(0b00011100) = 28,
+    B11101    DEPRECATED(0b11101   ) = 29,
+    B011101   DEPRECATED(0b011101  ) = 29,
+    B0011101  DEPRECATED(0b0011101 ) = 29,
+    B00011101 DEPRECATED(0b00011101) = 29,
+    B11110    DEPRECATED(0b11110   ) = 30,
+    B011110   DEPRECATED(0b011110  ) = 30,
+    B0011110  DEPRECATED(0b0011110 ) = 30,
+    B00011110 DEPRECATED(0b00011110) = 30,
+    B11111    DEPRECATED(0b11111   ) = 31,
+    B011111   DEPRECATED(0b011111  ) = 31,
+    B0011111  DEPRECATED(0b0011111 ) = 31,
+    B00011111 DEPRECATED(0b00011111) = 31,
+    B100000   DEPRECATED(0b100000  ) = 32,
+    B0100000  DEPRECATED(0b0100000 ) = 32,
+    B00100000 DEPRECATED(0b00100000) = 32,
+    B100001   DEPRECATED(0b100001  ) = 33,
+    B0100001  DEPRECATED(0b0100001 ) = 33,
+    B00100001 DEPRECATED(0b00100001) = 33,
+    B100010   DEPRECATED(0b100010  ) = 34,
+    B0100010  DEPRECATED(0b0100010 ) = 34,
+    B00100010 DEPRECATED(0b00100010) = 34,
+    B100011   DEPRECATED(0b100011  ) = 35,
+    B0100011  DEPRECATED(0b0100011 ) = 35,
+    B00100011 DEPRECATED(0b00100011) = 35,
+    B100100   DEPRECATED(0b100100  ) = 36,
+    B0100100  DEPRECATED(0b0100100 ) = 36,
+    B00100100 DEPRECATED(0b00100100) = 36,
+    B100101   DEPRECATED(0b100101  ) = 37,
+    B0100101  DEPRECATED(0b0100101 ) = 37,
+    B00100101 DEPRECATED(0b00100101) = 37,
+    B100110   DEPRECATED(0b100110  ) = 38,
+    B0100110  DEPRECATED(0b0100110 ) = 38,
+    B00100110 DEPRECATED(0b00100110) = 38,
+    B100111   DEPRECATED(0b100111  ) = 39,
+    B0100111  DEPRECATED(0b0100111 ) = 39,
+    B00100111 DEPRECATED(0b00100111) = 39,
+    B101000   DEPRECATED(0b101000  ) = 40,
+    B0101000  DEPRECATED(0b0101000 ) = 40,
+    B00101000 DEPRECATED(0b00101000) = 40,
+    B101001   DEPRECATED(0b101001  ) = 41,
+    B0101001  DEPRECATED(0b0101001 ) = 41,
+    B00101001 DEPRECATED(0b00101001) = 41,
+    B101010   DEPRECATED(0b101010  ) = 42,
+    B0101010  DEPRECATED(0b0101010 ) = 42,
+    B00101010 DEPRECATED(0b00101010) = 42,
+    B101011   DEPRECATED(0b101011  ) = 43,
+    B0101011  DEPRECATED(0b0101011 ) = 43,
+    B00101011 DEPRECATED(0b00101011) = 43,
+    B101100   DEPRECATED(0b101100  ) = 44,
+    B0101100  DEPRECATED(0b0101100 ) = 44,
+    B00101100 DEPRECATED(0b00101100) = 44,
+    B101101   DEPRECATED(0b101101  ) = 45,
+    B0101101  DEPRECATED(0b0101101 ) = 45,
+    B00101101 DEPRECATED(0b00101101) = 45,
+    B101110   DEPRECATED(0b101110  ) = 46,
+    B0101110  DEPRECATED(0b0101110 ) = 46,
+    B00101110 DEPRECATED(0b00101110) = 46,
+    B101111   DEPRECATED(0b101111  ) = 47,
+    B0101111  DEPRECATED(0b0101111 ) = 47,
+    B00101111 DEPRECATED(0b00101111) = 47,
+    B110000   DEPRECATED(0b110000  ) = 48,
+    B0110000  DEPRECATED(0b0110000 ) = 48,
+    B00110000 DEPRECATED(0b00110000) = 48,
+    B110001   DEPRECATED(0b110001  ) = 49,
+    B0110001  DEPRECATED(0b0110001 ) = 49,
+    B00110001 DEPRECATED(0b00110001) = 49,
+    B110010   DEPRECATED(0b110010  ) = 50,
+    B0110010  DEPRECATED(0b0110010 ) = 50,
+    B00110010 DEPRECATED(0b00110010) = 50,
+    B110011   DEPRECATED(0b110011  ) = 51,
+    B0110011  DEPRECATED(0b0110011 ) = 51,
+    B00110011 DEPRECATED(0b00110011) = 51,
+    B110100   DEPRECATED(0b110100  ) = 52,
+    B0110100  DEPRECATED(0b0110100 ) = 52,
+    B00110100 DEPRECATED(0b00110100) = 52,
+    B110101   DEPRECATED(0b110101  ) = 53,
+    B0110101  DEPRECATED(0b0110101 ) = 53,
+    B00110101 DEPRECATED(0b00110101) = 53,
+    B110110   DEPRECATED(0b110110  ) = 54,
+    B0110110  DEPRECATED(0b0110110 ) = 54,
+    B00110110 DEPRECATED(0b00110110) = 54,
+    B110111   DEPRECATED(0b110111  ) = 55,
+    B0110111  DEPRECATED(0b0110111 ) = 55,
+    B00110111 DEPRECATED(0b00110111) = 55,
+    B111000   DEPRECATED(0b111000  ) = 56,
+    B0111000  DEPRECATED(0b0111000 ) = 56,
+    B00111000 DEPRECATED(0b00111000) = 56,
+    B111001   DEPRECATED(0b111001  ) = 57,
+    B0111001  DEPRECATED(0b0111001 ) = 57,
+    B00111001 DEPRECATED(0b00111001) = 57,
+    B111010   DEPRECATED(0b111010  ) = 58,
+    B0111010  DEPRECATED(0b0111010 ) = 58,
+    B00111010 DEPRECATED(0b00111010) = 58,
+    B111011   DEPRECATED(0b111011  ) = 59,
+    B0111011  DEPRECATED(0b0111011 ) = 59,
+    B00111011 DEPRECATED(0b00111011) = 59,
+    B111100   DEPRECATED(0b111100  ) = 60,
+    B0111100  DEPRECATED(0b0111100 ) = 60,
+    B00111100 DEPRECATED(0b00111100) = 60,
+    B111101   DEPRECATED(0b111101  ) = 61,
+    B0111101  DEPRECATED(0b0111101 ) = 61,
+    B00111101 DEPRECATED(0b00111101) = 61,
+    B111110   DEPRECATED(0b111110  ) = 62,
+    B0111110  DEPRECATED(0b0111110 ) = 62,
+    B00111110 DEPRECATED(0b00111110) = 62,
+    B111111   DEPRECATED(0b111111  ) = 63,
+    B0111111  DEPRECATED(0b0111111 ) = 63,
+    B00111111 DEPRECATED(0b00111111) = 63,
+    B1000000  DEPRECATED(0b1000000 ) = 64,
+    B01000000 DEPRECATED(0b01000000) = 64,
+    B1000001  DEPRECATED(0b1000001 ) = 65,
+    B01000001 DEPRECATED(0b01000001) = 65,
+    B1000010  DEPRECATED(0b1000010 ) = 66,
+    B01000010 DEPRECATED(0b01000010) = 66,
+    B1000011  DEPRECATED(0b1000011 ) = 67,
+    B01000011 DEPRECATED(0b01000011) = 67,
+    B1000100  DEPRECATED(0b1000100 ) = 68,
+    B01000100 DEPRECATED(0b01000100) = 68,
+    B1000101  DEPRECATED(0b1000101 ) = 69,
+    B01000101 DEPRECATED(0b01000101) = 69,
+    B1000110  DEPRECATED(0b1000110 ) = 70,
+    B01000110 DEPRECATED(0b01000110) = 70,
+    B1000111  DEPRECATED(0b1000111 ) = 71,
+    B01000111 DEPRECATED(0b01000111) = 71,
+    B1001000  DEPRECATED(0b1001000 ) = 72,
+    B01001000 DEPRECATED(0b01001000) = 72,
+    B1001001  DEPRECATED(0b1001001 ) = 73,
+    B01001001 DEPRECATED(0b01001001) = 73,
+    B1001010  DEPRECATED(0b1001010 ) = 74,
+    B01001010 DEPRECATED(0b01001010) = 74,
+    B1001011  DEPRECATED(0b1001011 ) = 75,
+    B01001011 DEPRECATED(0b01001011) = 75,
+    B1001100  DEPRECATED(0b1001100 ) = 76,
+    B01001100 DEPRECATED(0b01001100) = 76,
+    B1001101  DEPRECATED(0b1001101 ) = 77,
+    B01001101 DEPRECATED(0b01001101) = 77,
+    B1001110  DEPRECATED(0b1001110 ) = 78,
+    B01001110 DEPRECATED(0b01001110) = 78,
+    B1001111  DEPRECATED(0b1001111 ) = 79,
+    B01001111 DEPRECATED(0b01001111) = 79,
+    B1010000  DEPRECATED(0b1010000 ) = 80,
+    B01010000 DEPRECATED(0b01010000) = 80,
+    B1010001  DEPRECATED(0b1010001 ) = 81,
+    B01010001 DEPRECATED(0b01010001) = 81,
+    B1010010  DEPRECATED(0b1010010 ) = 82,
+    B01010010 DEPRECATED(0b01010010) = 82,
+    B1010011  DEPRECATED(0b1010011 ) = 83,
+    B01010011 DEPRECATED(0b01010011) = 83,
+    B1010100  DEPRECATED(0b1010100 ) = 84,
+    B01010100 DEPRECATED(0b01010100) = 84,
+    B1010101  DEPRECATED(0b1010101 ) = 85,
+    B01010101 DEPRECATED(0b01010101) = 85,
+    B1010110  DEPRECATED(0b1010110 ) = 86,
+    B01010110 DEPRECATED(0b01010110) = 86,
+    B1010111  DEPRECATED(0b1010111 ) = 87,
+    B01010111 DEPRECATED(0b01010111) = 87,
+    B1011000  DEPRECATED(0b1011000 ) = 88,
+    B01011000 DEPRECATED(0b01011000) = 88,
+    B1011001  DEPRECATED(0b1011001 ) = 89,
+    B01011001 DEPRECATED(0b01011001) = 89,
+    B1011010  DEPRECATED(0b1011010 ) = 90,
+    B01011010 DEPRECATED(0b01011010) = 90,
+    B1011011  DEPRECATED(0b1011011 ) = 91,
+    B01011011 DEPRECATED(0b01011011) = 91,
+    B1011100  DEPRECATED(0b1011100 ) = 92,
+    B01011100 DEPRECATED(0b01011100) = 92,
+    B1011101  DEPRECATED(0b1011101 ) = 93,
+    B01011101 DEPRECATED(0b01011101) = 93,
+    B1011110  DEPRECATED(0b1011110 ) = 94,
+    B01011110 DEPRECATED(0b01011110) = 94,
+    B1011111  DEPRECATED(0b1011111 ) = 95,
+    B01011111 DEPRECATED(0b01011111) = 95,
+    B1100000  DEPRECATED(0b1100000 ) = 96,
+    B01100000 DEPRECATED(0b01100000) = 96,
+    B1100001  DEPRECATED(0b1100001 ) = 97,
+    B01100001 DEPRECATED(0b01100001) = 97,
+    B1100010  DEPRECATED(0b1100010 ) = 98,
+    B01100010 DEPRECATED(0b01100010) = 98,
+    B1100011  DEPRECATED(0b1100011 ) = 99,
+    B01100011 DEPRECATED(0b01100011) = 99,
+    B1100100  DEPRECATED(0b1100100 ) = 100,
+    B01100100 DEPRECATED(0b01100100) = 100,
+    B1100101  DEPRECATED(0b1100101 ) = 101,
+    B01100101 DEPRECATED(0b01100101) = 101,
+    B1100110  DEPRECATED(0b1100110 ) = 102,
+    B01100110 DEPRECATED(0b01100110) = 102,
+    B1100111  DEPRECATED(0b1100111 ) = 103,
+    B01100111 DEPRECATED(0b01100111) = 103,
+    B1101000  DEPRECATED(0b1101000 ) = 104,
+    B01101000 DEPRECATED(0b01101000) = 104,
+    B1101001  DEPRECATED(0b1101001 ) = 105,
+    B01101001 DEPRECATED(0b01101001) = 105,
+    B1101010  DEPRECATED(0b1101010 ) = 106,
+    B01101010 DEPRECATED(0b01101010) = 106,
+    B1101011  DEPRECATED(0b1101011 ) = 107,
+    B01101011 DEPRECATED(0b01101011) = 107,
+    B1101100  DEPRECATED(0b1101100 ) = 108,
+    B01101100 DEPRECATED(0b01101100) = 108,
+    B1101101  DEPRECATED(0b1101101 ) = 109,
+    B01101101 DEPRECATED(0b01101101) = 109,
+    B1101110  DEPRECATED(0b1101110 ) = 110,
+    B01101110 DEPRECATED(0b01101110) = 110,
+    B1101111  DEPRECATED(0b1101111 ) = 111,
+    B01101111 DEPRECATED(0b01101111) = 111,
+    B1110000  DEPRECATED(0b1110000 ) = 112,
+    B01110000 DEPRECATED(0b01110000) = 112,
+    B1110001  DEPRECATED(0b1110001 ) = 113,
+    B01110001 DEPRECATED(0b01110001) = 113,
+    B1110010  DEPRECATED(0b1110010 ) = 114,
+    B01110010 DEPRECATED(0b01110010) = 114,
+    B1110011  DEPRECATED(0b1110011 ) = 115,
+    B01110011 DEPRECATED(0b01110011) = 115,
+    B1110100  DEPRECATED(0b1110100 ) = 116,
+    B01110100 DEPRECATED(0b01110100) = 116,
+    B1110101  DEPRECATED(0b1110101 ) = 117,
+    B01110101 DEPRECATED(0b01110101) = 117,
+    B1110110  DEPRECATED(0b1110110 ) = 118,
+    B01110110 DEPRECATED(0b01110110) = 118,
+    B1110111  DEPRECATED(0b1110111 ) = 119,
+    B01110111 DEPRECATED(0b01110111) = 119,
+    B1111000  DEPRECATED(0b1111000 ) = 120,
+    B01111000 DEPRECATED(0b01111000) = 120,
+    B1111001  DEPRECATED(0b1111001 ) = 121,
+    B01111001 DEPRECATED(0b01111001) = 121,
+    B1111010  DEPRECATED(0b1111010 ) = 122,
+    B01111010 DEPRECATED(0b01111010) = 122,
+    B1111011  DEPRECATED(0b1111011 ) = 123,
+    B01111011 DEPRECATED(0b01111011) = 123,
+    B1111100  DEPRECATED(0b1111100 ) = 124,
+    B01111100 DEPRECATED(0b01111100) = 124,
+    B1111101  DEPRECATED(0b1111101 ) = 125,
+    B01111101 DEPRECATED(0b01111101) = 125,
+    B1111110  DEPRECATED(0b1111110 ) = 126,
+    B01111110 DEPRECATED(0b01111110) = 126,
+    B1111111  DEPRECATED(0b1111111 ) = 127,
+    B01111111 DEPRECATED(0b01111111) = 127,
+    B10000000 DEPRECATED(0b10000000) = 128,
+    B10000001 DEPRECATED(0b10000001) = 129,
+    B10000010 DEPRECATED(0b10000010) = 130,
+    B10000011 DEPRECATED(0b10000011) = 131,
+    B10000100 DEPRECATED(0b10000100) = 132,
+    B10000101 DEPRECATED(0b10000101) = 133,
+    B10000110 DEPRECATED(0b10000110) = 134,
+    B10000111 DEPRECATED(0b10000111) = 135,
+    B10001000 DEPRECATED(0b10001000) = 136,
+    B10001001 DEPRECATED(0b10001001) = 137,
+    B10001010 DEPRECATED(0b10001010) = 138,
+    B10001011 DEPRECATED(0b10001011) = 139,
+    B10001100 DEPRECATED(0b10001100) = 140,
+    B10001101 DEPRECATED(0b10001101) = 141,
+    B10001110 DEPRECATED(0b10001110) = 142,
+    B10001111 DEPRECATED(0b10001111) = 143,
+    B10010000 DEPRECATED(0b10010000) = 144,
+    B10010001 DEPRECATED(0b10010001) = 145,
+    B10010010 DEPRECATED(0b10010010) = 146,
+    B10010011 DEPRECATED(0b10010011) = 147,
+    B10010100 DEPRECATED(0b10010100) = 148,
+    B10010101 DEPRECATED(0b10010101) = 149,
+    B10010110 DEPRECATED(0b10010110) = 150,
+    B10010111 DEPRECATED(0b10010111) = 151,
+    B10011000 DEPRECATED(0b10011000) = 152,
+    B10011001 DEPRECATED(0b10011001) = 153,
+    B10011010 DEPRECATED(0b10011010) = 154,
+    B10011011 DEPRECATED(0b10011011) = 155,
+    B10011100 DEPRECATED(0b10011100) = 156,
+    B10011101 DEPRECATED(0b10011101) = 157,
+    B10011110 DEPRECATED(0b10011110) = 158,
+    B10011111 DEPRECATED(0b10011111) = 159,
+    B10100000 DEPRECATED(0b10100000) = 160,
+    B10100001 DEPRECATED(0b10100001) = 161,
+    B10100010 DEPRECATED(0b10100010) = 162,
+    B10100011 DEPRECATED(0b10100011) = 163,
+    B10100100 DEPRECATED(0b10100100) = 164,
+    B10100101 DEPRECATED(0b10100101) = 165,
+    B10100110 DEPRECATED(0b10100110) = 166,
+    B10100111 DEPRECATED(0b10100111) = 167,
+    B10101000 DEPRECATED(0b10101000) = 168,
+    B10101001 DEPRECATED(0b10101001) = 169,
+    B10101010 DEPRECATED(0b10101010) = 170,
+    B10101011 DEPRECATED(0b10101011) = 171,
+    B10101100 DEPRECATED(0b10101100) = 172,
+    B10101101 DEPRECATED(0b10101101) = 173,
+    B10101110 DEPRECATED(0b10101110) = 174,
+    B10101111 DEPRECATED(0b10101111) = 175,
+    B10110000 DEPRECATED(0b10110000) = 176,
+    B10110001 DEPRECATED(0b10110001) = 177,
+    B10110010 DEPRECATED(0b10110010) = 178,
+    B10110011 DEPRECATED(0b10110011) = 179,
+    B10110100 DEPRECATED(0b10110100) = 180,
+    B10110101 DEPRECATED(0b10110101) = 181,
+    B10110110 DEPRECATED(0b10110110) = 182,
+    B10110111 DEPRECATED(0b10110111) = 183,
+    B10111000 DEPRECATED(0b10111000) = 184,
+    B10111001 DEPRECATED(0b10111001) = 185,
+    B10111010 DEPRECATED(0b10111010) = 186,
+    B10111011 DEPRECATED(0b10111011) = 187,
+    B10111100 DEPRECATED(0b10111100) = 188,
+    B10111101 DEPRECATED(0b10111101) = 189,
+    B10111110 DEPRECATED(0b10111110) = 190,
+    B10111111 DEPRECATED(0b10111111) = 191,
+    B11000000 DEPRECATED(0b11000000) = 192,
+    B11000001 DEPRECATED(0b11000001) = 193,
+    B11000010 DEPRECATED(0b11000010) = 194,
+    B11000011 DEPRECATED(0b11000011) = 195,
+    B11000100 DEPRECATED(0b11000100) = 196,
+    B11000101 DEPRECATED(0b11000101) = 197,
+    B11000110 DEPRECATED(0b11000110) = 198,
+    B11000111 DEPRECATED(0b11000111) = 199,
+    B11001000 DEPRECATED(0b11001000) = 200,
+    B11001001 DEPRECATED(0b11001001) = 201,
+    B11001010 DEPRECATED(0b11001010) = 202,
+    B11001011 DEPRECATED(0b11001011) = 203,
+    B11001100 DEPRECATED(0b11001100) = 204,
+    B11001101 DEPRECATED(0b11001101) = 205,
+    B11001110 DEPRECATED(0b11001110) = 206,
+    B11001111 DEPRECATED(0b11001111) = 207,
+    B11010000 DEPRECATED(0b11010000) = 208,
+    B11010001 DEPRECATED(0b11010001) = 209,
+    B11010010 DEPRECATED(0b11010010) = 210,
+    B11010011 DEPRECATED(0b11010011) = 211,
+    B11010100 DEPRECATED(0b11010100) = 212,
+    B11010101 DEPRECATED(0b11010101) = 213,
+    B11010110 DEPRECATED(0b11010110) = 214,
+    B11010111 DEPRECATED(0b11010111) = 215,
+    B11011000 DEPRECATED(0b11011000) = 216,
+    B11011001 DEPRECATED(0b11011001) = 217,
+    B11011010 DEPRECATED(0b11011010) = 218,
+    B11011011 DEPRECATED(0b11011011) = 219,
+    B11011100 DEPRECATED(0b11011100) = 220,
+    B11011101 DEPRECATED(0b11011101) = 221,
+    B11011110 DEPRECATED(0b11011110) = 222,
+    B11011111 DEPRECATED(0b11011111) = 223,
+    B11100000 DEPRECATED(0b11100000) = 224,
+    B11100001 DEPRECATED(0b11100001) = 225,
+    B11100010 DEPRECATED(0b11100010) = 226,
+    B11100011 DEPRECATED(0b11100011) = 227,
+    B11100100 DEPRECATED(0b11100100) = 228,
+    B11100101 DEPRECATED(0b11100101) = 229,
+    B11100110 DEPRECATED(0b11100110) = 230,
+    B11100111 DEPRECATED(0b11100111) = 231,
+    B11101000 DEPRECATED(0b11101000) = 232,
+    B11101001 DEPRECATED(0b11101001) = 233,
+    B11101010 DEPRECATED(0b11101010) = 234,
+    B11101011 DEPRECATED(0b11101011) = 235,
+    B11101100 DEPRECATED(0b11101100) = 236,
+    B11101101 DEPRECATED(0b11101101) = 237,
+    B11101110 DEPRECATED(0b11101110) = 238,
+    B11101111 DEPRECATED(0b11101111) = 239,
+    B11110000 DEPRECATED(0b11110000) = 240,
+    B11110001 DEPRECATED(0b11110001) = 241,
+    B11110010 DEPRECATED(0b11110010) = 242,
+    B11110011 DEPRECATED(0b11110011) = 243,
+    B11110100 DEPRECATED(0b11110100) = 244,
+    B11110101 DEPRECATED(0b11110101) = 245,
+    B11110110 DEPRECATED(0b11110110) = 246,
+    B11110111 DEPRECATED(0b11110111) = 247,
+    B11111000 DEPRECATED(0b11111000) = 248,
+    B11111001 DEPRECATED(0b11111001) = 249,
+    B11111010 DEPRECATED(0b11111010) = 250,
+    B11111011 DEPRECATED(0b11111011) = 251,
+    B11111100 DEPRECATED(0b11111100) = 252,
+    B11111101 DEPRECATED(0b11111101) = 253,
+    B11111110 DEPRECATED(0b11111110) = 254,
+    B11111111 DEPRECATED(0b11111111) = 255
+};
+
+#undef DEPRECATED
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Client.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Client.h
new file mode 100644
index 000000000..188184927
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Client.h
@@ -0,0 +1,45 @@
+/*
+    Client.h - Base class that provides Client
+    Copyright (c) 2011 Adrian McEwen.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "Stream.h"
+#include "IPAddress.h"
+
+class Client : public Stream {
+
+public:
+    virtual int connect(IPAddress ip, uint16_t port) = 0;
+    virtual int connect(const char *host, uint16_t port) = 0;
+    virtual size_t write(uint8_t) = 0;
+    virtual size_t write(const uint8_t *buf, size_t size) = 0;
+    virtual int available() = 0;
+    virtual int read() = 0;
+    virtual int read(uint8_t *buf, size_t size) = 0;
+    virtual int peek() = 0;
+    virtual void flush() = 0;
+    virtual void stop() = 0;
+    virtual uint8_t connected() = 0;
+    virtual operator bool() = 0;
+protected:
+    uint8_t *rawIPAddress(IPAddress &addr) {
+        return addr.raw_address();
+    };
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Common.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Common.cpp
new file mode 100644
index 000000000..9d2217421
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Common.cpp
@@ -0,0 +1,31 @@
+/*
+    Copyright (c) 2019 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "Common.h"
+
+/* C++ prototypes */
+long map(long x, long in_min, long in_max, long out_min, long out_max) {
+    return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;
+}
+
+uint16_t makeWord(uint16_t w) {
+    return w;
+}
+uint16_t makeWord(uint8_t h, uint8_t l) {
+    return (h << 8) | l;
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Common.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Common.h
new file mode 100644
index 000000000..a9fb15281
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Common.h
@@ -0,0 +1,227 @@
+/*
+    Copyright (c) 2019 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void yield(void);
+
+typedef enum {
+    LOW = 0,
+    HIGH = 1,
+    CHANGE = 2,
+    FALLING = 3,
+    RISING = 4,
+} PinStatus;
+
+typedef enum {
+    INPUT = 0x0,
+    OUTPUT = 0x1,
+    INPUT_PULLUP = 0x2,
+} PinMode;
+
+typedef enum {
+    PWM,
+    CURRENT
+} AnalogOutMode;
+
+typedef enum {
+    ADC_RAW,
+    MILLIVOLTS
+} AnalogInputUnits;
+
+typedef enum {
+    DAC_RAW,
+    MICROAMPS
+} AnalogOutputUnits;
+
+typedef enum {
+    LSBFIRST = 0,
+    MSBFIRST = 1,
+} BitOrder;
+
+#define PI         3.1415926535897932384626433832795
+#define HALF_PI    1.5707963267948966192313216916398
+#define TWO_PI     6.283185307179586476925286766559
+#define DEG_TO_RAD 0.017453292519943295769236907684886
+#define RAD_TO_DEG 57.295779513082320876798154814105
+#define EULER      2.718281828459045235360287471352
+
+#define SERIAL     0x0
+#define DISPLAY    0x1
+
+typedef void (*voidFuncPtr)(void);
+typedef void (*voidFuncPtrParam)(void *);
+
+// interrupts() / noInterrupts() must be defined by the core
+
+#define lowByte(w) ((uint8_t)((w)&0xff))
+#define highByte(w) ((uint8_t)((w) >> 8))
+
+#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
+#define bitSet(value, bit) ((value) |= (1UL << (bit)))
+#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
+#define bitWrite(value, bit, bitvalue) \
+    (bitvalue ? bitSet(value, bit) : bitClear(value, bit))
+
+#ifndef bit
+#define bit(b) (1UL << (b))
+#endif
+
+typedef bool     boolean;
+typedef uint8_t  byte;
+typedef uint16_t word;
+typedef uint16_t _iq15_s;
+
+void init(void);
+void initVariant(void);
+
+int atexit(void (*func)()) __attribute__((weak));
+int main() __attribute__((weak));
+
+#ifdef EXTENDED_PIN_MODE
+// Platforms who want to declare more than 256 pins need to define
+// EXTENDED_PIN_MODE globally
+typedef uint32_t pin_size_t;
+#else
+typedef uint8_t pin_size_t;
+#endif
+
+// Define sketch exposed functions
+// New API definitions for these functions break Arduino's included examples.
+// Created "overloaded" versions to facilitate this
+
+// Digital I/O
+PinStatus digitalRead(pin_size_t pinNumber);
+void digitalWrite(pin_size_t ulPin, uint32_t ulVal);
+void pinMode(pin_size_t ulPin, uint32_t ulMode);
+
+PinStatus digitalReadClearCore(pin_size_t pinNumber);
+void digitalWriteClearCore(pin_size_t pinNumber, PinStatus status);
+void pinModeAPI(pin_size_t pinNumber, PinMode ulMode);
+
+// Analog I/O
+int analogReadAPI(pin_size_t pinNumber, AnalogInputUnits units);
+void analogWriteAPI(pin_size_t pinNumber, int value, AnalogOutMode mode,
+                    AnalogOutputUnits units);
+
+// Zero, Due & MKR Family
+void analogReadResolution(int res);
+
+// Advanced I/O
+void noTone(uint8_t _pin);
+unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout);
+unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout);
+pin_size_t shiftIn(pin_size_t dataPin, pin_size_t clockPin, BitOrder bitOrder);
+void shiftOut(pin_size_t dataPin, pin_size_t clockPin, BitOrder bitOrder,
+              uint8_t val);
+void tone(uint8_t _pin, unsigned int frequency, unsigned long duration);
+void toneVolume(unsigned char outputPin, float volume);
+void OutputPulsesStop(pin_size_t pin);
+
+// Time
+void delay(unsigned long);
+void delayMicroseconds(unsigned int usec);
+unsigned long micros(void);
+unsigned long millis(void);
+
+// Math
+#ifndef constrain
+#define constrain(amt, low, high) \
+    ((amt) < (low) ? (low) : ((amt) > (high) ? (high) : (amt)))
+#endif
+
+#ifndef min
+#define min(a, b) \
+    ({ __typeof__ (a) _a = (a); \
+       __typeof__ (b) _b = (b); \
+     _a < _b ? _a : _b; })
+#endif
+
+#ifndef max
+#define max(a, b) \
+    ({ __typeof__ (a) _a = (a); \
+       __typeof__ (b) _b = (b); \
+     _a > _b ? _a : _b; })
+#endif
+
+#ifndef sq
+#define sq(x) ((x) * (x))
+#endif
+
+// Trigonometry
+#ifndef radians
+#define radians(deg) ((deg) * DEG_TO_RAD)
+#endif
+
+#ifndef degrees
+#define degrees(rad) ((rad) * RAD_TO_DEG)
+#endif
+
+// External Interrupts
+void attachInterrupt(pin_size_t interruptNumber, voidFuncPtr callback,
+                     PinStatus mode);
+void attachInterruptParam(pin_size_t interruptNumber, voidFuncPtrParam callback,
+                          PinStatus mode, void *param);
+void detachInterrupt(pin_size_t interruptNumber);
+
+// Interrupts
+void interrupts();
+void noInterrupts();
+
+// Test Sketch
+void setup(void);
+void loop(void);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#ifdef __cplusplus
+
+/* C++ prototypes */
+int analogRead(pin_size_t pinNumber, AnalogInputUnits units = ADC_RAW);
+void analogWrite(pin_size_t pinNumber, uint32_t value,
+                 AnalogOutMode mode = PWM, AnalogOutputUnits units = DAC_RAW);
+
+uint16_t makeWord(uint16_t w);
+uint16_t makeWord(byte h, byte l);
+
+#define word(...) makeWord(__VA_ARGS__)
+
+unsigned long pulseIn(uint8_t pin, uint8_t state,
+                      unsigned long timeout = 1000000L); // timeout in microsec
+unsigned long pulseInLong(uint8_t pin, uint8_t state,
+                          unsigned long timeout = 1000000L);
+
+void OutputPulsesStart(pin_size_t pin, uint32_t onTime, uint32_t offTime,
+                       uint16_t pulseCnt = 0, bool blockUntilDone = false);
+void OutputPulsesStop(pin_size_t pin, bool stopImmediately);
+
+void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0);
+// WMath prototypes
+long random(long);
+long random(long, long);
+void randomSeed(unsigned long);
+long map(long, long, long, long, long);
+
+#endif // __cplusplus
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/HardwareI2C.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/HardwareI2C.h
new file mode 100644
index 000000000..c74a8162c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/HardwareI2C.h
@@ -0,0 +1,42 @@
+/*
+    Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include <inttypes.h>
+#include "Stream.h"
+
+class HardwareI2C : public Stream {
+public:
+    virtual void begin() = 0;
+    virtual void begin(uint8_t address) = 0;
+    virtual void end() = 0;
+
+    virtual void setClock(uint32_t freq) = 0;
+
+    virtual void beginTransmission(uint8_t address) = 0;
+    virtual uint8_t endTransmission(bool stopBit) = 0;
+    virtual uint8_t endTransmission(void) = 0;
+
+    virtual uint8_t requestFrom(uint8_t address, size_t len, bool stopBit) = 0;
+    virtual uint8_t requestFrom(uint8_t address, size_t len) = 0;
+
+    virtual void onReceive(void(*)(int)) = 0;
+    virtual void onRequest(void(*)(void)) = 0;
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/HardwareSerial.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/HardwareSerial.h
new file mode 100644
index 000000000..0bc644d54
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/HardwareSerial.h
@@ -0,0 +1,102 @@
+/*
+    Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "Stream.h"
+
+// XXX: Those constants should be defined as const int / enums?
+// XXX: shall we use namespaces too?
+#define SERIAL_PARITY_EVEN   (0x1ul)
+#define SERIAL_PARITY_ODD    (0x2ul)
+#define SERIAL_PARITY_NONE   (0x3ul)
+#define SERIAL_PARITY_MARK   (0x4ul)
+#define SERIAL_PARITY_SPACE  (0x5ul)
+#define SERIAL_PARITY_MASK   (0xFul)
+
+#define SERIAL_STOP_BIT_1    (0x10ul)
+#define SERIAL_STOP_BIT_1_5  (0x20ul)
+#define SERIAL_STOP_BIT_2    (0x30ul)
+#define SERIAL_STOP_BIT_MASK (0xF0ul)
+
+#define SERIAL_DATA_5        (0x100ul)
+#define SERIAL_DATA_6        (0x200ul)
+#define SERIAL_DATA_7        (0x300ul)
+#define SERIAL_DATA_8        (0x400ul)
+#define SERIAL_DATA_MASK     (0xF00ul)
+
+#define SERIAL_5N1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_NONE  | SERIAL_DATA_5)
+#define SERIAL_6N1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_NONE  | SERIAL_DATA_6)
+#define SERIAL_7N1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_NONE  | SERIAL_DATA_7)
+#define SERIAL_8N1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_NONE  | SERIAL_DATA_8)
+#define SERIAL_5N2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_NONE  | SERIAL_DATA_5)
+#define SERIAL_6N2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_NONE  | SERIAL_DATA_6)
+#define SERIAL_7N2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_NONE  | SERIAL_DATA_7)
+#define SERIAL_8N2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_NONE  | SERIAL_DATA_8)
+#define SERIAL_5E1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_EVEN  | SERIAL_DATA_5)
+#define SERIAL_6E1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_EVEN  | SERIAL_DATA_6)
+#define SERIAL_7E1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_EVEN  | SERIAL_DATA_7)
+#define SERIAL_8E1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_EVEN  | SERIAL_DATA_8)
+#define SERIAL_5E2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_EVEN  | SERIAL_DATA_5)
+#define SERIAL_6E2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_EVEN  | SERIAL_DATA_6)
+#define SERIAL_7E2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_EVEN  | SERIAL_DATA_7)
+#define SERIAL_8E2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_EVEN  | SERIAL_DATA_8)
+#define SERIAL_5O1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_ODD   | SERIAL_DATA_5)
+#define SERIAL_6O1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_ODD   | SERIAL_DATA_6)
+#define SERIAL_7O1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_ODD   | SERIAL_DATA_7)
+#define SERIAL_8O1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_ODD   | SERIAL_DATA_8)
+#define SERIAL_5O2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_ODD   | SERIAL_DATA_5)
+#define SERIAL_6O2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_ODD   | SERIAL_DATA_6)
+#define SERIAL_7O2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_ODD   | SERIAL_DATA_7)
+#define SERIAL_8O2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_ODD   | SERIAL_DATA_8)
+#define SERIAL_5M1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_MARK  | SERIAL_DATA_5)
+#define SERIAL_6M1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_MARK  | SERIAL_DATA_6)
+#define SERIAL_7M1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_MARK  | SERIAL_DATA_7)
+#define SERIAL_8M1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_MARK  | SERIAL_DATA_8)
+#define SERIAL_5M2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_MARK  | SERIAL_DATA_5)
+#define SERIAL_6M2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_MARK  | SERIAL_DATA_6)
+#define SERIAL_7M2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_MARK  | SERIAL_DATA_7)
+#define SERIAL_8M2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_MARK  | SERIAL_DATA_8)
+#define SERIAL_5S1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_SPACE | SERIAL_DATA_5)
+#define SERIAL_6S1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_SPACE | SERIAL_DATA_6)
+#define SERIAL_7S1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_SPACE | SERIAL_DATA_7)
+#define SERIAL_8S1     (SERIAL_STOP_BIT_1 | SERIAL_PARITY_SPACE | SERIAL_DATA_8)
+#define SERIAL_5S2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_SPACE | SERIAL_DATA_5)
+#define SERIAL_6S2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_SPACE | SERIAL_DATA_6)
+#define SERIAL_7S2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_SPACE | SERIAL_DATA_7)
+#define SERIAL_8S2     (SERIAL_STOP_BIT_2 | SERIAL_PARITY_SPACE | SERIAL_DATA_8)
+
+class HardwareSerial : public Stream {
+public:
+    virtual void begin(unsigned long) = 0;
+    virtual void begin(unsigned long baudrate, uint16_t config) = 0;
+    virtual void end() = 0;
+    virtual int available(void) = 0;
+    virtual int peek(void) = 0;
+    virtual int read(void) = 0;
+    virtual void flush(void) = 0;
+    virtual size_t write(uint8_t) = 0;
+    using Print::write; // pull in write(str) and write(buf, size) from Print
+    virtual operator bool() = 0;
+};
+
+extern void serialEventRun(void)  __attribute__((weak));
+extern void serialEvent(void)  __attribute__((weak));
+extern void serialEvent0(void) __attribute__((weak));
+extern void serialEvent1(void) __attribute__((weak));
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/IPAddress.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/IPAddress.cpp
new file mode 100644
index 000000000..cf170520f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/IPAddress.cpp
@@ -0,0 +1,103 @@
+/*
+    IPAddress.cpp - Base class that provides IPAddress
+    Copyright (c) 2011 Adrian McEwen.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "IPAddress.h"
+#include "Print.h"
+
+IPAddress::IPAddress() {
+    _address.dword = 0;
+}
+
+IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet,
+                     uint8_t third_octet, uint8_t fourth_octet) {
+    _address.bytes[0] = first_octet;
+    _address.bytes[1] = second_octet;
+    _address.bytes[2] = third_octet;
+    _address.bytes[3] = fourth_octet;
+}
+
+IPAddress::IPAddress(uint32_t address) {
+    _address.dword = address;
+}
+
+IPAddress::IPAddress(const uint8_t *address) {
+    memcpy(_address.bytes, address, sizeof(_address.bytes));
+}
+
+bool IPAddress::fromString(const char *address) {
+
+    uint16_t acc = 0; // Accumulator
+    uint8_t dots = 0;
+
+    while (*address) {
+        char c = *address++;
+        if (c >= '0' && c <= '9') {
+            acc = acc * 10 + (c - '0');
+            if (acc > 255) {
+                // Value out of [0..255] range
+                return false;
+            }
+        }
+        else if (c == '.') {
+            if (dots == 3) {
+                // Too much dots (there must be 3 dots)
+                return false;
+            }
+            _address.bytes[dots++] = acc;
+            acc = 0;
+        }
+        else {
+            // Invalid char
+            return false;
+        }
+    }
+
+    if (dots != 3) {
+        // Too few dots (there must be 3 dots)
+        return false;
+    }
+    _address.bytes[3] = acc;
+    return true;
+}
+
+IPAddress &IPAddress::operator=(const uint8_t *address) {
+    memcpy(_address.bytes, address, sizeof(_address.bytes));
+    return *this;
+}
+
+IPAddress &IPAddress::operator=(uint32_t address) {
+    _address.dword = address;
+    return *this;
+}
+
+bool IPAddress::operator==(const uint8_t *addr) const {
+    return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0;
+}
+
+size_t IPAddress::printTo(Print &p) const {
+    size_t n = 0;
+    for (int i = 0; i < 3; i++) {
+        n += p.print(_address.bytes[i], DEC);
+        n += p.print('.');
+    }
+    n += p.print(_address.bytes[3], DEC);
+    return n;
+}
+
+const IPAddress INADDR_NONE(0, 0, 0, 0);
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/IPAddress.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/IPAddress.h
new file mode 100644
index 000000000..860f384aa
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/IPAddress.h
@@ -0,0 +1,93 @@
+/*
+    IPAddress.h - Base class that provides IPAddress
+    Copyright (c) 2011 Adrian McEwen.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include <stdint.h>
+#include "Printable.h"
+#include "ArduinoString.h"
+
+// A class to make it easier to handle and pass around IP addresses
+
+class IPAddress : public Printable {
+private:
+    union {
+        uint8_t bytes[4];  // IPv4 address
+        uint32_t dword;
+    } _address;
+
+    // Access the raw byte array containing the address.  Because this returns a
+    // pointer to the internal structure rather than a copy of the address this
+    // function should only be used when you know that the usage of the returned
+    // uint8_t* will be transient and not stored.
+    uint8_t *raw_address() {
+        return _address.bytes;
+    };
+
+public:
+    // Constructors
+    IPAddress();
+    IPAddress(uint8_t first_octet, uint8_t second_octet,
+              uint8_t third_octet, uint8_t fourth_octet);
+    IPAddress(uint32_t address);
+    IPAddress(const uint8_t *address);
+
+    bool fromString(const char *address);
+    bool fromString(const String &address) {
+        return fromString(address.c_str());
+    }
+
+    // Overloaded cast operator to allow IPAddress objects to be used where a
+    // pointer to a four-byte uint8_t array is expected
+    operator uint32_t() const {
+        return _address.dword;
+    };
+    bool operator==(const IPAddress &addr) const {
+        return _address.dword == addr._address.dword;
+    };
+    bool operator!=(const IPAddress &addr) const {
+        return _address.dword != addr._address.dword;
+    };
+    bool operator==(const uint8_t *addr) const;
+
+    // Overloaded index operator to allow getting and setting individual octets
+    // of the address
+    uint8_t operator[](int index) const {
+        return _address.bytes[index];
+    };
+    uint8_t &operator[](int index) {
+        return _address.bytes[index];
+    };
+
+    // Overloaded copy operators to allow initialisation of IPAddress objects
+    // from other types
+    IPAddress &operator=(const uint8_t *address);
+    IPAddress &operator=(uint32_t address);
+
+    virtual size_t printTo(Print &p) const;
+
+    friend class EthernetClass;
+    friend class UDP;
+    friend class Client;
+    friend class Server;
+    friend class DhcpClass;
+    friend class DNSClient;
+};
+
+extern const IPAddress INADDR_NONE;
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Interrupts.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Interrupts.h
new file mode 100644
index 000000000..c81ab9480
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Interrupts.h
@@ -0,0 +1,59 @@
+/*
+    Copyright (c) 2019 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef W_INTERRUPTS_CPP
+#define W_INTERRUPTS_CPP
+#ifdef __cplusplus
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "Common.h"
+
+template <typename T>
+using voidTemplateFuncPtrParam =  void (*)(T param);
+
+template<typename T> struct __container__ {
+    void *param;
+    voidTemplateFuncPtrParam<T> function;
+};
+
+// C++ only overloaded version of attachInterrupt function
+template<typename T> void attachInterrupt(pin_size_t interruptNum,
+        voidTemplateFuncPtrParam<T> userFunc, PinStatus mode, T &param) {
+
+    struct __container__<T> *cont = new __container__<T>();
+    cont->param = &param;
+    cont->function = userFunc;
+
+    auto f = [](void *a) -> void {
+        T param = *(T *)((struct __container__<T> *)a)->param;
+        (((struct __container__<T> *)a)->function)(param);
+    };
+
+    attachInterruptParam(interruptNum, f, mode, cont);
+}
+
+template<typename T> void attachInterrupt(pin_size_t interruptNum,
+        voidTemplateFuncPtrParam<T *> userFunc, PinStatus mode, T *param) {
+    attachInterruptParam(interruptNum, (voidFuncPtrParam)userFunc, mode,
+                         (void *)param);
+}
+
+#endif
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Print.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Print.cpp
new file mode 100644
index 000000000..9082cc1df
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Print.cpp
@@ -0,0 +1,375 @@
+/*
+    Copyright (c) 2014 Arduino.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <math.h>
+
+#include "Print.h"
+
+// Public Methods //////////////////////////////////////////////////////////////
+
+/* default implementation: may be overridden */
+size_t Print::write(const uint8_t *buffer, size_t size) {
+    size_t n = 0;
+    while (size--) {
+        if (write(*buffer++)) {
+            n++;
+        }
+        else {
+            break;
+        }
+    }
+    return n;
+}
+
+size_t Print::print(const __FlashStringHelper *ifsh) {
+#if defined(__AVR__)
+    PGM_P p = reinterpret_cast<PGM_P>(ifsh);
+    size_t n = 0;
+    while (1) {
+        unsigned char c = pgm_read_byte(p++);
+        if (c == 0) {
+            break;
+        }
+        if (write(c)) {
+            n++;
+        }
+        else {
+            break;
+        }
+    }
+    return n;
+#else
+    return print(reinterpret_cast<const char *>(ifsh));
+#endif
+}
+
+size_t Print::print(const String &s) {
+    return write(s.c_str(), s.length());
+}
+
+size_t Print::print(const char str[]) {
+    return write(str);
+}
+
+size_t Print::print(char c) {
+    return write(c);
+}
+
+size_t Print::print(unsigned char b, int base) {
+    return print((unsigned long) b, base);
+}
+
+size_t Print::print(int n, int base) {
+    return print((long) n, base);
+}
+
+size_t Print::print(unsigned int n, int base) {
+    return print((unsigned long) n, base);
+}
+
+size_t Print::print(long n, int base) {
+    if (base == 0) {
+        return write(n);
+    }
+    else if (base == 10) {
+        if (n < 0) {
+            int t = print('-');
+            n = -n;
+            return printNumber(n, 10) + t;
+        }
+        return printNumber(n, 10);
+    }
+    else {
+        return printNumber(n, base);
+    }
+}
+
+size_t Print::print(unsigned long n, int base) {
+    if (base == 0) {
+        return write(n);
+    }
+    else {
+        return printNumber(n, base);
+    }
+}
+
+size_t Print::print(long long n, int base) {
+    if (base == 0) {
+        return write(n);
+    }
+    else if (base == 10) {
+        if (n < 0) {
+            int t = print('-');
+            n = -n;
+            return printULLNumber(n, 10) + t;
+        }
+        return printULLNumber(n, 10);
+    }
+    else {
+        return printULLNumber(n, base);
+    }
+}
+
+size_t Print::print(unsigned long long n, int base) {
+    if (base == 0) {
+        return write(n);
+    }
+    else {
+        return printULLNumber(n, base);
+    }
+}
+
+size_t Print::print(double n, int digits) {
+    return printFloat(n, digits);
+}
+
+size_t Print::println(const __FlashStringHelper *ifsh) {
+    size_t n = print(ifsh);
+    n += println();
+    return n;
+}
+
+size_t Print::print(const Printable &x) {
+    return x.printTo(*this);
+}
+
+size_t Print::println(void) {
+    return write("\r\n");
+}
+
+size_t Print::println(const String &s) {
+    size_t n = print(s);
+    n += println();
+    return n;
+}
+
+size_t Print::println(const char c[]) {
+    size_t n = print(c);
+    n += println();
+    return n;
+}
+
+size_t Print::println(char c) {
+    size_t n = print(c);
+    n += println();
+    return n;
+}
+
+size_t Print::println(unsigned char b, int base) {
+    size_t n = print(b, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(int num, int base) {
+    size_t n = print(num, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(unsigned int num, int base) {
+    size_t n = print(num, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(long num, int base) {
+    size_t n = print(num, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(unsigned long num, int base) {
+    size_t n = print(num, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(long long num, int base) {
+    size_t n = print(num, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(unsigned long long num, int base) {
+    size_t n = print(num, base);
+    n += println();
+    return n;
+}
+
+size_t Print::println(double num, int digits) {
+    size_t n = print(num, digits);
+    n += println();
+    return n;
+}
+
+size_t Print::println(const Printable &x) {
+    size_t n = print(x);
+    n += println();
+    return n;
+}
+
+// Private Methods /////////////////////////////////////////////////////////////
+
+size_t Print::printNumber(unsigned long n, uint8_t base) {
+    char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte.
+    char *str = &buf[sizeof(buf) - 1];
+
+    *str = '\0';
+
+    // prevent crash if called with base == 1
+    if (base < 2) {
+        base = 10;
+    }
+
+    do {
+        char c = n % base;
+        n /= base;
+
+        *--str = c < 10 ? c + '0' : c + 'A' - 10;
+    } while(n);
+
+    return write(str);
+}
+
+// REFERENCE IMPLEMENTATION FOR ULL
+// size_t Print::printULLNumber(unsigned long long n, uint8_t base)
+// {
+  // // if limited to base 10 and 16 the bufsize can be smaller
+  // char buf[65];
+  // char *str = &buf[64];
+
+  // *str = '\0';
+
+  // // prevent crash if called with base == 1
+  // if (base < 2) base = 10;
+
+    // do {
+      // unsigned long long t = n / base;
+      // char c = n - t * base;  // faster than c = n%base;
+      // n = t;
+      // *--str = c < 10 ? c + '0' : c + 'A' - 10;
+  // } while(n);
+
+  // return write(str);
+// }
+
+// FAST IMPLEMENTATION FOR ULL
+size_t Print::printULLNumber(unsigned long long n64, uint8_t base) {
+    // if limited to base 10 and 16 the bufsize can be 20
+    char buf[64];
+    uint8_t i = 0;
+    uint8_t innerLoops = 0;
+
+    // prevent crash if called with base == 1
+    if (base < 2) {
+        base = 10;
+    }
+
+    // process chunks that fit in "16 bit math".
+    uint16_t top = 0xFFFF / base;
+    uint16_t th16 = 1;
+    while (th16 < top) {
+        th16 *= base;
+        innerLoops++;
+    }
+
+    while (n64 > th16) {
+        // 64 bit math part
+        uint64_t q = n64 / th16;
+        uint16_t r = n64 - q * th16;
+        n64 = q;
+
+        // 16 bit math loop to do remainder. (note buffer is filled reverse)
+        for (uint8_t j = 0; j < innerLoops; j++) {
+            uint16_t qq = r / base;
+            buf[i++] = r - qq * base;
+            r = qq;
+        }
+    }
+
+    uint16_t n16 = n64;
+    while (n16 > 0) {
+        uint16_t qq = n16 / base;
+        buf[i++] = n16 - qq * base;
+        n16 = qq;
+    }
+
+    size_t bytes = i;
+    for (; i > 0; i--) {
+        write((char)(buf[i - 1] < 10 ?
+                     '0' + buf[i - 1] :
+                     'A' + buf[i - 1] - 10));
+    }
+
+    return bytes;
+}
+
+size_t Print::printFloat(double number, uint8_t digits) {
+    size_t n = 0;
+
+    if (isnan(number)) {
+        return print("nan");
+    }
+    if (isinf(number)) {
+        return print("inf");
+    }
+    if (number > 4294967040.0) {
+        return print("ovf");    // constant determined empirically
+    }
+    if (number < -4294967040.0) {
+        return print("ovf");    // constant determined empirically
+    }
+
+    // Handle negative numbers
+    if (number < 0.0) {
+        n += print('-');
+        number = -number;
+    }
+
+    // Round correctly so that print(1.999, 2) prints as "2.00"
+    double rounding = 0.5;
+    for (uint8_t i = 0; i < digits; ++i) {
+        rounding /= 10.0;
+    }
+
+    number += rounding;
+
+    // Extract the integer part of the number and print it
+    unsigned long int_part = (unsigned long)number;
+    double remainder = number - (double)int_part;
+    n += print(int_part);
+
+    // Print the decimal point, but only if there are digits beyond
+    if (digits > 0) {
+        n += print(".");
+    }
+
+    // Extract digits from the remainder one at a time
+    while (digits-- > 0) {
+        remainder *= 10.0;
+        unsigned int toPrint = (unsigned int)remainder;
+        n += print(toPrint);
+        remainder -= toPrint;
+    }
+
+    return n;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Print.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Print.h
new file mode 100644
index 000000000..215b99636
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Print.h
@@ -0,0 +1,93 @@
+/*
+    Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include <inttypes.h>
+#include <stdio.h> // for size_t
+
+#include "ArduinoString.h"
+#include "Printable.h"
+
+#define DEC 10
+#define HEX 16
+#define OCT 8
+#define BIN 2
+
+class Print {
+private:
+    int write_error;
+    size_t printNumber(unsigned long, uint8_t);
+    size_t printULLNumber(unsigned long long, uint8_t);
+    size_t printFloat(double, uint8_t);
+protected:
+    void setWriteError(int err = 1) {
+        write_error = err;
+    }
+public:
+    Print() : write_error(0) {}
+
+    int getWriteError() {
+        return write_error;
+    }
+    void clearWriteError() {
+        setWriteError(0);
+    }
+
+    virtual size_t write(uint8_t) = 0;
+    size_t write(const char *str) {
+        if (str == NULL) {
+            return 0;
+        }
+        return write((const uint8_t *)str, strlen(str));
+    }
+    virtual size_t write(const uint8_t *buffer, size_t size);
+    size_t write(const char *buffer, size_t size) {
+        return write((const uint8_t *)buffer, size);
+    }
+
+    size_t print(const __FlashStringHelper *);
+    size_t print(const String &);
+    size_t print(const char[]);
+    size_t print(char);
+    size_t print(unsigned char, int = DEC);
+    size_t print(int, int = DEC);
+    size_t print(unsigned int, int = DEC);
+    size_t print(long, int = DEC);
+    size_t print(unsigned long, int = DEC);
+    size_t print(long long, int = DEC);
+    size_t print(unsigned long long, int = DEC);
+    size_t print(double, int = 2);
+    size_t print(const Printable &);
+
+    size_t println(const __FlashStringHelper *);
+    size_t println(const String &s);
+    size_t println(const char[]);
+    size_t println(char);
+    size_t println(unsigned char, int = DEC);
+    size_t println(int, int = DEC);
+    size_t println(unsigned int, int = DEC);
+    size_t println(long, int = DEC);
+    size_t println(unsigned long, int = DEC);
+    size_t println(long long, int = DEC);
+    size_t println(unsigned long long, int = DEC);
+    size_t println(double, int = 2);
+    size_t println(const Printable &);
+    size_t println(void);
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Printable.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Printable.h
new file mode 100644
index 000000000..5501f805f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Printable.h
@@ -0,0 +1,35 @@
+/*
+    Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include <stdlib.h>
+
+class Print;
+
+/** The Printable class provides a way for new classes to allow themselves to be
+    printed. By deriving from Printable and implementing the printTo method, it
+    will then be possible for users to print out instances of this class by
+    passing them into the usual Print::print and Print::println methods.
+*/
+
+class Printable {
+public:
+    virtual size_t printTo(Print &p) const = 0;
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/SPI.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/SPI.cpp
new file mode 100644
index 000000000..fa7a9d096
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/SPI.cpp
@@ -0,0 +1,177 @@
+/*
+ * SPI Master library for Teknic ClearCore.
+ * Copyright (c) 2015 Arduino LLC
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include "SPI.h"
+#include "ISerial.h"
+#include "SerialBase.h"
+#include "SerialDriver.h"
+#include "SdCardDriver.h"
+
+using ClearCore::Connector;
+using ClearCore::SerialBase;
+using ClearCore::SerialDriver;
+using ClearCore::ISerial;
+
+namespace ClearCore {
+extern SdCardDriver SdCard;
+extern SerialDriver ConnectorCOM0;
+extern SerialDriver ConnectorCOM1;
+}
+
+SPIClass::SPIClass(SerialBase &thePort, bool isCom)
+    : m_serial(&thePort),
+      m_isCom(isCom),
+      m_settings() {
+}
+
+void SPIClass::begin() {
+    if (m_isCom) {
+        ISerial *asISerial = dynamic_cast<ISerial *>(m_serial);
+        SerialDriver *serialDriver = static_cast<SerialDriver *>(asISerial);
+        serialDriver->Mode(Connector::ConnectorModes::SPI);
+    }
+    else {
+        m_serial->PortMode(SerialBase::PortModes::SPI);
+    }
+    m_serial->SpiSsMode(SerialBase::CtrlLineModes::LINE_OFF);
+    config();
+    m_serial->PortOpen();
+}
+
+void SPIClass::config() {
+    m_serial->Speed(m_settings.m_clockFreq);
+    switch (m_settings.m_dataMode) {
+        case SPI_MODE0:
+            m_serial->SpiClock(SerialBase::SpiClockPolarities::SCK_LOW,
+                               SerialBase::SpiClockPhases::LEAD_SAMPLE);
+            break;
+        case SPI_MODE1:
+            m_serial->SpiClock(SerialBase::SpiClockPolarities::SCK_LOW,
+                               SerialBase::SpiClockPhases::LEAD_CHANGE);
+            break;
+        case SPI_MODE2:
+            m_serial->SpiClock(SerialBase::SpiClockPolarities::SCK_HIGH,
+                               SerialBase::SpiClockPhases::LEAD_SAMPLE);
+            break;
+        case SPI_MODE3:
+            m_serial->SpiClock(SerialBase::SpiClockPolarities::SCK_HIGH,
+                               SerialBase::SpiClockPhases::LEAD_CHANGE);
+            break;
+        default:
+            break;
+    }
+}
+
+void SPIClass::end() {
+    m_serial->PortClose();
+}
+
+void SPIClass::usingInterrupt(int interruptNumber) {
+    (void)interruptNumber;
+}
+
+void SPIClass::notUsingInterrupt(int interruptNumber) {
+    (void)interruptNumber;
+}
+
+void SPIClass::beginTransaction(SPISettings settings) {
+    m_settings.m_bitOrder = settings.m_bitOrder;
+    m_settings.m_dataMode = settings.m_dataMode;
+    m_settings.m_clockFreq = settings.m_clockFreq;
+    config();
+    m_serial->SpiSsMode(SerialBase::CtrlLineModes::LINE_ON);
+}
+
+void SPIClass::endTransaction(void) {
+    m_serial->SpiSsMode(SerialBase::CtrlLineModes::LINE_OFF);
+}
+
+void SPIClass::setBitOrder(BitOrder order) {
+    m_settings.m_bitOrder = order;
+    config();
+}
+
+void SPIClass::setDataMode(uint8_t mode) {
+    m_settings.m_dataMode = mode;
+    config();
+}
+
+void SPIClass::setClockDivider(uint8_t div) {
+    m_settings.m_clockFreq = MAX_SPI / div;
+    config();
+}
+
+byte SPIClass::transfer(uint8_t data) {
+    return m_serial->SpiTransferData(data);
+}
+
+uint16_t SPIClass::transfer16(uint16_t data) {
+    union {
+        uint16_t val;
+        struct {
+            uint8_t lsb;
+            uint8_t msb;
+        };
+    } t;
+
+    t.val = data;
+
+    if (m_settings.m_bitOrder == LSBFIRST) {
+        t.lsb = transfer(t.lsb);
+        t.msb = transfer(t.msb);
+    }
+    else {
+        t.msb = transfer(t.msb);
+        t.lsb = transfer(t.lsb);
+    }
+
+    return t.val;
+}
+
+void SPIClass::transfer(void *buf, size_t count) {
+    m_serial->SpiTransferData((uint8_t *)buf, (uint8_t *)buf, count);
+}
+
+void SPIClass::transfer(const void *txbuf, void *rxbuf, size_t count,
+                        bool block) {
+    if (!block &&
+            m_serial->SpiTransferDataAsync((uint8_t *)txbuf, (uint8_t *)rxbuf, count)) {
+        return;
+    }
+    m_serial->SpiTransferData((uint8_t *)txbuf, (uint8_t *)rxbuf, count);
+}
+
+// Waits for a prior in-background DMA transfer to complete.
+void SPIClass::waitForTransfer(void) {
+    m_serial->SpiAsyncWaitComplete();
+}
+
+void SPIClass::attachInterrupt() {
+    // Should be enableInterrupt()
+}
+
+void SPIClass::detachInterrupt() {
+    // Should be disableInterrupt()
+}
+
+
+SPIClass SPI(ClearCore::ConnectorCOM0, true);
+SPIClass SPI1(ClearCore::ConnectorCOM1, true);
+SPIClass SPI2(ClearCore::SdCard, false);
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/SPI.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/SPI.h
new file mode 100644
index 000000000..54355657d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/SPI.h
@@ -0,0 +1,119 @@
+/*
+ * SPI Master library for Teknic ClearCore.
+ * Copyright (c) 2015 Arduino LLC
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _SPI_H_INCLUDED
+#define _SPI_H_INCLUDED
+
+#include <Arduino.h>
+#include "SerialBase.h"
+
+// SPI_HAS_TRANSACTION means SPI has
+//   - beginTransaction()
+//   - endTransaction()
+//   - usingInterrupt()
+//   - SPISetting(clock, bitOrder, dataMode)
+#define SPI_HAS_TRANSACTION 1
+
+// SPI_HAS_NOTUSINGINTERRUPT means that SPI has notUsingInterrupt() method
+#define SPI_HAS_NOTUSINGINTERRUPT 1
+
+#define SPI_MODE0 0x00
+#define SPI_MODE1 0x01
+#define SPI_MODE2 0x02
+#define SPI_MODE3 0x03
+
+#define MAX_SPI 10000000
+#define SPI_MIN_CLOCK_DIVIDER 1
+
+class SPISettings {
+public:
+    SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode)
+        : m_clockFreq(clock),
+          m_bitOrder(bitOrder),
+          m_dataMode(dataMode) {
+    }
+
+    // Default speed set to 4MHz, SPI mode set to MODE 0 and Bit order set to
+    // MSB first.
+    SPISettings()
+        : m_clockFreq(10000000),
+          m_bitOrder(BitOrder::MSBFIRST),
+          m_dataMode(SPI_MODE0) {
+    }
+
+private:
+    uint32_t m_clockFreq;
+    BitOrder m_bitOrder;
+    uint8_t m_dataMode;
+
+    friend class SPIClass;
+};
+
+class SPIClass {
+public:
+    SPIClass(ClearCore::SerialBase &thePort, bool isCom);
+
+    byte transfer(uint8_t data);
+    uint16_t transfer16(uint16_t data);
+    void transfer(void *buf, size_t count);
+    void transfer(const void *txbuf, void *rxbuf, size_t count,
+                  bool block = true);
+    void waitForTransfer(void);
+
+    // Transaction Functions
+    void usingInterrupt(int interruptNumber);
+    void notUsingInterrupt(int interruptNumber);
+    void beginTransaction(SPISettings settings);
+    void endTransaction(void);
+
+    // SPI Configuration methods
+    void attachInterrupt();
+    void detachInterrupt();
+
+    void begin();
+    void end();
+
+    void setBitOrder(BitOrder order);
+    void setDataMode(uint8_t uc_mode);
+    void setClockDivider(uint8_t uc_div);
+
+private:
+    void config();
+
+    ClearCore::SerialBase *m_serial;
+    bool m_isCom;
+    SPISettings m_settings;
+
+};
+
+extern SPIClass SPI;
+extern SPIClass SPI1;
+extern SPIClass SPI2;
+
+// For compatibility with sketches designed for AVR @ 16 MHz
+// New programs should use SPI.beginTransaction to set the SPI clock
+#define SPI_CLOCK_DIV2   (MAX_SPI * 2 / 8000000)
+#define SPI_CLOCK_DIV4   (MAX_SPI * 2 / 4000000)
+#define SPI_CLOCK_DIV8   (MAX_SPI * 2 / 2000000)
+#define SPI_CLOCK_DIV16  (MAX_SPI * 2 / 1000000)
+#define SPI_CLOCK_DIV32  (MAX_SPI * 2 / 500000)
+#define SPI_CLOCK_DIV64  (MAX_SPI * 2 / 250000)
+#define SPI_CLOCK_DIV128 (MAX_SPI * 2 / 125000)
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Server.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Server.h
new file mode 100644
index 000000000..6bc23e6df
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Server.h
@@ -0,0 +1,28 @@
+/*
+    Server.h - Base class that provides Server
+    Copyright (c) 2011 Adrian McEwen.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "Print.h"
+
+class Server : public Print {
+public:
+    virtual void begin() = 0;
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Stream.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Stream.cpp
new file mode 100644
index 000000000..2bf06d51c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Stream.cpp
@@ -0,0 +1,344 @@
+/*
+    Stream.cpp - adds parsing methods to Stream class
+    Copyright (c) 2008 David A. Mellis.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+    Created July 2011
+    parsing functions based on TextFinder library by Michael Margolis
+
+    findMulti/findUntil routines written by Jim Leonard/Xuth
+*/
+
+#include "Common.h"
+#include "Stream.h"
+
+#define PARSE_TIMEOUT 1000  // default number of milli-seconds to wait
+
+// private method to read stream with timeout
+int Stream::timedRead() {
+    int c;
+    _startMillis = millis();
+    do {
+        c = read();
+        if (c >= 0) {
+            return c;
+        }
+    } while (millis() - _startMillis < _timeout);
+    return -1;     // -1 indicates timeout
+}
+
+// private method to peek stream with timeout
+int Stream::timedPeek() {
+    int c;
+    _startMillis = millis();
+    do {
+        c = peek();
+        if (c >= 0) {
+            return c;
+        }
+    } while (millis() - _startMillis < _timeout);
+    return -1;     // -1 indicates timeout
+}
+
+// returns peek of the next digit in the stream or -1 if timeout
+// discards non-numeric characters
+int Stream::peekNextDigit(LookaheadMode lookahead, bool detectDecimal) {
+    int c;
+    while (1) {
+        c = timedPeek();
+
+        if (c < 0 || c == '-' || (c >= '0' && c <= '9') ||
+                (detectDecimal && c == '.')) {
+            return c;
+        }
+
+        switch (lookahead) {
+            case SKIP_NONE:
+                return -1; // Fail code.
+            case SKIP_WHITESPACE:
+                switch (c) {
+                    case ' ':
+                    case '\t':
+                    case '\r':
+                    case '\n':
+                        break;
+                    default:
+                        return -1; // Fail code.
+                }
+            case SKIP_ALL:
+                break;
+        }
+        read();  // discard non-numeric
+    }
+}
+
+// Public Methods
+//////////////////////////////////////////////////////////////
+
+// sets the maximum number of milliseconds to wait
+void Stream::setTimeout(unsigned long timeout) {
+    _timeout = timeout;
+}
+
+// find returns true if the target string is found
+bool  Stream::find(const char *target) {
+    return findUntil(target, strlen(target), NULL, 0);
+}
+
+// reads data from the stream until the target string of given length is found
+// returns true if target string is found, false if timed out
+bool Stream::find(const char *target, size_t length) {
+    return findUntil(target, length, NULL, 0);
+}
+
+// as find but search ends if the terminator string is found
+bool  Stream::findUntil(const char *target, const char *terminator) {
+    return findUntil(target, strlen(target), terminator, strlen(terminator));
+}
+
+// reads data from the stream until the target string of the given length is
+// found
+// search terminated if the terminator string is found
+// returns true if target string is found, false if terminated or timed out
+bool Stream::findUntil(const char *target, size_t targetLen,
+                       const char *terminator, size_t termLen) {
+    if (terminator == NULL) {
+        MultiTarget t[1] = {{target, targetLen, 0}};
+        return findMulti(t, 1) == 0;
+    }
+    else {
+        MultiTarget t[2] = {{target, targetLen, 0}, {terminator, termLen, 0}};
+        return findMulti(t, 2) == 0;
+    }
+}
+
+// returns the first valid (long) integer value from the current position.
+// lookahead determines how parseInt looks ahead in the stream.
+// See LookaheadMode enumeration at the top of the file.
+// Lookahead is terminated by the first character that is not a valid part of an
+//  integer. Once parsing commences, 'ignore' will be skipped in the stream.
+long Stream::parseInt(LookaheadMode lookahead, char ignore) {
+    bool isNegative = false;
+    long value = 0;
+    int c;
+
+    c = peekNextDigit(lookahead, false);
+    // ignore non numeric leading characters
+    if (c < 0) {
+        return 0; // zero returned if timeout
+    }
+
+    do {
+        if ((char)c == ignore) {
+            ; // ignore this character
+        }
+        else if (c == '-') {
+            isNegative = true;
+        }
+        else if (c >= '0' && c <= '9') {       // is c a digit?
+            value = value * 10 + c - '0';
+        }
+        read();  // consume the character we got with peek
+        c = timedPeek();
+    } while ((c >= '0' && c <= '9') || (char)c == ignore);
+
+    if (isNegative) {
+        value = -value;
+    }
+    return value;
+}
+
+// as parseInt but returns a floating point value
+float Stream::parseFloat(LookaheadMode lookahead, char ignore) {
+    bool isNegative = false;
+    bool isFraction = false;
+    long value = 0;
+    int c;
+    float fraction = 1.0;
+
+    c = peekNextDigit(lookahead, true);
+    // ignore non numeric leading characters
+    if (c < 0) {
+        return 0; // zero returned if timeout
+    }
+
+
+
+    do {
+        if ((char)c == ignore) {
+            ; // ignore
+        }
+        else if (c == '-') {
+            isNegative = true;
+        }
+        else if (c == '.') {
+            isFraction = true;
+        }
+        else if (c >= '0' && c <= '9')  {     // is c a digit?
+            value = value * 10 + c - '0';
+            if (isFraction) {
+                fraction *= 0.1;
+            }
+        }
+        read();  // consume the character we got with peek
+        c = timedPeek();
+    }
+    while ((c >= '0' && c <= '9')  || (c == '.' && !isFraction) ||
+            (char)c == ignore);
+
+    if (isNegative) {
+        value = -value;
+    }
+    if (isFraction) {
+        return value * fraction;
+    }
+    else {
+        return value;
+    }
+}
+
+// read characters from stream into buffer
+// terminates if length characters have been read, or timeout (see setTimeout)
+// returns the number of characters placed in the buffer
+// the buffer is NOT null terminated.
+//
+size_t Stream::readBytes(char *buffer, size_t length) {
+    size_t count = 0;
+    while (count < length) {
+        int c = timedRead();
+        if (c < 0) {
+            break;
+        }
+        *buffer++ = (char)c;
+        count++;
+    }
+    return count;
+}
+
+
+// as readBytes with terminator character
+// terminates if length characters have been read, timeout, or if the terminator
+// character  detected returns the number of characters placed in the buffer
+// (0 means no valid data found)
+
+size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) {
+    if (length < 1) {
+        return 0;
+    }
+    size_t index = 0;
+    while (index < length) {
+        int c = timedRead();
+        if (c < 0 || (char)c == terminator) {
+            break;
+        }
+        *buffer++ = (char)c;
+        index++;
+    }
+    return index; // return number of characters, not including null terminator
+}
+
+String Stream::readString() {
+    String ret;
+    int c = timedRead();
+    while (c >= 0) {
+        ret += (char)c;
+        c = timedRead();
+    }
+    return ret;
+}
+
+String Stream::readStringUntil(char terminator) {
+    String ret;
+    int c = timedRead();
+    while (c >= 0 && (char)c != terminator) {
+        ret += (char)c;
+        c = timedRead();
+    }
+    return ret;
+}
+
+int Stream::findMulti(struct Stream::MultiTarget *targets, int tCount) {
+    // any zero length target string automatically matches and would make
+    // a mess of the rest of the algorithm.
+    for (struct MultiTarget *t = targets; t < targets + tCount; ++t) {
+        if (t->len <= 0) {
+            return t - targets;
+        }
+    }
+
+    while (1) {
+        int c = timedRead();
+        if (c < 0) {
+            return -1;
+        }
+
+        for (struct MultiTarget *t = targets; t < targets + tCount; ++t) {
+            // the simple case is if we match, deal with that first.
+            if ((char)c == t->str[t->index]) {
+                if (++t->index == t->len) {
+                    return t - targets;
+                }
+                else {
+                    continue;
+                }
+            }
+
+            // if not we need to walk back and see if we could have matched
+            // further down the stream (ie '1112' doesn't match the first
+            // position in '11112' but it will match the second position so we
+            // can't just reset the current index to 0 when we find a mismatch.
+            if (t->index == 0) {
+                continue;
+            }
+
+            int origIndex = t->index;
+            do {
+                --t->index;
+                // first check if current char works against the new current
+                // index
+                if ((char)c != t->str[t->index]) {
+                    continue;
+                }
+
+                // if it's the only char then we're good, nothing more to check
+                if (t->index == 0) {
+                    t->index++;
+                    break;
+                }
+
+                // otherwise we need to check the rest of the found string
+                int diff = origIndex - t->index;
+                size_t i;
+                for (i = 0; i < t->index; ++i) {
+                    if (t->str[i] != t->str[i + diff]) {
+                        break;
+                    }
+                }
+
+                // if we successfully got through the previous loop then our
+                // current index is good.
+                if (i == t->index) {
+                    t->index++;
+                    break;
+                }
+
+                // otherwise we just try the next index
+            } while (t->index);
+        }
+    }
+    // unreachable
+    return -1;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Stream.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Stream.h
new file mode 100644
index 000000000..de7bb1a59
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Stream.h
@@ -0,0 +1,172 @@
+/*
+    Stream.h - base class for character-based streams.
+    Copyright (c) 2010 David A. Mellis.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+    parsing functions based on TextFinder library by Michael Margolis
+*/
+
+#pragma once
+
+#include "Print.h"
+
+// compatability macros for testing
+/*
+#define   getInt()            parseInt()
+#define   getInt(ignore)      parseInt(ignore)
+#define   getFloat()          parseFloat()
+#define   getFloat(ignore)    parseFloat(ignore)
+#define   getString( pre_string, post_string, buffer, length)
+readBytesBetween( pre_string, terminator, buffer, length)
+*/
+
+// This enumeration provides the lookahead options for parseInt(), parseFloat()
+// The rules set out here are used until either the first valid character is
+// found or a time out occurs due to lack of input.
+enum LookaheadMode {
+    SKIP_ALL,       // All invalid characters are ignored.
+    SKIP_NONE,      // Nothing is skipped, and the stream is not touched unless
+                    // the first waiting character is valid.
+    SKIP_WHITESPACE // Only tabs, spaces, line feeds & carriage returns are
+                    // skipped.
+};
+
+// a char not found in a valid ASCII numeric field
+#define NO_IGNORE_CHAR  '\x01'
+
+class Stream : public Print {
+protected:
+    // number of milliseconds to wait for the next char before aborting timed
+    // read
+    unsigned long _timeout;
+    unsigned long _startMillis;  // used for timeout measurement
+    int timedRead();    // private method to read stream with timeout
+    int timedPeek();    // private method to peek stream with timeout
+    // returns the next numeric digit in the stream or -1 if timeout
+    int peekNextDigit(LookaheadMode lookahead, bool detectDecimal);
+
+public:
+    virtual int available() = 0;
+    virtual int read() = 0;
+    virtual int peek() = 0;
+    virtual void flush() = 0;
+
+    Stream() {
+        _timeout = 1000;
+    }
+
+// parsing methods
+
+    // sets maximum milliseconds to wait for stream data, default is 1 second
+    void setTimeout(unsigned long timeout);
+    unsigned long getTimeout(void) {
+        return _timeout;
+    }
+
+    // reads data from the stream until the target string is found
+    bool find(const char *target);
+    bool find(const uint8_t *target) {
+        return find((const char *)target);
+    }
+    // returns true if target string is found, false if timed out
+    // (see setTimeout)
+
+    // reads data from the stream until the target string of given length is
+    // found
+    bool find(const char *target, size_t length);
+    bool find(const uint8_t *target, size_t length) {
+        return find((const char *)target, length);
+    }
+    // returns true if target string is found, false if timed out
+
+    bool find(char target) {
+        return find(&target, 1);
+    }
+
+    // as find but search ends if the terminator string is found
+    bool findUntil(const char *target, const char *terminator);
+    bool findUntil(const uint8_t *target, const char *terminator) {
+        return findUntil((const char *)target, terminator);
+    }
+
+    // as above but search ends if the terminate string is found
+    bool findUntil(const char *target, size_t targetLen,
+                   const char *terminate, size_t termLen);
+    bool findUntil(const uint8_t *target, size_t targetLen,
+                   const char *terminate, size_t termLen) {
+        return findUntil((const char *)target, targetLen, terminate, termLen);
+    }
+
+    long parseInt(LookaheadMode lookahead = SKIP_ALL,
+                  char ignore = NO_IGNORE_CHAR);
+    // returns the first valid (long) integer value from the current position.
+    // lookahead determines how parseInt looks ahead in the stream.
+    // See LookaheadMode enumeration at the top of the file.
+    // Lookahead is terminated by the first character that is not a valid part
+    // of an integer. Once parsing commences, 'ignore' will be skipped in the
+    // stream.
+
+    float parseFloat(LookaheadMode lookahead = SKIP_ALL,
+                     char ignore = NO_IGNORE_CHAR);
+    // float version of parseInt
+
+    // read chars from stream into buffer
+    size_t readBytes(char *buffer, size_t length);
+    size_t readBytes(uint8_t *buffer, size_t length) {
+        return readBytes((char *)buffer, length);
+    }
+    // terminates if length characters have been read or timeout (see
+    // setTimeout)
+    // returns the number of characters placed in the buffer (0 means no valid
+    // data found)
+
+    // as readBytes with terminator character
+    size_t readBytesUntil(char terminator, char *buffer, size_t length);
+    size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) {
+        return readBytesUntil(terminator, (char *)buffer, length);
+    }
+    // terminates if length characters have been read, timeout, or if the
+    // terminator character  detected
+    // returns the number of characters placed in the buffer (0 means no valid
+    // data found)
+
+    // Arduino String functions to be added here
+    String readString();
+    String readStringUntil(char terminator);
+
+protected:
+    long parseInt(char ignore) {
+        return parseInt(SKIP_ALL, ignore);
+    }
+    float parseFloat(char ignore) {
+        return parseFloat(SKIP_ALL, ignore);
+    }
+    // These overload exists for compatibility with any class that has derived
+    // Stream and used parseFloat/Int with a custom ignore character. To keep
+    // the public API simple, these overload remains protected.
+
+    struct MultiTarget {
+        const char *str;  // string you're searching for
+        size_t len;       // length of string you're searching for
+        size_t index;     // index used by the search routine.
+    };
+
+    // This allows you to search for an arbitrary number of strings.
+    // Returns index of the target that is found first or -1 if timeout occurs.
+    int findMulti(struct MultiTarget *targets, int tCount);
+};
+
+#undef NO_IGNORE_CHAR
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/String.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/String.cpp
new file mode 100644
index 000000000..1593c272a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/String.cpp
@@ -0,0 +1,820 @@
+/*
+    String library for Wiring & Arduino
+    ...mostly rewritten by Paul Stoffregen...
+    Copyright (c) 2009-10 Hernando Barragan.  All rights reserved.
+    Copyright 2011, Paul Stoffregen, paul@pjrc.com
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "ArduinoString.h"
+#include "itoa.h"
+#include "deprecated-avr-comp/avr/dtostrf.h"
+
+/*********************************************/
+/*  Constructors                             */
+/*********************************************/
+
+String::String(const char *cstr) {
+    init();
+    if (cstr) {
+        copy(cstr, strlen(cstr));
+    }
+}
+
+String::String(const String &value) {
+    init();
+    *this = value;
+}
+
+String::String(const __FlashStringHelper *pstr) {
+    init();
+    *this = pstr;
+}
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+String::String(String &&rval) {
+    init();
+    move(rval);
+}
+String::String(StringSumHelper &&rval) {
+    init();
+    move(rval);
+}
+#endif
+
+String::String(char c) {
+    init();
+    char buf[2];
+    buf[0] = c;
+    buf[1] = 0;
+    *this = buf;
+}
+
+String::String(unsigned char value, unsigned char base) {
+    init();
+    char buf[1 + 8 * sizeof(unsigned char)];
+    utoa(value, buf, base);
+    *this = buf;
+}
+
+String::String(int value, unsigned char base) {
+    init();
+    char buf[2 + 8 * sizeof(int)];
+    itoa(value, buf, base);
+    *this = buf;
+}
+
+String::String(unsigned int value, unsigned char base) {
+    init();
+    char buf[1 + 8 * sizeof(unsigned int)];
+    utoa(value, buf, base);
+    *this = buf;
+}
+
+String::String(long value, unsigned char base) {
+    init();
+    char buf[2 + 8 * sizeof(long)];
+    ltoa(value, buf, base);
+    *this = buf;
+}
+
+String::String(unsigned long value, unsigned char base) {
+    init();
+    char buf[1 + 8 * sizeof(unsigned long)];
+    ultoa(value, buf, base);
+    *this = buf;
+}
+
+String::String(float value, unsigned char decimalPlaces) {
+    init();
+    char buf[33];
+    *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);
+}
+
+String::String(double value, unsigned char decimalPlaces) {
+    init();
+    char buf[33];
+    *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);
+}
+
+String::~String() {
+    free(buffer);
+}
+
+/*********************************************/
+/*  Memory Management                        */
+/*********************************************/
+
+inline void String::init(void) {
+    buffer = NULL;
+    capacity = 0;
+    len = 0;
+}
+
+void String::invalidate(void) {
+    if (buffer) {
+        free(buffer);
+    }
+    buffer = NULL;
+    capacity = len = 0;
+}
+
+unsigned char String::reserve(unsigned int size) {
+    if (buffer && capacity >= size) {
+        return 1;
+    }
+    if (changeBuffer(size)) {
+        if (len == 0) {
+            buffer[0] = 0;
+        }
+        return 1;
+    }
+    return 0;
+}
+
+unsigned char String::changeBuffer(unsigned int maxStrLen) {
+    char *newbuffer = (char *)realloc(buffer, maxStrLen + 1);
+    if (newbuffer) {
+        buffer = newbuffer;
+        capacity = maxStrLen;
+        return 1;
+    }
+    return 0;
+}
+
+/*********************************************/
+/*  Copy and Move                            */
+/*********************************************/
+
+String &String::copy(const char *cstr, unsigned int length) {
+    if (!reserve(length)) {
+        invalidate();
+        return *this;
+    }
+    len = length;
+    strcpy(buffer, cstr);
+    return *this;
+}
+
+String &String::copy(const __FlashStringHelper *pstr, unsigned int length) {
+    if (!reserve(length)) {
+        invalidate();
+        return *this;
+    }
+    len = length;
+    strcpy_P(buffer, (PGM_P)pstr);
+    return *this;
+}
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+void String::move(String &rhs) {
+    if (buffer) {
+        if (rhs && capacity >= rhs.len) {
+            strcpy(buffer, rhs.buffer);
+            len = rhs.len;
+            rhs.len = 0;
+            return;
+        }
+        else {
+            free(buffer);
+        }
+    }
+    buffer = rhs.buffer;
+    capacity = rhs.capacity;
+    len = rhs.len;
+    rhs.buffer = NULL;
+    rhs.capacity = 0;
+    rhs.len = 0;
+}
+#endif
+
+String &String::operator = (const String &rhs) {
+    if (this == &rhs) {
+        return *this;
+    }
+
+    if (rhs.buffer) {
+        copy(rhs.buffer, rhs.len);
+    }
+    else {
+        invalidate();
+    }
+
+    return *this;
+}
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+String &String::operator = (String &&rval) {
+    if (this != &rval) {
+        move(rval);
+    }
+    return *this;
+}
+
+String &String::operator = (StringSumHelper &&rval) {
+    if (this != &rval) {
+        move(rval);
+    }
+    return *this;
+}
+#endif
+
+String &String::operator = (const char *cstr) {
+    if (cstr) {
+        copy(cstr, strlen(cstr));
+    }
+    else {
+        invalidate();
+    }
+
+    return *this;
+}
+
+String &String::operator = (const __FlashStringHelper *pstr) {
+    if (pstr) {
+        copy(pstr, strlen_P((PGM_P)pstr));
+    }
+    else {
+        invalidate();
+    }
+
+    return *this;
+}
+
+/*********************************************/
+/*  concat                                   */
+/*********************************************/
+
+unsigned char String::concat(const String &s) {
+    return concat(s.buffer, s.len);
+}
+
+unsigned char String::concat(const char *cstr, unsigned int length) {
+    unsigned int newlen = len + length;
+    if (!cstr) {
+        return 0;
+    }
+    if (length == 0) {
+        return 1;
+    }
+    if (!reserve(newlen)) {
+        return 0;
+    }
+    strcpy(buffer + len, cstr);
+    len = newlen;
+    return 1;
+}
+
+unsigned char String::concat(const char *cstr) {
+    if (!cstr) {
+        return 0;
+    }
+    return concat(cstr, strlen(cstr));
+}
+
+unsigned char String::concat(char c) {
+    char buf[2];
+    buf[0] = c;
+    buf[1] = 0;
+    return concat(buf, 1);
+}
+
+unsigned char String::concat(unsigned char num) {
+    char buf[1 + 3 * sizeof(unsigned char)];
+    itoa(num, buf, 10);
+    return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(int num) {
+    char buf[2 + 3 * sizeof(int)];
+    itoa(num, buf, 10);
+    return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(unsigned int num) {
+    char buf[1 + 3 * sizeof(unsigned int)];
+    utoa(num, buf, 10);
+    return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(long num) {
+    char buf[2 + 3 * sizeof(long)];
+    ltoa(num, buf, 10);
+    return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(unsigned long num) {
+    char buf[1 + 3 * sizeof(unsigned long)];
+    ultoa(num, buf, 10);
+    return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(float num) {
+    char buf[20];
+    char *string = dtostrf(num, 4, 2, buf);
+    return concat(string, strlen(string));
+}
+
+unsigned char String::concat(double num) {
+    char buf[20];
+    char *string = dtostrf(num, 4, 2, buf);
+    return concat(string, strlen(string));
+}
+
+unsigned char String::concat(const __FlashStringHelper *str) {
+    if (!str) {
+        return 0;
+    }
+    int length = strlen_P((const char *) str);
+    if (length == 0) {
+        return 1;
+    }
+    unsigned int newlen = len + length;
+    if (!reserve(newlen)) {
+        return 0;
+    }
+    strcpy_P(buffer + len, (const char *) str);
+    len = newlen;
+    return 1;
+}
+
+/*********************************************/
+/*  Concatenate                              */
+/*********************************************/
+
+StringSumHelper &operator + (const StringSumHelper &lhs, const String &rhs) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(rhs.buffer, rhs.len)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, const char *cstr) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!cstr || !a.concat(cstr, strlen(cstr))) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, char c) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(c)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, unsigned char num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, int num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, unsigned int num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, long num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, unsigned long num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, float num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs, double num) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(num)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+StringSumHelper &operator + (const StringSumHelper &lhs,
+                             const __FlashStringHelper *rhs) {
+    StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+    if (!a.concat(rhs)) {
+        a.invalidate();
+    }
+    return a;
+}
+
+/*********************************************/
+/*  Comparison                               */
+/*********************************************/
+
+int String::compareTo(const String &s) const {
+    if (!buffer || !s.buffer) {
+        if (s.buffer && s.len > 0) {
+            return 0 - *(unsigned char *)s.buffer;
+        }
+        if (buffer && len > 0) {
+            return *(unsigned char *)buffer;
+        }
+        return 0;
+    }
+    return strcmp(buffer, s.buffer);
+}
+
+int String::compareTo(const char *cstr) const {
+    if (!buffer || !cstr) {
+        if (cstr && !*cstr) {
+            return 0 - *(unsigned char *)cstr;
+        }
+        if (buffer && len > 0) {
+            return *(unsigned char *)buffer;
+        }
+        return 0;
+    }
+    return strcmp(buffer, cstr);
+}
+
+unsigned char String::equals(const String &s2) const {
+    return (len == s2.len && compareTo(s2) == 0);
+}
+
+unsigned char String::equals(const char *cstr) const {
+    if (len == 0) {
+        return (cstr == NULL || *cstr == 0);
+    }
+    if (cstr == NULL) {
+        return buffer[0] == 0;
+    }
+    return strcmp(buffer, cstr) == 0;
+}
+
+unsigned char String::equalsIgnoreCase(const String &s2) const {
+    if (this == &s2) {
+        return 1;
+    }
+    if (len != s2.len) {
+        return 0;
+    }
+    if (len == 0) {
+        return 1;
+    }
+    const char *p1 = buffer;
+    const char *p2 = s2.buffer;
+    while (*p1) {
+        if (tolower(*p1++) != tolower(*p2++)) {
+            return 0;
+        }
+    }
+    return 1;
+}
+
+unsigned char String::startsWith(const String &s2) const {
+    if (len < s2.len) {
+        return 0;
+    }
+    return startsWith(s2, 0);
+}
+
+unsigned char String::startsWith(const String &s2, unsigned int offset) const {
+    if (offset > len - s2.len || !buffer || !s2.buffer) {
+        return 0;
+    }
+    return strncmp(&buffer[offset], s2.buffer, s2.len) == 0;
+}
+
+unsigned char String::endsWith(const String &s2) const {
+    if (len < s2.len || !buffer || !s2.buffer) {
+        return 0;
+    }
+    return strcmp(&buffer[len - s2.len], s2.buffer) == 0;
+}
+
+/*********************************************/
+/*  Character Access                         */
+/*********************************************/
+
+char String::charAt(unsigned int loc) const {
+    return operator[](loc);
+}
+
+void String::setCharAt(unsigned int loc, char c) {
+    if (loc < len) {
+        buffer[loc] = c;
+    }
+}
+
+char &String::operator[](unsigned int index) {
+    static char dummy_writable_char;
+    if (index >= len || !buffer) {
+        dummy_writable_char = 0;
+        return dummy_writable_char;
+    }
+    return buffer[index];
+}
+
+char String::operator[](unsigned int index) const {
+    if (index >= len || !buffer) {
+        return 0;
+    }
+    return buffer[index];
+}
+
+void String::getBytes(unsigned char *buf, unsigned int bufsize,
+                      unsigned int index) const {
+    if (!bufsize || !buf) {
+        return;
+    }
+    if (index >= len) {
+        buf[0] = 0;
+        return;
+    }
+    unsigned int n = bufsize - 1;
+    if (n > len - index) {
+        n = len - index;
+    }
+    strncpy((char *)buf, buffer + index, n);
+    buf[n] = 0;
+}
+
+/*********************************************/
+/*  Search                                   */
+/*********************************************/
+
+int String::indexOf(char c) const {
+    return indexOf(c, 0);
+}
+
+int String::indexOf(char ch, unsigned int fromIndex) const {
+    if (fromIndex >= len) {
+        return -1;
+    }
+    const char *temp = strchr(buffer + fromIndex, ch);
+    if (temp == NULL) {
+        return -1;
+    }
+    return temp - buffer;
+}
+
+int String::indexOf(const String &s2) const {
+    return indexOf(s2, 0);
+}
+
+int String::indexOf(const String &s2, unsigned int fromIndex) const {
+    if (fromIndex >= len) {
+        return -1;
+    }
+    const char *found = strstr(buffer + fromIndex, s2.buffer);
+    if (found == NULL) {
+        return -1;
+    }
+    return found - buffer;
+}
+
+int String::lastIndexOf(char theChar) const {
+    return lastIndexOf(theChar, len - 1);
+}
+
+int String::lastIndexOf(char ch, unsigned int fromIndex) const {
+    if (fromIndex >= len) {
+        return -1;
+    }
+    char tempchar = buffer[fromIndex + 1];
+    buffer[fromIndex + 1] = '\0';
+    char *temp = strrchr(buffer, ch);
+    buffer[fromIndex + 1] = tempchar;
+    if (temp == NULL) {
+        return -1;
+    }
+    return temp - buffer;
+}
+
+int String::lastIndexOf(const String &s2) const {
+    return lastIndexOf(s2, len - s2.len);
+}
+
+int String::lastIndexOf(const String &s2, unsigned int fromIndex) const {
+    if (s2.len == 0 || len == 0 || s2.len > len) {
+        return -1;
+    }
+    if (fromIndex >= len) {
+        fromIndex = len - 1;
+    }
+    int found = -1;
+    for (char *p = buffer; p <= buffer + fromIndex; p++) {
+        p = strstr(p, s2.buffer);
+        if (!p) {
+            break;
+        }
+        if ((unsigned int)(p - buffer) <= fromIndex) {
+            found = p - buffer;
+        }
+    }
+    return found;
+}
+
+String String::substring(unsigned int left, unsigned int right) const {
+    if (left > right) {
+        unsigned int temp = right;
+        right = left;
+        left = temp;
+    }
+    String out;
+    if (left >= len) {
+        return out;
+    }
+    if (right > len) {
+        right = len;
+    }
+    char temp = buffer[right];  // save the replaced character
+    buffer[right] = '\0';
+    out = buffer + left;  // pointer arithmetic
+    buffer[right] = temp;  //restore character
+    return out;
+}
+
+/*********************************************/
+/*  Modification                             */
+/*********************************************/
+
+void String::replace(char find, char replace) {
+    if (!buffer) {
+        return;
+    }
+    for (char *p = buffer; *p; p++) {
+        if (*p == find) {
+            *p = replace;
+        }
+    }
+}
+
+void String::replace(const String &find, const String &replace) {
+    if (len == 0 || find.len == 0) {
+        return;
+    }
+    int diff = replace.len - find.len;
+    char *readFrom = buffer;
+    char *foundAt;
+    if (diff == 0) {
+        while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
+            memcpy(foundAt, replace.buffer, replace.len);
+            readFrom = foundAt + replace.len;
+        }
+    }
+    else if (diff < 0) {
+        char *writeTo = buffer;
+        while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
+            unsigned int n = foundAt - readFrom;
+            memcpy(writeTo, readFrom, n);
+            writeTo += n;
+            memcpy(writeTo, replace.buffer, replace.len);
+            writeTo += replace.len;
+            readFrom = foundAt + find.len;
+            len += diff;
+        }
+        strcpy(writeTo, readFrom);
+    }
+    else {
+        unsigned int size = len; // compute size needed for result
+        while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
+            readFrom = foundAt + find.len;
+            size += diff;
+        }
+        if (size == len) {
+            return;
+        }
+        if (size > capacity && !changeBuffer(size)) {
+            return; // XXX: tell user!
+        }
+        int index = len - 1;
+        while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) {
+            readFrom = buffer + index + find.len;
+            memmove(readFrom + diff, readFrom, len - (readFrom - buffer));
+            len += diff;
+            buffer[len] = 0;
+            memcpy(buffer + index, replace.buffer, replace.len);
+            index--;
+        }
+    }
+}
+
+void String::remove(unsigned int index) {
+    // Pass the biggest integer as the count. The remove method
+    // below will take care of truncating it at the end of the
+    // string.
+    remove(index, (unsigned int) -1);
+}
+
+void String::remove(unsigned int index, unsigned int count) {
+    if (index >= len) {
+        return;
+    }
+    if (count == 0) {
+        return;
+    }
+    if (count > len - index) {
+        count = len - index;
+    }
+    char *writeTo = buffer + index;
+    len = len - count;
+    memmove(writeTo, buffer + index + count, len - index);
+    buffer[len] = 0;
+}
+
+void String::toLowerCase(void) {
+    if (!buffer) {
+        return;
+    }
+    for (char *p = buffer; *p; p++) {
+        *p = tolower(*p);
+    }
+}
+
+void String::toUpperCase(void) {
+    if (!buffer) {
+        return;
+    }
+    for (char *p = buffer; *p; p++) {
+        *p = toupper(*p);
+    }
+}
+
+void String::trim(void) {
+    if (!buffer || len == 0) {
+        return;
+    }
+    char *begin = buffer;
+    while (isspace(*begin)) {
+        begin++;
+    }
+    char *end = buffer + len - 1;
+    while (isspace(*end) && end >= begin) {
+        end--;
+    }
+    len = end + 1 - begin;
+    if (begin > buffer) {
+        memmove(buffer, begin, len);
+    }
+    buffer[len] = 0;
+}
+
+/*********************************************/
+/*  Parsing / Conversion                     */
+/*********************************************/
+
+long String::toInt(void) const {
+    if (buffer) {
+        return atol(buffer);
+    }
+    return 0;
+}
+
+float String::toFloat(void) const {
+    return float(toDouble());
+}
+
+double String::toDouble(void) const {
+    if (buffer) {
+        return atof(buffer);
+    }
+    return 0;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Udp.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Udp.h
new file mode 100644
index 000000000..b561359bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/Udp.h
@@ -0,0 +1,98 @@
+/*
+ *  Udp.cpp: Library to send/receive UDP packets.
+ *
+ * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray
+ * for mentioning these)
+ * 1) UDP does not guarantee the order in which assembled UDP packets are
+ * received. This might not happen often in practice, but in larger network
+ * topologies, a UDP packet can be received out of sequence.
+ * 2) UDP does not guard against lost packets - so packets *can* disappear
+ * without the sender being aware of it. Again, this may not be a concern in
+ * practice on small local networks.
+ * For more information, see http://www.cafeaulait.org/course/week12/35.html
+ *
+ * MIT License:
+ * Copyright (c) 2008 Bjoern Hartmann
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * bjoern@cs.stanford.edu 12/30/2008
+ */
+
+#pragma once
+
+#include "Stream.h"
+#include "IPAddress.h"
+
+class UDP : public Stream {
+
+public:
+    // initialize, start listening on specified port. Returns 1 if successful,
+    // 0 if there are no sockets available to use
+    virtual uint8_t begin(uint16_t) = 0;
+    virtual void stop() = 0; // Finish with the UDP socket
+
+    // Sending UDP packets
+
+    // Start building up a packet to send to the remote host specific in ip and
+    // port
+    // Returns 1 if successful, 0 if there was a problem with the supplied IP
+    // address or port
+    virtual int beginPacket(IPAddress ip, uint16_t port) = 0;
+    // Start building up a packet to send to the remote host specific in host
+    // and port
+    // Returns 1 if successful, 0 if there was a problem resolving the hostname
+    // or port
+    virtual int beginPacket(const char *host, uint16_t port) = 0;
+    // Finish off this packet and send it
+    // Returns 1 if the packet was sent successfully, 0 if there was an error
+    virtual int endPacket() = 0;
+    // Write a single byte into the packet
+    virtual size_t write(uint8_t) = 0;
+    // Write size bytes from buffer into the packet
+    virtual size_t write(const uint8_t *buffer, size_t size) = 0;
+
+    // Start processing the next available incoming packet
+    // Returns the size of the packet in bytes, or 0 if no packets are available
+    virtual int parsePacket() = 0;
+    // Number of bytes remaining in the current packet
+    virtual int available() = 0;
+    // Read a single byte from the current packet
+    virtual int read() = 0;
+    // Read up to len bytes from the current packet and place them into buffer
+    // Returns the number of bytes read, or 0 if none are available
+    virtual int read(unsigned char *buffer, size_t len) = 0;
+    // Read up to len characters from the current packet and place them into
+    // buffer
+    // Returns the number of characters read, or 0 if none are available
+    virtual int read(char *buffer, size_t len) = 0;
+    // Return the next byte from the current packet without moving on to the
+    // next byte
+    virtual int peek() = 0;
+    virtual void flush() = 0;   // Finish reading the current packet
+
+    // Return the IP address of the host who sent the current incoming packet
+    virtual IPAddress remoteIP() = 0;
+    // Return the port of the host who sent the current incoming packet
+    virtual uint16_t remotePort() = 0;
+protected:
+    uint8_t *rawIPAddress(IPAddress &addr) {
+        return addr.raw_address();
+    };
+};
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/WCharacter.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/WCharacter.h
new file mode 100644
index 000000000..39ee6a4fc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/WCharacter.h
@@ -0,0 +1,137 @@
+/*
+    WCharacter.h - Character utility functions for Wiring & Arduino
+    Copyright (c) 2010 Hernando Barragan.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef Character_h
+#define Character_h
+
+#include <ctype.h>
+
+// WCharacter.h prototypes
+inline bool isAlphaNumeric(int c) __attribute__((always_inline));
+inline bool isAlpha(int c) __attribute__((always_inline));
+inline bool isAscii(int c) __attribute__((always_inline));
+inline bool isWhitespace(int c) __attribute__((always_inline));
+inline bool isControl(int c) __attribute__((always_inline));
+inline bool isDigit(int c) __attribute__((always_inline));
+inline bool isGraph(int c) __attribute__((always_inline));
+inline bool isLowerCase(int c) __attribute__((always_inline));
+inline bool isPrintable(int c) __attribute__((always_inline));
+inline bool isPunct(int c) __attribute__((always_inline));
+inline bool isSpace(int c) __attribute__((always_inline));
+inline bool isUpperCase(int c) __attribute__((always_inline));
+inline bool isHexadecimalDigit(int c) __attribute__((always_inline));
+inline int toAscii(int c) __attribute__((always_inline));
+inline int toLowerCase(int c) __attribute__((always_inline));
+inline int toUpperCase(int c)__attribute__((always_inline));
+
+
+// Checks for an alphanumeric character.
+// It is equivalent to (isalpha(c) || isdigit(c)).
+inline bool isAlphaNumeric(int c) {
+    return (isalnum(c) == 0 ? false : true);
+}
+
+// Checks for an alphabetic character.
+// It is equivalent to (isupper(c) || islower(c)).
+inline bool isAlpha(int c) {
+    return (isalpha(c) == 0 ? false : true);
+}
+
+// Checks whether c is a 7-bit unsigned char value
+// that fits into the ASCII character set.
+inline bool isAscii(int c) {
+    return (isascii(c) == 0 ? false : true);
+}
+
+// Checks for a blank character, that is, a space or a tab.
+inline bool isWhitespace(int c) {
+    return (isblank(c) == 0 ? false : true);
+}
+
+// Checks for a control character.
+inline bool isControl(int c) {
+    return (iscntrl(c) == 0 ? false : true);
+}
+
+// Checks for a digit (0 through 9).
+inline bool isDigit(int c) {
+    return (isdigit(c) == 0 ? false : true);
+}
+
+// Checks for any printable character except space.
+inline bool isGraph(int c) {
+    return (isgraph(c) == 0 ? false : true);
+}
+
+// Checks for a lower-case character.
+inline bool isLowerCase(int c) {
+    return (islower(c) == 0 ? false : true);
+}
+
+// Checks for any printable character including space.
+inline bool isPrintable(int c) {
+    return (isprint(c) == 0 ? false : true);
+}
+
+// Checks for any printable character which is not a space
+// or an alphanumeric character.
+inline bool isPunct(int c) {
+    return (ispunct(c) == 0 ? false : true);
+}
+
+// Checks for white-space characters. For the avr-libc library,
+// these are: space, formfeed ('\f'), newline ('\n'), carriage
+// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v').
+inline bool isSpace(int c) {
+    return (isspace(c) == 0 ? false : true);
+}
+
+// Checks for an uppercase letter.
+inline bool isUpperCase(int c) {
+    return (isupper(c) == 0 ? false : true);
+}
+
+// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7
+// 8 9 a b c d e f A B C D E F.
+inline bool isHexadecimalDigit(int c) {
+    return (isxdigit(c) == 0 ? false : true);
+}
+
+// Converts c to a 7-bit unsigned char value that fits into the
+// ASCII character set, by clearing the high-order bits.
+inline int toAscii(int c) {
+    return toascii(c);
+}
+
+// Warning:
+// Many people will be unhappy if you use this function.
+// This function will convert accented letters into random
+// characters.
+
+// Converts the letter c to lower case, if possible.
+inline int toLowerCase(int c) {
+    return tolower(c);
+}
+
+// Converts the letter c to upper case, if possible.
+inline int toUpperCase(int c) {
+    return toupper(c);
+}
+
+#endif
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/dtostrf.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/dtostrf.h
new file mode 100644
index 000000000..2d287ca1b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/dtostrf.h
@@ -0,0 +1,34 @@
+/*
+  dtostrf - Emulation for dtostrf function from avr-libc
+  Copyright (c) 2015 Arduino LLC.  All rights reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#if !defined(ARDUINO_ARCH_AVR)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+char *dtostrf(double val, signed char width, unsigned char prec, char *sout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/interrupt.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/interrupt.h
new file mode 100644
index 000000000..950509dde
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/interrupt.h
@@ -0,0 +1,23 @@
+/*
+  Copyright (c) 2015 Arduino LCC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/*
+  Empty file.
+  This file is here to allow compatibility with sketches (made for AVR)
+  that includes <AVR/interrupt.h>
+*/
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/pgmspace.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/pgmspace.h
new file mode 100644
index 000000000..97040b2ba
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated-avr-comp/avr/pgmspace.h
@@ -0,0 +1,122 @@
+/*
+  pgmspace.h - Definitions for compatibility with AVR pgmspace macros
+
+  Copyright (c) 2015 Arduino LLC
+
+  Based on work of Paul Stoffregen on Teensy 3 (http://pjrc.com)
+
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+
+  The above copyright notice and this permission notice shall be included in
+  all copies or substantial portions of the Software.
+
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE
+*/
+
+#ifndef __PGMSPACE_H_
+#define __PGMSPACE_H_ 1
+
+#include <inttypes.h>
+
+#define PROGMEM
+#define PGM_P  const char *
+#define PSTR(str) (str)
+
+#define _SFR_BYTE(n) (n)
+
+typedef void prog_void;
+typedef char prog_char;
+typedef unsigned char prog_uchar;
+typedef int8_t prog_int8_t;
+typedef uint8_t prog_uint8_t;
+typedef int16_t prog_int16_t;
+typedef uint16_t prog_uint16_t;
+typedef int32_t prog_int32_t;
+typedef uint32_t prog_uint32_t;
+typedef int64_t prog_int64_t;
+typedef uint64_t prog_uint64_t;
+
+typedef const void *int_farptr_t;
+typedef const void *uint_farptr_t;
+
+#define memchr_P(s, c, n) memchr((s), (c), (n))
+#define memcmp_P(s1, s2, n) memcmp((s1), (s2), (n))
+#define memccpy_P(dest, src, c, n) memccpy((dest), (src), (c), (n))
+#define memcpy_P(dest, src, n) memcpy((dest), (src), (n))
+#define memmem_P(haystack, haystacklen, needle, needlelen) memmem((haystack), (haystacklen), (needle), (needlelen))
+#define memrchr_P(s, c, n) memrchr((s), (c), (n))
+#define strcat_P(dest, src) strcat((dest), (src))
+#define strchr_P(s, c) strchr((s), (c))
+#define strchrnul_P(s, c) strchrnul((s), (c))
+#define strcmp_P(a, b) strcmp((a), (b))
+#define strcpy_P(dest, src) strcpy((dest), (src))
+#define strcasecmp_P(s1, s2) strcasecmp((s1), (s2))
+#define strcasestr_P(haystack, needle) strcasestr((haystack), (needle))
+#define strcspn_P(s, accept) strcspn((s), (accept))
+#define strlcat_P(s1, s2, n) strlcat((s1), (s2), (n))
+#define strlcpy_P(s1, s2, n) strlcpy((s1), (s2), (n))
+#define strlen_P(a) strlen((a))
+#define strnlen_P(s, n) strnlen((s), (n))
+#define strncmp_P(s1, s2, n) strncmp((s1), (s2), (n))
+#define strncasecmp_P(s1, s2, n) strncasecmp((s1), (s2), (n))
+#define strncat_P(s1, s2, n) strncat((s1), (s2), (n))
+#define strncpy_P(s1, s2, n) strncpy((s1), (s2), (n))
+#define strpbrk_P(s, accept) strpbrk((s), (accept))
+#define strrchr_P(s, c) strrchr((s), (c))
+#define strsep_P(sp, delim) strsep((sp), (delim))
+#define strspn_P(s, accept) strspn((s), (accept))
+#define strstr_P(a, b) strstr((a), (b))
+#define strtok_P(s, delim) strtok((s), (delim))
+#define strtok_rP(s, delim, last) strtok((s), (delim), (last))
+
+#define strlen_PF(a) strlen((a))
+#define strnlen_PF(src, len) strnlen((src), (len))
+#define memcpy_PF(dest, src, len) memcpy((dest), (src), (len))
+#define strcpy_PF(dest, src) strcpy((dest), (src))
+#define strncpy_PF(dest, src, len) strncpy((dest), (src), (len))
+#define strcat_PF(dest, src) strcat((dest), (src))
+#define strlcat_PF(dest, src, len) strlcat((dest), (src), (len))
+#define strncat_PF(dest, src, len) strncat((dest), (src), (len))
+#define strcmp_PF(s1, s2) strcmp((s1), (s2))
+#define strncmp_PF(s1, s2, n) strncmp((s1), (s2), (n))
+#define strcasecmp_PF(s1, s2) strcasecmp((s1), (s2))
+#define strncasecmp_PF(s1, s2, n) strncasecmp((s1), (s2), (n))
+#define strstr_PF(s1, s2) strstr((s1), (s2))
+#define strlcpy_PF(dest, src, n) strlcpy((dest), (src), (n))
+#define memcmp_PF(s1, s2, n) memcmp((s1), (s2), (n))
+
+#define sprintf_P(s, f, ...) sprintf((s), (f), __VA_ARGS__)
+#define snprintf_P(s, f, ...) snprintf((s), (f), __VA_ARGS__)
+
+#define pgm_read_byte(addr) (*(const unsigned char *)(addr))
+#define pgm_read_word(addr) (*(const unsigned short *)(addr))
+#define pgm_read_dword(addr) (*(const unsigned long *)(addr))
+#define pgm_read_float(addr) (*(const float *)(addr))
+#define pgm_read_ptr(addr) (*(const void *)(addr))
+
+#define pgm_read_byte_near(addr) pgm_read_byte(addr)
+#define pgm_read_word_near(addr) pgm_read_word(addr)
+#define pgm_read_dword_near(addr) pgm_read_dword(addr)
+#define pgm_read_float_near(addr) pgm_read_float(addr)
+#define pgm_read_ptr_near(addr) pgm_read_ptr(addr)
+
+#define pgm_read_byte_far(addr) pgm_read_byte(addr)
+#define pgm_read_word_far(addr) pgm_read_word(addr)
+#define pgm_read_dword_far(addr) pgm_read_dword(addr)
+#define pgm_read_float_far(addr) pgm_read_float(addr)
+#define pgm_read_ptr_far(addr) pgm_read_ptr(addr)
+
+#define pgm_get_far_address(addr) (&(addr))
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Client.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Client.h
new file mode 100644
index 000000000..5f8d4be97
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Client.h
@@ -0,0 +1,25 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including Client.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../Client.h"
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/HardwareSerial.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/HardwareSerial.h
new file mode 100644
index 000000000..19d77c78d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/HardwareSerial.h
@@ -0,0 +1,25 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including HardwareSerial.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../HardwareSerial.h"
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/IPAddress.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/IPAddress.h
new file mode 100644
index 000000000..bf7fb7f0e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/IPAddress.h
@@ -0,0 +1,25 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including IPAddress.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../IPAddress.h"
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Print.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Print.h
new file mode 100644
index 000000000..2ac088d82
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Print.h
@@ -0,0 +1,24 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including Print.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../Print.h"
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Printable.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Printable.h
new file mode 100644
index 000000000..bd7212640
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Printable.h
@@ -0,0 +1,24 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including Printable.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../Printable.h"
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Server.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Server.h
new file mode 100644
index 000000000..f3b02c168
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Server.h
@@ -0,0 +1,25 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including Server.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../Server.h"
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Stream.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Stream.h
new file mode 100644
index 000000000..aa5dc8e04
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Stream.h
@@ -0,0 +1,25 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including Stream.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../Stream.h"
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Udp.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Udp.h
new file mode 100644
index 000000000..569806037
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/Udp.h
@@ -0,0 +1,25 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including Udp.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../Udp.h"
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/WString.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/WString.h
new file mode 100644
index 000000000..072323e00
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/deprecated/WString.h
@@ -0,0 +1,24 @@
+/*
+  Copyright 2016, Arduino LLC.  All Right Reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// including WString.h is deprecated, for all future projects use Arduino.h instead
+
+// This include is added for compatibility, it will be remove on the next
+// major release of the API
+#include "../String.h"
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/dtostrf.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/dtostrf.c
new file mode 100644
index 000000000..301d8bbc6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/dtostrf.c
@@ -0,0 +1,37 @@
+/*
+    dtostrf - Emulation for dtostrf function from avr-libc
+    Copyright (c) 2016 Arduino LLC.  All rights reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// This is a default implementation for dtostrf function.
+// This file should be used if the standard lib doesn't provide an
+// implementation of dtostrf.
+
+// Create a file called "dtostrf.c" with the following include:
+// #include "api/deprecated-avr-comp/avr/dtostrf.c.impl"
+
+#include <stdio.h>
+
+char *dtostrf (double val, signed char width, unsigned char prec, char *sout) {
+    asm(".global _printf_float");
+
+    char fmt[20];
+    sprintf(fmt, "%%%d.%df", width, prec);
+    sprintf(sout, fmt, val);
+    return sout;
+}
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/itoa.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/itoa.c
new file mode 100644
index 000000000..b302dc57c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/itoa.c
@@ -0,0 +1,133 @@
+/*
+  Copyright (c) 2014 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "itoa.h"
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef IMPL_ITOA
+// DCB: We need to keep the implementations of the functions in this file!
+// ltoa, itoa, etc. are not in the ANSI-C or C++ standards, so not 
+// all compilers support them. You may be able to replace these with 
+// standard versions in some cases, but they won't always work for everyone.
+
+char* ltoa( long value, char *string, int radix )
+{
+  char tmp[33];
+  char *tp = tmp;
+  long i;
+  unsigned long v;
+  int sign;
+  char *sp;
+
+  if ( string == NULL )
+  {
+    return 0 ;
+  }
+
+  if (radix > 36 || radix <= 1)
+  {
+    return 0 ;
+  }
+
+  sign = (radix == 10 && value < 0);
+  if (sign)
+  {
+    v = -value;
+  }
+  else
+  {
+    v = (unsigned long)value;
+  }
+
+  while (v || tp == tmp)
+  {
+    i = v % radix;
+    v = v / radix;
+    if (i < 10)
+      *tp++ = i+'0';
+    else
+      *tp++ = i + 'a' - 10;
+  }
+
+  sp = string;
+
+  if (sign)
+    *sp++ = '-';
+  while (tp > tmp)
+    *sp++ = *--tp;
+  *sp = 0;
+
+  return string;
+}
+
+char* ultoa( unsigned long value, char *string, int radix )
+{
+  char tmp[33];
+  char *tp = tmp;
+  long i;
+  unsigned long v = value;
+  char *sp;
+
+  if ( string == NULL )
+  {
+    return 0;
+  }
+
+  if (radix > 36 || radix <= 1)
+  {
+    return 0;
+  }
+
+  while (v || tp == tmp)
+  {
+    i = v % radix;
+    v = v / radix;
+    if (i < 10)
+      *tp++ = i+'0';
+    else
+      *tp++ = i + 'a' - 10;
+  }
+
+  sp = string;
+
+
+  while (tp > tmp)
+    *sp++ = *--tp;
+  *sp = 0;
+
+  return string;
+}
+
+char* itoa( int value, char *string, int radix )
+{
+  return ltoa( value, string, radix ) ;
+}
+
+char* utoa( unsigned int value, char *string, int radix )
+{
+  return ultoa( value, string, radix ) ;
+}
+#endif
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/itoa.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/itoa.h
new file mode 100644
index 000000000..d3a470c75
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/api/itoa.h
@@ -0,0 +1,50 @@
+/*
+    Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+// Standard C functions required in Arduino API
+// If these functions are not provided by the standard library, the
+// core should supply an implementation of them.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef IMPL_ITOA
+extern char *itoa(int value, char *string, int radix);
+extern char *ltoa(long value, char *string, int radix);
+extern char *utoa(unsigned value, char *string, int radix);
+extern char *ultoa(unsigned long value, char *string, int radix);
+
+#else
+
+#include "stdlib.h"
+extern char *ltoa(long value, char *string, int radix) {
+    return itoa((int)value, string, radix);
+}
+
+extern char *ultoa(unsigned long value, char *string, int radix) {
+    return utoa((unsigned)value, string, radix);
+}
+#endif
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/delay.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/delay.cpp
new file mode 100644
index 000000000..dcd0d988f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/delay.cpp
@@ -0,0 +1,56 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <Arduino.h>
+#include <sam.h>
+#include "Reset.h" // for tickReset()
+#include "SysTiming.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Tick Counter united by ms */
+static volatile uint32_t _ulTickCount = 0;
+
+unsigned long millis(void) {
+    return Milliseconds();
+}
+
+unsigned long micros(void) {
+    return Microseconds();
+}
+
+void delay(unsigned long ms) {
+    Delay_ms(ms);
+}
+
+void delayMicroseconds(unsigned int usec) {
+    Delay_us(usec);
+}
+
+void SysTick_DefaultHandler(void) {
+    // Increment tick count each ms
+    _ulTickCount++;
+    // See if USB Serial or others have caused a reset to bootloader cycle
+    tickReset();
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/delay.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/delay.h
new file mode 100644
index 000000000..234bce977
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/delay.h
@@ -0,0 +1,71 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _DELAY_
+#define _DELAY_
+
+#include <stdint.h>
+#include "variant.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Returns the number of milliseconds since the Arduino board began
+ * running the current program.
+ *
+ * This number will overflow (go back to zero), after approximately 50 days.
+ *
+ * \return Number of milliseconds since the program started (uint32_t)
+ */
+extern unsigned long millis(void) ;
+
+/**
+ * \brief Returns the number of microseconds since the Arduino board began
+ * running the current program.
+ *
+ * This number will overflow (go back to zero), after approximately 70 minutes.
+ *
+ * \note There are 1,000 microseconds in a millisecond and 1,000,000
+ * microseconds in a second.
+ */
+extern unsigned long micros(void) ;
+
+/**
+ * \brief Pauses the program for the amount of time (in milliseconds) specified
+ * as parameter.
+ * (There are 1000 milliseconds in a second.)
+ *
+ * \param dwMs the number of milliseconds to pause (uint32_t)
+ */
+extern void delay(unsigned long dwMs) ;
+
+/**
+ * \brief Pauses the program for the amount of time (in microseconds) specified
+ * as parameter.
+ *
+ * \param usec the number of microseconds to pause (uint32_t)
+ */
+extern void delayMicroseconds(unsigned int usec) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DELAY_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/hooks.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/hooks.c
new file mode 100644
index 000000000..c6237f639
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/hooks.c
@@ -0,0 +1,58 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/**
+ * Empty yield() hook.
+ *
+ * This function is intended to be used by library writers to build
+ * libraries or sketches that supports cooperative threads.
+ *
+ * Its defined as a weak symbol and it can be redefined to implement a
+ * real cooperative scheduler.
+ */
+static void __empty() {
+	// Empty
+}
+void yield(void) __attribute__ ((weak, alias("__empty")));
+
+/**
+ * SysTick hook
+ *
+ * This function is called from SysTick handler, before the default
+ * handler provided by Arduino.
+ */
+static int __false() {
+	// Return false
+	return 0;
+}
+int sysTickHook(void) __attribute__ ((weak, alias("__false")));
+
+/**
+ * SVC hook
+ * PendSV hook
+ *
+ * These functions are called from SVC handler, and PensSV handler.
+ * Default action is halting.
+ */
+static void __halt() {
+	// Halts
+	while (1)
+		;
+}
+void svcHook(void)    __attribute__ ((weak, alias("__halt")));
+void pendSVHook(void) __attribute__ ((weak, alias("__halt")));
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/main.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/main.cpp
new file mode 100644
index 000000000..d1f826d03
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/main.cpp
@@ -0,0 +1,68 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#define ARDUINO_MAIN
+#include "SysManager.h"
+#include "SerialDriver.h"
+#include "SerialUsb.h"
+#include "SysTiming.h"
+#include "sam.h"
+#include <Arduino.h>
+
+// Board resource controller
+namespace ClearCore {
+extern SysManager SysMgr;
+extern SerialUsb ConnectorUsb;
+extern SerialDriver ConnectorCOM0;
+extern SerialDriver ConnectorCOM1;
+}
+
+/*
+ * \brief Main entry point of Arduino application
+ */
+int main(void) {
+    // - - - - - - - - - - - - - - - - - - - - - -
+    // Perform C++ initializations before sketch
+    // - - - - - - - - - - - - - - - - - - - - - -
+    delay(1);
+    // Start sketch "setup"
+    setup();
+
+    for (;;) {
+        // sketch "loop"
+        loop();
+        if (serialEventRun) {
+            serialEventRun();
+        }
+    }
+
+    return 0;
+}
+
+/* Default Arduino systick handler */
+extern "C" int sysTickHook(void);
+extern "C" void SysTick_DefaultHandler(void);
+
+extern "C" void SysTick_Handler(void) __attribute__((weak));
+extern "C" void SysTick_Handler(void) {
+    ClearCore::SysMgr.SysTickUpdate();
+    if (sysTickHook()) {
+        return;
+    }
+    SysTick_DefaultHandler();
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/new.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/new.cpp
new file mode 100644
index 000000000..ab43a766d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/new.cpp
@@ -0,0 +1,36 @@
+/*
+  Copyright (c) 2014 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <stdlib.h>
+
+void *operator new (size_t size) {
+    return malloc(size);
+}
+
+void *operator new[](size_t size) {
+    return malloc(size);
+}
+
+void operator delete (void *ptr) {
+    free(ptr);
+}
+
+void operator delete[](void *ptr) {
+    free(ptr);
+}
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/startup_same53.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_analog.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_analog.cpp
new file mode 100644
index 000000000..835eee0b1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_analog.cpp
@@ -0,0 +1,29 @@
+/*
+    Copyright (c) 2014 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <ArduinoAPI.h>
+#include "Arduino.h"
+
+void analogWrite(pin_size_t ulPin, uint32_t ulVal, AnalogOutMode mode,
+                 AnalogOutputUnits units) {
+    analogWriteAPI(ulPin, (int)ulVal, mode, units);
+}
+
+int analogRead(pin_size_t ulPin, AnalogInputUnits units) {
+    return analogReadAPI(ulPin, units);
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_digital.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_digital.c
new file mode 100644
index 000000000..4b857b3c2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_digital.c
@@ -0,0 +1,37 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <ArduinoAPI.h>
+#include "WVariant.h"
+#include "Common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void digitalWrite(pin_size_t ulPin, uint32_t ulVal) {
+    digitalWriteClearCore(ulPin, (PinStatus)ulVal);
+}
+
+PinStatus digitalRead(pin_size_t ulPin) {
+    return digitalReadClearCore(ulPin);
+}
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_digital.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_digital.h
new file mode 100644
index 000000000..2b9e9d4f2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_digital.h
@@ -0,0 +1,21 @@
+/*
+    Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "variant.h"
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_shift.c b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_shift.c
new file mode 100644
index 000000000..749628636
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/cores/arduino/wiring_shift.c
@@ -0,0 +1,68 @@
+/*
+    Copyright (c) 2014 Arduino.  All right reserved.
+
+    This library is free software; you can redistribute it and/or
+    modify it under the terms of the GNU Lesser General Public
+    License as published by the Free Software Foundation; either
+    version 2.1 of the License, or (at your option) any later version.
+
+    This library is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+    See the GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public
+    License along with this library; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <ArduinoAPI.h>
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+uint8_t shiftIn(pin_size_t ulDataPin, 
+                pin_size_t ulClockPin, 
+                BitOrder ulBitOrder) {
+    uint8_t value = 0 ;
+    uint8_t i ;
+
+    for ( i=0 ; i < 8 ; ++i ) {
+        digitalWrite( ulClockPin, HIGH ) ;
+
+        if ( ulBitOrder == LSBFIRST ) {
+            value |= digitalRead( ulDataPin ) << i ;
+        }
+        else {
+            value |= digitalRead( ulDataPin ) << (7 - i) ;
+        }
+
+        digitalWrite( ulClockPin, LOW ) ;
+    }
+
+    return value ;
+}
+
+void shiftOut(pin_size_t ulDataPin, 
+              pin_size_t ulClockPin, 
+              BitOrder ulBitOrder, 
+              uint8_t ulVal) {
+    uint8_t i ;
+
+    for ( i=0 ; i < 8 ; i++ ) {
+        if ( ulBitOrder == LSBFIRST ) {
+            digitalWrite( ulDataPin, !!(ulVal & (1 << i)) ) ;
+        }
+        else {
+            digitalWrite( ulDataPin, !!(ulVal & (1 << (7 - i))) ) ;
+        }
+
+        digitalWrite( ulClockPin, HIGH ) ;
+        digitalWrite( ulClockPin, LOW ) ;
+    }
+}
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/drivers/TeknicClearCore.inf b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/drivers/TeknicClearCore.inf
new file mode 100644
index 000000000..3cfece80c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/drivers/TeknicClearCore.inf
@@ -0,0 +1,112 @@
+; Windows 2000, XP, Vista, 7 and 8 (x32 and x64) setup file for Atmel CDC Devices
+; Copyright (c) 2000-2013 ATMEL, Inc.
+
+[Version] 
+Signature   = "$Windows NT$" 
+Class       = Ports 
+ClassGuid   = {4D36E978-E325-11CE-BFC1-08002BE10318} 
+
+Provider    = %Manufacturer% 
+LayoutFile  = layout.inf 
+CatalogFile = teknicclearcore.cat
+DriverVer   = 01/09/2020,1.0.0.7
+
+;----------------------------------------------------------
+; Targets
+;----------------------------------------------------------
+[Manufacturer] 
+%Manufacturer%=DeviceList, NTAMD64, NTIA64, NT 
+
+[DeviceList]
+%TEK_CORE%	= DriverInstall, USB\VID_2890&PID_8022
+%TEK_BOOT%	= DriverInstall, USB\VID_2890&PID_0022&MI_00
+
+[DeviceList.NTAMD64]
+%TEK_CORE%	= DriverInstall, USB\VID_2890&PID_8022
+%TEK_BOOT%	= DriverInstall, USB\VID_2890&PID_0022&MI_00
+
+[DeviceList.NTIA64]
+%TEK_CORE%	= DriverInstall, USB\VID_2890&PID_8022
+%TEK_BOOT%	= DriverInstall, USB\VID_2890&PID_0022&MI_00
+
+[DeviceList.NT]
+%TEK_CORE%	= DriverInstall, USB\VID_2890&PID_8022
+%TEK_BOOT%	= DriverInstall, USB\VID_2890&PID_0022&MI_00
+
+;----------------------------------------------------------
+; Windows 2000, XP, Vista, Windows 7, Windows 8 - 32bit
+;----------------------------------------------------------
+[Reader_Install.NTx86] 
+
+
+[DestinationDirs] 
+DefaultDestDir=12 
+DriverInstall.NT.Copy=12 
+
+[DriverInstall.NT] 
+include=mdmcpq.inf
+CopyFiles=DriverInstall.NT.Copy 
+AddReg=DriverInstall.NT.AddReg 
+
+[DriverInstall.NT.Copy] 
+usbser.sys 
+
+[DriverInstall.NT.AddReg]
+HKR,,DevLoader,,*ntkern 
+HKR,,NTMPDriver,,usbser.sys 
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" 
+
+[DriverInstall.NT.Services] 
+AddService = usbser, 0x00000002, DriverService.NT 
+
+[DriverService.NT] 
+DisplayName = %Serial.SvcDesc% 
+ServiceType = 1 ; SERVICE_KERNEL_DRIVER 
+StartType = 3 ; SERVICE_DEMAND_START 
+ErrorControl = 1 ; SERVICE_ERROR_NORMAL 
+ServiceBinary = %12%\usbser.sys 
+LoadOrderGroup = Base 
+
+;----------------------------------------------------------
+; Windows XP, Vista, Windows 7, Windows 8 - 64bit
+;----------------------------------------------------------
+
+[DriverInstall.NTamd64]
+include=mdmcpq.inf
+CopyFiles=DriverCopyFiles.NTamd64
+AddReg=DriverInstall.NTamd64.AddReg
+
+[DriverCopyFiles.NTamd64]
+usbser.sys,,,0x20
+
+[DriverInstall.NTamd64.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[DriverInstall.NTamd64.Services]
+AddService=usbser, 0x00000002, DriverService.NTamd64
+
+[DriverService.NTamd64]
+DisplayName=%Serial.SvcDesc%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\usbser.sys
+
+;----------------------------------------------------------
+; String
+;----------------------------------------------------------
+
+[Strings] 
+Manufacturer = "Teknic, Inc."
+MFGFILENAME="TeknicClearCore"
+ManufacturerName="Teknic, Inc."
+INSTDISK="Teknic ClearCore USB Installer"
+DESCRIPTION="Teknic ClearCore Module"
+ServiceName="ClearCore USB Serial Emulation Driver"
+TEK_CORE="Teknic ClearCore"
+TEK_BOOT="Teknic ClearCore UF2 Bootloader"
+
+Serial.SvcDesc = "USB Serial emulation driver" 
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/drivers/teknicclearcore.cat b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/drivers/teknicclearcore.cat
new file mode 100644
index 000000000..05465bbc0
Binary files /dev/null and b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/drivers/teknicclearcore.cat differ
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/keywordify.py b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/keywordify.py
new file mode 100644
index 000000000..696dfaf0b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/keywordify.py
@@ -0,0 +1,284 @@
+# This script generates a keywords.txt file for the Arduino IDE by scraping 
+# through the codebase, and picking keywords using the following scheme
+# that seems to be widely accepted by the Arduino community:
+#
+# KEYWORD1 for Classes, Datatypes, and C++ keywords
+# KEYWORD2 for Methods and functions
+# LITERAL1 for constants
+#
+# Author: Cody Burrows
+# Date: 2019-07-08
+
+import argparse
+import datetime
+import os
+import re
+
+
+# path to the variants\clearcore\Teknic directory
+REL_PATH_TEKNIC = os.path.dirname(os.path.abspath(__file__)) + '\\Teknic\\libClearCore\\'
+# path to the pins_arduino header file
+REL_PATH_PINS_ARDUINO = os.path.dirname(os.path.abspath(__file__)) + '\\variants\\clearcore\\pins_arduino.h'
+# I love escaping escapes
+PATTERN_PUBLIC_FUNC = re.compile(r'(?!return|operator\b)\b[\w\*&]+ [\w]+\([^(){}]*\)? ?(override ?)?(;|{)?')
+PATTERN_PUBLIC_ENUM = re.compile('(typedef )?enum[^{}()]+{')
+PATTERN_ENUM_NAME = re.compile('[A-Z0-9_]+n?[A-Z0-9_]*( += (-)?(0x)?([0-9 <>UL]+|[A-Z0-9_]+n?[A-Z0-9_]*)( [+-] [0-9]+)?)?' + 
+                               '((,)?(\s*)\n|(,)?(\s*)//((\s*)(\S*)(\s*))*\n)')        
+                               # AL 9-24-2019 updated PATTERN_ENUM_NAME to allow inline comments after an enum,
+                               # (\s*) allows optionally any amount of whitespace.
+PATTERN_DEFINE_DIRECTIVE = re.compile('(#define)(\s*)[A-Z0-9_]*(\s*)(\w|\W)+')
+PATTERN_GLOBAL_INSTANCE = re.compile(r'extern [A-Za-z][&A-Za-z0-9]* *&? *(\*const )?(?P<name>[A-Za-z][A-Za-z0-9]*);')
+
+# relative path of keywords.txt file
+keywords = "keywords.txt"
+
+# Argument setup
+parser = argparse.ArgumentParser(description='Generate keywords.txt from the ClearCore source files.')
+parser.add_argument('-S', action='store_true', help='silent mode, no permission request to remove the file')
+parser.add_argument('-p', action='store', dest="p", default="", help="relative path to the keywords.txt file")
+
+# print error and die
+def error(errString):
+    print('Error: ' + errString)
+    exit()
+
+
+# Prompt user for y/n
+def confirmYN(msg):
+    ans = str(input(msg + '  (y/n) ')).lower().strip()
+    return ans[0] == 'y'
+    
+        
+# write a line out to the keywords.txt file
+def writeline(f, line):
+    f.write(line + '\n')
+
+
+# find all public functions in the given file
+def publicFunctions(f):
+    public = False
+    inComment = False
+    matches = set()
+    openedFile = open(f, 'r')
+    for line in openedFile:
+        if 'public:' in line:
+            public = True
+        elif 'protected:' in line:
+            public = False
+        elif 'private:' in line:
+            public = False
+
+        if public:
+            # Detect beginning of a multi-line comment.
+            if not inComment:
+                if '/*' in line:
+                    inComment = True
+            # Detect end of a multi-line comment.
+            if inComment:
+                if '*/' in line:
+                    inComment = False
+                    
+            x = re.search(PATTERN_PUBLIC_FUNC, line)
+            # "Match objects always have a boolean value of True" https://docs.python.org/2/library/re.html
+            if x and not inComment:
+                wholeMatch = x.string[x.start():x.end()]
+                name = wholeMatch.split('(')[0] # gets func name with return ty
+                name = name.split(' ')[1] # gets rid of return type
+                matches.add(name)
+                #print('\tFound: ' + name)
+            
+    openedFile.close()
+    return matches
+
+
+# find all of the enum names in the given file
+def publicEnums(f):
+    public = False
+    inEnum = False
+    inComment = False
+    matches = set()
+    openedFile = open(f, 'r')
+    for line in openedFile:
+        if 'public:' in line:
+            public = True
+            inEnum = False
+        elif 'protected:' in line:
+            public = False
+            inEnum = False
+        elif 'private:' in line:
+            public = False
+            inEnum = False
+
+        if public:
+            if inEnum:
+                # Detect beginning of a multi-line comment.
+                if not inComment:
+                    if '/*' in line:
+                        inComment = True
+                # Detect end of a multi-line comment.
+                if inComment:
+                    if '*/' in line:
+                        inComment = False
+                # Detect end of an enum.
+                if '}' in line:
+                    inEnum = False
+            else:
+                inEnum = re.search(PATTERN_PUBLIC_ENUM, line) is not None
+
+            if inEnum and not inComment:
+                x = re.search(PATTERN_ENUM_NAME, line)
+                if x:
+                    wholeMatch = x.string[x.start():x.end()]
+                    if '=' in wholeMatch:
+                        name = wholeMatch.split('=')[0].strip()
+                    elif ',' in wholeMatch:
+                        name = wholeMatch.split(',')[0].strip()
+                    else:
+                        name = wholeMatch.split(' ')[0].strip()
+                    #print(f'Match: {wholeMatch}')
+                    #print(f'Found: {name}')
+                    matches.add(name)
+            
+    openedFile.close()
+    return matches
+
+# find all #defines and declare the first two values as literals
+# ex:       #define IO3 CLEARCORE_PIN_IO3  -> declare IO3 and CLEARCORE_PIN_IO3
+def pinDefines(f):
+    define = False
+    matches = set()
+    with open(f) as fp:
+        for line in fp:
+            if PATTERN_DEFINE_DIRECTIVE.match(line):
+                # this is a hack for pins_arduino.h and not how a standard 
+                # define would be handled
+                pinDirective = line.split()[1].strip()
+                pinEnum = line.split()[2].strip()
+                #print('\tFound: ' + pinDirective)
+                matches.add(pinDirective)
+                #print('\tFound: ' + pinEnum)
+                matches.add(pinEnum)
+    return matches
+
+# find global connector instances
+def globalInstances(f):
+    matches = set()
+    with open(f) as fp:
+        for line in fp:
+            if PATTERN_GLOBAL_INSTANCE.match(line):
+                global_instance = PATTERN_GLOBAL_INSTANCE.match(line).group('name')
+                matches.add(global_instance)
+    return matches
+            
+
+# start "running" the script
+print('Running keywordify ' + datetime.date.today().strftime("%Y-%m-%d"))
+
+# parse arguments
+args = parser.parse_args()
+
+# make sure we're starting in the right directory
+inc_found = os.path.exists(REL_PATH_TEKNIC + 'inc')
+src_found = os.path.exists(REL_PATH_TEKNIC + 'src')
+pins_h_found = os.path.exists(REL_PATH_PINS_ARDUINO)
+if not inc_found:
+    error('Couldn\'t find ' + REL_PATH_TEKNIC + 'inc!')
+elif not src_found:
+    error('Couldn\'t find ' + REL_PATH_TEKNIC + 'src!')
+elif not pins_h_found:
+    error("Couldn't find " + REL_PATH_PINS_ARDUINO + "!")
+else:
+    print('Found ' + REL_PATH_TEKNIC + 'inc and\n' + REL_PATH_TEKNIC + 'src\n')
+
+# update the keywords.txt path with an optionally specified location
+keywords = args.p + keywords
+
+# check to see if keywords.txt already exists
+if os.path.exists(keywords):
+    # the '-S' flag indicates silence, don't ask
+    if not args.S:
+        if not confirmYN('keywords.txt already exists. Overwrite?'):
+           exit()
+    os.remove(keywords)
+
+# fall through to start scraping
+keyword1s = set()
+keyword2s = set()
+literal1s = set()
+REL_PATH_INC = REL_PATH_TEKNIC + 'inc'
+REL_PATH_SRC = REL_PATH_TEKNIC + 'src'
+
+# get all of the classes in ...\Teknic\src (KEYWORD1)
+print('Searching for Classes...')
+for (_, _, f) in os.walk(REL_PATH_SRC):
+    for filename in f:
+        if filename.endswith('.cpp'):
+            name = os.path.splitext(filename)[0]
+            #print('\tFound: ' + name)
+            keyword1s.add(name)
+
+# add in Serial0
+keyword1s.add("Serial0")
+
+# get all of the global connector instances (KEYWORD1)
+print('Searching for global instances...')
+for (_,_,f) in os.walk(REL_PATH_INC):
+    for filename in f:
+        if filename == "ClearCore.h":
+            keyword1s = keyword1s.union(globalInstances(REL_PATH_INC + '\\' + filename))
+
+# get all of the public functions (KEYWORD2)
+print('Searching for public functions...')
+for(_, _, f) in os.walk(REL_PATH_INC):
+    for filename in f:
+        if filename.endswith('.h'):
+            #print('\nLooking at file: ' + filename + '\n')
+            keyword2s = keyword2s.union(publicFunctions(REL_PATH_INC + 
+                                        '\\' + filename))
+
+# get all of the constants (LITERAL1)
+print('Searching for constants...')
+for(_, _, f) in os.walk(REL_PATH_INC):
+    for filename in f:
+        if filename.endswith('.h'):
+            #print('\nLooking at file: ' + filename + '\n')
+            literal1s = literal1s.union(publicEnums(REL_PATH_INC + 
+                                        '\\' + filename))
+
+# get all of the pin mappings (LITERAL1)
+print('Looking at pin mapping...')
+literal1s = literal1s.union(pinDefines(REL_PATH_PINS_ARDUINO))
+
+
+# done collecting names
+# write out to file
+# write a timestamp to the file
+keywords_txt = open(keywords, 'w+')
+timestamp = datetime.datetime.now()
+
+# write out KEYWORD1 entries
+writeline(keywords_txt, '# Classes, Datatypes, and C++ keywords')
+# sort alphabetically
+keyword1sSorted = sorted(keyword1s)
+for fname in keyword1sSorted:
+    writeline(keywords_txt, fname + '\t' + 'KEYWORD1')
+
+# write out KEYWORD2 entries
+keyword2s = keyword2s - keyword1s
+# sort alphabetically
+keyword2sSorted = sorted(keyword2s)
+writeline(keywords_txt, '\n# Public methods and functions')
+for fname in keyword2sSorted:
+    writeline(keywords_txt, fname + '\t' + 'KEYWORD2')
+
+# write out LITERAL1 entries (sorted alphabetically)
+literal1s = literal1s - keyword2s - keyword1s
+# sort alphabetically
+literal1sSorted = sorted(literal1s)
+writeline(keywords_txt, '\n# Public Constants')
+for fname in literal1sSorted:
+    writeline(keywords_txt, fname + '\t' + 'LITERAL1')
+
+writeline(keywords_txt, '\n# keywordify done')
+keywords_txt.close()
+print('keywordify done.')
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/keywords.txt b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/keywords.txt
new file mode 100644
index 000000000..44d5c9871
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/keywords.txt
@@ -0,0 +1,661 @@
+# Classes, Datatypes, and C++ keywords
+AdcManager	KEYWORD1
+AdcMgr	KEYWORD1
+BlinkCodeDriver	KEYWORD1
+CcioBoardManager	KEYWORD1
+CcioMgr	KEYWORD1
+CcioPin	KEYWORD1
+ConnectorA10	KEYWORD1
+ConnectorA11	KEYWORD1
+ConnectorA12	KEYWORD1
+ConnectorA9	KEYWORD1
+ConnectorCOM0	KEYWORD1
+ConnectorCOM1	KEYWORD1
+ConnectorDI6	KEYWORD1
+ConnectorDI7	KEYWORD1
+ConnectorDI8	KEYWORD1
+ConnectorIO0	KEYWORD1
+ConnectorIO1	KEYWORD1
+ConnectorIO2	KEYWORD1
+ConnectorIO3	KEYWORD1
+ConnectorIO4	KEYWORD1
+ConnectorIO5	KEYWORD1
+ConnectorLed	KEYWORD1
+ConnectorM0	KEYWORD1
+ConnectorM1	KEYWORD1
+ConnectorM2	KEYWORD1
+ConnectorM3	KEYWORD1
+ConnectorUsb	KEYWORD1
+DigitalIn	KEYWORD1
+DigitalInAnalogIn	KEYWORD1
+DigitalInOut	KEYWORD1
+DigitalInOutAnalogOut	KEYWORD1
+DigitalInOutHBridge	KEYWORD1
+DmaManager	KEYWORD1
+EncoderIn	KEYWORD1
+EncoderInput	KEYWORD1
+EthernetManager	KEYWORD1
+EthernetMgr	KEYWORD1
+EthernetTcp	KEYWORD1
+EthernetTcpClient	KEYWORD1
+EthernetTcpServer	KEYWORD1
+EthernetUdp	KEYWORD1
+EthernetUtils	KEYWORD1
+InputManager	KEYWORD1
+InputMgr	KEYWORD1
+LedDriver	KEYWORD1
+MotorDriver	KEYWORD1
+MotorManager	KEYWORD1
+MotorMgr	KEYWORD1
+NvmManager	KEYWORD1
+SdCard	KEYWORD1
+SdCardDriver	KEYWORD1
+Serial0	KEYWORD1
+SerialBase	KEYWORD1
+SerialDriver	KEYWORD1
+SerialUsb	KEYWORD1
+ShiftRegister	KEYWORD1
+StatusManager	KEYWORD1
+StatusMgr	KEYWORD1
+StepGenerator	KEYWORD1
+SysManager	KEYWORD1
+SysMgr	KEYWORD1
+SysTiming	KEYWORD1
+TimingMgr	KEYWORD1
+UsbManager	KEYWORD1
+XBee	KEYWORD1
+XBeeDriver	KEYWORD1
+
+# Public methods and functions
+AccelMax	KEYWORD2
+Accept	KEYWORD2
+AdcIsInTimeout	KEYWORD2
+AdcResolution	KEYWORD2
+AdcTimeoutLimit	KEYWORD2
+AddToPosition	KEYWORD2
+AnalogVoltage	KEYWORD2
+AnalogWrite	KEYWORD2
+AnalogWriteUncalibrated	KEYWORD2
+Available	KEYWORD2
+AvailableForRead	KEYWORD2
+AvailableForWrite	KEYWORD2
+Begin	KEYWORD2
+BlinkCode	KEYWORD2
+BlinkCodeClear	KEYWORD2
+BlockRead	KEYWORD2
+BlockWrite	KEYWORD2
+BrakeOutput	KEYWORD2
+Byte	KEYWORD2
+BytesAvailable	KEYWORD2
+CcioDiscover	KEYWORD2
+CcioRediscoverEnable	KEYWORD2
+CharGet	KEYWORD2
+CharPeek	KEYWORD2
+CharSize	KEYWORD2
+CheckTravelLimits	KEYWORD2
+ClearAlerts	KEYWORD2
+ClearFaults	KEYWORD2
+ClearFaultsActive	KEYWORD2
+ClearQuadratureError	KEYWORD2
+Close	KEYWORD2
+CodePresent	KEYWORD2
+Connect	KEYWORD2
+Connected	KEYWORD2
+ConnectionTimeout	KEYWORD2
+ConnectorIndex	KEYWORD2
+CruiseVelocityReached	KEYWORD2
+CtsState	KEYWORD2
+DacStoreCalibration	KEYWORD2
+DataOrder	KEYWORD2
+DhcpBegin	KEYWORD2
+DiagnosticLedSweep	KEYWORD2
+DnsIp	KEYWORD2
+EIC_Handler	KEYWORD2
+EStopConnector	KEYWORD2
+EStopDecelMax	KEYWORD2
+Enable	KEYWORD2
+EnableActiveLevel	KEYWORD2
+EnableConnector	KEYWORD2
+EnableRequest	KEYWORD2
+EnableTriggerPulse	KEYWORD2
+End	KEYWORD2
+ErrorStatusAccum	KEYWORD2
+ExternalInterrupt	KEYWORD2
+FastUpdate	KEYWORD2
+FilterLength	KEYWORD2
+FilterReset	KEYWORD2
+FilterTc	KEYWORD2
+Filter_ms	KEYWORD2
+FinishNvmWrite	KEYWORD2
+FlowControl	KEYWORD2
+Flush	KEYWORD2
+FlushInput	KEYWORD2
+GatewayIp	KEYWORD2
+GetIsrLoading	KEYWORD2
+HBridgeReset	KEYWORD2
+HBridgeState	KEYWORD2
+HandleFrameError	KEYWORD2
+HandleOverflow	KEYWORD2
+HandleParityError	KEYWORD2
+HlfbActiveLevel	KEYWORD2
+HlfbCarrier	KEYWORD2
+HlfbFilterLength	KEYWORD2
+HlfbHasFallen	KEYWORD2
+HlfbHasRisen	KEYWORD2
+HlfbInputStatus	KEYWORD2
+HlfbMode	KEYWORD2
+HwPosition	KEYWORD2
+IndexDetected	KEYWORD2
+IndexInverted	KEYWORD2
+IndexPosition	KEYWORD2
+Initialize	KEYWORD2
+InputAConnector	KEYWORD2
+InputBConnector	KEYWORD2
+InputFallen	KEYWORD2
+InputRegMask	KEYWORD2
+InputRisen	KEYWORD2
+InputsFallen	KEYWORD2
+InputsRT	KEYWORD2
+InputsRisen	KEYWORD2
+Int16	KEYWORD2
+Int32	KEYWORD2
+Int64	KEYWORD2
+InterruptEnable	KEYWORD2
+InterruptHandlerSet	KEYWORD2
+InterruptsEnabled	KEYWORD2
+IoOverloadAccum	KEYWORD2
+IoOverloadRT	KEYWORD2
+IoOverloadSinceStartupAccum	KEYWORD2
+IpAddress	KEYWORD2
+IrqHandler1	KEYWORD2
+IrqHandlerException	KEYWORD2
+IrqHandlerGmac	KEYWORD2
+IrqHandlerPhy	KEYWORD2
+IrqHandlerRx	KEYWORD2
+IrqHandlerTx	KEYWORD2
+IsInFault	KEYWORD2
+IsInHwFault	KEYWORD2
+IsValidInputPin	KEYWORD2
+IsValidOutputPin	KEYWORD2
+IsWritable	KEYWORD2
+LastOutput	KEYWORD2
+LimitSwitchNeg	KEYWORD2
+LimitSwitchPos	KEYWORD2
+LinkClose	KEYWORD2
+LocalIp	KEYWORD2
+LocalPort	KEYWORD2
+MacAddress	KEYWORD2
+Microseconds	KEYWORD2
+Mode	KEYWORD2
+MotorInACount	KEYWORD2
+MotorInADuty	KEYWORD2
+MotorInAState	KEYWORD2
+MotorInBCount	KEYWORD2
+MotorInBDuty	KEYWORD2
+MotorInBState	KEYWORD2
+MotorInputClocking	KEYWORD2
+MotorModeSet	KEYWORD2
+Move	KEYWORD2
+MoveStopAbrupt	KEYWORD2
+MoveStopDecel	KEYWORD2
+MoveVelocity	KEYWORD2
+NegLimitActive	KEYWORD2
+NetmaskIp	KEYWORD2
+OutputCurrent	KEYWORD2
+OutputDirection	KEYWORD2
+OutputPulsesStart	KEYWORD2
+OutputPulsesStop	KEYWORD2
+PacketFlush	KEYWORD2
+PacketParse	KEYWORD2
+PacketRead	KEYWORD2
+PacketSend	KEYWORD2
+PacketWrite	KEYWORD2
+Parity	KEYWORD2
+Peek	KEYWORD2
+PhyInitialize	KEYWORD2
+PhyRead	KEYWORD2
+PhyShift	KEYWORD2
+PhyWrite	KEYWORD2
+PinState	KEYWORD2
+PolarityInvertSDDirection	KEYWORD2
+PolarityInvertSDEnable	KEYWORD2
+PolarityInvertSDHlfb	KEYWORD2
+PortClose	KEYWORD2
+PortIsOpen	KEYWORD2
+PortMode	KEYWORD2
+PortOpen	KEYWORD2
+PosLimitActive	KEYWORD2
+Position	KEYWORD2
+PositionRefSet	KEYWORD2
+PwmDuty	KEYWORD2
+QuadratureError	KEYWORD2
+Read	KEYWORD2
+Ready	KEYWORD2
+ReceivedFrameFlag	KEYWORD2
+Refresh	KEYWORD2
+RefreshRate	KEYWORD2
+Reinitialize	KEYWORD2
+RemoteIp	KEYWORD2
+RemotePort	KEYWORD2
+Reset	KEYWORD2
+ResetBoard	KEYWORD2
+ResetMicroseconds	KEYWORD2
+ResetMilliseconds	KEYWORD2
+RetransmissionCount	KEYWORD2
+RetransmissionTimeout	KEYWORD2
+RtsMode	KEYWORD2
+Send	KEYWORD2
+SendChar	KEYWORD2
+SendLine	KEYWORD2
+SerialBreak	KEYWORD2
+SerialNumber	KEYWORD2
+SetErrorCode	KEYWORD2
+Setup	KEYWORD2
+ShifterStateClear	KEYWORD2
+ShifterStateSet	KEYWORD2
+SinceStartupAccum	KEYWORD2
+Speed	KEYWORD2
+SpiAsyncWaitComplete	KEYWORD2
+SpiClock	KEYWORD2
+SpiSsMode	KEYWORD2
+SpiTransferData	KEYWORD2
+SpiTransferDataAsync	KEYWORD2
+State	KEYWORD2
+StateRT	KEYWORD2
+StatusAccum	KEYWORD2
+StatusFallen	KEYWORD2
+StatusRT	KEYWORD2
+StatusRegFallen	KEYWORD2
+StatusRegRisen	KEYWORD2
+StatusRisen	KEYWORD2
+StepsCalculated	KEYWORD2
+StepsComplete	KEYWORD2
+StepsLastSample	KEYWORD2
+StepsPrevious	KEYWORD2
+StopBits	KEYWORD2
+SwapDirection	KEYWORD2
+Synchonized	KEYWORD2
+SysTickPeriodMicroSec	KEYWORD2
+SysTickUpdate	KEYWORD2
+Tc	KEYWORD2
+TcSamples	KEYWORD2
+Tc_ms	KEYWORD2
+ToneAmplitude	KEYWORD2
+ToneContinuous	KEYWORD2
+TonePeriodic	KEYWORD2
+ToneStop	KEYWORD2
+ToneTimed	KEYWORD2
+ToneUpdate	KEYWORD2
+Type	KEYWORD2
+Update	KEYWORD2
+UpdateBegin	KEYWORD2
+UpdateEnd	KEYWORD2
+UserBlinkCode	KEYWORD2
+ValidateMove	KEYWORD2
+VelMax	KEYWORD2
+Velocity	KEYWORD2
+VelocityRefCommanded	KEYWORD2
+WaitForTransmitIdle	KEYWORD2
+WaitForWriteFinish	KEYWORD2
+
+# Public Constants
+A10	LITERAL1
+A11	LITERAL1
+A12	LITERAL1
+A9	LITERAL1
+ADC_5VOB_MON	LITERAL1
+ADC_AIN09	LITERAL1
+ADC_AIN10	LITERAL1
+ADC_AIN11	LITERAL1
+ADC_AIN12	LITERAL1
+ADC_CHANNEL_COUNT	LITERAL1
+ADC_SDRVR2_IMON	LITERAL1
+ADC_SDRVR3_IMON	LITERAL1
+ADC_VSUPPLY_MON	LITERAL1
+ANALOG_IN_DIGITAL_IN_TYPE	LITERAL1
+ANALOG_OUT_DIGITAL_IN_OUT_TYPE	LITERAL1
+BLINK_GROUP_APPLICATION	LITERAL1
+BLINK_GROUP_CCIO_OVERLOAD	LITERAL1
+BLINK_GROUP_DEVICE_ERROR	LITERAL1
+BLINK_GROUP_IO_OVERLOAD	LITERAL1
+BLINK_GROUP_MAX	LITERAL1
+BLINK_GROUP_SUPPLY_ERROR	LITERAL1
+CCIO	LITERAL1
+CCIOA0	LITERAL1
+CCIOA1	LITERAL1
+CCIOA2	LITERAL1
+CCIOA3	LITERAL1
+CCIOA4	LITERAL1
+CCIOA5	LITERAL1
+CCIOA6	LITERAL1
+CCIOA7	LITERAL1
+CCIOB0	LITERAL1
+CCIOB1	LITERAL1
+CCIOB2	LITERAL1
+CCIOB3	LITERAL1
+CCIOB4	LITERAL1
+CCIOB5	LITERAL1
+CCIOB6	LITERAL1
+CCIOB7	LITERAL1
+CCIOC0	LITERAL1
+CCIOC1	LITERAL1
+CCIOC2	LITERAL1
+CCIOC3	LITERAL1
+CCIOC4	LITERAL1
+CCIOC5	LITERAL1
+CCIOC6	LITERAL1
+CCIOC7	LITERAL1
+CCIOD0	LITERAL1
+CCIOD1	LITERAL1
+CCIOD2	LITERAL1
+CCIOD3	LITERAL1
+CCIOD4	LITERAL1
+CCIOD5	LITERAL1
+CCIOD6	LITERAL1
+CCIOD7	LITERAL1
+CCIOE0	LITERAL1
+CCIOE1	LITERAL1
+CCIOE2	LITERAL1
+CCIOE3	LITERAL1
+CCIOE4	LITERAL1
+CCIOE5	LITERAL1
+CCIOE6	LITERAL1
+CCIOE7	LITERAL1
+CCIOF0	LITERAL1
+CCIOF1	LITERAL1
+CCIOF2	LITERAL1
+CCIOF3	LITERAL1
+CCIOF4	LITERAL1
+CCIOF5	LITERAL1
+CCIOF6	LITERAL1
+CCIOF7	LITERAL1
+CCIOG0	LITERAL1
+CCIOG1	LITERAL1
+CCIOG2	LITERAL1
+CCIOG3	LITERAL1
+CCIOG4	LITERAL1
+CCIOG5	LITERAL1
+CCIOG6	LITERAL1
+CCIOG7	LITERAL1
+CCIOH0	LITERAL1
+CCIOH1	LITERAL1
+CCIOH2	LITERAL1
+CCIOH3	LITERAL1
+CCIOH4	LITERAL1
+CCIOH5	LITERAL1
+CCIOH6	LITERAL1
+CCIOH7	LITERAL1
+CCIO_DIGITAL_IN_OUT_TYPE	LITERAL1
+CCIO_OVERLOAD_BOARD0	LITERAL1
+CCIO_OVERLOAD_BOARD1	LITERAL1
+CCIO_OVERLOAD_BOARD2	LITERAL1
+CCIO_OVERLOAD_BOARD3	LITERAL1
+CCIO_OVERLOAD_BOARD4	LITERAL1
+CCIO_OVERLOAD_BOARD5	LITERAL1
+CCIO_OVERLOAD_BOARD6	LITERAL1
+CCIO_OVERLOAD_BOARD7	LITERAL1
+CCIO_OVERLOAD_NONE	LITERAL1
+CHANGE	LITERAL1
+CLEARCORE_PIN_A10	LITERAL1
+CLEARCORE_PIN_A11	LITERAL1
+CLEARCORE_PIN_A12	LITERAL1
+CLEARCORE_PIN_A9	LITERAL1
+CLEARCORE_PIN_CCIOA0	LITERAL1
+CLEARCORE_PIN_CCIOA1	LITERAL1
+CLEARCORE_PIN_CCIOA2	LITERAL1
+CLEARCORE_PIN_CCIOA3	LITERAL1
+CLEARCORE_PIN_CCIOA4	LITERAL1
+CLEARCORE_PIN_CCIOA5	LITERAL1
+CLEARCORE_PIN_CCIOA6	LITERAL1
+CLEARCORE_PIN_CCIOA7	LITERAL1
+CLEARCORE_PIN_CCIOB0	LITERAL1
+CLEARCORE_PIN_CCIOB1	LITERAL1
+CLEARCORE_PIN_CCIOB2	LITERAL1
+CLEARCORE_PIN_CCIOB3	LITERAL1
+CLEARCORE_PIN_CCIOB4	LITERAL1
+CLEARCORE_PIN_CCIOB5	LITERAL1
+CLEARCORE_PIN_CCIOB6	LITERAL1
+CLEARCORE_PIN_CCIOB7	LITERAL1
+CLEARCORE_PIN_CCIOC0	LITERAL1
+CLEARCORE_PIN_CCIOC1	LITERAL1
+CLEARCORE_PIN_CCIOC2	LITERAL1
+CLEARCORE_PIN_CCIOC3	LITERAL1
+CLEARCORE_PIN_CCIOC4	LITERAL1
+CLEARCORE_PIN_CCIOC5	LITERAL1
+CLEARCORE_PIN_CCIOC6	LITERAL1
+CLEARCORE_PIN_CCIOC7	LITERAL1
+CLEARCORE_PIN_CCIOD0	LITERAL1
+CLEARCORE_PIN_CCIOD1	LITERAL1
+CLEARCORE_PIN_CCIOD2	LITERAL1
+CLEARCORE_PIN_CCIOD3	LITERAL1
+CLEARCORE_PIN_CCIOD4	LITERAL1
+CLEARCORE_PIN_CCIOD5	LITERAL1
+CLEARCORE_PIN_CCIOD6	LITERAL1
+CLEARCORE_PIN_CCIOD7	LITERAL1
+CLEARCORE_PIN_CCIOE0	LITERAL1
+CLEARCORE_PIN_CCIOE1	LITERAL1
+CLEARCORE_PIN_CCIOE2	LITERAL1
+CLEARCORE_PIN_CCIOE3	LITERAL1
+CLEARCORE_PIN_CCIOE4	LITERAL1
+CLEARCORE_PIN_CCIOE5	LITERAL1
+CLEARCORE_PIN_CCIOE6	LITERAL1
+CLEARCORE_PIN_CCIOE7	LITERAL1
+CLEARCORE_PIN_CCIOF0	LITERAL1
+CLEARCORE_PIN_CCIOF1	LITERAL1
+CLEARCORE_PIN_CCIOF2	LITERAL1
+CLEARCORE_PIN_CCIOF3	LITERAL1
+CLEARCORE_PIN_CCIOF4	LITERAL1
+CLEARCORE_PIN_CCIOF5	LITERAL1
+CLEARCORE_PIN_CCIOF6	LITERAL1
+CLEARCORE_PIN_CCIOF7	LITERAL1
+CLEARCORE_PIN_CCIOG0	LITERAL1
+CLEARCORE_PIN_CCIOG1	LITERAL1
+CLEARCORE_PIN_CCIOG2	LITERAL1
+CLEARCORE_PIN_CCIOG3	LITERAL1
+CLEARCORE_PIN_CCIOG4	LITERAL1
+CLEARCORE_PIN_CCIOG5	LITERAL1
+CLEARCORE_PIN_CCIOG6	LITERAL1
+CLEARCORE_PIN_CCIOG7	LITERAL1
+CLEARCORE_PIN_CCIOH0	LITERAL1
+CLEARCORE_PIN_CCIOH1	LITERAL1
+CLEARCORE_PIN_CCIOH2	LITERAL1
+CLEARCORE_PIN_CCIOH3	LITERAL1
+CLEARCORE_PIN_CCIOH4	LITERAL1
+CLEARCORE_PIN_CCIOH5	LITERAL1
+CLEARCORE_PIN_CCIOH6	LITERAL1
+CLEARCORE_PIN_CCIOH7	LITERAL1
+CLEARCORE_PIN_DI6	LITERAL1
+CLEARCORE_PIN_DI7	LITERAL1
+CLEARCORE_PIN_DI8	LITERAL1
+CLEARCORE_PIN_INVALID	LITERAL1
+CLEARCORE_PIN_IO0	LITERAL1
+CLEARCORE_PIN_IO1	LITERAL1
+CLEARCORE_PIN_IO2	LITERAL1
+CLEARCORE_PIN_IO3	LITERAL1
+CLEARCORE_PIN_IO4	LITERAL1
+CLEARCORE_PIN_IO5	LITERAL1
+CLEARCORE_PIN_M0	LITERAL1
+CLEARCORE_PIN_M0_INA	LITERAL1
+CLEARCORE_PIN_M0_INB	LITERAL1
+CLEARCORE_PIN_M1	LITERAL1
+CLEARCORE_PIN_M1_INA	LITERAL1
+CLEARCORE_PIN_M1_INB	LITERAL1
+CLEARCORE_PIN_M2	LITERAL1
+CLEARCORE_PIN_M2_INA	LITERAL1
+CLEARCORE_PIN_M2_INB	LITERAL1
+CLEARCORE_PIN_M3	LITERAL1
+CLEARCORE_PIN_M3_INA	LITERAL1
+CLEARCORE_PIN_M3_INB	LITERAL1
+CLOCK_RATE_HIGH	LITERAL1
+CLOCK_RATE_LOW	LITERAL1
+CLOCK_RATE_NORMAL	LITERAL1
+COM_LSB_FIRST	LITERAL1
+COM_MSB_FIRST	LITERAL1
+CPM_MODE_A_DIRECT_B_DIRECT	LITERAL1
+CPM_MODE_A_DIRECT_B_PWM	LITERAL1
+CPM_MODE_A_PWM_B_PWM	LITERAL1
+CPM_MODE_STEP_AND_DIR	LITERAL1
+CPM_TYPE	LITERAL1
+DEVICE_ERROR_CCIO	LITERAL1
+DEVICE_ERROR_ETHERNET	LITERAL1
+DEVICE_ERROR_HBRIDGE	LITERAL1
+DEVICE_ERROR_NONE	LITERAL1
+DEVICE_ERROR_SD_CARD	LITERAL1
+DEVICE_ERROR_XBEE	LITERAL1
+DI6	LITERAL1
+DI7	LITERAL1
+DI8	LITERAL1
+DIGITAL_IN_OUT_TYPE	LITERAL1
+DIGITAL_IN_TYPE	LITERAL1
+FALLING	LITERAL1
+FILTER_UNIT_MS	LITERAL1
+FILTER_UNIT_RAW	LITERAL1
+FILTER_UNIT_SAMPLES	LITERAL1
+HIGH	LITERAL1
+HLFB_ASSERTED	LITERAL1
+HLFB_CARRIER_45_HZ	LITERAL1
+HLFB_CARRIER_482_HZ	LITERAL1
+HLFB_DEASSERTED	LITERAL1
+HLFB_HAS_MEASUREMENT	LITERAL1
+HLFB_MODE_HAS_BIPOLAR_PWM	LITERAL1
+HLFB_MODE_HAS_PWM	LITERAL1
+HLFB_MODE_STATIC	LITERAL1
+HLFB_UNKNOWN	LITERAL1
+H_BRIDGE_TYPE	LITERAL1
+INPUT_ANALOG	LITERAL1
+INPUT_DIGITAL	LITERAL1
+INVALID_NONE	LITERAL1
+IO0	LITERAL1
+IO1	LITERAL1
+IO2	LITERAL1
+IO3	LITERAL1
+IO4	LITERAL1
+IO5	LITERAL1
+LEAD_CHANGE	LITERAL1
+LEAD_SAMPLE	LITERAL1
+LED_BLINK_BREATHING	LITERAL1
+LED_BLINK_CCIO_COMM_ERR	LITERAL1
+LED_BLINK_CCIO_ONLINE	LITERAL1
+LED_BLINK_CODE_MAX	LITERAL1
+LED_BLINK_FADE	LITERAL1
+LED_BLINK_FAST_STROBE	LITERAL1
+LED_BLINK_IO_SET	LITERAL1
+LED_BLINK_OVERLOAD	LITERAL1
+LED_BLINK_PWM	LITERAL1
+LINE_HW	LITERAL1
+LINE_OFF	LITERAL1
+LINE_ON	LITERAL1
+LOW	LITERAL1
+M0	LITERAL1
+M0_INA	LITERAL1
+M0_INB	LITERAL1
+M1	LITERAL1
+M1_INA	LITERAL1
+M1_INB	LITERAL1
+M2	LITERAL1
+M2_INA	LITERAL1
+M2_INB	LITERAL1
+M3	LITERAL1
+M3_INA	LITERAL1
+M3_INB	LITERAL1
+MISO	LITERAL1
+MOSI	LITERAL1
+MOTOR_ALL	LITERAL1
+MOTOR_DISABLED	LITERAL1
+MOTOR_ENABLING	LITERAL1
+MOTOR_FAULTED	LITERAL1
+MOTOR_M0M1	LITERAL1
+MOTOR_M2M3	LITERAL1
+MOTOR_MOVING	LITERAL1
+MOTOR_READY	LITERAL1
+MOVE_TARGET_ABSOLUTE	LITERAL1
+MOVE_TARGET_REL_END_POSN	LITERAL1
+MS_ACCEL	LITERAL1
+MS_CHANGE_DIR	LITERAL1
+MS_CRUISE	LITERAL1
+MS_DECEL	LITERAL1
+MS_DECEL_VEL	LITERAL1
+MS_END	LITERAL1
+MS_IDLE	LITERAL1
+MS_START	LITERAL1
+NONE	LITERAL1
+NUM_MOTOR_PAIRS	LITERAL1
+NVM_LOC_DAC_SPAN	LITERAL1
+NVM_LOC_DAC_ZERO	LITERAL1
+NVM_LOC_HW_REVISION	LITERAL1
+NVM_LOC_MAC_FIRST	LITERAL1
+NVM_LOC_MAC_SECOND	LITERAL1
+NVM_LOC_RESERVED_TEKNIC	LITERAL1
+NVM_LOC_SERIAL_NUMBER	LITERAL1
+NVM_LOC_USER_MAX	LITERAL1
+NVM_LOC_USER_START	LITERAL1
+OUTPUT_ANALOG	LITERAL1
+OUTPUT_DIGITAL	LITERAL1
+OUTPUT_H_BRIDGE	LITERAL1
+OUTPUT_PWM	LITERAL1
+OUTPUT_TONE	LITERAL1
+OUTPUT_WAVE	LITERAL1
+PARITY_E	LITERAL1
+PARITY_N	LITERAL1
+PARITY_O	LITERAL1
+RESET_NORMAL	LITERAL1
+RESET_TO_BOOTLOADER	LITERAL1
+RISING	LITERAL1
+RS232	LITERAL1
+SCK	LITERAL1
+SCK_HIGH	LITERAL1
+SCK_LOW	LITERAL1
+SDCARD_SPI	LITERAL1
+SERIAL_TYPE	LITERAL1
+SERIAL_USB_TYPE	LITERAL1
+SHIFT_REG_TYPE	LITERAL1
+SPI	LITERAL1
+SPI2	LITERAL1
+SR_ANAIN_DIGITAL_09_MASK	LITERAL1
+SR_ANAIN_DIGITAL_10_MASK	LITERAL1
+SR_ANAIN_DIGITAL_11_MASK	LITERAL1
+SR_ANAIN_DIGITAL_12_MASK	LITERAL1
+SR_A_CTRL_2_MASK	LITERAL1
+SR_A_CTRL_3_MASK	LITERAL1
+SR_CFG00_AOUT_MASK	LITERAL1
+SR_EN_OUT_0_MASK	LITERAL1
+SR_EN_OUT_1_MASK	LITERAL1
+SR_EN_OUT_2_MASK	LITERAL1
+SR_EN_OUT_3_MASK	LITERAL1
+SR_LED_ADI_09_MASK	LITERAL1
+SR_LED_ADI_10_MASK	LITERAL1
+SR_LED_ADI_11_MASK	LITERAL1
+SR_LED_ADI_12_MASK	LITERAL1
+SR_LED_COM_0_MASK	LITERAL1
+SR_LED_COM_1_MASK	LITERAL1
+SR_LED_DI_6_MASK	LITERAL1
+SR_LED_DI_7_MASK	LITERAL1
+SR_LED_DI_8_MASK	LITERAL1
+SR_LED_IO_0_MASK	LITERAL1
+SR_LED_IO_1_MASK	LITERAL1
+SR_LED_IO_2_MASK	LITERAL1
+SR_LED_IO_3_MASK	LITERAL1
+SR_LED_IO_4_MASK	LITERAL1
+SR_LED_IO_5_MASK	LITERAL1
+SR_LED_USB_MASK	LITERAL1
+SR_NO_FEEDBACK_MASK	LITERAL1
+SR_UART_SPI_SEL_0_MASK	LITERAL1
+SR_UART_SPI_SEL_1_MASK	LITERAL1
+SR_UART_TTL_0_MASK	LITERAL1
+SR_UART_TTL_1_MASK	LITERAL1
+SR_UNDERGLOW_MASK	LITERAL1
+SS	LITERAL1
+SUPPLY_ERROR_5VOB_OVERLOAD	LITERAL1
+SUPPLY_ERROR_NONE	LITERAL1
+SUPPLY_ERROR_VSUPPLY_HIGH	LITERAL1
+SUPPLY_ERROR_VSUPPLY_LOW	LITERAL1
+TONE_CONTINUOUS	LITERAL1
+TONE_OFF	LITERAL1
+TONE_PERIODIC_OFF	LITERAL1
+TONE_PERIODIC_ON	LITERAL1
+TONE_TIMED	LITERAL1
+TTL	LITERAL1
+UART	LITERAL1
+USB_CDC	LITERAL1
+
+# keywordify done
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/AnalogIO-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/AnalogIO-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/AnalogIO-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/ReadAnalogInput/ReadAnalogInput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/ReadAnalogInput/ReadAnalogInput.ino
new file mode 100644
index 000000000..27b792e48
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/ReadAnalogInput/ReadAnalogInput.ino
@@ -0,0 +1,137 @@
+/*
+ * Title: ReadAnalogInput
+ *
+ * Objective:
+ *    This example demonstrates how to read the analog voltage of an analog
+ *    input. ClearCore analog inputs are natively compatible with 0-10V signals,
+ *    and 0-20mA signals with addition of an external resistor (see ClearCore
+ *    manual link below for wiring).
+ *
+ * Description:
+ *    This example sets up pin A-12 as an analog input, queries the value on
+ *    that connector every second, and calculates the input voltage. This
+ *    calculated voltage is written/displayed to the USB serial port.
+ *    Connectors IO-0 through IO-5 will act as a coarse meter of the voltage
+ *    read-in by turning on their outputs and LEDs (with more than 0V and less
+ *    than 2V, IO-0 will be on as an output. With ~2V and less than 4V, IO-0 and
+ *    IO-1 will be on; and so on until, with near 10V read in, IO-0 through IO-5
+ *    will be turned on).
+ *
+ * Requirements:
+ * ** An analog input source connected to A-12.
+ * ** Optional: LEDs connected to IO-0 through IO-5 to act as a more prominent
+ *    voltage meter than the ClearCore's onboard LEDs.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Defines the bit-depth of the ADC readings (8-bit, 10-bit, or 12-bit)
+// Supported adcResolution values are 8, 10, and 12
+#define adcResolution 12
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Initialize the serial port for printing analog voltage readings and wait
+    // up to 5 seconds for a port to open. Serial communication is not required
+    // for this example to run, however without it only the coarse LED meter
+    // can be used to read the analog signal.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Make a voltage meter display with the I/O pins.
+    pinMode(IO0, OUTPUT);
+    pinMode(IO1, OUTPUT);
+    pinMode(IO2, OUTPUT);
+    pinMode(IO3, OUTPUT);
+    pinMode(IO4, OUTPUT);
+    pinMode(IO5, OUTPUT);
+
+    // Clear out the state of our voltage meter to start.
+    digitalWrite(IO0, false);
+    digitalWrite(IO1, false);
+    digitalWrite(IO2, false);
+    digitalWrite(IO3, false);
+    digitalWrite(IO4, false);
+    digitalWrite(IO5, false);
+
+    // Since analog inputs default to analog input mode, there's no need to
+    // call pinMode().
+
+    // Set the resolution of the ADC.
+    analogReadResolution(adcResolution);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Read the analog input (A-9 through A-12 may be configured as analog
+    // inputs).
+    int adcResult = analogRead(A12);
+    // Convert the reading to a voltage.
+    double inputVoltage = 10.0 * adcResult / ((1 << adcResolution) - 1);
+
+    // Alternatively, you can use the following to get a measurement in
+    // volts:
+    // inputVoltage = analogRead(A12, MILLIVOLTS) / 1000.0;
+
+    // Display the voltage reading to the USB serial port.
+    Serial.print("A-12 input voltage: ");
+    Serial.print(inputVoltage);
+    Serial.println("V.");
+
+    // Write the voltage reading to the voltage meter display pins
+    // (IO-0 through IO-5).
+    if (inputVoltage > 0.1) {
+        digitalWrite(IO0, true);
+    }
+    else {
+        digitalWrite(IO0, false);
+    }
+    if (inputVoltage > 2.0) {
+        digitalWrite(IO1, true);
+    }
+    else {
+        digitalWrite(IO1, false);
+    }
+    if (inputVoltage > 4.0) {
+        digitalWrite(IO2, true);
+    }
+    else {
+        digitalWrite(IO2, false);
+    }
+    if (inputVoltage > 6.0) {
+        digitalWrite(IO3, true);
+    }
+    else {
+        digitalWrite(IO3, false);
+    }
+    if (inputVoltage > 8.0) {
+        digitalWrite(IO4, true);
+    }
+    else {
+        digitalWrite(IO4, false);
+    }
+    if (inputVoltage >= 9.9) {
+        digitalWrite(IO5, true);
+    }
+    else {
+        digitalWrite(IO5, false);
+    }
+
+    // Wait a second before the next reading.
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.ino
new file mode 100644
index 000000000..15eb8f03d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.ino
@@ -0,0 +1,55 @@
+/*
+ * Title: WriteAnalogCurrentOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write analog current values to an analog
+ *    current output connector.
+ *
+ * Description:
+ *    This example configures pin IO-0 as an analog current output. It outputs
+ *    a repeating analog signal, starting at 0mA, increasing to 20mA, and
+ *    decreasing back to 0mA.
+ *
+ * Requirements:
+ * ** Connect a device to IO-0 which takes in analog current.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up connector IO-0 to be an output. We will specify that it outputs
+    // current in our analogWrite functions later (as opposed to a digital
+    // signal or PWM).
+    // Note that only connector IO-0 is capable of analog current output.
+    pinMode(IO0, OUTPUT);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Ramp the current output of IO-0 up to 20 mA. If using an operating
+    // range of 4-20 mA, change the lower bounds of the loops below to 410
+    // instead of 0.
+    for (uint16_t value = 0; value < 2047; value++) {
+        // ClearCore's analog current output has 11-bit resolution, so we write
+        // values of 0 to 2047 (corresponding to 0-20 mA) or 410 to 2047
+        // (corresponding to 4-20 mA).
+        analogWrite(IO0, value, CURRENT);
+        delay(2);
+    }
+
+    // Ramp the current output of IO-0 back down.
+    for (uint16_t value = 2047; value > 0; value--) {
+        analogWrite(IO0, value, CURRENT);
+        delay(2);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/WritePwmOutput/WritePwmOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/WritePwmOutput/WritePwmOutput.ino
new file mode 100644
index 000000000..398913f69
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/WritePwmOutput/WritePwmOutput.ino
@@ -0,0 +1,57 @@
+/*
+ * Title: WritePwmOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write a digital PWM signal to a ClearCore
+ *    digital output.
+ *
+ * Description:
+ *    This example sets the defined pin as an output then writes a series of
+ *    PWM signals with varying duty cycles to the output.
+ *
+ * Requirements:
+ * ** Connect a device that takes in a PWM signal to IO-1
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Specify which output pin to write digital PWM to.
+// PWM-capable pins: IO-0 through IO-5.
+// Note: IO-4 and IO-5 are capable of bi-directional and higher-current PWM
+//       output using an H-Bridge. See the WriteHBridgeOutput example.
+#define outputPin IO1
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up the output pin to be an output
+    pinMode(outputPin, OUTPUT);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Write some digital PWM signals to the output connector.
+    // Note: analogWrite() is the Arduino wrapper function used to write PWM,
+    // despite the fact that it is not a "true" analog signal
+    // Valid values range from 0 (0% duty cycle / always off)
+    // to 255 (100% duty cycle / always on).
+
+    // Output a low duty cycle for 1 second.
+    analogWrite(outputPin, 10);
+    delay(1000);
+
+    // Output a medium duty cycle for 1 second.
+    analogWrite(outputPin, 120);
+    delay(1000);
+
+    // Output a high duty cycle for 1 second.
+    analogWrite(outputPin, 230);
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/library.properties
new file mode 100644
index 000000000..e16086e83
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/AnalogIO/library.properties
@@ -0,0 +1,9 @@
+name=Analog I/O
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic Analog I/O Examples
+paragraph=Teknic Analog I/O Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.ino
new file mode 100644
index 000000000..278751f37
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.ino
@@ -0,0 +1,173 @@
+/*
+ * Title: ClearCoreIOExpansionBoard
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    read from or write to it. Up to 8 total CCIO-8 boards can be used.
+ *
+ * Description:
+ *    This example sets up COM-0 to control up to 8 CCIO-8 Expansion Boards, 
+ *    sets all CCIO-8 connectors to be either inputs or outputs depending on the 
+ *    selected mode. In input mode, pin statuses are printed to the USB serial 
+ *    port. In output mode, all pins outputs are sequentially turned on then off. 
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board, with power wired, and connected to COM-0. Any 
+ *    other CCIO-8 boards should be chained off of this first board 
+ * ** Edit the value of "inputMode" below to select input mode or output mode
+ * ** (For input mode) A number of inputs, like switches, wired to CCIO-8
+ *    connectors.
+ * ** (For output mode) A number of outputs, like LEDs, wired to CCIO-8
+ *    connectors.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which ClearCore serial COM port is connected to the "COM IN" port
+// of the CCIO-8 board. COM-1 may also be used.
+#define CcioPort ConnectorCOM0
+
+// Set this flag to true to use the CCIO-8 connectors as digital inputs.
+// Set it to false to use the CCIO-8 connectors as digital outputs.
+const bool inputMode = true;
+
+uint8_t ccioBoardCount;     // Store the number of connected CCIO-8 boards here.
+uint8_t ccioPinCount;       // Store the number of connected CCIO-8 pins here.
+
+// Select the baud rate to match the target device
+#define baudRate 9600
+
+// These will be used to format the text that is printed to the serial port.
+#define MAX_MSG_LEN 80
+char msg[MAX_MSG_LEN + 1];
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication to display CCIO-8 state.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Initialize the CCIO-8 board.
+    ccioBoardCount = CcioMgr.CcioCount();
+    // CCIO_PINS_PER_BOARD is a constant defined in the main ClearCore library
+    // that evaluates to 8.
+    ccioPinCount = ccioBoardCount * CCIO_PINS_PER_BOARD;
+
+    // Print the number of discovered CCIO-8 boards to the serial port.
+    snprintf(msg, MAX_MSG_LEN, "Discovered %d CCIO-8 board", ccioBoardCount);
+    Serial.print(msg);
+
+    if (ccioBoardCount != 1) {
+        Serial.print("s");
+    }
+    Serial.println("...");
+    Serial.println();
+
+    if (!inputMode) {
+        // Set each CCIO-8 pin to the correct mode. The CCIO-8 pins default to
+        // being an input so the pin mode doesn't need to be set for input mode.
+        for (uint8_t ccioPinIndex = 0; ccioPinIndex < ccioPinCount; ccioPinIndex++) {
+            pinMode(CLEARCORE_PIN_CCIOA0 + ccioPinIndex, OUTPUT);
+        }
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Make sure the CCIO-8 link is established.
+    if (CcioMgr.LinkBroken()) {
+        uint32_t lastStatusTime = millis();
+        Serial.println("The CCIO-8 link is broken!");
+        // Make sure the CCIO-8 link is established.
+        while (CcioMgr.LinkBroken()) {
+            if (millis() - lastStatusTime > 1000) {
+                Serial.println("The CCIO-8 link is still broken!");
+                lastStatusTime = millis();
+            }
+        }
+        Serial.println("The CCIO-8 link is online again!");
+    }
+
+    // ClearCore can automatically detect when the number of attached CCIO-8
+    // boards changes. Check to see if there's been a change.
+    uint8_t newBoardCount = CcioMgr.CcioCount();
+    if (ccioBoardCount != newBoardCount) {
+        snprintf(msg, MAX_MSG_LEN, "CCIO-8 board count changed from %d to %d.",
+                 ccioBoardCount, newBoardCount);
+        Serial.println(msg);
+        ccioPinCount = newBoardCount * CCIO_PINS_PER_BOARD;
+        ccioBoardCount = newBoardCount;
+    }
+
+    // With one CCIO-8 board attached, we have control over eight additional
+    // digital I/O connectors. On these connectors, we can perform digital
+    // reads and non-PWM digital writes.
+    if (inputMode) {
+        // Read the digital state of CCIO-8 connectors 0 through 7 as inputs.
+        for (uint8_t ccioPinIndex = 0; ccioPinIndex < CCIO_PINS_PER_BOARD; ccioPinIndex++) {
+            uint16_t state = digitalRead(CLEARCORE_PIN_CCIOA0 + ccioPinIndex);
+
+            snprintf(msg, MAX_MSG_LEN, "CCIO-A%d:   ", ccioPinIndex);
+            Serial.print(msg);
+
+            if (state) {
+                Serial.println("ON");
+            }
+            else {
+                Serial.println("OFF");
+            }
+        }
+
+        // If you have multiple CCIO-8 boards attached, individual printouts
+        // become hard to read. We can access all of the CCIO-8 bits at once and
+        // print them out in hex.
+        snprintf(msg, MAX_MSG_LEN, "All CCIO-8 Inputs:   0x%0*llX", ccioBoardCount * 2, CcioMgr.InputState());
+        Serial.println(msg);
+
+        // The application may be only interested in the transitions of an input.
+        // We can read the rise and fall registers and print them out.
+        snprintf(msg, MAX_MSG_LEN, "CCIO-8 Input Rise:   0x%0*llX", ccioBoardCount * 2, CcioMgr.InputsRisen());
+        Serial.println(msg);
+        snprintf(msg, MAX_MSG_LEN, "CCIO-8 Input Fall:   0x%0*llX", ccioBoardCount * 2, CcioMgr.InputsFallen());
+        Serial.println(msg);
+
+        Serial.println("---------------------");
+
+        delay(1000);
+    }
+    else {
+        // Write digital true then digital false to each CCIO-8 connector.
+
+        Serial.println("Writing digital true to each CCIO-8 connector...");
+
+        for (uint8_t ccioPinIndex = 0; ccioPinIndex < ccioPinCount; ccioPinIndex++) {
+            digitalWrite(CLEARCORE_PIN_CCIOA0 + ccioPinIndex, true);
+            delay(500);
+        }
+
+        Serial.println("Writing digital false to each CCIO-8 connector...");
+
+        for (int8_t ccioPinIndex = ccioPinCount - 1; ccioPinIndex >= 0; ccioPinIndex--) {
+            digitalWrite(CLEARCORE_PIN_CCIOA0 + ccioPinIndex, false);
+            delay(500);
+        }
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ReadCCIODigitalInput/ReadCCIODigitalInput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ReadCCIODigitalInput/ReadCCIODigitalInput.ino
new file mode 100644
index 000000000..6201a651f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ReadCCIODigitalInput/ReadCCIODigitalInput.ino
@@ -0,0 +1,74 @@
+/*
+ * Title: ReadCCIODigitalInput
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    read from one of its inputs.
+ *
+ * Description:
+ *    This example sets up COM-0 to control a CCIO-8 Expansion Board then reads
+ *    the state of an input on the CCIO-8's connector 0. During operation, the
+ *    state of the input is printed to the USB serial port.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board powered and connected to COM-0.
+ * ** An digital input device such as a switch connected to the CCIO-8's 
+ *    connector 0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+
+// Specify which ClearCore serial COM port is connected to the COM IN port
+// of the CCIO-8 board: ConnectorCOM0 or ConnectorCOM1.
+#define CcioPort ConnectorCOM0
+
+// Select the baud rate to match the target serial device.
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication to display CCIO-8 state.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Make sure the input connector is in input mode (the default for all
+    // CCIO-8 pins).
+    pinMode(CLEARCORE_PIN_CCIOA0, INPUT);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Read the state of the input connector
+    PinStatus state = digitalRead(CLEARCORE_PIN_CCIOA0);
+
+    // Display the state of the input connector.
+    Serial.print("CCIOA0 Input state: ");
+    if (state) {
+        Serial.println("ON");
+    }
+    else {
+        Serial.println("OFF");
+    }
+
+    // Wait a second then repeat...
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/WriteCCIODigitalOutput/WriteCCIODigitalOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/WriteCCIODigitalOutput/WriteCCIODigitalOutput.ino
new file mode 100644
index 000000000..c3411300c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/WriteCCIODigitalOutput/WriteCCIODigitalOutput.ino
@@ -0,0 +1,74 @@
+/*
+ * Title: WriteCCIODigitalOutput
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    write to its outputs.
+ *
+ * Description:
+ *    This example sets up COM-0 to control a CCIO-8 Expansion Board then
+ *    toggles the state of all of the CCIO-8's outputs from true to false.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board powered and connected to COM-0.
+ * ** An output such as an LED connected to one or more of the CCIO-8's
+ *    connectors.
+ *      Note: You can leave the I/O points disconnected and still see the
+ *      built-in I/O LEDs toggle with the connector state.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which ClearCore serial COM port is connected to the COM IN port
+// of the CCIO-8 board: ConnectorCOM0 or ConnectorCOM1.
+#define CcioPort ConnectorCOM0
+
+// The state to be written to each output connector.
+bool outputState;
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Using the CCIO-8 Board Manager, configure each connector on a single
+    // ClearCore I/O Expansion Board as an output. They can be either digital
+    // inputs or digital outputs.
+    // Note: If there is more than one CCIO-8 in the link, you may want to
+    // to change the limit of the for-loop from "CLEARCORE_PIN_CCIOA7" to the
+    // value of the last CCIO-8 connector to accommodate the additional boards.
+    // For example, if you are using three CCIO-8 boards, change this value to
+    // "CLEARCORE_PIN_CCIOC7", and do the same for the for-loop in the loop()
+    // function below.
+    for (int pin = CLEARCORE_PIN_CCIOA0; pin <= CLEARCORE_PIN_CCIOA7; pin++) {
+        pinMode(pin, OUTPUT);
+    }
+
+    // The connectors are all set up; start the loop with turning them all on.
+    outputState = true;
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Send the current state to each of the outputs.
+    for (int pin = CLEARCORE_PIN_CCIOA0; pin <= CLEARCORE_PIN_CCIOA7; pin++) {
+        digitalWrite(pin, outputState);
+    }
+
+    // Toggle the state to be written next time.
+    outputState = !outputState;
+
+    // Wait 1 second.
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.ino
new file mode 100644
index 000000000..417cb6847
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.ino
@@ -0,0 +1,77 @@
+/*
+ * Title: WriteCCIODigitalOutputPulses
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    write digital pulses to its outputs.
+ *
+ * Description:
+ *    This example sets up COM-0 to control a CCIO-8 Expansion Board then
+ *    writes a series of digital pulses to the defined connector.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board powered and connected to COM-0
+ * ** An output such as an LED connected to defined connector (CCIO-0)
+ *      Note: You can leave the I/O point disconnected and still see the
+ *      built-in I/O LED toggle with the connector state.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which ClearCore serial COM port is connected to the COM IN port
+// of the CCIO-8 board: ConnectorCOM0 or ConnectorCOM1.
+#define CcioPort ConnectorCOM0
+
+// Specify which output pin to write digital output pulses.
+// All connectors on the ClearCore I/O Expansion Board are capable of
+// pulsing the output.
+#define OutputPin CLEARCORE_PIN_CCIOA0
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Set up the output connector in output mode.
+    pinMode(OutputPin, OUTPUT);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Generate a 100ms on/100ms off pulse that runs until
+    // the stop function is called.
+    OutputPulsesStart(OutputPin, 100, 100);
+    delay(1000);
+
+    // Stop any further pulses on the pin. The second argument controls how
+    // output pulses are stopped. If true, the output pulses will be stopped
+    // immediately (this is the default behavior); if false, the active pulse
+    // cycle will be completed first.
+    OutputPulsesStop(OutputPin, true);
+
+    // Generate a 250ms on/50ms off pulse that continues until
+    // 20 on/off cycles are complete or until the stop function
+    // is called.
+    OutputPulsesStart(OutputPin, 250, 50, 20);
+    delay(6000);
+
+    // Pulses should be complete, but call stop to be safe.
+    OutputPulsesStop(OutputPin, true);
+
+    // Generate a 300ms on/500ms off pulse that runs for 5
+    // complete cycles. With the final true argument, the sketch will pause here
+    // until all the pulse cycles are complete.
+    OutputPulsesStart(OutputPin, 300, 500, 5, true);
+    delay(3000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ccio8-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ccio8-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/ccio8-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/library.properties
new file mode 100644
index 000000000..35530bf5f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/CCIO-8/library.properties
@@ -0,0 +1,9 @@
+name=CCIO-8 (I/O Expansion Board)
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic CCIO-8 Examples
+paragraph=Teknic CCIO-8 Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.ino
new file mode 100644
index 000000000..64e970e31
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.ino
@@ -0,0 +1,151 @@
+/*
+ * Title: ClearCoreStatusRegister
+ *
+ * Objective:
+ *    This example demonstrates how to read and display bits in the ClearCore
+ *    Status Register.
+ *
+ * Description:
+ *    This example gets a snapshot of the ClearCore's real-time status register
+ *    and prints the state of the status register bits to the USB serial port.
+ *
+ * Requirements:
+ * ** None
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    Serial.begin(9600);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Get a copy of the real-time status register.
+    StatusManager::StatusRegister statusReg = StatusMgr.StatusRT();
+
+    Serial.println("Status Register:");
+
+    Serial.print("Vsupply over-voltage:\t\t");
+    if (statusReg.bit.VSupplyOverVoltage) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("Vsupply under-voltage:\t\t");
+    if (statusReg.bit.VSupplyUnderVoltage) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("H-Bridge output overloaded:\t");
+    if (statusReg.bit.HBridgeOverloaded) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("H-Bridge resetting:\t\t");
+    if (statusReg.bit.HBridgeReset) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    // This status bit denotes the state of the 5 volt supply for off-board
+    // items
+    Serial.print("Offboard 5V overloaded:\t\t");
+    if (statusReg.bit.Overloaded5V) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("Output overloaded:\t\t");
+    if (statusReg.bit.OutputOverloaded) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("CCIO-8 output overloaded:\t");
+    if (statusReg.bit.CcioOverloaded) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("CCIO-8 link broken:\t\t");
+    if (statusReg.bit.CcioLinkBroken) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("ADC in timeout:\t\t\t");
+    if (statusReg.bit.AdcTimeout) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("Ethernet disconnect:\t\t");
+    if (statusReg.bit.EthernetDisconnect) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("Ethernet remote fault:\t\t");
+    if (statusReg.bit.EthernetRemoteFault) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.print("SD card error:\t\t\t");
+    if (statusReg.bit.SdCardError) {
+        Serial.println('1');
+    }
+    else {
+        Serial.println('0');
+    }
+
+    Serial.println("------------------------");
+
+    // Wait a couple seconds then repeat...
+    delay(2000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/clearcore-board-status-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/clearcore-board-status-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/clearcore-board-status-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/library.properties
new file mode 100644
index 000000000..c1122f507
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearCoreBoardStatus/library.properties
@@ -0,0 +1,9 @@
+name=ClearCore Board Status
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Board Status Examples
+paragraph=Teknic ClearCore Board Status Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalPosition/FollowDigitalPosition.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalPosition/FollowDigitalPosition.ino
new file mode 100644
index 000000000..4b51f12fc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalPosition/FollowDigitalPosition.ino	
@@ -0,0 +1,246 @@
+
+/*
+ * Title: FollowDigitalPosition
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Follow Digital Position Command, Unipolar PWM Command.
+ *
+ * Description:
+ *    This example enables and then moves a ClearPath motor between various
+ *    positions within a range defined in the MSP software based on the state
+ *    of an analog input. During operation, various move statuses are written
+ *    to the USB serial port.
+ *    To achieve better positioning resolution (i.e. more commandable positions),  
+ *    consider using the ClearPath operational modes "Pulse Burst Positioning"
+ *    or "Move Incremental Distance" instead.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Position Command, Unipolar PWM Command mode (In MSP
+ *    select Mode>>Position>>Follow Digital Position Command, then with
+ *    "Unipolar PWM Command" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined positions for 0% and 100% PWM (On the
+ *    main MSP window check the "Position Range Setup (cnts)" box and fill in
+ *    the two text boxes labeled "Posn at 0% PWM" and "Posn at 100% PWM").
+ *    Change the "PositionZeroPWM" and "PositionMaxPWM" variables in the example
+ *    below to match.
+ * 5. Homing must be configured in the MSP software for your mechanical
+ *    system (e.g. homing direction, torque limit, etc.). This example does
+ *    not use the ClearPath's Input A as a homing sensor, although that may
+ *    be configured in this mode through MSP.
+ * 6. An analog input source (0-10V) connected to Connector A-9 to control motor 
+ *    position.
+ * 7. (Optional) An input source, such as a switch, connected to DI-6 to control
+ *    the Command Lock or Home Sensor (configured in MSP).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode12
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector
+#define motor ConnectorM0
+
+// Defines the command lock sensor connector
+#define LockSensor DI6
+
+// Defines the analog input to control commanded position
+#define AnalogSensor ConnectorA9
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Defines the bounds for our position range. These positions cannot actually be
+// commanded, only values inside this range.
+double positionZeroPWM = 0;
+double positionMaxPWM = 10000;
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+void LockSensorCallback();
+bool CommandPosition(int commandedPosition);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+    
+    // Set up an analog sensor to control commanded position.
+    AnalogSensor.Mode(Connector::INPUT_ANALOG);
+
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Position mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_PWM);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // This section attaches the interrupt callback to the locking sensor pin,
+    // set to trigger on any change of sensor state
+    pinMode(LockSensor, INPUT);
+    attachInterrupt(digitalPinToInterrupt(LockSensor), LockSensorCallback, CHANGE);
+    // Set input A to match the initial state of the sensor
+    motor.MotorInAState(digitalRead(LockSensor));
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Read the voltage on the analog sensor (0-10V).
+    float analogVoltage = AnalogSensor.AnalogVoltage();
+    // Convert the voltage measured to a position within the valid range.
+    int32_t commandedPosition =
+        static_cast<int32_t>(round(analogVoltage / 10 * positionMaxPWM));
+    CommandPosition(commandedPosition);    // See below for the detailed function definition.
+}
+
+/*------------------------------------------------------------------------------
+ * CommandPosition
+ *
+ *    Move to position number commandedPosition (counts in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns whether the command has been updated.
+ *
+ * Parameters:
+ *    int commandedPosition  - The position, in counts, to command
+ *
+ */
+bool CommandPosition(int commandedPosition) {
+    if (abs(commandedPosition) > abs(positionMaxPWM) || 
+        abs(commandedPosition) < abs(positionZeroPWM)) {
+        Serial.println("Move rejected, invalid position requested");
+        return false;
+    }
+
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving to position: ");
+    Serial.println(commandedPosition);
+
+    // Find the scaling factor of our position range mapped to the PWM duty
+    // cycle range (255 is the max duty cycle).
+    double scaleFactor = 255 / abs(positionMaxPWM - positionZeroPWM);
+
+    // Scale the position command to our duty cycle range.
+    int dutyRequest = abs(commandedPosition - positionZeroPWM) * scaleFactor;
+
+    // Command the move.
+    motor.MotorInBDuty(dutyRequest);
+    
+    return true;
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * LockSensorCallback
+ *
+ *    Reads the state of the locking sensor and passes the state to the motor.
+ *
+ * Parameters:
+ *    None
+ *
+ * Returns: None
+ */
+void LockSensorCallback() {
+    // A 1 ms delay is required in order to pass the correct filtered sensor
+    // state.
+    delay(1);
+    motor.MotorInAState(digitalRead(LockSensor));
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalTorque/FollowDigitalTorque.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalTorque/FollowDigitalTorque.ino
new file mode 100644
index 000000000..f24e170d0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalTorque/FollowDigitalTorque.ino	
@@ -0,0 +1,175 @@
+/*
+ * Title: FollowDigitalTorque
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Follow Digital Torque Command, Unipolar PWM Command.
+ *
+ * Description:
+ *    This example enables and then commands a ClearPath motor to output various
+ *    torques. in both the clockwise and counterclockwise directions.
+ *    During operation, various move statuses are written to the USB serial
+ *    port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Torque Command, Unipolar PWM Command mode  (In MSP
+ *    select Mode>>Torque>>Follow Digital Torque Command, then with
+ *    "Unipolar PWM Command" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Torque"
+ *    through the MSP software (select Advanced>>High Level Feedback [Mode]...
+ *    then choose "All Systems Go (ASG) - Torque" from the dropdown and hit
+ *    the OK button).
+ * 4. The ClearPath must have a defined Max Torque Command configured through
+ *    the MSP software. This value must match the "maxTorque" variable defined
+ *    below.
+ * 5. Ensure the Input A filter in MSP is set to 20ms (In MSP select
+ *    Advanced>>Input A, B Filtering... then in the Settings box fill in the
+ *    textbox labeled "Input A Filter Time Constant (msec)" then hit the OK
+ *    button).
+ * 6. Set your Max Speed and Over-Speed Timeout in MSP according to your
+ *    mechanical system. Note you may notice any of the following if this max
+ *    speed is reached: motor shutdown, speed limit cycling at the max speed,
+ *    HLFB not signaling ASG/move done.
+ * 7. Ensure the "Invert PWM Input" box is unchecked in MSP.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_FILTER must match the Input A filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Defines the limit of the torque command, as a percent of the motor's peak
+// torque rating (must match the value used in MSP).
+double maxTorque = 100;
+
+// Declares our user-defined helper function, which is used to command torque.
+// The definition/implementation of this function is at the bottom of the sketch.
+bool CommandTorque(int commandedTorque);
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Torque mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_PWM);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+    Serial.println("Motor Ready");
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Output 15% of the motor's peak torque in the positive (CCW) direction.
+    CommandTorque(15);    // See below for the detailed function definition.
+    // Wait 2000ms.
+    delay(2000);
+
+    CommandTorque(-75); // Output 75% peak torque in the negative (CW) direction.
+    delay(2000);
+
+    CommandTorque(5); // Output 5% peak torque in the positive (CCW) direction.
+    delay(2000);
+
+    CommandTorque(-35); // Output 35% peak torque in the negative (CW) direction.
+    delay(2000);
+
+    CommandTorque(10); // Output 10% peak torque in the positive (CCW) direction.
+    delay(2000);
+}
+
+/*------------------------------------------------------------------------------
+ * CommandTorque
+ *
+ *    Command the motor to move using a torque of commandedTorque
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    torque)
+ *
+ * Parameters:
+ *    int commandedTorque  - The torque to command
+ *
+ * Returns: True/False depending on whether the torque was successfully
+ * commanded.
+ */
+bool CommandTorque(int commandedTorque) {
+    if (abs(commandedTorque) > abs(maxTorque)) {
+        Serial.println("Move rejected, invalid torque requested");
+        return false;
+    }
+	
+    Serial.print("Commanding torque: ");
+    Serial.println(commandedTorque);
+
+    // Find the scaling factor of our torque range mapped to the PWM duty cycle
+    // range (255 is the max duty cycle).
+    double scaleFactor = 255 / maxTorque;
+
+    // Scale the torque command to our duty cycle range.
+    int dutyRequest = abs(commandedTorque) * scaleFactor;
+
+    // Set input A to match the direction of torque.
+    if (commandedTorque < 0) {
+        motor.MotorInAState(true);
+    }
+    else {
+        motor.MotorInAState(false);
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A filter
+    // setting in MSP
+    delay(2 + INPUT_A_FILTER);
+
+    // Command the move
+    motor.MotorInBDuty(dutyRequest);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving... Waiting for HLFB");
+    // Allow some time for HLFB to transition
+    delay(1);
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+
+    Serial.println("Move Done");
+    return true;
+}
+//------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalVelocity/FollowDigitalVelocity.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalVelocity/FollowDigitalVelocity.ino
new file mode 100644
index 000000000..fa6562a64
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalVelocity/FollowDigitalVelocity.ino	
@@ -0,0 +1,155 @@
+/* 
+ * Title: FollowDigitalVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Follow Digital Velocity Command, Unipolar PWM Command.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes velocity moves based
+ *    on the state of an analog input sensor. During operation, various move
+ *    statuses are written to the USB serial port.
+ *    Consider using Manual Velocity Control mode instead if you do not wish to 
+ *    use an analog sensor to command velocity, if you require greater velocity 
+ *    command resolution (i.e. more commandable positions), or if HLFB is needed 
+ *    for "move done/at speed" status feedback.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Velocity Command, Unipolar PWM Command mode (In MSP
+ *    select Mode>>Velocity>>Follow Digital Velocity Command, then with
+ *    "Unipolar PWM Command" selected hit the OK button).
+ * 3. The ClearPath must have a defined Max Speed configured through the MSP
+ *    software (On the main MSP window fill in the "Max Speed (RPM)" box with
+ *    your desired maximum speed). Ensure the value of maxSpeed below matches
+ *    this Max Speed.
+ * 4. Ensure the "Invert PWM Input" checkbox found on the MSP's main window is
+ *    unchecked.
+ * 5. Ensure the Input A filter in MSP is set to 20ms, (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textbox labeled "Input A Filter Time Constant (msec)" then hit the OK
+ *    button).
+ * 6. An analog input source (0-10V) connected to ConnectorA9 to control
+ *    motor velocity.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode8
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Defines the analog input to control commanded velocity
+#define AnalogSensor ConnectorA9
+
+// The INPUT_A_FILTER must match the Input A filter setting in MSP
+// (Advanced >> Input A, B Filtering...)
+#define INPUT_A_FILTER 20
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This is the commanded speed limit in RPM (must match the MSP value). This speed
+// cannot actually be commanded, so use something slightly higher than your real
+// max speed here and in MSP.
+double maxSpeed = 510;
+
+// Declares our user-defined helper function, which is used to command velocity 
+// The definition/implementation of this function is at the bottom of
+// this example.
+bool CommandVelocity(long commandedVelocity);
+
+void setup() {
+    // Put your setup code here, it will only run once:
+    
+    // Set up an analog sensor to control commanded velocity.
+    AnalogSensor.Mode(Connector::INPUT_ANALOG);
+    
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Velocity, Unipolar PWM mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_PWM);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+}
+
+void loop() {
+    // Read the voltage on the analog sensor (0-10V).
+    float analogVoltage = AnalogSensor.AnalogVoltage();
+    // Convert the voltage measured to a velocity within the valid range.
+    long commandedVelocity =
+        static_cast<int32_t>(round(analogVoltage / 10 * maxSpeed));
+
+    // Move at the commanded velocity.
+    CommandVelocity(commandedVelocity);    // See below for the detailed function definition.
+}
+
+/*------------------------------------------------------------------------------
+ * CommandVelocity
+ *
+ *    Command the motor to move using a velocity of commandedVelocity
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int commandedVelocity  - The velocity to command
+ *
+ * Returns: True/False depending on whether the velocity was successfully
+ * commanded.
+ */
+bool CommandVelocity(long commandedVelocity) {  
+    if (abs(commandedVelocity) >= abs(maxSpeed)) {
+        Serial.println("Move rejected, requested velocity at or over the limit.");
+        return false;
+    }
+
+    Serial.print("Commanding Velocity: ");
+    Serial.println(commandedVelocity);
+
+    // Change ClearPath's Input A state to change direction.
+    // Note: this section of code was included so this commandVelocity function 
+    // could be used to command negative (opposite direction) velocity. However the 
+    // analog signal used by this example only commands positive velocities.
+    if (commandedVelocity >= 0) {
+        motor.MotorInAState(false);
+    }
+    else {
+        motor.MotorInAState(true);
+    }
+    // Delays to send the correct filtered direction.
+    delay(2 + INPUT_A_FILTER);
+
+    // Find the scaling factor of our velocity range mapped to the PWM duty
+    // cycle range (255 is the max duty cycle).
+    double scaleFactor = 255 / maxSpeed;
+
+    // Scale the velocity command to our duty cycle range.
+    int dutyRequest = abs(commandedVelocity) * scaleFactor;
+
+    // Command the move.
+    motor.MotorInBDuty(dutyRequest);
+
+    return true;
+}
+//------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.ino
new file mode 100644
index 000000000..e051498b2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.ino	
@@ -0,0 +1,220 @@
+/*
+ * Title: FollowDigitalVelocityWithVariableTorque
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Follow Digital Velocity Command, Bipolar PWM Command with Variable Torque
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    bidirectional velocity moves and torque limits. During operation, various
+ *    move statuses are written to the USB serial port.
+ *    The resolution for PWM outputs is 8-bit, meaning only 256 discrete speeds
+ *    and torque limits can be commanded. The motor's actual commanded speed
+ *    and torque limit may differ slightly from what you input below because
+ *    of this.
+ *    Consider using Manual Velocity Control mode if greater velocity command
+ *    resolution is required, or if HLFB is needed for "move done/at speed"
+ *    status feedback.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Velocity Command, Bipolar PWM Command with Variable
+ *    Torque mode (In MSP select Mode>>Velocity>>Follow Digital Velocity
+ *    Command, then with "Bipolar PWM Command w/ Variable Torque")
+ * 3. The ClearPath must have a defined Max Speed configured through the MSP
+ *    software (On the main MSP window fill in the "Max Speed (RPM)" box with
+ *    your desired maximum speed). Ensure the value of maxSpeed below matches
+ *    this Max Speed.
+ * 4. Set the PWM Deadband in MSP to 2.
+ * 5. In MSP, ensure the two checkboxes for "Invert Torque PWM Input" and
+ *    "Invert Speed PWM Input" are unchecked.
+ * 6. A primary Torque Limit and Alternate Torque Limit must be defined using
+ *    the Torque Limit setup window through the MSP software (To configure,
+ *    click the "Setup..." button found under the "Torque Limit" label. Then
+ *    fill in the textbox labeled "Alt Torque Limit (% of max)" and hit the
+ *    Apply button). Use only symmetric limits. These limits must match the
+ *    "torqueLimit" and "torqueLimitAlternate" variables defined below.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This is the commanded speed limit (must match the MSP value). This speed
+// cannot actually be commanded, so use something slightly higher than your real
+// max speed here and in MSP.
+double maxVelocity = 2000;
+
+// Defines the default torque limit and the alternate torque limit
+// (must match MSP values)
+double torqueLimit = 100.0;
+double torqueLimitAlternate = 10.0;
+
+// A PWM deadband of 2% prevents signal jitter from effecting a 0 RPM command
+// (must match MSP value)
+double pwmDeadBand = 2.0;
+
+// Declares our user-defined helper functions, which are used to command
+// velocity and limit torque. The definitions/implementations of these functions
+// are at the bottom of the sketch.
+bool CommandVelocity(int commandedVelocity);
+bool LimitTorque(double limit);
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Velocity, Bipolar PWM mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_PWM_B_PWM);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for 5 seconds for motor to come up to speed
+    Serial.println("Waiting for motor to come up to speed...");
+    startTime = millis();
+    while (millis() - startTime < timeout) {
+        continue;
+    }
+    Serial.println("Motor Ready");
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move at +100 RPM (CCW).
+    CommandVelocity(100);    // See below for the detailed function definition.
+    // Wait 5000ms
+    delay(5000);
+
+    CommandVelocity(300);    // Move at +300 RPM (CCW).
+    delay(5000);
+
+    // Limit the torque to 70%.
+    LimitTorque(70);         // See below for the detailed function definition.
+
+    CommandVelocity(-200);   // Move at -200 RPM (CW).
+    delay(5000);
+
+    LimitTorque(15);         // Limit the torque to 15%.
+    CommandVelocity(-300);   // Move at -300 RPM (CW).
+    delay(5000);
+
+    LimitTorque(100);        // Increase torque limit to 100%.
+    CommandVelocity(100);    // Move at +100 RPM (CCW).
+    delay(5000);
+}
+
+/*------------------------------------------------------------------------------
+ * CommandVelocity
+ *
+ *    Command the motor to move using a velocity of commandedVelocity
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int commandedVelocity  - The velocity to command
+ *
+ * Returns: True/False depending on whether the velocity was successfully
+ * commanded.
+ */
+bool CommandVelocity(int commandedVelocity) {
+    if (abs(commandedVelocity) > maxVelocity) {
+        Serial.println("Move rejected, invalid velocity requested.");
+        return false;
+    }
+
+    Serial.print("Commanding velocity: ");
+    Serial.println(commandedVelocity);
+
+    // If there is a deadband defined, the range of the PWM scale is reduced.
+    double rangeUnsigned = 127.5 - (pwmDeadBand / 100 * 255);
+
+    // Find the scaling factor of our velocity range mapped to the PWM duty cycle
+    // range (the PWM to the ClearPath is bipolar, so the range starts at a 50%
+    // duty cycle).
+    double scaleFactor = rangeUnsigned / maxVelocity;
+
+    // Scale the velocity command to our duty cycle range.
+    double dutyRequest;
+    if (commandedVelocity < 0) {
+        dutyRequest = 127.5 - (pwmDeadBand / 100 * 255)
+                      + (commandedVelocity * scaleFactor);
+    }
+    else if (commandedVelocity > 0) {
+        dutyRequest = 127.5 + (pwmDeadBand / 100 * 255)
+                      + (commandedVelocity * scaleFactor);
+    }
+    else {
+        dutyRequest = 128.0;
+    }
+
+    // Command the move.
+    motor.MotorInBDuty(dutyRequest);
+
+    Serial.println("Velocity Commanded");
+    return true;
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * LimitTorque
+ *
+ *    Command the motor to limit the maximum applied torque to (limit)%
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int limit  - The torque level to command
+ *
+ * Returns: True/False depending on whether the torque limit was successfully
+ * commanded.
+ */
+bool LimitTorque(double limit) {
+    if (limit > torqueLimit || limit < torqueLimitAlternate) {
+        Serial.println("Torque limiting rejected, invalid torque requested.");
+        return false;
+    }
+    Serial.print("Limit torque to: ");
+    Serial.print(limit);
+    Serial.println("%.");
+
+    // Find the scaling factor of our torque range mapped to the PWM duty cycle
+    // range (255 is the max duty cycle).
+    double scaleFactor = 255 / (torqueLimit - torqueLimitAlternate);
+
+    // Scale the torque limit command to our duty cycle range.
+    int dutyRequest = (torqueLimit - limit) * scaleFactor;
+
+    // Command the new torque limit.
+    motor.MotorInADuty(dutyRequest);
+
+    return true;
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/ManualVelocity/ManualVelocity.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/ManualVelocity/ManualVelocity.ino
new file mode 100644
index 000000000..2f438c73d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/ManualVelocity/ManualVelocity.ino	
@@ -0,0 +1,290 @@
+/*
+ * Title: ManualVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Manual Velocity Control.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    bidirectional velocity moves. During operation, various move statuses are
+ *    written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Manual Velocity Control mode (In MSP select Mode>>Velocity>>Manual
+ *    Velocity Control, then hit the OK button).
+ * 3. In the MSP software:
+ *    * Define a Max Clockwise and Counter-Clockwise (CW/CCW) Velocity (On the
+ *      main MSP window fill in the textboxes labeled "Max CW Velocity (RPM)"
+ *      and "Max CCW Velocity (RPM)"). Any velocity commanded outside of this
+ *      range will be rejected.
+ *    * Set the Velocity Resolution to 2 (On the main MSP window check the
+ *      textbox labeled "Velocity Resolution (RPM per knob count)" 2 is
+ *      default). This means the commanded velocity will always be a multiple
+ *      of 2. For finer resolution, lower this value and change
+ *      velocityResolution in the sketch below to match.
+ *    * Set Knob Direction to As-Wired, and check the Has Detents box (On the
+ *      main MSP window check the dropdown labeled "Knob Direction" and the
+ *      checkbox directly below it labeled "Has Detents").
+ *    * On the main MSP window set the dropdown labeled "On Enable..." to be
+ *      "Zero Velocity".
+ *    * Set the HLFB mode to "ASG-Velocity w/Measured Torque" with a PWM carrier
+ *      frequency of 482 Hz through the MSP software (select Advanced>>High
+ *      Level Feedback [Mode]... then choose "ASG-Velocity w/Measured Torque" 
+ *      from the dropdown, make sure that 482 Hz is selected in the "PWM Carrier
+ *      Frequency" dropdown, and hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// This is the variable used to keep track of the current commanded velocity
+double commandedVelocity = 0;
+
+// A reference to the maximum clockwise and counter-clockwise velocities set in
+// the MSP software. These must match the values in MSP
+int maxVelocityCW = 1000;
+int maxVelocityCCW = 1000;
+
+// Each velocity commanded will be a multiple of this value, which must match
+// the Velocity Resolution value in MSP. Use a lower value here (and in MSP) to
+// command velocity with a finer resolution
+double velocityResolution = 2.0;
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveAtVelocity(double velocity);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set all motor connectors to the correct mode for Manual Velocity
+    // mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    // the motor.
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert 
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Spin at 500 RPM in the CCW direction.
+    MoveAtVelocity(500);    // See below for the detailed function definition.
+
+    // Hold the velocity for 5 seconds before issuing a new command.
+    delay(5000);
+
+    // Spin at 100 RPM in the CW direction.
+    MoveAtVelocity(-100);
+    delay(5000);
+
+    // Spin at 750 RPM in the CW direction.
+    MoveAtVelocity(-750);
+    delay(5000);
+
+    // Spin at 1000 RPM in the CCW direction.
+    MoveAtVelocity(1000);
+    delay(5000);
+
+    // Command 0 RPM, the motor shaft is stationary.
+    MoveAtVelocity(0);
+    delay(5000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveAtVelocity
+ *
+ *    Triggers a quadrature output commanding the desired velocity.
+ *    Prints the velocity and move status to the USB serial port.
+ *    Returns when HLFB asserts (indicating move has successfully completed).
+ *
+ * Parameters:
+ *    double velocity  - The velocity in RPM to command
+ *
+ * Returns: True/False depending on whether a new velocity was reached
+ */
+bool MoveAtVelocity(double velocity) {
+    // If the same velocity is commanded there's nothing to do.
+    if (velocity == commandedVelocity) {
+        return false;
+    }
+
+    // Check to see if the requested velocity exceeds the valid range.
+    if (velocity > maxVelocityCCW || velocity < -maxVelocityCW) {
+        Serial.print("An invalid velocity of ");
+        Serial.print(velocity);
+        Serial.println(" RPM has been requested.");
+        return false;
+    }
+
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Commanding ");
+    Serial.print(velocity);
+    Serial.println(" RPM");
+
+    // Determine which order the quadrature must be sent by determining if the
+    // new velocity is greater or less than the previously commanded velocity
+    // If greater, Input A begins the quadrature. If less, Input B begins the
+    // quadrature.
+    int32_t currentVelocityRounded = round(commandedVelocity / velocityResolution);
+    int32_t targetVelocityRounded = round(velocity / velocityResolution);
+    int32_t velocityDifference = labs(targetVelocityRounded - currentVelocityRounded);
+    for (int32_t i = 0; i < velocityDifference; i++) {
+        if (velocity > commandedVelocity) {
+            // Toggle Input A to begin the quadrature signal.
+            motor.MotorInAState(true);
+            // Command a 5 microsecond delay to ensure proper signal timing.
+            delayMicroseconds(5);
+            motor.MotorInBState(true);
+            delayMicroseconds(5);
+            motor.MotorInAState(false);
+            delayMicroseconds(5);
+            motor.MotorInBState(false);
+            delayMicroseconds(5);
+        }
+        else {
+            motor.MotorInBState(true);
+            delayMicroseconds(5);
+            motor.MotorInAState(true);
+            delayMicroseconds(5);
+            motor.MotorInBState(false);
+            delayMicroseconds(5);
+            motor.MotorInAState(false);
+            delayMicroseconds(5);
+        }
+    }
+
+    // Keeps track of the new commanded velocity
+    commandedVelocity = velocity;
+
+    // Waits for HLFB to assert (signaling the motor has successfully reached
+    // its target velocity).
+    Serial.println("Ramping Speed... Waiting for HLFB");
+    // Wait for some time so HLFB has time to transition.
+    delay(1);
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.ino
new file mode 100644
index 000000000..0a3cde868
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.ino	
@@ -0,0 +1,259 @@
+/*
+ * Title: 16PositionsHomeToHardStop
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move To Absolute Position, 16 Positions (Home to Hard Stop)
+ *
+ * Description:
+ *    This example enables, homes, and then moves a ClearPath motor between
+ *    preprogrammed absolute positions as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move To Absolute Position, 16 Positions (Home to Hard Stop) mode (In
+ *    MSP select Mode>>Position>>Move to Absolute Position, then with "16
+ *    Positions (Home to Hard Stop)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Absolute Position Selections through
+ *    the MSP software (On the main MSP window fill in the textboxes labeled
+ *    1-16 found under "Position Selection Setup (cnts)").
+ * 5. Homing must be configured in the MSP software for your mechanical
+ *    system (e.g. homing direction, torque limit, etc.). To configure, click
+ *    the "Setup..." button found under the "Homing" label on the MSP's main
+ *    window.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveToPosition(int positionNum);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets all motor connectors to the correct mode for Absolute Position mode
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling the motor
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and wait up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(9600);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move to Position 1 defined in MSP
+    MoveToPosition(1);    // See below for the detailed function definition
+    // Wait 1000ms
+    delay(1000);
+    MoveToPosition(2);
+    delay(1000);
+    MoveToPosition(3);
+    delay(1000);
+    MoveToPosition(4);
+    delay(1000);
+
+    MoveToPosition(5);
+    delay(1000);
+    MoveToPosition(6);
+    delay(1000);
+    MoveToPosition(7);
+    delay(1000);
+    MoveToPosition(8);
+    delay(1000);
+
+    MoveToPosition(9);
+    delay(1000);
+    MoveToPosition(10);
+    delay(1000);
+    MoveToPosition(11);
+    delay(1000);
+    MoveToPosition(12);
+    delay(1000);
+
+    MoveToPosition(13);
+    delay(1000);
+    MoveToPosition(14);
+    delay(1000);
+    MoveToPosition(15);
+    delay(1000);
+    MoveToPosition(16);
+    delay(1000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveToPosition
+ *
+ *    Move to position number positionNum (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int positionNum  - The position number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether the position was successfully
+ * commanded.
+ */
+bool MoveToPosition(int positionNum) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving to position: ");
+    Serial.println(positionNum);
+
+    if (positionNum < 17 && positionNum > 0) {
+        // Sends pulses on Input B based on positionNum
+        for (int i = 0; i < positionNum; i++) {
+            motor.MotorInBState(true);
+            delay(1);
+            motor.MotorInBState(false);
+            delay(1);
+        }
+
+        // Triggers the command
+        motor.MotorInAState(true);
+        delay(1);
+        motor.MotorInAState(false);
+    }
+    else {
+        // If an invalid positionNum has been entered, returns a failure
+        return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    delay(1);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+
+    Serial.println("Move Done");
+    return true;
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.ino
new file mode 100644
index 000000000..2ef40733f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.ino	
@@ -0,0 +1,258 @@
+/*
+ * Title: 2PositionsHomeToSwitch
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Move To Absolute Position, 2 Positions (Home to Switch)
+ *
+ * Description:
+ *    This example enables, homes, and then moves a ClearPath motor between
+ *    preprogrammed absolute positions as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move To Absolute Position, 2 Positions (Home to Switch) mode (In MSP
+ *    select Mode>>Position>>Move to Absolute Position, then with "2 Positions
+ *    (Home to Switch)" selected hit the OK button).
+ * 3. Homing must be configured in the MSP software for your mechanical system
+ *    (e.g. homing direction, switch polarity, etc.). To configure, click the
+ *    "Setup..." button found under the "Homing" label on the MSP's main window.
+ * 4. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 5. Wire the homing sensor to Connector DI-6
+ * 6. The ClearPath must have defined Absolute Position Selections set up in the
+ *    MSP software (On the main MSP window check the "Position Selection Setup
+ *    (cnts)" box and fill in the two text boxes labeled "A off" and "A on").
+ * 7. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Specifies the home sensor connector
+#define HomingSensor DI6
+
+// Select the baud rate to match the target device
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+void HomingSensorCallback();
+bool MoveToPosition(int positionNum);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets all motor connectors to the correct mode for Absolute Position mode
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's Input A before enabling the motor
+    motor.MotorInAState(false);
+
+    // This section attaches the interrupt callback to the homing sensor pin,
+    // set to trigger on any change of sensor state
+    pinMode(HomingSensor, INPUT);
+    attachInterrupt(digitalPinToInterrupt(HomingSensor), HomingSensorCallback, CHANGE);
+    // Set input B to match the initial state of the sensor
+    motor.MotorInBState(digitalRead(HomingSensor));
+
+    // Sets up serial communication and wait up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move to Position 1 defined in MSP
+    MoveToPosition(1);    // See below for the detailed function definition
+    // Wait 1000ms
+    delay(1000);
+    MoveToPosition(2);
+    delay(1000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveToPosition
+ *
+ *    Move to position number positionNum (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int positionNum  - The position number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether a valid position was
+ * successfully commanded and reached.
+ */
+bool MoveToPosition(int positionNum) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving to position: ");
+    Serial.print(positionNum);
+
+    switch (positionNum) {
+        case 1:
+            // Sets Input A "off" for position 1
+            motor.MotorInAState(false);
+            Serial.println(" (Input A Off)");
+            break;
+        case 2:
+            // Sets Input A "on" for position 2
+            motor.MotorInAState(true);
+            Serial.println(" (Input A On)");
+            break;
+        default:
+            // If this case is reached then an incorrect positionNum was entered
+            return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    delay(2 + INPUT_A_B_FILTER);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+
+    Serial.println("Move Done");
+    return true;
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * HomingSensorCallback
+ *
+ *    Reads the state of the homing sensor and passes the state to the motor.
+ */
+void HomingSensorCallback() {
+    // A 1 ms delay is required in order to pass the correct filtered sensor
+    // state
+    delay(1);
+    motor.MotorInBState(digitalRead(HomingSensor));
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.ino
new file mode 100644
index 000000000..89b90a9cd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveAbsolutePosition/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.ino	
@@ -0,0 +1,265 @@
+/*
+ * Title: 4PositionsHomeToHardStop
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move To Absolute Position, 4 Positions (Home to Hard Stop)
+ *
+ * Description:
+ *    This example enables, homes, and then moves a ClearPath motor between
+ *    preprogrammed absolute positions as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move To Absolute Position, 4 Positions (Home to Hard Stop) mode (In
+ *    MSP select Mode>>Position>>Move to Absolute Position, then with "4
+ *    Positions (Home to Hard Stop)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Absolute Position Selections through
+ *    the MSP software (On the main MSP window check the "Position Selection
+ *    Setup (cnts)" box and fill in the four text boxes labeled "A off B off",
+ *    "A on B off", "A off B on" and "A on B on").
+ * 5. Homing must be configured in the MSP software for your mechanical
+ *    system (e.g. homing direction, torque limit, etc.). To configure, click
+ *    the "Setup..." button found under the "Homing" label on the MSP's main
+ *    window.
+ * 6. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveToPosition(int positionNum);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets all motor connectors to the correct mode for Absolute Position mode
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling the motor
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move to Position 1 defined in MSP
+    MoveToPosition(1);    // See below for the detailed function definition
+    // Wait 1000ms
+    delay(1000);
+    MoveToPosition(2);
+    delay(1000);
+    MoveToPosition(3);
+    delay(1000);
+    MoveToPosition(4);
+    delay(1000);
+
+    // Alternatively, if you'd like to control the ClearPath servo's inputs
+    // externally using ClearCore inputs, consider doing something like this:
+    /*
+     motor.MotorInAState(digitalRead(DI6)); // Sets ClearPath's InA to DI6's
+                                            // state
+     motor.MotorInBState(digitalRead(DI7)); // Sets ClearPath's InB to DI7's
+                                            // state
+    */
+}
+
+/*------------------------------------------------------------------------------
+ * MoveToPosition
+ *
+ *    Move to position number positionNum (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int positionNum  - The position number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether the position was successfully
+ * commanded.
+ */
+bool MoveToPosition(int positionNum) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving to position: ");
+    Serial.print(positionNum);
+
+    switch (positionNum) {
+        case 1:
+            // Sets Input A and B for position 1
+            motor.MotorInAState(false);
+            motor.MotorInBState(false);
+            Serial.println(" (Inputs A Off/B Off)");
+            break;
+        case 2:
+            // Sets Input A and B for position 2
+            motor.MotorInAState(true);
+            motor.MotorInBState(false);
+            Serial.println(" (Inputs A On/B Off)");
+            break;
+        case 3:
+            // Sets Input A and B for position 3
+            motor.MotorInAState(false);
+            motor.MotorInBState(true);
+            Serial.println(" (Inputs A Off/B On)");
+            break;
+        case 4:
+            // Sets Input A and B for position 4
+            motor.MotorInAState(true);
+            motor.MotorInBState(true);
+            Serial.println(" (Inputs A On/B On)");
+            break;
+        default:
+            // If this case is reached then an incorrect positionNum was entered
+            return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    delay(2 + INPUT_A_B_FILTER);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+
+    Serial.println("Move Done");
+    return true;
+}
+//------------------------------------------------------------------------------
+
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveIncrementalDistance/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveIncrementalDistance/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.ino
new file mode 100644
index 000000000..db514fe76
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveIncrementalDistance/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.ino	
@@ -0,0 +1,298 @@
+/*
+ * Title: 2IncrementsHomeToSwitch
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move Incremental Distance, 2 Increments (Home to Switch).
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    incremental moves. During operation, various move statuses are written to
+ *    the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move Incremental Distance, 2 Increments (Home to Switch) mode (In MSP
+ *    select Mode>>Position>>Move Incremental Distance, then with "2 Increments
+ *    (Home to Switch)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. If the ClearPath is configured for sensor-based homing, ensure that the
+ *    homing sensor is wired to Connector DI-6 (homing is optional, not required
+ *    in this operational mode or in this example).
+ * 5. The ClearPath must have defined Position Increments through the MSP
+ *    software which match the #define values below (On the main MSP window
+ *    check the "Position Increment Setup (cnts)" box and fill in the two text
+ *    boxes labeled "A off" and "A on").
+ * 6. Ensure the Trigger Pulse Time in MSP is set to 20ms. To configure, click
+ *    the "Setup..." button found under the "Trigger Pulse" label on the MSP's
+ *    main window, fill in the text box, and hit the OK button. Setting this to 
+ *    20ms allows trigger pulses to be as long as 60ms, which will accommodate 
+ *    our 25ms pulses used later.
+ * 7. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction or there are no
+ *    end of travel limits
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Define the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// The TRIGGER_PULSE_TIME is set to 25ms to ensure it is within the
+// Trigger Pulse Range defined in the MSP software (Default is 20-60ms)
+#define TRIGGER_PULSE_TIME 25
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Increments defined below must be set identically to the position increments
+// set in MSP
+#define POSITION_INCREMENT_1 1000  // Input A "off" setup selection, 1000 counts (CCW)
+#define POSITION_INCREMENT_2 -1000 // Input A "on" setup selection, -1000 counts (CW)
+
+// Specify the home sensor connector
+#define HomingSensor DI6
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+void HomingSensorCallback();
+bool MoveIncrements(int numberOfIncrements, int positionIncrement);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Sets all motor connectors to the correct mode for Incremental Distance
+    // mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling the motor
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // This section attaches the interrupt callback to the homing sensor pin,
+    // set to trigger on any change of sensor state.
+    pinMode(HomingSensor, INPUT);
+    attachInterrupt(digitalPinToInterrupt(HomingSensor), HomingSensorCallback, CHANGE);
+    // Set input B to match the initial state of the sensor
+    motor.MotorInBState(digitalRead(HomingSensor));
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if homing is enabled
+    // in MSP.
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move a distance equal to 1 * POSITION_INCREMENT_1 = 1000 counts.
+    // See below for the detailed function definition.
+    MoveIncrements(1, POSITION_INCREMENT_1);
+    // Stay settled for 1 second before moving again.
+    delay(1000);
+
+    // Move a distance equal to 1 * POSITION_INCREMENT_2 = -1000 counts.
+    MoveIncrements(1, POSITION_INCREMENT_2);
+    delay(1000);
+
+    // Note: If another incremental move is triggered in the same direction as
+    // an active move before deceleration begins, then the moves will be
+    // seamlessly combined into one continuous move
+
+    // Move a distance equal to 4 * POSITION_INCREMENT_1 = 4000 counts.
+    MoveIncrements(4, POSITION_INCREMENT_1);
+    delay(1000);
+
+    // Move a distance equal to 4 * POSITION_INCREMENT_2 = -4000 counts.
+    MoveIncrements(4, POSITION_INCREMENT_2);
+    delay(1000);
+}
+
+
+/*------------------------------------------------------------------------------
+ * MoveIncrements
+ *
+ *    Triggers an incremental move of length numberOfIncrements *
+ *    positionIncrement.
+ *    Prints the distance and move status to the USB serial port.
+ *    Returns when HLFB asserts (indicating move has successfully completed).
+ *
+ * Parameters:
+ *    int numberOfIncrements  - The number of increments to command
+ *    int positionIncrement   - The position increment commanded
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveIncrements(int numberOfIncrements, int positionIncrement) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving ");
+    Serial.print(numberOfIncrements);
+    Serial.print(" * ");
+
+    switch (positionIncrement) {
+        case POSITION_INCREMENT_1:
+            // Sets Input A to position increment 1
+            Serial.println(POSITION_INCREMENT_1);
+            motor.MotorInAState(false);
+            break;
+        case POSITION_INCREMENT_2:
+            // Sets Input A to position increment 2
+            Serial.println(POSITION_INCREMENT_2);
+            motor.MotorInAState(true);
+            break;
+        default:
+            // If this case is reached then an incorrect positionIncrement was
+            // entered
+            return false;
+    }
+
+    // Delays for 2ms longer than the Input A, B filter setting in MSP
+    delay(2 + INPUT_A_B_FILTER);
+
+    // Sends trigger pulses to the motor
+    motor.EnableTriggerPulse(numberOfIncrements, TRIGGER_PULSE_TIME, true);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * HomingSensorCallback
+ *
+ *    Reads the state of the homing sensor and passes the state to the motor.
+ */
+void HomingSensorCallback() {
+    // A 1 ms delay is required in order to pass the correct filtered sensor
+    // state.
+    delay(1);
+    motor.MotorInBState(digitalRead(HomingSensor));
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+    Delay_ms(3*TRIGGER_PULSE_TIME);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveIncrementalDistance/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveIncrementalDistance/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.ino
new file mode 100644
index 000000000..659d97c27
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/MoveIncrementalDistance/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.ino	
@@ -0,0 +1,286 @@
+/*
+ * Title: 4IncrementsHomeToHardStop
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move Incremental Distance, 4 Increments (Home to Hard Stop).
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    incremental moves. During operation, various move statuses are written to
+ *    the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move Incremental Distance, 4 Increments (Home to Hard Stop) mode (In
+ *    MSP select Mode>>Position>>Move Incremental Distance, then with "4
+ *    Increments (Home to Hard Stop)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Position Increments through the MSP
+ *    software which match the #define values below (On the main MSP window
+ *    check the "Position Increment Setup (cnts)" box and fill in the four text
+ *    boxes labeled "A off B off", "A on B off", "A off B on", and "A on B on").
+ * 5. Ensure the Trigger Pulse Time in MSP is set to 20ms. To configure, click
+ *    the "Setup..." button found under the "Trigger Pulse" label on the MSP's
+ *    main window, fill in the text box, and hit the OK button. Setting this to 
+ *    20ms allows trigger pulses to be as long as 60ms, which will accommodate 
+ *    our 25ms pulses used later.
+ * 6. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Define the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// The TRIGGER_PULSE_TIME is set to 25ms to ensure it is within the
+// Trigger Pulse Range defined in the MSP software (Default is 20-60ms)
+#define TRIGGER_PULSE_TIME 25
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Increments defined below must be set identically to the position increments
+// set in MSP
+#define POSITION_INCREMENT_1 750   // Inputs A off / B off, 750 counts (CCW)
+#define POSITION_INCREMENT_2 -750  // Inputs A on / B off, -750 counts (CW)
+#define POSITION_INCREMENT_3 1666  // Inputs A off / B on, 1666 counts (CCW)
+#define POSITION_INCREMENT_4 -1666 // Inputs A on / B on, -1666 counts (CW)
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveIncrements(int NumberOfIncrements, int PositionIncrement);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Sets all motor connectors to the correct mode for Incremental Distance
+    // mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling the motor
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if homing is enabled
+    // in MSP
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move a distance equal to 1 * POSITION_INCREMENT_1 = 750 counts
+    MoveIncrements(1, POSITION_INCREMENT_1);    // See below for the detailed
+                                                // function definition
+    // Stay settled for 1 second before moving again.
+    delay(1000);
+
+    // Move a distance equal to 1 * POSITION_INCREMENT_2 = -750 counts
+    MoveIncrements(1, POSITION_INCREMENT_2);
+    delay(1000);
+
+    // Note: If another incremental move is triggered in the same direction as
+    // an active move before deceleration begins, then the moves will be
+    // seamlessly combined into one continuous move
+
+    // Move a distance equal to 2 * POSITION_INCREMENT_3 = 3332 counts
+    MoveIncrements(2, POSITION_INCREMENT_3);
+    delay(1000);
+
+    // Move a distance equal to 2 * POSITION_INCREMENT_4 = -3332 counts
+    MoveIncrements(2, POSITION_INCREMENT_4);
+    delay(1000);
+}
+
+
+/*------------------------------------------------------------------------------
+ * MoveIncrements
+ *
+ *    Triggers an incremental move of length numberOfIncrements *
+ *    positionIncrement.
+ *    Prints the distance and move status to the USB serial port.
+ *    Returns when HLFB asserts (indicating move has successfully completed).
+ *
+ * Parameters:
+ *    int numberOfIncrements  - The number of increments to command
+ *    int positionIncrement   - The position increment commanded
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveIncrements(int numberOfIncrements, int positionIncrement) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving ");
+    Serial.print(numberOfIncrements);
+    Serial.print(" * ");
+
+    switch (positionIncrement) {
+        case POSITION_INCREMENT_1:
+            // Sets Input A and B to position increment 1
+            Serial.println(POSITION_INCREMENT_1);
+            motor.MotorInAState(false);
+            motor.MotorInBState(false);
+            break;
+        case POSITION_INCREMENT_2:
+            // Sets Input A and B to position increment 2
+            Serial.println(POSITION_INCREMENT_2);
+            motor.MotorInAState(true);
+            motor.MotorInBState(false);
+            break;
+        case POSITION_INCREMENT_3:
+            // Sets Input A and B to position increment 3
+            Serial.println(POSITION_INCREMENT_3);
+            motor.MotorInAState(false);
+            motor.MotorInBState(true);
+            break;
+        case POSITION_INCREMENT_4:
+            // Sets Input A and B to position increment 4
+            Serial.println(POSITION_INCREMENT_4);
+            motor.MotorInAState(true);
+            motor.MotorInBState(true);
+            break;
+        default:
+            // If this case is reached then an incorrect positionIncrement was
+            // entered
+            return false;
+    }
+
+    // Delays 2ms longer than the Input A, B filter setting in MSP
+    delay(2 + INPUT_A_B_FILTER);
+
+    // Sends trigger pulses to the motor
+    motor.EnableTriggerPulse(numberOfIncrements, TRIGGER_PULSE_TIME, true);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+    Delay_ms(3*TRIGGER_PULSE_TIME);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/PulseBurstPositioning/PulseBurstPositioning.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/PulseBurstPositioning/PulseBurstPositioning.ino
new file mode 100644
index 000000000..b918623d0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/PulseBurstPositioning/PulseBurstPositioning.ino	
@@ -0,0 +1,287 @@
+/*
+ * Title: PulseBurstPositioning
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Pulse Burst Positioning.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    positional move commands. During operation, various move statuses are
+ *    written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Pulse Burst Positioning mode (In MSP select Mode>>Position>>Pulse
+ *    Burst Positioning, then hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Ensure the Trigger Pulse Time in MSP is set to 20ms. To configure, click
+ *    the "Setup..." button found under the "Trigger Pulse" label on the MSP's
+ *    main window, fill in the text box, and hit the OK button. Setting this to 
+ *    20ms allows trigger pulses to be as long as 60ms, which will accommodate 
+ *    our 25ms pulses used later.
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// The TRIGGER_PULSE_TIME is set to 25ms to ensure it is within the
+// Trigger Pulse Range defined in the MSP software (Default is 20ms, which 
+// allows a range of pulses up to 60ms)
+#define TRIGGER_PULSE_TIME 25
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveDistance(int pulseNum);
+void PrintAlerts();
+void HandleAlerts();
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // To command for Pulse Burst Positioning, use the step and direction
+    // interface with the acceleration and velocity limits set to their
+    // maximum values. The ClearPath will then take the pulses and enforce
+    // the motion profile constraints.
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(INT32_MAX);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(INT32_MAX);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if homing is enabled
+    // in MSP.
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move 6400 counts (positive direction) then wait 1000ms
+    MoveDistance(6400);
+    delay(1000);
+    // Move 19200 counts farther positive, then wait 1000ms
+    MoveDistance(19200);
+    delay(1000);
+
+    // Generates a trigger pulse on the enable line so the next move uses the
+    // Alt Speed Limit.
+    motor.EnableTriggerPulse(1, TRIGGER_PULSE_TIME, true);
+
+    // Move back 12800 counts (negative direction), then wait 1000ms
+    MoveDistance(-12800);
+    delay(1000);
+    // Move back 6400 counts (negative direction), then wait 1000ms
+    MoveDistance(-6400);
+    delay(1000);
+    // Move back to the start (negative 6400 pulses), then wait 1000ms
+    MoveDistance(-6400);
+    delay(1000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveDistance
+ *
+ *    Command "distance" number of step pulses away from the current position
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int distance  - The distance, in step pulses, to move
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveDistance(int distance) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Move canceled.");		
+		Serial.println();
+        return false;
+    }
+
+    Serial.print("Commanding ");
+    Serial.print(distance);
+    Serial.println(" pulses");
+
+    // Command the move of incremental distance
+    motor.Move(distance);
+
+    // Add a short delay to allow HLFB to update
+    delay(2);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while ( (!motor.StepsComplete() || motor.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	Serial.println("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		Serial.println("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		Serial.println("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		Serial.println("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		Serial.println("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		Serial.println("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		Serial.println("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		Serial.println("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(3*TRIGGER_PULSE_TIME);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	Serial.println("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.ino
new file mode 100644
index 000000000..1007e503b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.ino	
@@ -0,0 +1,261 @@
+/*
+ * Title: RampUpDownToSelectedVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Ramp Up/Down To Selected Velocity.
+ *
+ * Description:
+ *    This example enables and then moves a ClearPath motor between
+ *    preprogrammed velocity selections as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Ramp Up/Down to Selected Velocity mode (In MSP
+ *    select Mode>>Velocity>>Ramp Up/Down to Selected Velocity, then hit the OK
+ *    button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Velocity
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Velocity w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Velocity Selections through the MSP
+ *    software (On the main MSP window check the "Velocity Selection Setup
+ *    (RPM)" box and fill in the four text boxes labeled "A off B off", "A on B
+ *    off", "A off B on", and "A on B on").
+ * 5. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool RampToVelocitySelection(int velocityIndex);
+void HandleMotorFaults();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets all motor connectors to the correct mode for Ramp Up/Down to
+    // Selected Velocity mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling the motor
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+
+void loop() {
+    // Move to Velocity 1 defined in MSP (Inputs A off, B off).
+    // See below for the detailed function definition.
+    RampToVelocitySelection(1);
+
+    // Wait 1000ms.
+    delay(1000);
+    RampToVelocitySelection(2); // Inputs A on, B off
+    delay(1000);
+    RampToVelocitySelection(3); // Inputs A off, B on
+    delay(1000);
+    RampToVelocitySelection(4); // Inputs A on, B on
+    delay(1000);
+
+    // Alternatively, if you'd like to control the ClearPath motor's inputs
+    // directly using ClearCore inputs consider doing something like this:
+    /*
+    // Sets ClearPath's InA to DI6's state.
+     motor.MotorInAState(digitalRead(DI6));
+
+    // Sets ClearPath's InB to DI7's state.
+     motor.MotorInBState(digitalRead(DI7));
+    */
+}
+
+/*------------------------------------------------------------------------------
+ * RampToVelocitySelection
+ *
+ *    Move to Velocity Selection number velocityIndex (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the target
+ *    velocity)
+ *
+ * Parameters:
+ *    int velocityIndex  - The velocity number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether the velocity selection was
+ * successfully commanded.
+ */
+bool RampToVelocitySelection(int velocityIndex) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			Serial.println("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			Serial.println("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    Serial.print("Moving to Velocity Selection: ");
+    Serial.print(velocityIndex);
+
+    switch (velocityIndex) {
+        case 1:
+            // Sets Input A and B for velocity 1
+            motor.MotorInAState(false);
+            motor.MotorInBState(false);
+            Serial.println(" (Inputs A Off/B Off)");
+            break;
+        case 2:
+            // Sets Input A and B for velocity 2
+            motor.MotorInAState(true);
+            motor.MotorInBState(false);
+            Serial.println(" (Inputs A On/B Off)");
+            break;
+        case 3:
+            // Sets Input A and B for velocity 3
+            motor.MotorInAState(false);
+            motor.MotorInBState(true);
+            Serial.println(" (Inputs A Off/B On)");
+            break;
+        case 4:
+            // Sets Input A and B for velocity 4
+            motor.MotorInAState(true);
+            motor.MotorInBState(true);
+            Serial.println(" (Inputs A On/B On)");
+            break;
+        default:
+            // If this case is reached then an incorrect velocityIndex was
+            // entered
+            return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    delay(2 + INPUT_A_B_FILTER);
+
+    // Waits for HLFB to assert (signaling the move has successfully reached its
+    // target velocity)
+    Serial.println("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		Serial.println("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	Serial.println("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/library.properties
new file mode 100644
index 000000000..f4d06d39f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-MC Series/library.properties	
@@ -0,0 +1,9 @@
+name=ClearPath-MC Series
+version=0.0.1
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Library
+paragraph=Teknic ClearCore Library
+category=Device Control
+url=https://git-server.teknic.com/Git-Playground/clearcore-examples
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/DualAxisSynchronized/DualAxisSynchronized.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/DualAxisSynchronized/DualAxisSynchronized.ino
new file mode 100644
index 000000000..67e01e8f5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/DualAxisSynchronized/DualAxisSynchronized.ino	
@@ -0,0 +1,325 @@
+/*
+ * Title: DualAxisSynchronized
+ *
+ * Objective:
+ *    This example demonstrates control of two ClearPath-SD motors synchronously
+ *    in Step and Direction mode. Use this example when two motors must follow
+ *    identical commands (e.g. a mechanically connected dual-axis or gantry).
+ *
+ * Description:
+ *    This example enables two motors then commands a repeating series of
+ *    synchronized moves. Move status is printed to the USB serial port. This
+ *    example commands a max travel of 25600 pulses.
+ *
+ * Requirements:
+ * 1. Two ClearPath motors must be connected, one to Connector M-0 the other to
+ *    Connector M-1.
+ * 2. The connected ClearPath motors must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motors must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. If the two motors must spin in opposite directions (i.e. they are mounted
+ *    facing different directions), check the "Reverse Direction" checkbox of
+ *    one motor in MSP.
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motors to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor0 ConnectorM0
+#define motor1 ConnectorM1
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int velocityLimit = 10000; // pulses per sec
+int accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool SynchronizedMove(int distance);
+void PrintAlerts();
+void HandleAlerts();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Put the motor connectors into the HLFB mode to read bipolar PWM (the
+    // correct mode for ASG w/ Measured Torque)
+    motor0.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    motor1.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+ 
+    // Set the HFLB carrier frequencies to 482 Hz
+    motor0.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+    motor1.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+    
+    // Sets the maximum velocity for each move
+    motor0.VelMax(velocityLimit);
+    motor1.VelMax(velocityLimit);
+
+    // Sets the maximum acceleration for each move
+    motor0.AccelMax(accelerationLimit);
+    motor1.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motors; homing will begin automatically if enabled in MSP
+    motor0.EnableRequest(true);
+    Serial.println("Motor 0 Enabled");
+    motor1.EnableRequest(true);
+    Serial.println("Motor 1 Enabled");
+
+	
+    // Waits for both motors to finish enabling
+    uint32_t lastStatusTime = millis();
+    Serial.println("Waiting for HLFB...");
+    while (motor0.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			motor1.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor0.StatusReg().bit.AlertsPresent && 
+			!motor1.StatusReg().bit.AlertsPresent) {
+		// Periodically prints out why the application is waiting
+        if (millis() - lastStatusTime > 100) {
+            Serial.println("Waiting for HLFB to assert on both motors");
+            lastStatusTime = millis();
+        }    
+	}
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor0.StatusReg().bit.AlertsPresent || 
+		motor1.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motors Ready");	
+	}
+}
+
+void loop() {
+    // Move 6400 counts (positive direction) then wait 2000ms.
+    SynchronizedMove(6400);
+    delay(2000);
+    // Move 19200 counts farther positive, then wait 2000ms.
+    SynchronizedMove(19200);
+    delay(2000);
+    // Move back 12800 counts (negative direction), then wait 2000ms.
+    SynchronizedMove(-12800);
+    delay(2000);
+    // Move back 6400 counts (negative direction), then wait 2000ms.
+    SynchronizedMove(-6400);
+    delay(2000);
+    // Move back to the start (negative 6400 pulses), then wait 2000ms.
+    SynchronizedMove(-6400);
+    delay(2000);
+}
+
+/*------------------------------------------------------------------------------
+ * SynchronizedMove
+ *
+ *    Moves two motors an incremental distance synchronously.
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int distance  - The distance, in counts, to move
+ *
+ * Returns: True/False depending on whether the moves were successfully
+ *    triggered.
+ */
+bool SynchronizedMove(int distance) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor0.StatusReg().bit.AlertsPresent || motor1.StatusReg().bit.AlertsPresent ) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Move canceled.");		
+		Serial.println();
+        return false;
+    }
+	
+	
+	Serial.print("Moving distance: ");
+    Serial.println(distance);
+
+    // Move both motors the same distance
+    motor0.Move(distance);
+    motor1.Move(distance);
+
+    // Wait until both motors complete their moves
+    uint32_t lastStatusTime = millis();
+    while ( (!motor0.StepsComplete() || motor0.HlfbState() != MotorDriver::HLFB_ASSERTED ||
+           !motor1.StepsComplete() || motor1.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+		   !motor0.StatusReg().bit.AlertsPresent && !motor1.StatusReg().bit.AlertsPresent ){
+        // Periodically print out why the application is waiting
+        if (millis() - lastStatusTime > 100) {
+            Serial.println("Waiting for HLFB to assert on both motors");
+            lastStatusTime = millis();
+        }
+        
+        // Check if motor alert occurred during move
+		// Clear alert if configured to do so 
+        if (motor0.StatusReg().bit.AlertsPresent || motor1.StatusReg().bit.AlertsPresent){
+            motor0.MoveStopAbrupt();
+            motor1.MoveStopAbrupt();
+			Serial.println("Motor alert detected.");		
+			PrintAlerts();
+			if(HANDLE_ALERTS){
+				HandleAlerts();
+			} else {
+				Serial.println("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+			}
+			Serial.println("Motion may not have completed as expected. Proceed with caution.");
+			Serial.println();
+			return false;
+		} else {
+			Serial.println("Move Done");
+			return true;
+		}
+   }
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor0" and "motor1" to be defined as ClearCore motor connectors
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts on motor0
+ 	Serial.println("Alerts present on motor0: ");
+	if(motor0.AlertReg().bit.MotionCanceledInAlert){
+		Serial.println("    MotionCanceledInAlert "); }
+	if(motor0.AlertReg().bit.MotionCanceledPositiveLimit){
+		Serial.println("    MotionCanceledPositiveLimit "); }
+	if(motor0.AlertReg().bit.MotionCanceledNegativeLimit){
+		Serial.println("    MotionCanceledNegativeLimit "); }
+	if(motor0.AlertReg().bit.MotionCanceledSensorEStop){
+		Serial.println("    MotionCanceledSensorEStop "); }
+	if(motor0.AlertReg().bit.MotionCanceledMotorDisabled){
+		Serial.println("    MotionCanceledMotorDisabled "); }
+	if(motor0.AlertReg().bit.MotorFaulted){
+		Serial.println("    MotorFaulted ");
+	}
+	
+	// report status of alerts on motor1
+ 	Serial.println("Alerts present on motor1: ");
+	if(motor1.AlertReg().bit.MotionCanceledInAlert){
+		Serial.println("    MotionCanceledInAlert "); }
+	if(motor1.AlertReg().bit.MotionCanceledPositiveLimit){
+		Serial.println("    MotionCanceledPositiveLimit "); }
+	if(motor1.AlertReg().bit.MotionCanceledNegativeLimit){
+		Serial.println("    MotionCanceledNegativeLimit "); }
+	if(motor1.AlertReg().bit.MotionCanceledSensorEStop){
+		Serial.println("    MotionCanceledSensorEStop "); }
+	if(motor1.AlertReg().bit.MotionCanceledMotorDisabled){
+		Serial.println("    MotionCanceledMotorDisabled "); }
+	if(motor1.AlertReg().bit.MotorFaulted){
+		Serial.println("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor0" and "motor1" to be defined as ClearCore motor connectors
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	// for each motor, if a motor fault is present, clear it by cycling enable
+	if(motor0.AlertReg().bit.MotorFaulted){
+		Serial.println("Faults present on motor0. Cycling enable signal to motor to clear faults.");
+		motor0.EnableRequest(false);
+		Delay_ms(10);
+		motor0.EnableRequest(true);
+	}
+	if(motor1.AlertReg().bit.MotorFaulted){
+		Serial.println("Faults present on motor1. Cycling enable signal to motor to clear faults.");
+		motor1.EnableRequest(false);
+		Delay_ms(10);
+		motor1.EnableRequest(true);
+	}
+	// clear alerts
+	Serial.println("Clearing alerts on both motors.");
+	motor0.ClearAlerts();
+	motor1.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MotorStatusRegister/MotorStatusRegister.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MotorStatusRegister/MotorStatusRegister.ino
new file mode 100644
index 000000000..f21b316ae
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MotorStatusRegister/MotorStatusRegister.ino	
@@ -0,0 +1,185 @@
+/*
+ * Title: MotorStatusRegister
+ *
+ * Objective:
+ *    This example demonstrates how to read and display bits in the ClearCore's
+ *    MotorDriver status register.
+ *
+ * Description:
+ *    This example gets a snapshot of the status register for each MotorDriver
+ *    connector with an attached motor. Then, the state of the status register
+ *    bits is printed to the USB serial port.
+ *
+ * Requirements:
+ * ** A ClearPath motor must be connected to Connector M-0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// The containers for our motor objects. If only some of the motor connectors
+// are being used, remove the unused entries from the following arrays and
+// reduce motorConnectorCount.
+MotorDriver *motorConnectors[] = {&ConnectorM0, &ConnectorM1,
+                                  &ConnectorM2, &ConnectorM3
+                                 };
+char motorConnectorNames[][4] = { "M-0", "M-1", "M-2", "M-3" };
+uint8_t motorConnectorCount = 4;
+
+// Hold a string representation of each motor's ready state.
+char *readyStateStr;
+
+// Declare our helper function so that it may be used before it is defined.
+char *ReadyStateString(MotorDriver::MotorReadyStates readyState);
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Get a copy of the motor status register for each motor connector.
+    for (uint8_t i = 0; i < motorConnectorCount; i++) {
+        MotorDriver *motor = motorConnectors[i];
+        volatile const MotorDriver::StatusRegMotor &statusReg = motor->StatusReg();
+        volatile const MotorDriver::AlertRegMotor &alertReg = motor->AlertReg();
+        
+        Serial.print("Motor status register for motor M");
+      Serial.print(i);
+      Serial.print(": ");
+      Serial.println(statusReg.reg, 2); // prints the status register in binary
+      
+      Serial.print("AtTargetPosition:  ");
+      Serial.println(statusReg.bit.AtTargetPosition);
+    
+      Serial.print("StepsActive:       ");
+      Serial.println(statusReg.bit.StepsActive);
+    
+      Serial.print("AtTargetVelocity:  ");
+      Serial.println(statusReg.bit.AtTargetVelocity);
+    
+      Serial.print("MoveDirection:     ");
+      Serial.println(statusReg.bit.MoveDirection);
+    
+      Serial.print("MotorInFault:      ");
+      Serial.println(statusReg.bit.MotorInFault);
+    
+      Serial.print("Enabled:           ");
+      Serial.println(statusReg.bit.Enabled);
+    
+      Serial.print("PositionalMove:    ");
+      Serial.println(statusReg.bit.PositionalMove);
+    
+      Serial.print("HLFB State:    ");
+      switch (statusReg.bit.HlfbState) {
+        case 0:
+          Serial.println("HLFB_DEASSERTED");
+          break;
+        case 1:
+          Serial.println("HLFB_ASSERTED");
+          break;
+        case 2:
+          Serial.println("HLFB_HAS_MEASUREMENT");
+          break;
+        case 3:
+          Serial.println("HLFB_UNKNOWN");
+          break;
+        default:
+          // something has gone wrong if this is printed
+          Serial.println("???");
+      }
+    
+      Serial.print("AlertsPresent:     ");
+      Serial.println(statusReg.bit.AlertsPresent);
+    
+      Serial.print("Ready state:   ");
+      switch (statusReg.bit.ReadyState) {
+        case MotorDriver::MOTOR_DISABLED:
+          Serial.println("Disabled");
+          break;
+        case MotorDriver::MOTOR_ENABLING:
+          Serial.println("Enabling");
+          break;
+        case MotorDriver::MOTOR_FAULTED:
+          Serial.println("Faulted");
+          break;
+        case MotorDriver::MOTOR_READY:
+          Serial.println("Ready");
+          break;
+        case MotorDriver::MOTOR_MOVING:
+          Serial.println("Moving");
+          break;
+        default:
+          // something has gone wrong if this is printed
+          Serial.println("???");
+      }
+      
+      Serial.print("Triggering:        ");
+      Serial.println(statusReg.bit.Triggering);
+    
+      Serial.print("InPositiveLimit:   ");
+      Serial.println(statusReg.bit.InPositiveLimit);
+    
+      Serial.print("InNegativeLimit:   ");
+      Serial.println(statusReg.bit.InNegativeLimit);
+    
+      Serial.print("InEStopSensor:     ");
+      Serial.println(statusReg.bit.InEStopSensor); 
+    
+      Serial.println("--------------------------------");
+      
+        
+      if (statusReg.bit.AlertsPresent){
+        Serial.print("Alert register:  ");
+        Serial.println(alertReg.reg, 2); // prints the alert register in binary
+    
+        Serial.print("MotionCanceledInAlert:         ");
+        Serial.println(alertReg.bit.MotionCanceledInAlert);
+    
+        Serial.print("MotionCanceledPositiveLimit:   ");
+        Serial.println(alertReg.bit.MotionCanceledPositiveLimit);
+    
+        Serial.print("MotionCanceledNegativeLimit:   ");
+        Serial.println(alertReg.bit.MotionCanceledNegativeLimit);
+    
+        Serial.print("MotionCanceledSensorEStop:     ");
+        Serial.println(alertReg.bit.MotionCanceledSensorEStop);
+    
+        Serial.print("MotionCanceledMotorDisabled:   ");
+        Serial.println(alertReg.bit.MotionCanceledMotorDisabled);
+    
+        Serial.print("MotorFaulted:                  ");
+        Serial.println(alertReg.bit.MotorFaulted);
+    
+        Serial.println("--------------------------------");
+      }
+    }
+    // Wait a few seconds then repeat...
+    delay(5000);
+}
+
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MovePositionAbsolute/MovePositionAbsolute.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MovePositionAbsolute/MovePositionAbsolute.ino
new file mode 100644
index 000000000..ae64ec2de
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MovePositionAbsolute/MovePositionAbsolute.ino	
@@ -0,0 +1,272 @@
+ /*
+ * Title: MovePositionAbsolute
+ *
+ * Objective:
+ *    This example demonstrates control of a ClearPath motor in Step and
+ *    Direction mode.
+ *
+ * Description:
+ *    This example enables a ClearPath then commands a series of repeating
+ *    absolute position moves to the motor.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes positive absolute position moves,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int velocityLimit = 10000; // pulses per sec
+int accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+void PrintAlerts();
+void HandleAlerts();
+
+// Declares our user-defined helper function, which is used to command moves to
+// the motor. The definition/implementation of this function is at the  bottom
+// of the example
+bool MoveAbsolutePosition(int32_t position);
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(velocityLimit);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if enabled
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move to +10000 counts (positive direction), then wait 2000ms
+    MoveAbsolutePosition(10000);
+    delay(2000);
+    // Move to 19200 counts, then wait 2000ms
+    MoveAbsolutePosition(19200);
+    delay(2000);
+    // Move to 12800 counts, then wait 2000ms
+    MoveAbsolutePosition(12800);
+    delay(2000);
+    // Move back to "home", then wait 2000ms
+    MoveAbsolutePosition(0);
+    delay(2000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveAbsolutePosition
+ *
+ *    Command step pulses to move the motor's current position to the absolute
+ *    position specified by "position"
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int position  - The absolute position, in step pulses, to move to
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveAbsolutePosition(int position) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Move canceled.");		
+		Serial.println();
+        return false;
+    }
+
+    Serial.print("Moving to absolute position: ");
+    Serial.println(position);
+
+    // Command the move of absolute distance
+    motor.Move(position, MotorDriver::MOVE_TARGET_ABSOLUTE);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while ( (!motor.StepsComplete() || motor.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	Serial.println("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		Serial.println("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		Serial.println("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		Serial.println("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		Serial.println("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		Serial.println("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		Serial.println("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		Serial.println("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(10);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	Serial.println("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MovePositionRelative/MovePositionRelative.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MovePositionRelative/MovePositionRelative.ino
new file mode 100644
index 000000000..4a9f9b752
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MovePositionRelative/MovePositionRelative.ino	
@@ -0,0 +1,270 @@
+/*
+ * Title: MovePositionRelative
+ *
+ * Objective:
+ *    This example demonstrates control of a ClearPath motor in Step and
+ *    Direction mode.
+ *
+ * Description:
+ *    This example enables a ClearPath then commands a series of repeating
+ *    moves to the motor.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int velocityLimit = 10000; // pulses per sec
+int accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveDistance(int distance);
+void PrintAlerts();
+void HandleAlerts();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(velocityLimit);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if enabled
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move 6400 counts (positive direction), then wait 2000ms
+    MoveDistance(6400);
+    delay(2000);
+    // Move 19200 counts farther positive, then wait 2000ms
+    MoveDistance(19200);
+    delay(2000);
+    // Move back 12800 counts (negative direction), then wait 2000ms
+    MoveDistance(-12800);
+    delay(2000);
+    // Move back 6400 counts (negative direction), then wait 2000ms
+    MoveDistance(-6400);
+    delay(2000);
+    // Move back to the start (negative 6400 pulses), then wait 2000ms
+    MoveDistance(-6400);
+    delay(2000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveDistance
+ *
+ *    Command "distance" number of step pulses away from the current position
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int distance  - The distance, in step pulses, to move
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveDistance(int distance) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Move canceled.");		
+		Serial.println();
+        return false;
+    }
+
+    Serial.print("Moving distance: ");
+    Serial.println(distance);
+
+    // Command the move of incremental distance
+    motor.Move(distance);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    Serial.println("Moving.. Waiting for HLFB");
+    while ( (!motor.StepsComplete() || motor.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Motion may not have completed as expected. Proceed with caution.");
+		Serial.println();
+		return false;
+    } else {
+		Serial.println("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	Serial.println("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		Serial.println("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		Serial.println("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		Serial.println("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		Serial.println("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		Serial.println("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		Serial.println("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		Serial.println("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(10);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	Serial.println("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MoveVelocity/MoveVelocity.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MoveVelocity/MoveVelocity.ino
new file mode 100644
index 000000000..9f831a13d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/MoveVelocity/MoveVelocity.ino	
@@ -0,0 +1,246 @@
+/*
+ * Title: MoveVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of a ClearPath motor in Step and
+ *    Direction mode, making velocity moves.
+ *
+ * Description:
+ *    This example enables a ClearPath then commands a series of repeating
+ *    velocity moves to the motor.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulse frequency sent by ClearCore to 
+ *    command the same frequency in motor encoder counts/sec, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveAtVelocity(int32_t velocity);
+void PrintAlerts();
+void HandleAlerts();
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if enabled
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Enabling may not have completed as expected. Proceed with caution.");		
+ 		Serial.println();
+	} else {
+		Serial.println("Motor Ready");	
+	}
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+        
+    // Move at 1,000 steps/sec for 2000ms
+    MoveAtVelocity(1000);
+    delay(2000);
+    // Move at -5,000 steps/sec for 2000ms
+    MoveAtVelocity(-5000);
+    delay(2000);
+    // Move at 10,000 steps/sec for 2000ms
+    MoveAtVelocity(10000);
+    delay(2000);
+    // Move at -10,000 steps/sec for 2000ms
+    MoveAtVelocity(-10000);
+    delay(2000);
+    // Command a 0 steps/sec velocity to stop motion for 2000ms
+    MoveAtVelocity(0);
+    delay(2000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveAtVelocity
+ *
+ *    Command the motor to move at the specified "velocity", in pulses/second.
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int velocity  - The velocity, in step pulses/sec, to command
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveAtVelocity(int velocity) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		Serial.println("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			Serial.println("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		Serial.println("Move canceled.");		
+		Serial.println();
+        return false;
+    }
+
+    Serial.print("Moving at velocity: ");
+    Serial.println(velocity);
+
+    // Command the velocity move
+    motor.MoveVelocity(velocity);
+
+    // Waits for the step command to ramp up/down to the commanded velocity. 
+    // This time will depend on your Acceleration Limit.
+    Serial.println("Ramping to speed...");
+    while (!motor.StatusReg().bit.AtTargetVelocity) {
+        continue;
+    }
+
+    Serial.println("At Speed");
+    return true; 
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	Serial.println("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		Serial.println("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		Serial.println("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		Serial.println("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		Serial.println("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		Serial.println("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		Serial.println("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		Serial.println("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(10);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	Serial.println("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/UserSeeksHome/UserSeeksHome.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/UserSeeksHome/UserSeeksHome.ino
new file mode 100644
index 000000000..e87e68a54
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/UserSeeksHome/UserSeeksHome.ino	
@@ -0,0 +1,175 @@
+/*
+ * Title: UserSeeksHome
+ *
+ * Objective:
+ *    This example demonstrates control of the "User Seeks Home" homing feature
+ *    of a ClearPath-SD motor (this feature is also available in ClearPath-MCPV
+ *    Pulse Burst Positioning Mode, but this example is only for Step and
+ *    Direction mode). "User Seeks Home" should be used when more flexibility is
+ *    required during a homing sequence (e.g. to move at multiple velocities,
+ *    stopping to perform other tasks, manually exiting a homing sequence, or
+ *    using sensor-based homing).
+ *
+ * Description:
+ *    This example enables the motor, moves towards a hardstop at a velocity for
+ *    2 seconds, then with a slower velocity until clamping into the hardstop.
+ *    An offset position move is then commanded away from the hardstop to
+ *    complete the homing sequence. Homing status is printed to the USB serial
+ *    port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have homing enabled and configured. To configure, look
+ *    under the "Homing" label on the MSP's main window, check the "Enabled"
+ *    radial button, then click the "Setup..." button. Set the Homing Style set
+ *    to "User seeks home; ClearPath ASG signals when homing is complete" then
+ *    hit the OK button.
+ * 5. A hardstop for homing must be installed on your mechanics. Set the homing
+ *    torque limit accordingly. This torque will be used to move toward and
+ *    clamp up against the hardstop.
+ *
+ * ** IMPORTANT: This examples homes in the Positive (CCW) direction, assuming
+ *    the hardstop is on the positive end of travel
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Selects the baud rate to match the target serial device
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity in step pulses/sec.
+    motor.VelMax(10000);
+    // Sets the maximum acceleration in step pulses/sec^2.
+    motor.AccelMax(100000);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Check if an alert would prevent motion
+    if (motor.StatusReg().bit.AlertsPresent) {
+        // In this case, we can't proceed with homing. Print the alert and bail.
+        Serial.println("Motor status: 'In Alert'. Move Canceled.");
+        // The end...
+        while (true) {
+            continue;
+        }
+    }
+
+    // Commands a speed of 5000 pulses/sec towards the hardstop for 2 seconds
+    Serial.println("Moving toward hardstop... Waiting for HLFB");
+    motor.MoveVelocity(5000);
+    delay(2000);
+    // Then slows down to 1000 pulses/sec until clamping into the hard stop
+    motor.MoveVelocity(1000);
+	
+	// Check if an alert occurred during motion
+    if (motor.StatusReg().bit.AlertsPresent) {
+        // In this case, we can't proceed with homing. Print the alert and bail.
+        Serial.println("Motor alert occurred during motion. Homing canceled.");
+        // The end...
+        while (true) {
+            continue;
+        }
+    }	
+
+
+    // Delay so HLFB has time to deassert
+    delay(10);
+    // Waits for HLFB to assert again, meaning the hardstop has been reached
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        if (motor.StatusReg().bit.AlertsPresent) {
+			// In this case, we can't proceed with homing. Print the alert and bail.
+			Serial.println("Motor alert detected. Homing canceled.");
+			// The end...
+			while (true) {
+				continue;
+			}
+		}
+    }
+
+    // Stop the velocity move now that the hardstop is reached
+    motor.MoveStopAbrupt();
+
+    // Move away from the hard stop. Any move away from the hardstop will
+    // conclude the homing sequence.
+    motor.Move(-1000);
+
+    // Delay so HLFB has time to deassert
+    delay(10);
+    // Waits for HLFB to assert, meaning homing is complete
+    Serial.println("Moving away from hardstop... Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+	
+	// Check if an alert occurred during offset move
+    if (motor.StatusReg().bit.AlertsPresent) {
+        // In this case, we can't proceed with homing. Print the alert and bail.
+        Serial.println("Motor alert occurred during offset move. Homing canceled.");
+        // The end...
+        while (true) {
+            continue;
+        }
+    } else {
+		Serial.println("Homing Complete. Motor Ready.");
+	}
+    // Zero the motor's reference position after homing to allow for accurate
+    // absolute position moves
+    motor.PositionRefSet(0);     
+}
+
+void loop() {
+    // This example doesn't have any ongoing tasks to perform.
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/library.properties
new file mode 100644
index 000000000..70fa0d360
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/ClearPath-SD Series/library.properties	
@@ -0,0 +1,9 @@
+name=ClearPath-SD Series
+version=0.0.1
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Library
+paragraph=Teknic ClearCore Library
+category=Device Control
+url=https://git-server.teknic.com/Git-Playground/clearcore-examples
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/AsgWithMeasuredTorque/AsgWithMeasuredTorque.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/AsgWithMeasuredTorque/AsgWithMeasuredTorque.ino
new file mode 100644
index 000000000..31c3995ba
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/AsgWithMeasuredTorque/AsgWithMeasuredTorque.ino	
@@ -0,0 +1,97 @@
+/*
+ * Title: AsgWithMeasuredTorque
+ *
+ * Objective:
+ *    This example demonstrates how to configure and read the High-Level
+ *    Feedback output mode "ASG-Position with Measured Torque" or "ASG-Velocity
+ *    with Measured Torque" from a ClearPath motor.
+ *
+ *    Note: There are two different versions of the ASG with Measured Torque
+ *    HLFB mode, one for Position modes and one for Velocity modes. See the
+ *    ClearPath MC/SD manual for a full description of all HLFB modes.
+ *
+ * Description:
+ *    This example reads the state of an attached ClearPath motor's HLFB output
+ *    in All Systems Go with Measured Torque mode. During operation, the state
+ *    of the HLFB is written to the USB serial port.
+ *
+ *    This example does not enable the motor or command any motion. Use the
+ *    Motion Generator in MSP to easily exercise the full features of this
+ *    example and see HLFB change state and give a torque measurement.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. To command motion, the connected ClearPath motor must be configured for
+ *    the Motion Generator mode through the MSP software (In MSP select Mode>>
+ *    Motion Generator).
+ * 3. The connected ClearPath motor must have its HLFB mode set to ASG with
+ *    measured torque through the MSP software (select Advanced>>High Level
+ *    Feedback [Mode]... then choose "ASG-Position, w/Measured Torque" or
+ *    "ASG-Velocity, w/ Measured Torque" and hit the OK button).
+ *    Select a 482 Hz PWM Carrier Frequency in this menu.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Put the motor connector into the HLFB mode to read bipolar PWM (the
+    // correct mode for ASG w/ Measured Torque)
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set up serial communication and wait up to 5 seconds for a port to open
+    // HLFB states are written to the serial port
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    Serial.print("HLFB state: ");
+
+    // Check the current state of the ClearPath's HLFB.
+    MotorDriver::HlfbStates hlfbState = motor.HlfbState();
+
+    // Write the HLFB state to the serial port
+    if (hlfbState == MotorDriver::HLFB_HAS_MEASUREMENT) {
+        // Writes the torque measured, as a percent of motor peak torque rating
+        Serial.print(int(round(motor.HlfbPercent())));
+        Serial.println("% torque");
+    }
+    else if (hlfbState == MotorDriver::HLFB_ASSERTED) {
+        // Asserted indicates either "Move Done" for position modes, or
+        // "At Target Velocity" for velocity moves
+        Serial.println("ASSERTED");
+    }
+    else {
+        Serial.println("DISABLED or SHUTDOWN");
+    }
+
+    // Wait before reading HLFB again
+    delay(500);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/SpeedOutput/SpeedOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/SpeedOutput/SpeedOutput.ino
new file mode 100644
index 000000000..50648d0c4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/SpeedOutput/SpeedOutput.ino	
@@ -0,0 +1,101 @@
+/*
+ * Title: SpeedOutput
+ *
+ * Objective:
+ *    This example demonstrates how to configure and read-in the High-Level
+ *    Feedback mode "Speed Output" of a ClearPath motor.
+ *
+ *    This HLFB mode is available in ClearPath-MC series servos, in every
+ *    ClearPath-MC operational mode except Ramp Up/Down to Selected Velocity.
+ *
+ * Description:
+ *    This example reads the state of an attached ClearPath motor's HLFB output
+ *    when configured for "Speed Output". During operation, the state of HLFB
+ *    and calculated measured speed are written to the USB serial port.
+ *
+ *    This example does not enable the motor or command motion. Use the
+ *    "Override Inputs" feature in MSP to command motion and see changes in the
+ *    HLFB measurement.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2.  The connected ClearPath motor must be configured through the MSP software
+ *    for an operational mode compatible with Speed Output HLFB mode (see above)
+ * 3. The connected ClearPath motor must have its HLFB mode set to "Speed Output"
+ *    (select Advanced>>High Level Feedback [Mode]... then choose "Speed Output"
+ *    from the dropdown and hit the OK button).
+ *    Select a 482 Hz PWM Carrier Frequency in this menu.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Put the motor connector into the correct HLFB mode to read the Speed
+    // Output PWM signal and convert it to percent of Max Speed.
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set up serial communication at a baud rate of baudRate (9600 bps) then
+    // wait up to 5 seconds for a port to open.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Use the MSP application to enable and move the motor. The duty cycle of
+    // the HFLB output will be refreshed and displayed every 0.5 seconds.
+
+    // Check the state of the HLFB.
+    MotorDriver::HlfbStates hlfbState = motor.HlfbState();
+
+    // Print the HLFB state.
+    if (hlfbState == MotorDriver::HLFB_HAS_MEASUREMENT) {
+        // Get the measured speed as a percent of Max Speed.
+        float hlfbPercent = motor.HlfbPercent();
+
+        Serial.print("Speed output: ");
+
+        if (hlfbPercent == MotorDriver::HLFB_DUTY_UNKNOWN) {
+            Serial.println("UNKNOWN");
+        }
+        else {
+            char hlfbPercentStr[10];
+            // Convert the floating point duty cycle into a string representation.
+            snprintf(hlfbPercentStr, sizeof(hlfbPercentStr), "%.0f%%", hlfbPercent);
+            Serial.print(hlfbPercentStr);
+            Serial.println(" of maximum speed");
+        }
+    }
+    else if (hlfbState == MotorDriver::HLFB_DEASSERTED) {
+        Serial.println("Disabled or Shutdown");
+    }
+
+    // Wait 0.5 secs before reading the HLFB again.
+    delay(500);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/library.properties
new file mode 100644
index 000000000..318ea6bf6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/High-Level Feedback (HLFB)/library.properties	
@@ -0,0 +1,9 @@
+name=High Level Feedback (HLFB)
+version=0.0.1
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Library
+paragraph=Teknic ClearCore Library
+category=Device Control
+url=https://git-server.teknic.com/Git-Playground/clearcore-examples
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/clearpath-mode-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/clearpath-mode-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/clearpath-mode-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/library.properties
new file mode 100644
index 000000000..6761c5958
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/ClearPathModeExamples/library.properties
@@ -0,0 +1,9 @@
+name=ClearPath Mode Examples
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore ClearPath Mode Examples
+paragraph=Teknic ClearCore ClearPath Mode Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/InputInterrupts/InputInterrupts.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/InputInterrupts/InputInterrupts.ino
new file mode 100644
index 000000000..df49cf423
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/InputInterrupts/InputInterrupts.ino
@@ -0,0 +1,107 @@
+/*
+ * Title: InputInterrupts
+ *
+ * Objective:
+ *    This example demonstrates how to configure a digital interrupt on a
+ *    ClearCore input.
+ *
+ * Description:
+ *    This example sets up and attaches a callback function to be triggered by
+ *    a digital interrupt. Interrupts are useful when a function needs to be
+ *    called asynchronously from the rest of the code's execution.
+ *
+ *    This example's interrupt blinks the on-board user LED when the interrupt
+ *    pin goes from on to off (aka "falling"). You may notice multiple blinks
+ *    depending on how much bounce the input device has.
+ *
+ *    The interrupt callback function's ability to run is turned on and off
+ *    periodically by this example. The callback function can only run when
+ *    interrupts are turned "on", regardless of the interrupt pin state. If the
+ *    interrupt pin is triggered while interrupts are "off", the callback will
+ *    execute when interrupts are next turned on. This on/off state is printed
+ *    to the USB serial port.
+ *
+ * Requirements:
+ * ** A digital signal source, such as a switch or sensor, connected to DI-6 to
+ *    trigger the interrupt
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Pins that support digital interrupts are:
+// DI-6, DI-7, DI-8, A-9, A-10, A-11, A-12
+#define interruptPin DI6
+
+// Declare the signature for our interrupt service routine (ISR). The function
+// is defined below
+void MyCallback();
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up the interrupt pin in digital input mode.
+    pinMode(interruptPin, INPUT);
+
+    // Set an ISR to be called when the state of the interrupt pin goes from
+    // true to false.
+    attachInterrupt(digitalPinToInterrupt(interruptPin), MyCallback, FALLING);
+
+    // Set up serial communication and wait up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run
+    Serial.begin(9600);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Enable digital interrupts.
+    interrupts();
+
+    Serial.println("Interrupts are turned on.");
+
+    // Test that the ISR is triggered when the state of the interrupt pin
+    // transitions from true to false by toggling your switch.
+
+    // Wait while the interrupt is triggered.
+    delay(5000);
+
+    // Disable digital interrupts.
+    noInterrupts();
+
+    Serial.println("Interrupts are turned off.");
+
+    // Test that the ISR does not get triggered when the state of the interrupt
+    // pin transitions from true to false by toggling your switch.
+    delay(5000);
+}
+
+// The function to be triggered on an interrupt.
+// This function blinks the user-controlled LED once.
+/*------------------------------------------------------------------------------
+ * MyCallback
+ *
+ *    Flashes the ClearCore's built-in LED (next to the USB port) on and off.
+ *
+ * Parameters:
+ *    None
+ *
+ * Returns: None
+ */
+void MyCallback() {
+    digitalWrite(LED_BUILTIN, true);
+    delay(100);
+    digitalWrite(LED_BUILTIN, false);
+    delay(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/PlayTone/PlayTone.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/PlayTone/PlayTone.ino
new file mode 100644
index 000000000..6fc20cad7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/PlayTone/PlayTone.ino
@@ -0,0 +1,69 @@
+/*
+ * Title: PlayTone
+ *
+ * Objective:
+ *    This example demonstrates how to play a sequence of tones on the
+ *    ClearCore's H-Bridge connectors using the musical frequency values defined
+ *    in the pitches.h header file.
+ *
+ * Description:
+ *    This example sets up an H-Bridge connector into output mode, sets the
+ *    volume, and plays a melodic sequence of tones of equal duration.
+ *
+ * Requirements:
+ * ** A speaker or other audio output device connected to IO-4
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "pitches.h"
+
+// Notes to be played in sequence as part of a melody.
+// The maximum tone frequency is 1/4 of the tone interrupt rate, i.e. 5512 Hz.
+// Any commanded frequency above 5512 Hz will get clipped to 5512 Hz.
+// See the "pitches.h" file for the frequency definitions of these notes
+const int melody[] = {NOTE_C4, NOTE_E4, NOTE_G4, NOTE_C5,
+                      NOTE_CS4, NOTE_FS4, NOTE_AS4, NOTE_CS5,
+                      NOTE_E4, NOTE_G4, NOTE_C5, NOTE_E5,
+                      NOTE_FS4, NOTE_AS4, NOTE_CS5, NOTE_FS5
+                     };
+const uint32_t noteCount = sizeof(melody) / sizeof(melody[0]);
+
+const uint32_t toneDuration = 200; // in milliseconds
+const float toneAmplitude = 0.01;  // max volume is 1
+
+// Tone output is supported on connectors IO-4 and IO-5 only
+#define tonePin IO4
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set the tone connector into output mode.
+    pinMode(tonePin, OUTPUT);
+
+    // Set the volume of the tone connector to the value specified
+    // by toneAmplitude.
+    toneVolume(tonePin, toneAmplitude);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Play the melody in order with equal note durations
+    for (int note = 0; note < noteCount; note++) {
+        tone(tonePin, melody[note]);
+        delay(toneDuration);
+    }
+
+    // Stop the tone generation
+    noTone(tonePin);
+
+    // Wait a second, then repeat...
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/PlayTone/pitches.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/PlayTone/pitches.h
new file mode 100644
index 000000000..9f16b4d6c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/PlayTone/pitches.h
@@ -0,0 +1,93 @@
+/*************************************************
+ * Public Constants
+ *************************************************/
+
+#define NOTE_B0  31
+#define NOTE_C1  33
+#define NOTE_CS1 35
+#define NOTE_D1  37
+#define NOTE_DS1 39
+#define NOTE_E1  41
+#define NOTE_F1  44
+#define NOTE_FS1 46
+#define NOTE_G1  49
+#define NOTE_GS1 52
+#define NOTE_A1  55
+#define NOTE_AS1 58
+#define NOTE_B1  62
+#define NOTE_C2  65
+#define NOTE_CS2 69
+#define NOTE_D2  73
+#define NOTE_DS2 78
+#define NOTE_E2  82
+#define NOTE_F2  87
+#define NOTE_FS2 93
+#define NOTE_G2  98
+#define NOTE_GS2 104
+#define NOTE_A2  110
+#define NOTE_AS2 117
+#define NOTE_B2  123
+#define NOTE_C3  131
+#define NOTE_CS3 139
+#define NOTE_D3  147
+#define NOTE_DS3 156
+#define NOTE_E3  165
+#define NOTE_F3  175
+#define NOTE_FS3 185
+#define NOTE_G3  196
+#define NOTE_GS3 208
+#define NOTE_A3  220
+#define NOTE_AS3 233
+#define NOTE_B3  247
+#define NOTE_C4  262
+#define NOTE_CS4 277
+#define NOTE_D4  294
+#define NOTE_DS4 311
+#define NOTE_E4  330
+#define NOTE_F4  349
+#define NOTE_FS4 370
+#define NOTE_G4  392
+#define NOTE_GS4 415
+#define NOTE_A4  440
+#define NOTE_AS4 466
+#define NOTE_B4  494
+#define NOTE_C5  523
+#define NOTE_CS5 554
+#define NOTE_D5  587
+#define NOTE_DS5 622
+#define NOTE_E5  659
+#define NOTE_F5  698
+#define NOTE_FS5 740
+#define NOTE_G5  784
+#define NOTE_GS5 831
+#define NOTE_A5  880
+#define NOTE_AS5 932
+#define NOTE_B5  988
+#define NOTE_C6  1047
+#define NOTE_CS6 1109
+#define NOTE_D6  1175
+#define NOTE_DS6 1245
+#define NOTE_E6  1319
+#define NOTE_F6  1397
+#define NOTE_FS6 1480
+#define NOTE_G6  1568
+#define NOTE_GS6 1661
+#define NOTE_A6  1760
+#define NOTE_AS6 1865
+#define NOTE_B6  1976
+#define NOTE_C7  2093
+#define NOTE_CS7 2217
+#define NOTE_D7  2349
+#define NOTE_DS7 2489
+#define NOTE_E7  2637
+#define NOTE_F7  2794
+#define NOTE_FS7 2960
+#define NOTE_G7  3136
+#define NOTE_GS7 3322
+#define NOTE_A7  3520
+#define NOTE_AS7 3729
+#define NOTE_B7  3951
+#define NOTE_C8  4186
+#define NOTE_CS8 4435
+#define NOTE_D8  4699
+#define NOTE_DS8 4978
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/ReadDigitalInput/ReadDigitalInput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/ReadDigitalInput/ReadDigitalInput.ino
new file mode 100644
index 000000000..1dc6eeabd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/ReadDigitalInput/ReadDigitalInput.ino
@@ -0,0 +1,68 @@
+/*
+ * Title: ReadDigitalInput
+ *
+ * Objective:
+ *    This example demonstrates how to read the state of a ClearCore digital
+ *    input.
+ *
+ * Description:
+ *    This example repeatedly reads the state of a defined digital input. During
+ *    operation, the state of the input is printed to the USB serial port.
+ *
+ * Requirements:
+ * ** A digital input device, such as a switch or sensor, connected to DI-6
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Specify which input pin to read from.
+// IO-0 through A-12 are all available as digital inputs.
+#define inputPin DI6
+
+// The current state of the input pin
+PinStatus state;
+
+// Select the baud rate to match the target serial device.
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    pinMode(inputPin, INPUT); // Set the pin as an INPUT
+    
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Read the state of the input connector.
+    state = digitalRead(inputPin);
+
+    // Display the state of the input connector.
+    Serial.print("DI-6 Input state: ");
+    if (state) {
+        Serial.println("ON");
+    }
+    else {
+        Serial.println("OFF");
+    }
+
+    // Wait a second then repeat...
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.ino
new file mode 100644
index 000000000..9f9d88158
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.ino
@@ -0,0 +1,80 @@
+/*
+ * Title: ReadDigitalInputRiseFall
+ *
+ * Objective:
+ *    This example demonstrates how to read the transition state (risen or
+ *    fallen since last checked) of a ClearCore digital input.
+ *
+ * Description:
+ *    This example repeatedly reads the transition state of a defined digital
+ *    input. Information on how the input state has transitioned is printed
+ *    to the USB serial port every 2 seconds.
+ *
+ * Requirements:
+ * ** An input device, such as a switch or sensor, connected to DI-6.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which input connector to use.
+// ConnectorIO0 through ConnectorA12 all have digital input capability.
+#define InputConnector ConnectorDI6
+
+// Declares two boolean variables used to hold information on whether the input
+// has risen or fallen
+bool risen, fallen;
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    pinMode(DI6, INPUT); //Set connector as an Input
+
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Check whether the digital input has risen, fallen, or is unchanged
+    // since the last time we checked.
+    risen = InputConnector.InputRisen();
+    fallen = InputConnector.InputFallen();
+
+    Serial.print("DI-6 Transitions: ");
+
+    if (risen && fallen) {
+        Serial.println("RISEN and FALLEN");
+    }
+    else if (risen) {
+        Serial.println("RISEN");
+    }
+    else if (fallen) {
+        Serial.println("FALLEN");
+    }
+    else {
+        Serial.println("NO CHANGE");
+    }
+
+    // Wait a couple seconds then repeat...
+    delay(2000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WriteDigitalOutput/WriteDigitalOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WriteDigitalOutput/WriteDigitalOutput.ino
new file mode 100644
index 000000000..df7969ca6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WriteDigitalOutput/WriteDigitalOutput.ino
@@ -0,0 +1,73 @@
+/*
+ * Title: WriteDigitalOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write the state of a ClearCore digital
+ *    output.
+ *
+ * Description:
+ *    This example repeatedly toggles the state of the ClearCore's six digital
+ *    outputs, IO-0 through IO-5.
+ *
+ * Requirements:
+ * ** A device that takes in a digital signal connected to any of the I/O's,
+ *    IO-0 through IO-5.
+ *      Note: You can leave the I/O points disconnected and still see the
+ *      built-in I/O LEDs toggle with the connector state.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Declares a variable used to write new states to the output. We will toggle
+// this true/false.
+bool outputState;
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Configure pins IO-0 through IO-5 as digital outputs. These are the only
+    // pins that support digital output mode.
+    pinMode(IO0, OUTPUT);
+    pinMode(IO1, OUTPUT);
+    pinMode(IO2, OUTPUT);
+    pinMode(IO3, OUTPUT);
+    pinMode(IO4, OUTPUT);
+    pinMode(IO5, OUTPUT);
+
+    // The connectors are all set up; start the loop with turning them all on.
+    outputState = true;
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Toggle the digital output state.
+    if (outputState) {
+        digitalWrite(IO0, true);
+        digitalWrite(IO1, true);
+        digitalWrite(IO2, true);
+        digitalWrite(IO3, true);
+        digitalWrite(IO4, true);
+        digitalWrite(IO5, true);
+    }
+    else {
+        digitalWrite(IO0, false);
+        digitalWrite(IO1, false);
+        digitalWrite(IO2, false);
+        digitalWrite(IO3, false);
+        digitalWrite(IO4, false);
+        digitalWrite(IO5, false);
+    }
+
+    // Toggle the state to write in the next loop.
+    outputState = !outputState;
+
+    // Wait a second, then repeat.
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WriteHBridgeOutput/WriteHBridgeOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WriteHBridgeOutput/WriteHBridgeOutput.ino
new file mode 100644
index 000000000..97318e3ff
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WriteHBridgeOutput/WriteHBridgeOutput.ino
@@ -0,0 +1,105 @@
+/*
+ * Title: WriteHBridgeOutput
+ *
+ * Objective:
+ *    This example demonstrates how to output a differential/bi-directional PWM
+ *    signal from a ClearCore H-Bridge connector.
+ *
+ * Description:
+ *    This example sets up a ClearCore H-Bridge connector for H-Bridge output,
+ *    then repeatedly ramps the PWM duty cycle output up and down, both sourcing
+ *    and sinking current.
+ *
+ * Requirements:
+ * ** A device capable of receiving an H-Bridge bi-directional PWM signal, like
+ *    a bi-directional brushed DC motor, connected to IO-4. Refer to the
+ *    ClearCore System Diagram on how to wire a device to the H-Bridge capable
+ *    connectors.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines which H-Bridge capable connector to use: ConnectorIO4 or ConnectorIO5
+#define HBridgeConnector ConnectorIO4
+
+// Declares our user-defined helper function, which is used to check for
+// overloads and reset the H-Bridge output as necessary. The definition/
+// implementation of this function is at the bottom of the example.
+void CheckHBridgeOverload();
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // H-Bridge output is supported on connectors IO-4 and IO-5 only.
+    // Set the H-Bridge connector into H-Bridge output mode.
+    HBridgeConnector.Mode(Connector::OUTPUT_H_BRIDGE);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Output bi-directional PWM on the H-Bridge connector over the full range
+    // of output values/duty cycles (-INT16_MAX-1 to INT16_MAX).
+
+    // Positive values (between 1 and INT16_MAX) will sink current into the
+    // signal pin.
+    // Negative values (between -1 and -INT16_MAX-1) will source current
+    // from the signal pin.
+
+    for (int16_t i = 0; i < INT16_MAX; i++) {
+        // Check for overloads and reset if needed
+        CheckHBridgeOverload();
+
+        // Write to the output.
+        HBridgeConnector.State(i);
+        delayMicroseconds(125);
+    }
+
+    for (int16_t i = 0; i < INT16_MAX; i++) {
+        CheckHBridgeOverload();
+
+        HBridgeConnector.State(INT16_MAX - i);
+        delayMicroseconds(125);
+    }
+
+    for (int16_t i = 0; i < INT16_MAX; i++) {
+        CheckHBridgeOverload();
+
+        HBridgeConnector.State(-i);
+        delayMicroseconds(125);
+    }
+
+    for (int16_t i = 0; i < INT16_MAX; i++) {
+        CheckHBridgeOverload();
+
+        HBridgeConnector.State(-INT16_MAX + i);
+        delayMicroseconds(125);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * CheckHBridgeOverload
+ *
+ *    Checks whether any of the ClearCore's H-Bridge connectors are experiencing
+ *    an overload. If an overload is detected the H-Bridge connectors are reset.
+ *
+ * Parameters:
+ *    None
+ *
+ * Returns: None
+ */
+void CheckHBridgeOverload() {
+    if (StatusMgr.StatusRT().bit.HBridgeOverloaded) {
+        StatusMgr.HBridgeReset();
+        delay(10);
+    }
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WritePwmOutput/WritePwmOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WritePwmOutput/WritePwmOutput.ino
new file mode 100644
index 000000000..fb49daf6a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/WritePwmOutput/WritePwmOutput.ino
@@ -0,0 +1,57 @@
+/*
+ * Title: WritePwmOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write a digital PWM signal to a ClearCore
+ *    digital output.
+ *
+ * Description:
+ *    This example sets the defined pin as an output then writes a series of
+ *    PWM signals with varying duty cycles to the output.
+ *
+ * Requirements:
+ * ** Connect a device that takes in a PWM signal to IO-1.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Specify which output pin to write digital PWM to.
+// PWM-capable pins: IO-0 through IO-5.
+// Note: IO-4 and IO-5 are capable of bi-directional and higher-current PWM
+//       output using an H-Bridge. See the WriteHBridgeOutput example.
+#define outputPin IO1
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up the output pin to be an output.
+    pinMode(outputPin, OUTPUT);
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Write some digital PWM signals to the output connector.
+    // Note: analogWrite() is the Arduino wrapper function used to write PWM,
+    // despite the fact that it is not a "true" analog signal.
+    // Valid values range from 0 (0% duty cycle / always off)
+    // to 255 (100% duty cycle / always on).
+
+    // Output a low duty cycle for 1 second.
+    analogWrite(outputPin, 10);
+    delay(1000);
+
+    // Output a medium duty cycle for 1 second.
+    analogWrite(outputPin, 120);
+    delay(1000);
+
+    // Output a high duty cycle for 1 second.
+    analogWrite(outputPin, 230);
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/digitalIO-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/digitalIO-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/digitalIO-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/library.properties
new file mode 100644
index 000000000..803364c39
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/DigitalIO/library.properties
@@ -0,0 +1,9 @@
+name=Digital I/O
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Digital I/O Examples
+paragraph=Teknic ClearCore Digital I/O Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/FollowEncoder/FollowEncoder.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/FollowEncoder/FollowEncoder.ino
new file mode 100644
index 000000000..a1dfcae78
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/FollowEncoder/FollowEncoder.ino
@@ -0,0 +1,178 @@
+/*
+ * Title: FollowEncoder
+ *
+ * Objective:
+ *    This example demonstrates the ClearCore's Encoder Input module
+ *    functionality.
+ *
+ * Description:
+ *    This example takes input signals from an external encoder through the 
+ *    CL-ENCRD-DFIN Encoder Adapter Board, and uses the encoder position
+ *    or velocity to control a ClearPath-SD servo.
+ *
+ * Requirements:
+ * 1. A ClearPath-SD motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ * 5. An external encoder much be wired to the CL-ENCRD-DFIN Encoder Adapter Board, 
+ *    and the board connected to the ClearCore I/O Header. See the ClearCore User 
+ *    Manaual for connector pinouts.
+ *
+ * ** Reminder: When using the CL-ENCRD-DFIN Encoder Adapter Board, ClearCore 
+ *    connectors DI-6, DI-7, and DI-8 are unavailable and should be left Not  
+ *    Connected to any external device.
+ *
+ * ** Note: Homing is optional and not required in this operational mode or in
+ *    this example.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+
+// Set the operational mode of this example:
+// If true, the motor will faithfully follow the encoder's position.
+// If false, the motor will faithfully follow the encoder's velocity instead.
+bool followPosition = false;
+
+// Define the velocity and acceleration limits to be used for positional moves
+int32_t velocityLimit = 100000; // pulses per sec
+int32_t accelerationLimit = 1000000; // pulses per sec^2
+
+// Set to true if the sense of encoder direction should be inverted.
+bool swapDirection = false;
+// Set to true if index detection should occur on the falling edge,
+// rather than the rising edge.
+bool indexInverted = false;
+
+// Variables for printing info to the serial port
+char info[100];
+uint32_t timeout;
+uint32_t startTime;
+
+// Variables to store encoder state
+int32_t position = 0;
+int32_t velocity = 0;
+int32_t indexPosition = 0;
+int32_t lastIndexPosition = 0;
+bool quadratureError = false;
+
+void setup() {
+    // Set up serial communication and wait up to 5 seconds for a port to open
+    timeout = 5000;
+    startTime = millis();
+    Serial.begin(9600);
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enable the encoder input feature
+    EncoderIn.Enable(true);
+    // Zero the position to start
+    EncoderIn.Position(0);
+    // Set the encoder direction
+    EncoderIn.SwapDirection(swapDirection);
+    // Set the sense of index detection (true = rising edge, false = falling edge)
+    EncoderIn.IndexInverted(indexInverted);
+
+    // Motor setup:
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL, Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    ConnectorM0.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    ConnectorM0.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set velocity and acceleration limits for each move
+    ConnectorM0.VelMax(velocityLimit);
+    ConnectorM0.AccelMax(accelerationLimit);
+
+    // Enables the motor; homing will begin automatically if enabled
+    ConnectorM0.EnableRequest(true);
+    Serial.println("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    Serial.println("Waiting for HLFB...");
+    while (ConnectorM0.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+    Serial.println("Motor Ready");
+
+    // Use a timeout to print out encoder information every 500 ms.
+    timeout = 500;
+    startTime = millis();
+}
+
+void loop() {
+    position = EncoderIn.Position();
+    velocity = EncoderIn.Velocity();
+    indexPosition = EncoderIn.IndexPosition();
+    quadratureError = EncoderIn.QuadratureError();
+
+    // Print out encoder info at a fixed timeout rate
+    if (millis() - startTime >= timeout) {
+        if (followPosition) {
+            snprintf(info, 100, "Encoder position: %ld counts", position);
+        }
+        else {
+            snprintf(info, 100, "Encoder velocity: %ld counts/sec", velocity);
+        }
+        Serial.println(info);
+        startTime = millis();
+    }
+
+    if (indexPosition != lastIndexPosition) {
+        snprintf(info, 100, "Detected index at position: %ld",
+        EncoderIn.IndexPosition());
+        Serial.println(info);
+    }
+
+    lastIndexPosition = indexPosition;
+
+    // Check if an alert is currently preventing motion
+    if (ConnectorM0.StatusReg().bit.AlertsPresent) {
+        Serial.println("Motor status: 'In Alert'. Move Canceled.");
+        return;
+    }
+
+    if (followPosition) {
+        // Move the motor to the current position read by the encoder
+        ConnectorM0.Move(position, MotorDriver::MOVE_TARGET_ABSOLUTE);
+    }
+    else {
+        // Command the motor to follow the encoder's velocity
+        ConnectorM0.MoveVelocity(velocity);
+    }
+    
+    if (quadratureError) {
+         // We detected a quadrature error!
+        ConnectorM0.MoveVelocity(0);
+        ConnectorM0.EnableRequest(false);
+        Serial.println("Quadrature error detected. Stopping motion...");
+        
+        while (true) {
+            // End of sketch
+            continue;
+        }
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/encoder-input-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/encoder-input-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/encoder-input-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/library.properties
new file mode 100644
index 000000000..095de76ec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/EncoderInput/library.properties
@@ -0,0 +1,9 @@
+name=Encoder Input
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Encoder Input Examples
+paragraph=Teknic ClearCore Encoder Input Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPClientHelloWorld/EthernetTCPClientHelloWorld.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPClientHelloWorld/EthernetTCPClientHelloWorld.ino
new file mode 100644
index 000000000..8e5cc5813
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPClientHelloWorld/EthernetTCPClientHelloWorld.ino
@@ -0,0 +1,182 @@
+/*
+ * Title: EthernetTcpClientHelloWorld   
+ *
+ * Objective:
+ *    This example demonstrates how to configure a ClearCore as a TCP client to 
+ *    send and receive TCP datagrams (packets).
+ *
+ * Description:
+ *    This example configures a ClearCore device to act as a TCP client. This client 
+ *    connects to another device acting as a TCP server to exchange data over 
+ *    ethernet TCP. This simple example connects to a server, sends a simple "Hello server"
+ *    message, and receives and prints incoming data from the server.
+ *
+ *    Partner projects, EthernetTcpServer_autoClientManagement and EthernetTcpServer_manualClientManagement 
+ *    are available to configure another ClearCore to act as a server.
+ *
+ * Setup:
+ * 1. Identify the IP address of the server and specify it (as serverIp) below. If 
+ *    using either EthernetTcpServer example, the server IP will print to a 
+ *    connected serial terminal on startup.
+ * 2. Set the usingDhcp boolean as appropriate. If not using DHCP, specify static 
+ *    IP and network information.
+ * 3. Ensure the server and client are connected to communicate on the same network.
+ *    If both devices are directly connected (as opposed to going through a switch)
+ *    an ethernet crossover cable may be required. 
+ * 4. It may be helpful to use another application to view serial output from 
+ *    each device. PuTTY is one such application: https://www.putty.org/
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * 
+ * Copyright (c) 2022 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */ 
+
+#include <SPI.h>
+#include <Ethernet.h>
+
+
+// MAC address of the ClearCore
+byte mac[] = {};
+
+// The IP address of the server to which to connect
+IPAddress serverIp = IPAddress(192, 168, 2, 109);
+
+// The port number on the server over which packets will be sent/received
+#define PORT_NUM 8888
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets.
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+
+// Set usingDhcp to false to use user defined network settings
+bool usingDhcp = true;
+
+// Initialize a client object
+// The ClearCore will operate as a TCP client using this object
+EthernetClient client;
+  
+void setup(){
+  // Set up serial communication between ClearCore and PC serial terminal
+  Serial.begin(9600);
+  uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+  
+  // Set connector IO0 as a digital output
+  // When IO0 state is true, a LED will light on the
+  // ClearCore indicating a successful connection to a server 
+  pinMode(IO0, OUTPUT);
+
+  // Make sure the physical link is active before continuing
+  while (Ethernet.linkStatus() == LinkOFF) {
+    Serial.println("The Ethernet cable is unplugged...");
+    delay(1000);
+  }
+  
+  // Configure with an IP address assigned via DHCP
+  if (usingDhcp) {
+    // Use DHCP to configure the local IP address
+    bool dhcpSuccess = Ethernet.begin(mac);
+    if (dhcpSuccess) {
+      Serial.print("DHCP successfully assigned an IP address: ");
+      Serial.println(Ethernet.localIP());
+    } else {
+      Serial.println("DHCP configuration was unsuccessful!");
+      while (true) {
+        // TCP will not work without a configured IP address
+        continue;
+      }
+    }
+  } else {
+    // Configure with a manually assigned IP address
+    // ClearCore MAC address
+    byte mac[] = {0xDE, 0xAD, 0xBE, 0xEF, 0xFE, 0xED};
+    //  ClearCore IP address:
+    IPAddress ip(192, 168, 0, 103);
+
+    // Set ClearCore's IP address
+    Ethernet.begin(mac, ip);
+    Serial.print("Assigned manual IP address: ");
+    Serial.println(Ethernet.localIP());
+    
+    //Optionally, set additional network addresses if needed
+
+    //IpAddress myDns = myDns(192, 168, 1, 1);
+    //IpAddress gateway = gateway(192, 168, 1, 1);
+    //IpAddress netmask = subnetress(255, 255, 255, 0);
+
+    //Ehternet.begin(mac, ip, myDns, gateway, subnet);
+  }
+    // Attempt to connect to a server
+    if (!client.connect(serverIp, PORT_NUM)) {
+         Serial.println("Failed to connect to server. Retrying...");
+        }
+}  
+      
+  uint32_t startTime = millis();
+  // Connect to server, and send/receive packets
+  void loop(){
+    
+    // Make sure the physical link is active before continuing
+    while (!Ethernet.linkStatus() == LinkOFF) {
+      Serial.println("The Ethernet cable is unplugged...");
+    }
+    
+    // Attempt to connect to server
+    if(!client.connected()){
+      // Turn off LED if the client is not connected
+      //ConnectorIO0.State(false); 
+      digitalWrite(IO0, false); 
+      
+      uint32_t connectionDelay = 1000;
+      if (!client.connect(serverIp, PORT_NUM)) {
+        if(millis() - startTime > connectionDelay){
+          Serial.println("Failed to connect to server. Retrying...");
+          startTime = millis();
+        }
+      }
+    } else {
+      // Turn on LED if client is connected
+      digitalWrite(IO0, true);
+      
+      // If connection was successful, send and receive packets
+      if( client.write("Hello server") >0)
+      {
+        Serial.print("Sent 'Hello server'. Response from server: ");
+        bool receivedMessage = false;
+        
+        // Read any incoming packets from the server over the next second
+        uint32_t readDelay = 1000;
+        uint32_t startTime = millis();
+        while((millis() - startTime) < readDelay){
+          if (client.read(packetReceived, MAX_PACKET_LENGTH) > 0)
+          {
+            receivedMessage = true;
+            Serial.print((char *)packetReceived);
+            
+            // Clear the message buffer for the next iteration of the loop
+            for(int i=0; i<MAX_PACKET_LENGTH; i++){
+              packetReceived[i]=NULL;
+            }
+          }
+        }
+        // If no packets were received, inform the user via serial message
+        if (!receivedMessage){
+          Serial.println("Didn't receive message.");
+        }else{
+          Serial.println();
+        }
+      }
+      else
+      {
+        Serial.println("Hit client.stop()");
+        client.stop();
+      }
+    }
+  }
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPServer_autoClientManagement/EthernetTCPServer_autoClientManagement.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPServer_autoClientManagement/EthernetTCPServer_autoClientManagement.ino
new file mode 100644
index 000000000..c0915a5be
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPServer_autoClientManagement/EthernetTCPServer_autoClientManagement.ino
@@ -0,0 +1,186 @@
+/*
+ * Title: EthernetTCPServer_autoClientManagement
+ *
+ * Objective:
+ *    This example demonstrates how to configure a ClearCore as a TCP server to 
+ *    send and receive TCP datagrams (packets). 
+ *    
+ * Description:
+ *    This example configures a ClearCore device to act as a TCP server. 
+ *    This server can receive connections from another device acting as a TCP 
+ *    client to exchange data over ethernet TCP. 
+ *    This simple example accepts connection requests from clients, receives and
+ *    prints incoming data from connected devices, and sends a simple "Hello 
+ *    client" response.
+ *    A partner project, EthernetTcpClientHelloWorld, is available to configure 
+ *    another ClearCore as a client.
+ *
+ * Setup:
+ * 1. Set the usingDhcp boolean as appropriate. If not using DHCP, specify static 
+ *    IP and network information.
+ * 2. Ensure the server and client are connected to communicate on the same network.
+ *    If both devices are directly connected (as opposed to going through a switch)
+ *    a ethernet crossover cable may be required. 
+ * 3. It may be helpful to use another application to view serial output from 
+ *    each device. PuTTY is one such application: https://www.putty.org/
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * 
+ * Copyright (c) 2022 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include <SPI.h>
+#include <Ethernet.h>
+
+// MAC address of the ClearCore
+byte mac[] = {};
+
+// The port number on the server over which packets will be sent/received 
+#define PORT_NUM 8888
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+
+// Set usingDhcp to false to use user defined network settings
+bool usingDhcp = true;
+
+// Initialize the ClearCore as a server listening for incoming 
+// client connections on specified port (8888 by default)
+EthernetServer server = EthernetServer(PORT_NUM);
+  
+// Initialize a client object
+// This object will hold a connected clients information 
+// allowing the server to interact with the client 
+EthernetClient client;
+  
+void setup(){
+  // Set up serial communication between ClearCore and PC serial terminal 
+  Serial.begin(9600);
+  uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+  // Set connector IO0 as a digital output
+  // When IO0 state is true, a LED will light on the
+  // ClearCore indicating a successful connection to a client
+  pinMode(IO0, OUTPUT);
+  
+  // Make sure the physical link is active before continuing
+  while (Ethernet.linkStatus() == LinkOFF) {
+    Serial.println("The Ethernet cable is unplugged...");
+    delay(1000);
+  }
+  
+  // To configure with an IP address assigned via DHCP
+  if (usingDhcp) {
+    // Use DHCP to configure the local IP address
+    bool dhcpSuccess = Ethernet.begin(mac);
+    if (dhcpSuccess) {
+      Serial.print("DHCP successfully assigned an IP address: ");
+      Serial.println(Ethernet.localIP());
+    }
+    else {
+      Serial.println("DHCP configuration was unsuccessful!");
+      while (true) {
+        // TCP will not work without a configured IP address
+        continue;
+      }
+    }
+  } else {
+    // Configure with a manually assigned IP address
+    
+    // ClearCore MAC address
+    byte mac[] = {0xDE, 0xAD, 0xBE, 0xEF, 0xFE, 0xED};
+    
+    // Set ClearCore's IP address
+    IPAddress ip = IPAddress(192, 168, 0, 100);
+    Ethernet.begin(mac, ip);
+    Serial.print("Assigned manual IP address: ");
+    Serial.println(Ethernet.localIP());
+    
+    // Optionally set additional network addresses if needed
+    
+    //IpAddress myDns = myDns(192, 168, 1, 1);
+    //IpAddress gateway = gateway(192, 168, 1, 1);
+    //IpAddress netmask = subnetress(255, 255, 255, 0);
+
+    //Ehternet.begin(mac, ip, myDns, gateway, subnet);
+  }
+
+  // Start listening for TCP connections
+  server.begin();
+
+  Serial.println("Server now listening for client connections...");
+}
+
+uint32_t startTime = millis();
+// Connect to clients, and send/receive packets
+void loop(){
+    // Obtain a reference to a connected client with incoming data available
+    // This function will only return a valid reference if the connected device has 
+    // data available to read
+    client = server.available();
+    
+    // Check if the server has returned a connected client with incoming data available
+    if (client.connected()) {
+      // Flash on LED if a client has sent a message
+      digitalWrite(IO0, true);
+      
+      // Delay to allow user to see the LED
+      // This example will flash the LED each time a message from a client is received
+      delay(100); 
+      
+      // Read packet from the client
+      Serial.print("Read the following from the client: ");
+      while (client.available() > 0) {
+        int lengthOfMessage = client.available();
+        for(int i=0; i < lengthOfMessage && i != 100; i++){ 
+          char currentChar = client.read();
+          packetReceived[i] = currentChar;
+        }
+        // Send the data received from the client over a serial port
+        Serial.print((char *)packetReceived);
+        
+        // Clear the message buffer for the next iteration of the loop
+        for(int i=0; i<MAX_PACKET_LENGTH; i++){
+          packetReceived[i]=NULL;
+        }
+      }
+      Serial.println();
+      
+      // Send response message to client
+      if (client.write("Hello client ")>0){
+        Serial.println("Sent 'Hello Client' response");
+      }
+      else{
+        Serial.println("Unable to send reply");
+      }
+    } else{
+      // Turn off LED if a message has not been received
+      digitalWrite(IO0, false);
+
+      //Not sure how to impliment in arduino
+      //if(client.ConnectionState()->state == CLOSING){
+        //client.stop();
+      //}
+      client.stop();
+      int connectionDelay = 1000;
+      if(Ethernet.linkStatus() == LinkON && (millis() - startTime > connectionDelay)){
+        //Serial.println(client.ConnectionState()->state);
+        Serial.println("client.connected returned false and ethernet link is active");
+        startTime = millis();
+      }
+      // Make sure the physical link is active before continuing
+      while (Ethernet.linkStatus() == LinkOFF) {
+        Serial.println("The Ethernet cable is unplugged...");
+        delay(1000);
+      }
+    }
+  }
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPServer_manualClientManagement/EthernetTCPServer_manualClientManagement.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPServer_manualClientManagement/EthernetTCPServer_manualClientManagement.ino
new file mode 100644
index 000000000..9ad5c5aef
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetTCPServer_manualClientManagement/EthernetTCPServer_manualClientManagement.ino
@@ -0,0 +1,253 @@
+/*
+ * Title: EthernetTCPServer_manualClientManagement 
+ *
+ * Objective:
+ *    This example demonstrates how to configure a ClearCore as a TCP server to 
+ *    send and receive TCP datagrams (packets).
+ *    
+ * Description:
+ *    This example configures a ClearCore device to act as a TCP server. 
+ *    This server can receive connections from several other devices acting as TCP 
+ *    clients to exchange data over ethernet TCP. 
+ *    This simple example accepts connection requests from clients, checks for
+ *    incoming data from connected devices, and sends a simple "Hello 
+ *    client" response.
+ *    A partner project, EthernetTcpClientHelloWorld, is available to configure 
+ *    another ClearCore as a client.  
+ *
+ * Setup:
+ * 1. Set the usingDhcp boolean as appropriate. If not using DHCP, specify static 
+ *    IP and network information.
+ * 2. Ensure the server and client are setup to communicate on the same network.
+ *    If both devices are directly connected (as opposed to going through a switch)
+ *    a ethernet crossover cable may be required. 
+ * 3. It may be helpful to use another application to view serial output from 
+ *    each device. PuTTY is one such application: https://www.putty.org/
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * 
+ * Copyright (c) 2022 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+//#include <ClearCore.h>
+#include <SPI.h>
+#include <Ethernet.h>
+
+
+
+// MAC address of the ClearCore
+byte mac[] = {};
+
+// The port number on the server over which packets will be sent/received 
+#define PORT_NUM 8888
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+// Buffer for holding packets to send
+char packetToSend[MAX_PACKET_LENGTH]; 
+
+// Set total number of clients the server will accept
+#define NUMBER_OF_CLIENTS 6
+
+// Set usingDhcp to false to use user defined network settings
+bool usingDhcp = true;
+
+// Initialize the ClearCore as a server 
+// Clients connect on specified port (8888 by default)
+EthernetServer server = EthernetServer(PORT_NUM);
+  
+// Initialize an array of clients
+// This array holds the information of any client which
+// is currently connected to the server and is used by the
+// server to interact with these clients
+EthernetClient clients[NUMBER_OF_CLIENTS];
+// Initialize an temporary client for client management
+EthernetClient tempClient;
+  
+// Array of output LEDs to indicate client connections
+// NOTE: only connectors IO0 through IO5 can be configured as digital outputs (LEDs) 
+pin_size_t outputLEDs[6] = {
+  IO0, IO1, IO2, IO3, IO4, IO5
+};
+
+
+void setup() {
+  // Set up serial communication between ClearCore and PC serial terminal 
+  Serial.begin(9600);
+  uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+  // Set connectors IO0-IO5 as a digital outputs 
+  // When an outputLEDs state is true, a LED will light on the
+  // ClearCore indicating a successful connection to a client
+  for(int i=0; i<6; i++){
+  pinMode(outputLEDs[i], OUTPUT);
+  }
+  
+  // Make sure the physical link is active before continuing
+  while (Ethernet.linkStatus() == LinkOFF) {
+    Serial.println("The Ethernet cable is unplugged...");
+    delay(1000);
+  }
+  
+  //To configure with an IP address assigned via DHCP
+  if (usingDhcp) {
+    // Use DHCP to configure the local IP address
+    bool dhcpSuccess = Ethernet.begin(mac);
+    if (dhcpSuccess) {
+      Serial.print("DHCP successfully assigned an IP address: ");
+      Serial.println(Ethernet.localIP());
+    }
+    else {
+      Serial.println("DHCP configuration was unsuccessful!");
+      while (true) {
+        // TCP will not work without a configured IP address
+        continue;
+      }
+    }
+  } else {
+    // Configure with a manually assigned IP address
+    
+    // Set ClearCore's IP address
+    IPAddress ip = IPAddress(192, 168, 0, 100);
+    Ethernet.begin(mac, ip);
+    Serial.print("Assigned manual IP address: ");
+    Serial.println(Ethernet.localIP());
+    
+    
+    // Optionally set additional network addresses if needed
+    
+    //IpAddress myDns = myDns(192, 168, 1, 1);
+    //IpAddress gateway = gateway(192, 168, 1, 1);
+    //IpAddress netmask = subnetress(255, 255, 255, 0);
+
+    //Ehternet.begin(mac, ip, myDns, gateway, subnet);
+  }
+
+  // Start listening for TCP connections
+  server.begin();
+
+  Serial.println("Server now listening for client connections...");
+}
+
+  bool newClient = 0;
+  
+  // Resets a timmer used to display a list of connected clients
+  uint32_t startTime = 0;
+  
+  // Connect to clients, and send/receive packets
+void loop(){
+    
+    // Obtain a reference to a connected client
+    // This function returns a specific client once per connection attempt
+    // To maintain a connection with a client using Accept() 
+    // some basic client management must be performed
+    tempClient = server.accept();
+    
+    // Checks if server.Accept() has returned a new client
+    if(tempClient.connected()){
+      newClient = 1; 
+      
+      for(int i=0; i<NUMBER_OF_CLIENTS; i++){
+        //Checks for an available location to store a new client
+        if(!clients[i].connected()){
+          clients[i].stop();
+          clients[i] = tempClient;
+          Serial.print(clients[i].remoteIP());
+          Serial.println(" has been connected");
+          newClient = 0;
+          break;
+        }
+      }
+      // Rejects client if the client list is full 
+      if(newClient == 1){
+        newClient = 0;
+        tempClient.write("This server has reached its max number of clients. Closing connection.");
+        Serial.println("This server has reached its max number of clients. Closing connection.");
+        tempClient.stop();
+      }
+    }
+    
+    // Loops through list of clients to receive/send messages
+    for(int i=0; i<NUMBER_OF_CLIENTS; i++){
+      if (clients[i].connected()) {
+        
+        // Indicate connection on corresponding output LED
+        digitalWrite(outputLEDs[i], true);
+        
+        // Check if client has incoming data available  
+        if(clients[i].available()){
+          Serial.print("Read the following from the client(");
+          Serial.print(clients[i].remoteIP());
+          Serial.print("): ");
+          // Read packet from the client
+          while (clients[i].available()) {
+            // Send the data received from the client over a serial port
+            clients[i].read(packetReceived, MAX_PACKET_LENGTH);
+            Serial.print((char *)packetReceived);
+            // Clear the message buffer for the next iteration of the loop
+            for(int i=0; i<MAX_PACKET_LENGTH; i++){
+              packetReceived[i]=NULL;
+            }
+          }
+          Serial.println();
+          
+          //Sends unique response to the client
+          if(clients[i].write("Hello client ") == 0){
+            // If the message was unable to send close the client connection
+            clients[i].stop();
+            Serial.print("Client ("); 
+            Serial.print(clients[i].remoteIP());
+            Serial.print(") has been removed from client list. ");
+            clients[i] = EthernetClient();
+            
+            // Indicate loss of connection by turning off corresponding LED
+            digitalWrite(outputLEDs[i], false);
+          }
+
+        }
+        
+      } else{
+        // Removes any disconnected clients
+        if(clients[i].remoteIP() != IPAddress(0,0,0,0)){
+          Serial.print("Client (");
+          Serial.print(clients[i].remoteIP());
+          Serial.print(") has been removed from client list. ");
+          clients[i].stop();
+          clients[i] = EthernetClient();
+
+          // Indicate loss of connection by turning off corresponding LED
+          digitalWrite(outputLEDs[i], false);
+        }
+      }
+    }
+    
+    // Make sure the physical link is active before continuing
+    while (Ethernet.linkStatus() == LinkOFF) {
+      Serial.println("The Ethernet cable is unplugged...");
+      delay(1000);
+    }
+    
+    // Print out a list of current clients
+    int delay = 5000;
+    if(millis()- startTime > delay){
+      Serial.println("List of current clients: ");
+      for(int i=0; i<NUMBER_OF_CLIENTS; i++){
+        if(clients[i].remoteIP() != IPAddress(0,0,0,0)){
+          Serial.print("Client ");
+          Serial.print(i);
+          Serial.print(" = ");
+          Serial.println(clients[i].remoteIP());
+        }
+      }
+      startTime = millis();
+    }
+  }
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetUdpHelloWorld/EthernetUdpHelloWorld.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetUdpHelloWorld/EthernetUdpHelloWorld.ino
new file mode 100644
index 000000000..1595f2309
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/EthernetUdpHelloWorld/EthernetUdpHelloWorld.ino
@@ -0,0 +1,231 @@
+/*
+ * Title: EthernetUdpHelloWorld
+ *
+ * Objective:
+ *    This example demonstrates how to enable Ethernet functionality to send and
+ *    receive UDP datagrams (packets).
+ *
+ * Description:
+ *    This example will set up ethernet communications between a ClearCore and
+ *    another Ethernet source (a PC or ClearCore). The example then prints the
+ *    contents of the packets received to the specified serial port and sends
+ *    a "Hello World" response to the sender.
+ *
+ * Requirements:
+ * ** Setup 1 (ClearCore and a PC): The PC should be running software capable
+ *    of sending and receiving UDP packets. PacketSender is highly recommended
+ *    as a free, cross-platform software. Configure PacketSender to send a UDP
+ *    packet to the ClearCore by specifying the IP address and port provided to
+ *    Ethernet.begin(). Your firewall or network settings may need to be
+ *    adjusted in order to receive the response back from the ClearCore.
+ * ** Setup 2 (ClearCore to a ClearCore): A partner sketch is included at the
+ *    end of this file that can be used on the other ClearCore. The MAC address
+ *    and IP address values set up for each ClearCore must be unique. The remote
+ *    IP address and port used in the partner sketch must match the IP address
+ *    and port used to setup the ClearCore in this sketch.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include <Ethernet.h>
+
+// Change the MAC address and IP address below to match your ClearCore's
+// MAC address and IP.
+byte mac[] = {0xDE, 0xAD, 0xBE, 0xEF, 0xFE, 0xED};
+IPAddress ip(192, 168, 1, 177);
+
+// The local port to listen for connections on.
+unsigned int localPort = 8888;
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets.
+char packetReceived[MAX_PACKET_LENGTH];
+
+// An EthernetUDP instance to let us send and receive packets over UDP
+EthernetUDP Udp;
+
+// Set this false if not using DHCP to configure the local IP address.
+bool usingDhcp = true;
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    Serial.begin(9600);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Get the Ethernet module up and running.
+    if (usingDhcp) {
+        int dhcpSuccess = Ethernet.begin(mac);
+        if (dhcpSuccess) {
+            Serial.println("DHCP configuration was successful.");
+        }
+        else {
+            Serial.println("DHCP configuration was unsuccessful!");
+            Serial.println("Try again using a manual configuration...");
+            while (true) {
+                // UDP will not work without a configured IP address.
+                continue;
+            }
+        }
+    }
+    else {
+        Ethernet.begin(mac, ip);
+    }
+
+    // Make sure the physical link is up before continuing.
+    while (Ethernet.linkStatus() == LinkOFF) {
+        Serial.println("The Ethernet cable is unplugged...");
+        delay(1000);
+    }
+
+    // Begin listening on the local port for UDP datagrams
+    Udp.begin(localPort);
+}
+
+// This loop will wait to receive a packet from a remote source, then reply back
+// with a packet containing a "Hello, world!" message.
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Look for a received packet.
+    int packetSize = Udp.parsePacket();
+
+    if (packetSize > 0) {
+        Serial.print("Received packet of size ");
+        Serial.print(packetSize);
+        Serial.println(" bytes.");
+
+        Serial.print("Remote IP: ");
+
+        IPAddress remote = Udp.remoteIP();
+        for (int i = 0; i < 4; i++) {
+            if (i < 3) {
+                Serial.print(remote[i], DEC);
+                Serial.print(".");
+            }
+            else {
+                Serial.println(remote[i], DEC);
+            }
+        }
+        Serial.print("Remote port: ");
+        Serial.println(Udp.remotePort());
+
+        // Read the packet.
+        int bytesRead = Udp.read(packetReceived, MAX_PACKET_LENGTH);
+        Serial.print("Packet contents: ");
+        Serial.write(packetReceived, bytesRead);
+        Serial.println();
+
+        // Send a "Hello, world!" reply packet back to the sender.
+        Udp.beginPacket(Udp.remoteIP(), Udp.remotePort());
+        Udp.write("Hello, world!");
+        Udp.endPacket();
+    }
+
+    delay(10);
+}
+
+
+/*
+
+  // ---------------------------------
+  // Partner ClearCore Example Sketch
+  // ---------------------------------
+
+#include <Ethernet.h>
+
+// Change the MAC address and IP address below to match your ClearCore's
+// MAC address and IP.
+byte mac[] = {0xDE, 0xAD, 0xBE, 0xEF, 0xFE, 0xEE};
+IPAddress ip(192, 168, 1, 178);
+
+// The local port to listen for connections on.
+unsigned int localPort = 8888;
+
+// The remote ClearCore's IP address and port
+IPAddress remoteIp(192, 168, 1, 177);
+unsigned int remotePort = 8888;
+
+// The last time you sent a packet to the remote device, in milliseconds.
+unsigned long lastSendTime = 0;
+// Delay between sending packets, in milliseconds
+const unsigned long sendingInterval = 10*1000;
+
+// An EthernetUDP instance to let us send and receive packets over UDP
+EthernetUDP Udp;
+
+// Set this false if not using DHCP to configure the local IP address.
+bool usingDhcp = true;
+
+void setup() {
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    Serial.begin(9600);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Get the Ethernet module up and running.
+    if (usingDhcp) {
+        int dhcpSuccess = Ethernet.begin(mac);
+        if (dhcpSuccess) {
+            Serial.println("DHCP configuration was successful.");
+        }
+        else {
+            Serial.println("DHCP configuration was unsuccessful!");
+            Serial.println("Try again using a manual configuration...");
+            while (true) {
+                // UDP will not work without a configured IP address.
+                continue;
+            }
+        }
+    }
+    else {
+        Ethernet.begin(mac, ip);
+    }
+
+    // Make sure the physical link is up before continuing.
+    while (Ethernet.linkStatus() == LinkOFF) {
+        // Turn the BUILTIN_LED on while the physical link is down.
+    }
+
+    // Begin listening on the local port for UDP datagrams
+    Udp.begin(localPort);
+}
+
+// This loop will send a packet to the remote IP and port specified every
+// 10 seconds.
+void loop() {
+
+    // Wait for 10 seconds.
+    if (millis() - lastSendTime > sendingInterval) {
+        Udp.beginPacket(remoteIp, remotePort);
+        Udp.write("Hello ClearCore.");
+        Udp.endPacket();
+        lastSendTime = millis();
+    }
+
+    // Keep the connection alive.
+    Ethernet.maintain();
+}
+
+*/
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/ethernet-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/ethernet-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/ethernet-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/library.properties
new file mode 100644
index 000000000..f0b4bf6ca
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/Ethernet/library.properties
@@ -0,0 +1,9 @@
+name=ClearCore Ethernet
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Ethernet Examples
+paragraph=Teknic ClearCore Ethernet Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/README.md b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/README.md
new file mode 100644
index 000000000..283e07766
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/README.md
@@ -0,0 +1,3 @@
+# Examples for Teknic ClearCore
+
+When you have the Teknic ClearCore device selected in the Arduino IDE, these examples will appear in the File/Examples menu item under the "Examples for Teknic ClearCore" heading.
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/ReadWrite/ReadWrite.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/ReadWrite/ReadWrite.ino
new file mode 100644
index 000000000..ff34b5039
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/ReadWrite/ReadWrite.ino
@@ -0,0 +1,88 @@
+/*
+ * Title: ReadWrite
+ *
+ * Objective:
+ *    This example demonstrates how to read from and write to a file on the
+ *    SD card.
+ *
+ * Description:
+ *    This example writes to a text file on the SD card then reads the file
+ *    back to the USB serial port.
+ *
+ * Requirements:
+ * ** A micro SD card installed in the ClearCore.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 11/25/2020
+ * This is a slightly modified version of the builtin Arduino SD ReadWrite sketch.
+ * This example code is in the public domain. 
+ */
+#include <SPI.h>
+#include <SD.h>
+
+File myFile;
+
+void setup() {
+    // Open serial communications and wait for port to open:
+    Serial.begin(9600);
+    while (!Serial) {
+        // Wait for the USB serial port to open.
+        continue; 
+    }
+
+    Serial.print("Initializing SD card...");
+
+    if (!SD.begin()) {
+        Serial.println("initialization failed!");
+        while (true) {
+            // We can't continue without a working SD card
+            continue;
+        }
+    }
+    Serial.println("initialization done.");
+
+    // open the file. note that only one file can be open at a time,
+    // so you have to close this one before opening another.
+    myFile = SD.open("test.txt", FILE_WRITE);
+
+    // If the file opened okay, write to it:
+    if (myFile) {
+        Serial.print("Writing to test.txt...");
+        myFile.println("testing 1, 2, 3.");
+        // Close the file:
+        myFile.close();
+        Serial.println("done.");
+    } 
+    else {
+        // If the file didn't open, print an error:
+        Serial.println("error opening test.txt");
+        while (true) {
+            continue;
+        }
+    }
+
+    // Re-open the file for reading:
+    myFile = SD.open("test.txt");
+    if (myFile) {
+        Serial.println("test.txt:");
+
+        // Read from the file until there's nothing else in it:
+        while (myFile.available()) {
+            Serial.write(myFile.read());
+        }
+        // Close the file:
+        myFile.close();
+    } 
+    else {
+        // If the file didn't open, print an error:
+        Serial.println("error opening test.txt");
+    }
+}
+
+void loop() {
+    // Nothing happens after setup
+}
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/library.properties
new file mode 100644
index 000000000..5334f02df
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/library.properties
@@ -0,0 +1,9 @@
+name=SD Card
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Serial Communication Examples
+paragraph=Teknic ClearCore Serial Communication Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/sd-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/sd-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SD/sd-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/ClearCoreCommandProtocol/ClearCoreCommandProtocol.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/ClearCoreCommandProtocol/ClearCoreCommandProtocol.ino
new file mode 100644
index 000000000..e2325b4fd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/ClearCoreCommandProtocol/ClearCoreCommandProtocol.ino
@@ -0,0 +1,868 @@
+/*
+ * Title: ClearCoreCommandProtocol
+ *
+ * Objective:
+ *    This example demonstrates control of various functionality of the Teknic 
+ *     ClearCoreI/O and motion controller, including controlling ClearPath-SD 
+ *     motors instep and direction mode.
+ *
+ * Description:
+ *    This example processes strings of characters formatted according to the
+ *     specifications below and commands the corresponding action on a ClearCore device. 
+ *    This example is designed to be highly configurable to meet the requirements
+ *     of a variety of applications. The protocol accepts input and sends output
+ *     via USB connection by default but can be configured to accept commands from
+ *     other streams - such as ClearCore's COM ports, ethernet port, or XBee
+ *     connection - and sources - such as manual user input, input from a text
+ *     file, or control from another device sending text commands to ClearCore.
+ *    
+ * Setup:
+ * 0. Consult the accompanying ClearCore Command Protocol User Guide for more
+ *     information on using this example project. 
+ *     https://teknic.com/files/downloads/ClearCoreCommandProtocol_UserGuide.pdf
+ * 1. Connect ClearCore via USB to a terminal that can send and receive ASCII
+ *     (standard text encoding) messages, or modify the code and connect to a
+ *     different source of messages. Other ClearCore examples demonstrate
+ *     communication via these alternate connection options. 
+ * 2. ClearPath-SD motors can be connected to connector M-0, M-1, M-2, and/or M-3.
+ * 3. The connected ClearPath-SD motor(s) must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 4. The ClearPath-SD motor(s) must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 5. Set the Input Format in MSP for "Step + Direction".  
+ * 6. Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ * 7. Input and output devices can be wired to connectors IO0-IO5, DI6-DI8, and/or
+ *     AI9-AI12. A table summarizing the acceptable connector modes for each
+ *     ClearCore connector can be found in the ClearCore manual and in the User
+ *     Guide for this example. This example explicitly sets the operational mode
+ *     for each connector, but these modes can be reconfigured according to the
+ *     table in the manual. Be sure to consult the ClearCore manual and
+ *     supplemental wiring and connection diagrams to view the operating modes
+ *     for each pin and corresponding connection setups.
+ *    
+ * Example Command Sequences
+ *	The following provides an example command sequence and corresponding behavior:
+ *		e1			//enable motor1
+ *		e2			//enable motor2
+ *		m1 1000		// if ABSOLUTE_MOVE==1, move motor1 to absolute position 1000 steps 
+ *					// if ABSOLUTE_MOVE==0, move motor1 1000 steps in the positive direction 
+ *		v2 -200		//move motor2 at -200 steps/s in the negative direction
+ *		q2s			//query the status of motor2
+ *		l3v	100		//limit motor3's velocity (of positional moves only) to 100 steps/s
+ *		z1			//zero Clear's position reference for motor1 (no motion is commanded to the motor)  
+ *		i6			//read the current state of connector6 (DI6)
+ *		o5 1		//output a value of 1 (digital high) to connector5 (IO5)
+ *		h 			//display the help message
+ *		
+ *	The following example command sequence highlights special cases and notable behavior:
+ *		v0 1000		//since motor0 has not yet been enabled, no motion will be commanded
+ *		e0			//enable motor0
+ *		v0 1000		//move motor0 at 1000 steps/s
+ *		d0			//disable motor0. since motor0 was actively moving, motor0 will fault
+ *		v0 1000		//since motor0 is in fault (disabled during motion), no motion will be commanded
+ *		q1s			//query the status of motor0. since the motor is in alert, the alert status will also print
+ *		f 0			//disable verbose feedback 
+ *		q1s			//with verbose feedback disabled, only the numerical status (and alert, in this case) 
+ *					//	register(s) will print, not the full status (and alert) message
+ *		c0			//clear alerts on motor0
+ *		v0 1000		//move motor0 at 1000 steps/s
+ *		
+ *		m1 2000		//assuming ABSOLUTE_MOVE is left as default, move motor1 to absolute position 2000 steps
+ *		m1 2000		//since motor1 is already at absolute position 2000 steps, no motion will be commanded
+ *		z1			//define motor1's current position as the zero position 
+ *		m1 2000		//move motor1 to absolute position 2000, which is 2000 steps  
+ *					//	away from its freshly-zeroed current position
+ *    
+ * Additional Resources:
+ * ** ClearCore Command Protocol User Guide:
+ *     https://teknic.com/files/downloads/ClearCoreCommandProtocol_UserGuide.pdf
+ * ** ClearCore Documentation:
+ * 		https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual:
+ * 		 https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearCore System Diagram and Connection Diagrams:
+ * 		https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power):
+ * 		https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power):
+ * 		https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+ 
+ #include "ClearCore.h"
+#include <stdint.h>
+#include <stdlib.h> //for atoi (ASCII to Integer) parsing utility
+
+// specify which serial interface to use as input/output
+#define ioPort ConnectorUsb
+// select the baud rate to match the target device.
+#define ioPortBaudRate  115200
+// specify whether the target serial interface uses CTS/RTS flow control
+//   set to true if your target device uses CTS/RTS flow control
+// this is only necessary if using COM ports or XBee module (not necessary for USB)
+#define ioFlowControl false
+
+// structure to hold information on the feedback messages
+struct FeedbackMessage{
+  uint32_t number;
+  char *message; 
+};
+
+// feedback message numbers
+#define FB_COMMAND_OK                               ( 0)  
+#define FB_ERR_BUFFER_OVERRUN                       ( 1)
+#define FB_ERR_INPUT_INVALID_NONLETTER              ( 2)
+#define FB_ERR_MOTOR_NUM_INVALID                    ( 3)  
+#define FB_ERR_CONNECTOR_NUM_INVALID                ( 4)  
+#define FB_ERR_CONNECTOR_MODE_INCOMPATIBLE          ( 5)
+#define FB_ENABLED_WAITING_ON_HLFB                  ( 6)
+#define FB_ENABLE_FAILURE                           ( 7)
+#define FB_ERR_IO_OUTPUT                            ( 8)
+#define FB_ERR_MOVE_NOT_ENABLED                     ( 9)  
+#define FB_ERR_MOVE_IN_ALERT                        (10)
+#define FB_ERR_INVALID_QUERY_REQUEST                (11)
+#define FB_ERR_LIMIT_OUT_OF_BOUNDS                  (12)        
+#define FB_ERR_INVALID_LIMIT_REQUEST                (13)
+#define FB_ERR_INVALID_FEEDBACK_OPTION              (14)
+#define FB_ERR_UNRECOGNIZED_COMMAND                 (15)
+#define FB_HELP                                     (16)
+
+// verbose feedback messages            
+char *msg_command_ok = 
+  "Command received";
+char *msg_err_buffer_overrun = 
+  "Error: input buffer overrun.";
+char *msg_err_input_invalid_nonletter = 
+  "Error: invalid input. Commands begin with a single letter character.";
+char *msg_err_motor_num_invalid = 
+  "Error: a required motor was not specified or specified incorrectly. Acceptable motor numbers are 0, 1, 2, and 3.";
+char *msg_err_connector_num_invalid = 
+  "Error: a required connector was not specified or specified incorrectly. Acceptable connector numbers are 0 through 12, inclusive.";
+char *msg_err_io_output = 
+  "Error: an I/O output parameter is invalid. Ensure the output value is appropriate for the type of output pin.";
+char *msg_err_connector_mode_incompatible = 
+	"Error: a specified connector is of an inappropriate mode. Verify the I/O connector is configured as necessary."; 
+char *msg_enabled_waiting_on_hlfb = 
+  "Motor enabled; waiting on HLFB to assert before accepting other commands.";
+char *msg_enable_failure = 
+  "Motor failed to enable due to motor fault, loss of power, or loss/absence of connection. Motor disabled.";
+char *msg_err_move_not_enabled = 
+  "Error: motion commanded while motor not enabled. Command e# to enable motor number #.";
+char *msg_err_move_in_alert = 
+  "Error: motion commanded while motor in fault. Command c# to clear alerts on motor number #.";
+char *msg_err_invalid_query_request = 
+  "Error: invalid query request. Command h for more information.";
+char *msg_err_limit_out_of_bounds = 
+  "Error: commanded limit falls outside the acceptable bounds for this limit.";
+char *msg_err_invalid_limit_request = 
+  "Error: invalid limit request. Command h for more information.";
+char *msg_err_invalid_feedback_option = 
+  "Error: invalid feedback request. Command h for more information.";
+char *msg_err_unrecognized_command = 
+  "Error: unrecognized command. Command h for more information.";
+char *msg_help = 
+      "ClearCore Command Protocol\n"
+      "Acceptable commands, where # specifies a motor number* (0, 1, 2, or 3): \n"
+      "    e#              | enable specified motor\n"
+      "    d#              | disable specified motor\n"
+      "    m# distance     | if(ABSOLUTE_MOVE==1) move to the specified position\n"
+      "                      if(ABSOLUTE_MOVE==0) move the specified number of steps\n"
+      "    v# velocity     | move at the specified velocity (steps/s)\n"
+      "    q#<p/v/s>       | query specified motor's position/velocity/status\n"
+      "    l#<v/a> limit   | set specified motor's velocity/acceleration limit\n"
+      "    c#              | clear alerts\n"
+      "    z#              | set the zero position for motor # to the current commanded position\n"
+      "    i#              | read input on pin #\n"
+      "                        Digital pins return 1 or 0; analog pins return [0,4095] corresponding to [0,10]V\n"
+      "                        (*note that # for this command can be 0 through 5)\n"
+      "    o# outputVal    | write output on pin #\n"
+      "                        Digital pins allow 1 or 0; analog pins allow [409,2047] corresponding to [4,20]mA\n"
+      "                        (*note that # for this command can be 0 through 12)\n"
+      "    f fdbkType      | specify the type of feedback printed:\n"
+      "                        0  : send message number only\n"
+      "                        1  : send verbose message\n"
+      "    h               | print this help message\n";
+
+// array of feedback messages, accessed by SendFeedback() when feedback is sent 
+FeedbackMessage FeedbackMessages[17] = {
+  {FB_COMMAND_OK					,   msg_command_ok					},
+  {FB_ERR_BUFFER_OVERRUN			,   msg_err_buffer_overrun			},
+  {FB_ERR_INPUT_INVALID_NONLETTER	,   msg_err_input_invalid_nonletter	},
+  {FB_ERR_MOTOR_NUM_INVALID   		,   msg_err_motor_num_invalid		},
+  {FB_ERR_CONNECTOR_NUM_INVALID		,   msg_err_connector_num_invalid   },
+  {FB_ERR_CONNECTOR_MODE_INCOMPATIBLE,  
+                    msg_err_connector_mode_incompatible					},
+  {FB_ENABLED_WAITING_ON_HLFB		,   msg_enabled_waiting_on_hlfb     },
+  {FB_ENABLE_FAILURE				,   msg_enable_failure				},
+  {FB_ERR_IO_OUTPUT					,   msg_err_io_output				},
+  {FB_ERR_MOVE_NOT_ENABLED			,   msg_err_move_not_enabled		},
+  {FB_ERR_MOVE_IN_ALERT				,   msg_err_move_in_alert			},
+  {FB_ERR_INVALID_QUERY_REQUEST		,   msg_err_invalid_query_request	},
+  {FB_ERR_LIMIT_OUT_OF_BOUNDS		,   msg_err_limit_out_of_bounds		},
+  {FB_ERR_INVALID_LIMIT_REQUEST		,   msg_err_invalid_limit_request	},
+  {FB_ERR_INVALID_FEEDBACK_OPTION	,   msg_err_invalid_feedback_option	},
+  {FB_ERR_UNRECOGNIZED_COMMAND		, msg_err_unrecognized_command		},
+  {FB_HELP							,   msg_help						}
+};
+
+// global variable to select between printing only feedback number or verbose feedback message
+bool verboseFeedback = true;
+
+// macro to select between commanding absolute positional moves or relative 
+//  positional moves. See CCCP User Guide for more information.                     
+#define ABSOLUTE_MOVE (0)
+
+// container for the char stream to be read-in. 
+//  allows for IN_BUFFER_LEN characters to be stored followed by a NULL terminator 
+#define IN_BUFFER_LEN 32
+char input[IN_BUFFER_LEN+1];
+
+// motor connectors
+MotorDriver *const motors[MOTOR_CON_CNT] = {
+  &ConnectorM0, &ConnectorM1, &ConnectorM2, &ConnectorM3
+};
+
+// I/O connectors
+Connector *const connectors[13] = {
+  &ConnectorIO0, &ConnectorIO1, &ConnectorIO2, &ConnectorIO3, &ConnectorIO4, &ConnectorIO5, 
+  &ConnectorDI6, &ConnectorDI7, &ConnectorDI8,
+  &ConnectorA9, &ConnectorA10, &ConnectorA11, &ConnectorA12
+};
+
+// acceleration and velocity limit bounds 
+// (note that velocity limits take effect only on positional moves)
+#define DEFAULT_ACCEL_LIMIT (100000) // pulses per sec^2
+#define MAX_ACCEL_LIMIT (1000000000) 
+#define MIN_ACCEL_LIMIT (1)
+#define DEFAULT_VEL_LIMIT (10000) // pulses per sec
+#define MAX_VEL_LIMIT (500000)
+#define MIN_VEL_LIMIT (1)
+
+// helper functions to print feedback and status information
+// the implementations of these functions are at the bottom of this example
+void SendFeedback(int32_t messageNumber);
+void SendVerboseStatus(int32_t motorNumber);
+
+
+  // local storage for velocity and acceleration limits
+  // (note that velocity limits only take effect on positional moves)
+  uint32_t accelerationLimits[MOTOR_CON_CNT] = { 
+    DEFAULT_ACCEL_LIMIT, DEFAULT_ACCEL_LIMIT, DEFAULT_ACCEL_LIMIT, DEFAULT_ACCEL_LIMIT
+  };
+  uint32_t velocityLimits[MOTOR_CON_CNT] = { 
+    DEFAULT_VEL_LIMIT, DEFAULT_VEL_LIMIT, DEFAULT_VEL_LIMIT, DEFAULT_VEL_LIMIT
+  };
+
+ // generic iterator
+  uint32_t i;
+
+  // program control variables
+  bool inputValid;
+  bool motorNumValid;
+  bool connectorNumValid;
+  bool motorEnabledBeforeClearingAlerts;
+
+  // parsing variables
+  int32_t motorNum_in; 
+  int32_t connectorNum_in; 
+  int32_t moveDistance_in;
+  int32_t velocity_in;
+  int32_t limit_in; 
+  int32_t queriedValue;
+  int16_t inputConnectorValue;
+  int16_t outputConnectorValue_in;
+
+
+void setup() {
+// configure serial communication to USB port and wait for the port to open
+  ioPort.Mode(Connector::USB_CDC);  
+  ioPort.Speed(ioPortBaudRate);
+  // ioPort.FlowControl(ioFlowControl); //only necessary if using COM ports or XBee module
+  ioPort.PortOpen();
+  while (!ioPort) {
+    continue;
+  }
+  
+  // configure input clocking rate
+  // this normal rate is ideal for ClearPath step and direction applications
+  MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+  // set all motor connectors into step and direction mode
+  MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL, Connector::CPM_MODE_STEP_AND_DIR);
+  
+ 
+  // configure all motor connectors for bipolar PWM HLFB mode at 482Hz, and set 
+  //  velocity and acceleration limits
+  for (i=0; i<MOTOR_CON_CNT; i++){
+    motors[i]->HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    motors[i]->HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+    motors[i]->VelMax(velocityLimits[i]);
+    motors[i]->AccelMax(accelerationLimits[i]);
+  }
+
+  // configure I/O pins
+  //  these defaults can be modified according to application needs
+  //  for more information and to view a list of configurable modes for each pin, 
+  //  see the ClearCore manual: https://teknic.com/files/downloads/clearcore_user_manual.pdf
+  ConnectorIO0.Mode(Connector::OUTPUT_ANALOG );
+  ConnectorIO1.Mode(Connector::OUTPUT_DIGITAL);
+  ConnectorIO2.Mode(Connector::OUTPUT_DIGITAL);
+  ConnectorIO3.Mode(Connector::OUTPUT_DIGITAL);
+  ConnectorIO4.Mode(Connector::OUTPUT_DIGITAL);
+  ConnectorIO5.Mode(Connector::OUTPUT_DIGITAL);
+  ConnectorDI6.Mode(Connector::INPUT_DIGITAL );
+  ConnectorDI7.Mode(Connector::INPUT_DIGITAL );
+  ConnectorDI8.Mode(Connector::INPUT_DIGITAL );
+  ConnectorA9 .Mode(Connector::INPUT_ANALOG  );
+  ConnectorA10.Mode(Connector::INPUT_ANALOG  );
+  ConnectorA11.Mode(Connector::INPUT_ANALOG  );
+  ConnectorA12.Mode(Connector::INPUT_ANALOG  );
+  
+  ioPort.SendLine("Setup successful");
+  ioPort.SendLine("Send 'h' to receive a list of valid commands"); 
+}
+
+void loop() {
+
+// reset the input buffer by populating each index with a NULL character
+    for (i = 0; i<IN_BUFFER_LEN+1; i++){
+      input[i] = (char) NULL;
+    }
+    
+    // read and store the input character by character
+	// input buffer has a default maximum size, defined by IN_BUFFER_LEN, of 32. 
+	// if more characters are provided by the user, program will reject input.
+	inputValid = true;
+    i = 0;
+    while(i<IN_BUFFER_LEN && ioPort.CharPeek() != -1){
+      input[i] = (char) ioPort.CharGet();
+      i++;
+	  Delay_ms(1);
+    }
+    
+    //-------------------------
+    // This line divides the command reading and storing section of the code from 
+    //  the command parsing section of the code. To use this protocol to accept commands 
+    //  from another source than the default USB input, ensure that the command is stored 
+    //  in a character array called "input" and is ready to be parsed after this line.
+    //-------------------------
+
+    // echo nonempty input when in verbose feedback mode
+    if(verboseFeedback && i!=0){
+      ioPort.SendLine(input);
+    }
+    
+    if (i==0){
+      // user did not input any characters. input invalid, but no need to report 
+      inputValid = false;
+    } else if (ioPort.CharPeek()!=-1){ 
+      // buffer overflow (there is no space left in the buffer, but there are still characters to read from ioPort)
+      // report error, reject input, and flush input stream (so the leftover characters aren't read as part of the next command)
+      SendFeedback(FB_ERR_BUFFER_OVERRUN);
+      inputValid = false;
+      ioPort.FlushInput();
+    }
+    
+    // verify first character of command is a letter
+    if (inputValid){
+      if (('A' <= input[0] && input[0] <= 'Z') || ('a' <= input[0] && input[0] <= 'z')){
+        // if letter is uppercase, convert to lowercase
+        if ('A' <= input[0] && input[0] <= 'Z'){
+          // to convert an ASCII character from upper to lower case, add 32 to the character
+          input[0] += 32; 
+        }
+      } else {
+        // if first letter of command is not letter, reject input
+        SendFeedback(FB_ERR_INPUT_INVALID_NONLETTER);
+        inputValid = false;
+        while(ioPort.CharPeek()!=-1){
+			ioPort.FlushInput();
+			Delay_ms(10);
+		}
+      }
+    }
+    
+    if (inputValid){
+
+      // store and validate motor number input from command
+      motorNum_in = atoi(&input[1]); 
+      motorNumValid = (0<=motorNum_in && motorNum_in<=3 && input[1]!=NULL);
+      
+      // store and validate connector number input from command
+      connectorNum_in = atoi(&input[1]); 
+      connectorNumValid = (0<=connectorNum_in && connectorNum_in<=12 && input[1]!=NULL);
+      
+      // status register for accessing motor status information
+      volatile const MotorDriver::StatusRegMotor &statusReg = motors[motorNum_in]->StatusReg();
+      volatile const MotorDriver::AlertRegMotor  &alertReg  = motors[motorNum_in]->AlertReg();
+
+
+      // process the command based on the command letter (first character of input)
+      switch(input[0]){
+              
+        // enable 
+        case 'e':
+          // verify motor number valid
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+          } else {
+            // enable the motor
+            motors[motorNum_in]->EnableRequest(true);
+            SendFeedback(FB_ENABLED_WAITING_ON_HLFB);
+            // wait until motor is ready before accepting other commands 
+            //  (allows any automatic homing move to complete if configured)
+            //  (loop will exit on fault during homing, or if motor is disconnected or loses power)
+            while (statusReg.bit.HlfbState != MotorDriver::HLFB_ASSERTED &&
+					!statusReg.bit.MotorInFault){
+				continue;
+			}
+			if(statusReg.bit.MotorInFault){
+              // if there is a fault while trying to enable, disable and report
+              motors[motorNum_in]->EnableRequest(false);
+              SendFeedback(FB_ENABLE_FAILURE);
+            } else {
+              SendFeedback(FB_COMMAND_OK);
+            }
+          }
+          break; 
+
+        // disable
+        case 'd':
+          // verify motor number valid
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+          } else {
+            // disable the motor
+            motors[motorNum_in]->EnableRequest(false);
+            SendFeedback(FB_COMMAND_OK);
+          }
+          break;
+          
+        // position move 
+        case 'm': 
+          // verify motor number valid, motor enabled, and no faults present
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+          } else if ( statusReg.bit.ReadyState==MotorDriver::MOTOR_DISABLED || 
+                  statusReg.bit.ReadyState==MotorDriver::MOTOR_ENABLING){
+            SendFeedback(FB_ERR_MOVE_NOT_ENABLED);
+          } else if (motors[motorNum_in]->StatusReg().bit.AlertsPresent) {
+            SendFeedback(FB_ERR_MOVE_IN_ALERT);
+          } else {
+            // command the move
+            // #define ABSOLUTE_MOVE (0) commands absolute moves.
+            // #define ABSOLUTE_MOVE (1) commands relative moves.
+            // absolute moves are configured by default.
+            // See User Guide for more information.
+            moveDistance_in = atoi(&input[2]);    
+            if (ABSOLUTE_MOVE){
+              motors[motorNum_in]->Move(moveDistance_in, MotorDriver::MOVE_TARGET_ABSOLUTE);
+            } else {
+              motors[motorNum_in]->Move(moveDistance_in);
+            }       
+            SendFeedback(FB_COMMAND_OK);
+          }
+          break;
+
+        // velocity move 
+        case 'v': 
+          // verify motor number valid, motor enabled, and no faults present
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+          } else if ( statusReg.bit.ReadyState==MotorDriver::MOTOR_DISABLED ||
+                  statusReg.bit.ReadyState==MotorDriver::MOTOR_ENABLING){
+            SendFeedback(FB_ERR_MOVE_NOT_ENABLED);
+          } else if (motors[motorNum_in]->StatusReg().bit.AlertsPresent) {
+            SendFeedback(FB_ERR_MOVE_IN_ALERT);
+          } else {
+            // command the move
+            velocity_in = atoi(&input[2]);
+            motors[motorNum_in]->MoveVelocity(velocity_in);
+            SendFeedback(FB_COMMAND_OK);
+          }
+          break;
+        
+        // query position, velocity, or status
+        case 'q':
+          // verify motor number valid
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+            break;
+          }
+          switch(input[2]){
+            // query commanded position 
+            case 'p':
+            case 'P':
+              // send commanded position. 
+              // this can differ from the position counter in MSP if the ClearCore 
+              //  position reference has not been synced with ClearPath's position
+              queriedValue = (int32_t) motors[motorNum_in]->PositionRefCommanded();
+              if (verboseFeedback){
+                ioPort.Send("Motor ");
+                ioPort.Send(motorNum_in);
+                ioPort.Send(" is in position (steps) ");
+              }
+              ioPort.SendLine(queriedValue);
+              break;
+              
+            // query velocity
+            case 'v':
+            case 'V':
+              // send motor velocity
+              queriedValue = motors[motorNum_in]->VelocityRefCommanded();
+              if (verboseFeedback){
+                ioPort.Send("Motor ");
+                ioPort.Send(motorNum_in);
+                ioPort.Send(" is at velocity (steps/s) ");
+              }
+              ioPort.SendLine(queriedValue);
+              break;
+              
+            // query status 
+            case 's':
+            case 'S':
+              // send motor status
+              if (verboseFeedback){
+                SendVerboseStatus(motorNum_in);
+              } else {
+                ioPort.SendLine(statusReg.reg, 2);  // prints the status register in binary
+                if (statusReg.bit.AlertsPresent){
+                  ioPort.SendLine(alertReg.reg, 2); // prints the alert register in binary
+                }
+              }
+              break;
+            
+            // invalid query request
+            default:
+              SendFeedback(FB_ERR_INVALID_QUERY_REQUEST);
+          }
+          break;
+        
+        // set acceleration or velocity limit
+        case 'l': 
+          // verify motor number valid
+          if ( !motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+            break;
+          }
+          // store limit input from command
+          limit_in = atoi(&input[3]);
+          
+          switch(input[2]){
+            // velocity limit
+            case 'v':
+            case 'V':
+              // verify limit is valid, store, then propagate the change to the motor
+              if (MIN_VEL_LIMIT<=limit_in && limit_in<=MAX_VEL_LIMIT){
+                velocityLimits[motorNum_in] = limit_in;
+                motors[motorNum_in]->VelMax(velocityLimits[motorNum_in]);
+                SendFeedback(FB_COMMAND_OK);
+              } else {
+                SendFeedback(FB_ERR_LIMIT_OUT_OF_BOUNDS);
+              }
+              break;
+              
+            // acceleration limit
+            case 'a':
+            case 'A':
+              // verify limit is valid, store, then propagate the change to the motor
+              if (MIN_ACCEL_LIMIT<=limit_in && limit_in<=MAX_ACCEL_LIMIT){
+                accelerationLimits[motorNum_in] = limit_in;
+                motors[motorNum_in]->AccelMax(velocityLimits[motorNum_in]);
+                SendFeedback(FB_COMMAND_OK);
+              } else {
+                SendFeedback(FB_ERR_LIMIT_OUT_OF_BOUNDS);
+              }
+              break;
+              
+            // invalid limit request
+            default:
+              SendFeedback(FB_ERR_INVALID_LIMIT_REQUEST);
+              break;
+          }
+          break;
+
+        // clear alerts
+        case 'c':
+          // verify motor number valid
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+            break;
+          }
+		  
+		  // capture the current state of enable 
+		  //	this value will be restored after alerts are cleared
+		  motorEnabledBeforeClearingAlerts = motors[motorNum_in]->EnableRequest();
+			
+          // to clear all ClearCore alerts (which can include motor faults): 
+          //  - cycle enable if faults present (clears faults, if any)
+          //  - clear alert register (clears alerts)
+          // this command clears both ClearCore motor alerts and motor faults
+          if (statusReg.bit.MotorInFault){
+            motors[motorNum_in]->EnableRequest(false);
+            Delay_ms(10);
+            if(motorEnabledBeforeClearingAlerts){
+              motors[motorNum_in]->EnableRequest(true);
+            }
+          }
+          motors[motorNum_in]->ClearAlerts();
+          SendFeedback(FB_COMMAND_OK);
+          break;
+          
+        // set the zero position for motor # to the current commanded position
+        case 'z':
+          // verify motor number valid
+          if (!motorNumValid){
+            SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+            break;
+          }
+          // zero position
+          motors[motorNum_in]->PositionRefSet(0);
+          SendFeedback(FB_COMMAND_OK);
+          break;
+
+        // read input from ClearCore connector 
+        case 'i':
+          // verify connector number valid
+          if (!connectorNumValid){
+            SendFeedback(FB_ERR_CONNECTOR_NUM_INVALID);
+            break;
+          }
+          // verify connector mode valid
+          if (connectors[connectorNum_in]->Mode() != Connector::INPUT_DIGITAL && 
+                connectors[connectorNum_in]->Mode() != Connector::INPUT_ANALOG){
+            SendFeedback(FB_ERR_CONNECTOR_MODE_INCOMPATIBLE); 
+            break;
+          }
+          inputConnectorValue = connectors[connectorNum_in]->State();
+          if(verboseFeedback){
+            ioPort.Send("Connector ");
+            ioPort.Send(connectorNum_in);
+            ioPort.Send(" value: ");
+          }
+          ioPort.SendLine(inputConnectorValue);
+          break;
+        
+        
+        // write digital output to ClearCore digital output connector 
+        case 'o':
+          // verify connector number valid
+          if (!connectorNumValid){
+            SendFeedback(FB_ERR_CONNECTOR_NUM_INVALID); 
+            break;
+          }
+          // verify connector type valid
+          if (connectors[connectorNum_in]->Mode() != Connector::OUTPUT_DIGITAL && 
+                connectors[connectorNum_in]->Mode() != Connector::OUTPUT_ANALOG){
+            SendFeedback(FB_ERR_CONNECTOR_MODE_INCOMPATIBLE); 
+            break;
+          }
+          // store and write value
+          outputConnectorValue_in = atoi(&input[3]);
+          if(!connectors[connectorNum_in]->State(outputConnectorValue_in)){
+            SendFeedback(FB_ERR_IO_OUTPUT);
+          } else {
+            SendFeedback(FB_COMMAND_OK);
+          }
+          break;
+        
+        
+        // change feedback type 
+        case 'f':
+          switch(atoi(&input[1])){
+            
+            // feedback number only
+            case 0:
+              verboseFeedback = false;
+              SendFeedback(FB_COMMAND_OK);
+            break;
+            
+            // verbose feedback messages
+            case 1:
+              verboseFeedback = true;
+              SendFeedback(FB_COMMAND_OK);
+              break;
+            
+            // invalid feedback request
+            default:
+              SendFeedback(FB_ERR_INVALID_FEEDBACK_OPTION);
+            break;
+          }
+          break;
+
+        // help
+        case 'h':
+          SendFeedback(FB_HELP);
+          break;
+
+        // invalid command letter
+        default:
+          SendFeedback(FB_ERR_UNRECOGNIZED_COMMAND);
+          break;
+
+      } // switch(command letter)
+    } // if (inputValid)
+}
+
+
+
+/*------------------------------------------------------------------------------
+ * SendFeedback
+ *
+ *    Helper function to send feedback for specified feedback message.
+ *   
+ * Parameters:
+ *    int messageNumber  - The feedback identification number corresponding the 
+ *      feedback struct array index
+ *
+ * Returns: None (feedback message is sent directly to output)
+*/
+ void SendFeedback(int32_t messageNumber){
+  // send either the verbose message or only the message number, based on verboseFeedback bool
+  if (verboseFeedback){
+    ioPort.SendLine(FeedbackMessages[messageNumber].message);
+  } else {
+    ioPort.SendLine(FeedbackMessages[messageNumber].number);
+  }
+ } // SendFeedback()
+//------------------------------------------------------------------------------
+
+
+
+/*------------------------------------------------------------------------------
+ * SendVerboseStatus
+ *
+ *    Outputs verbose status information. 
+ *    Functionality adapted from MotorStatusRegister example project
+ *
+ * Parameters:
+ *    int motorNumber  - The motor whose status should be printed
+ *
+ * Returns: None (status message is sent directly to output)
+ */
+void SendVerboseStatus(int32_t motorNumber) {
+  // status register for accessing motor status information
+  volatile const MotorDriver::StatusRegMotor &statusReg = motors[motorNumber]->StatusReg();
+  volatile const MotorDriver::AlertRegMotor &alertReg = motors[motorNumber]->AlertReg();
+  
+  ioPort.Send("Motor status register for motor M");
+  ioPort.Send(motorNumber);
+  ioPort.Send(": ");
+  ioPort.SendLine(statusReg.reg, 2); // prints the status register in binary
+  
+  ioPort.Send("AtTargetPosition:  ");
+  ioPort.SendLine(statusReg.bit.AtTargetPosition);
+
+  ioPort.Send("StepsActive:       ");
+  ioPort.SendLine(statusReg.bit.StepsActive);
+
+  ioPort.Send("AtTargetVelocity:  ");
+  ioPort.SendLine(statusReg.bit.AtTargetVelocity);
+
+  ioPort.Send("MoveDirection:     ");
+  ioPort.SendLine(statusReg.bit.MoveDirection);
+
+  ioPort.Send("MotorInFault:      ");
+  ioPort.SendLine(statusReg.bit.MotorInFault);
+
+  ioPort.Send("Enabled:           ");
+  ioPort.SendLine(statusReg.bit.Enabled);
+
+  ioPort.Send("PositionalMove:    ");
+  ioPort.SendLine(statusReg.bit.PositionalMove);
+
+  ioPort.Send("HLFB State:    ");
+  switch (statusReg.bit.HlfbState) {
+    case 0:
+      ioPort.SendLine("HLFB_DEASSERTED");
+      break;
+    case 1:
+      ioPort.SendLine("HLFB_ASSERTED");
+      break;
+    case 2:
+      ioPort.SendLine("HLFB_HAS_MEASUREMENT");
+      break;
+    case 3:
+      ioPort.SendLine("HLFB_UNKNOWN");
+      break;
+    default:
+      // something has gone wrong if this is printed
+      ioPort.SendLine("???");
+  }
+
+  ioPort.Send("AlertsPresent:     ");
+  ioPort.SendLine(statusReg.bit.AlertsPresent);
+
+  ioPort.Send("Ready state:   ");
+  switch (statusReg.bit.ReadyState) {
+    case MotorDriver::MOTOR_DISABLED:
+      ioPort.SendLine("Disabled");
+      break;
+    case MotorDriver::MOTOR_ENABLING:
+      ioPort.SendLine("Enabling");
+      break;
+    case MotorDriver::MOTOR_FAULTED:
+      ioPort.SendLine("Faulted");
+      break;
+    case MotorDriver::MOTOR_READY:
+      ioPort.SendLine("Ready");
+      break;
+    case MotorDriver::MOTOR_MOVING:
+      ioPort.SendLine("Moving");
+      break;
+    default:
+      // something has gone wrong if this is printed
+      ioPort.SendLine("???");
+  }
+  
+  ioPort.Send("Triggering:        ");
+  ioPort.SendLine(statusReg.bit.Triggering);
+
+  ioPort.Send("InPositiveLimit:   ");
+  ioPort.SendLine(statusReg.bit.InPositiveLimit);
+
+  ioPort.Send("InNegativeLimit:   ");
+  ioPort.SendLine(statusReg.bit.InNegativeLimit);
+
+  ioPort.Send("InEStopSensor:     ");
+  ioPort.SendLine(statusReg.bit.InEStopSensor); 
+
+  ioPort.SendLine("--------------------------------");
+  
+    
+  if (statusReg.bit.AlertsPresent){
+    ioPort.Send("Alert register:  ");
+    ioPort.SendLine(alertReg.reg, 2); // prints the alert register in binary
+
+    ioPort.Send("MotionCanceledInAlert:         ");
+    ioPort.SendLine(alertReg.bit.MotionCanceledInAlert);
+
+    ioPort.Send("MotionCanceledPositiveLimit:   ");
+    ioPort.SendLine(alertReg.bit.MotionCanceledPositiveLimit);
+
+    ioPort.Send("MotionCanceledNegativeLimit:   ");
+    ioPort.SendLine(alertReg.bit.MotionCanceledNegativeLimit);
+
+    ioPort.Send("MotionCanceledSensorEStop:     ");
+    ioPort.SendLine(alertReg.bit.MotionCanceledSensorEStop);
+
+    ioPort.Send("MotionCanceledMotorDisabled:   ");
+    ioPort.SendLine(alertReg.bit.MotionCanceledMotorDisabled);
+
+    ioPort.Send("MotorFaulted:                  ");
+    ioPort.SendLine(alertReg.bit.MotorFaulted);
+
+    ioPort.SendLine("--------------------------------");
+  }
+
+
+}// SendVerboseStatus()
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/ReadSerialInput/ReadSerialInput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/ReadSerialInput/ReadSerialInput.ino
new file mode 100644
index 000000000..ed653b7d7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/ReadSerialInput/ReadSerialInput.ino
@@ -0,0 +1,70 @@
+/*
+ * Title: ReadSerialInput
+ *
+ * Objective:
+ *    This example demonstrates how to read and display incoming data from a
+ *    serial port.
+ *
+ * Description:
+ *    This example will read one byte per second from the serial input buffer.
+ *    During operation, if a byte has been received, it will be printed to the
+ *    USB serial port as a character.
+ *
+ * Requirements:
+ * ** A serial input source connected to Serial0 (COM-0 on the ClearCore)
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// Select the baud rate to match the target device.
+#define baudRateSerialPort 115200
+#define baudRateInputPort  115200
+
+// When using COM ports, is the device TTL or RS232?
+#define isTtlInputPort  false
+
+// Container for the byte to be read-in
+int input;
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication to print out the serial input.
+    Serial.begin(baudRateSerialPort);
+    while (!Serial) {
+        continue;
+    }
+
+    // Set up serial communication to send serial input over.
+    Serial0.begin(baudRateInputPort);
+    Serial0.ttl(isTtlInputPort);
+    while (!Serial0) {
+        continue;
+    }
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Read the input.
+    input = Serial0.read();
+
+    // If there was a valid byte read-in, print it.
+    if (input != -1) {
+        // Display the input character received.
+        Serial.print("Received: ");
+        Serial.println((char)input);
+    }
+    else {
+        Serial.println("No data received...");
+    }
+
+    // Wait a second then repeat...
+    delay(1000);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SerialPrint/SerialPrint.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SerialPrint/SerialPrint.ino
new file mode 100644
index 000000000..0bbbd564d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SerialPrint/SerialPrint.ino
@@ -0,0 +1,42 @@
+/*
+ * Title: SerialPrint
+ *
+ * Objective:
+ *    This example demonstrates how to print text using serial output.
+ *
+ * Description:
+ *    This example will print the basic "Hello World" message to the USB serial
+ *    port.
+ *
+ * Requirements:
+ * ** None
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+// ClearCore provides three separate serial interfaces for communications.
+// The three options are Serial (USB), Serial0 (COM-0), or Serial1 (COM-1)
+#define SerialPort Serial
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication to print.
+    SerialPort.begin(9600);
+    while (!SerialPort) {
+        continue;
+    }
+
+    // The port is open and ready to talk.
+    SerialPort.println("Hello World!");
+}
+
+void loop() {
+    // This example doesn't have any ongoing tasks to perform.
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SpiComPortInitialization/SpiComPortInitialization.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SpiComPortInitialization/SpiComPortInitialization.ino
new file mode 100644
index 000000000..5da1cec4b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SpiComPortInitialization/SpiComPortInitialization.ino
@@ -0,0 +1,93 @@
+/*
+ * Title: SpiComPortInitialization
+ *
+ * Objective:
+ *    This example demonstrates how to configure a COM port for use with an
+ *    SPI device.
+ *
+ * Description:
+ *    This example will explain the basic configuration settings of an SPI
+ *    device then perform a brief transaction with the SPI device connected to
+ *    COM-0.
+ *
+ * Requirements:
+ * ** An SPI device connected to COM-0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+#include <SPI.h>
+
+// Select the baud rate to match the target device.
+#define baudRate 80000
+
+// Select the clock polarity to match the target device. The clock polarity
+// setting indicates whether the device expects a low signal when idle or a
+// high signal when idle. It also indicates whether the leading or trailing
+// edge of the clock cycle are rising or falling edges.
+// Selecting SCK_LOW indicates that SCK is low when idle and the leading edge
+// of the clock cycle is a rising edge while the trailing edge is a falling
+// edge.
+// Selecting SCK_HIGH indicates that SCK is high when idle and the leading edge
+// of the clock cycle is a falling edge while the trailing edge is a rising
+// edge.
+// The default value for a COM connector's clock polarity is SCK_LOW.
+#define clockPolarity SerialDriver::SCK_LOW
+
+// Select the clock phase setting to match the target device. The clock phase
+// setting indicates whether data is sampled or changed on the leading or
+// trailing edge in the clock cycle.
+// Selecting LEAD_SAMPLE indicates that data is sampled on the leading edge and
+// changed on the trailing edge.
+// Selecting LEAD_CHANGE indicates that data is sampled on the trailing edge
+// and changed on the leading edge.
+// The default value for a COM connector's clock phase is LEAD_CHANGE.
+#define clockPhase SerialDriver::LEAD_CHANGE
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // With the user settings, decide which SPI mode is needed
+    int spiMode;
+    if (clockPolarity == SerialDriver::SCK_LOW) {
+        if (clockPhase == SerialDriver::LEAD_SAMPLE) {
+            spiMode = SPI_MODE0;
+        }
+        else {
+            spiMode = SPI_MODE1;
+        }
+    }
+    else {
+        if (clockPhase == SerialDriver::LEAD_SAMPLE) {
+            spiMode = SPI_MODE2;
+        }
+        else {
+            spiMode = SPI_MODE3;
+        }
+    }
+
+    // Create the settings object to be passed when beginning SPI communications
+    SPISettings spiConfig(baudRate, MSBFIRST, spiMode);
+
+    // Open the SPI port on ConnectorCOM0
+    SPI.begin();
+
+    // Output some arbitrary sample data to the SPI device. This data is not
+    // required for set up, just to demonstrate the transfer process.
+    SPI.beginTransaction(spiConfig);
+    SPI.transfer('a');
+    SPI.transfer(98);
+    SPI.transfer(0x63);
+    SPI.endTransaction();
+}
+
+void loop() {
+    // This example doesn't have any ongoing tasks to perform.
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SpiSerialDisplay/SpiSerialDisplay.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SpiSerialDisplay/SpiSerialDisplay.ino
new file mode 100644
index 000000000..8380832e1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/SpiSerialDisplay/SpiSerialDisplay.ino
@@ -0,0 +1,125 @@
+/*
+ * Title: SpiSerialDisplay
+ *
+ * Objective:
+ *    This example demonstrates how to write data to an SPI device.
+ *
+ * Description:
+ *    This example will set up SPI communications on COM-0 then write various
+ *    data to the device.
+ *
+ * Requirements:
+ * ** A NHD-0420D3Z LCD display in SPI mode connected to COM-0
+ *    Datasheet: http://www.newhavendisplay.com/specs/NHD-0420D3Z-NSW-BBW-V3.pdf
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include <SPI.h>
+
+// Data bounds of the device
+#define NUM_ROWS 4
+#define NUM_COLUMNS 20
+
+// The settings object to be passed-in when we configure the COM port
+SPISettings spiConfig(80000, MSBFIRST, SPI_MODE3);
+
+// Sample data to write to the display
+const uint8_t line1[21] = "abcdefghijklmnopqrst";
+const uint8_t line2[21] = "ABCDEFGHIJKLMNOPQRST";
+const uint8_t line3[21] = "01234567890123456789";
+const uint8_t line4[21] = "98765432109876543210";
+
+// Declare our helper functions so that they may be used before they are defined
+void SetBrightness(uint8_t level);
+void SetCursor(uint8_t row, uint8_t column);
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    SPI.begin();
+
+    // The COM port is now configured and ready to send commands and
+    // data to the display.
+
+    // Set the display brightness level.
+    // The maximum value for full brightness is 8.
+    SetBrightness(4);
+
+    // Set the cursor position to the top-left corner.
+    SetCursor(0, 0);
+
+    SPI.beginTransaction(spiConfig);
+
+    // Send the lines "out of order" (1, 3, 2, 4) to the display.
+    // Without resetting the cursor position for each line, this is the order
+    // in which lines must be sent to be displayed correctly.
+    SPI.transfer(line1, NULL, 20);
+    SPI.transfer(line3, NULL, 20);
+    SPI.transfer(line2, NULL, 20);
+    SPI.transfer(line4, NULL, 20);
+
+    SPI.endTransaction();
+}
+
+void loop() {
+    // This example doesn't have any ongoing tasks to perform.
+}
+
+/*------------------------------------------------------------------------------
+ * SetBrightness
+ *
+ *    Sends a short SPI transaction to control the brightness of the attached
+ *    LCD screen. See the device's datasheet for a full set of commands and
+ *    syntax.
+ *
+ * Parameters:
+ *    uint8_t level  - The brightness level to be set
+ *
+ * Returns: None
+ */
+void SetBrightness(uint8_t level) {
+    SPI.beginTransaction(spiConfig);
+    SPI.transfer(0xfe);
+    SPI.transfer(0x53);
+    SPI.transfer(level);
+    SPI.endTransaction();
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * SetCursor
+ *
+ *    Sends a short SPI transaction to control the position of the device's
+ *    internal cursor that controls where characters are printed on the LCD
+ *    screen. See the device's datasheet for a full set of commands and syntax.
+ *
+ * Parameters:
+ *    uint8_t row  - The character row to move the cursor to.
+ *    uint8_t column  - The character column to move the cursor to.
+ *
+ * Returns: None
+ */
+void SetCursor(uint8_t row, uint8_t column) {
+    // Bounds-check the passed-in row and column
+    if (row >= NUM_ROWS) {
+        row = 0;
+    }
+    if (column >= NUM_COLUMNS) {
+        column = 0;
+    }
+
+    uint8_t position = row * NUM_COLUMNS + column;
+    SPI.beginTransaction(spiConfig);
+    SPI.transfer(0xfe);
+    SPI.transfer(0x45);
+    SPI.transfer(position);
+    SPI.endTransaction();
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/TtlSerialDisplay/TtlSerialDisplay.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/TtlSerialDisplay/TtlSerialDisplay.ino
new file mode 100644
index 000000000..51f651d10
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/TtlSerialDisplay/TtlSerialDisplay.ino
@@ -0,0 +1,116 @@
+/*
+ * Title: TtlSerialDisplay
+ *
+ * Objective:
+ *    This example demonstrates how to write data to a TTL device.
+ *
+ * Description:
+ *    This example will set up TTL communications on COM-0 then write various
+ *    data to the device.
+ *
+ * Requirements:
+ * ** A NHD-0420D3Z LCD display in TTL mode connected to COM-0.
+ *    Datasheet: http://www.newhavendisplay.com/specs/NHD-0420D3Z-NSW-BBW-V3.pdf
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Data bounds of the device
+#define NUM_ROWS 4
+#define NUM_COLUMNS 20
+
+// Sample data to write to the display
+const uint8_t line1[21] = "abcdefghijklmnopqrst";
+const uint8_t line2[21] = "ABCDEFGHIJKLMNOPQRST";
+const uint8_t line3[21] = "01234567890123456789";
+const uint8_t line4[21] = "98765432109876543210";
+
+// Declare our helper functions so that they may be used before they are defined
+void SetBrightness(uint8_t level);
+void SetCursor(uint8_t row, uint8_t column);
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    Serial0.begin(57600);
+    Serial0.ttl(true);
+
+    // The COM port is now configured and ready to send commands and
+    // data to the display
+
+    // Set the display brightness level.
+    // The maximum value for full brightness is 8.
+    SetBrightness(4);
+
+    // Set the cursor position to the top-left corner.
+    SetCursor(0, 0);
+
+    // Send the lines "out of order" (1, 3, 2, 4) to the display.
+    // Without resetting the cursor position for each line, this is the order
+    // in which lines must be sent to be displayed correctly.
+    Serial0.print((char *)line1);
+    Serial0.print((char *)line3);
+    Serial0.print((char *)line2);
+    Serial0.print((char *)line4);
+}
+
+void loop() {
+    // This example doesn't have any ongoing tasks to perform.
+}
+
+/*------------------------------------------------------------------------------
+ * SetBrightness
+ *
+ *    Sends a short group of data to control the brightness of the attached
+ *    LCD screen. See the device's datasheet for a full set of commands and
+ *    syntax.
+ *
+ * Parameters:
+ *    uint8_t level  - The brightness level to be set
+ *
+ * Returns: None
+ */
+void SetBrightness(uint8_t level) {
+    Serial0.write(0xfe);
+    Serial0.write(0x53);
+    Serial0.write(level);
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * SetCursor
+ *
+ *    Sends a short group of data to control the position of the device's
+ *    internal cursor that controls where characters are printed on the LCD
+ *    screen. See the device's datasheet for a full set of commands and syntax.
+ *
+ * Parameters:
+ *    uint8_t row  - The character row to move the cursor to.
+ *    uint8_t column  - The character column to move the cursor to.
+ *
+ * Returns: None
+ */
+void SetCursor(uint8_t row, uint8_t column) {
+    // Bounds-check the passed-in row and column
+    if (row >= NUM_ROWS) {
+        row = 0;
+    }
+
+    if (column >= NUM_COLUMNS) {
+        column = 0;
+    }
+
+    uint8_t position = row * NUM_COLUMNS + column;
+    Serial0.write(0xfe);
+    Serial0.write(0x45);
+    Serial0.write(position);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/library.properties
new file mode 100644
index 000000000..4fd9a63e4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/library.properties
@@ -0,0 +1,9 @@
+name=Serial Communication
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Serial Communication Examples
+paragraph=Teknic ClearCore Serial Communication Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/serial-comm-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/serial-comm-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/SerialCommunication/serial-comm-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/StepAndDirection/StepAndDirection.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/StepAndDirection/StepAndDirection.ino
new file mode 100644
index 000000000..fb6755f5e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/StepAndDirection/StepAndDirection.ino
@@ -0,0 +1,137 @@
+/*
+ * Title: StepAndDirection
+ *
+ * Objective:
+ *    This example demonstrates control of a third party Step and
+ *    Direction motor using a ClearCore motor connector.
+ *    This example is NOT intended to be used with ClearPath servos.
+ *    There are other examples created specifically for ClearPath.
+ *
+ * Description:
+ *    This example enables a motor then commands a series of repeating
+ *    moves to the motor.
+ *
+ * Requirements:
+ * 1. A motor capable of step and direction must be connected to Connector M-0.
+ * 2. The motor may optionally be connected to the MotorDriver's HLFB line if 
+ *    the motor has a "servo on" type feedback feature.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Define the velocity and acceleration limits to be used for each move
+int velocityLimit = 10000; // pulses per sec
+int accelerationLimit = 100000; // pulses per sec^2
+
+// Declares our user-defined helper function, which is used to command moves to
+// the motor. The definition/implementation of this function is at the  bottom
+// of the example.
+void MoveDistance(int distance);
+
+void setup() {
+    // Put your setup code here, it will only run once:
+
+    // Sets the input clocking rate.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // These lines may be uncommented to invert the output signals of the 
+    // Enable, Direction, and HLFB lines. Some motors may have input polarities 
+    // that are inverted from the ClearCore's polarity.
+    //motor.PolarityInvertSDEnable(true);
+    //motor.PolarityInvertSDDirection(true);
+    //motor.PolarityInvertSDHlfb(true);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(velocityLimit);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    Serial.begin(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = millis();
+    while (!Serial && millis() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor.
+    motor.EnableRequest(true);
+
+    // Waits for HLFB to assert. Uncomment these lines if your motor has a 
+    // "servo on" feature and it is wired to the HLFB line on the connector.
+    //Serial.println("Waiting for HLFB...");
+    //while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+    //    continue;
+    //}
+    Serial.println("Motor Ready");
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // Move 6400 counts (positive direction), then wait 2000ms
+    MoveDistance(6400);
+    delay(2000);
+    // Move 19200 counts farther positive, then wait 2000ms
+    MoveDistance(19200);
+    delay(2000);
+    // Move back 12800 counts (negative direction), then wait 2000ms
+    MoveDistance(-12800);
+    delay(2000);
+    // Move back 6400 counts (negative direction), then wait 2000ms
+    MoveDistance(-6400);
+    delay(2000);
+    // Move back to the start (negative 6400 pulses), then wait 2000ms
+    MoveDistance(-6400);
+    delay(2000);
+}
+
+/*------------------------------------------------------------------------------
+ * MoveDistance
+ *
+ *    Command "distance" number of step pulses away from the current position
+ *    Prints the move status to the USB serial port
+ *    Returns when step pulses have completed
+ *
+ * Parameters:
+ *    int distance  - The distance, in step pulses, to move
+ *
+ * Returns: None
+ */
+void MoveDistance(int distance) {
+    Serial.print("Moving distance: ");
+    Serial.println(distance);
+
+    // Command the move of incremental distance
+    motor.Move(distance);
+
+    // Waits for all step pulses to output
+    Serial.println("Moving... Waiting for the step output to finish...");
+    while (!motor.StepsComplete()) {
+        continue;
+    }
+
+    Serial.println("Steps Complete");
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/library.properties
new file mode 100644
index 000000000..79b385221
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/library.properties
@@ -0,0 +1,9 @@
+name=Step and Direction (non-ClearPath)
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore Step and Direction Examples
+paragraph=Teknic ClearCore Step and Direction Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/step-and-direction-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/step-and-direction-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/StepAndDirection/step-and-direction-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/WriteXbeeOutput/WriteXbeeOutput.ino b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/WriteXbeeOutput/WriteXbeeOutput.ino
new file mode 100644
index 000000000..ea78af61e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/WriteXbeeOutput/WriteXbeeOutput.ino
@@ -0,0 +1,63 @@
+/*
+ * Title: WriteXBeeOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write data to an XBee device conncted to
+ *    the ClearCore's XBee port.
+ *
+ * Description:   
+ *    This example sets up the XBee connector and writes data to the XBee 
+ *    device. Any data received is then read-in and written to the USB serial 
+ *    port.
+ *
+ * Requirements:
+ * ** An XBee device connected to ClearCore's XBee connector. Use the XBee in 
+ *    Transparent Mode to simply send and receive data without packet structuring.
+ * ** Another remote XBee, also in transparent mode and configured to communicate 
+ *    with the first.  
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// ClearCore provides three separate serial interfaces to send communications.
+// The three options are Serial (USB), Serial0 (COM-0), or Serial1 (COM-1)
+#define SerialPort Serial
+
+void setup() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication to print.
+    // A port must be open to continue and view incoming data.
+    SerialPort.begin(9600);
+    while (!SerialPort) {
+        continue;
+    }
+
+    //Uncomment the line below if you have turned RTS flow control on in the XBee's parameters
+    //XBee.FlowControl(true);
+
+    // Set the XBee communication speed and open the XBee port
+    XBee.Speed(115200);
+    XBee.PortOpen();
+
+    // Send a message to the XBee.
+    XBee.Send("Hello XBee");
+}
+
+void loop() {
+    // Put your main code here, it will run repeatedly:
+
+    // As long as there are characters to be read-in, print the character at the
+    // top of the receive buffer.
+    if (XBee.AvailableForRead()) {
+        SerialPort.println(XBee.CharGet());
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/library.properties b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/library.properties
new file mode 100644
index 000000000..2e8455563
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/library.properties
@@ -0,0 +1,9 @@
+name=XBee
+version=1.0.0
+author=Teknic
+maintainer=Teknic <sales@teknic.com>
+sentence=Teknic ClearCore XBee Examples
+paragraph=Teknic ClearCore XBee Examples
+category=Device Control
+url=https://github.com/Teknic-Inc/ClearCore-Arduino-wrapper
+architectures=sam
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/xbee-examples.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/xbee-examples.h
new file mode 100644
index 000000000..ff4816467
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/libraries/XBee/xbee-examples.h
@@ -0,0 +1,2 @@
+
+// This is just an empty header file to make this a valid Arduino library
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/package_clearcore_index.json b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/package_clearcore_index.json
new file mode 100644
index 000000000..4bbd48cac
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/package_clearcore_index.json
@@ -0,0 +1,106 @@
+{
+  "packages": [
+    {
+      "name": "ClearCore",
+      "maintainer": "Teknic, Inc",
+      "websiteURL": "https://www.teknic.com",
+      "email": "support@teknic.com",
+      "help": { "online": "https://www.teknic.com" },
+      "platforms": [
+        {
+          "name": "ClearCore",
+          "architecture": "sam",
+          "version": "1.0.14",
+          "category": "Contributed",
+          "help": { "online": "https://teknic-inc.github.io/ClearCore-library/" },
+          "url": "https://www.teknic.com/files/downloads/ClearCore-1.0.14.zip",
+          "archiveFileName": "ClearCore-1.0.14.zip",
+          "checksum": "MD5:30cf4782b0462715fbad1d20d2104ac7",
+          "size": "10401173",
+          "boards": [
+            {"name": "ClearCore"}
+          ],
+          "toolsDependencies": [
+            {
+              "packager": "arduino",
+              "name": "arm-none-eabi-gcc",
+              "version": "7-2017q4"
+            },
+            {
+              "packager": "arduino",
+              "name": "bossac",
+              "version": "1.9.1-arduino1"
+            },
+            {
+              "name": "CMSIS",
+              "packager": "arduino",
+              "version": "4.5.0"
+            }
+          ]
+        },
+        {
+          "name": "ClearCore",
+          "architecture": "sam",
+          "version": "1.1.1",
+          "category": "Contributed",
+          "help": { "online": "https://teknic-inc.github.io/ClearCore-library/" },
+          "url": "https://www.teknic.com/files/downloads/ClearCore-1.1.1.zip",
+          "archiveFileName": "ClearCore-1.1.1.zip",
+          "checksum": "MD5:f55b44cc0a880cce4eb8981a6fe564a6",
+          "size": "6441471",
+          "boards": [
+            {"name": "ClearCore"}
+          ],
+          "toolsDependencies": [
+            {
+              "packager": "arduino",
+              "name": "arm-none-eabi-gcc",
+              "version": "7-2017q4"
+            },
+            {
+              "packager": "arduino",
+              "name": "bossac",
+              "version": "1.9.1-arduino1"
+            },
+            {
+              "name": "CMSIS",
+              "packager": "arduino",
+              "version": "4.5.0"
+            }
+          ]
+        },
+        {
+          "name": "ClearCore",
+          "architecture": "sam",
+          "version": "1.1.2",
+          "category": "Contributed",
+          "help": { "online": "https://teknic-inc.github.io/ClearCore-library/" },
+          "url": "https://www.teknic.com/files/downloads/ClearCore-1.1.2.zip",
+          "archiveFileName": "ClearCore-1.1.2.zip",
+          "checksum": "MD5:230ae503582c98eba978c7b81c5c5634",
+          "size": "8120661",
+          "boards": [
+            {"name": "ClearCore"}
+          ],
+          "toolsDependencies": [
+            {
+              "packager": "arduino",
+              "name": "arm-none-eabi-gcc",
+              "version": "7-2017q4"
+            },
+            {
+              "packager": "arduino",
+              "name": "bossac",
+              "version": "1.9.1-arduino1"
+            },
+            {
+              "name": "CMSIS",
+              "packager": "arduino",
+              "version": "4.5.0"
+            }
+          ]
+        }
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/platform.txt b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/platform.txt
new file mode 100644
index 000000000..d75e13b66
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/platform.txt
@@ -0,0 +1,151 @@
+
+# Teknic Sam Core and platform.
+# ------------------------------
+#
+# For more info:
+# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5-3rd-party-Hardware-specification
+
+name=Teknic ClearCore board
+version=1.0.1
+
+# SAM compile variables
+# ---------------------
+
+compiler.warning_flags=-w
+compiler.warning_flags.none=-w
+compiler.warning_flags.default=
+compiler.warning_flags.more=-Wall
+compiler.warning_flags.all=-Wall -Wextra
+
+# Default "compiler.path" is correct, change only if you want to override the initial value
+compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
+compiler.opt_flags=-O3
+compiler.c.cmd=arm-none-eabi-gcc
+compiler.c.flags=-c -g {compiler.opt_flags} {compiler.warning_flags} -ffunction-sections -fdata-sections -std=gnu11 -mthumb -mcpu={build.mcu} -mfloat-abi={build.float} -mfpu={build.fpu} --param max-inline-insns-single=50 -MMD --specs=nosys.specs
+compiler.c.elf.cmd=arm-none-eabi-g++
+compiler.c.elf.flags= -Wl,--gc-sections
+compiler.S.cmd=arm-none-eabi-gcc
+compiler.S.flags=-c -g -x assembler-with-cpp -MMD
+compiler.cpp.cmd=arm-none-eabi-g++
+compiler.cpp.flags=-mthumb -mcpu={build.mcu} -mfloat-abi={build.float} -mfpu={build.fpu} -c -g {compiler.opt_flags} {compiler.warning_flags} -std=gnu++11 -ffunction-sections -fdata-sections -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -MMD
+compiler.ar.cmd=arm-none-eabi-ar
+compiler.ar.flags=rcs
+compiler.objcopy.cmd=arm-none-eabi-objcopy
+compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
+compiler.elf2hex.flags=-O binary
+compiler.elf2hex.cmd=arm-none-eabi-objcopy
+compiler.ldflags=-mthumb -mcpu={build.mcu} -mfloat-abi={build.float} -mfpu={build.fpu} -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,-Map,output.map
+compiler.size.cmd=arm-none-eabi-size
+
+# This can be overridden in boards.txt
+build.extra_flags=
+
+compiler.libsam.c.flags=-DUSBCON -DUSB_CONFIG_POWER=0 -D__CLEARCORE__ -D__SAME53N19A__ -DARM_MATH_CM4 "-I{build.core.path}/api" {compiler.arm.cmsis.c.flags} "-I{runtime.platform.path}/Teknic/libClearCore/inc" "-I{runtime.platform.path}/Teknic/LwIP/LwIP/src/include" "-I{runtime.platform.path}/Teknic/LwIP/LwIP/port/include" 
+
+# These can be overridden in platform.local.txt
+compiler.c.extra_flags=
+compiler.c.elf.extra_flags=
+compiler.S.extra_flags=
+compiler.cpp.extra_flags=-D__ARM_FEATURE_DSP=1 -DCPPUTEST_USE_MEM_LEAK_DETECTION=0
+compiler.ar.extra_flags=
+compiler.objcopy.eep.extra_flags=
+compiler.elf2hex.extra_flags=
+
+compiler.arm.cmsis.c.flags="-I{runtime.tools.CMSIS.path}/CMSIS/Include/" "-I{build.variant.path}/Third Party/SAME53/CMSIS/Device/Include"
+compiler.arm.cmsis.ldflags="-L{runtime.platform.path}/Teknic/libClearCore/Release" -lClearCore "-L{runtime.platform.path}/Teknic/LwIP/Release" -lLwIP "-L{runtime.tools.CMSIS.path}/CMSIS/Lib/GCC/" -larm_cortexM4lf_math
+
+# Compile patterns
+# --------------------
+
+## Compile c files
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -DF_CPU={build.f_cpu} -D__FPU_PRESENT=1 -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {compiler.libsam.c.flags} {includes} "{source_file}" -o "{object_file}"
+
+## Compile c++ files
+recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -DF_CPU={build.f_cpu}  -D__FPU_PRESENT=1 -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {compiler.libsam.c.flags} {includes} "{source_file}" -o "{object_file}"
+
+## Compile S files
+recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {compiler.libsam.c.flags} {includes} "{source_file}" -o "{object_file}"
+
+## Create archives
+# archive_file_path is needed for backwards compatibility with IDE 1.6.5 or older, IDE 1.6.6 or newer overrides this value
+archive_file_path={build.path}/{archive_file}
+recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
+
+## Linker: Combine gc-sections, archives, and objects
+recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mthumb -mcpu={build.mcu} -mfloat-abi={build.float} -mfpu={build.fpu} {compiler.c.elf.extra_flags} -specs=rdimon.specs -o "{build.path}/{build.project_name}.elf" "-T{build.variant.path}/{build.ldscript}" {object_files} "{build.path}/{archive_file}" {compiler.arm.cmsis.ldflags} -lm -Xlinker -Map={build.path}/{build.project_name}.map
+
+## Create output files (.eep and .bin)
+recipe.objcopy.eep.pattern="{compiler.path}{compiler.objcopy.cmd}" {compiler.objcopy.eep.flags} {compiler.objcopy.eep.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.eep"
+recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.bin"
+
+## Compute size
+recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf"
+recipe.size.regex=^(?:\.text|\.data|\.bootloader)\s+([0-9]+).*
+recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*
+recipe.size.regex.eeprom=^(?:\.eeprom)\s+([0-9]+).*
+
+## Save hex
+recipe.output.tmp_file={build.project_name}.hex
+recipe.output.save_file={build.project_name}.{build.variant}.hex
+
+## Preprocessor
+#preproc.includes.flags=-w -x c++ -M -MG -MP
+#recipe.preproc.includes="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.includes.flags} -mcpu={build.mcu} -mfloat-abi={build.float} -mfpu={build.fpu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -save-temps -D__FPU_PRESENT=1
+
+#preproc.macros.flags=-w -x c++ -E -CC
+#recipe.preproc.macros="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} {preproc.macros.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {compiler.libsam.c.flags} {includes} "{source_file}" -o "{preprocessed_file_path}"
+#-mmcu={build.mcu}
+
+# SAM Uploader/Programmers tools
+# ------------------------------
+
+# BOSSA
+
+tools.bossac.path={runtime.tools.bossac.path}
+#tools.bossac.path={runtime.platform.path}/Teknic/Tools/bossac
+tools.bossac.cmd=bossac
+tools.bossac.cmd.windows=bossac.exe
+tools.bossac.cmd.path={path}bossac
+
+tools.bossac.upload.params.verbose=-i -d
+tools.bossac.upload.params.quiet=
+tools.bossac.upload.pattern="{path}/{cmd}" {upload.verbose} --port={serial.port.file} -U -e -w -v --offset={upload.offset} "{build.path}/{build.project_name}.bin" -R
+tools.bossac.upload.native_usb=true
+#tools.bossac_remote.upload.pattern=/usr/bin/run-bossac {upload.verbose} --port=ttyATH0 -U -e -w -v -b /tmp/sketch.bin -R
+
+#tools.bossac.upload.network_pattern="{network_cmd}" -address {serial.port} -port 65280 -username arduino -password "{network.password}" -sketch "{build.path}/{build.project_name}.bin" -upload /sketch -b
+#tools.bossac.upload.verify=
+#tools.bossac.upload.params.noverify=-V
+#tools.bossac.network_cmd={runtime.tools.arduinoOTA.path}/bin/arduinoOTA
+
+# OpenOCD sketch upload
+
+tools.openocd.path={runtime.tools.openocd.path}
+tools.openocd.cmd=bin/openocd
+tools.openocd.cmd.windows=bin/openocd.exe
+
+tools.openocd.upload.params.verbose=-d2
+tools.openocd.upload.params.quiet=-d0
+tools.openocd.upload.pattern="{path}/{cmd}" {upload.verbose} -s "{path}/share/openocd/scripts/" -f "{runtime.platform.path}/variants/{build.variant}/{build.openocdscript}" -c "telnet_port disabled; program {build.path}/{build.project_name}.bin verify reset {bootloader.size}; shutdown"
+
+#tools.openocd.network_cmd={runtime.tools.arduinoOTA.path}/bin/arduinoOTA
+#tools.openocd.upload.network_pattern={network_cmd} -address {serial.port} -port 65280 -username arduino -password "{network.password}" -sketch "{build.path}/{build.project_name}.bin" -upload /sketch -b
+
+tools.openocd.program.params.verbose=-d2
+tools.openocd.program.params.quiet=-d0
+tools.openocd.program.pattern="{path}/{cmd}" {program.verbose} -s "{path}/share/openocd/scripts/" -f "{runtime.platform.path}/variants/{build.variant}/{build.openocdscript}" -c "telnet_port disabled; program {build.path}/{build.project_name}.elf verify reset; shutdown"
+
+tools.openocd.erase.params.verbose=-d3
+tools.openocd.erase.params.quiet=-d0
+tools.openocd.erase.pattern=
+
+tools.openocd.bootloader.params.verbose=-d2
+tools.openocd.bootloader.params.quiet=-d0
+tools.openocd.bootloader.pattern="{path}/{cmd}" {bootloader.verbose} -s "{path}/share/openocd/scripts/" -f "{runtime.platform.path}/variants/{build.variant}/{build.openocdscript}" -c "telnet_port disabled; init; halt; at91samd bootloader 0; program {runtime.platform.path}/bootloaders/{bootloader.file} verify; reset; shutdown"
+
+
+## USB Default Flags
+## Default blank usb manufacturer will be filled in at compile time
+## - from numeric vendor ID, set to Unknown otherwise
+#build.usb_manufacturer="Unknown"
+build.usb_flags=-DUSB_VID={build.vid} -DUSB_PID={build.pid} '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}'
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component-version.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component-version.h
new file mode 100644
index 000000000..50056eee2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component-version.h	
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Component version header file
+ *
+ * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \license_stop
+ *
+ */
+
+#ifndef _COMPONENT_VERSION_H_INCLUDED
+#define _COMPONENT_VERSION_H_INCLUDED
+
+#define COMPONENT_VERSION_MAJOR 1
+#define COMPONENT_VERSION_MINOR 1
+
+//
+// The COMPONENT_VERSION define is composed of the major and the minor version number.
+//
+// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
+// The rest of the COMPONENT_VERSION is the major version.
+//
+#define COMPONENT_VERSION 10001
+
+//
+// The build number does not refer to the component, but to the build number
+// of the device pack that provides the component.
+//
+#define BUILD_NUMBER 118
+
+//
+// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
+//
+#define COMPONENT_VERSION_STRING "1.1"
+
+//
+// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
+//
+// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
+//
+//     "%Y-%m-%d %H:%M:%S"
+//
+//
+#define COMPONENT_DATE_STRING "2019-04-09 08:16:24"
+
+#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ac.h
new file mode 100644
index 000000000..96c6ecb4c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ac.h	
@@ -0,0 +1,598 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_AC_COMPONENT_
+#define _SAME53_AC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAME53_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2501
+#define REV_AC                      0x100
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE         _U_(0x00)    /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST              (_U_(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE             (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_MASK               _U_(0x03)    /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
+    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE         _U_(0x00)    /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0             (_U_(1) << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1             (_U_(1) << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk          (_U_(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK               _U_(0x03)    /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
+    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input Enable    */
+    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input Enable    */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t INVEI0:1;         /*!< bit:     12  Comparator 0 Input Event Invert Enable */
+    uint16_t INVEI1:1;         /*!< bit:     13  Comparator 1 Input Event Invert Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input Enable    */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t INVEI:2;          /*!< bit: 12..13  Comparator x Input Event Invert Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE        _U_(0x0000)  /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0           (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1           (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk        (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0            (_U_(1) << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk         (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
+#define AC_EVCTRL_COMPEI0           (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
+#define AC_EVCTRL_COMPEI1           (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
+#define AC_EVCTRL_COMPEI_Msk        (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_INVEI0_Pos        12           /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI0            (_U_(1) << AC_EVCTRL_INVEI0_Pos)
+#define AC_EVCTRL_INVEI1_Pos        13           /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI1            (_U_(1) << AC_EVCTRL_INVEI1_Pos)
+#define AC_EVCTRL_INVEI_Pos         12           /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
+#define AC_EVCTRL_INVEI_Msk         (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
+#define AC_EVCTRL_INVEI(value)      (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
+#define AC_EVCTRL_MASK              _U_(0x3313)  /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0           (_U_(1) << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1           (_U_(1) << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk        (_U_(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0            (_U_(1) << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk         (_U_(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK            _U_(0x13)    /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0           (_U_(1) << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1           (_U_(1) << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk        (_U_(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0            (_U_(1) << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk         (_U_(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK            _U_(0x13)    /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
+    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0            (_U_(1) << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1            (_U_(1) << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk         (_U_(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0             (_U_(1) << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk          (_U_(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK             _U_(0x13)    /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x07) (R/   8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET           0x07         /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE       _U_(0x00)    /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0           (_U_(1) << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1           (_U_(1) << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk        (_U_(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk      (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    _U_(0x0)   /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   _U_(0x1)   /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    _U_(0x2)   /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK             _U_(0x33)    /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x08) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
+    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET           0x08         /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE       _U_(0x00)    /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0           (_U_(1) << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1           (_U_(1) << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk        (_U_(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_MASK             _U_(0x03)    /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_DBGCTRL_OFFSET           0x09         /**< \brief (AC_DBGCTRL offset) Debug Control */
+#define AC_DBGCTRL_RESETVALUE       _U_(0x00)    /**< \brief (AC_DBGCTRL reset_value) Debug Control */
+
+#define AC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (AC_DBGCTRL) Debug Run */
+#define AC_DBGCTRL_DBGRUN           (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
+#define AC_DBGCTRL_MASK             _U_(0x01)    /**< \brief (AC_DBGCTRL) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W  8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
+    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET           0x0A         /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE       _U_(0x00)    /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0             (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk     (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   _U_(0x0)   /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  _U_(0x1)   /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   _U_(0x2)   /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3)   /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK             _U_(0x07)    /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W  8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET            0x0C         /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE        _U_(0x00)    /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk         (_U_(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK              _U_(0x3F)    /**< \brief (AC_SCALER) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t SINGLE:1;         /*!< bit:      2  Single-Shot Mode                   */
+    uint32_t INTSEL:2;         /*!< bit:  3.. 4  Interrupt Selection                */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t MUXPOS:3;         /*!< bit: 12..14  Positive Input Mux Selection       */
+    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
+    uint32_t SPEED:2;          /*!< bit: 16..17  Speed Selection                    */
+    uint32_t :1;               /*!< bit:     18  Reserved                           */
+    uint32_t HYSTEN:1;         /*!< bit:     19  Hysteresis Enable                  */
+    uint32_t HYST:2;           /*!< bit: 20..21  Hysteresis Level                   */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t OUT:2;            /*!< bit: 28..29  Output                             */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos      1            /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE          (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos      2            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE          (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_INTSEL_Pos      3            /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk      (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   _U_(0x0)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   _U_(0x1)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  _U_(0x2)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      _U_(0x3)   /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_RUNSTDBY_Pos    6            /**< \brief (AC_COMPCTRL) Run in Standby */
+#define AC_COMPCTRL_RUNSTDBY        (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk      (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     _U_(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      _U_(0x4)   /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   _U_(0x5)   /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  _U_(0x6)   /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      _U_(0x7)   /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk      (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     _U_(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXPOS_VSCALE_Val   _U_(0x4)   /**< \brief (AC_COMPCTRL) VDD Scaler */
+#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_VSCALE   (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP            (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_SPEED_Pos       16           /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk       (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define   AC_COMPCTRL_SPEED_HIGH_Val      _U_(0x3)   /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_HYSTEN_Pos      19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYSTEN          (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
+#define AC_COMPCTRL_HYST_Pos        20           /**< \brief (AC_COMPCTRL) Hysteresis Level */
+#define AC_COMPCTRL_HYST_Msk        (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST(value)     (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
+#define   AC_COMPCTRL_HYST_HYST50_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) 50mV */
+#define   AC_COMPCTRL_HYST_HYST100_Val    _U_(0x1)   /**< \brief (AC_COMPCTRL) 100mV */
+#define   AC_COMPCTRL_HYST_HYST150_Val    _U_(0x2)   /**< \brief (AC_COMPCTRL) 150mV */
+#define AC_COMPCTRL_HYST_HYST50     (AC_COMPCTRL_HYST_HYST50_Val   << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST100    (AC_COMPCTRL_HYST_HYST100_Val  << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST150    (AC_COMPCTRL_HYST_HYST150_Val  << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk        (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define   AC_COMPCTRL_FLEN_OFF_Val        _U_(0x0)   /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       _U_(0x1)   /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       _U_(0x2)   /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_OUT_Pos         28           /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk         (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define   AC_COMPCTRL_OUT_OFF_Val         _U_(0x0)   /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       _U_(0x1)   /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        _U_(0x2)   /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_MASK            _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint32_t WINCTRL:1;        /*!< bit:      2  WINCTRL Synchronization Busy       */
+    uint32_t COMPCTRL0:1;      /*!< bit:      3  COMPCTRL 0 Synchronization Busy    */
+    uint32_t COMPCTRL1:1;      /*!< bit:      4  COMPCTRL 1 Synchronization Busy    */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :3;               /*!< bit:  0.. 2  Reserved                           */
+    uint32_t COMPCTRL:2;       /*!< bit:  3.. 4  COMPCTRL x Synchronization Busy    */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SYNCBUSY_OFFSET          0x20         /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
+#define AC_SYNCBUSY_RESETVALUE      _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define AC_SYNCBUSY_SWRST_Pos       0            /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
+#define AC_SYNCBUSY_SWRST           (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
+#define AC_SYNCBUSY_ENABLE_Pos      1            /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
+#define AC_SYNCBUSY_ENABLE          (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
+#define AC_SYNCBUSY_WINCTRL_Pos     2            /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
+#define AC_SYNCBUSY_WINCTRL         (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL0_Pos   3            /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL0       (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
+#define AC_SYNCBUSY_COMPCTRL1_Pos   4            /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL1       (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
+#define AC_SYNCBUSY_COMPCTRL_Pos    3            /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL_Msk    (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
+#define AC_SYNCBUSY_MASK            _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
+
+/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BIAS0:2;          /*!< bit:  0.. 1  COMP0/1 Bias Scaling               */
+    uint16_t :14;              /*!< bit:  2..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CALIB_OFFSET             0x24         /**< \brief (AC_CALIB offset) Calibration */
+#define AC_CALIB_RESETVALUE         _U_(0x0101)  /**< \brief (AC_CALIB reset_value) Calibration */
+
+#define AC_CALIB_BIAS0_Pos          0            /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
+#define AC_CALIB_BIAS0_Msk          (_U_(0x3) << AC_CALIB_BIAS0_Pos)
+#define AC_CALIB_BIAS0(value)       (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
+#define AC_CALIB_MASK               _U_(0x0003)  /**< \brief (AC_CALIB) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
+  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
+  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x07 (R/   8) Status A */
+  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x08 (R/   8) Status B */
+  __IO AC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x09 (R/W  8) Debug Control */
+  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0A (R/W  8) Window Control */
+       RoReg8                    Reserved1[0x1];
+  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x0C (R/W  8) Scaler n */
+       RoReg8                    Reserved2[0x2];
+  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+       RoReg8                    Reserved3[0x8];
+  __I  AC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x20 (R/  32) Synchronization Busy */
+  __IO AC_CALIB_Type             CALIB;       /**< \brief Offset: 0x24 (R/W 16) Calibration */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_AC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/adc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/adc.h
new file mode 100644
index 000000000..b8476ee45
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/adc.h	
@@ -0,0 +1,871 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_ADC_COMPONENT_
+#define _SAME53_ADC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAME53_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2500
+#define REV_ADC                     0x100
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t :1;               /*!< bit:      2  Reserved                           */
+    uint16_t DUALSEL:2;        /*!< bit:  3.. 4  Dual Mode Trigger Selection        */
+    uint16_t SLAVEEN:1;        /*!< bit:      5  Slave Enable                       */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
+    uint16_t :4;               /*!< bit: 11..14  Reserved                           */
+    uint16_t R2R:1;            /*!< bit:     15  Rail to Rail Operation Enable      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST             (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE            (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_DUALSEL_Pos       3            /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
+#define ADC_CTRLA_DUALSEL_Msk       (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_DUALSEL(value)    (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
+#define   ADC_CTRLA_DUALSEL_BOTH_Val      _U_(0x0)   /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
+#define   ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1)   /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
+#define ADC_CTRLA_DUALSEL_BOTH      (ADC_CTRLA_DUALSEL_BOTH_Val    << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
+#define ADC_CTRLA_SLAVEEN_Pos       5            /**< \brief (ADC_CTRLA) Slave Enable */
+#define ADC_CTRLA_SLAVEEN           (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos      6            /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY          (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_ONDEMAND_Pos      7            /**< \brief (ADC_CTRLA) On Demand Control */
+#define ADC_CTRLA_ONDEMAND          (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
+#define ADC_CTRLA_PRESCALER_Pos     8            /**< \brief (ADC_CTRLA) Prescaler Configuration */
+#define ADC_CTRLA_PRESCALER_Msk     (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER(value)  (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
+#define   ADC_CTRLA_PRESCALER_DIV2_Val    _U_(0x0)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
+#define   ADC_CTRLA_PRESCALER_DIV4_Val    _U_(0x1)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
+#define   ADC_CTRLA_PRESCALER_DIV8_Val    _U_(0x2)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
+#define   ADC_CTRLA_PRESCALER_DIV16_Val   _U_(0x3)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
+#define   ADC_CTRLA_PRESCALER_DIV32_Val   _U_(0x4)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
+#define   ADC_CTRLA_PRESCALER_DIV64_Val   _U_(0x5)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
+#define   ADC_CTRLA_PRESCALER_DIV128_Val  _U_(0x6)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
+#define   ADC_CTRLA_PRESCALER_DIV256_Val  _U_(0x7)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
+#define ADC_CTRLA_PRESCALER_DIV2    (ADC_CTRLA_PRESCALER_DIV2_Val  << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV4    (ADC_CTRLA_PRESCALER_DIV4_Val  << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV8    (ADC_CTRLA_PRESCALER_DIV8_Val  << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV16   (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV32   (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV64   (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV128  (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_PRESCALER_DIV256  (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
+#define ADC_CTRLA_R2R_Pos           15           /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
+#define ADC_CTRLA_R2R               (_U_(0x1) << ADC_CTRLA_R2R_Pos)
+#define ADC_CTRLA_MASK              _U_(0x87FB)  /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSHEI:1;        /*!< bit:      0  Flush Event Input Enable           */
+    uint8_t  STARTEI:1;        /*!< bit:      1  Start Conversion Event Input Enable */
+    uint8_t  FLUSHINV:1;       /*!< bit:      2  Flush Event Invert Enable          */
+    uint8_t  STARTINV:1;       /*!< bit:      3  Start Conversion Event Invert Enable */
+    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
+    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET           0x02         /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_FLUSHEI_Pos      0            /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
+#define ADC_EVCTRL_FLUSHEI          (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
+#define ADC_EVCTRL_STARTEI_Pos      1            /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
+#define ADC_EVCTRL_STARTEI          (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_FLUSHINV_Pos     2            /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
+#define ADC_EVCTRL_FLUSHINV         (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
+#define ADC_EVCTRL_STARTINV_Pos     3            /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
+#define ADC_EVCTRL_STARTINV         (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO         (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO         (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             _U_(0x3F)    /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET          0x03         /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN          (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
+    uint16_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint16_t DIFFMODE:1;       /*!< bit:      7  Differential Mode                  */
+    uint16_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
+    uint16_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint16_t DSEQSTOP:1;       /*!< bit:     15  Stop DMA Sequencing                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET        0x04         /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE    _U_(0x0000)  /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define   ADC_INPUTCTRL_MUXPOS_AIN0_Val   _U_(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN1_Val   _U_(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN2_Val   _U_(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN3_Val   _U_(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN4_Val   _U_(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN5_Val   _U_(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN6_Val   _U_(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN7_Val   _U_(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN8_Val   _U_(0x8)   /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN9_Val   _U_(0x9)   /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN10_Val  _U_(0xA)   /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN11_Val  _U_(0xB)   /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN12_Val  _U_(0xC)   /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN13_Val  _U_(0xD)   /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN14_Val  _U_(0xE)   /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN15_Val  _U_(0xF)   /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN16_Val  _U_(0x10)   /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN17_Val  _U_(0x11)   /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN18_Val  _U_(0x12)   /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN19_Val  _U_(0x13)   /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN20_Val  _U_(0x14)   /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN21_Val  _U_(0x15)   /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN22_Val  _U_(0x16)   /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN23_Val  _U_(0x17)   /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B)   /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_PTAT_Val   _U_(0x1C)   /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define   ADC_INPUTCTRL_MUXPOS_CTAT_Val   _U_(0x1D)   /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    _U_(0x1E)   /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define   ADC_INPUTCTRL_MUXPOS_PTC_Val    _U_(0x1F)   /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
+#define ADC_INPUTCTRL_MUXPOS_AIN0   (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN1   (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN2   (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN3   (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN4   (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN5   (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN6   (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN7   (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN8   (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN9   (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN10  (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN11  (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN12  (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN13  (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN14  (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN15  (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN16  (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN17  (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN18  (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN19  (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN20  (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN21  (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN22  (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN23  (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PTAT   (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_CTAT   (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PTC    (ADC_INPUTCTRL_MUXPOS_PTC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_DIFFMODE_Pos  7            /**< \brief (ADC_INPUTCTRL) Differential Mode */
+#define ADC_INPUTCTRL_DIFFMODE      (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define   ADC_INPUTCTRL_MUXNEG_AIN0_Val   _U_(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN1_Val   _U_(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN2_Val   _U_(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN3_Val   _U_(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN4_Val   _U_(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN5_Val   _U_(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN6_Val   _U_(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN7_Val   _U_(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    _U_(0x18)   /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_AIN0   (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN1   (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN2   (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN3   (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN4   (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN5   (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN6   (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN7   (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_DSEQSTOP_Pos  15           /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
+#define ADC_INPUTCTRL_DSEQSTOP      (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
+#define ADC_INPUTCTRL_MASK          _U_(0x9F9F)  /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LEFTADJ:1;        /*!< bit:      0  Left-Adjusted Result               */
+    uint16_t FREERUN:1;        /*!< bit:      1  Free Running Mode                  */
+    uint16_t CORREN:1;         /*!< bit:      2  Digital Correction Logic Enable    */
+    uint16_t RESSEL:2;         /*!< bit:  3.. 4  Conversion Result Resolution       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t WINMODE:3;        /*!< bit:  8..10  Window Monitor Mode                */
+    uint16_t WINSS:1;          /*!< bit:     11  Window Single Sample               */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET            0x06         /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_LEFTADJ_Pos       0            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ           (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos       1            /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN           (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos        2            /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
+#define ADC_CTRLB_CORREN            (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos        3            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk        (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define   ADC_CTRLB_RESSEL_12BIT_Val      _U_(0x0)   /**< \brief (ADC_CTRLB) 12-bit result */
+#define   ADC_CTRLB_RESSEL_16BIT_Val      _U_(0x1)   /**< \brief (ADC_CTRLB) For averaging mode output */
+#define   ADC_CTRLB_RESSEL_10BIT_Val      _U_(0x2)   /**< \brief (ADC_CTRLB) 10-bit result */
+#define   ADC_CTRLB_RESSEL_8BIT_Val       _U_(0x3)   /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_WINMODE_Pos       8            /**< \brief (ADC_CTRLB) Window Monitor Mode */
+#define ADC_CTRLB_WINMODE_Msk       (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE(value)    (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
+#define   ADC_CTRLB_WINMODE_DISABLE_Val   _U_(0x0)   /**< \brief (ADC_CTRLB) No window mode (default) */
+#define   ADC_CTRLB_WINMODE_MODE1_Val     _U_(0x1)   /**< \brief (ADC_CTRLB) RESULT > WINLT */
+#define   ADC_CTRLB_WINMODE_MODE2_Val     _U_(0x2)   /**< \brief (ADC_CTRLB) RESULT < WINUT */
+#define   ADC_CTRLB_WINMODE_MODE3_Val     _U_(0x3)   /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
+#define   ADC_CTRLB_WINMODE_MODE4_Val     _U_(0x4)   /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
+#define ADC_CTRLB_WINMODE_DISABLE   (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE1     (ADC_CTRLB_WINMODE_MODE1_Val   << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE2     (ADC_CTRLB_WINMODE_MODE2_Val   << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE3     (ADC_CTRLB_WINMODE_MODE3_Val   << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINMODE_MODE4     (ADC_CTRLB_WINMODE_MODE4_Val   << ADC_CTRLB_WINMODE_Pos)
+#define ADC_CTRLB_WINSS_Pos         11           /**< \brief (ADC_CTRLB) Window Single Sample */
+#define ADC_CTRLB_WINSS             (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
+#define ADC_CTRLB_MASK              _U_(0x0F1F)  /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W  8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET          0x08         /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk      (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define   ADC_REFCTRL_REFSEL_INTREF_Val   _U_(0x0)   /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  _U_(0x2)   /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  _U_(0x3)   /**< \brief (ADC_REFCTRL) VDDANA */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    _U_(0x4)   /**< \brief (ADC_REFCTRL) External Reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    _U_(0x5)   /**< \brief (ADC_REFCTRL) External Reference */
+#define   ADC_REFCTRL_REFSEL_AREFC_Val    _U_(0x6)   /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
+#define ADC_REFCTRL_REFSEL_INTREF   (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFC    (ADC_REFCTRL_REFSEL_AREFC_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP         (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            _U_(0x8F)    /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W  8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
+    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET          0x0A         /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     _U_(0x0)   /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     _U_(0x1)   /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     _U_(0x2)   /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     _U_(0x3)   /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    _U_(0x4)   /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    _U_(0x5)   /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    _U_(0x6)   /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   _U_(0x7)   /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   _U_(0x8)   /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   _U_(0x9)   /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  _U_(0xA)   /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk      (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK            _U_(0x7F)    /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W  8) Sample Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  OFFCOMP:1;        /*!< bit:      7  Comparator Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET         0x0B         /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     _U_(0x00)    /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_OFFCOMP_Pos    7            /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
+#define ADC_SAMPCTRL_OFFCOMP        (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
+#define ADC_SAMPCTRL_MASK           _U_(0xBF)    /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET            0x0C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk         (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK              _U_(0xFFFF)  /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET            0x0E         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk         (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK              _U_(0xFFFF)  /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET         0x10         /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     _U_(0x0000)  /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk   (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK           _U_(0x0FFF)  /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET       0x12         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   _U_(0x0000)  /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK         _U_(0x0FFF)  /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W  8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
+    uint8_t  START:1;          /*!< bit:      1  Start ADC Conversion               */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET           0x14         /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       _U_(0x00)    /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH            (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) Start ADC Conversion */
+#define ADC_SWTRIG_START            (_U_(0x1) << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             _U_(0x03)    /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Disable     */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Disable          */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Disable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET         0x2C         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
+#define ADC_INTENCLR_RESRDY         (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
+#define ADC_INTENCLR_OVERRUN        (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
+#define ADC_INTENCLR_WINMON         (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_MASK           _U_(0x07)    /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET         0x2D         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY         (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN        (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON         (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_MASK           _U_(0x07)    /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Flag        */
+    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Flag             */
+    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Flag      */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET          0x2E         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
+#define ADC_INTFLAG_RESRDY          (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
+#define ADC_INTFLAG_OVERRUN         (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
+#define ADC_INTFLAG_WINMON          (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_MASK            _U_(0x07)    /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ADCBUSY:1;        /*!< bit:      0  ADC Busy Status                    */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  WCC:6;            /*!< bit:  2.. 7  Window Comparator Counter          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET           0x2F         /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE       _U_(0x00)    /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_ADCBUSY_Pos      0            /**< \brief (ADC_STATUS) ADC Busy Status */
+#define ADC_STATUS_ADCBUSY          (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
+#define ADC_STATUS_WCC_Pos          2            /**< \brief (ADC_STATUS) Window Comparator Counter */
+#define ADC_STATUS_WCC_Msk          (_U_(0x3F) << ADC_STATUS_WCC_Pos)
+#define ADC_STATUS_WCC(value)       (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
+#define ADC_STATUS_MASK             _U_(0xFD)    /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  SWRST Synchronization Busy         */
+    uint32_t ENABLE:1;         /*!< bit:      1  ENABLE Synchronization Busy        */
+    uint32_t INPUTCTRL:1;      /*!< bit:      2  Input Control Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      3  Control B Synchronization Busy     */
+    uint32_t REFCTRL:1;        /*!< bit:      4  Reference Control Synchronization Busy */
+    uint32_t AVGCTRL:1;        /*!< bit:      5  Average Control Synchronization Busy */
+    uint32_t SAMPCTRL:1;       /*!< bit:      6  Sampling Time Control Synchronization Busy */
+    uint32_t WINLT:1;          /*!< bit:      7  Window Monitor Lower Threshold Synchronization Busy */
+    uint32_t WINUT:1;          /*!< bit:      8  Window Monitor Upper Threshold Synchronization Busy */
+    uint32_t GAINCORR:1;       /*!< bit:      9  Gain Correction Synchronization Busy */
+    uint32_t OFFSETCORR:1;     /*!< bit:     10  Offset Correction Synchronization Busy */
+    uint32_t SWTRIG:1;         /*!< bit:     11  Software Trigger Synchronization Busy */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SYNCBUSY_OFFSET         0x30         /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
+#define ADC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define ADC_SYNCBUSY_SWRST_Pos      0            /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
+#define ADC_SYNCBUSY_SWRST          (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
+#define ADC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
+#define ADC_SYNCBUSY_ENABLE         (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
+#define ADC_SYNCBUSY_INPUTCTRL_Pos  2            /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
+#define ADC_SYNCBUSY_INPUTCTRL      (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
+#define ADC_SYNCBUSY_CTRLB_Pos      3            /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
+#define ADC_SYNCBUSY_CTRLB          (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
+#define ADC_SYNCBUSY_REFCTRL_Pos    4            /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
+#define ADC_SYNCBUSY_REFCTRL        (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
+#define ADC_SYNCBUSY_AVGCTRL_Pos    5            /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
+#define ADC_SYNCBUSY_AVGCTRL        (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
+#define ADC_SYNCBUSY_SAMPCTRL_Pos   6            /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
+#define ADC_SYNCBUSY_SAMPCTRL       (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
+#define ADC_SYNCBUSY_WINLT_Pos      7            /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
+#define ADC_SYNCBUSY_WINLT          (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
+#define ADC_SYNCBUSY_WINUT_Pos      8            /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
+#define ADC_SYNCBUSY_WINUT          (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
+#define ADC_SYNCBUSY_GAINCORR_Pos   9            /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
+#define ADC_SYNCBUSY_GAINCORR       (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
+#define ADC_SYNCBUSY_OFFSETCORR_Pos 10           /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
+#define ADC_SYNCBUSY_OFFSETCORR     (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
+#define ADC_SYNCBUSY_SWTRIG_Pos     11           /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
+#define ADC_SYNCBUSY_SWTRIG         (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
+#define ADC_SYNCBUSY_MASK           _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
+
+/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  DMA Sequential Data                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_DSEQDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQDATA_OFFSET         0x34         /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
+#define ADC_DSEQDATA_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
+
+#define ADC_DSEQDATA_DATA_Pos       0            /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
+#define ADC_DSEQDATA_DATA_Msk       (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
+#define ADC_DSEQDATA_DATA(value)    (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
+#define ADC_DSEQDATA_MASK           _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
+
+/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t INPUTCTRL:1;      /*!< bit:      0  Input Control                      */
+    uint32_t CTRLB:1;          /*!< bit:      1  Control B                          */
+    uint32_t REFCTRL:1;        /*!< bit:      2  Reference Control                  */
+    uint32_t AVGCTRL:1;        /*!< bit:      3  Average Control                    */
+    uint32_t SAMPCTRL:1;       /*!< bit:      4  Sampling Time Control              */
+    uint32_t WINLT:1;          /*!< bit:      5  Window Monitor Lower Threshold     */
+    uint32_t WINUT:1;          /*!< bit:      6  Window Monitor Upper Threshold     */
+    uint32_t GAINCORR:1;       /*!< bit:      7  Gain Correction                    */
+    uint32_t OFFSETCORR:1;     /*!< bit:      8  Offset Correction                  */
+    uint32_t :22;              /*!< bit:  9..30  Reserved                           */
+    uint32_t AUTOSTART:1;      /*!< bit:     31  ADC Auto-Start Conversion          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_DSEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQCTRL_OFFSET         0x38         /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
+#define ADC_DSEQCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
+
+#define ADC_DSEQCTRL_INPUTCTRL_Pos  0            /**< \brief (ADC_DSEQCTRL) Input Control */
+#define ADC_DSEQCTRL_INPUTCTRL      (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
+#define ADC_DSEQCTRL_CTRLB_Pos      1            /**< \brief (ADC_DSEQCTRL) Control B */
+#define ADC_DSEQCTRL_CTRLB          (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
+#define ADC_DSEQCTRL_REFCTRL_Pos    2            /**< \brief (ADC_DSEQCTRL) Reference Control */
+#define ADC_DSEQCTRL_REFCTRL        (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
+#define ADC_DSEQCTRL_AVGCTRL_Pos    3            /**< \brief (ADC_DSEQCTRL) Average Control */
+#define ADC_DSEQCTRL_AVGCTRL        (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
+#define ADC_DSEQCTRL_SAMPCTRL_Pos   4            /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
+#define ADC_DSEQCTRL_SAMPCTRL       (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
+#define ADC_DSEQCTRL_WINLT_Pos      5            /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
+#define ADC_DSEQCTRL_WINLT          (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
+#define ADC_DSEQCTRL_WINUT_Pos      6            /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
+#define ADC_DSEQCTRL_WINUT          (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
+#define ADC_DSEQCTRL_GAINCORR_Pos   7            /**< \brief (ADC_DSEQCTRL) Gain Correction */
+#define ADC_DSEQCTRL_GAINCORR       (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
+#define ADC_DSEQCTRL_OFFSETCORR_Pos 8            /**< \brief (ADC_DSEQCTRL) Offset Correction */
+#define ADC_DSEQCTRL_OFFSETCORR     (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
+#define ADC_DSEQCTRL_AUTOSTART_Pos  31           /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
+#define ADC_DSEQCTRL_AUTOSTART      (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
+#define ADC_DSEQCTRL_MASK           _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
+
+/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/  32) DMA Sequencial Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t INPUTCTRL:1;      /*!< bit:      0  Input Control                      */
+    uint32_t CTRLB:1;          /*!< bit:      1  Control B                          */
+    uint32_t REFCTRL:1;        /*!< bit:      2  Reference Control                  */
+    uint32_t AVGCTRL:1;        /*!< bit:      3  Average Control                    */
+    uint32_t SAMPCTRL:1;       /*!< bit:      4  Sampling Time Control              */
+    uint32_t WINLT:1;          /*!< bit:      5  Window Monitor Lower Threshold     */
+    uint32_t WINUT:1;          /*!< bit:      6  Window Monitor Upper Threshold     */
+    uint32_t GAINCORR:1;       /*!< bit:      7  Gain Correction                    */
+    uint32_t OFFSETCORR:1;     /*!< bit:      8  Offset Correction                  */
+    uint32_t :22;              /*!< bit:  9..30  Reserved                           */
+    uint32_t BUSY:1;           /*!< bit:     31  DMA Sequencing Busy                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_DSEQSTAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DSEQSTAT_OFFSET         0x3C         /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
+#define ADC_DSEQSTAT_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
+
+#define ADC_DSEQSTAT_INPUTCTRL_Pos  0            /**< \brief (ADC_DSEQSTAT) Input Control */
+#define ADC_DSEQSTAT_INPUTCTRL      (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
+#define ADC_DSEQSTAT_CTRLB_Pos      1            /**< \brief (ADC_DSEQSTAT) Control B */
+#define ADC_DSEQSTAT_CTRLB          (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
+#define ADC_DSEQSTAT_REFCTRL_Pos    2            /**< \brief (ADC_DSEQSTAT) Reference Control */
+#define ADC_DSEQSTAT_REFCTRL        (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
+#define ADC_DSEQSTAT_AVGCTRL_Pos    3            /**< \brief (ADC_DSEQSTAT) Average Control */
+#define ADC_DSEQSTAT_AVGCTRL        (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
+#define ADC_DSEQSTAT_SAMPCTRL_Pos   4            /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
+#define ADC_DSEQSTAT_SAMPCTRL       (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
+#define ADC_DSEQSTAT_WINLT_Pos      5            /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
+#define ADC_DSEQSTAT_WINLT          (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
+#define ADC_DSEQSTAT_WINUT_Pos      6            /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
+#define ADC_DSEQSTAT_WINUT          (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
+#define ADC_DSEQSTAT_GAINCORR_Pos   7            /**< \brief (ADC_DSEQSTAT) Gain Correction */
+#define ADC_DSEQSTAT_GAINCORR       (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
+#define ADC_DSEQSTAT_OFFSETCORR_Pos 8            /**< \brief (ADC_DSEQSTAT) Offset Correction */
+#define ADC_DSEQSTAT_OFFSETCORR     (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
+#define ADC_DSEQSTAT_BUSY_Pos       31           /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
+#define ADC_DSEQSTAT_BUSY           (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
+#define ADC_DSEQSTAT_MASK           _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/  16) Result Conversion Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET           0x40         /**< \brief (ADC_RESULT offset) Result Conversion Value */
+#define ADC_RESULT_RESETVALUE       _U_(0x0000)  /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
+
+#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk       (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK             _U_(0xFFFF)  /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_RESS : (ADC Offset: 0x44) (R/  16) Last Sample Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESS:16;          /*!< bit:  0..15  Last ADC conversion result         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESS_OFFSET             0x44         /**< \brief (ADC_RESS offset) Last Sample Result */
+#define ADC_RESS_RESETVALUE         _U_(0x0000)  /**< \brief (ADC_RESS reset_value) Last Sample Result */
+
+#define ADC_RESS_RESS_Pos           0            /**< \brief (ADC_RESS) Last ADC conversion result */
+#define ADC_RESS_RESS_Msk           (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
+#define ADC_RESS_RESS(value)        (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
+#define ADC_RESS_MASK               _U_(0xFFFF)  /**< \brief (ADC_RESS) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BIASCOMP:3;       /*!< bit:  0.. 2  Bias Comparator Scaling            */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t BIASR2R:3;        /*!< bit:  4.. 6  Bias R2R Ampli scaling             */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t BIASREFBUF:3;     /*!< bit:  8..10  Bias  Reference Buffer Scaling     */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET            0x48         /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_BIASCOMP_Pos      0            /**< \brief (ADC_CALIB) Bias Comparator Scaling */
+#define ADC_CALIB_BIASCOMP_Msk      (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
+#define ADC_CALIB_BIASCOMP(value)   (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
+#define ADC_CALIB_BIASR2R_Pos       4            /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
+#define ADC_CALIB_BIASR2R_Msk       (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
+#define ADC_CALIB_BIASR2R(value)    (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
+#define ADC_CALIB_BIASREFBUF_Pos    8            /**< \brief (ADC_CALIB) Bias  Reference Buffer Scaling */
+#define ADC_CALIB_BIASREFBUF_Msk    (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
+#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
+#define ADC_CALIB_MASK              _U_(0x0777)  /**< \brief (ADC_CALIB) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x02 (R/W  8) Event Control */
+  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x03 (R/W  8) Debug Control */
+  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x04 (R/W 16) Input Control */
+  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x06 (R/W 16) Control B */
+  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x08 (R/W  8) Reference Control */
+       RoReg8                    Reserved1[0x1];
+  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x0A (R/W  8) Average Control */
+  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x0B (R/W  8) Sample Time Control */
+  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
+  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
+  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
+  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
+  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x14 (R/W  8) Software Trigger */
+       RoReg8                    Reserved2[0x17];
+  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x2C (R/W  8) Interrupt Enable Clear */
+  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x2D (R/W  8) Interrupt Enable Set */
+  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2E (R/W  8) Interrupt Flag Status and Clear */
+  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x2F (R/   8) Status */
+  __I  ADC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x30 (R/  32) Synchronization Busy */
+  __O  ADC_DSEQDATA_Type         DSEQDATA;    /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
+  __IO ADC_DSEQCTRL_Type         DSEQCTRL;    /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
+  __I  ADC_DSEQSTAT_Type         DSEQSTAT;    /**< \brief Offset: 0x3C (R/  32) DMA Sequencial Status */
+  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x40 (R/  16) Result Conversion Value */
+       RoReg8                    Reserved3[0x2];
+  __I  ADC_RESS_Type             RESS;        /**< \brief Offset: 0x44 (R/  16) Last Sample Result */
+       RoReg8                    Reserved4[0x2];
+  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x48 (R/W 16) Calibration */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_ADC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/aes.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/aes.h
new file mode 100644
index 000000000..9a7e59f93
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/aes.h	
@@ -0,0 +1,375 @@
+/**
+ * \file
+ *
+ * \brief Component description for AES
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_AES_COMPONENT_
+#define _SAME53_AES_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AES */
+/* ========================================================================== */
+/** \addtogroup SAME53_AES Advanced Encryption Standard */
+/*@{*/
+
+#define AES_U2238
+#define REV_AES                     0x220
+
+/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t AESMODE:3;        /*!< bit:  2.. 4  AES Modes of operation             */
+    uint32_t CFBS:3;           /*!< bit:  5.. 7  Cipher Feedback Block Size         */
+    uint32_t KEYSIZE:2;        /*!< bit:  8.. 9  Encryption Key Size                */
+    uint32_t CIPHER:1;         /*!< bit:     10  Cipher Mode                        */
+    uint32_t STARTMODE:1;      /*!< bit:     11  Start Mode Select                  */
+    uint32_t LOD:1;            /*!< bit:     12  Last Output Data Mode              */
+    uint32_t KEYGEN:1;         /*!< bit:     13  Last Key Generation                */
+    uint32_t XORKEY:1;         /*!< bit:     14  XOR Key Operation                  */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t CTYPE:4;          /*!< bit: 16..19  Counter Measure Type               */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLA_OFFSET            0x00         /**< \brief (AES_CTRLA offset) Control A */
+#define AES_CTRLA_RESETVALUE        _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
+
+#define AES_CTRLA_SWRST_Pos         0            /**< \brief (AES_CTRLA) Software Reset */
+#define AES_CTRLA_SWRST             (_U_(0x1) << AES_CTRLA_SWRST_Pos)
+#define AES_CTRLA_ENABLE_Pos        1            /**< \brief (AES_CTRLA) Enable */
+#define AES_CTRLA_ENABLE            (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
+#define AES_CTRLA_AESMODE_Pos       2            /**< \brief (AES_CTRLA) AES Modes of operation */
+#define AES_CTRLA_AESMODE_Msk       (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE(value)    (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
+#define   AES_CTRLA_AESMODE_ECB_Val       _U_(0x0)   /**< \brief (AES_CTRLA) Electronic code book mode */
+#define   AES_CTRLA_AESMODE_CBC_Val       _U_(0x1)   /**< \brief (AES_CTRLA) Cipher block chaining mode */
+#define   AES_CTRLA_AESMODE_OFB_Val       _U_(0x2)   /**< \brief (AES_CTRLA) Output feedback mode */
+#define   AES_CTRLA_AESMODE_CFB_Val       _U_(0x3)   /**< \brief (AES_CTRLA) Cipher feedback mode */
+#define   AES_CTRLA_AESMODE_COUNTER_Val   _U_(0x4)   /**< \brief (AES_CTRLA) Counter mode */
+#define   AES_CTRLA_AESMODE_CCM_Val       _U_(0x5)   /**< \brief (AES_CTRLA) CCM mode */
+#define   AES_CTRLA_AESMODE_GCM_Val       _U_(0x6)   /**< \brief (AES_CTRLA) Galois counter mode */
+#define AES_CTRLA_AESMODE_ECB       (AES_CTRLA_AESMODE_ECB_Val     << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CBC       (AES_CTRLA_AESMODE_CBC_Val     << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_OFB       (AES_CTRLA_AESMODE_OFB_Val     << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CFB       (AES_CTRLA_AESMODE_CFB_Val     << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_COUNTER   (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_CCM       (AES_CTRLA_AESMODE_CCM_Val     << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE_GCM       (AES_CTRLA_AESMODE_GCM_Val     << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_CFBS_Pos          5            /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
+#define AES_CTRLA_CFBS_Msk          (_U_(0x7) << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS(value)       (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
+#define   AES_CTRLA_CFBS_128BIT_Val       _U_(0x0)   /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define   AES_CTRLA_CFBS_64BIT_Val        _U_(0x1)   /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define   AES_CTRLA_CFBS_32BIT_Val        _U_(0x2)   /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define   AES_CTRLA_CFBS_16BIT_Val        _U_(0x3)   /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define   AES_CTRLA_CFBS_8BIT_Val         _U_(0x4)   /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
+#define AES_CTRLA_CFBS_128BIT       (AES_CTRLA_CFBS_128BIT_Val     << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_64BIT        (AES_CTRLA_CFBS_64BIT_Val      << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_32BIT        (AES_CTRLA_CFBS_32BIT_Val      << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_16BIT        (AES_CTRLA_CFBS_16BIT_Val      << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS_8BIT         (AES_CTRLA_CFBS_8BIT_Val       << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_KEYSIZE_Pos       8            /**< \brief (AES_CTRLA) Encryption Key Size */
+#define AES_CTRLA_KEYSIZE_Msk       (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE(value)    (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
+#define   AES_CTRLA_KEYSIZE_128BIT_Val    _U_(0x0)   /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
+#define   AES_CTRLA_KEYSIZE_192BIT_Val    _U_(0x1)   /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
+#define   AES_CTRLA_KEYSIZE_256BIT_Val    _U_(0x2)   /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
+#define AES_CTRLA_KEYSIZE_128BIT    (AES_CTRLA_KEYSIZE_128BIT_Val  << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE_192BIT    (AES_CTRLA_KEYSIZE_192BIT_Val  << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE_256BIT    (AES_CTRLA_KEYSIZE_256BIT_Val  << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_CIPHER_Pos        10           /**< \brief (AES_CTRLA) Cipher Mode */
+#define AES_CTRLA_CIPHER            (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
+#define   AES_CTRLA_CIPHER_DEC_Val        _U_(0x0)   /**< \brief (AES_CTRLA) Decryption */
+#define   AES_CTRLA_CIPHER_ENC_Val        _U_(0x1)   /**< \brief (AES_CTRLA) Encryption */
+#define AES_CTRLA_CIPHER_DEC        (AES_CTRLA_CIPHER_DEC_Val      << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_CIPHER_ENC        (AES_CTRLA_CIPHER_ENC_Val      << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_STARTMODE_Pos     11           /**< \brief (AES_CTRLA) Start Mode Select */
+#define AES_CTRLA_STARTMODE         (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
+#define   AES_CTRLA_STARTMODE_MANUAL_Val  _U_(0x0)   /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
+#define   AES_CTRLA_STARTMODE_AUTO_Val    _U_(0x1)   /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
+#define AES_CTRLA_STARTMODE_MANUAL  (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_STARTMODE_AUTO    (AES_CTRLA_STARTMODE_AUTO_Val  << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_LOD_Pos           12           /**< \brief (AES_CTRLA) Last Output Data Mode */
+#define AES_CTRLA_LOD               (_U_(0x1) << AES_CTRLA_LOD_Pos)
+#define   AES_CTRLA_LOD_NONE_Val          _U_(0x0)   /**< \brief (AES_CTRLA) No effect */
+#define   AES_CTRLA_LOD_LAST_Val          _U_(0x1)   /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
+#define AES_CTRLA_LOD_NONE          (AES_CTRLA_LOD_NONE_Val        << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_LOD_LAST          (AES_CTRLA_LOD_LAST_Val        << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_KEYGEN_Pos        13           /**< \brief (AES_CTRLA) Last Key Generation */
+#define AES_CTRLA_KEYGEN            (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
+#define   AES_CTRLA_KEYGEN_NONE_Val       _U_(0x0)   /**< \brief (AES_CTRLA) No effect */
+#define   AES_CTRLA_KEYGEN_LAST_Val       _U_(0x1)   /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
+#define AES_CTRLA_KEYGEN_NONE       (AES_CTRLA_KEYGEN_NONE_Val     << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_KEYGEN_LAST       (AES_CTRLA_KEYGEN_LAST_Val     << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_XORKEY_Pos        14           /**< \brief (AES_CTRLA) XOR Key Operation */
+#define AES_CTRLA_XORKEY            (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
+#define   AES_CTRLA_XORKEY_NONE_Val       _U_(0x0)   /**< \brief (AES_CTRLA) No effect */
+#define   AES_CTRLA_XORKEY_XOR_Val        _U_(0x1)   /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
+#define AES_CTRLA_XORKEY_NONE       (AES_CTRLA_XORKEY_NONE_Val     << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_XORKEY_XOR        (AES_CTRLA_XORKEY_XOR_Val      << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_CTYPE_Pos         16           /**< \brief (AES_CTRLA) Counter Measure Type */
+#define AES_CTRLA_CTYPE_Msk         (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
+#define AES_CTRLA_CTYPE(value)      (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
+#define AES_CTRLA_MASK              _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
+
+/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START:1;          /*!< bit:      0  Start Encryption/Decryption        */
+    uint8_t  NEWMSG:1;         /*!< bit:      1  New message                        */
+    uint8_t  EOM:1;            /*!< bit:      2  End of message                     */
+    uint8_t  GFMUL:1;          /*!< bit:      3  GF Multiplication                  */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLB_OFFSET            0x04         /**< \brief (AES_CTRLB offset) Control B */
+#define AES_CTRLB_RESETVALUE        _U_(0x00)    /**< \brief (AES_CTRLB reset_value) Control B */
+
+#define AES_CTRLB_START_Pos         0            /**< \brief (AES_CTRLB) Start Encryption/Decryption */
+#define AES_CTRLB_START             (_U_(0x1) << AES_CTRLB_START_Pos)
+#define AES_CTRLB_NEWMSG_Pos        1            /**< \brief (AES_CTRLB) New message */
+#define AES_CTRLB_NEWMSG            (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
+#define AES_CTRLB_EOM_Pos           2            /**< \brief (AES_CTRLB) End of message */
+#define AES_CTRLB_EOM               (_U_(0x1) << AES_CTRLB_EOM_Pos)
+#define AES_CTRLB_GFMUL_Pos         3            /**< \brief (AES_CTRLB) GF Multiplication */
+#define AES_CTRLB_GFMUL             (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
+#define AES_CTRLB_MASK              _U_(0x0F)    /**< \brief (AES_CTRLB) MASK Register */
+
+/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete Interrupt Enable */
+    uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENCLR_OFFSET         0x05         /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
+#define AES_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AES_INTENCLR_ENCCMP_Pos     0            /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
+#define AES_INTENCLR_ENCCMP         (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
+#define AES_INTENCLR_GFMCMP_Pos     1            /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
+#define AES_INTENCLR_GFMCMP         (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
+#define AES_INTENCLR_MASK           _U_(0x03)    /**< \brief (AES_INTENCLR) MASK Register */
+
+/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete Interrupt Enable */
+    uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENSET_OFFSET         0x06         /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
+#define AES_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
+
+#define AES_INTENSET_ENCCMP_Pos     0            /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
+#define AES_INTENSET_ENCCMP         (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
+#define AES_INTENSET_GFMCMP_Pos     1            /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
+#define AES_INTENSET_GFMCMP         (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
+#define AES_INTENSET_MASK           _U_(0x03)    /**< \brief (AES_INTENSET) MASK Register */
+
+/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W  8) Interrupt Flag Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete                */
+    __I uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete         */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTFLAG_OFFSET          0x07         /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
+#define AES_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
+
+#define AES_INTFLAG_ENCCMP_Pos      0            /**< \brief (AES_INTFLAG) Encryption Complete */
+#define AES_INTFLAG_ENCCMP          (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
+#define AES_INTFLAG_GFMCMP_Pos      1            /**< \brief (AES_INTFLAG) GF Multiplication Complete */
+#define AES_INTFLAG_GFMCMP          (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
+#define AES_INTFLAG_MASK            _U_(0x03)    /**< \brief (AES_INTFLAG) MASK Register */
+
+/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W  8) Data buffer pointer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INDATAPTR:2;      /*!< bit:  0.. 1  Input Data Pointer                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_DATABUFPTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DATABUFPTR_OFFSET       0x08         /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
+#define AES_DATABUFPTR_RESETVALUE   _U_(0x00)    /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
+
+#define AES_DATABUFPTR_INDATAPTR_Pos 0            /**< \brief (AES_DATABUFPTR) Input Data Pointer */
+#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
+#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
+#define AES_DATABUFPTR_MASK         _U_(0x03)    /**< \brief (AES_DATABUFPTR) MASK Register */
+
+/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W  8) Debug control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DBGCTRL_OFFSET          0x09         /**< \brief (AES_DBGCTRL offset) Debug control */
+#define AES_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (AES_DBGCTRL reset_value) Debug control */
+
+#define AES_DBGCTRL_DBGRUN_Pos      0            /**< \brief (AES_DBGCTRL) Debug Run */
+#define AES_DBGCTRL_DBGRUN          (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
+#define AES_DBGCTRL_MASK            _U_(0x01)    /**< \brief (AES_DBGCTRL) MASK Register */
+
+/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_KEYWORD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_KEYWORD_OFFSET          0x0C         /**< \brief (AES_KEYWORD offset) Keyword n */
+#define AES_KEYWORD_RESETVALUE      _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
+#define AES_KEYWORD_MASK            _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
+
+/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_INDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INDATA_OFFSET           0x38         /**< \brief (AES_INDATA offset) Indata */
+#define AES_INDATA_RESETVALUE       _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
+#define AES_INDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
+
+/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_INTVECTV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTVECTV_OFFSET         0x3C         /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
+#define AES_INTVECTV_RESETVALUE     _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
+#define AES_INTVECTV_MASK           _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
+
+/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_HASHKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_HASHKEY_OFFSET          0x5C         /**< \brief (AES_HASHKEY offset) Hash key n */
+#define AES_HASHKEY_RESETVALUE      _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
+#define AES_HASHKEY_MASK            _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
+
+/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_GHASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_GHASH_OFFSET            0x6C         /**< \brief (AES_GHASH offset) Galois Hash n */
+#define AES_GHASH_RESETVALUE        _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
+#define AES_GHASH_MASK              _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
+
+/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_CIPLEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CIPLEN_OFFSET           0x80         /**< \brief (AES_CIPLEN offset) Cipher Length */
+#define AES_CIPLEN_RESETVALUE       _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
+#define AES_CIPLEN_MASK             _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
+
+/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_RANDSEED_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_RANDSEED_OFFSET         0x84         /**< \brief (AES_RANDSEED offset) Random Seed */
+#define AES_RANDSEED_RESETVALUE     _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
+#define AES_RANDSEED_MASK           _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
+
+/** \brief AES hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AES_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO AES_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W  8) Control B */
+  __IO AES_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Clear */
+  __IO AES_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x06 (R/W  8) Interrupt Enable Set */
+  __IO AES_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x07 (R/W  8) Interrupt Flag Status */
+  __IO AES_DATABUFPTR_Type       DATABUFPTR;  /**< \brief Offset: 0x08 (R/W  8) Data buffer pointer */
+  __IO AES_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x09 (R/W  8) Debug control */
+       RoReg8                    Reserved1[0x2];
+  __O  AES_KEYWORD_Type          KEYWORD[8];  /**< \brief Offset: 0x0C ( /W 32) Keyword n */
+       RoReg8                    Reserved2[0xC];
+  __IO AES_INDATA_Type           INDATA;      /**< \brief Offset: 0x38 (R/W 32) Indata */
+  __O  AES_INTVECTV_Type         INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
+       RoReg8                    Reserved3[0x10];
+  __IO AES_HASHKEY_Type          HASHKEY[4];  /**< \brief Offset: 0x5C (R/W 32) Hash key n */
+  __IO AES_GHASH_Type            GHASH[4];    /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
+       RoReg8                    Reserved4[0x4];
+  __IO AES_CIPLEN_Type           CIPLEN;      /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
+  __IO AES_RANDSEED_Type         RANDSEED;    /**< \brief Offset: 0x84 (R/W 32) Random Seed */
+} Aes;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_AES_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ccl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ccl.h
new file mode 100644
index 000000000..c81318d1a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ccl.h	
@@ -0,0 +1,228 @@
+/**
+ * \file
+ *
+ * \brief Component description for CCL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_CCL_COMPONENT_
+#define _SAME53_CCL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR CCL */
+/* ========================================================================== */
+/** \addtogroup SAME53_CCL Configurable Custom Logic */
+/*@{*/
+
+#define CCL_U2225
+#define REV_CCL                     0x110
+
+/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} CCL_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_CTRL_OFFSET             0x0          /**< \brief (CCL_CTRL offset) Control */
+#define CCL_CTRL_RESETVALUE         _U_(0x00)    /**< \brief (CCL_CTRL reset_value) Control */
+
+#define CCL_CTRL_SWRST_Pos          0            /**< \brief (CCL_CTRL) Software Reset */
+#define CCL_CTRL_SWRST              (_U_(0x1) << CCL_CTRL_SWRST_Pos)
+#define CCL_CTRL_ENABLE_Pos         1            /**< \brief (CCL_CTRL) Enable */
+#define CCL_CTRL_ENABLE             (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
+#define CCL_CTRL_RUNSTDBY_Pos       6            /**< \brief (CCL_CTRL) Run in Standby */
+#define CCL_CTRL_RUNSTDBY           (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
+#define CCL_CTRL_MASK               _U_(0x43)    /**< \brief (CCL_CTRL) MASK Register */
+
+/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W  8) SEQ Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEQSEL:4;         /*!< bit:  0.. 3  Sequential Selection               */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} CCL_SEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_SEQCTRL_OFFSET          0x4          /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
+#define CCL_SEQCTRL_RESETVALUE      _U_(0x00)    /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
+
+#define CCL_SEQCTRL_SEQSEL_Pos      0            /**< \brief (CCL_SEQCTRL) Sequential Selection */
+#define CCL_SEQCTRL_SEQSEL_Msk      (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL(value)   (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
+#define   CCL_SEQCTRL_SEQSEL_DISABLE_Val  _U_(0x0)   /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
+#define   CCL_SEQCTRL_SEQSEL_DFF_Val      _U_(0x1)   /**< \brief (CCL_SEQCTRL) D flip flop */
+#define   CCL_SEQCTRL_SEQSEL_JK_Val       _U_(0x2)   /**< \brief (CCL_SEQCTRL) JK flip flop */
+#define   CCL_SEQCTRL_SEQSEL_LATCH_Val    _U_(0x3)   /**< \brief (CCL_SEQCTRL) D latch */
+#define   CCL_SEQCTRL_SEQSEL_RS_Val       _U_(0x4)   /**< \brief (CCL_SEQCTRL) RS latch */
+#define CCL_SEQCTRL_SEQSEL_DISABLE  (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_DFF      (CCL_SEQCTRL_SEQSEL_DFF_Val    << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_JK       (CCL_SEQCTRL_SEQSEL_JK_Val     << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_LATCH    (CCL_SEQCTRL_SEQSEL_LATCH_Val  << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_RS       (CCL_SEQCTRL_SEQSEL_RS_Val     << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_MASK            _U_(0x0F)    /**< \brief (CCL_SEQCTRL) MASK Register */
+
+/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  LUT Enable                         */
+    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint32_t FILTSEL:2;        /*!< bit:  4.. 5  Filter Selection                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t EDGESEL:1;        /*!< bit:      7  Edge Selection                     */
+    uint32_t INSEL0:4;         /*!< bit:  8..11  Input Selection 0                  */
+    uint32_t INSEL1:4;         /*!< bit: 12..15  Input Selection 1                  */
+    uint32_t INSEL2:4;         /*!< bit: 16..19  Input Selection 2                  */
+    uint32_t INVEI:1;          /*!< bit:     20  Inverted Event Input Enable        */
+    uint32_t LUTEI:1;          /*!< bit:     21  LUT Event Input Enable             */
+    uint32_t LUTEO:1;          /*!< bit:     22  LUT Event Output Enable            */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t TRUTH:8;          /*!< bit: 24..31  Truth Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CCL_LUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_LUTCTRL_OFFSET          0x8          /**< \brief (CCL_LUTCTRL offset) LUT Control x */
+#define CCL_LUTCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
+
+#define CCL_LUTCTRL_ENABLE_Pos      1            /**< \brief (CCL_LUTCTRL) LUT Enable */
+#define CCL_LUTCTRL_ENABLE          (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
+#define CCL_LUTCTRL_FILTSEL_Pos     4            /**< \brief (CCL_LUTCTRL) Filter Selection */
+#define CCL_LUTCTRL_FILTSEL_Msk     (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL(value)  (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
+#define   CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0)   /**< \brief (CCL_LUTCTRL) Filter disabled */
+#define   CCL_LUTCTRL_FILTSEL_SYNCH_Val   _U_(0x1)   /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
+#define   CCL_LUTCTRL_FILTSEL_FILTER_Val  _U_(0x2)   /**< \brief (CCL_LUTCTRL) Filter enabled */
+#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_SYNCH   (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_FILTER  (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_EDGESEL_Pos     7            /**< \brief (CCL_LUTCTRL) Edge Selection */
+#define CCL_LUTCTRL_EDGESEL         (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
+#define CCL_LUTCTRL_INSEL0_Pos      8            /**< \brief (CCL_LUTCTRL) Input Selection 0 */
+#define CCL_LUTCTRL_INSEL0_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0(value)   (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
+#define   CCL_LUTCTRL_INSEL0_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
+#define   CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define   CCL_LUTCTRL_INSEL0_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define   CCL_LUTCTRL_INSEL0_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event input source */
+#define   CCL_LUTCTRL_INSEL0_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define   CCL_LUTCTRL_INSEL0_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
+#define   CCL_LUTCTRL_INSEL0_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
+#define   CCL_LUTCTRL_INSEL0_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define   CCL_LUTCTRL_INSEL0_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
+#define   CCL_LUTCTRL_INSEL0_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL0_MASK     (CCL_LUTCTRL_INSEL0_MASK_Val   << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_LINK     (CCL_LUTCTRL_INSEL0_LINK_Val   << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_EVENT    (CCL_LUTCTRL_INSEL0_EVENT_Val  << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_IO       (CCL_LUTCTRL_INSEL0_IO_Val     << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_AC       (CCL_LUTCTRL_INSEL0_AC_Val     << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TC       (CCL_LUTCTRL_INSEL0_TC_Val     << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_ALTTC    (CCL_LUTCTRL_INSEL0_ALTTC_Val  << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TCC      (CCL_LUTCTRL_INSEL0_TCC_Val    << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_SERCOM   (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL1_Pos      12           /**< \brief (CCL_LUTCTRL) Input Selection 1 */
+#define CCL_LUTCTRL_INSEL1_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1(value)   (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
+#define   CCL_LUTCTRL_INSEL1_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
+#define   CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define   CCL_LUTCTRL_INSEL1_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define   CCL_LUTCTRL_INSEL1_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event input source */
+#define   CCL_LUTCTRL_INSEL1_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define   CCL_LUTCTRL_INSEL1_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
+#define   CCL_LUTCTRL_INSEL1_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
+#define   CCL_LUTCTRL_INSEL1_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define   CCL_LUTCTRL_INSEL1_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
+#define   CCL_LUTCTRL_INSEL1_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL1_MASK     (CCL_LUTCTRL_INSEL1_MASK_Val   << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_LINK     (CCL_LUTCTRL_INSEL1_LINK_Val   << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_EVENT    (CCL_LUTCTRL_INSEL1_EVENT_Val  << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_IO       (CCL_LUTCTRL_INSEL1_IO_Val     << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_AC       (CCL_LUTCTRL_INSEL1_AC_Val     << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_TC       (CCL_LUTCTRL_INSEL1_TC_Val     << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_ALTTC    (CCL_LUTCTRL_INSEL1_ALTTC_Val  << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_TCC      (CCL_LUTCTRL_INSEL1_TCC_Val    << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1_SERCOM   (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL2_Pos      16           /**< \brief (CCL_LUTCTRL) Input Selection 2 */
+#define CCL_LUTCTRL_INSEL2_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2(value)   (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
+#define   CCL_LUTCTRL_INSEL2_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
+#define   CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define   CCL_LUTCTRL_INSEL2_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define   CCL_LUTCTRL_INSEL2_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event input source */
+#define   CCL_LUTCTRL_INSEL2_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define   CCL_LUTCTRL_INSEL2_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
+#define   CCL_LUTCTRL_INSEL2_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
+#define   CCL_LUTCTRL_INSEL2_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define   CCL_LUTCTRL_INSEL2_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
+#define   CCL_LUTCTRL_INSEL2_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM input source */
+#define CCL_LUTCTRL_INSEL2_MASK     (CCL_LUTCTRL_INSEL2_MASK_Val   << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_LINK     (CCL_LUTCTRL_INSEL2_LINK_Val   << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_EVENT    (CCL_LUTCTRL_INSEL2_EVENT_Val  << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_IO       (CCL_LUTCTRL_INSEL2_IO_Val     << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_AC       (CCL_LUTCTRL_INSEL2_AC_Val     << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_TC       (CCL_LUTCTRL_INSEL2_TC_Val     << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_ALTTC    (CCL_LUTCTRL_INSEL2_ALTTC_Val  << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_TCC      (CCL_LUTCTRL_INSEL2_TCC_Val    << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2_SERCOM   (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INVEI_Pos       20           /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
+#define CCL_LUTCTRL_INVEI           (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
+#define CCL_LUTCTRL_LUTEI_Pos       21           /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
+#define CCL_LUTCTRL_LUTEI           (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
+#define CCL_LUTCTRL_LUTEO_Pos       22           /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
+#define CCL_LUTCTRL_LUTEO           (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
+#define CCL_LUTCTRL_TRUTH_Pos       24           /**< \brief (CCL_LUTCTRL) Truth Value */
+#define CCL_LUTCTRL_TRUTH_Msk       (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
+#define CCL_LUTCTRL_TRUTH(value)    (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
+#define CCL_LUTCTRL_MASK            _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
+
+/** \brief CCL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO CCL_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO CCL_SEQCTRL_Type          SEQCTRL[2];  /**< \brief Offset: 0x4 (R/W  8) SEQ Control x */
+       RoReg8                    Reserved2[0x2];
+  __IO CCL_LUTCTRL_Type          LUTCTRL[4];  /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
+} Ccl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_CCL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/cmcc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/cmcc.h
new file mode 100644
index 000000000..c0714ed0c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/cmcc.h	
@@ -0,0 +1,357 @@
+/**
+ * \file
+ *
+ * \brief Component description for CMCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_CMCC_COMPONENT_
+#define _SAME53_CMCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR CMCC */
+/* ========================================================================== */
+/** \addtogroup SAME53_CMCC Cortex M Cache Controller */
+/*@{*/
+
+#define CMCC_U2015
+#define REV_CMCC                    0x600
+
+/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/  32) Cache Type Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t GCLK:1;           /*!< bit:      1  dynamic Clock Gating supported     */
+    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint32_t RRP:1;            /*!< bit:      4  Round Robin Policy supported       */
+    uint32_t WAYNUM:2;         /*!< bit:  5.. 6  Number of Way                      */
+    uint32_t LCKDOWN:1;        /*!< bit:      7  Lock Down supported                */
+    uint32_t CSIZE:3;          /*!< bit:  8..10  Cache Size                         */
+    uint32_t CLSIZE:3;         /*!< bit: 11..13  Cache Line Size                    */
+    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_TYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_TYPE_OFFSET            0x00         /**< \brief (CMCC_TYPE offset) Cache Type Register */
+#define CMCC_TYPE_RESETVALUE        _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
+
+#define CMCC_TYPE_GCLK_Pos          1            /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
+#define CMCC_TYPE_GCLK              (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
+#define CMCC_TYPE_RRP_Pos           4            /**< \brief (CMCC_TYPE) Round Robin Policy supported */
+#define CMCC_TYPE_RRP               (_U_(0x1) << CMCC_TYPE_RRP_Pos)
+#define CMCC_TYPE_WAYNUM_Pos        5            /**< \brief (CMCC_TYPE) Number of Way */
+#define CMCC_TYPE_WAYNUM_Msk        (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM(value)     (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
+#define   CMCC_TYPE_WAYNUM_DMAPPED_Val    _U_(0x0)   /**< \brief (CMCC_TYPE) Direct Mapped Cache */
+#define   CMCC_TYPE_WAYNUM_ARCH2WAY_Val   _U_(0x1)   /**< \brief (CMCC_TYPE) 2-WAY set associative */
+#define   CMCC_TYPE_WAYNUM_ARCH4WAY_Val   _U_(0x2)   /**< \brief (CMCC_TYPE) 4-WAY set associative */
+#define CMCC_TYPE_WAYNUM_DMAPPED    (CMCC_TYPE_WAYNUM_DMAPPED_Val  << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM_ARCH2WAY   (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_WAYNUM_ARCH4WAY   (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
+#define CMCC_TYPE_LCKDOWN_Pos       7            /**< \brief (CMCC_TYPE) Lock Down supported */
+#define CMCC_TYPE_LCKDOWN           (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
+#define CMCC_TYPE_CSIZE_Pos         8            /**< \brief (CMCC_TYPE) Cache Size */
+#define CMCC_TYPE_CSIZE_Msk         (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE(value)      (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
+#define   CMCC_TYPE_CSIZE_CSIZE_1KB_Val   _U_(0x0)   /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
+#define   CMCC_TYPE_CSIZE_CSIZE_2KB_Val   _U_(0x1)   /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
+#define   CMCC_TYPE_CSIZE_CSIZE_4KB_Val   _U_(0x2)   /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
+#define   CMCC_TYPE_CSIZE_CSIZE_8KB_Val   _U_(0x3)   /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
+#define   CMCC_TYPE_CSIZE_CSIZE_16KB_Val  _U_(0x4)   /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
+#define   CMCC_TYPE_CSIZE_CSIZE_32KB_Val  _U_(0x5)   /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
+#define   CMCC_TYPE_CSIZE_CSIZE_64KB_Val  _U_(0x6)   /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
+#define CMCC_TYPE_CSIZE_CSIZE_1KB   (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_2KB   (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_4KB   (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_8KB   (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_16KB  (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_32KB  (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CSIZE_CSIZE_64KB  (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_Pos        11           /**< \brief (CMCC_TYPE) Cache Line Size */
+#define CMCC_TYPE_CLSIZE_Msk        (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE(value)     (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
+#define   CMCC_TYPE_CLSIZE_CLSIZE_4B_Val  _U_(0x0)   /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
+#define   CMCC_TYPE_CLSIZE_CLSIZE_8B_Val  _U_(0x1)   /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
+#define   CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2)   /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
+#define   CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3)   /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
+#define   CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4)   /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
+#define   CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5)   /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_4B  (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_8B  (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
+#define CMCC_TYPE_MASK              _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
+
+/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ICDIS:1;          /*!< bit:      1  Instruction Cache Disable          */
+    uint32_t DCDIS:1;          /*!< bit:      2  Data Cache Disable                 */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t CSIZESW:3;        /*!< bit:  4.. 6  Cache size configured by software  */
+    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_CFG_OFFSET             0x04         /**< \brief (CMCC_CFG offset) Cache Configuration Register */
+#define CMCC_CFG_RESETVALUE         _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
+
+#define CMCC_CFG_ICDIS_Pos          1            /**< \brief (CMCC_CFG) Instruction Cache Disable */
+#define CMCC_CFG_ICDIS              (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
+#define CMCC_CFG_DCDIS_Pos          2            /**< \brief (CMCC_CFG) Data Cache Disable */
+#define CMCC_CFG_DCDIS              (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
+#define CMCC_CFG_CSIZESW_Pos        4            /**< \brief (CMCC_CFG) Cache size configured by software */
+#define CMCC_CFG_CSIZESW_Msk        (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW(value)     (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0)   /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1)   /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2)   /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3)   /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4)   /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5)   /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
+#define   CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6)   /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
+#define CMCC_CFG_MASK               _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
+
+/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CEN:1;            /*!< bit:      0  Cache Controller Enable            */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_CTRL_OFFSET            0x08         /**< \brief (CMCC_CTRL offset) Cache Control Register */
+#define CMCC_CTRL_RESETVALUE        _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
+
+#define CMCC_CTRL_CEN_Pos           0            /**< \brief (CMCC_CTRL) Cache Controller Enable */
+#define CMCC_CTRL_CEN               (_U_(0x1) << CMCC_CTRL_CEN_Pos)
+#define CMCC_CTRL_MASK              _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
+
+/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/  32) Cache Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CSTS:1;           /*!< bit:      0  Cache Controller Status            */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_SR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_SR_OFFSET              0x0C         /**< \brief (CMCC_SR offset) Cache Status Register */
+#define CMCC_SR_RESETVALUE          _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
+
+#define CMCC_SR_CSTS_Pos            0            /**< \brief (CMCC_SR) Cache Controller Status */
+#define CMCC_SR_CSTS                (_U_(0x1) << CMCC_SR_CSTS_Pos)
+#define CMCC_SR_MASK                _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
+
+/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LCKWAY:4;         /*!< bit:  0.. 3  Lockdown way Register              */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_LCKWAY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_LCKWAY_OFFSET          0x10         /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
+#define CMCC_LCKWAY_RESETVALUE      _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
+
+#define CMCC_LCKWAY_LCKWAY_Pos      0            /**< \brief (CMCC_LCKWAY) Lockdown way Register */
+#define CMCC_LCKWAY_LCKWAY_Msk      (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
+#define CMCC_LCKWAY_LCKWAY(value)   (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
+#define CMCC_LCKWAY_MASK            _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
+
+/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t INVALL:1;         /*!< bit:      0  Cache Controller invalidate All    */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_MAINT0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MAINT0_OFFSET          0x20         /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
+#define CMCC_MAINT0_RESETVALUE      _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
+
+#define CMCC_MAINT0_INVALL_Pos      0            /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
+#define CMCC_MAINT0_INVALL          (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
+#define CMCC_MAINT0_MASK            _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
+
+/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t INDEX:8;          /*!< bit:  4..11  Invalidate Index                   */
+    uint32_t :16;              /*!< bit: 12..27  Reserved                           */
+    uint32_t WAY:4;            /*!< bit: 28..31  Invalidate Way                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_MAINT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MAINT1_OFFSET          0x24         /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
+#define CMCC_MAINT1_RESETVALUE      _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
+
+#define CMCC_MAINT1_INDEX_Pos       4            /**< \brief (CMCC_MAINT1) Invalidate Index */
+#define CMCC_MAINT1_INDEX_Msk       (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
+#define CMCC_MAINT1_INDEX(value)    (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
+#define CMCC_MAINT1_WAY_Pos         28           /**< \brief (CMCC_MAINT1) Invalidate Way */
+#define CMCC_MAINT1_WAY_Msk         (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY(value)      (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
+#define   CMCC_MAINT1_WAY_WAY0_Val        _U_(0x0)   /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
+#define   CMCC_MAINT1_WAY_WAY1_Val        _U_(0x1)   /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
+#define   CMCC_MAINT1_WAY_WAY2_Val        _U_(0x2)   /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
+#define   CMCC_MAINT1_WAY_WAY3_Val        _U_(0x3)   /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY0        (CMCC_MAINT1_WAY_WAY0_Val      << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY1        (CMCC_MAINT1_WAY_WAY1_Val      << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY2        (CMCC_MAINT1_WAY_WAY2_Val      << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_WAY_WAY3        (CMCC_MAINT1_WAY_WAY3_Val      << CMCC_MAINT1_WAY_Pos)
+#define CMCC_MAINT1_MASK            _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
+
+/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MODE:2;           /*!< bit:  0.. 1  Cache Controller Monitor Counter Mode */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_MCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MCFG_OFFSET            0x28         /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
+#define CMCC_MCFG_RESETVALUE        _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
+
+#define CMCC_MCFG_MODE_Pos          0            /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
+#define CMCC_MCFG_MODE_Msk          (_U_(0x3) << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE(value)       (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
+#define   CMCC_MCFG_MODE_CYCLE_COUNT_Val  _U_(0x0)   /**< \brief (CMCC_MCFG) cycle counter */
+#define   CMCC_MCFG_MODE_IHIT_COUNT_Val   _U_(0x1)   /**< \brief (CMCC_MCFG) instruction hit counter */
+#define   CMCC_MCFG_MODE_DHIT_COUNT_Val   _U_(0x2)   /**< \brief (CMCC_MCFG) data hit counter */
+#define CMCC_MCFG_MODE_CYCLE_COUNT  (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE_IHIT_COUNT   (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MODE_DHIT_COUNT   (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
+#define CMCC_MCFG_MASK              _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
+
+/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MENABLE:1;        /*!< bit:      0  Cache Controller Monitor Enable    */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_MEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MEN_OFFSET             0x2C         /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
+#define CMCC_MEN_RESETVALUE         _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
+
+#define CMCC_MEN_MENABLE_Pos        0            /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
+#define CMCC_MEN_MENABLE            (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
+#define CMCC_MEN_MASK               _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
+
+/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Cache Controller Software Reset    */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_MCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MCTRL_OFFSET           0x30         /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
+#define CMCC_MCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
+
+#define CMCC_MCTRL_SWRST_Pos        0            /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
+#define CMCC_MCTRL_SWRST            (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
+#define CMCC_MCTRL_MASK             _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
+
+/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/  32) Cache Monitor Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVENT_CNT:32;     /*!< bit:  0..31  Monitor Event Counter              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CMCC_MSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CMCC_MSR_OFFSET             0x34         /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
+#define CMCC_MSR_RESETVALUE         _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
+
+#define CMCC_MSR_EVENT_CNT_Pos      0            /**< \brief (CMCC_MSR) Monitor Event Counter */
+#define CMCC_MSR_EVENT_CNT_Msk      (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
+#define CMCC_MSR_EVENT_CNT(value)   (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
+#define CMCC_MSR_MASK               _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
+
+/** \brief CMCC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __I  CMCC_TYPE_Type            TYPE;        /**< \brief Offset: 0x00 (R/  32) Cache Type Register */
+  __IO CMCC_CFG_Type             CFG;         /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
+  __O  CMCC_CTRL_Type            CTRL;        /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
+  __I  CMCC_SR_Type              SR;          /**< \brief Offset: 0x0C (R/  32) Cache Status Register */
+  __IO CMCC_LCKWAY_Type          LCKWAY;      /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
+       RoReg8                    Reserved1[0xC];
+  __O  CMCC_MAINT0_Type          MAINT0;      /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
+  __O  CMCC_MAINT1_Type          MAINT1;      /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
+  __IO CMCC_MCFG_Type            MCFG;        /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
+  __IO CMCC_MEN_Type             MEN;         /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
+  __O  CMCC_MCTRL_Type           MCTRL;       /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
+  __I  CMCC_MSR_Type             MSR;         /**< \brief Offset: 0x34 (R/  32) Cache Monitor Status Register */
+} Cmcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_CMCC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dac.h
new file mode 100644
index 000000000..a969a4ea7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dac.h	
@@ -0,0 +1,544 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_DAC_COMPONENT_
+#define _SAME53_DAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAME53_DAC Digital-to-Analog Converter */
+/*@{*/
+
+#define DAC_U2502
+#define REV_DAC                     0x100
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable DAC Controller              */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET            0x00         /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST             (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable DAC Controller */
+#define DAC_CTRLA_ENABLE            (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_MASK              _U_(0x03)    /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIFF:1;           /*!< bit:      0  Differential mode enable           */
+    uint8_t  REFSEL:2;         /*!< bit:  1.. 2  Reference Selection for DAC0/1     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET            0x01         /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE        _U_(0x02)    /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_DIFF_Pos          0            /**< \brief (DAC_CTRLB) Differential mode enable */
+#define DAC_CTRLB_DIFF              (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
+#define DAC_CTRLB_REFSEL_Pos        1            /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
+#define DAC_CTRLB_REFSEL_Msk        (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define   DAC_CTRLB_REFSEL_VREFPU_Val     _U_(0x0)   /**< \brief (DAC_CTRLB) External reference unbuffered */
+#define   DAC_CTRLB_REFSEL_VDDANA_Val     _U_(0x1)   /**< \brief (DAC_CTRLB) Analog supply */
+#define   DAC_CTRLB_REFSEL_VREFPB_Val     _U_(0x2)   /**< \brief (DAC_CTRLB) External reference buffered */
+#define   DAC_CTRLB_REFSEL_INTREF_Val     _U_(0x3)   /**< \brief (DAC_CTRLB) Internal bandgap reference */
+#define DAC_CTRLB_REFSEL_VREFPU     (DAC_CTRLB_REFSEL_VREFPU_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VDDANA     (DAC_CTRLB_REFSEL_VDDANA_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFPB     (DAC_CTRLB_REFSEL_VREFPB_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_INTREF     (DAC_CTRLB_REFSEL_INTREF_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK              _U_(0x07)    /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI0:1;       /*!< bit:      0  Start Conversion Event Input DAC 0 */
+    uint8_t  STARTEI1:1;       /*!< bit:      1  Start Conversion Event Input DAC 1 */
+    uint8_t  EMPTYEO0:1;       /*!< bit:      2  Data Buffer Empty Event Output DAC 0 */
+    uint8_t  EMPTYEO1:1;       /*!< bit:      3  Data Buffer Empty Event Output DAC 1 */
+    uint8_t  INVEI0:1;         /*!< bit:      4  Enable Invertion of DAC 0 input event */
+    uint8_t  INVEI1:1;         /*!< bit:      5  Enable Invertion of DAC 1 input event */
+    uint8_t  RESRDYEO0:1;      /*!< bit:      6  Result Ready Event Output 0        */
+    uint8_t  RESRDYEO1:1;      /*!< bit:      7  Result Ready Event Output 1        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STARTEI:2;        /*!< bit:  0.. 1  Start Conversion Event Input DAC x */
+    uint8_t  EMPTYEO:2;        /*!< bit:  2.. 3  Data Buffer Empty Event Output DAC x */
+    uint8_t  INVEI:2;          /*!< bit:  4.. 5  Enable Invertion of DAC x input event */
+    uint8_t  RESRDYEO:2;       /*!< bit:  6.. 7  Result Ready Event Output x        */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET           0x02         /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI0_Pos     0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
+#define DAC_EVCTRL_STARTEI0         (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
+#define DAC_EVCTRL_STARTEI1_Pos     1            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
+#define DAC_EVCTRL_STARTEI1         (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
+#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
+#define DAC_EVCTRL_STARTEI_Msk      (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_STARTEI(value)   (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
+#define DAC_EVCTRL_EMPTYEO0_Pos     2            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
+#define DAC_EVCTRL_EMPTYEO0         (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
+#define DAC_EVCTRL_EMPTYEO1_Pos     3            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
+#define DAC_EVCTRL_EMPTYEO1         (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos      2            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
+#define DAC_EVCTRL_EMPTYEO_Msk      (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_EMPTYEO(value)   (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
+#define DAC_EVCTRL_INVEI0_Pos       4            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
+#define DAC_EVCTRL_INVEI0           (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
+#define DAC_EVCTRL_INVEI1_Pos       5            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
+#define DAC_EVCTRL_INVEI1           (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
+#define DAC_EVCTRL_INVEI_Pos        4            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
+#define DAC_EVCTRL_INVEI_Msk        (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
+#define DAC_EVCTRL_INVEI(value)     (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
+#define DAC_EVCTRL_RESRDYEO0_Pos    6            /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
+#define DAC_EVCTRL_RESRDYEO0        (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
+#define DAC_EVCTRL_RESRDYEO1_Pos    7            /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
+#define DAC_EVCTRL_RESRDYEO1        (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
+#define DAC_EVCTRL_RESRDYEO_Pos     6            /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
+#define DAC_EVCTRL_RESRDYEO_Msk     (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
+#define DAC_EVCTRL_RESRDYEO(value)  (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
+#define DAC_EVCTRL_MASK             _U_(0xFF)    /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN0:1;      /*!< bit:      0  Underrun 0 Interrupt Enable        */
+    uint8_t  UNDERRUN1:1;      /*!< bit:      1  Underrun 1 Interrupt Enable        */
+    uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty Interrupt Enable */
+    uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty Interrupt Enable */
+    uint8_t  RESRDY0:1;        /*!< bit:      4  Result 0 Ready Interrupt Enable    */
+    uint8_t  RESRDY1:1;        /*!< bit:      5  Result 1 Ready Interrupt Enable    */
+    uint8_t  OVERRUN0:1;       /*!< bit:      6  Overrun 0 Interrupt Enable         */
+    uint8_t  OVERRUN1:1;       /*!< bit:      7  Overrun 1 Interrupt Enable         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Underrun x Interrupt Enable        */
+    uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty Interrupt Enable */
+    uint8_t  RESRDY:2;         /*!< bit:  4.. 5  Result x Ready Interrupt Enable    */
+    uint8_t  OVERRUN:2;        /*!< bit:  6.. 7  Overrun x Interrupt Enable         */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET         0x04         /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN0_Pos  0            /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN0      (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
+#define DAC_INTENCLR_UNDERRUN1_Pos  1            /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN1      (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
+#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN_Msk   (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
+#define DAC_INTENCLR_EMPTY0_Pos     2            /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY0         (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
+#define DAC_INTENCLR_EMPTY1_Pos     3            /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY1         (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
+#define DAC_INTENCLR_EMPTY_Pos      2            /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY_Msk      (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_EMPTY(value)   (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
+#define DAC_INTENCLR_RESRDY0_Pos    4            /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY0        (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
+#define DAC_INTENCLR_RESRDY1_Pos    5            /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY1        (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
+#define DAC_INTENCLR_RESRDY_Pos     4            /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
+#define DAC_INTENCLR_RESRDY_Msk     (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
+#define DAC_INTENCLR_RESRDY(value)  (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
+#define DAC_INTENCLR_OVERRUN0_Pos   6            /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN0       (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
+#define DAC_INTENCLR_OVERRUN1_Pos   7            /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN1       (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
+#define DAC_INTENCLR_OVERRUN_Pos    6            /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
+#define DAC_INTENCLR_OVERRUN_Msk    (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
+#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
+#define DAC_INTENCLR_MASK           _U_(0xFF)    /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN0:1;      /*!< bit:      0  Underrun 0 Interrupt Enable        */
+    uint8_t  UNDERRUN1:1;      /*!< bit:      1  Underrun 1 Interrupt Enable        */
+    uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty Interrupt Enable */
+    uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty Interrupt Enable */
+    uint8_t  RESRDY0:1;        /*!< bit:      4  Result 0 Ready Interrupt Enable    */
+    uint8_t  RESRDY1:1;        /*!< bit:      5  Result 1 Ready Interrupt Enable    */
+    uint8_t  OVERRUN0:1;       /*!< bit:      6  Overrun 0 Interrupt Enable         */
+    uint8_t  OVERRUN1:1;       /*!< bit:      7  Overrun 1 Interrupt Enable         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Underrun x Interrupt Enable        */
+    uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty Interrupt Enable */
+    uint8_t  RESRDY:2;         /*!< bit:  4.. 5  Result x Ready Interrupt Enable    */
+    uint8_t  OVERRUN:2;        /*!< bit:  6.. 7  Overrun x Interrupt Enable         */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET         0x05         /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN0_Pos  0            /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN0      (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
+#define DAC_INTENSET_UNDERRUN1_Pos  1            /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN1      (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
+#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN_Msk   (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
+#define DAC_INTENSET_EMPTY0_Pos     2            /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY0         (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
+#define DAC_INTENSET_EMPTY1_Pos     3            /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY1         (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
+#define DAC_INTENSET_EMPTY_Pos      2            /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY_Msk      (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_EMPTY(value)   (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
+#define DAC_INTENSET_RESRDY0_Pos    4            /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY0        (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
+#define DAC_INTENSET_RESRDY1_Pos    5            /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY1        (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
+#define DAC_INTENSET_RESRDY_Pos     4            /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
+#define DAC_INTENSET_RESRDY_Msk     (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
+#define DAC_INTENSET_RESRDY(value)  (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
+#define DAC_INTENSET_OVERRUN0_Pos   6            /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
+#define DAC_INTENSET_OVERRUN0       (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
+#define DAC_INTENSET_OVERRUN1_Pos   7            /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
+#define DAC_INTENSET_OVERRUN1       (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
+#define DAC_INTENSET_OVERRUN_Pos    6            /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
+#define DAC_INTENSET_OVERRUN_Msk    (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
+#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
+#define DAC_INTENSET_MASK           _U_(0xFF)    /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  UNDERRUN0:1;      /*!< bit:      0  Result 0 Underrun                  */
+    __I uint8_t  UNDERRUN1:1;      /*!< bit:      1  Result 1 Underrun                  */
+    __I uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty                */
+    __I uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty                */
+    __I uint8_t  RESRDY0:1;        /*!< bit:      4  Result 0 Ready                     */
+    __I uint8_t  RESRDY1:1;        /*!< bit:      5  Result 1 Ready                     */
+    __I uint8_t  OVERRUN0:1;       /*!< bit:      6  Result 0 Overrun                   */
+    __I uint8_t  OVERRUN1:1;       /*!< bit:      7  Result 1 Overrun                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Result x Underrun                  */
+    __I uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty                */
+    __I uint8_t  RESRDY:2;         /*!< bit:  4.. 5  Result x Ready                     */
+    __I uint8_t  OVERRUN:2;        /*!< bit:  6.. 7  Result x Overrun                   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET          0x06         /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN0_Pos   0            /**< \brief (DAC_INTFLAG) Result 0 Underrun */
+#define DAC_INTFLAG_UNDERRUN0       (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
+#define DAC_INTFLAG_UNDERRUN1_Pos   1            /**< \brief (DAC_INTFLAG) Result 1 Underrun */
+#define DAC_INTFLAG_UNDERRUN1       (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
+#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Result x Underrun */
+#define DAC_INTFLAG_UNDERRUN_Msk    (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
+#define DAC_INTFLAG_EMPTY0_Pos      2            /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
+#define DAC_INTFLAG_EMPTY0          (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
+#define DAC_INTFLAG_EMPTY1_Pos      3            /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
+#define DAC_INTFLAG_EMPTY1          (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
+#define DAC_INTFLAG_EMPTY_Pos       2            /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
+#define DAC_INTFLAG_EMPTY_Msk       (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_EMPTY(value)    (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
+#define DAC_INTFLAG_RESRDY0_Pos     4            /**< \brief (DAC_INTFLAG) Result 0 Ready */
+#define DAC_INTFLAG_RESRDY0         (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
+#define DAC_INTFLAG_RESRDY1_Pos     5            /**< \brief (DAC_INTFLAG) Result 1 Ready */
+#define DAC_INTFLAG_RESRDY1         (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
+#define DAC_INTFLAG_RESRDY_Pos      4            /**< \brief (DAC_INTFLAG) Result x Ready */
+#define DAC_INTFLAG_RESRDY_Msk      (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
+#define DAC_INTFLAG_RESRDY(value)   (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
+#define DAC_INTFLAG_OVERRUN0_Pos    6            /**< \brief (DAC_INTFLAG) Result 0 Overrun */
+#define DAC_INTFLAG_OVERRUN0        (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
+#define DAC_INTFLAG_OVERRUN1_Pos    7            /**< \brief (DAC_INTFLAG) Result 1 Overrun */
+#define DAC_INTFLAG_OVERRUN1        (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
+#define DAC_INTFLAG_OVERRUN_Pos     6            /**< \brief (DAC_INTFLAG) Result x Overrun */
+#define DAC_INTFLAG_OVERRUN_Msk     (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
+#define DAC_INTFLAG_OVERRUN(value)  (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
+#define DAC_INTFLAG_MASK            _U_(0xFF)    /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  DAC 0 Startup Ready                */
+    uint8_t  READY1:1;         /*!< bit:      1  DAC 1 Startup Ready                */
+    uint8_t  EOC0:1;           /*!< bit:      2  DAC 0 End of Conversion            */
+    uint8_t  EOC1:1;           /*!< bit:      3  DAC 1 End of Conversion            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  DAC x Startup Ready                */
+    uint8_t  EOC:2;            /*!< bit:  2.. 3  DAC x End of Conversion            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET           0x07         /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE       _U_(0x00)    /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_READY0_Pos       0            /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
+#define DAC_STATUS_READY0           (_U_(1) << DAC_STATUS_READY0_Pos)
+#define DAC_STATUS_READY1_Pos       1            /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
+#define DAC_STATUS_READY1           (_U_(1) << DAC_STATUS_READY1_Pos)
+#define DAC_STATUS_READY_Pos        0            /**< \brief (DAC_STATUS) DAC x Startup Ready */
+#define DAC_STATUS_READY_Msk        (_U_(0x3) << DAC_STATUS_READY_Pos)
+#define DAC_STATUS_READY(value)     (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
+#define DAC_STATUS_EOC0_Pos         2            /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
+#define DAC_STATUS_EOC0             (_U_(1) << DAC_STATUS_EOC0_Pos)
+#define DAC_STATUS_EOC1_Pos         3            /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
+#define DAC_STATUS_EOC1             (_U_(1) << DAC_STATUS_EOC1_Pos)
+#define DAC_STATUS_EOC_Pos          2            /**< \brief (DAC_STATUS) DAC x End of Conversion */
+#define DAC_STATUS_EOC_Msk          (_U_(0x3) << DAC_STATUS_EOC_Pos)
+#define DAC_STATUS_EOC(value)       (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
+#define DAC_STATUS_MASK             _U_(0x0F)    /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  DAC Enable Status                  */
+    uint32_t DATA0:1;          /*!< bit:      2  Data DAC 0                         */
+    uint32_t DATA1:1;          /*!< bit:      3  Data DAC 1                         */
+    uint32_t DATABUF0:1;       /*!< bit:      4  Data Buffer DAC 0                  */
+    uint32_t DATABUF1:1;       /*!< bit:      5  Data Buffer DAC 1                  */
+    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t DATA:2;           /*!< bit:  2.. 3  Data DAC x                         */
+    uint32_t DATABUF:2;        /*!< bit:  4.. 5  Data Buffer DAC x                  */
+    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DAC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_SYNCBUSY_OFFSET         0x08         /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
+#define DAC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define DAC_SYNCBUSY_SWRST_Pos      0            /**< \brief (DAC_SYNCBUSY) Software Reset */
+#define DAC_SYNCBUSY_SWRST          (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
+#define DAC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
+#define DAC_SYNCBUSY_ENABLE         (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
+#define DAC_SYNCBUSY_DATA0_Pos      2            /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
+#define DAC_SYNCBUSY_DATA0          (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
+#define DAC_SYNCBUSY_DATA1_Pos      3            /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
+#define DAC_SYNCBUSY_DATA1          (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
+#define DAC_SYNCBUSY_DATA_Pos       2            /**< \brief (DAC_SYNCBUSY) Data DAC x */
+#define DAC_SYNCBUSY_DATA_Msk       (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
+#define DAC_SYNCBUSY_DATA(value)    (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
+#define DAC_SYNCBUSY_DATABUF0_Pos   4            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
+#define DAC_SYNCBUSY_DATABUF0       (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
+#define DAC_SYNCBUSY_DATABUF1_Pos   5            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
+#define DAC_SYNCBUSY_DATABUF1       (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
+#define DAC_SYNCBUSY_DATABUF_Pos    4            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
+#define DAC_SYNCBUSY_DATABUF_Msk    (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
+#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
+#define DAC_SYNCBUSY_MASK           _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
+
+/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LEFTADJ:1;        /*!< bit:      0  Left Adjusted Data                 */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable DAC0                        */
+    uint16_t CCTRL:2;          /*!< bit:  2.. 3  Current Control                    */
+    uint16_t :1;               /*!< bit:      4  Reserved                           */
+    uint16_t FEXT:1;           /*!< bit:      5  Standalone Filter                  */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t DITHER:1;         /*!< bit:      7  Dithering Mode                     */
+    uint16_t REFRESH:4;        /*!< bit:  8..11  Refresh period                     */
+    uint16_t :1;               /*!< bit:     12  Reserved                           */
+    uint16_t OSR:3;            /*!< bit: 13..15  Sampling Rate                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DACCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DACCTRL_OFFSET          0x0C         /**< \brief (DAC_DACCTRL offset) DAC n Control */
+#define DAC_DACCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
+
+#define DAC_DACCTRL_LEFTADJ_Pos     0            /**< \brief (DAC_DACCTRL) Left Adjusted Data */
+#define DAC_DACCTRL_LEFTADJ         (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
+#define DAC_DACCTRL_ENABLE_Pos      1            /**< \brief (DAC_DACCTRL) Enable DAC0 */
+#define DAC_DACCTRL_ENABLE          (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
+#define DAC_DACCTRL_CCTRL_Pos       2            /**< \brief (DAC_DACCTRL) Current Control */
+#define DAC_DACCTRL_CCTRL_Msk       (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL(value)    (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
+#define   DAC_DACCTRL_CCTRL_CC100K_Val    _U_(0x0)   /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
+#define   DAC_DACCTRL_CCTRL_CC1M_Val      _U_(0x1)   /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC  ≤ 6MHz (500kSPS) */
+#define   DAC_DACCTRL_CCTRL_CC12M_Val     _U_(0x2)   /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
+#define DAC_DACCTRL_CCTRL_CC100K    (DAC_DACCTRL_CCTRL_CC100K_Val  << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC1M      (DAC_DACCTRL_CCTRL_CC1M_Val    << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC12M     (DAC_DACCTRL_CCTRL_CC12M_Val   << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_FEXT_Pos        5            /**< \brief (DAC_DACCTRL) Standalone Filter */
+#define DAC_DACCTRL_FEXT            (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
+#define DAC_DACCTRL_RUNSTDBY_Pos    6            /**< \brief (DAC_DACCTRL) Run in Standby */
+#define DAC_DACCTRL_RUNSTDBY        (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
+#define DAC_DACCTRL_DITHER_Pos      7            /**< \brief (DAC_DACCTRL) Dithering Mode */
+#define DAC_DACCTRL_DITHER          (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
+#define DAC_DACCTRL_REFRESH_Pos     8            /**< \brief (DAC_DACCTRL) Refresh period */
+#define DAC_DACCTRL_REFRESH_Msk     (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
+#define DAC_DACCTRL_REFRESH(value)  (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
+#define DAC_DACCTRL_OSR_Pos         13           /**< \brief (DAC_DACCTRL) Sampling Rate */
+#define DAC_DACCTRL_OSR_Msk         (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
+#define DAC_DACCTRL_OSR(value)      (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
+#define DAC_DACCTRL_MASK            _U_(0xEFEF)  /**< \brief (DAC_DACCTRL) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:16;          /*!< bit:  0..15  DAC0 Data                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET             0x10         /**< \brief (DAC_DATA offset) DAC n Data */
+#define DAC_DATA_RESETVALUE         _U_(0x0000)  /**< \brief (DAC_DATA reset_value) DAC n Data */
+
+#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) DAC0 Data */
+#define DAC_DATA_DATA_Msk           (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK               _U_(0xFFFF)  /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATABUF:16;       /*!< bit:  0..15  DAC0 Data Buffer                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET          0x14         /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
+#define DAC_DATABUF_RESETVALUE      _U_(0x0000)  /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk     (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK            _U_(0xFFFF)  /**< \brief (DAC_DATABUF) MASK Register */
+
+/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DBGCTRL_OFFSET          0x18         /**< \brief (DAC_DBGCTRL offset) Debug Control */
+#define DAC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
+
+#define DAC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (DAC_DBGCTRL) Debug Run */
+#define DAC_DBGCTRL_DBGRUN          (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
+#define DAC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (DAC_DBGCTRL) MASK Register */
+
+/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/  16) Filter Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Filter Result                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_RESULT_OFFSET           0x1C         /**< \brief (DAC_RESULT offset) Filter Result */
+#define DAC_RESULT_RESETVALUE       _U_(0x0000)  /**< \brief (DAC_RESULT reset_value) Filter Result */
+
+#define DAC_RESULT_RESULT_Pos       0            /**< \brief (DAC_RESULT) Filter Result */
+#define DAC_RESULT_RESULT_Msk       (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
+#define DAC_RESULT_RESULT(value)    (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
+#define DAC_RESULT_MASK             _U_(0xFFFF)  /**< \brief (DAC_RESULT) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x01 (R/W  8) Control B */
+  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x02 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x07 (R/   8) Status */
+  __I  DAC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO DAC_DACCTRL_Type          DACCTRL[2];  /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
+  __O  DAC_DATA_Type             DATA[2];     /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
+  __O  DAC_DATABUF_Type          DATABUF[2];  /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
+  __IO DAC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x18 (R/W  8) Debug Control */
+       RoReg8                    Reserved2[0x3];
+  __I  DAC_RESULT_Type           RESULT[2];   /**< \brief Offset: 0x1C (R/  16) Filter Result */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_DAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dmac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dmac.h
new file mode 100644
index 000000000..d23c21498
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dmac.h	
@@ -0,0 +1,1416 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_DMAC_COMPONENT_
+#define _SAME53_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAME53_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2503
+#define REV_DMAC                    0x101
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
+    uint16_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
+    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
+    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
+    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE        _U_(0x0000)  /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST             (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE         (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0            (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1            (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2            (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3            (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk         (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK              _U_(0x0F03)  /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
+    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
+    uint16_t CRCMODE:2;        /*!< bit: 14..15  CRC Operating Mode                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE     _U_(0x0000)  /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0)   /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1)   /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2)   /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk    (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  _U_(0x0)   /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  _U_(0x1)   /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk     (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define   DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0)   /**< \brief (DMAC_CRCCTRL) CRC Disabled */
+#define   DMAC_CRCCTRL_CRCSRC_IO_Val      _U_(0x1)   /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCMODE_Pos    14           /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
+#define DMAC_CRCCTRL_CRCMODE_Msk    (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
+#define   DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0)   /**< \brief (DMAC_CRCCTRL) Default operating mode */
+#define   DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2)   /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
+#define   DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3)   /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
+#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
+#define DMAC_CRCCTRL_MASK           _U_(0xFF0F)  /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE   _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK         _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE   _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK         _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
+    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
+    uint8_t  CRCERR:1;         /*!< bit:      2  CRC Error                          */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE   _U_(0x00)    /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY      (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO      (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_CRCERR_Pos   2            /**< \brief (DMAC_CRCSTATUS) CRC Error */
+#define DMAC_CRCSTATUS_CRCERR       (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
+#define DMAC_CRCSTATUS_MASK         _U_(0x07)    /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE     _U_(0x00)    /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN         (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK           _U_(0x01)    /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
+    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
+    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
+    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
+    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
+    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
+    uint32_t SWTRIG6:1;        /*!< bit:      6  Channel 6 Software Trigger         */
+    uint32_t SWTRIG7:1;        /*!< bit:      7  Channel 7 Software Trigger         */
+    uint32_t SWTRIG8:1;        /*!< bit:      8  Channel 8 Software Trigger         */
+    uint32_t SWTRIG9:1;        /*!< bit:      9  Channel 9 Software Trigger         */
+    uint32_t SWTRIG10:1;       /*!< bit:     10  Channel 10 Software Trigger        */
+    uint32_t SWTRIG11:1;       /*!< bit:     11  Channel 11 Software Trigger        */
+    uint32_t SWTRIG12:1;       /*!< bit:     12  Channel 12 Software Trigger        */
+    uint32_t SWTRIG13:1;       /*!< bit:     13  Channel 13 Software Trigger        */
+    uint32_t SWTRIG14:1;       /*!< bit:     14  Channel 14 Software Trigger        */
+    uint32_t SWTRIG15:1;       /*!< bit:     15  Channel 15 Software Trigger        */
+    uint32_t SWTRIG16:1;       /*!< bit:     16  Channel 16 Software Trigger        */
+    uint32_t SWTRIG17:1;       /*!< bit:     17  Channel 17 Software Trigger        */
+    uint32_t SWTRIG18:1;       /*!< bit:     18  Channel 18 Software Trigger        */
+    uint32_t SWTRIG19:1;       /*!< bit:     19  Channel 19 Software Trigger        */
+    uint32_t SWTRIG20:1;       /*!< bit:     20  Channel 20 Software Trigger        */
+    uint32_t SWTRIG21:1;       /*!< bit:     21  Channel 21 Software Trigger        */
+    uint32_t SWTRIG22:1;       /*!< bit:     22  Channel 22 Software Trigger        */
+    uint32_t SWTRIG23:1;       /*!< bit:     23  Channel 23 Software Trigger        */
+    uint32_t SWTRIG24:1;       /*!< bit:     24  Channel 24 Software Trigger        */
+    uint32_t SWTRIG25:1;       /*!< bit:     25  Channel 25 Software Trigger        */
+    uint32_t SWTRIG26:1;       /*!< bit:     26  Channel 26 Software Trigger        */
+    uint32_t SWTRIG27:1;       /*!< bit:     27  Channel 27 Software Trigger        */
+    uint32_t SWTRIG28:1;       /*!< bit:     28  Channel 28 Software Trigger        */
+    uint32_t SWTRIG29:1;       /*!< bit:     29  Channel 29 Software Trigger        */
+    uint32_t SWTRIG30:1;       /*!< bit:     30  Channel 30 Software Trigger        */
+    uint32_t SWTRIG31:1;       /*!< bit:     31  Channel 31 Software Trigger        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t SWTRIG:32;        /*!< bit:  0..31  Channel x Software Trigger         */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE  _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6            /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7            /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8            /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9            /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10           /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12           /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG12    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13           /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG13    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14           /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG14    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15           /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG15    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16           /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG16    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17           /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG17    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18           /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG18    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19           /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG19    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20           /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG20    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21           /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG21    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22           /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG22    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23           /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG23    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24           /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG24    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25           /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG25    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26           /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG26    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27           /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG27    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28           /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG28    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29           /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG29    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30           /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG30    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31           /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG31    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK        _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLPRI0:5;        /*!< bit:  0.. 4  Level 0 Channel Priority Number    */
+    uint32_t QOS0:2;           /*!< bit:  5.. 6  Level 0 Quality of Service         */
+    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI1:5;        /*!< bit:  8..12  Level 1 Channel Priority Number    */
+    uint32_t QOS1:2;           /*!< bit: 13..14  Level 1 Quality of Service         */
+    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI2:5;        /*!< bit: 16..20  Level 2 Channel Priority Number    */
+    uint32_t QOS2:2;           /*!< bit: 21..22  Level 2 Quality of Service         */
+    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
+    uint32_t LVLPRI3:5;        /*!< bit: 24..28  Level 3 Channel Priority Number    */
+    uint32_t QOS3:2;           /*!< bit: 29..30  Level 3 Quality of Service         */
+    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE    _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_QOS0_Pos      5            /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
+#define DMAC_PRICTRL0_QOS0_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0(value)   (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
+#define   DMAC_PRICTRL0_QOS0_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define   DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define   DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define   DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS0_REGULAR  (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
+#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_QOS1_Pos      13           /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
+#define DMAC_PRICTRL0_QOS1_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1(value)   (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
+#define   DMAC_PRICTRL0_QOS1_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define   DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define   DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define   DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS1_REGULAR  (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
+#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_QOS2_Pos      21           /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
+#define DMAC_PRICTRL0_QOS2_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2(value)   (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
+#define   DMAC_PRICTRL0_QOS2_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define   DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define   DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define   DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS2_REGULAR  (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
+#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_QOS3_Pos      29           /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
+#define DMAC_PRICTRL0_QOS3_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3(value)   (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
+#define   DMAC_PRICTRL0_QOS3_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
+#define   DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
+#define   DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
+#define   DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
+#define DMAC_PRICTRL0_QOS3_REGULAR  (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
+#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK          _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:5;             /*!< bit:  0.. 4  Channel ID                         */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
+    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
+    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t CRCERR:1;         /*!< bit:     12  CRC Error                          */
+    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
+    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
+    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE     _U_(0x0000)  /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk         (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR           (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL          (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP           (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_CRCERR_Pos     12           /**< \brief (DMAC_INTPEND) CRC Error */
+#define DMAC_INTPEND_CRCERR         (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
+#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR           (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY           (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND           (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK           _U_(0xF71F)  /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
+    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
+    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
+    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
+    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
+    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
+    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
+    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
+    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
+    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
+    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
+    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
+    uint32_t CHINT12:1;        /*!< bit:     12  Channel 12 Pending Interrupt       */
+    uint32_t CHINT13:1;        /*!< bit:     13  Channel 13 Pending Interrupt       */
+    uint32_t CHINT14:1;        /*!< bit:     14  Channel 14 Pending Interrupt       */
+    uint32_t CHINT15:1;        /*!< bit:     15  Channel 15 Pending Interrupt       */
+    uint32_t CHINT16:1;        /*!< bit:     16  Channel 16 Pending Interrupt       */
+    uint32_t CHINT17:1;        /*!< bit:     17  Channel 17 Pending Interrupt       */
+    uint32_t CHINT18:1;        /*!< bit:     18  Channel 18 Pending Interrupt       */
+    uint32_t CHINT19:1;        /*!< bit:     19  Channel 19 Pending Interrupt       */
+    uint32_t CHINT20:1;        /*!< bit:     20  Channel 20 Pending Interrupt       */
+    uint32_t CHINT21:1;        /*!< bit:     21  Channel 21 Pending Interrupt       */
+    uint32_t CHINT22:1;        /*!< bit:     22  Channel 22 Pending Interrupt       */
+    uint32_t CHINT23:1;        /*!< bit:     23  Channel 23 Pending Interrupt       */
+    uint32_t CHINT24:1;        /*!< bit:     24  Channel 24 Pending Interrupt       */
+    uint32_t CHINT25:1;        /*!< bit:     25  Channel 25 Pending Interrupt       */
+    uint32_t CHINT26:1;        /*!< bit:     26  Channel 26 Pending Interrupt       */
+    uint32_t CHINT27:1;        /*!< bit:     27  Channel 27 Pending Interrupt       */
+    uint32_t CHINT28:1;        /*!< bit:     28  Channel 28 Pending Interrupt       */
+    uint32_t CHINT29:1;        /*!< bit:     29  Channel 29 Pending Interrupt       */
+    uint32_t CHINT30:1;        /*!< bit:     30  Channel 30 Pending Interrupt       */
+    uint32_t CHINT31:1;        /*!< bit:     31  Channel 31 Pending Interrupt       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHINT:32;         /*!< bit:  0..31  Channel x Pending Interrupt        */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE   _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0       (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1       (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2       (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3       (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4       (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5       (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos   6            /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6       (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos   7            /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7       (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos   8            /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8       (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos   9            /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9       (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos  10           /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10      (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11      (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT12_Pos  12           /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT12      (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
+#define DMAC_INTSTATUS_CHINT13_Pos  13           /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT13      (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
+#define DMAC_INTSTATUS_CHINT14_Pos  14           /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT14      (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
+#define DMAC_INTSTATUS_CHINT15_Pos  15           /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT15      (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
+#define DMAC_INTSTATUS_CHINT16_Pos  16           /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT16      (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
+#define DMAC_INTSTATUS_CHINT17_Pos  17           /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT17      (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
+#define DMAC_INTSTATUS_CHINT18_Pos  18           /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT18      (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
+#define DMAC_INTSTATUS_CHINT19_Pos  19           /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT19      (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
+#define DMAC_INTSTATUS_CHINT20_Pos  20           /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT20      (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
+#define DMAC_INTSTATUS_CHINT21_Pos  21           /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT21      (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
+#define DMAC_INTSTATUS_CHINT22_Pos  22           /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT22      (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
+#define DMAC_INTSTATUS_CHINT23_Pos  23           /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT23      (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
+#define DMAC_INTSTATUS_CHINT24_Pos  24           /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT24      (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
+#define DMAC_INTSTATUS_CHINT25_Pos  25           /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT25      (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
+#define DMAC_INTSTATUS_CHINT26_Pos  26           /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT26      (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
+#define DMAC_INTSTATUS_CHINT27_Pos  27           /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT27      (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
+#define DMAC_INTSTATUS_CHINT28_Pos  28           /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT28      (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
+#define DMAC_INTSTATUS_CHINT29_Pos  29           /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT29      (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
+#define DMAC_INTSTATUS_CHINT30_Pos  30           /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT30      (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
+#define DMAC_INTSTATUS_CHINT31_Pos  31           /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT31      (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk    (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK         _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
+    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
+    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
+    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
+    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
+    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
+    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
+    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
+    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
+    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
+    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
+    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
+    uint32_t BUSYCH12:1;       /*!< bit:     12  Busy Channel 12                    */
+    uint32_t BUSYCH13:1;       /*!< bit:     13  Busy Channel 13                    */
+    uint32_t BUSYCH14:1;       /*!< bit:     14  Busy Channel 14                    */
+    uint32_t BUSYCH15:1;       /*!< bit:     15  Busy Channel 15                    */
+    uint32_t BUSYCH16:1;       /*!< bit:     16  Busy Channel 16                    */
+    uint32_t BUSYCH17:1;       /*!< bit:     17  Busy Channel 17                    */
+    uint32_t BUSYCH18:1;       /*!< bit:     18  Busy Channel 18                    */
+    uint32_t BUSYCH19:1;       /*!< bit:     19  Busy Channel 19                    */
+    uint32_t BUSYCH20:1;       /*!< bit:     20  Busy Channel 20                    */
+    uint32_t BUSYCH21:1;       /*!< bit:     21  Busy Channel 21                    */
+    uint32_t BUSYCH22:1;       /*!< bit:     22  Busy Channel 22                    */
+    uint32_t BUSYCH23:1;       /*!< bit:     23  Busy Channel 23                    */
+    uint32_t BUSYCH24:1;       /*!< bit:     24  Busy Channel 24                    */
+    uint32_t BUSYCH25:1;       /*!< bit:     25  Busy Channel 25                    */
+    uint32_t BUSYCH26:1;       /*!< bit:     26  Busy Channel 26                    */
+    uint32_t BUSYCH27:1;       /*!< bit:     27  Busy Channel 27                    */
+    uint32_t BUSYCH28:1;       /*!< bit:     28  Busy Channel 28                    */
+    uint32_t BUSYCH29:1;       /*!< bit:     29  Busy Channel 29                    */
+    uint32_t BUSYCH30:1;       /*!< bit:     30  Busy Channel 30                    */
+    uint32_t BUSYCH31:1;       /*!< bit:     31  Busy Channel 31                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t BUSYCH:32;        /*!< bit:  0..31  Busy Channel x                     */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE      _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0         (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1         (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2         (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3         (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4         (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5         (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos     6            /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6         (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos     7            /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7         (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos     8            /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8         (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos     9            /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9         (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos    10           /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10        (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11        (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH12_Pos    12           /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
+#define DMAC_BUSYCH_BUSYCH12        (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
+#define DMAC_BUSYCH_BUSYCH13_Pos    13           /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
+#define DMAC_BUSYCH_BUSYCH13        (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
+#define DMAC_BUSYCH_BUSYCH14_Pos    14           /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
+#define DMAC_BUSYCH_BUSYCH14        (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
+#define DMAC_BUSYCH_BUSYCH15_Pos    15           /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
+#define DMAC_BUSYCH_BUSYCH15        (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
+#define DMAC_BUSYCH_BUSYCH16_Pos    16           /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
+#define DMAC_BUSYCH_BUSYCH16        (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
+#define DMAC_BUSYCH_BUSYCH17_Pos    17           /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
+#define DMAC_BUSYCH_BUSYCH17        (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
+#define DMAC_BUSYCH_BUSYCH18_Pos    18           /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
+#define DMAC_BUSYCH_BUSYCH18        (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
+#define DMAC_BUSYCH_BUSYCH19_Pos    19           /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
+#define DMAC_BUSYCH_BUSYCH19        (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
+#define DMAC_BUSYCH_BUSYCH20_Pos    20           /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
+#define DMAC_BUSYCH_BUSYCH20        (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
+#define DMAC_BUSYCH_BUSYCH21_Pos    21           /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
+#define DMAC_BUSYCH_BUSYCH21        (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
+#define DMAC_BUSYCH_BUSYCH22_Pos    22           /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
+#define DMAC_BUSYCH_BUSYCH22        (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
+#define DMAC_BUSYCH_BUSYCH23_Pos    23           /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
+#define DMAC_BUSYCH_BUSYCH23        (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
+#define DMAC_BUSYCH_BUSYCH24_Pos    24           /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
+#define DMAC_BUSYCH_BUSYCH24        (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
+#define DMAC_BUSYCH_BUSYCH25_Pos    25           /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
+#define DMAC_BUSYCH_BUSYCH25        (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
+#define DMAC_BUSYCH_BUSYCH26_Pos    26           /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
+#define DMAC_BUSYCH_BUSYCH26        (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
+#define DMAC_BUSYCH_BUSYCH27_Pos    27           /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
+#define DMAC_BUSYCH_BUSYCH27        (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
+#define DMAC_BUSYCH_BUSYCH28_Pos    28           /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
+#define DMAC_BUSYCH_BUSYCH28        (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
+#define DMAC_BUSYCH_BUSYCH29_Pos    29           /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
+#define DMAC_BUSYCH_BUSYCH29        (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
+#define DMAC_BUSYCH_BUSYCH30_Pos    30           /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
+#define DMAC_BUSYCH_BUSYCH30        (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
+#define DMAC_BUSYCH_BUSYCH31_Pos    31           /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
+#define DMAC_BUSYCH_BUSYCH31        (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk      (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK            _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
+    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
+    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
+    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
+    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
+    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
+    uint32_t PENDCH6:1;        /*!< bit:      6  Pending Channel 6                  */
+    uint32_t PENDCH7:1;        /*!< bit:      7  Pending Channel 7                  */
+    uint32_t PENDCH8:1;        /*!< bit:      8  Pending Channel 8                  */
+    uint32_t PENDCH9:1;        /*!< bit:      9  Pending Channel 9                  */
+    uint32_t PENDCH10:1;       /*!< bit:     10  Pending Channel 10                 */
+    uint32_t PENDCH11:1;       /*!< bit:     11  Pending Channel 11                 */
+    uint32_t PENDCH12:1;       /*!< bit:     12  Pending Channel 12                 */
+    uint32_t PENDCH13:1;       /*!< bit:     13  Pending Channel 13                 */
+    uint32_t PENDCH14:1;       /*!< bit:     14  Pending Channel 14                 */
+    uint32_t PENDCH15:1;       /*!< bit:     15  Pending Channel 15                 */
+    uint32_t PENDCH16:1;       /*!< bit:     16  Pending Channel 16                 */
+    uint32_t PENDCH17:1;       /*!< bit:     17  Pending Channel 17                 */
+    uint32_t PENDCH18:1;       /*!< bit:     18  Pending Channel 18                 */
+    uint32_t PENDCH19:1;       /*!< bit:     19  Pending Channel 19                 */
+    uint32_t PENDCH20:1;       /*!< bit:     20  Pending Channel 20                 */
+    uint32_t PENDCH21:1;       /*!< bit:     21  Pending Channel 21                 */
+    uint32_t PENDCH22:1;       /*!< bit:     22  Pending Channel 22                 */
+    uint32_t PENDCH23:1;       /*!< bit:     23  Pending Channel 23                 */
+    uint32_t PENDCH24:1;       /*!< bit:     24  Pending Channel 24                 */
+    uint32_t PENDCH25:1;       /*!< bit:     25  Pending Channel 25                 */
+    uint32_t PENDCH26:1;       /*!< bit:     26  Pending Channel 26                 */
+    uint32_t PENDCH27:1;       /*!< bit:     27  Pending Channel 27                 */
+    uint32_t PENDCH28:1;       /*!< bit:     28  Pending Channel 28                 */
+    uint32_t PENDCH29:1;       /*!< bit:     29  Pending Channel 29                 */
+    uint32_t PENDCH30:1;       /*!< bit:     30  Pending Channel 30                 */
+    uint32_t PENDCH31:1;       /*!< bit:     31  Pending Channel 31                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PENDCH:32;        /*!< bit:  0..31  Pending Channel x                  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE      _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0         (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1         (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2         (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3         (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4         (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5         (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos     6            /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6         (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos     7            /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7         (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos     8            /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8         (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos     9            /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9         (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos    10           /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10        (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11        (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH12_Pos    12           /**< \brief (DMAC_PENDCH) Pending Channel 12 */
+#define DMAC_PENDCH_PENDCH12        (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
+#define DMAC_PENDCH_PENDCH13_Pos    13           /**< \brief (DMAC_PENDCH) Pending Channel 13 */
+#define DMAC_PENDCH_PENDCH13        (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
+#define DMAC_PENDCH_PENDCH14_Pos    14           /**< \brief (DMAC_PENDCH) Pending Channel 14 */
+#define DMAC_PENDCH_PENDCH14        (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
+#define DMAC_PENDCH_PENDCH15_Pos    15           /**< \brief (DMAC_PENDCH) Pending Channel 15 */
+#define DMAC_PENDCH_PENDCH15        (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
+#define DMAC_PENDCH_PENDCH16_Pos    16           /**< \brief (DMAC_PENDCH) Pending Channel 16 */
+#define DMAC_PENDCH_PENDCH16        (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
+#define DMAC_PENDCH_PENDCH17_Pos    17           /**< \brief (DMAC_PENDCH) Pending Channel 17 */
+#define DMAC_PENDCH_PENDCH17        (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
+#define DMAC_PENDCH_PENDCH18_Pos    18           /**< \brief (DMAC_PENDCH) Pending Channel 18 */
+#define DMAC_PENDCH_PENDCH18        (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
+#define DMAC_PENDCH_PENDCH19_Pos    19           /**< \brief (DMAC_PENDCH) Pending Channel 19 */
+#define DMAC_PENDCH_PENDCH19        (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
+#define DMAC_PENDCH_PENDCH20_Pos    20           /**< \brief (DMAC_PENDCH) Pending Channel 20 */
+#define DMAC_PENDCH_PENDCH20        (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
+#define DMAC_PENDCH_PENDCH21_Pos    21           /**< \brief (DMAC_PENDCH) Pending Channel 21 */
+#define DMAC_PENDCH_PENDCH21        (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
+#define DMAC_PENDCH_PENDCH22_Pos    22           /**< \brief (DMAC_PENDCH) Pending Channel 22 */
+#define DMAC_PENDCH_PENDCH22        (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
+#define DMAC_PENDCH_PENDCH23_Pos    23           /**< \brief (DMAC_PENDCH) Pending Channel 23 */
+#define DMAC_PENDCH_PENDCH23        (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
+#define DMAC_PENDCH_PENDCH24_Pos    24           /**< \brief (DMAC_PENDCH) Pending Channel 24 */
+#define DMAC_PENDCH_PENDCH24        (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
+#define DMAC_PENDCH_PENDCH25_Pos    25           /**< \brief (DMAC_PENDCH) Pending Channel 25 */
+#define DMAC_PENDCH_PENDCH25        (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
+#define DMAC_PENDCH_PENDCH26_Pos    26           /**< \brief (DMAC_PENDCH) Pending Channel 26 */
+#define DMAC_PENDCH_PENDCH26        (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
+#define DMAC_PENDCH_PENDCH27_Pos    27           /**< \brief (DMAC_PENDCH) Pending Channel 27 */
+#define DMAC_PENDCH_PENDCH27        (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
+#define DMAC_PENDCH_PENDCH28_Pos    28           /**< \brief (DMAC_PENDCH) Pending Channel 28 */
+#define DMAC_PENDCH_PENDCH28        (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
+#define DMAC_PENDCH_PENDCH29_Pos    29           /**< \brief (DMAC_PENDCH) Pending Channel 29 */
+#define DMAC_PENDCH_PENDCH29        (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
+#define DMAC_PENDCH_PENDCH30_Pos    30           /**< \brief (DMAC_PENDCH) Pending Channel 30 */
+#define DMAC_PENDCH_PENDCH30        (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
+#define DMAC_PENDCH_PENDCH31_Pos    31           /**< \brief (DMAC_PENDCH) Pending Channel 31 */
+#define DMAC_PENDCH_PENDCH31        (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
+#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk      (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK            _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
+    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
+    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
+    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
+    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE      _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0          (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1          (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2          (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3          (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk       (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk          (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY           (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk       (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK            _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE    _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk  (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK          _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE     _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk    (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK           _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Channel Software Reset             */
+    uint32_t ENABLE:1;         /*!< bit:      1  Channel Enable                     */
+    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Channel Run in Standby             */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t TRIGSRC:7;        /*!< bit:  8..14  Trigger Source                     */
+    uint32_t :5;               /*!< bit: 15..19  Reserved                           */
+    uint32_t TRIGACT:2;        /*!< bit: 20..21  Trigger Action                     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t BURSTLEN:4;       /*!< bit: 24..27  Burst Length                       */
+    uint32_t THRESHOLD:2;      /*!< bit: 28..29  FIFO Threshold                     */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
+#define DMAC_CHCTRLA_RESETVALUE     _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST          (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE         (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_RUNSTDBY_Pos   6            /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
+#define DMAC_CHCTRLA_RUNSTDBY       (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
+#define DMAC_CHCTRLA_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLA) Trigger Source */
+#define DMAC_CHCTRLA_TRIGSRC_Msk    (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
+#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
+#define   DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0)   /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
+#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
+#define DMAC_CHCTRLA_TRIGACT_Pos    20           /**< \brief (DMAC_CHCTRLA) Trigger Action */
+#define DMAC_CHCTRLA_TRIGACT_Msk    (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
+#define   DMAC_CHCTRLA_TRIGACT_BLOCK_Val  _U_(0x0)   /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
+#define   DMAC_CHCTRLA_TRIGACT_BURST_Val  _U_(0x2)   /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
+#define   DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3)   /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
+#define DMAC_CHCTRLA_TRIGACT_BLOCK  (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT_BURST  (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_Pos   24           /**< \brief (DMAC_CHCTRLA) Burst Length */
+#define DMAC_CHCTRLA_BURSTLEN_Msk   (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
+#define   DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0)   /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1)   /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2)   /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3)   /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4)   /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5)   /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6)   /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7)   /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8)   /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9)   /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA)   /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB)   /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC)   /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD)   /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE)   /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
+#define   DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF)   /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
+#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_Pos  28           /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
+#define DMAC_CHCTRLA_THRESHOLD_Msk  (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
+#define   DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0)   /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
+#define   DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1)   /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
+#define   DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2)   /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
+#define   DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3)   /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
+#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
+#define DMAC_CHCTRLA_MASK           _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W  8) CHANNEL Channel n Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMD:2;            /*!< bit:  0.. 1  Software Command                   */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
+#define DMAC_CHCTRLB_RESETVALUE     _U_(0x00)    /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
+
+#define DMAC_CHCTRLB_CMD_Pos        0            /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk        (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define   DMAC_CHCTRLB_CMD_NOACT_Val      _U_(0x0)   /**< \brief (DMAC_CHCTRLB) No action */
+#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    _U_(0x1)   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define   DMAC_CHCTRLB_CMD_RESUME_Val     _U_(0x2)   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK           _U_(0x03)    /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W  8) CHANNEL Channel n Priority Level -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PRILVL:2;         /*!< bit:  0.. 1  Channel Priority Level             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHPRILVL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHPRILVL_OFFSET        0x45         /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
+#define DMAC_CHPRILVL_RESETVALUE    _U_(0x00)    /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
+
+#define DMAC_CHPRILVL_PRILVL_Pos    0            /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
+#define DMAC_CHPRILVL_PRILVL_Msk    (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
+#define   DMAC_CHPRILVL_PRILVL_LVL0_Val   _U_(0x0)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
+#define   DMAC_CHPRILVL_PRILVL_LVL1_Val   _U_(0x1)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
+#define   DMAC_CHPRILVL_PRILVL_LVL2_Val   _U_(0x2)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
+#define   DMAC_CHPRILVL_PRILVL_LVL3_Val   _U_(0x3)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
+#define   DMAC_CHPRILVL_PRILVL_LVL4_Val   _U_(0x4)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
+#define   DMAC_CHPRILVL_PRILVL_LVL5_Val   _U_(0x5)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
+#define   DMAC_CHPRILVL_PRILVL_LVL6_Val   _U_(0x6)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
+#define   DMAC_CHPRILVL_PRILVL_LVL7_Val   _U_(0x7)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
+#define DMAC_CHPRILVL_PRILVL_LVL0   (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL1   (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL2   (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL3   (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL4   (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL5   (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL6   (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_PRILVL_LVL7   (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
+#define DMAC_CHPRILVL_MASK          _U_(0x03)    /**< \brief (DMAC_CHPRILVL) MASK Register */
+
+/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W  8) CHANNEL Channel n Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EVACT:3;          /*!< bit:  0.. 2  Channel Event Input Action         */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EVOMODE:2;        /*!< bit:  4.. 5  Channel Event Output Mode          */
+    uint8_t  EVIE:1;           /*!< bit:      6  Channel Event Input Enable         */
+    uint8_t  EVOE:1;           /*!< bit:      7  Channel Event Output Enable        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHEVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHEVCTRL_OFFSET        0x46         /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
+#define DMAC_CHEVCTRL_RESETVALUE    _U_(0x00)    /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
+
+#define DMAC_CHEVCTRL_EVACT_Pos     0            /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
+#define DMAC_CHEVCTRL_EVACT_Msk     (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT(value)  (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
+#define   DMAC_CHEVCTRL_EVACT_NOACT_Val   _U_(0x0)   /**< \brief (DMAC_CHEVCTRL) No action */
+#define   DMAC_CHEVCTRL_EVACT_TRIG_Val    _U_(0x1)   /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
+#define   DMAC_CHEVCTRL_EVACT_CTRIG_Val   _U_(0x2)   /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
+#define   DMAC_CHEVCTRL_EVACT_CBLOCK_Val  _U_(0x3)   /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
+#define   DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4)   /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
+#define   DMAC_CHEVCTRL_EVACT_RESUME_Val  _U_(0x5)   /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
+#define   DMAC_CHEVCTRL_EVACT_SSKIP_Val   _U_(0x6)   /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
+#define   DMAC_CHEVCTRL_EVACT_INCPRI_Val  _U_(0x7)   /**< \brief (DMAC_CHEVCTRL) Increase priority */
+#define DMAC_CHEVCTRL_EVACT_NOACT   (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_TRIG    (DMAC_CHEVCTRL_EVACT_TRIG_Val  << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_CTRIG   (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_CBLOCK  (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_RESUME  (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_SSKIP   (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVACT_INCPRI  (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
+#define DMAC_CHEVCTRL_EVOMODE_Pos   4            /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
+#define DMAC_CHEVCTRL_EVOMODE_Msk   (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
+#define   DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0)   /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
+#define   DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1)   /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
+#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
+#define DMAC_CHEVCTRL_EVIE_Pos      6            /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
+#define DMAC_CHEVCTRL_EVIE          (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
+#define DMAC_CHEVCTRL_EVOE_Pos      7            /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
+#define DMAC_CHEVCTRL_EVOE          (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
+#define DMAC_CHEVCTRL_MASK          _U_(0xF7)    /**< \brief (DMAC_CHEVCTRL) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) CHANNEL Channel n Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error Interrupt Enable */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE  _U_(0x00)    /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR        (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL       (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP        (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK        _U_(0x07)    /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) CHANNEL Channel n Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error Interrupt Enable */
+    uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete Interrupt Enable */
+    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE  _U_(0x00)    /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR        (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL       (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP        (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK        _U_(0x07)    /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error             */
+    __I uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete          */
+    __I uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE   _U_(0x00)    /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR         (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL        (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP         (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK         _U_(0x07)    /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W  8) CHANNEL Channel n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
+    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
+    uint8_t  FERR:1;           /*!< bit:      2  Channel Fetch Error                */
+    uint8_t  CRCERR:1;         /*!< bit:      3  Channel CRC Error                  */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
+#define DMAC_CHSTATUS_RESETVALUE    _U_(0x00)    /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
+
+#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND          (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY          (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR          (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_CRCERR_Pos    3            /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
+#define DMAC_CHSTATUS_CRCERR        (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
+#define DMAC_CHSTATUS_MASK          _U_(0x0F)    /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
+    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Block Event Output Selection       */
+    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
+    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
+    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
+    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
+    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID           (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk      (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  _U_(0x0)   /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    _U_(0x1)   /**< \brief (DMAC_BTCTRL) Block event strobe */
+#define   DMAC_BTCTRL_EVOSEL_BURST_Val    _U_(0x3)   /**< \brief (DMAC_BTCTRL) Burst event strobe */
+#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BURST    (DMAC_BTCTRL_EVOSEL_BURST_Val  << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk    (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  _U_(0x0)   /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define   DMAC_BTCTRL_BLOCKACT_INT_Val    _U_(0x1)   /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2)   /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   _U_(0x3)   /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk    (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   _U_(0x0)   /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  _U_(0x1)   /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   _U_(0x2)   /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC          (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC          (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL         (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
+#define   DMAC_BTCTRL_STEPSEL_DST_Val     _U_(0x0)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define   DMAC_BTCTRL_STEPSEL_SRC_Val     _U_(0x1)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk    (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define   DMAC_BTCTRL_STEPSIZE_X1_Val     _U_(0x0)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
+#define   DMAC_BTCTRL_STEPSIZE_X2_Val     _U_(0x1)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
+#define   DMAC_BTCTRL_STEPSIZE_X4_Val     _U_(0x2)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
+#define   DMAC_BTCTRL_STEPSIZE_X8_Val     _U_(0x3)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
+#define   DMAC_BTCTRL_STEPSIZE_X16_Val    _U_(0x4)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
+#define   DMAC_BTCTRL_STEPSIZE_X32_Val    _U_(0x5)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
+#define   DMAC_BTCTRL_STEPSIZE_X64_Val    _U_(0x6)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
+#define   DMAC_BTCTRL_STEPSIZE_X128_Val   _U_(0x7)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK            _U_(0xFF1F)  /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+#define DMAC_BTCNT_RESETVALUE       _U_(0x0000)  /**< \brief (DMAC_BTCNT reset_value) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk        (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK             _U_(0xFFFF)  /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
+#define DMAC_SRCADDR_RESETVALUE     _U_(0x00000000) /**< \brief (DMAC_SRCADDR reset_value) Block Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk    (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK           _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // CRC mode
+    uint32_t CHKINIT:32;       /*!< bit:  0..31  CRC Checksum Initial Value         */
+  } CRC;                       /*!< Structure used for CRC                          */
+  struct {
+    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
+
+// CRC mode
+#define DMAC_DSTADDR_CRC_CHKINIT_Pos 0            /**< \brief (DMAC_DSTADDR_CRC) CRC Checksum Initial Value */
+#define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
+#define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
+#define DMAC_DSTADDR_CRC_MASK       _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR_CRC) MASK Register */
+
+#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk    (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK           _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk  (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK          _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DmacChannel hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */
+  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x04 (R/W  8) Channel n Control B */
+  __IO DMAC_CHPRILVL_Type        CHPRILVL;    /**< \brief Offset: 0x05 (R/W  8) Channel n Priority Level */
+  __IO DMAC_CHEVCTRL_Type        CHEVCTRL;    /**< \brief Offset: 0x06 (R/W  8) Channel n Event Control */
+       RoReg8                    Reserved1[0x5];
+  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x0C (R/W  8) Channel n Interrupt Enable Clear */
+  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x0D (R/W  8) Channel n Interrupt Enable Set */
+  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x0E (R/W  8) Channel n Interrupt Flag Status and Clear */
+  __IO DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x0F (R/W  8) Channel n Status */
+} DmacChannel;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
+  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
+  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
+       RoReg8                    Reserved1[0x2];
+  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+       RoReg8                    Reserved2[0x8];
+  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+       RoReg8                    Reserved3[0x2];
+  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
+  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
+  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
+  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
+  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+       RoReg8                    Reserved4[0x4];
+       DmacChannel               Channel[32]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+  __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#ifdef __GNUC__
+ #define SECTION_DMAC_DESCRIPTOR      __attribute__ ((section(".hsram")))
+#elif defined(__ICCARM__)
+ #define SECTION_DMAC_DESCRIPTOR      @".hsram"
+#endif
+
+/*@}*/
+
+#endif /* _SAME53_DMAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dsu.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dsu.h
new file mode 100644
index 000000000..02e3c2462
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/dsu.h	
@@ -0,0 +1,647 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_DSU_COMPONENT_
+#define _SAME53_DSU_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAME53_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2410
+#define REV_DSU                     0x100
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Code      */
+    uint8_t  MBIST:1;          /*!< bit:      3  Memory built-in self-test          */
+    uint8_t  CE:1;             /*!< bit:      4  Chip-Erase                         */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  ARR:1;            /*!< bit:      6  Auxiliary Row Read                 */
+    uint8_t  SMSA:1;           /*!< bit:      7  Start Memory Stream Access         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE         _U_(0x00)    /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST              (_U_(0x1) << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
+#define DSU_CTRL_CRC                (_U_(0x1) << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory built-in self-test */
+#define DSU_CTRL_MBIST              (_U_(0x1) << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip-Erase */
+#define DSU_CTRL_CE                 (_U_(0x1) << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_ARR_Pos            6            /**< \brief (DSU_CTRL) Auxiliary Row Read */
+#define DSU_CTRL_ARR                (_U_(0x1) << DSU_CTRL_ARR_Pos)
+#define DSU_CTRL_SMSA_Pos           7            /**< \brief (DSU_CTRL) Start Memory Stream Access */
+#define DSU_CTRL_SMSA               (_U_(0x1) << DSU_CTRL_SMSA_Pos)
+#define DSU_CTRL_MASK               _U_(0xDD)    /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
+    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
+    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
+    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
+    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE      _U_(0x00)    /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE            (_U_(0x1) << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT         (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR            (_U_(0x1) << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL            (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR            (_U_(0x1) << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            _U_(0x1F)    /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
+    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
+    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
+    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
+    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
+    uint8_t  CELCK:1;          /*!< bit:      5  Chip Erase Locked                  */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE      _U_(0x00)    /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT            (_U_(0x1) << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES         (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0           (_U_(1) << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1           (_U_(1) << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk        (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE             (_U_(0x1) << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_CELCK_Pos       5            /**< \brief (DSU_STATUSB) Chip Erase Locked */
+#define DSU_STATUSB_CELCK           (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
+#define DSU_STATUSB_MASK            _U_(0x3F)    /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AMOD:2;           /*!< bit:  0.. 1  Access Mode                        */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_AMOD_Pos           0            /**< \brief (DSU_ADDR) Access Mode */
+#define DSU_ADDR_AMOD_Msk           (_U_(0x3) << DSU_ADDR_AMOD_Pos)
+#define DSU_ADDR_AMOD(value)        (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
+#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk           (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk       (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK             _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk           (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk            (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK                _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
+    uint32_t REVISION:4;       /*!< bit:  8..11  Revision Number                    */
+    uint32_t DIE:4;            /*!< bit: 12..15  Die Number                         */
+    uint32_t SERIES:6;         /*!< bit: 16..21  Series                             */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t FAMILY:5;         /*!< bit: 23..27  Family                             */
+    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk          (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision Number */
+#define DSU_DID_REVISION_Msk        (_U_(0xF) << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Number */
+#define DSU_DID_DIE_Msk             (_U_(0xF) << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Series */
+#define DSU_DID_SERIES_Msk          (_U_(0x3F) << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define   DSU_DID_SERIES_0_Val            _U_(0x0)   /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
+#define   DSU_DID_SERIES_1_Val            _U_(0x1)   /**< \brief (DSU_DID) Cortex-M0+ processor, USB */
+#define DSU_DID_SERIES_0            (DSU_DID_SERIES_0_Val          << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES_1            (DSU_DID_SERIES_1_Val          << DSU_DID_SERIES_Pos)
+#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Family */
+#define DSU_DID_FAMILY_Msk          (_U_(0x1F) << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define   DSU_DID_FAMILY_0_Val            _U_(0x0)   /**< \brief (DSU_DID) General purpose microcontroller */
+#define   DSU_DID_FAMILY_1_Val            _U_(0x1)   /**< \brief (DSU_DID) PicoPower */
+#define DSU_DID_FAMILY_0            (DSU_DID_FAMILY_0_Val          << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY_1            (DSU_DID_FAMILY_1_Val          << DSU_DID_FAMILY_Pos)
+#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk       (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define   DSU_DID_PROCESSOR_CM0P_Val      _U_(0x1)   /**< \brief (DSU_DID) Cortex-M0+ */
+#define   DSU_DID_PROCESSOR_CM23_Val      _U_(0x2)   /**< \brief (DSU_DID) Cortex-M23 */
+#define   DSU_DID_PROCESSOR_CM3_Val       _U_(0x3)   /**< \brief (DSU_DID) Cortex-M3 */
+#define   DSU_DID_PROCESSOR_CM4_Val       _U_(0x5)   /**< \brief (DSU_DID) Cortex-M4 */
+#define   DSU_DID_PROCESSOR_CM4F_Val      _U_(0x6)   /**< \brief (DSU_DID) Cortex-M4 with FPU */
+#define   DSU_DID_PROCESSOR_CM33_Val      _U_(0x7)   /**< \brief (DSU_DID) Cortex-M33 */
+#define DSU_DID_PROCESSOR_CM0P      (DSU_DID_PROCESSOR_CM0P_Val    << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM23      (DSU_DID_PROCESSOR_CM23_Val    << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM3       (DSU_DID_PROCESSOR_CM3_Val     << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM4       (DSU_DID_PROCESSOR_CM4_Val     << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM4F      (DSU_DID_PROCESSOR_CM4F_Val    << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_CM33      (DSU_DID_PROCESSOR_CM33_Val    << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_MASK                _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LQOS:2;           /*!< bit:  0.. 1  Latency Quality Of Service         */
+    uint32_t DCCDMALEVEL:2;    /*!< bit:  2.. 3  DMA Trigger Level                  */
+    uint32_t ETBRAMEN:1;       /*!< bit:      4  Trace Control                      */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CFG_OFFSET              0x001C       /**< \brief (DSU_CFG offset) Configuration */
+#define DSU_CFG_RESETVALUE          _U_(0x00000002) /**< \brief (DSU_CFG reset_value) Configuration */
+
+#define DSU_CFG_LQOS_Pos            0            /**< \brief (DSU_CFG) Latency Quality Of Service */
+#define DSU_CFG_LQOS_Msk            (_U_(0x3) << DSU_CFG_LQOS_Pos)
+#define DSU_CFG_LQOS(value)         (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))
+#define DSU_CFG_DCCDMALEVEL_Pos     2            /**< \brief (DSU_CFG) DMA Trigger Level */
+#define DSU_CFG_DCCDMALEVEL_Msk     (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos)
+#define DSU_CFG_DCCDMALEVEL(value)  (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))
+#define   DSU_CFG_DCCDMALEVEL_EMPTY_Val   _U_(0x0)   /**< \brief (DSU_CFG) Trigger rises when DCC is empty */
+#define   DSU_CFG_DCCDMALEVEL_FULL_Val    _U_(0x1)   /**< \brief (DSU_CFG) Trigger rises when DCC is full */
+#define DSU_CFG_DCCDMALEVEL_EMPTY   (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos)
+#define DSU_CFG_DCCDMALEVEL_FULL    (DSU_CFG_DCCDMALEVEL_FULL_Val  << DSU_CFG_DCCDMALEVEL_Pos)
+#define DSU_CFG_ETBRAMEN_Pos        4            /**< \brief (DSU_CFG) Trace Control */
+#define DSU_CFG_ETBRAMEN            (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
+#define DSU_CFG_MASK                _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */
+
+/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/  32) CoreSight ROM Table Entry 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
+    uint32_t FMT:1;            /*!< bit:      1  Format                             */
+    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
+    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY0_OFFSET           0x1000       /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */
+#define DSU_ENTRY0_RESETVALUE       _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */
+
+#define DSU_ENTRY0_EPRES_Pos        0            /**< \brief (DSU_ENTRY0) Entry Present */
+#define DSU_ENTRY0_EPRES            (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
+#define DSU_ENTRY0_FMT_Pos          1            /**< \brief (DSU_ENTRY0) Format */
+#define DSU_ENTRY0_FMT              (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
+#define DSU_ENTRY0_ADDOFF_Pos       12           /**< \brief (DSU_ENTRY0) Address Offset */
+#define DSU_ENTRY0_ADDOFF_Msk       (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
+#define DSU_ENTRY0_ADDOFF(value)    (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
+#define DSU_ENTRY0_MASK             _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */
+
+/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/  32) CoreSight ROM Table Entry 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY1_OFFSET           0x1004       /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */
+#define DSU_ENTRY1_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */
+#define DSU_ENTRY1_MASK             _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) CoreSight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) CoreSight ROM Table End */
+#define DSU_END_RESETVALUE          _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */
+
+#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk             (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
+#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK                _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) CoreSight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP           (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
+    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB count                          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk          (_U_(0xF) << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB count */
+#define DSU_PID4_FKBC_Msk           (_U_(0xF) << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK               _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/  32) Peripheral Identification 5 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID5_OFFSET             0x1FD4       /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
+#define DSU_PID5_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */
+#define DSU_PID5_MASK               _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */
+
+/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/  32) Peripheral Identification 6 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID6_OFFSET             0x1FD8       /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
+#define DSU_PID6_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */
+#define DSU_PID6_MASK               _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */
+
+/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/  32) Peripheral Identification 7 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID7_OFFSET             0x1FDC       /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
+#define DSU_PID7_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */
+#define DSU_PID7_MASK               _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk        (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK               _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
+    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk        (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk        (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK               _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
+    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
+    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk        (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU               (_U_(0x1) << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk       (_U_(0xF) << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK               _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
+    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk         (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk         (_U_(0xF) << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK               _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk     (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK               _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
+    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk       (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk         (_U_(0xF) << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK               _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk     (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK               _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk     (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK               _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
+  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
+  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
+       RoReg8                    Reserved1[0x1];
+  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
+  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
+  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
+  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
+  __IO DSU_CFG_Type              CFG;         /**< \brief Offset: 0x001C (R/W 32) Configuration */
+       RoReg8                    Reserved2[0xFE0];
+  __I  DSU_ENTRY0_Type           ENTRY0;      /**< \brief Offset: 0x1000 (R/  32) CoreSight ROM Table Entry 0 */
+  __I  DSU_ENTRY1_Type           ENTRY1;      /**< \brief Offset: 0x1004 (R/  32) CoreSight ROM Table Entry 1 */
+  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) CoreSight ROM Table End */
+       RoReg8                    Reserved3[0xFC0];
+  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) CoreSight ROM Table Memory Type */
+  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
+  __I  DSU_PID5_Type             PID5;        /**< \brief Offset: 0x1FD4 (R/  32) Peripheral Identification 5 */
+  __I  DSU_PID6_Type             PID6;        /**< \brief Offset: 0x1FD8 (R/  32) Peripheral Identification 6 */
+  __I  DSU_PID7_Type             PID7;        /**< \brief Offset: 0x1FDC (R/  32) Peripheral Identification 7 */
+  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
+  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
+  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
+  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
+  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
+  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
+  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
+  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_DSU_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/eic.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/eic.h
new file mode 100644
index 000000000..3e66e4671
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/eic.h	
@@ -0,0 +1,497 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_EIC_COMPONENT_
+#define _SAME53_EIC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAME53_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2254
+#define REV_EIC                     0x300
+
+/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CKSEL:1;          /*!< bit:      4  Clock Selection                    */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRLA_OFFSET            0x00         /**< \brief (EIC_CTRLA offset) Control A */
+#define EIC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (EIC_CTRLA reset_value) Control A */
+
+#define EIC_CTRLA_SWRST_Pos         0            /**< \brief (EIC_CTRLA) Software Reset */
+#define EIC_CTRLA_SWRST             (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
+#define EIC_CTRLA_ENABLE_Pos        1            /**< \brief (EIC_CTRLA) Enable */
+#define EIC_CTRLA_ENABLE            (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
+#define EIC_CTRLA_CKSEL_Pos         4            /**< \brief (EIC_CTRLA) Clock Selection */
+#define EIC_CTRLA_CKSEL             (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
+#define EIC_CTRLA_MASK              _U_(0x13)    /**< \brief (EIC_CTRLA) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W  8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense Configuration */
+    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
+    uint8_t  NMIASYNCH:1;      /*!< bit:      4  Asynchronous Edge Detection Mode   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET          0x01         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE      _U_(0x00)    /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
+#define EIC_NMICTRL_NMISENSE_Msk    (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   _U_(0x0)   /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   _U_(0x1)   /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   _U_(0x2)   /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   _U_(0x3)   /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   _U_(0x4)   /**< \brief (EIC_NMICTRL) High-level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    _U_(0x5)   /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN       (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_NMIASYNCH_Pos   4            /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
+#define EIC_NMICTRL_NMIASYNCH       (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
+#define EIC_NMICTRL_MASK            _U_(0x1F)    /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
+    uint16_t :15;              /*!< bit:  1..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET          0x02         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE      _U_(0x0000)  /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI             (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            _U_(0x0001)  /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy Status */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy Status */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_SYNCBUSY_OFFSET         0x04         /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
+#define EIC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define EIC_SYNCBUSY_SWRST_Pos      0            /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
+#define EIC_SYNCBUSY_SWRST          (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
+#define EIC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
+#define EIC_SYNCBUSY_ENABLE         (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
+#define EIC_SYNCBUSY_MASK           _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET           0x08         /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk     (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK             _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Enable          */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET         0x0C         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt Enable */
+#define EIC_INTENCLR_EXTINT_Msk     (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK           _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Enable          */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET         0x10         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt Enable */
+#define EIC_INTENSET_EXTINT_Msk     (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK           _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt                 */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET          0x14         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt */
+#define EIC_INTFLAG_EXTINT_Msk      (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK            _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ASYNCH:16;        /*!< bit:  0..15  Asynchronous Edge Detection Mode   */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_ASYNCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_ASYNCH_OFFSET           0x18         /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
+#define EIC_ASYNCH_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
+
+#define EIC_ASYNCH_ASYNCH_Pos       0            /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
+#define EIC_ASYNCH_ASYNCH_Msk       (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
+#define EIC_ASYNCH_ASYNCH(value)    (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
+#define EIC_ASYNCH_MASK             _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense Configuration 0        */
+    uint32_t FILTEN0:1;        /*!< bit:      3  Filter Enable 0                    */
+    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense Configuration 1        */
+    uint32_t FILTEN1:1;        /*!< bit:      7  Filter Enable 1                    */
+    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense Configuration 2        */
+    uint32_t FILTEN2:1;        /*!< bit:     11  Filter Enable 2                    */
+    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense Configuration 3        */
+    uint32_t FILTEN3:1;        /*!< bit:     15  Filter Enable 3                    */
+    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense Configuration 4        */
+    uint32_t FILTEN4:1;        /*!< bit:     19  Filter Enable 4                    */
+    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense Configuration 5        */
+    uint32_t FILTEN5:1;        /*!< bit:     23  Filter Enable 5                    */
+    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense Configuration 6        */
+    uint32_t FILTEN6:1;        /*!< bit:     27  Filter Enable 6                    */
+    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense Configuration 7        */
+    uint32_t FILTEN7:1;        /*!< bit:     31  Filter Enable 7                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET           0x1C         /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
+#define EIC_CONFIG_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
+
+#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
+#define EIC_CONFIG_SENSE0_Msk       (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define   EIC_CONFIG_SENSE0_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter Enable 0 */
+#define EIC_CONFIG_FILTEN0          (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
+#define EIC_CONFIG_SENSE1_Msk       (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define   EIC_CONFIG_SENSE1_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter Enable 1 */
+#define EIC_CONFIG_FILTEN1          (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
+#define EIC_CONFIG_SENSE2_Msk       (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define   EIC_CONFIG_SENSE2_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter Enable 2 */
+#define EIC_CONFIG_FILTEN2          (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
+#define EIC_CONFIG_SENSE3_Msk       (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define   EIC_CONFIG_SENSE3_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter Enable 3 */
+#define EIC_CONFIG_FILTEN3          (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
+#define EIC_CONFIG_SENSE4_Msk       (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define   EIC_CONFIG_SENSE4_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter Enable 4 */
+#define EIC_CONFIG_FILTEN4          (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
+#define EIC_CONFIG_SENSE5_Msk       (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define   EIC_CONFIG_SENSE5_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter Enable 5 */
+#define EIC_CONFIG_FILTEN5          (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
+#define EIC_CONFIG_SENSE6_Msk       (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define   EIC_CONFIG_SENSE6_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter Enable 6 */
+#define EIC_CONFIG_FILTEN6          (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
+#define EIC_CONFIG_SENSE7_Msk       (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define   EIC_CONFIG_SENSE7_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter Enable 7 */
+#define EIC_CONFIG_FILTEN7          (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
+
+/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEBOUNCEN:16;     /*!< bit:  0..15  Debouncer Enable                   */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_DEBOUNCEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_DEBOUNCEN_OFFSET        0x30         /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
+#define EIC_DEBOUNCEN_RESETVALUE    _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
+
+#define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0            /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
+#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
+#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
+#define EIC_DEBOUNCEN_MASK          _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
+
+/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PRESCALER0:3;     /*!< bit:  0.. 2  Debouncer Prescaler                */
+    uint32_t STATES0:1;        /*!< bit:      3  Debouncer number of states         */
+    uint32_t PRESCALER1:3;     /*!< bit:  4.. 6  Debouncer Prescaler                */
+    uint32_t STATES1:1;        /*!< bit:      7  Debouncer number of states         */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t TICKON:1;         /*!< bit:     16  Pin Sampler frequency selection    */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_DPRESCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_DPRESCALER_OFFSET       0x34         /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
+#define EIC_DPRESCALER_RESETVALUE   _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
+
+#define EIC_DPRESCALER_PRESCALER0_Pos 0            /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
+#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
+#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
+#define EIC_DPRESCALER_STATES0_Pos  3            /**< \brief (EIC_DPRESCALER) Debouncer number of states */
+#define EIC_DPRESCALER_STATES0      (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
+#define EIC_DPRESCALER_PRESCALER1_Pos 4            /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
+#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
+#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
+#define EIC_DPRESCALER_STATES1_Pos  7            /**< \brief (EIC_DPRESCALER) Debouncer number of states */
+#define EIC_DPRESCALER_STATES1      (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
+#define EIC_DPRESCALER_TICKON_Pos   16           /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
+#define EIC_DPRESCALER_TICKON       (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
+#define EIC_DPRESCALER_MASK         _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
+
+/* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/  32) Pin State -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINSTATE:16;      /*!< bit:  0..15  Pin State                          */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_PINSTATE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_PINSTATE_OFFSET         0x38         /**< \brief (EIC_PINSTATE offset) Pin State */
+#define EIC_PINSTATE_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
+
+#define EIC_PINSTATE_PINSTATE_Pos   0            /**< \brief (EIC_PINSTATE) Pin State */
+#define EIC_PINSTATE_PINSTATE_Msk   (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
+#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
+#define EIC_PINSTATE_MASK           _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EIC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x01 (R/W  8) Non-Maskable Interrupt Control */
+  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
+  __I  EIC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x04 (R/  32) Synchronization Busy */
+  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x08 (R/W 32) Event Control */
+  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
+  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
+  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
+  __IO EIC_ASYNCH_Type           ASYNCH;      /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
+  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
+       RoReg8                    Reserved1[0xC];
+  __IO EIC_DEBOUNCEN_Type        DEBOUNCEN;   /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
+  __IO EIC_DPRESCALER_Type       DPRESCALER;  /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
+  __I  EIC_PINSTATE_Type         PINSTATE;    /**< \brief Offset: 0x38 (R/  32) Pin State */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_EIC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/evsys.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/evsys.h
new file mode 100644
index 000000000..82b3f4472
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/evsys.h	
@@ -0,0 +1,587 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_EVSYS_COMPONENT_
+#define _SAME53_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAME53_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2504
+#define REV_EVSYS                   0x100
+
+/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRLA_OFFSET          0x000        /**< \brief (EVSYS_CTRLA offset) Control */
+#define EVSYS_CTRLA_RESETVALUE      _U_(0x00)    /**< \brief (EVSYS_CTRLA reset_value) Control */
+
+#define EVSYS_CTRLA_SWRST_Pos       0            /**< \brief (EVSYS_CTRLA) Software Reset */
+#define EVSYS_CTRLA_SWRST           (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
+#define EVSYS_CTRLA_MASK            _U_(0x01)    /**< \brief (EVSYS_CTRLA) MASK Register */
+
+/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL0:1;       /*!< bit:      0  Channel 0 Software Selection       */
+    uint32_t CHANNEL1:1;       /*!< bit:      1  Channel 1 Software Selection       */
+    uint32_t CHANNEL2:1;       /*!< bit:      2  Channel 2 Software Selection       */
+    uint32_t CHANNEL3:1;       /*!< bit:      3  Channel 3 Software Selection       */
+    uint32_t CHANNEL4:1;       /*!< bit:      4  Channel 4 Software Selection       */
+    uint32_t CHANNEL5:1;       /*!< bit:      5  Channel 5 Software Selection       */
+    uint32_t CHANNEL6:1;       /*!< bit:      6  Channel 6 Software Selection       */
+    uint32_t CHANNEL7:1;       /*!< bit:      7  Channel 7 Software Selection       */
+    uint32_t CHANNEL8:1;       /*!< bit:      8  Channel 8 Software Selection       */
+    uint32_t CHANNEL9:1;       /*!< bit:      9  Channel 9 Software Selection       */
+    uint32_t CHANNEL10:1;      /*!< bit:     10  Channel 10 Software Selection      */
+    uint32_t CHANNEL11:1;      /*!< bit:     11  Channel 11 Software Selection      */
+    uint32_t CHANNEL12:1;      /*!< bit:     12  Channel 12 Software Selection      */
+    uint32_t CHANNEL13:1;      /*!< bit:     13  Channel 13 Software Selection      */
+    uint32_t CHANNEL14:1;      /*!< bit:     14  Channel 14 Software Selection      */
+    uint32_t CHANNEL15:1;      /*!< bit:     15  Channel 15 Software Selection      */
+    uint32_t CHANNEL16:1;      /*!< bit:     16  Channel 16 Software Selection      */
+    uint32_t CHANNEL17:1;      /*!< bit:     17  Channel 17 Software Selection      */
+    uint32_t CHANNEL18:1;      /*!< bit:     18  Channel 18 Software Selection      */
+    uint32_t CHANNEL19:1;      /*!< bit:     19  Channel 19 Software Selection      */
+    uint32_t CHANNEL20:1;      /*!< bit:     20  Channel 20 Software Selection      */
+    uint32_t CHANNEL21:1;      /*!< bit:     21  Channel 21 Software Selection      */
+    uint32_t CHANNEL22:1;      /*!< bit:     22  Channel 22 Software Selection      */
+    uint32_t CHANNEL23:1;      /*!< bit:     23  Channel 23 Software Selection      */
+    uint32_t CHANNEL24:1;      /*!< bit:     24  Channel 24 Software Selection      */
+    uint32_t CHANNEL25:1;      /*!< bit:     25  Channel 25 Software Selection      */
+    uint32_t CHANNEL26:1;      /*!< bit:     26  Channel 26 Software Selection      */
+    uint32_t CHANNEL27:1;      /*!< bit:     27  Channel 27 Software Selection      */
+    uint32_t CHANNEL28:1;      /*!< bit:     28  Channel 28 Software Selection      */
+    uint32_t CHANNEL29:1;      /*!< bit:     29  Channel 29 Software Selection      */
+    uint32_t CHANNEL30:1;      /*!< bit:     30  Channel 30 Software Selection      */
+    uint32_t CHANNEL31:1;      /*!< bit:     31  Channel 31 Software Selection      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHANNEL:32;       /*!< bit:  0..31  Channel x Software Selection       */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_SWEVT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_SWEVT_OFFSET          0x004        /**< \brief (EVSYS_SWEVT offset) Software Event */
+#define EVSYS_SWEVT_RESETVALUE      _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
+
+#define EVSYS_SWEVT_CHANNEL0_Pos    0            /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
+#define EVSYS_SWEVT_CHANNEL0        (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
+#define EVSYS_SWEVT_CHANNEL1_Pos    1            /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
+#define EVSYS_SWEVT_CHANNEL1        (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
+#define EVSYS_SWEVT_CHANNEL2_Pos    2            /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
+#define EVSYS_SWEVT_CHANNEL2        (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
+#define EVSYS_SWEVT_CHANNEL3_Pos    3            /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
+#define EVSYS_SWEVT_CHANNEL3        (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
+#define EVSYS_SWEVT_CHANNEL4_Pos    4            /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
+#define EVSYS_SWEVT_CHANNEL4        (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
+#define EVSYS_SWEVT_CHANNEL5_Pos    5            /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
+#define EVSYS_SWEVT_CHANNEL5        (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
+#define EVSYS_SWEVT_CHANNEL6_Pos    6            /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
+#define EVSYS_SWEVT_CHANNEL6        (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
+#define EVSYS_SWEVT_CHANNEL7_Pos    7            /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
+#define EVSYS_SWEVT_CHANNEL7        (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
+#define EVSYS_SWEVT_CHANNEL8_Pos    8            /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
+#define EVSYS_SWEVT_CHANNEL8        (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
+#define EVSYS_SWEVT_CHANNEL9_Pos    9            /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
+#define EVSYS_SWEVT_CHANNEL9        (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
+#define EVSYS_SWEVT_CHANNEL10_Pos   10           /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
+#define EVSYS_SWEVT_CHANNEL10       (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
+#define EVSYS_SWEVT_CHANNEL11_Pos   11           /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
+#define EVSYS_SWEVT_CHANNEL11       (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
+#define EVSYS_SWEVT_CHANNEL12_Pos   12           /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
+#define EVSYS_SWEVT_CHANNEL12       (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
+#define EVSYS_SWEVT_CHANNEL13_Pos   13           /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
+#define EVSYS_SWEVT_CHANNEL13       (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
+#define EVSYS_SWEVT_CHANNEL14_Pos   14           /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
+#define EVSYS_SWEVT_CHANNEL14       (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
+#define EVSYS_SWEVT_CHANNEL15_Pos   15           /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
+#define EVSYS_SWEVT_CHANNEL15       (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
+#define EVSYS_SWEVT_CHANNEL16_Pos   16           /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
+#define EVSYS_SWEVT_CHANNEL16       (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
+#define EVSYS_SWEVT_CHANNEL17_Pos   17           /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
+#define EVSYS_SWEVT_CHANNEL17       (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
+#define EVSYS_SWEVT_CHANNEL18_Pos   18           /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
+#define EVSYS_SWEVT_CHANNEL18       (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
+#define EVSYS_SWEVT_CHANNEL19_Pos   19           /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
+#define EVSYS_SWEVT_CHANNEL19       (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
+#define EVSYS_SWEVT_CHANNEL20_Pos   20           /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
+#define EVSYS_SWEVT_CHANNEL20       (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
+#define EVSYS_SWEVT_CHANNEL21_Pos   21           /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
+#define EVSYS_SWEVT_CHANNEL21       (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
+#define EVSYS_SWEVT_CHANNEL22_Pos   22           /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
+#define EVSYS_SWEVT_CHANNEL22       (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
+#define EVSYS_SWEVT_CHANNEL23_Pos   23           /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
+#define EVSYS_SWEVT_CHANNEL23       (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
+#define EVSYS_SWEVT_CHANNEL24_Pos   24           /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
+#define EVSYS_SWEVT_CHANNEL24       (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
+#define EVSYS_SWEVT_CHANNEL25_Pos   25           /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
+#define EVSYS_SWEVT_CHANNEL25       (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
+#define EVSYS_SWEVT_CHANNEL26_Pos   26           /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
+#define EVSYS_SWEVT_CHANNEL26       (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
+#define EVSYS_SWEVT_CHANNEL27_Pos   27           /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
+#define EVSYS_SWEVT_CHANNEL27       (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
+#define EVSYS_SWEVT_CHANNEL28_Pos   28           /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
+#define EVSYS_SWEVT_CHANNEL28       (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
+#define EVSYS_SWEVT_CHANNEL29_Pos   29           /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
+#define EVSYS_SWEVT_CHANNEL29       (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
+#define EVSYS_SWEVT_CHANNEL30_Pos   30           /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
+#define EVSYS_SWEVT_CHANNEL30       (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
+#define EVSYS_SWEVT_CHANNEL31_Pos   31           /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
+#define EVSYS_SWEVT_CHANNEL31       (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
+#define EVSYS_SWEVT_CHANNEL_Pos     0            /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
+#define EVSYS_SWEVT_CHANNEL_Msk     (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
+#define EVSYS_SWEVT_CHANNEL(value)  (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
+#define EVSYS_SWEVT_MASK            _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
+
+/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W  8) Priority Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PRI:4;            /*!< bit:  0.. 3  Channel Priority Number            */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  RREN:1;           /*!< bit:      7  Round-Robin Scheduling Enable      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_PRICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_PRICTRL_OFFSET        0x008        /**< \brief (EVSYS_PRICTRL offset) Priority Control */
+#define EVSYS_PRICTRL_RESETVALUE    _U_(0x00)    /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
+
+#define EVSYS_PRICTRL_PRI_Pos       0            /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
+#define EVSYS_PRICTRL_PRI_Msk       (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
+#define EVSYS_PRICTRL_PRI(value)    (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
+#define EVSYS_PRICTRL_RREN_Pos      7            /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
+#define EVSYS_PRICTRL_RREN          (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
+#define EVSYS_PRICTRL_MASK          _U_(0x8F)    /**< \brief (EVSYS_PRICTRL) MASK Register */
+
+/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ID:4;             /*!< bit:  0.. 3  Channel ID                         */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t OVR:1;            /*!< bit:      8  Channel Overrun                    */
+    uint16_t EVD:1;            /*!< bit:      9  Channel Event Detected             */
+    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint16_t READY:1;          /*!< bit:     14  Ready                              */
+    uint16_t BUSY:1;           /*!< bit:     15  Busy                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTPEND_OFFSET        0x010        /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
+#define EVSYS_INTPEND_RESETVALUE    _U_(0x4000)  /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
+
+#define EVSYS_INTPEND_ID_Pos        0            /**< \brief (EVSYS_INTPEND) Channel ID */
+#define EVSYS_INTPEND_ID_Msk        (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
+#define EVSYS_INTPEND_ID(value)     (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
+#define EVSYS_INTPEND_OVR_Pos       8            /**< \brief (EVSYS_INTPEND) Channel Overrun */
+#define EVSYS_INTPEND_OVR           (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
+#define EVSYS_INTPEND_EVD_Pos       9            /**< \brief (EVSYS_INTPEND) Channel Event Detected */
+#define EVSYS_INTPEND_EVD           (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
+#define EVSYS_INTPEND_READY_Pos     14           /**< \brief (EVSYS_INTPEND) Ready */
+#define EVSYS_INTPEND_READY         (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
+#define EVSYS_INTPEND_BUSY_Pos      15           /**< \brief (EVSYS_INTPEND) Busy */
+#define EVSYS_INTPEND_BUSY          (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
+#define EVSYS_INTPEND_MASK          _U_(0xC30F)  /**< \brief (EVSYS_INTPEND) MASK Register */
+
+/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/  32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
+    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
+    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
+    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
+    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
+    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
+    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
+    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
+    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
+    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
+    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
+    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHINT:12;         /*!< bit:  0..11  Channel x Pending Interrupt        */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTSTATUS_OFFSET      0x014        /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
+#define EVSYS_INTSTATUS_RESETVALUE  _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
+
+#define EVSYS_INTSTATUS_CHINT0_Pos  0            /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT0      (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
+#define EVSYS_INTSTATUS_CHINT1_Pos  1            /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT1      (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
+#define EVSYS_INTSTATUS_CHINT2_Pos  2            /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT2      (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
+#define EVSYS_INTSTATUS_CHINT3_Pos  3            /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT3      (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
+#define EVSYS_INTSTATUS_CHINT4_Pos  4            /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT4      (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
+#define EVSYS_INTSTATUS_CHINT5_Pos  5            /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT5      (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
+#define EVSYS_INTSTATUS_CHINT6_Pos  6            /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT6      (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
+#define EVSYS_INTSTATUS_CHINT7_Pos  7            /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT7      (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
+#define EVSYS_INTSTATUS_CHINT8_Pos  8            /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT8      (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
+#define EVSYS_INTSTATUS_CHINT9_Pos  9            /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT9      (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
+#define EVSYS_INTSTATUS_CHINT10_Pos 10           /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT10     (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
+#define EVSYS_INTSTATUS_CHINT11_Pos 11           /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT11     (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
+#define EVSYS_INTSTATUS_CHINT_Pos   0            /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
+#define EVSYS_INTSTATUS_CHINT_Msk   (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
+#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
+#define EVSYS_INTSTATUS_MASK        _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
+
+/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/  32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
+    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
+    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
+    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
+    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
+    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
+    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
+    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
+    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
+    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
+    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
+    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t BUSYCH:12;        /*!< bit:  0..11  Busy Channel x                     */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_BUSYCH_OFFSET         0x018        /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
+#define EVSYS_BUSYCH_RESETVALUE     _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
+
+#define EVSYS_BUSYCH_BUSYCH0_Pos    0            /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
+#define EVSYS_BUSYCH_BUSYCH0        (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
+#define EVSYS_BUSYCH_BUSYCH1_Pos    1            /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
+#define EVSYS_BUSYCH_BUSYCH1        (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
+#define EVSYS_BUSYCH_BUSYCH2_Pos    2            /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
+#define EVSYS_BUSYCH_BUSYCH2        (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
+#define EVSYS_BUSYCH_BUSYCH3_Pos    3            /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
+#define EVSYS_BUSYCH_BUSYCH3        (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
+#define EVSYS_BUSYCH_BUSYCH4_Pos    4            /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
+#define EVSYS_BUSYCH_BUSYCH4        (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
+#define EVSYS_BUSYCH_BUSYCH5_Pos    5            /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
+#define EVSYS_BUSYCH_BUSYCH5        (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
+#define EVSYS_BUSYCH_BUSYCH6_Pos    6            /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
+#define EVSYS_BUSYCH_BUSYCH6        (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
+#define EVSYS_BUSYCH_BUSYCH7_Pos    7            /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
+#define EVSYS_BUSYCH_BUSYCH7        (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
+#define EVSYS_BUSYCH_BUSYCH8_Pos    8            /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
+#define EVSYS_BUSYCH_BUSYCH8        (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
+#define EVSYS_BUSYCH_BUSYCH9_Pos    9            /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
+#define EVSYS_BUSYCH_BUSYCH9        (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
+#define EVSYS_BUSYCH_BUSYCH10_Pos   10           /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
+#define EVSYS_BUSYCH_BUSYCH10       (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
+#define EVSYS_BUSYCH_BUSYCH11_Pos   11           /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
+#define EVSYS_BUSYCH_BUSYCH11       (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
+#define EVSYS_BUSYCH_BUSYCH_Pos     0            /**< \brief (EVSYS_BUSYCH) Busy Channel x */
+#define EVSYS_BUSYCH_BUSYCH_Msk     (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
+#define EVSYS_BUSYCH_BUSYCH(value)  (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
+#define EVSYS_BUSYCH_MASK           _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
+
+/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/  32) Ready Users -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t READYUSR0:1;      /*!< bit:      0  Ready User for Channel 0           */
+    uint32_t READYUSR1:1;      /*!< bit:      1  Ready User for Channel 1           */
+    uint32_t READYUSR2:1;      /*!< bit:      2  Ready User for Channel 2           */
+    uint32_t READYUSR3:1;      /*!< bit:      3  Ready User for Channel 3           */
+    uint32_t READYUSR4:1;      /*!< bit:      4  Ready User for Channel 4           */
+    uint32_t READYUSR5:1;      /*!< bit:      5  Ready User for Channel 5           */
+    uint32_t READYUSR6:1;      /*!< bit:      6  Ready User for Channel 6           */
+    uint32_t READYUSR7:1;      /*!< bit:      7  Ready User for Channel 7           */
+    uint32_t READYUSR8:1;      /*!< bit:      8  Ready User for Channel 8           */
+    uint32_t READYUSR9:1;      /*!< bit:      9  Ready User for Channel 9           */
+    uint32_t READYUSR10:1;     /*!< bit:     10  Ready User for Channel 10          */
+    uint32_t READYUSR11:1;     /*!< bit:     11  Ready User for Channel 11          */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t READYUSR:12;      /*!< bit:  0..11  Ready User for Channel x           */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_READYUSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_READYUSR_OFFSET       0x01C        /**< \brief (EVSYS_READYUSR offset) Ready Users */
+#define EVSYS_READYUSR_RESETVALUE   _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
+
+#define EVSYS_READYUSR_READYUSR0_Pos 0            /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
+#define EVSYS_READYUSR_READYUSR0    (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
+#define EVSYS_READYUSR_READYUSR1_Pos 1            /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
+#define EVSYS_READYUSR_READYUSR1    (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
+#define EVSYS_READYUSR_READYUSR2_Pos 2            /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
+#define EVSYS_READYUSR_READYUSR2    (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
+#define EVSYS_READYUSR_READYUSR3_Pos 3            /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
+#define EVSYS_READYUSR_READYUSR3    (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
+#define EVSYS_READYUSR_READYUSR4_Pos 4            /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
+#define EVSYS_READYUSR_READYUSR4    (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
+#define EVSYS_READYUSR_READYUSR5_Pos 5            /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
+#define EVSYS_READYUSR_READYUSR5    (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
+#define EVSYS_READYUSR_READYUSR6_Pos 6            /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
+#define EVSYS_READYUSR_READYUSR6    (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
+#define EVSYS_READYUSR_READYUSR7_Pos 7            /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
+#define EVSYS_READYUSR_READYUSR7    (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
+#define EVSYS_READYUSR_READYUSR8_Pos 8            /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
+#define EVSYS_READYUSR_READYUSR8    (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
+#define EVSYS_READYUSR_READYUSR9_Pos 9            /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
+#define EVSYS_READYUSR_READYUSR9    (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
+#define EVSYS_READYUSR_READYUSR10_Pos 10           /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
+#define EVSYS_READYUSR_READYUSR10   (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
+#define EVSYS_READYUSR_READYUSR11_Pos 11           /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
+#define EVSYS_READYUSR_READYUSR11   (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
+#define EVSYS_READYUSR_READYUSR_Pos 0            /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
+#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
+#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
+#define EVSYS_READYUSR_MASK         _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVGEN:7;          /*!< bit:  0.. 6  Event Generator Selection          */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PATH:2;           /*!< bit:  8.. 9  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 10..11  Edge Detection Selection           */
+    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:     14  Run in standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:     15  Generic Clock On Demand            */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x020        /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
+#define EVSYS_CHANNEL_RESETVALUE    _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
+
+#define EVSYS_CHANNEL_EVGEN_Pos     0            /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos      8            /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0)   /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1)   /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2)   /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    10           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0)   /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1)   /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2)   /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3)   /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_RUNSTDBY_Pos  14           /**< \brief (EVSYS_CHANNEL) Run in standby */
+#define EVSYS_CHANNEL_RUNSTDBY      (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
+#define EVSYS_CHANNEL_ONDEMAND_Pos  15           /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
+#define EVSYS_CHANNEL_ONDEMAND      (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
+#define EVSYS_CHANNEL_MASK          _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W  8) CHANNEL Channel n Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVR:1;            /*!< bit:      0  Channel Overrun Interrupt Disable  */
+    uint8_t  EVD:1;            /*!< bit:      1  Channel Event Detected Interrupt Disable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTENCLR_OFFSET     0x024        /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
+#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00)    /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
+
+#define EVSYS_CHINTENCLR_OVR_Pos    0            /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
+#define EVSYS_CHINTENCLR_OVR        (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
+#define EVSYS_CHINTENCLR_EVD_Pos    1            /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
+#define EVSYS_CHINTENCLR_EVD        (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
+#define EVSYS_CHINTENCLR_MASK       _U_(0x03)    /**< \brief (EVSYS_CHINTENCLR) MASK Register */
+
+/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W  8) CHANNEL Channel n Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVR:1;            /*!< bit:      0  Channel Overrun Interrupt Enable   */
+    uint8_t  EVD:1;            /*!< bit:      1  Channel Event Detected Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTENSET_OFFSET     0x025        /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
+#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00)    /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
+
+#define EVSYS_CHINTENSET_OVR_Pos    0            /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
+#define EVSYS_CHINTENSET_OVR        (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
+#define EVSYS_CHINTENSET_EVD_Pos    1            /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
+#define EVSYS_CHINTENSET_EVD        (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
+#define EVSYS_CHINTENSET_MASK       _U_(0x03)    /**< \brief (EVSYS_CHINTENSET) MASK Register */
+
+/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W  8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  OVR:1;            /*!< bit:      0  Channel Overrun                    */
+    __I uint8_t  EVD:1;            /*!< bit:      1  Channel Event Detected             */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHINTFLAG_OFFSET      0x026        /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
+#define EVSYS_CHINTFLAG_RESETVALUE  _U_(0x00)    /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
+
+#define EVSYS_CHINTFLAG_OVR_Pos     0            /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
+#define EVSYS_CHINTFLAG_OVR         (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
+#define EVSYS_CHINTFLAG_EVD_Pos     1            /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
+#define EVSYS_CHINTFLAG_EVD         (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
+#define EVSYS_CHINTFLAG_MASK        _U_(0x03)    /**< \brief (EVSYS_CHINTFLAG) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/   8) CHANNEL Channel n Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RDYUSR:1;         /*!< bit:      0  Ready User                         */
+    uint8_t  BUSYCH:1;         /*!< bit:      1  Busy Channel                       */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x027        /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
+#define EVSYS_CHSTATUS_RESETVALUE   _U_(0x01)    /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
+
+#define EVSYS_CHSTATUS_RDYUSR_Pos   0            /**< \brief (EVSYS_CHSTATUS) Ready User */
+#define EVSYS_CHSTATUS_RDYUSR       (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
+#define EVSYS_CHSTATUS_BUSYCH_Pos   1            /**< \brief (EVSYS_CHSTATUS) Busy Channel */
+#define EVSYS_CHSTATUS_BUSYCH       (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
+#define EVSYS_CHSTATUS_MASK         _U_(0x03)    /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:6;        /*!< bit:  0.. 5  Channel Event Selection            */
+    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x120        /**< \brief (EVSYS_USER offset) User Multiplexer n */
+#define EVSYS_USER_RESETVALUE       _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
+
+#define EVSYS_USER_CHANNEL_Pos      0            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define EVSYS_USER_MASK             _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
+
+/** \brief EvsysChannel hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
+  __IO EVSYS_CHINTENCLR_Type     CHINTENCLR;  /**< \brief Offset: 0x004 (R/W  8) Channel n Interrupt Enable Clear */
+  __IO EVSYS_CHINTENSET_Type     CHINTENSET;  /**< \brief Offset: 0x005 (R/W  8) Channel n Interrupt Enable Set */
+  __IO EVSYS_CHINTFLAG_Type      CHINTFLAG;   /**< \brief Offset: 0x006 (R/W  8) Channel n Interrupt Flag Status and Clear */
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x007 (R/   8) Channel n Status */
+} EvsysChannel;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EVSYS_CTRLA_Type          CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __O  EVSYS_SWEVT_Type          SWEVT;       /**< \brief Offset: 0x004 ( /W 32) Software Event */
+  __IO EVSYS_PRICTRL_Type        PRICTRL;     /**< \brief Offset: 0x008 (R/W  8) Priority Control */
+       RoReg8                    Reserved2[0x7];
+  __IO EVSYS_INTPEND_Type        INTPEND;     /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
+       RoReg8                    Reserved3[0x2];
+  __I  EVSYS_INTSTATUS_Type      INTSTATUS;   /**< \brief Offset: 0x014 (R/  32) Interrupt Status */
+  __I  EVSYS_BUSYCH_Type         BUSYCH;      /**< \brief Offset: 0x018 (R/  32) Busy Channels */
+  __I  EVSYS_READYUSR_Type       READYUSR;    /**< \brief Offset: 0x01C (R/  32) Ready Users */
+       EvsysChannel              Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
+  __IO EVSYS_USER_Type           USER[67];    /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_EVSYS_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/freqm.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/freqm.h
new file mode 100644
index 000000000..0f6da7721
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/freqm.h	
@@ -0,0 +1,233 @@
+/**
+ * \file
+ *
+ * \brief Component description for FREQM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_FREQM_COMPONENT_
+#define _SAME53_FREQM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR FREQM */
+/* ========================================================================== */
+/** \addtogroup SAME53_FREQM Frequency Meter */
+/*@{*/
+
+#define FREQM_U2257
+#define REV_FREQM                   0x110
+
+/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W  8) Control A Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} FREQM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CTRLA_OFFSET          0x00         /**< \brief (FREQM_CTRLA offset) Control A Register */
+#define FREQM_CTRLA_RESETVALUE      _U_(0x00)    /**< \brief (FREQM_CTRLA reset_value) Control A Register */
+
+#define FREQM_CTRLA_SWRST_Pos       0            /**< \brief (FREQM_CTRLA) Software Reset */
+#define FREQM_CTRLA_SWRST           (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
+#define FREQM_CTRLA_ENABLE_Pos      1            /**< \brief (FREQM_CTRLA) Enable */
+#define FREQM_CTRLA_ENABLE          (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
+#define FREQM_CTRLA_MASK            _U_(0x03)    /**< \brief (FREQM_CTRLA) MASK Register */
+
+/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W  8) Control B Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START:1;          /*!< bit:      0  Start Measurement                  */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} FREQM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CTRLB_OFFSET          0x01         /**< \brief (FREQM_CTRLB offset) Control B Register */
+#define FREQM_CTRLB_RESETVALUE      _U_(0x00)    /**< \brief (FREQM_CTRLB reset_value) Control B Register */
+
+#define FREQM_CTRLB_START_Pos       0            /**< \brief (FREQM_CTRLB) Start Measurement */
+#define FREQM_CTRLB_START           (_U_(0x1) << FREQM_CTRLB_START_Pos)
+#define FREQM_CTRLB_MASK            _U_(0x01)    /**< \brief (FREQM_CTRLB) MASK Register */
+
+/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t REFNUM:8;         /*!< bit:  0.. 7  Number of Reference Clock Cycles   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} FREQM_CFGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_CFGA_OFFSET           0x02         /**< \brief (FREQM_CFGA offset) Config A register */
+#define FREQM_CFGA_RESETVALUE       _U_(0x0000)  /**< \brief (FREQM_CFGA reset_value) Config A register */
+
+#define FREQM_CFGA_REFNUM_Pos       0            /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
+#define FREQM_CFGA_REFNUM_Msk       (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
+#define FREQM_CFGA_REFNUM(value)    (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
+#define FREQM_CFGA_MASK             _U_(0x00FF)  /**< \brief (FREQM_CFGA) MASK Register */
+
+/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W  8) Interrupt Enable Clear Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Measurement Done Interrupt Enable  */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} FREQM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTENCLR_OFFSET       0x08         /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
+#define FREQM_INTENCLR_RESETVALUE   _U_(0x00)    /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
+
+#define FREQM_INTENCLR_DONE_Pos     0            /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
+#define FREQM_INTENCLR_DONE         (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
+#define FREQM_INTENCLR_MASK         _U_(0x01)    /**< \brief (FREQM_INTENCLR) MASK Register */
+
+/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W  8) Interrupt Enable Set Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Measurement Done Interrupt Enable  */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} FREQM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTENSET_OFFSET       0x09         /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
+#define FREQM_INTENSET_RESETVALUE   _U_(0x00)    /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
+
+#define FREQM_INTENSET_DONE_Pos     0            /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
+#define FREQM_INTENSET_DONE         (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
+#define FREQM_INTENSET_MASK         _U_(0x01)    /**< \brief (FREQM_INTENSET) MASK Register */
+
+/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W  8) Interrupt Flag Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DONE:1;           /*!< bit:      0  Measurement Done                   */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} FREQM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_INTFLAG_OFFSET        0x0A         /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
+#define FREQM_INTFLAG_RESETVALUE    _U_(0x00)    /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
+
+#define FREQM_INTFLAG_DONE_Pos      0            /**< \brief (FREQM_INTFLAG) Measurement Done */
+#define FREQM_INTFLAG_DONE          (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
+#define FREQM_INTFLAG_MASK          _U_(0x01)    /**< \brief (FREQM_INTFLAG) MASK Register */
+
+/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W  8) Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BUSY:1;           /*!< bit:      0  FREQM Status                       */
+    uint8_t  OVF:1;            /*!< bit:      1  Sticky Count Value Overflow        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} FREQM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_STATUS_OFFSET         0x0B         /**< \brief (FREQM_STATUS offset) Status Register */
+#define FREQM_STATUS_RESETVALUE     _U_(0x00)    /**< \brief (FREQM_STATUS reset_value) Status Register */
+
+#define FREQM_STATUS_BUSY_Pos       0            /**< \brief (FREQM_STATUS) FREQM Status */
+#define FREQM_STATUS_BUSY           (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
+#define FREQM_STATUS_OVF_Pos        1            /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
+#define FREQM_STATUS_OVF            (_U_(0x1) << FREQM_STATUS_OVF_Pos)
+#define FREQM_STATUS_MASK           _U_(0x03)    /**< \brief (FREQM_STATUS) MASK Register */
+
+/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/  32) Synchronization Busy Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} FREQM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_SYNCBUSY_OFFSET       0x0C         /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
+#define FREQM_SYNCBUSY_RESETVALUE   _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
+
+#define FREQM_SYNCBUSY_SWRST_Pos    0            /**< \brief (FREQM_SYNCBUSY) Software Reset */
+#define FREQM_SYNCBUSY_SWRST        (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
+#define FREQM_SYNCBUSY_ENABLE_Pos   1            /**< \brief (FREQM_SYNCBUSY) Enable */
+#define FREQM_SYNCBUSY_ENABLE       (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
+#define FREQM_SYNCBUSY_MASK         _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
+
+/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/  32) Count Value Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t VALUE:24;         /*!< bit:  0..23  Measurement Value                  */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} FREQM_VALUE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define FREQM_VALUE_OFFSET          0x10         /**< \brief (FREQM_VALUE offset) Count Value Register */
+#define FREQM_VALUE_RESETVALUE      _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
+
+#define FREQM_VALUE_VALUE_Pos       0            /**< \brief (FREQM_VALUE) Measurement Value */
+#define FREQM_VALUE_VALUE_Msk       (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
+#define FREQM_VALUE_VALUE(value)    (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
+#define FREQM_VALUE_MASK            _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
+
+/** \brief FREQM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO FREQM_CTRLA_Type          CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A Register */
+  __O  FREQM_CTRLB_Type          CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B Register */
+  __IO FREQM_CFGA_Type           CFGA;        /**< \brief Offset: 0x02 (R/W 16) Config A register */
+       RoReg8                    Reserved1[0x4];
+  __IO FREQM_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear Register */
+  __IO FREQM_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set Register */
+  __IO FREQM_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Register */
+  __IO FREQM_STATUS_Type         STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status Register */
+  __I  FREQM_SYNCBUSY_Type       SYNCBUSY;    /**< \brief Offset: 0x0C (R/  32) Synchronization Busy Register */
+  __I  FREQM_VALUE_Type          VALUE;       /**< \brief Offset: 0x10 (R/  32) Count Value Register */
+} Freqm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_FREQM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/gclk.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/gclk.h
new file mode 100644
index 000000000..f4ae21e72
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/gclk.h	
@@ -0,0 +1,272 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_GCLK_COMPONENT_
+#define _SAME53_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAME53_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2122
+#define REV_GCLK                    0x120
+
+/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRLA_OFFSET           0x00         /**< \brief (GCLK_CTRLA offset) Control */
+#define GCLK_CTRLA_RESETVALUE       _U_(0x00)    /**< \brief (GCLK_CTRLA reset_value) Control */
+
+#define GCLK_CTRLA_SWRST_Pos        0            /**< \brief (GCLK_CTRLA) Software Reset */
+#define GCLK_CTRLA_SWRST            (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
+#define GCLK_CTRLA_MASK             _U_(0x01)    /**< \brief (GCLK_CTRLA) MASK Register */
+
+/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchroniation Busy bit */
+    uint32_t :1;               /*!< bit:      1  Reserved                           */
+    uint32_t GENCTRL0:1;       /*!< bit:      2  Generic Clock Generator Control 0 Synchronization Busy bits */
+    uint32_t GENCTRL1:1;       /*!< bit:      3  Generic Clock Generator Control 1 Synchronization Busy bits */
+    uint32_t GENCTRL2:1;       /*!< bit:      4  Generic Clock Generator Control 2 Synchronization Busy bits */
+    uint32_t GENCTRL3:1;       /*!< bit:      5  Generic Clock Generator Control 3 Synchronization Busy bits */
+    uint32_t GENCTRL4:1;       /*!< bit:      6  Generic Clock Generator Control 4 Synchronization Busy bits */
+    uint32_t GENCTRL5:1;       /*!< bit:      7  Generic Clock Generator Control 5 Synchronization Busy bits */
+    uint32_t GENCTRL6:1;       /*!< bit:      8  Generic Clock Generator Control 6 Synchronization Busy bits */
+    uint32_t GENCTRL7:1;       /*!< bit:      9  Generic Clock Generator Control 7 Synchronization Busy bits */
+    uint32_t GENCTRL8:1;       /*!< bit:     10  Generic Clock Generator Control 8 Synchronization Busy bits */
+    uint32_t GENCTRL9:1;       /*!< bit:     11  Generic Clock Generator Control 9 Synchronization Busy bits */
+    uint32_t GENCTRL10:1;      /*!< bit:     12  Generic Clock Generator Control 10 Synchronization Busy bits */
+    uint32_t GENCTRL11:1;      /*!< bit:     13  Generic Clock Generator Control 11 Synchronization Busy bits */
+    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t GENCTRL:12;       /*!< bit:  2..13  Generic Clock Generator Control x Synchronization Busy bits */
+    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_SYNCBUSY_OFFSET        0x04         /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
+#define GCLK_SYNCBUSY_RESETVALUE    _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
+
+#define GCLK_SYNCBUSY_SWRST_Pos     0            /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
+#define GCLK_SYNCBUSY_SWRST         (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
+#define GCLK_SYNCBUSY_GENCTRL0_Pos  2            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL0      (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
+#define GCLK_SYNCBUSY_GENCTRL1_Pos  3            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL1      (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
+#define GCLK_SYNCBUSY_GENCTRL2_Pos  4            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL2      (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
+#define GCLK_SYNCBUSY_GENCTRL3_Pos  5            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL3      (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
+#define GCLK_SYNCBUSY_GENCTRL4_Pos  6            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL4      (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
+#define GCLK_SYNCBUSY_GENCTRL5_Pos  7            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL5      (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
+#define GCLK_SYNCBUSY_GENCTRL6_Pos  8            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL6      (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
+#define GCLK_SYNCBUSY_GENCTRL7_Pos  9            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL7      (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
+#define GCLK_SYNCBUSY_GENCTRL8_Pos  10           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL8      (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
+#define GCLK_SYNCBUSY_GENCTRL9_Pos  11           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL9      (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
+#define GCLK_SYNCBUSY_GENCTRL10_Pos 12           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL10     (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
+#define GCLK_SYNCBUSY_GENCTRL11_Pos 13           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL11     (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_Pos   2            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL_Msk   (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_MASK          _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:4;            /*!< bit:  0.. 3  Source Select                      */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t GENEN:1;          /*!< bit:      8  Generic Clock Generator Enable     */
+    uint32_t IDC:1;            /*!< bit:      9  Improve Duty Cycle                 */
+    uint32_t OOV:1;            /*!< bit:     10  Output Off Value                   */
+    uint32_t OE:1;             /*!< bit:     11  Output Enable                      */
+    uint32_t DIVSEL:1;         /*!< bit:     12  Divide Selection                   */
+    uint32_t RUNSTDBY:1;       /*!< bit:     13  Run in Standby                     */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t DIV:16;           /*!< bit: 16..31  Division Factor                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET         0x20         /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_SRC_Pos        0            /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk        (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define   GCLK_GENCTRL_SRC_XOSC0_Val      _U_(0x0)   /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC1_Val      _U_(0x1)   /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     _U_(0x2)   /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   _U_(0x3)   /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  _U_(0x4)   /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    _U_(0x5)   /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL_Val       _U_(0x6)   /**< \brief (GCLK_GENCTRL) DFLL output */
+#define   GCLK_GENCTRL_SRC_DPLL0_Val      _U_(0x7)   /**< \brief (GCLK_GENCTRL) DPLL0 output */
+#define   GCLK_GENCTRL_SRC_DPLL1_Val      _U_(0x8)   /**< \brief (GCLK_GENCTRL) DPLL1 output */
+#define GCLK_GENCTRL_SRC_XOSC0      (GCLK_GENCTRL_SRC_XOSC0_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC1      (GCLK_GENCTRL_SRC_XOSC1_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL       (GCLK_GENCTRL_SRC_DFLL_Val     << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL0      (GCLK_GENCTRL_SRC_DPLL0_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL1      (GCLK_GENCTRL_SRC_DPLL1_Val    << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos      8            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN          (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos        9            /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC            (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos        10           /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV            (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos         11           /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE             (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos     12           /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL         (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos   13           /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY       (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_DIV_Pos        16           /**< \brief (GCLK_GENCTRL) Division Factor */
+#define GCLK_GENCTRL_DIV_Msk        (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
+#define GCLK_GENCTRL_DIV(value)     (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
+#define GCLK_GENCTRL_MASK           _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GEN:4;            /*!< bit:  0.. 3  Generic Clock Generator            */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t CHEN:1;           /*!< bit:      6  Channel Enable                     */
+    uint32_t WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_PCHCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_PCHCTRL_OFFSET         0x80         /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
+#define GCLK_PCHCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
+
+#define GCLK_PCHCTRL_GEN_Pos        0            /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
+#define GCLK_PCHCTRL_GEN_Msk        (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN(value)     (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
+#define   GCLK_PCHCTRL_GEN_GCLK0_Val      _U_(0x0)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
+#define   GCLK_PCHCTRL_GEN_GCLK1_Val      _U_(0x1)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
+#define   GCLK_PCHCTRL_GEN_GCLK2_Val      _U_(0x2)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
+#define   GCLK_PCHCTRL_GEN_GCLK3_Val      _U_(0x3)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
+#define   GCLK_PCHCTRL_GEN_GCLK4_Val      _U_(0x4)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
+#define   GCLK_PCHCTRL_GEN_GCLK5_Val      _U_(0x5)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
+#define   GCLK_PCHCTRL_GEN_GCLK6_Val      _U_(0x6)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
+#define   GCLK_PCHCTRL_GEN_GCLK7_Val      _U_(0x7)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
+#define   GCLK_PCHCTRL_GEN_GCLK8_Val      _U_(0x8)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
+#define   GCLK_PCHCTRL_GEN_GCLK9_Val      _U_(0x9)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
+#define   GCLK_PCHCTRL_GEN_GCLK10_Val     _U_(0xA)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
+#define   GCLK_PCHCTRL_GEN_GCLK11_Val     _U_(0xB)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
+#define GCLK_PCHCTRL_GEN_GCLK0      (GCLK_PCHCTRL_GEN_GCLK0_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK1      (GCLK_PCHCTRL_GEN_GCLK1_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK2      (GCLK_PCHCTRL_GEN_GCLK2_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK3      (GCLK_PCHCTRL_GEN_GCLK3_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK4      (GCLK_PCHCTRL_GEN_GCLK4_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK5      (GCLK_PCHCTRL_GEN_GCLK5_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK6      (GCLK_PCHCTRL_GEN_GCLK6_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK7      (GCLK_PCHCTRL_GEN_GCLK7_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK8      (GCLK_PCHCTRL_GEN_GCLK8_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK9      (GCLK_PCHCTRL_GEN_GCLK9_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK10     (GCLK_PCHCTRL_GEN_GCLK10_Val   << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK11     (GCLK_PCHCTRL_GEN_GCLK11_Val   << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_CHEN_Pos       6            /**< \brief (GCLK_PCHCTRL) Channel Enable */
+#define GCLK_PCHCTRL_CHEN           (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
+#define GCLK_PCHCTRL_WRTLOCK_Pos    7            /**< \brief (GCLK_PCHCTRL) Write Lock */
+#define GCLK_PCHCTRL_WRTLOCK        (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
+#define GCLK_PCHCTRL_MASK           _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GCLK_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __I  GCLK_SYNCBUSY_Type        SYNCBUSY;    /**< \brief Offset: 0x04 (R/  32) Synchronization Busy */
+       RoReg8                    Reserved2[0x18];
+  __IO GCLK_GENCTRL_Type         GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
+       RoReg8                    Reserved3[0x30];
+  __IO GCLK_PCHCTRL_Type         PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_GCLK_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/gmac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/gmac.h
new file mode 100644
index 000000000..a865d5349
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/gmac.h	
@@ -0,0 +1,2593 @@
+/**
+ * \file
+ *
+ * \brief Component description for GMAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_GMAC_COMPONENT_
+#define _SAME53_GMAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GMAC */
+/* ========================================================================== */
+/** \addtogroup SAME53_GMAC Ethernet MAC */
+/*@{*/
+
+#define GMAC_U2005
+#define REV_GMAC                    0x100
+
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) (R/W 32) Network Control Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t LBL:1;            /*!< bit:      1  Loop Back Local                    */
+    uint32_t RXEN:1;           /*!< bit:      2  Receive Enable                     */
+    uint32_t TXEN:1;           /*!< bit:      3  Transmit Enable                    */
+    uint32_t MPE:1;            /*!< bit:      4  Management Port Enable             */
+    uint32_t CLRSTAT:1;        /*!< bit:      5  Clear Statistics Registers         */
+    uint32_t INCSTAT:1;        /*!< bit:      6  Increment Statistics Registers     */
+    uint32_t WESTAT:1;         /*!< bit:      7  Write Enable for Statistics Registers */
+    uint32_t BP:1;             /*!< bit:      8  Back pressure                      */
+    uint32_t TSTART:1;         /*!< bit:      9  Start Transmission                 */
+    uint32_t THALT:1;          /*!< bit:     10  Transmit Halt                      */
+    uint32_t TXPF:1;           /*!< bit:     11  Transmit Pause Frame               */
+    uint32_t TXZQPF:1;         /*!< bit:     12  Transmit Zero Quantum Pause Frame  */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t SRTSM:1;          /*!< bit:     15  Store Receive Time Stamp to Memory */
+    uint32_t ENPBPR:1;         /*!< bit:     16  Enable PFC Priority-based Pause Reception */
+    uint32_t TXPBPF:1;         /*!< bit:     17  Transmit PFC Priority-based Pause Frame */
+    uint32_t FNP:1;            /*!< bit:     18  Flush Next Packet                  */
+    uint32_t LPI:1;            /*!< bit:     19  Low Power Idle Enable              */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_NCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NCR_OFFSET             0x000        /**< \brief (GMAC_NCR offset) Network Control Register */
+#define GMAC_NCR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_NCR reset_value) Network Control Register */
+
+#define GMAC_NCR_LBL_Pos            1            /**< \brief (GMAC_NCR) Loop Back Local */
+#define GMAC_NCR_LBL                (_U_(0x1) << GMAC_NCR_LBL_Pos)
+#define GMAC_NCR_RXEN_Pos           2            /**< \brief (GMAC_NCR) Receive Enable */
+#define GMAC_NCR_RXEN               (_U_(0x1) << GMAC_NCR_RXEN_Pos)
+#define GMAC_NCR_TXEN_Pos           3            /**< \brief (GMAC_NCR) Transmit Enable */
+#define GMAC_NCR_TXEN               (_U_(0x1) << GMAC_NCR_TXEN_Pos)
+#define GMAC_NCR_MPE_Pos            4            /**< \brief (GMAC_NCR) Management Port Enable */
+#define GMAC_NCR_MPE                (_U_(0x1) << GMAC_NCR_MPE_Pos)
+#define GMAC_NCR_CLRSTAT_Pos        5            /**< \brief (GMAC_NCR) Clear Statistics Registers */
+#define GMAC_NCR_CLRSTAT            (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos)
+#define GMAC_NCR_INCSTAT_Pos        6            /**< \brief (GMAC_NCR) Increment Statistics Registers */
+#define GMAC_NCR_INCSTAT            (_U_(0x1) << GMAC_NCR_INCSTAT_Pos)
+#define GMAC_NCR_WESTAT_Pos         7            /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
+#define GMAC_NCR_WESTAT             (_U_(0x1) << GMAC_NCR_WESTAT_Pos)
+#define GMAC_NCR_BP_Pos             8            /**< \brief (GMAC_NCR) Back pressure */
+#define GMAC_NCR_BP                 (_U_(0x1) << GMAC_NCR_BP_Pos)
+#define GMAC_NCR_TSTART_Pos         9            /**< \brief (GMAC_NCR) Start Transmission */
+#define GMAC_NCR_TSTART             (_U_(0x1) << GMAC_NCR_TSTART_Pos)
+#define GMAC_NCR_THALT_Pos          10           /**< \brief (GMAC_NCR) Transmit Halt */
+#define GMAC_NCR_THALT              (_U_(0x1) << GMAC_NCR_THALT_Pos)
+#define GMAC_NCR_TXPF_Pos           11           /**< \brief (GMAC_NCR) Transmit Pause Frame */
+#define GMAC_NCR_TXPF               (_U_(0x1) << GMAC_NCR_TXPF_Pos)
+#define GMAC_NCR_TXZQPF_Pos         12           /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
+#define GMAC_NCR_TXZQPF             (_U_(0x1) << GMAC_NCR_TXZQPF_Pos)
+#define GMAC_NCR_SRTSM_Pos          15           /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
+#define GMAC_NCR_SRTSM              (_U_(0x1) << GMAC_NCR_SRTSM_Pos)
+#define GMAC_NCR_ENPBPR_Pos         16           /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
+#define GMAC_NCR_ENPBPR             (_U_(0x1) << GMAC_NCR_ENPBPR_Pos)
+#define GMAC_NCR_TXPBPF_Pos         17           /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
+#define GMAC_NCR_TXPBPF             (_U_(0x1) << GMAC_NCR_TXPBPF_Pos)
+#define GMAC_NCR_FNP_Pos            18           /**< \brief (GMAC_NCR) Flush Next Packet */
+#define GMAC_NCR_FNP                (_U_(0x1) << GMAC_NCR_FNP_Pos)
+#define GMAC_NCR_LPI_Pos            19           /**< \brief (GMAC_NCR) Low Power Idle Enable */
+#define GMAC_NCR_LPI                (_U_(0x1) << GMAC_NCR_LPI_Pos)
+#define GMAC_NCR_MASK               _U_(0x000F9FFE) /**< \brief (GMAC_NCR) MASK Register */
+
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) (R/W 32) Network Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SPD:1;            /*!< bit:      0  Speed                              */
+    uint32_t FD:1;             /*!< bit:      1  Full Duplex                        */
+    uint32_t DNVLAN:1;         /*!< bit:      2  Discard Non-VLAN FRAMES            */
+    uint32_t JFRAME:1;         /*!< bit:      3  Jumbo Frame Size                   */
+    uint32_t CAF:1;            /*!< bit:      4  Copy All Frames                    */
+    uint32_t NBC:1;            /*!< bit:      5  No Broadcast                       */
+    uint32_t MTIHEN:1;         /*!< bit:      6  Multicast Hash Enable              */
+    uint32_t UNIHEN:1;         /*!< bit:      7  Unicast Hash Enable                */
+    uint32_t MAXFS:1;          /*!< bit:      8  1536 Maximum Frame Size            */
+    uint32_t :3;               /*!< bit:  9..11  Reserved                           */
+    uint32_t RTY:1;            /*!< bit:     12  Retry Test                         */
+    uint32_t PEN:1;            /*!< bit:     13  Pause Enable                       */
+    uint32_t RXBUFO:2;         /*!< bit: 14..15  Receive Buffer Offset              */
+    uint32_t LFERD:1;          /*!< bit:     16  Length Field Error Frame Discard   */
+    uint32_t RFCS:1;           /*!< bit:     17  Remove FCS                         */
+    uint32_t CLK:3;            /*!< bit: 18..20  MDC CLock Division                 */
+    uint32_t DBW:2;            /*!< bit: 21..22  Data Bus Width                     */
+    uint32_t DCPF:1;           /*!< bit:     23  Disable Copy of Pause Frames       */
+    uint32_t RXCOEN:1;         /*!< bit:     24  Receive Checksum Offload Enable    */
+    uint32_t EFRHD:1;          /*!< bit:     25  Enable Frames Received in Half Duplex */
+    uint32_t IRXFCS:1;         /*!< bit:     26  Ignore RX FCS                      */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t IPGSEN:1;         /*!< bit:     28  IP Stretch Enable                  */
+    uint32_t RXBP:1;           /*!< bit:     29  Receive Bad Preamble               */
+    uint32_t IRXER:1;          /*!< bit:     30  Ignore IPG GRXER                   */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_NCFGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NCFGR_OFFSET           0x004        /**< \brief (GMAC_NCFGR offset) Network Configuration Register */
+#define GMAC_NCFGR_RESETVALUE       _U_(0x00080000) /**< \brief (GMAC_NCFGR reset_value) Network Configuration Register */
+
+#define GMAC_NCFGR_SPD_Pos          0            /**< \brief (GMAC_NCFGR) Speed */
+#define GMAC_NCFGR_SPD              (_U_(0x1) << GMAC_NCFGR_SPD_Pos)
+#define GMAC_NCFGR_FD_Pos           1            /**< \brief (GMAC_NCFGR) Full Duplex */
+#define GMAC_NCFGR_FD               (_U_(0x1) << GMAC_NCFGR_FD_Pos)
+#define GMAC_NCFGR_DNVLAN_Pos       2            /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
+#define GMAC_NCFGR_DNVLAN           (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos)
+#define GMAC_NCFGR_JFRAME_Pos       3            /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
+#define GMAC_NCFGR_JFRAME           (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos)
+#define GMAC_NCFGR_CAF_Pos          4            /**< \brief (GMAC_NCFGR) Copy All Frames */
+#define GMAC_NCFGR_CAF              (_U_(0x1) << GMAC_NCFGR_CAF_Pos)
+#define GMAC_NCFGR_NBC_Pos          5            /**< \brief (GMAC_NCFGR) No Broadcast */
+#define GMAC_NCFGR_NBC              (_U_(0x1) << GMAC_NCFGR_NBC_Pos)
+#define GMAC_NCFGR_MTIHEN_Pos       6            /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
+#define GMAC_NCFGR_MTIHEN           (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos)
+#define GMAC_NCFGR_UNIHEN_Pos       7            /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
+#define GMAC_NCFGR_UNIHEN           (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos)
+#define GMAC_NCFGR_MAXFS_Pos        8            /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
+#define GMAC_NCFGR_MAXFS            (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos)
+#define GMAC_NCFGR_RTY_Pos          12           /**< \brief (GMAC_NCFGR) Retry Test */
+#define GMAC_NCFGR_RTY              (_U_(0x1) << GMAC_NCFGR_RTY_Pos)
+#define GMAC_NCFGR_PEN_Pos          13           /**< \brief (GMAC_NCFGR) Pause Enable */
+#define GMAC_NCFGR_PEN              (_U_(0x1) << GMAC_NCFGR_PEN_Pos)
+#define GMAC_NCFGR_RXBUFO_Pos       14           /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
+#define GMAC_NCFGR_RXBUFO_Msk       (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos)
+#define GMAC_NCFGR_RXBUFO(value)    (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))
+#define GMAC_NCFGR_LFERD_Pos        16           /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
+#define GMAC_NCFGR_LFERD            (_U_(0x1) << GMAC_NCFGR_LFERD_Pos)
+#define GMAC_NCFGR_RFCS_Pos         17           /**< \brief (GMAC_NCFGR) Remove FCS */
+#define GMAC_NCFGR_RFCS             (_U_(0x1) << GMAC_NCFGR_RFCS_Pos)
+#define GMAC_NCFGR_CLK_Pos          18           /**< \brief (GMAC_NCFGR) MDC CLock Division */
+#define GMAC_NCFGR_CLK_Msk          (_U_(0x7) << GMAC_NCFGR_CLK_Pos)
+#define GMAC_NCFGR_CLK(value)       (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))
+#define GMAC_NCFGR_DBW_Pos          21           /**< \brief (GMAC_NCFGR) Data Bus Width */
+#define GMAC_NCFGR_DBW_Msk          (_U_(0x3) << GMAC_NCFGR_DBW_Pos)
+#define GMAC_NCFGR_DBW(value)       (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))
+#define GMAC_NCFGR_DCPF_Pos         23           /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
+#define GMAC_NCFGR_DCPF             (_U_(0x1) << GMAC_NCFGR_DCPF_Pos)
+#define GMAC_NCFGR_RXCOEN_Pos       24           /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
+#define GMAC_NCFGR_RXCOEN           (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos)
+#define GMAC_NCFGR_EFRHD_Pos        25           /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
+#define GMAC_NCFGR_EFRHD            (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos)
+#define GMAC_NCFGR_IRXFCS_Pos       26           /**< \brief (GMAC_NCFGR) Ignore RX FCS */
+#define GMAC_NCFGR_IRXFCS           (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos)
+#define GMAC_NCFGR_IPGSEN_Pos       28           /**< \brief (GMAC_NCFGR) IP Stretch Enable */
+#define GMAC_NCFGR_IPGSEN           (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos)
+#define GMAC_NCFGR_RXBP_Pos         29           /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
+#define GMAC_NCFGR_RXBP             (_U_(0x1) << GMAC_NCFGR_RXBP_Pos)
+#define GMAC_NCFGR_IRXER_Pos        30           /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */
+#define GMAC_NCFGR_IRXER            (_U_(0x1) << GMAC_NCFGR_IRXER_Pos)
+#define GMAC_NCFGR_MASK             _U_(0x77FFF1FF) /**< \brief (GMAC_NCFGR) MASK Register */
+
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) (R/  32) Network Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t MDIO:1;           /*!< bit:      1  MDIO Input Status                  */
+    uint32_t IDLE:1;           /*!< bit:      2  PHY Management Logic Idle          */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_NSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NSR_OFFSET             0x008        /**< \brief (GMAC_NSR offset) Network Status Register */
+#define GMAC_NSR_RESETVALUE         _U_(0x00000004) /**< \brief (GMAC_NSR reset_value) Network Status Register */
+
+#define GMAC_NSR_MDIO_Pos           1            /**< \brief (GMAC_NSR) MDIO Input Status */
+#define GMAC_NSR_MDIO               (_U_(0x1) << GMAC_NSR_MDIO_Pos)
+#define GMAC_NSR_IDLE_Pos           2            /**< \brief (GMAC_NSR) PHY Management Logic Idle */
+#define GMAC_NSR_IDLE               (_U_(0x1) << GMAC_NSR_IDLE_Pos)
+#define GMAC_NSR_MASK               _U_(0x00000006) /**< \brief (GMAC_NSR) MASK Register */
+
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) (R/W 32) User Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MII:1;            /*!< bit:      0  MII Mode                           */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_UR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UR_OFFSET              0x00C        /**< \brief (GMAC_UR offset) User Register */
+#define GMAC_UR_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_UR reset_value) User Register */
+
+#define GMAC_UR_MII_Pos             0            /**< \brief (GMAC_UR) MII Mode */
+#define GMAC_UR_MII                 (_U_(0x1) << GMAC_UR_MII_Pos)
+#define GMAC_UR_MASK                _U_(0x00000001) /**< \brief (GMAC_UR) MASK Register */
+
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) (R/W 32) DMA Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FBLDO:5;          /*!< bit:  0.. 4  Fixed Burst Length for DMA Data Operations: */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t ESMA:1;           /*!< bit:      6  Endian Swap Mode Enable for Management Descriptor Accesses */
+    uint32_t ESPA:1;           /*!< bit:      7  Endian Swap Mode Enable for Packet Data Accesses */
+    uint32_t RXBMS:2;          /*!< bit:  8.. 9  Receiver Packet Buffer Memory Size Select */
+    uint32_t TXPBMS:1;         /*!< bit:     10  Transmitter Packet Buffer Memory Size Select */
+    uint32_t TXCOEN:1;         /*!< bit:     11  Transmitter Checksum Generation Offload Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DRBS:8;           /*!< bit: 16..23  DMA Receive Buffer Size            */
+    uint32_t DDRP:1;           /*!< bit:     24  DMA Discard Receive Packets        */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_DCFGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_DCFGR_OFFSET           0x010        /**< \brief (GMAC_DCFGR offset) DMA Configuration Register */
+#define GMAC_DCFGR_RESETVALUE       _U_(0x00020704) /**< \brief (GMAC_DCFGR reset_value) DMA Configuration Register */
+
+#define GMAC_DCFGR_FBLDO_Pos        0            /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
+#define GMAC_DCFGR_FBLDO_Msk        (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos)
+#define GMAC_DCFGR_FBLDO(value)     (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))
+#define GMAC_DCFGR_ESMA_Pos         6            /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
+#define GMAC_DCFGR_ESMA             (_U_(0x1) << GMAC_DCFGR_ESMA_Pos)
+#define GMAC_DCFGR_ESPA_Pos         7            /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
+#define GMAC_DCFGR_ESPA             (_U_(0x1) << GMAC_DCFGR_ESPA_Pos)
+#define GMAC_DCFGR_RXBMS_Pos        8            /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_RXBMS_Msk        (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos)
+#define GMAC_DCFGR_RXBMS(value)     (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))
+#define GMAC_DCFGR_TXPBMS_Pos       10           /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_TXPBMS           (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos)
+#define GMAC_DCFGR_TXCOEN_Pos       11           /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
+#define GMAC_DCFGR_TXCOEN           (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos)
+#define GMAC_DCFGR_DRBS_Pos         16           /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
+#define GMAC_DCFGR_DRBS_Msk         (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos)
+#define GMAC_DCFGR_DRBS(value)      (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))
+#define GMAC_DCFGR_DDRP_Pos         24           /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
+#define GMAC_DCFGR_DDRP             (_U_(0x1) << GMAC_DCFGR_DDRP_Pos)
+#define GMAC_DCFGR_MASK             _U_(0x01FF0FDF) /**< \brief (GMAC_DCFGR) MASK Register */
+
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) (R/W 32) Transmit Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t UBR:1;            /*!< bit:      0  Used Bit Read                      */
+    uint32_t COL:1;            /*!< bit:      1  Collision Occurred                 */
+    uint32_t RLE:1;            /*!< bit:      2  Retry Limit Exceeded               */
+    uint32_t TXGO:1;           /*!< bit:      3  Transmit Go                        */
+    uint32_t TFC:1;            /*!< bit:      4  Transmit Frame Corruption Due to AHB Error */
+    uint32_t TXCOMP:1;         /*!< bit:      5  Transmit Complete                  */
+    uint32_t UND:1;            /*!< bit:      6  Transmit Underrun                  */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t HRESP:1;          /*!< bit:      8  HRESP Not OK                       */
+    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSR_OFFSET             0x014        /**< \brief (GMAC_TSR offset) Transmit Status Register */
+#define GMAC_TSR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_TSR reset_value) Transmit Status Register */
+
+#define GMAC_TSR_UBR_Pos            0            /**< \brief (GMAC_TSR) Used Bit Read */
+#define GMAC_TSR_UBR                (_U_(0x1) << GMAC_TSR_UBR_Pos)
+#define GMAC_TSR_COL_Pos            1            /**< \brief (GMAC_TSR) Collision Occurred */
+#define GMAC_TSR_COL                (_U_(0x1) << GMAC_TSR_COL_Pos)
+#define GMAC_TSR_RLE_Pos            2            /**< \brief (GMAC_TSR) Retry Limit Exceeded */
+#define GMAC_TSR_RLE                (_U_(0x1) << GMAC_TSR_RLE_Pos)
+#define GMAC_TSR_TXGO_Pos           3            /**< \brief (GMAC_TSR) Transmit Go */
+#define GMAC_TSR_TXGO               (_U_(0x1) << GMAC_TSR_TXGO_Pos)
+#define GMAC_TSR_TFC_Pos            4            /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_TSR_TFC                (_U_(0x1) << GMAC_TSR_TFC_Pos)
+#define GMAC_TSR_TXCOMP_Pos         5            /**< \brief (GMAC_TSR) Transmit Complete */
+#define GMAC_TSR_TXCOMP             (_U_(0x1) << GMAC_TSR_TXCOMP_Pos)
+#define GMAC_TSR_UND_Pos            6            /**< \brief (GMAC_TSR) Transmit Underrun */
+#define GMAC_TSR_UND                (_U_(0x1) << GMAC_TSR_UND_Pos)
+#define GMAC_TSR_HRESP_Pos          8            /**< \brief (GMAC_TSR) HRESP Not OK */
+#define GMAC_TSR_HRESP              (_U_(0x1) << GMAC_TSR_HRESP_Pos)
+#define GMAC_TSR_MASK               _U_(0x0000017F) /**< \brief (GMAC_TSR) MASK Register */
+
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) (R/W 32) Receive Buffer Queue Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Receive Buffer Queue Base Address  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RBQB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RBQB_OFFSET            0x018        /**< \brief (GMAC_RBQB offset) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_RBQB reset_value) Receive Buffer Queue Base Address */
+
+#define GMAC_RBQB_ADDR_Pos          2            /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_ADDR_Msk          (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos)
+#define GMAC_RBQB_ADDR(value)       (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))
+#define GMAC_RBQB_MASK              _U_(0xFFFFFFFC) /**< \brief (GMAC_RBQB) MASK Register */
+
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) (R/W 32) Transmit Buffer Queue Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Transmit Buffer Queue Base Address */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBQB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBQB_OFFSET            0x01C        /**< \brief (GMAC_TBQB offset) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_TBQB reset_value) Transmit Buffer Queue Base Address */
+
+#define GMAC_TBQB_ADDR_Pos          2            /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_ADDR_Msk          (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos)
+#define GMAC_TBQB_ADDR(value)       (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))
+#define GMAC_TBQB_MASK              _U_(0xFFFFFFFC) /**< \brief (GMAC_TBQB) MASK Register */
+
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) (R/W 32) Receive Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BNA:1;            /*!< bit:      0  Buffer Not Available               */
+    uint32_t REC:1;            /*!< bit:      1  Frame Received                     */
+    uint32_t RXOVR:1;          /*!< bit:      2  Receive Overrun                    */
+    uint32_t HNO:1;            /*!< bit:      3  HRESP Not OK                       */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RSR_OFFSET             0x020        /**< \brief (GMAC_RSR offset) Receive Status Register */
+#define GMAC_RSR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_RSR reset_value) Receive Status Register */
+
+#define GMAC_RSR_BNA_Pos            0            /**< \brief (GMAC_RSR) Buffer Not Available */
+#define GMAC_RSR_BNA                (_U_(0x1) << GMAC_RSR_BNA_Pos)
+#define GMAC_RSR_REC_Pos            1            /**< \brief (GMAC_RSR) Frame Received */
+#define GMAC_RSR_REC                (_U_(0x1) << GMAC_RSR_REC_Pos)
+#define GMAC_RSR_RXOVR_Pos          2            /**< \brief (GMAC_RSR) Receive Overrun */
+#define GMAC_RSR_RXOVR              (_U_(0x1) << GMAC_RSR_RXOVR_Pos)
+#define GMAC_RSR_HNO_Pos            3            /**< \brief (GMAC_RSR) HRESP Not OK */
+#define GMAC_RSR_HNO                (_U_(0x1) << GMAC_RSR_HNO_Pos)
+#define GMAC_RSR_MASK               _U_(0x0000000F) /**< \brief (GMAC_RSR) MASK Register */
+
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) (R/W 32) Interrupt Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
+    uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
+    uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
+    uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
+    uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
+    uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded               */
+    uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
+    uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
+    uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
+    uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
+    uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
+    uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
+    uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
+    uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
+    uint32_t :3;               /*!< bit: 15..17  Reserved                           */
+    uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
+    uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
+    uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
+    uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
+    uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
+    uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
+    uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
+    uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
+    uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t WOL:1;            /*!< bit:     28  Wake On LAN                        */
+    uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ISR_OFFSET             0x024        /**< \brief (GMAC_ISR offset) Interrupt Status Register */
+#define GMAC_ISR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_ISR reset_value) Interrupt Status Register */
+
+#define GMAC_ISR_MFS_Pos            0            /**< \brief (GMAC_ISR) Management Frame Sent */
+#define GMAC_ISR_MFS                (_U_(0x1) << GMAC_ISR_MFS_Pos)
+#define GMAC_ISR_RCOMP_Pos          1            /**< \brief (GMAC_ISR) Receive Complete */
+#define GMAC_ISR_RCOMP              (_U_(0x1) << GMAC_ISR_RCOMP_Pos)
+#define GMAC_ISR_RXUBR_Pos          2            /**< \brief (GMAC_ISR) RX Used Bit Read */
+#define GMAC_ISR_RXUBR              (_U_(0x1) << GMAC_ISR_RXUBR_Pos)
+#define GMAC_ISR_TXUBR_Pos          3            /**< \brief (GMAC_ISR) TX Used Bit Read */
+#define GMAC_ISR_TXUBR              (_U_(0x1) << GMAC_ISR_TXUBR_Pos)
+#define GMAC_ISR_TUR_Pos            4            /**< \brief (GMAC_ISR) Transmit Underrun */
+#define GMAC_ISR_TUR                (_U_(0x1) << GMAC_ISR_TUR_Pos)
+#define GMAC_ISR_RLEX_Pos           5            /**< \brief (GMAC_ISR) Retry Limit Exceeded */
+#define GMAC_ISR_RLEX               (_U_(0x1) << GMAC_ISR_RLEX_Pos)
+#define GMAC_ISR_TFC_Pos            6            /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_ISR_TFC                (_U_(0x1) << GMAC_ISR_TFC_Pos)
+#define GMAC_ISR_TCOMP_Pos          7            /**< \brief (GMAC_ISR) Transmit Complete */
+#define GMAC_ISR_TCOMP              (_U_(0x1) << GMAC_ISR_TCOMP_Pos)
+#define GMAC_ISR_ROVR_Pos           10           /**< \brief (GMAC_ISR) Receive Overrun */
+#define GMAC_ISR_ROVR               (_U_(0x1) << GMAC_ISR_ROVR_Pos)
+#define GMAC_ISR_HRESP_Pos          11           /**< \brief (GMAC_ISR) HRESP Not OK */
+#define GMAC_ISR_HRESP              (_U_(0x1) << GMAC_ISR_HRESP_Pos)
+#define GMAC_ISR_PFNZ_Pos           12           /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_ISR_PFNZ               (_U_(0x1) << GMAC_ISR_PFNZ_Pos)
+#define GMAC_ISR_PTZ_Pos            13           /**< \brief (GMAC_ISR) Pause Time Zero */
+#define GMAC_ISR_PTZ                (_U_(0x1) << GMAC_ISR_PTZ_Pos)
+#define GMAC_ISR_PFTR_Pos           14           /**< \brief (GMAC_ISR) Pause Frame Transmitted */
+#define GMAC_ISR_PFTR               (_U_(0x1) << GMAC_ISR_PFTR_Pos)
+#define GMAC_ISR_DRQFR_Pos          18           /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
+#define GMAC_ISR_DRQFR              (_U_(0x1) << GMAC_ISR_DRQFR_Pos)
+#define GMAC_ISR_SFR_Pos            19           /**< \brief (GMAC_ISR) PTP Sync Frame Received */
+#define GMAC_ISR_SFR                (_U_(0x1) << GMAC_ISR_SFR_Pos)
+#define GMAC_ISR_DRQFT_Pos          20           /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
+#define GMAC_ISR_DRQFT              (_U_(0x1) << GMAC_ISR_DRQFT_Pos)
+#define GMAC_ISR_SFT_Pos            21           /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
+#define GMAC_ISR_SFT                (_U_(0x1) << GMAC_ISR_SFT_Pos)
+#define GMAC_ISR_PDRQFR_Pos         22           /**< \brief (GMAC_ISR) PDelay Request Frame Received */
+#define GMAC_ISR_PDRQFR             (_U_(0x1) << GMAC_ISR_PDRQFR_Pos)
+#define GMAC_ISR_PDRSFR_Pos         23           /**< \brief (GMAC_ISR) PDelay Response Frame Received */
+#define GMAC_ISR_PDRSFR             (_U_(0x1) << GMAC_ISR_PDRSFR_Pos)
+#define GMAC_ISR_PDRQFT_Pos         24           /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
+#define GMAC_ISR_PDRQFT             (_U_(0x1) << GMAC_ISR_PDRQFT_Pos)
+#define GMAC_ISR_PDRSFT_Pos         25           /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
+#define GMAC_ISR_PDRSFT             (_U_(0x1) << GMAC_ISR_PDRSFT_Pos)
+#define GMAC_ISR_SRI_Pos            26           /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
+#define GMAC_ISR_SRI                (_U_(0x1) << GMAC_ISR_SRI_Pos)
+#define GMAC_ISR_WOL_Pos            28           /**< \brief (GMAC_ISR) Wake On LAN */
+#define GMAC_ISR_WOL                (_U_(0x1) << GMAC_ISR_WOL_Pos)
+#define GMAC_ISR_TSUCMP_Pos         29           /**< \brief (GMAC_ISR) Tsu timer comparison */
+#define GMAC_ISR_TSUCMP             (_U_(0x1) << GMAC_ISR_TSUCMP_Pos)
+#define GMAC_ISR_MASK               _U_(0x37FC7CFF) /**< \brief (GMAC_ISR) MASK Register */
+
+/* -------- GMAC_IER : (GMAC Offset: 0x028) ( /W 32) Interrupt Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
+    uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
+    uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
+    uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
+    uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
+    uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded or Late Collision */
+    uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
+    uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
+    uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
+    uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
+    uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
+    uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
+    uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
+    uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
+    uint32_t EXINT:1;          /*!< bit:     15  External Interrupt                 */
+    uint32_t :2;               /*!< bit: 16..17  Reserved                           */
+    uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
+    uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
+    uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
+    uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
+    uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
+    uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
+    uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
+    uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
+    uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t WOL:1;            /*!< bit:     28  Wake On LAN                        */
+    uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IER_OFFSET             0x028        /**< \brief (GMAC_IER offset) Interrupt Enable Register */
+
+#define GMAC_IER_MFS_Pos            0            /**< \brief (GMAC_IER) Management Frame Sent */
+#define GMAC_IER_MFS                (_U_(0x1) << GMAC_IER_MFS_Pos)
+#define GMAC_IER_RCOMP_Pos          1            /**< \brief (GMAC_IER) Receive Complete */
+#define GMAC_IER_RCOMP              (_U_(0x1) << GMAC_IER_RCOMP_Pos)
+#define GMAC_IER_RXUBR_Pos          2            /**< \brief (GMAC_IER) RX Used Bit Read */
+#define GMAC_IER_RXUBR              (_U_(0x1) << GMAC_IER_RXUBR_Pos)
+#define GMAC_IER_TXUBR_Pos          3            /**< \brief (GMAC_IER) TX Used Bit Read */
+#define GMAC_IER_TXUBR              (_U_(0x1) << GMAC_IER_TXUBR_Pos)
+#define GMAC_IER_TUR_Pos            4            /**< \brief (GMAC_IER) Transmit Underrun */
+#define GMAC_IER_TUR                (_U_(0x1) << GMAC_IER_TUR_Pos)
+#define GMAC_IER_RLEX_Pos           5            /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
+#define GMAC_IER_RLEX               (_U_(0x1) << GMAC_IER_RLEX_Pos)
+#define GMAC_IER_TFC_Pos            6            /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IER_TFC                (_U_(0x1) << GMAC_IER_TFC_Pos)
+#define GMAC_IER_TCOMP_Pos          7            /**< \brief (GMAC_IER) Transmit Complete */
+#define GMAC_IER_TCOMP              (_U_(0x1) << GMAC_IER_TCOMP_Pos)
+#define GMAC_IER_ROVR_Pos           10           /**< \brief (GMAC_IER) Receive Overrun */
+#define GMAC_IER_ROVR               (_U_(0x1) << GMAC_IER_ROVR_Pos)
+#define GMAC_IER_HRESP_Pos          11           /**< \brief (GMAC_IER) HRESP Not OK */
+#define GMAC_IER_HRESP              (_U_(0x1) << GMAC_IER_HRESP_Pos)
+#define GMAC_IER_PFNZ_Pos           12           /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IER_PFNZ               (_U_(0x1) << GMAC_IER_PFNZ_Pos)
+#define GMAC_IER_PTZ_Pos            13           /**< \brief (GMAC_IER) Pause Time Zero */
+#define GMAC_IER_PTZ                (_U_(0x1) << GMAC_IER_PTZ_Pos)
+#define GMAC_IER_PFTR_Pos           14           /**< \brief (GMAC_IER) Pause Frame Transmitted */
+#define GMAC_IER_PFTR               (_U_(0x1) << GMAC_IER_PFTR_Pos)
+#define GMAC_IER_EXINT_Pos          15           /**< \brief (GMAC_IER) External Interrupt */
+#define GMAC_IER_EXINT              (_U_(0x1) << GMAC_IER_EXINT_Pos)
+#define GMAC_IER_DRQFR_Pos          18           /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
+#define GMAC_IER_DRQFR              (_U_(0x1) << GMAC_IER_DRQFR_Pos)
+#define GMAC_IER_SFR_Pos            19           /**< \brief (GMAC_IER) PTP Sync Frame Received */
+#define GMAC_IER_SFR                (_U_(0x1) << GMAC_IER_SFR_Pos)
+#define GMAC_IER_DRQFT_Pos          20           /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
+#define GMAC_IER_DRQFT              (_U_(0x1) << GMAC_IER_DRQFT_Pos)
+#define GMAC_IER_SFT_Pos            21           /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
+#define GMAC_IER_SFT                (_U_(0x1) << GMAC_IER_SFT_Pos)
+#define GMAC_IER_PDRQFR_Pos         22           /**< \brief (GMAC_IER) PDelay Request Frame Received */
+#define GMAC_IER_PDRQFR             (_U_(0x1) << GMAC_IER_PDRQFR_Pos)
+#define GMAC_IER_PDRSFR_Pos         23           /**< \brief (GMAC_IER) PDelay Response Frame Received */
+#define GMAC_IER_PDRSFR             (_U_(0x1) << GMAC_IER_PDRSFR_Pos)
+#define GMAC_IER_PDRQFT_Pos         24           /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
+#define GMAC_IER_PDRQFT             (_U_(0x1) << GMAC_IER_PDRQFT_Pos)
+#define GMAC_IER_PDRSFT_Pos         25           /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
+#define GMAC_IER_PDRSFT             (_U_(0x1) << GMAC_IER_PDRSFT_Pos)
+#define GMAC_IER_SRI_Pos            26           /**< \brief (GMAC_IER) TSU Seconds Register Increment */
+#define GMAC_IER_SRI                (_U_(0x1) << GMAC_IER_SRI_Pos)
+#define GMAC_IER_WOL_Pos            28           /**< \brief (GMAC_IER) Wake On LAN */
+#define GMAC_IER_WOL                (_U_(0x1) << GMAC_IER_WOL_Pos)
+#define GMAC_IER_TSUCMP_Pos         29           /**< \brief (GMAC_IER) Tsu timer comparison */
+#define GMAC_IER_TSUCMP             (_U_(0x1) << GMAC_IER_TSUCMP_Pos)
+#define GMAC_IER_MASK               _U_(0x37FCFCFF) /**< \brief (GMAC_IER) MASK Register */
+
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) ( /W 32) Interrupt Disable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
+    uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
+    uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
+    uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
+    uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
+    uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded or Late Collision */
+    uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
+    uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
+    uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
+    uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
+    uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
+    uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
+    uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
+    uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
+    uint32_t EXINT:1;          /*!< bit:     15  External Interrupt                 */
+    uint32_t :2;               /*!< bit: 16..17  Reserved                           */
+    uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
+    uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
+    uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
+    uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
+    uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
+    uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
+    uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
+    uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
+    uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t WOL:1;            /*!< bit:     28  Wake On LAN                        */
+    uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IDR_OFFSET             0x02C        /**< \brief (GMAC_IDR offset) Interrupt Disable Register */
+
+#define GMAC_IDR_MFS_Pos            0            /**< \brief (GMAC_IDR) Management Frame Sent */
+#define GMAC_IDR_MFS                (_U_(0x1) << GMAC_IDR_MFS_Pos)
+#define GMAC_IDR_RCOMP_Pos          1            /**< \brief (GMAC_IDR) Receive Complete */
+#define GMAC_IDR_RCOMP              (_U_(0x1) << GMAC_IDR_RCOMP_Pos)
+#define GMAC_IDR_RXUBR_Pos          2            /**< \brief (GMAC_IDR) RX Used Bit Read */
+#define GMAC_IDR_RXUBR              (_U_(0x1) << GMAC_IDR_RXUBR_Pos)
+#define GMAC_IDR_TXUBR_Pos          3            /**< \brief (GMAC_IDR) TX Used Bit Read */
+#define GMAC_IDR_TXUBR              (_U_(0x1) << GMAC_IDR_TXUBR_Pos)
+#define GMAC_IDR_TUR_Pos            4            /**< \brief (GMAC_IDR) Transmit Underrun */
+#define GMAC_IDR_TUR                (_U_(0x1) << GMAC_IDR_TUR_Pos)
+#define GMAC_IDR_RLEX_Pos           5            /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
+#define GMAC_IDR_RLEX               (_U_(0x1) << GMAC_IDR_RLEX_Pos)
+#define GMAC_IDR_TFC_Pos            6            /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IDR_TFC                (_U_(0x1) << GMAC_IDR_TFC_Pos)
+#define GMAC_IDR_TCOMP_Pos          7            /**< \brief (GMAC_IDR) Transmit Complete */
+#define GMAC_IDR_TCOMP              (_U_(0x1) << GMAC_IDR_TCOMP_Pos)
+#define GMAC_IDR_ROVR_Pos           10           /**< \brief (GMAC_IDR) Receive Overrun */
+#define GMAC_IDR_ROVR               (_U_(0x1) << GMAC_IDR_ROVR_Pos)
+#define GMAC_IDR_HRESP_Pos          11           /**< \brief (GMAC_IDR) HRESP Not OK */
+#define GMAC_IDR_HRESP              (_U_(0x1) << GMAC_IDR_HRESP_Pos)
+#define GMAC_IDR_PFNZ_Pos           12           /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IDR_PFNZ               (_U_(0x1) << GMAC_IDR_PFNZ_Pos)
+#define GMAC_IDR_PTZ_Pos            13           /**< \brief (GMAC_IDR) Pause Time Zero */
+#define GMAC_IDR_PTZ                (_U_(0x1) << GMAC_IDR_PTZ_Pos)
+#define GMAC_IDR_PFTR_Pos           14           /**< \brief (GMAC_IDR) Pause Frame Transmitted */
+#define GMAC_IDR_PFTR               (_U_(0x1) << GMAC_IDR_PFTR_Pos)
+#define GMAC_IDR_EXINT_Pos          15           /**< \brief (GMAC_IDR) External Interrupt */
+#define GMAC_IDR_EXINT              (_U_(0x1) << GMAC_IDR_EXINT_Pos)
+#define GMAC_IDR_DRQFR_Pos          18           /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
+#define GMAC_IDR_DRQFR              (_U_(0x1) << GMAC_IDR_DRQFR_Pos)
+#define GMAC_IDR_SFR_Pos            19           /**< \brief (GMAC_IDR) PTP Sync Frame Received */
+#define GMAC_IDR_SFR                (_U_(0x1) << GMAC_IDR_SFR_Pos)
+#define GMAC_IDR_DRQFT_Pos          20           /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
+#define GMAC_IDR_DRQFT              (_U_(0x1) << GMAC_IDR_DRQFT_Pos)
+#define GMAC_IDR_SFT_Pos            21           /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
+#define GMAC_IDR_SFT                (_U_(0x1) << GMAC_IDR_SFT_Pos)
+#define GMAC_IDR_PDRQFR_Pos         22           /**< \brief (GMAC_IDR) PDelay Request Frame Received */
+#define GMAC_IDR_PDRQFR             (_U_(0x1) << GMAC_IDR_PDRQFR_Pos)
+#define GMAC_IDR_PDRSFR_Pos         23           /**< \brief (GMAC_IDR) PDelay Response Frame Received */
+#define GMAC_IDR_PDRSFR             (_U_(0x1) << GMAC_IDR_PDRSFR_Pos)
+#define GMAC_IDR_PDRQFT_Pos         24           /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
+#define GMAC_IDR_PDRQFT             (_U_(0x1) << GMAC_IDR_PDRQFT_Pos)
+#define GMAC_IDR_PDRSFT_Pos         25           /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
+#define GMAC_IDR_PDRSFT             (_U_(0x1) << GMAC_IDR_PDRSFT_Pos)
+#define GMAC_IDR_SRI_Pos            26           /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
+#define GMAC_IDR_SRI                (_U_(0x1) << GMAC_IDR_SRI_Pos)
+#define GMAC_IDR_WOL_Pos            28           /**< \brief (GMAC_IDR) Wake On LAN */
+#define GMAC_IDR_WOL                (_U_(0x1) << GMAC_IDR_WOL_Pos)
+#define GMAC_IDR_TSUCMP_Pos         29           /**< \brief (GMAC_IDR) Tsu timer comparison */
+#define GMAC_IDR_TSUCMP             (_U_(0x1) << GMAC_IDR_TSUCMP_Pos)
+#define GMAC_IDR_MASK               _U_(0x37FCFCFF) /**< \brief (GMAC_IDR) MASK Register */
+
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) (R/  32) Interrupt Mask Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
+    uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
+    uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
+    uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
+    uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
+    uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded               */
+    uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
+    uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
+    uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
+    uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
+    uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
+    uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
+    uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
+    uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
+    uint32_t EXINT:1;          /*!< bit:     15  External Interrupt                 */
+    uint32_t :2;               /*!< bit: 16..17  Reserved                           */
+    uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
+    uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
+    uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
+    uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
+    uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
+    uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
+    uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
+    uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
+    uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t WOL:1;            /*!< bit:     28  Wake On Lan                        */
+    uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IMR_OFFSET             0x030        /**< \brief (GMAC_IMR offset) Interrupt Mask Register */
+#define GMAC_IMR_RESETVALUE         _U_(0x3FFFFFFF) /**< \brief (GMAC_IMR reset_value) Interrupt Mask Register */
+
+#define GMAC_IMR_MFS_Pos            0            /**< \brief (GMAC_IMR) Management Frame Sent */
+#define GMAC_IMR_MFS                (_U_(0x1) << GMAC_IMR_MFS_Pos)
+#define GMAC_IMR_RCOMP_Pos          1            /**< \brief (GMAC_IMR) Receive Complete */
+#define GMAC_IMR_RCOMP              (_U_(0x1) << GMAC_IMR_RCOMP_Pos)
+#define GMAC_IMR_RXUBR_Pos          2            /**< \brief (GMAC_IMR) RX Used Bit Read */
+#define GMAC_IMR_RXUBR              (_U_(0x1) << GMAC_IMR_RXUBR_Pos)
+#define GMAC_IMR_TXUBR_Pos          3            /**< \brief (GMAC_IMR) TX Used Bit Read */
+#define GMAC_IMR_TXUBR              (_U_(0x1) << GMAC_IMR_TXUBR_Pos)
+#define GMAC_IMR_TUR_Pos            4            /**< \brief (GMAC_IMR) Transmit Underrun */
+#define GMAC_IMR_TUR                (_U_(0x1) << GMAC_IMR_TUR_Pos)
+#define GMAC_IMR_RLEX_Pos           5            /**< \brief (GMAC_IMR) Retry Limit Exceeded */
+#define GMAC_IMR_RLEX               (_U_(0x1) << GMAC_IMR_RLEX_Pos)
+#define GMAC_IMR_TFC_Pos            6            /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IMR_TFC                (_U_(0x1) << GMAC_IMR_TFC_Pos)
+#define GMAC_IMR_TCOMP_Pos          7            /**< \brief (GMAC_IMR) Transmit Complete */
+#define GMAC_IMR_TCOMP              (_U_(0x1) << GMAC_IMR_TCOMP_Pos)
+#define GMAC_IMR_ROVR_Pos           10           /**< \brief (GMAC_IMR) Receive Overrun */
+#define GMAC_IMR_ROVR               (_U_(0x1) << GMAC_IMR_ROVR_Pos)
+#define GMAC_IMR_HRESP_Pos          11           /**< \brief (GMAC_IMR) HRESP Not OK */
+#define GMAC_IMR_HRESP              (_U_(0x1) << GMAC_IMR_HRESP_Pos)
+#define GMAC_IMR_PFNZ_Pos           12           /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IMR_PFNZ               (_U_(0x1) << GMAC_IMR_PFNZ_Pos)
+#define GMAC_IMR_PTZ_Pos            13           /**< \brief (GMAC_IMR) Pause Time Zero */
+#define GMAC_IMR_PTZ                (_U_(0x1) << GMAC_IMR_PTZ_Pos)
+#define GMAC_IMR_PFTR_Pos           14           /**< \brief (GMAC_IMR) Pause Frame Transmitted */
+#define GMAC_IMR_PFTR               (_U_(0x1) << GMAC_IMR_PFTR_Pos)
+#define GMAC_IMR_EXINT_Pos          15           /**< \brief (GMAC_IMR) External Interrupt */
+#define GMAC_IMR_EXINT              (_U_(0x1) << GMAC_IMR_EXINT_Pos)
+#define GMAC_IMR_DRQFR_Pos          18           /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
+#define GMAC_IMR_DRQFR              (_U_(0x1) << GMAC_IMR_DRQFR_Pos)
+#define GMAC_IMR_SFR_Pos            19           /**< \brief (GMAC_IMR) PTP Sync Frame Received */
+#define GMAC_IMR_SFR                (_U_(0x1) << GMAC_IMR_SFR_Pos)
+#define GMAC_IMR_DRQFT_Pos          20           /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
+#define GMAC_IMR_DRQFT              (_U_(0x1) << GMAC_IMR_DRQFT_Pos)
+#define GMAC_IMR_SFT_Pos            21           /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
+#define GMAC_IMR_SFT                (_U_(0x1) << GMAC_IMR_SFT_Pos)
+#define GMAC_IMR_PDRQFR_Pos         22           /**< \brief (GMAC_IMR) PDelay Request Frame Received */
+#define GMAC_IMR_PDRQFR             (_U_(0x1) << GMAC_IMR_PDRQFR_Pos)
+#define GMAC_IMR_PDRSFR_Pos         23           /**< \brief (GMAC_IMR) PDelay Response Frame Received */
+#define GMAC_IMR_PDRSFR             (_U_(0x1) << GMAC_IMR_PDRSFR_Pos)
+#define GMAC_IMR_PDRQFT_Pos         24           /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
+#define GMAC_IMR_PDRQFT             (_U_(0x1) << GMAC_IMR_PDRQFT_Pos)
+#define GMAC_IMR_PDRSFT_Pos         25           /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
+#define GMAC_IMR_PDRSFT             (_U_(0x1) << GMAC_IMR_PDRSFT_Pos)
+#define GMAC_IMR_SRI_Pos            26           /**< \brief (GMAC_IMR) TSU Seconds Register Increment */
+#define GMAC_IMR_SRI                (_U_(0x1) << GMAC_IMR_SRI_Pos)
+#define GMAC_IMR_WOL_Pos            28           /**< \brief (GMAC_IMR) Wake On Lan */
+#define GMAC_IMR_WOL                (_U_(0x1) << GMAC_IMR_WOL_Pos)
+#define GMAC_IMR_TSUCMP_Pos         29           /**< \brief (GMAC_IMR) Tsu timer comparison */
+#define GMAC_IMR_TSUCMP             (_U_(0x1) << GMAC_IMR_TSUCMP_Pos)
+#define GMAC_IMR_MASK               _U_(0x37FCFCFF) /**< \brief (GMAC_IMR) MASK Register */
+
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) (R/W 32) PHY Maintenance Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:16;          /*!< bit:  0..15  PHY Data                           */
+    uint32_t WTN:2;            /*!< bit: 16..17  Write Ten                          */
+    uint32_t REGA:5;           /*!< bit: 18..22  Register Address                   */
+    uint32_t PHYA:5;           /*!< bit: 23..27  PHY Address                        */
+    uint32_t OP:2;             /*!< bit: 28..29  Operation                          */
+    uint32_t CLTTO:1;          /*!< bit:     30  Clause 22 Operation                */
+    uint32_t WZO:1;            /*!< bit:     31  Write ZERO                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_MAN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MAN_OFFSET             0x034        /**< \brief (GMAC_MAN offset) PHY Maintenance Register */
+#define GMAC_MAN_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_MAN reset_value) PHY Maintenance Register */
+
+#define GMAC_MAN_DATA_Pos           0            /**< \brief (GMAC_MAN) PHY Data */
+#define GMAC_MAN_DATA_Msk           (_U_(0xFFFF) << GMAC_MAN_DATA_Pos)
+#define GMAC_MAN_DATA(value)        (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))
+#define GMAC_MAN_WTN_Pos            16           /**< \brief (GMAC_MAN) Write Ten */
+#define GMAC_MAN_WTN_Msk            (_U_(0x3) << GMAC_MAN_WTN_Pos)
+#define GMAC_MAN_WTN(value)         (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))
+#define GMAC_MAN_REGA_Pos           18           /**< \brief (GMAC_MAN) Register Address */
+#define GMAC_MAN_REGA_Msk           (_U_(0x1F) << GMAC_MAN_REGA_Pos)
+#define GMAC_MAN_REGA(value)        (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))
+#define GMAC_MAN_PHYA_Pos           23           /**< \brief (GMAC_MAN) PHY Address */
+#define GMAC_MAN_PHYA_Msk           (_U_(0x1F) << GMAC_MAN_PHYA_Pos)
+#define GMAC_MAN_PHYA(value)        (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))
+#define GMAC_MAN_OP_Pos             28           /**< \brief (GMAC_MAN) Operation */
+#define GMAC_MAN_OP_Msk             (_U_(0x3) << GMAC_MAN_OP_Pos)
+#define GMAC_MAN_OP(value)          (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))
+#define GMAC_MAN_CLTTO_Pos          30           /**< \brief (GMAC_MAN) Clause 22 Operation */
+#define GMAC_MAN_CLTTO              (_U_(0x1) << GMAC_MAN_CLTTO_Pos)
+#define GMAC_MAN_WZO_Pos            31           /**< \brief (GMAC_MAN) Write ZERO */
+#define GMAC_MAN_WZO                (_U_(0x1) << GMAC_MAN_WZO_Pos)
+#define GMAC_MAN_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_MAN) MASK Register */
+
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) (R/  32) Received Pause Quantum Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RPQ:16;           /*!< bit:  0..15  Received Pause Quantum             */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RPQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RPQ_OFFSET             0x038        /**< \brief (GMAC_RPQ offset) Received Pause Quantum Register */
+#define GMAC_RPQ_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_RPQ reset_value) Received Pause Quantum Register */
+
+#define GMAC_RPQ_RPQ_Pos            0            /**< \brief (GMAC_RPQ) Received Pause Quantum */
+#define GMAC_RPQ_RPQ_Msk            (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos)
+#define GMAC_RPQ_RPQ(value)         (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos))
+#define GMAC_RPQ_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_RPQ) MASK Register */
+
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) (R/W 32) Transmit Pause Quantum Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TPQ:16;           /*!< bit:  0..15  Transmit Pause Quantum             */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TPQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPQ_OFFSET             0x03C        /**< \brief (GMAC_TPQ offset) Transmit Pause Quantum Register */
+#define GMAC_TPQ_RESETVALUE         _U_(0x0000FFFF) /**< \brief (GMAC_TPQ reset_value) Transmit Pause Quantum Register */
+
+#define GMAC_TPQ_TPQ_Pos            0            /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
+#define GMAC_TPQ_TPQ_Msk            (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos)
+#define GMAC_TPQ_TPQ(value)         (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))
+#define GMAC_TPQ_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_TPQ) MASK Register */
+
+/* -------- GMAC_TPSF : (GMAC Offset: 0x040) (R/W 32) TX partial store and forward Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TPB1ADR:10;       /*!< bit:  0.. 9  TX packet buffer address           */
+    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
+    uint32_t ENTXP:1;          /*!< bit:     31  Enable TX partial store and forward operation */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TPSF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPSF_OFFSET            0x040        /**< \brief (GMAC_TPSF offset) TX partial store and forward Register */
+#define GMAC_TPSF_RESETVALUE        _U_(0x000003FF) /**< \brief (GMAC_TPSF reset_value) TX partial store and forward Register */
+
+#define GMAC_TPSF_TPB1ADR_Pos       0            /**< \brief (GMAC_TPSF) TX packet buffer address */
+#define GMAC_TPSF_TPB1ADR_Msk       (_U_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos)
+#define GMAC_TPSF_TPB1ADR(value)    (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))
+#define GMAC_TPSF_ENTXP_Pos         31           /**< \brief (GMAC_TPSF) Enable TX partial store and forward operation */
+#define GMAC_TPSF_ENTXP             (_U_(0x1) << GMAC_TPSF_ENTXP_Pos)
+#define GMAC_TPSF_MASK              _U_(0x800003FF) /**< \brief (GMAC_TPSF) MASK Register */
+
+/* -------- GMAC_RPSF : (GMAC Offset: 0x044) (R/W 32) RX partial store and forward Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RPB1ADR:10;       /*!< bit:  0.. 9  RX packet buffer address           */
+    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
+    uint32_t ENRXP:1;          /*!< bit:     31  Enable RX partial store and forward operation */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RPSF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RPSF_OFFSET            0x044        /**< \brief (GMAC_RPSF offset) RX partial store and forward Register */
+#define GMAC_RPSF_RESETVALUE        _U_(0x000003FF) /**< \brief (GMAC_RPSF reset_value) RX partial store and forward Register */
+
+#define GMAC_RPSF_RPB1ADR_Pos       0            /**< \brief (GMAC_RPSF) RX packet buffer address */
+#define GMAC_RPSF_RPB1ADR_Msk       (_U_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos)
+#define GMAC_RPSF_RPB1ADR(value)    (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))
+#define GMAC_RPSF_ENRXP_Pos         31           /**< \brief (GMAC_RPSF) Enable RX partial store and forward operation */
+#define GMAC_RPSF_ENRXP             (_U_(0x1) << GMAC_RPSF_ENRXP_Pos)
+#define GMAC_RPSF_MASK              _U_(0x800003FF) /**< \brief (GMAC_RPSF) MASK Register */
+
+/* -------- GMAC_RJFML : (GMAC Offset: 0x048) (R/W 32) RX Jumbo Frame Max Length Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FML:14;           /*!< bit:  0..13  Frame Max Length                   */
+    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RJFML_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RJFML_OFFSET           0x048        /**< \brief (GMAC_RJFML offset) RX Jumbo Frame Max Length Register */
+#define GMAC_RJFML_RESETVALUE       _U_(0x00003FFF) /**< \brief (GMAC_RJFML reset_value) RX Jumbo Frame Max Length Register */
+
+#define GMAC_RJFML_FML_Pos          0            /**< \brief (GMAC_RJFML) Frame Max Length */
+#define GMAC_RJFML_FML_Msk          (_U_(0x3FFF) << GMAC_RJFML_FML_Pos)
+#define GMAC_RJFML_FML(value)       (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))
+#define GMAC_RJFML_MASK             _U_(0x00003FFF) /**< \brief (GMAC_RJFML) MASK Register */
+
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) (R/W 32) Hash Register Bottom [31:0] -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Hash Address                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_HRB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_HRB_OFFSET             0x080        /**< \brief (GMAC_HRB offset) Hash Register Bottom [31:0] */
+#define GMAC_HRB_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_HRB reset_value) Hash Register Bottom [31:0] */
+
+#define GMAC_HRB_ADDR_Pos           0            /**< \brief (GMAC_HRB) Hash Address */
+#define GMAC_HRB_ADDR_Msk           (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos)
+#define GMAC_HRB_ADDR(value)        (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))
+#define GMAC_HRB_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_HRB) MASK Register */
+
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) (R/W 32) Hash Register Top [63:32] -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Hash Address                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_HRT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_HRT_OFFSET             0x084        /**< \brief (GMAC_HRT offset) Hash Register Top [63:32] */
+#define GMAC_HRT_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_HRT reset_value) Hash Register Top [63:32] */
+
+#define GMAC_HRT_ADDR_Pos           0            /**< \brief (GMAC_HRT) Hash Address */
+#define GMAC_HRT_ADDR_Msk           (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos)
+#define GMAC_HRT_ADDR(value)        (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))
+#define GMAC_HRT_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_HRT) MASK Register */
+
+/* -------- GMAC_SAB : (GMAC Offset: 0x088) (R/W 32) SA Specific Address Bottom [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Specific Address 1                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SAB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAB_OFFSET             0x088        /**< \brief (GMAC_SAB offset) Specific Address Bottom [31:0] Register */
+#define GMAC_SAB_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_SAB reset_value) Specific Address Bottom [31:0] Register */
+
+#define GMAC_SAB_ADDR_Pos           0            /**< \brief (GMAC_SAB) Specific Address 1 */
+#define GMAC_SAB_ADDR_Msk           (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos)
+#define GMAC_SAB_ADDR(value)        (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))
+#define GMAC_SAB_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_SAB) MASK Register */
+
+/* -------- GMAC_SAT : (GMAC Offset: 0x08C) (R/W 32) SA Specific Address Top [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:16;          /*!< bit:  0..15  Specific Address 1                 */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAT_OFFSET             0x08C        /**< \brief (GMAC_SAT offset) Specific Address Top [47:32] Register */
+#define GMAC_SAT_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_SAT reset_value) Specific Address Top [47:32] Register */
+
+#define GMAC_SAT_ADDR_Pos           0            /**< \brief (GMAC_SAT) Specific Address 1 */
+#define GMAC_SAT_ADDR_Msk           (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos)
+#define GMAC_SAT_ADDR(value)        (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))
+#define GMAC_SAT_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_SAT) MASK Register */
+
+/* -------- GMAC_TIDM : (GMAC Offset: 0x0A8) (R/W 32) Type ID Match Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TID:16;           /*!< bit:  0..15  Type ID Match 1                    */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TIDM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TIDM_OFFSET            0x0A8        /**< \brief (GMAC_TIDM offset) Type ID Match Register */
+#define GMAC_TIDM_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_TIDM reset_value) Type ID Match Register */
+
+#define GMAC_TIDM_TID_Pos           0            /**< \brief (GMAC_TIDM) Type ID Match 1 */
+#define GMAC_TIDM_TID_Msk           (_U_(0xFFFF) << GMAC_TIDM_TID_Pos)
+#define GMAC_TIDM_TID(value)        (GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))
+#define GMAC_TIDM_MASK              _U_(0x0000FFFF) /**< \brief (GMAC_TIDM) MASK Register */
+
+/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) (R/W 32) Wake on LAN -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IP:16;            /*!< bit:  0..15  IP address                         */
+    uint32_t MAG:1;            /*!< bit:     16  Event enable                       */
+    uint32_t ARP:1;            /*!< bit:     17  LAN ARP req                        */
+    uint32_t SA1:1;            /*!< bit:     18  WOL specific address reg 1         */
+    uint32_t MTI:1;            /*!< bit:     19  WOL LAN multicast                  */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_WOL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_WOL_OFFSET             0x0B8        /**< \brief (GMAC_WOL offset) Wake on LAN */
+#define GMAC_WOL_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_WOL reset_value) Wake on LAN */
+
+#define GMAC_WOL_IP_Pos             0            /**< \brief (GMAC_WOL) IP address */
+#define GMAC_WOL_IP_Msk             (_U_(0xFFFF) << GMAC_WOL_IP_Pos)
+#define GMAC_WOL_IP(value)          (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))
+#define GMAC_WOL_MAG_Pos            16           /**< \brief (GMAC_WOL) Event enable */
+#define GMAC_WOL_MAG                (_U_(0x1) << GMAC_WOL_MAG_Pos)
+#define GMAC_WOL_ARP_Pos            17           /**< \brief (GMAC_WOL) LAN ARP req */
+#define GMAC_WOL_ARP                (_U_(0x1) << GMAC_WOL_ARP_Pos)
+#define GMAC_WOL_SA1_Pos            18           /**< \brief (GMAC_WOL) WOL specific address reg 1 */
+#define GMAC_WOL_SA1                (_U_(0x1) << GMAC_WOL_SA1_Pos)
+#define GMAC_WOL_MTI_Pos            19           /**< \brief (GMAC_WOL) WOL LAN multicast */
+#define GMAC_WOL_MTI                (_U_(0x1) << GMAC_WOL_MTI_Pos)
+#define GMAC_WOL_MASK               _U_(0x000FFFFF) /**< \brief (GMAC_WOL) MASK Register */
+
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) (R/W 32) IPG Stretch Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FL:16;            /*!< bit:  0..15  Frame Length                       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_IPGS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IPGS_OFFSET            0x0BC        /**< \brief (GMAC_IPGS offset) IPG Stretch Register */
+#define GMAC_IPGS_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_IPGS reset_value) IPG Stretch Register */
+
+#define GMAC_IPGS_FL_Pos            0            /**< \brief (GMAC_IPGS) Frame Length */
+#define GMAC_IPGS_FL_Msk            (_U_(0xFFFF) << GMAC_IPGS_FL_Pos)
+#define GMAC_IPGS_FL(value)         (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))
+#define GMAC_IPGS_MASK              _U_(0x0000FFFF) /**< \brief (GMAC_IPGS) MASK Register */
+
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) (R/W 32) Stacked VLAN Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t VLAN_TYPE:16;     /*!< bit:  0..15  User Defined VLAN_TYPE Field       */
+    uint32_t :15;              /*!< bit: 16..30  Reserved                           */
+    uint32_t ESVLAN:1;         /*!< bit:     31  Enable Stacked VLAN Processing Mode */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SVLAN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SVLAN_OFFSET           0x0C0        /**< \brief (GMAC_SVLAN offset) Stacked VLAN Register */
+#define GMAC_SVLAN_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_SVLAN reset_value) Stacked VLAN Register */
+
+#define GMAC_SVLAN_VLAN_TYPE_Pos    0            /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
+#define GMAC_SVLAN_VLAN_TYPE_Msk    (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos)
+#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))
+#define GMAC_SVLAN_ESVLAN_Pos       31           /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
+#define GMAC_SVLAN_ESVLAN           (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos)
+#define GMAC_SVLAN_MASK             _U_(0x8000FFFF) /**< \brief (GMAC_SVLAN) MASK Register */
+
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) (R/W 32) Transmit PFC Pause Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PEV:8;            /*!< bit:  0.. 7  Priority Enable Vector             */
+    uint32_t PQ:8;             /*!< bit:  8..15  Pause Quantum                      */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TPFCP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TPFCP_OFFSET           0x0C4        /**< \brief (GMAC_TPFCP offset) Transmit PFC Pause Register */
+#define GMAC_TPFCP_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_TPFCP reset_value) Transmit PFC Pause Register */
+
+#define GMAC_TPFCP_PEV_Pos          0            /**< \brief (GMAC_TPFCP) Priority Enable Vector */
+#define GMAC_TPFCP_PEV_Msk          (_U_(0xFF) << GMAC_TPFCP_PEV_Pos)
+#define GMAC_TPFCP_PEV(value)       (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))
+#define GMAC_TPFCP_PQ_Pos           8            /**< \brief (GMAC_TPFCP) Pause Quantum */
+#define GMAC_TPFCP_PQ_Msk           (_U_(0xFF) << GMAC_TPFCP_PQ_Pos)
+#define GMAC_TPFCP_PQ(value)        (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))
+#define GMAC_TPFCP_MASK             _U_(0x0000FFFF) /**< \brief (GMAC_TPFCP) MASK Register */
+
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Specific Address 1 Mask            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SAMB1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAMB1_OFFSET           0x0C8        /**< \brief (GMAC_SAMB1 offset) Specific Address 1 Mask Bottom [31:0] Register */
+#define GMAC_SAMB1_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_SAMB1 reset_value) Specific Address 1 Mask Bottom [31:0] Register */
+
+#define GMAC_SAMB1_ADDR_Pos         0            /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
+#define GMAC_SAMB1_ADDR_Msk         (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos)
+#define GMAC_SAMB1_ADDR(value)      (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))
+#define GMAC_SAMB1_MASK             _U_(0xFFFFFFFF) /**< \brief (GMAC_SAMB1) MASK Register */
+
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:16;          /*!< bit:  0..15  Specific Address 1 Mask            */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SAMT1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SAMT1_OFFSET           0x0CC        /**< \brief (GMAC_SAMT1 offset) Specific Address 1 Mask Top [47:32] Register */
+#define GMAC_SAMT1_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_SAMT1 reset_value) Specific Address 1 Mask Top [47:32] Register */
+
+#define GMAC_SAMT1_ADDR_Pos         0            /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
+#define GMAC_SAMT1_ADDR_Msk         (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos)
+#define GMAC_SAMT1_ADDR(value)      (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))
+#define GMAC_SAMT1_MASK             _U_(0x0000FFFF) /**< \brief (GMAC_SAMT1) MASK Register */
+
+/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NANOSEC:21;       /*!< bit:  0..20  1588 Timer Nanosecond comparison value */
+    uint32_t :11;              /*!< bit: 21..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_NSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_NSC_OFFSET             0x0DC        /**< \brief (GMAC_NSC offset) Tsu timer comparison nanoseconds Register */
+#define GMAC_NSC_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_NSC reset_value) Tsu timer comparison nanoseconds Register */
+
+#define GMAC_NSC_NANOSEC_Pos        0            /**< \brief (GMAC_NSC) 1588 Timer Nanosecond comparison value */
+#define GMAC_NSC_NANOSEC_Msk        (_U_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos)
+#define GMAC_NSC_NANOSEC(value)     (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))
+#define GMAC_NSC_MASK               _U_(0x001FFFFF) /**< \brief (GMAC_NSC) MASK Register */
+
+/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) (R/W 32) Tsu timer second comparison Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SEC:32;           /*!< bit:  0..31  1588 Timer Second comparison value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SCL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCL_OFFSET             0x0E0        /**< \brief (GMAC_SCL offset) Tsu timer second comparison Register */
+#define GMAC_SCL_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_SCL reset_value) Tsu timer second comparison Register */
+
+#define GMAC_SCL_SEC_Pos            0            /**< \brief (GMAC_SCL) 1588 Timer Second comparison value */
+#define GMAC_SCL_SEC_Msk            (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos)
+#define GMAC_SCL_SEC(value)         (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))
+#define GMAC_SCL_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_SCL) MASK Register */
+
+/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) (R/W 32) Tsu timer second comparison Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SEC:16;           /*!< bit:  0..15  1588 Timer Second comparison value */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCH_OFFSET             0x0E4        /**< \brief (GMAC_SCH offset) Tsu timer second comparison Register */
+#define GMAC_SCH_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_SCH reset_value) Tsu timer second comparison Register */
+
+#define GMAC_SCH_SEC_Pos            0            /**< \brief (GMAC_SCH) 1588 Timer Second comparison value */
+#define GMAC_SCH_SEC_Msk            (_U_(0xFFFF) << GMAC_SCH_SEC_Pos)
+#define GMAC_SCH_SEC(value)         (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))
+#define GMAC_SCH_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_SCH) MASK Register */
+
+/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) (R/  32) PTP Event Frame Transmitted Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EFTSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTSH_OFFSET           0x0E8        /**< \brief (GMAC_EFTSH offset) PTP Event Frame Transmitted Seconds High Register */
+#define GMAC_EFTSH_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_EFTSH reset_value) PTP Event Frame Transmitted Seconds High Register */
+
+#define GMAC_EFTSH_RUD_Pos          0            /**< \brief (GMAC_EFTSH) Register Update */
+#define GMAC_EFTSH_RUD_Msk          (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos)
+#define GMAC_EFTSH_RUD(value)       (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos))
+#define GMAC_EFTSH_MASK             _U_(0x0000FFFF) /**< \brief (GMAC_EFTSH) MASK Register */
+
+/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) (R/  32) PTP Event Frame Received Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EFRSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRSH_OFFSET           0x0EC        /**< \brief (GMAC_EFRSH offset) PTP Event Frame Received Seconds High Register */
+#define GMAC_EFRSH_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_EFRSH reset_value) PTP Event Frame Received Seconds High Register */
+
+#define GMAC_EFRSH_RUD_Pos          0            /**< \brief (GMAC_EFRSH) Register Update */
+#define GMAC_EFRSH_RUD_Msk          (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos)
+#define GMAC_EFRSH_RUD(value)       (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos))
+#define GMAC_EFRSH_MASK             _U_(0x0000FFFF) /**< \brief (GMAC_EFRSH) MASK Register */
+
+/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) (R/  32) PTP Peer Event Frame Transmitted Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PEFTSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTSH_OFFSET          0x0F0        /**< \brief (GMAC_PEFTSH offset) PTP Peer Event Frame Transmitted Seconds High Register */
+#define GMAC_PEFTSH_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_PEFTSH reset_value) PTP Peer Event Frame Transmitted Seconds High Register */
+
+#define GMAC_PEFTSH_RUD_Pos         0            /**< \brief (GMAC_PEFTSH) Register Update */
+#define GMAC_PEFTSH_RUD_Msk         (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos)
+#define GMAC_PEFTSH_RUD(value)      (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos))
+#define GMAC_PEFTSH_MASK            _U_(0x0000FFFF) /**< \brief (GMAC_PEFTSH) MASK Register */
+
+/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) (R/  32) PTP Peer Event Frame Received Seconds High Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PEFRSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRSH_OFFSET          0x0F4        /**< \brief (GMAC_PEFRSH offset) PTP Peer Event Frame Received Seconds High Register */
+#define GMAC_PEFRSH_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_PEFRSH reset_value) PTP Peer Event Frame Received Seconds High Register */
+
+#define GMAC_PEFRSH_RUD_Pos         0            /**< \brief (GMAC_PEFRSH) Register Update */
+#define GMAC_PEFRSH_RUD_Msk         (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos)
+#define GMAC_PEFRSH_RUD(value)      (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos))
+#define GMAC_PEFRSH_MASK            _U_(0x0000FFFF) /**< \brief (GMAC_PEFRSH) MASK Register */
+
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/  32) Octets Transmitted [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TXO:32;           /*!< bit:  0..31  Transmitted Octets                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_OTLO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OTLO_OFFSET            0x100        /**< \brief (GMAC_OTLO offset) Octets Transmitted [31:0] Register */
+#define GMAC_OTLO_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_OTLO reset_value) Octets Transmitted [31:0] Register */
+
+#define GMAC_OTLO_TXO_Pos           0            /**< \brief (GMAC_OTLO) Transmitted Octets */
+#define GMAC_OTLO_TXO_Msk           (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos)
+#define GMAC_OTLO_TXO(value)        (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos))
+#define GMAC_OTLO_MASK              _U_(0xFFFFFFFF) /**< \brief (GMAC_OTLO) MASK Register */
+
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/  32) Octets Transmitted [47:32] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TXO:16;           /*!< bit:  0..15  Transmitted Octets                 */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_OTHI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OTHI_OFFSET            0x104        /**< \brief (GMAC_OTHI offset) Octets Transmitted [47:32] Register */
+#define GMAC_OTHI_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_OTHI reset_value) Octets Transmitted [47:32] Register */
+
+#define GMAC_OTHI_TXO_Pos           0            /**< \brief (GMAC_OTHI) Transmitted Octets */
+#define GMAC_OTHI_TXO_Msk           (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos)
+#define GMAC_OTHI_TXO(value)        (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos))
+#define GMAC_OTHI_MASK              _U_(0x0000FFFF) /**< \brief (GMAC_OTHI) MASK Register */
+
+/* -------- GMAC_FT : (GMAC Offset: 0x108) (R/  32) Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FTX:32;           /*!< bit:  0..31  Frames Transmitted without Error   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_FT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FT_OFFSET              0x108        /**< \brief (GMAC_FT offset) Frames Transmitted Register */
+#define GMAC_FT_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_FT reset_value) Frames Transmitted Register */
+
+#define GMAC_FT_FTX_Pos             0            /**< \brief (GMAC_FT) Frames Transmitted without Error */
+#define GMAC_FT_FTX_Msk             (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos)
+#define GMAC_FT_FTX(value)          (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos))
+#define GMAC_FT_MASK                _U_(0xFFFFFFFF) /**< \brief (GMAC_FT) MASK Register */
+
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) (R/  32) Broadcast Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BFTX:32;          /*!< bit:  0..31  Broadcast Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_BCFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BCFT_OFFSET            0x10C        /**< \brief (GMAC_BCFT offset) Broadcast Frames Transmitted Register */
+#define GMAC_BCFT_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_BCFT reset_value) Broadcast Frames Transmitted Register */
+
+#define GMAC_BCFT_BFTX_Pos          0            /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
+#define GMAC_BCFT_BFTX_Msk          (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos)
+#define GMAC_BCFT_BFTX(value)       (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos))
+#define GMAC_BCFT_MASK              _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFT) MASK Register */
+
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/  32) Multicast Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MFTX:32;          /*!< bit:  0..31  Multicast Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_MFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MFT_OFFSET             0x110        /**< \brief (GMAC_MFT offset) Multicast Frames Transmitted Register */
+#define GMAC_MFT_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_MFT reset_value) Multicast Frames Transmitted Register */
+
+#define GMAC_MFT_MFTX_Pos           0            /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
+#define GMAC_MFT_MFTX_Msk           (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos)
+#define GMAC_MFT_MFTX(value)        (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos))
+#define GMAC_MFT_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_MFT) MASK Register */
+
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/  32) Pause Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PFTX:16;          /*!< bit:  0..15  Pause Frames Transmitted Register  */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PFT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PFT_OFFSET             0x114        /**< \brief (GMAC_PFT offset) Pause Frames Transmitted Register */
+#define GMAC_PFT_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_PFT reset_value) Pause Frames Transmitted Register */
+
+#define GMAC_PFT_PFTX_Pos           0            /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
+#define GMAC_PFT_PFTX_Msk           (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos)
+#define GMAC_PFT_PFTX(value)        (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos))
+#define GMAC_PFT_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_PFT) MASK Register */
+
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/  32) 64 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  64 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_BFT64_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BFT64_OFFSET           0x118        /**< \brief (GMAC_BFT64 offset) 64 Byte Frames Transmitted Register */
+#define GMAC_BFT64_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_BFT64 reset_value) 64 Byte Frames Transmitted Register */
+
+#define GMAC_BFT64_NFTX_Pos         0            /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
+#define GMAC_BFT64_NFTX_Msk         (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos)
+#define GMAC_BFT64_NFTX(value)      (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos))
+#define GMAC_BFT64_MASK             _U_(0xFFFFFFFF) /**< \brief (GMAC_BFT64) MASK Register */
+
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) (R/  32) 65 to 127 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  65 to 127 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFT127_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT127_OFFSET         0x11C        /**< \brief (GMAC_TBFT127 offset) 65 to 127 Byte Frames Transmitted Register */
+#define GMAC_TBFT127_RESETVALUE     _U_(0x00000000) /**< \brief (GMAC_TBFT127 reset_value) 65 to 127 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT127_NFTX_Pos       0            /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
+#define GMAC_TBFT127_NFTX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos)
+#define GMAC_TBFT127_NFTX(value)    (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos))
+#define GMAC_TBFT127_MASK           _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT127) MASK Register */
+
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/  32) 128 to 255 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  128 to 255 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFT255_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT255_OFFSET         0x120        /**< \brief (GMAC_TBFT255 offset) 128 to 255 Byte Frames Transmitted Register */
+#define GMAC_TBFT255_RESETVALUE     _U_(0x00000000) /**< \brief (GMAC_TBFT255 reset_value) 128 to 255 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT255_NFTX_Pos       0            /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
+#define GMAC_TBFT255_NFTX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos)
+#define GMAC_TBFT255_NFTX(value)    (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos))
+#define GMAC_TBFT255_MASK           _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT255) MASK Register */
+
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/  32) 256 to 511 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  256 to 511 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFT511_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT511_OFFSET         0x124        /**< \brief (GMAC_TBFT511 offset) 256 to 511 Byte Frames Transmitted Register */
+#define GMAC_TBFT511_RESETVALUE     _U_(0x00000000) /**< \brief (GMAC_TBFT511 reset_value) 256 to 511 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT511_NFTX_Pos       0            /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
+#define GMAC_TBFT511_NFTX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos)
+#define GMAC_TBFT511_NFTX(value)    (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos))
+#define GMAC_TBFT511_MASK           _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT511) MASK Register */
+
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/  32) 512 to 1023 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  512 to 1023 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFT1023_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT1023_OFFSET        0x128        /**< \brief (GMAC_TBFT1023 offset) 512 to 1023 Byte Frames Transmitted Register */
+#define GMAC_TBFT1023_RESETVALUE    _U_(0x00000000) /**< \brief (GMAC_TBFT1023 reset_value) 512 to 1023 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT1023_NFTX_Pos      0            /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
+#define GMAC_TBFT1023_NFTX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos)
+#define GMAC_TBFT1023_NFTX(value)   (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos))
+#define GMAC_TBFT1023_MASK          _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1023) MASK Register */
+
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) (R/  32) 1024 to 1518 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  1024 to 1518 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFT1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFT1518_OFFSET        0x12C        /**< \brief (GMAC_TBFT1518 offset) 1024 to 1518 Byte Frames Transmitted Register */
+#define GMAC_TBFT1518_RESETVALUE    _U_(0x00000000) /**< \brief (GMAC_TBFT1518 reset_value) 1024 to 1518 Byte Frames Transmitted Register */
+
+#define GMAC_TBFT1518_NFTX_Pos      0            /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
+#define GMAC_TBFT1518_NFTX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos)
+#define GMAC_TBFT1518_NFTX(value)   (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos))
+#define GMAC_TBFT1518_MASK          _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFT1518) MASK Register */
+
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/  32) Greater Than 1518 Byte Frames Transmitted Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFTX:32;          /*!< bit:  0..31  Greater than 1518 Byte Frames Transmitted without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_GTBFT1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_GTBFT1518_OFFSET       0x130        /**< \brief (GMAC_GTBFT1518 offset) Greater Than 1518 Byte Frames Transmitted Register */
+#define GMAC_GTBFT1518_RESETVALUE   _U_(0x00000000) /**< \brief (GMAC_GTBFT1518 reset_value) Greater Than 1518 Byte Frames Transmitted Register */
+
+#define GMAC_GTBFT1518_NFTX_Pos     0            /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
+#define GMAC_GTBFT1518_NFTX_Msk     (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos)
+#define GMAC_GTBFT1518_NFTX(value)  (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos))
+#define GMAC_GTBFT1518_MASK         _U_(0xFFFFFFFF) /**< \brief (GMAC_GTBFT1518) MASK Register */
+
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/  32) Transmit Underruns Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TXUNR:10;         /*!< bit:  0.. 9  Transmit Underruns                 */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TUR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TUR_OFFSET             0x134        /**< \brief (GMAC_TUR offset) Transmit Underruns Register */
+#define GMAC_TUR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_TUR reset_value) Transmit Underruns Register */
+
+#define GMAC_TUR_TXUNR_Pos          0            /**< \brief (GMAC_TUR) Transmit Underruns */
+#define GMAC_TUR_TXUNR_Msk          (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos)
+#define GMAC_TUR_TXUNR(value)       (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos))
+#define GMAC_TUR_MASK               _U_(0x000003FF) /**< \brief (GMAC_TUR) MASK Register */
+
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/  32) Single Collision Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SCOL:18;          /*!< bit:  0..17  Single Collision                   */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_SCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_SCF_OFFSET             0x138        /**< \brief (GMAC_SCF offset) Single Collision Frames Register */
+#define GMAC_SCF_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_SCF reset_value) Single Collision Frames Register */
+
+#define GMAC_SCF_SCOL_Pos           0            /**< \brief (GMAC_SCF) Single Collision */
+#define GMAC_SCF_SCOL_Msk           (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos)
+#define GMAC_SCF_SCOL(value)        (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos))
+#define GMAC_SCF_MASK               _U_(0x0003FFFF) /**< \brief (GMAC_SCF) MASK Register */
+
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) (R/  32) Multiple Collision Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MCOL:18;          /*!< bit:  0..17  Multiple Collision                 */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_MCF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MCF_OFFSET             0x13C        /**< \brief (GMAC_MCF offset) Multiple Collision Frames Register */
+#define GMAC_MCF_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_MCF reset_value) Multiple Collision Frames Register */
+
+#define GMAC_MCF_MCOL_Pos           0            /**< \brief (GMAC_MCF) Multiple Collision */
+#define GMAC_MCF_MCOL_Msk           (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos)
+#define GMAC_MCF_MCOL(value)        (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos))
+#define GMAC_MCF_MASK               _U_(0x0003FFFF) /**< \brief (GMAC_MCF) MASK Register */
+
+/* -------- GMAC_EC : (GMAC Offset: 0x140) (R/  32) Excessive Collisions Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XCOL:10;          /*!< bit:  0.. 9  Excessive Collisions               */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EC_OFFSET              0x140        /**< \brief (GMAC_EC offset) Excessive Collisions Register */
+#define GMAC_EC_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_EC reset_value) Excessive Collisions Register */
+
+#define GMAC_EC_XCOL_Pos            0            /**< \brief (GMAC_EC) Excessive Collisions */
+#define GMAC_EC_XCOL_Msk            (_U_(0x3FF) << GMAC_EC_XCOL_Pos)
+#define GMAC_EC_XCOL(value)         (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos))
+#define GMAC_EC_MASK                _U_(0x000003FF) /**< \brief (GMAC_EC) MASK Register */
+
+/* -------- GMAC_LC : (GMAC Offset: 0x144) (R/  32) Late Collisions Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LCOL:10;          /*!< bit:  0.. 9  Late Collisions                    */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_LC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_LC_OFFSET              0x144        /**< \brief (GMAC_LC offset) Late Collisions Register */
+#define GMAC_LC_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_LC reset_value) Late Collisions Register */
+
+#define GMAC_LC_LCOL_Pos            0            /**< \brief (GMAC_LC) Late Collisions */
+#define GMAC_LC_LCOL_Msk            (_U_(0x3FF) << GMAC_LC_LCOL_Pos)
+#define GMAC_LC_LCOL(value)         (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos))
+#define GMAC_LC_MASK                _U_(0x000003FF) /**< \brief (GMAC_LC) MASK Register */
+
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/  32) Deferred Transmission Frames Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEFT:18;          /*!< bit:  0..17  Deferred Transmission              */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_DTF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_DTF_OFFSET             0x148        /**< \brief (GMAC_DTF offset) Deferred Transmission Frames Register */
+#define GMAC_DTF_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_DTF reset_value) Deferred Transmission Frames Register */
+
+#define GMAC_DTF_DEFT_Pos           0            /**< \brief (GMAC_DTF) Deferred Transmission */
+#define GMAC_DTF_DEFT_Msk           (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos)
+#define GMAC_DTF_DEFT(value)        (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos))
+#define GMAC_DTF_MASK               _U_(0x0003FFFF) /**< \brief (GMAC_DTF) MASK Register */
+
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) (R/  32) Carrier Sense Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CSR:10;           /*!< bit:  0.. 9  Carrier Sense Error                */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_CSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_CSE_OFFSET             0x14C        /**< \brief (GMAC_CSE offset) Carrier Sense Errors Register */
+#define GMAC_CSE_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_CSE reset_value) Carrier Sense Errors Register */
+
+#define GMAC_CSE_CSR_Pos            0            /**< \brief (GMAC_CSE) Carrier Sense Error */
+#define GMAC_CSE_CSR_Msk            (_U_(0x3FF) << GMAC_CSE_CSR_Pos)
+#define GMAC_CSE_CSR(value)         (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos))
+#define GMAC_CSE_MASK               _U_(0x000003FF) /**< \brief (GMAC_CSE) MASK Register */
+
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/  32) Octets Received [31:0] Received -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXO:32;           /*!< bit:  0..31  Received Octets                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_ORLO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ORLO_OFFSET            0x150        /**< \brief (GMAC_ORLO offset) Octets Received [31:0] Received */
+#define GMAC_ORLO_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_ORLO reset_value) Octets Received [31:0] Received */
+
+#define GMAC_ORLO_RXO_Pos           0            /**< \brief (GMAC_ORLO) Received Octets */
+#define GMAC_ORLO_RXO_Msk           (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos)
+#define GMAC_ORLO_RXO(value)        (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos))
+#define GMAC_ORLO_MASK              _U_(0xFFFFFFFF) /**< \brief (GMAC_ORLO) MASK Register */
+
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/  32) Octets Received [47:32] Received -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXO:16;           /*!< bit:  0..15  Received Octets                    */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_ORHI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ORHI_OFFSET            0x154        /**< \brief (GMAC_ORHI offset) Octets Received [47:32] Received */
+#define GMAC_ORHI_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_ORHI reset_value) Octets Received [47:32] Received */
+
+#define GMAC_ORHI_RXO_Pos           0            /**< \brief (GMAC_ORHI) Received Octets */
+#define GMAC_ORHI_RXO_Msk           (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos)
+#define GMAC_ORHI_RXO(value)        (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos))
+#define GMAC_ORHI_MASK              _U_(0x0000FFFF) /**< \brief (GMAC_ORHI) MASK Register */
+
+/* -------- GMAC_FR : (GMAC Offset: 0x158) (R/  32) Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FRX:32;           /*!< bit:  0..31  Frames Received without Error      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_FR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FR_OFFSET              0x158        /**< \brief (GMAC_FR offset) Frames Received Register */
+#define GMAC_FR_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_FR reset_value) Frames Received Register */
+
+#define GMAC_FR_FRX_Pos             0            /**< \brief (GMAC_FR) Frames Received without Error */
+#define GMAC_FR_FRX_Msk             (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos)
+#define GMAC_FR_FRX(value)          (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos))
+#define GMAC_FR_MASK                _U_(0xFFFFFFFF) /**< \brief (GMAC_FR) MASK Register */
+
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) (R/  32) Broadcast Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BFRX:32;          /*!< bit:  0..31  Broadcast Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_BCFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BCFR_OFFSET            0x15C        /**< \brief (GMAC_BCFR offset) Broadcast Frames Received Register */
+#define GMAC_BCFR_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_BCFR reset_value) Broadcast Frames Received Register */
+
+#define GMAC_BCFR_BFRX_Pos          0            /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
+#define GMAC_BCFR_BFRX_Msk          (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos)
+#define GMAC_BCFR_BFRX(value)       (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos))
+#define GMAC_BCFR_MASK              _U_(0xFFFFFFFF) /**< \brief (GMAC_BCFR) MASK Register */
+
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/  32) Multicast Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MFRX:32;          /*!< bit:  0..31  Multicast Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_MFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_MFR_OFFSET             0x160        /**< \brief (GMAC_MFR offset) Multicast Frames Received Register */
+#define GMAC_MFR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_MFR reset_value) Multicast Frames Received Register */
+
+#define GMAC_MFR_MFRX_Pos           0            /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
+#define GMAC_MFR_MFRX_Msk           (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos)
+#define GMAC_MFR_MFRX(value)        (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos))
+#define GMAC_MFR_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_MFR) MASK Register */
+
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/  32) Pause Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PFRX:16;          /*!< bit:  0..15  Pause Frames Received Register     */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PFR_OFFSET             0x164        /**< \brief (GMAC_PFR offset) Pause Frames Received Register */
+#define GMAC_PFR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_PFR reset_value) Pause Frames Received Register */
+
+#define GMAC_PFR_PFRX_Pos           0            /**< \brief (GMAC_PFR) Pause Frames Received Register */
+#define GMAC_PFR_PFRX_Msk           (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos)
+#define GMAC_PFR_PFRX(value)        (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos))
+#define GMAC_PFR_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_PFR) MASK Register */
+
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/  32) 64 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  64 Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_BFR64_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_BFR64_OFFSET           0x168        /**< \brief (GMAC_BFR64 offset) 64 Byte Frames Received Register */
+#define GMAC_BFR64_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_BFR64 reset_value) 64 Byte Frames Received Register */
+
+#define GMAC_BFR64_NFRX_Pos         0            /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
+#define GMAC_BFR64_NFRX_Msk         (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos)
+#define GMAC_BFR64_NFRX(value)      (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos))
+#define GMAC_BFR64_MASK             _U_(0xFFFFFFFF) /**< \brief (GMAC_BFR64) MASK Register */
+
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) (R/  32) 65 to 127 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  65 to 127 Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFR127_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR127_OFFSET         0x16C        /**< \brief (GMAC_TBFR127 offset) 65 to 127 Byte Frames Received Register */
+#define GMAC_TBFR127_RESETVALUE     _U_(0x00000000) /**< \brief (GMAC_TBFR127 reset_value) 65 to 127 Byte Frames Received Register */
+
+#define GMAC_TBFR127_NFRX_Pos       0            /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
+#define GMAC_TBFR127_NFRX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos)
+#define GMAC_TBFR127_NFRX(value)    (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos))
+#define GMAC_TBFR127_MASK           _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR127) MASK Register */
+
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/  32) 128 to 255 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  128 to 255 Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFR255_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR255_OFFSET         0x170        /**< \brief (GMAC_TBFR255 offset) 128 to 255 Byte Frames Received Register */
+#define GMAC_TBFR255_RESETVALUE     _U_(0x00000000) /**< \brief (GMAC_TBFR255 reset_value) 128 to 255 Byte Frames Received Register */
+
+#define GMAC_TBFR255_NFRX_Pos       0            /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
+#define GMAC_TBFR255_NFRX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos)
+#define GMAC_TBFR255_NFRX(value)    (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos))
+#define GMAC_TBFR255_MASK           _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR255) MASK Register */
+
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/  32) 256 to 511Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  256 to 511 Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFR511_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR511_OFFSET         0x174        /**< \brief (GMAC_TBFR511 offset) 256 to 511Byte Frames Received Register */
+#define GMAC_TBFR511_RESETVALUE     _U_(0x00000000) /**< \brief (GMAC_TBFR511 reset_value) 256 to 511Byte Frames Received Register */
+
+#define GMAC_TBFR511_NFRX_Pos       0            /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
+#define GMAC_TBFR511_NFRX_Msk       (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos)
+#define GMAC_TBFR511_NFRX(value)    (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos))
+#define GMAC_TBFR511_MASK           _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR511) MASK Register */
+
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/  32) 512 to 1023 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  512 to 1023 Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFR1023_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR1023_OFFSET        0x178        /**< \brief (GMAC_TBFR1023 offset) 512 to 1023 Byte Frames Received Register */
+#define GMAC_TBFR1023_RESETVALUE    _U_(0x00000000) /**< \brief (GMAC_TBFR1023 reset_value) 512 to 1023 Byte Frames Received Register */
+
+#define GMAC_TBFR1023_NFRX_Pos      0            /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
+#define GMAC_TBFR1023_NFRX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos)
+#define GMAC_TBFR1023_NFRX(value)   (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos))
+#define GMAC_TBFR1023_MASK          _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1023) MASK Register */
+
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) (R/  32) 1024 to 1518 Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  1024 to 1518 Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TBFR1518_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TBFR1518_OFFSET        0x17C        /**< \brief (GMAC_TBFR1518 offset) 1024 to 1518 Byte Frames Received Register */
+#define GMAC_TBFR1518_RESETVALUE    _U_(0x00000000) /**< \brief (GMAC_TBFR1518 reset_value) 1024 to 1518 Byte Frames Received Register */
+
+#define GMAC_TBFR1518_NFRX_Pos      0            /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
+#define GMAC_TBFR1518_NFRX_Msk      (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos)
+#define GMAC_TBFR1518_NFRX(value)   (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos))
+#define GMAC_TBFR1518_MASK          _U_(0xFFFFFFFF) /**< \brief (GMAC_TBFR1518) MASK Register */
+
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/  32) 1519 to Maximum Byte Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NFRX:32;          /*!< bit:  0..31  1519 to Maximum Byte Frames Received without Error */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TMXBFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TMXBFR_OFFSET          0x180        /**< \brief (GMAC_TMXBFR offset) 1519 to Maximum Byte Frames Received Register */
+#define GMAC_TMXBFR_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_TMXBFR reset_value) 1519 to Maximum Byte Frames Received Register */
+
+#define GMAC_TMXBFR_NFRX_Pos        0            /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
+#define GMAC_TMXBFR_NFRX_Msk        (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos)
+#define GMAC_TMXBFR_NFRX(value)     (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos))
+#define GMAC_TMXBFR_MASK            _U_(0xFFFFFFFF) /**< \brief (GMAC_TMXBFR) MASK Register */
+
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/  32) Undersize Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t UFRX:10;          /*!< bit:  0.. 9  Undersize Frames Received          */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_UFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UFR_OFFSET             0x184        /**< \brief (GMAC_UFR offset) Undersize Frames Received Register */
+#define GMAC_UFR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_UFR reset_value) Undersize Frames Received Register */
+
+#define GMAC_UFR_UFRX_Pos           0            /**< \brief (GMAC_UFR) Undersize Frames Received */
+#define GMAC_UFR_UFRX_Msk           (_U_(0x3FF) << GMAC_UFR_UFRX_Pos)
+#define GMAC_UFR_UFRX(value)        (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos))
+#define GMAC_UFR_MASK               _U_(0x000003FF) /**< \brief (GMAC_UFR) MASK Register */
+
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/  32) Oversize Frames Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OFRX:10;          /*!< bit:  0.. 9  Oversized Frames Received          */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_OFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_OFR_OFFSET             0x188        /**< \brief (GMAC_OFR offset) Oversize Frames Received Register */
+#define GMAC_OFR_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_OFR reset_value) Oversize Frames Received Register */
+
+#define GMAC_OFR_OFRX_Pos           0            /**< \brief (GMAC_OFR) Oversized Frames Received */
+#define GMAC_OFR_OFRX_Msk           (_U_(0x3FF) << GMAC_OFR_OFRX_Pos)
+#define GMAC_OFR_OFRX(value)        (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos))
+#define GMAC_OFR_MASK               _U_(0x000003FF) /**< \brief (GMAC_OFR) MASK Register */
+
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) (R/  32) Jabbers Received Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JRX:10;           /*!< bit:  0.. 9  Jabbers Received                   */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_JR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_JR_OFFSET              0x18C        /**< \brief (GMAC_JR offset) Jabbers Received Register */
+#define GMAC_JR_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_JR reset_value) Jabbers Received Register */
+
+#define GMAC_JR_JRX_Pos             0            /**< \brief (GMAC_JR) Jabbers Received */
+#define GMAC_JR_JRX_Msk             (_U_(0x3FF) << GMAC_JR_JRX_Pos)
+#define GMAC_JR_JRX(value)          (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos))
+#define GMAC_JR_MASK                _U_(0x000003FF) /**< \brief (GMAC_JR) MASK Register */
+
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/  32) Frame Check Sequence Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FCKR:10;          /*!< bit:  0.. 9  Frame Check Sequence Errors        */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_FCSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_FCSE_OFFSET            0x190        /**< \brief (GMAC_FCSE offset) Frame Check Sequence Errors Register */
+#define GMAC_FCSE_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_FCSE reset_value) Frame Check Sequence Errors Register */
+
+#define GMAC_FCSE_FCKR_Pos          0            /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
+#define GMAC_FCSE_FCKR_Msk          (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos)
+#define GMAC_FCSE_FCKR(value)       (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos))
+#define GMAC_FCSE_MASK              _U_(0x000003FF) /**< \brief (GMAC_FCSE) MASK Register */
+
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/  32) Length Field Frame Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LFER:10;          /*!< bit:  0.. 9  Length Field Frame Errors          */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_LFFE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_LFFE_OFFSET            0x194        /**< \brief (GMAC_LFFE offset) Length Field Frame Errors Register */
+#define GMAC_LFFE_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_LFFE reset_value) Length Field Frame Errors Register */
+
+#define GMAC_LFFE_LFER_Pos          0            /**< \brief (GMAC_LFFE) Length Field Frame Errors */
+#define GMAC_LFFE_LFER_Msk          (_U_(0x3FF) << GMAC_LFFE_LFER_Pos)
+#define GMAC_LFFE_LFER(value)       (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos))
+#define GMAC_LFFE_MASK              _U_(0x000003FF) /**< \brief (GMAC_LFFE) MASK Register */
+
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/  32) Receive Symbol Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXSE:10;          /*!< bit:  0.. 9  Receive Symbol Errors              */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RSE_OFFSET             0x198        /**< \brief (GMAC_RSE offset) Receive Symbol Errors Register */
+#define GMAC_RSE_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_RSE reset_value) Receive Symbol Errors Register */
+
+#define GMAC_RSE_RXSE_Pos           0            /**< \brief (GMAC_RSE) Receive Symbol Errors */
+#define GMAC_RSE_RXSE_Msk           (_U_(0x3FF) << GMAC_RSE_RXSE_Pos)
+#define GMAC_RSE_RXSE(value)        (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos))
+#define GMAC_RSE_MASK               _U_(0x000003FF) /**< \brief (GMAC_RSE) MASK Register */
+
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) (R/  32) Alignment Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AER:10;           /*!< bit:  0.. 9  Alignment Errors                   */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_AE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_AE_OFFSET              0x19C        /**< \brief (GMAC_AE offset) Alignment Errors Register */
+#define GMAC_AE_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_AE reset_value) Alignment Errors Register */
+
+#define GMAC_AE_AER_Pos             0            /**< \brief (GMAC_AE) Alignment Errors */
+#define GMAC_AE_AER_Msk             (_U_(0x3FF) << GMAC_AE_AER_Pos)
+#define GMAC_AE_AER(value)          (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos))
+#define GMAC_AE_MASK                _U_(0x000003FF) /**< \brief (GMAC_AE) MASK Register */
+
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) (R/  32) Receive Resource Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXRER:18;         /*!< bit:  0..17  Receive Resource Errors            */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RRE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RRE_OFFSET             0x1A0        /**< \brief (GMAC_RRE offset) Receive Resource Errors Register */
+#define GMAC_RRE_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_RRE reset_value) Receive Resource Errors Register */
+
+#define GMAC_RRE_RXRER_Pos          0            /**< \brief (GMAC_RRE) Receive Resource Errors */
+#define GMAC_RRE_RXRER_Msk          (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos)
+#define GMAC_RRE_RXRER(value)       (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos))
+#define GMAC_RRE_MASK               _U_(0x0003FFFF) /**< \brief (GMAC_RRE) MASK Register */
+
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) (R/  32) Receive Overrun Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXOVR:10;         /*!< bit:  0.. 9  Receive Overruns                   */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_ROE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_ROE_OFFSET             0x1A4        /**< \brief (GMAC_ROE offset) Receive Overrun Register */
+#define GMAC_ROE_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_ROE reset_value) Receive Overrun Register */
+
+#define GMAC_ROE_RXOVR_Pos          0            /**< \brief (GMAC_ROE) Receive Overruns */
+#define GMAC_ROE_RXOVR_Msk          (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos)
+#define GMAC_ROE_RXOVR(value)       (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos))
+#define GMAC_ROE_MASK               _U_(0x000003FF) /**< \brief (GMAC_ROE) MASK Register */
+
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) (R/  32) IP Header Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HCKER:8;          /*!< bit:  0.. 7  IP Header Checksum Errors          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_IHCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_IHCE_OFFSET            0x1A8        /**< \brief (GMAC_IHCE offset) IP Header Checksum Errors Register */
+#define GMAC_IHCE_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_IHCE reset_value) IP Header Checksum Errors Register */
+
+#define GMAC_IHCE_HCKER_Pos         0            /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
+#define GMAC_IHCE_HCKER_Msk         (_U_(0xFF) << GMAC_IHCE_HCKER_Pos)
+#define GMAC_IHCE_HCKER(value)      (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos))
+#define GMAC_IHCE_MASK              _U_(0x000000FF) /**< \brief (GMAC_IHCE) MASK Register */
+
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) (R/  32) TCP Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TCKER:8;          /*!< bit:  0.. 7  TCP Checksum Errors                */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TCE_OFFSET             0x1AC        /**< \brief (GMAC_TCE offset) TCP Checksum Errors Register */
+#define GMAC_TCE_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_TCE reset_value) TCP Checksum Errors Register */
+
+#define GMAC_TCE_TCKER_Pos          0            /**< \brief (GMAC_TCE) TCP Checksum Errors */
+#define GMAC_TCE_TCKER_Msk          (_U_(0xFF) << GMAC_TCE_TCKER_Pos)
+#define GMAC_TCE_TCKER(value)       (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos))
+#define GMAC_TCE_MASK               _U_(0x000000FF) /**< \brief (GMAC_TCE) MASK Register */
+
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) (R/  32) UDP Checksum Errors Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t UCKER:8;          /*!< bit:  0.. 7  UDP Checksum Errors                */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_UCE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_UCE_OFFSET             0x1B0        /**< \brief (GMAC_UCE offset) UDP Checksum Errors Register */
+#define GMAC_UCE_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_UCE reset_value) UDP Checksum Errors Register */
+
+#define GMAC_UCE_UCKER_Pos          0            /**< \brief (GMAC_UCE) UDP Checksum Errors */
+#define GMAC_UCE_UCKER_Msk          (_U_(0xFF) << GMAC_UCE_UCKER_Pos)
+#define GMAC_UCE_UCKER(value)       (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos))
+#define GMAC_UCE_MASK               _U_(0x000000FF) /**< \brief (GMAC_UCE) MASK Register */
+
+/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LSBTIR:16;        /*!< bit:  0..15  Lower Significant Bits of Timer Increment */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TISUBN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TISUBN_OFFSET          0x1BC        /**< \brief (GMAC_TISUBN offset) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define GMAC_TISUBN_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_TISUBN reset_value) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+
+#define GMAC_TISUBN_LSBTIR_Pos      0            /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment */
+#define GMAC_TISUBN_LSBTIR_Msk      (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos)
+#define GMAC_TISUBN_LSBTIR(value)   (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))
+#define GMAC_TISUBN_MASK            _U_(0x0000FFFF) /**< \brief (GMAC_TISUBN) MASK Register */
+
+/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TCS:16;           /*!< bit:  0..15  Timer Count in Seconds             */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TSH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSH_OFFSET             0x1C0        /**< \brief (GMAC_TSH offset) 1588 Timer Seconds High [15:0] Register */
+#define GMAC_TSH_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_TSH reset_value) 1588 Timer Seconds High [15:0] Register */
+
+#define GMAC_TSH_TCS_Pos            0            /**< \brief (GMAC_TSH) Timer Count in Seconds */
+#define GMAC_TSH_TCS_Msk            (_U_(0xFFFF) << GMAC_TSH_TCS_Pos)
+#define GMAC_TSH_TCS(value)         (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))
+#define GMAC_TSH_MASK               _U_(0x0000FFFF) /**< \brief (GMAC_TSH) MASK Register */
+
+/* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t VTS:32;           /*!< bit:  0..31  Value of Timer Seconds Register Capture */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TSSSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSSSL_OFFSET           0x1C8        /**< \brief (GMAC_TSSSL offset) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define GMAC_TSSSL_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_TSSSL reset_value) 1588 Timer Sync Strobe Seconds [31:0] Register */
+
+#define GMAC_TSSSL_VTS_Pos          0            /**< \brief (GMAC_TSSSL) Value of Timer Seconds Register Capture */
+#define GMAC_TSSSL_VTS_Msk          (_U_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos)
+#define GMAC_TSSSL_VTS(value)       (GMAC_TSSSL_VTS_Msk & ((value) << GMAC_TSSSL_VTS_Pos))
+#define GMAC_TSSSL_MASK             _U_(0xFFFFFFFF) /**< \brief (GMAC_TSSSL) MASK Register */
+
+/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t VTN:30;           /*!< bit:  0..29  Value Timer Nanoseconds Register Capture */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TSSN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSSN_OFFSET            0x1CC        /**< \brief (GMAC_TSSN offset) 1588 Timer Sync Strobe Nanoseconds Register */
+#define GMAC_TSSN_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_TSSN reset_value) 1588 Timer Sync Strobe Nanoseconds Register */
+
+#define GMAC_TSSN_VTN_Pos           0            /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */
+#define GMAC_TSSN_VTN_Msk           (_U_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos)
+#define GMAC_TSSN_VTN(value)        (GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))
+#define GMAC_TSSN_MASK              _U_(0x3FFFFFFF) /**< \brief (GMAC_TSSN) MASK Register */
+
+/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TCS:32;           /*!< bit:  0..31  Timer Count in Seconds             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TSL_OFFSET             0x1D0        /**< \brief (GMAC_TSL offset) 1588 Timer Seconds [31:0] Register */
+#define GMAC_TSL_RESETVALUE         _U_(0x00000000) /**< \brief (GMAC_TSL reset_value) 1588 Timer Seconds [31:0] Register */
+
+#define GMAC_TSL_TCS_Pos            0            /**< \brief (GMAC_TSL) Timer Count in Seconds */
+#define GMAC_TSL_TCS_Msk            (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos)
+#define GMAC_TSL_TCS(value)         (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))
+#define GMAC_TSL_MASK               _U_(0xFFFFFFFF) /**< \brief (GMAC_TSL) MASK Register */
+
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TNS:30;           /*!< bit:  0..29  Timer Count in Nanoseconds         */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TN_OFFSET              0x1D4        /**< \brief (GMAC_TN offset) 1588 Timer Nanoseconds Register */
+#define GMAC_TN_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_TN reset_value) 1588 Timer Nanoseconds Register */
+
+#define GMAC_TN_TNS_Pos             0            /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
+#define GMAC_TN_TNS_Msk             (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos)
+#define GMAC_TN_TNS(value)          (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))
+#define GMAC_TN_MASK                _U_(0x3FFFFFFF) /**< \brief (GMAC_TN) MASK Register */
+
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ITDT:30;          /*!< bit:  0..29  Increment/Decrement                */
+    uint32_t :1;               /*!< bit:     30  Reserved                           */
+    uint32_t ADJ:1;            /*!< bit:     31  Adjust 1588 Timer                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TA_OFFSET              0x1D8        /**< \brief (GMAC_TA offset) 1588 Timer Adjust Register */
+#define GMAC_TA_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_TA reset_value) 1588 Timer Adjust Register */
+
+#define GMAC_TA_ITDT_Pos            0            /**< \brief (GMAC_TA) Increment/Decrement */
+#define GMAC_TA_ITDT_Msk            (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos)
+#define GMAC_TA_ITDT(value)         (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))
+#define GMAC_TA_ADJ_Pos             31           /**< \brief (GMAC_TA) Adjust 1588 Timer */
+#define GMAC_TA_ADJ                 (_U_(0x1) << GMAC_TA_ADJ_Pos)
+#define GMAC_TA_MASK                _U_(0xBFFFFFFF) /**< \brief (GMAC_TA) MASK Register */
+
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CNS:8;            /*!< bit:  0.. 7  Count Nanoseconds                  */
+    uint32_t ACNS:8;           /*!< bit:  8..15  Alternative Count Nanoseconds      */
+    uint32_t NIT:8;            /*!< bit: 16..23  Number of Increments               */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TI_OFFSET              0x1DC        /**< \brief (GMAC_TI offset) 1588 Timer Increment Register */
+#define GMAC_TI_RESETVALUE          _U_(0x00000000) /**< \brief (GMAC_TI reset_value) 1588 Timer Increment Register */
+
+#define GMAC_TI_CNS_Pos             0            /**< \brief (GMAC_TI) Count Nanoseconds */
+#define GMAC_TI_CNS_Msk             (_U_(0xFF) << GMAC_TI_CNS_Pos)
+#define GMAC_TI_CNS(value)          (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))
+#define GMAC_TI_ACNS_Pos            8            /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
+#define GMAC_TI_ACNS_Msk            (_U_(0xFF) << GMAC_TI_ACNS_Pos)
+#define GMAC_TI_ACNS(value)         (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))
+#define GMAC_TI_NIT_Pos             16           /**< \brief (GMAC_TI) Number of Increments */
+#define GMAC_TI_NIT_Msk             (_U_(0xFF) << GMAC_TI_NIT_Pos)
+#define GMAC_TI_NIT(value)          (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))
+#define GMAC_TI_MASK                _U_(0x00FFFFFF) /**< \brief (GMAC_TI) MASK Register */
+
+/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) (R/  32) PTP Event Frame Transmitted Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EFTSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTSL_OFFSET           0x1E0        /**< \brief (GMAC_EFTSL offset) PTP Event Frame Transmitted Seconds Low Register */
+#define GMAC_EFTSL_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_EFTSL reset_value) PTP Event Frame Transmitted Seconds Low Register */
+
+#define GMAC_EFTSL_RUD_Pos          0            /**< \brief (GMAC_EFTSL) Register Update */
+#define GMAC_EFTSL_RUD_Msk          (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos)
+#define GMAC_EFTSL_RUD(value)       (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos))
+#define GMAC_EFTSL_MASK             _U_(0xFFFFFFFF) /**< \brief (GMAC_EFTSL) MASK Register */
+
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) (R/  32) PTP Event Frame Transmitted Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EFTN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFTN_OFFSET            0x1E4        /**< \brief (GMAC_EFTN offset) PTP Event Frame Transmitted Nanoseconds */
+#define GMAC_EFTN_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_EFTN reset_value) PTP Event Frame Transmitted Nanoseconds */
+
+#define GMAC_EFTN_RUD_Pos           0            /**< \brief (GMAC_EFTN) Register Update */
+#define GMAC_EFTN_RUD_Msk           (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos)
+#define GMAC_EFTN_RUD(value)        (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos))
+#define GMAC_EFTN_MASK              _U_(0x3FFFFFFF) /**< \brief (GMAC_EFTN) MASK Register */
+
+/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) (R/  32) PTP Event Frame Received Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EFRSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRSL_OFFSET           0x1E8        /**< \brief (GMAC_EFRSL offset) PTP Event Frame Received Seconds Low Register */
+#define GMAC_EFRSL_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_EFRSL reset_value) PTP Event Frame Received Seconds Low Register */
+
+#define GMAC_EFRSL_RUD_Pos          0            /**< \brief (GMAC_EFRSL) Register Update */
+#define GMAC_EFRSL_RUD_Msk          (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos)
+#define GMAC_EFRSL_RUD(value)       (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos))
+#define GMAC_EFRSL_MASK             _U_(0xFFFFFFFF) /**< \brief (GMAC_EFRSL) MASK Register */
+
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) (R/  32) PTP Event Frame Received Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_EFRN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_EFRN_OFFSET            0x1EC        /**< \brief (GMAC_EFRN offset) PTP Event Frame Received Nanoseconds */
+#define GMAC_EFRN_RESETVALUE        _U_(0x00000000) /**< \brief (GMAC_EFRN reset_value) PTP Event Frame Received Nanoseconds */
+
+#define GMAC_EFRN_RUD_Pos           0            /**< \brief (GMAC_EFRN) Register Update */
+#define GMAC_EFRN_RUD_Msk           (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos)
+#define GMAC_EFRN_RUD(value)        (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos))
+#define GMAC_EFRN_MASK              _U_(0x3FFFFFFF) /**< \brief (GMAC_EFRN) MASK Register */
+
+/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) (R/  32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PEFTSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTSL_OFFSET          0x1F0        /**< \brief (GMAC_PEFTSL offset) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define GMAC_PEFTSL_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_PEFTSL reset_value) PTP Peer Event Frame Transmitted Seconds Low Register */
+
+#define GMAC_PEFTSL_RUD_Pos         0            /**< \brief (GMAC_PEFTSL) Register Update */
+#define GMAC_PEFTSL_RUD_Msk         (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos)
+#define GMAC_PEFTSL_RUD(value)      (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos))
+#define GMAC_PEFTSL_MASK            _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFTSL) MASK Register */
+
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) (R/  32) PTP Peer Event Frame Transmitted Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PEFTN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFTN_OFFSET           0x1F4        /**< \brief (GMAC_PEFTN offset) PTP Peer Event Frame Transmitted Nanoseconds */
+#define GMAC_PEFTN_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_PEFTN reset_value) PTP Peer Event Frame Transmitted Nanoseconds */
+
+#define GMAC_PEFTN_RUD_Pos          0            /**< \brief (GMAC_PEFTN) Register Update */
+#define GMAC_PEFTN_RUD_Msk          (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos)
+#define GMAC_PEFTN_RUD(value)       (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos))
+#define GMAC_PEFTN_MASK             _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFTN) MASK Register */
+
+/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) (R/  32) PTP Peer Event Frame Received Seconds Low Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PEFRSL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRSL_OFFSET          0x1F8        /**< \brief (GMAC_PEFRSL offset) PTP Peer Event Frame Received Seconds Low Register */
+#define GMAC_PEFRSL_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_PEFRSL reset_value) PTP Peer Event Frame Received Seconds Low Register */
+
+#define GMAC_PEFRSL_RUD_Pos         0            /**< \brief (GMAC_PEFRSL) Register Update */
+#define GMAC_PEFRSL_RUD_Msk         (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos)
+#define GMAC_PEFRSL_RUD(value)      (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos))
+#define GMAC_PEFRSL_MASK            _U_(0xFFFFFFFF) /**< \brief (GMAC_PEFRSL) MASK Register */
+
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) (R/  32) PTP Peer Event Frame Received Nanoseconds -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_PEFRN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_PEFRN_OFFSET           0x1FC        /**< \brief (GMAC_PEFRN offset) PTP Peer Event Frame Received Nanoseconds */
+#define GMAC_PEFRN_RESETVALUE       _U_(0x00000000) /**< \brief (GMAC_PEFRN reset_value) PTP Peer Event Frame Received Nanoseconds */
+
+#define GMAC_PEFRN_RUD_Pos          0            /**< \brief (GMAC_PEFRN) Register Update */
+#define GMAC_PEFRN_RUD_Msk          (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos)
+#define GMAC_PEFRN_RUD(value)       (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos))
+#define GMAC_PEFRN_MASK             _U_(0x3FFFFFFF) /**< \brief (GMAC_PEFRN) MASK Register */
+
+/* -------- GMAC_RLPITR : (GMAC Offset: 0x270) (R/  32) Receive LPI transition Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RLPITR:16;        /*!< bit:  0..15  Count number of times transition from rx normal idle to low power idle */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RLPITR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RLPITR_OFFSET          0x270        /**< \brief (GMAC_RLPITR offset) Receive LPI transition Register */
+#define GMAC_RLPITR_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_RLPITR reset_value) Receive LPI transition Register */
+
+#define GMAC_RLPITR_RLPITR_Pos      0            /**< \brief (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle */
+#define GMAC_RLPITR_RLPITR_Msk      (_U_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos)
+#define GMAC_RLPITR_RLPITR(value)   (GMAC_RLPITR_RLPITR_Msk & ((value) << GMAC_RLPITR_RLPITR_Pos))
+#define GMAC_RLPITR_MASK            _U_(0x0000FFFF) /**< \brief (GMAC_RLPITR) MASK Register */
+
+/* -------- GMAC_RLPITI : (GMAC Offset: 0x274) (R/  32) Receive LPI Time Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RLPITI:24;        /*!< bit:  0..23  Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_RLPITI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_RLPITI_OFFSET          0x274        /**< \brief (GMAC_RLPITI offset) Receive LPI Time Register */
+#define GMAC_RLPITI_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_RLPITI reset_value) Receive LPI Time Register */
+
+#define GMAC_RLPITI_RLPITI_Pos      0            /**< \brief (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
+#define GMAC_RLPITI_RLPITI_Msk      (_U_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos)
+#define GMAC_RLPITI_RLPITI(value)   (GMAC_RLPITI_RLPITI_Msk & ((value) << GMAC_RLPITI_RLPITI_Pos))
+#define GMAC_RLPITI_MASK            _U_(0x00FFFFFF) /**< \brief (GMAC_RLPITI) MASK Register */
+
+/* -------- GMAC_TLPITR : (GMAC Offset: 0x278) (R/  32) Receive LPI transition Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TLPITR:16;        /*!< bit:  0..15  Count number of times enable LPI tx bit 20 goes from low to high */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TLPITR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TLPITR_OFFSET          0x278        /**< \brief (GMAC_TLPITR offset) Receive LPI transition Register */
+#define GMAC_TLPITR_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_TLPITR reset_value) Receive LPI transition Register */
+
+#define GMAC_TLPITR_TLPITR_Pos      0            /**< \brief (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high */
+#define GMAC_TLPITR_TLPITR_Msk      (_U_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos)
+#define GMAC_TLPITR_TLPITR(value)   (GMAC_TLPITR_TLPITR_Msk & ((value) << GMAC_TLPITR_TLPITR_Pos))
+#define GMAC_TLPITR_MASK            _U_(0x0000FFFF) /**< \brief (GMAC_TLPITR) MASK Register */
+
+/* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) (R/  32) Receive LPI Time Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TLPITI:24;        /*!< bit:  0..23  Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GMAC_TLPITI_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GMAC_TLPITI_OFFSET          0x27C        /**< \brief (GMAC_TLPITI offset) Receive LPI Time Register */
+#define GMAC_TLPITI_RESETVALUE      _U_(0x00000000) /**< \brief (GMAC_TLPITI reset_value) Receive LPI Time Register */
+
+#define GMAC_TLPITI_TLPITI_Pos      0            /**< \brief (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
+#define GMAC_TLPITI_TLPITI_Msk      (_U_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos)
+#define GMAC_TLPITI_TLPITI(value)   (GMAC_TLPITI_TLPITI_Msk & ((value) << GMAC_TLPITI_TLPITI_Pos))
+#define GMAC_TLPITI_MASK            _U_(0x00FFFFFF) /**< \brief (GMAC_TLPITI) MASK Register */
+
+/** \brief GmacSa hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GMAC_SAB_Type             SAB;         /**< \brief Offset: 0x000 (R/W 32) Specific Address Bottom [31:0] Register */
+  __IO GMAC_SAT_Type             SAT;         /**< \brief Offset: 0x004 (R/W 32) Specific Address Top [47:32] Register */
+} GmacSa;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief GMAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GMAC_NCR_Type             NCR;         /**< \brief Offset: 0x000 (R/W 32) Network Control Register */
+  __IO GMAC_NCFGR_Type           NCFGR;       /**< \brief Offset: 0x004 (R/W 32) Network Configuration Register */
+  __I  GMAC_NSR_Type             NSR;         /**< \brief Offset: 0x008 (R/  32) Network Status Register */
+  __IO GMAC_UR_Type              UR;          /**< \brief Offset: 0x00C (R/W 32) User Register */
+  __IO GMAC_DCFGR_Type           DCFGR;       /**< \brief Offset: 0x010 (R/W 32) DMA Configuration Register */
+  __IO GMAC_TSR_Type             TSR;         /**< \brief Offset: 0x014 (R/W 32) Transmit Status Register */
+  __IO GMAC_RBQB_Type            RBQB;        /**< \brief Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address */
+  __IO GMAC_TBQB_Type            TBQB;        /**< \brief Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address */
+  __IO GMAC_RSR_Type             RSR;         /**< \brief Offset: 0x020 (R/W 32) Receive Status Register */
+  __IO GMAC_ISR_Type             ISR;         /**< \brief Offset: 0x024 (R/W 32) Interrupt Status Register */
+  __O  GMAC_IER_Type             IER;         /**< \brief Offset: 0x028 ( /W 32) Interrupt Enable Register */
+  __O  GMAC_IDR_Type             IDR;         /**< \brief Offset: 0x02C ( /W 32) Interrupt Disable Register */
+  __I  GMAC_IMR_Type             IMR;         /**< \brief Offset: 0x030 (R/  32) Interrupt Mask Register */
+  __IO GMAC_MAN_Type             MAN;         /**< \brief Offset: 0x034 (R/W 32) PHY Maintenance Register */
+  __I  GMAC_RPQ_Type             RPQ;         /**< \brief Offset: 0x038 (R/  32) Received Pause Quantum Register */
+  __IO GMAC_TPQ_Type             TPQ;         /**< \brief Offset: 0x03C (R/W 32) Transmit Pause Quantum Register */
+  __IO GMAC_TPSF_Type            TPSF;        /**< \brief Offset: 0x040 (R/W 32) TX partial store and forward Register */
+  __IO GMAC_RPSF_Type            RPSF;        /**< \brief Offset: 0x044 (R/W 32) RX partial store and forward Register */
+  __IO GMAC_RJFML_Type           RJFML;       /**< \brief Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register */
+       RoReg8                    Reserved1[0x34];
+  __IO GMAC_HRB_Type             HRB;         /**< \brief Offset: 0x080 (R/W 32) Hash Register Bottom [31:0] */
+  __IO GMAC_HRT_Type             HRT;         /**< \brief Offset: 0x084 (R/W 32) Hash Register Top [63:32] */
+       GmacSa                    Sa[4];       /**< \brief Offset: 0x088 GmacSa groups */
+  __IO GMAC_TIDM_Type            TIDM[4];     /**< \brief Offset: 0x0A8 (R/W 32) Type ID Match Register */
+  __IO GMAC_WOL_Type             WOL;         /**< \brief Offset: 0x0B8 (R/W 32) Wake on LAN */
+  __IO GMAC_IPGS_Type            IPGS;        /**< \brief Offset: 0x0BC (R/W 32) IPG Stretch Register */
+  __IO GMAC_SVLAN_Type           SVLAN;       /**< \brief Offset: 0x0C0 (R/W 32) Stacked VLAN Register */
+  __IO GMAC_TPFCP_Type           TPFCP;       /**< \brief Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register */
+  __IO GMAC_SAMB1_Type           SAMB1;       /**< \brief Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */
+  __IO GMAC_SAMT1_Type           SAMT1;       /**< \brief Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register */
+       RoReg8                    Reserved2[0xC];
+  __IO GMAC_NSC_Type             NSC;         /**< \brief Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register */
+  __IO GMAC_SCL_Type             SCL;         /**< \brief Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register */
+  __IO GMAC_SCH_Type             SCH;         /**< \brief Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register */
+  __I  GMAC_EFTSH_Type           EFTSH;       /**< \brief Offset: 0x0E8 (R/  32) PTP Event Frame Transmitted Seconds High Register */
+  __I  GMAC_EFRSH_Type           EFRSH;       /**< \brief Offset: 0x0EC (R/  32) PTP Event Frame Received Seconds High Register */
+  __I  GMAC_PEFTSH_Type          PEFTSH;      /**< \brief Offset: 0x0F0 (R/  32) PTP Peer Event Frame Transmitted Seconds High Register */
+  __I  GMAC_PEFRSH_Type          PEFRSH;      /**< \brief Offset: 0x0F4 (R/  32) PTP Peer Event Frame Received Seconds High Register */
+       RoReg8                    Reserved3[0x8];
+  __I  GMAC_OTLO_Type            OTLO;        /**< \brief Offset: 0x100 (R/  32) Octets Transmitted [31:0] Register */
+  __I  GMAC_OTHI_Type            OTHI;        /**< \brief Offset: 0x104 (R/  32) Octets Transmitted [47:32] Register */
+  __I  GMAC_FT_Type              FT;          /**< \brief Offset: 0x108 (R/  32) Frames Transmitted Register */
+  __I  GMAC_BCFT_Type            BCFT;        /**< \brief Offset: 0x10C (R/  32) Broadcast Frames Transmitted Register */
+  __I  GMAC_MFT_Type             MFT;         /**< \brief Offset: 0x110 (R/  32) Multicast Frames Transmitted Register */
+  __I  GMAC_PFT_Type             PFT;         /**< \brief Offset: 0x114 (R/  32) Pause Frames Transmitted Register */
+  __I  GMAC_BFT64_Type           BFT64;       /**< \brief Offset: 0x118 (R/  32) 64 Byte Frames Transmitted Register */
+  __I  GMAC_TBFT127_Type         TBFT127;     /**< \brief Offset: 0x11C (R/  32) 65 to 127 Byte Frames Transmitted Register */
+  __I  GMAC_TBFT255_Type         TBFT255;     /**< \brief Offset: 0x120 (R/  32) 128 to 255 Byte Frames Transmitted Register */
+  __I  GMAC_TBFT511_Type         TBFT511;     /**< \brief Offset: 0x124 (R/  32) 256 to 511 Byte Frames Transmitted Register */
+  __I  GMAC_TBFT1023_Type        TBFT1023;    /**< \brief Offset: 0x128 (R/  32) 512 to 1023 Byte Frames Transmitted Register */
+  __I  GMAC_TBFT1518_Type        TBFT1518;    /**< \brief Offset: 0x12C (R/  32) 1024 to 1518 Byte Frames Transmitted Register */
+  __I  GMAC_GTBFT1518_Type       GTBFT1518;   /**< \brief Offset: 0x130 (R/  32) Greater Than 1518 Byte Frames Transmitted Register */
+  __I  GMAC_TUR_Type             TUR;         /**< \brief Offset: 0x134 (R/  32) Transmit Underruns Register */
+  __I  GMAC_SCF_Type             SCF;         /**< \brief Offset: 0x138 (R/  32) Single Collision Frames Register */
+  __I  GMAC_MCF_Type             MCF;         /**< \brief Offset: 0x13C (R/  32) Multiple Collision Frames Register */
+  __I  GMAC_EC_Type              EC;          /**< \brief Offset: 0x140 (R/  32) Excessive Collisions Register */
+  __I  GMAC_LC_Type              LC;          /**< \brief Offset: 0x144 (R/  32) Late Collisions Register */
+  __I  GMAC_DTF_Type             DTF;         /**< \brief Offset: 0x148 (R/  32) Deferred Transmission Frames Register */
+  __I  GMAC_CSE_Type             CSE;         /**< \brief Offset: 0x14C (R/  32) Carrier Sense Errors Register */
+  __I  GMAC_ORLO_Type            ORLO;        /**< \brief Offset: 0x150 (R/  32) Octets Received [31:0] Received */
+  __I  GMAC_ORHI_Type            ORHI;        /**< \brief Offset: 0x154 (R/  32) Octets Received [47:32] Received */
+  __I  GMAC_FR_Type              FR;          /**< \brief Offset: 0x158 (R/  32) Frames Received Register */
+  __I  GMAC_BCFR_Type            BCFR;        /**< \brief Offset: 0x15C (R/  32) Broadcast Frames Received Register */
+  __I  GMAC_MFR_Type             MFR;         /**< \brief Offset: 0x160 (R/  32) Multicast Frames Received Register */
+  __I  GMAC_PFR_Type             PFR;         /**< \brief Offset: 0x164 (R/  32) Pause Frames Received Register */
+  __I  GMAC_BFR64_Type           BFR64;       /**< \brief Offset: 0x168 (R/  32) 64 Byte Frames Received Register */
+  __I  GMAC_TBFR127_Type         TBFR127;     /**< \brief Offset: 0x16C (R/  32) 65 to 127 Byte Frames Received Register */
+  __I  GMAC_TBFR255_Type         TBFR255;     /**< \brief Offset: 0x170 (R/  32) 128 to 255 Byte Frames Received Register */
+  __I  GMAC_TBFR511_Type         TBFR511;     /**< \brief Offset: 0x174 (R/  32) 256 to 511Byte Frames Received Register */
+  __I  GMAC_TBFR1023_Type        TBFR1023;    /**< \brief Offset: 0x178 (R/  32) 512 to 1023 Byte Frames Received Register */
+  __I  GMAC_TBFR1518_Type        TBFR1518;    /**< \brief Offset: 0x17C (R/  32) 1024 to 1518 Byte Frames Received Register */
+  __I  GMAC_TMXBFR_Type          TMXBFR;      /**< \brief Offset: 0x180 (R/  32) 1519 to Maximum Byte Frames Received Register */
+  __I  GMAC_UFR_Type             UFR;         /**< \brief Offset: 0x184 (R/  32) Undersize Frames Received Register */
+  __I  GMAC_OFR_Type             OFR;         /**< \brief Offset: 0x188 (R/  32) Oversize Frames Received Register */
+  __I  GMAC_JR_Type              JR;          /**< \brief Offset: 0x18C (R/  32) Jabbers Received Register */
+  __I  GMAC_FCSE_Type            FCSE;        /**< \brief Offset: 0x190 (R/  32) Frame Check Sequence Errors Register */
+  __I  GMAC_LFFE_Type            LFFE;        /**< \brief Offset: 0x194 (R/  32) Length Field Frame Errors Register */
+  __I  GMAC_RSE_Type             RSE;         /**< \brief Offset: 0x198 (R/  32) Receive Symbol Errors Register */
+  __I  GMAC_AE_Type              AE;          /**< \brief Offset: 0x19C (R/  32) Alignment Errors Register */
+  __I  GMAC_RRE_Type             RRE;         /**< \brief Offset: 0x1A0 (R/  32) Receive Resource Errors Register */
+  __I  GMAC_ROE_Type             ROE;         /**< \brief Offset: 0x1A4 (R/  32) Receive Overrun Register */
+  __I  GMAC_IHCE_Type            IHCE;        /**< \brief Offset: 0x1A8 (R/  32) IP Header Checksum Errors Register */
+  __I  GMAC_TCE_Type             TCE;         /**< \brief Offset: 0x1AC (R/  32) TCP Checksum Errors Register */
+  __I  GMAC_UCE_Type             UCE;         /**< \brief Offset: 0x1B0 (R/  32) UDP Checksum Errors Register */
+       RoReg8                    Reserved4[0x8];
+  __IO GMAC_TISUBN_Type          TISUBN;      /**< \brief Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+  __IO GMAC_TSH_Type             TSH;         /**< \brief Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */
+       RoReg8                    Reserved5[0x4];
+  __IO GMAC_TSSSL_Type           TSSSL;       /**< \brief Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */
+  __IO GMAC_TSSN_Type            TSSN;        /**< \brief Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */
+  __IO GMAC_TSL_Type             TSL;         /**< \brief Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */
+  __IO GMAC_TN_Type              TN;          /**< \brief Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */
+  __O  GMAC_TA_Type              TA;          /**< \brief Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */
+  __IO GMAC_TI_Type              TI;          /**< \brief Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */
+  __I  GMAC_EFTSL_Type           EFTSL;       /**< \brief Offset: 0x1E0 (R/  32) PTP Event Frame Transmitted Seconds Low Register */
+  __I  GMAC_EFTN_Type            EFTN;        /**< \brief Offset: 0x1E4 (R/  32) PTP Event Frame Transmitted Nanoseconds */
+  __I  GMAC_EFRSL_Type           EFRSL;       /**< \brief Offset: 0x1E8 (R/  32) PTP Event Frame Received Seconds Low Register */
+  __I  GMAC_EFRN_Type            EFRN;        /**< \brief Offset: 0x1EC (R/  32) PTP Event Frame Received Nanoseconds */
+  __I  GMAC_PEFTSL_Type          PEFTSL;      /**< \brief Offset: 0x1F0 (R/  32) PTP Peer Event Frame Transmitted Seconds Low Register */
+  __I  GMAC_PEFTN_Type           PEFTN;       /**< \brief Offset: 0x1F4 (R/  32) PTP Peer Event Frame Transmitted Nanoseconds */
+  __I  GMAC_PEFRSL_Type          PEFRSL;      /**< \brief Offset: 0x1F8 (R/  32) PTP Peer Event Frame Received Seconds Low Register */
+  __I  GMAC_PEFRN_Type           PEFRN;       /**< \brief Offset: 0x1FC (R/  32) PTP Peer Event Frame Received Nanoseconds */
+       RoReg8                    Reserved6[0x70];
+  __I  GMAC_RLPITR_Type          RLPITR;      /**< \brief Offset: 0x270 (R/  32) Receive LPI transition Register */
+  __I  GMAC_RLPITI_Type          RLPITI;      /**< \brief Offset: 0x274 (R/  32) Receive LPI Time Register */
+  __I  GMAC_TLPITR_Type          TLPITR;      /**< \brief Offset: 0x278 (R/  32) Receive LPI transition Register */
+  __I  GMAC_TLPITI_Type          TLPITI;      /**< \brief Offset: 0x27C (R/  32) Receive LPI Time Register */
+} Gmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_GMAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/hmatrixb.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/hmatrixb.h
new file mode 100644
index 000000000..74d4e1c88
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/hmatrixb.h	
@@ -0,0 +1,84 @@
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_HMATRIXB_COMPONENT_
+#define _SAME53_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAME53_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB                0x214
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE    _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK          _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE    _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK          _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO HMATRIXB_PRAS_Type        PRAS;        /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+  __IO HMATRIXB_PRBS_Type        PRBS;        /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       RoReg8                    Reserved1[0x80];
+       HmatrixbPrs               Prs[16];     /**< \brief Offset: 0x080 HmatrixbPrs groups */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_HMATRIXB_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/i2s.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/i2s.h
new file mode 100644
index 000000000..63bfe2268
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/i2s.h	
@@ -0,0 +1,747 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_I2S_COMPONENT_
+#define _SAME53_I2S_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAME53_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S                     0x200
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable                */
+    uint8_t  CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable                */
+    uint8_t  TXEN:1;           /*!< bit:      4  Tx Serializer Enable               */
+    uint8_t  RXEN:1;           /*!< bit:      5  Rx Serializer Enable               */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable                */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST             (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE            (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0             (_U_(1) << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1             (_U_(1) << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk          (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_TXEN_Pos          4            /**< \brief (I2S_CTRLA) Tx Serializer Enable */
+#define I2S_CTRLA_TXEN              (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
+#define I2S_CTRLA_RXEN_Pos          5            /**< \brief (I2S_CTRLA) Rx Serializer Enable */
+#define I2S_CTRLA_RXEN              (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
+#define I2S_CTRLA_MASK              _U_(0x3F)    /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SLOTSIZE:2;       /*!< bit:  0.. 1  Slot Size                          */
+    uint32_t NBSLOTS:3;        /*!< bit:  2.. 4  Number of Slots in Frame           */
+    uint32_t FSWIDTH:2;        /*!< bit:  5.. 6  Frame Sync Width                   */
+    uint32_t BITDELAY:1;       /*!< bit:      7  Data Delay from Frame Sync         */
+    uint32_t FSSEL:1;          /*!< bit:      8  Frame Sync Select                  */
+    uint32_t FSINV:1;          /*!< bit:      9  Frame Sync Invert                  */
+    uint32_t FSOUTINV:1;       /*!< bit:     10  Frame Sync Output Invert           */
+    uint32_t SCKSEL:1;         /*!< bit:     11  Serial Clock Select                */
+    uint32_t SCKOUTINV:1;      /*!< bit:     12  Serial Clock Output Invert         */
+    uint32_t MCKSEL:1;         /*!< bit:     13  Master Clock Select                */
+    uint32_t MCKEN:1;          /*!< bit:     14  Master Clock Enable                */
+    uint32_t MCKOUTINV:1;      /*!< bit:     15  Master Clock Output Invert         */
+    uint32_t MCKDIV:6;         /*!< bit: 16..21  Master Clock Division Factor       */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t MCKOUTDIV:6;      /*!< bit: 24..29  Master Clock Output Division Factor */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk    (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define   I2S_CLKCTRL_SLOTSIZE_8_Val      _U_(0x0)   /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_16_Val     _U_(0x1)   /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_24_Val     _U_(0x2)   /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define   I2S_CLKCTRL_SLOTSIZE_32_Val     _U_(0x3)   /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk     (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk     (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    _U_(0x0)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    _U_(0x1)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     _U_(0x2)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   _U_(0x3)   /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY        (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
+#define   I2S_CLKCTRL_BITDELAY_LJ_Val     _U_(0x0)   /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define   I2S_CLKCTRL_BITDELAY_I2S_Val    _U_(0x1)   /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL           (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
+#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    _U_(0x0)   /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     _U_(0x1)   /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos       9            /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV           (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_FSOUTINV_Pos    10           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV        (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos      11           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL          (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
+#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   _U_(0x0)   /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   _U_(0x1)   /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos   12           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV       (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos      13           /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL          (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
+#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     _U_(0x0)   /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   _U_(0x1)   /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos       14           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN           (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos   15           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV       (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk      (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk   (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_MASK            _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE     _U_(0x0000)  /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0         (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1         (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk      (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0          (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1          (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk       (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0         (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1         (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk      (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0          (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1          (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk       (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK           _U_(0x3333)  /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
+    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
+    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
+    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
+    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE     _U_(0x0000)  /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0         (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1         (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk      (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0          (_U_(1) << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1          (_U_(1) << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk       (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0         (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1         (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk      (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0          (_U_(1) << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1          (_U_(1) << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk       (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK           _U_(0x3333)  /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
+    __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0                  */
+    __I uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0                   */
+    __I uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0                */
+    __I uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x                    */
+    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x                  */
+    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    __I uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x                   */
+    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    __I uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x                */
+    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE      _U_(0x0000)  /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0          (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1          (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk       (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0           (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1           (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk        (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0          (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1          (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk       (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0           (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1           (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk        (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK            _U_(0x3333)  /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Status */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Status      */
+    uint16_t CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable Synchronization Status */
+    uint16_t CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable Synchronization Status */
+    uint16_t TXEN:1;           /*!< bit:      4  Tx Serializer Enable Synchronization Status */
+    uint16_t RXEN:1;           /*!< bit:      5  Rx Serializer Enable Synchronization Status */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t TXDATA:1;         /*!< bit:      8  Tx Data Synchronization Status     */
+    uint16_t RXDATA:1;         /*!< bit:      9  Rx Data Synchronization Status     */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable Synchronization Status */
+    uint16_t :12;              /*!< bit:  4..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE     _U_(0x0000)  /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST          (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE         (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0          (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1          (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk       (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_TXEN_Pos       4            /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
+#define I2S_SYNCBUSY_TXEN           (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
+#define I2S_SYNCBUSY_RXEN_Pos       5            /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
+#define I2S_SYNCBUSY_RXEN           (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
+#define I2S_SYNCBUSY_TXDATA_Pos     8            /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
+#define I2S_SYNCBUSY_TXDATA         (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
+#define I2S_SYNCBUSY_RXDATA_Pos     9            /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
+#define I2S_SYNCBUSY_RXDATA         (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
+#define I2S_SYNCBUSY_MASK           _U_(0x033F)  /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t TXDEFAULT:2;      /*!< bit:  2.. 3  Line Default Line when Slot Disabled */
+    uint32_t TXSAME:1;         /*!< bit:      4  Transmit Data when Underrun        */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
+    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
+    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
+    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
+    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
+    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
+    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
+    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
+    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
+    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
+    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
+    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
+    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
+    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_TXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_TXCTRL_OFFSET           0x20         /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
+#define I2S_TXCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
+
+#define I2S_TXCTRL_TXDEFAULT_Pos    2            /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
+#define I2S_TXCTRL_TXDEFAULT_Msk    (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
+#define   I2S_TXCTRL_TXDEFAULT_ZERO_Val   _U_(0x0)   /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
+#define   I2S_TXCTRL_TXDEFAULT_ONE_Val    _U_(0x1)   /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
+#define   I2S_TXCTRL_TXDEFAULT_HIZ_Val    _U_(0x3)   /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
+#define I2S_TXCTRL_TXDEFAULT_ZERO   (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT_ONE    (I2S_TXCTRL_TXDEFAULT_ONE_Val  << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXDEFAULT_HIZ    (I2S_TXCTRL_TXDEFAULT_HIZ_Val  << I2S_TXCTRL_TXDEFAULT_Pos)
+#define I2S_TXCTRL_TXSAME_Pos       4            /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
+#define I2S_TXCTRL_TXSAME           (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
+#define   I2S_TXCTRL_TXSAME_ZERO_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
+#define   I2S_TXCTRL_TXSAME_SAME_Val      _U_(0x1)   /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
+#define I2S_TXCTRL_TXSAME_ZERO      (I2S_TXCTRL_TXSAME_ZERO_Val    << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_TXSAME_SAME      (I2S_TXCTRL_TXSAME_SAME_Val    << I2S_TXCTRL_TXSAME_Pos)
+#define I2S_TXCTRL_SLOTADJ_Pos      7            /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
+#define I2S_TXCTRL_SLOTADJ          (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
+#define   I2S_TXCTRL_SLOTADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
+#define   I2S_TXCTRL_SLOTADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
+#define I2S_TXCTRL_SLOTADJ_RIGHT    (I2S_TXCTRL_SLOTADJ_RIGHT_Val  << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_SLOTADJ_LEFT     (I2S_TXCTRL_SLOTADJ_LEFT_Val   << I2S_TXCTRL_SLOTADJ_Pos)
+#define I2S_TXCTRL_DATASIZE_Pos     8            /**< \brief (I2S_TXCTRL) Data Word Size */
+#define I2S_TXCTRL_DATASIZE_Msk     (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE(value)  (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
+#define   I2S_TXCTRL_DATASIZE_32_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) 32 bits */
+#define   I2S_TXCTRL_DATASIZE_24_Val      _U_(0x1)   /**< \brief (I2S_TXCTRL) 24 bits */
+#define   I2S_TXCTRL_DATASIZE_20_Val      _U_(0x2)   /**< \brief (I2S_TXCTRL) 20 bits */
+#define   I2S_TXCTRL_DATASIZE_18_Val      _U_(0x3)   /**< \brief (I2S_TXCTRL) 18 bits */
+#define   I2S_TXCTRL_DATASIZE_16_Val      _U_(0x4)   /**< \brief (I2S_TXCTRL) 16 bits */
+#define   I2S_TXCTRL_DATASIZE_16C_Val     _U_(0x5)   /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
+#define   I2S_TXCTRL_DATASIZE_8_Val       _U_(0x6)   /**< \brief (I2S_TXCTRL) 8 bits */
+#define   I2S_TXCTRL_DATASIZE_8C_Val      _U_(0x7)   /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
+#define I2S_TXCTRL_DATASIZE_32      (I2S_TXCTRL_DATASIZE_32_Val    << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_24      (I2S_TXCTRL_DATASIZE_24_Val    << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_20      (I2S_TXCTRL_DATASIZE_20_Val    << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_18      (I2S_TXCTRL_DATASIZE_18_Val    << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_16      (I2S_TXCTRL_DATASIZE_16_Val    << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_16C     (I2S_TXCTRL_DATASIZE_16C_Val   << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_8       (I2S_TXCTRL_DATASIZE_8_Val     << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_DATASIZE_8C      (I2S_TXCTRL_DATASIZE_8C_Val    << I2S_TXCTRL_DATASIZE_Pos)
+#define I2S_TXCTRL_WORDADJ_Pos      12           /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
+#define I2S_TXCTRL_WORDADJ          (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
+#define   I2S_TXCTRL_WORDADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
+#define   I2S_TXCTRL_WORDADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
+#define I2S_TXCTRL_WORDADJ_RIGHT    (I2S_TXCTRL_WORDADJ_RIGHT_Val  << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_WORDADJ_LEFT     (I2S_TXCTRL_WORDADJ_LEFT_Val   << I2S_TXCTRL_WORDADJ_Pos)
+#define I2S_TXCTRL_EXTEND_Pos       13           /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
+#define I2S_TXCTRL_EXTEND_Msk       (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND(value)    (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
+#define   I2S_TXCTRL_EXTEND_ZERO_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) Extend with zeroes */
+#define   I2S_TXCTRL_EXTEND_ONE_Val       _U_(0x1)   /**< \brief (I2S_TXCTRL) Extend with ones */
+#define   I2S_TXCTRL_EXTEND_MSBIT_Val     _U_(0x2)   /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
+#define   I2S_TXCTRL_EXTEND_LSBIT_Val     _U_(0x3)   /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
+#define I2S_TXCTRL_EXTEND_ZERO      (I2S_TXCTRL_EXTEND_ZERO_Val    << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_ONE       (I2S_TXCTRL_EXTEND_ONE_Val     << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_MSBIT     (I2S_TXCTRL_EXTEND_MSBIT_Val   << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_EXTEND_LSBIT     (I2S_TXCTRL_EXTEND_LSBIT_Val   << I2S_TXCTRL_EXTEND_Pos)
+#define I2S_TXCTRL_BITREV_Pos       15           /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
+#define I2S_TXCTRL_BITREV           (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
+#define   I2S_TXCTRL_BITREV_MSBIT_Val     _U_(0x0)   /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define   I2S_TXCTRL_BITREV_LSBIT_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_TXCTRL_BITREV_MSBIT     (I2S_TXCTRL_BITREV_MSBIT_Val   << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_BITREV_LSBIT     (I2S_TXCTRL_BITREV_LSBIT_Val   << I2S_TXCTRL_BITREV_Pos)
+#define I2S_TXCTRL_SLOTDIS0_Pos     16           /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS0         (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
+#define I2S_TXCTRL_SLOTDIS1_Pos     17           /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS1         (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
+#define I2S_TXCTRL_SLOTDIS2_Pos     18           /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS2         (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
+#define I2S_TXCTRL_SLOTDIS3_Pos     19           /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS3         (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
+#define I2S_TXCTRL_SLOTDIS4_Pos     20           /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS4         (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
+#define I2S_TXCTRL_SLOTDIS5_Pos     21           /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS5         (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
+#define I2S_TXCTRL_SLOTDIS6_Pos     22           /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS6         (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
+#define I2S_TXCTRL_SLOTDIS7_Pos     23           /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS7         (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
+#define I2S_TXCTRL_SLOTDIS_Pos      16           /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
+#define I2S_TXCTRL_SLOTDIS_Msk      (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
+#define I2S_TXCTRL_SLOTDIS(value)   (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
+#define I2S_TXCTRL_MONO_Pos         24           /**< \brief (I2S_TXCTRL) Mono Mode */
+#define I2S_TXCTRL_MONO             (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
+#define   I2S_TXCTRL_MONO_STEREO_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) Normal mode */
+#define   I2S_TXCTRL_MONO_MONO_Val        _U_(0x1)   /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
+#define I2S_TXCTRL_MONO_STEREO      (I2S_TXCTRL_MONO_STEREO_Val    << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_MONO_MONO        (I2S_TXCTRL_MONO_MONO_Val      << I2S_TXCTRL_MONO_Pos)
+#define I2S_TXCTRL_DMA_Pos          25           /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
+#define I2S_TXCTRL_DMA              (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
+#define   I2S_TXCTRL_DMA_SINGLE_Val       _U_(0x0)   /**< \brief (I2S_TXCTRL) Single DMA channel */
+#define   I2S_TXCTRL_DMA_MULTIPLE_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
+#define I2S_TXCTRL_DMA_SINGLE       (I2S_TXCTRL_DMA_SINGLE_Val     << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_DMA_MULTIPLE     (I2S_TXCTRL_DMA_MULTIPLE_Val   << I2S_TXCTRL_DMA_Pos)
+#define I2S_TXCTRL_MASK             _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
+
+/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERMODE:2;        /*!< bit:  0.. 1  Serializer Mode                    */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t CLKSEL:1;         /*!< bit:      5  Clock Unit Selection               */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
+    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
+    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
+    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
+    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
+    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
+    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
+    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
+    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
+    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
+    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
+    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
+    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
+    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
+    uint32_t RXLOOP:1;         /*!< bit:     26  Loop-back Test Mode                */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_RXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_RXCTRL_OFFSET           0x24         /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
+#define I2S_RXCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
+
+#define I2S_RXCTRL_SERMODE_Pos      0            /**< \brief (I2S_RXCTRL) Serializer Mode */
+#define I2S_RXCTRL_SERMODE_Msk      (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_SERMODE(value)   (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
+#define   I2S_RXCTRL_SERMODE_RX_Val       _U_(0x0)   /**< \brief (I2S_RXCTRL) Receive */
+#define   I2S_RXCTRL_SERMODE_PDM2_Val     _U_(0x2)   /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_RXCTRL_SERMODE_RX       (I2S_RXCTRL_SERMODE_RX_Val     << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_SERMODE_PDM2     (I2S_RXCTRL_SERMODE_PDM2_Val   << I2S_RXCTRL_SERMODE_Pos)
+#define I2S_RXCTRL_CLKSEL_Pos       5            /**< \brief (I2S_RXCTRL) Clock Unit Selection */
+#define I2S_RXCTRL_CLKSEL           (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
+#define   I2S_RXCTRL_CLKSEL_CLK0_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
+#define   I2S_RXCTRL_CLKSEL_CLK1_Val      _U_(0x1)   /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
+#define I2S_RXCTRL_CLKSEL_CLK0      (I2S_RXCTRL_CLKSEL_CLK0_Val    << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_CLKSEL_CLK1      (I2S_RXCTRL_CLKSEL_CLK1_Val    << I2S_RXCTRL_CLKSEL_Pos)
+#define I2S_RXCTRL_SLOTADJ_Pos      7            /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
+#define I2S_RXCTRL_SLOTADJ          (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
+#define   I2S_RXCTRL_SLOTADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
+#define   I2S_RXCTRL_SLOTADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
+#define I2S_RXCTRL_SLOTADJ_RIGHT    (I2S_RXCTRL_SLOTADJ_RIGHT_Val  << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_SLOTADJ_LEFT     (I2S_RXCTRL_SLOTADJ_LEFT_Val   << I2S_RXCTRL_SLOTADJ_Pos)
+#define I2S_RXCTRL_DATASIZE_Pos     8            /**< \brief (I2S_RXCTRL) Data Word Size */
+#define I2S_RXCTRL_DATASIZE_Msk     (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE(value)  (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
+#define   I2S_RXCTRL_DATASIZE_32_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) 32 bits */
+#define   I2S_RXCTRL_DATASIZE_24_Val      _U_(0x1)   /**< \brief (I2S_RXCTRL) 24 bits */
+#define   I2S_RXCTRL_DATASIZE_20_Val      _U_(0x2)   /**< \brief (I2S_RXCTRL) 20 bits */
+#define   I2S_RXCTRL_DATASIZE_18_Val      _U_(0x3)   /**< \brief (I2S_RXCTRL) 18 bits */
+#define   I2S_RXCTRL_DATASIZE_16_Val      _U_(0x4)   /**< \brief (I2S_RXCTRL) 16 bits */
+#define   I2S_RXCTRL_DATASIZE_16C_Val     _U_(0x5)   /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
+#define   I2S_RXCTRL_DATASIZE_8_Val       _U_(0x6)   /**< \brief (I2S_RXCTRL) 8 bits */
+#define   I2S_RXCTRL_DATASIZE_8C_Val      _U_(0x7)   /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
+#define I2S_RXCTRL_DATASIZE_32      (I2S_RXCTRL_DATASIZE_32_Val    << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_24      (I2S_RXCTRL_DATASIZE_24_Val    << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_20      (I2S_RXCTRL_DATASIZE_20_Val    << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_18      (I2S_RXCTRL_DATASIZE_18_Val    << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_16      (I2S_RXCTRL_DATASIZE_16_Val    << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_16C     (I2S_RXCTRL_DATASIZE_16C_Val   << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_8       (I2S_RXCTRL_DATASIZE_8_Val     << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_DATASIZE_8C      (I2S_RXCTRL_DATASIZE_8C_Val    << I2S_RXCTRL_DATASIZE_Pos)
+#define I2S_RXCTRL_WORDADJ_Pos      12           /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
+#define I2S_RXCTRL_WORDADJ          (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
+#define   I2S_RXCTRL_WORDADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
+#define   I2S_RXCTRL_WORDADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
+#define I2S_RXCTRL_WORDADJ_RIGHT    (I2S_RXCTRL_WORDADJ_RIGHT_Val  << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_WORDADJ_LEFT     (I2S_RXCTRL_WORDADJ_LEFT_Val   << I2S_RXCTRL_WORDADJ_Pos)
+#define I2S_RXCTRL_EXTEND_Pos       13           /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
+#define I2S_RXCTRL_EXTEND_Msk       (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND(value)    (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
+#define   I2S_RXCTRL_EXTEND_ZERO_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) Extend with zeroes */
+#define   I2S_RXCTRL_EXTEND_ONE_Val       _U_(0x1)   /**< \brief (I2S_RXCTRL) Extend with ones */
+#define   I2S_RXCTRL_EXTEND_MSBIT_Val     _U_(0x2)   /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
+#define   I2S_RXCTRL_EXTEND_LSBIT_Val     _U_(0x3)   /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
+#define I2S_RXCTRL_EXTEND_ZERO      (I2S_RXCTRL_EXTEND_ZERO_Val    << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_ONE       (I2S_RXCTRL_EXTEND_ONE_Val     << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_MSBIT     (I2S_RXCTRL_EXTEND_MSBIT_Val   << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_EXTEND_LSBIT     (I2S_RXCTRL_EXTEND_LSBIT_Val   << I2S_RXCTRL_EXTEND_Pos)
+#define I2S_RXCTRL_BITREV_Pos       15           /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
+#define I2S_RXCTRL_BITREV           (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
+#define   I2S_RXCTRL_BITREV_MSBIT_Val     _U_(0x0)   /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define   I2S_RXCTRL_BITREV_LSBIT_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_RXCTRL_BITREV_MSBIT     (I2S_RXCTRL_BITREV_MSBIT_Val   << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_BITREV_LSBIT     (I2S_RXCTRL_BITREV_LSBIT_Val   << I2S_RXCTRL_BITREV_Pos)
+#define I2S_RXCTRL_SLOTDIS0_Pos     16           /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS0         (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
+#define I2S_RXCTRL_SLOTDIS1_Pos     17           /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS1         (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
+#define I2S_RXCTRL_SLOTDIS2_Pos     18           /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS2         (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
+#define I2S_RXCTRL_SLOTDIS3_Pos     19           /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS3         (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
+#define I2S_RXCTRL_SLOTDIS4_Pos     20           /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS4         (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
+#define I2S_RXCTRL_SLOTDIS5_Pos     21           /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS5         (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
+#define I2S_RXCTRL_SLOTDIS6_Pos     22           /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS6         (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
+#define I2S_RXCTRL_SLOTDIS7_Pos     23           /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS7         (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
+#define I2S_RXCTRL_SLOTDIS_Pos      16           /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
+#define I2S_RXCTRL_SLOTDIS_Msk      (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
+#define I2S_RXCTRL_SLOTDIS(value)   (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
+#define I2S_RXCTRL_MONO_Pos         24           /**< \brief (I2S_RXCTRL) Mono Mode */
+#define I2S_RXCTRL_MONO             (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
+#define   I2S_RXCTRL_MONO_STEREO_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) Normal mode */
+#define   I2S_RXCTRL_MONO_MONO_Val        _U_(0x1)   /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
+#define I2S_RXCTRL_MONO_STEREO      (I2S_RXCTRL_MONO_STEREO_Val    << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_MONO_MONO        (I2S_RXCTRL_MONO_MONO_Val      << I2S_RXCTRL_MONO_Pos)
+#define I2S_RXCTRL_DMA_Pos          25           /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
+#define I2S_RXCTRL_DMA              (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
+#define   I2S_RXCTRL_DMA_SINGLE_Val       _U_(0x0)   /**< \brief (I2S_RXCTRL) Single DMA channel */
+#define   I2S_RXCTRL_DMA_MULTIPLE_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
+#define I2S_RXCTRL_DMA_SINGLE       (I2S_RXCTRL_DMA_SINGLE_Val     << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_DMA_MULTIPLE     (I2S_RXCTRL_DMA_MULTIPLE_Val   << I2S_RXCTRL_DMA_Pos)
+#define I2S_RXCTRL_RXLOOP_Pos       26           /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
+#define I2S_RXCTRL_RXLOOP           (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
+#define I2S_RXCTRL_MASK             _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
+
+/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_TXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_TXDATA_OFFSET           0x30         /**< \brief (I2S_TXDATA offset) Tx Data */
+#define I2S_TXDATA_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
+
+#define I2S_TXDATA_DATA_Pos         0            /**< \brief (I2S_TXDATA) Sample Data */
+#define I2S_TXDATA_DATA_Msk         (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
+#define I2S_TXDATA_DATA(value)      (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
+#define I2S_TXDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
+
+/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/  32) Rx Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} I2S_RXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_RXDATA_OFFSET           0x34         /**< \brief (I2S_RXDATA offset) Rx Data */
+#define I2S_RXDATA_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
+
+#define I2S_RXDATA_DATA_Pos         0            /**< \brief (I2S_RXDATA) Sample Data */
+#define I2S_RXDATA_DATA_Msk         (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
+#define I2S_RXDATA_DATA(value)      (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
+#define I2S_RXDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO I2S_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x3];
+  __IO I2S_CLKCTRL_Type          CLKCTRL[2];  /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+  __IO I2S_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x2];
+  __IO I2S_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x2];
+  __IO I2S_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x2];
+  __I  I2S_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x18 (R/  16) Synchronization Status */
+       RoReg8                    Reserved5[0x6];
+  __IO I2S_TXCTRL_Type           TXCTRL;      /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
+  __IO I2S_RXCTRL_Type           RXCTRL;      /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
+       RoReg8                    Reserved6[0x8];
+  __O  I2S_TXDATA_Type           TXDATA;      /**< \brief Offset: 0x30 ( /W 32) Tx Data */
+  __I  I2S_RXDATA_Type           RXDATA;      /**< \brief Offset: 0x34 (R/  32) Rx Data */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_I2S_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/icm.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/icm.h
new file mode 100644
index 000000000..d163bc160
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/icm.h	
@@ -0,0 +1,582 @@
+/**
+ * \file
+ *
+ * \brief Component description for ICM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_ICM_COMPONENT_
+#define _SAME53_ICM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ICM */
+/* ========================================================================== */
+/** \addtogroup SAME53_ICM Integrity Check Monitor */
+/*@{*/
+
+#define ICM_U2010
+#define REV_ICM                     0x120
+
+/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WBDIS:1;          /*!< bit:      0  Write Back Disable                 */
+    uint32_t EOMDIS:1;         /*!< bit:      1  End of Monitoring Disable          */
+    uint32_t SLBDIS:1;         /*!< bit:      2  Secondary List Branching Disable   */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t BBC:4;            /*!< bit:  4.. 7  Bus Burden Control                 */
+    uint32_t ASCD:1;           /*!< bit:      8  Automatic Switch To Compare Digest */
+    uint32_t DUALBUFF:1;       /*!< bit:      9  Dual Input Buffer                  */
+    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint32_t UIHASH:1;         /*!< bit:     12  User Initial Hash Value            */
+    uint32_t UALGO:3;          /*!< bit: 13..15  User SHA Algorithm                 */
+    uint32_t HAPROT:6;         /*!< bit: 16..21  Region Hash Area Protection        */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t DAPROT:6;         /*!< bit: 24..29  Region Descriptor Area Protection  */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_CFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_CFG_OFFSET              0x00         /**< \brief (ICM_CFG offset) Configuration */
+#define ICM_CFG_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */
+
+#define ICM_CFG_WBDIS_Pos           0            /**< \brief (ICM_CFG) Write Back Disable */
+#define ICM_CFG_WBDIS               (_U_(0x1) << ICM_CFG_WBDIS_Pos)
+#define ICM_CFG_EOMDIS_Pos          1            /**< \brief (ICM_CFG) End of Monitoring Disable */
+#define ICM_CFG_EOMDIS              (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
+#define ICM_CFG_SLBDIS_Pos          2            /**< \brief (ICM_CFG) Secondary List Branching Disable */
+#define ICM_CFG_SLBDIS              (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
+#define ICM_CFG_BBC_Pos             4            /**< \brief (ICM_CFG) Bus Burden Control */
+#define ICM_CFG_BBC_Msk             (_U_(0xF) << ICM_CFG_BBC_Pos)
+#define ICM_CFG_BBC(value)          (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
+#define ICM_CFG_ASCD_Pos            8            /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
+#define ICM_CFG_ASCD                (_U_(0x1) << ICM_CFG_ASCD_Pos)
+#define ICM_CFG_DUALBUFF_Pos        9            /**< \brief (ICM_CFG) Dual Input Buffer */
+#define ICM_CFG_DUALBUFF            (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
+#define ICM_CFG_UIHASH_Pos          12           /**< \brief (ICM_CFG) User Initial Hash Value */
+#define ICM_CFG_UIHASH              (_U_(0x1) << ICM_CFG_UIHASH_Pos)
+#define ICM_CFG_UALGO_Pos           13           /**< \brief (ICM_CFG) User SHA Algorithm */
+#define ICM_CFG_UALGO_Msk           (_U_(0x7) << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO(value)        (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
+#define   ICM_CFG_UALGO_SHA1_Val          _U_(0x0)   /**< \brief (ICM_CFG) SHA1 Algorithm */
+#define   ICM_CFG_UALGO_SHA256_Val        _U_(0x1)   /**< \brief (ICM_CFG) SHA256 Algorithm */
+#define   ICM_CFG_UALGO_SHA224_Val        _U_(0x4)   /**< \brief (ICM_CFG) SHA224 Algorithm */
+#define ICM_CFG_UALGO_SHA1          (ICM_CFG_UALGO_SHA1_Val        << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO_SHA256        (ICM_CFG_UALGO_SHA256_Val      << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_UALGO_SHA224        (ICM_CFG_UALGO_SHA224_Val      << ICM_CFG_UALGO_Pos)
+#define ICM_CFG_HAPROT_Pos          16           /**< \brief (ICM_CFG) Region Hash Area Protection */
+#define ICM_CFG_HAPROT_Msk          (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
+#define ICM_CFG_HAPROT(value)       (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
+#define ICM_CFG_DAPROT_Pos          24           /**< \brief (ICM_CFG) Region Descriptor Area Protection */
+#define ICM_CFG_DAPROT_Msk          (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
+#define ICM_CFG_DAPROT(value)       (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
+#define ICM_CFG_MASK                _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */
+
+/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  ICM Enable                         */
+    uint32_t DISABLE:1;        /*!< bit:      1  ICM Disable Register               */
+    uint32_t SWRST:1;          /*!< bit:      2  Software Reset                     */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t REHASH:4;         /*!< bit:  4.. 7  Recompute Internal Hash            */
+    uint32_t RMDIS:4;          /*!< bit:  8..11  Region Monitoring Disable          */
+    uint32_t RMEN:4;           /*!< bit: 12..15  Region Monitoring Enable           */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_CTRL_OFFSET             0x04         /**< \brief (ICM_CTRL offset) Control */
+
+#define ICM_CTRL_ENABLE_Pos         0            /**< \brief (ICM_CTRL) ICM Enable */
+#define ICM_CTRL_ENABLE             (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
+#define ICM_CTRL_DISABLE_Pos        1            /**< \brief (ICM_CTRL) ICM Disable Register */
+#define ICM_CTRL_DISABLE            (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
+#define ICM_CTRL_SWRST_Pos          2            /**< \brief (ICM_CTRL) Software Reset */
+#define ICM_CTRL_SWRST              (_U_(0x1) << ICM_CTRL_SWRST_Pos)
+#define ICM_CTRL_REHASH_Pos         4            /**< \brief (ICM_CTRL) Recompute Internal Hash */
+#define ICM_CTRL_REHASH_Msk         (_U_(0xF) << ICM_CTRL_REHASH_Pos)
+#define ICM_CTRL_REHASH(value)      (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
+#define ICM_CTRL_RMDIS_Pos          8            /**< \brief (ICM_CTRL) Region Monitoring Disable */
+#define ICM_CTRL_RMDIS_Msk          (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
+#define ICM_CTRL_RMDIS(value)       (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
+#define ICM_CTRL_RMEN_Pos           12           /**< \brief (ICM_CTRL) Region Monitoring Enable */
+#define ICM_CTRL_RMEN_Msk           (_U_(0xF) << ICM_CTRL_RMEN_Pos)
+#define ICM_CTRL_RMEN(value)        (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
+#define ICM_CTRL_MASK               _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */
+
+/* -------- ICM_SR : (ICM Offset: 0x08) (R/  32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  ICM Controller Enable Register     */
+    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
+    uint32_t RAWRMDIS:4;       /*!< bit:  8..11  RAW Region Monitoring Disabled Status */
+    uint32_t RMDIS:4;          /*!< bit: 12..15  Region Monitoring Disabled Status  */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_SR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_SR_OFFSET               0x08         /**< \brief (ICM_SR offset) Status */
+#define ICM_SR_RESETVALUE           _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */
+
+#define ICM_SR_ENABLE_Pos           0            /**< \brief (ICM_SR) ICM Controller Enable Register */
+#define ICM_SR_ENABLE               (_U_(0x1) << ICM_SR_ENABLE_Pos)
+#define ICM_SR_RAWRMDIS_Pos         8            /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
+#define ICM_SR_RAWRMDIS_Msk         (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
+#define ICM_SR_RAWRMDIS(value)      (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
+#define ICM_SR_RMDIS_Pos            12           /**< \brief (ICM_SR) Region Monitoring Disabled Status */
+#define ICM_SR_RMDIS_Msk            (_U_(0xF) << ICM_SR_RMDIS_Pos)
+#define ICM_SR_RMDIS(value)         (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
+#define ICM_SR_MASK                 _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */
+
+/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed Interrupt Enable */
+    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch Interrupt Enable */
+    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error Interrupt Enable  */
+    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition detected Interrupt Enable */
+    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition Detected Interrupt Enable */
+    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Interrupt Disable */
+    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Interrupt Enable */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IER_OFFSET              0x10         /**< \brief (ICM_IER offset) Interrupt Enable */
+
+#define ICM_IER_RHC_Pos             0            /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
+#define ICM_IER_RHC_Msk             (_U_(0xF) << ICM_IER_RHC_Pos)
+#define ICM_IER_RHC(value)          (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
+#define ICM_IER_RDM_Pos             4            /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
+#define ICM_IER_RDM_Msk             (_U_(0xF) << ICM_IER_RDM_Pos)
+#define ICM_IER_RDM(value)          (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
+#define ICM_IER_RBE_Pos             8            /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
+#define ICM_IER_RBE_Msk             (_U_(0xF) << ICM_IER_RBE_Pos)
+#define ICM_IER_RBE(value)          (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
+#define ICM_IER_RWC_Pos             12           /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
+#define ICM_IER_RWC_Msk             (_U_(0xF) << ICM_IER_RWC_Pos)
+#define ICM_IER_RWC(value)          (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
+#define ICM_IER_REC_Pos             16           /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
+#define ICM_IER_REC_Msk             (_U_(0xF) << ICM_IER_REC_Pos)
+#define ICM_IER_REC(value)          (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
+#define ICM_IER_RSU_Pos             20           /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
+#define ICM_IER_RSU_Msk             (_U_(0xF) << ICM_IER_RSU_Pos)
+#define ICM_IER_RSU(value)          (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
+#define ICM_IER_URAD_Pos            24           /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
+#define ICM_IER_URAD                (_U_(0x1) << ICM_IER_URAD_Pos)
+#define ICM_IER_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */
+
+/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed Interrupt Disable */
+    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch Interrupt Disable */
+    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error Interrupt Disable */
+    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition Detected Interrupt Disable */
+    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition detected Interrupt Disable */
+    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Interrupt Disable */
+    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Interrupt Disable */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IDR_OFFSET              0x14         /**< \brief (ICM_IDR offset) Interrupt Disable */
+#define ICM_IDR_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */
+
+#define ICM_IDR_RHC_Pos             0            /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
+#define ICM_IDR_RHC_Msk             (_U_(0xF) << ICM_IDR_RHC_Pos)
+#define ICM_IDR_RHC(value)          (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
+#define ICM_IDR_RDM_Pos             4            /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
+#define ICM_IDR_RDM_Msk             (_U_(0xF) << ICM_IDR_RDM_Pos)
+#define ICM_IDR_RDM(value)          (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
+#define ICM_IDR_RBE_Pos             8            /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
+#define ICM_IDR_RBE_Msk             (_U_(0xF) << ICM_IDR_RBE_Pos)
+#define ICM_IDR_RBE(value)          (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
+#define ICM_IDR_RWC_Pos             12           /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
+#define ICM_IDR_RWC_Msk             (_U_(0xF) << ICM_IDR_RWC_Pos)
+#define ICM_IDR_RWC(value)          (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
+#define ICM_IDR_REC_Pos             16           /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
+#define ICM_IDR_REC_Msk             (_U_(0xF) << ICM_IDR_REC_Pos)
+#define ICM_IDR_REC(value)          (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
+#define ICM_IDR_RSU_Pos             20           /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
+#define ICM_IDR_RSU_Msk             (_U_(0xF) << ICM_IDR_RSU_Pos)
+#define ICM_IDR_RSU(value)          (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
+#define ICM_IDR_URAD_Pos            24           /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
+#define ICM_IDR_URAD                (_U_(0x1) << ICM_IDR_URAD_Pos)
+#define ICM_IDR_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */
+
+/* -------- ICM_IMR : (ICM Offset: 0x18) (R/  32) Interrupt Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed Interrupt Mask */
+    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch Interrupt Mask */
+    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error Interrupt Mask    */
+    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition Detected Interrupt Mask */
+    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition Detected Interrupt Mask */
+    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Interrupt Mask */
+    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Interrupt Mask */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_IMR_OFFSET              0x18         /**< \brief (ICM_IMR offset) Interrupt Mask */
+#define ICM_IMR_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */
+
+#define ICM_IMR_RHC_Pos             0            /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
+#define ICM_IMR_RHC_Msk             (_U_(0xF) << ICM_IMR_RHC_Pos)
+#define ICM_IMR_RHC(value)          (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
+#define ICM_IMR_RDM_Pos             4            /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
+#define ICM_IMR_RDM_Msk             (_U_(0xF) << ICM_IMR_RDM_Pos)
+#define ICM_IMR_RDM(value)          (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
+#define ICM_IMR_RBE_Pos             8            /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
+#define ICM_IMR_RBE_Msk             (_U_(0xF) << ICM_IMR_RBE_Pos)
+#define ICM_IMR_RBE(value)          (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
+#define ICM_IMR_RWC_Pos             12           /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
+#define ICM_IMR_RWC_Msk             (_U_(0xF) << ICM_IMR_RWC_Pos)
+#define ICM_IMR_RWC(value)          (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
+#define ICM_IMR_REC_Pos             16           /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
+#define ICM_IMR_REC_Msk             (_U_(0xF) << ICM_IMR_REC_Pos)
+#define ICM_IMR_REC(value)          (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
+#define ICM_IMR_RSU_Pos             20           /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
+#define ICM_IMR_RSU_Msk             (_U_(0xF) << ICM_IMR_RSU_Pos)
+#define ICM_IMR_RSU(value)          (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
+#define ICM_IMR_URAD_Pos            24           /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
+#define ICM_IMR_URAD                (_U_(0x1) << ICM_IMR_URAD_Pos)
+#define ICM_IMR_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */
+
+/* -------- ICM_ISR : (ICM Offset: 0x1C) (R/  32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed              */
+    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch             */
+    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error                   */
+    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition Detected     */
+    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition Detected  */
+    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Detected     */
+    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Status */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_ISR_OFFSET              0x1C         /**< \brief (ICM_ISR offset) Interrupt Status */
+#define ICM_ISR_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */
+
+#define ICM_ISR_RHC_Pos             0            /**< \brief (ICM_ISR) Region Hash Completed */
+#define ICM_ISR_RHC_Msk             (_U_(0xF) << ICM_ISR_RHC_Pos)
+#define ICM_ISR_RHC(value)          (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
+#define ICM_ISR_RDM_Pos             4            /**< \brief (ICM_ISR) Region Digest Mismatch */
+#define ICM_ISR_RDM_Msk             (_U_(0xF) << ICM_ISR_RDM_Pos)
+#define ICM_ISR_RDM(value)          (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
+#define ICM_ISR_RBE_Pos             8            /**< \brief (ICM_ISR) Region Bus Error */
+#define ICM_ISR_RBE_Msk             (_U_(0xF) << ICM_ISR_RBE_Pos)
+#define ICM_ISR_RBE(value)          (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
+#define ICM_ISR_RWC_Pos             12           /**< \brief (ICM_ISR) Region Wrap Condition Detected */
+#define ICM_ISR_RWC_Msk             (_U_(0xF) << ICM_ISR_RWC_Pos)
+#define ICM_ISR_RWC(value)          (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
+#define ICM_ISR_REC_Pos             16           /**< \brief (ICM_ISR) Region End bit Condition Detected */
+#define ICM_ISR_REC_Msk             (_U_(0xF) << ICM_ISR_REC_Pos)
+#define ICM_ISR_REC(value)          (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
+#define ICM_ISR_RSU_Pos             20           /**< \brief (ICM_ISR) Region Status Updated Detected */
+#define ICM_ISR_RSU_Msk             (_U_(0xF) << ICM_ISR_RSU_Pos)
+#define ICM_ISR_RSU(value)          (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
+#define ICM_ISR_URAD_Pos            24           /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
+#define ICM_ISR_URAD                (_U_(0x1) << ICM_ISR_URAD_Pos)
+#define ICM_ISR_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */
+
+/* -------- ICM_UASR : (ICM Offset: 0x20) (R/  32) Undefined Access Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t URAT:3;           /*!< bit:  0.. 2  Undefined Register Access Trace    */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_UASR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_UASR_OFFSET             0x20         /**< \brief (ICM_UASR offset) Undefined Access Status */
+#define ICM_UASR_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */
+
+#define ICM_UASR_URAT_Pos           0            /**< \brief (ICM_UASR) Undefined Register Access Trace */
+#define ICM_UASR_URAT_Msk           (_U_(0x7) << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT(value)        (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
+#define   ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0)   /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
+#define   ICM_UASR_URAT_CFG_MODIFIED_Val  _U_(0x1)   /**< \brief (ICM_UASR) CFG modified during active monitoring */
+#define   ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2)   /**< \brief (ICM_UASR) DSCR modified during active monitoring */
+#define   ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3)   /**< \brief (ICM_UASR) HASH modified during active monitoring */
+#define   ICM_UASR_URAT_READ_ACCESS_Val   _U_(0x4)   /**< \brief (ICM_UASR) Write-only register read access */
+#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_CFG_MODIFIED  (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_URAT_READ_ACCESS   (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
+#define ICM_UASR_MASK               _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */
+
+/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t DASA:26;          /*!< bit:  6..31  Descriptor Area Start Address      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_DSCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_DSCR_OFFSET             0x30         /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */
+#define ICM_DSCR_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */
+
+#define ICM_DSCR_DASA_Pos           6            /**< \brief (ICM_DSCR) Descriptor Area Start Address */
+#define ICM_DSCR_DASA_Msk           (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
+#define ICM_DSCR_DASA(value)        (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
+#define ICM_DSCR_MASK               _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */
+
+/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint32_t HASA:25;          /*!< bit:  7..31  Hash Area Start Address            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_HASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_HASH_OFFSET             0x34         /**< \brief (ICM_HASH offset) Region Hash Area Start Address */
+#define ICM_HASH_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */
+
+#define ICM_HASH_HASA_Pos           7            /**< \brief (ICM_HASH) Hash Area Start Address */
+#define ICM_HASH_HASA_Msk           (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
+#define ICM_HASH_HASA(value)        (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
+#define ICM_HASH_MASK               _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */
+
+/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t VAL:32;           /*!< bit:  0..31  Initial Hash Value                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_UIHVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_UIHVAL_OFFSET           0x38         /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */
+#define ICM_UIHVAL_RESETVALUE       _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */
+
+#define ICM_UIHVAL_VAL_Pos          0            /**< \brief (ICM_UIHVAL) Initial Hash Value */
+#define ICM_UIHVAL_VAL_Msk          (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
+#define ICM_UIHVAL_VAL(value)       (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
+#define ICM_UIHVAL_MASK             _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */
+
+/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_RADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RADDR_OFFSET            0x00         /**< \brief (ICM_RADDR offset) Region Start Address */
+#define ICM_RADDR_MASK              _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */
+
+/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CDWBN:1;          /*!< bit:      0  Compare Digest Write Back          */
+    uint32_t WRAP:1;           /*!< bit:      1  Region Wrap                        */
+    uint32_t EOM:1;            /*!< bit:      2  End of Monitoring                  */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RHIEN:1;          /*!< bit:      4  Region Hash Interrupt Enable       */
+    uint32_t DMIEN:1;          /*!< bit:      5  Region Digest Mismatch Interrupt Enable */
+    uint32_t BEIEN:1;          /*!< bit:      6  Region Bus Error Interrupt Enable  */
+    uint32_t WCIEN:1;          /*!< bit:      7  Region Wrap Condition Detected Interrupt Enable */
+    uint32_t ECIEN:1;          /*!< bit:      8  Region End bit Condition detected Interrupt Enable */
+    uint32_t SUIEN:1;          /*!< bit:      9  Region Status Updated Interrupt Enable */
+    uint32_t PROCDLY:1;        /*!< bit:     10  SHA Processing Delay               */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t ALGO:3;           /*!< bit: 12..14  SHA Algorithm                      */
+    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
+    uint32_t MRPROT:6;         /*!< bit: 24..29  Memory Region AHB Protection       */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_RCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RCFG_OFFSET             0x04         /**< \brief (ICM_RCFG offset) Region Configuration */
+#define ICM_RCFG_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */
+
+#define ICM_RCFG_CDWBN_Pos          0            /**< \brief (ICM_RCFG) Compare Digest Write Back */
+#define ICM_RCFG_CDWBN              (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
+#define   ICM_RCFG_CDWBN_WRBA_Val         _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_CDWBN_COMP_Val         _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_CDWBN_WRBA         (ICM_RCFG_CDWBN_WRBA_Val       << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_CDWBN_COMP         (ICM_RCFG_CDWBN_COMP_Val       << ICM_RCFG_CDWBN_Pos)
+#define ICM_RCFG_WRAP_Pos           1            /**< \brief (ICM_RCFG) Region Wrap */
+#define ICM_RCFG_WRAP               (_U_(0x1) << ICM_RCFG_WRAP_Pos)
+#define   ICM_RCFG_WRAP_NO_Val            _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_WRAP_YES_Val           _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_WRAP_NO            (ICM_RCFG_WRAP_NO_Val          << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_WRAP_YES           (ICM_RCFG_WRAP_YES_Val         << ICM_RCFG_WRAP_Pos)
+#define ICM_RCFG_EOM_Pos            2            /**< \brief (ICM_RCFG) End of Monitoring */
+#define ICM_RCFG_EOM                (_U_(0x1) << ICM_RCFG_EOM_Pos)
+#define   ICM_RCFG_EOM_NO_Val             _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_EOM_YES_Val            _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_EOM_NO             (ICM_RCFG_EOM_NO_Val           << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_EOM_YES            (ICM_RCFG_EOM_YES_Val          << ICM_RCFG_EOM_Pos)
+#define ICM_RCFG_RHIEN_Pos          4            /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */
+#define ICM_RCFG_RHIEN              (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
+#define   ICM_RCFG_RHIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_RHIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_RHIEN_EN           (ICM_RCFG_RHIEN_EN_Val         << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_RHIEN_DIS          (ICM_RCFG_RHIEN_DIS_Val        << ICM_RCFG_RHIEN_Pos)
+#define ICM_RCFG_DMIEN_Pos          5            /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */
+#define ICM_RCFG_DMIEN              (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
+#define   ICM_RCFG_DMIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_DMIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_DMIEN_EN           (ICM_RCFG_DMIEN_EN_Val         << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_DMIEN_DIS          (ICM_RCFG_DMIEN_DIS_Val        << ICM_RCFG_DMIEN_Pos)
+#define ICM_RCFG_BEIEN_Pos          6            /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */
+#define ICM_RCFG_BEIEN              (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
+#define   ICM_RCFG_BEIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_BEIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_BEIEN_EN           (ICM_RCFG_BEIEN_EN_Val         << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_BEIEN_DIS          (ICM_RCFG_BEIEN_DIS_Val        << ICM_RCFG_BEIEN_Pos)
+#define ICM_RCFG_WCIEN_Pos          7            /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */
+#define ICM_RCFG_WCIEN              (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
+#define   ICM_RCFG_WCIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_WCIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_WCIEN_EN           (ICM_RCFG_WCIEN_EN_Val         << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_WCIEN_DIS          (ICM_RCFG_WCIEN_DIS_Val        << ICM_RCFG_WCIEN_Pos)
+#define ICM_RCFG_ECIEN_Pos          8            /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */
+#define ICM_RCFG_ECIEN              (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
+#define   ICM_RCFG_ECIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_ECIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_ECIEN_EN           (ICM_RCFG_ECIEN_EN_Val         << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_ECIEN_DIS          (ICM_RCFG_ECIEN_DIS_Val        << ICM_RCFG_ECIEN_Pos)
+#define ICM_RCFG_SUIEN_Pos          9            /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */
+#define ICM_RCFG_SUIEN              (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
+#define   ICM_RCFG_SUIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_SUIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_SUIEN_EN           (ICM_RCFG_SUIEN_EN_Val         << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_SUIEN_DIS          (ICM_RCFG_SUIEN_DIS_Val        << ICM_RCFG_SUIEN_Pos)
+#define ICM_RCFG_PROCDLY_Pos        10           /**< \brief (ICM_RCFG) SHA Processing Delay */
+#define ICM_RCFG_PROCDLY            (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
+#define   ICM_RCFG_PROCDLY_SHORT_Val      _U_(0x0)   /**< \brief (ICM_RCFG)  */
+#define   ICM_RCFG_PROCDLY_LONG_Val       _U_(0x1)   /**< \brief (ICM_RCFG)  */
+#define ICM_RCFG_PROCDLY_SHORT      (ICM_RCFG_PROCDLY_SHORT_Val    << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_PROCDLY_LONG       (ICM_RCFG_PROCDLY_LONG_Val     << ICM_RCFG_PROCDLY_Pos)
+#define ICM_RCFG_ALGO_Pos           12           /**< \brief (ICM_RCFG) SHA Algorithm */
+#define ICM_RCFG_ALGO_Msk           (_U_(0x7) << ICM_RCFG_ALGO_Pos)
+#define ICM_RCFG_ALGO(value)        (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
+#define ICM_RCFG_MRPROT_Pos         24           /**< \brief (ICM_RCFG) Memory Region AHB Protection */
+#define ICM_RCFG_MRPROT_Msk         (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
+#define ICM_RCFG_MRPROT(value)      (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
+#define ICM_RCFG_MASK               _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */
+
+/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TRSIZE:16;        /*!< bit:  0..15  Transfer Size                      */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_RCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RCTRL_OFFSET            0x08         /**< \brief (ICM_RCTRL offset) Region Control */
+
+#define ICM_RCTRL_TRSIZE_Pos        0            /**< \brief (ICM_RCTRL) Transfer Size */
+#define ICM_RCTRL_TRSIZE_Msk        (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
+#define ICM_RCTRL_TRSIZE(value)     (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
+#define ICM_RCTRL_MASK              _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */
+
+/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} ICM_RNEXT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ICM_RNEXT_OFFSET            0x0C         /**< \brief (ICM_RNEXT offset) Region Next Address */
+#define ICM_RNEXT_MASK              _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */
+
+/** \brief ICM APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ICM_CFG_Type              CFG;         /**< \brief Offset: 0x00 (R/W 32) Configuration */
+  __O  ICM_CTRL_Type             CTRL;        /**< \brief Offset: 0x04 ( /W 32) Control */
+  __I  ICM_SR_Type               SR;          /**< \brief Offset: 0x08 (R/  32) Status */
+       RoReg8                    Reserved1[0x4];
+  __O  ICM_IER_Type              IER;         /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */
+  __O  ICM_IDR_Type              IDR;         /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */
+  __I  ICM_IMR_Type              IMR;         /**< \brief Offset: 0x18 (R/  32) Interrupt Mask */
+  __I  ICM_ISR_Type              ISR;         /**< \brief Offset: 0x1C (R/  32) Interrupt Status */
+  __I  ICM_UASR_Type             UASR;        /**< \brief Offset: 0x20 (R/  32) Undefined Access Status */
+       RoReg8                    Reserved2[0xC];
+  __IO ICM_DSCR_Type             DSCR;        /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
+  __IO ICM_HASH_Type             HASH;        /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */
+  __O  ICM_UIHVAL_Type           UIHVAL[8];   /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */
+} Icm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief ICM Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ICM_RADDR_Type            RADDR;       /**< \brief Offset: 0x00 (R/W 32) Region Start Address */
+  __IO ICM_RCFG_Type             RCFG;        /**< \brief Offset: 0x04 (R/W 32) Region Configuration */
+  __IO ICM_RCTRL_Type            RCTRL;       /**< \brief Offset: 0x08 (R/W 32) Region Control */
+  __IO ICM_RNEXT_Type            RNEXT;       /**< \brief Offset: 0x0C (R/W 32) Region Next Address */
+} IcmDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_ICM_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAME53_ICM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/mclk.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/mclk.h
new file mode 100644
index 000000000..f7e708607
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/mclk.h	
@@ -0,0 +1,477 @@
+/**
+ * \file
+ *
+ * \brief Component description for MCLK
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_MCLK_COMPONENT_
+#define _SAME53_MCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR MCLK */
+/* ========================================================================== */
+/** \addtogroup SAME53_MCLK Main Clock */
+/*@{*/
+
+#define MCLK_U2408
+#define REV_MCLK                    0x100
+
+/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENCLR_OFFSET        0x01         /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
+#define MCLK_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define MCLK_INTENCLR_CKRDY_Pos     0            /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
+#define MCLK_INTENCLR_CKRDY         (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
+#define MCLK_INTENCLR_MASK          _U_(0x01)    /**< \brief (MCLK_INTENCLR) MASK Register */
+
+/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENSET_OFFSET        0x02         /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
+#define MCLK_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
+
+#define MCLK_INTENSET_CKRDY_Pos     0            /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
+#define MCLK_INTENSET_CKRDY         (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
+#define MCLK_INTENSET_MASK          _U_(0x01)    /**< \brief (MCLK_INTENSET) MASK Register */
+
+/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTFLAG_OFFSET         0x03         /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
+#define MCLK_INTFLAG_RESETVALUE     _U_(0x01)    /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define MCLK_INTFLAG_CKRDY_Pos      0            /**< \brief (MCLK_INTFLAG) Clock Ready */
+#define MCLK_INTFLAG_CKRDY          (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
+#define MCLK_INTFLAG_MASK           _U_(0x01)    /**< \brief (MCLK_INTFLAG) MASK Register */
+
+/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/   8) HS Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIV:8;            /*!< bit:  0.. 7  CPU Clock Division Factor          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_HSDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_HSDIV_OFFSET           0x04         /**< \brief (MCLK_HSDIV offset) HS Clock Division */
+#define MCLK_HSDIV_RESETVALUE       _U_(0x01)    /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
+
+#define MCLK_HSDIV_DIV_Pos          0            /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
+#define MCLK_HSDIV_DIV_Msk          (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
+#define MCLK_HSDIV_DIV(value)       (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
+#define   MCLK_HSDIV_DIV_DIV1_Val         _U_(0x1)   /**< \brief (MCLK_HSDIV) Divide by 1 */
+#define MCLK_HSDIV_DIV_DIV1         (MCLK_HSDIV_DIV_DIV1_Val       << MCLK_HSDIV_DIV_Pos)
+#define MCLK_HSDIV_MASK             _U_(0xFF)    /**< \brief (MCLK_HSDIV) MASK Register */
+
+/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W  8) CPU Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIV:8;            /*!< bit:  0.. 7  Low-Power Clock Division Factor    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_CPUDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_CPUDIV_OFFSET          0x05         /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
+#define MCLK_CPUDIV_RESETVALUE      _U_(0x01)    /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
+
+#define MCLK_CPUDIV_DIV_Pos         0            /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
+#define MCLK_CPUDIV_DIV_Msk         (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV(value)      (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
+#define   MCLK_CPUDIV_DIV_DIV1_Val        _U_(0x1)   /**< \brief (MCLK_CPUDIV) Divide by 1 */
+#define   MCLK_CPUDIV_DIV_DIV2_Val        _U_(0x2)   /**< \brief (MCLK_CPUDIV) Divide by 2 */
+#define   MCLK_CPUDIV_DIV_DIV4_Val        _U_(0x4)   /**< \brief (MCLK_CPUDIV) Divide by 4 */
+#define   MCLK_CPUDIV_DIV_DIV8_Val        _U_(0x8)   /**< \brief (MCLK_CPUDIV) Divide by 8 */
+#define   MCLK_CPUDIV_DIV_DIV16_Val       _U_(0x10)   /**< \brief (MCLK_CPUDIV) Divide by 16 */
+#define   MCLK_CPUDIV_DIV_DIV32_Val       _U_(0x20)   /**< \brief (MCLK_CPUDIV) Divide by 32 */
+#define   MCLK_CPUDIV_DIV_DIV64_Val       _U_(0x40)   /**< \brief (MCLK_CPUDIV) Divide by 64 */
+#define   MCLK_CPUDIV_DIV_DIV128_Val      _U_(0x80)   /**< \brief (MCLK_CPUDIV) Divide by 128 */
+#define MCLK_CPUDIV_DIV_DIV1        (MCLK_CPUDIV_DIV_DIV1_Val      << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV2        (MCLK_CPUDIV_DIV_DIV2_Val      << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV4        (MCLK_CPUDIV_DIV_DIV4_Val      << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV8        (MCLK_CPUDIV_DIV_DIV8_Val      << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV16       (MCLK_CPUDIV_DIV_DIV16_Val     << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV32       (MCLK_CPUDIV_DIV_DIV32_Val     << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV64       (MCLK_CPUDIV_DIV_DIV64_Val     << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_DIV_DIV128      (MCLK_CPUDIV_DIV_DIV128_Val    << MCLK_CPUDIV_DIV_Pos)
+#define MCLK_CPUDIV_MASK            _U_(0xFF)    /**< \brief (MCLK_CPUDIV) MASK Register */
+
+/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t HPB3_:1;          /*!< bit:      3  HPB3 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      4  DSU AHB Clock Mask                 */
+    uint32_t HMATRIX_:1;       /*!< bit:      5  HMATRIX AHB Clock Mask             */
+    uint32_t NVMCTRL_:1;       /*!< bit:      6  NVMCTRL AHB Clock Mask             */
+    uint32_t HSRAM_:1;         /*!< bit:      7  HSRAM AHB Clock Mask               */
+    uint32_t CMCC_:1;          /*!< bit:      8  CMCC AHB Clock Mask                */
+    uint32_t DMAC_:1;          /*!< bit:      9  DMAC AHB Clock Mask                */
+    uint32_t USB_:1;           /*!< bit:     10  USB AHB Clock Mask                 */
+    uint32_t BKUPRAM_:1;       /*!< bit:     11  BKUPRAM AHB Clock Mask             */
+    uint32_t PAC_:1;           /*!< bit:     12  PAC AHB Clock Mask                 */
+    uint32_t QSPI_:1;          /*!< bit:     13  QSPI AHB Clock Mask                */
+    uint32_t GMAC_:1;          /*!< bit:     14  GMAC AHB Clock Mask                */
+    uint32_t SDHC0_:1;         /*!< bit:     15  SDHC0 AHB Clock Mask               */
+    uint32_t SDHC1_:1;         /*!< bit:     16  SDHC1 AHB Clock Mask               */
+    uint32_t :2;               /*!< bit: 17..18  Reserved                           */
+    uint32_t ICM_:1;           /*!< bit:     19  ICM AHB Clock Mask                 */
+    uint32_t PUKCC_:1;         /*!< bit:     20  PUKCC AHB Clock Mask               */
+    uint32_t QSPI_2X_:1;       /*!< bit:     21  QSPI_2X AHB Clock Mask             */
+    uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit:     22  NVMCTRL_SMEEPROM AHB Clock Mask    */
+    uint32_t NVMCTRL_CACHE_:1; /*!< bit:     23  NVMCTRL_CACHE AHB Clock Mask       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_AHBMASK_OFFSET         0x10         /**< \brief (MCLK_AHBMASK offset) AHB Mask */
+#define MCLK_AHBMASK_RESETVALUE     _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
+
+#define MCLK_AHBMASK_HPB0_Pos       0            /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB0           (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
+#define MCLK_AHBMASK_HPB1_Pos       1            /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB1           (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
+#define MCLK_AHBMASK_HPB2_Pos       2            /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB2           (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
+#define MCLK_AHBMASK_HPB3_Pos       3            /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB3           (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
+#define MCLK_AHBMASK_DSU_Pos        4            /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
+#define MCLK_AHBMASK_DSU            (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
+#define MCLK_AHBMASK_HMATRIX_Pos    5            /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
+#define MCLK_AHBMASK_HMATRIX        (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
+#define MCLK_AHBMASK_NVMCTRL_Pos    6            /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL        (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
+#define MCLK_AHBMASK_HSRAM_Pos      7            /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
+#define MCLK_AHBMASK_HSRAM          (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
+#define MCLK_AHBMASK_CMCC_Pos       8            /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
+#define MCLK_AHBMASK_CMCC           (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
+#define MCLK_AHBMASK_DMAC_Pos       9            /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
+#define MCLK_AHBMASK_DMAC           (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
+#define MCLK_AHBMASK_USB_Pos        10           /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
+#define MCLK_AHBMASK_USB            (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
+#define MCLK_AHBMASK_BKUPRAM_Pos    11           /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
+#define MCLK_AHBMASK_BKUPRAM        (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
+#define MCLK_AHBMASK_PAC_Pos        12           /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
+#define MCLK_AHBMASK_PAC            (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
+#define MCLK_AHBMASK_QSPI_Pos       13           /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
+#define MCLK_AHBMASK_QSPI           (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
+#define MCLK_AHBMASK_GMAC_Pos       14           /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */
+#define MCLK_AHBMASK_GMAC           (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
+#define MCLK_AHBMASK_SDHC0_Pos      15           /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC0          (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
+#define MCLK_AHBMASK_SDHC1_Pos      16           /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC1          (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
+#define MCLK_AHBMASK_ICM_Pos        19           /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
+#define MCLK_AHBMASK_ICM            (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
+#define MCLK_AHBMASK_PUKCC_Pos      20           /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
+#define MCLK_AHBMASK_PUKCC          (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
+#define MCLK_AHBMASK_QSPI_2X_Pos    21           /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
+#define MCLK_AHBMASK_QSPI_2X        (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22           /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
+#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23           /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_CACHE  (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
+#define MCLK_AHBMASK_MASK           _U_(0x00F9FFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
+
+/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Clock Enable               */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
+    uint32_t MCLK_:1;          /*!< bit:      2  MCLK APB Clock Enable              */
+    uint32_t RSTC_:1;          /*!< bit:      3  RSTC APB Clock Enable              */
+    uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL APB Clock Enable           */
+    uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL APB Clock Enable        */
+    uint32_t SUPC_:1;          /*!< bit:      6  SUPC APB Clock Enable              */
+    uint32_t GCLK_:1;          /*!< bit:      7  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      8  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      9  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:     10  EIC APB Clock Enable               */
+    uint32_t FREQM_:1;         /*!< bit:     11  FREQM APB Clock Enable             */
+    uint32_t SERCOM0_:1;       /*!< bit:     12  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:     13  SERCOM1 APB Clock Enable           */
+    uint32_t TC0_:1;           /*!< bit:     14  TC0 APB Clock Enable               */
+    uint32_t TC1_:1;           /*!< bit:     15  TC1 APB Clock Enable               */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBAMASK_OFFSET        0x14         /**< \brief (MCLK_APBAMASK offset) APBA Mask */
+#define MCLK_APBAMASK_RESETVALUE    _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
+
+#define MCLK_APBAMASK_PAC_Pos       0            /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
+#define MCLK_APBAMASK_PAC           (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
+#define MCLK_APBAMASK_PM_Pos        1            /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
+#define MCLK_APBAMASK_PM            (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
+#define MCLK_APBAMASK_MCLK_Pos      2            /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
+#define MCLK_APBAMASK_MCLK          (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
+#define MCLK_APBAMASK_RSTC_Pos      3            /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
+#define MCLK_APBAMASK_RSTC          (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
+#define MCLK_APBAMASK_OSCCTRL_Pos   4            /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSCCTRL       (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
+#define MCLK_APBAMASK_OSC32KCTRL_Pos 5            /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSC32KCTRL    (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
+#define MCLK_APBAMASK_SUPC_Pos      6            /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
+#define MCLK_APBAMASK_SUPC          (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
+#define MCLK_APBAMASK_GCLK_Pos      7            /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
+#define MCLK_APBAMASK_GCLK          (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
+#define MCLK_APBAMASK_WDT_Pos       8            /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
+#define MCLK_APBAMASK_WDT           (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
+#define MCLK_APBAMASK_RTC_Pos       9            /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
+#define MCLK_APBAMASK_RTC           (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
+#define MCLK_APBAMASK_EIC_Pos       10           /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
+#define MCLK_APBAMASK_EIC           (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
+#define MCLK_APBAMASK_FREQM_Pos     11           /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
+#define MCLK_APBAMASK_FREQM         (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
+#define MCLK_APBAMASK_SERCOM0_Pos   12           /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM0       (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
+#define MCLK_APBAMASK_SERCOM1_Pos   13           /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM1       (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
+#define MCLK_APBAMASK_TC0_Pos       14           /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
+#define MCLK_APBAMASK_TC0           (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
+#define MCLK_APBAMASK_TC1_Pos       15           /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
+#define MCLK_APBAMASK_TC1           (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
+#define MCLK_APBAMASK_MASK          _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
+
+/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USB_:1;           /*!< bit:      0  USB APB Clock Enable               */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t PORT_:1;          /*!< bit:      4  PORT APB Clock Enable              */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
+    uint32_t EVSYS_:1;         /*!< bit:      7  EVSYS APB Clock Enable             */
+    uint32_t :1;               /*!< bit:      8  Reserved                           */
+    uint32_t SERCOM2_:1;       /*!< bit:      9  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:     10  SERCOM3 APB Clock Enable           */
+    uint32_t TCC0_:1;          /*!< bit:     11  TCC0 APB Clock Enable              */
+    uint32_t TCC1_:1;          /*!< bit:     12  TCC1 APB Clock Enable              */
+    uint32_t TC2_:1;           /*!< bit:     13  TC2 APB Clock Enable               */
+    uint32_t TC3_:1;           /*!< bit:     14  TC3 APB Clock Enable               */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t RAMECC_:1;        /*!< bit:     16  RAMECC APB Clock Enable            */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBBMASK_OFFSET        0x18         /**< \brief (MCLK_APBBMASK offset) APBB Mask */
+#define MCLK_APBBMASK_RESETVALUE    _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
+
+#define MCLK_APBBMASK_USB_Pos       0            /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
+#define MCLK_APBBMASK_USB           (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
+#define MCLK_APBBMASK_DSU_Pos       1            /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
+#define MCLK_APBBMASK_DSU           (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
+#define MCLK_APBBMASK_NVMCTRL_Pos   2            /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
+#define MCLK_APBBMASK_NVMCTRL       (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
+#define MCLK_APBBMASK_PORT_Pos      4            /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
+#define MCLK_APBBMASK_PORT          (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
+#define MCLK_APBBMASK_HMATRIX_Pos   6            /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
+#define MCLK_APBBMASK_HMATRIX       (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
+#define MCLK_APBBMASK_EVSYS_Pos     7            /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
+#define MCLK_APBBMASK_EVSYS         (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
+#define MCLK_APBBMASK_SERCOM2_Pos   9            /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM2       (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
+#define MCLK_APBBMASK_SERCOM3_Pos   10           /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM3       (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
+#define MCLK_APBBMASK_TCC0_Pos      11           /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
+#define MCLK_APBBMASK_TCC0          (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
+#define MCLK_APBBMASK_TCC1_Pos      12           /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
+#define MCLK_APBBMASK_TCC1          (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
+#define MCLK_APBBMASK_TC2_Pos       13           /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
+#define MCLK_APBBMASK_TC2           (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
+#define MCLK_APBBMASK_TC3_Pos       14           /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
+#define MCLK_APBBMASK_TC3           (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
+#define MCLK_APBBMASK_RAMECC_Pos    16           /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
+#define MCLK_APBBMASK_RAMECC        (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
+#define MCLK_APBBMASK_MASK          _U_(0x00017ED7) /**< \brief (MCLK_APBBMASK) MASK Register */
+
+/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t GMAC_:1;          /*!< bit:      2  GMAC APB Clock Enable              */
+    uint32_t TCC2_:1;          /*!< bit:      3  TCC2 APB Clock Enable              */
+    uint32_t TCC3_:1;          /*!< bit:      4  TCC3 APB Clock Enable              */
+    uint32_t TC4_:1;           /*!< bit:      5  TC4 APB Clock Enable               */
+    uint32_t TC5_:1;           /*!< bit:      6  TC5 APB Clock Enable               */
+    uint32_t PDEC_:1;          /*!< bit:      7  PDEC APB Clock Enable              */
+    uint32_t AC_:1;            /*!< bit:      8  AC APB Clock Enable                */
+    uint32_t AES_:1;           /*!< bit:      9  AES APB Clock Enable               */
+    uint32_t TRNG_:1;          /*!< bit:     10  TRNG APB Clock Enable              */
+    uint32_t ICM_:1;           /*!< bit:     11  ICM APB Clock Enable               */
+    uint32_t :1;               /*!< bit:     12  Reserved                           */
+    uint32_t QSPI_:1;          /*!< bit:     13  QSPI APB Clock Enable              */
+    uint32_t CCL_:1;           /*!< bit:     14  CCL APB Clock Enable               */
+    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBCMASK_OFFSET        0x1C         /**< \brief (MCLK_APBCMASK offset) APBC Mask */
+#define MCLK_APBCMASK_RESETVALUE    _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
+
+#define MCLK_APBCMASK_GMAC_Pos      2            /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */
+#define MCLK_APBCMASK_GMAC          (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
+#define MCLK_APBCMASK_TCC2_Pos      3            /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
+#define MCLK_APBCMASK_TCC2          (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
+#define MCLK_APBCMASK_TCC3_Pos      4            /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
+#define MCLK_APBCMASK_TCC3          (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
+#define MCLK_APBCMASK_TC4_Pos       5            /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
+#define MCLK_APBCMASK_TC4           (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
+#define MCLK_APBCMASK_TC5_Pos       6            /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
+#define MCLK_APBCMASK_TC5           (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
+#define MCLK_APBCMASK_PDEC_Pos      7            /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
+#define MCLK_APBCMASK_PDEC          (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
+#define MCLK_APBCMASK_AC_Pos        8            /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
+#define MCLK_APBCMASK_AC            (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
+#define MCLK_APBCMASK_AES_Pos       9            /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
+#define MCLK_APBCMASK_AES           (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
+#define MCLK_APBCMASK_TRNG_Pos      10           /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
+#define MCLK_APBCMASK_TRNG          (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
+#define MCLK_APBCMASK_ICM_Pos       11           /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
+#define MCLK_APBCMASK_ICM           (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
+#define MCLK_APBCMASK_QSPI_Pos      13           /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
+#define MCLK_APBCMASK_QSPI          (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
+#define MCLK_APBCMASK_CCL_Pos       14           /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
+#define MCLK_APBCMASK_CCL           (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
+#define MCLK_APBCMASK_MASK          _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */
+
+/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERCOM4_:1;       /*!< bit:      0  SERCOM4 APB Clock Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5 APB Clock Enable           */
+    uint32_t SERCOM6_:1;       /*!< bit:      2  SERCOM6 APB Clock Enable           */
+    uint32_t SERCOM7_:1;       /*!< bit:      3  SERCOM7 APB Clock Enable           */
+    uint32_t TCC4_:1;          /*!< bit:      4  TCC4 APB Clock Enable              */
+    uint32_t TC6_:1;           /*!< bit:      5  TC6 APB Clock Enable               */
+    uint32_t TC7_:1;           /*!< bit:      6  TC7 APB Clock Enable               */
+    uint32_t ADC0_:1;          /*!< bit:      7  ADC0 APB Clock Enable              */
+    uint32_t ADC1_:1;          /*!< bit:      8  ADC1 APB Clock Enable              */
+    uint32_t DAC_:1;           /*!< bit:      9  DAC APB Clock Enable               */
+    uint32_t I2S_:1;           /*!< bit:     10  I2S APB Clock Enable               */
+    uint32_t PCC_:1;           /*!< bit:     11  PCC APB Clock Enable               */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBDMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBDMASK_OFFSET        0x20         /**< \brief (MCLK_APBDMASK offset) APBD Mask */
+#define MCLK_APBDMASK_RESETVALUE    _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
+
+#define MCLK_APBDMASK_SERCOM4_Pos   0            /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM4       (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
+#define MCLK_APBDMASK_SERCOM5_Pos   1            /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM5       (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
+#define MCLK_APBDMASK_SERCOM6_Pos   2            /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM6       (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
+#define MCLK_APBDMASK_SERCOM7_Pos   3            /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM7       (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
+#define MCLK_APBDMASK_TCC4_Pos      4            /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
+#define MCLK_APBDMASK_TCC4          (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
+#define MCLK_APBDMASK_TC6_Pos       5            /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
+#define MCLK_APBDMASK_TC6           (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
+#define MCLK_APBDMASK_TC7_Pos       6            /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
+#define MCLK_APBDMASK_TC7           (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
+#define MCLK_APBDMASK_ADC0_Pos      7            /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
+#define MCLK_APBDMASK_ADC0          (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
+#define MCLK_APBDMASK_ADC1_Pos      8            /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
+#define MCLK_APBDMASK_ADC1          (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
+#define MCLK_APBDMASK_DAC_Pos       9            /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
+#define MCLK_APBDMASK_DAC           (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
+#define MCLK_APBDMASK_I2S_Pos       10           /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
+#define MCLK_APBDMASK_I2S           (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
+#define MCLK_APBDMASK_PCC_Pos       11           /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
+#define MCLK_APBDMASK_PCC           (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
+#define MCLK_APBDMASK_MASK          _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
+
+/** \brief MCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       RoReg8                    Reserved1[0x1];
+  __IO MCLK_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x01 (R/W  8) Interrupt Enable Clear */
+  __IO MCLK_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x02 (R/W  8) Interrupt Enable Set */
+  __IO MCLK_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x03 (R/W  8) Interrupt Flag Status and Clear */
+  __I  MCLK_HSDIV_Type           HSDIV;       /**< \brief Offset: 0x04 (R/   8) HS Clock Division */
+  __IO MCLK_CPUDIV_Type          CPUDIV;      /**< \brief Offset: 0x05 (R/W  8) CPU Clock Division */
+       RoReg8                    Reserved2[0xA];
+  __IO MCLK_AHBMASK_Type         AHBMASK;     /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
+  __IO MCLK_APBAMASK_Type        APBAMASK;    /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
+  __IO MCLK_APBBMASK_Type        APBBMASK;    /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
+  __IO MCLK_APBCMASK_Type        APBCMASK;    /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
+  __IO MCLK_APBDMASK_Type        APBDMASK;    /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
+} Mclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_MCLK_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/nvmctrl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/nvmctrl.h
new file mode 100644
index 000000000..786016e71
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/nvmctrl.h	
@@ -0,0 +1,787 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_NVMCTRL_COMPONENT_
+#define _SAME53_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME53_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2409
+#define REV_NVMCTRL                 0x100
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t AUTOWS:1;         /*!< bit:      2  Auto Wait State Enable             */
+    uint16_t SUSPEN:1;         /*!< bit:      3  Suspend Enable                     */
+    uint16_t WMODE:2;          /*!< bit:  4.. 5  Write Mode                         */
+    uint16_t PRM:2;            /*!< bit:  6.. 7  Power Reduction Mode during Sleep  */
+    uint16_t RWS:4;            /*!< bit:  8..11  NVM Read Wait States               */
+    uint16_t AHBNS0:1;         /*!< bit:     12  Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
+    uint16_t AHBNS1:1;         /*!< bit:     13  Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
+    uint16_t CACHEDIS0:1;      /*!< bit:     14  AHB0 Cache Disable                 */
+    uint16_t CACHEDIS1:1;      /*!< bit:     15  AHB1 Cache Disable                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    _U_(0x0004)  /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_AUTOWS_Pos    2            /**< \brief (NVMCTRL_CTRLA) Auto Wait State Enable */
+#define NVMCTRL_CTRLA_AUTOWS        (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos)
+#define NVMCTRL_CTRLA_SUSPEN_Pos    3            /**< \brief (NVMCTRL_CTRLA) Suspend Enable */
+#define NVMCTRL_CTRLA_SUSPEN        (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos)
+#define NVMCTRL_CTRLA_WMODE_Pos     4            /**< \brief (NVMCTRL_CTRLA) Write Mode */
+#define NVMCTRL_CTRLA_WMODE_Msk     (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE(value)  (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
+#define   NVMCTRL_CTRLA_WMODE_MAN_Val     _U_(0x0)   /**< \brief (NVMCTRL_CTRLA) Manual Write */
+#define   NVMCTRL_CTRLA_WMODE_ADW_Val     _U_(0x1)   /**< \brief (NVMCTRL_CTRLA) Automatic Double Word Write */
+#define   NVMCTRL_CTRLA_WMODE_AQW_Val     _U_(0x2)   /**< \brief (NVMCTRL_CTRLA) Automatic Quad Word */
+#define   NVMCTRL_CTRLA_WMODE_AP_Val      _U_(0x3)   /**< \brief (NVMCTRL_CTRLA) Automatic Page Write */
+#define NVMCTRL_CTRLA_WMODE_MAN     (NVMCTRL_CTRLA_WMODE_MAN_Val   << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE_ADW     (NVMCTRL_CTRLA_WMODE_ADW_Val   << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE_AQW     (NVMCTRL_CTRLA_WMODE_AQW_Val   << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_WMODE_AP      (NVMCTRL_CTRLA_WMODE_AP_Val    << NVMCTRL_CTRLA_WMODE_Pos)
+#define NVMCTRL_CTRLA_PRM_Pos       6            /**< \brief (NVMCTRL_CTRLA) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLA_PRM_Msk       (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_PRM(value)    (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
+#define   NVMCTRL_CTRLA_PRM_SEMIAUTO_Val  _U_(0x0)   /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLA_PRM_FULLAUTO_Val  _U_(0x1)   /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */
+#define   NVMCTRL_CTRLA_PRM_MANUAL_Val    _U_(0x3)   /**< \brief (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
+#define NVMCTRL_CTRLA_PRM_SEMIAUTO  (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_PRM_FULLAUTO  (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_PRM_MANUAL    (NVMCTRL_CTRLA_PRM_MANUAL_Val  << NVMCTRL_CTRLA_PRM_Pos)
+#define NVMCTRL_CTRLA_RWS_Pos       8            /**< \brief (NVMCTRL_CTRLA) NVM Read Wait States */
+#define NVMCTRL_CTRLA_RWS_Msk       (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos)
+#define NVMCTRL_CTRLA_RWS(value)    (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
+#define NVMCTRL_CTRLA_AHBNS0_Pos    12           /**< \brief (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
+#define NVMCTRL_CTRLA_AHBNS0        (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos)
+#define NVMCTRL_CTRLA_AHBNS1_Pos    13           /**< \brief (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
+#define NVMCTRL_CTRLA_AHBNS1        (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos)
+#define NVMCTRL_CTRLA_CACHEDIS0_Pos 14           /**< \brief (NVMCTRL_CTRLA) AHB0 Cache Disable */
+#define NVMCTRL_CTRLA_CACHEDIS0     (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos)
+#define NVMCTRL_CTRLA_CACHEDIS1_Pos 15           /**< \brief (NVMCTRL_CTRLA) AHB1 Cache Disable */
+#define NVMCTRL_CTRLA_CACHEDIS1     (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos)
+#define NVMCTRL_CTRLA_MASK          _U_(0xFFFC)  /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    _U_(0x0000)  /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLB) Command */
+#define NVMCTRL_CTRLB_CMD_Msk       (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD(value)    (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
+#define   NVMCTRL_CTRLB_CMD_EP_Val        _U_(0x0)   /**< \brief (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */
+#define   NVMCTRL_CTRLB_CMD_EB_Val        _U_(0x1)   /**< \brief (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */
+#define   NVMCTRL_CTRLB_CMD_WP_Val        _U_(0x3)   /**< \brief (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */
+#define   NVMCTRL_CTRLB_CMD_WQW_Val       _U_(0x4)   /**< \brief (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */
+#define   NVMCTRL_CTRLB_CMD_SWRST_Val     _U_(0x10)   /**< \brief (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */
+#define   NVMCTRL_CTRLB_CMD_LR_Val        _U_(0x11)   /**< \brief (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLB_CMD_UR_Val        _U_(0x12)   /**< \brief (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLB_CMD_SPRM_Val      _U_(0x13)   /**< \brief (NVMCTRL_CTRLB) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLB_CMD_CPRM_Val      _U_(0x14)   /**< \brief (NVMCTRL_CTRLB) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLB_CMD_PBC_Val       _U_(0x15)   /**< \brief (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLB_CMD_SSB_Val       _U_(0x16)   /**< \brief (NVMCTRL_CTRLB) Set Security Bit */
+#define   NVMCTRL_CTRLB_CMD_BKSWRST_Val   _U_(0x17)   /**< \brief (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */
+#define   NVMCTRL_CTRLB_CMD_CELCK_Val     _U_(0x18)   /**< \brief (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */
+#define   NVMCTRL_CTRLB_CMD_CEULCK_Val    _U_(0x19)   /**< \brief (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */
+#define   NVMCTRL_CTRLB_CMD_SBPDIS_Val    _U_(0x1A)   /**< \brief (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */
+#define   NVMCTRL_CTRLB_CMD_CBPDIS_Val    _U_(0x1B)   /**< \brief (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */
+#define   NVMCTRL_CTRLB_CMD_ASEES0_Val    _U_(0x30)   /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */
+#define   NVMCTRL_CTRLB_CMD_ASEES1_Val    _U_(0x31)   /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */
+#define   NVMCTRL_CTRLB_CMD_SEERALOC_Val  _U_(0x32)   /**< \brief (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */
+#define   NVMCTRL_CTRLB_CMD_SEEFLUSH_Val  _U_(0x33)   /**< \brief (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode */
+#define   NVMCTRL_CTRLB_CMD_LSEE_Val      _U_(0x34)   /**< \brief (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */
+#define   NVMCTRL_CTRLB_CMD_USEE_Val      _U_(0x35)   /**< \brief (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */
+#define   NVMCTRL_CTRLB_CMD_LSEER_Val     _U_(0x36)   /**< \brief (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */
+#define   NVMCTRL_CTRLB_CMD_USEER_Val     _U_(0x37)   /**< \brief (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */
+#define NVMCTRL_CTRLB_CMD_EP        (NVMCTRL_CTRLB_CMD_EP_Val      << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_EB        (NVMCTRL_CTRLB_CMD_EB_Val      << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_WP        (NVMCTRL_CTRLB_CMD_WP_Val      << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_WQW       (NVMCTRL_CTRLB_CMD_WQW_Val     << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SWRST     (NVMCTRL_CTRLB_CMD_SWRST_Val   << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_LR        (NVMCTRL_CTRLB_CMD_LR_Val      << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_UR        (NVMCTRL_CTRLB_CMD_UR_Val      << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SPRM      (NVMCTRL_CTRLB_CMD_SPRM_Val    << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CPRM      (NVMCTRL_CTRLB_CMD_CPRM_Val    << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_PBC       (NVMCTRL_CTRLB_CMD_PBC_Val     << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SSB       (NVMCTRL_CTRLB_CMD_SSB_Val     << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_BKSWRST   (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CELCK     (NVMCTRL_CTRLB_CMD_CELCK_Val   << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CEULCK    (NVMCTRL_CTRLB_CMD_CEULCK_Val  << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SBPDIS    (NVMCTRL_CTRLB_CMD_SBPDIS_Val  << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_CBPDIS    (NVMCTRL_CTRLB_CMD_CBPDIS_Val  << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_ASEES0    (NVMCTRL_CTRLB_CMD_ASEES0_Val  << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_ASEES1    (NVMCTRL_CTRLB_CMD_ASEES1_Val  << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SEERALOC  (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_SEEFLUSH  (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_LSEE      (NVMCTRL_CTRLB_CMD_LSEE_Val    << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_USEE      (NVMCTRL_CTRLB_CMD_USEE_Val    << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_LSEER     (NVMCTRL_CTRLB_CMD_LSEER_Val   << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMD_USEER     (NVMCTRL_CTRLB_CMD_USEER_Val   << NVMCTRL_CTRLB_CMD_Pos)
+#define NVMCTRL_CTRLB_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLB) Command Execution */
+#define NVMCTRL_CTRLB_CMDEX_Msk     (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos)
+#define NVMCTRL_CTRLB_CMDEX(value)  (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
+#define   NVMCTRL_CTRLB_CMDEX_KEY_Val     _U_(0xA5)   /**< \brief (NVMCTRL_CTRLB) Execution Key */
+#define NVMCTRL_CTRLB_CMDEX_KEY     (NVMCTRL_CTRLB_CMDEX_KEY_Val   << NVMCTRL_CTRLB_CMDEX_Pos)
+#define NVMCTRL_CTRLB_MASK          _U_(0xFF7F)  /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/  32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :12;              /*!< bit: 19..30  Reserved                           */
+    uint32_t SEE:1;            /*!< bit:     31  SmartEEPROM Supported              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    _U_(0x00060000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define   NVMCTRL_PARAM_PSZ_8_Val         _U_(0x0)   /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        _U_(0x1)   /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        _U_(0x2)   /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        _U_(0x3)   /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       _U_(0x4)   /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       _U_(0x5)   /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       _U_(0x6)   /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      _U_(0x7)   /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_SEE_Pos       31           /**< \brief (NVMCTRL_PARAM) SmartEEPROM Supported */
+#define NVMCTRL_PARAM_SEE           (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos)
+#define NVMCTRL_PARAM_MASK          _U_(0x8007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DONE:1;           /*!< bit:      0  Command Done Interrupt Clear       */
+    uint16_t ADDRE:1;          /*!< bit:      1  Address Error                      */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Interrupt Clear  */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Interrupt Clear         */
+    uint16_t ECCSE:1;          /*!< bit:      4  ECC Single Error Interrupt Clear   */
+    uint16_t ECCDE:1;          /*!< bit:      5  ECC Dual Error Interrupt Clear     */
+    uint16_t NVME:1;           /*!< bit:      6  NVM Error Interrupt Clear          */
+    uint16_t SUSP:1;           /*!< bit:      7  Suspended Write Or Erase Interrupt Clear */
+    uint16_t SEESFULL:1;       /*!< bit:      8  Active SEES Full Interrupt Clear   */
+    uint16_t SEESOVF:1;        /*!< bit:      9  Active SEES Overflow Interrupt Clear */
+    uint16_t SEEWRC:1;         /*!< bit:     10  SEE Write Completed Interrupt Clear */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_DONE_Pos   0            /**< \brief (NVMCTRL_INTENCLR) Command Done Interrupt Clear */
+#define NVMCTRL_INTENCLR_DONE       (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos)
+#define NVMCTRL_INTENCLR_ADDRE_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Address Error */
+#define NVMCTRL_INTENCLR_ADDRE      (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos)
+#define NVMCTRL_INTENCLR_PROGE_Pos  2            /**< \brief (NVMCTRL_INTENCLR) Programming Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_PROGE      (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos)
+#define NVMCTRL_INTENCLR_LOCKE_Pos  3            /**< \brief (NVMCTRL_INTENCLR) Lock Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_LOCKE      (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos)
+#define NVMCTRL_INTENCLR_ECCSE_Pos  4            /**< \brief (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_ECCSE      (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos)
+#define NVMCTRL_INTENCLR_ECCDE_Pos  5            /**< \brief (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_ECCDE      (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos)
+#define NVMCTRL_INTENCLR_NVME_Pos   6            /**< \brief (NVMCTRL_INTENCLR) NVM Error Interrupt Clear */
+#define NVMCTRL_INTENCLR_NVME       (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos)
+#define NVMCTRL_INTENCLR_SUSP_Pos   7            /**< \brief (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear */
+#define NVMCTRL_INTENCLR_SUSP       (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos)
+#define NVMCTRL_INTENCLR_SEESFULL_Pos 8            /**< \brief (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear */
+#define NVMCTRL_INTENCLR_SEESFULL   (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos)
+#define NVMCTRL_INTENCLR_SEESOVF_Pos 9            /**< \brief (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear */
+#define NVMCTRL_INTENCLR_SEESOVF    (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos)
+#define NVMCTRL_INTENCLR_SEEWRC_Pos 10           /**< \brief (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear */
+#define NVMCTRL_INTENCLR_SEEWRC     (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos)
+#define NVMCTRL_INTENCLR_MASK       _U_(0x07FF)  /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DONE:1;           /*!< bit:      0  Command Done Interrupt Enable      */
+    uint16_t ADDRE:1;          /*!< bit:      1  Address Error Interrupt Enable     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Interrupt Enable */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Interrupt Enable        */
+    uint16_t ECCSE:1;          /*!< bit:      4  ECC Single Error Interrupt Enable  */
+    uint16_t ECCDE:1;          /*!< bit:      5  ECC Dual Error Interrupt Enable    */
+    uint16_t NVME:1;           /*!< bit:      6  NVM Error Interrupt Enable         */
+    uint16_t SUSP:1;           /*!< bit:      7  Suspended Write Or Erase  Interrupt Enable */
+    uint16_t SEESFULL:1;       /*!< bit:      8  Active SEES Full Interrupt Enable  */
+    uint16_t SEESOVF:1;        /*!< bit:      9  Active SEES Overflow Interrupt Enable */
+    uint16_t SEEWRC:1;         /*!< bit:     10  SEE Write Completed Interrupt Enable */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x0E         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_DONE_Pos   0            /**< \brief (NVMCTRL_INTENSET) Command Done Interrupt Enable */
+#define NVMCTRL_INTENSET_DONE       (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos)
+#define NVMCTRL_INTENSET_ADDRE_Pos  1            /**< \brief (NVMCTRL_INTENSET) Address Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ADDRE      (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos)
+#define NVMCTRL_INTENSET_PROGE_Pos  2            /**< \brief (NVMCTRL_INTENSET) Programming Error Interrupt Enable */
+#define NVMCTRL_INTENSET_PROGE      (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos)
+#define NVMCTRL_INTENSET_LOCKE_Pos  3            /**< \brief (NVMCTRL_INTENSET) Lock Error Interrupt Enable */
+#define NVMCTRL_INTENSET_LOCKE      (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos)
+#define NVMCTRL_INTENSET_ECCSE_Pos  4            /**< \brief (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ECCSE      (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos)
+#define NVMCTRL_INTENSET_ECCDE_Pos  5            /**< \brief (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ECCDE      (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos)
+#define NVMCTRL_INTENSET_NVME_Pos   6            /**< \brief (NVMCTRL_INTENSET) NVM Error Interrupt Enable */
+#define NVMCTRL_INTENSET_NVME       (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos)
+#define NVMCTRL_INTENSET_SUSP_Pos   7            /**< \brief (NVMCTRL_INTENSET) Suspended Write Or Erase  Interrupt Enable */
+#define NVMCTRL_INTENSET_SUSP       (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos)
+#define NVMCTRL_INTENSET_SEESFULL_Pos 8            /**< \brief (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable */
+#define NVMCTRL_INTENSET_SEESFULL   (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos)
+#define NVMCTRL_INTENSET_SEESOVF_Pos 9            /**< \brief (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable */
+#define NVMCTRL_INTENSET_SEESOVF    (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos)
+#define NVMCTRL_INTENSET_SEEWRC_Pos 10           /**< \brief (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable */
+#define NVMCTRL_INTENSET_SEEWRC     (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos)
+#define NVMCTRL_INTENSET_MASK       _U_(0x07FF)  /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t DONE:1;           /*!< bit:      0  Command Done                       */
+    __I uint16_t ADDRE:1;          /*!< bit:      1  Address Error                      */
+    __I uint16_t PROGE:1;          /*!< bit:      2  Programming Error                  */
+    __I uint16_t LOCKE:1;          /*!< bit:      3  Lock Error                         */
+    __I uint16_t ECCSE:1;          /*!< bit:      4  ECC Single Error                   */
+    __I uint16_t ECCDE:1;          /*!< bit:      5  ECC Dual Error                     */
+    __I uint16_t NVME:1;           /*!< bit:      6  NVM Error                          */
+    __I uint16_t SUSP:1;           /*!< bit:      7  Suspended Write Or Erase Operation */
+    __I uint16_t SEESFULL:1;       /*!< bit:      8  Active SEES Full                   */
+    __I uint16_t SEESOVF:1;        /*!< bit:      9  Active SEES Overflow               */
+    __I uint16_t SEEWRC:1;         /*!< bit:     10  SEE Write Completed                */
+    __I uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x10         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  _U_(0x0000)  /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_DONE_Pos    0            /**< \brief (NVMCTRL_INTFLAG) Command Done */
+#define NVMCTRL_INTFLAG_DONE        (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos)
+#define NVMCTRL_INTFLAG_ADDRE_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Address Error */
+#define NVMCTRL_INTFLAG_ADDRE       (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos)
+#define NVMCTRL_INTFLAG_PROGE_Pos   2            /**< \brief (NVMCTRL_INTFLAG) Programming Error */
+#define NVMCTRL_INTFLAG_PROGE       (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos)
+#define NVMCTRL_INTFLAG_LOCKE_Pos   3            /**< \brief (NVMCTRL_INTFLAG) Lock Error */
+#define NVMCTRL_INTFLAG_LOCKE       (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos)
+#define NVMCTRL_INTFLAG_ECCSE_Pos   4            /**< \brief (NVMCTRL_INTFLAG) ECC Single Error */
+#define NVMCTRL_INTFLAG_ECCSE       (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos)
+#define NVMCTRL_INTFLAG_ECCDE_Pos   5            /**< \brief (NVMCTRL_INTFLAG) ECC Dual Error */
+#define NVMCTRL_INTFLAG_ECCDE       (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos)
+#define NVMCTRL_INTFLAG_NVME_Pos    6            /**< \brief (NVMCTRL_INTFLAG) NVM Error */
+#define NVMCTRL_INTFLAG_NVME        (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos)
+#define NVMCTRL_INTFLAG_SUSP_Pos    7            /**< \brief (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation */
+#define NVMCTRL_INTFLAG_SUSP        (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos)
+#define NVMCTRL_INTFLAG_SEESFULL_Pos 8            /**< \brief (NVMCTRL_INTFLAG) Active SEES Full */
+#define NVMCTRL_INTFLAG_SEESFULL    (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos)
+#define NVMCTRL_INTFLAG_SEESOVF_Pos 9            /**< \brief (NVMCTRL_INTFLAG) Active SEES Overflow */
+#define NVMCTRL_INTFLAG_SEESOVF     (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos)
+#define NVMCTRL_INTFLAG_SEEWRC_Pos  10           /**< \brief (NVMCTRL_INTFLAG) SEE Write Completed */
+#define NVMCTRL_INTFLAG_SEEWRC      (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos)
+#define NVMCTRL_INTFLAG_MASK        _U_(0x07FF)  /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) (R/  16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t READY:1;          /*!< bit:      0  Ready to accept a command          */
+    uint16_t PRM:1;            /*!< bit:      1  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      2  NVM Page Buffer Active Loading     */
+    uint16_t SUSP:1;           /*!< bit:      3  NVM Write Or Erase Operation Is Suspended */
+    uint16_t AFIRST:1;         /*!< bit:      4  BANKA First                        */
+    uint16_t BPDIS:1;          /*!< bit:      5  Boot Loader Protection Disable     */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t BOOTPROT:4;       /*!< bit:  8..11  Boot Loader Protection Size        */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x12         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   _U_(0x0000)  /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_READY_Pos    0            /**< \brief (NVMCTRL_STATUS) Ready to accept a command */
+#define NVMCTRL_STATUS_READY        (_U_(0x1) << NVMCTRL_STATUS_READY_Pos)
+#define NVMCTRL_STATUS_PRM_Pos      1            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     2            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_SUSP_Pos     3            /**< \brief (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended */
+#define NVMCTRL_STATUS_SUSP         (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos)
+#define NVMCTRL_STATUS_AFIRST_Pos   4            /**< \brief (NVMCTRL_STATUS) BANKA First */
+#define NVMCTRL_STATUS_AFIRST       (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos)
+#define NVMCTRL_STATUS_BPDIS_Pos    5            /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Disable */
+#define NVMCTRL_STATUS_BPDIS        (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos)
+#define NVMCTRL_STATUS_BOOTPROT_Pos 8            /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Size */
+#define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos)
+#define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
+#define NVMCTRL_STATUS_MASK         _U_(0x0F3F)  /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:24;          /*!< bit:  0..23  NVM Address                        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x14         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK           _U_(0x00FFFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) (R/  32) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RUNLOCK:32;       /*!< bit:  0..31  Region Un-Lock Bits                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_RUNLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_RUNLOCK_OFFSET      0x18         /**< \brief (NVMCTRL_RUNLOCK offset) Lock Section */
+#define NVMCTRL_RUNLOCK_RESETVALUE  _U_(0x00000000) /**< \brief (NVMCTRL_RUNLOCK reset_value) Lock Section */
+
+#define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0            /**< \brief (NVMCTRL_RUNLOCK) Region Un-Lock Bits */
+#define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)
+#define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
+#define NVMCTRL_RUNLOCK_MASK        _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_RUNLOCK) MASK Register */
+
+/* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) (R/  32) Page Buffer Load Data x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Page Buffer Data                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PBLDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PBLDATA_OFFSET      0x1C         /**< \brief (NVMCTRL_PBLDATA offset) Page Buffer Load Data x */
+#define NVMCTRL_PBLDATA_RESETVALUE  _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA reset_value) Page Buffer Load Data x */
+
+#define NVMCTRL_PBLDATA_DATA_Pos    0            /**< \brief (NVMCTRL_PBLDATA) Page Buffer Data */
+#define NVMCTRL_PBLDATA_DATA_Msk    (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos)
+#define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
+#define NVMCTRL_PBLDATA_MASK        _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA) MASK Register */
+
+/* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) (R/  32) ECC Error Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:24;          /*!< bit:  0..23  Error Address                      */
+    uint32_t :4;               /*!< bit: 24..27  Reserved                           */
+    uint32_t TYPEL:2;          /*!< bit: 28..29  Low Double-Word Error Type         */
+    uint32_t TYPEH:2;          /*!< bit: 30..31  High Double-Word Error Type        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ECCERR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ECCERR_OFFSET       0x24         /**< \brief (NVMCTRL_ECCERR offset) ECC Error Status Register */
+#define NVMCTRL_ECCERR_RESETVALUE   _U_(0x00000000) /**< \brief (NVMCTRL_ECCERR reset_value) ECC Error Status Register */
+
+#define NVMCTRL_ECCERR_ADDR_Pos     0            /**< \brief (NVMCTRL_ECCERR) Error Address */
+#define NVMCTRL_ECCERR_ADDR_Msk     (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos)
+#define NVMCTRL_ECCERR_ADDR(value)  (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
+#define NVMCTRL_ECCERR_TYPEL_Pos    28           /**< \brief (NVMCTRL_ECCERR) Low Double-Word Error Type */
+#define NVMCTRL_ECCERR_TYPEL_Msk    (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
+#define   NVMCTRL_ECCERR_TYPEL_NONE_Val   _U_(0x0)   /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
+#define   NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1)   /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
+#define   NVMCTRL_ECCERR_TYPEL_DUAL_Val   _U_(0x2)   /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
+#define NVMCTRL_ECCERR_TYPEL_NONE   (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEL_DUAL   (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos)
+#define NVMCTRL_ECCERR_TYPEH_Pos    30           /**< \brief (NVMCTRL_ECCERR) High Double-Word Error Type */
+#define NVMCTRL_ECCERR_TYPEH_Msk    (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
+#define   NVMCTRL_ECCERR_TYPEH_NONE_Val   _U_(0x0)   /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
+#define   NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1)   /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
+#define   NVMCTRL_ECCERR_TYPEH_DUAL_Val   _U_(0x2)   /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
+#define NVMCTRL_ECCERR_TYPEH_NONE   (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_TYPEH_DUAL   (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos)
+#define NVMCTRL_ECCERR_MASK         _U_(0xF0FFFFFF) /**< \brief (NVMCTRL_ECCERR) MASK Register */
+
+/* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ECCDIS:1;         /*!< bit:      0  Debugger ECC Read Disable          */
+    uint8_t  ECCELOG:1;        /*!< bit:      1  Debugger ECC Error Tracking Mode   */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_DBGCTRL_OFFSET      0x28         /**< \brief (NVMCTRL_DBGCTRL offset) Debug Control */
+#define NVMCTRL_DBGCTRL_RESETVALUE  _U_(0x00)    /**< \brief (NVMCTRL_DBGCTRL reset_value) Debug Control */
+
+#define NVMCTRL_DBGCTRL_ECCDIS_Pos  0            /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Read Disable */
+#define NVMCTRL_DBGCTRL_ECCDIS      (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos)
+#define NVMCTRL_DBGCTRL_ECCELOG_Pos 1            /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode */
+#define NVMCTRL_DBGCTRL_ECCELOG     (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos)
+#define NVMCTRL_DBGCTRL_MASK        _U_(0x03)    /**< \brief (NVMCTRL_DBGCTRL) MASK Register */
+
+/* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W  8) SmartEEPROM Configuration Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WMODE:1;          /*!< bit:      0  Write Mode                         */
+    uint8_t  APRDIS:1;         /*!< bit:      1  Automatic Page Reallocation Disable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_SEECFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_SEECFG_OFFSET       0x2A         /**< \brief (NVMCTRL_SEECFG offset) SmartEEPROM Configuration Register */
+#define NVMCTRL_SEECFG_RESETVALUE   _U_(0x00)    /**< \brief (NVMCTRL_SEECFG reset_value) SmartEEPROM Configuration Register */
+
+#define NVMCTRL_SEECFG_WMODE_Pos    0            /**< \brief (NVMCTRL_SEECFG) Write Mode */
+#define NVMCTRL_SEECFG_WMODE        (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos)
+#define   NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0)   /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */
+#define   NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1)   /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested */
+#define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
+#define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
+#define NVMCTRL_SEECFG_APRDIS_Pos   1            /**< \brief (NVMCTRL_SEECFG) Automatic Page Reallocation Disable */
+#define NVMCTRL_SEECFG_APRDIS       (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos)
+#define NVMCTRL_SEECFG_MASK         _U_(0x03)    /**< \brief (NVMCTRL_SEECFG) MASK Register */
+
+/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) (R/  32) SmartEEPROM Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ASEES:1;          /*!< bit:      0  Active SmartEEPROM Sector          */
+    uint32_t LOAD:1;           /*!< bit:      1  Page Buffer Loaded                 */
+    uint32_t BUSY:1;           /*!< bit:      2  Busy                               */
+    uint32_t LOCK:1;           /*!< bit:      3  SmartEEPROM Write Access Is Locked */
+    uint32_t RLOCK:1;          /*!< bit:      4  SmartEEPROM Write Access To Register Address Space Is Locked */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t SBLK:4;           /*!< bit:  8..11  Blocks Number In a Sector          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t PSZ:3;            /*!< bit: 16..18  SmartEEPROM Page Size              */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_SEESTAT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_SEESTAT_OFFSET      0x2C         /**< \brief (NVMCTRL_SEESTAT offset) SmartEEPROM Status Register */
+#define NVMCTRL_SEESTAT_RESETVALUE  _U_(0x00000000) /**< \brief (NVMCTRL_SEESTAT reset_value) SmartEEPROM Status Register */
+
+#define NVMCTRL_SEESTAT_ASEES_Pos   0            /**< \brief (NVMCTRL_SEESTAT) Active SmartEEPROM Sector */
+#define NVMCTRL_SEESTAT_ASEES       (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos)
+#define NVMCTRL_SEESTAT_LOAD_Pos    1            /**< \brief (NVMCTRL_SEESTAT) Page Buffer Loaded */
+#define NVMCTRL_SEESTAT_LOAD        (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos)
+#define NVMCTRL_SEESTAT_BUSY_Pos    2            /**< \brief (NVMCTRL_SEESTAT) Busy */
+#define NVMCTRL_SEESTAT_BUSY        (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos)
+#define NVMCTRL_SEESTAT_LOCK_Pos    3            /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked */
+#define NVMCTRL_SEESTAT_LOCK        (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos)
+#define NVMCTRL_SEESTAT_RLOCK_Pos   4            /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked */
+#define NVMCTRL_SEESTAT_RLOCK       (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos)
+#define NVMCTRL_SEESTAT_SBLK_Pos    8            /**< \brief (NVMCTRL_SEESTAT) Blocks Number In a Sector */
+#define NVMCTRL_SEESTAT_SBLK_Msk    (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos)
+#define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
+#define NVMCTRL_SEESTAT_PSZ_Pos     16           /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Page Size */
+#define NVMCTRL_SEESTAT_PSZ_Msk     (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos)
+#define NVMCTRL_SEESTAT_PSZ(value)  (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
+#define NVMCTRL_SEESTAT_MASK        _U_(0x00070F1F) /**< \brief (NVMCTRL_SEESTAT) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __O  NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 ( /W 16) Control B */
+       RoReg8                    Reserved2[0x2];
+  __I  NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/  32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set */
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */
+  __I  NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x12 (R/  16) Status */
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x14 (R/W 32) Address */
+  __I  NVMCTRL_RUNLOCK_Type      RUNLOCK;     /**< \brief Offset: 0x18 (R/  32) Lock Section */
+  __I  NVMCTRL_PBLDATA_Type      PBLDATA[2];  /**< \brief Offset: 0x1C (R/  32) Page Buffer Load Data x */
+  __I  NVMCTRL_ECCERR_Type       ECCERR;      /**< \brief Offset: 0x24 (R/  32) ECC Error Status Register */
+  __IO NVMCTRL_DBGCTRL_Type      DBGCTRL;     /**< \brief Offset: 0x28 (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO NVMCTRL_SEECFG_Type       SEECFG;      /**< \brief Offset: 0x2A (R/W  8) SmartEEPROM Configuration Register */
+       RoReg8                    Reserved4[0x1];
+  __I  NVMCTRL_SEESTAT_Type      SEESTAT;     /**< \brief Offset: 0x2C (R/  32) SmartEEPROM Status Register */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_SW0
+#define SECTION_NVMCTRL_TEMP_LOG
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define AC_FUSES_BIAS0_ADDR         NVMCTRL_SW0
+#define AC_FUSES_BIAS0_Pos          0            /**< \brief (NVMCTRL_SW0) PAIR0 Bias Calibration */
+#define AC_FUSES_BIAS0_Msk          (_U_(0x3) << AC_FUSES_BIAS0_Pos)
+#define AC_FUSES_BIAS0(value)       (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos))
+
+#define ADC0_FUSES_BIASCOMP_ADDR    NVMCTRL_SW0
+#define ADC0_FUSES_BIASCOMP_Pos     2            /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
+#define ADC0_FUSES_BIASCOMP_Msk     (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
+#define ADC0_FUSES_BIASCOMP(value)  (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
+
+#define ADC0_FUSES_BIASR2R_ADDR     NVMCTRL_SW0
+#define ADC0_FUSES_BIASR2R_Pos      8            /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
+#define ADC0_FUSES_BIASR2R_Msk      (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos)
+#define ADC0_FUSES_BIASR2R(value)   (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos))
+
+#define ADC0_FUSES_BIASREFBUF_ADDR  NVMCTRL_SW0
+#define ADC0_FUSES_BIASREFBUF_Pos   5            /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
+#define ADC0_FUSES_BIASREFBUF_Msk   (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
+#define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
+
+#define ADC1_FUSES_BIASCOMP_ADDR    NVMCTRL_SW0
+#define ADC1_FUSES_BIASCOMP_Pos     16           /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
+#define ADC1_FUSES_BIASCOMP_Msk     (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
+#define ADC1_FUSES_BIASCOMP(value)  (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
+
+#define ADC1_FUSES_BIASR2R_ADDR     NVMCTRL_SW0
+#define ADC1_FUSES_BIASR2R_Pos      22           /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
+#define ADC1_FUSES_BIASR2R_Msk      (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos)
+#define ADC1_FUSES_BIASR2R(value)   (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos))
+
+#define ADC1_FUSES_BIASREFBUF_ADDR  NVMCTRL_SW0
+#define ADC1_FUSES_BIASREFBUF_Pos   19           /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
+#define ADC1_FUSES_BIASREFBUF_Msk   (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
+#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    1            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      9            /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_DIS_ADDR        NVMCTRL_USER
+#define FUSES_BOD33_DIS_Pos         0            /**< \brief (NVMCTRL_USER) BOD33 Disable */
+#define FUSES_BOD33_DIS_Msk         (_U_(0x1) << FUSES_BOD33_DIS_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       NVMCTRL_USER
+#define FUSES_BOD33_HYST_Pos        11           /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (_U_(0xF) << FUSES_BOD33_HYST_Pos)
+#define FUSES_BOD33_HYST(value)     (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos))
+
+#define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
+#define FUSES_HOT_ADC_VAL_CTAT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature CTAT */
+#define FUSES_HOT_ADC_VAL_CTAT_Msk  (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos)
+#define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos))
+
+#define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_PTAT_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature PTAT */
+#define FUSES_HOT_ADC_VAL_PTAT_Msk  (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos)
+#define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk     (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
+#define FUSES_ROOM_ADC_VAL_CTAT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature CTAT */
+#define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos)
+#define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos))
+
+#define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_PTAT_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature PTAT */
+#define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos)
+#define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk    (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  26           /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 0            /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+#define NVMCTRL_FUSES_SEEPSZ_ADDR   (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_SEEPSZ_Pos    4            /**< \brief (NVMCTRL_USER) Size Of SmartEEPROM Page */
+#define NVMCTRL_FUSES_SEEPSZ_Msk    (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos)
+#define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos))
+
+#define NVMCTRL_FUSES_SEESBLK_ADDR  (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_SEESBLK_Pos   0            /**< \brief (NVMCTRL_USER) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector */
+#define NVMCTRL_FUSES_SEESBLK_Msk   (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos)
+#define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos))
+
+#define RAMECC_FUSES_ECCDIS_ADDR    (NVMCTRL_USER + 4)
+#define RAMECC_FUSES_ECCDIS_Pos     7            /**< \brief (NVMCTRL_USER) RAM ECC Disable fuse */
+#define RAMECC_FUSES_ECCDIS_Msk     (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos)
+
+#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_SW0 + 4)
+#define USB_FUSES_TRANSN_Pos        0            /**< \brief (NVMCTRL_SW0) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk        (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_SW0 + 4)
+#define USB_FUSES_TRANSP_Pos        5            /**< \brief (NVMCTRL_SW0) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk        (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR         (NVMCTRL_SW0 + 4)
+#define USB_FUSES_TRIM_Pos          10           /**< \brief (NVMCTRL_SW0) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk          (_U_(0x7) << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_ALWAYSON_Pos      17           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       (NVMCTRL_USER + 4)
+#define WDT_FUSES_ENABLE_Pos        16           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      26           /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_PER_Pos           18           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (_U_(0xF) << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           30           /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (_U_(0x1) << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_ADDR       (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_Pos        22           /**< \brief (NVMCTRL_USER) WDT Window */
+#define WDT_FUSES_WINDOW_Msk        (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
+#define WDT_FUSES_WINDOW(value)     (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
+
+/*@}*/
+
+#endif /* _SAME53_NVMCTRL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/osc32kctrl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/osc32kctrl.h
new file mode 100644
index 000000000..45b6e4392
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/osc32kctrl.h	
@@ -0,0 +1,303 @@
+/**
+ * \file
+ *
+ * \brief Component description for OSC32KCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_OSC32KCTRL_COMPONENT_
+#define _SAME53_OSC32KCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR OSC32KCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME53_OSC32KCTRL 32kHz Oscillators Control */
+/*@{*/
+
+#define OSC32KCTRL_U2400
+#define REV_OSC32KCTRL              0x100
+
+/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready Interrupt Enable     */
+    uint32_t :1;               /*!< bit:      1  Reserved                           */
+    uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector Interrupt Enable */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENCLR_OFFSET  0x00         /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTENCLR_MASK    _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
+
+/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready Interrupt Enable     */
+    uint32_t :1;               /*!< bit:      1  Reserved                           */
+    uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector Interrupt Enable */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENSET_OFFSET  0x04         /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTENSET_MASK    _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
+
+/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready                      */
+    __I uint32_t :1;               /*!< bit:      1  Reserved                           */
+    __I uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector     */
+    __I uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTFLAG_OFFSET   0x08         /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_INTFLAG_MASK     _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
+
+/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready                      */
+    uint32_t :1;               /*!< bit:      1  Reserved                           */
+    uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector     */
+    uint32_t XOSC32KSW:1;      /*!< bit:      3  XOSC32K Clock switch               */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_STATUS_OFFSET    0x0C         /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
+#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
+
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
+#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
+#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
+#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
+#define OSC32KCTRL_STATUS_MASK      _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
+
+/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W  8) RTC Clock Selection -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RTCSEL:3;         /*!< bit:  0.. 2  RTC Clock Selection                */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSC32KCTRL_RTCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_RTCCTRL_OFFSET   0x10         /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00)    /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
+
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0            /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_MASK     _U_(0x07)    /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
+    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint16_t CGM:2;            /*!< bit: 13..14  Control Gain Mode                  */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_XOSC32K_OFFSET   0x14         /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080)  /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1            /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_ENABLE   (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
+#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2            /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_XTALEN   (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
+#define OSC32KCTRL_XOSC32K_EN32K_Pos 3            /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN32K    (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
+#define OSC32KCTRL_XOSC32K_EN1K_Pos 4            /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN1K     (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
+#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
+#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
+#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
+#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
+#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
+#define OSC32KCTRL_XOSC32K_WRTLOCK  (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
+#define OSC32KCTRL_XOSC32K_CGM_Pos  13           /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
+#define OSC32KCTRL_XOSC32K_CGM_Msk  (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
+#define   OSC32KCTRL_XOSC32K_CGM_XT_Val   _U_(0x1)   /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
+#define   OSC32KCTRL_XOSC32K_CGM_HS_Val   _U_(0x2)   /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
+#define OSC32KCTRL_XOSC32K_CGM_XT   (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_CGM_HS   (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
+#define OSC32KCTRL_XOSC32K_MASK     _U_(0x77DE)  /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
+
+/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W  8) Clock Failure Detector Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CFDEN:1;          /*!< bit:      0  Clock Failure Detector Enable      */
+    uint8_t  SWBACK:1;         /*!< bit:      1  Clock Switch Back                  */
+    uint8_t  CFDPRESC:1;       /*!< bit:      2  Clock Failure Detector Prescaler   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSC32KCTRL_CFDCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_CFDCTRL_OFFSET   0x16         /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
+#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00)    /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
+
+#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0            /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
+#define OSC32KCTRL_CFDCTRL_CFDEN    (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
+#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1            /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
+#define OSC32KCTRL_CFDCTRL_SWBACK   (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2            /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
+#define OSC32KCTRL_CFDCTRL_MASK     _U_(0x07)    /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CFDEO:1;          /*!< bit:      0  Clock Failure Detector Event Output Enable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSC32KCTRL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_EVCTRL_OFFSET    0x17         /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
+#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00)    /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
+
+#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0            /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
+#define OSC32KCTRL_EVCTRL_CFDEO     (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
+#define OSC32KCTRL_EVCTRL_MASK      _U_(0x01)    /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t EN32K:1;          /*!< bit:      1  Enable Out 32k                     */
+    uint32_t EN1K:1;           /*!< bit:      2  Enable Out 1k                      */
+    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint32_t CALIB:6;          /*!< bit:  8..13  Oscillator Calibration             */
+    uint32_t :1;               /*!< bit:     14  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C         /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1            /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
+#define OSC32KCTRL_OSCULP32K_EN32K  (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
+#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2            /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
+#define OSC32KCTRL_OSCULP32K_EN1K   (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8            /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
+#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
+#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15           /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
+#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
+#define OSC32KCTRL_OSCULP32K_MASK   _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
+
+/** \brief OSC32KCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO OSC32KCTRL_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO OSC32KCTRL_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO OSC32KCTRL_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  OSC32KCTRL_STATUS_Type    STATUS;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO OSC32KCTRL_RTCCTRL_Type   RTCCTRL;     /**< \brief Offset: 0x10 (R/W  8) RTC Clock Selection */
+       RoReg8                    Reserved1[0x3];
+  __IO OSC32KCTRL_XOSC32K_Type   XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+  __IO OSC32KCTRL_CFDCTRL_Type   CFDCTRL;     /**< \brief Offset: 0x16 (R/W  8) Clock Failure Detector Control */
+  __IO OSC32KCTRL_EVCTRL_Type    EVCTRL;      /**< \brief Offset: 0x17 (R/W  8) Event Control */
+       RoReg8                    Reserved2[0x4];
+  __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K;   /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+} Osc32kctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_OSC32KCTRL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/oscctrl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/oscctrl.h
new file mode 100644
index 000000000..0265621c5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/oscctrl.h	
@@ -0,0 +1,793 @@
+/**
+ * \file
+ *
+ * \brief Component description for OSCCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_OSCCTRL_COMPONENT_
+#define _SAME53_OSCCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR OSCCTRL */
+/* ========================================================================== */
+/** \addtogroup SAME53_OSCCTRL Oscillators Control */
+/*@{*/
+
+#define OSCCTRL_U2401
+#define REV_OSCCTRL                 0x100
+
+/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CFDEO0:1;         /*!< bit:      0  Clock 0 Failure Detector Event Output Enable */
+    uint8_t  CFDEO1:1;         /*!< bit:      1  Clock 1 Failure Detector Event Output Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  CFDEO:2;          /*!< bit:  0.. 1  Clock x Failure Detector Event Output Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_EVCTRL_OFFSET       0x00         /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
+#define OSCCTRL_EVCTRL_RESETVALUE   _U_(0x00)    /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
+
+#define OSCCTRL_EVCTRL_CFDEO0_Pos   0            /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO0       (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
+#define OSCCTRL_EVCTRL_CFDEO1_Pos   1            /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO1       (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
+#define OSCCTRL_EVCTRL_CFDEO_Pos    0            /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO_Msk    (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
+#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
+#define OSCCTRL_EVCTRL_MASK         _U_(0x03)    /**< \brief (OSCCTRL_EVCTRL) MASK Register */
+
+/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready Interrupt Enable      */
+    uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready Interrupt Enable      */
+    uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector Interrupt Enable */
+    uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector Interrupt Enable */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise Interrupt Enable   */
+    uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall Interrupt Enable   */
+    uint32_t DPLL0LTO:1;       /*!< bit:     18  DPLL0 Lock Timeout Interrupt Enable */
+    uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise Interrupt Enable   */
+    uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall Interrupt Enable   */
+    uint32_t DPLL1LTO:1;       /*!< bit:     26  DPLL1 Lock Timeout Interrupt Enable */
+    uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready Interrupt Enable      */
+    uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector Interrupt Enable */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENCLR_OFFSET     0x04         /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY0   (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY1   (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
+#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
+#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL0  (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL1  (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
+#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
+#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRDY    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
+#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLOOB    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKF   (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKC   (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
+#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRCS    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LCKR  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LCKF  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LTO   (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LCKR  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LCKF  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LTO   (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
+#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTENCLR_MASK       _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
+
+/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready Interrupt Enable      */
+    uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready Interrupt Enable      */
+    uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector Interrupt Enable */
+    uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector Interrupt Enable */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise Interrupt Enable   */
+    uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall Interrupt Enable   */
+    uint32_t DPLL0LTO:1;       /*!< bit:     18  DPLL0 Lock Timeout Interrupt Enable */
+    uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise Interrupt Enable   */
+    uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall Interrupt Enable   */
+    uint32_t DPLL1LTO:1;       /*!< bit:     26  DPLL1 Lock Timeout Interrupt Enable */
+    uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready Interrupt Enable      */
+    uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector Interrupt Enable */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENSET_OFFSET     0x08         /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSCCTRL_INTENSET_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY0   (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY1   (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
+#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
+#define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL0  (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL1  (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
+#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
+#define OSCCTRL_INTENSET_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRDY    (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
+#define OSCCTRL_INTENSET_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLOOB    (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKF   (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKC   (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
+#define OSCCTRL_INTENSET_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRCS    (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
+#define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LCKR  (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
+#define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LCKF  (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
+#define OSCCTRL_INTENSET_DPLL0LTO_Pos 18           /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LTO   (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
+#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LCKR  (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
+#define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LCKF  (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
+#define OSCCTRL_INTENSET_DPLL1LTO_Pos 26           /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LTO   (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
+#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTENSET_MASK       _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */
+
+/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready                       */
+    __I uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready                       */
+    __I uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector      */
+    __I uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector      */
+    __I uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    __I uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready                         */
+    __I uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds                 */
+    __I uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine                     */
+    __I uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse                   */
+    __I uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped       */
+    __I uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    __I uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise                    */
+    __I uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall                    */
+    __I uint32_t DPLL0LTO:1;       /*!< bit:     18  DPLL0 Lock Timeout                 */
+    __I uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete */
+    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    __I uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise                    */
+    __I uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall                    */
+    __I uint32_t DPLL1LTO:1;       /*!< bit:     26  DPLL1 Lock Timeout                 */
+    __I uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready                       */
+    __I uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector      */
+    __I uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTFLAG_OFFSET      0x0C         /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSCCTRL_INTFLAG_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY0    (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY1    (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
+#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
+#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL0   (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL1   (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
+#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
+#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
+#define OSCCTRL_INTFLAG_DFLLRDY     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
+#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
+#define OSCCTRL_INTFLAG_DFLLOOB     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
+#define OSCCTRL_INTFLAG_DFLLLCKF    (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
+#define OSCCTRL_INTFLAG_DFLLLCKC    (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
+#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define OSCCTRL_INTFLAG_DFLLRCS     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */
+#define OSCCTRL_INTFLAG_DPLL0LCKR   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */
+#define OSCCTRL_INTFLAG_DPLL0LCKF   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */
+#define OSCCTRL_INTFLAG_DPLL0LTO    (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */
+#define OSCCTRL_INTFLAG_DPLL0LDRTO  (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */
+#define OSCCTRL_INTFLAG_DPLL1LCKR   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */
+#define OSCCTRL_INTFLAG_DPLL1LCKF   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */
+#define OSCCTRL_INTFLAG_DPLL1LTO    (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
+#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */
+#define OSCCTRL_INTFLAG_DPLL1LDRTO  (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
+#define OSCCTRL_INTFLAG_MASK        _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
+
+/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/  32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready                       */
+    uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready                       */
+    uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector      */
+    uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector      */
+    uint32_t XOSCCKSW0:1;      /*!< bit:      4  XOSC 0 Clock Switch                */
+    uint32_t XOSCCKSW1:1;      /*!< bit:      5  XOSC 1 Clock Switch                */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped       */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise                    */
+    uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall                    */
+    uint32_t DPLL0TO:1;        /*!< bit:     18  DPLL0 Timeout                      */
+    uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete */
+    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise                    */
+    uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall                    */
+    uint32_t DPLL1TO:1;        /*!< bit:     26  DPLL1 Timeout                      */
+    uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready                       */
+    uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector      */
+    uint32_t XOSCCKSW:2;       /*!< bit:  4.. 5  XOSC x Clock Switch                */
+    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_STATUS_OFFSET       0x10         /**< \brief (OSCCTRL_STATUS offset) Status */
+#define OSCCTRL_STATUS_RESETVALUE   _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */
+
+#define OSCCTRL_STATUS_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */
+#define OSCCTRL_STATUS_XOSCRDY0     (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
+#define OSCCTRL_STATUS_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */
+#define OSCCTRL_STATUS_XOSCRDY1     (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
+#define OSCCTRL_STATUS_XOSCRDY_Pos  0            /**< \brief (OSCCTRL_STATUS) XOSC x Ready */
+#define OSCCTRL_STATUS_XOSCRDY_Msk  (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
+#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
+#define OSCCTRL_STATUS_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL0    (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL1    (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
+#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
+#define OSCCTRL_STATUS_XOSCCKSW0_Pos 4            /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW0    (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW1_Pos 5            /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW1    (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW_Pos 4            /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
+#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
+#define OSCCTRL_STATUS_DFLLRDY_Pos  8            /**< \brief (OSCCTRL_STATUS) DFLL Ready */
+#define OSCCTRL_STATUS_DFLLRDY      (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
+#define OSCCTRL_STATUS_DFLLOOB_Pos  9            /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
+#define OSCCTRL_STATUS_DFLLOOB      (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
+#define OSCCTRL_STATUS_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
+#define OSCCTRL_STATUS_DFLLLCKF     (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
+#define OSCCTRL_STATUS_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
+#define OSCCTRL_STATUS_DFLLLCKC     (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
+#define OSCCTRL_STATUS_DFLLRCS_Pos  12           /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
+#define OSCCTRL_STATUS_DFLLRCS      (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
+#define OSCCTRL_STATUS_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */
+#define OSCCTRL_STATUS_DPLL0LCKR    (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
+#define OSCCTRL_STATUS_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */
+#define OSCCTRL_STATUS_DPLL0LCKF    (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
+#define OSCCTRL_STATUS_DPLL0TO_Pos  18           /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */
+#define OSCCTRL_STATUS_DPLL0TO      (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
+#define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */
+#define OSCCTRL_STATUS_DPLL0LDRTO   (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
+#define OSCCTRL_STATUS_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */
+#define OSCCTRL_STATUS_DPLL1LCKR    (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
+#define OSCCTRL_STATUS_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */
+#define OSCCTRL_STATUS_DPLL1LCKF    (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
+#define OSCCTRL_STATUS_DPLL1TO_Pos  26           /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */
+#define OSCCTRL_STATUS_DPLL1TO      (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
+#define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */
+#define OSCCTRL_STATUS_DPLL1LDRTO   (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
+#define OSCCTRL_STATUS_MASK         _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */
+
+/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t LOWBUFGAIN:1;     /*!< bit:      8  Low Buffer Gain Enable             */
+    uint32_t IPTAT:2;          /*!< bit:  9..10  Oscillator Current Reference       */
+    uint32_t IMULT:4;          /*!< bit: 11..14  Oscillator Current Multiplier      */
+    uint32_t ENALC:1;          /*!< bit:     15  Automatic Loop Control Enable      */
+    uint32_t CFDEN:1;          /*!< bit:     16  Clock Failure Detector Enable      */
+    uint32_t SWBEN:1;          /*!< bit:     17  Xosc Clock Switch Enable           */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t STARTUP:4;        /*!< bit: 20..23  Start-Up Time                      */
+    uint32_t CFDPRESC:4;       /*!< bit: 24..27  Clock Failure Detector Prescaler   */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_XOSCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_XOSCCTRL_OFFSET     0x14         /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */
+#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */
+
+#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1            /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_ENABLE     (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
+#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2            /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_XTALEN     (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
+#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
+#define OSCCTRL_XOSCCTRL_RUNSTDBY   (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
+#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
+#define OSCCTRL_XOSCCTRL_ONDEMAND   (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8            /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
+#define OSCCTRL_XOSCCTRL_IPTAT_Pos  9            /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */
+#define OSCCTRL_XOSCCTRL_IPTAT_Msk  (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
+#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
+#define OSCCTRL_XOSCCTRL_IMULT_Pos  11           /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */
+#define OSCCTRL_XOSCCTRL_IMULT_Msk  (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
+#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
+#define OSCCTRL_XOSCCTRL_ENALC_Pos  15           /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */
+#define OSCCTRL_XOSCCTRL_ENALC      (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
+#define OSCCTRL_XOSCCTRL_CFDEN_Pos  16           /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */
+#define OSCCTRL_XOSCCTRL_CFDEN      (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
+#define OSCCTRL_XOSCCTRL_SWBEN_Pos  17           /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
+#define OSCCTRL_XOSCCTRL_SWBEN      (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP_Pos 20           /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
+#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24           /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
+#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
+#define OSCCTRL_XOSCCTRL_MASK       _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W  8) DFLL48M Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DFLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRLA_OFFSET    0x1C         /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */
+#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82)    /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */
+
+#define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1            /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */
+#define OSCCTRL_DFLLCTRLA_ENABLE    (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY  (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND  (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DFLLCTRLA_MASK      _U_(0xC2)    /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W  8) DFLL48M Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MODE:1;           /*!< bit:      0  Operating Mode Selection           */
+    uint8_t  STABLE:1;         /*!< bit:      1  Stable DFLL Frequency              */
+    uint8_t  LLAW:1;           /*!< bit:      2  Lose Lock After Wake               */
+    uint8_t  USBCRM:1;         /*!< bit:      3  USB Clock Recovery Mode            */
+    uint8_t  CCDIS:1;          /*!< bit:      4  Chill Cycle Disable                */
+    uint8_t  QLDIS:1;          /*!< bit:      5  Quick Lock Disable                 */
+    uint8_t  BPLCKC:1;         /*!< bit:      6  Bypass Coarse Lock                 */
+    uint8_t  WAITLOCK:1;       /*!< bit:      7  Wait Lock                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DFLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRLB_OFFSET    0x20         /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */
+#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */
+
+#define OSCCTRL_DFLLCTRLB_MODE_Pos  0            /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */
+#define OSCCTRL_DFLLCTRLB_MODE      (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
+#define OSCCTRL_DFLLCTRLB_STABLE_Pos 1            /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */
+#define OSCCTRL_DFLLCTRLB_STABLE    (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
+#define OSCCTRL_DFLLCTRLB_LLAW_Pos  2            /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */
+#define OSCCTRL_DFLLCTRLB_LLAW      (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
+#define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3            /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */
+#define OSCCTRL_DFLLCTRLB_USBCRM    (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
+#define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4            /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */
+#define OSCCTRL_DFLLCTRLB_CCDIS     (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
+#define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5            /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */
+#define OSCCTRL_DFLLCTRLB_QLDIS     (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
+#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6            /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */
+#define OSCCTRL_DFLLCTRLB_BPLCKC    (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7            /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK  (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
+#define OSCCTRL_DFLLCTRLB_MASK      _U_(0xFF)    /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FINE:8;           /*!< bit:  0.. 7  Fine Value                         */
+    uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
+    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
+    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLVAL_OFFSET      0x24         /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
+#define OSCCTRL_DFLLVAL_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define OSCCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
+#define OSCCTRL_DFLLVAL_FINE_Msk    (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
+#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
+#define OSCCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
+#define OSCCTRL_DFLLVAL_COARSE_Msk  (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
+#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
+#define OSCCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define OSCCTRL_DFLLVAL_DIFF_Msk    (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
+#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
+#define OSCCTRL_DFLLVAL_MASK        _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
+
+/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
+    uint32_t FSTEP:8;          /*!< bit: 16..23  Fine Maximum Step                  */
+    uint32_t :2;               /*!< bit: 24..25  Reserved                           */
+    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLMUL_OFFSET      0x28         /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define OSCCTRL_DFLLMUL_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define OSCCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
+#define OSCCTRL_DFLLMUL_MUL_Msk     (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
+#define OSCCTRL_DFLLMUL_MUL(value)  (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
+#define OSCCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
+#define OSCCTRL_DFLLMUL_FSTEP_Msk   (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
+#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
+#define OSCCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
+#define OSCCTRL_DFLLMUL_CSTEP_Msk   (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
+#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
+#define OSCCTRL_DFLLMUL_MASK        _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
+
+/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W  8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  ENABLE Synchronization Busy        */
+    uint8_t  DFLLCTRLB:1;      /*!< bit:      2  DFLLCTRLB Synchronization Busy     */
+    uint8_t  DFLLVAL:1;        /*!< bit:      3  DFLLVAL Synchronization Busy       */
+    uint8_t  DFLLMUL:1;        /*!< bit:      4  DFLLMUL Synchronization Busy       */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLSYNC_OFFSET     0x2C         /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define OSCCTRL_DFLLSYNC_ENABLE_Pos 1            /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_ENABLE     (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2            /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB  (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3            /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLVAL    (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
+#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4            /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */
+#define OSCCTRL_DFLLSYNC_DFLLMUL    (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
+#define OSCCTRL_DFLLSYNC_MASK       _U_(0x1E)    /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W  8) DPLL DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable                        */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLA_OFFSET    0x30         /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */
+#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80)    /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */
+#define OSCCTRL_DPLLCTRLA_ENABLE    (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY  (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */
+#define OSCCTRL_DPLLCTRLA_ONDEMAND  (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DPLLCTRLA_MASK      _U_(0xC2)    /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LDR:13;           /*!< bit:  0..12  Loop Divider Ratio                 */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t LDRFRAC:5;        /*!< bit: 16..20  Loop Divider Ratio Fractional Part */
+    uint32_t :11;              /*!< bit: 21..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLRATIO_OFFSET    0x34         /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define OSCCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
+#define OSCCTRL_DPLLRATIO_LDR_Msk   (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
+#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define OSCCTRL_DPLLRATIO_MASK      _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FILTER:4;         /*!< bit:  0.. 3  Proportional Integral Filter Selection */
+    uint32_t WUF:1;            /*!< bit:      4  Wake Up Fast                       */
+    uint32_t REFCLK:3;         /*!< bit:  5.. 7  Reference Clock Selection          */
+    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
+    uint32_t LBYPASS:1;        /*!< bit:     11  Lock Bypass                        */
+    uint32_t DCOFILTER:3;      /*!< bit: 12..14  Sigma-Delta DCO Filter Selection   */
+    uint32_t DCOEN:1;          /*!< bit:     15  DCO Filter Enable                  */
+    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLB_OFFSET    0x38         /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */
+#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_WUF_Pos   4            /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
+#define OSCCTRL_DPLLCTRLB_WUF       (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5            /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
+#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
+#define   OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0)   /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
+#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1)   /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
+#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2)   /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
+#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3)   /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
+#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
+#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
+#define   OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0)   /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
+#define   OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
+#define   OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
+#define   OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
+#define   OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
+#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11           /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
+#define OSCCTRL_DPLLCTRLB_LBYPASS   (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12           /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15           /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */
+#define OSCCTRL_DPLLCTRLB_DCOEN     (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
+#define OSCCTRL_DPLLCTRLB_DIV_Msk   (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
+#define OSCCTRL_DPLLCTRLB_MASK      _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/  32) DPLL DPLL Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  DPLL Enable Synchronization Status */
+    uint32_t DPLLRATIO:1;      /*!< bit:      2  DPLL Loop Divider Ratio Synchronization Status */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DPLLSYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C         /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
+#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
+
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_MASK   _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
+
+/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/  32) DPLL DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
+    uint32_t CLKRDY:1;         /*!< bit:      1  DPLL Clock Ready                   */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSTATUS_OFFSET   0x40         /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
+#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
+#define OSCCTRL_DPLLSTATUS_LOCK     (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
+#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
+#define OSCCTRL_DPLLSTATUS_CLKRDY   (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define OSCCTRL_DPLLSTATUS_MASK     _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief OscctrlDpll hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO OSCCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x00 (R/W  8) DPLL Control A */
+       RoReg8                    Reserved1[0x3];
+  __IO OSCCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */
+  __IO OSCCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */
+  __I  OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/  32) DPLL Synchronization Busy */
+  __I  OSCCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x10 (R/  32) DPLL Status */
+} OscctrlDpll;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief OSCCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO OSCCTRL_EVCTRL_Type       EVCTRL;      /**< \brief Offset: 0x00 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x3];
+  __IO OSCCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */
+  __IO OSCCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */
+  __IO OSCCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
+  __I  OSCCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x10 (R/  32) Status */
+  __IO OSCCTRL_XOSCCTRL_Type     XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
+  __IO OSCCTRL_DFLLCTRLA_Type    DFLLCTRLA;   /**< \brief Offset: 0x1C (R/W  8) DFLL48M Control A */
+       RoReg8                    Reserved2[0x3];
+  __IO OSCCTRL_DFLLCTRLB_Type    DFLLCTRLB;   /**< \brief Offset: 0x20 (R/W  8) DFLL48M Control B */
+       RoReg8                    Reserved3[0x3];
+  __IO OSCCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */
+  __IO OSCCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */
+  __IO OSCCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x2C (R/W  8) DFLL48M Synchronization */
+       RoReg8                    Reserved4[0x3];
+       OscctrlDpll               Dpll[2];     /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */
+} Oscctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_OSCCTRL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pac.h
new file mode 100644
index 000000000..480ef7cb1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pac.h	
@@ -0,0 +1,676 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PAC_COMPONENT_
+#define _SAME53_PAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAME53_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2120
+#define REV_PAC                     0x120
+
+/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PERID:16;         /*!< bit:  0..15  Peripheral identifier              */
+    uint32_t KEY:8;            /*!< bit: 16..23  Peripheral access control key      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WRCTRL_OFFSET           0x00         /**< \brief (PAC_WRCTRL offset) Write control */
+#define PAC_WRCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
+
+#define PAC_WRCTRL_PERID_Pos        0            /**< \brief (PAC_WRCTRL) Peripheral identifier */
+#define PAC_WRCTRL_PERID_Msk        (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
+#define PAC_WRCTRL_PERID(value)     (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
+#define PAC_WRCTRL_KEY_Pos          16           /**< \brief (PAC_WRCTRL) Peripheral access control key */
+#define PAC_WRCTRL_KEY_Msk          (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY(value)       (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
+#define   PAC_WRCTRL_KEY_OFF_Val          _U_(0x0)   /**< \brief (PAC_WRCTRL) No action */
+#define   PAC_WRCTRL_KEY_CLR_Val          _U_(0x1)   /**< \brief (PAC_WRCTRL) Clear protection */
+#define   PAC_WRCTRL_KEY_SET_Val          _U_(0x2)   /**< \brief (PAC_WRCTRL) Set protection */
+#define   PAC_WRCTRL_KEY_SETLCK_Val       _U_(0x3)   /**< \brief (PAC_WRCTRL) Set and lock protection */
+#define PAC_WRCTRL_KEY_OFF          (PAC_WRCTRL_KEY_OFF_Val        << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_CLR          (PAC_WRCTRL_KEY_CLR_Val        << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SET          (PAC_WRCTRL_KEY_SET_Val        << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SETLCK       (PAC_WRCTRL_KEY_SETLCK_Val     << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_MASK             _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
+
+/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W  8) Event control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERREO:1;          /*!< bit:      0  Peripheral acess error event output */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_EVCTRL_OFFSET           0x04         /**< \brief (PAC_EVCTRL offset) Event control */
+#define PAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (PAC_EVCTRL reset_value) Event control */
+
+#define PAC_EVCTRL_ERREO_Pos        0            /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
+#define PAC_EVCTRL_ERREO            (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
+#define PAC_EVCTRL_MASK             _U_(0x01)    /**< \brief (PAC_EVCTRL) MASK Register */
+
+/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W  8) Interrupt enable clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt disable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENCLR_OFFSET         0x08         /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
+#define PAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
+
+#define PAC_INTENCLR_ERR_Pos        0            /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
+#define PAC_INTENCLR_ERR            (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
+#define PAC_INTENCLR_MASK           _U_(0x01)    /**< \brief (PAC_INTENCLR) MASK Register */
+
+/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W  8) Interrupt enable set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt enable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENSET_OFFSET         0x09         /**< \brief (PAC_INTENSET offset) Interrupt enable set */
+#define PAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
+
+#define PAC_INTENSET_ERR_Pos        0            /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
+#define PAC_INTENSET_ERR            (_U_(0x1) << PAC_INTENSET_ERR_Pos)
+#define PAC_INTENSET_MASK           _U_(0x01)    /**< \brief (PAC_INTENSET) MASK Register */
+
+/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t FLASH_:1;         /*!< bit:      0  FLASH                              */
+    __I uint32_t FLASH_ALT_:1;     /*!< bit:      1  FLASH_ALT                          */
+    __I uint32_t SEEPROM_:1;       /*!< bit:      2  SEEPROM                            */
+    __I uint32_t RAMCM4S_:1;       /*!< bit:      3  RAMCM4S                            */
+    __I uint32_t RAMPPPDSU_:1;     /*!< bit:      4  RAMPPPDSU                          */
+    __I uint32_t RAMDMAWR_:1;      /*!< bit:      5  RAMDMAWR                           */
+    __I uint32_t RAMDMACICM_:1;    /*!< bit:      6  RAMDMACICM                         */
+    __I uint32_t HPB0_:1;          /*!< bit:      7  HPB0                               */
+    __I uint32_t HPB1_:1;          /*!< bit:      8  HPB1                               */
+    __I uint32_t HPB2_:1;          /*!< bit:      9  HPB2                               */
+    __I uint32_t HPB3_:1;          /*!< bit:     10  HPB3                               */
+    __I uint32_t PUKCC_:1;         /*!< bit:     11  PUKCC                              */
+    __I uint32_t SDHC0_:1;         /*!< bit:     12  SDHC0                              */
+    __I uint32_t SDHC1_:1;         /*!< bit:     13  SDHC1                              */
+    __I uint32_t QSPI_:1;          /*!< bit:     14  QSPI                               */
+    __I uint32_t BKUPRAM_:1;       /*!< bit:     15  BKUPRAM                            */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGAHB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGAHB_OFFSET       0x10         /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
+#define PAC_INTFLAGAHB_RESETVALUE   _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
+
+#define PAC_INTFLAGAHB_FLASH_Pos    0            /**< \brief (PAC_INTFLAGAHB) FLASH */
+#define PAC_INTFLAGAHB_FLASH        (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
+#define PAC_INTFLAGAHB_FLASH_ALT_Pos 1            /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */
+#define PAC_INTFLAGAHB_FLASH_ALT    (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
+#define PAC_INTFLAGAHB_SEEPROM_Pos  2            /**< \brief (PAC_INTFLAGAHB) SEEPROM */
+#define PAC_INTFLAGAHB_SEEPROM      (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
+#define PAC_INTFLAGAHB_RAMCM4S_Pos  3            /**< \brief (PAC_INTFLAGAHB) RAMCM4S */
+#define PAC_INTFLAGAHB_RAMCM4S      (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
+#define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4            /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */
+#define PAC_INTFLAGAHB_RAMPPPDSU    (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
+#define PAC_INTFLAGAHB_RAMDMAWR_Pos 5            /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */
+#define PAC_INTFLAGAHB_RAMDMAWR     (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
+#define PAC_INTFLAGAHB_RAMDMACICM_Pos 6            /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */
+#define PAC_INTFLAGAHB_RAMDMACICM   (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
+#define PAC_INTFLAGAHB_HPB0_Pos     7            /**< \brief (PAC_INTFLAGAHB) HPB0 */
+#define PAC_INTFLAGAHB_HPB0         (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
+#define PAC_INTFLAGAHB_HPB1_Pos     8            /**< \brief (PAC_INTFLAGAHB) HPB1 */
+#define PAC_INTFLAGAHB_HPB1         (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
+#define PAC_INTFLAGAHB_HPB2_Pos     9            /**< \brief (PAC_INTFLAGAHB) HPB2 */
+#define PAC_INTFLAGAHB_HPB2         (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
+#define PAC_INTFLAGAHB_HPB3_Pos     10           /**< \brief (PAC_INTFLAGAHB) HPB3 */
+#define PAC_INTFLAGAHB_HPB3         (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
+#define PAC_INTFLAGAHB_PUKCC_Pos    11           /**< \brief (PAC_INTFLAGAHB) PUKCC */
+#define PAC_INTFLAGAHB_PUKCC        (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
+#define PAC_INTFLAGAHB_SDHC0_Pos    12           /**< \brief (PAC_INTFLAGAHB) SDHC0 */
+#define PAC_INTFLAGAHB_SDHC0        (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
+#define PAC_INTFLAGAHB_SDHC1_Pos    13           /**< \brief (PAC_INTFLAGAHB) SDHC1 */
+#define PAC_INTFLAGAHB_SDHC1        (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
+#define PAC_INTFLAGAHB_QSPI_Pos     14           /**< \brief (PAC_INTFLAGAHB) QSPI */
+#define PAC_INTFLAGAHB_QSPI         (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
+#define PAC_INTFLAGAHB_BKUPRAM_Pos  15           /**< \brief (PAC_INTFLAGAHB) BKUPRAM */
+#define PAC_INTFLAGAHB_BKUPRAM      (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
+#define PAC_INTFLAGAHB_MASK         _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
+
+/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t PAC_:1;           /*!< bit:      0  PAC                                */
+    __I uint32_t PM_:1;            /*!< bit:      1  PM                                 */
+    __I uint32_t MCLK_:1;          /*!< bit:      2  MCLK                               */
+    __I uint32_t RSTC_:1;          /*!< bit:      3  RSTC                               */
+    __I uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL                            */
+    __I uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL                         */
+    __I uint32_t SUPC_:1;          /*!< bit:      6  SUPC                               */
+    __I uint32_t GCLK_:1;          /*!< bit:      7  GCLK                               */
+    __I uint32_t WDT_:1;           /*!< bit:      8  WDT                                */
+    __I uint32_t RTC_:1;           /*!< bit:      9  RTC                                */
+    __I uint32_t EIC_:1;           /*!< bit:     10  EIC                                */
+    __I uint32_t FREQM_:1;         /*!< bit:     11  FREQM                              */
+    __I uint32_t SERCOM0_:1;       /*!< bit:     12  SERCOM0                            */
+    __I uint32_t SERCOM1_:1;       /*!< bit:     13  SERCOM1                            */
+    __I uint32_t TC0_:1;           /*!< bit:     14  TC0                                */
+    __I uint32_t TC1_:1;           /*!< bit:     15  TC1                                */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGA_OFFSET         0x14         /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
+#define PAC_INTFLAGA_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
+
+#define PAC_INTFLAGA_PAC_Pos        0            /**< \brief (PAC_INTFLAGA) PAC */
+#define PAC_INTFLAGA_PAC            (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
+#define PAC_INTFLAGA_PM_Pos         1            /**< \brief (PAC_INTFLAGA) PM */
+#define PAC_INTFLAGA_PM             (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
+#define PAC_INTFLAGA_MCLK_Pos       2            /**< \brief (PAC_INTFLAGA) MCLK */
+#define PAC_INTFLAGA_MCLK           (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
+#define PAC_INTFLAGA_RSTC_Pos       3            /**< \brief (PAC_INTFLAGA) RSTC */
+#define PAC_INTFLAGA_RSTC           (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
+#define PAC_INTFLAGA_OSCCTRL_Pos    4            /**< \brief (PAC_INTFLAGA) OSCCTRL */
+#define PAC_INTFLAGA_OSCCTRL        (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
+#define PAC_INTFLAGA_OSC32KCTRL_Pos 5            /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
+#define PAC_INTFLAGA_OSC32KCTRL     (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
+#define PAC_INTFLAGA_SUPC_Pos       6            /**< \brief (PAC_INTFLAGA) SUPC */
+#define PAC_INTFLAGA_SUPC           (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
+#define PAC_INTFLAGA_GCLK_Pos       7            /**< \brief (PAC_INTFLAGA) GCLK */
+#define PAC_INTFLAGA_GCLK           (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
+#define PAC_INTFLAGA_WDT_Pos        8            /**< \brief (PAC_INTFLAGA) WDT */
+#define PAC_INTFLAGA_WDT            (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
+#define PAC_INTFLAGA_RTC_Pos        9            /**< \brief (PAC_INTFLAGA) RTC */
+#define PAC_INTFLAGA_RTC            (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
+#define PAC_INTFLAGA_EIC_Pos        10           /**< \brief (PAC_INTFLAGA) EIC */
+#define PAC_INTFLAGA_EIC            (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
+#define PAC_INTFLAGA_FREQM_Pos      11           /**< \brief (PAC_INTFLAGA) FREQM */
+#define PAC_INTFLAGA_FREQM          (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
+#define PAC_INTFLAGA_SERCOM0_Pos    12           /**< \brief (PAC_INTFLAGA) SERCOM0 */
+#define PAC_INTFLAGA_SERCOM0        (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
+#define PAC_INTFLAGA_SERCOM1_Pos    13           /**< \brief (PAC_INTFLAGA) SERCOM1 */
+#define PAC_INTFLAGA_SERCOM1        (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
+#define PAC_INTFLAGA_TC0_Pos        14           /**< \brief (PAC_INTFLAGA) TC0 */
+#define PAC_INTFLAGA_TC0            (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
+#define PAC_INTFLAGA_TC1_Pos        15           /**< \brief (PAC_INTFLAGA) TC1 */
+#define PAC_INTFLAGA_TC1            (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
+#define PAC_INTFLAGA_MASK           _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */
+
+/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t USB_:1;           /*!< bit:      0  USB                                */
+    __I uint32_t DSU_:1;           /*!< bit:      1  DSU                                */
+    __I uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL                            */
+    __I uint32_t CMCC_:1;          /*!< bit:      3  CMCC                               */
+    __I uint32_t PORT_:1;          /*!< bit:      4  PORT                               */
+    __I uint32_t DMAC_:1;          /*!< bit:      5  DMAC                               */
+    __I uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX                            */
+    __I uint32_t EVSYS_:1;         /*!< bit:      7  EVSYS                              */
+    __I uint32_t :1;               /*!< bit:      8  Reserved                           */
+    __I uint32_t SERCOM2_:1;       /*!< bit:      9  SERCOM2                            */
+    __I uint32_t SERCOM3_:1;       /*!< bit:     10  SERCOM3                            */
+    __I uint32_t TCC0_:1;          /*!< bit:     11  TCC0                               */
+    __I uint32_t TCC1_:1;          /*!< bit:     12  TCC1                               */
+    __I uint32_t TC2_:1;           /*!< bit:     13  TC2                                */
+    __I uint32_t TC3_:1;           /*!< bit:     14  TC3                                */
+    __I uint32_t :1;               /*!< bit:     15  Reserved                           */
+    __I uint32_t RAMECC_:1;        /*!< bit:     16  RAMECC                             */
+    __I uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGB_OFFSET         0x18         /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
+#define PAC_INTFLAGB_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
+
+#define PAC_INTFLAGB_USB_Pos        0            /**< \brief (PAC_INTFLAGB) USB */
+#define PAC_INTFLAGB_USB            (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
+#define PAC_INTFLAGB_DSU_Pos        1            /**< \brief (PAC_INTFLAGB) DSU */
+#define PAC_INTFLAGB_DSU            (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
+#define PAC_INTFLAGB_NVMCTRL_Pos    2            /**< \brief (PAC_INTFLAGB) NVMCTRL */
+#define PAC_INTFLAGB_NVMCTRL        (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
+#define PAC_INTFLAGB_CMCC_Pos       3            /**< \brief (PAC_INTFLAGB) CMCC */
+#define PAC_INTFLAGB_CMCC           (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
+#define PAC_INTFLAGB_PORT_Pos       4            /**< \brief (PAC_INTFLAGB) PORT */
+#define PAC_INTFLAGB_PORT           (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
+#define PAC_INTFLAGB_DMAC_Pos       5            /**< \brief (PAC_INTFLAGB) DMAC */
+#define PAC_INTFLAGB_DMAC           (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
+#define PAC_INTFLAGB_HMATRIX_Pos    6            /**< \brief (PAC_INTFLAGB) HMATRIX */
+#define PAC_INTFLAGB_HMATRIX        (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
+#define PAC_INTFLAGB_EVSYS_Pos      7            /**< \brief (PAC_INTFLAGB) EVSYS */
+#define PAC_INTFLAGB_EVSYS          (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
+#define PAC_INTFLAGB_SERCOM2_Pos    9            /**< \brief (PAC_INTFLAGB) SERCOM2 */
+#define PAC_INTFLAGB_SERCOM2        (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
+#define PAC_INTFLAGB_SERCOM3_Pos    10           /**< \brief (PAC_INTFLAGB) SERCOM3 */
+#define PAC_INTFLAGB_SERCOM3        (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
+#define PAC_INTFLAGB_TCC0_Pos       11           /**< \brief (PAC_INTFLAGB) TCC0 */
+#define PAC_INTFLAGB_TCC0           (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
+#define PAC_INTFLAGB_TCC1_Pos       12           /**< \brief (PAC_INTFLAGB) TCC1 */
+#define PAC_INTFLAGB_TCC1           (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
+#define PAC_INTFLAGB_TC2_Pos        13           /**< \brief (PAC_INTFLAGB) TC2 */
+#define PAC_INTFLAGB_TC2            (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
+#define PAC_INTFLAGB_TC3_Pos        14           /**< \brief (PAC_INTFLAGB) TC3 */
+#define PAC_INTFLAGB_TC3            (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
+#define PAC_INTFLAGB_RAMECC_Pos     16           /**< \brief (PAC_INTFLAGB) RAMECC */
+#define PAC_INTFLAGB_RAMECC         (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
+#define PAC_INTFLAGB_MASK           _U_(0x00017EFF) /**< \brief (PAC_INTFLAGB) MASK Register */
+
+/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    __I uint32_t GMAC_:1;          /*!< bit:      2  GMAC                               */
+    __I uint32_t TCC2_:1;          /*!< bit:      3  TCC2                               */
+    __I uint32_t TCC3_:1;          /*!< bit:      4  TCC3                               */
+    __I uint32_t TC4_:1;           /*!< bit:      5  TC4                                */
+    __I uint32_t TC5_:1;           /*!< bit:      6  TC5                                */
+    __I uint32_t PDEC_:1;          /*!< bit:      7  PDEC                               */
+    __I uint32_t AC_:1;            /*!< bit:      8  AC                                 */
+    __I uint32_t AES_:1;           /*!< bit:      9  AES                                */
+    __I uint32_t TRNG_:1;          /*!< bit:     10  TRNG                               */
+    __I uint32_t ICM_:1;           /*!< bit:     11  ICM                                */
+    __I uint32_t PUKCC_:1;         /*!< bit:     12  PUKCC                              */
+    __I uint32_t QSPI_:1;          /*!< bit:     13  QSPI                               */
+    __I uint32_t CCL_:1;           /*!< bit:     14  CCL                                */
+    __I uint32_t :17;              /*!< bit: 15..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGC_OFFSET         0x1C         /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
+#define PAC_INTFLAGC_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
+
+#define PAC_INTFLAGC_GMAC_Pos       2            /**< \brief (PAC_INTFLAGC) GMAC */
+#define PAC_INTFLAGC_GMAC           (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
+#define PAC_INTFLAGC_TCC2_Pos       3            /**< \brief (PAC_INTFLAGC) TCC2 */
+#define PAC_INTFLAGC_TCC2           (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
+#define PAC_INTFLAGC_TCC3_Pos       4            /**< \brief (PAC_INTFLAGC) TCC3 */
+#define PAC_INTFLAGC_TCC3           (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
+#define PAC_INTFLAGC_TC4_Pos        5            /**< \brief (PAC_INTFLAGC) TC4 */
+#define PAC_INTFLAGC_TC4            (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
+#define PAC_INTFLAGC_TC5_Pos        6            /**< \brief (PAC_INTFLAGC) TC5 */
+#define PAC_INTFLAGC_TC5            (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
+#define PAC_INTFLAGC_PDEC_Pos       7            /**< \brief (PAC_INTFLAGC) PDEC */
+#define PAC_INTFLAGC_PDEC           (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
+#define PAC_INTFLAGC_AC_Pos         8            /**< \brief (PAC_INTFLAGC) AC */
+#define PAC_INTFLAGC_AC             (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
+#define PAC_INTFLAGC_AES_Pos        9            /**< \brief (PAC_INTFLAGC) AES */
+#define PAC_INTFLAGC_AES            (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
+#define PAC_INTFLAGC_TRNG_Pos       10           /**< \brief (PAC_INTFLAGC) TRNG */
+#define PAC_INTFLAGC_TRNG           (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
+#define PAC_INTFLAGC_ICM_Pos        11           /**< \brief (PAC_INTFLAGC) ICM */
+#define PAC_INTFLAGC_ICM            (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
+#define PAC_INTFLAGC_PUKCC_Pos      12           /**< \brief (PAC_INTFLAGC) PUKCC */
+#define PAC_INTFLAGC_PUKCC          (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
+#define PAC_INTFLAGC_QSPI_Pos       13           /**< \brief (PAC_INTFLAGC) QSPI */
+#define PAC_INTFLAGC_QSPI           (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
+#define PAC_INTFLAGC_CCL_Pos        14           /**< \brief (PAC_INTFLAGC) CCL */
+#define PAC_INTFLAGC_CCL            (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
+#define PAC_INTFLAGC_MASK           _U_(0x00007FFC) /**< \brief (PAC_INTFLAGC) MASK Register */
+
+/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t SERCOM4_:1;       /*!< bit:      0  SERCOM4                            */
+    __I uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5                            */
+    __I uint32_t SERCOM6_:1;       /*!< bit:      2  SERCOM6                            */
+    __I uint32_t SERCOM7_:1;       /*!< bit:      3  SERCOM7                            */
+    __I uint32_t TCC4_:1;          /*!< bit:      4  TCC4                               */
+    __I uint32_t TC6_:1;           /*!< bit:      5  TC6                                */
+    __I uint32_t TC7_:1;           /*!< bit:      6  TC7                                */
+    __I uint32_t ADC0_:1;          /*!< bit:      7  ADC0                               */
+    __I uint32_t ADC1_:1;          /*!< bit:      8  ADC1                               */
+    __I uint32_t DAC_:1;           /*!< bit:      9  DAC                                */
+    __I uint32_t I2S_:1;           /*!< bit:     10  I2S                                */
+    __I uint32_t PCC_:1;           /*!< bit:     11  PCC                                */
+    __I uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGD_OFFSET         0x20         /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
+#define PAC_INTFLAGD_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
+
+#define PAC_INTFLAGD_SERCOM4_Pos    0            /**< \brief (PAC_INTFLAGD) SERCOM4 */
+#define PAC_INTFLAGD_SERCOM4        (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
+#define PAC_INTFLAGD_SERCOM5_Pos    1            /**< \brief (PAC_INTFLAGD) SERCOM5 */
+#define PAC_INTFLAGD_SERCOM5        (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
+#define PAC_INTFLAGD_SERCOM6_Pos    2            /**< \brief (PAC_INTFLAGD) SERCOM6 */
+#define PAC_INTFLAGD_SERCOM6        (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
+#define PAC_INTFLAGD_SERCOM7_Pos    3            /**< \brief (PAC_INTFLAGD) SERCOM7 */
+#define PAC_INTFLAGD_SERCOM7        (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
+#define PAC_INTFLAGD_TCC4_Pos       4            /**< \brief (PAC_INTFLAGD) TCC4 */
+#define PAC_INTFLAGD_TCC4           (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
+#define PAC_INTFLAGD_TC6_Pos        5            /**< \brief (PAC_INTFLAGD) TC6 */
+#define PAC_INTFLAGD_TC6            (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
+#define PAC_INTFLAGD_TC7_Pos        6            /**< \brief (PAC_INTFLAGD) TC7 */
+#define PAC_INTFLAGD_TC7            (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
+#define PAC_INTFLAGD_ADC0_Pos       7            /**< \brief (PAC_INTFLAGD) ADC0 */
+#define PAC_INTFLAGD_ADC0           (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
+#define PAC_INTFLAGD_ADC1_Pos       8            /**< \brief (PAC_INTFLAGD) ADC1 */
+#define PAC_INTFLAGD_ADC1           (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
+#define PAC_INTFLAGD_DAC_Pos        9            /**< \brief (PAC_INTFLAGD) DAC */
+#define PAC_INTFLAGD_DAC            (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
+#define PAC_INTFLAGD_I2S_Pos        10           /**< \brief (PAC_INTFLAGD) I2S */
+#define PAC_INTFLAGD_I2S            (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
+#define PAC_INTFLAGD_PCC_Pos        11           /**< \brief (PAC_INTFLAGD) PCC */
+#define PAC_INTFLAGD_PCC            (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
+#define PAC_INTFLAGD_MASK           _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */
+
+/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/  32) Peripheral write protection status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Protect Enable             */
+    uint32_t PM_:1;            /*!< bit:      1  PM APB Protect Enable              */
+    uint32_t MCLK_:1;          /*!< bit:      2  MCLK APB Protect Enable            */
+    uint32_t RSTC_:1;          /*!< bit:      3  RSTC APB Protect Enable            */
+    uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL APB Protect Enable         */
+    uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL APB Protect Enable      */
+    uint32_t SUPC_:1;          /*!< bit:      6  SUPC APB Protect Enable            */
+    uint32_t GCLK_:1;          /*!< bit:      7  GCLK APB Protect Enable            */
+    uint32_t WDT_:1;           /*!< bit:      8  WDT APB Protect Enable             */
+    uint32_t RTC_:1;           /*!< bit:      9  RTC APB Protect Enable             */
+    uint32_t EIC_:1;           /*!< bit:     10  EIC APB Protect Enable             */
+    uint32_t FREQM_:1;         /*!< bit:     11  FREQM APB Protect Enable           */
+    uint32_t SERCOM0_:1;       /*!< bit:     12  SERCOM0 APB Protect Enable         */
+    uint32_t SERCOM1_:1;       /*!< bit:     13  SERCOM1 APB Protect Enable         */
+    uint32_t TC0_:1;           /*!< bit:     14  TC0 APB Protect Enable             */
+    uint32_t TC1_:1;           /*!< bit:     15  TC1 APB Protect Enable             */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSA_OFFSET          0x34         /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
+#define PAC_STATUSA_RESETVALUE      _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
+
+#define PAC_STATUSA_PAC_Pos         0            /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
+#define PAC_STATUSA_PAC             (_U_(0x1) << PAC_STATUSA_PAC_Pos)
+#define PAC_STATUSA_PM_Pos          1            /**< \brief (PAC_STATUSA) PM APB Protect Enable */
+#define PAC_STATUSA_PM              (_U_(0x1) << PAC_STATUSA_PM_Pos)
+#define PAC_STATUSA_MCLK_Pos        2            /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
+#define PAC_STATUSA_MCLK            (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
+#define PAC_STATUSA_RSTC_Pos        3            /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
+#define PAC_STATUSA_RSTC            (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
+#define PAC_STATUSA_OSCCTRL_Pos     4            /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
+#define PAC_STATUSA_OSCCTRL         (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
+#define PAC_STATUSA_OSC32KCTRL_Pos  5            /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
+#define PAC_STATUSA_OSC32KCTRL      (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
+#define PAC_STATUSA_SUPC_Pos        6            /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
+#define PAC_STATUSA_SUPC            (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
+#define PAC_STATUSA_GCLK_Pos        7            /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
+#define PAC_STATUSA_GCLK            (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
+#define PAC_STATUSA_WDT_Pos         8            /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
+#define PAC_STATUSA_WDT             (_U_(0x1) << PAC_STATUSA_WDT_Pos)
+#define PAC_STATUSA_RTC_Pos         9            /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
+#define PAC_STATUSA_RTC             (_U_(0x1) << PAC_STATUSA_RTC_Pos)
+#define PAC_STATUSA_EIC_Pos         10           /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
+#define PAC_STATUSA_EIC             (_U_(0x1) << PAC_STATUSA_EIC_Pos)
+#define PAC_STATUSA_FREQM_Pos       11           /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
+#define PAC_STATUSA_FREQM           (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
+#define PAC_STATUSA_SERCOM0_Pos     12           /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */
+#define PAC_STATUSA_SERCOM0         (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
+#define PAC_STATUSA_SERCOM1_Pos     13           /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */
+#define PAC_STATUSA_SERCOM1         (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
+#define PAC_STATUSA_TC0_Pos         14           /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */
+#define PAC_STATUSA_TC0             (_U_(0x1) << PAC_STATUSA_TC0_Pos)
+#define PAC_STATUSA_TC1_Pos         15           /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */
+#define PAC_STATUSA_TC1             (_U_(0x1) << PAC_STATUSA_TC1_Pos)
+#define PAC_STATUSA_MASK            _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */
+
+/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/  32) Peripheral write protection status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USB_:1;           /*!< bit:      0  USB APB Protect Enable             */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Protect Enable             */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Protect Enable         */
+    uint32_t CMCC_:1;          /*!< bit:      3  CMCC APB Protect Enable            */
+    uint32_t PORT_:1;          /*!< bit:      4  PORT APB Protect Enable            */
+    uint32_t DMAC_:1;          /*!< bit:      5  DMAC APB Protect Enable            */
+    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Protect Enable         */
+    uint32_t EVSYS_:1;         /*!< bit:      7  EVSYS APB Protect Enable           */
+    uint32_t :1;               /*!< bit:      8  Reserved                           */
+    uint32_t SERCOM2_:1;       /*!< bit:      9  SERCOM2 APB Protect Enable         */
+    uint32_t SERCOM3_:1;       /*!< bit:     10  SERCOM3 APB Protect Enable         */
+    uint32_t TCC0_:1;          /*!< bit:     11  TCC0 APB Protect Enable            */
+    uint32_t TCC1_:1;          /*!< bit:     12  TCC1 APB Protect Enable            */
+    uint32_t TC2_:1;           /*!< bit:     13  TC2 APB Protect Enable             */
+    uint32_t TC3_:1;           /*!< bit:     14  TC3 APB Protect Enable             */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t RAMECC_:1;        /*!< bit:     16  RAMECC APB Protect Enable          */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSB_OFFSET          0x38         /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
+#define PAC_STATUSB_RESETVALUE      _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
+
+#define PAC_STATUSB_USB_Pos         0            /**< \brief (PAC_STATUSB) USB APB Protect Enable */
+#define PAC_STATUSB_USB             (_U_(0x1) << PAC_STATUSB_USB_Pos)
+#define PAC_STATUSB_DSU_Pos         1            /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
+#define PAC_STATUSB_DSU             (_U_(0x1) << PAC_STATUSB_DSU_Pos)
+#define PAC_STATUSB_NVMCTRL_Pos     2            /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
+#define PAC_STATUSB_NVMCTRL         (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
+#define PAC_STATUSB_CMCC_Pos        3            /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */
+#define PAC_STATUSB_CMCC            (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
+#define PAC_STATUSB_PORT_Pos        4            /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
+#define PAC_STATUSB_PORT            (_U_(0x1) << PAC_STATUSB_PORT_Pos)
+#define PAC_STATUSB_DMAC_Pos        5            /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
+#define PAC_STATUSB_DMAC            (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
+#define PAC_STATUSB_HMATRIX_Pos     6            /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */
+#define PAC_STATUSB_HMATRIX         (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
+#define PAC_STATUSB_EVSYS_Pos       7            /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */
+#define PAC_STATUSB_EVSYS           (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
+#define PAC_STATUSB_SERCOM2_Pos     9            /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */
+#define PAC_STATUSB_SERCOM2         (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
+#define PAC_STATUSB_SERCOM3_Pos     10           /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */
+#define PAC_STATUSB_SERCOM3         (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
+#define PAC_STATUSB_TCC0_Pos        11           /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */
+#define PAC_STATUSB_TCC0            (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
+#define PAC_STATUSB_TCC1_Pos        12           /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */
+#define PAC_STATUSB_TCC1            (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
+#define PAC_STATUSB_TC2_Pos         13           /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */
+#define PAC_STATUSB_TC2             (_U_(0x1) << PAC_STATUSB_TC2_Pos)
+#define PAC_STATUSB_TC3_Pos         14           /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */
+#define PAC_STATUSB_TC3             (_U_(0x1) << PAC_STATUSB_TC3_Pos)
+#define PAC_STATUSB_RAMECC_Pos      16           /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */
+#define PAC_STATUSB_RAMECC          (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
+#define PAC_STATUSB_MASK            _U_(0x00017EFF) /**< \brief (PAC_STATUSB) MASK Register */
+
+/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/  32) Peripheral write protection status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t GMAC_:1;          /*!< bit:      2  GMAC APB Protect Enable            */
+    uint32_t TCC2_:1;          /*!< bit:      3  TCC2 APB Protect Enable            */
+    uint32_t TCC3_:1;          /*!< bit:      4  TCC3 APB Protect Enable            */
+    uint32_t TC4_:1;           /*!< bit:      5  TC4 APB Protect Enable             */
+    uint32_t TC5_:1;           /*!< bit:      6  TC5 APB Protect Enable             */
+    uint32_t PDEC_:1;          /*!< bit:      7  PDEC APB Protect Enable            */
+    uint32_t AC_:1;            /*!< bit:      8  AC APB Protect Enable              */
+    uint32_t AES_:1;           /*!< bit:      9  AES APB Protect Enable             */
+    uint32_t TRNG_:1;          /*!< bit:     10  TRNG APB Protect Enable            */
+    uint32_t ICM_:1;           /*!< bit:     11  ICM APB Protect Enable             */
+    uint32_t PUKCC_:1;         /*!< bit:     12  PUKCC APB Protect Enable           */
+    uint32_t QSPI_:1;          /*!< bit:     13  QSPI APB Protect Enable            */
+    uint32_t CCL_:1;           /*!< bit:     14  CCL APB Protect Enable             */
+    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSC_OFFSET          0x3C         /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
+#define PAC_STATUSC_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
+
+#define PAC_STATUSC_GMAC_Pos        2            /**< \brief (PAC_STATUSC) GMAC APB Protect Enable */
+#define PAC_STATUSC_GMAC            (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
+#define PAC_STATUSC_TCC2_Pos        3            /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
+#define PAC_STATUSC_TCC2            (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
+#define PAC_STATUSC_TCC3_Pos        4            /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
+#define PAC_STATUSC_TCC3            (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
+#define PAC_STATUSC_TC4_Pos         5            /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
+#define PAC_STATUSC_TC4             (_U_(0x1) << PAC_STATUSC_TC4_Pos)
+#define PAC_STATUSC_TC5_Pos         6            /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */
+#define PAC_STATUSC_TC5             (_U_(0x1) << PAC_STATUSC_TC5_Pos)
+#define PAC_STATUSC_PDEC_Pos        7            /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */
+#define PAC_STATUSC_PDEC            (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
+#define PAC_STATUSC_AC_Pos          8            /**< \brief (PAC_STATUSC) AC APB Protect Enable */
+#define PAC_STATUSC_AC              (_U_(0x1) << PAC_STATUSC_AC_Pos)
+#define PAC_STATUSC_AES_Pos         9            /**< \brief (PAC_STATUSC) AES APB Protect Enable */
+#define PAC_STATUSC_AES             (_U_(0x1) << PAC_STATUSC_AES_Pos)
+#define PAC_STATUSC_TRNG_Pos        10           /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
+#define PAC_STATUSC_TRNG            (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
+#define PAC_STATUSC_ICM_Pos         11           /**< \brief (PAC_STATUSC) ICM APB Protect Enable */
+#define PAC_STATUSC_ICM             (_U_(0x1) << PAC_STATUSC_ICM_Pos)
+#define PAC_STATUSC_PUKCC_Pos       12           /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */
+#define PAC_STATUSC_PUKCC           (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
+#define PAC_STATUSC_QSPI_Pos        13           /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */
+#define PAC_STATUSC_QSPI            (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
+#define PAC_STATUSC_CCL_Pos         14           /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
+#define PAC_STATUSC_CCL             (_U_(0x1) << PAC_STATUSC_CCL_Pos)
+#define PAC_STATUSC_MASK            _U_(0x00007FFC) /**< \brief (PAC_STATUSC) MASK Register */
+
+/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/  32) Peripheral write protection status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERCOM4_:1;       /*!< bit:      0  SERCOM4 APB Protect Enable         */
+    uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5 APB Protect Enable         */
+    uint32_t SERCOM6_:1;       /*!< bit:      2  SERCOM6 APB Protect Enable         */
+    uint32_t SERCOM7_:1;       /*!< bit:      3  SERCOM7 APB Protect Enable         */
+    uint32_t TCC4_:1;          /*!< bit:      4  TCC4 APB Protect Enable            */
+    uint32_t TC6_:1;           /*!< bit:      5  TC6 APB Protect Enable             */
+    uint32_t TC7_:1;           /*!< bit:      6  TC7 APB Protect Enable             */
+    uint32_t ADC0_:1;          /*!< bit:      7  ADC0 APB Protect Enable            */
+    uint32_t ADC1_:1;          /*!< bit:      8  ADC1 APB Protect Enable            */
+    uint32_t DAC_:1;           /*!< bit:      9  DAC APB Protect Enable             */
+    uint32_t I2S_:1;           /*!< bit:     10  I2S APB Protect Enable             */
+    uint32_t PCC_:1;           /*!< bit:     11  PCC APB Protect Enable             */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSD_OFFSET          0x40         /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
+#define PAC_STATUSD_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
+
+#define PAC_STATUSD_SERCOM4_Pos     0            /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */
+#define PAC_STATUSD_SERCOM4         (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
+#define PAC_STATUSD_SERCOM5_Pos     1            /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
+#define PAC_STATUSD_SERCOM5         (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
+#define PAC_STATUSD_SERCOM6_Pos     2            /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */
+#define PAC_STATUSD_SERCOM6         (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
+#define PAC_STATUSD_SERCOM7_Pos     3            /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */
+#define PAC_STATUSD_SERCOM7         (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
+#define PAC_STATUSD_TCC4_Pos        4            /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */
+#define PAC_STATUSD_TCC4            (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
+#define PAC_STATUSD_TC6_Pos         5            /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */
+#define PAC_STATUSD_TC6             (_U_(0x1) << PAC_STATUSD_TC6_Pos)
+#define PAC_STATUSD_TC7_Pos         6            /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */
+#define PAC_STATUSD_TC7             (_U_(0x1) << PAC_STATUSD_TC7_Pos)
+#define PAC_STATUSD_ADC0_Pos        7            /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */
+#define PAC_STATUSD_ADC0            (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
+#define PAC_STATUSD_ADC1_Pos        8            /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */
+#define PAC_STATUSD_ADC1            (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
+#define PAC_STATUSD_DAC_Pos         9            /**< \brief (PAC_STATUSD) DAC APB Protect Enable */
+#define PAC_STATUSD_DAC             (_U_(0x1) << PAC_STATUSD_DAC_Pos)
+#define PAC_STATUSD_I2S_Pos         10           /**< \brief (PAC_STATUSD) I2S APB Protect Enable */
+#define PAC_STATUSD_I2S             (_U_(0x1) << PAC_STATUSD_I2S_Pos)
+#define PAC_STATUSD_PCC_Pos         11           /**< \brief (PAC_STATUSD) PCC APB Protect Enable */
+#define PAC_STATUSD_PCC             (_U_(0x1) << PAC_STATUSD_PCC_Pos)
+#define PAC_STATUSD_MASK            _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PAC_WRCTRL_Type           WRCTRL;      /**< \brief Offset: 0x00 (R/W 32) Write control */
+  __IO PAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W  8) Event control */
+       RoReg8                    Reserved1[0x3];
+  __IO PAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt enable clear */
+  __IO PAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt enable set */
+       RoReg8                    Reserved2[0x6];
+  __IO PAC_INTFLAGAHB_Type       INTFLAGAHB;  /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
+  __IO PAC_INTFLAGA_Type         INTFLAGA;    /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
+  __IO PAC_INTFLAGB_Type         INTFLAGB;    /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
+  __IO PAC_INTFLAGC_Type         INTFLAGC;    /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
+  __IO PAC_INTFLAGD_Type         INTFLAGD;    /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
+       RoReg8                    Reserved3[0x10];
+  __I  PAC_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x34 (R/  32) Peripheral write protection status - Bridge A */
+  __I  PAC_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x38 (R/  32) Peripheral write protection status - Bridge B */
+  __I  PAC_STATUSC_Type          STATUSC;     /**< \brief Offset: 0x3C (R/  32) Peripheral write protection status - Bridge C */
+  __I  PAC_STATUSD_Type          STATUSD;     /**< \brief Offset: 0x40 (R/  32) Peripheral write protection status - Bridge D */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_PAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pcc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pcc.h
new file mode 100644
index 000000000..9cdfd5729
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pcc.h	
@@ -0,0 +1,251 @@
+/**
+ * \file
+ *
+ * \brief Component description for PCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PCC_COMPONENT_
+#define _SAME53_PCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PCC */
+/* ========================================================================== */
+/** \addtogroup SAME53_PCC Parallel Capture Controller */
+/*@{*/
+
+#define PCC_U2017
+#define REV_PCC                     0x110
+
+/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PCEN:1;           /*!< bit:      0  Parallel Capture Enable            */
+    uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint32_t DSIZE:2;          /*!< bit:  4.. 5  Data size                          */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t SCALE:1;          /*!< bit:      8  Scale data                         */
+    uint32_t ALWYS:1;          /*!< bit:      9  Always Sampling                    */
+    uint32_t HALFS:1;          /*!< bit:     10  Half Sampling                      */
+    uint32_t FRSTS:1;          /*!< bit:     11  First sample                       */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t ISIZE:3;          /*!< bit: 16..18  Input Data Size                    */
+    uint32_t :11;              /*!< bit: 19..29  Reserved                           */
+    uint32_t CID:2;            /*!< bit: 30..31  Clear If Disabled                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_MR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_MR_OFFSET               0x00         /**< \brief (PCC_MR offset) Mode Register */
+#define PCC_MR_RESETVALUE           _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
+
+#define PCC_MR_PCEN_Pos             0            /**< \brief (PCC_MR) Parallel Capture Enable */
+#define PCC_MR_PCEN                 (_U_(0x1) << PCC_MR_PCEN_Pos)
+#define PCC_MR_DSIZE_Pos            4            /**< \brief (PCC_MR) Data size */
+#define PCC_MR_DSIZE_Msk            (_U_(0x3) << PCC_MR_DSIZE_Pos)
+#define PCC_MR_DSIZE(value)         (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
+#define PCC_MR_SCALE_Pos            8            /**< \brief (PCC_MR) Scale data */
+#define PCC_MR_SCALE                (_U_(0x1) << PCC_MR_SCALE_Pos)
+#define PCC_MR_ALWYS_Pos            9            /**< \brief (PCC_MR) Always Sampling */
+#define PCC_MR_ALWYS                (_U_(0x1) << PCC_MR_ALWYS_Pos)
+#define PCC_MR_HALFS_Pos            10           /**< \brief (PCC_MR) Half Sampling */
+#define PCC_MR_HALFS                (_U_(0x1) << PCC_MR_HALFS_Pos)
+#define PCC_MR_FRSTS_Pos            11           /**< \brief (PCC_MR) First sample */
+#define PCC_MR_FRSTS                (_U_(0x1) << PCC_MR_FRSTS_Pos)
+#define PCC_MR_ISIZE_Pos            16           /**< \brief (PCC_MR) Input Data Size */
+#define PCC_MR_ISIZE_Msk            (_U_(0x7) << PCC_MR_ISIZE_Pos)
+#define PCC_MR_ISIZE(value)         (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
+#define PCC_MR_CID_Pos              30           /**< \brief (PCC_MR) Clear If Disabled */
+#define PCC_MR_CID_Msk              (_U_(0x3) << PCC_MR_CID_Pos)
+#define PCC_MR_CID(value)           (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
+#define PCC_MR_MASK                 _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
+
+/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Enable        */
+    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Enable     */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_IER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IER_OFFSET              0x04         /**< \brief (PCC_IER offset) Interrupt Enable Register */
+#define PCC_IER_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
+
+#define PCC_IER_DRDY_Pos            0            /**< \brief (PCC_IER) Data Ready Interrupt Enable */
+#define PCC_IER_DRDY                (_U_(0x1) << PCC_IER_DRDY_Pos)
+#define PCC_IER_OVRE_Pos            1            /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
+#define PCC_IER_OVRE                (_U_(0x1) << PCC_IER_OVRE_Pos)
+#define PCC_IER_MASK                _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
+
+/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Disable       */
+    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Disable    */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_IDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IDR_OFFSET              0x08         /**< \brief (PCC_IDR offset) Interrupt Disable Register */
+#define PCC_IDR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
+
+#define PCC_IDR_DRDY_Pos            0            /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
+#define PCC_IDR_DRDY                (_U_(0x1) << PCC_IDR_DRDY_Pos)
+#define PCC_IDR_OVRE_Pos            1            /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
+#define PCC_IDR_OVRE                (_U_(0x1) << PCC_IDR_OVRE_Pos)
+#define PCC_IDR_MASK                _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
+
+/* -------- PCC_IMR : (PCC Offset: 0x0C) (R/  32) Interrupt Mask Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Mask          */
+    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Mask       */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_IMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_IMR_OFFSET              0x0C         /**< \brief (PCC_IMR offset) Interrupt Mask Register */
+#define PCC_IMR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
+
+#define PCC_IMR_DRDY_Pos            0            /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
+#define PCC_IMR_DRDY                (_U_(0x1) << PCC_IMR_DRDY_Pos)
+#define PCC_IMR_OVRE_Pos            1            /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
+#define PCC_IMR_OVRE                (_U_(0x1) << PCC_IMR_OVRE_Pos)
+#define PCC_IMR_MASK                _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
+
+/* -------- PCC_ISR : (PCC Offset: 0x10) (R/  32) Interrupt Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Status        */
+    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Status     */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_ISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_ISR_OFFSET              0x10         /**< \brief (PCC_ISR offset) Interrupt Status Register */
+#define PCC_ISR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
+
+#define PCC_ISR_DRDY_Pos            0            /**< \brief (PCC_ISR) Data Ready Interrupt Status */
+#define PCC_ISR_DRDY                (_U_(0x1) << PCC_ISR_DRDY_Pos)
+#define PCC_ISR_OVRE_Pos            1            /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
+#define PCC_ISR_OVRE                (_U_(0x1) << PCC_ISR_OVRE_Pos)
+#define PCC_ISR_MASK                _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
+
+/* -------- PCC_RHR : (PCC Offset: 0x14) (R/  32) Reception Holding Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RDATA:32;         /*!< bit:  0..31  Reception Data                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_RHR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_RHR_OFFSET              0x14         /**< \brief (PCC_RHR offset) Reception Holding Register */
+#define PCC_RHR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
+
+#define PCC_RHR_RDATA_Pos           0            /**< \brief (PCC_RHR) Reception Data */
+#define PCC_RHR_RDATA_Msk           (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
+#define PCC_RHR_RDATA(value)        (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
+#define PCC_RHR_MASK                _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
+
+/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WPEN:1;           /*!< bit:      0  Write Protection Enable            */
+    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
+    uint32_t WPKEY:24;         /*!< bit:  8..31  Write Protection Key               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_WPMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_WPMR_OFFSET             0xE0         /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
+#define PCC_WPMR_RESETVALUE         _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
+
+#define PCC_WPMR_WPEN_Pos           0            /**< \brief (PCC_WPMR) Write Protection Enable */
+#define PCC_WPMR_WPEN               (_U_(0x1) << PCC_WPMR_WPEN_Pos)
+#define PCC_WPMR_WPKEY_Pos          8            /**< \brief (PCC_WPMR) Write Protection Key */
+#define PCC_WPMR_WPKEY_Msk          (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
+#define PCC_WPMR_WPKEY(value)       (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
+#define PCC_WPMR_MASK               _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
+
+/* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/  32) Write Protection Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WPVS:1;           /*!< bit:      0  Write Protection Violation Source  */
+    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
+    uint32_t WPVSRC:16;        /*!< bit:  8..23  Write Protection Violation Status  */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PCC_WPSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PCC_WPSR_OFFSET             0xE4         /**< \brief (PCC_WPSR offset) Write Protection Status Register */
+#define PCC_WPSR_RESETVALUE         _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
+
+#define PCC_WPSR_WPVS_Pos           0            /**< \brief (PCC_WPSR) Write Protection Violation Source */
+#define PCC_WPSR_WPVS               (_U_(0x1) << PCC_WPSR_WPVS_Pos)
+#define PCC_WPSR_WPVSRC_Pos         8            /**< \brief (PCC_WPSR) Write Protection Violation Status */
+#define PCC_WPSR_WPVSRC_Msk         (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
+#define PCC_WPSR_WPVSRC(value)      (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
+#define PCC_WPSR_MASK               _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
+
+/** \brief PCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PCC_MR_Type               MR;          /**< \brief Offset: 0x00 (R/W 32) Mode Register */
+  __O  PCC_IER_Type              IER;         /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
+  __O  PCC_IDR_Type              IDR;         /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
+  __I  PCC_IMR_Type              IMR;         /**< \brief Offset: 0x0C (R/  32) Interrupt Mask Register */
+  __I  PCC_ISR_Type              ISR;         /**< \brief Offset: 0x10 (R/  32) Interrupt Status Register */
+  __I  PCC_RHR_Type              RHR;         /**< \brief Offset: 0x14 (R/  32) Reception Holding Register */
+       RoReg8                    Reserved1[0xC8];
+  __IO PCC_WPMR_Type             WPMR;        /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
+  __I  PCC_WPSR_Type             WPSR;        /**< \brief Offset: 0xE4 (R/  32) Write Protection Status Register */
+} Pcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_PCC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pdec.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pdec.h
new file mode 100644
index 000000000..babd9d492
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pdec.h	
@@ -0,0 +1,726 @@
+/**
+ * \file
+ *
+ * \brief Component description for PDEC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PDEC_COMPONENT_
+#define _SAME53_PDEC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PDEC */
+/* ========================================================================== */
+/** \addtogroup SAME53_PDEC Quadrature Decodeur */
+/*@{*/
+
+#define PDEC_U2263
+#define REV_PDEC                    0x100
+
+/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:2;           /*!< bit:  2.. 3  Operation Mode                     */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t CONF:3;           /*!< bit:  8..10  PDEC Configuration                 */
+    uint32_t ALOCK:1;          /*!< bit:     11  Auto Lock                          */
+    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint32_t SWAP:1;           /*!< bit:     14  PDEC Phase A and B Swap            */
+    uint32_t PEREN:1;          /*!< bit:     15  Period Enable                      */
+    uint32_t PINEN0:1;         /*!< bit:     16  PDEC Input From Pin 0 Enable       */
+    uint32_t PINEN1:1;         /*!< bit:     17  PDEC Input From Pin 1 Enable       */
+    uint32_t PINEN2:1;         /*!< bit:     18  PDEC Input From Pin 2 Enable       */
+    uint32_t :1;               /*!< bit:     19  Reserved                           */
+    uint32_t PINVEN0:1;        /*!< bit:     20  IO Pin 0 Invert Enable             */
+    uint32_t PINVEN1:1;        /*!< bit:     21  IO Pin 1 Invert Enable             */
+    uint32_t PINVEN2:1;        /*!< bit:     22  IO Pin 2 Invert Enable             */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t ANGULAR:3;        /*!< bit: 24..26  Angular Counter Length             */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t MAXCMP:4;         /*!< bit: 28..31  Maximum Consecutive Missing Pulses */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t PINEN:3;          /*!< bit: 16..18  PDEC Input From Pin x Enable       */
+    uint32_t :1;               /*!< bit:     19  Reserved                           */
+    uint32_t PINVEN:3;         /*!< bit: 20..22  IO Pin x Invert Enable             */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PDEC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLA_OFFSET           0x00         /**< \brief (PDEC_CTRLA offset) Control A */
+#define PDEC_CTRLA_RESETVALUE       _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
+
+#define PDEC_CTRLA_SWRST_Pos        0            /**< \brief (PDEC_CTRLA) Software Reset */
+#define PDEC_CTRLA_SWRST            (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
+#define PDEC_CTRLA_ENABLE_Pos       1            /**< \brief (PDEC_CTRLA) Enable */
+#define PDEC_CTRLA_ENABLE           (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
+#define PDEC_CTRLA_MODE_Pos         2            /**< \brief (PDEC_CTRLA) Operation Mode */
+#define PDEC_CTRLA_MODE_Msk         (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE(value)      (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
+#define   PDEC_CTRLA_MODE_QDEC_Val        _U_(0x0)   /**< \brief (PDEC_CTRLA) QDEC operating mode */
+#define   PDEC_CTRLA_MODE_HALL_Val        _U_(0x1)   /**< \brief (PDEC_CTRLA) HALL operating mode */
+#define   PDEC_CTRLA_MODE_COUNTER_Val     _U_(0x2)   /**< \brief (PDEC_CTRLA) COUNTER operating mode */
+#define PDEC_CTRLA_MODE_QDEC        (PDEC_CTRLA_MODE_QDEC_Val      << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE_HALL        (PDEC_CTRLA_MODE_HALL_Val      << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_MODE_COUNTER     (PDEC_CTRLA_MODE_COUNTER_Val   << PDEC_CTRLA_MODE_Pos)
+#define PDEC_CTRLA_RUNSTDBY_Pos     6            /**< \brief (PDEC_CTRLA) Run in Standby */
+#define PDEC_CTRLA_RUNSTDBY         (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
+#define PDEC_CTRLA_CONF_Pos         8            /**< \brief (PDEC_CTRLA) PDEC Configuration */
+#define PDEC_CTRLA_CONF_Msk         (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF(value)      (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
+#define   PDEC_CTRLA_CONF_X4_Val          _U_(0x0)   /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
+#define   PDEC_CTRLA_CONF_X4S_Val         _U_(0x1)   /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
+#define   PDEC_CTRLA_CONF_X2_Val          _U_(0x2)   /**< \brief (PDEC_CTRLA) Decoder direction */
+#define   PDEC_CTRLA_CONF_X2S_Val         _U_(0x3)   /**< \brief (PDEC_CTRLA) Secure decoder direction */
+#define   PDEC_CTRLA_CONF_AUTOC_Val       _U_(0x4)   /**< \brief (PDEC_CTRLA) Auto correction mode */
+#define PDEC_CTRLA_CONF_X4          (PDEC_CTRLA_CONF_X4_Val        << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X4S         (PDEC_CTRLA_CONF_X4S_Val       << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X2          (PDEC_CTRLA_CONF_X2_Val        << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_X2S         (PDEC_CTRLA_CONF_X2S_Val       << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_CONF_AUTOC       (PDEC_CTRLA_CONF_AUTOC_Val     << PDEC_CTRLA_CONF_Pos)
+#define PDEC_CTRLA_ALOCK_Pos        11           /**< \brief (PDEC_CTRLA) Auto Lock */
+#define PDEC_CTRLA_ALOCK            (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
+#define PDEC_CTRLA_SWAP_Pos         14           /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
+#define PDEC_CTRLA_SWAP             (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
+#define PDEC_CTRLA_PEREN_Pos        15           /**< \brief (PDEC_CTRLA) Period Enable */
+#define PDEC_CTRLA_PEREN            (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
+#define PDEC_CTRLA_PINEN0_Pos       16           /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
+#define PDEC_CTRLA_PINEN0           (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
+#define PDEC_CTRLA_PINEN1_Pos       17           /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
+#define PDEC_CTRLA_PINEN1           (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
+#define PDEC_CTRLA_PINEN2_Pos       18           /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
+#define PDEC_CTRLA_PINEN2           (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
+#define PDEC_CTRLA_PINEN_Pos        16           /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
+#define PDEC_CTRLA_PINEN_Msk        (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
+#define PDEC_CTRLA_PINEN(value)     (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
+#define PDEC_CTRLA_PINVEN0_Pos      20           /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
+#define PDEC_CTRLA_PINVEN0          (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
+#define PDEC_CTRLA_PINVEN1_Pos      21           /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
+#define PDEC_CTRLA_PINVEN1          (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
+#define PDEC_CTRLA_PINVEN2_Pos      22           /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
+#define PDEC_CTRLA_PINVEN2          (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
+#define PDEC_CTRLA_PINVEN_Pos       20           /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
+#define PDEC_CTRLA_PINVEN_Msk       (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
+#define PDEC_CTRLA_PINVEN(value)    (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
+#define PDEC_CTRLA_ANGULAR_Pos      24           /**< \brief (PDEC_CTRLA) Angular Counter Length */
+#define PDEC_CTRLA_ANGULAR_Msk      (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
+#define PDEC_CTRLA_ANGULAR(value)   (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
+#define PDEC_CTRLA_MAXCMP_Pos       28           /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
+#define PDEC_CTRLA_MAXCMP_Msk       (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
+#define PDEC_CTRLA_MAXCMP(value)    (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
+#define PDEC_CTRLA_MASK             _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
+
+/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLBCLR_OFFSET        0x04         /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
+#define PDEC_CTRLBCLR_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
+
+#define PDEC_CTRLBCLR_LUPD_Pos      1            /**< \brief (PDEC_CTRLBCLR) Lock Update */
+#define PDEC_CTRLBCLR_LUPD          (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
+#define PDEC_CTRLBCLR_CMD_Pos       5            /**< \brief (PDEC_CTRLBCLR) Command */
+#define PDEC_CTRLBCLR_CMD_Msk       (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD(value)    (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
+#define   PDEC_CTRLBCLR_CMD_NONE_Val      _U_(0x0)   /**< \brief (PDEC_CTRLBCLR) No action */
+#define   PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1)   /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
+#define   PDEC_CTRLBCLR_CMD_UPDATE_Val    _U_(0x2)   /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
+#define   PDEC_CTRLBCLR_CMD_READSYNC_Val  _U_(0x3)   /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
+#define   PDEC_CTRLBCLR_CMD_START_Val     _U_(0x4)   /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
+#define   PDEC_CTRLBCLR_CMD_STOP_Val      _U_(0x5)   /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
+#define PDEC_CTRLBCLR_CMD_NONE      (PDEC_CTRLBCLR_CMD_NONE_Val    << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_UPDATE    (PDEC_CTRLBCLR_CMD_UPDATE_Val  << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_READSYNC  (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_START     (PDEC_CTRLBCLR_CMD_START_Val   << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_CMD_STOP      (PDEC_CTRLBCLR_CMD_STOP_Val    << PDEC_CTRLBCLR_CMD_Pos)
+#define PDEC_CTRLBCLR_MASK          _U_(0xE2)    /**< \brief (PDEC_CTRLBCLR) MASK Register */
+
+/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CTRLBSET_OFFSET        0x05         /**< \brief (PDEC_CTRLBSET offset) Control B Set */
+#define PDEC_CTRLBSET_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
+
+#define PDEC_CTRLBSET_LUPD_Pos      1            /**< \brief (PDEC_CTRLBSET) Lock Update */
+#define PDEC_CTRLBSET_LUPD          (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
+#define PDEC_CTRLBSET_CMD_Pos       5            /**< \brief (PDEC_CTRLBSET) Command */
+#define PDEC_CTRLBSET_CMD_Msk       (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD(value)    (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
+#define   PDEC_CTRLBSET_CMD_NONE_Val      _U_(0x0)   /**< \brief (PDEC_CTRLBSET) No action */
+#define   PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1)   /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
+#define   PDEC_CTRLBSET_CMD_UPDATE_Val    _U_(0x2)   /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
+#define   PDEC_CTRLBSET_CMD_READSYNC_Val  _U_(0x3)   /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
+#define   PDEC_CTRLBSET_CMD_START_Val     _U_(0x4)   /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
+#define   PDEC_CTRLBSET_CMD_STOP_Val      _U_(0x5)   /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
+#define PDEC_CTRLBSET_CMD_NONE      (PDEC_CTRLBSET_CMD_NONE_Val    << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_UPDATE    (PDEC_CTRLBSET_CMD_UPDATE_Val  << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_READSYNC  (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_START     (PDEC_CTRLBSET_CMD_START_Val   << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_CMD_STOP      (PDEC_CTRLBSET_CMD_STOP_Val    << PDEC_CTRLBSET_CMD_Pos)
+#define PDEC_CTRLBSET_MASK          _U_(0xE2)    /**< \brief (PDEC_CTRLBSET) MASK Register */
+
+/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EVACT:2;          /*!< bit:  0.. 1  Event Action                       */
+    uint16_t EVINV:3;          /*!< bit:  2.. 4  Inverted Event Input Enable        */
+    uint16_t EVEI:3;           /*!< bit:  5.. 7  Event Input Enable                 */
+    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint16_t ERREO:1;          /*!< bit:      9  Error  Output Event Enable         */
+    uint16_t DIREO:1;          /*!< bit:     10  Direction Output Event Enable      */
+    uint16_t VLCEO:1;          /*!< bit:     11  Velocity Output Event Enable       */
+    uint16_t MCEO0:1;          /*!< bit:     12  Match Channel 0 Event Output Enable */
+    uint16_t MCEO1:1;          /*!< bit:     13  Match Channel 1 Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t MCEO:2;           /*!< bit: 12..13  Match Channel x Event Output Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} PDEC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_EVCTRL_OFFSET          0x06         /**< \brief (PDEC_EVCTRL offset) Event Control */
+#define PDEC_EVCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (PDEC_EVCTRL reset_value) Event Control */
+
+#define PDEC_EVCTRL_EVACT_Pos       0            /**< \brief (PDEC_EVCTRL) Event Action */
+#define PDEC_EVCTRL_EVACT_Msk       (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT(value)    (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
+#define   PDEC_EVCTRL_EVACT_OFF_Val       _U_(0x0)   /**< \brief (PDEC_EVCTRL) Event action disabled */
+#define   PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1)   /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
+#define   PDEC_EVCTRL_EVACT_COUNT_Val     _U_(0x2)   /**< \brief (PDEC_EVCTRL) Count on event */
+#define PDEC_EVCTRL_EVACT_OFF       (PDEC_EVCTRL_EVACT_OFF_Val     << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVACT_COUNT     (PDEC_EVCTRL_EVACT_COUNT_Val   << PDEC_EVCTRL_EVACT_Pos)
+#define PDEC_EVCTRL_EVINV_Pos       2            /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
+#define PDEC_EVCTRL_EVINV_Msk       (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
+#define PDEC_EVCTRL_EVINV(value)    (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
+#define PDEC_EVCTRL_EVEI_Pos        5            /**< \brief (PDEC_EVCTRL) Event Input Enable */
+#define PDEC_EVCTRL_EVEI_Msk        (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
+#define PDEC_EVCTRL_EVEI(value)     (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
+#define PDEC_EVCTRL_OVFEO_Pos       8            /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define PDEC_EVCTRL_OVFEO           (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
+#define PDEC_EVCTRL_ERREO_Pos       9            /**< \brief (PDEC_EVCTRL) Error  Output Event Enable */
+#define PDEC_EVCTRL_ERREO           (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
+#define PDEC_EVCTRL_DIREO_Pos       10           /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
+#define PDEC_EVCTRL_DIREO           (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
+#define PDEC_EVCTRL_VLCEO_Pos       11           /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
+#define PDEC_EVCTRL_VLCEO           (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
+#define PDEC_EVCTRL_MCEO0_Pos       12           /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
+#define PDEC_EVCTRL_MCEO0           (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
+#define PDEC_EVCTRL_MCEO1_Pos       13           /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
+#define PDEC_EVCTRL_MCEO1           (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
+#define PDEC_EVCTRL_MCEO_Pos        12           /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
+#define PDEC_EVCTRL_MCEO_Msk        (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
+#define PDEC_EVCTRL_MCEO(value)     (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
+#define PDEC_EVCTRL_MASK            _U_(0x3FFF)  /**< \brief (PDEC_EVCTRL) MASK Register */
+
+/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow/Underflow Interrupt Disable */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Disable            */
+    uint8_t  DIR:1;            /*!< bit:      2  Direction Interrupt Disable        */
+    uint8_t  VLC:1;            /*!< bit:      3  Velocity Interrupt Disable         */
+    uint8_t  MC0:1;            /*!< bit:      4  Channel 0 Compare Match Disable    */
+    uint8_t  MC1:1;            /*!< bit:      5  Channel 1 Compare Match Disable    */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Channel x Compare Match Disable    */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTENCLR_OFFSET        0x08         /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
+#define PDEC_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PDEC_INTENCLR_OVF_Pos       0            /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
+#define PDEC_INTENCLR_OVF           (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
+#define PDEC_INTENCLR_ERR_Pos       1            /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
+#define PDEC_INTENCLR_ERR           (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
+#define PDEC_INTENCLR_DIR_Pos       2            /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
+#define PDEC_INTENCLR_DIR           (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
+#define PDEC_INTENCLR_VLC_Pos       3            /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
+#define PDEC_INTENCLR_VLC           (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
+#define PDEC_INTENCLR_MC0_Pos       4            /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
+#define PDEC_INTENCLR_MC0           (_U_(1) << PDEC_INTENCLR_MC0_Pos)
+#define PDEC_INTENCLR_MC1_Pos       5            /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
+#define PDEC_INTENCLR_MC1           (_U_(1) << PDEC_INTENCLR_MC1_Pos)
+#define PDEC_INTENCLR_MC_Pos        4            /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
+#define PDEC_INTENCLR_MC_Msk        (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
+#define PDEC_INTENCLR_MC(value)     (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
+#define PDEC_INTENCLR_MASK          _U_(0x3F)    /**< \brief (PDEC_INTENCLR) MASK Register */
+
+/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  Overflow/Underflow Interrupt Enable */
+    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  DIR:1;            /*!< bit:      2  Direction Interrupt Enable         */
+    uint8_t  VLC:1;            /*!< bit:      3  Velocity Interrupt Enable          */
+    uint8_t  MC0:1;            /*!< bit:      4  Channel 0 Compare Match Enable     */
+    uint8_t  MC1:1;            /*!< bit:      5  Channel 1 Compare Match Enable     */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  Channel x Compare Match Enable     */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTENSET_OFFSET        0x09         /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
+#define PDEC_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
+
+#define PDEC_INTENSET_OVF_Pos       0            /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
+#define PDEC_INTENSET_OVF           (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
+#define PDEC_INTENSET_ERR_Pos       1            /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
+#define PDEC_INTENSET_ERR           (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
+#define PDEC_INTENSET_DIR_Pos       2            /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
+#define PDEC_INTENSET_DIR           (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
+#define PDEC_INTENSET_VLC_Pos       3            /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
+#define PDEC_INTENSET_VLC           (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
+#define PDEC_INTENSET_MC0_Pos       4            /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
+#define PDEC_INTENSET_MC0           (_U_(1) << PDEC_INTENSET_MC0_Pos)
+#define PDEC_INTENSET_MC1_Pos       5            /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
+#define PDEC_INTENSET_MC1           (_U_(1) << PDEC_INTENSET_MC1_Pos)
+#define PDEC_INTENSET_MC_Pos        4            /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
+#define PDEC_INTENSET_MC_Msk        (_U_(0x3) << PDEC_INTENSET_MC_Pos)
+#define PDEC_INTENSET_MC(value)     (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
+#define PDEC_INTENSET_MASK          _U_(0x3F)    /**< \brief (PDEC_INTENSET) MASK Register */
+
+/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  OVF:1;            /*!< bit:      0  Overflow/Underflow                 */
+    __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
+    __I uint8_t  DIR:1;            /*!< bit:      2  Direction Change                   */
+    __I uint8_t  VLC:1;            /*!< bit:      3  Velocity                           */
+    __I uint8_t  MC0:1;            /*!< bit:      4  Channel 0 Compare Match            */
+    __I uint8_t  MC1:1;            /*!< bit:      5  Channel 1 Compare Match            */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    __I uint8_t  MC:2;             /*!< bit:  4.. 5  Channel x Compare Match            */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_INTFLAG_OFFSET         0x0A         /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PDEC_INTFLAG_RESETVALUE     _U_(0x00)    /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PDEC_INTFLAG_OVF_Pos        0            /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
+#define PDEC_INTFLAG_OVF            (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
+#define PDEC_INTFLAG_ERR_Pos        1            /**< \brief (PDEC_INTFLAG) Error */
+#define PDEC_INTFLAG_ERR            (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
+#define PDEC_INTFLAG_DIR_Pos        2            /**< \brief (PDEC_INTFLAG) Direction Change */
+#define PDEC_INTFLAG_DIR            (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
+#define PDEC_INTFLAG_VLC_Pos        3            /**< \brief (PDEC_INTFLAG) Velocity */
+#define PDEC_INTFLAG_VLC            (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
+#define PDEC_INTFLAG_MC0_Pos        4            /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
+#define PDEC_INTFLAG_MC0            (_U_(1) << PDEC_INTFLAG_MC0_Pos)
+#define PDEC_INTFLAG_MC1_Pos        5            /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
+#define PDEC_INTFLAG_MC1            (_U_(1) << PDEC_INTFLAG_MC1_Pos)
+#define PDEC_INTFLAG_MC_Pos         4            /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
+#define PDEC_INTFLAG_MC_Msk         (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
+#define PDEC_INTFLAG_MC(value)      (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
+#define PDEC_INTFLAG_MASK           _U_(0x3F)    /**< \brief (PDEC_INTFLAG) MASK Register */
+
+/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t QERR:1;           /*!< bit:      0  Quadrature Error Flag              */
+    uint16_t IDXERR:1;         /*!< bit:      1  Index Error Flag                   */
+    uint16_t MPERR:1;          /*!< bit:      2  Missing Pulse Error flag           */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t WINERR:1;         /*!< bit:      4  Window Error Flag                  */
+    uint16_t HERR:1;           /*!< bit:      5  Hall Error Flag                    */
+    uint16_t STOP:1;           /*!< bit:      6  Stop                               */
+    uint16_t DIR:1;            /*!< bit:      7  Direction Status Flag              */
+    uint16_t PRESCBUFV:1;      /*!< bit:      8  Prescaler Buffer Valid             */
+    uint16_t FILTERBUFV:1;     /*!< bit:      9  Filter Buffer Valid                */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t CCBUFV0:1;        /*!< bit:     12  Compare Channel 0 Buffer Valid     */
+    uint16_t CCBUFV1:1;        /*!< bit:     13  Compare Channel 1 Buffer Valid     */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t CCBUFV:2;         /*!< bit: 12..13  Compare Channel x Buffer Valid     */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} PDEC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_STATUS_OFFSET          0x0C         /**< \brief (PDEC_STATUS offset) Status */
+#define PDEC_STATUS_RESETVALUE      _U_(0x0040)  /**< \brief (PDEC_STATUS reset_value) Status */
+
+#define PDEC_STATUS_QERR_Pos        0            /**< \brief (PDEC_STATUS) Quadrature Error Flag */
+#define PDEC_STATUS_QERR            (_U_(0x1) << PDEC_STATUS_QERR_Pos)
+#define PDEC_STATUS_IDXERR_Pos      1            /**< \brief (PDEC_STATUS) Index Error Flag */
+#define PDEC_STATUS_IDXERR          (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
+#define PDEC_STATUS_MPERR_Pos       2            /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
+#define PDEC_STATUS_MPERR           (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
+#define PDEC_STATUS_WINERR_Pos      4            /**< \brief (PDEC_STATUS) Window Error Flag */
+#define PDEC_STATUS_WINERR          (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
+#define PDEC_STATUS_HERR_Pos        5            /**< \brief (PDEC_STATUS) Hall Error Flag */
+#define PDEC_STATUS_HERR            (_U_(0x1) << PDEC_STATUS_HERR_Pos)
+#define PDEC_STATUS_STOP_Pos        6            /**< \brief (PDEC_STATUS) Stop */
+#define PDEC_STATUS_STOP            (_U_(0x1) << PDEC_STATUS_STOP_Pos)
+#define PDEC_STATUS_DIR_Pos         7            /**< \brief (PDEC_STATUS) Direction Status Flag */
+#define PDEC_STATUS_DIR             (_U_(0x1) << PDEC_STATUS_DIR_Pos)
+#define PDEC_STATUS_PRESCBUFV_Pos   8            /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
+#define PDEC_STATUS_PRESCBUFV       (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
+#define PDEC_STATUS_FILTERBUFV_Pos  9            /**< \brief (PDEC_STATUS) Filter Buffer Valid */
+#define PDEC_STATUS_FILTERBUFV      (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
+#define PDEC_STATUS_CCBUFV0_Pos     12           /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
+#define PDEC_STATUS_CCBUFV0         (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
+#define PDEC_STATUS_CCBUFV1_Pos     13           /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
+#define PDEC_STATUS_CCBUFV1         (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
+#define PDEC_STATUS_CCBUFV_Pos      12           /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
+#define PDEC_STATUS_CCBUFV_Msk      (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
+#define PDEC_STATUS_CCBUFV(value)   (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
+#define PDEC_STATUS_MASK            _U_(0x33F7)  /**< \brief (PDEC_STATUS) MASK Register */
+
+/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_DBGCTRL_OFFSET         0x0F         /**< \brief (PDEC_DBGCTRL offset) Debug Control */
+#define PDEC_DBGCTRL_RESETVALUE     _U_(0x00)    /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
+
+#define PDEC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
+#define PDEC_DBGCTRL_DBGRUN         (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
+#define PDEC_DBGCTRL_MASK           _U_(0x01)    /**< \brief (PDEC_DBGCTRL) MASK Register */
+
+/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/  32) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Control B Synchronization Busy     */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Synchronization Busy        */
+    uint32_t PRESC:1;          /*!< bit:      4  Prescaler Synchronization Busy     */
+    uint32_t FILTER:1;         /*!< bit:      5  Filter Synchronization Busy        */
+    uint32_t COUNT:1;          /*!< bit:      6  Count Synchronization Busy         */
+    uint32_t CC0:1;            /*!< bit:      7  Compare Channel 0 Synchronization Busy */
+    uint32_t CC1:1;            /*!< bit:      8  Compare Channel 1 Synchronization Busy */
+    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint32_t CC:2;             /*!< bit:  7.. 8  Compare Channel x Synchronization Busy */
+    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PDEC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_SYNCBUSY_OFFSET        0x10         /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
+#define PDEC_SYNCBUSY_RESETVALUE    _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
+
+#define PDEC_SYNCBUSY_SWRST_Pos     0            /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
+#define PDEC_SYNCBUSY_SWRST         (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
+#define PDEC_SYNCBUSY_ENABLE_Pos    1            /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
+#define PDEC_SYNCBUSY_ENABLE        (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
+#define PDEC_SYNCBUSY_CTRLB_Pos     2            /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
+#define PDEC_SYNCBUSY_CTRLB         (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
+#define PDEC_SYNCBUSY_STATUS_Pos    3            /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
+#define PDEC_SYNCBUSY_STATUS        (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
+#define PDEC_SYNCBUSY_PRESC_Pos     4            /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
+#define PDEC_SYNCBUSY_PRESC         (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
+#define PDEC_SYNCBUSY_FILTER_Pos    5            /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
+#define PDEC_SYNCBUSY_FILTER        (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
+#define PDEC_SYNCBUSY_COUNT_Pos     6            /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
+#define PDEC_SYNCBUSY_COUNT         (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
+#define PDEC_SYNCBUSY_CC0_Pos       7            /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
+#define PDEC_SYNCBUSY_CC0           (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
+#define PDEC_SYNCBUSY_CC1_Pos       8            /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
+#define PDEC_SYNCBUSY_CC1           (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
+#define PDEC_SYNCBUSY_CC_Pos        7            /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
+#define PDEC_SYNCBUSY_CC_Msk        (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
+#define PDEC_SYNCBUSY_CC(value)     (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
+#define PDEC_SYNCBUSY_MASK          _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
+
+/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W  8) Prescaler Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PRESC:4;          /*!< bit:  0.. 3  Prescaler Value                    */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_PRESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_PRESC_OFFSET           0x14         /**< \brief (PDEC_PRESC offset) Prescaler Value */
+#define PDEC_PRESC_RESETVALUE       _U_(0x00)    /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
+
+#define PDEC_PRESC_PRESC_Pos        0            /**< \brief (PDEC_PRESC) Prescaler Value */
+#define PDEC_PRESC_PRESC_Msk        (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC(value)     (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
+#define   PDEC_PRESC_PRESC_DIV1_Val       _U_(0x0)   /**< \brief (PDEC_PRESC) No division */
+#define   PDEC_PRESC_PRESC_DIV2_Val       _U_(0x1)   /**< \brief (PDEC_PRESC) Divide by 2 */
+#define   PDEC_PRESC_PRESC_DIV4_Val       _U_(0x2)   /**< \brief (PDEC_PRESC) Divide by 4 */
+#define   PDEC_PRESC_PRESC_DIV8_Val       _U_(0x3)   /**< \brief (PDEC_PRESC) Divide by 8 */
+#define   PDEC_PRESC_PRESC_DIV16_Val      _U_(0x4)   /**< \brief (PDEC_PRESC) Divide by 16 */
+#define   PDEC_PRESC_PRESC_DIV32_Val      _U_(0x5)   /**< \brief (PDEC_PRESC) Divide by 32 */
+#define   PDEC_PRESC_PRESC_DIV64_Val      _U_(0x6)   /**< \brief (PDEC_PRESC) Divide by 64 */
+#define   PDEC_PRESC_PRESC_DIV128_Val     _U_(0x7)   /**< \brief (PDEC_PRESC) Divide by 128 */
+#define   PDEC_PRESC_PRESC_DIV256_Val     _U_(0x8)   /**< \brief (PDEC_PRESC) Divide by 256 */
+#define   PDEC_PRESC_PRESC_DIV512_Val     _U_(0x9)   /**< \brief (PDEC_PRESC) Divide by 512 */
+#define   PDEC_PRESC_PRESC_DIV1024_Val    _U_(0xA)   /**< \brief (PDEC_PRESC) Divide by 1024 */
+#define PDEC_PRESC_PRESC_DIV1       (PDEC_PRESC_PRESC_DIV1_Val     << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV2       (PDEC_PRESC_PRESC_DIV2_Val     << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV4       (PDEC_PRESC_PRESC_DIV4_Val     << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV8       (PDEC_PRESC_PRESC_DIV8_Val     << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV16      (PDEC_PRESC_PRESC_DIV16_Val    << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV32      (PDEC_PRESC_PRESC_DIV32_Val    << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV64      (PDEC_PRESC_PRESC_DIV64_Val    << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV128     (PDEC_PRESC_PRESC_DIV128_Val   << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV256     (PDEC_PRESC_PRESC_DIV256_Val   << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV512     (PDEC_PRESC_PRESC_DIV512_Val   << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_PRESC_DIV1024    (PDEC_PRESC_PRESC_DIV1024_Val  << PDEC_PRESC_PRESC_Pos)
+#define PDEC_PRESC_MASK             _U_(0x0F)    /**< \brief (PDEC_PRESC) MASK Register */
+
+/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W  8) Filter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FILTER:8;         /*!< bit:  0.. 7  Filter Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_FILTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_FILTER_OFFSET          0x15         /**< \brief (PDEC_FILTER offset) Filter Value */
+#define PDEC_FILTER_RESETVALUE      _U_(0x00)    /**< \brief (PDEC_FILTER reset_value) Filter Value */
+
+#define PDEC_FILTER_FILTER_Pos      0            /**< \brief (PDEC_FILTER) Filter Value */
+#define PDEC_FILTER_FILTER_Msk      (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
+#define PDEC_FILTER_FILTER(value)   (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
+#define PDEC_FILTER_MASK            _U_(0xFF)    /**< \brief (PDEC_FILTER) MASK Register */
+
+/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W  8) Prescaler Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PRESCBUF:4;       /*!< bit:  0.. 3  Prescaler Buffer Value             */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_PRESCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_PRESCBUF_OFFSET        0x18         /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
+#define PDEC_PRESCBUF_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
+
+#define PDEC_PRESCBUF_PRESCBUF_Pos  0            /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
+#define PDEC_PRESCBUF_PRESCBUF_Msk  (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
+#define   PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0)   /**< \brief (PDEC_PRESCBUF) No division */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1)   /**< \brief (PDEC_PRESCBUF) Divide by 2 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2)   /**< \brief (PDEC_PRESCBUF) Divide by 4 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3)   /**< \brief (PDEC_PRESCBUF) Divide by 8 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4)   /**< \brief (PDEC_PRESCBUF) Divide by 16 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5)   /**< \brief (PDEC_PRESCBUF) Divide by 32 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6)   /**< \brief (PDEC_PRESCBUF) Divide by 64 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7)   /**< \brief (PDEC_PRESCBUF) Divide by 128 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8)   /**< \brief (PDEC_PRESCBUF) Divide by 256 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9)   /**< \brief (PDEC_PRESCBUF) Divide by 512 */
+#define   PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA)   /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
+#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
+#define PDEC_PRESCBUF_MASK          _U_(0x0F)    /**< \brief (PDEC_PRESCBUF) MASK Register */
+
+/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W  8) Filter Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FILTERBUF:8;      /*!< bit:  0.. 7  Filter Buffer Value                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PDEC_FILTERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_FILTERBUF_OFFSET       0x19         /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
+#define PDEC_FILTERBUF_RESETVALUE   _U_(0x00)    /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
+
+#define PDEC_FILTERBUF_FILTERBUF_Pos 0            /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
+#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
+#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
+#define PDEC_FILTERBUF_MASK         _U_(0xFF)    /**< \brief (PDEC_FILTERBUF) MASK Register */
+
+/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PDEC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_COUNT_OFFSET           0x1C         /**< \brief (PDEC_COUNT offset) Counter Value */
+#define PDEC_COUNT_RESETVALUE       _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
+
+#define PDEC_COUNT_COUNT_Pos        0            /**< \brief (PDEC_COUNT) Counter Value */
+#define PDEC_COUNT_COUNT_Msk        (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
+#define PDEC_COUNT_COUNT(value)     (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
+#define PDEC_COUNT_MASK             _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
+
+/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CC:16;            /*!< bit:  0..15  Channel Compare Value              */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PDEC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CC_OFFSET              0x20         /**< \brief (PDEC_CC offset) Channel n Compare Value */
+#define PDEC_CC_RESETVALUE          _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
+
+#define PDEC_CC_CC_Pos              0            /**< \brief (PDEC_CC) Channel Compare Value */
+#define PDEC_CC_CC_Msk              (_U_(0xFFFF) << PDEC_CC_CC_Pos)
+#define PDEC_CC_CC(value)           (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
+#define PDEC_CC_MASK                _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
+
+/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CCBUF:16;         /*!< bit:  0..15  Channel Compare Buffer Value       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PDEC_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PDEC_CCBUF_OFFSET           0x30         /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
+#define PDEC_CCBUF_RESETVALUE       _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
+
+#define PDEC_CCBUF_CCBUF_Pos        0            /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
+#define PDEC_CCBUF_CCBUF_Msk        (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
+#define PDEC_CCBUF_CCBUF(value)     (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
+#define PDEC_CCBUF_MASK             _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
+
+/** \brief PDEC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PDEC_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO PDEC_CTRLBCLR_Type        CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO PDEC_CTRLBSET_Type        CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO PDEC_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
+  __IO PDEC_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
+  __IO PDEC_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
+  __IO PDEC_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved1[0x1];
+  __IO PDEC_STATUS_Type          STATUS;      /**< \brief Offset: 0x0C (R/W 16) Status */
+       RoReg8                    Reserved2[0x1];
+  __IO PDEC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
+  __I  PDEC_SYNCBUSY_Type        SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
+  __IO PDEC_PRESC_Type           PRESC;       /**< \brief Offset: 0x14 (R/W  8) Prescaler Value */
+  __IO PDEC_FILTER_Type          FILTER;      /**< \brief Offset: 0x15 (R/W  8) Filter Value */
+       RoReg8                    Reserved3[0x2];
+  __IO PDEC_PRESCBUF_Type        PRESCBUF;    /**< \brief Offset: 0x18 (R/W  8) Prescaler Buffer Value */
+  __IO PDEC_FILTERBUF_Type       FILTERBUF;   /**< \brief Offset: 0x19 (R/W  8) Filter Buffer Value */
+       RoReg8                    Reserved4[0x2];
+  __IO PDEC_COUNT_Type           COUNT;       /**< \brief Offset: 0x1C (R/W 32) Counter Value */
+  __IO PDEC_CC_Type              CC[2];       /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
+       RoReg8                    Reserved5[0x8];
+  __IO PDEC_CCBUF_Type           CCBUF[2];    /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
+} Pdec;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_PDEC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pm.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pm.h
new file mode 100644
index 000000000..25c6adc26
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/pm.h	
@@ -0,0 +1,261 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PM_COMPONENT_
+#define _SAME53_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAME53_PM Power Manager */
+/*@{*/
+
+#define PM_U2406
+#define REV_PM                      0x100
+
+/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  IORET:1;          /*!< bit:      2  I/O Retention                      */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRLA_OFFSET             0x00         /**< \brief (PM_CTRLA offset) Control A */
+#define PM_CTRLA_RESETVALUE         _U_(0x00)    /**< \brief (PM_CTRLA reset_value) Control A */
+
+#define PM_CTRLA_IORET_Pos          2            /**< \brief (PM_CTRLA) I/O Retention */
+#define PM_CTRLA_IORET              (_U_(0x1) << PM_CTRLA_IORET_Pos)
+#define PM_CTRLA_MASK               _U_(0x04)    /**< \brief (PM_CTRLA) MASK Register */
+
+/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W  8) Sleep Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SLEEPMODE:3;      /*!< bit:  0.. 2  Sleep Mode                         */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEPCFG_OFFSET          0x01         /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
+#define PM_SLEEPCFG_RESETVALUE      _U_(0x02)    /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
+
+#define PM_SLEEPCFG_SLEEPMODE_Pos   0            /**< \brief (PM_SLEEPCFG) Sleep Mode */
+#define PM_SLEEPCFG_SLEEPMODE_Msk   (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
+#define   PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0)   /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
+#define   PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1)   /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
+#define   PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2)   /**< \brief (PM_SLEEPCFG) APB clock are OFF */
+#define   PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4)   /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
+#define   PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5)   /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
+#define   PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6)   /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
+#define   PM_SLEEPCFG_SLEEPMODE_OFF_Val   _U_(0x7)   /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_OFF   (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_MASK            _U_(0x07)    /**< \brief (PM_SLEEPCFG) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SLEEPRDY:1;       /*!< bit:      0  Sleep Mode Entry Ready Enable      */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x04         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_SLEEPRDY_Pos    0            /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
+#define PM_INTENCLR_SLEEPRDY        (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
+#define PM_INTENCLR_MASK            _U_(0x01)    /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SLEEPRDY:1;       /*!< bit:      0  Sleep Mode Entry Ready Enable      */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x05         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_SLEEPRDY_Pos    0            /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
+#define PM_INTENSET_SLEEPRDY        (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
+#define PM_INTENSET_MASK            _U_(0x01)    /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  SLEEPRDY:1;       /*!< bit:      0  Sleep Mode Entry Ready             */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x06         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_SLEEPRDY_Pos     0            /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
+#define PM_INTFLAG_SLEEPRDY         (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
+#define PM_INTFLAG_MASK             _U_(0x01)    /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W  8) Standby Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RAMCFG:2;         /*!< bit:  0.. 1  Ram Configuration                  */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  FASTWKUP:2;       /*!< bit:  4.. 5  Fast Wakeup                        */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_STDBYCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_STDBYCFG_OFFSET          0x08         /**< \brief (PM_STDBYCFG offset) Standby Configuration */
+#define PM_STDBYCFG_RESETVALUE      _U_(0x00)    /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
+
+#define PM_STDBYCFG_RAMCFG_Pos      0            /**< \brief (PM_STDBYCFG) Ram Configuration */
+#define PM_STDBYCFG_RAMCFG_Msk      (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG(value)   (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
+#define   PM_STDBYCFG_RAMCFG_RET_Val      _U_(0x0)   /**< \brief (PM_STDBYCFG) All the RAMs are retained */
+#define   PM_STDBYCFG_RAMCFG_PARTIAL_Val  _U_(0x1)   /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
+#define   PM_STDBYCFG_RAMCFG_OFF_Val      _U_(0x2)   /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
+#define PM_STDBYCFG_RAMCFG_RET      (PM_STDBYCFG_RAMCFG_RET_Val    << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG_PARTIAL  (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_RAMCFG_OFF      (PM_STDBYCFG_RAMCFG_OFF_Val    << PM_STDBYCFG_RAMCFG_Pos)
+#define PM_STDBYCFG_FASTWKUP_Pos    4            /**< \brief (PM_STDBYCFG) Fast Wakeup */
+#define PM_STDBYCFG_FASTWKUP_Msk    (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
+#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
+#define PM_STDBYCFG_MASK            _U_(0x33)    /**< \brief (PM_STDBYCFG) MASK Register */
+
+/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W  8) Hibernate Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RAMCFG:2;         /*!< bit:  0.. 1  Ram Configuration                  */
+    uint8_t  BRAMCFG:2;        /*!< bit:  2.. 3  Backup Ram Configuration           */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_HIBCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_HIBCFG_OFFSET            0x09         /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
+#define PM_HIBCFG_RESETVALUE        _U_(0x00)    /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
+
+#define PM_HIBCFG_RAMCFG_Pos        0            /**< \brief (PM_HIBCFG) Ram Configuration */
+#define PM_HIBCFG_RAMCFG_Msk        (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
+#define PM_HIBCFG_RAMCFG(value)     (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
+#define PM_HIBCFG_BRAMCFG_Pos       2            /**< \brief (PM_HIBCFG) Backup Ram Configuration */
+#define PM_HIBCFG_BRAMCFG_Msk       (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
+#define PM_HIBCFG_BRAMCFG(value)    (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
+#define PM_HIBCFG_MASK              _U_(0x0F)    /**< \brief (PM_HIBCFG) MASK Register */
+
+/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W  8) Backup Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BRAMCFG:2;        /*!< bit:  0.. 1  Ram Configuration                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_BKUPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_BKUPCFG_OFFSET           0x0A         /**< \brief (PM_BKUPCFG offset) Backup Configuration */
+#define PM_BKUPCFG_RESETVALUE       _U_(0x00)    /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
+
+#define PM_BKUPCFG_BRAMCFG_Pos      0            /**< \brief (PM_BKUPCFG) Ram Configuration */
+#define PM_BKUPCFG_BRAMCFG_Msk      (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
+#define PM_BKUPCFG_BRAMCFG(value)   (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
+#define PM_BKUPCFG_MASK             _U_(0x03)    /**< \brief (PM_BKUPCFG) MASK Register */
+
+/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W  8) Power Switch Acknowledge Delay -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DLYVAL:7;         /*!< bit:  0.. 6  Delay Value                        */
+    uint8_t  IGNACK:1;         /*!< bit:      7  Ignore Acknowledge                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_PWSAKDLY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_PWSAKDLY_OFFSET          0x12         /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
+#define PM_PWSAKDLY_RESETVALUE      _U_(0x00)    /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
+
+#define PM_PWSAKDLY_DLYVAL_Pos      0            /**< \brief (PM_PWSAKDLY) Delay Value */
+#define PM_PWSAKDLY_DLYVAL_Msk      (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
+#define PM_PWSAKDLY_DLYVAL(value)   (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
+#define PM_PWSAKDLY_IGNACK_Pos      7            /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
+#define PM_PWSAKDLY_IGNACK          (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
+#define PM_PWSAKDLY_MASK            _U_(0xFF)    /**< \brief (PM_PWSAKDLY) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO PM_SLEEPCFG_Type          SLEEPCFG;    /**< \brief Offset: 0x01 (R/W  8) Sleep Configuration */
+       RoReg8                    Reserved1[0x2];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO PM_STDBYCFG_Type          STDBYCFG;    /**< \brief Offset: 0x08 (R/W  8) Standby Configuration */
+  __IO PM_HIBCFG_Type            HIBCFG;      /**< \brief Offset: 0x09 (R/W  8) Hibernate Configuration */
+  __IO PM_BKUPCFG_Type           BKUPCFG;     /**< \brief Offset: 0x0A (R/W  8) Backup Configuration */
+       RoReg8                    Reserved3[0x7];
+  __IO PM_PWSAKDLY_Type          PWSAKDLY;    /**< \brief Offset: 0x12 (R/W  8) Power Switch Acknowledge Delay */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_PM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/port.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/port.h
new file mode 100644
index 000000000..1d38194a4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/port.h	
@@ -0,0 +1,414 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PORT_COMPONENT_
+#define _SAME53_PORT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAME53_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT                    0x220
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE         _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk            (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK               _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk      (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk      (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk      (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUT:32;           /*!< bit:  0..31  PORT Data Output Value             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE         _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) PORT Data Output Value */
+#define PORT_OUT_OUT_Msk            (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK               _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTCLR:32;        /*!< bit:  0..31  PORT Data Output Value Clear       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk      (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTSET:32;        /*!< bit:  0..31  PORT Data Output Value Set         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) PORT Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk      (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTTGL:32;        /*!< bit:  0..31  PORT Data Output Value Toggle      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk      (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN:32;            /*!< bit:  0..31  PORT Data Input Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE          _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) PORT Data Input Value */
+#define PORT_IN_IN_Msk              (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK                _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE        _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk      (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK              _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
+    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
+    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
+    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
+    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
+    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
+    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
+    uint32_t :1;               /*!< bit:     29  Reserved                           */
+    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
+    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE    _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk   (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN        (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN          (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN        (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR        (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk      (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX        (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG      (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL         (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK          _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PID0:5;           /*!< bit:  0.. 4  PORT Event Pin Identifier 0        */
+    uint32_t EVACT0:2;         /*!< bit:  5.. 6  PORT Event Action 0                */
+    uint32_t PORTEI0:1;        /*!< bit:      7  PORT Event Input Enable 0          */
+    uint32_t PID1:5;           /*!< bit:  8..12  PORT Event Pin Identifier 1        */
+    uint32_t EVACT1:2;         /*!< bit: 13..14  PORT Event Action 1                */
+    uint32_t PORTEI1:1;        /*!< bit:     15  PORT Event Input Enable 1          */
+    uint32_t PID2:5;           /*!< bit: 16..20  PORT Event Pin Identifier 2        */
+    uint32_t EVACT2:2;         /*!< bit: 21..22  PORT Event Action 2                */
+    uint32_t PORTEI2:1;        /*!< bit:     23  PORT Event Input Enable 2          */
+    uint32_t PID3:5;           /*!< bit: 24..28  PORT Event Pin Identifier 3        */
+    uint32_t EVACT3:2;         /*!< bit: 29..30  PORT Event Action 3                */
+    uint32_t PORTEI3:1;        /*!< bit:     31  PORT Event Input Enable 3          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_EVCTRL_OFFSET          0x2C         /**< \brief (PORT_EVCTRL offset) Event Input Control */
+#define PORT_EVCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
+
+#define PORT_EVCTRL_PID0_Pos        0            /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */
+#define PORT_EVCTRL_PID0_Msk        (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
+#define PORT_EVCTRL_PID0(value)     (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
+#define PORT_EVCTRL_EVACT0_Pos      5            /**< \brief (PORT_EVCTRL) PORT Event Action 0 */
+#define PORT_EVCTRL_EVACT0_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0(value)   (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
+#define   PORT_EVCTRL_EVACT0_OUT_Val      _U_(0x0)   /**< \brief (PORT_EVCTRL) Event output to pin */
+#define   PORT_EVCTRL_EVACT0_SET_Val      _U_(0x1)   /**< \brief (PORT_EVCTRL) Set output register of pin on event */
+#define   PORT_EVCTRL_EVACT0_CLR_Val      _U_(0x2)   /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
+#define   PORT_EVCTRL_EVACT0_TGL_Val      _U_(0x3)   /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
+#define PORT_EVCTRL_EVACT0_OUT      (PORT_EVCTRL_EVACT0_OUT_Val    << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_SET      (PORT_EVCTRL_EVACT0_SET_Val    << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_CLR      (PORT_EVCTRL_EVACT0_CLR_Val    << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0_TGL      (PORT_EVCTRL_EVACT0_TGL_Val    << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_PORTEI0_Pos     7            /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */
+#define PORT_EVCTRL_PORTEI0         (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
+#define PORT_EVCTRL_PID1_Pos        8            /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */
+#define PORT_EVCTRL_PID1_Msk        (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
+#define PORT_EVCTRL_PID1(value)     (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
+#define PORT_EVCTRL_EVACT1_Pos      13           /**< \brief (PORT_EVCTRL) PORT Event Action 1 */
+#define PORT_EVCTRL_EVACT1_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
+#define PORT_EVCTRL_EVACT1(value)   (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
+#define PORT_EVCTRL_PORTEI1_Pos     15           /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */
+#define PORT_EVCTRL_PORTEI1         (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
+#define PORT_EVCTRL_PID2_Pos        16           /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */
+#define PORT_EVCTRL_PID2_Msk        (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
+#define PORT_EVCTRL_PID2(value)     (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
+#define PORT_EVCTRL_EVACT2_Pos      21           /**< \brief (PORT_EVCTRL) PORT Event Action 2 */
+#define PORT_EVCTRL_EVACT2_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
+#define PORT_EVCTRL_EVACT2(value)   (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
+#define PORT_EVCTRL_PORTEI2_Pos     23           /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */
+#define PORT_EVCTRL_PORTEI2         (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
+#define PORT_EVCTRL_PID3_Pos        24           /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */
+#define PORT_EVCTRL_PID3_Msk        (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
+#define PORT_EVCTRL_PID3(value)     (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
+#define PORT_EVCTRL_EVACT3_Pos      29           /**< \brief (PORT_EVCTRL) PORT Event Action 3 */
+#define PORT_EVCTRL_EVACT3_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
+#define PORT_EVCTRL_EVACT3(value)   (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
+#define PORT_EVCTRL_PORTEI3_Pos     31           /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */
+#define PORT_EVCTRL_PORTEI3         (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
+#define PORT_EVCTRL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing for Even-Numbered Pin */
+    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing for Odd-Numbered Pin */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */
+#define PORT_PMUX_RESETVALUE        _U_(0x00)    /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */
+
+#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
+#define PORT_PMUX_PMUXE_Msk         (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
+#define PORT_PMUX_PMUXO_Msk         (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define PORT_PMUX_MASK              _U_(0xFF)    /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
+    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
+    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration */
+#define PORT_PINCFG_RESETVALUE      _U_(0x00)    /**< \brief (PORT_PINCFG reset_value) Pin Configuration */
+
+#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN          (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN            (_U_(0x1) << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN          (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR          (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK            _U_(0x47)    /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
+  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
+  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+  __IO PORT_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
+  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing */
+  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration */
+       RoReg8                    Reserved1[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       PortGroup                 Group[3];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_PORT_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/qspi.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/qspi.h
new file mode 100644
index 000000000..955471b1d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/qspi.h	
@@ -0,0 +1,528 @@
+/**
+ * \file
+ *
+ * \brief Component description for QSPI
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_QSPI_COMPONENT_
+#define _SAME53_QSPI_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR QSPI */
+/* ========================================================================== */
+/** \addtogroup SAME53_QSPI Quad SPI interface */
+/*@{*/
+
+#define QSPI_U2008
+#define REV_QSPI                    0x163
+
+/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :22;              /*!< bit:  2..23  Reserved                           */
+    uint32_t LASTXFER:1;       /*!< bit:     24  Last Transfer                      */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_CTRLA_OFFSET           0x00         /**< \brief (QSPI_CTRLA offset) Control A */
+#define QSPI_CTRLA_RESETVALUE       _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
+
+#define QSPI_CTRLA_SWRST_Pos        0            /**< \brief (QSPI_CTRLA) Software Reset */
+#define QSPI_CTRLA_SWRST            (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
+#define QSPI_CTRLA_ENABLE_Pos       1            /**< \brief (QSPI_CTRLA) Enable */
+#define QSPI_CTRLA_ENABLE           (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
+#define QSPI_CTRLA_LASTXFER_Pos     24           /**< \brief (QSPI_CTRLA) Last Transfer */
+#define QSPI_CTRLA_LASTXFER         (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
+#define QSPI_CTRLA_MASK             _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
+
+/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MODE:1;           /*!< bit:      0  Serial Memory Mode                 */
+    uint32_t LOOPEN:1;         /*!< bit:      1  Local Loopback Enable              */
+    uint32_t WDRBT:1;          /*!< bit:      2  Wait Data Read Before Transfer     */
+    uint32_t SMEMREG:1;        /*!< bit:      3  Serial Memory reg                  */
+    uint32_t CSMODE:2;         /*!< bit:  4.. 5  Chip Select Mode                   */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t DATALEN:4;        /*!< bit:  8..11  Data Length                        */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DLYBCT:8;         /*!< bit: 16..23  Delay Between Consecutive Transfers */
+    uint32_t DLYCS:8;          /*!< bit: 24..31  Minimum Inactive CS Delay          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_CTRLB_OFFSET           0x04         /**< \brief (QSPI_CTRLB offset) Control B */
+#define QSPI_CTRLB_RESETVALUE       _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
+
+#define QSPI_CTRLB_MODE_Pos         0            /**< \brief (QSPI_CTRLB) Serial Memory Mode */
+#define QSPI_CTRLB_MODE             (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
+#define   QSPI_CTRLB_MODE_SPI_Val         _U_(0x0)   /**< \brief (QSPI_CTRLB) SPI operating mode */
+#define   QSPI_CTRLB_MODE_MEMORY_Val      _U_(0x1)   /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
+#define QSPI_CTRLB_MODE_SPI         (QSPI_CTRLB_MODE_SPI_Val       << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_MODE_MEMORY      (QSPI_CTRLB_MODE_MEMORY_Val    << QSPI_CTRLB_MODE_Pos)
+#define QSPI_CTRLB_LOOPEN_Pos       1            /**< \brief (QSPI_CTRLB) Local Loopback Enable */
+#define QSPI_CTRLB_LOOPEN           (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
+#define QSPI_CTRLB_WDRBT_Pos        2            /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
+#define QSPI_CTRLB_WDRBT            (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
+#define QSPI_CTRLB_SMEMREG_Pos      3            /**< \brief (QSPI_CTRLB) Serial Memory reg */
+#define QSPI_CTRLB_SMEMREG          (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
+#define QSPI_CTRLB_CSMODE_Pos       4            /**< \brief (QSPI_CTRLB) Chip Select Mode */
+#define QSPI_CTRLB_CSMODE_Msk       (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE(value)    (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
+#define   QSPI_CTRLB_CSMODE_NORELOAD_Val  _U_(0x0)   /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
+#define   QSPI_CTRLB_CSMODE_LASTXFER_Val  _U_(0x1)   /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
+#define   QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2)   /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
+#define QSPI_CTRLB_CSMODE_NORELOAD  (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE_LASTXFER  (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
+#define QSPI_CTRLB_DATALEN_Pos      8            /**< \brief (QSPI_CTRLB) Data Length */
+#define QSPI_CTRLB_DATALEN_Msk      (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN(value)   (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
+#define   QSPI_CTRLB_DATALEN_8BITS_Val    _U_(0x0)   /**< \brief (QSPI_CTRLB) 8-bits transfer */
+#define   QSPI_CTRLB_DATALEN_9BITS_Val    _U_(0x1)   /**< \brief (QSPI_CTRLB) 9 bits transfer */
+#define   QSPI_CTRLB_DATALEN_10BITS_Val   _U_(0x2)   /**< \brief (QSPI_CTRLB) 10-bits transfer */
+#define   QSPI_CTRLB_DATALEN_11BITS_Val   _U_(0x3)   /**< \brief (QSPI_CTRLB) 11-bits transfer */
+#define   QSPI_CTRLB_DATALEN_12BITS_Val   _U_(0x4)   /**< \brief (QSPI_CTRLB) 12-bits transfer */
+#define   QSPI_CTRLB_DATALEN_13BITS_Val   _U_(0x5)   /**< \brief (QSPI_CTRLB) 13-bits transfer */
+#define   QSPI_CTRLB_DATALEN_14BITS_Val   _U_(0x6)   /**< \brief (QSPI_CTRLB) 14-bits transfer */
+#define   QSPI_CTRLB_DATALEN_15BITS_Val   _U_(0x7)   /**< \brief (QSPI_CTRLB) 15-bits transfer */
+#define   QSPI_CTRLB_DATALEN_16BITS_Val   _U_(0x8)   /**< \brief (QSPI_CTRLB) 16-bits transfer */
+#define QSPI_CTRLB_DATALEN_8BITS    (QSPI_CTRLB_DATALEN_8BITS_Val  << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_9BITS    (QSPI_CTRLB_DATALEN_9BITS_Val  << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_10BITS   (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_11BITS   (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_12BITS   (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_13BITS   (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_14BITS   (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_15BITS   (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DATALEN_16BITS   (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
+#define QSPI_CTRLB_DLYBCT_Pos       16           /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
+#define QSPI_CTRLB_DLYBCT_Msk       (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
+#define QSPI_CTRLB_DLYBCT(value)    (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
+#define QSPI_CTRLB_DLYCS_Pos        24           /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
+#define QSPI_CTRLB_DLYCS_Msk        (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
+#define QSPI_CTRLB_DLYCS(value)     (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
+#define QSPI_CTRLB_MASK             _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
+
+/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CPOL:1;           /*!< bit:      0  Clock Polarity                     */
+    uint32_t CPHA:1;           /*!< bit:      1  Clock Phase                        */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t BAUD:8;           /*!< bit:  8..15  Serial Clock Baud Rate             */
+    uint32_t DLYBS:8;          /*!< bit: 16..23  Delay Before SCK                   */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_BAUD_OFFSET            0x08         /**< \brief (QSPI_BAUD offset) Baud Rate */
+#define QSPI_BAUD_RESETVALUE        _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
+
+#define QSPI_BAUD_CPOL_Pos          0            /**< \brief (QSPI_BAUD) Clock Polarity */
+#define QSPI_BAUD_CPOL              (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
+#define QSPI_BAUD_CPHA_Pos          1            /**< \brief (QSPI_BAUD) Clock Phase */
+#define QSPI_BAUD_CPHA              (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
+#define QSPI_BAUD_BAUD_Pos          8            /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
+#define QSPI_BAUD_BAUD_Msk          (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
+#define QSPI_BAUD_BAUD(value)       (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
+#define QSPI_BAUD_DLYBS_Pos         16           /**< \brief (QSPI_BAUD) Delay Before SCK */
+#define QSPI_BAUD_DLYBS_Msk         (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
+#define QSPI_BAUD_DLYBS(value)      (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
+#define QSPI_BAUD_MASK              _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
+
+/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/  32) Receive Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:16;          /*!< bit:  0..15  Receive Data                       */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_RXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_RXDATA_OFFSET          0x0C         /**< \brief (QSPI_RXDATA offset) Receive Data */
+#define QSPI_RXDATA_RESETVALUE      _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
+
+#define QSPI_RXDATA_DATA_Pos        0            /**< \brief (QSPI_RXDATA) Receive Data */
+#define QSPI_RXDATA_DATA_Msk        (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
+#define QSPI_RXDATA_DATA(value)     (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
+#define QSPI_RXDATA_MASK            _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
+
+/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:16;          /*!< bit:  0..15  Transmit Data                      */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_TXDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_TXDATA_OFFSET          0x10         /**< \brief (QSPI_TXDATA offset) Transmit Data */
+#define QSPI_TXDATA_RESETVALUE      _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
+
+#define QSPI_TXDATA_DATA_Pos        0            /**< \brief (QSPI_TXDATA) Transmit Data */
+#define QSPI_TXDATA_DATA_Msk        (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
+#define QSPI_TXDATA_DATA(value)     (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
+#define QSPI_TXDATA_MASK            _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
+
+/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXC:1;            /*!< bit:      0  Receive Data Register Full Interrupt Disable */
+    uint32_t DRE:1;            /*!< bit:      1  Transmit Data Register Empty Interrupt Disable */
+    uint32_t TXC:1;            /*!< bit:      2  Transmission Complete Interrupt Disable */
+    uint32_t ERROR:1;          /*!< bit:      3  Overrun Error Interrupt Disable    */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t CSRISE:1;         /*!< bit:      8  Chip Select Rise Interrupt Disable */
+    uint32_t :1;               /*!< bit:      9  Reserved                           */
+    uint32_t INSTREND:1;       /*!< bit:     10  Instruction End Interrupt Disable  */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTENCLR_OFFSET        0x14         /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
+#define QSPI_INTENCLR_RESETVALUE    _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define QSPI_INTENCLR_RXC_Pos       0            /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
+#define QSPI_INTENCLR_RXC           (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
+#define QSPI_INTENCLR_DRE_Pos       1            /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
+#define QSPI_INTENCLR_DRE           (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
+#define QSPI_INTENCLR_TXC_Pos       2            /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
+#define QSPI_INTENCLR_TXC           (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
+#define QSPI_INTENCLR_ERROR_Pos     3            /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
+#define QSPI_INTENCLR_ERROR         (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
+#define QSPI_INTENCLR_CSRISE_Pos    8            /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
+#define QSPI_INTENCLR_CSRISE        (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
+#define QSPI_INTENCLR_INSTREND_Pos  10           /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
+#define QSPI_INTENCLR_INSTREND      (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
+#define QSPI_INTENCLR_MASK          _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
+
+/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RXC:1;            /*!< bit:      0  Receive Data Register Full Interrupt Enable */
+    uint32_t DRE:1;            /*!< bit:      1  Transmit Data Register Empty Interrupt Enable */
+    uint32_t TXC:1;            /*!< bit:      2  Transmission Complete Interrupt Enable */
+    uint32_t ERROR:1;          /*!< bit:      3  Overrun Error Interrupt Enable     */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t CSRISE:1;         /*!< bit:      8  Chip Select Rise Interrupt Enable  */
+    uint32_t :1;               /*!< bit:      9  Reserved                           */
+    uint32_t INSTREND:1;       /*!< bit:     10  Instruction End Interrupt Enable   */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTENSET_OFFSET        0x18         /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
+#define QSPI_INTENSET_RESETVALUE    _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
+
+#define QSPI_INTENSET_RXC_Pos       0            /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
+#define QSPI_INTENSET_RXC           (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
+#define QSPI_INTENSET_DRE_Pos       1            /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
+#define QSPI_INTENSET_DRE           (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
+#define QSPI_INTENSET_TXC_Pos       2            /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
+#define QSPI_INTENSET_TXC           (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
+#define QSPI_INTENSET_ERROR_Pos     3            /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
+#define QSPI_INTENSET_ERROR         (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
+#define QSPI_INTENSET_CSRISE_Pos    8            /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
+#define QSPI_INTENSET_CSRISE        (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
+#define QSPI_INTENSET_INSTREND_Pos  10           /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
+#define QSPI_INTENSET_INSTREND      (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
+#define QSPI_INTENSET_MASK          _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
+
+/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t RXC:1;            /*!< bit:      0  Receive Data Register Full         */
+    __I uint32_t DRE:1;            /*!< bit:      1  Transmit Data Register Empty       */
+    __I uint32_t TXC:1;            /*!< bit:      2  Transmission Complete              */
+    __I uint32_t ERROR:1;          /*!< bit:      3  Overrun Error                      */
+    __I uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    __I uint32_t CSRISE:1;         /*!< bit:      8  Chip Select Rise                   */
+    __I uint32_t :1;               /*!< bit:      9  Reserved                           */
+    __I uint32_t INSTREND:1;       /*!< bit:     10  Instruction End                    */
+    __I uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INTFLAG_OFFSET         0x1C         /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
+#define QSPI_INTFLAG_RESETVALUE     _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define QSPI_INTFLAG_RXC_Pos        0            /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
+#define QSPI_INTFLAG_RXC            (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
+#define QSPI_INTFLAG_DRE_Pos        1            /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
+#define QSPI_INTFLAG_DRE            (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
+#define QSPI_INTFLAG_TXC_Pos        2            /**< \brief (QSPI_INTFLAG) Transmission Complete */
+#define QSPI_INTFLAG_TXC            (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
+#define QSPI_INTFLAG_ERROR_Pos      3            /**< \brief (QSPI_INTFLAG) Overrun Error */
+#define QSPI_INTFLAG_ERROR          (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
+#define QSPI_INTFLAG_CSRISE_Pos     8            /**< \brief (QSPI_INTFLAG) Chip Select Rise */
+#define QSPI_INTFLAG_CSRISE         (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
+#define QSPI_INTFLAG_INSTREND_Pos   10           /**< \brief (QSPI_INTFLAG) Instruction End */
+#define QSPI_INTFLAG_INSTREND       (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
+#define QSPI_INTFLAG_MASK           _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
+
+/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/  32) Status Register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :7;               /*!< bit:  2.. 8  Reserved                           */
+    uint32_t CSSTATUS:1;       /*!< bit:      9  Chip Select                        */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_STATUS_OFFSET          0x20         /**< \brief (QSPI_STATUS offset) Status Register */
+#define QSPI_STATUS_RESETVALUE      _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
+
+#define QSPI_STATUS_ENABLE_Pos      1            /**< \brief (QSPI_STATUS) Enable */
+#define QSPI_STATUS_ENABLE          (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
+#define QSPI_STATUS_CSSTATUS_Pos    9            /**< \brief (QSPI_STATUS) Chip Select */
+#define QSPI_STATUS_CSSTATUS        (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
+#define QSPI_STATUS_MASK            _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
+
+/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Instruction Address                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_INSTRADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRADDR_OFFSET       0x30         /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
+#define QSPI_INSTRADDR_RESETVALUE   _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
+
+#define QSPI_INSTRADDR_ADDR_Pos     0            /**< \brief (QSPI_INSTRADDR) Instruction Address */
+#define QSPI_INSTRADDR_ADDR_Msk     (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
+#define QSPI_INSTRADDR_ADDR(value)  (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
+#define QSPI_INSTRADDR_MASK         _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
+
+/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t INSTR:8;          /*!< bit:  0.. 7  Instruction Code                   */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t OPTCODE:8;        /*!< bit: 16..23  Option Code                        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_INSTRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRCTRL_OFFSET       0x34         /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
+#define QSPI_INSTRCTRL_RESETVALUE   _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
+
+#define QSPI_INSTRCTRL_INSTR_Pos    0            /**< \brief (QSPI_INSTRCTRL) Instruction Code */
+#define QSPI_INSTRCTRL_INSTR_Msk    (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
+#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
+#define QSPI_INSTRCTRL_OPTCODE_Pos  16           /**< \brief (QSPI_INSTRCTRL) Option Code */
+#define QSPI_INSTRCTRL_OPTCODE_Msk  (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
+#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
+#define QSPI_INSTRCTRL_MASK         _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
+
+/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WIDTH:3;          /*!< bit:  0.. 2  Instruction Code, Address, Option Code and Data Width */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t INSTREN:1;        /*!< bit:      4  Instruction Enable                 */
+    uint32_t ADDREN:1;         /*!< bit:      5  Address Enable                     */
+    uint32_t OPTCODEEN:1;      /*!< bit:      6  Option Enable                      */
+    uint32_t DATAEN:1;         /*!< bit:      7  Data Enable                        */
+    uint32_t OPTCODELEN:2;     /*!< bit:  8.. 9  Option Code Length                 */
+    uint32_t ADDRLEN:1;        /*!< bit:     10  Address Length                     */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TFRTYPE:2;        /*!< bit: 12..13  Data Transfer Type                 */
+    uint32_t CRMODE:1;         /*!< bit:     14  Continuous Read Mode               */
+    uint32_t DDREN:1;          /*!< bit:     15  Double Data Rate Enable            */
+    uint32_t DUMMYLEN:5;       /*!< bit: 16..20  Dummy Cycles Length                */
+    uint32_t :11;              /*!< bit: 21..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_INSTRFRAME_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_INSTRFRAME_OFFSET      0x38         /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
+#define QSPI_INSTRFRAME_RESETVALUE  _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
+
+#define QSPI_INSTRFRAME_WIDTH_Pos   0            /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
+#define QSPI_INSTRFRAME_WIDTH_Msk   (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
+#define   QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
+#define   QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
+#define   QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
+#define   QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define   QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define   QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5)   /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define   QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6)   /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
+#define QSPI_INSTRFRAME_INSTREN_Pos 4            /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
+#define QSPI_INSTRFRAME_INSTREN     (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
+#define QSPI_INSTRFRAME_ADDREN_Pos  5            /**< \brief (QSPI_INSTRFRAME) Address Enable */
+#define QSPI_INSTRFRAME_ADDREN      (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
+#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6            /**< \brief (QSPI_INSTRFRAME) Option Enable */
+#define QSPI_INSTRFRAME_OPTCODEEN   (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
+#define QSPI_INSTRFRAME_DATAEN_Pos  7            /**< \brief (QSPI_INSTRFRAME) Data Enable */
+#define QSPI_INSTRFRAME_DATAEN      (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8            /**< \brief (QSPI_INSTRFRAME) Option Code Length */
+#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
+#define   QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
+#define   QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
+#define   QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2)   /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
+#define   QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3)   /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
+#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_Pos 10           /**< \brief (QSPI_INSTRFRAME) Address Length */
+#define QSPI_INSTRFRAME_ADDRLEN     (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define   QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
+#define   QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
+#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_Pos 12           /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
+#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
+#define   QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
+#define   QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
+#define   QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2)   /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
+#define   QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3)   /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
+#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
+#define QSPI_INSTRFRAME_CRMODE_Pos  14           /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
+#define QSPI_INSTRFRAME_CRMODE      (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
+#define QSPI_INSTRFRAME_DDREN_Pos   15           /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
+#define QSPI_INSTRFRAME_DDREN       (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
+#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16           /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
+#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
+#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
+#define QSPI_INSTRFRAME_MASK        _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
+
+/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ENABLE:1;         /*!< bit:      0  Scrambling/Unscrambling Enable     */
+    uint32_t RANDOMDIS:1;      /*!< bit:      1  Scrambling/Unscrambling Random Value Disable */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_SCRAMBCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_SCRAMBCTRL_OFFSET      0x40         /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
+#define QSPI_SCRAMBCTRL_RESETVALUE  _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
+
+#define QSPI_SCRAMBCTRL_ENABLE_Pos  0            /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
+#define QSPI_SCRAMBCTRL_ENABLE      (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
+#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1            /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
+#define QSPI_SCRAMBCTRL_RANDOMDIS   (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
+#define QSPI_SCRAMBCTRL_MASK        _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
+
+/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t KEY:32;           /*!< bit:  0..31  Scrambling User Key                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} QSPI_SCRAMBKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define QSPI_SCRAMBKEY_OFFSET       0x44         /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
+#define QSPI_SCRAMBKEY_RESETVALUE   _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
+
+#define QSPI_SCRAMBKEY_KEY_Pos      0            /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
+#define QSPI_SCRAMBKEY_KEY_Msk      (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
+#define QSPI_SCRAMBKEY_KEY(value)   (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
+#define QSPI_SCRAMBKEY_MASK         _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
+
+/** \brief QSPI APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO QSPI_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO QSPI_CTRLB_Type           CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO QSPI_BAUD_Type            BAUD;        /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
+  __I  QSPI_RXDATA_Type          RXDATA;      /**< \brief Offset: 0x0C (R/  32) Receive Data */
+  __O  QSPI_TXDATA_Type          TXDATA;      /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
+  __IO QSPI_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
+  __IO QSPI_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
+  __IO QSPI_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
+  __I  QSPI_STATUS_Type          STATUS;      /**< \brief Offset: 0x20 (R/  32) Status Register */
+       RoReg8                    Reserved1[0xC];
+  __IO QSPI_INSTRADDR_Type       INSTRADDR;   /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
+  __IO QSPI_INSTRCTRL_Type       INSTRCTRL;   /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
+  __IO QSPI_INSTRFRAME_Type      INSTRFRAME;  /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
+       RoReg8                    Reserved2[0x4];
+  __IO QSPI_SCRAMBCTRL_Type      SCRAMBCTRL;  /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
+  __O  QSPI_SCRAMBKEY_Type       SCRAMBKEY;   /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
+} Qspi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_QSPI_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ramecc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ramecc.h
new file mode 100644
index 000000000..d1dd3d19c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/ramecc.h	
@@ -0,0 +1,178 @@
+/**
+ * \file
+ *
+ * \brief Component description for RAMECC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_RAMECC_COMPONENT_
+#define _SAME53_RAMECC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RAMECC */
+/* ========================================================================== */
+/** \addtogroup SAME53_RAMECC RAM ECC */
+/*@{*/
+
+#define RAMECC_U2268
+#define REV_RAMECC                  0x100
+
+/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt Enable Clear */
+    uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt Enable Clear */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RAMECC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTENCLR_OFFSET      0x0          /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
+#define RAMECC_INTENCLR_RESETVALUE  _U_(0x00)    /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define RAMECC_INTENCLR_SINGLEE_Pos 0            /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
+#define RAMECC_INTENCLR_SINGLEE     (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
+#define RAMECC_INTENCLR_DUALE_Pos   1            /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
+#define RAMECC_INTENCLR_DUALE       (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
+#define RAMECC_INTENCLR_MASK        _U_(0x03)    /**< \brief (RAMECC_INTENCLR) MASK Register */
+
+/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt Enable Set */
+    uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt Enable Set */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RAMECC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTENSET_OFFSET      0x1          /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
+#define RAMECC_INTENSET_RESETVALUE  _U_(0x00)    /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
+
+#define RAMECC_INTENSET_SINGLEE_Pos 0            /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
+#define RAMECC_INTENSET_SINGLEE     (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
+#define RAMECC_INTENSET_DUALE_Pos   1            /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
+#define RAMECC_INTENSET_DUALE       (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
+#define RAMECC_INTENSET_MASK        _U_(0x03)    /**< \brief (RAMECC_INTENSET) MASK Register */
+
+/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W  8) Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt     */
+    __I uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt       */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RAMECC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_INTFLAG_OFFSET       0x2          /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
+#define RAMECC_INTFLAG_RESETVALUE   _U_(0x00)    /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
+
+#define RAMECC_INTFLAG_SINGLEE_Pos  0            /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
+#define RAMECC_INTFLAG_SINGLEE      (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
+#define RAMECC_INTFLAG_DUALE_Pos    1            /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
+#define RAMECC_INTFLAG_DUALE        (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
+#define RAMECC_INTFLAG_MASK         _U_(0x03)    /**< \brief (RAMECC_INTFLAG) MASK Register */
+
+/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ECCDIS:1;         /*!< bit:      0  ECC Disable                        */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RAMECC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_STATUS_OFFSET        0x3          /**< \brief (RAMECC_STATUS offset) Status */
+#define RAMECC_STATUS_RESETVALUE    _U_(0x00)    /**< \brief (RAMECC_STATUS reset_value) Status */
+
+#define RAMECC_STATUS_ECCDIS_Pos    0            /**< \brief (RAMECC_STATUS) ECC Disable */
+#define RAMECC_STATUS_ECCDIS        (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
+#define RAMECC_STATUS_MASK          _U_(0x01)    /**< \brief (RAMECC_STATUS) MASK Register */
+
+/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/  32) Error Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ERRADDR:17;       /*!< bit:  0..16  Error Address                      */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RAMECC_ERRADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_ERRADDR_OFFSET       0x4          /**< \brief (RAMECC_ERRADDR offset) Error Address */
+#define RAMECC_ERRADDR_RESETVALUE   _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
+
+#define RAMECC_ERRADDR_ERRADDR_Pos  0            /**< \brief (RAMECC_ERRADDR) Error Address */
+#define RAMECC_ERRADDR_ERRADDR_Msk  (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
+#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
+#define RAMECC_ERRADDR_MASK         _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
+
+/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ECCDIS:1;         /*!< bit:      0  ECC Disable                        */
+    uint8_t  ECCELOG:1;        /*!< bit:      1  ECC Error Log                      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RAMECC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RAMECC_DBGCTRL_OFFSET       0xF          /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
+#define RAMECC_DBGCTRL_RESETVALUE   _U_(0x00)    /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
+
+#define RAMECC_DBGCTRL_ECCDIS_Pos   0            /**< \brief (RAMECC_DBGCTRL) ECC Disable */
+#define RAMECC_DBGCTRL_ECCDIS       (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
+#define RAMECC_DBGCTRL_ECCELOG_Pos  1            /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
+#define RAMECC_DBGCTRL_ECCELOG      (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
+#define RAMECC_DBGCTRL_MASK         _U_(0x03)    /**< \brief (RAMECC_DBGCTRL) MASK Register */
+
+/** \brief RAMECC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO RAMECC_INTENCLR_Type      INTENCLR;    /**< \brief Offset: 0x0 (R/W  8) Interrupt Enable Clear */
+  __IO RAMECC_INTENSET_Type      INTENSET;    /**< \brief Offset: 0x1 (R/W  8) Interrupt Enable Set */
+  __IO RAMECC_INTFLAG_Type       INTFLAG;     /**< \brief Offset: 0x2 (R/W  8) Interrupt Flag */
+  __I  RAMECC_STATUS_Type        STATUS;      /**< \brief Offset: 0x3 (R/   8) Status */
+  __I  RAMECC_ERRADDR_Type       ERRADDR;     /**< \brief Offset: 0x4 (R/  32) Error Address */
+       RoReg8                    Reserved1[0x7];
+  __IO RAMECC_DBGCTRL_Type       DBGCTRL;     /**< \brief Offset: 0xF (R/W  8) Debug Control */
+} Ramecc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_RAMECC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/rstc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/rstc.h
new file mode 100644
index 000000000..317e4c245
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/rstc.h	
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Component description for RSTC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_RSTC_COMPONENT_
+#define _SAME53_RSTC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RSTC */
+/* ========================================================================== */
+/** \addtogroup SAME53_RSTC Reset Controller */
+/*@{*/
+
+#define RSTC_U2239
+#define REV_RSTC                    0x400
+
+/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/   8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
+    uint8_t  BODCORE:1;        /*!< bit:      1  Brown Out CORE Detector Reset      */
+    uint8_t  BODVDD:1;         /*!< bit:      2  Brown Out VDD Detector Reset       */
+    uint8_t  NVM:1;            /*!< bit:      3  NVM Reset                          */
+    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
+    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
+    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
+    uint8_t  BACKUP:1;         /*!< bit:      7  Backup Reset                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RSTC_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RSTC_RCAUSE_OFFSET          0x00         /**< \brief (RSTC_RCAUSE offset) Reset Cause */
+
+#define RSTC_RCAUSE_POR_Pos         0            /**< \brief (RSTC_RCAUSE) Power On Reset */
+#define RSTC_RCAUSE_POR             (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
+#define RSTC_RCAUSE_BODCORE_Pos     1            /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
+#define RSTC_RCAUSE_BODCORE         (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
+#define RSTC_RCAUSE_BODVDD_Pos      2            /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
+#define RSTC_RCAUSE_BODVDD          (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
+#define RSTC_RCAUSE_NVM_Pos         3            /**< \brief (RSTC_RCAUSE) NVM Reset */
+#define RSTC_RCAUSE_NVM             (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
+#define RSTC_RCAUSE_EXT_Pos         4            /**< \brief (RSTC_RCAUSE) External Reset */
+#define RSTC_RCAUSE_EXT             (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
+#define RSTC_RCAUSE_WDT_Pos         5            /**< \brief (RSTC_RCAUSE) Watchdog Reset */
+#define RSTC_RCAUSE_WDT             (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
+#define RSTC_RCAUSE_SYST_Pos        6            /**< \brief (RSTC_RCAUSE) System Reset Request */
+#define RSTC_RCAUSE_SYST            (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
+#define RSTC_RCAUSE_BACKUP_Pos      7            /**< \brief (RSTC_RCAUSE) Backup Reset */
+#define RSTC_RCAUSE_BACKUP          (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
+#define RSTC_RCAUSE_MASK            _U_(0xFF)    /**< \brief (RSTC_RCAUSE) MASK Register */
+
+/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/   8) Backup Exit Source -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  RTC:1;            /*!< bit:      1  Real Timer Counter Interrupt       */
+    uint8_t  BBPS:1;           /*!< bit:      2  Battery Backup Power Switch        */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  HIB:1;            /*!< bit:      7  Hibernate                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RSTC_BKUPEXIT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RSTC_BKUPEXIT_OFFSET        0x02         /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
+#define RSTC_BKUPEXIT_RESETVALUE    _U_(0x00)    /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
+
+#define RSTC_BKUPEXIT_RTC_Pos       1            /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
+#define RSTC_BKUPEXIT_RTC           (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
+#define RSTC_BKUPEXIT_BBPS_Pos      2            /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
+#define RSTC_BKUPEXIT_BBPS          (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
+#define RSTC_BKUPEXIT_HIB_Pos       7            /**< \brief (RSTC_BKUPEXIT) Hibernate */
+#define RSTC_BKUPEXIT_HIB           (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
+#define RSTC_BKUPEXIT_MASK          _U_(0x86)    /**< \brief (RSTC_BKUPEXIT) MASK Register */
+
+/** \brief RSTC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __I  RSTC_RCAUSE_Type          RCAUSE;      /**< \brief Offset: 0x00 (R/   8) Reset Cause */
+       RoReg8                    Reserved1[0x1];
+  __I  RSTC_BKUPEXIT_Type        BKUPEXIT;    /**< \brief Offset: 0x02 (R/   8) Backup Exit Source */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_RSTC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/rtc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/rtc.h
new file mode 100644
index 000000000..245014aea
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/rtc.h	
@@ -0,0 +1,2098 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_RTC_COMPONENT_
+#define _SAME53_RTC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAME53_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2250
+#define REV_RTC                     0x210
+
+/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :1;               /*!< bit:     12  Reserved                           */
+    uint16_t BKTRST:1;         /*!< bit:     13  BKUP Registers Reset On Tamper Enable */
+    uint16_t GPTRST:1;         /*!< bit:     14  GP Registers Reset On Tamper Enable */
+    uint16_t COUNTSYNC:1;      /*!< bit:     15  Count Read Synchronization Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRLA_OFFSET      0x00         /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */
+#define RTC_MODE0_CTRLA_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */
+
+#define RTC_MODE0_CTRLA_SWRST_Pos   0            /**< \brief (RTC_MODE0_CTRLA) Software Reset */
+#define RTC_MODE0_CTRLA_SWRST       (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)
+#define RTC_MODE0_CTRLA_ENABLE_Pos  1            /**< \brief (RTC_MODE0_CTRLA) Enable */
+#define RTC_MODE0_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)
+#define RTC_MODE0_CTRLA_MODE_Pos    2            /**< \brief (RTC_MODE0_CTRLA) Operating Mode */
+#define RTC_MODE0_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
+#define   RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0)   /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */
+#define   RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1)   /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */
+#define   RTC_MODE0_CTRLA_MODE_CLOCK_Val  _U_(0x2)   /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MODE_CLOCK  (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)
+#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRLA) Clear on Match */
+#define RTC_MODE0_CTRLA_MATCHCLR    (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRLA) Prescaler */
+#define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
+#define   RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
+#define RTC_MODE0_CTRLA_BKTRST_Pos  13           /**< \brief (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE0_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)
+#define RTC_MODE0_CTRLA_GPTRST_Pos  14           /**< \brief (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE0_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)
+#define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */
+#define RTC_MODE0_CTRLA_COUNTSYNC   (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
+#define RTC_MODE0_CTRLA_MASK        _U_(0xEF8F)  /**< \brief (RTC_MODE0_CTRLA) MASK Register */
+
+/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :1;               /*!< bit:     12  Reserved                           */
+    uint16_t BKTRST:1;         /*!< bit:     13  BKUP Registers Reset On Tamper Enable */
+    uint16_t GPTRST:1;         /*!< bit:     14  GP Registers Reset On Tamper Enable */
+    uint16_t COUNTSYNC:1;      /*!< bit:     15  Count Read Synchronization Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRLA_OFFSET      0x00         /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */
+#define RTC_MODE1_CTRLA_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */
+
+#define RTC_MODE1_CTRLA_SWRST_Pos   0            /**< \brief (RTC_MODE1_CTRLA) Software Reset */
+#define RTC_MODE1_CTRLA_SWRST       (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)
+#define RTC_MODE1_CTRLA_ENABLE_Pos  1            /**< \brief (RTC_MODE1_CTRLA) Enable */
+#define RTC_MODE1_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)
+#define RTC_MODE1_CTRLA_MODE_Pos    2            /**< \brief (RTC_MODE1_CTRLA) Operating Mode */
+#define RTC_MODE1_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
+#define   RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0)   /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */
+#define   RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1)   /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */
+#define   RTC_MODE1_CTRLA_MODE_CLOCK_Val  _U_(0x2)   /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_MODE_CLOCK  (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRLA) Prescaler */
+#define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
+#define   RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
+#define RTC_MODE1_CTRLA_BKTRST_Pos  13           /**< \brief (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE1_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)
+#define RTC_MODE1_CTRLA_GPTRST_Pos  14           /**< \brief (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE1_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)
+#define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */
+#define RTC_MODE1_CTRLA_COUNTSYNC   (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)
+#define RTC_MODE1_CTRLA_MASK        _U_(0xEF0F)  /**< \brief (RTC_MODE1_CTRLA) MASK Register */
+
+/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
+    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
+    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
+    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
+    uint16_t :1;               /*!< bit:     12  Reserved                           */
+    uint16_t BKTRST:1;         /*!< bit:     13  BKUP Registers Reset On Tamper Enable */
+    uint16_t GPTRST:1;         /*!< bit:     14  GP Registers Reset On Tamper Enable */
+    uint16_t CLOCKSYNC:1;      /*!< bit:     15  Clock Read Synchronization Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRLA_OFFSET      0x00         /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */
+#define RTC_MODE2_CTRLA_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */
+
+#define RTC_MODE2_CTRLA_SWRST_Pos   0            /**< \brief (RTC_MODE2_CTRLA) Software Reset */
+#define RTC_MODE2_CTRLA_SWRST       (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)
+#define RTC_MODE2_CTRLA_ENABLE_Pos  1            /**< \brief (RTC_MODE2_CTRLA) Enable */
+#define RTC_MODE2_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)
+#define RTC_MODE2_CTRLA_MODE_Pos    2            /**< \brief (RTC_MODE2_CTRLA) Operating Mode */
+#define RTC_MODE2_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
+#define   RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0)   /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */
+#define   RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1)   /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */
+#define   RTC_MODE2_CTRLA_MODE_CLOCK_Val  _U_(0x2)   /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_MODE_CLOCK  (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)
+#define RTC_MODE2_CTRLA_CLKREP_Pos  6            /**< \brief (RTC_MODE2_CTRLA) Clock Representation */
+#define RTC_MODE2_CTRLA_CLKREP      (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)
+#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRLA) Clear on Match */
+#define RTC_MODE2_CTRLA_MATCHCLR    (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRLA) Prescaler */
+#define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
+#define   RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
+#define   RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
+#define RTC_MODE2_CTRLA_BKTRST_Pos  13           /**< \brief (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable */
+#define RTC_MODE2_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)
+#define RTC_MODE2_CTRLA_GPTRST_Pos  14           /**< \brief (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable */
+#define RTC_MODE2_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)
+#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15           /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */
+#define RTC_MODE2_CTRLA_CLOCKSYNC   (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)
+#define RTC_MODE2_CTRLA_MASK        _U_(0xEFCF)  /**< \brief (RTC_MODE2_CTRLA) MASK Register */
+
+/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GP0EN:1;          /*!< bit:      0  General Purpose 0 Enable           */
+    uint16_t GP2EN:1;          /*!< bit:      1  General Purpose 2 Enable           */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t DEBMAJ:1;         /*!< bit:      4  Debouncer Majority Enable          */
+    uint16_t DEBASYNC:1;       /*!< bit:      5  Debouncer Asynchronous Enable      */
+    uint16_t RTCOUT:1;         /*!< bit:      6  RTC Output Enable                  */
+    uint16_t DMAEN:1;          /*!< bit:      7  DMA Enable                         */
+    uint16_t DEBF:3;           /*!< bit:  8..10  Debounce Freqnuency                */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t ACTF:3;           /*!< bit: 12..14  Active Layer Freqnuency            */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRLB_OFFSET      0x02         /**< \brief (RTC_MODE0_CTRLB offset) MODE0 Control B */
+#define RTC_MODE0_CTRLB_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE0_CTRLB reset_value) MODE0 Control B */
+
+#define RTC_MODE0_CTRLB_GP0EN_Pos   0            /**< \brief (RTC_MODE0_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE0_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)
+#define RTC_MODE0_CTRLB_GP2EN_Pos   1            /**< \brief (RTC_MODE0_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE0_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)
+#define RTC_MODE0_CTRLB_DEBMAJ_Pos  4            /**< \brief (RTC_MODE0_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE0_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE0_CTRLB_DEBASYNC_Pos 5            /**< \brief (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE0_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE0_CTRLB_RTCOUT_Pos  6            /**< \brief (RTC_MODE0_CTRLB) RTC Output Enable */
+#define RTC_MODE0_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)
+#define RTC_MODE0_CTRLB_DMAEN_Pos   7            /**< \brief (RTC_MODE0_CTRLB) DMA Enable */
+#define RTC_MODE0_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)
+#define RTC_MODE0_CTRLB_DEBF_Pos    8            /**< \brief (RTC_MODE0_CTRLB) Debounce Freqnuency */
+#define RTC_MODE0_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
+#define   RTC_MODE0_CTRLB_DEBF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define   RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE0_CTRLB_DEBF_DIV2   (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV4   (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV8   (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV16  (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV32  (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV64  (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_Pos    12           /**< \brief (RTC_MODE0_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE0_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
+#define   RTC_MODE0_CTRLB_ACTF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define   RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE0_CTRLB_ACTF_DIV2   (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV4   (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV8   (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV16  (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV32  (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV64  (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)
+#define RTC_MODE0_CTRLB_MASK        _U_(0x77F3)  /**< \brief (RTC_MODE0_CTRLB) MASK Register */
+
+/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GP0EN:1;          /*!< bit:      0  General Purpose 0 Enable           */
+    uint16_t GP2EN:1;          /*!< bit:      1  General Purpose 2 Enable           */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t DEBMAJ:1;         /*!< bit:      4  Debouncer Majority Enable          */
+    uint16_t DEBASYNC:1;       /*!< bit:      5  Debouncer Asynchronous Enable      */
+    uint16_t RTCOUT:1;         /*!< bit:      6  RTC Output Enable                  */
+    uint16_t DMAEN:1;          /*!< bit:      7  DMA Enable                         */
+    uint16_t DEBF:3;           /*!< bit:  8..10  Debounce Freqnuency                */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t ACTF:3;           /*!< bit: 12..14  Active Layer Freqnuency            */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRLB_OFFSET      0x02         /**< \brief (RTC_MODE1_CTRLB offset) MODE1 Control B */
+#define RTC_MODE1_CTRLB_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE1_CTRLB reset_value) MODE1 Control B */
+
+#define RTC_MODE1_CTRLB_GP0EN_Pos   0            /**< \brief (RTC_MODE1_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE1_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)
+#define RTC_MODE1_CTRLB_GP2EN_Pos   1            /**< \brief (RTC_MODE1_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE1_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)
+#define RTC_MODE1_CTRLB_DEBMAJ_Pos  4            /**< \brief (RTC_MODE1_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE1_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE1_CTRLB_DEBASYNC_Pos 5            /**< \brief (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE1_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE1_CTRLB_RTCOUT_Pos  6            /**< \brief (RTC_MODE1_CTRLB) RTC Output Enable */
+#define RTC_MODE1_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)
+#define RTC_MODE1_CTRLB_DMAEN_Pos   7            /**< \brief (RTC_MODE1_CTRLB) DMA Enable */
+#define RTC_MODE1_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)
+#define RTC_MODE1_CTRLB_DEBF_Pos    8            /**< \brief (RTC_MODE1_CTRLB) Debounce Freqnuency */
+#define RTC_MODE1_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
+#define   RTC_MODE1_CTRLB_DEBF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define   RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE1_CTRLB_DEBF_DIV2   (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV4   (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV8   (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV16  (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV32  (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV64  (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_Pos    12           /**< \brief (RTC_MODE1_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE1_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
+#define   RTC_MODE1_CTRLB_ACTF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define   RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE1_CTRLB_ACTF_DIV2   (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV4   (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV8   (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV16  (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV32  (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV64  (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)
+#define RTC_MODE1_CTRLB_MASK        _U_(0x77F3)  /**< \brief (RTC_MODE1_CTRLB) MASK Register */
+
+/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GP0EN:1;          /*!< bit:      0  General Purpose 0 Enable           */
+    uint16_t GP2EN:1;          /*!< bit:      1  General Purpose 2 Enable           */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t DEBMAJ:1;         /*!< bit:      4  Debouncer Majority Enable          */
+    uint16_t DEBASYNC:1;       /*!< bit:      5  Debouncer Asynchronous Enable      */
+    uint16_t RTCOUT:1;         /*!< bit:      6  RTC Output Enable                  */
+    uint16_t DMAEN:1;          /*!< bit:      7  DMA Enable                         */
+    uint16_t DEBF:3;           /*!< bit:  8..10  Debounce Freqnuency                */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t ACTF:3;           /*!< bit: 12..14  Active Layer Freqnuency            */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRLB_OFFSET      0x02         /**< \brief (RTC_MODE2_CTRLB offset) MODE2 Control B */
+#define RTC_MODE2_CTRLB_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE2_CTRLB reset_value) MODE2 Control B */
+
+#define RTC_MODE2_CTRLB_GP0EN_Pos   0            /**< \brief (RTC_MODE2_CTRLB) General Purpose 0 Enable */
+#define RTC_MODE2_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)
+#define RTC_MODE2_CTRLB_GP2EN_Pos   1            /**< \brief (RTC_MODE2_CTRLB) General Purpose 2 Enable */
+#define RTC_MODE2_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)
+#define RTC_MODE2_CTRLB_DEBMAJ_Pos  4            /**< \brief (RTC_MODE2_CTRLB) Debouncer Majority Enable */
+#define RTC_MODE2_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)
+#define RTC_MODE2_CTRLB_DEBASYNC_Pos 5            /**< \brief (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable */
+#define RTC_MODE2_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)
+#define RTC_MODE2_CTRLB_RTCOUT_Pos  6            /**< \brief (RTC_MODE2_CTRLB) RTC Output Enable */
+#define RTC_MODE2_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)
+#define RTC_MODE2_CTRLB_DMAEN_Pos   7            /**< \brief (RTC_MODE2_CTRLB) DMA Enable */
+#define RTC_MODE2_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)
+#define RTC_MODE2_CTRLB_DEBF_Pos    8            /**< \brief (RTC_MODE2_CTRLB) Debounce Freqnuency */
+#define RTC_MODE2_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
+#define   RTC_MODE2_CTRLB_DEBF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
+#define   RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
+#define RTC_MODE2_CTRLB_DEBF_DIV2   (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV4   (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV8   (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV16  (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV32  (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV64  (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_Pos    12           /**< \brief (RTC_MODE2_CTRLB) Active Layer Freqnuency */
+#define RTC_MODE2_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
+#define   RTC_MODE2_CTRLB_ACTF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
+#define   RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
+#define RTC_MODE2_CTRLB_ACTF_DIV2   (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV4   (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV8   (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV16  (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV32  (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV64  (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)
+#define RTC_MODE2_CTRLB_MASK        _U_(0x77F3)  /**< \brief (RTC_MODE2_CTRLB) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint32_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint32_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint32_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint32_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint32_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint32_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint32_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint32_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint32_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
+    uint32_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint32_t TAMPEREO:1;       /*!< bit:     14  Tamper Event Output Enable         */
+    uint32_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+    uint32_t TAMPEVEI:1;       /*!< bit:     16  Tamper Event Input Enable          */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint32_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0     (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1     (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2     (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3     (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4     (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5     (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6     (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7     (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0     (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO1     (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk  (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14           /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE0_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16           /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE0_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE0_EVCTRL_MASK       _U_(0x0001C3FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint32_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint32_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint32_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint32_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint32_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint32_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint32_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint32_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
+    uint32_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
+    uint32_t CMPEO2:1;         /*!< bit:     10  Compare 2 Event Output Enable      */
+    uint32_t CMPEO3:1;         /*!< bit:     11  Compare 3 Event Output Enable      */
+    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint32_t TAMPEREO:1;       /*!< bit:     14  Tamper Event Output Enable         */
+    uint32_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+    uint32_t TAMPEVEI:1;       /*!< bit:     16  Tamper Event Input Enable          */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint32_t CMPEO:4;          /*!< bit:  8..11  Compare x Event Output Enable      */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0     (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1     (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2     (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3     (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4     (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5     (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6     (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7     (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO2_Pos 10           /**< \brief (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO2     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO3_Pos 11           /**< \brief (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO3     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk  (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14           /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE1_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16           /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE1_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE1_EVCTRL_MASK       _U_(0x0001CFFF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
+    uint32_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
+    uint32_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
+    uint32_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
+    uint32_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
+    uint32_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
+    uint32_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
+    uint32_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
+    uint32_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
+    uint32_t ALARMEO1:1;       /*!< bit:      9  Alarm 1 Event Output Enable        */
+    uint32_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint32_t TAMPEREO:1;       /*!< bit:     14  Tamper Event Output Enable         */
+    uint32_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
+    uint32_t TAMPEVEI:1;       /*!< bit:     16  Tamper Event Input Enable          */
+    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
+    uint32_t ALARMEO:2;        /*!< bit:  8.. 9  Alarm x Event Output Enable        */
+    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0     (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1     (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2     (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3     (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4     (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5     (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6     (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7     (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0   (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9            /**< \brief (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO1   (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14           /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Output Enable */
+#define RTC_MODE2_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)
+#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16           /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Input Enable */
+#define RTC_MODE2_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)
+#define RTC_MODE2_EVCTRL_MASK       _U_(0x0001C3FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
+    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
+    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
+    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
+    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
+    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
+    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
+    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
+    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
+    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
+    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
+    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
+    uint16_t CMP:2;            /*!< bit:  8.. 9  Compare x Interrupt Enable         */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET   0x08         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_PER0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER0     (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)
+#define RTC_MODE0_INTENCLR_PER1_Pos 1            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER1     (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)
+#define RTC_MODE0_INTENCLR_PER2_Pos 2            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER2     (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)
+#define RTC_MODE0_INTENCLR_PER3_Pos 3            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER3     (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)
+#define RTC_MODE0_INTENCLR_PER4_Pos 4            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER4     (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)
+#define RTC_MODE0_INTENCLR_PER5_Pos 5            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER5     (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)
+#define RTC_MODE0_INTENCLR_PER6_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER6     (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)
+#define RTC_MODE0_INTENCLR_PER7_Pos 7            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER7     (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)
+#define RTC_MODE0_INTENCLR_PER_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)
+#define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))
+#define RTC_MODE0_INTENCLR_CMP0_Pos 8            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0     (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP1_Pos 9            /**< \brief (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP1     (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos  8            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk  (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_TAMPER_Pos 14           /**< \brief (RTC_MODE0_INTENCLR) Tamper Enable */
+#define RTC_MODE0_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos  15           /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF      (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
+    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
+    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
+    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
+    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
+    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
+    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
+    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
+    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
+    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
+    uint16_t CMP2:1;           /*!< bit:     10  Compare 2 Interrupt Enable         */
+    uint16_t CMP3:1;           /*!< bit:     11  Compare 3 Interrupt Enable         */
+    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
+    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
+    uint16_t CMP:4;            /*!< bit:  8..11  Compare x Interrupt Enable         */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET   0x08         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_PER0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER0     (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)
+#define RTC_MODE1_INTENCLR_PER1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER1     (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)
+#define RTC_MODE1_INTENCLR_PER2_Pos 2            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER2     (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)
+#define RTC_MODE1_INTENCLR_PER3_Pos 3            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER3     (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)
+#define RTC_MODE1_INTENCLR_PER4_Pos 4            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER4     (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)
+#define RTC_MODE1_INTENCLR_PER5_Pos 5            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER5     (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)
+#define RTC_MODE1_INTENCLR_PER6_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER6     (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)
+#define RTC_MODE1_INTENCLR_PER7_Pos 7            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER7     (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)
+#define RTC_MODE1_INTENCLR_PER_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)
+#define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))
+#define RTC_MODE1_INTENCLR_CMP0_Pos 8            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0     (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 9            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1     (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP2_Pos 10           /**< \brief (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP2     (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)
+#define RTC_MODE1_INTENCLR_CMP3_Pos 11           /**< \brief (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP3     (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos  8            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk  (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_TAMPER_Pos 14           /**< \brief (RTC_MODE1_INTENCLR) Tamper Enable */
+#define RTC_MODE1_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos  15           /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF      (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK     _U_(0xCFFF)  /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
+    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
+    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
+    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
+    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
+    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
+    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
+    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
+    uint16_t ALARM0:1;         /*!< bit:      8  Alarm 0 Interrupt Enable           */
+    uint16_t ALARM1:1;         /*!< bit:      9  Alarm 1 Interrupt Enable           */
+    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
+    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
+    uint16_t ALARM:2;          /*!< bit:  8.. 9  Alarm x Interrupt Enable           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET   0x08         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_PER0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER0     (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)
+#define RTC_MODE2_INTENCLR_PER1_Pos 1            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER1     (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)
+#define RTC_MODE2_INTENCLR_PER2_Pos 2            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER2     (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)
+#define RTC_MODE2_INTENCLR_PER3_Pos 3            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER3     (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)
+#define RTC_MODE2_INTENCLR_PER4_Pos 4            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER4     (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)
+#define RTC_MODE2_INTENCLR_PER5_Pos 5            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER5     (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)
+#define RTC_MODE2_INTENCLR_PER6_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER6     (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)
+#define RTC_MODE2_INTENCLR_PER7_Pos 7            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER7     (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)
+#define RTC_MODE2_INTENCLR_PER_Pos  0            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)
+#define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 8            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0   (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM1_Pos 9            /**< \brief (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM1   (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 8            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_TAMPER_Pos 14           /**< \brief (RTC_MODE2_INTENCLR) Tamper Enable */
+#define RTC_MODE2_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos  15           /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF      (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
+    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
+    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
+    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
+    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
+    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
+    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
+    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
+    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
+    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
+    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
+    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
+    uint16_t CMP:2;            /*!< bit:  8.. 9  Compare x Interrupt Enable         */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET   0x0A         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_PER0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER0     (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)
+#define RTC_MODE0_INTENSET_PER1_Pos 1            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER1     (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)
+#define RTC_MODE0_INTENSET_PER2_Pos 2            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER2     (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)
+#define RTC_MODE0_INTENSET_PER3_Pos 3            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER3     (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)
+#define RTC_MODE0_INTENSET_PER4_Pos 4            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER4     (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)
+#define RTC_MODE0_INTENSET_PER5_Pos 5            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER5     (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)
+#define RTC_MODE0_INTENSET_PER6_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER6     (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)
+#define RTC_MODE0_INTENSET_PER7_Pos 7            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER7     (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)
+#define RTC_MODE0_INTENSET_PER_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */
+#define RTC_MODE0_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)
+#define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))
+#define RTC_MODE0_INTENSET_CMP0_Pos 8            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0     (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP1_Pos 9            /**< \brief (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP1     (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos  8            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk  (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_TAMPER_Pos 14           /**< \brief (RTC_MODE0_INTENSET) Tamper Enable */
+#define RTC_MODE0_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos  15           /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF      (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
+    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
+    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
+    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
+    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
+    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
+    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
+    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
+    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
+    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
+    uint16_t CMP2:1;           /*!< bit:     10  Compare 2 Interrupt Enable         */
+    uint16_t CMP3:1;           /*!< bit:     11  Compare 3 Interrupt Enable         */
+    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
+    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
+    uint16_t CMP:4;            /*!< bit:  8..11  Compare x Interrupt Enable         */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET   0x0A         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_PER0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER0     (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)
+#define RTC_MODE1_INTENSET_PER1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER1     (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)
+#define RTC_MODE1_INTENSET_PER2_Pos 2            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER2     (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)
+#define RTC_MODE1_INTENSET_PER3_Pos 3            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER3     (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)
+#define RTC_MODE1_INTENSET_PER4_Pos 4            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER4     (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)
+#define RTC_MODE1_INTENSET_PER5_Pos 5            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER5     (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)
+#define RTC_MODE1_INTENSET_PER6_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER6     (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)
+#define RTC_MODE1_INTENSET_PER7_Pos 7            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER7     (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)
+#define RTC_MODE1_INTENSET_PER_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */
+#define RTC_MODE1_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)
+#define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))
+#define RTC_MODE1_INTENSET_CMP0_Pos 8            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0     (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 9            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1     (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP2_Pos 10           /**< \brief (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP2     (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)
+#define RTC_MODE1_INTENSET_CMP3_Pos 11           /**< \brief (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP3     (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos  8            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk  (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_TAMPER_Pos 14           /**< \brief (RTC_MODE1_INTENSET) Tamper Enable */
+#define RTC_MODE1_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos  15           /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF      (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK     _U_(0xCFFF)  /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Enable         */
+    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Enable         */
+    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Enable         */
+    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Enable         */
+    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Enable         */
+    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Enable         */
+    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Enable         */
+    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Enable         */
+    uint16_t ALARM0:1;         /*!< bit:      8  Alarm 0 Interrupt Enable           */
+    uint16_t ALARM1:1;         /*!< bit:      9  Alarm 1 Interrupt Enable           */
+    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
+    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Enable         */
+    uint16_t ALARM:2;          /*!< bit:  8.. 9  Alarm x Interrupt Enable           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET   0x0A         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_PER0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */
+#define RTC_MODE2_INTENSET_PER0     (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)
+#define RTC_MODE2_INTENSET_PER1_Pos 1            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */
+#define RTC_MODE2_INTENSET_PER1     (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)
+#define RTC_MODE2_INTENSET_PER2_Pos 2            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */
+#define RTC_MODE2_INTENSET_PER2     (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)
+#define RTC_MODE2_INTENSET_PER3_Pos 3            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */
+#define RTC_MODE2_INTENSET_PER3     (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)
+#define RTC_MODE2_INTENSET_PER4_Pos 4            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */
+#define RTC_MODE2_INTENSET_PER4     (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)
+#define RTC_MODE2_INTENSET_PER5_Pos 5            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */
+#define RTC_MODE2_INTENSET_PER5     (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)
+#define RTC_MODE2_INTENSET_PER6_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */
+#define RTC_MODE2_INTENSET_PER6     (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)
+#define RTC_MODE2_INTENSET_PER7_Pos 7            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */
+#define RTC_MODE2_INTENSET_PER7     (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)
+#define RTC_MODE2_INTENSET_PER_Pos  0            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */
+#define RTC_MODE2_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)
+#define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))
+#define RTC_MODE2_INTENSET_ALARM0_Pos 8            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0   (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM1_Pos 9            /**< \brief (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM1   (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 8            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_TAMPER_Pos 14           /**< \brief (RTC_MODE2_INTENSET) Tamper Enable */
+#define RTC_MODE2_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos  15           /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF      (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0                */
+    __I uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1                */
+    __I uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2                */
+    __I uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3                */
+    __I uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4                */
+    __I uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5                */
+    __I uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6                */
+    __I uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7                */
+    __I uint16_t CMP0:1;           /*!< bit:      8  Compare 0                          */
+    __I uint16_t CMP1:1;           /*!< bit:      9  Compare 1                          */
+    __I uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    __I uint16_t TAMPER:1;         /*!< bit:     14  Tamper                             */
+    __I uint16_t OVF:1;            /*!< bit:     15  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x                */
+    __I uint16_t CMP:2;            /*!< bit:  8.. 9  Compare x                          */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET    0x0C         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_PER0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE0_INTFLAG_PER0      (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)
+#define RTC_MODE0_INTFLAG_PER1_Pos  1            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE0_INTFLAG_PER1      (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)
+#define RTC_MODE0_INTFLAG_PER2_Pos  2            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE0_INTFLAG_PER2      (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)
+#define RTC_MODE0_INTFLAG_PER3_Pos  3            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE0_INTFLAG_PER3      (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)
+#define RTC_MODE0_INTFLAG_PER4_Pos  4            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE0_INTFLAG_PER4      (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)
+#define RTC_MODE0_INTFLAG_PER5_Pos  5            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE0_INTFLAG_PER5      (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)
+#define RTC_MODE0_INTFLAG_PER6_Pos  6            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE0_INTFLAG_PER6      (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)
+#define RTC_MODE0_INTFLAG_PER7_Pos  7            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE0_INTFLAG_PER7      (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)
+#define RTC_MODE0_INTFLAG_PER_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */
+#define RTC_MODE0_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)
+#define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))
+#define RTC_MODE0_INTFLAG_CMP0_Pos  8            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0      (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP1_Pos  9            /**< \brief (RTC_MODE0_INTFLAG) Compare 1 */
+#define RTC_MODE0_INTFLAG_CMP1      (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos   8            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk   (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_TAMPER_Pos 14           /**< \brief (RTC_MODE0_INTFLAG) Tamper */
+#define RTC_MODE0_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos   15           /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF       (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK      _U_(0xC3FF)  /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0                */
+    __I uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1                */
+    __I uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2                */
+    __I uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3                */
+    __I uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4                */
+    __I uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5                */
+    __I uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6                */
+    __I uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7                */
+    __I uint16_t CMP0:1;           /*!< bit:      8  Compare 0                          */
+    __I uint16_t CMP1:1;           /*!< bit:      9  Compare 1                          */
+    __I uint16_t CMP2:1;           /*!< bit:     10  Compare 2                          */
+    __I uint16_t CMP3:1;           /*!< bit:     11  Compare 3                          */
+    __I uint16_t :2;               /*!< bit: 12..13  Reserved                           */
+    __I uint16_t TAMPER:1;         /*!< bit:     14  Tamper                             */
+    __I uint16_t OVF:1;            /*!< bit:     15  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x                */
+    __I uint16_t CMP:4;            /*!< bit:  8..11  Compare x                          */
+    __I uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET    0x0C         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_PER0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE1_INTFLAG_PER0      (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)
+#define RTC_MODE1_INTFLAG_PER1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE1_INTFLAG_PER1      (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)
+#define RTC_MODE1_INTFLAG_PER2_Pos  2            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE1_INTFLAG_PER2      (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)
+#define RTC_MODE1_INTFLAG_PER3_Pos  3            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE1_INTFLAG_PER3      (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)
+#define RTC_MODE1_INTFLAG_PER4_Pos  4            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE1_INTFLAG_PER4      (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)
+#define RTC_MODE1_INTFLAG_PER5_Pos  5            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE1_INTFLAG_PER5      (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)
+#define RTC_MODE1_INTFLAG_PER6_Pos  6            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE1_INTFLAG_PER6      (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)
+#define RTC_MODE1_INTFLAG_PER7_Pos  7            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE1_INTFLAG_PER7      (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)
+#define RTC_MODE1_INTFLAG_PER_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */
+#define RTC_MODE1_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)
+#define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))
+#define RTC_MODE1_INTFLAG_CMP0_Pos  8            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0      (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos  9            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1      (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP2_Pos  10           /**< \brief (RTC_MODE1_INTFLAG) Compare 2 */
+#define RTC_MODE1_INTFLAG_CMP2      (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)
+#define RTC_MODE1_INTFLAG_CMP3_Pos  11           /**< \brief (RTC_MODE1_INTFLAG) Compare 3 */
+#define RTC_MODE1_INTFLAG_CMP3      (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos   8            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk   (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_TAMPER_Pos 14           /**< \brief (RTC_MODE1_INTFLAG) Tamper */
+#define RTC_MODE1_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos   15           /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF       (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK      _U_(0xCFFF)  /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0                */
+    __I uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1                */
+    __I uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2                */
+    __I uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3                */
+    __I uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4                */
+    __I uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5                */
+    __I uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6                */
+    __I uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7                */
+    __I uint16_t ALARM0:1;         /*!< bit:      8  Alarm 0                            */
+    __I uint16_t ALARM1:1;         /*!< bit:      9  Alarm 1                            */
+    __I uint16_t :4;               /*!< bit: 10..13  Reserved                           */
+    __I uint16_t TAMPER:1;         /*!< bit:     14  Tamper                             */
+    __I uint16_t OVF:1;            /*!< bit:     15  Overflow                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x                */
+    __I uint16_t ALARM:2;          /*!< bit:  8.. 9  Alarm x                            */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET    0x0C         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_PER0_Pos  0            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */
+#define RTC_MODE2_INTFLAG_PER0      (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)
+#define RTC_MODE2_INTFLAG_PER1_Pos  1            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */
+#define RTC_MODE2_INTFLAG_PER1      (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)
+#define RTC_MODE2_INTFLAG_PER2_Pos  2            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */
+#define RTC_MODE2_INTFLAG_PER2      (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)
+#define RTC_MODE2_INTFLAG_PER3_Pos  3            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */
+#define RTC_MODE2_INTFLAG_PER3      (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)
+#define RTC_MODE2_INTFLAG_PER4_Pos  4            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */
+#define RTC_MODE2_INTFLAG_PER4      (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)
+#define RTC_MODE2_INTFLAG_PER5_Pos  5            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */
+#define RTC_MODE2_INTFLAG_PER5      (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)
+#define RTC_MODE2_INTFLAG_PER6_Pos  6            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */
+#define RTC_MODE2_INTFLAG_PER6      (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)
+#define RTC_MODE2_INTFLAG_PER7_Pos  7            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */
+#define RTC_MODE2_INTFLAG_PER7      (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)
+#define RTC_MODE2_INTFLAG_PER_Pos   0            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */
+#define RTC_MODE2_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)
+#define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 8            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0    (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM1_Pos 9            /**< \brief (RTC_MODE2_INTFLAG) Alarm 1 */
+#define RTC_MODE2_INTFLAG_ALARM1    (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 8            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_TAMPER_Pos 14           /**< \brief (RTC_MODE2_INTFLAG) Tamper */
+#define RTC_MODE2_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos   15           /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF       (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK      _U_(0xC3FF)  /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET          0x0E         /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN          (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE0 MODE0 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Busy                */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Bit Busy                    */
+    uint32_t FREQCORR:1;       /*!< bit:      2  FREQCORR Register Busy             */
+    uint32_t COUNT:1;          /*!< bit:      3  COUNT Register Busy                */
+    uint32_t :1;               /*!< bit:      4  Reserved                           */
+    uint32_t COMP0:1;          /*!< bit:      5  COMP 0 Register Busy               */
+    uint32_t COMP1:1;          /*!< bit:      6  COMP 1 Register Busy               */
+    uint32_t :8;               /*!< bit:  7..14  Reserved                           */
+    uint32_t COUNTSYNC:1;      /*!< bit:     15  Count Synchronization Enable Bit Busy */
+    uint32_t GP0:1;            /*!< bit:     16  General Purpose 0 Register Busy    */
+    uint32_t GP1:1;            /*!< bit:     17  General Purpose 1 Register Busy    */
+    uint32_t GP2:1;            /*!< bit:     18  General Purpose 2 Register Busy    */
+    uint32_t GP3:1;            /*!< bit:     19  General Purpose 3 Register Busy    */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COMP:2;           /*!< bit:  5.. 6  COMP x Register Busy               */
+    uint32_t :9;               /*!< bit:  7..15  Reserved                           */
+    uint32_t GP:4;             /*!< bit: 16..19  General Purpose x Register Busy    */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_SYNCBUSY_OFFSET   0x10         /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */
+#define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */
+
+#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0            /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */
+#define RTC_MODE0_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1            /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE0_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2            /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3            /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */
+#define RTC_MODE0_SYNCBUSY_COUNT    (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5            /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP0    (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP1_Pos 6            /**< \brief (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP1    (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP_Pos 5            /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */
+#define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)
+#define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy */
+#define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)
+#define RTC_MODE0_SYNCBUSY_GP0_Pos  16           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP0      (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)
+#define RTC_MODE0_SYNCBUSY_GP1_Pos  17           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP1      (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)
+#define RTC_MODE0_SYNCBUSY_GP2_Pos  18           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP2      (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)
+#define RTC_MODE0_SYNCBUSY_GP3_Pos  19           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP3      (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)
+#define RTC_MODE0_SYNCBUSY_GP_Pos   16           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE0_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)
+#define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))
+#define RTC_MODE0_SYNCBUSY_MASK     _U_(0x000F806F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */
+
+/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE1 MODE1 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Bit Busy            */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Bit Busy                    */
+    uint32_t FREQCORR:1;       /*!< bit:      2  FREQCORR Register Busy             */
+    uint32_t COUNT:1;          /*!< bit:      3  COUNT Register Busy                */
+    uint32_t PER:1;            /*!< bit:      4  PER Register Busy                  */
+    uint32_t COMP0:1;          /*!< bit:      5  COMP 0 Register Busy               */
+    uint32_t COMP1:1;          /*!< bit:      6  COMP 1 Register Busy               */
+    uint32_t COMP2:1;          /*!< bit:      7  COMP 2 Register Busy               */
+    uint32_t COMP3:1;          /*!< bit:      8  COMP 3 Register Busy               */
+    uint32_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint32_t COUNTSYNC:1;      /*!< bit:     15  Count Synchronization Enable Bit Busy */
+    uint32_t GP0:1;            /*!< bit:     16  General Purpose 0 Register Busy    */
+    uint32_t GP1:1;            /*!< bit:     17  General Purpose 1 Register Busy    */
+    uint32_t GP2:1;            /*!< bit:     18  General Purpose 2 Register Busy    */
+    uint32_t GP3:1;            /*!< bit:     19  General Purpose 3 Register Busy    */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COMP:4;           /*!< bit:  5.. 8  COMP x Register Busy               */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GP:4;             /*!< bit: 16..19  General Purpose x Register Busy    */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_SYNCBUSY_OFFSET   0x10         /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */
+#define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */
+
+#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0            /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */
+#define RTC_MODE1_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1            /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE1_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2            /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3            /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */
+#define RTC_MODE1_SYNCBUSY_COUNT    (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)
+#define RTC_MODE1_SYNCBUSY_PER_Pos  4            /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */
+#define RTC_MODE1_SYNCBUSY_PER      (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP0    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP1    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP2_Pos 7            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP2    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP3_Pos 8            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP3    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP_Pos 5            /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */
+#define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)
+#define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy */
+#define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)
+#define RTC_MODE1_SYNCBUSY_GP0_Pos  16           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP0      (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)
+#define RTC_MODE1_SYNCBUSY_GP1_Pos  17           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP1      (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)
+#define RTC_MODE1_SYNCBUSY_GP2_Pos  18           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP2      (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)
+#define RTC_MODE1_SYNCBUSY_GP3_Pos  19           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP3      (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)
+#define RTC_MODE1_SYNCBUSY_GP_Pos   16           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE1_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)
+#define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))
+#define RTC_MODE1_SYNCBUSY_MASK     _U_(0x000F81FF) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */
+
+/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE2 MODE2 Synchronization Busy Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Bit Busy            */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Bit Busy                    */
+    uint32_t FREQCORR:1;       /*!< bit:      2  FREQCORR Register Busy             */
+    uint32_t CLOCK:1;          /*!< bit:      3  CLOCK Register Busy                */
+    uint32_t :1;               /*!< bit:      4  Reserved                           */
+    uint32_t ALARM0:1;         /*!< bit:      5  ALARM 0 Register Busy              */
+    uint32_t ALARM1:1;         /*!< bit:      6  ALARM 1 Register Busy              */
+    uint32_t :4;               /*!< bit:  7..10  Reserved                           */
+    uint32_t MASK0:1;          /*!< bit:     11  MASK 0 Register Busy               */
+    uint32_t MASK1:1;          /*!< bit:     12  MASK 1 Register Busy               */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t CLOCKSYNC:1;      /*!< bit:     15  Clock Synchronization Enable Bit Busy */
+    uint32_t GP0:1;            /*!< bit:     16  General Purpose 0 Register Busy    */
+    uint32_t GP1:1;            /*!< bit:     17  General Purpose 1 Register Busy    */
+    uint32_t GP2:1;            /*!< bit:     18  General Purpose 2 Register Busy    */
+    uint32_t GP3:1;            /*!< bit:     19  General Purpose 3 Register Busy    */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t ALARM:2;          /*!< bit:  5.. 6  ALARM x Register Busy              */
+    uint32_t :4;               /*!< bit:  7..10  Reserved                           */
+    uint32_t MASK:2;           /*!< bit: 11..12  MASK x Register Busy               */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t GP:4;             /*!< bit: 16..19  General Purpose x Register Busy    */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_SYNCBUSY_OFFSET   0x10         /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */
+#define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */
+
+#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0            /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */
+#define RTC_MODE2_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)
+#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1            /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */
+#define RTC_MODE2_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)
+#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2            /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */
+#define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)
+#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3            /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */
+#define RTC_MODE2_SYNCBUSY_CLOCK    (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5            /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM0   (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6            /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM1   (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5            /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */
+#define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)
+#define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))
+#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11           /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK0    (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK1_Pos 12           /**< \brief (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK1    (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK_Pos 11           /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */
+#define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)
+#define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15           /**< \brief (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy */
+#define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)
+#define RTC_MODE2_SYNCBUSY_GP0_Pos  16           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP0      (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)
+#define RTC_MODE2_SYNCBUSY_GP1_Pos  17           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP1      (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)
+#define RTC_MODE2_SYNCBUSY_GP2_Pos  18           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP2      (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)
+#define RTC_MODE2_SYNCBUSY_GP3_Pos  19           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP3      (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)
+#define RTC_MODE2_SYNCBUSY_GP_Pos   16           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose x Register Busy */
+#define RTC_MODE2_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)
+#define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))
+#define RTC_MODE2_SYNCBUSY_MASK_    _U_(0x000F986F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W  8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
+    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET         0x14         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE     _U_(0x00)    /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk      (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN           (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK           _U_(0xFF)    /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET      0x18         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE  _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk   (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK        _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET      0x18         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk   (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK        _U_(0xFFFF)  /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET      0x18         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE  _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk  (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk  (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk    (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define   RTC_MODE2_CLOCK_HOUR_AM_Val     _U_(0x0)   /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
+#define   RTC_MODE2_CLOCK_HOUR_PM_Val     _U_(0x10)   /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
+#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk     (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk   (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk    (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK        _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET        0x1C         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE    _U_(0x0000)  /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk       (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK          _U_(0xFFFF)  /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET       0x20         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE   _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk     (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK         _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET       0x20         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE   _U_(0x0000)  /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk     (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK         _U_(0xFFFF)  /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET      0x20         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE  _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk  (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk  (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk    (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define   RTC_MODE2_ALARM_HOUR_AM_Val     _U_(0x0)   /**< \brief (RTC_MODE2_ALARM) Morning hour */
+#define   RTC_MODE2_ALARM_HOUR_PM_Val     _U_(0x10)   /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
+#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk     (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk   (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk    (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK        _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET       0x24         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE   _U_(0x00)    /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk      (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define   RTC_MODE2_MASK_SEL_OFF_Val      _U_(0x0)   /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define   RTC_MODE2_MASK_SEL_SS_Val       _U_(0x1)   /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define   RTC_MODE2_MASK_SEL_MMSS_Val     _U_(0x2)   /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   _U_(0x3)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK         _U_(0x07)    /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GP:32;            /*!< bit:  0..31  General Purpose                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_GP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_GP_OFFSET               0x40         /**< \brief (RTC_GP offset) General Purpose */
+#define RTC_GP_RESETVALUE           _U_(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */
+
+#define RTC_GP_GP_Pos               0            /**< \brief (RTC_GP) General Purpose */
+#define RTC_GP_GP_Msk               (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)
+#define RTC_GP_GP(value)            (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))
+#define RTC_GP_MASK                 _U_(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */
+
+/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN0ACT:2;         /*!< bit:  0.. 1  Tamper Input 0 Action              */
+    uint32_t IN1ACT:2;         /*!< bit:  2.. 3  Tamper Input 1 Action              */
+    uint32_t IN2ACT:2;         /*!< bit:  4.. 5  Tamper Input 2 Action              */
+    uint32_t IN3ACT:2;         /*!< bit:  6.. 7  Tamper Input 3 Action              */
+    uint32_t IN4ACT:2;         /*!< bit:  8.. 9  Tamper Input 4 Action              */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t TAMLVL0:1;        /*!< bit:     16  Tamper Level Select 0              */
+    uint32_t TAMLVL1:1;        /*!< bit:     17  Tamper Level Select 1              */
+    uint32_t TAMLVL2:1;        /*!< bit:     18  Tamper Level Select 2              */
+    uint32_t TAMLVL3:1;        /*!< bit:     19  Tamper Level Select 3              */
+    uint32_t TAMLVL4:1;        /*!< bit:     20  Tamper Level Select 4              */
+    uint32_t :3;               /*!< bit: 21..23  Reserved                           */
+    uint32_t DEBNC0:1;         /*!< bit:     24  Debouncer Enable 0                 */
+    uint32_t DEBNC1:1;         /*!< bit:     25  Debouncer Enable 1                 */
+    uint32_t DEBNC2:1;         /*!< bit:     26  Debouncer Enable 2                 */
+    uint32_t DEBNC3:1;         /*!< bit:     27  Debouncer Enable 3                 */
+    uint32_t DEBNC4:1;         /*!< bit:     28  Debouncer Enable 4                 */
+    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t TAMLVL:5;         /*!< bit: 16..20  Tamper Level Select x              */
+    uint32_t :3;               /*!< bit: 21..23  Reserved                           */
+    uint32_t DEBNC:5;          /*!< bit: 24..28  Debouncer Enable x                 */
+    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_TAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_TAMPCTRL_OFFSET         0x60         /**< \brief (RTC_TAMPCTRL offset) Tamper Control */
+#define RTC_TAMPCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (RTC_TAMPCTRL reset_value) Tamper Control */
+
+#define RTC_TAMPCTRL_IN0ACT_Pos     0            /**< \brief (RTC_TAMPCTRL) Tamper Input 0 Action */
+#define RTC_TAMPCTRL_IN0ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT(value)  (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
+#define   RTC_TAMPCTRL_IN0ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define   RTC_TAMPCTRL_IN0ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define   RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define   RTC_TAMPCTRL_IN0ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN0 to OUT */
+#define RTC_TAMPCTRL_IN0ACT_OFF     (RTC_TAMPCTRL_IN0ACT_OFF_Val   << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_WAKE    (RTC_TAMPCTRL_IN0ACT_WAKE_Val  << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN0ACT_ACTL    (RTC_TAMPCTRL_IN0ACT_ACTL_Val  << RTC_TAMPCTRL_IN0ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_Pos     2            /**< \brief (RTC_TAMPCTRL) Tamper Input 1 Action */
+#define RTC_TAMPCTRL_IN1ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT(value)  (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
+#define   RTC_TAMPCTRL_IN1ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define   RTC_TAMPCTRL_IN1ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define   RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define   RTC_TAMPCTRL_IN1ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN1 to OUT */
+#define RTC_TAMPCTRL_IN1ACT_OFF     (RTC_TAMPCTRL_IN1ACT_OFF_Val   << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_WAKE    (RTC_TAMPCTRL_IN1ACT_WAKE_Val  << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN1ACT_ACTL    (RTC_TAMPCTRL_IN1ACT_ACTL_Val  << RTC_TAMPCTRL_IN1ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_Pos     4            /**< \brief (RTC_TAMPCTRL) Tamper Input 2 Action */
+#define RTC_TAMPCTRL_IN2ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT(value)  (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
+#define   RTC_TAMPCTRL_IN2ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define   RTC_TAMPCTRL_IN2ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define   RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define   RTC_TAMPCTRL_IN2ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN2 to OUT */
+#define RTC_TAMPCTRL_IN2ACT_OFF     (RTC_TAMPCTRL_IN2ACT_OFF_Val   << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_WAKE    (RTC_TAMPCTRL_IN2ACT_WAKE_Val  << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN2ACT_ACTL    (RTC_TAMPCTRL_IN2ACT_ACTL_Val  << RTC_TAMPCTRL_IN2ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_Pos     6            /**< \brief (RTC_TAMPCTRL) Tamper Input 3 Action */
+#define RTC_TAMPCTRL_IN3ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT(value)  (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
+#define   RTC_TAMPCTRL_IN3ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define   RTC_TAMPCTRL_IN3ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define   RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define   RTC_TAMPCTRL_IN3ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN3 to OUT */
+#define RTC_TAMPCTRL_IN3ACT_OFF     (RTC_TAMPCTRL_IN3ACT_OFF_Val   << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_WAKE    (RTC_TAMPCTRL_IN3ACT_WAKE_Val  << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN3ACT_ACTL    (RTC_TAMPCTRL_IN3ACT_ACTL_Val  << RTC_TAMPCTRL_IN3ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_Pos     8            /**< \brief (RTC_TAMPCTRL) Tamper Input 4 Action */
+#define RTC_TAMPCTRL_IN4ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT(value)  (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))
+#define   RTC_TAMPCTRL_IN4ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
+#define   RTC_TAMPCTRL_IN4ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
+#define   RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
+#define   RTC_TAMPCTRL_IN4ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN4 to OUT */
+#define RTC_TAMPCTRL_IN4ACT_OFF     (RTC_TAMPCTRL_IN4ACT_OFF_Val   << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_WAKE    (RTC_TAMPCTRL_IN4ACT_WAKE_Val  << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_IN4ACT_ACTL    (RTC_TAMPCTRL_IN4ACT_ACTL_Val  << RTC_TAMPCTRL_IN4ACT_Pos)
+#define RTC_TAMPCTRL_TAMLVL0_Pos    16           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 0 */
+#define RTC_TAMPCTRL_TAMLVL0        (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)
+#define RTC_TAMPCTRL_TAMLVL1_Pos    17           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 1 */
+#define RTC_TAMPCTRL_TAMLVL1        (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)
+#define RTC_TAMPCTRL_TAMLVL2_Pos    18           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 2 */
+#define RTC_TAMPCTRL_TAMLVL2        (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)
+#define RTC_TAMPCTRL_TAMLVL3_Pos    19           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 3 */
+#define RTC_TAMPCTRL_TAMLVL3        (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)
+#define RTC_TAMPCTRL_TAMLVL4_Pos    20           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 4 */
+#define RTC_TAMPCTRL_TAMLVL4        (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)
+#define RTC_TAMPCTRL_TAMLVL_Pos     16           /**< \brief (RTC_TAMPCTRL) Tamper Level Select x */
+#define RTC_TAMPCTRL_TAMLVL_Msk     (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)
+#define RTC_TAMPCTRL_TAMLVL(value)  (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))
+#define RTC_TAMPCTRL_DEBNC0_Pos     24           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 0 */
+#define RTC_TAMPCTRL_DEBNC0         (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)
+#define RTC_TAMPCTRL_DEBNC1_Pos     25           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 1 */
+#define RTC_TAMPCTRL_DEBNC1         (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)
+#define RTC_TAMPCTRL_DEBNC2_Pos     26           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 2 */
+#define RTC_TAMPCTRL_DEBNC2         (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)
+#define RTC_TAMPCTRL_DEBNC3_Pos     27           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 3 */
+#define RTC_TAMPCTRL_DEBNC3         (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)
+#define RTC_TAMPCTRL_DEBNC4_Pos     28           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 4 */
+#define RTC_TAMPCTRL_DEBNC4         (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)
+#define RTC_TAMPCTRL_DEBNC_Pos      24           /**< \brief (RTC_TAMPCTRL) Debouncer Enable x */
+#define RTC_TAMPCTRL_DEBNC_Msk      (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)
+#define RTC_TAMPCTRL_DEBNC(value)   (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))
+#define RTC_TAMPCTRL_MASK           _U_(0x1F1F03FF) /**< \brief (RTC_TAMPCTRL) MASK Register */
+
+/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE0 MODE0 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Count Timestamp Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE0_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_TIMESTAMP_OFFSET  0x64         /**< \brief (RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp */
+#define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp */
+
+#define RTC_MODE0_TIMESTAMP_COUNT_Pos 0            /**< \brief (RTC_MODE0_TIMESTAMP) Count Timestamp Value */
+#define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)
+#define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
+#define RTC_MODE0_TIMESTAMP_MASK    _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_TIMESTAMP) MASK Register */
+
+/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE1 MODE1 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:16;         /*!< bit:  0..15  Count Timestamp Value              */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE1_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_TIMESTAMP_OFFSET  0x64         /**< \brief (RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp */
+#define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp */
+
+#define RTC_MODE1_TIMESTAMP_COUNT_Pos 0            /**< \brief (RTC_MODE1_TIMESTAMP) Count Timestamp Value */
+#define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)
+#define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
+#define RTC_MODE1_TIMESTAMP_MASK    _U_(0x0000FFFF) /**< \brief (RTC_MODE1_TIMESTAMP) MASK Register */
+
+/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE2 MODE2 Timestamp -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second Timestamp Value             */
+    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute Timestamp Value             */
+    uint32_t HOUR:5;           /*!< bit: 12..16  Hour Timestamp Value               */
+    uint32_t DAY:5;            /*!< bit: 17..21  Day Timestamp Value                */
+    uint32_t MONTH:4;          /*!< bit: 22..25  Month Timestamp Value              */
+    uint32_t YEAR:6;           /*!< bit: 26..31  Year Timestamp Value               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_MODE2_TIMESTAMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_TIMESTAMP_OFFSET  0x64         /**< \brief (RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp */
+#define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp */
+
+#define RTC_MODE2_TIMESTAMP_SECOND_Pos 0            /**< \brief (RTC_MODE2_TIMESTAMP) Second Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)
+#define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
+#define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6            /**< \brief (RTC_MODE2_TIMESTAMP) Minute Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)
+#define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
+#define RTC_MODE2_TIMESTAMP_HOUR_Pos 12           /**< \brief (RTC_MODE2_TIMESTAMP) Hour Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
+#define   RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0)   /**< \brief (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */
+#define   RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10)   /**< \brief (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */
+#define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
+#define RTC_MODE2_TIMESTAMP_DAY_Pos 17           /**< \brief (RTC_MODE2_TIMESTAMP) Day Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)
+#define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
+#define RTC_MODE2_TIMESTAMP_MONTH_Pos 22           /**< \brief (RTC_MODE2_TIMESTAMP) Month Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)
+#define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
+#define RTC_MODE2_TIMESTAMP_YEAR_Pos 26           /**< \brief (RTC_MODE2_TIMESTAMP) Year Timestamp Value */
+#define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)
+#define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
+#define RTC_MODE2_TIMESTAMP_MASK    _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_TIMESTAMP) MASK Register */
+
+/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TAMPID0:1;        /*!< bit:      0  Tamper Input 0 Detected            */
+    uint32_t TAMPID1:1;        /*!< bit:      1  Tamper Input 1 Detected            */
+    uint32_t TAMPID2:1;        /*!< bit:      2  Tamper Input 2 Detected            */
+    uint32_t TAMPID3:1;        /*!< bit:      3  Tamper Input 3 Detected            */
+    uint32_t TAMPID4:1;        /*!< bit:      4  Tamper Input 4 Detected            */
+    uint32_t :26;              /*!< bit:  5..30  Reserved                           */
+    uint32_t TAMPEVT:1;        /*!< bit:     31  Tamper Event Detected              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t TAMPID:5;         /*!< bit:  0.. 4  Tamper Input x Detected            */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_TAMPID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_TAMPID_OFFSET           0x68         /**< \brief (RTC_TAMPID offset) Tamper ID */
+#define RTC_TAMPID_RESETVALUE       _U_(0x00000000) /**< \brief (RTC_TAMPID reset_value) Tamper ID */
+
+#define RTC_TAMPID_TAMPID0_Pos      0            /**< \brief (RTC_TAMPID) Tamper Input 0 Detected */
+#define RTC_TAMPID_TAMPID0          (_U_(1) << RTC_TAMPID_TAMPID0_Pos)
+#define RTC_TAMPID_TAMPID1_Pos      1            /**< \brief (RTC_TAMPID) Tamper Input 1 Detected */
+#define RTC_TAMPID_TAMPID1          (_U_(1) << RTC_TAMPID_TAMPID1_Pos)
+#define RTC_TAMPID_TAMPID2_Pos      2            /**< \brief (RTC_TAMPID) Tamper Input 2 Detected */
+#define RTC_TAMPID_TAMPID2          (_U_(1) << RTC_TAMPID_TAMPID2_Pos)
+#define RTC_TAMPID_TAMPID3_Pos      3            /**< \brief (RTC_TAMPID) Tamper Input 3 Detected */
+#define RTC_TAMPID_TAMPID3          (_U_(1) << RTC_TAMPID_TAMPID3_Pos)
+#define RTC_TAMPID_TAMPID4_Pos      4            /**< \brief (RTC_TAMPID) Tamper Input 4 Detected */
+#define RTC_TAMPID_TAMPID4          (_U_(1) << RTC_TAMPID_TAMPID4_Pos)
+#define RTC_TAMPID_TAMPID_Pos       0            /**< \brief (RTC_TAMPID) Tamper Input x Detected */
+#define RTC_TAMPID_TAMPID_Msk       (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)
+#define RTC_TAMPID_TAMPID(value)    (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))
+#define RTC_TAMPID_TAMPEVT_Pos      31           /**< \brief (RTC_TAMPID) Tamper Event Detected */
+#define RTC_TAMPID_TAMPEVT          (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)
+#define RTC_TAMPID_MASK             _U_(0x8000001F) /**< \brief (RTC_TAMPID) MASK Register */
+
+/* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BKUP:32;          /*!< bit:  0..31  Backup                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} RTC_BKUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_BKUP_OFFSET             0x80         /**< \brief (RTC_BKUP offset) Backup */
+#define RTC_BKUP_RESETVALUE         _U_(0x00000000) /**< \brief (RTC_BKUP reset_value) Backup */
+
+#define RTC_BKUP_BKUP_Pos           0            /**< \brief (RTC_BKUP) Backup */
+#define RTC_BKUP_BKUP_Msk           (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)
+#define RTC_BKUP_BKUP(value)        (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))
+#define RTC_BKUP_MASK               _U_(0xFFFFFFFF) /**< \brief (RTC_BKUP) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
+       RoReg8                    Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+  __IO RTC_MODE0_CTRLA_Type      CTRLA;       /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
+  __IO RTC_MODE0_CTRLB_Type      CTRLB;       /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
+  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */
+  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */
+  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */
+  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0E (R/W  8) Debug Control */
+       RoReg8                    Reserved1[0x1];
+  __I  RTC_MODE0_SYNCBUSY_Type   SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) MODE0 Synchronization Busy Status */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x14 (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */
+       RoReg8                    Reserved3[0x4];
+  __IO RTC_MODE0_COMP_Type       COMP[2];     /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */
+       RoReg8                    Reserved4[0x18];
+  __IO RTC_GP_Type               GP[4];       /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+       RoReg8                    Reserved5[0x10];
+  __IO RTC_TAMPCTRL_Type         TAMPCTRL;    /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+  __I  RTC_MODE0_TIMESTAMP_Type  TIMESTAMP;   /**< \brief Offset: 0x64 (R/  32) MODE0 Timestamp */
+  __IO RTC_TAMPID_Type           TAMPID;      /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+       RoReg8                    Reserved6[0x14];
+  __IO RTC_BKUP_Type             BKUP[8];     /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+  __IO RTC_MODE1_CTRLA_Type      CTRLA;       /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */
+  __IO RTC_MODE1_CTRLB_Type      CTRLB;       /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */
+  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */
+  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */
+  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */
+  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0E (R/W  8) Debug Control */
+       RoReg8                    Reserved1[0x1];
+  __I  RTC_MODE1_SYNCBUSY_Type   SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) MODE1 Synchronization Busy Status */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x14 (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */
+       RoReg8                    Reserved3[0x2];
+  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */
+       RoReg8                    Reserved4[0x2];
+  __IO RTC_MODE1_COMP_Type       COMP[4];     /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */
+       RoReg8                    Reserved5[0x18];
+  __IO RTC_GP_Type               GP[4];       /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+       RoReg8                    Reserved6[0x10];
+  __IO RTC_TAMPCTRL_Type         TAMPCTRL;    /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+  __I  RTC_MODE1_TIMESTAMP_Type  TIMESTAMP;   /**< \brief Offset: 0x64 (R/  32) MODE1 Timestamp */
+  __IO RTC_TAMPID_Type           TAMPID;      /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+       RoReg8                    Reserved7[0x14];
+  __IO RTC_BKUP_Type             BKUP[8];     /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+  __IO RTC_MODE2_CTRLA_Type      CTRLA;       /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */
+  __IO RTC_MODE2_CTRLB_Type      CTRLB;       /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */
+  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */
+  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */
+  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */
+  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */
+  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0E (R/W  8) Debug Control */
+       RoReg8                    Reserved1[0x1];
+  __I  RTC_MODE2_SYNCBUSY_Type   SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) MODE2 Synchronization Busy Status */
+  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x14 (R/W  8) Frequency Correction */
+       RoReg8                    Reserved2[0x3];
+  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */
+       RoReg8                    Reserved3[0x4];
+       RtcMode2Alarm             Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */
+       RoReg8                    Reserved4[0x10];
+  __IO RTC_GP_Type               GP[4];       /**< \brief Offset: 0x40 (R/W 32) General Purpose */
+       RoReg8                    Reserved5[0x10];
+  __IO RTC_TAMPCTRL_Type         TAMPCTRL;    /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
+  __I  RTC_MODE2_TIMESTAMP_Type  TIMESTAMP;   /**< \brief Offset: 0x64 (R/  32) MODE2 Timestamp */
+  __IO RTC_TAMPID_Type           TAMPID;      /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
+       RoReg8                    Reserved6[0x14];
+  __IO RTC_BKUP_Type             BKUP[8];     /**< \brief Offset: 0x80 (R/W 32) Backup */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_RTC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/sdhc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/sdhc.h
new file mode 100644
index 000000000..b1a230405
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/sdhc.h	
@@ -0,0 +1,2599 @@
+/**
+ * \file
+ *
+ * \brief Component description for SDHC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SDHC_COMPONENT_
+#define _SAME53_SDHC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SDHC */
+/* ========================================================================== */
+/** \addtogroup SAME53_SDHC SD/MMC Host Controller */
+/*@{*/
+
+#define SDHC_U2011
+#define REV_SDHC                    0x183
+
+/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // CMD23 mode
+    uint32_t ARG2:32;          /*!< bit:  0..31  Argument 2                         */
+  } CMD23;                     /*!< Structure used for CMD23                        */
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  SDMA System Address                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_SSAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SSAR_OFFSET            0x000        /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */
+#define SDHC_SSAR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */
+
+// CMD23 mode
+#define SDHC_SSAR_CMD23_ARG2_Pos    0            /**< \brief (SDHC_SSAR_CMD23) Argument 2 */
+#define SDHC_SSAR_CMD23_ARG2_Msk    (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)
+#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))
+#define SDHC_SSAR_CMD23_MASK        _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */
+
+#define SDHC_SSAR_ADDR_Pos          0            /**< \brief (SDHC_SSAR) SDMA System Address */
+#define SDHC_SSAR_ADDR_Msk          (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)
+#define SDHC_SSAR_ADDR(value)       (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))
+#define SDHC_SSAR_MASK              _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */
+
+/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BLOCKSIZE:10;     /*!< bit:  0.. 9  Transfer Block Size                */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t BOUNDARY:3;       /*!< bit: 12..14  SDMA Buffer Boundary               */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_BSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BSR_OFFSET             0x004        /**< \brief (SDHC_BSR offset) Block Size */
+#define SDHC_BSR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_BSR reset_value) Block Size */
+
+#define SDHC_BSR_BLOCKSIZE_Pos      0            /**< \brief (SDHC_BSR) Transfer Block Size */
+#define SDHC_BSR_BLOCKSIZE_Msk      (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)
+#define SDHC_BSR_BLOCKSIZE(value)   (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))
+#define SDHC_BSR_BOUNDARY_Pos       12           /**< \brief (SDHC_BSR) SDMA Buffer Boundary */
+#define SDHC_BSR_BOUNDARY_Msk       (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY(value)    (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))
+#define   SDHC_BSR_BOUNDARY_4K_Val        _U_(0x0)   /**< \brief (SDHC_BSR) 4k bytes */
+#define   SDHC_BSR_BOUNDARY_8K_Val        _U_(0x1)   /**< \brief (SDHC_BSR) 8k bytes */
+#define   SDHC_BSR_BOUNDARY_16K_Val       _U_(0x2)   /**< \brief (SDHC_BSR) 16k bytes */
+#define   SDHC_BSR_BOUNDARY_32K_Val       _U_(0x3)   /**< \brief (SDHC_BSR) 32k bytes */
+#define   SDHC_BSR_BOUNDARY_64K_Val       _U_(0x4)   /**< \brief (SDHC_BSR) 64k bytes */
+#define   SDHC_BSR_BOUNDARY_128K_Val      _U_(0x5)   /**< \brief (SDHC_BSR) 128k bytes */
+#define   SDHC_BSR_BOUNDARY_256K_Val      _U_(0x6)   /**< \brief (SDHC_BSR) 256k bytes */
+#define   SDHC_BSR_BOUNDARY_512K_Val      _U_(0x7)   /**< \brief (SDHC_BSR) 512k bytes */
+#define SDHC_BSR_BOUNDARY_4K        (SDHC_BSR_BOUNDARY_4K_Val      << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_8K        (SDHC_BSR_BOUNDARY_8K_Val      << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_16K       (SDHC_BSR_BOUNDARY_16K_Val     << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_32K       (SDHC_BSR_BOUNDARY_32K_Val     << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_64K       (SDHC_BSR_BOUNDARY_64K_Val     << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_128K      (SDHC_BSR_BOUNDARY_128K_Val    << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_256K      (SDHC_BSR_BOUNDARY_256K_Val    << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_BOUNDARY_512K      (SDHC_BSR_BOUNDARY_512K_Val    << SDHC_BSR_BOUNDARY_Pos)
+#define SDHC_BSR_MASK               _U_(0x73FF)  /**< \brief (SDHC_BSR) MASK Register */
+
+/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BCNT:16;          /*!< bit:  0..15  Blocks Count for Current Transfer  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_BCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BCR_OFFSET             0x006        /**< \brief (SDHC_BCR offset) Block Count */
+#define SDHC_BCR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_BCR reset_value) Block Count */
+
+#define SDHC_BCR_BCNT_Pos           0            /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */
+#define SDHC_BCR_BCNT_Msk           (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)
+#define SDHC_BCR_BCNT(value)        (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))
+#define SDHC_BCR_MASK               _U_(0xFFFF)  /**< \brief (SDHC_BCR) MASK Register */
+
+/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ARG:32;           /*!< bit:  0..31  Argument 1                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_ARG1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ARG1R_OFFSET           0x008        /**< \brief (SDHC_ARG1R offset) Argument 1 */
+#define SDHC_ARG1R_RESETVALUE       _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */
+
+#define SDHC_ARG1R_ARG_Pos          0            /**< \brief (SDHC_ARG1R) Argument 1 */
+#define SDHC_ARG1R_ARG_Msk          (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)
+#define SDHC_ARG1R_ARG(value)       (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))
+#define SDHC_ARG1R_MASK             _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */
+
+/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DMAEN:1;          /*!< bit:      0  DMA Enable                         */
+    uint16_t BCEN:1;           /*!< bit:      1  Block Count Enable                 */
+    uint16_t ACMDEN:2;         /*!< bit:  2.. 3  Auto Command Enable                */
+    uint16_t DTDSEL:1;         /*!< bit:      4  Data Transfer Direction Selection  */
+    uint16_t MSBSEL:1;         /*!< bit:      5  Multi/Single Block Selection       */
+    uint16_t :10;              /*!< bit:  6..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_TMR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_TMR_OFFSET             0x00C        /**< \brief (SDHC_TMR offset) Transfer Mode */
+#define SDHC_TMR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_TMR reset_value) Transfer Mode */
+
+#define SDHC_TMR_DMAEN_Pos          0            /**< \brief (SDHC_TMR) DMA Enable */
+#define SDHC_TMR_DMAEN              (_U_(0x1) << SDHC_TMR_DMAEN_Pos)
+#define   SDHC_TMR_DMAEN_DISABLE_Val      _U_(0x0)   /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */
+#define   SDHC_TMR_DMAEN_ENABLE_Val       _U_(0x1)   /**< \brief (SDHC_TMR) DMA data transfer */
+#define SDHC_TMR_DMAEN_DISABLE      (SDHC_TMR_DMAEN_DISABLE_Val    << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_DMAEN_ENABLE       (SDHC_TMR_DMAEN_ENABLE_Val     << SDHC_TMR_DMAEN_Pos)
+#define SDHC_TMR_BCEN_Pos           1            /**< \brief (SDHC_TMR) Block Count Enable */
+#define SDHC_TMR_BCEN               (_U_(0x1) << SDHC_TMR_BCEN_Pos)
+#define   SDHC_TMR_BCEN_DISABLE_Val       _U_(0x0)   /**< \brief (SDHC_TMR) Disable */
+#define   SDHC_TMR_BCEN_ENABLE_Val        _U_(0x1)   /**< \brief (SDHC_TMR) Enable */
+#define SDHC_TMR_BCEN_DISABLE       (SDHC_TMR_BCEN_DISABLE_Val     << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_BCEN_ENABLE        (SDHC_TMR_BCEN_ENABLE_Val      << SDHC_TMR_BCEN_Pos)
+#define SDHC_TMR_ACMDEN_Pos         2            /**< \brief (SDHC_TMR) Auto Command Enable */
+#define SDHC_TMR_ACMDEN_Msk         (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN(value)      (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))
+#define   SDHC_TMR_ACMDEN_DISABLED_Val    _U_(0x0)   /**< \brief (SDHC_TMR) Auto Command Disabled */
+#define   SDHC_TMR_ACMDEN_CMD12_Val       _U_(0x1)   /**< \brief (SDHC_TMR) Auto CMD12 Enable */
+#define   SDHC_TMR_ACMDEN_CMD23_Val       _U_(0x2)   /**< \brief (SDHC_TMR) Auto CMD23 Enable */
+#define   SDHC_TMR_ACMDEN_3_Val           _U_(0x3)   /**< \brief (SDHC_TMR) Reserved */
+#define SDHC_TMR_ACMDEN_DISABLED    (SDHC_TMR_ACMDEN_DISABLED_Val  << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_CMD12       (SDHC_TMR_ACMDEN_CMD12_Val     << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_CMD23       (SDHC_TMR_ACMDEN_CMD23_Val     << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_ACMDEN_3           (SDHC_TMR_ACMDEN_3_Val         << SDHC_TMR_ACMDEN_Pos)
+#define SDHC_TMR_DTDSEL_Pos         4            /**< \brief (SDHC_TMR) Data Transfer Direction Selection */
+#define SDHC_TMR_DTDSEL             (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)
+#define   SDHC_TMR_DTDSEL_WRITE_Val       _U_(0x0)   /**< \brief (SDHC_TMR) Write (Host to Card) */
+#define   SDHC_TMR_DTDSEL_READ_Val        _U_(0x1)   /**< \brief (SDHC_TMR) Read (Card to Host) */
+#define SDHC_TMR_DTDSEL_WRITE       (SDHC_TMR_DTDSEL_WRITE_Val     << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_DTDSEL_READ        (SDHC_TMR_DTDSEL_READ_Val      << SDHC_TMR_DTDSEL_Pos)
+#define SDHC_TMR_MSBSEL_Pos         5            /**< \brief (SDHC_TMR) Multi/Single Block Selection */
+#define SDHC_TMR_MSBSEL             (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)
+#define   SDHC_TMR_MSBSEL_SINGLE_Val      _U_(0x0)   /**< \brief (SDHC_TMR) Single Block */
+#define   SDHC_TMR_MSBSEL_MULTIPLE_Val    _U_(0x1)   /**< \brief (SDHC_TMR) Multiple Block */
+#define SDHC_TMR_MSBSEL_SINGLE      (SDHC_TMR_MSBSEL_SINGLE_Val    << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MSBSEL_MULTIPLE    (SDHC_TMR_MSBSEL_MULTIPLE_Val  << SDHC_TMR_MSBSEL_Pos)
+#define SDHC_TMR_MASK               _U_(0x003F)  /**< \brief (SDHC_TMR) MASK Register */
+
+/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESPTYP:2;        /*!< bit:  0.. 1  Response Type                      */
+    uint16_t :1;               /*!< bit:      2  Reserved                           */
+    uint16_t CMDCCEN:1;        /*!< bit:      3  Command CRC Check Enable           */
+    uint16_t CMDICEN:1;        /*!< bit:      4  Command Index Check Enable         */
+    uint16_t DPSEL:1;          /*!< bit:      5  Data Present Select                */
+    uint16_t CMDTYP:2;         /*!< bit:  6.. 7  Command Type                       */
+    uint16_t CMDIDX:6;         /*!< bit:  8..13  Command Index                      */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_CR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CR_OFFSET              0x00E        /**< \brief (SDHC_CR offset) Command */
+#define SDHC_CR_RESETVALUE          _U_(0x0000)  /**< \brief (SDHC_CR reset_value) Command */
+
+#define SDHC_CR_RESPTYP_Pos         0            /**< \brief (SDHC_CR) Response Type */
+#define SDHC_CR_RESPTYP_Msk         (_U_(0x3) << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP(value)      (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))
+#define   SDHC_CR_RESPTYP_NONE_Val        _U_(0x0)   /**< \brief (SDHC_CR) No response */
+#define   SDHC_CR_RESPTYP_136_BIT_Val     _U_(0x1)   /**< \brief (SDHC_CR) 136-bit response */
+#define   SDHC_CR_RESPTYP_48_BIT_Val      _U_(0x2)   /**< \brief (SDHC_CR) 48-bit response */
+#define   SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3)   /**< \brief (SDHC_CR) 48-bit response check busy after response */
+#define SDHC_CR_RESPTYP_NONE        (SDHC_CR_RESPTYP_NONE_Val      << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_136_BIT     (SDHC_CR_RESPTYP_136_BIT_Val   << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_48_BIT      (SDHC_CR_RESPTYP_48_BIT_Val    << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)
+#define SDHC_CR_CMDCCEN_Pos         3            /**< \brief (SDHC_CR) Command CRC Check Enable */
+#define SDHC_CR_CMDCCEN             (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)
+#define   SDHC_CR_CMDCCEN_DISABLE_Val     _U_(0x0)   /**< \brief (SDHC_CR) Disable */
+#define   SDHC_CR_CMDCCEN_ENABLE_Val      _U_(0x1)   /**< \brief (SDHC_CR) Enable */
+#define SDHC_CR_CMDCCEN_DISABLE     (SDHC_CR_CMDCCEN_DISABLE_Val   << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDCCEN_ENABLE      (SDHC_CR_CMDCCEN_ENABLE_Val    << SDHC_CR_CMDCCEN_Pos)
+#define SDHC_CR_CMDICEN_Pos         4            /**< \brief (SDHC_CR) Command Index Check Enable */
+#define SDHC_CR_CMDICEN             (_U_(0x1) << SDHC_CR_CMDICEN_Pos)
+#define   SDHC_CR_CMDICEN_DISABLE_Val     _U_(0x0)   /**< \brief (SDHC_CR) Disable */
+#define   SDHC_CR_CMDICEN_ENABLE_Val      _U_(0x1)   /**< \brief (SDHC_CR) Enable */
+#define SDHC_CR_CMDICEN_DISABLE     (SDHC_CR_CMDICEN_DISABLE_Val   << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_CMDICEN_ENABLE      (SDHC_CR_CMDICEN_ENABLE_Val    << SDHC_CR_CMDICEN_Pos)
+#define SDHC_CR_DPSEL_Pos           5            /**< \brief (SDHC_CR) Data Present Select */
+#define SDHC_CR_DPSEL               (_U_(0x1) << SDHC_CR_DPSEL_Pos)
+#define   SDHC_CR_DPSEL_NO_DATA_Val       _U_(0x0)   /**< \brief (SDHC_CR) No Data Present */
+#define   SDHC_CR_DPSEL_DATA_Val          _U_(0x1)   /**< \brief (SDHC_CR) Data Present */
+#define SDHC_CR_DPSEL_NO_DATA       (SDHC_CR_DPSEL_NO_DATA_Val     << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_DPSEL_DATA          (SDHC_CR_DPSEL_DATA_Val        << SDHC_CR_DPSEL_Pos)
+#define SDHC_CR_CMDTYP_Pos          6            /**< \brief (SDHC_CR) Command Type */
+#define SDHC_CR_CMDTYP_Msk          (_U_(0x3) << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP(value)       (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))
+#define   SDHC_CR_CMDTYP_NORMAL_Val       _U_(0x0)   /**< \brief (SDHC_CR) Other commands */
+#define   SDHC_CR_CMDTYP_SUSPEND_Val      _U_(0x1)   /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */
+#define   SDHC_CR_CMDTYP_RESUME_Val       _U_(0x2)   /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */
+#define   SDHC_CR_CMDTYP_ABORT_Val        _U_(0x3)   /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */
+#define SDHC_CR_CMDTYP_NORMAL       (SDHC_CR_CMDTYP_NORMAL_Val     << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_SUSPEND      (SDHC_CR_CMDTYP_SUSPEND_Val    << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_RESUME       (SDHC_CR_CMDTYP_RESUME_Val     << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDTYP_ABORT        (SDHC_CR_CMDTYP_ABORT_Val      << SDHC_CR_CMDTYP_Pos)
+#define SDHC_CR_CMDIDX_Pos          8            /**< \brief (SDHC_CR) Command Index */
+#define SDHC_CR_CMDIDX_Msk          (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)
+#define SDHC_CR_CMDIDX(value)       (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))
+#define SDHC_CR_MASK                _U_(0x3FFB)  /**< \brief (SDHC_CR) MASK Register */
+
+/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/  32) Response -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CMDRESP:32;       /*!< bit:  0..31  Command Response                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_RR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_RR_OFFSET              0x010        /**< \brief (SDHC_RR offset) Response */
+#define SDHC_RR_RESETVALUE          _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */
+
+#define SDHC_RR_CMDRESP_Pos         0            /**< \brief (SDHC_RR) Command Response */
+#define SDHC_RR_CMDRESP_Msk         (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)
+#define SDHC_RR_CMDRESP(value)      (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))
+#define SDHC_RR_MASK                _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */
+
+/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BUFDATA:32;       /*!< bit:  0..31  Buffer Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_BDPR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BDPR_OFFSET            0x020        /**< \brief (SDHC_BDPR offset) Buffer Data Port */
+#define SDHC_BDPR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */
+
+#define SDHC_BDPR_BUFDATA_Pos       0            /**< \brief (SDHC_BDPR) Buffer Data */
+#define SDHC_BDPR_BUFDATA_Msk       (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)
+#define SDHC_BDPR_BUFDATA(value)    (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))
+#define SDHC_BDPR_MASK              _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */
+
+/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/  32) Present State -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CMDINHC:1;        /*!< bit:      0  Command Inhibit (CMD)              */
+    uint32_t CMDINHD:1;        /*!< bit:      1  Command Inhibit (DAT)              */
+    uint32_t DLACT:1;          /*!< bit:      2  DAT Line Active                    */
+    uint32_t RTREQ:1;          /*!< bit:      3  Re-Tuning Request                  */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t WTACT:1;          /*!< bit:      8  Write Transfer Active              */
+    uint32_t RTACT:1;          /*!< bit:      9  Read Transfer Active               */
+    uint32_t BUFWREN:1;        /*!< bit:     10  Buffer Write Enable                */
+    uint32_t BUFRDEN:1;        /*!< bit:     11  Buffer Read Enable                 */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t CARDINS:1;        /*!< bit:     16  Card Inserted                      */
+    uint32_t CARDSS:1;         /*!< bit:     17  Card State Stable                  */
+    uint32_t CARDDPL:1;        /*!< bit:     18  Card Detect Pin Level              */
+    uint32_t WRPPL:1;          /*!< bit:     19  Write Protect Pin Level            */
+    uint32_t DATLL:4;          /*!< bit: 20..23  DAT[3:0] Line Level                */
+    uint32_t CMDLL:1;          /*!< bit:     24  CMD Line Level                     */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_PSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PSR_OFFSET             0x024        /**< \brief (SDHC_PSR offset) Present State */
+#define SDHC_PSR_RESETVALUE         _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */
+
+#define SDHC_PSR_CMDINHC_Pos        0            /**< \brief (SDHC_PSR) Command Inhibit (CMD) */
+#define SDHC_PSR_CMDINHC            (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)
+#define   SDHC_PSR_CMDINHC_CAN_Val        _U_(0x0)   /**< \brief (SDHC_PSR) Can issue command using only CMD line */
+#define   SDHC_PSR_CMDINHC_CANNOT_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Cannot issue command */
+#define SDHC_PSR_CMDINHC_CAN        (SDHC_PSR_CMDINHC_CAN_Val      << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHC_CANNOT     (SDHC_PSR_CMDINHC_CANNOT_Val   << SDHC_PSR_CMDINHC_Pos)
+#define SDHC_PSR_CMDINHD_Pos        1            /**< \brief (SDHC_PSR) Command Inhibit (DAT) */
+#define SDHC_PSR_CMDINHD            (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)
+#define   SDHC_PSR_CMDINHD_CAN_Val        _U_(0x0)   /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */
+#define   SDHC_PSR_CMDINHD_CANNOT_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */
+#define SDHC_PSR_CMDINHD_CAN        (SDHC_PSR_CMDINHD_CAN_Val      << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_CMDINHD_CANNOT     (SDHC_PSR_CMDINHD_CANNOT_Val   << SDHC_PSR_CMDINHD_Pos)
+#define SDHC_PSR_DLACT_Pos          2            /**< \brief (SDHC_PSR) DAT Line Active */
+#define SDHC_PSR_DLACT              (_U_(0x1) << SDHC_PSR_DLACT_Pos)
+#define   SDHC_PSR_DLACT_INACTIVE_Val     _U_(0x0)   /**< \brief (SDHC_PSR) DAT Line Inactive */
+#define   SDHC_PSR_DLACT_ACTIVE_Val       _U_(0x1)   /**< \brief (SDHC_PSR) DAT Line Active */
+#define SDHC_PSR_DLACT_INACTIVE     (SDHC_PSR_DLACT_INACTIVE_Val   << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_DLACT_ACTIVE       (SDHC_PSR_DLACT_ACTIVE_Val     << SDHC_PSR_DLACT_Pos)
+#define SDHC_PSR_RTREQ_Pos          3            /**< \brief (SDHC_PSR) Re-Tuning Request */
+#define SDHC_PSR_RTREQ              (_U_(0x1) << SDHC_PSR_RTREQ_Pos)
+#define   SDHC_PSR_RTREQ_OK_Val           _U_(0x0)   /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */
+#define   SDHC_PSR_RTREQ_REQUIRED_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */
+#define SDHC_PSR_RTREQ_OK           (SDHC_PSR_RTREQ_OK_Val         << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_RTREQ_REQUIRED     (SDHC_PSR_RTREQ_REQUIRED_Val   << SDHC_PSR_RTREQ_Pos)
+#define SDHC_PSR_WTACT_Pos          8            /**< \brief (SDHC_PSR) Write Transfer Active */
+#define SDHC_PSR_WTACT              (_U_(0x1) << SDHC_PSR_WTACT_Pos)
+#define   SDHC_PSR_WTACT_NO_Val           _U_(0x0)   /**< \brief (SDHC_PSR) No valid data */
+#define   SDHC_PSR_WTACT_YES_Val          _U_(0x1)   /**< \brief (SDHC_PSR) Transferring data */
+#define SDHC_PSR_WTACT_NO           (SDHC_PSR_WTACT_NO_Val         << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_WTACT_YES          (SDHC_PSR_WTACT_YES_Val        << SDHC_PSR_WTACT_Pos)
+#define SDHC_PSR_RTACT_Pos          9            /**< \brief (SDHC_PSR) Read Transfer Active */
+#define SDHC_PSR_RTACT              (_U_(0x1) << SDHC_PSR_RTACT_Pos)
+#define   SDHC_PSR_RTACT_NO_Val           _U_(0x0)   /**< \brief (SDHC_PSR) No valid data */
+#define   SDHC_PSR_RTACT_YES_Val          _U_(0x1)   /**< \brief (SDHC_PSR) Transferring data */
+#define SDHC_PSR_RTACT_NO           (SDHC_PSR_RTACT_NO_Val         << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_RTACT_YES          (SDHC_PSR_RTACT_YES_Val        << SDHC_PSR_RTACT_Pos)
+#define SDHC_PSR_BUFWREN_Pos        10           /**< \brief (SDHC_PSR) Buffer Write Enable */
+#define SDHC_PSR_BUFWREN            (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)
+#define   SDHC_PSR_BUFWREN_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_PSR) Write disable */
+#define   SDHC_PSR_BUFWREN_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Write enable */
+#define SDHC_PSR_BUFWREN_DISABLE    (SDHC_PSR_BUFWREN_DISABLE_Val  << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFWREN_ENABLE     (SDHC_PSR_BUFWREN_ENABLE_Val   << SDHC_PSR_BUFWREN_Pos)
+#define SDHC_PSR_BUFRDEN_Pos        11           /**< \brief (SDHC_PSR) Buffer Read Enable */
+#define SDHC_PSR_BUFRDEN            (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)
+#define   SDHC_PSR_BUFRDEN_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_PSR) Read disable */
+#define   SDHC_PSR_BUFRDEN_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Read enable */
+#define SDHC_PSR_BUFRDEN_DISABLE    (SDHC_PSR_BUFRDEN_DISABLE_Val  << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_BUFRDEN_ENABLE     (SDHC_PSR_BUFRDEN_ENABLE_Val   << SDHC_PSR_BUFRDEN_Pos)
+#define SDHC_PSR_CARDINS_Pos        16           /**< \brief (SDHC_PSR) Card Inserted */
+#define SDHC_PSR_CARDINS            (_U_(0x1) << SDHC_PSR_CARDINS_Pos)
+#define   SDHC_PSR_CARDINS_NO_Val         _U_(0x0)   /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */
+#define   SDHC_PSR_CARDINS_YES_Val        _U_(0x1)   /**< \brief (SDHC_PSR) Card inserted */
+#define SDHC_PSR_CARDINS_NO         (SDHC_PSR_CARDINS_NO_Val       << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDINS_YES        (SDHC_PSR_CARDINS_YES_Val      << SDHC_PSR_CARDINS_Pos)
+#define SDHC_PSR_CARDSS_Pos         17           /**< \brief (SDHC_PSR) Card State Stable */
+#define SDHC_PSR_CARDSS             (_U_(0x1) << SDHC_PSR_CARDSS_Pos)
+#define   SDHC_PSR_CARDSS_NO_Val          _U_(0x0)   /**< \brief (SDHC_PSR) Reset or Debouncing */
+#define   SDHC_PSR_CARDSS_YES_Val         _U_(0x1)   /**< \brief (SDHC_PSR) No Card or Insered */
+#define SDHC_PSR_CARDSS_NO          (SDHC_PSR_CARDSS_NO_Val        << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDSS_YES         (SDHC_PSR_CARDSS_YES_Val       << SDHC_PSR_CARDSS_Pos)
+#define SDHC_PSR_CARDDPL_Pos        18           /**< \brief (SDHC_PSR) Card Detect Pin Level */
+#define SDHC_PSR_CARDDPL            (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)
+#define   SDHC_PSR_CARDDPL_NO_Val         _U_(0x0)   /**< \brief (SDHC_PSR) No card present (SDCD#=1) */
+#define   SDHC_PSR_CARDDPL_YES_Val        _U_(0x1)   /**< \brief (SDHC_PSR) Card present (SDCD#=0) */
+#define SDHC_PSR_CARDDPL_NO         (SDHC_PSR_CARDDPL_NO_Val       << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_CARDDPL_YES        (SDHC_PSR_CARDDPL_YES_Val      << SDHC_PSR_CARDDPL_Pos)
+#define SDHC_PSR_WRPPL_Pos          19           /**< \brief (SDHC_PSR) Write Protect Pin Level */
+#define SDHC_PSR_WRPPL              (_U_(0x1) << SDHC_PSR_WRPPL_Pos)
+#define   SDHC_PSR_WRPPL_PROTECTED_Val    _U_(0x0)   /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */
+#define   SDHC_PSR_WRPPL_ENABLED_Val      _U_(0x1)   /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */
+#define SDHC_PSR_WRPPL_PROTECTED    (SDHC_PSR_WRPPL_PROTECTED_Val  << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_WRPPL_ENABLED      (SDHC_PSR_WRPPL_ENABLED_Val    << SDHC_PSR_WRPPL_Pos)
+#define SDHC_PSR_DATLL_Pos          20           /**< \brief (SDHC_PSR) DAT[3:0] Line Level */
+#define SDHC_PSR_DATLL_Msk          (_U_(0xF) << SDHC_PSR_DATLL_Pos)
+#define SDHC_PSR_DATLL(value)       (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))
+#define SDHC_PSR_CMDLL_Pos          24           /**< \brief (SDHC_PSR) CMD Line Level */
+#define SDHC_PSR_CMDLL              (_U_(0x1) << SDHC_PSR_CMDLL_Pos)
+#define SDHC_PSR_MASK               _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */
+
+/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W  8) Host Control 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  LEDCTRL:1;        /*!< bit:      0  LED Control                        */
+    uint8_t  DW:1;             /*!< bit:      1  Data Width                         */
+    uint8_t  HSEN:1;           /*!< bit:      2  High Speed Enable                  */
+    uint8_t  DMASEL:2;         /*!< bit:  3.. 4  DMA Select                         */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  CARDDTL:1;        /*!< bit:      6  Card Detect Test Level             */
+    uint8_t  CARDDSEL:1;       /*!< bit:      7  Card Detect Signal Selection       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  DW:1;             /*!< bit:      1  Data Width                         */
+    uint8_t  HSEN:1;           /*!< bit:      2  High Speed Enable                  */
+    uint8_t  DMASEL:2;         /*!< bit:  3.. 4  DMA Select                         */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_HC1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HC1R_OFFSET            0x028        /**< \brief (SDHC_HC1R offset) Host Control 1 */
+#define SDHC_HC1R_RESETVALUE        _U_(0xE00)   /**< \brief (SDHC_HC1R reset_value) Host Control 1 */
+
+#define SDHC_HC1R_LEDCTRL_Pos       0            /**< \brief (SDHC_HC1R) LED Control */
+#define SDHC_HC1R_LEDCTRL           (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)
+#define   SDHC_HC1R_LEDCTRL_OFF_Val       _U_(0x0)   /**< \brief (SDHC_HC1R) LED off */
+#define   SDHC_HC1R_LEDCTRL_ON_Val        _U_(0x1)   /**< \brief (SDHC_HC1R) LED on */
+#define SDHC_HC1R_LEDCTRL_OFF       (SDHC_HC1R_LEDCTRL_OFF_Val     << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_LEDCTRL_ON        (SDHC_HC1R_LEDCTRL_ON_Val      << SDHC_HC1R_LEDCTRL_Pos)
+#define SDHC_HC1R_DW_Pos            1            /**< \brief (SDHC_HC1R) Data Width */
+#define SDHC_HC1R_DW                (_U_(0x1) << SDHC_HC1R_DW_Pos)
+#define   SDHC_HC1R_DW_1BIT_Val           _U_(0x0)   /**< \brief (SDHC_HC1R) 1-bit mode */
+#define   SDHC_HC1R_DW_4BIT_Val           _U_(0x1)   /**< \brief (SDHC_HC1R) 4-bit mode */
+#define SDHC_HC1R_DW_1BIT           (SDHC_HC1R_DW_1BIT_Val         << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_DW_4BIT           (SDHC_HC1R_DW_4BIT_Val         << SDHC_HC1R_DW_Pos)
+#define SDHC_HC1R_HSEN_Pos          2            /**< \brief (SDHC_HC1R) High Speed Enable */
+#define SDHC_HC1R_HSEN              (_U_(0x1) << SDHC_HC1R_HSEN_Pos)
+#define   SDHC_HC1R_HSEN_NORMAL_Val       _U_(0x0)   /**< \brief (SDHC_HC1R) Normal Speed mode */
+#define   SDHC_HC1R_HSEN_HIGH_Val         _U_(0x1)   /**< \brief (SDHC_HC1R) High Speed mode */
+#define SDHC_HC1R_HSEN_NORMAL       (SDHC_HC1R_HSEN_NORMAL_Val     << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_HSEN_HIGH         (SDHC_HC1R_HSEN_HIGH_Val       << SDHC_HC1R_HSEN_Pos)
+#define SDHC_HC1R_DMASEL_Pos        3            /**< \brief (SDHC_HC1R) DMA Select */
+#define SDHC_HC1R_DMASEL_Msk        (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL(value)     (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))
+#define   SDHC_HC1R_DMASEL_SDMA_Val       _U_(0x0)   /**< \brief (SDHC_HC1R) SDMA is selected */
+#define   SDHC_HC1R_DMASEL_1_Val          _U_(0x1)   /**< \brief (SDHC_HC1R) Reserved */
+#define   SDHC_HC1R_DMASEL_32BIT_Val      _U_(0x2)   /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */
+#define SDHC_HC1R_DMASEL_SDMA       (SDHC_HC1R_DMASEL_SDMA_Val     << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL_1          (SDHC_HC1R_DMASEL_1_Val        << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_DMASEL_32BIT      (SDHC_HC1R_DMASEL_32BIT_Val    << SDHC_HC1R_DMASEL_Pos)
+#define SDHC_HC1R_CARDDTL_Pos       6            /**< \brief (SDHC_HC1R) Card Detect Test Level */
+#define SDHC_HC1R_CARDDTL           (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)
+#define   SDHC_HC1R_CARDDTL_NO_Val        _U_(0x0)   /**< \brief (SDHC_HC1R) No Card */
+#define   SDHC_HC1R_CARDDTL_YES_Val       _U_(0x1)   /**< \brief (SDHC_HC1R) Card Inserted */
+#define SDHC_HC1R_CARDDTL_NO        (SDHC_HC1R_CARDDTL_NO_Val      << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDTL_YES       (SDHC_HC1R_CARDDTL_YES_Val     << SDHC_HC1R_CARDDTL_Pos)
+#define SDHC_HC1R_CARDDSEL_Pos      7            /**< \brief (SDHC_HC1R) Card Detect Signal Selection */
+#define SDHC_HC1R_CARDDSEL          (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)
+#define   SDHC_HC1R_CARDDSEL_NORMAL_Val   _U_(0x0)   /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */
+#define   SDHC_HC1R_CARDDSEL_TEST_Val     _U_(0x1)   /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */
+#define SDHC_HC1R_CARDDSEL_NORMAL   (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_CARDDSEL_TEST     (SDHC_HC1R_CARDDSEL_TEST_Val   << SDHC_HC1R_CARDDSEL_Pos)
+#define SDHC_HC1R_MASK              _U_(0xDF)    /**< \brief (SDHC_HC1R) MASK Register */
+
+// EMMC mode
+#define SDHC_HC1R_EMMC_DW_Pos       1            /**< \brief (SDHC_HC1R_EMMC) Data Width */
+#define SDHC_HC1R_EMMC_DW           (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)
+#define   SDHC_HC1R_EMMC_DW_1BIT_Val      _U_(0x0)   /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */
+#define   SDHC_HC1R_EMMC_DW_4BIT_Val      _U_(0x1)   /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */
+#define SDHC_HC1R_EMMC_DW_1BIT      (SDHC_HC1R_EMMC_DW_1BIT_Val    << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_DW_4BIT      (SDHC_HC1R_EMMC_DW_4BIT_Val    << SDHC_HC1R_EMMC_DW_Pos)
+#define SDHC_HC1R_EMMC_HSEN_Pos     2            /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */
+#define SDHC_HC1R_EMMC_HSEN         (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)
+#define   SDHC_HC1R_EMMC_HSEN_NORMAL_Val  _U_(0x0)   /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */
+#define   SDHC_HC1R_EMMC_HSEN_HIGH_Val    _U_(0x1)   /**< \brief (SDHC_HC1R_EMMC) High Speed mode */
+#define SDHC_HC1R_EMMC_HSEN_NORMAL  (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_HSEN_HIGH    (SDHC_HC1R_EMMC_HSEN_HIGH_Val  << SDHC_HC1R_EMMC_HSEN_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_Pos   3            /**< \brief (SDHC_HC1R_EMMC) DMA Select */
+#define SDHC_HC1R_EMMC_DMASEL_Msk   (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))
+#define   SDHC_HC1R_EMMC_DMASEL_SDMA_Val  _U_(0x0)   /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */
+#define   SDHC_HC1R_EMMC_DMASEL_1_Val     _U_(0x1)   /**< \brief (SDHC_HC1R_EMMC) Reserved */
+#define   SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2)   /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */
+#define SDHC_HC1R_EMMC_DMASEL_SDMA  (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_1     (SDHC_HC1R_EMMC_DMASEL_1_Val   << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
+#define SDHC_HC1R_EMMC_MASK         _U_(0x1E)    /**< \brief (SDHC_HC1R_EMMC) MASK Register */
+
+/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W  8) Power Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SDBPWR:1;         /*!< bit:      0  SD Bus Power                       */
+    uint8_t  SDBVSEL:3;        /*!< bit:  1.. 3  SD Bus Voltage Select              */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_PCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PCR_OFFSET             0x029        /**< \brief (SDHC_PCR offset) Power Control */
+#define SDHC_PCR_RESETVALUE         _U_(0x0E)    /**< \brief (SDHC_PCR reset_value) Power Control */
+
+#define SDHC_PCR_SDBPWR_Pos         0            /**< \brief (SDHC_PCR) SD Bus Power */
+#define SDHC_PCR_SDBPWR             (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)
+#define   SDHC_PCR_SDBPWR_OFF_Val         _U_(0x0)   /**< \brief (SDHC_PCR) Power off */
+#define   SDHC_PCR_SDBPWR_ON_Val          _U_(0x1)   /**< \brief (SDHC_PCR) Power on */
+#define SDHC_PCR_SDBPWR_OFF         (SDHC_PCR_SDBPWR_OFF_Val       << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBPWR_ON          (SDHC_PCR_SDBPWR_ON_Val        << SDHC_PCR_SDBPWR_Pos)
+#define SDHC_PCR_SDBVSEL_Pos        1            /**< \brief (SDHC_PCR) SD Bus Voltage Select */
+#define SDHC_PCR_SDBVSEL_Msk        (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL(value)     (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))
+#define   SDHC_PCR_SDBVSEL_1V8_Val        _U_(0x5)   /**< \brief (SDHC_PCR) 1.8V (Typ.) */
+#define   SDHC_PCR_SDBVSEL_3V0_Val        _U_(0x6)   /**< \brief (SDHC_PCR) 3.0V (Typ.) */
+#define   SDHC_PCR_SDBVSEL_3V3_Val        _U_(0x7)   /**< \brief (SDHC_PCR) 3.3V (Typ.) */
+#define SDHC_PCR_SDBVSEL_1V8        (SDHC_PCR_SDBVSEL_1V8_Val      << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL_3V0        (SDHC_PCR_SDBVSEL_3V0_Val      << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_SDBVSEL_3V3        (SDHC_PCR_SDBVSEL_3V3_Val      << SDHC_PCR_SDBVSEL_Pos)
+#define SDHC_PCR_MASK               _U_(0x0F)    /**< \brief (SDHC_PCR) MASK Register */
+
+/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W  8) Block Gap Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STPBGR:1;         /*!< bit:      0  Stop at Block Gap Request          */
+    uint8_t  CONTR:1;          /*!< bit:      1  Continue Request                   */
+    uint8_t  RWCTRL:1;         /*!< bit:      2  Read Wait Control                  */
+    uint8_t  INTBG:1;          /*!< bit:      3  Interrupt at Block Gap             */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint8_t  STPBGR:1;         /*!< bit:      0  Stop at Block Gap Request          */
+    uint8_t  CONTR:1;          /*!< bit:      1  Continue Request                   */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_BGCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_BGCR_OFFSET            0x02A        /**< \brief (SDHC_BGCR offset) Block Gap Control */
+#define SDHC_BGCR_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_BGCR reset_value) Block Gap Control */
+
+#define SDHC_BGCR_STPBGR_Pos        0            /**< \brief (SDHC_BGCR) Stop at Block Gap Request */
+#define SDHC_BGCR_STPBGR            (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)
+#define   SDHC_BGCR_STPBGR_TRANSFER_Val   _U_(0x0)   /**< \brief (SDHC_BGCR) Transfer */
+#define   SDHC_BGCR_STPBGR_STOP_Val       _U_(0x1)   /**< \brief (SDHC_BGCR) Stop */
+#define SDHC_BGCR_STPBGR_TRANSFER   (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_STPBGR_STOP       (SDHC_BGCR_STPBGR_STOP_Val     << SDHC_BGCR_STPBGR_Pos)
+#define SDHC_BGCR_CONTR_Pos         1            /**< \brief (SDHC_BGCR) Continue Request */
+#define SDHC_BGCR_CONTR             (_U_(0x1) << SDHC_BGCR_CONTR_Pos)
+#define   SDHC_BGCR_CONTR_GO_ON_Val       _U_(0x0)   /**< \brief (SDHC_BGCR) Not affected */
+#define   SDHC_BGCR_CONTR_RESTART_Val     _U_(0x1)   /**< \brief (SDHC_BGCR) Restart */
+#define SDHC_BGCR_CONTR_GO_ON       (SDHC_BGCR_CONTR_GO_ON_Val     << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_CONTR_RESTART     (SDHC_BGCR_CONTR_RESTART_Val   << SDHC_BGCR_CONTR_Pos)
+#define SDHC_BGCR_RWCTRL_Pos        2            /**< \brief (SDHC_BGCR) Read Wait Control */
+#define SDHC_BGCR_RWCTRL            (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)
+#define   SDHC_BGCR_RWCTRL_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_BGCR) Disable Read Wait Control */
+#define   SDHC_BGCR_RWCTRL_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_BGCR) Enable Read Wait Control */
+#define SDHC_BGCR_RWCTRL_DISABLE    (SDHC_BGCR_RWCTRL_DISABLE_Val  << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_RWCTRL_ENABLE     (SDHC_BGCR_RWCTRL_ENABLE_Val   << SDHC_BGCR_RWCTRL_Pos)
+#define SDHC_BGCR_INTBG_Pos         3            /**< \brief (SDHC_BGCR) Interrupt at Block Gap */
+#define SDHC_BGCR_INTBG             (_U_(0x1) << SDHC_BGCR_INTBG_Pos)
+#define   SDHC_BGCR_INTBG_DISABLED_Val    _U_(0x0)   /**< \brief (SDHC_BGCR) Disabled */
+#define   SDHC_BGCR_INTBG_ENABLED_Val     _U_(0x1)   /**< \brief (SDHC_BGCR) Enabled */
+#define SDHC_BGCR_INTBG_DISABLED    (SDHC_BGCR_INTBG_DISABLED_Val  << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_INTBG_ENABLED     (SDHC_BGCR_INTBG_ENABLED_Val   << SDHC_BGCR_INTBG_Pos)
+#define SDHC_BGCR_MASK              _U_(0x0F)    /**< \brief (SDHC_BGCR) MASK Register */
+
+// EMMC mode
+#define SDHC_BGCR_EMMC_STPBGR_Pos   0            /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */
+#define SDHC_BGCR_EMMC_STPBGR       (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define   SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0)   /**< \brief (SDHC_BGCR_EMMC) Transfer */
+#define   SDHC_BGCR_EMMC_STPBGR_STOP_Val  _U_(0x1)   /**< \brief (SDHC_BGCR_EMMC) Stop */
+#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_STPBGR_STOP  (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_Pos    1            /**< \brief (SDHC_BGCR_EMMC) Continue Request */
+#define SDHC_BGCR_EMMC_CONTR        (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)
+#define   SDHC_BGCR_EMMC_CONTR_GO_ON_Val  _U_(0x0)   /**< \brief (SDHC_BGCR_EMMC) Not affected */
+#define   SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1)   /**< \brief (SDHC_BGCR_EMMC) Restart */
+#define SDHC_BGCR_EMMC_CONTR_GO_ON  (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)
+#define SDHC_BGCR_EMMC_MASK         _U_(0x03)    /**< \brief (SDHC_BGCR_EMMC) MASK Register */
+
+/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W  8) Wakeup Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WKENCINT:1;       /*!< bit:      0  Wakeup Event Enable on Card Interrupt */
+    uint8_t  WKENCINS:1;       /*!< bit:      1  Wakeup Event Enable on Card Insertion */
+    uint8_t  WKENCREM:1;       /*!< bit:      2  Wakeup Event Enable on Card Removal */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_WCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_WCR_OFFSET             0x02B        /**< \brief (SDHC_WCR offset) Wakeup Control */
+#define SDHC_WCR_RESETVALUE         _U_(0x00)    /**< \brief (SDHC_WCR reset_value) Wakeup Control */
+
+#define SDHC_WCR_WKENCINT_Pos       0            /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Interrupt */
+#define SDHC_WCR_WKENCINT           (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)
+#define   SDHC_WCR_WKENCINT_DISABLE_Val   _U_(0x0)   /**< \brief (SDHC_WCR) Disable */
+#define   SDHC_WCR_WKENCINT_ENABLE_Val    _U_(0x1)   /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCINT_DISABLE   (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINT_ENABLE    (SDHC_WCR_WKENCINT_ENABLE_Val  << SDHC_WCR_WKENCINT_Pos)
+#define SDHC_WCR_WKENCINS_Pos       1            /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Insertion */
+#define SDHC_WCR_WKENCINS           (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)
+#define   SDHC_WCR_WKENCINS_DISABLE_Val   _U_(0x0)   /**< \brief (SDHC_WCR) Disable */
+#define   SDHC_WCR_WKENCINS_ENABLE_Val    _U_(0x1)   /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCINS_DISABLE   (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCINS_ENABLE    (SDHC_WCR_WKENCINS_ENABLE_Val  << SDHC_WCR_WKENCINS_Pos)
+#define SDHC_WCR_WKENCREM_Pos       2            /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Removal */
+#define SDHC_WCR_WKENCREM           (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)
+#define   SDHC_WCR_WKENCREM_DISABLE_Val   _U_(0x0)   /**< \brief (SDHC_WCR) Disable */
+#define   SDHC_WCR_WKENCREM_ENABLE_Val    _U_(0x1)   /**< \brief (SDHC_WCR) Enable */
+#define SDHC_WCR_WKENCREM_DISABLE   (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_WKENCREM_ENABLE    (SDHC_WCR_WKENCREM_ENABLE_Val  << SDHC_WCR_WKENCREM_Pos)
+#define SDHC_WCR_MASK               _U_(0x07)    /**< \brief (SDHC_WCR) MASK Register */
+
+/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t INTCLKEN:1;       /*!< bit:      0  Internal Clock Enable              */
+    uint16_t INTCLKS:1;        /*!< bit:      1  Internal Clock Stable              */
+    uint16_t SDCLKEN:1;        /*!< bit:      2  SD Clock Enable                    */
+    uint16_t :2;               /*!< bit:  3.. 4  Reserved                           */
+    uint16_t CLKGSEL:1;        /*!< bit:      5  Clock Generator Select             */
+    uint16_t USDCLKFSEL:2;     /*!< bit:  6.. 7  Upper Bits of SDCLK Frequency Select */
+    uint16_t SDCLKFSEL:8;      /*!< bit:  8..15  SDCLK Frequency Select             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_CCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CCR_OFFSET             0x02C        /**< \brief (SDHC_CCR offset) Clock Control */
+#define SDHC_CCR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_CCR reset_value) Clock Control */
+
+#define SDHC_CCR_INTCLKEN_Pos       0            /**< \brief (SDHC_CCR) Internal Clock Enable */
+#define SDHC_CCR_INTCLKEN           (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)
+#define   SDHC_CCR_INTCLKEN_OFF_Val       _U_(0x0)   /**< \brief (SDHC_CCR) Stop */
+#define   SDHC_CCR_INTCLKEN_ON_Val        _U_(0x1)   /**< \brief (SDHC_CCR) Oscillate */
+#define SDHC_CCR_INTCLKEN_OFF       (SDHC_CCR_INTCLKEN_OFF_Val     << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKEN_ON        (SDHC_CCR_INTCLKEN_ON_Val      << SDHC_CCR_INTCLKEN_Pos)
+#define SDHC_CCR_INTCLKS_Pos        1            /**< \brief (SDHC_CCR) Internal Clock Stable */
+#define SDHC_CCR_INTCLKS            (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)
+#define   SDHC_CCR_INTCLKS_NOT_READY_Val  _U_(0x0)   /**< \brief (SDHC_CCR) Not Ready */
+#define   SDHC_CCR_INTCLKS_READY_Val      _U_(0x1)   /**< \brief (SDHC_CCR) Ready */
+#define SDHC_CCR_INTCLKS_NOT_READY  (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_INTCLKS_READY      (SDHC_CCR_INTCLKS_READY_Val    << SDHC_CCR_INTCLKS_Pos)
+#define SDHC_CCR_SDCLKEN_Pos        2            /**< \brief (SDHC_CCR) SD Clock Enable */
+#define SDHC_CCR_SDCLKEN            (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)
+#define   SDHC_CCR_SDCLKEN_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_CCR) Disable */
+#define   SDHC_CCR_SDCLKEN_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_CCR) Enable */
+#define SDHC_CCR_SDCLKEN_DISABLE    (SDHC_CCR_SDCLKEN_DISABLE_Val  << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_SDCLKEN_ENABLE     (SDHC_CCR_SDCLKEN_ENABLE_Val   << SDHC_CCR_SDCLKEN_Pos)
+#define SDHC_CCR_CLKGSEL_Pos        5            /**< \brief (SDHC_CCR) Clock Generator Select */
+#define SDHC_CCR_CLKGSEL            (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)
+#define   SDHC_CCR_CLKGSEL_DIV_Val        _U_(0x0)   /**< \brief (SDHC_CCR) Divided Clock Mode */
+#define   SDHC_CCR_CLKGSEL_PROG_Val       _U_(0x1)   /**< \brief (SDHC_CCR) Programmable Clock Mode */
+#define SDHC_CCR_CLKGSEL_DIV        (SDHC_CCR_CLKGSEL_DIV_Val      << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_CLKGSEL_PROG       (SDHC_CCR_CLKGSEL_PROG_Val     << SDHC_CCR_CLKGSEL_Pos)
+#define SDHC_CCR_USDCLKFSEL_Pos     6            /**< \brief (SDHC_CCR) Upper Bits of SDCLK Frequency Select */
+#define SDHC_CCR_USDCLKFSEL_Msk     (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)
+#define SDHC_CCR_USDCLKFSEL(value)  (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))
+#define SDHC_CCR_SDCLKFSEL_Pos      8            /**< \brief (SDHC_CCR) SDCLK Frequency Select */
+#define SDHC_CCR_SDCLKFSEL_Msk      (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)
+#define SDHC_CCR_SDCLKFSEL(value)   (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))
+#define SDHC_CCR_MASK               _U_(0xFFE7)  /**< \brief (SDHC_CCR) MASK Register */
+
+/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W  8) Timeout Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTCVAL:4;         /*!< bit:  0.. 3  Data Timeout Counter Value         */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_TCR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_TCR_OFFSET             0x02E        /**< \brief (SDHC_TCR offset) Timeout Control */
+#define SDHC_TCR_RESETVALUE         _U_(0x00)    /**< \brief (SDHC_TCR reset_value) Timeout Control */
+
+#define SDHC_TCR_DTCVAL_Pos         0            /**< \brief (SDHC_TCR) Data Timeout Counter Value */
+#define SDHC_TCR_DTCVAL_Msk         (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)
+#define SDHC_TCR_DTCVAL(value)      (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))
+#define SDHC_TCR_MASK               _U_(0x0F)    /**< \brief (SDHC_TCR) MASK Register */
+
+/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W  8) Software Reset -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRSTALL:1;       /*!< bit:      0  Software Reset For All             */
+    uint8_t  SWRSTCMD:1;       /*!< bit:      1  Software Reset For CMD Line        */
+    uint8_t  SWRSTDAT:1;       /*!< bit:      2  Software Reset For DAT Line        */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_SRR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SRR_OFFSET             0x02F        /**< \brief (SDHC_SRR offset) Software Reset */
+#define SDHC_SRR_RESETVALUE         _U_(0x00)    /**< \brief (SDHC_SRR reset_value) Software Reset */
+
+#define SDHC_SRR_SWRSTALL_Pos       0            /**< \brief (SDHC_SRR) Software Reset For All */
+#define SDHC_SRR_SWRSTALL           (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)
+#define   SDHC_SRR_SWRSTALL_WORK_Val      _U_(0x0)   /**< \brief (SDHC_SRR) Work */
+#define   SDHC_SRR_SWRSTALL_RESET_Val     _U_(0x1)   /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTALL_WORK      (SDHC_SRR_SWRSTALL_WORK_Val    << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTALL_RESET     (SDHC_SRR_SWRSTALL_RESET_Val   << SDHC_SRR_SWRSTALL_Pos)
+#define SDHC_SRR_SWRSTCMD_Pos       1            /**< \brief (SDHC_SRR) Software Reset For CMD Line */
+#define SDHC_SRR_SWRSTCMD           (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)
+#define   SDHC_SRR_SWRSTCMD_WORK_Val      _U_(0x0)   /**< \brief (SDHC_SRR) Work */
+#define   SDHC_SRR_SWRSTCMD_RESET_Val     _U_(0x1)   /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTCMD_WORK      (SDHC_SRR_SWRSTCMD_WORK_Val    << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTCMD_RESET     (SDHC_SRR_SWRSTCMD_RESET_Val   << SDHC_SRR_SWRSTCMD_Pos)
+#define SDHC_SRR_SWRSTDAT_Pos       2            /**< \brief (SDHC_SRR) Software Reset For DAT Line */
+#define SDHC_SRR_SWRSTDAT           (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)
+#define   SDHC_SRR_SWRSTDAT_WORK_Val      _U_(0x0)   /**< \brief (SDHC_SRR) Work */
+#define   SDHC_SRR_SWRSTDAT_RESET_Val     _U_(0x1)   /**< \brief (SDHC_SRR) Reset */
+#define SDHC_SRR_SWRSTDAT_WORK      (SDHC_SRR_SWRSTDAT_WORK_Val    << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_SWRSTDAT_RESET     (SDHC_SRR_SWRSTDAT_RESET_Val   << SDHC_SRR_SWRSTDAT_Pos)
+#define SDHC_SRR_MASK               _U_(0x07)    /**< \brief (SDHC_SRR) MASK Register */
+
+/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDC:1;           /*!< bit:      0  Command Complete                   */
+    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete                  */
+    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event                    */
+    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt                      */
+    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready                 */
+    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready                  */
+    uint16_t CINS:1;           /*!< bit:      6  Card Insertion                     */
+    uint16_t CREM:1;           /*!< bit:      7  Card Removal                       */
+    uint16_t CINT:1;           /*!< bit:      8  Card Interrupt                     */
+    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
+    uint16_t ERRINT:1;         /*!< bit:     15  Error Interrupt                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t CMDC:1;           /*!< bit:      0  Command Complete                   */
+    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete                  */
+    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event                    */
+    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt                      */
+    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready                 */
+    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready                  */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t BOOTAR:1;         /*!< bit:     14  Boot Acknowledge Received          */
+    uint16_t ERRINT:1;         /*!< bit:     15  Error Interrupt                    */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_NISTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISTR_OFFSET           0x030        /**< \brief (SDHC_NISTR offset) Normal Interrupt Status */
+#define SDHC_NISTR_RESETVALUE       _U_(0x0000)  /**< \brief (SDHC_NISTR reset_value) Normal Interrupt Status */
+
+#define SDHC_NISTR_CMDC_Pos         0            /**< \brief (SDHC_NISTR) Command Complete */
+#define SDHC_NISTR_CMDC             (_U_(0x1) << SDHC_NISTR_CMDC_Pos)
+#define   SDHC_NISTR_CMDC_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) No command complete */
+#define   SDHC_NISTR_CMDC_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Command complete */
+#define SDHC_NISTR_CMDC_NO          (SDHC_NISTR_CMDC_NO_Val        << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_CMDC_YES         (SDHC_NISTR_CMDC_YES_Val       << SDHC_NISTR_CMDC_Pos)
+#define SDHC_NISTR_TRFC_Pos         1            /**< \brief (SDHC_NISTR) Transfer Complete */
+#define SDHC_NISTR_TRFC             (_U_(0x1) << SDHC_NISTR_TRFC_Pos)
+#define   SDHC_NISTR_TRFC_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) Not complete */
+#define   SDHC_NISTR_TRFC_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Command execution is completed */
+#define SDHC_NISTR_TRFC_NO          (SDHC_NISTR_TRFC_NO_Val        << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_TRFC_YES         (SDHC_NISTR_TRFC_YES_Val       << SDHC_NISTR_TRFC_Pos)
+#define SDHC_NISTR_BLKGE_Pos        2            /**< \brief (SDHC_NISTR) Block Gap Event */
+#define SDHC_NISTR_BLKGE            (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)
+#define   SDHC_NISTR_BLKGE_NO_Val         _U_(0x0)   /**< \brief (SDHC_NISTR) No Block Gap Event */
+#define   SDHC_NISTR_BLKGE_STOP_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Transaction stopped at block gap */
+#define SDHC_NISTR_BLKGE_NO         (SDHC_NISTR_BLKGE_NO_Val       << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_BLKGE_STOP       (SDHC_NISTR_BLKGE_STOP_Val     << SDHC_NISTR_BLKGE_Pos)
+#define SDHC_NISTR_DMAINT_Pos       3            /**< \brief (SDHC_NISTR) DMA Interrupt */
+#define SDHC_NISTR_DMAINT           (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)
+#define   SDHC_NISTR_DMAINT_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) No DMA Interrupt */
+#define   SDHC_NISTR_DMAINT_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) DMA Interrupt is generated */
+#define SDHC_NISTR_DMAINT_NO        (SDHC_NISTR_DMAINT_NO_Val      << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_DMAINT_YES       (SDHC_NISTR_DMAINT_YES_Val     << SDHC_NISTR_DMAINT_Pos)
+#define SDHC_NISTR_BWRRDY_Pos       4            /**< \brief (SDHC_NISTR) Buffer Write Ready */
+#define SDHC_NISTR_BWRRDY           (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)
+#define   SDHC_NISTR_BWRRDY_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) Not ready to write buffer */
+#define   SDHC_NISTR_BWRRDY_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Ready to write buffer */
+#define SDHC_NISTR_BWRRDY_NO        (SDHC_NISTR_BWRRDY_NO_Val      << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BWRRDY_YES       (SDHC_NISTR_BWRRDY_YES_Val     << SDHC_NISTR_BWRRDY_Pos)
+#define SDHC_NISTR_BRDRDY_Pos       5            /**< \brief (SDHC_NISTR) Buffer Read Ready */
+#define SDHC_NISTR_BRDRDY           (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)
+#define   SDHC_NISTR_BRDRDY_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) Not ready to read buffer */
+#define   SDHC_NISTR_BRDRDY_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Ready to read buffer */
+#define SDHC_NISTR_BRDRDY_NO        (SDHC_NISTR_BRDRDY_NO_Val      << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_BRDRDY_YES       (SDHC_NISTR_BRDRDY_YES_Val     << SDHC_NISTR_BRDRDY_Pos)
+#define SDHC_NISTR_CINS_Pos         6            /**< \brief (SDHC_NISTR) Card Insertion */
+#define SDHC_NISTR_CINS             (_U_(0x1) << SDHC_NISTR_CINS_Pos)
+#define   SDHC_NISTR_CINS_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
+#define   SDHC_NISTR_CINS_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Card inserted */
+#define SDHC_NISTR_CINS_NO          (SDHC_NISTR_CINS_NO_Val        << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CINS_YES         (SDHC_NISTR_CINS_YES_Val       << SDHC_NISTR_CINS_Pos)
+#define SDHC_NISTR_CREM_Pos         7            /**< \brief (SDHC_NISTR) Card Removal */
+#define SDHC_NISTR_CREM             (_U_(0x1) << SDHC_NISTR_CREM_Pos)
+#define   SDHC_NISTR_CREM_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
+#define   SDHC_NISTR_CREM_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Card Removed */
+#define SDHC_NISTR_CREM_NO          (SDHC_NISTR_CREM_NO_Val        << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CREM_YES         (SDHC_NISTR_CREM_YES_Val       << SDHC_NISTR_CREM_Pos)
+#define SDHC_NISTR_CINT_Pos         8            /**< \brief (SDHC_NISTR) Card Interrupt */
+#define SDHC_NISTR_CINT             (_U_(0x1) << SDHC_NISTR_CINT_Pos)
+#define   SDHC_NISTR_CINT_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) No Card Interrupt */
+#define   SDHC_NISTR_CINT_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Generate Card Interrupt */
+#define SDHC_NISTR_CINT_NO          (SDHC_NISTR_CINT_NO_Val        << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_CINT_YES         (SDHC_NISTR_CINT_YES_Val       << SDHC_NISTR_CINT_Pos)
+#define SDHC_NISTR_ERRINT_Pos       15           /**< \brief (SDHC_NISTR) Error Interrupt */
+#define SDHC_NISTR_ERRINT           (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)
+#define   SDHC_NISTR_ERRINT_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) No Error */
+#define   SDHC_NISTR_ERRINT_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Error */
+#define SDHC_NISTR_ERRINT_NO        (SDHC_NISTR_ERRINT_NO_Val      << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_ERRINT_YES       (SDHC_NISTR_ERRINT_YES_Val     << SDHC_NISTR_ERRINT_Pos)
+#define SDHC_NISTR_MASK             _U_(0x81FF)  /**< \brief (SDHC_NISTR) MASK Register */
+
+// EMMC mode
+#define SDHC_NISTR_EMMC_CMDC_Pos    0            /**< \brief (SDHC_NISTR_EMMC) Command Complete */
+#define SDHC_NISTR_EMMC_CMDC        (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)
+#define   SDHC_NISTR_EMMC_CMDC_NO_Val     _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No command complete */
+#define   SDHC_NISTR_EMMC_CMDC_YES_Val    _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Command complete */
+#define SDHC_NISTR_EMMC_CMDC_NO     (SDHC_NISTR_EMMC_CMDC_NO_Val   << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_CMDC_YES    (SDHC_NISTR_EMMC_CMDC_YES_Val  << SDHC_NISTR_EMMC_CMDC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_Pos    1            /**< \brief (SDHC_NISTR_EMMC) Transfer Complete */
+#define SDHC_NISTR_EMMC_TRFC        (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)
+#define   SDHC_NISTR_EMMC_TRFC_NO_Val     _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) Not complete */
+#define   SDHC_NISTR_EMMC_TRFC_YES_Val    _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Command execution is completed */
+#define SDHC_NISTR_EMMC_TRFC_NO     (SDHC_NISTR_EMMC_TRFC_NO_Val   << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_TRFC_YES    (SDHC_NISTR_EMMC_TRFC_YES_Val  << SDHC_NISTR_EMMC_TRFC_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_Pos   2            /**< \brief (SDHC_NISTR_EMMC) Block Gap Event */
+#define SDHC_NISTR_EMMC_BLKGE       (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define   SDHC_NISTR_EMMC_BLKGE_NO_Val    _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No Block Gap Event */
+#define   SDHC_NISTR_EMMC_BLKGE_STOP_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Transaction stopped at block gap */
+#define SDHC_NISTR_EMMC_BLKGE_NO    (SDHC_NISTR_EMMC_BLKGE_NO_Val  << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_BLKGE_STOP  (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_Pos  3            /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt */
+#define SDHC_NISTR_EMMC_DMAINT      (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define   SDHC_NISTR_EMMC_DMAINT_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No DMA Interrupt */
+#define   SDHC_NISTR_EMMC_DMAINT_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt is generated */
+#define SDHC_NISTR_EMMC_DMAINT_NO   (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_DMAINT_YES  (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_Pos  4            /**< \brief (SDHC_NISTR_EMMC) Buffer Write Ready */
+#define SDHC_NISTR_EMMC_BWRRDY      (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define   SDHC_NISTR_EMMC_BWRRDY_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) Not ready to write buffer */
+#define   SDHC_NISTR_EMMC_BWRRDY_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Ready to write buffer */
+#define SDHC_NISTR_EMMC_BWRRDY_NO   (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BWRRDY_YES  (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_Pos  5            /**< \brief (SDHC_NISTR_EMMC) Buffer Read Ready */
+#define SDHC_NISTR_EMMC_BRDRDY      (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define   SDHC_NISTR_EMMC_BRDRDY_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) Not ready to read buffer */
+#define   SDHC_NISTR_EMMC_BRDRDY_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Ready to read buffer */
+#define SDHC_NISTR_EMMC_BRDRDY_NO   (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BRDRDY_YES  (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
+#define SDHC_NISTR_EMMC_BOOTAR_Pos  14           /**< \brief (SDHC_NISTR_EMMC) Boot Acknowledge Received */
+#define SDHC_NISTR_EMMC_BOOTAR      (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_Pos  15           /**< \brief (SDHC_NISTR_EMMC) Error Interrupt */
+#define SDHC_NISTR_EMMC_ERRINT      (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define   SDHC_NISTR_EMMC_ERRINT_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No Error */
+#define   SDHC_NISTR_EMMC_ERRINT_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Error */
+#define SDHC_NISTR_EMMC_ERRINT_NO   (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_ERRINT_YES  (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
+#define SDHC_NISTR_EMMC_MASK        _U_(0xC03F)  /**< \brief (SDHC_NISTR_EMMC) MASK Register */
+
+/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error              */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error                  */
+    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error              */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error                */
+    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error                 */
+    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error                     */
+    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error                 */
+    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error                */
+    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error                     */
+    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error                         */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error              */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error                  */
+    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error              */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error                */
+    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error                 */
+    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error                     */
+    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error                 */
+    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error                */
+    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error                     */
+    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error                         */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t BOOTAE:1;         /*!< bit:     12  Boot Acknowledge Error             */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_EISTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISTR_OFFSET           0x032        /**< \brief (SDHC_EISTR offset) Error Interrupt Status */
+#define SDHC_EISTR_RESETVALUE       _U_(0x0000)  /**< \brief (SDHC_EISTR reset_value) Error Interrupt Status */
+
+#define SDHC_EISTR_CMDTEO_Pos       0            /**< \brief (SDHC_EISTR) Command Timeout Error */
+#define SDHC_EISTR_CMDTEO           (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)
+#define   SDHC_EISTR_CMDTEO_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_CMDTEO_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Timeout */
+#define SDHC_EISTR_CMDTEO_NO        (SDHC_EISTR_CMDTEO_NO_Val      << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDTEO_YES       (SDHC_EISTR_CMDTEO_YES_Val     << SDHC_EISTR_CMDTEO_Pos)
+#define SDHC_EISTR_CMDCRC_Pos       1            /**< \brief (SDHC_EISTR) Command CRC Error */
+#define SDHC_EISTR_CMDCRC           (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)
+#define   SDHC_EISTR_CMDCRC_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_CMDCRC_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) CRC Error Generated */
+#define SDHC_EISTR_CMDCRC_NO        (SDHC_EISTR_CMDCRC_NO_Val      << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDCRC_YES       (SDHC_EISTR_CMDCRC_YES_Val     << SDHC_EISTR_CMDCRC_Pos)
+#define SDHC_EISTR_CMDEND_Pos       2            /**< \brief (SDHC_EISTR) Command End Bit Error */
+#define SDHC_EISTR_CMDEND           (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)
+#define   SDHC_EISTR_CMDEND_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No error */
+#define   SDHC_EISTR_CMDEND_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) End Bit Error Generated */
+#define SDHC_EISTR_CMDEND_NO        (SDHC_EISTR_CMDEND_NO_Val      << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDEND_YES       (SDHC_EISTR_CMDEND_YES_Val     << SDHC_EISTR_CMDEND_Pos)
+#define SDHC_EISTR_CMDIDX_Pos       3            /**< \brief (SDHC_EISTR) Command Index Error */
+#define SDHC_EISTR_CMDIDX           (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)
+#define   SDHC_EISTR_CMDIDX_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_CMDIDX_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_CMDIDX_NO        (SDHC_EISTR_CMDIDX_NO_Val      << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_CMDIDX_YES       (SDHC_EISTR_CMDIDX_YES_Val     << SDHC_EISTR_CMDIDX_Pos)
+#define SDHC_EISTR_DATTEO_Pos       4            /**< \brief (SDHC_EISTR) Data Timeout Error */
+#define SDHC_EISTR_DATTEO           (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)
+#define   SDHC_EISTR_DATTEO_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_DATTEO_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Timeout */
+#define SDHC_EISTR_DATTEO_NO        (SDHC_EISTR_DATTEO_NO_Val      << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATTEO_YES       (SDHC_EISTR_DATTEO_YES_Val     << SDHC_EISTR_DATTEO_Pos)
+#define SDHC_EISTR_DATCRC_Pos       5            /**< \brief (SDHC_EISTR) Data CRC Error */
+#define SDHC_EISTR_DATCRC           (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)
+#define   SDHC_EISTR_DATCRC_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_DATCRC_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_DATCRC_NO        (SDHC_EISTR_DATCRC_NO_Val      << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATCRC_YES       (SDHC_EISTR_DATCRC_YES_Val     << SDHC_EISTR_DATCRC_Pos)
+#define SDHC_EISTR_DATEND_Pos       6            /**< \brief (SDHC_EISTR) Data End Bit Error */
+#define SDHC_EISTR_DATEND           (_U_(0x1) << SDHC_EISTR_DATEND_Pos)
+#define   SDHC_EISTR_DATEND_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_DATEND_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_DATEND_NO        (SDHC_EISTR_DATEND_NO_Val      << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_DATEND_YES       (SDHC_EISTR_DATEND_YES_Val     << SDHC_EISTR_DATEND_Pos)
+#define SDHC_EISTR_CURLIM_Pos       7            /**< \brief (SDHC_EISTR) Current Limit Error */
+#define SDHC_EISTR_CURLIM           (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)
+#define   SDHC_EISTR_CURLIM_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_CURLIM_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Power Fail */
+#define SDHC_EISTR_CURLIM_NO        (SDHC_EISTR_CURLIM_NO_Val      << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_CURLIM_YES       (SDHC_EISTR_CURLIM_YES_Val     << SDHC_EISTR_CURLIM_Pos)
+#define SDHC_EISTR_ACMD_Pos         8            /**< \brief (SDHC_EISTR) Auto CMD Error */
+#define SDHC_EISTR_ACMD             (_U_(0x1) << SDHC_EISTR_ACMD_Pos)
+#define   SDHC_EISTR_ACMD_NO_Val          _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_ACMD_YES_Val         _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_ACMD_NO          (SDHC_EISTR_ACMD_NO_Val        << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ACMD_YES         (SDHC_EISTR_ACMD_YES_Val       << SDHC_EISTR_ACMD_Pos)
+#define SDHC_EISTR_ADMA_Pos         9            /**< \brief (SDHC_EISTR) ADMA Error */
+#define SDHC_EISTR_ADMA             (_U_(0x1) << SDHC_EISTR_ADMA_Pos)
+#define   SDHC_EISTR_ADMA_NO_Val          _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
+#define   SDHC_EISTR_ADMA_YES_Val         _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
+#define SDHC_EISTR_ADMA_NO          (SDHC_EISTR_ADMA_NO_Val        << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_ADMA_YES         (SDHC_EISTR_ADMA_YES_Val       << SDHC_EISTR_ADMA_Pos)
+#define SDHC_EISTR_MASK             _U_(0x03FF)  /**< \brief (SDHC_EISTR) MASK Register */
+
+// EMMC mode
+#define SDHC_EISTR_EMMC_CMDTEO_Pos  0            /**< \brief (SDHC_EISTR_EMMC) Command Timeout Error */
+#define SDHC_EISTR_EMMC_CMDTEO      (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define   SDHC_EISTR_EMMC_CMDTEO_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_CMDTEO_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Timeout */
+#define SDHC_EISTR_EMMC_CMDTEO_NO   (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDTEO_YES  (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_Pos  1            /**< \brief (SDHC_EISTR_EMMC) Command CRC Error */
+#define SDHC_EISTR_EMMC_CMDCRC      (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define   SDHC_EISTR_EMMC_CMDCRC_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_CMDCRC_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) CRC Error Generated */
+#define SDHC_EISTR_EMMC_CMDCRC_NO   (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDCRC_YES  (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_Pos  2            /**< \brief (SDHC_EISTR_EMMC) Command End Bit Error */
+#define SDHC_EISTR_EMMC_CMDEND      (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define   SDHC_EISTR_EMMC_CMDEND_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No error */
+#define   SDHC_EISTR_EMMC_CMDEND_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) End Bit Error Generated */
+#define SDHC_EISTR_EMMC_CMDEND_NO   (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDEND_YES  (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_Pos  3            /**< \brief (SDHC_EISTR_EMMC) Command Index Error */
+#define SDHC_EISTR_EMMC_CMDIDX      (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define   SDHC_EISTR_EMMC_CMDIDX_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_CMDIDX_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_CMDIDX_NO   (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_CMDIDX_YES  (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_Pos  4            /**< \brief (SDHC_EISTR_EMMC) Data Timeout Error */
+#define SDHC_EISTR_EMMC_DATTEO      (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define   SDHC_EISTR_EMMC_DATTEO_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_DATTEO_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Timeout */
+#define SDHC_EISTR_EMMC_DATTEO_NO   (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATTEO_YES  (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_Pos  5            /**< \brief (SDHC_EISTR_EMMC) Data CRC Error */
+#define SDHC_EISTR_EMMC_DATCRC      (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define   SDHC_EISTR_EMMC_DATCRC_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_DATCRC_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_DATCRC_NO   (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATCRC_YES  (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
+#define SDHC_EISTR_EMMC_DATEND_Pos  6            /**< \brief (SDHC_EISTR_EMMC) Data End Bit Error */
+#define SDHC_EISTR_EMMC_DATEND      (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)
+#define   SDHC_EISTR_EMMC_DATEND_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_DATEND_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_DATEND_NO   (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_DATEND_YES  (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_Pos  7            /**< \brief (SDHC_EISTR_EMMC) Current Limit Error */
+#define SDHC_EISTR_EMMC_CURLIM      (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define   SDHC_EISTR_EMMC_CURLIM_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_CURLIM_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Power Fail */
+#define SDHC_EISTR_EMMC_CURLIM_NO   (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_CURLIM_YES  (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
+#define SDHC_EISTR_EMMC_ACMD_Pos    8            /**< \brief (SDHC_EISTR_EMMC) Auto CMD Error */
+#define SDHC_EISTR_EMMC_ACMD        (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)
+#define   SDHC_EISTR_EMMC_ACMD_NO_Val     _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_ACMD_YES_Val    _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_ACMD_NO     (SDHC_EISTR_EMMC_ACMD_NO_Val   << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ACMD_YES    (SDHC_EISTR_EMMC_ACMD_YES_Val  << SDHC_EISTR_EMMC_ACMD_Pos)
+#define SDHC_EISTR_EMMC_ADMA_Pos    9            /**< \brief (SDHC_EISTR_EMMC) ADMA Error */
+#define SDHC_EISTR_EMMC_ADMA        (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)
+#define   SDHC_EISTR_EMMC_ADMA_NO_Val     _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
+#define   SDHC_EISTR_EMMC_ADMA_YES_Val    _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
+#define SDHC_EISTR_EMMC_ADMA_NO     (SDHC_EISTR_EMMC_ADMA_NO_Val   << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_ADMA_YES    (SDHC_EISTR_EMMC_ADMA_YES_Val  << SDHC_EISTR_EMMC_ADMA_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_Pos  12           /**< \brief (SDHC_EISTR_EMMC) Boot Acknowledge Error */
+#define SDHC_EISTR_EMMC_BOOTAE      (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define   SDHC_EISTR_EMMC_BOOTAE_0_Val    _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) FIFO contains at least one byte */
+#define   SDHC_EISTR_EMMC_BOOTAE_1_Val    _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) FIFO is empty */
+#define SDHC_EISTR_EMMC_BOOTAE_0    (SDHC_EISTR_EMMC_BOOTAE_0_Val  << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_BOOTAE_1    (SDHC_EISTR_EMMC_BOOTAE_1_Val  << SDHC_EISTR_EMMC_BOOTAE_Pos)
+#define SDHC_EISTR_EMMC_MASK        _U_(0x13FF)  /**< \brief (SDHC_EISTR_EMMC) MASK Register */
+
+/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Status Enable     */
+    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Status Enable    */
+    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Status Enable      */
+    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Status Enable        */
+    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Status Enable   */
+    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Status Enable    */
+    uint16_t CINS:1;           /*!< bit:      6  Card Insertion Status Enable       */
+    uint16_t CREM:1;           /*!< bit:      7  Card Removal Status Enable         */
+    uint16_t CINT:1;           /*!< bit:      8  Card Interrupt Status Enable       */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Status Enable     */
+    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Status Enable    */
+    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Status Enable      */
+    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Status Enable        */
+    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Status Enable   */
+    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Status Enable    */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t BOOTAR:1;         /*!< bit:     14  Boot Acknowledge Received Status Enable */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_NISTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISTER_OFFSET          0x034        /**< \brief (SDHC_NISTER offset) Normal Interrupt Status Enable */
+#define SDHC_NISTER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_NISTER reset_value) Normal Interrupt Status Enable */
+
+#define SDHC_NISTER_CMDC_Pos        0            /**< \brief (SDHC_NISTER) Command Complete Status Enable */
+#define SDHC_NISTER_CMDC            (_U_(0x1) << SDHC_NISTER_CMDC_Pos)
+#define   SDHC_NISTER_CMDC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_CMDC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CMDC_MASKED     (SDHC_NISTER_CMDC_MASKED_Val   << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_CMDC_ENABLED    (SDHC_NISTER_CMDC_ENABLED_Val  << SDHC_NISTER_CMDC_Pos)
+#define SDHC_NISTER_TRFC_Pos        1            /**< \brief (SDHC_NISTER) Transfer Complete Status Enable */
+#define SDHC_NISTER_TRFC            (_U_(0x1) << SDHC_NISTER_TRFC_Pos)
+#define   SDHC_NISTER_TRFC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_TRFC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_TRFC_MASKED     (SDHC_NISTER_TRFC_MASKED_Val   << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_TRFC_ENABLED    (SDHC_NISTER_TRFC_ENABLED_Val  << SDHC_NISTER_TRFC_Pos)
+#define SDHC_NISTER_BLKGE_Pos       2            /**< \brief (SDHC_NISTER) Block Gap Event Status Enable */
+#define SDHC_NISTER_BLKGE           (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)
+#define   SDHC_NISTER_BLKGE_MASKED_Val    _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_BLKGE_ENABLED_Val   _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BLKGE_MASKED    (SDHC_NISTER_BLKGE_MASKED_Val  << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_BLKGE_ENABLED   (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)
+#define SDHC_NISTER_DMAINT_Pos      3            /**< \brief (SDHC_NISTER) DMA Interrupt Status Enable */
+#define SDHC_NISTER_DMAINT          (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)
+#define   SDHC_NISTER_DMAINT_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_DMAINT_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_DMAINT_MASKED   (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_DMAINT_ENABLED  (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)
+#define SDHC_NISTER_BWRRDY_Pos      4            /**< \brief (SDHC_NISTER) Buffer Write Ready Status Enable */
+#define SDHC_NISTER_BWRRDY          (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)
+#define   SDHC_NISTER_BWRRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_BWRRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BWRRDY_MASKED   (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BWRRDY_ENABLED  (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)
+#define SDHC_NISTER_BRDRDY_Pos      5            /**< \brief (SDHC_NISTER) Buffer Read Ready Status Enable */
+#define SDHC_NISTER_BRDRDY          (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)
+#define   SDHC_NISTER_BRDRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_BRDRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_BRDRDY_MASKED   (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_BRDRDY_ENABLED  (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)
+#define SDHC_NISTER_CINS_Pos        6            /**< \brief (SDHC_NISTER) Card Insertion Status Enable */
+#define SDHC_NISTER_CINS            (_U_(0x1) << SDHC_NISTER_CINS_Pos)
+#define   SDHC_NISTER_CINS_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_CINS_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CINS_MASKED     (SDHC_NISTER_CINS_MASKED_Val   << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CINS_ENABLED    (SDHC_NISTER_CINS_ENABLED_Val  << SDHC_NISTER_CINS_Pos)
+#define SDHC_NISTER_CREM_Pos        7            /**< \brief (SDHC_NISTER) Card Removal Status Enable */
+#define SDHC_NISTER_CREM            (_U_(0x1) << SDHC_NISTER_CREM_Pos)
+#define   SDHC_NISTER_CREM_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_CREM_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CREM_MASKED     (SDHC_NISTER_CREM_MASKED_Val   << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CREM_ENABLED    (SDHC_NISTER_CREM_ENABLED_Val  << SDHC_NISTER_CREM_Pos)
+#define SDHC_NISTER_CINT_Pos        8            /**< \brief (SDHC_NISTER) Card Interrupt Status Enable */
+#define SDHC_NISTER_CINT            (_U_(0x1) << SDHC_NISTER_CINT_Pos)
+#define   SDHC_NISTER_CINT_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
+#define   SDHC_NISTER_CINT_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
+#define SDHC_NISTER_CINT_MASKED     (SDHC_NISTER_CINT_MASKED_Val   << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_CINT_ENABLED    (SDHC_NISTER_CINT_ENABLED_Val  << SDHC_NISTER_CINT_Pos)
+#define SDHC_NISTER_MASK            _U_(0x01FF)  /**< \brief (SDHC_NISTER) MASK Register */
+
+// EMMC mode
+#define SDHC_NISTER_EMMC_CMDC_Pos   0            /**< \brief (SDHC_NISTER_EMMC) Command Complete Status Enable */
+#define SDHC_NISTER_EMMC_CMDC       (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)
+#define   SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define   SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_Pos   1            /**< \brief (SDHC_NISTER_EMMC) Transfer Complete Status Enable */
+#define SDHC_NISTER_EMMC_TRFC       (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)
+#define   SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define   SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_Pos  2            /**< \brief (SDHC_NISTER_EMMC) Block Gap Event Status Enable */
+#define SDHC_NISTER_EMMC_BLKGE      (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define   SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define   SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_Pos 3            /**< \brief (SDHC_NISTER_EMMC) DMA Interrupt Status Enable */
+#define SDHC_NISTER_EMMC_DMAINT     (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define   SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define   SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_Pos 4            /**< \brief (SDHC_NISTER_EMMC) Buffer Write Ready Status Enable */
+#define SDHC_NISTER_EMMC_BWRRDY     (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define   SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define   SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_Pos 5            /**< \brief (SDHC_NISTER_EMMC) Buffer Read Ready Status Enable */
+#define SDHC_NISTER_EMMC_BRDRDY     (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define   SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
+#define   SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
+#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
+#define SDHC_NISTER_EMMC_BOOTAR_Pos 14           /**< \brief (SDHC_NISTER_EMMC) Boot Acknowledge Received Status Enable */
+#define SDHC_NISTER_EMMC_BOOTAR     (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)
+#define SDHC_NISTER_EMMC_MASK       _U_(0x403F)  /**< \brief (SDHC_NISTER_EMMC) MASK Register */
+
+/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Status Enable */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Status Enable    */
+    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Status Enable */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Status Enable  */
+    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Status Enable   */
+    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Status Enable       */
+    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Status Enable   */
+    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Status Enable  */
+    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Status Enable       */
+    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Status Enable           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Status Enable */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Status Enable    */
+    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Status Enable */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Status Enable  */
+    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Status Enable   */
+    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Status Enable       */
+    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Status Enable   */
+    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Status Enable  */
+    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Status Enable       */
+    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Status Enable           */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t BOOTAE:1;         /*!< bit:     12  Boot Acknowledge Error Status Enable */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_EISTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISTER_OFFSET          0x036        /**< \brief (SDHC_EISTER offset) Error Interrupt Status Enable */
+#define SDHC_EISTER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_EISTER reset_value) Error Interrupt Status Enable */
+
+#define SDHC_EISTER_CMDTEO_Pos      0            /**< \brief (SDHC_EISTER) Command Timeout Error Status Enable */
+#define SDHC_EISTER_CMDTEO          (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)
+#define   SDHC_EISTER_CMDTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_CMDTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDTEO_MASKED   (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDTEO_ENABLED  (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)
+#define SDHC_EISTER_CMDCRC_Pos      1            /**< \brief (SDHC_EISTER) Command CRC Error Status Enable */
+#define SDHC_EISTER_CMDCRC          (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)
+#define   SDHC_EISTER_CMDCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_CMDCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDCRC_MASKED   (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDCRC_ENABLED  (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)
+#define SDHC_EISTER_CMDEND_Pos      2            /**< \brief (SDHC_EISTER) Command End Bit Error Status Enable */
+#define SDHC_EISTER_CMDEND          (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)
+#define   SDHC_EISTER_CMDEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_CMDEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDEND_MASKED   (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDEND_ENABLED  (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)
+#define SDHC_EISTER_CMDIDX_Pos      3            /**< \brief (SDHC_EISTER) Command Index Error Status Enable */
+#define SDHC_EISTER_CMDIDX          (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)
+#define   SDHC_EISTER_CMDIDX_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_CMDIDX_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CMDIDX_MASKED   (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_CMDIDX_ENABLED  (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)
+#define SDHC_EISTER_DATTEO_Pos      4            /**< \brief (SDHC_EISTER) Data Timeout Error Status Enable */
+#define SDHC_EISTER_DATTEO          (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)
+#define   SDHC_EISTER_DATTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_DATTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATTEO_MASKED   (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATTEO_ENABLED  (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)
+#define SDHC_EISTER_DATCRC_Pos      5            /**< \brief (SDHC_EISTER) Data CRC Error Status Enable */
+#define SDHC_EISTER_DATCRC          (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)
+#define   SDHC_EISTER_DATCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_DATCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATCRC_MASKED   (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATCRC_ENABLED  (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)
+#define SDHC_EISTER_DATEND_Pos      6            /**< \brief (SDHC_EISTER) Data End Bit Error Status Enable */
+#define SDHC_EISTER_DATEND          (_U_(0x1) << SDHC_EISTER_DATEND_Pos)
+#define   SDHC_EISTER_DATEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_DATEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_DATEND_MASKED   (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_DATEND_ENABLED  (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)
+#define SDHC_EISTER_CURLIM_Pos      7            /**< \brief (SDHC_EISTER) Current Limit Error Status Enable */
+#define SDHC_EISTER_CURLIM          (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)
+#define   SDHC_EISTER_CURLIM_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_CURLIM_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_CURLIM_MASKED   (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_CURLIM_ENABLED  (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)
+#define SDHC_EISTER_ACMD_Pos        8            /**< \brief (SDHC_EISTER) Auto CMD Error Status Enable */
+#define SDHC_EISTER_ACMD            (_U_(0x1) << SDHC_EISTER_ACMD_Pos)
+#define   SDHC_EISTER_ACMD_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_ACMD_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_ACMD_MASKED     (SDHC_EISTER_ACMD_MASKED_Val   << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ACMD_ENABLED    (SDHC_EISTER_ACMD_ENABLED_Val  << SDHC_EISTER_ACMD_Pos)
+#define SDHC_EISTER_ADMA_Pos        9            /**< \brief (SDHC_EISTER) ADMA Error Status Enable */
+#define SDHC_EISTER_ADMA            (_U_(0x1) << SDHC_EISTER_ADMA_Pos)
+#define   SDHC_EISTER_ADMA_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
+#define   SDHC_EISTER_ADMA_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
+#define SDHC_EISTER_ADMA_MASKED     (SDHC_EISTER_ADMA_MASKED_Val   << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_ADMA_ENABLED    (SDHC_EISTER_ADMA_ENABLED_Val  << SDHC_EISTER_ADMA_Pos)
+#define SDHC_EISTER_MASK            _U_(0x03FF)  /**< \brief (SDHC_EISTER) MASK Register */
+
+// EMMC mode
+#define SDHC_EISTER_EMMC_CMDTEO_Pos 0            /**< \brief (SDHC_EISTER_EMMC) Command Timeout Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDTEO     (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define   SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_Pos 1            /**< \brief (SDHC_EISTER_EMMC) Command CRC Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDCRC     (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define   SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_Pos 2            /**< \brief (SDHC_EISTER_EMMC) Command End Bit Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDEND     (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define   SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_Pos 3            /**< \brief (SDHC_EISTER_EMMC) Command Index Error Status Enable */
+#define SDHC_EISTER_EMMC_CMDIDX     (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define   SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_Pos 4            /**< \brief (SDHC_EISTER_EMMC) Data Timeout Error Status Enable */
+#define SDHC_EISTER_EMMC_DATTEO     (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define   SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_Pos 5            /**< \brief (SDHC_EISTER_EMMC) Data CRC Error Status Enable */
+#define SDHC_EISTER_EMMC_DATCRC     (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define   SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
+#define SDHC_EISTER_EMMC_DATEND_Pos 6            /**< \brief (SDHC_EISTER_EMMC) Data End Bit Error Status Enable */
+#define SDHC_EISTER_EMMC_DATEND     (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)
+#define   SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_Pos 7            /**< \brief (SDHC_EISTER_EMMC) Current Limit Error Status Enable */
+#define SDHC_EISTER_EMMC_CURLIM     (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define   SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
+#define SDHC_EISTER_EMMC_ACMD_Pos   8            /**< \brief (SDHC_EISTER_EMMC) Auto CMD Error Status Enable */
+#define SDHC_EISTER_EMMC_ACMD       (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)
+#define   SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
+#define SDHC_EISTER_EMMC_ADMA_Pos   9            /**< \brief (SDHC_EISTER_EMMC) ADMA Error Status Enable */
+#define SDHC_EISTER_EMMC_ADMA       (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)
+#define   SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
+#define   SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
+#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
+#define SDHC_EISTER_EMMC_BOOTAE_Pos 12           /**< \brief (SDHC_EISTER_EMMC) Boot Acknowledge Error Status Enable */
+#define SDHC_EISTER_EMMC_BOOTAE     (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)
+#define SDHC_EISTER_EMMC_MASK       _U_(0x13FF)  /**< \brief (SDHC_EISTER_EMMC) MASK Register */
+
+/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Signal Enable     */
+    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Signal Enable    */
+    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Signal Enable      */
+    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Signal Enable        */
+    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Signal Enable   */
+    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Signal Enable    */
+    uint16_t CINS:1;           /*!< bit:      6  Card Insertion Signal Enable       */
+    uint16_t CREM:1;           /*!< bit:      7  Card Removal Signal Enable         */
+    uint16_t CINT:1;           /*!< bit:      8  Card Interrupt Signal Enable       */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Signal Enable     */
+    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Signal Enable    */
+    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Signal Enable      */
+    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Signal Enable        */
+    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Signal Enable   */
+    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Signal Enable    */
+    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
+    uint16_t BOOTAR:1;         /*!< bit:     14  Boot Acknowledge Received Signal Enable */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_NISIER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_NISIER_OFFSET          0x038        /**< \brief (SDHC_NISIER offset) Normal Interrupt Signal Enable */
+#define SDHC_NISIER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_NISIER reset_value) Normal Interrupt Signal Enable */
+
+#define SDHC_NISIER_CMDC_Pos        0            /**< \brief (SDHC_NISIER) Command Complete Signal Enable */
+#define SDHC_NISIER_CMDC            (_U_(0x1) << SDHC_NISIER_CMDC_Pos)
+#define   SDHC_NISIER_CMDC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_CMDC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CMDC_MASKED     (SDHC_NISIER_CMDC_MASKED_Val   << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_CMDC_ENABLED    (SDHC_NISIER_CMDC_ENABLED_Val  << SDHC_NISIER_CMDC_Pos)
+#define SDHC_NISIER_TRFC_Pos        1            /**< \brief (SDHC_NISIER) Transfer Complete Signal Enable */
+#define SDHC_NISIER_TRFC            (_U_(0x1) << SDHC_NISIER_TRFC_Pos)
+#define   SDHC_NISIER_TRFC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_TRFC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_TRFC_MASKED     (SDHC_NISIER_TRFC_MASKED_Val   << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_TRFC_ENABLED    (SDHC_NISIER_TRFC_ENABLED_Val  << SDHC_NISIER_TRFC_Pos)
+#define SDHC_NISIER_BLKGE_Pos       2            /**< \brief (SDHC_NISIER) Block Gap Event Signal Enable */
+#define SDHC_NISIER_BLKGE           (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)
+#define   SDHC_NISIER_BLKGE_MASKED_Val    _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_BLKGE_ENABLED_Val   _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BLKGE_MASKED    (SDHC_NISIER_BLKGE_MASKED_Val  << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_BLKGE_ENABLED   (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)
+#define SDHC_NISIER_DMAINT_Pos      3            /**< \brief (SDHC_NISIER) DMA Interrupt Signal Enable */
+#define SDHC_NISIER_DMAINT          (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)
+#define   SDHC_NISIER_DMAINT_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_DMAINT_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_DMAINT_MASKED   (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_DMAINT_ENABLED  (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)
+#define SDHC_NISIER_BWRRDY_Pos      4            /**< \brief (SDHC_NISIER) Buffer Write Ready Signal Enable */
+#define SDHC_NISIER_BWRRDY          (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)
+#define   SDHC_NISIER_BWRRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_BWRRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BWRRDY_MASKED   (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BWRRDY_ENABLED  (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)
+#define SDHC_NISIER_BRDRDY_Pos      5            /**< \brief (SDHC_NISIER) Buffer Read Ready Signal Enable */
+#define SDHC_NISIER_BRDRDY          (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)
+#define   SDHC_NISIER_BRDRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_BRDRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_BRDRDY_MASKED   (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_BRDRDY_ENABLED  (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)
+#define SDHC_NISIER_CINS_Pos        6            /**< \brief (SDHC_NISIER) Card Insertion Signal Enable */
+#define SDHC_NISIER_CINS            (_U_(0x1) << SDHC_NISIER_CINS_Pos)
+#define   SDHC_NISIER_CINS_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_CINS_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CINS_MASKED     (SDHC_NISIER_CINS_MASKED_Val   << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CINS_ENABLED    (SDHC_NISIER_CINS_ENABLED_Val  << SDHC_NISIER_CINS_Pos)
+#define SDHC_NISIER_CREM_Pos        7            /**< \brief (SDHC_NISIER) Card Removal Signal Enable */
+#define SDHC_NISIER_CREM            (_U_(0x1) << SDHC_NISIER_CREM_Pos)
+#define   SDHC_NISIER_CREM_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_CREM_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CREM_MASKED     (SDHC_NISIER_CREM_MASKED_Val   << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CREM_ENABLED    (SDHC_NISIER_CREM_ENABLED_Val  << SDHC_NISIER_CREM_Pos)
+#define SDHC_NISIER_CINT_Pos        8            /**< \brief (SDHC_NISIER) Card Interrupt Signal Enable */
+#define SDHC_NISIER_CINT            (_U_(0x1) << SDHC_NISIER_CINT_Pos)
+#define   SDHC_NISIER_CINT_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
+#define   SDHC_NISIER_CINT_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
+#define SDHC_NISIER_CINT_MASKED     (SDHC_NISIER_CINT_MASKED_Val   << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_CINT_ENABLED    (SDHC_NISIER_CINT_ENABLED_Val  << SDHC_NISIER_CINT_Pos)
+#define SDHC_NISIER_MASK            _U_(0x01FF)  /**< \brief (SDHC_NISIER) MASK Register */
+
+// EMMC mode
+#define SDHC_NISIER_EMMC_CMDC_Pos   0            /**< \brief (SDHC_NISIER_EMMC) Command Complete Signal Enable */
+#define SDHC_NISIER_EMMC_CMDC       (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)
+#define   SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define   SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_Pos   1            /**< \brief (SDHC_NISIER_EMMC) Transfer Complete Signal Enable */
+#define SDHC_NISIER_EMMC_TRFC       (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)
+#define   SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define   SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_Pos  2            /**< \brief (SDHC_NISIER_EMMC) Block Gap Event Signal Enable */
+#define SDHC_NISIER_EMMC_BLKGE      (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define   SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define   SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_Pos 3            /**< \brief (SDHC_NISIER_EMMC) DMA Interrupt Signal Enable */
+#define SDHC_NISIER_EMMC_DMAINT     (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define   SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define   SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_Pos 4            /**< \brief (SDHC_NISIER_EMMC) Buffer Write Ready Signal Enable */
+#define SDHC_NISIER_EMMC_BWRRDY     (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define   SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define   SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_Pos 5            /**< \brief (SDHC_NISIER_EMMC) Buffer Read Ready Signal Enable */
+#define SDHC_NISIER_EMMC_BRDRDY     (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define   SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
+#define   SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
+#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
+#define SDHC_NISIER_EMMC_BOOTAR_Pos 14           /**< \brief (SDHC_NISIER_EMMC) Boot Acknowledge Received Signal Enable */
+#define SDHC_NISIER_EMMC_BOOTAR     (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)
+#define SDHC_NISIER_EMMC_MASK       _U_(0x403F)  /**< \brief (SDHC_NISIER_EMMC) MASK Register */
+
+/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Signal Enable */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Signal Enable    */
+    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Signal Enable */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Signal Enable  */
+    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Signal Enable   */
+    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Signal Enable       */
+    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Signal Enable   */
+    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Signal Enable  */
+    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Signal Enable       */
+    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Signal Enable           */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Signal Enable */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Signal Enable    */
+    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Signal Enable */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Signal Enable  */
+    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Signal Enable   */
+    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Signal Enable       */
+    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Signal Enable   */
+    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Signal Enable  */
+    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Signal Enable       */
+    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Signal Enable           */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t BOOTAE:1;         /*!< bit:     12  Boot Acknowledge Error Signal Enable */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_EISIER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_EISIER_OFFSET          0x03A        /**< \brief (SDHC_EISIER offset) Error Interrupt Signal Enable */
+#define SDHC_EISIER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_EISIER reset_value) Error Interrupt Signal Enable */
+
+#define SDHC_EISIER_CMDTEO_Pos      0            /**< \brief (SDHC_EISIER) Command Timeout Error Signal Enable */
+#define SDHC_EISIER_CMDTEO          (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)
+#define   SDHC_EISIER_CMDTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_CMDTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDTEO_MASKED   (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDTEO_ENABLED  (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)
+#define SDHC_EISIER_CMDCRC_Pos      1            /**< \brief (SDHC_EISIER) Command CRC Error Signal Enable */
+#define SDHC_EISIER_CMDCRC          (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)
+#define   SDHC_EISIER_CMDCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_CMDCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDCRC_MASKED   (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDCRC_ENABLED  (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)
+#define SDHC_EISIER_CMDEND_Pos      2            /**< \brief (SDHC_EISIER) Command End Bit Error Signal Enable */
+#define SDHC_EISIER_CMDEND          (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)
+#define   SDHC_EISIER_CMDEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_CMDEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDEND_MASKED   (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDEND_ENABLED  (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)
+#define SDHC_EISIER_CMDIDX_Pos      3            /**< \brief (SDHC_EISIER) Command Index Error Signal Enable */
+#define SDHC_EISIER_CMDIDX          (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)
+#define   SDHC_EISIER_CMDIDX_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_CMDIDX_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CMDIDX_MASKED   (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_CMDIDX_ENABLED  (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)
+#define SDHC_EISIER_DATTEO_Pos      4            /**< \brief (SDHC_EISIER) Data Timeout Error Signal Enable */
+#define SDHC_EISIER_DATTEO          (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)
+#define   SDHC_EISIER_DATTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_DATTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATTEO_MASKED   (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATTEO_ENABLED  (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)
+#define SDHC_EISIER_DATCRC_Pos      5            /**< \brief (SDHC_EISIER) Data CRC Error Signal Enable */
+#define SDHC_EISIER_DATCRC          (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)
+#define   SDHC_EISIER_DATCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_DATCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATCRC_MASKED   (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATCRC_ENABLED  (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)
+#define SDHC_EISIER_DATEND_Pos      6            /**< \brief (SDHC_EISIER) Data End Bit Error Signal Enable */
+#define SDHC_EISIER_DATEND          (_U_(0x1) << SDHC_EISIER_DATEND_Pos)
+#define   SDHC_EISIER_DATEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_DATEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_DATEND_MASKED   (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_DATEND_ENABLED  (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)
+#define SDHC_EISIER_CURLIM_Pos      7            /**< \brief (SDHC_EISIER) Current Limit Error Signal Enable */
+#define SDHC_EISIER_CURLIM          (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)
+#define   SDHC_EISIER_CURLIM_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_CURLIM_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_CURLIM_MASKED   (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_CURLIM_ENABLED  (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)
+#define SDHC_EISIER_ACMD_Pos        8            /**< \brief (SDHC_EISIER) Auto CMD Error Signal Enable */
+#define SDHC_EISIER_ACMD            (_U_(0x1) << SDHC_EISIER_ACMD_Pos)
+#define   SDHC_EISIER_ACMD_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_ACMD_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_ACMD_MASKED     (SDHC_EISIER_ACMD_MASKED_Val   << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ACMD_ENABLED    (SDHC_EISIER_ACMD_ENABLED_Val  << SDHC_EISIER_ACMD_Pos)
+#define SDHC_EISIER_ADMA_Pos        9            /**< \brief (SDHC_EISIER) ADMA Error Signal Enable */
+#define SDHC_EISIER_ADMA            (_U_(0x1) << SDHC_EISIER_ADMA_Pos)
+#define   SDHC_EISIER_ADMA_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
+#define   SDHC_EISIER_ADMA_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
+#define SDHC_EISIER_ADMA_MASKED     (SDHC_EISIER_ADMA_MASKED_Val   << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_ADMA_ENABLED    (SDHC_EISIER_ADMA_ENABLED_Val  << SDHC_EISIER_ADMA_Pos)
+#define SDHC_EISIER_MASK            _U_(0x03FF)  /**< \brief (SDHC_EISIER) MASK Register */
+
+// EMMC mode
+#define SDHC_EISIER_EMMC_CMDTEO_Pos 0            /**< \brief (SDHC_EISIER_EMMC) Command Timeout Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDTEO     (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define   SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_Pos 1            /**< \brief (SDHC_EISIER_EMMC) Command CRC Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDCRC     (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define   SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_Pos 2            /**< \brief (SDHC_EISIER_EMMC) Command End Bit Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDEND     (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define   SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_Pos 3            /**< \brief (SDHC_EISIER_EMMC) Command Index Error Signal Enable */
+#define SDHC_EISIER_EMMC_CMDIDX     (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define   SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_Pos 4            /**< \brief (SDHC_EISIER_EMMC) Data Timeout Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATTEO     (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define   SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_Pos 5            /**< \brief (SDHC_EISIER_EMMC) Data CRC Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATCRC     (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define   SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
+#define SDHC_EISIER_EMMC_DATEND_Pos 6            /**< \brief (SDHC_EISIER_EMMC) Data End Bit Error Signal Enable */
+#define SDHC_EISIER_EMMC_DATEND     (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)
+#define   SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_Pos 7            /**< \brief (SDHC_EISIER_EMMC) Current Limit Error Signal Enable */
+#define SDHC_EISIER_EMMC_CURLIM     (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define   SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
+#define SDHC_EISIER_EMMC_ACMD_Pos   8            /**< \brief (SDHC_EISIER_EMMC) Auto CMD Error Signal Enable */
+#define SDHC_EISIER_EMMC_ACMD       (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)
+#define   SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
+#define SDHC_EISIER_EMMC_ADMA_Pos   9            /**< \brief (SDHC_EISIER_EMMC) ADMA Error Signal Enable */
+#define SDHC_EISIER_EMMC_ADMA       (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)
+#define   SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
+#define   SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
+#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
+#define SDHC_EISIER_EMMC_BOOTAE_Pos 12           /**< \brief (SDHC_EISIER_EMMC) Boot Acknowledge Error Signal Enable */
+#define SDHC_EISIER_EMMC_BOOTAE     (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)
+#define SDHC_EISIER_EMMC_MASK       _U_(0x13FF)  /**< \brief (SDHC_EISIER_EMMC) MASK Register */
+
+/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/  16) Auto CMD Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ACMD12NE:1;       /*!< bit:      0  Auto CMD12 Not Executed            */
+    uint16_t ACMDTEO:1;        /*!< bit:      1  Auto CMD Timeout Error             */
+    uint16_t ACMDCRC:1;        /*!< bit:      2  Auto CMD CRC Error                 */
+    uint16_t ACMDEND:1;        /*!< bit:      3  Auto CMD End Bit Error             */
+    uint16_t ACMDIDX:1;        /*!< bit:      4  Auto CMD Index Error               */
+    uint16_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint16_t CMDNI:1;          /*!< bit:      7  Command not Issued By Auto CMD12 Error */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_ACESR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ACESR_OFFSET           0x03C        /**< \brief (SDHC_ACESR offset) Auto CMD Error Status */
+#define SDHC_ACESR_RESETVALUE       _U_(0x0000)  /**< \brief (SDHC_ACESR reset_value) Auto CMD Error Status */
+
+#define SDHC_ACESR_ACMD12NE_Pos     0            /**< \brief (SDHC_ACESR) Auto CMD12 Not Executed */
+#define SDHC_ACESR_ACMD12NE         (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)
+#define   SDHC_ACESR_ACMD12NE_EXEC_Val    _U_(0x0)   /**< \brief (SDHC_ACESR) Executed */
+#define   SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1)   /**< \brief (SDHC_ACESR) Not executed */
+#define SDHC_ACESR_ACMD12NE_EXEC    (SDHC_ACESR_ACMD12NE_EXEC_Val  << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
+#define SDHC_ACESR_ACMDTEO_Pos      1            /**< \brief (SDHC_ACESR) Auto CMD Timeout Error */
+#define SDHC_ACESR_ACMDTEO          (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)
+#define   SDHC_ACESR_ACMDTEO_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
+#define   SDHC_ACESR_ACMDTEO_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) Timeout */
+#define SDHC_ACESR_ACMDTEO_NO       (SDHC_ACESR_ACMDTEO_NO_Val     << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDTEO_YES      (SDHC_ACESR_ACMDTEO_YES_Val    << SDHC_ACESR_ACMDTEO_Pos)
+#define SDHC_ACESR_ACMDCRC_Pos      2            /**< \brief (SDHC_ACESR) Auto CMD CRC Error */
+#define SDHC_ACESR_ACMDCRC          (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)
+#define   SDHC_ACESR_ACMDCRC_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
+#define   SDHC_ACESR_ACMDCRC_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) CRC Error Generated */
+#define SDHC_ACESR_ACMDCRC_NO       (SDHC_ACESR_ACMDCRC_NO_Val     << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDCRC_YES      (SDHC_ACESR_ACMDCRC_YES_Val    << SDHC_ACESR_ACMDCRC_Pos)
+#define SDHC_ACESR_ACMDEND_Pos      3            /**< \brief (SDHC_ACESR) Auto CMD End Bit Error */
+#define SDHC_ACESR_ACMDEND          (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)
+#define   SDHC_ACESR_ACMDEND_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
+#define   SDHC_ACESR_ACMDEND_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) End Bit Error Generated */
+#define SDHC_ACESR_ACMDEND_NO       (SDHC_ACESR_ACMDEND_NO_Val     << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDEND_YES      (SDHC_ACESR_ACMDEND_YES_Val    << SDHC_ACESR_ACMDEND_Pos)
+#define SDHC_ACESR_ACMDIDX_Pos      4            /**< \brief (SDHC_ACESR) Auto CMD Index Error */
+#define SDHC_ACESR_ACMDIDX          (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)
+#define   SDHC_ACESR_ACMDIDX_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
+#define   SDHC_ACESR_ACMDIDX_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) Error */
+#define SDHC_ACESR_ACMDIDX_NO       (SDHC_ACESR_ACMDIDX_NO_Val     << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_ACMDIDX_YES      (SDHC_ACESR_ACMDIDX_YES_Val    << SDHC_ACESR_ACMDIDX_Pos)
+#define SDHC_ACESR_CMDNI_Pos        7            /**< \brief (SDHC_ACESR) Command not Issued By Auto CMD12 Error */
+#define SDHC_ACESR_CMDNI            (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)
+#define   SDHC_ACESR_CMDNI_OK_Val         _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
+#define   SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1)   /**< \brief (SDHC_ACESR) Not Issued */
+#define SDHC_ACESR_CMDNI_OK         (SDHC_ACESR_CMDNI_OK_Val       << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)
+#define SDHC_ACESR_MASK             _U_(0x009F)  /**< \brief (SDHC_ACESR) MASK Register */
+
+/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t UHSMS:3;          /*!< bit:  0.. 2  UHS Mode Select                    */
+    uint16_t VS18EN:1;         /*!< bit:      3  1.8V Signaling Enable              */
+    uint16_t DRVSEL:2;         /*!< bit:  4.. 5  Driver Strength Select             */
+    uint16_t EXTUN:1;          /*!< bit:      6  Execute Tuning                     */
+    uint16_t SLCKSEL:1;        /*!< bit:      7  Sampling Clock Select              */
+    uint16_t :6;               /*!< bit:  8..13  Reserved                           */
+    uint16_t ASINTEN:1;        /*!< bit:     14  Asynchronous Interrupt Enable      */
+    uint16_t PVALEN:1;         /*!< bit:     15  Preset Value Enable                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // EMMC mode
+    uint16_t HS200EN:4;        /*!< bit:  0.. 3  HS200 Mode Enable                  */
+    uint16_t DRVSEL:2;         /*!< bit:  4.. 5  Driver Strength Select             */
+    uint16_t EXTUN:1;          /*!< bit:      6  Execute Tuning                     */
+    uint16_t SLCKSEL:1;        /*!< bit:      7  Sampling Clock Select              */
+    uint16_t :7;               /*!< bit:  8..14  Reserved                           */
+    uint16_t PVALEN:1;         /*!< bit:     15  Preset Value Enable                */
+  } EMMC;                      /*!< Structure used for EMMC                         */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_HC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HC2R_OFFSET            0x03E        /**< \brief (SDHC_HC2R offset) Host Control 2 */
+#define SDHC_HC2R_RESETVALUE        _U_(0x0000)  /**< \brief (SDHC_HC2R reset_value) Host Control 2 */
+
+#define SDHC_HC2R_UHSMS_Pos         0            /**< \brief (SDHC_HC2R) UHS Mode Select */
+#define SDHC_HC2R_UHSMS_Msk         (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS(value)      (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))
+#define   SDHC_HC2R_UHSMS_SDR12_Val       _U_(0x0)   /**< \brief (SDHC_HC2R) SDR12 */
+#define   SDHC_HC2R_UHSMS_SDR25_Val       _U_(0x1)   /**< \brief (SDHC_HC2R) SDR25 */
+#define   SDHC_HC2R_UHSMS_SDR50_Val       _U_(0x2)   /**< \brief (SDHC_HC2R) SDR50 */
+#define   SDHC_HC2R_UHSMS_SDR104_Val      _U_(0x3)   /**< \brief (SDHC_HC2R) SDR104 */
+#define   SDHC_HC2R_UHSMS_DDR50_Val       _U_(0x4)   /**< \brief (SDHC_HC2R) DDR50 */
+#define SDHC_HC2R_UHSMS_SDR12       (SDHC_HC2R_UHSMS_SDR12_Val     << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR25       (SDHC_HC2R_UHSMS_SDR25_Val     << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR50       (SDHC_HC2R_UHSMS_SDR50_Val     << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_SDR104      (SDHC_HC2R_UHSMS_SDR104_Val    << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_UHSMS_DDR50       (SDHC_HC2R_UHSMS_DDR50_Val     << SDHC_HC2R_UHSMS_Pos)
+#define SDHC_HC2R_VS18EN_Pos        3            /**< \brief (SDHC_HC2R) 1.8V Signaling Enable */
+#define SDHC_HC2R_VS18EN            (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)
+#define   SDHC_HC2R_VS18EN_S33V_Val       _U_(0x0)   /**< \brief (SDHC_HC2R) 3.3V Signaling */
+#define   SDHC_HC2R_VS18EN_S18V_Val       _U_(0x1)   /**< \brief (SDHC_HC2R) 1.8V Signaling */
+#define SDHC_HC2R_VS18EN_S33V       (SDHC_HC2R_VS18EN_S33V_Val     << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_VS18EN_S18V       (SDHC_HC2R_VS18EN_S18V_Val     << SDHC_HC2R_VS18EN_Pos)
+#define SDHC_HC2R_DRVSEL_Pos        4            /**< \brief (SDHC_HC2R) Driver Strength Select */
+#define SDHC_HC2R_DRVSEL_Msk        (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL(value)     (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))
+#define   SDHC_HC2R_DRVSEL_B_Val          _U_(0x0)   /**< \brief (SDHC_HC2R) Driver Type B is Selected (Default) */
+#define   SDHC_HC2R_DRVSEL_A_Val          _U_(0x1)   /**< \brief (SDHC_HC2R) Driver Type A is Selected */
+#define   SDHC_HC2R_DRVSEL_C_Val          _U_(0x2)   /**< \brief (SDHC_HC2R) Driver Type C is Selected */
+#define   SDHC_HC2R_DRVSEL_D_Val          _U_(0x3)   /**< \brief (SDHC_HC2R) Driver Type D is Selected */
+#define SDHC_HC2R_DRVSEL_B          (SDHC_HC2R_DRVSEL_B_Val        << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_A          (SDHC_HC2R_DRVSEL_A_Val        << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_C          (SDHC_HC2R_DRVSEL_C_Val        << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_DRVSEL_D          (SDHC_HC2R_DRVSEL_D_Val        << SDHC_HC2R_DRVSEL_Pos)
+#define SDHC_HC2R_EXTUN_Pos         6            /**< \brief (SDHC_HC2R) Execute Tuning */
+#define SDHC_HC2R_EXTUN             (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)
+#define   SDHC_HC2R_EXTUN_NO_Val          _U_(0x0)   /**< \brief (SDHC_HC2R) Not Tuned or Tuning Completed */
+#define   SDHC_HC2R_EXTUN_REQUESTED_Val   _U_(0x1)   /**< \brief (SDHC_HC2R) Execute Tuning */
+#define SDHC_HC2R_EXTUN_NO          (SDHC_HC2R_EXTUN_NO_Val        << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_EXTUN_REQUESTED   (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)
+#define SDHC_HC2R_SLCKSEL_Pos       7            /**< \brief (SDHC_HC2R) Sampling Clock Select */
+#define SDHC_HC2R_SLCKSEL           (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)
+#define   SDHC_HC2R_SLCKSEL_FIXED_Val     _U_(0x0)   /**< \brief (SDHC_HC2R) Fixed clock is used to sample data */
+#define   SDHC_HC2R_SLCKSEL_TUNED_Val     _U_(0x1)   /**< \brief (SDHC_HC2R) Tuned clock is used to sample data */
+#define SDHC_HC2R_SLCKSEL_FIXED     (SDHC_HC2R_SLCKSEL_FIXED_Val   << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_SLCKSEL_TUNED     (SDHC_HC2R_SLCKSEL_TUNED_Val   << SDHC_HC2R_SLCKSEL_Pos)
+#define SDHC_HC2R_ASINTEN_Pos       14           /**< \brief (SDHC_HC2R) Asynchronous Interrupt Enable */
+#define SDHC_HC2R_ASINTEN           (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)
+#define   SDHC_HC2R_ASINTEN_DISABLED_Val  _U_(0x0)   /**< \brief (SDHC_HC2R) Disabled */
+#define   SDHC_HC2R_ASINTEN_ENABLED_Val   _U_(0x1)   /**< \brief (SDHC_HC2R) Enabled */
+#define SDHC_HC2R_ASINTEN_DISABLED  (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_ASINTEN_ENABLED   (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)
+#define SDHC_HC2R_PVALEN_Pos        15           /**< \brief (SDHC_HC2R) Preset Value Enable */
+#define SDHC_HC2R_PVALEN            (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)
+#define   SDHC_HC2R_PVALEN_HOST_Val       _U_(0x0)   /**< \brief (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */
+#define   SDHC_HC2R_PVALEN_AUTO_Val       _U_(0x1)   /**< \brief (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */
+#define SDHC_HC2R_PVALEN_HOST       (SDHC_HC2R_PVALEN_HOST_Val     << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_PVALEN_AUTO       (SDHC_HC2R_PVALEN_AUTO_Val     << SDHC_HC2R_PVALEN_Pos)
+#define SDHC_HC2R_MASK              _U_(0xC0FF)  /**< \brief (SDHC_HC2R) MASK Register */
+
+// EMMC mode
+#define SDHC_HC2R_EMMC_HS200EN_Pos  0            /**< \brief (SDHC_HC2R_EMMC) HS200 Mode Enable */
+#define SDHC_HC2R_EMMC_HS200EN_Msk  (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))
+#define   SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) SDR12 */
+#define   SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) SDR25 */
+#define   SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2)   /**< \brief (SDHC_HC2R_EMMC) SDR50 */
+#define   SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3)   /**< \brief (SDHC_HC2R_EMMC) SDR104 */
+#define   SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4)   /**< \brief (SDHC_HC2R_EMMC) DDR50 */
+#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_Pos   4            /**< \brief (SDHC_HC2R_EMMC) Driver Strength Select */
+#define SDHC_HC2R_EMMC_DRVSEL_Msk   (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))
+#define   SDHC_HC2R_EMMC_DRVSEL_B_Val     _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) Driver Type B is Selected (Default) */
+#define   SDHC_HC2R_EMMC_DRVSEL_A_Val     _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Driver Type A is Selected */
+#define   SDHC_HC2R_EMMC_DRVSEL_C_Val     _U_(0x2)   /**< \brief (SDHC_HC2R_EMMC) Driver Type C is Selected */
+#define   SDHC_HC2R_EMMC_DRVSEL_D_Val     _U_(0x3)   /**< \brief (SDHC_HC2R_EMMC) Driver Type D is Selected */
+#define SDHC_HC2R_EMMC_DRVSEL_B     (SDHC_HC2R_EMMC_DRVSEL_B_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_A     (SDHC_HC2R_EMMC_DRVSEL_A_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_C     (SDHC_HC2R_EMMC_DRVSEL_C_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_DRVSEL_D     (SDHC_HC2R_EMMC_DRVSEL_D_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_Pos    6            /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
+#define SDHC_HC2R_EMMC_EXTUN        (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define   SDHC_HC2R_EMMC_EXTUN_NO_Val     _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) Not Tuned or Tuning Completed */
+#define   SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
+#define SDHC_HC2R_EMMC_EXTUN_NO     (SDHC_HC2R_EMMC_EXTUN_NO_Val   << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_Pos  7            /**< \brief (SDHC_HC2R_EMMC) Sampling Clock Select */
+#define SDHC_HC2R_EMMC_SLCKSEL      (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define   SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) Fixed clock is used to sample data */
+#define   SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Tuned clock is used to sample data */
+#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_Pos   15           /**< \brief (SDHC_HC2R_EMMC) Preset Value Enable */
+#define SDHC_HC2R_EMMC_PVALEN       (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define   SDHC_HC2R_EMMC_PVALEN_HOST_Val  _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) SDCLK and Driver Strength are controlled by Host Controller */
+#define   SDHC_HC2R_EMMC_PVALEN_AUTO_Val  _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Automatic Selection by Preset Value is Enabled */
+#define SDHC_HC2R_EMMC_PVALEN_HOST  (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_PVALEN_AUTO  (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
+#define SDHC_HC2R_EMMC_MASK         _U_(0x80FF)  /**< \brief (SDHC_HC2R_EMMC) MASK Register */
+
+/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/  32) Capabilities 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t TEOCLKF:6;        /*!< bit:  0.. 5  Timeout Clock Frequency            */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t TEOCLKU:1;        /*!< bit:      7  Timeout Clock Unit                 */
+    uint32_t BASECLKF:8;       /*!< bit:  8..15  Base Clock Frequency               */
+    uint32_t MAXBLKL:2;        /*!< bit: 16..17  Max Block Length                   */
+    uint32_t ED8SUP:1;         /*!< bit:     18  8-bit Support for Embedded Device  */
+    uint32_t ADMA2SUP:1;       /*!< bit:     19  ADMA2 Support                      */
+    uint32_t :1;               /*!< bit:     20  Reserved                           */
+    uint32_t HSSUP:1;          /*!< bit:     21  High Speed Support                 */
+    uint32_t SDMASUP:1;        /*!< bit:     22  SDMA Support                       */
+    uint32_t SRSUP:1;          /*!< bit:     23  Suspend/Resume Support             */
+    uint32_t V33VSUP:1;        /*!< bit:     24  Voltage Support 3.3V               */
+    uint32_t V30VSUP:1;        /*!< bit:     25  Voltage Support 3.0V               */
+    uint32_t V18VSUP:1;        /*!< bit:     26  Voltage Support 1.8V               */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t SB64SUP:1;        /*!< bit:     28  64-Bit System Bus Support          */
+    uint32_t ASINTSUP:1;       /*!< bit:     29  Asynchronous Interrupt Support     */
+    uint32_t SLTYPE:2;         /*!< bit: 30..31  Slot Type                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_CA0R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CA0R_OFFSET            0x040        /**< \brief (SDHC_CA0R offset) Capabilities 0 */
+#define SDHC_CA0R_RESETVALUE        _U_(0x27E80080) /**< \brief (SDHC_CA0R reset_value) Capabilities 0 */
+
+#define SDHC_CA0R_TEOCLKF_Pos       0            /**< \brief (SDHC_CA0R) Timeout Clock Frequency */
+#define SDHC_CA0R_TEOCLKF_Msk       (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)
+#define SDHC_CA0R_TEOCLKF(value)    (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))
+#define   SDHC_CA0R_TEOCLKF_OTHER_Val     _U_(0x0)   /**< \brief (SDHC_CA0R) Get information via another method */
+#define SDHC_CA0R_TEOCLKF_OTHER     (SDHC_CA0R_TEOCLKF_OTHER_Val   << SDHC_CA0R_TEOCLKF_Pos)
+#define SDHC_CA0R_TEOCLKU_Pos       7            /**< \brief (SDHC_CA0R) Timeout Clock Unit */
+#define SDHC_CA0R_TEOCLKU           (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)
+#define   SDHC_CA0R_TEOCLKU_KHZ_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) kHz */
+#define   SDHC_CA0R_TEOCLKU_MHZ_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) MHz */
+#define SDHC_CA0R_TEOCLKU_KHZ       (SDHC_CA0R_TEOCLKU_KHZ_Val     << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_TEOCLKU_MHZ       (SDHC_CA0R_TEOCLKU_MHZ_Val     << SDHC_CA0R_TEOCLKU_Pos)
+#define SDHC_CA0R_BASECLKF_Pos      8            /**< \brief (SDHC_CA0R) Base Clock Frequency */
+#define SDHC_CA0R_BASECLKF_Msk      (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)
+#define SDHC_CA0R_BASECLKF(value)   (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))
+#define   SDHC_CA0R_BASECLKF_OTHER_Val    _U_(0x0)   /**< \brief (SDHC_CA0R) Get information via another method */
+#define SDHC_CA0R_BASECLKF_OTHER    (SDHC_CA0R_BASECLKF_OTHER_Val  << SDHC_CA0R_BASECLKF_Pos)
+#define SDHC_CA0R_MAXBLKL_Pos       16           /**< \brief (SDHC_CA0R) Max Block Length */
+#define SDHC_CA0R_MAXBLKL_Msk       (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL(value)    (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))
+#define   SDHC_CA0R_MAXBLKL_512_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) 512 bytes */
+#define   SDHC_CA0R_MAXBLKL_1024_Val      _U_(0x1)   /**< \brief (SDHC_CA0R) 1024 bytes */
+#define   SDHC_CA0R_MAXBLKL_2048_Val      _U_(0x2)   /**< \brief (SDHC_CA0R) 2048 bytes */
+#define SDHC_CA0R_MAXBLKL_512       (SDHC_CA0R_MAXBLKL_512_Val     << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL_1024      (SDHC_CA0R_MAXBLKL_1024_Val    << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_MAXBLKL_2048      (SDHC_CA0R_MAXBLKL_2048_Val    << SDHC_CA0R_MAXBLKL_Pos)
+#define SDHC_CA0R_ED8SUP_Pos        18           /**< \brief (SDHC_CA0R) 8-bit Support for Embedded Device */
+#define SDHC_CA0R_ED8SUP            (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)
+#define   SDHC_CA0R_ED8SUP_NO_Val         _U_(0x0)   /**< \brief (SDHC_CA0R) 8-bit Bus Width not Supported */
+#define   SDHC_CA0R_ED8SUP_YES_Val        _U_(0x1)   /**< \brief (SDHC_CA0R) 8-bit Bus Width Supported */
+#define SDHC_CA0R_ED8SUP_NO         (SDHC_CA0R_ED8SUP_NO_Val       << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ED8SUP_YES        (SDHC_CA0R_ED8SUP_YES_Val      << SDHC_CA0R_ED8SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_Pos      19           /**< \brief (SDHC_CA0R) ADMA2 Support */
+#define SDHC_CA0R_ADMA2SUP          (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)
+#define   SDHC_CA0R_ADMA2SUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) ADMA2 not Supported */
+#define   SDHC_CA0R_ADMA2SUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA0R) ADMA2 Supported */
+#define SDHC_CA0R_ADMA2SUP_NO       (SDHC_CA0R_ADMA2SUP_NO_Val     << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_ADMA2SUP_YES      (SDHC_CA0R_ADMA2SUP_YES_Val    << SDHC_CA0R_ADMA2SUP_Pos)
+#define SDHC_CA0R_HSSUP_Pos         21           /**< \brief (SDHC_CA0R) High Speed Support */
+#define SDHC_CA0R_HSSUP             (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)
+#define   SDHC_CA0R_HSSUP_NO_Val          _U_(0x0)   /**< \brief (SDHC_CA0R) High Speed not Supported */
+#define   SDHC_CA0R_HSSUP_YES_Val         _U_(0x1)   /**< \brief (SDHC_CA0R) High Speed Supported */
+#define SDHC_CA0R_HSSUP_NO          (SDHC_CA0R_HSSUP_NO_Val        << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_HSSUP_YES         (SDHC_CA0R_HSSUP_YES_Val       << SDHC_CA0R_HSSUP_Pos)
+#define SDHC_CA0R_SDMASUP_Pos       22           /**< \brief (SDHC_CA0R) SDMA Support */
+#define SDHC_CA0R_SDMASUP           (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)
+#define   SDHC_CA0R_SDMASUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) SDMA not Supported */
+#define   SDHC_CA0R_SDMASUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) SDMA Supported */
+#define SDHC_CA0R_SDMASUP_NO        (SDHC_CA0R_SDMASUP_NO_Val      << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SDMASUP_YES       (SDHC_CA0R_SDMASUP_YES_Val     << SDHC_CA0R_SDMASUP_Pos)
+#define SDHC_CA0R_SRSUP_Pos         23           /**< \brief (SDHC_CA0R) Suspend/Resume Support */
+#define SDHC_CA0R_SRSUP             (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)
+#define   SDHC_CA0R_SRSUP_NO_Val          _U_(0x0)   /**< \brief (SDHC_CA0R) Suspend/Resume not Supported */
+#define   SDHC_CA0R_SRSUP_YES_Val         _U_(0x1)   /**< \brief (SDHC_CA0R) Suspend/Resume Supported */
+#define SDHC_CA0R_SRSUP_NO          (SDHC_CA0R_SRSUP_NO_Val        << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_SRSUP_YES         (SDHC_CA0R_SRSUP_YES_Val       << SDHC_CA0R_SRSUP_Pos)
+#define SDHC_CA0R_V33VSUP_Pos       24           /**< \brief (SDHC_CA0R) Voltage Support 3.3V */
+#define SDHC_CA0R_V33VSUP           (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)
+#define   SDHC_CA0R_V33VSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 3.3V Not Supported */
+#define   SDHC_CA0R_V33VSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 3.3V Supported */
+#define SDHC_CA0R_V33VSUP_NO        (SDHC_CA0R_V33VSUP_NO_Val      << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V33VSUP_YES       (SDHC_CA0R_V33VSUP_YES_Val     << SDHC_CA0R_V33VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_Pos       25           /**< \brief (SDHC_CA0R) Voltage Support 3.0V */
+#define SDHC_CA0R_V30VSUP           (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)
+#define   SDHC_CA0R_V30VSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 3.0V Not Supported */
+#define   SDHC_CA0R_V30VSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 3.0V Supported */
+#define SDHC_CA0R_V30VSUP_NO        (SDHC_CA0R_V30VSUP_NO_Val      << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V30VSUP_YES       (SDHC_CA0R_V30VSUP_YES_Val     << SDHC_CA0R_V30VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_Pos       26           /**< \brief (SDHC_CA0R) Voltage Support 1.8V */
+#define SDHC_CA0R_V18VSUP           (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)
+#define   SDHC_CA0R_V18VSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 1.8V Not Supported */
+#define   SDHC_CA0R_V18VSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 1.8V Supported */
+#define SDHC_CA0R_V18VSUP_NO        (SDHC_CA0R_V18VSUP_NO_Val      << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_V18VSUP_YES       (SDHC_CA0R_V18VSUP_YES_Val     << SDHC_CA0R_V18VSUP_Pos)
+#define SDHC_CA0R_SB64SUP_Pos       28           /**< \brief (SDHC_CA0R) 64-Bit System Bus Support */
+#define SDHC_CA0R_SB64SUP           (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)
+#define   SDHC_CA0R_SB64SUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 32-bit Address Descriptors and System Bus */
+#define   SDHC_CA0R_SB64SUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 64-bit Address Descriptors and System Bus */
+#define SDHC_CA0R_SB64SUP_NO        (SDHC_CA0R_SB64SUP_NO_Val      << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_SB64SUP_YES       (SDHC_CA0R_SB64SUP_YES_Val     << SDHC_CA0R_SB64SUP_Pos)
+#define SDHC_CA0R_ASINTSUP_Pos      29           /**< \brief (SDHC_CA0R) Asynchronous Interrupt Support */
+#define SDHC_CA0R_ASINTSUP          (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)
+#define   SDHC_CA0R_ASINTSUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) Asynchronous Interrupt not Supported */
+#define   SDHC_CA0R_ASINTSUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA0R) Asynchronous Interrupt supported */
+#define SDHC_CA0R_ASINTSUP_NO       (SDHC_CA0R_ASINTSUP_NO_Val     << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_ASINTSUP_YES      (SDHC_CA0R_ASINTSUP_YES_Val    << SDHC_CA0R_ASINTSUP_Pos)
+#define SDHC_CA0R_SLTYPE_Pos        30           /**< \brief (SDHC_CA0R) Slot Type */
+#define SDHC_CA0R_SLTYPE_Msk        (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_SLTYPE(value)     (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))
+#define   SDHC_CA0R_SLTYPE_REMOVABLE_Val  _U_(0x0)   /**< \brief (SDHC_CA0R) Removable Card Slot */
+#define   SDHC_CA0R_SLTYPE_EMBEDDED_Val   _U_(0x1)   /**< \brief (SDHC_CA0R) Embedded Slot for One Device */
+#define SDHC_CA0R_SLTYPE_REMOVABLE  (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_SLTYPE_EMBEDDED   (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)
+#define SDHC_CA0R_MASK              _U_(0xF7EFFFBF) /**< \brief (SDHC_CA0R) MASK Register */
+
+/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/  32) Capabilities 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SDR50SUP:1;       /*!< bit:      0  SDR50 Support                      */
+    uint32_t SDR104SUP:1;      /*!< bit:      1  SDR104 Support                     */
+    uint32_t DDR50SUP:1;       /*!< bit:      2  DDR50 Support                      */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t DRVASUP:1;        /*!< bit:      4  Driver Type A Support              */
+    uint32_t DRVCSUP:1;        /*!< bit:      5  Driver Type C Support              */
+    uint32_t DRVDSUP:1;        /*!< bit:      6  Driver Type D Support              */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t TCNTRT:4;         /*!< bit:  8..11  Timer Count for Re-Tuning          */
+    uint32_t :1;               /*!< bit:     12  Reserved                           */
+    uint32_t TSDR50:1;         /*!< bit:     13  Use Tuning for SDR50               */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t CLKMULT:8;        /*!< bit: 16..23  Clock Multiplier                   */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_CA1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CA1R_OFFSET            0x044        /**< \brief (SDHC_CA1R offset) Capabilities 1 */
+#define SDHC_CA1R_RESETVALUE        _U_(0x00000070) /**< \brief (SDHC_CA1R reset_value) Capabilities 1 */
+
+#define SDHC_CA1R_SDR50SUP_Pos      0            /**< \brief (SDHC_CA1R) SDR50 Support */
+#define SDHC_CA1R_SDR50SUP          (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)
+#define   SDHC_CA1R_SDR50SUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA1R) SDR50 is Not Supported */
+#define   SDHC_CA1R_SDR50SUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA1R) SDR50 is Supported */
+#define SDHC_CA1R_SDR50SUP_NO       (SDHC_CA1R_SDR50SUP_NO_Val     << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR50SUP_YES      (SDHC_CA1R_SDR50SUP_YES_Val    << SDHC_CA1R_SDR50SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_Pos     1            /**< \brief (SDHC_CA1R) SDR104 Support */
+#define SDHC_CA1R_SDR104SUP         (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)
+#define   SDHC_CA1R_SDR104SUP_NO_Val      _U_(0x0)   /**< \brief (SDHC_CA1R) SDR104 is Not Supported */
+#define   SDHC_CA1R_SDR104SUP_YES_Val     _U_(0x1)   /**< \brief (SDHC_CA1R) SDR104 is Supported */
+#define SDHC_CA1R_SDR104SUP_NO      (SDHC_CA1R_SDR104SUP_NO_Val    << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_SDR104SUP_YES     (SDHC_CA1R_SDR104SUP_YES_Val   << SDHC_CA1R_SDR104SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_Pos      2            /**< \brief (SDHC_CA1R) DDR50 Support */
+#define SDHC_CA1R_DDR50SUP          (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)
+#define   SDHC_CA1R_DDR50SUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA1R) DDR50 is Not Supported */
+#define   SDHC_CA1R_DDR50SUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA1R) DDR50 is Supported */
+#define SDHC_CA1R_DDR50SUP_NO       (SDHC_CA1R_DDR50SUP_NO_Val     << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DDR50SUP_YES      (SDHC_CA1R_DDR50SUP_YES_Val    << SDHC_CA1R_DDR50SUP_Pos)
+#define SDHC_CA1R_DRVASUP_Pos       4            /**< \brief (SDHC_CA1R) Driver Type A Support */
+#define SDHC_CA1R_DRVASUP           (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)
+#define   SDHC_CA1R_DRVASUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Driver Type A is Not Supported */
+#define   SDHC_CA1R_DRVASUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA1R) Driver Type A is Supported */
+#define SDHC_CA1R_DRVASUP_NO        (SDHC_CA1R_DRVASUP_NO_Val      << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVASUP_YES       (SDHC_CA1R_DRVASUP_YES_Val     << SDHC_CA1R_DRVASUP_Pos)
+#define SDHC_CA1R_DRVCSUP_Pos       5            /**< \brief (SDHC_CA1R) Driver Type C Support */
+#define SDHC_CA1R_DRVCSUP           (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)
+#define   SDHC_CA1R_DRVCSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Driver Type C is Not Supported */
+#define   SDHC_CA1R_DRVCSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA1R) Driver Type C is Supported */
+#define SDHC_CA1R_DRVCSUP_NO        (SDHC_CA1R_DRVCSUP_NO_Val      << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVCSUP_YES       (SDHC_CA1R_DRVCSUP_YES_Val     << SDHC_CA1R_DRVCSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_Pos       6            /**< \brief (SDHC_CA1R) Driver Type D Support */
+#define SDHC_CA1R_DRVDSUP           (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)
+#define   SDHC_CA1R_DRVDSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Driver Type D is Not Supported */
+#define   SDHC_CA1R_DRVDSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA1R) Driver Type D is Supported */
+#define SDHC_CA1R_DRVDSUP_NO        (SDHC_CA1R_DRVDSUP_NO_Val      << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_DRVDSUP_YES       (SDHC_CA1R_DRVDSUP_YES_Val     << SDHC_CA1R_DRVDSUP_Pos)
+#define SDHC_CA1R_TCNTRT_Pos        8            /**< \brief (SDHC_CA1R) Timer Count for Re-Tuning */
+#define SDHC_CA1R_TCNTRT_Msk        (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT(value)     (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))
+#define   SDHC_CA1R_TCNTRT_DISABLED_Val   _U_(0x0)   /**< \brief (SDHC_CA1R) Re-Tuning Timer disabled */
+#define   SDHC_CA1R_TCNTRT_1S_Val         _U_(0x1)   /**< \brief (SDHC_CA1R) 1 second */
+#define   SDHC_CA1R_TCNTRT_2S_Val         _U_(0x2)   /**< \brief (SDHC_CA1R) 2 seconds */
+#define   SDHC_CA1R_TCNTRT_4S_Val         _U_(0x3)   /**< \brief (SDHC_CA1R) 4 seconds */
+#define   SDHC_CA1R_TCNTRT_8S_Val         _U_(0x4)   /**< \brief (SDHC_CA1R) 8 seconds */
+#define   SDHC_CA1R_TCNTRT_16S_Val        _U_(0x5)   /**< \brief (SDHC_CA1R) 16 seconds */
+#define   SDHC_CA1R_TCNTRT_32S_Val        _U_(0x6)   /**< \brief (SDHC_CA1R) 32 seconds */
+#define   SDHC_CA1R_TCNTRT_64S_Val        _U_(0x7)   /**< \brief (SDHC_CA1R) 64 seconds */
+#define   SDHC_CA1R_TCNTRT_128S_Val       _U_(0x8)   /**< \brief (SDHC_CA1R) 128 seconds */
+#define   SDHC_CA1R_TCNTRT_256S_Val       _U_(0x9)   /**< \brief (SDHC_CA1R) 256 seconds */
+#define   SDHC_CA1R_TCNTRT_512S_Val       _U_(0xA)   /**< \brief (SDHC_CA1R) 512 seconds */
+#define   SDHC_CA1R_TCNTRT_1024S_Val      _U_(0xB)   /**< \brief (SDHC_CA1R) 1024 seconds */
+#define   SDHC_CA1R_TCNTRT_OTHER_Val      _U_(0xF)   /**< \brief (SDHC_CA1R) Get information from other source */
+#define SDHC_CA1R_TCNTRT_DISABLED   (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_1S         (SDHC_CA1R_TCNTRT_1S_Val       << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_2S         (SDHC_CA1R_TCNTRT_2S_Val       << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_4S         (SDHC_CA1R_TCNTRT_4S_Val       << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_8S         (SDHC_CA1R_TCNTRT_8S_Val       << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_16S        (SDHC_CA1R_TCNTRT_16S_Val      << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_32S        (SDHC_CA1R_TCNTRT_32S_Val      << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_64S        (SDHC_CA1R_TCNTRT_64S_Val      << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_128S       (SDHC_CA1R_TCNTRT_128S_Val     << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_256S       (SDHC_CA1R_TCNTRT_256S_Val     << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_512S       (SDHC_CA1R_TCNTRT_512S_Val     << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_1024S      (SDHC_CA1R_TCNTRT_1024S_Val    << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TCNTRT_OTHER      (SDHC_CA1R_TCNTRT_OTHER_Val    << SDHC_CA1R_TCNTRT_Pos)
+#define SDHC_CA1R_TSDR50_Pos        13           /**< \brief (SDHC_CA1R) Use Tuning for SDR50 */
+#define SDHC_CA1R_TSDR50            (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)
+#define   SDHC_CA1R_TSDR50_NO_Val         _U_(0x0)   /**< \brief (SDHC_CA1R) SDR50 does not require tuning */
+#define   SDHC_CA1R_TSDR50_YES_Val        _U_(0x1)   /**< \brief (SDHC_CA1R) SDR50 requires tuning */
+#define SDHC_CA1R_TSDR50_NO         (SDHC_CA1R_TSDR50_NO_Val       << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_TSDR50_YES        (SDHC_CA1R_TSDR50_YES_Val      << SDHC_CA1R_TSDR50_Pos)
+#define SDHC_CA1R_CLKMULT_Pos       16           /**< \brief (SDHC_CA1R) Clock Multiplier */
+#define SDHC_CA1R_CLKMULT_Msk       (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)
+#define SDHC_CA1R_CLKMULT(value)    (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))
+#define   SDHC_CA1R_CLKMULT_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Clock Multiplier is Not Supported */
+#define SDHC_CA1R_CLKMULT_NO        (SDHC_CA1R_CLKMULT_NO_Val      << SDHC_CA1R_CLKMULT_Pos)
+#define SDHC_CA1R_MASK              _U_(0x00FF2F77) /**< \brief (SDHC_CA1R) MASK Register */
+
+/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/  32) Maximum Current Capabilities -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MAXCUR33V:8;      /*!< bit:  0.. 7  Maximum Current for 3.3V           */
+    uint32_t MAXCUR30V:8;      /*!< bit:  8..15  Maximum Current for 3.0V           */
+    uint32_t MAXCUR18V:8;      /*!< bit: 16..23  Maximum Current for 1.8V           */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_MCCAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MCCAR_OFFSET           0x048        /**< \brief (SDHC_MCCAR offset) Maximum Current Capabilities */
+#define SDHC_MCCAR_RESETVALUE       _U_(0x00000000) /**< \brief (SDHC_MCCAR reset_value) Maximum Current Capabilities */
+
+#define SDHC_MCCAR_MAXCUR33V_Pos    0            /**< \brief (SDHC_MCCAR) Maximum Current for 3.3V */
+#define SDHC_MCCAR_MAXCUR33V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))
+#define   SDHC_MCCAR_MAXCUR33V_OTHER_Val  _U_(0x0)   /**< \brief (SDHC_MCCAR) Get information via another method */
+#define   SDHC_MCCAR_MAXCUR33V_4MA_Val    _U_(0x1)   /**< \brief (SDHC_MCCAR) 4mA */
+#define   SDHC_MCCAR_MAXCUR33V_8MA_Val    _U_(0x2)   /**< \brief (SDHC_MCCAR) 8mA */
+#define   SDHC_MCCAR_MAXCUR33V_12MA_Val   _U_(0x3)   /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR33V_OTHER  (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_4MA    (SDHC_MCCAR_MAXCUR33V_4MA_Val  << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_8MA    (SDHC_MCCAR_MAXCUR33V_8MA_Val  << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR33V_12MA   (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_Pos    8            /**< \brief (SDHC_MCCAR) Maximum Current for 3.0V */
+#define SDHC_MCCAR_MAXCUR30V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))
+#define   SDHC_MCCAR_MAXCUR30V_OTHER_Val  _U_(0x0)   /**< \brief (SDHC_MCCAR) Get information via another method */
+#define   SDHC_MCCAR_MAXCUR30V_4MA_Val    _U_(0x1)   /**< \brief (SDHC_MCCAR) 4mA */
+#define   SDHC_MCCAR_MAXCUR30V_8MA_Val    _U_(0x2)   /**< \brief (SDHC_MCCAR) 8mA */
+#define   SDHC_MCCAR_MAXCUR30V_12MA_Val   _U_(0x3)   /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR30V_OTHER  (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_4MA    (SDHC_MCCAR_MAXCUR30V_4MA_Val  << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_8MA    (SDHC_MCCAR_MAXCUR30V_8MA_Val  << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR30V_12MA   (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_Pos    16           /**< \brief (SDHC_MCCAR) Maximum Current for 1.8V */
+#define SDHC_MCCAR_MAXCUR18V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))
+#define   SDHC_MCCAR_MAXCUR18V_OTHER_Val  _U_(0x0)   /**< \brief (SDHC_MCCAR) Get information via another method */
+#define   SDHC_MCCAR_MAXCUR18V_4MA_Val    _U_(0x1)   /**< \brief (SDHC_MCCAR) 4mA */
+#define   SDHC_MCCAR_MAXCUR18V_8MA_Val    _U_(0x2)   /**< \brief (SDHC_MCCAR) 8mA */
+#define   SDHC_MCCAR_MAXCUR18V_12MA_Val   _U_(0x3)   /**< \brief (SDHC_MCCAR) 12mA */
+#define SDHC_MCCAR_MAXCUR18V_OTHER  (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_4MA    (SDHC_MCCAR_MAXCUR18V_4MA_Val  << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_8MA    (SDHC_MCCAR_MAXCUR18V_8MA_Val  << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MAXCUR18V_12MA   (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
+#define SDHC_MCCAR_MASK             _U_(0x00FFFFFF) /**< \brief (SDHC_MCCAR) MASK Register */
+
+/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t ACMD12NE:1;       /*!< bit:      0  Force Event for Auto CMD12 Not Executed */
+    uint16_t ACMDTEO:1;        /*!< bit:      1  Force Event for Auto CMD Timeout Error */
+    uint16_t ACMDCRC:1;        /*!< bit:      2  Force Event for Auto CMD CRC Error */
+    uint16_t ACMDEND:1;        /*!< bit:      3  Force Event for Auto CMD End Bit Error */
+    uint16_t ACMDIDX:1;        /*!< bit:      4  Force Event for Auto CMD Index Error */
+    uint16_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint16_t CMDNI:1;          /*!< bit:      7  Force Event for Command Not Issued By Auto CMD12 Error */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_FERACES_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_FERACES_OFFSET         0x050        /**< \brief (SDHC_FERACES offset) Force Event for Auto CMD Error Status */
+#define SDHC_FERACES_RESETVALUE     _U_(0x0000)  /**< \brief (SDHC_FERACES reset_value) Force Event for Auto CMD Error Status */
+
+#define SDHC_FERACES_ACMD12NE_Pos   0            /**< \brief (SDHC_FERACES) Force Event for Auto CMD12 Not Executed */
+#define SDHC_FERACES_ACMD12NE       (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)
+#define   SDHC_FERACES_ACMD12NE_NO_Val    _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
+#define   SDHC_FERACES_ACMD12NE_YES_Val   _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMD12NE_NO    (SDHC_FERACES_ACMD12NE_NO_Val  << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMD12NE_YES   (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)
+#define SDHC_FERACES_ACMDTEO_Pos    1            /**< \brief (SDHC_FERACES) Force Event for Auto CMD Timeout Error */
+#define SDHC_FERACES_ACMDTEO        (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)
+#define   SDHC_FERACES_ACMDTEO_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
+#define   SDHC_FERACES_ACMDTEO_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDTEO_NO     (SDHC_FERACES_ACMDTEO_NO_Val   << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDTEO_YES    (SDHC_FERACES_ACMDTEO_YES_Val  << SDHC_FERACES_ACMDTEO_Pos)
+#define SDHC_FERACES_ACMDCRC_Pos    2            /**< \brief (SDHC_FERACES) Force Event for Auto CMD CRC Error */
+#define SDHC_FERACES_ACMDCRC        (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)
+#define   SDHC_FERACES_ACMDCRC_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
+#define   SDHC_FERACES_ACMDCRC_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDCRC_NO     (SDHC_FERACES_ACMDCRC_NO_Val   << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDCRC_YES    (SDHC_FERACES_ACMDCRC_YES_Val  << SDHC_FERACES_ACMDCRC_Pos)
+#define SDHC_FERACES_ACMDEND_Pos    3            /**< \brief (SDHC_FERACES) Force Event for Auto CMD End Bit Error */
+#define SDHC_FERACES_ACMDEND        (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)
+#define   SDHC_FERACES_ACMDEND_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
+#define   SDHC_FERACES_ACMDEND_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDEND_NO     (SDHC_FERACES_ACMDEND_NO_Val   << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDEND_YES    (SDHC_FERACES_ACMDEND_YES_Val  << SDHC_FERACES_ACMDEND_Pos)
+#define SDHC_FERACES_ACMDIDX_Pos    4            /**< \brief (SDHC_FERACES) Force Event for Auto CMD Index Error */
+#define SDHC_FERACES_ACMDIDX        (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)
+#define   SDHC_FERACES_ACMDIDX_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
+#define   SDHC_FERACES_ACMDIDX_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_ACMDIDX_NO     (SDHC_FERACES_ACMDIDX_NO_Val   << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_ACMDIDX_YES    (SDHC_FERACES_ACMDIDX_YES_Val  << SDHC_FERACES_ACMDIDX_Pos)
+#define SDHC_FERACES_CMDNI_Pos      7            /**< \brief (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error */
+#define SDHC_FERACES_CMDNI          (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)
+#define   SDHC_FERACES_CMDNI_NO_Val       _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
+#define   SDHC_FERACES_CMDNI_YES_Val      _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
+#define SDHC_FERACES_CMDNI_NO       (SDHC_FERACES_CMDNI_NO_Val     << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_CMDNI_YES      (SDHC_FERACES_CMDNI_YES_Val    << SDHC_FERACES_CMDNI_Pos)
+#define SDHC_FERACES_MASK           _U_(0x009F)  /**< \brief (SDHC_FERACES) MASK Register */
+
+/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMDTEO:1;         /*!< bit:      0  Force Event for Command Timeout Error */
+    uint16_t CMDCRC:1;         /*!< bit:      1  Force Event for Command CRC Error  */
+    uint16_t CMDEND:1;         /*!< bit:      2  Force Event for Command End Bit Error */
+    uint16_t CMDIDX:1;         /*!< bit:      3  Force Event for Command Index Error */
+    uint16_t DATTEO:1;         /*!< bit:      4  Force Event for Data Timeout Error */
+    uint16_t DATCRC:1;         /*!< bit:      5  Force Event for Data CRC Error     */
+    uint16_t DATEND:1;         /*!< bit:      6  Force Event for Data End Bit Error */
+    uint16_t CURLIM:1;         /*!< bit:      7  Force Event for Current Limit Error */
+    uint16_t ACMD:1;           /*!< bit:      8  Force Event for Auto CMD Error     */
+    uint16_t ADMA:1;           /*!< bit:      9  Force Event for ADMA Error         */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t BOOTAE:1;         /*!< bit:     12  Force Event for Boot Acknowledge Error */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_FEREIS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_FEREIS_OFFSET          0x052        /**< \brief (SDHC_FEREIS offset) Force Event for Error Interrupt Status */
+#define SDHC_FEREIS_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_FEREIS reset_value) Force Event for Error Interrupt Status */
+
+#define SDHC_FEREIS_CMDTEO_Pos      0            /**< \brief (SDHC_FEREIS) Force Event for Command Timeout Error */
+#define SDHC_FEREIS_CMDTEO          (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)
+#define   SDHC_FEREIS_CMDTEO_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_CMDTEO_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDTEO_NO       (SDHC_FEREIS_CMDTEO_NO_Val     << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDTEO_YES      (SDHC_FEREIS_CMDTEO_YES_Val    << SDHC_FEREIS_CMDTEO_Pos)
+#define SDHC_FEREIS_CMDCRC_Pos      1            /**< \brief (SDHC_FEREIS) Force Event for Command CRC Error */
+#define SDHC_FEREIS_CMDCRC          (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)
+#define   SDHC_FEREIS_CMDCRC_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_CMDCRC_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDCRC_NO       (SDHC_FEREIS_CMDCRC_NO_Val     << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDCRC_YES      (SDHC_FEREIS_CMDCRC_YES_Val    << SDHC_FEREIS_CMDCRC_Pos)
+#define SDHC_FEREIS_CMDEND_Pos      2            /**< \brief (SDHC_FEREIS) Force Event for Command End Bit Error */
+#define SDHC_FEREIS_CMDEND          (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)
+#define   SDHC_FEREIS_CMDEND_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_CMDEND_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDEND_NO       (SDHC_FEREIS_CMDEND_NO_Val     << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDEND_YES      (SDHC_FEREIS_CMDEND_YES_Val    << SDHC_FEREIS_CMDEND_Pos)
+#define SDHC_FEREIS_CMDIDX_Pos      3            /**< \brief (SDHC_FEREIS) Force Event for Command Index Error */
+#define SDHC_FEREIS_CMDIDX          (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)
+#define   SDHC_FEREIS_CMDIDX_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_CMDIDX_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CMDIDX_NO       (SDHC_FEREIS_CMDIDX_NO_Val     << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_CMDIDX_YES      (SDHC_FEREIS_CMDIDX_YES_Val    << SDHC_FEREIS_CMDIDX_Pos)
+#define SDHC_FEREIS_DATTEO_Pos      4            /**< \brief (SDHC_FEREIS) Force Event for Data Timeout Error */
+#define SDHC_FEREIS_DATTEO          (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)
+#define   SDHC_FEREIS_DATTEO_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_DATTEO_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATTEO_NO       (SDHC_FEREIS_DATTEO_NO_Val     << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATTEO_YES      (SDHC_FEREIS_DATTEO_YES_Val    << SDHC_FEREIS_DATTEO_Pos)
+#define SDHC_FEREIS_DATCRC_Pos      5            /**< \brief (SDHC_FEREIS) Force Event for Data CRC Error */
+#define SDHC_FEREIS_DATCRC          (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)
+#define   SDHC_FEREIS_DATCRC_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_DATCRC_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATCRC_NO       (SDHC_FEREIS_DATCRC_NO_Val     << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATCRC_YES      (SDHC_FEREIS_DATCRC_YES_Val    << SDHC_FEREIS_DATCRC_Pos)
+#define SDHC_FEREIS_DATEND_Pos      6            /**< \brief (SDHC_FEREIS) Force Event for Data End Bit Error */
+#define SDHC_FEREIS_DATEND          (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)
+#define   SDHC_FEREIS_DATEND_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_DATEND_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_DATEND_NO       (SDHC_FEREIS_DATEND_NO_Val     << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_DATEND_YES      (SDHC_FEREIS_DATEND_YES_Val    << SDHC_FEREIS_DATEND_Pos)
+#define SDHC_FEREIS_CURLIM_Pos      7            /**< \brief (SDHC_FEREIS) Force Event for Current Limit Error */
+#define SDHC_FEREIS_CURLIM          (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)
+#define   SDHC_FEREIS_CURLIM_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_CURLIM_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_CURLIM_NO       (SDHC_FEREIS_CURLIM_NO_Val     << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_CURLIM_YES      (SDHC_FEREIS_CURLIM_YES_Val    << SDHC_FEREIS_CURLIM_Pos)
+#define SDHC_FEREIS_ACMD_Pos        8            /**< \brief (SDHC_FEREIS) Force Event for Auto CMD Error */
+#define SDHC_FEREIS_ACMD            (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)
+#define   SDHC_FEREIS_ACMD_NO_Val         _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_ACMD_YES_Val        _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_ACMD_NO         (SDHC_FEREIS_ACMD_NO_Val       << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ACMD_YES        (SDHC_FEREIS_ACMD_YES_Val      << SDHC_FEREIS_ACMD_Pos)
+#define SDHC_FEREIS_ADMA_Pos        9            /**< \brief (SDHC_FEREIS) Force Event for ADMA Error */
+#define SDHC_FEREIS_ADMA            (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)
+#define   SDHC_FEREIS_ADMA_NO_Val         _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_ADMA_YES_Val        _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_ADMA_NO         (SDHC_FEREIS_ADMA_NO_Val       << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_ADMA_YES        (SDHC_FEREIS_ADMA_YES_Val      << SDHC_FEREIS_ADMA_Pos)
+#define SDHC_FEREIS_BOOTAE_Pos      12           /**< \brief (SDHC_FEREIS) Force Event for Boot Acknowledge Error */
+#define SDHC_FEREIS_BOOTAE          (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)
+#define   SDHC_FEREIS_BOOTAE_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
+#define   SDHC_FEREIS_BOOTAE_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
+#define SDHC_FEREIS_BOOTAE_NO       (SDHC_FEREIS_BOOTAE_NO_Val     << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_BOOTAE_YES      (SDHC_FEREIS_BOOTAE_YES_Val    << SDHC_FEREIS_BOOTAE_Pos)
+#define SDHC_FEREIS_MASK            _U_(0x13FF)  /**< \brief (SDHC_FEREIS) MASK Register */
+
+/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/   8) ADMA Error Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERRST:2;          /*!< bit:  0.. 1  ADMA Error State                   */
+    uint8_t  LMIS:1;           /*!< bit:      2  ADMA Length Mismatch Error         */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_AESR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_AESR_OFFSET            0x054        /**< \brief (SDHC_AESR offset) ADMA Error Status */
+#define SDHC_AESR_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_AESR reset_value) ADMA Error Status */
+
+#define SDHC_AESR_ERRST_Pos         0            /**< \brief (SDHC_AESR) ADMA Error State */
+#define SDHC_AESR_ERRST_Msk         (_U_(0x3) << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST(value)      (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))
+#define   SDHC_AESR_ERRST_STOP_Val        _U_(0x0)   /**< \brief (SDHC_AESR) ST_STOP (Stop DMA) */
+#define   SDHC_AESR_ERRST_FDS_Val         _U_(0x1)   /**< \brief (SDHC_AESR) ST_FDS (Fetch Descriptor) */
+#define   SDHC_AESR_ERRST_2_Val           _U_(0x2)   /**< \brief (SDHC_AESR) Reserved */
+#define   SDHC_AESR_ERRST_TFR_Val         _U_(0x3)   /**< \brief (SDHC_AESR) ST_TFR (Transfer Data) */
+#define SDHC_AESR_ERRST_STOP        (SDHC_AESR_ERRST_STOP_Val      << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_FDS         (SDHC_AESR_ERRST_FDS_Val       << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_2           (SDHC_AESR_ERRST_2_Val         << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_ERRST_TFR         (SDHC_AESR_ERRST_TFR_Val       << SDHC_AESR_ERRST_Pos)
+#define SDHC_AESR_LMIS_Pos          2            /**< \brief (SDHC_AESR) ADMA Length Mismatch Error */
+#define SDHC_AESR_LMIS              (_U_(0x1) << SDHC_AESR_LMIS_Pos)
+#define   SDHC_AESR_LMIS_NO_Val           _U_(0x0)   /**< \brief (SDHC_AESR) No Error */
+#define   SDHC_AESR_LMIS_YES_Val          _U_(0x1)   /**< \brief (SDHC_AESR) Error */
+#define SDHC_AESR_LMIS_NO           (SDHC_AESR_LMIS_NO_Val         << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_LMIS_YES          (SDHC_AESR_LMIS_YES_Val        << SDHC_AESR_LMIS_Pos)
+#define SDHC_AESR_MASK              _U_(0x07)    /**< \brief (SDHC_AESR) MASK Register */
+
+/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADMASA:32;        /*!< bit:  0..31  ADMA System Address                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_ASAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ASAR_OFFSET            0x058        /**< \brief (SDHC_ASAR offset) ADMA System Address n */
+#define SDHC_ASAR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_ASAR reset_value) ADMA System Address n */
+
+#define SDHC_ASAR_ADMASA_Pos        0            /**< \brief (SDHC_ASAR) ADMA System Address */
+#define SDHC_ASAR_ADMASA_Msk        (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)
+#define SDHC_ASAR_ADMASA(value)     (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))
+#define SDHC_ASAR_MASK              _U_(0xFFFFFFFF) /**< \brief (SDHC_ASAR) MASK Register */
+
+/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SDCLKFSEL:10;     /*!< bit:  0.. 9  SDCLK Frequency Select Value for Initialization */
+    uint16_t CLKGSEL:1;        /*!< bit:     10  Clock Generator Select Value for Initialization */
+    uint16_t :3;               /*!< bit: 11..13  Reserved                           */
+    uint16_t DRVSEL:2;         /*!< bit: 14..15  Driver Strength Select Value for Initialization */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_PVR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_PVR_OFFSET             0x060        /**< \brief (SDHC_PVR offset) Preset Value n */
+#define SDHC_PVR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_PVR reset_value) Preset Value n */
+
+#define SDHC_PVR_SDCLKFSEL_Pos      0            /**< \brief (SDHC_PVR) SDCLK Frequency Select Value for Initialization */
+#define SDHC_PVR_SDCLKFSEL_Msk      (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)
+#define SDHC_PVR_SDCLKFSEL(value)   (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))
+#define SDHC_PVR_CLKGSEL_Pos        10           /**< \brief (SDHC_PVR) Clock Generator Select Value for Initialization */
+#define SDHC_PVR_CLKGSEL            (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)
+#define   SDHC_PVR_CLKGSEL_DIV_Val        _U_(0x0)   /**< \brief (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */
+#define   SDHC_PVR_CLKGSEL_PROG_Val       _U_(0x1)   /**< \brief (SDHC_PVR) Programmable Clock Generator */
+#define SDHC_PVR_CLKGSEL_DIV        (SDHC_PVR_CLKGSEL_DIV_Val      << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_CLKGSEL_PROG       (SDHC_PVR_CLKGSEL_PROG_Val     << SDHC_PVR_CLKGSEL_Pos)
+#define SDHC_PVR_DRVSEL_Pos         14           /**< \brief (SDHC_PVR) Driver Strength Select Value for Initialization */
+#define SDHC_PVR_DRVSEL_Msk         (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL(value)      (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))
+#define   SDHC_PVR_DRVSEL_B_Val           _U_(0x0)   /**< \brief (SDHC_PVR) Driver Type B is Selected */
+#define   SDHC_PVR_DRVSEL_A_Val           _U_(0x1)   /**< \brief (SDHC_PVR) Driver Type A is Selected */
+#define   SDHC_PVR_DRVSEL_C_Val           _U_(0x2)   /**< \brief (SDHC_PVR) Driver Type C is Selected */
+#define   SDHC_PVR_DRVSEL_D_Val           _U_(0x3)   /**< \brief (SDHC_PVR) Driver Type D is Selected */
+#define SDHC_PVR_DRVSEL_B           (SDHC_PVR_DRVSEL_B_Val         << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_A           (SDHC_PVR_DRVSEL_A_Val         << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_C           (SDHC_PVR_DRVSEL_C_Val         << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_DRVSEL_D           (SDHC_PVR_DRVSEL_D_Val         << SDHC_PVR_DRVSEL_Pos)
+#define SDHC_PVR_MASK               _U_(0xC7FF)  /**< \brief (SDHC_PVR) MASK Register */
+
+/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/  16) Slot Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t INTSSL:1;         /*!< bit:      0  Interrupt Signal for Each Slot     */
+    uint16_t :15;              /*!< bit:  1..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_SISR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_SISR_OFFSET            0x0FC        /**< \brief (SDHC_SISR offset) Slot Interrupt Status */
+#define SDHC_SISR_RESETVALUE        _U_(0x20000) /**< \brief (SDHC_SISR reset_value) Slot Interrupt Status */
+
+#define SDHC_SISR_INTSSL_Pos        0            /**< \brief (SDHC_SISR) Interrupt Signal for Each Slot */
+#define SDHC_SISR_INTSSL_Msk        (_U_(0x1) << SDHC_SISR_INTSSL_Pos)
+#define SDHC_SISR_INTSSL(value)     (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))
+#define SDHC_SISR_MASK              _U_(0x0001)  /**< \brief (SDHC_SISR) MASK Register */
+
+/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/  16) Host Controller Version -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SVER:8;           /*!< bit:  0.. 7  Spec Version                       */
+    uint16_t VVER:8;           /*!< bit:  8..15  Vendor Version                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SDHC_HCVR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_HCVR_OFFSET            0x0FE        /**< \brief (SDHC_HCVR offset) Host Controller Version */
+#define SDHC_HCVR_RESETVALUE        _U_(0x1802)  /**< \brief (SDHC_HCVR reset_value) Host Controller Version */
+
+#define SDHC_HCVR_SVER_Pos          0            /**< \brief (SDHC_HCVR) Spec Version */
+#define SDHC_HCVR_SVER_Msk          (_U_(0xFF) << SDHC_HCVR_SVER_Pos)
+#define SDHC_HCVR_SVER(value)       (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))
+#define SDHC_HCVR_VVER_Pos          8            /**< \brief (SDHC_HCVR) Vendor Version */
+#define SDHC_HCVR_VVER_Msk          (_U_(0xFF) << SDHC_HCVR_VVER_Pos)
+#define SDHC_HCVR_VVER(value)       (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))
+#define SDHC_HCVR_MASK              _U_(0xFFFF)  /**< \brief (SDHC_HCVR) MASK Register */
+
+/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W  8) MMC Control 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CMDTYP:2;         /*!< bit:  0.. 1  e.MMC Command Type                 */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  DDR:1;            /*!< bit:      3  e.MMC HSDDR Mode                   */
+    uint8_t  OPD:1;            /*!< bit:      4  e.MMC Open Drain Mode              */
+    uint8_t  BOOTA:1;          /*!< bit:      5  e.MMC Boot Acknowledge Enable      */
+    uint8_t  RSTN:1;           /*!< bit:      6  e.MMC Reset Signal                 */
+    uint8_t  FCD:1;            /*!< bit:      7  e.MMC Force Card Detect            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_MC1R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MC1R_OFFSET            0x204        /**< \brief (SDHC_MC1R offset) MMC Control 1 */
+#define SDHC_MC1R_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_MC1R reset_value) MMC Control 1 */
+
+#define SDHC_MC1R_CMDTYP_Pos        0            /**< \brief (SDHC_MC1R) e.MMC Command Type */
+#define SDHC_MC1R_CMDTYP_Msk        (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP(value)     (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))
+#define   SDHC_MC1R_CMDTYP_NORMAL_Val     _U_(0x0)   /**< \brief (SDHC_MC1R) Not a MMC specific command */
+#define   SDHC_MC1R_CMDTYP_WAITIRQ_Val    _U_(0x1)   /**< \brief (SDHC_MC1R) Wait IRQ Command */
+#define   SDHC_MC1R_CMDTYP_STREAM_Val     _U_(0x2)   /**< \brief (SDHC_MC1R) Stream Command */
+#define   SDHC_MC1R_CMDTYP_BOOT_Val       _U_(0x3)   /**< \brief (SDHC_MC1R) Boot Command */
+#define SDHC_MC1R_CMDTYP_NORMAL     (SDHC_MC1R_CMDTYP_NORMAL_Val   << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_WAITIRQ    (SDHC_MC1R_CMDTYP_WAITIRQ_Val  << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_STREAM     (SDHC_MC1R_CMDTYP_STREAM_Val   << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_CMDTYP_BOOT       (SDHC_MC1R_CMDTYP_BOOT_Val     << SDHC_MC1R_CMDTYP_Pos)
+#define SDHC_MC1R_DDR_Pos           3            /**< \brief (SDHC_MC1R) e.MMC HSDDR Mode */
+#define SDHC_MC1R_DDR               (_U_(0x1) << SDHC_MC1R_DDR_Pos)
+#define SDHC_MC1R_OPD_Pos           4            /**< \brief (SDHC_MC1R) e.MMC Open Drain Mode */
+#define SDHC_MC1R_OPD               (_U_(0x1) << SDHC_MC1R_OPD_Pos)
+#define SDHC_MC1R_BOOTA_Pos         5            /**< \brief (SDHC_MC1R) e.MMC Boot Acknowledge Enable */
+#define SDHC_MC1R_BOOTA             (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)
+#define SDHC_MC1R_RSTN_Pos          6            /**< \brief (SDHC_MC1R) e.MMC Reset Signal */
+#define SDHC_MC1R_RSTN              (_U_(0x1) << SDHC_MC1R_RSTN_Pos)
+#define SDHC_MC1R_FCD_Pos           7            /**< \brief (SDHC_MC1R) e.MMC Force Card Detect */
+#define SDHC_MC1R_FCD               (_U_(0x1) << SDHC_MC1R_FCD_Pos)
+#define SDHC_MC1R_MASK              _U_(0xFB)    /**< \brief (SDHC_MC1R) MASK Register */
+
+/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W  8) MMC Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SRESP:1;          /*!< bit:      0  e.MMC Abort Wait IRQ               */
+    uint8_t  ABOOT:1;          /*!< bit:      1  e.MMC Abort Boot                   */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_MC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_MC2R_OFFSET            0x205        /**< \brief (SDHC_MC2R offset) MMC Control 2 */
+#define SDHC_MC2R_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_MC2R reset_value) MMC Control 2 */
+
+#define SDHC_MC2R_SRESP_Pos         0            /**< \brief (SDHC_MC2R) e.MMC Abort Wait IRQ */
+#define SDHC_MC2R_SRESP             (_U_(0x1) << SDHC_MC2R_SRESP_Pos)
+#define SDHC_MC2R_ABOOT_Pos         1            /**< \brief (SDHC_MC2R) e.MMC Abort Boot */
+#define SDHC_MC2R_ABOOT             (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)
+#define SDHC_MC2R_MASK              _U_(0x03)    /**< \brief (SDHC_MC2R) MASK Register */
+
+/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BMAX:2;           /*!< bit:  0.. 1  AHB Maximum Burst                  */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_ACR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_ACR_OFFSET             0x208        /**< \brief (SDHC_ACR offset) AHB Control */
+#define SDHC_ACR_RESETVALUE         _U_(0x00000000) /**< \brief (SDHC_ACR reset_value) AHB Control */
+
+#define SDHC_ACR_BMAX_Pos           0            /**< \brief (SDHC_ACR) AHB Maximum Burst */
+#define SDHC_ACR_BMAX_Msk           (_U_(0x3) << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX(value)        (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))
+#define   SDHC_ACR_BMAX_INCR16_Val        _U_(0x0)   /**< \brief (SDHC_ACR)  */
+#define   SDHC_ACR_BMAX_INCR8_Val         _U_(0x1)   /**< \brief (SDHC_ACR)  */
+#define   SDHC_ACR_BMAX_INCR4_Val         _U_(0x2)   /**< \brief (SDHC_ACR)  */
+#define   SDHC_ACR_BMAX_SINGLE_Val        _U_(0x3)   /**< \brief (SDHC_ACR)  */
+#define SDHC_ACR_BMAX_INCR16        (SDHC_ACR_BMAX_INCR16_Val      << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_INCR8         (SDHC_ACR_BMAX_INCR8_Val       << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_INCR4         (SDHC_ACR_BMAX_INCR4_Val       << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_BMAX_SINGLE        (SDHC_ACR_BMAX_SINGLE_Val      << SDHC_ACR_BMAX_Pos)
+#define SDHC_ACR_MASK               _U_(0x00000003) /**< \brief (SDHC_ACR) MASK Register */
+
+/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FSDCLKD:1;        /*!< bit:      0  Force SDCK Disabled                */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_CC2R_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CC2R_OFFSET            0x20C        /**< \brief (SDHC_CC2R offset) Clock Control 2 */
+#define SDHC_CC2R_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_CC2R reset_value) Clock Control 2 */
+
+#define SDHC_CC2R_FSDCLKD_Pos       0            /**< \brief (SDHC_CC2R) Force SDCK Disabled */
+#define SDHC_CC2R_FSDCLKD           (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)
+#define   SDHC_CC2R_FSDCLKD_NOEFFECT_Val  _U_(0x0)   /**< \brief (SDHC_CC2R) No effect */
+#define   SDHC_CC2R_FSDCLKD_DISABLE_Val   _U_(0x1)   /**< \brief (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */
+#define SDHC_CC2R_FSDCLKD_NOEFFECT  (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_FSDCLKD_DISABLE   (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)
+#define SDHC_CC2R_MASK              _U_(0x00000001) /**< \brief (SDHC_CC2R) MASK Register */
+
+/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CAPWREN:1;        /*!< bit:      0  Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
+    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
+    uint32_t KEY:8;            /*!< bit:  8..15  Key (0x46)                         */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SDHC_CACR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_CACR_OFFSET            0x230        /**< \brief (SDHC_CACR offset) Capabilities Control */
+#define SDHC_CACR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_CACR reset_value) Capabilities Control */
+
+#define SDHC_CACR_CAPWREN_Pos       0            /**< \brief (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
+#define SDHC_CACR_CAPWREN           (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)
+#define SDHC_CACR_KEY_Pos           8            /**< \brief (SDHC_CACR) Key (0x46) */
+#define SDHC_CACR_KEY_Msk           (_U_(0xFF) << SDHC_CACR_KEY_Pos)
+#define SDHC_CACR_KEY(value)        (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))
+#define SDHC_CACR_MASK              _U_(0x0000FF01) /**< \brief (SDHC_CACR) MASK Register */
+
+/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W  8) Debug -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NIDBG:1;          /*!< bit:      0  Non-intrusive debug enable         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SDHC_DBGR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SDHC_DBGR_OFFSET            0x234        /**< \brief (SDHC_DBGR offset) Debug */
+#define SDHC_DBGR_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_DBGR reset_value) Debug */
+
+#define SDHC_DBGR_NIDBG_Pos         0            /**< \brief (SDHC_DBGR) Non-intrusive debug enable */
+#define SDHC_DBGR_NIDBG             (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)
+#define   SDHC_DBGR_NIDBG_IDBG_Val        _U_(0x0)   /**< \brief (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */
+#define   SDHC_DBGR_NIDBG_NIDBG_Val       _U_(0x1)   /**< \brief (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */
+#define SDHC_DBGR_NIDBG_IDBG        (SDHC_DBGR_NIDBG_IDBG_Val      << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_NIDBG_NIDBG       (SDHC_DBGR_NIDBG_NIDBG_Val     << SDHC_DBGR_NIDBG_Pos)
+#define SDHC_DBGR_MASK              _U_(0x01)    /**< \brief (SDHC_DBGR) MASK Register */
+
+/** \brief SDHC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO SDHC_SSAR_Type            SSAR;        /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */
+  __IO SDHC_BSR_Type             BSR;         /**< \brief Offset: 0x004 (R/W 16) Block Size */
+  __IO SDHC_BCR_Type             BCR;         /**< \brief Offset: 0x006 (R/W 16) Block Count */
+  __IO SDHC_ARG1R_Type           ARG1R;       /**< \brief Offset: 0x008 (R/W 32) Argument 1 */
+  __IO SDHC_TMR_Type             TMR;         /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */
+  __IO SDHC_CR_Type              CR;          /**< \brief Offset: 0x00E (R/W 16) Command */
+  __I  SDHC_RR_Type              RR[4];       /**< \brief Offset: 0x010 (R/  32) Response */
+  __IO SDHC_BDPR_Type            BDPR;        /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */
+  __I  SDHC_PSR_Type             PSR;         /**< \brief Offset: 0x024 (R/  32) Present State */
+  __IO SDHC_HC1R_Type            HC1R;        /**< \brief Offset: 0x028 (R/W  8) Host Control 1 */
+  __IO SDHC_PCR_Type             PCR;         /**< \brief Offset: 0x029 (R/W  8) Power Control */
+  __IO SDHC_BGCR_Type            BGCR;        /**< \brief Offset: 0x02A (R/W  8) Block Gap Control */
+  __IO SDHC_WCR_Type             WCR;         /**< \brief Offset: 0x02B (R/W  8) Wakeup Control */
+  __IO SDHC_CCR_Type             CCR;         /**< \brief Offset: 0x02C (R/W 16) Clock Control */
+  __IO SDHC_TCR_Type             TCR;         /**< \brief Offset: 0x02E (R/W  8) Timeout Control */
+  __IO SDHC_SRR_Type             SRR;         /**< \brief Offset: 0x02F (R/W  8) Software Reset */
+  __IO SDHC_NISTR_Type           NISTR;       /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */
+  __IO SDHC_EISTR_Type           EISTR;       /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */
+  __IO SDHC_NISTER_Type          NISTER;      /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */
+  __IO SDHC_EISTER_Type          EISTER;      /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */
+  __IO SDHC_NISIER_Type          NISIER;      /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */
+  __IO SDHC_EISIER_Type          EISIER;      /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */
+  __I  SDHC_ACESR_Type           ACESR;       /**< \brief Offset: 0x03C (R/  16) Auto CMD Error Status */
+  __IO SDHC_HC2R_Type            HC2R;        /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */
+  __I  SDHC_CA0R_Type            CA0R;        /**< \brief Offset: 0x040 (R/  32) Capabilities 0 */
+  __I  SDHC_CA1R_Type            CA1R;        /**< \brief Offset: 0x044 (R/  32) Capabilities 1 */
+  __I  SDHC_MCCAR_Type           MCCAR;       /**< \brief Offset: 0x048 (R/  32) Maximum Current Capabilities */
+       RoReg8                    Reserved1[0x4];
+  __O  SDHC_FERACES_Type         FERACES;     /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */
+  __O  SDHC_FEREIS_Type          FEREIS;      /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */
+  __I  SDHC_AESR_Type            AESR;        /**< \brief Offset: 0x054 (R/   8) ADMA Error Status */
+       RoReg8                    Reserved2[0x3];
+  __IO SDHC_ASAR_Type            ASAR[1];     /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */
+       RoReg8                    Reserved3[0x4];
+  __IO SDHC_PVR_Type             PVR[8];      /**< \brief Offset: 0x060 (R/W 16) Preset Value n */
+       RoReg8                    Reserved4[0x8C];
+  __I  SDHC_SISR_Type            SISR;        /**< \brief Offset: 0x0FC (R/  16) Slot Interrupt Status */
+  __I  SDHC_HCVR_Type            HCVR;        /**< \brief Offset: 0x0FE (R/  16) Host Controller Version */
+       RoReg8                    Reserved5[0x104];
+  __IO SDHC_MC1R_Type            MC1R;        /**< \brief Offset: 0x204 (R/W  8) MMC Control 1 */
+  __O  SDHC_MC2R_Type            MC2R;        /**< \brief Offset: 0x205 ( /W  8) MMC Control 2 */
+       RoReg8                    Reserved6[0x2];
+  __IO SDHC_ACR_Type             ACR;         /**< \brief Offset: 0x208 (R/W 32) AHB Control */
+  __IO SDHC_CC2R_Type            CC2R;        /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */
+       RoReg8                    Reserved7[0x20];
+  __IO SDHC_CACR_Type            CACR;        /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */
+  __IO SDHC_DBGR_Type            DBGR;        /**< \brief Offset: 0x234 (R/W  8) Debug */
+} Sdhc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_SDHC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/sercom.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/sercom.h
new file mode 100644
index 000000000..90608b275
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/sercom.h	
@@ -0,0 +1,1680 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM_COMPONENT_
+#define _SAME53_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAME53_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM                  0x500
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST     (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE    (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk  (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY  (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT    (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22           /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN  (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN  (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM     (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK      _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
+    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
+    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
+    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
+    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
+    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST     (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE    (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk  (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY  (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT    (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN  (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM     (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK      _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST      (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE     (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk   (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY   (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON       (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk   (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk   (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk   (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA       (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL       (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD       (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK       _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
+    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
+    uint32_t TXINV:1;          /*!< bit:      9  Transmit Data Invert               */
+    uint32_t RXINV:1;          /*!< bit:     10  Receive Data Invert                */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
+    uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
+    uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
+    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
+    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
+    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
+    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
+    uint32_t :1;               /*!< bit:     31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST    (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE   (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON     (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_TXINV_Pos 9            /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
+#define SERCOM_USART_CTRLA_TXINV    (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
+#define SERCOM_USART_CTRLA_RXINV_Pos 10           /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
+#define SERCOM_USART_CTRLA_RXINV    (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE    (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL     (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD     (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK     _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN      (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN      (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk   (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT    (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK      _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
+    uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
+    uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
+    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
+    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN      (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos  9            /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD      (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10           /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN    (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk   (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT    (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK      _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
+    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
+    uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
+    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
+    uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
+    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN    (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE       (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN      (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk  (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN       (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK       _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
+    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
+    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
+    uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
+    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
+    uint32_t :6;               /*!< bit: 18..23  Reserved                           */
+    uint32_t LINCMD:2;         /*!< bit: 24..25  LIN Command                        */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE   (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN   (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE     (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC      (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE    (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN     (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN     (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_LINCMD_Pos 24           /**< \brief (SERCOM_USART_CTRLB) LIN Command */
+#define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
+#define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
+#define SERCOM_USART_CTRLB_MASK     _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM I2CM Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLC_OFFSET    0x08         /**< \brief (SERCOM_I2CM_CTRLC offset) I2CM Control C */
+#define SERCOM_I2CM_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLC reset_value) I2CM Control C */
+
+#define SERCOM_I2CM_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_I2CM_CTRLC) Data 32 Bit */
+#define SERCOM_I2CM_CTRLC_DATA32B   (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)
+#define SERCOM_I2CM_CTRLC_MASK      _U_(0x01000000) /**< \brief (SERCOM_I2CM_CTRLC) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS I2CS Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SDASETUP:4;       /*!< bit:  0.. 3  SDA Setup Time                     */
+    uint32_t :20;              /*!< bit:  4..23  Reserved                           */
+    uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLC_OFFSET    0x08         /**< \brief (SERCOM_I2CS_CTRLC offset) I2CS Control C */
+#define SERCOM_I2CS_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLC reset_value) I2CS Control C */
+
+#define SERCOM_I2CS_CTRLC_SDASETUP_Pos 0            /**< \brief (SERCOM_I2CS_CTRLC) SDA Setup Time */
+#define SERCOM_I2CS_CTRLC_SDASETUP_Msk (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)
+#define SERCOM_I2CS_CTRLC_SDASETUP(value) (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
+#define SERCOM_I2CS_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_I2CS_CTRLC) Data 32 Bit */
+#define SERCOM_I2CS_CTRLC_DATA32B   (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)
+#define SERCOM_I2CS_CTRLC_MASK      _U_(0x0100000F) /**< \brief (SERCOM_I2CS_CTRLC) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ICSPACE:6;        /*!< bit:  0.. 5  Inter-Character Spacing            */
+    uint32_t :18;              /*!< bit:  6..23  Reserved                           */
+    uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
+    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLC_OFFSET     0x08         /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
+#define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
+
+#define SERCOM_SPI_CTRLC_ICSPACE_Pos 0            /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
+#define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
+#define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
+#define SERCOM_SPI_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
+#define SERCOM_SPI_CTRLC_DATA32B    (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
+#define SERCOM_SPI_CTRLC_MASK       _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
+
+/* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GTIME:3;          /*!< bit:  0.. 2  Guard Time                         */
+    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint32_t BRKLEN:2;         /*!< bit:  8.. 9  LIN Master Break Length            */
+    uint32_t HDRDLY:2;         /*!< bit: 10..11  LIN Master Header Delay            */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t INACK:1;          /*!< bit:     16  Inhibit Not Acknowledge            */
+    uint32_t DSNACK:1;         /*!< bit:     17  Disable Successive NACK            */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t MAXITER:3;        /*!< bit: 20..22  Maximum Iterations                 */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t DATA32B:2;        /*!< bit: 24..25  Data 32 Bit                        */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLC_OFFSET   0x08         /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
+#define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
+
+#define SERCOM_USART_CTRLC_GTIME_Pos 0            /**< \brief (SERCOM_USART_CTRLC) Guard Time */
+#define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
+#define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
+#define SERCOM_USART_CTRLC_BRKLEN_Pos 8            /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
+#define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
+#define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
+#define SERCOM_USART_CTRLC_HDRDLY_Pos 10           /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
+#define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
+#define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
+#define SERCOM_USART_CTRLC_INACK_Pos 16           /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
+#define SERCOM_USART_CTRLC_INACK    (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
+#define SERCOM_USART_CTRLC_DSNACK_Pos 17           /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
+#define SERCOM_USART_CTRLC_DSNACK   (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
+#define SERCOM_USART_CTRLC_MAXITER_Pos 20           /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
+#define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
+#define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
+#define SERCOM_USART_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
+#define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
+#define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
+#define SERCOM_USART_CTRLC_MASK     _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+    uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
+    uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
+    uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET     0x0C         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk   (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK       _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE  _U_(0x00)    /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk    (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK        _U_(0xFF)    /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct { // FRAC mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRAC;                      /*!< Structure used for FRAC                         */
+  struct { // FRACFP mode
+    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
+    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
+  } FRACFP;                    /*!< Structure used for FRACFP                       */
+  struct { // USARTFP mode
+    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
+  } USARTFP;                   /*!< Structure used for USARTFP                      */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk  (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK      _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk  (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK      _U_(0xFF)    /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB     (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB     (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR  (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK   _U_(0x83)    /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC   (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY   (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR  (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK   _U_(0x87)    /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE     (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC     (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC     (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL     (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR   (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK    _U_(0x8F)    /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE   (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC   (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC   (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS   (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK  _U_(0xBF)    /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
+    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB     (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB     (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR  (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK   _U_(0x83)    /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
+    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
+    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC   (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY   (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR  (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK   _U_(0x87)    /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE     (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC     (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC     (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL     (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR   (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK    _U_(0x8F)    /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
+    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
+    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
+    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
+    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
+    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE   (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC   (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC   (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS   (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK  _U_(0xBF)    /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
+    __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
+    __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB      (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB      (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR   (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK    _U_(0x83)    /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
+    __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
+    __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
+    __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC    (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH  (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY    (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR   (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK    _U_(0x87)    /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
+    __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE      (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC      (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC      (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL      (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR    (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK     _U_(0x8F)    /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
+    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
+    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
+    __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
+    __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
+    __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
+    __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE    (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC    (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC    (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS    (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC  (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK  (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR  (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK   _U_(0xBF)    /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR   (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST  (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK   (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT  (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD  (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8            /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10           /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR   (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK     _U_(0x07F7)  /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
+    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
+    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
+    uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
+    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
+    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
+    uint16_t :1;               /*!< bit:      8  Reserved                           */
+    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
+    uint16_t HS:1;             /*!< bit:     10  High Speed                         */
+    uint16_t LENERR:1;         /*!< bit:     11  Transaction Length Error           */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR   (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL     (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK   (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR      (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR       (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT  (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD  (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos   10           /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS       (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_LENERR_Pos 11           /**< \brief (SERCOM_I2CS_STATUS) Transaction Length Error */
+#define SERCOM_I2CS_STATUS_LENERR   (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)
+#define SERCOM_I2CS_STATUS_MASK     _U_(0x0EDF)  /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t :8;               /*!< bit:  3..10  Reserved                           */
+    uint16_t LENERR:1;         /*!< bit:     11  Transaction Length Error           */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF    (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_LENERR_Pos 11           /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
+#define SERCOM_SPI_STATUS_LENERR    (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
+#define SERCOM_SPI_STATUS_MASK      _U_(0x0804)  /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
+    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
+    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
+    uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
+    uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
+    uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
+    uint16_t TXE:1;            /*!< bit:      6  Transmitter Empty                  */
+    uint16_t ITER:1;           /*!< bit:      7  Maximum Number of Repetitions Reached */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR    (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR    (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF  (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS     (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF     (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL    (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_TXE_Pos 6            /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
+#define SERCOM_USART_STATUS_TXE     (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
+#define SERCOM_USART_STATUS_ITER_Pos 7            /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
+#define SERCOM_USART_STATUS_ITER    (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
+#define SERCOM_USART_STATUS_MASK    _U_(0x00FF)  /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CM I2CM Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t LENGTH:1;         /*!< bit:      4  Length Synchronization Busy        */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST  (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2            /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP  (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK   _U_(0x00000017) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CS I2CS Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint32_t LENGTH:1;         /*!< bit:      4  Length Synchronization Busy        */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST  (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK   _U_(0x00000013) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t LENGTH:1;         /*!< bit:      4  LENGTH Synchronization Busy        */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST   (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE  (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB   (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_LENGTH  (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK    _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
+    uint32_t RXERRCNT:1;       /*!< bit:      3  RXERRCNT Synchronization Busy      */
+    uint32_t LENGTH:1;         /*!< bit:      4  LENGTH Synchronization Busy        */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3            /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
+#define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK  _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/   8) USART USART Receive Error Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_RXERRCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXERRCNT_OFFSET 0x20         /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
+#define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
+#define SERCOM_USART_RXERRCNT_MASK  _U_(0xFF)    /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
+
+/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS I2CS Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
+    uint16_t LENEN:1;          /*!< bit:      8  Data Length Enable                 */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_LENGTH_OFFSET   0x22         /**< \brief (SERCOM_I2CS_LENGTH offset) I2CS Length */
+#define SERCOM_I2CS_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_I2CS_LENGTH reset_value) I2CS Length */
+
+#define SERCOM_I2CS_LENGTH_LEN_Pos  0            /**< \brief (SERCOM_I2CS_LENGTH) Data Length */
+#define SERCOM_I2CS_LENGTH_LEN_Msk  (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)
+#define SERCOM_I2CS_LENGTH_LEN(value) (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
+#define SERCOM_I2CS_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_I2CS_LENGTH) Data Length Enable */
+#define SERCOM_I2CS_LENGTH_LENEN    (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)
+#define SERCOM_I2CS_LENGTH_MASK     _U_(0x01FF)  /**< \brief (SERCOM_I2CS_LENGTH) MASK Register */
+
+/* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
+    uint16_t LENEN:1;          /*!< bit:      8  Data Length Enable                 */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_LENGTH_OFFSET    0x22         /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
+#define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
+
+#define SERCOM_SPI_LENGTH_LEN_Pos   0            /**< \brief (SERCOM_SPI_LENGTH) Data Length */
+#define SERCOM_SPI_LENGTH_LEN_Msk   (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
+#define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
+#define SERCOM_SPI_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
+#define SERCOM_SPI_LENGTH_LENEN     (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
+#define SERCOM_SPI_LENGTH_MASK      _U_(0x01FF)  /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
+
+/* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
+    uint16_t LENEN:2;          /*!< bit:  8.. 9  Data Length Enable                 */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_LENGTH_OFFSET  0x22         /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
+#define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
+
+#define SERCOM_USART_LENGTH_LEN_Pos 0            /**< \brief (SERCOM_USART_LENGTH) Data Length */
+#define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
+#define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
+#define SERCOM_USART_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
+#define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
+#define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
+#define SERCOM_USART_LENGTH_MASK    _U_(0x03FF)  /**< \brief (SERCOM_USART_LENGTH) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
+    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
+    uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
+    uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk   (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos  13           /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN      (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos     14           /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS         (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN   (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos    16           /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk    (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK       _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
+    uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
+    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
+    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
+    uint32_t :1;               /*!< bit:     16  Reserved                           */
+    uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN     (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk   (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN   (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK       _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE  _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk    (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK        _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk   (_U_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK       _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk   (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK       _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE  _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk    (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK        _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk  (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK      _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET  0x30         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK    _U_(0x01)    /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP  (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK     _U_(0x01)    /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK   _U_(0x01)    /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+  __IO SERCOM_I2CM_CTRLC_Type    CTRLC;       /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
+  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+       RoReg8                    Reserved1[0x4];
+  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+  __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Synchronization Busy */
+       RoReg8                    Reserved5[0x4];
+  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+  __IO SERCOM_I2CS_CTRLC_Type    CTRLC;       /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
+       RoReg8                    Reserved1[0x8];
+  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+  __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Synchronization Busy */
+       RoReg8                    Reserved5[0x2];
+  __IO SERCOM_I2CS_LENGTH_Type   LENGTH;      /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
+  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+  __IO SERCOM_SPI_CTRLC_Type     CTRLC;       /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
+  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
+       RoReg8                    Reserved1[0x7];
+  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+  __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Synchronization Busy */
+       RoReg8                    Reserved5[0x2];
+  __IO SERCOM_SPI_LENGTH_Type    LENGTH;      /**< \brief Offset: 0x22 (R/W 16) SPI Length */
+  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+  __IO SERCOM_USART_CTRLC_Type   CTRLC;       /**< \brief Offset: 0x08 (R/W 32) USART Control C */
+  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+  __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
+       RoReg8                    Reserved1[0x5];
+  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
+       RoReg8                    Reserved3[0x1];
+  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x1];
+  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
+  __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Synchronization Busy */
+  __I  SERCOM_USART_RXERRCNT_Type RXERRCNT;    /**< \brief Offset: 0x20 (R/   8) USART Receive Error Count */
+       RoReg8                    Reserved5[0x1];
+  __IO SERCOM_USART_LENGTH_Type  LENGTH;      /**< \brief Offset: 0x22 (R/W 16) USART Length */
+       RoReg8                    Reserved6[0x4];
+  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 32) USART Data */
+       RoReg8                    Reserved7[0x4];
+  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
+       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
+       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
+       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_SERCOM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/supc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/supc.h
new file mode 100644
index 000000000..465772f6b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/supc.h	
@@ -0,0 +1,435 @@
+/**
+ * \file
+ *
+ * \brief Component description for SUPC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SUPC_COMPONENT_
+#define _SAME53_SUPC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR SUPC */
+/* ========================================================================== */
+/** \addtogroup SAME53_SUPC Supply Controller */
+/*@{*/
+
+#define SUPC_U2407
+#define REV_SUPC                    0x110
+
+/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
+    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
+    uint32_t :1;               /*!< bit:      9  Reserved                           */
+    uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_INTENCLR_OFFSET        0x00         /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */
+#define SUPC_INTENCLR_RESETVALUE    _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SUPC_INTENCLR_BOD33RDY_Pos  0            /**< \brief (SUPC_INTENCLR) BOD33 Ready */
+#define SUPC_INTENCLR_BOD33RDY      (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)
+#define SUPC_INTENCLR_BOD33DET_Pos  1            /**< \brief (SUPC_INTENCLR) BOD33 Detection */
+#define SUPC_INTENCLR_BOD33DET      (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
+#define SUPC_INTENCLR_B33SRDY_Pos   2            /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
+#define SUPC_INTENCLR_B33SRDY       (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
+#define SUPC_INTENCLR_VREGRDY_Pos   8            /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
+#define SUPC_INTENCLR_VREGRDY       (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
+#define SUPC_INTENCLR_VCORERDY_Pos  10           /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
+#define SUPC_INTENCLR_VCORERDY      (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
+#define SUPC_INTENCLR_MASK          _U_(0x00000507) /**< \brief (SUPC_INTENCLR) MASK Register */
+
+/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
+    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
+    uint32_t :1;               /*!< bit:      9  Reserved                           */
+    uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_INTENSET_OFFSET        0x04         /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */
+#define SUPC_INTENSET_RESETVALUE    _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */
+
+#define SUPC_INTENSET_BOD33RDY_Pos  0            /**< \brief (SUPC_INTENSET) BOD33 Ready */
+#define SUPC_INTENSET_BOD33RDY      (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)
+#define SUPC_INTENSET_BOD33DET_Pos  1            /**< \brief (SUPC_INTENSET) BOD33 Detection */
+#define SUPC_INTENSET_BOD33DET      (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
+#define SUPC_INTENSET_B33SRDY_Pos   2            /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
+#define SUPC_INTENSET_B33SRDY       (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
+#define SUPC_INTENSET_VREGRDY_Pos   8            /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
+#define SUPC_INTENSET_VREGRDY       (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
+#define SUPC_INTENSET_VCORERDY_Pos  10           /**< \brief (SUPC_INTENSET) VDDCORE Ready */
+#define SUPC_INTENSET_VCORERDY      (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
+#define SUPC_INTENSET_MASK          _U_(0x00000507) /**< \brief (SUPC_INTENSET) MASK Register */
+
+/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
+    __I uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
+    __I uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
+    __I uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    __I uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
+    __I uint32_t :1;               /*!< bit:      9  Reserved                           */
+    __I uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
+    __I uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_INTFLAG_OFFSET         0x08         /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SUPC_INTFLAG_RESETVALUE     _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SUPC_INTFLAG_BOD33RDY_Pos   0            /**< \brief (SUPC_INTFLAG) BOD33 Ready */
+#define SUPC_INTFLAG_BOD33RDY       (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)
+#define SUPC_INTFLAG_BOD33DET_Pos   1            /**< \brief (SUPC_INTFLAG) BOD33 Detection */
+#define SUPC_INTFLAG_BOD33DET       (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
+#define SUPC_INTFLAG_B33SRDY_Pos    2            /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
+#define SUPC_INTFLAG_B33SRDY        (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
+#define SUPC_INTFLAG_VREGRDY_Pos    8            /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
+#define SUPC_INTFLAG_VREGRDY        (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
+#define SUPC_INTFLAG_VCORERDY_Pos   10           /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
+#define SUPC_INTFLAG_VCORERDY       (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
+#define SUPC_INTFLAG_MASK           _U_(0x00000507) /**< \brief (SUPC_INTFLAG) MASK Register */
+
+/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
+    uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
+    uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
+    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
+    uint32_t :1;               /*!< bit:      9  Reserved                           */
+    uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_STATUS_OFFSET          0x0C         /**< \brief (SUPC_STATUS offset) Power and Clocks Status */
+#define SUPC_STATUS_RESETVALUE      _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */
+
+#define SUPC_STATUS_BOD33RDY_Pos    0            /**< \brief (SUPC_STATUS) BOD33 Ready */
+#define SUPC_STATUS_BOD33RDY        (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)
+#define SUPC_STATUS_BOD33DET_Pos    1            /**< \brief (SUPC_STATUS) BOD33 Detection */
+#define SUPC_STATUS_BOD33DET        (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
+#define SUPC_STATUS_B33SRDY_Pos     2            /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
+#define SUPC_STATUS_B33SRDY         (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
+#define SUPC_STATUS_VREGRDY_Pos     8            /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
+#define SUPC_STATUS_VREGRDY         (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
+#define SUPC_STATUS_VCORERDY_Pos    10           /**< \brief (SUPC_STATUS) VDDCORE Ready */
+#define SUPC_STATUS_VCORERDY        (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
+#define SUPC_STATUS_MASK            _U_(0x00000507) /**< \brief (SUPC_STATUS) MASK Register */
+
+/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t ACTION:2;         /*!< bit:  2.. 3  Action when Threshold Crossed      */
+    uint32_t STDBYCFG:1;       /*!< bit:      4  Configuration in Standby mode      */
+    uint32_t RUNSTDBY:1;       /*!< bit:      5  Run in Standby mode                */
+    uint32_t RUNHIB:1;         /*!< bit:      6  Run in Hibernate mode              */
+    uint32_t RUNBKUP:1;        /*!< bit:      7  Run in Backup mode                 */
+    uint32_t HYST:4;           /*!< bit:  8..11  Hysteresis value                   */
+    uint32_t PSEL:3;           /*!< bit: 12..14  Prescaler Select                   */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t LEVEL:8;          /*!< bit: 16..23  Threshold Level for VDD            */
+    uint32_t VBATLEVEL:8;      /*!< bit: 24..31  Threshold Level in battery backup sleep mode for VBAT */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BOD33_OFFSET           0x10         /**< \brief (SUPC_BOD33 offset) BOD33 Control */
+#define SUPC_BOD33_RESETVALUE       _U_(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */
+
+#define SUPC_BOD33_ENABLE_Pos       1            /**< \brief (SUPC_BOD33) Enable */
+#define SUPC_BOD33_ENABLE           (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)
+#define SUPC_BOD33_ACTION_Pos       2            /**< \brief (SUPC_BOD33) Action when Threshold Crossed */
+#define SUPC_BOD33_ACTION_Msk       (_U_(0x3) << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION(value)    (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))
+#define   SUPC_BOD33_ACTION_NONE_Val      _U_(0x0)   /**< \brief (SUPC_BOD33) No action */
+#define   SUPC_BOD33_ACTION_RESET_Val     _U_(0x1)   /**< \brief (SUPC_BOD33) The BOD33 generates a reset */
+#define   SUPC_BOD33_ACTION_INT_Val       _U_(0x2)   /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */
+#define   SUPC_BOD33_ACTION_BKUP_Val      _U_(0x3)   /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */
+#define SUPC_BOD33_ACTION_NONE      (SUPC_BOD33_ACTION_NONE_Val    << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION_RESET     (SUPC_BOD33_ACTION_RESET_Val   << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION_INT       (SUPC_BOD33_ACTION_INT_Val     << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_ACTION_BKUP      (SUPC_BOD33_ACTION_BKUP_Val    << SUPC_BOD33_ACTION_Pos)
+#define SUPC_BOD33_STDBYCFG_Pos     4            /**< \brief (SUPC_BOD33) Configuration in Standby mode */
+#define SUPC_BOD33_STDBYCFG         (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)
+#define SUPC_BOD33_RUNSTDBY_Pos     5            /**< \brief (SUPC_BOD33) Run in Standby mode */
+#define SUPC_BOD33_RUNSTDBY         (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)
+#define SUPC_BOD33_RUNHIB_Pos       6            /**< \brief (SUPC_BOD33) Run in Hibernate mode */
+#define SUPC_BOD33_RUNHIB           (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)
+#define SUPC_BOD33_RUNBKUP_Pos      7            /**< \brief (SUPC_BOD33) Run in Backup mode */
+#define SUPC_BOD33_RUNBKUP          (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)
+#define SUPC_BOD33_HYST_Pos         8            /**< \brief (SUPC_BOD33) Hysteresis value */
+#define SUPC_BOD33_HYST_Msk         (_U_(0xF) << SUPC_BOD33_HYST_Pos)
+#define SUPC_BOD33_HYST(value)      (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))
+#define SUPC_BOD33_PSEL_Pos         12           /**< \brief (SUPC_BOD33) Prescaler Select */
+#define SUPC_BOD33_PSEL_Msk         (_U_(0x7) << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL(value)      (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))
+#define   SUPC_BOD33_PSEL_NODIV_Val       _U_(0x0)   /**< \brief (SUPC_BOD33) Not divided */
+#define   SUPC_BOD33_PSEL_DIV4_Val        _U_(0x1)   /**< \brief (SUPC_BOD33) Divide clock by 4 */
+#define   SUPC_BOD33_PSEL_DIV8_Val        _U_(0x2)   /**< \brief (SUPC_BOD33) Divide clock by 8 */
+#define   SUPC_BOD33_PSEL_DIV16_Val       _U_(0x3)   /**< \brief (SUPC_BOD33) Divide clock by 16 */
+#define   SUPC_BOD33_PSEL_DIV32_Val       _U_(0x4)   /**< \brief (SUPC_BOD33) Divide clock by 32 */
+#define   SUPC_BOD33_PSEL_DIV64_Val       _U_(0x5)   /**< \brief (SUPC_BOD33) Divide clock by 64 */
+#define   SUPC_BOD33_PSEL_DIV128_Val      _U_(0x6)   /**< \brief (SUPC_BOD33) Divide clock by 128 */
+#define   SUPC_BOD33_PSEL_DIV256_Val      _U_(0x7)   /**< \brief (SUPC_BOD33) Divide clock by 256 */
+#define SUPC_BOD33_PSEL_NODIV       (SUPC_BOD33_PSEL_NODIV_Val     << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV4        (SUPC_BOD33_PSEL_DIV4_Val      << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV8        (SUPC_BOD33_PSEL_DIV8_Val      << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV16       (SUPC_BOD33_PSEL_DIV16_Val     << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV32       (SUPC_BOD33_PSEL_DIV32_Val     << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV64       (SUPC_BOD33_PSEL_DIV64_Val     << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV128      (SUPC_BOD33_PSEL_DIV128_Val    << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_PSEL_DIV256      (SUPC_BOD33_PSEL_DIV256_Val    << SUPC_BOD33_PSEL_Pos)
+#define SUPC_BOD33_LEVEL_Pos        16           /**< \brief (SUPC_BOD33) Threshold Level for VDD */
+#define SUPC_BOD33_LEVEL_Msk        (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)
+#define SUPC_BOD33_LEVEL(value)     (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))
+#define SUPC_BOD33_VBATLEVEL_Pos    24           /**< \brief (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT */
+#define SUPC_BOD33_VBATLEVEL_Msk    (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)
+#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
+#define SUPC_BOD33_MASK             _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
+
+/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t SEL:1;            /*!< bit:      2  Voltage Regulator Selection        */
+    uint32_t :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint32_t RUNBKUP:1;        /*!< bit:      7  Run in Backup mode                 */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t VSEN:1;           /*!< bit:     16  Voltage Scaling Enable             */
+    uint32_t :7;               /*!< bit: 17..23  Reserved                           */
+    uint32_t VSPER:3;          /*!< bit: 24..26  Voltage Scaling Period             */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_VREG_OFFSET            0x18         /**< \brief (SUPC_VREG offset) VREG Control */
+#define SUPC_VREG_RESETVALUE        _U_(0x00000002) /**< \brief (SUPC_VREG reset_value) VREG Control */
+
+#define SUPC_VREG_ENABLE_Pos        1            /**< \brief (SUPC_VREG) Enable */
+#define SUPC_VREG_ENABLE            (_U_(0x1) << SUPC_VREG_ENABLE_Pos)
+#define SUPC_VREG_SEL_Pos           2            /**< \brief (SUPC_VREG) Voltage Regulator Selection */
+#define SUPC_VREG_SEL               (_U_(0x1) << SUPC_VREG_SEL_Pos)
+#define   SUPC_VREG_SEL_LDO_Val           _U_(0x0)   /**< \brief (SUPC_VREG) LDO selection */
+#define   SUPC_VREG_SEL_BUCK_Val          _U_(0x1)   /**< \brief (SUPC_VREG) Buck selection */
+#define SUPC_VREG_SEL_LDO           (SUPC_VREG_SEL_LDO_Val         << SUPC_VREG_SEL_Pos)
+#define SUPC_VREG_SEL_BUCK          (SUPC_VREG_SEL_BUCK_Val        << SUPC_VREG_SEL_Pos)
+#define SUPC_VREG_RUNBKUP_Pos       7            /**< \brief (SUPC_VREG) Run in Backup mode */
+#define SUPC_VREG_RUNBKUP           (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)
+#define SUPC_VREG_VSEN_Pos          16           /**< \brief (SUPC_VREG) Voltage Scaling Enable */
+#define SUPC_VREG_VSEN              (_U_(0x1) << SUPC_VREG_VSEN_Pos)
+#define SUPC_VREG_VSPER_Pos         24           /**< \brief (SUPC_VREG) Voltage Scaling Period */
+#define SUPC_VREG_VSPER_Msk         (_U_(0x7) << SUPC_VREG_VSPER_Pos)
+#define SUPC_VREG_VSPER(value)      (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))
+#define SUPC_VREG_MASK              _U_(0x07010086) /**< \brief (SUPC_VREG) MASK Register */
+
+/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Output Enable   */
+    uint32_t VREFOE:1;         /*!< bit:      2  Voltage Reference Output Enable    */
+    uint32_t TSSEL:1;          /*!< bit:      3  Temperature Sensor Selection       */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Contrl                   */
+    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
+    uint32_t SEL:4;            /*!< bit: 16..19  Voltage Reference Selection        */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_VREF_OFFSET            0x1C         /**< \brief (SUPC_VREF offset) VREF Control */
+#define SUPC_VREF_RESETVALUE        _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */
+
+#define SUPC_VREF_TSEN_Pos          1            /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */
+#define SUPC_VREF_TSEN              (_U_(0x1) << SUPC_VREF_TSEN_Pos)
+#define SUPC_VREF_VREFOE_Pos        2            /**< \brief (SUPC_VREF) Voltage Reference Output Enable */
+#define SUPC_VREF_VREFOE            (_U_(0x1) << SUPC_VREF_VREFOE_Pos)
+#define SUPC_VREF_TSSEL_Pos         3            /**< \brief (SUPC_VREF) Temperature Sensor Selection */
+#define SUPC_VREF_TSSEL             (_U_(0x1) << SUPC_VREF_TSSEL_Pos)
+#define SUPC_VREF_RUNSTDBY_Pos      6            /**< \brief (SUPC_VREF) Run during Standby */
+#define SUPC_VREF_RUNSTDBY          (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)
+#define SUPC_VREF_ONDEMAND_Pos      7            /**< \brief (SUPC_VREF) On Demand Contrl */
+#define SUPC_VREF_ONDEMAND          (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)
+#define SUPC_VREF_SEL_Pos           16           /**< \brief (SUPC_VREF) Voltage Reference Selection */
+#define SUPC_VREF_SEL_Msk           (_U_(0xF) << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL(value)        (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
+#define   SUPC_VREF_SEL_1V0_Val           _U_(0x0)   /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */
+#define   SUPC_VREF_SEL_1V1_Val           _U_(0x1)   /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */
+#define   SUPC_VREF_SEL_1V2_Val           _U_(0x2)   /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */
+#define   SUPC_VREF_SEL_1V25_Val          _U_(0x3)   /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */
+#define   SUPC_VREF_SEL_2V0_Val           _U_(0x4)   /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */
+#define   SUPC_VREF_SEL_2V2_Val           _U_(0x5)   /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */
+#define   SUPC_VREF_SEL_2V4_Val           _U_(0x6)   /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */
+#define   SUPC_VREF_SEL_2V5_Val           _U_(0x7)   /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */
+#define SUPC_VREF_SEL_1V0           (SUPC_VREF_SEL_1V0_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_1V1           (SUPC_VREF_SEL_1V1_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_1V2           (SUPC_VREF_SEL_1V2_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_1V25          (SUPC_VREF_SEL_1V25_Val        << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V0           (SUPC_VREF_SEL_2V0_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V2           (SUPC_VREF_SEL_2V2_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V4           (SUPC_VREF_SEL_2V4_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_SEL_2V5           (SUPC_VREF_SEL_2V5_Val         << SUPC_VREF_SEL_Pos)
+#define SUPC_VREF_MASK              _U_(0x000F00CE) /**< \brief (SUPC_VREF) MASK Register */
+
+/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CONF:1;           /*!< bit:      0  Battery Backup Configuration       */
+    uint32_t :1;               /*!< bit:      1  Reserved                           */
+    uint32_t WAKEEN:1;         /*!< bit:      2  Wake Enable                        */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_BBPS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BBPS_OFFSET            0x20         /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */
+#define SUPC_BBPS_RESETVALUE        _U_(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */
+
+#define SUPC_BBPS_CONF_Pos          0            /**< \brief (SUPC_BBPS) Battery Backup Configuration */
+#define SUPC_BBPS_CONF              (_U_(0x1) << SUPC_BBPS_CONF_Pos)
+#define   SUPC_BBPS_CONF_BOD33_Val        _U_(0x0)   /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */
+#define   SUPC_BBPS_CONF_FORCED_Val       _U_(0x1)   /**< \brief (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */
+#define SUPC_BBPS_CONF_BOD33        (SUPC_BBPS_CONF_BOD33_Val      << SUPC_BBPS_CONF_Pos)
+#define SUPC_BBPS_CONF_FORCED       (SUPC_BBPS_CONF_FORCED_Val     << SUPC_BBPS_CONF_Pos)
+#define SUPC_BBPS_WAKEEN_Pos        2            /**< \brief (SUPC_BBPS) Wake Enable */
+#define SUPC_BBPS_WAKEEN            (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)
+#define SUPC_BBPS_MASK              _U_(0x00000005) /**< \brief (SUPC_BBPS) MASK Register */
+
+/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EN:2;             /*!< bit:  0.. 1  Enable Output                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t CLR:2;            /*!< bit:  8.. 9  Clear Output                       */
+    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
+    uint32_t SET:2;            /*!< bit: 16..17  Set Output                         */
+    uint32_t :6;               /*!< bit: 18..23  Reserved                           */
+    uint32_t RTCTGL:2;         /*!< bit: 24..25  RTC Toggle Output                  */
+    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_BKOUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BKOUT_OFFSET           0x24         /**< \brief (SUPC_BKOUT offset) Backup Output Control */
+#define SUPC_BKOUT_RESETVALUE       _U_(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */
+
+#define SUPC_BKOUT_EN_Pos           0            /**< \brief (SUPC_BKOUT) Enable Output */
+#define SUPC_BKOUT_EN_Msk           (_U_(0x3) << SUPC_BKOUT_EN_Pos)
+#define SUPC_BKOUT_EN(value)        (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))
+#define SUPC_BKOUT_CLR_Pos          8            /**< \brief (SUPC_BKOUT) Clear Output */
+#define SUPC_BKOUT_CLR_Msk          (_U_(0x3) << SUPC_BKOUT_CLR_Pos)
+#define SUPC_BKOUT_CLR(value)       (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))
+#define SUPC_BKOUT_SET_Pos          16           /**< \brief (SUPC_BKOUT) Set Output */
+#define SUPC_BKOUT_SET_Msk          (_U_(0x3) << SUPC_BKOUT_SET_Pos)
+#define SUPC_BKOUT_SET(value)       (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))
+#define SUPC_BKOUT_RTCTGL_Pos       24           /**< \brief (SUPC_BKOUT) RTC Toggle Output */
+#define SUPC_BKOUT_RTCTGL_Msk       (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)
+#define SUPC_BKOUT_RTCTGL(value)    (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))
+#define SUPC_BKOUT_MASK             _U_(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */
+
+/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/  32) Backup Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BKIN:8;           /*!< bit:  0.. 7  Backup Input Value                 */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} SUPC_BKIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SUPC_BKIN_OFFSET            0x28         /**< \brief (SUPC_BKIN offset) Backup Input Control */
+#define SUPC_BKIN_RESETVALUE        _U_(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */
+
+#define SUPC_BKIN_BKIN_Pos          0            /**< \brief (SUPC_BKIN) Backup Input Value */
+#define SUPC_BKIN_BKIN_Msk          (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)
+#define SUPC_BKIN_BKIN(value)       (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))
+#define SUPC_BKIN_MASK              _U_(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */
+
+/** \brief SUPC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO SUPC_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO SUPC_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO SUPC_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  SUPC_STATUS_Type          STATUS;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO SUPC_BOD33_Type           BOD33;       /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
+       RoReg8                    Reserved1[0x4];
+  __IO SUPC_VREG_Type            VREG;        /**< \brief Offset: 0x18 (R/W 32) VREG Control */
+  __IO SUPC_VREF_Type            VREF;        /**< \brief Offset: 0x1C (R/W 32) VREF Control */
+  __IO SUPC_BBPS_Type            BBPS;        /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */
+  __IO SUPC_BKOUT_Type           BKOUT;       /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */
+  __I  SUPC_BKIN_Type            BKIN;        /**< \brief Offset: 0x28 (R/  32) Backup Input Control */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_SUPC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/tc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/tc.h
new file mode 100644
index 000000000..f2b07c54a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/tc.h	
@@ -0,0 +1,851 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC_COMPONENT_
+#define _SAME53_TC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAME53_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2249
+#define REV_TC                      0x300
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t MODE:2;           /*!< bit:  2.. 3  Timer Counter Mode                 */
+    uint32_t PRESCSYNC:2;      /*!< bit:  4.. 5  Prescaler and Counter Synchronization */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  Clock On Demand                    */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t ALOCK:1;          /*!< bit:     11  Auto Lock                          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t CAPTEN0:1;        /*!< bit:     16  Capture Channel 0 Enable           */
+    uint32_t CAPTEN1:1;        /*!< bit:     17  Capture Channel 1 Enable           */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t COPEN0:1;         /*!< bit:     20  Capture On Pin 0 Enable            */
+    uint32_t COPEN1:1;         /*!< bit:     21  Capture On Pin 1 Enable            */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t CAPTMODE0:2;      /*!< bit: 24..25  Capture Mode Channel 0             */
+    uint32_t :1;               /*!< bit:     26  Reserved                           */
+    uint32_t CAPTMODE1:2;      /*!< bit: 27..28  Capture mode Channel 1             */
+    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CAPTEN:2;         /*!< bit: 16..17  Capture Channel x Enable           */
+    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
+    uint32_t COPEN:2;          /*!< bit: 20..21  Capture On Pin x Enable            */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE         _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST              (_U_(0x1) << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE             (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) Timer Counter Mode */
+#define TC_CTRLA_MODE_Msk           (_U_(0x3) << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value)        (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define   TC_CTRLA_MODE_COUNT16_Val       _U_(0x0)   /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define   TC_CTRLA_MODE_COUNT8_Val        _U_(0x1)   /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define   TC_CTRLA_MODE_COUNT32_Val       _U_(0x2)   /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos      4            /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk      (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value)   (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define   TC_CTRLA_PRESCSYNC_GCLK_Val     _U_(0x0)   /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define   TC_CTRLA_PRESCSYNC_PRESC_Val    _U_(0x1)   /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   _U_(0x2)   /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos       6            /**< \brief (TC_CTRLA) Run during Standby */
+#define TC_CTRLA_RUNSTDBY           (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_ONDEMAND_Pos       7            /**< \brief (TC_CTRLA) Clock On Demand */
+#define TC_CTRLA_ONDEMAND           (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
+#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk      (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value)   (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define   TC_CTRLA_PRESCALER_DIV1_Val     _U_(0x0)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define   TC_CTRLA_PRESCALER_DIV2_Val     _U_(0x1)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define   TC_CTRLA_PRESCALER_DIV4_Val     _U_(0x2)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define   TC_CTRLA_PRESCALER_DIV8_Val     _U_(0x3)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define   TC_CTRLA_PRESCALER_DIV16_Val    _U_(0x4)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define   TC_CTRLA_PRESCALER_DIV64_Val    _U_(0x5)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define   TC_CTRLA_PRESCALER_DIV256_Val   _U_(0x6)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define   TC_CTRLA_PRESCALER_DIV1024_Val  _U_(0x7)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_ALOCK_Pos          11           /**< \brief (TC_CTRLA) Auto Lock */
+#define TC_CTRLA_ALOCK              (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
+#define TC_CTRLA_CAPTEN0_Pos        16           /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
+#define TC_CTRLA_CAPTEN0            (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
+#define TC_CTRLA_CAPTEN1_Pos        17           /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
+#define TC_CTRLA_CAPTEN1            (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
+#define TC_CTRLA_CAPTEN_Pos         16           /**< \brief (TC_CTRLA) Capture Channel x Enable */
+#define TC_CTRLA_CAPTEN_Msk         (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
+#define TC_CTRLA_CAPTEN(value)      (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
+#define TC_CTRLA_COPEN0_Pos         20           /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
+#define TC_CTRLA_COPEN0             (_U_(1) << TC_CTRLA_COPEN0_Pos)
+#define TC_CTRLA_COPEN1_Pos         21           /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
+#define TC_CTRLA_COPEN1             (_U_(1) << TC_CTRLA_COPEN1_Pos)
+#define TC_CTRLA_COPEN_Pos          20           /**< \brief (TC_CTRLA) Capture On Pin x Enable */
+#define TC_CTRLA_COPEN_Msk          (_U_(0x3) << TC_CTRLA_COPEN_Pos)
+#define TC_CTRLA_COPEN(value)       (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
+#define TC_CTRLA_CAPTMODE0_Pos      24           /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
+#define TC_CTRLA_CAPTMODE0_Msk      (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0(value)   (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
+#define   TC_CTRLA_CAPTMODE0_DEFAULT_Val  _U_(0x0)   /**< \brief (TC_CTRLA) Default capture */
+#define   TC_CTRLA_CAPTMODE0_CAPTMIN_Val  _U_(0x1)   /**< \brief (TC_CTRLA) Minimum capture */
+#define   TC_CTRLA_CAPTMODE0_CAPTMAX_Val  _U_(0x2)   /**< \brief (TC_CTRLA) Maximum capture */
+#define TC_CTRLA_CAPTMODE0_DEFAULT  (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0_CAPTMIN  (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE0_CAPTMAX  (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
+#define TC_CTRLA_CAPTMODE1_Pos      27           /**< \brief (TC_CTRLA) Capture mode Channel 1 */
+#define TC_CTRLA_CAPTMODE1_Msk      (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1(value)   (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
+#define   TC_CTRLA_CAPTMODE1_DEFAULT_Val  _U_(0x0)   /**< \brief (TC_CTRLA) Default capture */
+#define   TC_CTRLA_CAPTMODE1_CAPTMIN_Val  _U_(0x1)   /**< \brief (TC_CTRLA) Minimum capture */
+#define   TC_CTRLA_CAPTMODE1_CAPTMAX_Val  _U_(0x2)   /**< \brief (TC_CTRLA) Maximum capture */
+#define TC_CTRLA_CAPTMODE1_DEFAULT  (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1_CAPTMIN  (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_CAPTMODE1_CAPTMAX  (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
+#define TC_CTRLA_MASK               _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot on Counter                */
+    uint8_t  :2;               /*!< bit:  3.. 4  Reserved                           */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE      _U_(0x00)    /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR             (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_LUPD_Pos        1            /**< \brief (TC_CTRLBCLR) Lock Update */
+#define TC_CTRLBCLR_LUPD            (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
+#define TC_CTRLBCLR_ONESHOT         (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos         5            /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk         (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value)      (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define   TC_CTRLBCLR_CMD_NONE_Val        _U_(0x0)   /**< \brief (TC_CTRLBCLR) No action */
+#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   _U_(0x1)   /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define   TC_CTRLBCLR_CMD_STOP_Val        _U_(0x2)   /**< \brief (TC_CTRLBCLR) Force a stop */
+#define   TC_CTRLBCLR_CMD_UPDATE_Val      _U_(0x3)   /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
+#define   TC_CTRLBCLR_CMD_READSYNC_Val    _U_(0x4)   /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
+#define   TC_CTRLBCLR_CMD_DMAOS_Val       _U_(0x5)   /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
+#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_UPDATE      (TC_CTRLBCLR_CMD_UPDATE_Val    << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_READSYNC    (TC_CTRLBCLR_CMD_READSYNC_Val  << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_DMAOS       (TC_CTRLBCLR_CMD_DMAOS_Val     << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK            _U_(0xE7)    /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot on Counter                */
+    uint8_t  :2;               /*!< bit:  3.. 4  Reserved                           */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE      _U_(0x00)    /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR             (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_LUPD_Pos        1            /**< \brief (TC_CTRLBSET) Lock Update */
+#define TC_CTRLBSET_LUPD            (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-Shot on Counter */
+#define TC_CTRLBSET_ONESHOT         (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos         5            /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk         (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value)      (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define   TC_CTRLBSET_CMD_NONE_Val        _U_(0x0)   /**< \brief (TC_CTRLBSET) No action */
+#define   TC_CTRLBSET_CMD_RETRIGGER_Val   _U_(0x1)   /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define   TC_CTRLBSET_CMD_STOP_Val        _U_(0x2)   /**< \brief (TC_CTRLBSET) Force a stop */
+#define   TC_CTRLBSET_CMD_UPDATE_Val      _U_(0x3)   /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
+#define   TC_CTRLBSET_CMD_READSYNC_Val    _U_(0x4)   /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
+#define   TC_CTRLBSET_CMD_DMAOS_Val       _U_(0x5)   /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
+#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_UPDATE      (TC_CTRLBSET_CMD_UPDATE_Val    << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_READSYNC    (TC_CTRLBSET_CMD_READSYNC_Val  << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_DMAOS       (TC_CTRLBSET_CMD_DMAOS_Val     << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK            _U_(0xE7)    /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
+    uint16_t :1;               /*!< bit:      3  Reserved                           */
+    uint16_t TCINV:1;          /*!< bit:      4  TC Event Input Polarity            */
+    uint16_t TCEI:1;           /*!< bit:      5  TC Event Enable                    */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t OVFEO:1;          /*!< bit:      8  Event Output Enable                */
+    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
+    uint16_t MCEO0:1;          /*!< bit:     12  MC Event Output Enable 0           */
+    uint16_t MCEO1:1;          /*!< bit:     13  MC Event Output Enable 1           */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint16_t MCEO:2;           /*!< bit: 12..13  MC Event Output Enable x           */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET            0x06         /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE        _U_(0x0000)  /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk         (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value)      (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define   TC_EVCTRL_EVACT_OFF_Val         _U_(0x0)   /**< \brief (TC_EVCTRL) Event action disabled */
+#define   TC_EVCTRL_EVACT_RETRIGGER_Val   _U_(0x1)   /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define   TC_EVCTRL_EVACT_COUNT_Val       _U_(0x2)   /**< \brief (TC_EVCTRL) Count on event */
+#define   TC_EVCTRL_EVACT_START_Val       _U_(0x3)   /**< \brief (TC_EVCTRL) Start TC on event */
+#define   TC_EVCTRL_EVACT_STAMP_Val       _U_(0x4)   /**< \brief (TC_EVCTRL) Time stamp capture */
+#define   TC_EVCTRL_EVACT_PPW_Val         _U_(0x5)   /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
+#define   TC_EVCTRL_EVACT_PWP_Val         _U_(0x6)   /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
+#define   TC_EVCTRL_EVACT_PW_Val          _U_(0x7)   /**< \brief (TC_EVCTRL) Pulse width capture */
+#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_STAMP       (TC_EVCTRL_EVACT_STAMP_Val     << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PW          (TC_EVCTRL_EVACT_PW_Val        << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Event Input Polarity */
+#define TC_EVCTRL_TCINV             (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Enable */
+#define TC_EVCTRL_TCEI              (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Event Output Enable */
+#define TC_EVCTRL_OVFEO             (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
+#define TC_EVCTRL_MCEO0             (_U_(1) << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
+#define TC_EVCTRL_MCEO1             (_U_(1) << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) MC Event Output Enable x */
+#define TC_EVCTRL_MCEO_Msk          (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value)       (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK              _U_(0x3137)  /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  OVF Interrupt Disable              */
+    uint8_t  ERR:1;            /*!< bit:      1  ERR Interrupt Disable              */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  MC0:1;            /*!< bit:      4  MC Interrupt Disable 0             */
+    uint8_t  MC1:1;            /*!< bit:      5  MC Interrupt Disable 1             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  MC Interrupt Disable x             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET          0x08         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
+#define TC_INTENCLR_OVF             (_U_(0x1) << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
+#define TC_INTENCLR_ERR             (_U_(0x1) << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
+#define TC_INTENCLR_MC0             (_U_(1) << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
+#define TC_INTENCLR_MC1             (_U_(1) << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
+#define TC_INTENCLR_MC_Msk          (_U_(0x3) << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value)       (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK            _U_(0x33)    /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  OVF:1;            /*!< bit:      0  OVF Interrupt Enable               */
+    uint8_t  ERR:1;            /*!< bit:      1  ERR Interrupt Enable               */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  MC0:1;            /*!< bit:      4  MC Interrupt Enable 0              */
+    uint8_t  MC1:1;            /*!< bit:      5  MC Interrupt Enable 1              */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  MC:2;             /*!< bit:  4.. 5  MC Interrupt Enable x              */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET          0x09         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) OVF Interrupt Enable */
+#define TC_INTENSET_OVF             (_U_(0x1) << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) ERR Interrupt Enable */
+#define TC_INTENSET_ERR             (_U_(0x1) << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
+#define TC_INTENSET_MC0             (_U_(1) << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
+#define TC_INTENSET_MC1             (_U_(1) << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) MC Interrupt Enable x */
+#define TC_INTENSET_MC_Msk          (_U_(0x3) << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value)       (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK            _U_(0x33)    /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  OVF:1;            /*!< bit:      0  OVF Interrupt Flag                 */
+    __I uint8_t  ERR:1;            /*!< bit:      1  ERR Interrupt Flag                 */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  MC0:1;            /*!< bit:      4  MC Interrupt Flag 0                */
+    __I uint8_t  MC1:1;            /*!< bit:      5  MC Interrupt Flag 1                */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    __I uint8_t  MC:2;             /*!< bit:  4.. 5  MC Interrupt Flag x                */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET           0x0A         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
+#define TC_INTFLAG_OVF              (_U_(0x1) << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
+#define TC_INTFLAG_ERR              (_U_(0x1) << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
+#define TC_INTFLAG_MC0              (_U_(1) << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
+#define TC_INTFLAG_MC1              (_U_(1) << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
+#define TC_INTFLAG_MC_Msk           (_U_(0x3) << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value)        (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK             _U_(0x33)    /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W  8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STOP:1;           /*!< bit:      0  Stop Status Flag                   */
+    uint8_t  SLAVE:1;          /*!< bit:      1  Slave Status Flag                  */
+    uint8_t  :1;               /*!< bit:      2  Reserved                           */
+    uint8_t  PERBUFV:1;        /*!< bit:      3  Synchronization Busy Status        */
+    uint8_t  CCBUFV0:1;        /*!< bit:      4  Compare channel buffer 0 valid     */
+    uint8_t  CCBUFV1:1;        /*!< bit:      5  Compare channel buffer 1 valid     */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  CCBUFV:2;         /*!< bit:  4.. 5  Compare channel buffer x valid     */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET            0x0B         /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE        _U_(0x01)    /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos          0            /**< \brief (TC_STATUS) Stop Status Flag */
+#define TC_STATUS_STOP              (_U_(0x1) << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos         1            /**< \brief (TC_STATUS) Slave Status Flag */
+#define TC_STATUS_SLAVE             (_U_(0x1) << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_PERBUFV_Pos       3            /**< \brief (TC_STATUS) Synchronization Busy Status */
+#define TC_STATUS_PERBUFV           (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
+#define TC_STATUS_CCBUFV0_Pos       4            /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
+#define TC_STATUS_CCBUFV0           (_U_(1) << TC_STATUS_CCBUFV0_Pos)
+#define TC_STATUS_CCBUFV1_Pos       5            /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
+#define TC_STATUS_CCBUFV1           (_U_(1) << TC_STATUS_CCBUFV1_Pos)
+#define TC_STATUS_CCBUFV_Pos        4            /**< \brief (TC_STATUS) Compare channel buffer x valid */
+#define TC_STATUS_CCBUFV_Msk        (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
+#define TC_STATUS_CCBUFV(value)     (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
+#define TC_STATUS_MASK              _U_(0x3B)    /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W  8) Waveform Generation Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WAVEGEN:2;        /*!< bit:  0.. 1  Waveform Generation Mode           */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_WAVE_OFFSET              0x0C         /**< \brief (TC_WAVE offset) Waveform Generation Control */
+#define TC_WAVE_RESETVALUE          _U_(0x00)    /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
+
+#define TC_WAVE_WAVEGEN_Pos         0            /**< \brief (TC_WAVE) Waveform Generation Mode */
+#define TC_WAVE_WAVEGEN_Msk         (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN(value)      (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
+#define   TC_WAVE_WAVEGEN_NFRQ_Val        _U_(0x0)   /**< \brief (TC_WAVE) Normal frequency */
+#define   TC_WAVE_WAVEGEN_MFRQ_Val        _U_(0x1)   /**< \brief (TC_WAVE) Match frequency */
+#define   TC_WAVE_WAVEGEN_NPWM_Val        _U_(0x2)   /**< \brief (TC_WAVE) Normal PWM */
+#define   TC_WAVE_WAVEGEN_MPWM_Val        _U_(0x3)   /**< \brief (TC_WAVE) Match PWM */
+#define TC_WAVE_WAVEGEN_NFRQ        (TC_WAVE_WAVEGEN_NFRQ_Val      << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_MFRQ        (TC_WAVE_WAVEGEN_MFRQ_Val      << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_NPWM        (TC_WAVE_WAVEGEN_NPWM_Val      << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_WAVEGEN_MPWM        (TC_WAVE_WAVEGEN_MPWM_Val      << TC_WAVE_WAVEGEN_Pos)
+#define TC_WAVE_MASK                _U_(0x03)    /**< \brief (TC_WAVE) MASK Register */
+
+/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W  8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform Invert Enable 0    */
+    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform Invert Enable 1    */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform Invert Enable x    */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DRVCTRL_OFFSET           0x0D         /**< \brief (TC_DRVCTRL offset) Control C */
+#define TC_DRVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (TC_DRVCTRL reset_value) Control C */
+
+#define TC_DRVCTRL_INVEN0_Pos       0            /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
+#define TC_DRVCTRL_INVEN0           (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
+#define TC_DRVCTRL_INVEN1_Pos       1            /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
+#define TC_DRVCTRL_INVEN1           (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
+#define TC_DRVCTRL_INVEN_Pos        0            /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
+#define TC_DRVCTRL_INVEN_Msk        (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
+#define TC_DRVCTRL_INVEN(value)     (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
+#define TC_DRVCTRL_MASK             _U_(0x03)    /**< \brief (TC_DRVCTRL) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET           0x0F         /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE       _U_(0x00)    /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Run During Debug */
+#define TC_DBGCTRL_DBGRUN           (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK             _U_(0x01)    /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/  32) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  swrst                              */
+    uint32_t ENABLE:1;         /*!< bit:      1  enable                             */
+    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB                              */
+    uint32_t STATUS:1;         /*!< bit:      3  STATUS                             */
+    uint32_t COUNT:1;          /*!< bit:      4  Counter                            */
+    uint32_t PER:1;            /*!< bit:      5  Period                             */
+    uint32_t CC0:1;            /*!< bit:      6  Compare Channel 0                  */
+    uint32_t CC1:1;            /*!< bit:      7  Compare Channel 1                  */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t CC:2;             /*!< bit:  6.. 7  Compare Channel x                  */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_SYNCBUSY_OFFSET          0x10         /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
+#define TC_SYNCBUSY_RESETVALUE      _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
+
+#define TC_SYNCBUSY_SWRST_Pos       0            /**< \brief (TC_SYNCBUSY) swrst */
+#define TC_SYNCBUSY_SWRST           (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
+#define TC_SYNCBUSY_ENABLE_Pos      1            /**< \brief (TC_SYNCBUSY) enable */
+#define TC_SYNCBUSY_ENABLE          (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
+#define TC_SYNCBUSY_CTRLB_Pos       2            /**< \brief (TC_SYNCBUSY) CTRLB */
+#define TC_SYNCBUSY_CTRLB           (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
+#define TC_SYNCBUSY_STATUS_Pos      3            /**< \brief (TC_SYNCBUSY) STATUS */
+#define TC_SYNCBUSY_STATUS          (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
+#define TC_SYNCBUSY_COUNT_Pos       4            /**< \brief (TC_SYNCBUSY) Counter */
+#define TC_SYNCBUSY_COUNT           (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
+#define TC_SYNCBUSY_PER_Pos         5            /**< \brief (TC_SYNCBUSY) Period */
+#define TC_SYNCBUSY_PER             (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
+#define TC_SYNCBUSY_CC0_Pos         6            /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
+#define TC_SYNCBUSY_CC0             (_U_(1) << TC_SYNCBUSY_CC0_Pos)
+#define TC_SYNCBUSY_CC1_Pos         7            /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
+#define TC_SYNCBUSY_CC1             (_U_(1) << TC_SYNCBUSY_CC1_Pos)
+#define TC_SYNCBUSY_CC_Pos          6            /**< \brief (TC_SYNCBUSY) Compare Channel x */
+#define TC_SYNCBUSY_CC_Msk          (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
+#define TC_SYNCBUSY_CC(value)       (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
+#define TC_SYNCBUSY_MASK            _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET     0x14         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
+#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000)  /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
+
+#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Counter Value */
+#define TC_COUNT16_COUNT_COUNT_Msk  (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK       _U_(0xFFFF)  /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET     0x14         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
+#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
+
+#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Counter Value */
+#define TC_COUNT32_COUNT_COUNT_Msk  (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK       _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET      0x14         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
+#define TC_COUNT8_COUNT_RESETVALUE  _U_(0x00)    /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
+
+#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk   (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK        _U_(0xFF)    /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W  8) COUNT8 COUNT8 Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET        0x1B         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
+#define TC_COUNT8_PER_RESETVALUE    _U_(0xFF)    /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
+
+#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk       (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value)    (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK          _U_(0xFF)    /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CC:16;            /*!< bit:  0..15  Counter/Compare Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET        0x1C         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
+#define TC_COUNT16_CC_RESETVALUE    _U_(0x0000)  /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
+
+#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
+#define TC_COUNT16_CC_CC_Msk        (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value)     (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK          _U_(0xFFFF)  /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CC:32;            /*!< bit:  0..31  Counter/Compare Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET        0x1C         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
+#define TC_COUNT32_CC_RESETVALUE    _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
+
+#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
+#define TC_COUNT32_CC_CC_Msk        (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value)     (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK          _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W  8) COUNT8 COUNT8 Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CC:8;             /*!< bit:  0.. 7  Counter/Compare Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET         0x1C         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
+#define TC_COUNT8_CC_RESETVALUE     _U_(0x00)    /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
+
+#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
+#define TC_COUNT8_CC_CC_Msk         (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value)      (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK           _U_(0xFF)    /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W  8) COUNT8 COUNT8 Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PERBUF:8;         /*!< bit:  0.. 7  Period Buffer Value                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_PERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PERBUF_OFFSET     0x2F         /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
+#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF)    /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
+
+#define TC_COUNT8_PERBUF_PERBUF_Pos 0            /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
+#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
+#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
+#define TC_COUNT8_PERBUF_MASK       _U_(0xFF)    /**< \brief (TC_COUNT8_PERBUF) MASK Register */
+
+/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CCBUF:16;         /*!< bit:  0..15  Counter/Compare Buffer Value       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TC_COUNT16_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CCBUF_OFFSET     0x30         /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
+#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000)  /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
+
+#define TC_COUNT16_CCBUF_CCBUF_Pos  0            /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT16_CCBUF_CCBUF_Msk  (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
+#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
+#define TC_COUNT16_CCBUF_MASK       _U_(0xFFFF)  /**< \brief (TC_COUNT16_CCBUF) MASK Register */
+
+/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CCBUF:32;         /*!< bit:  0..31  Counter/Compare Buffer Value       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TC_COUNT32_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CCBUF_OFFSET     0x30         /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
+#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
+
+#define TC_COUNT32_CCBUF_CCBUF_Pos  0            /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT32_CCBUF_CCBUF_Msk  (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
+#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
+#define TC_COUNT32_CCBUF_MASK       _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
+
+/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W  8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CCBUF:8;          /*!< bit:  0.. 7  Counter/Compare Buffer Value       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TC_COUNT8_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CCBUF_OFFSET      0x30         /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
+#define TC_COUNT8_CCBUF_RESETVALUE  _U_(0x00)    /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
+
+#define TC_COUNT8_CCBUF_CCBUF_Pos   0            /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
+#define TC_COUNT8_CCBUF_CCBUF_Msk   (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
+#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
+#define TC_COUNT8_CCBUF_MASK        _U_(0xFF)    /**< \brief (TC_COUNT8_CCBUF) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
+  __IO TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status */
+  __IO TC_WAVE_Type              WAVE;        /**< \brief Offset: 0x0C (R/W  8) Waveform Generation Control */
+  __IO TC_DRVCTRL_Type           DRVCTRL;     /**< \brief Offset: 0x0D (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
+  __I  TC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
+  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x14 (R/W  8) COUNT8 Count */
+       RoReg8                    Reserved2[0x6];
+  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x1B (R/W  8) COUNT8 Period */
+  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x1C (R/W  8) COUNT8 Compare and Capture */
+       RoReg8                    Reserved3[0x11];
+  __IO TC_COUNT8_PERBUF_Type     PERBUF;      /**< \brief Offset: 0x2F (R/W  8) COUNT8 Period Buffer */
+  __IO TC_COUNT8_CCBUF_Type      CCBUF[2];    /**< \brief Offset: 0x30 (R/W  8) COUNT8 Compare and Capture Buffer */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
+  __IO TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status */
+  __IO TC_WAVE_Type              WAVE;        /**< \brief Offset: 0x0C (R/W  8) Waveform Generation Control */
+  __IO TC_DRVCTRL_Type           DRVCTRL;     /**< \brief Offset: 0x0D (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
+  __I  TC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
+  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
+       RoReg8                    Reserved2[0x6];
+  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
+       RoReg8                    Reserved3[0x10];
+  __IO TC_COUNT16_CCBUF_Type     CCBUF[2];    /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
+  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
+  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
+  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
+  __IO TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status */
+  __IO TC_WAVE_Type              WAVE;        /**< \brief Offset: 0x0C (R/W  8) Waveform Generation Control */
+  __IO TC_DRVCTRL_Type           DRVCTRL;     /**< \brief Offset: 0x0D (R/W  8) Control C */
+       RoReg8                    Reserved1[0x1];
+  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
+  __I  TC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
+  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
+       RoReg8                    Reserved2[0x4];
+  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
+       RoReg8                    Reserved3[0xC];
+  __IO TC_COUNT32_CCBUF_Type     CCBUF[2];    /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
+       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
+       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_TC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/tcc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/tcc.h
new file mode 100644
index 000000000..fdec3f3d1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/tcc.h	
@@ -0,0 +1,1762 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TCC_COMPONENT_
+#define _SAME53_TCC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAME53_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC                     0x310
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
+    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
+    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
+    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
+    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
+    uint32_t MSYNC:1;          /*!< bit:     15  Master Synchronization (only for TCC Slave Instance) */
+    uint32_t :7;               /*!< bit: 16..22  Reserved                           */
+    uint32_t DMAOS:1;          /*!< bit:     23  DMA One-shot Trigger Mode          */
+    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
+    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
+    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
+    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
+    uint32_t CPTEN4:1;         /*!< bit:     28  Capture Channel 4 Enable           */
+    uint32_t CPTEN5:1;         /*!< bit:     29  Capture Channel 5 Enable           */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
+    uint32_t CPTEN:6;          /*!< bit: 24..29  Capture Channel x Enable           */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE        _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST             (_U_(0x1) << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE            (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk    (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define   TCC_CTRLA_RESOLUTION_NONE_Val   _U_(0x0)   /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define   TCC_CTRLA_RESOLUTION_DITH4_Val  _U_(0x1)   /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH5_Val  _U_(0x2)   /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define   TCC_CTRLA_RESOLUTION_DITH6_Val  _U_(0x3)   /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk     (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define   TCC_CTRLA_PRESCALER_DIV1_Val    _U_(0x0)   /**< \brief (TCC_CTRLA) No division */
+#define   TCC_CTRLA_PRESCALER_DIV2_Val    _U_(0x1)   /**< \brief (TCC_CTRLA) Divide by 2 */
+#define   TCC_CTRLA_PRESCALER_DIV4_Val    _U_(0x2)   /**< \brief (TCC_CTRLA) Divide by 4 */
+#define   TCC_CTRLA_PRESCALER_DIV8_Val    _U_(0x3)   /**< \brief (TCC_CTRLA) Divide by 8 */
+#define   TCC_CTRLA_PRESCALER_DIV16_Val   _U_(0x4)   /**< \brief (TCC_CTRLA) Divide by 16 */
+#define   TCC_CTRLA_PRESCALER_DIV64_Val   _U_(0x5)   /**< \brief (TCC_CTRLA) Divide by 64 */
+#define   TCC_CTRLA_PRESCALER_DIV256_Val  _U_(0x6)   /**< \brief (TCC_CTRLA) Divide by 256 */
+#define   TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7)   /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY          (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk     (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    _U_(0x0)   /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   _U_(0x1)   /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  _U_(0x2)   /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK             (_U_(0x1) << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_MSYNC_Pos         15           /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */
+#define TCC_CTRLA_MSYNC             (_U_(0x1) << TCC_CTRLA_MSYNC_Pos)
+#define TCC_CTRLA_DMAOS_Pos         23           /**< \brief (TCC_CTRLA) DMA One-shot Trigger Mode */
+#define TCC_CTRLA_DMAOS             (_U_(0x1) << TCC_CTRLA_DMAOS_Pos)
+#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0            (_U_(1) << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1            (_U_(1) << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2            (_U_(1) << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3            (_U_(1) << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN4_Pos        28           /**< \brief (TCC_CTRLA) Capture Channel 4 Enable */
+#define TCC_CTRLA_CPTEN4            (_U_(1) << TCC_CTRLA_CPTEN4_Pos)
+#define TCC_CTRLA_CPTEN5_Pos        29           /**< \brief (TCC_CTRLA) Capture Channel 5 Enable */
+#define TCC_CTRLA_CPTEN5            (_U_(1) << TCC_CTRLA_CPTEN5_Pos)
+#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk         (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK              _U_(0x3F80FF63) /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE     _U_(0x00)    /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR            (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD           (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT        (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk     (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0)   /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBCLR_IDXCMD_SET_Val     _U_(0x1)   /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   _U_(0x2)   /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    _U_(0x3)   /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk        (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define   TCC_CTRLBCLR_CMD_NONE_Val       _U_(0x0)   /**< \brief (TCC_CTRLBCLR) No action */
+#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  _U_(0x1)   /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define   TCC_CTRLBCLR_CMD_STOP_Val       _U_(0x2)   /**< \brief (TCC_CTRLBCLR) Force stop */
+#define   TCC_CTRLBCLR_CMD_UPDATE_Val     _U_(0x3)   /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */
+#define   TCC_CTRLBCLR_CMD_READSYNC_Val   _U_(0x4)   /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define   TCC_CTRLBCLR_CMD_DMAOS_Val      _U_(0x5)   /**< \brief (TCC_CTRLBCLR) One-shot DMA trigger */
+#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_DMAOS      (TCC_CTRLBCLR_CMD_DMAOS_Val    << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK           _U_(0xFF)    /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
+    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
+    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
+    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
+    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE     _U_(0x00)    /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR            (_U_(0x1) << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD           (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT        (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk     (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0)   /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define   TCC_CTRLBSET_IDXCMD_SET_Val     _U_(0x1)   /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   _U_(0x2)   /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    _U_(0x3)   /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk        (_U_(0x7) << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define   TCC_CTRLBSET_CMD_NONE_Val       _U_(0x0)   /**< \brief (TCC_CTRLBSET) No action */
+#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  _U_(0x1)   /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define   TCC_CTRLBSET_CMD_STOP_Val       _U_(0x2)   /**< \brief (TCC_CTRLBSET) Force stop */
+#define   TCC_CTRLBSET_CMD_UPDATE_Val     _U_(0x3)   /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */
+#define   TCC_CTRLBSET_CMD_READSYNC_Val   _U_(0x4)   /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define   TCC_CTRLBSET_CMD_DMAOS_Val      _U_(0x5)   /**< \brief (TCC_CTRLBSET) One-shot DMA trigger */
+#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_DMAOS      (TCC_CTRLBSET_CMD_DMAOS_Val    << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK           _U_(0xFF)    /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
+    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
+    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
+    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
+    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
+    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
+    uint32_t PER:1;            /*!< bit:      7  Period Busy                        */
+    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
+    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
+    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
+    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
+    uint32_t CC4:1;            /*!< bit:     12  Compare Channel 4 Busy             */
+    uint32_t CC5:1;            /*!< bit:     13  Compare Channel 5 Busy             */
+    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CC:6;             /*!< bit:  8..13  Compare Channel x Busy             */
+    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST          (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE         (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB          (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS         (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT          (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT           (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE           (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period Busy */
+#define TCC_SYNCBUSY_PER            (_U_(0x1) << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0            (_U_(1) << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1            (_U_(1) << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2            (_U_(1) << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3            (_U_(1) << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC4_Pos        12           /**< \brief (TCC_SYNCBUSY) Compare Channel 4 Busy */
+#define TCC_SYNCBUSY_CC4            (_U_(1) << TCC_SYNCBUSY_CC4_Pos)
+#define TCC_SYNCBUSY_CC5_Pos        13           /**< \brief (TCC_SYNCBUSY) Compare Channel 5 Busy */
+#define TCC_SYNCBUSY_CC5            (_U_(1) << TCC_SYNCBUSY_CC5_Pos)
+#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk         (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_MASK           _U_(0x00003FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
+    uint32_t BLANKPRESC:1;     /*!< bit:     15  Fault A Blanking Prescaler         */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE       _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk          (_U_(0x3) << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define   TCC_FCTRLA_SRC_DISABLE_Val      _U_(0x0)   /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define   TCC_FCTRLA_SRC_ENABLE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_INVERT_Val       _U_(0x2)   /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLA_SRC_ALTFAULT_Val     _U_(0x3)   /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP             (_U_(0x1) << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL             (_U_(0x1) << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk        (_U_(0x3) << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define   TCC_FCTRLA_BLANK_START_Val      _U_(0x0)   /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */
+#define   TCC_FCTRLA_BLANK_RISE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_FALL_Val       _U_(0x2)   /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLA_BLANK_BOTH_Val       _U_(0x3)   /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART          (_U_(0x1) << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk         (_U_(0x3) << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define   TCC_FCTRLA_HALT_DISABLE_Val     _U_(0x0)   /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define   TCC_FCTRLA_HALT_HW_Val          _U_(0x1)   /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define   TCC_FCTRLA_HALT_SW_Val          _U_(0x2)   /**< \brief (TCC_FCTRLA) Software halt action */
+#define   TCC_FCTRLA_HALT_NR_Val          _U_(0x3)   /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk        (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define   TCC_FCTRLA_CHSEL_CC0_Val        _U_(0x0)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define   TCC_FCTRLA_CHSEL_CC1_Val        _U_(0x1)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define   TCC_FCTRLA_CHSEL_CC2_Val        _U_(0x2)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define   TCC_FCTRLA_CHSEL_CC3_Val        _U_(0x3)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk      (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  _U_(0x0)   /**< \brief (TCC_FCTRLA) No capture */
+#define   TCC_FCTRLA_CAPTURE_CAPT_Val     _U_(0x1)   /**< \brief (TCC_FCTRLA) Capture on fault */
+#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  _U_(0x2)   /**< \brief (TCC_FCTRLA) Minimum capture */
+#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  _U_(0x3)   /**< \brief (TCC_FCTRLA) Maximum capture */
+#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   _U_(0x4)   /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   _U_(0x5)   /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   _U_(0x6)   /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7)   /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
+#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKPRESC_Pos   15           /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */
+#define TCC_FCTRLA_BLANKPRESC       (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk     (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk    (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK             _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
+    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
+    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
+    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
+    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
+    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
+    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
+    uint32_t BLANKPRESC:1;     /*!< bit:     15  Fault B Blanking Prescaler         */
+    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
+    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE       _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk          (_U_(0x3) << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define   TCC_FCTRLB_SRC_DISABLE_Val      _U_(0x0)   /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define   TCC_FCTRLB_SRC_ENABLE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_INVERT_Val       _U_(0x2)   /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define   TCC_FCTRLB_SRC_ALTFAULT_Val     _U_(0x3)   /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP             (_U_(0x1) << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL             (_U_(0x1) << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk        (_U_(0x3) << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define   TCC_FCTRLB_BLANK_START_Val      _U_(0x0)   /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */
+#define   TCC_FCTRLB_BLANK_RISE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_FALL_Val       _U_(0x2)   /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define   TCC_FCTRLB_BLANK_BOTH_Val       _U_(0x3)   /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART          (_U_(0x1) << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk         (_U_(0x3) << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define   TCC_FCTRLB_HALT_DISABLE_Val     _U_(0x0)   /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define   TCC_FCTRLB_HALT_HW_Val          _U_(0x1)   /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define   TCC_FCTRLB_HALT_SW_Val          _U_(0x2)   /**< \brief (TCC_FCTRLB) Software halt action */
+#define   TCC_FCTRLB_HALT_NR_Val          _U_(0x3)   /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk        (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define   TCC_FCTRLB_CHSEL_CC0_Val        _U_(0x0)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define   TCC_FCTRLB_CHSEL_CC1_Val        _U_(0x1)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define   TCC_FCTRLB_CHSEL_CC2_Val        _U_(0x2)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define   TCC_FCTRLB_CHSEL_CC3_Val        _U_(0x3)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk      (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  _U_(0x0)   /**< \brief (TCC_FCTRLB) No capture */
+#define   TCC_FCTRLB_CAPTURE_CAPT_Val     _U_(0x1)   /**< \brief (TCC_FCTRLB) Capture on fault */
+#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  _U_(0x2)   /**< \brief (TCC_FCTRLB) Minimum capture */
+#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  _U_(0x3)   /**< \brief (TCC_FCTRLB) Maximum capture */
+#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   _U_(0x4)   /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   _U_(0x5)   /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   _U_(0x6)   /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7)   /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
+#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKPRESC_Pos   15           /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */
+#define TCC_FCTRLB_BLANKPRESC       (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk     (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk    (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK             _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
+    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
+    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
+    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
+    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
+    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
+    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk        (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0          (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1          (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2          (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3          (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk       (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk        (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk        (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK            _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
+    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
+    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
+    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
+    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
+    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
+    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
+    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
+    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
+    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
+    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
+    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
+    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
+    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
+    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
+    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
+    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
+    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
+    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
+    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
+    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
+    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
+    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
+    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
+    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
+    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
+    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
+    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0            (_U_(1) << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1            (_U_(1) << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2            (_U_(1) << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3            (_U_(1) << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4            (_U_(1) << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5            (_U_(1) << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6            (_U_(1) << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7            (_U_(1) << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk         (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0            (_U_(1) << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1            (_U_(1) << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2            (_U_(1) << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3            (_U_(1) << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4            (_U_(1) << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5            (_U_(1) << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6            (_U_(1) << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7            (_U_(1) << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk         (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0          (_U_(1) << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1          (_U_(1) << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2          (_U_(1) << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3          (_U_(1) << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4          (_U_(1) << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5          (_U_(1) << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6          (_U_(1) << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7          (_U_(1) << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk       (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk  (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk  (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK            _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN          (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD           (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK            _U_(0x05)    /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
+    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
+    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
+    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
+    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
+    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
+    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
+    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
+    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
+    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
+    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
+    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
+    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
+    uint32_t MCEI4:1;          /*!< bit:     20  Match or Capture Channel 4 Event Input Enable */
+    uint32_t MCEI5:1;          /*!< bit:     21  Match or Capture Channel 5 Event Input Enable */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
+    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
+    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
+    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
+    uint32_t MCEO4:1;          /*!< bit:     28  Match or Capture Channel 4 Event Output Enable */
+    uint32_t MCEO5:1;          /*!< bit:     29  Match or Capture Channel 5 Event Output Enable */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
+    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
+    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
+    uint32_t MCEI:6;           /*!< bit: 16..21  Match or Capture Channel x Event Input Enable */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t MCEO:6;           /*!< bit: 24..29  Match or Capture Channel x Event Output Enable */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk       (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define   TCC_EVCTRL_EVACT0_OFF_Val       _U_(0x0)   /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1)   /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   _U_(0x2)   /**< \brief (TCC_EVCTRL) Count on event */
+#define   TCC_EVCTRL_EVACT0_START_Val     _U_(0x3)   /**< \brief (TCC_EVCTRL) Start counter on event */
+#define   TCC_EVCTRL_EVACT0_INC_Val       _U_(0x4)   /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define   TCC_EVCTRL_EVACT0_COUNT_Val     _U_(0x5)   /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define   TCC_EVCTRL_EVACT0_STAMP_Val     _U_(0x6)   /**< \brief (TCC_EVCTRL) Stamp capture */
+#define   TCC_EVCTRL_EVACT0_FAULT_Val     _U_(0x7)   /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk       (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define   TCC_EVCTRL_EVACT1_OFF_Val       _U_(0x0)   /**< \brief (TCC_EVCTRL) Event action disabled */
+#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1)   /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define   TCC_EVCTRL_EVACT1_DIR_Val       _U_(0x2)   /**< \brief (TCC_EVCTRL) Direction control */
+#define   TCC_EVCTRL_EVACT1_STOP_Val      _U_(0x3)   /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define   TCC_EVCTRL_EVACT1_DEC_Val       _U_(0x4)   /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define   TCC_EVCTRL_EVACT1_PPW_Val       _U_(0x5)   /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define   TCC_EVCTRL_EVACT1_PWP_Val       _U_(0x6)   /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define   TCC_EVCTRL_EVACT1_FAULT_Val     _U_(0x7)   /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk       (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define   TCC_EVCTRL_CNTSEL_START_Val     _U_(0x0)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define   TCC_EVCTRL_CNTSEL_END_Val       _U_(0x1)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   _U_(0x2)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  _U_(0x3)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO            (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO            (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO            (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0           (_U_(1) << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1           (_U_(1) << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk        (_U_(0x3) << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0            (_U_(1) << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1            (_U_(1) << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk         (_U_(0x3) << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0            (_U_(1) << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1            (_U_(1) << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2            (_U_(1) << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3            (_U_(1) << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI4_Pos        20           /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable */
+#define TCC_EVCTRL_MCEI4            (_U_(1) << TCC_EVCTRL_MCEI4_Pos)
+#define TCC_EVCTRL_MCEI5_Pos        21           /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable */
+#define TCC_EVCTRL_MCEI5            (_U_(1) << TCC_EVCTRL_MCEI5_Pos)
+#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk         (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0            (_U_(1) << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1            (_U_(1) << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2            (_U_(1) << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3            (_U_(1) << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO4_Pos        28           /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable */
+#define TCC_EVCTRL_MCEO4            (_U_(1) << TCC_EVCTRL_MCEO4_Pos)
+#define TCC_EVCTRL_MCEO5_Pos        29           /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable */
+#define TCC_EVCTRL_MCEO5            (_U_(1) << TCC_EVCTRL_MCEO5_Pos)
+#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk         (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK             _U_(0x3F3FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t MC4:1;            /*!< bit:     20  Match or Capture Channel 4 Interrupt Enable */
+    uint32_t MC5:1;            /*!< bit:     21  Match or Capture Channel 5 Interrupt Enable */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:6;             /*!< bit: 16..21  Match or Capture Channel x Interrupt Enable */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE     _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF            (_U_(0x1) << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG            (_U_(0x1) << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT            (_U_(0x1) << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR            (_U_(0x1) << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENCLR_UFS            (_U_(0x1) << TCC_INTENCLR_UFS_Pos)
+#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS            (_U_(0x1) << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA         (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB         (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0         (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1         (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0            (_U_(1) << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1            (_U_(1) << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2            (_U_(1) << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3            (_U_(1) << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC4_Pos        20           /**< \brief (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable */
+#define TCC_INTENCLR_MC4            (_U_(1) << TCC_INTENCLR_MC4_Pos)
+#define TCC_INTENCLR_MC5_Pos        21           /**< \brief (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable */
+#define TCC_INTENCLR_MC5            (_U_(1) << TCC_INTENCLR_MC5_Pos)
+#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk         (_U_(0x3F) << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK           _U_(0x003FFC0F) /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
+    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
+    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
+    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
+    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
+    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
+    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
+    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
+    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
+    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
+    uint32_t MC4:1;            /*!< bit:     20  Match or Capture Channel 4 Interrupt Enable */
+    uint32_t MC5:1;            /*!< bit:     21  Match or Capture Channel 5 Interrupt Enable */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t MC:6;             /*!< bit: 16..21  Match or Capture Channel x Interrupt Enable */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE     _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF            (_U_(0x1) << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG            (_U_(0x1) << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT            (_U_(0x1) << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR            (_U_(0x1) << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
+#define TCC_INTENSET_UFS            (_U_(0x1) << TCC_INTENSET_UFS_Pos)
+#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS            (_U_(0x1) << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA         (_U_(0x1) << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB         (_U_(0x1) << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0         (_U_(0x1) << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1         (_U_(0x1) << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0            (_U_(1) << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1            (_U_(1) << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2            (_U_(1) << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3            (_U_(1) << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC4_Pos        20           /**< \brief (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable */
+#define TCC_INTENSET_MC4            (_U_(1) << TCC_INTENSET_MC4_Pos)
+#define TCC_INTENSET_MC5_Pos        21           /**< \brief (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable */
+#define TCC_INTENSET_MC5            (_U_(1) << TCC_INTENSET_MC5_Pos)
+#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk         (_U_(0x3F) << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK           _U_(0x003FFC0F) /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
+    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
+    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
+    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
+    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
+    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
+    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
+    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
+    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
+    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
+    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
+    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
+    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
+    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
+    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
+    __I uint32_t MC4:1;            /*!< bit:     20  Match or Capture 4                 */
+    __I uint32_t MC5:1;            /*!< bit:     21  Match or Capture 5                 */
+    __I uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    __I uint32_t MC:6;             /*!< bit: 16..21  Match or Capture x                 */
+    __I uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE      _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF             (_U_(0x1) << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG             (_U_(0x1) << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT             (_U_(0x1) << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR             (_U_(0x1) << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
+#define TCC_INTFLAG_UFS             (_U_(0x1) << TCC_INTFLAG_UFS_Pos)
+#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS             (_U_(0x1) << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA          (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB          (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0          (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1          (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0             (_U_(1) << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1             (_U_(1) << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2             (_U_(1) << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3             (_U_(1) << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC4_Pos         20           /**< \brief (TCC_INTFLAG) Match or Capture 4 */
+#define TCC_INTFLAG_MC4             (_U_(1) << TCC_INTFLAG_MC4_Pos)
+#define TCC_INTFLAG_MC5_Pos         21           /**< \brief (TCC_INTFLAG) Match or Capture 5 */
+#define TCC_INTFLAG_MC5             (_U_(1) << TCC_INTFLAG_MC5_Pos)
+#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk          (_U_(0x3F) << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK            _U_(0x003FFC0F) /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
+    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
+    uint32_t UFS:1;            /*!< bit:      2  Non-recoverable Update Fault State */
+    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
+    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
+    uint32_t PATTBUFV:1;       /*!< bit:      5  Pattern Buffer Valid               */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t PERBUFV:1;        /*!< bit:      7  Period Buffer Valid                */
+    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
+    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
+    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
+    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
+    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
+    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
+    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
+    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
+    uint32_t CCBUFV0:1;        /*!< bit:     16  Compare Channel 0 Buffer Valid     */
+    uint32_t CCBUFV1:1;        /*!< bit:     17  Compare Channel 1 Buffer Valid     */
+    uint32_t CCBUFV2:1;        /*!< bit:     18  Compare Channel 2 Buffer Valid     */
+    uint32_t CCBUFV3:1;        /*!< bit:     19  Compare Channel 3 Buffer Valid     */
+    uint32_t CCBUFV4:1;        /*!< bit:     20  Compare Channel 4 Buffer Valid     */
+    uint32_t CCBUFV5:1;        /*!< bit:     21  Compare Channel 5 Buffer Valid     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
+    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
+    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
+    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
+    uint32_t CMP4:1;           /*!< bit:     28  Compare Channel 4 Value            */
+    uint32_t CMP5:1;           /*!< bit:     29  Compare Channel 5 Value            */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t CCBUFV:6;         /*!< bit: 16..21  Compare Channel x Buffer Valid     */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t CMP:6;            /*!< bit: 24..29  Compare Channel x Value            */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE       _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP             (_U_(0x1) << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX              (_U_(0x1) << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */
+#define TCC_STATUS_UFS              (_U_(0x1) << TCC_STATUS_UFS_Pos)
+#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS              (_U_(0x1) << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE            (_U_(0x1) << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBUFV_Pos     5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBUFV         (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos)
+#define TCC_STATUS_PERBUFV_Pos      7            /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBUFV          (_U_(0x1) << TCC_STATUS_PERBUFV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN         (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN         (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN         (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN         (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA           (_U_(0x1) << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB           (_U_(0x1) << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0           (_U_(0x1) << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1           (_U_(0x1) << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBUFV0_Pos      16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBUFV0          (_U_(1) << TCC_STATUS_CCBUFV0_Pos)
+#define TCC_STATUS_CCBUFV1_Pos      17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBUFV1          (_U_(1) << TCC_STATUS_CCBUFV1_Pos)
+#define TCC_STATUS_CCBUFV2_Pos      18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBUFV2          (_U_(1) << TCC_STATUS_CCBUFV2_Pos)
+#define TCC_STATUS_CCBUFV3_Pos      19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBUFV3          (_U_(1) << TCC_STATUS_CCBUFV3_Pos)
+#define TCC_STATUS_CCBUFV4_Pos      20           /**< \brief (TCC_STATUS) Compare Channel 4 Buffer Valid */
+#define TCC_STATUS_CCBUFV4          (_U_(1) << TCC_STATUS_CCBUFV4_Pos)
+#define TCC_STATUS_CCBUFV5_Pos      21           /**< \brief (TCC_STATUS) Compare Channel 5 Buffer Valid */
+#define TCC_STATUS_CCBUFV5          (_U_(1) << TCC_STATUS_CCBUFV5_Pos)
+#define TCC_STATUS_CCBUFV_Pos       16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBUFV_Msk       (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos)
+#define TCC_STATUS_CCBUFV(value)    (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))
+#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0             (_U_(1) << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1             (_U_(1) << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2             (_U_(1) << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3             (_U_(1) << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP4_Pos         28           /**< \brief (TCC_STATUS) Compare Channel 4 Value */
+#define TCC_STATUS_CMP4             (_U_(1) << TCC_STATUS_CMP4_Pos)
+#define TCC_STATUS_CMP5_Pos         29           /**< \brief (TCC_STATUS) Compare Channel 5 Value */
+#define TCC_STATUS_CMP5             (_U_(1) << TCC_STATUS_CMP5_Pos)
+#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk          (_U_(0x3F) << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK             _U_(0x3F3FFFBF) /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
+    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
+    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE        _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk   (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK        _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk   (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK        _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk   (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK        _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk         (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK              _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
+    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
+    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
+    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
+    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
+    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
+    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
+    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
+    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
+    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
+    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
+    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
+    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
+    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
+    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
+    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
+    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE         _U_(0x0000)  /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0               (_U_(1) << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1               (_U_(1) << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2               (_U_(1) << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3               (_U_(1) << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4               (_U_(1) << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5               (_U_(1) << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6               (_U_(1) << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7               (_U_(1) << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk            (_U_(0xFF) << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0               (_U_(1) << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1               (_U_(1) << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2               (_U_(1) << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3               (_U_(1) << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4               (_U_(1) << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5               (_U_(1) << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6               (_U_(1) << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7               (_U_(1) << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk            (_U_(0xFF) << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK               _U_(0xFFFF)  /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
+    uint32_t :1;               /*!< bit:      3  Reserved                           */
+    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
+    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
+    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
+    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
+    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
+    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
+    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
+    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
+    uint32_t POL4:1;           /*!< bit:     20  Channel 4 Polarity                 */
+    uint32_t POL5:1;           /*!< bit:     21  Channel 5 Polarity                 */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
+    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
+    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
+    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t POL:6;            /*!< bit: 16..21  Channel x Polarity                 */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE         _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk        (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define   TCC_WAVE_WAVEGEN_NFRQ_Val       _U_(0x0)   /**< \brief (TCC_WAVE) Normal frequency */
+#define   TCC_WAVE_WAVEGEN_MFRQ_Val       _U_(0x1)   /**< \brief (TCC_WAVE) Match frequency */
+#define   TCC_WAVE_WAVEGEN_NPWM_Val       _U_(0x2)   /**< \brief (TCC_WAVE) Normal PWM */
+#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4)   /**< \brief (TCC_WAVE) Dual-slope critical */
+#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   _U_(0x5)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     _U_(0x6)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define   TCC_WAVE_WAVEGEN_DSTOP_Val      _U_(0x7)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk           (_U_(0x3) << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define   TCC_WAVE_RAMP_RAMP1_Val         _U_(0x0)   /**< \brief (TCC_WAVE) RAMP1 operation */
+#define   TCC_WAVE_RAMP_RAMP2A_Val        _U_(0x1)   /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2_Val         _U_(0x2)   /**< \brief (TCC_WAVE) RAMP2 operation */
+#define   TCC_WAVE_RAMP_RAMP2C_Val        _U_(0x3)   /**< \brief (TCC_WAVE) Critical RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN            (_U_(0x1) << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0            (_U_(1) << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1            (_U_(1) << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2            (_U_(1) << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3            (_U_(1) << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk         (_U_(0xF) << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0               (_U_(1) << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1               (_U_(1) << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2               (_U_(1) << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3               (_U_(1) << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL4_Pos           20           /**< \brief (TCC_WAVE) Channel 4 Polarity */
+#define TCC_WAVE_POL4               (_U_(1) << TCC_WAVE_POL4_Pos)
+#define TCC_WAVE_POL5_Pos           21           /**< \brief (TCC_WAVE) Channel 5 Polarity */
+#define TCC_WAVE_POL5               (_U_(1) << TCC_WAVE_POL5_Pos)
+#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk            (_U_(0x3F) << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0              (_U_(1) << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1              (_U_(1) << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2              (_U_(1) << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3              (_U_(1) << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk           (_U_(0xF) << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK               _U_(0x0F3F0FB7) /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHER:4;         /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHER:5;         /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHER:6;         /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE          _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHER_Pos    0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHER_Msk    (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos)
+#define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))
+#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk       (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK          _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHER_Pos    0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHER_Msk    (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos)
+#define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))
+#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk       (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK          _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHER_Pos    0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHER_Msk    (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos)
+#define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))
+#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk       (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK          _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk             (_U_(0xFFFFFF) << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK                _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHER:4;         /*!< bit:  0.. 3  Dithering Cycle Number             */
+    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHER:5;         /*!< bit:  0.. 4  Dithering Cycle Number             */
+    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHER:6;         /*!< bit:  0.. 5  Dithering Cycle Number             */
+    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE           _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHER_Pos     0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHER_Msk     (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos)
+#define TCC_CC_DITH4_DITHER(value)  (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))
+#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk         (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK           _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHER_Pos     0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHER_Msk     (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos)
+#define TCC_CC_DITH5_DITHER(value)  (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))
+#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk         (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK           _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHER_Pos     0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHER_Msk     (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos)
+#define TCC_CC_DITH6_DITHER(value)  (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))
+#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk         (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK           _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk               (_U_(0xFFFFFF) << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK                 _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
+    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
+    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
+    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
+    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
+    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
+    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
+    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
+    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
+    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
+    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
+    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
+    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
+    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
+    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
+    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
+    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} TCC_PATTBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTBUF_OFFSET          0x64         /**< \brief (TCC_PATTBUF offset) Pattern Buffer */
+#define TCC_PATTBUF_RESETVALUE      _U_(0x0000)  /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */
+
+#define TCC_PATTBUF_PGEB0_Pos       0            /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB0           (_U_(1) << TCC_PATTBUF_PGEB0_Pos)
+#define TCC_PATTBUF_PGEB1_Pos       1            /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB1           (_U_(1) << TCC_PATTBUF_PGEB1_Pos)
+#define TCC_PATTBUF_PGEB2_Pos       2            /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB2           (_U_(1) << TCC_PATTBUF_PGEB2_Pos)
+#define TCC_PATTBUF_PGEB3_Pos       3            /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB3           (_U_(1) << TCC_PATTBUF_PGEB3_Pos)
+#define TCC_PATTBUF_PGEB4_Pos       4            /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB4           (_U_(1) << TCC_PATTBUF_PGEB4_Pos)
+#define TCC_PATTBUF_PGEB5_Pos       5            /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB5           (_U_(1) << TCC_PATTBUF_PGEB5_Pos)
+#define TCC_PATTBUF_PGEB6_Pos       6            /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB6           (_U_(1) << TCC_PATTBUF_PGEB6_Pos)
+#define TCC_PATTBUF_PGEB7_Pos       7            /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTBUF_PGEB7           (_U_(1) << TCC_PATTBUF_PGEB7_Pos)
+#define TCC_PATTBUF_PGEB_Pos        0            /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTBUF_PGEB_Msk        (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos)
+#define TCC_PATTBUF_PGEB(value)     (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))
+#define TCC_PATTBUF_PGVB0_Pos       8            /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */
+#define TCC_PATTBUF_PGVB0           (_U_(1) << TCC_PATTBUF_PGVB0_Pos)
+#define TCC_PATTBUF_PGVB1_Pos       9            /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */
+#define TCC_PATTBUF_PGVB1           (_U_(1) << TCC_PATTBUF_PGVB1_Pos)
+#define TCC_PATTBUF_PGVB2_Pos       10           /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */
+#define TCC_PATTBUF_PGVB2           (_U_(1) << TCC_PATTBUF_PGVB2_Pos)
+#define TCC_PATTBUF_PGVB3_Pos       11           /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */
+#define TCC_PATTBUF_PGVB3           (_U_(1) << TCC_PATTBUF_PGVB3_Pos)
+#define TCC_PATTBUF_PGVB4_Pos       12           /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */
+#define TCC_PATTBUF_PGVB4           (_U_(1) << TCC_PATTBUF_PGVB4_Pos)
+#define TCC_PATTBUF_PGVB5_Pos       13           /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */
+#define TCC_PATTBUF_PGVB5           (_U_(1) << TCC_PATTBUF_PGVB5_Pos)
+#define TCC_PATTBUF_PGVB6_Pos       14           /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */
+#define TCC_PATTBUF_PGVB6           (_U_(1) << TCC_PATTBUF_PGVB6_Pos)
+#define TCC_PATTBUF_PGVB7_Pos       15           /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */
+#define TCC_PATTBUF_PGVB7           (_U_(1) << TCC_PATTBUF_PGVB7_Pos)
+#define TCC_PATTBUF_PGVB_Pos        8            /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */
+#define TCC_PATTBUF_PGVB_Msk        (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos)
+#define TCC_PATTBUF_PGVB(value)     (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))
+#define TCC_PATTBUF_MASK            _U_(0xFFFF)  /**< \brief (TCC_PATTBUF) MASK Register */
+
+/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t DITHERBUF:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
+    uint32_t PERBUF:20;        /*!< bit:  4..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERBUF:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t PERBUF:19;        /*!< bit:  5..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERBUF:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t PERBUF:18;        /*!< bit:  6..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t PERBUF:24;        /*!< bit:  0..23  Period Buffer Value                */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_PERBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERBUF_OFFSET           0x6C         /**< \brief (TCC_PERBUF offset) Period Buffer */
+#define TCC_PERBUF_RESETVALUE       _U_(0xFFFFFFFF) /**< \brief (TCC_PERBUF reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0            /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH4_PERBUF_Pos 4            /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */
+#define TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)
+#define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))
+#define TCC_PERBUF_DITH4_MASK       _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0            /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH5_PERBUF_Pos 5            /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */
+#define TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos)
+#define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))
+#define TCC_PERBUF_DITH5_MASK       _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0            /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)
+#define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
+#define TCC_PERBUF_DITH6_PERBUF_Pos 6            /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */
+#define TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos)
+#define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))
+#define TCC_PERBUF_DITH6_MASK       _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH6) MASK Register */
+
+#define TCC_PERBUF_PERBUF_Pos       0            /**< \brief (TCC_PERBUF) Period Buffer Value */
+#define TCC_PERBUF_PERBUF_Msk       (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos)
+#define TCC_PERBUF_PERBUF(value)    (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))
+#define TCC_PERBUF_MASK             _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF) MASK Register */
+
+/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct { // DITH4 mode
+    uint32_t CCBUF:4;          /*!< bit:  0.. 3  Channel Compare/Capture Buffer Value */
+    uint32_t DITHERBUF:20;     /*!< bit:  4..23  Dithering Buffer Cycle Number      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH4;                     /*!< Structure used for DITH4                        */
+  struct { // DITH5 mode
+    uint32_t DITHERBUF:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
+    uint32_t CCBUF:19;         /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH5;                     /*!< Structure used for DITH5                        */
+  struct { // DITH6 mode
+    uint32_t DITHERBUF:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
+    uint32_t CCBUF:18;         /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } DITH6;                     /*!< Structure used for DITH6                        */
+  struct {
+    uint32_t CCBUF:24;         /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TCC_CCBUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCBUF_OFFSET            0x70         /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */
+#define TCC_CCBUF_RESETVALUE        _U_(0x00000000) /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCBUF_DITH4_CCBUF_Pos   0            /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH4_CCBUF_Msk   (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos)
+#define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))
+#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4            /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH4_MASK        _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0            /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH5_CCBUF_Pos   5            /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH5_CCBUF_Msk   (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos)
+#define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))
+#define TCC_CCBUF_DITH5_MASK        _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0            /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)
+#define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
+#define TCC_CCBUF_DITH6_CCBUF_Pos   6            /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_DITH6_CCBUF_Msk   (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos)
+#define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))
+#define TCC_CCBUF_DITH6_MASK        _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH6) MASK Register */
+
+#define TCC_CCBUF_CCBUF_Pos         0            /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */
+#define TCC_CCBUF_CCBUF_Msk         (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos)
+#define TCC_CCBUF_CCBUF(value)      (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))
+#define TCC_CCBUF_MASK              _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
+  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
+       RoReg8                    Reserved1[0x2];
+  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+       RoReg8                    Reserved2[0x2];
+  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x1];
+  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
+  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
+  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
+  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
+       RoReg8                    Reserved4[0x2];
+  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
+  __IO TCC_CC_Type               CC[6];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+       RoReg8                    Reserved5[0x8];
+  __IO TCC_PATTBUF_Type          PATTBUF;     /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+       RoReg8                    Reserved6[0x6];
+  __IO TCC_PERBUF_Type           PERBUF;      /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+  __IO TCC_CCBUF_Type            CCBUF[6];    /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_TCC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/trng.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/trng.h
new file mode 100644
index 000000000..ae35e0ae4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/trng.h	
@@ -0,0 +1,172 @@
+/**
+ * \file
+ *
+ * \brief Component description for TRNG
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TRNG_COMPONENT_
+#define _SAME53_TRNG_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR TRNG */
+/* ========================================================================== */
+/** \addtogroup SAME53_TRNG True Random Generator */
+/*@{*/
+
+#define TRNG_U2242
+#define REV_TRNG                    0x110
+
+/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TRNG_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_CTRLA_OFFSET           0x00         /**< \brief (TRNG_CTRLA offset) Control A */
+#define TRNG_CTRLA_RESETVALUE       _U_(0x00)    /**< \brief (TRNG_CTRLA reset_value) Control A */
+
+#define TRNG_CTRLA_ENABLE_Pos       1            /**< \brief (TRNG_CTRLA) Enable */
+#define TRNG_CTRLA_ENABLE           (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
+#define TRNG_CTRLA_RUNSTDBY_Pos     6            /**< \brief (TRNG_CTRLA) Run in Standby */
+#define TRNG_CTRLA_RUNSTDBY         (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
+#define TRNG_CTRLA_MASK             _U_(0x42)    /**< \brief (TRNG_CTRLA) MASK Register */
+
+/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATARDYEO:1;      /*!< bit:      0  Data Ready Event Output            */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TRNG_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_EVCTRL_OFFSET          0x04         /**< \brief (TRNG_EVCTRL offset) Event Control */
+#define TRNG_EVCTRL_RESETVALUE      _U_(0x00)    /**< \brief (TRNG_EVCTRL reset_value) Event Control */
+
+#define TRNG_EVCTRL_DATARDYEO_Pos   0            /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
+#define TRNG_EVCTRL_DATARDYEO       (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
+#define TRNG_EVCTRL_MASK            _U_(0x01)    /**< \brief (TRNG_EVCTRL) MASK Register */
+
+/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATARDY:1;        /*!< bit:      0  Data Ready Interrupt Enable        */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TRNG_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTENCLR_OFFSET        0x08         /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
+#define TRNG_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TRNG_INTENCLR_DATARDY_Pos   0            /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
+#define TRNG_INTENCLR_DATARDY       (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
+#define TRNG_INTENCLR_MASK          _U_(0x01)    /**< \brief (TRNG_INTENCLR) MASK Register */
+
+/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DATARDY:1;        /*!< bit:      0  Data Ready Interrupt Enable        */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TRNG_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTENSET_OFFSET        0x09         /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
+#define TRNG_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
+
+#define TRNG_INTENSET_DATARDY_Pos   0            /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
+#define TRNG_INTENSET_DATARDY       (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
+#define TRNG_INTENSET_MASK          _U_(0x01)    /**< \brief (TRNG_INTENSET) MASK Register */
+
+/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  DATARDY:1;        /*!< bit:      0  Data Ready Interrupt Flag          */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} TRNG_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_INTFLAG_OFFSET         0x0A         /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TRNG_INTFLAG_RESETVALUE     _U_(0x00)    /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TRNG_INTFLAG_DATARDY_Pos    0            /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
+#define TRNG_INTFLAG_DATARDY        (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
+#define TRNG_INTFLAG_MASK           _U_(0x01)    /**< \brief (TRNG_INTFLAG) MASK Register */
+
+/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/  32) Output Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Output Data                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} TRNG_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TRNG_DATA_OFFSET            0x20         /**< \brief (TRNG_DATA offset) Output Data */
+#define TRNG_DATA_RESETVALUE        _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
+
+#define TRNG_DATA_DATA_Pos          0            /**< \brief (TRNG_DATA) Output Data */
+#define TRNG_DATA_DATA_Msk          (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
+#define TRNG_DATA_DATA(value)       (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
+#define TRNG_DATA_MASK              _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
+
+/** \brief TRNG hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO TRNG_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x3];
+  __IO TRNG_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x04 (R/W  8) Event Control */
+       RoReg8                    Reserved2[0x3];
+  __IO TRNG_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
+  __IO TRNG_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
+  __IO TRNG_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved3[0x15];
+  __I  TRNG_DATA_Type            DATA;        /**< \brief Offset: 0x20 (R/  32) Output Data */
+} Trng;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_TRNG_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/usb.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/usb.h
new file mode 100644
index 000000000..cb8a8c61e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/usb.h	
@@ -0,0 +1,1777 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_USB_COMPONENT_
+#define _SAME53_USB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAME53_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB                     0x120
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby Mode                */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  MODE:1;           /*!< bit:      7  Operating Mode                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET            0x000        /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos         0            /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST             (_U_(0x1) << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos        1            /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE            (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos      2            /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY          (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos          7            /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE              (_U_(0x1) << USB_CTRLA_MODE_Pos)
+#define   USB_CTRLA_MODE_DEVICE_Val       _U_(0x0)   /**< \brief (USB_CTRLA) Device Mode */
+#define   USB_CTRLA_MODE_HOST_Val         _U_(0x1)   /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE       (USB_CTRLA_MODE_DEVICE_Val     << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST         (USB_CTRLA_MODE_HOST_Val       << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK              _U_(0x87)    /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/   8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET         0x002        /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE     _U_(0x00)    /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos      0            /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST          (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos     1            /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE         (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK           _U_(0x03)    /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W  8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CQOS:2;           /*!< bit:  0.. 1  Configuration Quality of Service   */
+    uint8_t  DQOS:2;           /*!< bit:  2.. 3  Data Quality of Service            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET          0x003        /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE      _U_(0x0F)    /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos        0            /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk        (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value)     (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define USB_QOSCTRL_DQOS_Pos        2            /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk        (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value)     (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define USB_QOSCTRL_MASK            _U_(0x0F)    /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DETACH:1;         /*!< bit:      0  Detach                             */
+    uint16_t UPRSM:1;          /*!< bit:      1  Upstream Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration                */
+    uint16_t NREPLY:1;         /*!< bit:      4  No Reply                           */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t TSTPCKT:1;        /*!< bit:      7  Test packet mode                   */
+    uint16_t OPMODE2:1;        /*!< bit:      8  Specific Operational Mode          */
+    uint16_t GNAK:1;           /*!< bit:      9  Global NAK                         */
+    uint16_t LPMHDSK:2;        /*!< bit: 10..11  Link Power Management Handshake    */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET     0x008        /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001)  /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0            /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH     (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos  1            /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM      (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2            /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0)   /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1)   /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2)   /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3)   /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4            /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY     (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos   5            /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ       (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos   6            /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK       (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7            /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT    (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8            /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2    (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos   9            /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK       (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10           /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0)   /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1)   /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2)   /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3)   /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK       _U_(0x0FFF)  /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t RESUME:1;         /*!< bit:      1  Send USB Resume                    */
+    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration for Host       */
+    uint16_t AUTORESUME:1;     /*!< bit:      4  Auto Resume Enable                 */
+    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
+    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t SOFE:1;           /*!< bit:      8  Start of Frame Generation Enable   */
+    uint16_t BUSRESET:1;       /*!< bit:      9  Send USB Reset                     */
+    uint16_t VBUSOK:1;         /*!< bit:     10  VBUS is OK                         */
+    uint16_t L1RESUME:1;       /*!< bit:     11  Send L1 Resume                     */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET       0x008        /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE   _U_(0x0000)  /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos   1            /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME       (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos  2            /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk  (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0)   /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define   USB_HOST_CTRLB_SPDCONF_FS_Val   _U_(0x3)   /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS   (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_AUTORESUME_Pos 4            /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */
+#define USB_HOST_CTRLB_AUTORESUME   (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos     5            /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ         (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos     6            /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK         (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos     8            /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE         (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9            /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET     (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos   10           /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK       (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11           /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME     (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK         _U_(0x0F7E)  /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DADD:7;           /*!< bit:  0.. 6  Device Address                     */
+    uint8_t  ADDEN:1;          /*!< bit:      7  Device Address Enable              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET      0x00A        /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE  _U_(0x00)    /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos    0            /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk    (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos   7            /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN       (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK        _U_(0xFF)    /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W  8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENC:4;          /*!< bit:  0.. 3  Frame Length Control               */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  FLENCE:1;         /*!< bit:      7  Frame Length Control Enable        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET       0x00A        /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE   _U_(0x00)    /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos    0            /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk    (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos   7            /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE       (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK         _U_(0x8F)    /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/   8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET    0x00C        /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE _U_(0x40)    /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2            /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define   USB_DEVICE_STATUS_SPEED_FS_Val  _U_(0x0)   /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_LS_Val  _U_(0x1)   /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define   USB_DEVICE_STATUS_SPEED_HS_Val  _U_(0x2)   /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS  (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS  (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS  (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6            /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define   USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0)   /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define   USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1)   /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define   USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2)   /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK      _U_(0xCC)    /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W  8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET      0x00C        /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE  _U_(0x00)    /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos   2            /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk   (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6            /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK        _U_(0xCC)    /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/   8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FSMSTATE:7;       /*!< bit:  0.. 6  Fine State Machine Status          */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET        0x00D        /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE    _U_(0x01)    /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos  0            /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk  (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define   USB_FSMSTATUS_FSMSTATE_OFF_Val  _U_(0x1)   /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define   USB_FSMSTATUS_FSMSTATE_ON_Val   _U_(0x2)   /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4)   /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8)   /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10)   /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20)   /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define   USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40)   /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF  (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON   (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK          _U_(0x7F)    /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/  16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :1;               /*!< bit:     14  Reserved                           */
+    uint16_t FNCERR:1;         /*!< bit:     15  Frame Number CRC Error             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET      0x010        /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE  _U_(0x0000)  /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos   0            /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk   (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos    3            /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk    (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos  15           /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR      (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK        _U_(0xBFFF)  /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
+    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET        0x010        /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE    _U_(0x0000)  /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos     0            /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk     (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value)  (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos      3            /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk      (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value)   (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK          _U_(0x3FFF)  /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/   8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLENHIGH:8;       /*!< bit:  0.. 7  Frame Length                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET    0x012        /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0            /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK      _U_(0xFF)    /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET  0x014        /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF    (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF     (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST   (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP  (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM   (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM   (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK    _U_(0x03FF)  /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Disable */
+    uint16_t RST:1;            /*!< bit:      3  BUS Reset Interrupt Disable        */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Disable          */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to Device Interrupt Disable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from Device Interrupt Disable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Disable       */
+    uint16_t DCONN:1;          /*!< bit:      8  Device Connection Interrupt Disable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Disable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET    0x014        /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos  2            /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF      (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos   3            /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST       (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP    (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM     (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM     (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER   (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8            /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN     (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9            /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC     (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK      _U_(0x03FC)  /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
+    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
+    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
+    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
+    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET  0x018        /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF    (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF     (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST   (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP  (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM   (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM   (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK    _U_(0x03FF)  /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Enable */
+    uint16_t RST:1;            /*!< bit:      3  Bus Reset Interrupt Enable         */
+    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
+    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to the Device Interrupt Enable */
+    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume fromthe device Interrupt Enable */
+    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
+    uint16_t DCONN:1;          /*!< bit:      8  Link Power Management Interrupt Enable */
+    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Enable */
+    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET    0x018        /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos  2            /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF      (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos   3            /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST       (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP    (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM     (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM     (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER   (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8            /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN     (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9            /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC     (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK      _U_(0x03FC)  /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
+    __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
+    __I uint16_t SOF:1;            /*!< bit:      2  Start Of Frame                     */
+    __I uint16_t EORST:1;          /*!< bit:      3  End of Reset                       */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t EORSM:1;          /*!< bit:      5  End Of Resume                      */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume                    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet      */
+    __I uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend      */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET   0x01C        /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND  (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF     (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos  2            /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF      (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3            /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST    (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP   (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM    (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM    (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER  (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET  (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP  (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK     _U_(0x03FF)  /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
+    __I uint16_t RST:1;            /*!< bit:      3  Bus Reset                          */
+    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
+    __I uint16_t DNRSM:1;          /*!< bit:      5  Downstream                         */
+    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from the Device    */
+    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
+    __I uint16_t DCONN:1;          /*!< bit:      8  Device Connection                  */
+    __I uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection               */
+    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET     0x01C        /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos   2            /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF       (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos    3            /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST        (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP     (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos  5            /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM      (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos  6            /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM      (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER    (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos  8            /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN      (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos  9            /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC      (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK       _U_(0x03FC)  /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/  16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  End Point 0 Interrupt              */
+    uint16_t EPINT1:1;         /*!< bit:      1  End Point 1 Interrupt              */
+    uint16_t EPINT2:1;         /*!< bit:      2  End Point 2 Interrupt              */
+    uint16_t EPINT3:1;         /*!< bit:      3  End Point 3 Interrupt              */
+    uint16_t EPINT4:1;         /*!< bit:      4  End Point 4 Interrupt              */
+    uint16_t EPINT5:1;         /*!< bit:      5  End Point 5 Interrupt              */
+    uint16_t EPINT6:1;         /*!< bit:      6  End Point 6 Interrupt              */
+    uint16_t EPINT7:1;         /*!< bit:      7  End Point 7 Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  End Point x Interrupt              */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020        /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK   _U_(0x00FF)  /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/  16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t EPINT0:1;         /*!< bit:      0  Pipe 0 Interrupt                   */
+    uint16_t EPINT1:1;         /*!< bit:      1  Pipe 1 Interrupt                   */
+    uint16_t EPINT2:1;         /*!< bit:      2  Pipe 2 Interrupt                   */
+    uint16_t EPINT3:1;         /*!< bit:      3  Pipe 3 Interrupt                   */
+    uint16_t EPINT4:1;         /*!< bit:      4  Pipe 4 Interrupt                   */
+    uint16_t EPINT5:1;         /*!< bit:      5  Pipe 5 Interrupt                   */
+    uint16_t EPINT6:1;         /*!< bit:      6  Pipe 6 Interrupt                   */
+    uint16_t EPINT7:1;         /*!< bit:      7  Pipe 7 Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t EPINT:8;          /*!< bit:  0.. 7  Pipe x Interrupt                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET    0x020        /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0    (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1            /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1    (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2            /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2    (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3            /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3    (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4            /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4    (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5            /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5    (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6            /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6    (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7            /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7    (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK      _U_(0x00FF)  /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DESCADD:32;       /*!< bit:  0..31  Descriptor Address Value           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET          0x024        /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE      _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos     0            /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk     (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value)  (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK            _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t TRANSP:5;         /*!< bit:  0.. 4  USB Pad Transp calibration         */
+    uint16_t :1;               /*!< bit:      5  Reserved                           */
+    uint16_t TRANSN:5;         /*!< bit:  6..10  USB Pad Transn calibration         */
+    uint16_t :1;               /*!< bit:     11  Reserved                           */
+    uint16_t TRIM:3;           /*!< bit: 12..14  USB Pad Trim calibration           */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET           0x028        /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE       _U_(0x0000)  /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos       0            /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk       (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value)    (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos       6            /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk       (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value)    (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos         12           /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk         (_U_(0x7) << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value)      (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK             _U_(0x77DF)  /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EPTYPE0:3;        /*!< bit:  0.. 2  End Point Type0                    */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  EPTYPE1:3;        /*!< bit:  4.. 6  End Point Type1                    */
+    uint8_t  NYETDIS:1;        /*!< bit:      7  NYET Token Disable                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET     0x100        /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0            /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4            /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7            /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS    (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK       _U_(0xF7)    /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W  8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PTOKEN:2;         /*!< bit:  0.. 1  Pipe Token                         */
+    uint8_t  BK:1;             /*!< bit:      2  Pipe Bank                          */
+    uint8_t  PTYPE:3;          /*!< bit:  3.. 5  Pipe Type                          */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET        0x100        /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE    _U_(0x00)    /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos    0            /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk    (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos        2            /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK            (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos     3            /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk     (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value)  (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK          _U_(0x3F)    /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W  8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BITINTERVAL:8;    /*!< bit:  0.. 7  Bit Interval                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET   0x103        /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0            /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK     _U_(0xFF)    /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Clear              */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Clear               */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Clear                 */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Clear              */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Clear              */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Clear              */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104        /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7)    /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W  8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle clear                  */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank clear                  */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Clear                  */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET  0x104        /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL    (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK   (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY  (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY  (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK    _U_(0xD5)    /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Set                */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Set                 */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Set                */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Set                */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Set                */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105        /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7)    /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W  8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle Set                    */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Set                    */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET  0x105        /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL    (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK   (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY  (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY  (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK    _U_(0xD5)    /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/   8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle Out                    */
+    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle In                     */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request                    */
+    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request                    */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
+    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request                    */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET  0x106        /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN  (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK   (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY  (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY  (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK    _U_(0xF7)    /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/   8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle                        */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
+    uint8_t  :1;               /*!< bit:      3  Reserved                           */
+    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze                        */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
+    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET     0x106        /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos   0            /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL       (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos  2            /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK      (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE    (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY     (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY     (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK       _U_(0xD5)    /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
+    __I uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0                       */
+    __I uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1                       */
+    __I uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup                     */
+    __I uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out                     */
+    __I uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x                */
+    __I uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x                       */
+    __I uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    __I uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out                     */
+    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107        /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP  (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK   _U_(0x7F)    /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
+    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
+    __I uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Flag          */
+    __I uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Flag          */
+    __I uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Flag     */
+    __I uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Flag               */
+    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Flag */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET    0x107        /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0    (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1    (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL    (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos  3            /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR      (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP     (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5            /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL     (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK      _U_(0x3F)    /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Disable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Disable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Disable     */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Disable     */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Disable   */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/Out Interrupt Disable   */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Disable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Disable     */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/Out Interrupt Disable   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108        /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK  _U_(0x7F)    /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Disable        */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Disable        */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Disable       */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Disable       */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit Setup Interrupt Disable   */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Inetrrupt Disable            */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Disable        */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET   0x108        /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0   (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1   (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL   (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3            /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR     (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP    (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5            /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL    (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK     _U_(0x3F)    /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Enable      */
+    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Enable      */
+    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Enable    */
+    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out Interrupt enable    */
+    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Enable      */
+    uint8_t  :1;               /*!< bit:      4  Reserved                           */
+    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out Interrupt enable    */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109        /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK  _U_(0x7F)    /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
+    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
+    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Enable        */
+    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Enable        */
+    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Enable   */
+    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Enable             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET   0x109        /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0   (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1   (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL   (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3            /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR     (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP    (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5            /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL    (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK     _U_(0x3F)    /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET      0x000        /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos    0            /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk    (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK        _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET        0x000        /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos      0            /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk      (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value)   (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK          _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Enpoint size                       */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET   0x004        /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28           /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK     _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
+    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
+    uint32_t SIZE:3;           /*!< bit: 28..30  Pipe size                          */
+    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET     0x004        /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos   28           /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk   (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP   (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK       _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET    0x008        /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0            /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK      _U_(0x7FFF)  /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
+    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
+    uint16_t :1;               /*!< bit:     15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET      0x008        /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos  0            /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk  (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK        _U_(0x7FFF)  /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A        /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK   _U_(0x03)    /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W  8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
+    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET   0x00A        /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR   (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK     _U_(0x03)    /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PDADDR:7;         /*!< bit:  0.. 6  Pipe Device Adress                 */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t PEPNUM:4;         /*!< bit:  8..11  Pipe Endpoint Number               */
+    uint16_t PERMAX:4;         /*!< bit: 12..15  Pipe Error Max Number              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET   0x00C        /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12           /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK     _U_(0xFF7F)  /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DTGLER:1;         /*!< bit:      0  Data Toggle Error                  */
+    uint16_t DAPIDER:1;        /*!< bit:      1  Data PID Error                     */
+    uint16_t PIDER:1;          /*!< bit:      2  PID Error                          */
+    uint16_t TOUTER:1;         /*!< bit:      3  Time Out Error                     */
+    uint16_t CRC16ER:1;        /*!< bit:      4  CRC16 Error                        */
+    uint16_t ERCNT:3;          /*!< bit:  5.. 7  Pipe Error Count                   */
+    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E        /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0            /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1            /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2            /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER  (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3            /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4            /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5            /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK   _U_(0x00FF)  /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_ADDR_Type      ADDR;        /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+  __IO USB_DEVICE_PCKSIZE_Type   PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+  __IO USB_DEVICE_EXTREG_Type    EXTREG;      /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+  __IO USB_DEVICE_STATUS_BK_Type STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+       RoReg8                    Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_ADDR_Type        ADDR;        /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+  __IO USB_HOST_PCKSIZE_Type     PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+  __IO USB_HOST_EXTREG_Type      EXTREG;      /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+  __IO USB_HOST_STATUS_BK_Type   STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
+       RoReg8                    Reserved1[0x1];
+  __IO USB_HOST_CTRL_PIPE_Type   CTRL_PIPE;   /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+  __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_DEVICE_EPCFG_Type     EPCFG;       /**< \brief Offset: 0x000 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
+       RoReg8                    Reserved1[0x3];
+  __O  USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+  __O  USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
+  __I  USB_DEVICE_EPSTATUS_Type  EPSTATUS;    /**< \brief Offset: 0x006 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
+  __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG;   /**< \brief Offset: 0x007 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
+  __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR;  /**< \brief Offset: 0x008 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+  __IO USB_DEVICE_EPINTENSET_Type EPINTENSET;  /**< \brief Offset: 0x009 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+       RoReg8                    Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO USB_HOST_PCFG_Type        PCFG;        /**< \brief Offset: 0x000 (R/W  8) HOST_PIPE End Point Configuration */
+       RoReg8                    Reserved1[0x2];
+  __IO USB_HOST_BINTERVAL_Type   BINTERVAL;   /**< \brief Offset: 0x003 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
+  __O  USB_HOST_PSTATUSCLR_Type  PSTATUSCLR;  /**< \brief Offset: 0x004 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
+  __O  USB_HOST_PSTATUSSET_Type  PSTATUSSET;  /**< \brief Offset: 0x005 ( /W  8) HOST_PIPE End Point Pipe Status Set */
+  __I  USB_HOST_PSTATUS_Type     PSTATUS;     /**< \brief Offset: 0x006 (R/   8) HOST_PIPE End Point Pipe Status */
+  __IO USB_HOST_PINTFLAG_Type    PINTFLAG;    /**< \brief Offset: 0x007 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
+  __IO USB_HOST_PINTENCLR_Type   PINTENCLR;   /**< \brief Offset: 0x008 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
+  __IO USB_HOST_PINTENSET_Type   PINTENSET;   /**< \brief Offset: 0x009 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
+       RoReg8                    Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_DEVICE_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+  __IO USB_DEVICE_DADD_Type      DADD;        /**< \brief Offset: 0x00A (R/W  8) DEVICE Device Address */
+       RoReg8                    Reserved3[0x1];
+  __I  USB_DEVICE_STATUS_Type    STATUS;      /**< \brief Offset: 0x00C (R/   8) DEVICE Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __I  USB_DEVICE_FNUM_Type      FNUM;        /**< \brief Offset: 0x010 (R/  16) DEVICE Device Frame Number */
+       RoReg8                    Reserved5[0x2];
+  __IO USB_DEVICE_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_DEVICE_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_DEVICE_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_DEVICE_EPINTSMRY_Type EPINTSMRY;   /**< \brief Offset: 0x020 (R/  16) DEVICE End Point Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbDeviceEndpoint         DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
+       RoReg8                    Reserved1[0x1];
+  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
+  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
+       RoReg8                    Reserved2[0x4];
+  __IO USB_HOST_CTRLB_Type       CTRLB;       /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+  __IO USB_HOST_HSOFC_Type       HSOFC;       /**< \brief Offset: 0x00A (R/W  8) HOST Host Start Of Frame Control */
+       RoReg8                    Reserved3[0x1];
+  __IO USB_HOST_STATUS_Type      STATUS;      /**< \brief Offset: 0x00C (R/W  8) HOST Status */
+  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
+       RoReg8                    Reserved4[0x2];
+  __IO USB_HOST_FNUM_Type        FNUM;        /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+  __I  USB_HOST_FLENHIGH_Type    FLENHIGH;    /**< \brief Offset: 0x012 (R/   8) HOST Host Frame Length */
+       RoReg8                    Reserved5[0x1];
+  __IO USB_HOST_INTENCLR_Type    INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+       RoReg8                    Reserved6[0x2];
+  __IO USB_HOST_INTENSET_Type    INTENSET;    /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+       RoReg8                    Reserved7[0x2];
+  __IO USB_HOST_INTFLAG_Type     INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+       RoReg8                    Reserved8[0x2];
+  __I  USB_HOST_PINTSMRY_Type    PINTSMRY;    /**< \brief Offset: 0x020 (R/  16) HOST Pipe Interrupt Summary */
+       RoReg8                    Reserved9[0x2];
+  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+       RoReg8                    Reserved10[0xD6];
+       UsbHostPipe               HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+       UsbDeviceDescBank         DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+       UsbHostDescBank           HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+       UsbDevice                 DEVICE;      /**< \brief Offset: 0x000 USB is Device */
+       UsbHost                   HOST;        /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_USB_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/wdt.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/wdt.h
new file mode 100644
index 000000000..0421d2b89
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/component/wdt.h	
@@ -0,0 +1,300 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_WDT_COMPONENT_
+#define _SAME53_WDT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAME53_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2251
+#define REV_WDT                     0x110
+
+/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
+    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
+    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRLA_OFFSET            0x0          /**< \brief (WDT_CTRLA offset) Control */
+#define WDT_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (WDT_CTRLA reset_value) Control */
+
+#define WDT_CTRLA_ENABLE_Pos        1            /**< \brief (WDT_CTRLA) Enable */
+#define WDT_CTRLA_ENABLE            (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
+#define WDT_CTRLA_WEN_Pos           2            /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
+#define WDT_CTRLA_WEN               (_U_(0x1) << WDT_CTRLA_WEN_Pos)
+#define WDT_CTRLA_ALWAYSON_Pos      7            /**< \brief (WDT_CTRLA) Always-On */
+#define WDT_CTRLA_ALWAYSON          (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
+#define WDT_CTRLA_MASK              _U_(0x86)    /**< \brief (WDT_CTRLA) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
+    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE       _U_(0xBB)    /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk          (_U_(0xF) << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value)       (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define   WDT_CONFIG_PER_CYC8_Val         _U_(0x0)   /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_PER_CYC16_Val        _U_(0x1)   /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_PER_CYC32_Val        _U_(0x2)   /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_PER_CYC64_Val        _U_(0x3)   /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_PER_CYC128_Val       _U_(0x4)   /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_PER_CYC256_Val       _U_(0x5)   /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_PER_CYC512_Val       _U_(0x6)   /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_PER_CYC1024_Val      _U_(0x7)   /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_PER_CYC2048_Val      _U_(0x8)   /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_PER_CYC4096_Val      _U_(0x9)   /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_PER_CYC8192_Val      _U_(0xA)   /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_PER_CYC16384_Val     _U_(0xB)   /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_CYC8         (WDT_CONFIG_PER_CYC8_Val       << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC16        (WDT_CONFIG_PER_CYC16_Val      << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC32        (WDT_CONFIG_PER_CYC32_Val      << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC64        (WDT_CONFIG_PER_CYC64_Val      << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC128       (WDT_CONFIG_PER_CYC128_Val     << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC256       (WDT_CONFIG_PER_CYC256_Val     << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC512       (WDT_CONFIG_PER_CYC512_Val     << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC1024      (WDT_CONFIG_PER_CYC1024_Val    << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC2048      (WDT_CONFIG_PER_CYC2048_Val    << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC4096      (WDT_CONFIG_PER_CYC4096_Val    << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC8192      (WDT_CONFIG_PER_CYC8192_Val    << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_CYC16384     (WDT_CONFIG_PER_CYC16384_Val   << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk       (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value)    (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define   WDT_CONFIG_WINDOW_CYC8_Val      _U_(0x0)   /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC16_Val     _U_(0x1)   /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC32_Val     _U_(0x2)   /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC64_Val     _U_(0x3)   /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC128_Val    _U_(0x4)   /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC256_Val    _U_(0x5)   /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC512_Val    _U_(0x6)   /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC1024_Val   _U_(0x7)   /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC2048_Val   _U_(0x8)   /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC4096_Val   _U_(0x9)   /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC8192_Val   _U_(0xA)   /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define   WDT_CONFIG_WINDOW_CYC16384_Val  _U_(0xB)   /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_CYC8      (WDT_CONFIG_WINDOW_CYC8_Val    << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC16     (WDT_CONFIG_WINDOW_CYC16_Val   << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC32     (WDT_CONFIG_WINDOW_CYC32_Val   << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC64     (WDT_CONFIG_WINDOW_CYC64_Val   << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC128    (WDT_CONFIG_WINDOW_CYC128_Val  << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC256    (WDT_CONFIG_WINDOW_CYC256_Val  << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC512    (WDT_CONFIG_WINDOW_CYC512_Val  << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC1024   (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC2048   (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC4096   (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC8192   (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_CYC16384  (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK             _U_(0xFF)    /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE       _U_(0x0B)    /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk     (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value)  (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define   WDT_EWCTRL_EWOFFSET_CYC8_Val    _U_(0x0)   /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC16_Val   _U_(0x1)   /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC32_Val   _U_(0x2)   /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC64_Val   _U_(0x3)   /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC128_Val  _U_(0x4)   /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC256_Val  _U_(0x5)   /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC512_Val  _U_(0x6)   /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7)   /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8)   /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9)   /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA)   /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define   WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB)   /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_CYC8    (WDT_EWCTRL_EWOFFSET_CYC8_Val  << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC16   (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC32   (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC64   (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC128  (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC256  (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC512  (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK             _U_(0x0F)    /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW             (_U_(0x1) << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK           _U_(0x01)    /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW             (_U_(0x1) << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK           _U_(0x01)    /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW              (_U_(0x1) << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK            _U_(0x01)    /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint32_t WEN:1;            /*!< bit:      2  Window Enable Synchronization Busy */
+    uint32_t ALWAYSON:1;       /*!< bit:      3  Always-On Synchronization Busy     */
+    uint32_t CLEAR:1;          /*!< bit:      4  Clear Synchronization Busy         */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} WDT_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_SYNCBUSY_OFFSET         0x8          /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
+#define WDT_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
+
+#define WDT_SYNCBUSY_ENABLE_Pos     1            /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
+#define WDT_SYNCBUSY_ENABLE         (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
+#define WDT_SYNCBUSY_WEN_Pos        2            /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
+#define WDT_SYNCBUSY_WEN            (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
+#define WDT_SYNCBUSY_ALWAYSON_Pos   3            /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
+#define WDT_SYNCBUSY_ALWAYSON       (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
+#define WDT_SYNCBUSY_CLEAR_Pos      4            /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
+#define WDT_SYNCBUSY_CLEAR          (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
+#define WDT_SYNCBUSY_MASK           _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W  8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET            0xC          /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE        _U_(0x00)    /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk         (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value)      (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define   WDT_CLEAR_CLEAR_KEY_Val         _U_(0xA5)   /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK              _U_(0xFF)    /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO WDT_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control */
+  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
+  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
+       RoReg8                    Reserved1[0x1];
+  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
+  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
+  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved2[0x1];
+  __I  WDT_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x8 (R/  32) Synchronization Busy */
+  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0xC ( /W  8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAME53_WDT_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ac.h
new file mode 100644
index 000000000..4a541d6ef
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ac.h	
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_AC_INSTANCE_
+#define _SAME53_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA               (0x42002000) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (0x42002001) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (0x42002002) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (0x42002004) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (0x42002005) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (0x42002006) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (0x42002007) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (0x42002008) /**< \brief (AC) Status B */
+#define REG_AC_DBGCTRL             (0x42002009) /**< \brief (AC) Debug Control */
+#define REG_AC_WINCTRL             (0x4200200A) /**< \brief (AC) Window Control */
+#define REG_AC_SCALER0             (0x4200200C) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (0x4200200D) /**< \brief (AC) Scaler 1 */
+#define REG_AC_COMPCTRL0           (0x42002010) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (0x42002014) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SYNCBUSY            (0x42002020) /**< \brief (AC) Synchronization Busy */
+#define REG_AC_CALIB               (0x42002024) /**< \brief (AC) Calibration */
+#else
+#define REG_AC_CTRLA               (*(RwReg8 *)0x42002000UL) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB               (*(WoReg8 *)0x42002001UL) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL              (*(RwReg16*)0x42002002UL) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR            (*(RwReg8 *)0x42002004UL) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET            (*(RwReg8 *)0x42002005UL) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG             (*(RwReg8 *)0x42002006UL) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA             (*(RoReg8 *)0x42002007UL) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB             (*(RoReg8 *)0x42002008UL) /**< \brief (AC) Status B */
+#define REG_AC_DBGCTRL             (*(RwReg8 *)0x42002009UL) /**< \brief (AC) Debug Control */
+#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200200AUL) /**< \brief (AC) Window Control */
+#define REG_AC_SCALER0             (*(RwReg8 *)0x4200200CUL) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1             (*(RwReg8 *)0x4200200DUL) /**< \brief (AC) Scaler 1 */
+#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42002010UL) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42002014UL) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SYNCBUSY            (*(RoReg  *)0x42002020UL) /**< \brief (AC) Synchronization Busy */
+#define REG_AC_CALIB               (*(RwReg16*)0x42002024UL) /**< \brief (AC) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_COMPCTRL_MUXNEG_OPAMP    7        // OPAMP selection for MUXNEG
+#define AC_FUSES_BIAS1                       // PAIR1 Bias Calibration
+#define AC_GCLK_ID                  32       // Index of Generic Clock
+#define AC_IMPLEMENTS_VDBLR         0        // VDoubler implemented ?
+#define AC_NUM_CMP                  2        // Number of comparators
+#define AC_PAIRS                    1        // Number of pairs of comparators
+#define AC_SPEED_LEVELS             2        // Number of speed values
+
+#endif /* _SAME53_AC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/adc0.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/adc0.h
new file mode 100644
index 000000000..eaaae5873
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/adc0.h	
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC0
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_ADC0_INSTANCE_
+#define _SAME53_ADC0_INSTANCE_
+
+/* ========== Register definition for ADC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC0_CTRLA             (0x43001C00) /**< \brief (ADC0) Control A */
+#define REG_ADC0_EVCTRL            (0x43001C02) /**< \brief (ADC0) Event Control */
+#define REG_ADC0_DBGCTRL           (0x43001C03) /**< \brief (ADC0) Debug Control */
+#define REG_ADC0_INPUTCTRL         (0x43001C04) /**< \brief (ADC0) Input Control */
+#define REG_ADC0_CTRLB             (0x43001C06) /**< \brief (ADC0) Control B */
+#define REG_ADC0_REFCTRL           (0x43001C08) /**< \brief (ADC0) Reference Control */
+#define REG_ADC0_AVGCTRL           (0x43001C0A) /**< \brief (ADC0) Average Control */
+#define REG_ADC0_SAMPCTRL          (0x43001C0B) /**< \brief (ADC0) Sample Time Control */
+#define REG_ADC0_WINLT             (0x43001C0C) /**< \brief (ADC0) Window Monitor Lower Threshold */
+#define REG_ADC0_WINUT             (0x43001C0E) /**< \brief (ADC0) Window Monitor Upper Threshold */
+#define REG_ADC0_GAINCORR          (0x43001C10) /**< \brief (ADC0) Gain Correction */
+#define REG_ADC0_OFFSETCORR        (0x43001C12) /**< \brief (ADC0) Offset Correction */
+#define REG_ADC0_SWTRIG            (0x43001C14) /**< \brief (ADC0) Software Trigger */
+#define REG_ADC0_INTENCLR          (0x43001C2C) /**< \brief (ADC0) Interrupt Enable Clear */
+#define REG_ADC0_INTENSET          (0x43001C2D) /**< \brief (ADC0) Interrupt Enable Set */
+#define REG_ADC0_INTFLAG           (0x43001C2E) /**< \brief (ADC0) Interrupt Flag Status and Clear */
+#define REG_ADC0_STATUS            (0x43001C2F) /**< \brief (ADC0) Status */
+#define REG_ADC0_SYNCBUSY          (0x43001C30) /**< \brief (ADC0) Synchronization Busy */
+#define REG_ADC0_DSEQDATA          (0x43001C34) /**< \brief (ADC0) DMA Sequencial Data */
+#define REG_ADC0_DSEQCTRL          (0x43001C38) /**< \brief (ADC0) DMA Sequential Control */
+#define REG_ADC0_DSEQSTAT          (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */
+#define REG_ADC0_RESULT            (0x43001C40) /**< \brief (ADC0) Result Conversion Value */
+#define REG_ADC0_RESS              (0x43001C44) /**< \brief (ADC0) Last Sample Result */
+#define REG_ADC0_CALIB             (0x43001C48) /**< \brief (ADC0) Calibration */
+#else
+#define REG_ADC0_CTRLA             (*(RwReg16*)0x43001C00UL) /**< \brief (ADC0) Control A */
+#define REG_ADC0_EVCTRL            (*(RwReg8 *)0x43001C02UL) /**< \brief (ADC0) Event Control */
+#define REG_ADC0_DBGCTRL           (*(RwReg8 *)0x43001C03UL) /**< \brief (ADC0) Debug Control */
+#define REG_ADC0_INPUTCTRL         (*(RwReg16*)0x43001C04UL) /**< \brief (ADC0) Input Control */
+#define REG_ADC0_CTRLB             (*(RwReg16*)0x43001C06UL) /**< \brief (ADC0) Control B */
+#define REG_ADC0_REFCTRL           (*(RwReg8 *)0x43001C08UL) /**< \brief (ADC0) Reference Control */
+#define REG_ADC0_AVGCTRL           (*(RwReg8 *)0x43001C0AUL) /**< \brief (ADC0) Average Control */
+#define REG_ADC0_SAMPCTRL          (*(RwReg8 *)0x43001C0BUL) /**< \brief (ADC0) Sample Time Control */
+#define REG_ADC0_WINLT             (*(RwReg16*)0x43001C0CUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
+#define REG_ADC0_WINUT             (*(RwReg16*)0x43001C0EUL) /**< \brief (ADC0) Window Monitor Upper Threshold */
+#define REG_ADC0_GAINCORR          (*(RwReg16*)0x43001C10UL) /**< \brief (ADC0) Gain Correction */
+#define REG_ADC0_OFFSETCORR        (*(RwReg16*)0x43001C12UL) /**< \brief (ADC0) Offset Correction */
+#define REG_ADC0_SWTRIG            (*(RwReg8 *)0x43001C14UL) /**< \brief (ADC0) Software Trigger */
+#define REG_ADC0_INTENCLR          (*(RwReg8 *)0x43001C2CUL) /**< \brief (ADC0) Interrupt Enable Clear */
+#define REG_ADC0_INTENSET          (*(RwReg8 *)0x43001C2DUL) /**< \brief (ADC0) Interrupt Enable Set */
+#define REG_ADC0_INTFLAG           (*(RwReg8 *)0x43001C2EUL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
+#define REG_ADC0_STATUS            (*(RoReg8 *)0x43001C2FUL) /**< \brief (ADC0) Status */
+#define REG_ADC0_SYNCBUSY          (*(RoReg  *)0x43001C30UL) /**< \brief (ADC0) Synchronization Busy */
+#define REG_ADC0_DSEQDATA          (*(WoReg  *)0x43001C34UL) /**< \brief (ADC0) DMA Sequencial Data */
+#define REG_ADC0_DSEQCTRL          (*(RwReg  *)0x43001C38UL) /**< \brief (ADC0) DMA Sequential Control */
+#define REG_ADC0_DSEQSTAT          (*(RoReg  *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Status */
+#define REG_ADC0_RESULT            (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion Value */
+#define REG_ADC0_RESS              (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result */
+#define REG_ADC0_CALIB             (*(RwReg16*)0x43001C48UL) /**< \brief (ADC0) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC0 peripheral ========== */
+#define ADC0_BANDGAP                27       // MUXPOS value to select BANDGAP
+#define ADC0_CTAT                   29       // MUXPOS value to select CTAT
+#define ADC0_DMAC_ID_RESRDY         68       // index of DMA RESRDY trigger
+#define ADC0_DMAC_ID_SEQ            69       // Index of DMA SEQ trigger
+#define ADC0_EXTCHANNEL_MSB         15       // Number of external channels
+#define ADC0_GCLK_ID                40       // index of Generic Clock
+#define ADC0_MASTER_SLAVE_MODE      1        // ADC Master/Slave Mode
+#define ADC0_OPAMP2                 0        // MUXPOS value to select OPAMP2
+#define ADC0_OPAMP01                0        // MUXPOS value to select OPAMP01
+#define ADC0_PTAT                   28       // MUXPOS value to select PTAT
+#define ADC0_TOUCH_IMPLEMENTED      1        // TOUCH implemented or not
+
+#endif /* _SAME53_ADC0_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/adc1.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/adc1.h
new file mode 100644
index 000000000..d0dcb68c5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/adc1.h	
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC1
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_ADC1_INSTANCE_
+#define _SAME53_ADC1_INSTANCE_
+
+/* ========== Register definition for ADC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC1_CTRLA             (0x43002000) /**< \brief (ADC1) Control A */
+#define REG_ADC1_EVCTRL            (0x43002002) /**< \brief (ADC1) Event Control */
+#define REG_ADC1_DBGCTRL           (0x43002003) /**< \brief (ADC1) Debug Control */
+#define REG_ADC1_INPUTCTRL         (0x43002004) /**< \brief (ADC1) Input Control */
+#define REG_ADC1_CTRLB             (0x43002006) /**< \brief (ADC1) Control B */
+#define REG_ADC1_REFCTRL           (0x43002008) /**< \brief (ADC1) Reference Control */
+#define REG_ADC1_AVGCTRL           (0x4300200A) /**< \brief (ADC1) Average Control */
+#define REG_ADC1_SAMPCTRL          (0x4300200B) /**< \brief (ADC1) Sample Time Control */
+#define REG_ADC1_WINLT             (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */
+#define REG_ADC1_WINUT             (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */
+#define REG_ADC1_GAINCORR          (0x43002010) /**< \brief (ADC1) Gain Correction */
+#define REG_ADC1_OFFSETCORR        (0x43002012) /**< \brief (ADC1) Offset Correction */
+#define REG_ADC1_SWTRIG            (0x43002014) /**< \brief (ADC1) Software Trigger */
+#define REG_ADC1_INTENCLR          (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */
+#define REG_ADC1_INTENSET          (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */
+#define REG_ADC1_INTFLAG           (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */
+#define REG_ADC1_STATUS            (0x4300202F) /**< \brief (ADC1) Status */
+#define REG_ADC1_SYNCBUSY          (0x43002030) /**< \brief (ADC1) Synchronization Busy */
+#define REG_ADC1_DSEQDATA          (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */
+#define REG_ADC1_DSEQCTRL          (0x43002038) /**< \brief (ADC1) DMA Sequential Control */
+#define REG_ADC1_DSEQSTAT          (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */
+#define REG_ADC1_RESULT            (0x43002040) /**< \brief (ADC1) Result Conversion Value */
+#define REG_ADC1_RESS              (0x43002044) /**< \brief (ADC1) Last Sample Result */
+#define REG_ADC1_CALIB             (0x43002048) /**< \brief (ADC1) Calibration */
+#else
+#define REG_ADC1_CTRLA             (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */
+#define REG_ADC1_EVCTRL            (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */
+#define REG_ADC1_DBGCTRL           (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */
+#define REG_ADC1_INPUTCTRL         (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */
+#define REG_ADC1_CTRLB             (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */
+#define REG_ADC1_REFCTRL           (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */
+#define REG_ADC1_AVGCTRL           (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */
+#define REG_ADC1_SAMPCTRL          (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */
+#define REG_ADC1_WINLT             (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
+#define REG_ADC1_WINUT             (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */
+#define REG_ADC1_GAINCORR          (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */
+#define REG_ADC1_OFFSETCORR        (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */
+#define REG_ADC1_SWTRIG            (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */
+#define REG_ADC1_INTENCLR          (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */
+#define REG_ADC1_INTENSET          (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */
+#define REG_ADC1_INTFLAG           (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
+#define REG_ADC1_STATUS            (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */
+#define REG_ADC1_SYNCBUSY          (*(RoReg  *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */
+#define REG_ADC1_DSEQDATA          (*(WoReg  *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */
+#define REG_ADC1_DSEQCTRL          (*(RwReg  *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */
+#define REG_ADC1_DSEQSTAT          (*(RoReg  *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */
+#define REG_ADC1_RESULT            (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */
+#define REG_ADC1_RESS              (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */
+#define REG_ADC1_CALIB             (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC1 peripheral ========== */
+#define ADC1_BANDGAP                27       // MUXPOS value to select BANDGAP
+#define ADC1_CTAT                   29       // MUXPOS value to select CTAT
+#define ADC1_DMAC_ID_RESRDY         70       // Index of DMA RESRDY trigger
+#define ADC1_DMAC_ID_SEQ            71       // Index of DMA SEQ trigger
+#define ADC1_EXTCHANNEL_MSB         15       // Number of external channels
+#define ADC1_GCLK_ID                41       // Index of Generic Clock
+#define ADC1_MASTER_SLAVE_MODE      2        // ADC Master/Slave Mode
+#define ADC1_OPAMP2                 0        // MUXPOS value to select OPAMP2
+#define ADC1_OPAMP01                0        // MUXPOS value to select OPAMP01
+#define ADC1_PTAT                   28       // MUXPOS value to select PTAT
+#define ADC1_TOUCH_IMPLEMENTED      0        // TOUCH implemented or not
+#define ADC1_TOUCH_LINES_NUM        1        // Number of touch lines
+
+#endif /* _SAME53_ADC1_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/aes.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/aes.h
new file mode 100644
index 000000000..8e36a4222
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/aes.h	
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AES
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_AES_INSTANCE_
+#define _SAME53_AES_INSTANCE_
+
+/* ========== Register definition for AES peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AES_CTRLA              (0x42002400) /**< \brief (AES) Control A */
+#define REG_AES_CTRLB              (0x42002404) /**< \brief (AES) Control B */
+#define REG_AES_INTENCLR           (0x42002405) /**< \brief (AES) Interrupt Enable Clear */
+#define REG_AES_INTENSET           (0x42002406) /**< \brief (AES) Interrupt Enable Set */
+#define REG_AES_INTFLAG            (0x42002407) /**< \brief (AES) Interrupt Flag Status */
+#define REG_AES_DATABUFPTR         (0x42002408) /**< \brief (AES) Data buffer pointer */
+#define REG_AES_DBGCTRL            (0x42002409) /**< \brief (AES) Debug control */
+#define REG_AES_KEYWORD0           (0x4200240C) /**< \brief (AES) Keyword 0 */
+#define REG_AES_KEYWORD1           (0x42002410) /**< \brief (AES) Keyword 1 */
+#define REG_AES_KEYWORD2           (0x42002414) /**< \brief (AES) Keyword 2 */
+#define REG_AES_KEYWORD3           (0x42002418) /**< \brief (AES) Keyword 3 */
+#define REG_AES_KEYWORD4           (0x4200241C) /**< \brief (AES) Keyword 4 */
+#define REG_AES_KEYWORD5           (0x42002420) /**< \brief (AES) Keyword 5 */
+#define REG_AES_KEYWORD6           (0x42002424) /**< \brief (AES) Keyword 6 */
+#define REG_AES_KEYWORD7           (0x42002428) /**< \brief (AES) Keyword 7 */
+#define REG_AES_INDATA             (0x42002438) /**< \brief (AES) Indata */
+#define REG_AES_INTVECTV0          (0x4200243C) /**< \brief (AES) Initialisation Vector 0 */
+#define REG_AES_INTVECTV1          (0x42002440) /**< \brief (AES) Initialisation Vector 1 */
+#define REG_AES_INTVECTV2          (0x42002444) /**< \brief (AES) Initialisation Vector 2 */
+#define REG_AES_INTVECTV3          (0x42002448) /**< \brief (AES) Initialisation Vector 3 */
+#define REG_AES_HASHKEY0           (0x4200245C) /**< \brief (AES) Hash key 0 */
+#define REG_AES_HASHKEY1           (0x42002460) /**< \brief (AES) Hash key 1 */
+#define REG_AES_HASHKEY2           (0x42002464) /**< \brief (AES) Hash key 2 */
+#define REG_AES_HASHKEY3           (0x42002468) /**< \brief (AES) Hash key 3 */
+#define REG_AES_GHASH0             (0x4200246C) /**< \brief (AES) Galois Hash 0 */
+#define REG_AES_GHASH1             (0x42002470) /**< \brief (AES) Galois Hash 1 */
+#define REG_AES_GHASH2             (0x42002474) /**< \brief (AES) Galois Hash 2 */
+#define REG_AES_GHASH3             (0x42002478) /**< \brief (AES) Galois Hash 3 */
+#define REG_AES_CIPLEN             (0x42002480) /**< \brief (AES) Cipher Length */
+#define REG_AES_RANDSEED           (0x42002484) /**< \brief (AES) Random Seed */
+#else
+#define REG_AES_CTRLA              (*(RwReg  *)0x42002400UL) /**< \brief (AES) Control A */
+#define REG_AES_CTRLB              (*(RwReg8 *)0x42002404UL) /**< \brief (AES) Control B */
+#define REG_AES_INTENCLR           (*(RwReg8 *)0x42002405UL) /**< \brief (AES) Interrupt Enable Clear */
+#define REG_AES_INTENSET           (*(RwReg8 *)0x42002406UL) /**< \brief (AES) Interrupt Enable Set */
+#define REG_AES_INTFLAG            (*(RwReg8 *)0x42002407UL) /**< \brief (AES) Interrupt Flag Status */
+#define REG_AES_DATABUFPTR         (*(RwReg8 *)0x42002408UL) /**< \brief (AES) Data buffer pointer */
+#define REG_AES_DBGCTRL            (*(RwReg8 *)0x42002409UL) /**< \brief (AES) Debug control */
+#define REG_AES_KEYWORD0           (*(WoReg  *)0x4200240CUL) /**< \brief (AES) Keyword 0 */
+#define REG_AES_KEYWORD1           (*(WoReg  *)0x42002410UL) /**< \brief (AES) Keyword 1 */
+#define REG_AES_KEYWORD2           (*(WoReg  *)0x42002414UL) /**< \brief (AES) Keyword 2 */
+#define REG_AES_KEYWORD3           (*(WoReg  *)0x42002418UL) /**< \brief (AES) Keyword 3 */
+#define REG_AES_KEYWORD4           (*(WoReg  *)0x4200241CUL) /**< \brief (AES) Keyword 4 */
+#define REG_AES_KEYWORD5           (*(WoReg  *)0x42002420UL) /**< \brief (AES) Keyword 5 */
+#define REG_AES_KEYWORD6           (*(WoReg  *)0x42002424UL) /**< \brief (AES) Keyword 6 */
+#define REG_AES_KEYWORD7           (*(WoReg  *)0x42002428UL) /**< \brief (AES) Keyword 7 */
+#define REG_AES_INDATA             (*(RwReg  *)0x42002438UL) /**< \brief (AES) Indata */
+#define REG_AES_INTVECTV0          (*(WoReg  *)0x4200243CUL) /**< \brief (AES) Initialisation Vector 0 */
+#define REG_AES_INTVECTV1          (*(WoReg  *)0x42002440UL) /**< \brief (AES) Initialisation Vector 1 */
+#define REG_AES_INTVECTV2          (*(WoReg  *)0x42002444UL) /**< \brief (AES) Initialisation Vector 2 */
+#define REG_AES_INTVECTV3          (*(WoReg  *)0x42002448UL) /**< \brief (AES) Initialisation Vector 3 */
+#define REG_AES_HASHKEY0           (*(RwReg  *)0x4200245CUL) /**< \brief (AES) Hash key 0 */
+#define REG_AES_HASHKEY1           (*(RwReg  *)0x42002460UL) /**< \brief (AES) Hash key 1 */
+#define REG_AES_HASHKEY2           (*(RwReg  *)0x42002464UL) /**< \brief (AES) Hash key 2 */
+#define REG_AES_HASHKEY3           (*(RwReg  *)0x42002468UL) /**< \brief (AES) Hash key 3 */
+#define REG_AES_GHASH0             (*(RwReg  *)0x4200246CUL) /**< \brief (AES) Galois Hash 0 */
+#define REG_AES_GHASH1             (*(RwReg  *)0x42002470UL) /**< \brief (AES) Galois Hash 1 */
+#define REG_AES_GHASH2             (*(RwReg  *)0x42002474UL) /**< \brief (AES) Galois Hash 2 */
+#define REG_AES_GHASH3             (*(RwReg  *)0x42002478UL) /**< \brief (AES) Galois Hash 3 */
+#define REG_AES_CIPLEN             (*(RwReg  *)0x42002480UL) /**< \brief (AES) Cipher Length */
+#define REG_AES_RANDSEED           (*(RwReg  *)0x42002484UL) /**< \brief (AES) Random Seed */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AES peripheral ========== */
+#define AES_DMAC_ID_RD              82       // DMA DATA Read trigger
+#define AES_DMAC_ID_WR              81       // DMA DATA Write trigger
+#define AES_FOUR_BYTE_OPERATION     1        // Byte Operation
+#define AES_GCM                     1        // GCM
+#define AES_KEYLEN                  2        // Key Length
+
+#endif /* _SAME53_AES_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ccl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ccl.h
new file mode 100644
index 000000000..c40ee6b1c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ccl.h	
@@ -0,0 +1,57 @@
+/**
+ * \file
+ *
+ * \brief Instance description for CCL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_CCL_INSTANCE_
+#define _SAME53_CCL_INSTANCE_
+
+/* ========== Register definition for CCL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CCL_CTRL               (0x42003800) /**< \brief (CCL) Control */
+#define REG_CCL_SEQCTRL0           (0x42003804) /**< \brief (CCL) SEQ Control x 0 */
+#define REG_CCL_SEQCTRL1           (0x42003805) /**< \brief (CCL) SEQ Control x 1 */
+#define REG_CCL_LUTCTRL0           (0x42003808) /**< \brief (CCL) LUT Control x 0 */
+#define REG_CCL_LUTCTRL1           (0x4200380C) /**< \brief (CCL) LUT Control x 1 */
+#define REG_CCL_LUTCTRL2           (0x42003810) /**< \brief (CCL) LUT Control x 2 */
+#define REG_CCL_LUTCTRL3           (0x42003814) /**< \brief (CCL) LUT Control x 3 */
+#else
+#define REG_CCL_CTRL               (*(RwReg8 *)0x42003800UL) /**< \brief (CCL) Control */
+#define REG_CCL_SEQCTRL0           (*(RwReg8 *)0x42003804UL) /**< \brief (CCL) SEQ Control x 0 */
+#define REG_CCL_SEQCTRL1           (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */
+#define REG_CCL_LUTCTRL0           (*(RwReg  *)0x42003808UL) /**< \brief (CCL) LUT Control x 0 */
+#define REG_CCL_LUTCTRL1           (*(RwReg  *)0x4200380CUL) /**< \brief (CCL) LUT Control x 1 */
+#define REG_CCL_LUTCTRL2           (*(RwReg  *)0x42003810UL) /**< \brief (CCL) LUT Control x 2 */
+#define REG_CCL_LUTCTRL3           (*(RwReg  *)0x42003814UL) /**< \brief (CCL) LUT Control x 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for CCL peripheral ========== */
+#define CCL_GCLK_ID                 33       // GCLK index for CCL
+#define CCL_LUT_NUM                 4        // Number of LUT in a CCL
+#define CCL_SEQ_NUM                 2        // Number of SEQ in a CCL
+
+#endif /* _SAME53_CCL_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/cmcc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/cmcc.h
new file mode 100644
index 000000000..d2f7ec66c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/cmcc.h	
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Instance description for CMCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_CMCC_INSTANCE_
+#define _SAME53_CMCC_INSTANCE_
+
+/* ========== Register definition for CMCC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CMCC_TYPE              (0x41006000) /**< \brief (CMCC) Cache Type Register */
+#define REG_CMCC_CFG               (0x41006004) /**< \brief (CMCC) Cache Configuration Register */
+#define REG_CMCC_CTRL              (0x41006008) /**< \brief (CMCC) Cache Control Register */
+#define REG_CMCC_SR                (0x4100600C) /**< \brief (CMCC) Cache Status Register */
+#define REG_CMCC_LCKWAY            (0x41006010) /**< \brief (CMCC) Cache Lock per Way Register */
+#define REG_CMCC_MAINT0            (0x41006020) /**< \brief (CMCC) Cache Maintenance Register 0 */
+#define REG_CMCC_MAINT1            (0x41006024) /**< \brief (CMCC) Cache Maintenance Register 1 */
+#define REG_CMCC_MCFG              (0x41006028) /**< \brief (CMCC) Cache Monitor Configuration Register */
+#define REG_CMCC_MEN               (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */
+#define REG_CMCC_MCTRL             (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */
+#define REG_CMCC_MSR               (0x41006034) /**< \brief (CMCC) Cache Monitor Status Register */
+#else
+#define REG_CMCC_TYPE              (*(RoReg  *)0x41006000UL) /**< \brief (CMCC) Cache Type Register */
+#define REG_CMCC_CFG               (*(RwReg  *)0x41006004UL) /**< \brief (CMCC) Cache Configuration Register */
+#define REG_CMCC_CTRL              (*(WoReg  *)0x41006008UL) /**< \brief (CMCC) Cache Control Register */
+#define REG_CMCC_SR                (*(RoReg  *)0x4100600CUL) /**< \brief (CMCC) Cache Status Register */
+#define REG_CMCC_LCKWAY            (*(RwReg  *)0x41006010UL) /**< \brief (CMCC) Cache Lock per Way Register */
+#define REG_CMCC_MAINT0            (*(WoReg  *)0x41006020UL) /**< \brief (CMCC) Cache Maintenance Register 0 */
+#define REG_CMCC_MAINT1            (*(WoReg  *)0x41006024UL) /**< \brief (CMCC) Cache Maintenance Register 1 */
+#define REG_CMCC_MCFG              (*(RwReg  *)0x41006028UL) /**< \brief (CMCC) Cache Monitor Configuration Register */
+#define REG_CMCC_MEN               (*(RwReg  *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enable Register */
+#define REG_CMCC_MCTRL             (*(WoReg  *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Control Register */
+#define REG_CMCC_MSR               (*(RoReg  *)0x41006034UL) /**< \brief (CMCC) Cache Monitor Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME53_CMCC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dac.h
new file mode 100644
index 000000000..9d3bd7b67
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dac.h	
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_DAC_INSTANCE_
+#define _SAME53_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA              (0x43002400) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (0x43002401) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (0x43002402) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (0x43002407) /**< \brief (DAC) Status */
+#define REG_DAC_SYNCBUSY           (0x43002408) /**< \brief (DAC) Synchronization Busy */
+#define REG_DAC_DACCTRL0           (0x4300240C) /**< \brief (DAC) DAC 0 Control */
+#define REG_DAC_DACCTRL1           (0x4300240E) /**< \brief (DAC) DAC 1 Control */
+#define REG_DAC_DATA0              (0x43002410) /**< \brief (DAC) DAC 0 Data */
+#define REG_DAC_DATA1              (0x43002412) /**< \brief (DAC) DAC 1 Data */
+#define REG_DAC_DATABUF0           (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
+#define REG_DAC_DATABUF1           (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
+#define REG_DAC_DBGCTRL            (0x43002418) /**< \brief (DAC) Debug Control */
+#define REG_DAC_RESULT0            (0x4300241C) /**< \brief (DAC) Filter Result 0 */
+#define REG_DAC_RESULT1            (0x4300241E) /**< \brief (DAC) Filter Result 1 */
+#else
+#define REG_DAC_CTRLA              (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB              (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL             (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR           (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET           (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG            (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS             (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
+#define REG_DAC_SYNCBUSY           (*(RoReg  *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
+#define REG_DAC_DACCTRL0           (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
+#define REG_DAC_DACCTRL1           (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
+#define REG_DAC_DATA0              (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
+#define REG_DAC_DATA1              (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
+#define REG_DAC_DATABUF0           (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
+#define REG_DAC_DATABUF1           (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
+#define REG_DAC_DBGCTRL            (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
+#define REG_DAC_RESULT0            (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
+#define REG_DAC_RESULT1            (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_CHANNEL_SIZE            2        // Number of DACs
+#define DAC_DATA_SIZE               12       // Number of bits in data
+#define DAC_DMAC_ID_EMPTY_0         72
+#define DAC_DMAC_ID_EMPTY_1         73
+#define DAC_DMAC_ID_EMPTY_LSB       72
+#define DAC_DMAC_ID_EMPTY_MSB       73
+#define DAC_DMAC_ID_EMPTY_SIZE      2
+#define DAC_DMAC_ID_RESRDY_0        74
+#define DAC_DMAC_ID_RESRDY_1        75
+#define DAC_DMAC_ID_RESRDY_LSB      74
+#define DAC_DMAC_ID_RESRDY_MSB      75
+#define DAC_DMAC_ID_RESRDY_SIZE     2
+#define DAC_GCLK_ID                 42       // Index of Generic Clock
+#define DAC_STEP                    7        // Number of steps to reach full scale
+
+#endif /* _SAME53_DAC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dmac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dmac.h
new file mode 100644
index 000000000..212d73a9c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dmac.h	
@@ -0,0 +1,596 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_DMAC_INSTANCE_
+#define _SAME53_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL              (0x4100A000) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (0x4100A002) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (0x4100A004) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (0x4100A008) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (0x4100A00C) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (0x4100A00D) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL        (0x4100A010) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (0x4100A014) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (0x4100A020) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (0x4100A024) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (0x4100A028) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (0x4100A02C) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (0x4100A030) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (0x4100A034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (0x4100A038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHCTRLA0          (0x4100A040) /**< \brief (DMAC) Channel 0 Control A */
+#define REG_DMAC_CHCTRLB0          (0x4100A044) /**< \brief (DMAC) Channel 0 Control B */
+#define REG_DMAC_CHPRILVL0         (0x4100A045) /**< \brief (DMAC) Channel 0 Priority Level */
+#define REG_DMAC_CHEVCTRL0         (0x4100A046) /**< \brief (DMAC) Channel 0 Event Control */
+#define REG_DMAC_CHINTENCLR0       (0x4100A04C) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET0       (0x4100A04D) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG0        (0x4100A04E) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS0         (0x4100A04F) /**< \brief (DMAC) Channel 0 Status */
+#define REG_DMAC_CHCTRLA1          (0x4100A050) /**< \brief (DMAC) Channel 1 Control A */
+#define REG_DMAC_CHCTRLB1          (0x4100A054) /**< \brief (DMAC) Channel 1 Control B */
+#define REG_DMAC_CHPRILVL1         (0x4100A055) /**< \brief (DMAC) Channel 1 Priority Level */
+#define REG_DMAC_CHEVCTRL1         (0x4100A056) /**< \brief (DMAC) Channel 1 Event Control */
+#define REG_DMAC_CHINTENCLR1       (0x4100A05C) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET1       (0x4100A05D) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG1        (0x4100A05E) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS1         (0x4100A05F) /**< \brief (DMAC) Channel 1 Status */
+#define REG_DMAC_CHCTRLA2          (0x4100A060) /**< \brief (DMAC) Channel 2 Control A */
+#define REG_DMAC_CHCTRLB2          (0x4100A064) /**< \brief (DMAC) Channel 2 Control B */
+#define REG_DMAC_CHPRILVL2         (0x4100A065) /**< \brief (DMAC) Channel 2 Priority Level */
+#define REG_DMAC_CHEVCTRL2         (0x4100A066) /**< \brief (DMAC) Channel 2 Event Control */
+#define REG_DMAC_CHINTENCLR2       (0x4100A06C) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET2       (0x4100A06D) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG2        (0x4100A06E) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS2         (0x4100A06F) /**< \brief (DMAC) Channel 2 Status */
+#define REG_DMAC_CHCTRLA3          (0x4100A070) /**< \brief (DMAC) Channel 3 Control A */
+#define REG_DMAC_CHCTRLB3          (0x4100A074) /**< \brief (DMAC) Channel 3 Control B */
+#define REG_DMAC_CHPRILVL3         (0x4100A075) /**< \brief (DMAC) Channel 3 Priority Level */
+#define REG_DMAC_CHEVCTRL3         (0x4100A076) /**< \brief (DMAC) Channel 3 Event Control */
+#define REG_DMAC_CHINTENCLR3       (0x4100A07C) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET3       (0x4100A07D) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG3        (0x4100A07E) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS3         (0x4100A07F) /**< \brief (DMAC) Channel 3 Status */
+#define REG_DMAC_CHCTRLA4          (0x4100A080) /**< \brief (DMAC) Channel 4 Control A */
+#define REG_DMAC_CHCTRLB4          (0x4100A084) /**< \brief (DMAC) Channel 4 Control B */
+#define REG_DMAC_CHPRILVL4         (0x4100A085) /**< \brief (DMAC) Channel 4 Priority Level */
+#define REG_DMAC_CHEVCTRL4         (0x4100A086) /**< \brief (DMAC) Channel 4 Event Control */
+#define REG_DMAC_CHINTENCLR4       (0x4100A08C) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET4       (0x4100A08D) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG4        (0x4100A08E) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS4         (0x4100A08F) /**< \brief (DMAC) Channel 4 Status */
+#define REG_DMAC_CHCTRLA5          (0x4100A090) /**< \brief (DMAC) Channel 5 Control A */
+#define REG_DMAC_CHCTRLB5          (0x4100A094) /**< \brief (DMAC) Channel 5 Control B */
+#define REG_DMAC_CHPRILVL5         (0x4100A095) /**< \brief (DMAC) Channel 5 Priority Level */
+#define REG_DMAC_CHEVCTRL5         (0x4100A096) /**< \brief (DMAC) Channel 5 Event Control */
+#define REG_DMAC_CHINTENCLR5       (0x4100A09C) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET5       (0x4100A09D) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG5        (0x4100A09E) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS5         (0x4100A09F) /**< \brief (DMAC) Channel 5 Status */
+#define REG_DMAC_CHCTRLA6          (0x4100A0A0) /**< \brief (DMAC) Channel 6 Control A */
+#define REG_DMAC_CHCTRLB6          (0x4100A0A4) /**< \brief (DMAC) Channel 6 Control B */
+#define REG_DMAC_CHPRILVL6         (0x4100A0A5) /**< \brief (DMAC) Channel 6 Priority Level */
+#define REG_DMAC_CHEVCTRL6         (0x4100A0A6) /**< \brief (DMAC) Channel 6 Event Control */
+#define REG_DMAC_CHINTENCLR6       (0x4100A0AC) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET6       (0x4100A0AD) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG6        (0x4100A0AE) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS6         (0x4100A0AF) /**< \brief (DMAC) Channel 6 Status */
+#define REG_DMAC_CHCTRLA7          (0x4100A0B0) /**< \brief (DMAC) Channel 7 Control A */
+#define REG_DMAC_CHCTRLB7          (0x4100A0B4) /**< \brief (DMAC) Channel 7 Control B */
+#define REG_DMAC_CHPRILVL7         (0x4100A0B5) /**< \brief (DMAC) Channel 7 Priority Level */
+#define REG_DMAC_CHEVCTRL7         (0x4100A0B6) /**< \brief (DMAC) Channel 7 Event Control */
+#define REG_DMAC_CHINTENCLR7       (0x4100A0BC) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET7       (0x4100A0BD) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG7        (0x4100A0BE) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS7         (0x4100A0BF) /**< \brief (DMAC) Channel 7 Status */
+#define REG_DMAC_CHCTRLA8          (0x4100A0C0) /**< \brief (DMAC) Channel 8 Control A */
+#define REG_DMAC_CHCTRLB8          (0x4100A0C4) /**< \brief (DMAC) Channel 8 Control B */
+#define REG_DMAC_CHPRILVL8         (0x4100A0C5) /**< \brief (DMAC) Channel 8 Priority Level */
+#define REG_DMAC_CHEVCTRL8         (0x4100A0C6) /**< \brief (DMAC) Channel 8 Event Control */
+#define REG_DMAC_CHINTENCLR8       (0x4100A0CC) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET8       (0x4100A0CD) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG8        (0x4100A0CE) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS8         (0x4100A0CF) /**< \brief (DMAC) Channel 8 Status */
+#define REG_DMAC_CHCTRLA9          (0x4100A0D0) /**< \brief (DMAC) Channel 9 Control A */
+#define REG_DMAC_CHCTRLB9          (0x4100A0D4) /**< \brief (DMAC) Channel 9 Control B */
+#define REG_DMAC_CHPRILVL9         (0x4100A0D5) /**< \brief (DMAC) Channel 9 Priority Level */
+#define REG_DMAC_CHEVCTRL9         (0x4100A0D6) /**< \brief (DMAC) Channel 9 Event Control */
+#define REG_DMAC_CHINTENCLR9       (0x4100A0DC) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET9       (0x4100A0DD) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG9        (0x4100A0DE) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS9         (0x4100A0DF) /**< \brief (DMAC) Channel 9 Status */
+#define REG_DMAC_CHCTRLA10         (0x4100A0E0) /**< \brief (DMAC) Channel 10 Control A */
+#define REG_DMAC_CHCTRLB10         (0x4100A0E4) /**< \brief (DMAC) Channel 10 Control B */
+#define REG_DMAC_CHPRILVL10        (0x4100A0E5) /**< \brief (DMAC) Channel 10 Priority Level */
+#define REG_DMAC_CHEVCTRL10        (0x4100A0E6) /**< \brief (DMAC) Channel 10 Event Control */
+#define REG_DMAC_CHINTENCLR10      (0x4100A0EC) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET10      (0x4100A0ED) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG10       (0x4100A0EE) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS10        (0x4100A0EF) /**< \brief (DMAC) Channel 10 Status */
+#define REG_DMAC_CHCTRLA11         (0x4100A0F0) /**< \brief (DMAC) Channel 11 Control A */
+#define REG_DMAC_CHCTRLB11         (0x4100A0F4) /**< \brief (DMAC) Channel 11 Control B */
+#define REG_DMAC_CHPRILVL11        (0x4100A0F5) /**< \brief (DMAC) Channel 11 Priority Level */
+#define REG_DMAC_CHEVCTRL11        (0x4100A0F6) /**< \brief (DMAC) Channel 11 Event Control */
+#define REG_DMAC_CHINTENCLR11      (0x4100A0FC) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET11      (0x4100A0FD) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG11       (0x4100A0FE) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS11        (0x4100A0FF) /**< \brief (DMAC) Channel 11 Status */
+#define REG_DMAC_CHCTRLA12         (0x4100A100) /**< \brief (DMAC) Channel 12 Control A */
+#define REG_DMAC_CHCTRLB12         (0x4100A104) /**< \brief (DMAC) Channel 12 Control B */
+#define REG_DMAC_CHPRILVL12        (0x4100A105) /**< \brief (DMAC) Channel 12 Priority Level */
+#define REG_DMAC_CHEVCTRL12        (0x4100A106) /**< \brief (DMAC) Channel 12 Event Control */
+#define REG_DMAC_CHINTENCLR12      (0x4100A10C) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET12      (0x4100A10D) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG12       (0x4100A10E) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS12        (0x4100A10F) /**< \brief (DMAC) Channel 12 Status */
+#define REG_DMAC_CHCTRLA13         (0x4100A110) /**< \brief (DMAC) Channel 13 Control A */
+#define REG_DMAC_CHCTRLB13         (0x4100A114) /**< \brief (DMAC) Channel 13 Control B */
+#define REG_DMAC_CHPRILVL13        (0x4100A115) /**< \brief (DMAC) Channel 13 Priority Level */
+#define REG_DMAC_CHEVCTRL13        (0x4100A116) /**< \brief (DMAC) Channel 13 Event Control */
+#define REG_DMAC_CHINTENCLR13      (0x4100A11C) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET13      (0x4100A11D) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG13       (0x4100A11E) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS13        (0x4100A11F) /**< \brief (DMAC) Channel 13 Status */
+#define REG_DMAC_CHCTRLA14         (0x4100A120) /**< \brief (DMAC) Channel 14 Control A */
+#define REG_DMAC_CHCTRLB14         (0x4100A124) /**< \brief (DMAC) Channel 14 Control B */
+#define REG_DMAC_CHPRILVL14        (0x4100A125) /**< \brief (DMAC) Channel 14 Priority Level */
+#define REG_DMAC_CHEVCTRL14        (0x4100A126) /**< \brief (DMAC) Channel 14 Event Control */
+#define REG_DMAC_CHINTENCLR14      (0x4100A12C) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET14      (0x4100A12D) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG14       (0x4100A12E) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS14        (0x4100A12F) /**< \brief (DMAC) Channel 14 Status */
+#define REG_DMAC_CHCTRLA15         (0x4100A130) /**< \brief (DMAC) Channel 15 Control A */
+#define REG_DMAC_CHCTRLB15         (0x4100A134) /**< \brief (DMAC) Channel 15 Control B */
+#define REG_DMAC_CHPRILVL15        (0x4100A135) /**< \brief (DMAC) Channel 15 Priority Level */
+#define REG_DMAC_CHEVCTRL15        (0x4100A136) /**< \brief (DMAC) Channel 15 Event Control */
+#define REG_DMAC_CHINTENCLR15      (0x4100A13C) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET15      (0x4100A13D) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG15       (0x4100A13E) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS15        (0x4100A13F) /**< \brief (DMAC) Channel 15 Status */
+#define REG_DMAC_CHCTRLA16         (0x4100A140) /**< \brief (DMAC) Channel 16 Control A */
+#define REG_DMAC_CHCTRLB16         (0x4100A144) /**< \brief (DMAC) Channel 16 Control B */
+#define REG_DMAC_CHPRILVL16        (0x4100A145) /**< \brief (DMAC) Channel 16 Priority Level */
+#define REG_DMAC_CHEVCTRL16        (0x4100A146) /**< \brief (DMAC) Channel 16 Event Control */
+#define REG_DMAC_CHINTENCLR16      (0x4100A14C) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET16      (0x4100A14D) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG16       (0x4100A14E) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS16        (0x4100A14F) /**< \brief (DMAC) Channel 16 Status */
+#define REG_DMAC_CHCTRLA17         (0x4100A150) /**< \brief (DMAC) Channel 17 Control A */
+#define REG_DMAC_CHCTRLB17         (0x4100A154) /**< \brief (DMAC) Channel 17 Control B */
+#define REG_DMAC_CHPRILVL17        (0x4100A155) /**< \brief (DMAC) Channel 17 Priority Level */
+#define REG_DMAC_CHEVCTRL17        (0x4100A156) /**< \brief (DMAC) Channel 17 Event Control */
+#define REG_DMAC_CHINTENCLR17      (0x4100A15C) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET17      (0x4100A15D) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG17       (0x4100A15E) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS17        (0x4100A15F) /**< \brief (DMAC) Channel 17 Status */
+#define REG_DMAC_CHCTRLA18         (0x4100A160) /**< \brief (DMAC) Channel 18 Control A */
+#define REG_DMAC_CHCTRLB18         (0x4100A164) /**< \brief (DMAC) Channel 18 Control B */
+#define REG_DMAC_CHPRILVL18        (0x4100A165) /**< \brief (DMAC) Channel 18 Priority Level */
+#define REG_DMAC_CHEVCTRL18        (0x4100A166) /**< \brief (DMAC) Channel 18 Event Control */
+#define REG_DMAC_CHINTENCLR18      (0x4100A16C) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET18      (0x4100A16D) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG18       (0x4100A16E) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS18        (0x4100A16F) /**< \brief (DMAC) Channel 18 Status */
+#define REG_DMAC_CHCTRLA19         (0x4100A170) /**< \brief (DMAC) Channel 19 Control A */
+#define REG_DMAC_CHCTRLB19         (0x4100A174) /**< \brief (DMAC) Channel 19 Control B */
+#define REG_DMAC_CHPRILVL19        (0x4100A175) /**< \brief (DMAC) Channel 19 Priority Level */
+#define REG_DMAC_CHEVCTRL19        (0x4100A176) /**< \brief (DMAC) Channel 19 Event Control */
+#define REG_DMAC_CHINTENCLR19      (0x4100A17C) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET19      (0x4100A17D) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG19       (0x4100A17E) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS19        (0x4100A17F) /**< \brief (DMAC) Channel 19 Status */
+#define REG_DMAC_CHCTRLA20         (0x4100A180) /**< \brief (DMAC) Channel 20 Control A */
+#define REG_DMAC_CHCTRLB20         (0x4100A184) /**< \brief (DMAC) Channel 20 Control B */
+#define REG_DMAC_CHPRILVL20        (0x4100A185) /**< \brief (DMAC) Channel 20 Priority Level */
+#define REG_DMAC_CHEVCTRL20        (0x4100A186) /**< \brief (DMAC) Channel 20 Event Control */
+#define REG_DMAC_CHINTENCLR20      (0x4100A18C) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET20      (0x4100A18D) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG20       (0x4100A18E) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS20        (0x4100A18F) /**< \brief (DMAC) Channel 20 Status */
+#define REG_DMAC_CHCTRLA21         (0x4100A190) /**< \brief (DMAC) Channel 21 Control A */
+#define REG_DMAC_CHCTRLB21         (0x4100A194) /**< \brief (DMAC) Channel 21 Control B */
+#define REG_DMAC_CHPRILVL21        (0x4100A195) /**< \brief (DMAC) Channel 21 Priority Level */
+#define REG_DMAC_CHEVCTRL21        (0x4100A196) /**< \brief (DMAC) Channel 21 Event Control */
+#define REG_DMAC_CHINTENCLR21      (0x4100A19C) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET21      (0x4100A19D) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG21       (0x4100A19E) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS21        (0x4100A19F) /**< \brief (DMAC) Channel 21 Status */
+#define REG_DMAC_CHCTRLA22         (0x4100A1A0) /**< \brief (DMAC) Channel 22 Control A */
+#define REG_DMAC_CHCTRLB22         (0x4100A1A4) /**< \brief (DMAC) Channel 22 Control B */
+#define REG_DMAC_CHPRILVL22        (0x4100A1A5) /**< \brief (DMAC) Channel 22 Priority Level */
+#define REG_DMAC_CHEVCTRL22        (0x4100A1A6) /**< \brief (DMAC) Channel 22 Event Control */
+#define REG_DMAC_CHINTENCLR22      (0x4100A1AC) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET22      (0x4100A1AD) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG22       (0x4100A1AE) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS22        (0x4100A1AF) /**< \brief (DMAC) Channel 22 Status */
+#define REG_DMAC_CHCTRLA23         (0x4100A1B0) /**< \brief (DMAC) Channel 23 Control A */
+#define REG_DMAC_CHCTRLB23         (0x4100A1B4) /**< \brief (DMAC) Channel 23 Control B */
+#define REG_DMAC_CHPRILVL23        (0x4100A1B5) /**< \brief (DMAC) Channel 23 Priority Level */
+#define REG_DMAC_CHEVCTRL23        (0x4100A1B6) /**< \brief (DMAC) Channel 23 Event Control */
+#define REG_DMAC_CHINTENCLR23      (0x4100A1BC) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET23      (0x4100A1BD) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG23       (0x4100A1BE) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS23        (0x4100A1BF) /**< \brief (DMAC) Channel 23 Status */
+#define REG_DMAC_CHCTRLA24         (0x4100A1C0) /**< \brief (DMAC) Channel 24 Control A */
+#define REG_DMAC_CHCTRLB24         (0x4100A1C4) /**< \brief (DMAC) Channel 24 Control B */
+#define REG_DMAC_CHPRILVL24        (0x4100A1C5) /**< \brief (DMAC) Channel 24 Priority Level */
+#define REG_DMAC_CHEVCTRL24        (0x4100A1C6) /**< \brief (DMAC) Channel 24 Event Control */
+#define REG_DMAC_CHINTENCLR24      (0x4100A1CC) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET24      (0x4100A1CD) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG24       (0x4100A1CE) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS24        (0x4100A1CF) /**< \brief (DMAC) Channel 24 Status */
+#define REG_DMAC_CHCTRLA25         (0x4100A1D0) /**< \brief (DMAC) Channel 25 Control A */
+#define REG_DMAC_CHCTRLB25         (0x4100A1D4) /**< \brief (DMAC) Channel 25 Control B */
+#define REG_DMAC_CHPRILVL25        (0x4100A1D5) /**< \brief (DMAC) Channel 25 Priority Level */
+#define REG_DMAC_CHEVCTRL25        (0x4100A1D6) /**< \brief (DMAC) Channel 25 Event Control */
+#define REG_DMAC_CHINTENCLR25      (0x4100A1DC) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET25      (0x4100A1DD) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG25       (0x4100A1DE) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS25        (0x4100A1DF) /**< \brief (DMAC) Channel 25 Status */
+#define REG_DMAC_CHCTRLA26         (0x4100A1E0) /**< \brief (DMAC) Channel 26 Control A */
+#define REG_DMAC_CHCTRLB26         (0x4100A1E4) /**< \brief (DMAC) Channel 26 Control B */
+#define REG_DMAC_CHPRILVL26        (0x4100A1E5) /**< \brief (DMAC) Channel 26 Priority Level */
+#define REG_DMAC_CHEVCTRL26        (0x4100A1E6) /**< \brief (DMAC) Channel 26 Event Control */
+#define REG_DMAC_CHINTENCLR26      (0x4100A1EC) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET26      (0x4100A1ED) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG26       (0x4100A1EE) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS26        (0x4100A1EF) /**< \brief (DMAC) Channel 26 Status */
+#define REG_DMAC_CHCTRLA27         (0x4100A1F0) /**< \brief (DMAC) Channel 27 Control A */
+#define REG_DMAC_CHCTRLB27         (0x4100A1F4) /**< \brief (DMAC) Channel 27 Control B */
+#define REG_DMAC_CHPRILVL27        (0x4100A1F5) /**< \brief (DMAC) Channel 27 Priority Level */
+#define REG_DMAC_CHEVCTRL27        (0x4100A1F6) /**< \brief (DMAC) Channel 27 Event Control */
+#define REG_DMAC_CHINTENCLR27      (0x4100A1FC) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET27      (0x4100A1FD) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG27       (0x4100A1FE) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS27        (0x4100A1FF) /**< \brief (DMAC) Channel 27 Status */
+#define REG_DMAC_CHCTRLA28         (0x4100A200) /**< \brief (DMAC) Channel 28 Control A */
+#define REG_DMAC_CHCTRLB28         (0x4100A204) /**< \brief (DMAC) Channel 28 Control B */
+#define REG_DMAC_CHPRILVL28        (0x4100A205) /**< \brief (DMAC) Channel 28 Priority Level */
+#define REG_DMAC_CHEVCTRL28        (0x4100A206) /**< \brief (DMAC) Channel 28 Event Control */
+#define REG_DMAC_CHINTENCLR28      (0x4100A20C) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET28      (0x4100A20D) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG28       (0x4100A20E) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS28        (0x4100A20F) /**< \brief (DMAC) Channel 28 Status */
+#define REG_DMAC_CHCTRLA29         (0x4100A210) /**< \brief (DMAC) Channel 29 Control A */
+#define REG_DMAC_CHCTRLB29         (0x4100A214) /**< \brief (DMAC) Channel 29 Control B */
+#define REG_DMAC_CHPRILVL29        (0x4100A215) /**< \brief (DMAC) Channel 29 Priority Level */
+#define REG_DMAC_CHEVCTRL29        (0x4100A216) /**< \brief (DMAC) Channel 29 Event Control */
+#define REG_DMAC_CHINTENCLR29      (0x4100A21C) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET29      (0x4100A21D) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG29       (0x4100A21E) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS29        (0x4100A21F) /**< \brief (DMAC) Channel 29 Status */
+#define REG_DMAC_CHCTRLA30         (0x4100A220) /**< \brief (DMAC) Channel 30 Control A */
+#define REG_DMAC_CHCTRLB30         (0x4100A224) /**< \brief (DMAC) Channel 30 Control B */
+#define REG_DMAC_CHPRILVL30        (0x4100A225) /**< \brief (DMAC) Channel 30 Priority Level */
+#define REG_DMAC_CHEVCTRL30        (0x4100A226) /**< \brief (DMAC) Channel 30 Event Control */
+#define REG_DMAC_CHINTENCLR30      (0x4100A22C) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET30      (0x4100A22D) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG30       (0x4100A22E) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS30        (0x4100A22F) /**< \brief (DMAC) Channel 30 Status */
+#define REG_DMAC_CHCTRLA31         (0x4100A230) /**< \brief (DMAC) Channel 31 Control A */
+#define REG_DMAC_CHCTRLB31         (0x4100A234) /**< \brief (DMAC) Channel 31 Control B */
+#define REG_DMAC_CHPRILVL31        (0x4100A235) /**< \brief (DMAC) Channel 31 Priority Level */
+#define REG_DMAC_CHEVCTRL31        (0x4100A236) /**< \brief (DMAC) Channel 31 Event Control */
+#define REG_DMAC_CHINTENCLR31      (0x4100A23C) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET31      (0x4100A23D) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG31       (0x4100A23E) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS31        (0x4100A23F) /**< \brief (DMAC) Channel 31 Status */
+#else
+#define REG_DMAC_CTRL              (*(RwReg16*)0x4100A000UL) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL           (*(RwReg16*)0x4100A002UL) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN         (*(RwReg  *)0x4100A004UL) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM         (*(RwReg  *)0x4100A008UL) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS         (*(RwReg8 *)0x4100A00CUL) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL           (*(RwReg8 *)0x4100A00DUL) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL        (*(RwReg  *)0x4100A010UL) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0          (*(RwReg  *)0x4100A014UL) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND           (*(RwReg16*)0x4100A020UL) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS         (*(RoReg  *)0x4100A024UL) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH            (*(RoReg  *)0x4100A028UL) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH            (*(RoReg  *)0x4100A02CUL) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE            (*(RoReg  *)0x4100A030UL) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR          (*(RwReg  *)0x4100A034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR           (*(RwReg  *)0x4100A038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHCTRLA0          (*(RwReg  *)0x4100A040UL) /**< \brief (DMAC) Channel 0 Control A */
+#define REG_DMAC_CHCTRLB0          (*(RwReg8 *)0x4100A044UL) /**< \brief (DMAC) Channel 0 Control B */
+#define REG_DMAC_CHPRILVL0         (*(RwReg8 *)0x4100A045UL) /**< \brief (DMAC) Channel 0 Priority Level */
+#define REG_DMAC_CHEVCTRL0         (*(RwReg8 *)0x4100A046UL) /**< \brief (DMAC) Channel 0 Event Control */
+#define REG_DMAC_CHINTENCLR0       (*(RwReg8 *)0x4100A04CUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET0       (*(RwReg8 *)0x4100A04DUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG0        (*(RwReg8 *)0x4100A04EUL) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS0         (*(RwReg8 *)0x4100A04FUL) /**< \brief (DMAC) Channel 0 Status */
+#define REG_DMAC_CHCTRLA1          (*(RwReg  *)0x4100A050UL) /**< \brief (DMAC) Channel 1 Control A */
+#define REG_DMAC_CHCTRLB1          (*(RwReg8 *)0x4100A054UL) /**< \brief (DMAC) Channel 1 Control B */
+#define REG_DMAC_CHPRILVL1         (*(RwReg8 *)0x4100A055UL) /**< \brief (DMAC) Channel 1 Priority Level */
+#define REG_DMAC_CHEVCTRL1         (*(RwReg8 *)0x4100A056UL) /**< \brief (DMAC) Channel 1 Event Control */
+#define REG_DMAC_CHINTENCLR1       (*(RwReg8 *)0x4100A05CUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET1       (*(RwReg8 *)0x4100A05DUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG1        (*(RwReg8 *)0x4100A05EUL) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS1         (*(RwReg8 *)0x4100A05FUL) /**< \brief (DMAC) Channel 1 Status */
+#define REG_DMAC_CHCTRLA2          (*(RwReg  *)0x4100A060UL) /**< \brief (DMAC) Channel 2 Control A */
+#define REG_DMAC_CHCTRLB2          (*(RwReg8 *)0x4100A064UL) /**< \brief (DMAC) Channel 2 Control B */
+#define REG_DMAC_CHPRILVL2         (*(RwReg8 *)0x4100A065UL) /**< \brief (DMAC) Channel 2 Priority Level */
+#define REG_DMAC_CHEVCTRL2         (*(RwReg8 *)0x4100A066UL) /**< \brief (DMAC) Channel 2 Event Control */
+#define REG_DMAC_CHINTENCLR2       (*(RwReg8 *)0x4100A06CUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET2       (*(RwReg8 *)0x4100A06DUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG2        (*(RwReg8 *)0x4100A06EUL) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS2         (*(RwReg8 *)0x4100A06FUL) /**< \brief (DMAC) Channel 2 Status */
+#define REG_DMAC_CHCTRLA3          (*(RwReg  *)0x4100A070UL) /**< \brief (DMAC) Channel 3 Control A */
+#define REG_DMAC_CHCTRLB3          (*(RwReg8 *)0x4100A074UL) /**< \brief (DMAC) Channel 3 Control B */
+#define REG_DMAC_CHPRILVL3         (*(RwReg8 *)0x4100A075UL) /**< \brief (DMAC) Channel 3 Priority Level */
+#define REG_DMAC_CHEVCTRL3         (*(RwReg8 *)0x4100A076UL) /**< \brief (DMAC) Channel 3 Event Control */
+#define REG_DMAC_CHINTENCLR3       (*(RwReg8 *)0x4100A07CUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET3       (*(RwReg8 *)0x4100A07DUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG3        (*(RwReg8 *)0x4100A07EUL) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS3         (*(RwReg8 *)0x4100A07FUL) /**< \brief (DMAC) Channel 3 Status */
+#define REG_DMAC_CHCTRLA4          (*(RwReg  *)0x4100A080UL) /**< \brief (DMAC) Channel 4 Control A */
+#define REG_DMAC_CHCTRLB4          (*(RwReg8 *)0x4100A084UL) /**< \brief (DMAC) Channel 4 Control B */
+#define REG_DMAC_CHPRILVL4         (*(RwReg8 *)0x4100A085UL) /**< \brief (DMAC) Channel 4 Priority Level */
+#define REG_DMAC_CHEVCTRL4         (*(RwReg8 *)0x4100A086UL) /**< \brief (DMAC) Channel 4 Event Control */
+#define REG_DMAC_CHINTENCLR4       (*(RwReg8 *)0x4100A08CUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET4       (*(RwReg8 *)0x4100A08DUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG4        (*(RwReg8 *)0x4100A08EUL) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS4         (*(RwReg8 *)0x4100A08FUL) /**< \brief (DMAC) Channel 4 Status */
+#define REG_DMAC_CHCTRLA5          (*(RwReg  *)0x4100A090UL) /**< \brief (DMAC) Channel 5 Control A */
+#define REG_DMAC_CHCTRLB5          (*(RwReg8 *)0x4100A094UL) /**< \brief (DMAC) Channel 5 Control B */
+#define REG_DMAC_CHPRILVL5         (*(RwReg8 *)0x4100A095UL) /**< \brief (DMAC) Channel 5 Priority Level */
+#define REG_DMAC_CHEVCTRL5         (*(RwReg8 *)0x4100A096UL) /**< \brief (DMAC) Channel 5 Event Control */
+#define REG_DMAC_CHINTENCLR5       (*(RwReg8 *)0x4100A09CUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET5       (*(RwReg8 *)0x4100A09DUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG5        (*(RwReg8 *)0x4100A09EUL) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS5         (*(RwReg8 *)0x4100A09FUL) /**< \brief (DMAC) Channel 5 Status */
+#define REG_DMAC_CHCTRLA6          (*(RwReg  *)0x4100A0A0UL) /**< \brief (DMAC) Channel 6 Control A */
+#define REG_DMAC_CHCTRLB6          (*(RwReg8 *)0x4100A0A4UL) /**< \brief (DMAC) Channel 6 Control B */
+#define REG_DMAC_CHPRILVL6         (*(RwReg8 *)0x4100A0A5UL) /**< \brief (DMAC) Channel 6 Priority Level */
+#define REG_DMAC_CHEVCTRL6         (*(RwReg8 *)0x4100A0A6UL) /**< \brief (DMAC) Channel 6 Event Control */
+#define REG_DMAC_CHINTENCLR6       (*(RwReg8 *)0x4100A0ACUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET6       (*(RwReg8 *)0x4100A0ADUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG6        (*(RwReg8 *)0x4100A0AEUL) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS6         (*(RwReg8 *)0x4100A0AFUL) /**< \brief (DMAC) Channel 6 Status */
+#define REG_DMAC_CHCTRLA7          (*(RwReg  *)0x4100A0B0UL) /**< \brief (DMAC) Channel 7 Control A */
+#define REG_DMAC_CHCTRLB7          (*(RwReg8 *)0x4100A0B4UL) /**< \brief (DMAC) Channel 7 Control B */
+#define REG_DMAC_CHPRILVL7         (*(RwReg8 *)0x4100A0B5UL) /**< \brief (DMAC) Channel 7 Priority Level */
+#define REG_DMAC_CHEVCTRL7         (*(RwReg8 *)0x4100A0B6UL) /**< \brief (DMAC) Channel 7 Event Control */
+#define REG_DMAC_CHINTENCLR7       (*(RwReg8 *)0x4100A0BCUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET7       (*(RwReg8 *)0x4100A0BDUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG7        (*(RwReg8 *)0x4100A0BEUL) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS7         (*(RwReg8 *)0x4100A0BFUL) /**< \brief (DMAC) Channel 7 Status */
+#define REG_DMAC_CHCTRLA8          (*(RwReg  *)0x4100A0C0UL) /**< \brief (DMAC) Channel 8 Control A */
+#define REG_DMAC_CHCTRLB8          (*(RwReg8 *)0x4100A0C4UL) /**< \brief (DMAC) Channel 8 Control B */
+#define REG_DMAC_CHPRILVL8         (*(RwReg8 *)0x4100A0C5UL) /**< \brief (DMAC) Channel 8 Priority Level */
+#define REG_DMAC_CHEVCTRL8         (*(RwReg8 *)0x4100A0C6UL) /**< \brief (DMAC) Channel 8 Event Control */
+#define REG_DMAC_CHINTENCLR8       (*(RwReg8 *)0x4100A0CCUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET8       (*(RwReg8 *)0x4100A0CDUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG8        (*(RwReg8 *)0x4100A0CEUL) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS8         (*(RwReg8 *)0x4100A0CFUL) /**< \brief (DMAC) Channel 8 Status */
+#define REG_DMAC_CHCTRLA9          (*(RwReg  *)0x4100A0D0UL) /**< \brief (DMAC) Channel 9 Control A */
+#define REG_DMAC_CHCTRLB9          (*(RwReg8 *)0x4100A0D4UL) /**< \brief (DMAC) Channel 9 Control B */
+#define REG_DMAC_CHPRILVL9         (*(RwReg8 *)0x4100A0D5UL) /**< \brief (DMAC) Channel 9 Priority Level */
+#define REG_DMAC_CHEVCTRL9         (*(RwReg8 *)0x4100A0D6UL) /**< \brief (DMAC) Channel 9 Event Control */
+#define REG_DMAC_CHINTENCLR9       (*(RwReg8 *)0x4100A0DCUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET9       (*(RwReg8 *)0x4100A0DDUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG9        (*(RwReg8 *)0x4100A0DEUL) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS9         (*(RwReg8 *)0x4100A0DFUL) /**< \brief (DMAC) Channel 9 Status */
+#define REG_DMAC_CHCTRLA10         (*(RwReg  *)0x4100A0E0UL) /**< \brief (DMAC) Channel 10 Control A */
+#define REG_DMAC_CHCTRLB10         (*(RwReg8 *)0x4100A0E4UL) /**< \brief (DMAC) Channel 10 Control B */
+#define REG_DMAC_CHPRILVL10        (*(RwReg8 *)0x4100A0E5UL) /**< \brief (DMAC) Channel 10 Priority Level */
+#define REG_DMAC_CHEVCTRL10        (*(RwReg8 *)0x4100A0E6UL) /**< \brief (DMAC) Channel 10 Event Control */
+#define REG_DMAC_CHINTENCLR10      (*(RwReg8 *)0x4100A0ECUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET10      (*(RwReg8 *)0x4100A0EDUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG10       (*(RwReg8 *)0x4100A0EEUL) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS10        (*(RwReg8 *)0x4100A0EFUL) /**< \brief (DMAC) Channel 10 Status */
+#define REG_DMAC_CHCTRLA11         (*(RwReg  *)0x4100A0F0UL) /**< \brief (DMAC) Channel 11 Control A */
+#define REG_DMAC_CHCTRLB11         (*(RwReg8 *)0x4100A0F4UL) /**< \brief (DMAC) Channel 11 Control B */
+#define REG_DMAC_CHPRILVL11        (*(RwReg8 *)0x4100A0F5UL) /**< \brief (DMAC) Channel 11 Priority Level */
+#define REG_DMAC_CHEVCTRL11        (*(RwReg8 *)0x4100A0F6UL) /**< \brief (DMAC) Channel 11 Event Control */
+#define REG_DMAC_CHINTENCLR11      (*(RwReg8 *)0x4100A0FCUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET11      (*(RwReg8 *)0x4100A0FDUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG11       (*(RwReg8 *)0x4100A0FEUL) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS11        (*(RwReg8 *)0x4100A0FFUL) /**< \brief (DMAC) Channel 11 Status */
+#define REG_DMAC_CHCTRLA12         (*(RwReg  *)0x4100A100UL) /**< \brief (DMAC) Channel 12 Control A */
+#define REG_DMAC_CHCTRLB12         (*(RwReg8 *)0x4100A104UL) /**< \brief (DMAC) Channel 12 Control B */
+#define REG_DMAC_CHPRILVL12        (*(RwReg8 *)0x4100A105UL) /**< \brief (DMAC) Channel 12 Priority Level */
+#define REG_DMAC_CHEVCTRL12        (*(RwReg8 *)0x4100A106UL) /**< \brief (DMAC) Channel 12 Event Control */
+#define REG_DMAC_CHINTENCLR12      (*(RwReg8 *)0x4100A10CUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET12      (*(RwReg8 *)0x4100A10DUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG12       (*(RwReg8 *)0x4100A10EUL) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS12        (*(RwReg8 *)0x4100A10FUL) /**< \brief (DMAC) Channel 12 Status */
+#define REG_DMAC_CHCTRLA13         (*(RwReg  *)0x4100A110UL) /**< \brief (DMAC) Channel 13 Control A */
+#define REG_DMAC_CHCTRLB13         (*(RwReg8 *)0x4100A114UL) /**< \brief (DMAC) Channel 13 Control B */
+#define REG_DMAC_CHPRILVL13        (*(RwReg8 *)0x4100A115UL) /**< \brief (DMAC) Channel 13 Priority Level */
+#define REG_DMAC_CHEVCTRL13        (*(RwReg8 *)0x4100A116UL) /**< \brief (DMAC) Channel 13 Event Control */
+#define REG_DMAC_CHINTENCLR13      (*(RwReg8 *)0x4100A11CUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET13      (*(RwReg8 *)0x4100A11DUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG13       (*(RwReg8 *)0x4100A11EUL) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS13        (*(RwReg8 *)0x4100A11FUL) /**< \brief (DMAC) Channel 13 Status */
+#define REG_DMAC_CHCTRLA14         (*(RwReg  *)0x4100A120UL) /**< \brief (DMAC) Channel 14 Control A */
+#define REG_DMAC_CHCTRLB14         (*(RwReg8 *)0x4100A124UL) /**< \brief (DMAC) Channel 14 Control B */
+#define REG_DMAC_CHPRILVL14        (*(RwReg8 *)0x4100A125UL) /**< \brief (DMAC) Channel 14 Priority Level */
+#define REG_DMAC_CHEVCTRL14        (*(RwReg8 *)0x4100A126UL) /**< \brief (DMAC) Channel 14 Event Control */
+#define REG_DMAC_CHINTENCLR14      (*(RwReg8 *)0x4100A12CUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET14      (*(RwReg8 *)0x4100A12DUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG14       (*(RwReg8 *)0x4100A12EUL) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS14        (*(RwReg8 *)0x4100A12FUL) /**< \brief (DMAC) Channel 14 Status */
+#define REG_DMAC_CHCTRLA15         (*(RwReg  *)0x4100A130UL) /**< \brief (DMAC) Channel 15 Control A */
+#define REG_DMAC_CHCTRLB15         (*(RwReg8 *)0x4100A134UL) /**< \brief (DMAC) Channel 15 Control B */
+#define REG_DMAC_CHPRILVL15        (*(RwReg8 *)0x4100A135UL) /**< \brief (DMAC) Channel 15 Priority Level */
+#define REG_DMAC_CHEVCTRL15        (*(RwReg8 *)0x4100A136UL) /**< \brief (DMAC) Channel 15 Event Control */
+#define REG_DMAC_CHINTENCLR15      (*(RwReg8 *)0x4100A13CUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET15      (*(RwReg8 *)0x4100A13DUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG15       (*(RwReg8 *)0x4100A13EUL) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS15        (*(RwReg8 *)0x4100A13FUL) /**< \brief (DMAC) Channel 15 Status */
+#define REG_DMAC_CHCTRLA16         (*(RwReg  *)0x4100A140UL) /**< \brief (DMAC) Channel 16 Control A */
+#define REG_DMAC_CHCTRLB16         (*(RwReg8 *)0x4100A144UL) /**< \brief (DMAC) Channel 16 Control B */
+#define REG_DMAC_CHPRILVL16        (*(RwReg8 *)0x4100A145UL) /**< \brief (DMAC) Channel 16 Priority Level */
+#define REG_DMAC_CHEVCTRL16        (*(RwReg8 *)0x4100A146UL) /**< \brief (DMAC) Channel 16 Event Control */
+#define REG_DMAC_CHINTENCLR16      (*(RwReg8 *)0x4100A14CUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET16      (*(RwReg8 *)0x4100A14DUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG16       (*(RwReg8 *)0x4100A14EUL) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS16        (*(RwReg8 *)0x4100A14FUL) /**< \brief (DMAC) Channel 16 Status */
+#define REG_DMAC_CHCTRLA17         (*(RwReg  *)0x4100A150UL) /**< \brief (DMAC) Channel 17 Control A */
+#define REG_DMAC_CHCTRLB17         (*(RwReg8 *)0x4100A154UL) /**< \brief (DMAC) Channel 17 Control B */
+#define REG_DMAC_CHPRILVL17        (*(RwReg8 *)0x4100A155UL) /**< \brief (DMAC) Channel 17 Priority Level */
+#define REG_DMAC_CHEVCTRL17        (*(RwReg8 *)0x4100A156UL) /**< \brief (DMAC) Channel 17 Event Control */
+#define REG_DMAC_CHINTENCLR17      (*(RwReg8 *)0x4100A15CUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET17      (*(RwReg8 *)0x4100A15DUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG17       (*(RwReg8 *)0x4100A15EUL) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS17        (*(RwReg8 *)0x4100A15FUL) /**< \brief (DMAC) Channel 17 Status */
+#define REG_DMAC_CHCTRLA18         (*(RwReg  *)0x4100A160UL) /**< \brief (DMAC) Channel 18 Control A */
+#define REG_DMAC_CHCTRLB18         (*(RwReg8 *)0x4100A164UL) /**< \brief (DMAC) Channel 18 Control B */
+#define REG_DMAC_CHPRILVL18        (*(RwReg8 *)0x4100A165UL) /**< \brief (DMAC) Channel 18 Priority Level */
+#define REG_DMAC_CHEVCTRL18        (*(RwReg8 *)0x4100A166UL) /**< \brief (DMAC) Channel 18 Event Control */
+#define REG_DMAC_CHINTENCLR18      (*(RwReg8 *)0x4100A16CUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET18      (*(RwReg8 *)0x4100A16DUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG18       (*(RwReg8 *)0x4100A16EUL) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS18        (*(RwReg8 *)0x4100A16FUL) /**< \brief (DMAC) Channel 18 Status */
+#define REG_DMAC_CHCTRLA19         (*(RwReg  *)0x4100A170UL) /**< \brief (DMAC) Channel 19 Control A */
+#define REG_DMAC_CHCTRLB19         (*(RwReg8 *)0x4100A174UL) /**< \brief (DMAC) Channel 19 Control B */
+#define REG_DMAC_CHPRILVL19        (*(RwReg8 *)0x4100A175UL) /**< \brief (DMAC) Channel 19 Priority Level */
+#define REG_DMAC_CHEVCTRL19        (*(RwReg8 *)0x4100A176UL) /**< \brief (DMAC) Channel 19 Event Control */
+#define REG_DMAC_CHINTENCLR19      (*(RwReg8 *)0x4100A17CUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET19      (*(RwReg8 *)0x4100A17DUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG19       (*(RwReg8 *)0x4100A17EUL) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS19        (*(RwReg8 *)0x4100A17FUL) /**< \brief (DMAC) Channel 19 Status */
+#define REG_DMAC_CHCTRLA20         (*(RwReg  *)0x4100A180UL) /**< \brief (DMAC) Channel 20 Control A */
+#define REG_DMAC_CHCTRLB20         (*(RwReg8 *)0x4100A184UL) /**< \brief (DMAC) Channel 20 Control B */
+#define REG_DMAC_CHPRILVL20        (*(RwReg8 *)0x4100A185UL) /**< \brief (DMAC) Channel 20 Priority Level */
+#define REG_DMAC_CHEVCTRL20        (*(RwReg8 *)0x4100A186UL) /**< \brief (DMAC) Channel 20 Event Control */
+#define REG_DMAC_CHINTENCLR20      (*(RwReg8 *)0x4100A18CUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET20      (*(RwReg8 *)0x4100A18DUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG20       (*(RwReg8 *)0x4100A18EUL) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS20        (*(RwReg8 *)0x4100A18FUL) /**< \brief (DMAC) Channel 20 Status */
+#define REG_DMAC_CHCTRLA21         (*(RwReg  *)0x4100A190UL) /**< \brief (DMAC) Channel 21 Control A */
+#define REG_DMAC_CHCTRLB21         (*(RwReg8 *)0x4100A194UL) /**< \brief (DMAC) Channel 21 Control B */
+#define REG_DMAC_CHPRILVL21        (*(RwReg8 *)0x4100A195UL) /**< \brief (DMAC) Channel 21 Priority Level */
+#define REG_DMAC_CHEVCTRL21        (*(RwReg8 *)0x4100A196UL) /**< \brief (DMAC) Channel 21 Event Control */
+#define REG_DMAC_CHINTENCLR21      (*(RwReg8 *)0x4100A19CUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET21      (*(RwReg8 *)0x4100A19DUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG21       (*(RwReg8 *)0x4100A19EUL) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS21        (*(RwReg8 *)0x4100A19FUL) /**< \brief (DMAC) Channel 21 Status */
+#define REG_DMAC_CHCTRLA22         (*(RwReg  *)0x4100A1A0UL) /**< \brief (DMAC) Channel 22 Control A */
+#define REG_DMAC_CHCTRLB22         (*(RwReg8 *)0x4100A1A4UL) /**< \brief (DMAC) Channel 22 Control B */
+#define REG_DMAC_CHPRILVL22        (*(RwReg8 *)0x4100A1A5UL) /**< \brief (DMAC) Channel 22 Priority Level */
+#define REG_DMAC_CHEVCTRL22        (*(RwReg8 *)0x4100A1A6UL) /**< \brief (DMAC) Channel 22 Event Control */
+#define REG_DMAC_CHINTENCLR22      (*(RwReg8 *)0x4100A1ACUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET22      (*(RwReg8 *)0x4100A1ADUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG22       (*(RwReg8 *)0x4100A1AEUL) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS22        (*(RwReg8 *)0x4100A1AFUL) /**< \brief (DMAC) Channel 22 Status */
+#define REG_DMAC_CHCTRLA23         (*(RwReg  *)0x4100A1B0UL) /**< \brief (DMAC) Channel 23 Control A */
+#define REG_DMAC_CHCTRLB23         (*(RwReg8 *)0x4100A1B4UL) /**< \brief (DMAC) Channel 23 Control B */
+#define REG_DMAC_CHPRILVL23        (*(RwReg8 *)0x4100A1B5UL) /**< \brief (DMAC) Channel 23 Priority Level */
+#define REG_DMAC_CHEVCTRL23        (*(RwReg8 *)0x4100A1B6UL) /**< \brief (DMAC) Channel 23 Event Control */
+#define REG_DMAC_CHINTENCLR23      (*(RwReg8 *)0x4100A1BCUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET23      (*(RwReg8 *)0x4100A1BDUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG23       (*(RwReg8 *)0x4100A1BEUL) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS23        (*(RwReg8 *)0x4100A1BFUL) /**< \brief (DMAC) Channel 23 Status */
+#define REG_DMAC_CHCTRLA24         (*(RwReg  *)0x4100A1C0UL) /**< \brief (DMAC) Channel 24 Control A */
+#define REG_DMAC_CHCTRLB24         (*(RwReg8 *)0x4100A1C4UL) /**< \brief (DMAC) Channel 24 Control B */
+#define REG_DMAC_CHPRILVL24        (*(RwReg8 *)0x4100A1C5UL) /**< \brief (DMAC) Channel 24 Priority Level */
+#define REG_DMAC_CHEVCTRL24        (*(RwReg8 *)0x4100A1C6UL) /**< \brief (DMAC) Channel 24 Event Control */
+#define REG_DMAC_CHINTENCLR24      (*(RwReg8 *)0x4100A1CCUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET24      (*(RwReg8 *)0x4100A1CDUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG24       (*(RwReg8 *)0x4100A1CEUL) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS24        (*(RwReg8 *)0x4100A1CFUL) /**< \brief (DMAC) Channel 24 Status */
+#define REG_DMAC_CHCTRLA25         (*(RwReg  *)0x4100A1D0UL) /**< \brief (DMAC) Channel 25 Control A */
+#define REG_DMAC_CHCTRLB25         (*(RwReg8 *)0x4100A1D4UL) /**< \brief (DMAC) Channel 25 Control B */
+#define REG_DMAC_CHPRILVL25        (*(RwReg8 *)0x4100A1D5UL) /**< \brief (DMAC) Channel 25 Priority Level */
+#define REG_DMAC_CHEVCTRL25        (*(RwReg8 *)0x4100A1D6UL) /**< \brief (DMAC) Channel 25 Event Control */
+#define REG_DMAC_CHINTENCLR25      (*(RwReg8 *)0x4100A1DCUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET25      (*(RwReg8 *)0x4100A1DDUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG25       (*(RwReg8 *)0x4100A1DEUL) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS25        (*(RwReg8 *)0x4100A1DFUL) /**< \brief (DMAC) Channel 25 Status */
+#define REG_DMAC_CHCTRLA26         (*(RwReg  *)0x4100A1E0UL) /**< \brief (DMAC) Channel 26 Control A */
+#define REG_DMAC_CHCTRLB26         (*(RwReg8 *)0x4100A1E4UL) /**< \brief (DMAC) Channel 26 Control B */
+#define REG_DMAC_CHPRILVL26        (*(RwReg8 *)0x4100A1E5UL) /**< \brief (DMAC) Channel 26 Priority Level */
+#define REG_DMAC_CHEVCTRL26        (*(RwReg8 *)0x4100A1E6UL) /**< \brief (DMAC) Channel 26 Event Control */
+#define REG_DMAC_CHINTENCLR26      (*(RwReg8 *)0x4100A1ECUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET26      (*(RwReg8 *)0x4100A1EDUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG26       (*(RwReg8 *)0x4100A1EEUL) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS26        (*(RwReg8 *)0x4100A1EFUL) /**< \brief (DMAC) Channel 26 Status */
+#define REG_DMAC_CHCTRLA27         (*(RwReg  *)0x4100A1F0UL) /**< \brief (DMAC) Channel 27 Control A */
+#define REG_DMAC_CHCTRLB27         (*(RwReg8 *)0x4100A1F4UL) /**< \brief (DMAC) Channel 27 Control B */
+#define REG_DMAC_CHPRILVL27        (*(RwReg8 *)0x4100A1F5UL) /**< \brief (DMAC) Channel 27 Priority Level */
+#define REG_DMAC_CHEVCTRL27        (*(RwReg8 *)0x4100A1F6UL) /**< \brief (DMAC) Channel 27 Event Control */
+#define REG_DMAC_CHINTENCLR27      (*(RwReg8 *)0x4100A1FCUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET27      (*(RwReg8 *)0x4100A1FDUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG27       (*(RwReg8 *)0x4100A1FEUL) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS27        (*(RwReg8 *)0x4100A1FFUL) /**< \brief (DMAC) Channel 27 Status */
+#define REG_DMAC_CHCTRLA28         (*(RwReg  *)0x4100A200UL) /**< \brief (DMAC) Channel 28 Control A */
+#define REG_DMAC_CHCTRLB28         (*(RwReg8 *)0x4100A204UL) /**< \brief (DMAC) Channel 28 Control B */
+#define REG_DMAC_CHPRILVL28        (*(RwReg8 *)0x4100A205UL) /**< \brief (DMAC) Channel 28 Priority Level */
+#define REG_DMAC_CHEVCTRL28        (*(RwReg8 *)0x4100A206UL) /**< \brief (DMAC) Channel 28 Event Control */
+#define REG_DMAC_CHINTENCLR28      (*(RwReg8 *)0x4100A20CUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET28      (*(RwReg8 *)0x4100A20DUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG28       (*(RwReg8 *)0x4100A20EUL) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS28        (*(RwReg8 *)0x4100A20FUL) /**< \brief (DMAC) Channel 28 Status */
+#define REG_DMAC_CHCTRLA29         (*(RwReg  *)0x4100A210UL) /**< \brief (DMAC) Channel 29 Control A */
+#define REG_DMAC_CHCTRLB29         (*(RwReg8 *)0x4100A214UL) /**< \brief (DMAC) Channel 29 Control B */
+#define REG_DMAC_CHPRILVL29        (*(RwReg8 *)0x4100A215UL) /**< \brief (DMAC) Channel 29 Priority Level */
+#define REG_DMAC_CHEVCTRL29        (*(RwReg8 *)0x4100A216UL) /**< \brief (DMAC) Channel 29 Event Control */
+#define REG_DMAC_CHINTENCLR29      (*(RwReg8 *)0x4100A21CUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET29      (*(RwReg8 *)0x4100A21DUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG29       (*(RwReg8 *)0x4100A21EUL) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS29        (*(RwReg8 *)0x4100A21FUL) /**< \brief (DMAC) Channel 29 Status */
+#define REG_DMAC_CHCTRLA30         (*(RwReg  *)0x4100A220UL) /**< \brief (DMAC) Channel 30 Control A */
+#define REG_DMAC_CHCTRLB30         (*(RwReg8 *)0x4100A224UL) /**< \brief (DMAC) Channel 30 Control B */
+#define REG_DMAC_CHPRILVL30        (*(RwReg8 *)0x4100A225UL) /**< \brief (DMAC) Channel 30 Priority Level */
+#define REG_DMAC_CHEVCTRL30        (*(RwReg8 *)0x4100A226UL) /**< \brief (DMAC) Channel 30 Event Control */
+#define REG_DMAC_CHINTENCLR30      (*(RwReg8 *)0x4100A22CUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET30      (*(RwReg8 *)0x4100A22DUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG30       (*(RwReg8 *)0x4100A22EUL) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS30        (*(RwReg8 *)0x4100A22FUL) /**< \brief (DMAC) Channel 30 Status */
+#define REG_DMAC_CHCTRLA31         (*(RwReg  *)0x4100A230UL) /**< \brief (DMAC) Channel 31 Control A */
+#define REG_DMAC_CHCTRLB31         (*(RwReg8 *)0x4100A234UL) /**< \brief (DMAC) Channel 31 Control B */
+#define REG_DMAC_CHPRILVL31        (*(RwReg8 *)0x4100A235UL) /**< \brief (DMAC) Channel 31 Priority Level */
+#define REG_DMAC_CHEVCTRL31        (*(RwReg8 *)0x4100A236UL) /**< \brief (DMAC) Channel 31 Event Control */
+#define REG_DMAC_CHINTENCLR31      (*(RwReg8 *)0x4100A23CUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET31      (*(RwReg8 *)0x4100A23DUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG31       (*(RwReg8 *)0x4100A23EUL) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS31        (*(RwReg8 *)0x4100A23FUL) /**< \brief (DMAC) Channel 31 Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_BURST                  1        // 0: no burst support; 1: burst support
+#define DMAC_CH_BITS                5        // Number of bits to select channel
+#define DMAC_CH_NUM                 32       // Number of channels
+#define DMAC_CLK_AHB_ID             9        // AHB clock index
+#define DMAC_EVIN_NUM               8        // Number of input events
+#define DMAC_EVOUT_NUM              4        // Number of output events
+#define DMAC_FIFO_SIZE              16       // FIFO size for burst mode.
+#define DMAC_LVL_BITS               2        // Number of bits to select level priority
+#define DMAC_LVL_NUM                4        // Enable priority level number
+#define DMAC_QOSCTRL_D_RESETVALUE   2        // QOS dmac ahb interface reset value
+#define DMAC_QOSCTRL_F_RESETVALUE   2        // QOS dmac fetch interface reset value
+#define DMAC_QOSCTRL_WRB_RESETVALUE 2        // QOS dmac write back interface reset value
+#define DMAC_TRIG_BITS              7        // Number of bits to select trigger source
+#define DMAC_TRIG_NUM               85       // Number of peripheral triggers
+
+#endif /* _SAME53_DMAC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dsu.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dsu.h
new file mode 100644
index 000000000..5f541d582
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/dsu.h	
@@ -0,0 +1,95 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_DSU_INSTANCE_
+#define _SAME53_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL               (0x41002000) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (0x41002001) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (0x41002002) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (0x41002004) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (0x41002008) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (0x4100200C) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (0x41002018) /**< \brief (DSU) Device Identification */
+#define REG_DSU_CFG                (0x4100201C) /**< \brief (DSU) Configuration */
+#define REG_DSU_ENTRY0             (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
+#define REG_DSU_END                (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
+#define REG_DSU_MEMTYPE            (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
+#define REG_DSU_PID4               (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5               (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6               (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7               (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0               (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR               (*(RwReg  *)0x41002004UL) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008UL) /**< \brief (DSU) Length */
+#define REG_DSU_DATA               (*(RwReg  *)0x4100200CUL) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0               (*(RwReg  *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1               (*(RwReg  *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID                (*(RoReg  *)0x41002018UL) /**< \brief (DSU) Device Identification */
+#define REG_DSU_CFG                (*(RwReg  *)0x4100201CUL) /**< \brief (DSU) Configuration */
+#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
+#define REG_DSU_END                (*(RoReg  *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
+#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
+#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5               (*(RoReg  *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6               (*(RoReg  *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7               (*(RoReg  *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3               (*(RoReg  *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_AHB_ID              4       
+#define DSU_DMAC_ID_DCC0            2        // DMAC ID for DCC0 register
+#define DSU_DMAC_ID_DCC1            3        // DMAC ID for DCC1 register
+
+#endif /* _SAME53_DSU_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/eic.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/eic.h
new file mode 100644
index 000000000..dcbd62bda
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/eic.h	
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_EIC_INSTANCE_
+#define _SAME53_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRLA              (0x40002800) /**< \brief (EIC) Control A */
+#define REG_EIC_NMICTRL            (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_SYNCBUSY           (0x40002804) /**< \brief (EIC) Synchronization Busy */
+#define REG_EIC_EVCTRL             (0x40002808) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_ASYNCH             (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */
+#define REG_EIC_CONFIG0            (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
+#define REG_EIC_CONFIG1            (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
+#define REG_EIC_DEBOUNCEN          (0x40002830) /**< \brief (EIC) Debouncer Enable */
+#define REG_EIC_DPRESCALER         (0x40002834) /**< \brief (EIC) Debouncer Prescaler */
+#define REG_EIC_PINSTATE           (0x40002838) /**< \brief (EIC) Pin State */
+#else
+#define REG_EIC_CTRLA              (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */
+#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG            (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_SYNCBUSY           (*(RoReg  *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */
+#define REG_EIC_EVCTRL             (*(RwReg  *)0x40002808UL) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR           (*(RwReg  *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET           (*(RwReg  *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG            (*(RwReg  *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_ASYNCH             (*(RwReg  *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */
+#define REG_EIC_CONFIG0            (*(RwReg  *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
+#define REG_EIC_CONFIG1            (*(RwReg  *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
+#define REG_EIC_DEBOUNCEN          (*(RwReg  *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */
+#define REG_EIC_DPRESCALER         (*(RwReg  *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */
+#define REG_EIC_PINSTATE           (*(RoReg  *)0x40002838UL) /**< \brief (EIC) Pin State */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_EXTINT_NUM              16       // Number of external interrupts
+#define EIC_GCLK_ID                 4        // Generic Clock index
+#define EIC_NUMBER_OF_CONFIG_REGS   2        // Number of CONFIG registers
+#define EIC_NUMBER_OF_DPRESCALER_REGS 2        // Number of DPRESCALER pin groups
+#define EIC_NUMBER_OF_INTERRUPTS    16       // Number of external interrupts (obsolete)
+
+#endif /* _SAME53_EIC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/evsys.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/evsys.h
new file mode 100644
index 000000000..4af1b57a3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/evsys.h	
@@ -0,0 +1,720 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_EVSYS_INSTANCE_
+#define _SAME53_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRLA            (0x4100E000) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_SWEVT            (0x4100E004) /**< \brief (EVSYS) Software Event */
+#define REG_EVSYS_PRICTRL          (0x4100E008) /**< \brief (EVSYS) Priority Control */
+#define REG_EVSYS_INTPEND          (0x4100E010) /**< \brief (EVSYS) Channel Pending Interrupt */
+#define REG_EVSYS_INTSTATUS        (0x4100E014) /**< \brief (EVSYS) Interrupt Status */
+#define REG_EVSYS_BUSYCH           (0x4100E018) /**< \brief (EVSYS) Busy Channels */
+#define REG_EVSYS_READYUSR         (0x4100E01C) /**< \brief (EVSYS) Ready Users */
+#define REG_EVSYS_CHANNEL0         (0x4100E020) /**< \brief (EVSYS) Channel 0 Control */
+#define REG_EVSYS_CHINTENCLR0      (0x4100E024) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET0      (0x4100E025) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG0       (0x4100E026) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS0        (0x4100E027) /**< \brief (EVSYS) Channel 0 Status */
+#define REG_EVSYS_CHANNEL1         (0x4100E028) /**< \brief (EVSYS) Channel 1 Control */
+#define REG_EVSYS_CHINTENCLR1      (0x4100E02C) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET1      (0x4100E02D) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG1       (0x4100E02E) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS1        (0x4100E02F) /**< \brief (EVSYS) Channel 1 Status */
+#define REG_EVSYS_CHANNEL2         (0x4100E030) /**< \brief (EVSYS) Channel 2 Control */
+#define REG_EVSYS_CHINTENCLR2      (0x4100E034) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET2      (0x4100E035) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG2       (0x4100E036) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS2        (0x4100E037) /**< \brief (EVSYS) Channel 2 Status */
+#define REG_EVSYS_CHANNEL3         (0x4100E038) /**< \brief (EVSYS) Channel 3 Control */
+#define REG_EVSYS_CHINTENCLR3      (0x4100E03C) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET3      (0x4100E03D) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG3       (0x4100E03E) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS3        (0x4100E03F) /**< \brief (EVSYS) Channel 3 Status */
+#define REG_EVSYS_CHANNEL4         (0x4100E040) /**< \brief (EVSYS) Channel 4 Control */
+#define REG_EVSYS_CHINTENCLR4      (0x4100E044) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET4      (0x4100E045) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG4       (0x4100E046) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS4        (0x4100E047) /**< \brief (EVSYS) Channel 4 Status */
+#define REG_EVSYS_CHANNEL5         (0x4100E048) /**< \brief (EVSYS) Channel 5 Control */
+#define REG_EVSYS_CHINTENCLR5      (0x4100E04C) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET5      (0x4100E04D) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG5       (0x4100E04E) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS5        (0x4100E04F) /**< \brief (EVSYS) Channel 5 Status */
+#define REG_EVSYS_CHANNEL6         (0x4100E050) /**< \brief (EVSYS) Channel 6 Control */
+#define REG_EVSYS_CHINTENCLR6      (0x4100E054) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET6      (0x4100E055) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG6       (0x4100E056) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS6        (0x4100E057) /**< \brief (EVSYS) Channel 6 Status */
+#define REG_EVSYS_CHANNEL7         (0x4100E058) /**< \brief (EVSYS) Channel 7 Control */
+#define REG_EVSYS_CHINTENCLR7      (0x4100E05C) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET7      (0x4100E05D) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG7       (0x4100E05E) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS7        (0x4100E05F) /**< \brief (EVSYS) Channel 7 Status */
+#define REG_EVSYS_CHANNEL8         (0x4100E060) /**< \brief (EVSYS) Channel 8 Control */
+#define REG_EVSYS_CHINTENCLR8      (0x4100E064) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET8      (0x4100E065) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG8       (0x4100E066) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS8        (0x4100E067) /**< \brief (EVSYS) Channel 8 Status */
+#define REG_EVSYS_CHANNEL9         (0x4100E068) /**< \brief (EVSYS) Channel 9 Control */
+#define REG_EVSYS_CHINTENCLR9      (0x4100E06C) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET9      (0x4100E06D) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG9       (0x4100E06E) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS9        (0x4100E06F) /**< \brief (EVSYS) Channel 9 Status */
+#define REG_EVSYS_CHANNEL10        (0x4100E070) /**< \brief (EVSYS) Channel 10 Control */
+#define REG_EVSYS_CHINTENCLR10     (0x4100E074) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET10     (0x4100E075) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG10      (0x4100E076) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS10       (0x4100E077) /**< \brief (EVSYS) Channel 10 Status */
+#define REG_EVSYS_CHANNEL11        (0x4100E078) /**< \brief (EVSYS) Channel 11 Control */
+#define REG_EVSYS_CHINTENCLR11     (0x4100E07C) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET11     (0x4100E07D) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG11      (0x4100E07E) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS11       (0x4100E07F) /**< \brief (EVSYS) Channel 11 Status */
+#define REG_EVSYS_CHANNEL12        (0x4100E080) /**< \brief (EVSYS) Channel 12 Control */
+#define REG_EVSYS_CHINTENCLR12     (0x4100E084) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET12     (0x4100E085) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG12      (0x4100E086) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS12       (0x4100E087) /**< \brief (EVSYS) Channel 12 Status */
+#define REG_EVSYS_CHANNEL13        (0x4100E088) /**< \brief (EVSYS) Channel 13 Control */
+#define REG_EVSYS_CHINTENCLR13     (0x4100E08C) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET13     (0x4100E08D) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG13      (0x4100E08E) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS13       (0x4100E08F) /**< \brief (EVSYS) Channel 13 Status */
+#define REG_EVSYS_CHANNEL14        (0x4100E090) /**< \brief (EVSYS) Channel 14 Control */
+#define REG_EVSYS_CHINTENCLR14     (0x4100E094) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET14     (0x4100E095) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG14      (0x4100E096) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS14       (0x4100E097) /**< \brief (EVSYS) Channel 14 Status */
+#define REG_EVSYS_CHANNEL15        (0x4100E098) /**< \brief (EVSYS) Channel 15 Control */
+#define REG_EVSYS_CHINTENCLR15     (0x4100E09C) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET15     (0x4100E09D) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG15      (0x4100E09E) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS15       (0x4100E09F) /**< \brief (EVSYS) Channel 15 Status */
+#define REG_EVSYS_CHANNEL16        (0x4100E0A0) /**< \brief (EVSYS) Channel 16 Control */
+#define REG_EVSYS_CHINTENCLR16     (0x4100E0A4) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET16     (0x4100E0A5) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG16      (0x4100E0A6) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS16       (0x4100E0A7) /**< \brief (EVSYS) Channel 16 Status */
+#define REG_EVSYS_CHANNEL17        (0x4100E0A8) /**< \brief (EVSYS) Channel 17 Control */
+#define REG_EVSYS_CHINTENCLR17     (0x4100E0AC) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET17     (0x4100E0AD) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG17      (0x4100E0AE) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS17       (0x4100E0AF) /**< \brief (EVSYS) Channel 17 Status */
+#define REG_EVSYS_CHANNEL18        (0x4100E0B0) /**< \brief (EVSYS) Channel 18 Control */
+#define REG_EVSYS_CHINTENCLR18     (0x4100E0B4) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET18     (0x4100E0B5) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG18      (0x4100E0B6) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS18       (0x4100E0B7) /**< \brief (EVSYS) Channel 18 Status */
+#define REG_EVSYS_CHANNEL19        (0x4100E0B8) /**< \brief (EVSYS) Channel 19 Control */
+#define REG_EVSYS_CHINTENCLR19     (0x4100E0BC) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET19     (0x4100E0BD) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG19      (0x4100E0BE) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS19       (0x4100E0BF) /**< \brief (EVSYS) Channel 19 Status */
+#define REG_EVSYS_CHANNEL20        (0x4100E0C0) /**< \brief (EVSYS) Channel 20 Control */
+#define REG_EVSYS_CHINTENCLR20     (0x4100E0C4) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET20     (0x4100E0C5) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG20      (0x4100E0C6) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS20       (0x4100E0C7) /**< \brief (EVSYS) Channel 20 Status */
+#define REG_EVSYS_CHANNEL21        (0x4100E0C8) /**< \brief (EVSYS) Channel 21 Control */
+#define REG_EVSYS_CHINTENCLR21     (0x4100E0CC) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET21     (0x4100E0CD) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG21      (0x4100E0CE) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS21       (0x4100E0CF) /**< \brief (EVSYS) Channel 21 Status */
+#define REG_EVSYS_CHANNEL22        (0x4100E0D0) /**< \brief (EVSYS) Channel 22 Control */
+#define REG_EVSYS_CHINTENCLR22     (0x4100E0D4) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET22     (0x4100E0D5) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG22      (0x4100E0D6) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS22       (0x4100E0D7) /**< \brief (EVSYS) Channel 22 Status */
+#define REG_EVSYS_CHANNEL23        (0x4100E0D8) /**< \brief (EVSYS) Channel 23 Control */
+#define REG_EVSYS_CHINTENCLR23     (0x4100E0DC) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET23     (0x4100E0DD) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG23      (0x4100E0DE) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS23       (0x4100E0DF) /**< \brief (EVSYS) Channel 23 Status */
+#define REG_EVSYS_CHANNEL24        (0x4100E0E0) /**< \brief (EVSYS) Channel 24 Control */
+#define REG_EVSYS_CHINTENCLR24     (0x4100E0E4) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET24     (0x4100E0E5) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG24      (0x4100E0E6) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS24       (0x4100E0E7) /**< \brief (EVSYS) Channel 24 Status */
+#define REG_EVSYS_CHANNEL25        (0x4100E0E8) /**< \brief (EVSYS) Channel 25 Control */
+#define REG_EVSYS_CHINTENCLR25     (0x4100E0EC) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET25     (0x4100E0ED) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG25      (0x4100E0EE) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS25       (0x4100E0EF) /**< \brief (EVSYS) Channel 25 Status */
+#define REG_EVSYS_CHANNEL26        (0x4100E0F0) /**< \brief (EVSYS) Channel 26 Control */
+#define REG_EVSYS_CHINTENCLR26     (0x4100E0F4) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET26     (0x4100E0F5) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG26      (0x4100E0F6) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS26       (0x4100E0F7) /**< \brief (EVSYS) Channel 26 Status */
+#define REG_EVSYS_CHANNEL27        (0x4100E0F8) /**< \brief (EVSYS) Channel 27 Control */
+#define REG_EVSYS_CHINTENCLR27     (0x4100E0FC) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET27     (0x4100E0FD) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG27      (0x4100E0FE) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS27       (0x4100E0FF) /**< \brief (EVSYS) Channel 27 Status */
+#define REG_EVSYS_CHANNEL28        (0x4100E100) /**< \brief (EVSYS) Channel 28 Control */
+#define REG_EVSYS_CHINTENCLR28     (0x4100E104) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET28     (0x4100E105) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG28      (0x4100E106) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS28       (0x4100E107) /**< \brief (EVSYS) Channel 28 Status */
+#define REG_EVSYS_CHANNEL29        (0x4100E108) /**< \brief (EVSYS) Channel 29 Control */
+#define REG_EVSYS_CHINTENCLR29     (0x4100E10C) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET29     (0x4100E10D) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG29      (0x4100E10E) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS29       (0x4100E10F) /**< \brief (EVSYS) Channel 29 Status */
+#define REG_EVSYS_CHANNEL30        (0x4100E110) /**< \brief (EVSYS) Channel 30 Control */
+#define REG_EVSYS_CHINTENCLR30     (0x4100E114) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET30     (0x4100E115) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG30      (0x4100E116) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS30       (0x4100E117) /**< \brief (EVSYS) Channel 30 Status */
+#define REG_EVSYS_CHANNEL31        (0x4100E118) /**< \brief (EVSYS) Channel 31 Control */
+#define REG_EVSYS_CHINTENCLR31     (0x4100E11C) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET31     (0x4100E11D) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG31      (0x4100E11E) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS31       (0x4100E11F) /**< \brief (EVSYS) Channel 31 Status */
+#define REG_EVSYS_USER0            (0x4100E120) /**< \brief (EVSYS) User Multiplexer 0 */
+#define REG_EVSYS_USER1            (0x4100E124) /**< \brief (EVSYS) User Multiplexer 1 */
+#define REG_EVSYS_USER2            (0x4100E128) /**< \brief (EVSYS) User Multiplexer 2 */
+#define REG_EVSYS_USER3            (0x4100E12C) /**< \brief (EVSYS) User Multiplexer 3 */
+#define REG_EVSYS_USER4            (0x4100E130) /**< \brief (EVSYS) User Multiplexer 4 */
+#define REG_EVSYS_USER5            (0x4100E134) /**< \brief (EVSYS) User Multiplexer 5 */
+#define REG_EVSYS_USER6            (0x4100E138) /**< \brief (EVSYS) User Multiplexer 6 */
+#define REG_EVSYS_USER7            (0x4100E13C) /**< \brief (EVSYS) User Multiplexer 7 */
+#define REG_EVSYS_USER8            (0x4100E140) /**< \brief (EVSYS) User Multiplexer 8 */
+#define REG_EVSYS_USER9            (0x4100E144) /**< \brief (EVSYS) User Multiplexer 9 */
+#define REG_EVSYS_USER10           (0x4100E148) /**< \brief (EVSYS) User Multiplexer 10 */
+#define REG_EVSYS_USER11           (0x4100E14C) /**< \brief (EVSYS) User Multiplexer 11 */
+#define REG_EVSYS_USER12           (0x4100E150) /**< \brief (EVSYS) User Multiplexer 12 */
+#define REG_EVSYS_USER13           (0x4100E154) /**< \brief (EVSYS) User Multiplexer 13 */
+#define REG_EVSYS_USER14           (0x4100E158) /**< \brief (EVSYS) User Multiplexer 14 */
+#define REG_EVSYS_USER15           (0x4100E15C) /**< \brief (EVSYS) User Multiplexer 15 */
+#define REG_EVSYS_USER16           (0x4100E160) /**< \brief (EVSYS) User Multiplexer 16 */
+#define REG_EVSYS_USER17           (0x4100E164) /**< \brief (EVSYS) User Multiplexer 17 */
+#define REG_EVSYS_USER18           (0x4100E168) /**< \brief (EVSYS) User Multiplexer 18 */
+#define REG_EVSYS_USER19           (0x4100E16C) /**< \brief (EVSYS) User Multiplexer 19 */
+#define REG_EVSYS_USER20           (0x4100E170) /**< \brief (EVSYS) User Multiplexer 20 */
+#define REG_EVSYS_USER21           (0x4100E174) /**< \brief (EVSYS) User Multiplexer 21 */
+#define REG_EVSYS_USER22           (0x4100E178) /**< \brief (EVSYS) User Multiplexer 22 */
+#define REG_EVSYS_USER23           (0x4100E17C) /**< \brief (EVSYS) User Multiplexer 23 */
+#define REG_EVSYS_USER24           (0x4100E180) /**< \brief (EVSYS) User Multiplexer 24 */
+#define REG_EVSYS_USER25           (0x4100E184) /**< \brief (EVSYS) User Multiplexer 25 */
+#define REG_EVSYS_USER26           (0x4100E188) /**< \brief (EVSYS) User Multiplexer 26 */
+#define REG_EVSYS_USER27           (0x4100E18C) /**< \brief (EVSYS) User Multiplexer 27 */
+#define REG_EVSYS_USER28           (0x4100E190) /**< \brief (EVSYS) User Multiplexer 28 */
+#define REG_EVSYS_USER29           (0x4100E194) /**< \brief (EVSYS) User Multiplexer 29 */
+#define REG_EVSYS_USER30           (0x4100E198) /**< \brief (EVSYS) User Multiplexer 30 */
+#define REG_EVSYS_USER31           (0x4100E19C) /**< \brief (EVSYS) User Multiplexer 31 */
+#define REG_EVSYS_USER32           (0x4100E1A0) /**< \brief (EVSYS) User Multiplexer 32 */
+#define REG_EVSYS_USER33           (0x4100E1A4) /**< \brief (EVSYS) User Multiplexer 33 */
+#define REG_EVSYS_USER34           (0x4100E1A8) /**< \brief (EVSYS) User Multiplexer 34 */
+#define REG_EVSYS_USER35           (0x4100E1AC) /**< \brief (EVSYS) User Multiplexer 35 */
+#define REG_EVSYS_USER36           (0x4100E1B0) /**< \brief (EVSYS) User Multiplexer 36 */
+#define REG_EVSYS_USER37           (0x4100E1B4) /**< \brief (EVSYS) User Multiplexer 37 */
+#define REG_EVSYS_USER38           (0x4100E1B8) /**< \brief (EVSYS) User Multiplexer 38 */
+#define REG_EVSYS_USER39           (0x4100E1BC) /**< \brief (EVSYS) User Multiplexer 39 */
+#define REG_EVSYS_USER40           (0x4100E1C0) /**< \brief (EVSYS) User Multiplexer 40 */
+#define REG_EVSYS_USER41           (0x4100E1C4) /**< \brief (EVSYS) User Multiplexer 41 */
+#define REG_EVSYS_USER42           (0x4100E1C8) /**< \brief (EVSYS) User Multiplexer 42 */
+#define REG_EVSYS_USER43           (0x4100E1CC) /**< \brief (EVSYS) User Multiplexer 43 */
+#define REG_EVSYS_USER44           (0x4100E1D0) /**< \brief (EVSYS) User Multiplexer 44 */
+#define REG_EVSYS_USER45           (0x4100E1D4) /**< \brief (EVSYS) User Multiplexer 45 */
+#define REG_EVSYS_USER46           (0x4100E1D8) /**< \brief (EVSYS) User Multiplexer 46 */
+#define REG_EVSYS_USER47           (0x4100E1DC) /**< \brief (EVSYS) User Multiplexer 47 */
+#define REG_EVSYS_USER48           (0x4100E1E0) /**< \brief (EVSYS) User Multiplexer 48 */
+#define REG_EVSYS_USER49           (0x4100E1E4) /**< \brief (EVSYS) User Multiplexer 49 */
+#define REG_EVSYS_USER50           (0x4100E1E8) /**< \brief (EVSYS) User Multiplexer 50 */
+#define REG_EVSYS_USER51           (0x4100E1EC) /**< \brief (EVSYS) User Multiplexer 51 */
+#define REG_EVSYS_USER52           (0x4100E1F0) /**< \brief (EVSYS) User Multiplexer 52 */
+#define REG_EVSYS_USER53           (0x4100E1F4) /**< \brief (EVSYS) User Multiplexer 53 */
+#define REG_EVSYS_USER54           (0x4100E1F8) /**< \brief (EVSYS) User Multiplexer 54 */
+#define REG_EVSYS_USER55           (0x4100E1FC) /**< \brief (EVSYS) User Multiplexer 55 */
+#define REG_EVSYS_USER56           (0x4100E200) /**< \brief (EVSYS) User Multiplexer 56 */
+#define REG_EVSYS_USER57           (0x4100E204) /**< \brief (EVSYS) User Multiplexer 57 */
+#define REG_EVSYS_USER58           (0x4100E208) /**< \brief (EVSYS) User Multiplexer 58 */
+#define REG_EVSYS_USER59           (0x4100E20C) /**< \brief (EVSYS) User Multiplexer 59 */
+#define REG_EVSYS_USER60           (0x4100E210) /**< \brief (EVSYS) User Multiplexer 60 */
+#define REG_EVSYS_USER61           (0x4100E214) /**< \brief (EVSYS) User Multiplexer 61 */
+#define REG_EVSYS_USER62           (0x4100E218) /**< \brief (EVSYS) User Multiplexer 62 */
+#define REG_EVSYS_USER63           (0x4100E21C) /**< \brief (EVSYS) User Multiplexer 63 */
+#define REG_EVSYS_USER64           (0x4100E220) /**< \brief (EVSYS) User Multiplexer 64 */
+#define REG_EVSYS_USER65           (0x4100E224) /**< \brief (EVSYS) User Multiplexer 65 */
+#define REG_EVSYS_USER66           (0x4100E228) /**< \brief (EVSYS) User Multiplexer 66 */
+#else
+#define REG_EVSYS_CTRLA            (*(RwReg8 *)0x4100E000UL) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_SWEVT            (*(WoReg  *)0x4100E004UL) /**< \brief (EVSYS) Software Event */
+#define REG_EVSYS_PRICTRL          (*(RwReg8 *)0x4100E008UL) /**< \brief (EVSYS) Priority Control */
+#define REG_EVSYS_INTPEND          (*(RwReg16*)0x4100E010UL) /**< \brief (EVSYS) Channel Pending Interrupt */
+#define REG_EVSYS_INTSTATUS        (*(RoReg  *)0x4100E014UL) /**< \brief (EVSYS) Interrupt Status */
+#define REG_EVSYS_BUSYCH           (*(RoReg  *)0x4100E018UL) /**< \brief (EVSYS) Busy Channels */
+#define REG_EVSYS_READYUSR         (*(RoReg  *)0x4100E01CUL) /**< \brief (EVSYS) Ready Users */
+#define REG_EVSYS_CHANNEL0         (*(RwReg  *)0x4100E020UL) /**< \brief (EVSYS) Channel 0 Control */
+#define REG_EVSYS_CHINTENCLR0      (*(RwReg8 *)0x4100E024UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET0      (*(RwReg8 *)0x4100E025UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG0       (*(RwReg8 *)0x4100E026UL) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS0        (*(RoReg8 *)0x4100E027UL) /**< \brief (EVSYS) Channel 0 Status */
+#define REG_EVSYS_CHANNEL1         (*(RwReg  *)0x4100E028UL) /**< \brief (EVSYS) Channel 1 Control */
+#define REG_EVSYS_CHINTENCLR1      (*(RwReg8 *)0x4100E02CUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET1      (*(RwReg8 *)0x4100E02DUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG1       (*(RwReg8 *)0x4100E02EUL) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS1        (*(RoReg8 *)0x4100E02FUL) /**< \brief (EVSYS) Channel 1 Status */
+#define REG_EVSYS_CHANNEL2         (*(RwReg  *)0x4100E030UL) /**< \brief (EVSYS) Channel 2 Control */
+#define REG_EVSYS_CHINTENCLR2      (*(RwReg8 *)0x4100E034UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET2      (*(RwReg8 *)0x4100E035UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG2       (*(RwReg8 *)0x4100E036UL) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS2        (*(RoReg8 *)0x4100E037UL) /**< \brief (EVSYS) Channel 2 Status */
+#define REG_EVSYS_CHANNEL3         (*(RwReg  *)0x4100E038UL) /**< \brief (EVSYS) Channel 3 Control */
+#define REG_EVSYS_CHINTENCLR3      (*(RwReg8 *)0x4100E03CUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET3      (*(RwReg8 *)0x4100E03DUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG3       (*(RwReg8 *)0x4100E03EUL) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS3        (*(RoReg8 *)0x4100E03FUL) /**< \brief (EVSYS) Channel 3 Status */
+#define REG_EVSYS_CHANNEL4         (*(RwReg  *)0x4100E040UL) /**< \brief (EVSYS) Channel 4 Control */
+#define REG_EVSYS_CHINTENCLR4      (*(RwReg8 *)0x4100E044UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET4      (*(RwReg8 *)0x4100E045UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG4       (*(RwReg8 *)0x4100E046UL) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS4        (*(RoReg8 *)0x4100E047UL) /**< \brief (EVSYS) Channel 4 Status */
+#define REG_EVSYS_CHANNEL5         (*(RwReg  *)0x4100E048UL) /**< \brief (EVSYS) Channel 5 Control */
+#define REG_EVSYS_CHINTENCLR5      (*(RwReg8 *)0x4100E04CUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET5      (*(RwReg8 *)0x4100E04DUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG5       (*(RwReg8 *)0x4100E04EUL) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS5        (*(RoReg8 *)0x4100E04FUL) /**< \brief (EVSYS) Channel 5 Status */
+#define REG_EVSYS_CHANNEL6         (*(RwReg  *)0x4100E050UL) /**< \brief (EVSYS) Channel 6 Control */
+#define REG_EVSYS_CHINTENCLR6      (*(RwReg8 *)0x4100E054UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET6      (*(RwReg8 *)0x4100E055UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG6       (*(RwReg8 *)0x4100E056UL) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS6        (*(RoReg8 *)0x4100E057UL) /**< \brief (EVSYS) Channel 6 Status */
+#define REG_EVSYS_CHANNEL7         (*(RwReg  *)0x4100E058UL) /**< \brief (EVSYS) Channel 7 Control */
+#define REG_EVSYS_CHINTENCLR7      (*(RwReg8 *)0x4100E05CUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET7      (*(RwReg8 *)0x4100E05DUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG7       (*(RwReg8 *)0x4100E05EUL) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS7        (*(RoReg8 *)0x4100E05FUL) /**< \brief (EVSYS) Channel 7 Status */
+#define REG_EVSYS_CHANNEL8         (*(RwReg  *)0x4100E060UL) /**< \brief (EVSYS) Channel 8 Control */
+#define REG_EVSYS_CHINTENCLR8      (*(RwReg8 *)0x4100E064UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET8      (*(RwReg8 *)0x4100E065UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG8       (*(RwReg8 *)0x4100E066UL) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS8        (*(RoReg8 *)0x4100E067UL) /**< \brief (EVSYS) Channel 8 Status */
+#define REG_EVSYS_CHANNEL9         (*(RwReg  *)0x4100E068UL) /**< \brief (EVSYS) Channel 9 Control */
+#define REG_EVSYS_CHINTENCLR9      (*(RwReg8 *)0x4100E06CUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET9      (*(RwReg8 *)0x4100E06DUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG9       (*(RwReg8 *)0x4100E06EUL) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS9        (*(RoReg8 *)0x4100E06FUL) /**< \brief (EVSYS) Channel 9 Status */
+#define REG_EVSYS_CHANNEL10        (*(RwReg  *)0x4100E070UL) /**< \brief (EVSYS) Channel 10 Control */
+#define REG_EVSYS_CHINTENCLR10     (*(RwReg8 *)0x4100E074UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET10     (*(RwReg8 *)0x4100E075UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG10      (*(RwReg8 *)0x4100E076UL) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS10       (*(RoReg8 *)0x4100E077UL) /**< \brief (EVSYS) Channel 10 Status */
+#define REG_EVSYS_CHANNEL11        (*(RwReg  *)0x4100E078UL) /**< \brief (EVSYS) Channel 11 Control */
+#define REG_EVSYS_CHINTENCLR11     (*(RwReg8 *)0x4100E07CUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET11     (*(RwReg8 *)0x4100E07DUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG11      (*(RwReg8 *)0x4100E07EUL) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS11       (*(RoReg8 *)0x4100E07FUL) /**< \brief (EVSYS) Channel 11 Status */
+#define REG_EVSYS_CHANNEL12        (*(RwReg  *)0x4100E080UL) /**< \brief (EVSYS) Channel 12 Control */
+#define REG_EVSYS_CHINTENCLR12     (*(RwReg8 *)0x4100E084UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET12     (*(RwReg8 *)0x4100E085UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG12      (*(RwReg8 *)0x4100E086UL) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS12       (*(RoReg8 *)0x4100E087UL) /**< \brief (EVSYS) Channel 12 Status */
+#define REG_EVSYS_CHANNEL13        (*(RwReg  *)0x4100E088UL) /**< \brief (EVSYS) Channel 13 Control */
+#define REG_EVSYS_CHINTENCLR13     (*(RwReg8 *)0x4100E08CUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET13     (*(RwReg8 *)0x4100E08DUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG13      (*(RwReg8 *)0x4100E08EUL) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS13       (*(RoReg8 *)0x4100E08FUL) /**< \brief (EVSYS) Channel 13 Status */
+#define REG_EVSYS_CHANNEL14        (*(RwReg  *)0x4100E090UL) /**< \brief (EVSYS) Channel 14 Control */
+#define REG_EVSYS_CHINTENCLR14     (*(RwReg8 *)0x4100E094UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET14     (*(RwReg8 *)0x4100E095UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG14      (*(RwReg8 *)0x4100E096UL) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS14       (*(RoReg8 *)0x4100E097UL) /**< \brief (EVSYS) Channel 14 Status */
+#define REG_EVSYS_CHANNEL15        (*(RwReg  *)0x4100E098UL) /**< \brief (EVSYS) Channel 15 Control */
+#define REG_EVSYS_CHINTENCLR15     (*(RwReg8 *)0x4100E09CUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET15     (*(RwReg8 *)0x4100E09DUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG15      (*(RwReg8 *)0x4100E09EUL) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS15       (*(RoReg8 *)0x4100E09FUL) /**< \brief (EVSYS) Channel 15 Status */
+#define REG_EVSYS_CHANNEL16        (*(RwReg  *)0x4100E0A0UL) /**< \brief (EVSYS) Channel 16 Control */
+#define REG_EVSYS_CHINTENCLR16     (*(RwReg8 *)0x4100E0A4UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET16     (*(RwReg8 *)0x4100E0A5UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG16      (*(RwReg8 *)0x4100E0A6UL) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS16       (*(RoReg8 *)0x4100E0A7UL) /**< \brief (EVSYS) Channel 16 Status */
+#define REG_EVSYS_CHANNEL17        (*(RwReg  *)0x4100E0A8UL) /**< \brief (EVSYS) Channel 17 Control */
+#define REG_EVSYS_CHINTENCLR17     (*(RwReg8 *)0x4100E0ACUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET17     (*(RwReg8 *)0x4100E0ADUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG17      (*(RwReg8 *)0x4100E0AEUL) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS17       (*(RoReg8 *)0x4100E0AFUL) /**< \brief (EVSYS) Channel 17 Status */
+#define REG_EVSYS_CHANNEL18        (*(RwReg  *)0x4100E0B0UL) /**< \brief (EVSYS) Channel 18 Control */
+#define REG_EVSYS_CHINTENCLR18     (*(RwReg8 *)0x4100E0B4UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET18     (*(RwReg8 *)0x4100E0B5UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG18      (*(RwReg8 *)0x4100E0B6UL) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS18       (*(RoReg8 *)0x4100E0B7UL) /**< \brief (EVSYS) Channel 18 Status */
+#define REG_EVSYS_CHANNEL19        (*(RwReg  *)0x4100E0B8UL) /**< \brief (EVSYS) Channel 19 Control */
+#define REG_EVSYS_CHINTENCLR19     (*(RwReg8 *)0x4100E0BCUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET19     (*(RwReg8 *)0x4100E0BDUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG19      (*(RwReg8 *)0x4100E0BEUL) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS19       (*(RoReg8 *)0x4100E0BFUL) /**< \brief (EVSYS) Channel 19 Status */
+#define REG_EVSYS_CHANNEL20        (*(RwReg  *)0x4100E0C0UL) /**< \brief (EVSYS) Channel 20 Control */
+#define REG_EVSYS_CHINTENCLR20     (*(RwReg8 *)0x4100E0C4UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET20     (*(RwReg8 *)0x4100E0C5UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG20      (*(RwReg8 *)0x4100E0C6UL) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS20       (*(RoReg8 *)0x4100E0C7UL) /**< \brief (EVSYS) Channel 20 Status */
+#define REG_EVSYS_CHANNEL21        (*(RwReg  *)0x4100E0C8UL) /**< \brief (EVSYS) Channel 21 Control */
+#define REG_EVSYS_CHINTENCLR21     (*(RwReg8 *)0x4100E0CCUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET21     (*(RwReg8 *)0x4100E0CDUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG21      (*(RwReg8 *)0x4100E0CEUL) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS21       (*(RoReg8 *)0x4100E0CFUL) /**< \brief (EVSYS) Channel 21 Status */
+#define REG_EVSYS_CHANNEL22        (*(RwReg  *)0x4100E0D0UL) /**< \brief (EVSYS) Channel 22 Control */
+#define REG_EVSYS_CHINTENCLR22     (*(RwReg8 *)0x4100E0D4UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET22     (*(RwReg8 *)0x4100E0D5UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG22      (*(RwReg8 *)0x4100E0D6UL) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS22       (*(RoReg8 *)0x4100E0D7UL) /**< \brief (EVSYS) Channel 22 Status */
+#define REG_EVSYS_CHANNEL23        (*(RwReg  *)0x4100E0D8UL) /**< \brief (EVSYS) Channel 23 Control */
+#define REG_EVSYS_CHINTENCLR23     (*(RwReg8 *)0x4100E0DCUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET23     (*(RwReg8 *)0x4100E0DDUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG23      (*(RwReg8 *)0x4100E0DEUL) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS23       (*(RoReg8 *)0x4100E0DFUL) /**< \brief (EVSYS) Channel 23 Status */
+#define REG_EVSYS_CHANNEL24        (*(RwReg  *)0x4100E0E0UL) /**< \brief (EVSYS) Channel 24 Control */
+#define REG_EVSYS_CHINTENCLR24     (*(RwReg8 *)0x4100E0E4UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET24     (*(RwReg8 *)0x4100E0E5UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG24      (*(RwReg8 *)0x4100E0E6UL) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS24       (*(RoReg8 *)0x4100E0E7UL) /**< \brief (EVSYS) Channel 24 Status */
+#define REG_EVSYS_CHANNEL25        (*(RwReg  *)0x4100E0E8UL) /**< \brief (EVSYS) Channel 25 Control */
+#define REG_EVSYS_CHINTENCLR25     (*(RwReg8 *)0x4100E0ECUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET25     (*(RwReg8 *)0x4100E0EDUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG25      (*(RwReg8 *)0x4100E0EEUL) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS25       (*(RoReg8 *)0x4100E0EFUL) /**< \brief (EVSYS) Channel 25 Status */
+#define REG_EVSYS_CHANNEL26        (*(RwReg  *)0x4100E0F0UL) /**< \brief (EVSYS) Channel 26 Control */
+#define REG_EVSYS_CHINTENCLR26     (*(RwReg8 *)0x4100E0F4UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET26     (*(RwReg8 *)0x4100E0F5UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG26      (*(RwReg8 *)0x4100E0F6UL) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS26       (*(RoReg8 *)0x4100E0F7UL) /**< \brief (EVSYS) Channel 26 Status */
+#define REG_EVSYS_CHANNEL27        (*(RwReg  *)0x4100E0F8UL) /**< \brief (EVSYS) Channel 27 Control */
+#define REG_EVSYS_CHINTENCLR27     (*(RwReg8 *)0x4100E0FCUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET27     (*(RwReg8 *)0x4100E0FDUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG27      (*(RwReg8 *)0x4100E0FEUL) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS27       (*(RoReg8 *)0x4100E0FFUL) /**< \brief (EVSYS) Channel 27 Status */
+#define REG_EVSYS_CHANNEL28        (*(RwReg  *)0x4100E100UL) /**< \brief (EVSYS) Channel 28 Control */
+#define REG_EVSYS_CHINTENCLR28     (*(RwReg8 *)0x4100E104UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET28     (*(RwReg8 *)0x4100E105UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG28      (*(RwReg8 *)0x4100E106UL) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS28       (*(RoReg8 *)0x4100E107UL) /**< \brief (EVSYS) Channel 28 Status */
+#define REG_EVSYS_CHANNEL29        (*(RwReg  *)0x4100E108UL) /**< \brief (EVSYS) Channel 29 Control */
+#define REG_EVSYS_CHINTENCLR29     (*(RwReg8 *)0x4100E10CUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET29     (*(RwReg8 *)0x4100E10DUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG29      (*(RwReg8 *)0x4100E10EUL) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS29       (*(RoReg8 *)0x4100E10FUL) /**< \brief (EVSYS) Channel 29 Status */
+#define REG_EVSYS_CHANNEL30        (*(RwReg  *)0x4100E110UL) /**< \brief (EVSYS) Channel 30 Control */
+#define REG_EVSYS_CHINTENCLR30     (*(RwReg8 *)0x4100E114UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET30     (*(RwReg8 *)0x4100E115UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG30      (*(RwReg8 *)0x4100E116UL) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS30       (*(RoReg8 *)0x4100E117UL) /**< \brief (EVSYS) Channel 30 Status */
+#define REG_EVSYS_CHANNEL31        (*(RwReg  *)0x4100E118UL) /**< \brief (EVSYS) Channel 31 Control */
+#define REG_EVSYS_CHINTENCLR31     (*(RwReg8 *)0x4100E11CUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
+#define REG_EVSYS_CHINTENSET31     (*(RwReg8 *)0x4100E11DUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
+#define REG_EVSYS_CHINTFLAG31      (*(RwReg8 *)0x4100E11EUL) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
+#define REG_EVSYS_CHSTATUS31       (*(RoReg8 *)0x4100E11FUL) /**< \brief (EVSYS) Channel 31 Status */
+#define REG_EVSYS_USER0            (*(RwReg  *)0x4100E120UL) /**< \brief (EVSYS) User Multiplexer 0 */
+#define REG_EVSYS_USER1            (*(RwReg  *)0x4100E124UL) /**< \brief (EVSYS) User Multiplexer 1 */
+#define REG_EVSYS_USER2            (*(RwReg  *)0x4100E128UL) /**< \brief (EVSYS) User Multiplexer 2 */
+#define REG_EVSYS_USER3            (*(RwReg  *)0x4100E12CUL) /**< \brief (EVSYS) User Multiplexer 3 */
+#define REG_EVSYS_USER4            (*(RwReg  *)0x4100E130UL) /**< \brief (EVSYS) User Multiplexer 4 */
+#define REG_EVSYS_USER5            (*(RwReg  *)0x4100E134UL) /**< \brief (EVSYS) User Multiplexer 5 */
+#define REG_EVSYS_USER6            (*(RwReg  *)0x4100E138UL) /**< \brief (EVSYS) User Multiplexer 6 */
+#define REG_EVSYS_USER7            (*(RwReg  *)0x4100E13CUL) /**< \brief (EVSYS) User Multiplexer 7 */
+#define REG_EVSYS_USER8            (*(RwReg  *)0x4100E140UL) /**< \brief (EVSYS) User Multiplexer 8 */
+#define REG_EVSYS_USER9            (*(RwReg  *)0x4100E144UL) /**< \brief (EVSYS) User Multiplexer 9 */
+#define REG_EVSYS_USER10           (*(RwReg  *)0x4100E148UL) /**< \brief (EVSYS) User Multiplexer 10 */
+#define REG_EVSYS_USER11           (*(RwReg  *)0x4100E14CUL) /**< \brief (EVSYS) User Multiplexer 11 */
+#define REG_EVSYS_USER12           (*(RwReg  *)0x4100E150UL) /**< \brief (EVSYS) User Multiplexer 12 */
+#define REG_EVSYS_USER13           (*(RwReg  *)0x4100E154UL) /**< \brief (EVSYS) User Multiplexer 13 */
+#define REG_EVSYS_USER14           (*(RwReg  *)0x4100E158UL) /**< \brief (EVSYS) User Multiplexer 14 */
+#define REG_EVSYS_USER15           (*(RwReg  *)0x4100E15CUL) /**< \brief (EVSYS) User Multiplexer 15 */
+#define REG_EVSYS_USER16           (*(RwReg  *)0x4100E160UL) /**< \brief (EVSYS) User Multiplexer 16 */
+#define REG_EVSYS_USER17           (*(RwReg  *)0x4100E164UL) /**< \brief (EVSYS) User Multiplexer 17 */
+#define REG_EVSYS_USER18           (*(RwReg  *)0x4100E168UL) /**< \brief (EVSYS) User Multiplexer 18 */
+#define REG_EVSYS_USER19           (*(RwReg  *)0x4100E16CUL) /**< \brief (EVSYS) User Multiplexer 19 */
+#define REG_EVSYS_USER20           (*(RwReg  *)0x4100E170UL) /**< \brief (EVSYS) User Multiplexer 20 */
+#define REG_EVSYS_USER21           (*(RwReg  *)0x4100E174UL) /**< \brief (EVSYS) User Multiplexer 21 */
+#define REG_EVSYS_USER22           (*(RwReg  *)0x4100E178UL) /**< \brief (EVSYS) User Multiplexer 22 */
+#define REG_EVSYS_USER23           (*(RwReg  *)0x4100E17CUL) /**< \brief (EVSYS) User Multiplexer 23 */
+#define REG_EVSYS_USER24           (*(RwReg  *)0x4100E180UL) /**< \brief (EVSYS) User Multiplexer 24 */
+#define REG_EVSYS_USER25           (*(RwReg  *)0x4100E184UL) /**< \brief (EVSYS) User Multiplexer 25 */
+#define REG_EVSYS_USER26           (*(RwReg  *)0x4100E188UL) /**< \brief (EVSYS) User Multiplexer 26 */
+#define REG_EVSYS_USER27           (*(RwReg  *)0x4100E18CUL) /**< \brief (EVSYS) User Multiplexer 27 */
+#define REG_EVSYS_USER28           (*(RwReg  *)0x4100E190UL) /**< \brief (EVSYS) User Multiplexer 28 */
+#define REG_EVSYS_USER29           (*(RwReg  *)0x4100E194UL) /**< \brief (EVSYS) User Multiplexer 29 */
+#define REG_EVSYS_USER30           (*(RwReg  *)0x4100E198UL) /**< \brief (EVSYS) User Multiplexer 30 */
+#define REG_EVSYS_USER31           (*(RwReg  *)0x4100E19CUL) /**< \brief (EVSYS) User Multiplexer 31 */
+#define REG_EVSYS_USER32           (*(RwReg  *)0x4100E1A0UL) /**< \brief (EVSYS) User Multiplexer 32 */
+#define REG_EVSYS_USER33           (*(RwReg  *)0x4100E1A4UL) /**< \brief (EVSYS) User Multiplexer 33 */
+#define REG_EVSYS_USER34           (*(RwReg  *)0x4100E1A8UL) /**< \brief (EVSYS) User Multiplexer 34 */
+#define REG_EVSYS_USER35           (*(RwReg  *)0x4100E1ACUL) /**< \brief (EVSYS) User Multiplexer 35 */
+#define REG_EVSYS_USER36           (*(RwReg  *)0x4100E1B0UL) /**< \brief (EVSYS) User Multiplexer 36 */
+#define REG_EVSYS_USER37           (*(RwReg  *)0x4100E1B4UL) /**< \brief (EVSYS) User Multiplexer 37 */
+#define REG_EVSYS_USER38           (*(RwReg  *)0x4100E1B8UL) /**< \brief (EVSYS) User Multiplexer 38 */
+#define REG_EVSYS_USER39           (*(RwReg  *)0x4100E1BCUL) /**< \brief (EVSYS) User Multiplexer 39 */
+#define REG_EVSYS_USER40           (*(RwReg  *)0x4100E1C0UL) /**< \brief (EVSYS) User Multiplexer 40 */
+#define REG_EVSYS_USER41           (*(RwReg  *)0x4100E1C4UL) /**< \brief (EVSYS) User Multiplexer 41 */
+#define REG_EVSYS_USER42           (*(RwReg  *)0x4100E1C8UL) /**< \brief (EVSYS) User Multiplexer 42 */
+#define REG_EVSYS_USER43           (*(RwReg  *)0x4100E1CCUL) /**< \brief (EVSYS) User Multiplexer 43 */
+#define REG_EVSYS_USER44           (*(RwReg  *)0x4100E1D0UL) /**< \brief (EVSYS) User Multiplexer 44 */
+#define REG_EVSYS_USER45           (*(RwReg  *)0x4100E1D4UL) /**< \brief (EVSYS) User Multiplexer 45 */
+#define REG_EVSYS_USER46           (*(RwReg  *)0x4100E1D8UL) /**< \brief (EVSYS) User Multiplexer 46 */
+#define REG_EVSYS_USER47           (*(RwReg  *)0x4100E1DCUL) /**< \brief (EVSYS) User Multiplexer 47 */
+#define REG_EVSYS_USER48           (*(RwReg  *)0x4100E1E0UL) /**< \brief (EVSYS) User Multiplexer 48 */
+#define REG_EVSYS_USER49           (*(RwReg  *)0x4100E1E4UL) /**< \brief (EVSYS) User Multiplexer 49 */
+#define REG_EVSYS_USER50           (*(RwReg  *)0x4100E1E8UL) /**< \brief (EVSYS) User Multiplexer 50 */
+#define REG_EVSYS_USER51           (*(RwReg  *)0x4100E1ECUL) /**< \brief (EVSYS) User Multiplexer 51 */
+#define REG_EVSYS_USER52           (*(RwReg  *)0x4100E1F0UL) /**< \brief (EVSYS) User Multiplexer 52 */
+#define REG_EVSYS_USER53           (*(RwReg  *)0x4100E1F4UL) /**< \brief (EVSYS) User Multiplexer 53 */
+#define REG_EVSYS_USER54           (*(RwReg  *)0x4100E1F8UL) /**< \brief (EVSYS) User Multiplexer 54 */
+#define REG_EVSYS_USER55           (*(RwReg  *)0x4100E1FCUL) /**< \brief (EVSYS) User Multiplexer 55 */
+#define REG_EVSYS_USER56           (*(RwReg  *)0x4100E200UL) /**< \brief (EVSYS) User Multiplexer 56 */
+#define REG_EVSYS_USER57           (*(RwReg  *)0x4100E204UL) /**< \brief (EVSYS) User Multiplexer 57 */
+#define REG_EVSYS_USER58           (*(RwReg  *)0x4100E208UL) /**< \brief (EVSYS) User Multiplexer 58 */
+#define REG_EVSYS_USER59           (*(RwReg  *)0x4100E20CUL) /**< \brief (EVSYS) User Multiplexer 59 */
+#define REG_EVSYS_USER60           (*(RwReg  *)0x4100E210UL) /**< \brief (EVSYS) User Multiplexer 60 */
+#define REG_EVSYS_USER61           (*(RwReg  *)0x4100E214UL) /**< \brief (EVSYS) User Multiplexer 61 */
+#define REG_EVSYS_USER62           (*(RwReg  *)0x4100E218UL) /**< \brief (EVSYS) User Multiplexer 62 */
+#define REG_EVSYS_USER63           (*(RwReg  *)0x4100E21CUL) /**< \brief (EVSYS) User Multiplexer 63 */
+#define REG_EVSYS_USER64           (*(RwReg  *)0x4100E220UL) /**< \brief (EVSYS) User Multiplexer 64 */
+#define REG_EVSYS_USER65           (*(RwReg  *)0x4100E224UL) /**< \brief (EVSYS) User Multiplexer 65 */
+#define REG_EVSYS_USER66           (*(RwReg  *)0x4100E228UL) /**< \brief (EVSYS) User Multiplexer 66 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_ASYNCHRONOUS_CHANNELS 0xFFFFF000 // Mask of Only Asynchronous Channels
+#define EVSYS_CHANNELS              32       // Total Number of Channels
+#define EVSYS_CHANNELS_BITS         5        // Number of bits to select Channel
+#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
+#define EVSYS_GCLK_ID_0             11
+#define EVSYS_GCLK_ID_1             12
+#define EVSYS_GCLK_ID_2             13
+#define EVSYS_GCLK_ID_3             14
+#define EVSYS_GCLK_ID_4             15
+#define EVSYS_GCLK_ID_5             16
+#define EVSYS_GCLK_ID_6             17
+#define EVSYS_GCLK_ID_7             18
+#define EVSYS_GCLK_ID_8             19
+#define EVSYS_GCLK_ID_9             20
+#define EVSYS_GCLK_ID_10            21
+#define EVSYS_GCLK_ID_11            22
+#define EVSYS_GCLK_ID_LSB           11
+#define EVSYS_GCLK_ID_MSB           22
+#define EVSYS_GCLK_ID_SIZE          12
+#define EVSYS_GENERATORS            119      // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
+#define EVSYS_SYNCH_NUM             12       // Number of Synchronous Channels
+#define EVSYS_SYNCH_NUM_BITS        4        // Number of bits to select Synchronous Channels
+#define EVSYS_USERS                 67       // Total Number of Event Users
+#define EVSYS_USERS_BITS            7        // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_0 1
+#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_1 2
+#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3
+#define EVSYS_ID_GEN_RTC_PER_0      4
+#define EVSYS_ID_GEN_RTC_PER_1      5
+#define EVSYS_ID_GEN_RTC_PER_2      6
+#define EVSYS_ID_GEN_RTC_PER_3      7
+#define EVSYS_ID_GEN_RTC_PER_4      8
+#define EVSYS_ID_GEN_RTC_PER_5      9
+#define EVSYS_ID_GEN_RTC_PER_6      10
+#define EVSYS_ID_GEN_RTC_PER_7      11
+#define EVSYS_ID_GEN_RTC_CMP_0      12
+#define EVSYS_ID_GEN_RTC_CMP_1      13
+#define EVSYS_ID_GEN_RTC_CMP_2      14
+#define EVSYS_ID_GEN_RTC_CMP_3      15
+#define EVSYS_ID_GEN_RTC_TAMPER     16
+#define EVSYS_ID_GEN_RTC_OVF        17
+#define EVSYS_ID_GEN_EIC_EXTINT_0   18
+#define EVSYS_ID_GEN_EIC_EXTINT_1   19
+#define EVSYS_ID_GEN_EIC_EXTINT_2   20
+#define EVSYS_ID_GEN_EIC_EXTINT_3   21
+#define EVSYS_ID_GEN_EIC_EXTINT_4   22
+#define EVSYS_ID_GEN_EIC_EXTINT_5   23
+#define EVSYS_ID_GEN_EIC_EXTINT_6   24
+#define EVSYS_ID_GEN_EIC_EXTINT_7   25
+#define EVSYS_ID_GEN_EIC_EXTINT_8   26
+#define EVSYS_ID_GEN_EIC_EXTINT_9   27
+#define EVSYS_ID_GEN_EIC_EXTINT_10  28
+#define EVSYS_ID_GEN_EIC_EXTINT_11  29
+#define EVSYS_ID_GEN_EIC_EXTINT_12  30
+#define EVSYS_ID_GEN_EIC_EXTINT_13  31
+#define EVSYS_ID_GEN_EIC_EXTINT_14  32
+#define EVSYS_ID_GEN_EIC_EXTINT_15  33
+#define EVSYS_ID_GEN_DMAC_CH_0      34
+#define EVSYS_ID_GEN_DMAC_CH_1      35
+#define EVSYS_ID_GEN_DMAC_CH_2      36
+#define EVSYS_ID_GEN_DMAC_CH_3      37
+#define EVSYS_ID_GEN_PAC_ACCERR     38
+#define EVSYS_ID_GEN_TCC0_OVF       41
+#define EVSYS_ID_GEN_TCC0_TRG       42
+#define EVSYS_ID_GEN_TCC0_CNT       43
+#define EVSYS_ID_GEN_TCC0_MC_0      44
+#define EVSYS_ID_GEN_TCC0_MC_1      45
+#define EVSYS_ID_GEN_TCC0_MC_2      46
+#define EVSYS_ID_GEN_TCC0_MC_3      47
+#define EVSYS_ID_GEN_TCC0_MC_4      48
+#define EVSYS_ID_GEN_TCC0_MC_5      49
+#define EVSYS_ID_GEN_TCC1_OVF       50
+#define EVSYS_ID_GEN_TCC1_TRG       51
+#define EVSYS_ID_GEN_TCC1_CNT       52
+#define EVSYS_ID_GEN_TCC1_MC_0      53
+#define EVSYS_ID_GEN_TCC1_MC_1      54
+#define EVSYS_ID_GEN_TCC1_MC_2      55
+#define EVSYS_ID_GEN_TCC1_MC_3      56
+#define EVSYS_ID_GEN_TCC2_OVF       57
+#define EVSYS_ID_GEN_TCC2_TRG       58
+#define EVSYS_ID_GEN_TCC2_CNT       59
+#define EVSYS_ID_GEN_TCC2_MC_0      60
+#define EVSYS_ID_GEN_TCC2_MC_1      61
+#define EVSYS_ID_GEN_TCC2_MC_2      62
+#define EVSYS_ID_GEN_TCC3_OVF       63
+#define EVSYS_ID_GEN_TCC3_TRG       64
+#define EVSYS_ID_GEN_TCC3_CNT       65
+#define EVSYS_ID_GEN_TCC3_MC_0      66
+#define EVSYS_ID_GEN_TCC3_MC_1      67
+#define EVSYS_ID_GEN_TCC4_OVF       68
+#define EVSYS_ID_GEN_TCC4_TRG       69
+#define EVSYS_ID_GEN_TCC4_CNT       70
+#define EVSYS_ID_GEN_TCC4_MC_0      71
+#define EVSYS_ID_GEN_TCC4_MC_1      72
+#define EVSYS_ID_GEN_TC0_OVF        73
+#define EVSYS_ID_GEN_TC0_MC_0       74
+#define EVSYS_ID_GEN_TC0_MC_1       75
+#define EVSYS_ID_GEN_TC1_OVF        76
+#define EVSYS_ID_GEN_TC1_MC_0       77
+#define EVSYS_ID_GEN_TC1_MC_1       78
+#define EVSYS_ID_GEN_TC2_OVF        79
+#define EVSYS_ID_GEN_TC2_MC_0       80
+#define EVSYS_ID_GEN_TC2_MC_1       81
+#define EVSYS_ID_GEN_TC3_OVF        82
+#define EVSYS_ID_GEN_TC3_MC_0       83
+#define EVSYS_ID_GEN_TC3_MC_1       84
+#define EVSYS_ID_GEN_TC4_OVF        85
+#define EVSYS_ID_GEN_TC4_MC_0       86
+#define EVSYS_ID_GEN_TC4_MC_1       87
+#define EVSYS_ID_GEN_TC5_OVF        88
+#define EVSYS_ID_GEN_TC5_MC_0       89
+#define EVSYS_ID_GEN_TC5_MC_1       90
+#define EVSYS_ID_GEN_TC6_OVF        91
+#define EVSYS_ID_GEN_TC6_MC_0       92
+#define EVSYS_ID_GEN_TC6_MC_1       93
+#define EVSYS_ID_GEN_TC7_OVF        94
+#define EVSYS_ID_GEN_TC7_MC_0       95
+#define EVSYS_ID_GEN_TC7_MC_1       96
+#define EVSYS_ID_GEN_PDEC_OVF       97
+#define EVSYS_ID_GEN_PDEC_ERR       98
+#define EVSYS_ID_GEN_PDEC_DIR       99
+#define EVSYS_ID_GEN_PDEC_VLC       100
+#define EVSYS_ID_GEN_PDEC_MC_0      101
+#define EVSYS_ID_GEN_PDEC_MC_1      102
+#define EVSYS_ID_GEN_ADC0_RESRDY    103
+#define EVSYS_ID_GEN_ADC0_WINMON    104
+#define EVSYS_ID_GEN_ADC1_RESRDY    105
+#define EVSYS_ID_GEN_ADC1_WINMON    106
+#define EVSYS_ID_GEN_AC_COMP_0      107
+#define EVSYS_ID_GEN_AC_COMP_1      108
+#define EVSYS_ID_GEN_AC_WIN_0       109
+#define EVSYS_ID_GEN_DAC_EMPTY_0    110
+#define EVSYS_ID_GEN_DAC_EMPTY_1    111
+#define EVSYS_ID_GEN_DAC_RESRDY_0   112
+#define EVSYS_ID_GEN_DAC_RESRDY_1   113
+#define EVSYS_ID_GEN_GMAC_TSU_CMP   114
+#define EVSYS_ID_GEN_TRNG_READY     115
+#define EVSYS_ID_GEN_CCL_LUTOUT_0   116
+#define EVSYS_ID_GEN_CCL_LUTOUT_1   117
+#define EVSYS_ID_GEN_CCL_LUTOUT_2   118
+#define EVSYS_ID_GEN_CCL_LUTOUT_3   119
+
+// USERS
+#define EVSYS_ID_USER_RTC_TAMPER    0
+#define EVSYS_ID_USER_PORT_EV_0     1
+#define EVSYS_ID_USER_PORT_EV_1     2
+#define EVSYS_ID_USER_PORT_EV_2     3
+#define EVSYS_ID_USER_PORT_EV_3     4
+#define EVSYS_ID_USER_DMAC_CH_0     5
+#define EVSYS_ID_USER_DMAC_CH_1     6
+#define EVSYS_ID_USER_DMAC_CH_2     7
+#define EVSYS_ID_USER_DMAC_CH_3     8
+#define EVSYS_ID_USER_DMAC_CH_4     9
+#define EVSYS_ID_USER_DMAC_CH_5     10
+#define EVSYS_ID_USER_DMAC_CH_6     11
+#define EVSYS_ID_USER_DMAC_CH_7     12
+#define EVSYS_ID_USER_CM4_TRACE_START 14
+#define EVSYS_ID_USER_CM4_TRACE_STOP 15
+#define EVSYS_ID_USER_CM4_TRACE_TRIG 16
+#define EVSYS_ID_USER_TCC0_EV_0     17
+#define EVSYS_ID_USER_TCC0_EV_1     18
+#define EVSYS_ID_USER_TCC0_MC_0     19
+#define EVSYS_ID_USER_TCC0_MC_1     20
+#define EVSYS_ID_USER_TCC0_MC_2     21
+#define EVSYS_ID_USER_TCC0_MC_3     22
+#define EVSYS_ID_USER_TCC0_MC_4     23
+#define EVSYS_ID_USER_TCC0_MC_5     24
+#define EVSYS_ID_USER_TCC1_EV_0     25
+#define EVSYS_ID_USER_TCC1_EV_1     26
+#define EVSYS_ID_USER_TCC1_MC_0     27
+#define EVSYS_ID_USER_TCC1_MC_1     28
+#define EVSYS_ID_USER_TCC1_MC_2     29
+#define EVSYS_ID_USER_TCC1_MC_3     30
+#define EVSYS_ID_USER_TCC2_EV_0     31
+#define EVSYS_ID_USER_TCC2_EV_1     32
+#define EVSYS_ID_USER_TCC2_MC_0     33
+#define EVSYS_ID_USER_TCC2_MC_1     34
+#define EVSYS_ID_USER_TCC2_MC_2     35
+#define EVSYS_ID_USER_TCC3_EV_0     36
+#define EVSYS_ID_USER_TCC3_EV_1     37
+#define EVSYS_ID_USER_TCC3_MC_0     38
+#define EVSYS_ID_USER_TCC3_MC_1     39
+#define EVSYS_ID_USER_TCC4_EV_0     40
+#define EVSYS_ID_USER_TCC4_EV_1     41
+#define EVSYS_ID_USER_TCC4_MC_0     42
+#define EVSYS_ID_USER_TCC4_MC_1     43
+#define EVSYS_ID_USER_TC0_EVU       44
+#define EVSYS_ID_USER_TC1_EVU       45
+#define EVSYS_ID_USER_TC2_EVU       46
+#define EVSYS_ID_USER_TC3_EVU       47
+#define EVSYS_ID_USER_TC4_EVU       48
+#define EVSYS_ID_USER_TC5_EVU       49
+#define EVSYS_ID_USER_TC6_EVU       50
+#define EVSYS_ID_USER_TC7_EVU       51
+#define EVSYS_ID_USER_PDEC_EVU_0    52
+#define EVSYS_ID_USER_PDEC_EVU_1    53
+#define EVSYS_ID_USER_PDEC_EVU_2    54
+#define EVSYS_ID_USER_ADC0_START    55
+#define EVSYS_ID_USER_ADC0_SYNC     56
+#define EVSYS_ID_USER_ADC1_START    57
+#define EVSYS_ID_USER_ADC1_SYNC     58
+#define EVSYS_ID_USER_AC_SOC_0      59
+#define EVSYS_ID_USER_AC_SOC_1      60
+#define EVSYS_ID_USER_DAC_START_0   61
+#define EVSYS_ID_USER_DAC_START_1   62
+#define EVSYS_ID_USER_CCL_LUTIN_0   63
+#define EVSYS_ID_USER_CCL_LUTIN_1   64
+#define EVSYS_ID_USER_CCL_LUTIN_2   65
+#define EVSYS_ID_USER_CCL_LUTIN_3   66
+
+#endif /* _SAME53_EVSYS_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/freqm.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/freqm.h
new file mode 100644
index 000000000..bd8684112
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/freqm.h	
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for FREQM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_FREQM_INSTANCE_
+#define _SAME53_FREQM_INSTANCE_
+
+/* ========== Register definition for FREQM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_FREQM_CTRLA            (0x40002C00) /**< \brief (FREQM) Control A Register */
+#define REG_FREQM_CTRLB            (0x40002C01) /**< \brief (FREQM) Control B Register */
+#define REG_FREQM_CFGA             (0x40002C02) /**< \brief (FREQM) Config A register */
+#define REG_FREQM_INTENCLR         (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */
+#define REG_FREQM_INTENSET         (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */
+#define REG_FREQM_INTFLAG          (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */
+#define REG_FREQM_STATUS           (0x40002C0B) /**< \brief (FREQM) Status Register */
+#define REG_FREQM_SYNCBUSY         (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */
+#define REG_FREQM_VALUE            (0x40002C10) /**< \brief (FREQM) Count Value Register */
+#else
+#define REG_FREQM_CTRLA            (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */
+#define REG_FREQM_CTRLB            (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */
+#define REG_FREQM_CFGA             (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */
+#define REG_FREQM_INTENCLR         (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */
+#define REG_FREQM_INTENSET         (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */
+#define REG_FREQM_INTFLAG          (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */
+#define REG_FREQM_STATUS           (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */
+#define REG_FREQM_SYNCBUSY         (*(RoReg  *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */
+#define REG_FREQM_VALUE            (*(RoReg  *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for FREQM peripheral ========== */
+#define FREQM_GCLK_ID_MSR           5        // Index of measure generic clock
+
+#endif /* _SAME53_FREQM_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/gclk.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/gclk.h
new file mode 100644
index 000000000..3f0f7eaa6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/gclk.h	
@@ -0,0 +1,191 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_GCLK_INSTANCE_
+#define _SAME53_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRLA             (0x40001C00) /**< \brief (GCLK) Control */
+#define REG_GCLK_SYNCBUSY          (0x40001C04) /**< \brief (GCLK) Synchronization Busy */
+#define REG_GCLK_GENCTRL0          (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */
+#define REG_GCLK_GENCTRL1          (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */
+#define REG_GCLK_GENCTRL2          (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */
+#define REG_GCLK_GENCTRL3          (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */
+#define REG_GCLK_GENCTRL4          (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */
+#define REG_GCLK_GENCTRL5          (0x40001C34) /**< \brief (GCLK) Generic Clock Generator Control 5 */
+#define REG_GCLK_GENCTRL6          (0x40001C38) /**< \brief (GCLK) Generic Clock Generator Control 6 */
+#define REG_GCLK_GENCTRL7          (0x40001C3C) /**< \brief (GCLK) Generic Clock Generator Control 7 */
+#define REG_GCLK_GENCTRL8          (0x40001C40) /**< \brief (GCLK) Generic Clock Generator Control 8 */
+#define REG_GCLK_GENCTRL9          (0x40001C44) /**< \brief (GCLK) Generic Clock Generator Control 9 */
+#define REG_GCLK_GENCTRL10         (0x40001C48) /**< \brief (GCLK) Generic Clock Generator Control 10 */
+#define REG_GCLK_GENCTRL11         (0x40001C4C) /**< \brief (GCLK) Generic Clock Generator Control 11 */
+#define REG_GCLK_PCHCTRL0          (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */
+#define REG_GCLK_PCHCTRL1          (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */
+#define REG_GCLK_PCHCTRL2          (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */
+#define REG_GCLK_PCHCTRL3          (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */
+#define REG_GCLK_PCHCTRL4          (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */
+#define REG_GCLK_PCHCTRL5          (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */
+#define REG_GCLK_PCHCTRL6          (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */
+#define REG_GCLK_PCHCTRL7          (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */
+#define REG_GCLK_PCHCTRL8          (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */
+#define REG_GCLK_PCHCTRL9          (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */
+#define REG_GCLK_PCHCTRL10         (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */
+#define REG_GCLK_PCHCTRL11         (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */
+#define REG_GCLK_PCHCTRL12         (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */
+#define REG_GCLK_PCHCTRL13         (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */
+#define REG_GCLK_PCHCTRL14         (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */
+#define REG_GCLK_PCHCTRL15         (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */
+#define REG_GCLK_PCHCTRL16         (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */
+#define REG_GCLK_PCHCTRL17         (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */
+#define REG_GCLK_PCHCTRL18         (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */
+#define REG_GCLK_PCHCTRL19         (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */
+#define REG_GCLK_PCHCTRL20         (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */
+#define REG_GCLK_PCHCTRL21         (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */
+#define REG_GCLK_PCHCTRL22         (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */
+#define REG_GCLK_PCHCTRL23         (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */
+#define REG_GCLK_PCHCTRL24         (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */
+#define REG_GCLK_PCHCTRL25         (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */
+#define REG_GCLK_PCHCTRL26         (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */
+#define REG_GCLK_PCHCTRL27         (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */
+#define REG_GCLK_PCHCTRL28         (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */
+#define REG_GCLK_PCHCTRL29         (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */
+#define REG_GCLK_PCHCTRL30         (0x40001CF8) /**< \brief (GCLK) Peripheral Clock Control 30 */
+#define REG_GCLK_PCHCTRL31         (0x40001CFC) /**< \brief (GCLK) Peripheral Clock Control 31 */
+#define REG_GCLK_PCHCTRL32         (0x40001D00) /**< \brief (GCLK) Peripheral Clock Control 32 */
+#define REG_GCLK_PCHCTRL33         (0x40001D04) /**< \brief (GCLK) Peripheral Clock Control 33 */
+#define REG_GCLK_PCHCTRL34         (0x40001D08) /**< \brief (GCLK) Peripheral Clock Control 34 */
+#define REG_GCLK_PCHCTRL35         (0x40001D0C) /**< \brief (GCLK) Peripheral Clock Control 35 */
+#define REG_GCLK_PCHCTRL36         (0x40001D10) /**< \brief (GCLK) Peripheral Clock Control 36 */
+#define REG_GCLK_PCHCTRL37         (0x40001D14) /**< \brief (GCLK) Peripheral Clock Control 37 */
+#define REG_GCLK_PCHCTRL38         (0x40001D18) /**< \brief (GCLK) Peripheral Clock Control 38 */
+#define REG_GCLK_PCHCTRL39         (0x40001D1C) /**< \brief (GCLK) Peripheral Clock Control 39 */
+#define REG_GCLK_PCHCTRL40         (0x40001D20) /**< \brief (GCLK) Peripheral Clock Control 40 */
+#define REG_GCLK_PCHCTRL41         (0x40001D24) /**< \brief (GCLK) Peripheral Clock Control 41 */
+#define REG_GCLK_PCHCTRL42         (0x40001D28) /**< \brief (GCLK) Peripheral Clock Control 42 */
+#define REG_GCLK_PCHCTRL43         (0x40001D2C) /**< \brief (GCLK) Peripheral Clock Control 43 */
+#define REG_GCLK_PCHCTRL44         (0x40001D30) /**< \brief (GCLK) Peripheral Clock Control 44 */
+#define REG_GCLK_PCHCTRL45         (0x40001D34) /**< \brief (GCLK) Peripheral Clock Control 45 */
+#define REG_GCLK_PCHCTRL46         (0x40001D38) /**< \brief (GCLK) Peripheral Clock Control 46 */
+#define REG_GCLK_PCHCTRL47         (0x40001D3C) /**< \brief (GCLK) Peripheral Clock Control 47 */
+#else
+#define REG_GCLK_CTRLA             (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */
+#define REG_GCLK_SYNCBUSY          (*(RoReg  *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */
+#define REG_GCLK_GENCTRL0          (*(RwReg  *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */
+#define REG_GCLK_GENCTRL1          (*(RwReg  *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */
+#define REG_GCLK_GENCTRL2          (*(RwReg  *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */
+#define REG_GCLK_GENCTRL3          (*(RwReg  *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */
+#define REG_GCLK_GENCTRL4          (*(RwReg  *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */
+#define REG_GCLK_GENCTRL5          (*(RwReg  *)0x40001C34UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */
+#define REG_GCLK_GENCTRL6          (*(RwReg  *)0x40001C38UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */
+#define REG_GCLK_GENCTRL7          (*(RwReg  *)0x40001C3CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */
+#define REG_GCLK_GENCTRL8          (*(RwReg  *)0x40001C40UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */
+#define REG_GCLK_GENCTRL9          (*(RwReg  *)0x40001C44UL) /**< \brief (GCLK) Generic Clock Generator Control 9 */
+#define REG_GCLK_GENCTRL10         (*(RwReg  *)0x40001C48UL) /**< \brief (GCLK) Generic Clock Generator Control 10 */
+#define REG_GCLK_GENCTRL11         (*(RwReg  *)0x40001C4CUL) /**< \brief (GCLK) Generic Clock Generator Control 11 */
+#define REG_GCLK_PCHCTRL0          (*(RwReg  *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */
+#define REG_GCLK_PCHCTRL1          (*(RwReg  *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */
+#define REG_GCLK_PCHCTRL2          (*(RwReg  *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */
+#define REG_GCLK_PCHCTRL3          (*(RwReg  *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */
+#define REG_GCLK_PCHCTRL4          (*(RwReg  *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */
+#define REG_GCLK_PCHCTRL5          (*(RwReg  *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */
+#define REG_GCLK_PCHCTRL6          (*(RwReg  *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */
+#define REG_GCLK_PCHCTRL7          (*(RwReg  *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */
+#define REG_GCLK_PCHCTRL8          (*(RwReg  *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */
+#define REG_GCLK_PCHCTRL9          (*(RwReg  *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */
+#define REG_GCLK_PCHCTRL10         (*(RwReg  *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */
+#define REG_GCLK_PCHCTRL11         (*(RwReg  *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */
+#define REG_GCLK_PCHCTRL12         (*(RwReg  *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */
+#define REG_GCLK_PCHCTRL13         (*(RwReg  *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */
+#define REG_GCLK_PCHCTRL14         (*(RwReg  *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */
+#define REG_GCLK_PCHCTRL15         (*(RwReg  *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */
+#define REG_GCLK_PCHCTRL16         (*(RwReg  *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */
+#define REG_GCLK_PCHCTRL17         (*(RwReg  *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */
+#define REG_GCLK_PCHCTRL18         (*(RwReg  *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */
+#define REG_GCLK_PCHCTRL19         (*(RwReg  *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */
+#define REG_GCLK_PCHCTRL20         (*(RwReg  *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */
+#define REG_GCLK_PCHCTRL21         (*(RwReg  *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */
+#define REG_GCLK_PCHCTRL22         (*(RwReg  *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */
+#define REG_GCLK_PCHCTRL23         (*(RwReg  *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */
+#define REG_GCLK_PCHCTRL24         (*(RwReg  *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */
+#define REG_GCLK_PCHCTRL25         (*(RwReg  *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */
+#define REG_GCLK_PCHCTRL26         (*(RwReg  *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */
+#define REG_GCLK_PCHCTRL27         (*(RwReg  *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */
+#define REG_GCLK_PCHCTRL28         (*(RwReg  *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */
+#define REG_GCLK_PCHCTRL29         (*(RwReg  *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */
+#define REG_GCLK_PCHCTRL30         (*(RwReg  *)0x40001CF8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */
+#define REG_GCLK_PCHCTRL31         (*(RwReg  *)0x40001CFCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */
+#define REG_GCLK_PCHCTRL32         (*(RwReg  *)0x40001D00UL) /**< \brief (GCLK) Peripheral Clock Control 32 */
+#define REG_GCLK_PCHCTRL33         (*(RwReg  *)0x40001D04UL) /**< \brief (GCLK) Peripheral Clock Control 33 */
+#define REG_GCLK_PCHCTRL34         (*(RwReg  *)0x40001D08UL) /**< \brief (GCLK) Peripheral Clock Control 34 */
+#define REG_GCLK_PCHCTRL35         (*(RwReg  *)0x40001D0CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */
+#define REG_GCLK_PCHCTRL36         (*(RwReg  *)0x40001D10UL) /**< \brief (GCLK) Peripheral Clock Control 36 */
+#define REG_GCLK_PCHCTRL37         (*(RwReg  *)0x40001D14UL) /**< \brief (GCLK) Peripheral Clock Control 37 */
+#define REG_GCLK_PCHCTRL38         (*(RwReg  *)0x40001D18UL) /**< \brief (GCLK) Peripheral Clock Control 38 */
+#define REG_GCLK_PCHCTRL39         (*(RwReg  *)0x40001D1CUL) /**< \brief (GCLK) Peripheral Clock Control 39 */
+#define REG_GCLK_PCHCTRL40         (*(RwReg  *)0x40001D20UL) /**< \brief (GCLK) Peripheral Clock Control 40 */
+#define REG_GCLK_PCHCTRL41         (*(RwReg  *)0x40001D24UL) /**< \brief (GCLK) Peripheral Clock Control 41 */
+#define REG_GCLK_PCHCTRL42         (*(RwReg  *)0x40001D28UL) /**< \brief (GCLK) Peripheral Clock Control 42 */
+#define REG_GCLK_PCHCTRL43         (*(RwReg  *)0x40001D2CUL) /**< \brief (GCLK) Peripheral Clock Control 43 */
+#define REG_GCLK_PCHCTRL44         (*(RwReg  *)0x40001D30UL) /**< \brief (GCLK) Peripheral Clock Control 44 */
+#define REG_GCLK_PCHCTRL45         (*(RwReg  *)0x40001D34UL) /**< \brief (GCLK) Peripheral Clock Control 45 */
+#define REG_GCLK_PCHCTRL46         (*(RwReg  *)0x40001D38UL) /**< \brief (GCLK) Peripheral Clock Control 46 */
+#define REG_GCLK_PCHCTRL47         (*(RwReg  *)0x40001D3CUL) /**< \brief (GCLK) Peripheral Clock Control 47 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENCTRL0_RESETVALUE    106      // Default specific reset value for generator 0
+#define GCLK_GENDIV_BITS            16      
+#define GCLK_GEN_BITS               4       
+#define GCLK_GEN_NUM                12       // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB            11       // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
+#define GCLK_IO_NUM                 8        // Number of Generic Clock I/Os
+#define GCLK_NUM                    48       // Number of Generic Clock Users
+#define GCLK_SOURCE_BITS            4       
+#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
+#define GCLK_SOURCE_XOSC0           0        // Crystal Oscillator 0
+#define GCLK_SOURCE_XOSC            0        //   Alias to GCLK_SOURCE_XOSC0
+#define GCLK_SOURCE_XOSC1           1        // Crystal Oscillator 1
+#define GCLK_SOURCE_GCLKIN          2        // Input Pin of Corresponding GCLK Generator
+#define GCLK_SOURCE_GCLKGEN1        3        // GCLK Generator 1 output
+#define GCLK_SOURCE_OSCULP32K       4        // Ultra-low-power 32kHz Oscillator
+#define GCLK_SOURCE_XOSC32K         5        // 32kHz Crystal Oscillator
+#define GCLK_SOURCE_DFLL            6        // Digital FLL
+#define GCLK_SOURCE_DFLL48M         6        //   Alias to GCLK_SOURCE_DFLL
+#define GCLK_SOURCE_OSC16M          6        //   Alias to GCLK_SOURCE_DFLL
+#define GCLK_SOURCE_OSC48M          6        //   Alias to GCLK_SOURCE_DFLL
+#define GCLK_SOURCE_DPLL0           7        // Digital PLL 0
+#define GCLK_SOURCE_FDPLL           7        //   Alias to GCLK_SOURCE_DPLL0
+#define GCLK_SOURCE_FDPLL0          7        //   Alias to GCLK_SOURCE_DPLL0
+#define GCLK_SOURCE_DPLL1           8        // Digital PLL 1
+#define GCLK_SOURCE_FDPLL1          8        //   Alias to GCLK_SOURCE_DPLL1
+#define GCLK_GEN_DIV_BITS           { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }
+
+#endif /* _SAME53_GCLK_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/gmac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/gmac.h
new file mode 100644
index 000000000..717f941ee
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/gmac.h	
@@ -0,0 +1,263 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GMAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_GMAC_INSTANCE_
+#define _SAME53_GMAC_INSTANCE_
+
+/* ========== Register definition for GMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GMAC_NCR               (0x42000800) /**< \brief (GMAC) Network Control Register */
+#define REG_GMAC_NCFGR             (0x42000804) /**< \brief (GMAC) Network Configuration Register */
+#define REG_GMAC_NSR               (0x42000808) /**< \brief (GMAC) Network Status Register */
+#define REG_GMAC_UR                (0x4200080C) /**< \brief (GMAC) User Register */
+#define REG_GMAC_DCFGR             (0x42000810) /**< \brief (GMAC) DMA Configuration Register */
+#define REG_GMAC_TSR               (0x42000814) /**< \brief (GMAC) Transmit Status Register */
+#define REG_GMAC_RBQB              (0x42000818) /**< \brief (GMAC) Receive Buffer Queue Base Address */
+#define REG_GMAC_TBQB              (0x4200081C) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
+#define REG_GMAC_RSR               (0x42000820) /**< \brief (GMAC) Receive Status Register */
+#define REG_GMAC_ISR               (0x42000824) /**< \brief (GMAC) Interrupt Status Register */
+#define REG_GMAC_IER               (0x42000828) /**< \brief (GMAC) Interrupt Enable Register */
+#define REG_GMAC_IDR               (0x4200082C) /**< \brief (GMAC) Interrupt Disable Register */
+#define REG_GMAC_IMR               (0x42000830) /**< \brief (GMAC) Interrupt Mask Register */
+#define REG_GMAC_MAN               (0x42000834) /**< \brief (GMAC) PHY Maintenance Register */
+#define REG_GMAC_RPQ               (0x42000838) /**< \brief (GMAC) Received Pause Quantum Register */
+#define REG_GMAC_TPQ               (0x4200083C) /**< \brief (GMAC) Transmit Pause Quantum Register */
+#define REG_GMAC_TPSF              (0x42000840) /**< \brief (GMAC) TX partial store and forward Register */
+#define REG_GMAC_RPSF              (0x42000844) /**< \brief (GMAC) RX partial store and forward Register */
+#define REG_GMAC_RJFML             (0x42000848) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
+#define REG_GMAC_HRB               (0x42000880) /**< \brief (GMAC) Hash Register Bottom [31:0] */
+#define REG_GMAC_HRT               (0x42000884) /**< \brief (GMAC) Hash Register Top [63:32] */
+#define REG_GMAC_SAB0              (0x42000888) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 0 */
+#define REG_GMAC_SAT0              (0x4200088C) /**< \brief (GMAC) Specific Address Top [47:32] Register 0 */
+#define REG_GMAC_SAB1              (0x42000890) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 1 */
+#define REG_GMAC_SAT1              (0x42000894) /**< \brief (GMAC) Specific Address Top [47:32] Register 1 */
+#define REG_GMAC_SAB2              (0x42000898) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 2 */
+#define REG_GMAC_SAT2              (0x4200089C) /**< \brief (GMAC) Specific Address Top [47:32] Register 2 */
+#define REG_GMAC_SAB3              (0x420008A0) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 3 */
+#define REG_GMAC_SAT3              (0x420008A4) /**< \brief (GMAC) Specific Address Top [47:32] Register 3 */
+#define REG_GMAC_TIDM0             (0x420008A8) /**< \brief (GMAC) Type ID Match Register 0 */
+#define REG_GMAC_TIDM1             (0x420008AC) /**< \brief (GMAC) Type ID Match Register 1 */
+#define REG_GMAC_TIDM2             (0x420008B0) /**< \brief (GMAC) Type ID Match Register 2 */
+#define REG_GMAC_TIDM3             (0x420008B4) /**< \brief (GMAC) Type ID Match Register 3 */
+#define REG_GMAC_WOL               (0x420008B8) /**< \brief (GMAC) Wake on LAN */
+#define REG_GMAC_IPGS              (0x420008BC) /**< \brief (GMAC) IPG Stretch Register */
+#define REG_GMAC_SVLAN             (0x420008C0) /**< \brief (GMAC) Stacked VLAN Register */
+#define REG_GMAC_TPFCP             (0x420008C4) /**< \brief (GMAC) Transmit PFC Pause Register */
+#define REG_GMAC_SAMB1             (0x420008C8) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
+#define REG_GMAC_SAMT1             (0x420008CC) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
+#define REG_GMAC_NSC               (0x420008DC) /**< \brief (GMAC) Tsu timer comparison nanoseconds Register */
+#define REG_GMAC_SCL               (0x420008E0) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_SCH               (0x420008E4) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_EFTSH             (0x420008E8) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_EFRSH             (0x420008EC) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
+#define REG_GMAC_PEFTSH            (0x420008F0) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_PEFRSH            (0x420008F4) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
+#define REG_GMAC_OTLO              (0x42000900) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
+#define REG_GMAC_OTHI              (0x42000904) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
+#define REG_GMAC_FT                (0x42000908) /**< \brief (GMAC) Frames Transmitted Register */
+#define REG_GMAC_BCFT              (0x4200090C) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
+#define REG_GMAC_MFT               (0x42000910) /**< \brief (GMAC) Multicast Frames Transmitted Register */
+#define REG_GMAC_PFT               (0x42000914) /**< \brief (GMAC) Pause Frames Transmitted Register */
+#define REG_GMAC_BFT64             (0x42000918) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT127           (0x4200091C) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT255           (0x42000920) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT511           (0x42000924) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1023          (0x42000928) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1518          (0x4200092C) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_GTBFT1518         (0x42000930) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_TUR               (0x42000934) /**< \brief (GMAC) Transmit Underruns Register */
+#define REG_GMAC_SCF               (0x42000938) /**< \brief (GMAC) Single Collision Frames Register */
+#define REG_GMAC_MCF               (0x4200093C) /**< \brief (GMAC) Multiple Collision Frames Register */
+#define REG_GMAC_EC                (0x42000940) /**< \brief (GMAC) Excessive Collisions Register */
+#define REG_GMAC_LC                (0x42000944) /**< \brief (GMAC) Late Collisions Register */
+#define REG_GMAC_DTF               (0x42000948) /**< \brief (GMAC) Deferred Transmission Frames Register */
+#define REG_GMAC_CSE               (0x4200094C) /**< \brief (GMAC) Carrier Sense Errors Register */
+#define REG_GMAC_ORLO              (0x42000950) /**< \brief (GMAC) Octets Received [31:0] Received */
+#define REG_GMAC_ORHI              (0x42000954) /**< \brief (GMAC) Octets Received [47:32] Received */
+#define REG_GMAC_FR                (0x42000958) /**< \brief (GMAC) Frames Received Register */
+#define REG_GMAC_BCFR              (0x4200095C) /**< \brief (GMAC) Broadcast Frames Received Register */
+#define REG_GMAC_MFR               (0x42000960) /**< \brief (GMAC) Multicast Frames Received Register */
+#define REG_GMAC_PFR               (0x42000964) /**< \brief (GMAC) Pause Frames Received Register */
+#define REG_GMAC_BFR64             (0x42000968) /**< \brief (GMAC) 64 Byte Frames Received Register */
+#define REG_GMAC_TBFR127           (0x4200096C) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
+#define REG_GMAC_TBFR255           (0x42000970) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
+#define REG_GMAC_TBFR511           (0x42000974) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
+#define REG_GMAC_TBFR1023          (0x42000978) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
+#define REG_GMAC_TBFR1518          (0x4200097C) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
+#define REG_GMAC_TMXBFR            (0x42000980) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
+#define REG_GMAC_UFR               (0x42000984) /**< \brief (GMAC) Undersize Frames Received Register */
+#define REG_GMAC_OFR               (0x42000988) /**< \brief (GMAC) Oversize Frames Received Register */
+#define REG_GMAC_JR                (0x4200098C) /**< \brief (GMAC) Jabbers Received Register */
+#define REG_GMAC_FCSE              (0x42000990) /**< \brief (GMAC) Frame Check Sequence Errors Register */
+#define REG_GMAC_LFFE              (0x42000994) /**< \brief (GMAC) Length Field Frame Errors Register */
+#define REG_GMAC_RSE               (0x42000998) /**< \brief (GMAC) Receive Symbol Errors Register */
+#define REG_GMAC_AE                (0x4200099C) /**< \brief (GMAC) Alignment Errors Register */
+#define REG_GMAC_RRE               (0x420009A0) /**< \brief (GMAC) Receive Resource Errors Register */
+#define REG_GMAC_ROE               (0x420009A4) /**< \brief (GMAC) Receive Overrun Register */
+#define REG_GMAC_IHCE              (0x420009A8) /**< \brief (GMAC) IP Header Checksum Errors Register */
+#define REG_GMAC_TCE               (0x420009AC) /**< \brief (GMAC) TCP Checksum Errors Register */
+#define REG_GMAC_UCE               (0x420009B0) /**< \brief (GMAC) UDP Checksum Errors Register */
+#define REG_GMAC_TISUBN            (0x420009BC) /**< \brief (GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define REG_GMAC_TSH               (0x420009C0) /**< \brief (GMAC) 1588 Timer Seconds High [15:0] Register */
+#define REG_GMAC_TSSSL             (0x420009C8) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define REG_GMAC_TSSN              (0x420009CC) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
+#define REG_GMAC_TSL               (0x420009D0) /**< \brief (GMAC) 1588 Timer Seconds [31:0] Register */
+#define REG_GMAC_TN                (0x420009D4) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
+#define REG_GMAC_TA                (0x420009D8) /**< \brief (GMAC) 1588 Timer Adjust Register */
+#define REG_GMAC_TI                (0x420009DC) /**< \brief (GMAC) 1588 Timer Increment Register */
+#define REG_GMAC_EFTSL             (0x420009E0) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_EFTN              (0x420009E4) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_EFRSL             (0x420009E8) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
+#define REG_GMAC_EFRN              (0x420009EC) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
+#define REG_GMAC_PEFTSL            (0x420009F0) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_PEFTN             (0x420009F4) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_PEFRSL            (0x420009F8) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
+#define REG_GMAC_PEFRN             (0x420009FC) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
+#define REG_GMAC_RLPITR            (0x42000A70) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_RLPITI            (0x42000A74) /**< \brief (GMAC) Receive LPI Time Register */
+#define REG_GMAC_TLPITR            (0x42000A78) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_TLPITI            (0x42000A7C) /**< \brief (GMAC) Receive LPI Time Register */
+#else
+#define REG_GMAC_NCR               (*(RwReg  *)0x42000800UL) /**< \brief (GMAC) Network Control Register */
+#define REG_GMAC_NCFGR             (*(RwReg  *)0x42000804UL) /**< \brief (GMAC) Network Configuration Register */
+#define REG_GMAC_NSR               (*(RoReg  *)0x42000808UL) /**< \brief (GMAC) Network Status Register */
+#define REG_GMAC_UR                (*(RwReg  *)0x4200080CUL) /**< \brief (GMAC) User Register */
+#define REG_GMAC_DCFGR             (*(RwReg  *)0x42000810UL) /**< \brief (GMAC) DMA Configuration Register */
+#define REG_GMAC_TSR               (*(RwReg  *)0x42000814UL) /**< \brief (GMAC) Transmit Status Register */
+#define REG_GMAC_RBQB              (*(RwReg  *)0x42000818UL) /**< \brief (GMAC) Receive Buffer Queue Base Address */
+#define REG_GMAC_TBQB              (*(RwReg  *)0x4200081CUL) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
+#define REG_GMAC_RSR               (*(RwReg  *)0x42000820UL) /**< \brief (GMAC) Receive Status Register */
+#define REG_GMAC_ISR               (*(RwReg  *)0x42000824UL) /**< \brief (GMAC) Interrupt Status Register */
+#define REG_GMAC_IER               (*(WoReg  *)0x42000828UL) /**< \brief (GMAC) Interrupt Enable Register */
+#define REG_GMAC_IDR               (*(WoReg  *)0x4200082CUL) /**< \brief (GMAC) Interrupt Disable Register */
+#define REG_GMAC_IMR               (*(RoReg  *)0x42000830UL) /**< \brief (GMAC) Interrupt Mask Register */
+#define REG_GMAC_MAN               (*(RwReg  *)0x42000834UL) /**< \brief (GMAC) PHY Maintenance Register */
+#define REG_GMAC_RPQ               (*(RoReg  *)0x42000838UL) /**< \brief (GMAC) Received Pause Quantum Register */
+#define REG_GMAC_TPQ               (*(RwReg  *)0x4200083CUL) /**< \brief (GMAC) Transmit Pause Quantum Register */
+#define REG_GMAC_TPSF              (*(RwReg  *)0x42000840UL) /**< \brief (GMAC) TX partial store and forward Register */
+#define REG_GMAC_RPSF              (*(RwReg  *)0x42000844UL) /**< \brief (GMAC) RX partial store and forward Register */
+#define REG_GMAC_RJFML             (*(RwReg  *)0x42000848UL) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */
+#define REG_GMAC_HRB               (*(RwReg  *)0x42000880UL) /**< \brief (GMAC) Hash Register Bottom [31:0] */
+#define REG_GMAC_HRT               (*(RwReg  *)0x42000884UL) /**< \brief (GMAC) Hash Register Top [63:32] */
+#define REG_GMAC_SAB0              (*(RwReg  *)0x42000888UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 0 */
+#define REG_GMAC_SAT0              (*(RwReg  *)0x4200088CUL) /**< \brief (GMAC) Specific Address Top [47:32] Register 0 */
+#define REG_GMAC_SAB1              (*(RwReg  *)0x42000890UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 1 */
+#define REG_GMAC_SAT1              (*(RwReg  *)0x42000894UL) /**< \brief (GMAC) Specific Address Top [47:32] Register 1 */
+#define REG_GMAC_SAB2              (*(RwReg  *)0x42000898UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 2 */
+#define REG_GMAC_SAT2              (*(RwReg  *)0x4200089CUL) /**< \brief (GMAC) Specific Address Top [47:32] Register 2 */
+#define REG_GMAC_SAB3              (*(RwReg  *)0x420008A0UL) /**< \brief (GMAC) Specific Address Bottom [31:0] Register 3 */
+#define REG_GMAC_SAT3              (*(RwReg  *)0x420008A4UL) /**< \brief (GMAC) Specific Address Top [47:32] Register 3 */
+#define REG_GMAC_TIDM0             (*(RwReg  *)0x420008A8UL) /**< \brief (GMAC) Type ID Match Register 0 */
+#define REG_GMAC_TIDM1             (*(RwReg  *)0x420008ACUL) /**< \brief (GMAC) Type ID Match Register 1 */
+#define REG_GMAC_TIDM2             (*(RwReg  *)0x420008B0UL) /**< \brief (GMAC) Type ID Match Register 2 */
+#define REG_GMAC_TIDM3             (*(RwReg  *)0x420008B4UL) /**< \brief (GMAC) Type ID Match Register 3 */
+#define REG_GMAC_WOL               (*(RwReg  *)0x420008B8UL) /**< \brief (GMAC) Wake on LAN */
+#define REG_GMAC_IPGS              (*(RwReg  *)0x420008BCUL) /**< \brief (GMAC) IPG Stretch Register */
+#define REG_GMAC_SVLAN             (*(RwReg  *)0x420008C0UL) /**< \brief (GMAC) Stacked VLAN Register */
+#define REG_GMAC_TPFCP             (*(RwReg  *)0x420008C4UL) /**< \brief (GMAC) Transmit PFC Pause Register */
+#define REG_GMAC_SAMB1             (*(RwReg  *)0x420008C8UL) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
+#define REG_GMAC_SAMT1             (*(RwReg  *)0x420008CCUL) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
+#define REG_GMAC_NSC               (*(RwReg  *)0x420008DCUL) /**< \brief (GMAC) Tsu timer comparison nanoseconds Register */
+#define REG_GMAC_SCL               (*(RwReg  *)0x420008E0UL) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_SCH               (*(RwReg  *)0x420008E4UL) /**< \brief (GMAC) Tsu timer second comparison Register */
+#define REG_GMAC_EFTSH             (*(RoReg  *)0x420008E8UL) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_EFRSH             (*(RoReg  *)0x420008ECUL) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */
+#define REG_GMAC_PEFTSH            (*(RoReg  *)0x420008F0UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
+#define REG_GMAC_PEFRSH            (*(RoReg  *)0x420008F4UL) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */
+#define REG_GMAC_OTLO              (*(RoReg  *)0x42000900UL) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
+#define REG_GMAC_OTHI              (*(RoReg  *)0x42000904UL) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
+#define REG_GMAC_FT                (*(RoReg  *)0x42000908UL) /**< \brief (GMAC) Frames Transmitted Register */
+#define REG_GMAC_BCFT              (*(RoReg  *)0x4200090CUL) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
+#define REG_GMAC_MFT               (*(RoReg  *)0x42000910UL) /**< \brief (GMAC) Multicast Frames Transmitted Register */
+#define REG_GMAC_PFT               (*(RoReg  *)0x42000914UL) /**< \brief (GMAC) Pause Frames Transmitted Register */
+#define REG_GMAC_BFT64             (*(RoReg  *)0x42000918UL) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT127           (*(RoReg  *)0x4200091CUL) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT255           (*(RoReg  *)0x42000920UL) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT511           (*(RoReg  *)0x42000924UL) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1023          (*(RoReg  *)0x42000928UL) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
+#define REG_GMAC_TBFT1518          (*(RoReg  *)0x4200092CUL) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_GTBFT1518         (*(RoReg  *)0x42000930UL) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
+#define REG_GMAC_TUR               (*(RoReg  *)0x42000934UL) /**< \brief (GMAC) Transmit Underruns Register */
+#define REG_GMAC_SCF               (*(RoReg  *)0x42000938UL) /**< \brief (GMAC) Single Collision Frames Register */
+#define REG_GMAC_MCF               (*(RoReg  *)0x4200093CUL) /**< \brief (GMAC) Multiple Collision Frames Register */
+#define REG_GMAC_EC                (*(RoReg  *)0x42000940UL) /**< \brief (GMAC) Excessive Collisions Register */
+#define REG_GMAC_LC                (*(RoReg  *)0x42000944UL) /**< \brief (GMAC) Late Collisions Register */
+#define REG_GMAC_DTF               (*(RoReg  *)0x42000948UL) /**< \brief (GMAC) Deferred Transmission Frames Register */
+#define REG_GMAC_CSE               (*(RoReg  *)0x4200094CUL) /**< \brief (GMAC) Carrier Sense Errors Register */
+#define REG_GMAC_ORLO              (*(RoReg  *)0x42000950UL) /**< \brief (GMAC) Octets Received [31:0] Received */
+#define REG_GMAC_ORHI              (*(RoReg  *)0x42000954UL) /**< \brief (GMAC) Octets Received [47:32] Received */
+#define REG_GMAC_FR                (*(RoReg  *)0x42000958UL) /**< \brief (GMAC) Frames Received Register */
+#define REG_GMAC_BCFR              (*(RoReg  *)0x4200095CUL) /**< \brief (GMAC) Broadcast Frames Received Register */
+#define REG_GMAC_MFR               (*(RoReg  *)0x42000960UL) /**< \brief (GMAC) Multicast Frames Received Register */
+#define REG_GMAC_PFR               (*(RoReg  *)0x42000964UL) /**< \brief (GMAC) Pause Frames Received Register */
+#define REG_GMAC_BFR64             (*(RoReg  *)0x42000968UL) /**< \brief (GMAC) 64 Byte Frames Received Register */
+#define REG_GMAC_TBFR127           (*(RoReg  *)0x4200096CUL) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
+#define REG_GMAC_TBFR255           (*(RoReg  *)0x42000970UL) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
+#define REG_GMAC_TBFR511           (*(RoReg  *)0x42000974UL) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
+#define REG_GMAC_TBFR1023          (*(RoReg  *)0x42000978UL) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
+#define REG_GMAC_TBFR1518          (*(RoReg  *)0x4200097CUL) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
+#define REG_GMAC_TMXBFR            (*(RoReg  *)0x42000980UL) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
+#define REG_GMAC_UFR               (*(RoReg  *)0x42000984UL) /**< \brief (GMAC) Undersize Frames Received Register */
+#define REG_GMAC_OFR               (*(RoReg  *)0x42000988UL) /**< \brief (GMAC) Oversize Frames Received Register */
+#define REG_GMAC_JR                (*(RoReg  *)0x4200098CUL) /**< \brief (GMAC) Jabbers Received Register */
+#define REG_GMAC_FCSE              (*(RoReg  *)0x42000990UL) /**< \brief (GMAC) Frame Check Sequence Errors Register */
+#define REG_GMAC_LFFE              (*(RoReg  *)0x42000994UL) /**< \brief (GMAC) Length Field Frame Errors Register */
+#define REG_GMAC_RSE               (*(RoReg  *)0x42000998UL) /**< \brief (GMAC) Receive Symbol Errors Register */
+#define REG_GMAC_AE                (*(RoReg  *)0x4200099CUL) /**< \brief (GMAC) Alignment Errors Register */
+#define REG_GMAC_RRE               (*(RoReg  *)0x420009A0UL) /**< \brief (GMAC) Receive Resource Errors Register */
+#define REG_GMAC_ROE               (*(RoReg  *)0x420009A4UL) /**< \brief (GMAC) Receive Overrun Register */
+#define REG_GMAC_IHCE              (*(RoReg  *)0x420009A8UL) /**< \brief (GMAC) IP Header Checksum Errors Register */
+#define REG_GMAC_TCE               (*(RoReg  *)0x420009ACUL) /**< \brief (GMAC) TCP Checksum Errors Register */
+#define REG_GMAC_UCE               (*(RoReg  *)0x420009B0UL) /**< \brief (GMAC) UDP Checksum Errors Register */
+#define REG_GMAC_TISUBN            (*(RwReg  *)0x420009BCUL) /**< \brief (GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
+#define REG_GMAC_TSH               (*(RwReg  *)0x420009C0UL) /**< \brief (GMAC) 1588 Timer Seconds High [15:0] Register */
+#define REG_GMAC_TSSSL             (*(RwReg  *)0x420009C8UL) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register */
+#define REG_GMAC_TSSN              (*(RwReg  *)0x420009CCUL) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
+#define REG_GMAC_TSL               (*(RwReg  *)0x420009D0UL) /**< \brief (GMAC) 1588 Timer Seconds [31:0] Register */
+#define REG_GMAC_TN                (*(RwReg  *)0x420009D4UL) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
+#define REG_GMAC_TA                (*(WoReg  *)0x420009D8UL) /**< \brief (GMAC) 1588 Timer Adjust Register */
+#define REG_GMAC_TI                (*(RwReg  *)0x420009DCUL) /**< \brief (GMAC) 1588 Timer Increment Register */
+#define REG_GMAC_EFTSL             (*(RoReg  *)0x420009E0UL) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_EFTN              (*(RoReg  *)0x420009E4UL) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_EFRSL             (*(RoReg  *)0x420009E8UL) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */
+#define REG_GMAC_EFRN              (*(RoReg  *)0x420009ECUL) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
+#define REG_GMAC_PEFTSL            (*(RoReg  *)0x420009F0UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
+#define REG_GMAC_PEFTN             (*(RoReg  *)0x420009F4UL) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
+#define REG_GMAC_PEFRSL            (*(RoReg  *)0x420009F8UL) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */
+#define REG_GMAC_PEFRN             (*(RoReg  *)0x420009FCUL) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
+#define REG_GMAC_RLPITR            (*(RoReg  *)0x42000A70UL) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_RLPITI            (*(RoReg  *)0x42000A74UL) /**< \brief (GMAC) Receive LPI Time Register */
+#define REG_GMAC_TLPITR            (*(RoReg  *)0x42000A78UL) /**< \brief (GMAC) Receive LPI transition Register */
+#define REG_GMAC_TLPITI            (*(RoReg  *)0x42000A7CUL) /**< \brief (GMAC) Receive LPI Time Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GMAC peripheral ========== */
+#define GMAC_CLK_AHB_ID             14       // Index of AHB clock
+
+#endif /* _SAME53_GMAC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/hmatrix.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/hmatrix.h
new file mode 100644
index 000000000..158aaee1d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/hmatrix.h	
@@ -0,0 +1,133 @@
+/**
+ * \file
+ *
+ * \brief Instance description for HMATRIX
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_HMATRIX_INSTANCE_
+#define _SAME53_HMATRIX_INSTANCE_
+
+/* ========== Register definition for HMATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HMATRIX_PRAS0          (0x4100C080) /**< \brief (HMATRIX) Priority A for Slave 0 */
+#define REG_HMATRIX_PRBS0          (0x4100C084) /**< \brief (HMATRIX) Priority B for Slave 0 */
+#define REG_HMATRIX_PRAS1          (0x4100C088) /**< \brief (HMATRIX) Priority A for Slave 1 */
+#define REG_HMATRIX_PRBS1          (0x4100C08C) /**< \brief (HMATRIX) Priority B for Slave 1 */
+#define REG_HMATRIX_PRAS2          (0x4100C090) /**< \brief (HMATRIX) Priority A for Slave 2 */
+#define REG_HMATRIX_PRBS2          (0x4100C094) /**< \brief (HMATRIX) Priority B for Slave 2 */
+#define REG_HMATRIX_PRAS3          (0x4100C098) /**< \brief (HMATRIX) Priority A for Slave 3 */
+#define REG_HMATRIX_PRBS3          (0x4100C09C) /**< \brief (HMATRIX) Priority B for Slave 3 */
+#define REG_HMATRIX_PRAS4          (0x4100C0A0) /**< \brief (HMATRIX) Priority A for Slave 4 */
+#define REG_HMATRIX_PRBS4          (0x4100C0A4) /**< \brief (HMATRIX) Priority B for Slave 4 */
+#define REG_HMATRIX_PRAS5          (0x4100C0A8) /**< \brief (HMATRIX) Priority A for Slave 5 */
+#define REG_HMATRIX_PRBS5          (0x4100C0AC) /**< \brief (HMATRIX) Priority B for Slave 5 */
+#define REG_HMATRIX_PRAS6          (0x4100C0B0) /**< \brief (HMATRIX) Priority A for Slave 6 */
+#define REG_HMATRIX_PRBS6          (0x4100C0B4) /**< \brief (HMATRIX) Priority B for Slave 6 */
+#define REG_HMATRIX_PRAS7          (0x4100C0B8) /**< \brief (HMATRIX) Priority A for Slave 7 */
+#define REG_HMATRIX_PRBS7          (0x4100C0BC) /**< \brief (HMATRIX) Priority B for Slave 7 */
+#define REG_HMATRIX_PRAS8          (0x4100C0C0) /**< \brief (HMATRIX) Priority A for Slave 8 */
+#define REG_HMATRIX_PRBS8          (0x4100C0C4) /**< \brief (HMATRIX) Priority B for Slave 8 */
+#define REG_HMATRIX_PRAS9          (0x4100C0C8) /**< \brief (HMATRIX) Priority A for Slave 9 */
+#define REG_HMATRIX_PRBS9          (0x4100C0CC) /**< \brief (HMATRIX) Priority B for Slave 9 */
+#define REG_HMATRIX_PRAS10         (0x4100C0D0) /**< \brief (HMATRIX) Priority A for Slave 10 */
+#define REG_HMATRIX_PRBS10         (0x4100C0D4) /**< \brief (HMATRIX) Priority B for Slave 10 */
+#define REG_HMATRIX_PRAS11         (0x4100C0D8) /**< \brief (HMATRIX) Priority A for Slave 11 */
+#define REG_HMATRIX_PRBS11         (0x4100C0DC) /**< \brief (HMATRIX) Priority B for Slave 11 */
+#define REG_HMATRIX_PRAS12         (0x4100C0E0) /**< \brief (HMATRIX) Priority A for Slave 12 */
+#define REG_HMATRIX_PRBS12         (0x4100C0E4) /**< \brief (HMATRIX) Priority B for Slave 12 */
+#define REG_HMATRIX_PRAS13         (0x4100C0E8) /**< \brief (HMATRIX) Priority A for Slave 13 */
+#define REG_HMATRIX_PRBS13         (0x4100C0EC) /**< \brief (HMATRIX) Priority B for Slave 13 */
+#define REG_HMATRIX_PRAS14         (0x4100C0F0) /**< \brief (HMATRIX) Priority A for Slave 14 */
+#define REG_HMATRIX_PRBS14         (0x4100C0F4) /**< \brief (HMATRIX) Priority B for Slave 14 */
+#define REG_HMATRIX_PRAS15         (0x4100C0F8) /**< \brief (HMATRIX) Priority A for Slave 15 */
+#define REG_HMATRIX_PRBS15         (0x4100C0FC) /**< \brief (HMATRIX) Priority B for Slave 15 */
+#else
+#define REG_HMATRIX_PRAS0          (*(RwReg  *)0x4100C080UL) /**< \brief (HMATRIX) Priority A for Slave 0 */
+#define REG_HMATRIX_PRBS0          (*(RwReg  *)0x4100C084UL) /**< \brief (HMATRIX) Priority B for Slave 0 */
+#define REG_HMATRIX_PRAS1          (*(RwReg  *)0x4100C088UL) /**< \brief (HMATRIX) Priority A for Slave 1 */
+#define REG_HMATRIX_PRBS1          (*(RwReg  *)0x4100C08CUL) /**< \brief (HMATRIX) Priority B for Slave 1 */
+#define REG_HMATRIX_PRAS2          (*(RwReg  *)0x4100C090UL) /**< \brief (HMATRIX) Priority A for Slave 2 */
+#define REG_HMATRIX_PRBS2          (*(RwReg  *)0x4100C094UL) /**< \brief (HMATRIX) Priority B for Slave 2 */
+#define REG_HMATRIX_PRAS3          (*(RwReg  *)0x4100C098UL) /**< \brief (HMATRIX) Priority A for Slave 3 */
+#define REG_HMATRIX_PRBS3          (*(RwReg  *)0x4100C09CUL) /**< \brief (HMATRIX) Priority B for Slave 3 */
+#define REG_HMATRIX_PRAS4          (*(RwReg  *)0x4100C0A0UL) /**< \brief (HMATRIX) Priority A for Slave 4 */
+#define REG_HMATRIX_PRBS4          (*(RwReg  *)0x4100C0A4UL) /**< \brief (HMATRIX) Priority B for Slave 4 */
+#define REG_HMATRIX_PRAS5          (*(RwReg  *)0x4100C0A8UL) /**< \brief (HMATRIX) Priority A for Slave 5 */
+#define REG_HMATRIX_PRBS5          (*(RwReg  *)0x4100C0ACUL) /**< \brief (HMATRIX) Priority B for Slave 5 */
+#define REG_HMATRIX_PRAS6          (*(RwReg  *)0x4100C0B0UL) /**< \brief (HMATRIX) Priority A for Slave 6 */
+#define REG_HMATRIX_PRBS6          (*(RwReg  *)0x4100C0B4UL) /**< \brief (HMATRIX) Priority B for Slave 6 */
+#define REG_HMATRIX_PRAS7          (*(RwReg  *)0x4100C0B8UL) /**< \brief (HMATRIX) Priority A for Slave 7 */
+#define REG_HMATRIX_PRBS7          (*(RwReg  *)0x4100C0BCUL) /**< \brief (HMATRIX) Priority B for Slave 7 */
+#define REG_HMATRIX_PRAS8          (*(RwReg  *)0x4100C0C0UL) /**< \brief (HMATRIX) Priority A for Slave 8 */
+#define REG_HMATRIX_PRBS8          (*(RwReg  *)0x4100C0C4UL) /**< \brief (HMATRIX) Priority B for Slave 8 */
+#define REG_HMATRIX_PRAS9          (*(RwReg  *)0x4100C0C8UL) /**< \brief (HMATRIX) Priority A for Slave 9 */
+#define REG_HMATRIX_PRBS9          (*(RwReg  *)0x4100C0CCUL) /**< \brief (HMATRIX) Priority B for Slave 9 */
+#define REG_HMATRIX_PRAS10         (*(RwReg  *)0x4100C0D0UL) /**< \brief (HMATRIX) Priority A for Slave 10 */
+#define REG_HMATRIX_PRBS10         (*(RwReg  *)0x4100C0D4UL) /**< \brief (HMATRIX) Priority B for Slave 10 */
+#define REG_HMATRIX_PRAS11         (*(RwReg  *)0x4100C0D8UL) /**< \brief (HMATRIX) Priority A for Slave 11 */
+#define REG_HMATRIX_PRBS11         (*(RwReg  *)0x4100C0DCUL) /**< \brief (HMATRIX) Priority B for Slave 11 */
+#define REG_HMATRIX_PRAS12         (*(RwReg  *)0x4100C0E0UL) /**< \brief (HMATRIX) Priority A for Slave 12 */
+#define REG_HMATRIX_PRBS12         (*(RwReg  *)0x4100C0E4UL) /**< \brief (HMATRIX) Priority B for Slave 12 */
+#define REG_HMATRIX_PRAS13         (*(RwReg  *)0x4100C0E8UL) /**< \brief (HMATRIX) Priority A for Slave 13 */
+#define REG_HMATRIX_PRBS13         (*(RwReg  *)0x4100C0ECUL) /**< \brief (HMATRIX) Priority B for Slave 13 */
+#define REG_HMATRIX_PRAS14         (*(RwReg  *)0x4100C0F0UL) /**< \brief (HMATRIX) Priority A for Slave 14 */
+#define REG_HMATRIX_PRBS14         (*(RwReg  *)0x4100C0F4UL) /**< \brief (HMATRIX) Priority B for Slave 14 */
+#define REG_HMATRIX_PRAS15         (*(RwReg  *)0x4100C0F8UL) /**< \brief (HMATRIX) Priority A for Slave 15 */
+#define REG_HMATRIX_PRBS15         (*(RwReg  *)0x4100C0FCUL) /**< \brief (HMATRIX) Priority B for Slave 15 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for HMATRIX peripheral ========== */
+#define HMATRIX_CLK_AHB_ID          5        // Index of AHB Clock in MCLK.AHBMASK register (MASK may be tied to 1 depending on chip integration)
+#define HMATRIX_DEFINED                     
+/* ========== Instance parameters for HMATRIX ========== */
+#define HMATRIX_SLAVE_FLASH         0
+#define HMATRIX_SLAVE_FLASH_ALT     1
+#define HMATRIX_SLAVE_SEEPROM       2
+#define HMATRIX_SLAVE_RAMCM4S       3
+#define HMATRIX_SLAVE_RAMPPPDSU     4
+#define HMATRIX_SLAVE_RAMDMAWR      5
+#define HMATRIX_SLAVE_RAMDMACICM    6
+#define HMATRIX_SLAVE_HPB0          7
+#define HMATRIX_SLAVE_HPB1          8
+#define HMATRIX_SLAVE_HPB2          9
+#define HMATRIX_SLAVE_HPB3          10
+#define HMATRIX_SLAVE_SDHC0         12
+#define HMATRIX_SLAVE_SDHC1         13
+#define HMATRIX_SLAVE_QSPI          14
+#define HMATRIX_SLAVE_BKUPRAM       15
+#define HMATRIX_SLAVE_NUM           16
+
+#define HMATRIX_MASTER_CM4_S        0
+#define HMATRIX_MASTER_CMCC         1
+#define HMATRIX_MASTER_PICOP_MEM    2
+#define HMATRIX_MASTER_PICOP_IO     3
+#define HMATRIX_MASTER_DMAC_DTWR    4
+#define HMATRIX_MASTER_DMAC_DTRD    5
+#define HMATRIX_MASTER_ICM          6
+#define HMATRIX_MASTER_DSU          7
+#define HMATRIX_MASTER_NUM          8
+
+#endif /* _SAME53_HMATRIX_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/i2s.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/i2s.h
new file mode 100644
index 000000000..003e7603d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/i2s.h	
@@ -0,0 +1,81 @@
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_I2S_INSTANCE_
+#define _SAME53_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA              (0x43002800) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (0x43002804) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (0x43002808) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (0x4300280C) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (0x43002810) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (0x43002814) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (0x43002818) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_TXCTRL             (0x43002820) /**< \brief (I2S) Tx Serializer Control */
+#define REG_I2S_RXCTRL             (0x43002824) /**< \brief (I2S) Rx Serializer Control */
+#define REG_I2S_TXDATA             (0x43002830) /**< \brief (I2S) Tx Data */
+#define REG_I2S_RXDATA             (0x43002834) /**< \brief (I2S) Rx Data */
+#else
+#define REG_I2S_CTRLA              (*(RwReg8 *)0x43002800UL) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0           (*(RwReg  *)0x43002804UL) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1           (*(RwReg  *)0x43002808UL) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR           (*(RwReg16*)0x4300280CUL) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET           (*(RwReg16*)0x43002810UL) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG            (*(RwReg16*)0x43002814UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY           (*(RoReg16*)0x43002818UL) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_TXCTRL             (*(RwReg  *)0x43002820UL) /**< \brief (I2S) Tx Serializer Control */
+#define REG_I2S_RXCTRL             (*(RwReg  *)0x43002824UL) /**< \brief (I2S) Rx Serializer Control */
+#define REG_I2S_TXDATA             (*(WoReg  *)0x43002830UL) /**< \brief (I2S) Tx Data */
+#define REG_I2S_RXDATA             (*(RoReg  *)0x43002834UL) /**< \brief (I2S) Rx Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM                 2        // Number of clock units
+#define I2S_DMAC_ID_RX_0            76
+#define I2S_DMAC_ID_RX_1            77
+#define I2S_DMAC_ID_RX_LSB          76
+#define I2S_DMAC_ID_RX_MSB          77
+#define I2S_DMAC_ID_RX_SIZE         2
+#define I2S_DMAC_ID_TX_0            78
+#define I2S_DMAC_ID_TX_1            79
+#define I2S_DMAC_ID_TX_LSB          78
+#define I2S_DMAC_ID_TX_MSB          79
+#define I2S_DMAC_ID_TX_SIZE         2
+#define I2S_GCLK_ID_0               43
+#define I2S_GCLK_ID_1               44
+#define I2S_GCLK_ID_LSB             43
+#define I2S_GCLK_ID_MSB             44
+#define I2S_GCLK_ID_SIZE            2
+#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
+#define I2S_MAX_WL_BITS             32       // Max number of bits in data samples
+#define I2S_SER_NUM                 2        // Number of serializers
+
+#endif /* _SAME53_I2S_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/icm.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/icm.h
new file mode 100644
index 000000000..6286ad795
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/icm.h	
@@ -0,0 +1,77 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ICM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_ICM_INSTANCE_
+#define _SAME53_ICM_INSTANCE_
+
+/* ========== Register definition for ICM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ICM_CFG                (0x42002C00) /**< \brief (ICM) Configuration */
+#define REG_ICM_CTRL               (0x42002C04) /**< \brief (ICM) Control */
+#define REG_ICM_SR                 (0x42002C08) /**< \brief (ICM) Status */
+#define REG_ICM_IER                (0x42002C10) /**< \brief (ICM) Interrupt Enable */
+#define REG_ICM_IDR                (0x42002C14) /**< \brief (ICM) Interrupt Disable */
+#define REG_ICM_IMR                (0x42002C18) /**< \brief (ICM) Interrupt Mask */
+#define REG_ICM_ISR                (0x42002C1C) /**< \brief (ICM) Interrupt Status */
+#define REG_ICM_UASR               (0x42002C20) /**< \brief (ICM) Undefined Access Status */
+#define REG_ICM_DSCR               (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */
+#define REG_ICM_HASH               (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */
+#define REG_ICM_UIHVAL0            (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */
+#define REG_ICM_UIHVAL1            (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */
+#define REG_ICM_UIHVAL2            (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */
+#define REG_ICM_UIHVAL3            (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */
+#define REG_ICM_UIHVAL4            (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */
+#define REG_ICM_UIHVAL5            (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */
+#define REG_ICM_UIHVAL6            (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */
+#define REG_ICM_UIHVAL7            (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */
+#else
+#define REG_ICM_CFG                (*(RwReg  *)0x42002C00UL) /**< \brief (ICM) Configuration */
+#define REG_ICM_CTRL               (*(WoReg  *)0x42002C04UL) /**< \brief (ICM) Control */
+#define REG_ICM_SR                 (*(RoReg  *)0x42002C08UL) /**< \brief (ICM) Status */
+#define REG_ICM_IER                (*(WoReg  *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */
+#define REG_ICM_IDR                (*(WoReg  *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */
+#define REG_ICM_IMR                (*(RoReg  *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */
+#define REG_ICM_ISR                (*(RoReg  *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */
+#define REG_ICM_UASR               (*(RoReg  *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */
+#define REG_ICM_DSCR               (*(RwReg  *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */
+#define REG_ICM_HASH               (*(RwReg  *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */
+#define REG_ICM_UIHVAL0            (*(WoReg  *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */
+#define REG_ICM_UIHVAL1            (*(WoReg  *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */
+#define REG_ICM_UIHVAL2            (*(WoReg  *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */
+#define REG_ICM_UIHVAL3            (*(WoReg  *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */
+#define REG_ICM_UIHVAL4            (*(WoReg  *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */
+#define REG_ICM_UIHVAL5            (*(WoReg  *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */
+#define REG_ICM_UIHVAL6            (*(WoReg  *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */
+#define REG_ICM_UIHVAL7            (*(WoReg  *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ICM peripheral ========== */
+#define ICM_CLK_AHB_ID              19      
+
+#endif /* _SAME53_ICM_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/mclk.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/mclk.h
new file mode 100644
index 000000000..bc5751960
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/mclk.h	
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Instance description for MCLK
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_MCLK_INSTANCE_
+#define _SAME53_MCLK_INSTANCE_
+
+/* ========== Register definition for MCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MCLK_INTENCLR          (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
+#define REG_MCLK_INTENSET          (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
+#define REG_MCLK_INTFLAG           (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
+#define REG_MCLK_HSDIV             (0x40000804) /**< \brief (MCLK) HS Clock Division */
+#define REG_MCLK_CPUDIV            (0x40000805) /**< \brief (MCLK) CPU Clock Division */
+#define REG_MCLK_AHBMASK           (0x40000810) /**< \brief (MCLK) AHB Mask */
+#define REG_MCLK_APBAMASK          (0x40000814) /**< \brief (MCLK) APBA Mask */
+#define REG_MCLK_APBBMASK          (0x40000818) /**< \brief (MCLK) APBB Mask */
+#define REG_MCLK_APBCMASK          (0x4000081C) /**< \brief (MCLK) APBC Mask */
+#define REG_MCLK_APBDMASK          (0x40000820) /**< \brief (MCLK) APBD Mask */
+#else
+#define REG_MCLK_INTENCLR          (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
+#define REG_MCLK_INTENSET          (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
+#define REG_MCLK_INTFLAG           (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
+#define REG_MCLK_HSDIV             (*(RoReg8 *)0x40000804UL) /**< \brief (MCLK) HS Clock Division */
+#define REG_MCLK_CPUDIV            (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division */
+#define REG_MCLK_AHBMASK           (*(RwReg  *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
+#define REG_MCLK_APBAMASK          (*(RwReg  *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
+#define REG_MCLK_APBBMASK          (*(RwReg  *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
+#define REG_MCLK_APBCMASK          (*(RwReg  *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
+#define REG_MCLK_APBDMASK          (*(RwReg  *)0x40000820UL) /**< \brief (MCLK) APBD Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for MCLK peripheral ========== */
+#define MCLK_SYSTEM_CLOCK           48000000 // System Clock Frequency at Reset
+
+#endif /* _SAME53_MCLK_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/nvmctrl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/nvmctrl.h
new file mode 100644
index 000000000..628e35caf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/nvmctrl.h	
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_NVMCTRL_INSTANCE_
+#define _SAME53_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA          (0x41004000) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (0x41004004) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (0x4100400E) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (0x41004010) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (0x41004012) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (0x41004014) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_RUNLOCK        (0x41004018) /**< \brief (NVMCTRL) Lock Section */
+#define REG_NVMCTRL_PBLDATA0       (0x4100401C) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
+#define REG_NVMCTRL_PBLDATA1       (0x41004020) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
+#define REG_NVMCTRL_ECCERR         (0x41004024) /**< \brief (NVMCTRL) ECC Error Status Register */
+#define REG_NVMCTRL_DBGCTRL        (0x41004028) /**< \brief (NVMCTRL) Debug Control */
+#define REG_NVMCTRL_SEECFG         (0x4100402A) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
+#define REG_NVMCTRL_SEESTAT        (0x4100402C) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
+#else
+#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB          (*(WoReg16*)0x41004004UL) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM          (*(RoReg  *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR       (*(RwReg16*)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET       (*(RwReg16*)0x4100400EUL) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG        (*(RwReg16*)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS         (*(RoReg16*)0x41004012UL) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x41004014UL) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_RUNLOCK        (*(RoReg  *)0x41004018UL) /**< \brief (NVMCTRL) Lock Section */
+#define REG_NVMCTRL_PBLDATA0       (*(RoReg  *)0x4100401CUL) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
+#define REG_NVMCTRL_PBLDATA1       (*(RoReg  *)0x41004020UL) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
+#define REG_NVMCTRL_ECCERR         (*(RoReg  *)0x41004024UL) /**< \brief (NVMCTRL) ECC Error Status Register */
+#define REG_NVMCTRL_DBGCTRL        (*(RwReg8 *)0x41004028UL) /**< \brief (NVMCTRL) Debug Control */
+#define REG_NVMCTRL_SEECFG         (*(RwReg8 *)0x4100402AUL) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
+#define REG_NVMCTRL_SEESTAT        (*(RoReg  *)0x4100402CUL) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_BLOCK_SIZE          8192     // Size Of Block (Bytes, Smallest Granularity for Erase Operation)
+#define NVMCTRL_CLK_AHB_ID          6        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_CLK_AHB_ID_CACHE    23       // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines
+#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22       // Index of AHB Clock in PM.AHBMASK register for SMEE submodule
+#define NVMCTRL_PAGE_SIZE           512      // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)
+
+#endif /* _SAME53_NVMCTRL_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/osc32kctrl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/osc32kctrl.h
new file mode 100644
index 000000000..a2a328f94
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/osc32kctrl.h	
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for OSC32KCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_OSC32KCTRL_INSTANCE_
+#define _SAME53_OSC32KCTRL_INSTANCE_
+
+/* ========== Register definition for OSC32KCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_OSC32KCTRL_INTENCLR    (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
+#define REG_OSC32KCTRL_INTENSET    (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
+#define REG_OSC32KCTRL_INTFLAG     (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
+#define REG_OSC32KCTRL_STATUS      (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
+#define REG_OSC32KCTRL_RTCCTRL     (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */
+#define REG_OSC32KCTRL_XOSC32K     (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_OSC32KCTRL_CFDCTRL     (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
+#define REG_OSC32KCTRL_EVCTRL      (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
+#define REG_OSC32KCTRL_OSCULP32K   (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#else
+#define REG_OSC32KCTRL_INTENCLR    (*(RwReg  *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
+#define REG_OSC32KCTRL_INTENSET    (*(RwReg  *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
+#define REG_OSC32KCTRL_INTFLAG     (*(RwReg  *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
+#define REG_OSC32KCTRL_STATUS      (*(RoReg  *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
+#define REG_OSC32KCTRL_RTCCTRL     (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */
+#define REG_OSC32KCTRL_XOSC32K     (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_OSC32KCTRL_CFDCTRL     (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
+#define REG_OSC32KCTRL_EVCTRL      (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
+#define REG_OSC32KCTRL_OSCULP32K   (*(RwReg  *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
+#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0        // OSC32K coarse calibration size
+
+#endif /* _SAME53_OSC32KCTRL_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/oscctrl.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/oscctrl.h
new file mode 100644
index 000000000..3de419cba
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/oscctrl.h	
@@ -0,0 +1,130 @@
+/**
+ * \file
+ *
+ * \brief Instance description for OSCCTRL
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_OSCCTRL_INSTANCE_
+#define _SAME53_OSCCTRL_INSTANCE_
+
+/* ========== Register definition for OSCCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_OSCCTRL_EVCTRL         (0x40001000) /**< \brief (OSCCTRL) Event Control */
+#define REG_OSCCTRL_INTENCLR       (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Clear */
+#define REG_OSCCTRL_INTENSET       (0x40001008) /**< \brief (OSCCTRL) Interrupt Enable Set */
+#define REG_OSCCTRL_INTFLAG        (0x4000100C) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
+#define REG_OSCCTRL_STATUS         (0x40001010) /**< \brief (OSCCTRL) Status */
+#define REG_OSCCTRL_XOSCCTRL0      (0x40001014) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
+#define REG_OSCCTRL_XOSCCTRL1      (0x40001018) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
+#define REG_OSCCTRL_DFLLCTRLA      (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Control A */
+#define REG_OSCCTRL_DFLLCTRLB      (0x40001020) /**< \brief (OSCCTRL) DFLL48M Control B */
+#define REG_OSCCTRL_DFLLVAL        (0x40001024) /**< \brief (OSCCTRL) DFLL48M Value */
+#define REG_OSCCTRL_DFLLMUL        (0x40001028) /**< \brief (OSCCTRL) DFLL48M Multiplier */
+#define REG_OSCCTRL_DFLLSYNC       (0x4000102C) /**< \brief (OSCCTRL) DFLL48M Synchronization */
+#define REG_OSCCTRL_DPLLCTRLA0     (0x40001030) /**< \brief (OSCCTRL) DPLL Control A 0 */
+#define REG_OSCCTRL_DPLLRATIO0     (0x40001034) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
+#define REG_OSCCTRL_DPLLCTRLB0     (0x40001038) /**< \brief (OSCCTRL) DPLL Control B 0 */
+#define REG_OSCCTRL_DPLLSYNCBUSY0  (0x4000103C) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
+#define REG_OSCCTRL_DPLLSTATUS0    (0x40001040) /**< \brief (OSCCTRL) DPLL Status 0 */
+#define REG_OSCCTRL_DPLLCTRLA1     (0x40001044) /**< \brief (OSCCTRL) DPLL Control A 1 */
+#define REG_OSCCTRL_DPLLRATIO1     (0x40001048) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
+#define REG_OSCCTRL_DPLLCTRLB1     (0x4000104C) /**< \brief (OSCCTRL) DPLL Control B 1 */
+#define REG_OSCCTRL_DPLLSYNCBUSY1  (0x40001050) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
+#define REG_OSCCTRL_DPLLSTATUS1    (0x40001054) /**< \brief (OSCCTRL) DPLL Status 1 */
+#else
+#define REG_OSCCTRL_EVCTRL         (*(RwReg8 *)0x40001000UL) /**< \brief (OSCCTRL) Event Control */
+#define REG_OSCCTRL_INTENCLR       (*(RwReg  *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
+#define REG_OSCCTRL_INTENSET       (*(RwReg  *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
+#define REG_OSCCTRL_INTFLAG        (*(RwReg  *)0x4000100CUL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
+#define REG_OSCCTRL_STATUS         (*(RoReg  *)0x40001010UL) /**< \brief (OSCCTRL) Status */
+#define REG_OSCCTRL_XOSCCTRL0      (*(RwReg  *)0x40001014UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
+#define REG_OSCCTRL_XOSCCTRL1      (*(RwReg  *)0x40001018UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
+#define REG_OSCCTRL_DFLLCTRLA      (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Control A */
+#define REG_OSCCTRL_DFLLCTRLB      (*(RwReg8 *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Control B */
+#define REG_OSCCTRL_DFLLVAL        (*(RwReg  *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Value */
+#define REG_OSCCTRL_DFLLMUL        (*(RwReg  *)0x40001028UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
+#define REG_OSCCTRL_DFLLSYNC       (*(RwReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
+#define REG_OSCCTRL_DPLLCTRLA0     (*(RwReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Control A 0 */
+#define REG_OSCCTRL_DPLLRATIO0     (*(RwReg  *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
+#define REG_OSCCTRL_DPLLCTRLB0     (*(RwReg  *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Control B 0 */
+#define REG_OSCCTRL_DPLLSYNCBUSY0  (*(RoReg  *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
+#define REG_OSCCTRL_DPLLSTATUS0    (*(RoReg  *)0x40001040UL) /**< \brief (OSCCTRL) DPLL Status 0 */
+#define REG_OSCCTRL_DPLLCTRLA1     (*(RwReg8 *)0x40001044UL) /**< \brief (OSCCTRL) DPLL Control A 1 */
+#define REG_OSCCTRL_DPLLRATIO1     (*(RwReg  *)0x40001048UL) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
+#define REG_OSCCTRL_DPLLCTRLB1     (*(RwReg  *)0x4000104CUL) /**< \brief (OSCCTRL) DPLL Control B 1 */
+#define REG_OSCCTRL_DPLLSYNCBUSY1  (*(RoReg  *)0x40001050UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
+#define REG_OSCCTRL_DPLLSTATUS1    (*(RoReg  *)0x40001054UL) /**< \brief (OSCCTRL) DPLL Status 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for OSCCTRL peripheral ========== */
+#define OSCCTRL_DFLLS_NUM           1        // Number of DFLLs
+#define OSCCTRL_DFLL_IMPLEMENTED    1        // DFLL implemented
+#define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0        // DFLL48M bias test mode implemented
+#define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2        // Size COARSE DAC STEP
+#define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32       // DFLL48M Frequency Coarse Reset Value (Before Calibration)
+#define OSCCTRL_DFLL48M_COARSE_SIZE 6        // Size COARSE CALIBRATION
+#define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1        // Run oscillator at reset
+#define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2        // Size FINE DAC STEP
+#define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128      // DFLL48M Frequency Fine Reset Value (Before Calibration)
+#define OSCCTRL_DFLL48M_FINE_SIZE   8        // Size FINE CALIBRATION
+#define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1        // Run oscillator always or only when requested
+#define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0        // Run oscillator even if standby mode
+#define OSCCTRL_DFLL48M_TCAL_SIZE   4        // Size TEMP CALIBRATION
+#define OSCCTRL_DFLL48M_TCBIAS_SIZE 2        // Size TC BIAS CALIBRATION
+#define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3        // Size TEST POINT SELECTOR
+#define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1        // Enable Wait Lock Feature
+#define OSCCTRL_DPLLS_NUM           2        // Number of DPLLs
+#define OSCCTRL_DPLL0_IMPLEMENTED   1        // DPLL0 implemented
+#define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0        // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
+#define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1        // DPLL0 OCC Implemented
+#define OSCCTRL_DPLL1_IMPLEMENTED   1        // DPLL1 implemented
+#define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0        // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
+#define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0        // DPLL1 OCC Implemented
+#define OSCCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
+#define OSCCTRL_GCLK_ID_FDPLL0      1        // Index of Generic Clock for DPLL0
+#define OSCCTRL_GCLK_ID_FDPLL1      2        // Index of Generic Clock for DPLL1
+#define OSCCTRL_GCLK_ID_FDPLL032K   3        // Index of Generic Clock for DPLL0 32K
+#define OSCCTRL_GCLK_ID_FDPLL132K   3        // Index of Generic Clock for DPLL1 32K
+#define OSCCTRL_OSC16M_IMPLEMENTED  0        // OSC16M implemented
+#define OSCCTRL_OSC48M_IMPLEMENTED  0        // OSC48M implemented
+#define OSCCTRL_OSC48M_NUM          1       
+#define OSCCTRL_RCOSCS_NUM          1        // Number of RCOSCs (min 1)
+#define OSCCTRL_XOSCS_NUM           2        // Number of XOSCs
+#define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4        // Clock fail prescaler size
+#define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1        // Clock fail detected for xosc implemented
+#define OSCCTRL_XOSC0_IMPLEMENTED   1        // XOSC0 implemented
+#define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1        // Run oscillator always or only when requested
+#define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0        // Run oscillator even if standby mode
+#define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4        // Clock fail prescaler size
+#define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1        // Clock fail detected for xosc implemented
+#define OSCCTRL_XOSC1_IMPLEMENTED   1        // XOSC1 implemented
+#define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1        // Run oscillator always or only when requested
+#define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0        // Run oscillator even if standby mode
+#define OSCCTRL_DFLL48M_VERSION     0x100   
+#define OSCCTRL_FDPLL_VERSION       0x100   
+#define OSCCTRL_XOSC_VERSION        0x100   
+
+#endif /* _SAME53_OSCCTRL_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pac.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pac.h
new file mode 100644
index 000000000..0571e3e27
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pac.h	
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PAC_INSTANCE_
+#define _SAME53_PAC_INSTANCE_
+
+/* ========== Register definition for PAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC_WRCTRL             (0x40000000) /**< \brief (PAC) Write control */
+#define REG_PAC_EVCTRL             (0x40000004) /**< \brief (PAC) Event control */
+#define REG_PAC_INTENCLR           (0x40000008) /**< \brief (PAC) Interrupt enable clear */
+#define REG_PAC_INTENSET           (0x40000009) /**< \brief (PAC) Interrupt enable set */
+#define REG_PAC_INTFLAGAHB         (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
+#define REG_PAC_INTFLAGA           (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
+#define REG_PAC_INTFLAGB           (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
+#define REG_PAC_INTFLAGC           (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
+#define REG_PAC_INTFLAGD           (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
+#define REG_PAC_STATUSA            (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
+#define REG_PAC_STATUSB            (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
+#define REG_PAC_STATUSC            (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
+#define REG_PAC_STATUSD            (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */
+#else
+#define REG_PAC_WRCTRL             (*(RwReg  *)0x40000000UL) /**< \brief (PAC) Write control */
+#define REG_PAC_EVCTRL             (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
+#define REG_PAC_INTENCLR           (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
+#define REG_PAC_INTENSET           (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
+#define REG_PAC_INTFLAGAHB         (*(RwReg  *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
+#define REG_PAC_INTFLAGA           (*(RwReg  *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
+#define REG_PAC_INTFLAGB           (*(RwReg  *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
+#define REG_PAC_INTFLAGC           (*(RwReg  *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
+#define REG_PAC_INTFLAGD           (*(RwReg  *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
+#define REG_PAC_STATUSA            (*(RoReg  *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
+#define REG_PAC_STATUSB            (*(RoReg  *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
+#define REG_PAC_STATUSC            (*(RoReg  *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
+#define REG_PAC_STATUSD            (*(RoReg  *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC peripheral ========== */
+#define PAC_CLK_AHB_DOMAIN                   // Clock domain of AHB clock
+#define PAC_CLK_AHB_ID              12       // AHB clock index
+#define PAC_HPB_NUM                 4        // Number of bridges AHB/APB
+
+#endif /* _SAME53_PAC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pcc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pcc.h
new file mode 100644
index 000000000..07a82848a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pcc.h	
@@ -0,0 +1,58 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PCC_INSTANCE_
+#define _SAME53_PCC_INSTANCE_
+
+/* ========== Register definition for PCC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PCC_MR                 (0x43002C00) /**< \brief (PCC) Mode Register */
+#define REG_PCC_IER                (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */
+#define REG_PCC_IDR                (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */
+#define REG_PCC_IMR                (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */
+#define REG_PCC_ISR                (0x43002C10) /**< \brief (PCC) Interrupt Status Register */
+#define REG_PCC_RHR                (0x43002C14) /**< \brief (PCC) Reception Holding Register */
+#define REG_PCC_WPMR               (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */
+#define REG_PCC_WPSR               (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */
+#else
+#define REG_PCC_MR                 (*(RwReg  *)0x43002C00UL) /**< \brief (PCC) Mode Register */
+#define REG_PCC_IER                (*(WoReg  *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */
+#define REG_PCC_IDR                (*(WoReg  *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */
+#define REG_PCC_IMR                (*(RoReg  *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */
+#define REG_PCC_ISR                (*(RoReg  *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */
+#define REG_PCC_RHR                (*(RoReg  *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */
+#define REG_PCC_WPMR               (*(RwReg  *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */
+#define REG_PCC_WPSR               (*(RoReg  *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PCC peripheral ========== */
+#define PCC_DATA_SIZE               14      
+#define PCC_DMAC_ID_RX              80      
+
+#endif /* _SAME53_PCC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pdec.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pdec.h
new file mode 100644
index 000000000..d5105985f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pdec.h	
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PDEC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PDEC_INSTANCE_
+#define _SAME53_PDEC_INSTANCE_
+
+/* ========== Register definition for PDEC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PDEC_CTRLA             (0x42001C00) /**< \brief (PDEC) Control A */
+#define REG_PDEC_CTRLBCLR          (0x42001C04) /**< \brief (PDEC) Control B Clear */
+#define REG_PDEC_CTRLBSET          (0x42001C05) /**< \brief (PDEC) Control B Set */
+#define REG_PDEC_EVCTRL            (0x42001C06) /**< \brief (PDEC) Event Control */
+#define REG_PDEC_INTENCLR          (0x42001C08) /**< \brief (PDEC) Interrupt Enable Clear */
+#define REG_PDEC_INTENSET          (0x42001C09) /**< \brief (PDEC) Interrupt Enable Set */
+#define REG_PDEC_INTFLAG           (0x42001C0A) /**< \brief (PDEC) Interrupt Flag Status and Clear */
+#define REG_PDEC_STATUS            (0x42001C0C) /**< \brief (PDEC) Status */
+#define REG_PDEC_DBGCTRL           (0x42001C0F) /**< \brief (PDEC) Debug Control */
+#define REG_PDEC_SYNCBUSY          (0x42001C10) /**< \brief (PDEC) Synchronization Status */
+#define REG_PDEC_PRESC             (0x42001C14) /**< \brief (PDEC) Prescaler Value */
+#define REG_PDEC_FILTER            (0x42001C15) /**< \brief (PDEC) Filter Value */
+#define REG_PDEC_PRESCBUF          (0x42001C18) /**< \brief (PDEC) Prescaler Buffer Value */
+#define REG_PDEC_FILTERBUF         (0x42001C19) /**< \brief (PDEC) Filter Buffer Value */
+#define REG_PDEC_COUNT             (0x42001C1C) /**< \brief (PDEC) Counter Value */
+#define REG_PDEC_CC0               (0x42001C20) /**< \brief (PDEC) Channel 0 Compare Value */
+#define REG_PDEC_CC1               (0x42001C24) /**< \brief (PDEC) Channel 1 Compare Value */
+#define REG_PDEC_CCBUF0            (0x42001C30) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
+#define REG_PDEC_CCBUF1            (0x42001C34) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
+#else
+#define REG_PDEC_CTRLA             (*(RwReg  *)0x42001C00UL) /**< \brief (PDEC) Control A */
+#define REG_PDEC_CTRLBCLR          (*(RwReg8 *)0x42001C04UL) /**< \brief (PDEC) Control B Clear */
+#define REG_PDEC_CTRLBSET          (*(RwReg8 *)0x42001C05UL) /**< \brief (PDEC) Control B Set */
+#define REG_PDEC_EVCTRL            (*(RwReg16*)0x42001C06UL) /**< \brief (PDEC) Event Control */
+#define REG_PDEC_INTENCLR          (*(RwReg8 *)0x42001C08UL) /**< \brief (PDEC) Interrupt Enable Clear */
+#define REG_PDEC_INTENSET          (*(RwReg8 *)0x42001C09UL) /**< \brief (PDEC) Interrupt Enable Set */
+#define REG_PDEC_INTFLAG           (*(RwReg8 *)0x42001C0AUL) /**< \brief (PDEC) Interrupt Flag Status and Clear */
+#define REG_PDEC_STATUS            (*(RwReg16*)0x42001C0CUL) /**< \brief (PDEC) Status */
+#define REG_PDEC_DBGCTRL           (*(RwReg8 *)0x42001C0FUL) /**< \brief (PDEC) Debug Control */
+#define REG_PDEC_SYNCBUSY          (*(RoReg  *)0x42001C10UL) /**< \brief (PDEC) Synchronization Status */
+#define REG_PDEC_PRESC             (*(RwReg8 *)0x42001C14UL) /**< \brief (PDEC) Prescaler Value */
+#define REG_PDEC_FILTER            (*(RwReg8 *)0x42001C15UL) /**< \brief (PDEC) Filter Value */
+#define REG_PDEC_PRESCBUF          (*(RwReg8 *)0x42001C18UL) /**< \brief (PDEC) Prescaler Buffer Value */
+#define REG_PDEC_FILTERBUF         (*(RwReg8 *)0x42001C19UL) /**< \brief (PDEC) Filter Buffer Value */
+#define REG_PDEC_COUNT             (*(RwReg  *)0x42001C1CUL) /**< \brief (PDEC) Counter Value */
+#define REG_PDEC_CC0               (*(RwReg  *)0x42001C20UL) /**< \brief (PDEC) Channel 0 Compare Value */
+#define REG_PDEC_CC1               (*(RwReg  *)0x42001C24UL) /**< \brief (PDEC) Channel 1 Compare Value */
+#define REG_PDEC_CCBUF0            (*(RwReg  *)0x42001C30UL) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
+#define REG_PDEC_CCBUF1            (*(RwReg  *)0x42001C34UL) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PDEC peripheral ========== */
+#define PDEC_CC_NUM                 2        // Number of Compare Channels units
+#define PDEC_GCLK_ID                31      
+
+#endif /* _SAME53_PDEC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pm.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pm.h
new file mode 100644
index 000000000..c61e4371c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pm.h	
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PM_INSTANCE_
+#define _SAME53_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRLA               (0x40000400) /**< \brief (PM) Control A */
+#define REG_PM_SLEEPCFG            (0x40000401) /**< \brief (PM) Sleep Configuration */
+#define REG_PM_INTENCLR            (0x40000404) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (0x40000405) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_STDBYCFG            (0x40000408) /**< \brief (PM) Standby Configuration */
+#define REG_PM_HIBCFG              (0x40000409) /**< \brief (PM) Hibernate Configuration */
+#define REG_PM_BKUPCFG             (0x4000040A) /**< \brief (PM) Backup Configuration */
+#define REG_PM_PWSAKDLY            (0x40000412) /**< \brief (PM) Power Switch Acknowledge Delay */
+#else
+#define REG_PM_CTRLA               (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */
+#define REG_PM_SLEEPCFG            (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
+#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET            (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_STDBYCFG            (*(RwReg8 *)0x40000408UL) /**< \brief (PM) Standby Configuration */
+#define REG_PM_HIBCFG              (*(RwReg8 *)0x40000409UL) /**< \brief (PM) Hibernate Configuration */
+#define REG_PM_BKUPCFG             (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) Backup Configuration */
+#define REG_PM_PWSAKDLY            (*(RwReg8 *)0x40000412UL) /**< \brief (PM) Power Switch Acknowledge Delay */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_PD_NUM                   0        // Number of switchable Power Domains
+
+#endif /* _SAME53_PM_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/port.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/port.h
new file mode 100644
index 000000000..551ec99b3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/port.h	
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PORT_INSTANCE_
+#define _SAME53_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0              (0x41008000) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (0x41008004) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (0x41008008) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (0x4100800C) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (0x41008010) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (0x41008014) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (0x41008018) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (0x4100801C) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (0x41008020) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (0x41008024) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (0x41008028) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_EVCTRL0           (0x4100802C) /**< \brief (PORT) Event Input Control 0 */
+#define REG_PORT_PMUX0             (0x41008030) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (0x41008040) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (0x41008080) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (0x41008084) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (0x41008088) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (0x4100808C) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (0x41008090) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (0x41008094) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (0x41008098) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (0x4100809C) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (0x410080A0) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (0x410080A4) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (0x410080A8) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_EVCTRL1           (0x410080AC) /**< \brief (PORT) Event Input Control 1 */
+#define REG_PORT_PMUX1             (0x410080B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (0x410080C0) /**< \brief (PORT) Pin Configuration 1 */
+#define REG_PORT_DIR2              (0x41008100) /**< \brief (PORT) Data Direction 2 */
+#define REG_PORT_DIRCLR2           (0x41008104) /**< \brief (PORT) Data Direction Clear 2 */
+#define REG_PORT_DIRSET2           (0x41008108) /**< \brief (PORT) Data Direction Set 2 */
+#define REG_PORT_DIRTGL2           (0x4100810C) /**< \brief (PORT) Data Direction Toggle 2 */
+#define REG_PORT_OUT2              (0x41008110) /**< \brief (PORT) Data Output Value 2 */
+#define REG_PORT_OUTCLR2           (0x41008114) /**< \brief (PORT) Data Output Value Clear 2 */
+#define REG_PORT_OUTSET2           (0x41008118) /**< \brief (PORT) Data Output Value Set 2 */
+#define REG_PORT_OUTTGL2           (0x4100811C) /**< \brief (PORT) Data Output Value Toggle 2 */
+#define REG_PORT_IN2               (0x41008120) /**< \brief (PORT) Data Input Value 2 */
+#define REG_PORT_CTRL2             (0x41008124) /**< \brief (PORT) Control 2 */
+#define REG_PORT_WRCONFIG2         (0x41008128) /**< \brief (PORT) Write Configuration 2 */
+#define REG_PORT_EVCTRL2           (0x4100812C) /**< \brief (PORT) Event Input Control 2 */
+#define REG_PORT_PMUX2             (0x41008130) /**< \brief (PORT) Peripheral Multiplexing 2 */
+#define REG_PORT_PINCFG2           (0x41008140) /**< \brief (PORT) Pin Configuration 2 */
+#else
+#define REG_PORT_DIR0              (*(RwReg  *)0x41008000UL) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41008004UL) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0           (*(RwReg  *)0x41008008UL) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100800CUL) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0              (*(RwReg  *)0x41008010UL) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41008014UL) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0           (*(RwReg  *)0x41008018UL) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100801CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0               (*(RoReg  *)0x41008020UL) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0             (*(RwReg  *)0x41008024UL) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41008028UL) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_EVCTRL0           (*(RwReg  *)0x4100802CUL) /**< \brief (PORT) Event Input Control 0 */
+#define REG_PORT_PMUX0             (*(RwReg8 *)0x41008030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0           (*(RwReg8 *)0x41008040UL) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1              (*(RwReg  *)0x41008080UL) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41008084UL) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1           (*(RwReg  *)0x41008088UL) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100808CUL) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1              (*(RwReg  *)0x41008090UL) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41008094UL) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1           (*(RwReg  *)0x41008098UL) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100809CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1               (*(RoReg  *)0x410080A0UL) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1             (*(RwReg  *)0x410080A4UL) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410080A8UL) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_EVCTRL1           (*(RwReg  *)0x410080ACUL) /**< \brief (PORT) Event Input Control 1 */
+#define REG_PORT_PMUX1             (*(RwReg8 *)0x410080B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1           (*(RwReg8 *)0x410080C0UL) /**< \brief (PORT) Pin Configuration 1 */
+#define REG_PORT_DIR2              (*(RwReg  *)0x41008100UL) /**< \brief (PORT) Data Direction 2 */
+#define REG_PORT_DIRCLR2           (*(RwReg  *)0x41008104UL) /**< \brief (PORT) Data Direction Clear 2 */
+#define REG_PORT_DIRSET2           (*(RwReg  *)0x41008108UL) /**< \brief (PORT) Data Direction Set 2 */
+#define REG_PORT_DIRTGL2           (*(RwReg  *)0x4100810CUL) /**< \brief (PORT) Data Direction Toggle 2 */
+#define REG_PORT_OUT2              (*(RwReg  *)0x41008110UL) /**< \brief (PORT) Data Output Value 2 */
+#define REG_PORT_OUTCLR2           (*(RwReg  *)0x41008114UL) /**< \brief (PORT) Data Output Value Clear 2 */
+#define REG_PORT_OUTSET2           (*(RwReg  *)0x41008118UL) /**< \brief (PORT) Data Output Value Set 2 */
+#define REG_PORT_OUTTGL2           (*(RwReg  *)0x4100811CUL) /**< \brief (PORT) Data Output Value Toggle 2 */
+#define REG_PORT_IN2               (*(RoReg  *)0x41008120UL) /**< \brief (PORT) Data Input Value 2 */
+#define REG_PORT_CTRL2             (*(RwReg  *)0x41008124UL) /**< \brief (PORT) Control 2 */
+#define REG_PORT_WRCONFIG2         (*(WoReg  *)0x41008128UL) /**< \brief (PORT) Write Configuration 2 */
+#define REG_PORT_EVCTRL2           (*(RwReg  *)0x4100812CUL) /**< \brief (PORT) Event Input Control 2 */
+#define REG_PORT_PMUX2             (*(RwReg8 *)0x41008130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */
+#define REG_PORT_PINCFG2           (*(RwReg8 *)0x41008140UL) /**< \brief (PORT) Pin Configuration 2 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS                   118     
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DIR_IMPLEMENTED        { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_DRVSTR                 1        // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DRVSTR_IMPLEMENTED     { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_EVENT_IMPLEMENTED      { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_EV_NUM                 4       
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_IMPLEMENTED       { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_ODRAIN                 0        // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_IMPLEMENTED        { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_PIN_IMPLEMENTED        { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXEN_IMPLEMENTED     { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_PPP_IMPLEMENTED        { 0x00000001 } // IOBUS2 implemented?
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PULLEN_IMPLEMENTED     { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
+#define PORT_SLEWLIM                0        // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+
+#endif /* _SAME53_PORT_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pukcc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pukcc.h
new file mode 100644
index 000000000..c205a18f1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/pukcc.h	
@@ -0,0 +1,38 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PUKCC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_PUKCC_INSTANCE_
+#define _SAME53_PUKCC_INSTANCE_
+
+/* ========== Instance parameters for PUKCC peripheral ========== */
+#define PUKCC_CLK_AHB_ID            20      
+#define PUKCC_RAM_ADDR_SIZE         12      
+#define PUKCC_ROM_ADDR_SIZE         16      
+
+#endif /* _SAME53_PUKCC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/qspi.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/qspi.h
new file mode 100644
index 000000000..aae81a934
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/qspi.h	
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief Instance description for QSPI
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_QSPI_INSTANCE_
+#define _SAME53_QSPI_INSTANCE_
+
+/* ========== Register definition for QSPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_QSPI_CTRLA             (0x42003400) /**< \brief (QSPI) Control A */
+#define REG_QSPI_CTRLB             (0x42003404) /**< \brief (QSPI) Control B */
+#define REG_QSPI_BAUD              (0x42003408) /**< \brief (QSPI) Baud Rate */
+#define REG_QSPI_RXDATA            (0x4200340C) /**< \brief (QSPI) Receive Data */
+#define REG_QSPI_TXDATA            (0x42003410) /**< \brief (QSPI) Transmit Data */
+#define REG_QSPI_INTENCLR          (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */
+#define REG_QSPI_INTENSET          (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */
+#define REG_QSPI_INTFLAG           (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */
+#define REG_QSPI_STATUS            (0x42003420) /**< \brief (QSPI) Status Register */
+#define REG_QSPI_INSTRADDR         (0x42003430) /**< \brief (QSPI) Instruction Address */
+#define REG_QSPI_INSTRCTRL         (0x42003434) /**< \brief (QSPI) Instruction Code */
+#define REG_QSPI_INSTRFRAME        (0x42003438) /**< \brief (QSPI) Instruction Frame */
+#define REG_QSPI_SCRAMBCTRL        (0x42003440) /**< \brief (QSPI) Scrambling Mode */
+#define REG_QSPI_SCRAMBKEY         (0x42003444) /**< \brief (QSPI) Scrambling Key */
+#else
+#define REG_QSPI_CTRLA             (*(RwReg  *)0x42003400UL) /**< \brief (QSPI) Control A */
+#define REG_QSPI_CTRLB             (*(RwReg  *)0x42003404UL) /**< \brief (QSPI) Control B */
+#define REG_QSPI_BAUD              (*(RwReg  *)0x42003408UL) /**< \brief (QSPI) Baud Rate */
+#define REG_QSPI_RXDATA            (*(RoReg  *)0x4200340CUL) /**< \brief (QSPI) Receive Data */
+#define REG_QSPI_TXDATA            (*(WoReg  *)0x42003410UL) /**< \brief (QSPI) Transmit Data */
+#define REG_QSPI_INTENCLR          (*(RwReg  *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */
+#define REG_QSPI_INTENSET          (*(RwReg  *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */
+#define REG_QSPI_INTFLAG           (*(RwReg  *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */
+#define REG_QSPI_STATUS            (*(RoReg  *)0x42003420UL) /**< \brief (QSPI) Status Register */
+#define REG_QSPI_INSTRADDR         (*(RwReg  *)0x42003430UL) /**< \brief (QSPI) Instruction Address */
+#define REG_QSPI_INSTRCTRL         (*(RwReg  *)0x42003434UL) /**< \brief (QSPI) Instruction Code */
+#define REG_QSPI_INSTRFRAME        (*(RwReg  *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */
+#define REG_QSPI_SCRAMBCTRL        (*(RwReg  *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */
+#define REG_QSPI_SCRAMBKEY         (*(WoReg  *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for QSPI peripheral ========== */
+#define QSPI_DMAC_ID_RX             83      
+#define QSPI_DMAC_ID_TX             84      
+#define QSPI_HADDR_MSB              23      
+#define QSPI_OCMS                   1       
+
+#endif /* _SAME53_QSPI_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ramecc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ramecc.h
new file mode 100644
index 000000000..76caa6745
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/ramecc.h	
@@ -0,0 +1,54 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RAMECC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_RAMECC_INSTANCE_
+#define _SAME53_RAMECC_INSTANCE_
+
+/* ========== Register definition for RAMECC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RAMECC_INTENCLR        (0x41020000) /**< \brief (RAMECC) Interrupt Enable Clear */
+#define REG_RAMECC_INTENSET        (0x41020001) /**< \brief (RAMECC) Interrupt Enable Set */
+#define REG_RAMECC_INTFLAG         (0x41020002) /**< \brief (RAMECC) Interrupt Flag */
+#define REG_RAMECC_STATUS          (0x41020003) /**< \brief (RAMECC) Status */
+#define REG_RAMECC_ERRADDR         (0x41020004) /**< \brief (RAMECC) Error Address */
+#define REG_RAMECC_DBGCTRL         (0x4102000F) /**< \brief (RAMECC) Debug Control */
+#else
+#define REG_RAMECC_INTENCLR        (*(RwReg8 *)0x41020000UL) /**< \brief (RAMECC) Interrupt Enable Clear */
+#define REG_RAMECC_INTENSET        (*(RwReg8 *)0x41020001UL) /**< \brief (RAMECC) Interrupt Enable Set */
+#define REG_RAMECC_INTFLAG         (*(RwReg8 *)0x41020002UL) /**< \brief (RAMECC) Interrupt Flag */
+#define REG_RAMECC_STATUS          (*(RoReg8 *)0x41020003UL) /**< \brief (RAMECC) Status */
+#define REG_RAMECC_ERRADDR         (*(RoReg  *)0x41020004UL) /**< \brief (RAMECC) Error Address */
+#define REG_RAMECC_DBGCTRL         (*(RwReg8 *)0x4102000FUL) /**< \brief (RAMECC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RAMECC peripheral ========== */
+#define RAMECC_RAMADDR_BITS         13       // Number of RAM address bits
+#define RAMECC_RAMBANK_NUM          4        // Number of RAM banks
+
+#endif /* _SAME53_RAMECC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/rstc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/rstc.h
new file mode 100644
index 000000000..5746f3d94
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/rstc.h	
@@ -0,0 +1,48 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RSTC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_RSTC_INSTANCE_
+#define _SAME53_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_RCAUSE            (0x40000C00) /**< \brief (RSTC) Reset Cause */
+#define REG_RSTC_BKUPEXIT          (0x40000C02) /**< \brief (RSTC) Backup Exit Source */
+#else
+#define REG_RSTC_RCAUSE            (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */
+#define REG_RSTC_BKUPEXIT          (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RSTC peripheral ========== */
+#define RSTC_BACKUP_IMPLEMENTED     1       
+#define RSTC_HIB_IMPLEMENTED        1       
+#define RSTC_NUMBER_OF_EXTWAKE      0        // number of external wakeup line
+#define RSTC_NVMRST_IMPLEMENTED     1       
+
+#endif /* _SAME53_RSTC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/rtc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/rtc.h
new file mode 100644
index 000000000..19f148a14
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/rtc.h	
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_RTC_INSTANCE_
+#define _SAME53_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_DBGCTRL            (0x4000240E) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (0x40002414) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_GP0                (0x40002440) /**< \brief (RTC) General Purpose 0 */
+#define REG_RTC_GP1                (0x40002444) /**< \brief (RTC) General Purpose 1 */
+#define REG_RTC_GP2                (0x40002448) /**< \brief (RTC) General Purpose 2 */
+#define REG_RTC_GP3                (0x4000244C) /**< \brief (RTC) General Purpose 3 */
+#define REG_RTC_TAMPCTRL           (0x40002460) /**< \brief (RTC) Tamper Control */
+#define REG_RTC_TAMPID             (0x40002468) /**< \brief (RTC) Tamper ID */
+#define REG_RTC_BKUP0              (0x40002480) /**< \brief (RTC) Backup 0 */
+#define REG_RTC_BKUP1              (0x40002484) /**< \brief (RTC) Backup 1 */
+#define REG_RTC_BKUP2              (0x40002488) /**< \brief (RTC) Backup 2 */
+#define REG_RTC_BKUP3              (0x4000248C) /**< \brief (RTC) Backup 3 */
+#define REG_RTC_BKUP4              (0x40002490) /**< \brief (RTC) Backup 4 */
+#define REG_RTC_BKUP5              (0x40002494) /**< \brief (RTC) Backup 5 */
+#define REG_RTC_BKUP6              (0x40002498) /**< \brief (RTC) Backup 6 */
+#define REG_RTC_BKUP7              (0x4000249C) /**< \brief (RTC) Backup 7 */
+#define REG_RTC_MODE0_CTRLA        (0x40002400) /**< \brief (RTC) MODE0 Control A */
+#define REG_RTC_MODE0_CTRLB        (0x40002402) /**< \brief (RTC) MODE0 Control B */
+#define REG_RTC_MODE0_EVCTRL       (0x40002404) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_SYNCBUSY     (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
+#define REG_RTC_MODE0_COUNT        (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE0_COMP1        (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */
+#define REG_RTC_MODE0_TIMESTAMP    (0x40002464) /**< \brief (RTC) MODE0 Timestamp */
+#define REG_RTC_MODE1_CTRLA        (0x40002400) /**< \brief (RTC) MODE1 Control A */
+#define REG_RTC_MODE1_CTRLB        (0x40002402) /**< \brief (RTC) MODE1 Control B */
+#define REG_RTC_MODE1_EVCTRL       (0x40002404) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_SYNCBUSY     (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
+#define REG_RTC_MODE1_COUNT        (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE1_COMP2        (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */
+#define REG_RTC_MODE1_COMP3        (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */
+#define REG_RTC_MODE1_TIMESTAMP    (0x40002464) /**< \brief (RTC) MODE1 Timestamp */
+#define REG_RTC_MODE2_CTRLA        (0x40002400) /**< \brief (RTC) MODE2 Control A */
+#define REG_RTC_MODE2_CTRLB        (0x40002402) /**< \brief (RTC) MODE2 Control B */
+#define REG_RTC_MODE2_EVCTRL       (0x40002404) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_SYNCBUSY     (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
+#define REG_RTC_MODE2_CLOCK        (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_TIMESTAMP    (0x40002464) /**< \brief (RTC) MODE2 Timestamp */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
+#define REG_RTC_MODE2_ALARM_MASK1  (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
+#else
+#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR           (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_GP0                (*(RwReg  *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */
+#define REG_RTC_GP1                (*(RwReg  *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */
+#define REG_RTC_GP2                (*(RwReg  *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */
+#define REG_RTC_GP3                (*(RwReg  *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */
+#define REG_RTC_TAMPCTRL           (*(RwReg  *)0x40002460UL) /**< \brief (RTC) Tamper Control */
+#define REG_RTC_TAMPID             (*(RwReg  *)0x40002468UL) /**< \brief (RTC) Tamper ID */
+#define REG_RTC_BKUP0              (*(RwReg  *)0x40002480UL) /**< \brief (RTC) Backup 0 */
+#define REG_RTC_BKUP1              (*(RwReg  *)0x40002484UL) /**< \brief (RTC) Backup 1 */
+#define REG_RTC_BKUP2              (*(RwReg  *)0x40002488UL) /**< \brief (RTC) Backup 2 */
+#define REG_RTC_BKUP3              (*(RwReg  *)0x4000248CUL) /**< \brief (RTC) Backup 3 */
+#define REG_RTC_BKUP4              (*(RwReg  *)0x40002490UL) /**< \brief (RTC) Backup 4 */
+#define REG_RTC_BKUP5              (*(RwReg  *)0x40002494UL) /**< \brief (RTC) Backup 5 */
+#define REG_RTC_BKUP6              (*(RwReg  *)0x40002498UL) /**< \brief (RTC) Backup 6 */
+#define REG_RTC_BKUP7              (*(RwReg  *)0x4000249CUL) /**< \brief (RTC) Backup 7 */
+#define REG_RTC_MODE0_CTRLA        (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
+#define REG_RTC_MODE0_CTRLB        (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */
+#define REG_RTC_MODE0_EVCTRL       (*(RwReg  *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR     (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET     (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG      (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_SYNCBUSY     (*(RoReg  *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
+#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE0_COMP1        (*(RwReg  *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */
+#define REG_RTC_MODE0_TIMESTAMP    (*(RoReg  *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */
+#define REG_RTC_MODE1_CTRLA        (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
+#define REG_RTC_MODE1_CTRLB        (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */
+#define REG_RTC_MODE1_EVCTRL       (*(RwReg  *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR     (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET     (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG      (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_SYNCBUSY     (*(RoReg  *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
+#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER          (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE1_COMP2        (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */
+#define REG_RTC_MODE1_COMP3        (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */
+#define REG_RTC_MODE1_TIMESTAMP    (*(RoReg  *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */
+#define REG_RTC_MODE2_CTRLA        (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
+#define REG_RTC_MODE2_CTRLB        (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */
+#define REG_RTC_MODE2_EVCTRL       (*(RwReg  *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR     (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET     (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG      (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_SYNCBUSY     (*(RoReg  *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
+#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_TIMESTAMP    (*(RoReg  *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg  *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
+#define REG_RTC_MODE2_ALARM_MASK1  (*(RwReg8 *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_DMAC_ID_TIMESTAMP       1        // DMA RTC timestamp trigger
+#define RTC_GPR_NUM                 4        // Number of General-Purpose Registers
+#define RTC_NUM_OF_ALARMS           2        // Number of Alarms
+#define RTC_NUM_OF_BKREGS           8        // Number of Backup Registers
+#define RTC_NUM_OF_COMP16           4        // Number of 16-bit Comparators
+#define RTC_NUM_OF_COMP32           2        // Number of 32-bit Comparators
+#define RTC_NUM_OF_TAMPERS          5        // Number of Tamper Inputs
+#define RTC_PER_NUM                 8        // Number of Periodic Intervals
+
+#endif /* _SAME53_RTC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sdhc0.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sdhc0.h
new file mode 100644
index 000000000..0302bfc73
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sdhc0.h	
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SDHC0
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SDHC0_INSTANCE_
+#define _SAME53_SDHC0_INSTANCE_
+
+/* ========== Register definition for SDHC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SDHC0_SSAR             (0x45000000) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
+#define REG_SDHC0_BSR              (0x45000004) /**< \brief (SDHC0) Block Size */
+#define REG_SDHC0_BCR              (0x45000006) /**< \brief (SDHC0) Block Count */
+#define REG_SDHC0_ARG1R            (0x45000008) /**< \brief (SDHC0) Argument 1 */
+#define REG_SDHC0_TMR              (0x4500000C) /**< \brief (SDHC0) Transfer Mode */
+#define REG_SDHC0_CR               (0x4500000E) /**< \brief (SDHC0) Command */
+#define REG_SDHC0_RR0              (0x45000010) /**< \brief (SDHC0) Response 0 */
+#define REG_SDHC0_RR1              (0x45000014) /**< \brief (SDHC0) Response 1 */
+#define REG_SDHC0_RR2              (0x45000018) /**< \brief (SDHC0) Response 2 */
+#define REG_SDHC0_RR3              (0x4500001C) /**< \brief (SDHC0) Response 3 */
+#define REG_SDHC0_BDPR             (0x45000020) /**< \brief (SDHC0) Buffer Data Port */
+#define REG_SDHC0_PSR              (0x45000024) /**< \brief (SDHC0) Present State */
+#define REG_SDHC0_HC1R             (0x45000028) /**< \brief (SDHC0) Host Control 1 */
+#define REG_SDHC0_PCR              (0x45000029) /**< \brief (SDHC0) Power Control */
+#define REG_SDHC0_BGCR             (0x4500002A) /**< \brief (SDHC0) Block Gap Control */
+#define REG_SDHC0_WCR              (0x4500002B) /**< \brief (SDHC0) Wakeup Control */
+#define REG_SDHC0_CCR              (0x4500002C) /**< \brief (SDHC0) Clock Control */
+#define REG_SDHC0_TCR              (0x4500002E) /**< \brief (SDHC0) Timeout Control */
+#define REG_SDHC0_SRR              (0x4500002F) /**< \brief (SDHC0) Software Reset */
+#define REG_SDHC0_NISTR            (0x45000030) /**< \brief (SDHC0) Normal Interrupt Status */
+#define REG_SDHC0_EISTR            (0x45000032) /**< \brief (SDHC0) Error Interrupt Status */
+#define REG_SDHC0_NISTER           (0x45000034) /**< \brief (SDHC0) Normal Interrupt Status Enable */
+#define REG_SDHC0_EISTER           (0x45000036) /**< \brief (SDHC0) Error Interrupt Status Enable */
+#define REG_SDHC0_NISIER           (0x45000038) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
+#define REG_SDHC0_EISIER           (0x4500003A) /**< \brief (SDHC0) Error Interrupt Signal Enable */
+#define REG_SDHC0_ACESR            (0x4500003C) /**< \brief (SDHC0) Auto CMD Error Status */
+#define REG_SDHC0_HC2R             (0x4500003E) /**< \brief (SDHC0) Host Control 2 */
+#define REG_SDHC0_CA0R             (0x45000040) /**< \brief (SDHC0) Capabilities 0 */
+#define REG_SDHC0_CA1R             (0x45000044) /**< \brief (SDHC0) Capabilities 1 */
+#define REG_SDHC0_MCCAR            (0x45000048) /**< \brief (SDHC0) Maximum Current Capabilities */
+#define REG_SDHC0_FERACES          (0x45000050) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
+#define REG_SDHC0_FEREIS           (0x45000052) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
+#define REG_SDHC0_AESR             (0x45000054) /**< \brief (SDHC0) ADMA Error Status */
+#define REG_SDHC0_ASAR0            (0x45000058) /**< \brief (SDHC0) ADMA System Address 0 */
+#define REG_SDHC0_PVR0             (0x45000060) /**< \brief (SDHC0) Preset Value 0 */
+#define REG_SDHC0_PVR1             (0x45000062) /**< \brief (SDHC0) Preset Value 1 */
+#define REG_SDHC0_PVR2             (0x45000064) /**< \brief (SDHC0) Preset Value 2 */
+#define REG_SDHC0_PVR3             (0x45000066) /**< \brief (SDHC0) Preset Value 3 */
+#define REG_SDHC0_PVR4             (0x45000068) /**< \brief (SDHC0) Preset Value 4 */
+#define REG_SDHC0_PVR5             (0x4500006A) /**< \brief (SDHC0) Preset Value 5 */
+#define REG_SDHC0_PVR6             (0x4500006C) /**< \brief (SDHC0) Preset Value 6 */
+#define REG_SDHC0_PVR7             (0x4500006E) /**< \brief (SDHC0) Preset Value 7 */
+#define REG_SDHC0_SISR             (0x450000FC) /**< \brief (SDHC0) Slot Interrupt Status */
+#define REG_SDHC0_HCVR             (0x450000FE) /**< \brief (SDHC0) Host Controller Version */
+#define REG_SDHC0_MC1R             (0x45000204) /**< \brief (SDHC0) MMC Control 1 */
+#define REG_SDHC0_MC2R             (0x45000205) /**< \brief (SDHC0) MMC Control 2 */
+#define REG_SDHC0_ACR              (0x45000208) /**< \brief (SDHC0) AHB Control */
+#define REG_SDHC0_CC2R             (0x4500020C) /**< \brief (SDHC0) Clock Control 2 */
+#define REG_SDHC0_CACR             (0x45000230) /**< \brief (SDHC0) Capabilities Control */
+#define REG_SDHC0_DBGR             (0x45000234) /**< \brief (SDHC0) Debug */
+#else
+#define REG_SDHC0_SSAR             (*(RwReg  *)0x45000000UL) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
+#define REG_SDHC0_BSR              (*(RwReg16*)0x45000004UL) /**< \brief (SDHC0) Block Size */
+#define REG_SDHC0_BCR              (*(RwReg16*)0x45000006UL) /**< \brief (SDHC0) Block Count */
+#define REG_SDHC0_ARG1R            (*(RwReg  *)0x45000008UL) /**< \brief (SDHC0) Argument 1 */
+#define REG_SDHC0_TMR              (*(RwReg16*)0x4500000CUL) /**< \brief (SDHC0) Transfer Mode */
+#define REG_SDHC0_CR               (*(RwReg16*)0x4500000EUL) /**< \brief (SDHC0) Command */
+#define REG_SDHC0_RR0              (*(RoReg  *)0x45000010UL) /**< \brief (SDHC0) Response 0 */
+#define REG_SDHC0_RR1              (*(RoReg  *)0x45000014UL) /**< \brief (SDHC0) Response 1 */
+#define REG_SDHC0_RR2              (*(RoReg  *)0x45000018UL) /**< \brief (SDHC0) Response 2 */
+#define REG_SDHC0_RR3              (*(RoReg  *)0x4500001CUL) /**< \brief (SDHC0) Response 3 */
+#define REG_SDHC0_BDPR             (*(RwReg  *)0x45000020UL) /**< \brief (SDHC0) Buffer Data Port */
+#define REG_SDHC0_PSR              (*(RoReg  *)0x45000024UL) /**< \brief (SDHC0) Present State */
+#define REG_SDHC0_HC1R             (*(RwReg8 *)0x45000028UL) /**< \brief (SDHC0) Host Control 1 */
+#define REG_SDHC0_PCR              (*(RwReg8 *)0x45000029UL) /**< \brief (SDHC0) Power Control */
+#define REG_SDHC0_BGCR             (*(RwReg8 *)0x4500002AUL) /**< \brief (SDHC0) Block Gap Control */
+#define REG_SDHC0_WCR              (*(RwReg8 *)0x4500002BUL) /**< \brief (SDHC0) Wakeup Control */
+#define REG_SDHC0_CCR              (*(RwReg16*)0x4500002CUL) /**< \brief (SDHC0) Clock Control */
+#define REG_SDHC0_TCR              (*(RwReg8 *)0x4500002EUL) /**< \brief (SDHC0) Timeout Control */
+#define REG_SDHC0_SRR              (*(RwReg8 *)0x4500002FUL) /**< \brief (SDHC0) Software Reset */
+#define REG_SDHC0_NISTR            (*(RwReg16*)0x45000030UL) /**< \brief (SDHC0) Normal Interrupt Status */
+#define REG_SDHC0_EISTR            (*(RwReg16*)0x45000032UL) /**< \brief (SDHC0) Error Interrupt Status */
+#define REG_SDHC0_NISTER           (*(RwReg16*)0x45000034UL) /**< \brief (SDHC0) Normal Interrupt Status Enable */
+#define REG_SDHC0_EISTER           (*(RwReg16*)0x45000036UL) /**< \brief (SDHC0) Error Interrupt Status Enable */
+#define REG_SDHC0_NISIER           (*(RwReg16*)0x45000038UL) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
+#define REG_SDHC0_EISIER           (*(RwReg16*)0x4500003AUL) /**< \brief (SDHC0) Error Interrupt Signal Enable */
+#define REG_SDHC0_ACESR            (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Status */
+#define REG_SDHC0_HC2R             (*(RwReg16*)0x4500003EUL) /**< \brief (SDHC0) Host Control 2 */
+#define REG_SDHC0_CA0R             (*(RoReg  *)0x45000040UL) /**< \brief (SDHC0) Capabilities 0 */
+#define REG_SDHC0_CA1R             (*(RoReg  *)0x45000044UL) /**< \brief (SDHC0) Capabilities 1 */
+#define REG_SDHC0_MCCAR            (*(RoReg  *)0x45000048UL) /**< \brief (SDHC0) Maximum Current Capabilities */
+#define REG_SDHC0_FERACES          (*(WoReg16*)0x45000050UL) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
+#define REG_SDHC0_FEREIS           (*(WoReg16*)0x45000052UL) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
+#define REG_SDHC0_AESR             (*(RoReg8 *)0x45000054UL) /**< \brief (SDHC0) ADMA Error Status */
+#define REG_SDHC0_ASAR0            (*(RwReg  *)0x45000058UL) /**< \brief (SDHC0) ADMA System Address 0 */
+#define REG_SDHC0_PVR0             (*(RwReg16*)0x45000060UL) /**< \brief (SDHC0) Preset Value 0 */
+#define REG_SDHC0_PVR1             (*(RwReg16*)0x45000062UL) /**< \brief (SDHC0) Preset Value 1 */
+#define REG_SDHC0_PVR2             (*(RwReg16*)0x45000064UL) /**< \brief (SDHC0) Preset Value 2 */
+#define REG_SDHC0_PVR3             (*(RwReg16*)0x45000066UL) /**< \brief (SDHC0) Preset Value 3 */
+#define REG_SDHC0_PVR4             (*(RwReg16*)0x45000068UL) /**< \brief (SDHC0) Preset Value 4 */
+#define REG_SDHC0_PVR5             (*(RwReg16*)0x4500006AUL) /**< \brief (SDHC0) Preset Value 5 */
+#define REG_SDHC0_PVR6             (*(RwReg16*)0x4500006CUL) /**< \brief (SDHC0) Preset Value 6 */
+#define REG_SDHC0_PVR7             (*(RwReg16*)0x4500006EUL) /**< \brief (SDHC0) Preset Value 7 */
+#define REG_SDHC0_SISR             (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Status */
+#define REG_SDHC0_HCVR             (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Version */
+#define REG_SDHC0_MC1R             (*(RwReg8 *)0x45000204UL) /**< \brief (SDHC0) MMC Control 1 */
+#define REG_SDHC0_MC2R             (*(WoReg8 *)0x45000205UL) /**< \brief (SDHC0) MMC Control 2 */
+#define REG_SDHC0_ACR              (*(RwReg  *)0x45000208UL) /**< \brief (SDHC0) AHB Control */
+#define REG_SDHC0_CC2R             (*(RwReg  *)0x4500020CUL) /**< \brief (SDHC0) Clock Control 2 */
+#define REG_SDHC0_CACR             (*(RwReg  *)0x45000230UL) /**< \brief (SDHC0) Capabilities Control */
+#define REG_SDHC0_DBGR             (*(RwReg8 *)0x45000234UL) /**< \brief (SDHC0) Debug */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SDHC0 peripheral ========== */
+#define SDHC0_CARD_DATA_SIZE        4       
+#define SDHC0_CLK_AHB_ID            15      
+#define SDHC0_GCLK_ID               45      
+#define SDHC0_GCLK_ID_SLOW          3       
+#define SDHC0_NB_OF_DEVICES         1       
+#define SDHC0_NB_REG_PVR            8       
+#define SDHC0_NB_REG_RR             4       
+
+#endif /* _SAME53_SDHC0_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sdhc1.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sdhc1.h
new file mode 100644
index 000000000..c16f83ec9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sdhc1.h	
@@ -0,0 +1,147 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SDHC1
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SDHC1_INSTANCE_
+#define _SAME53_SDHC1_INSTANCE_
+
+/* ========== Register definition for SDHC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SDHC1_SSAR             (0x46000000) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
+#define REG_SDHC1_BSR              (0x46000004) /**< \brief (SDHC1) Block Size */
+#define REG_SDHC1_BCR              (0x46000006) /**< \brief (SDHC1) Block Count */
+#define REG_SDHC1_ARG1R            (0x46000008) /**< \brief (SDHC1) Argument 1 */
+#define REG_SDHC1_TMR              (0x4600000C) /**< \brief (SDHC1) Transfer Mode */
+#define REG_SDHC1_CR               (0x4600000E) /**< \brief (SDHC1) Command */
+#define REG_SDHC1_RR0              (0x46000010) /**< \brief (SDHC1) Response 0 */
+#define REG_SDHC1_RR1              (0x46000014) /**< \brief (SDHC1) Response 1 */
+#define REG_SDHC1_RR2              (0x46000018) /**< \brief (SDHC1) Response 2 */
+#define REG_SDHC1_RR3              (0x4600001C) /**< \brief (SDHC1) Response 3 */
+#define REG_SDHC1_BDPR             (0x46000020) /**< \brief (SDHC1) Buffer Data Port */
+#define REG_SDHC1_PSR              (0x46000024) /**< \brief (SDHC1) Present State */
+#define REG_SDHC1_HC1R             (0x46000028) /**< \brief (SDHC1) Host Control 1 */
+#define REG_SDHC1_PCR              (0x46000029) /**< \brief (SDHC1) Power Control */
+#define REG_SDHC1_BGCR             (0x4600002A) /**< \brief (SDHC1) Block Gap Control */
+#define REG_SDHC1_WCR              (0x4600002B) /**< \brief (SDHC1) Wakeup Control */
+#define REG_SDHC1_CCR              (0x4600002C) /**< \brief (SDHC1) Clock Control */
+#define REG_SDHC1_TCR              (0x4600002E) /**< \brief (SDHC1) Timeout Control */
+#define REG_SDHC1_SRR              (0x4600002F) /**< \brief (SDHC1) Software Reset */
+#define REG_SDHC1_NISTR            (0x46000030) /**< \brief (SDHC1) Normal Interrupt Status */
+#define REG_SDHC1_EISTR            (0x46000032) /**< \brief (SDHC1) Error Interrupt Status */
+#define REG_SDHC1_NISTER           (0x46000034) /**< \brief (SDHC1) Normal Interrupt Status Enable */
+#define REG_SDHC1_EISTER           (0x46000036) /**< \brief (SDHC1) Error Interrupt Status Enable */
+#define REG_SDHC1_NISIER           (0x46000038) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
+#define REG_SDHC1_EISIER           (0x4600003A) /**< \brief (SDHC1) Error Interrupt Signal Enable */
+#define REG_SDHC1_ACESR            (0x4600003C) /**< \brief (SDHC1) Auto CMD Error Status */
+#define REG_SDHC1_HC2R             (0x4600003E) /**< \brief (SDHC1) Host Control 2 */
+#define REG_SDHC1_CA0R             (0x46000040) /**< \brief (SDHC1) Capabilities 0 */
+#define REG_SDHC1_CA1R             (0x46000044) /**< \brief (SDHC1) Capabilities 1 */
+#define REG_SDHC1_MCCAR            (0x46000048) /**< \brief (SDHC1) Maximum Current Capabilities */
+#define REG_SDHC1_FERACES          (0x46000050) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
+#define REG_SDHC1_FEREIS           (0x46000052) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
+#define REG_SDHC1_AESR             (0x46000054) /**< \brief (SDHC1) ADMA Error Status */
+#define REG_SDHC1_ASAR0            (0x46000058) /**< \brief (SDHC1) ADMA System Address 0 */
+#define REG_SDHC1_PVR0             (0x46000060) /**< \brief (SDHC1) Preset Value 0 */
+#define REG_SDHC1_PVR1             (0x46000062) /**< \brief (SDHC1) Preset Value 1 */
+#define REG_SDHC1_PVR2             (0x46000064) /**< \brief (SDHC1) Preset Value 2 */
+#define REG_SDHC1_PVR3             (0x46000066) /**< \brief (SDHC1) Preset Value 3 */
+#define REG_SDHC1_PVR4             (0x46000068) /**< \brief (SDHC1) Preset Value 4 */
+#define REG_SDHC1_PVR5             (0x4600006A) /**< \brief (SDHC1) Preset Value 5 */
+#define REG_SDHC1_PVR6             (0x4600006C) /**< \brief (SDHC1) Preset Value 6 */
+#define REG_SDHC1_PVR7             (0x4600006E) /**< \brief (SDHC1) Preset Value 7 */
+#define REG_SDHC1_SISR             (0x460000FC) /**< \brief (SDHC1) Slot Interrupt Status */
+#define REG_SDHC1_HCVR             (0x460000FE) /**< \brief (SDHC1) Host Controller Version */
+#define REG_SDHC1_MC1R             (0x46000204) /**< \brief (SDHC1) MMC Control 1 */
+#define REG_SDHC1_MC2R             (0x46000205) /**< \brief (SDHC1) MMC Control 2 */
+#define REG_SDHC1_ACR              (0x46000208) /**< \brief (SDHC1) AHB Control */
+#define REG_SDHC1_CC2R             (0x4600020C) /**< \brief (SDHC1) Clock Control 2 */
+#define REG_SDHC1_CACR             (0x46000230) /**< \brief (SDHC1) Capabilities Control */
+#define REG_SDHC1_DBGR             (0x46000234) /**< \brief (SDHC1) Debug */
+#else
+#define REG_SDHC1_SSAR             (*(RwReg  *)0x46000000UL) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
+#define REG_SDHC1_BSR              (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */
+#define REG_SDHC1_BCR              (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */
+#define REG_SDHC1_ARG1R            (*(RwReg  *)0x46000008UL) /**< \brief (SDHC1) Argument 1 */
+#define REG_SDHC1_TMR              (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */
+#define REG_SDHC1_CR               (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */
+#define REG_SDHC1_RR0              (*(RoReg  *)0x46000010UL) /**< \brief (SDHC1) Response 0 */
+#define REG_SDHC1_RR1              (*(RoReg  *)0x46000014UL) /**< \brief (SDHC1) Response 1 */
+#define REG_SDHC1_RR2              (*(RoReg  *)0x46000018UL) /**< \brief (SDHC1) Response 2 */
+#define REG_SDHC1_RR3              (*(RoReg  *)0x4600001CUL) /**< \brief (SDHC1) Response 3 */
+#define REG_SDHC1_BDPR             (*(RwReg  *)0x46000020UL) /**< \brief (SDHC1) Buffer Data Port */
+#define REG_SDHC1_PSR              (*(RoReg  *)0x46000024UL) /**< \brief (SDHC1) Present State */
+#define REG_SDHC1_HC1R             (*(RwReg8 *)0x46000028UL) /**< \brief (SDHC1) Host Control 1 */
+#define REG_SDHC1_PCR              (*(RwReg8 *)0x46000029UL) /**< \brief (SDHC1) Power Control */
+#define REG_SDHC1_BGCR             (*(RwReg8 *)0x4600002AUL) /**< \brief (SDHC1) Block Gap Control */
+#define REG_SDHC1_WCR              (*(RwReg8 *)0x4600002BUL) /**< \brief (SDHC1) Wakeup Control */
+#define REG_SDHC1_CCR              (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */
+#define REG_SDHC1_TCR              (*(RwReg8 *)0x4600002EUL) /**< \brief (SDHC1) Timeout Control */
+#define REG_SDHC1_SRR              (*(RwReg8 *)0x4600002FUL) /**< \brief (SDHC1) Software Reset */
+#define REG_SDHC1_NISTR            (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt Status */
+#define REG_SDHC1_EISTR            (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt Status */
+#define REG_SDHC1_NISTER           (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt Status Enable */
+#define REG_SDHC1_EISTER           (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt Status Enable */
+#define REG_SDHC1_NISIER           (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
+#define REG_SDHC1_EISIER           (*(RwReg16*)0x4600003AUL) /**< \brief (SDHC1) Error Interrupt Signal Enable */
+#define REG_SDHC1_ACESR            (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Status */
+#define REG_SDHC1_HC2R             (*(RwReg16*)0x4600003EUL) /**< \brief (SDHC1) Host Control 2 */
+#define REG_SDHC1_CA0R             (*(RoReg  *)0x46000040UL) /**< \brief (SDHC1) Capabilities 0 */
+#define REG_SDHC1_CA1R             (*(RoReg  *)0x46000044UL) /**< \brief (SDHC1) Capabilities 1 */
+#define REG_SDHC1_MCCAR            (*(RoReg  *)0x46000048UL) /**< \brief (SDHC1) Maximum Current Capabilities */
+#define REG_SDHC1_FERACES          (*(WoReg16*)0x46000050UL) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
+#define REG_SDHC1_FEREIS           (*(WoReg16*)0x46000052UL) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
+#define REG_SDHC1_AESR             (*(RoReg8 *)0x46000054UL) /**< \brief (SDHC1) ADMA Error Status */
+#define REG_SDHC1_ASAR0            (*(RwReg  *)0x46000058UL) /**< \brief (SDHC1) ADMA System Address 0 */
+#define REG_SDHC1_PVR0             (*(RwReg16*)0x46000060UL) /**< \brief (SDHC1) Preset Value 0 */
+#define REG_SDHC1_PVR1             (*(RwReg16*)0x46000062UL) /**< \brief (SDHC1) Preset Value 1 */
+#define REG_SDHC1_PVR2             (*(RwReg16*)0x46000064UL) /**< \brief (SDHC1) Preset Value 2 */
+#define REG_SDHC1_PVR3             (*(RwReg16*)0x46000066UL) /**< \brief (SDHC1) Preset Value 3 */
+#define REG_SDHC1_PVR4             (*(RwReg16*)0x46000068UL) /**< \brief (SDHC1) Preset Value 4 */
+#define REG_SDHC1_PVR5             (*(RwReg16*)0x4600006AUL) /**< \brief (SDHC1) Preset Value 5 */
+#define REG_SDHC1_PVR6             (*(RwReg16*)0x4600006CUL) /**< \brief (SDHC1) Preset Value 6 */
+#define REG_SDHC1_PVR7             (*(RwReg16*)0x4600006EUL) /**< \brief (SDHC1) Preset Value 7 */
+#define REG_SDHC1_SISR             (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Status */
+#define REG_SDHC1_HCVR             (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Version */
+#define REG_SDHC1_MC1R             (*(RwReg8 *)0x46000204UL) /**< \brief (SDHC1) MMC Control 1 */
+#define REG_SDHC1_MC2R             (*(WoReg8 *)0x46000205UL) /**< \brief (SDHC1) MMC Control 2 */
+#define REG_SDHC1_ACR              (*(RwReg  *)0x46000208UL) /**< \brief (SDHC1) AHB Control */
+#define REG_SDHC1_CC2R             (*(RwReg  *)0x4600020CUL) /**< \brief (SDHC1) Clock Control 2 */
+#define REG_SDHC1_CACR             (*(RwReg  *)0x46000230UL) /**< \brief (SDHC1) Capabilities Control */
+#define REG_SDHC1_DBGR             (*(RwReg8 *)0x46000234UL) /**< \brief (SDHC1) Debug */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SDHC1 peripheral ========== */
+#define SDHC1_CARD_DATA_SIZE        4       
+#define SDHC1_CLK_AHB_ID            16      
+#define SDHC1_GCLK_ID               46      
+#define SDHC1_GCLK_ID_SLOW          3       
+#define SDHC1_NB_OF_DEVICES         1       
+#define SDHC1_NB_REG_PVR            8       
+#define SDHC1_NB_REG_RR             4       
+
+#endif /* _SAME53_SDHC1_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom0.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom0.h
new file mode 100644
index 000000000..562cc26c9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom0.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM0_INSTANCE_
+#define _SAME53_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA     (0x40003000) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (0x40003004) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_CTRLC     (0x40003008) /**< \brief (SERCOM0) I2CM Control C */
+#define REG_SERCOM0_I2CM_BAUD      (0x4000300C) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (0x40003014) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (0x40003016) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (0x40003018) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (0x4000301A) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (0x4000301C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR      (0x40003024) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (0x40003028) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (0x40003030) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (0x40003000) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (0x40003004) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_CTRLC     (0x40003008) /**< \brief (SERCOM0) I2CS Control C */
+#define REG_SERCOM0_I2CS_INTENCLR  (0x40003014) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (0x40003016) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (0x40003018) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (0x4000301A) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (0x4000301C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_LENGTH    (0x40003022) /**< \brief (SERCOM0) I2CS Length */
+#define REG_SERCOM0_I2CS_ADDR      (0x40003024) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (0x40003028) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (0x40003000) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (0x40003004) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_CTRLC      (0x40003008) /**< \brief (SERCOM0) SPI Control C */
+#define REG_SERCOM0_SPI_BAUD       (0x4000300C) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (0x40003014) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (0x40003016) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (0x40003018) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (0x4000301A) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (0x4000301C) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_LENGTH     (0x40003022) /**< \brief (SERCOM0) SPI Length */
+#define REG_SERCOM0_SPI_ADDR       (0x40003024) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (0x40003028) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (0x40003030) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (0x40003000) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (0x40003004) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_CTRLC    (0x40003008) /**< \brief (SERCOM0) USART Control C */
+#define REG_SERCOM0_USART_BAUD     (0x4000300C) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (0x4000300E) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x40003014) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x40003016) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (0x40003018) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (0x4000301A) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_RXERRCNT (0x40003020) /**< \brief (SERCOM0) USART Receive Error Count */
+#define REG_SERCOM0_USART_LENGTH   (0x40003022) /**< \brief (SERCOM0) USART Length */
+#define REG_SERCOM0_USART_DATA     (0x40003028) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (0x40003030) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_CTRLC     (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) I2CM Control C */
+#define REG_SERCOM0_I2CM_BAUD      (*(RwReg  *)0x4000300CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY  (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR      (*(RwReg  *)0x40003024UL) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA      (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_CTRLC     (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) I2CS Control C */
+#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY  (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_LENGTH    (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) I2CS Length */
+#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x40003024UL) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA      (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_CTRLC      (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) SPI Control C */
+#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4000300CUL) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY   (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_LENGTH     (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) SPI Length */
+#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x40003024UL) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA       (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_CTRLC    (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) USART Control C */
+#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4000300CUL) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL     (*(RwReg8 *)0x4000300EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x40003020UL) /**< \brief (SERCOM0) USART Receive Error Count */
+#define REG_SERCOM0_USART_LENGTH   (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) USART Length */
+#define REG_SERCOM0_USART_DATA     (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM0_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM0_DMA                 1        // DMA support implemented?
+#define SERCOM0_DMAC_ID_RX          4        // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX          5        // Index of DMA TX trigger
+#define SERCOM0_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM0_GCLK_ID_CORE        7       
+#define SERCOM0_GCLK_ID_SLOW        3       
+#define SERCOM0_INT_MSB             6       
+#define SERCOM0_I2CM                1        // I2C Master mode implemented?
+#define SERCOM0_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM0_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM0_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM0_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM0_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM0_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM0_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM0_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM0_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM0_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM0_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM0_PMSB                3       
+#define SERCOM0_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM0_SE_CNT              1        // SE counter included?
+#define SERCOM0_SPI                 1        // SPI mode implemented?
+#define SERCOM0_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM0_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM0_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM0_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM0_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM0_USART               1        // USART mode implemented?
+#define SERCOM0_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM0_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM0_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM0_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM0_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM0_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM0_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM0_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM0_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM0_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM0_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom1.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom1.h
new file mode 100644
index 000000000..fa7a3e107
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom1.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM1_INSTANCE_
+#define _SAME53_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA     (0x40003400) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (0x40003404) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_CTRLC     (0x40003408) /**< \brief (SERCOM1) I2CM Control C */
+#define REG_SERCOM1_I2CM_BAUD      (0x4000340C) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (0x40003414) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (0x40003416) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (0x40003418) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (0x4000341A) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (0x4000341C) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR      (0x40003424) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (0x40003428) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (0x40003430) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (0x40003400) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (0x40003404) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_CTRLC     (0x40003408) /**< \brief (SERCOM1) I2CS Control C */
+#define REG_SERCOM1_I2CS_INTENCLR  (0x40003414) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (0x40003416) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (0x40003418) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (0x4000341A) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (0x4000341C) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_LENGTH    (0x40003422) /**< \brief (SERCOM1) I2CS Length */
+#define REG_SERCOM1_I2CS_ADDR      (0x40003424) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (0x40003428) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (0x40003400) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (0x40003404) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_CTRLC      (0x40003408) /**< \brief (SERCOM1) SPI Control C */
+#define REG_SERCOM1_SPI_BAUD       (0x4000340C) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (0x40003414) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (0x40003416) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (0x40003418) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (0x4000341A) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (0x4000341C) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_LENGTH     (0x40003422) /**< \brief (SERCOM1) SPI Length */
+#define REG_SERCOM1_SPI_ADDR       (0x40003424) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (0x40003428) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (0x40003430) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (0x40003400) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (0x40003404) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_CTRLC    (0x40003408) /**< \brief (SERCOM1) USART Control C */
+#define REG_SERCOM1_USART_BAUD     (0x4000340C) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (0x4000340E) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x40003414) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x40003416) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (0x40003418) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (0x4000341A) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_RXERRCNT (0x40003420) /**< \brief (SERCOM1) USART Receive Error Count */
+#define REG_SERCOM1_USART_LENGTH   (0x40003422) /**< \brief (SERCOM1) USART Length */
+#define REG_SERCOM1_USART_DATA     (0x40003428) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (0x40003430) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_CTRLC     (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) I2CM Control C */
+#define REG_SERCOM1_I2CM_BAUD      (*(RwReg  *)0x4000340CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY  (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR      (*(RwReg  *)0x40003424UL) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA      (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_CTRLC     (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) I2CS Control C */
+#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY  (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_LENGTH    (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) I2CS Length */
+#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x40003424UL) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA      (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_CTRLC      (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) SPI Control C */
+#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x4000340CUL) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY   (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_LENGTH     (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) SPI Length */
+#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x40003424UL) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA       (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_CTRLC    (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) USART Control C */
+#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x4000340CUL) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL     (*(RwReg8 *)0x4000340EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL) /**< \brief (SERCOM1) USART Receive Error Count */
+#define REG_SERCOM1_USART_LENGTH   (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) USART Length */
+#define REG_SERCOM1_USART_DATA     (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM1_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM1_DMA                 1        // DMA support implemented?
+#define SERCOM1_DMAC_ID_RX          6        // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX          7        // Index of DMA TX trigger
+#define SERCOM1_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM1_GCLK_ID_CORE        8       
+#define SERCOM1_GCLK_ID_SLOW        3       
+#define SERCOM1_INT_MSB             6       
+#define SERCOM1_I2CM                1        // I2C Master mode implemented?
+#define SERCOM1_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM1_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM1_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM1_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM1_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM1_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM1_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM1_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM1_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM1_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM1_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM1_PMSB                3       
+#define SERCOM1_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM1_SE_CNT              1        // SE counter included?
+#define SERCOM1_SPI                 1        // SPI mode implemented?
+#define SERCOM1_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM1_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM1_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM1_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM1_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM1_USART               1        // USART mode implemented?
+#define SERCOM1_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM1_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM1_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM1_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM1_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM1_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM1_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM1_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM1_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM1_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM1_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom2.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom2.h
new file mode 100644
index 000000000..2dc214dfb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom2.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM2_INSTANCE_
+#define _SAME53_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA     (0x41012000) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (0x41012004) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_CTRLC     (0x41012008) /**< \brief (SERCOM2) I2CM Control C */
+#define REG_SERCOM2_I2CM_BAUD      (0x4101200C) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (0x41012014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (0x41012016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (0x41012018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (0x4101201A) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (0x4101201C) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR      (0x41012024) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (0x41012028) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (0x41012030) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (0x41012000) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (0x41012004) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_CTRLC     (0x41012008) /**< \brief (SERCOM2) I2CS Control C */
+#define REG_SERCOM2_I2CS_INTENCLR  (0x41012014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (0x41012016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (0x41012018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (0x4101201A) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (0x4101201C) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_LENGTH    (0x41012022) /**< \brief (SERCOM2) I2CS Length */
+#define REG_SERCOM2_I2CS_ADDR      (0x41012024) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (0x41012028) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (0x41012000) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (0x41012004) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_CTRLC      (0x41012008) /**< \brief (SERCOM2) SPI Control C */
+#define REG_SERCOM2_SPI_BAUD       (0x4101200C) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (0x41012014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (0x41012016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (0x41012018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (0x4101201A) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (0x4101201C) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_LENGTH     (0x41012022) /**< \brief (SERCOM2) SPI Length */
+#define REG_SERCOM2_SPI_ADDR       (0x41012024) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (0x41012028) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (0x41012030) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (0x41012000) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (0x41012004) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_CTRLC    (0x41012008) /**< \brief (SERCOM2) USART Control C */
+#define REG_SERCOM2_USART_BAUD     (0x4101200C) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (0x4101200E) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x41012014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x41012016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (0x41012018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (0x4101201A) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4101201C) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_RXERRCNT (0x41012020) /**< \brief (SERCOM2) USART Receive Error Count */
+#define REG_SERCOM2_USART_LENGTH   (0x41012022) /**< \brief (SERCOM2) USART Length */
+#define REG_SERCOM2_USART_DATA     (0x41012028) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (0x41012030) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_CTRLC     (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) I2CM Control C */
+#define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4101200CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x41012024UL) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA      (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_CTRLC     (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) I2CS Control C */
+#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_LENGTH    (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) I2CS Length */
+#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x41012024UL) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA      (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_CTRLC      (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) SPI Control C */
+#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4101200CUL) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_LENGTH     (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) SPI Length */
+#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x41012024UL) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_CTRLC    (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) USART Control C */
+#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4101200CUL) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4101200EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x41012020UL) /**< \brief (SERCOM2) USART Receive Error Count */
+#define REG_SERCOM2_USART_LENGTH   (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) USART Length */
+#define REG_SERCOM2_USART_DATA     (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM2_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM2_DMA                 1        // DMA support implemented?
+#define SERCOM2_DMAC_ID_RX          8        // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX          9        // Index of DMA TX trigger
+#define SERCOM2_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM2_GCLK_ID_CORE        23      
+#define SERCOM2_GCLK_ID_SLOW        3       
+#define SERCOM2_INT_MSB             6       
+#define SERCOM2_I2CM                1        // I2C Master mode implemented?
+#define SERCOM2_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM2_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM2_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM2_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM2_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM2_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM2_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM2_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM2_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM2_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM2_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM2_PMSB                3       
+#define SERCOM2_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM2_SE_CNT              1        // SE counter included?
+#define SERCOM2_SPI                 1        // SPI mode implemented?
+#define SERCOM2_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM2_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM2_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM2_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM2_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM2_USART               1        // USART mode implemented?
+#define SERCOM2_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM2_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM2_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM2_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM2_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM2_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM2_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM2_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM2_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM2_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM2_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom3.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom3.h
new file mode 100644
index 000000000..62515aae9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom3.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM3_INSTANCE_
+#define _SAME53_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA     (0x41014000) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (0x41014004) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_CTRLC     (0x41014008) /**< \brief (SERCOM3) I2CM Control C */
+#define REG_SERCOM3_I2CM_BAUD      (0x4101400C) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (0x41014014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (0x41014016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (0x41014018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (0x4101401A) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (0x4101401C) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR      (0x41014024) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (0x41014028) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (0x41014030) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (0x41014000) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (0x41014004) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_CTRLC     (0x41014008) /**< \brief (SERCOM3) I2CS Control C */
+#define REG_SERCOM3_I2CS_INTENCLR  (0x41014014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (0x41014016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (0x41014018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (0x4101401A) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (0x4101401C) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_LENGTH    (0x41014022) /**< \brief (SERCOM3) I2CS Length */
+#define REG_SERCOM3_I2CS_ADDR      (0x41014024) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (0x41014028) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (0x41014000) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (0x41014004) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_CTRLC      (0x41014008) /**< \brief (SERCOM3) SPI Control C */
+#define REG_SERCOM3_SPI_BAUD       (0x4101400C) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (0x41014014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (0x41014016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (0x41014018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (0x4101401A) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (0x4101401C) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_LENGTH     (0x41014022) /**< \brief (SERCOM3) SPI Length */
+#define REG_SERCOM3_SPI_ADDR       (0x41014024) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (0x41014028) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (0x41014030) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (0x41014000) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (0x41014004) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_CTRLC    (0x41014008) /**< \brief (SERCOM3) USART Control C */
+#define REG_SERCOM3_USART_BAUD     (0x4101400C) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (0x4101400E) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x41014014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x41014016) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (0x41014018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (0x4101401A) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4101401C) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_RXERRCNT (0x41014020) /**< \brief (SERCOM3) USART Receive Error Count */
+#define REG_SERCOM3_USART_LENGTH   (0x41014022) /**< \brief (SERCOM3) USART Length */
+#define REG_SERCOM3_USART_DATA     (0x41014028) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (0x41014030) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_CTRLC     (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) I2CM Control C */
+#define REG_SERCOM3_I2CM_BAUD      (*(RwReg  *)0x4101400CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY  (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR      (*(RwReg  *)0x41014024UL) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA      (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_CTRLC     (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) I2CS Control C */
+#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY  (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_LENGTH    (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) I2CS Length */
+#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x41014024UL) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA      (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_CTRLC      (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) SPI Control C */
+#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4101400CUL) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY   (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_LENGTH     (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) SPI Length */
+#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x41014024UL) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA       (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_CTRLC    (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) USART Control C */
+#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4101400CUL) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL     (*(RwReg8 *)0x4101400EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x41014020UL) /**< \brief (SERCOM3) USART Receive Error Count */
+#define REG_SERCOM3_USART_LENGTH   (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) USART Length */
+#define REG_SERCOM3_USART_DATA     (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM3_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM3_DMA                 1        // DMA support implemented?
+#define SERCOM3_DMAC_ID_RX          10       // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX          11       // Index of DMA TX trigger
+#define SERCOM3_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM3_GCLK_ID_CORE        24      
+#define SERCOM3_GCLK_ID_SLOW        3       
+#define SERCOM3_INT_MSB             6       
+#define SERCOM3_I2CM                1        // I2C Master mode implemented?
+#define SERCOM3_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM3_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM3_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM3_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM3_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM3_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM3_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM3_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM3_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM3_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM3_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM3_PMSB                3       
+#define SERCOM3_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM3_SE_CNT              1        // SE counter included?
+#define SERCOM3_SPI                 1        // SPI mode implemented?
+#define SERCOM3_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM3_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM3_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM3_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM3_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM3_USART               1        // USART mode implemented?
+#define SERCOM3_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM3_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM3_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM3_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM3_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM3_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM3_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM3_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM3_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM3_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM3_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom4.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom4.h
new file mode 100644
index 000000000..83a8a82b4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom4.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM4_INSTANCE_
+#define _SAME53_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA     (0x43000000) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (0x43000004) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_CTRLC     (0x43000008) /**< \brief (SERCOM4) I2CM Control C */
+#define REG_SERCOM4_I2CM_BAUD      (0x4300000C) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (0x43000014) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (0x43000016) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (0x43000018) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (0x4300001A) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (0x4300001C) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR      (0x43000024) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (0x43000028) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (0x43000030) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (0x43000000) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (0x43000004) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_CTRLC     (0x43000008) /**< \brief (SERCOM4) I2CS Control C */
+#define REG_SERCOM4_I2CS_INTENCLR  (0x43000014) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (0x43000016) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (0x43000018) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (0x4300001A) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (0x4300001C) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_LENGTH    (0x43000022) /**< \brief (SERCOM4) I2CS Length */
+#define REG_SERCOM4_I2CS_ADDR      (0x43000024) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (0x43000028) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (0x43000000) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (0x43000004) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_CTRLC      (0x43000008) /**< \brief (SERCOM4) SPI Control C */
+#define REG_SERCOM4_SPI_BAUD       (0x4300000C) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (0x43000014) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (0x43000018) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (0x4300001A) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (0x4300001C) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_LENGTH     (0x43000022) /**< \brief (SERCOM4) SPI Length */
+#define REG_SERCOM4_SPI_ADDR       (0x43000024) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (0x43000028) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (0x43000030) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (0x43000000) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (0x43000004) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_CTRLC    (0x43000008) /**< \brief (SERCOM4) USART Control C */
+#define REG_SERCOM4_USART_BAUD     (0x4300000C) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (0x4300000E) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x43000014) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x43000016) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (0x43000018) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (0x4300001A) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4300001C) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_RXERRCNT (0x43000020) /**< \brief (SERCOM4) USART Receive Error Count */
+#define REG_SERCOM4_USART_LENGTH   (0x43000022) /**< \brief (SERCOM4) USART Length */
+#define REG_SERCOM4_USART_DATA     (0x43000028) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (0x43000030) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_CTRLC     (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) I2CM Control C */
+#define REG_SERCOM4_I2CM_BAUD      (*(RwReg  *)0x4300000CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY  (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR      (*(RwReg  *)0x43000024UL) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA      (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_CTRLC     (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) I2CS Control C */
+#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY  (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_LENGTH    (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) I2CS Length */
+#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x43000024UL) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA      (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_CTRLC      (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) SPI Control C */
+#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4300000CUL) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY   (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_LENGTH     (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) SPI Length */
+#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x43000024UL) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA       (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_CTRLC    (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) USART Control C */
+#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4300000CUL) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL     (*(RwReg8 *)0x4300000EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x43000020UL) /**< \brief (SERCOM4) USART Receive Error Count */
+#define REG_SERCOM4_USART_LENGTH   (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) USART Length */
+#define REG_SERCOM4_USART_DATA     (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM4_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM4_DMA                 1        // DMA support implemented?
+#define SERCOM4_DMAC_ID_RX          12       // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX          13       // Index of DMA TX trigger
+#define SERCOM4_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM4_GCLK_ID_CORE        34      
+#define SERCOM4_GCLK_ID_SLOW        3       
+#define SERCOM4_INT_MSB             6       
+#define SERCOM4_I2CM                1        // I2C Master mode implemented?
+#define SERCOM4_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM4_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM4_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM4_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM4_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM4_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM4_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM4_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM4_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM4_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM4_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM4_PMSB                3       
+#define SERCOM4_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM4_SE_CNT              1        // SE counter included?
+#define SERCOM4_SPI                 1        // SPI mode implemented?
+#define SERCOM4_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM4_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM4_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM4_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM4_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM4_USART               1        // USART mode implemented?
+#define SERCOM4_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM4_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM4_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM4_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM4_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM4_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM4_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM4_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM4_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM4_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM4_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom5.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom5.h
new file mode 100644
index 000000000..c699a7a37
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom5.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM5_INSTANCE_
+#define _SAME53_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA     (0x43000400) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (0x43000404) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_CTRLC     (0x43000408) /**< \brief (SERCOM5) I2CM Control C */
+#define REG_SERCOM5_I2CM_BAUD      (0x4300040C) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (0x43000414) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (0x43000416) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (0x43000418) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (0x4300041A) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (0x4300041C) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR      (0x43000424) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (0x43000428) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (0x43000430) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (0x43000400) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (0x43000404) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_CTRLC     (0x43000408) /**< \brief (SERCOM5) I2CS Control C */
+#define REG_SERCOM5_I2CS_INTENCLR  (0x43000414) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (0x43000416) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (0x43000418) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (0x4300041A) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (0x4300041C) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_LENGTH    (0x43000422) /**< \brief (SERCOM5) I2CS Length */
+#define REG_SERCOM5_I2CS_ADDR      (0x43000424) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (0x43000428) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (0x43000400) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (0x43000404) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_CTRLC      (0x43000408) /**< \brief (SERCOM5) SPI Control C */
+#define REG_SERCOM5_SPI_BAUD       (0x4300040C) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (0x43000414) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (0x43000416) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (0x43000418) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (0x4300041A) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (0x4300041C) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_LENGTH     (0x43000422) /**< \brief (SERCOM5) SPI Length */
+#define REG_SERCOM5_SPI_ADDR       (0x43000424) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (0x43000428) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (0x43000430) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (0x43000400) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (0x43000404) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_CTRLC    (0x43000408) /**< \brief (SERCOM5) USART Control C */
+#define REG_SERCOM5_USART_BAUD     (0x4300040C) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (0x4300040E) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x43000414) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x43000416) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (0x43000418) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (0x4300041A) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_RXERRCNT (0x43000420) /**< \brief (SERCOM5) USART Receive Error Count */
+#define REG_SERCOM5_USART_LENGTH   (0x43000422) /**< \brief (SERCOM5) USART Length */
+#define REG_SERCOM5_USART_DATA     (0x43000428) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (0x43000430) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_CTRLC     (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) I2CM Control C */
+#define REG_SERCOM5_I2CM_BAUD      (*(RwReg  *)0x4300040CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY  (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR      (*(RwReg  *)0x43000424UL) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA      (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_CTRLC     (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) I2CS Control C */
+#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY  (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_LENGTH    (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) I2CS Length */
+#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x43000424UL) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA      (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_CTRLC      (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) SPI Control C */
+#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x4300040CUL) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY   (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_LENGTH     (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) SPI Length */
+#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x43000424UL) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA       (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_CTRLC    (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) USART Control C */
+#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x4300040CUL) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL     (*(RwReg8 *)0x4300040EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x43000420UL) /**< \brief (SERCOM5) USART Receive Error Count */
+#define REG_SERCOM5_USART_LENGTH   (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) USART Length */
+#define REG_SERCOM5_USART_DATA     (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM5_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM5_DMA                 1        // DMA support implemented?
+#define SERCOM5_DMAC_ID_RX          14       // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX          15       // Index of DMA TX trigger
+#define SERCOM5_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM5_GCLK_ID_CORE        35      
+#define SERCOM5_GCLK_ID_SLOW        3       
+#define SERCOM5_INT_MSB             6       
+#define SERCOM5_I2CM                1        // I2C Master mode implemented?
+#define SERCOM5_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM5_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM5_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM5_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM5_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM5_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM5_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM5_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM5_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM5_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM5_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM5_PMSB                3       
+#define SERCOM5_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM5_SE_CNT              1        // SE counter included?
+#define SERCOM5_SPI                 1        // SPI mode implemented?
+#define SERCOM5_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM5_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM5_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM5_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM5_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM5_USART               1        // USART mode implemented?
+#define SERCOM5_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM5_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM5_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM5_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM5_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM5_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM5_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM5_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM5_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM5_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM5_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom6.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom6.h
new file mode 100644
index 000000000..2d3ec7bae
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom6.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM6
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM6_INSTANCE_
+#define _SAME53_SERCOM6_INSTANCE_
+
+/* ========== Register definition for SERCOM6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM6_I2CM_CTRLA     (0x43000800) /**< \brief (SERCOM6) I2CM Control A */
+#define REG_SERCOM6_I2CM_CTRLB     (0x43000804) /**< \brief (SERCOM6) I2CM Control B */
+#define REG_SERCOM6_I2CM_CTRLC     (0x43000808) /**< \brief (SERCOM6) I2CM Control C */
+#define REG_SERCOM6_I2CM_BAUD      (0x4300080C) /**< \brief (SERCOM6) I2CM Baud Rate */
+#define REG_SERCOM6_I2CM_INTENCLR  (0x43000814) /**< \brief (SERCOM6) I2CM Interrupt Enable Clear */
+#define REG_SERCOM6_I2CM_INTENSET  (0x43000816) /**< \brief (SERCOM6) I2CM Interrupt Enable Set */
+#define REG_SERCOM6_I2CM_INTFLAG   (0x43000818) /**< \brief (SERCOM6) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CM_STATUS    (0x4300081A) /**< \brief (SERCOM6) I2CM Status */
+#define REG_SERCOM6_I2CM_SYNCBUSY  (0x4300081C) /**< \brief (SERCOM6) I2CM Synchronization Busy */
+#define REG_SERCOM6_I2CM_ADDR      (0x43000824) /**< \brief (SERCOM6) I2CM Address */
+#define REG_SERCOM6_I2CM_DATA      (0x43000828) /**< \brief (SERCOM6) I2CM Data */
+#define REG_SERCOM6_I2CM_DBGCTRL   (0x43000830) /**< \brief (SERCOM6) I2CM Debug Control */
+#define REG_SERCOM6_I2CS_CTRLA     (0x43000800) /**< \brief (SERCOM6) I2CS Control A */
+#define REG_SERCOM6_I2CS_CTRLB     (0x43000804) /**< \brief (SERCOM6) I2CS Control B */
+#define REG_SERCOM6_I2CS_CTRLC     (0x43000808) /**< \brief (SERCOM6) I2CS Control C */
+#define REG_SERCOM6_I2CS_INTENCLR  (0x43000814) /**< \brief (SERCOM6) I2CS Interrupt Enable Clear */
+#define REG_SERCOM6_I2CS_INTENSET  (0x43000816) /**< \brief (SERCOM6) I2CS Interrupt Enable Set */
+#define REG_SERCOM6_I2CS_INTFLAG   (0x43000818) /**< \brief (SERCOM6) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CS_STATUS    (0x4300081A) /**< \brief (SERCOM6) I2CS Status */
+#define REG_SERCOM6_I2CS_SYNCBUSY  (0x4300081C) /**< \brief (SERCOM6) I2CS Synchronization Busy */
+#define REG_SERCOM6_I2CS_LENGTH    (0x43000822) /**< \brief (SERCOM6) I2CS Length */
+#define REG_SERCOM6_I2CS_ADDR      (0x43000824) /**< \brief (SERCOM6) I2CS Address */
+#define REG_SERCOM6_I2CS_DATA      (0x43000828) /**< \brief (SERCOM6) I2CS Data */
+#define REG_SERCOM6_SPI_CTRLA      (0x43000800) /**< \brief (SERCOM6) SPI Control A */
+#define REG_SERCOM6_SPI_CTRLB      (0x43000804) /**< \brief (SERCOM6) SPI Control B */
+#define REG_SERCOM6_SPI_CTRLC      (0x43000808) /**< \brief (SERCOM6) SPI Control C */
+#define REG_SERCOM6_SPI_BAUD       (0x4300080C) /**< \brief (SERCOM6) SPI Baud Rate */
+#define REG_SERCOM6_SPI_INTENCLR   (0x43000814) /**< \brief (SERCOM6) SPI Interrupt Enable Clear */
+#define REG_SERCOM6_SPI_INTENSET   (0x43000816) /**< \brief (SERCOM6) SPI Interrupt Enable Set */
+#define REG_SERCOM6_SPI_INTFLAG    (0x43000818) /**< \brief (SERCOM6) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM6_SPI_STATUS     (0x4300081A) /**< \brief (SERCOM6) SPI Status */
+#define REG_SERCOM6_SPI_SYNCBUSY   (0x4300081C) /**< \brief (SERCOM6) SPI Synchronization Busy */
+#define REG_SERCOM6_SPI_LENGTH     (0x43000822) /**< \brief (SERCOM6) SPI Length */
+#define REG_SERCOM6_SPI_ADDR       (0x43000824) /**< \brief (SERCOM6) SPI Address */
+#define REG_SERCOM6_SPI_DATA       (0x43000828) /**< \brief (SERCOM6) SPI Data */
+#define REG_SERCOM6_SPI_DBGCTRL    (0x43000830) /**< \brief (SERCOM6) SPI Debug Control */
+#define REG_SERCOM6_USART_CTRLA    (0x43000800) /**< \brief (SERCOM6) USART Control A */
+#define REG_SERCOM6_USART_CTRLB    (0x43000804) /**< \brief (SERCOM6) USART Control B */
+#define REG_SERCOM6_USART_CTRLC    (0x43000808) /**< \brief (SERCOM6) USART Control C */
+#define REG_SERCOM6_USART_BAUD     (0x4300080C) /**< \brief (SERCOM6) USART Baud Rate */
+#define REG_SERCOM6_USART_RXPL     (0x4300080E) /**< \brief (SERCOM6) USART Receive Pulse Length */
+#define REG_SERCOM6_USART_INTENCLR (0x43000814) /**< \brief (SERCOM6) USART Interrupt Enable Clear */
+#define REG_SERCOM6_USART_INTENSET (0x43000816) /**< \brief (SERCOM6) USART Interrupt Enable Set */
+#define REG_SERCOM6_USART_INTFLAG  (0x43000818) /**< \brief (SERCOM6) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM6_USART_STATUS   (0x4300081A) /**< \brief (SERCOM6) USART Status */
+#define REG_SERCOM6_USART_SYNCBUSY (0x4300081C) /**< \brief (SERCOM6) USART Synchronization Busy */
+#define REG_SERCOM6_USART_RXERRCNT (0x43000820) /**< \brief (SERCOM6) USART Receive Error Count */
+#define REG_SERCOM6_USART_LENGTH   (0x43000822) /**< \brief (SERCOM6) USART Length */
+#define REG_SERCOM6_USART_DATA     (0x43000828) /**< \brief (SERCOM6) USART Data */
+#define REG_SERCOM6_USART_DBGCTRL  (0x43000830) /**< \brief (SERCOM6) USART Debug Control */
+#else
+#define REG_SERCOM6_I2CM_CTRLA     (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) I2CM Control A */
+#define REG_SERCOM6_I2CM_CTRLB     (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) I2CM Control B */
+#define REG_SERCOM6_I2CM_CTRLC     (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) I2CM Control C */
+#define REG_SERCOM6_I2CM_BAUD      (*(RwReg  *)0x4300080CUL) /**< \brief (SERCOM6) I2CM Baud Rate */
+#define REG_SERCOM6_I2CM_INTENCLR  (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) I2CM Interrupt Enable Clear */
+#define REG_SERCOM6_I2CM_INTENSET  (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) I2CM Interrupt Enable Set */
+#define REG_SERCOM6_I2CM_INTFLAG   (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CM_STATUS    (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) I2CM Status */
+#define REG_SERCOM6_I2CM_SYNCBUSY  (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) I2CM Synchronization Busy */
+#define REG_SERCOM6_I2CM_ADDR      (*(RwReg  *)0x43000824UL) /**< \brief (SERCOM6) I2CM Address */
+#define REG_SERCOM6_I2CM_DATA      (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) I2CM Data */
+#define REG_SERCOM6_I2CM_DBGCTRL   (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) I2CM Debug Control */
+#define REG_SERCOM6_I2CS_CTRLA     (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) I2CS Control A */
+#define REG_SERCOM6_I2CS_CTRLB     (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) I2CS Control B */
+#define REG_SERCOM6_I2CS_CTRLC     (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) I2CS Control C */
+#define REG_SERCOM6_I2CS_INTENCLR  (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) I2CS Interrupt Enable Clear */
+#define REG_SERCOM6_I2CS_INTENSET  (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) I2CS Interrupt Enable Set */
+#define REG_SERCOM6_I2CS_INTFLAG   (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM6_I2CS_STATUS    (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) I2CS Status */
+#define REG_SERCOM6_I2CS_SYNCBUSY  (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) I2CS Synchronization Busy */
+#define REG_SERCOM6_I2CS_LENGTH    (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) I2CS Length */
+#define REG_SERCOM6_I2CS_ADDR      (*(RwReg  *)0x43000824UL) /**< \brief (SERCOM6) I2CS Address */
+#define REG_SERCOM6_I2CS_DATA      (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) I2CS Data */
+#define REG_SERCOM6_SPI_CTRLA      (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) SPI Control A */
+#define REG_SERCOM6_SPI_CTRLB      (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) SPI Control B */
+#define REG_SERCOM6_SPI_CTRLC      (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) SPI Control C */
+#define REG_SERCOM6_SPI_BAUD       (*(RwReg8 *)0x4300080CUL) /**< \brief (SERCOM6) SPI Baud Rate */
+#define REG_SERCOM6_SPI_INTENCLR   (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) SPI Interrupt Enable Clear */
+#define REG_SERCOM6_SPI_INTENSET   (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) SPI Interrupt Enable Set */
+#define REG_SERCOM6_SPI_INTFLAG    (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM6_SPI_STATUS     (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) SPI Status */
+#define REG_SERCOM6_SPI_SYNCBUSY   (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) SPI Synchronization Busy */
+#define REG_SERCOM6_SPI_LENGTH     (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) SPI Length */
+#define REG_SERCOM6_SPI_ADDR       (*(RwReg  *)0x43000824UL) /**< \brief (SERCOM6) SPI Address */
+#define REG_SERCOM6_SPI_DATA       (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) SPI Data */
+#define REG_SERCOM6_SPI_DBGCTRL    (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) SPI Debug Control */
+#define REG_SERCOM6_USART_CTRLA    (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) USART Control A */
+#define REG_SERCOM6_USART_CTRLB    (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) USART Control B */
+#define REG_SERCOM6_USART_CTRLC    (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) USART Control C */
+#define REG_SERCOM6_USART_BAUD     (*(RwReg16*)0x4300080CUL) /**< \brief (SERCOM6) USART Baud Rate */
+#define REG_SERCOM6_USART_RXPL     (*(RwReg8 *)0x4300080EUL) /**< \brief (SERCOM6) USART Receive Pulse Length */
+#define REG_SERCOM6_USART_INTENCLR (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) USART Interrupt Enable Clear */
+#define REG_SERCOM6_USART_INTENSET (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) USART Interrupt Enable Set */
+#define REG_SERCOM6_USART_INTFLAG  (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM6_USART_STATUS   (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) USART Status */
+#define REG_SERCOM6_USART_SYNCBUSY (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) USART Synchronization Busy */
+#define REG_SERCOM6_USART_RXERRCNT (*(RoReg8 *)0x43000820UL) /**< \brief (SERCOM6) USART Receive Error Count */
+#define REG_SERCOM6_USART_LENGTH   (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) USART Length */
+#define REG_SERCOM6_USART_DATA     (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) USART Data */
+#define REG_SERCOM6_USART_DBGCTRL  (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM6 peripheral ========== */
+#define SERCOM6_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM6_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM6_DMA                 1        // DMA support implemented?
+#define SERCOM6_DMAC_ID_RX          16       // Index of DMA RX trigger
+#define SERCOM6_DMAC_ID_TX          17       // Index of DMA TX trigger
+#define SERCOM6_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM6_GCLK_ID_CORE        36      
+#define SERCOM6_GCLK_ID_SLOW        3       
+#define SERCOM6_INT_MSB             6       
+#define SERCOM6_I2CM                1        // I2C Master mode implemented?
+#define SERCOM6_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM6_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM6_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM6_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM6_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM6_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM6_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM6_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM6_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM6_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM6_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM6_PMSB                3       
+#define SERCOM6_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM6_SE_CNT              1        // SE counter included?
+#define SERCOM6_SPI                 1        // SPI mode implemented?
+#define SERCOM6_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM6_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM6_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM6_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM6_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM6_USART               1        // USART mode implemented?
+#define SERCOM6_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM6_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM6_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM6_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM6_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM6_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM6_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM6_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM6_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM6_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM6_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom7.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom7.h
new file mode 100644
index 000000000..671b57a31
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/sercom7.h	
@@ -0,0 +1,181 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM7
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SERCOM7_INSTANCE_
+#define _SAME53_SERCOM7_INSTANCE_
+
+/* ========== Register definition for SERCOM7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM7_I2CM_CTRLA     (0x43000C00) /**< \brief (SERCOM7) I2CM Control A */
+#define REG_SERCOM7_I2CM_CTRLB     (0x43000C04) /**< \brief (SERCOM7) I2CM Control B */
+#define REG_SERCOM7_I2CM_CTRLC     (0x43000C08) /**< \brief (SERCOM7) I2CM Control C */
+#define REG_SERCOM7_I2CM_BAUD      (0x43000C0C) /**< \brief (SERCOM7) I2CM Baud Rate */
+#define REG_SERCOM7_I2CM_INTENCLR  (0x43000C14) /**< \brief (SERCOM7) I2CM Interrupt Enable Clear */
+#define REG_SERCOM7_I2CM_INTENSET  (0x43000C16) /**< \brief (SERCOM7) I2CM Interrupt Enable Set */
+#define REG_SERCOM7_I2CM_INTFLAG   (0x43000C18) /**< \brief (SERCOM7) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CM_STATUS    (0x43000C1A) /**< \brief (SERCOM7) I2CM Status */
+#define REG_SERCOM7_I2CM_SYNCBUSY  (0x43000C1C) /**< \brief (SERCOM7) I2CM Synchronization Busy */
+#define REG_SERCOM7_I2CM_ADDR      (0x43000C24) /**< \brief (SERCOM7) I2CM Address */
+#define REG_SERCOM7_I2CM_DATA      (0x43000C28) /**< \brief (SERCOM7) I2CM Data */
+#define REG_SERCOM7_I2CM_DBGCTRL   (0x43000C30) /**< \brief (SERCOM7) I2CM Debug Control */
+#define REG_SERCOM7_I2CS_CTRLA     (0x43000C00) /**< \brief (SERCOM7) I2CS Control A */
+#define REG_SERCOM7_I2CS_CTRLB     (0x43000C04) /**< \brief (SERCOM7) I2CS Control B */
+#define REG_SERCOM7_I2CS_CTRLC     (0x43000C08) /**< \brief (SERCOM7) I2CS Control C */
+#define REG_SERCOM7_I2CS_INTENCLR  (0x43000C14) /**< \brief (SERCOM7) I2CS Interrupt Enable Clear */
+#define REG_SERCOM7_I2CS_INTENSET  (0x43000C16) /**< \brief (SERCOM7) I2CS Interrupt Enable Set */
+#define REG_SERCOM7_I2CS_INTFLAG   (0x43000C18) /**< \brief (SERCOM7) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CS_STATUS    (0x43000C1A) /**< \brief (SERCOM7) I2CS Status */
+#define REG_SERCOM7_I2CS_SYNCBUSY  (0x43000C1C) /**< \brief (SERCOM7) I2CS Synchronization Busy */
+#define REG_SERCOM7_I2CS_LENGTH    (0x43000C22) /**< \brief (SERCOM7) I2CS Length */
+#define REG_SERCOM7_I2CS_ADDR      (0x43000C24) /**< \brief (SERCOM7) I2CS Address */
+#define REG_SERCOM7_I2CS_DATA      (0x43000C28) /**< \brief (SERCOM7) I2CS Data */
+#define REG_SERCOM7_SPI_CTRLA      (0x43000C00) /**< \brief (SERCOM7) SPI Control A */
+#define REG_SERCOM7_SPI_CTRLB      (0x43000C04) /**< \brief (SERCOM7) SPI Control B */
+#define REG_SERCOM7_SPI_CTRLC      (0x43000C08) /**< \brief (SERCOM7) SPI Control C */
+#define REG_SERCOM7_SPI_BAUD       (0x43000C0C) /**< \brief (SERCOM7) SPI Baud Rate */
+#define REG_SERCOM7_SPI_INTENCLR   (0x43000C14) /**< \brief (SERCOM7) SPI Interrupt Enable Clear */
+#define REG_SERCOM7_SPI_INTENSET   (0x43000C16) /**< \brief (SERCOM7) SPI Interrupt Enable Set */
+#define REG_SERCOM7_SPI_INTFLAG    (0x43000C18) /**< \brief (SERCOM7) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM7_SPI_STATUS     (0x43000C1A) /**< \brief (SERCOM7) SPI Status */
+#define REG_SERCOM7_SPI_SYNCBUSY   (0x43000C1C) /**< \brief (SERCOM7) SPI Synchronization Busy */
+#define REG_SERCOM7_SPI_LENGTH     (0x43000C22) /**< \brief (SERCOM7) SPI Length */
+#define REG_SERCOM7_SPI_ADDR       (0x43000C24) /**< \brief (SERCOM7) SPI Address */
+#define REG_SERCOM7_SPI_DATA       (0x43000C28) /**< \brief (SERCOM7) SPI Data */
+#define REG_SERCOM7_SPI_DBGCTRL    (0x43000C30) /**< \brief (SERCOM7) SPI Debug Control */
+#define REG_SERCOM7_USART_CTRLA    (0x43000C00) /**< \brief (SERCOM7) USART Control A */
+#define REG_SERCOM7_USART_CTRLB    (0x43000C04) /**< \brief (SERCOM7) USART Control B */
+#define REG_SERCOM7_USART_CTRLC    (0x43000C08) /**< \brief (SERCOM7) USART Control C */
+#define REG_SERCOM7_USART_BAUD     (0x43000C0C) /**< \brief (SERCOM7) USART Baud Rate */
+#define REG_SERCOM7_USART_RXPL     (0x43000C0E) /**< \brief (SERCOM7) USART Receive Pulse Length */
+#define REG_SERCOM7_USART_INTENCLR (0x43000C14) /**< \brief (SERCOM7) USART Interrupt Enable Clear */
+#define REG_SERCOM7_USART_INTENSET (0x43000C16) /**< \brief (SERCOM7) USART Interrupt Enable Set */
+#define REG_SERCOM7_USART_INTFLAG  (0x43000C18) /**< \brief (SERCOM7) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM7_USART_STATUS   (0x43000C1A) /**< \brief (SERCOM7) USART Status */
+#define REG_SERCOM7_USART_SYNCBUSY (0x43000C1C) /**< \brief (SERCOM7) USART Synchronization Busy */
+#define REG_SERCOM7_USART_RXERRCNT (0x43000C20) /**< \brief (SERCOM7) USART Receive Error Count */
+#define REG_SERCOM7_USART_LENGTH   (0x43000C22) /**< \brief (SERCOM7) USART Length */
+#define REG_SERCOM7_USART_DATA     (0x43000C28) /**< \brief (SERCOM7) USART Data */
+#define REG_SERCOM7_USART_DBGCTRL  (0x43000C30) /**< \brief (SERCOM7) USART Debug Control */
+#else
+#define REG_SERCOM7_I2CM_CTRLA     (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) I2CM Control A */
+#define REG_SERCOM7_I2CM_CTRLB     (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) I2CM Control B */
+#define REG_SERCOM7_I2CM_CTRLC     (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) I2CM Control C */
+#define REG_SERCOM7_I2CM_BAUD      (*(RwReg  *)0x43000C0CUL) /**< \brief (SERCOM7) I2CM Baud Rate */
+#define REG_SERCOM7_I2CM_INTENCLR  (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) I2CM Interrupt Enable Clear */
+#define REG_SERCOM7_I2CM_INTENSET  (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) I2CM Interrupt Enable Set */
+#define REG_SERCOM7_I2CM_INTFLAG   (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CM_STATUS    (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) I2CM Status */
+#define REG_SERCOM7_I2CM_SYNCBUSY  (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) I2CM Synchronization Busy */
+#define REG_SERCOM7_I2CM_ADDR      (*(RwReg  *)0x43000C24UL) /**< \brief (SERCOM7) I2CM Address */
+#define REG_SERCOM7_I2CM_DATA      (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) I2CM Data */
+#define REG_SERCOM7_I2CM_DBGCTRL   (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) I2CM Debug Control */
+#define REG_SERCOM7_I2CS_CTRLA     (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) I2CS Control A */
+#define REG_SERCOM7_I2CS_CTRLB     (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) I2CS Control B */
+#define REG_SERCOM7_I2CS_CTRLC     (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) I2CS Control C */
+#define REG_SERCOM7_I2CS_INTENCLR  (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) I2CS Interrupt Enable Clear */
+#define REG_SERCOM7_I2CS_INTENSET  (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) I2CS Interrupt Enable Set */
+#define REG_SERCOM7_I2CS_INTFLAG   (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM7_I2CS_STATUS    (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) I2CS Status */
+#define REG_SERCOM7_I2CS_SYNCBUSY  (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) I2CS Synchronization Busy */
+#define REG_SERCOM7_I2CS_LENGTH    (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) I2CS Length */
+#define REG_SERCOM7_I2CS_ADDR      (*(RwReg  *)0x43000C24UL) /**< \brief (SERCOM7) I2CS Address */
+#define REG_SERCOM7_I2CS_DATA      (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) I2CS Data */
+#define REG_SERCOM7_SPI_CTRLA      (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) SPI Control A */
+#define REG_SERCOM7_SPI_CTRLB      (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) SPI Control B */
+#define REG_SERCOM7_SPI_CTRLC      (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) SPI Control C */
+#define REG_SERCOM7_SPI_BAUD       (*(RwReg8 *)0x43000C0CUL) /**< \brief (SERCOM7) SPI Baud Rate */
+#define REG_SERCOM7_SPI_INTENCLR   (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) SPI Interrupt Enable Clear */
+#define REG_SERCOM7_SPI_INTENSET   (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) SPI Interrupt Enable Set */
+#define REG_SERCOM7_SPI_INTFLAG    (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM7_SPI_STATUS     (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) SPI Status */
+#define REG_SERCOM7_SPI_SYNCBUSY   (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) SPI Synchronization Busy */
+#define REG_SERCOM7_SPI_LENGTH     (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) SPI Length */
+#define REG_SERCOM7_SPI_ADDR       (*(RwReg  *)0x43000C24UL) /**< \brief (SERCOM7) SPI Address */
+#define REG_SERCOM7_SPI_DATA       (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) SPI Data */
+#define REG_SERCOM7_SPI_DBGCTRL    (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) SPI Debug Control */
+#define REG_SERCOM7_USART_CTRLA    (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) USART Control A */
+#define REG_SERCOM7_USART_CTRLB    (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) USART Control B */
+#define REG_SERCOM7_USART_CTRLC    (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) USART Control C */
+#define REG_SERCOM7_USART_BAUD     (*(RwReg16*)0x43000C0CUL) /**< \brief (SERCOM7) USART Baud Rate */
+#define REG_SERCOM7_USART_RXPL     (*(RwReg8 *)0x43000C0EUL) /**< \brief (SERCOM7) USART Receive Pulse Length */
+#define REG_SERCOM7_USART_INTENCLR (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) USART Interrupt Enable Clear */
+#define REG_SERCOM7_USART_INTENSET (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) USART Interrupt Enable Set */
+#define REG_SERCOM7_USART_INTFLAG  (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM7_USART_STATUS   (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) USART Status */
+#define REG_SERCOM7_USART_SYNCBUSY (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) USART Synchronization Busy */
+#define REG_SERCOM7_USART_RXERRCNT (*(RoReg8 *)0x43000C20UL) /**< \brief (SERCOM7) USART Receive Error Count */
+#define REG_SERCOM7_USART_LENGTH   (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) USART Length */
+#define REG_SERCOM7_USART_DATA     (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) USART Data */
+#define REG_SERCOM7_USART_DBGCTRL  (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM7 peripheral ========== */
+#define SERCOM7_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
+#define SERCOM7_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
+#define SERCOM7_DMA                 1        // DMA support implemented?
+#define SERCOM7_DMAC_ID_RX          18       // Index of DMA RX trigger
+#define SERCOM7_DMAC_ID_TX          19       // Index of DMA TX trigger
+#define SERCOM7_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
+#define SERCOM7_GCLK_ID_CORE        37      
+#define SERCOM7_GCLK_ID_SLOW        3       
+#define SERCOM7_INT_MSB             6       
+#define SERCOM7_I2CM                1        // I2C Master mode implemented?
+#define SERCOM7_I2CS                1        // I2C Slave mode implemented?
+#define SERCOM7_I2CS_AUTO_ACK       1        // I2C slave automatic acknowledge implemented?
+#define SERCOM7_I2CS_GROUP_CMD      1        // I2C slave group command implemented?
+#define SERCOM7_I2CS_SDASETUP_CNT_SIZE 8        // I2CS sda setup count size
+#define SERCOM7_I2CS_SDASETUP_SIZE  4        // I2CS sda setup size
+#define SERCOM7_I2CS_SUDAT          1        // I2C slave SDA setup implemented?
+#define SERCOM7_I2C_FASTMP          1        // I2C fast mode plus implemented?
+#define SERCOM7_I2C_HSMODE          1        // USART mode implemented?
+#define SERCOM7_I2C_SCLSM_MODE      1        // I2C SCL clock stretch mode implemented?
+#define SERCOM7_I2C_SMB_TIMEOUTS    1        // I2C SMBus timeouts implemented?
+#define SERCOM7_I2C_TENBIT_ADR      1        // I2C ten bit enabled?
+#define SERCOM7_PMSB                3       
+#define SERCOM7_RETENTION_SUPPORT   0        // Retention supported?
+#define SERCOM7_SE_CNT              1        // SE counter included?
+#define SERCOM7_SPI                 1        // SPI mode implemented?
+#define SERCOM7_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
+#define SERCOM7_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
+#define SERCOM7_SPI_OZMO            0        // OZMO features implemented?
+#define SERCOM7_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
+#define SERCOM7_TTBIT_EXTENSION     1        // 32-bit extension implemented?
+#define SERCOM7_USART               1        // USART mode implemented?
+#define SERCOM7_USART_AUTOBAUD      1        // USART autobaud implemented?
+#define SERCOM7_USART_COLDET        1        // USART collision detection implemented?
+#define SERCOM7_USART_FLOW_CTRL     1        // USART flow control implemented?
+#define SERCOM7_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
+#define SERCOM7_USART_IRDA          1        // USART IrDA implemented?
+#define SERCOM7_USART_ISO7816       1        // USART ISO7816 mode implemented?
+#define SERCOM7_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
+#define SERCOM7_USART_RS485         1        // USART RS485 mode implemented?
+#define SERCOM7_USART_SAMPA_EXT     1        // USART sample adjust implemented?
+#define SERCOM7_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
+
+#endif /* _SAME53_SERCOM7_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/supc.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/supc.h
new file mode 100644
index 000000000..b56691bab
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/supc.h	
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SUPC
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_SUPC_INSTANCE_
+#define _SAME53_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_INTENCLR          (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */
+#define REG_SUPC_INTENSET          (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */
+#define REG_SUPC_INTFLAG           (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */
+#define REG_SUPC_STATUS            (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */
+#define REG_SUPC_BOD33             (0x40001810) /**< \brief (SUPC) BOD33 Control */
+#define REG_SUPC_VREG              (0x40001818) /**< \brief (SUPC) VREG Control */
+#define REG_SUPC_VREF              (0x4000181C) /**< \brief (SUPC) VREF Control */
+#define REG_SUPC_BBPS              (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */
+#define REG_SUPC_BKOUT             (0x40001824) /**< \brief (SUPC) Backup Output Control */
+#define REG_SUPC_BKIN              (0x40001828) /**< \brief (SUPC) Backup Input Control */
+#else
+#define REG_SUPC_INTENCLR          (*(RwReg  *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */
+#define REG_SUPC_INTENSET          (*(RwReg  *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */
+#define REG_SUPC_INTFLAG           (*(RwReg  *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */
+#define REG_SUPC_STATUS            (*(RoReg  *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */
+#define REG_SUPC_BOD33             (*(RwReg  *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */
+#define REG_SUPC_VREG              (*(RwReg  *)0x40001818UL) /**< \brief (SUPC) VREG Control */
+#define REG_SUPC_VREF              (*(RwReg  *)0x4000181CUL) /**< \brief (SUPC) VREF Control */
+#define REG_SUPC_BBPS              (*(RwReg  *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */
+#define REG_SUPC_BKOUT             (*(RwReg  *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */
+#define REG_SUPC_BKIN              (*(RoReg  *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SUPC peripheral ========== */
+#define SUPC_BOD12_CALIB_MSB        5       
+#define SUPC_BOD33_CALIB_MSB        5       
+
+#endif /* _SAME53_SUPC_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc0.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc0.h
new file mode 100644
index 000000000..eeafde854
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc0.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC0
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC0_INSTANCE_
+#define _SAME53_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CTRLA              (0x40003800) /**< \brief (TC0) Control A */
+#define REG_TC0_CTRLBCLR           (0x40003804) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET           (0x40003805) /**< \brief (TC0) Control B Set */
+#define REG_TC0_EVCTRL             (0x40003806) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR           (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET           (0x40003809) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG            (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS             (0x4000380B) /**< \brief (TC0) Status */
+#define REG_TC0_WAVE               (0x4000380C) /**< \brief (TC0) Waveform Generation Control */
+#define REG_TC0_DRVCTRL            (0x4000380D) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL            (0x4000380F) /**< \brief (TC0) Debug Control */
+#define REG_TC0_SYNCBUSY           (0x40003810) /**< \brief (TC0) Synchronization Status */
+#define REG_TC0_COUNT16_COUNT      (0x40003814) /**< \brief (TC0) COUNT16 Count */
+#define REG_TC0_COUNT16_CC0        (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
+#define REG_TC0_COUNT16_CC1        (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
+#define REG_TC0_COUNT16_CCBUF0     (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT16_CCBUF1     (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT32_COUNT      (0x40003814) /**< \brief (TC0) COUNT32 Count */
+#define REG_TC0_COUNT32_CC0        (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
+#define REG_TC0_COUNT32_CC1        (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
+#define REG_TC0_COUNT32_CCBUF0     (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT32_CCBUF1     (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT8_COUNT       (0x40003814) /**< \brief (TC0) COUNT8 Count */
+#define REG_TC0_COUNT8_PER         (0x4000381B) /**< \brief (TC0) COUNT8 Period */
+#define REG_TC0_COUNT8_CC0         (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
+#define REG_TC0_COUNT8_CC1         (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
+#define REG_TC0_COUNT8_PERBUF      (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */
+#define REG_TC0_COUNT8_CCBUF0      (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT8_CCBUF1      (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC0_CTRLA              (*(RwReg  *)0x40003800UL) /**< \brief (TC0) Control A */
+#define REG_TC0_CTRLBCLR           (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET           (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */
+#define REG_TC0_EVCTRL             (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR           (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET           (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG            (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS             (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */
+#define REG_TC0_WAVE               (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */
+#define REG_TC0_DRVCTRL            (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL            (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */
+#define REG_TC0_SYNCBUSY           (*(RoReg  *)0x40003810UL) /**< \brief (TC0) Synchronization Status */
+#define REG_TC0_COUNT16_COUNT      (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */
+#define REG_TC0_COUNT16_CC0        (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
+#define REG_TC0_COUNT16_CC1        (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
+#define REG_TC0_COUNT16_CCBUF0     (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT16_CCBUF1     (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT32_COUNT      (*(RwReg  *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */
+#define REG_TC0_COUNT32_CC0        (*(RwReg  *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
+#define REG_TC0_COUNT32_CC1        (*(RwReg  *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
+#define REG_TC0_COUNT32_CCBUF0     (*(RwReg  *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT32_CCBUF1     (*(RwReg  *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT8_COUNT       (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */
+#define REG_TC0_COUNT8_PER         (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */
+#define REG_TC0_COUNT8_CC0         (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
+#define REG_TC0_COUNT8_CC1         (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
+#define REG_TC0_COUNT8_PERBUF      (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */
+#define REG_TC0_COUNT8_CCBUF0      (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT8_CCBUF1      (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC0 peripheral ========== */
+#define TC0_CC_NUM                  2       
+#define TC0_DMAC_ID_MC_0            45
+#define TC0_DMAC_ID_MC_1            46
+#define TC0_DMAC_ID_MC_LSB          45
+#define TC0_DMAC_ID_MC_MSB          46
+#define TC0_DMAC_ID_MC_SIZE         2
+#define TC0_DMAC_ID_OVF             44       // Indexes of DMA Overflow trigger
+#define TC0_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC0_GCLK_ID                 9        // Index of Generic Clock
+#define TC0_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC0_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC0_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc1.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc1.h
new file mode 100644
index 000000000..d94518265
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc1.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC1
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC1_INSTANCE_
+#define _SAME53_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CTRLA              (0x40003C00) /**< \brief (TC1) Control A */
+#define REG_TC1_CTRLBCLR           (0x40003C04) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET           (0x40003C05) /**< \brief (TC1) Control B Set */
+#define REG_TC1_EVCTRL             (0x40003C06) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR           (0x40003C08) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET           (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG            (0x40003C0A) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS             (0x40003C0B) /**< \brief (TC1) Status */
+#define REG_TC1_WAVE               (0x40003C0C) /**< \brief (TC1) Waveform Generation Control */
+#define REG_TC1_DRVCTRL            (0x40003C0D) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL            (0x40003C0F) /**< \brief (TC1) Debug Control */
+#define REG_TC1_SYNCBUSY           (0x40003C10) /**< \brief (TC1) Synchronization Status */
+#define REG_TC1_COUNT16_COUNT      (0x40003C14) /**< \brief (TC1) COUNT16 Count */
+#define REG_TC1_COUNT16_CC0        (0x40003C1C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
+#define REG_TC1_COUNT16_CC1        (0x40003C1E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
+#define REG_TC1_COUNT16_CCBUF0     (0x40003C30) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT16_CCBUF1     (0x40003C32) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT32_COUNT      (0x40003C14) /**< \brief (TC1) COUNT32 Count */
+#define REG_TC1_COUNT32_CC0        (0x40003C1C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
+#define REG_TC1_COUNT32_CC1        (0x40003C20) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
+#define REG_TC1_COUNT32_CCBUF0     (0x40003C30) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT32_CCBUF1     (0x40003C34) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT8_COUNT       (0x40003C14) /**< \brief (TC1) COUNT8 Count */
+#define REG_TC1_COUNT8_PER         (0x40003C1B) /**< \brief (TC1) COUNT8 Period */
+#define REG_TC1_COUNT8_CC0         (0x40003C1C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
+#define REG_TC1_COUNT8_CC1         (0x40003C1D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
+#define REG_TC1_COUNT8_PERBUF      (0x40003C2F) /**< \brief (TC1) COUNT8 Period Buffer */
+#define REG_TC1_COUNT8_CCBUF0      (0x40003C30) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT8_CCBUF1      (0x40003C31) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC1_CTRLA              (*(RwReg  *)0x40003C00UL) /**< \brief (TC1) Control A */
+#define REG_TC1_CTRLBCLR           (*(RwReg8 *)0x40003C04UL) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET           (*(RwReg8 *)0x40003C05UL) /**< \brief (TC1) Control B Set */
+#define REG_TC1_EVCTRL             (*(RwReg16*)0x40003C06UL) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR           (*(RwReg8 *)0x40003C08UL) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET           (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG            (*(RwReg8 *)0x40003C0AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS             (*(RwReg8 *)0x40003C0BUL) /**< \brief (TC1) Status */
+#define REG_TC1_WAVE               (*(RwReg8 *)0x40003C0CUL) /**< \brief (TC1) Waveform Generation Control */
+#define REG_TC1_DRVCTRL            (*(RwReg8 *)0x40003C0DUL) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL            (*(RwReg8 *)0x40003C0FUL) /**< \brief (TC1) Debug Control */
+#define REG_TC1_SYNCBUSY           (*(RoReg  *)0x40003C10UL) /**< \brief (TC1) Synchronization Status */
+#define REG_TC1_COUNT16_COUNT      (*(RwReg16*)0x40003C14UL) /**< \brief (TC1) COUNT16 Count */
+#define REG_TC1_COUNT16_CC0        (*(RwReg16*)0x40003C1CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
+#define REG_TC1_COUNT16_CC1        (*(RwReg16*)0x40003C1EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
+#define REG_TC1_COUNT16_CCBUF0     (*(RwReg16*)0x40003C30UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT16_CCBUF1     (*(RwReg16*)0x40003C32UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT32_COUNT      (*(RwReg  *)0x40003C14UL) /**< \brief (TC1) COUNT32 Count */
+#define REG_TC1_COUNT32_CC0        (*(RwReg  *)0x40003C1CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
+#define REG_TC1_COUNT32_CC1        (*(RwReg  *)0x40003C20UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
+#define REG_TC1_COUNT32_CCBUF0     (*(RwReg  *)0x40003C30UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT32_CCBUF1     (*(RwReg  *)0x40003C34UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT8_COUNT       (*(RwReg8 *)0x40003C14UL) /**< \brief (TC1) COUNT8 Count */
+#define REG_TC1_COUNT8_PER         (*(RwReg8 *)0x40003C1BUL) /**< \brief (TC1) COUNT8 Period */
+#define REG_TC1_COUNT8_CC0         (*(RwReg8 *)0x40003C1CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
+#define REG_TC1_COUNT8_CC1         (*(RwReg8 *)0x40003C1DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
+#define REG_TC1_COUNT8_PERBUF      (*(RwReg8 *)0x40003C2FUL) /**< \brief (TC1) COUNT8 Period Buffer */
+#define REG_TC1_COUNT8_CCBUF0      (*(RwReg8 *)0x40003C30UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT8_CCBUF1      (*(RwReg8 *)0x40003C31UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC1 peripheral ========== */
+#define TC1_CC_NUM                  2       
+#define TC1_DMAC_ID_MC_0            48
+#define TC1_DMAC_ID_MC_1            49
+#define TC1_DMAC_ID_MC_LSB          48
+#define TC1_DMAC_ID_MC_MSB          49
+#define TC1_DMAC_ID_MC_SIZE         2
+#define TC1_DMAC_ID_OVF             47       // Indexes of DMA Overflow trigger
+#define TC1_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC1_GCLK_ID                 9        // Index of Generic Clock
+#define TC1_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC1_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC1_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc2.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc2.h
new file mode 100644
index 000000000..921e9eaf0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc2.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC2
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC2_INSTANCE_
+#define _SAME53_TC2_INSTANCE_
+
+/* ========== Register definition for TC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC2_CTRLA              (0x4101A000) /**< \brief (TC2) Control A */
+#define REG_TC2_CTRLBCLR           (0x4101A004) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET           (0x4101A005) /**< \brief (TC2) Control B Set */
+#define REG_TC2_EVCTRL             (0x4101A006) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR           (0x4101A008) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET           (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG            (0x4101A00A) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS             (0x4101A00B) /**< \brief (TC2) Status */
+#define REG_TC2_WAVE               (0x4101A00C) /**< \brief (TC2) Waveform Generation Control */
+#define REG_TC2_DRVCTRL            (0x4101A00D) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL            (0x4101A00F) /**< \brief (TC2) Debug Control */
+#define REG_TC2_SYNCBUSY           (0x4101A010) /**< \brief (TC2) Synchronization Status */
+#define REG_TC2_COUNT16_COUNT      (0x4101A014) /**< \brief (TC2) COUNT16 Count */
+#define REG_TC2_COUNT16_CC0        (0x4101A01C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
+#define REG_TC2_COUNT16_CC1        (0x4101A01E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
+#define REG_TC2_COUNT16_CCBUF0     (0x4101A030) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT16_CCBUF1     (0x4101A032) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT32_COUNT      (0x4101A014) /**< \brief (TC2) COUNT32 Count */
+#define REG_TC2_COUNT32_CC0        (0x4101A01C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
+#define REG_TC2_COUNT32_CC1        (0x4101A020) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
+#define REG_TC2_COUNT32_CCBUF0     (0x4101A030) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT32_CCBUF1     (0x4101A034) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT8_COUNT       (0x4101A014) /**< \brief (TC2) COUNT8 Count */
+#define REG_TC2_COUNT8_PER         (0x4101A01B) /**< \brief (TC2) COUNT8 Period */
+#define REG_TC2_COUNT8_CC0         (0x4101A01C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
+#define REG_TC2_COUNT8_CC1         (0x4101A01D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
+#define REG_TC2_COUNT8_PERBUF      (0x4101A02F) /**< \brief (TC2) COUNT8 Period Buffer */
+#define REG_TC2_COUNT8_CCBUF0      (0x4101A030) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT8_CCBUF1      (0x4101A031) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC2_CTRLA              (*(RwReg  *)0x4101A000UL) /**< \brief (TC2) Control A */
+#define REG_TC2_CTRLBCLR           (*(RwReg8 *)0x4101A004UL) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET           (*(RwReg8 *)0x4101A005UL) /**< \brief (TC2) Control B Set */
+#define REG_TC2_EVCTRL             (*(RwReg16*)0x4101A006UL) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR           (*(RwReg8 *)0x4101A008UL) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET           (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG            (*(RwReg8 *)0x4101A00AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS             (*(RwReg8 *)0x4101A00BUL) /**< \brief (TC2) Status */
+#define REG_TC2_WAVE               (*(RwReg8 *)0x4101A00CUL) /**< \brief (TC2) Waveform Generation Control */
+#define REG_TC2_DRVCTRL            (*(RwReg8 *)0x4101A00DUL) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL            (*(RwReg8 *)0x4101A00FUL) /**< \brief (TC2) Debug Control */
+#define REG_TC2_SYNCBUSY           (*(RoReg  *)0x4101A010UL) /**< \brief (TC2) Synchronization Status */
+#define REG_TC2_COUNT16_COUNT      (*(RwReg16*)0x4101A014UL) /**< \brief (TC2) COUNT16 Count */
+#define REG_TC2_COUNT16_CC0        (*(RwReg16*)0x4101A01CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
+#define REG_TC2_COUNT16_CC1        (*(RwReg16*)0x4101A01EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
+#define REG_TC2_COUNT16_CCBUF0     (*(RwReg16*)0x4101A030UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT16_CCBUF1     (*(RwReg16*)0x4101A032UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT32_COUNT      (*(RwReg  *)0x4101A014UL) /**< \brief (TC2) COUNT32 Count */
+#define REG_TC2_COUNT32_CC0        (*(RwReg  *)0x4101A01CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
+#define REG_TC2_COUNT32_CC1        (*(RwReg  *)0x4101A020UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
+#define REG_TC2_COUNT32_CCBUF0     (*(RwReg  *)0x4101A030UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT32_CCBUF1     (*(RwReg  *)0x4101A034UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT8_COUNT       (*(RwReg8 *)0x4101A014UL) /**< \brief (TC2) COUNT8 Count */
+#define REG_TC2_COUNT8_PER         (*(RwReg8 *)0x4101A01BUL) /**< \brief (TC2) COUNT8 Period */
+#define REG_TC2_COUNT8_CC0         (*(RwReg8 *)0x4101A01CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
+#define REG_TC2_COUNT8_CC1         (*(RwReg8 *)0x4101A01DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
+#define REG_TC2_COUNT8_PERBUF      (*(RwReg8 *)0x4101A02FUL) /**< \brief (TC2) COUNT8 Period Buffer */
+#define REG_TC2_COUNT8_CCBUF0      (*(RwReg8 *)0x4101A030UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT8_CCBUF1      (*(RwReg8 *)0x4101A031UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC2 peripheral ========== */
+#define TC2_CC_NUM                  2       
+#define TC2_DMAC_ID_MC_0            51
+#define TC2_DMAC_ID_MC_1            52
+#define TC2_DMAC_ID_MC_LSB          51
+#define TC2_DMAC_ID_MC_MSB          52
+#define TC2_DMAC_ID_MC_SIZE         2
+#define TC2_DMAC_ID_OVF             50       // Indexes of DMA Overflow trigger
+#define TC2_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC2_GCLK_ID                 26       // Index of Generic Clock
+#define TC2_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC2_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC2_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc3.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc3.h
new file mode 100644
index 000000000..cd4ae283a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc3.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC3_INSTANCE_
+#define _SAME53_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA              (0x4101C000) /**< \brief (TC3) Control A */
+#define REG_TC3_CTRLBCLR           (0x4101C004) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (0x4101C005) /**< \brief (TC3) Control B Set */
+#define REG_TC3_EVCTRL             (0x4101C006) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (0x4101C008) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (0x4101C009) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (0x4101C00A) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (0x4101C00B) /**< \brief (TC3) Status */
+#define REG_TC3_WAVE               (0x4101C00C) /**< \brief (TC3) Waveform Generation Control */
+#define REG_TC3_DRVCTRL            (0x4101C00D) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (0x4101C00F) /**< \brief (TC3) Debug Control */
+#define REG_TC3_SYNCBUSY           (0x4101C010) /**< \brief (TC3) Synchronization Status */
+#define REG_TC3_COUNT16_COUNT      (0x4101C014) /**< \brief (TC3) COUNT16 Count */
+#define REG_TC3_COUNT16_CC0        (0x4101C01C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
+#define REG_TC3_COUNT16_CC1        (0x4101C01E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
+#define REG_TC3_COUNT16_CCBUF0     (0x4101C030) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT16_CCBUF1     (0x4101C032) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT32_COUNT      (0x4101C014) /**< \brief (TC3) COUNT32 Count */
+#define REG_TC3_COUNT32_CC0        (0x4101C01C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
+#define REG_TC3_COUNT32_CC1        (0x4101C020) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
+#define REG_TC3_COUNT32_CCBUF0     (0x4101C030) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT32_CCBUF1     (0x4101C034) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT8_COUNT       (0x4101C014) /**< \brief (TC3) COUNT8 Count */
+#define REG_TC3_COUNT8_PER         (0x4101C01B) /**< \brief (TC3) COUNT8 Period */
+#define REG_TC3_COUNT8_CC0         (0x4101C01C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
+#define REG_TC3_COUNT8_CC1         (0x4101C01D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
+#define REG_TC3_COUNT8_PERBUF      (0x4101C02F) /**< \brief (TC3) COUNT8 Period Buffer */
+#define REG_TC3_COUNT8_CCBUF0      (0x4101C030) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT8_CCBUF1      (0x4101C031) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC3_CTRLA              (*(RwReg  *)0x4101C000UL) /**< \brief (TC3) Control A */
+#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x4101C004UL) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x4101C005UL) /**< \brief (TC3) Control B Set */
+#define REG_TC3_EVCTRL             (*(RwReg16*)0x4101C006UL) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR           (*(RwReg8 *)0x4101C008UL) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET           (*(RwReg8 *)0x4101C009UL) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG            (*(RwReg8 *)0x4101C00AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS             (*(RwReg8 *)0x4101C00BUL) /**< \brief (TC3) Status */
+#define REG_TC3_WAVE               (*(RwReg8 *)0x4101C00CUL) /**< \brief (TC3) Waveform Generation Control */
+#define REG_TC3_DRVCTRL            (*(RwReg8 *)0x4101C00DUL) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x4101C00FUL) /**< \brief (TC3) Debug Control */
+#define REG_TC3_SYNCBUSY           (*(RoReg  *)0x4101C010UL) /**< \brief (TC3) Synchronization Status */
+#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x4101C014UL) /**< \brief (TC3) COUNT16 Count */
+#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x4101C01CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
+#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x4101C01EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
+#define REG_TC3_COUNT16_CCBUF0     (*(RwReg16*)0x4101C030UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT16_CCBUF1     (*(RwReg16*)0x4101C032UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x4101C014UL) /**< \brief (TC3) COUNT32 Count */
+#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x4101C01CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
+#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x4101C020UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
+#define REG_TC3_COUNT32_CCBUF0     (*(RwReg  *)0x4101C030UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT32_CCBUF1     (*(RwReg  *)0x4101C034UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x4101C014UL) /**< \brief (TC3) COUNT8 Count */
+#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x4101C01BUL) /**< \brief (TC3) COUNT8 Period */
+#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x4101C01CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
+#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x4101C01DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
+#define REG_TC3_COUNT8_PERBUF      (*(RwReg8 *)0x4101C02FUL) /**< \brief (TC3) COUNT8 Period Buffer */
+#define REG_TC3_COUNT8_CCBUF0      (*(RwReg8 *)0x4101C030UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT8_CCBUF1      (*(RwReg8 *)0x4101C031UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC_NUM                  2       
+#define TC3_DMAC_ID_MC_0            54
+#define TC3_DMAC_ID_MC_1            55
+#define TC3_DMAC_ID_MC_LSB          54
+#define TC3_DMAC_ID_MC_MSB          55
+#define TC3_DMAC_ID_MC_SIZE         2
+#define TC3_DMAC_ID_OVF             53       // Indexes of DMA Overflow trigger
+#define TC3_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC3_GCLK_ID                 26       // Index of Generic Clock
+#define TC3_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC3_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC3_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc4.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc4.h
new file mode 100644
index 000000000..5ce4f2e91
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc4.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC4_INSTANCE_
+#define _SAME53_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA              (0x42001400) /**< \brief (TC4) Control A */
+#define REG_TC4_CTRLBCLR           (0x42001404) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (0x42001405) /**< \brief (TC4) Control B Set */
+#define REG_TC4_EVCTRL             (0x42001406) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (0x42001408) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (0x42001409) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (0x4200140A) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (0x4200140B) /**< \brief (TC4) Status */
+#define REG_TC4_WAVE               (0x4200140C) /**< \brief (TC4) Waveform Generation Control */
+#define REG_TC4_DRVCTRL            (0x4200140D) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (0x4200140F) /**< \brief (TC4) Debug Control */
+#define REG_TC4_SYNCBUSY           (0x42001410) /**< \brief (TC4) Synchronization Status */
+#define REG_TC4_COUNT16_COUNT      (0x42001414) /**< \brief (TC4) COUNT16 Count */
+#define REG_TC4_COUNT16_CC0        (0x4200141C) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
+#define REG_TC4_COUNT16_CC1        (0x4200141E) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
+#define REG_TC4_COUNT16_CCBUF0     (0x42001430) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT16_CCBUF1     (0x42001432) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT32_COUNT      (0x42001414) /**< \brief (TC4) COUNT32 Count */
+#define REG_TC4_COUNT32_CC0        (0x4200141C) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
+#define REG_TC4_COUNT32_CC1        (0x42001420) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
+#define REG_TC4_COUNT32_CCBUF0     (0x42001430) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT32_CCBUF1     (0x42001434) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT8_COUNT       (0x42001414) /**< \brief (TC4) COUNT8 Count */
+#define REG_TC4_COUNT8_PER         (0x4200141B) /**< \brief (TC4) COUNT8 Period */
+#define REG_TC4_COUNT8_CC0         (0x4200141C) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
+#define REG_TC4_COUNT8_CC1         (0x4200141D) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
+#define REG_TC4_COUNT8_PERBUF      (0x4200142F) /**< \brief (TC4) COUNT8 Period Buffer */
+#define REG_TC4_COUNT8_CCBUF0      (0x42001430) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT8_CCBUF1      (0x42001431) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC4_CTRLA              (*(RwReg  *)0x42001400UL) /**< \brief (TC4) Control A */
+#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42001404UL) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42001405UL) /**< \brief (TC4) Control B Set */
+#define REG_TC4_EVCTRL             (*(RwReg16*)0x42001406UL) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR           (*(RwReg8 *)0x42001408UL) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET           (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200140AUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS             (*(RwReg8 *)0x4200140BUL) /**< \brief (TC4) Status */
+#define REG_TC4_WAVE               (*(RwReg8 *)0x4200140CUL) /**< \brief (TC4) Waveform Generation Control */
+#define REG_TC4_DRVCTRL            (*(RwReg8 *)0x4200140DUL) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x4200140FUL) /**< \brief (TC4) Debug Control */
+#define REG_TC4_SYNCBUSY           (*(RoReg  *)0x42001410UL) /**< \brief (TC4) Synchronization Status */
+#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42001414UL) /**< \brief (TC4) COUNT16 Count */
+#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x4200141CUL) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
+#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200141EUL) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
+#define REG_TC4_COUNT16_CCBUF0     (*(RwReg16*)0x42001430UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT16_CCBUF1     (*(RwReg16*)0x42001432UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42001414UL) /**< \brief (TC4) COUNT32 Count */
+#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x4200141CUL) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
+#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x42001420UL) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
+#define REG_TC4_COUNT32_CCBUF0     (*(RwReg  *)0x42001430UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT32_CCBUF1     (*(RwReg  *)0x42001434UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42001414UL) /**< \brief (TC4) COUNT8 Count */
+#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x4200141BUL) /**< \brief (TC4) COUNT8 Period */
+#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x4200141CUL) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
+#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x4200141DUL) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
+#define REG_TC4_COUNT8_PERBUF      (*(RwReg8 *)0x4200142FUL) /**< \brief (TC4) COUNT8 Period Buffer */
+#define REG_TC4_COUNT8_CCBUF0      (*(RwReg8 *)0x42001430UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC4_COUNT8_CCBUF1      (*(RwReg8 *)0x42001431UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC_NUM                  2       
+#define TC4_DMAC_ID_MC_0            57
+#define TC4_DMAC_ID_MC_1            58
+#define TC4_DMAC_ID_MC_LSB          57
+#define TC4_DMAC_ID_MC_MSB          58
+#define TC4_DMAC_ID_MC_SIZE         2
+#define TC4_DMAC_ID_OVF             56       // Indexes of DMA Overflow trigger
+#define TC4_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC4_GCLK_ID                 30       // Index of Generic Clock
+#define TC4_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC4_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC4_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc5.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc5.h
new file mode 100644
index 000000000..05521fb17
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc5.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC5_INSTANCE_
+#define _SAME53_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA              (0x42001800) /**< \brief (TC5) Control A */
+#define REG_TC5_CTRLBCLR           (0x42001804) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (0x42001805) /**< \brief (TC5) Control B Set */
+#define REG_TC5_EVCTRL             (0x42001806) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (0x42001808) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (0x42001809) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (0x4200180A) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (0x4200180B) /**< \brief (TC5) Status */
+#define REG_TC5_WAVE               (0x4200180C) /**< \brief (TC5) Waveform Generation Control */
+#define REG_TC5_DRVCTRL            (0x4200180D) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (0x4200180F) /**< \brief (TC5) Debug Control */
+#define REG_TC5_SYNCBUSY           (0x42001810) /**< \brief (TC5) Synchronization Status */
+#define REG_TC5_COUNT16_COUNT      (0x42001814) /**< \brief (TC5) COUNT16 Count */
+#define REG_TC5_COUNT16_CC0        (0x4200181C) /**< \brief (TC5) COUNT16 Compare and Capture 0 */
+#define REG_TC5_COUNT16_CC1        (0x4200181E) /**< \brief (TC5) COUNT16 Compare and Capture 1 */
+#define REG_TC5_COUNT16_CCBUF0     (0x42001830) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT16_CCBUF1     (0x42001832) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT32_COUNT      (0x42001814) /**< \brief (TC5) COUNT32 Count */
+#define REG_TC5_COUNT32_CC0        (0x4200181C) /**< \brief (TC5) COUNT32 Compare and Capture 0 */
+#define REG_TC5_COUNT32_CC1        (0x42001820) /**< \brief (TC5) COUNT32 Compare and Capture 1 */
+#define REG_TC5_COUNT32_CCBUF0     (0x42001830) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT32_CCBUF1     (0x42001834) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT8_COUNT       (0x42001814) /**< \brief (TC5) COUNT8 Count */
+#define REG_TC5_COUNT8_PER         (0x4200181B) /**< \brief (TC5) COUNT8 Period */
+#define REG_TC5_COUNT8_CC0         (0x4200181C) /**< \brief (TC5) COUNT8 Compare and Capture 0 */
+#define REG_TC5_COUNT8_CC1         (0x4200181D) /**< \brief (TC5) COUNT8 Compare and Capture 1 */
+#define REG_TC5_COUNT8_PERBUF      (0x4200182F) /**< \brief (TC5) COUNT8 Period Buffer */
+#define REG_TC5_COUNT8_CCBUF0      (0x42001830) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT8_CCBUF1      (0x42001831) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC5_CTRLA              (*(RwReg  *)0x42001800UL) /**< \brief (TC5) Control A */
+#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42001804UL) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42001805UL) /**< \brief (TC5) Control B Set */
+#define REG_TC5_EVCTRL             (*(RwReg16*)0x42001806UL) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR           (*(RwReg8 *)0x42001808UL) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET           (*(RwReg8 *)0x42001809UL) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200180AUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS             (*(RwReg8 *)0x4200180BUL) /**< \brief (TC5) Status */
+#define REG_TC5_WAVE               (*(RwReg8 *)0x4200180CUL) /**< \brief (TC5) Waveform Generation Control */
+#define REG_TC5_DRVCTRL            (*(RwReg8 *)0x4200180DUL) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x4200180FUL) /**< \brief (TC5) Debug Control */
+#define REG_TC5_SYNCBUSY           (*(RoReg  *)0x42001810UL) /**< \brief (TC5) Synchronization Status */
+#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42001814UL) /**< \brief (TC5) COUNT16 Count */
+#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x4200181CUL) /**< \brief (TC5) COUNT16 Compare and Capture 0 */
+#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200181EUL) /**< \brief (TC5) COUNT16 Compare and Capture 1 */
+#define REG_TC5_COUNT16_CCBUF0     (*(RwReg16*)0x42001830UL) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT16_CCBUF1     (*(RwReg16*)0x42001832UL) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42001814UL) /**< \brief (TC5) COUNT32 Count */
+#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x4200181CUL) /**< \brief (TC5) COUNT32 Compare and Capture 0 */
+#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x42001820UL) /**< \brief (TC5) COUNT32 Compare and Capture 1 */
+#define REG_TC5_COUNT32_CCBUF0     (*(RwReg  *)0x42001830UL) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT32_CCBUF1     (*(RwReg  *)0x42001834UL) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42001814UL) /**< \brief (TC5) COUNT8 Count */
+#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x4200181BUL) /**< \brief (TC5) COUNT8 Period */
+#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x4200181CUL) /**< \brief (TC5) COUNT8 Compare and Capture 0 */
+#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x4200181DUL) /**< \brief (TC5) COUNT8 Compare and Capture 1 */
+#define REG_TC5_COUNT8_PERBUF      (*(RwReg8 *)0x4200182FUL) /**< \brief (TC5) COUNT8 Period Buffer */
+#define REG_TC5_COUNT8_CCBUF0      (*(RwReg8 *)0x42001830UL) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC5_COUNT8_CCBUF1      (*(RwReg8 *)0x42001831UL) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC_NUM                  2       
+#define TC5_DMAC_ID_MC_0            60
+#define TC5_DMAC_ID_MC_1            61
+#define TC5_DMAC_ID_MC_LSB          60
+#define TC5_DMAC_ID_MC_MSB          61
+#define TC5_DMAC_ID_MC_SIZE         2
+#define TC5_DMAC_ID_OVF             59       // Indexes of DMA Overflow trigger
+#define TC5_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC5_GCLK_ID                 30       // Index of Generic Clock
+#define TC5_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC5_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC5_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc6.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc6.h
new file mode 100644
index 000000000..1d5aad3db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc6.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC6_INSTANCE_
+#define _SAME53_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA              (0x43001400) /**< \brief (TC6) Control A */
+#define REG_TC6_CTRLBCLR           (0x43001404) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (0x43001405) /**< \brief (TC6) Control B Set */
+#define REG_TC6_EVCTRL             (0x43001406) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (0x43001408) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (0x43001409) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (0x4300140A) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (0x4300140B) /**< \brief (TC6) Status */
+#define REG_TC6_WAVE               (0x4300140C) /**< \brief (TC6) Waveform Generation Control */
+#define REG_TC6_DRVCTRL            (0x4300140D) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (0x4300140F) /**< \brief (TC6) Debug Control */
+#define REG_TC6_SYNCBUSY           (0x43001410) /**< \brief (TC6) Synchronization Status */
+#define REG_TC6_COUNT16_COUNT      (0x43001414) /**< \brief (TC6) COUNT16 Count */
+#define REG_TC6_COUNT16_CC0        (0x4300141C) /**< \brief (TC6) COUNT16 Compare and Capture 0 */
+#define REG_TC6_COUNT16_CC1        (0x4300141E) /**< \brief (TC6) COUNT16 Compare and Capture 1 */
+#define REG_TC6_COUNT16_CCBUF0     (0x43001430) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT16_CCBUF1     (0x43001432) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT32_COUNT      (0x43001414) /**< \brief (TC6) COUNT32 Count */
+#define REG_TC6_COUNT32_CC0        (0x4300141C) /**< \brief (TC6) COUNT32 Compare and Capture 0 */
+#define REG_TC6_COUNT32_CC1        (0x43001420) /**< \brief (TC6) COUNT32 Compare and Capture 1 */
+#define REG_TC6_COUNT32_CCBUF0     (0x43001430) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT32_CCBUF1     (0x43001434) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT8_COUNT       (0x43001414) /**< \brief (TC6) COUNT8 Count */
+#define REG_TC6_COUNT8_PER         (0x4300141B) /**< \brief (TC6) COUNT8 Period */
+#define REG_TC6_COUNT8_CC0         (0x4300141C) /**< \brief (TC6) COUNT8 Compare and Capture 0 */
+#define REG_TC6_COUNT8_CC1         (0x4300141D) /**< \brief (TC6) COUNT8 Compare and Capture 1 */
+#define REG_TC6_COUNT8_PERBUF      (0x4300142F) /**< \brief (TC6) COUNT8 Period Buffer */
+#define REG_TC6_COUNT8_CCBUF0      (0x43001430) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT8_CCBUF1      (0x43001431) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC6_CTRLA              (*(RwReg  *)0x43001400UL) /**< \brief (TC6) Control A */
+#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x43001404UL) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x43001405UL) /**< \brief (TC6) Control B Set */
+#define REG_TC6_EVCTRL             (*(RwReg16*)0x43001406UL) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR           (*(RwReg8 *)0x43001408UL) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET           (*(RwReg8 *)0x43001409UL) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4300140AUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS             (*(RwReg8 *)0x4300140BUL) /**< \brief (TC6) Status */
+#define REG_TC6_WAVE               (*(RwReg8 *)0x4300140CUL) /**< \brief (TC6) Waveform Generation Control */
+#define REG_TC6_DRVCTRL            (*(RwReg8 *)0x4300140DUL) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x4300140FUL) /**< \brief (TC6) Debug Control */
+#define REG_TC6_SYNCBUSY           (*(RoReg  *)0x43001410UL) /**< \brief (TC6) Synchronization Status */
+#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x43001414UL) /**< \brief (TC6) COUNT16 Count */
+#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x4300141CUL) /**< \brief (TC6) COUNT16 Compare and Capture 0 */
+#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4300141EUL) /**< \brief (TC6) COUNT16 Compare and Capture 1 */
+#define REG_TC6_COUNT16_CCBUF0     (*(RwReg16*)0x43001430UL) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT16_CCBUF1     (*(RwReg16*)0x43001432UL) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x43001414UL) /**< \brief (TC6) COUNT32 Count */
+#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x4300141CUL) /**< \brief (TC6) COUNT32 Compare and Capture 0 */
+#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x43001420UL) /**< \brief (TC6) COUNT32 Compare and Capture 1 */
+#define REG_TC6_COUNT32_CCBUF0     (*(RwReg  *)0x43001430UL) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT32_CCBUF1     (*(RwReg  *)0x43001434UL) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x43001414UL) /**< \brief (TC6) COUNT8 Count */
+#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x4300141BUL) /**< \brief (TC6) COUNT8 Period */
+#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x4300141CUL) /**< \brief (TC6) COUNT8 Compare and Capture 0 */
+#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x4300141DUL) /**< \brief (TC6) COUNT8 Compare and Capture 1 */
+#define REG_TC6_COUNT8_PERBUF      (*(RwReg8 *)0x4300142FUL) /**< \brief (TC6) COUNT8 Period Buffer */
+#define REG_TC6_COUNT8_CCBUF0      (*(RwReg8 *)0x43001430UL) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC6_COUNT8_CCBUF1      (*(RwReg8 *)0x43001431UL) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC_NUM                  2       
+#define TC6_DMAC_ID_MC_0            63
+#define TC6_DMAC_ID_MC_1            64
+#define TC6_DMAC_ID_MC_LSB          63
+#define TC6_DMAC_ID_MC_MSB          64
+#define TC6_DMAC_ID_MC_SIZE         2
+#define TC6_DMAC_ID_OVF             62       // Indexes of DMA Overflow trigger
+#define TC6_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC6_GCLK_ID                 39       // Index of Generic Clock
+#define TC6_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC6_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC6_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc7.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc7.h
new file mode 100644
index 000000000..e6baa4340
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tc7.h	
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TC7_INSTANCE_
+#define _SAME53_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA              (0x43001800) /**< \brief (TC7) Control A */
+#define REG_TC7_CTRLBCLR           (0x43001804) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (0x43001805) /**< \brief (TC7) Control B Set */
+#define REG_TC7_EVCTRL             (0x43001806) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (0x43001808) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (0x43001809) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (0x4300180A) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (0x4300180B) /**< \brief (TC7) Status */
+#define REG_TC7_WAVE               (0x4300180C) /**< \brief (TC7) Waveform Generation Control */
+#define REG_TC7_DRVCTRL            (0x4300180D) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (0x4300180F) /**< \brief (TC7) Debug Control */
+#define REG_TC7_SYNCBUSY           (0x43001810) /**< \brief (TC7) Synchronization Status */
+#define REG_TC7_COUNT16_COUNT      (0x43001814) /**< \brief (TC7) COUNT16 Count */
+#define REG_TC7_COUNT16_CC0        (0x4300181C) /**< \brief (TC7) COUNT16 Compare and Capture 0 */
+#define REG_TC7_COUNT16_CC1        (0x4300181E) /**< \brief (TC7) COUNT16 Compare and Capture 1 */
+#define REG_TC7_COUNT16_CCBUF0     (0x43001830) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT16_CCBUF1     (0x43001832) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT32_COUNT      (0x43001814) /**< \brief (TC7) COUNT32 Count */
+#define REG_TC7_COUNT32_CC0        (0x4300181C) /**< \brief (TC7) COUNT32 Compare and Capture 0 */
+#define REG_TC7_COUNT32_CC1        (0x43001820) /**< \brief (TC7) COUNT32 Compare and Capture 1 */
+#define REG_TC7_COUNT32_CCBUF0     (0x43001830) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT32_CCBUF1     (0x43001834) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT8_COUNT       (0x43001814) /**< \brief (TC7) COUNT8 Count */
+#define REG_TC7_COUNT8_PER         (0x4300181B) /**< \brief (TC7) COUNT8 Period */
+#define REG_TC7_COUNT8_CC0         (0x4300181C) /**< \brief (TC7) COUNT8 Compare and Capture 0 */
+#define REG_TC7_COUNT8_CC1         (0x4300181D) /**< \brief (TC7) COUNT8 Compare and Capture 1 */
+#define REG_TC7_COUNT8_PERBUF      (0x4300182F) /**< \brief (TC7) COUNT8 Period Buffer */
+#define REG_TC7_COUNT8_CCBUF0      (0x43001830) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT8_CCBUF1      (0x43001831) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC7_CTRLA              (*(RwReg  *)0x43001800UL) /**< \brief (TC7) Control A */
+#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x43001804UL) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x43001805UL) /**< \brief (TC7) Control B Set */
+#define REG_TC7_EVCTRL             (*(RwReg16*)0x43001806UL) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR           (*(RwReg8 *)0x43001808UL) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET           (*(RwReg8 *)0x43001809UL) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG            (*(RwReg8 *)0x4300180AUL) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS             (*(RwReg8 *)0x4300180BUL) /**< \brief (TC7) Status */
+#define REG_TC7_WAVE               (*(RwReg8 *)0x4300180CUL) /**< \brief (TC7) Waveform Generation Control */
+#define REG_TC7_DRVCTRL            (*(RwReg8 *)0x4300180DUL) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x4300180FUL) /**< \brief (TC7) Debug Control */
+#define REG_TC7_SYNCBUSY           (*(RoReg  *)0x43001810UL) /**< \brief (TC7) Synchronization Status */
+#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x43001814UL) /**< \brief (TC7) COUNT16 Count */
+#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x4300181CUL) /**< \brief (TC7) COUNT16 Compare and Capture 0 */
+#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x4300181EUL) /**< \brief (TC7) COUNT16 Compare and Capture 1 */
+#define REG_TC7_COUNT16_CCBUF0     (*(RwReg16*)0x43001830UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT16_CCBUF1     (*(RwReg16*)0x43001832UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x43001814UL) /**< \brief (TC7) COUNT32 Count */
+#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x4300181CUL) /**< \brief (TC7) COUNT32 Compare and Capture 0 */
+#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x43001820UL) /**< \brief (TC7) COUNT32 Compare and Capture 1 */
+#define REG_TC7_COUNT32_CCBUF0     (*(RwReg  *)0x43001830UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT32_CCBUF1     (*(RwReg  *)0x43001834UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x43001814UL) /**< \brief (TC7) COUNT8 Count */
+#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x4300181BUL) /**< \brief (TC7) COUNT8 Period */
+#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x4300181CUL) /**< \brief (TC7) COUNT8 Compare and Capture 0 */
+#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x4300181DUL) /**< \brief (TC7) COUNT8 Compare and Capture 1 */
+#define REG_TC7_COUNT8_PERBUF      (*(RwReg8 *)0x4300182FUL) /**< \brief (TC7) COUNT8 Period Buffer */
+#define REG_TC7_COUNT8_CCBUF0      (*(RwReg8 *)0x43001830UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC7_COUNT8_CCBUF1      (*(RwReg8 *)0x43001831UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC_NUM                  2       
+#define TC7_DMAC_ID_MC_0            66
+#define TC7_DMAC_ID_MC_1            67
+#define TC7_DMAC_ID_MC_LSB          66
+#define TC7_DMAC_ID_MC_MSB          67
+#define TC7_DMAC_ID_MC_SIZE         2
+#define TC7_DMAC_ID_OVF             65       // Indexes of DMA Overflow trigger
+#define TC7_EXT                     0        // Coding of implemented extended features (keep 0 value)
+#define TC7_GCLK_ID                 39       // Index of Generic Clock
+#define TC7_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
+#define TC7_OW_NUM                  2        // Number of Output Waveforms
+
+#endif /* _SAME53_TC7_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc0.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc0.h
new file mode 100644
index 000000000..fa85d13b2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc0.h	
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TCC0_INSTANCE_
+#define _SAME53_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA             (0x41016000) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (0x41016004) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (0x41016005) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (0x41016008) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (0x4101600C) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (0x41016010) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (0x41016014) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (0x41016018) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (0x4101601E) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (0x41016020) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (0x41016024) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (0x41016028) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (0x4101602C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (0x41016030) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (0x41016034) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (0x41016038) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (0x4101603C) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (0x41016040) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (0x41016044) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (0x41016048) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (0x4101604C) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (0x41016050) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_CC4               (0x41016054) /**< \brief (TCC0) Compare and Capture 4 */
+#define REG_TCC0_CC5               (0x41016058) /**< \brief (TCC0) Compare and Capture 5 */
+#define REG_TCC0_PATTBUF           (0x41016064) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_PERBUF            (0x4101606C) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCBUF0            (0x41016070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCBUF1            (0x41016074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCBUF2            (0x41016078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCBUF3            (0x4101607C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#define REG_TCC0_CCBUF4            (0x41016080) /**< \brief (TCC0) Compare and Capture Buffer 4 */
+#define REG_TCC0_CCBUF5            (0x41016084) /**< \brief (TCC0) Compare and Capture Buffer 5 */
+#else
+#define REG_TCC0_CTRLA             (*(RwReg  *)0x41016000UL) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x41016004UL) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x41016005UL) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x41016008UL) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4101600CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB            (*(RwReg  *)0x41016010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x41016014UL) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x41016018UL) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4101601EUL) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL            (*(RwReg  *)0x41016020UL) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR          (*(RwReg  *)0x41016024UL) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET          (*(RwReg  *)0x41016028UL) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4101602CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS            (*(RwReg  *)0x41016030UL) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT             (*(RwReg  *)0x41016034UL) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT              (*(RwReg16*)0x41016038UL) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE              (*(RwReg  *)0x4101603CUL) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER               (*(RwReg  *)0x41016040UL) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0               (*(RwReg  *)0x41016044UL) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1               (*(RwReg  *)0x41016048UL) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2               (*(RwReg  *)0x4101604CUL) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3               (*(RwReg  *)0x41016050UL) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_CC4               (*(RwReg  *)0x41016054UL) /**< \brief (TCC0) Compare and Capture 4 */
+#define REG_TCC0_CC5               (*(RwReg  *)0x41016058UL) /**< \brief (TCC0) Compare and Capture 5 */
+#define REG_TCC0_PATTBUF           (*(RwReg16*)0x41016064UL) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_PERBUF            (*(RwReg  *)0x4101606CUL) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCBUF0            (*(RwReg  *)0x41016070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCBUF1            (*(RwReg  *)0x41016074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCBUF2            (*(RwReg  *)0x41016078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCBUF3            (*(RwReg  *)0x4101607CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#define REG_TCC0_CCBUF4            (*(RwReg  *)0x41016080UL) /**< \brief (TCC0) Compare and Capture Buffer 4 */
+#define REG_TCC0_CCBUF5            (*(RwReg  *)0x41016084UL) /**< \brief (TCC0) Compare and Capture Buffer 5 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM                 6        // Number of Compare/Capture units
+#define TCC0_DITHERING              1        // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0           23
+#define TCC0_DMAC_ID_MC_1           24
+#define TCC0_DMAC_ID_MC_2           25
+#define TCC0_DMAC_ID_MC_3           26
+#define TCC0_DMAC_ID_MC_4           27
+#define TCC0_DMAC_ID_MC_5           28
+#define TCC0_DMAC_ID_MC_LSB         23
+#define TCC0_DMAC_ID_MC_MSB         28
+#define TCC0_DMAC_ID_MC_SIZE        6
+#define TCC0_DMAC_ID_OVF            22       // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
+#define TCC0_EXT                    31       // Coding of implemented extended features
+#define TCC0_GCLK_ID                25       // Index of Generic Clock
+#define TCC0_MASTER_SLAVE_MODE      1        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC0_OTMX                   1        // Output Matrix feature implemented
+#define TCC0_OW_NUM                 8        // Number of Output Waveforms
+#define TCC0_PG                     1        // Pattern Generation feature implemented
+#define TCC0_SIZE                   24      
+#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
+
+#endif /* _SAME53_TCC0_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc1.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc1.h
new file mode 100644
index 000000000..68df73ab1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc1.h	
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TCC1_INSTANCE_
+#define _SAME53_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA             (0x41018000) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (0x41018004) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (0x41018005) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (0x41018008) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (0x4101800C) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (0x41018010) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_WEXCTRL           (0x41018014) /**< \brief (TCC1) Waveform Extension Configuration */
+#define REG_TCC1_DRVCTRL           (0x41018018) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (0x4101801E) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (0x41018020) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (0x41018024) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (0x41018028) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (0x4101802C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (0x41018030) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (0x41018034) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (0x41018038) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (0x4101803C) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (0x41018040) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (0x41018044) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (0x41018048) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_CC2               (0x4101804C) /**< \brief (TCC1) Compare and Capture 2 */
+#define REG_TCC1_CC3               (0x41018050) /**< \brief (TCC1) Compare and Capture 3 */
+#define REG_TCC1_PATTBUF           (0x41018064) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_PERBUF            (0x4101806C) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCBUF0            (0x41018070) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCBUF1            (0x41018074) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#define REG_TCC1_CCBUF2            (0x41018078) /**< \brief (TCC1) Compare and Capture Buffer 2 */
+#define REG_TCC1_CCBUF3            (0x4101807C) /**< \brief (TCC1) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC1_CTRLA             (*(RwReg  *)0x41018000UL) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR          (*(RwReg8 *)0x41018004UL) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET          (*(RwReg8 *)0x41018005UL) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY          (*(RoReg  *)0x41018008UL) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA            (*(RwReg  *)0x4101800CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB            (*(RwReg  *)0x41018010UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_WEXCTRL           (*(RwReg  *)0x41018014UL) /**< \brief (TCC1) Waveform Extension Configuration */
+#define REG_TCC1_DRVCTRL           (*(RwReg  *)0x41018018UL) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL           (*(RwReg8 *)0x4101801EUL) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL            (*(RwReg  *)0x41018020UL) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR          (*(RwReg  *)0x41018024UL) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET          (*(RwReg  *)0x41018028UL) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG           (*(RwReg  *)0x4101802CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS            (*(RwReg  *)0x41018030UL) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT             (*(RwReg  *)0x41018034UL) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT              (*(RwReg16*)0x41018038UL) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE              (*(RwReg  *)0x4101803CUL) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER               (*(RwReg  *)0x41018040UL) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0               (*(RwReg  *)0x41018044UL) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1               (*(RwReg  *)0x41018048UL) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_CC2               (*(RwReg  *)0x4101804CUL) /**< \brief (TCC1) Compare and Capture 2 */
+#define REG_TCC1_CC3               (*(RwReg  *)0x41018050UL) /**< \brief (TCC1) Compare and Capture 3 */
+#define REG_TCC1_PATTBUF           (*(RwReg16*)0x41018064UL) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_PERBUF            (*(RwReg  *)0x4101806CUL) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCBUF0            (*(RwReg  *)0x41018070UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCBUF1            (*(RwReg  *)0x41018074UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#define REG_TCC1_CCBUF2            (*(RwReg  *)0x41018078UL) /**< \brief (TCC1) Compare and Capture Buffer 2 */
+#define REG_TCC1_CCBUF3            (*(RwReg  *)0x4101807CUL) /**< \brief (TCC1) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM                 4        // Number of Compare/Capture units
+#define TCC1_DITHERING              1        // Dithering feature implemented
+#define TCC1_DMAC_ID_MC_0           30
+#define TCC1_DMAC_ID_MC_1           31
+#define TCC1_DMAC_ID_MC_2           32
+#define TCC1_DMAC_ID_MC_3           33
+#define TCC1_DMAC_ID_MC_LSB         30
+#define TCC1_DMAC_ID_MC_MSB         33
+#define TCC1_DMAC_ID_MC_SIZE        4
+#define TCC1_DMAC_ID_OVF            29       // DMA overflow/underflow/retrigger trigger
+#define TCC1_DTI                    1        // Dead-Time-Insertion feature implemented
+#define TCC1_EXT                    31       // Coding of implemented extended features
+#define TCC1_GCLK_ID                25       // Index of Generic Clock
+#define TCC1_MASTER_SLAVE_MODE      2        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC1_OTMX                   1        // Output Matrix feature implemented
+#define TCC1_OW_NUM                 8        // Number of Output Waveforms
+#define TCC1_PG                     1        // Pattern Generation feature implemented
+#define TCC1_SIZE                   24      
+#define TCC1_SWAP                   1        // DTI outputs swap feature implemented
+
+#endif /* _SAME53_TCC1_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc2.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc2.h
new file mode 100644
index 000000000..a07f666b9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc2.h	
@@ -0,0 +1,106 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TCC2_INSTANCE_
+#define _SAME53_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA             (0x42000C00) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (0x42000C04) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (0x42000C05) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (0x42000C08) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (0x42000C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (0x42000C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_WEXCTRL           (0x42000C14) /**< \brief (TCC2) Waveform Extension Configuration */
+#define REG_TCC2_DRVCTRL           (0x42000C18) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (0x42000C1E) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (0x42000C20) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (0x42000C24) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (0x42000C28) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (0x42000C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (0x42000C30) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (0x42000C34) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (0x42000C3C) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (0x42000C40) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (0x42000C44) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (0x42000C48) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_CC2               (0x42000C4C) /**< \brief (TCC2) Compare and Capture 2 */
+#define REG_TCC2_PERBUF            (0x42000C6C) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCBUF0            (0x42000C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCBUF1            (0x42000C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#define REG_TCC2_CCBUF2            (0x42000C78) /**< \brief (TCC2) Compare and Capture Buffer 2 */
+#else
+#define REG_TCC2_CTRLA             (*(RwReg  *)0x42000C00UL) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR          (*(RwReg8 *)0x42000C04UL) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET          (*(RwReg8 *)0x42000C05UL) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY          (*(RoReg  *)0x42000C08UL) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA            (*(RwReg  *)0x42000C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB            (*(RwReg  *)0x42000C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_WEXCTRL           (*(RwReg  *)0x42000C14UL) /**< \brief (TCC2) Waveform Extension Configuration */
+#define REG_TCC2_DRVCTRL           (*(RwReg  *)0x42000C18UL) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL           (*(RwReg8 *)0x42000C1EUL) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL            (*(RwReg  *)0x42000C20UL) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR          (*(RwReg  *)0x42000C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET          (*(RwReg  *)0x42000C28UL) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG           (*(RwReg  *)0x42000C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS            (*(RwReg  *)0x42000C30UL) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT             (*(RwReg  *)0x42000C34UL) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE              (*(RwReg  *)0x42000C3CUL) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER               (*(RwReg  *)0x42000C40UL) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0               (*(RwReg  *)0x42000C44UL) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1               (*(RwReg  *)0x42000C48UL) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_CC2               (*(RwReg  *)0x42000C4CUL) /**< \brief (TCC2) Compare and Capture 2 */
+#define REG_TCC2_PERBUF            (*(RwReg  *)0x42000C6CUL) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCBUF0            (*(RwReg  *)0x42000C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCBUF1            (*(RwReg  *)0x42000C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#define REG_TCC2_CCBUF2            (*(RwReg  *)0x42000C78UL) /**< \brief (TCC2) Compare and Capture Buffer 2 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM                 3        // Number of Compare/Capture units
+#define TCC2_DITHERING              0        // Dithering feature implemented
+#define TCC2_DMAC_ID_MC_0           35
+#define TCC2_DMAC_ID_MC_1           36
+#define TCC2_DMAC_ID_MC_2           37
+#define TCC2_DMAC_ID_MC_LSB         35
+#define TCC2_DMAC_ID_MC_MSB         37
+#define TCC2_DMAC_ID_MC_SIZE        3
+#define TCC2_DMAC_ID_OVF            34       // DMA overflow/underflow/retrigger trigger
+#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC2_EXT                    1        // Coding of implemented extended features
+#define TCC2_GCLK_ID                29       // Index of Generic Clock
+#define TCC2_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC2_OTMX                   1        // Output Matrix feature implemented
+#define TCC2_OW_NUM                 3        // Number of Output Waveforms
+#define TCC2_PG                     0        // Pattern Generation feature implemented
+#define TCC2_SIZE                   16      
+#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
+
+#endif /* _SAME53_TCC2_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc3.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc3.h
new file mode 100644
index 000000000..fbabf01bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc3.h	
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC3
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TCC3_INSTANCE_
+#define _SAME53_TCC3_INSTANCE_
+
+/* ========== Register definition for TCC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC3_CTRLA             (0x42001000) /**< \brief (TCC3) Control A */
+#define REG_TCC3_CTRLBCLR          (0x42001004) /**< \brief (TCC3) Control B Clear */
+#define REG_TCC3_CTRLBSET          (0x42001005) /**< \brief (TCC3) Control B Set */
+#define REG_TCC3_SYNCBUSY          (0x42001008) /**< \brief (TCC3) Synchronization Busy */
+#define REG_TCC3_FCTRLA            (0x4200100C) /**< \brief (TCC3) Recoverable Fault A Configuration */
+#define REG_TCC3_FCTRLB            (0x42001010) /**< \brief (TCC3) Recoverable Fault B Configuration */
+#define REG_TCC3_DRVCTRL           (0x42001018) /**< \brief (TCC3) Driver Control */
+#define REG_TCC3_DBGCTRL           (0x4200101E) /**< \brief (TCC3) Debug Control */
+#define REG_TCC3_EVCTRL            (0x42001020) /**< \brief (TCC3) Event Control */
+#define REG_TCC3_INTENCLR          (0x42001024) /**< \brief (TCC3) Interrupt Enable Clear */
+#define REG_TCC3_INTENSET          (0x42001028) /**< \brief (TCC3) Interrupt Enable Set */
+#define REG_TCC3_INTFLAG           (0x4200102C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
+#define REG_TCC3_STATUS            (0x42001030) /**< \brief (TCC3) Status */
+#define REG_TCC3_COUNT             (0x42001034) /**< \brief (TCC3) Count */
+#define REG_TCC3_WAVE              (0x4200103C) /**< \brief (TCC3) Waveform Control */
+#define REG_TCC3_PER               (0x42001040) /**< \brief (TCC3) Period */
+#define REG_TCC3_CC0               (0x42001044) /**< \brief (TCC3) Compare and Capture 0 */
+#define REG_TCC3_CC1               (0x42001048) /**< \brief (TCC3) Compare and Capture 1 */
+#define REG_TCC3_PERBUF            (0x4200106C) /**< \brief (TCC3) Period Buffer */
+#define REG_TCC3_CCBUF0            (0x42001070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
+#define REG_TCC3_CCBUF1            (0x42001074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC3_CTRLA             (*(RwReg  *)0x42001000UL) /**< \brief (TCC3) Control A */
+#define REG_TCC3_CTRLBCLR          (*(RwReg8 *)0x42001004UL) /**< \brief (TCC3) Control B Clear */
+#define REG_TCC3_CTRLBSET          (*(RwReg8 *)0x42001005UL) /**< \brief (TCC3) Control B Set */
+#define REG_TCC3_SYNCBUSY          (*(RoReg  *)0x42001008UL) /**< \brief (TCC3) Synchronization Busy */
+#define REG_TCC3_FCTRLA            (*(RwReg  *)0x4200100CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
+#define REG_TCC3_FCTRLB            (*(RwReg  *)0x42001010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
+#define REG_TCC3_DRVCTRL           (*(RwReg  *)0x42001018UL) /**< \brief (TCC3) Driver Control */
+#define REG_TCC3_DBGCTRL           (*(RwReg8 *)0x4200101EUL) /**< \brief (TCC3) Debug Control */
+#define REG_TCC3_EVCTRL            (*(RwReg  *)0x42001020UL) /**< \brief (TCC3) Event Control */
+#define REG_TCC3_INTENCLR          (*(RwReg  *)0x42001024UL) /**< \brief (TCC3) Interrupt Enable Clear */
+#define REG_TCC3_INTENSET          (*(RwReg  *)0x42001028UL) /**< \brief (TCC3) Interrupt Enable Set */
+#define REG_TCC3_INTFLAG           (*(RwReg  *)0x4200102CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
+#define REG_TCC3_STATUS            (*(RwReg  *)0x42001030UL) /**< \brief (TCC3) Status */
+#define REG_TCC3_COUNT             (*(RwReg  *)0x42001034UL) /**< \brief (TCC3) Count */
+#define REG_TCC3_WAVE              (*(RwReg  *)0x4200103CUL) /**< \brief (TCC3) Waveform Control */
+#define REG_TCC3_PER               (*(RwReg  *)0x42001040UL) /**< \brief (TCC3) Period */
+#define REG_TCC3_CC0               (*(RwReg  *)0x42001044UL) /**< \brief (TCC3) Compare and Capture 0 */
+#define REG_TCC3_CC1               (*(RwReg  *)0x42001048UL) /**< \brief (TCC3) Compare and Capture 1 */
+#define REG_TCC3_PERBUF            (*(RwReg  *)0x4200106CUL) /**< \brief (TCC3) Period Buffer */
+#define REG_TCC3_CCBUF0            (*(RwReg  *)0x42001070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
+#define REG_TCC3_CCBUF1            (*(RwReg  *)0x42001074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC3 peripheral ========== */
+#define TCC3_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC3_DITHERING              0        // Dithering feature implemented
+#define TCC3_DMAC_ID_MC_0           39
+#define TCC3_DMAC_ID_MC_1           40
+#define TCC3_DMAC_ID_MC_LSB         39
+#define TCC3_DMAC_ID_MC_MSB         40
+#define TCC3_DMAC_ID_MC_SIZE        2
+#define TCC3_DMAC_ID_OVF            38       // DMA overflow/underflow/retrigger trigger
+#define TCC3_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC3_EXT                    0        // Coding of implemented extended features
+#define TCC3_GCLK_ID                29       // Index of Generic Clock
+#define TCC3_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC3_OTMX                   0        // Output Matrix feature implemented
+#define TCC3_OW_NUM                 2        // Number of Output Waveforms
+#define TCC3_PG                     0        // Pattern Generation feature implemented
+#define TCC3_SIZE                   16      
+#define TCC3_SWAP                   0        // DTI outputs swap feature implemented
+
+#endif /* _SAME53_TCC3_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc4.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc4.h
new file mode 100644
index 000000000..047fd8572
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/tcc4.h	
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC4
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TCC4_INSTANCE_
+#define _SAME53_TCC4_INSTANCE_
+
+/* ========== Register definition for TCC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC4_CTRLA             (0x43001000) /**< \brief (TCC4) Control A */
+#define REG_TCC4_CTRLBCLR          (0x43001004) /**< \brief (TCC4) Control B Clear */
+#define REG_TCC4_CTRLBSET          (0x43001005) /**< \brief (TCC4) Control B Set */
+#define REG_TCC4_SYNCBUSY          (0x43001008) /**< \brief (TCC4) Synchronization Busy */
+#define REG_TCC4_FCTRLA            (0x4300100C) /**< \brief (TCC4) Recoverable Fault A Configuration */
+#define REG_TCC4_FCTRLB            (0x43001010) /**< \brief (TCC4) Recoverable Fault B Configuration */
+#define REG_TCC4_DRVCTRL           (0x43001018) /**< \brief (TCC4) Driver Control */
+#define REG_TCC4_DBGCTRL           (0x4300101E) /**< \brief (TCC4) Debug Control */
+#define REG_TCC4_EVCTRL            (0x43001020) /**< \brief (TCC4) Event Control */
+#define REG_TCC4_INTENCLR          (0x43001024) /**< \brief (TCC4) Interrupt Enable Clear */
+#define REG_TCC4_INTENSET          (0x43001028) /**< \brief (TCC4) Interrupt Enable Set */
+#define REG_TCC4_INTFLAG           (0x4300102C) /**< \brief (TCC4) Interrupt Flag Status and Clear */
+#define REG_TCC4_STATUS            (0x43001030) /**< \brief (TCC4) Status */
+#define REG_TCC4_COUNT             (0x43001034) /**< \brief (TCC4) Count */
+#define REG_TCC4_WAVE              (0x4300103C) /**< \brief (TCC4) Waveform Control */
+#define REG_TCC4_PER               (0x43001040) /**< \brief (TCC4) Period */
+#define REG_TCC4_CC0               (0x43001044) /**< \brief (TCC4) Compare and Capture 0 */
+#define REG_TCC4_CC1               (0x43001048) /**< \brief (TCC4) Compare and Capture 1 */
+#define REG_TCC4_PERBUF            (0x4300106C) /**< \brief (TCC4) Period Buffer */
+#define REG_TCC4_CCBUF0            (0x43001070) /**< \brief (TCC4) Compare and Capture Buffer 0 */
+#define REG_TCC4_CCBUF1            (0x43001074) /**< \brief (TCC4) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC4_CTRLA             (*(RwReg  *)0x43001000UL) /**< \brief (TCC4) Control A */
+#define REG_TCC4_CTRLBCLR          (*(RwReg8 *)0x43001004UL) /**< \brief (TCC4) Control B Clear */
+#define REG_TCC4_CTRLBSET          (*(RwReg8 *)0x43001005UL) /**< \brief (TCC4) Control B Set */
+#define REG_TCC4_SYNCBUSY          (*(RoReg  *)0x43001008UL) /**< \brief (TCC4) Synchronization Busy */
+#define REG_TCC4_FCTRLA            (*(RwReg  *)0x4300100CUL) /**< \brief (TCC4) Recoverable Fault A Configuration */
+#define REG_TCC4_FCTRLB            (*(RwReg  *)0x43001010UL) /**< \brief (TCC4) Recoverable Fault B Configuration */
+#define REG_TCC4_DRVCTRL           (*(RwReg  *)0x43001018UL) /**< \brief (TCC4) Driver Control */
+#define REG_TCC4_DBGCTRL           (*(RwReg8 *)0x4300101EUL) /**< \brief (TCC4) Debug Control */
+#define REG_TCC4_EVCTRL            (*(RwReg  *)0x43001020UL) /**< \brief (TCC4) Event Control */
+#define REG_TCC4_INTENCLR          (*(RwReg  *)0x43001024UL) /**< \brief (TCC4) Interrupt Enable Clear */
+#define REG_TCC4_INTENSET          (*(RwReg  *)0x43001028UL) /**< \brief (TCC4) Interrupt Enable Set */
+#define REG_TCC4_INTFLAG           (*(RwReg  *)0x4300102CUL) /**< \brief (TCC4) Interrupt Flag Status and Clear */
+#define REG_TCC4_STATUS            (*(RwReg  *)0x43001030UL) /**< \brief (TCC4) Status */
+#define REG_TCC4_COUNT             (*(RwReg  *)0x43001034UL) /**< \brief (TCC4) Count */
+#define REG_TCC4_WAVE              (*(RwReg  *)0x4300103CUL) /**< \brief (TCC4) Waveform Control */
+#define REG_TCC4_PER               (*(RwReg  *)0x43001040UL) /**< \brief (TCC4) Period */
+#define REG_TCC4_CC0               (*(RwReg  *)0x43001044UL) /**< \brief (TCC4) Compare and Capture 0 */
+#define REG_TCC4_CC1               (*(RwReg  *)0x43001048UL) /**< \brief (TCC4) Compare and Capture 1 */
+#define REG_TCC4_PERBUF            (*(RwReg  *)0x4300106CUL) /**< \brief (TCC4) Period Buffer */
+#define REG_TCC4_CCBUF0            (*(RwReg  *)0x43001070UL) /**< \brief (TCC4) Compare and Capture Buffer 0 */
+#define REG_TCC4_CCBUF1            (*(RwReg  *)0x43001074UL) /**< \brief (TCC4) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC4 peripheral ========== */
+#define TCC4_CC_NUM                 2        // Number of Compare/Capture units
+#define TCC4_DITHERING              0        // Dithering feature implemented
+#define TCC4_DMAC_ID_MC_0           42
+#define TCC4_DMAC_ID_MC_1           43
+#define TCC4_DMAC_ID_MC_LSB         42
+#define TCC4_DMAC_ID_MC_MSB         43
+#define TCC4_DMAC_ID_MC_SIZE        2
+#define TCC4_DMAC_ID_OVF            41       // DMA overflow/underflow/retrigger trigger
+#define TCC4_DTI                    0        // Dead-Time-Insertion feature implemented
+#define TCC4_EXT                    0        // Coding of implemented extended features
+#define TCC4_GCLK_ID                38       // Index of Generic Clock
+#define TCC4_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC4_OTMX                   0        // Output Matrix feature implemented
+#define TCC4_OW_NUM                 2        // Number of Output Waveforms
+#define TCC4_PG                     0        // Pattern Generation feature implemented
+#define TCC4_SIZE                   16      
+#define TCC4_SWAP                   0        // DTI outputs swap feature implemented
+
+#endif /* _SAME53_TCC4_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/trng.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/trng.h
new file mode 100644
index 000000000..1c730761e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/trng.h	
@@ -0,0 +1,51 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TRNG
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_TRNG_INSTANCE_
+#define _SAME53_TRNG_INSTANCE_
+
+/* ========== Register definition for TRNG peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TRNG_CTRLA             (0x42002800) /**< \brief (TRNG) Control A */
+#define REG_TRNG_EVCTRL            (0x42002804) /**< \brief (TRNG) Event Control */
+#define REG_TRNG_INTENCLR          (0x42002808) /**< \brief (TRNG) Interrupt Enable Clear */
+#define REG_TRNG_INTENSET          (0x42002809) /**< \brief (TRNG) Interrupt Enable Set */
+#define REG_TRNG_INTFLAG           (0x4200280A) /**< \brief (TRNG) Interrupt Flag Status and Clear */
+#define REG_TRNG_DATA              (0x42002820) /**< \brief (TRNG) Output Data */
+#else
+#define REG_TRNG_CTRLA             (*(RwReg8 *)0x42002800UL) /**< \brief (TRNG) Control A */
+#define REG_TRNG_EVCTRL            (*(RwReg8 *)0x42002804UL) /**< \brief (TRNG) Event Control */
+#define REG_TRNG_INTENCLR          (*(RwReg8 *)0x42002808UL) /**< \brief (TRNG) Interrupt Enable Clear */
+#define REG_TRNG_INTENSET          (*(RwReg8 *)0x42002809UL) /**< \brief (TRNG) Interrupt Enable Set */
+#define REG_TRNG_INTFLAG           (*(RwReg8 *)0x4200280AUL) /**< \brief (TRNG) Interrupt Flag Status and Clear */
+#define REG_TRNG_DATA              (*(RoReg  *)0x42002820UL) /**< \brief (TRNG) Output Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME53_TRNG_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/usb.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/usb.h
new file mode 100644
index 000000000..0540fd52c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/usb.h	
@@ -0,0 +1,343 @@
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_USB_INSTANCE_
+#define _SAME53_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA              (0x41000000) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (0x41000002) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (0x41000003) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (0x4100000D) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (0x41000024) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (0x41000028) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (0x41000008) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (0x4100000A) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (0x4100000C) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (0x41000008) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (0x4100000A) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (0x4100000C) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (0x41000010) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (0x41000012) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (0x41000014) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (0x41000018) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (0x4100001C) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (0x41000020) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (0x41000100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41000103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41000104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41000105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41000106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41000107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41000108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41000109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (0x41000120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41000123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41000124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41000125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41000126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41000127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41000128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41000129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (0x41000140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41000143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41000144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41000145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41000146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41000147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41000148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41000149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (0x41000160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41000163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41000164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41000165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41000166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41000167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41000168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41000169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (0x41000180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41000183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41000184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41000185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41000186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41000187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41000188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41000189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (0x410001A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410001A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410001A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410001A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410001A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410001A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410001A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410001A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (0x410001C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410001C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410001C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410001C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410001C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410001C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410001C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410001C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (0x410001E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410001E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410001E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410001E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410001E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410001E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410001E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410001E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA              (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY           (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL            (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS          (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD            (*(RwReg  *)0x41000024UL) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL             (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB       (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD        (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS      (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM        (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR    (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET    (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG     (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY   (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB         (*(RwReg16*)0x41000008UL) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC         (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS        (*(RwReg8 *)0x4100000CUL) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM          (*(RwReg16*)0x41000010UL) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH      (*(RoReg8 *)0x41000012UL) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR      (*(RwReg16*)0x41000014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET      (*(RwReg16*)0x41000018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG       (*(RwReg16*)0x4100001CUL) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY      (*(RoReg16*)0x41000020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0    (*(RwReg8 *)0x41000100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41000103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1    (*(RwReg8 *)0x41000120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41000123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2    (*(RwReg8 *)0x41000140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41000143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3    (*(RwReg8 *)0x41000160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41000163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4    (*(RwReg8 *)0x41000180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41000183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5    (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410001A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6    (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410001C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7    (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410001E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_AHB_2_USB_FIFO_DEPTH    4        // bytes number, should be at least 2, and 2^n (4,8,16 ...)
+#define USB_AHB_2_USB_RD_DATA_BITS  8        // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
+#define USB_AHB_2_USB_WR_DATA_BITS  32       // 8, 16 or 32 : here, AHB transfer is made in word mode
+#define USB_AHB_2_USB_WR_THRESHOLD  2        // as soon as there are N bytes-free inside the fifo, ahb read transfer is requested
+#define USB_DATA_BUS_16_8           0        // UTMI/SIE data bus size : 0 -> 8 bits, 1 -> 16 bits
+#define USB_EPNUM                   8        // parameter for rtl : max of ENDPOINT and PIPE NUM
+#define USB_EPT_NUM                 8        // Number of USB end points
+#define USB_GCLK_ID                 10       // Index of Generic Clock
+#define USB_INITIAL_CONTROL_QOS     3        // CONTROL QOS RESET value
+#define USB_INITIAL_DATA_QOS        3        // DATA QOS RESET value
+#define USB_MISSING_SOF_DET_IMPLEMENTED 1        // 48 mHz xPLL feature implemented
+#define USB_PIPE_NUM                8        // Number of USB pipes
+#define USB_SYSTEM_CLOCK_IS_CKUSB   0        // Dual (1'b0) or Single (1'b1) clock system
+#define USB_USB_2_AHB_FIFO_DEPTH    4        // bytes number, should be at least 2, and 2^n (4,8,16 ...)
+#define USB_USB_2_AHB_RD_DATA_BITS  16       // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
+#define USB_USB_2_AHB_RD_THRESHOLD  2        // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested
+#define USB_USB_2_AHB_WR_DATA_BITS  8        // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode
+
+#endif /* _SAME53_USB_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/wdt.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/wdt.h
new file mode 100644
index 000000000..427c5564b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/instance/wdt.h	
@@ -0,0 +1,55 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_WDT_INSTANCE_
+#define _SAME53_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRLA              (0x40002000) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (0x40002001) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (0x40002005) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_SYNCBUSY           (0x40002008) /**< \brief (WDT) Synchronization Busy */
+#define REG_WDT_CLEAR              (0x4000200C) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRLA              (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG             (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET           (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_SYNCBUSY           (*(RoReg  *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */
+#define REG_WDT_CLEAR              (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAME53_WDT_INSTANCE_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j18a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j18a.h
new file mode 100644
index 000000000..e88a8d2d2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j18a.h	
@@ -0,0 +1,1911 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME53J18A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53J18A_PIO_
+#define _SAME53J18A_PIO_
+
+#define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                           12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL_(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                           13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL_(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                           20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL_(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                           21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL_(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                           32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                           33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                           34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                           35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                           36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                           37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                           38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                           39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                           40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                           41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                           42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL_(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                           43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL_(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                           44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL_(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                           45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL_(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                           46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL_(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                           47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL_(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                           48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL_(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                           49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL_(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                           54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL_(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                           55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL_(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                           62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL_(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                           63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL_(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK            _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK             _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK     ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK   (_UL_(1) << 30)
+#define PIN_PB30H_CM4_SWO              _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO               _L_(7)
+#define PINMUX_PB30H_CM4_SWO       ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO     (_UL_(1) << 30)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0          _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0          _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0  ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0  (_UL_(1) <<  3)
+#define PIN_PA04B_ANAREF_VREF1          _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1          _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1  ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1  (_UL_(1) <<  4)
+#define PIN_PA06B_ANAREF_VREF2          _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2          _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2  ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2  (_UL_(1) <<  6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0             _L_(12)
+#define PINMUX_PA30M_GCLK_IO0      ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0    (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0             _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0             _L_(12)
+#define PINMUX_PB14M_GCLK_IO0      ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0             _L_(12)
+#define PINMUX_PA14M_GCLK_IO0      ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0             _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0             _L_(12)
+#define PINMUX_PB22M_GCLK_IO0      ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0    (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1             _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1             _L_(12)
+#define PINMUX_PB15M_GCLK_IO1      ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1             _L_(12)
+#define PINMUX_PA15M_GCLK_IO1      ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1             _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1             _L_(12)
+#define PINMUX_PB23M_GCLK_IO1      ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1    (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1             _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1             _L_(12)
+#define PINMUX_PA27M_GCLK_IO1      ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1    (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2             _L_(12)
+#define PINMUX_PA16M_GCLK_IO2      ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2             _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2             _L_(12)
+#define PINMUX_PB16M_GCLK_IO2      ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3             _L_(12)
+#define PINMUX_PA17M_GCLK_IO3      ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3             _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3             _L_(12)
+#define PINMUX_PB17M_GCLK_IO3      ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4             _L_(12)
+#define PINMUX_PA10M_GCLK_IO4      ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4             _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4             _L_(12)
+#define PINMUX_PB10M_GCLK_IO4      ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PA11M_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5             _L_(12)
+#define PINMUX_PA11M_GCLK_IO5      ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5             _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5             _L_(12)
+#define PINMUX_PB11M_GCLK_IO5      ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB12M_GCLK_IO6             _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6             _L_(12)
+#define PINMUX_PB12M_GCLK_IO6      ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6    (_UL_(1) << 12)
+#define PIN_PB13M_GCLK_IO7             _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7             _L_(12)
+#define PINMUX_PB13M_GCLK_IO7      ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7    (_UL_(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8          _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8   ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL_(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9          _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9   ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11         _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11  ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14         _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14  ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15         _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15  ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L_(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
+#define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
+#define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
+#define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
+#define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2         _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2  ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2  (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3         _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3  ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3  (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0               _L_(4)
+#define PINMUX_PA04E_TC0_WO0       ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0     (_UL_(1) <<  4)
+#define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0               _L_(4)
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
+#define PIN_PB30E_TC0_WO0              _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0               _L_(4)
+#define PINMUX_PB30E_TC0_WO0       ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0     (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1               _L_(4)
+#define PINMUX_PA05E_TC0_WO1       ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1     (_UL_(1) <<  5)
+#define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1               _L_(4)
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
+#define PIN_PB31E_TC0_WO1              _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1               _L_(4)
+#define PINMUX_PB31E_TC0_WO1       ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1     (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0               _L_(4)
+#define PINMUX_PA06E_TC1_WO0       ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0     (_UL_(1) <<  6)
+#define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0               _L_(4)
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1               _L_(4)
+#define PINMUX_PA07E_TC1_WO1       ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1     (_UL_(1) <<  7)
+#define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1               _L_(4)
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM               _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM                _L_(7)
+#define PINMUX_PA24H_USB_DM        ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM      (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP               _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP                _L_(7)
+#define PINMUX_PA25H_USB_DP        ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP      (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ         _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ  ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ  (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ         _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ  ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ  (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0          _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0  ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0  (_UL_(1) <<  9)
+#define PIN_PA12C_SERCOM2_PAD0         _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1          _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1  ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1  (_UL_(1) <<  8)
+#define PIN_PA13C_SERCOM2_PAD1         _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0         _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0          _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0  ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0  (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
+#define PIN_PA16D_SERCOM3_PAD1         _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1          _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1  ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1  (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0             _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0              _L_(6)
+#define PINMUX_PA20G_TCC0_WO0      ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0    (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0             _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0              _L_(6)
+#define PINMUX_PB12G_TCC0_WO0      ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0    (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0              _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0              _L_(5)
+#define PINMUX_PA08F_TCC0_WO0      ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0    (_UL_(1) <<  8)
+#define PIN_PA21G_TCC0_WO1             _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1              _L_(6)
+#define PINMUX_PA21G_TCC0_WO1      ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1    (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1             _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1              _L_(6)
+#define PINMUX_PB13G_TCC0_WO1      ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1    (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1              _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1              _L_(5)
+#define PINMUX_PA09F_TCC0_WO1      ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1    (_UL_(1) <<  9)
+#define PIN_PA22G_TCC0_WO2             _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2              _L_(6)
+#define PINMUX_PA22G_TCC0_WO2      ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2    (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2             _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2              _L_(6)
+#define PINMUX_PB14G_TCC0_WO2      ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2    (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2             _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L_(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL_(1) << 10)
+#define PIN_PA23G_TCC0_WO3             _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3              _L_(6)
+#define PINMUX_PA23G_TCC0_WO3      ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3    (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3             _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3              _L_(6)
+#define PINMUX_PB15G_TCC0_WO3      ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3    (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3             _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L_(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL_(1) << 11)
+#define PIN_PA16G_TCC0_WO4             _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4              _L_(6)
+#define PINMUX_PA16G_TCC0_WO4      ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4             _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4              _L_(6)
+#define PINMUX_PB16G_TCC0_WO4      ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4             _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L_(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL_(1) << 10)
+#define PIN_PA17G_TCC0_WO5             _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5              _L_(6)
+#define PINMUX_PA17G_TCC0_WO5      ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5             _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5              _L_(6)
+#define PINMUX_PB17G_TCC0_WO5      ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5             _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L_(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL_(1) << 11)
+#define PIN_PA18G_TCC0_WO6             _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6              _L_(6)
+#define PINMUX_PA18G_TCC0_WO6      ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6    (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6             _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6              _L_(6)
+#define PINMUX_PB30G_TCC0_WO6      ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6    (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6             _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L_(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7             _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7              _L_(6)
+#define PINMUX_PA19G_TCC0_WO7      ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7    (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7             _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7              _L_(6)
+#define PINMUX_PB31G_TCC0_WO7      ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7    (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7             _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L_(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0             _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0              _L_(6)
+#define PINMUX_PB10G_TCC1_WO0      ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0    (_UL_(1) << 10)
+#define PIN_PA16F_TCC1_WO0             _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0              _L_(5)
+#define PINMUX_PA16F_TCC1_WO0      ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0    (_UL_(1) << 16)
+#define PIN_PB11G_TCC1_WO1             _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1              _L_(6)
+#define PINMUX_PB11G_TCC1_WO1      ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1    (_UL_(1) << 11)
+#define PIN_PA17F_TCC1_WO1             _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1              _L_(5)
+#define PINMUX_PA17F_TCC1_WO1      ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1    (_UL_(1) << 17)
+#define PIN_PA12G_TCC1_WO2             _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2              _L_(6)
+#define PINMUX_PA12G_TCC1_WO2      ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2    (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2             _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2              _L_(6)
+#define PINMUX_PA14G_TCC1_WO2      ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2    (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2             _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2              _L_(5)
+#define PINMUX_PA18F_TCC1_WO2      ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2    (_UL_(1) << 18)
+#define PIN_PA13G_TCC1_WO3             _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3              _L_(6)
+#define PINMUX_PA13G_TCC1_WO3      ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3    (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3             _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3              _L_(6)
+#define PINMUX_PA15G_TCC1_WO3      ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3    (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3             _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3              _L_(5)
+#define PINMUX_PA19F_TCC1_WO3      ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3    (_UL_(1) << 19)
+#define PIN_PA08G_TCC1_WO4              _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4              _L_(6)
+#define PINMUX_PA08G_TCC1_WO4      ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4    (_UL_(1) <<  8)
+#define PIN_PA20F_TCC1_WO4             _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4              _L_(5)
+#define PINMUX_PA20F_TCC1_WO4      ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4    (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5              _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5              _L_(6)
+#define PINMUX_PA09G_TCC1_WO5      ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5    (_UL_(1) <<  9)
+#define PIN_PA21F_TCC1_WO5             _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5              _L_(5)
+#define PINMUX_PA21F_TCC1_WO5      ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5    (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6             _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6              _L_(6)
+#define PINMUX_PA10G_TCC1_WO6      ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6    (_UL_(1) << 10)
+#define PIN_PA22F_TCC1_WO6             _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6              _L_(5)
+#define PINMUX_PA22F_TCC1_WO6      ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6    (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7             _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7              _L_(6)
+#define PINMUX_PA11G_TCC1_WO7      ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7    (_UL_(1) << 11)
+#define PIN_PA23F_TCC1_WO7             _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7              _L_(5)
+#define PINMUX_PA23F_TCC1_WO7      ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7    (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0              _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0               _L_(4)
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0     (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0               _L_(4)
+#define PINMUX_PA16E_TC2_WO0       ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0     (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0               _L_(4)
+#define PINMUX_PA00E_TC2_WO0       ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0     (_UL_(1) <<  0)
+#define PIN_PA01E_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1               _L_(4)
+#define PINMUX_PA01E_TC2_WO1       ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1     (_UL_(1) <<  1)
+#define PIN_PA13E_TC2_WO1              _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1               _L_(4)
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1     (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1               _L_(4)
+#define PINMUX_PA17E_TC2_WO1       ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L_(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L_(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L_(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L_(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL_(1) << 19)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PA16L_GMAC_GCRS            _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS            _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS     ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS   (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC            _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC            _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC     ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC   (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC            _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC            _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC     ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC   (_UL_(1) << 14)
+#define PIN_PA21L_GMAC_GMDIO           _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO    ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO  (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO           _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO    ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO  (_UL_(1) << 15)
+#define PIN_PA13L_GMAC_GRX0            _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0            _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0     ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0   (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1            _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1            _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1     ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1   (_UL_(1) << 12)
+#define PIN_PA16L_GMAC_GRXDV           _L_(16) /**< \brief GMAC signal: GRXDV on PA16 mux L */
+#define MUX_PA16L_GMAC_GRXDV           _L_(11)
+#define PINMUX_PA16L_GMAC_GRXDV    ((PIN_PA16L_GMAC_GRXDV << 16) | MUX_PA16L_GMAC_GRXDV)
+#define PORT_PA16L_GMAC_GRXDV  (_UL_(1) << 16)
+#define PIN_PA15L_GMAC_GRXER           _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER           _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER    ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER  (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0            _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0            _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0     ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0   (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1            _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1            _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1     ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1   (_UL_(1) << 19)
+#define PIN_PA14L_GMAC_GTXCK           _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK           _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK    ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK  (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN           _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN           _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN    ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN  (_UL_(1) << 17)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0             _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0              _L_(5)
+#define PINMUX_PA14F_TCC2_WO0      ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0    (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0             _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0              _L_(5)
+#define PINMUX_PA30F_TCC2_WO0      ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0    (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1             _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1              _L_(5)
+#define PINMUX_PA15F_TCC2_WO1      ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1    (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1             _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1              _L_(5)
+#define PINMUX_PA31F_TCC2_WO1      ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1    (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2             _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2              _L_(5)
+#define PINMUX_PA24F_TCC2_WO2      ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2    (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2             _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2              _L_(5)
+#define PINMUX_PB02F_TCC2_WO2      ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2    (_UL_(1) <<  2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0             _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0              _L_(5)
+#define PINMUX_PB12F_TCC3_WO0      ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0    (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0             _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0              _L_(5)
+#define PINMUX_PB16F_TCC3_WO0      ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0    (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1             _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1              _L_(5)
+#define PINMUX_PB13F_TCC3_WO1      ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1    (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1             _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1              _L_(5)
+#define PINMUX_PB17F_TCC3_WO1      ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1    (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L_(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L_(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL_(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L_(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L_(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L_(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL_(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L_(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L_(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L_(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L_(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L_(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L_(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L_(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB23G_PDEC_QDI0            _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0     ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0   (_UL_(1) << 23)
+#define PIN_PA24G_PDEC_QDI0            _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0             _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0     ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0   (_UL_(1) << 24)
+#define PIN_PA25G_PDEC_QDI1            _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1             _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1     ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1   (_UL_(1) << 25)
+#define PIN_PB22G_PDEC_QDI2            _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2     ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2   (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L_(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L_(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L_(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L_(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
+#define PIN_PA12M_AC_CMP0              _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0              _L_(12)
+#define PINMUX_PA12M_AC_CMP0       ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0     (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0              _L_(12)
+#define PINMUX_PA18M_AC_CMP0       ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0     (_UL_(1) << 18)
+#define PIN_PA13M_AC_CMP1              _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1              _L_(12)
+#define PINMUX_PA13M_AC_CMP1       ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1     (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1              _L_(12)
+#define PINMUX_PA19M_AC_CMP1       ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1     (_UL_(1) << 19)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS              _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS               _L_(7)
+#define PINMUX_PB11H_QSPI_CS       ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS     (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0            _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0            _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0    ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0  (_UL_(1) <<  8)
+#define PIN_PA09H_QSPI_DATA1            _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1            _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1    ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1  (_UL_(1) <<  9)
+#define PIN_PA10H_QSPI_DATA2           _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2            _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2    ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2  (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3           _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3            _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3    ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3  (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK             _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK              _L_(7)
+#define PINMUX_PB10H_QSPI_SCK      ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK    (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0               _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0              _L_(13)
+#define PINMUX_PA04N_CCL_IN0       ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0     (_UL_(1) <<  4)
+#define PIN_PA16N_CCL_IN0              _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0              _L_(13)
+#define PINMUX_PA16N_CCL_IN0       ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0     (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0              _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0              _L_(13)
+#define PINMUX_PB22N_CCL_IN0       ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0     (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1               _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1              _L_(13)
+#define PINMUX_PA05N_CCL_IN1       ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1     (_UL_(1) <<  5)
+#define PIN_PA17N_CCL_IN1              _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1              _L_(13)
+#define PINMUX_PA17N_CCL_IN1       ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1     (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1              _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1              _L_(13)
+#define PINMUX_PB00N_CCL_IN1       ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1     (_UL_(1) <<  0)
+#define PIN_PA06N_CCL_IN2               _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2              _L_(13)
+#define PINMUX_PA06N_CCL_IN2       ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2     (_UL_(1) <<  6)
+#define PIN_PA18N_CCL_IN2              _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2              _L_(13)
+#define PINMUX_PA18N_CCL_IN2       ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2     (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2              _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2              _L_(13)
+#define PINMUX_PB01N_CCL_IN2       ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2     (_UL_(1) <<  1)
+#define PIN_PA08N_CCL_IN3               _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3              _L_(13)
+#define PINMUX_PA08N_CCL_IN3       ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3     (_UL_(1) <<  8)
+#define PIN_PA30N_CCL_IN3              _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3              _L_(13)
+#define PINMUX_PA30N_CCL_IN3       ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3     (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4               _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4              _L_(13)
+#define PINMUX_PA09N_CCL_IN4       ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4     (_UL_(1) <<  9)
+#define PIN_PA10N_CCL_IN5              _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5              _L_(13)
+#define PINMUX_PA10N_CCL_IN5       ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5     (_UL_(1) << 10)
+#define PIN_PA22N_CCL_IN6              _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6              _L_(13)
+#define PINMUX_PA22N_CCL_IN6       ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6     (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6              _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6              _L_(13)
+#define PINMUX_PB06N_CCL_IN6       ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6     (_UL_(1) <<  6)
+#define PIN_PA23N_CCL_IN7              _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7              _L_(13)
+#define PINMUX_PA23N_CCL_IN7       ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7     (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7              _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7              _L_(13)
+#define PINMUX_PB07N_CCL_IN7       ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7     (_UL_(1) <<  7)
+#define PIN_PA24N_CCL_IN8              _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8              _L_(13)
+#define PINMUX_PA24N_CCL_IN8       ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8     (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8              _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8              _L_(13)
+#define PINMUX_PB08N_CCL_IN8       ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8     (_UL_(1) <<  8)
+#define PIN_PB14N_CCL_IN9              _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9              _L_(13)
+#define PINMUX_PB14N_CCL_IN9       ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9     (_UL_(1) << 14)
+#define PIN_PB15N_CCL_IN10             _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10             _L_(13)
+#define PINMUX_PB15N_CCL_IN10      ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10    (_UL_(1) << 15)
+#define PIN_PB10N_CCL_IN11             _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11             _L_(13)
+#define PINMUX_PB10N_CCL_IN11      ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11    (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11             _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11             _L_(13)
+#define PINMUX_PB16N_CCL_IN11      ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11    (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0              _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0             _L_(13)
+#define PINMUX_PA07N_CCL_OUT0      ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0    (_UL_(1) <<  7)
+#define PIN_PA19N_CCL_OUT0             _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0             _L_(13)
+#define PINMUX_PA19N_CCL_OUT0      ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0    (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0             _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0             _L_(13)
+#define PINMUX_PB02N_CCL_OUT0      ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0    (_UL_(1) <<  2)
+#define PIN_PB23N_CCL_OUT0             _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0             _L_(13)
+#define PINMUX_PB23N_CCL_OUT0      ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0    (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1             _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1             _L_(13)
+#define PINMUX_PA11N_CCL_OUT1      ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1             _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1             _L_(13)
+#define PINMUX_PA31N_CCL_OUT1      ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1    (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1             _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1             _L_(13)
+#define PINMUX_PB11N_CCL_OUT1      ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2             _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2             _L_(13)
+#define PINMUX_PA25N_CCL_OUT2      ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2    (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2             _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2             _L_(13)
+#define PINMUX_PB09N_CCL_OUT2      ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2    (_UL_(1) <<  9)
+#define PIN_PB17N_CCL_OUT3             _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3             _L_(13)
+#define PINMUX_PB17N_CCL_OUT3      ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3    (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0         _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0  ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0  (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0         _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL_(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1         _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1  ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1  (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1         _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL_(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3         _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3         _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3         _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0         _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0  ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0  (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0         _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL_(1) <<  2)
+#define PIN_PB31D_SERCOM5_PAD0         _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0  ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0  (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0         _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1         _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1  ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1  (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1         _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL_(1) <<  3)
+#define PIN_PB30D_SERCOM5_PAD1         _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1  ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1  (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2         _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL_(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL_(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL_(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL_(1) << 21)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0             _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0              _L_(5)
+#define PINMUX_PB14F_TCC4_WO0      ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0    (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0             _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0              _L_(5)
+#define PINMUX_PB30F_TCC4_WO0      ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0    (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1             _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1              _L_(5)
+#define PINMUX_PB15F_TCC4_WO1      ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1    (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1             _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1              _L_(5)
+#define PINMUX_PB31F_TCC4_WO1      ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1    (_UL_(1) << 31)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0             _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0             _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0     ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0   (_UL_(1) <<  2)
+#define PIN_PA03B_ADC0_AIN1             _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1             _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1     ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1   (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_AIN2            _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2             _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2     ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_AIN3            _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3             _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3     ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3   (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_AIN4             _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4             _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4     ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4   (_UL_(1) <<  4)
+#define PIN_PA05B_ADC0_AIN5             _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5             _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5     ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5   (_UL_(1) <<  5)
+#define PIN_PA06B_ADC0_AIN6             _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6             _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6     ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6   (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_AIN7             _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7             _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7     ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7   (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_AIN8             _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8             _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8     ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_AIN9             _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9             _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9     ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9   (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_AIN10           _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10            _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10    ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11           _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11            _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11    ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11  (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12           _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12            _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12    ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_AIN13           _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13            _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13    ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13  (_UL_(1) <<  1)
+#define PIN_PB02B_ADC0_AIN14           _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14            _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14    ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_AIN15           _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15            _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15    ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15  (_UL_(1) <<  3)
+#define PIN_PA03O_ADC0_DRV0             _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0            _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0     ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0   (_UL_(1) <<  3)
+#define PIN_PB08O_ADC0_DRV1            _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1            _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1     ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1   (_UL_(1) <<  8)
+#define PIN_PB09O_ADC0_DRV2            _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2            _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2     ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2   (_UL_(1) <<  9)
+#define PIN_PA04O_ADC0_DRV3             _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3            _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3     ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3   (_UL_(1) <<  4)
+#define PIN_PA06O_ADC0_DRV4             _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4            _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4     ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4   (_UL_(1) <<  6)
+#define PIN_PA07O_ADC0_DRV5             _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5            _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5     ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5   (_UL_(1) <<  7)
+#define PIN_PA08O_ADC0_DRV6             _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6            _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6     ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6   (_UL_(1) <<  8)
+#define PIN_PA09O_ADC0_DRV7             _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7            _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7     ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7   (_UL_(1) <<  9)
+#define PIN_PA10O_ADC0_DRV8            _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8            _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8     ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8   (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9            _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9            _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9     ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9   (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10           _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10           _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10    ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10  (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11           _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11           _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11    ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11  (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12           _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12           _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12    ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12  (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13           _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13           _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13    ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13  (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14           _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14           _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14    ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14  (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15           _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15           _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15    ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15  (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16           _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16           _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16    ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16  (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17           _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17           _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17    ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17  (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18           _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18           _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18    ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18  (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19           _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19           _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19    ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19  (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20           _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20           _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20    ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20  (_UL_(1) <<  2)
+#define PIN_PB03O_ADC0_DRV21           _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21           _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21    ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21  (_UL_(1) <<  3)
+#define PIN_PB04O_ADC0_DRV22           _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22           _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22    ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22  (_UL_(1) <<  4)
+#define PIN_PB05O_ADC0_DRV23           _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23           _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23    ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23  (_UL_(1) <<  5)
+#define PIN_PB06O_ADC0_DRV24           _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24           _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24    ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24  (_UL_(1) <<  6)
+#define PIN_PB07O_ADC0_DRV25           _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25           _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25    ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25  (_UL_(1) <<  7)
+#define PIN_PB12O_ADC0_DRV26           _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26           _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26    ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26  (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27           _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27           _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27    ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27  (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28           _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28           _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28    ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28  (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29           _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29           _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29    ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29  (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30           _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30           _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30    ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30  (_UL_(1) <<  0)
+#define PIN_PB01O_ADC0_DRV31           _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31           _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31    ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31  (_UL_(1) <<  1)
+#define PIN_PA03B_ADC0_PTCXY0           _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0           _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0   ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0  (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_PTCXY1          _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1           _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1   ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1  (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_PTCXY2          _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2           _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2   ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2  (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_PTCXY3           _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3           _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3   ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3  (_UL_(1) <<  4)
+#define PIN_PA06B_ADC0_PTCXY4           _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4           _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4   ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4  (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_PTCXY5           _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5           _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5   ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5  (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_PTCXY6           _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6           _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6   ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6  (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_PTCXY7           _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7           _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7   ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7  (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_PTCXY8          _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8           _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8   ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9          _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9           _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9   ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9  (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10         _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10          _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10  ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10  (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11         _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11          _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11  ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11  (_UL_(1) << 17)
+#define PIN_PA18B_ADC0_PTCXY12         _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */
+#define MUX_PA18B_ADC0_PTCXY12          _L_(1)
+#define PINMUX_PA18B_ADC0_PTCXY12  ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
+#define PORT_PA18B_ADC0_PTCXY12  (_UL_(1) << 18)
+#define PIN_PA19B_ADC0_PTCXY13         _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13          _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13  ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13  (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14         _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14          _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14  ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14  (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15         _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15          _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15  ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15  (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16         _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16          _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16  ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16  (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17         _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17          _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17  ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17  (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18         _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18          _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18  ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18  (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19         _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19          _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19  ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19  (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20         _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20          _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20  ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_PTCXY21         _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21          _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21  ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21  (_UL_(1) <<  3)
+#define PIN_PB04B_ADC0_PTCXY22         _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22          _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22  ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22  (_UL_(1) <<  4)
+#define PIN_PB05B_ADC0_PTCXY23         _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23          _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23  ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23  (_UL_(1) <<  5)
+#define PIN_PB06B_ADC0_PTCXY24         _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24          _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24  ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24  (_UL_(1) <<  6)
+#define PIN_PB07B_ADC0_PTCXY25         _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25          _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25  ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25  (_UL_(1) <<  7)
+#define PIN_PB12B_ADC0_PTCXY26         _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26          _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26  ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26  (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27         _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27          _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27  ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27  (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28         _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28          _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28  ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28  (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29         _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29          _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29  ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29  (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30         _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30          _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30  ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_PTCXY31         _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31          _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31  ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31  (_UL_(1) <<  1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0            _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0             _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0     ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC1_AIN1            _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1             _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1     ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1   (_UL_(1) <<  9)
+#define PIN_PA08B_ADC1_AIN2             _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2             _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2     ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC1_AIN3             _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3             _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3     ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3   (_UL_(1) <<  9)
+#define PIN_PB04B_ADC1_AIN6            _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6             _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6     ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6   (_UL_(1) <<  4)
+#define PIN_PB05B_ADC1_AIN7            _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7             _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7     ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7   (_UL_(1) <<  5)
+#define PIN_PB06B_ADC1_AIN8            _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8             _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8     ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8   (_UL_(1) <<  6)
+#define PIN_PB07B_ADC1_AIN9            _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9             _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9     ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9   (_UL_(1) <<  7)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0             _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0             _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0   (_UL_(1) <<  2)
+#define PIN_PA05B_DAC_VOUT1             _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1             _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1   (_UL_(1) <<  5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0               _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0               _L_(9)
+#define PINMUX_PA09J_I2S_FS0       ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0     (_UL_(1) <<  9)
+#define PIN_PA20J_I2S_FS0              _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0               _L_(9)
+#define PINMUX_PA20J_I2S_FS0       ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0     (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1              _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1               _L_(9)
+#define PINMUX_PA23J_I2S_FS1       ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1     (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1              _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1               _L_(9)
+#define PINMUX_PB11J_I2S_FS1       ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1     (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0              _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0              _L_(9)
+#define PINMUX_PA08J_I2S_MCK0      ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0    (_UL_(1) <<  8)
+#define PIN_PB17J_I2S_MCK0             _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0              _L_(9)
+#define PINMUX_PB17J_I2S_MCK0      ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0    (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1             _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1              _L_(9)
+#define PINMUX_PB13J_I2S_MCK1      ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1    (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0             _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0              _L_(9)
+#define PINMUX_PA10J_I2S_SCK0      ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0    (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0             _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0              _L_(9)
+#define PINMUX_PB16J_I2S_SCK0      ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0    (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1             _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1              _L_(9)
+#define PINMUX_PB12J_I2S_SCK1      ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1    (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI              _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI               _L_(9)
+#define PINMUX_PA22J_I2S_SDI       ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI     (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI              _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI               _L_(9)
+#define PINMUX_PB10J_I2S_SDI       ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI     (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO              _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO               _L_(9)
+#define PINMUX_PA11J_I2S_SDO       ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO     (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO              _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO               _L_(9)
+#define PINMUX_PA21J_I2S_SDO       ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO     (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK              _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK              _L_(10)
+#define PINMUX_PA14K_PCC_CLK       ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK     (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0            _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0            _L_(10)
+#define PINMUX_PA16K_PCC_DATA0     ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0   (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1            _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1            _L_(10)
+#define PINMUX_PA17K_PCC_DATA1     ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1   (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2            _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2            _L_(10)
+#define PINMUX_PA18K_PCC_DATA2     ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2   (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3            _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3            _L_(10)
+#define PINMUX_PA19K_PCC_DATA3     ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3   (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4            _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4            _L_(10)
+#define PINMUX_PA20K_PCC_DATA4     ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4   (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5            _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5            _L_(10)
+#define PINMUX_PA21K_PCC_DATA5     ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5   (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6            _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6            _L_(10)
+#define PINMUX_PA22K_PCC_DATA6     ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6   (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7            _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7            _L_(10)
+#define PINMUX_PA23K_PCC_DATA7     ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7   (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8            _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8            _L_(10)
+#define PINMUX_PB14K_PCC_DATA8     ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8   (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9            _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9            _L_(10)
+#define PINMUX_PB15K_PCC_DATA9     ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9   (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1             _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1             _L_(10)
+#define PINMUX_PA12K_PCC_DEN1      ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1    (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2             _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2             _L_(10)
+#define PINMUX_PA13K_PCC_DEN2      ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2    (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD            _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD    ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PA12I_SDHC0_SDCD           _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD    ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD           _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD    ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB11I_SDHC0_SDCK           _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK            _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK    ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK  (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD           _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD           _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD   ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD  (_UL_(1) <<  8)
+#define PIN_PA09I_SDHC0_SDDAT0          _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0          _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0  ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0  (_UL_(1) <<  9)
+#define PIN_PA10I_SDHC0_SDDAT1         _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1          _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1  ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1  (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2         _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2          _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2  ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2  (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3         _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3          _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3  ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3  (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP            _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP    ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP  (_UL_(1) <<  7)
+#define PIN_PA13I_SDHC0_SDWP           _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP    ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP           _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP    ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP  (_UL_(1) << 13)
+
+#endif /* _SAME53J18A_PIO_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j19a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j19a.h
new file mode 100644
index 000000000..2aa17ac77
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j19a.h	
@@ -0,0 +1,1911 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME53J19A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53J19A_PIO_
+#define _SAME53J19A_PIO_
+
+#define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                           12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL_(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                           13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL_(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                           20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL_(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                           21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL_(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                           32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                           33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                           34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                           35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                           36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                           37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                           38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                           39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                           40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                           41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                           42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL_(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                           43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL_(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                           44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL_(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                           45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL_(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                           46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL_(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                           47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL_(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                           48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL_(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                           49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL_(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                           54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL_(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                           55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL_(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                           62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL_(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                           63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL_(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK            _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK             _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK     ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK   (_UL_(1) << 30)
+#define PIN_PB30H_CM4_SWO              _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO               _L_(7)
+#define PINMUX_PB30H_CM4_SWO       ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO     (_UL_(1) << 30)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0          _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0          _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0  ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0  (_UL_(1) <<  3)
+#define PIN_PA04B_ANAREF_VREF1          _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1          _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1  ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1  (_UL_(1) <<  4)
+#define PIN_PA06B_ANAREF_VREF2          _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2          _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2  ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2  (_UL_(1) <<  6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0             _L_(12)
+#define PINMUX_PA30M_GCLK_IO0      ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0    (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0             _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0             _L_(12)
+#define PINMUX_PB14M_GCLK_IO0      ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0             _L_(12)
+#define PINMUX_PA14M_GCLK_IO0      ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0             _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0             _L_(12)
+#define PINMUX_PB22M_GCLK_IO0      ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0    (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1             _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1             _L_(12)
+#define PINMUX_PB15M_GCLK_IO1      ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1             _L_(12)
+#define PINMUX_PA15M_GCLK_IO1      ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1             _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1             _L_(12)
+#define PINMUX_PB23M_GCLK_IO1      ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1    (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1             _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1             _L_(12)
+#define PINMUX_PA27M_GCLK_IO1      ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1    (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2             _L_(12)
+#define PINMUX_PA16M_GCLK_IO2      ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2             _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2             _L_(12)
+#define PINMUX_PB16M_GCLK_IO2      ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3             _L_(12)
+#define PINMUX_PA17M_GCLK_IO3      ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3             _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3             _L_(12)
+#define PINMUX_PB17M_GCLK_IO3      ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4             _L_(12)
+#define PINMUX_PA10M_GCLK_IO4      ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4             _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4             _L_(12)
+#define PINMUX_PB10M_GCLK_IO4      ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PA11M_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5             _L_(12)
+#define PINMUX_PA11M_GCLK_IO5      ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5             _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5             _L_(12)
+#define PINMUX_PB11M_GCLK_IO5      ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB12M_GCLK_IO6             _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6             _L_(12)
+#define PINMUX_PB12M_GCLK_IO6      ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6    (_UL_(1) << 12)
+#define PIN_PB13M_GCLK_IO7             _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7             _L_(12)
+#define PINMUX_PB13M_GCLK_IO7      ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7    (_UL_(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8          _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8   ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL_(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9          _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9   ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11         _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11  ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14         _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14  ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15         _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15  ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L_(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
+#define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
+#define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
+#define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
+#define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2         _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2  ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2  (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3         _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3  ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3  (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0               _L_(4)
+#define PINMUX_PA04E_TC0_WO0       ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0     (_UL_(1) <<  4)
+#define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0               _L_(4)
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
+#define PIN_PB30E_TC0_WO0              _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0               _L_(4)
+#define PINMUX_PB30E_TC0_WO0       ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0     (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1               _L_(4)
+#define PINMUX_PA05E_TC0_WO1       ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1     (_UL_(1) <<  5)
+#define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1               _L_(4)
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
+#define PIN_PB31E_TC0_WO1              _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1               _L_(4)
+#define PINMUX_PB31E_TC0_WO1       ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1     (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0               _L_(4)
+#define PINMUX_PA06E_TC1_WO0       ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0     (_UL_(1) <<  6)
+#define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0               _L_(4)
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1               _L_(4)
+#define PINMUX_PA07E_TC1_WO1       ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1     (_UL_(1) <<  7)
+#define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1               _L_(4)
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM               _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM                _L_(7)
+#define PINMUX_PA24H_USB_DM        ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM      (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP               _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP                _L_(7)
+#define PINMUX_PA25H_USB_DP        ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP      (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ         _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ  ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ  (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ         _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ  ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ  (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0          _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0  ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0  (_UL_(1) <<  9)
+#define PIN_PA12C_SERCOM2_PAD0         _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1          _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1  ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1  (_UL_(1) <<  8)
+#define PIN_PA13C_SERCOM2_PAD1         _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0         _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0          _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0  ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0  (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
+#define PIN_PA16D_SERCOM3_PAD1         _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1          _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1  ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1  (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0             _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0              _L_(6)
+#define PINMUX_PA20G_TCC0_WO0      ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0    (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0             _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0              _L_(6)
+#define PINMUX_PB12G_TCC0_WO0      ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0    (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0              _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0              _L_(5)
+#define PINMUX_PA08F_TCC0_WO0      ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0    (_UL_(1) <<  8)
+#define PIN_PA21G_TCC0_WO1             _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1              _L_(6)
+#define PINMUX_PA21G_TCC0_WO1      ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1    (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1             _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1              _L_(6)
+#define PINMUX_PB13G_TCC0_WO1      ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1    (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1              _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1              _L_(5)
+#define PINMUX_PA09F_TCC0_WO1      ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1    (_UL_(1) <<  9)
+#define PIN_PA22G_TCC0_WO2             _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2              _L_(6)
+#define PINMUX_PA22G_TCC0_WO2      ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2    (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2             _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2              _L_(6)
+#define PINMUX_PB14G_TCC0_WO2      ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2    (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2             _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L_(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL_(1) << 10)
+#define PIN_PA23G_TCC0_WO3             _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3              _L_(6)
+#define PINMUX_PA23G_TCC0_WO3      ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3    (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3             _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3              _L_(6)
+#define PINMUX_PB15G_TCC0_WO3      ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3    (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3             _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L_(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL_(1) << 11)
+#define PIN_PA16G_TCC0_WO4             _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4              _L_(6)
+#define PINMUX_PA16G_TCC0_WO4      ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4             _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4              _L_(6)
+#define PINMUX_PB16G_TCC0_WO4      ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4             _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L_(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL_(1) << 10)
+#define PIN_PA17G_TCC0_WO5             _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5              _L_(6)
+#define PINMUX_PA17G_TCC0_WO5      ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5             _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5              _L_(6)
+#define PINMUX_PB17G_TCC0_WO5      ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5             _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L_(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL_(1) << 11)
+#define PIN_PA18G_TCC0_WO6             _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6              _L_(6)
+#define PINMUX_PA18G_TCC0_WO6      ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6    (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6             _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6              _L_(6)
+#define PINMUX_PB30G_TCC0_WO6      ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6    (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6             _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L_(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7             _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7              _L_(6)
+#define PINMUX_PA19G_TCC0_WO7      ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7    (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7             _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7              _L_(6)
+#define PINMUX_PB31G_TCC0_WO7      ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7    (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7             _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L_(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0             _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0              _L_(6)
+#define PINMUX_PB10G_TCC1_WO0      ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0    (_UL_(1) << 10)
+#define PIN_PA16F_TCC1_WO0             _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0              _L_(5)
+#define PINMUX_PA16F_TCC1_WO0      ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0    (_UL_(1) << 16)
+#define PIN_PB11G_TCC1_WO1             _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1              _L_(6)
+#define PINMUX_PB11G_TCC1_WO1      ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1    (_UL_(1) << 11)
+#define PIN_PA17F_TCC1_WO1             _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1              _L_(5)
+#define PINMUX_PA17F_TCC1_WO1      ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1    (_UL_(1) << 17)
+#define PIN_PA12G_TCC1_WO2             _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2              _L_(6)
+#define PINMUX_PA12G_TCC1_WO2      ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2    (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2             _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2              _L_(6)
+#define PINMUX_PA14G_TCC1_WO2      ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2    (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2             _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2              _L_(5)
+#define PINMUX_PA18F_TCC1_WO2      ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2    (_UL_(1) << 18)
+#define PIN_PA13G_TCC1_WO3             _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3              _L_(6)
+#define PINMUX_PA13G_TCC1_WO3      ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3    (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3             _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3              _L_(6)
+#define PINMUX_PA15G_TCC1_WO3      ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3    (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3             _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3              _L_(5)
+#define PINMUX_PA19F_TCC1_WO3      ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3    (_UL_(1) << 19)
+#define PIN_PA08G_TCC1_WO4              _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4              _L_(6)
+#define PINMUX_PA08G_TCC1_WO4      ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4    (_UL_(1) <<  8)
+#define PIN_PA20F_TCC1_WO4             _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4              _L_(5)
+#define PINMUX_PA20F_TCC1_WO4      ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4    (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5              _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5              _L_(6)
+#define PINMUX_PA09G_TCC1_WO5      ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5    (_UL_(1) <<  9)
+#define PIN_PA21F_TCC1_WO5             _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5              _L_(5)
+#define PINMUX_PA21F_TCC1_WO5      ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5    (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6             _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6              _L_(6)
+#define PINMUX_PA10G_TCC1_WO6      ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6    (_UL_(1) << 10)
+#define PIN_PA22F_TCC1_WO6             _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6              _L_(5)
+#define PINMUX_PA22F_TCC1_WO6      ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6    (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7             _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7              _L_(6)
+#define PINMUX_PA11G_TCC1_WO7      ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7    (_UL_(1) << 11)
+#define PIN_PA23F_TCC1_WO7             _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7              _L_(5)
+#define PINMUX_PA23F_TCC1_WO7      ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7    (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0              _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0               _L_(4)
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0     (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0               _L_(4)
+#define PINMUX_PA16E_TC2_WO0       ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0     (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0               _L_(4)
+#define PINMUX_PA00E_TC2_WO0       ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0     (_UL_(1) <<  0)
+#define PIN_PA01E_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1               _L_(4)
+#define PINMUX_PA01E_TC2_WO1       ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1     (_UL_(1) <<  1)
+#define PIN_PA13E_TC2_WO1              _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1               _L_(4)
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1     (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1               _L_(4)
+#define PINMUX_PA17E_TC2_WO1       ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L_(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L_(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L_(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L_(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL_(1) << 19)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PA16L_GMAC_GCRS            _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS            _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS     ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS   (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC            _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC            _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC     ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC   (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC            _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC            _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC     ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC   (_UL_(1) << 14)
+#define PIN_PA21L_GMAC_GMDIO           _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO    ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO  (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO           _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO    ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO  (_UL_(1) << 15)
+#define PIN_PA13L_GMAC_GRX0            _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0            _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0     ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0   (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1            _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1            _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1     ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1   (_UL_(1) << 12)
+#define PIN_PA16L_GMAC_GRXDV           _L_(16) /**< \brief GMAC signal: GRXDV on PA16 mux L */
+#define MUX_PA16L_GMAC_GRXDV           _L_(11)
+#define PINMUX_PA16L_GMAC_GRXDV    ((PIN_PA16L_GMAC_GRXDV << 16) | MUX_PA16L_GMAC_GRXDV)
+#define PORT_PA16L_GMAC_GRXDV  (_UL_(1) << 16)
+#define PIN_PA15L_GMAC_GRXER           _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER           _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER    ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER  (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0            _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0            _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0     ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0   (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1            _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1            _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1     ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1   (_UL_(1) << 19)
+#define PIN_PA14L_GMAC_GTXCK           _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK           _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK    ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK  (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN           _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN           _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN    ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN  (_UL_(1) << 17)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0             _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0              _L_(5)
+#define PINMUX_PA14F_TCC2_WO0      ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0    (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0             _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0              _L_(5)
+#define PINMUX_PA30F_TCC2_WO0      ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0    (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1             _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1              _L_(5)
+#define PINMUX_PA15F_TCC2_WO1      ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1    (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1             _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1              _L_(5)
+#define PINMUX_PA31F_TCC2_WO1      ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1    (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2             _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2              _L_(5)
+#define PINMUX_PA24F_TCC2_WO2      ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2    (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2             _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2              _L_(5)
+#define PINMUX_PB02F_TCC2_WO2      ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2    (_UL_(1) <<  2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0             _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0              _L_(5)
+#define PINMUX_PB12F_TCC3_WO0      ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0    (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0             _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0              _L_(5)
+#define PINMUX_PB16F_TCC3_WO0      ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0    (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1             _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1              _L_(5)
+#define PINMUX_PB13F_TCC3_WO1      ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1    (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1             _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1              _L_(5)
+#define PINMUX_PB17F_TCC3_WO1      ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1    (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L_(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L_(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL_(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L_(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L_(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L_(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL_(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L_(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L_(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L_(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L_(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L_(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L_(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L_(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB23G_PDEC_QDI0            _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0     ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0   (_UL_(1) << 23)
+#define PIN_PA24G_PDEC_QDI0            _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0             _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0     ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0   (_UL_(1) << 24)
+#define PIN_PA25G_PDEC_QDI1            _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1             _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1     ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1   (_UL_(1) << 25)
+#define PIN_PB22G_PDEC_QDI2            _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2     ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2   (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L_(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L_(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L_(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L_(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
+#define PIN_PA12M_AC_CMP0              _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0              _L_(12)
+#define PINMUX_PA12M_AC_CMP0       ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0     (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0              _L_(12)
+#define PINMUX_PA18M_AC_CMP0       ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0     (_UL_(1) << 18)
+#define PIN_PA13M_AC_CMP1              _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1              _L_(12)
+#define PINMUX_PA13M_AC_CMP1       ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1     (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1              _L_(12)
+#define PINMUX_PA19M_AC_CMP1       ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1     (_UL_(1) << 19)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS              _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS               _L_(7)
+#define PINMUX_PB11H_QSPI_CS       ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS     (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0            _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0            _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0    ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0  (_UL_(1) <<  8)
+#define PIN_PA09H_QSPI_DATA1            _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1            _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1    ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1  (_UL_(1) <<  9)
+#define PIN_PA10H_QSPI_DATA2           _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2            _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2    ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2  (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3           _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3            _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3    ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3  (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK             _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK              _L_(7)
+#define PINMUX_PB10H_QSPI_SCK      ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK    (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0               _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0              _L_(13)
+#define PINMUX_PA04N_CCL_IN0       ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0     (_UL_(1) <<  4)
+#define PIN_PA16N_CCL_IN0              _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0              _L_(13)
+#define PINMUX_PA16N_CCL_IN0       ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0     (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0              _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0              _L_(13)
+#define PINMUX_PB22N_CCL_IN0       ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0     (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1               _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1              _L_(13)
+#define PINMUX_PA05N_CCL_IN1       ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1     (_UL_(1) <<  5)
+#define PIN_PA17N_CCL_IN1              _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1              _L_(13)
+#define PINMUX_PA17N_CCL_IN1       ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1     (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1              _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1              _L_(13)
+#define PINMUX_PB00N_CCL_IN1       ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1     (_UL_(1) <<  0)
+#define PIN_PA06N_CCL_IN2               _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2              _L_(13)
+#define PINMUX_PA06N_CCL_IN2       ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2     (_UL_(1) <<  6)
+#define PIN_PA18N_CCL_IN2              _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2              _L_(13)
+#define PINMUX_PA18N_CCL_IN2       ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2     (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2              _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2              _L_(13)
+#define PINMUX_PB01N_CCL_IN2       ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2     (_UL_(1) <<  1)
+#define PIN_PA08N_CCL_IN3               _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3              _L_(13)
+#define PINMUX_PA08N_CCL_IN3       ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3     (_UL_(1) <<  8)
+#define PIN_PA30N_CCL_IN3              _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3              _L_(13)
+#define PINMUX_PA30N_CCL_IN3       ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3     (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4               _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4              _L_(13)
+#define PINMUX_PA09N_CCL_IN4       ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4     (_UL_(1) <<  9)
+#define PIN_PA10N_CCL_IN5              _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5              _L_(13)
+#define PINMUX_PA10N_CCL_IN5       ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5     (_UL_(1) << 10)
+#define PIN_PA22N_CCL_IN6              _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6              _L_(13)
+#define PINMUX_PA22N_CCL_IN6       ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6     (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6              _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6              _L_(13)
+#define PINMUX_PB06N_CCL_IN6       ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6     (_UL_(1) <<  6)
+#define PIN_PA23N_CCL_IN7              _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7              _L_(13)
+#define PINMUX_PA23N_CCL_IN7       ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7     (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7              _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7              _L_(13)
+#define PINMUX_PB07N_CCL_IN7       ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7     (_UL_(1) <<  7)
+#define PIN_PA24N_CCL_IN8              _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8              _L_(13)
+#define PINMUX_PA24N_CCL_IN8       ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8     (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8              _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8              _L_(13)
+#define PINMUX_PB08N_CCL_IN8       ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8     (_UL_(1) <<  8)
+#define PIN_PB14N_CCL_IN9              _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9              _L_(13)
+#define PINMUX_PB14N_CCL_IN9       ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9     (_UL_(1) << 14)
+#define PIN_PB15N_CCL_IN10             _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10             _L_(13)
+#define PINMUX_PB15N_CCL_IN10      ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10    (_UL_(1) << 15)
+#define PIN_PB10N_CCL_IN11             _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11             _L_(13)
+#define PINMUX_PB10N_CCL_IN11      ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11    (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11             _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11             _L_(13)
+#define PINMUX_PB16N_CCL_IN11      ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11    (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0              _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0             _L_(13)
+#define PINMUX_PA07N_CCL_OUT0      ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0    (_UL_(1) <<  7)
+#define PIN_PA19N_CCL_OUT0             _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0             _L_(13)
+#define PINMUX_PA19N_CCL_OUT0      ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0    (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0             _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0             _L_(13)
+#define PINMUX_PB02N_CCL_OUT0      ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0    (_UL_(1) <<  2)
+#define PIN_PB23N_CCL_OUT0             _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0             _L_(13)
+#define PINMUX_PB23N_CCL_OUT0      ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0    (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1             _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1             _L_(13)
+#define PINMUX_PA11N_CCL_OUT1      ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1             _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1             _L_(13)
+#define PINMUX_PA31N_CCL_OUT1      ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1    (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1             _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1             _L_(13)
+#define PINMUX_PB11N_CCL_OUT1      ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2             _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2             _L_(13)
+#define PINMUX_PA25N_CCL_OUT2      ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2    (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2             _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2             _L_(13)
+#define PINMUX_PB09N_CCL_OUT2      ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2    (_UL_(1) <<  9)
+#define PIN_PB17N_CCL_OUT3             _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3             _L_(13)
+#define PINMUX_PB17N_CCL_OUT3      ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3    (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0         _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0  ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0  (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0         _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL_(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1         _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1  ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1  (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1         _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL_(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3         _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3         _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3         _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0         _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0  ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0  (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0         _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL_(1) <<  2)
+#define PIN_PB31D_SERCOM5_PAD0         _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0  ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0  (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0         _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1         _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1  ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1  (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1         _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL_(1) <<  3)
+#define PIN_PB30D_SERCOM5_PAD1         _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1  ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1  (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2         _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL_(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL_(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL_(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL_(1) << 21)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0             _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0              _L_(5)
+#define PINMUX_PB14F_TCC4_WO0      ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0    (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0             _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0              _L_(5)
+#define PINMUX_PB30F_TCC4_WO0      ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0    (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1             _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1              _L_(5)
+#define PINMUX_PB15F_TCC4_WO1      ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1    (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1             _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1              _L_(5)
+#define PINMUX_PB31F_TCC4_WO1      ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1    (_UL_(1) << 31)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0             _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0             _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0     ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0   (_UL_(1) <<  2)
+#define PIN_PA03B_ADC0_AIN1             _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1             _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1     ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1   (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_AIN2            _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2             _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2     ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_AIN3            _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3             _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3     ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3   (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_AIN4             _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4             _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4     ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4   (_UL_(1) <<  4)
+#define PIN_PA05B_ADC0_AIN5             _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5             _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5     ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5   (_UL_(1) <<  5)
+#define PIN_PA06B_ADC0_AIN6             _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6             _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6     ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6   (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_AIN7             _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7             _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7     ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7   (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_AIN8             _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8             _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8     ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_AIN9             _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9             _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9     ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9   (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_AIN10           _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10            _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10    ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11           _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11            _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11    ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11  (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12           _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12            _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12    ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_AIN13           _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13            _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13    ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13  (_UL_(1) <<  1)
+#define PIN_PB02B_ADC0_AIN14           _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14            _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14    ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_AIN15           _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15            _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15    ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15  (_UL_(1) <<  3)
+#define PIN_PA03O_ADC0_DRV0             _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0            _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0     ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0   (_UL_(1) <<  3)
+#define PIN_PB08O_ADC0_DRV1            _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1            _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1     ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1   (_UL_(1) <<  8)
+#define PIN_PB09O_ADC0_DRV2            _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2            _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2     ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2   (_UL_(1) <<  9)
+#define PIN_PA04O_ADC0_DRV3             _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3            _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3     ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3   (_UL_(1) <<  4)
+#define PIN_PA06O_ADC0_DRV4             _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4            _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4     ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4   (_UL_(1) <<  6)
+#define PIN_PA07O_ADC0_DRV5             _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5            _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5     ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5   (_UL_(1) <<  7)
+#define PIN_PA08O_ADC0_DRV6             _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6            _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6     ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6   (_UL_(1) <<  8)
+#define PIN_PA09O_ADC0_DRV7             _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7            _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7     ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7   (_UL_(1) <<  9)
+#define PIN_PA10O_ADC0_DRV8            _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8            _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8     ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8   (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9            _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9            _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9     ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9   (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10           _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10           _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10    ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10  (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11           _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11           _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11    ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11  (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12           _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12           _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12    ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12  (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13           _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13           _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13    ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13  (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14           _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14           _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14    ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14  (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15           _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15           _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15    ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15  (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16           _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16           _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16    ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16  (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17           _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17           _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17    ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17  (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18           _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18           _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18    ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18  (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19           _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19           _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19    ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19  (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20           _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20           _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20    ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20  (_UL_(1) <<  2)
+#define PIN_PB03O_ADC0_DRV21           _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21           _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21    ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21  (_UL_(1) <<  3)
+#define PIN_PB04O_ADC0_DRV22           _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22           _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22    ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22  (_UL_(1) <<  4)
+#define PIN_PB05O_ADC0_DRV23           _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23           _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23    ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23  (_UL_(1) <<  5)
+#define PIN_PB06O_ADC0_DRV24           _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24           _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24    ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24  (_UL_(1) <<  6)
+#define PIN_PB07O_ADC0_DRV25           _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25           _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25    ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25  (_UL_(1) <<  7)
+#define PIN_PB12O_ADC0_DRV26           _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26           _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26    ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26  (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27           _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27           _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27    ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27  (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28           _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28           _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28    ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28  (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29           _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29           _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29    ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29  (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30           _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30           _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30    ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30  (_UL_(1) <<  0)
+#define PIN_PB01O_ADC0_DRV31           _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31           _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31    ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31  (_UL_(1) <<  1)
+#define PIN_PA03B_ADC0_PTCXY0           _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0           _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0   ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0  (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_PTCXY1          _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1           _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1   ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1  (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_PTCXY2          _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2           _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2   ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2  (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_PTCXY3           _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3           _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3   ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3  (_UL_(1) <<  4)
+#define PIN_PA06B_ADC0_PTCXY4           _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4           _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4   ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4  (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_PTCXY5           _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5           _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5   ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5  (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_PTCXY6           _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6           _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6   ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6  (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_PTCXY7           _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7           _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7   ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7  (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_PTCXY8          _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8           _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8   ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9          _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9           _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9   ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9  (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10         _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10          _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10  ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10  (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11         _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11          _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11  ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11  (_UL_(1) << 17)
+#define PIN_PA18B_ADC0_PTCXY12         _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */
+#define MUX_PA18B_ADC0_PTCXY12          _L_(1)
+#define PINMUX_PA18B_ADC0_PTCXY12  ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
+#define PORT_PA18B_ADC0_PTCXY12  (_UL_(1) << 18)
+#define PIN_PA19B_ADC0_PTCXY13         _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13          _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13  ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13  (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14         _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14          _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14  ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14  (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15         _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15          _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15  ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15  (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16         _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16          _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16  ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16  (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17         _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17          _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17  ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17  (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18         _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18          _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18  ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18  (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19         _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19          _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19  ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19  (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20         _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20          _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20  ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_PTCXY21         _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21          _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21  ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21  (_UL_(1) <<  3)
+#define PIN_PB04B_ADC0_PTCXY22         _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22          _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22  ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22  (_UL_(1) <<  4)
+#define PIN_PB05B_ADC0_PTCXY23         _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23          _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23  ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23  (_UL_(1) <<  5)
+#define PIN_PB06B_ADC0_PTCXY24         _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24          _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24  ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24  (_UL_(1) <<  6)
+#define PIN_PB07B_ADC0_PTCXY25         _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25          _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25  ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25  (_UL_(1) <<  7)
+#define PIN_PB12B_ADC0_PTCXY26         _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26          _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26  ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26  (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27         _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27          _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27  ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27  (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28         _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28          _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28  ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28  (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29         _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29          _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29  ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29  (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30         _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30          _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30  ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_PTCXY31         _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31          _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31  ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31  (_UL_(1) <<  1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0            _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0             _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0     ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC1_AIN1            _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1             _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1     ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1   (_UL_(1) <<  9)
+#define PIN_PA08B_ADC1_AIN2             _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2             _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2     ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC1_AIN3             _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3             _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3     ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3   (_UL_(1) <<  9)
+#define PIN_PB04B_ADC1_AIN6            _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6             _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6     ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6   (_UL_(1) <<  4)
+#define PIN_PB05B_ADC1_AIN7            _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7             _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7     ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7   (_UL_(1) <<  5)
+#define PIN_PB06B_ADC1_AIN8            _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8             _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8     ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8   (_UL_(1) <<  6)
+#define PIN_PB07B_ADC1_AIN9            _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9             _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9     ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9   (_UL_(1) <<  7)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0             _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0             _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0   (_UL_(1) <<  2)
+#define PIN_PA05B_DAC_VOUT1             _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1             _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1   (_UL_(1) <<  5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0               _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0               _L_(9)
+#define PINMUX_PA09J_I2S_FS0       ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0     (_UL_(1) <<  9)
+#define PIN_PA20J_I2S_FS0              _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0               _L_(9)
+#define PINMUX_PA20J_I2S_FS0       ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0     (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1              _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1               _L_(9)
+#define PINMUX_PA23J_I2S_FS1       ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1     (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1              _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1               _L_(9)
+#define PINMUX_PB11J_I2S_FS1       ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1     (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0              _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0              _L_(9)
+#define PINMUX_PA08J_I2S_MCK0      ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0    (_UL_(1) <<  8)
+#define PIN_PB17J_I2S_MCK0             _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0              _L_(9)
+#define PINMUX_PB17J_I2S_MCK0      ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0    (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1             _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1              _L_(9)
+#define PINMUX_PB13J_I2S_MCK1      ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1    (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0             _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0              _L_(9)
+#define PINMUX_PA10J_I2S_SCK0      ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0    (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0             _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0              _L_(9)
+#define PINMUX_PB16J_I2S_SCK0      ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0    (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1             _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1              _L_(9)
+#define PINMUX_PB12J_I2S_SCK1      ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1    (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI              _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI               _L_(9)
+#define PINMUX_PA22J_I2S_SDI       ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI     (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI              _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI               _L_(9)
+#define PINMUX_PB10J_I2S_SDI       ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI     (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO              _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO               _L_(9)
+#define PINMUX_PA11J_I2S_SDO       ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO     (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO              _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO               _L_(9)
+#define PINMUX_PA21J_I2S_SDO       ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO     (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK              _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK              _L_(10)
+#define PINMUX_PA14K_PCC_CLK       ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK     (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0            _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0            _L_(10)
+#define PINMUX_PA16K_PCC_DATA0     ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0   (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1            _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1            _L_(10)
+#define PINMUX_PA17K_PCC_DATA1     ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1   (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2            _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2            _L_(10)
+#define PINMUX_PA18K_PCC_DATA2     ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2   (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3            _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3            _L_(10)
+#define PINMUX_PA19K_PCC_DATA3     ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3   (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4            _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4            _L_(10)
+#define PINMUX_PA20K_PCC_DATA4     ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4   (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5            _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5            _L_(10)
+#define PINMUX_PA21K_PCC_DATA5     ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5   (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6            _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6            _L_(10)
+#define PINMUX_PA22K_PCC_DATA6     ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6   (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7            _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7            _L_(10)
+#define PINMUX_PA23K_PCC_DATA7     ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7   (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8            _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8            _L_(10)
+#define PINMUX_PB14K_PCC_DATA8     ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8   (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9            _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9            _L_(10)
+#define PINMUX_PB15K_PCC_DATA9     ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9   (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1             _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1             _L_(10)
+#define PINMUX_PA12K_PCC_DEN1      ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1    (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2             _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2             _L_(10)
+#define PINMUX_PA13K_PCC_DEN2      ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2    (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD            _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD    ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PA12I_SDHC0_SDCD           _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD    ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD           _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD    ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB11I_SDHC0_SDCK           _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK            _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK    ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK  (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD           _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD           _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD   ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD  (_UL_(1) <<  8)
+#define PIN_PA09I_SDHC0_SDDAT0          _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0          _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0  ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0  (_UL_(1) <<  9)
+#define PIN_PA10I_SDHC0_SDDAT1         _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1          _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1  ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1  (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2         _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2          _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2  ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2  (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3         _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3          _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3  ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3  (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP            _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP    ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP  (_UL_(1) <<  7)
+#define PIN_PA13I_SDHC0_SDWP           _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP    ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP           _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP    ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP  (_UL_(1) << 13)
+
+#endif /* _SAME53J19A_PIO_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j20a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j20a.h
new file mode 100644
index 000000000..d45317606
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53j20a.h	
@@ -0,0 +1,1911 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME53J20A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53J20A_PIO_
+#define _SAME53J20A_PIO_
+
+#define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                           12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL_(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                           13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL_(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                           20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL_(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                           21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL_(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                           32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                           33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                           34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                           35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                           36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                           37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                           38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                           39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                           40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                           41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                           42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL_(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                           43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL_(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                           44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL_(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                           45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL_(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                           46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL_(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                           47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL_(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                           48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL_(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                           49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL_(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB22                           54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL_(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                           55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL_(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB30                           62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL_(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                           63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL_(1) << 31) /**< \brief PORT Mask  for PB31 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK            _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK             _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK     ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK   (_UL_(1) << 30)
+#define PIN_PB30H_CM4_SWO              _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO               _L_(7)
+#define PINMUX_PB30H_CM4_SWO       ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO     (_UL_(1) << 30)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0          _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0          _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0  ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0  (_UL_(1) <<  3)
+#define PIN_PA04B_ANAREF_VREF1          _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1          _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1  ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1  (_UL_(1) <<  4)
+#define PIN_PA06B_ANAREF_VREF2          _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2          _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2  ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2  (_UL_(1) <<  6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0             _L_(12)
+#define PINMUX_PA30M_GCLK_IO0      ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0    (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0             _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0             _L_(12)
+#define PINMUX_PB14M_GCLK_IO0      ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0             _L_(12)
+#define PINMUX_PA14M_GCLK_IO0      ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0             _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0             _L_(12)
+#define PINMUX_PB22M_GCLK_IO0      ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0    (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1             _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1             _L_(12)
+#define PINMUX_PB15M_GCLK_IO1      ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1             _L_(12)
+#define PINMUX_PA15M_GCLK_IO1      ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1             _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1             _L_(12)
+#define PINMUX_PB23M_GCLK_IO1      ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1    (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1             _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1             _L_(12)
+#define PINMUX_PA27M_GCLK_IO1      ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1    (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2             _L_(12)
+#define PINMUX_PA16M_GCLK_IO2      ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2             _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2             _L_(12)
+#define PINMUX_PB16M_GCLK_IO2      ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3             _L_(12)
+#define PINMUX_PA17M_GCLK_IO3      ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3             _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3             _L_(12)
+#define PINMUX_PB17M_GCLK_IO3      ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4             _L_(12)
+#define PINMUX_PA10M_GCLK_IO4      ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4             _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4             _L_(12)
+#define PINMUX_PB10M_GCLK_IO4      ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PA11M_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5             _L_(12)
+#define PINMUX_PA11M_GCLK_IO5      ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5             _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5             _L_(12)
+#define PINMUX_PB11M_GCLK_IO5      ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB12M_GCLK_IO6             _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6             _L_(12)
+#define PINMUX_PB12M_GCLK_IO6      ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6    (_UL_(1) << 12)
+#define PIN_PB13M_GCLK_IO7             _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7             _L_(12)
+#define PINMUX_PB13M_GCLK_IO7      ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7    (_UL_(1) << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8          _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8   ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL_(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9          _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9   ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11         _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11  ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14         _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14  ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15         _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15  ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L_(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
+#define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
+#define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
+#define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
+#define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
+#define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
+#define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
+#define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
+#define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
+#define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
+#define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
+#define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2         _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2  ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2  (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3         _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3  ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3  (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0               _L_(4)
+#define PINMUX_PA04E_TC0_WO0       ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0     (_UL_(1) <<  4)
+#define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0               _L_(4)
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
+#define PIN_PB30E_TC0_WO0              _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0               _L_(4)
+#define PINMUX_PB30E_TC0_WO0       ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0     (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1               _L_(4)
+#define PINMUX_PA05E_TC0_WO1       ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1     (_UL_(1) <<  5)
+#define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1               _L_(4)
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
+#define PIN_PB31E_TC0_WO1              _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1               _L_(4)
+#define PINMUX_PB31E_TC0_WO1       ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1     (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0               _L_(4)
+#define PINMUX_PA06E_TC1_WO0       ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0     (_UL_(1) <<  6)
+#define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0               _L_(4)
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1               _L_(4)
+#define PINMUX_PA07E_TC1_WO1       ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1     (_UL_(1) <<  7)
+#define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1               _L_(4)
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM               _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM                _L_(7)
+#define PINMUX_PA24H_USB_DM        ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM      (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP               _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP                _L_(7)
+#define PINMUX_PA25H_USB_DP        ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP      (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ         _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ  ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ  (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ         _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ  ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ  (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0          _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0  ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0  (_UL_(1) <<  9)
+#define PIN_PA12C_SERCOM2_PAD0         _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1          _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1  ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1  (_UL_(1) <<  8)
+#define PIN_PA13C_SERCOM2_PAD1         _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
+#define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
+#define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0         _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0          _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0  ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0  (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
+#define PIN_PA16D_SERCOM3_PAD1         _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1          _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1  ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1  (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
+#define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0             _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0              _L_(6)
+#define PINMUX_PA20G_TCC0_WO0      ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0    (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0             _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0              _L_(6)
+#define PINMUX_PB12G_TCC0_WO0      ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0    (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0              _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0              _L_(5)
+#define PINMUX_PA08F_TCC0_WO0      ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0    (_UL_(1) <<  8)
+#define PIN_PA21G_TCC0_WO1             _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1              _L_(6)
+#define PINMUX_PA21G_TCC0_WO1      ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1    (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1             _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1              _L_(6)
+#define PINMUX_PB13G_TCC0_WO1      ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1    (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1              _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1              _L_(5)
+#define PINMUX_PA09F_TCC0_WO1      ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1    (_UL_(1) <<  9)
+#define PIN_PA22G_TCC0_WO2             _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2              _L_(6)
+#define PINMUX_PA22G_TCC0_WO2      ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2    (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2             _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2              _L_(6)
+#define PINMUX_PB14G_TCC0_WO2      ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2    (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2             _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L_(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL_(1) << 10)
+#define PIN_PA23G_TCC0_WO3             _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3              _L_(6)
+#define PINMUX_PA23G_TCC0_WO3      ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3    (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3             _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3              _L_(6)
+#define PINMUX_PB15G_TCC0_WO3      ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3    (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3             _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L_(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL_(1) << 11)
+#define PIN_PA16G_TCC0_WO4             _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4              _L_(6)
+#define PINMUX_PA16G_TCC0_WO4      ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4             _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4              _L_(6)
+#define PINMUX_PB16G_TCC0_WO4      ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4             _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L_(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL_(1) << 10)
+#define PIN_PA17G_TCC0_WO5             _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5              _L_(6)
+#define PINMUX_PA17G_TCC0_WO5      ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5             _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5              _L_(6)
+#define PINMUX_PB17G_TCC0_WO5      ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5             _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L_(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL_(1) << 11)
+#define PIN_PA18G_TCC0_WO6             _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6              _L_(6)
+#define PINMUX_PA18G_TCC0_WO6      ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6    (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6             _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6              _L_(6)
+#define PINMUX_PB30G_TCC0_WO6      ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6    (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6             _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L_(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7             _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7              _L_(6)
+#define PINMUX_PA19G_TCC0_WO7      ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7    (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7             _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7              _L_(6)
+#define PINMUX_PB31G_TCC0_WO7      ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7    (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7             _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L_(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0             _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0              _L_(6)
+#define PINMUX_PB10G_TCC1_WO0      ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0    (_UL_(1) << 10)
+#define PIN_PA16F_TCC1_WO0             _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0              _L_(5)
+#define PINMUX_PA16F_TCC1_WO0      ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0    (_UL_(1) << 16)
+#define PIN_PB11G_TCC1_WO1             _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1              _L_(6)
+#define PINMUX_PB11G_TCC1_WO1      ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1    (_UL_(1) << 11)
+#define PIN_PA17F_TCC1_WO1             _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1              _L_(5)
+#define PINMUX_PA17F_TCC1_WO1      ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1    (_UL_(1) << 17)
+#define PIN_PA12G_TCC1_WO2             _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2              _L_(6)
+#define PINMUX_PA12G_TCC1_WO2      ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2    (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2             _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2              _L_(6)
+#define PINMUX_PA14G_TCC1_WO2      ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2    (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2             _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2              _L_(5)
+#define PINMUX_PA18F_TCC1_WO2      ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2    (_UL_(1) << 18)
+#define PIN_PA13G_TCC1_WO3             _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3              _L_(6)
+#define PINMUX_PA13G_TCC1_WO3      ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3    (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3             _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3              _L_(6)
+#define PINMUX_PA15G_TCC1_WO3      ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3    (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3             _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3              _L_(5)
+#define PINMUX_PA19F_TCC1_WO3      ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3    (_UL_(1) << 19)
+#define PIN_PA08G_TCC1_WO4              _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4              _L_(6)
+#define PINMUX_PA08G_TCC1_WO4      ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4    (_UL_(1) <<  8)
+#define PIN_PA20F_TCC1_WO4             _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4              _L_(5)
+#define PINMUX_PA20F_TCC1_WO4      ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4    (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5              _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5              _L_(6)
+#define PINMUX_PA09G_TCC1_WO5      ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5    (_UL_(1) <<  9)
+#define PIN_PA21F_TCC1_WO5             _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5              _L_(5)
+#define PINMUX_PA21F_TCC1_WO5      ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5    (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6             _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6              _L_(6)
+#define PINMUX_PA10G_TCC1_WO6      ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6    (_UL_(1) << 10)
+#define PIN_PA22F_TCC1_WO6             _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6              _L_(5)
+#define PINMUX_PA22F_TCC1_WO6      ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6    (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7             _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7              _L_(6)
+#define PINMUX_PA11G_TCC1_WO7      ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7    (_UL_(1) << 11)
+#define PIN_PA23F_TCC1_WO7             _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7              _L_(5)
+#define PINMUX_PA23F_TCC1_WO7      ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7    (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0              _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0               _L_(4)
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0     (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0               _L_(4)
+#define PINMUX_PA16E_TC2_WO0       ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0     (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0               _L_(4)
+#define PINMUX_PA00E_TC2_WO0       ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0     (_UL_(1) <<  0)
+#define PIN_PA01E_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1               _L_(4)
+#define PINMUX_PA01E_TC2_WO1       ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1     (_UL_(1) <<  1)
+#define PIN_PA13E_TC2_WO1              _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1               _L_(4)
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1     (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1               _L_(4)
+#define PINMUX_PA17E_TC2_WO1       ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L_(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L_(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L_(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L_(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL_(1) << 19)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PA16L_GMAC_GCRS            _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS            _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS     ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS   (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC            _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC            _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC     ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC   (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC            _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC            _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC     ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC   (_UL_(1) << 14)
+#define PIN_PA21L_GMAC_GMDIO           _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO    ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO  (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO           _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO    ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO  (_UL_(1) << 15)
+#define PIN_PA13L_GMAC_GRX0            _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0            _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0     ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0   (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1            _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1            _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1     ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1   (_UL_(1) << 12)
+#define PIN_PA16L_GMAC_GRXDV           _L_(16) /**< \brief GMAC signal: GRXDV on PA16 mux L */
+#define MUX_PA16L_GMAC_GRXDV           _L_(11)
+#define PINMUX_PA16L_GMAC_GRXDV    ((PIN_PA16L_GMAC_GRXDV << 16) | MUX_PA16L_GMAC_GRXDV)
+#define PORT_PA16L_GMAC_GRXDV  (_UL_(1) << 16)
+#define PIN_PA15L_GMAC_GRXER           _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER           _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER    ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER  (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0            _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0            _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0     ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0   (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1            _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1            _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1     ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1   (_UL_(1) << 19)
+#define PIN_PA14L_GMAC_GTXCK           _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK           _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK    ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK  (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN           _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN           _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN    ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN  (_UL_(1) << 17)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0             _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0              _L_(5)
+#define PINMUX_PA14F_TCC2_WO0      ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0    (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0             _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0              _L_(5)
+#define PINMUX_PA30F_TCC2_WO0      ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0    (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1             _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1              _L_(5)
+#define PINMUX_PA15F_TCC2_WO1      ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1    (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1             _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1              _L_(5)
+#define PINMUX_PA31F_TCC2_WO1      ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1    (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2             _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2              _L_(5)
+#define PINMUX_PA24F_TCC2_WO2      ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2    (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2             _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2              _L_(5)
+#define PINMUX_PB02F_TCC2_WO2      ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2    (_UL_(1) <<  2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0             _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0              _L_(5)
+#define PINMUX_PB12F_TCC3_WO0      ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0    (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0             _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0              _L_(5)
+#define PINMUX_PB16F_TCC3_WO0      ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0    (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1             _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1              _L_(5)
+#define PINMUX_PB13F_TCC3_WO1      ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1    (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1             _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1              _L_(5)
+#define PINMUX_PB17F_TCC3_WO1      ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1    (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L_(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L_(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL_(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L_(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L_(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L_(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL_(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L_(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L_(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L_(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L_(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L_(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L_(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L_(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB23G_PDEC_QDI0            _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0     ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0   (_UL_(1) << 23)
+#define PIN_PA24G_PDEC_QDI0            _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0             _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0     ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0   (_UL_(1) << 24)
+#define PIN_PA25G_PDEC_QDI1            _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1             _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1     ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1   (_UL_(1) << 25)
+#define PIN_PB22G_PDEC_QDI2            _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2     ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2   (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L_(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L_(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L_(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L_(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
+#define PIN_PA12M_AC_CMP0              _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0              _L_(12)
+#define PINMUX_PA12M_AC_CMP0       ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0     (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0              _L_(12)
+#define PINMUX_PA18M_AC_CMP0       ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0     (_UL_(1) << 18)
+#define PIN_PA13M_AC_CMP1              _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1              _L_(12)
+#define PINMUX_PA13M_AC_CMP1       ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1     (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1              _L_(12)
+#define PINMUX_PA19M_AC_CMP1       ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1     (_UL_(1) << 19)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS              _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS               _L_(7)
+#define PINMUX_PB11H_QSPI_CS       ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS     (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0            _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0            _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0    ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0  (_UL_(1) <<  8)
+#define PIN_PA09H_QSPI_DATA1            _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1            _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1    ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1  (_UL_(1) <<  9)
+#define PIN_PA10H_QSPI_DATA2           _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2            _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2    ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2  (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3           _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3            _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3    ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3  (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK             _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK              _L_(7)
+#define PINMUX_PB10H_QSPI_SCK      ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK    (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0               _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0              _L_(13)
+#define PINMUX_PA04N_CCL_IN0       ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0     (_UL_(1) <<  4)
+#define PIN_PA16N_CCL_IN0              _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0              _L_(13)
+#define PINMUX_PA16N_CCL_IN0       ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0     (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0              _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0              _L_(13)
+#define PINMUX_PB22N_CCL_IN0       ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0     (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1               _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1              _L_(13)
+#define PINMUX_PA05N_CCL_IN1       ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1     (_UL_(1) <<  5)
+#define PIN_PA17N_CCL_IN1              _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1              _L_(13)
+#define PINMUX_PA17N_CCL_IN1       ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1     (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1              _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1              _L_(13)
+#define PINMUX_PB00N_CCL_IN1       ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1     (_UL_(1) <<  0)
+#define PIN_PA06N_CCL_IN2               _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2              _L_(13)
+#define PINMUX_PA06N_CCL_IN2       ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2     (_UL_(1) <<  6)
+#define PIN_PA18N_CCL_IN2              _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2              _L_(13)
+#define PINMUX_PA18N_CCL_IN2       ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2     (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2              _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2              _L_(13)
+#define PINMUX_PB01N_CCL_IN2       ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2     (_UL_(1) <<  1)
+#define PIN_PA08N_CCL_IN3               _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3              _L_(13)
+#define PINMUX_PA08N_CCL_IN3       ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3     (_UL_(1) <<  8)
+#define PIN_PA30N_CCL_IN3              _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3              _L_(13)
+#define PINMUX_PA30N_CCL_IN3       ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3     (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4               _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4              _L_(13)
+#define PINMUX_PA09N_CCL_IN4       ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4     (_UL_(1) <<  9)
+#define PIN_PA10N_CCL_IN5              _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5              _L_(13)
+#define PINMUX_PA10N_CCL_IN5       ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5     (_UL_(1) << 10)
+#define PIN_PA22N_CCL_IN6              _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6              _L_(13)
+#define PINMUX_PA22N_CCL_IN6       ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6     (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6              _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6              _L_(13)
+#define PINMUX_PB06N_CCL_IN6       ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6     (_UL_(1) <<  6)
+#define PIN_PA23N_CCL_IN7              _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7              _L_(13)
+#define PINMUX_PA23N_CCL_IN7       ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7     (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7              _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7              _L_(13)
+#define PINMUX_PB07N_CCL_IN7       ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7     (_UL_(1) <<  7)
+#define PIN_PA24N_CCL_IN8              _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8              _L_(13)
+#define PINMUX_PA24N_CCL_IN8       ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8     (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8              _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8              _L_(13)
+#define PINMUX_PB08N_CCL_IN8       ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8     (_UL_(1) <<  8)
+#define PIN_PB14N_CCL_IN9              _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9              _L_(13)
+#define PINMUX_PB14N_CCL_IN9       ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9     (_UL_(1) << 14)
+#define PIN_PB15N_CCL_IN10             _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10             _L_(13)
+#define PINMUX_PB15N_CCL_IN10      ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10    (_UL_(1) << 15)
+#define PIN_PB10N_CCL_IN11             _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11             _L_(13)
+#define PINMUX_PB10N_CCL_IN11      ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11    (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11             _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11             _L_(13)
+#define PINMUX_PB16N_CCL_IN11      ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11    (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0              _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0             _L_(13)
+#define PINMUX_PA07N_CCL_OUT0      ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0    (_UL_(1) <<  7)
+#define PIN_PA19N_CCL_OUT0             _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0             _L_(13)
+#define PINMUX_PA19N_CCL_OUT0      ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0    (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0             _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0             _L_(13)
+#define PINMUX_PB02N_CCL_OUT0      ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0    (_UL_(1) <<  2)
+#define PIN_PB23N_CCL_OUT0             _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0             _L_(13)
+#define PINMUX_PB23N_CCL_OUT0      ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0    (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1             _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1             _L_(13)
+#define PINMUX_PA11N_CCL_OUT1      ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1             _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1             _L_(13)
+#define PINMUX_PA31N_CCL_OUT1      ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1    (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1             _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1             _L_(13)
+#define PINMUX_PB11N_CCL_OUT1      ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2             _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2             _L_(13)
+#define PINMUX_PA25N_CCL_OUT2      ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2    (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2             _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2             _L_(13)
+#define PINMUX_PB09N_CCL_OUT2      ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2    (_UL_(1) <<  9)
+#define PIN_PB17N_CCL_OUT3             _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3             _L_(13)
+#define PINMUX_PB17N_CCL_OUT3      ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3    (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0         _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0  ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0  (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0         _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL_(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1         _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1  ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1  (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1         _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL_(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3         _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3         _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3         _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0         _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0  ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0  (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0         _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL_(1) <<  2)
+#define PIN_PB31D_SERCOM5_PAD0         _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0  ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0  (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0         _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1         _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1  ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1  (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1         _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL_(1) <<  3)
+#define PIN_PB30D_SERCOM5_PAD1         _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1  ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1  (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2         _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL_(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL_(1) << 20)
+#define PIN_PA25D_SERCOM5_PAD3         _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL_(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL_(1) << 21)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0             _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0              _L_(5)
+#define PINMUX_PB14F_TCC4_WO0      ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0    (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0             _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0              _L_(5)
+#define PINMUX_PB30F_TCC4_WO0      ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0    (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1             _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1              _L_(5)
+#define PINMUX_PB15F_TCC4_WO1      ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1    (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1             _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1              _L_(5)
+#define PINMUX_PB31F_TCC4_WO1      ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1    (_UL_(1) << 31)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0             _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0             _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0     ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0   (_UL_(1) <<  2)
+#define PIN_PA03B_ADC0_AIN1             _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1             _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1     ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1   (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_AIN2            _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2             _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2     ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_AIN3            _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3             _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3     ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3   (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_AIN4             _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4             _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4     ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4   (_UL_(1) <<  4)
+#define PIN_PA05B_ADC0_AIN5             _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5             _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5     ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5   (_UL_(1) <<  5)
+#define PIN_PA06B_ADC0_AIN6             _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6             _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6     ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6   (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_AIN7             _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7             _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7     ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7   (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_AIN8             _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8             _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8     ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_AIN9             _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9             _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9     ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9   (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_AIN10           _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10            _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10    ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11           _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11            _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11    ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11  (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12           _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12            _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12    ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_AIN13           _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13            _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13    ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13  (_UL_(1) <<  1)
+#define PIN_PB02B_ADC0_AIN14           _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14            _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14    ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_AIN15           _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15            _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15    ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15  (_UL_(1) <<  3)
+#define PIN_PA03O_ADC0_DRV0             _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0            _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0     ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0   (_UL_(1) <<  3)
+#define PIN_PB08O_ADC0_DRV1            _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1            _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1     ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1   (_UL_(1) <<  8)
+#define PIN_PB09O_ADC0_DRV2            _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2            _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2     ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2   (_UL_(1) <<  9)
+#define PIN_PA04O_ADC0_DRV3             _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3            _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3     ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3   (_UL_(1) <<  4)
+#define PIN_PA06O_ADC0_DRV4             _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4            _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4     ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4   (_UL_(1) <<  6)
+#define PIN_PA07O_ADC0_DRV5             _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5            _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5     ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5   (_UL_(1) <<  7)
+#define PIN_PA08O_ADC0_DRV6             _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6            _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6     ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6   (_UL_(1) <<  8)
+#define PIN_PA09O_ADC0_DRV7             _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7            _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7     ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7   (_UL_(1) <<  9)
+#define PIN_PA10O_ADC0_DRV8            _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8            _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8     ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8   (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9            _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9            _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9     ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9   (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10           _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10           _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10    ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10  (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11           _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11           _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11    ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11  (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12           _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12           _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12    ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12  (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13           _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13           _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13    ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13  (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14           _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14           _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14    ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14  (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15           _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15           _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15    ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15  (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16           _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16           _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16    ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16  (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17           _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17           _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17    ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17  (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18           _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18           _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18    ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18  (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19           _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19           _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19    ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19  (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20           _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20           _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20    ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20  (_UL_(1) <<  2)
+#define PIN_PB03O_ADC0_DRV21           _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21           _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21    ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21  (_UL_(1) <<  3)
+#define PIN_PB04O_ADC0_DRV22           _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22           _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22    ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22  (_UL_(1) <<  4)
+#define PIN_PB05O_ADC0_DRV23           _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23           _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23    ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23  (_UL_(1) <<  5)
+#define PIN_PB06O_ADC0_DRV24           _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24           _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24    ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24  (_UL_(1) <<  6)
+#define PIN_PB07O_ADC0_DRV25           _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25           _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25    ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25  (_UL_(1) <<  7)
+#define PIN_PB12O_ADC0_DRV26           _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26           _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26    ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26  (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27           _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27           _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27    ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27  (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28           _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28           _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28    ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28  (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29           _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29           _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29    ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29  (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30           _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30           _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30    ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30  (_UL_(1) <<  0)
+#define PIN_PB01O_ADC0_DRV31           _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31           _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31    ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31  (_UL_(1) <<  1)
+#define PIN_PA03B_ADC0_PTCXY0           _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0           _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0   ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0  (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_PTCXY1          _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1           _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1   ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1  (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_PTCXY2          _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2           _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2   ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2  (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_PTCXY3           _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3           _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3   ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3  (_UL_(1) <<  4)
+#define PIN_PA06B_ADC0_PTCXY4           _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4           _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4   ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4  (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_PTCXY5           _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5           _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5   ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5  (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_PTCXY6           _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6           _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6   ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6  (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_PTCXY7           _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7           _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7   ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7  (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_PTCXY8          _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8           _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8   ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9          _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9           _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9   ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9  (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10         _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10          _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10  ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10  (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11         _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11          _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11  ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11  (_UL_(1) << 17)
+#define PIN_PA18B_ADC0_PTCXY12         _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */
+#define MUX_PA18B_ADC0_PTCXY12          _L_(1)
+#define PINMUX_PA18B_ADC0_PTCXY12  ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
+#define PORT_PA18B_ADC0_PTCXY12  (_UL_(1) << 18)
+#define PIN_PA19B_ADC0_PTCXY13         _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13          _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13  ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13  (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14         _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14          _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14  ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14  (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15         _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15          _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15  ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15  (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16         _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16          _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16  ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16  (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17         _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17          _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17  ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17  (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18         _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18          _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18  ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18  (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19         _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19          _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19  ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19  (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20         _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20          _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20  ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_PTCXY21         _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21          _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21  ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21  (_UL_(1) <<  3)
+#define PIN_PB04B_ADC0_PTCXY22         _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22          _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22  ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22  (_UL_(1) <<  4)
+#define PIN_PB05B_ADC0_PTCXY23         _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23          _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23  ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23  (_UL_(1) <<  5)
+#define PIN_PB06B_ADC0_PTCXY24         _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24          _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24  ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24  (_UL_(1) <<  6)
+#define PIN_PB07B_ADC0_PTCXY25         _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25          _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25  ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25  (_UL_(1) <<  7)
+#define PIN_PB12B_ADC0_PTCXY26         _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26          _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26  ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26  (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27         _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27          _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27  ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27  (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28         _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28          _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28  ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28  (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29         _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29          _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29  ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29  (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30         _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30          _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30  ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_PTCXY31         _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31          _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31  ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31  (_UL_(1) <<  1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0            _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0             _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0     ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC1_AIN1            _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1             _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1     ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1   (_UL_(1) <<  9)
+#define PIN_PA08B_ADC1_AIN2             _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2             _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2     ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC1_AIN3             _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3             _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3     ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3   (_UL_(1) <<  9)
+#define PIN_PB04B_ADC1_AIN6            _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6             _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6     ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6   (_UL_(1) <<  4)
+#define PIN_PB05B_ADC1_AIN7            _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7             _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7     ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7   (_UL_(1) <<  5)
+#define PIN_PB06B_ADC1_AIN8            _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8             _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8     ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8   (_UL_(1) <<  6)
+#define PIN_PB07B_ADC1_AIN9            _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9             _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9     ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9   (_UL_(1) <<  7)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0             _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0             _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0   (_UL_(1) <<  2)
+#define PIN_PA05B_DAC_VOUT1             _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1             _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1   (_UL_(1) <<  5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0               _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0               _L_(9)
+#define PINMUX_PA09J_I2S_FS0       ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0     (_UL_(1) <<  9)
+#define PIN_PA20J_I2S_FS0              _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0               _L_(9)
+#define PINMUX_PA20J_I2S_FS0       ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0     (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1              _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1               _L_(9)
+#define PINMUX_PA23J_I2S_FS1       ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1     (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1              _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1               _L_(9)
+#define PINMUX_PB11J_I2S_FS1       ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1     (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0              _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0              _L_(9)
+#define PINMUX_PA08J_I2S_MCK0      ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0    (_UL_(1) <<  8)
+#define PIN_PB17J_I2S_MCK0             _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0              _L_(9)
+#define PINMUX_PB17J_I2S_MCK0      ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0    (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1             _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1              _L_(9)
+#define PINMUX_PB13J_I2S_MCK1      ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1    (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0             _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0              _L_(9)
+#define PINMUX_PA10J_I2S_SCK0      ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0    (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0             _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0              _L_(9)
+#define PINMUX_PB16J_I2S_SCK0      ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0    (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1             _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1              _L_(9)
+#define PINMUX_PB12J_I2S_SCK1      ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1    (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI              _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI               _L_(9)
+#define PINMUX_PA22J_I2S_SDI       ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI     (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI              _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI               _L_(9)
+#define PINMUX_PB10J_I2S_SDI       ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI     (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO              _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO               _L_(9)
+#define PINMUX_PA11J_I2S_SDO       ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO     (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO              _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO               _L_(9)
+#define PINMUX_PA21J_I2S_SDO       ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO     (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK              _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK              _L_(10)
+#define PINMUX_PA14K_PCC_CLK       ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK     (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0            _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0            _L_(10)
+#define PINMUX_PA16K_PCC_DATA0     ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0   (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1            _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1            _L_(10)
+#define PINMUX_PA17K_PCC_DATA1     ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1   (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2            _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2            _L_(10)
+#define PINMUX_PA18K_PCC_DATA2     ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2   (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3            _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3            _L_(10)
+#define PINMUX_PA19K_PCC_DATA3     ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3   (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4            _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4            _L_(10)
+#define PINMUX_PA20K_PCC_DATA4     ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4   (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5            _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5            _L_(10)
+#define PINMUX_PA21K_PCC_DATA5     ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5   (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6            _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6            _L_(10)
+#define PINMUX_PA22K_PCC_DATA6     ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6   (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7            _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7            _L_(10)
+#define PINMUX_PA23K_PCC_DATA7     ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7   (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8            _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8            _L_(10)
+#define PINMUX_PB14K_PCC_DATA8     ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8   (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9            _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9            _L_(10)
+#define PINMUX_PB15K_PCC_DATA9     ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9   (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1             _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1             _L_(10)
+#define PINMUX_PA12K_PCC_DEN1      ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1    (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2             _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2             _L_(10)
+#define PINMUX_PA13K_PCC_DEN2      ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2    (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD            _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD    ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PA12I_SDHC0_SDCD           _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD    ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD           _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD    ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB11I_SDHC0_SDCK           _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK            _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK    ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK  (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD           _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD           _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD   ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD  (_UL_(1) <<  8)
+#define PIN_PA09I_SDHC0_SDDAT0          _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0          _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0  ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0  (_UL_(1) <<  9)
+#define PIN_PA10I_SDHC0_SDDAT1         _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1          _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1  ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1  (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2         _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2          _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2  ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2  (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3         _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3          _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3  ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3  (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP            _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP    ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP  (_UL_(1) <<  7)
+#define PIN_PA13I_SDHC0_SDWP           _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP    ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP           _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP    ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP  (_UL_(1) << 13)
+
+#endif /* _SAME53J20A_PIO_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53n19a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53n19a.h
new file mode 100644
index 000000000..a91508000
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53n19a.h	
@@ -0,0 +1,2654 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME53N19A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53N19A_PIO_
+#define _SAME53N19A_PIO_
+
+#define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                           12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL_(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                           13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL_(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                           20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL_(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                           21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL_(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                           32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                           33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                           34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                           35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                           36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                           37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                           38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                           39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                           40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                           41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                           42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL_(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                           43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL_(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                           44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL_(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                           45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL_(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                           46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL_(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                           47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL_(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                           48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL_(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                           49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL_(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB18                           50  /**< \brief Pin Number for PB18 */
+#define PORT_PB18              (_UL_(1) << 18) /**< \brief PORT Mask  for PB18 */
+#define PIN_PB19                           51  /**< \brief Pin Number for PB19 */
+#define PORT_PB19              (_UL_(1) << 19) /**< \brief PORT Mask  for PB19 */
+#define PIN_PB20                           52  /**< \brief Pin Number for PB20 */
+#define PORT_PB20              (_UL_(1) << 20) /**< \brief PORT Mask  for PB20 */
+#define PIN_PB21                           53  /**< \brief Pin Number for PB21 */
+#define PORT_PB21              (_UL_(1) << 21) /**< \brief PORT Mask  for PB21 */
+#define PIN_PB22                           54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL_(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                           55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL_(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB24                           56  /**< \brief Pin Number for PB24 */
+#define PORT_PB24              (_UL_(1) << 24) /**< \brief PORT Mask  for PB24 */
+#define PIN_PB25                           57  /**< \brief Pin Number for PB25 */
+#define PORT_PB25              (_UL_(1) << 25) /**< \brief PORT Mask  for PB25 */
+#define PIN_PB30                           62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL_(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                           63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL_(1) << 31) /**< \brief PORT Mask  for PB31 */
+#define PIN_PC00                           64  /**< \brief Pin Number for PC00 */
+#define PORT_PC00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PC00 */
+#define PIN_PC01                           65  /**< \brief Pin Number for PC01 */
+#define PORT_PC01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PC01 */
+#define PIN_PC02                           66  /**< \brief Pin Number for PC02 */
+#define PORT_PC02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PC02 */
+#define PIN_PC03                           67  /**< \brief Pin Number for PC03 */
+#define PORT_PC03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PC03 */
+#define PIN_PC05                           69  /**< \brief Pin Number for PC05 */
+#define PORT_PC05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PC05 */
+#define PIN_PC06                           70  /**< \brief Pin Number for PC06 */
+#define PORT_PC06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PC06 */
+#define PIN_PC07                           71  /**< \brief Pin Number for PC07 */
+#define PORT_PC07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PC07 */
+#define PIN_PC10                           74  /**< \brief Pin Number for PC10 */
+#define PORT_PC10              (_UL_(1) << 10) /**< \brief PORT Mask  for PC10 */
+#define PIN_PC11                           75  /**< \brief Pin Number for PC11 */
+#define PORT_PC11              (_UL_(1) << 11) /**< \brief PORT Mask  for PC11 */
+#define PIN_PC12                           76  /**< \brief Pin Number for PC12 */
+#define PORT_PC12              (_UL_(1) << 12) /**< \brief PORT Mask  for PC12 */
+#define PIN_PC13                           77  /**< \brief Pin Number for PC13 */
+#define PORT_PC13              (_UL_(1) << 13) /**< \brief PORT Mask  for PC13 */
+#define PIN_PC14                           78  /**< \brief Pin Number for PC14 */
+#define PORT_PC14              (_UL_(1) << 14) /**< \brief PORT Mask  for PC14 */
+#define PIN_PC15                           79  /**< \brief Pin Number for PC15 */
+#define PORT_PC15              (_UL_(1) << 15) /**< \brief PORT Mask  for PC15 */
+#define PIN_PC16                           80  /**< \brief Pin Number for PC16 */
+#define PORT_PC16              (_UL_(1) << 16) /**< \brief PORT Mask  for PC16 */
+#define PIN_PC17                           81  /**< \brief Pin Number for PC17 */
+#define PORT_PC17              (_UL_(1) << 17) /**< \brief PORT Mask  for PC17 */
+#define PIN_PC18                           82  /**< \brief Pin Number for PC18 */
+#define PORT_PC18              (_UL_(1) << 18) /**< \brief PORT Mask  for PC18 */
+#define PIN_PC19                           83  /**< \brief Pin Number for PC19 */
+#define PORT_PC19              (_UL_(1) << 19) /**< \brief PORT Mask  for PC19 */
+#define PIN_PC20                           84  /**< \brief Pin Number for PC20 */
+#define PORT_PC20              (_UL_(1) << 20) /**< \brief PORT Mask  for PC20 */
+#define PIN_PC21                           85  /**< \brief Pin Number for PC21 */
+#define PORT_PC21              (_UL_(1) << 21) /**< \brief PORT Mask  for PC21 */
+#define PIN_PC24                           88  /**< \brief Pin Number for PC24 */
+#define PORT_PC24              (_UL_(1) << 24) /**< \brief PORT Mask  for PC24 */
+#define PIN_PC25                           89  /**< \brief Pin Number for PC25 */
+#define PORT_PC25              (_UL_(1) << 25) /**< \brief PORT Mask  for PC25 */
+#define PIN_PC26                           90  /**< \brief Pin Number for PC26 */
+#define PORT_PC26              (_UL_(1) << 26) /**< \brief PORT Mask  for PC26 */
+#define PIN_PC27                           91  /**< \brief Pin Number for PC27 */
+#define PORT_PC27              (_UL_(1) << 27) /**< \brief PORT Mask  for PC27 */
+#define PIN_PC28                           92  /**< \brief Pin Number for PC28 */
+#define PORT_PC28              (_UL_(1) << 28) /**< \brief PORT Mask  for PC28 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK            _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK             _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK     ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK   (_UL_(1) << 30)
+#define PIN_PC27M_CM4_SWO              _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
+#define MUX_PC27M_CM4_SWO              _L_(12)
+#define PINMUX_PC27M_CM4_SWO       ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
+#define PORT_PC27M_CM4_SWO     (_UL_(1) << 27)
+#define PIN_PB30H_CM4_SWO              _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO               _L_(7)
+#define PINMUX_PB30H_CM4_SWO       ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO     (_UL_(1) << 30)
+#define PIN_PC27H_CM4_TRACECLK         _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
+#define MUX_PC27H_CM4_TRACECLK          _L_(7)
+#define PINMUX_PC27H_CM4_TRACECLK  ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
+#define PORT_PC27H_CM4_TRACECLK  (_UL_(1) << 27)
+#define PIN_PC28H_CM4_TRACEDATA0       _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
+#define MUX_PC28H_CM4_TRACEDATA0        _L_(7)
+#define PINMUX_PC28H_CM4_TRACEDATA0  ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
+#define PORT_PC28H_CM4_TRACEDATA0  (_UL_(1) << 28)
+#define PIN_PC26H_CM4_TRACEDATA1       _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
+#define MUX_PC26H_CM4_TRACEDATA1        _L_(7)
+#define PINMUX_PC26H_CM4_TRACEDATA1  ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
+#define PORT_PC26H_CM4_TRACEDATA1  (_UL_(1) << 26)
+#define PIN_PC25H_CM4_TRACEDATA2       _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
+#define MUX_PC25H_CM4_TRACEDATA2        _L_(7)
+#define PINMUX_PC25H_CM4_TRACEDATA2  ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
+#define PORT_PC25H_CM4_TRACEDATA2  (_UL_(1) << 25)
+#define PIN_PC24H_CM4_TRACEDATA3       _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
+#define MUX_PC24H_CM4_TRACEDATA3        _L_(7)
+#define PINMUX_PC24H_CM4_TRACEDATA3  ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
+#define PORT_PC24H_CM4_TRACEDATA3  (_UL_(1) << 24)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0          _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0          _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0  ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0  (_UL_(1) <<  3)
+#define PIN_PA04B_ANAREF_VREF1          _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1          _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1  ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1  (_UL_(1) <<  4)
+#define PIN_PA06B_ANAREF_VREF2          _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2          _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2  ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2  (_UL_(1) <<  6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0             _L_(12)
+#define PINMUX_PA30M_GCLK_IO0      ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0    (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0             _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0             _L_(12)
+#define PINMUX_PB14M_GCLK_IO0      ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0             _L_(12)
+#define PINMUX_PA14M_GCLK_IO0      ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0             _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0             _L_(12)
+#define PINMUX_PB22M_GCLK_IO0      ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0    (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1             _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1             _L_(12)
+#define PINMUX_PB15M_GCLK_IO1      ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1             _L_(12)
+#define PINMUX_PA15M_GCLK_IO1      ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1             _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1             _L_(12)
+#define PINMUX_PB23M_GCLK_IO1      ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1    (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1             _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1             _L_(12)
+#define PINMUX_PA27M_GCLK_IO1      ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1    (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2             _L_(12)
+#define PINMUX_PA16M_GCLK_IO2      ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2             _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2             _L_(12)
+#define PINMUX_PB16M_GCLK_IO2      ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3             _L_(12)
+#define PINMUX_PA17M_GCLK_IO3      ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3             _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3             _L_(12)
+#define PINMUX_PB17M_GCLK_IO3      ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4             _L_(12)
+#define PINMUX_PA10M_GCLK_IO4      ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4             _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4             _L_(12)
+#define PINMUX_PB10M_GCLK_IO4      ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB18M_GCLK_IO4             _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
+#define MUX_PB18M_GCLK_IO4             _L_(12)
+#define PINMUX_PB18M_GCLK_IO4      ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
+#define PORT_PB18M_GCLK_IO4    (_UL_(1) << 18)
+#define PIN_PA11M_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5             _L_(12)
+#define PINMUX_PA11M_GCLK_IO5      ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5             _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5             _L_(12)
+#define PINMUX_PB11M_GCLK_IO5      ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB19M_GCLK_IO5             _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
+#define MUX_PB19M_GCLK_IO5             _L_(12)
+#define PINMUX_PB19M_GCLK_IO5      ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
+#define PORT_PB19M_GCLK_IO5    (_UL_(1) << 19)
+#define PIN_PB12M_GCLK_IO6             _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6             _L_(12)
+#define PINMUX_PB12M_GCLK_IO6      ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6    (_UL_(1) << 12)
+#define PIN_PB20M_GCLK_IO6             _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
+#define MUX_PB20M_GCLK_IO6             _L_(12)
+#define PINMUX_PB20M_GCLK_IO6      ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
+#define PORT_PB20M_GCLK_IO6    (_UL_(1) << 20)
+#define PIN_PB13M_GCLK_IO7             _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7             _L_(12)
+#define PINMUX_PB13M_GCLK_IO7      ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7    (_UL_(1) << 13)
+#define PIN_PB21M_GCLK_IO7             _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
+#define MUX_PB21M_GCLK_IO7             _L_(12)
+#define PINMUX_PB21M_GCLK_IO7      ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
+#define PORT_PB21M_GCLK_IO7    (_UL_(1) << 21)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PC00A_EIC_EXTINT0          _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PC00A_EIC_EXTINT0   ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PC00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
+#define PIN_PC16A_EIC_EXTINT0          _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PC16A_EIC_EXTINT0   ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PC01A_EIC_EXTINT1          _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PC01A_EIC_EXTINT1   ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PC01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
+#define PIN_PC17A_EIC_EXTINT1          _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PC17A_EIC_EXTINT1   ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PB18A_EIC_EXTINT2          _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB18A_EIC_EXTINT2   ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PB18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
+#define PIN_PC02A_EIC_EXTINT2          _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PC02A_EIC_EXTINT2   ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PC02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
+#define PIN_PC18A_EIC_EXTINT2          _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PC18A_EIC_EXTINT2   ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PB19A_EIC_EXTINT3          _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB19A_EIC_EXTINT3   ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PB19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
+#define PIN_PC03A_EIC_EXTINT3          _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PC03A_EIC_EXTINT3   ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PC03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
+#define PIN_PC19A_EIC_EXTINT3          _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PC19A_EIC_EXTINT3   ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PB20A_EIC_EXTINT4          _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB20A_EIC_EXTINT4   ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PB20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
+#define PIN_PC20A_EIC_EXTINT4          _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PC20A_EIC_EXTINT4   ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
+#define PORT_PC20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PC20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PB21A_EIC_EXTINT5          _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB21A_EIC_EXTINT5   ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PB21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
+#define PIN_PC05A_EIC_EXTINT5          _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PC05A_EIC_EXTINT5   ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PC05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
+#define PIN_PC21A_EIC_EXTINT5          _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PC21A_EIC_EXTINT5   ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
+#define PORT_PC21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PC21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PC06A_EIC_EXTINT6          _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PC06A_EIC_EXTINT6   ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PC06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8          _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8   ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL_(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PB24A_EIC_EXTINT8          _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB24A_EIC_EXTINT8   ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PB24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
+#define PIN_PC24A_EIC_EXTINT8          _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PC24A_EIC_EXTINT8   ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
+#define PORT_PC24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PC24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9          _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9   ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PB25A_EIC_EXTINT9          _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB25A_EIC_EXTINT9   ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PB25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
+#define PIN_PC07A_EIC_EXTINT9          _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PC07A_EIC_EXTINT9   ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
+#define PORT_PC07A_EIC_EXTINT9  (_UL_(1) <<  7)
+#define PIN_PC07A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
+#define PIN_PC25A_EIC_EXTINT9          _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PC25A_EIC_EXTINT9   ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
+#define PORT_PC25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PC25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PC10A_EIC_EXTINT10         _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PC10A_EIC_EXTINT10  ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
+#define PIN_PC26A_EIC_EXTINT10         _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PC26A_EIC_EXTINT10  ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
+#define PORT_PC26A_EIC_EXTINT10  (_UL_(1) << 26)
+#define PIN_PC26A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11         _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11  ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PC11A_EIC_EXTINT11         _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PC11A_EIC_EXTINT11  ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
+#define PIN_PC27A_EIC_EXTINT11         _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PC27A_EIC_EXTINT11  ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
+#define PORT_PC27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PC27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PC12A_EIC_EXTINT12         _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PC12A_EIC_EXTINT12  ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
+#define PIN_PC28A_EIC_EXTINT12         _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PC28A_EIC_EXTINT12  ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
+#define PORT_PC28A_EIC_EXTINT12  (_UL_(1) << 28)
+#define PIN_PC28A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PC13A_EIC_EXTINT13         _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PC13A_EIC_EXTINT13  ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14         _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14  ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PC14A_EIC_EXTINT14         _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PC14A_EIC_EXTINT14  ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15         _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15  ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PC15A_EIC_EXTINT15         _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PC15A_EIC_EXTINT15  ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L_(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
+#define PIN_PC17D_SERCOM0_PAD0         _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
+#define MUX_PC17D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PC17D_SERCOM0_PAD0  ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
+#define PORT_PC17D_SERCOM0_PAD0  (_UL_(1) << 17)
+#define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
+#define PIN_PB24C_SERCOM0_PAD0         _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PB24C_SERCOM0_PAD0  ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0  (_UL_(1) << 24)
+#define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
+#define PIN_PC16D_SERCOM0_PAD1         _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
+#define MUX_PC16D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PC16D_SERCOM0_PAD1  ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
+#define PORT_PC16D_SERCOM0_PAD1  (_UL_(1) << 16)
+#define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
+#define PIN_PB25C_SERCOM0_PAD1         _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PB25C_SERCOM0_PAD1  ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1  (_UL_(1) << 25)
+#define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
+#define PIN_PC18D_SERCOM0_PAD2         _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
+#define MUX_PC18D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PC18D_SERCOM0_PAD2  ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
+#define PORT_PC18D_SERCOM0_PAD2  (_UL_(1) << 18)
+#define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
+#define PIN_PC24C_SERCOM0_PAD2         _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PC24C_SERCOM0_PAD2  ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2  (_UL_(1) << 24)
+#define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
+#define PIN_PC19D_SERCOM0_PAD3         _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
+#define MUX_PC19D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PC19D_SERCOM0_PAD3  ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
+#define PORT_PC19D_SERCOM0_PAD3  (_UL_(1) << 19)
+#define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
+#define PIN_PC25C_SERCOM0_PAD3         _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PC25C_SERCOM0_PAD3  ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
+#define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
+#define PIN_PC27C_SERCOM1_PAD0         _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
+#define MUX_PC27C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PC27C_SERCOM1_PAD0  ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
+#define PORT_PC27C_SERCOM1_PAD0  (_UL_(1) << 27)
+#define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
+#define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
+#define PIN_PC28C_SERCOM1_PAD1         _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
+#define MUX_PC28C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PC28C_SERCOM1_PAD1  ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
+#define PORT_PC28C_SERCOM1_PAD1  (_UL_(1) << 28)
+#define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2         _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2  ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2  (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3         _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3  ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3  (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0               _L_(4)
+#define PINMUX_PA04E_TC0_WO0       ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0     (_UL_(1) <<  4)
+#define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0               _L_(4)
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
+#define PIN_PB30E_TC0_WO0              _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0               _L_(4)
+#define PINMUX_PB30E_TC0_WO0       ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0     (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1               _L_(4)
+#define PINMUX_PA05E_TC0_WO1       ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1     (_UL_(1) <<  5)
+#define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1               _L_(4)
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
+#define PIN_PB31E_TC0_WO1              _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1               _L_(4)
+#define PINMUX_PB31E_TC0_WO1       ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1     (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0               _L_(4)
+#define PINMUX_PA06E_TC1_WO0       ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0     (_UL_(1) <<  6)
+#define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0               _L_(4)
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1               _L_(4)
+#define PINMUX_PA07E_TC1_WO1       ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1     (_UL_(1) <<  7)
+#define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1               _L_(4)
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM               _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM                _L_(7)
+#define PINMUX_PA24H_USB_DM        ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM      (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP               _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP                _L_(7)
+#define PINMUX_PA25H_USB_DP        ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP      (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ         _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ  ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ  (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ         _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ  ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ  (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0          _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0  ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0  (_UL_(1) <<  9)
+#define PIN_PB25D_SERCOM2_PAD0         _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
+#define MUX_PB25D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PB25D_SERCOM2_PAD0  ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
+#define PORT_PB25D_SERCOM2_PAD0  (_UL_(1) << 25)
+#define PIN_PA12C_SERCOM2_PAD0         _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1          _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1  ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1  (_UL_(1) <<  8)
+#define PIN_PB24D_SERCOM2_PAD1         _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
+#define MUX_PB24D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PB24D_SERCOM2_PAD1  ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
+#define PORT_PB24D_SERCOM2_PAD1  (_UL_(1) << 24)
+#define PIN_PA13C_SERCOM2_PAD1         _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
+#define PIN_PC24D_SERCOM2_PAD2         _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PC24D_SERCOM2_PAD2  ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
+#define PORT_PC24D_SERCOM2_PAD2  (_UL_(1) << 24)
+#define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
+#define PIN_PC25D_SERCOM2_PAD3         _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PC25D_SERCOM2_PAD3  ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
+#define PORT_PC25D_SERCOM2_PAD3  (_UL_(1) << 25)
+#define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0         _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0          _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0  ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0  (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
+#define PIN_PB20C_SERCOM3_PAD0         _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PB20C_SERCOM3_PAD0  ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0  (_UL_(1) << 20)
+#define PIN_PA16D_SERCOM3_PAD1         _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1          _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1  ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1  (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
+#define PIN_PB21C_SERCOM3_PAD1         _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PB21C_SERCOM3_PAD1  ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1  (_UL_(1) << 21)
+#define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0             _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0              _L_(6)
+#define PINMUX_PA20G_TCC0_WO0      ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0    (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0             _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0              _L_(6)
+#define PINMUX_PB12G_TCC0_WO0      ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0    (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0              _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0              _L_(5)
+#define PINMUX_PA08F_TCC0_WO0      ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0    (_UL_(1) <<  8)
+#define PIN_PC10F_TCC0_WO0             _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
+#define MUX_PC10F_TCC0_WO0              _L_(5)
+#define PINMUX_PC10F_TCC0_WO0      ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
+#define PORT_PC10F_TCC0_WO0    (_UL_(1) << 10)
+#define PIN_PC16F_TCC0_WO0             _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
+#define MUX_PC16F_TCC0_WO0              _L_(5)
+#define PINMUX_PC16F_TCC0_WO0      ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
+#define PORT_PC16F_TCC0_WO0    (_UL_(1) << 16)
+#define PIN_PA21G_TCC0_WO1             _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1              _L_(6)
+#define PINMUX_PA21G_TCC0_WO1      ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1    (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1             _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1              _L_(6)
+#define PINMUX_PB13G_TCC0_WO1      ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1    (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1              _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1              _L_(5)
+#define PINMUX_PA09F_TCC0_WO1      ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1    (_UL_(1) <<  9)
+#define PIN_PC11F_TCC0_WO1             _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
+#define MUX_PC11F_TCC0_WO1              _L_(5)
+#define PINMUX_PC11F_TCC0_WO1      ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
+#define PORT_PC11F_TCC0_WO1    (_UL_(1) << 11)
+#define PIN_PC17F_TCC0_WO1             _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
+#define MUX_PC17F_TCC0_WO1              _L_(5)
+#define PINMUX_PC17F_TCC0_WO1      ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
+#define PORT_PC17F_TCC0_WO1    (_UL_(1) << 17)
+#define PIN_PA22G_TCC0_WO2             _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2              _L_(6)
+#define PINMUX_PA22G_TCC0_WO2      ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2    (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2             _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2              _L_(6)
+#define PINMUX_PB14G_TCC0_WO2      ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2    (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2             _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L_(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL_(1) << 10)
+#define PIN_PC12F_TCC0_WO2             _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
+#define MUX_PC12F_TCC0_WO2              _L_(5)
+#define PINMUX_PC12F_TCC0_WO2      ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
+#define PORT_PC12F_TCC0_WO2    (_UL_(1) << 12)
+#define PIN_PC18F_TCC0_WO2             _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
+#define MUX_PC18F_TCC0_WO2              _L_(5)
+#define PINMUX_PC18F_TCC0_WO2      ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
+#define PORT_PC18F_TCC0_WO2    (_UL_(1) << 18)
+#define PIN_PA23G_TCC0_WO3             _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3              _L_(6)
+#define PINMUX_PA23G_TCC0_WO3      ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3    (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3             _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3              _L_(6)
+#define PINMUX_PB15G_TCC0_WO3      ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3    (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3             _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L_(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL_(1) << 11)
+#define PIN_PC13F_TCC0_WO3             _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
+#define MUX_PC13F_TCC0_WO3              _L_(5)
+#define PINMUX_PC13F_TCC0_WO3      ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
+#define PORT_PC13F_TCC0_WO3    (_UL_(1) << 13)
+#define PIN_PC19F_TCC0_WO3             _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
+#define MUX_PC19F_TCC0_WO3              _L_(5)
+#define PINMUX_PC19F_TCC0_WO3      ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
+#define PORT_PC19F_TCC0_WO3    (_UL_(1) << 19)
+#define PIN_PA16G_TCC0_WO4             _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4              _L_(6)
+#define PINMUX_PA16G_TCC0_WO4      ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4             _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4              _L_(6)
+#define PINMUX_PB16G_TCC0_WO4      ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4             _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L_(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL_(1) << 10)
+#define PIN_PC14F_TCC0_WO4             _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
+#define MUX_PC14F_TCC0_WO4              _L_(5)
+#define PINMUX_PC14F_TCC0_WO4      ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
+#define PORT_PC14F_TCC0_WO4    (_UL_(1) << 14)
+#define PIN_PC20F_TCC0_WO4             _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
+#define MUX_PC20F_TCC0_WO4              _L_(5)
+#define PINMUX_PC20F_TCC0_WO4      ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
+#define PORT_PC20F_TCC0_WO4    (_UL_(1) << 20)
+#define PIN_PA17G_TCC0_WO5             _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5              _L_(6)
+#define PINMUX_PA17G_TCC0_WO5      ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5             _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5              _L_(6)
+#define PINMUX_PB17G_TCC0_WO5      ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5             _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L_(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL_(1) << 11)
+#define PIN_PC15F_TCC0_WO5             _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
+#define MUX_PC15F_TCC0_WO5              _L_(5)
+#define PINMUX_PC15F_TCC0_WO5      ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
+#define PORT_PC15F_TCC0_WO5    (_UL_(1) << 15)
+#define PIN_PC21F_TCC0_WO5             _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
+#define MUX_PC21F_TCC0_WO5              _L_(5)
+#define PINMUX_PC21F_TCC0_WO5      ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
+#define PORT_PC21F_TCC0_WO5    (_UL_(1) << 21)
+#define PIN_PA18G_TCC0_WO6             _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6              _L_(6)
+#define PINMUX_PA18G_TCC0_WO6      ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6    (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6             _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6              _L_(6)
+#define PINMUX_PB30G_TCC0_WO6      ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6    (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6             _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L_(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7             _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7              _L_(6)
+#define PINMUX_PA19G_TCC0_WO7      ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7    (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7             _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7              _L_(6)
+#define PINMUX_PB31G_TCC0_WO7      ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7    (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7             _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L_(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0             _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0              _L_(6)
+#define PINMUX_PB10G_TCC1_WO0      ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0    (_UL_(1) << 10)
+#define PIN_PC14G_TCC1_WO0             _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
+#define MUX_PC14G_TCC1_WO0              _L_(6)
+#define PINMUX_PC14G_TCC1_WO0      ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
+#define PORT_PC14G_TCC1_WO0    (_UL_(1) << 14)
+#define PIN_PA16F_TCC1_WO0             _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0              _L_(5)
+#define PINMUX_PA16F_TCC1_WO0      ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0    (_UL_(1) << 16)
+#define PIN_PB18F_TCC1_WO0             _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC1_WO0              _L_(5)
+#define PINMUX_PB18F_TCC1_WO0      ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
+#define PORT_PB18F_TCC1_WO0    (_UL_(1) << 18)
+#define PIN_PB11G_TCC1_WO1             _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1              _L_(6)
+#define PINMUX_PB11G_TCC1_WO1      ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1    (_UL_(1) << 11)
+#define PIN_PC15G_TCC1_WO1             _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
+#define MUX_PC15G_TCC1_WO1              _L_(6)
+#define PINMUX_PC15G_TCC1_WO1      ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
+#define PORT_PC15G_TCC1_WO1    (_UL_(1) << 15)
+#define PIN_PA17F_TCC1_WO1             _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1              _L_(5)
+#define PINMUX_PA17F_TCC1_WO1      ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1    (_UL_(1) << 17)
+#define PIN_PB19F_TCC1_WO1             _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC1_WO1              _L_(5)
+#define PINMUX_PB19F_TCC1_WO1      ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
+#define PORT_PB19F_TCC1_WO1    (_UL_(1) << 19)
+#define PIN_PA12G_TCC1_WO2             _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2              _L_(6)
+#define PINMUX_PA12G_TCC1_WO2      ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2    (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2             _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2              _L_(6)
+#define PINMUX_PA14G_TCC1_WO2      ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2    (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2             _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2              _L_(5)
+#define PINMUX_PA18F_TCC1_WO2      ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2    (_UL_(1) << 18)
+#define PIN_PB20F_TCC1_WO2             _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC1_WO2              _L_(5)
+#define PINMUX_PB20F_TCC1_WO2      ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
+#define PORT_PB20F_TCC1_WO2    (_UL_(1) << 20)
+#define PIN_PA13G_TCC1_WO3             _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3              _L_(6)
+#define PINMUX_PA13G_TCC1_WO3      ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3    (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3             _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3              _L_(6)
+#define PINMUX_PA15G_TCC1_WO3      ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3    (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3             _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3              _L_(5)
+#define PINMUX_PA19F_TCC1_WO3      ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3    (_UL_(1) << 19)
+#define PIN_PB21F_TCC1_WO3             _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC1_WO3              _L_(5)
+#define PINMUX_PB21F_TCC1_WO3      ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
+#define PORT_PB21F_TCC1_WO3    (_UL_(1) << 21)
+#define PIN_PA08G_TCC1_WO4              _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4              _L_(6)
+#define PINMUX_PA08G_TCC1_WO4      ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4    (_UL_(1) <<  8)
+#define PIN_PC10G_TCC1_WO4             _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
+#define MUX_PC10G_TCC1_WO4              _L_(6)
+#define PINMUX_PC10G_TCC1_WO4      ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
+#define PORT_PC10G_TCC1_WO4    (_UL_(1) << 10)
+#define PIN_PA20F_TCC1_WO4             _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4              _L_(5)
+#define PINMUX_PA20F_TCC1_WO4      ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4    (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5              _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5              _L_(6)
+#define PINMUX_PA09G_TCC1_WO5      ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5    (_UL_(1) <<  9)
+#define PIN_PC11G_TCC1_WO5             _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
+#define MUX_PC11G_TCC1_WO5              _L_(6)
+#define PINMUX_PC11G_TCC1_WO5      ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
+#define PORT_PC11G_TCC1_WO5    (_UL_(1) << 11)
+#define PIN_PA21F_TCC1_WO5             _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5              _L_(5)
+#define PINMUX_PA21F_TCC1_WO5      ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5    (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6             _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6              _L_(6)
+#define PINMUX_PA10G_TCC1_WO6      ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6    (_UL_(1) << 10)
+#define PIN_PC12G_TCC1_WO6             _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
+#define MUX_PC12G_TCC1_WO6              _L_(6)
+#define PINMUX_PC12G_TCC1_WO6      ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
+#define PORT_PC12G_TCC1_WO6    (_UL_(1) << 12)
+#define PIN_PA22F_TCC1_WO6             _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6              _L_(5)
+#define PINMUX_PA22F_TCC1_WO6      ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6    (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7             _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7              _L_(6)
+#define PINMUX_PA11G_TCC1_WO7      ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7    (_UL_(1) << 11)
+#define PIN_PC13G_TCC1_WO7             _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
+#define MUX_PC13G_TCC1_WO7              _L_(6)
+#define PINMUX_PC13G_TCC1_WO7      ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
+#define PORT_PC13G_TCC1_WO7    (_UL_(1) << 13)
+#define PIN_PA23F_TCC1_WO7             _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7              _L_(5)
+#define PINMUX_PA23F_TCC1_WO7      ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7    (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0              _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0               _L_(4)
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0     (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0               _L_(4)
+#define PINMUX_PA16E_TC2_WO0       ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0     (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0               _L_(4)
+#define PINMUX_PA00E_TC2_WO0       ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0     (_UL_(1) <<  0)
+#define PIN_PA01E_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1               _L_(4)
+#define PINMUX_PA01E_TC2_WO1       ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1     (_UL_(1) <<  1)
+#define PIN_PA13E_TC2_WO1              _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1               _L_(4)
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1     (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1               _L_(4)
+#define PINMUX_PA17E_TC2_WO1       ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L_(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L_(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L_(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L_(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL_(1) << 19)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PC21L_GMAC_GCOL            _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
+#define MUX_PC21L_GMAC_GCOL            _L_(11)
+#define PINMUX_PC21L_GMAC_GCOL     ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
+#define PORT_PC21L_GMAC_GCOL   (_UL_(1) << 21)
+#define PIN_PA16L_GMAC_GCRS            _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS            _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS     ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS   (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC            _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC            _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC     ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC   (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC            _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC            _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC     ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC   (_UL_(1) << 14)
+#define PIN_PC11L_GMAC_GMDC            _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
+#define MUX_PC11L_GMAC_GMDC            _L_(11)
+#define PINMUX_PC11L_GMAC_GMDC     ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
+#define PORT_PC11L_GMAC_GMDC   (_UL_(1) << 11)
+#define PIN_PA21L_GMAC_GMDIO           _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO    ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO  (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO           _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO    ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO  (_UL_(1) << 15)
+#define PIN_PC12L_GMAC_GMDIO           _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
+#define MUX_PC12L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PC12L_GMAC_GMDIO    ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
+#define PORT_PC12L_GMAC_GMDIO  (_UL_(1) << 12)
+#define PIN_PA13L_GMAC_GRX0            _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0            _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0     ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0   (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1            _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1            _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1     ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1   (_UL_(1) << 12)
+#define PIN_PC15L_GMAC_GRX2            _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
+#define MUX_PC15L_GMAC_GRX2            _L_(11)
+#define PINMUX_PC15L_GMAC_GRX2     ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
+#define PORT_PC15L_GMAC_GRX2   (_UL_(1) << 15)
+#define PIN_PC14L_GMAC_GRX3            _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
+#define MUX_PC14L_GMAC_GRX3            _L_(11)
+#define PINMUX_PC14L_GMAC_GRX3     ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
+#define PORT_PC14L_GMAC_GRX3   (_UL_(1) << 14)
+#define PIN_PC18L_GMAC_GRXCK           _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
+#define MUX_PC18L_GMAC_GRXCK           _L_(11)
+#define PINMUX_PC18L_GMAC_GRXCK    ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
+#define PORT_PC18L_GMAC_GRXCK  (_UL_(1) << 18)
+#define PIN_PC20L_GMAC_GRXDV           _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
+#define MUX_PC20L_GMAC_GRXDV           _L_(11)
+#define PINMUX_PC20L_GMAC_GRXDV    ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
+#define PORT_PC20L_GMAC_GRXDV  (_UL_(1) << 20)
+#define PIN_PA15L_GMAC_GRXER           _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER           _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER    ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER  (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0            _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0            _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0     ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0   (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1            _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1            _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1     ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1   (_UL_(1) << 19)
+#define PIN_PC16L_GMAC_GTX2            _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
+#define MUX_PC16L_GMAC_GTX2            _L_(11)
+#define PINMUX_PC16L_GMAC_GTX2     ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
+#define PORT_PC16L_GMAC_GTX2   (_UL_(1) << 16)
+#define PIN_PC17L_GMAC_GTX3            _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
+#define MUX_PC17L_GMAC_GTX3            _L_(11)
+#define PINMUX_PC17L_GMAC_GTX3     ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
+#define PORT_PC17L_GMAC_GTX3   (_UL_(1) << 17)
+#define PIN_PA14L_GMAC_GTXCK           _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK           _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK    ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK  (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN           _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN           _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN    ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN  (_UL_(1) << 17)
+#define PIN_PC19L_GMAC_GTXER           _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
+#define MUX_PC19L_GMAC_GTXER           _L_(11)
+#define PINMUX_PC19L_GMAC_GTXER    ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
+#define PORT_PC19L_GMAC_GTXER  (_UL_(1) << 19)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0             _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0              _L_(5)
+#define PINMUX_PA14F_TCC2_WO0      ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0    (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0             _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0              _L_(5)
+#define PINMUX_PA30F_TCC2_WO0      ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0    (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1             _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1              _L_(5)
+#define PINMUX_PA15F_TCC2_WO1      ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1    (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1             _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1              _L_(5)
+#define PINMUX_PA31F_TCC2_WO1      ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1    (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2             _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2              _L_(5)
+#define PINMUX_PA24F_TCC2_WO2      ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2    (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2             _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2              _L_(5)
+#define PINMUX_PB02F_TCC2_WO2      ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2    (_UL_(1) <<  2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0             _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0              _L_(5)
+#define PINMUX_PB12F_TCC3_WO0      ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0    (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0             _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0              _L_(5)
+#define PINMUX_PB16F_TCC3_WO0      ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0    (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1             _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1              _L_(5)
+#define PINMUX_PB13F_TCC3_WO1      ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1    (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1             _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1              _L_(5)
+#define PINMUX_PB17F_TCC3_WO1      ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1    (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L_(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L_(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL_(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L_(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L_(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L_(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL_(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L_(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L_(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L_(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L_(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L_(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L_(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L_(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB18G_PDEC_QDI0            _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
+#define MUX_PB18G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB18G_PDEC_QDI0     ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
+#define PORT_PB18G_PDEC_QDI0   (_UL_(1) << 18)
+#define PIN_PB23G_PDEC_QDI0            _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0     ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0   (_UL_(1) << 23)
+#define PIN_PC16G_PDEC_QDI0            _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
+#define MUX_PC16G_PDEC_QDI0             _L_(6)
+#define PINMUX_PC16G_PDEC_QDI0     ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
+#define PORT_PC16G_PDEC_QDI0   (_UL_(1) << 16)
+#define PIN_PA24G_PDEC_QDI0            _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0             _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0     ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0   (_UL_(1) << 24)
+#define PIN_PB19G_PDEC_QDI1            _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
+#define MUX_PB19G_PDEC_QDI1             _L_(6)
+#define PINMUX_PB19G_PDEC_QDI1     ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
+#define PORT_PB19G_PDEC_QDI1   (_UL_(1) << 19)
+#define PIN_PB24G_PDEC_QDI1            _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
+#define MUX_PB24G_PDEC_QDI1             _L_(6)
+#define PINMUX_PB24G_PDEC_QDI1     ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
+#define PORT_PB24G_PDEC_QDI1   (_UL_(1) << 24)
+#define PIN_PC17G_PDEC_QDI1            _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
+#define MUX_PC17G_PDEC_QDI1             _L_(6)
+#define PINMUX_PC17G_PDEC_QDI1     ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
+#define PORT_PC17G_PDEC_QDI1   (_UL_(1) << 17)
+#define PIN_PA25G_PDEC_QDI1            _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1             _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1     ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1   (_UL_(1) << 25)
+#define PIN_PB20G_PDEC_QDI2            _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
+#define MUX_PB20G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB20G_PDEC_QDI2     ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
+#define PORT_PB20G_PDEC_QDI2   (_UL_(1) << 20)
+#define PIN_PB25G_PDEC_QDI2            _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
+#define MUX_PB25G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB25G_PDEC_QDI2     ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
+#define PORT_PB25G_PDEC_QDI2   (_UL_(1) << 25)
+#define PIN_PC18G_PDEC_QDI2            _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
+#define MUX_PC18G_PDEC_QDI2             _L_(6)
+#define PINMUX_PC18G_PDEC_QDI2     ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
+#define PORT_PC18G_PDEC_QDI2   (_UL_(1) << 18)
+#define PIN_PB22G_PDEC_QDI2            _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2     ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2   (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L_(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L_(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L_(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L_(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
+#define PIN_PA12M_AC_CMP0              _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0              _L_(12)
+#define PINMUX_PA12M_AC_CMP0       ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0     (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0              _L_(12)
+#define PINMUX_PA18M_AC_CMP0       ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0     (_UL_(1) << 18)
+#define PIN_PB24M_AC_CMP0              _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
+#define MUX_PB24M_AC_CMP0              _L_(12)
+#define PINMUX_PB24M_AC_CMP0       ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
+#define PORT_PB24M_AC_CMP0     (_UL_(1) << 24)
+#define PIN_PA13M_AC_CMP1              _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1              _L_(12)
+#define PINMUX_PA13M_AC_CMP1       ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1     (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1              _L_(12)
+#define PINMUX_PA19M_AC_CMP1       ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1     (_UL_(1) << 19)
+#define PIN_PB25M_AC_CMP1              _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
+#define MUX_PB25M_AC_CMP1              _L_(12)
+#define PINMUX_PB25M_AC_CMP1       ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
+#define PORT_PB25M_AC_CMP1     (_UL_(1) << 25)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS              _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS               _L_(7)
+#define PINMUX_PB11H_QSPI_CS       ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS     (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0            _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0            _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0    ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0  (_UL_(1) <<  8)
+#define PIN_PA09H_QSPI_DATA1            _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1            _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1    ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1  (_UL_(1) <<  9)
+#define PIN_PA10H_QSPI_DATA2           _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2            _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2    ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2  (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3           _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3            _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3    ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3  (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK             _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK              _L_(7)
+#define PINMUX_PB10H_QSPI_SCK      ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK    (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0               _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0              _L_(13)
+#define PINMUX_PA04N_CCL_IN0       ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0     (_UL_(1) <<  4)
+#define PIN_PA16N_CCL_IN0              _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0              _L_(13)
+#define PINMUX_PA16N_CCL_IN0       ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0     (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0              _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0              _L_(13)
+#define PINMUX_PB22N_CCL_IN0       ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0     (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1               _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1              _L_(13)
+#define PINMUX_PA05N_CCL_IN1       ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1     (_UL_(1) <<  5)
+#define PIN_PA17N_CCL_IN1              _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1              _L_(13)
+#define PINMUX_PA17N_CCL_IN1       ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1     (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1              _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1              _L_(13)
+#define PINMUX_PB00N_CCL_IN1       ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1     (_UL_(1) <<  0)
+#define PIN_PA06N_CCL_IN2               _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2              _L_(13)
+#define PINMUX_PA06N_CCL_IN2       ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2     (_UL_(1) <<  6)
+#define PIN_PA18N_CCL_IN2              _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2              _L_(13)
+#define PINMUX_PA18N_CCL_IN2       ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2     (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2              _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2              _L_(13)
+#define PINMUX_PB01N_CCL_IN2       ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2     (_UL_(1) <<  1)
+#define PIN_PA08N_CCL_IN3               _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3              _L_(13)
+#define PINMUX_PA08N_CCL_IN3       ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3     (_UL_(1) <<  8)
+#define PIN_PA30N_CCL_IN3              _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3              _L_(13)
+#define PINMUX_PA30N_CCL_IN3       ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3     (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4               _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4              _L_(13)
+#define PINMUX_PA09N_CCL_IN4       ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4     (_UL_(1) <<  9)
+#define PIN_PC27N_CCL_IN4              _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
+#define MUX_PC27N_CCL_IN4              _L_(13)
+#define PINMUX_PC27N_CCL_IN4       ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
+#define PORT_PC27N_CCL_IN4     (_UL_(1) << 27)
+#define PIN_PA10N_CCL_IN5              _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5              _L_(13)
+#define PINMUX_PA10N_CCL_IN5       ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5     (_UL_(1) << 10)
+#define PIN_PC28N_CCL_IN5              _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
+#define MUX_PC28N_CCL_IN5              _L_(13)
+#define PINMUX_PC28N_CCL_IN5       ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
+#define PORT_PC28N_CCL_IN5     (_UL_(1) << 28)
+#define PIN_PA22N_CCL_IN6              _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6              _L_(13)
+#define PINMUX_PA22N_CCL_IN6       ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6     (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6              _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6              _L_(13)
+#define PINMUX_PB06N_CCL_IN6       ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6     (_UL_(1) <<  6)
+#define PIN_PA23N_CCL_IN7              _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7              _L_(13)
+#define PINMUX_PA23N_CCL_IN7       ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7     (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7              _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7              _L_(13)
+#define PINMUX_PB07N_CCL_IN7       ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7     (_UL_(1) <<  7)
+#define PIN_PA24N_CCL_IN8              _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8              _L_(13)
+#define PINMUX_PA24N_CCL_IN8       ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8     (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8              _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8              _L_(13)
+#define PINMUX_PB08N_CCL_IN8       ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8     (_UL_(1) <<  8)
+#define PIN_PB14N_CCL_IN9              _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9              _L_(13)
+#define PINMUX_PB14N_CCL_IN9       ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9     (_UL_(1) << 14)
+#define PIN_PC20N_CCL_IN9              _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
+#define MUX_PC20N_CCL_IN9              _L_(13)
+#define PINMUX_PC20N_CCL_IN9       ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
+#define PORT_PC20N_CCL_IN9     (_UL_(1) << 20)
+#define PIN_PB15N_CCL_IN10             _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10             _L_(13)
+#define PINMUX_PB15N_CCL_IN10      ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10    (_UL_(1) << 15)
+#define PIN_PC21N_CCL_IN10             _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
+#define MUX_PC21N_CCL_IN10             _L_(13)
+#define PINMUX_PC21N_CCL_IN10      ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
+#define PORT_PC21N_CCL_IN10    (_UL_(1) << 21)
+#define PIN_PB10N_CCL_IN11             _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11             _L_(13)
+#define PINMUX_PB10N_CCL_IN11      ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11    (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11             _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11             _L_(13)
+#define PINMUX_PB16N_CCL_IN11      ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11    (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0              _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0             _L_(13)
+#define PINMUX_PA07N_CCL_OUT0      ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0    (_UL_(1) <<  7)
+#define PIN_PA19N_CCL_OUT0             _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0             _L_(13)
+#define PINMUX_PA19N_CCL_OUT0      ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0    (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0             _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0             _L_(13)
+#define PINMUX_PB02N_CCL_OUT0      ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0    (_UL_(1) <<  2)
+#define PIN_PB23N_CCL_OUT0             _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0             _L_(13)
+#define PINMUX_PB23N_CCL_OUT0      ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0    (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1             _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1             _L_(13)
+#define PINMUX_PA11N_CCL_OUT1      ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1             _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1             _L_(13)
+#define PINMUX_PA31N_CCL_OUT1      ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1    (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1             _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1             _L_(13)
+#define PINMUX_PB11N_CCL_OUT1      ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2             _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2             _L_(13)
+#define PINMUX_PA25N_CCL_OUT2      ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2    (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2             _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2             _L_(13)
+#define PINMUX_PB09N_CCL_OUT2      ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2    (_UL_(1) <<  9)
+#define PIN_PB17N_CCL_OUT3             _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3             _L_(13)
+#define PINMUX_PB17N_CCL_OUT3      ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3    (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0         _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0  ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0  (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0         _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL_(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1         _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1  ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1  (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1         _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL_(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3         _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3         _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3         _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0         _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0  ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0  (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0         _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL_(1) <<  2)
+#define PIN_PB31D_SERCOM5_PAD0         _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0  ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0  (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0         _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1         _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1  ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1  (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1         _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL_(1) <<  3)
+#define PIN_PB30D_SERCOM5_PAD1         _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1  ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1  (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2         _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL_(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL_(1) << 20)
+#define PIN_PB18C_SERCOM5_PAD2         _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PB18C_SERCOM5_PAD2  ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2  (_UL_(1) << 18)
+#define PIN_PA25D_SERCOM5_PAD3         _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL_(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL_(1) << 21)
+#define PIN_PB19C_SERCOM5_PAD3         _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PB19C_SERCOM5_PAD3  ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3  (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM6 peripheral ========== */
+#define PIN_PC13D_SERCOM6_PAD0         _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
+#define MUX_PC13D_SERCOM6_PAD0          _L_(3)
+#define PINMUX_PC13D_SERCOM6_PAD0  ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
+#define PORT_PC13D_SERCOM6_PAD0  (_UL_(1) << 13)
+#define PIN_PC16C_SERCOM6_PAD0         _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
+#define MUX_PC16C_SERCOM6_PAD0          _L_(2)
+#define PINMUX_PC16C_SERCOM6_PAD0  ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
+#define PORT_PC16C_SERCOM6_PAD0  (_UL_(1) << 16)
+#define PIN_PC12D_SERCOM6_PAD1         _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
+#define MUX_PC12D_SERCOM6_PAD1          _L_(3)
+#define PINMUX_PC12D_SERCOM6_PAD1  ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
+#define PORT_PC12D_SERCOM6_PAD1  (_UL_(1) << 12)
+#define PIN_PC05C_SERCOM6_PAD1         _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
+#define MUX_PC05C_SERCOM6_PAD1          _L_(2)
+#define PINMUX_PC05C_SERCOM6_PAD1  ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
+#define PORT_PC05C_SERCOM6_PAD1  (_UL_(1) <<  5)
+#define PIN_PC17C_SERCOM6_PAD1         _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
+#define MUX_PC17C_SERCOM6_PAD1          _L_(2)
+#define PINMUX_PC17C_SERCOM6_PAD1  ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
+#define PORT_PC17C_SERCOM6_PAD1  (_UL_(1) << 17)
+#define PIN_PC14D_SERCOM6_PAD2         _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
+#define MUX_PC14D_SERCOM6_PAD2          _L_(3)
+#define PINMUX_PC14D_SERCOM6_PAD2  ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
+#define PORT_PC14D_SERCOM6_PAD2  (_UL_(1) << 14)
+#define PIN_PC06C_SERCOM6_PAD2         _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
+#define MUX_PC06C_SERCOM6_PAD2          _L_(2)
+#define PINMUX_PC06C_SERCOM6_PAD2  ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
+#define PORT_PC06C_SERCOM6_PAD2  (_UL_(1) <<  6)
+#define PIN_PC10C_SERCOM6_PAD2         _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM6_PAD2          _L_(2)
+#define PINMUX_PC10C_SERCOM6_PAD2  ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
+#define PORT_PC10C_SERCOM6_PAD2  (_UL_(1) << 10)
+#define PIN_PC18C_SERCOM6_PAD2         _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
+#define MUX_PC18C_SERCOM6_PAD2          _L_(2)
+#define PINMUX_PC18C_SERCOM6_PAD2  ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
+#define PORT_PC18C_SERCOM6_PAD2  (_UL_(1) << 18)
+#define PIN_PC15D_SERCOM6_PAD3         _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
+#define MUX_PC15D_SERCOM6_PAD3          _L_(3)
+#define PINMUX_PC15D_SERCOM6_PAD3  ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
+#define PORT_PC15D_SERCOM6_PAD3  (_UL_(1) << 15)
+#define PIN_PC07C_SERCOM6_PAD3         _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
+#define MUX_PC07C_SERCOM6_PAD3          _L_(2)
+#define PINMUX_PC07C_SERCOM6_PAD3  ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
+#define PORT_PC07C_SERCOM6_PAD3  (_UL_(1) <<  7)
+#define PIN_PC11C_SERCOM6_PAD3         _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM6_PAD3          _L_(2)
+#define PINMUX_PC11C_SERCOM6_PAD3  ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
+#define PORT_PC11C_SERCOM6_PAD3  (_UL_(1) << 11)
+#define PIN_PC19C_SERCOM6_PAD3         _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
+#define MUX_PC19C_SERCOM6_PAD3          _L_(2)
+#define PINMUX_PC19C_SERCOM6_PAD3  ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
+#define PORT_PC19C_SERCOM6_PAD3  (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM7 peripheral ========== */
+#define PIN_PB21D_SERCOM7_PAD0         _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
+#define MUX_PB21D_SERCOM7_PAD0          _L_(3)
+#define PINMUX_PB21D_SERCOM7_PAD0  ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
+#define PORT_PB21D_SERCOM7_PAD0  (_UL_(1) << 21)
+#define PIN_PB30C_SERCOM7_PAD0         _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM7_PAD0          _L_(2)
+#define PINMUX_PB30C_SERCOM7_PAD0  ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
+#define PORT_PB30C_SERCOM7_PAD0  (_UL_(1) << 30)
+#define PIN_PC12C_SERCOM7_PAD0         _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM7_PAD0          _L_(2)
+#define PINMUX_PC12C_SERCOM7_PAD0  ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
+#define PORT_PC12C_SERCOM7_PAD0  (_UL_(1) << 12)
+#define PIN_PB20D_SERCOM7_PAD1         _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
+#define MUX_PB20D_SERCOM7_PAD1          _L_(3)
+#define PINMUX_PB20D_SERCOM7_PAD1  ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
+#define PORT_PB20D_SERCOM7_PAD1  (_UL_(1) << 20)
+#define PIN_PB31C_SERCOM7_PAD1         _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM7_PAD1          _L_(2)
+#define PINMUX_PB31C_SERCOM7_PAD1  ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
+#define PORT_PB31C_SERCOM7_PAD1  (_UL_(1) << 31)
+#define PIN_PC13C_SERCOM7_PAD1         _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM7_PAD1          _L_(2)
+#define PINMUX_PC13C_SERCOM7_PAD1  ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
+#define PORT_PC13C_SERCOM7_PAD1  (_UL_(1) << 13)
+#define PIN_PB18D_SERCOM7_PAD2         _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM7_PAD2          _L_(3)
+#define PINMUX_PB18D_SERCOM7_PAD2  ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
+#define PORT_PB18D_SERCOM7_PAD2  (_UL_(1) << 18)
+#define PIN_PC10D_SERCOM7_PAD2         _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
+#define MUX_PC10D_SERCOM7_PAD2          _L_(3)
+#define PINMUX_PC10D_SERCOM7_PAD2  ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
+#define PORT_PC10D_SERCOM7_PAD2  (_UL_(1) << 10)
+#define PIN_PC14C_SERCOM7_PAD2         _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
+#define MUX_PC14C_SERCOM7_PAD2          _L_(2)
+#define PINMUX_PC14C_SERCOM7_PAD2  ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
+#define PORT_PC14C_SERCOM7_PAD2  (_UL_(1) << 14)
+#define PIN_PA30C_SERCOM7_PAD2         _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
+#define MUX_PA30C_SERCOM7_PAD2          _L_(2)
+#define PINMUX_PA30C_SERCOM7_PAD2  ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
+#define PORT_PA30C_SERCOM7_PAD2  (_UL_(1) << 30)
+#define PIN_PB19D_SERCOM7_PAD3         _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM7_PAD3          _L_(3)
+#define PINMUX_PB19D_SERCOM7_PAD3  ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
+#define PORT_PB19D_SERCOM7_PAD3  (_UL_(1) << 19)
+#define PIN_PC11D_SERCOM7_PAD3         _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
+#define MUX_PC11D_SERCOM7_PAD3          _L_(3)
+#define PINMUX_PC11D_SERCOM7_PAD3  ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
+#define PORT_PC11D_SERCOM7_PAD3  (_UL_(1) << 11)
+#define PIN_PC15C_SERCOM7_PAD3         _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
+#define MUX_PC15C_SERCOM7_PAD3          _L_(2)
+#define PINMUX_PC15C_SERCOM7_PAD3  ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
+#define PORT_PC15C_SERCOM7_PAD3  (_UL_(1) << 15)
+#define PIN_PA31C_SERCOM7_PAD3         _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
+#define MUX_PA31C_SERCOM7_PAD3          _L_(2)
+#define PINMUX_PA31C_SERCOM7_PAD3  ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
+#define PORT_PA31C_SERCOM7_PAD3  (_UL_(1) << 31)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0             _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0              _L_(5)
+#define PINMUX_PB14F_TCC4_WO0      ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0    (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0             _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0              _L_(5)
+#define PINMUX_PB30F_TCC4_WO0      ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0    (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1             _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1              _L_(5)
+#define PINMUX_PB15F_TCC4_WO1      ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1    (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1             _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1              _L_(5)
+#define PINMUX_PB31F_TCC4_WO1      ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1    (_UL_(1) << 31)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PA30E_TC6_WO0              _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TC6_WO0               _L_(4)
+#define PINMUX_PA30E_TC6_WO0       ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
+#define PORT_PA30E_TC6_WO0     (_UL_(1) << 30)
+#define PIN_PB02E_TC6_WO0              _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L_(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL_(1) <<  2)
+#define PIN_PB16E_TC6_WO0              _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0               _L_(4)
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0     (_UL_(1) << 16)
+#define PIN_PA31E_TC6_WO1              _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TC6_WO1               _L_(4)
+#define PINMUX_PA31E_TC6_WO1       ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
+#define PORT_PA31E_TC6_WO1     (_UL_(1) << 31)
+#define PIN_PB03E_TC6_WO1              _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L_(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL_(1) <<  3)
+#define PIN_PB17E_TC6_WO1              _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1               _L_(4)
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L_(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL_(1) << 20)
+#define PIN_PB00E_TC7_WO0              _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0               _L_(4)
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0     (_UL_(1) <<  0)
+#define PIN_PB22E_TC7_WO0              _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0               _L_(4)
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0     (_UL_(1) << 22)
+#define PIN_PA21E_TC7_WO1              _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L_(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL_(1) << 21)
+#define PIN_PB01E_TC7_WO1              _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1               _L_(4)
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1     (_UL_(1) <<  1)
+#define PIN_PB23E_TC7_WO1              _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1               _L_(4)
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1     (_UL_(1) << 23)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0             _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0             _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0     ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0   (_UL_(1) <<  2)
+#define PIN_PA03B_ADC0_AIN1             _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1             _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1     ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1   (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_AIN2            _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2             _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2     ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_AIN3            _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3             _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3     ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3   (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_AIN4             _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4             _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4     ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4   (_UL_(1) <<  4)
+#define PIN_PA05B_ADC0_AIN5             _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5             _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5     ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5   (_UL_(1) <<  5)
+#define PIN_PA06B_ADC0_AIN6             _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6             _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6     ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6   (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_AIN7             _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7             _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7     ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7   (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_AIN8             _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8             _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8     ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_AIN9             _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9             _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9     ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9   (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_AIN10           _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10            _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10    ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11           _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11            _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11    ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11  (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12           _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12            _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12    ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_AIN13           _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13            _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13    ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13  (_UL_(1) <<  1)
+#define PIN_PB02B_ADC0_AIN14           _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14            _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14    ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_AIN15           _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15            _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15    ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15  (_UL_(1) <<  3)
+#define PIN_PA03O_ADC0_DRV0             _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0            _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0     ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0   (_UL_(1) <<  3)
+#define PIN_PB08O_ADC0_DRV1            _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1            _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1     ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1   (_UL_(1) <<  8)
+#define PIN_PB09O_ADC0_DRV2            _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2            _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2     ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2   (_UL_(1) <<  9)
+#define PIN_PA04O_ADC0_DRV3             _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3            _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3     ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3   (_UL_(1) <<  4)
+#define PIN_PA06O_ADC0_DRV4             _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4            _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4     ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4   (_UL_(1) <<  6)
+#define PIN_PA07O_ADC0_DRV5             _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5            _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5     ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5   (_UL_(1) <<  7)
+#define PIN_PA08O_ADC0_DRV6             _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6            _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6     ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6   (_UL_(1) <<  8)
+#define PIN_PA09O_ADC0_DRV7             _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7            _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7     ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7   (_UL_(1) <<  9)
+#define PIN_PA10O_ADC0_DRV8            _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8            _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8     ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8   (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9            _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9            _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9     ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9   (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10           _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10           _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10    ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10  (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11           _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11           _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11    ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11  (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12           _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12           _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12    ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12  (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13           _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13           _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13    ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13  (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14           _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14           _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14    ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14  (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15           _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15           _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15    ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15  (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16           _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16           _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16    ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16  (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17           _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17           _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17    ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17  (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18           _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18           _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18    ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18  (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19           _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19           _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19    ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19  (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20           _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20           _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20    ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20  (_UL_(1) <<  2)
+#define PIN_PB03O_ADC0_DRV21           _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21           _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21    ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21  (_UL_(1) <<  3)
+#define PIN_PB04O_ADC0_DRV22           _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22           _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22    ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22  (_UL_(1) <<  4)
+#define PIN_PB05O_ADC0_DRV23           _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23           _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23    ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23  (_UL_(1) <<  5)
+#define PIN_PB06O_ADC0_DRV24           _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24           _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24    ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24  (_UL_(1) <<  6)
+#define PIN_PB07O_ADC0_DRV25           _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25           _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25    ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25  (_UL_(1) <<  7)
+#define PIN_PB12O_ADC0_DRV26           _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26           _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26    ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26  (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27           _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27           _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27    ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27  (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28           _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28           _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28    ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28  (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29           _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29           _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29    ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29  (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30           _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30           _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30    ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30  (_UL_(1) <<  0)
+#define PIN_PB01O_ADC0_DRV31           _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31           _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31    ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31  (_UL_(1) <<  1)
+#define PIN_PA03B_ADC0_PTCXY0           _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0           _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0   ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0  (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_PTCXY1          _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1           _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1   ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1  (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_PTCXY2          _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2           _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2   ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2  (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_PTCXY3           _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3           _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3   ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3  (_UL_(1) <<  4)
+#define PIN_PA06B_ADC0_PTCXY4           _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4           _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4   ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4  (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_PTCXY5           _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5           _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5   ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5  (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_PTCXY6           _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6           _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6   ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6  (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_PTCXY7           _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7           _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7   ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7  (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_PTCXY8          _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8           _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8   ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9          _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9           _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9   ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9  (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10         _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10          _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10  ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10  (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11         _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11          _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11  ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11  (_UL_(1) << 17)
+#define PIN_PA18B_ADC0_PTCXY12         _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */
+#define MUX_PA18B_ADC0_PTCXY12          _L_(1)
+#define PINMUX_PA18B_ADC0_PTCXY12  ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
+#define PORT_PA18B_ADC0_PTCXY12  (_UL_(1) << 18)
+#define PIN_PA19B_ADC0_PTCXY13         _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13          _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13  ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13  (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14         _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14          _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14  ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14  (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15         _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15          _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15  ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15  (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16         _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16          _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16  ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16  (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17         _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17          _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17  ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17  (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18         _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18          _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18  ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18  (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19         _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19          _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19  ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19  (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20         _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20          _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20  ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_PTCXY21         _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21          _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21  ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21  (_UL_(1) <<  3)
+#define PIN_PB04B_ADC0_PTCXY22         _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22          _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22  ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22  (_UL_(1) <<  4)
+#define PIN_PB05B_ADC0_PTCXY23         _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23          _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23  ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23  (_UL_(1) <<  5)
+#define PIN_PB06B_ADC0_PTCXY24         _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24          _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24  ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24  (_UL_(1) <<  6)
+#define PIN_PB07B_ADC0_PTCXY25         _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25          _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25  ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25  (_UL_(1) <<  7)
+#define PIN_PB12B_ADC0_PTCXY26         _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26          _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26  ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26  (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27         _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27          _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27  ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27  (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28         _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28          _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28  ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28  (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29         _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29          _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29  ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29  (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30         _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30          _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30  ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_PTCXY31         _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31          _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31  ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31  (_UL_(1) <<  1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0            _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0             _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0     ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC1_AIN1            _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1             _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1     ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1   (_UL_(1) <<  9)
+#define PIN_PA08B_ADC1_AIN2             _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2             _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2     ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC1_AIN3             _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3             _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3     ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3   (_UL_(1) <<  9)
+#define PIN_PC02B_ADC1_AIN4            _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
+#define MUX_PC02B_ADC1_AIN4             _L_(1)
+#define PINMUX_PC02B_ADC1_AIN4     ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
+#define PORT_PC02B_ADC1_AIN4   (_UL_(1) <<  2)
+#define PIN_PC03B_ADC1_AIN5            _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
+#define MUX_PC03B_ADC1_AIN5             _L_(1)
+#define PINMUX_PC03B_ADC1_AIN5     ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
+#define PORT_PC03B_ADC1_AIN5   (_UL_(1) <<  3)
+#define PIN_PB04B_ADC1_AIN6            _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6             _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6     ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6   (_UL_(1) <<  4)
+#define PIN_PB05B_ADC1_AIN7            _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7             _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7     ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7   (_UL_(1) <<  5)
+#define PIN_PB06B_ADC1_AIN8            _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8             _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8     ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8   (_UL_(1) <<  6)
+#define PIN_PB07B_ADC1_AIN9            _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9             _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9     ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9   (_UL_(1) <<  7)
+#define PIN_PC00B_ADC1_AIN10           _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
+#define MUX_PC00B_ADC1_AIN10            _L_(1)
+#define PINMUX_PC00B_ADC1_AIN10    ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
+#define PORT_PC00B_ADC1_AIN10  (_UL_(1) <<  0)
+#define PIN_PC01B_ADC1_AIN11           _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
+#define MUX_PC01B_ADC1_AIN11            _L_(1)
+#define PINMUX_PC01B_ADC1_AIN11    ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
+#define PORT_PC01B_ADC1_AIN11  (_UL_(1) <<  1)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0             _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0             _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0   (_UL_(1) <<  2)
+#define PIN_PA05B_DAC_VOUT1             _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1             _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1   (_UL_(1) <<  5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0               _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0               _L_(9)
+#define PINMUX_PA09J_I2S_FS0       ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0     (_UL_(1) <<  9)
+#define PIN_PA20J_I2S_FS0              _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0               _L_(9)
+#define PINMUX_PA20J_I2S_FS0       ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0     (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1              _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1               _L_(9)
+#define PINMUX_PA23J_I2S_FS1       ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1     (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1              _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1               _L_(9)
+#define PINMUX_PB11J_I2S_FS1       ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1     (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0              _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0              _L_(9)
+#define PINMUX_PA08J_I2S_MCK0      ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0    (_UL_(1) <<  8)
+#define PIN_PB17J_I2S_MCK0             _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0              _L_(9)
+#define PINMUX_PB17J_I2S_MCK0      ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0    (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1             _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1              _L_(9)
+#define PINMUX_PB13J_I2S_MCK1      ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1    (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0             _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0              _L_(9)
+#define PINMUX_PA10J_I2S_SCK0      ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0    (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0             _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0              _L_(9)
+#define PINMUX_PB16J_I2S_SCK0      ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0    (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1             _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1              _L_(9)
+#define PINMUX_PB12J_I2S_SCK1      ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1    (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI              _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI               _L_(9)
+#define PINMUX_PA22J_I2S_SDI       ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI     (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI              _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI               _L_(9)
+#define PINMUX_PB10J_I2S_SDI       ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI     (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO              _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO               _L_(9)
+#define PINMUX_PA11J_I2S_SDO       ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO     (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO              _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO               _L_(9)
+#define PINMUX_PA21J_I2S_SDO       ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO     (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK              _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK              _L_(10)
+#define PINMUX_PA14K_PCC_CLK       ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK     (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0            _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0            _L_(10)
+#define PINMUX_PA16K_PCC_DATA0     ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0   (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1            _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1            _L_(10)
+#define PINMUX_PA17K_PCC_DATA1     ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1   (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2            _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2            _L_(10)
+#define PINMUX_PA18K_PCC_DATA2     ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2   (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3            _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3            _L_(10)
+#define PINMUX_PA19K_PCC_DATA3     ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3   (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4            _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4            _L_(10)
+#define PINMUX_PA20K_PCC_DATA4     ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4   (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5            _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5            _L_(10)
+#define PINMUX_PA21K_PCC_DATA5     ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5   (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6            _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6            _L_(10)
+#define PINMUX_PA22K_PCC_DATA6     ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6   (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7            _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7            _L_(10)
+#define PINMUX_PA23K_PCC_DATA7     ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7   (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8            _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8            _L_(10)
+#define PINMUX_PB14K_PCC_DATA8     ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8   (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9            _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9            _L_(10)
+#define PINMUX_PB15K_PCC_DATA9     ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9   (_UL_(1) << 15)
+#define PIN_PC12K_PCC_DATA10           _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
+#define MUX_PC12K_PCC_DATA10           _L_(10)
+#define PINMUX_PC12K_PCC_DATA10    ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
+#define PORT_PC12K_PCC_DATA10  (_UL_(1) << 12)
+#define PIN_PC13K_PCC_DATA11           _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
+#define MUX_PC13K_PCC_DATA11           _L_(10)
+#define PINMUX_PC13K_PCC_DATA11    ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
+#define PORT_PC13K_PCC_DATA11  (_UL_(1) << 13)
+#define PIN_PC14K_PCC_DATA12           _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
+#define MUX_PC14K_PCC_DATA12           _L_(10)
+#define PINMUX_PC14K_PCC_DATA12    ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
+#define PORT_PC14K_PCC_DATA12  (_UL_(1) << 14)
+#define PIN_PC15K_PCC_DATA13           _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
+#define MUX_PC15K_PCC_DATA13           _L_(10)
+#define PINMUX_PC15K_PCC_DATA13    ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
+#define PORT_PC15K_PCC_DATA13  (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1             _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1             _L_(10)
+#define PINMUX_PA12K_PCC_DEN1      ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1    (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2             _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2             _L_(10)
+#define PINMUX_PA13K_PCC_DEN2      ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2    (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD            _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD    ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PA12I_SDHC0_SDCD           _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD    ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD           _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD    ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PC06I_SDHC0_SDCD           _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
+#define MUX_PC06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PC06I_SDHC0_SDCD    ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
+#define PORT_PC06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PB11I_SDHC0_SDCK           _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK            _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK    ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK  (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD           _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD           _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD   ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD  (_UL_(1) <<  8)
+#define PIN_PA09I_SDHC0_SDDAT0          _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0          _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0  ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0  (_UL_(1) <<  9)
+#define PIN_PA10I_SDHC0_SDDAT1         _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1          _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1  ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1  (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2         _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2          _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2  ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2  (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3         _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3          _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3  ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3  (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP            _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP    ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP  (_UL_(1) <<  7)
+#define PIN_PA13I_SDHC0_SDWP           _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP    ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP           _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP    ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PC07I_SDHC0_SDWP           _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
+#define MUX_PC07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PC07I_SDHC0_SDWP    ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
+#define PORT_PC07I_SDHC0_SDWP  (_UL_(1) <<  7)
+/* ========== PORT definition for SDHC1 peripheral ========== */
+#define PIN_PB16I_SDHC1_SDCD           _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
+#define MUX_PB16I_SDHC1_SDCD            _L_(8)
+#define PINMUX_PB16I_SDHC1_SDCD    ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
+#define PORT_PB16I_SDHC1_SDCD  (_UL_(1) << 16)
+#define PIN_PC20I_SDHC1_SDCD           _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
+#define MUX_PC20I_SDHC1_SDCD            _L_(8)
+#define PINMUX_PC20I_SDHC1_SDCD    ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
+#define PORT_PC20I_SDHC1_SDCD  (_UL_(1) << 20)
+#define PIN_PA21I_SDHC1_SDCK           _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
+#define MUX_PA21I_SDHC1_SDCK            _L_(8)
+#define PINMUX_PA21I_SDHC1_SDCK    ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
+#define PORT_PA21I_SDHC1_SDCK  (_UL_(1) << 21)
+#define PIN_PA20I_SDHC1_SDCMD          _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
+#define MUX_PA20I_SDHC1_SDCMD           _L_(8)
+#define PINMUX_PA20I_SDHC1_SDCMD   ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
+#define PORT_PA20I_SDHC1_SDCMD  (_UL_(1) << 20)
+#define PIN_PB18I_SDHC1_SDDAT0         _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
+#define MUX_PB18I_SDHC1_SDDAT0          _L_(8)
+#define PINMUX_PB18I_SDHC1_SDDAT0  ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
+#define PORT_PB18I_SDHC1_SDDAT0  (_UL_(1) << 18)
+#define PIN_PB19I_SDHC1_SDDAT1         _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
+#define MUX_PB19I_SDHC1_SDDAT1          _L_(8)
+#define PINMUX_PB19I_SDHC1_SDDAT1  ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
+#define PORT_PB19I_SDHC1_SDDAT1  (_UL_(1) << 19)
+#define PIN_PB20I_SDHC1_SDDAT2         _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
+#define MUX_PB20I_SDHC1_SDDAT2          _L_(8)
+#define PINMUX_PB20I_SDHC1_SDDAT2  ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
+#define PORT_PB20I_SDHC1_SDDAT2  (_UL_(1) << 20)
+#define PIN_PB21I_SDHC1_SDDAT3         _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
+#define MUX_PB21I_SDHC1_SDDAT3          _L_(8)
+#define PINMUX_PB21I_SDHC1_SDDAT3  ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
+#define PORT_PB21I_SDHC1_SDDAT3  (_UL_(1) << 21)
+#define PIN_PB17I_SDHC1_SDWP           _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
+#define MUX_PB17I_SDHC1_SDWP            _L_(8)
+#define PINMUX_PB17I_SDHC1_SDWP    ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
+#define PORT_PB17I_SDHC1_SDWP  (_UL_(1) << 17)
+#define PIN_PC21I_SDHC1_SDWP           _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
+#define MUX_PC21I_SDHC1_SDWP            _L_(8)
+#define PINMUX_PC21I_SDHC1_SDWP    ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
+#define PORT_PC21I_SDHC1_SDWP  (_UL_(1) << 21)
+
+#endif /* _SAME53N19A_PIO_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53n20a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53n20a.h
new file mode 100644
index 000000000..a784e1fad
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/pio/same53n20a.h	
@@ -0,0 +1,2654 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAME53N20A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53N20A_PIO_
+#define _SAME53N20A_PIO_
+
+#define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
+#define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
+#define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
+#define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
+#define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
+#define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
+#define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
+#define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
+#define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
+#define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
+#define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
+#define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
+#define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
+#define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
+#define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
+#define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
+#define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
+#define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
+#define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
+#define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
+#define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
+#define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
+#define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
+#define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
+#define PIN_PA12                           12  /**< \brief Pin Number for PA12 */
+#define PORT_PA12              (_UL_(1) << 12) /**< \brief PORT Mask  for PA12 */
+#define PIN_PA13                           13  /**< \brief Pin Number for PA13 */
+#define PORT_PA13              (_UL_(1) << 13) /**< \brief PORT Mask  for PA13 */
+#define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
+#define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
+#define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
+#define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
+#define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
+#define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
+#define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
+#define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
+#define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
+#define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
+#define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
+#define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
+#define PIN_PA20                           20  /**< \brief Pin Number for PA20 */
+#define PORT_PA20              (_UL_(1) << 20) /**< \brief PORT Mask  for PA20 */
+#define PIN_PA21                           21  /**< \brief Pin Number for PA21 */
+#define PORT_PA21              (_UL_(1) << 21) /**< \brief PORT Mask  for PA21 */
+#define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
+#define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
+#define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
+#define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
+#define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
+#define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
+#define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
+#define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
+#define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
+#define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
+#define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
+#define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
+#define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
+#define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
+#define PIN_PB00                           32  /**< \brief Pin Number for PB00 */
+#define PORT_PB00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PB00 */
+#define PIN_PB01                           33  /**< \brief Pin Number for PB01 */
+#define PORT_PB01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PB01 */
+#define PIN_PB02                           34  /**< \brief Pin Number for PB02 */
+#define PORT_PB02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PB02 */
+#define PIN_PB03                           35  /**< \brief Pin Number for PB03 */
+#define PORT_PB03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PB03 */
+#define PIN_PB04                           36  /**< \brief Pin Number for PB04 */
+#define PORT_PB04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PB04 */
+#define PIN_PB05                           37  /**< \brief Pin Number for PB05 */
+#define PORT_PB05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PB05 */
+#define PIN_PB06                           38  /**< \brief Pin Number for PB06 */
+#define PORT_PB06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PB06 */
+#define PIN_PB07                           39  /**< \brief Pin Number for PB07 */
+#define PORT_PB07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PB07 */
+#define PIN_PB08                           40  /**< \brief Pin Number for PB08 */
+#define PORT_PB08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PB08 */
+#define PIN_PB09                           41  /**< \brief Pin Number for PB09 */
+#define PORT_PB09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PB09 */
+#define PIN_PB10                           42  /**< \brief Pin Number for PB10 */
+#define PORT_PB10              (_UL_(1) << 10) /**< \brief PORT Mask  for PB10 */
+#define PIN_PB11                           43  /**< \brief Pin Number for PB11 */
+#define PORT_PB11              (_UL_(1) << 11) /**< \brief PORT Mask  for PB11 */
+#define PIN_PB12                           44  /**< \brief Pin Number for PB12 */
+#define PORT_PB12              (_UL_(1) << 12) /**< \brief PORT Mask  for PB12 */
+#define PIN_PB13                           45  /**< \brief Pin Number for PB13 */
+#define PORT_PB13              (_UL_(1) << 13) /**< \brief PORT Mask  for PB13 */
+#define PIN_PB14                           46  /**< \brief Pin Number for PB14 */
+#define PORT_PB14              (_UL_(1) << 14) /**< \brief PORT Mask  for PB14 */
+#define PIN_PB15                           47  /**< \brief Pin Number for PB15 */
+#define PORT_PB15              (_UL_(1) << 15) /**< \brief PORT Mask  for PB15 */
+#define PIN_PB16                           48  /**< \brief Pin Number for PB16 */
+#define PORT_PB16              (_UL_(1) << 16) /**< \brief PORT Mask  for PB16 */
+#define PIN_PB17                           49  /**< \brief Pin Number for PB17 */
+#define PORT_PB17              (_UL_(1) << 17) /**< \brief PORT Mask  for PB17 */
+#define PIN_PB18                           50  /**< \brief Pin Number for PB18 */
+#define PORT_PB18              (_UL_(1) << 18) /**< \brief PORT Mask  for PB18 */
+#define PIN_PB19                           51  /**< \brief Pin Number for PB19 */
+#define PORT_PB19              (_UL_(1) << 19) /**< \brief PORT Mask  for PB19 */
+#define PIN_PB20                           52  /**< \brief Pin Number for PB20 */
+#define PORT_PB20              (_UL_(1) << 20) /**< \brief PORT Mask  for PB20 */
+#define PIN_PB21                           53  /**< \brief Pin Number for PB21 */
+#define PORT_PB21              (_UL_(1) << 21) /**< \brief PORT Mask  for PB21 */
+#define PIN_PB22                           54  /**< \brief Pin Number for PB22 */
+#define PORT_PB22              (_UL_(1) << 22) /**< \brief PORT Mask  for PB22 */
+#define PIN_PB23                           55  /**< \brief Pin Number for PB23 */
+#define PORT_PB23              (_UL_(1) << 23) /**< \brief PORT Mask  for PB23 */
+#define PIN_PB24                           56  /**< \brief Pin Number for PB24 */
+#define PORT_PB24              (_UL_(1) << 24) /**< \brief PORT Mask  for PB24 */
+#define PIN_PB25                           57  /**< \brief Pin Number for PB25 */
+#define PORT_PB25              (_UL_(1) << 25) /**< \brief PORT Mask  for PB25 */
+#define PIN_PB30                           62  /**< \brief Pin Number for PB30 */
+#define PORT_PB30              (_UL_(1) << 30) /**< \brief PORT Mask  for PB30 */
+#define PIN_PB31                           63  /**< \brief Pin Number for PB31 */
+#define PORT_PB31              (_UL_(1) << 31) /**< \brief PORT Mask  for PB31 */
+#define PIN_PC00                           64  /**< \brief Pin Number for PC00 */
+#define PORT_PC00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PC00 */
+#define PIN_PC01                           65  /**< \brief Pin Number for PC01 */
+#define PORT_PC01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PC01 */
+#define PIN_PC02                           66  /**< \brief Pin Number for PC02 */
+#define PORT_PC02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PC02 */
+#define PIN_PC03                           67  /**< \brief Pin Number for PC03 */
+#define PORT_PC03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PC03 */
+#define PIN_PC05                           69  /**< \brief Pin Number for PC05 */
+#define PORT_PC05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PC05 */
+#define PIN_PC06                           70  /**< \brief Pin Number for PC06 */
+#define PORT_PC06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PC06 */
+#define PIN_PC07                           71  /**< \brief Pin Number for PC07 */
+#define PORT_PC07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PC07 */
+#define PIN_PC10                           74  /**< \brief Pin Number for PC10 */
+#define PORT_PC10              (_UL_(1) << 10) /**< \brief PORT Mask  for PC10 */
+#define PIN_PC11                           75  /**< \brief Pin Number for PC11 */
+#define PORT_PC11              (_UL_(1) << 11) /**< \brief PORT Mask  for PC11 */
+#define PIN_PC12                           76  /**< \brief Pin Number for PC12 */
+#define PORT_PC12              (_UL_(1) << 12) /**< \brief PORT Mask  for PC12 */
+#define PIN_PC13                           77  /**< \brief Pin Number for PC13 */
+#define PORT_PC13              (_UL_(1) << 13) /**< \brief PORT Mask  for PC13 */
+#define PIN_PC14                           78  /**< \brief Pin Number for PC14 */
+#define PORT_PC14              (_UL_(1) << 14) /**< \brief PORT Mask  for PC14 */
+#define PIN_PC15                           79  /**< \brief Pin Number for PC15 */
+#define PORT_PC15              (_UL_(1) << 15) /**< \brief PORT Mask  for PC15 */
+#define PIN_PC16                           80  /**< \brief Pin Number for PC16 */
+#define PORT_PC16              (_UL_(1) << 16) /**< \brief PORT Mask  for PC16 */
+#define PIN_PC17                           81  /**< \brief Pin Number for PC17 */
+#define PORT_PC17              (_UL_(1) << 17) /**< \brief PORT Mask  for PC17 */
+#define PIN_PC18                           82  /**< \brief Pin Number for PC18 */
+#define PORT_PC18              (_UL_(1) << 18) /**< \brief PORT Mask  for PC18 */
+#define PIN_PC19                           83  /**< \brief Pin Number for PC19 */
+#define PORT_PC19              (_UL_(1) << 19) /**< \brief PORT Mask  for PC19 */
+#define PIN_PC20                           84  /**< \brief Pin Number for PC20 */
+#define PORT_PC20              (_UL_(1) << 20) /**< \brief PORT Mask  for PC20 */
+#define PIN_PC21                           85  /**< \brief Pin Number for PC21 */
+#define PORT_PC21              (_UL_(1) << 21) /**< \brief PORT Mask  for PC21 */
+#define PIN_PC24                           88  /**< \brief Pin Number for PC24 */
+#define PORT_PC24              (_UL_(1) << 24) /**< \brief PORT Mask  for PC24 */
+#define PIN_PC25                           89  /**< \brief Pin Number for PC25 */
+#define PORT_PC25              (_UL_(1) << 25) /**< \brief PORT Mask  for PC25 */
+#define PIN_PC26                           90  /**< \brief Pin Number for PC26 */
+#define PORT_PC26              (_UL_(1) << 26) /**< \brief PORT Mask  for PC26 */
+#define PIN_PC27                           91  /**< \brief Pin Number for PC27 */
+#define PORT_PC27              (_UL_(1) << 27) /**< \brief PORT Mask  for PC27 */
+#define PIN_PC28                           92  /**< \brief Pin Number for PC28 */
+#define PORT_PC28              (_UL_(1) << 28) /**< \brief PORT Mask  for PC28 */
+/* ========== PORT definition for CM4 peripheral ========== */
+#define PIN_PA30H_CM4_SWCLK            _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
+#define MUX_PA30H_CM4_SWCLK             _L_(7)
+#define PINMUX_PA30H_CM4_SWCLK     ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
+#define PORT_PA30H_CM4_SWCLK   (_UL_(1) << 30)
+#define PIN_PC27M_CM4_SWO              _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
+#define MUX_PC27M_CM4_SWO              _L_(12)
+#define PINMUX_PC27M_CM4_SWO       ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
+#define PORT_PC27M_CM4_SWO     (_UL_(1) << 27)
+#define PIN_PB30H_CM4_SWO              _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
+#define MUX_PB30H_CM4_SWO               _L_(7)
+#define PINMUX_PB30H_CM4_SWO       ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
+#define PORT_PB30H_CM4_SWO     (_UL_(1) << 30)
+#define PIN_PC27H_CM4_TRACECLK         _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
+#define MUX_PC27H_CM4_TRACECLK          _L_(7)
+#define PINMUX_PC27H_CM4_TRACECLK  ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
+#define PORT_PC27H_CM4_TRACECLK  (_UL_(1) << 27)
+#define PIN_PC28H_CM4_TRACEDATA0       _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
+#define MUX_PC28H_CM4_TRACEDATA0        _L_(7)
+#define PINMUX_PC28H_CM4_TRACEDATA0  ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
+#define PORT_PC28H_CM4_TRACEDATA0  (_UL_(1) << 28)
+#define PIN_PC26H_CM4_TRACEDATA1       _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
+#define MUX_PC26H_CM4_TRACEDATA1        _L_(7)
+#define PINMUX_PC26H_CM4_TRACEDATA1  ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
+#define PORT_PC26H_CM4_TRACEDATA1  (_UL_(1) << 26)
+#define PIN_PC25H_CM4_TRACEDATA2       _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
+#define MUX_PC25H_CM4_TRACEDATA2        _L_(7)
+#define PINMUX_PC25H_CM4_TRACEDATA2  ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
+#define PORT_PC25H_CM4_TRACEDATA2  (_UL_(1) << 25)
+#define PIN_PC24H_CM4_TRACEDATA3       _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
+#define MUX_PC24H_CM4_TRACEDATA3        _L_(7)
+#define PINMUX_PC24H_CM4_TRACEDATA3  ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
+#define PORT_PC24H_CM4_TRACEDATA3  (_UL_(1) << 24)
+/* ========== PORT definition for ANAREF peripheral ========== */
+#define PIN_PA03B_ANAREF_VREF0          _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
+#define MUX_PA03B_ANAREF_VREF0          _L_(1)
+#define PINMUX_PA03B_ANAREF_VREF0  ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
+#define PORT_PA03B_ANAREF_VREF0  (_UL_(1) <<  3)
+#define PIN_PA04B_ANAREF_VREF1          _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
+#define MUX_PA04B_ANAREF_VREF1          _L_(1)
+#define PINMUX_PA04B_ANAREF_VREF1  ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
+#define PORT_PA04B_ANAREF_VREF1  (_UL_(1) <<  4)
+#define PIN_PA06B_ANAREF_VREF2          _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
+#define MUX_PA06B_ANAREF_VREF2          _L_(1)
+#define PINMUX_PA06B_ANAREF_VREF2  ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
+#define PORT_PA06B_ANAREF_VREF2  (_UL_(1) <<  6)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA30M_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
+#define MUX_PA30M_GCLK_IO0             _L_(12)
+#define PINMUX_PA30M_GCLK_IO0      ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
+#define PORT_PA30M_GCLK_IO0    (_UL_(1) << 30)
+#define PIN_PB14M_GCLK_IO0             _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
+#define MUX_PB14M_GCLK_IO0             _L_(12)
+#define PINMUX_PB14M_GCLK_IO0      ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
+#define PORT_PB14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PA14M_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
+#define MUX_PA14M_GCLK_IO0             _L_(12)
+#define PINMUX_PA14M_GCLK_IO0      ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
+#define PORT_PA14M_GCLK_IO0    (_UL_(1) << 14)
+#define PIN_PB22M_GCLK_IO0             _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
+#define MUX_PB22M_GCLK_IO0             _L_(12)
+#define PINMUX_PB22M_GCLK_IO0      ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
+#define PORT_PB22M_GCLK_IO0    (_UL_(1) << 22)
+#define PIN_PB15M_GCLK_IO1             _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
+#define MUX_PB15M_GCLK_IO1             _L_(12)
+#define PINMUX_PB15M_GCLK_IO1      ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
+#define PORT_PB15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PA15M_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
+#define MUX_PA15M_GCLK_IO1             _L_(12)
+#define PINMUX_PA15M_GCLK_IO1      ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
+#define PORT_PA15M_GCLK_IO1    (_UL_(1) << 15)
+#define PIN_PB23M_GCLK_IO1             _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
+#define MUX_PB23M_GCLK_IO1             _L_(12)
+#define PINMUX_PB23M_GCLK_IO1      ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
+#define PORT_PB23M_GCLK_IO1    (_UL_(1) << 23)
+#define PIN_PA27M_GCLK_IO1             _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
+#define MUX_PA27M_GCLK_IO1             _L_(12)
+#define PINMUX_PA27M_GCLK_IO1      ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
+#define PORT_PA27M_GCLK_IO1    (_UL_(1) << 27)
+#define PIN_PA16M_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
+#define MUX_PA16M_GCLK_IO2             _L_(12)
+#define PINMUX_PA16M_GCLK_IO2      ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
+#define PORT_PA16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PB16M_GCLK_IO2             _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
+#define MUX_PB16M_GCLK_IO2             _L_(12)
+#define PINMUX_PB16M_GCLK_IO2      ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
+#define PORT_PB16M_GCLK_IO2    (_UL_(1) << 16)
+#define PIN_PA17M_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
+#define MUX_PA17M_GCLK_IO3             _L_(12)
+#define PINMUX_PA17M_GCLK_IO3      ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
+#define PORT_PA17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PB17M_GCLK_IO3             _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
+#define MUX_PB17M_GCLK_IO3             _L_(12)
+#define PINMUX_PB17M_GCLK_IO3      ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
+#define PORT_PB17M_GCLK_IO3    (_UL_(1) << 17)
+#define PIN_PA10M_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
+#define MUX_PA10M_GCLK_IO4             _L_(12)
+#define PINMUX_PA10M_GCLK_IO4      ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
+#define PORT_PA10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB10M_GCLK_IO4             _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
+#define MUX_PB10M_GCLK_IO4             _L_(12)
+#define PINMUX_PB10M_GCLK_IO4      ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
+#define PORT_PB10M_GCLK_IO4    (_UL_(1) << 10)
+#define PIN_PB18M_GCLK_IO4             _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
+#define MUX_PB18M_GCLK_IO4             _L_(12)
+#define PINMUX_PB18M_GCLK_IO4      ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
+#define PORT_PB18M_GCLK_IO4    (_UL_(1) << 18)
+#define PIN_PA11M_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
+#define MUX_PA11M_GCLK_IO5             _L_(12)
+#define PINMUX_PA11M_GCLK_IO5      ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
+#define PORT_PA11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB11M_GCLK_IO5             _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
+#define MUX_PB11M_GCLK_IO5             _L_(12)
+#define PINMUX_PB11M_GCLK_IO5      ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
+#define PORT_PB11M_GCLK_IO5    (_UL_(1) << 11)
+#define PIN_PB19M_GCLK_IO5             _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
+#define MUX_PB19M_GCLK_IO5             _L_(12)
+#define PINMUX_PB19M_GCLK_IO5      ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
+#define PORT_PB19M_GCLK_IO5    (_UL_(1) << 19)
+#define PIN_PB12M_GCLK_IO6             _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
+#define MUX_PB12M_GCLK_IO6             _L_(12)
+#define PINMUX_PB12M_GCLK_IO6      ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
+#define PORT_PB12M_GCLK_IO6    (_UL_(1) << 12)
+#define PIN_PB20M_GCLK_IO6             _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
+#define MUX_PB20M_GCLK_IO6             _L_(12)
+#define PINMUX_PB20M_GCLK_IO6      ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
+#define PORT_PB20M_GCLK_IO6    (_UL_(1) << 20)
+#define PIN_PB13M_GCLK_IO7             _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
+#define MUX_PB13M_GCLK_IO7             _L_(12)
+#define PINMUX_PB13M_GCLK_IO7      ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
+#define PORT_PB13M_GCLK_IO7    (_UL_(1) << 13)
+#define PIN_PB21M_GCLK_IO7             _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
+#define MUX_PB21M_GCLK_IO7             _L_(12)
+#define PINMUX_PB21M_GCLK_IO7      ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
+#define PORT_PB21M_GCLK_IO7    (_UL_(1) << 21)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
+#define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
+#define PIN_PB00A_EIC_EXTINT0          _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PB00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
+#define PIN_PB16A_EIC_EXTINT0          _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PB16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
+#define PIN_PC00A_EIC_EXTINT0          _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PC00A_EIC_EXTINT0   ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
+#define PORT_PC00A_EIC_EXTINT0  (_UL_(1) <<  0)
+#define PIN_PC00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
+#define PIN_PC16A_EIC_EXTINT0          _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT0           _L_(0)
+#define PINMUX_PC16A_EIC_EXTINT0   ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
+#define PORT_PC16A_EIC_EXTINT0  (_UL_(1) << 16)
+#define PIN_PC16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
+#define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
+#define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
+#define PIN_PB01A_EIC_EXTINT1          _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PB01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
+#define PIN_PB17A_EIC_EXTINT1          _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PB17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
+#define PIN_PC01A_EIC_EXTINT1          _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PC01A_EIC_EXTINT1   ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
+#define PORT_PC01A_EIC_EXTINT1  (_UL_(1) <<  1)
+#define PIN_PC01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
+#define PIN_PC17A_EIC_EXTINT1          _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT1           _L_(0)
+#define PINMUX_PC17A_EIC_EXTINT1   ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
+#define PORT_PC17A_EIC_EXTINT1  (_UL_(1) << 17)
+#define PIN_PC17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
+#define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
+#define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
+#define PIN_PB02A_EIC_EXTINT2          _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PB02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
+#define PIN_PB18A_EIC_EXTINT2          _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PB18A_EIC_EXTINT2   ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PB18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
+#define PIN_PC02A_EIC_EXTINT2          _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PC02A_EIC_EXTINT2   ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
+#define PORT_PC02A_EIC_EXTINT2  (_UL_(1) <<  2)
+#define PIN_PC02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
+#define PIN_PC18A_EIC_EXTINT2          _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT2           _L_(0)
+#define PINMUX_PC18A_EIC_EXTINT2   ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
+#define PORT_PC18A_EIC_EXTINT2  (_UL_(1) << 18)
+#define PIN_PC18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
+#define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
+#define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
+#define PIN_PB03A_EIC_EXTINT3          _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PB03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
+#define PIN_PB19A_EIC_EXTINT3          _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PB19A_EIC_EXTINT3   ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PB19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
+#define PIN_PC03A_EIC_EXTINT3          _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PC03A_EIC_EXTINT3   ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
+#define PORT_PC03A_EIC_EXTINT3  (_UL_(1) <<  3)
+#define PIN_PC03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
+#define PIN_PC19A_EIC_EXTINT3          _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT3           _L_(0)
+#define PINMUX_PC19A_EIC_EXTINT3   ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
+#define PORT_PC19A_EIC_EXTINT3  (_UL_(1) << 19)
+#define PIN_PC19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
+#define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
+#define PIN_PA20A_EIC_EXTINT4          _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PA20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
+#define PIN_PB04A_EIC_EXTINT4          _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4  (_UL_(1) <<  4)
+#define PIN_PB04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
+#define PIN_PB20A_EIC_EXTINT4          _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PB20A_EIC_EXTINT4   ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PB20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
+#define PIN_PC20A_EIC_EXTINT4          _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT4           _L_(0)
+#define PINMUX_PC20A_EIC_EXTINT4   ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
+#define PORT_PC20A_EIC_EXTINT4  (_UL_(1) << 20)
+#define PIN_PC20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
+#define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
+#define PIN_PA21A_EIC_EXTINT5          _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PA21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
+#define PIN_PB05A_EIC_EXTINT5          _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PB05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
+#define PIN_PB21A_EIC_EXTINT5          _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PB21A_EIC_EXTINT5   ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PB21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
+#define PIN_PC05A_EIC_EXTINT5          _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PC05A_EIC_EXTINT5   ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
+#define PORT_PC05A_EIC_EXTINT5  (_UL_(1) <<  5)
+#define PIN_PC05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
+#define PIN_PC21A_EIC_EXTINT5          _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT5           _L_(0)
+#define PINMUX_PC21A_EIC_EXTINT5   ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
+#define PORT_PC21A_EIC_EXTINT5  (_UL_(1) << 21)
+#define PIN_PC21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
+#define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
+#define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
+#define PIN_PB06A_EIC_EXTINT6          _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PB06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
+#define PIN_PB22A_EIC_EXTINT6          _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6  (_UL_(1) << 22)
+#define PIN_PB22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
+#define PIN_PC06A_EIC_EXTINT6          _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT6           _L_(0)
+#define PINMUX_PC06A_EIC_EXTINT6   ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
+#define PORT_PC06A_EIC_EXTINT6  (_UL_(1) <<  6)
+#define PIN_PC06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
+#define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
+#define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
+#define PIN_PB07A_EIC_EXTINT7          _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7  (_UL_(1) <<  7)
+#define PIN_PB07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
+#define PIN_PB23A_EIC_EXTINT7          _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7           _L_(0)
+#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7  (_UL_(1) << 23)
+#define PIN_PB23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
+#define PIN_PA24A_EIC_EXTINT8          _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PA24A_EIC_EXTINT8   ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
+#define PORT_PA24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PA24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
+#define PIN_PB08A_EIC_EXTINT8          _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8  (_UL_(1) <<  8)
+#define PIN_PB08A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
+#define PIN_PB24A_EIC_EXTINT8          _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PB24A_EIC_EXTINT8   ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PB24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
+#define PIN_PC24A_EIC_EXTINT8          _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT8           _L_(0)
+#define PINMUX_PC24A_EIC_EXTINT8   ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
+#define PORT_PC24A_EIC_EXTINT8  (_UL_(1) << 24)
+#define PIN_PC24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
+#define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
+#define PIN_PA25A_EIC_EXTINT9          _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PA25A_EIC_EXTINT9   ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
+#define PORT_PA25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PA25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
+#define PIN_PB09A_EIC_EXTINT9          _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9  (_UL_(1) <<  9)
+#define PIN_PB09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
+#define PIN_PB25A_EIC_EXTINT9          _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PB25A_EIC_EXTINT9   ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PB25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
+#define PIN_PC07A_EIC_EXTINT9          _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PC07A_EIC_EXTINT9   ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
+#define PORT_PC07A_EIC_EXTINT9  (_UL_(1) <<  7)
+#define PIN_PC07A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
+#define PIN_PC25A_EIC_EXTINT9          _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT9           _L_(0)
+#define PINMUX_PC25A_EIC_EXTINT9   ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
+#define PORT_PC25A_EIC_EXTINT9  (_UL_(1) << 25)
+#define PIN_PC25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
+#define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
+#define PIN_PB10A_EIC_EXTINT10         _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PB10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
+#define PIN_PC10A_EIC_EXTINT10         _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PC10A_EIC_EXTINT10  ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
+#define PORT_PC10A_EIC_EXTINT10  (_UL_(1) << 10)
+#define PIN_PC10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
+#define PIN_PC26A_EIC_EXTINT10         _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT10          _L_(0)
+#define PINMUX_PC26A_EIC_EXTINT10  ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
+#define PORT_PC26A_EIC_EXTINT10  (_UL_(1) << 26)
+#define PIN_PC26A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
+#define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
+#define PIN_PA27A_EIC_EXTINT11         _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PA27A_EIC_EXTINT11  ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
+#define PORT_PA27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PA27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
+#define PIN_PB11A_EIC_EXTINT11         _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PB11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
+#define PIN_PC11A_EIC_EXTINT11         _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PC11A_EIC_EXTINT11  ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
+#define PORT_PC11A_EIC_EXTINT11  (_UL_(1) << 11)
+#define PIN_PC11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
+#define PIN_PC27A_EIC_EXTINT11         _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT11          _L_(0)
+#define PINMUX_PC27A_EIC_EXTINT11  ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
+#define PORT_PC27A_EIC_EXTINT11  (_UL_(1) << 27)
+#define PIN_PC27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
+#define PIN_PA12A_EIC_EXTINT12         _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PA12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
+#define PIN_PB12A_EIC_EXTINT12         _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PB12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
+#define PIN_PC12A_EIC_EXTINT12         _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PC12A_EIC_EXTINT12  ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
+#define PORT_PC12A_EIC_EXTINT12  (_UL_(1) << 12)
+#define PIN_PC12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
+#define PIN_PC28A_EIC_EXTINT12         _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT12          _L_(0)
+#define PINMUX_PC28A_EIC_EXTINT12  ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
+#define PORT_PC28A_EIC_EXTINT12  (_UL_(1) << 28)
+#define PIN_PC28A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
+#define PIN_PA13A_EIC_EXTINT13         _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PA13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
+#define PIN_PB13A_EIC_EXTINT13         _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PB13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
+#define PIN_PC13A_EIC_EXTINT13         _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT13          _L_(0)
+#define PINMUX_PC13A_EIC_EXTINT13  ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
+#define PORT_PC13A_EIC_EXTINT13  (_UL_(1) << 13)
+#define PIN_PC13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
+#define PIN_PA30A_EIC_EXTINT14         _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA30A_EIC_EXTINT14  ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
+#define PORT_PA30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PA30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
+#define PIN_PB14A_EIC_EXTINT14         _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PB14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
+#define PIN_PB30A_EIC_EXTINT14         _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14  (_UL_(1) << 30)
+#define PIN_PB30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
+#define PIN_PC14A_EIC_EXTINT14         _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PC14A_EIC_EXTINT14  ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
+#define PORT_PC14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PC14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
+#define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14          _L_(0)
+#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
+#define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
+#define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
+#define PIN_PA31A_EIC_EXTINT15         _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PA31A_EIC_EXTINT15  ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
+#define PORT_PA31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PA31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
+#define PIN_PB15A_EIC_EXTINT15         _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PB15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
+#define PIN_PB31A_EIC_EXTINT15         _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15  (_UL_(1) << 31)
+#define PIN_PB31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
+#define PIN_PC15A_EIC_EXTINT15         _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT15          _L_(0)
+#define PINMUX_PC15A_EIC_EXTINT15  ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
+#define PORT_PC15A_EIC_EXTINT15  (_UL_(1) << 15)
+#define PIN_PC15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
+#define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI               _L_(0)
+#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
+#define PIN_PC17D_SERCOM0_PAD0         _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
+#define MUX_PC17D_SERCOM0_PAD0          _L_(3)
+#define PINMUX_PC17D_SERCOM0_PAD0  ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
+#define PORT_PC17D_SERCOM0_PAD0  (_UL_(1) << 17)
+#define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
+#define PIN_PB24C_SERCOM0_PAD0         _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0          _L_(2)
+#define PINMUX_PB24C_SERCOM0_PAD0  ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0  (_UL_(1) << 24)
+#define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
+#define PIN_PC16D_SERCOM0_PAD1         _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
+#define MUX_PC16D_SERCOM0_PAD1          _L_(3)
+#define PINMUX_PC16D_SERCOM0_PAD1  ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
+#define PORT_PC16D_SERCOM0_PAD1  (_UL_(1) << 16)
+#define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
+#define PIN_PB25C_SERCOM0_PAD1         _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1          _L_(2)
+#define PINMUX_PB25C_SERCOM0_PAD1  ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1  (_UL_(1) << 25)
+#define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
+#define PIN_PC18D_SERCOM0_PAD2         _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
+#define MUX_PC18D_SERCOM0_PAD2          _L_(3)
+#define PINMUX_PC18D_SERCOM0_PAD2  ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
+#define PORT_PC18D_SERCOM0_PAD2  (_UL_(1) << 18)
+#define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
+#define PIN_PC24C_SERCOM0_PAD2         _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2          _L_(2)
+#define PINMUX_PC24C_SERCOM0_PAD2  ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2  (_UL_(1) << 24)
+#define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
+#define PIN_PC19D_SERCOM0_PAD3         _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
+#define MUX_PC19D_SERCOM0_PAD3          _L_(3)
+#define PINMUX_PC19D_SERCOM0_PAD3  ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
+#define PORT_PC19D_SERCOM0_PAD3  (_UL_(1) << 19)
+#define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
+#define PIN_PC25C_SERCOM0_PAD3         _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3          _L_(2)
+#define PINMUX_PC25C_SERCOM0_PAD3  ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0          _L_(3)
+#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
+#define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
+#define PIN_PC27C_SERCOM1_PAD0         _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
+#define MUX_PC27C_SERCOM1_PAD0          _L_(2)
+#define PINMUX_PC27C_SERCOM1_PAD0  ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
+#define PORT_PC27C_SERCOM1_PAD0  (_UL_(1) << 27)
+#define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1          _L_(3)
+#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
+#define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
+#define PIN_PC28C_SERCOM1_PAD1         _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
+#define MUX_PC28C_SERCOM1_PAD1          _L_(2)
+#define PINMUX_PC28C_SERCOM1_PAD1  ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
+#define PORT_PC28C_SERCOM1_PAD1  (_UL_(1) << 28)
+#define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2          _L_(3)
+#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
+#define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
+#define PIN_PB22C_SERCOM1_PAD2         _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM1_PAD2          _L_(2)
+#define PINMUX_PB22C_SERCOM1_PAD2  ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
+#define PORT_PB22C_SERCOM1_PAD2  (_UL_(1) << 22)
+#define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3          _L_(3)
+#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
+#define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
+#define PIN_PB23C_SERCOM1_PAD3         _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM1_PAD3          _L_(2)
+#define PINMUX_PB23C_SERCOM1_PAD3  ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
+#define PORT_PB23C_SERCOM1_PAD3  (_UL_(1) << 23)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA04E_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TC0_WO0               _L_(4)
+#define PINMUX_PA04E_TC0_WO0       ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
+#define PORT_PA04E_TC0_WO0     (_UL_(1) <<  4)
+#define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TC0_WO0               _L_(4)
+#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
+#define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
+#define PIN_PB30E_TC0_WO0              _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TC0_WO0               _L_(4)
+#define PINMUX_PB30E_TC0_WO0       ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
+#define PORT_PB30E_TC0_WO0     (_UL_(1) << 30)
+#define PIN_PA05E_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TC0_WO1               _L_(4)
+#define PINMUX_PA05E_TC0_WO1       ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
+#define PORT_PA05E_TC0_WO1     (_UL_(1) <<  5)
+#define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TC0_WO1               _L_(4)
+#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
+#define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
+#define PIN_PB31E_TC0_WO1              _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TC0_WO1               _L_(4)
+#define PINMUX_PB31E_TC0_WO1       ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
+#define PORT_PB31E_TC0_WO1     (_UL_(1) << 31)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA06E_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TC1_WO0               _L_(4)
+#define PINMUX_PA06E_TC1_WO0       ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
+#define PORT_PA06E_TC1_WO0     (_UL_(1) <<  6)
+#define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TC1_WO0               _L_(4)
+#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
+#define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
+#define PIN_PA07E_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TC1_WO1               _L_(4)
+#define PINMUX_PA07E_TC1_WO1       ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
+#define PORT_PA07E_TC1_WO1     (_UL_(1) <<  7)
+#define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TC1_WO1               _L_(4)
+#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
+#define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24H_USB_DM               _L_(24) /**< \brief USB signal: DM on PA24 mux H */
+#define MUX_PA24H_USB_DM                _L_(7)
+#define PINMUX_PA24H_USB_DM        ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
+#define PORT_PA24H_USB_DM      (_UL_(1) << 24)
+#define PIN_PA25H_USB_DP               _L_(25) /**< \brief USB signal: DP on PA25 mux H */
+#define MUX_PA25H_USB_DP                _L_(7)
+#define PINMUX_PA25H_USB_DP        ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
+#define PORT_PA25H_USB_DP      (_UL_(1) << 25)
+#define PIN_PA23H_USB_SOF_1KHZ         _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
+#define MUX_PA23H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PA23H_USB_SOF_1KHZ  ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
+#define PORT_PA23H_USB_SOF_1KHZ  (_UL_(1) << 23)
+#define PIN_PB22H_USB_SOF_1KHZ         _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
+#define MUX_PB22H_USB_SOF_1KHZ          _L_(7)
+#define PINMUX_PB22H_USB_SOF_1KHZ  ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
+#define PORT_PB22H_USB_SOF_1KHZ  (_UL_(1) << 22)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA09D_SERCOM2_PAD0          _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PA09D_SERCOM2_PAD0  ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
+#define PORT_PA09D_SERCOM2_PAD0  (_UL_(1) <<  9)
+#define PIN_PB25D_SERCOM2_PAD0         _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
+#define MUX_PB25D_SERCOM2_PAD0          _L_(3)
+#define PINMUX_PB25D_SERCOM2_PAD0  ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
+#define PORT_PB25D_SERCOM2_PAD0  (_UL_(1) << 25)
+#define PIN_PA12C_SERCOM2_PAD0         _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0          _L_(2)
+#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0  (_UL_(1) << 12)
+#define PIN_PA08D_SERCOM2_PAD1          _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PA08D_SERCOM2_PAD1  ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
+#define PORT_PA08D_SERCOM2_PAD1  (_UL_(1) <<  8)
+#define PIN_PB24D_SERCOM2_PAD1         _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
+#define MUX_PB24D_SERCOM2_PAD1          _L_(3)
+#define PINMUX_PB24D_SERCOM2_PAD1  ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
+#define PORT_PB24D_SERCOM2_PAD1  (_UL_(1) << 24)
+#define PIN_PA13C_SERCOM2_PAD1         _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1          _L_(2)
+#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1  (_UL_(1) << 13)
+#define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
+#define PIN_PC24D_SERCOM2_PAD2         _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM2_PAD2          _L_(3)
+#define PINMUX_PC24D_SERCOM2_PAD2  ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
+#define PORT_PC24D_SERCOM2_PAD2  (_UL_(1) << 24)
+#define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2          _L_(2)
+#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
+#define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
+#define PIN_PC25D_SERCOM2_PAD3         _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM2_PAD3          _L_(3)
+#define PINMUX_PC25D_SERCOM2_PAD3  ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
+#define PORT_PC25D_SERCOM2_PAD3  (_UL_(1) << 25)
+#define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3          _L_(2)
+#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA17D_SERCOM3_PAD0         _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD0          _L_(3)
+#define PINMUX_PA17D_SERCOM3_PAD0  ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
+#define PORT_PA17D_SERCOM3_PAD0  (_UL_(1) << 17)
+#define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
+#define PIN_PB20C_SERCOM3_PAD0         _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0          _L_(2)
+#define PINMUX_PB20C_SERCOM3_PAD0  ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0  (_UL_(1) << 20)
+#define PIN_PA16D_SERCOM3_PAD1         _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD1          _L_(3)
+#define PINMUX_PA16D_SERCOM3_PAD1  ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
+#define PORT_PA16D_SERCOM3_PAD1  (_UL_(1) << 16)
+#define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
+#define PIN_PB21C_SERCOM3_PAD1         _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1          _L_(2)
+#define PINMUX_PB21C_SERCOM3_PAD1  ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1  (_UL_(1) << 21)
+#define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
+#define PIN_PA20D_SERCOM3_PAD2         _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2          _L_(3)
+#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2  (_UL_(1) << 20)
+#define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2          _L_(2)
+#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
+#define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
+#define PIN_PA21D_SERCOM3_PAD3         _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3          _L_(3)
+#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3  (_UL_(1) << 21)
+#define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3          _L_(2)
+#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA20G_TCC0_WO0             _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
+#define MUX_PA20G_TCC0_WO0              _L_(6)
+#define PINMUX_PA20G_TCC0_WO0      ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
+#define PORT_PA20G_TCC0_WO0    (_UL_(1) << 20)
+#define PIN_PB12G_TCC0_WO0             _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
+#define MUX_PB12G_TCC0_WO0              _L_(6)
+#define PINMUX_PB12G_TCC0_WO0      ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
+#define PORT_PB12G_TCC0_WO0    (_UL_(1) << 12)
+#define PIN_PA08F_TCC0_WO0              _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
+#define MUX_PA08F_TCC0_WO0              _L_(5)
+#define PINMUX_PA08F_TCC0_WO0      ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
+#define PORT_PA08F_TCC0_WO0    (_UL_(1) <<  8)
+#define PIN_PC10F_TCC0_WO0             _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
+#define MUX_PC10F_TCC0_WO0              _L_(5)
+#define PINMUX_PC10F_TCC0_WO0      ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
+#define PORT_PC10F_TCC0_WO0    (_UL_(1) << 10)
+#define PIN_PC16F_TCC0_WO0             _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
+#define MUX_PC16F_TCC0_WO0              _L_(5)
+#define PINMUX_PC16F_TCC0_WO0      ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
+#define PORT_PC16F_TCC0_WO0    (_UL_(1) << 16)
+#define PIN_PA21G_TCC0_WO1             _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
+#define MUX_PA21G_TCC0_WO1              _L_(6)
+#define PINMUX_PA21G_TCC0_WO1      ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
+#define PORT_PA21G_TCC0_WO1    (_UL_(1) << 21)
+#define PIN_PB13G_TCC0_WO1             _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
+#define MUX_PB13G_TCC0_WO1              _L_(6)
+#define PINMUX_PB13G_TCC0_WO1      ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
+#define PORT_PB13G_TCC0_WO1    (_UL_(1) << 13)
+#define PIN_PA09F_TCC0_WO1              _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
+#define MUX_PA09F_TCC0_WO1              _L_(5)
+#define PINMUX_PA09F_TCC0_WO1      ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
+#define PORT_PA09F_TCC0_WO1    (_UL_(1) <<  9)
+#define PIN_PC11F_TCC0_WO1             _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
+#define MUX_PC11F_TCC0_WO1              _L_(5)
+#define PINMUX_PC11F_TCC0_WO1      ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
+#define PORT_PC11F_TCC0_WO1    (_UL_(1) << 11)
+#define PIN_PC17F_TCC0_WO1             _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
+#define MUX_PC17F_TCC0_WO1              _L_(5)
+#define PINMUX_PC17F_TCC0_WO1      ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
+#define PORT_PC17F_TCC0_WO1    (_UL_(1) << 17)
+#define PIN_PA22G_TCC0_WO2             _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
+#define MUX_PA22G_TCC0_WO2              _L_(6)
+#define PINMUX_PA22G_TCC0_WO2      ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
+#define PORT_PA22G_TCC0_WO2    (_UL_(1) << 22)
+#define PIN_PB14G_TCC0_WO2             _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
+#define MUX_PB14G_TCC0_WO2              _L_(6)
+#define PINMUX_PB14G_TCC0_WO2      ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
+#define PORT_PB14G_TCC0_WO2    (_UL_(1) << 14)
+#define PIN_PA10F_TCC0_WO2             _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2              _L_(5)
+#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2    (_UL_(1) << 10)
+#define PIN_PC12F_TCC0_WO2             _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
+#define MUX_PC12F_TCC0_WO2              _L_(5)
+#define PINMUX_PC12F_TCC0_WO2      ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
+#define PORT_PC12F_TCC0_WO2    (_UL_(1) << 12)
+#define PIN_PC18F_TCC0_WO2             _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
+#define MUX_PC18F_TCC0_WO2              _L_(5)
+#define PINMUX_PC18F_TCC0_WO2      ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
+#define PORT_PC18F_TCC0_WO2    (_UL_(1) << 18)
+#define PIN_PA23G_TCC0_WO3             _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
+#define MUX_PA23G_TCC0_WO3              _L_(6)
+#define PINMUX_PA23G_TCC0_WO3      ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
+#define PORT_PA23G_TCC0_WO3    (_UL_(1) << 23)
+#define PIN_PB15G_TCC0_WO3             _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
+#define MUX_PB15G_TCC0_WO3              _L_(6)
+#define PINMUX_PB15G_TCC0_WO3      ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
+#define PORT_PB15G_TCC0_WO3    (_UL_(1) << 15)
+#define PIN_PA11F_TCC0_WO3             _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3              _L_(5)
+#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3    (_UL_(1) << 11)
+#define PIN_PC13F_TCC0_WO3             _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
+#define MUX_PC13F_TCC0_WO3              _L_(5)
+#define PINMUX_PC13F_TCC0_WO3      ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
+#define PORT_PC13F_TCC0_WO3    (_UL_(1) << 13)
+#define PIN_PC19F_TCC0_WO3             _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
+#define MUX_PC19F_TCC0_WO3              _L_(5)
+#define PINMUX_PC19F_TCC0_WO3      ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
+#define PORT_PC19F_TCC0_WO3    (_UL_(1) << 19)
+#define PIN_PA16G_TCC0_WO4             _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
+#define MUX_PA16G_TCC0_WO4              _L_(6)
+#define PINMUX_PA16G_TCC0_WO4      ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
+#define PORT_PA16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB16G_TCC0_WO4             _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
+#define MUX_PB16G_TCC0_WO4              _L_(6)
+#define PINMUX_PB16G_TCC0_WO4      ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
+#define PORT_PB16G_TCC0_WO4    (_UL_(1) << 16)
+#define PIN_PB10F_TCC0_WO4             _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4              _L_(5)
+#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4    (_UL_(1) << 10)
+#define PIN_PC14F_TCC0_WO4             _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
+#define MUX_PC14F_TCC0_WO4              _L_(5)
+#define PINMUX_PC14F_TCC0_WO4      ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
+#define PORT_PC14F_TCC0_WO4    (_UL_(1) << 14)
+#define PIN_PC20F_TCC0_WO4             _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
+#define MUX_PC20F_TCC0_WO4              _L_(5)
+#define PINMUX_PC20F_TCC0_WO4      ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
+#define PORT_PC20F_TCC0_WO4    (_UL_(1) << 20)
+#define PIN_PA17G_TCC0_WO5             _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
+#define MUX_PA17G_TCC0_WO5              _L_(6)
+#define PINMUX_PA17G_TCC0_WO5      ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
+#define PORT_PA17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB17G_TCC0_WO5             _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
+#define MUX_PB17G_TCC0_WO5              _L_(6)
+#define PINMUX_PB17G_TCC0_WO5      ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
+#define PORT_PB17G_TCC0_WO5    (_UL_(1) << 17)
+#define PIN_PB11F_TCC0_WO5             _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5              _L_(5)
+#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5    (_UL_(1) << 11)
+#define PIN_PC15F_TCC0_WO5             _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
+#define MUX_PC15F_TCC0_WO5              _L_(5)
+#define PINMUX_PC15F_TCC0_WO5      ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
+#define PORT_PC15F_TCC0_WO5    (_UL_(1) << 15)
+#define PIN_PC21F_TCC0_WO5             _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
+#define MUX_PC21F_TCC0_WO5              _L_(5)
+#define PINMUX_PC21F_TCC0_WO5      ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
+#define PORT_PC21F_TCC0_WO5    (_UL_(1) << 21)
+#define PIN_PA18G_TCC0_WO6             _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
+#define MUX_PA18G_TCC0_WO6              _L_(6)
+#define PINMUX_PA18G_TCC0_WO6      ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
+#define PORT_PA18G_TCC0_WO6    (_UL_(1) << 18)
+#define PIN_PB30G_TCC0_WO6             _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
+#define MUX_PB30G_TCC0_WO6              _L_(6)
+#define PINMUX_PB30G_TCC0_WO6      ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
+#define PORT_PB30G_TCC0_WO6    (_UL_(1) << 30)
+#define PIN_PA12F_TCC0_WO6             _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6              _L_(5)
+#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6    (_UL_(1) << 12)
+#define PIN_PA19G_TCC0_WO7             _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
+#define MUX_PA19G_TCC0_WO7              _L_(6)
+#define PINMUX_PA19G_TCC0_WO7      ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
+#define PORT_PA19G_TCC0_WO7    (_UL_(1) << 19)
+#define PIN_PB31G_TCC0_WO7             _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
+#define MUX_PB31G_TCC0_WO7              _L_(6)
+#define PINMUX_PB31G_TCC0_WO7      ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
+#define PORT_PB31G_TCC0_WO7    (_UL_(1) << 31)
+#define PIN_PA13F_TCC0_WO7             _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7              _L_(5)
+#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7    (_UL_(1) << 13)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PB10G_TCC1_WO0             _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
+#define MUX_PB10G_TCC1_WO0              _L_(6)
+#define PINMUX_PB10G_TCC1_WO0      ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
+#define PORT_PB10G_TCC1_WO0    (_UL_(1) << 10)
+#define PIN_PC14G_TCC1_WO0             _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
+#define MUX_PC14G_TCC1_WO0              _L_(6)
+#define PINMUX_PC14G_TCC1_WO0      ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
+#define PORT_PC14G_TCC1_WO0    (_UL_(1) << 14)
+#define PIN_PA16F_TCC1_WO0             _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
+#define MUX_PA16F_TCC1_WO0              _L_(5)
+#define PINMUX_PA16F_TCC1_WO0      ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
+#define PORT_PA16F_TCC1_WO0    (_UL_(1) << 16)
+#define PIN_PB18F_TCC1_WO0             _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC1_WO0              _L_(5)
+#define PINMUX_PB18F_TCC1_WO0      ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
+#define PORT_PB18F_TCC1_WO0    (_UL_(1) << 18)
+#define PIN_PB11G_TCC1_WO1             _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
+#define MUX_PB11G_TCC1_WO1              _L_(6)
+#define PINMUX_PB11G_TCC1_WO1      ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
+#define PORT_PB11G_TCC1_WO1    (_UL_(1) << 11)
+#define PIN_PC15G_TCC1_WO1             _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
+#define MUX_PC15G_TCC1_WO1              _L_(6)
+#define PINMUX_PC15G_TCC1_WO1      ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
+#define PORT_PC15G_TCC1_WO1    (_UL_(1) << 15)
+#define PIN_PA17F_TCC1_WO1             _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
+#define MUX_PA17F_TCC1_WO1              _L_(5)
+#define PINMUX_PA17F_TCC1_WO1      ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
+#define PORT_PA17F_TCC1_WO1    (_UL_(1) << 17)
+#define PIN_PB19F_TCC1_WO1             _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC1_WO1              _L_(5)
+#define PINMUX_PB19F_TCC1_WO1      ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
+#define PORT_PB19F_TCC1_WO1    (_UL_(1) << 19)
+#define PIN_PA12G_TCC1_WO2             _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
+#define MUX_PA12G_TCC1_WO2              _L_(6)
+#define PINMUX_PA12G_TCC1_WO2      ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
+#define PORT_PA12G_TCC1_WO2    (_UL_(1) << 12)
+#define PIN_PA14G_TCC1_WO2             _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
+#define MUX_PA14G_TCC1_WO2              _L_(6)
+#define PINMUX_PA14G_TCC1_WO2      ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
+#define PORT_PA14G_TCC1_WO2    (_UL_(1) << 14)
+#define PIN_PA18F_TCC1_WO2             _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC1_WO2              _L_(5)
+#define PINMUX_PA18F_TCC1_WO2      ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
+#define PORT_PA18F_TCC1_WO2    (_UL_(1) << 18)
+#define PIN_PB20F_TCC1_WO2             _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC1_WO2              _L_(5)
+#define PINMUX_PB20F_TCC1_WO2      ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
+#define PORT_PB20F_TCC1_WO2    (_UL_(1) << 20)
+#define PIN_PA13G_TCC1_WO3             _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
+#define MUX_PA13G_TCC1_WO3              _L_(6)
+#define PINMUX_PA13G_TCC1_WO3      ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
+#define PORT_PA13G_TCC1_WO3    (_UL_(1) << 13)
+#define PIN_PA15G_TCC1_WO3             _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
+#define MUX_PA15G_TCC1_WO3              _L_(6)
+#define PINMUX_PA15G_TCC1_WO3      ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
+#define PORT_PA15G_TCC1_WO3    (_UL_(1) << 15)
+#define PIN_PA19F_TCC1_WO3             _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC1_WO3              _L_(5)
+#define PINMUX_PA19F_TCC1_WO3      ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
+#define PORT_PA19F_TCC1_WO3    (_UL_(1) << 19)
+#define PIN_PB21F_TCC1_WO3             _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC1_WO3              _L_(5)
+#define PINMUX_PB21F_TCC1_WO3      ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
+#define PORT_PB21F_TCC1_WO3    (_UL_(1) << 21)
+#define PIN_PA08G_TCC1_WO4              _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
+#define MUX_PA08G_TCC1_WO4              _L_(6)
+#define PINMUX_PA08G_TCC1_WO4      ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
+#define PORT_PA08G_TCC1_WO4    (_UL_(1) <<  8)
+#define PIN_PC10G_TCC1_WO4             _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
+#define MUX_PC10G_TCC1_WO4              _L_(6)
+#define PINMUX_PC10G_TCC1_WO4      ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
+#define PORT_PC10G_TCC1_WO4    (_UL_(1) << 10)
+#define PIN_PA20F_TCC1_WO4             _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
+#define MUX_PA20F_TCC1_WO4              _L_(5)
+#define PINMUX_PA20F_TCC1_WO4      ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
+#define PORT_PA20F_TCC1_WO4    (_UL_(1) << 20)
+#define PIN_PA09G_TCC1_WO5              _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
+#define MUX_PA09G_TCC1_WO5              _L_(6)
+#define PINMUX_PA09G_TCC1_WO5      ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
+#define PORT_PA09G_TCC1_WO5    (_UL_(1) <<  9)
+#define PIN_PC11G_TCC1_WO5             _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
+#define MUX_PC11G_TCC1_WO5              _L_(6)
+#define PINMUX_PC11G_TCC1_WO5      ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
+#define PORT_PC11G_TCC1_WO5    (_UL_(1) << 11)
+#define PIN_PA21F_TCC1_WO5             _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
+#define MUX_PA21F_TCC1_WO5              _L_(5)
+#define PINMUX_PA21F_TCC1_WO5      ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
+#define PORT_PA21F_TCC1_WO5    (_UL_(1) << 21)
+#define PIN_PA10G_TCC1_WO6             _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
+#define MUX_PA10G_TCC1_WO6              _L_(6)
+#define PINMUX_PA10G_TCC1_WO6      ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
+#define PORT_PA10G_TCC1_WO6    (_UL_(1) << 10)
+#define PIN_PC12G_TCC1_WO6             _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
+#define MUX_PC12G_TCC1_WO6              _L_(6)
+#define PINMUX_PC12G_TCC1_WO6      ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
+#define PORT_PC12G_TCC1_WO6    (_UL_(1) << 12)
+#define PIN_PA22F_TCC1_WO6             _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
+#define MUX_PA22F_TCC1_WO6              _L_(5)
+#define PINMUX_PA22F_TCC1_WO6      ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
+#define PORT_PA22F_TCC1_WO6    (_UL_(1) << 22)
+#define PIN_PA11G_TCC1_WO7             _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
+#define MUX_PA11G_TCC1_WO7              _L_(6)
+#define PINMUX_PA11G_TCC1_WO7      ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
+#define PORT_PA11G_TCC1_WO7    (_UL_(1) << 11)
+#define PIN_PC13G_TCC1_WO7             _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
+#define MUX_PC13G_TCC1_WO7              _L_(6)
+#define PINMUX_PC13G_TCC1_WO7      ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
+#define PORT_PC13G_TCC1_WO7    (_UL_(1) << 13)
+#define PIN_PA23F_TCC1_WO7             _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
+#define MUX_PA23F_TCC1_WO7              _L_(5)
+#define PINMUX_PA23F_TCC1_WO7      ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
+#define PORT_PA23F_TCC1_WO7    (_UL_(1) << 23)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PA12E_TC2_WO0              _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TC2_WO0               _L_(4)
+#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
+#define PORT_PA12E_TC2_WO0     (_UL_(1) << 12)
+#define PIN_PA16E_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TC2_WO0               _L_(4)
+#define PINMUX_PA16E_TC2_WO0       ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
+#define PORT_PA16E_TC2_WO0     (_UL_(1) << 16)
+#define PIN_PA00E_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TC2_WO0               _L_(4)
+#define PINMUX_PA00E_TC2_WO0       ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
+#define PORT_PA00E_TC2_WO0     (_UL_(1) <<  0)
+#define PIN_PA01E_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TC2_WO1               _L_(4)
+#define PINMUX_PA01E_TC2_WO1       ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
+#define PORT_PA01E_TC2_WO1     (_UL_(1) <<  1)
+#define PIN_PA13E_TC2_WO1              _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TC2_WO1               _L_(4)
+#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
+#define PORT_PA13E_TC2_WO1     (_UL_(1) << 13)
+#define PIN_PA17E_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TC2_WO1               _L_(4)
+#define PINMUX_PA17E_TC2_WO1       ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
+#define PORT_PA17E_TC2_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0               _L_(4)
+#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0     (_UL_(1) << 18)
+#define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0               _L_(4)
+#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
+#define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1               _L_(4)
+#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
+#define PIN_PA19E_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1               _L_(4)
+#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1     (_UL_(1) << 19)
+/* ========== PORT definition for GMAC peripheral ========== */
+#define PIN_PC21L_GMAC_GCOL            _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
+#define MUX_PC21L_GMAC_GCOL            _L_(11)
+#define PINMUX_PC21L_GMAC_GCOL     ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
+#define PORT_PC21L_GMAC_GCOL   (_UL_(1) << 21)
+#define PIN_PA16L_GMAC_GCRS            _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
+#define MUX_PA16L_GMAC_GCRS            _L_(11)
+#define PINMUX_PA16L_GMAC_GCRS     ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
+#define PORT_PA16L_GMAC_GCRS   (_UL_(1) << 16)
+#define PIN_PA20L_GMAC_GMDC            _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
+#define MUX_PA20L_GMAC_GMDC            _L_(11)
+#define PINMUX_PA20L_GMAC_GMDC     ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
+#define PORT_PA20L_GMAC_GMDC   (_UL_(1) << 20)
+#define PIN_PB14L_GMAC_GMDC            _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
+#define MUX_PB14L_GMAC_GMDC            _L_(11)
+#define PINMUX_PB14L_GMAC_GMDC     ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
+#define PORT_PB14L_GMAC_GMDC   (_UL_(1) << 14)
+#define PIN_PC11L_GMAC_GMDC            _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
+#define MUX_PC11L_GMAC_GMDC            _L_(11)
+#define PINMUX_PC11L_GMAC_GMDC     ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
+#define PORT_PC11L_GMAC_GMDC   (_UL_(1) << 11)
+#define PIN_PA21L_GMAC_GMDIO           _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
+#define MUX_PA21L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PA21L_GMAC_GMDIO    ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
+#define PORT_PA21L_GMAC_GMDIO  (_UL_(1) << 21)
+#define PIN_PB15L_GMAC_GMDIO           _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
+#define MUX_PB15L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PB15L_GMAC_GMDIO    ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
+#define PORT_PB15L_GMAC_GMDIO  (_UL_(1) << 15)
+#define PIN_PC12L_GMAC_GMDIO           _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
+#define MUX_PC12L_GMAC_GMDIO           _L_(11)
+#define PINMUX_PC12L_GMAC_GMDIO    ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
+#define PORT_PC12L_GMAC_GMDIO  (_UL_(1) << 12)
+#define PIN_PA13L_GMAC_GRX0            _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
+#define MUX_PA13L_GMAC_GRX0            _L_(11)
+#define PINMUX_PA13L_GMAC_GRX0     ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
+#define PORT_PA13L_GMAC_GRX0   (_UL_(1) << 13)
+#define PIN_PA12L_GMAC_GRX1            _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
+#define MUX_PA12L_GMAC_GRX1            _L_(11)
+#define PINMUX_PA12L_GMAC_GRX1     ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
+#define PORT_PA12L_GMAC_GRX1   (_UL_(1) << 12)
+#define PIN_PC15L_GMAC_GRX2            _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
+#define MUX_PC15L_GMAC_GRX2            _L_(11)
+#define PINMUX_PC15L_GMAC_GRX2     ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
+#define PORT_PC15L_GMAC_GRX2   (_UL_(1) << 15)
+#define PIN_PC14L_GMAC_GRX3            _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
+#define MUX_PC14L_GMAC_GRX3            _L_(11)
+#define PINMUX_PC14L_GMAC_GRX3     ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
+#define PORT_PC14L_GMAC_GRX3   (_UL_(1) << 14)
+#define PIN_PC18L_GMAC_GRXCK           _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
+#define MUX_PC18L_GMAC_GRXCK           _L_(11)
+#define PINMUX_PC18L_GMAC_GRXCK    ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
+#define PORT_PC18L_GMAC_GRXCK  (_UL_(1) << 18)
+#define PIN_PC20L_GMAC_GRXDV           _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
+#define MUX_PC20L_GMAC_GRXDV           _L_(11)
+#define PINMUX_PC20L_GMAC_GRXDV    ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
+#define PORT_PC20L_GMAC_GRXDV  (_UL_(1) << 20)
+#define PIN_PA15L_GMAC_GRXER           _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
+#define MUX_PA15L_GMAC_GRXER           _L_(11)
+#define PINMUX_PA15L_GMAC_GRXER    ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
+#define PORT_PA15L_GMAC_GRXER  (_UL_(1) << 15)
+#define PIN_PA18L_GMAC_GTX0            _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
+#define MUX_PA18L_GMAC_GTX0            _L_(11)
+#define PINMUX_PA18L_GMAC_GTX0     ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
+#define PORT_PA18L_GMAC_GTX0   (_UL_(1) << 18)
+#define PIN_PA19L_GMAC_GTX1            _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
+#define MUX_PA19L_GMAC_GTX1            _L_(11)
+#define PINMUX_PA19L_GMAC_GTX1     ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
+#define PORT_PA19L_GMAC_GTX1   (_UL_(1) << 19)
+#define PIN_PC16L_GMAC_GTX2            _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
+#define MUX_PC16L_GMAC_GTX2            _L_(11)
+#define PINMUX_PC16L_GMAC_GTX2     ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
+#define PORT_PC16L_GMAC_GTX2   (_UL_(1) << 16)
+#define PIN_PC17L_GMAC_GTX3            _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
+#define MUX_PC17L_GMAC_GTX3            _L_(11)
+#define PINMUX_PC17L_GMAC_GTX3     ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
+#define PORT_PC17L_GMAC_GTX3   (_UL_(1) << 17)
+#define PIN_PA14L_GMAC_GTXCK           _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
+#define MUX_PA14L_GMAC_GTXCK           _L_(11)
+#define PINMUX_PA14L_GMAC_GTXCK    ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
+#define PORT_PA14L_GMAC_GTXCK  (_UL_(1) << 14)
+#define PIN_PA17L_GMAC_GTXEN           _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
+#define MUX_PA17L_GMAC_GTXEN           _L_(11)
+#define PINMUX_PA17L_GMAC_GTXEN    ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
+#define PORT_PA17L_GMAC_GTXEN  (_UL_(1) << 17)
+#define PIN_PC19L_GMAC_GTXER           _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
+#define MUX_PC19L_GMAC_GTXER           _L_(11)
+#define PINMUX_PC19L_GMAC_GTXER    ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
+#define PORT_PC19L_GMAC_GTXER  (_UL_(1) << 19)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA14F_TCC2_WO0             _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
+#define MUX_PA14F_TCC2_WO0              _L_(5)
+#define PINMUX_PA14F_TCC2_WO0      ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
+#define PORT_PA14F_TCC2_WO0    (_UL_(1) << 14)
+#define PIN_PA30F_TCC2_WO0             _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
+#define MUX_PA30F_TCC2_WO0              _L_(5)
+#define PINMUX_PA30F_TCC2_WO0      ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
+#define PORT_PA30F_TCC2_WO0    (_UL_(1) << 30)
+#define PIN_PA15F_TCC2_WO1             _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
+#define MUX_PA15F_TCC2_WO1              _L_(5)
+#define PINMUX_PA15F_TCC2_WO1      ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
+#define PORT_PA15F_TCC2_WO1    (_UL_(1) << 15)
+#define PIN_PA31F_TCC2_WO1             _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
+#define MUX_PA31F_TCC2_WO1              _L_(5)
+#define PINMUX_PA31F_TCC2_WO1      ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
+#define PORT_PA31F_TCC2_WO1    (_UL_(1) << 31)
+#define PIN_PA24F_TCC2_WO2             _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC2_WO2              _L_(5)
+#define PINMUX_PA24F_TCC2_WO2      ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
+#define PORT_PA24F_TCC2_WO2    (_UL_(1) << 24)
+#define PIN_PB02F_TCC2_WO2             _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
+#define MUX_PB02F_TCC2_WO2              _L_(5)
+#define PINMUX_PB02F_TCC2_WO2      ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
+#define PORT_PB02F_TCC2_WO2    (_UL_(1) <<  2)
+/* ========== PORT definition for TCC3 peripheral ========== */
+#define PIN_PB12F_TCC3_WO0             _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
+#define MUX_PB12F_TCC3_WO0              _L_(5)
+#define PINMUX_PB12F_TCC3_WO0      ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
+#define PORT_PB12F_TCC3_WO0    (_UL_(1) << 12)
+#define PIN_PB16F_TCC3_WO0             _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
+#define MUX_PB16F_TCC3_WO0              _L_(5)
+#define PINMUX_PB16F_TCC3_WO0      ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
+#define PORT_PB16F_TCC3_WO0    (_UL_(1) << 16)
+#define PIN_PB13F_TCC3_WO1             _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
+#define MUX_PB13F_TCC3_WO1              _L_(5)
+#define PINMUX_PB13F_TCC3_WO1      ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
+#define PORT_PB13F_TCC3_WO1    (_UL_(1) << 13)
+#define PIN_PB17F_TCC3_WO1             _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
+#define MUX_PB17F_TCC3_WO1              _L_(5)
+#define PINMUX_PB17F_TCC3_WO1      ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
+#define PORT_PB17F_TCC3_WO1    (_UL_(1) << 17)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0               _L_(4)
+#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0     (_UL_(1) << 22)
+#define PIN_PB08E_TC4_WO0              _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0               _L_(4)
+#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0     (_UL_(1) <<  8)
+#define PIN_PB12E_TC4_WO0              _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0               _L_(4)
+#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0     (_UL_(1) << 12)
+#define PIN_PA23E_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1               _L_(4)
+#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1     (_UL_(1) << 23)
+#define PIN_PB09E_TC4_WO1              _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1               _L_(4)
+#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1     (_UL_(1) <<  9)
+#define PIN_PB13E_TC4_WO1              _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1               _L_(4)
+#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1     (_UL_(1) << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0               _L_(4)
+#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0     (_UL_(1) << 24)
+#define PIN_PB10E_TC5_WO0              _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0               _L_(4)
+#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0     (_UL_(1) << 10)
+#define PIN_PB14E_TC5_WO0              _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0               _L_(4)
+#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0     (_UL_(1) << 14)
+#define PIN_PA25E_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1               _L_(4)
+#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1     (_UL_(1) << 25)
+#define PIN_PB11E_TC5_WO1              _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1               _L_(4)
+#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1     (_UL_(1) << 11)
+#define PIN_PB15E_TC5_WO1              _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1               _L_(4)
+#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1     (_UL_(1) << 15)
+/* ========== PORT definition for PDEC peripheral ========== */
+#define PIN_PB18G_PDEC_QDI0            _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
+#define MUX_PB18G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB18G_PDEC_QDI0     ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
+#define PORT_PB18G_PDEC_QDI0   (_UL_(1) << 18)
+#define PIN_PB23G_PDEC_QDI0            _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
+#define MUX_PB23G_PDEC_QDI0             _L_(6)
+#define PINMUX_PB23G_PDEC_QDI0     ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
+#define PORT_PB23G_PDEC_QDI0   (_UL_(1) << 23)
+#define PIN_PC16G_PDEC_QDI0            _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
+#define MUX_PC16G_PDEC_QDI0             _L_(6)
+#define PINMUX_PC16G_PDEC_QDI0     ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
+#define PORT_PC16G_PDEC_QDI0   (_UL_(1) << 16)
+#define PIN_PA24G_PDEC_QDI0            _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
+#define MUX_PA24G_PDEC_QDI0             _L_(6)
+#define PINMUX_PA24G_PDEC_QDI0     ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
+#define PORT_PA24G_PDEC_QDI0   (_UL_(1) << 24)
+#define PIN_PB19G_PDEC_QDI1            _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
+#define MUX_PB19G_PDEC_QDI1             _L_(6)
+#define PINMUX_PB19G_PDEC_QDI1     ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
+#define PORT_PB19G_PDEC_QDI1   (_UL_(1) << 19)
+#define PIN_PB24G_PDEC_QDI1            _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
+#define MUX_PB24G_PDEC_QDI1             _L_(6)
+#define PINMUX_PB24G_PDEC_QDI1     ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
+#define PORT_PB24G_PDEC_QDI1   (_UL_(1) << 24)
+#define PIN_PC17G_PDEC_QDI1            _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
+#define MUX_PC17G_PDEC_QDI1             _L_(6)
+#define PINMUX_PC17G_PDEC_QDI1     ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
+#define PORT_PC17G_PDEC_QDI1   (_UL_(1) << 17)
+#define PIN_PA25G_PDEC_QDI1            _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
+#define MUX_PA25G_PDEC_QDI1             _L_(6)
+#define PINMUX_PA25G_PDEC_QDI1     ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
+#define PORT_PA25G_PDEC_QDI1   (_UL_(1) << 25)
+#define PIN_PB20G_PDEC_QDI2            _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
+#define MUX_PB20G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB20G_PDEC_QDI2     ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
+#define PORT_PB20G_PDEC_QDI2   (_UL_(1) << 20)
+#define PIN_PB25G_PDEC_QDI2            _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
+#define MUX_PB25G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB25G_PDEC_QDI2     ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
+#define PORT_PB25G_PDEC_QDI2   (_UL_(1) << 25)
+#define PIN_PC18G_PDEC_QDI2            _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
+#define MUX_PC18G_PDEC_QDI2             _L_(6)
+#define PINMUX_PC18G_PDEC_QDI2     ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
+#define PORT_PC18G_PDEC_QDI2   (_UL_(1) << 18)
+#define PIN_PB22G_PDEC_QDI2            _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
+#define MUX_PB22G_PDEC_QDI2             _L_(6)
+#define PINMUX_PB22G_PDEC_QDI2     ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
+#define PORT_PB22G_PDEC_QDI2   (_UL_(1) << 22)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0               _L_(1)
+#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
+#define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1               _L_(1)
+#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
+#define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2               _L_(1)
+#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
+#define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3               _L_(1)
+#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
+#define PIN_PA12M_AC_CMP0              _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
+#define MUX_PA12M_AC_CMP0              _L_(12)
+#define PINMUX_PA12M_AC_CMP0       ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
+#define PORT_PA12M_AC_CMP0     (_UL_(1) << 12)
+#define PIN_PA18M_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
+#define MUX_PA18M_AC_CMP0              _L_(12)
+#define PINMUX_PA18M_AC_CMP0       ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
+#define PORT_PA18M_AC_CMP0     (_UL_(1) << 18)
+#define PIN_PB24M_AC_CMP0              _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
+#define MUX_PB24M_AC_CMP0              _L_(12)
+#define PINMUX_PB24M_AC_CMP0       ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
+#define PORT_PB24M_AC_CMP0     (_UL_(1) << 24)
+#define PIN_PA13M_AC_CMP1              _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
+#define MUX_PA13M_AC_CMP1              _L_(12)
+#define PINMUX_PA13M_AC_CMP1       ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
+#define PORT_PA13M_AC_CMP1     (_UL_(1) << 13)
+#define PIN_PA19M_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
+#define MUX_PA19M_AC_CMP1              _L_(12)
+#define PINMUX_PA19M_AC_CMP1       ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
+#define PORT_PA19M_AC_CMP1     (_UL_(1) << 19)
+#define PIN_PB25M_AC_CMP1              _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
+#define MUX_PB25M_AC_CMP1              _L_(12)
+#define PINMUX_PB25M_AC_CMP1       ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
+#define PORT_PB25M_AC_CMP1     (_UL_(1) << 25)
+/* ========== PORT definition for QSPI peripheral ========== */
+#define PIN_PB11H_QSPI_CS              _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
+#define MUX_PB11H_QSPI_CS               _L_(7)
+#define PINMUX_PB11H_QSPI_CS       ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
+#define PORT_PB11H_QSPI_CS     (_UL_(1) << 11)
+#define PIN_PA08H_QSPI_DATA0            _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
+#define MUX_PA08H_QSPI_DATA0            _L_(7)
+#define PINMUX_PA08H_QSPI_DATA0    ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
+#define PORT_PA08H_QSPI_DATA0  (_UL_(1) <<  8)
+#define PIN_PA09H_QSPI_DATA1            _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
+#define MUX_PA09H_QSPI_DATA1            _L_(7)
+#define PINMUX_PA09H_QSPI_DATA1    ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
+#define PORT_PA09H_QSPI_DATA1  (_UL_(1) <<  9)
+#define PIN_PA10H_QSPI_DATA2           _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
+#define MUX_PA10H_QSPI_DATA2            _L_(7)
+#define PINMUX_PA10H_QSPI_DATA2    ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
+#define PORT_PA10H_QSPI_DATA2  (_UL_(1) << 10)
+#define PIN_PA11H_QSPI_DATA3           _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
+#define MUX_PA11H_QSPI_DATA3            _L_(7)
+#define PINMUX_PA11H_QSPI_DATA3    ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
+#define PORT_PA11H_QSPI_DATA3  (_UL_(1) << 11)
+#define PIN_PB10H_QSPI_SCK             _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
+#define MUX_PB10H_QSPI_SCK              _L_(7)
+#define PINMUX_PB10H_QSPI_SCK      ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
+#define PORT_PB10H_QSPI_SCK    (_UL_(1) << 10)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04N_CCL_IN0               _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
+#define MUX_PA04N_CCL_IN0              _L_(13)
+#define PINMUX_PA04N_CCL_IN0       ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
+#define PORT_PA04N_CCL_IN0     (_UL_(1) <<  4)
+#define PIN_PA16N_CCL_IN0              _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
+#define MUX_PA16N_CCL_IN0              _L_(13)
+#define PINMUX_PA16N_CCL_IN0       ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
+#define PORT_PA16N_CCL_IN0     (_UL_(1) << 16)
+#define PIN_PB22N_CCL_IN0              _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
+#define MUX_PB22N_CCL_IN0              _L_(13)
+#define PINMUX_PB22N_CCL_IN0       ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
+#define PORT_PB22N_CCL_IN0     (_UL_(1) << 22)
+#define PIN_PA05N_CCL_IN1               _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
+#define MUX_PA05N_CCL_IN1              _L_(13)
+#define PINMUX_PA05N_CCL_IN1       ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
+#define PORT_PA05N_CCL_IN1     (_UL_(1) <<  5)
+#define PIN_PA17N_CCL_IN1              _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
+#define MUX_PA17N_CCL_IN1              _L_(13)
+#define PINMUX_PA17N_CCL_IN1       ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
+#define PORT_PA17N_CCL_IN1     (_UL_(1) << 17)
+#define PIN_PB00N_CCL_IN1              _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
+#define MUX_PB00N_CCL_IN1              _L_(13)
+#define PINMUX_PB00N_CCL_IN1       ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
+#define PORT_PB00N_CCL_IN1     (_UL_(1) <<  0)
+#define PIN_PA06N_CCL_IN2               _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
+#define MUX_PA06N_CCL_IN2              _L_(13)
+#define PINMUX_PA06N_CCL_IN2       ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
+#define PORT_PA06N_CCL_IN2     (_UL_(1) <<  6)
+#define PIN_PA18N_CCL_IN2              _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
+#define MUX_PA18N_CCL_IN2              _L_(13)
+#define PINMUX_PA18N_CCL_IN2       ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
+#define PORT_PA18N_CCL_IN2     (_UL_(1) << 18)
+#define PIN_PB01N_CCL_IN2              _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
+#define MUX_PB01N_CCL_IN2              _L_(13)
+#define PINMUX_PB01N_CCL_IN2       ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
+#define PORT_PB01N_CCL_IN2     (_UL_(1) <<  1)
+#define PIN_PA08N_CCL_IN3               _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
+#define MUX_PA08N_CCL_IN3              _L_(13)
+#define PINMUX_PA08N_CCL_IN3       ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
+#define PORT_PA08N_CCL_IN3     (_UL_(1) <<  8)
+#define PIN_PA30N_CCL_IN3              _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
+#define MUX_PA30N_CCL_IN3              _L_(13)
+#define PINMUX_PA30N_CCL_IN3       ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
+#define PORT_PA30N_CCL_IN3     (_UL_(1) << 30)
+#define PIN_PA09N_CCL_IN4               _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
+#define MUX_PA09N_CCL_IN4              _L_(13)
+#define PINMUX_PA09N_CCL_IN4       ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
+#define PORT_PA09N_CCL_IN4     (_UL_(1) <<  9)
+#define PIN_PC27N_CCL_IN4              _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
+#define MUX_PC27N_CCL_IN4              _L_(13)
+#define PINMUX_PC27N_CCL_IN4       ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
+#define PORT_PC27N_CCL_IN4     (_UL_(1) << 27)
+#define PIN_PA10N_CCL_IN5              _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
+#define MUX_PA10N_CCL_IN5              _L_(13)
+#define PINMUX_PA10N_CCL_IN5       ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
+#define PORT_PA10N_CCL_IN5     (_UL_(1) << 10)
+#define PIN_PC28N_CCL_IN5              _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
+#define MUX_PC28N_CCL_IN5              _L_(13)
+#define PINMUX_PC28N_CCL_IN5       ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
+#define PORT_PC28N_CCL_IN5     (_UL_(1) << 28)
+#define PIN_PA22N_CCL_IN6              _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
+#define MUX_PA22N_CCL_IN6              _L_(13)
+#define PINMUX_PA22N_CCL_IN6       ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
+#define PORT_PA22N_CCL_IN6     (_UL_(1) << 22)
+#define PIN_PB06N_CCL_IN6              _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
+#define MUX_PB06N_CCL_IN6              _L_(13)
+#define PINMUX_PB06N_CCL_IN6       ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
+#define PORT_PB06N_CCL_IN6     (_UL_(1) <<  6)
+#define PIN_PA23N_CCL_IN7              _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
+#define MUX_PA23N_CCL_IN7              _L_(13)
+#define PINMUX_PA23N_CCL_IN7       ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
+#define PORT_PA23N_CCL_IN7     (_UL_(1) << 23)
+#define PIN_PB07N_CCL_IN7              _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
+#define MUX_PB07N_CCL_IN7              _L_(13)
+#define PINMUX_PB07N_CCL_IN7       ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
+#define PORT_PB07N_CCL_IN7     (_UL_(1) <<  7)
+#define PIN_PA24N_CCL_IN8              _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
+#define MUX_PA24N_CCL_IN8              _L_(13)
+#define PINMUX_PA24N_CCL_IN8       ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
+#define PORT_PA24N_CCL_IN8     (_UL_(1) << 24)
+#define PIN_PB08N_CCL_IN8              _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
+#define MUX_PB08N_CCL_IN8              _L_(13)
+#define PINMUX_PB08N_CCL_IN8       ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
+#define PORT_PB08N_CCL_IN8     (_UL_(1) <<  8)
+#define PIN_PB14N_CCL_IN9              _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
+#define MUX_PB14N_CCL_IN9              _L_(13)
+#define PINMUX_PB14N_CCL_IN9       ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
+#define PORT_PB14N_CCL_IN9     (_UL_(1) << 14)
+#define PIN_PC20N_CCL_IN9              _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
+#define MUX_PC20N_CCL_IN9              _L_(13)
+#define PINMUX_PC20N_CCL_IN9       ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
+#define PORT_PC20N_CCL_IN9     (_UL_(1) << 20)
+#define PIN_PB15N_CCL_IN10             _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
+#define MUX_PB15N_CCL_IN10             _L_(13)
+#define PINMUX_PB15N_CCL_IN10      ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
+#define PORT_PB15N_CCL_IN10    (_UL_(1) << 15)
+#define PIN_PC21N_CCL_IN10             _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
+#define MUX_PC21N_CCL_IN10             _L_(13)
+#define PINMUX_PC21N_CCL_IN10      ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
+#define PORT_PC21N_CCL_IN10    (_UL_(1) << 21)
+#define PIN_PB10N_CCL_IN11             _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
+#define MUX_PB10N_CCL_IN11             _L_(13)
+#define PINMUX_PB10N_CCL_IN11      ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
+#define PORT_PB10N_CCL_IN11    (_UL_(1) << 10)
+#define PIN_PB16N_CCL_IN11             _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
+#define MUX_PB16N_CCL_IN11             _L_(13)
+#define PINMUX_PB16N_CCL_IN11      ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
+#define PORT_PB16N_CCL_IN11    (_UL_(1) << 16)
+#define PIN_PA07N_CCL_OUT0              _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
+#define MUX_PA07N_CCL_OUT0             _L_(13)
+#define PINMUX_PA07N_CCL_OUT0      ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
+#define PORT_PA07N_CCL_OUT0    (_UL_(1) <<  7)
+#define PIN_PA19N_CCL_OUT0             _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
+#define MUX_PA19N_CCL_OUT0             _L_(13)
+#define PINMUX_PA19N_CCL_OUT0      ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
+#define PORT_PA19N_CCL_OUT0    (_UL_(1) << 19)
+#define PIN_PB02N_CCL_OUT0             _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
+#define MUX_PB02N_CCL_OUT0             _L_(13)
+#define PINMUX_PB02N_CCL_OUT0      ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
+#define PORT_PB02N_CCL_OUT0    (_UL_(1) <<  2)
+#define PIN_PB23N_CCL_OUT0             _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
+#define MUX_PB23N_CCL_OUT0             _L_(13)
+#define PINMUX_PB23N_CCL_OUT0      ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
+#define PORT_PB23N_CCL_OUT0    (_UL_(1) << 23)
+#define PIN_PA11N_CCL_OUT1             _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
+#define MUX_PA11N_CCL_OUT1             _L_(13)
+#define PINMUX_PA11N_CCL_OUT1      ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
+#define PORT_PA11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA31N_CCL_OUT1             _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
+#define MUX_PA31N_CCL_OUT1             _L_(13)
+#define PINMUX_PA31N_CCL_OUT1      ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
+#define PORT_PA31N_CCL_OUT1    (_UL_(1) << 31)
+#define PIN_PB11N_CCL_OUT1             _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
+#define MUX_PB11N_CCL_OUT1             _L_(13)
+#define PINMUX_PB11N_CCL_OUT1      ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
+#define PORT_PB11N_CCL_OUT1    (_UL_(1) << 11)
+#define PIN_PA25N_CCL_OUT2             _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
+#define MUX_PA25N_CCL_OUT2             _L_(13)
+#define PINMUX_PA25N_CCL_OUT2      ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
+#define PORT_PA25N_CCL_OUT2    (_UL_(1) << 25)
+#define PIN_PB09N_CCL_OUT2             _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
+#define MUX_PB09N_CCL_OUT2             _L_(13)
+#define PINMUX_PB09N_CCL_OUT2      ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
+#define PORT_PB09N_CCL_OUT2    (_UL_(1) <<  9)
+#define PIN_PB17N_CCL_OUT3             _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
+#define MUX_PB17N_CCL_OUT3             _L_(13)
+#define PINMUX_PB17N_CCL_OUT3      ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
+#define PORT_PB17N_CCL_OUT3    (_UL_(1) << 17)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA13D_SERCOM4_PAD0         _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PA13D_SERCOM4_PAD0  ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
+#define PORT_PA13D_SERCOM4_PAD0  (_UL_(1) << 13)
+#define PIN_PB08D_SERCOM4_PAD0         _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0          _L_(3)
+#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0  (_UL_(1) <<  8)
+#define PIN_PB12C_SERCOM4_PAD0         _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0          _L_(2)
+#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0  (_UL_(1) << 12)
+#define PIN_PA12D_SERCOM4_PAD1         _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PA12D_SERCOM4_PAD1  ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
+#define PORT_PA12D_SERCOM4_PAD1  (_UL_(1) << 12)
+#define PIN_PB09D_SERCOM4_PAD1         _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1          _L_(3)
+#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1  (_UL_(1) <<  9)
+#define PIN_PB13C_SERCOM4_PAD1         _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1          _L_(2)
+#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1  (_UL_(1) << 13)
+#define PIN_PA14D_SERCOM4_PAD2         _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB10D_SERCOM4_PAD2         _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2          _L_(3)
+#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2  (_UL_(1) << 10)
+#define PIN_PB14C_SERCOM4_PAD2         _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2          _L_(2)
+#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2  (_UL_(1) << 14)
+#define PIN_PB11D_SERCOM4_PAD3         _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3  (_UL_(1) << 11)
+#define PIN_PA15D_SERCOM4_PAD3         _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3          _L_(3)
+#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3  (_UL_(1) << 15)
+#define PIN_PB15C_SERCOM4_PAD3         _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3          _L_(2)
+#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3  (_UL_(1) << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA23D_SERCOM5_PAD0         _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PA23D_SERCOM5_PAD0  ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
+#define PORT_PA23D_SERCOM5_PAD0  (_UL_(1) << 23)
+#define PIN_PB02D_SERCOM5_PAD0         _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0  (_UL_(1) <<  2)
+#define PIN_PB31D_SERCOM5_PAD0         _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD0          _L_(3)
+#define PINMUX_PB31D_SERCOM5_PAD0  ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
+#define PORT_PB31D_SERCOM5_PAD0  (_UL_(1) << 31)
+#define PIN_PB16C_SERCOM5_PAD0         _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0          _L_(2)
+#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0  (_UL_(1) << 16)
+#define PIN_PA22D_SERCOM5_PAD1         _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PA22D_SERCOM5_PAD1  ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
+#define PORT_PA22D_SERCOM5_PAD1  (_UL_(1) << 22)
+#define PIN_PB03D_SERCOM5_PAD1         _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1  (_UL_(1) <<  3)
+#define PIN_PB30D_SERCOM5_PAD1         _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD1          _L_(3)
+#define PINMUX_PB30D_SERCOM5_PAD1  ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
+#define PORT_PB30D_SERCOM5_PAD1  (_UL_(1) << 30)
+#define PIN_PB17C_SERCOM5_PAD1         _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1          _L_(2)
+#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1  (_UL_(1) << 17)
+#define PIN_PA24D_SERCOM5_PAD2         _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2  (_UL_(1) << 24)
+#define PIN_PB00D_SERCOM5_PAD2         _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2  (_UL_(1) <<  0)
+#define PIN_PB22D_SERCOM5_PAD2         _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2          _L_(3)
+#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2  (_UL_(1) << 22)
+#define PIN_PA20C_SERCOM5_PAD2         _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2  (_UL_(1) << 20)
+#define PIN_PB18C_SERCOM5_PAD2         _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2          _L_(2)
+#define PINMUX_PB18C_SERCOM5_PAD2  ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2  (_UL_(1) << 18)
+#define PIN_PA25D_SERCOM5_PAD3         _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3  (_UL_(1) << 25)
+#define PIN_PB01D_SERCOM5_PAD3         _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3  (_UL_(1) <<  1)
+#define PIN_PB23D_SERCOM5_PAD3         _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3          _L_(3)
+#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3  (_UL_(1) << 23)
+#define PIN_PA21C_SERCOM5_PAD3         _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3  (_UL_(1) << 21)
+#define PIN_PB19C_SERCOM5_PAD3         _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3          _L_(2)
+#define PINMUX_PB19C_SERCOM5_PAD3  ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3  (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM6 peripheral ========== */
+#define PIN_PC13D_SERCOM6_PAD0         _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
+#define MUX_PC13D_SERCOM6_PAD0          _L_(3)
+#define PINMUX_PC13D_SERCOM6_PAD0  ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
+#define PORT_PC13D_SERCOM6_PAD0  (_UL_(1) << 13)
+#define PIN_PC16C_SERCOM6_PAD0         _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
+#define MUX_PC16C_SERCOM6_PAD0          _L_(2)
+#define PINMUX_PC16C_SERCOM6_PAD0  ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
+#define PORT_PC16C_SERCOM6_PAD0  (_UL_(1) << 16)
+#define PIN_PC12D_SERCOM6_PAD1         _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
+#define MUX_PC12D_SERCOM6_PAD1          _L_(3)
+#define PINMUX_PC12D_SERCOM6_PAD1  ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
+#define PORT_PC12D_SERCOM6_PAD1  (_UL_(1) << 12)
+#define PIN_PC05C_SERCOM6_PAD1         _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
+#define MUX_PC05C_SERCOM6_PAD1          _L_(2)
+#define PINMUX_PC05C_SERCOM6_PAD1  ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
+#define PORT_PC05C_SERCOM6_PAD1  (_UL_(1) <<  5)
+#define PIN_PC17C_SERCOM6_PAD1         _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
+#define MUX_PC17C_SERCOM6_PAD1          _L_(2)
+#define PINMUX_PC17C_SERCOM6_PAD1  ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
+#define PORT_PC17C_SERCOM6_PAD1  (_UL_(1) << 17)
+#define PIN_PC14D_SERCOM6_PAD2         _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
+#define MUX_PC14D_SERCOM6_PAD2          _L_(3)
+#define PINMUX_PC14D_SERCOM6_PAD2  ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
+#define PORT_PC14D_SERCOM6_PAD2  (_UL_(1) << 14)
+#define PIN_PC06C_SERCOM6_PAD2         _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
+#define MUX_PC06C_SERCOM6_PAD2          _L_(2)
+#define PINMUX_PC06C_SERCOM6_PAD2  ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
+#define PORT_PC06C_SERCOM6_PAD2  (_UL_(1) <<  6)
+#define PIN_PC10C_SERCOM6_PAD2         _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM6_PAD2          _L_(2)
+#define PINMUX_PC10C_SERCOM6_PAD2  ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
+#define PORT_PC10C_SERCOM6_PAD2  (_UL_(1) << 10)
+#define PIN_PC18C_SERCOM6_PAD2         _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
+#define MUX_PC18C_SERCOM6_PAD2          _L_(2)
+#define PINMUX_PC18C_SERCOM6_PAD2  ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
+#define PORT_PC18C_SERCOM6_PAD2  (_UL_(1) << 18)
+#define PIN_PC15D_SERCOM6_PAD3         _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
+#define MUX_PC15D_SERCOM6_PAD3          _L_(3)
+#define PINMUX_PC15D_SERCOM6_PAD3  ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
+#define PORT_PC15D_SERCOM6_PAD3  (_UL_(1) << 15)
+#define PIN_PC07C_SERCOM6_PAD3         _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
+#define MUX_PC07C_SERCOM6_PAD3          _L_(2)
+#define PINMUX_PC07C_SERCOM6_PAD3  ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
+#define PORT_PC07C_SERCOM6_PAD3  (_UL_(1) <<  7)
+#define PIN_PC11C_SERCOM6_PAD3         _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM6_PAD3          _L_(2)
+#define PINMUX_PC11C_SERCOM6_PAD3  ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
+#define PORT_PC11C_SERCOM6_PAD3  (_UL_(1) << 11)
+#define PIN_PC19C_SERCOM6_PAD3         _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
+#define MUX_PC19C_SERCOM6_PAD3          _L_(2)
+#define PINMUX_PC19C_SERCOM6_PAD3  ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
+#define PORT_PC19C_SERCOM6_PAD3  (_UL_(1) << 19)
+/* ========== PORT definition for SERCOM7 peripheral ========== */
+#define PIN_PB21D_SERCOM7_PAD0         _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
+#define MUX_PB21D_SERCOM7_PAD0          _L_(3)
+#define PINMUX_PB21D_SERCOM7_PAD0  ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
+#define PORT_PB21D_SERCOM7_PAD0  (_UL_(1) << 21)
+#define PIN_PB30C_SERCOM7_PAD0         _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM7_PAD0          _L_(2)
+#define PINMUX_PB30C_SERCOM7_PAD0  ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
+#define PORT_PB30C_SERCOM7_PAD0  (_UL_(1) << 30)
+#define PIN_PC12C_SERCOM7_PAD0         _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM7_PAD0          _L_(2)
+#define PINMUX_PC12C_SERCOM7_PAD0  ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
+#define PORT_PC12C_SERCOM7_PAD0  (_UL_(1) << 12)
+#define PIN_PB20D_SERCOM7_PAD1         _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
+#define MUX_PB20D_SERCOM7_PAD1          _L_(3)
+#define PINMUX_PB20D_SERCOM7_PAD1  ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
+#define PORT_PB20D_SERCOM7_PAD1  (_UL_(1) << 20)
+#define PIN_PB31C_SERCOM7_PAD1         _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM7_PAD1          _L_(2)
+#define PINMUX_PB31C_SERCOM7_PAD1  ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
+#define PORT_PB31C_SERCOM7_PAD1  (_UL_(1) << 31)
+#define PIN_PC13C_SERCOM7_PAD1         _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM7_PAD1          _L_(2)
+#define PINMUX_PC13C_SERCOM7_PAD1  ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
+#define PORT_PC13C_SERCOM7_PAD1  (_UL_(1) << 13)
+#define PIN_PB18D_SERCOM7_PAD2         _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM7_PAD2          _L_(3)
+#define PINMUX_PB18D_SERCOM7_PAD2  ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
+#define PORT_PB18D_SERCOM7_PAD2  (_UL_(1) << 18)
+#define PIN_PC10D_SERCOM7_PAD2         _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
+#define MUX_PC10D_SERCOM7_PAD2          _L_(3)
+#define PINMUX_PC10D_SERCOM7_PAD2  ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
+#define PORT_PC10D_SERCOM7_PAD2  (_UL_(1) << 10)
+#define PIN_PC14C_SERCOM7_PAD2         _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
+#define MUX_PC14C_SERCOM7_PAD2          _L_(2)
+#define PINMUX_PC14C_SERCOM7_PAD2  ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
+#define PORT_PC14C_SERCOM7_PAD2  (_UL_(1) << 14)
+#define PIN_PA30C_SERCOM7_PAD2         _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
+#define MUX_PA30C_SERCOM7_PAD2          _L_(2)
+#define PINMUX_PA30C_SERCOM7_PAD2  ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
+#define PORT_PA30C_SERCOM7_PAD2  (_UL_(1) << 30)
+#define PIN_PB19D_SERCOM7_PAD3         _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM7_PAD3          _L_(3)
+#define PINMUX_PB19D_SERCOM7_PAD3  ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
+#define PORT_PB19D_SERCOM7_PAD3  (_UL_(1) << 19)
+#define PIN_PC11D_SERCOM7_PAD3         _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
+#define MUX_PC11D_SERCOM7_PAD3          _L_(3)
+#define PINMUX_PC11D_SERCOM7_PAD3  ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
+#define PORT_PC11D_SERCOM7_PAD3  (_UL_(1) << 11)
+#define PIN_PC15C_SERCOM7_PAD3         _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
+#define MUX_PC15C_SERCOM7_PAD3          _L_(2)
+#define PINMUX_PC15C_SERCOM7_PAD3  ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
+#define PORT_PC15C_SERCOM7_PAD3  (_UL_(1) << 15)
+#define PIN_PA31C_SERCOM7_PAD3         _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
+#define MUX_PA31C_SERCOM7_PAD3          _L_(2)
+#define PINMUX_PA31C_SERCOM7_PAD3  ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
+#define PORT_PA31C_SERCOM7_PAD3  (_UL_(1) << 31)
+/* ========== PORT definition for TCC4 peripheral ========== */
+#define PIN_PB14F_TCC4_WO0             _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
+#define MUX_PB14F_TCC4_WO0              _L_(5)
+#define PINMUX_PB14F_TCC4_WO0      ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
+#define PORT_PB14F_TCC4_WO0    (_UL_(1) << 14)
+#define PIN_PB30F_TCC4_WO0             _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
+#define MUX_PB30F_TCC4_WO0              _L_(5)
+#define PINMUX_PB30F_TCC4_WO0      ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
+#define PORT_PB30F_TCC4_WO0    (_UL_(1) << 30)
+#define PIN_PB15F_TCC4_WO1             _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
+#define MUX_PB15F_TCC4_WO1              _L_(5)
+#define PINMUX_PB15F_TCC4_WO1      ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
+#define PORT_PB15F_TCC4_WO1    (_UL_(1) << 15)
+#define PIN_PB31F_TCC4_WO1             _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
+#define MUX_PB31F_TCC4_WO1              _L_(5)
+#define PINMUX_PB31F_TCC4_WO1      ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
+#define PORT_PB31F_TCC4_WO1    (_UL_(1) << 31)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PA30E_TC6_WO0              _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TC6_WO0               _L_(4)
+#define PINMUX_PA30E_TC6_WO0       ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
+#define PORT_PA30E_TC6_WO0     (_UL_(1) << 30)
+#define PIN_PB02E_TC6_WO0              _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0               _L_(4)
+#define PINMUX_PB02E_TC6_WO0       ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0     (_UL_(1) <<  2)
+#define PIN_PB16E_TC6_WO0              _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0               _L_(4)
+#define PINMUX_PB16E_TC6_WO0       ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0     (_UL_(1) << 16)
+#define PIN_PA31E_TC6_WO1              _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TC6_WO1               _L_(4)
+#define PINMUX_PA31E_TC6_WO1       ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
+#define PORT_PA31E_TC6_WO1     (_UL_(1) << 31)
+#define PIN_PB03E_TC6_WO1              _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1               _L_(4)
+#define PINMUX_PB03E_TC6_WO1       ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1     (_UL_(1) <<  3)
+#define PIN_PB17E_TC6_WO1              _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1               _L_(4)
+#define PINMUX_PB17E_TC6_WO1       ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1     (_UL_(1) << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0              _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0               _L_(4)
+#define PINMUX_PA20E_TC7_WO0       ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0     (_UL_(1) << 20)
+#define PIN_PB00E_TC7_WO0              _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0               _L_(4)
+#define PINMUX_PB00E_TC7_WO0       ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0     (_UL_(1) <<  0)
+#define PIN_PB22E_TC7_WO0              _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0               _L_(4)
+#define PINMUX_PB22E_TC7_WO0       ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0     (_UL_(1) << 22)
+#define PIN_PA21E_TC7_WO1              _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1               _L_(4)
+#define PINMUX_PA21E_TC7_WO1       ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1     (_UL_(1) << 21)
+#define PIN_PB01E_TC7_WO1              _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1               _L_(4)
+#define PINMUX_PB01E_TC7_WO1       ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1     (_UL_(1) <<  1)
+#define PIN_PB23E_TC7_WO1              _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1               _L_(4)
+#define PINMUX_PB23E_TC7_WO1       ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1     (_UL_(1) << 23)
+/* ========== PORT definition for ADC0 peripheral ========== */
+#define PIN_PA02B_ADC0_AIN0             _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC0_AIN0             _L_(1)
+#define PINMUX_PA02B_ADC0_AIN0     ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
+#define PORT_PA02B_ADC0_AIN0   (_UL_(1) <<  2)
+#define PIN_PA03B_ADC0_AIN1             _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC0_AIN1             _L_(1)
+#define PINMUX_PA03B_ADC0_AIN1     ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
+#define PORT_PA03B_ADC0_AIN1   (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_AIN2            _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC0_AIN2             _L_(1)
+#define PINMUX_PB08B_ADC0_AIN2     ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
+#define PORT_PB08B_ADC0_AIN2   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_AIN3            _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC0_AIN3             _L_(1)
+#define PINMUX_PB09B_ADC0_AIN3     ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
+#define PORT_PB09B_ADC0_AIN3   (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_AIN4             _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC0_AIN4             _L_(1)
+#define PINMUX_PA04B_ADC0_AIN4     ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
+#define PORT_PA04B_ADC0_AIN4   (_UL_(1) <<  4)
+#define PIN_PA05B_ADC0_AIN5             _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC0_AIN5             _L_(1)
+#define PINMUX_PA05B_ADC0_AIN5     ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
+#define PORT_PA05B_ADC0_AIN5   (_UL_(1) <<  5)
+#define PIN_PA06B_ADC0_AIN6             _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC0_AIN6             _L_(1)
+#define PINMUX_PA06B_ADC0_AIN6     ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
+#define PORT_PA06B_ADC0_AIN6   (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_AIN7             _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC0_AIN7             _L_(1)
+#define PINMUX_PA07B_ADC0_AIN7     ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
+#define PORT_PA07B_ADC0_AIN7   (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_AIN8             _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
+#define MUX_PA08B_ADC0_AIN8             _L_(1)
+#define PINMUX_PA08B_ADC0_AIN8     ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
+#define PORT_PA08B_ADC0_AIN8   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_AIN9             _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
+#define MUX_PA09B_ADC0_AIN9             _L_(1)
+#define PINMUX_PA09B_ADC0_AIN9     ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
+#define PORT_PA09B_ADC0_AIN9   (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_AIN10           _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
+#define MUX_PA10B_ADC0_AIN10            _L_(1)
+#define PINMUX_PA10B_ADC0_AIN10    ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
+#define PORT_PA10B_ADC0_AIN10  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_AIN11           _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
+#define MUX_PA11B_ADC0_AIN11            _L_(1)
+#define PINMUX_PA11B_ADC0_AIN11    ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
+#define PORT_PA11B_ADC0_AIN11  (_UL_(1) << 11)
+#define PIN_PB00B_ADC0_AIN12           _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
+#define MUX_PB00B_ADC0_AIN12            _L_(1)
+#define PINMUX_PB00B_ADC0_AIN12    ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
+#define PORT_PB00B_ADC0_AIN12  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_AIN13           _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
+#define MUX_PB01B_ADC0_AIN13            _L_(1)
+#define PINMUX_PB01B_ADC0_AIN13    ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
+#define PORT_PB01B_ADC0_AIN13  (_UL_(1) <<  1)
+#define PIN_PB02B_ADC0_AIN14           _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
+#define MUX_PB02B_ADC0_AIN14            _L_(1)
+#define PINMUX_PB02B_ADC0_AIN14    ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
+#define PORT_PB02B_ADC0_AIN14  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_AIN15           _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
+#define MUX_PB03B_ADC0_AIN15            _L_(1)
+#define PINMUX_PB03B_ADC0_AIN15    ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
+#define PORT_PB03B_ADC0_AIN15  (_UL_(1) <<  3)
+#define PIN_PA03O_ADC0_DRV0             _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
+#define MUX_PA03O_ADC0_DRV0            _L_(14)
+#define PINMUX_PA03O_ADC0_DRV0     ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
+#define PORT_PA03O_ADC0_DRV0   (_UL_(1) <<  3)
+#define PIN_PB08O_ADC0_DRV1            _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
+#define MUX_PB08O_ADC0_DRV1            _L_(14)
+#define PINMUX_PB08O_ADC0_DRV1     ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
+#define PORT_PB08O_ADC0_DRV1   (_UL_(1) <<  8)
+#define PIN_PB09O_ADC0_DRV2            _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
+#define MUX_PB09O_ADC0_DRV2            _L_(14)
+#define PINMUX_PB09O_ADC0_DRV2     ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
+#define PORT_PB09O_ADC0_DRV2   (_UL_(1) <<  9)
+#define PIN_PA04O_ADC0_DRV3             _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
+#define MUX_PA04O_ADC0_DRV3            _L_(14)
+#define PINMUX_PA04O_ADC0_DRV3     ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
+#define PORT_PA04O_ADC0_DRV3   (_UL_(1) <<  4)
+#define PIN_PA06O_ADC0_DRV4             _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
+#define MUX_PA06O_ADC0_DRV4            _L_(14)
+#define PINMUX_PA06O_ADC0_DRV4     ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
+#define PORT_PA06O_ADC0_DRV4   (_UL_(1) <<  6)
+#define PIN_PA07O_ADC0_DRV5             _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
+#define MUX_PA07O_ADC0_DRV5            _L_(14)
+#define PINMUX_PA07O_ADC0_DRV5     ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
+#define PORT_PA07O_ADC0_DRV5   (_UL_(1) <<  7)
+#define PIN_PA08O_ADC0_DRV6             _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
+#define MUX_PA08O_ADC0_DRV6            _L_(14)
+#define PINMUX_PA08O_ADC0_DRV6     ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
+#define PORT_PA08O_ADC0_DRV6   (_UL_(1) <<  8)
+#define PIN_PA09O_ADC0_DRV7             _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
+#define MUX_PA09O_ADC0_DRV7            _L_(14)
+#define PINMUX_PA09O_ADC0_DRV7     ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
+#define PORT_PA09O_ADC0_DRV7   (_UL_(1) <<  9)
+#define PIN_PA10O_ADC0_DRV8            _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
+#define MUX_PA10O_ADC0_DRV8            _L_(14)
+#define PINMUX_PA10O_ADC0_DRV8     ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
+#define PORT_PA10O_ADC0_DRV8   (_UL_(1) << 10)
+#define PIN_PA11O_ADC0_DRV9            _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
+#define MUX_PA11O_ADC0_DRV9            _L_(14)
+#define PINMUX_PA11O_ADC0_DRV9     ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
+#define PORT_PA11O_ADC0_DRV9   (_UL_(1) << 11)
+#define PIN_PA16O_ADC0_DRV10           _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
+#define MUX_PA16O_ADC0_DRV10           _L_(14)
+#define PINMUX_PA16O_ADC0_DRV10    ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
+#define PORT_PA16O_ADC0_DRV10  (_UL_(1) << 16)
+#define PIN_PA17O_ADC0_DRV11           _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
+#define MUX_PA17O_ADC0_DRV11           _L_(14)
+#define PINMUX_PA17O_ADC0_DRV11    ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
+#define PORT_PA17O_ADC0_DRV11  (_UL_(1) << 17)
+#define PIN_PA18O_ADC0_DRV12           _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
+#define MUX_PA18O_ADC0_DRV12           _L_(14)
+#define PINMUX_PA18O_ADC0_DRV12    ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
+#define PORT_PA18O_ADC0_DRV12  (_UL_(1) << 18)
+#define PIN_PA19O_ADC0_DRV13           _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
+#define MUX_PA19O_ADC0_DRV13           _L_(14)
+#define PINMUX_PA19O_ADC0_DRV13    ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
+#define PORT_PA19O_ADC0_DRV13  (_UL_(1) << 19)
+#define PIN_PA20O_ADC0_DRV14           _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
+#define MUX_PA20O_ADC0_DRV14           _L_(14)
+#define PINMUX_PA20O_ADC0_DRV14    ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
+#define PORT_PA20O_ADC0_DRV14  (_UL_(1) << 20)
+#define PIN_PA21O_ADC0_DRV15           _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
+#define MUX_PA21O_ADC0_DRV15           _L_(14)
+#define PINMUX_PA21O_ADC0_DRV15    ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
+#define PORT_PA21O_ADC0_DRV15  (_UL_(1) << 21)
+#define PIN_PA22O_ADC0_DRV16           _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
+#define MUX_PA22O_ADC0_DRV16           _L_(14)
+#define PINMUX_PA22O_ADC0_DRV16    ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
+#define PORT_PA22O_ADC0_DRV16  (_UL_(1) << 22)
+#define PIN_PA23O_ADC0_DRV17           _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
+#define MUX_PA23O_ADC0_DRV17           _L_(14)
+#define PINMUX_PA23O_ADC0_DRV17    ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
+#define PORT_PA23O_ADC0_DRV17  (_UL_(1) << 23)
+#define PIN_PA27O_ADC0_DRV18           _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
+#define MUX_PA27O_ADC0_DRV18           _L_(14)
+#define PINMUX_PA27O_ADC0_DRV18    ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
+#define PORT_PA27O_ADC0_DRV18  (_UL_(1) << 27)
+#define PIN_PA30O_ADC0_DRV19           _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
+#define MUX_PA30O_ADC0_DRV19           _L_(14)
+#define PINMUX_PA30O_ADC0_DRV19    ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
+#define PORT_PA30O_ADC0_DRV19  (_UL_(1) << 30)
+#define PIN_PB02O_ADC0_DRV20           _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
+#define MUX_PB02O_ADC0_DRV20           _L_(14)
+#define PINMUX_PB02O_ADC0_DRV20    ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
+#define PORT_PB02O_ADC0_DRV20  (_UL_(1) <<  2)
+#define PIN_PB03O_ADC0_DRV21           _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
+#define MUX_PB03O_ADC0_DRV21           _L_(14)
+#define PINMUX_PB03O_ADC0_DRV21    ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
+#define PORT_PB03O_ADC0_DRV21  (_UL_(1) <<  3)
+#define PIN_PB04O_ADC0_DRV22           _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
+#define MUX_PB04O_ADC0_DRV22           _L_(14)
+#define PINMUX_PB04O_ADC0_DRV22    ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
+#define PORT_PB04O_ADC0_DRV22  (_UL_(1) <<  4)
+#define PIN_PB05O_ADC0_DRV23           _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
+#define MUX_PB05O_ADC0_DRV23           _L_(14)
+#define PINMUX_PB05O_ADC0_DRV23    ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
+#define PORT_PB05O_ADC0_DRV23  (_UL_(1) <<  5)
+#define PIN_PB06O_ADC0_DRV24           _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
+#define MUX_PB06O_ADC0_DRV24           _L_(14)
+#define PINMUX_PB06O_ADC0_DRV24    ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
+#define PORT_PB06O_ADC0_DRV24  (_UL_(1) <<  6)
+#define PIN_PB07O_ADC0_DRV25           _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
+#define MUX_PB07O_ADC0_DRV25           _L_(14)
+#define PINMUX_PB07O_ADC0_DRV25    ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
+#define PORT_PB07O_ADC0_DRV25  (_UL_(1) <<  7)
+#define PIN_PB12O_ADC0_DRV26           _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
+#define MUX_PB12O_ADC0_DRV26           _L_(14)
+#define PINMUX_PB12O_ADC0_DRV26    ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
+#define PORT_PB12O_ADC0_DRV26  (_UL_(1) << 12)
+#define PIN_PB13O_ADC0_DRV27           _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
+#define MUX_PB13O_ADC0_DRV27           _L_(14)
+#define PINMUX_PB13O_ADC0_DRV27    ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
+#define PORT_PB13O_ADC0_DRV27  (_UL_(1) << 13)
+#define PIN_PB14O_ADC0_DRV28           _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
+#define MUX_PB14O_ADC0_DRV28           _L_(14)
+#define PINMUX_PB14O_ADC0_DRV28    ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
+#define PORT_PB14O_ADC0_DRV28  (_UL_(1) << 14)
+#define PIN_PB15O_ADC0_DRV29           _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
+#define MUX_PB15O_ADC0_DRV29           _L_(14)
+#define PINMUX_PB15O_ADC0_DRV29    ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
+#define PORT_PB15O_ADC0_DRV29  (_UL_(1) << 15)
+#define PIN_PB00O_ADC0_DRV30           _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
+#define MUX_PB00O_ADC0_DRV30           _L_(14)
+#define PINMUX_PB00O_ADC0_DRV30    ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
+#define PORT_PB00O_ADC0_DRV30  (_UL_(1) <<  0)
+#define PIN_PB01O_ADC0_DRV31           _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
+#define MUX_PB01O_ADC0_DRV31           _L_(14)
+#define PINMUX_PB01O_ADC0_DRV31    ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
+#define PORT_PB01O_ADC0_DRV31  (_UL_(1) <<  1)
+#define PIN_PA03B_ADC0_PTCXY0           _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
+#define MUX_PA03B_ADC0_PTCXY0           _L_(1)
+#define PINMUX_PA03B_ADC0_PTCXY0   ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
+#define PORT_PA03B_ADC0_PTCXY0  (_UL_(1) <<  3)
+#define PIN_PB08B_ADC0_PTCXY1          _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
+#define MUX_PB08B_ADC0_PTCXY1           _L_(1)
+#define PINMUX_PB08B_ADC0_PTCXY1   ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
+#define PORT_PB08B_ADC0_PTCXY1  (_UL_(1) <<  8)
+#define PIN_PB09B_ADC0_PTCXY2          _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
+#define MUX_PB09B_ADC0_PTCXY2           _L_(1)
+#define PINMUX_PB09B_ADC0_PTCXY2   ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
+#define PORT_PB09B_ADC0_PTCXY2  (_UL_(1) <<  9)
+#define PIN_PA04B_ADC0_PTCXY3           _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
+#define MUX_PA04B_ADC0_PTCXY3           _L_(1)
+#define PINMUX_PA04B_ADC0_PTCXY3   ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
+#define PORT_PA04B_ADC0_PTCXY3  (_UL_(1) <<  4)
+#define PIN_PA06B_ADC0_PTCXY4           _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
+#define MUX_PA06B_ADC0_PTCXY4           _L_(1)
+#define PINMUX_PA06B_ADC0_PTCXY4   ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
+#define PORT_PA06B_ADC0_PTCXY4  (_UL_(1) <<  6)
+#define PIN_PA07B_ADC0_PTCXY5           _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
+#define MUX_PA07B_ADC0_PTCXY5           _L_(1)
+#define PINMUX_PA07B_ADC0_PTCXY5   ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
+#define PORT_PA07B_ADC0_PTCXY5  (_UL_(1) <<  7)
+#define PIN_PA08B_ADC0_PTCXY6           _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
+#define MUX_PA08B_ADC0_PTCXY6           _L_(1)
+#define PINMUX_PA08B_ADC0_PTCXY6   ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
+#define PORT_PA08B_ADC0_PTCXY6  (_UL_(1) <<  8)
+#define PIN_PA09B_ADC0_PTCXY7           _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
+#define MUX_PA09B_ADC0_PTCXY7           _L_(1)
+#define PINMUX_PA09B_ADC0_PTCXY7   ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
+#define PORT_PA09B_ADC0_PTCXY7  (_UL_(1) <<  9)
+#define PIN_PA10B_ADC0_PTCXY8          _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
+#define MUX_PA10B_ADC0_PTCXY8           _L_(1)
+#define PINMUX_PA10B_ADC0_PTCXY8   ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
+#define PORT_PA10B_ADC0_PTCXY8  (_UL_(1) << 10)
+#define PIN_PA11B_ADC0_PTCXY9          _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
+#define MUX_PA11B_ADC0_PTCXY9           _L_(1)
+#define PINMUX_PA11B_ADC0_PTCXY9   ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
+#define PORT_PA11B_ADC0_PTCXY9  (_UL_(1) << 11)
+#define PIN_PA16B_ADC0_PTCXY10         _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
+#define MUX_PA16B_ADC0_PTCXY10          _L_(1)
+#define PINMUX_PA16B_ADC0_PTCXY10  ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
+#define PORT_PA16B_ADC0_PTCXY10  (_UL_(1) << 16)
+#define PIN_PA17B_ADC0_PTCXY11         _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
+#define MUX_PA17B_ADC0_PTCXY11          _L_(1)
+#define PINMUX_PA17B_ADC0_PTCXY11  ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
+#define PORT_PA17B_ADC0_PTCXY11  (_UL_(1) << 17)
+#define PIN_PA18B_ADC0_PTCXY12         _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */
+#define MUX_PA18B_ADC0_PTCXY12          _L_(1)
+#define PINMUX_PA18B_ADC0_PTCXY12  ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
+#define PORT_PA18B_ADC0_PTCXY12  (_UL_(1) << 18)
+#define PIN_PA19B_ADC0_PTCXY13         _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
+#define MUX_PA19B_ADC0_PTCXY13          _L_(1)
+#define PINMUX_PA19B_ADC0_PTCXY13  ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
+#define PORT_PA19B_ADC0_PTCXY13  (_UL_(1) << 19)
+#define PIN_PA20B_ADC0_PTCXY14         _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
+#define MUX_PA20B_ADC0_PTCXY14          _L_(1)
+#define PINMUX_PA20B_ADC0_PTCXY14  ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
+#define PORT_PA20B_ADC0_PTCXY14  (_UL_(1) << 20)
+#define PIN_PA21B_ADC0_PTCXY15         _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
+#define MUX_PA21B_ADC0_PTCXY15          _L_(1)
+#define PINMUX_PA21B_ADC0_PTCXY15  ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
+#define PORT_PA21B_ADC0_PTCXY15  (_UL_(1) << 21)
+#define PIN_PA22B_ADC0_PTCXY16         _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
+#define MUX_PA22B_ADC0_PTCXY16          _L_(1)
+#define PINMUX_PA22B_ADC0_PTCXY16  ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
+#define PORT_PA22B_ADC0_PTCXY16  (_UL_(1) << 22)
+#define PIN_PA23B_ADC0_PTCXY17         _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
+#define MUX_PA23B_ADC0_PTCXY17          _L_(1)
+#define PINMUX_PA23B_ADC0_PTCXY17  ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
+#define PORT_PA23B_ADC0_PTCXY17  (_UL_(1) << 23)
+#define PIN_PA27B_ADC0_PTCXY18         _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
+#define MUX_PA27B_ADC0_PTCXY18          _L_(1)
+#define PINMUX_PA27B_ADC0_PTCXY18  ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
+#define PORT_PA27B_ADC0_PTCXY18  (_UL_(1) << 27)
+#define PIN_PA30B_ADC0_PTCXY19         _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
+#define MUX_PA30B_ADC0_PTCXY19          _L_(1)
+#define PINMUX_PA30B_ADC0_PTCXY19  ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
+#define PORT_PA30B_ADC0_PTCXY19  (_UL_(1) << 30)
+#define PIN_PB02B_ADC0_PTCXY20         _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
+#define MUX_PB02B_ADC0_PTCXY20          _L_(1)
+#define PINMUX_PB02B_ADC0_PTCXY20  ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
+#define PORT_PB02B_ADC0_PTCXY20  (_UL_(1) <<  2)
+#define PIN_PB03B_ADC0_PTCXY21         _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
+#define MUX_PB03B_ADC0_PTCXY21          _L_(1)
+#define PINMUX_PB03B_ADC0_PTCXY21  ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
+#define PORT_PB03B_ADC0_PTCXY21  (_UL_(1) <<  3)
+#define PIN_PB04B_ADC0_PTCXY22         _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
+#define MUX_PB04B_ADC0_PTCXY22          _L_(1)
+#define PINMUX_PB04B_ADC0_PTCXY22  ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
+#define PORT_PB04B_ADC0_PTCXY22  (_UL_(1) <<  4)
+#define PIN_PB05B_ADC0_PTCXY23         _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
+#define MUX_PB05B_ADC0_PTCXY23          _L_(1)
+#define PINMUX_PB05B_ADC0_PTCXY23  ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
+#define PORT_PB05B_ADC0_PTCXY23  (_UL_(1) <<  5)
+#define PIN_PB06B_ADC0_PTCXY24         _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
+#define MUX_PB06B_ADC0_PTCXY24          _L_(1)
+#define PINMUX_PB06B_ADC0_PTCXY24  ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
+#define PORT_PB06B_ADC0_PTCXY24  (_UL_(1) <<  6)
+#define PIN_PB07B_ADC0_PTCXY25         _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
+#define MUX_PB07B_ADC0_PTCXY25          _L_(1)
+#define PINMUX_PB07B_ADC0_PTCXY25  ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
+#define PORT_PB07B_ADC0_PTCXY25  (_UL_(1) <<  7)
+#define PIN_PB12B_ADC0_PTCXY26         _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
+#define MUX_PB12B_ADC0_PTCXY26          _L_(1)
+#define PINMUX_PB12B_ADC0_PTCXY26  ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
+#define PORT_PB12B_ADC0_PTCXY26  (_UL_(1) << 12)
+#define PIN_PB13B_ADC0_PTCXY27         _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
+#define MUX_PB13B_ADC0_PTCXY27          _L_(1)
+#define PINMUX_PB13B_ADC0_PTCXY27  ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
+#define PORT_PB13B_ADC0_PTCXY27  (_UL_(1) << 13)
+#define PIN_PB14B_ADC0_PTCXY28         _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
+#define MUX_PB14B_ADC0_PTCXY28          _L_(1)
+#define PINMUX_PB14B_ADC0_PTCXY28  ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
+#define PORT_PB14B_ADC0_PTCXY28  (_UL_(1) << 14)
+#define PIN_PB15B_ADC0_PTCXY29         _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
+#define MUX_PB15B_ADC0_PTCXY29          _L_(1)
+#define PINMUX_PB15B_ADC0_PTCXY29  ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
+#define PORT_PB15B_ADC0_PTCXY29  (_UL_(1) << 15)
+#define PIN_PB00B_ADC0_PTCXY30         _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
+#define MUX_PB00B_ADC0_PTCXY30          _L_(1)
+#define PINMUX_PB00B_ADC0_PTCXY30  ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
+#define PORT_PB00B_ADC0_PTCXY30  (_UL_(1) <<  0)
+#define PIN_PB01B_ADC0_PTCXY31         _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
+#define MUX_PB01B_ADC0_PTCXY31          _L_(1)
+#define PINMUX_PB01B_ADC0_PTCXY31  ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
+#define PORT_PB01B_ADC0_PTCXY31  (_UL_(1) <<  1)
+/* ========== PORT definition for ADC1 peripheral ========== */
+#define PIN_PB08B_ADC1_AIN0            _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
+#define MUX_PB08B_ADC1_AIN0             _L_(1)
+#define PINMUX_PB08B_ADC1_AIN0     ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
+#define PORT_PB08B_ADC1_AIN0   (_UL_(1) <<  8)
+#define PIN_PB09B_ADC1_AIN1            _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
+#define MUX_PB09B_ADC1_AIN1             _L_(1)
+#define PINMUX_PB09B_ADC1_AIN1     ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
+#define PORT_PB09B_ADC1_AIN1   (_UL_(1) <<  9)
+#define PIN_PA08B_ADC1_AIN2             _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
+#define MUX_PA08B_ADC1_AIN2             _L_(1)
+#define PINMUX_PA08B_ADC1_AIN2     ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
+#define PORT_PA08B_ADC1_AIN2   (_UL_(1) <<  8)
+#define PIN_PA09B_ADC1_AIN3             _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
+#define MUX_PA09B_ADC1_AIN3             _L_(1)
+#define PINMUX_PA09B_ADC1_AIN3     ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
+#define PORT_PA09B_ADC1_AIN3   (_UL_(1) <<  9)
+#define PIN_PC02B_ADC1_AIN4            _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
+#define MUX_PC02B_ADC1_AIN4             _L_(1)
+#define PINMUX_PC02B_ADC1_AIN4     ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
+#define PORT_PC02B_ADC1_AIN4   (_UL_(1) <<  2)
+#define PIN_PC03B_ADC1_AIN5            _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
+#define MUX_PC03B_ADC1_AIN5             _L_(1)
+#define PINMUX_PC03B_ADC1_AIN5     ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
+#define PORT_PC03B_ADC1_AIN5   (_UL_(1) <<  3)
+#define PIN_PB04B_ADC1_AIN6            _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
+#define MUX_PB04B_ADC1_AIN6             _L_(1)
+#define PINMUX_PB04B_ADC1_AIN6     ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
+#define PORT_PB04B_ADC1_AIN6   (_UL_(1) <<  4)
+#define PIN_PB05B_ADC1_AIN7            _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
+#define MUX_PB05B_ADC1_AIN7             _L_(1)
+#define PINMUX_PB05B_ADC1_AIN7     ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
+#define PORT_PB05B_ADC1_AIN7   (_UL_(1) <<  5)
+#define PIN_PB06B_ADC1_AIN8            _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
+#define MUX_PB06B_ADC1_AIN8             _L_(1)
+#define PINMUX_PB06B_ADC1_AIN8     ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
+#define PORT_PB06B_ADC1_AIN8   (_UL_(1) <<  6)
+#define PIN_PB07B_ADC1_AIN9            _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
+#define MUX_PB07B_ADC1_AIN9             _L_(1)
+#define PINMUX_PB07B_ADC1_AIN9     ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
+#define PORT_PB07B_ADC1_AIN9   (_UL_(1) <<  7)
+#define PIN_PC00B_ADC1_AIN10           _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
+#define MUX_PC00B_ADC1_AIN10            _L_(1)
+#define PINMUX_PC00B_ADC1_AIN10    ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
+#define PORT_PC00B_ADC1_AIN10  (_UL_(1) <<  0)
+#define PIN_PC01B_ADC1_AIN11           _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
+#define MUX_PC01B_ADC1_AIN11            _L_(1)
+#define PINMUX_PC01B_ADC1_AIN11    ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
+#define PORT_PC01B_ADC1_AIN11  (_UL_(1) <<  1)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT0             _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT0             _L_(1)
+#define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
+#define PORT_PA02B_DAC_VOUT0   (_UL_(1) <<  2)
+#define PIN_PA05B_DAC_VOUT1             _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
+#define MUX_PA05B_DAC_VOUT1             _L_(1)
+#define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
+#define PORT_PA05B_DAC_VOUT1   (_UL_(1) <<  5)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA09J_I2S_FS0               _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
+#define MUX_PA09J_I2S_FS0               _L_(9)
+#define PINMUX_PA09J_I2S_FS0       ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
+#define PORT_PA09J_I2S_FS0     (_UL_(1) <<  9)
+#define PIN_PA20J_I2S_FS0              _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
+#define MUX_PA20J_I2S_FS0               _L_(9)
+#define PINMUX_PA20J_I2S_FS0       ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
+#define PORT_PA20J_I2S_FS0     (_UL_(1) << 20)
+#define PIN_PA23J_I2S_FS1              _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
+#define MUX_PA23J_I2S_FS1               _L_(9)
+#define PINMUX_PA23J_I2S_FS1       ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
+#define PORT_PA23J_I2S_FS1     (_UL_(1) << 23)
+#define PIN_PB11J_I2S_FS1              _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
+#define MUX_PB11J_I2S_FS1               _L_(9)
+#define PINMUX_PB11J_I2S_FS1       ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
+#define PORT_PB11J_I2S_FS1     (_UL_(1) << 11)
+#define PIN_PA08J_I2S_MCK0              _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
+#define MUX_PA08J_I2S_MCK0              _L_(9)
+#define PINMUX_PA08J_I2S_MCK0      ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
+#define PORT_PA08J_I2S_MCK0    (_UL_(1) <<  8)
+#define PIN_PB17J_I2S_MCK0             _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
+#define MUX_PB17J_I2S_MCK0              _L_(9)
+#define PINMUX_PB17J_I2S_MCK0      ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
+#define PORT_PB17J_I2S_MCK0    (_UL_(1) << 17)
+#define PIN_PB13J_I2S_MCK1             _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
+#define MUX_PB13J_I2S_MCK1              _L_(9)
+#define PINMUX_PB13J_I2S_MCK1      ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
+#define PORT_PB13J_I2S_MCK1    (_UL_(1) << 13)
+#define PIN_PA10J_I2S_SCK0             _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
+#define MUX_PA10J_I2S_SCK0              _L_(9)
+#define PINMUX_PA10J_I2S_SCK0      ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
+#define PORT_PA10J_I2S_SCK0    (_UL_(1) << 10)
+#define PIN_PB16J_I2S_SCK0             _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
+#define MUX_PB16J_I2S_SCK0              _L_(9)
+#define PINMUX_PB16J_I2S_SCK0      ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
+#define PORT_PB16J_I2S_SCK0    (_UL_(1) << 16)
+#define PIN_PB12J_I2S_SCK1             _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
+#define MUX_PB12J_I2S_SCK1              _L_(9)
+#define PINMUX_PB12J_I2S_SCK1      ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
+#define PORT_PB12J_I2S_SCK1    (_UL_(1) << 12)
+#define PIN_PA22J_I2S_SDI              _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
+#define MUX_PA22J_I2S_SDI               _L_(9)
+#define PINMUX_PA22J_I2S_SDI       ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
+#define PORT_PA22J_I2S_SDI     (_UL_(1) << 22)
+#define PIN_PB10J_I2S_SDI              _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
+#define MUX_PB10J_I2S_SDI               _L_(9)
+#define PINMUX_PB10J_I2S_SDI       ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
+#define PORT_PB10J_I2S_SDI     (_UL_(1) << 10)
+#define PIN_PA11J_I2S_SDO              _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
+#define MUX_PA11J_I2S_SDO               _L_(9)
+#define PINMUX_PA11J_I2S_SDO       ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
+#define PORT_PA11J_I2S_SDO     (_UL_(1) << 11)
+#define PIN_PA21J_I2S_SDO              _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
+#define MUX_PA21J_I2S_SDO               _L_(9)
+#define PINMUX_PA21J_I2S_SDO       ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
+#define PORT_PA21J_I2S_SDO     (_UL_(1) << 21)
+/* ========== PORT definition for PCC peripheral ========== */
+#define PIN_PA14K_PCC_CLK              _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
+#define MUX_PA14K_PCC_CLK              _L_(10)
+#define PINMUX_PA14K_PCC_CLK       ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
+#define PORT_PA14K_PCC_CLK     (_UL_(1) << 14)
+#define PIN_PA16K_PCC_DATA0            _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
+#define MUX_PA16K_PCC_DATA0            _L_(10)
+#define PINMUX_PA16K_PCC_DATA0     ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
+#define PORT_PA16K_PCC_DATA0   (_UL_(1) << 16)
+#define PIN_PA17K_PCC_DATA1            _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
+#define MUX_PA17K_PCC_DATA1            _L_(10)
+#define PINMUX_PA17K_PCC_DATA1     ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
+#define PORT_PA17K_PCC_DATA1   (_UL_(1) << 17)
+#define PIN_PA18K_PCC_DATA2            _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
+#define MUX_PA18K_PCC_DATA2            _L_(10)
+#define PINMUX_PA18K_PCC_DATA2     ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
+#define PORT_PA18K_PCC_DATA2   (_UL_(1) << 18)
+#define PIN_PA19K_PCC_DATA3            _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
+#define MUX_PA19K_PCC_DATA3            _L_(10)
+#define PINMUX_PA19K_PCC_DATA3     ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
+#define PORT_PA19K_PCC_DATA3   (_UL_(1) << 19)
+#define PIN_PA20K_PCC_DATA4            _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
+#define MUX_PA20K_PCC_DATA4            _L_(10)
+#define PINMUX_PA20K_PCC_DATA4     ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
+#define PORT_PA20K_PCC_DATA4   (_UL_(1) << 20)
+#define PIN_PA21K_PCC_DATA5            _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
+#define MUX_PA21K_PCC_DATA5            _L_(10)
+#define PINMUX_PA21K_PCC_DATA5     ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
+#define PORT_PA21K_PCC_DATA5   (_UL_(1) << 21)
+#define PIN_PA22K_PCC_DATA6            _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
+#define MUX_PA22K_PCC_DATA6            _L_(10)
+#define PINMUX_PA22K_PCC_DATA6     ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
+#define PORT_PA22K_PCC_DATA6   (_UL_(1) << 22)
+#define PIN_PA23K_PCC_DATA7            _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
+#define MUX_PA23K_PCC_DATA7            _L_(10)
+#define PINMUX_PA23K_PCC_DATA7     ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
+#define PORT_PA23K_PCC_DATA7   (_UL_(1) << 23)
+#define PIN_PB14K_PCC_DATA8            _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
+#define MUX_PB14K_PCC_DATA8            _L_(10)
+#define PINMUX_PB14K_PCC_DATA8     ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
+#define PORT_PB14K_PCC_DATA8   (_UL_(1) << 14)
+#define PIN_PB15K_PCC_DATA9            _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
+#define MUX_PB15K_PCC_DATA9            _L_(10)
+#define PINMUX_PB15K_PCC_DATA9     ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
+#define PORT_PB15K_PCC_DATA9   (_UL_(1) << 15)
+#define PIN_PC12K_PCC_DATA10           _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
+#define MUX_PC12K_PCC_DATA10           _L_(10)
+#define PINMUX_PC12K_PCC_DATA10    ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
+#define PORT_PC12K_PCC_DATA10  (_UL_(1) << 12)
+#define PIN_PC13K_PCC_DATA11           _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
+#define MUX_PC13K_PCC_DATA11           _L_(10)
+#define PINMUX_PC13K_PCC_DATA11    ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
+#define PORT_PC13K_PCC_DATA11  (_UL_(1) << 13)
+#define PIN_PC14K_PCC_DATA12           _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
+#define MUX_PC14K_PCC_DATA12           _L_(10)
+#define PINMUX_PC14K_PCC_DATA12    ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
+#define PORT_PC14K_PCC_DATA12  (_UL_(1) << 14)
+#define PIN_PC15K_PCC_DATA13           _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
+#define MUX_PC15K_PCC_DATA13           _L_(10)
+#define PINMUX_PC15K_PCC_DATA13    ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
+#define PORT_PC15K_PCC_DATA13  (_UL_(1) << 15)
+#define PIN_PA12K_PCC_DEN1             _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
+#define MUX_PA12K_PCC_DEN1             _L_(10)
+#define PINMUX_PA12K_PCC_DEN1      ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
+#define PORT_PA12K_PCC_DEN1    (_UL_(1) << 12)
+#define PIN_PA13K_PCC_DEN2             _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
+#define MUX_PA13K_PCC_DEN2             _L_(10)
+#define PINMUX_PA13K_PCC_DEN2      ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
+#define PORT_PA13K_PCC_DEN2    (_UL_(1) << 13)
+/* ========== PORT definition for SDHC0 peripheral ========== */
+#define PIN_PA06I_SDHC0_SDCD            _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
+#define MUX_PA06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA06I_SDHC0_SDCD    ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
+#define PORT_PA06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PA12I_SDHC0_SDCD           _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
+#define MUX_PA12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PA12I_SDHC0_SDCD    ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
+#define PORT_PA12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PB12I_SDHC0_SDCD           _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
+#define MUX_PB12I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PB12I_SDHC0_SDCD    ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
+#define PORT_PB12I_SDHC0_SDCD  (_UL_(1) << 12)
+#define PIN_PC06I_SDHC0_SDCD           _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
+#define MUX_PC06I_SDHC0_SDCD            _L_(8)
+#define PINMUX_PC06I_SDHC0_SDCD    ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
+#define PORT_PC06I_SDHC0_SDCD  (_UL_(1) <<  6)
+#define PIN_PB11I_SDHC0_SDCK           _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
+#define MUX_PB11I_SDHC0_SDCK            _L_(8)
+#define PINMUX_PB11I_SDHC0_SDCK    ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
+#define PORT_PB11I_SDHC0_SDCK  (_UL_(1) << 11)
+#define PIN_PA08I_SDHC0_SDCMD           _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
+#define MUX_PA08I_SDHC0_SDCMD           _L_(8)
+#define PINMUX_PA08I_SDHC0_SDCMD   ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
+#define PORT_PA08I_SDHC0_SDCMD  (_UL_(1) <<  8)
+#define PIN_PA09I_SDHC0_SDDAT0          _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
+#define MUX_PA09I_SDHC0_SDDAT0          _L_(8)
+#define PINMUX_PA09I_SDHC0_SDDAT0  ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
+#define PORT_PA09I_SDHC0_SDDAT0  (_UL_(1) <<  9)
+#define PIN_PA10I_SDHC0_SDDAT1         _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
+#define MUX_PA10I_SDHC0_SDDAT1          _L_(8)
+#define PINMUX_PA10I_SDHC0_SDDAT1  ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
+#define PORT_PA10I_SDHC0_SDDAT1  (_UL_(1) << 10)
+#define PIN_PA11I_SDHC0_SDDAT2         _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
+#define MUX_PA11I_SDHC0_SDDAT2          _L_(8)
+#define PINMUX_PA11I_SDHC0_SDDAT2  ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
+#define PORT_PA11I_SDHC0_SDDAT2  (_UL_(1) << 11)
+#define PIN_PB10I_SDHC0_SDDAT3         _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
+#define MUX_PB10I_SDHC0_SDDAT3          _L_(8)
+#define PINMUX_PB10I_SDHC0_SDDAT3  ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
+#define PORT_PB10I_SDHC0_SDDAT3  (_UL_(1) << 10)
+#define PIN_PA07I_SDHC0_SDWP            _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
+#define MUX_PA07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA07I_SDHC0_SDWP    ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
+#define PORT_PA07I_SDHC0_SDWP  (_UL_(1) <<  7)
+#define PIN_PA13I_SDHC0_SDWP           _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
+#define MUX_PA13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PA13I_SDHC0_SDWP    ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
+#define PORT_PA13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PB13I_SDHC0_SDWP           _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
+#define MUX_PB13I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PB13I_SDHC0_SDWP    ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
+#define PORT_PB13I_SDHC0_SDWP  (_UL_(1) << 13)
+#define PIN_PC07I_SDHC0_SDWP           _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
+#define MUX_PC07I_SDHC0_SDWP            _L_(8)
+#define PINMUX_PC07I_SDHC0_SDWP    ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
+#define PORT_PC07I_SDHC0_SDWP  (_UL_(1) <<  7)
+/* ========== PORT definition for SDHC1 peripheral ========== */
+#define PIN_PB16I_SDHC1_SDCD           _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
+#define MUX_PB16I_SDHC1_SDCD            _L_(8)
+#define PINMUX_PB16I_SDHC1_SDCD    ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
+#define PORT_PB16I_SDHC1_SDCD  (_UL_(1) << 16)
+#define PIN_PC20I_SDHC1_SDCD           _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
+#define MUX_PC20I_SDHC1_SDCD            _L_(8)
+#define PINMUX_PC20I_SDHC1_SDCD    ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
+#define PORT_PC20I_SDHC1_SDCD  (_UL_(1) << 20)
+#define PIN_PA21I_SDHC1_SDCK           _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
+#define MUX_PA21I_SDHC1_SDCK            _L_(8)
+#define PINMUX_PA21I_SDHC1_SDCK    ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
+#define PORT_PA21I_SDHC1_SDCK  (_UL_(1) << 21)
+#define PIN_PA20I_SDHC1_SDCMD          _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
+#define MUX_PA20I_SDHC1_SDCMD           _L_(8)
+#define PINMUX_PA20I_SDHC1_SDCMD   ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
+#define PORT_PA20I_SDHC1_SDCMD  (_UL_(1) << 20)
+#define PIN_PB18I_SDHC1_SDDAT0         _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
+#define MUX_PB18I_SDHC1_SDDAT0          _L_(8)
+#define PINMUX_PB18I_SDHC1_SDDAT0  ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
+#define PORT_PB18I_SDHC1_SDDAT0  (_UL_(1) << 18)
+#define PIN_PB19I_SDHC1_SDDAT1         _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
+#define MUX_PB19I_SDHC1_SDDAT1          _L_(8)
+#define PINMUX_PB19I_SDHC1_SDDAT1  ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
+#define PORT_PB19I_SDHC1_SDDAT1  (_UL_(1) << 19)
+#define PIN_PB20I_SDHC1_SDDAT2         _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
+#define MUX_PB20I_SDHC1_SDDAT2          _L_(8)
+#define PINMUX_PB20I_SDHC1_SDDAT2  ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
+#define PORT_PB20I_SDHC1_SDDAT2  (_UL_(1) << 20)
+#define PIN_PB21I_SDHC1_SDDAT3         _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
+#define MUX_PB21I_SDHC1_SDDAT3          _L_(8)
+#define PINMUX_PB21I_SDHC1_SDDAT3  ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
+#define PORT_PB21I_SDHC1_SDDAT3  (_UL_(1) << 21)
+#define PIN_PB17I_SDHC1_SDWP           _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
+#define MUX_PB17I_SDHC1_SDWP            _L_(8)
+#define PINMUX_PB17I_SDHC1_SDWP    ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
+#define PORT_PB17I_SDHC1_SDWP  (_UL_(1) << 17)
+#define PIN_PC21I_SDHC1_SDWP           _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
+#define MUX_PC21I_SDHC1_SDWP            _L_(8)
+#define PINMUX_PC21I_SDHC1_SDWP    ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
+#define PORT_PC21I_SDHC1_SDWP  (_UL_(1) << 21)
+
+#endif /* _SAME53N20A_PIO_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/sam.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/sam.h
new file mode 100644
index 000000000..9596fae03
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/sam.h	
@@ -0,0 +1,48 @@
+/**
+ * \file
+ *
+ * \brief Top level header file
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \license_stop
+ *
+ */
+
+#ifndef _SAM_
+#define _SAM_
+
+#if   defined(__SAME53J18A__) || defined(__ATSAME53J18A__)
+  #include "same53j18a.h"
+#elif defined(__SAME53J19A__) || defined(__ATSAME53J19A__)
+  #include "same53j19a.h"
+#elif defined(__SAME53J20A__) || defined(__ATSAME53J20A__)
+  #include "same53j20a.h"
+#elif defined(__SAME53N19A__) || defined(__ATSAME53N19A__)
+  #include "same53n19a.h"
+#elif defined(__SAME53N20A__) || defined(__ATSAME53N20A__)
+  #include "same53n20a.h"
+#else
+  #error Library does not support the specified device
+#endif
+
+#endif /* _SAM_ */
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53.h
new file mode 100644
index 000000000..748a32050
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53.h	
@@ -0,0 +1,52 @@
+/**
+ * \file
+ *
+ * \brief Top header file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53_
+#define _SAME53_
+
+/**
+ * \defgroup SAME53_definitions SAME53 Device Definitions
+ * \brief SAME53 CMSIS Definitions.
+ */
+
+#if   defined(__SAME53J18A__) || defined(__ATSAME53J18A__)
+  #include "same53j18a.h"
+#elif defined(__SAME53J19A__) || defined(__ATSAME53J19A__)
+  #include "same53j19a.h"
+#elif defined(__SAME53J20A__) || defined(__ATSAME53J20A__)
+  #include "same53j20a.h"
+#elif defined(__SAME53N19A__) || defined(__ATSAME53N19A__)
+  #include "same53n19a.h"
+#elif defined(__SAME53N20A__) || defined(__ATSAME53N20A__)
+  #include "same53n20a.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAME53_ */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j18a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j18a.h
new file mode 100644
index 000000000..b66699089
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j18a.h	
@@ -0,0 +1,1027 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME53J18A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53J18A_
+#define _SAME53J18A_
+
+/**
+ * \ingroup SAME53_definitions
+ * \addtogroup SAME53J18A_definitions SAME53J18A definitions
+ * This file defines all structures and symbols for SAME53J18A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+/** \defgroup SAME53J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M4 Processor Exceptions Numbers *******************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt      */
+  HardFault_IRQn           = -13,/**<  3 Hard Fault Interrupt        */
+  MemoryManagement_IRQn    = -12,/**<  4 Memory Management Interrupt */
+  BusFault_IRQn            = -11,/**<  5 Bus Fault Interrupt         */
+  UsageFault_IRQn          = -10,/**<  6 Usage Fault Interrupt       */
+  SVCall_IRQn              = -5, /**< 11 SV Call Interrupt           */
+  DebugMonitor_IRQn        = -4, /**< 12 Debug Monitor Interrupt     */
+  PendSV_IRQn              = -2, /**< 14 Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 System Tick Interrupt       */
+  /******  SAME53J18A-specific Interrupt Numbers *********************/
+  PM_IRQn                  =  0, /**<  0 SAME53J18A Power Manager (PM) */
+  MCLK_IRQn                =  1, /**<  1 SAME53J18A Main Clock (MCLK) */
+  OSCCTRL_0_IRQn           =  2, /**<  2 SAME53J18A Oscillators Control (OSCCTRL) IRQ 0 */
+  OSCCTRL_1_IRQn           =  3, /**<  3 SAME53J18A Oscillators Control (OSCCTRL) IRQ 1 */
+  OSCCTRL_2_IRQn           =  4, /**<  4 SAME53J18A Oscillators Control (OSCCTRL) IRQ 2 */
+  OSCCTRL_3_IRQn           =  5, /**<  5 SAME53J18A Oscillators Control (OSCCTRL) IRQ 3 */
+  OSCCTRL_4_IRQn           =  6, /**<  6 SAME53J18A Oscillators Control (OSCCTRL) IRQ 4 */
+  OSC32KCTRL_IRQn          =  7, /**<  7 SAME53J18A 32kHz Oscillators Control (OSC32KCTRL) */
+  SUPC_0_IRQn              =  8, /**<  8 SAME53J18A Supply Controller (SUPC) IRQ 0 */
+  SUPC_1_IRQn              =  9, /**<  9 SAME53J18A Supply Controller (SUPC) IRQ 1 */
+  WDT_IRQn                 = 10, /**< 10 SAME53J18A Watchdog Timer (WDT) */
+  RTC_IRQn                 = 11, /**< 11 SAME53J18A Real-Time Counter (RTC) */
+  EIC_0_IRQn               = 12, /**< 12 SAME53J18A External Interrupt Controller (EIC) IRQ 0 */
+  EIC_1_IRQn               = 13, /**< 13 SAME53J18A External Interrupt Controller (EIC) IRQ 1 */
+  EIC_2_IRQn               = 14, /**< 14 SAME53J18A External Interrupt Controller (EIC) IRQ 2 */
+  EIC_3_IRQn               = 15, /**< 15 SAME53J18A External Interrupt Controller (EIC) IRQ 3 */
+  EIC_4_IRQn               = 16, /**< 16 SAME53J18A External Interrupt Controller (EIC) IRQ 4 */
+  EIC_5_IRQn               = 17, /**< 17 SAME53J18A External Interrupt Controller (EIC) IRQ 5 */
+  EIC_6_IRQn               = 18, /**< 18 SAME53J18A External Interrupt Controller (EIC) IRQ 6 */
+  EIC_7_IRQn               = 19, /**< 19 SAME53J18A External Interrupt Controller (EIC) IRQ 7 */
+  EIC_8_IRQn               = 20, /**< 20 SAME53J18A External Interrupt Controller (EIC) IRQ 8 */
+  EIC_9_IRQn               = 21, /**< 21 SAME53J18A External Interrupt Controller (EIC) IRQ 9 */
+  EIC_10_IRQn              = 22, /**< 22 SAME53J18A External Interrupt Controller (EIC) IRQ 10 */
+  EIC_11_IRQn              = 23, /**< 23 SAME53J18A External Interrupt Controller (EIC) IRQ 11 */
+  EIC_12_IRQn              = 24, /**< 24 SAME53J18A External Interrupt Controller (EIC) IRQ 12 */
+  EIC_13_IRQn              = 25, /**< 25 SAME53J18A External Interrupt Controller (EIC) IRQ 13 */
+  EIC_14_IRQn              = 26, /**< 26 SAME53J18A External Interrupt Controller (EIC) IRQ 14 */
+  EIC_15_IRQn              = 27, /**< 27 SAME53J18A External Interrupt Controller (EIC) IRQ 15 */
+  FREQM_IRQn               = 28, /**< 28 SAME53J18A Frequency Meter (FREQM) */
+  NVMCTRL_0_IRQn           = 29, /**< 29 SAME53J18A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+  NVMCTRL_1_IRQn           = 30, /**< 30 SAME53J18A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+  DMAC_0_IRQn              = 31, /**< 31 SAME53J18A Direct Memory Access Controller (DMAC) IRQ 0 */
+  DMAC_1_IRQn              = 32, /**< 32 SAME53J18A Direct Memory Access Controller (DMAC) IRQ 1 */
+  DMAC_2_IRQn              = 33, /**< 33 SAME53J18A Direct Memory Access Controller (DMAC) IRQ 2 */
+  DMAC_3_IRQn              = 34, /**< 34 SAME53J18A Direct Memory Access Controller (DMAC) IRQ 3 */
+  DMAC_4_IRQn              = 35, /**< 35 SAME53J18A Direct Memory Access Controller (DMAC) IRQ 4 */
+  EVSYS_0_IRQn             = 36, /**< 36 SAME53J18A Event System Interface (EVSYS) IRQ 0 */
+  EVSYS_1_IRQn             = 37, /**< 37 SAME53J18A Event System Interface (EVSYS) IRQ 1 */
+  EVSYS_2_IRQn             = 38, /**< 38 SAME53J18A Event System Interface (EVSYS) IRQ 2 */
+  EVSYS_3_IRQn             = 39, /**< 39 SAME53J18A Event System Interface (EVSYS) IRQ 3 */
+  EVSYS_4_IRQn             = 40, /**< 40 SAME53J18A Event System Interface (EVSYS) IRQ 4 */
+  PAC_IRQn                 = 41, /**< 41 SAME53J18A Peripheral Access Controller (PAC) */
+  RAMECC_IRQn              = 45, /**< 45 SAME53J18A RAM ECC (RAMECC) */
+  SERCOM0_0_IRQn           = 46, /**< 46 SAME53J18A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+  SERCOM0_1_IRQn           = 47, /**< 47 SAME53J18A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+  SERCOM0_2_IRQn           = 48, /**< 48 SAME53J18A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+  SERCOM0_3_IRQn           = 49, /**< 49 SAME53J18A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+  SERCOM1_0_IRQn           = 50, /**< 50 SAME53J18A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+  SERCOM1_1_IRQn           = 51, /**< 51 SAME53J18A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+  SERCOM1_2_IRQn           = 52, /**< 52 SAME53J18A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+  SERCOM1_3_IRQn           = 53, /**< 53 SAME53J18A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+  SERCOM2_0_IRQn           = 54, /**< 54 SAME53J18A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+  SERCOM2_1_IRQn           = 55, /**< 55 SAME53J18A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+  SERCOM2_2_IRQn           = 56, /**< 56 SAME53J18A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+  SERCOM2_3_IRQn           = 57, /**< 57 SAME53J18A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+  SERCOM3_0_IRQn           = 58, /**< 58 SAME53J18A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+  SERCOM3_1_IRQn           = 59, /**< 59 SAME53J18A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+  SERCOM3_2_IRQn           = 60, /**< 60 SAME53J18A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+  SERCOM3_3_IRQn           = 61, /**< 61 SAME53J18A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+  SERCOM4_0_IRQn           = 62, /**< 62 SAME53J18A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+  SERCOM4_1_IRQn           = 63, /**< 63 SAME53J18A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+  SERCOM4_2_IRQn           = 64, /**< 64 SAME53J18A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+  SERCOM4_3_IRQn           = 65, /**< 65 SAME53J18A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+  SERCOM5_0_IRQn           = 66, /**< 66 SAME53J18A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+  SERCOM5_1_IRQn           = 67, /**< 67 SAME53J18A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+  SERCOM5_2_IRQn           = 68, /**< 68 SAME53J18A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+  SERCOM5_3_IRQn           = 69, /**< 69 SAME53J18A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+  USB_0_IRQn               = 80, /**< 80 SAME53J18A Universal Serial Bus (USB) IRQ 0 */
+  USB_1_IRQn               = 81, /**< 81 SAME53J18A Universal Serial Bus (USB) IRQ 1 */
+  USB_2_IRQn               = 82, /**< 82 SAME53J18A Universal Serial Bus (USB) IRQ 2 */
+  USB_3_IRQn               = 83, /**< 83 SAME53J18A Universal Serial Bus (USB) IRQ 3 */
+  GMAC_IRQn                = 84, /**< 84 SAME53J18A Ethernet MAC (GMAC) */
+  TCC0_0_IRQn              = 85, /**< 85 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 0 */
+  TCC0_1_IRQn              = 86, /**< 86 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 1 */
+  TCC0_2_IRQn              = 87, /**< 87 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 2 */
+  TCC0_3_IRQn              = 88, /**< 88 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 3 */
+  TCC0_4_IRQn              = 89, /**< 89 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 4 */
+  TCC0_5_IRQn              = 90, /**< 90 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 5 */
+  TCC0_6_IRQn              = 91, /**< 91 SAME53J18A Timer Counter Control 0 (TCC0) IRQ 6 */
+  TCC1_0_IRQn              = 92, /**< 92 SAME53J18A Timer Counter Control 1 (TCC1) IRQ 0 */
+  TCC1_1_IRQn              = 93, /**< 93 SAME53J18A Timer Counter Control 1 (TCC1) IRQ 1 */
+  TCC1_2_IRQn              = 94, /**< 94 SAME53J18A Timer Counter Control 1 (TCC1) IRQ 2 */
+  TCC1_3_IRQn              = 95, /**< 95 SAME53J18A Timer Counter Control 1 (TCC1) IRQ 3 */
+  TCC1_4_IRQn              = 96, /**< 96 SAME53J18A Timer Counter Control 1 (TCC1) IRQ 4 */
+  TCC2_0_IRQn              = 97, /**< 97 SAME53J18A Timer Counter Control 2 (TCC2) IRQ 0 */
+  TCC2_1_IRQn              = 98, /**< 98 SAME53J18A Timer Counter Control 2 (TCC2) IRQ 1 */
+  TCC2_2_IRQn              = 99, /**< 99 SAME53J18A Timer Counter Control 2 (TCC2) IRQ 2 */
+  TCC2_3_IRQn              = 100, /**< 100 SAME53J18A Timer Counter Control 2 (TCC2) IRQ 3 */
+  TCC3_0_IRQn              = 101, /**< 101 SAME53J18A Timer Counter Control 3 (TCC3) IRQ 0 */
+  TCC3_1_IRQn              = 102, /**< 102 SAME53J18A Timer Counter Control 3 (TCC3) IRQ 1 */
+  TCC3_2_IRQn              = 103, /**< 103 SAME53J18A Timer Counter Control 3 (TCC3) IRQ 2 */
+  TCC4_0_IRQn              = 104, /**< 104 SAME53J18A Timer Counter Control 4 (TCC4) IRQ 0 */
+  TCC4_1_IRQn              = 105, /**< 105 SAME53J18A Timer Counter Control 4 (TCC4) IRQ 1 */
+  TCC4_2_IRQn              = 106, /**< 106 SAME53J18A Timer Counter Control 4 (TCC4) IRQ 2 */
+  TC0_IRQn                 = 107, /**< 107 SAME53J18A Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 108, /**< 108 SAME53J18A Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 109, /**< 109 SAME53J18A Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 110, /**< 110 SAME53J18A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 111, /**< 111 SAME53J18A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 112, /**< 112 SAME53J18A Basic Timer Counter 5 (TC5) */
+  PDEC_0_IRQn              = 115, /**< 115 SAME53J18A Quadrature Decodeur (PDEC) IRQ 0 */
+  PDEC_1_IRQn              = 116, /**< 116 SAME53J18A Quadrature Decodeur (PDEC) IRQ 1 */
+  PDEC_2_IRQn              = 117, /**< 117 SAME53J18A Quadrature Decodeur (PDEC) IRQ 2 */
+  ADC0_0_IRQn              = 118, /**< 118 SAME53J18A Analog Digital Converter 0 (ADC0) IRQ 0 */
+  ADC0_1_IRQn              = 119, /**< 119 SAME53J18A Analog Digital Converter 0 (ADC0) IRQ 1 */
+  ADC1_0_IRQn              = 120, /**< 120 SAME53J18A Analog Digital Converter 1 (ADC1) IRQ 0 */
+  ADC1_1_IRQn              = 121, /**< 121 SAME53J18A Analog Digital Converter 1 (ADC1) IRQ 1 */
+  AC_IRQn                  = 122, /**< 122 SAME53J18A Analog Comparators (AC) */
+  DAC_0_IRQn               = 123, /**< 123 SAME53J18A Digital-to-Analog Converter (DAC) IRQ 0 */
+  DAC_1_IRQn               = 124, /**< 124 SAME53J18A Digital-to-Analog Converter (DAC) IRQ 1 */
+  DAC_2_IRQn               = 125, /**< 125 SAME53J18A Digital-to-Analog Converter (DAC) IRQ 2 */
+  DAC_3_IRQn               = 126, /**< 126 SAME53J18A Digital-to-Analog Converter (DAC) IRQ 3 */
+  DAC_4_IRQn               = 127, /**< 127 SAME53J18A Digital-to-Analog Converter (DAC) IRQ 4 */
+  I2S_IRQn                 = 128, /**< 128 SAME53J18A Inter-IC Sound Interface (I2S) */
+  PCC_IRQn                 = 129, /**< 129 SAME53J18A Parallel Capture Controller (PCC) */
+  AES_IRQn                 = 130, /**< 130 SAME53J18A Advanced Encryption Standard (AES) */
+  TRNG_IRQn                = 131, /**< 131 SAME53J18A True Random Generator (TRNG) */
+  ICM_IRQn                 = 132, /**< 132 SAME53J18A Integrity Check Monitor (ICM) */
+  PUKCC_IRQn               = 133, /**< 133 SAME53J18A PUblic-Key Cryptography Controller (PUKCC) */
+  QSPI_IRQn                = 134, /**< 134 SAME53J18A Quad SPI interface (QSPI) */
+  SDHC0_IRQn               = 135, /**< 135 SAME53J18A SD/MMC Host Controller 0 (SDHC0) */
+
+  PERIPH_COUNT_IRQn        = 137  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNonMaskableInt_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManagement_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVCall_Handler;
+  void* pfnDebugMonitor_Handler;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnMCLK_Handler;                  /*  1 Main Clock */
+  void* pfnOSCCTRL_0_Handler;             /*  2 Oscillators Control IRQ 0 */
+  void* pfnOSCCTRL_1_Handler;             /*  3 Oscillators Control IRQ 1 */
+  void* pfnOSCCTRL_2_Handler;             /*  4 Oscillators Control IRQ 2 */
+  void* pfnOSCCTRL_3_Handler;             /*  5 Oscillators Control IRQ 3 */
+  void* pfnOSCCTRL_4_Handler;             /*  6 Oscillators Control IRQ 4 */
+  void* pfnOSC32KCTRL_Handler;            /*  7 32kHz Oscillators Control */
+  void* pfnSUPC_0_Handler;                /*  8 Supply Controller IRQ 0 */
+  void* pfnSUPC_1_Handler;                /*  9 Supply Controller IRQ 1 */
+  void* pfnWDT_Handler;                   /* 10 Watchdog Timer */
+  void* pfnRTC_Handler;                   /* 11 Real-Time Counter */
+  void* pfnEIC_0_Handler;                 /* 12 External Interrupt Controller IRQ 0 */
+  void* pfnEIC_1_Handler;                 /* 13 External Interrupt Controller IRQ 1 */
+  void* pfnEIC_2_Handler;                 /* 14 External Interrupt Controller IRQ 2 */
+  void* pfnEIC_3_Handler;                 /* 15 External Interrupt Controller IRQ 3 */
+  void* pfnEIC_4_Handler;                 /* 16 External Interrupt Controller IRQ 4 */
+  void* pfnEIC_5_Handler;                 /* 17 External Interrupt Controller IRQ 5 */
+  void* pfnEIC_6_Handler;                 /* 18 External Interrupt Controller IRQ 6 */
+  void* pfnEIC_7_Handler;                 /* 19 External Interrupt Controller IRQ 7 */
+  void* pfnEIC_8_Handler;                 /* 20 External Interrupt Controller IRQ 8 */
+  void* pfnEIC_9_Handler;                 /* 21 External Interrupt Controller IRQ 9 */
+  void* pfnEIC_10_Handler;                /* 22 External Interrupt Controller IRQ 10 */
+  void* pfnEIC_11_Handler;                /* 23 External Interrupt Controller IRQ 11 */
+  void* pfnEIC_12_Handler;                /* 24 External Interrupt Controller IRQ 12 */
+  void* pfnEIC_13_Handler;                /* 25 External Interrupt Controller IRQ 13 */
+  void* pfnEIC_14_Handler;                /* 26 External Interrupt Controller IRQ 14 */
+  void* pfnEIC_15_Handler;                /* 27 External Interrupt Controller IRQ 15 */
+  void* pfnFREQM_Handler;                 /* 28 Frequency Meter */
+  void* pfnNVMCTRL_0_Handler;             /* 29 Non-Volatile Memory Controller IRQ 0 */
+  void* pfnNVMCTRL_1_Handler;             /* 30 Non-Volatile Memory Controller IRQ 1 */
+  void* pfnDMAC_0_Handler;                /* 31 Direct Memory Access Controller IRQ 0 */
+  void* pfnDMAC_1_Handler;                /* 32 Direct Memory Access Controller IRQ 1 */
+  void* pfnDMAC_2_Handler;                /* 33 Direct Memory Access Controller IRQ 2 */
+  void* pfnDMAC_3_Handler;                /* 34 Direct Memory Access Controller IRQ 3 */
+  void* pfnDMAC_4_Handler;                /* 35 Direct Memory Access Controller IRQ 4 */
+  void* pfnEVSYS_0_Handler;               /* 36 Event System Interface IRQ 0 */
+  void* pfnEVSYS_1_Handler;               /* 37 Event System Interface IRQ 1 */
+  void* pfnEVSYS_2_Handler;               /* 38 Event System Interface IRQ 2 */
+  void* pfnEVSYS_3_Handler;               /* 39 Event System Interface IRQ 3 */
+  void* pfnEVSYS_4_Handler;               /* 40 Event System Interface IRQ 4 */
+  void* pfnPAC_Handler;                   /* 41 Peripheral Access Controller */
+  void* pvReserved42;
+  void* pvReserved43;
+  void* pvReserved44;
+  void* pfnRAMECC_Handler;                /* 45 RAM ECC */
+  void* pfnSERCOM0_0_Handler;             /* 46 Serial Communication Interface 0 IRQ 0 */
+  void* pfnSERCOM0_1_Handler;             /* 47 Serial Communication Interface 0 IRQ 1 */
+  void* pfnSERCOM0_2_Handler;             /* 48 Serial Communication Interface 0 IRQ 2 */
+  void* pfnSERCOM0_3_Handler;             /* 49 Serial Communication Interface 0 IRQ 3 */
+  void* pfnSERCOM1_0_Handler;             /* 50 Serial Communication Interface 1 IRQ 0 */
+  void* pfnSERCOM1_1_Handler;             /* 51 Serial Communication Interface 1 IRQ 1 */
+  void* pfnSERCOM1_2_Handler;             /* 52 Serial Communication Interface 1 IRQ 2 */
+  void* pfnSERCOM1_3_Handler;             /* 53 Serial Communication Interface 1 IRQ 3 */
+  void* pfnSERCOM2_0_Handler;             /* 54 Serial Communication Interface 2 IRQ 0 */
+  void* pfnSERCOM2_1_Handler;             /* 55 Serial Communication Interface 2 IRQ 1 */
+  void* pfnSERCOM2_2_Handler;             /* 56 Serial Communication Interface 2 IRQ 2 */
+  void* pfnSERCOM2_3_Handler;             /* 57 Serial Communication Interface 2 IRQ 3 */
+  void* pfnSERCOM3_0_Handler;             /* 58 Serial Communication Interface 3 IRQ 0 */
+  void* pfnSERCOM3_1_Handler;             /* 59 Serial Communication Interface 3 IRQ 1 */
+  void* pfnSERCOM3_2_Handler;             /* 60 Serial Communication Interface 3 IRQ 2 */
+  void* pfnSERCOM3_3_Handler;             /* 61 Serial Communication Interface 3 IRQ 3 */
+  void* pfnSERCOM4_0_Handler;             /* 62 Serial Communication Interface 4 IRQ 0 */
+  void* pfnSERCOM4_1_Handler;             /* 63 Serial Communication Interface 4 IRQ 1 */
+  void* pfnSERCOM4_2_Handler;             /* 64 Serial Communication Interface 4 IRQ 2 */
+  void* pfnSERCOM4_3_Handler;             /* 65 Serial Communication Interface 4 IRQ 3 */
+  void* pfnSERCOM5_0_Handler;             /* 66 Serial Communication Interface 5 IRQ 0 */
+  void* pfnSERCOM5_1_Handler;             /* 67 Serial Communication Interface 5 IRQ 1 */
+  void* pfnSERCOM5_2_Handler;             /* 68 Serial Communication Interface 5 IRQ 2 */
+  void* pfnSERCOM5_3_Handler;             /* 69 Serial Communication Interface 5 IRQ 3 */
+  void* pvReserved70;
+  void* pvReserved71;
+  void* pvReserved72;
+  void* pvReserved73;
+  void* pvReserved74;
+  void* pvReserved75;
+  void* pvReserved76;
+  void* pvReserved77;
+  void* pvReserved78;
+  void* pvReserved79;
+  void* pfnUSB_0_Handler;                 /* 80 Universal Serial Bus IRQ 0 */
+  void* pfnUSB_1_Handler;                 /* 81 Universal Serial Bus IRQ 1 */
+  void* pfnUSB_2_Handler;                 /* 82 Universal Serial Bus IRQ 2 */
+  void* pfnUSB_3_Handler;                 /* 83 Universal Serial Bus IRQ 3 */
+  void* pfnGMAC_Handler;                  /* 84 Ethernet MAC */
+  void* pfnTCC0_0_Handler;                /* 85 Timer Counter Control 0 IRQ 0 */
+  void* pfnTCC0_1_Handler;                /* 86 Timer Counter Control 0 IRQ 1 */
+  void* pfnTCC0_2_Handler;                /* 87 Timer Counter Control 0 IRQ 2 */
+  void* pfnTCC0_3_Handler;                /* 88 Timer Counter Control 0 IRQ 3 */
+  void* pfnTCC0_4_Handler;                /* 89 Timer Counter Control 0 IRQ 4 */
+  void* pfnTCC0_5_Handler;                /* 90 Timer Counter Control 0 IRQ 5 */
+  void* pfnTCC0_6_Handler;                /* 91 Timer Counter Control 0 IRQ 6 */
+  void* pfnTCC1_0_Handler;                /* 92 Timer Counter Control 1 IRQ 0 */
+  void* pfnTCC1_1_Handler;                /* 93 Timer Counter Control 1 IRQ 1 */
+  void* pfnTCC1_2_Handler;                /* 94 Timer Counter Control 1 IRQ 2 */
+  void* pfnTCC1_3_Handler;                /* 95 Timer Counter Control 1 IRQ 3 */
+  void* pfnTCC1_4_Handler;                /* 96 Timer Counter Control 1 IRQ 4 */
+  void* pfnTCC2_0_Handler;                /* 97 Timer Counter Control 2 IRQ 0 */
+  void* pfnTCC2_1_Handler;                /* 98 Timer Counter Control 2 IRQ 1 */
+  void* pfnTCC2_2_Handler;                /* 99 Timer Counter Control 2 IRQ 2 */
+  void* pfnTCC2_3_Handler;                /* 100 Timer Counter Control 2 IRQ 3 */
+  void* pfnTCC3_0_Handler;                /* 101 Timer Counter Control 3 IRQ 0 */
+  void* pfnTCC3_1_Handler;                /* 102 Timer Counter Control 3 IRQ 1 */
+  void* pfnTCC3_2_Handler;                /* 103 Timer Counter Control 3 IRQ 2 */
+  void* pfnTCC4_0_Handler;                /* 104 Timer Counter Control 4 IRQ 0 */
+  void* pfnTCC4_1_Handler;                /* 105 Timer Counter Control 4 IRQ 1 */
+  void* pfnTCC4_2_Handler;                /* 106 Timer Counter Control 4 IRQ 2 */
+  void* pfnTC0_Handler;                   /* 107 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 108 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 109 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 110 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 111 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 112 Basic Timer Counter 5 */
+  void* pvReserved113;
+  void* pvReserved114;
+  void* pfnPDEC_0_Handler;                /* 115 Quadrature Decodeur IRQ 0 */
+  void* pfnPDEC_1_Handler;                /* 116 Quadrature Decodeur IRQ 1 */
+  void* pfnPDEC_2_Handler;                /* 117 Quadrature Decodeur IRQ 2 */
+  void* pfnADC0_0_Handler;                /* 118 Analog Digital Converter 0 IRQ 0 */
+  void* pfnADC0_1_Handler;                /* 119 Analog Digital Converter 0 IRQ 1 */
+  void* pfnADC1_0_Handler;                /* 120 Analog Digital Converter 1 IRQ 0 */
+  void* pfnADC1_1_Handler;                /* 121 Analog Digital Converter 1 IRQ 1 */
+  void* pfnAC_Handler;                    /* 122 Analog Comparators */
+  void* pfnDAC_0_Handler;                 /* 123 Digital-to-Analog Converter IRQ 0 */
+  void* pfnDAC_1_Handler;                 /* 124 Digital-to-Analog Converter IRQ 1 */
+  void* pfnDAC_2_Handler;                 /* 125 Digital-to-Analog Converter IRQ 2 */
+  void* pfnDAC_3_Handler;                 /* 126 Digital-to-Analog Converter IRQ 3 */
+  void* pfnDAC_4_Handler;                 /* 127 Digital-to-Analog Converter IRQ 4 */
+  void* pfnI2S_Handler;                   /* 128 Inter-IC Sound Interface */
+  void* pfnPCC_Handler;                   /* 129 Parallel Capture Controller */
+  void* pfnAES_Handler;                   /* 130 Advanced Encryption Standard */
+  void* pfnTRNG_Handler;                  /* 131 True Random Generator */
+  void* pfnICM_Handler;                   /* 132 Integrity Check Monitor */
+  void* pfnPUKCC_Handler;                 /* 133 PUblic-Key Cryptography Controller */
+  void* pfnQSPI_Handler;                  /* 134 Quad SPI interface */
+  void* pfnSDHC0_Handler;                 /* 135 SD/MMC Host Controller 0 */
+  void* pvReserved136;
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler               ( void );
+void NonMaskableInt_Handler      ( void );
+void HardFault_Handler           ( void );
+void MemManagement_Handler       ( void );
+void BusFault_Handler            ( void );
+void UsageFault_Handler          ( void );
+void SVCall_Handler              ( void );
+void DebugMonitor_Handler        ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void MCLK_Handler                ( void );
+void OSCCTRL_0_Handler           ( void );
+void OSCCTRL_1_Handler           ( void );
+void OSCCTRL_2_Handler           ( void );
+void OSCCTRL_3_Handler           ( void );
+void OSCCTRL_4_Handler           ( void );
+void OSC32KCTRL_Handler          ( void );
+void SUPC_0_Handler              ( void );
+void SUPC_1_Handler              ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_0_Handler               ( void );
+void EIC_1_Handler               ( void );
+void EIC_2_Handler               ( void );
+void EIC_3_Handler               ( void );
+void EIC_4_Handler               ( void );
+void EIC_5_Handler               ( void );
+void EIC_6_Handler               ( void );
+void EIC_7_Handler               ( void );
+void EIC_8_Handler               ( void );
+void EIC_9_Handler               ( void );
+void EIC_10_Handler              ( void );
+void EIC_11_Handler              ( void );
+void EIC_12_Handler              ( void );
+void EIC_13_Handler              ( void );
+void EIC_14_Handler              ( void );
+void EIC_15_Handler              ( void );
+void FREQM_Handler               ( void );
+void NVMCTRL_0_Handler           ( void );
+void NVMCTRL_1_Handler           ( void );
+void DMAC_0_Handler              ( void );
+void DMAC_1_Handler              ( void );
+void DMAC_2_Handler              ( void );
+void DMAC_3_Handler              ( void );
+void DMAC_4_Handler              ( void );
+void EVSYS_0_Handler             ( void );
+void EVSYS_1_Handler             ( void );
+void EVSYS_2_Handler             ( void );
+void EVSYS_3_Handler             ( void );
+void EVSYS_4_Handler             ( void );
+void PAC_Handler                 ( void );
+void RAMECC_Handler              ( void );
+void SERCOM0_0_Handler           ( void );
+void SERCOM0_1_Handler           ( void );
+void SERCOM0_2_Handler           ( void );
+void SERCOM0_3_Handler           ( void );
+void SERCOM1_0_Handler           ( void );
+void SERCOM1_1_Handler           ( void );
+void SERCOM1_2_Handler           ( void );
+void SERCOM1_3_Handler           ( void );
+void SERCOM2_0_Handler           ( void );
+void SERCOM2_1_Handler           ( void );
+void SERCOM2_2_Handler           ( void );
+void SERCOM2_3_Handler           ( void );
+void SERCOM3_0_Handler           ( void );
+void SERCOM3_1_Handler           ( void );
+void SERCOM3_2_Handler           ( void );
+void SERCOM3_3_Handler           ( void );
+void SERCOM4_0_Handler           ( void );
+void SERCOM4_1_Handler           ( void );
+void SERCOM4_2_Handler           ( void );
+void SERCOM4_3_Handler           ( void );
+void SERCOM5_0_Handler           ( void );
+void SERCOM5_1_Handler           ( void );
+void SERCOM5_2_Handler           ( void );
+void SERCOM5_3_Handler           ( void );
+void USB_0_Handler               ( void );
+void USB_1_Handler               ( void );
+void USB_2_Handler               ( void );
+void USB_3_Handler               ( void );
+void GMAC_Handler                ( void );
+void TCC0_0_Handler              ( void );
+void TCC0_1_Handler              ( void );
+void TCC0_2_Handler              ( void );
+void TCC0_3_Handler              ( void );
+void TCC0_4_Handler              ( void );
+void TCC0_5_Handler              ( void );
+void TCC0_6_Handler              ( void );
+void TCC1_0_Handler              ( void );
+void TCC1_1_Handler              ( void );
+void TCC1_2_Handler              ( void );
+void TCC1_3_Handler              ( void );
+void TCC1_4_Handler              ( void );
+void TCC2_0_Handler              ( void );
+void TCC2_1_Handler              ( void );
+void TCC2_2_Handler              ( void );
+void TCC2_3_Handler              ( void );
+void TCC3_0_Handler              ( void );
+void TCC3_1_Handler              ( void );
+void TCC3_2_Handler              ( void );
+void TCC4_0_Handler              ( void );
+void TCC4_1_Handler              ( void );
+void TCC4_2_Handler              ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void PDEC_0_Handler              ( void );
+void PDEC_1_Handler              ( void );
+void PDEC_2_Handler              ( void );
+void ADC0_0_Handler              ( void );
+void ADC0_1_Handler              ( void );
+void ADC1_0_Handler              ( void );
+void ADC1_1_Handler              ( void );
+void AC_Handler                  ( void );
+void DAC_0_Handler               ( void );
+void DAC_1_Handler               ( void );
+void DAC_2_Handler               ( void );
+void DAC_3_Handler               ( void );
+void DAC_4_Handler               ( void );
+void I2S_Handler                 ( void );
+void PCC_Handler                 ( void );
+void AES_Handler                 ( void );
+void TRNG_Handler                ( void );
+void ICM_Handler                 ( void );
+void PUKCC_Handler               ( void );
+void QSPI_Handler                ( void );
+void SDHC0_Handler               ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              1         /*!< Core revision r0p1 */
+#define __DEBUG_LVL            3         /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT          1         /*!< FPU present or not */
+#define __MPU_PRESENT          1         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       3         /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL            2         /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same53.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME53J18A */
+/* ************************************************************************** */
+/** \defgroup SAME53J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+/** \defgroup SAME53J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/pukcc.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/supc.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+/** \defgroup SAME53J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC            0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_MCLK           2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC           3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL        4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL     5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC           6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK           7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC           10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM         11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0       12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0           14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB           32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC          35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT          36 /**< \brief Port Module (PORT) */
+#define ID_DMAC          37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX       38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS         39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2       41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2           45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_RAMECC        48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_GMAC          66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2          67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3          68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4           69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC          71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC            72 /**< \brief Analog Comparators (AC) */
+#define ID_AES           73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG          74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM           75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC         76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI          77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL           78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4       96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC4         100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_ADC0         103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1         104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC          105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S          106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC          107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0        128 /**< \brief SD/MMC Host Controller (SDHC0) */
+
+#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+/** \defgroup SAME53J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0                          (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1                          (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES                           (0x42002400) /**< \brief (AES) APB Base Address */
+#define CCL                           (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC                          (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC                           (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM                         (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK                          (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC                          (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX                       (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM                           (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S                           (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK                          (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL                       (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL                    (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC                           (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC                           (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC                          (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC                         (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB                     (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI                          (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC                        (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC                          (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC                           (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0                         (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SERCOM0                       (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SUPC                          (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TC0                           (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4                          (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG                          (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB                           (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC0              ((Adc      *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1              ((Adc      *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM      2                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC0, ADC1 }             /**< \brief (ADC) Instances List */
+
+#define AES               ((Aes      *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM      1                          /**< \brief (AES) Number of instances */
+#define AES_INSTS         { AES }                    /**< \brief (AES) Instances List */
+
+#define CCL               ((Ccl      *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM      1                          /**< \brief (CCL) Number of instances */
+#define CCL_INSTS         { CCL }                    /**< \brief (CCL) Instances List */
+
+#define CMCC              ((Cmcc     *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM     1                          /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS        { CMCC }                   /**< \brief (CMCC) Instances List */
+
+#define DAC               ((Dac      *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define FREQM             ((Freqm    *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM    1                          /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS       { FREQM }                  /**< \brief (FREQM) Instances List */
+
+#define GCLK              ((Gclk     *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define GMAC              ((Gmac     *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM     1                          /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS        { GMAC }                   /**< \brief (GMAC) Instances List */
+
+#define HMATRIX           ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { HMATRIX }                /**< \brief (HMATRIXB) Instances List */
+
+#define ICM               ((Icm      *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM      1                          /**< \brief (ICM) Number of instances */
+#define ICM_INSTS         { ICM }                    /**< \brief (ICM) Instances List */
+
+#define I2S               ((I2s      *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MCLK              ((Mclk     *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM     1                          /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS        { MCLK }                   /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL           ((Oscctrl  *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM  1                          /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS     { OSCCTRL }                /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL        ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1                          /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS  { OSC32KCTRL }             /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC               ((Pac      *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM      1                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC }                    /**< \brief (PAC) Instances List */
+
+#define PCC               ((Pcc      *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM      1                          /**< \brief (PCC) Number of instances */
+#define PCC_INSTS         { PCC }                    /**< \brief (PCC) Instances List */
+
+#define PDEC              ((Pdec     *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM     1                          /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS        { PDEC }                   /**< \brief (PDEC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PUKCC             ((void     *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB         ((void     *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM    1                          /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS       { PUKCC }                  /**< \brief (PUKCC) Instances List */
+
+#define QSPI              ((Qspi     *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM     1                          /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS        { QSPI }                   /**< \brief (QSPI) Instances List */
+
+#define RAMECC            ((Ramecc   *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM   1                          /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS      { RAMECC }                 /**< \brief (RAMECC) Instances List */
+
+#define RSTC              ((Rstc     *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM     1                          /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS        { RSTC }                   /**< \brief (RSTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SDHC0             ((Sdhc     *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC_INST_NUM     1                          /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS        { SDHC0 }                  /**< \brief (SDHC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC              ((Supc     *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM     1                          /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS        { SUPC }                   /**< \brief (SUPC) Instances List */
+
+#define TC0               ((Tc       *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4              ((Tcc      *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM      5                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG              ((Trng     *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM     1                          /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS        { TRNG }                   /**< \brief (TRNG) Instances List */
+
+#define USB               ((Usb      *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+/** \defgroup SAME53J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same53j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE            _UL_(0x00020000) /* 128 kB */
+#define FLASH_SIZE            _UL_(0x00040000) /* 256 kB */
+#define FLASH_PAGE_SIZE       512
+#define FLASH_NB_OF_PAGES     512
+#define FLASH_USER_PAGE_SIZE  512
+#define BKUPRAM_SIZE          _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE             _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR     _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE     _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR      _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE      _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR    _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE    _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR            _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR        _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE        _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR       _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE       _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR             _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR          _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR          _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x61830306)
+#define ADC0_TOUCH_LINES_NUM  32
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAME53J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME53J18A_H */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j19a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j19a.h
new file mode 100644
index 000000000..801952bbd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j19a.h	
@@ -0,0 +1,1027 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME53J19A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53J19A_
+#define _SAME53J19A_
+
+/**
+ * \ingroup SAME53_definitions
+ * \addtogroup SAME53J19A_definitions SAME53J19A definitions
+ * This file defines all structures and symbols for SAME53J19A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+/** \defgroup SAME53J19A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M4 Processor Exceptions Numbers *******************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt      */
+  HardFault_IRQn           = -13,/**<  3 Hard Fault Interrupt        */
+  MemoryManagement_IRQn    = -12,/**<  4 Memory Management Interrupt */
+  BusFault_IRQn            = -11,/**<  5 Bus Fault Interrupt         */
+  UsageFault_IRQn          = -10,/**<  6 Usage Fault Interrupt       */
+  SVCall_IRQn              = -5, /**< 11 SV Call Interrupt           */
+  DebugMonitor_IRQn        = -4, /**< 12 Debug Monitor Interrupt     */
+  PendSV_IRQn              = -2, /**< 14 Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 System Tick Interrupt       */
+  /******  SAME53J19A-specific Interrupt Numbers *********************/
+  PM_IRQn                  =  0, /**<  0 SAME53J19A Power Manager (PM) */
+  MCLK_IRQn                =  1, /**<  1 SAME53J19A Main Clock (MCLK) */
+  OSCCTRL_0_IRQn           =  2, /**<  2 SAME53J19A Oscillators Control (OSCCTRL) IRQ 0 */
+  OSCCTRL_1_IRQn           =  3, /**<  3 SAME53J19A Oscillators Control (OSCCTRL) IRQ 1 */
+  OSCCTRL_2_IRQn           =  4, /**<  4 SAME53J19A Oscillators Control (OSCCTRL) IRQ 2 */
+  OSCCTRL_3_IRQn           =  5, /**<  5 SAME53J19A Oscillators Control (OSCCTRL) IRQ 3 */
+  OSCCTRL_4_IRQn           =  6, /**<  6 SAME53J19A Oscillators Control (OSCCTRL) IRQ 4 */
+  OSC32KCTRL_IRQn          =  7, /**<  7 SAME53J19A 32kHz Oscillators Control (OSC32KCTRL) */
+  SUPC_0_IRQn              =  8, /**<  8 SAME53J19A Supply Controller (SUPC) IRQ 0 */
+  SUPC_1_IRQn              =  9, /**<  9 SAME53J19A Supply Controller (SUPC) IRQ 1 */
+  WDT_IRQn                 = 10, /**< 10 SAME53J19A Watchdog Timer (WDT) */
+  RTC_IRQn                 = 11, /**< 11 SAME53J19A Real-Time Counter (RTC) */
+  EIC_0_IRQn               = 12, /**< 12 SAME53J19A External Interrupt Controller (EIC) IRQ 0 */
+  EIC_1_IRQn               = 13, /**< 13 SAME53J19A External Interrupt Controller (EIC) IRQ 1 */
+  EIC_2_IRQn               = 14, /**< 14 SAME53J19A External Interrupt Controller (EIC) IRQ 2 */
+  EIC_3_IRQn               = 15, /**< 15 SAME53J19A External Interrupt Controller (EIC) IRQ 3 */
+  EIC_4_IRQn               = 16, /**< 16 SAME53J19A External Interrupt Controller (EIC) IRQ 4 */
+  EIC_5_IRQn               = 17, /**< 17 SAME53J19A External Interrupt Controller (EIC) IRQ 5 */
+  EIC_6_IRQn               = 18, /**< 18 SAME53J19A External Interrupt Controller (EIC) IRQ 6 */
+  EIC_7_IRQn               = 19, /**< 19 SAME53J19A External Interrupt Controller (EIC) IRQ 7 */
+  EIC_8_IRQn               = 20, /**< 20 SAME53J19A External Interrupt Controller (EIC) IRQ 8 */
+  EIC_9_IRQn               = 21, /**< 21 SAME53J19A External Interrupt Controller (EIC) IRQ 9 */
+  EIC_10_IRQn              = 22, /**< 22 SAME53J19A External Interrupt Controller (EIC) IRQ 10 */
+  EIC_11_IRQn              = 23, /**< 23 SAME53J19A External Interrupt Controller (EIC) IRQ 11 */
+  EIC_12_IRQn              = 24, /**< 24 SAME53J19A External Interrupt Controller (EIC) IRQ 12 */
+  EIC_13_IRQn              = 25, /**< 25 SAME53J19A External Interrupt Controller (EIC) IRQ 13 */
+  EIC_14_IRQn              = 26, /**< 26 SAME53J19A External Interrupt Controller (EIC) IRQ 14 */
+  EIC_15_IRQn              = 27, /**< 27 SAME53J19A External Interrupt Controller (EIC) IRQ 15 */
+  FREQM_IRQn               = 28, /**< 28 SAME53J19A Frequency Meter (FREQM) */
+  NVMCTRL_0_IRQn           = 29, /**< 29 SAME53J19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+  NVMCTRL_1_IRQn           = 30, /**< 30 SAME53J19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+  DMAC_0_IRQn              = 31, /**< 31 SAME53J19A Direct Memory Access Controller (DMAC) IRQ 0 */
+  DMAC_1_IRQn              = 32, /**< 32 SAME53J19A Direct Memory Access Controller (DMAC) IRQ 1 */
+  DMAC_2_IRQn              = 33, /**< 33 SAME53J19A Direct Memory Access Controller (DMAC) IRQ 2 */
+  DMAC_3_IRQn              = 34, /**< 34 SAME53J19A Direct Memory Access Controller (DMAC) IRQ 3 */
+  DMAC_4_IRQn              = 35, /**< 35 SAME53J19A Direct Memory Access Controller (DMAC) IRQ 4 */
+  EVSYS_0_IRQn             = 36, /**< 36 SAME53J19A Event System Interface (EVSYS) IRQ 0 */
+  EVSYS_1_IRQn             = 37, /**< 37 SAME53J19A Event System Interface (EVSYS) IRQ 1 */
+  EVSYS_2_IRQn             = 38, /**< 38 SAME53J19A Event System Interface (EVSYS) IRQ 2 */
+  EVSYS_3_IRQn             = 39, /**< 39 SAME53J19A Event System Interface (EVSYS) IRQ 3 */
+  EVSYS_4_IRQn             = 40, /**< 40 SAME53J19A Event System Interface (EVSYS) IRQ 4 */
+  PAC_IRQn                 = 41, /**< 41 SAME53J19A Peripheral Access Controller (PAC) */
+  RAMECC_IRQn              = 45, /**< 45 SAME53J19A RAM ECC (RAMECC) */
+  SERCOM0_0_IRQn           = 46, /**< 46 SAME53J19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+  SERCOM0_1_IRQn           = 47, /**< 47 SAME53J19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+  SERCOM0_2_IRQn           = 48, /**< 48 SAME53J19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+  SERCOM0_3_IRQn           = 49, /**< 49 SAME53J19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+  SERCOM1_0_IRQn           = 50, /**< 50 SAME53J19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+  SERCOM1_1_IRQn           = 51, /**< 51 SAME53J19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+  SERCOM1_2_IRQn           = 52, /**< 52 SAME53J19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+  SERCOM1_3_IRQn           = 53, /**< 53 SAME53J19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+  SERCOM2_0_IRQn           = 54, /**< 54 SAME53J19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+  SERCOM2_1_IRQn           = 55, /**< 55 SAME53J19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+  SERCOM2_2_IRQn           = 56, /**< 56 SAME53J19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+  SERCOM2_3_IRQn           = 57, /**< 57 SAME53J19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+  SERCOM3_0_IRQn           = 58, /**< 58 SAME53J19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+  SERCOM3_1_IRQn           = 59, /**< 59 SAME53J19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+  SERCOM3_2_IRQn           = 60, /**< 60 SAME53J19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+  SERCOM3_3_IRQn           = 61, /**< 61 SAME53J19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+  SERCOM4_0_IRQn           = 62, /**< 62 SAME53J19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+  SERCOM4_1_IRQn           = 63, /**< 63 SAME53J19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+  SERCOM4_2_IRQn           = 64, /**< 64 SAME53J19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+  SERCOM4_3_IRQn           = 65, /**< 65 SAME53J19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+  SERCOM5_0_IRQn           = 66, /**< 66 SAME53J19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+  SERCOM5_1_IRQn           = 67, /**< 67 SAME53J19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+  SERCOM5_2_IRQn           = 68, /**< 68 SAME53J19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+  SERCOM5_3_IRQn           = 69, /**< 69 SAME53J19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+  USB_0_IRQn               = 80, /**< 80 SAME53J19A Universal Serial Bus (USB) IRQ 0 */
+  USB_1_IRQn               = 81, /**< 81 SAME53J19A Universal Serial Bus (USB) IRQ 1 */
+  USB_2_IRQn               = 82, /**< 82 SAME53J19A Universal Serial Bus (USB) IRQ 2 */
+  USB_3_IRQn               = 83, /**< 83 SAME53J19A Universal Serial Bus (USB) IRQ 3 */
+  GMAC_IRQn                = 84, /**< 84 SAME53J19A Ethernet MAC (GMAC) */
+  TCC0_0_IRQn              = 85, /**< 85 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 0 */
+  TCC0_1_IRQn              = 86, /**< 86 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 1 */
+  TCC0_2_IRQn              = 87, /**< 87 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 2 */
+  TCC0_3_IRQn              = 88, /**< 88 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 3 */
+  TCC0_4_IRQn              = 89, /**< 89 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 4 */
+  TCC0_5_IRQn              = 90, /**< 90 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 5 */
+  TCC0_6_IRQn              = 91, /**< 91 SAME53J19A Timer Counter Control 0 (TCC0) IRQ 6 */
+  TCC1_0_IRQn              = 92, /**< 92 SAME53J19A Timer Counter Control 1 (TCC1) IRQ 0 */
+  TCC1_1_IRQn              = 93, /**< 93 SAME53J19A Timer Counter Control 1 (TCC1) IRQ 1 */
+  TCC1_2_IRQn              = 94, /**< 94 SAME53J19A Timer Counter Control 1 (TCC1) IRQ 2 */
+  TCC1_3_IRQn              = 95, /**< 95 SAME53J19A Timer Counter Control 1 (TCC1) IRQ 3 */
+  TCC1_4_IRQn              = 96, /**< 96 SAME53J19A Timer Counter Control 1 (TCC1) IRQ 4 */
+  TCC2_0_IRQn              = 97, /**< 97 SAME53J19A Timer Counter Control 2 (TCC2) IRQ 0 */
+  TCC2_1_IRQn              = 98, /**< 98 SAME53J19A Timer Counter Control 2 (TCC2) IRQ 1 */
+  TCC2_2_IRQn              = 99, /**< 99 SAME53J19A Timer Counter Control 2 (TCC2) IRQ 2 */
+  TCC2_3_IRQn              = 100, /**< 100 SAME53J19A Timer Counter Control 2 (TCC2) IRQ 3 */
+  TCC3_0_IRQn              = 101, /**< 101 SAME53J19A Timer Counter Control 3 (TCC3) IRQ 0 */
+  TCC3_1_IRQn              = 102, /**< 102 SAME53J19A Timer Counter Control 3 (TCC3) IRQ 1 */
+  TCC3_2_IRQn              = 103, /**< 103 SAME53J19A Timer Counter Control 3 (TCC3) IRQ 2 */
+  TCC4_0_IRQn              = 104, /**< 104 SAME53J19A Timer Counter Control 4 (TCC4) IRQ 0 */
+  TCC4_1_IRQn              = 105, /**< 105 SAME53J19A Timer Counter Control 4 (TCC4) IRQ 1 */
+  TCC4_2_IRQn              = 106, /**< 106 SAME53J19A Timer Counter Control 4 (TCC4) IRQ 2 */
+  TC0_IRQn                 = 107, /**< 107 SAME53J19A Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 108, /**< 108 SAME53J19A Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 109, /**< 109 SAME53J19A Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 110, /**< 110 SAME53J19A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 111, /**< 111 SAME53J19A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 112, /**< 112 SAME53J19A Basic Timer Counter 5 (TC5) */
+  PDEC_0_IRQn              = 115, /**< 115 SAME53J19A Quadrature Decodeur (PDEC) IRQ 0 */
+  PDEC_1_IRQn              = 116, /**< 116 SAME53J19A Quadrature Decodeur (PDEC) IRQ 1 */
+  PDEC_2_IRQn              = 117, /**< 117 SAME53J19A Quadrature Decodeur (PDEC) IRQ 2 */
+  ADC0_0_IRQn              = 118, /**< 118 SAME53J19A Analog Digital Converter 0 (ADC0) IRQ 0 */
+  ADC0_1_IRQn              = 119, /**< 119 SAME53J19A Analog Digital Converter 0 (ADC0) IRQ 1 */
+  ADC1_0_IRQn              = 120, /**< 120 SAME53J19A Analog Digital Converter 1 (ADC1) IRQ 0 */
+  ADC1_1_IRQn              = 121, /**< 121 SAME53J19A Analog Digital Converter 1 (ADC1) IRQ 1 */
+  AC_IRQn                  = 122, /**< 122 SAME53J19A Analog Comparators (AC) */
+  DAC_0_IRQn               = 123, /**< 123 SAME53J19A Digital-to-Analog Converter (DAC) IRQ 0 */
+  DAC_1_IRQn               = 124, /**< 124 SAME53J19A Digital-to-Analog Converter (DAC) IRQ 1 */
+  DAC_2_IRQn               = 125, /**< 125 SAME53J19A Digital-to-Analog Converter (DAC) IRQ 2 */
+  DAC_3_IRQn               = 126, /**< 126 SAME53J19A Digital-to-Analog Converter (DAC) IRQ 3 */
+  DAC_4_IRQn               = 127, /**< 127 SAME53J19A Digital-to-Analog Converter (DAC) IRQ 4 */
+  I2S_IRQn                 = 128, /**< 128 SAME53J19A Inter-IC Sound Interface (I2S) */
+  PCC_IRQn                 = 129, /**< 129 SAME53J19A Parallel Capture Controller (PCC) */
+  AES_IRQn                 = 130, /**< 130 SAME53J19A Advanced Encryption Standard (AES) */
+  TRNG_IRQn                = 131, /**< 131 SAME53J19A True Random Generator (TRNG) */
+  ICM_IRQn                 = 132, /**< 132 SAME53J19A Integrity Check Monitor (ICM) */
+  PUKCC_IRQn               = 133, /**< 133 SAME53J19A PUblic-Key Cryptography Controller (PUKCC) */
+  QSPI_IRQn                = 134, /**< 134 SAME53J19A Quad SPI interface (QSPI) */
+  SDHC0_IRQn               = 135, /**< 135 SAME53J19A SD/MMC Host Controller 0 (SDHC0) */
+
+  PERIPH_COUNT_IRQn        = 137  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNonMaskableInt_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManagement_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVCall_Handler;
+  void* pfnDebugMonitor_Handler;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnMCLK_Handler;                  /*  1 Main Clock */
+  void* pfnOSCCTRL_0_Handler;             /*  2 Oscillators Control IRQ 0 */
+  void* pfnOSCCTRL_1_Handler;             /*  3 Oscillators Control IRQ 1 */
+  void* pfnOSCCTRL_2_Handler;             /*  4 Oscillators Control IRQ 2 */
+  void* pfnOSCCTRL_3_Handler;             /*  5 Oscillators Control IRQ 3 */
+  void* pfnOSCCTRL_4_Handler;             /*  6 Oscillators Control IRQ 4 */
+  void* pfnOSC32KCTRL_Handler;            /*  7 32kHz Oscillators Control */
+  void* pfnSUPC_0_Handler;                /*  8 Supply Controller IRQ 0 */
+  void* pfnSUPC_1_Handler;                /*  9 Supply Controller IRQ 1 */
+  void* pfnWDT_Handler;                   /* 10 Watchdog Timer */
+  void* pfnRTC_Handler;                   /* 11 Real-Time Counter */
+  void* pfnEIC_0_Handler;                 /* 12 External Interrupt Controller IRQ 0 */
+  void* pfnEIC_1_Handler;                 /* 13 External Interrupt Controller IRQ 1 */
+  void* pfnEIC_2_Handler;                 /* 14 External Interrupt Controller IRQ 2 */
+  void* pfnEIC_3_Handler;                 /* 15 External Interrupt Controller IRQ 3 */
+  void* pfnEIC_4_Handler;                 /* 16 External Interrupt Controller IRQ 4 */
+  void* pfnEIC_5_Handler;                 /* 17 External Interrupt Controller IRQ 5 */
+  void* pfnEIC_6_Handler;                 /* 18 External Interrupt Controller IRQ 6 */
+  void* pfnEIC_7_Handler;                 /* 19 External Interrupt Controller IRQ 7 */
+  void* pfnEIC_8_Handler;                 /* 20 External Interrupt Controller IRQ 8 */
+  void* pfnEIC_9_Handler;                 /* 21 External Interrupt Controller IRQ 9 */
+  void* pfnEIC_10_Handler;                /* 22 External Interrupt Controller IRQ 10 */
+  void* pfnEIC_11_Handler;                /* 23 External Interrupt Controller IRQ 11 */
+  void* pfnEIC_12_Handler;                /* 24 External Interrupt Controller IRQ 12 */
+  void* pfnEIC_13_Handler;                /* 25 External Interrupt Controller IRQ 13 */
+  void* pfnEIC_14_Handler;                /* 26 External Interrupt Controller IRQ 14 */
+  void* pfnEIC_15_Handler;                /* 27 External Interrupt Controller IRQ 15 */
+  void* pfnFREQM_Handler;                 /* 28 Frequency Meter */
+  void* pfnNVMCTRL_0_Handler;             /* 29 Non-Volatile Memory Controller IRQ 0 */
+  void* pfnNVMCTRL_1_Handler;             /* 30 Non-Volatile Memory Controller IRQ 1 */
+  void* pfnDMAC_0_Handler;                /* 31 Direct Memory Access Controller IRQ 0 */
+  void* pfnDMAC_1_Handler;                /* 32 Direct Memory Access Controller IRQ 1 */
+  void* pfnDMAC_2_Handler;                /* 33 Direct Memory Access Controller IRQ 2 */
+  void* pfnDMAC_3_Handler;                /* 34 Direct Memory Access Controller IRQ 3 */
+  void* pfnDMAC_4_Handler;                /* 35 Direct Memory Access Controller IRQ 4 */
+  void* pfnEVSYS_0_Handler;               /* 36 Event System Interface IRQ 0 */
+  void* pfnEVSYS_1_Handler;               /* 37 Event System Interface IRQ 1 */
+  void* pfnEVSYS_2_Handler;               /* 38 Event System Interface IRQ 2 */
+  void* pfnEVSYS_3_Handler;               /* 39 Event System Interface IRQ 3 */
+  void* pfnEVSYS_4_Handler;               /* 40 Event System Interface IRQ 4 */
+  void* pfnPAC_Handler;                   /* 41 Peripheral Access Controller */
+  void* pvReserved42;
+  void* pvReserved43;
+  void* pvReserved44;
+  void* pfnRAMECC_Handler;                /* 45 RAM ECC */
+  void* pfnSERCOM0_0_Handler;             /* 46 Serial Communication Interface 0 IRQ 0 */
+  void* pfnSERCOM0_1_Handler;             /* 47 Serial Communication Interface 0 IRQ 1 */
+  void* pfnSERCOM0_2_Handler;             /* 48 Serial Communication Interface 0 IRQ 2 */
+  void* pfnSERCOM0_3_Handler;             /* 49 Serial Communication Interface 0 IRQ 3 */
+  void* pfnSERCOM1_0_Handler;             /* 50 Serial Communication Interface 1 IRQ 0 */
+  void* pfnSERCOM1_1_Handler;             /* 51 Serial Communication Interface 1 IRQ 1 */
+  void* pfnSERCOM1_2_Handler;             /* 52 Serial Communication Interface 1 IRQ 2 */
+  void* pfnSERCOM1_3_Handler;             /* 53 Serial Communication Interface 1 IRQ 3 */
+  void* pfnSERCOM2_0_Handler;             /* 54 Serial Communication Interface 2 IRQ 0 */
+  void* pfnSERCOM2_1_Handler;             /* 55 Serial Communication Interface 2 IRQ 1 */
+  void* pfnSERCOM2_2_Handler;             /* 56 Serial Communication Interface 2 IRQ 2 */
+  void* pfnSERCOM2_3_Handler;             /* 57 Serial Communication Interface 2 IRQ 3 */
+  void* pfnSERCOM3_0_Handler;             /* 58 Serial Communication Interface 3 IRQ 0 */
+  void* pfnSERCOM3_1_Handler;             /* 59 Serial Communication Interface 3 IRQ 1 */
+  void* pfnSERCOM3_2_Handler;             /* 60 Serial Communication Interface 3 IRQ 2 */
+  void* pfnSERCOM3_3_Handler;             /* 61 Serial Communication Interface 3 IRQ 3 */
+  void* pfnSERCOM4_0_Handler;             /* 62 Serial Communication Interface 4 IRQ 0 */
+  void* pfnSERCOM4_1_Handler;             /* 63 Serial Communication Interface 4 IRQ 1 */
+  void* pfnSERCOM4_2_Handler;             /* 64 Serial Communication Interface 4 IRQ 2 */
+  void* pfnSERCOM4_3_Handler;             /* 65 Serial Communication Interface 4 IRQ 3 */
+  void* pfnSERCOM5_0_Handler;             /* 66 Serial Communication Interface 5 IRQ 0 */
+  void* pfnSERCOM5_1_Handler;             /* 67 Serial Communication Interface 5 IRQ 1 */
+  void* pfnSERCOM5_2_Handler;             /* 68 Serial Communication Interface 5 IRQ 2 */
+  void* pfnSERCOM5_3_Handler;             /* 69 Serial Communication Interface 5 IRQ 3 */
+  void* pvReserved70;
+  void* pvReserved71;
+  void* pvReserved72;
+  void* pvReserved73;
+  void* pvReserved74;
+  void* pvReserved75;
+  void* pvReserved76;
+  void* pvReserved77;
+  void* pvReserved78;
+  void* pvReserved79;
+  void* pfnUSB_0_Handler;                 /* 80 Universal Serial Bus IRQ 0 */
+  void* pfnUSB_1_Handler;                 /* 81 Universal Serial Bus IRQ 1 */
+  void* pfnUSB_2_Handler;                 /* 82 Universal Serial Bus IRQ 2 */
+  void* pfnUSB_3_Handler;                 /* 83 Universal Serial Bus IRQ 3 */
+  void* pfnGMAC_Handler;                  /* 84 Ethernet MAC */
+  void* pfnTCC0_0_Handler;                /* 85 Timer Counter Control 0 IRQ 0 */
+  void* pfnTCC0_1_Handler;                /* 86 Timer Counter Control 0 IRQ 1 */
+  void* pfnTCC0_2_Handler;                /* 87 Timer Counter Control 0 IRQ 2 */
+  void* pfnTCC0_3_Handler;                /* 88 Timer Counter Control 0 IRQ 3 */
+  void* pfnTCC0_4_Handler;                /* 89 Timer Counter Control 0 IRQ 4 */
+  void* pfnTCC0_5_Handler;                /* 90 Timer Counter Control 0 IRQ 5 */
+  void* pfnTCC0_6_Handler;                /* 91 Timer Counter Control 0 IRQ 6 */
+  void* pfnTCC1_0_Handler;                /* 92 Timer Counter Control 1 IRQ 0 */
+  void* pfnTCC1_1_Handler;                /* 93 Timer Counter Control 1 IRQ 1 */
+  void* pfnTCC1_2_Handler;                /* 94 Timer Counter Control 1 IRQ 2 */
+  void* pfnTCC1_3_Handler;                /* 95 Timer Counter Control 1 IRQ 3 */
+  void* pfnTCC1_4_Handler;                /* 96 Timer Counter Control 1 IRQ 4 */
+  void* pfnTCC2_0_Handler;                /* 97 Timer Counter Control 2 IRQ 0 */
+  void* pfnTCC2_1_Handler;                /* 98 Timer Counter Control 2 IRQ 1 */
+  void* pfnTCC2_2_Handler;                /* 99 Timer Counter Control 2 IRQ 2 */
+  void* pfnTCC2_3_Handler;                /* 100 Timer Counter Control 2 IRQ 3 */
+  void* pfnTCC3_0_Handler;                /* 101 Timer Counter Control 3 IRQ 0 */
+  void* pfnTCC3_1_Handler;                /* 102 Timer Counter Control 3 IRQ 1 */
+  void* pfnTCC3_2_Handler;                /* 103 Timer Counter Control 3 IRQ 2 */
+  void* pfnTCC4_0_Handler;                /* 104 Timer Counter Control 4 IRQ 0 */
+  void* pfnTCC4_1_Handler;                /* 105 Timer Counter Control 4 IRQ 1 */
+  void* pfnTCC4_2_Handler;                /* 106 Timer Counter Control 4 IRQ 2 */
+  void* pfnTC0_Handler;                   /* 107 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 108 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 109 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 110 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 111 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 112 Basic Timer Counter 5 */
+  void* pvReserved113;
+  void* pvReserved114;
+  void* pfnPDEC_0_Handler;                /* 115 Quadrature Decodeur IRQ 0 */
+  void* pfnPDEC_1_Handler;                /* 116 Quadrature Decodeur IRQ 1 */
+  void* pfnPDEC_2_Handler;                /* 117 Quadrature Decodeur IRQ 2 */
+  void* pfnADC0_0_Handler;                /* 118 Analog Digital Converter 0 IRQ 0 */
+  void* pfnADC0_1_Handler;                /* 119 Analog Digital Converter 0 IRQ 1 */
+  void* pfnADC1_0_Handler;                /* 120 Analog Digital Converter 1 IRQ 0 */
+  void* pfnADC1_1_Handler;                /* 121 Analog Digital Converter 1 IRQ 1 */
+  void* pfnAC_Handler;                    /* 122 Analog Comparators */
+  void* pfnDAC_0_Handler;                 /* 123 Digital-to-Analog Converter IRQ 0 */
+  void* pfnDAC_1_Handler;                 /* 124 Digital-to-Analog Converter IRQ 1 */
+  void* pfnDAC_2_Handler;                 /* 125 Digital-to-Analog Converter IRQ 2 */
+  void* pfnDAC_3_Handler;                 /* 126 Digital-to-Analog Converter IRQ 3 */
+  void* pfnDAC_4_Handler;                 /* 127 Digital-to-Analog Converter IRQ 4 */
+  void* pfnI2S_Handler;                   /* 128 Inter-IC Sound Interface */
+  void* pfnPCC_Handler;                   /* 129 Parallel Capture Controller */
+  void* pfnAES_Handler;                   /* 130 Advanced Encryption Standard */
+  void* pfnTRNG_Handler;                  /* 131 True Random Generator */
+  void* pfnICM_Handler;                   /* 132 Integrity Check Monitor */
+  void* pfnPUKCC_Handler;                 /* 133 PUblic-Key Cryptography Controller */
+  void* pfnQSPI_Handler;                  /* 134 Quad SPI interface */
+  void* pfnSDHC0_Handler;                 /* 135 SD/MMC Host Controller 0 */
+  void* pvReserved136;
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler               ( void );
+void NonMaskableInt_Handler      ( void );
+void HardFault_Handler           ( void );
+void MemManagement_Handler       ( void );
+void BusFault_Handler            ( void );
+void UsageFault_Handler          ( void );
+void SVCall_Handler              ( void );
+void DebugMonitor_Handler        ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void MCLK_Handler                ( void );
+void OSCCTRL_0_Handler           ( void );
+void OSCCTRL_1_Handler           ( void );
+void OSCCTRL_2_Handler           ( void );
+void OSCCTRL_3_Handler           ( void );
+void OSCCTRL_4_Handler           ( void );
+void OSC32KCTRL_Handler          ( void );
+void SUPC_0_Handler              ( void );
+void SUPC_1_Handler              ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_0_Handler               ( void );
+void EIC_1_Handler               ( void );
+void EIC_2_Handler               ( void );
+void EIC_3_Handler               ( void );
+void EIC_4_Handler               ( void );
+void EIC_5_Handler               ( void );
+void EIC_6_Handler               ( void );
+void EIC_7_Handler               ( void );
+void EIC_8_Handler               ( void );
+void EIC_9_Handler               ( void );
+void EIC_10_Handler              ( void );
+void EIC_11_Handler              ( void );
+void EIC_12_Handler              ( void );
+void EIC_13_Handler              ( void );
+void EIC_14_Handler              ( void );
+void EIC_15_Handler              ( void );
+void FREQM_Handler               ( void );
+void NVMCTRL_0_Handler           ( void );
+void NVMCTRL_1_Handler           ( void );
+void DMAC_0_Handler              ( void );
+void DMAC_1_Handler              ( void );
+void DMAC_2_Handler              ( void );
+void DMAC_3_Handler              ( void );
+void DMAC_4_Handler              ( void );
+void EVSYS_0_Handler             ( void );
+void EVSYS_1_Handler             ( void );
+void EVSYS_2_Handler             ( void );
+void EVSYS_3_Handler             ( void );
+void EVSYS_4_Handler             ( void );
+void PAC_Handler                 ( void );
+void RAMECC_Handler              ( void );
+void SERCOM0_0_Handler           ( void );
+void SERCOM0_1_Handler           ( void );
+void SERCOM0_2_Handler           ( void );
+void SERCOM0_3_Handler           ( void );
+void SERCOM1_0_Handler           ( void );
+void SERCOM1_1_Handler           ( void );
+void SERCOM1_2_Handler           ( void );
+void SERCOM1_3_Handler           ( void );
+void SERCOM2_0_Handler           ( void );
+void SERCOM2_1_Handler           ( void );
+void SERCOM2_2_Handler           ( void );
+void SERCOM2_3_Handler           ( void );
+void SERCOM3_0_Handler           ( void );
+void SERCOM3_1_Handler           ( void );
+void SERCOM3_2_Handler           ( void );
+void SERCOM3_3_Handler           ( void );
+void SERCOM4_0_Handler           ( void );
+void SERCOM4_1_Handler           ( void );
+void SERCOM4_2_Handler           ( void );
+void SERCOM4_3_Handler           ( void );
+void SERCOM5_0_Handler           ( void );
+void SERCOM5_1_Handler           ( void );
+void SERCOM5_2_Handler           ( void );
+void SERCOM5_3_Handler           ( void );
+void USB_0_Handler               ( void );
+void USB_1_Handler               ( void );
+void USB_2_Handler               ( void );
+void USB_3_Handler               ( void );
+void GMAC_Handler                ( void );
+void TCC0_0_Handler              ( void );
+void TCC0_1_Handler              ( void );
+void TCC0_2_Handler              ( void );
+void TCC0_3_Handler              ( void );
+void TCC0_4_Handler              ( void );
+void TCC0_5_Handler              ( void );
+void TCC0_6_Handler              ( void );
+void TCC1_0_Handler              ( void );
+void TCC1_1_Handler              ( void );
+void TCC1_2_Handler              ( void );
+void TCC1_3_Handler              ( void );
+void TCC1_4_Handler              ( void );
+void TCC2_0_Handler              ( void );
+void TCC2_1_Handler              ( void );
+void TCC2_2_Handler              ( void );
+void TCC2_3_Handler              ( void );
+void TCC3_0_Handler              ( void );
+void TCC3_1_Handler              ( void );
+void TCC3_2_Handler              ( void );
+void TCC4_0_Handler              ( void );
+void TCC4_1_Handler              ( void );
+void TCC4_2_Handler              ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void PDEC_0_Handler              ( void );
+void PDEC_1_Handler              ( void );
+void PDEC_2_Handler              ( void );
+void ADC0_0_Handler              ( void );
+void ADC0_1_Handler              ( void );
+void ADC1_0_Handler              ( void );
+void ADC1_1_Handler              ( void );
+void AC_Handler                  ( void );
+void DAC_0_Handler               ( void );
+void DAC_1_Handler               ( void );
+void DAC_2_Handler               ( void );
+void DAC_3_Handler               ( void );
+void DAC_4_Handler               ( void );
+void I2S_Handler                 ( void );
+void PCC_Handler                 ( void );
+void AES_Handler                 ( void );
+void TRNG_Handler                ( void );
+void ICM_Handler                 ( void );
+void PUKCC_Handler               ( void );
+void QSPI_Handler                ( void );
+void SDHC0_Handler               ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              1         /*!< Core revision r0p1 */
+#define __DEBUG_LVL            3         /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT          1         /*!< FPU present or not */
+#define __MPU_PRESENT          1         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       3         /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL            2         /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same53.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME53J19A */
+/* ************************************************************************** */
+/** \defgroup SAME53J19A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+/** \defgroup SAME53J19A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/pukcc.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/supc.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+/** \defgroup SAME53J19A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC            0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_MCLK           2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC           3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL        4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL     5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC           6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK           7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC           10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM         11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0       12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0           14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB           32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC          35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT          36 /**< \brief Port Module (PORT) */
+#define ID_DMAC          37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX       38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS         39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2       41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2           45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_RAMECC        48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_GMAC          66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2          67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3          68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4           69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC          71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC            72 /**< \brief Analog Comparators (AC) */
+#define ID_AES           73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG          74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM           75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC         76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI          77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL           78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4       96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC4         100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_ADC0         103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1         104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC          105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S          106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC          107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0        128 /**< \brief SD/MMC Host Controller (SDHC0) */
+
+#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+/** \defgroup SAME53J19A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0                          (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1                          (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES                           (0x42002400) /**< \brief (AES) APB Base Address */
+#define CCL                           (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC                          (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC                           (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM                         (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK                          (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC                          (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX                       (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM                           (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S                           (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK                          (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL                       (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL                    (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC                           (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC                           (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC                          (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC                         (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB                     (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI                          (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC                        (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC                          (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC                           (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0                         (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SERCOM0                       (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SUPC                          (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TC0                           (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4                          (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG                          (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB                           (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC0              ((Adc      *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1              ((Adc      *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM      2                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC0, ADC1 }             /**< \brief (ADC) Instances List */
+
+#define AES               ((Aes      *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM      1                          /**< \brief (AES) Number of instances */
+#define AES_INSTS         { AES }                    /**< \brief (AES) Instances List */
+
+#define CCL               ((Ccl      *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM      1                          /**< \brief (CCL) Number of instances */
+#define CCL_INSTS         { CCL }                    /**< \brief (CCL) Instances List */
+
+#define CMCC              ((Cmcc     *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM     1                          /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS        { CMCC }                   /**< \brief (CMCC) Instances List */
+
+#define DAC               ((Dac      *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define FREQM             ((Freqm    *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM    1                          /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS       { FREQM }                  /**< \brief (FREQM) Instances List */
+
+#define GCLK              ((Gclk     *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define GMAC              ((Gmac     *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM     1                          /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS        { GMAC }                   /**< \brief (GMAC) Instances List */
+
+#define HMATRIX           ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { HMATRIX }                /**< \brief (HMATRIXB) Instances List */
+
+#define ICM               ((Icm      *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM      1                          /**< \brief (ICM) Number of instances */
+#define ICM_INSTS         { ICM }                    /**< \brief (ICM) Instances List */
+
+#define I2S               ((I2s      *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MCLK              ((Mclk     *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM     1                          /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS        { MCLK }                   /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL           ((Oscctrl  *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM  1                          /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS     { OSCCTRL }                /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL        ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1                          /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS  { OSC32KCTRL }             /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC               ((Pac      *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM      1                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC }                    /**< \brief (PAC) Instances List */
+
+#define PCC               ((Pcc      *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM      1                          /**< \brief (PCC) Number of instances */
+#define PCC_INSTS         { PCC }                    /**< \brief (PCC) Instances List */
+
+#define PDEC              ((Pdec     *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM     1                          /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS        { PDEC }                   /**< \brief (PDEC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PUKCC             ((void     *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB         ((void     *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM    1                          /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS       { PUKCC }                  /**< \brief (PUKCC) Instances List */
+
+#define QSPI              ((Qspi     *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM     1                          /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS        { QSPI }                   /**< \brief (QSPI) Instances List */
+
+#define RAMECC            ((Ramecc   *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM   1                          /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS      { RAMECC }                 /**< \brief (RAMECC) Instances List */
+
+#define RSTC              ((Rstc     *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM     1                          /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS        { RSTC }                   /**< \brief (RSTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SDHC0             ((Sdhc     *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC_INST_NUM     1                          /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS        { SDHC0 }                  /**< \brief (SDHC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC              ((Supc     *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM     1                          /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS        { SUPC }                   /**< \brief (SUPC) Instances List */
+
+#define TC0               ((Tc       *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4              ((Tcc      *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM      5                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG              ((Trng     *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM     1                          /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS        { TRNG }                   /**< \brief (TRNG) Instances List */
+
+#define USB               ((Usb      *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+/** \defgroup SAME53J19A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same53j19a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE            _UL_(0x00030000) /* 192 kB */
+#define FLASH_SIZE            _UL_(0x00080000) /* 512 kB */
+#define FLASH_PAGE_SIZE       512
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  512
+#define BKUPRAM_SIZE          _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE             _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR     _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE     _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR      _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE      _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR    _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE    _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR            _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR        _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE        _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR       _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE       _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR             _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR          _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR          _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x61830305)
+#define ADC0_TOUCH_LINES_NUM  32
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAME53J19A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME53J19A_H */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j20a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j20a.h
new file mode 100644
index 000000000..99f76ab6c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53j20a.h	
@@ -0,0 +1,1027 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME53J20A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53J20A_
+#define _SAME53J20A_
+
+/**
+ * \ingroup SAME53_definitions
+ * \addtogroup SAME53J20A_definitions SAME53J20A definitions
+ * This file defines all structures and symbols for SAME53J20A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+/** \defgroup SAME53J20A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M4 Processor Exceptions Numbers *******************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt      */
+  HardFault_IRQn           = -13,/**<  3 Hard Fault Interrupt        */
+  MemoryManagement_IRQn    = -12,/**<  4 Memory Management Interrupt */
+  BusFault_IRQn            = -11,/**<  5 Bus Fault Interrupt         */
+  UsageFault_IRQn          = -10,/**<  6 Usage Fault Interrupt       */
+  SVCall_IRQn              = -5, /**< 11 SV Call Interrupt           */
+  DebugMonitor_IRQn        = -4, /**< 12 Debug Monitor Interrupt     */
+  PendSV_IRQn              = -2, /**< 14 Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 System Tick Interrupt       */
+  /******  SAME53J20A-specific Interrupt Numbers *********************/
+  PM_IRQn                  =  0, /**<  0 SAME53J20A Power Manager (PM) */
+  MCLK_IRQn                =  1, /**<  1 SAME53J20A Main Clock (MCLK) */
+  OSCCTRL_0_IRQn           =  2, /**<  2 SAME53J20A Oscillators Control (OSCCTRL) IRQ 0 */
+  OSCCTRL_1_IRQn           =  3, /**<  3 SAME53J20A Oscillators Control (OSCCTRL) IRQ 1 */
+  OSCCTRL_2_IRQn           =  4, /**<  4 SAME53J20A Oscillators Control (OSCCTRL) IRQ 2 */
+  OSCCTRL_3_IRQn           =  5, /**<  5 SAME53J20A Oscillators Control (OSCCTRL) IRQ 3 */
+  OSCCTRL_4_IRQn           =  6, /**<  6 SAME53J20A Oscillators Control (OSCCTRL) IRQ 4 */
+  OSC32KCTRL_IRQn          =  7, /**<  7 SAME53J20A 32kHz Oscillators Control (OSC32KCTRL) */
+  SUPC_0_IRQn              =  8, /**<  8 SAME53J20A Supply Controller (SUPC) IRQ 0 */
+  SUPC_1_IRQn              =  9, /**<  9 SAME53J20A Supply Controller (SUPC) IRQ 1 */
+  WDT_IRQn                 = 10, /**< 10 SAME53J20A Watchdog Timer (WDT) */
+  RTC_IRQn                 = 11, /**< 11 SAME53J20A Real-Time Counter (RTC) */
+  EIC_0_IRQn               = 12, /**< 12 SAME53J20A External Interrupt Controller (EIC) IRQ 0 */
+  EIC_1_IRQn               = 13, /**< 13 SAME53J20A External Interrupt Controller (EIC) IRQ 1 */
+  EIC_2_IRQn               = 14, /**< 14 SAME53J20A External Interrupt Controller (EIC) IRQ 2 */
+  EIC_3_IRQn               = 15, /**< 15 SAME53J20A External Interrupt Controller (EIC) IRQ 3 */
+  EIC_4_IRQn               = 16, /**< 16 SAME53J20A External Interrupt Controller (EIC) IRQ 4 */
+  EIC_5_IRQn               = 17, /**< 17 SAME53J20A External Interrupt Controller (EIC) IRQ 5 */
+  EIC_6_IRQn               = 18, /**< 18 SAME53J20A External Interrupt Controller (EIC) IRQ 6 */
+  EIC_7_IRQn               = 19, /**< 19 SAME53J20A External Interrupt Controller (EIC) IRQ 7 */
+  EIC_8_IRQn               = 20, /**< 20 SAME53J20A External Interrupt Controller (EIC) IRQ 8 */
+  EIC_9_IRQn               = 21, /**< 21 SAME53J20A External Interrupt Controller (EIC) IRQ 9 */
+  EIC_10_IRQn              = 22, /**< 22 SAME53J20A External Interrupt Controller (EIC) IRQ 10 */
+  EIC_11_IRQn              = 23, /**< 23 SAME53J20A External Interrupt Controller (EIC) IRQ 11 */
+  EIC_12_IRQn              = 24, /**< 24 SAME53J20A External Interrupt Controller (EIC) IRQ 12 */
+  EIC_13_IRQn              = 25, /**< 25 SAME53J20A External Interrupt Controller (EIC) IRQ 13 */
+  EIC_14_IRQn              = 26, /**< 26 SAME53J20A External Interrupt Controller (EIC) IRQ 14 */
+  EIC_15_IRQn              = 27, /**< 27 SAME53J20A External Interrupt Controller (EIC) IRQ 15 */
+  FREQM_IRQn               = 28, /**< 28 SAME53J20A Frequency Meter (FREQM) */
+  NVMCTRL_0_IRQn           = 29, /**< 29 SAME53J20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+  NVMCTRL_1_IRQn           = 30, /**< 30 SAME53J20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+  DMAC_0_IRQn              = 31, /**< 31 SAME53J20A Direct Memory Access Controller (DMAC) IRQ 0 */
+  DMAC_1_IRQn              = 32, /**< 32 SAME53J20A Direct Memory Access Controller (DMAC) IRQ 1 */
+  DMAC_2_IRQn              = 33, /**< 33 SAME53J20A Direct Memory Access Controller (DMAC) IRQ 2 */
+  DMAC_3_IRQn              = 34, /**< 34 SAME53J20A Direct Memory Access Controller (DMAC) IRQ 3 */
+  DMAC_4_IRQn              = 35, /**< 35 SAME53J20A Direct Memory Access Controller (DMAC) IRQ 4 */
+  EVSYS_0_IRQn             = 36, /**< 36 SAME53J20A Event System Interface (EVSYS) IRQ 0 */
+  EVSYS_1_IRQn             = 37, /**< 37 SAME53J20A Event System Interface (EVSYS) IRQ 1 */
+  EVSYS_2_IRQn             = 38, /**< 38 SAME53J20A Event System Interface (EVSYS) IRQ 2 */
+  EVSYS_3_IRQn             = 39, /**< 39 SAME53J20A Event System Interface (EVSYS) IRQ 3 */
+  EVSYS_4_IRQn             = 40, /**< 40 SAME53J20A Event System Interface (EVSYS) IRQ 4 */
+  PAC_IRQn                 = 41, /**< 41 SAME53J20A Peripheral Access Controller (PAC) */
+  RAMECC_IRQn              = 45, /**< 45 SAME53J20A RAM ECC (RAMECC) */
+  SERCOM0_0_IRQn           = 46, /**< 46 SAME53J20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+  SERCOM0_1_IRQn           = 47, /**< 47 SAME53J20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+  SERCOM0_2_IRQn           = 48, /**< 48 SAME53J20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+  SERCOM0_3_IRQn           = 49, /**< 49 SAME53J20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+  SERCOM1_0_IRQn           = 50, /**< 50 SAME53J20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+  SERCOM1_1_IRQn           = 51, /**< 51 SAME53J20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+  SERCOM1_2_IRQn           = 52, /**< 52 SAME53J20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+  SERCOM1_3_IRQn           = 53, /**< 53 SAME53J20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+  SERCOM2_0_IRQn           = 54, /**< 54 SAME53J20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+  SERCOM2_1_IRQn           = 55, /**< 55 SAME53J20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+  SERCOM2_2_IRQn           = 56, /**< 56 SAME53J20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+  SERCOM2_3_IRQn           = 57, /**< 57 SAME53J20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+  SERCOM3_0_IRQn           = 58, /**< 58 SAME53J20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+  SERCOM3_1_IRQn           = 59, /**< 59 SAME53J20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+  SERCOM3_2_IRQn           = 60, /**< 60 SAME53J20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+  SERCOM3_3_IRQn           = 61, /**< 61 SAME53J20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+  SERCOM4_0_IRQn           = 62, /**< 62 SAME53J20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+  SERCOM4_1_IRQn           = 63, /**< 63 SAME53J20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+  SERCOM4_2_IRQn           = 64, /**< 64 SAME53J20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+  SERCOM4_3_IRQn           = 65, /**< 65 SAME53J20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+  SERCOM5_0_IRQn           = 66, /**< 66 SAME53J20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+  SERCOM5_1_IRQn           = 67, /**< 67 SAME53J20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+  SERCOM5_2_IRQn           = 68, /**< 68 SAME53J20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+  SERCOM5_3_IRQn           = 69, /**< 69 SAME53J20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+  USB_0_IRQn               = 80, /**< 80 SAME53J20A Universal Serial Bus (USB) IRQ 0 */
+  USB_1_IRQn               = 81, /**< 81 SAME53J20A Universal Serial Bus (USB) IRQ 1 */
+  USB_2_IRQn               = 82, /**< 82 SAME53J20A Universal Serial Bus (USB) IRQ 2 */
+  USB_3_IRQn               = 83, /**< 83 SAME53J20A Universal Serial Bus (USB) IRQ 3 */
+  GMAC_IRQn                = 84, /**< 84 SAME53J20A Ethernet MAC (GMAC) */
+  TCC0_0_IRQn              = 85, /**< 85 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 0 */
+  TCC0_1_IRQn              = 86, /**< 86 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 1 */
+  TCC0_2_IRQn              = 87, /**< 87 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 2 */
+  TCC0_3_IRQn              = 88, /**< 88 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 3 */
+  TCC0_4_IRQn              = 89, /**< 89 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 4 */
+  TCC0_5_IRQn              = 90, /**< 90 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 5 */
+  TCC0_6_IRQn              = 91, /**< 91 SAME53J20A Timer Counter Control 0 (TCC0) IRQ 6 */
+  TCC1_0_IRQn              = 92, /**< 92 SAME53J20A Timer Counter Control 1 (TCC1) IRQ 0 */
+  TCC1_1_IRQn              = 93, /**< 93 SAME53J20A Timer Counter Control 1 (TCC1) IRQ 1 */
+  TCC1_2_IRQn              = 94, /**< 94 SAME53J20A Timer Counter Control 1 (TCC1) IRQ 2 */
+  TCC1_3_IRQn              = 95, /**< 95 SAME53J20A Timer Counter Control 1 (TCC1) IRQ 3 */
+  TCC1_4_IRQn              = 96, /**< 96 SAME53J20A Timer Counter Control 1 (TCC1) IRQ 4 */
+  TCC2_0_IRQn              = 97, /**< 97 SAME53J20A Timer Counter Control 2 (TCC2) IRQ 0 */
+  TCC2_1_IRQn              = 98, /**< 98 SAME53J20A Timer Counter Control 2 (TCC2) IRQ 1 */
+  TCC2_2_IRQn              = 99, /**< 99 SAME53J20A Timer Counter Control 2 (TCC2) IRQ 2 */
+  TCC2_3_IRQn              = 100, /**< 100 SAME53J20A Timer Counter Control 2 (TCC2) IRQ 3 */
+  TCC3_0_IRQn              = 101, /**< 101 SAME53J20A Timer Counter Control 3 (TCC3) IRQ 0 */
+  TCC3_1_IRQn              = 102, /**< 102 SAME53J20A Timer Counter Control 3 (TCC3) IRQ 1 */
+  TCC3_2_IRQn              = 103, /**< 103 SAME53J20A Timer Counter Control 3 (TCC3) IRQ 2 */
+  TCC4_0_IRQn              = 104, /**< 104 SAME53J20A Timer Counter Control 4 (TCC4) IRQ 0 */
+  TCC4_1_IRQn              = 105, /**< 105 SAME53J20A Timer Counter Control 4 (TCC4) IRQ 1 */
+  TCC4_2_IRQn              = 106, /**< 106 SAME53J20A Timer Counter Control 4 (TCC4) IRQ 2 */
+  TC0_IRQn                 = 107, /**< 107 SAME53J20A Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 108, /**< 108 SAME53J20A Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 109, /**< 109 SAME53J20A Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 110, /**< 110 SAME53J20A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 111, /**< 111 SAME53J20A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 112, /**< 112 SAME53J20A Basic Timer Counter 5 (TC5) */
+  PDEC_0_IRQn              = 115, /**< 115 SAME53J20A Quadrature Decodeur (PDEC) IRQ 0 */
+  PDEC_1_IRQn              = 116, /**< 116 SAME53J20A Quadrature Decodeur (PDEC) IRQ 1 */
+  PDEC_2_IRQn              = 117, /**< 117 SAME53J20A Quadrature Decodeur (PDEC) IRQ 2 */
+  ADC0_0_IRQn              = 118, /**< 118 SAME53J20A Analog Digital Converter 0 (ADC0) IRQ 0 */
+  ADC0_1_IRQn              = 119, /**< 119 SAME53J20A Analog Digital Converter 0 (ADC0) IRQ 1 */
+  ADC1_0_IRQn              = 120, /**< 120 SAME53J20A Analog Digital Converter 1 (ADC1) IRQ 0 */
+  ADC1_1_IRQn              = 121, /**< 121 SAME53J20A Analog Digital Converter 1 (ADC1) IRQ 1 */
+  AC_IRQn                  = 122, /**< 122 SAME53J20A Analog Comparators (AC) */
+  DAC_0_IRQn               = 123, /**< 123 SAME53J20A Digital-to-Analog Converter (DAC) IRQ 0 */
+  DAC_1_IRQn               = 124, /**< 124 SAME53J20A Digital-to-Analog Converter (DAC) IRQ 1 */
+  DAC_2_IRQn               = 125, /**< 125 SAME53J20A Digital-to-Analog Converter (DAC) IRQ 2 */
+  DAC_3_IRQn               = 126, /**< 126 SAME53J20A Digital-to-Analog Converter (DAC) IRQ 3 */
+  DAC_4_IRQn               = 127, /**< 127 SAME53J20A Digital-to-Analog Converter (DAC) IRQ 4 */
+  I2S_IRQn                 = 128, /**< 128 SAME53J20A Inter-IC Sound Interface (I2S) */
+  PCC_IRQn                 = 129, /**< 129 SAME53J20A Parallel Capture Controller (PCC) */
+  AES_IRQn                 = 130, /**< 130 SAME53J20A Advanced Encryption Standard (AES) */
+  TRNG_IRQn                = 131, /**< 131 SAME53J20A True Random Generator (TRNG) */
+  ICM_IRQn                 = 132, /**< 132 SAME53J20A Integrity Check Monitor (ICM) */
+  PUKCC_IRQn               = 133, /**< 133 SAME53J20A PUblic-Key Cryptography Controller (PUKCC) */
+  QSPI_IRQn                = 134, /**< 134 SAME53J20A Quad SPI interface (QSPI) */
+  SDHC0_IRQn               = 135, /**< 135 SAME53J20A SD/MMC Host Controller 0 (SDHC0) */
+
+  PERIPH_COUNT_IRQn        = 137  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNonMaskableInt_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManagement_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVCall_Handler;
+  void* pfnDebugMonitor_Handler;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnMCLK_Handler;                  /*  1 Main Clock */
+  void* pfnOSCCTRL_0_Handler;             /*  2 Oscillators Control IRQ 0 */
+  void* pfnOSCCTRL_1_Handler;             /*  3 Oscillators Control IRQ 1 */
+  void* pfnOSCCTRL_2_Handler;             /*  4 Oscillators Control IRQ 2 */
+  void* pfnOSCCTRL_3_Handler;             /*  5 Oscillators Control IRQ 3 */
+  void* pfnOSCCTRL_4_Handler;             /*  6 Oscillators Control IRQ 4 */
+  void* pfnOSC32KCTRL_Handler;            /*  7 32kHz Oscillators Control */
+  void* pfnSUPC_0_Handler;                /*  8 Supply Controller IRQ 0 */
+  void* pfnSUPC_1_Handler;                /*  9 Supply Controller IRQ 1 */
+  void* pfnWDT_Handler;                   /* 10 Watchdog Timer */
+  void* pfnRTC_Handler;                   /* 11 Real-Time Counter */
+  void* pfnEIC_0_Handler;                 /* 12 External Interrupt Controller IRQ 0 */
+  void* pfnEIC_1_Handler;                 /* 13 External Interrupt Controller IRQ 1 */
+  void* pfnEIC_2_Handler;                 /* 14 External Interrupt Controller IRQ 2 */
+  void* pfnEIC_3_Handler;                 /* 15 External Interrupt Controller IRQ 3 */
+  void* pfnEIC_4_Handler;                 /* 16 External Interrupt Controller IRQ 4 */
+  void* pfnEIC_5_Handler;                 /* 17 External Interrupt Controller IRQ 5 */
+  void* pfnEIC_6_Handler;                 /* 18 External Interrupt Controller IRQ 6 */
+  void* pfnEIC_7_Handler;                 /* 19 External Interrupt Controller IRQ 7 */
+  void* pfnEIC_8_Handler;                 /* 20 External Interrupt Controller IRQ 8 */
+  void* pfnEIC_9_Handler;                 /* 21 External Interrupt Controller IRQ 9 */
+  void* pfnEIC_10_Handler;                /* 22 External Interrupt Controller IRQ 10 */
+  void* pfnEIC_11_Handler;                /* 23 External Interrupt Controller IRQ 11 */
+  void* pfnEIC_12_Handler;                /* 24 External Interrupt Controller IRQ 12 */
+  void* pfnEIC_13_Handler;                /* 25 External Interrupt Controller IRQ 13 */
+  void* pfnEIC_14_Handler;                /* 26 External Interrupt Controller IRQ 14 */
+  void* pfnEIC_15_Handler;                /* 27 External Interrupt Controller IRQ 15 */
+  void* pfnFREQM_Handler;                 /* 28 Frequency Meter */
+  void* pfnNVMCTRL_0_Handler;             /* 29 Non-Volatile Memory Controller IRQ 0 */
+  void* pfnNVMCTRL_1_Handler;             /* 30 Non-Volatile Memory Controller IRQ 1 */
+  void* pfnDMAC_0_Handler;                /* 31 Direct Memory Access Controller IRQ 0 */
+  void* pfnDMAC_1_Handler;                /* 32 Direct Memory Access Controller IRQ 1 */
+  void* pfnDMAC_2_Handler;                /* 33 Direct Memory Access Controller IRQ 2 */
+  void* pfnDMAC_3_Handler;                /* 34 Direct Memory Access Controller IRQ 3 */
+  void* pfnDMAC_4_Handler;                /* 35 Direct Memory Access Controller IRQ 4 */
+  void* pfnEVSYS_0_Handler;               /* 36 Event System Interface IRQ 0 */
+  void* pfnEVSYS_1_Handler;               /* 37 Event System Interface IRQ 1 */
+  void* pfnEVSYS_2_Handler;               /* 38 Event System Interface IRQ 2 */
+  void* pfnEVSYS_3_Handler;               /* 39 Event System Interface IRQ 3 */
+  void* pfnEVSYS_4_Handler;               /* 40 Event System Interface IRQ 4 */
+  void* pfnPAC_Handler;                   /* 41 Peripheral Access Controller */
+  void* pvReserved42;
+  void* pvReserved43;
+  void* pvReserved44;
+  void* pfnRAMECC_Handler;                /* 45 RAM ECC */
+  void* pfnSERCOM0_0_Handler;             /* 46 Serial Communication Interface 0 IRQ 0 */
+  void* pfnSERCOM0_1_Handler;             /* 47 Serial Communication Interface 0 IRQ 1 */
+  void* pfnSERCOM0_2_Handler;             /* 48 Serial Communication Interface 0 IRQ 2 */
+  void* pfnSERCOM0_3_Handler;             /* 49 Serial Communication Interface 0 IRQ 3 */
+  void* pfnSERCOM1_0_Handler;             /* 50 Serial Communication Interface 1 IRQ 0 */
+  void* pfnSERCOM1_1_Handler;             /* 51 Serial Communication Interface 1 IRQ 1 */
+  void* pfnSERCOM1_2_Handler;             /* 52 Serial Communication Interface 1 IRQ 2 */
+  void* pfnSERCOM1_3_Handler;             /* 53 Serial Communication Interface 1 IRQ 3 */
+  void* pfnSERCOM2_0_Handler;             /* 54 Serial Communication Interface 2 IRQ 0 */
+  void* pfnSERCOM2_1_Handler;             /* 55 Serial Communication Interface 2 IRQ 1 */
+  void* pfnSERCOM2_2_Handler;             /* 56 Serial Communication Interface 2 IRQ 2 */
+  void* pfnSERCOM2_3_Handler;             /* 57 Serial Communication Interface 2 IRQ 3 */
+  void* pfnSERCOM3_0_Handler;             /* 58 Serial Communication Interface 3 IRQ 0 */
+  void* pfnSERCOM3_1_Handler;             /* 59 Serial Communication Interface 3 IRQ 1 */
+  void* pfnSERCOM3_2_Handler;             /* 60 Serial Communication Interface 3 IRQ 2 */
+  void* pfnSERCOM3_3_Handler;             /* 61 Serial Communication Interface 3 IRQ 3 */
+  void* pfnSERCOM4_0_Handler;             /* 62 Serial Communication Interface 4 IRQ 0 */
+  void* pfnSERCOM4_1_Handler;             /* 63 Serial Communication Interface 4 IRQ 1 */
+  void* pfnSERCOM4_2_Handler;             /* 64 Serial Communication Interface 4 IRQ 2 */
+  void* pfnSERCOM4_3_Handler;             /* 65 Serial Communication Interface 4 IRQ 3 */
+  void* pfnSERCOM5_0_Handler;             /* 66 Serial Communication Interface 5 IRQ 0 */
+  void* pfnSERCOM5_1_Handler;             /* 67 Serial Communication Interface 5 IRQ 1 */
+  void* pfnSERCOM5_2_Handler;             /* 68 Serial Communication Interface 5 IRQ 2 */
+  void* pfnSERCOM5_3_Handler;             /* 69 Serial Communication Interface 5 IRQ 3 */
+  void* pvReserved70;
+  void* pvReserved71;
+  void* pvReserved72;
+  void* pvReserved73;
+  void* pvReserved74;
+  void* pvReserved75;
+  void* pvReserved76;
+  void* pvReserved77;
+  void* pvReserved78;
+  void* pvReserved79;
+  void* pfnUSB_0_Handler;                 /* 80 Universal Serial Bus IRQ 0 */
+  void* pfnUSB_1_Handler;                 /* 81 Universal Serial Bus IRQ 1 */
+  void* pfnUSB_2_Handler;                 /* 82 Universal Serial Bus IRQ 2 */
+  void* pfnUSB_3_Handler;                 /* 83 Universal Serial Bus IRQ 3 */
+  void* pfnGMAC_Handler;                  /* 84 Ethernet MAC */
+  void* pfnTCC0_0_Handler;                /* 85 Timer Counter Control 0 IRQ 0 */
+  void* pfnTCC0_1_Handler;                /* 86 Timer Counter Control 0 IRQ 1 */
+  void* pfnTCC0_2_Handler;                /* 87 Timer Counter Control 0 IRQ 2 */
+  void* pfnTCC0_3_Handler;                /* 88 Timer Counter Control 0 IRQ 3 */
+  void* pfnTCC0_4_Handler;                /* 89 Timer Counter Control 0 IRQ 4 */
+  void* pfnTCC0_5_Handler;                /* 90 Timer Counter Control 0 IRQ 5 */
+  void* pfnTCC0_6_Handler;                /* 91 Timer Counter Control 0 IRQ 6 */
+  void* pfnTCC1_0_Handler;                /* 92 Timer Counter Control 1 IRQ 0 */
+  void* pfnTCC1_1_Handler;                /* 93 Timer Counter Control 1 IRQ 1 */
+  void* pfnTCC1_2_Handler;                /* 94 Timer Counter Control 1 IRQ 2 */
+  void* pfnTCC1_3_Handler;                /* 95 Timer Counter Control 1 IRQ 3 */
+  void* pfnTCC1_4_Handler;                /* 96 Timer Counter Control 1 IRQ 4 */
+  void* pfnTCC2_0_Handler;                /* 97 Timer Counter Control 2 IRQ 0 */
+  void* pfnTCC2_1_Handler;                /* 98 Timer Counter Control 2 IRQ 1 */
+  void* pfnTCC2_2_Handler;                /* 99 Timer Counter Control 2 IRQ 2 */
+  void* pfnTCC2_3_Handler;                /* 100 Timer Counter Control 2 IRQ 3 */
+  void* pfnTCC3_0_Handler;                /* 101 Timer Counter Control 3 IRQ 0 */
+  void* pfnTCC3_1_Handler;                /* 102 Timer Counter Control 3 IRQ 1 */
+  void* pfnTCC3_2_Handler;                /* 103 Timer Counter Control 3 IRQ 2 */
+  void* pfnTCC4_0_Handler;                /* 104 Timer Counter Control 4 IRQ 0 */
+  void* pfnTCC4_1_Handler;                /* 105 Timer Counter Control 4 IRQ 1 */
+  void* pfnTCC4_2_Handler;                /* 106 Timer Counter Control 4 IRQ 2 */
+  void* pfnTC0_Handler;                   /* 107 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 108 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 109 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 110 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 111 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 112 Basic Timer Counter 5 */
+  void* pvReserved113;
+  void* pvReserved114;
+  void* pfnPDEC_0_Handler;                /* 115 Quadrature Decodeur IRQ 0 */
+  void* pfnPDEC_1_Handler;                /* 116 Quadrature Decodeur IRQ 1 */
+  void* pfnPDEC_2_Handler;                /* 117 Quadrature Decodeur IRQ 2 */
+  void* pfnADC0_0_Handler;                /* 118 Analog Digital Converter 0 IRQ 0 */
+  void* pfnADC0_1_Handler;                /* 119 Analog Digital Converter 0 IRQ 1 */
+  void* pfnADC1_0_Handler;                /* 120 Analog Digital Converter 1 IRQ 0 */
+  void* pfnADC1_1_Handler;                /* 121 Analog Digital Converter 1 IRQ 1 */
+  void* pfnAC_Handler;                    /* 122 Analog Comparators */
+  void* pfnDAC_0_Handler;                 /* 123 Digital-to-Analog Converter IRQ 0 */
+  void* pfnDAC_1_Handler;                 /* 124 Digital-to-Analog Converter IRQ 1 */
+  void* pfnDAC_2_Handler;                 /* 125 Digital-to-Analog Converter IRQ 2 */
+  void* pfnDAC_3_Handler;                 /* 126 Digital-to-Analog Converter IRQ 3 */
+  void* pfnDAC_4_Handler;                 /* 127 Digital-to-Analog Converter IRQ 4 */
+  void* pfnI2S_Handler;                   /* 128 Inter-IC Sound Interface */
+  void* pfnPCC_Handler;                   /* 129 Parallel Capture Controller */
+  void* pfnAES_Handler;                   /* 130 Advanced Encryption Standard */
+  void* pfnTRNG_Handler;                  /* 131 True Random Generator */
+  void* pfnICM_Handler;                   /* 132 Integrity Check Monitor */
+  void* pfnPUKCC_Handler;                 /* 133 PUblic-Key Cryptography Controller */
+  void* pfnQSPI_Handler;                  /* 134 Quad SPI interface */
+  void* pfnSDHC0_Handler;                 /* 135 SD/MMC Host Controller 0 */
+  void* pvReserved136;
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler               ( void );
+void NonMaskableInt_Handler      ( void );
+void HardFault_Handler           ( void );
+void MemManagement_Handler       ( void );
+void BusFault_Handler            ( void );
+void UsageFault_Handler          ( void );
+void SVCall_Handler              ( void );
+void DebugMonitor_Handler        ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void MCLK_Handler                ( void );
+void OSCCTRL_0_Handler           ( void );
+void OSCCTRL_1_Handler           ( void );
+void OSCCTRL_2_Handler           ( void );
+void OSCCTRL_3_Handler           ( void );
+void OSCCTRL_4_Handler           ( void );
+void OSC32KCTRL_Handler          ( void );
+void SUPC_0_Handler              ( void );
+void SUPC_1_Handler              ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_0_Handler               ( void );
+void EIC_1_Handler               ( void );
+void EIC_2_Handler               ( void );
+void EIC_3_Handler               ( void );
+void EIC_4_Handler               ( void );
+void EIC_5_Handler               ( void );
+void EIC_6_Handler               ( void );
+void EIC_7_Handler               ( void );
+void EIC_8_Handler               ( void );
+void EIC_9_Handler               ( void );
+void EIC_10_Handler              ( void );
+void EIC_11_Handler              ( void );
+void EIC_12_Handler              ( void );
+void EIC_13_Handler              ( void );
+void EIC_14_Handler              ( void );
+void EIC_15_Handler              ( void );
+void FREQM_Handler               ( void );
+void NVMCTRL_0_Handler           ( void );
+void NVMCTRL_1_Handler           ( void );
+void DMAC_0_Handler              ( void );
+void DMAC_1_Handler              ( void );
+void DMAC_2_Handler              ( void );
+void DMAC_3_Handler              ( void );
+void DMAC_4_Handler              ( void );
+void EVSYS_0_Handler             ( void );
+void EVSYS_1_Handler             ( void );
+void EVSYS_2_Handler             ( void );
+void EVSYS_3_Handler             ( void );
+void EVSYS_4_Handler             ( void );
+void PAC_Handler                 ( void );
+void RAMECC_Handler              ( void );
+void SERCOM0_0_Handler           ( void );
+void SERCOM0_1_Handler           ( void );
+void SERCOM0_2_Handler           ( void );
+void SERCOM0_3_Handler           ( void );
+void SERCOM1_0_Handler           ( void );
+void SERCOM1_1_Handler           ( void );
+void SERCOM1_2_Handler           ( void );
+void SERCOM1_3_Handler           ( void );
+void SERCOM2_0_Handler           ( void );
+void SERCOM2_1_Handler           ( void );
+void SERCOM2_2_Handler           ( void );
+void SERCOM2_3_Handler           ( void );
+void SERCOM3_0_Handler           ( void );
+void SERCOM3_1_Handler           ( void );
+void SERCOM3_2_Handler           ( void );
+void SERCOM3_3_Handler           ( void );
+void SERCOM4_0_Handler           ( void );
+void SERCOM4_1_Handler           ( void );
+void SERCOM4_2_Handler           ( void );
+void SERCOM4_3_Handler           ( void );
+void SERCOM5_0_Handler           ( void );
+void SERCOM5_1_Handler           ( void );
+void SERCOM5_2_Handler           ( void );
+void SERCOM5_3_Handler           ( void );
+void USB_0_Handler               ( void );
+void USB_1_Handler               ( void );
+void USB_2_Handler               ( void );
+void USB_3_Handler               ( void );
+void GMAC_Handler                ( void );
+void TCC0_0_Handler              ( void );
+void TCC0_1_Handler              ( void );
+void TCC0_2_Handler              ( void );
+void TCC0_3_Handler              ( void );
+void TCC0_4_Handler              ( void );
+void TCC0_5_Handler              ( void );
+void TCC0_6_Handler              ( void );
+void TCC1_0_Handler              ( void );
+void TCC1_1_Handler              ( void );
+void TCC1_2_Handler              ( void );
+void TCC1_3_Handler              ( void );
+void TCC1_4_Handler              ( void );
+void TCC2_0_Handler              ( void );
+void TCC2_1_Handler              ( void );
+void TCC2_2_Handler              ( void );
+void TCC2_3_Handler              ( void );
+void TCC3_0_Handler              ( void );
+void TCC3_1_Handler              ( void );
+void TCC3_2_Handler              ( void );
+void TCC4_0_Handler              ( void );
+void TCC4_1_Handler              ( void );
+void TCC4_2_Handler              ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void PDEC_0_Handler              ( void );
+void PDEC_1_Handler              ( void );
+void PDEC_2_Handler              ( void );
+void ADC0_0_Handler              ( void );
+void ADC0_1_Handler              ( void );
+void ADC1_0_Handler              ( void );
+void ADC1_1_Handler              ( void );
+void AC_Handler                  ( void );
+void DAC_0_Handler               ( void );
+void DAC_1_Handler               ( void );
+void DAC_2_Handler               ( void );
+void DAC_3_Handler               ( void );
+void DAC_4_Handler               ( void );
+void I2S_Handler                 ( void );
+void PCC_Handler                 ( void );
+void AES_Handler                 ( void );
+void TRNG_Handler                ( void );
+void ICM_Handler                 ( void );
+void PUKCC_Handler               ( void );
+void QSPI_Handler                ( void );
+void SDHC0_Handler               ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              1         /*!< Core revision r0p1 */
+#define __DEBUG_LVL            3         /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT          1         /*!< FPU present or not */
+#define __MPU_PRESENT          1         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       3         /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL            2         /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same53.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME53J20A */
+/* ************************************************************************** */
+/** \defgroup SAME53J20A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+/** \defgroup SAME53J20A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/pukcc.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/supc.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+/** \defgroup SAME53J20A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC            0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_MCLK           2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC           3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL        4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL     5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC           6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK           7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC           10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM         11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0       12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0           14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB           32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC          35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT          36 /**< \brief Port Module (PORT) */
+#define ID_DMAC          37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX       38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS         39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2       41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2           45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_RAMECC        48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_GMAC          66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2          67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3          68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4           69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC          71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC            72 /**< \brief Analog Comparators (AC) */
+#define ID_AES           73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG          74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM           75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC         76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI          77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL           78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4       96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC4         100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_ADC0         103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1         104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC          105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S          106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC          107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0        128 /**< \brief SD/MMC Host Controller (SDHC0) */
+
+#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+/** \defgroup SAME53J20A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0                          (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1                          (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES                           (0x42002400) /**< \brief (AES) APB Base Address */
+#define CCL                           (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC                          (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC                           (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM                         (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK                          (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC                          (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX                       (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM                           (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S                           (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK                          (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL                       (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL                    (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC                           (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC                           (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC                          (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC                         (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB                     (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI                          (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC                        (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC                          (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC                           (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0                         (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SERCOM0                       (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SUPC                          (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TC0                           (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TCC0                          (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4                          (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG                          (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB                           (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC0              ((Adc      *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1              ((Adc      *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM      2                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC0, ADC1 }             /**< \brief (ADC) Instances List */
+
+#define AES               ((Aes      *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM      1                          /**< \brief (AES) Number of instances */
+#define AES_INSTS         { AES }                    /**< \brief (AES) Instances List */
+
+#define CCL               ((Ccl      *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM      1                          /**< \brief (CCL) Number of instances */
+#define CCL_INSTS         { CCL }                    /**< \brief (CCL) Instances List */
+
+#define CMCC              ((Cmcc     *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM     1                          /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS        { CMCC }                   /**< \brief (CMCC) Instances List */
+
+#define DAC               ((Dac      *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define FREQM             ((Freqm    *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM    1                          /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS       { FREQM }                  /**< \brief (FREQM) Instances List */
+
+#define GCLK              ((Gclk     *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define GMAC              ((Gmac     *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM     1                          /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS        { GMAC }                   /**< \brief (GMAC) Instances List */
+
+#define HMATRIX           ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { HMATRIX }                /**< \brief (HMATRIXB) Instances List */
+
+#define ICM               ((Icm      *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM      1                          /**< \brief (ICM) Number of instances */
+#define ICM_INSTS         { ICM }                    /**< \brief (ICM) Instances List */
+
+#define I2S               ((I2s      *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MCLK              ((Mclk     *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM     1                          /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS        { MCLK }                   /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL           ((Oscctrl  *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM  1                          /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS     { OSCCTRL }                /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL        ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1                          /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS  { OSC32KCTRL }             /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC               ((Pac      *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM      1                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC }                    /**< \brief (PAC) Instances List */
+
+#define PCC               ((Pcc      *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM      1                          /**< \brief (PCC) Number of instances */
+#define PCC_INSTS         { PCC }                    /**< \brief (PCC) Instances List */
+
+#define PDEC              ((Pdec     *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM     1                          /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS        { PDEC }                   /**< \brief (PDEC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PUKCC             ((void     *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB         ((void     *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM    1                          /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS       { PUKCC }                  /**< \brief (PUKCC) Instances List */
+
+#define QSPI              ((Qspi     *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM     1                          /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS        { QSPI }                   /**< \brief (QSPI) Instances List */
+
+#define RAMECC            ((Ramecc   *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM   1                          /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS      { RAMECC }                 /**< \brief (RAMECC) Instances List */
+
+#define RSTC              ((Rstc     *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM     1                          /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS        { RSTC }                   /**< \brief (RSTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SDHC0             ((Sdhc     *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC_INST_NUM     1                          /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS        { SDHC0 }                  /**< \brief (SDHC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC              ((Supc     *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM     1                          /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS        { SUPC }                   /**< \brief (SUPC) Instances List */
+
+#define TC0               ((Tc       *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4              ((Tcc      *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM      5                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG              ((Trng     *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM     1                          /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS        { TRNG }                   /**< \brief (TRNG) Instances List */
+
+#define USB               ((Usb      *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+/** \defgroup SAME53J20A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same53j20a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE            _UL_(0x00040000) /* 256 kB */
+#define FLASH_SIZE            _UL_(0x00100000) /* 1024 kB */
+#define FLASH_PAGE_SIZE       512
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  512
+#define BKUPRAM_SIZE          _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE             _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR     _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE     _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR      _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE      _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR    _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE    _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR            _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR        _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE        _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR       _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE       _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR             _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR          _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR          _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x61830304)
+#define ADC0_TOUCH_LINES_NUM  32
+#define PORT_GROUPS           2
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAME53J20A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME53J20A_H */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53n19a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53n19a.h
new file mode 100644
index 000000000..f6b530afb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53n19a.h	
@@ -0,0 +1,1069 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME53N19A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53N19A_
+#define _SAME53N19A_
+
+/**
+ * \ingroup SAME53_definitions
+ * \addtogroup SAME53N19A_definitions SAME53N19A definitions
+ * This file defines all structures and symbols for SAME53N19A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+/** \defgroup SAME53N19A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M4 Processor Exceptions Numbers *******************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt      */
+  HardFault_IRQn           = -13,/**<  3 Hard Fault Interrupt        */
+  MemoryManagement_IRQn    = -12,/**<  4 Memory Management Interrupt */
+  BusFault_IRQn            = -11,/**<  5 Bus Fault Interrupt         */
+  UsageFault_IRQn          = -10,/**<  6 Usage Fault Interrupt       */
+  SVCall_IRQn              = -5, /**< 11 SV Call Interrupt           */
+  DebugMonitor_IRQn        = -4, /**< 12 Debug Monitor Interrupt     */
+  PendSV_IRQn              = -2, /**< 14 Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 System Tick Interrupt       */
+  /******  SAME53N19A-specific Interrupt Numbers *********************/
+  PM_IRQn                  =  0, /**<  0 SAME53N19A Power Manager (PM) */
+  MCLK_IRQn                =  1, /**<  1 SAME53N19A Main Clock (MCLK) */
+  OSCCTRL_0_IRQn           =  2, /**<  2 SAME53N19A Oscillators Control (OSCCTRL) IRQ 0 */
+  OSCCTRL_1_IRQn           =  3, /**<  3 SAME53N19A Oscillators Control (OSCCTRL) IRQ 1 */
+  OSCCTRL_2_IRQn           =  4, /**<  4 SAME53N19A Oscillators Control (OSCCTRL) IRQ 2 */
+  OSCCTRL_3_IRQn           =  5, /**<  5 SAME53N19A Oscillators Control (OSCCTRL) IRQ 3 */
+  OSCCTRL_4_IRQn           =  6, /**<  6 SAME53N19A Oscillators Control (OSCCTRL) IRQ 4 */
+  OSC32KCTRL_IRQn          =  7, /**<  7 SAME53N19A 32kHz Oscillators Control (OSC32KCTRL) */
+  SUPC_0_IRQn              =  8, /**<  8 SAME53N19A Supply Controller (SUPC) IRQ 0 */
+  SUPC_1_IRQn              =  9, /**<  9 SAME53N19A Supply Controller (SUPC) IRQ 1 */
+  WDT_IRQn                 = 10, /**< 10 SAME53N19A Watchdog Timer (WDT) */
+  RTC_IRQn                 = 11, /**< 11 SAME53N19A Real-Time Counter (RTC) */
+  EIC_0_IRQn               = 12, /**< 12 SAME53N19A External Interrupt Controller (EIC) IRQ 0 */
+  EIC_1_IRQn               = 13, /**< 13 SAME53N19A External Interrupt Controller (EIC) IRQ 1 */
+  EIC_2_IRQn               = 14, /**< 14 SAME53N19A External Interrupt Controller (EIC) IRQ 2 */
+  EIC_3_IRQn               = 15, /**< 15 SAME53N19A External Interrupt Controller (EIC) IRQ 3 */
+  EIC_4_IRQn               = 16, /**< 16 SAME53N19A External Interrupt Controller (EIC) IRQ 4 */
+  EIC_5_IRQn               = 17, /**< 17 SAME53N19A External Interrupt Controller (EIC) IRQ 5 */
+  EIC_6_IRQn               = 18, /**< 18 SAME53N19A External Interrupt Controller (EIC) IRQ 6 */
+  EIC_7_IRQn               = 19, /**< 19 SAME53N19A External Interrupt Controller (EIC) IRQ 7 */
+  EIC_8_IRQn               = 20, /**< 20 SAME53N19A External Interrupt Controller (EIC) IRQ 8 */
+  EIC_9_IRQn               = 21, /**< 21 SAME53N19A External Interrupt Controller (EIC) IRQ 9 */
+  EIC_10_IRQn              = 22, /**< 22 SAME53N19A External Interrupt Controller (EIC) IRQ 10 */
+  EIC_11_IRQn              = 23, /**< 23 SAME53N19A External Interrupt Controller (EIC) IRQ 11 */
+  EIC_12_IRQn              = 24, /**< 24 SAME53N19A External Interrupt Controller (EIC) IRQ 12 */
+  EIC_13_IRQn              = 25, /**< 25 SAME53N19A External Interrupt Controller (EIC) IRQ 13 */
+  EIC_14_IRQn              = 26, /**< 26 SAME53N19A External Interrupt Controller (EIC) IRQ 14 */
+  EIC_15_IRQn              = 27, /**< 27 SAME53N19A External Interrupt Controller (EIC) IRQ 15 */
+  FREQM_IRQn               = 28, /**< 28 SAME53N19A Frequency Meter (FREQM) */
+  NVMCTRL_0_IRQn           = 29, /**< 29 SAME53N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+  NVMCTRL_1_IRQn           = 30, /**< 30 SAME53N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+  DMAC_0_IRQn              = 31, /**< 31 SAME53N19A Direct Memory Access Controller (DMAC) IRQ 0 */
+  DMAC_1_IRQn              = 32, /**< 32 SAME53N19A Direct Memory Access Controller (DMAC) IRQ 1 */
+  DMAC_2_IRQn              = 33, /**< 33 SAME53N19A Direct Memory Access Controller (DMAC) IRQ 2 */
+  DMAC_3_IRQn              = 34, /**< 34 SAME53N19A Direct Memory Access Controller (DMAC) IRQ 3 */
+  DMAC_4_IRQn              = 35, /**< 35 SAME53N19A Direct Memory Access Controller (DMAC) IRQ 4 */
+  EVSYS_0_IRQn             = 36, /**< 36 SAME53N19A Event System Interface (EVSYS) IRQ 0 */
+  EVSYS_1_IRQn             = 37, /**< 37 SAME53N19A Event System Interface (EVSYS) IRQ 1 */
+  EVSYS_2_IRQn             = 38, /**< 38 SAME53N19A Event System Interface (EVSYS) IRQ 2 */
+  EVSYS_3_IRQn             = 39, /**< 39 SAME53N19A Event System Interface (EVSYS) IRQ 3 */
+  EVSYS_4_IRQn             = 40, /**< 40 SAME53N19A Event System Interface (EVSYS) IRQ 4 */
+  PAC_IRQn                 = 41, /**< 41 SAME53N19A Peripheral Access Controller (PAC) */
+  RAMECC_IRQn              = 45, /**< 45 SAME53N19A RAM ECC (RAMECC) */
+  SERCOM0_0_IRQn           = 46, /**< 46 SAME53N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+  SERCOM0_1_IRQn           = 47, /**< 47 SAME53N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+  SERCOM0_2_IRQn           = 48, /**< 48 SAME53N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+  SERCOM0_3_IRQn           = 49, /**< 49 SAME53N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+  SERCOM1_0_IRQn           = 50, /**< 50 SAME53N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+  SERCOM1_1_IRQn           = 51, /**< 51 SAME53N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+  SERCOM1_2_IRQn           = 52, /**< 52 SAME53N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+  SERCOM1_3_IRQn           = 53, /**< 53 SAME53N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+  SERCOM2_0_IRQn           = 54, /**< 54 SAME53N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+  SERCOM2_1_IRQn           = 55, /**< 55 SAME53N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+  SERCOM2_2_IRQn           = 56, /**< 56 SAME53N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+  SERCOM2_3_IRQn           = 57, /**< 57 SAME53N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+  SERCOM3_0_IRQn           = 58, /**< 58 SAME53N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+  SERCOM3_1_IRQn           = 59, /**< 59 SAME53N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+  SERCOM3_2_IRQn           = 60, /**< 60 SAME53N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+  SERCOM3_3_IRQn           = 61, /**< 61 SAME53N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+  SERCOM4_0_IRQn           = 62, /**< 62 SAME53N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+  SERCOM4_1_IRQn           = 63, /**< 63 SAME53N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+  SERCOM4_2_IRQn           = 64, /**< 64 SAME53N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+  SERCOM4_3_IRQn           = 65, /**< 65 SAME53N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+  SERCOM5_0_IRQn           = 66, /**< 66 SAME53N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+  SERCOM5_1_IRQn           = 67, /**< 67 SAME53N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+  SERCOM5_2_IRQn           = 68, /**< 68 SAME53N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+  SERCOM5_3_IRQn           = 69, /**< 69 SAME53N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+  SERCOM6_0_IRQn           = 70, /**< 70 SAME53N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
+  SERCOM6_1_IRQn           = 71, /**< 71 SAME53N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
+  SERCOM6_2_IRQn           = 72, /**< 72 SAME53N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
+  SERCOM6_3_IRQn           = 73, /**< 73 SAME53N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
+  SERCOM7_0_IRQn           = 74, /**< 74 SAME53N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
+  SERCOM7_1_IRQn           = 75, /**< 75 SAME53N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
+  SERCOM7_2_IRQn           = 76, /**< 76 SAME53N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
+  SERCOM7_3_IRQn           = 77, /**< 77 SAME53N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
+  USB_0_IRQn               = 80, /**< 80 SAME53N19A Universal Serial Bus (USB) IRQ 0 */
+  USB_1_IRQn               = 81, /**< 81 SAME53N19A Universal Serial Bus (USB) IRQ 1 */
+  USB_2_IRQn               = 82, /**< 82 SAME53N19A Universal Serial Bus (USB) IRQ 2 */
+  USB_3_IRQn               = 83, /**< 83 SAME53N19A Universal Serial Bus (USB) IRQ 3 */
+  GMAC_IRQn                = 84, /**< 84 SAME53N19A Ethernet MAC (GMAC) */
+  TCC0_0_IRQn              = 85, /**< 85 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 0 */
+  TCC0_1_IRQn              = 86, /**< 86 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 1 */
+  TCC0_2_IRQn              = 87, /**< 87 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 2 */
+  TCC0_3_IRQn              = 88, /**< 88 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 3 */
+  TCC0_4_IRQn              = 89, /**< 89 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 4 */
+  TCC0_5_IRQn              = 90, /**< 90 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 5 */
+  TCC0_6_IRQn              = 91, /**< 91 SAME53N19A Timer Counter Control 0 (TCC0) IRQ 6 */
+  TCC1_0_IRQn              = 92, /**< 92 SAME53N19A Timer Counter Control 1 (TCC1) IRQ 0 */
+  TCC1_1_IRQn              = 93, /**< 93 SAME53N19A Timer Counter Control 1 (TCC1) IRQ 1 */
+  TCC1_2_IRQn              = 94, /**< 94 SAME53N19A Timer Counter Control 1 (TCC1) IRQ 2 */
+  TCC1_3_IRQn              = 95, /**< 95 SAME53N19A Timer Counter Control 1 (TCC1) IRQ 3 */
+  TCC1_4_IRQn              = 96, /**< 96 SAME53N19A Timer Counter Control 1 (TCC1) IRQ 4 */
+  TCC2_0_IRQn              = 97, /**< 97 SAME53N19A Timer Counter Control 2 (TCC2) IRQ 0 */
+  TCC2_1_IRQn              = 98, /**< 98 SAME53N19A Timer Counter Control 2 (TCC2) IRQ 1 */
+  TCC2_2_IRQn              = 99, /**< 99 SAME53N19A Timer Counter Control 2 (TCC2) IRQ 2 */
+  TCC2_3_IRQn              = 100, /**< 100 SAME53N19A Timer Counter Control 2 (TCC2) IRQ 3 */
+  TCC3_0_IRQn              = 101, /**< 101 SAME53N19A Timer Counter Control 3 (TCC3) IRQ 0 */
+  TCC3_1_IRQn              = 102, /**< 102 SAME53N19A Timer Counter Control 3 (TCC3) IRQ 1 */
+  TCC3_2_IRQn              = 103, /**< 103 SAME53N19A Timer Counter Control 3 (TCC3) IRQ 2 */
+  TCC4_0_IRQn              = 104, /**< 104 SAME53N19A Timer Counter Control 4 (TCC4) IRQ 0 */
+  TCC4_1_IRQn              = 105, /**< 105 SAME53N19A Timer Counter Control 4 (TCC4) IRQ 1 */
+  TCC4_2_IRQn              = 106, /**< 106 SAME53N19A Timer Counter Control 4 (TCC4) IRQ 2 */
+  TC0_IRQn                 = 107, /**< 107 SAME53N19A Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 108, /**< 108 SAME53N19A Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 109, /**< 109 SAME53N19A Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 110, /**< 110 SAME53N19A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 111, /**< 111 SAME53N19A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 112, /**< 112 SAME53N19A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 113, /**< 113 SAME53N19A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 114, /**< 114 SAME53N19A Basic Timer Counter 7 (TC7) */
+  PDEC_0_IRQn              = 115, /**< 115 SAME53N19A Quadrature Decodeur (PDEC) IRQ 0 */
+  PDEC_1_IRQn              = 116, /**< 116 SAME53N19A Quadrature Decodeur (PDEC) IRQ 1 */
+  PDEC_2_IRQn              = 117, /**< 117 SAME53N19A Quadrature Decodeur (PDEC) IRQ 2 */
+  ADC0_0_IRQn              = 118, /**< 118 SAME53N19A Analog Digital Converter 0 (ADC0) IRQ 0 */
+  ADC0_1_IRQn              = 119, /**< 119 SAME53N19A Analog Digital Converter 0 (ADC0) IRQ 1 */
+  ADC1_0_IRQn              = 120, /**< 120 SAME53N19A Analog Digital Converter 1 (ADC1) IRQ 0 */
+  ADC1_1_IRQn              = 121, /**< 121 SAME53N19A Analog Digital Converter 1 (ADC1) IRQ 1 */
+  AC_IRQn                  = 122, /**< 122 SAME53N19A Analog Comparators (AC) */
+  DAC_0_IRQn               = 123, /**< 123 SAME53N19A Digital-to-Analog Converter (DAC) IRQ 0 */
+  DAC_1_IRQn               = 124, /**< 124 SAME53N19A Digital-to-Analog Converter (DAC) IRQ 1 */
+  DAC_2_IRQn               = 125, /**< 125 SAME53N19A Digital-to-Analog Converter (DAC) IRQ 2 */
+  DAC_3_IRQn               = 126, /**< 126 SAME53N19A Digital-to-Analog Converter (DAC) IRQ 3 */
+  DAC_4_IRQn               = 127, /**< 127 SAME53N19A Digital-to-Analog Converter (DAC) IRQ 4 */
+  I2S_IRQn                 = 128, /**< 128 SAME53N19A Inter-IC Sound Interface (I2S) */
+  PCC_IRQn                 = 129, /**< 129 SAME53N19A Parallel Capture Controller (PCC) */
+  AES_IRQn                 = 130, /**< 130 SAME53N19A Advanced Encryption Standard (AES) */
+  TRNG_IRQn                = 131, /**< 131 SAME53N19A True Random Generator (TRNG) */
+  ICM_IRQn                 = 132, /**< 132 SAME53N19A Integrity Check Monitor (ICM) */
+  PUKCC_IRQn               = 133, /**< 133 SAME53N19A PUblic-Key Cryptography Controller (PUKCC) */
+  QSPI_IRQn                = 134, /**< 134 SAME53N19A Quad SPI interface (QSPI) */
+  SDHC0_IRQn               = 135, /**< 135 SAME53N19A SD/MMC Host Controller 0 (SDHC0) */
+  SDHC1_IRQn               = 136, /**< 136 SAME53N19A SD/MMC Host Controller 1 (SDHC1) */
+
+  PERIPH_COUNT_IRQn        = 137  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNonMaskableInt_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManagement_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVCall_Handler;
+  void* pfnDebugMonitor_Handler;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnMCLK_Handler;                  /*  1 Main Clock */
+  void* pfnOSCCTRL_0_Handler;             /*  2 Oscillators Control IRQ 0 */
+  void* pfnOSCCTRL_1_Handler;             /*  3 Oscillators Control IRQ 1 */
+  void* pfnOSCCTRL_2_Handler;             /*  4 Oscillators Control IRQ 2 */
+  void* pfnOSCCTRL_3_Handler;             /*  5 Oscillators Control IRQ 3 */
+  void* pfnOSCCTRL_4_Handler;             /*  6 Oscillators Control IRQ 4 */
+  void* pfnOSC32KCTRL_Handler;            /*  7 32kHz Oscillators Control */
+  void* pfnSUPC_0_Handler;                /*  8 Supply Controller IRQ 0 */
+  void* pfnSUPC_1_Handler;                /*  9 Supply Controller IRQ 1 */
+  void* pfnWDT_Handler;                   /* 10 Watchdog Timer */
+  void* pfnRTC_Handler;                   /* 11 Real-Time Counter */
+  void* pfnEIC_0_Handler;                 /* 12 External Interrupt Controller IRQ 0 */
+  void* pfnEIC_1_Handler;                 /* 13 External Interrupt Controller IRQ 1 */
+  void* pfnEIC_2_Handler;                 /* 14 External Interrupt Controller IRQ 2 */
+  void* pfnEIC_3_Handler;                 /* 15 External Interrupt Controller IRQ 3 */
+  void* pfnEIC_4_Handler;                 /* 16 External Interrupt Controller IRQ 4 */
+  void* pfnEIC_5_Handler;                 /* 17 External Interrupt Controller IRQ 5 */
+  void* pfnEIC_6_Handler;                 /* 18 External Interrupt Controller IRQ 6 */
+  void* pfnEIC_7_Handler;                 /* 19 External Interrupt Controller IRQ 7 */
+  void* pfnEIC_8_Handler;                 /* 20 External Interrupt Controller IRQ 8 */
+  void* pfnEIC_9_Handler;                 /* 21 External Interrupt Controller IRQ 9 */
+  void* pfnEIC_10_Handler;                /* 22 External Interrupt Controller IRQ 10 */
+  void* pfnEIC_11_Handler;                /* 23 External Interrupt Controller IRQ 11 */
+  void* pfnEIC_12_Handler;                /* 24 External Interrupt Controller IRQ 12 */
+  void* pfnEIC_13_Handler;                /* 25 External Interrupt Controller IRQ 13 */
+  void* pfnEIC_14_Handler;                /* 26 External Interrupt Controller IRQ 14 */
+  void* pfnEIC_15_Handler;                /* 27 External Interrupt Controller IRQ 15 */
+  void* pfnFREQM_Handler;                 /* 28 Frequency Meter */
+  void* pfnNVMCTRL_0_Handler;             /* 29 Non-Volatile Memory Controller IRQ 0 */
+  void* pfnNVMCTRL_1_Handler;             /* 30 Non-Volatile Memory Controller IRQ 1 */
+  void* pfnDMAC_0_Handler;                /* 31 Direct Memory Access Controller IRQ 0 */
+  void* pfnDMAC_1_Handler;                /* 32 Direct Memory Access Controller IRQ 1 */
+  void* pfnDMAC_2_Handler;                /* 33 Direct Memory Access Controller IRQ 2 */
+  void* pfnDMAC_3_Handler;                /* 34 Direct Memory Access Controller IRQ 3 */
+  void* pfnDMAC_4_Handler;                /* 35 Direct Memory Access Controller IRQ 4 */
+  void* pfnEVSYS_0_Handler;               /* 36 Event System Interface IRQ 0 */
+  void* pfnEVSYS_1_Handler;               /* 37 Event System Interface IRQ 1 */
+  void* pfnEVSYS_2_Handler;               /* 38 Event System Interface IRQ 2 */
+  void* pfnEVSYS_3_Handler;               /* 39 Event System Interface IRQ 3 */
+  void* pfnEVSYS_4_Handler;               /* 40 Event System Interface IRQ 4 */
+  void* pfnPAC_Handler;                   /* 41 Peripheral Access Controller */
+  void* pvReserved42;
+  void* pvReserved43;
+  void* pvReserved44;
+  void* pfnRAMECC_Handler;                /* 45 RAM ECC */
+  void* pfnSERCOM0_0_Handler;             /* 46 Serial Communication Interface 0 IRQ 0 */
+  void* pfnSERCOM0_1_Handler;             /* 47 Serial Communication Interface 0 IRQ 1 */
+  void* pfnSERCOM0_2_Handler;             /* 48 Serial Communication Interface 0 IRQ 2 */
+  void* pfnSERCOM0_3_Handler;             /* 49 Serial Communication Interface 0 IRQ 3 */
+  void* pfnSERCOM1_0_Handler;             /* 50 Serial Communication Interface 1 IRQ 0 */
+  void* pfnSERCOM1_1_Handler;             /* 51 Serial Communication Interface 1 IRQ 1 */
+  void* pfnSERCOM1_2_Handler;             /* 52 Serial Communication Interface 1 IRQ 2 */
+  void* pfnSERCOM1_3_Handler;             /* 53 Serial Communication Interface 1 IRQ 3 */
+  void* pfnSERCOM2_0_Handler;             /* 54 Serial Communication Interface 2 IRQ 0 */
+  void* pfnSERCOM2_1_Handler;             /* 55 Serial Communication Interface 2 IRQ 1 */
+  void* pfnSERCOM2_2_Handler;             /* 56 Serial Communication Interface 2 IRQ 2 */
+  void* pfnSERCOM2_3_Handler;             /* 57 Serial Communication Interface 2 IRQ 3 */
+  void* pfnSERCOM3_0_Handler;             /* 58 Serial Communication Interface 3 IRQ 0 */
+  void* pfnSERCOM3_1_Handler;             /* 59 Serial Communication Interface 3 IRQ 1 */
+  void* pfnSERCOM3_2_Handler;             /* 60 Serial Communication Interface 3 IRQ 2 */
+  void* pfnSERCOM3_3_Handler;             /* 61 Serial Communication Interface 3 IRQ 3 */
+  void* pfnSERCOM4_0_Handler;             /* 62 Serial Communication Interface 4 IRQ 0 */
+  void* pfnSERCOM4_1_Handler;             /* 63 Serial Communication Interface 4 IRQ 1 */
+  void* pfnSERCOM4_2_Handler;             /* 64 Serial Communication Interface 4 IRQ 2 */
+  void* pfnSERCOM4_3_Handler;             /* 65 Serial Communication Interface 4 IRQ 3 */
+  void* pfnSERCOM5_0_Handler;             /* 66 Serial Communication Interface 5 IRQ 0 */
+  void* pfnSERCOM5_1_Handler;             /* 67 Serial Communication Interface 5 IRQ 1 */
+  void* pfnSERCOM5_2_Handler;             /* 68 Serial Communication Interface 5 IRQ 2 */
+  void* pfnSERCOM5_3_Handler;             /* 69 Serial Communication Interface 5 IRQ 3 */
+  void* pfnSERCOM6_0_Handler;             /* 70 Serial Communication Interface 6 IRQ 0 */
+  void* pfnSERCOM6_1_Handler;             /* 71 Serial Communication Interface 6 IRQ 1 */
+  void* pfnSERCOM6_2_Handler;             /* 72 Serial Communication Interface 6 IRQ 2 */
+  void* pfnSERCOM6_3_Handler;             /* 73 Serial Communication Interface 6 IRQ 3 */
+  void* pfnSERCOM7_0_Handler;             /* 74 Serial Communication Interface 7 IRQ 0 */
+  void* pfnSERCOM7_1_Handler;             /* 75 Serial Communication Interface 7 IRQ 1 */
+  void* pfnSERCOM7_2_Handler;             /* 76 Serial Communication Interface 7 IRQ 2 */
+  void* pfnSERCOM7_3_Handler;             /* 77 Serial Communication Interface 7 IRQ 3 */
+  void* pvReserved78;
+  void* pvReserved79;
+  void* pfnUSB_0_Handler;                 /* 80 Universal Serial Bus IRQ 0 */
+  void* pfnUSB_1_Handler;                 /* 81 Universal Serial Bus IRQ 1 */
+  void* pfnUSB_2_Handler;                 /* 82 Universal Serial Bus IRQ 2 */
+  void* pfnUSB_3_Handler;                 /* 83 Universal Serial Bus IRQ 3 */
+  void* pfnGMAC_Handler;                  /* 84 Ethernet MAC */
+  void* pfnTCC0_0_Handler;                /* 85 Timer Counter Control 0 IRQ 0 */
+  void* pfnTCC0_1_Handler;                /* 86 Timer Counter Control 0 IRQ 1 */
+  void* pfnTCC0_2_Handler;                /* 87 Timer Counter Control 0 IRQ 2 */
+  void* pfnTCC0_3_Handler;                /* 88 Timer Counter Control 0 IRQ 3 */
+  void* pfnTCC0_4_Handler;                /* 89 Timer Counter Control 0 IRQ 4 */
+  void* pfnTCC0_5_Handler;                /* 90 Timer Counter Control 0 IRQ 5 */
+  void* pfnTCC0_6_Handler;                /* 91 Timer Counter Control 0 IRQ 6 */
+  void* pfnTCC1_0_Handler;                /* 92 Timer Counter Control 1 IRQ 0 */
+  void* pfnTCC1_1_Handler;                /* 93 Timer Counter Control 1 IRQ 1 */
+  void* pfnTCC1_2_Handler;                /* 94 Timer Counter Control 1 IRQ 2 */
+  void* pfnTCC1_3_Handler;                /* 95 Timer Counter Control 1 IRQ 3 */
+  void* pfnTCC1_4_Handler;                /* 96 Timer Counter Control 1 IRQ 4 */
+  void* pfnTCC2_0_Handler;                /* 97 Timer Counter Control 2 IRQ 0 */
+  void* pfnTCC2_1_Handler;                /* 98 Timer Counter Control 2 IRQ 1 */
+  void* pfnTCC2_2_Handler;                /* 99 Timer Counter Control 2 IRQ 2 */
+  void* pfnTCC2_3_Handler;                /* 100 Timer Counter Control 2 IRQ 3 */
+  void* pfnTCC3_0_Handler;                /* 101 Timer Counter Control 3 IRQ 0 */
+  void* pfnTCC3_1_Handler;                /* 102 Timer Counter Control 3 IRQ 1 */
+  void* pfnTCC3_2_Handler;                /* 103 Timer Counter Control 3 IRQ 2 */
+  void* pfnTCC4_0_Handler;                /* 104 Timer Counter Control 4 IRQ 0 */
+  void* pfnTCC4_1_Handler;                /* 105 Timer Counter Control 4 IRQ 1 */
+  void* pfnTCC4_2_Handler;                /* 106 Timer Counter Control 4 IRQ 2 */
+  void* pfnTC0_Handler;                   /* 107 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 108 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 109 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 110 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 111 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 112 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 113 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 114 Basic Timer Counter 7 */
+  void* pfnPDEC_0_Handler;                /* 115 Quadrature Decodeur IRQ 0 */
+  void* pfnPDEC_1_Handler;                /* 116 Quadrature Decodeur IRQ 1 */
+  void* pfnPDEC_2_Handler;                /* 117 Quadrature Decodeur IRQ 2 */
+  void* pfnADC0_0_Handler;                /* 118 Analog Digital Converter 0 IRQ 0 */
+  void* pfnADC0_1_Handler;                /* 119 Analog Digital Converter 0 IRQ 1 */
+  void* pfnADC1_0_Handler;                /* 120 Analog Digital Converter 1 IRQ 0 */
+  void* pfnADC1_1_Handler;                /* 121 Analog Digital Converter 1 IRQ 1 */
+  void* pfnAC_Handler;                    /* 122 Analog Comparators */
+  void* pfnDAC_0_Handler;                 /* 123 Digital-to-Analog Converter IRQ 0 */
+  void* pfnDAC_1_Handler;                 /* 124 Digital-to-Analog Converter IRQ 1 */
+  void* pfnDAC_2_Handler;                 /* 125 Digital-to-Analog Converter IRQ 2 */
+  void* pfnDAC_3_Handler;                 /* 126 Digital-to-Analog Converter IRQ 3 */
+  void* pfnDAC_4_Handler;                 /* 127 Digital-to-Analog Converter IRQ 4 */
+  void* pfnI2S_Handler;                   /* 128 Inter-IC Sound Interface */
+  void* pfnPCC_Handler;                   /* 129 Parallel Capture Controller */
+  void* pfnAES_Handler;                   /* 130 Advanced Encryption Standard */
+  void* pfnTRNG_Handler;                  /* 131 True Random Generator */
+  void* pfnICM_Handler;                   /* 132 Integrity Check Monitor */
+  void* pfnPUKCC_Handler;                 /* 133 PUblic-Key Cryptography Controller */
+  void* pfnQSPI_Handler;                  /* 134 Quad SPI interface */
+  void* pfnSDHC0_Handler;                 /* 135 SD/MMC Host Controller 0 */
+  void* pfnSDHC1_Handler;                 /* 136 SD/MMC Host Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler               ( void );
+void NonMaskableInt_Handler      ( void );
+void HardFault_Handler           ( void );
+void MemManagement_Handler       ( void );
+void BusFault_Handler            ( void );
+void UsageFault_Handler          ( void );
+void SVCall_Handler              ( void );
+void DebugMonitor_Handler        ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void MCLK_Handler                ( void );
+void OSCCTRL_0_Handler           ( void );
+void OSCCTRL_1_Handler           ( void );
+void OSCCTRL_2_Handler           ( void );
+void OSCCTRL_3_Handler           ( void );
+void OSCCTRL_4_Handler           ( void );
+void OSC32KCTRL_Handler          ( void );
+void SUPC_0_Handler              ( void );
+void SUPC_1_Handler              ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_0_Handler               ( void );
+void EIC_1_Handler               ( void );
+void EIC_2_Handler               ( void );
+void EIC_3_Handler               ( void );
+void EIC_4_Handler               ( void );
+void EIC_5_Handler               ( void );
+void EIC_6_Handler               ( void );
+void EIC_7_Handler               ( void );
+void EIC_8_Handler               ( void );
+void EIC_9_Handler               ( void );
+void EIC_10_Handler              ( void );
+void EIC_11_Handler              ( void );
+void EIC_12_Handler              ( void );
+void EIC_13_Handler              ( void );
+void EIC_14_Handler              ( void );
+void EIC_15_Handler              ( void );
+void FREQM_Handler               ( void );
+void NVMCTRL_0_Handler           ( void );
+void NVMCTRL_1_Handler           ( void );
+void DMAC_0_Handler              ( void );
+void DMAC_1_Handler              ( void );
+void DMAC_2_Handler              ( void );
+void DMAC_3_Handler              ( void );
+void DMAC_4_Handler              ( void );
+void EVSYS_0_Handler             ( void );
+void EVSYS_1_Handler             ( void );
+void EVSYS_2_Handler             ( void );
+void EVSYS_3_Handler             ( void );
+void EVSYS_4_Handler             ( void );
+void PAC_Handler                 ( void );
+void RAMECC_Handler              ( void );
+void SERCOM0_0_Handler           ( void );
+void SERCOM0_1_Handler           ( void );
+void SERCOM0_2_Handler           ( void );
+void SERCOM0_3_Handler           ( void );
+void SERCOM1_0_Handler           ( void );
+void SERCOM1_1_Handler           ( void );
+void SERCOM1_2_Handler           ( void );
+void SERCOM1_3_Handler           ( void );
+void SERCOM2_0_Handler           ( void );
+void SERCOM2_1_Handler           ( void );
+void SERCOM2_2_Handler           ( void );
+void SERCOM2_3_Handler           ( void );
+void SERCOM3_0_Handler           ( void );
+void SERCOM3_1_Handler           ( void );
+void SERCOM3_2_Handler           ( void );
+void SERCOM3_3_Handler           ( void );
+void SERCOM4_0_Handler           ( void );
+void SERCOM4_1_Handler           ( void );
+void SERCOM4_2_Handler           ( void );
+void SERCOM4_3_Handler           ( void );
+void SERCOM5_0_Handler           ( void );
+void SERCOM5_1_Handler           ( void );
+void SERCOM5_2_Handler           ( void );
+void SERCOM5_3_Handler           ( void );
+void SERCOM6_0_Handler           ( void );
+void SERCOM6_1_Handler           ( void );
+void SERCOM6_2_Handler           ( void );
+void SERCOM6_3_Handler           ( void );
+void SERCOM7_0_Handler           ( void );
+void SERCOM7_1_Handler           ( void );
+void SERCOM7_2_Handler           ( void );
+void SERCOM7_3_Handler           ( void );
+void USB_0_Handler               ( void );
+void USB_1_Handler               ( void );
+void USB_2_Handler               ( void );
+void USB_3_Handler               ( void );
+void GMAC_Handler                ( void );
+void TCC0_0_Handler              ( void );
+void TCC0_1_Handler              ( void );
+void TCC0_2_Handler              ( void );
+void TCC0_3_Handler              ( void );
+void TCC0_4_Handler              ( void );
+void TCC0_5_Handler              ( void );
+void TCC0_6_Handler              ( void );
+void TCC1_0_Handler              ( void );
+void TCC1_1_Handler              ( void );
+void TCC1_2_Handler              ( void );
+void TCC1_3_Handler              ( void );
+void TCC1_4_Handler              ( void );
+void TCC2_0_Handler              ( void );
+void TCC2_1_Handler              ( void );
+void TCC2_2_Handler              ( void );
+void TCC2_3_Handler              ( void );
+void TCC3_0_Handler              ( void );
+void TCC3_1_Handler              ( void );
+void TCC3_2_Handler              ( void );
+void TCC4_0_Handler              ( void );
+void TCC4_1_Handler              ( void );
+void TCC4_2_Handler              ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void PDEC_0_Handler              ( void );
+void PDEC_1_Handler              ( void );
+void PDEC_2_Handler              ( void );
+void ADC0_0_Handler              ( void );
+void ADC0_1_Handler              ( void );
+void ADC1_0_Handler              ( void );
+void ADC1_1_Handler              ( void );
+void AC_Handler                  ( void );
+void DAC_0_Handler               ( void );
+void DAC_1_Handler               ( void );
+void DAC_2_Handler               ( void );
+void DAC_3_Handler               ( void );
+void DAC_4_Handler               ( void );
+void I2S_Handler                 ( void );
+void PCC_Handler                 ( void );
+void AES_Handler                 ( void );
+void TRNG_Handler                ( void );
+void ICM_Handler                 ( void );
+void PUKCC_Handler               ( void );
+void QSPI_Handler                ( void );
+void SDHC0_Handler               ( void );
+void SDHC1_Handler               ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              1         /*!< Core revision r0p1 */
+#define __DEBUG_LVL            3         /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT          1         /*!< FPU present or not */
+#define __MPU_PRESENT          1         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       3         /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL            2         /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same53.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME53N19A */
+/* ************************************************************************** */
+/** \defgroup SAME53N19A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+/** \defgroup SAME53N19A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/pukcc.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sdhc1.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sercom6.h"
+#include "instance/sercom7.h"
+#include "instance/supc.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+/** \defgroup SAME53N19A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC            0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_MCLK           2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC           3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL        4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL     5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC           6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK           7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC           10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM         11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0       12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0           14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB           32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC          35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT          36 /**< \brief Port Module (PORT) */
+#define ID_DMAC          37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX       38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS         39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2       41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2           45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_RAMECC        48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_GMAC          66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2          67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3          68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4           69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC          71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC            72 /**< \brief Analog Comparators (AC) */
+#define ID_AES           73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG          74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM           75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC         76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI          77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL           78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4       96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_SERCOM6       98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
+#define ID_SERCOM7       99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
+#define ID_TCC4         100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_TC6          101 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7          102 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC0         103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1         104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC          105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S          106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC          107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0        128 /**< \brief SD/MMC Host Controller (SDHC0) */
+#define ID_SDHC1        129 /**< \brief SD/MMC Host Controller (SDHC1) */
+
+#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+/** \defgroup SAME53N19A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0                          (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1                          (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES                           (0x42002400) /**< \brief (AES) APB Base Address */
+#define CCL                           (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC                          (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC                           (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM                         (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK                          (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC                          (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX                       (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM                           (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S                           (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK                          (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL                       (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL                    (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC                           (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC                           (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC                          (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC                         (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB                     (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI                          (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC                        (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC                          (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC                           (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0                         (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1                         (0x46000000) /**< \brief (SDHC1) AHB Base Address */
+#define SERCOM0                       (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6                       (0x43000800) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7                       (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
+#define SUPC                          (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TC0                           (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x43001400) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x43001800) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4                          (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG                          (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB                           (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC0              ((Adc      *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1              ((Adc      *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM      2                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC0, ADC1 }             /**< \brief (ADC) Instances List */
+
+#define AES               ((Aes      *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM      1                          /**< \brief (AES) Number of instances */
+#define AES_INSTS         { AES }                    /**< \brief (AES) Instances List */
+
+#define CCL               ((Ccl      *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM      1                          /**< \brief (CCL) Number of instances */
+#define CCL_INSTS         { CCL }                    /**< \brief (CCL) Instances List */
+
+#define CMCC              ((Cmcc     *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM     1                          /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS        { CMCC }                   /**< \brief (CMCC) Instances List */
+
+#define DAC               ((Dac      *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define FREQM             ((Freqm    *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM    1                          /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS       { FREQM }                  /**< \brief (FREQM) Instances List */
+
+#define GCLK              ((Gclk     *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define GMAC              ((Gmac     *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM     1                          /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS        { GMAC }                   /**< \brief (GMAC) Instances List */
+
+#define HMATRIX           ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { HMATRIX }                /**< \brief (HMATRIXB) Instances List */
+
+#define ICM               ((Icm      *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM      1                          /**< \brief (ICM) Number of instances */
+#define ICM_INSTS         { ICM }                    /**< \brief (ICM) Instances List */
+
+#define I2S               ((I2s      *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MCLK              ((Mclk     *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM     1                          /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS        { MCLK }                   /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL           ((Oscctrl  *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM  1                          /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS     { OSCCTRL }                /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL        ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1                          /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS  { OSC32KCTRL }             /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC               ((Pac      *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM      1                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC }                    /**< \brief (PAC) Instances List */
+
+#define PCC               ((Pcc      *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM      1                          /**< \brief (PCC) Number of instances */
+#define PCC_INSTS         { PCC }                    /**< \brief (PCC) Instances List */
+
+#define PDEC              ((Pdec     *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM     1                          /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS        { PDEC }                   /**< \brief (PDEC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PUKCC             ((void     *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB         ((void     *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM    1                          /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS       { PUKCC }                  /**< \brief (PUKCC) Instances List */
+
+#define QSPI              ((Qspi     *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM     1                          /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS        { QSPI }                   /**< \brief (QSPI) Instances List */
+
+#define RAMECC            ((Ramecc   *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM   1                          /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS      { RAMECC }                 /**< \brief (RAMECC) Instances List */
+
+#define RSTC              ((Rstc     *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM     1                          /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS        { RSTC }                   /**< \brief (RSTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SDHC0             ((Sdhc     *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1             ((Sdhc     *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
+#define SDHC_INST_NUM     2                          /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS        { SDHC0, SDHC1 }           /**< \brief (SDHC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6           ((Sercom   *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7           ((Sercom   *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
+#define SERCOM_INST_NUM   8                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC              ((Supc     *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM     1                          /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS        { SUPC }                   /**< \brief (SUPC) Instances List */
+
+#define TC0               ((Tc       *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x43001400UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x43001800UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4              ((Tcc      *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM      5                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG              ((Trng     *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM     1                          /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS        { TRNG }                   /**< \brief (TRNG) Instances List */
+
+#define USB               ((Usb      *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+/** \defgroup SAME53N19A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same53n19a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE            _UL_(0x00030000) /* 192 kB */
+#define FLASH_SIZE            _UL_(0x00080000) /* 512 kB */
+#define FLASH_PAGE_SIZE       512
+#define FLASH_NB_OF_PAGES     1024
+#define FLASH_USER_PAGE_SIZE  512
+#define BKUPRAM_SIZE          _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE             _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR     _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE     _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR      _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE      _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR    _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE    _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR            _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR        _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE        _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR       _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE       _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR             _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR          _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR          _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x61830303)
+#define ADC0_TOUCH_LINES_NUM  32
+#define PORT_GROUPS           3
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAME53N19A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME53N19A_H */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53n20a.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53n20a.h
new file mode 100644
index 000000000..749fea242
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/same53n20a.h	
@@ -0,0 +1,1069 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAME53N20A
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAME53N20A_
+#define _SAME53N20A_
+
+/**
+ * \ingroup SAME53_definitions
+ * \addtogroup SAME53N20A_definitions SAME53N20A definitions
+ * This file defines all structures and symbols for SAME53N20A:
+ *   - registers and bitfields
+ *   - peripheral base address
+ *   - peripheral ID
+ *   - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
+#endif
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#if defined(_U_) || defined(_L_) || defined(_UL_)
+  #error "Integer Literals macros already defined elsewhere"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
+#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
+#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
+#else /* Assembler */
+#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
+#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
+#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+
+/* ************************************************************************** */
+/**  CMSIS DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+/** \defgroup SAME53N20A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+  /******  Cortex-M4 Processor Exceptions Numbers *******************/
+  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt      */
+  HardFault_IRQn           = -13,/**<  3 Hard Fault Interrupt        */
+  MemoryManagement_IRQn    = -12,/**<  4 Memory Management Interrupt */
+  BusFault_IRQn            = -11,/**<  5 Bus Fault Interrupt         */
+  UsageFault_IRQn          = -10,/**<  6 Usage Fault Interrupt       */
+  SVCall_IRQn              = -5, /**< 11 SV Call Interrupt           */
+  DebugMonitor_IRQn        = -4, /**< 12 Debug Monitor Interrupt     */
+  PendSV_IRQn              = -2, /**< 14 Pend SV Interrupt           */
+  SysTick_IRQn             = -1, /**< 15 System Tick Interrupt       */
+  /******  SAME53N20A-specific Interrupt Numbers *********************/
+  PM_IRQn                  =  0, /**<  0 SAME53N20A Power Manager (PM) */
+  MCLK_IRQn                =  1, /**<  1 SAME53N20A Main Clock (MCLK) */
+  OSCCTRL_0_IRQn           =  2, /**<  2 SAME53N20A Oscillators Control (OSCCTRL) IRQ 0 */
+  OSCCTRL_1_IRQn           =  3, /**<  3 SAME53N20A Oscillators Control (OSCCTRL) IRQ 1 */
+  OSCCTRL_2_IRQn           =  4, /**<  4 SAME53N20A Oscillators Control (OSCCTRL) IRQ 2 */
+  OSCCTRL_3_IRQn           =  5, /**<  5 SAME53N20A Oscillators Control (OSCCTRL) IRQ 3 */
+  OSCCTRL_4_IRQn           =  6, /**<  6 SAME53N20A Oscillators Control (OSCCTRL) IRQ 4 */
+  OSC32KCTRL_IRQn          =  7, /**<  7 SAME53N20A 32kHz Oscillators Control (OSC32KCTRL) */
+  SUPC_0_IRQn              =  8, /**<  8 SAME53N20A Supply Controller (SUPC) IRQ 0 */
+  SUPC_1_IRQn              =  9, /**<  9 SAME53N20A Supply Controller (SUPC) IRQ 1 */
+  WDT_IRQn                 = 10, /**< 10 SAME53N20A Watchdog Timer (WDT) */
+  RTC_IRQn                 = 11, /**< 11 SAME53N20A Real-Time Counter (RTC) */
+  EIC_0_IRQn               = 12, /**< 12 SAME53N20A External Interrupt Controller (EIC) IRQ 0 */
+  EIC_1_IRQn               = 13, /**< 13 SAME53N20A External Interrupt Controller (EIC) IRQ 1 */
+  EIC_2_IRQn               = 14, /**< 14 SAME53N20A External Interrupt Controller (EIC) IRQ 2 */
+  EIC_3_IRQn               = 15, /**< 15 SAME53N20A External Interrupt Controller (EIC) IRQ 3 */
+  EIC_4_IRQn               = 16, /**< 16 SAME53N20A External Interrupt Controller (EIC) IRQ 4 */
+  EIC_5_IRQn               = 17, /**< 17 SAME53N20A External Interrupt Controller (EIC) IRQ 5 */
+  EIC_6_IRQn               = 18, /**< 18 SAME53N20A External Interrupt Controller (EIC) IRQ 6 */
+  EIC_7_IRQn               = 19, /**< 19 SAME53N20A External Interrupt Controller (EIC) IRQ 7 */
+  EIC_8_IRQn               = 20, /**< 20 SAME53N20A External Interrupt Controller (EIC) IRQ 8 */
+  EIC_9_IRQn               = 21, /**< 21 SAME53N20A External Interrupt Controller (EIC) IRQ 9 */
+  EIC_10_IRQn              = 22, /**< 22 SAME53N20A External Interrupt Controller (EIC) IRQ 10 */
+  EIC_11_IRQn              = 23, /**< 23 SAME53N20A External Interrupt Controller (EIC) IRQ 11 */
+  EIC_12_IRQn              = 24, /**< 24 SAME53N20A External Interrupt Controller (EIC) IRQ 12 */
+  EIC_13_IRQn              = 25, /**< 25 SAME53N20A External Interrupt Controller (EIC) IRQ 13 */
+  EIC_14_IRQn              = 26, /**< 26 SAME53N20A External Interrupt Controller (EIC) IRQ 14 */
+  EIC_15_IRQn              = 27, /**< 27 SAME53N20A External Interrupt Controller (EIC) IRQ 15 */
+  FREQM_IRQn               = 28, /**< 28 SAME53N20A Frequency Meter (FREQM) */
+  NVMCTRL_0_IRQn           = 29, /**< 29 SAME53N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+  NVMCTRL_1_IRQn           = 30, /**< 30 SAME53N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+  DMAC_0_IRQn              = 31, /**< 31 SAME53N20A Direct Memory Access Controller (DMAC) IRQ 0 */
+  DMAC_1_IRQn              = 32, /**< 32 SAME53N20A Direct Memory Access Controller (DMAC) IRQ 1 */
+  DMAC_2_IRQn              = 33, /**< 33 SAME53N20A Direct Memory Access Controller (DMAC) IRQ 2 */
+  DMAC_3_IRQn              = 34, /**< 34 SAME53N20A Direct Memory Access Controller (DMAC) IRQ 3 */
+  DMAC_4_IRQn              = 35, /**< 35 SAME53N20A Direct Memory Access Controller (DMAC) IRQ 4 */
+  EVSYS_0_IRQn             = 36, /**< 36 SAME53N20A Event System Interface (EVSYS) IRQ 0 */
+  EVSYS_1_IRQn             = 37, /**< 37 SAME53N20A Event System Interface (EVSYS) IRQ 1 */
+  EVSYS_2_IRQn             = 38, /**< 38 SAME53N20A Event System Interface (EVSYS) IRQ 2 */
+  EVSYS_3_IRQn             = 39, /**< 39 SAME53N20A Event System Interface (EVSYS) IRQ 3 */
+  EVSYS_4_IRQn             = 40, /**< 40 SAME53N20A Event System Interface (EVSYS) IRQ 4 */
+  PAC_IRQn                 = 41, /**< 41 SAME53N20A Peripheral Access Controller (PAC) */
+  RAMECC_IRQn              = 45, /**< 45 SAME53N20A RAM ECC (RAMECC) */
+  SERCOM0_0_IRQn           = 46, /**< 46 SAME53N20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+  SERCOM0_1_IRQn           = 47, /**< 47 SAME53N20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+  SERCOM0_2_IRQn           = 48, /**< 48 SAME53N20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+  SERCOM0_3_IRQn           = 49, /**< 49 SAME53N20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+  SERCOM1_0_IRQn           = 50, /**< 50 SAME53N20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+  SERCOM1_1_IRQn           = 51, /**< 51 SAME53N20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+  SERCOM1_2_IRQn           = 52, /**< 52 SAME53N20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+  SERCOM1_3_IRQn           = 53, /**< 53 SAME53N20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+  SERCOM2_0_IRQn           = 54, /**< 54 SAME53N20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+  SERCOM2_1_IRQn           = 55, /**< 55 SAME53N20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+  SERCOM2_2_IRQn           = 56, /**< 56 SAME53N20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+  SERCOM2_3_IRQn           = 57, /**< 57 SAME53N20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+  SERCOM3_0_IRQn           = 58, /**< 58 SAME53N20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+  SERCOM3_1_IRQn           = 59, /**< 59 SAME53N20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+  SERCOM3_2_IRQn           = 60, /**< 60 SAME53N20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+  SERCOM3_3_IRQn           = 61, /**< 61 SAME53N20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+  SERCOM4_0_IRQn           = 62, /**< 62 SAME53N20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+  SERCOM4_1_IRQn           = 63, /**< 63 SAME53N20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+  SERCOM4_2_IRQn           = 64, /**< 64 SAME53N20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+  SERCOM4_3_IRQn           = 65, /**< 65 SAME53N20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+  SERCOM5_0_IRQn           = 66, /**< 66 SAME53N20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+  SERCOM5_1_IRQn           = 67, /**< 67 SAME53N20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+  SERCOM5_2_IRQn           = 68, /**< 68 SAME53N20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+  SERCOM5_3_IRQn           = 69, /**< 69 SAME53N20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+  SERCOM6_0_IRQn           = 70, /**< 70 SAME53N20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
+  SERCOM6_1_IRQn           = 71, /**< 71 SAME53N20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
+  SERCOM6_2_IRQn           = 72, /**< 72 SAME53N20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
+  SERCOM6_3_IRQn           = 73, /**< 73 SAME53N20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
+  SERCOM7_0_IRQn           = 74, /**< 74 SAME53N20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
+  SERCOM7_1_IRQn           = 75, /**< 75 SAME53N20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
+  SERCOM7_2_IRQn           = 76, /**< 76 SAME53N20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
+  SERCOM7_3_IRQn           = 77, /**< 77 SAME53N20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
+  USB_0_IRQn               = 80, /**< 80 SAME53N20A Universal Serial Bus (USB) IRQ 0 */
+  USB_1_IRQn               = 81, /**< 81 SAME53N20A Universal Serial Bus (USB) IRQ 1 */
+  USB_2_IRQn               = 82, /**< 82 SAME53N20A Universal Serial Bus (USB) IRQ 2 */
+  USB_3_IRQn               = 83, /**< 83 SAME53N20A Universal Serial Bus (USB) IRQ 3 */
+  GMAC_IRQn                = 84, /**< 84 SAME53N20A Ethernet MAC (GMAC) */
+  TCC0_0_IRQn              = 85, /**< 85 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 0 */
+  TCC0_1_IRQn              = 86, /**< 86 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 1 */
+  TCC0_2_IRQn              = 87, /**< 87 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 2 */
+  TCC0_3_IRQn              = 88, /**< 88 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 3 */
+  TCC0_4_IRQn              = 89, /**< 89 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 4 */
+  TCC0_5_IRQn              = 90, /**< 90 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 5 */
+  TCC0_6_IRQn              = 91, /**< 91 SAME53N20A Timer Counter Control 0 (TCC0) IRQ 6 */
+  TCC1_0_IRQn              = 92, /**< 92 SAME53N20A Timer Counter Control 1 (TCC1) IRQ 0 */
+  TCC1_1_IRQn              = 93, /**< 93 SAME53N20A Timer Counter Control 1 (TCC1) IRQ 1 */
+  TCC1_2_IRQn              = 94, /**< 94 SAME53N20A Timer Counter Control 1 (TCC1) IRQ 2 */
+  TCC1_3_IRQn              = 95, /**< 95 SAME53N20A Timer Counter Control 1 (TCC1) IRQ 3 */
+  TCC1_4_IRQn              = 96, /**< 96 SAME53N20A Timer Counter Control 1 (TCC1) IRQ 4 */
+  TCC2_0_IRQn              = 97, /**< 97 SAME53N20A Timer Counter Control 2 (TCC2) IRQ 0 */
+  TCC2_1_IRQn              = 98, /**< 98 SAME53N20A Timer Counter Control 2 (TCC2) IRQ 1 */
+  TCC2_2_IRQn              = 99, /**< 99 SAME53N20A Timer Counter Control 2 (TCC2) IRQ 2 */
+  TCC2_3_IRQn              = 100, /**< 100 SAME53N20A Timer Counter Control 2 (TCC2) IRQ 3 */
+  TCC3_0_IRQn              = 101, /**< 101 SAME53N20A Timer Counter Control 3 (TCC3) IRQ 0 */
+  TCC3_1_IRQn              = 102, /**< 102 SAME53N20A Timer Counter Control 3 (TCC3) IRQ 1 */
+  TCC3_2_IRQn              = 103, /**< 103 SAME53N20A Timer Counter Control 3 (TCC3) IRQ 2 */
+  TCC4_0_IRQn              = 104, /**< 104 SAME53N20A Timer Counter Control 4 (TCC4) IRQ 0 */
+  TCC4_1_IRQn              = 105, /**< 105 SAME53N20A Timer Counter Control 4 (TCC4) IRQ 1 */
+  TCC4_2_IRQn              = 106, /**< 106 SAME53N20A Timer Counter Control 4 (TCC4) IRQ 2 */
+  TC0_IRQn                 = 107, /**< 107 SAME53N20A Basic Timer Counter 0 (TC0) */
+  TC1_IRQn                 = 108, /**< 108 SAME53N20A Basic Timer Counter 1 (TC1) */
+  TC2_IRQn                 = 109, /**< 109 SAME53N20A Basic Timer Counter 2 (TC2) */
+  TC3_IRQn                 = 110, /**< 110 SAME53N20A Basic Timer Counter 3 (TC3) */
+  TC4_IRQn                 = 111, /**< 111 SAME53N20A Basic Timer Counter 4 (TC4) */
+  TC5_IRQn                 = 112, /**< 112 SAME53N20A Basic Timer Counter 5 (TC5) */
+  TC6_IRQn                 = 113, /**< 113 SAME53N20A Basic Timer Counter 6 (TC6) */
+  TC7_IRQn                 = 114, /**< 114 SAME53N20A Basic Timer Counter 7 (TC7) */
+  PDEC_0_IRQn              = 115, /**< 115 SAME53N20A Quadrature Decodeur (PDEC) IRQ 0 */
+  PDEC_1_IRQn              = 116, /**< 116 SAME53N20A Quadrature Decodeur (PDEC) IRQ 1 */
+  PDEC_2_IRQn              = 117, /**< 117 SAME53N20A Quadrature Decodeur (PDEC) IRQ 2 */
+  ADC0_0_IRQn              = 118, /**< 118 SAME53N20A Analog Digital Converter 0 (ADC0) IRQ 0 */
+  ADC0_1_IRQn              = 119, /**< 119 SAME53N20A Analog Digital Converter 0 (ADC0) IRQ 1 */
+  ADC1_0_IRQn              = 120, /**< 120 SAME53N20A Analog Digital Converter 1 (ADC1) IRQ 0 */
+  ADC1_1_IRQn              = 121, /**< 121 SAME53N20A Analog Digital Converter 1 (ADC1) IRQ 1 */
+  AC_IRQn                  = 122, /**< 122 SAME53N20A Analog Comparators (AC) */
+  DAC_0_IRQn               = 123, /**< 123 SAME53N20A Digital-to-Analog Converter (DAC) IRQ 0 */
+  DAC_1_IRQn               = 124, /**< 124 SAME53N20A Digital-to-Analog Converter (DAC) IRQ 1 */
+  DAC_2_IRQn               = 125, /**< 125 SAME53N20A Digital-to-Analog Converter (DAC) IRQ 2 */
+  DAC_3_IRQn               = 126, /**< 126 SAME53N20A Digital-to-Analog Converter (DAC) IRQ 3 */
+  DAC_4_IRQn               = 127, /**< 127 SAME53N20A Digital-to-Analog Converter (DAC) IRQ 4 */
+  I2S_IRQn                 = 128, /**< 128 SAME53N20A Inter-IC Sound Interface (I2S) */
+  PCC_IRQn                 = 129, /**< 129 SAME53N20A Parallel Capture Controller (PCC) */
+  AES_IRQn                 = 130, /**< 130 SAME53N20A Advanced Encryption Standard (AES) */
+  TRNG_IRQn                = 131, /**< 131 SAME53N20A True Random Generator (TRNG) */
+  ICM_IRQn                 = 132, /**< 132 SAME53N20A Integrity Check Monitor (ICM) */
+  PUKCC_IRQn               = 133, /**< 133 SAME53N20A PUblic-Key Cryptography Controller (PUKCC) */
+  QSPI_IRQn                = 134, /**< 134 SAME53N20A Quad SPI interface (QSPI) */
+  SDHC0_IRQn               = 135, /**< 135 SAME53N20A SD/MMC Host Controller 0 (SDHC0) */
+  SDHC1_IRQn               = 136, /**< 136 SAME53N20A SD/MMC Host Controller 1 (SDHC1) */
+
+  PERIPH_COUNT_IRQn        = 137  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNonMaskableInt_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManagement_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pvReservedM9;
+  void* pvReservedM8;
+  void* pvReservedM7;
+  void* pvReservedM6;
+  void* pfnSVCall_Handler;
+  void* pfnDebugMonitor_Handler;
+  void* pvReservedM3;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                    /*  0 Power Manager */
+  void* pfnMCLK_Handler;                  /*  1 Main Clock */
+  void* pfnOSCCTRL_0_Handler;             /*  2 Oscillators Control IRQ 0 */
+  void* pfnOSCCTRL_1_Handler;             /*  3 Oscillators Control IRQ 1 */
+  void* pfnOSCCTRL_2_Handler;             /*  4 Oscillators Control IRQ 2 */
+  void* pfnOSCCTRL_3_Handler;             /*  5 Oscillators Control IRQ 3 */
+  void* pfnOSCCTRL_4_Handler;             /*  6 Oscillators Control IRQ 4 */
+  void* pfnOSC32KCTRL_Handler;            /*  7 32kHz Oscillators Control */
+  void* pfnSUPC_0_Handler;                /*  8 Supply Controller IRQ 0 */
+  void* pfnSUPC_1_Handler;                /*  9 Supply Controller IRQ 1 */
+  void* pfnWDT_Handler;                   /* 10 Watchdog Timer */
+  void* pfnRTC_Handler;                   /* 11 Real-Time Counter */
+  void* pfnEIC_0_Handler;                 /* 12 External Interrupt Controller IRQ 0 */
+  void* pfnEIC_1_Handler;                 /* 13 External Interrupt Controller IRQ 1 */
+  void* pfnEIC_2_Handler;                 /* 14 External Interrupt Controller IRQ 2 */
+  void* pfnEIC_3_Handler;                 /* 15 External Interrupt Controller IRQ 3 */
+  void* pfnEIC_4_Handler;                 /* 16 External Interrupt Controller IRQ 4 */
+  void* pfnEIC_5_Handler;                 /* 17 External Interrupt Controller IRQ 5 */
+  void* pfnEIC_6_Handler;                 /* 18 External Interrupt Controller IRQ 6 */
+  void* pfnEIC_7_Handler;                 /* 19 External Interrupt Controller IRQ 7 */
+  void* pfnEIC_8_Handler;                 /* 20 External Interrupt Controller IRQ 8 */
+  void* pfnEIC_9_Handler;                 /* 21 External Interrupt Controller IRQ 9 */
+  void* pfnEIC_10_Handler;                /* 22 External Interrupt Controller IRQ 10 */
+  void* pfnEIC_11_Handler;                /* 23 External Interrupt Controller IRQ 11 */
+  void* pfnEIC_12_Handler;                /* 24 External Interrupt Controller IRQ 12 */
+  void* pfnEIC_13_Handler;                /* 25 External Interrupt Controller IRQ 13 */
+  void* pfnEIC_14_Handler;                /* 26 External Interrupt Controller IRQ 14 */
+  void* pfnEIC_15_Handler;                /* 27 External Interrupt Controller IRQ 15 */
+  void* pfnFREQM_Handler;                 /* 28 Frequency Meter */
+  void* pfnNVMCTRL_0_Handler;             /* 29 Non-Volatile Memory Controller IRQ 0 */
+  void* pfnNVMCTRL_1_Handler;             /* 30 Non-Volatile Memory Controller IRQ 1 */
+  void* pfnDMAC_0_Handler;                /* 31 Direct Memory Access Controller IRQ 0 */
+  void* pfnDMAC_1_Handler;                /* 32 Direct Memory Access Controller IRQ 1 */
+  void* pfnDMAC_2_Handler;                /* 33 Direct Memory Access Controller IRQ 2 */
+  void* pfnDMAC_3_Handler;                /* 34 Direct Memory Access Controller IRQ 3 */
+  void* pfnDMAC_4_Handler;                /* 35 Direct Memory Access Controller IRQ 4 */
+  void* pfnEVSYS_0_Handler;               /* 36 Event System Interface IRQ 0 */
+  void* pfnEVSYS_1_Handler;               /* 37 Event System Interface IRQ 1 */
+  void* pfnEVSYS_2_Handler;               /* 38 Event System Interface IRQ 2 */
+  void* pfnEVSYS_3_Handler;               /* 39 Event System Interface IRQ 3 */
+  void* pfnEVSYS_4_Handler;               /* 40 Event System Interface IRQ 4 */
+  void* pfnPAC_Handler;                   /* 41 Peripheral Access Controller */
+  void* pvReserved42;
+  void* pvReserved43;
+  void* pvReserved44;
+  void* pfnRAMECC_Handler;                /* 45 RAM ECC */
+  void* pfnSERCOM0_0_Handler;             /* 46 Serial Communication Interface 0 IRQ 0 */
+  void* pfnSERCOM0_1_Handler;             /* 47 Serial Communication Interface 0 IRQ 1 */
+  void* pfnSERCOM0_2_Handler;             /* 48 Serial Communication Interface 0 IRQ 2 */
+  void* pfnSERCOM0_3_Handler;             /* 49 Serial Communication Interface 0 IRQ 3 */
+  void* pfnSERCOM1_0_Handler;             /* 50 Serial Communication Interface 1 IRQ 0 */
+  void* pfnSERCOM1_1_Handler;             /* 51 Serial Communication Interface 1 IRQ 1 */
+  void* pfnSERCOM1_2_Handler;             /* 52 Serial Communication Interface 1 IRQ 2 */
+  void* pfnSERCOM1_3_Handler;             /* 53 Serial Communication Interface 1 IRQ 3 */
+  void* pfnSERCOM2_0_Handler;             /* 54 Serial Communication Interface 2 IRQ 0 */
+  void* pfnSERCOM2_1_Handler;             /* 55 Serial Communication Interface 2 IRQ 1 */
+  void* pfnSERCOM2_2_Handler;             /* 56 Serial Communication Interface 2 IRQ 2 */
+  void* pfnSERCOM2_3_Handler;             /* 57 Serial Communication Interface 2 IRQ 3 */
+  void* pfnSERCOM3_0_Handler;             /* 58 Serial Communication Interface 3 IRQ 0 */
+  void* pfnSERCOM3_1_Handler;             /* 59 Serial Communication Interface 3 IRQ 1 */
+  void* pfnSERCOM3_2_Handler;             /* 60 Serial Communication Interface 3 IRQ 2 */
+  void* pfnSERCOM3_3_Handler;             /* 61 Serial Communication Interface 3 IRQ 3 */
+  void* pfnSERCOM4_0_Handler;             /* 62 Serial Communication Interface 4 IRQ 0 */
+  void* pfnSERCOM4_1_Handler;             /* 63 Serial Communication Interface 4 IRQ 1 */
+  void* pfnSERCOM4_2_Handler;             /* 64 Serial Communication Interface 4 IRQ 2 */
+  void* pfnSERCOM4_3_Handler;             /* 65 Serial Communication Interface 4 IRQ 3 */
+  void* pfnSERCOM5_0_Handler;             /* 66 Serial Communication Interface 5 IRQ 0 */
+  void* pfnSERCOM5_1_Handler;             /* 67 Serial Communication Interface 5 IRQ 1 */
+  void* pfnSERCOM5_2_Handler;             /* 68 Serial Communication Interface 5 IRQ 2 */
+  void* pfnSERCOM5_3_Handler;             /* 69 Serial Communication Interface 5 IRQ 3 */
+  void* pfnSERCOM6_0_Handler;             /* 70 Serial Communication Interface 6 IRQ 0 */
+  void* pfnSERCOM6_1_Handler;             /* 71 Serial Communication Interface 6 IRQ 1 */
+  void* pfnSERCOM6_2_Handler;             /* 72 Serial Communication Interface 6 IRQ 2 */
+  void* pfnSERCOM6_3_Handler;             /* 73 Serial Communication Interface 6 IRQ 3 */
+  void* pfnSERCOM7_0_Handler;             /* 74 Serial Communication Interface 7 IRQ 0 */
+  void* pfnSERCOM7_1_Handler;             /* 75 Serial Communication Interface 7 IRQ 1 */
+  void* pfnSERCOM7_2_Handler;             /* 76 Serial Communication Interface 7 IRQ 2 */
+  void* pfnSERCOM7_3_Handler;             /* 77 Serial Communication Interface 7 IRQ 3 */
+  void* pvReserved78;
+  void* pvReserved79;
+  void* pfnUSB_0_Handler;                 /* 80 Universal Serial Bus IRQ 0 */
+  void* pfnUSB_1_Handler;                 /* 81 Universal Serial Bus IRQ 1 */
+  void* pfnUSB_2_Handler;                 /* 82 Universal Serial Bus IRQ 2 */
+  void* pfnUSB_3_Handler;                 /* 83 Universal Serial Bus IRQ 3 */
+  void* pfnGMAC_Handler;                  /* 84 Ethernet MAC */
+  void* pfnTCC0_0_Handler;                /* 85 Timer Counter Control 0 IRQ 0 */
+  void* pfnTCC0_1_Handler;                /* 86 Timer Counter Control 0 IRQ 1 */
+  void* pfnTCC0_2_Handler;                /* 87 Timer Counter Control 0 IRQ 2 */
+  void* pfnTCC0_3_Handler;                /* 88 Timer Counter Control 0 IRQ 3 */
+  void* pfnTCC0_4_Handler;                /* 89 Timer Counter Control 0 IRQ 4 */
+  void* pfnTCC0_5_Handler;                /* 90 Timer Counter Control 0 IRQ 5 */
+  void* pfnTCC0_6_Handler;                /* 91 Timer Counter Control 0 IRQ 6 */
+  void* pfnTCC1_0_Handler;                /* 92 Timer Counter Control 1 IRQ 0 */
+  void* pfnTCC1_1_Handler;                /* 93 Timer Counter Control 1 IRQ 1 */
+  void* pfnTCC1_2_Handler;                /* 94 Timer Counter Control 1 IRQ 2 */
+  void* pfnTCC1_3_Handler;                /* 95 Timer Counter Control 1 IRQ 3 */
+  void* pfnTCC1_4_Handler;                /* 96 Timer Counter Control 1 IRQ 4 */
+  void* pfnTCC2_0_Handler;                /* 97 Timer Counter Control 2 IRQ 0 */
+  void* pfnTCC2_1_Handler;                /* 98 Timer Counter Control 2 IRQ 1 */
+  void* pfnTCC2_2_Handler;                /* 99 Timer Counter Control 2 IRQ 2 */
+  void* pfnTCC2_3_Handler;                /* 100 Timer Counter Control 2 IRQ 3 */
+  void* pfnTCC3_0_Handler;                /* 101 Timer Counter Control 3 IRQ 0 */
+  void* pfnTCC3_1_Handler;                /* 102 Timer Counter Control 3 IRQ 1 */
+  void* pfnTCC3_2_Handler;                /* 103 Timer Counter Control 3 IRQ 2 */
+  void* pfnTCC4_0_Handler;                /* 104 Timer Counter Control 4 IRQ 0 */
+  void* pfnTCC4_1_Handler;                /* 105 Timer Counter Control 4 IRQ 1 */
+  void* pfnTCC4_2_Handler;                /* 106 Timer Counter Control 4 IRQ 2 */
+  void* pfnTC0_Handler;                   /* 107 Basic Timer Counter 0 */
+  void* pfnTC1_Handler;                   /* 108 Basic Timer Counter 1 */
+  void* pfnTC2_Handler;                   /* 109 Basic Timer Counter 2 */
+  void* pfnTC3_Handler;                   /* 110 Basic Timer Counter 3 */
+  void* pfnTC4_Handler;                   /* 111 Basic Timer Counter 4 */
+  void* pfnTC5_Handler;                   /* 112 Basic Timer Counter 5 */
+  void* pfnTC6_Handler;                   /* 113 Basic Timer Counter 6 */
+  void* pfnTC7_Handler;                   /* 114 Basic Timer Counter 7 */
+  void* pfnPDEC_0_Handler;                /* 115 Quadrature Decodeur IRQ 0 */
+  void* pfnPDEC_1_Handler;                /* 116 Quadrature Decodeur IRQ 1 */
+  void* pfnPDEC_2_Handler;                /* 117 Quadrature Decodeur IRQ 2 */
+  void* pfnADC0_0_Handler;                /* 118 Analog Digital Converter 0 IRQ 0 */
+  void* pfnADC0_1_Handler;                /* 119 Analog Digital Converter 0 IRQ 1 */
+  void* pfnADC1_0_Handler;                /* 120 Analog Digital Converter 1 IRQ 0 */
+  void* pfnADC1_1_Handler;                /* 121 Analog Digital Converter 1 IRQ 1 */
+  void* pfnAC_Handler;                    /* 122 Analog Comparators */
+  void* pfnDAC_0_Handler;                 /* 123 Digital-to-Analog Converter IRQ 0 */
+  void* pfnDAC_1_Handler;                 /* 124 Digital-to-Analog Converter IRQ 1 */
+  void* pfnDAC_2_Handler;                 /* 125 Digital-to-Analog Converter IRQ 2 */
+  void* pfnDAC_3_Handler;                 /* 126 Digital-to-Analog Converter IRQ 3 */
+  void* pfnDAC_4_Handler;                 /* 127 Digital-to-Analog Converter IRQ 4 */
+  void* pfnI2S_Handler;                   /* 128 Inter-IC Sound Interface */
+  void* pfnPCC_Handler;                   /* 129 Parallel Capture Controller */
+  void* pfnAES_Handler;                   /* 130 Advanced Encryption Standard */
+  void* pfnTRNG_Handler;                  /* 131 True Random Generator */
+  void* pfnICM_Handler;                   /* 132 Integrity Check Monitor */
+  void* pfnPUKCC_Handler;                 /* 133 PUblic-Key Cryptography Controller */
+  void* pfnQSPI_Handler;                  /* 134 Quad SPI interface */
+  void* pfnSDHC0_Handler;                 /* 135 SD/MMC Host Controller 0 */
+  void* pfnSDHC1_Handler;                 /* 136 SD/MMC Host Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M4 processor handlers */
+void Reset_Handler               ( void );
+void NonMaskableInt_Handler      ( void );
+void HardFault_Handler           ( void );
+void MemManagement_Handler       ( void );
+void BusFault_Handler            ( void );
+void UsageFault_Handler          ( void );
+void SVCall_Handler              ( void );
+void DebugMonitor_Handler        ( void );
+void PendSV_Handler              ( void );
+void SysTick_Handler             ( void );
+
+/* Peripherals handlers */
+void PM_Handler                  ( void );
+void MCLK_Handler                ( void );
+void OSCCTRL_0_Handler           ( void );
+void OSCCTRL_1_Handler           ( void );
+void OSCCTRL_2_Handler           ( void );
+void OSCCTRL_3_Handler           ( void );
+void OSCCTRL_4_Handler           ( void );
+void OSC32KCTRL_Handler          ( void );
+void SUPC_0_Handler              ( void );
+void SUPC_1_Handler              ( void );
+void WDT_Handler                 ( void );
+void RTC_Handler                 ( void );
+void EIC_0_Handler               ( void );
+void EIC_1_Handler               ( void );
+void EIC_2_Handler               ( void );
+void EIC_3_Handler               ( void );
+void EIC_4_Handler               ( void );
+void EIC_5_Handler               ( void );
+void EIC_6_Handler               ( void );
+void EIC_7_Handler               ( void );
+void EIC_8_Handler               ( void );
+void EIC_9_Handler               ( void );
+void EIC_10_Handler              ( void );
+void EIC_11_Handler              ( void );
+void EIC_12_Handler              ( void );
+void EIC_13_Handler              ( void );
+void EIC_14_Handler              ( void );
+void EIC_15_Handler              ( void );
+void FREQM_Handler               ( void );
+void NVMCTRL_0_Handler           ( void );
+void NVMCTRL_1_Handler           ( void );
+void DMAC_0_Handler              ( void );
+void DMAC_1_Handler              ( void );
+void DMAC_2_Handler              ( void );
+void DMAC_3_Handler              ( void );
+void DMAC_4_Handler              ( void );
+void EVSYS_0_Handler             ( void );
+void EVSYS_1_Handler             ( void );
+void EVSYS_2_Handler             ( void );
+void EVSYS_3_Handler             ( void );
+void EVSYS_4_Handler             ( void );
+void PAC_Handler                 ( void );
+void RAMECC_Handler              ( void );
+void SERCOM0_0_Handler           ( void );
+void SERCOM0_1_Handler           ( void );
+void SERCOM0_2_Handler           ( void );
+void SERCOM0_3_Handler           ( void );
+void SERCOM1_0_Handler           ( void );
+void SERCOM1_1_Handler           ( void );
+void SERCOM1_2_Handler           ( void );
+void SERCOM1_3_Handler           ( void );
+void SERCOM2_0_Handler           ( void );
+void SERCOM2_1_Handler           ( void );
+void SERCOM2_2_Handler           ( void );
+void SERCOM2_3_Handler           ( void );
+void SERCOM3_0_Handler           ( void );
+void SERCOM3_1_Handler           ( void );
+void SERCOM3_2_Handler           ( void );
+void SERCOM3_3_Handler           ( void );
+void SERCOM4_0_Handler           ( void );
+void SERCOM4_1_Handler           ( void );
+void SERCOM4_2_Handler           ( void );
+void SERCOM4_3_Handler           ( void );
+void SERCOM5_0_Handler           ( void );
+void SERCOM5_1_Handler           ( void );
+void SERCOM5_2_Handler           ( void );
+void SERCOM5_3_Handler           ( void );
+void SERCOM6_0_Handler           ( void );
+void SERCOM6_1_Handler           ( void );
+void SERCOM6_2_Handler           ( void );
+void SERCOM6_3_Handler           ( void );
+void SERCOM7_0_Handler           ( void );
+void SERCOM7_1_Handler           ( void );
+void SERCOM7_2_Handler           ( void );
+void SERCOM7_3_Handler           ( void );
+void USB_0_Handler               ( void );
+void USB_1_Handler               ( void );
+void USB_2_Handler               ( void );
+void USB_3_Handler               ( void );
+void GMAC_Handler                ( void );
+void TCC0_0_Handler              ( void );
+void TCC0_1_Handler              ( void );
+void TCC0_2_Handler              ( void );
+void TCC0_3_Handler              ( void );
+void TCC0_4_Handler              ( void );
+void TCC0_5_Handler              ( void );
+void TCC0_6_Handler              ( void );
+void TCC1_0_Handler              ( void );
+void TCC1_1_Handler              ( void );
+void TCC1_2_Handler              ( void );
+void TCC1_3_Handler              ( void );
+void TCC1_4_Handler              ( void );
+void TCC2_0_Handler              ( void );
+void TCC2_1_Handler              ( void );
+void TCC2_2_Handler              ( void );
+void TCC2_3_Handler              ( void );
+void TCC3_0_Handler              ( void );
+void TCC3_1_Handler              ( void );
+void TCC3_2_Handler              ( void );
+void TCC4_0_Handler              ( void );
+void TCC4_1_Handler              ( void );
+void TCC4_2_Handler              ( void );
+void TC0_Handler                 ( void );
+void TC1_Handler                 ( void );
+void TC2_Handler                 ( void );
+void TC3_Handler                 ( void );
+void TC4_Handler                 ( void );
+void TC5_Handler                 ( void );
+void TC6_Handler                 ( void );
+void TC7_Handler                 ( void );
+void PDEC_0_Handler              ( void );
+void PDEC_1_Handler              ( void );
+void PDEC_2_Handler              ( void );
+void ADC0_0_Handler              ( void );
+void ADC0_1_Handler              ( void );
+void ADC1_0_Handler              ( void );
+void ADC1_1_Handler              ( void );
+void AC_Handler                  ( void );
+void DAC_0_Handler               ( void );
+void DAC_1_Handler               ( void );
+void DAC_2_Handler               ( void );
+void DAC_3_Handler               ( void );
+void DAC_4_Handler               ( void );
+void I2S_Handler                 ( void );
+void PCC_Handler                 ( void );
+void AES_Handler                 ( void );
+void TRNG_Handler                ( void );
+void ICM_Handler                 ( void );
+void PUKCC_Handler               ( void );
+void QSPI_Handler                ( void );
+void SDHC0_Handler               ( void );
+void SDHC1_Handler               ( void );
+
+/*
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              1         /*!< Core revision r0p1 */
+#define __DEBUG_LVL            3         /*!< Full debug plus DWT data matching */
+#define __FPU_PRESENT          1         /*!< FPU present or not */
+#define __MPU_PRESENT          1         /*!< MPU present or not */
+#define __NVIC_PRIO_BITS       3         /*!< Number of bits used for Priority Levels */
+#define __TRACE_LVL            2         /*!< Full trace: ITM, DWT triggers and counters, ETM */
+#define __VTOR_PRESENT         1         /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_same53.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME53N20A */
+/* ************************************************************************** */
+/** \defgroup SAME53N20A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/aes.h"
+#include "component/ccl.h"
+#include "component/cmcc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/freqm.h"
+#include "component/gclk.h"
+#include "component/gmac.h"
+#include "component/hmatrixb.h"
+#include "component/icm.h"
+#include "component/i2s.h"
+#include "component/mclk.h"
+#include "component/nvmctrl.h"
+#include "component/oscctrl.h"
+#include "component/osc32kctrl.h"
+#include "component/pac.h"
+#include "component/pcc.h"
+#include "component/pdec.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/qspi.h"
+#include "component/ramecc.h"
+#include "component/rstc.h"
+#include "component/rtc.h"
+#include "component/sdhc.h"
+#include "component/sercom.h"
+#include "component/supc.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/trng.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  REGISTERS ACCESS DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+/** \defgroup SAME53N20A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc0.h"
+#include "instance/adc1.h"
+#include "instance/aes.h"
+#include "instance/ccl.h"
+#include "instance/cmcc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/freqm.h"
+#include "instance/gclk.h"
+#include "instance/gmac.h"
+#include "instance/hmatrix.h"
+#include "instance/icm.h"
+#include "instance/i2s.h"
+#include "instance/mclk.h"
+#include "instance/nvmctrl.h"
+#include "instance/oscctrl.h"
+#include "instance/osc32kctrl.h"
+#include "instance/pac.h"
+#include "instance/pcc.h"
+#include "instance/pdec.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/pukcc.h"
+#include "instance/qspi.h"
+#include "instance/ramecc.h"
+#include "instance/rstc.h"
+#include "instance/rtc.h"
+#include "instance/sdhc0.h"
+#include "instance/sdhc1.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sercom6.h"
+#include "instance/sercom7.h"
+#include "instance/supc.h"
+#include "instance/tc0.h"
+#include "instance/tc1.h"
+#include "instance/tc2.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/tcc3.h"
+#include "instance/tcc4.h"
+#include "instance/trng.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  PERIPHERAL ID DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+/** \defgroup SAME53N20A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC            0 /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM             1 /**< \brief Power Manager (PM) */
+#define ID_MCLK           2 /**< \brief Main Clock (MCLK) */
+#define ID_RSTC           3 /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL        4 /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL     5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC           6 /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK           7 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT            8 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC            9 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC           10 /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM         11 /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0       12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1       13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_TC0           14 /**< \brief Basic Timer Counter 0 (TC0) */
+#define ID_TC1           15 /**< \brief Basic Timer Counter 1 (TC1) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_USB           32 /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC          35 /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT          36 /**< \brief Port Module (PORT) */
+#define ID_DMAC          37 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX       38 /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS         39 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2       41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3       42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0          43 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1          44 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TC2           45 /**< \brief Basic Timer Counter 2 (TC2) */
+#define ID_TC3           46 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_RAMECC        48 /**< \brief RAM ECC (RAMECC) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_GMAC          66 /**< \brief Ethernet MAC (GMAC) */
+#define ID_TCC2          67 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TCC3          68 /**< \brief Timer Counter Control 3 (TCC3) */
+#define ID_TC4           69 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5           70 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_PDEC          71 /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC            72 /**< \brief Analog Comparators (AC) */
+#define ID_AES           73 /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG          74 /**< \brief True Random Generator (TRNG) */
+#define ID_ICM           75 /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC         76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI          77 /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL           78 /**< \brief Configurable Custom Logic (CCL) */
+
+// Peripheral instances on HPB3 bridge
+#define ID_SERCOM4       96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5       97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_SERCOM6       98 /**< \brief Serial Communication Interface 6 (SERCOM6) */
+#define ID_SERCOM7       99 /**< \brief Serial Communication Interface 7 (SERCOM7) */
+#define ID_TCC4         100 /**< \brief Timer Counter Control 4 (TCC4) */
+#define ID_TC6          101 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7          102 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC0         103 /**< \brief Analog Digital Converter 0 (ADC0) */
+#define ID_ADC1         104 /**< \brief Analog Digital Converter 1 (ADC1) */
+#define ID_DAC          105 /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S          106 /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC          107 /**< \brief Parallel Capture Controller (PCC) */
+
+// Peripheral instances on AHB (as if on bridge 4)
+#define ID_SDHC0        128 /**< \brief SD/MMC Host Controller (SDHC0) */
+#define ID_SDHC1        129 /**< \brief SD/MMC Host Controller (SDHC1) */
+
+#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/**  BASE ADDRESS DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+/** \defgroup SAME53N20A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC                            (0x42002000) /**< \brief (AC) APB Base Address */
+#define ADC0                          (0x43001C00) /**< \brief (ADC0) APB Base Address */
+#define ADC1                          (0x43002000) /**< \brief (ADC1) APB Base Address */
+#define AES                           (0x42002400) /**< \brief (AES) APB Base Address */
+#define CCL                           (0x42003800) /**< \brief (CCL) APB Base Address */
+#define CMCC                          (0x41006000) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000) /**< \brief (CMCC) AHB Base Address */
+#define DAC                           (0x43002400) /**< \brief (DAC) APB Base Address */
+#define DMAC                          (0x4100A000) /**< \brief (DMAC) APB Base Address */
+#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
+#define EIC                           (0x40002800) /**< \brief (EIC) APB Base Address */
+#define EVSYS                         (0x4100E000) /**< \brief (EVSYS) APB Base Address */
+#define FREQM                         (0x40002C00) /**< \brief (FREQM) APB Base Address */
+#define GCLK                          (0x40001C00) /**< \brief (GCLK) APB Base Address */
+#define GMAC                          (0x42000800) /**< \brief (GMAC) APB Base Address */
+#define HMATRIX                       (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
+#define ICM                           (0x42002C00) /**< \brief (ICM) APB Base Address */
+#define I2S                           (0x43002800) /**< \brief (I2S) APB Base Address */
+#define MCLK                          (0x40000800) /**< \brief (MCLK) APB Base Address */
+#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
+#define OSCCTRL                       (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
+#define OSC32KCTRL                    (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
+#define PAC                           (0x40000000) /**< \brief (PAC) APB Base Address */
+#define PCC                           (0x43002C00) /**< \brief (PCC) APB Base Address */
+#define PDEC                          (0x42001C00) /**< \brief (PDEC) APB Base Address */
+#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
+#define PORT                          (0x41008000) /**< \brief (PORT) APB Base Address */
+#define PUKCC                         (0x42003000) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB                     (0x02000000) /**< \brief (PUKCC) AHB Base Address */
+#define QSPI                          (0x42003400) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000) /**< \brief (QSPI) AHB Base Address */
+#define RAMECC                        (0x41020000) /**< \brief (RAMECC) APB Base Address */
+#define RSTC                          (0x40000C00) /**< \brief (RSTC) APB Base Address */
+#define RTC                           (0x40002400) /**< \brief (RTC) APB Base Address */
+#define SDHC0                         (0x45000000) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1                         (0x46000000) /**< \brief (SDHC1) AHB Base Address */
+#define SERCOM0                       (0x40003000) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1                       (0x40003400) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2                       (0x41012000) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3                       (0x41014000) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4                       (0x43000000) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5                       (0x43000400) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6                       (0x43000800) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7                       (0x43000C00) /**< \brief (SERCOM7) APB Base Address */
+#define SUPC                          (0x40001800) /**< \brief (SUPC) APB Base Address */
+#define TC0                           (0x40003800) /**< \brief (TC0) APB Base Address */
+#define TC1                           (0x40003C00) /**< \brief (TC1) APB Base Address */
+#define TC2                           (0x4101A000) /**< \brief (TC2) APB Base Address */
+#define TC3                           (0x4101C000) /**< \brief (TC3) APB Base Address */
+#define TC4                           (0x42001400) /**< \brief (TC4) APB Base Address */
+#define TC5                           (0x42001800) /**< \brief (TC5) APB Base Address */
+#define TC6                           (0x43001400) /**< \brief (TC6) APB Base Address */
+#define TC7                           (0x43001800) /**< \brief (TC7) APB Base Address */
+#define TCC0                          (0x41016000) /**< \brief (TCC0) APB Base Address */
+#define TCC1                          (0x41018000) /**< \brief (TCC1) APB Base Address */
+#define TCC2                          (0x42000C00) /**< \brief (TCC2) APB Base Address */
+#define TCC3                          (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4                          (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG                          (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB                           (0x41000000) /**< \brief (USB) APB Base Address */
+#define WDT                           (0x40002000) /**< \brief (WDT) APB Base Address */
+#else
+#define AC                ((Ac       *)0x42002000UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
+#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
+
+#define ADC0              ((Adc      *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
+#define ADC1              ((Adc      *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
+#define ADC_INST_NUM      2                          /**< \brief (ADC) Number of instances */
+#define ADC_INSTS         { ADC0, ADC1 }             /**< \brief (ADC) Instances List */
+
+#define AES               ((Aes      *)0x42002400UL) /**< \brief (AES) APB Base Address */
+#define AES_INST_NUM      1                          /**< \brief (AES) Number of instances */
+#define AES_INSTS         { AES }                    /**< \brief (AES) Instances List */
+
+#define CCL               ((Ccl      *)0x42003800UL) /**< \brief (CCL) APB Base Address */
+#define CCL_INST_NUM      1                          /**< \brief (CCL) Number of instances */
+#define CCL_INSTS         { CCL }                    /**< \brief (CCL) Instances List */
+
+#define CMCC              ((Cmcc     *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
+#define CMCC_AHB                      (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
+#define CMCC_INST_NUM     1                          /**< \brief (CMCC) Number of instances */
+#define CMCC_INSTS        { CMCC }                   /**< \brief (CMCC) Instances List */
+
+#define DAC               ((Dac      *)0x43002400UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
+#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
+
+#define DMAC              ((Dmac     *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
+
+#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
+#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
+
+#define EIC               ((Eic      *)0x40002800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
+#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
+
+#define EVSYS             ((Evsys    *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
+
+#define FREQM             ((Freqm    *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
+#define FREQM_INST_NUM    1                          /**< \brief (FREQM) Number of instances */
+#define FREQM_INSTS       { FREQM }                  /**< \brief (FREQM) Instances List */
+
+#define GCLK              ((Gclk     *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
+
+#define GMAC              ((Gmac     *)0x42000800UL) /**< \brief (GMAC) APB Base Address */
+#define GMAC_INST_NUM     1                          /**< \brief (GMAC) Number of instances */
+#define GMAC_INSTS        { GMAC }                   /**< \brief (GMAC) Instances List */
+
+#define HMATRIX           ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS    { HMATRIX }                /**< \brief (HMATRIXB) Instances List */
+
+#define ICM               ((Icm      *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
+#define ICM_INST_NUM      1                          /**< \brief (ICM) Number of instances */
+#define ICM_INSTS         { ICM }                    /**< \brief (ICM) Instances List */
+
+#define I2S               ((I2s      *)0x43002800UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
+#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
+
+#define MCLK              ((Mclk     *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
+#define MCLK_INST_NUM     1                          /**< \brief (MCLK) Number of instances */
+#define MCLK_INSTS        { MCLK }                   /**< \brief (MCLK) Instances List */
+
+#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_SW0                   (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
+#define NVMCTRL_TEMP_LOG              (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
+
+#define OSCCTRL           ((Oscctrl  *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
+#define OSCCTRL_INST_NUM  1                          /**< \brief (OSCCTRL) Number of instances */
+#define OSCCTRL_INSTS     { OSCCTRL }                /**< \brief (OSCCTRL) Instances List */
+
+#define OSC32KCTRL        ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
+#define OSC32KCTRL_INST_NUM 1                          /**< \brief (OSC32KCTRL) Number of instances */
+#define OSC32KCTRL_INSTS  { OSC32KCTRL }             /**< \brief (OSC32KCTRL) Instances List */
+
+#define PAC               ((Pac      *)0x40000000UL) /**< \brief (PAC) APB Base Address */
+#define PAC_INST_NUM      1                          /**< \brief (PAC) Number of instances */
+#define PAC_INSTS         { PAC }                    /**< \brief (PAC) Instances List */
+
+#define PCC               ((Pcc      *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
+#define PCC_INST_NUM      1                          /**< \brief (PCC) Number of instances */
+#define PCC_INSTS         { PCC }                    /**< \brief (PCC) Instances List */
+
+#define PDEC              ((Pdec     *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
+#define PDEC_INST_NUM     1                          /**< \brief (PDEC) Number of instances */
+#define PDEC_INSTS        { PDEC }                   /**< \brief (PDEC) Instances List */
+
+#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
+#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
+
+#define PORT              ((Port     *)0x41008000UL) /**< \brief (PORT) APB Base Address */
+#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
+#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
+
+#define PUKCC             ((void     *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
+#define PUKCC_AHB         ((void     *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
+#define PUKCC_INST_NUM    1                          /**< \brief (PUKCC) Number of instances */
+#define PUKCC_INSTS       { PUKCC }                  /**< \brief (PUKCC) Instances List */
+
+#define QSPI              ((Qspi     *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
+#define QSPI_AHB                      (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
+#define QSPI_INST_NUM     1                          /**< \brief (QSPI) Number of instances */
+#define QSPI_INSTS        { QSPI }                   /**< \brief (QSPI) Instances List */
+
+#define RAMECC            ((Ramecc   *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
+#define RAMECC_INST_NUM   1                          /**< \brief (RAMECC) Number of instances */
+#define RAMECC_INSTS      { RAMECC }                 /**< \brief (RAMECC) Instances List */
+
+#define RSTC              ((Rstc     *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
+#define RSTC_INST_NUM     1                          /**< \brief (RSTC) Number of instances */
+#define RSTC_INSTS        { RSTC }                   /**< \brief (RSTC) Instances List */
+
+#define RTC               ((Rtc      *)0x40002400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
+#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
+
+#define SDHC0             ((Sdhc     *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
+#define SDHC1             ((Sdhc     *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */
+#define SDHC_INST_NUM     2                          /**< \brief (SDHC) Number of instances */
+#define SDHC_INSTS        { SDHC0, SDHC1 }           /**< \brief (SDHC) Instances List */
+
+#define SERCOM0           ((Sercom   *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1           ((Sercom   *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2           ((Sercom   *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3           ((Sercom   *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4           ((Sercom   *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5           ((Sercom   *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM6           ((Sercom   *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */
+#define SERCOM7           ((Sercom   *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */
+#define SERCOM_INST_NUM   8                          /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */
+
+#define SUPC              ((Supc     *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
+#define SUPC_INST_NUM     1                          /**< \brief (SUPC) Number of instances */
+#define SUPC_INSTS        { SUPC }                   /**< \brief (SUPC) Instances List */
+
+#define TC0               ((Tc       *)0x40003800UL) /**< \brief (TC0) APB Base Address */
+#define TC1               ((Tc       *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
+#define TC2               ((Tc       *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
+#define TC3               ((Tc       *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
+#define TC4               ((Tc       *)0x42001400UL) /**< \brief (TC4) APB Base Address */
+#define TC5               ((Tc       *)0x42001800UL) /**< \brief (TC5) APB Base Address */
+#define TC6               ((Tc       *)0x43001400UL) /**< \brief (TC6) APB Base Address */
+#define TC7               ((Tc       *)0x43001800UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM       8                          /**< \brief (TC) Number of instances */
+#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0              ((Tcc      *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1              ((Tcc      *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2              ((Tcc      *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
+#define TCC3              ((Tcc      *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
+#define TCC4              ((Tcc      *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
+#define TCC_INST_NUM      5                          /**< \brief (TCC) Number of instances */
+#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
+
+#define TRNG              ((Trng     *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
+#define TRNG_INST_NUM     1                          /**< \brief (TRNG) Number of instances */
+#define TRNG_INSTS        { TRNG }                   /**< \brief (TRNG) Instances List */
+
+#define USB               ((Usb      *)0x41000000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
+#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
+
+#define WDT               ((Wdt      *)0x40002000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
+#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/**  PORT DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+/** \defgroup SAME53N20A_port PORT Definitions */
+/*@{*/
+
+#include "pio/same53n20a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/**  MEMORY MAPPING DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+
+#define HSRAM_SIZE            _UL_(0x00040000) /* 256 kB */
+#define FLASH_SIZE            _UL_(0x00100000) /* 1024 kB */
+#define FLASH_PAGE_SIZE       512
+#define FLASH_NB_OF_PAGES     2048
+#define FLASH_USER_PAGE_SIZE  512
+#define BKUPRAM_SIZE          _UL_(0x00002000) /* 8 kB */
+#define QSPI_SIZE             _UL_(0x01000000) /* 16384 kB */
+
+#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
+#define CMCC_DATARAM_ADDR     _UL_(0x03000000) /**< CMCC_DATARAM base address */
+#define CMCC_DATARAM_SIZE     _UL_(0x00001000) /**< CMCC_DATARAM size */
+#define CMCC_TAGRAM_ADDR      _UL_(0x03001000) /**< CMCC_TAGRAM base address */
+#define CMCC_TAGRAM_SIZE      _UL_(0x00000400) /**< CMCC_TAGRAM size */
+#define CMCC_VALIDRAM_ADDR    _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
+#define CMCC_VALIDRAM_SIZE    _UL_(0x00000040) /**< CMCC_VALIDRAM size */
+#define HSRAM_ADDR            _UL_(0x20000000) /**< HSRAM base address */
+#define HSRAM_ETB_ADDR        _UL_(0x20000000) /**< HSRAM_ETB base address */
+#define HSRAM_ETB_SIZE        _UL_(0x00008000) /**< HSRAM_ETB size */
+#define HSRAM_RET1_ADDR       _UL_(0x20000000) /**< HSRAM_RET1 base address */
+#define HSRAM_RET1_SIZE       _UL_(0x00008000) /**< HSRAM_RET1 size */
+#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
+#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
+#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
+#define HPB3_ADDR             _UL_(0x43000000) /**< HPB3 base address */
+#define SEEPROM_ADDR          _UL_(0x44000000) /**< SEEPROM base address */
+#define BKUPRAM_ADDR          _UL_(0x47000000) /**< BKUPRAM base address */
+#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE    _UL_(0x61830302)
+#define ADC0_TOUCH_LINES_NUM  32
+#define PORT_GROUPS           3
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAME53N20A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAME53N20A_H */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/system_same53.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/system_same53.h
new file mode 100644
index 000000000..50f8ec774
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/Third Party/SAME53/CMSIS/Device/Include/system_same53.h	
@@ -0,0 +1,48 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SYSTEM_SAME53_H_INCLUDED_
+#define _SYSTEM_SAME53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern const uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAME53_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/linker_scripts/gcc/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/linker_scripts/gcc/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/linker_scripts/gcc/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/linker_scripts/gcc/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/linker_scripts/gcc/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/linker_scripts/gcc/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/pins_arduino.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/pins_arduino.h
new file mode 100644
index 000000000..c6118a3ad
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/pins_arduino.h
@@ -0,0 +1,129 @@
+/*
+  pins_arduino.h - Pin definition functions for Arduino
+  Part of Arduino - http://www.arduino.cc/
+
+  Copyright 2020, Teknic, Inc.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General
+  Public License along with this library; if not, write to the
+  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
+  Boston, MA  02111-1307  USA
+*/
+
+#include "variant.h"
+#include "SysManager.h"
+
+// Arduino-esque pin names
+#define IO0 CLEARCORE_PIN_IO0
+#define IO1 CLEARCORE_PIN_IO1
+#define IO2 CLEARCORE_PIN_IO2
+#define IO3 CLEARCORE_PIN_IO3
+#define IO4 CLEARCORE_PIN_IO4
+#define IO5 CLEARCORE_PIN_IO5
+
+#define DI6 CLEARCORE_PIN_DI6
+#define DI7 CLEARCORE_PIN_DI7
+#define DI8 CLEARCORE_PIN_DI8
+
+#define A9  CLEARCORE_PIN_A9
+#define A10 CLEARCORE_PIN_A10
+#define A11 CLEARCORE_PIN_A11
+#define A12 CLEARCORE_PIN_A12
+
+#define M0 CLEARCORE_PIN_M0
+#define M1 CLEARCORE_PIN_M1
+#define M2 CLEARCORE_PIN_M2
+#define M3 CLEARCORE_PIN_M3
+
+#define M0_INA CLEARCORE_PIN_M0_INA
+#define M0_INB CLEARCORE_PIN_M0_INB
+#define M1_INA CLEARCORE_PIN_M1_INA
+#define M1_INB CLEARCORE_PIN_M1_INB
+#define M2_INA CLEARCORE_PIN_M2_INA
+#define M2_INB CLEARCORE_PIN_M2_INB
+#define M3_INA CLEARCORE_PIN_M3_INA
+#define M3_INB CLEARCORE_PIN_M3_INB
+
+// CCIO-8 pin names 
+#define CCIOA0 CLEARCORE_PIN_CCIOA0
+#define CCIOA1 CLEARCORE_PIN_CCIOA1
+#define CCIOA2 CLEARCORE_PIN_CCIOA2
+#define CCIOA3 CLEARCORE_PIN_CCIOA3
+#define CCIOA4 CLEARCORE_PIN_CCIOA4
+#define CCIOA5 CLEARCORE_PIN_CCIOA5
+#define CCIOA6 CLEARCORE_PIN_CCIOA6
+#define CCIOA7 CLEARCORE_PIN_CCIOA7
+#define CCIOB0 CLEARCORE_PIN_CCIOB0
+#define CCIOB1 CLEARCORE_PIN_CCIOB1
+#define CCIOB2 CLEARCORE_PIN_CCIOB2
+#define CCIOB3 CLEARCORE_PIN_CCIOB3
+#define CCIOB4 CLEARCORE_PIN_CCIOB4
+#define CCIOB5 CLEARCORE_PIN_CCIOB5
+#define CCIOB6 CLEARCORE_PIN_CCIOB6
+#define CCIOB7 CLEARCORE_PIN_CCIOB7
+#define CCIOC0 CLEARCORE_PIN_CCIOC0
+#define CCIOC1 CLEARCORE_PIN_CCIOC1
+#define CCIOC2 CLEARCORE_PIN_CCIOC2
+#define CCIOC3 CLEARCORE_PIN_CCIOC3
+#define CCIOC4 CLEARCORE_PIN_CCIOC4
+#define CCIOC5 CLEARCORE_PIN_CCIOC5
+#define CCIOC6 CLEARCORE_PIN_CCIOC6
+#define CCIOC7 CLEARCORE_PIN_CCIOC7
+#define CCIOD0 CLEARCORE_PIN_CCIOD0
+#define CCIOD1 CLEARCORE_PIN_CCIOD1
+#define CCIOD2 CLEARCORE_PIN_CCIOD2
+#define CCIOD3 CLEARCORE_PIN_CCIOD3
+#define CCIOD4 CLEARCORE_PIN_CCIOD4
+#define CCIOD5 CLEARCORE_PIN_CCIOD5
+#define CCIOD6 CLEARCORE_PIN_CCIOD6
+#define CCIOD7 CLEARCORE_PIN_CCIOD7
+#define CCIOE0 CLEARCORE_PIN_CCIOE0
+#define CCIOE1 CLEARCORE_PIN_CCIOE1
+#define CCIOE2 CLEARCORE_PIN_CCIOE2
+#define CCIOE3 CLEARCORE_PIN_CCIOE3
+#define CCIOE4 CLEARCORE_PIN_CCIOE4
+#define CCIOE5 CLEARCORE_PIN_CCIOE5
+#define CCIOE6 CLEARCORE_PIN_CCIOE6
+#define CCIOE7 CLEARCORE_PIN_CCIOE7
+#define CCIOF0 CLEARCORE_PIN_CCIOF0
+#define CCIOF1 CLEARCORE_PIN_CCIOF1
+#define CCIOF2 CLEARCORE_PIN_CCIOF2
+#define CCIOF3 CLEARCORE_PIN_CCIOF3
+#define CCIOF4 CLEARCORE_PIN_CCIOF4
+#define CCIOF5 CLEARCORE_PIN_CCIOF5
+#define CCIOF6 CLEARCORE_PIN_CCIOF6
+#define CCIOF7 CLEARCORE_PIN_CCIOF7
+#define CCIOG0 CLEARCORE_PIN_CCIOG0
+#define CCIOG1 CLEARCORE_PIN_CCIOG1
+#define CCIOG2 CLEARCORE_PIN_CCIOG2
+#define CCIOG3 CLEARCORE_PIN_CCIOG3
+#define CCIOG4 CLEARCORE_PIN_CCIOG4
+#define CCIOG5 CLEARCORE_PIN_CCIOG5
+#define CCIOG6 CLEARCORE_PIN_CCIOG6
+#define CCIOG7 CLEARCORE_PIN_CCIOG7
+#define CCIOH0 CLEARCORE_PIN_CCIOH0
+#define CCIOH1 CLEARCORE_PIN_CCIOH1
+#define CCIOH2 CLEARCORE_PIN_CCIOH2
+#define CCIOH3 CLEARCORE_PIN_CCIOH3
+#define CCIOH4 CLEARCORE_PIN_CCIOH4
+#define CCIOH5 CLEARCORE_PIN_CCIOH5
+#define CCIOH6 CLEARCORE_PIN_CCIOH6
+#define CCIOH7 CLEARCORE_PIN_CCIOH7
+
+
+#define SS   CLEARCORE_PIN_INVALID
+#define MOSI CLEARCORE_PIN_INVALID
+#define MISO CLEARCORE_PIN_INVALID
+#define SCK  CLEARCORE_PIN_INVALID
+
+#define SDCARD_SPI SPI2
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/sync.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/sync.h
new file mode 100644
index 000000000..de5ba06fb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/sync.h
@@ -0,0 +1,47 @@
+/*
+  Copyright (c) 2019 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <stdint.h>
+
+#ifndef _SYNC_H_
+#define _SYNC_H_
+/*
+ * Synchronization primitives.
+ */
+
+class __Guard {
+public:
+	__Guard() : primask(__get_PRIMASK()), loops(1) {
+		__disable_irq();
+	}
+	~__Guard() {
+		if (primask == 0) {
+			__enable_irq();
+			// http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/BIHBFEIB.html
+			__ISB();
+		}
+	}
+	uint32_t enter() { return loops--; }
+private:
+	uint32_t primask;
+	uint32_t loops;
+};
+
+#define synchronized for (__Guard __guard; __guard.enter(); )
+
+#endif
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/variant.cpp b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/variant.cpp
new file mode 100644
index 000000000..de84cab20
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/variant.cpp
@@ -0,0 +1,543 @@
+/*
+  Copyright 2020, Teknic, Inc.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+
+#include "variant.h"
+#include <component/eic.h>
+#include <delay.h>
+#include <sam.h>
+#include "AdcManager.h"
+#include "DigitalInOutAnalogOut.h"
+#include "DigitalInAnalogIn.h"
+#include "DigitalInOut.h"
+#include "DigitalIn.h"
+#include "DigitalInOutHBridge.h"
+#include "InputManager.h"
+#include "LedDriver.h"
+#include "MotorDriver.h"
+#include "SysConnectors.h"
+#include "SysManager.h"
+#include "SysUtils.h"
+#include "CcioBoardManager.h"
+#include "ShiftRegister.h"
+#include "MotorManager.h"
+
+#define ADC ADC1
+
+// Board resource controller
+namespace ClearCore {
+extern SysManager SysMgr;
+extern AdcManager &AdcMgr;
+extern InputManager &InputMgr;
+}
+
+static void *OutputPulsesSetup(pin_size_t pin);
+
+// analogReadResolution(), mapResolution() from wiring_analog.c
+
+void analogReadResolution(int res) {
+    ClearCore::AdcMgr.AdcResolution(res);
+}
+
+static inline uint32_t mapResolution(uint32_t value,
+    uint32_t from, uint32_t to) {
+    if (from == to) {
+        return value;
+    }
+    if (from > to) {
+        return value >> (from - to);
+    }
+    return value << (to - from);
+}
+
+PinStatus digitalReadClearCore(pin_size_t conNum) {
+    // check if trying to read a motor input
+    if (conNum > CLEARCORE_PIN_MAX && conNum <= M3_INB) {
+        int motorPin = -1;
+        switch (conNum) {
+            case M0_INA:
+            case M0_INB:
+                motorPin = M0;
+                break;
+            case M1_INA:
+            case M1_INB:
+                motorPin = M1;
+                break;
+            case M2_INA:
+            case M2_INB:
+                motorPin = M2;
+                break;
+            case M3_INA:
+            case M3_INB:
+                motorPin = M3;
+                break;
+        }
+        
+        // Get a reference to the appropriate motor
+        ClearCore::MotorDriver *motor =
+            static_cast<ClearCore::MotorDriver*>(
+                ClearCore::SysMgr.ConnectorByIndex(
+                    static_cast<ClearCorePins>(motorPin)));
+                
+        if (conNum > CLEARCORE_PIN_MAX && conNum < M0_INB) {
+            return motor->MotorInAState() ? LOW : HIGH;
+        } 
+        else {
+            return motor->MotorInBState() ? LOW : HIGH;
+        }
+    }
+    
+    // Get a reference to the appropriate connector
+    ClearCore::Connector *connector =
+        ClearCore::SysMgr.ConnectorByIndex(
+            static_cast<ClearCorePins>(conNum));
+
+    if (!connector) {
+        return LOW;
+    }
+
+    // If connector is in an input mode, make sure it is in digital input
+    if (!connector->IsWritable()) {
+        connector->Mode(ClearCore::Connector::INPUT_DIGITAL);
+    }
+
+    return (PinStatus)connector->State();
+}
+
+void digitalWriteClearCore(pin_size_t conNum, PinStatus ulVal) {
+    // check if trying to write to a motor input
+    if (conNum > CLEARCORE_PIN_MAX && conNum <= M3_INB) {
+        int motorPin = -1;
+        switch (conNum) {
+            case M0_INA:
+            case M0_INB:
+                motorPin = M0;
+                break;
+            case M1_INA:
+            case M1_INB:
+                motorPin = M1;
+                break;
+            case M2_INA:
+            case M2_INB:
+                motorPin = M2;
+                break;
+            case M3_INA:
+            case M3_INB:
+                motorPin = M3;
+                break;
+        }
+        
+        // Get a reference to the appropriate motor
+        ClearCore::MotorDriver *motor =
+            static_cast<ClearCore::MotorDriver*>(
+                ClearCore::SysMgr.ConnectorByIndex(
+                    static_cast<ClearCorePins>(motorPin)));
+
+        if (conNum > CLEARCORE_PIN_MAX && conNum < M0_INB) {
+            motor->MotorInAState(ulVal);
+        }
+        else {
+            motor->MotorInBState(ulVal);
+        }
+    } 
+    else {
+        // Get a reference to the appropriate connector
+        ClearCore::Connector *connector =
+            ClearCore::SysMgr.ConnectorByIndex(
+                static_cast<ClearCorePins>(conNum));
+
+        // If connector cannot be written, just return
+        if (!connector || !connector->IsWritable()) {
+            return;
+        }
+
+        connector->Mode(ClearCore::Connector::OUTPUT_DIGITAL);
+        if (connector->Mode() == ClearCore::Connector::OUTPUT_DIGITAL) {
+            connector->State(ulVal);
+        }
+    }    
+}
+
+/**
+    This function replaces pinModeAPI in most cases as ClearCore uses
+    a connector model in place of the pin model of the traditional Arduino
+    implementations.
+**/
+void pinModeClearCore(ClearCorePins conNum, PinMode ulMode) {
+    // Get a reference to the appropriate connector
+    ClearCore::Connector *connector =
+        ClearCore::SysMgr.ConnectorByIndex(
+            static_cast<ClearCorePins>(conNum));
+
+    if (!connector) {
+        return;
+    }
+
+    switch (ulMode) {
+        case OUTPUT:
+            connector->Mode(ClearCore::Connector::OUTPUT_DIGITAL);
+            break;
+        case INPUT:
+            connector->Mode(ClearCore::Connector::INPUT_DIGITAL);
+            break;
+        case INPUT_PULLUP:
+            connector->Mode(ClearCore::Connector::INPUT_DIGITAL);
+            break;
+        default:
+            break;
+    }
+}
+
+int analogReadAPI(pin_size_t pinNumber, AnalogInputUnits units) {
+    // Get a reference to the appropriate connector
+    ClearCore::Connector *connector =
+        ClearCore::SysMgr.ConnectorByIndex(
+            static_cast<ClearCorePins>(pinNumber));
+    
+    if (!connector) {
+        return 0;
+    }
+    
+    // Ensure the connector is in analog input mode
+    connector->Mode(ClearCore::Connector::INPUT_ANALOG);
+    if (connector->Mode() != ClearCore::Connector::INPUT_ANALOG) {
+        // Analog input not supported on this connector
+        return 0;
+    }
+    // Assume State() function returns 15-bit result
+    int adcRawValue = connector->State();
+
+    // Convert result to millivolts if applicable.
+    if (units == MILLIVOLTS) {
+        int valueMax;
+
+        switch (ClearCore::AdcMgr.AdcResolution()) {
+            case 8:
+                valueMax = 255;
+                break;
+            case 10:
+                valueMax = 1023;
+                break;
+            case 12:
+                valueMax = 4095;
+                break;
+            case 16:
+                valueMax = 65535;
+                break;
+            default:
+                // Shouldn't get here, assume 12-bit default
+                valueMax = 4095;
+            break;
+        }
+        
+        return int(round(1000 * 9.9 * adcRawValue / valueMax));
+    }
+    else {
+        return adcRawValue;
+    }
+}
+
+void analogWriteAPI(pin_size_t conNum, int value, AnalogOutMode mode,
+                    AnalogOutputUnits units) {
+    // Get a reference to the appropriate connector
+    ClearCore::Connector *connector =
+        ClearCore::SysMgr.ConnectorByIndex(
+            static_cast<ClearCorePins>(conNum));
+
+    // If connector cannot be written, just return
+    if (!connector || !connector->IsWritable()) {
+        return;
+    }
+
+    if (mode == PWM && units == MICROAMPS) {
+        return; // Invalid combination of mode/units.
+    }
+
+    // Convert to raw DAC value if specified in microamps
+    if (units == MICROAMPS) {
+        // First constrain the value to be in the 0-20 mA range.
+        value = constrain(value, 0, 20000);
+        value = int(round(value * 4095.0 / 20000.0));
+    }
+
+    switch (mode) {
+        case PWM:
+            switch (connector->Type()) {
+                case ClearCore::Connector::ANALOG_OUT_DIGITAL_IN_OUT_TYPE:
+                case ClearCore::Connector::DIGITAL_IN_OUT_TYPE:
+                case ClearCore::Connector::H_BRIDGE_TYPE:
+                    connector->Mode(ClearCore::Connector::OUTPUT_PWM);
+                    connector->State(value);
+                    break;
+                default:
+                    break;
+            }
+            break;
+        case CURRENT:
+            switch (connector->Type()) {
+                case ClearCore::Connector::ANALOG_OUT_DIGITAL_IN_OUT_TYPE:
+                    connector->Mode(ClearCore::Connector::OUTPUT_ANALOG);
+                    connector->State(value);
+                    break;
+                default:
+                    // unsupported connector type
+                    break;
+            }
+            break;
+    } // switch (mode)
+}
+
+/**
+    This function is the implementation of the public facing pinMode. The pin 
+    number in this case refers to a "connector" object in the global Connector
+    connector array.
+**/
+void pinMode(pin_size_t pinNumber, uint32_t ulMode) {
+    pinModeClearCore((ClearCorePins)pinNumber, (PinMode)ulMode);
+}
+
+pin_size_t digitalPinToInterrupt(pin_size_t pinNumber) {
+    // assert pin number is within valid range
+    ClearCorePins ccPin = static_cast<ClearCorePins>(pinNumber);
+
+    if (ccPin < CLEARCORE_PIN_DI6 || ccPin > CLEARCORE_PIN_A12) {
+        return 255;
+    }
+    
+    return ClearCore::SysMgr.ConnectorByIndex(ccPin)->ExternalInterrupt();
+}
+
+void attachInterrupt(pin_size_t interruptNumber, voidFuncPtr callback,
+                     PinStatus mode) {
+    if (interruptNumber >= EIC_NUMBER_OF_INTERRUPTS) {
+        return;
+    }
+
+    // If attaching an interrupt to an analog input connector, make sure to 
+    // set up the connector in digital input mode.
+    ClearCore::Connector *analogInput;
+    for (int32_t pin = CLEARCORE_PIN_A9; pin <= CLEARCORE_PIN_A12; pin++) {
+        analogInput = ClearCore::SysMgr.ConnectorByIndex((ClearCorePins)pin);
+
+        if (interruptNumber == analogInput->ExternalInterrupt()) {
+            if (analogInput->Mode() != ClearCore::Connector::INPUT_DIGITAL) {
+                analogInput->Mode(ClearCore::Connector::INPUT_DIGITAL);
+            }
+            break;
+        }
+    }
+
+    ClearCore::InputMgr.InterruptHandlerSet(interruptNumber, callback,
+        static_cast<ClearCore::InputManager::InterruptTrigger>(mode));
+}
+
+void detachInterrupt(pin_size_t interruptNumber) {
+    if (interruptNumber >= EIC_NUMBER_OF_INTERRUPTS) {
+        return;
+    }
+
+    ClearCore::InputMgr.InterruptHandlerSet(interruptNumber);
+}
+
+void interrupts() {
+    ClearCore::InputMgr.InterruptsEnabled(true);
+}
+
+void noInterrupts() {
+   ClearCore::InputMgr.InterruptsEnabled(false);
+}
+
+// implementation of pulseIn and pulseInLong from Common.h
+
+/** 
+    Measures the length (in microseconds) of a pulse on the pin.
+
+    This function is essentially a wrapper for pulseInLong().
+
+    \param <pin> {The pin to measure a pulse on}
+    \param <state> {HIGH or LOW}
+    \param <timeout> {The maximum amount of time to measure a pulse for in uS.}
+    \return {The pulse width, or 0 if there was no pulse detected before 
+    timeout.}
+ **/
+uint32_t pulseIn(pin_size_t pin, uint8_t state, unsigned long timeout) {
+    return pulseInLong(pin, state, timeout);
+}
+
+/** 
+    \brief Measures the length (in microseconds) of a pulse on the pin.
+
+    \details Measures the duration of a pulse on a pin. The minimum pulse width
+    duration depends on the digital input filtering selected on the given pin.
+    The minimum pulse width is the digital filter sample length * 200 
+    microseconds. If state is HIGH, this function will measure the width
+    between a rising edge and its falling edge. If state is LOW, it will
+    measure between a falling edge and its rising edge. This function will
+    return after a complete pulse is measured, or the timeout period has
+    elapsed regardless of whether or not any edges were detected.
+
+    \param <pin> {The pin to measure a pulse on}
+    \param <state> HIGH or LOW}
+    \param <timeout> {The maximum amount of time to measure a pulse for in uS.}
+    \return {The pulse width in uS, or 0 if there was no pulse detected before 
+            timeout.}
+ **/
+uint32_t pulseInLong(pin_size_t pin, uint8_t state, unsigned long timeout) {
+
+    PinStatus desiredState = (PinStatus) state;
+    if (!(desiredState == HIGH || desiredState == LOW)) {
+        // unsupported pin state
+        return 0;
+    }
+
+    // Get a reference to the appropriate connector
+    ClearCore::Connector *connector =
+        ClearCore::SysMgr.ConnectorByIndex(
+            static_cast<ClearCorePins>(pin));
+
+    // If this is an invalid connector or in output mode, bail out
+    if (!connector || connector->IsWritable()) {
+        return 0;
+    }
+
+    // Put the connector in digital input mode
+    connector->Mode(ClearCore::Connector::INPUT_DIGITAL);
+    if (connector->Mode() != ClearCore::Connector::INPUT_DIGITAL) {
+        // This connector does not support digital input, bail out
+        return 0;
+    }
+
+    unsigned long startTime = micros();
+
+    // twiddle your thumbs until the previous pulse ends
+    while (connector->State() == desiredState) {
+        if (micros() - startTime < timeout) {
+            continue;
+        }
+        else {
+            // out of time for the pulse request
+            return 0;
+        }
+    }
+
+    // wait for a new pulse to begin
+    while (connector->State() != desiredState) {
+        if (micros() - startTime < timeout) {
+            continue;
+        }
+        else {
+            // out of time for the pulse request
+            return 0;
+        }
+    }
+
+    // wait for the pulse to end
+    unsigned long pulseBegin = micros();
+    while (connector->State() == desiredState) {
+        if (micros() - startTime < timeout) {
+            continue;
+        }
+        else {
+            // ran out of time before the pulse ended
+            return 0;
+        }
+    }
+
+    unsigned long currentTime = micros();
+    if (currentTime - startTime < timeout) {
+        return currentTime - pulseBegin;
+    }
+    else {
+        return 0;
+    }
+}
+
+/**
+    \return Returns a pointer to the connector or CCIO-8 manager responsible for 
+    the pin or null if pulse out operations aren't unsupported for the pin.
+**/
+static void *OutputPulsesSetup(pin_size_t pin) {
+    ClearCore::Connector *connector =
+        ClearCore::SysMgr.ConnectorByIndex(static_cast<ClearCorePins>(pin));
+
+	if (!connector) {
+		return NULL;
+	}
+    // If connector hasn't been initialized yet, just return
+    if (connector->Mode() == ClearCore::Connector::INVALID_NONE) {
+		return NULL;
+	}
+    switch (connector->Type()) {
+        case ClearCore::Connector::ANALOG_OUT_DIGITAL_IN_OUT_TYPE:
+        case ClearCore::Connector::H_BRIDGE_TYPE:
+        case ClearCore::Connector::DIGITAL_IN_OUT_TYPE:
+        case ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE:
+            return connector;
+        default:
+            return nullptr; // unsupported connector type
+    }
+}
+
+void OutputPulsesStart(pin_size_t pin, uint32_t onTime, uint32_t offTime,
+                       uint16_t pulseCnt, bool blockUntilDone) {
+    ClearCore::Connector *connector = 
+        static_cast<ClearCore::Connector *>(OutputPulsesSetup(pin));
+
+    if (!connector) {
+        return;
+    }
+    // If connector hasn't been initialized yet, just return
+    if (connector->Mode() == ClearCore::Connector::INVALID_NONE) {
+		return;
+	}
+
+    if (connector->Type() == ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE) {
+	    static_cast<ClearCore::CcioPin *>(connector)->
+		    OutputPulsesStart(onTime, offTime, pulseCnt, blockUntilDone);
+	}
+	else {
+        static_cast<ClearCore::DigitalInOut *>(connector)->
+            OutputPulsesStart(onTime, offTime, pulseCnt, blockUntilDone);
+    }
+}
+
+void OutputPulsesStop(pin_size_t pin) {
+    OutputPulsesStop(pin, true);
+}
+
+void OutputPulsesStop(pin_size_t pin, bool stopImmediately) {
+	ClearCore::Connector *connector = 
+        static_cast<ClearCore::Connector *>(OutputPulsesSetup(pin));
+
+	if (!connector) {
+        return;
+    }
+    // If connector hasn't been initialized yet, just return
+    if (connector->Mode() == ClearCore::Connector::INVALID_NONE) {
+		return;
+	}
+
+	if (connector->Type() == ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE) {
+	    static_cast<ClearCore::CcioPin *>(
+            connector)->OutputPulsesStop(stopImmediately);
+    }
+    else {
+	    static_cast<ClearCore::DigitalInOut *>(
+            connector)->OutputPulsesStop(stopImmediately);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/variant.h b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/variant.h
new file mode 100644
index 000000000..52a73e1e5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/variants/clearcore/variant.h
@@ -0,0 +1,49 @@
+/*
+  Copyright 2020, Teknic, Inc.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef __CLEARCORE_VARIANT_H__
+#define __CLEARCORE_VARIANT_H__
+
+// The definitions here needs a SAMD core >=1.6.10
+#define ARDUINO_SAMD_VARIANT_COMPLIANCE 10610
+// Core clock frequency
+#define VARIANT_MCK 120000000       // __SYSTEM_CLOCK
+
+
+#include "WVariant.h"
+#include "Common.h"
+
+#ifdef __cplusplus
+#include "SERCOM.h"
+#include "Uart.h"
+#endif
+
+enum _ADC_CHANNELS {
+    SDRVR3_IMON = PIN_PC00,
+    SDRVR2_IMON = PIN_PC01,
+    VSUPP_MON = PIN_PC02,
+    V5VOB_MON = PIN_PB04,
+    AIN09 = PIN_PB07,
+    AIN10 = PIN_PB06,
+    AIN11 = PIN_PB05,
+    AIN12 = PIN_PC03
+};
+
+
+#endif //__CLEARCORE_VARIANT_H__
+
diff --git a/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/zipClearCore.cmd b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/zipClearCore.cmd
new file mode 100644
index 000000000..9a6ae3e07
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Arduino-wrapper/zipClearCore.cmd
@@ -0,0 +1,42 @@
+set ver=1.1.2
+rem set version=shell git describe --dirty --always --tags
+
+.\keywordify.py -S -p .\ 
+
+set zipDir=ClearCore-%ver%
+
+rem Make the directory to zip
+md %zipDir%
+
+rem Copy everything into the zip directory
+robocopy .\ .\%zipDir% *.* /E
+
+cd %zipDir%
+
+rem Remove the copied (empty) zip directory
+rd /s /q .\%zipDir%
+
+rem Remove various files not intended for release
+rd /s /q .\Style
+rd /s /q .\Debug
+rd /s /q .\Release
+del .\zipClearCore.cmd
+del .\package_clearcore_index.json
+
+rem Delete all the git repos in the directory structure
+for /d /r . %%d in (.git) do @if exist "%%d" rd /s /q "%%d"
+for /d /r . %%d in (.gitlab) do @if exist "%%d" rd /s /q "%%d"
+
+rem Delete all git-related files in the directory structure
+del /s .\*.git*
+
+rem Delete all object and dependency files in the directory structure
+del /s .\*.o .\*.d
+
+cd ..
+
+rem Zip it
+"C:\Program Files\7-Zip\7z.exe" a -r "%zipDir%.zip" ".\%zipDir%"
+
+rem Remove the temp directory
+rd /s /q .\%zipDir%
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-Modbus-HMI-example.zip b/vendor/teknic/clear-core/ClearCore-Modbus-HMI-example.zip
new file mode 100644
index 000000000..7090041c9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-Modbus-HMI-example.zip
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:9207d0362c9357b6d11fcb3d051a7f0e6a738ecfcf2da19532146e7fbf7ad020
+size 11213419
diff --git a/vendor/teknic/clear-core/ClearCore-library/.gitignore b/vendor/teknic/clear-core/ClearCore-library/.gitignore
new file mode 100644
index 000000000..2c5e11bd2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/.gitignore
@@ -0,0 +1,40 @@
+# Prerequisites
+*.d
+
+# Compiled Object files
+*.slo
+*.lo
+*.o
+*.obj
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+*.dll
+
+# Fortran module files
+*.mod
+*.smod
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
+*.lib
+
+# Executables
+*.exe
+*.out
+*.app
+
+libClearCore/UnitTests/
+libClearCore/Doc/DoxygenOut/html/
+jlink.*
+*.componentinfo.xml
+.vs/
+Debug/
+Release/
diff --git a/vendor/teknic/clear-core/ClearCore-library/.travis.yml b/vendor/teknic/clear-core/ClearCore-library/.travis.yml
new file mode 100644
index 000000000..d77316ef9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/.travis.yml
@@ -0,0 +1,28 @@
+# This will run on Travis' 'new' container-based infrastructure
+sudo: false 
+
+# Blacklist
+branches:
+  only:
+    - master
+
+# Install dependencies
+addons:
+  apt:
+    packages:
+      - doxygen
+      - graphviz
+
+# Build your code e.g. by calling make
+script:
+  - doxygen libClearCore/Doc/libClearCore.cfg
+  - touch /home/travis/build/Teknic-Inc/ClearCore-library/html/.nojekyll
+
+# Generate and deploy documentation
+deploy:
+  provider: pages
+  skip_cleanup: true
+  local_dir: html
+  github_token: $GH_REPO_TOKEN
+  on:
+    branch: master
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP.cppproj b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP.cppproj
new file mode 100644
index 000000000..a7eda8394
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP.cppproj
@@ -0,0 +1,860 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{c373696c-5d45-4b91-ad62-a21552361596}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>StaticLibrary</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>lib$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.a</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AvrGccProjectExtensions>
+    </AvrGccProjectExtensions>
+    <AssemblyName>LwIP</AssemblyName>
+    <Name>LwIP</Name>
+    <RootNamespace>LwIP</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>0</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>False</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include</Value>
+            <Value>../LwIP/port/include</Value>
+            <Value>../LwIP/src/include</Value>
+            <Value>../../libClearCore/inc</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Default (-g2)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
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+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.assembler.general.IncludePaths>
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+            <Value>%24(PackRepoDir)\Atmel\SAME53_DFP\1.1.118\include</Value>
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+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
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+        </armgcccpp.preprocessingassembler.general.IncludePaths>
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+      </ArmGccCpp>
+    </ToolchainSettings>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>False</armgcc.common.outputfiles.bin>
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+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include</Value>
+            <Value>../LwIP/port/include</Value>
+            <Value>../LwIP/src/include</Value>
+            <Value>../../libClearCore/inc</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include</Value>
+            <Value>../LwIP/port/include</Value>
+            <Value>../LwIP/src/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\cmsis\5.0.1\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\Atmel\SAME53_DFP\1.1.118\include</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\cmsis\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\Atmel\SAME53_DFP\1.1.118\include</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <OutputPath>bin\Release\</OutputPath>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="LwIP\port\include\arch\cc.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\port\include\arch\perf.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\port\include\ethernetif.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\port\include\lwipopts.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\api_lib.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\api_msg.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\err.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\if_api.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\netbuf.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\netdb.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\netifapi.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\sockets.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\api\tcpip.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\core\altcp.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\core\altcp_alloc.c">
+      <SubType>compile</SubType>
+    </Compile>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\core\ipv4\ip4_addr.c">
+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\core\ipv6\dhcp6.c">
+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\lwip\priv\sockets_priv.h">
+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\lwip\priv\tcpip_priv.h">
+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\lwip\priv\tcp_priv.h">
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\lwip\tcp.h">
+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\lwip\tcpbase.h">
+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\netif\ppp\polarssl\sha1.h">
+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\include\netif\ppp\pppoe.h">
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+      <SubType>compile</SubType>
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+    <Compile Include="LwIP\src\netif\ppp\ipcp.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\ipv6cp.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\lcp.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\magic.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\mppe.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\multilink.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\polarssl\arc4.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\polarssl\des.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\polarssl\md4.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\polarssl\md5.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\polarssl\sha1.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\ppp.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\pppapi.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\pppcrypt.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\pppoe.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\pppol2tp.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\pppos.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\upap.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\utils.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\ppp\vj.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\slipif.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="LwIP\src\netif\zepif.c">
+      <SubType>compile</SubType>
+    </Compile>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="LwIP\src" />
+    <Folder Include="LwIP\port\include" />
+    <Folder Include="LwIP\port\include\arch" />
+    <Folder Include="LwIP\port" />
+    <Folder Include="LwIP" />
+    <Folder Include="LwIP\src\api" />
+    <Folder Include="LwIP\src\core" />
+    <Folder Include="LwIP\src\core\ipv4" />
+    <Folder Include="LwIP\src\core\ipv6" />
+    <Folder Include="LwIP\src\include" />
+    <Folder Include="LwIP\src\include\compat" />
+    <Folder Include="LwIP\src\include\compat\posix\arpa" />
+    <Folder Include="LwIP\src\include\compat\posix\net" />
+    <Folder Include="LwIP\src\include\compat\posix\sys" />
+    <Folder Include="LwIP\src\include\compat\stdc" />
+    <Folder Include="LwIP\src\include\compat\posix" />
+    <Folder Include="LwIP\src\include\lwip" />
+    <Folder Include="LwIP\src\include\lwip\prot" />
+    <Folder Include="LwIP\src\include\lwip\priv" />
+    <Folder Include="LwIP\src\include\netif" />
+    <Folder Include="LwIP\src\include\netif\ppp" />
+    <Folder Include="LwIP\src\include\netif\ppp\polarssl" />
+    <Folder Include="LwIP\src\netif" />
+    <Folder Include="LwIP\src\netif\ppp" />
+    <Folder Include="LwIP\src\netif\ppp\polarssl" />
+  </ItemGroup>
+  <ItemGroup>
+    <None Include="LwIP\src\include\lwip\init.h.cmake.in">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="LwIP\src\netif\FILES">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="LwIP\src\netif\ppp\polarssl\README">
+      <SubType>compile</SubType>
+    </None>
+    <None Include="LwIP\src\netif\ppp\PPPD_FOLLOWUP">
+      <SubType>compile</SubType>
+    </None>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/arch/cc.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/arch/cc.h
new file mode 100644
index 000000000..7000376a6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/arch/cc.h
@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief lwIP abstraction layer.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef CC_H_INCLUDED
+#define CC_H_INCLUDED
+
+#include <stdio.h>
+#include <stdint.h>
+
+/* Define platform endianness */
+#if BYTE_ORDER != LITTLE_ENDIAN
+#define BYTE_ORDER LITTLE_ENDIAN
+#endif
+
+/* Types based on stdint.h */
+typedef uint8_t   u8_t;
+typedef int8_t    s8_t;
+typedef uint16_t  u16_t;
+typedef int16_t   s16_t;
+typedef uint32_t  u32_t;
+typedef int32_t   s32_t;
+typedef uintptr_t mem_ptr_t;
+
+/* Define (sn)printf formatters for these lwIP types */
+#define U16_F "hu"
+#define S16_F "hd"
+#define X16_F "hx"
+#define U32_F "u"
+#define S32_F "d"
+#define X32_F "x"
+
+/* Compiler hints for packing lwip's structures */
+#if defined(__CC_ARM)
+/* Setup PACKing macros for MDK Tools */
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+#elif defined(__ICCARM__)
+/* Setup PACKing macros for EWARM Tools */
+#define PACK_STRUCT_BEGIN __packed
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+#elif defined(__GNUC__)
+/* Setup PACKing macros for GCC Tools */
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+#else
+#error "This compiler does not support."
+#endif
+
+/* define LWIP_COMPAT_MUTEX
+    to let sys.h use binary semaphores instead of mutexes - as before in 1.3.2
+    Refer CHANGELOG
+*/
+#define LWIP_COMPAT_MUTEX 1
+
+/* Make lwip/arch.h define the codes which are used throughout */
+#define LWIP_PROVIDE_ERRNO
+
+/* Debug facilities. LWIP_DEBUG must be defined to read output */
+#ifdef LWIP_DEBUG
+#define LWIP_PLATFORM_DIAG(x)                                                                                          \
+	{                                                                                                                  \
+		printf x;                                                                                                      \
+	}
+#define LWIP_PLATFORM_ASSERT(x)                                                                                        \
+	{                                                                                                                  \
+		printf("Assertion \"%s\" failed at line %d in %s\n", x, __LINE__, __FILE__);                                   \
+		while (1)                                                                                                      \
+			;                                                                                                          \
+	}
+#else
+#define LWIP_PLATFORM_DIAG(x)                                                                                          \
+	{                                                                                                                  \
+		;                                                                                                              \
+	}
+#define LWIP_PLATFORM_ASSERT(x)                                                                                        \
+	{                                                                                                                  \
+		while (1)                                                                                                      \
+			;                                                                                                          \
+	}
+#endif
+
+#endif /* CC_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/arch/perf.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/arch/perf.h
new file mode 100644
index 000000000..f0c353858
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/arch/perf.h
@@ -0,0 +1,40 @@
+/**
+ * \file
+ *
+ * \brief lwIP abstraction layer.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef PERF_H_INCLUDED
+#define PERF_H_INCLUDED
+
+#define PERF_START   /* null definition */
+#define PERF_STOP(x) /* null definition */
+
+#endif /* PERF_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/ethernetif.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/ethernetif.c
new file mode 100644
index 000000000..381604064
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/ethernetif.c
@@ -0,0 +1,437 @@
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/**
+    \file ethernetif.c
+    \brief A device driver for the ClearCore to use LwIP.
+**/
+#include "EthernetApi.h"
+
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+
+#include <string.h>
+
+#include "lwip/def.h"
+#if LWIP_IPV6
+#include "lwip/ethip6.h"
+#endif
+#include "lwip/mem.h"
+#include "lwip/netif.h"
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#if LWIP_SNMP
+#include "lwip/snmp.h"
+#endif
+#include "lwip/stats.h"
+#include "netif/etharp.h"
+#include "sam.h"
+
+typedef struct netif netInt;
+typedef struct pbuf packetBuf;
+
+/**
+    \brief Determine the total length of a received packet.
+
+    \param ethernetif   An Ethernet interface reference structure.
+    \return The size of the packet in bytes.
+**/
+uint32_t PacketLength(ethInt *ethernetif) {
+    // Calculated length of the received packet
+    uint32_t length = 0;
+
+    uint8_t sf = 0;
+    uint32_t index;
+
+    // Start at the current RX buffer index.
+    index = *(ethernetif->rxBuffIndex);
+
+    // Find the length of the packet.
+    for (uint32_t i = 0; i < RX_BUFF_CNT; i++) {
+        // The OWN bit indicates software has ownership of this buffer.
+        if (!ethernetif->rxDesc[index].bit.OWN) {
+            break;
+        }
+        // Check for the beginning of the frame.
+        if (ethernetif->rxDesc[index].bit.SF) {
+            sf = 1;
+        }
+        // If the beginning of the frame has been found, sum the length.
+        if (sf == 1) {
+            length += ethernetif->rxDesc[index].bit.LEN;
+        }
+        // Check for the end of the frame.
+        if (ethernetif->rxDesc[index].bit.EF) {
+            break;
+        }
+        // Increment the local index, treating RX buffers as circular.
+        index = (index + 1) % RX_BUFF_CNT;
+    }
+    return length;
+}
+
+/**
+    \brief Copies a frame into a buffer for a packet to be built.
+
+    \param ethernetif   An Ethernet interface reference structure.
+    \param buffer       The destination buffer for the contents of the frame.
+    \param bytesToCopy  The total number of bytes that may be copied into buffer.
+
+    \return The total number of bytes copied.
+**/
+uint32_t PacketRead(ethInt *ethernetif, uint8_t *buffer, uint32_t bytesToCopy) {
+    // Offsets to the SF and EF RX buffers from the current RX index.
+    uint8_t startFrameOffset = RX_BUFF_CNT;
+    uint8_t endFrameOffset = RX_BUFF_CNT;
+    // Count of RX buffers in the frame.
+    uint8_t bufferCount = 0;
+    // Total length of the packet.
+    uint32_t packetLength;
+    // Start at the current RX index.
+    uint8_t index = *(ethernetif->rxBuffIndex);
+
+    // Determine the number of buffers in the frame.
+    for (uint8_t i = 0; i < RX_BUFF_CNT; i++) {
+        // The OWN bit indicates software has ownership of this buffer.
+        if (!ethernetif->rxDesc[index].bit.OWN) {
+            break;
+        }
+        // The SF bit indicates this RX buffer is the first in the frame.
+        if (ethernetif->rxDesc[index].bit.SF) {
+            startFrameOffset = i;
+        }
+        // THE EF bit indicates this RX buffer is the last in the frame.
+        if (ethernetif->rxDesc[index].bit.EF && startFrameOffset != RX_BUFF_CNT) {
+            endFrameOffset = i;
+            packetLength = ethernetif->rxDesc[index].bit.LEN;
+            bytesToCopy = min(packetLength, bytesToCopy);
+            break;
+        }
+        // Increment the local index, treating RX buffers as circular.
+        index = (index + 1) % RX_BUFF_CNT;
+    }
+
+    if (endFrameOffset == RX_BUFF_CNT || startFrameOffset == RX_BUFF_CNT) {
+        return 0; // Failed to find the frame..
+    }
+
+    // Bytes moved into buffer.
+    uint32_t bytesCopied = 0;
+
+    // Move the RX index to be at the start of frame RX buffer.
+    *ethernetif->rxBuffIndex = (*(ethernetif->rxBuffIndex) + startFrameOffset) % RX_BUFF_CNT;
+    // Determine the number of buffers in the frame.
+    bufferCount = endFrameOffset - startFrameOffset + 1;
+    if (endFrameOffset < startFrameOffset) {
+        bufferCount += RX_BUFF_CNT;
+    }
+    // Copy the RX buffer(s) contents into buffer, treating RX buffers as circular.
+    for (uint8_t i = 0; i < bufferCount; i++) {
+        if (bytesToCopy > 0) {
+            uint32_t bytes = min(bytesToCopy, RX_BUFFER_SIZE);
+            // Mask to ignore the lowest 2 bits that are not part of the address.
+            memcpy(buffer, (void *)(ethernetif->rxDesc[*(ethernetif->rxBuffIndex)].reg[0] & 0xFFFFFFFC), bytes);
+            buffer += bytes;
+            bytesCopied += bytes;
+            bytesToCopy -= bytes;
+            // Give ownership of this buffer back to hardware.
+        }
+        ethernetif->rxDesc[*(ethernetif->rxBuffIndex)].bit.OWN = 0;
+        // Increment the buffer index, treating RX buffers as circular.
+        *ethernetif->rxBuffIndex = (*(ethernetif->rxBuffIndex) + 1) % RX_BUFF_CNT;
+    }
+    return bytesCopied;
+}
+
+static err_t PacketWrite(ethInt *ethernetif, uint8_t *buffer, uint32_t length) {
+    uint16_t startIndex = *ethernetif->txBuffIndex;
+    uint16_t endIndex = *ethernetif->txBuffIndex;
+
+    // Check that enough TX buffers are available to fit the entire frame.
+    // Start at the current TX index.
+    uint8_t index = *ethernetif->txBuffIndex;
+    for (uint16_t i = 0; i < TX_BUFF_CNT; i++) {
+        uint8_t tempIndex = (index + i) % TX_BUFF_CNT;
+        // LwIP recommends just waiting for something to be available..
+        while (ethernetif->txDesc[tempIndex].bit.OWN != 1) {
+            continue;
+        }
+        // GMAC only returns the first TX buffer descriptor to ownership
+        // on transmission complete. Reclaim remaining TX buffers.
+        uint8_t buffLb;
+        do {
+            buffLb = ethernetif->txDesc[tempIndex].bit.LB;
+            // Reclaim TX buffers that should belong to software.
+            ethernetif->txDesc[tempIndex].bit.LB = 1;
+            ethernetif->txDesc[tempIndex].bit.OWN = 1;
+            tempIndex = (tempIndex + 1) % TX_BUFF_CNT;
+        } while (buffLb == 0);
+        // Require that one additional buffer always remain available/empty.
+        if (length < TX_BUFFER_SIZE * i) {
+            break;
+        }
+    }
+
+    // Write into the transmit buffer(s).
+    for (uint32_t i = 0; i < TX_BUFF_CNT; i++) {
+        uint32_t bufferLength = min(length, TX_BUFFER_SIZE);
+        memcpy((void *)(ethernetif->txDesc[*ethernetif->txBuffIndex].reg[0]),
+               buffer + (i * TX_BUFFER_SIZE), bufferLength);
+        length -= bufferLength;
+
+        // Clear all fields except OWN or WRAP.
+        ethernetif->txDesc[*ethernetif->txBuffIndex].reg[1] &= (0xC0000000);
+        // Set only LEN.
+        ethernetif->txDesc[*ethernetif->txBuffIndex].bit.LEN = bufferLength;
+
+        if (length <= 0) {
+            // Indicate last buffer of this frame.
+            ethernetif->txDesc[*ethernetif->txBuffIndex].bit.LB = 1;
+            endIndex = *ethernetif->txBuffIndex;
+        }
+
+        // Increment the TX buffer index.
+        *ethernetif->txBuffIndex = (*ethernetif->txBuffIndex + 1) % TX_BUFF_CNT;
+
+        if (length <= 0) {
+            break;
+        }
+    }
+
+    // Pass the transmit buffers for this frame to the GMAC.
+    for (uint32_t i = endIndex; i != startIndex; i = (i + TX_BUFF_CNT - 1) % TX_BUFF_CNT) {
+        ethernetif->txDesc[i].bit.OWN = 0;
+    }
+    // Final hand-off to the GMAC.
+    ethernetif->txDesc[startIndex].bit.OWN = 0;
+
+    // Activate the transmit.
+    GMAC->NCR.bit.TSTART = 1;
+
+    return ERR_OK;
+}
+
+/**
+    In this function, the hardware should be initialized.
+    Called from ethernetif_init().
+
+    @param netif the already initialized lwip network interface structure
+        for this ethernetif
+**/
+static void low_level_init(netInt *netif) {
+    // Setup MAC address & TIDM
+    // Specific Address Bottom stores the first four bytes.
+    memcpy((void *)&GMAC->Sa[0].SAB.reg, netif->hwaddr, 4);
+    // Specific Address Top stores the last two bytes.
+    memcpy((void *)&GMAC->Sa[0].SAT.reg, netif->hwaddr + 4, 2);
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+  // May need to implement something here if we are using MAC filtering.
+#endif
+
+}
+
+/**
+    This function should do the actual transmission of the packet. The packet is
+    contained in the pbuf that is passed to the function. This pbuf
+    might be chained.
+
+    @param netif the lwip network interface structure for this ethernetif
+    @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+    @return ERR_OK if the packet could be sent
+        an err_t value if the packet couldn't be sent
+
+    @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+        strange results. You might consider waiting for space in the DMA queue
+        to become available since the stack doesn't retry to send a packet
+        dropped because of memory failure (except for the TCP timers).
+**/
+static err_t low_level_output(netInt *netif, packetBuf *p) {
+    ethInt *ethernetif;
+    packetBuf *q;
+    void * tempBuffer;
+    uint8_t * index;
+    err_t err;
+    ethernetif = (ethInt *)(netif->state);
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE); // Drop the padding word.
+#endif
+
+    if (p->tot_len == p->len) {
+        err = PacketWrite(ethernetif, (uint8_t *)p->payload, p->tot_len);
+    }
+    else {
+        tempBuffer = mem_malloc(LWIP_MEM_ALIGN_SIZE(p->tot_len));
+        index = (uint8_t *)tempBuffer;
+        if (tempBuffer == NULL) {
+            return ERR_MEM; // Allocation error.
+        }
+        for (q = p; q != NULL; q = q->next) {
+            memcpy(index, q->payload, q->len);
+            index += q->len;
+        }
+        err = PacketWrite(ethernetif, (uint8_t *)tempBuffer, p->tot_len);
+        mem_free(tempBuffer);
+    }
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE); // Reclaim the padding word.
+#endif
+
+    LINK_STATS_INC(link.xmit);
+    return err;
+}
+
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-function"
+/**
+    Should allocate a pbuf and transfer the bytes of the incoming
+    packet from the interface into the pbuf.
+
+    @param netif the lwip network interface structure for this ethernetif
+    @return a pbuf filled with the received packet (including MAC header)
+        NULL on memory error
+**/
+static packetBuf *low_level_input(netInt *netif) {
+    ethInt *ethernetif;
+    packetBuf *p;
+    uint32_t length;
+    ethernetif = (ethInt *)netif->state;
+
+    // Obtain the size of the packet.
+    length = PacketLength(ethernetif);
+
+    if (length == 0) {
+        return NULL;
+    }
+
+    // Allow room for Ethernet padding.
+#if ETH_PAD_SIZE
+    length += ETH_PAD_SIZE;
+#endif
+
+    // Allocate a packet buffer.
+    p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
+
+    if (p != NULL) {
+#if ETH_PAD_SIZE
+        pbuf_header(p, -ETH_PAD_SIZE); // Drop the padding word.
+#endif
+        // read the packet into the buffer
+        PacketRead(ethernetif, (uint8_t*)p->payload, p->len);
+
+#if ETH_PAD_SIZE
+        pbuf_header(p, ETH_PAD_SIZE); // Reclaim the padding word.
+#endif
+
+        LINK_STATS_INC(link.recv);
+    } 
+    else { // P == NULL
+        PacketRead(ethernetif, NULL, 0);
+        LINK_STATS_INC(link.memerr);
+        LINK_STATS_INC(link.drop);
+    }
+    return p;
+}
+
+/**
+    This function should be called when a packet is ready to be read
+    from the interface. Then the type of the received packet is determined and
+    the appropriate input function is called.
+
+    @param netif the lwip network interface structure for this ethernetif
+**/
+static void ethernetif_input(netInt *netif, packetBuf *p) {
+    u16_t packetType;
+    // Determine packet type from payload's Ethernet header.
+    packetType = htons(((struct eth_hdr *)p->payload)->type);
+    switch (packetType) {
+        case ETHTYPE_ARP:   // Address resolution protocol
+        // fall through
+        case ETHTYPE_IP:    //  Internet protocol v4
+            if (netif->input(p, netif) == ERR_OK) {
+                break;
+            }
+            // Otherwise fall through to default of freeing pbuf.
+            LWIP_DEBUGF(NETIF_DEBUG, ("IP input error.."));
+            // fall through
+        default:
+            pbuf_free(p);
+            p = NULL;
+            break;
+    }
+}
+#pragma GCC diagnostic push
+
+/**
+    Should be called at the beginning of the program to set up the
+    network interface. It calls the function low_level_init() to do the
+    actual setup of the hardware.
+
+    This function should be passed as a parameter to netif_add().
+
+    @param netif the lwip network interface structure for this ethernetif
+    @return ERR_OK if the loopif is initialized
+        ERR_MEM if private data couldn't be allocated
+        any other err_t on error
+ */
+err_t ethernetif_init(netInt *netif) {
+    netif->output = etharp_output;
+    netif->linkoutput = low_level_output;
+
+    // flags to set device capabilities
+    netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP |
+                   NETIF_FLAG_ETHERNET;
+    // maximum transfer unit
+    netif->mtu = 1536;
+
+    // MAC address
+    ethInt* ethernetif;
+
+    ethernetif = (ethInt *) netif->state;
+    netif->hwaddr_len = NETIF_MAX_HWADDR_LEN;
+    memcpy(netif->hwaddr, ethernetif->mac, NETIF_MAX_HWADDR_LEN);
+
+    // interface hostname (?)
+
+    // descriptive name (only allows len 2)
+    netif->name[0] = 'T';
+    netif->name[1] = 'C';
+
+    low_level_init(netif);
+
+    return ERR_OK;
+
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/lwipopts.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/lwipopts.h
new file mode 100644
index 000000000..7a9fa23aa
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/port/include/lwipopts.h
@@ -0,0 +1,789 @@
+/* Auto-generated config file lwipopts.h */
+#ifndef LWIPOPTS_H
+#define LWIPOPTS_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Configuration
+
+// <q> Enable DHCP
+// <id> lwip_dhcp
+#ifndef LWIP_DHCP
+#define LWIP_DHCP 1
+#endif
+
+// <q> NO RTOS
+// <id> lwip_no_sys
+#ifndef NO_SYS
+#define NO_SYS 1
+#endif
+
+// <o> The size of the heap memory <0-100000>
+// <i> Defines size of the heap memory
+// <i> Default: 4096
+// <id> lwip_mem_size
+#ifndef MEM_SIZE
+#define MEM_SIZE 4096
+#endif
+
+// <q> Enables TCP
+// <id> lwip_tcp
+#ifndef LWIP_TCP
+#define LWIP_TCP 1
+#endif
+
+// <q> Enables UDP
+// <id> lwip_udp
+#ifndef LWIP_UDP
+#define LWIP_UDP 1
+#endif
+
+// <q> Enables ICMP
+// <id> lwip_icmp
+#ifndef LWIP_ICMP
+#define LWIP_ICMP 1
+#endif
+
+// <q> Enables AUTOIP
+// <id> lwip_autoip
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP 1
+#endif
+
+// <q> Enables SNMP
+// <id> lwip_snmp
+#ifndef LWIP_SNMP
+#define LWIP_SNMP 0
+#endif
+
+// <q> Enables IGMP
+// <id> lwip_igmp
+#ifndef LWIP_IGMP
+#define LWIP_IGMP 0
+#endif
+
+// <q> Enables SLIP interface
+// <id> lwip_have_slipif
+#ifndef LWIP_HAVE_SLIPIF
+#define LWIP_HAVE_SLIPIF 0
+#endif
+
+// <q> Enables DNS
+// <id> lwip_dns
+#ifndef LWIP_DNS
+#define LWIP_DNS 1
+#endif
+// <q> Enable PPP
+// <id> lwip_ppp_support
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT 0
+#endif
+
+// <q> Enable PPPoE
+// <id> lwip_pppoe_support
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT 0
+#endif
+
+// <q> Enable PPPoS
+// <id> lwip_pppos_support
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT 0
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> lwip_advanced_config
+#ifndef LWIP_ADVANCED_CONFIG
+#define LWIP_ADVANCED_CONFIG 0
+#endif
+
+// <o> TCP Maximum segment size<0-100000>
+// <i> TCP_MSS
+// <i> Default: 1460
+// <id> lwip_tcp_mss
+#ifndef TCP_MSS
+#define TCP_MSS 1460
+#endif
+
+// <o> The size of a TCP window<0-100000>
+// <i> multiple of TCP_MSS
+// <i> Default: 4
+// <id> lwip_tcp_wnd_mul
+#ifndef TCP_WND_MUL
+#define TCP_WND_MUL 4
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND (TCP_WND_MUL * TCP_MSS)
+#endif
+
+// <o> TCP sender buffer space (bytes)<0-100000>
+// <i> multiple of TCP_MSS
+// <i> Default: 2
+// <id> lwip_tcp_snd_buf_mul
+#ifndef TCP_SND_BUF_MUL
+#define TCP_SND_BUF_MUL 2
+#endif
+
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF (TCP_SND_BUF_MUL * TCP_MSS)
+#endif
+
+// <o> The number of simultaneously active TCP connections<0-1000>
+// <i> The number of simultaneously active TCP connections
+// <i> Default: 5
+// <id> lwip_memp_num_tcp_pcb
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB 5
+#endif
+
+// <o> the number of listening TCP connections<0-1000>
+// <i> the number of listening TCP connections
+// <i> Default: 8
+// <id> lwip_memp_num_tcp_pcb_listen
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+#endif
+
+// <o> the number of simultaneously queued TCP segments<0-1000>
+// <i> the number of simultaneously queued TCP segments
+// <i> Default: 16
+// <id> lwip_memp_num_tcp_seg
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG 16
+#endif
+
+// <o> Number of bytes added before the ethernet header CPU<0-100000>
+// <i> Ensure alignment of payload after that header
+// <i> Default:  2 can speed up 32-bit-platforms
+// <id> lwip_eth_pad_size
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+// <o> Memory alignment(Byte) of the CPU<0-8>
+// <i> Memory alignment(Byte)
+// <i> Default: 4 byte alignment
+// <id> lwip_mem_alignment
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT 4
+#endif
+
+// <q> Enables application layer to hook into the IP layer itself
+// <id> lwip_raw
+#ifndef LWIP_RAW
+#define LWIP_RAW 1
+#endif
+
+// <q> Enable interface up/down status callback
+// <id> lwip_netif_status_callback
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#endif
+
+// <q> Support callback when a netif is removed
+// <id> lwip_netif_remove_callback
+#ifndef LWIP_NETIF_REMOVE_CALLBACK
+#define LWIP_NETIF_REMOVE_CALLBACK 0
+#endif
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+// <q> Enable inter-task protection for certain critical regions during buffer/memory allocation etc.
+// <id> lwip_sys_lightweight_prot
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT 0
+#endif
+
+// <q> Enables Netconn API(not available when using "NO_SYS")
+// <id> lwip_netconn
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN 0
+#endif
+
+// <q> Enables TCP/IP timeout
+// <id> lwip_tcpip_timeout
+#ifndef LWIP_TCPIP_TIMEOUT
+#define LWIP_TCPIP_TIMEOUT 0
+#endif
+
+// <q> Enables Socket functions(not available when using "NO_SYS")
+// <id> lwip_socket
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET 0
+#endif
+
+// <q> Enables BSD-style sockets functions(not available when using "NO_SYS")
+// <id> lwip_compat_sockets
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS 0
+#endif
+
+// <q> Enables the ability to forward IP packets
+// <id> lwip_ip_forward
+#ifndef IP_FORWARD
+#define IP_FORWARD 0
+#endif
+
+// <o> Value for Time-To-Live used by transport layers<0-255>
+// <i> IP TTL
+// <i> Default: 255
+// <id> lwip_ip_default_ttl
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL 255
+#endif
+
+// <o> the number of IP packets simultaneously queued<0-1000>
+// <i> the number of IP packets simultaneously queued
+// <i> Default: 5
+// <id> lwip_memp_num_reassdata
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA 5
+#endif
+
+// <o> the number of IP fragments simultaneously sent<0-1000>
+// <i> the number of IP fragments simultaneously sent
+// <i> Default: 15
+// <id> lwip_memp_num_frag_pbuf
+#ifndef MEMP_NUM_FRAG_PBUF
+#define MEMP_NUM_FRAG_PBUF 15
+#endif
+
+// <o> the number of simultaneously queued outgoing packets<0-1000>
+// <i> Pbuf
+// <i> Default: 30
+// <id> lwip_memp_num_arp_queue
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE 30
+#endif
+
+// <o> the number of struct netbufs<0-1000>
+// <i> the number of struct netbufs
+// <i> Default: 2
+// <id> lwip_memp_num_netbuf
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF 2
+#endif
+
+// <o> the number of struct netconns<0-1000>
+// <i> the number of struct netconns
+// <i> Default: 4
+// <id> lwip_memp_num_netconn
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN 4
+#endif
+
+// <o> the number of buffers in the pbuf pool<0-1000>
+// <i> the number of buffers in the pbuf pool
+// <i> Default: 16
+// <id> lwip_pbuf_pool_size
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE 16
+#endif
+
+// <o> the number of bytes that should be allocated for a link level header<0-1000>
+// <i> The default is 14, the standard value for Ethernet.
+// <i> Default: 14
+// <id> lwip_pbuf_link_hlen_s
+#ifndef PBUF_LINK_HLEN_S
+#define PBUF_LINK_HLEN_S 14
+#endif
+
+#define PBUF_LINK_HLEN (PBUF_LINK_HLEN_S + ETH_PAD_SIZE)
+
+// <o> Extra size of each pbuf in the pbuf pool<0-1000>
+// <i> The default is designed to accommodate single full size TCP frame in one pbuf.
+// <i> It will include TCP_MSS, IP header, and link header, plus an extra word
+// <id> lwip_pbuf_pool_bufsize_added
+#ifndef PBUF_POOL_BUFSIZE_ADDED
+#define PBUF_POOL_BUFSIZE_ADDED 0
+#endif
+
+#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS + 40 + PBUF_LINK_HLEN + PBUF_POOL_BUFSIZE_ADDED)
+
+// <o> the number of multicast groups<0-1000>
+// <i> the number of multicast groups
+// <i> Default: 8
+// <id> lwip_memp_num_igmp_group
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP 8
+#endif
+
+// <q> Using malloc C-library function instead of the lwip internal allocator
+// <id> lwip_mem_libc_malloc
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC 0
+#endif
+
+// <q> Using mem_malloc function instead of the lwip internal allocator
+// <id> lwip_memp_mem_malloc
+#ifndef MEMP_MEM_MALLOC
+#define MEMP_MEM_MALLOC 0
+#endif
+
+// <o> The stack size used by the main tcpip thread<0-10000>
+// <i> It is passed to sys_thread_new() when the thread is created.
+// <i> The stack size value itself is platform-dependent
+// <id> lwip_tcpip_thread_stacksize
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE 256
+#endif
+
+// <o> The priority assigned to the main tcpip thread<0-1000>
+// <i> It is passed to sys_thread_new() when the thread is created.
+// <i> The priority value itself is platform-dependent
+// <id> lwip_tcpip_thread_prio
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO 1
+#endif
+
+// <o> The mailbox size for the tcpip thread messages<0-1000>
+// <i> It is passed to sys_mbox_new() when tcpip_init is called.
+// <i> The queue size value itself is platform-dependent
+// <id> lwip_tcpip_mbox_size
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE 16
+#endif
+// <o> The mailbox size for the incoming packets on a NETCONN_RAW<0-100000>
+// <i> It is passed to sys_mbox_new() when tcpip_init is called.
+// <i> The queue size value itself is platform-dependent
+// <id> lwip_default_raw_recvmbox_size
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE 16
+#endif
+
+// <o> The mailbox size for the incoming packets on a NETCONN_UDP<0-100000>
+// <i> It is passed to sys_mbox_new() when tcpip_init is called.
+// <i> The queue size value itself is platform-dependent
+// <id> lwip_default_udp_recvmbox_size
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE 16
+#endif
+
+// <o> The mailbox size for the incoming packets on a NETCONN_TCP<0-1000>
+// <i> It is passed to sys_mbox_new() when tcpip_init is called.
+// <i> The queue size value itself is platform-dependent
+// <id> lwip_default_tcp_recvmbox_size
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE 16
+#endif
+
+// <o> The mailbox size for  the incoming connections<0-1000>
+// <i> It is passed to sys_mbox_new() when tcpip_init is called.
+// <i> The queue size value itself is platform-dependent
+// <id> lwip_default_acceptmbox_size
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE 16
+#endif
+
+// <q> Enables loop interface (127.0.0.1)
+// <id> lwip_loopif
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF 0
+#endif
+
+// <q> Enables statistics collection in lwip_stats
+// <id> lwip_stats
+#ifndef LWIP_STATS
+#define LWIP_STATS 0
+#endif
+
+// <q> Compile in the statistics output functions
+// <id> lwip_stats_display
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+// <q> Compile in the statistics output functions
+// <id> lwip_link_stats
+#ifndef LINK_STATS
+#define LINK_STATS 0
+#endif
+
+// <q> Enable etharp stats
+// <id> lwip_etharp_stats
+#ifndef ETHARP_STATS
+#define ETHARP_STATS 0
+#endif
+
+// <q> Enable IP stats
+// <id> lwip_ip_stats
+#ifndef IP_STATS
+#define IP_STATS 0
+#endif
+
+// <q> Enable IP fragmentation stats
+// <id> lwip_ipfrag_stats
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS 0
+#endif
+
+// <q> Enable ICMP stats
+// <id> lwip_icmp_stats
+#ifndef ICMP_STATS
+#define ICMP_STATS 0
+#endif
+
+// <q> Enable IGMP stats
+// <id> lwip_igmp_stats
+#ifndef IGMP_STATS
+#define IGMP_STATS 0
+#endif
+
+// <q> Enable UDP stats
+// <id> lwip_udp_stats
+#ifndef UDP_STATS
+#define UDP_STATS 0
+#endif
+
+// <q> Enable TCP stats
+// <id> lwip_tcp_stats
+#ifndef TCP_STATS
+#define TCP_STATS 0
+#endif
+
+// <q> Enable memp.c stats
+// <id> lwip_memp_stats
+#ifndef MEMP_STATS
+#define MEMP_STATS 0
+#endif
+
+// <q> Enable system stats
+// <id> lwip_sys_stats
+#ifndef SYS_STATS
+#define SYS_STATS 0
+#endif
+
+// <q> Disable LwIP Assert
+// <id> lwip_assert
+#ifndef LWIP_NOASSERT
+#define LWIP_NOASSERT 0
+#endif
+
+// <y> Debug level
+//    <LWIP_DBG_LEVEL_ALL"> All
+//    <LWIP_DBG_LEVEL_WARNING"> warning
+//    <LWIP_DBG_LEVEL_SERIOUS"> serious
+//    <LWIP_DBG_LEVEL_SEVERE"> severe
+// <i> Default LWIP_DBG_LEVEL_ALL
+// <id> lwip_dbg_min_level
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL
+#endif
+
+// <y> ARP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_etharp_debug
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> Netif Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_netif_debug
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> Pbuf Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_api_lib_debug
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> Pbuf Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_pbuf_debug
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> API message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_api_msg_debug
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> Socket Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_sockets_debug
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> ICMP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_icmp_debug
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> IGMP message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_igmp_debug
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> INET message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_inet_debug
+#ifndef INET_DEBUG
+#define INET_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> IP Frag message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_ip_reass_debug
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> IP message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_ip_debug
+#ifndef IP_DEBUG
+#define IP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> RAW message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_raw_debug
+#ifndef RAW_DEBUG
+#define RAW_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> MEM message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_mem_debug
+#ifndef MEM_DEBUG
+#define MEM_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> MEMP message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_memp_debug
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> System message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_sys_debug
+#ifndef SYS_DEBUG
+#define SYS_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> Timer message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_timers_debug
+#ifndef TIMERS_DEBUG
+#define TIMERS_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP message Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_debug
+#ifndef TCP_DEBUG
+#define TCP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP input Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_input_debug
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP in for fast retransmit Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_fr_debug
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP for retransmit Debug option
+//     <LWIP_DBG_ON"> Enable debug message
+//     <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_rto_debug
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP congestion window Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_cwnd_debug
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP window updating Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_wnd_debug
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP out Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_output_debug
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP RST Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_rst_debug
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP queue lengths Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcp_qlen_debug
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> UDP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_udp_debug
+#ifndef UDP_DEBUG
+#define UDP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> TCP/ip Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_tcpip_debug
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> PPP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_ppp_debug
+#ifndef PPP_DEBUG
+#define PPP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> SLIP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_slip_debug
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> DHCP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_dhcp_debug
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> AUTOIP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_autoip_debug
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> SNMP Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_snmp_msg_debug
+#ifndef SNMP_MSG_DEBUG
+#define SNMP_MSG_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> SNMP MIBs Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_snmp_mib_debug
+#ifndef SNMP_MIB_DEBUG
+#define SNMP_MIB_DEBUG LWIP_DBG_OFF
+#endif
+
+// <y> DNS Debug option
+//    <LWIP_DBG_ON"> Enable debug message
+//    <LWIP_DBG_OFF"> Disable debug message
+// <i> Default LWIP_DBG_OFF
+// <id> lwip_dns_debug
+#ifndef DNS_DEBUG
+#define DNS_DEBUG LWIP_DBG_OFF
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // LWIPOPTS_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/api_lib.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/api_lib.c
new file mode 100644
index 000000000..b0e1fb16b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/api_lib.c
@@ -0,0 +1,1367 @@
+/**
+ * @file
+ * Sequential API External module
+ *
+ * @defgroup netconn Netconn API
+ * @ingroup sequential_api
+ * Thread-safe, to be called from non-TCPIP threads only.
+ * TX/RX handling based on @ref netbuf (containing @ref pbuf)
+ * to avoid copying data around.
+ *
+ * @defgroup netconn_common Common functions
+ * @ingroup netconn
+ * For use with TCP and UDP
+ *
+ * @defgroup netconn_tcp TCP only
+ * @ingroup netconn
+ * TCP only functions
+ *
+ * @defgroup netconn_udp UDP only
+ * @ingroup netconn
+ * UDP only functions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/api.h"
+#include "lwip/memp.h"
+
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/priv/api_msg.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+#include <string.h>
+
+#define API_MSG_VAR_REF(name)               API_VAR_REF(name)
+#define API_MSG_VAR_DECLARE(name)           API_VAR_DECLARE(struct api_msg, name)
+#define API_MSG_VAR_ALLOC(name)             API_VAR_ALLOC(struct api_msg, MEMP_API_MSG, name, ERR_MEM)
+#define API_MSG_VAR_ALLOC_RETURN_NULL(name) API_VAR_ALLOC(struct api_msg, MEMP_API_MSG, name, NULL)
+#define API_MSG_VAR_FREE(name)              API_VAR_FREE(MEMP_API_MSG, name)
+
+#if TCP_LISTEN_BACKLOG
+/* need to allocate API message for accept so empty message pool does not result in event loss
+ * see bug #47512: MPU_COMPATIBLE may fail on empty pool */
+#define API_MSG_VAR_ALLOC_ACCEPT(msg) API_MSG_VAR_ALLOC(msg)
+#define API_MSG_VAR_FREE_ACCEPT(msg) API_MSG_VAR_FREE(msg)
+#else /* TCP_LISTEN_BACKLOG */
+#define API_MSG_VAR_ALLOC_ACCEPT(msg)
+#define API_MSG_VAR_FREE_ACCEPT(msg)
+#endif /* TCP_LISTEN_BACKLOG */
+
+#if LWIP_NETCONN_FULLDUPLEX
+#define NETCONN_RECVMBOX_WAITABLE(conn) (sys_mbox_valid(&(conn)->recvmbox) && (((conn)->flags & NETCONN_FLAG_MBOXINVALID) == 0))
+#define NETCONN_ACCEPTMBOX_WAITABLE(conn) (sys_mbox_valid(&(conn)->acceptmbox) && (((conn)->flags & (NETCONN_FLAG_MBOXCLOSED|NETCONN_FLAG_MBOXINVALID)) == 0))
+#define NETCONN_MBOX_WAITING_INC(conn) SYS_ARCH_INC(conn->mbox_threads_waiting, 1)
+#define NETCONN_MBOX_WAITING_DEC(conn) SYS_ARCH_DEC(conn->mbox_threads_waiting, 1)
+#else /* LWIP_NETCONN_FULLDUPLEX */
+#define NETCONN_RECVMBOX_WAITABLE(conn)   sys_mbox_valid(&(conn)->recvmbox)
+#define NETCONN_ACCEPTMBOX_WAITABLE(conn) (sys_mbox_valid(&(conn)->acceptmbox) && (((conn)->flags & NETCONN_FLAG_MBOXCLOSED) == 0))
+#define NETCONN_MBOX_WAITING_INC(conn)
+#define NETCONN_MBOX_WAITING_DEC(conn)
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+static err_t netconn_close_shutdown(struct netconn *conn, u8_t how);
+
+/**
+ * Call the lower part of a netconn_* function
+ * This function is then running in the thread context
+ * of tcpip_thread and has exclusive access to lwIP core code.
+ *
+ * @param fn function to call
+ * @param apimsg a struct containing the function to call and its parameters
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+static err_t
+netconn_apimsg(tcpip_callback_fn fn, struct api_msg *apimsg)
+{
+  err_t err;
+
+#ifdef LWIP_DEBUG
+  /* catch functions that don't set err */
+  apimsg->err = ERR_VAL;
+#endif /* LWIP_DEBUG */
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+  apimsg->op_completed_sem = LWIP_NETCONN_THREAD_SEM_GET();
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+  err = tcpip_send_msg_wait_sem(fn, apimsg, LWIP_API_MSG_SEM(apimsg));
+  if (err == ERR_OK) {
+    return apimsg->err;
+  }
+  return err;
+}
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is also created.
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param proto the IP protocol for RAW IP pcbs
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn *
+netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback)
+{
+  struct netconn *conn;
+  API_MSG_VAR_DECLARE(msg);
+  API_MSG_VAR_ALLOC_RETURN_NULL(msg);
+
+  conn = netconn_alloc(t, callback);
+  if (conn != NULL) {
+    err_t err;
+
+    API_MSG_VAR_REF(msg).msg.n.proto = proto;
+    API_MSG_VAR_REF(msg).conn = conn;
+    err = netconn_apimsg(lwip_netconn_do_newconn, &API_MSG_VAR_REF(msg));
+    if (err != ERR_OK) {
+      LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL);
+      LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox));
+#if LWIP_TCP
+      LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox));
+#endif /* LWIP_TCP */
+#if !LWIP_NETCONN_SEM_PER_THREAD
+      LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed));
+      sys_sem_free(&conn->op_completed);
+#endif /* !LWIP_NETCONN_SEM_PER_THREAD */
+      sys_mbox_free(&conn->recvmbox);
+      memp_free(MEMP_NETCONN, conn);
+      API_MSG_VAR_FREE(msg);
+      return NULL;
+    }
+  }
+  API_MSG_VAR_FREE(msg);
+  return conn;
+}
+
+/**
+ * @ingroup netconn_common
+ * Close a netconn 'connection' and free all its resources but not the netconn itself.
+ * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate
+ * after this returns.
+ *
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_prepare_delete(struct netconn *conn)
+{
+  err_t err;
+  API_MSG_VAR_DECLARE(msg);
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+  /* get the time we started, which is later compared to
+     Milliseconds() + conn->send_timeout */
+  API_MSG_VAR_REF(msg).msg.sd.time_started = Milliseconds();
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+#if LWIP_TCP
+  API_MSG_VAR_REF(msg).msg.sd.polls_left =
+    ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1;
+#endif /* LWIP_TCP */
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+  err = netconn_apimsg(lwip_netconn_do_delconn, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  if (err != ERR_OK) {
+    return err;
+  }
+  return ERR_OK;
+}
+
+/**
+ * @ingroup netconn_common
+ * Close a netconn 'connection' and free its resources.
+ * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate
+ * after this returns.
+ *
+ * @param conn the netconn to delete
+ * @return ERR_OK if the connection was deleted
+ */
+err_t
+netconn_delete(struct netconn *conn)
+{
+  err_t err;
+
+  /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+
+#if LWIP_NETCONN_FULLDUPLEX
+  if (conn->flags & NETCONN_FLAG_MBOXINVALID) {
+    /* Already called netconn_prepare_delete() before */
+    err = ERR_OK;
+  } else
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+  {
+    err = netconn_prepare_delete(conn);
+  }
+  if (err == ERR_OK) {
+    netconn_free(conn);
+  }
+  return err;
+}
+
+/**
+ * Get the local or remote IP address and port of a netconn.
+ * For RAW netconns, this returns the protocol instead of a port!
+ *
+ * @param conn the netconn to query
+ * @param addr a pointer to which to save the IP address
+ * @param port a pointer to which to save the port (or protocol for RAW)
+ * @param local 1 to get the local IP address, 0 to get the remote one
+ * @return ERR_CONN for invalid connections
+ *         ERR_OK if the information was retrieved
+ */
+err_t
+netconn_getaddr(struct netconn *conn, ip_addr_t *addr, u16_t *port, u8_t local)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.ad.local = local;
+#if LWIP_MPU_COMPATIBLE
+  err = netconn_apimsg(lwip_netconn_do_getaddr, &API_MSG_VAR_REF(msg));
+  *addr = msg->msg.ad.ipaddr;
+  *port = msg->msg.ad.port;
+#else /* LWIP_MPU_COMPATIBLE */
+  msg.msg.ad.ipaddr = addr;
+  msg.msg.ad.port = port;
+  err = netconn_apimsg(lwip_netconn_do_getaddr, &msg);
+#endif /* LWIP_MPU_COMPATIBLE */
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_common
+ * Bind a netconn to a specific local IP address and port.
+ * Binding one netconn twice might not always be checked correctly!
+ *
+ * @param conn the netconn to bind
+ * @param addr the local IP address to bind the netconn to
+ *             (use IP4_ADDR_ANY/IP6_ADDR_ANY to bind to all addresses)
+ * @param port the local port to bind the netconn to (not used for RAW)
+ * @return ERR_OK if bound, any other err_t on failure
+ */
+err_t
+netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;);
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */
+  if (addr == NULL) {
+    addr = IP4_ADDR_ANY;
+  }
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV4 && LWIP_IPV6
+  /* "Socket API like" dual-stack support: If IP to bind to is IP6_ADDR_ANY,
+   * and NETCONN_FLAG_IPV6_V6ONLY is 0, use IP_ANY_TYPE to bind
+   */
+  if ((netconn_get_ipv6only(conn) == 0) &&
+      ip_addr_cmp(addr, IP6_ADDR_ANY)) {
+    addr = IP_ANY_TYPE;
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr);
+  API_MSG_VAR_REF(msg).msg.bc.port = port;
+  err = netconn_apimsg(lwip_netconn_do_bind, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_common
+ * Bind a netconn to a specific interface and port.
+ * Binding one netconn twice might not always be checked correctly!
+ *
+ * @param conn the netconn to bind
+ * @param if_idx the local interface index to bind the netconn to
+ * @return ERR_OK if bound, any other err_t on failure
+ */
+err_t
+netconn_bind_if(struct netconn *conn, u8_t if_idx)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_bind_if: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.bc.if_idx = if_idx;
+  err = netconn_apimsg(lwip_netconn_do_bind_if, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_common
+ * Connect a netconn to a specific remote IP address and port.
+ *
+ * @param conn the netconn to connect
+ * @param addr the remote IP address to connect to
+ * @param port the remote port to connect to (no used for RAW)
+ * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise
+ */
+err_t
+netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */
+  if (addr == NULL) {
+    addr = IP4_ADDR_ANY;
+  }
+#endif /* LWIP_IPV4 */
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr);
+  API_MSG_VAR_REF(msg).msg.bc.port = port;
+  err = netconn_apimsg(lwip_netconn_do_connect, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_udp
+ * Disconnect a netconn from its current peer (only valid for UDP netconns).
+ *
+ * @param conn the netconn to disconnect
+ * @return See @ref err_t
+ */
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+  err = netconn_apimsg(lwip_netconn_do_disconnect, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Set a TCP netconn into listen mode
+ *
+ * @param conn the tcp netconn to set to listen mode
+ * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1
+ * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns
+ *         don't return any error (yet?))
+ */
+err_t
+netconn_listen_with_backlog(struct netconn *conn, u8_t backlog)
+{
+#if LWIP_TCP
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */
+  LWIP_UNUSED_ARG(backlog);
+
+  LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+#if TCP_LISTEN_BACKLOG
+  API_MSG_VAR_REF(msg).msg.lb.backlog = backlog;
+#endif /* TCP_LISTEN_BACKLOG */
+  err = netconn_apimsg(lwip_netconn_do_listen, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+#else /* LWIP_TCP */
+  LWIP_UNUSED_ARG(conn);
+  LWIP_UNUSED_ARG(backlog);
+  return ERR_ARG;
+#endif /* LWIP_TCP */
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Accept a new connection on a TCP listening netconn.
+ *
+ * @param conn the TCP listen netconn
+ * @param new_conn pointer where the new connection is stored
+ * @return ERR_OK if a new connection has been received or an error
+ *                code otherwise
+ */
+err_t
+netconn_accept(struct netconn *conn, struct netconn **new_conn)
+{
+#if LWIP_TCP
+  err_t err;
+  void *accept_ptr;
+  struct netconn *newconn;
+#if TCP_LISTEN_BACKLOG
+  API_MSG_VAR_DECLARE(msg);
+#endif /* TCP_LISTEN_BACKLOG */
+
+  LWIP_ERROR("netconn_accept: invalid pointer",    (new_conn != NULL),                  return ERR_ARG;);
+  *new_conn = NULL;
+  LWIP_ERROR("netconn_accept: invalid conn",       (conn != NULL),                      return ERR_ARG;);
+
+  /* NOTE: Although the opengroup spec says a pending error shall be returned to
+           send/recv/getsockopt(SO_ERROR) only, we return it for listening
+           connections also, to handle embedded-system errors */
+  err = netconn_err(conn);
+  if (err != ERR_OK) {
+    /* return pending error */
+    return err;
+  }
+  if (!NETCONN_ACCEPTMBOX_WAITABLE(conn)) {
+    /* don't accept if closed: this might block the application task
+       waiting on acceptmbox forever! */
+    return ERR_CLSD;
+  }
+
+  API_MSG_VAR_ALLOC_ACCEPT(msg);
+
+  NETCONN_MBOX_WAITING_INC(conn);
+  if (netconn_is_nonblocking(conn)) {
+    if (sys_arch_mbox_tryfetch(&conn->acceptmbox, &accept_ptr) == SYS_ARCH_TIMEOUT) {
+      API_MSG_VAR_FREE_ACCEPT(msg);
+      NETCONN_MBOX_WAITING_DEC(conn);
+      return ERR_WOULDBLOCK;
+    }
+  } else {
+#if LWIP_SO_RCVTIMEO
+    if (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+      API_MSG_VAR_FREE_ACCEPT(msg);
+      NETCONN_MBOX_WAITING_DEC(conn);
+      return ERR_TIMEOUT;
+    }
+#else
+    sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+  }
+  NETCONN_MBOX_WAITING_DEC(conn);
+#if LWIP_NETCONN_FULLDUPLEX
+  if (conn->flags & NETCONN_FLAG_MBOXINVALID) {
+    if (lwip_netconn_is_deallocated_msg(accept_ptr)) {
+      /* the netconn has been closed from another thread */
+      API_MSG_VAR_FREE_ACCEPT(msg);
+      return ERR_CONN;
+    }
+  }
+#endif
+
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+
+  if (lwip_netconn_is_err_msg(accept_ptr, &err)) {
+    /* a connection has been aborted: e.g. out of pcbs or out of netconns during accept */
+    API_MSG_VAR_FREE_ACCEPT(msg);
+    return err;
+  }
+  if (accept_ptr == NULL) {
+    /* connection has been aborted */
+    API_MSG_VAR_FREE_ACCEPT(msg);
+    return ERR_CLSD;
+  }
+  newconn = (struct netconn *)accept_ptr;
+#if TCP_LISTEN_BACKLOG
+  /* Let the stack know that we have accepted the connection. */
+  API_MSG_VAR_REF(msg).conn = newconn;
+  /* don't care for the return value of lwip_netconn_do_recv */
+  netconn_apimsg(lwip_netconn_do_accepted, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+#endif /* TCP_LISTEN_BACKLOG */
+
+  *new_conn = newconn;
+  /* don't set conn->last_err: it's only ERR_OK, anyway */
+  return ERR_OK;
+#else /* LWIP_TCP */
+  LWIP_UNUSED_ARG(conn);
+  LWIP_UNUSED_ARG(new_conn);
+  return ERR_ARG;
+#endif /* LWIP_TCP */
+}
+
+/**
+ * @ingroup netconn_common
+ * Receive data: actual implementation that doesn't care whether pbuf or netbuf
+ * is received (this is internal, it's just here for describing common errors)
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new pbuf/netbuf is stored when received data
+ * @param apiflags flags that control function behaviour. For now only:
+ * - NETCONN_DONTBLOCK: only read data that is available now, don't wait for more data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ *         ERR_CONN if not connected
+ *         ERR_CLSD if TCP connection has been closed
+ *         ERR_WOULDBLOCK if the netconn is nonblocking but would block to wait for data
+ *         ERR_TIMEOUT if the netconn has a receive timeout and no data was received
+ */
+static err_t
+netconn_recv_data(struct netconn *conn, void **new_buf, u8_t apiflags)
+{
+  void *buf = NULL;
+  u16_t len;
+
+  LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;);
+  *new_buf = NULL;
+  LWIP_ERROR("netconn_recv: invalid conn",    (conn != NULL),    return ERR_ARG;);
+
+  if (!NETCONN_RECVMBOX_WAITABLE(conn)) {
+    err_t err = netconn_err(conn);
+    if (err != ERR_OK) {
+      /* return pending error */
+      return err;
+    }
+    return ERR_CONN;
+  }
+
+  NETCONN_MBOX_WAITING_INC(conn);
+  if (netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK) ||
+      (conn->flags & NETCONN_FLAG_MBOXCLOSED) || (conn->pending_err != ERR_OK)) {
+    if (sys_arch_mbox_tryfetch(&conn->recvmbox, &buf) == SYS_ARCH_TIMEOUT) {
+      err_t err;
+      NETCONN_MBOX_WAITING_DEC(conn);
+      err = netconn_err(conn);
+      if (err != ERR_OK) {
+        /* return pending error */
+        return err;
+      }
+      if (conn->flags & NETCONN_FLAG_MBOXCLOSED) {
+        return ERR_CONN;
+      }
+      return ERR_WOULDBLOCK;
+    }
+  } else {
+#if LWIP_SO_RCVTIMEO
+    if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) {
+      NETCONN_MBOX_WAITING_DEC(conn);
+      return ERR_TIMEOUT;
+    }
+#else
+    sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0);
+#endif /* LWIP_SO_RCVTIMEO*/
+  }
+  NETCONN_MBOX_WAITING_DEC(conn);
+#if LWIP_NETCONN_FULLDUPLEX
+  if (conn->flags & NETCONN_FLAG_MBOXINVALID) {
+    if (lwip_netconn_is_deallocated_msg(buf)) {
+      /* the netconn has been closed from another thread */
+      API_MSG_VAR_FREE_ACCEPT(msg);
+      return ERR_CONN;
+    }
+  }
+#endif
+
+#if LWIP_TCP
+#if (LWIP_UDP || LWIP_RAW)
+  if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  {
+    err_t err;
+    /* Check if this is an error message or a pbuf */
+    if (lwip_netconn_is_err_msg(buf, &err)) {
+      /* new_buf has been zeroed above already */
+      if (err == ERR_CLSD) {
+        /* connection closed translates to ERR_OK with *new_buf == NULL */
+        return ERR_OK;
+      }
+      return err;
+    }
+    len = ((struct pbuf *)buf)->tot_len;
+  }
+#endif /* LWIP_TCP */
+#if LWIP_TCP && (LWIP_UDP || LWIP_RAW)
+  else
+#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */
+#if (LWIP_UDP || LWIP_RAW)
+  {
+    LWIP_ASSERT("buf != NULL", buf != NULL);
+    len = netbuf_len((struct netbuf *)buf);
+  }
+#endif /* (LWIP_UDP || LWIP_RAW) */
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_DEC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+  /* Register event with callback */
+  API_EVENT(conn, NETCONN_EVT_RCVMINUS, len);
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len));
+
+  *new_buf = buf;
+  /* don't set conn->last_err: it's only ERR_OK, anyway */
+  return ERR_OK;
+}
+
+#if LWIP_TCP
+static err_t
+netconn_tcp_recvd_msg(struct netconn *conn, size_t len, struct api_msg *msg)
+{
+  LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) &&
+             NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;);
+
+  msg->conn = conn;
+  msg->msg.r.len = len;
+
+  return netconn_apimsg(lwip_netconn_do_recv, msg);
+}
+
+err_t
+netconn_tcp_recvd(struct netconn *conn, size_t len)
+{
+  err_t err;
+  API_MSG_VAR_DECLARE(msg);
+  LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) &&
+             NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+  err = netconn_tcp_recvd_msg(conn, len, &API_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+  return err;
+}
+
+static err_t
+netconn_recv_data_tcp(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags)
+{
+  err_t err;
+  struct pbuf *buf;
+  API_MSG_VAR_DECLARE(msg);
+#if LWIP_MPU_COMPATIBLE
+  msg = NULL;
+#endif
+
+  if (!NETCONN_RECVMBOX_WAITABLE(conn)) {
+    /* This only happens when calling this function more than once *after* receiving FIN */
+    return ERR_CONN;
+  }
+  if (netconn_is_flag_set(conn, NETCONN_FIN_RX_PENDING)) {
+    netconn_clear_flags(conn, NETCONN_FIN_RX_PENDING);
+    goto handle_fin;
+  }
+
+  if (!(apiflags & NETCONN_NOAUTORCVD)) {
+    /* need to allocate API message here so empty message pool does not result in event loss
+      * see bug #47512: MPU_COMPATIBLE may fail on empty pool */
+    API_MSG_VAR_ALLOC(msg);
+  }
+
+  err = netconn_recv_data(conn, (void **)new_buf, apiflags);
+  if (err != ERR_OK) {
+    if (!(apiflags & NETCONN_NOAUTORCVD)) {
+      API_MSG_VAR_FREE(msg);
+    }
+    return err;
+  }
+  buf = *new_buf;
+  if (!(apiflags & NETCONN_NOAUTORCVD)) {
+    /* Let the stack know that we have taken the data. */
+    u16_t len = buf ? buf->tot_len : 1;
+    /* don't care for the return value of lwip_netconn_do_recv */
+    /* @todo: this should really be fixed, e.g. by retrying in poll on error */
+    netconn_tcp_recvd_msg(conn, len,  &API_VAR_REF(msg));
+    API_MSG_VAR_FREE(msg);
+  }
+
+  /* If we are closed, we indicate that we no longer wish to use the socket */
+  if (buf == NULL) {
+    if (apiflags & NETCONN_NOFIN) {
+      /* received a FIN but the caller cannot handle it right now:
+         re-enqueue it and return "no data" */
+      netconn_set_flags(conn, NETCONN_FIN_RX_PENDING);
+      return ERR_WOULDBLOCK;
+    } else {
+handle_fin:
+      API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0);
+      if (conn->pcb.ip == NULL) {
+        /* race condition: RST during recv */
+        err = netconn_err(conn);
+        if (err != ERR_OK) {
+          return err;
+        }
+        return ERR_RST;
+      }
+      /* RX side is closed, so deallocate the recvmbox */
+      netconn_close_shutdown(conn, NETCONN_SHUT_RD);
+      /* Don' store ERR_CLSD as conn->err since we are only half-closed */
+      return ERR_CLSD;
+    }
+  }
+  return err;
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Receive data (in form of a pbuf) from a TCP netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new pbuf is stored when received data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error, @see netconn_recv_data)
+ *         ERR_ARG if conn is not a TCP netconn
+ */
+err_t
+netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf)
+{
+  LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) &&
+             NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;);
+
+  return netconn_recv_data_tcp(conn, new_buf, 0);
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Receive data (in form of a pbuf) from a TCP netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new pbuf is stored when received data
+ * @param apiflags flags that control function behaviour. For now only:
+ * - NETCONN_DONTBLOCK: only read data that is available now, don't wait for more data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error, @see netconn_recv_data)
+ *         ERR_ARG if conn is not a TCP netconn
+ */
+err_t
+netconn_recv_tcp_pbuf_flags(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags)
+{
+  LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) &&
+             NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;);
+
+  return netconn_recv_data_tcp(conn, new_buf, apiflags);
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Receive data (in form of a netbuf) from a UDP or RAW netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new netbuf is stored when received data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ *         ERR_ARG if conn is not a UDP/RAW netconn
+ */
+err_t
+netconn_recv_udp_raw_netbuf(struct netconn *conn, struct netbuf **new_buf)
+{
+  LWIP_ERROR("netconn_recv_udp_raw_netbuf: invalid conn", (conn != NULL) &&
+             NETCONNTYPE_GROUP(netconn_type(conn)) != NETCONN_TCP, return ERR_ARG;);
+
+  return netconn_recv_data(conn, (void **)new_buf, 0);
+}
+
+/**
+ * Receive data (in form of a netbuf) from a UDP or RAW netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new netbuf is stored when received data
+ * @param apiflags flags that control function behaviour. For now only:
+ * - NETCONN_DONTBLOCK: only read data that is available now, don't wait for more data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ *         ERR_ARG if conn is not a UDP/RAW netconn
+ */
+err_t
+netconn_recv_udp_raw_netbuf_flags(struct netconn *conn, struct netbuf **new_buf, u8_t apiflags)
+{
+  LWIP_ERROR("netconn_recv_udp_raw_netbuf: invalid conn", (conn != NULL) &&
+             NETCONNTYPE_GROUP(netconn_type(conn)) != NETCONN_TCP, return ERR_ARG;);
+
+  return netconn_recv_data(conn, (void **)new_buf, apiflags);
+}
+
+/**
+ * @ingroup netconn_common
+ * Receive data (in form of a netbuf containing a packet buffer) from a netconn
+ *
+ * @param conn the netconn from which to receive data
+ * @param new_buf pointer where a new netbuf is stored when received data
+ * @return ERR_OK if data has been received, an error code otherwise (timeout,
+ *                memory error or another error)
+ */
+err_t
+netconn_recv(struct netconn *conn, struct netbuf **new_buf)
+{
+#if LWIP_TCP
+  struct netbuf *buf = NULL;
+  err_t err;
+#endif /* LWIP_TCP */
+
+  LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;);
+  *new_buf = NULL;
+  LWIP_ERROR("netconn_recv: invalid conn",    (conn != NULL),    return ERR_ARG;);
+
+#if LWIP_TCP
+#if (LWIP_UDP || LWIP_RAW)
+  if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  {
+    struct pbuf *p = NULL;
+    /* This is not a listening netconn, since recvmbox is set */
+
+    buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+    if (buf == NULL) {
+      return ERR_MEM;
+    }
+
+    err = netconn_recv_data_tcp(conn, &p, 0);
+    if (err != ERR_OK) {
+      memp_free(MEMP_NETBUF, buf);
+      return err;
+    }
+    LWIP_ASSERT("p != NULL", p != NULL);
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->port = 0;
+    ip_addr_set_zero(&buf->addr);
+    *new_buf = buf;
+    /* don't set conn->last_err: it's only ERR_OK, anyway */
+    return ERR_OK;
+  }
+#endif /* LWIP_TCP */
+#if LWIP_TCP && (LWIP_UDP || LWIP_RAW)
+  else
+#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */
+  {
+#if (LWIP_UDP || LWIP_RAW)
+    return netconn_recv_data(conn, (void **)new_buf, 0);
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+}
+
+/**
+ * @ingroup netconn_udp
+ * Send data (in form of a netbuf) to a specific remote IP address and port.
+ * Only to be used for UDP and RAW netconns (not TCP).
+ *
+ * @param conn the netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @param addr the remote IP address to which to send the data
+ * @param port the remote port to which to send the data
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_sendto(struct netconn *conn, struct netbuf *buf, const ip_addr_t *addr, u16_t port)
+{
+  if (buf != NULL) {
+    ip_addr_set(&buf->addr, addr);
+    buf->port = port;
+    return netconn_send(conn, buf);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup netconn_udp
+ * Send data over a UDP or RAW netconn (that is already connected).
+ *
+ * @param conn the UDP or RAW netconn over which to send data
+ * @param buf a netbuf containing the data to send
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_send: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len));
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.b = buf;
+  err = netconn_apimsg(lwip_netconn_do_send, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Send data over a TCP netconn.
+ *
+ * @param conn the TCP netconn over which to send data
+ * @param dataptr pointer to the application buffer that contains the data to send
+ * @param size size of the application data to send
+ * @param apiflags combination of following flags :
+ * - NETCONN_COPY: data will be copied into memory belonging to the stack
+ * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent
+ * - NETCONN_DONTBLOCK: only write the data if all data can be written at once
+ * @param bytes_written pointer to a location that receives the number of written bytes
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size,
+                     u8_t apiflags, size_t *bytes_written)
+{
+  struct netvector vector;
+  vector.ptr = dataptr;
+  vector.len = size;
+  return netconn_write_vectors_partly(conn, &vector, 1, apiflags, bytes_written);
+}
+
+/**
+ * Send vectorized data atomically over a TCP netconn.
+ *
+ * @param conn the TCP netconn over which to send data
+ * @param vectors array of vectors containing data to send
+ * @param vectorcnt number of vectors in the array
+ * @param apiflags combination of following flags :
+ * - NETCONN_COPY: data will be copied into memory belonging to the stack
+ * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent
+ * - NETCONN_DONTBLOCK: only write the data if all data can be written at once
+ * @param bytes_written pointer to a location that receives the number of written bytes
+ * @return ERR_OK if data was sent, any other err_t on error
+ */
+err_t
+netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt,
+                             u8_t apiflags, size_t *bytes_written)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+  u8_t dontblock;
+  size_t size;
+  int i;
+
+  LWIP_ERROR("netconn_write: invalid conn",  (conn != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_write: invalid conn->type",  (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP), return ERR_VAL;);
+  dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK);
+#if LWIP_SO_SNDTIMEO
+  if (conn->send_timeout != 0) {
+    dontblock = 1;
+  }
+#endif /* LWIP_SO_SNDTIMEO */
+  if (dontblock && !bytes_written) {
+    /* This implies netconn_write() cannot be used for non-blocking send, since
+       it has no way to return the number of bytes written. */
+    return ERR_VAL;
+  }
+
+  /* sum up the total size */
+  size = 0;
+  for (i = 0; i < vectorcnt; i++) {
+    size += vectors[i].len;
+    if (size < vectors[i].len) {
+      /* overflow */
+      return ERR_VAL;
+    }
+  }
+  if (size == 0) {
+    return ERR_OK;
+  } else if (size > SSIZE_MAX) {
+    ssize_t limited;
+    /* this is required by the socket layer (cannot send full size_t range) */
+    if (!bytes_written) {
+      return ERR_VAL;
+    }
+    /* limit the amount of data to send */
+    limited = SSIZE_MAX;
+    size = (size_t)limited;
+  }
+
+  API_MSG_VAR_ALLOC(msg);
+  /* non-blocking write sends as much  */
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.w.vector = vectors;
+  API_MSG_VAR_REF(msg).msg.w.vector_cnt = vectorcnt;
+  API_MSG_VAR_REF(msg).msg.w.vector_off = 0;
+  API_MSG_VAR_REF(msg).msg.w.apiflags = apiflags;
+  API_MSG_VAR_REF(msg).msg.w.len = size;
+  API_MSG_VAR_REF(msg).msg.w.offset = 0;
+#if LWIP_SO_SNDTIMEO
+  if (conn->send_timeout != 0) {
+    /* get the time we started, which is later compared to
+        Milliseconds() + conn->send_timeout */
+    API_MSG_VAR_REF(msg).msg.w.time_started = Milliseconds();
+  } else {
+    API_MSG_VAR_REF(msg).msg.w.time_started = 0;
+  }
+#endif /* LWIP_SO_SNDTIMEO */
+
+  /* For locking the core: this _can_ be delayed on low memory/low send buffer,
+     but if it is, this is done inside api_msg.c:do_write(), so we can use the
+     non-blocking version here. */
+  err = netconn_apimsg(lwip_netconn_do_write, &API_MSG_VAR_REF(msg));
+  if (err == ERR_OK) {
+    if (bytes_written != NULL) {
+      *bytes_written = API_MSG_VAR_REF(msg).msg.w.offset;
+    }
+    /* for blocking, check all requested bytes were written, NOTE: send_timeout is
+       treated as dontblock (see dontblock assignment above) */
+    if (!dontblock) {
+      LWIP_ASSERT("do_write failed to write all bytes", API_MSG_VAR_REF(msg).msg.w.offset == size);
+    }
+  }
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Close or shutdown a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to close or shutdown
+ * @param how fully close or only shutdown one side?
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+static err_t
+netconn_close_shutdown(struct netconn *conn, u8_t how)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+  LWIP_UNUSED_ARG(how);
+
+  LWIP_ERROR("netconn_close: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+  API_MSG_VAR_REF(msg).conn = conn;
+#if LWIP_TCP
+  /* shutting down both ends is the same as closing */
+  API_MSG_VAR_REF(msg).msg.sd.shut = how;
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+  /* get the time we started, which is later compared to
+     Milliseconds() + conn->send_timeout */
+  API_MSG_VAR_REF(msg).msg.sd.time_started = Milliseconds();
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+  API_MSG_VAR_REF(msg).msg.sd.polls_left =
+    ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1;
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+#endif /* LWIP_TCP */
+  err = netconn_apimsg(lwip_netconn_do_close, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Close a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to close
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_close(struct netconn *conn)
+{
+  /* shutting down both ends is the same as closing */
+  return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR);
+}
+
+/**
+ * @ingroup netconn_common
+ * Get and reset pending error on a netconn
+ *
+ * @param conn the netconn to get the error from
+ * @return and pending error or ERR_OK if no error was pending
+ */
+err_t
+netconn_err(struct netconn *conn)
+{
+  err_t err;
+  SYS_ARCH_DECL_PROTECT(lev);
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+  SYS_ARCH_PROTECT(lev);
+  err = conn->pending_err;
+  conn->pending_err = ERR_OK;
+  SYS_ARCH_UNPROTECT(lev);
+  return err;
+}
+
+/**
+ * @ingroup netconn_tcp
+ * Shut down one or both sides of a TCP netconn (doesn't delete it).
+ *
+ * @param conn the TCP netconn to shut down
+ * @param shut_rx shut down the RX side (no more read possible after this)
+ * @param shut_tx shut down the TX side (no more write possible after this)
+ * @return ERR_OK if the netconn was closed, any other err_t on error
+ */
+err_t
+netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx)
+{
+  return netconn_close_shutdown(conn, (u8_t)((shut_rx ? NETCONN_SHUT_RD : 0) | (shut_tx ? NETCONN_SHUT_WR : 0)));
+}
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+/**
+ * @ingroup netconn_udp
+ * Join multicast groups for UDP netconns.
+ *
+ * @param conn the UDP netconn for which to change multicast addresses
+ * @param multiaddr IP address of the multicast group to join or leave
+ * @param netif_addr the IP address of the network interface on which to send
+ *                  the igmp message
+ * @param join_or_leave flag whether to send a join- or leave-message
+ * @return ERR_OK if the action was taken, any err_t on error
+ */
+err_t
+netconn_join_leave_group(struct netconn *conn,
+                         const ip_addr_t *multiaddr,
+                         const ip_addr_t *netif_addr,
+                         enum netconn_igmp join_or_leave)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_join_leave_group: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */
+  if (multiaddr == NULL) {
+    multiaddr = IP4_ADDR_ANY;
+  }
+  if (netif_addr == NULL) {
+    netif_addr = IP4_ADDR_ANY;
+  }
+#endif /* LWIP_IPV4 */
+
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.jl.multiaddr = API_MSG_VAR_REF(multiaddr);
+  API_MSG_VAR_REF(msg).msg.jl.netif_addr = API_MSG_VAR_REF(netif_addr);
+  API_MSG_VAR_REF(msg).msg.jl.join_or_leave = join_or_leave;
+  err = netconn_apimsg(lwip_netconn_do_join_leave_group, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+/**
+ * @ingroup netconn_udp
+ * Join multicast groups for UDP netconns.
+ *
+ * @param conn the UDP netconn for which to change multicast addresses
+ * @param multiaddr IP address of the multicast group to join or leave
+ * @param if_idx the index of the netif
+ * @param join_or_leave flag whether to send a join- or leave-message
+ * @return ERR_OK if the action was taken, any err_t on error
+ */
+err_t
+netconn_join_leave_group_netif(struct netconn *conn,
+                               const ip_addr_t *multiaddr,
+                               u8_t if_idx,
+                               enum netconn_igmp join_or_leave)
+{
+  API_MSG_VAR_DECLARE(msg);
+  err_t err;
+
+  LWIP_ERROR("netconn_join_leave_group: invalid conn",  (conn != NULL), return ERR_ARG;);
+
+  API_MSG_VAR_ALLOC(msg);
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */
+  if (multiaddr == NULL) {
+    multiaddr = IP4_ADDR_ANY;
+  }
+  if (if_idx == NETIF_NO_INDEX) {
+    return ERR_IF;
+  }
+#endif /* LWIP_IPV4 */
+
+  API_MSG_VAR_REF(msg).conn = conn;
+  API_MSG_VAR_REF(msg).msg.jl.multiaddr = API_MSG_VAR_REF(multiaddr);
+  API_MSG_VAR_REF(msg).msg.jl.if_idx = if_idx;
+  API_MSG_VAR_REF(msg).msg.jl.join_or_leave = join_or_leave;
+  err = netconn_apimsg(lwip_netconn_do_join_leave_group_netif, &API_MSG_VAR_REF(msg));
+  API_MSG_VAR_FREE(msg);
+
+  return err;
+}
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+/**
+ * @ingroup netconn_common
+ * Execute a DNS query, only one IP address is returned
+ *
+ * @param name a string representation of the DNS host name to query
+ * @param addr a preallocated ip_addr_t where to store the resolved IP address
+ * @param dns_addrtype IP address type (IPv4 / IPv6)
+ * @return ERR_OK: resolving succeeded
+ *         ERR_MEM: memory error, try again later
+ *         ERR_ARG: dns client not initialized or invalid hostname
+ *         ERR_VAL: dns server response was invalid
+ */
+#if LWIP_IPV4 && LWIP_IPV6
+err_t
+netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype)
+#else
+err_t
+netconn_gethostbyname(const char *name, ip_addr_t *addr)
+#endif
+{
+  API_VAR_DECLARE(struct dns_api_msg, msg);
+#if !LWIP_MPU_COMPATIBLE
+  sys_sem_t sem;
+#endif /* LWIP_MPU_COMPATIBLE */
+  err_t err;
+  err_t cberr;
+
+  LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;);
+  LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;);
+#if LWIP_MPU_COMPATIBLE
+  if (strlen(name) >= DNS_MAX_NAME_LENGTH) {
+    return ERR_ARG;
+  }
+#endif
+
+#ifdef LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE
+#if LWIP_IPV4 && LWIP_IPV6
+  if (LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, dns_addrtype, &err)) {
+#else
+  if (LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, NETCONN_DNS_DEFAULT, &err)) {
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+    return err;
+  }
+#endif /* LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE */
+
+  API_VAR_ALLOC(struct dns_api_msg, MEMP_DNS_API_MSG, msg, ERR_MEM);
+#if LWIP_MPU_COMPATIBLE
+  strncpy(API_VAR_REF(msg).name, name, DNS_MAX_NAME_LENGTH - 1);
+  API_VAR_REF(msg).name[DNS_MAX_NAME_LENGTH - 1] = 0;
+#else /* LWIP_MPU_COMPATIBLE */
+  msg.err = &err;
+  msg.sem = &sem;
+  API_VAR_REF(msg).addr = API_VAR_REF(addr);
+  API_VAR_REF(msg).name = name;
+#endif /* LWIP_MPU_COMPATIBLE */
+#if LWIP_IPV4 && LWIP_IPV6
+  API_VAR_REF(msg).dns_addrtype = dns_addrtype;
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#if LWIP_NETCONN_SEM_PER_THREAD
+  API_VAR_REF(msg).sem = LWIP_NETCONN_THREAD_SEM_GET();
+#else /* LWIP_NETCONN_SEM_PER_THREAD*/
+  err = sys_sem_new(API_EXPR_REF(API_VAR_REF(msg).sem), 0);
+  if (err != ERR_OK) {
+    API_VAR_FREE(MEMP_DNS_API_MSG, msg);
+    return err;
+  }
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+  cberr = tcpip_send_msg_wait_sem(lwip_netconn_do_gethostbyname, &API_VAR_REF(msg), API_EXPR_REF(API_VAR_REF(msg).sem));
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_free(API_EXPR_REF(API_VAR_REF(msg).sem));
+#endif /* !LWIP_NETCONN_SEM_PER_THREAD */
+  if (cberr != ERR_OK) {
+    API_VAR_FREE(MEMP_DNS_API_MSG, msg);
+    return cberr;
+  }
+
+#if LWIP_MPU_COMPATIBLE
+  *addr = msg->addr;
+  err = msg->err;
+#endif /* LWIP_MPU_COMPATIBLE */
+
+  API_VAR_FREE(MEMP_DNS_API_MSG, msg);
+  return err;
+}
+#endif /* LWIP_DNS*/
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+void
+netconn_thread_init(void)
+{
+  sys_sem_t *sem = LWIP_NETCONN_THREAD_SEM_GET();
+  if ((sem == NULL) || !sys_sem_valid(sem)) {
+    /* call alloc only once */
+    LWIP_NETCONN_THREAD_SEM_ALLOC();
+    LWIP_ASSERT("LWIP_NETCONN_THREAD_SEM_ALLOC() failed", sys_sem_valid(LWIP_NETCONN_THREAD_SEM_GET()));
+  }
+}
+
+void
+netconn_thread_cleanup(void)
+{
+  sys_sem_t *sem = LWIP_NETCONN_THREAD_SEM_GET();
+  if ((sem != NULL) && sys_sem_valid(sem)) {
+    /* call free only once */
+    LWIP_NETCONN_THREAD_SEM_FREE();
+  }
+}
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+#endif /* LWIP_NETCONN */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/api_msg.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/api_msg.c
new file mode 100644
index 000000000..7e77957fa
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/api_msg.c
@@ -0,0 +1,2173 @@
+/**
+ * @file
+ * Sequential API Internal module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/priv/api_msg.h"
+
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+
+#include "lwip/memp.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "lwip/mld6.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#include <string.h>
+
+/* netconns are polled once per second (e.g. continue write on memory error) */
+#define NETCONN_TCP_POLL_INTERVAL 2
+
+#define SET_NONBLOCKING_CONNECT(conn, val)  do { if (val) { \
+  netconn_set_flags(conn, NETCONN_FLAG_IN_NONBLOCKING_CONNECT); \
+} else { \
+  netconn_clear_flags(conn, NETCONN_FLAG_IN_NONBLOCKING_CONNECT); }} while(0)
+#define IN_NONBLOCKING_CONNECT(conn) netconn_is_flag_set(conn, NETCONN_FLAG_IN_NONBLOCKING_CONNECT)
+
+#if LWIP_NETCONN_FULLDUPLEX
+#define NETCONN_MBOX_VALID(conn, mbox) (sys_mbox_valid(mbox) && ((conn->flags & NETCONN_FLAG_MBOXINVALID) == 0))
+#else
+#define NETCONN_MBOX_VALID(conn, mbox) sys_mbox_valid(mbox)
+#endif
+
+/* forward declarations */
+#if LWIP_TCP
+#if LWIP_TCPIP_CORE_LOCKING
+#define WRITE_DELAYED         , 1
+#define WRITE_DELAYED_PARAM   , u8_t delayed
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define WRITE_DELAYED
+#define WRITE_DELAYED_PARAM
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+static err_t lwip_netconn_do_writemore(struct netconn *conn  WRITE_DELAYED_PARAM);
+static err_t lwip_netconn_do_close_internal(struct netconn *conn  WRITE_DELAYED_PARAM);
+#endif
+
+static void netconn_drain(struct netconn *conn);
+
+#if LWIP_TCPIP_CORE_LOCKING
+#define TCPIP_APIMSG_ACK(m)
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define TCPIP_APIMSG_ACK(m)   do { sys_sem_signal(LWIP_API_MSG_SEM(m)); } while(0)
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+#if LWIP_NETCONN_FULLDUPLEX
+const u8_t netconn_deleted = 0;
+
+int
+lwip_netconn_is_deallocated_msg(void *msg)
+{
+  if (msg == &netconn_deleted) {
+    return 1;
+  }
+  return 0;
+}
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+#if LWIP_TCP
+const u8_t netconn_aborted = 0;
+const u8_t netconn_reset = 0;
+const u8_t netconn_closed = 0;
+
+/** Translate an error to a unique void* passed via an mbox */
+static void *
+lwip_netconn_err_to_msg(err_t err)
+{
+  switch (err) {
+    case ERR_ABRT:
+      return LWIP_CONST_CAST(void *, &netconn_aborted);
+    case ERR_RST:
+      return LWIP_CONST_CAST(void *, &netconn_reset);
+    case ERR_CLSD:
+      return LWIP_CONST_CAST(void *, &netconn_closed);
+    default:
+      LWIP_ASSERT("unhandled error", err == ERR_OK);
+      return NULL;
+  }
+}
+
+int
+lwip_netconn_is_err_msg(void *msg, err_t *err)
+{
+  LWIP_ASSERT("err != NULL", err != NULL);
+
+  if (msg == &netconn_aborted) {
+    *err = ERR_ABRT;
+    return 1;
+  } else if (msg == &netconn_reset) {
+    *err = ERR_RST;
+    return 1;
+  } else if (msg == &netconn_closed) {
+    *err = ERR_CLSD;
+    return 1;
+  }
+  return 0;
+}
+#endif /* LWIP_TCP */
+
+
+#if LWIP_RAW
+/**
+ * Receive callback function for RAW netconns.
+ * Doesn't 'eat' the packet, only copies it and sends it to
+ * conn->recvmbox
+ *
+ * @see raw.h (struct raw_pcb.recv) for parameters and return value
+ */
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+         const ip_addr_t *addr)
+{
+  struct pbuf *q;
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  LWIP_UNUSED_ARG(addr);
+  conn = (struct netconn *)arg;
+
+  if ((conn != NULL) && NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+#if LWIP_SO_RCVBUF
+    int recv_avail;
+    SYS_ARCH_GET(conn->recv_avail, recv_avail);
+    if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) {
+      return 0;
+    }
+#endif /* LWIP_SO_RCVBUF */
+    /* copy the whole packet into new pbufs */
+    q = pbuf_clone(PBUF_RAW, PBUF_RAM, p);
+    if (q != NULL) {
+      u16_t len;
+      buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+      if (buf == NULL) {
+        pbuf_free(q);
+        return 0;
+      }
+
+      buf->p = q;
+      buf->ptr = q;
+      ip_addr_copy(buf->addr, *ip_current_src_addr());
+      buf->port = pcb->protocol;
+
+      len = q->tot_len;
+      if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) {
+        netbuf_delete(buf);
+        return 0;
+      } else {
+#if LWIP_SO_RCVBUF
+        SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+        /* Register event with callback */
+        API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+      }
+    }
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif /* LWIP_RAW*/
+
+#if LWIP_UDP
+/**
+ * Receive callback function for UDP netconns.
+ * Posts the packet to conn->recvmbox or deletes it on memory error.
+ *
+ * @see udp.h (struct udp_pcb.recv) for parameters
+ */
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+         const ip_addr_t *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+  u16_t len;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  LWIP_UNUSED_ARG(pcb); /* only used for asserts... */
+  LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_udp must have an argument", arg != NULL);
+  conn = (struct netconn *)arg;
+
+  if (conn == NULL) {
+    pbuf_free(p);
+    return;
+  }
+
+  LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb);
+
+#if LWIP_SO_RCVBUF
+  SYS_ARCH_GET(conn->recv_avail, recv_avail);
+  if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox) ||
+      ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) {
+#else  /* LWIP_SO_RCVBUF */
+  if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+#endif /* LWIP_SO_RCVBUF */
+    pbuf_free(p);
+    return;
+  }
+
+  buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+  if (buf == NULL) {
+    pbuf_free(p);
+    return;
+  } else {
+    buf->p = p;
+    buf->ptr = p;
+    ip_addr_set(&buf->addr, addr);
+    buf->port = port;
+#if LWIP_NETBUF_RECVINFO
+    if (conn->flags & NETCONN_FLAG_PKTINFO) {
+      /* get the UDP header - always in the first pbuf, ensured by udp_input */
+      const struct udp_hdr *udphdr = (const struct udp_hdr *)ip_next_header_ptr();
+      buf->flags = NETBUF_FLAG_DESTADDR;
+      ip_addr_set(&buf->toaddr, ip_current_dest_addr());
+      buf->toport_chksum = udphdr->dest;
+    }
+#endif /* LWIP_NETBUF_RECVINFO */
+  }
+
+  len = p->tot_len;
+  if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) {
+    netbuf_delete(buf);
+    return;
+  } else {
+#if LWIP_SO_RCVBUF
+    SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+  }
+}
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+/**
+ * Receive callback function for TCP netconns.
+ * Posts the packet to conn->recvmbox, but doesn't delete it on errors.
+ *
+ * @see tcp.h (struct tcp_pcb.recv) for parameters and return value
+ */
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+  void *msg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL);
+  LWIP_ASSERT("recv_tcp must have an argument", arg != NULL);
+  LWIP_ASSERT("err != ERR_OK unhandled", err == ERR_OK);
+  LWIP_UNUSED_ARG(err); /* for LWIP_NOASSERT */
+  conn = (struct netconn *)arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb);
+
+  if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+    /* recvmbox already deleted */
+    if (p != NULL) {
+      tcp_recved(pcb, p->tot_len);
+      pbuf_free(p);
+    }
+    return ERR_OK;
+  }
+  /* Unlike for UDP or RAW pcbs, don't check for available space
+     using recv_avail since that could break the connection
+     (data is already ACKed) */
+
+  if (p != NULL) {
+    msg = p;
+    len = p->tot_len;
+  } else {
+    msg = LWIP_CONST_CAST(void *, &netconn_closed);
+    len = 0;
+  }
+
+  if (sys_mbox_trypost(&conn->recvmbox, msg) != ERR_OK) {
+    /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */
+    return ERR_MEM;
+  } else {
+#if LWIP_SO_RCVBUF
+    SYS_ARCH_INC(conn->recv_avail, len);
+#endif /* LWIP_SO_RCVBUF */
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, len);
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Poll callback function for TCP netconns.
+ * Wakes up an application thread that waits for a connection to close
+ * or data to be sent. The application thread then takes the
+ * appropriate action to go on.
+ *
+ * Signals the conn->sem.
+ * netconn_close waits for conn->sem if closing failed.
+ *
+ * @see tcp.h (struct tcp_pcb.poll) for parameters and return value
+ */
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn = (struct netconn *)arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn->state == NETCONN_WRITE) {
+    lwip_netconn_do_writemore(conn  WRITE_DELAYED);
+  } else if (conn->state == NETCONN_CLOSE) {
+#if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER
+    if (conn->current_msg && conn->current_msg->msg.sd.polls_left) {
+      conn->current_msg->msg.sd.polls_left--;
+    }
+#endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */
+    lwip_netconn_do_close_internal(conn  WRITE_DELAYED);
+  }
+  /* @todo: implement connect timeout here? */
+
+  /* Did a nonblocking write fail before? Then check available write-space. */
+  if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) {
+    /* If the queued byte- or pbuf-count drops below the configured low-water limit,
+       let select mark this pcb as writable again. */
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+        (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) {
+      netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE);
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+    }
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Sent callback function for TCP netconns.
+ * Signals the conn->sem and calls API_EVENT.
+ * netconn_write waits for conn->sem if send buffer is low.
+ *
+ * @see tcp.h (struct tcp_pcb.sent) for parameters and return value
+ */
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn = (struct netconn *)arg;
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  if (conn) {
+    if (conn->state == NETCONN_WRITE) {
+      lwip_netconn_do_writemore(conn  WRITE_DELAYED);
+    } else if (conn->state == NETCONN_CLOSE) {
+      lwip_netconn_do_close_internal(conn  WRITE_DELAYED);
+    }
+
+    /* If the queued byte- or pbuf-count drops below the configured low-water limit,
+       let select mark this pcb as writable again. */
+    if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) &&
+        (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) {
+      netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE);
+      API_EVENT(conn, NETCONN_EVT_SENDPLUS, len);
+    }
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Error callback function for TCP netconns.
+ * Signals conn->sem, posts to all conn mboxes and calls API_EVENT.
+ * The application thread has then to decide what to do.
+ *
+ * @see tcp.h (struct tcp_pcb.err) for parameters
+ */
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+  enum netconn_state old_state;
+  void *mbox_msg;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  conn = (struct netconn *)arg;
+  LWIP_ASSERT("conn != NULL", (conn != NULL));
+
+  SYS_ARCH_PROTECT(lev);
+
+  /* when err is called, the pcb is deallocated, so delete the reference */
+  conn->pcb.tcp = NULL;
+  /* store pending error */
+  conn->pending_err = err;
+  /* prevent application threads from blocking on 'recvmbox'/'acceptmbox' */
+  conn->flags |= NETCONN_FLAG_MBOXCLOSED;
+
+  /* reset conn->state now before waking up other threads */
+  old_state = conn->state;
+  conn->state = NETCONN_NONE;
+
+  SYS_ARCH_UNPROTECT(lev);
+
+  /* Notify the user layer about a connection error. Used to signal select. */
+  API_EVENT(conn, NETCONN_EVT_ERROR, 0);
+  /* Try to release selects pending on 'read' or 'write', too.
+     They will get an error if they actually try to read or write. */
+  API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+  API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+
+  mbox_msg = lwip_netconn_err_to_msg(err);
+  /* pass error message to recvmbox to wake up pending recv */
+  if (NETCONN_MBOX_VALID(conn, &conn->recvmbox)) {
+    /* use trypost to prevent deadlock */
+    sys_mbox_trypost(&conn->recvmbox, mbox_msg);
+  }
+  /* pass error message to acceptmbox to wake up pending accept */
+  if (NETCONN_MBOX_VALID(conn, &conn->acceptmbox)) {
+    /* use trypost to preven deadlock */
+    sys_mbox_trypost(&conn->acceptmbox, mbox_msg);
+  }
+
+  if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) ||
+      (old_state == NETCONN_CONNECT)) {
+    /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary
+       since the pcb has already been deleted! */
+    int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn);
+    SET_NONBLOCKING_CONNECT(conn, 0);
+
+    if (!was_nonblocking_connect) {
+      sys_sem_t *op_completed_sem;
+      /* set error return code */
+      LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+      if (old_state == NETCONN_CLOSE) {
+        /* let close succeed: the connection is closed after all... */
+        conn->current_msg->err = ERR_OK;
+      } else {
+        /* Write and connect fail */
+        conn->current_msg->err = err;
+      }
+      op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+      LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem));
+      conn->current_msg = NULL;
+      /* wake up the waiting task */
+      sys_sem_signal(op_completed_sem);
+    } else {
+      /* @todo: test what happens for error on nonblocking connect */
+    }
+  } else {
+    LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL);
+  }
+}
+
+/**
+ * Setup a tcp_pcb with the correct callback function pointers
+ * and their arguments.
+ *
+ * @param conn the TCP netconn to setup
+ */
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL);
+  tcp_err(pcb, err_tcp);
+}
+
+/**
+ * Accept callback function for TCP netconns.
+ * Allocates a new netconn and posts that to conn->acceptmbox.
+ *
+ * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value
+ */
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  struct netconn *newconn;
+  struct netconn *conn = (struct netconn *)arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  if (!NETCONN_MBOX_VALID(conn, &conn->acceptmbox)) {
+    LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n"));
+    return ERR_VAL;
+  }
+
+  if (newpcb == NULL) {
+    /* out-of-pcbs during connect: pass on this error to the application */
+    if (sys_mbox_trypost(&conn->acceptmbox, lwip_netconn_err_to_msg(ERR_ABRT)) == ERR_OK) {
+      /* Register event with callback */
+      API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    }
+    return ERR_VAL;
+  }
+  LWIP_ASSERT("expect newpcb == NULL or err == ERR_OK", err == ERR_OK);
+  LWIP_UNUSED_ARG(err); /* for LWIP_NOASSERT */
+
+  LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->state: %s\n", tcp_debug_state_str(newpcb->state)));
+
+  /* We have to set the callback here even though
+   * the new socket is unknown. newconn->socket is marked as -1. */
+  newconn = netconn_alloc(conn->type, conn->callback);
+  if (newconn == NULL) {
+    /* outof netconns: pass on this error to the application */
+    if (sys_mbox_trypost(&conn->acceptmbox, lwip_netconn_err_to_msg(ERR_ABRT)) == ERR_OK) {
+      /* Register event with callback */
+      API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+    }
+    return ERR_MEM;
+  }
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+
+  /* handle backlog counter */
+  tcp_backlog_delayed(newpcb);
+
+  if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) {
+    /* When returning != ERR_OK, the pcb is aborted in tcp_process(),
+       so do nothing here! */
+    /* remove all references to this netconn from the pcb */
+    struct tcp_pcb *pcb = newconn->pcb.tcp;
+    tcp_arg(pcb, NULL);
+    tcp_recv(pcb, NULL);
+    tcp_sent(pcb, NULL);
+    tcp_poll(pcb, NULL, 0);
+    tcp_err(pcb, NULL);
+    /* remove reference from to the pcb from this netconn */
+    newconn->pcb.tcp = NULL;
+    /* no need to drain since we know the recvmbox is empty. */
+    sys_mbox_free(&newconn->recvmbox);
+    sys_mbox_set_invalid(&newconn->recvmbox);
+    netconn_free(newconn);
+    return ERR_MEM;
+  } else {
+    /* Register event with callback */
+    API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+  }
+
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Create a new pcb of a specific type.
+ * Called from lwip_netconn_do_newconn().
+ *
+ * @param msg the api_msg describing the connection type
+ */
+static void
+pcb_new(struct api_msg *msg)
+{
+  enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4;
+
+  LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL);
+
+#if LWIP_IPV6 && LWIP_IPV4
+  /* IPv6: Dual-stack by default, unless netconn_set_ipv6only() is called */
+  if (NETCONNTYPE_ISIPV6(netconn_type(msg->conn))) {
+    iptype = IPADDR_TYPE_ANY;
+  }
+#endif
+
+  /* Allocate a PCB for this connection */
+  switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new_ip_type(iptype, msg->msg.n.proto);
+      if (msg->conn->pcb.raw != NULL) {
+#if LWIP_IPV6
+        /* ICMPv6 packets should always have checksum calculated by the stack as per RFC 3542 chapter 3.1 */
+        if (NETCONNTYPE_ISIPV6(msg->conn->type) && msg->conn->pcb.raw->protocol == IP6_NEXTH_ICMP6) {
+          msg->conn->pcb.raw->chksum_reqd = 1;
+          msg->conn->pcb.raw->chksum_offset = 2;
+        }
+#endif /* LWIP_IPV6 */
+        raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      }
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new_ip_type(iptype);
+      if (msg->conn->pcb.udp != NULL) {
+#if LWIP_UDPLITE
+        if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) {
+          udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+        }
+#endif /* LWIP_UDPLITE */
+        if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) {
+          udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+        }
+        udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      }
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new_ip_type(iptype);
+      if (msg->conn->pcb.tcp != NULL) {
+        setup_tcp(msg->conn);
+      }
+      break;
+#endif /* LWIP_TCP */
+    default:
+      /* Unsupported netconn type, e.g. protocol disabled */
+      msg->err = ERR_VAL;
+      return;
+  }
+  if (msg->conn->pcb.ip == NULL) {
+    msg->err = ERR_MEM;
+  }
+}
+
+/**
+ * Create a new pcb of a specific type inside a netconn.
+ * Called from netconn_new_with_proto_and_callback.
+ *
+ * @param m the api_msg describing the connection type
+ */
+void
+lwip_netconn_do_newconn(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  msg->err = ERR_OK;
+  if (msg->conn->pcb.tcp == NULL) {
+    pcb_new(msg);
+  }
+  /* Else? This "new" connection already has a PCB allocated. */
+  /* Is this an error condition? Should it be deleted? */
+  /* We currently just are happy and return. */
+
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Create a new netconn (of a specific type) that has a callback function.
+ * The corresponding pcb is NOT created!
+ *
+ * @param t the type of 'connection' to create (@see enum netconn_type)
+ * @param callback a function to call on status changes (RX available, TX'ed)
+ * @return a newly allocated struct netconn or
+ *         NULL on memory error
+ */
+struct netconn *
+netconn_alloc(enum netconn_type t, netconn_callback callback)
+{
+  struct netconn *conn;
+  int size;
+  u8_t init_flags = 0;
+
+  conn = (struct netconn *)memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+
+  conn->pending_err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+  /* If all sizes are the same, every compiler should optimize this switch to nothing */
+  switch (NETCONNTYPE_GROUP(t)) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      size = DEFAULT_RAW_RECVMBOX_SIZE;
+      break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+    case NETCONN_UDP:
+      size = DEFAULT_UDP_RECVMBOX_SIZE;
+#if LWIP_NETBUF_RECVINFO
+      init_flags |= NETCONN_FLAG_PKTINFO;
+#endif /* LWIP_NETBUF_RECVINFO */
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      size = DEFAULT_TCP_RECVMBOX_SIZE;
+      break;
+#endif /* LWIP_TCP */
+    default:
+      LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0);
+      goto free_and_return;
+  }
+
+  if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) {
+    goto free_and_return;
+  }
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) {
+    sys_mbox_free(&conn->recvmbox);
+    goto free_and_return;
+  }
+#endif
+
+#if LWIP_TCP
+  sys_mbox_set_invalid(&conn->acceptmbox);
+#endif
+  conn->state        = NETCONN_NONE;
+#if LWIP_SOCKET
+  /* initialize socket to -1 since 0 is a valid socket */
+  conn->socket       = -1;
+#endif /* LWIP_SOCKET */
+  conn->callback     = callback;
+#if LWIP_TCP
+  conn->current_msg  = NULL;
+#endif /* LWIP_TCP */
+#if LWIP_SO_SNDTIMEO
+  conn->send_timeout = 0;
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_RCVTIMEO
+  conn->recv_timeout = 0;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  conn->recv_bufsize = RECV_BUFSIZE_DEFAULT;
+  conn->recv_avail   = 0;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+  conn->linger = -1;
+#endif /* LWIP_SO_LINGER */
+  conn->flags = init_flags;
+  return conn;
+free_and_return:
+  memp_free(MEMP_NETCONN, conn);
+  return NULL;
+}
+
+/**
+ * Delete a netconn and all its resources.
+ * The pcb is NOT freed (since we might not be in the right thread context do this).
+ *
+ * @param conn the netconn to free
+ */
+void
+netconn_free(struct netconn *conn)
+{
+  LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL);
+
+#if LWIP_NETCONN_FULLDUPLEX
+  /* in fullduplex, netconn is drained here */
+  netconn_drain(conn);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+  LWIP_ASSERT("recvmbox must be deallocated before calling this function",
+              !sys_mbox_valid(&conn->recvmbox));
+#if LWIP_TCP
+  LWIP_ASSERT("acceptmbox must be deallocated before calling this function",
+              !sys_mbox_valid(&conn->acceptmbox));
+#endif /* LWIP_TCP */
+
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_free(&conn->op_completed);
+  sys_sem_set_invalid(&conn->op_completed);
+#endif
+
+  memp_free(MEMP_NETCONN, conn);
+}
+
+/**
+ * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in
+ * these mboxes
+ *
+ * @param conn the netconn to free
+ * @bytes_drained bytes drained from recvmbox
+ * @accepts_drained pending connections drained from acceptmbox
+ */
+static void
+netconn_drain(struct netconn *conn)
+{
+  void *mem;
+
+  /* This runs when mbox and netconn are marked as closed,
+     so we don't need to lock against rx packets */
+#if LWIP_NETCONN_FULLDUPLEX
+  LWIP_ASSERT("netconn marked closed", conn->flags & NETCONN_FLAG_MBOXINVALID);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+  /* Delete and drain the recvmbox. */
+  if (sys_mbox_valid(&conn->recvmbox)) {
+    while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) {
+#if LWIP_NETCONN_FULLDUPLEX
+      if (!lwip_netconn_is_deallocated_msg(mem))
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      {
+#if LWIP_TCP
+        if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) {
+          err_t err;
+          if (!lwip_netconn_is_err_msg(mem, &err)) {
+            pbuf_free((struct pbuf *)mem);
+          }
+        } else
+#endif /* LWIP_TCP */
+        {
+          netbuf_delete((struct netbuf *)mem);
+        }
+      }
+    }
+    sys_mbox_free(&conn->recvmbox);
+    sys_mbox_set_invalid(&conn->recvmbox);
+  }
+
+  /* Delete and drain the acceptmbox. */
+#if LWIP_TCP
+  if (sys_mbox_valid(&conn->acceptmbox)) {
+    while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) {
+#if LWIP_NETCONN_FULLDUPLEX
+      if (!lwip_netconn_is_deallocated_msg(mem))
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      {
+        err_t err;
+        if (!lwip_netconn_is_err_msg(mem, &err)) {
+          struct netconn *newconn = (struct netconn *)mem;
+          /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */
+          /* pcb might be set to NULL already by err_tcp() */
+          /* drain recvmbox */
+          netconn_drain(newconn);
+          if (newconn->pcb.tcp != NULL) {
+            tcp_abort(newconn->pcb.tcp);
+            newconn->pcb.tcp = NULL;
+          }
+          netconn_free(newconn);
+        }
+      }
+    }
+    sys_mbox_free(&conn->acceptmbox);
+    sys_mbox_set_invalid(&conn->acceptmbox);
+  }
+#endif /* LWIP_TCP */
+}
+
+#if LWIP_NETCONN_FULLDUPLEX
+static void
+netconn_mark_mbox_invalid(struct netconn *conn)
+{
+  int i, num_waiting;
+  void *msg = LWIP_CONST_CAST(void *, &netconn_deleted);
+
+  /* Prevent new calls/threads from reading from the mbox */
+  conn->flags |= NETCONN_FLAG_MBOXINVALID;
+
+  SYS_ARCH_LOCKED(num_waiting = conn->mbox_threads_waiting);
+  for (i = 0; i < num_waiting; i++) {
+    if (sys_mbox_valid_val(conn->recvmbox)) {
+      sys_mbox_trypost(&conn->recvmbox, msg);
+    } else {
+      sys_mbox_trypost(&conn->acceptmbox, msg);
+    }
+  }
+}
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+#if LWIP_TCP
+/**
+ * Internal helper function to close a TCP netconn: since this sometimes
+ * doesn't work at the first attempt, this function is called from multiple
+ * places.
+ *
+ * @param conn the TCP netconn to close
+ */
+static err_t
+lwip_netconn_do_close_internal(struct netconn *conn  WRITE_DELAYED_PARAM)
+{
+  err_t err;
+  u8_t shut, shut_rx, shut_tx, shut_close;
+  u8_t close_finished = 0;
+  struct tcp_pcb *tpcb;
+#if LWIP_SO_LINGER
+  u8_t linger_wait_required = 0;
+#endif /* LWIP_SO_LINGER */
+
+  LWIP_ASSERT("invalid conn", (conn != NULL));
+  LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP));
+  LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE));
+  LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL));
+  LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+
+  tpcb = conn->pcb.tcp;
+  shut = conn->current_msg->msg.sd.shut;
+  shut_rx = shut & NETCONN_SHUT_RD;
+  shut_tx = shut & NETCONN_SHUT_WR;
+  /* shutting down both ends is the same as closing
+     (also if RD or WR side was shut down before already) */
+  if (shut == NETCONN_SHUT_RDWR) {
+    shut_close = 1;
+  } else if (shut_rx &&
+             ((tpcb->state == FIN_WAIT_1) ||
+              (tpcb->state == FIN_WAIT_2) ||
+              (tpcb->state == CLOSING))) {
+    shut_close = 1;
+  } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) {
+    shut_close = 1;
+  } else {
+    shut_close = 0;
+  }
+
+  /* Set back some callback pointers */
+  if (shut_close) {
+    tcp_arg(tpcb, NULL);
+  }
+  if (tpcb->state == LISTEN) {
+    tcp_accept(tpcb, NULL);
+  } else {
+    /* some callbacks have to be reset if tcp_close is not successful */
+    if (shut_rx) {
+      tcp_recv(tpcb, NULL);
+      tcp_accept(tpcb, NULL);
+    }
+    if (shut_tx) {
+      tcp_sent(tpcb, NULL);
+    }
+    if (shut_close) {
+      tcp_poll(tpcb, NULL, 0);
+      tcp_err(tpcb, NULL);
+    }
+  }
+  /* Try to close the connection */
+  if (shut_close) {
+#if LWIP_SO_LINGER
+    /* check linger possibilites before calling tcp_close */
+    err = ERR_OK;
+    /* linger enabled/required at all? (i.e. is there untransmitted data left?) */
+    if ((conn->linger >= 0) && (conn->pcb.tcp->unsent || conn->pcb.tcp->unacked)) {
+      if ((conn->linger == 0)) {
+        /* data left but linger prevents waiting */
+        tcp_abort(tpcb);
+        tpcb = NULL;
+      } else if (conn->linger > 0) {
+        /* data left and linger says we should wait */
+        if (netconn_is_nonblocking(conn)) {
+          /* data left on a nonblocking netconn -> cannot linger */
+          err = ERR_WOULDBLOCK;
+        } else if ((s32_t)(Milliseconds() - conn->current_msg->msg.sd.time_started) >=
+                   (conn->linger * 1000)) {
+          /* data left but linger timeout has expired (this happens on further
+             calls to this function through poll_tcp */
+          tcp_abort(tpcb);
+          tpcb = NULL;
+        } else {
+          /* data left -> need to wait for ACK after successful close */
+          linger_wait_required = 1;
+        }
+      }
+    }
+    if ((err == ERR_OK) && (tpcb != NULL))
+#endif /* LWIP_SO_LINGER */
+    {
+      err = tcp_close(tpcb);
+    }
+  } else {
+    err = tcp_shutdown(tpcb, shut_rx, shut_tx);
+  }
+  if (err == ERR_OK) {
+    close_finished = 1;
+#if LWIP_SO_LINGER
+    if (linger_wait_required) {
+      /* wait for ACK of all unsent/unacked data by just getting called again */
+      close_finished = 0;
+      err = ERR_INPROGRESS;
+    }
+#endif /* LWIP_SO_LINGER */
+  } else {
+    if (err == ERR_MEM) {
+      /* Closing failed because of memory shortage, try again later. Even for
+         nonblocking netconns, we have to wait since no standard socket application
+         is prepared for close failing because of resource shortage.
+         Check the timeout: this is kind of an lwip addition to the standard sockets:
+         we wait for some time when failing to allocate a segment for the FIN */
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+      s32_t close_timeout = LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT;
+#if LWIP_SO_SNDTIMEO
+      if (conn->send_timeout > 0) {
+        close_timeout = conn->send_timeout;
+      }
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_LINGER
+      if (conn->linger >= 0) {
+        /* use linger timeout (seconds) */
+        close_timeout = conn->linger * 1000U;
+      }
+#endif
+      if ((s32_t)(Milliseconds() - conn->current_msg->msg.sd.time_started) >= close_timeout) {
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+      if (conn->current_msg->msg.sd.polls_left == 0) {
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+        close_finished = 1;
+        if (shut_close) {
+          /* in this case, we want to RST the connection */
+          tcp_abort(tpcb);
+          err = ERR_OK;
+        }
+      }
+    } else {
+      /* Closing failed for a non-memory error: give up */
+      close_finished = 1;
+    }
+  }
+  if (close_finished) {
+    /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */
+    sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+    conn->current_msg->err = err;
+    conn->current_msg = NULL;
+    conn->state = NETCONN_NONE;
+    if (err == ERR_OK) {
+      if (shut_close) {
+        /* Set back some callback pointers as conn is going away */
+        conn->pcb.tcp = NULL;
+        /* Trigger select() in socket layer. Make sure everybody notices activity
+         on the connection, error first! */
+        API_EVENT(conn, NETCONN_EVT_ERROR, 0);
+      }
+      if (shut_rx) {
+        API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0);
+      }
+      if (shut_tx) {
+        API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+      }
+    }
+#if LWIP_TCPIP_CORE_LOCKING
+    if (delayed)
+#endif
+    {
+      /* wake up the application task */
+      sys_sem_signal(op_completed_sem);
+    }
+    return ERR_OK;
+  }
+  if (!close_finished) {
+    /* Closing failed and we want to wait: restore some of the callbacks */
+    /* Closing of listen pcb will never fail! */
+    LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN));
+    if (shut_tx) {
+      tcp_sent(tpcb, sent_tcp);
+    }
+    /* when waiting for close, set up poll interval to 500ms */
+    tcp_poll(tpcb, poll_tcp, 1);
+    tcp_err(tpcb, err_tcp);
+    tcp_arg(tpcb, conn);
+    /* don't restore recv callback: we don't want to receive any more data */
+  }
+  /* If closing didn't succeed, we get called again either
+     from poll_tcp or from sent_tcp */
+  LWIP_ASSERT("err != ERR_OK", err != ERR_OK);
+  return err;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Delete the pcb inside a netconn.
+ * Called from netconn_delete.
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_delconn(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  enum netconn_state state = msg->conn->state;
+  LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */
+              (state == NETCONN_NONE) || (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP));
+#if LWIP_NETCONN_FULLDUPLEX
+  /* In full duplex mode, blocking write/connect is aborted with ERR_CLSD */
+  if (state != NETCONN_NONE) {
+    if ((state == NETCONN_WRITE) ||
+        ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) {
+      /* close requested, abort running write/connect */
+      sys_sem_t *op_completed_sem;
+      LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL);
+      op_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg);
+      msg->conn->current_msg->err = ERR_CLSD;
+      msg->conn->current_msg = NULL;
+      msg->conn->state = NETCONN_NONE;
+      sys_sem_signal(op_completed_sem);
+    }
+  }
+#else /* LWIP_NETCONN_FULLDUPLEX */
+  if (((state != NETCONN_NONE) &&
+       (state != NETCONN_LISTEN) &&
+       (state != NETCONN_CONNECT)) ||
+      ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) {
+    /* This means either a blocking write or blocking connect is running
+       (nonblocking write returns and sets state to NONE) */
+    msg->err = ERR_INPROGRESS;
+  } else
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+  {
+    LWIP_ASSERT("blocking connect in progress",
+                (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn));
+    msg->err = ERR_OK;
+#if LWIP_NETCONN_FULLDUPLEX
+    /* Mark mboxes invalid */
+    netconn_mark_mbox_invalid(msg->conn);
+#else /* LWIP_NETCONN_FULLDUPLEX */
+    netconn_drain(msg->conn);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+    if (msg->conn->pcb.tcp != NULL) {
+
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+        case NETCONN_RAW:
+          raw_remove(msg->conn->pcb.raw);
+          break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+        case NETCONN_UDP:
+          msg->conn->pcb.udp->recv_arg = NULL;
+          udp_remove(msg->conn->pcb.udp);
+          break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+        case NETCONN_TCP:
+          LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL);
+          msg->conn->state = NETCONN_CLOSE;
+          msg->msg.sd.shut = NETCONN_SHUT_RDWR;
+          msg->conn->current_msg = msg;
+#if LWIP_TCPIP_CORE_LOCKING
+          if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) {
+            LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE);
+            UNLOCK_TCPIP_CORE();
+            sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+            LOCK_TCPIP_CORE();
+            LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+          }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+          lwip_netconn_do_close_internal(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+          /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing
+             the application thread, so we can return at this point! */
+          return;
+#endif /* LWIP_TCP */
+        default:
+          break;
+      }
+      msg->conn->pcb.tcp = NULL;
+    }
+    /* tcp netconns don't come here! */
+
+    /* @todo: this lets select make the socket readable and writable,
+       which is wrong! errfd instead? */
+    API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+    API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+  }
+  if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) {
+    TCPIP_APIMSG_ACK(msg);
+  }
+}
+
+/**
+ * Bind a pcb contained in a netconn
+ * Called from netconn_bind.
+ *
+ * @param m the api_msg pointing to the connection and containing
+ *          the IP address and port to bind to
+ */
+void
+lwip_netconn_do_bind(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+  err_t err;
+
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr));
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port);
+        break;
+#endif /* LWIP_TCP */
+      default:
+        err = ERR_VAL;
+        break;
+    }
+  } else {
+    err = ERR_VAL;
+  }
+  msg->err = err;
+  TCPIP_APIMSG_ACK(msg);
+}
+/**
+ * Bind a pcb contained in a netconn to an interface
+ * Called from netconn_bind_if.
+ *
+ * @param m the api_msg pointing to the connection and containing
+ *          the IP address and port to bind to
+ */
+void
+lwip_netconn_do_bind_if(void *m)
+{
+  struct netif *netif;
+  struct api_msg *msg = (struct api_msg *)m;
+  err_t err;
+
+  netif = netif_get_by_index(msg->msg.bc.if_idx);
+
+  if ((netif != NULL) && (msg->conn->pcb.tcp != NULL)) {
+    err = ERR_OK;
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        raw_bind_netif(msg->conn->pcb.raw, netif);
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        udp_bind_netif(msg->conn->pcb.udp, netif);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        tcp_bind_netif(msg->conn->pcb.tcp, netif);
+        break;
+#endif /* LWIP_TCP */
+      default:
+        err = ERR_VAL;
+        break;
+    }
+  } else {
+    err = ERR_VAL;
+  }
+  msg->err = err;
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * TCP callback function if a connection (opened by tcp_connect/lwip_netconn_do_connect) has
+ * been established (or reset by the remote host).
+ *
+ * @see tcp.h (struct tcp_pcb.connected) for parameters and return values
+ */
+static err_t
+lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+  int was_blocking;
+  sys_sem_t *op_completed_sem = NULL;
+
+  LWIP_UNUSED_ARG(pcb);
+
+  conn = (struct netconn *)arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT);
+  LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect",
+              (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn));
+
+  if (conn->current_msg != NULL) {
+    conn->current_msg->err = err;
+    op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+  }
+  if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) {
+    setup_tcp(conn);
+  }
+  was_blocking = !IN_NONBLOCKING_CONNECT(conn);
+  SET_NONBLOCKING_CONNECT(conn, 0);
+  LWIP_ASSERT("blocking connect state error",
+              (was_blocking && op_completed_sem != NULL) ||
+              (!was_blocking && op_completed_sem == NULL));
+  conn->current_msg = NULL;
+  conn->state = NETCONN_NONE;
+  API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0);
+
+  if (was_blocking) {
+    sys_sem_signal(op_completed_sem);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Connect a pcb contained inside a netconn
+ * Called from netconn_connect.
+ *
+ * @param m the api_msg pointing to the connection and containing
+ *          the IP address and port to connect to
+ */
+void
+lwip_netconn_do_connect(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+  err_t err;
+
+  if (msg->conn->pcb.tcp == NULL) {
+    /* This may happen when calling netconn_connect() a second time */
+    err = ERR_CLSD;
+  } else {
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr));
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        /* Prevent connect while doing any other action. */
+        if (msg->conn->state == NETCONN_CONNECT) {
+          err = ERR_ALREADY;
+        } else if (msg->conn->state != NETCONN_NONE) {
+          err = ERR_ISCONN;
+        } else {
+          setup_tcp(msg->conn);
+          err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr),
+                            msg->msg.bc.port, lwip_netconn_do_connected);
+          if (err == ERR_OK) {
+            u8_t non_blocking = netconn_is_nonblocking(msg->conn);
+            msg->conn->state = NETCONN_CONNECT;
+            SET_NONBLOCKING_CONNECT(msg->conn, non_blocking);
+            if (non_blocking) {
+              err = ERR_INPROGRESS;
+            } else {
+              msg->conn->current_msg = msg;
+              /* sys_sem_signal() is called from lwip_netconn_do_connected (or err_tcp()),
+                 when the connection is established! */
+#if LWIP_TCPIP_CORE_LOCKING
+              LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT);
+              UNLOCK_TCPIP_CORE();
+              sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+              LOCK_TCPIP_CORE();
+              LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+              return;
+            }
+          }
+        }
+        break;
+#endif /* LWIP_TCP */
+      default:
+        LWIP_ERROR("Invalid netconn type", 0, do {
+          err = ERR_VAL;
+        } while (0));
+        break;
+    }
+  }
+  msg->err = err;
+  /* For all other protocols, netconn_connect() calls netconn_apimsg(),
+     so use TCPIP_APIMSG_ACK() here. */
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Disconnect a pcb contained inside a netconn
+ * Only used for UDP netconns.
+ * Called from netconn_disconnect.
+ *
+ * @param m the api_msg pointing to the connection to disconnect
+ */
+void
+lwip_netconn_do_disconnect(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+#if LWIP_UDP
+  if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+    udp_disconnect(msg->conn->pcb.udp);
+    msg->err = ERR_OK;
+  } else
+#endif /* LWIP_UDP */
+  {
+    msg->err = ERR_VAL;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * Set a TCP pcb contained in a netconn into listen mode
+ * Called from netconn_listen.
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_listen(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+  err_t err;
+
+  if (msg->conn->pcb.tcp != NULL) {
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) {
+      if (msg->conn->state == NETCONN_NONE) {
+        struct tcp_pcb *lpcb;
+        if (msg->conn->pcb.tcp->state != CLOSED) {
+          /* connection is not closed, cannot listen */
+          err = ERR_VAL;
+        } else {
+          u8_t backlog;
+#if TCP_LISTEN_BACKLOG
+          backlog = msg->msg.lb.backlog;
+#else  /* TCP_LISTEN_BACKLOG */
+          backlog = TCP_DEFAULT_LISTEN_BACKLOG;
+#endif /* TCP_LISTEN_BACKLOG */
+#if LWIP_IPV4 && LWIP_IPV6
+          /* "Socket API like" dual-stack support: If IP to listen to is IP6_ADDR_ANY,
+            * and NETCONN_FLAG_IPV6_V6ONLY is NOT set, use IP_ANY_TYPE to listen
+            */
+          if (ip_addr_cmp(&msg->conn->pcb.ip->local_ip, IP6_ADDR_ANY) &&
+              (netconn_get_ipv6only(msg->conn) == 0)) {
+            /* change PCB type to IPADDR_TYPE_ANY */
+            IP_SET_TYPE_VAL(msg->conn->pcb.tcp->local_ip,  IPADDR_TYPE_ANY);
+            IP_SET_TYPE_VAL(msg->conn->pcb.tcp->remote_ip, IPADDR_TYPE_ANY);
+          }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+          lpcb = tcp_listen_with_backlog_and_err(msg->conn->pcb.tcp, backlog, &err);
+
+          if (lpcb == NULL) {
+            /* in this case, the old pcb is still allocated */
+          } else {
+            /* delete the recvmbox and allocate the acceptmbox */
+            if (sys_mbox_valid(&msg->conn->recvmbox)) {
+              /** @todo: should we drain the recvmbox here? */
+              sys_mbox_free(&msg->conn->recvmbox);
+              sys_mbox_set_invalid(&msg->conn->recvmbox);
+            }
+            err = ERR_OK;
+            if (!sys_mbox_valid(&msg->conn->acceptmbox)) {
+              err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE);
+            }
+            if (err == ERR_OK) {
+              msg->conn->state = NETCONN_LISTEN;
+              msg->conn->pcb.tcp = lpcb;
+              tcp_arg(msg->conn->pcb.tcp, msg->conn);
+              tcp_accept(msg->conn->pcb.tcp, accept_function);
+            } else {
+              /* since the old pcb is already deallocated, free lpcb now */
+              tcp_close(lpcb);
+              msg->conn->pcb.tcp = NULL;
+            }
+          }
+        }
+      } else if (msg->conn->state == NETCONN_LISTEN) {
+        /* already listening, allow updating of the backlog */
+        err = ERR_OK;
+        tcp_backlog_set(msg->conn->pcb.tcp, msg->msg.lb.backlog);
+      } else {
+        err = ERR_CONN;
+      }
+    } else {
+      err = ERR_ARG;
+    }
+  } else {
+    err = ERR_CONN;
+  }
+  msg->err = err;
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Send some data on a RAW or UDP pcb contained in a netconn
+ * Called from netconn_send
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_send(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  err_t err = netconn_err(msg->conn);
+  if (err == ERR_OK) {
+    if (msg->conn->pcb.tcp != NULL) {
+      switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+        case NETCONN_RAW:
+          if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) {
+            err = raw_send(msg->conn->pcb.raw, msg->msg.b->p);
+          } else {
+            err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr);
+          }
+          break;
+#endif
+#if LWIP_UDP
+        case NETCONN_UDP:
+#if LWIP_CHECKSUM_ON_COPY
+          if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) {
+            err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p,
+                                  msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum);
+          } else {
+            err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p,
+                                    &msg->msg.b->addr, msg->msg.b->port,
+                                    msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum);
+          }
+#else /* LWIP_CHECKSUM_ON_COPY */
+          if (ip_addr_isany_val(msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) {
+            err = udp_send(msg->conn->pcb.udp, msg->msg.b->p);
+          } else {
+            err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port);
+          }
+#endif /* LWIP_CHECKSUM_ON_COPY */
+          break;
+#endif /* LWIP_UDP */
+        default:
+          err = ERR_CONN;
+          break;
+      }
+    } else {
+      err = ERR_CONN;
+    }
+  }
+  msg->err = err;
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_TCP
+/**
+ * Indicate data has been received from a TCP pcb contained in a netconn
+ * Called from netconn_recv
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_recv(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  msg->err = ERR_OK;
+  if (msg->conn->pcb.tcp != NULL) {
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) {
+      size_t remaining = msg->msg.r.len;
+      do {
+        u16_t recved = (u16_t)((remaining > 0xffff) ? 0xffff : remaining);
+        tcp_recved(msg->conn->pcb.tcp, recved);
+        remaining -= recved;
+      } while (remaining != 0);
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if TCP_LISTEN_BACKLOG
+/** Indicate that a TCP pcb has been accepted
+ * Called from netconn_accept
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_accepted(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  msg->err = ERR_OK;
+  if (msg->conn->pcb.tcp != NULL) {
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) {
+      tcp_backlog_accepted(msg->conn->pcb.tcp);
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* TCP_LISTEN_BACKLOG */
+
+/**
+ * See if more data needs to be written from a previous call to netconn_write.
+ * Called initially from lwip_netconn_do_write. If the first call can't send all data
+ * (because of low memory or empty send-buffer), this function is called again
+ * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the
+ * blocking application thread (waiting in netconn_write) is released.
+ *
+ * @param conn netconn (that is currently in state NETCONN_WRITE) to process
+ * @return ERR_OK
+ *         ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished
+ */
+static err_t
+lwip_netconn_do_writemore(struct netconn *conn  WRITE_DELAYED_PARAM)
+{
+  err_t err;
+  const void *dataptr;
+  u16_t len, available;
+  u8_t write_finished = 0;
+  size_t diff;
+  u8_t dontblock;
+  u8_t apiflags;
+  u8_t write_more;
+
+  LWIP_ASSERT("conn != NULL", conn != NULL);
+  LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE));
+  LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL);
+  LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL);
+  LWIP_ASSERT("conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len",
+              conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len);
+  LWIP_ASSERT("conn->current_msg->msg.w.vector_cnt > 0", conn->current_msg->msg.w.vector_cnt > 0);
+
+  apiflags = conn->current_msg->msg.w.apiflags;
+  dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK);
+
+#if LWIP_SO_SNDTIMEO
+  if ((conn->send_timeout != 0) &&
+      ((s32_t)(Milliseconds() - conn->current_msg->msg.w.time_started) >= conn->send_timeout)) {
+    write_finished = 1;
+    if (conn->current_msg->msg.w.offset == 0) {
+      /* nothing has been written */
+      err = ERR_WOULDBLOCK;
+    } else {
+      /* partial write */
+      err = ERR_OK;
+    }
+  } else
+#endif /* LWIP_SO_SNDTIMEO */
+  {
+    do {
+      dataptr = (const u8_t *)conn->current_msg->msg.w.vector->ptr + conn->current_msg->msg.w.vector_off;
+      diff = conn->current_msg->msg.w.vector->len - conn->current_msg->msg.w.vector_off;
+      if (diff > 0xffffUL) { /* max_u16_t */
+        len = 0xffff;
+        apiflags |= TCP_WRITE_FLAG_MORE;
+      } else {
+        len = (u16_t)diff;
+      }
+      available = tcp_sndbuf(conn->pcb.tcp);
+      if (available < len) {
+        /* don't try to write more than sendbuf */
+        len = available;
+        if (dontblock) {
+          if (!len) {
+            /* set error according to partial write or not */
+            err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK;
+            goto err_mem;
+          }
+        } else {
+          apiflags |= TCP_WRITE_FLAG_MORE;
+        }
+      }
+      LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!",
+                  ((conn->current_msg->msg.w.vector_off + len) <= conn->current_msg->msg.w.vector->len));
+      /* we should loop around for more sending in the following cases:
+           1) We couldn't finish the current vector because of 16-bit size limitations.
+              tcp_write() and tcp_sndbuf() both are limited to 16-bit sizes
+           2) We are sending the remainder of the current vector and have more */
+      if ((len == 0xffff && diff > 0xffffUL) ||
+          (len == (u16_t)diff && conn->current_msg->msg.w.vector_cnt > 1)) {
+        write_more = 1;
+        apiflags |= TCP_WRITE_FLAG_MORE;
+      } else {
+        write_more = 0;
+      }
+      err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags);
+      if (err == ERR_OK) {
+        conn->current_msg->msg.w.offset += len;
+        conn->current_msg->msg.w.vector_off += len;
+        /* check if current vector is finished */
+        if (conn->current_msg->msg.w.vector_off == conn->current_msg->msg.w.vector->len) {
+          conn->current_msg->msg.w.vector_cnt--;
+          /* if we have additional vectors, move on to them */
+          if (conn->current_msg->msg.w.vector_cnt > 0) {
+            conn->current_msg->msg.w.vector++;
+            conn->current_msg->msg.w.vector_off = 0;
+          }
+        }
+      }
+    } while (write_more && err == ERR_OK);
+    /* if OK or memory error, check available space */
+    if ((err == ERR_OK) || (err == ERR_MEM)) {
+err_mem:
+      if (dontblock && (conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len)) {
+        /* non-blocking write did not write everything: mark the pcb non-writable
+           and let poll_tcp check writable space to mark the pcb writable again */
+        API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0);
+        conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE;
+      } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) ||
+                 (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) {
+        /* The queued byte- or pbuf-count exceeds the configured low-water limit,
+           let select mark this pcb as non-writable. */
+        API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0);
+      }
+    }
+
+    if (err == ERR_OK) {
+      err_t out_err;
+      if ((conn->current_msg->msg.w.offset == conn->current_msg->msg.w.len) || dontblock) {
+        /* return sent length (caller reads length from msg.w.offset) */
+        write_finished = 1;
+      }
+      out_err = tcp_output(conn->pcb.tcp);
+      if (out_err == ERR_RTE) {
+        /* If tcp_output fails because no route is found,
+           don't try writing any more but return the error
+           to the application thread. */
+        err = out_err;
+        write_finished = 1;
+      }
+    } else if (err == ERR_MEM) {
+      /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called.
+         For blocking sockets, we do NOT return to the application
+         thread, since ERR_MEM is only a temporary error! Non-blocking
+         will remain non-writable until sent_tcp/poll_tcp is called */
+
+      /* tcp_write returned ERR_MEM, try tcp_output anyway */
+      err_t out_err = tcp_output(conn->pcb.tcp);
+      if (out_err == ERR_RTE) {
+        /* If tcp_output fails because no route is found,
+           don't try writing any more but return the error
+           to the application thread. */
+        err = out_err;
+        write_finished = 1;
+      } else if (dontblock) {
+        /* non-blocking write is done on ERR_MEM, set error according
+           to partial write or not */
+        err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK;
+        write_finished = 1;
+      }
+    } else {
+      /* On errors != ERR_MEM, we don't try writing any more but return
+         the error to the application thread. */
+      write_finished = 1;
+    }
+  }
+  if (write_finished) {
+    /* everything was written: set back connection state
+       and back to application task */
+    sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg);
+    conn->current_msg->err = err;
+    conn->current_msg = NULL;
+    conn->state = NETCONN_NONE;
+#if LWIP_TCPIP_CORE_LOCKING
+    if (delayed)
+#endif
+    {
+      sys_sem_signal(op_completed_sem);
+    }
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  else {
+    return ERR_MEM;
+  }
+#endif
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+/**
+ * Send some data on a TCP pcb contained in a netconn
+ * Called from netconn_write
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_write(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  err_t err = netconn_err(msg->conn);
+  if (err == ERR_OK) {
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) {
+#if LWIP_TCP
+      if (msg->conn->state != NETCONN_NONE) {
+        /* netconn is connecting, closing or in blocking write */
+        err = ERR_INPROGRESS;
+      } else if (msg->conn->pcb.tcp != NULL) {
+        msg->conn->state = NETCONN_WRITE;
+        /* set all the variables used by lwip_netconn_do_writemore */
+        LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL);
+        LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0);
+        msg->conn->current_msg = msg;
+#if LWIP_TCPIP_CORE_LOCKING
+        if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) {
+          LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE);
+          UNLOCK_TCPIP_CORE();
+          sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+          LOCK_TCPIP_CORE();
+          LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE);
+        }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+        lwip_netconn_do_writemore(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+        /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG
+           since lwip_netconn_do_writemore ACKs it! */
+        return;
+      } else {
+        err = ERR_CONN;
+      }
+#else /* LWIP_TCP */
+      err = ERR_VAL;
+#endif /* LWIP_TCP */
+#if (LWIP_UDP || LWIP_RAW)
+    } else {
+      err = ERR_VAL;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+    }
+  }
+  msg->err = err;
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Return a connection's local or remote address
+ * Called from netconn_getaddr
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_getaddr(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  if (msg->conn->pcb.ip != NULL) {
+    if (msg->msg.ad.local) {
+      ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr),
+                   msg->conn->pcb.ip->local_ip);
+    } else {
+      ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr),
+                   msg->conn->pcb.ip->remote_ip);
+    }
+
+    msg->err = ERR_OK;
+    switch (NETCONNTYPE_GROUP(msg->conn->type)) {
+#if LWIP_RAW
+      case NETCONN_RAW:
+        if (msg->msg.ad.local) {
+          API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.raw->protocol;
+        } else {
+          /* return an error as connecting is only a helper for upper layers */
+          msg->err = ERR_CONN;
+        }
+        break;
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+      case NETCONN_UDP:
+        if (msg->msg.ad.local) {
+          API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->local_port;
+        } else {
+          if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) {
+            msg->err = ERR_CONN;
+          } else {
+            API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port;
+          }
+        }
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case NETCONN_TCP:
+        if ((msg->msg.ad.local == 0) &&
+            ((msg->conn->pcb.tcp->state == CLOSED) || (msg->conn->pcb.tcp->state == LISTEN))) {
+          /* pcb is not connected and remote name is requested */
+          msg->err = ERR_CONN;
+        } else {
+          API_EXPR_DEREF(msg->msg.ad.port) = (msg->msg.ad.local ? msg->conn->pcb.tcp->local_port : msg->conn->pcb.tcp->remote_port);
+        }
+        break;
+#endif /* LWIP_TCP */
+      default:
+        LWIP_ASSERT("invalid netconn_type", 0);
+        break;
+    }
+  } else {
+    msg->err = ERR_CONN;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+/**
+ * Close or half-shutdown a TCP pcb contained in a netconn
+ * Called from netconn_close
+ * In contrast to closing sockets, the netconn is not deallocated.
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_close(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+#if LWIP_TCP
+  enum netconn_state state = msg->conn->state;
+  /* First check if this is a TCP netconn and if it is in a correct state
+      (LISTEN doesn't support half shutdown) */
+  if ((msg->conn->pcb.tcp != NULL) &&
+      (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) &&
+      ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) {
+    /* Check if we are in a connected state */
+    if (state == NETCONN_CONNECT) {
+      /* TCP connect in progress: cannot shutdown */
+      msg->err = ERR_CONN;
+    } else if (state == NETCONN_WRITE) {
+#if LWIP_NETCONN_FULLDUPLEX
+      if (msg->msg.sd.shut & NETCONN_SHUT_WR) {
+        /* close requested, abort running write */
+        sys_sem_t *write_completed_sem;
+        LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL);
+        write_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg);
+        msg->conn->current_msg->err = ERR_CLSD;
+        msg->conn->current_msg = NULL;
+        msg->conn->state = NETCONN_NONE;
+        state = NETCONN_NONE;
+        sys_sem_signal(write_completed_sem);
+      } else {
+        LWIP_ASSERT("msg->msg.sd.shut == NETCONN_SHUT_RD", msg->msg.sd.shut == NETCONN_SHUT_RD);
+        /* In this case, let the write continue and do not interfere with
+           conn->current_msg or conn->state! */
+        msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0);
+      }
+    }
+    if (state == NETCONN_NONE) {
+#else /* LWIP_NETCONN_FULLDUPLEX */
+      msg->err = ERR_INPROGRESS;
+    } else {
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      if (msg->msg.sd.shut & NETCONN_SHUT_RD) {
+#if LWIP_NETCONN_FULLDUPLEX
+        /* Mark mboxes invalid */
+        netconn_mark_mbox_invalid(msg->conn);
+#else /* LWIP_NETCONN_FULLDUPLEX */
+        netconn_drain(msg->conn);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+      }
+      LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL);
+      msg->conn->state = NETCONN_CLOSE;
+      msg->conn->current_msg = msg;
+#if LWIP_TCPIP_CORE_LOCKING
+      if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) {
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE);
+        UNLOCK_TCPIP_CORE();
+        sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0);
+        LOCK_TCPIP_CORE();
+        LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE);
+      }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+      lwip_netconn_do_close_internal(msg->conn);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+      /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */
+      return;
+    }
+  } else
+#endif /* LWIP_TCP */
+  {
+    msg->err = ERR_CONN;
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+/**
+ * Join multicast groups for UDP netconns.
+ * Called from netconn_join_leave_group
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_join_leave_group(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+
+  msg->err = ERR_CONN;
+  if (msg->conn->pcb.tcp != NULL) {
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+#if LWIP_UDP
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+      if (NETCONNTYPE_ISIPV6(msg->conn->type)) {
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->err = mld6_joingroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)),
+                                    ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        } else {
+          msg->err = mld6_leavegroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)),
+                                     ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        }
+      } else
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+      {
+#if LWIP_IGMP
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->err = igmp_joingroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)),
+                                    ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        } else {
+          msg->err = igmp_leavegroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)),
+                                     ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        }
+#endif /* LWIP_IGMP */
+      }
+#endif /* LWIP_UDP */
+#if (LWIP_TCP || LWIP_RAW)
+    } else {
+      msg->err = ERR_VAL;
+#endif /* (LWIP_TCP || LWIP_RAW) */
+    }
+  }
+  TCPIP_APIMSG_ACK(msg);
+}
+/**
+ * Join multicast groups for UDP netconns.
+ * Called from netconn_join_leave_group_netif
+ *
+ * @param m the api_msg pointing to the connection
+ */
+void
+lwip_netconn_do_join_leave_group_netif(void *m)
+{
+  struct api_msg *msg = (struct api_msg *)m;
+  struct netif *netif;
+
+  netif = netif_get_by_index(msg->msg.jl.if_idx);
+  if (netif == NULL) {
+    msg->err = ERR_IF;
+    goto done;
+  }
+
+  msg->err = ERR_CONN;
+  if (msg->conn->pcb.tcp != NULL) {
+    if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) {
+#if LWIP_UDP
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+      if (NETCONNTYPE_ISIPV6(msg->conn->type)) {
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->err = mld6_joingroup_netif(netif,
+                                          ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        } else {
+          msg->err = mld6_leavegroup_netif(netif,
+                                           ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        }
+      } else
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+      {
+#if LWIP_IGMP
+        if (msg->msg.jl.join_or_leave == NETCONN_JOIN) {
+          msg->err = igmp_joingroup_netif(netif,
+                                          ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        } else {
+          msg->err = igmp_leavegroup_netif(netif,
+                                           ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr)));
+        }
+#endif /* LWIP_IGMP */
+      }
+#endif /* LWIP_UDP */
+#if (LWIP_TCP || LWIP_RAW)
+    } else {
+      msg->err = ERR_VAL;
+#endif /* (LWIP_TCP || LWIP_RAW) */
+    }
+  }
+
+done:
+  TCPIP_APIMSG_ACK(msg);
+}
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+/**
+ * Callback function that is called when DNS name is resolved
+ * (or on timeout). A waiting application thread is waked up by
+ * signaling the semaphore.
+ */
+static void
+lwip_netconn_do_dns_found(const char *name, const ip_addr_t *ipaddr, void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg *)arg;
+
+  /* we trust the internal implementation to be correct :-) */
+  LWIP_UNUSED_ARG(name);
+
+  if (ipaddr == NULL) {
+    /* timeout or memory error */
+    API_EXPR_DEREF(msg->err) = ERR_VAL;
+  } else {
+    /* address was resolved */
+    API_EXPR_DEREF(msg->err) = ERR_OK;
+    API_EXPR_DEREF(msg->addr) = *ipaddr;
+  }
+  /* wake up the application task waiting in netconn_gethostbyname */
+  sys_sem_signal(API_EXPR_REF_SEM(msg->sem));
+}
+
+/**
+ * Execute a DNS query
+ * Called from netconn_gethostbyname
+ *
+ * @param arg the dns_api_msg pointing to the query
+ */
+void
+lwip_netconn_do_gethostbyname(void *arg)
+{
+  struct dns_api_msg *msg = (struct dns_api_msg *)arg;
+  u8_t addrtype =
+#if LWIP_IPV4 && LWIP_IPV6
+    msg->dns_addrtype;
+#else
+    LWIP_DNS_ADDRTYPE_DEFAULT;
+#endif
+
+  API_EXPR_DEREF(msg->err) = dns_gethostbyname_addrtype(msg->name,
+                             API_EXPR_REF(msg->addr), lwip_netconn_do_dns_found, msg, addrtype);
+#if LWIP_TCPIP_CORE_LOCKING
+  /* For core locking, only block if we need to wait for answer/timeout */
+  if (API_EXPR_DEREF(msg->err) == ERR_INPROGRESS) {
+    UNLOCK_TCPIP_CORE();
+    sys_sem_wait(API_EXPR_REF_SEM(msg->sem));
+    LOCK_TCPIP_CORE();
+    LWIP_ASSERT("do_gethostbyname still in progress!!", API_EXPR_DEREF(msg->err) != ERR_INPROGRESS);
+  }
+#else /* LWIP_TCPIP_CORE_LOCKING */
+  if (API_EXPR_DEREF(msg->err) != ERR_INPROGRESS) {
+    /* on error or immediate success, wake up the application
+     * task waiting in netconn_gethostbyname */
+    sys_sem_signal(API_EXPR_REF_SEM(msg->sem));
+  }
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+}
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_NETCONN */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/err.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/err.c
new file mode 100644
index 000000000..dd2b62dab
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/err.c
@@ -0,0 +1,115 @@
+/**
+ * @file
+ * Error Management module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/err.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+
+#include "lwip/errno.h"
+
+#if !NO_SYS
+/** Table to quickly map an lwIP error (err_t) to a socket error
+  * by using -err as an index */
+static const int err_to_errno_table[] = {
+  0,             /* ERR_OK          0      No error, everything OK. */
+  ENOMEM,        /* ERR_MEM        -1      Out of memory error.     */
+  ENOBUFS,       /* ERR_BUF        -2      Buffer error.            */
+  EWOULDBLOCK,   /* ERR_TIMEOUT    -3      Timeout                  */
+  EHOSTUNREACH,  /* ERR_RTE        -4      Routing problem.         */
+  EINPROGRESS,   /* ERR_INPROGRESS -5      Operation in progress    */
+  EINVAL,        /* ERR_VAL        -6      Illegal value.           */
+  EWOULDBLOCK,   /* ERR_WOULDBLOCK -7      Operation would block.   */
+  EADDRINUSE,    /* ERR_USE        -8      Address in use.          */
+  EALREADY,      /* ERR_ALREADY    -9      Already connecting.      */
+  EISCONN,       /* ERR_ISCONN     -10     Conn already established.*/
+  ENOTCONN,      /* ERR_CONN       -11     Not connected.           */
+  -1,            /* ERR_IF         -12     Low-level netif error    */
+  ECONNABORTED,  /* ERR_ABRT       -13     Connection aborted.      */
+  ECONNRESET,    /* ERR_RST        -14     Connection reset.        */
+  ENOTCONN,      /* ERR_CLSD       -15     Connection closed.       */
+  EIO            /* ERR_ARG        -16     Illegal argument.        */
+};
+
+int
+err_to_errno(err_t err)
+{
+  if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_to_errno_table))) {
+    return EIO;
+  }
+  return err_to_errno_table[-err];
+}
+#endif /* !NO_SYS */
+
+#ifdef LWIP_DEBUG
+
+static const char *err_strerr[] = {
+  "Ok.",                    /* ERR_OK          0  */
+  "Out of memory error.",   /* ERR_MEM        -1  */
+  "Buffer error.",          /* ERR_BUF        -2  */
+  "Timeout.",               /* ERR_TIMEOUT    -3  */
+  "Routing problem.",       /* ERR_RTE        -4  */
+  "Operation in progress.", /* ERR_INPROGRESS -5  */
+  "Illegal value.",         /* ERR_VAL        -6  */
+  "Operation would block.", /* ERR_WOULDBLOCK -7  */
+  "Address in use.",        /* ERR_USE        -8  */
+  "Already connecting.",    /* ERR_ALREADY    -9  */
+  "Already connected.",     /* ERR_ISCONN     -10 */
+  "Not connected.",         /* ERR_CONN       -11 */
+  "Low-level netif error.", /* ERR_IF         -12 */
+  "Connection aborted.",    /* ERR_ABRT       -13 */
+  "Connection reset.",      /* ERR_RST        -14 */
+  "Connection closed.",     /* ERR_CLSD       -15 */
+  "Illegal argument."       /* ERR_ARG        -16 */
+};
+
+/**
+ * Convert an lwip internal error to a string representation.
+ *
+ * @param err an lwip internal err_t
+ * @return a string representation for err
+ */
+const char *
+lwip_strerr(err_t err)
+{
+  if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_strerr))) {
+    return "Unknown error.";
+  }
+  return err_strerr[-err];
+}
+
+#endif /* LWIP_DEBUG */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/if_api.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/if_api.c
new file mode 100644
index 000000000..8e094d090
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/if_api.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ * Interface Identification APIs from:
+ *              RFC 3493: Basic Socket Interface Extensions for IPv6
+ *                  Section 4: Interface Identification
+ *
+ * @defgroup if_api Interface Identification API
+ * @ingroup socket
+ */
+
+/*
+ * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. <joel.cunningham@garmin.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Joel Cunningham <joel.cunningham@me.com>
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET
+
+#include "lwip/errno.h"
+#include "lwip/if_api.h"
+#include "lwip/netifapi.h"
+#include "lwip/priv/sockets_priv.h"
+
+/**
+ * @ingroup if_api
+ * Maps an interface index to its corresponding name.
+ * @param ifindex interface index
+ * @param ifname shall point to a buffer of at least {IF_NAMESIZE} bytes
+ * @return If ifindex is an interface index, then the function shall return the
+ * value supplied in ifname, which points to a buffer now containing the interface name.
+ * Otherwise, the function shall return a NULL pointer.
+ */
+char *
+lwip_if_indextoname(unsigned int ifindex, char *ifname)
+{
+#if LWIP_NETIF_API
+  if (ifindex <= 0xff) {
+    err_t err = netifapi_netif_index_to_name((u8_t)ifindex, ifname);
+    if (!err && ifname[0] != '\0') {
+      return ifname;
+    }
+  }
+#else /* LWIP_NETIF_API */
+  LWIP_UNUSED_ARG(ifindex);
+  LWIP_UNUSED_ARG(ifname);
+#endif /* LWIP_NETIF_API */
+  set_errno(ENXIO);
+  return NULL;
+}
+
+/**
+ * @ingroup if_api
+ * Returs the interface index corresponding to name ifname.
+ * @param ifname Interface name
+ * @return The corresponding index if ifname is the name of an interface;
+ * otherwise, zero.
+ */
+unsigned int
+lwip_if_nametoindex(const char *ifname)
+{
+#if LWIP_NETIF_API
+  err_t err;
+  u8_t idx;
+
+  err = netifapi_netif_name_to_index(ifname, &idx);
+  if (!err) {
+    return idx;
+  }
+#else /* LWIP_NETIF_API */
+  LWIP_UNUSED_ARG(ifname);
+#endif /* LWIP_NETIF_API */
+  return 0; /* invalid index */
+}
+
+#endif /* LWIP_SOCKET */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netbuf.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netbuf.c
new file mode 100644
index 000000000..3b910de10
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netbuf.c
@@ -0,0 +1,250 @@
+/**
+ * @file
+ * Network buffer management
+ *
+ * @defgroup netbuf Network buffers
+ * @ingroup netconn
+ * Network buffer descriptor for @ref netconn. Based on @ref pbuf internally
+ * to avoid copying data around.\n
+ * Buffers must not be shared accross multiple threads, all functions except
+ * netbuf_new() and netbuf_delete() are not thread-safe.
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netbuf.h"
+#include "lwip/memp.h"
+
+#include <string.h>
+
+/**
+ * @ingroup netbuf
+ * Create (allocate) and initialize a new netbuf.
+ * The netbuf doesn't yet contain a packet buffer!
+ *
+ * @return a pointer to a new netbuf
+ *         NULL on lack of memory
+ */
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = (struct netbuf *)memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    memset(buf, 0, sizeof(struct netbuf));
+  }
+  return buf;
+}
+
+/**
+ * @ingroup netbuf
+ * Deallocate a netbuf allocated by netbuf_new().
+ *
+ * @param buf pointer to a netbuf allocated by netbuf_new()
+ */
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+/**
+ * @ingroup netbuf
+ * Allocate memory for a packet buffer for a given netbuf.
+ *
+ * @param buf the netbuf for which to allocate a packet buffer
+ * @param size the size of the packet buffer to allocate
+ * @return pointer to the allocated memory
+ *         NULL if no memory could be allocated
+ */
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;);
+
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+    return NULL;
+  }
+  LWIP_ASSERT("check that first pbuf can hold size",
+              (buf->p->len >= size));
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+/**
+ * @ingroup netbuf
+ * Free the packet buffer included in a netbuf
+ *
+ * @param buf pointer to the netbuf which contains the packet buffer to free
+ */
+void
+netbuf_free(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+#if LWIP_CHECKSUM_ON_COPY
+  buf->flags = 0;
+  buf->toport_chksum = 0;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+}
+
+/**
+ * @ingroup netbuf
+ * Let a netbuf reference existing (non-volatile) data.
+ *
+ * @param buf netbuf which should reference the data
+ * @param dataptr pointer to the data to reference
+ * @param size size of the data
+ * @return ERR_OK if data is referenced
+ *         ERR_MEM if data couldn't be referenced due to lack of memory
+ */
+err_t
+netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size)
+{
+  LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;);
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  if (buf->p == NULL) {
+    buf->ptr = NULL;
+    return ERR_MEM;
+  }
+  ((struct pbuf_rom *)buf->p)->payload = dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+  return ERR_OK;
+}
+
+/**
+ * @ingroup netbuf
+ * Chain one netbuf to another (@see pbuf_chain)
+ *
+ * @param head the first netbuf
+ * @param tail netbuf to chain after head, freed by this function, may not be reference after returning
+ */
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  LWIP_ERROR("netbuf_chain: invalid head", (head != NULL), return;);
+  LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;);
+  pbuf_cat(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+/**
+ * @ingroup netbuf
+ * Get the data pointer and length of the data inside a netbuf.
+ *
+ * @param buf netbuf to get the data from
+ * @param dataptr pointer to a void pointer where to store the data pointer
+ * @param len pointer to an u16_t where the length of the data is stored
+ * @return ERR_OK if the information was retrieved,
+ *         ERR_BUF on error.
+ */
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;);
+  LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;);
+
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+/**
+ * @ingroup netbuf
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the next part.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ * @return -1 if there is no next part
+ *         1  if moved to the next part but now there is no next part
+ *         0  if moved to the next part and there are still more parts
+ */
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_next: invalid buf", (buf != NULL), return -1;);
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+/**
+ * @ingroup netbuf
+ * Move the current data pointer of a packet buffer contained in a netbuf
+ * to the beginning of the packet.
+ * The packet buffer itself is not modified.
+ *
+ * @param buf the netbuf to modify
+ */
+void
+netbuf_first(struct netbuf *buf)
+{
+  LWIP_ERROR("netbuf_first: invalid buf", (buf != NULL), return;);
+  buf->ptr = buf->p;
+}
+
+#endif /* LWIP_NETCONN */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netdb.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netdb.c
new file mode 100644
index 000000000..87714259d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netdb.c
@@ -0,0 +1,414 @@
+/**
+ * @file
+ * API functions for name resolving
+ *
+ * @defgroup netdbapi NETDB API
+ * @ingroup socket
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/netdb.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/err.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/api.h"
+#include "lwip/dns.h"
+
+#include <string.h> /* memset */
+#include <stdlib.h> /* atoi */
+
+/** helper struct for gethostbyname_r to access the char* buffer */
+struct gethostbyname_r_helper {
+  ip_addr_t *addr_list[2];
+  ip_addr_t addr;
+  char *aliases;
+};
+
+/** h_errno is exported in netdb.h for access by applications. */
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */
+
+/** define "hostent" variables storage: 0 if we use a static (but unprotected)
+ * set of variables for lwip_gethostbyname, 1 if we use a local storage */
+#ifndef LWIP_DNS_API_HOSTENT_STORAGE
+#define LWIP_DNS_API_HOSTENT_STORAGE 0
+#endif
+
+/** define "hostent" variables storage */
+#if LWIP_DNS_API_HOSTENT_STORAGE
+#define HOSTENT_STORAGE
+#else
+#define HOSTENT_STORAGE static
+#endif /* LWIP_DNS_API_STATIC_HOSTENT */
+
+/**
+ * Returns an entry containing addresses of address family AF_INET
+ * for the host with name name.
+ * Due to dns_gethostbyname limitations, only one address is returned.
+ *
+ * @param name the hostname to resolve
+ * @return an entry containing addresses of address family AF_INET
+ *         for the host with name name
+ */
+struct hostent *
+lwip_gethostbyname(const char *name)
+{
+  err_t err;
+  ip_addr_t addr;
+
+  /* buffer variables for lwip_gethostbyname() */
+  HOSTENT_STORAGE struct hostent s_hostent;
+  HOSTENT_STORAGE char *s_aliases;
+  HOSTENT_STORAGE ip_addr_t s_hostent_addr;
+  HOSTENT_STORAGE ip_addr_t *s_phostent_addr[2];
+  HOSTENT_STORAGE char s_hostname[DNS_MAX_NAME_LENGTH + 1];
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &addr);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    h_errno = HOST_NOT_FOUND;
+    return NULL;
+  }
+
+  /* fill hostent */
+  s_hostent_addr = addr;
+  s_phostent_addr[0] = &s_hostent_addr;
+  s_phostent_addr[1] = NULL;
+  strncpy(s_hostname, name, DNS_MAX_NAME_LENGTH);
+  s_hostname[DNS_MAX_NAME_LENGTH] = 0;
+  s_hostent.h_name = s_hostname;
+  s_aliases = NULL;
+  s_hostent.h_aliases = &s_aliases;
+  s_hostent.h_addrtype = AF_INET;
+  s_hostent.h_length = sizeof(ip_addr_t);
+  s_hostent.h_addr_list = (char **)&s_phostent_addr;
+
+#if DNS_DEBUG
+  /* dump hostent */
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name           == %s\n", s_hostent.h_name));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases        == %p\n", (void *)s_hostent.h_aliases));
+  /* h_aliases are always empty */
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype       == %d\n", s_hostent.h_addrtype));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length         == %d\n", s_hostent.h_length));
+  LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list      == %p\n", (void *)s_hostent.h_addr_list));
+  if (s_hostent.h_addr_list != NULL) {
+    u8_t idx;
+    for (idx = 0; s_hostent.h_addr_list[idx]; idx++) {
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]   == %p\n", idx, s_hostent.h_addr_list[idx]));
+      LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n", idx, ipaddr_ntoa((ip_addr_t *)s_hostent.h_addr_list[idx])));
+    }
+  }
+#endif /* DNS_DEBUG */
+
+#if LWIP_DNS_API_HOSTENT_STORAGE
+  /* this function should return the "per-thread" hostent after copy from s_hostent */
+  return sys_thread_hostent(&s_hostent);
+#else
+  return &s_hostent;
+#endif /* LWIP_DNS_API_HOSTENT_STORAGE */
+}
+
+/**
+ * Thread-safe variant of lwip_gethostbyname: instead of using a static
+ * buffer, this function takes buffer and errno pointers as arguments
+ * and uses these for the result.
+ *
+ * @param name the hostname to resolve
+ * @param ret pre-allocated struct where to store the result
+ * @param buf pre-allocated buffer where to store additional data
+ * @param buflen the size of buf
+ * @param result pointer to a hostent pointer that is set to ret on success
+ *               and set to zero on error
+ * @param h_errnop pointer to an int where to store errors (instead of modifying
+ *                 the global h_errno)
+ * @return 0 on success, non-zero on error, additional error information
+ *         is stored in *h_errnop instead of h_errno to be thread-safe
+ */
+int
+lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                     size_t buflen, struct hostent **result, int *h_errnop)
+{
+  err_t err;
+  struct gethostbyname_r_helper *h;
+  char *hostname;
+  size_t namelen;
+  int lh_errno;
+
+  if (h_errnop == NULL) {
+    /* ensure h_errnop is never NULL */
+    h_errnop = &lh_errno;
+  }
+
+  if (result == NULL) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+  /* first thing to do: set *result to nothing */
+  *result = NULL;
+  if ((name == NULL) || (ret == NULL) || (buf == NULL)) {
+    /* not all arguments given */
+    *h_errnop = EINVAL;
+    return -1;
+  }
+
+  namelen = strlen(name);
+  if (buflen < (sizeof(struct gethostbyname_r_helper) + LWIP_MEM_ALIGN_BUFFER(namelen + 1))) {
+    /* buf can't hold the data needed + a copy of name */
+    *h_errnop = ERANGE;
+    return -1;
+  }
+
+  h = (struct gethostbyname_r_helper *)LWIP_MEM_ALIGN(buf);
+  hostname = ((char *)h) + sizeof(struct gethostbyname_r_helper);
+
+  /* query host IP address */
+  err = netconn_gethostbyname(name, &h->addr);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err));
+    *h_errnop = HOST_NOT_FOUND;
+    return -1;
+  }
+
+  /* copy the hostname into buf */
+  MEMCPY(hostname, name, namelen);
+  hostname[namelen] = 0;
+
+  /* fill hostent */
+  h->addr_list[0] = &h->addr;
+  h->addr_list[1] = NULL;
+  h->aliases = NULL;
+  ret->h_name = hostname;
+  ret->h_aliases = &h->aliases;
+  ret->h_addrtype = AF_INET;
+  ret->h_length = sizeof(ip_addr_t);
+  ret->h_addr_list = (char **)&h->addr_list;
+
+  /* set result != NULL */
+  *result = ret;
+
+  /* return success */
+  return 0;
+}
+
+/**
+ * Frees one or more addrinfo structures returned by getaddrinfo(), along with
+ * any additional storage associated with those structures. If the ai_next field
+ * of the structure is not null, the entire list of structures is freed.
+ *
+ * @param ai struct addrinfo to free
+ */
+void
+lwip_freeaddrinfo(struct addrinfo *ai)
+{
+  struct addrinfo *next;
+
+  while (ai != NULL) {
+    next = ai->ai_next;
+    memp_free(MEMP_NETDB, ai);
+    ai = next;
+  }
+}
+
+/**
+ * Translates the name of a service location (for example, a host name) and/or
+ * a service name and returns a set of socket addresses and associated
+ * information to be used in creating a socket with which to address the
+ * specified service.
+ * Memory for the result is allocated internally and must be freed by calling
+ * lwip_freeaddrinfo()!
+ *
+ * Due to a limitation in dns_gethostbyname, only the first address of a
+ * host is returned.
+ * Also, service names are not supported (only port numbers)!
+ *
+ * @param nodename descriptive name or address string of the host
+ *                 (may be NULL -> local address)
+ * @param servname port number as string of NULL
+ * @param hints structure containing input values that set socktype and protocol
+ * @param res pointer to a pointer where to store the result (set to NULL on failure)
+ * @return 0 on success, non-zero on failure
+ *
+ * @todo: implement AI_V4MAPPED, AI_ADDRCONFIG
+ */
+int
+lwip_getaddrinfo(const char *nodename, const char *servname,
+                 const struct addrinfo *hints, struct addrinfo **res)
+{
+  err_t err;
+  ip_addr_t addr;
+  struct addrinfo *ai;
+  struct sockaddr_storage *sa = NULL;
+  int port_nr = 0;
+  size_t total_size;
+  size_t namelen = 0;
+  int ai_family;
+
+  if (res == NULL) {
+    return EAI_FAIL;
+  }
+  *res = NULL;
+  if ((nodename == NULL) && (servname == NULL)) {
+    return EAI_NONAME;
+  }
+
+  if (hints != NULL) {
+    ai_family = hints->ai_family;
+    if ((ai_family != AF_UNSPEC)
+#if LWIP_IPV4
+        && (ai_family != AF_INET)
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+        && (ai_family != AF_INET6)
+#endif /* LWIP_IPV6 */
+       ) {
+      return EAI_FAMILY;
+    }
+  } else {
+    ai_family = AF_UNSPEC;
+  }
+
+  if (servname != NULL) {
+    /* service name specified: convert to port number
+     * @todo?: currently, only ASCII integers (port numbers) are supported (AI_NUMERICSERV)! */
+    port_nr = atoi(servname);
+    if ((port_nr <= 0) || (port_nr > 0xffff)) {
+      return EAI_SERVICE;
+    }
+  }
+
+  if (nodename != NULL) {
+    /* service location specified, try to resolve */
+    if ((hints != NULL) && (hints->ai_flags & AI_NUMERICHOST)) {
+      /* no DNS lookup, just parse for an address string */
+      if (!ipaddr_aton(nodename, &addr)) {
+        return EAI_NONAME;
+      }
+#if LWIP_IPV4 && LWIP_IPV6
+      if ((IP_IS_V6_VAL(addr) && ai_family == AF_INET) ||
+          (IP_IS_V4_VAL(addr) && ai_family == AF_INET6)) {
+        return EAI_NONAME;
+      }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+    } else {
+#if LWIP_IPV4 && LWIP_IPV6
+      /* AF_UNSPEC: prefer IPv4 */
+      u8_t type = NETCONN_DNS_IPV4_IPV6;
+      if (ai_family == AF_INET) {
+        type = NETCONN_DNS_IPV4;
+      } else if (ai_family == AF_INET6) {
+        type = NETCONN_DNS_IPV6;
+      }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+      err = netconn_gethostbyname_addrtype(nodename, &addr, type);
+      if (err != ERR_OK) {
+        return EAI_FAIL;
+      }
+    }
+  } else {
+    /* service location specified, use loopback address */
+    if ((hints != NULL) && (hints->ai_flags & AI_PASSIVE)) {
+      ip_addr_set_any_val(ai_family == AF_INET6, addr);
+    } else {
+      ip_addr_set_loopback_val(ai_family == AF_INET6, addr);
+    }
+  }
+
+  total_size = sizeof(struct addrinfo) + sizeof(struct sockaddr_storage);
+  if (nodename != NULL) {
+    namelen = strlen(nodename);
+    if (namelen > DNS_MAX_NAME_LENGTH) {
+      /* invalid name length */
+      return EAI_FAIL;
+    }
+    LWIP_ASSERT("namelen is too long", total_size + namelen + 1 > total_size);
+    total_size += namelen + 1;
+  }
+  /* If this fails, please report to lwip-devel! :-) */
+  LWIP_ASSERT("total_size <= NETDB_ELEM_SIZE: please report this!",
+              total_size <= NETDB_ELEM_SIZE);
+  ai = (struct addrinfo *)memp_malloc(MEMP_NETDB);
+  if (ai == NULL) {
+    return EAI_MEMORY;
+  }
+  memset(ai, 0, total_size);
+  /* cast through void* to get rid of alignment warnings */
+  sa = (struct sockaddr_storage *)(void *)((u8_t *)ai + sizeof(struct addrinfo));
+  if (IP_IS_V6_VAL(addr)) {
+#if LWIP_IPV6
+    struct sockaddr_in6 *sa6 = (struct sockaddr_in6 *)sa;
+    /* set up sockaddr */
+    inet6_addr_from_ip6addr(&sa6->sin6_addr, ip_2_ip6(&addr));
+    sa6->sin6_family = AF_INET6;
+    sa6->sin6_len = sizeof(struct sockaddr_in6);
+    sa6->sin6_port = lwip_htons((u16_t)port_nr);
+    sa6->sin6_scope_id = ip6_addr_zone(ip_2_ip6(&addr));
+    ai->ai_family = AF_INET6;
+#endif /* LWIP_IPV6 */
+  } else {
+#if LWIP_IPV4
+    struct sockaddr_in *sa4 = (struct sockaddr_in *)sa;
+    /* set up sockaddr */
+    inet_addr_from_ip4addr(&sa4->sin_addr, ip_2_ip4(&addr));
+    sa4->sin_family = AF_INET;
+    sa4->sin_len = sizeof(struct sockaddr_in);
+    sa4->sin_port = lwip_htons((u16_t)port_nr);
+    ai->ai_family = AF_INET;
+#endif /* LWIP_IPV4 */
+  }
+
+  /* set up addrinfo */
+  if (hints != NULL) {
+    /* copy socktype & protocol from hints if specified */
+    ai->ai_socktype = hints->ai_socktype;
+    ai->ai_protocol = hints->ai_protocol;
+  }
+  if (nodename != NULL) {
+    /* copy nodename to canonname if specified */
+    ai->ai_canonname = ((char *)ai + sizeof(struct addrinfo) + sizeof(struct sockaddr_storage));
+    MEMCPY(ai->ai_canonname, nodename, namelen);
+    ai->ai_canonname[namelen] = 0;
+  }
+  ai->ai_addrlen = sizeof(struct sockaddr_storage);
+  ai->ai_addr = (struct sockaddr *)sa;
+
+  *res = ai;
+
+  return 0;
+}
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netifapi.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netifapi.c
new file mode 100644
index 000000000..25957cd5c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/netifapi.c
@@ -0,0 +1,380 @@
+/**
+ * @file
+ * Network Interface Sequential API module
+ *
+ * @defgroup netifapi NETIF API
+ * @ingroup sequential_api
+ * Thread-safe functions to be called from non-TCPIP threads
+ *
+ * @defgroup netifapi_netif NETIF related
+ * @ingroup netifapi
+ * To be called from non-TCPIP threads
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/etharp.h"
+#include "lwip/netifapi.h"
+#include "lwip/memp.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#include <string.h> /* strncpy */
+
+#define NETIFAPI_VAR_REF(name)      API_VAR_REF(name)
+#define NETIFAPI_VAR_DECLARE(name)  API_VAR_DECLARE(struct netifapi_msg, name)
+#define NETIFAPI_VAR_ALLOC(name)    API_VAR_ALLOC(struct netifapi_msg, MEMP_NETIFAPI_MSG, name, ERR_MEM)
+#define NETIFAPI_VAR_FREE(name)     API_VAR_FREE(MEMP_NETIFAPI_MSG, name)
+
+/**
+ * Call netif_add() inside the tcpip_thread context.
+ */
+static err_t
+netifapi_do_netif_add(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings.
+   * We know it works because the structs have been instantiated as struct netifapi_msg */
+  struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m;
+
+  if (!netif_add( msg->netif,
+#if LWIP_IPV4
+                  API_EXPR_REF(msg->msg.add.ipaddr),
+                  API_EXPR_REF(msg->msg.add.netmask),
+                  API_EXPR_REF(msg->msg.add.gw),
+#endif /* LWIP_IPV4 */
+                  msg->msg.add.state,
+                  msg->msg.add.init,
+                  msg->msg.add.input)) {
+    return ERR_IF;
+  } else {
+    return ERR_OK;
+  }
+}
+
+#if LWIP_IPV4
+/**
+ * Call netif_set_addr() inside the tcpip_thread context.
+ */
+static err_t
+netifapi_do_netif_set_addr(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings.
+   * We know it works because the structs have been instantiated as struct netifapi_msg */
+  struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m;
+
+  netif_set_addr( msg->netif,
+                  API_EXPR_REF(msg->msg.add.ipaddr),
+                  API_EXPR_REF(msg->msg.add.netmask),
+                  API_EXPR_REF(msg->msg.add.gw));
+  return ERR_OK;
+}
+#endif /* LWIP_IPV4 */
+
+/**
+* Call netif_name_to_index() inside the tcpip_thread context.
+*/
+static err_t
+netifapi_do_name_to_index(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings.
+   * We know it works because the structs have been instantiated as struct netifapi_msg */
+  struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m;
+
+  msg->msg.ifs.index = netif_name_to_index(msg->msg.ifs.name);
+  return ERR_OK;
+}
+
+/**
+* Call netif_index_to_name() inside the tcpip_thread context.
+*/
+static err_t
+netifapi_do_index_to_name(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings.
+   * We know it works because the structs have been instantiated as struct netifapi_msg */
+  struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m;
+
+  if (!netif_index_to_name(msg->msg.ifs.index, msg->msg.ifs.name)) {
+    /* return failure via empty name */
+    msg->msg.ifs.name[0] = '\0';
+  }
+  return ERR_OK;
+}
+
+/**
+ * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the
+ * tcpip_thread context.
+ */
+static err_t
+netifapi_do_netif_common(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings.
+   * We know it works because the structs have been instantiated as struct netifapi_msg */
+  struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m;
+
+  if (msg->msg.common.errtfunc != NULL) {
+    return msg->msg.common.errtfunc(msg->netif);
+  } else {
+    msg->msg.common.voidfunc(msg->netif);
+    return ERR_OK;
+  }
+}
+
+#if LWIP_ARP && LWIP_IPV4
+/**
+ * @ingroup netifapi_arp
+ * Add or update an entry in the ARP cache.
+ * For an update, ipaddr is used to find the cache entry.
+ *
+ * @param ipaddr IPv4 address of cache entry
+ * @param ethaddr hardware address mapped to ipaddr
+ * @param type type of ARP cache entry
+ * @return ERR_OK: entry added/updated, else error from err_t
+ */
+err_t
+netifapi_arp_add(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, enum netifapi_arp_entry type)
+{
+  err_t err;
+
+  /* We only support permanent entries currently */
+  LWIP_UNUSED_ARG(type);
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING
+  LOCK_TCPIP_CORE();
+  err = etharp_add_static_entry(ipaddr, ethaddr);
+  UNLOCK_TCPIP_CORE();
+#else
+  /* @todo add new vars to struct netifapi_msg and create a 'do' func */
+  LWIP_UNUSED_ARG(ipaddr);
+  LWIP_UNUSED_ARG(ethaddr);
+  err = ERR_VAL;
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING */
+
+  return err;
+}
+
+/**
+ * @ingroup netifapi_arp
+ * Remove an entry in the ARP cache identified by ipaddr
+ *
+ * @param ipaddr IPv4 address of cache entry
+ * @param type type of ARP cache entry
+ * @return ERR_OK: entry removed, else error from err_t
+ */
+err_t
+netifapi_arp_remove(const ip4_addr_t *ipaddr, enum netifapi_arp_entry type)
+{
+  err_t err;
+
+  /* We only support permanent entries currently */
+  LWIP_UNUSED_ARG(type);
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING
+  LOCK_TCPIP_CORE();
+  err = etharp_remove_static_entry(ipaddr);
+  UNLOCK_TCPIP_CORE();
+#else
+  /* @todo add new vars to struct netifapi_msg and create a 'do' func */
+  LWIP_UNUSED_ARG(ipaddr);
+  err = ERR_VAL;
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING */
+
+  return err;
+}
+#endif /* LWIP_ARP && LWIP_IPV4 */
+
+/**
+ * @ingroup netifapi_netif
+ * Call netif_add() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_add()
+ */
+err_t
+netifapi_netif_add(struct netif *netif,
+#if LWIP_IPV4
+                   const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+                   void *state, netif_init_fn init, netif_input_fn input)
+{
+  err_t err;
+  NETIFAPI_VAR_DECLARE(msg);
+  NETIFAPI_VAR_ALLOC(msg);
+
+#if LWIP_IPV4
+  if (ipaddr == NULL) {
+    ipaddr = IP4_ADDR_ANY4;
+  }
+  if (netmask == NULL) {
+    netmask = IP4_ADDR_ANY4;
+  }
+  if (gw == NULL) {
+    gw = IP4_ADDR_ANY4;
+  }
+#endif /* LWIP_IPV4 */
+
+  NETIFAPI_VAR_REF(msg).netif = netif;
+#if LWIP_IPV4
+  NETIFAPI_VAR_REF(msg).msg.add.ipaddr  = NETIFAPI_VAR_REF(ipaddr);
+  NETIFAPI_VAR_REF(msg).msg.add.netmask = NETIFAPI_VAR_REF(netmask);
+  NETIFAPI_VAR_REF(msg).msg.add.gw      = NETIFAPI_VAR_REF(gw);
+#endif /* LWIP_IPV4 */
+  NETIFAPI_VAR_REF(msg).msg.add.state   = state;
+  NETIFAPI_VAR_REF(msg).msg.add.init    = init;
+  NETIFAPI_VAR_REF(msg).msg.add.input   = input;
+  err = tcpip_api_call(netifapi_do_netif_add, &API_VAR_REF(msg).call);
+  NETIFAPI_VAR_FREE(msg);
+  return err;
+}
+
+#if LWIP_IPV4
+/**
+ * @ingroup netifapi_netif
+ * Call netif_set_addr() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ *
+ * @note for params @see netif_set_addr()
+ */
+err_t
+netifapi_netif_set_addr(struct netif *netif,
+                        const ip4_addr_t *ipaddr,
+                        const ip4_addr_t *netmask,
+                        const ip4_addr_t *gw)
+{
+  err_t err;
+  NETIFAPI_VAR_DECLARE(msg);
+  NETIFAPI_VAR_ALLOC(msg);
+
+  if (ipaddr == NULL) {
+    ipaddr = IP4_ADDR_ANY4;
+  }
+  if (netmask == NULL) {
+    netmask = IP4_ADDR_ANY4;
+  }
+  if (gw == NULL) {
+    gw = IP4_ADDR_ANY4;
+  }
+
+  NETIFAPI_VAR_REF(msg).netif = netif;
+  NETIFAPI_VAR_REF(msg).msg.add.ipaddr  = NETIFAPI_VAR_REF(ipaddr);
+  NETIFAPI_VAR_REF(msg).msg.add.netmask = NETIFAPI_VAR_REF(netmask);
+  NETIFAPI_VAR_REF(msg).msg.add.gw      = NETIFAPI_VAR_REF(gw);
+  err = tcpip_api_call(netifapi_do_netif_set_addr, &API_VAR_REF(msg).call);
+  NETIFAPI_VAR_FREE(msg);
+  return err;
+}
+#endif /* LWIP_IPV4 */
+
+/**
+ * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe
+ * way by running that function inside the tcpip_thread context.
+ *
+ * @note use only for functions where there is only "netif" parameter.
+ */
+err_t
+netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc,
+                      netifapi_errt_fn errtfunc)
+{
+  err_t err;
+  NETIFAPI_VAR_DECLARE(msg);
+  NETIFAPI_VAR_ALLOC(msg);
+
+  NETIFAPI_VAR_REF(msg).netif = netif;
+  NETIFAPI_VAR_REF(msg).msg.common.voidfunc = voidfunc;
+  NETIFAPI_VAR_REF(msg).msg.common.errtfunc = errtfunc;
+  err = tcpip_api_call(netifapi_do_netif_common, &API_VAR_REF(msg).call);
+  NETIFAPI_VAR_FREE(msg);
+  return err;
+}
+
+/**
+* @ingroup netifapi_netif
+* Call netif_name_to_index() in a thread-safe way by running that function inside the
+* tcpip_thread context.
+*
+* @param name the interface name of the netif
+* @param idx output index of the found netif
+*/
+err_t
+netifapi_netif_name_to_index(const char *name, u8_t *idx)
+{
+  err_t err;
+  NETIFAPI_VAR_DECLARE(msg);
+  NETIFAPI_VAR_ALLOC(msg);
+
+  *idx = 0;
+
+#if LWIP_MPU_COMPATIBLE
+  strncpy(NETIFAPI_VAR_REF(msg).msg.ifs.name, name, NETIF_NAMESIZE - 1);
+  NETIFAPI_VAR_REF(msg).msg.ifs.name[NETIF_NAMESIZE - 1] = '\0';
+#else
+  NETIFAPI_VAR_REF(msg).msg.ifs.name = LWIP_CONST_CAST(char *, name);
+#endif /* LWIP_MPU_COMPATIBLE */
+  err = tcpip_api_call(netifapi_do_name_to_index, &API_VAR_REF(msg).call);
+  if (!err) {
+    *idx = NETIFAPI_VAR_REF(msg).msg.ifs.index;
+  }
+  NETIFAPI_VAR_FREE(msg);
+  return err;
+}
+
+/**
+* @ingroup netifapi_netif
+* Call netif_index_to_name() in a thread-safe way by running that function inside the
+* tcpip_thread context.
+*
+* @param idx the interface index of the netif
+* @param name output name of the found netif, empty '\0' string if netif not found.
+*             name should be of at least NETIF_NAMESIZE bytes
+*/
+err_t
+netifapi_netif_index_to_name(u8_t idx, char *name)
+{
+  err_t err;
+  NETIFAPI_VAR_DECLARE(msg);
+  NETIFAPI_VAR_ALLOC(msg);
+
+  NETIFAPI_VAR_REF(msg).msg.ifs.index = idx;
+#if !LWIP_MPU_COMPATIBLE
+  NETIFAPI_VAR_REF(msg).msg.ifs.name = name;
+#endif /* LWIP_MPU_COMPATIBLE */
+  err = tcpip_api_call(netifapi_do_index_to_name, &API_VAR_REF(msg).call);
+#if LWIP_MPU_COMPATIBLE
+  if (!err) {
+    strncpy(name, NETIFAPI_VAR_REF(msg).msg.ifs.name, NETIF_NAMESIZE - 1);
+    name[NETIF_NAMESIZE - 1] = '\0';
+  }
+#endif /* LWIP_MPU_COMPATIBLE */
+  NETIFAPI_VAR_FREE(msg);
+  return err;
+}
+
+#endif /* LWIP_NETIF_API */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/sockets.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/sockets.c
new file mode 100644
index 000000000..cb7df914f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/sockets.c
@@ -0,0 +1,4160 @@
+/**
+ * @file
+ * Sockets BSD-Like API module
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ * Improved by Marc Boucher <marc@mbsi.ca> and David Haas <dhaas@alum.rpi.edu>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sockets.h"
+#include "lwip/priv/sockets_priv.h"
+#include "lwip/api.h"
+#include "lwip/igmp.h"
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "lwip/mld6.h"
+#if LWIP_CHECKSUM_ON_COPY
+#include "lwip/inet_chksum.h"
+#endif
+
+#if LWIP_COMPAT_SOCKETS == 2 && LWIP_POSIX_SOCKETS_IO_NAMES
+#include <stdarg.h>
+#endif
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/* If the netconn API is not required publicly, then we include the necessary
+   files here to get the implementation */
+#if !LWIP_NETCONN
+#undef LWIP_NETCONN
+#define LWIP_NETCONN 1
+#include "api_msg.c"
+#include "api_lib.c"
+#include "netbuf.c"
+#undef LWIP_NETCONN
+#define LWIP_NETCONN 0
+#endif
+
+#define API_SELECT_CB_VAR_REF(name)               API_VAR_REF(name)
+#define API_SELECT_CB_VAR_DECLARE(name)           API_VAR_DECLARE(struct lwip_select_cb, name)
+#define API_SELECT_CB_VAR_ALLOC(name, retblock)   API_VAR_ALLOC_EXT(struct lwip_select_cb, MEMP_SELECT_CB, name, retblock)
+#define API_SELECT_CB_VAR_FREE(name)              API_VAR_FREE(MEMP_SELECT_CB, name)
+
+#if LWIP_IPV4
+#define IP4ADDR_PORT_TO_SOCKADDR(sin, ipaddr, port) do { \
+      (sin)->sin_len = sizeof(struct sockaddr_in); \
+      (sin)->sin_family = AF_INET; \
+      (sin)->sin_port = lwip_htons((port)); \
+      inet_addr_from_ip4addr(&(sin)->sin_addr, ipaddr); \
+      memset((sin)->sin_zero, 0, SIN_ZERO_LEN); }while(0)
+#define SOCKADDR4_TO_IP4ADDR_PORT(sin, ipaddr, port) do { \
+    inet_addr_to_ip4addr(ip_2_ip4(ipaddr), &((sin)->sin_addr)); \
+    (port) = lwip_ntohs((sin)->sin_port); }while(0)
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+#define IP6ADDR_PORT_TO_SOCKADDR(sin6, ipaddr, port) do { \
+      (sin6)->sin6_len = sizeof(struct sockaddr_in6); \
+      (sin6)->sin6_family = AF_INET6; \
+      (sin6)->sin6_port = lwip_htons((port)); \
+      (sin6)->sin6_flowinfo = 0; \
+      inet6_addr_from_ip6addr(&(sin6)->sin6_addr, ipaddr); \
+      (sin6)->sin6_scope_id = ip6_addr_zone(ipaddr); }while(0)
+#define SOCKADDR6_TO_IP6ADDR_PORT(sin6, ipaddr, port) do { \
+    inet6_addr_to_ip6addr(ip_2_ip6(ipaddr), &((sin6)->sin6_addr)); \
+    if (ip6_addr_has_scope(ip_2_ip6(ipaddr), IP6_UNKNOWN)) { \
+      ip6_addr_set_zone(ip_2_ip6(ipaddr), (u8_t)((sin6)->sin6_scope_id)); \
+    } \
+    (port) = lwip_ntohs((sin6)->sin6_port); }while(0)
+#endif /* LWIP_IPV6 */
+
+#if LWIP_IPV4 && LWIP_IPV6
+static void sockaddr_to_ipaddr_port(const struct sockaddr *sockaddr, ip_addr_t *ipaddr, u16_t *port);
+
+#define IS_SOCK_ADDR_LEN_VALID(namelen)  (((namelen) == sizeof(struct sockaddr_in)) || \
+                                         ((namelen) == sizeof(struct sockaddr_in6)))
+#define IS_SOCK_ADDR_TYPE_VALID(name)    (((name)->sa_family == AF_INET) || \
+                                         ((name)->sa_family == AF_INET6))
+#define SOCK_ADDR_TYPE_MATCH(name, sock) \
+       ((((name)->sa_family == AF_INET) && !(NETCONNTYPE_ISIPV6((sock)->conn->type))) || \
+       (((name)->sa_family == AF_INET6) && (NETCONNTYPE_ISIPV6((sock)->conn->type))))
+#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) do { \
+    if (IP_IS_ANY_TYPE_VAL(*ipaddr) || IP_IS_V6_VAL(*ipaddr)) { \
+      IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port); \
+    } else { \
+      IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port); \
+    } } while(0)
+#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) sockaddr_to_ipaddr_port(sockaddr, ipaddr, &(port))
+#define DOMAIN_TO_NETCONN_TYPE(domain, type) (((domain) == AF_INET) ? \
+  (type) : (enum netconn_type)((type) | NETCONN_TYPE_IPV6))
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+#define IS_SOCK_ADDR_LEN_VALID(namelen)  ((namelen) == sizeof(struct sockaddr_in6))
+#define IS_SOCK_ADDR_TYPE_VALID(name)    ((name)->sa_family == AF_INET6)
+#define SOCK_ADDR_TYPE_MATCH(name, sock) 1
+#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \
+        IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port)
+#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \
+        SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, port)
+#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type)
+#else /*-> LWIP_IPV4: LWIP_IPV4 && LWIP_IPV6 */
+#define IS_SOCK_ADDR_LEN_VALID(namelen)  ((namelen) == sizeof(struct sockaddr_in))
+#define IS_SOCK_ADDR_TYPE_VALID(name)    ((name)->sa_family == AF_INET)
+#define SOCK_ADDR_TYPE_MATCH(name, sock) 1
+#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \
+        IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port)
+#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \
+        SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, port)
+#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type)
+#endif /* LWIP_IPV6 */
+
+#define IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name)    (((name)->sa_family == AF_UNSPEC) || \
+                                                    IS_SOCK_ADDR_TYPE_VALID(name))
+#define SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock) (((name)->sa_family == AF_UNSPEC) || \
+                                                    SOCK_ADDR_TYPE_MATCH(name, sock))
+#define IS_SOCK_ADDR_ALIGNED(name)      ((((mem_ptr_t)(name)) % 4) == 0)
+
+
+#define LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype) do { if ((optlen) < sizeof(opttype)) { done_socket(sock); return EINVAL; }}while(0)
+#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, opttype) do { \
+  LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype); \
+  if ((sock)->conn == NULL) { done_socket(sock); return EINVAL; } }while(0)
+#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype) do { \
+  LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype); \
+  if (((sock)->conn == NULL) || ((sock)->conn->pcb.tcp == NULL)) { done_socket(sock); return EINVAL; } }while(0)
+#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, opttype, netconntype) do { \
+  LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype); \
+  if (NETCONNTYPE_GROUP(netconn_type((sock)->conn)) != netconntype) { done_socket(sock); return ENOPROTOOPT; } }while(0)
+
+
+#define LWIP_SETGETSOCKOPT_DATA_VAR_REF(name)     API_VAR_REF(name)
+#define LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(name) API_VAR_DECLARE(struct lwip_setgetsockopt_data, name)
+#define LWIP_SETGETSOCKOPT_DATA_VAR_FREE(name)    API_VAR_FREE(MEMP_SOCKET_SETGETSOCKOPT_DATA, name)
+#if LWIP_MPU_COMPATIBLE
+#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) do { \
+  name = (struct lwip_setgetsockopt_data *)memp_malloc(MEMP_SOCKET_SETGETSOCKOPT_DATA); \
+  if (name == NULL) { \
+    sock_set_errno(sock, ENOMEM); \
+    done_socket(sock); \
+    return -1; \
+  } }while(0)
+#else /* LWIP_MPU_COMPATIBLE */
+#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock)
+#endif /* LWIP_MPU_COMPATIBLE */
+
+#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD
+#define LWIP_SO_SNDRCVTIMEO_OPTTYPE int
+#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) (*(int *)(optval) = (val))
+#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval)   ((long)*(const int*)(optval))
+#else
+#define LWIP_SO_SNDRCVTIMEO_OPTTYPE struct timeval
+#define LWIP_SO_SNDRCVTIMEO_SET(optval, val)  do { \
+  u32_t loc = (val); \
+  ((struct timeval *)(optval))->tv_sec = (long)((loc) / 1000U); \
+  ((struct timeval *)(optval))->tv_usec = (long)(((loc) % 1000U) * 1000U); }while(0)
+#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((((const struct timeval *)(optval))->tv_sec * 1000) + (((const struct timeval *)(optval))->tv_usec / 1000))
+#endif
+
+
+/** A struct sockaddr replacement that has the same alignment as sockaddr_in/
+ *  sockaddr_in6 if instantiated.
+ */
+union sockaddr_aligned {
+  struct sockaddr sa;
+#if LWIP_IPV6
+  struct sockaddr_in6 sin6;
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+  struct sockaddr_in sin;
+#endif /* LWIP_IPV4 */
+};
+
+/* Define the number of IPv4 multicast memberships, default is one per socket */
+#ifndef LWIP_SOCKET_MAX_MEMBERSHIPS
+#define LWIP_SOCKET_MAX_MEMBERSHIPS NUM_SOCKETS
+#endif
+
+#if LWIP_IGMP
+/* This is to keep track of IP_ADD_MEMBERSHIP calls to drop the membership when
+   a socket is closed */
+struct lwip_socket_multicast_pair {
+  /** the socket */
+  struct lwip_sock *sock;
+  /** the interface address */
+  ip4_addr_t if_addr;
+  /** the group address */
+  ip4_addr_t multi_addr;
+};
+
+static struct lwip_socket_multicast_pair socket_ipv4_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS];
+
+static int  lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr);
+static void lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr);
+static void lwip_socket_drop_registered_memberships(int s);
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV6_MLD
+/* This is to keep track of IP_JOIN_GROUP calls to drop the membership when
+   a socket is closed */
+struct lwip_socket_multicast_mld6_pair {
+  /** the socket */
+  struct lwip_sock *sock;
+  /** the interface index */
+  u8_t if_idx;
+  /** the group address */
+  ip6_addr_t multi_addr;
+};
+
+static struct lwip_socket_multicast_mld6_pair socket_ipv6_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS];
+
+static int  lwip_socket_register_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr);
+static void lwip_socket_unregister_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr);
+static void lwip_socket_drop_registered_mld6_memberships(int s);
+#endif /* LWIP_IPV6_MLD */
+
+/** The global array of available sockets */
+static struct lwip_sock sockets[NUM_SOCKETS];
+
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+#if LWIP_TCPIP_CORE_LOCKING
+/* protect the select_cb_list using core lock */
+#define LWIP_SOCKET_SELECT_DECL_PROTECT(lev)
+#define LWIP_SOCKET_SELECT_PROTECT(lev)   LOCK_TCPIP_CORE()
+#define LWIP_SOCKET_SELECT_UNPROTECT(lev) UNLOCK_TCPIP_CORE()
+#else /* LWIP_TCPIP_CORE_LOCKING */
+/* protect the select_cb_list using SYS_LIGHTWEIGHT_PROT */
+#define LWIP_SOCKET_SELECT_DECL_PROTECT(lev)  SYS_ARCH_DECL_PROTECT(lev)
+#define LWIP_SOCKET_SELECT_PROTECT(lev)       SYS_ARCH_PROTECT(lev)
+#define LWIP_SOCKET_SELECT_UNPROTECT(lev)     SYS_ARCH_UNPROTECT(lev)
+/** This counter is increased from lwip_select when the list is changed
+    and checked in select_check_waiters to see if it has changed. */
+static volatile int select_cb_ctr;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+/** The global list of tasks waiting for select */
+static struct lwip_select_cb *select_cb_list;
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+
+#define sock_set_errno(sk, e) do { \
+  const int sockerr = (e); \
+  set_errno(sockerr); \
+} while (0)
+
+/* Forward declaration of some functions */
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+#define DEFAULT_SOCKET_EVENTCB event_callback
+static void select_check_waiters(int s, int has_recvevent, int has_sendevent, int has_errevent);
+#else
+#define DEFAULT_SOCKET_EVENTCB NULL
+#endif
+#if !LWIP_TCPIP_CORE_LOCKING
+static void lwip_getsockopt_callback(void *arg);
+static void lwip_setsockopt_callback(void *arg);
+#endif
+static int lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen);
+static int lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen);
+static int free_socket_locked(struct lwip_sock *sock, int is_tcp, struct netconn **conn,
+                              union lwip_sock_lastdata *lastdata);
+static void free_socket_free_elements(int is_tcp, struct netconn *conn, union lwip_sock_lastdata *lastdata);
+
+#if LWIP_IPV4 && LWIP_IPV6
+static void
+sockaddr_to_ipaddr_port(const struct sockaddr *sockaddr, ip_addr_t *ipaddr, u16_t *port)
+{
+  if ((sockaddr->sa_family) == AF_INET6) {
+    SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6 *)(const void *)(sockaddr), ipaddr, *port);
+    ipaddr->type = IPADDR_TYPE_V6;
+  } else {
+    SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in *)(const void *)(sockaddr), ipaddr, *port);
+    ipaddr->type = IPADDR_TYPE_V4;
+  }
+}
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */
+void
+lwip_socket_thread_init(void)
+{
+  netconn_thread_init();
+}
+
+/** LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */
+void
+lwip_socket_thread_cleanup(void)
+{
+  netconn_thread_cleanup();
+}
+
+#if LWIP_NETCONN_FULLDUPLEX
+/* Thread-safe increment of sock->fd_used, with overflow check */
+static int
+sock_inc_used(struct lwip_sock *sock)
+{
+  int ret;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_ASSERT("sock != NULL", sock != NULL);
+
+  SYS_ARCH_PROTECT(lev);
+  if (sock->fd_free_pending) {
+    /* prevent new usage of this socket if free is pending */
+    ret = 0;
+  } else {
+    ++sock->fd_used;
+    ret = 1;
+    LWIP_ASSERT("sock->fd_used != 0", sock->fd_used != 0);
+  }
+  SYS_ARCH_UNPROTECT(lev);
+  return ret;
+}
+
+/* Like sock_inc_used(), but called under SYS_ARCH_PROTECT lock. */
+static int
+sock_inc_used_locked(struct lwip_sock *sock)
+{
+  LWIP_ASSERT("sock != NULL", sock != NULL);
+
+  if (sock->fd_free_pending) {
+    LWIP_ASSERT("sock->fd_used != 0", sock->fd_used != 0);
+    return 0;
+  }
+
+  ++sock->fd_used;
+  LWIP_ASSERT("sock->fd_used != 0", sock->fd_used != 0);
+  return 1;
+}
+
+/* In full-duplex mode,sock->fd_used != 0 prevents a socket descriptor from being
+ * released (and possibly reused) when used from more than one thread
+ * (e.g. read-while-write or close-while-write, etc)
+ * This function is called at the end of functions using (try)get_socket*().
+ */
+static void
+done_socket(struct lwip_sock *sock)
+{
+  int freed = 0;
+  int is_tcp = 0;
+  struct netconn *conn = NULL;
+  union lwip_sock_lastdata lastdata;
+  SYS_ARCH_DECL_PROTECT(lev);
+  LWIP_ASSERT("sock != NULL", sock != NULL);
+
+  SYS_ARCH_PROTECT(lev);
+  LWIP_ASSERT("sock->fd_used > 0", sock->fd_used > 0);
+  if (--sock->fd_used == 0) {
+    if (sock->fd_free_pending) {
+      /* free the socket */
+      sock->fd_used = 1;
+      is_tcp = sock->fd_free_pending & LWIP_SOCK_FD_FREE_TCP;
+      freed = free_socket_locked(sock, is_tcp, &conn, &lastdata);
+    }
+  }
+  SYS_ARCH_UNPROTECT(lev);
+
+  if (freed) {
+    free_socket_free_elements(is_tcp, conn, &lastdata);
+  }
+}
+
+#else /* LWIP_NETCONN_FULLDUPLEX */
+#define sock_inc_used(sock)         1
+#define sock_inc_used_locked(sock)  1
+#define done_socket(sock)
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+/* Translate a socket 'int' into a pointer (only fails if the index is invalid) */
+static struct lwip_sock *
+tryget_socket_unconn_nouse(int fd)
+{
+  int s = fd - LWIP_SOCKET_OFFSET;
+  if ((s < 0) || (s >= NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("tryget_socket_unconn(%d): invalid\n", fd));
+    return NULL;
+  }
+  return &sockets[s];
+}
+
+struct lwip_sock *
+lwip_socket_dbg_get_socket(int fd)
+{
+  return tryget_socket_unconn_nouse(fd);
+}
+
+/* Translate a socket 'int' into a pointer (only fails if the index is invalid) */
+static struct lwip_sock *
+tryget_socket_unconn(int fd)
+{
+  struct lwip_sock *ret = tryget_socket_unconn_nouse(fd);
+  if (ret != NULL) {
+    if (!sock_inc_used(ret)) {
+      return NULL;
+    }
+  }
+  return ret;
+}
+
+/* Like tryget_socket_unconn(), but called under SYS_ARCH_PROTECT lock. */
+static struct lwip_sock *
+tryget_socket_unconn_locked(int fd)
+{
+  struct lwip_sock *ret = tryget_socket_unconn_nouse(fd);
+  if (ret != NULL) {
+    if (!sock_inc_used_locked(ret)) {
+      return NULL;
+    }
+  }
+  return ret;
+}
+
+/**
+ * Same as get_socket but doesn't set errno
+ *
+ * @param fd externally used socket index
+ * @return struct lwip_sock for the socket or NULL if not found
+ */
+static struct lwip_sock *
+tryget_socket(int fd)
+{
+  struct lwip_sock *sock = tryget_socket_unconn(fd);
+  if (sock != NULL) {
+    if (sock->conn) {
+      return sock;
+    }
+    done_socket(sock);
+  }
+  return NULL;
+}
+
+/**
+ * Map a externally used socket index to the internal socket representation.
+ *
+ * @param fd externally used socket index
+ * @return struct lwip_sock for the socket or NULL if not found
+ */
+static struct lwip_sock *
+get_socket(int fd)
+{
+  struct lwip_sock *sock = tryget_socket(fd);
+  if (!sock) {
+    if ((fd < LWIP_SOCKET_OFFSET) || (fd >= (LWIP_SOCKET_OFFSET + NUM_SOCKETS))) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", fd));
+    }
+    set_errno(EBADF);
+    return NULL;
+  }
+  return sock;
+}
+
+/**
+ * Allocate a new socket for a given netconn.
+ *
+ * @param newconn the netconn for which to allocate a socket
+ * @param accepted 1 if socket has been created by accept(),
+ *                 0 if socket has been created by socket()
+ * @return the index of the new socket; -1 on error
+ */
+static int
+alloc_socket(struct netconn *newconn, int accepted)
+{
+  int i;
+  SYS_ARCH_DECL_PROTECT(lev);
+  LWIP_UNUSED_ARG(accepted);
+
+  /* allocate a new socket identifier */
+  for (i = 0; i < NUM_SOCKETS; ++i) {
+    /* Protect socket array */
+    SYS_ARCH_PROTECT(lev);
+    if (!sockets[i].conn) {
+#if LWIP_NETCONN_FULLDUPLEX
+      if (sockets[i].fd_used) {
+        SYS_ARCH_UNPROTECT(lev);
+        continue;
+      }
+      sockets[i].fd_used    = 1;
+      sockets[i].fd_free_pending = 0;
+#endif
+      sockets[i].conn       = newconn;
+      /* The socket is not yet known to anyone, so no need to protect
+         after having marked it as used. */
+      SYS_ARCH_UNPROTECT(lev);
+      sockets[i].lastdata.pbuf = NULL;
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+      LWIP_ASSERT("sockets[i].select_waiting == 0", sockets[i].select_waiting == 0);
+      sockets[i].rcvevent   = 0;
+      /* TCP sendbuf is empty, but the socket is not yet writable until connected
+       * (unless it has been created by accept()). */
+      sockets[i].sendevent  = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1);
+      sockets[i].errevent   = 0;
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+      return i + LWIP_SOCKET_OFFSET;
+    }
+    SYS_ARCH_UNPROTECT(lev);
+  }
+  return -1;
+}
+
+/** Free a socket (under lock)
+ *
+ * @param sock the socket to free
+ * @param is_tcp != 0 for TCP sockets, used to free lastdata
+ * @param conn the socekt's netconn is stored here, must be freed externally
+ * @param lastdata lastdata is stored here, must be freed externally
+ */
+static int
+free_socket_locked(struct lwip_sock *sock, int is_tcp, struct netconn **conn,
+                   union lwip_sock_lastdata *lastdata)
+{
+#if LWIP_NETCONN_FULLDUPLEX
+  LWIP_ASSERT("sock->fd_used > 0", sock->fd_used > 0);
+  sock->fd_used--;
+  if (sock->fd_used > 0) {
+    sock->fd_free_pending = LWIP_SOCK_FD_FREE_FREE | (is_tcp ? LWIP_SOCK_FD_FREE_TCP : 0);
+    return 0;
+  }
+#else /* LWIP_NETCONN_FULLDUPLEX */
+  LWIP_UNUSED_ARG(is_tcp);
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+  *lastdata = sock->lastdata;
+  sock->lastdata.pbuf = NULL;
+  *conn = sock->conn;
+  sock->conn = NULL;
+  return 1;
+}
+
+/** Free a socket's leftover members.
+ */
+static void
+free_socket_free_elements(int is_tcp, struct netconn *conn, union lwip_sock_lastdata *lastdata)
+{
+  if (lastdata->pbuf != NULL) {
+    if (is_tcp) {
+      pbuf_free(lastdata->pbuf);
+    } else {
+      netbuf_delete(lastdata->netbuf);
+    }
+  }
+  if (conn != NULL) {
+    /* netconn_prepare_delete() has already been called, here we only free the conn */
+    netconn_delete(conn);
+  }
+}
+
+/** Free a socket. The socket's netconn must have been
+ * delete before!
+ *
+ * @param sock the socket to free
+ * @param is_tcp != 0 for TCP sockets, used to free lastdata
+ */
+static void
+free_socket(struct lwip_sock *sock, int is_tcp)
+{
+  int freed;
+  struct netconn *conn;
+  union lwip_sock_lastdata lastdata;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  /* Protect socket array */
+  SYS_ARCH_PROTECT(lev);
+
+  freed = free_socket_locked(sock, is_tcp, &conn, &lastdata);
+  SYS_ARCH_UNPROTECT(lev);
+  /* don't use 'sock' after this line, as another task might have allocated it */
+
+  if (freed) {
+    free_socket_free_elements(is_tcp, conn, &lastdata);
+  }
+}
+
+/* Below this, the well-known socket functions are implemented.
+ * Use google.com or opengroup.org to get a good description :-)
+ *
+ * Exceptions are documented!
+ */
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_sock *sock, *nsock;
+  struct netconn *newconn;
+  ip_addr_t naddr;
+  u16_t port = 0;
+  int newsock;
+  err_t err;
+  int recvevent;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* wait for a new connection */
+  err = netconn_accept(sock->conn, &newconn);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err));
+    if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) {
+      sock_set_errno(sock, EOPNOTSUPP);
+    } else if (err == ERR_CLSD) {
+      sock_set_errno(sock, EINVAL);
+    } else {
+      sock_set_errno(sock, err_to_errno(err));
+    }
+    done_socket(sock);
+    return -1;
+  }
+  LWIP_ASSERT("newconn != NULL", newconn != NULL);
+
+  newsock = alloc_socket(newconn, 1);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+    sock_set_errno(sock, ENFILE);
+    done_socket(sock);
+    return -1;
+  }
+  LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET));
+  nsock = &sockets[newsock - LWIP_SOCKET_OFFSET];
+
+  /* See event_callback: If data comes in right away after an accept, even
+   * though the server task might not have created a new socket yet.
+   * In that case, newconn->socket is counted down (newconn->socket--),
+   * so nsock->rcvevent is >= 1 here!
+   */
+  SYS_ARCH_PROTECT(lev);
+  recvevent = (s16_t)(-1 - newconn->socket);
+  newconn->socket = newsock;
+  SYS_ARCH_UNPROTECT(lev);
+
+  if (newconn->callback) {
+    LOCK_TCPIP_CORE();
+    while (recvevent > 0) {
+      recvevent--;
+      newconn->callback(newconn, NETCONN_EVT_RCVPLUS, 0);
+    }
+    UNLOCK_TCPIP_CORE();
+  }
+
+  /* Note that POSIX only requires us to check addr is non-NULL. addrlen must
+   * not be NULL if addr is valid.
+   */
+  if ((addr != NULL) && (addrlen != NULL)) {
+    union sockaddr_aligned tempaddr;
+    /* get the IP address and port of the remote host */
+    err = netconn_peer(newconn, &naddr, &port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err));
+      netconn_delete(newconn);
+      free_socket(nsock, 1);
+      sock_set_errno(sock, err_to_errno(err));
+      done_socket(sock);
+      return -1;
+    }
+
+    IPADDR_PORT_TO_SOCKADDR(&tempaddr, &naddr, port);
+    if (*addrlen > tempaddr.sa.sa_len) {
+      *addrlen = tempaddr.sa.sa_len;
+    }
+    MEMCPY(addr, &tempaddr, *addrlen);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+    ip_addr_debug_print_val(SOCKETS_DEBUG, naddr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port));
+  } else {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d", s, newsock));
+  }
+
+  sock_set_errno(sock, 0);
+  done_socket(sock);
+  done_socket(nsock);
+  return newsock;
+}
+
+int
+lwip_bind(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_sock *sock;
+  ip_addr_t local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (!SOCK_ADDR_TYPE_MATCH(name, sock)) {
+    /* sockaddr does not match socket type (IPv4/IPv6) */
+    sock_set_errno(sock, err_to_errno(ERR_VAL));
+    done_socket(sock);
+    return -1;
+  }
+
+  /* check size, family and alignment of 'name' */
+  LWIP_ERROR("lwip_bind: invalid address", (IS_SOCK_ADDR_LEN_VALID(namelen) &&
+             IS_SOCK_ADDR_TYPE_VALID(name) && IS_SOCK_ADDR_ALIGNED(name)),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;);
+  LWIP_UNUSED_ARG(namelen);
+
+  SOCKADDR_TO_IPADDR_PORT(name, &local_addr, local_port);
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print_val(SOCKETS_DEBUG, local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", local_port));
+
+#if LWIP_IPV4 && LWIP_IPV6
+  /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */
+  if (IP_IS_V6_VAL(local_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&local_addr))) {
+    unmap_ipv4_mapped_ipv6(ip_2_ip4(&local_addr), ip_2_ip6(&local_addr));
+    IP_SET_TYPE_VAL(local_addr, IPADDR_TYPE_V4);
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+  err = netconn_bind(sock->conn, &local_addr, local_port);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    done_socket(sock);
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  done_socket(sock);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_sock *sock;
+  int is_tcp = 0;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (sock->conn != NULL) {
+    is_tcp = NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP;
+  } else {
+    LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata.pbuf == NULL);
+  }
+
+#if LWIP_IGMP
+  /* drop all possibly joined IGMP memberships */
+  lwip_socket_drop_registered_memberships(s);
+#endif /* LWIP_IGMP */
+#if LWIP_IPV6_MLD
+  /* drop all possibly joined MLD6 memberships */
+  lwip_socket_drop_registered_mld6_memberships(s);
+#endif /* LWIP_IPV6_MLD */
+
+  err = netconn_prepare_delete(sock->conn);
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err_to_errno(err));
+    done_socket(sock);
+    return -1;
+  }
+
+  free_socket(sock, is_tcp);
+  set_errno(0);
+  return 0;
+}
+
+int
+lwip_connect(int s, const struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_sock *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (!SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock)) {
+    /* sockaddr does not match socket type (IPv4/IPv6) */
+    sock_set_errno(sock, err_to_errno(ERR_VAL));
+    done_socket(sock);
+    return -1;
+  }
+
+  LWIP_UNUSED_ARG(namelen);
+  if (name->sa_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    ip_addr_t remote_addr;
+    u16_t remote_port;
+
+    /* check size, family and alignment of 'name' */
+    LWIP_ERROR("lwip_connect: invalid address", IS_SOCK_ADDR_LEN_VALID(namelen) &&
+               IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) && IS_SOCK_ADDR_ALIGNED(name),
+               sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;);
+
+    SOCKADDR_TO_IPADDR_PORT(name, &remote_addr, remote_port);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print_val(SOCKETS_DEBUG, remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", remote_port));
+
+#if LWIP_IPV4 && LWIP_IPV6
+    /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */
+    if (IP_IS_V6_VAL(remote_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&remote_addr))) {
+      unmap_ipv4_mapped_ipv6(ip_2_ip4(&remote_addr), ip_2_ip6(&remote_addr));
+      IP_SET_TYPE_VAL(remote_addr, IPADDR_TYPE_V4);
+    }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+    err = netconn_connect(sock->conn, &remote_addr, remote_port);
+  }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    done_socket(sock);
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  done_socket(sock);
+  return 0;
+}
+
+/**
+ * Set a socket into listen mode.
+ * The socket may not have been used for another connection previously.
+ *
+ * @param s the socket to set to listening mode
+ * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1)
+ * @return 0 on success, non-zero on failure
+ */
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_sock *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* limit the "backlog" parameter to fit in an u8_t */
+  backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff);
+
+  err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) {
+      sock_set_errno(sock, EOPNOTSUPP);
+    } else {
+      sock_set_errno(sock, err_to_errno(err));
+    }
+    done_socket(sock);
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  done_socket(sock);
+  return 0;
+}
+
+#if LWIP_TCP
+/* Helper function to loop over receiving pbufs from netconn
+ * until "len" bytes are received or we're otherwise done.
+ * Keeps sock->lastdata for peeking or partly copying.
+ */
+static ssize_t
+lwip_recv_tcp(struct lwip_sock *sock, void *mem, size_t len, int flags)
+{
+  u8_t apiflags = NETCONN_NOAUTORCVD;
+  ssize_t recvd = 0;
+  ssize_t recv_left = (len <= SSIZE_MAX) ? (ssize_t)len : SSIZE_MAX;
+
+  LWIP_ASSERT("no socket given", sock != NULL);
+  LWIP_ASSERT("this should be checked internally", NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP);
+
+  if (flags & MSG_DONTWAIT) {
+    apiflags |= NETCONN_DONTBLOCK;
+  }
+
+  do {
+    struct pbuf *p;
+    err_t err;
+    u16_t copylen;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: top while sock->lastdata=%p\n", (void *)sock->lastdata.pbuf));
+    /* Check if there is data left from the last recv operation. */
+    if (sock->lastdata.pbuf) {
+      p = sock->lastdata.pbuf;
+    } else {
+      /* No data was left from the previous operation, so we try to get
+         some from the network. */
+      err = netconn_recv_tcp_pbuf_flags(sock->conn, &p, apiflags);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: netconn_recv err=%d, pbuf=%p\n",
+                                  err, (void *)p));
+
+      if (err != ERR_OK) {
+        if (recvd > 0) {
+          /* already received data, return that (this trusts in getting the same error from
+             netconn layer again next time netconn_recv is called) */
+          goto lwip_recv_tcp_done;
+        }
+        /* We should really do some error checking here. */
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: p == NULL, error is \"%s\"!\n",
+                                    lwip_strerr(err)));
+        sock_set_errno(sock, err_to_errno(err));
+        if (err == ERR_CLSD) {
+          return 0;
+        } else {
+          return -1;
+        }
+      }
+      LWIP_ASSERT("p != NULL", p != NULL);
+      sock->lastdata.pbuf = p;
+    }
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: buflen=%"U16_F" recv_left=%d off=%d\n",
+                                p->tot_len, (int)recv_left, (int)recvd));
+
+    if (recv_left > p->tot_len) {
+      copylen = p->tot_len;
+    } else {
+      copylen = (u16_t)recv_left;
+    }
+    if (recvd + copylen < recvd) {
+      /* overflow */
+      copylen = (u16_t)(SSIZE_MAX - recvd);
+    }
+
+    /* copy the contents of the received buffer into
+    the supplied memory pointer mem */
+    pbuf_copy_partial(p, (u8_t *)mem + recvd, copylen, 0);
+
+    recvd += copylen;
+
+    /* TCP combines multiple pbufs for one recv */
+    LWIP_ASSERT("invalid copylen, len would underflow", recv_left >= copylen);
+    recv_left -= copylen;
+
+    /* Unless we peek the incoming message... */
+    if ((flags & MSG_PEEK) == 0) {
+      /* ... check if there is data left in the pbuf */
+      LWIP_ASSERT("invalid copylen", p->tot_len >= copylen);
+      if (p->tot_len - copylen > 0) {
+        /* If so, it should be saved in the sock structure for the next recv call.
+           We store the pbuf but hide/free the consumed data: */
+        sock->lastdata.pbuf = pbuf_free_header(p, copylen);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: lastdata now pbuf=%p\n", (void *)sock->lastdata.pbuf));
+      } else {
+        sock->lastdata.pbuf = NULL;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: deleting pbuf=%p\n", (void *)p));
+        pbuf_free(p);
+      }
+    }
+    /* once we have some data to return, only add more if we don't need to wait */
+    apiflags |= NETCONN_DONTBLOCK | NETCONN_NOFIN;
+    /* @todo: do we need to support peeking more than one pbuf? */
+  } while ((recv_left > 0) && !(flags & MSG_PEEK));
+lwip_recv_tcp_done:
+  if ((recvd > 0) && !(flags & MSG_PEEK)) {
+    /* ensure window update after copying all data */
+    netconn_tcp_recvd(sock->conn, (size_t)recvd);
+  }
+  sock_set_errno(sock, 0);
+  return recvd;
+}
+#endif
+
+/* Convert a netbuf's address data to struct sockaddr */
+static int
+lwip_sock_make_addr(struct netconn *conn, ip_addr_t *fromaddr, u16_t port,
+                    struct sockaddr *from, socklen_t *fromlen)
+{
+  int truncated = 0;
+  union sockaddr_aligned saddr;
+
+  LWIP_UNUSED_ARG(conn);
+
+  LWIP_ASSERT("fromaddr != NULL", fromaddr != NULL);
+  LWIP_ASSERT("from != NULL", from != NULL);
+  LWIP_ASSERT("fromlen != NULL", fromlen != NULL);
+
+#if LWIP_IPV4 && LWIP_IPV6
+  /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */
+  if (NETCONNTYPE_ISIPV6(netconn_type(conn)) && IP_IS_V4(fromaddr)) {
+    ip4_2_ipv4_mapped_ipv6(ip_2_ip6(fromaddr), ip_2_ip4(fromaddr));
+    IP_SET_TYPE(fromaddr, IPADDR_TYPE_V6);
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+  IPADDR_PORT_TO_SOCKADDR(&saddr, fromaddr, port);
+  if (*fromlen < saddr.sa.sa_len) {
+    truncated = 1;
+  } else if (*fromlen > saddr.sa.sa_len) {
+    *fromlen = saddr.sa.sa_len;
+  }
+  MEMCPY(from, &saddr, *fromlen);
+  return truncated;
+}
+
+#if LWIP_TCP
+/* Helper function to get a tcp socket's remote address info */
+static int
+lwip_recv_tcp_from(struct lwip_sock *sock, struct sockaddr *from, socklen_t *fromlen, const char *dbg_fn, int dbg_s, ssize_t dbg_ret)
+{
+  if (sock == NULL) {
+    return 0;
+  }
+  LWIP_UNUSED_ARG(dbg_fn);
+  LWIP_UNUSED_ARG(dbg_s);
+  LWIP_UNUSED_ARG(dbg_ret);
+
+#if !SOCKETS_DEBUG
+  if (from && fromlen)
+#endif /* !SOCKETS_DEBUG */
+  {
+    /* get remote addr/port from tcp_pcb */
+    u16_t port;
+    ip_addr_t tmpaddr;
+    netconn_getaddr(sock->conn, &tmpaddr, &port, 0);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("%s(%d):  addr=", dbg_fn, dbg_s));
+    ip_addr_debug_print_val(SOCKETS_DEBUG, tmpaddr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, (int)dbg_ret));
+    if (from && fromlen) {
+      return lwip_sock_make_addr(sock->conn, &tmpaddr, port, from, fromlen);
+    }
+  }
+  return 0;
+}
+#endif
+
+/* Helper function to receive a netbuf from a udp or raw netconn.
+ * Keeps sock->lastdata for peeking.
+ */
+static err_t
+lwip_recvfrom_udp_raw(struct lwip_sock *sock, int flags, struct msghdr *msg, u16_t *datagram_len, int dbg_s)
+{
+  struct netbuf *buf;
+  u8_t apiflags;
+  err_t err;
+  u16_t buflen, copylen, copied;
+  int i;
+
+  LWIP_UNUSED_ARG(dbg_s);
+  LWIP_ERROR("lwip_recvfrom_udp_raw: invalid arguments", (msg->msg_iov != NULL) || (msg->msg_iovlen <= 0), return ERR_ARG;);
+
+  if (flags & MSG_DONTWAIT) {
+    apiflags = NETCONN_DONTBLOCK;
+  } else {
+    apiflags = 0;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw[UDP/RAW]: top sock->lastdata=%p\n", (void *)sock->lastdata.netbuf));
+  /* Check if there is data left from the last recv operation. */
+  buf = sock->lastdata.netbuf;
+  if (buf == NULL) {
+    /* No data was left from the previous operation, so we try to get
+        some from the network. */
+    err = netconn_recv_udp_raw_netbuf_flags(sock->conn, &buf, apiflags);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw[UDP/RAW]: netconn_recv err=%d, netbuf=%p\n",
+                                err, (void *)buf));
+
+    if (err != ERR_OK) {
+      return err;
+    }
+    LWIP_ASSERT("buf != NULL", buf != NULL);
+    sock->lastdata.netbuf = buf;
+  }
+  buflen = buf->p->tot_len;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw: buflen=%"U16_F"\n", buflen));
+
+  copied = 0;
+  /* copy the pbuf payload into the iovs */
+  for (i = 0; (i < msg->msg_iovlen) && (copied < buflen); i++) {
+    u16_t len_left = (u16_t)(buflen - copied);
+    if (msg->msg_iov[i].iov_len > len_left) {
+      copylen = len_left;
+    } else {
+      copylen = (u16_t)msg->msg_iov[i].iov_len;
+    }
+
+    /* copy the contents of the received buffer into
+        the supplied memory buffer */
+    pbuf_copy_partial(buf->p, (u8_t *)msg->msg_iov[i].iov_base, copylen, copied);
+    copied = (u16_t)(copied + copylen);
+  }
+
+  /* Check to see from where the data was.*/
+#if !SOCKETS_DEBUG
+  if (msg->msg_name && msg->msg_namelen)
+#endif /* !SOCKETS_DEBUG */
+  {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw(%d):  addr=", dbg_s));
+    ip_addr_debug_print_val(SOCKETS_DEBUG, *netbuf_fromaddr(buf));
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", netbuf_fromport(buf), copied));
+    if (msg->msg_name && msg->msg_namelen) {
+      lwip_sock_make_addr(sock->conn, netbuf_fromaddr(buf), netbuf_fromport(buf),
+                          (struct sockaddr *)msg->msg_name, &msg->msg_namelen);
+    }
+  }
+
+  /* Initialize flag output */
+  msg->msg_flags = 0;
+
+  if (msg->msg_control) {
+    u8_t wrote_msg = 0;
+#if LWIP_NETBUF_RECVINFO
+    /* Check if packet info was recorded */
+    if (buf->flags & NETBUF_FLAG_DESTADDR) {
+      if (IP_IS_V4(&buf->toaddr)) {
+#if LWIP_IPV4
+        if (msg->msg_controllen >= CMSG_SPACE(sizeof(struct in_pktinfo))) {
+          struct cmsghdr *chdr = CMSG_FIRSTHDR(msg); /* This will always return a header!! */
+          struct in_pktinfo *pkti = (struct in_pktinfo *)CMSG_DATA(chdr);
+          chdr->cmsg_level = IPPROTO_IP;
+          chdr->cmsg_type = IP_PKTINFO;
+          chdr->cmsg_len = CMSG_LEN(sizeof(struct in_pktinfo));
+          pkti->ipi_ifindex = buf->p->if_idx;
+          inet_addr_from_ip4addr(&pkti->ipi_addr, ip_2_ip4(netbuf_destaddr(buf)));
+          msg->msg_controllen = CMSG_SPACE(sizeof(struct in_pktinfo));
+          wrote_msg = 1;
+        } else {
+          msg->msg_flags |= MSG_CTRUNC;
+        }
+#endif /* LWIP_IPV4 */
+      }
+    }
+#endif /* LWIP_NETBUF_RECVINFO */
+
+    if (!wrote_msg) {
+      msg->msg_controllen = 0;
+    }
+  }
+
+  /* If we don't peek the incoming message: zero lastdata pointer and free the netbuf */
+  if ((flags & MSG_PEEK) == 0) {
+    sock->lastdata.netbuf = NULL;
+    netbuf_delete(buf);
+  }
+  if (datagram_len) {
+    *datagram_len = buflen;
+  }
+  return ERR_OK;
+}
+
+ssize_t
+lwip_recvfrom(int s, void *mem, size_t len, int flags,
+              struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_sock *sock;
+  ssize_t ret;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+#if LWIP_TCP
+  if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) {
+    ret = lwip_recv_tcp(sock, mem, len, flags);
+    lwip_recv_tcp_from(sock, from, fromlen, "lwip_recvfrom", s, ret);
+    done_socket(sock);
+    return ret;
+  } else
+#endif
+  {
+    u16_t datagram_len = 0;
+    struct iovec vec;
+    struct msghdr msg;
+    err_t err;
+    vec.iov_base = mem;
+    vec.iov_len = len;
+    msg.msg_control = NULL;
+    msg.msg_controllen = 0;
+    msg.msg_flags = 0;
+    msg.msg_iov = &vec;
+    msg.msg_iovlen = 1;
+    msg.msg_name = from;
+    msg.msg_namelen = (fromlen ? *fromlen : 0);
+    err = lwip_recvfrom_udp_raw(sock, flags, &msg, &datagram_len, s);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom[UDP/RAW](%d): buf == NULL, error is \"%s\"!\n",
+                                  s, lwip_strerr(err)));
+      sock_set_errno(sock, err_to_errno(err));
+      done_socket(sock);
+      return -1;
+    }
+    ret = (ssize_t)LWIP_MIN(LWIP_MIN(len, datagram_len), SSIZE_MAX);
+    if (fromlen) {
+      *fromlen = msg.msg_namelen;
+    }
+  }
+
+  sock_set_errno(sock, 0);
+  done_socket(sock);
+  return ret;
+}
+
+ssize_t
+lwip_read(int s, void *mem, size_t len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+ssize_t
+lwip_readv(int s, const struct iovec *iov, int iovcnt)
+{
+  struct msghdr msg;
+
+  msg.msg_name = NULL;
+  msg.msg_namelen = 0;
+  /* Hack: we have to cast via number to cast from 'const' pointer to non-const.
+     Blame the opengroup standard for this inconsistency. */
+  msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov);
+  msg.msg_iovlen = iovcnt;
+  msg.msg_control = NULL;
+  msg.msg_controllen = 0;
+  msg.msg_flags = 0;
+  return lwip_recvmsg(s, &msg, 0);
+}
+
+ssize_t
+lwip_recv(int s, void *mem, size_t len, int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+ssize_t
+lwip_recvmsg(int s, struct msghdr *message, int flags)
+{
+  struct lwip_sock *sock;
+  int i;
+  ssize_t buflen;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvmsg(%d, message=%p, flags=0x%x)\n", s, (void *)message, flags));
+  LWIP_ERROR("lwip_recvmsg: invalid message pointer", message != NULL, return ERR_ARG;);
+  LWIP_ERROR("lwip_recvmsg: unsupported flags", (flags & ~(MSG_PEEK|MSG_DONTWAIT)) == 0,
+             set_errno(EOPNOTSUPP); return -1;);
+
+  if ((message->msg_iovlen <= 0) || (message->msg_iovlen > IOV_MAX)) {
+    set_errno(EMSGSIZE);
+    return -1;
+  }
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* check for valid vectors */
+  buflen = 0;
+  for (i = 0; i < message->msg_iovlen; i++) {
+    if ((message->msg_iov[i].iov_base == NULL) || ((ssize_t)message->msg_iov[i].iov_len <= 0) ||
+        ((size_t)(ssize_t)message->msg_iov[i].iov_len != message->msg_iov[i].iov_len) ||
+        ((ssize_t)(buflen + (ssize_t)message->msg_iov[i].iov_len) <= 0)) {
+      sock_set_errno(sock, err_to_errno(ERR_VAL));
+      done_socket(sock);
+      return -1;
+    }
+    buflen = (ssize_t)(buflen + (ssize_t)message->msg_iov[i].iov_len);
+  }
+
+  if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) {
+#if LWIP_TCP
+    int recv_flags = flags;
+    message->msg_flags = 0;
+    /* recv the data */
+    buflen = 0;
+    for (i = 0; i < message->msg_iovlen; i++) {
+      /* try to receive into this vector's buffer */
+      ssize_t recvd_local = lwip_recv_tcp(sock, message->msg_iov[i].iov_base, message->msg_iov[i].iov_len, recv_flags);
+      if (recvd_local > 0) {
+        /* sum up received bytes */
+        buflen += recvd_local;
+      }
+      if ((recvd_local < 0) || (recvd_local < (int)message->msg_iov[i].iov_len) ||
+          (flags & MSG_PEEK)) {
+        /* returned prematurely (or peeking, which might actually be limitated to the first iov) */
+        if (buflen <= 0) {
+          /* nothing received at all, propagate the error */
+          buflen = recvd_local;
+        }
+        break;
+      }
+      /* pass MSG_DONTWAIT to lwip_recv_tcp() to prevent waiting for more data */
+      recv_flags |= MSG_DONTWAIT;
+    }
+    if (buflen > 0) {
+      /* reset socket error since we have received something */
+      sock_set_errno(sock, 0);
+    }
+    /* " If the socket is connected, the msg_name and msg_namelen members shall be ignored." */
+    done_socket(sock);
+    return buflen;
+#else /* LWIP_TCP */
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    done_socket(sock);
+    return -1;
+#endif /* LWIP_TCP */
+  }
+  /* else, UDP and RAW NETCONNs */
+#if LWIP_UDP || LWIP_RAW
+  {
+    u16_t datagram_len = 0;
+    err_t err;
+    err = lwip_recvfrom_udp_raw(sock, flags, message, &datagram_len, s);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvmsg[UDP/RAW](%d): buf == NULL, error is \"%s\"!\n",
+                                  s, lwip_strerr(err)));
+      sock_set_errno(sock, err_to_errno(err));
+      done_socket(sock);
+      return -1;
+    }
+    if (datagram_len > buflen) {
+      message->msg_flags |= MSG_TRUNC;
+    }
+
+    sock_set_errno(sock, 0);
+    done_socket(sock);
+    return (int)datagram_len;
+  }
+#else /* LWIP_UDP || LWIP_RAW */
+  sock_set_errno(sock, err_to_errno(ERR_ARG));
+  done_socket(sock);
+  return -1;
+#endif /* LWIP_UDP || LWIP_RAW */
+}
+
+ssize_t
+lwip_send(int s, const void *data, size_t size, int flags)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  u8_t write_flags;
+  size_t written;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n",
+                              s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) {
+#if (LWIP_UDP || LWIP_RAW)
+    done_socket(sock);
+    return lwip_sendto(s, data, size, flags, NULL, 0);
+#else /* (LWIP_UDP || LWIP_RAW) */
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    done_socket(sock);
+    return -1;
+#endif /* (LWIP_UDP || LWIP_RAW) */
+  }
+
+  write_flags = (u8_t)(NETCONN_COPY |
+                       ((flags & MSG_MORE)     ? NETCONN_MORE      : 0) |
+                       ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0));
+  written = 0;
+  err = netconn_write_partly(sock->conn, data, size, write_flags, &written);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d written=%"SZT_F"\n", s, err, written));
+  sock_set_errno(sock, err_to_errno(err));
+  done_socket(sock);
+  /* casting 'written' to ssize_t is OK here since the netconn API limits it to SSIZE_MAX */
+  return (err == ERR_OK ? (ssize_t)written : -1);
+}
+
+ssize_t
+lwip_sendmsg(int s, const struct msghdr *msg, int flags)
+{
+  struct lwip_sock *sock;
+#if LWIP_TCP
+  u8_t write_flags;
+  size_t written;
+#endif
+  err_t err = ERR_OK;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  LWIP_ERROR("lwip_sendmsg: invalid msghdr", msg != NULL,
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;);
+  LWIP_ERROR("lwip_sendmsg: invalid msghdr iov", msg->msg_iov != NULL,
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;);
+  LWIP_ERROR("lwip_sendmsg: maximum iovs exceeded", (msg->msg_iovlen > 0) && (msg->msg_iovlen <= IOV_MAX),
+             sock_set_errno(sock, EMSGSIZE); done_socket(sock); return -1;);
+  LWIP_ERROR("lwip_sendmsg: unsupported flags", (flags & ~(MSG_DONTWAIT | MSG_MORE)) == 0,
+             sock_set_errno(sock, EOPNOTSUPP); done_socket(sock); return -1;);
+
+  LWIP_UNUSED_ARG(msg->msg_control);
+  LWIP_UNUSED_ARG(msg->msg_controllen);
+  LWIP_UNUSED_ARG(msg->msg_flags);
+
+  if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) {
+#if LWIP_TCP
+    write_flags = (u8_t)(NETCONN_COPY |
+                         ((flags & MSG_MORE)     ? NETCONN_MORE      : 0) |
+                         ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0));
+
+    written = 0;
+    err = netconn_write_vectors_partly(sock->conn, (struct netvector *)msg->msg_iov, (u16_t)msg->msg_iovlen, write_flags, &written);
+    sock_set_errno(sock, err_to_errno(err));
+    done_socket(sock);
+    /* casting 'written' to ssize_t is OK here since the netconn API limits it to SSIZE_MAX */
+    return (err == ERR_OK ? (ssize_t)written : -1);
+#else /* LWIP_TCP */
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    done_socket(sock);
+    return -1;
+#endif /* LWIP_TCP */
+  }
+  /* else, UDP and RAW NETCONNs */
+#if LWIP_UDP || LWIP_RAW
+  {
+    struct netbuf chain_buf;
+    int i;
+    ssize_t size = 0;
+
+    LWIP_UNUSED_ARG(flags);
+    LWIP_ERROR("lwip_sendmsg: invalid msghdr name", (((msg->msg_name == NULL) && (msg->msg_namelen == 0)) ||
+               IS_SOCK_ADDR_LEN_VALID(msg->msg_namelen)),
+               sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;);
+
+    /* initialize chain buffer with destination */
+    memset(&chain_buf, 0, sizeof(struct netbuf));
+    if (msg->msg_name) {
+      u16_t remote_port;
+      SOCKADDR_TO_IPADDR_PORT((const struct sockaddr *)msg->msg_name, &chain_buf.addr, remote_port);
+      netbuf_fromport(&chain_buf) = remote_port;
+    }
+#if LWIP_NETIF_TX_SINGLE_PBUF
+    for (i = 0; i < msg->msg_iovlen; i++) {
+      size += msg->msg_iov[i].iov_len;
+      if ((msg->msg_iov[i].iov_len > INT_MAX) || (size < (int)msg->msg_iov[i].iov_len)) {
+        /* overflow */
+        goto sendmsg_emsgsize;
+      }
+    }
+    if (size > 0xFFFF) {
+      /* overflow */
+      goto sendmsg_emsgsize;
+    }
+    /* Allocate a new netbuf and copy the data into it. */
+    if (netbuf_alloc(&chain_buf, (u16_t)size) == NULL) {
+      err = ERR_MEM;
+    } else {
+      /* flatten the IO vectors */
+      size_t offset = 0;
+      for (i = 0; i < msg->msg_iovlen; i++) {
+        MEMCPY(&((u8_t *)chain_buf.p->payload)[offset], msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len);
+        offset += msg->msg_iov[i].iov_len;
+      }
+#if LWIP_CHECKSUM_ON_COPY
+      {
+        /* This can be improved by using LWIP_CHKSUM_COPY() and aggregating the checksum for each IO vector */
+        u16_t chksum = ~inet_chksum_pbuf(chain_buf.p);
+        netbuf_set_chksum(&chain_buf, chksum);
+      }
+#endif /* LWIP_CHECKSUM_ON_COPY */
+      err = ERR_OK;
+    }
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+    /* create a chained netbuf from the IO vectors. NOTE: we assemble a pbuf chain
+       manually to avoid having to allocate, chain, and delete a netbuf for each iov */
+    for (i = 0; i < msg->msg_iovlen; i++) {
+      struct pbuf *p;
+      if (msg->msg_iov[i].iov_len > 0xFFFF) {
+        /* overflow */
+        goto sendmsg_emsgsize;
+      }
+      p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+      if (p == NULL) {
+        err = ERR_MEM; /* let netbuf_delete() cleanup chain_buf */
+        break;
+      }
+      p->payload = msg->msg_iov[i].iov_base;
+      p->len = p->tot_len = (u16_t)msg->msg_iov[i].iov_len;
+      /* netbuf empty, add new pbuf */
+      if (chain_buf.p == NULL) {
+        chain_buf.p = chain_buf.ptr = p;
+        /* add pbuf to existing pbuf chain */
+      } else {
+        if (chain_buf.p->tot_len + p->len > 0xffff) {
+          /* overflow */
+          pbuf_free(p);
+          goto sendmsg_emsgsize;
+        }
+        pbuf_cat(chain_buf.p, p);
+      }
+    }
+    /* save size of total chain */
+    if (err == ERR_OK) {
+      size = netbuf_len(&chain_buf);
+    }
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+    if (err == ERR_OK) {
+#if LWIP_IPV4 && LWIP_IPV6
+      /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */
+      if (IP_IS_V6_VAL(chain_buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&chain_buf.addr))) {
+        unmap_ipv4_mapped_ipv6(ip_2_ip4(&chain_buf.addr), ip_2_ip6(&chain_buf.addr));
+        IP_SET_TYPE_VAL(chain_buf.addr, IPADDR_TYPE_V4);
+      }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+      /* send the data */
+      err = netconn_send(sock->conn, &chain_buf);
+    }
+
+    /* deallocated the buffer */
+    netbuf_free(&chain_buf);
+
+    sock_set_errno(sock, err_to_errno(err));
+    done_socket(sock);
+    return (err == ERR_OK ? size : -1);
+sendmsg_emsgsize:
+    sock_set_errno(sock, EMSGSIZE);
+    netbuf_free(&chain_buf);
+    done_socket(sock);
+    return -1;
+  }
+#else /* LWIP_UDP || LWIP_RAW */
+  sock_set_errno(sock, err_to_errno(ERR_ARG));
+  done_socket(sock);
+  return -1;
+#endif /* LWIP_UDP || LWIP_RAW */
+}
+
+ssize_t
+lwip_sendto(int s, const void *data, size_t size, int flags,
+            const struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  u16_t short_size;
+  u16_t remote_port;
+  struct netbuf buf;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) {
+#if LWIP_TCP
+    done_socket(sock);
+    return lwip_send(s, data, size, flags);
+#else /* LWIP_TCP */
+    LWIP_UNUSED_ARG(flags);
+    sock_set_errno(sock, err_to_errno(ERR_ARG));
+    done_socket(sock);
+    return -1;
+#endif /* LWIP_TCP */
+  }
+
+  if (size > LWIP_MIN(0xFFFF, SSIZE_MAX)) {
+    /* cannot fit into one datagram (at least for us) */
+    sock_set_errno(sock, EMSGSIZE);
+    done_socket(sock);
+    return -1;
+  }
+  short_size = (u16_t)size;
+  LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) ||
+             (IS_SOCK_ADDR_LEN_VALID(tolen) &&
+              ((to != NULL) && (IS_SOCK_ADDR_TYPE_VALID(to) && IS_SOCK_ADDR_ALIGNED(to))))),
+             sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;);
+  LWIP_UNUSED_ARG(tolen);
+
+  /* initialize a buffer */
+  buf.p = buf.ptr = NULL;
+#if LWIP_CHECKSUM_ON_COPY
+  buf.flags = 0;
+#endif /* LWIP_CHECKSUM_ON_COPY */
+  if (to) {
+    SOCKADDR_TO_IPADDR_PORT(to, &buf.addr, remote_port);
+  } else {
+    remote_port = 0;
+    ip_addr_set_any(NETCONNTYPE_ISIPV6(netconn_type(sock->conn)), &buf.addr);
+  }
+  netbuf_fromport(&buf) = remote_port;
+
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=",
+                              s, data, short_size, flags));
+  ip_addr_debug_print_val(SOCKETS_DEBUG, buf.addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port));
+
+  /* make the buffer point to the data that should be sent */
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  /* Allocate a new netbuf and copy the data into it. */
+  if (netbuf_alloc(&buf, short_size) == NULL) {
+    err = ERR_MEM;
+  } else {
+#if LWIP_CHECKSUM_ON_COPY
+    if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_RAW) {
+      u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size);
+      netbuf_set_chksum(&buf, chksum);
+    } else
+#endif /* LWIP_CHECKSUM_ON_COPY */
+    {
+      MEMCPY(buf.p->payload, data, short_size);
+    }
+    err = ERR_OK;
+  }
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+  err = netbuf_ref(&buf, data, short_size);
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+  if (err == ERR_OK) {
+#if LWIP_IPV4 && LWIP_IPV6
+    /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */
+    if (IP_IS_V6_VAL(buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&buf.addr))) {
+      unmap_ipv4_mapped_ipv6(ip_2_ip4(&buf.addr), ip_2_ip6(&buf.addr));
+      IP_SET_TYPE_VAL(buf.addr, IPADDR_TYPE_V4);
+    }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+    /* send the data */
+    err = netconn_send(sock->conn, &buf);
+  }
+
+  /* deallocated the buffer */
+  netbuf_free(&buf);
+
+  sock_set_errno(sock, err_to_errno(err));
+  done_socket(sock);
+  return (err == ERR_OK ? short_size : -1);
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  LWIP_UNUSED_ARG(domain); /* @todo: check this */
+
+  /* create a netconn */
+  switch (type) {
+    case SOCK_RAW:
+      conn = netconn_new_with_proto_and_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_RAW),
+             (u8_t)protocol, DEFAULT_SOCKET_EVENTCB);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ",
+                                  domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+      break;
+    case SOCK_DGRAM:
+      conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain,
+                                       ((protocol == IPPROTO_UDPLITE) ? NETCONN_UDPLITE : NETCONN_UDP)),
+                                       DEFAULT_SOCKET_EVENTCB);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ",
+                                  domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+#if LWIP_NETBUF_RECVINFO
+      if (conn) {
+        /* netconn layer enables pktinfo by default, sockets default to off */
+        conn->flags &= ~NETCONN_FLAG_PKTINFO;
+      }
+#endif /* LWIP_NETBUF_RECVINFO */
+      break;
+    case SOCK_STREAM:
+      conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_TCP), DEFAULT_SOCKET_EVENTCB);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ",
+                                  domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n",
+                                  domain, type, protocol));
+      set_errno(EINVAL);
+      return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn, 0);
+
+  if (i == -1) {
+    netconn_delete(conn);
+    set_errno(ENFILE);
+    return -1;
+  }
+  conn->socket = i;
+  done_socket(&sockets[i - LWIP_SOCKET_OFFSET]);
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+ssize_t
+lwip_write(int s, const void *data, size_t size)
+{
+  return lwip_send(s, data, size, 0);
+}
+
+ssize_t
+lwip_writev(int s, const struct iovec *iov, int iovcnt)
+{
+  struct msghdr msg;
+
+  msg.msg_name = NULL;
+  msg.msg_namelen = 0;
+  /* Hack: we have to cast via number to cast from 'const' pointer to non-const.
+     Blame the opengroup standard for this inconsistency. */
+  msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov);
+  msg.msg_iovlen = iovcnt;
+  msg.msg_control = NULL;
+  msg.msg_controllen = 0;
+  msg.msg_flags = 0;
+  return lwip_sendmsg(s, &msg, 0);
+}
+
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+/* Add select_cb to select_cb_list. */
+static void
+lwip_link_select_cb(struct lwip_select_cb *select_cb)
+{
+  LWIP_SOCKET_SELECT_DECL_PROTECT(lev);
+
+  /* Protect the select_cb_list */
+  LWIP_SOCKET_SELECT_PROTECT(lev);
+
+  /* Put this select_cb on top of list */
+  select_cb->next = select_cb_list;
+  if (select_cb_list != NULL) {
+    select_cb_list->prev = select_cb;
+  }
+  select_cb_list = select_cb;
+#if !LWIP_TCPIP_CORE_LOCKING
+  /* Increasing this counter tells select_check_waiters that the list has changed. */
+  select_cb_ctr++;
+#endif
+
+  /* Now we can safely unprotect */
+  LWIP_SOCKET_SELECT_UNPROTECT(lev);
+}
+
+/* Remove select_cb from select_cb_list. */
+static void
+lwip_unlink_select_cb(struct lwip_select_cb *select_cb)
+{
+  LWIP_SOCKET_SELECT_DECL_PROTECT(lev);
+
+  /* Take us off the list */
+  LWIP_SOCKET_SELECT_PROTECT(lev);
+  if (select_cb->next != NULL) {
+    select_cb->next->prev = select_cb->prev;
+  }
+  if (select_cb_list == select_cb) {
+    LWIP_ASSERT("select_cb->prev == NULL", select_cb->prev == NULL);
+    select_cb_list = select_cb->next;
+  } else {
+    LWIP_ASSERT("select_cb->prev != NULL", select_cb->prev != NULL);
+    select_cb->prev->next = select_cb->next;
+  }
+#if !LWIP_TCPIP_CORE_LOCKING
+  /* Increasing this counter tells select_check_waiters that the list has changed. */
+  select_cb_ctr++;
+#endif
+  LWIP_SOCKET_SELECT_UNPROTECT(lev);
+}
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+
+#if LWIP_SOCKET_SELECT
+/**
+ * Go through the readset and writeset lists and see which socket of the sockets
+ * set in the sets has events. On return, readset, writeset and exceptset have
+ * the sockets enabled that had events.
+ *
+ * @param maxfdp1 the highest socket index in the sets
+ * @param readset_in    set of sockets to check for read events
+ * @param writeset_in   set of sockets to check for write events
+ * @param exceptset_in  set of sockets to check for error events
+ * @param readset_out   set of sockets that had read events
+ * @param writeset_out  set of sockets that had write events
+ * @param exceptset_out set os sockets that had error events
+ * @return number of sockets that had events (read/write/exception) (>= 0)
+ */
+static int
+lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in,
+             fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out)
+{
+  int i, nready = 0;
+  fd_set lreadset, lwriteset, lexceptset;
+  struct lwip_sock *sock;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  FD_ZERO(&lreadset);
+  FD_ZERO(&lwriteset);
+  FD_ZERO(&lexceptset);
+
+  /* Go through each socket in each list to count number of sockets which
+     currently match */
+  for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) {
+    /* if this FD is not in the set, continue */
+    if (!(readset_in && FD_ISSET(i, readset_in)) &&
+        !(writeset_in && FD_ISSET(i, writeset_in)) &&
+        !(exceptset_in && FD_ISSET(i, exceptset_in))) {
+      continue;
+    }
+    /* First get the socket's status (protected)... */
+    SYS_ARCH_PROTECT(lev);
+    sock = tryget_socket_unconn_locked(i);
+    if (sock != NULL) {
+      void *lastdata = sock->lastdata.pbuf;
+      s16_t rcvevent = sock->rcvevent;
+      u16_t sendevent = sock->sendevent;
+      u16_t errevent = sock->errevent;
+      SYS_ARCH_UNPROTECT(lev);
+
+      /* ... then examine it: */
+      /* See if netconn of this socket is ready for read */
+      if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) {
+        FD_SET(i, &lreadset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+        nready++;
+      }
+      /* See if netconn of this socket is ready for write */
+      if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) {
+        FD_SET(i, &lwriteset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+        nready++;
+      }
+      /* See if netconn of this socket had an error */
+      if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) {
+        FD_SET(i, &lexceptset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i));
+        nready++;
+      }
+      done_socket(sock);
+    } else {
+      SYS_ARCH_UNPROTECT(lev);
+      /* no a valid open socket */
+      return -1;
+    }
+  }
+  /* copy local sets to the ones provided as arguments */
+  *readset_out = lreadset;
+  *writeset_out = lwriteset;
+  *exceptset_out = lexceptset;
+
+  LWIP_ASSERT("nready >= 0", nready >= 0);
+  return nready;
+}
+
+#if LWIP_NETCONN_FULLDUPLEX
+/* Mark all of the set sockets in one of the three fdsets passed to select as used.
+ * All sockets are marked (and later unmarked), whether they are open or not.
+ * This is OK as lwip_selscan aborts select when non-open sockets are found.
+ */
+static void
+lwip_select_inc_sockets_used_set(int maxfdp, fd_set *fdset, fd_set *used_sockets)
+{
+  SYS_ARCH_DECL_PROTECT(lev);
+  if (fdset) {
+    int i;
+    for (i = LWIP_SOCKET_OFFSET; i < maxfdp; i++) {
+      /* if this FD is in the set, lock it (unless already done) */
+      if (FD_ISSET(i, fdset) && !FD_ISSET(i, used_sockets)) {
+        struct lwip_sock *sock;
+        SYS_ARCH_PROTECT(lev);
+        sock = tryget_socket_unconn_locked(i);
+        if (sock != NULL) {
+          /* leave the socket used until released by lwip_select_dec_sockets_used */
+          FD_SET(i, used_sockets);
+        }
+        SYS_ARCH_UNPROTECT(lev);
+      }
+    }
+  }
+}
+
+/* Mark all sockets passed to select as used to prevent them from being freed
+ * from other threads while select is running.
+ * Marked sockets are added to 'used_sockets' to mark them only once an be able
+ * to unmark them correctly.
+ */
+static void
+lwip_select_inc_sockets_used(int maxfdp, fd_set *fdset1, fd_set *fdset2, fd_set *fdset3, fd_set *used_sockets)
+{
+  FD_ZERO(used_sockets);
+  lwip_select_inc_sockets_used_set(maxfdp, fdset1, used_sockets);
+  lwip_select_inc_sockets_used_set(maxfdp, fdset2, used_sockets);
+  lwip_select_inc_sockets_used_set(maxfdp, fdset3, used_sockets);
+}
+
+/* Let go all sockets that were marked as used when starting select */
+static void
+lwip_select_dec_sockets_used(int maxfdp, fd_set *used_sockets)
+{
+  int i;
+  for (i = LWIP_SOCKET_OFFSET; i < maxfdp; i++) {
+    /* if this FD is not in the set, continue */
+    if (FD_ISSET(i, used_sockets)) {
+      struct lwip_sock *sock = tryget_socket_unconn_nouse(i);
+      LWIP_ASSERT("socket gone at the end of select", sock != NULL);
+      if (sock != NULL) {
+        done_socket(sock);
+      }
+    }
+  }
+}
+#else /* LWIP_NETCONN_FULLDUPLEX */
+#define lwip_select_inc_sockets_used(maxfdp1, readset, writeset, exceptset, used_sockets)
+#define lwip_select_dec_sockets_used(maxfdp1, used_sockets)
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+            struct timeval *timeout)
+{
+  u32_t waitres = 0;
+  int nready;
+  fd_set lreadset, lwriteset, lexceptset;
+  u32_t msectimeout;
+  int i;
+  int maxfdp2;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  int waited = 0;
+#endif
+#if LWIP_NETCONN_FULLDUPLEX
+  fd_set used_sockets;
+#endif
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n",
+                              maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset,
+                              timeout ? (s32_t)timeout->tv_sec : (s32_t) - 1,
+                              timeout ? (s32_t)timeout->tv_usec : (s32_t) - 1));
+
+  if ((maxfdp1 < 0) || (maxfdp1 > LWIP_SELECT_MAXNFDS)) {
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  lwip_select_inc_sockets_used(maxfdp1, readset, writeset, exceptset, &used_sockets);
+
+  /* Go through each socket in each list to count number of sockets which
+     currently match */
+  nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset);
+
+  if (nready < 0) {
+    /* one of the sockets in one of the fd_sets was invalid */
+    set_errno(EBADF);
+    lwip_select_dec_sockets_used(maxfdp1, &used_sockets);
+    return -1;
+  } else if (nready > 0) {
+    /* one or more sockets are set, no need to wait */
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+  } else {
+    /* If we don't have any current events, then suspend if we are supposed to */
+    if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+      /* This is OK as the local fdsets are empty and nready is zero,
+         or we would have returned earlier. */
+    } else {
+      /* None ready: add our semaphore to list:
+         We don't actually need any dynamic memory. Our entry on the
+         list is only valid while we are in this function, so it's ok
+         to use local variables (unless we're running in MPU compatible
+         mode). */
+      API_SELECT_CB_VAR_DECLARE(select_cb);
+      API_SELECT_CB_VAR_ALLOC(select_cb, set_errno(ENOMEM); lwip_select_dec_sockets_used(maxfdp1, &used_sockets); return -1);
+      memset(&API_SELECT_CB_VAR_REF(select_cb), 0, sizeof(struct lwip_select_cb));
+
+      API_SELECT_CB_VAR_REF(select_cb).readset = readset;
+      API_SELECT_CB_VAR_REF(select_cb).writeset = writeset;
+      API_SELECT_CB_VAR_REF(select_cb).exceptset = exceptset;
+#if LWIP_NETCONN_SEM_PER_THREAD
+      API_SELECT_CB_VAR_REF(select_cb).sem = LWIP_NETCONN_THREAD_SEM_GET();
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+      if (sys_sem_new(&API_SELECT_CB_VAR_REF(select_cb).sem, 0) != ERR_OK) {
+        /* failed to create semaphore */
+        set_errno(ENOMEM);
+        lwip_select_dec_sockets_used(maxfdp1, &used_sockets);
+        API_SELECT_CB_VAR_FREE(select_cb);
+        return -1;
+      }
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+      lwip_link_select_cb(&API_SELECT_CB_VAR_REF(select_cb));
+
+      /* Increase select_waiting for each socket we are interested in */
+      maxfdp2 = maxfdp1;
+      for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) {
+        if ((readset && FD_ISSET(i, readset)) ||
+            (writeset && FD_ISSET(i, writeset)) ||
+            (exceptset && FD_ISSET(i, exceptset))) {
+          struct lwip_sock *sock;
+          SYS_ARCH_PROTECT(lev);
+          sock = tryget_socket_unconn_locked(i);
+          if (sock != NULL) {
+            sock->select_waiting++;
+            if (sock->select_waiting == 0) {
+              /* overflow - too many threads waiting */
+              sock->select_waiting--;
+              nready = -1;
+              maxfdp2 = i;
+              SYS_ARCH_UNPROTECT(lev);
+              done_socket(sock);
+              set_errno(EBUSY);
+              break;
+            }
+            SYS_ARCH_UNPROTECT(lev);
+            done_socket(sock);
+          } else {
+            /* Not a valid socket */
+            nready = -1;
+            maxfdp2 = i;
+            SYS_ARCH_UNPROTECT(lev);
+            set_errno(EBADF);
+            break;
+          }
+        }
+      }
+
+      if (nready >= 0) {
+        /* Call lwip_selscan again: there could have been events between
+           the last scan (without us on the list) and putting us on the list! */
+        nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset);
+        if (!nready) {
+          /* Still none ready, just wait to be woken */
+          if (timeout == 0) {
+            /* Wait forever */
+            msectimeout = 0;
+          } else {
+            long msecs_long = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500) / 1000));
+            if (msecs_long <= 0) {
+              /* Wait 1ms at least (0 means wait forever) */
+              msectimeout = 1;
+            } else {
+              msectimeout = (u32_t)msecs_long;
+            }
+          }
+
+          waitres = sys_arch_sem_wait(SELECT_SEM_PTR(API_SELECT_CB_VAR_REF(select_cb).sem), msectimeout);
+#if LWIP_NETCONN_SEM_PER_THREAD
+          waited = 1;
+#endif
+        }
+      }
+
+      /* Decrease select_waiting for each socket we are interested in */
+      for (i = LWIP_SOCKET_OFFSET; i < maxfdp2; i++) {
+        if ((readset && FD_ISSET(i, readset)) ||
+            (writeset && FD_ISSET(i, writeset)) ||
+            (exceptset && FD_ISSET(i, exceptset))) {
+          struct lwip_sock *sock;
+          SYS_ARCH_PROTECT(lev);
+          sock = tryget_socket_unconn_locked(i);
+          if (sock != NULL) {
+            /* for now, handle select_waiting==0... */
+            LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0);
+            if (sock->select_waiting > 0) {
+              sock->select_waiting--;
+            }
+            SYS_ARCH_UNPROTECT(lev);
+            done_socket(sock);
+          } else {
+            SYS_ARCH_UNPROTECT(lev);
+            /* Not a valid socket */
+            nready = -1;
+            set_errno(EBADF);
+          }
+        }
+      }
+
+      lwip_unlink_select_cb(&API_SELECT_CB_VAR_REF(select_cb));
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+      if (API_SELECT_CB_VAR_REF(select_cb).sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) {
+        /* don't leave the thread-local semaphore signalled */
+        sys_arch_sem_wait(API_SELECT_CB_VAR_REF(select_cb).sem, 1);
+      }
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+      sys_sem_free(&API_SELECT_CB_VAR_REF(select_cb).sem);
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+      API_SELECT_CB_VAR_FREE(select_cb);
+
+      if (nready < 0) {
+        /* This happens when a socket got closed while waiting */
+        lwip_select_dec_sockets_used(maxfdp1, &used_sockets);
+        return -1;
+      }
+
+      if (waitres == SYS_ARCH_TIMEOUT) {
+        /* Timeout */
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+        /* This is OK as the local fdsets are empty and nready is zero,
+           or we would have returned earlier. */
+      } else {
+        /* See what's set now after waiting */
+        nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset);
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+      }
+    }
+  }
+
+  lwip_select_dec_sockets_used(maxfdp1, &used_sockets);
+  set_errno(0);
+  if (readset) {
+    *readset = lreadset;
+  }
+  if (writeset) {
+    *writeset = lwriteset;
+  }
+  if (exceptset) {
+    *exceptset = lexceptset;
+  }
+  return nready;
+}
+#endif /* LWIP_SOCKET_SELECT */
+
+#if LWIP_SOCKET_POLL
+/** Options for the lwip_pollscan function. */
+enum lwip_pollscan_opts
+{
+  /** Clear revents in each struct pollfd. */
+  LWIP_POLLSCAN_CLEAR = 1,
+
+  /** Increment select_waiting in each struct lwip_sock. */
+  LWIP_POLLSCAN_INC_WAIT = 2,
+
+  /** Decrement select_waiting in each struct lwip_sock. */
+  LWIP_POLLSCAN_DEC_WAIT = 4
+};
+
+/**
+ * Update revents in each struct pollfd.
+ * Optionally update select_waiting in struct lwip_sock.
+ *
+ * @param fds          array of structures to update
+ * @param nfds         number of structures in fds
+ * @param opts         what to update and how
+ * @return number of structures that have revents != 0
+ */
+static int
+lwip_pollscan(struct pollfd *fds, nfds_t nfds, enum lwip_pollscan_opts opts)
+{
+  int nready = 0;
+  nfds_t fdi;
+  struct lwip_sock *sock;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  /* Go through each struct pollfd in the array. */
+  for (fdi = 0; fdi < nfds; fdi++) {
+    if ((opts & LWIP_POLLSCAN_CLEAR) != 0) {
+      fds[fdi].revents = 0;
+    }
+
+    /* Negative fd means the caller wants us to ignore this struct.
+       POLLNVAL means we already detected that the fd is invalid;
+       if another thread has since opened a new socket with that fd,
+       we must not use that socket. */
+    if (fds[fdi].fd >= 0 && (fds[fdi].revents & POLLNVAL) == 0) {
+      /* First get the socket's status (protected)... */
+      SYS_ARCH_PROTECT(lev);
+      sock = tryget_socket_unconn_locked(fds[fdi].fd);
+      if (sock != NULL) {
+        void* lastdata = sock->lastdata.pbuf;
+        s16_t rcvevent = sock->rcvevent;
+        u16_t sendevent = sock->sendevent;
+        u16_t errevent = sock->errevent;
+
+        if ((opts & LWIP_POLLSCAN_INC_WAIT) != 0) {
+          sock->select_waiting++;
+          if (sock->select_waiting == 0) {
+            /* overflow - too many threads waiting */
+            sock->select_waiting--;
+            nready = -1;
+            SYS_ARCH_UNPROTECT(lev);
+            done_socket(sock);
+            break;
+          }
+        } else if ((opts & LWIP_POLLSCAN_DEC_WAIT) != 0) {
+          /* for now, handle select_waiting==0... */
+          LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0);
+          if (sock->select_waiting > 0) {
+            sock->select_waiting--;
+          }
+        }
+        SYS_ARCH_UNPROTECT(lev);
+        done_socket(sock);
+
+        /* ... then examine it: */
+        /* See if netconn of this socket is ready for read */
+        if ((fds[fdi].events & POLLIN) != 0 && ((lastdata != NULL) || (rcvevent > 0))) {
+          fds[fdi].revents |= POLLIN;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_pollscan: fd=%d ready for reading\n", fds[fdi].fd));
+        }
+        /* See if netconn of this socket is ready for write */
+        if ((fds[fdi].events & POLLOUT) != 0 && (sendevent != 0)) {
+          fds[fdi].revents |= POLLOUT;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_pollscan: fd=%d ready for writing\n", fds[fdi].fd));
+        }
+        /* See if netconn of this socket had an error */
+        if (errevent != 0) {
+          /* POLLERR is output only. */
+          fds[fdi].revents |= POLLERR;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_pollscan: fd=%d ready for exception\n", fds[fdi].fd));
+        }
+      } else {
+        /* Not a valid socket */
+        SYS_ARCH_UNPROTECT(lev);
+        /* POLLNVAL is output only. */
+        fds[fdi].revents |= POLLNVAL;
+        return -1;
+      }
+    }
+
+    /* Will return the number of structures that have events,
+       not the number of events. */
+    if (fds[fdi].revents != 0) {
+      nready++;
+    }
+  }
+
+  LWIP_ASSERT("nready >= 0", nready >= 0);
+  return nready;
+}
+
+#if LWIP_NETCONN_FULLDUPLEX
+/* Mark all sockets as used.
+ *
+ * All sockets are marked (and later unmarked), whether they are open or not.
+ * This is OK as lwip_pollscan aborts select when non-open sockets are found.
+ */
+static void
+lwip_poll_inc_sockets_used(struct pollfd *fds, nfds_t nfds)
+{
+  nfds_t fdi;
+
+  if(fds) {
+    /* Go through each struct pollfd in the array. */
+    for (fdi = 0; fdi < nfds; fdi++) {
+      /* Increase the reference counter */
+      tryget_socket_unconn(fds[fdi].fd);
+    }
+  }
+}
+
+/* Let go all sockets that were marked as used when starting poll */
+static void
+lwip_poll_dec_sockets_used(struct pollfd *fds, nfds_t nfds)
+{
+  nfds_t fdi;
+
+  if(fds) {
+    /* Go through each struct pollfd in the array. */
+    for (fdi = 0; fdi < nfds; fdi++) {
+      struct lwip_sock *sock = tryget_socket_unconn_nouse(fds[fdi].fd);
+      if (sock != NULL) {
+        done_socket(sock);
+      }
+    }
+  }
+}
+#else /* LWIP_NETCONN_FULLDUPLEX */
+#define lwip_poll_inc_sockets_used(fds, nfds)
+#define lwip_poll_dec_sockets_used(fds, nfds)
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+
+int
+lwip_poll(struct pollfd *fds, nfds_t nfds, int timeout)
+{
+  u32_t waitres = 0;
+  int nready;
+  u32_t msectimeout;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  int waited = 0;
+#endif
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll(%p, %d, %d)\n",
+                  (void*)fds, (int)nfds, timeout));
+  LWIP_ERROR("lwip_poll: invalid fds", ((fds != NULL && nfds > 0) || (fds == NULL && nfds == 0)),
+             set_errno(EINVAL); return -1;);
+
+  lwip_poll_inc_sockets_used(fds, nfds);
+
+  /* Go through each struct pollfd to count number of structures
+     which currently match */
+  nready = lwip_pollscan(fds, nfds, LWIP_POLLSCAN_CLEAR);
+
+  if (nready < 0) {
+    lwip_poll_dec_sockets_used(fds, nfds);
+    return -1;
+  }
+
+  /* If we don't have any current events, then suspend if we are supposed to */
+  if (!nready) {
+    API_SELECT_CB_VAR_DECLARE(select_cb);
+
+    if (timeout == 0) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll: no timeout, returning 0\n"));
+      goto return_success;
+    }
+    API_SELECT_CB_VAR_ALLOC(select_cb, set_errno(EAGAIN); lwip_poll_dec_sockets_used(fds, nfds); return -1);
+    memset(&API_SELECT_CB_VAR_REF(select_cb), 0, sizeof(struct lwip_select_cb));
+
+    /* None ready: add our semaphore to list:
+       We don't actually need any dynamic memory. Our entry on the
+       list is only valid while we are in this function, so it's ok
+       to use local variables. */
+
+    API_SELECT_CB_VAR_REF(select_cb).poll_fds = fds;
+    API_SELECT_CB_VAR_REF(select_cb).poll_nfds = nfds;
+#if LWIP_NETCONN_SEM_PER_THREAD
+    API_SELECT_CB_VAR_REF(select_cb).sem = LWIP_NETCONN_THREAD_SEM_GET();
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+    if (sys_sem_new(&API_SELECT_CB_VAR_REF(select_cb).sem, 0) != ERR_OK) {
+      /* failed to create semaphore */
+      set_errno(EAGAIN);
+      lwip_poll_dec_sockets_used(fds, nfds);
+      API_SELECT_CB_VAR_FREE(select_cb);
+      return -1;
+    }
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+    lwip_link_select_cb(&API_SELECT_CB_VAR_REF(select_cb));
+
+    /* Increase select_waiting for each socket we are interested in.
+       Also, check for events again: there could have been events between
+       the last scan (without us on the list) and putting us on the list! */
+    nready = lwip_pollscan(fds, nfds, LWIP_POLLSCAN_INC_WAIT);
+
+    if (!nready) {
+      /* Still none ready, just wait to be woken */
+      if (timeout < 0) {
+        /* Wait forever */
+        msectimeout = 0;
+      } else {
+        /* timeout == 0 would have been handled earlier. */
+        LWIP_ASSERT("timeout > 0", timeout > 0);
+        msectimeout = timeout;
+      }
+      waitres = sys_arch_sem_wait(SELECT_SEM_PTR(API_SELECT_CB_VAR_REF(select_cb).sem), msectimeout);
+#if LWIP_NETCONN_SEM_PER_THREAD
+      waited = 1;
+#endif
+    }
+
+    /* Decrease select_waiting for each socket we are interested in,
+       and check which events occurred while we waited. */
+    nready = lwip_pollscan(fds, nfds, LWIP_POLLSCAN_DEC_WAIT);
+
+    lwip_unlink_select_cb(&API_SELECT_CB_VAR_REF(select_cb));
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+    if (select_cb.sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) {
+      /* don't leave the thread-local semaphore signalled */
+      sys_arch_sem_wait(API_SELECT_CB_VAR_REF(select_cb).sem, 1);
+    }
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+    sys_sem_free(&API_SELECT_CB_VAR_REF(select_cb).sem);
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+    API_SELECT_CB_VAR_FREE(select_cb);
+
+    if (nready < 0) {
+      /* This happens when a socket got closed while waiting */
+      lwip_poll_dec_sockets_used(fds, nfds);
+      return -1;
+    }
+
+    if (waitres == SYS_ARCH_TIMEOUT) {
+      /* Timeout */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll: timeout expired\n"));
+      goto return_success;
+    }
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll: nready=%d\n", nready));
+return_success:
+  lwip_poll_dec_sockets_used(fds, nfds);
+  set_errno(0);
+  return nready;
+}
+
+/**
+ * Check whether event_callback should wake up a thread waiting in
+ * lwip_poll.
+ */
+static int
+lwip_poll_should_wake(const struct lwip_select_cb *scb, int fd, int has_recvevent, int has_sendevent, int has_errevent)
+{
+  nfds_t fdi;
+  for (fdi = 0; fdi < scb->poll_nfds; fdi++) {
+    const struct pollfd *pollfd = &scb->poll_fds[fdi];
+    if (pollfd->fd == fd) {
+      /* Do not update pollfd->revents right here;
+         that would be a data race because lwip_pollscan
+         accesses revents without protecting. */
+      if (has_recvevent && (pollfd->events & POLLIN) != 0) {
+        return 1;
+      }
+      if (has_sendevent && (pollfd->events & POLLOUT) != 0) {
+        return 1;
+      }
+      if (has_errevent) {
+        /* POLLERR is output only. */
+        return 1;
+      }
+    }
+  }
+  return 0;
+}
+#endif /* LWIP_SOCKET_POLL */
+
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+/**
+ * Callback registered in the netconn layer for each socket-netconn.
+ * Processes recvevent (data available) and wakes up tasks waiting for select.
+ *
+ * @note for LWIP_TCPIP_CORE_LOCKING any caller of this function
+ * must have the core lock held when signaling the following events
+ * as they might cause select_list_cb to be checked:
+ *   NETCONN_EVT_RCVPLUS
+ *   NETCONN_EVT_SENDPLUS
+ *   NETCONN_EVT_ERROR
+ * This requirement will be asserted in select_check_waiters()
+ */
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+  int s, check_waiters;
+  struct lwip_sock *sock;
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_UNUSED_ARG(len);
+
+  /* Get socket */
+  if (conn) {
+    s = conn->socket;
+    if (s < 0) {
+      /* Data comes in right away after an accept, even though
+       * the server task might not have created a new socket yet.
+       * Just count down (or up) if that's the case and we
+       * will use the data later. Note that only receive events
+       * can happen before the new socket is set up. */
+      SYS_ARCH_PROTECT(lev);
+      if (conn->socket < 0) {
+        if (evt == NETCONN_EVT_RCVPLUS) {
+          /* conn->socket is -1 on initialization
+             lwip_accept adjusts sock->recvevent if conn->socket < -1 */
+          conn->socket--;
+        }
+        SYS_ARCH_UNPROTECT(lev);
+        return;
+      }
+      s = conn->socket;
+      SYS_ARCH_UNPROTECT(lev);
+    }
+
+    sock = get_socket(s);
+    if (!sock) {
+      return;
+    }
+  } else {
+    return;
+  }
+
+  check_waiters = 1;
+  SYS_ARCH_PROTECT(lev);
+  /* Set event as required */
+  switch (evt) {
+    case NETCONN_EVT_RCVPLUS:
+      sock->rcvevent++;
+      if (sock->rcvevent > 1) {
+        check_waiters = 0;
+      }
+      break;
+    case NETCONN_EVT_RCVMINUS:
+      sock->rcvevent--;
+      check_waiters = 0;
+      break;
+    case NETCONN_EVT_SENDPLUS:
+      if (sock->sendevent) {
+        check_waiters = 0;
+      }
+      sock->sendevent = 1;
+      break;
+    case NETCONN_EVT_SENDMINUS:
+      sock->sendevent = 0;
+      check_waiters = 0;
+      break;
+    case NETCONN_EVT_ERROR:
+      sock->errevent = 1;
+      break;
+    default:
+      LWIP_ASSERT("unknown event", 0);
+      break;
+  }
+
+  if (sock->select_waiting && check_waiters) {
+    /* Save which events are active */
+    int has_recvevent, has_sendevent, has_errevent;
+    has_recvevent = sock->rcvevent > 0;
+    has_sendevent = sock->sendevent != 0;
+    has_errevent = sock->errevent != 0;
+    SYS_ARCH_UNPROTECT(lev);
+    /* Check any select calls waiting on this socket */
+    select_check_waiters(s, has_recvevent, has_sendevent, has_errevent);
+  } else {
+    SYS_ARCH_UNPROTECT(lev);
+  }
+  done_socket(sock);
+}
+
+/**
+ * Check if any select waiters are waiting on this socket and its events
+ *
+ * @note on synchronization of select_cb_list:
+ * LWIP_TCPIP_CORE_LOCKING: the select_cb_list must only be accessed while holding
+ * the core lock. We do a single pass through the list and signal any waiters.
+ * Core lock should already be held when calling here!!!!
+
+ * !LWIP_TCPIP_CORE_LOCKING: we use SYS_ARCH_PROTECT but unlock on each iteration
+ * of the loop, thus creating a possibility where a thread could modify the
+ * select_cb_list during our UNPROTECT/PROTECT. We use a generational counter to
+ * detect this change and restart the list walk. The list is expected to be small
+ */
+static void select_check_waiters(int s, int has_recvevent, int has_sendevent, int has_errevent)
+{
+  struct lwip_select_cb *scb;
+#if !LWIP_TCPIP_CORE_LOCKING
+  int last_select_cb_ctr;
+  SYS_ARCH_DECL_PROTECT(lev);
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if !LWIP_TCPIP_CORE_LOCKING
+  SYS_ARCH_PROTECT(lev);
+again:
+  /* remember the state of select_cb_list to detect changes */
+  last_select_cb_ctr = select_cb_ctr;
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+  for (scb = select_cb_list; scb != NULL; scb = scb->next) {
+    if (scb->sem_signalled == 0) {
+      /* semaphore not signalled yet */
+      int do_signal = 0;
+#if LWIP_SOCKET_POLL
+      if (scb->poll_fds != NULL) {
+        do_signal = lwip_poll_should_wake(scb, s, has_recvevent, has_sendevent, has_errevent);
+      }
+#endif /* LWIP_SOCKET_POLL */
+#if LWIP_SOCKET_SELECT && LWIP_SOCKET_POLL
+      else
+#endif /* LWIP_SOCKET_SELECT && LWIP_SOCKET_POLL */
+#if LWIP_SOCKET_SELECT
+      {
+        /* Test this select call for our socket */
+        if (has_recvevent) {
+          if (scb->readset && FD_ISSET(s, scb->readset)) {
+            do_signal = 1;
+          }
+        }
+        if (has_sendevent) {
+          if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) {
+            do_signal = 1;
+          }
+        }
+        if (has_errevent) {
+          if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) {
+            do_signal = 1;
+          }
+        }
+      }
+#endif /* LWIP_SOCKET_SELECT */
+      if (do_signal) {
+        scb->sem_signalled = 1;
+        /* For !LWIP_TCPIP_CORE_LOCKING, we don't call SYS_ARCH_UNPROTECT() before signaling
+           the semaphore, as this might lead to the select thread taking itself off the list,
+           invalidating the semaphore. */
+        sys_sem_signal(SELECT_SEM_PTR(scb->sem));
+      }
+    }
+#if LWIP_TCPIP_CORE_LOCKING
+  }
+#else
+    /* unlock interrupts with each step */
+    SYS_ARCH_UNPROTECT(lev);
+    /* this makes sure interrupt protection time is short */
+    SYS_ARCH_PROTECT(lev);
+    if (last_select_cb_ctr != select_cb_ctr) {
+      /* someone has changed select_cb_list, restart at the beginning */
+      goto again;
+    }
+    /* remember the state of select_cb_list to detect changes */
+    last_select_cb_ctr = select_cb_ctr;
+  }
+  SYS_ARCH_UNPROTECT(lev);
+#endif
+}
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+
+/**
+ * Close one end of a full-duplex connection.
+ */
+int
+lwip_shutdown(int s, int how)
+{
+  struct lwip_sock *sock;
+  err_t err;
+  u8_t shut_rx = 0, shut_tx = 0;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  if (sock->conn != NULL) {
+    if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) {
+      sock_set_errno(sock, EOPNOTSUPP);
+      done_socket(sock);
+      return -1;
+    }
+  } else {
+    sock_set_errno(sock, ENOTCONN);
+    done_socket(sock);
+    return -1;
+  }
+
+  if (how == SHUT_RD) {
+    shut_rx = 1;
+  } else if (how == SHUT_WR) {
+    shut_tx = 1;
+  } else if (how == SHUT_RDWR) {
+    shut_rx = 1;
+    shut_tx = 1;
+  } else {
+    sock_set_errno(sock, EINVAL);
+    done_socket(sock);
+    return -1;
+  }
+  err = netconn_shutdown(sock->conn, shut_rx, shut_tx);
+
+  sock_set_errno(sock, err_to_errno(err));
+  done_socket(sock);
+  return (err == ERR_OK ? 0 : -1);
+}
+
+static int
+lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local)
+{
+  struct lwip_sock *sock;
+  union sockaddr_aligned saddr;
+  ip_addr_t naddr;
+  u16_t port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    return -1;
+  }
+
+  /* get the IP address and port */
+  err = netconn_getaddr(sock->conn, &naddr, &port, local);
+  if (err != ERR_OK) {
+    sock_set_errno(sock, err_to_errno(err));
+    done_socket(sock);
+    return -1;
+  }
+
+#if LWIP_IPV4 && LWIP_IPV6
+  /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */
+  if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) &&
+      IP_IS_V4_VAL(naddr)) {
+    ip4_2_ipv4_mapped_ipv6(ip_2_ip6(&naddr), ip_2_ip4(&naddr));
+    IP_SET_TYPE_VAL(naddr, IPADDR_TYPE_V6);
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+  IPADDR_PORT_TO_SOCKADDR(&saddr, &naddr, port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s));
+  ip_addr_debug_print_val(SOCKETS_DEBUG, naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", port));
+
+  if (*namelen > saddr.sa.sa_len) {
+    *namelen = saddr.sa.sa_len;
+  }
+  MEMCPY(name, &saddr, *namelen);
+
+  sock_set_errno(sock, 0);
+  done_socket(sock);
+  return 0;
+}
+
+int
+lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 0);
+}
+
+int
+lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen)
+{
+  return lwip_getaddrname(s, name, namelen, 1);
+}
+
+int
+lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  int err;
+  struct lwip_sock *sock = get_socket(s);
+#if !LWIP_TCPIP_CORE_LOCKING
+  err_t cberr;
+  LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data);
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+  if (!sock) {
+    return -1;
+  }
+
+  if ((NULL == optval) || (NULL == optlen)) {
+    sock_set_errno(sock, EFAULT);
+    done_socket(sock);
+    return -1;
+  }
+
+#if LWIP_TCPIP_CORE_LOCKING
+  /* core-locking can just call the -impl function */
+  LOCK_TCPIP_CORE();
+  err = lwip_getsockopt_impl(s, level, optname, optval, optlen);
+  UNLOCK_TCPIP_CORE();
+
+#else /* LWIP_TCPIP_CORE_LOCKING */
+
+#if LWIP_MPU_COMPATIBLE
+  /* MPU_COMPATIBLE copies the optval data, so check for max size here */
+  if (*optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) {
+    sock_set_errno(sock, ENOBUFS);
+    done_socket(sock);
+    return -1;
+  }
+#endif /* LWIP_MPU_COMPATIBLE */
+
+  LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock);
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s;
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level;
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname;
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = *optlen;
+#if !LWIP_MPU_COMPATIBLE
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.p = optval;
+#endif /* !LWIP_MPU_COMPATIBLE */
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET();
+#else
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed;
+#endif
+  cberr = tcpip_callback(lwip_getsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data));
+  if (cberr != ERR_OK) {
+    LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data);
+    sock_set_errno(sock, err_to_errno(cberr));
+    done_socket(sock);
+    return -1;
+  }
+  sys_arch_sem_wait((sys_sem_t *)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0);
+
+  /* write back optlen and optval */
+  *optlen = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen;
+#if LWIP_MPU_COMPATIBLE
+  MEMCPY(optval, LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval,
+         LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen);
+#endif /* LWIP_MPU_COMPATIBLE */
+
+  /* maybe lwip_getsockopt_internal has changed err */
+  err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err;
+  LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data);
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+  sock_set_errno(sock, err);
+  done_socket(sock);
+  return err ? -1 : 0;
+}
+
+#if !LWIP_TCPIP_CORE_LOCKING
+/** lwip_getsockopt_callback: only used without CORE_LOCKING
+ * to get into the tcpip_thread
+ */
+static void
+lwip_getsockopt_callback(void *arg)
+{
+  struct lwip_setgetsockopt_data *data;
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+  data = (struct lwip_setgetsockopt_data *)arg;
+
+  data->err = lwip_getsockopt_impl(data->s, data->level, data->optname,
+#if LWIP_MPU_COMPATIBLE
+                                   data->optval,
+#else /* LWIP_MPU_COMPATIBLE */
+                                   data->optval.p,
+#endif /* LWIP_MPU_COMPATIBLE */
+                                   &data->optlen);
+
+  sys_sem_signal((sys_sem_t *)(data->completed_sem));
+}
+#endif  /* LWIP_TCPIP_CORE_LOCKING */
+
+static int
+lwip_sockopt_to_ipopt(int optname)
+{
+  /* Map SO_* values to our internal SOF_* values
+   * We should not rely on #defines in socket.h
+   * being in sync with ip.h.
+   */
+  switch (optname) {
+  case SO_BROADCAST:
+    return SOF_BROADCAST;
+  case SO_KEEPALIVE:
+    return SOF_KEEPALIVE;
+  case SO_REUSEADDR:
+    return SOF_REUSEADDR;
+  default:
+    LWIP_ASSERT("Unknown socket option", 0);
+    return 0;
+  }
+}
+
+/** lwip_getsockopt_impl: the actual implementation of getsockopt:
+ * same argument as lwip_getsockopt, either called directly or through callback
+ */
+static int
+lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  int err = 0;
+  struct lwip_sock *sock = tryget_socket(s);
+  if (!sock) {
+    return EBADF;
+  }
+
+#ifdef LWIP_HOOK_SOCKETS_GETSOCKOPT
+  if (LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, &err)) {
+    return err;
+  }
+#endif
+
+  switch (level) {
+
+    /* Level: SOL_SOCKET */
+    case SOL_SOCKET:
+      switch (optname) {
+
+#if LWIP_TCP
+        case SO_ACCEPTCONN:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int);
+          if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_TCP) {
+            done_socket(sock);
+            return ENOPROTOOPT;
+          }
+          if ((sock->conn->pcb.tcp != NULL) && (sock->conn->pcb.tcp->state == LISTEN)) {
+            *(int *)optval = 1;
+          } else {
+            *(int *)optval = 0;
+          }
+          break;
+#endif /* LWIP_TCP */
+
+        /* The option flags */
+        case SO_BROADCAST:
+        case SO_KEEPALIVE:
+#if SO_REUSE
+        case SO_REUSEADDR:
+#endif /* SO_REUSE */
+          if ((optname == SO_BROADCAST) &&
+              (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP)) {
+            done_socket(sock);
+            return ENOPROTOOPT;
+          }
+
+          optname = lwip_sockopt_to_ipopt(optname);
+
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int);
+          *(int *)optval = ip_get_option(sock->conn->pcb.ip, optname);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n",
+                                      s, optname, (*(int *)optval ? "on" : "off")));
+          break;
+
+        case SO_TYPE:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int);
+          switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) {
+            case NETCONN_RAW:
+              *(int *)optval = SOCK_RAW;
+              break;
+            case NETCONN_TCP:
+              *(int *)optval = SOCK_STREAM;
+              break;
+            case NETCONN_UDP:
+              *(int *)optval = SOCK_DGRAM;
+              break;
+            default: /* unrecognized socket type */
+              *(int *)optval = netconn_type(sock->conn);
+              LWIP_DEBUGF(SOCKETS_DEBUG,
+                          ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n",
+                           s, *(int *)optval));
+          }  /* switch (netconn_type(sock->conn)) */
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n",
+                                      s, *(int *)optval));
+          break;
+
+        case SO_ERROR:
+          LWIP_SOCKOPT_CHECK_OPTLEN(sock, *optlen, int);
+          *(int *)optval = err_to_errno(netconn_err(sock->conn));
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n",
+                                      s, *(int *)optval));
+          break;
+
+#if LWIP_SO_SNDTIMEO
+        case SO_SNDTIMEO:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE);
+          LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_sendtimeout(sock->conn));
+          break;
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_RCVTIMEO
+        case SO_RCVTIMEO:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE);
+          LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_recvtimeout(sock->conn));
+          break;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+        case SO_RCVBUF:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int);
+          *(int *)optval = netconn_get_recvbufsize(sock->conn);
+          break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+        case SO_LINGER: {
+          s16_t conn_linger;
+          struct linger *linger = (struct linger *)optval;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, struct linger);
+          conn_linger = sock->conn->linger;
+          if (conn_linger >= 0) {
+            linger->l_onoff = 1;
+            linger->l_linger = (int)conn_linger;
+          } else {
+            linger->l_onoff = 0;
+            linger->l_linger = 0;
+          }
+        }
+        break;
+#endif /* LWIP_SO_LINGER */
+#if LWIP_UDP
+        case SO_NO_CHECK:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_UDP);
+#if LWIP_UDPLITE
+          if (udp_is_flag_set(sock->conn->pcb.udp, UDP_FLAGS_UDPLITE)) {
+            /* this flag is only available for UDP, not for UDP lite */
+            done_socket(sock);
+            return EAFNOSUPPORT;
+          }
+#endif /* LWIP_UDPLITE */
+          *(int *)optval = udp_is_flag_set(sock->conn->pcb.udp, UDP_FLAGS_NOCHKSUM) ? 1 : 0;
+          break;
+#endif /* LWIP_UDP*/
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+
+    /* Level: IPPROTO_IP */
+    case IPPROTO_IP:
+      switch (optname) {
+        case IP_TTL:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int);
+          *(int *)optval = sock->conn->pcb.ip->ttl;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n",
+                                      s, *(int *)optval));
+          break;
+        case IP_TOS:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int);
+          *(int *)optval = sock->conn->pcb.ip->tos;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n",
+                                      s, *(int *)optval));
+          break;
+#if LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP
+        case IP_MULTICAST_TTL:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t);
+          if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) {
+            done_socket(sock);
+            return ENOPROTOOPT;
+          }
+          *(u8_t *)optval = udp_get_multicast_ttl(sock->conn->pcb.udp);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n",
+                                      s, *(int *)optval));
+          break;
+        case IP_MULTICAST_IF:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, struct in_addr);
+          if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) {
+            done_socket(sock);
+            return ENOPROTOOPT;
+          }
+          inet_addr_from_ip4addr((struct in_addr *)optval, udp_get_multicast_netif_addr(sock->conn->pcb.udp));
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n",
+                                      s, *(u32_t *)optval));
+          break;
+        case IP_MULTICAST_LOOP:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t);
+          if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) {
+            *(u8_t *)optval = 1;
+          } else {
+            *(u8_t *)optval = 0;
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n",
+                                      s, *(int *)optval));
+          break;
+#endif /* LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+
+#if LWIP_TCP
+    /* Level: IPPROTO_TCP */
+    case IPPROTO_TCP:
+      /* Special case: all IPPROTO_TCP option take an int */
+      LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_TCP);
+      if (sock->conn->pcb.tcp->state == LISTEN) {
+        done_socket(sock);
+        return EINVAL;
+      }
+      switch (optname) {
+        case TCP_NODELAY:
+          *(int *)optval = tcp_nagle_disabled(sock->conn->pcb.tcp);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n",
+                                      s, (*(int *)optval) ? "on" : "off") );
+          break;
+        case TCP_KEEPALIVE:
+          *(int *)optval = (int)sock->conn->pcb.tcp->keep_idle;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) = %d\n",
+                                      s, *(int *)optval));
+          break;
+
+#if LWIP_TCP_KEEPALIVE
+        case TCP_KEEPIDLE:
+          *(int *)optval = (int)(sock->conn->pcb.tcp->keep_idle / 1000);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) = %d\n",
+                                      s, *(int *)optval));
+          break;
+        case TCP_KEEPINTVL:
+          *(int *)optval = (int)(sock->conn->pcb.tcp->keep_intvl / 1000);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) = %d\n",
+                                      s, *(int *)optval));
+          break;
+        case TCP_KEEPCNT:
+          *(int *)optval = (int)sock->conn->pcb.tcp->keep_cnt;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) = %d\n",
+                                      s, *(int *)optval));
+          break;
+#endif /* LWIP_TCP_KEEPALIVE */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+#endif /* LWIP_TCP */
+
+#if LWIP_IPV6
+    /* Level: IPPROTO_IPV6 */
+    case IPPROTO_IPV6:
+      switch (optname) {
+        case IPV6_V6ONLY:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int);
+          *(int *)optval = (netconn_get_ipv6only(sock->conn) ? 1 : 0);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY) = %d\n",
+                                      s, *(int *)optval));
+          break;
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+#endif /* LWIP_IPV6 */
+
+#if LWIP_UDP && LWIP_UDPLITE
+    /* Level: IPPROTO_UDPLITE */
+    case IPPROTO_UDPLITE:
+      /* Special case: all IPPROTO_UDPLITE option take an int */
+      LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int);
+      /* If this is no UDP lite socket, ignore any options. */
+      if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) {
+        done_socket(sock);
+        return ENOPROTOOPT;
+      }
+      switch (optname) {
+        case UDPLITE_SEND_CSCOV:
+          *(int *)optval = sock->conn->pcb.udp->chksum_len_tx;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n",
+                                      s, (*(int *)optval)) );
+          break;
+        case UDPLITE_RECV_CSCOV:
+          *(int *)optval = sock->conn->pcb.udp->chksum_len_rx;
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n",
+                                      s, (*(int *)optval)) );
+          break;
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+#endif /* LWIP_UDP */
+    /* Level: IPPROTO_RAW */
+    case IPPROTO_RAW:
+      switch (optname) {
+#if LWIP_IPV6 && LWIP_RAW
+        case IPV6_CHECKSUM:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_RAW);
+          if (sock->conn->pcb.raw->chksum_reqd == 0) {
+            *(int *)optval = -1;
+          } else {
+            *(int *)optval = sock->conn->pcb.raw->chksum_offset;
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM) = %d\n",
+                                      s, (*(int *)optval)) );
+          break;
+#endif /* LWIP_IPV6 && LWIP_RAW */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                                  s, level, optname));
+      err = ENOPROTOOPT;
+      break;
+  } /* switch (level) */
+
+  done_socket(sock);
+  return err;
+}
+
+int
+lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  int err = 0;
+  struct lwip_sock *sock = get_socket(s);
+#if !LWIP_TCPIP_CORE_LOCKING
+  err_t cberr;
+  LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data);
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+  if (!sock) {
+    return -1;
+  }
+
+  if (NULL == optval) {
+    sock_set_errno(sock, EFAULT);
+    done_socket(sock);
+    return -1;
+  }
+
+#if LWIP_TCPIP_CORE_LOCKING
+  /* core-locking can just call the -impl function */
+  LOCK_TCPIP_CORE();
+  err = lwip_setsockopt_impl(s, level, optname, optval, optlen);
+  UNLOCK_TCPIP_CORE();
+
+#else /* LWIP_TCPIP_CORE_LOCKING */
+
+#if LWIP_MPU_COMPATIBLE
+  /* MPU_COMPATIBLE copies the optval data, so check for max size here */
+  if (optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) {
+    sock_set_errno(sock, ENOBUFS);
+    done_socket(sock);
+    return -1;
+  }
+#endif /* LWIP_MPU_COMPATIBLE */
+
+  LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock);
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s;
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level;
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname;
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = optlen;
+#if LWIP_MPU_COMPATIBLE
+  MEMCPY(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, optval, optlen);
+#else /* LWIP_MPU_COMPATIBLE */
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.pc = (const void *)optval;
+#endif /* LWIP_MPU_COMPATIBLE */
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET();
+#else
+  LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed;
+#endif
+  cberr = tcpip_callback(lwip_setsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data));
+  if (cberr != ERR_OK) {
+    LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data);
+    sock_set_errno(sock, err_to_errno(cberr));
+    done_socket(sock);
+    return -1;
+  }
+  sys_arch_sem_wait((sys_sem_t *)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0);
+
+  /* maybe lwip_getsockopt_internal has changed err */
+  err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err;
+  LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data);
+#endif  /* LWIP_TCPIP_CORE_LOCKING */
+
+  sock_set_errno(sock, err);
+  done_socket(sock);
+  return err ? -1 : 0;
+}
+
+#if !LWIP_TCPIP_CORE_LOCKING
+/** lwip_setsockopt_callback: only used without CORE_LOCKING
+ * to get into the tcpip_thread
+ */
+static void
+lwip_setsockopt_callback(void *arg)
+{
+  struct lwip_setgetsockopt_data *data;
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+  data = (struct lwip_setgetsockopt_data *)arg;
+
+  data->err = lwip_setsockopt_impl(data->s, data->level, data->optname,
+#if LWIP_MPU_COMPATIBLE
+                                   data->optval,
+#else /* LWIP_MPU_COMPATIBLE */
+                                   data->optval.pc,
+#endif /* LWIP_MPU_COMPATIBLE */
+                                   data->optlen);
+
+  sys_sem_signal((sys_sem_t *)(data->completed_sem));
+}
+#endif  /* LWIP_TCPIP_CORE_LOCKING */
+
+/** lwip_setsockopt_impl: the actual implementation of setsockopt:
+ * same argument as lwip_setsockopt, either called directly or through callback
+ */
+static int
+lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  int err = 0;
+  struct lwip_sock *sock = tryget_socket(s);
+  if (!sock) {
+    return EBADF;
+  }
+
+#ifdef LWIP_HOOK_SOCKETS_SETSOCKOPT
+  if (LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, &err)) {
+    return err;
+  }
+#endif
+
+  switch (level) {
+
+    /* Level: SOL_SOCKET */
+    case SOL_SOCKET:
+      switch (optname) {
+
+        /* SO_ACCEPTCONN is get-only */
+
+        /* The option flags */
+        case SO_BROADCAST:
+        case SO_KEEPALIVE:
+#if SO_REUSE
+        case SO_REUSEADDR:
+#endif /* SO_REUSE */
+          if ((optname == SO_BROADCAST) &&
+              (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP)) {
+            done_socket(sock);
+            return ENOPROTOOPT;
+          }
+
+          optname = lwip_sockopt_to_ipopt(optname);
+
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int);
+          if (*(const int *)optval) {
+            ip_set_option(sock->conn->pcb.ip, optname);
+          } else {
+            ip_reset_option(sock->conn->pcb.ip, optname);
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n",
+                                      s, optname, (*(const int *)optval ? "on" : "off")));
+          break;
+
+          /* SO_TYPE is get-only */
+          /* SO_ERROR is get-only */
+
+#if LWIP_SO_SNDTIMEO
+        case SO_SNDTIMEO: {
+          long ms_long;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE);
+          ms_long = LWIP_SO_SNDRCVTIMEO_GET_MS(optval);
+          if (ms_long < 0) {
+            done_socket(sock);
+            return EINVAL;
+          }
+          netconn_set_sendtimeout(sock->conn, ms_long);
+          break;
+        }
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_RCVTIMEO
+        case SO_RCVTIMEO: {
+          long ms_long;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE);
+          ms_long = LWIP_SO_SNDRCVTIMEO_GET_MS(optval);
+          if (ms_long < 0) {
+            done_socket(sock);
+            return EINVAL;
+          }
+          netconn_set_recvtimeout(sock->conn, (u32_t)ms_long);
+          break;
+        }
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+        case SO_RCVBUF:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, int);
+          netconn_set_recvbufsize(sock->conn, *(const int *)optval);
+          break;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+        case SO_LINGER: {
+          const struct linger *linger = (const struct linger *)optval;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct linger);
+          if (linger->l_onoff) {
+            int lingersec = linger->l_linger;
+            if (lingersec < 0) {
+              done_socket(sock);
+              return EINVAL;
+            }
+            if (lingersec > 0xFFFF) {
+              lingersec = 0xFFFF;
+            }
+            sock->conn->linger = (s16_t)lingersec;
+          } else {
+            sock->conn->linger = -1;
+          }
+        }
+        break;
+#endif /* LWIP_SO_LINGER */
+#if LWIP_UDP
+        case SO_NO_CHECK:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP);
+#if LWIP_UDPLITE
+          if (udp_is_flag_set(sock->conn->pcb.udp, UDP_FLAGS_UDPLITE)) {
+            /* this flag is only available for UDP, not for UDP lite */
+            done_socket(sock);
+            return EAFNOSUPPORT;
+          }
+#endif /* LWIP_UDPLITE */
+          if (*(const int *)optval) {
+            udp_set_flags(sock->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+          } else {
+            udp_clear_flags(sock->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+          }
+          break;
+#endif /* LWIP_UDP */
+        case SO_BINDTODEVICE: {
+          const struct ifreq *iface;
+          struct netif *n = NULL;
+
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct ifreq);
+
+          iface = (const struct ifreq *)optval;
+          if (iface->ifr_name[0] != 0) {
+            n = netif_find(iface->ifr_name);
+            if (n == NULL) {
+              done_socket(sock);
+              return ENODEV;
+            }
+          }
+
+          switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) {
+#if LWIP_TCP
+            case NETCONN_TCP:
+              tcp_bind_netif(sock->conn->pcb.tcp, n);
+              break;
+#endif
+#if LWIP_UDP
+            case NETCONN_UDP:
+              udp_bind_netif(sock->conn->pcb.udp, n);
+              break;
+#endif
+#if LWIP_RAW
+            case NETCONN_RAW:
+              raw_bind_netif(sock->conn->pcb.raw, n);
+              break;
+#endif
+            default:
+              LWIP_ASSERT("Unhandled netconn type in SO_BINDTODEVICE", 0);
+              break;
+          }
+        }
+        break;
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+
+    /* Level: IPPROTO_IP */
+    case IPPROTO_IP:
+      switch (optname) {
+        case IP_TTL:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int);
+          sock->conn->pcb.ip->ttl = (u8_t)(*(const int *)optval);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n",
+                                      s, sock->conn->pcb.ip->ttl));
+          break;
+        case IP_TOS:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int);
+          sock->conn->pcb.ip->tos = (u8_t)(*(const int *)optval);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n",
+                                      s, sock->conn->pcb.ip->tos));
+          break;
+#if LWIP_NETBUF_RECVINFO
+        case IP_PKTINFO:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP);
+          if (*(const int *)optval) {
+            sock->conn->flags |= NETCONN_FLAG_PKTINFO;
+          } else {
+            sock->conn->flags &= ~NETCONN_FLAG_PKTINFO;
+          }
+          break;
+#endif /* LWIP_NETBUF_RECVINFO */
+#if LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP
+        case IP_MULTICAST_TTL:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP);
+          udp_set_multicast_ttl(sock->conn->pcb.udp, (u8_t)(*(const u8_t *)optval));
+          break;
+        case IP_MULTICAST_IF: {
+          ip4_addr_t if_addr;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct in_addr, NETCONN_UDP);
+          inet_addr_to_ip4addr(&if_addr, (const struct in_addr *)optval);
+          udp_set_multicast_netif_addr(sock->conn->pcb.udp, &if_addr);
+        }
+        break;
+        case IP_MULTICAST_LOOP:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP);
+          if (*(const u8_t *)optval) {
+            udp_set_flags(sock->conn->pcb.udp, UDP_FLAGS_MULTICAST_LOOP);
+          } else {
+            udp_clear_flags(sock->conn->pcb.udp, UDP_FLAGS_MULTICAST_LOOP);
+          }
+          break;
+#endif /* LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP */
+#if LWIP_IGMP
+        case IP_ADD_MEMBERSHIP:
+        case IP_DROP_MEMBERSHIP: {
+          /* If this is a TCP or a RAW socket, ignore these options. */
+          err_t igmp_err;
+          const struct ip_mreq *imr = (const struct ip_mreq *)optval;
+          ip4_addr_t if_addr;
+          ip4_addr_t multi_addr;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ip_mreq, NETCONN_UDP);
+          inet_addr_to_ip4addr(&if_addr, &imr->imr_interface);
+          inet_addr_to_ip4addr(&multi_addr, &imr->imr_multiaddr);
+          if (optname == IP_ADD_MEMBERSHIP) {
+            if (!lwip_socket_register_membership(s, &if_addr, &multi_addr)) {
+              /* cannot track membership (out of memory) */
+              err = ENOMEM;
+              igmp_err = ERR_OK;
+            } else {
+              igmp_err = igmp_joingroup(&if_addr, &multi_addr);
+            }
+          } else {
+            igmp_err = igmp_leavegroup(&if_addr, &multi_addr);
+            lwip_socket_unregister_membership(s, &if_addr, &multi_addr);
+          }
+          if (igmp_err != ERR_OK) {
+            err = EADDRNOTAVAIL;
+          }
+        }
+        break;
+#endif /* LWIP_IGMP */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+
+#if LWIP_TCP
+    /* Level: IPPROTO_TCP */
+    case IPPROTO_TCP:
+      /* Special case: all IPPROTO_TCP option take an int */
+      LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP);
+      if (sock->conn->pcb.tcp->state == LISTEN) {
+        done_socket(sock);
+        return EINVAL;
+      }
+      switch (optname) {
+        case TCP_NODELAY:
+          if (*(const int *)optval) {
+            tcp_nagle_disable(sock->conn->pcb.tcp);
+          } else {
+            tcp_nagle_enable(sock->conn->pcb.tcp);
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n",
+                                      s, (*(const int *)optval) ? "on" : "off") );
+          break;
+        case TCP_KEEPALIVE:
+          sock->conn->pcb.tcp->keep_idle = (u32_t)(*(const int *)optval);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n",
+                                      s, sock->conn->pcb.tcp->keep_idle));
+          break;
+
+#if LWIP_TCP_KEEPALIVE
+        case TCP_KEEPIDLE:
+          sock->conn->pcb.tcp->keep_idle = 1000 * (u32_t)(*(const int *)optval);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n",
+                                      s, sock->conn->pcb.tcp->keep_idle));
+          break;
+        case TCP_KEEPINTVL:
+          sock->conn->pcb.tcp->keep_intvl = 1000 * (u32_t)(*(const int *)optval);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n",
+                                      s, sock->conn->pcb.tcp->keep_intvl));
+          break;
+        case TCP_KEEPCNT:
+          sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(const int *)optval);
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n",
+                                      s, sock->conn->pcb.tcp->keep_cnt));
+          break;
+#endif /* LWIP_TCP_KEEPALIVE */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+#endif /* LWIP_TCP*/
+
+#if LWIP_IPV6
+    /* Level: IPPROTO_IPV6 */
+    case IPPROTO_IPV6:
+      switch (optname) {
+        case IPV6_V6ONLY:
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int);
+          if (*(const int *)optval) {
+            netconn_set_ipv6only(sock->conn, 1);
+          } else {
+            netconn_set_ipv6only(sock->conn, 0);
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY, ..) -> %d\n",
+                                      s, (netconn_get_ipv6only(sock->conn) ? 1 : 0)));
+          break;
+#if LWIP_IPV6_MLD
+        case IPV6_JOIN_GROUP:
+        case IPV6_LEAVE_GROUP: {
+          /* If this is a TCP or a RAW socket, ignore these options. */
+          err_t mld6_err;
+          struct netif *netif;
+          ip6_addr_t multi_addr;
+          const struct ipv6_mreq *imr = (const struct ipv6_mreq *)optval;
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ipv6_mreq, NETCONN_UDP);
+          inet6_addr_to_ip6addr(&multi_addr, &imr->ipv6mr_multiaddr);
+          LWIP_ASSERT("Invalid netif index", imr->ipv6mr_interface <= 0xFFu);
+          netif = netif_get_by_index((u8_t)imr->ipv6mr_interface);
+          if (netif == NULL) {
+            err = EADDRNOTAVAIL;
+            break;
+          }
+
+          if (optname == IPV6_JOIN_GROUP) {
+            if (!lwip_socket_register_mld6_membership(s, imr->ipv6mr_interface, &multi_addr)) {
+              /* cannot track membership (out of memory) */
+              err = ENOMEM;
+              mld6_err = ERR_OK;
+            } else {
+              mld6_err = mld6_joingroup_netif(netif, &multi_addr);
+            }
+          } else {
+            mld6_err = mld6_leavegroup_netif(netif, &multi_addr);
+            lwip_socket_unregister_mld6_membership(s, imr->ipv6mr_interface, &multi_addr);
+          }
+          if (mld6_err != ERR_OK) {
+            err = EADDRNOTAVAIL;
+          }
+        }
+        break;
+#endif /* LWIP_IPV6_MLD */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+#endif /* LWIP_IPV6 */
+
+#if LWIP_UDP && LWIP_UDPLITE
+    /* Level: IPPROTO_UDPLITE */
+    case IPPROTO_UDPLITE:
+      /* Special case: all IPPROTO_UDPLITE option take an int */
+      LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int);
+      /* If this is no UDP lite socket, ignore any options. */
+      if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) {
+        done_socket(sock);
+        return ENOPROTOOPT;
+      }
+      switch (optname) {
+        case UDPLITE_SEND_CSCOV:
+          if ((*(const int *)optval != 0) && ((*(const int *)optval < 8) || (*(const int *)optval > 0xffff))) {
+            /* don't allow illegal values! */
+            sock->conn->pcb.udp->chksum_len_tx = 8;
+          } else {
+            sock->conn->pcb.udp->chksum_len_tx = (u16_t) * (const int *)optval;
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n",
+                                      s, (*(const int *)optval)) );
+          break;
+        case UDPLITE_RECV_CSCOV:
+          if ((*(const int *)optval != 0) && ((*(const int *)optval < 8) || (*(const int *)optval > 0xffff))) {
+            /* don't allow illegal values! */
+            sock->conn->pcb.udp->chksum_len_rx = 8;
+          } else {
+            sock->conn->pcb.udp->chksum_len_rx = (u16_t) * (const int *)optval;
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n",
+                                      s, (*(const int *)optval)) );
+          break;
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+#endif /* LWIP_UDP */
+    /* Level: IPPROTO_RAW */
+    case IPPROTO_RAW:
+      switch (optname) {
+#if LWIP_IPV6 && LWIP_RAW
+        case IPV6_CHECKSUM:
+          /* It should not be possible to disable the checksum generation with ICMPv6
+           * as per RFC 3542 chapter 3.1 */
+          if (sock->conn->pcb.raw->protocol == IPPROTO_ICMPV6) {
+            done_socket(sock);
+            return EINVAL;
+          }
+
+          LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_RAW);
+          if (*(const int *)optval < 0) {
+            sock->conn->pcb.raw->chksum_reqd = 0;
+          } else if (*(const int *)optval & 1) {
+            /* Per RFC3542, odd offsets are not allowed */
+            done_socket(sock);
+            return EINVAL;
+          } else {
+            sock->conn->pcb.raw->chksum_reqd = 1;
+            sock->conn->pcb.raw->chksum_offset = (u16_t) * (const int *)optval;
+          }
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM, ..) -> %d\n",
+                                      s, sock->conn->pcb.raw->chksum_reqd));
+          break;
+#endif /* LWIP_IPV6 && LWIP_RAW */
+        default:
+          LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n",
+                                      s, optname));
+          err = ENOPROTOOPT;
+          break;
+      }  /* switch (optname) */
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n",
+                                  s, level, optname));
+      err = ENOPROTOOPT;
+      break;
+  }  /* switch (level) */
+
+  done_socket(sock);
+  return err;
+}
+
+int
+lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_sock *sock = get_socket(s);
+  u8_t val;
+#if LWIP_SO_RCVBUF
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+
+  if (!sock) {
+    return -1;
+  }
+
+  switch (cmd) {
+#if LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE
+    case FIONREAD:
+      if (!argp) {
+        sock_set_errno(sock, EINVAL);
+        done_socket(sock);
+        return -1;
+      }
+#if LWIP_FIONREAD_LINUXMODE
+      if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) {
+        struct netbuf *nb;
+        if (sock->lastdata.netbuf) {
+          nb = sock->lastdata.netbuf;
+          *((int *)argp) = nb->p->tot_len;
+        } else {
+          struct netbuf *rxbuf;
+          err_t err = netconn_recv_udp_raw_netbuf_flags(sock->conn, &rxbuf, NETCONN_DONTBLOCK);
+          if (err != ERR_OK) {
+            *((int *)argp) = 0;
+          } else {
+            sock->lastdata.netbuf = rxbuf;
+            *((int *)argp) = rxbuf->p->tot_len;
+          }
+        }
+        done_socket(sock);
+        return 0;
+      }
+#endif /* LWIP_FIONREAD_LINUXMODE */
+
+#if LWIP_SO_RCVBUF
+      /* we come here if either LWIP_FIONREAD_LINUXMODE==0 or this is a TCP socket */
+      SYS_ARCH_GET(sock->conn->recv_avail, recv_avail);
+      if (recv_avail < 0) {
+        recv_avail = 0;
+      }
+
+      /* Check if there is data left from the last recv operation. /maq 041215 */
+      if (sock->lastdata.netbuf) {
+        if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) {
+          recv_avail += sock->lastdata.pbuf->tot_len;
+        } else {
+          recv_avail += sock->lastdata.netbuf->p->tot_len;
+        }
+      }
+      *((int *)argp) = recv_avail;
+
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t *)argp)));
+      sock_set_errno(sock, 0);
+      done_socket(sock);
+      return 0;
+#else /* LWIP_SO_RCVBUF */
+      break;
+#endif /* LWIP_SO_RCVBUF */
+#endif /* LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE */
+
+    case (long)FIONBIO:
+      val = 0;
+      if (argp && *(int *)argp) {
+        val = 1;
+      }
+      netconn_set_nonblocking(sock->conn, val);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val));
+      sock_set_errno(sock, 0);
+      done_socket(sock);
+      return 0;
+
+    default:
+      break;
+  } /* switch (cmd) */
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+  sock_set_errno(sock, ENOSYS); /* not yet implemented */
+  done_socket(sock);
+  return -1;
+}
+
+/** A minimal implementation of fcntl.
+ * Currently only the commands F_GETFL and F_SETFL are implemented.
+ * The flag O_NONBLOCK and access modes are supported for F_GETFL, only
+ * the flag O_NONBLOCK is implemented for F_SETFL.
+ */
+int
+lwip_fcntl(int s, int cmd, int val)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int ret = -1;
+  int op_mode = 0;
+
+  if (!sock) {
+    return -1;
+  }
+
+  switch (cmd) {
+    case F_GETFL:
+      ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0;
+      sock_set_errno(sock, 0);
+
+      if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) {
+#if LWIP_TCPIP_CORE_LOCKING
+        LOCK_TCPIP_CORE();
+#else
+        SYS_ARCH_DECL_PROTECT(lev);
+        /* the proper thing to do here would be to get into the tcpip_thread,
+           but locking should be OK as well since we only *read* some flags */
+        SYS_ARCH_PROTECT(lev);
+#endif
+#if LWIP_TCP
+        if (sock->conn->pcb.tcp) {
+          if (!(sock->conn->pcb.tcp->flags & TF_RXCLOSED)) {
+            op_mode |= O_RDONLY;
+          }
+          if (!(sock->conn->pcb.tcp->flags & TF_FIN)) {
+            op_mode |= O_WRONLY;
+          }
+        }
+#endif
+#if LWIP_TCPIP_CORE_LOCKING
+        UNLOCK_TCPIP_CORE();
+#else
+        SYS_ARCH_UNPROTECT(lev);
+#endif
+      } else {
+        op_mode |= O_RDWR;
+      }
+
+      /* ensure O_RDWR for (O_RDONLY|O_WRONLY) != O_RDWR cases */
+      ret |= (op_mode == (O_RDONLY | O_WRONLY)) ? O_RDWR : op_mode;
+
+      break;
+    case F_SETFL:
+      /* Bits corresponding to the file access mode and the file creation flags [..] that are set in arg shall be ignored */
+      val &= ~(O_RDONLY | O_WRONLY | O_RDWR);
+      if ((val & ~O_NONBLOCK) == 0) {
+        /* only O_NONBLOCK, all other bits are zero */
+        netconn_set_nonblocking(sock->conn, val & O_NONBLOCK);
+        ret = 0;
+        sock_set_errno(sock, 0);
+      } else {
+        sock_set_errno(sock, ENOSYS); /* not yet implemented */
+      }
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val));
+      sock_set_errno(sock, ENOSYS); /* not yet implemented */
+      break;
+  }
+  done_socket(sock);
+  return ret;
+}
+
+#if LWIP_COMPAT_SOCKETS == 2 && LWIP_POSIX_SOCKETS_IO_NAMES
+int
+fcntl(int s, int cmd, ...)
+{
+  va_list ap;
+  int val;
+
+  va_start(ap, cmd);
+  val = va_arg(ap, int);
+  va_end(ap);
+  return lwip_fcntl(s, cmd, val);
+}
+#endif
+
+const char *
+lwip_inet_ntop(int af, const void *src, char *dst, socklen_t size)
+{
+  const char *ret = NULL;
+  int size_int = (int)size;
+  if (size_int < 0) {
+    set_errno(ENOSPC);
+    return NULL;
+  }
+  switch (af) {
+#if LWIP_IPV4
+    case AF_INET:
+      ret = ip4addr_ntoa_r((const ip4_addr_t *)src, dst, size_int);
+      if (ret == NULL) {
+        set_errno(ENOSPC);
+      }
+      break;
+#endif
+#if LWIP_IPV6
+    case AF_INET6:
+      ret = ip6addr_ntoa_r((const ip6_addr_t *)src, dst, size_int);
+      if (ret == NULL) {
+        set_errno(ENOSPC);
+      }
+      break;
+#endif
+    default:
+      set_errno(EAFNOSUPPORT);
+      break;
+  }
+  return ret;
+}
+
+int
+lwip_inet_pton(int af, const char *src, void *dst)
+{
+  int err;
+  switch (af) {
+#if LWIP_IPV4
+    case AF_INET:
+      err = ip4addr_aton(src, (ip4_addr_t *)dst);
+      break;
+#endif
+#if LWIP_IPV6
+    case AF_INET6: {
+      /* convert into temporary variable since ip6_addr_t might be larger
+         than in6_addr when scopes are enabled */
+      ip6_addr_t addr;
+      err = ip6addr_aton(src, &addr);
+      if (err) {
+        memcpy(dst, &addr.addr, sizeof(addr.addr));
+      }
+      break;
+    }
+#endif
+    default:
+      err = -1;
+      set_errno(EAFNOSUPPORT);
+      break;
+  }
+  return err;
+}
+
+#if LWIP_IGMP
+/** Register a new IGMP membership. On socket close, the membership is dropped automatically.
+ *
+ * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK).
+ *
+ * @return 1 on success, 0 on failure
+ */
+static int
+lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int i;
+
+  if (!sock) {
+    return 0;
+  }
+
+  for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) {
+    if (socket_ipv4_multicast_memberships[i].sock == NULL) {
+      socket_ipv4_multicast_memberships[i].sock = sock;
+      ip4_addr_copy(socket_ipv4_multicast_memberships[i].if_addr, *if_addr);
+      ip4_addr_copy(socket_ipv4_multicast_memberships[i].multi_addr, *multi_addr);
+      done_socket(sock);
+      return 1;
+    }
+  }
+  done_socket(sock);
+  return 0;
+}
+
+/** Unregister a previously registered membership. This prevents dropping the membership
+ * on socket close.
+ *
+ * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK).
+ */
+static void
+lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int i;
+
+  if (!sock) {
+    return;
+  }
+
+  for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) {
+    if ((socket_ipv4_multicast_memberships[i].sock == sock) &&
+        ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].if_addr, if_addr) &&
+        ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].multi_addr, multi_addr)) {
+      socket_ipv4_multicast_memberships[i].sock = NULL;
+      ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr);
+      ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr);
+      break;
+    }
+  }
+  done_socket(sock);
+}
+
+/** Drop all memberships of a socket that were not dropped explicitly via setsockopt.
+ *
+ * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK).
+ */
+static void
+lwip_socket_drop_registered_memberships(int s)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int i;
+
+  if (!sock) {
+    return;
+  }
+
+  for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) {
+    if (socket_ipv4_multicast_memberships[i].sock == sock) {
+      ip_addr_t multi_addr, if_addr;
+      ip_addr_copy_from_ip4(multi_addr, socket_ipv4_multicast_memberships[i].multi_addr);
+      ip_addr_copy_from_ip4(if_addr, socket_ipv4_multicast_memberships[i].if_addr);
+      socket_ipv4_multicast_memberships[i].sock = NULL;
+      ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr);
+      ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr);
+
+      netconn_join_leave_group(sock->conn, &multi_addr, &if_addr, NETCONN_LEAVE);
+    }
+  }
+  done_socket(sock);
+}
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV6_MLD
+/** Register a new MLD6 membership. On socket close, the membership is dropped automatically.
+ *
+ * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK).
+ *
+ * @return 1 on success, 0 on failure
+ */
+static int
+lwip_socket_register_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int i;
+
+  if (!sock) {
+    return 0;
+  }
+
+  for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) {
+    if (socket_ipv6_multicast_memberships[i].sock == NULL) {
+      socket_ipv6_multicast_memberships[i].sock   = sock;
+      socket_ipv6_multicast_memberships[i].if_idx = (u8_t)if_idx;
+      ip6_addr_copy(socket_ipv6_multicast_memberships[i].multi_addr, *multi_addr);
+      done_socket(sock);
+      return 1;
+    }
+  }
+  done_socket(sock);
+  return 0;
+}
+
+/** Unregister a previously registered MLD6 membership. This prevents dropping the membership
+ * on socket close.
+ *
+ * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK).
+ */
+static void
+lwip_socket_unregister_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int i;
+
+  if (!sock) {
+    return;
+  }
+
+  for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) {
+    if ((socket_ipv6_multicast_memberships[i].sock   == sock) &&
+        (socket_ipv6_multicast_memberships[i].if_idx == if_idx) &&
+        ip6_addr_cmp(&socket_ipv6_multicast_memberships[i].multi_addr, multi_addr)) {
+      socket_ipv6_multicast_memberships[i].sock   = NULL;
+      socket_ipv6_multicast_memberships[i].if_idx = NETIF_NO_INDEX;
+      ip6_addr_set_zero(&socket_ipv6_multicast_memberships[i].multi_addr);
+      break;
+    }
+  }
+  done_socket(sock);
+}
+
+/** Drop all MLD6 memberships of a socket that were not dropped explicitly via setsockopt.
+ *
+ * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK).
+ */
+static void
+lwip_socket_drop_registered_mld6_memberships(int s)
+{
+  struct lwip_sock *sock = get_socket(s);
+  int i;
+
+  if (!sock) {
+    return;
+  }
+
+  for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) {
+    if (socket_ipv6_multicast_memberships[i].sock == sock) {
+      ip_addr_t multi_addr;
+      u8_t if_idx;
+
+      ip_addr_copy_from_ip6(multi_addr, socket_ipv6_multicast_memberships[i].multi_addr);
+      if_idx = socket_ipv6_multicast_memberships[i].if_idx;
+
+      socket_ipv6_multicast_memberships[i].sock   = NULL;
+      socket_ipv6_multicast_memberships[i].if_idx = NETIF_NO_INDEX;
+      ip6_addr_set_zero(&socket_ipv6_multicast_memberships[i].multi_addr);
+
+      netconn_join_leave_group_netif(sock->conn, &multi_addr, if_idx, NETCONN_LEAVE);
+    }
+  }
+  done_socket(sock);
+}
+#endif /* LWIP_IPV6_MLD */
+
+#endif /* LWIP_SOCKET */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/tcpip.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/tcpip.c
new file mode 100644
index 000000000..743553a58
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/api/tcpip.c
@@ -0,0 +1,658 @@
+/**
+ * @file
+ * Sequential API Main thread module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/priv/tcpip_priv.h"
+#include "lwip/sys.h"
+#include "lwip/memp.h"
+#include "lwip/mem.h"
+#include "lwip/init.h"
+#include "lwip/ip.h"
+#include "lwip/pbuf.h"
+#include "lwip/etharp.h"
+#include "netif/ethernet.h"
+
+#define TCPIP_MSG_VAR_REF(name)     API_VAR_REF(name)
+#define TCPIP_MSG_VAR_DECLARE(name) API_VAR_DECLARE(struct tcpip_msg, name)
+#define TCPIP_MSG_VAR_ALLOC(name)   API_VAR_ALLOC(struct tcpip_msg, MEMP_TCPIP_MSG_API, name, ERR_MEM)
+#define TCPIP_MSG_VAR_FREE(name)    API_VAR_FREE(MEMP_TCPIP_MSG_API, name)
+
+/* global variables */
+static tcpip_init_done_fn tcpip_init_done;
+static void *tcpip_init_done_arg;
+static sys_mbox_t tcpip_mbox;
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+sys_mutex_t lock_tcpip_core;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+static void tcpip_thread_handle_msg(struct tcpip_msg *msg);
+
+#if !LWIP_TIMERS
+/* wait for a message with timers disabled (e.g. pass a timer-check trigger into tcpip_thread) */
+#define TCPIP_MBOX_FETCH(mbox, msg) sys_mbox_fetch(mbox, msg)
+#else /* !LWIP_TIMERS */
+/* wait for a message, timeouts are processed while waiting */
+#define TCPIP_MBOX_FETCH(mbox, msg) tcpip_timeouts_mbox_fetch(mbox, msg)
+/**
+ * Wait (forever) for a message to arrive in an mbox.
+ * While waiting, timeouts are processed.
+ *
+ * @param mbox the mbox to fetch the message from
+ * @param msg the place to store the message
+ */
+static void
+tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
+{
+  u32_t sleeptime, res;
+
+again:
+  LWIP_ASSERT_CORE_LOCKED();
+
+  sleeptime = sys_timeouts_sleeptime();
+  if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) {
+    UNLOCK_TCPIP_CORE();
+    sys_arch_mbox_fetch(mbox, msg, 0);
+    LOCK_TCPIP_CORE();
+    return;
+  } else if (sleeptime == 0) {
+    sys_check_timeouts();
+    /* We try again to fetch a message from the mbox. */
+    goto again;
+  }
+
+  UNLOCK_TCPIP_CORE();
+  res = sys_arch_mbox_fetch(mbox, msg, sleeptime);
+  LOCK_TCPIP_CORE();
+  if (res == SYS_ARCH_TIMEOUT) {
+    /* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred
+       before a message could be fetched. */
+    sys_check_timeouts();
+    /* We try again to fetch a message from the mbox. */
+    goto again;
+  }
+}
+#endif /* !LWIP_TIMERS */
+
+/**
+ * The main lwIP thread. This thread has exclusive access to lwIP core functions
+ * (unless access to them is not locked). Other threads communicate with this
+ * thread using message boxes.
+ *
+ * It also starts all the timers to make sure they are running in the right
+ * thread context.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+  LWIP_UNUSED_ARG(arg);
+
+  LWIP_MARK_TCPIP_THREAD();
+
+  LOCK_TCPIP_CORE();
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  while (1) {                          /* MAIN Loop */
+    LWIP_TCPIP_THREAD_ALIVE();
+    /* wait for a message, timeouts are processed while waiting */
+    TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
+    if (msg == NULL) {
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n"));
+      LWIP_ASSERT("tcpip_thread: invalid message", 0);
+      continue;
+    }
+    tcpip_thread_handle_msg(msg);
+  }
+}
+
+/* Handle a single tcpip_msg
+ * This is in its own function for access by tests only.
+ */
+static void
+tcpip_thread_handle_msg(struct tcpip_msg *msg)
+{
+  switch (msg->type) {
+#if !LWIP_TCPIP_CORE_LOCKING
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      msg->msg.api_msg.function(msg->msg.api_msg.msg);
+      break;
+    case TCPIP_MSG_API_CALL:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API CALL message %p\n", (void *)msg));
+      msg->msg.api_call.arg->err = msg->msg.api_call.function(msg->msg.api_call.arg);
+      sys_sem_signal(msg->msg.api_call.sem);
+      break;
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    case TCPIP_MSG_INPKT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
+      if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) {
+        pbuf_free(msg->msg.inp.p);
+      }
+      memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+      break;
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+    case TCPIP_MSG_TIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg));
+      sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+    case TCPIP_MSG_UNTIMEOUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg));
+      sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.function(msg->msg.cb.ctx);
+      memp_free(MEMP_TCPIP_MSG_API, msg);
+      break;
+
+    case TCPIP_MSG_CALLBACK_STATIC:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg));
+      msg->msg.cb.function(msg->msg.cb.ctx);
+      break;
+
+    default:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
+      LWIP_ASSERT("tcpip_thread: invalid message", 0);
+      break;
+  }
+}
+
+#ifdef TCPIP_THREAD_TEST
+/** Work on queued items in single-threaded test mode */
+int
+tcpip_thread_poll_one(void)
+{
+  int ret = 0;
+  struct tcpip_msg *msg;
+
+  if (sys_arch_mbox_tryfetch(&tcpip_mbox, (void **)&msg) != SYS_ARCH_TIMEOUT) {
+    LOCK_TCPIP_CORE();
+    if (msg != NULL) {
+      tcpip_thread_handle_msg(msg);
+      ret = 1;
+    }
+    UNLOCK_TCPIP_CORE();
+  }
+  return ret;
+}
+#endif
+
+/**
+ * Pass a received packet to tcpip_thread for input processing
+ *
+ * @param p the received packet
+ * @param inp the network interface on which the packet was received
+ * @param input_fn input function to call
+ */
+err_t
+tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn)
+{
+#if LWIP_TCPIP_CORE_LOCKING_INPUT
+  err_t ret;
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_inpkt: PACKET %p/%p\n", (void *)p, (void *)inp));
+  LOCK_TCPIP_CORE();
+  ret = input_fn(p, inp);
+  UNLOCK_TCPIP_CORE();
+  return ret;
+#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
+  if (msg == NULL) {
+    return ERR_MEM;
+  }
+
+  msg->type = TCPIP_MSG_INPKT;
+  msg->msg.inp.p = p;
+  msg->msg.inp.netif = inp;
+  msg->msg.inp.input_fn = input_fn;
+  if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
+    memp_free(MEMP_TCPIP_MSG_INPKT, msg);
+    return ERR_MEM;
+  }
+  return ERR_OK;
+#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
+}
+
+/**
+ * @ingroup lwip_os
+ * Pass a received packet to tcpip_thread for input processing with
+ * ethernet_input or ip_input. Don't call directly, pass to netif_add()
+ * and call netif->input().
+ *
+ * @param p the received packet, p->payload pointing to the Ethernet header or
+ *          to an IP header (if inp doesn't have NETIF_FLAG_ETHARP or
+ *          NETIF_FLAG_ETHERNET flags)
+ * @param inp the network interface on which the packet was received
+ */
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+#if LWIP_ETHERNET
+  if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
+    return tcpip_inpkt(p, inp, ethernet_input);
+  } else
+#endif /* LWIP_ETHERNET */
+    return tcpip_inpkt(p, inp, ip_input);
+}
+
+/**
+ * @ingroup lwip_os
+ * Call a specific function in the thread context of
+ * tcpip_thread for easy access synchronization.
+ * A function called in that way may access lwIP core code
+ * without fearing concurrent access.
+ * Blocks until the request is posted.
+ * Must not be called from interrupt context!
+ *
+ * @param function the function to call
+ * @param ctx parameter passed to f
+ * @return ERR_OK if the function was called, another err_t if not
+ *
+ * @see tcpip_try_callback
+ */
+err_t
+tcpip_callback(tcpip_callback_fn function, void *ctx)
+{
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+  if (msg == NULL) {
+    return ERR_MEM;
+  }
+
+  msg->type = TCPIP_MSG_CALLBACK;
+  msg->msg.cb.function = function;
+  msg->msg.cb.ctx = ctx;
+
+  sys_mbox_post(&tcpip_mbox, msg);
+  return ERR_OK;
+}
+
+/**
+ * @ingroup lwip_os
+ * Call a specific function in the thread context of
+ * tcpip_thread for easy access synchronization.
+ * A function called in that way may access lwIP core code
+ * without fearing concurrent access.
+ * Does NOT block when the request cannot be posted because the
+ * tcpip_mbox is full, but returns ERR_MEM instead.
+ * Can be called from interrupt context.
+ *
+ * @param function the function to call
+ * @param ctx parameter passed to f
+ * @return ERR_OK if the function was called, another err_t if not
+ *
+ * @see tcpip_callback
+ */
+err_t
+tcpip_try_callback(tcpip_callback_fn function, void *ctx)
+{
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+  if (msg == NULL) {
+    return ERR_MEM;
+  }
+
+  msg->type = TCPIP_MSG_CALLBACK;
+  msg->msg.cb.function = function;
+  msg->msg.cb.ctx = ctx;
+
+  if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
+    memp_free(MEMP_TCPIP_MSG_API, msg);
+    return ERR_MEM;
+  }
+  return ERR_OK;
+}
+
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+/**
+ * call sys_timeout in tcpip_thread
+ *
+ * @param msecs time in milliseconds for timeout
+ * @param h function to be called on timeout
+ * @param arg argument to pass to timeout function h
+ * @return ERR_MEM on memory error, ERR_OK otherwise
+ */
+err_t
+tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+  if (msg == NULL) {
+    return ERR_MEM;
+  }
+
+  msg->type = TCPIP_MSG_TIMEOUT;
+  msg->msg.tmo.msecs = msecs;
+  msg->msg.tmo.h = h;
+  msg->msg.tmo.arg = arg;
+  sys_mbox_post(&tcpip_mbox, msg);
+  return ERR_OK;
+}
+
+/**
+ * call sys_untimeout in tcpip_thread
+ *
+ * @param h function to be called on timeout
+ * @param arg argument to pass to timeout function h
+ * @return ERR_MEM on memory error, ERR_OK otherwise
+ */
+err_t
+tcpip_untimeout(sys_timeout_handler h, void *arg)
+{
+  struct tcpip_msg *msg;
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+  if (msg == NULL) {
+    return ERR_MEM;
+  }
+
+  msg->type = TCPIP_MSG_UNTIMEOUT;
+  msg->msg.tmo.h = h;
+  msg->msg.tmo.arg = arg;
+  sys_mbox_post(&tcpip_mbox, msg);
+  return ERR_OK;
+}
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+
+
+/**
+ * Sends a message to TCPIP thread to call a function. Caller thread blocks on
+ * on a provided semaphore, which ist NOT automatically signalled by TCPIP thread,
+ * this has to be done by the user.
+ * It is recommended to use LWIP_TCPIP_CORE_LOCKING since this is the way
+ * with least runtime overhead.
+ *
+ * @param fn function to be called from TCPIP thread
+ * @param apimsg argument to API function
+ * @param sem semaphore to wait on
+ * @return ERR_OK if the function was called, another err_t if not
+ */
+err_t
+tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t *sem)
+{
+#if LWIP_TCPIP_CORE_LOCKING
+  LWIP_UNUSED_ARG(sem);
+  LOCK_TCPIP_CORE();
+  fn(apimsg);
+  UNLOCK_TCPIP_CORE();
+  return ERR_OK;
+#else /* LWIP_TCPIP_CORE_LOCKING */
+  TCPIP_MSG_VAR_DECLARE(msg);
+
+  LWIP_ASSERT("semaphore not initialized", sys_sem_valid(sem));
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  TCPIP_MSG_VAR_ALLOC(msg);
+  TCPIP_MSG_VAR_REF(msg).type = TCPIP_MSG_API;
+  TCPIP_MSG_VAR_REF(msg).msg.api_msg.function = fn;
+  TCPIP_MSG_VAR_REF(msg).msg.api_msg.msg = apimsg;
+  sys_mbox_post(&tcpip_mbox, &TCPIP_MSG_VAR_REF(msg));
+  sys_arch_sem_wait(sem, 0);
+  TCPIP_MSG_VAR_FREE(msg);
+  return ERR_OK;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+}
+
+/**
+ * Synchronously calls function in TCPIP thread and waits for its completion.
+ * It is recommended to use LWIP_TCPIP_CORE_LOCKING (preferred) or
+ * LWIP_NETCONN_SEM_PER_THREAD.
+ * If not, a semaphore is created and destroyed on every call which is usually
+ * an expensive/slow operation.
+ * @param fn Function to call
+ * @param call Call parameters
+ * @return Return value from tcpip_api_call_fn
+ */
+err_t
+tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call)
+{
+#if LWIP_TCPIP_CORE_LOCKING
+  err_t err;
+  LOCK_TCPIP_CORE();
+  err = fn(call);
+  UNLOCK_TCPIP_CORE();
+  return err;
+#else /* LWIP_TCPIP_CORE_LOCKING */
+  TCPIP_MSG_VAR_DECLARE(msg);
+
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  err_t err = sys_sem_new(&call->sem, 0);
+  if (err != ERR_OK) {
+    return err;
+  }
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+
+  TCPIP_MSG_VAR_ALLOC(msg);
+  TCPIP_MSG_VAR_REF(msg).type = TCPIP_MSG_API_CALL;
+  TCPIP_MSG_VAR_REF(msg).msg.api_call.arg = call;
+  TCPIP_MSG_VAR_REF(msg).msg.api_call.function = fn;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  TCPIP_MSG_VAR_REF(msg).msg.api_call.sem = LWIP_NETCONN_THREAD_SEM_GET();
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+  TCPIP_MSG_VAR_REF(msg).msg.api_call.sem = &call->sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+  sys_mbox_post(&tcpip_mbox, &TCPIP_MSG_VAR_REF(msg));
+  sys_arch_sem_wait(TCPIP_MSG_VAR_REF(msg).msg.api_call.sem, 0);
+  TCPIP_MSG_VAR_FREE(msg);
+
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_free(&call->sem);
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+  return call->err;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+}
+
+/**
+ * @ingroup lwip_os
+ * Allocate a structure for a static callback message and initialize it.
+ * The message has a special type such that lwIP never frees it.
+ * This is intended to be used to send "static" messages from interrupt context,
+ * e.g. the message is allocated once and posted several times from an IRQ
+ * using tcpip_callbackmsg_trycallback().
+ * Example usage: Trigger execution of an ethernet IRQ DPC routine in lwIP thread context.
+ * 
+ * @param function the function to call
+ * @param ctx parameter passed to function
+ * @return a struct pointer to pass to tcpip_callbackmsg_trycallback().
+ *
+ * @see tcpip_callbackmsg_trycallback()
+ * @see tcpip_callbackmsg_delete()
+ */
+struct tcpip_callback_msg *
+tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx)
+{
+  struct tcpip_msg *msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
+  if (msg == NULL) {
+    return NULL;
+  }
+  msg->type = TCPIP_MSG_CALLBACK_STATIC;
+  msg->msg.cb.function = function;
+  msg->msg.cb.ctx = ctx;
+  return (struct tcpip_callback_msg *)msg;
+}
+
+/**
+ * @ingroup lwip_os
+ * Free a callback message allocated by tcpip_callbackmsg_new().
+ *
+ * @param msg the message to free
+ *
+ * @see tcpip_callbackmsg_new()
+ */
+void
+tcpip_callbackmsg_delete(struct tcpip_callback_msg *msg)
+{
+  memp_free(MEMP_TCPIP_MSG_API, msg);
+}
+
+/**
+ * @ingroup lwip_os
+ * Try to post a callback-message to the tcpip_thread tcpip_mbox.
+ *
+ * @param msg pointer to the message to post
+ * @return sys_mbox_trypost() return code
+ *
+ * @see tcpip_callbackmsg_new()
+ */
+err_t
+tcpip_callbackmsg_trycallback(struct tcpip_callback_msg *msg)
+{
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+  return sys_mbox_trypost(&tcpip_mbox, msg);
+}
+
+/**
+ * @ingroup lwip_os
+ * Try to post a callback-message to the tcpip_thread mbox.
+ * Same as @ref tcpip_callbackmsg_trycallback but calls sys_mbox_trypost_fromisr(),
+ * mainly to help FreeRTOS, where calls differ between task level and ISR level.
+ *
+ * @param msg pointer to the message to post
+ * @return sys_mbox_trypost_fromisr() return code (without change, so this
+ *         knowledge can be used to e.g. propagate "bool needs_scheduling")
+ *
+ * @see tcpip_callbackmsg_new()
+ */
+err_t
+tcpip_callbackmsg_trycallback_fromisr(struct tcpip_callback_msg *msg)
+{
+  LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
+  return sys_mbox_trypost_fromisr(&tcpip_mbox, msg);
+}
+
+/**
+ * @ingroup lwip_os
+ * Initialize this module:
+ * - initialize all sub modules
+ * - start the tcpip_thread
+ *
+ * @param initfunc a function to call when tcpip_thread is running and finished initializing
+ * @param arg argument to pass to initfunc
+ */
+void
+tcpip_init(tcpip_init_done_fn initfunc, void *arg)
+{
+  lwip_init();
+
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
+    LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
+  }
+#if LWIP_TCPIP_CORE_LOCKING
+  if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
+    LWIP_ASSERT("failed to create lock_tcpip_core", 0);
+  }
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+  sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
+}
+
+/**
+ * Simple callback function used with tcpip_callback to free a pbuf
+ * (pbuf_free has a wrong signature for tcpip_callback)
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ */
+static void
+pbuf_free_int(void *p)
+{
+  struct pbuf *q = (struct pbuf *)p;
+  pbuf_free(q);
+}
+
+/**
+ * A simple wrapper function that allows you to free a pbuf from interrupt context.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ * @return ERR_OK if callback could be enqueued, an err_t if not
+ */
+err_t
+pbuf_free_callback(struct pbuf *p)
+{
+  return tcpip_try_callback(pbuf_free_int, p);
+}
+
+/**
+ * A simple wrapper function that allows you to free heap memory from
+ * interrupt context.
+ *
+ * @param m the heap memory to free
+ * @return ERR_OK if callback could be enqueued, an err_t if not
+ */
+err_t
+mem_free_callback(void *m)
+{
+  return tcpip_try_callback(mem_free, m);
+}
+
+#endif /* !NO_SYS */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp.c
new file mode 100644
index 000000000..d46d6cdb1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp.c
@@ -0,0 +1,681 @@
+/**
+ * @file
+ * @defgroup altcp Application layered TCP Functions
+ * @ingroup altcp_api
+ *
+ * This file contains the common functions for altcp to work.
+ * For more details see @ref altcp_api.
+ */
+
+/**
+ * @defgroup altcp_api Application layered TCP Introduction
+ * @ingroup callbackstyle_api
+ *
+ * Overview
+ * --------
+ * altcp (application layered TCP connection API; to be used from TCPIP thread)
+ * is an abstraction layer that prevents applications linking hard against the
+ * @ref tcp.h functions while providing the same functionality. It is used to
+ * e.g. add SSL/TLS (see LWIP_ALTCP_TLS) or proxy-connect support to an application
+ * written for the tcp callback API without that application knowing the
+ * protocol details.
+ *
+ * * This interface mimics the tcp callback API to the application while preventing
+ *   direct linking (much like virtual functions).
+ * * This way, an application can make use of other application layer protocols
+ *   on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ * * This is achieved by simply including "lwip/altcp.h" instead of "lwip/tcp.h",
+ *   replacing "struct tcp_pcb" with "struct altcp_pcb" and prefixing all functions
+ *   with "altcp_" instead of "tcp_".
+ *
+ * With altcp support disabled (LWIP_ALTCP==0), applications written against the
+ * altcp API can still be compiled but are directly linked against the tcp.h
+ * callback API and then cannot use layered protocols. To minimize code changes
+ * in this case, the use of altcp_allocators is strongly suggested.
+ *
+ * Usage
+ * -----
+ * To make use of this API from an existing tcp raw API application:
+ * * Include "lwip/altcp.h" instead of "lwip/tcp.h"
+ * * Replace "struct tcp_pcb" with "struct altcp_pcb"
+ * * Prefix all called tcp API functions with "altcp_" instead of "tcp_" to link
+ *   against the altcp functions
+ * * @ref altcp_new (and @ref altcp_new_ip_type/@ref altcp_new_ip6) take
+ *   an @ref altcp_allocator_t as an argument, whereas the original tcp API
+ *   functions take no arguments.
+ * * An @ref altcp_allocator_t allocator is an object that holds a pointer to an
+ *   allocator object and a corresponding state (e.g. for TLS, the corresponding
+ *   state may hold certificates or keys). This way, the application does not
+ *   even need to know if it uses TLS or pure TCP, this is handled at runtime
+ *   by passing a specific allocator.
+ * * An application can alternatively bind hard to the altcp_tls API by calling
+ *   @ref altcp_tls_new or @ref altcp_tls_wrap.
+ * * The TLS layer is not directly implemented by lwIP, but a port to mbedTLS is
+ *   provided.
+ * * Another altcp layer is proxy-connect to use TLS behind a HTTP proxy (see
+ *   @ref altcp_proxyconnect.h)
+ *
+ * altcp_allocator_t
+ * -----------------
+ * An altcp allocator is created by the application by combining an allocator
+ * callback function and a corresponding state, e.g.:\code{.c}
+ * static const unsigned char cert[] = {0x2D, ... (see mbedTLS doc for how to create this)};
+ * struct altcp_tls_config * conf = altcp_tls_create_config_client(cert, sizeof(cert));
+ * altcp_allocator_t tls_allocator = {
+ *   altcp_tls_alloc, conf
+ * };
+ * \endcode
+ *
+ *
+ * struct altcp_tls_config
+ * -----------------------
+ * The struct altcp_tls_config holds state that is needed to create new TLS client
+ * or server connections (e.g. certificates and private keys).
+ *
+ * It is not defined by lwIP itself but by the TLS port (e.g. altcp_tls to mbedTLS
+ * adaption). However, the parameters used to create it are defined in @ref
+ * altcp_tls.h (see @ref altcp_tls_create_config_server_privkey_cert for servers
+ * and @ref altcp_tls_create_config_client/@ref altcp_tls_create_config_client_2wayauth
+ * for clients).
+ *
+ * For mbedTLS, ensure that certificates can be parsed by 'mbedtls_x509_crt_parse()' and
+ * private keys can be parsed by 'mbedtls_pk_parse_key()'.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+#include "lwip/priv/altcp_priv.h"
+#include "lwip/altcp_tcp.h"
+#include "lwip/tcp.h"
+#include "lwip/mem.h"
+
+#include <string.h>
+
+extern const struct altcp_functions altcp_tcp_functions;
+
+/**
+ * For altcp layer implementations only: allocate a new struct altcp_pcb from the pool
+ * and zero the memory
+ */
+struct altcp_pcb *
+altcp_alloc(void)
+{
+  struct altcp_pcb *ret = (struct altcp_pcb *)memp_malloc(MEMP_ALTCP_PCB);
+  if (ret != NULL) {
+    memset(ret, 0, sizeof(struct altcp_pcb));
+  }
+  return ret;
+}
+
+/**
+ * For altcp layer implementations only: return a struct altcp_pcb to the pool
+ */
+void
+altcp_free(struct altcp_pcb *conn)
+{
+  if (conn) {
+    if (conn->fns && conn->fns->dealloc) {
+      conn->fns->dealloc(conn);
+    }
+    memp_free(MEMP_ALTCP_PCB, conn);
+  }
+}
+
+/**
+ * @ingroup altcp
+ * altcp_new_ip6: @ref altcp_new for IPv6 
+ */
+struct altcp_pcb *
+altcp_new_ip6(altcp_allocator_t *allocator)
+{
+  return altcp_new_ip_type(allocator, IPADDR_TYPE_V6);
+}
+
+/** 
+ * @ingroup altcp
+ * altcp_new: @ref altcp_new for IPv4 
+ */
+struct altcp_pcb *
+altcp_new(altcp_allocator_t *allocator)
+{
+  return altcp_new_ip_type(allocator, IPADDR_TYPE_V4);
+}
+
+/**
+ * @ingroup altcp
+ * altcp_new_ip_type: called by applications to allocate a new pcb with the help of an
+ * allocator function.
+ *
+ * @param allocator allocator function and argument
+ * @param ip_type IP version of the pcb (@ref lwip_ip_addr_type)
+ * @return a new altcp_pcb or NULL on error
+ */
+struct altcp_pcb *
+altcp_new_ip_type(altcp_allocator_t *allocator, u8_t ip_type)
+{
+  struct altcp_pcb *conn;
+  if (allocator == NULL) {
+    /* no allocator given, create a simple TCP connection */
+    return altcp_tcp_new_ip_type(ip_type);
+  }
+  if (allocator->alloc == NULL) {
+    /* illegal allocator */
+    return NULL;
+  }
+  conn = allocator->alloc(allocator->arg, ip_type);
+  if (conn == NULL) {
+    /* allocation failed */
+    return NULL;
+  }
+  return conn;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_arg()
+ */
+void
+altcp_arg(struct altcp_pcb *conn, void *arg)
+{
+  if (conn) {
+    conn->arg = arg;
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_accept()
+ */
+void
+altcp_accept(struct altcp_pcb *conn, altcp_accept_fn accept)
+{
+  if (conn != NULL) {
+    conn->accept = accept;
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_recv()
+ */
+void
+altcp_recv(struct altcp_pcb *conn, altcp_recv_fn recv)
+{
+  if (conn) {
+    conn->recv = recv;
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_sent()
+ */
+void
+altcp_sent(struct altcp_pcb *conn, altcp_sent_fn sent)
+{
+  if (conn) {
+    conn->sent = sent;
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_poll()
+ */
+void
+altcp_poll(struct altcp_pcb *conn, altcp_poll_fn poll, u8_t interval)
+{
+  if (conn) {
+    conn->poll = poll;
+    conn->pollinterval = interval;
+    if (conn->fns && conn->fns->set_poll) {
+      conn->fns->set_poll(conn, interval);
+    }
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_err()
+ */
+void
+altcp_err(struct altcp_pcb *conn, altcp_err_fn err)
+{
+  if (conn) {
+    conn->err = err;
+  }
+}
+
+/* Generic functions calling the "virtual" ones */
+
+/**
+ * @ingroup altcp
+ * @see tcp_recved()
+ */
+void
+altcp_recved(struct altcp_pcb *conn, u16_t len)
+{
+  if (conn && conn->fns && conn->fns->recved) {
+    conn->fns->recved(conn, len);
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_bind()
+ */
+err_t
+altcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port)
+{
+  if (conn && conn->fns && conn->fns->bind) {
+    return conn->fns->bind(conn, ipaddr, port);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_connect()
+ */
+err_t
+altcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected)
+{
+  if (conn && conn->fns && conn->fns->connect) {
+    return conn->fns->connect(conn, ipaddr, port, connected);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_listen_with_backlog_and_err()
+ */
+struct altcp_pcb *
+altcp_listen_with_backlog_and_err(struct altcp_pcb *conn, u8_t backlog, err_t *err)
+{
+  if (conn && conn->fns && conn->fns->listen) {
+    return conn->fns->listen(conn, backlog, err);
+  }
+  return NULL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_abort()
+ */
+void
+altcp_abort(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->abort) {
+    conn->fns->abort(conn);
+  }
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_close()
+ */
+err_t
+altcp_close(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->close) {
+    return conn->fns->close(conn);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_shutdown()
+ */
+err_t
+altcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx)
+{
+  if (conn && conn->fns && conn->fns->shutdown) {
+    return conn->fns->shutdown(conn, shut_rx, shut_tx);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_write()
+ */
+err_t
+altcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags)
+{
+  if (conn && conn->fns && conn->fns->write) {
+    return conn->fns->write(conn, dataptr, len, apiflags);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_output()
+ */
+err_t
+altcp_output(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->output) {
+    return conn->fns->output(conn);
+  }
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_mss()
+ */
+u16_t
+altcp_mss(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->mss) {
+    return conn->fns->mss(conn);
+  }
+  return 0;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_sndbuf()
+ */
+u16_t
+altcp_sndbuf(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->sndbuf) {
+    return conn->fns->sndbuf(conn);
+  }
+  return 0;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_sndqueuelen()
+ */
+u16_t
+altcp_sndqueuelen(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->sndqueuelen) {
+    return conn->fns->sndqueuelen(conn);
+  }
+  return 0;
+}
+
+void
+altcp_nagle_disable(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->nagle_disable) {
+    conn->fns->nagle_disable(conn);
+  }
+}
+
+void
+altcp_nagle_enable(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->nagle_enable) {
+    conn->fns->nagle_enable(conn);
+  }
+}
+
+int
+altcp_nagle_disabled(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->nagle_disabled) {
+    return conn->fns->nagle_disabled(conn);
+  }
+  return 0;
+}
+
+/**
+ * @ingroup altcp
+ * @see tcp_setprio()
+ */
+void
+altcp_setprio(struct altcp_pcb *conn, u8_t prio)
+{
+  if (conn && conn->fns && conn->fns->setprio) {
+    conn->fns->setprio(conn, prio);
+  }
+}
+
+err_t
+altcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port)
+{
+  if (conn && conn->fns && conn->fns->addrinfo) {
+    return conn->fns->addrinfo(conn, local, addr, port);
+  }
+  return ERR_VAL;
+}
+
+ip_addr_t *
+altcp_get_ip(struct altcp_pcb *conn, int local)
+{
+  if (conn && conn->fns && conn->fns->getip) {
+    return conn->fns->getip(conn, local);
+  }
+  return NULL;
+}
+
+u16_t
+altcp_get_port(struct altcp_pcb *conn, int local)
+{
+  if (conn && conn->fns && conn->fns->getport) {
+    return conn->fns->getport(conn, local);
+  }
+  return 0;
+}
+
+#ifdef LWIP_DEBUG
+enum tcp_state
+altcp_dbg_get_tcp_state(struct altcp_pcb *conn)
+{
+  if (conn && conn->fns && conn->fns->dbg_get_tcp_state) {
+    return conn->fns->dbg_get_tcp_state(conn);
+  }
+  return CLOSED;
+}
+#endif
+
+/* Default implementations for the "virtual" functions */
+
+void
+altcp_default_set_poll(struct altcp_pcb *conn, u8_t interval)
+{
+  if (conn && conn->inner_conn) {
+    altcp_poll(conn->inner_conn, conn->poll, interval);
+  }
+}
+
+void
+altcp_default_recved(struct altcp_pcb *conn, u16_t len)
+{
+  if (conn && conn->inner_conn) {
+    altcp_recved(conn->inner_conn, len);
+  }
+}
+
+err_t
+altcp_default_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_bind(conn->inner_conn, ipaddr, port);
+  }
+  return ERR_VAL;
+}
+
+err_t
+altcp_default_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx)
+{
+  if (conn) {
+    if (shut_rx && shut_tx && conn->fns && conn->fns->close) {
+      /* default shutdown for both sides is close */
+      return conn->fns->close(conn);
+    }
+    if (conn->inner_conn) {
+      return altcp_shutdown(conn->inner_conn, shut_rx, shut_tx);
+    }
+  }
+  return ERR_VAL;
+}
+
+err_t
+altcp_default_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_write(conn->inner_conn, dataptr, len, apiflags);
+  }
+  return ERR_VAL;
+}
+
+err_t
+altcp_default_output(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_output(conn->inner_conn);
+  }
+  return ERR_VAL;
+}
+
+u16_t
+altcp_default_mss(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_mss(conn->inner_conn);
+  }
+  return 0;
+}
+
+u16_t
+altcp_default_sndbuf(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_sndbuf(conn->inner_conn);
+  }
+  return 0;
+}
+
+u16_t
+altcp_default_sndqueuelen(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_sndqueuelen(conn->inner_conn);
+  }
+  return 0;
+}
+
+void
+altcp_default_nagle_disable(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    altcp_nagle_disable(conn->inner_conn);
+  }
+}
+
+void
+altcp_default_nagle_enable(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    altcp_nagle_enable(conn->inner_conn);
+  }
+}
+
+int
+altcp_default_nagle_disabled(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_nagle_disabled(conn->inner_conn);
+  }
+  return 0;
+}
+
+void
+altcp_default_setprio(struct altcp_pcb *conn, u8_t prio)
+{
+  if (conn && conn->inner_conn) {
+    altcp_setprio(conn->inner_conn, prio);
+  }
+}
+
+void
+altcp_default_dealloc(struct altcp_pcb *conn)
+{
+  LWIP_UNUSED_ARG(conn);
+  /* nothing to do */
+}
+
+err_t
+altcp_default_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_get_tcp_addrinfo(conn->inner_conn, local, addr, port);
+  }
+  return ERR_VAL;
+}
+
+ip_addr_t *
+altcp_default_get_ip(struct altcp_pcb *conn, int local)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_get_ip(conn->inner_conn, local);
+  }
+  return NULL;
+}
+
+u16_t
+altcp_default_get_port(struct altcp_pcb *conn, int local)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_get_port(conn->inner_conn, local);
+  }
+  return 0;
+}
+
+#ifdef LWIP_DEBUG
+enum tcp_state
+altcp_default_dbg_get_tcp_state(struct altcp_pcb *conn)
+{
+  if (conn && conn->inner_conn) {
+    return altcp_dbg_get_tcp_state(conn->inner_conn);
+  }
+  return CLOSED;
+}
+#endif
+
+
+#endif /* LWIP_ALTCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp_alloc.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp_alloc.c
new file mode 100644
index 000000000..cd619bc1b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp_alloc.c
@@ -0,0 +1,87 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ * This interface mimics the tcp callback API to the application while preventing
+ * direct linking (much like virtual functions).
+ * This way, an application can make use of other application layer protocols
+ * on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ *
+ * This file contains allocation implementation that combine several layers.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+#include "lwip/altcp_tcp.h"
+#include "lwip/altcp_tls.h"
+#include "lwip/priv/altcp_priv.h"
+#include "lwip/mem.h"
+
+#include <string.h>
+
+#if LWIP_ALTCP_TLS
+
+/** This standard allocator function creates an altcp pcb for
+ * TLS over TCP */
+struct altcp_pcb *
+altcp_tls_new(struct altcp_tls_config *config, u8_t ip_type)
+{
+  struct altcp_pcb *inner_conn, *ret;
+  LWIP_UNUSED_ARG(ip_type);
+
+  inner_conn = altcp_tcp_new_ip_type(ip_type);
+  if (inner_conn == NULL) {
+    return NULL;
+  }
+  ret = altcp_tls_wrap(config, inner_conn);
+  if (ret == NULL) {
+    altcp_close(inner_conn);
+  }
+  return ret;
+}
+
+/** This standard allocator function creates an altcp pcb for
+ * TLS over TCP */
+struct altcp_pcb *
+altcp_tls_alloc(void *arg, u8_t ip_type)
+{
+  return altcp_tls_new((struct altcp_tls_config *)arg, ip_type);
+}
+
+#endif /* LWIP_ALTCP_TLS */
+
+#endif /* LWIP_ALTCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp_tcp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp_tcp.c
new file mode 100644
index 000000000..b715f0457
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/altcp_tcp.c
@@ -0,0 +1,543 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ * This interface mimics the tcp callback API to the application while preventing
+ * direct linking (much like virtual functions).
+ * This way, an application can make use of other application layer protocols
+ * on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ *
+ * This file contains the base implementation calling into tcp.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+#include "lwip/altcp_tcp.h"
+#include "lwip/priv/altcp_priv.h"
+#include "lwip/tcp.h"
+#include "lwip/mem.h"
+
+#include <string.h>
+
+#define ALTCP_TCP_ASSERT_CONN(conn) do { \
+  LWIP_ASSERT("conn->inner_conn == NULL", (conn)->inner_conn == NULL); \
+  LWIP_UNUSED_ARG(conn); /* for LWIP_NOASSERT */ } while(0)
+#define ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb) do { \
+  LWIP_ASSERT("pcb mismatch", (conn)->state == tpcb); \
+  LWIP_UNUSED_ARG(tpcb); /* for LWIP_NOASSERT */ \
+  ALTCP_TCP_ASSERT_CONN(conn); } while(0)
+
+
+/* Variable prototype, the actual declaration is at the end of this file
+   since it contains pointers to static functions declared here */
+extern const struct altcp_functions altcp_tcp_functions;
+
+static void altcp_tcp_setup(struct altcp_pcb *conn, struct tcp_pcb *tpcb);
+
+/* callback functions for TCP */
+static err_t
+altcp_tcp_accept(void *arg, struct tcp_pcb *new_tpcb, err_t err)
+{
+  struct altcp_pcb *listen_conn = (struct altcp_pcb *)arg;
+  if (listen_conn && listen_conn->accept) {
+    /* create a new altcp_conn to pass to the next 'accept' callback */
+    struct altcp_pcb *new_conn = altcp_alloc();
+    if (new_conn == NULL) {
+      return ERR_MEM;
+    }
+    altcp_tcp_setup(new_conn, new_tpcb);
+    return listen_conn->accept(listen_conn->arg, new_conn, err);
+  }
+  return ERR_ARG;
+}
+
+static err_t
+altcp_tcp_connected(void *arg, struct tcp_pcb *tpcb, err_t err)
+{
+  struct altcp_pcb *conn = (struct altcp_pcb *)arg;
+  if (conn) {
+    ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb);
+    if (conn->connected) {
+      return conn->connected(conn->arg, conn, err);
+    }
+  }
+  return ERR_OK;
+}
+
+static err_t
+altcp_tcp_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)
+{
+  struct altcp_pcb *conn = (struct altcp_pcb *)arg;
+  if (conn) {
+    ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb);
+    if (conn->recv) {
+      return conn->recv(conn->arg, conn, p, err);
+    }
+  }
+  if (p != NULL) {
+    /* prevent memory leaks */
+    pbuf_free(p);
+  }
+  return ERR_OK;
+}
+
+static err_t
+altcp_tcp_sent(void *arg, struct tcp_pcb *tpcb, u16_t len)
+{
+  struct altcp_pcb *conn = (struct altcp_pcb *)arg;
+  if (conn) {
+    ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb);
+    if (conn->sent) {
+      return conn->sent(conn->arg, conn, len);
+    }
+  }
+  return ERR_OK;
+}
+
+static err_t
+altcp_tcp_poll(void *arg, struct tcp_pcb *tpcb)
+{
+  struct altcp_pcb *conn = (struct altcp_pcb *)arg;
+  if (conn) {
+    ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb);
+    if (conn->poll) {
+      return conn->poll(conn->arg, conn);
+    }
+  }
+  return ERR_OK;
+}
+
+static void
+altcp_tcp_err(void *arg, err_t err)
+{
+  struct altcp_pcb *conn = (struct altcp_pcb *)arg;
+  if (conn) {
+    conn->state = NULL; /* already freed */
+    if (conn->err) {
+      conn->err(conn->arg, err);
+    }
+    altcp_free(conn);
+  }
+}
+
+/* setup functions */
+
+static void
+altcp_tcp_remove_callbacks(struct tcp_pcb *tpcb)
+{
+  tcp_arg(tpcb, NULL);
+  tcp_recv(tpcb, NULL);
+  tcp_sent(tpcb, NULL);
+  tcp_err(tpcb, NULL);
+  tcp_poll(tpcb, NULL, tpcb->pollinterval);
+}
+
+static void
+altcp_tcp_setup_callbacks(struct altcp_pcb *conn, struct tcp_pcb *tpcb)
+{
+  tcp_arg(tpcb, conn);
+  tcp_recv(tpcb, altcp_tcp_recv);
+  tcp_sent(tpcb, altcp_tcp_sent);
+  tcp_err(tpcb, altcp_tcp_err);
+  /* tcp_poll is set when interval is set by application */
+  /* listen is set totally different :-) */
+}
+
+static void
+altcp_tcp_setup(struct altcp_pcb *conn, struct tcp_pcb *tpcb)
+{
+  altcp_tcp_setup_callbacks(conn, tpcb);
+  conn->state = tpcb;
+  conn->fns = &altcp_tcp_functions;
+}
+
+struct altcp_pcb *
+altcp_tcp_new_ip_type(u8_t ip_type)
+{
+  /* Allocate the tcp pcb first to invoke the priority handling code
+     if we're out of pcbs */
+  struct tcp_pcb *tpcb = tcp_new_ip_type(ip_type);
+  if (tpcb != NULL) {
+    struct altcp_pcb *ret = altcp_alloc();
+    if (ret != NULL) {
+      altcp_tcp_setup(ret, tpcb);
+      return ret;
+    } else {
+      /* altcp_pcb allocation failed -> free the tcp_pcb too */
+      tcp_close(tpcb);
+    }
+  }
+  return NULL;
+}
+
+/** altcp_tcp allocator function fitting to @ref altcp_allocator_t / @ref altcp_new.
+*
+* arg pointer is not used for TCP.
+*/
+struct altcp_pcb *
+altcp_tcp_alloc(void *arg, u8_t ip_type)
+{
+  LWIP_UNUSED_ARG(arg);
+  return altcp_tcp_new_ip_type(ip_type);
+}
+
+struct altcp_pcb *
+altcp_tcp_wrap(struct tcp_pcb *tpcb)
+{
+  if (tpcb != NULL) {
+    struct altcp_pcb *ret = altcp_alloc();
+    if (ret != NULL) {
+      altcp_tcp_setup(ret, tpcb);
+      return ret;
+    }
+  }
+  return NULL;
+}
+
+
+/* "virtual" functions calling into tcp */
+static void
+altcp_tcp_set_poll(struct altcp_pcb *conn, u8_t interval)
+{
+  if (conn != NULL) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    tcp_poll(pcb, altcp_tcp_poll, interval);
+  }
+}
+
+static void
+altcp_tcp_recved(struct altcp_pcb *conn, u16_t len)
+{
+  if (conn != NULL) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    tcp_recved(pcb, len);
+  }
+}
+
+static err_t
+altcp_tcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_bind(pcb, ipaddr, port);
+}
+
+static err_t
+altcp_tcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  conn->connected = connected;
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_connect(pcb, ipaddr, port, altcp_tcp_connected);
+}
+
+static struct altcp_pcb *
+altcp_tcp_listen(struct altcp_pcb *conn, u8_t backlog, err_t *err)
+{
+  struct tcp_pcb *pcb;
+  struct tcp_pcb *lpcb;
+  if (conn == NULL) {
+    return NULL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  lpcb = tcp_listen_with_backlog_and_err(pcb, backlog, err);
+  if (lpcb != NULL) {
+    conn->state = lpcb;
+    tcp_accept(lpcb, altcp_tcp_accept);
+    return conn;
+  }
+  return NULL;
+}
+
+static void
+altcp_tcp_abort(struct altcp_pcb *conn)
+{
+  if (conn != NULL) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    if (pcb) {
+      tcp_abort(pcb);
+    }
+  }
+}
+
+static err_t
+altcp_tcp_close(struct altcp_pcb *conn)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  if (pcb) {
+    err_t err;
+    tcp_poll_fn oldpoll = pcb->poll;
+    altcp_tcp_remove_callbacks(pcb);
+    err = tcp_close(pcb);
+    if (err != ERR_OK) {
+      /* not closed, set up all callbacks again */
+      altcp_tcp_setup_callbacks(conn, pcb);
+      /* poll callback is not included in the above */
+      tcp_poll(pcb, oldpoll, pcb->pollinterval);
+      return err;
+    }
+    conn->state = NULL; /* unsafe to reference pcb after tcp_close(). */
+  }
+  altcp_free(conn);
+  return ERR_OK;
+}
+
+static err_t
+altcp_tcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_shutdown(pcb, shut_rx, shut_tx);
+}
+
+static err_t
+altcp_tcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_write(pcb, dataptr, len, apiflags);
+}
+
+static err_t
+altcp_tcp_output(struct altcp_pcb *conn)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_output(pcb);
+}
+
+static u16_t
+altcp_tcp_mss(struct altcp_pcb *conn)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return 0;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_mss(pcb);
+}
+
+static u16_t
+altcp_tcp_sndbuf(struct altcp_pcb *conn)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return 0;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_sndbuf(pcb);
+}
+
+static u16_t
+altcp_tcp_sndqueuelen(struct altcp_pcb *conn)
+{
+  struct tcp_pcb *pcb;
+  if (conn == NULL) {
+    return 0;
+  }
+  ALTCP_TCP_ASSERT_CONN(conn);
+  pcb = (struct tcp_pcb *)conn->state;
+  return tcp_sndqueuelen(pcb);
+}
+
+static void
+altcp_tcp_nagle_disable(struct altcp_pcb *conn)
+{
+  if (conn && conn->state) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    tcp_nagle_disable(pcb);
+  }
+}
+
+static void
+altcp_tcp_nagle_enable(struct altcp_pcb *conn)
+{
+  if (conn && conn->state) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    tcp_nagle_enable(pcb);
+  }
+}
+
+static int
+altcp_tcp_nagle_disabled(struct altcp_pcb *conn)
+{
+  if (conn && conn->state) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    return tcp_nagle_disabled(pcb);
+  }
+  return 0;
+}
+
+static void
+altcp_tcp_setprio(struct altcp_pcb *conn, u8_t prio)
+{
+  if (conn != NULL) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    tcp_setprio(pcb, prio);
+  }
+}
+
+static void
+altcp_tcp_dealloc(struct altcp_pcb *conn)
+{
+  LWIP_UNUSED_ARG(conn);
+  ALTCP_TCP_ASSERT_CONN(conn);
+  /* no private state to clean up */
+}
+
+static err_t
+altcp_tcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port)
+{
+  if (conn) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    return tcp_tcp_get_tcp_addrinfo(pcb, local, addr, port);
+  }
+  return ERR_VAL;
+}
+
+static ip_addr_t *
+altcp_tcp_get_ip(struct altcp_pcb *conn, int local)
+{
+  if (conn) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    if (pcb) {
+      if (local) {
+        return &pcb->local_ip;
+      } else {
+        return &pcb->remote_ip;
+      }
+    }
+  }
+  return NULL;
+}
+
+static u16_t
+altcp_tcp_get_port(struct altcp_pcb *conn, int local)
+{
+  if (conn) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    if (pcb) {
+      if (local) {
+        return pcb->local_port;
+      } else {
+        return pcb->remote_port;
+      }
+    }
+  }
+  return 0;
+}
+
+#ifdef LWIP_DEBUG
+static enum tcp_state
+altcp_tcp_dbg_get_tcp_state(struct altcp_pcb *conn)
+{
+  if (conn) {
+    struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state;
+    ALTCP_TCP_ASSERT_CONN(conn);
+    if (pcb) {
+      return pcb->state;
+    }
+  }
+  return CLOSED;
+}
+#endif
+const struct altcp_functions altcp_tcp_functions = {
+  altcp_tcp_set_poll,
+  altcp_tcp_recved,
+  altcp_tcp_bind,
+  altcp_tcp_connect,
+  altcp_tcp_listen,
+  altcp_tcp_abort,
+  altcp_tcp_close,
+  altcp_tcp_shutdown,
+  altcp_tcp_write,
+  altcp_tcp_output,
+  altcp_tcp_mss,
+  altcp_tcp_sndbuf,
+  altcp_tcp_sndqueuelen,
+  altcp_tcp_nagle_disable,
+  altcp_tcp_nagle_enable,
+  altcp_tcp_nagle_disabled,
+  altcp_tcp_setprio,
+  altcp_tcp_dealloc,
+  altcp_tcp_get_tcp_addrinfo,
+  altcp_tcp_get_ip,
+  altcp_tcp_get_port
+#ifdef LWIP_DEBUG
+  , altcp_tcp_dbg_get_tcp_state
+#endif
+};
+
+#endif /* LWIP_ALTCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/def.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/def.c
new file mode 100644
index 000000000..9da36fee8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/def.c
@@ -0,0 +1,240 @@
+/**
+ * @file
+ * Common functions used throughout the stack.
+ *
+ * These are reference implementations of the byte swapping functions.
+ * Again with the aim of being simple, correct and fully portable.
+ * Byte swapping is the second thing you would want to optimize. You will
+ * need to port it to your architecture and in your cc.h:
+ *
+ * \#define lwip_htons(x) your_htons
+ * \#define lwip_htonl(x) your_htonl
+ *
+ * Note lwip_ntohs() and lwip_ntohl() are merely references to the htonx counterparts.
+ *
+ * If you \#define them to htons() and htonl(), you should
+ * \#define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS to prevent lwIP from
+ * defining htonx/ntohx compatibility macros.
+
+ * @defgroup sys_nonstandard Non-standard functions
+ * @ingroup sys_layer
+ * lwIP provides default implementations for non-standard functions.
+ * These can be mapped to OS functions to reduce code footprint if desired.
+ * All defines related to this section must not be placed in lwipopts.h,
+ * but in arch/cc.h!
+ * These options cannot be \#defined in lwipopts.h since they are not options
+ * of lwIP itself, but options of the lwIP port to your system.
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#include <string.h>
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+
+#if !defined(lwip_htons)
+/**
+ * Convert an u16_t from host- to network byte order.
+ *
+ * @param n u16_t in host byte order
+ * @return n in network byte order
+ */
+u16_t
+lwip_htons(u16_t n)
+{
+  return PP_HTONS(n);
+}
+#endif /* lwip_htons */
+
+#if !defined(lwip_htonl)
+/**
+ * Convert an u32_t from host- to network byte order.
+ *
+ * @param n u32_t in host byte order
+ * @return n in network byte order
+ */
+u32_t
+lwip_htonl(u32_t n)
+{
+  return PP_HTONL(n);
+}
+#endif /* lwip_htonl */
+
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
+
+#ifndef lwip_strnstr
+/**
+ * @ingroup sys_nonstandard
+ * lwIP default implementation for strnstr() non-standard function.
+ * This can be \#defined to strnstr() depending on your platform port.
+ */
+char *
+lwip_strnstr(const char *buffer, const char *token, size_t n)
+{
+  const char *p;
+  size_t tokenlen = strlen(token);
+  if (tokenlen == 0) {
+    return LWIP_CONST_CAST(char *, buffer);
+  }
+  for (p = buffer; *p && (p + tokenlen <= buffer + n); p++) {
+    if ((*p == *token) && (strncmp(p, token, tokenlen) == 0)) {
+      return LWIP_CONST_CAST(char *, p);
+    }
+  }
+  return NULL;
+}
+#endif
+
+#ifndef lwip_stricmp
+/**
+ * @ingroup sys_nonstandard
+ * lwIP default implementation for stricmp() non-standard function.
+ * This can be \#defined to stricmp() depending on your platform port.
+ */
+int
+lwip_stricmp(const char *str1, const char *str2)
+{
+  char c1, c2;
+
+  do {
+    c1 = *str1++;
+    c2 = *str2++;
+    if (c1 != c2) {
+      char c1_upc = c1 | 0x20;
+      if ((c1_upc >= 'a') && (c1_upc <= 'z')) {
+        /* characters are not equal an one is in the alphabet range:
+        downcase both chars and check again */
+        char c2_upc = c2 | 0x20;
+        if (c1_upc != c2_upc) {
+          /* still not equal */
+          /* don't care for < or > */
+          return 1;
+        }
+      } else {
+        /* characters are not equal but none is in the alphabet range */
+        return 1;
+      }
+    }
+  } while (c1 != 0);
+  return 0;
+}
+#endif
+
+#ifndef lwip_strnicmp
+/**
+ * @ingroup sys_nonstandard
+ * lwIP default implementation for strnicmp() non-standard function.
+ * This can be \#defined to strnicmp() depending on your platform port.
+ */
+int
+lwip_strnicmp(const char *str1, const char *str2, size_t len)
+{
+  char c1, c2;
+
+  do {
+    c1 = *str1++;
+    c2 = *str2++;
+    if (c1 != c2) {
+      char c1_upc = c1 | 0x20;
+      if ((c1_upc >= 'a') && (c1_upc <= 'z')) {
+        /* characters are not equal an one is in the alphabet range:
+        downcase both chars and check again */
+        char c2_upc = c2 | 0x20;
+        if (c1_upc != c2_upc) {
+          /* still not equal */
+          /* don't care for < or > */
+          return 1;
+        }
+      } else {
+        /* characters are not equal but none is in the alphabet range */
+        return 1;
+      }
+    }
+    len--;
+  } while ((len != 0) && (c1 != 0));
+  return 0;
+}
+#endif
+
+#ifndef lwip_itoa
+/**
+ * @ingroup sys_nonstandard
+ * lwIP default implementation for itoa() non-standard function.
+ * This can be \#defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform port.
+ */
+void
+lwip_itoa(char *result, size_t bufsize, int number)
+{
+  char *res = result;
+  char *tmp = result + bufsize - 1;
+  int n = (number >= 0) ? number : -number;
+
+  /* handle invalid bufsize */
+  if (bufsize < 2) {
+    if (bufsize == 1) {
+      *result = 0;
+    }
+    return;
+  }
+
+  /* First, add sign */
+  if (number < 0) {
+    *res++ = '-';
+  }
+  /* Then create the string from the end and stop if buffer full,
+     and ensure output string is zero terminated */
+  *tmp = 0;
+  while ((n != 0) && (tmp > res)) {
+    char val = (char)('0' + (n % 10));
+    tmp--;
+    *tmp = val;
+    n = n / 10;
+  }
+  if (n) {
+    /* buffer is too small */
+    *result = 0;
+    return;
+  }
+  if (*tmp == 0) {
+    /* Nothing added? */
+    *res++ = '0';
+    *res++ = 0;
+    return;
+  }
+  /* move from temporary buffer to output buffer (sign is not moved) */
+  memmove(res, tmp, (size_t)((result + bufsize) - tmp));
+}
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/dns.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/dns.c
new file mode 100644
index 000000000..9d2f61ed8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/dns.c
@@ -0,0 +1,1631 @@
+/**
+ * @file
+ * DNS - host name to IP address resolver.
+ *
+ * @defgroup dns DNS
+ * @ingroup callbackstyle_api
+ *
+ * Implements a DNS host name to IP address resolver.
+ *
+ * The lwIP DNS resolver functions are used to lookup a host name and
+ * map it to a numerical IP address. It maintains a list of resolved
+ * hostnames that can be queried with the dns_lookup() function.
+ * New hostnames can be resolved using the dns_query() function.
+ *
+ * The lwIP version of the resolver also adds a non-blocking version of
+ * gethostbyname() that will work with a raw API application. This function
+ * checks for an IP address string first and converts it if it is valid.
+ * gethostbyname() then does a dns_lookup() to see if the name is
+ * already in the table. If so, the IP is returned. If not, a query is
+ * issued and the function returns with a ERR_INPROGRESS status. The app
+ * using the dns client must then go into a waiting state.
+ *
+ * Once a hostname has been resolved (or found to be non-existent),
+ * the resolver code calls a specified callback function (which
+ * must be implemented by the module that uses the resolver).
+ *
+ * Multicast DNS queries are supported for names ending on ".local".
+ * However, only "One-Shot Multicast DNS Queries" are supported (RFC 6762
+ * chapter 5.1), this is not a fully compliant implementation of continuous
+ * mDNS querying!
+ *
+ * All functions must be called from TCPIP thread.
+ *
+ * @see DNS_MAX_SERVERS
+ * @see LWIP_DHCP_MAX_DNS_SERVERS
+ * @see @ref netconn_common for thread-safe access.
+ */
+
+/*
+ * Port to lwIP from uIP
+ * by Jim Pettinato April 2007
+ *
+ * security fixes and more by Simon Goldschmidt
+ *
+ * uIP version Copyright (c) 2002-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-----------------------------------------------------------------------------
+ * RFC 1035 - Domain names - implementation and specification
+ * RFC 2181 - Clarifications to the DNS Specification
+ *----------------------------------------------------------------------------*/
+
+/** @todo: define good default values (rfc compliance) */
+/** @todo: improve answer parsing, more checkings... */
+/** @todo: check RFC1035 - 7.3. Processing responses */
+/** @todo: one-shot mDNS: dual-stack fallback to another IP version */
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/udp.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/dns.h"
+#include "lwip/prot/dns.h"
+
+#include <string.h>
+
+/** Random generator function to create random TXIDs and source ports for queries */
+#ifndef DNS_RAND_TXID
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_XID) != 0)
+#define DNS_RAND_TXID LWIP_RAND
+#else
+static u16_t dns_txid;
+#define DNS_RAND_TXID() (++dns_txid)
+#endif
+#endif
+
+/** Limits the source port to be >= 1024 by default */
+#ifndef DNS_PORT_ALLOWED
+#define DNS_PORT_ALLOWED(port) ((port) >= 1024)
+#endif
+
+/** DNS resource record max. TTL (one week as default) */
+#ifndef DNS_MAX_TTL
+#define DNS_MAX_TTL               604800
+#elif DNS_MAX_TTL > 0x7FFFFFFF
+#error DNS_MAX_TTL must be a positive 32-bit value
+#endif
+
+#if DNS_TABLE_SIZE > 255
+#error DNS_TABLE_SIZE must fit into an u8_t
+#endif
+#if DNS_MAX_SERVERS > 255
+#error DNS_MAX_SERVERS must fit into an u8_t
+#endif
+
+/* The number of parallel requests (i.e. calls to dns_gethostbyname
+ * that cannot be answered from the DNS table.
+ * This is set to the table size by default.
+ */
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0)
+#ifndef DNS_MAX_REQUESTS
+#define DNS_MAX_REQUESTS          DNS_TABLE_SIZE
+#else
+#if DNS_MAX_REQUESTS > 255
+#error DNS_MAX_REQUESTS must fit into an u8_t
+#endif
+#endif
+#else
+/* In this configuration, both arrays have to have the same size and are used
+ * like one entry (used/free) */
+#define DNS_MAX_REQUESTS          DNS_TABLE_SIZE
+#endif
+
+/* The number of UDP source ports used in parallel */
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+#ifndef DNS_MAX_SOURCE_PORTS
+#define DNS_MAX_SOURCE_PORTS      DNS_MAX_REQUESTS
+#else
+#if DNS_MAX_SOURCE_PORTS > 255
+#error DNS_MAX_SOURCE_PORTS must fit into an u8_t
+#endif
+#endif
+#else
+#ifdef DNS_MAX_SOURCE_PORTS
+#undef DNS_MAX_SOURCE_PORTS
+#endif
+#define DNS_MAX_SOURCE_PORTS      1
+#endif
+
+#if LWIP_IPV4 && LWIP_IPV6
+#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) (((t) == LWIP_DNS_ADDRTYPE_IPV6_IPV4) || ((t) == LWIP_DNS_ADDRTYPE_IPV6))
+#define LWIP_DNS_ADDRTYPE_MATCH_IP(t, ip) (IP_IS_V6_VAL(ip) ? LWIP_DNS_ADDRTYPE_IS_IPV6(t) : (!LWIP_DNS_ADDRTYPE_IS_IPV6(t)))
+#define LWIP_DNS_ADDRTYPE_ARG(x) , x
+#define LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(x) x
+#define LWIP_DNS_SET_ADDRTYPE(x, y) do { x = y; } while(0)
+#else
+#if LWIP_IPV6
+#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) 1
+#else
+#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) 0
+#endif
+#define LWIP_DNS_ADDRTYPE_MATCH_IP(t, ip) 1
+#define LWIP_DNS_ADDRTYPE_ARG(x)
+#define LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(x) 0
+#define LWIP_DNS_SET_ADDRTYPE(x, y)
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+#define LWIP_DNS_ISMDNS_ARG(x) , x
+#else
+#define LWIP_DNS_ISMDNS_ARG(x)
+#endif
+
+/** DNS query message structure.
+    No packing needed: only used locally on the stack. */
+struct dns_query {
+  /* DNS query record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  u16_t type;
+  u16_t cls;
+};
+#define SIZEOF_DNS_QUERY 4
+
+/** DNS answer message structure.
+    No packing needed: only used locally on the stack. */
+struct dns_answer {
+  /* DNS answer record starts with either a domain name or a pointer
+     to a name already present somewhere in the packet. */
+  u16_t type;
+  u16_t cls;
+  u32_t ttl;
+  u16_t len;
+};
+#define SIZEOF_DNS_ANSWER 10
+/* maximum allowed size for the struct due to non-packed */
+#define SIZEOF_DNS_ANSWER_ASSERT 12
+
+/* DNS table entry states */
+typedef enum {
+  DNS_STATE_UNUSED           = 0,
+  DNS_STATE_NEW              = 1,
+  DNS_STATE_ASKING           = 2,
+  DNS_STATE_DONE             = 3
+} dns_state_enum_t;
+
+/** DNS table entry */
+struct dns_table_entry {
+  u32_t ttl;
+  ip_addr_t ipaddr;
+  u16_t txid;
+  u8_t  state;
+  u8_t  server_idx;
+  u8_t  tmr;
+  u8_t  retries;
+  u8_t  seqno;
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+  u8_t pcb_idx;
+#endif
+  char name[DNS_MAX_NAME_LENGTH];
+#if LWIP_IPV4 && LWIP_IPV6
+  u8_t reqaddrtype;
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+  u8_t is_mdns;
+#endif
+};
+
+/** DNS request table entry: used when dns_gehostbyname cannot answer the
+ * request from the DNS table */
+struct dns_req_entry {
+  /* pointer to callback on DNS query done */
+  dns_found_callback found;
+  /* argument passed to the callback function */
+  void *arg;
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0)
+  u8_t dns_table_idx;
+#endif
+#if LWIP_IPV4 && LWIP_IPV6
+  u8_t reqaddrtype;
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+};
+
+#if DNS_LOCAL_HOSTLIST
+
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+/** Local host-list. For hostnames in this list, no
+ *  external name resolution is performed */
+static struct local_hostlist_entry *local_hostlist_dynamic;
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/** Defining this allows the local_hostlist_static to be placed in a different
+ * linker section (e.g. FLASH) */
+#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE
+#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static
+#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */
+/** Defining this allows the local_hostlist_static to be placed in a different
+ * linker section (e.g. FLASH) */
+#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST
+#define DNS_LOCAL_HOSTLIST_STORAGE_POST
+#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */
+DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[]
+  DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT;
+
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+static void dns_init_local(void);
+static err_t dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype));
+#endif /* DNS_LOCAL_HOSTLIST */
+
+
+/* forward declarations */
+static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port);
+static void dns_check_entries(void);
+static void dns_call_found(u8_t idx, ip_addr_t *addr);
+
+/*-----------------------------------------------------------------------------
+ * Globals
+ *----------------------------------------------------------------------------*/
+
+/* DNS variables */
+static struct udp_pcb        *dns_pcbs[DNS_MAX_SOURCE_PORTS];
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+static u8_t                   dns_last_pcb_idx;
+#endif
+static u8_t                   dns_seqno;
+static struct dns_table_entry dns_table[DNS_TABLE_SIZE];
+static struct dns_req_entry   dns_requests[DNS_MAX_REQUESTS];
+static ip_addr_t              dns_servers[DNS_MAX_SERVERS];
+
+#if LWIP_IPV4
+const ip_addr_t dns_mquery_v4group = DNS_MQUERY_IPV4_GROUP_INIT;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+const ip_addr_t dns_mquery_v6group = DNS_MQUERY_IPV6_GROUP_INIT;
+#endif /* LWIP_IPV6 */
+
+/**
+ * Initialize the resolver: set up the UDP pcb and configure the default server
+ * (if DNS_SERVER_ADDRESS is set).
+ */
+void
+dns_init(void)
+{
+#ifdef DNS_SERVER_ADDRESS
+  /* initialize default DNS server address */
+  ip_addr_t dnsserver;
+  DNS_SERVER_ADDRESS(&dnsserver);
+  dns_setserver(0, &dnsserver);
+#endif /* DNS_SERVER_ADDRESS */
+
+  LWIP_ASSERT("sanity check SIZEOF_DNS_QUERY",
+              sizeof(struct dns_query) == SIZEOF_DNS_QUERY);
+  LWIP_ASSERT("sanity check SIZEOF_DNS_ANSWER",
+              sizeof(struct dns_answer) <= SIZEOF_DNS_ANSWER_ASSERT);
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n"));
+
+  /* if dns client not yet initialized... */
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0)
+  if (dns_pcbs[0] == NULL) {
+    dns_pcbs[0] = udp_new_ip_type(IPADDR_TYPE_ANY);
+    LWIP_ASSERT("dns_pcbs[0] != NULL", dns_pcbs[0] != NULL);
+
+    /* initialize DNS table not needed (initialized to zero since it is a
+     * global variable) */
+    LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0",
+                DNS_STATE_UNUSED == 0);
+
+    /* initialize DNS client */
+    udp_bind(dns_pcbs[0], IP_ANY_TYPE, 0);
+    udp_recv(dns_pcbs[0], dns_recv, NULL);
+  }
+#endif
+
+#if DNS_LOCAL_HOSTLIST
+  dns_init_local();
+#endif
+}
+
+/**
+ * @ingroup dns
+ * Initialize one of the DNS servers.
+ *
+ * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS
+ * @param dnsserver IP address of the DNS server to set
+ */
+void
+dns_setserver(u8_t numdns, const ip_addr_t *dnsserver)
+{
+  if (numdns < DNS_MAX_SERVERS) {
+    if (dnsserver != NULL) {
+      dns_servers[numdns] = (*dnsserver);
+    } else {
+      dns_servers[numdns] = *IP_ADDR_ANY;
+    }
+  }
+}
+
+/**
+ * @ingroup dns
+ * Obtain one of the currently configured DNS server.
+ *
+ * @param numdns the index of the DNS server
+ * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS
+ *         server has not been configured.
+ */
+const ip_addr_t *
+dns_getserver(u8_t numdns)
+{
+  if (numdns < DNS_MAX_SERVERS) {
+    return &dns_servers[numdns];
+  } else {
+    return IP_ADDR_ANY;
+  }
+}
+
+/**
+ * The DNS resolver client timer - handle retries and timeouts and should
+ * be called every DNS_TMR_INTERVAL milliseconds (every second by default).
+ */
+void
+dns_tmr(void)
+{
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n"));
+  dns_check_entries();
+}
+
+#if DNS_LOCAL_HOSTLIST
+static void
+dns_init_local(void)
+{
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT)
+  size_t i;
+  struct local_hostlist_entry *entry;
+  /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */
+  struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT;
+  size_t namelen;
+  for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_init); i++) {
+    struct local_hostlist_entry *init_entry = &local_hostlist_init[i];
+    LWIP_ASSERT("invalid host name (NULL)", init_entry->name != NULL);
+    namelen = strlen(init_entry->name);
+    LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN);
+    entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST);
+    LWIP_ASSERT("mem-error in dns_init_local", entry != NULL);
+    if (entry != NULL) {
+      char *entry_name = (char *)entry + sizeof(struct local_hostlist_entry);
+      MEMCPY(entry_name, init_entry->name, namelen);
+      entry_name[namelen] = 0;
+      entry->name = entry_name;
+      entry->addr = init_entry->addr;
+      entry->next = local_hostlist_dynamic;
+      local_hostlist_dynamic = entry;
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */
+}
+
+/**
+ * @ingroup dns
+ * Iterate the local host-list for a hostname.
+ *
+ * @param iterator_fn a function that is called for every entry in the local host-list
+ * @param iterator_arg 3rd argument passed to iterator_fn
+ * @return the number of entries in the local host-list
+ */
+size_t
+dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg)
+{
+  size_t i;
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  i = 0;
+  while (entry != NULL) {
+    if (iterator_fn != NULL) {
+      iterator_fn(entry->name, &entry->addr, iterator_arg);
+    }
+    i++;
+    entry = entry->next;
+  }
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_static); i++) {
+    if (iterator_fn != NULL) {
+      iterator_fn(local_hostlist_static[i].name, &local_hostlist_static[i].addr, iterator_arg);
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  return i;
+}
+
+/**
+ * @ingroup dns
+ * Scans the local host-list for a hostname.
+ *
+ * @param hostname Hostname to look for in the local host-list
+ * @param addr the first IP address for the hostname in the local host-list or
+ *         IPADDR_NONE if not found.
+ * @param dns_addrtype - LWIP_DNS_ADDRTYPE_IPV4_IPV6: try to resolve IPv4 (ATTENTION: no fallback here!)
+ *                     - LWIP_DNS_ADDRTYPE_IPV6_IPV4: try to resolve IPv6 (ATTENTION: no fallback here!)
+ *                     - LWIP_DNS_ADDRTYPE_IPV4: try to resolve IPv4 only
+ *                     - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only
+ * @return ERR_OK if found, ERR_ARG if not found
+ */
+err_t
+dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype)
+{
+  LWIP_UNUSED_ARG(dns_addrtype);
+  return dns_lookup_local(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype));
+}
+
+/* Internal implementation for dns_local_lookup and dns_lookup */
+static err_t
+dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype))
+{
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  while (entry != NULL) {
+    if ((lwip_stricmp(entry->name, hostname) == 0) &&
+        LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, entry->addr)) {
+      if (addr) {
+        ip_addr_copy(*addr, entry->addr);
+      }
+      return ERR_OK;
+    }
+    entry = entry->next;
+  }
+#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  size_t i;
+  for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_static); i++) {
+    if ((lwip_stricmp(local_hostlist_static[i].name, hostname) == 0) &&
+        LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, local_hostlist_static[i].addr)) {
+      if (addr) {
+        ip_addr_copy(*addr, local_hostlist_static[i].addr);
+      }
+      return ERR_OK;
+    }
+  }
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+  return ERR_ARG;
+}
+
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+/**
+ * @ingroup dns
+ * Remove all entries from the local host-list for a specific hostname
+ * and/or IP address
+ *
+ * @param hostname hostname for which entries shall be removed from the local
+ *                 host-list
+ * @param addr address for which entries shall be removed from the local host-list
+ * @return the number of removed entries
+ */
+int
+dns_local_removehost(const char *hostname, const ip_addr_t *addr)
+{
+  int removed = 0;
+  struct local_hostlist_entry *entry = local_hostlist_dynamic;
+  struct local_hostlist_entry *last_entry = NULL;
+  while (entry != NULL) {
+    if (((hostname == NULL) || !lwip_stricmp(entry->name, hostname)) &&
+        ((addr == NULL) || ip_addr_cmp(&entry->addr, addr))) {
+      struct local_hostlist_entry *free_entry;
+      if (last_entry != NULL) {
+        last_entry->next = entry->next;
+      } else {
+        local_hostlist_dynamic = entry->next;
+      }
+      free_entry = entry;
+      entry = entry->next;
+      memp_free(MEMP_LOCALHOSTLIST, free_entry);
+      removed++;
+    } else {
+      last_entry = entry;
+      entry = entry->next;
+    }
+  }
+  return removed;
+}
+
+/**
+ * @ingroup dns
+ * Add a hostname/IP address pair to the local host-list.
+ * Duplicates are not checked.
+ *
+ * @param hostname hostname of the new entry
+ * @param addr IP address of the new entry
+ * @return ERR_OK if succeeded or ERR_MEM on memory error
+ */
+err_t
+dns_local_addhost(const char *hostname, const ip_addr_t *addr)
+{
+  struct local_hostlist_entry *entry;
+  size_t namelen;
+  char *entry_name;
+  LWIP_ASSERT("invalid host name (NULL)", hostname != NULL);
+  namelen = strlen(hostname);
+  LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN);
+  entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST);
+  if (entry == NULL) {
+    return ERR_MEM;
+  }
+  entry_name = (char *)entry + sizeof(struct local_hostlist_entry);
+  MEMCPY(entry_name, hostname, namelen);
+  entry_name[namelen] = 0;
+  entry->name = entry_name;
+  ip_addr_copy(entry->addr, *addr);
+  entry->next = local_hostlist_dynamic;
+  local_hostlist_dynamic = entry;
+  return ERR_OK;
+}
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/**
+ * @ingroup dns
+ * Look up a hostname in the array of known hostnames.
+ *
+ * @note This function only looks in the internal array of known
+ * hostnames, it does not send out a query for the hostname if none
+ * was found. The function dns_enqueue() can be used to send a query
+ * for a hostname.
+ *
+ * @param name the hostname to look up
+ * @param addr the hostname's IP address, as u32_t (instead of ip_addr_t to
+ *         better check for failure: != IPADDR_NONE) or IPADDR_NONE if the hostname
+ *         was not found in the cached dns_table.
+ * @return ERR_OK if found, ERR_ARG if not found
+ */
+static err_t
+dns_lookup(const char *name, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype))
+{
+  u8_t i;
+#if DNS_LOCAL_HOSTLIST
+  if (dns_lookup_local(name, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) {
+    return ERR_OK;
+  }
+#endif /* DNS_LOCAL_HOSTLIST */
+#ifdef DNS_LOOKUP_LOCAL_EXTERN
+  if (DNS_LOOKUP_LOCAL_EXTERN(name, addr, LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(dns_addrtype)) == ERR_OK) {
+    return ERR_OK;
+  }
+#endif /* DNS_LOOKUP_LOCAL_EXTERN */
+
+  /* Walk through name list, return entry if found. If not, return NULL. */
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    if ((dns_table[i].state == DNS_STATE_DONE) &&
+        (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0) &&
+        LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, dns_table[i].ipaddr)) {
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name));
+      ip_addr_debug_print_val(DNS_DEBUG, dns_table[i].ipaddr);
+      LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+      if (addr) {
+        ip_addr_copy(*addr, dns_table[i].ipaddr);
+      }
+      return ERR_OK;
+    }
+  }
+
+  return ERR_ARG;
+}
+
+/**
+ * Compare the "dotted" name "query" with the encoded name "response"
+ * to make sure an answer from the DNS server matches the current dns_table
+ * entry (otherwise, answers might arrive late for hostname not on the list
+ * any more).
+ *
+ * For now, this function compares case-insensitive to cope with all kinds of
+ * servers. This also means that "dns 0x20 bit encoding" must be checked
+ * externally, if we want to implement it.
+ * Currently, the request is sent exactly as passed in by he user request.
+ *
+ * @param query hostname (not encoded) from the dns_table
+ * @param p pbuf containing the encoded hostname in the DNS response
+ * @param start_offset offset into p where the name starts
+ * @return 0xFFFF: names differ, other: names equal -> offset behind name
+ */
+static u16_t
+dns_compare_name(const char *query, struct pbuf *p, u16_t start_offset)
+{
+  int n;
+  u16_t response_offset = start_offset;
+
+  do {
+    n = pbuf_try_get_at(p, response_offset);
+    if ((n < 0) || (response_offset == 0xFFFF)) {
+      /* error or overflow */
+      return 0xFFFF;
+    }
+    response_offset++;
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name: cannot be equal since we don't send them */
+      return 0xFFFF;
+    } else {
+      /* Not compressed name */
+      while (n > 0) {
+        int c = pbuf_try_get_at(p, response_offset);
+        if (c < 0) {
+          return 0xFFFF;
+        }
+        if (lwip_tolower((*query)) != lwip_tolower((u8_t)c)) {
+          return 0xFFFF;
+        }
+        if (response_offset == 0xFFFF) {
+          /* would overflow */
+          return 0xFFFF;
+        }
+        response_offset++;
+        ++query;
+        --n;
+      }
+      ++query;
+    }
+    n = pbuf_try_get_at(p, response_offset);
+    if (n < 0) {
+      return 0xFFFF;
+    }
+  } while (n != 0);
+
+  if (response_offset == 0xFFFF) {
+    /* would overflow */
+    return 0xFFFF;
+  }
+  return (u16_t)(response_offset + 1);
+}
+
+/**
+ * Walk through a compact encoded DNS name and return the end of the name.
+ *
+ * @param p pbuf containing the name
+ * @param query_idx start index into p pointing to encoded DNS name in the DNS server response
+ * @return index to end of the name
+ */
+static u16_t
+dns_skip_name(struct pbuf *p, u16_t query_idx)
+{
+  int n;
+  u16_t offset = query_idx;
+
+  do {
+    n = pbuf_try_get_at(p, offset++);
+    if ((n < 0) || (offset == 0)) {
+      return 0xFFFF;
+    }
+    /** @see RFC 1035 - 4.1.4. Message compression */
+    if ((n & 0xc0) == 0xc0) {
+      /* Compressed name: since we only want to skip it (not check it), stop here */
+      break;
+    } else {
+      /* Not compressed name */
+      if (offset + n >= p->tot_len) {
+        return 0xFFFF;
+      }
+      offset = (u16_t)(offset + n);
+    }
+    n = pbuf_try_get_at(p, offset);
+    if (n < 0) {
+      return 0xFFFF;
+    }
+  } while (n != 0);
+
+  if (offset == 0xFFFF) {
+    return 0xFFFF;
+  }
+  return (u16_t)(offset + 1);
+}
+
+/**
+ * Send a DNS query packet.
+ *
+ * @param idx the DNS table entry index for which to send a request
+ * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise
+ */
+static err_t
+dns_send(u8_t idx)
+{
+  err_t err;
+  struct dns_hdr hdr;
+  struct dns_query qry;
+  struct pbuf *p;
+  u16_t query_idx, copy_len;
+  const char *hostname, *hostname_part;
+  u8_t n;
+  u8_t pcb_idx;
+  struct dns_table_entry *entry = &dns_table[idx];
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n",
+                          (u16_t)(entry->server_idx), entry->name));
+  LWIP_ASSERT("dns server out of array", entry->server_idx < DNS_MAX_SERVERS);
+  if (ip_addr_isany_val(dns_servers[entry->server_idx])
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+      && !entry->is_mdns
+#endif
+     ) {
+    /* DNS server not valid anymore, e.g. PPP netif has been shut down */
+    /* call specified callback function if provided */
+    dns_call_found(idx, NULL);
+    /* flush this entry */
+    entry->state = DNS_STATE_UNUSED;
+    return ERR_OK;
+  }
+
+  /* if here, we have either a new query or a retry on a previous query to process */
+  p = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(SIZEOF_DNS_HDR + strlen(entry->name) + 2 +
+                                         SIZEOF_DNS_QUERY), PBUF_RAM);
+  if (p != NULL) {
+    const ip_addr_t *dst;
+    u16_t dst_port;
+    /* fill dns header */
+    memset(&hdr, 0, SIZEOF_DNS_HDR);
+    hdr.id = lwip_htons(entry->txid);
+    hdr.flags1 = DNS_FLAG1_RD;
+    hdr.numquestions = PP_HTONS(1);
+    pbuf_take(p, &hdr, SIZEOF_DNS_HDR);
+    hostname = entry->name;
+    --hostname;
+
+    /* convert hostname into suitable query format. */
+    query_idx = SIZEOF_DNS_HDR;
+    do {
+      ++hostname;
+      hostname_part = hostname;
+      for (n = 0; *hostname != '.' && *hostname != 0; ++hostname) {
+        ++n;
+      }
+      copy_len = (u16_t)(hostname - hostname_part);
+      if (query_idx + n + 1 > 0xFFFF) {
+        /* u16_t overflow */
+        goto overflow_return;
+      }
+      pbuf_put_at(p, query_idx, n);
+      pbuf_take_at(p, hostname_part, copy_len, (u16_t)(query_idx + 1));
+      query_idx = (u16_t)(query_idx + n + 1);
+    } while (*hostname != 0);
+    pbuf_put_at(p, query_idx, 0);
+    query_idx++;
+
+    /* fill dns query */
+    if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) {
+      qry.type = PP_HTONS(DNS_RRTYPE_AAAA);
+    } else {
+      qry.type = PP_HTONS(DNS_RRTYPE_A);
+    }
+    qry.cls = PP_HTONS(DNS_RRCLASS_IN);
+    pbuf_take_at(p, &qry, SIZEOF_DNS_QUERY, query_idx);
+
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+    pcb_idx = entry->pcb_idx;
+#else
+    pcb_idx = 0;
+#endif
+    /* send dns packet */
+    LWIP_DEBUGF(DNS_DEBUG, ("sending DNS request ID %d for name \"%s\" to server %d\r\n",
+                            entry->txid, entry->name, entry->server_idx));
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+    if (entry->is_mdns) {
+      dst_port = DNS_MQUERY_PORT;
+#if LWIP_IPV6
+      if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) {
+        dst = &dns_mquery_v6group;
+      }
+#endif
+#if LWIP_IPV4 && LWIP_IPV6
+      else
+#endif
+#if LWIP_IPV4
+      {
+        dst = &dns_mquery_v4group;
+      }
+#endif
+    } else
+#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */
+    {
+      dst_port = DNS_SERVER_PORT;
+      dst = &dns_servers[entry->server_idx];
+    }
+    err = udp_sendto(dns_pcbs[pcb_idx], p, dst, dst_port);
+
+    /* free pbuf */
+    pbuf_free(p);
+  } else {
+    err = ERR_MEM;
+  }
+
+  return err;
+overflow_return:
+  pbuf_free(p);
+  return ERR_VAL;
+}
+
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+static struct udp_pcb *
+dns_alloc_random_port(void)
+{
+  err_t err;
+  struct udp_pcb *pcb;
+
+  pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
+  if (pcb == NULL) {
+    /* out of memory, have to reuse an existing pcb */
+    return NULL;
+  }
+  do {
+    u16_t port = (u16_t)DNS_RAND_TXID();
+    if (DNS_PORT_ALLOWED(port)) {
+      err = udp_bind(pcb, IP_ANY_TYPE, port);
+    } else {
+      /* this port is not allowed, try again */
+      err = ERR_USE;
+    }
+  } while (err == ERR_USE);
+  if (err != ERR_OK) {
+    udp_remove(pcb);
+    return NULL;
+  }
+  udp_recv(pcb, dns_recv, NULL);
+  return pcb;
+}
+
+/**
+ * dns_alloc_pcb() - allocates a new pcb (or reuses an existing one) to be used
+ * for sending a request
+ *
+ * @return an index into dns_pcbs
+ */
+static u8_t
+dns_alloc_pcb(void)
+{
+  u8_t i;
+  u8_t idx;
+
+  for (i = 0; i < DNS_MAX_SOURCE_PORTS; i++) {
+    if (dns_pcbs[i] == NULL) {
+      break;
+    }
+  }
+  if (i < DNS_MAX_SOURCE_PORTS) {
+    dns_pcbs[i] = dns_alloc_random_port();
+    if (dns_pcbs[i] != NULL) {
+      /* succeeded */
+      dns_last_pcb_idx = i;
+      return i;
+    }
+  }
+  /* if we come here, creating a new UDP pcb failed, so we have to use
+     an already existing one (so overflow is no issue) */
+  for (i = 0, idx = (u8_t)(dns_last_pcb_idx + 1); i < DNS_MAX_SOURCE_PORTS; i++, idx++) {
+    if (idx >= DNS_MAX_SOURCE_PORTS) {
+      idx = 0;
+    }
+    if (dns_pcbs[idx] != NULL) {
+      dns_last_pcb_idx = idx;
+      return idx;
+    }
+  }
+  return DNS_MAX_SOURCE_PORTS;
+}
+#endif /* ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) */
+
+/**
+ * dns_call_found() - call the found callback and check if there are duplicate
+ * entries for the given hostname. If there are any, their found callback will
+ * be called and they will be removed.
+ *
+ * @param idx dns table index of the entry that is resolved or removed
+ * @param addr IP address for the hostname (or NULL on error or memory shortage)
+ */
+static void
+dns_call_found(u8_t idx, ip_addr_t *addr)
+{
+#if ((LWIP_DNS_SECURE & (LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)) != 0)
+  u8_t i;
+#endif
+
+#if LWIP_IPV4 && LWIP_IPV6
+  if (addr != NULL) {
+    /* check that address type matches the request and adapt the table entry */
+    if (IP_IS_V6_VAL(*addr)) {
+      LWIP_ASSERT("invalid response", LWIP_DNS_ADDRTYPE_IS_IPV6(dns_table[idx].reqaddrtype));
+      dns_table[idx].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV6;
+    } else {
+      LWIP_ASSERT("invalid response", !LWIP_DNS_ADDRTYPE_IS_IPV6(dns_table[idx].reqaddrtype));
+      dns_table[idx].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV4;
+    }
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0)
+  for (i = 0; i < DNS_MAX_REQUESTS; i++) {
+    if (dns_requests[i].found && (dns_requests[i].dns_table_idx == idx)) {
+      (*dns_requests[i].found)(dns_table[idx].name, addr, dns_requests[i].arg);
+      /* flush this entry */
+      dns_requests[i].found = NULL;
+    }
+  }
+#else
+  if (dns_requests[idx].found) {
+    (*dns_requests[idx].found)(dns_table[idx].name, addr, dns_requests[idx].arg);
+  }
+  dns_requests[idx].found = NULL;
+#endif
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+  /* close the pcb used unless other request are using it */
+  for (i = 0; i < DNS_MAX_REQUESTS; i++) {
+    if (i == idx) {
+      continue; /* only check other requests */
+    }
+    if (dns_table[i].state == DNS_STATE_ASKING) {
+      if (dns_table[i].pcb_idx == dns_table[idx].pcb_idx) {
+        /* another request is still using the same pcb */
+        dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS;
+        break;
+      }
+    }
+  }
+  if (dns_table[idx].pcb_idx < DNS_MAX_SOURCE_PORTS) {
+    /* if we come here, the pcb is not used any more and can be removed */
+    udp_remove(dns_pcbs[dns_table[idx].pcb_idx]);
+    dns_pcbs[dns_table[idx].pcb_idx] = NULL;
+    dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS;
+  }
+#endif
+}
+
+/* Create a query transmission ID that is unique for all outstanding queries */
+static u16_t
+dns_create_txid(void)
+{
+  u16_t txid;
+  u8_t i;
+
+again:
+  txid = (u16_t)DNS_RAND_TXID();
+
+  /* check whether the ID is unique */
+  for (i = 0; i < DNS_TABLE_SIZE; i++) {
+    if ((dns_table[i].state == DNS_STATE_ASKING) &&
+        (dns_table[i].txid == txid)) {
+      /* ID already used by another pending query */
+      goto again;
+    }
+  }
+
+  return txid;
+}
+
+/**
+ * Check whether there are other backup DNS servers available to try
+ */
+static u8_t
+dns_backupserver_available(struct dns_table_entry *pentry)
+{
+  u8_t ret = 0;
+
+  if (pentry) {
+    if ((pentry->server_idx + 1 < DNS_MAX_SERVERS) && !ip_addr_isany_val(dns_servers[pentry->server_idx + 1])) {
+      ret = 1;
+    }
+  }
+
+  return ret;
+}
+
+/**
+ * dns_check_entry() - see if entry has not yet been queried and, if so, sends out a query.
+ * Check an entry in the dns_table:
+ * - send out query for new entries
+ * - retry old pending entries on timeout (also with different servers)
+ * - remove completed entries from the table if their TTL has expired
+ *
+ * @param i index of the dns_table entry to check
+ */
+static void
+dns_check_entry(u8_t i)
+{
+  err_t err;
+  struct dns_table_entry *entry = &dns_table[i];
+
+  LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE);
+
+  switch (entry->state) {
+    case DNS_STATE_NEW:
+      /* initialize new entry */
+      entry->txid = dns_create_txid();
+      entry->state = DNS_STATE_ASKING;
+      entry->server_idx = 0;
+      entry->tmr = 1;
+      entry->retries = 0;
+
+      /* send DNS packet for this entry */
+      err = dns_send(i);
+      if (err != ERR_OK) {
+        LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING,
+                    ("dns_send returned error: %s\n", lwip_strerr(err)));
+      }
+      break;
+    case DNS_STATE_ASKING:
+      if (--entry->tmr == 0) {
+        if (++entry->retries == DNS_MAX_RETRIES) {
+          if (dns_backupserver_available(entry)
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+              && !entry->is_mdns
+#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */
+             ) {
+            /* change of server */
+            entry->server_idx++;
+            entry->tmr = 1;
+            entry->retries = 0;
+          } else {
+            LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", entry->name));
+            /* call specified callback function if provided */
+            dns_call_found(i, NULL);
+            /* flush this entry */
+            entry->state = DNS_STATE_UNUSED;
+            break;
+          }
+        } else {
+          /* wait longer for the next retry */
+          entry->tmr = entry->retries;
+        }
+
+        /* send DNS packet for this entry */
+        err = dns_send(i);
+        if (err != ERR_OK) {
+          LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING,
+                      ("dns_send returned error: %s\n", lwip_strerr(err)));
+        }
+      }
+      break;
+    case DNS_STATE_DONE:
+      /* if the time to live is nul */
+      if ((entry->ttl == 0) || (--entry->ttl == 0)) {
+        LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", entry->name));
+        /* flush this entry, there cannot be any related pending entries in this state */
+        entry->state = DNS_STATE_UNUSED;
+      }
+      break;
+    case DNS_STATE_UNUSED:
+      /* nothing to do */
+      break;
+    default:
+      LWIP_ASSERT("unknown dns_table entry state:", 0);
+      break;
+  }
+}
+
+/**
+ * Call dns_check_entry for each entry in dns_table - check all entries.
+ */
+static void
+dns_check_entries(void)
+{
+  u8_t i;
+
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    dns_check_entry(i);
+  }
+}
+
+/**
+ * Save TTL and call dns_call_found for correct response.
+ */
+static void
+dns_correct_response(u8_t idx, u32_t ttl)
+{
+  struct dns_table_entry *entry = &dns_table[idx];
+
+  entry->state = DNS_STATE_DONE;
+
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", entry->name));
+  ip_addr_debug_print_val(DNS_DEBUG, entry->ipaddr);
+  LWIP_DEBUGF(DNS_DEBUG, ("\n"));
+
+  /* read the answer resource record's TTL, and maximize it if needed */
+  entry->ttl = ttl;
+  if (entry->ttl > DNS_MAX_TTL) {
+    entry->ttl = DNS_MAX_TTL;
+  }
+  dns_call_found(idx, &entry->ipaddr);
+
+  if (entry->ttl == 0) {
+    /* RFC 883, page 29: "Zero values are
+       interpreted to mean that the RR can only be used for the
+       transaction in progress, and should not be cached."
+       -> flush this entry now */
+    /* entry reused during callback? */
+    if (entry->state == DNS_STATE_DONE) {
+      entry->state = DNS_STATE_UNUSED;
+    }
+  }
+}
+
+/**
+ * Receive input function for DNS response packets arriving for the dns UDP pcb.
+ */
+static void
+dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
+{
+  u8_t i;
+  u16_t txid;
+  u16_t res_idx;
+  struct dns_hdr hdr;
+  struct dns_answer ans;
+  struct dns_query qry;
+  u16_t nquestions, nanswers;
+
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(port);
+
+  /* is the dns message big enough ? */
+  if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY)) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n"));
+    /* free pbuf and return */
+    goto ignore_packet;
+  }
+
+  /* copy dns payload inside static buffer for processing */
+  if (pbuf_copy_partial(p, &hdr, SIZEOF_DNS_HDR, 0) == SIZEOF_DNS_HDR) {
+    /* Match the ID in the DNS header with the name table. */
+    txid = lwip_htons(hdr.id);
+    for (i = 0; i < DNS_TABLE_SIZE; i++) {
+      struct dns_table_entry *entry = &dns_table[i];
+      if ((entry->state == DNS_STATE_ASKING) &&
+          (entry->txid == txid)) {
+
+        /* We only care about the question(s) and the answers. The authrr
+           and the extrarr are simply discarded. */
+        nquestions = lwip_htons(hdr.numquestions);
+        nanswers   = lwip_htons(hdr.numanswers);
+
+        /* Check for correct response. */
+        if ((hdr.flags1 & DNS_FLAG1_RESPONSE) == 0) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": not a response\n", entry->name));
+          goto ignore_packet; /* ignore this packet */
+        }
+        if (nquestions != 1) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name));
+          goto ignore_packet; /* ignore this packet */
+        }
+
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+        if (!entry->is_mdns)
+#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */
+        {
+          /* Check whether response comes from the same network address to which the
+             question was sent. (RFC 5452) */
+          if (!ip_addr_cmp(addr, &dns_servers[entry->server_idx])) {
+            goto ignore_packet; /* ignore this packet */
+          }
+        }
+
+        /* Check if the name in the "question" part match with the name in the entry and
+           skip it if equal. */
+        res_idx = dns_compare_name(entry->name, p, SIZEOF_DNS_HDR);
+        if (res_idx == 0xFFFF) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name));
+          goto ignore_packet; /* ignore this packet */
+        }
+
+        /* check if "question" part matches the request */
+        if (pbuf_copy_partial(p, &qry, SIZEOF_DNS_QUERY, res_idx) != SIZEOF_DNS_QUERY) {
+          goto ignore_packet; /* ignore this packet */
+        }
+        if ((qry.cls != PP_HTONS(DNS_RRCLASS_IN)) ||
+            (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_AAAA))) ||
+            (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_A)))) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name));
+          goto ignore_packet; /* ignore this packet */
+        }
+        /* skip the rest of the "question" part */
+        if (res_idx + SIZEOF_DNS_QUERY > 0xFFFF) {
+          goto ignore_packet;
+        }
+        res_idx = (u16_t)(res_idx + SIZEOF_DNS_QUERY);
+
+        /* Check for error. If so, call callback to inform. */
+        if (hdr.flags2 & DNS_FLAG2_ERR_MASK) {
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", entry->name));
+
+          /* if there is another backup DNS server to try
+           * then don't stop the DNS request
+           */
+          if (dns_backupserver_available(entry)) {
+            /* avoid retrying the same server */
+            entry->retries = DNS_MAX_RETRIES-1;
+            entry->tmr     = 1;
+
+            /* contact next available server for this entry */
+            dns_check_entry(i);
+
+            goto ignore_packet;
+          }
+        } else {
+          while ((nanswers > 0) && (res_idx < p->tot_len)) {
+            /* skip answer resource record's host name */
+            res_idx = dns_skip_name(p, res_idx);
+            if (res_idx == 0xFFFF) {
+              goto ignore_packet; /* ignore this packet */
+            }
+
+            /* Check for IP address type and Internet class. Others are discarded. */
+            if (pbuf_copy_partial(p, &ans, SIZEOF_DNS_ANSWER, res_idx) != SIZEOF_DNS_ANSWER) {
+              goto ignore_packet; /* ignore this packet */
+            }
+            if (res_idx + SIZEOF_DNS_ANSWER > 0xFFFF) {
+              goto ignore_packet;
+            }
+            res_idx = (u16_t)(res_idx + SIZEOF_DNS_ANSWER);
+
+            if (ans.cls == PP_HTONS(DNS_RRCLASS_IN)) {
+#if LWIP_IPV4
+              if ((ans.type == PP_HTONS(DNS_RRTYPE_A)) && (ans.len == PP_HTONS(sizeof(ip4_addr_t)))) {
+#if LWIP_IPV4 && LWIP_IPV6
+                if (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype))
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+                {
+                  ip4_addr_t ip4addr;
+                  /* read the IP address after answer resource record's header */
+                  if (pbuf_copy_partial(p, &ip4addr, sizeof(ip4_addr_t), res_idx) != sizeof(ip4_addr_t)) {
+                    goto ignore_packet; /* ignore this packet */
+                  }
+                  ip_addr_copy_from_ip4(dns_table[i].ipaddr, ip4addr);
+                  pbuf_free(p);
+                  /* handle correct response */
+                  dns_correct_response(i, lwip_ntohl(ans.ttl));
+                  return;
+                }
+              }
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+              if ((ans.type == PP_HTONS(DNS_RRTYPE_AAAA)) && (ans.len == PP_HTONS(sizeof(ip6_addr_p_t)))) {
+#if LWIP_IPV4 && LWIP_IPV6
+                if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype))
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+                {
+                  ip6_addr_p_t ip6addr;
+                  /* read the IP address after answer resource record's header */
+                  if (pbuf_copy_partial(p, &ip6addr, sizeof(ip6_addr_p_t), res_idx) != sizeof(ip6_addr_p_t)) {
+                    goto ignore_packet; /* ignore this packet */
+                  }
+                  /* @todo: scope ip6addr? Might be required for link-local addresses at least? */
+                  ip_addr_copy_from_ip6_packed(dns_table[i].ipaddr, ip6addr);
+                  pbuf_free(p);
+                  /* handle correct response */
+                  dns_correct_response(i, lwip_ntohl(ans.ttl));
+                  return;
+                }
+              }
+#endif /* LWIP_IPV6 */
+            }
+            /* skip this answer */
+            if ((int)(res_idx + lwip_htons(ans.len)) > 0xFFFF) {
+              goto ignore_packet; /* ignore this packet */
+            }
+            res_idx = (u16_t)(res_idx + lwip_htons(ans.len));
+            --nanswers;
+          }
+#if LWIP_IPV4 && LWIP_IPV6
+          if ((entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) ||
+              (entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV6_IPV4)) {
+            if (entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) {
+              /* IPv4 failed, try IPv6 */
+              dns_table[i].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV6;
+            } else {
+              /* IPv6 failed, try IPv4 */
+              dns_table[i].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV4;
+            }
+            pbuf_free(p);
+            dns_table[i].state = DNS_STATE_NEW;
+            dns_check_entry(i);
+            return;
+          }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", entry->name));
+        }
+        /* call callback to indicate error, clean up memory and return */
+        pbuf_free(p);
+        dns_call_found(i, NULL);
+        dns_table[i].state = DNS_STATE_UNUSED;
+        return;
+      }
+    }
+  }
+
+ignore_packet:
+  /* deallocate memory and return */
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * Queues a new hostname to resolve and sends out a DNS query for that hostname
+ *
+ * @param name the hostname that is to be queried
+ * @param hostnamelen length of the hostname
+ * @param found a callback function to be called on success, failure or timeout
+ * @param callback_arg argument to pass to the callback function
+ * @return err_t return code.
+ */
+static err_t
+dns_enqueue(const char *name, size_t hostnamelen, dns_found_callback found,
+            void *callback_arg LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype) LWIP_DNS_ISMDNS_ARG(u8_t is_mdns))
+{
+  u8_t i;
+  u8_t lseq, lseqi;
+  struct dns_table_entry *entry = NULL;
+  size_t namelen;
+  struct dns_req_entry *req;
+
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0)
+  u8_t r;
+  /* check for duplicate entries */
+  for (i = 0; i < DNS_TABLE_SIZE; i++) {
+    if ((dns_table[i].state == DNS_STATE_ASKING) &&
+        (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0)) {
+#if LWIP_IPV4 && LWIP_IPV6
+      if (dns_table[i].reqaddrtype != dns_addrtype) {
+        /* requested address types don't match
+           this can lead to 2 concurrent requests, but mixing the address types
+           for the same host should not be that common */
+        continue;
+      }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+      /* this is a duplicate entry, find a free request entry */
+      for (r = 0; r < DNS_MAX_REQUESTS; r++) {
+        if (dns_requests[r].found == 0) {
+          dns_requests[r].found = found;
+          dns_requests[r].arg = callback_arg;
+          dns_requests[r].dns_table_idx = i;
+          LWIP_DNS_SET_ADDRTYPE(dns_requests[r].reqaddrtype, dns_addrtype);
+          LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": duplicate request\n", name));
+          return ERR_INPROGRESS;
+        }
+      }
+    }
+  }
+  /* no duplicate entries found */
+#endif
+
+  /* search an unused entry, or the oldest one */
+  lseq = 0;
+  lseqi = DNS_TABLE_SIZE;
+  for (i = 0; i < DNS_TABLE_SIZE; ++i) {
+    entry = &dns_table[i];
+    /* is it an unused entry ? */
+    if (entry->state == DNS_STATE_UNUSED) {
+      break;
+    }
+    /* check if this is the oldest completed entry */
+    if (entry->state == DNS_STATE_DONE) {
+      u8_t age = (u8_t)(dns_seqno - entry->seqno);
+      if (age > lseq) {
+        lseq = age;
+        lseqi = i;
+      }
+    }
+  }
+
+  /* if we don't have found an unused entry, use the oldest completed one */
+  if (i == DNS_TABLE_SIZE) {
+    if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) {
+      /* no entry can be used now, table is full */
+      LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name));
+      return ERR_MEM;
+    } else {
+      /* use the oldest completed one */
+      i = lseqi;
+      entry = &dns_table[i];
+    }
+  }
+
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0)
+  /* find a free request entry */
+  req = NULL;
+  for (r = 0; r < DNS_MAX_REQUESTS; r++) {
+    if (dns_requests[r].found == NULL) {
+      req = &dns_requests[r];
+      break;
+    }
+  }
+  if (req == NULL) {
+    /* no request entry can be used now, table is full */
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS request entries table is full\n", name));
+    return ERR_MEM;
+  }
+  req->dns_table_idx = i;
+#else
+  /* in this configuration, the entry index is the same as the request index */
+  req = &dns_requests[i];
+#endif
+
+  /* use this entry */
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i)));
+
+  /* fill the entry */
+  entry->state = DNS_STATE_NEW;
+  entry->seqno = dns_seqno;
+  LWIP_DNS_SET_ADDRTYPE(entry->reqaddrtype, dns_addrtype);
+  LWIP_DNS_SET_ADDRTYPE(req->reqaddrtype, dns_addrtype);
+  req->found = found;
+  req->arg   = callback_arg;
+  namelen = LWIP_MIN(hostnamelen, DNS_MAX_NAME_LENGTH - 1);
+  MEMCPY(entry->name, name, namelen);
+  entry->name[namelen] = 0;
+
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0)
+  entry->pcb_idx = dns_alloc_pcb();
+  if (entry->pcb_idx >= DNS_MAX_SOURCE_PORTS) {
+    /* failed to get a UDP pcb */
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": failed to allocate a pcb\n", name));
+    entry->state = DNS_STATE_UNUSED;
+    req->found = NULL;
+    return ERR_MEM;
+  }
+  LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS pcb %"U16_F"\n", name, (u16_t)(entry->pcb_idx)));
+#endif
+
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+  entry->is_mdns = is_mdns;
+#endif
+
+  dns_seqno++;
+
+  /* force to send query without waiting timer */
+  dns_check_entry(i);
+
+  /* dns query is enqueued */
+  return ERR_INPROGRESS;
+}
+
+/**
+ * @ingroup dns
+ * Resolve a hostname (string) into an IP address.
+ * NON-BLOCKING callback version for use with raw API!!!
+ *
+ * Returns immediately with one of err_t return codes:
+ * - ERR_OK if hostname is a valid IP address string or the host
+ *   name is already in the local names table.
+ * - ERR_INPROGRESS enqueue a request to be sent to the DNS server
+ *   for resolution if no errors are present.
+ * - ERR_ARG: dns client not initialized or invalid hostname
+ *
+ * @param hostname the hostname that is to be queried
+ * @param addr pointer to a ip_addr_t where to store the address if it is already
+ *             cached in the dns_table (only valid if ERR_OK is returned!)
+ * @param found a callback function to be called on success, failure or timeout (only if
+ *              ERR_INPROGRESS is returned!)
+ * @param callback_arg argument to pass to the callback function
+ * @return a err_t return code.
+ */
+err_t
+dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found,
+                  void *callback_arg)
+{
+  return dns_gethostbyname_addrtype(hostname, addr, found, callback_arg, LWIP_DNS_ADDRTYPE_DEFAULT);
+}
+
+/**
+ * @ingroup dns
+ * Like dns_gethostbyname, but returned address type can be controlled:
+ * @param hostname the hostname that is to be queried
+ * @param addr pointer to a ip_addr_t where to store the address if it is already
+ *             cached in the dns_table (only valid if ERR_OK is returned!)
+ * @param found a callback function to be called on success, failure or timeout (only if
+ *              ERR_INPROGRESS is returned!)
+ * @param callback_arg argument to pass to the callback function
+ * @param dns_addrtype - LWIP_DNS_ADDRTYPE_IPV4_IPV6: try to resolve IPv4 first, try IPv6 if IPv4 fails only
+ *                     - LWIP_DNS_ADDRTYPE_IPV6_IPV4: try to resolve IPv6 first, try IPv4 if IPv6 fails only
+ *                     - LWIP_DNS_ADDRTYPE_IPV4: try to resolve IPv4 only
+ *                     - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only
+ */
+err_t
+dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr, dns_found_callback found,
+                           void *callback_arg, u8_t dns_addrtype)
+{
+  size_t hostnamelen;
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+  u8_t is_mdns;
+#endif
+  /* not initialized or no valid server yet, or invalid addr pointer
+   * or invalid hostname or invalid hostname length */
+  if ((addr == NULL) ||
+      (!hostname) || (!hostname[0])) {
+    return ERR_ARG;
+  }
+#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0)
+  if (dns_pcbs[0] == NULL) {
+    return ERR_ARG;
+  }
+#endif
+  hostnamelen = strlen(hostname);
+  if (hostnamelen >= DNS_MAX_NAME_LENGTH) {
+    LWIP_DEBUGF(DNS_DEBUG, ("dns_gethostbyname: name too long to resolve"));
+    return ERR_ARG;
+  }
+
+
+#if LWIP_HAVE_LOOPIF
+  if (strcmp(hostname, "localhost") == 0) {
+    ip_addr_set_loopback(LWIP_DNS_ADDRTYPE_IS_IPV6(dns_addrtype), addr);
+    return ERR_OK;
+  }
+#endif /* LWIP_HAVE_LOOPIF */
+
+  /* host name already in octet notation? set ip addr and return ERR_OK */
+  if (ipaddr_aton(hostname, addr)) {
+#if LWIP_IPV4 && LWIP_IPV6
+    if ((IP_IS_V6(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV4)) ||
+        (IP_IS_V4(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV6)))
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+    {
+      return ERR_OK;
+    }
+  }
+  /* already have this address cached? */
+  if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) {
+    return ERR_OK;
+  }
+#if LWIP_IPV4 && LWIP_IPV6
+  if ((dns_addrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) || (dns_addrtype == LWIP_DNS_ADDRTYPE_IPV6_IPV4)) {
+    /* fallback to 2nd IP type and try again to lookup */
+    u8_t fallback;
+    if (dns_addrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) {
+      fallback = LWIP_DNS_ADDRTYPE_IPV6;
+    } else {
+      fallback = LWIP_DNS_ADDRTYPE_IPV4;
+    }
+    if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(fallback)) == ERR_OK) {
+      return ERR_OK;
+    }
+  }
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+  LWIP_UNUSED_ARG(dns_addrtype);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#if LWIP_DNS_SUPPORT_MDNS_QUERIES
+  if (strstr(hostname, ".local") == &hostname[hostnamelen] - 6) {
+    is_mdns = 1;
+  } else {
+    is_mdns = 0;
+  }
+
+  if (!is_mdns)
+#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */
+  {
+    /* prevent calling found callback if no server is set, return error instead */
+    if (ip_addr_isany_val(dns_servers[0])) {
+      return ERR_VAL;
+    }
+  }
+
+  /* queue query with specified callback */
+  return dns_enqueue(hostname, hostnamelen, found, callback_arg LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)
+                     LWIP_DNS_ISMDNS_ARG(is_mdns));
+}
+
+#endif /* LWIP_DNS */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/inet_chksum.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/inet_chksum.c
new file mode 100644
index 000000000..818c68f45
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/inet_chksum.c
@@ -0,0 +1,608 @@
+/**
+ * @file
+ * Internet checksum functions.\n
+ *
+ * These are some reference implementations of the checksum algorithm, with the
+ * aim of being simple, correct and fully portable. Checksumming is the
+ * first thing you would want to optimize for your platform. If you create
+ * your own version, link it in and in your cc.h put:
+ *
+ * \#define LWIP_CHKSUM your_checksum_routine
+ *
+ * Or you can select from the implementations below by defining
+ * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3.
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/inet_chksum.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+
+#include <string.h>
+
+#ifndef LWIP_CHKSUM
+# define LWIP_CHKSUM lwip_standard_chksum
+# ifndef LWIP_CHKSUM_ALGORITHM
+#  define LWIP_CHKSUM_ALGORITHM 2
+# endif
+u16_t lwip_standard_chksum(const void *dataptr, int len);
+#endif
+/* If none set: */
+#ifndef LWIP_CHKSUM_ALGORITHM
+# define LWIP_CHKSUM_ALGORITHM 0
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */
+/**
+ * lwip checksum
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ *
+ * @note accumulator size limits summable length to 64k
+ * @note host endianess is irrelevant (p3 RFC1071)
+ */
+u16_t
+lwip_standard_chksum(const void *dataptr, int len)
+{
+  u32_t acc;
+  u16_t src;
+  const u8_t *octetptr;
+
+  acc = 0;
+  /* dataptr may be at odd or even addresses */
+  octetptr = (const u8_t *)dataptr;
+  while (len > 1) {
+    /* declare first octet as most significant
+       thus assume network order, ignoring host order */
+    src = (*octetptr) << 8;
+    octetptr++;
+    /* declare second octet as least significant */
+    src |= (*octetptr);
+    octetptr++;
+    acc += src;
+    len -= 2;
+  }
+  if (len > 0) {
+    /* accumulate remaining octet */
+    src = (*octetptr) << 8;
+    acc += src;
+  }
+  /* add deferred carry bits */
+  acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  if ((acc & 0xffff0000UL) != 0) {
+    acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  }
+  /* This maybe a little confusing: reorder sum using lwip_htons()
+     instead of lwip_ntohs() since it has a little less call overhead.
+     The caller must invert bits for Internet sum ! */
+  return lwip_htons((u16_t)acc);
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */
+/*
+ * Curt McDowell
+ * Broadcom Corp.
+ * csm@broadcom.com
+ *
+ * IP checksum two bytes at a time with support for
+ * unaligned buffer.
+ * Works for len up to and including 0x20000.
+ * by Curt McDowell, Broadcom Corp. 12/08/2005
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ */
+u16_t
+lwip_standard_chksum(const void *dataptr, int len)
+{
+  const u8_t *pb = (const u8_t *)dataptr;
+  const u16_t *ps;
+  u16_t t = 0;
+  u32_t sum = 0;
+  int odd = ((mem_ptr_t)pb & 1);
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  /* Add the bulk of the data */
+  ps = (const u16_t *)(const void *)pb;
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0) {
+    ((u8_t *)&t)[0] = *(const u8_t *)ps;
+  }
+
+  /* Add end bytes */
+  sum += t;
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is probably faster than if statements... */
+  sum = FOLD_U32T(sum);
+  sum = FOLD_U32T(sum);
+
+  /* Swap if alignment was odd */
+  if (odd) {
+    sum = SWAP_BYTES_IN_WORD(sum);
+  }
+
+  return (u16_t)sum;
+}
+#endif
+
+#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */
+/**
+ * An optimized checksum routine. Basically, it uses loop-unrolling on
+ * the checksum loop, treating the head and tail bytes specially, whereas
+ * the inner loop acts on 8 bytes at a time.
+ *
+ * @arg start of buffer to be checksummed. May be an odd byte address.
+ * @len number of bytes in the buffer to be checksummed.
+ * @return host order (!) lwip checksum (non-inverted Internet sum)
+ *
+ * by Curt McDowell, Broadcom Corp. December 8th, 2005
+ */
+u16_t
+lwip_standard_chksum(const void *dataptr, int len)
+{
+  const u8_t *pb = (const u8_t *)dataptr;
+  const u16_t *ps;
+  u16_t t = 0;
+  const u32_t *pl;
+  u32_t sum = 0, tmp;
+  /* starts at odd byte address? */
+  int odd = ((mem_ptr_t)pb & 1);
+
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  ps = (const u16_t *)(const void *)pb;
+
+  if (((mem_ptr_t)ps & 3) && len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  pl = (const u32_t *)(const void *)ps;
+
+  while (len > 7)  {
+    tmp = sum + *pl++;          /* ping */
+    if (tmp < sum) {
+      tmp++;                    /* add back carry */
+    }
+
+    sum = tmp + *pl++;          /* pong */
+    if (sum < tmp) {
+      sum++;                    /* add back carry */
+    }
+
+    len -= 8;
+  }
+
+  /* make room in upper bits */
+  sum = FOLD_U32T(sum);
+
+  ps = (const u16_t *)pl;
+
+  /* 16-bit aligned word remaining? */
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* dangling tail byte remaining? */
+  if (len > 0) {                /* include odd byte */
+    ((u8_t *)&t)[0] = *(const u8_t *)ps;
+  }
+
+  sum += t;                     /* add end bytes */
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is probably faster than if statements... */
+  sum = FOLD_U32T(sum);
+  sum = FOLD_U32T(sum);
+
+  if (odd) {
+    sum = SWAP_BYTES_IN_WORD(sum);
+  }
+
+  return (u16_t)sum;
+}
+#endif
+
+/** Parts of the pseudo checksum which are common to IPv4 and IPv6 */
+static u16_t
+inet_cksum_pseudo_base(struct pbuf *p, u8_t proto, u16_t proto_len, u32_t acc)
+{
+  struct pbuf *q;
+  int swapped = 0;
+
+  /* iterate through all pbuf in chain */
+  for (q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+                             (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    /* just executing this next line is probably faster that the if statement needed
+       to check whether we really need to execute it, and does no harm */
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = !swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+
+  acc += (u32_t)lwip_htons((u16_t)proto);
+  acc += (u32_t)lwip_htons(proto_len);
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is probably faster than if statements... */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+#if LWIP_IPV4
+/* inet_chksum_pseudo:
+ *
+ * Calculates the IPv4 pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+                   const ip4_addr_t *src, const ip4_addr_t *dest)
+{
+  u32_t acc;
+  u32_t addr;
+
+  addr = ip4_addr_get_u32(src);
+  acc = (addr & 0xffffUL);
+  acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+  addr = ip4_addr_get_u32(dest);
+  acc = (u32_t)(acc + (addr & 0xffffUL));
+  acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+  /* fold down to 16 bits */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+
+  return inet_cksum_pseudo_base(p, proto, proto_len, acc);
+}
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+/**
+ * Calculates the checksum with IPv6 pseudo header used by TCP and UDP for a pbuf chain.
+ * IPv6 addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param proto ipv6 protocol/next header (used for checksum of pseudo header)
+ * @param proto_len length of the ipv6 payload (used for checksum of pseudo header)
+ * @param src source ipv6 address (used for checksum of pseudo header)
+ * @param dest destination ipv6 address (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+                  const ip6_addr_t *src, const ip6_addr_t *dest)
+{
+  u32_t acc = 0;
+  u32_t addr;
+  u8_t addr_part;
+
+  for (addr_part = 0; addr_part < 4; addr_part++) {
+    addr = src->addr[addr_part];
+    acc = (u32_t)(acc + (addr & 0xffffUL));
+    acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+    addr = dest->addr[addr_part];
+    acc = (u32_t)(acc + (addr & 0xffffUL));
+    acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+  }
+  /* fold down to 16 bits */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+
+  return inet_cksum_pseudo_base(p, proto, proto_len, acc);
+}
+#endif /* LWIP_IPV6 */
+
+/* ip_chksum_pseudo:
+ *
+ * Calculates the IPv4 or IPv6 pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+                 const ip_addr_t *src, const ip_addr_t *dest)
+{
+#if LWIP_IPV6
+  if (IP_IS_V6(dest)) {
+    return ip6_chksum_pseudo(p, proto, proto_len, ip_2_ip6(src), ip_2_ip6(dest));
+  }
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4 && LWIP_IPV6
+  else
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#if LWIP_IPV4
+  {
+    return inet_chksum_pseudo(p, proto, proto_len, ip_2_ip4(src), ip_2_ip4(dest));
+  }
+#endif /* LWIP_IPV4 */
+}
+
+/** Parts of the pseudo checksum which are common to IPv4 and IPv6 */
+static u16_t
+inet_cksum_pseudo_partial_base(struct pbuf *p, u8_t proto, u16_t proto_len,
+                               u16_t chksum_len, u32_t acc)
+{
+  struct pbuf *q;
+  int swapped = 0;
+  u16_t chklen;
+
+  /* iterate through all pbuf in chain */
+  for (q = p; (q != NULL) && (chksum_len > 0); q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+                             (void *)q, (void *)q->next));
+    chklen = q->len;
+    if (chklen > chksum_len) {
+      chklen = chksum_len;
+    }
+    acc += LWIP_CHKSUM(q->payload, chklen);
+    chksum_len = (u16_t)(chksum_len - chklen);
+    LWIP_ASSERT("delete me", chksum_len < 0x7fff);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    /* fold the upper bit down */
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = !swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+
+  acc += (u32_t)lwip_htons((u16_t)proto);
+  acc += (u32_t)lwip_htons(proto_len);
+
+  /* Fold 32-bit sum to 16 bits
+     calling this twice is probably faster than if statements... */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+#if LWIP_IPV4
+/* inet_chksum_pseudo_partial:
+ *
+ * Calculates the IPv4 pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ * IP addresses are expected to be in network byte order.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+                           u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest)
+{
+  u32_t acc;
+  u32_t addr;
+
+  addr = ip4_addr_get_u32(src);
+  acc = (addr & 0xffffUL);
+  acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+  addr = ip4_addr_get_u32(dest);
+  acc = (u32_t)(acc + (addr & 0xffffUL));
+  acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+  /* fold down to 16 bits */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+
+  return inet_cksum_pseudo_partial_base(p, proto, proto_len, chksum_len, acc);
+}
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+/**
+ * Calculates the checksum with IPv6 pseudo header used by TCP and UDP for a pbuf chain.
+ * IPv6 addresses are expected to be in network byte order. Will only compute for a
+ * portion of the payload.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param proto ipv6 protocol/next header (used for checksum of pseudo header)
+ * @param proto_len length of the ipv6 payload (used for checksum of pseudo header)
+ * @param chksum_len number of payload bytes used to compute chksum
+ * @param src source ipv6 address (used for checksum of pseudo header)
+ * @param dest destination ipv6 address (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+                          u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest)
+{
+  u32_t acc = 0;
+  u32_t addr;
+  u8_t addr_part;
+
+  for (addr_part = 0; addr_part < 4; addr_part++) {
+    addr = src->addr[addr_part];
+    acc = (u32_t)(acc + (addr & 0xffffUL));
+    acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+    addr = dest->addr[addr_part];
+    acc = (u32_t)(acc + (addr & 0xffffUL));
+    acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL));
+  }
+  /* fold down to 16 bits */
+  acc = FOLD_U32T(acc);
+  acc = FOLD_U32T(acc);
+
+  return inet_cksum_pseudo_partial_base(p, proto, proto_len, chksum_len, acc);
+}
+#endif /* LWIP_IPV6 */
+
+/* ip_chksum_pseudo_partial:
+ *
+ * Calculates the IPv4 or IPv6 pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ *
+ * @param p chain of pbufs over that a checksum should be calculated (ip data part)
+ * @param src source ip address (used for checksum of pseudo header)
+ * @param dst destination ip address (used for checksum of pseudo header)
+ * @param proto ip protocol (used for checksum of pseudo header)
+ * @param proto_len length of the ip data part (used for checksum of pseudo header)
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+                         u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest)
+{
+#if LWIP_IPV6
+  if (IP_IS_V6(dest)) {
+    return ip6_chksum_pseudo_partial(p, proto, proto_len, chksum_len, ip_2_ip6(src), ip_2_ip6(dest));
+  }
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4 && LWIP_IPV6
+  else
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#if LWIP_IPV4
+  {
+    return inet_chksum_pseudo_partial(p, proto, proto_len, chksum_len, ip_2_ip4(src), ip_2_ip4(dest));
+  }
+#endif /* LWIP_IPV4 */
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarily for IP
+ * and ICMP.
+ *
+ * @param dataptr start of the buffer to calculate the checksum (no alignment needed)
+ * @param len length of the buffer to calculate the checksum
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+
+u16_t
+inet_chksum(const void *dataptr, u16_t len)
+{
+  return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len);
+}
+
+/**
+ * Calculate a checksum over a chain of pbufs (without pseudo-header, much like
+ * inet_chksum only pbufs are used).
+ *
+ * @param p pbuf chain over that the checksum should be calculated
+ * @return checksum (as u16_t) to be saved directly in the protocol header
+ */
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  int swapped = 0;
+
+  acc = 0;
+  for (q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    acc = FOLD_U32T(acc);
+    if (q->len % 2 != 0) {
+      swapped = !swapped;
+      acc = SWAP_BYTES_IN_WORD(acc);
+    }
+  }
+
+  if (swapped) {
+    acc = SWAP_BYTES_IN_WORD(acc);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* These are some implementations for LWIP_CHKSUM_COPY, which copies data
+ * like MEMCPY but generates a checksum at the same time. Since this is a
+ * performance-sensitive function, you might want to create your own version
+ * in assembly targeted at your hardware by defining it in lwipopts.h:
+ *   #define LWIP_CHKSUM_COPY(dst, src, len) your_chksum_copy(dst, src, len)
+ */
+
+#if (LWIP_CHKSUM_COPY_ALGORITHM == 1) /* Version #1 */
+/** Safe but slow: first call MEMCPY, then call LWIP_CHKSUM.
+ * For architectures with big caches, data might still be in cache when
+ * generating the checksum after copying.
+ */
+u16_t
+lwip_chksum_copy(void *dst, const void *src, u16_t len)
+{
+  MEMCPY(dst, src, len);
+  return LWIP_CHKSUM(dst, len);
+}
+#endif /* (LWIP_CHKSUM_COPY_ALGORITHM == 1) */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/init.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/init.c
new file mode 100644
index 000000000..b3737a356
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/init.c
@@ -0,0 +1,380 @@
+/**
+ * @file
+ * Modules initialization
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/init.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/sockets.h"
+#include "lwip/ip.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "lwip/timeouts.h"
+#include "lwip/etharp.h"
+#include "lwip/ip6.h"
+#include "lwip/nd6.h"
+#include "lwip/mld6.h"
+#include "lwip/api.h"
+
+#include "netif/ppp/ppp_opts.h"
+#include "netif/ppp/ppp_impl.h"
+
+#ifndef LWIP_SKIP_PACKING_CHECK
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct packed_struct_test {
+  PACK_STRUCT_FLD_8(u8_t  dummy1);
+  PACK_STRUCT_FIELD(u32_t dummy2);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define PACKED_STRUCT_TEST_EXPECTED_SIZE 5
+
+#endif
+
+/* Compile-time sanity checks for configuration errors.
+ * These can be done independently of LWIP_DEBUG, without penalty.
+ */
+#ifndef BYTE_ORDER
+#error "BYTE_ORDER is not defined, you have to define it in your cc.h"
+#endif
+#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV)
+#error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_UDPLITE)
+#error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DHCP)
+#error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && !LWIP_RAW && LWIP_MULTICAST_TX_OPTIONS)
+#error "If you want to use LWIP_MULTICAST_TX_OPTIONS, you have to define LWIP_UDP=1 and/or LWIP_RAW=1 in your lwipopts.h"
+#endif
+#if (!LWIP_UDP && LWIP_DNS)
+#error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h"
+#endif
+#if !MEMP_MEM_MALLOC /* MEMP_NUM_* checks are disabled when not using the pool allocator */
+#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0))
+#error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h"
+#endif
+#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0))
+#error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0))
+#error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0))
+#error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h"
+#endif
+#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1))
+#error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h"
+#endif
+#if (LWIP_IGMP && !LWIP_MULTICAST_TX_OPTIONS)
+#error "If you want to use IGMP, you have to define LWIP_MULTICAST_TX_OPTIONS==1 in your lwipopts.h"
+#endif
+#if (LWIP_IGMP && !LWIP_IPV4)
+#error "IGMP needs LWIP_IPV4 enabled in your lwipopts.h"
+#endif
+#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0))
+#error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h"
+#endif
+/* There must be sufficient timeouts, taking into account requirements of the subsystems. */
+#if LWIP_TIMERS && (MEMP_NUM_SYS_TIMEOUT < LWIP_NUM_SYS_TIMEOUT_INTERNAL)
+#error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts"
+#endif
+#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS))
+#error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!"
+#endif
+#endif /* !MEMP_MEM_MALLOC */
+#if LWIP_WND_SCALE
+#if (LWIP_TCP && (TCP_WND > 0xffffffff))
+#error "If you want to use TCP, TCP_WND must fit in an u32_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_RCV_SCALE > 14))
+#error "The maximum valid window scale value is 14!"
+#endif
+#if (LWIP_TCP && (TCP_WND > (0xFFFFU << TCP_RCV_SCALE)))
+#error "TCP_WND is bigger than the configured LWIP_WND_SCALE allows!"
+#endif
+#if (LWIP_TCP && ((TCP_WND >> TCP_RCV_SCALE) == 0))
+#error "TCP_WND is too small for the configured LWIP_WND_SCALE (results in zero window)!"
+#endif
+#else /* LWIP_WND_SCALE */
+#if (LWIP_TCP && (TCP_WND > 0xffff))
+#error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h (or enable window scaling)"
+#endif
+#endif /* LWIP_WND_SCALE */
+#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff))
+#error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h"
+#endif
+#if (LWIP_TCP && (TCP_SND_QUEUELEN < 2))
+#error "TCP_SND_QUEUELEN must be at least 2 for no-copy TCP writes to work"
+#endif
+#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12)))
+#error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h"
+#endif
+#if (LWIP_TCP && TCP_LISTEN_BACKLOG && ((TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff)))
+#error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t"
+#endif
+#if (LWIP_TCP && LWIP_TCP_SACK_OUT && !TCP_QUEUE_OOSEQ)
+#error "To use LWIP_TCP_SACK_OUT, TCP_QUEUE_OOSEQ needs to be enabled"
+#endif
+#if (LWIP_TCP && LWIP_TCP_SACK_OUT && (LWIP_TCP_MAX_SACK_NUM < 1))
+#error "LWIP_TCP_MAX_SACK_NUM must be greater than 0"
+#endif
+#if (LWIP_NETIF_API && (NO_SYS==1))
+#error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1))
+#error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if (LWIP_PPP_API && (NO_SYS==1))
+#error "If you want to use PPP API, you have to define NO_SYS=0 in your lwipopts.h"
+#endif
+#if (LWIP_PPP_API && (PPP_SUPPORT==0))
+#error "If you want to use PPP API, you have to enable PPP_SUPPORT in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP)
+#error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h"
+#endif
+#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK)
+#error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (!LWIP_ARP && LWIP_AUTOIP)
+#error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h"
+#endif
+#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API)))
+#error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h"
+#endif
+#if (LWIP_ALTCP && LWIP_EVENT_API)
+#error "The application layered tcp API does not work with LWIP_EVENT_API"
+#endif
+#if (MEM_LIBC_MALLOC && MEM_USE_POOLS)
+#error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h"
+#endif
+#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS)
+#error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h"
+#endif
+#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT)
+#error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf"
+#endif
+#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT)))
+#error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST"
+#endif
+#if PPP_SUPPORT && !PPPOS_SUPPORT && !PPPOE_SUPPORT && !PPPOL2TP_SUPPORT
+#error "PPP_SUPPORT needs at least one of PPPOS_SUPPORT, PPPOE_SUPPORT or PPPOL2TP_SUPPORT turned on"
+#endif
+#if PPP_SUPPORT && !PPP_IPV4_SUPPORT && !PPP_IPV6_SUPPORT
+#error "PPP_SUPPORT needs PPP_IPV4_SUPPORT and/or PPP_IPV6_SUPPORT turned on"
+#endif
+#if PPP_SUPPORT && PPP_IPV4_SUPPORT && !LWIP_IPV4
+#error "PPP_IPV4_SUPPORT needs LWIP_IPV4 turned on"
+#endif
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT && !LWIP_IPV6
+#error "PPP_IPV6_SUPPORT needs LWIP_IPV6 turned on"
+#endif
+#if !LWIP_ETHERNET && (LWIP_ARP || PPPOE_SUPPORT)
+#error "LWIP_ETHERNET needs to be turned on for LWIP_ARP or PPPOE_SUPPORT"
+#endif
+#if LWIP_TCPIP_CORE_LOCKING_INPUT && !LWIP_TCPIP_CORE_LOCKING
+#error "When using LWIP_TCPIP_CORE_LOCKING_INPUT, LWIP_TCPIP_CORE_LOCKING must be enabled, too"
+#endif
+#if LWIP_TCP && LWIP_NETIF_TX_SINGLE_PBUF && !TCP_OVERSIZE
+#error "LWIP_NETIF_TX_SINGLE_PBUF needs TCP_OVERSIZE enabled to create single-pbuf TCP packets"
+#endif
+#if LWIP_NETCONN && LWIP_TCP
+#if NETCONN_COPY != TCP_WRITE_FLAG_COPY
+#error "NETCONN_COPY != TCP_WRITE_FLAG_COPY"
+#endif
+#if NETCONN_MORE != TCP_WRITE_FLAG_MORE
+#error "NETCONN_MORE != TCP_WRITE_FLAG_MORE"
+#endif
+#endif /* LWIP_NETCONN && LWIP_TCP */
+#if LWIP_SOCKET
+#endif /* LWIP_SOCKET */
+
+
+/* Compile-time checks for deprecated options.
+ */
+#ifdef MEMP_NUM_TCPIP_MSG
+#error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef TCP_REXMIT_DEBUG
+#error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef RAW_STATS
+#error "RAW_STATS option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_QUEUE_FIRST
+#error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h."
+#endif
+#ifdef ETHARP_ALWAYS_INSERT
+#error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h."
+#endif
+#if !NO_SYS && LWIP_TCPIP_CORE_LOCKING && LWIP_COMPAT_MUTEX && !defined(LWIP_COMPAT_MUTEX_ALLOWED)
+#error "LWIP_COMPAT_MUTEX cannot prevent priority inversion. It is recommended to implement priority-aware mutexes. (Define LWIP_COMPAT_MUTEX_ALLOWED to disable this error.)"
+#endif
+
+#ifndef LWIP_DISABLE_TCP_SANITY_CHECKS
+#define LWIP_DISABLE_TCP_SANITY_CHECKS  0
+#endif
+#ifndef LWIP_DISABLE_MEMP_SANITY_CHECKS
+#define LWIP_DISABLE_MEMP_SANITY_CHECKS 0
+#endif
+
+/* MEMP sanity checks */
+#if MEMP_MEM_MALLOC
+#if !LWIP_DISABLE_MEMP_SANITY_CHECKS
+#if LWIP_NETCONN || LWIP_SOCKET
+#if !MEMP_NUM_NETCONN && LWIP_SOCKET
+#error "lwip_sanity_check: WARNING: MEMP_NUM_NETCONN cannot be 0 when using sockets!"
+#endif
+#else /* MEMP_MEM_MALLOC */
+#if MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB)
+#error "lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN. If you know what you are doing, define LWIP_DISABLE_MEMP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+#endif /* !LWIP_DISABLE_MEMP_SANITY_CHECKS */
+#if MEM_USE_POOLS
+#error "MEMP_MEM_MALLOC and MEM_USE_POOLS cannot be enabled at the same time"
+#endif
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+#error "LWIP_HOOK_MEMP_AVAILABLE doesn't make sense with MEMP_MEM_MALLOC"
+#endif
+#endif /* MEMP_MEM_MALLOC */
+
+/* TCP sanity checks */
+#if !LWIP_DISABLE_TCP_SANITY_CHECKS
+#if LWIP_TCP
+#if !MEMP_MEM_MALLOC && (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN)
+#error "lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if TCP_SND_BUF < (2 * TCP_MSS)
+#error "lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF / TCP_MSS))
+#error "lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if TCP_SNDLOWAT >= TCP_SND_BUF
+#error "lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than TCP_SND_BUF. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if TCP_SNDLOWAT >= (0xFFFF - (4 * TCP_MSS))
+#error "lwip_sanity_check: WARNING: TCP_SNDLOWAT must at least be 4*MSS below u16_t overflow!"
+#endif
+#if TCP_SNDQUEUELOWAT >= TCP_SND_QUEUELEN
+#error "lwip_sanity_check: WARNING: TCP_SNDQUEUELOWAT must be less than TCP_SND_QUEUELEN. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if !MEMP_MEM_MALLOC && PBUF_POOL_SIZE && (PBUF_POOL_BUFSIZE <= (PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN))
+#error "lwip_sanity_check: WARNING: PBUF_POOL_BUFSIZE does not provide enough space for protocol headers. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if !MEMP_MEM_MALLOC && PBUF_POOL_SIZE && (TCP_WND > (PBUF_POOL_SIZE * (PBUF_POOL_BUFSIZE - (PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN))))
+#error "lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE * (PBUF_POOL_BUFSIZE - protocol headers). If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#if TCP_WND < TCP_MSS
+#error "lwip_sanity_check: WARNING: TCP_WND is smaller than MSS. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error."
+#endif
+#endif /* LWIP_TCP */
+#endif /* !LWIP_DISABLE_TCP_SANITY_CHECKS */
+
+/**
+ * @ingroup lwip_nosys
+ * Initialize all modules.
+ * Use this in NO_SYS mode. Use tcpip_init() otherwise.
+ */
+void
+lwip_init(void)
+{
+#ifndef LWIP_SKIP_CONST_CHECK
+  int a = 0;
+  LWIP_UNUSED_ARG(a);
+  LWIP_ASSERT("LWIP_CONST_CAST not implemented correctly. Check your lwIP port.", LWIP_CONST_CAST(void *, &a) == &a);
+#endif
+#ifndef LWIP_SKIP_PACKING_CHECK
+  LWIP_ASSERT("Struct packing not implemented correctly. Check your lwIP port.", sizeof(struct packed_struct_test) == PACKED_STRUCT_TEST_EXPECTED_SIZE);
+#endif
+
+  /* Modules initialization */
+  stats_init();
+#if !NO_SYS
+  sys_init();
+#endif /* !NO_SYS */
+  mem_init();
+  memp_init();
+  pbuf_init();
+  netif_init();
+#if LWIP_IPV4
+  ip_init();
+#if LWIP_ARP
+  etharp_init();
+#endif /* LWIP_ARP */
+#endif /* LWIP_IPV4 */
+#if LWIP_RAW
+  raw_init();
+#endif /* LWIP_RAW */
+#if LWIP_UDP
+  udp_init();
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  tcp_init();
+#endif /* LWIP_TCP */
+#if LWIP_IGMP
+  igmp_init();
+#endif /* LWIP_IGMP */
+#if LWIP_DNS
+  dns_init();
+#endif /* LWIP_DNS */
+#if PPP_SUPPORT
+  ppp_init();
+#endif
+
+#if LWIP_TIMERS
+  sys_timeouts_init();
+#endif /* LWIP_TIMERS */
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ip.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ip.c
new file mode 100644
index 000000000..18514cf32
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ip.c
@@ -0,0 +1,167 @@
+/**
+ * @file
+ * Common IPv4 and IPv6 code
+ *
+ * @defgroup ip IP
+ * @ingroup callbackstyle_api
+ *
+ * @defgroup ip4 IPv4
+ * @ingroup ip
+ *
+ * @defgroup ip6 IPv6
+ * @ingroup ip
+ *
+ * @defgroup ipaddr IP address handling
+ * @ingroup infrastructure
+ *
+ * @defgroup ip4addr IPv4 only
+ * @ingroup ipaddr
+ *
+ * @defgroup ip6addr IPv6 only
+ * @ingroup ipaddr
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 || LWIP_IPV6
+
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+/** Global data for both IPv4 and IPv6 */
+struct ip_globals ip_data;
+
+#if LWIP_IPV4 && LWIP_IPV6
+
+const ip_addr_t ip_addr_any_type = IPADDR_ANY_TYPE_INIT;
+
+/**
+ * @ingroup ipaddr
+ * Convert numeric IP address (both versions) into ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ *
+ * @param addr ip address in network order to convert
+ * @return pointer to a global static (!) buffer that holds the ASCII
+ *         representation of addr
+ */
+char *ipaddr_ntoa(const ip_addr_t *addr)
+{
+  if (addr == NULL) {
+    return NULL;
+  }
+  if (IP_IS_V6(addr)) {
+    return ip6addr_ntoa(ip_2_ip6(addr));
+  } else {
+    return ip4addr_ntoa(ip_2_ip4(addr));
+  }
+}
+
+/**
+ * @ingroup ipaddr
+ * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used.
+ *
+ * @param addr ip address in network order to convert
+ * @param buf target buffer where the string is stored
+ * @param buflen length of buf
+ * @return either pointer to buf which now holds the ASCII
+ *         representation of addr or NULL if buf was too small
+ */
+char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen)
+{
+  if (addr == NULL) {
+    return NULL;
+  }
+  if (IP_IS_V6(addr)) {
+    return ip6addr_ntoa_r(ip_2_ip6(addr), buf, buflen);
+  } else {
+    return ip4addr_ntoa_r(ip_2_ip4(addr), buf, buflen);
+  }
+}
+
+/**
+ * @ingroup ipaddr
+ * Convert IP address string (both versions) to numeric.
+ * The version is auto-detected from the string.
+ *
+ * @param cp IP address string to convert
+ * @param addr conversion result is stored here
+ * @return 1 on success, 0 on error
+ */
+int
+ipaddr_aton(const char *cp, ip_addr_t *addr)
+{
+  if (cp != NULL) {
+    const char *c;
+    for (c = cp; *c != 0; c++) {
+      if (*c == ':') {
+        /* contains a colon: IPv6 address */
+        if (addr) {
+          IP_SET_TYPE_VAL(*addr, IPADDR_TYPE_V6);
+        }
+        return ip6addr_aton(cp, ip_2_ip6(addr));
+      } else if (*c == '.') {
+        /* contains a dot: IPv4 address */
+        break;
+      }
+    }
+    /* call ip4addr_aton as fallback or if IPv4 was found */
+    if (addr) {
+      IP_SET_TYPE_VAL(*addr, IPADDR_TYPE_V4);
+    }
+    return ip4addr_aton(cp, ip_2_ip4(addr));
+  }
+  return 0;
+}
+
+/**
+ * @ingroup lwip_nosys
+ * If both IP versions are enabled, this function can dispatch packets to the correct one.
+ * Don't call directly, pass to netif_add() and call netif->input().
+ */
+err_t
+ip_input(struct pbuf *p, struct netif *inp)
+{
+  if (p != NULL) {
+    if (IP_HDR_GET_VERSION(p->payload) == 6) {
+      return ip6_input(p, inp);
+    }
+    return ip4_input(p, inp);
+  }
+  return ERR_VAL;
+}
+
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#endif /* LWIP_IPV4 || LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/autoip.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/autoip.c
new file mode 100644
index 000000000..9f7139bc6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/autoip.c
@@ -0,0 +1,527 @@
+/**
+ * @file
+ * AutoIP Automatic LinkLocal IP Configuration
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ * @defgroup autoip AUTOIP
+ * @ingroup ip4
+ * AUTOIP related functions
+ * USAGE:
+ *
+ * define @ref LWIP_AUTOIP 1 in your lwipopts.h
+ * Options:
+ * AUTOIP_TMR_INTERVAL msecs,
+ *   I recommend a value of 100. The value must divide 1000 with a remainder almost 0.
+ *   Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 ....
+ *
+ * Without DHCP:
+ * - Call autoip_start() after netif_add().
+ *
+ * With DHCP:
+ * - define @ref LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h.
+ * - Configure your DHCP Client.
+ *
+ * @see netifapi_autoip
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies <kontakt@dspies.de>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/mem.h"
+/* #include "lwip/udp.h" */
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/autoip.h"
+#include "lwip/etharp.h"
+#include "lwip/prot/autoip.h"
+
+#include <string.h>
+
+/** Pseudo random macro based on netif informations.
+ * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */
+#ifndef LWIP_AUTOIP_RAND
+#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \
+                                   ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \
+                                   ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \
+                                   ((u32_t)((netif->hwaddr[4]) & 0xff))) + \
+                                   (netif_autoip_data(netif)? netif_autoip_data(netif)->tried_llipaddr : 0))
+#endif /* LWIP_AUTOIP_RAND */
+
+/**
+ * Macro that generates the initial IP address to be tried by AUTOIP.
+ * If you want to override this, define it to something else in lwipopts.h.
+ */
+#ifndef LWIP_AUTOIP_CREATE_SEED_ADDR
+#define LWIP_AUTOIP_CREATE_SEED_ADDR(netif) \
+  lwip_htonl(AUTOIP_RANGE_START + ((u32_t)(((u8_t)(netif->hwaddr[4])) | \
+                 ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8)))
+#endif /* LWIP_AUTOIP_CREATE_SEED_ADDR */
+
+/* static functions */
+static err_t autoip_arp_announce(struct netif *netif);
+static void autoip_start_probing(struct netif *netif);
+
+/**
+ * @ingroup autoip
+ * Set a statically allocated struct autoip to work with.
+ * Using this prevents autoip_start to allocate it using mem_malloc.
+ *
+ * @param netif the netif for which to set the struct autoip
+ * @param autoip (uninitialised) autoip struct allocated by the application
+ */
+void
+autoip_set_struct(struct netif *netif, struct autoip *autoip)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("autoip != NULL", autoip != NULL);
+  LWIP_ASSERT("netif already has a struct autoip set",
+              netif_autoip_data(netif) == NULL);
+
+  /* clear data structure */
+  memset(autoip, 0, sizeof(struct autoip));
+  /* autoip->state = AUTOIP_STATE_OFF; */
+  netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP, autoip);
+}
+
+/** Restart AutoIP client and check the next address (conflict detected)
+ *
+ * @param netif The netif under AutoIP control
+ */
+static void
+autoip_restart(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+  autoip->tried_llipaddr++;
+  autoip_start(netif);
+}
+
+/**
+ * Handle a IP address conflict after an ARP conflict detection
+ */
+static void
+autoip_handle_arp_conflict(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+
+  /* RFC3927, 2.5 "Conflict Detection and Defense" allows two options where
+     a) means retreat on the first conflict and
+     b) allows to keep an already configured address when having only one
+        conflict in 10 seconds
+     We use option b) since it helps to improve the chance that one of the two
+     conflicting hosts may be able to retain its address. */
+
+  if (autoip->lastconflict > 0) {
+    /* retreat, there was a conflicting ARP in the last DEFEND_INTERVAL seconds */
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n"));
+
+    /* Active TCP sessions are aborted when removing the ip addresss */
+    autoip_restart(netif);
+  } else {
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n"));
+    autoip_arp_announce(netif);
+    autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+  }
+}
+
+/**
+ * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+ *
+ * @param netif network interface on which create the IP-Address
+ * @param ipaddr ip address to initialize
+ */
+static void
+autoip_create_addr(struct netif *netif, ip4_addr_t *ipaddr)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+
+  /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255
+   * compliant to RFC 3927 Section 2.1
+   * We have 254 * 256 possibilities */
+
+  u32_t addr = lwip_ntohl(LWIP_AUTOIP_CREATE_SEED_ADDR(netif));
+  addr += autoip->tried_llipaddr;
+  addr = AUTOIP_NET | (addr & 0xffff);
+  /* Now, 169.254.0.0 <= addr <= 169.254.255.255 */
+
+  if (addr < AUTOIP_RANGE_START) {
+    addr += AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1;
+  }
+  if (addr > AUTOIP_RANGE_END) {
+    addr -= AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1;
+  }
+  LWIP_ASSERT("AUTOIP address not in range", (addr >= AUTOIP_RANGE_START) &&
+              (addr <= AUTOIP_RANGE_END));
+  ip4_addr_set_u32(ipaddr, lwip_htonl(addr));
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("autoip_create_addr(): tried_llipaddr=%"U16_F", %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+               (u16_t)(autoip->tried_llipaddr), ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr),
+               ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr)));
+}
+
+/**
+ * Sends an ARP probe from a network interface
+ *
+ * @param netif network interface used to send the probe
+ */
+static err_t
+autoip_arp_probe(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+  /* this works because netif->ip_addr is ANY */
+  return etharp_request(netif, &autoip->llipaddr);
+}
+
+/**
+ * Sends an ARP announce from a network interface
+ *
+ * @param netif network interface used to send the announce
+ */
+static err_t
+autoip_arp_announce(struct netif *netif)
+{
+  return etharp_gratuitous(netif);
+}
+
+/**
+ * Configure interface for use with current LL IP-Address
+ *
+ * @param netif network interface to configure with current LL IP-Address
+ */
+static err_t
+autoip_bind(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+  ip4_addr_t sn_mask, gw_addr;
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+              ("autoip_bind(netif=%p) %c%c%"U16_F" %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+               (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num,
+               ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr),
+               ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr)));
+
+  IP4_ADDR(&sn_mask, 255, 255, 0, 0);
+  IP4_ADDR(&gw_addr, 0, 0, 0, 0);
+
+  netif_set_addr(netif, &autoip->llipaddr, &sn_mask, &gw_addr);
+  /* interface is used by routing now that an address is set */
+
+  return ERR_OK;
+}
+
+/**
+ * @ingroup autoip
+ * Start AutoIP client
+ *
+ * @param netif network interface on which start the AutoIP client
+ */
+err_t
+autoip_start(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+  err_t result = ERR_OK;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
+
+  /* Set IP-Address, Netmask and Gateway to 0 to make sure that
+   * ARP Packets are formed correctly
+   */
+  netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0],
+               netif->name[1], (u16_t)netif->num));
+  if (autoip == NULL) {
+    /* no AutoIP client attached yet? */
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                ("autoip_start(): starting new AUTOIP client\n"));
+    autoip = (struct autoip *)mem_calloc(1, sizeof(struct autoip));
+    if (autoip == NULL) {
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                  ("autoip_start(): could not allocate autoip\n"));
+      return ERR_MEM;
+    }
+    /* store this AutoIP client in the netif */
+    netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP, autoip);
+    LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip"));
+  } else {
+    autoip->state = AUTOIP_STATE_OFF;
+    autoip->ttw = 0;
+    autoip->sent_num = 0;
+    ip4_addr_set_zero(&autoip->llipaddr);
+    autoip->lastconflict = 0;
+  }
+
+  autoip_create_addr(netif, &(autoip->llipaddr));
+  autoip_start_probing(netif);
+
+  return result;
+}
+
+static void
+autoip_start_probing(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+
+  autoip->state = AUTOIP_STATE_PROBING;
+  autoip->sent_num = 0;
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+              ("autoip_start_probing(): changing state to PROBING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+               ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr),
+               ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr)));
+
+  /* time to wait to first probe, this is randomly
+   * chosen out of 0 to PROBE_WAIT seconds.
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND));
+
+  /*
+   * if we tried more then MAX_CONFLICTS we must limit our rate for
+   * acquiring and probing address
+   * compliant to RFC 3927 Section 2.2.1
+   */
+  if (autoip->tried_llipaddr > MAX_CONFLICTS) {
+    autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+  }
+}
+
+/**
+ * Handle a possible change in the network configuration.
+ *
+ * If there is an AutoIP address configured, take the interface down
+ * and begin probing with the same address.
+ */
+void
+autoip_network_changed(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+
+  if (autoip && (autoip->state != AUTOIP_STATE_OFF)) {
+    autoip_start_probing(netif);
+  }
+}
+
+/**
+ * @ingroup autoip
+ * Stop AutoIP client
+ *
+ * @param netif network interface on which stop the AutoIP client
+ */
+err_t
+autoip_stop(struct netif *netif)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+
+  LWIP_ASSERT_CORE_LOCKED();
+  if (autoip != NULL) {
+    autoip->state = AUTOIP_STATE_OFF;
+    if (ip4_addr_islinklocal(netif_ip4_addr(netif))) {
+      netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
+    }
+  }
+  return ERR_OK;
+}
+
+/**
+ * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds
+ */
+void
+autoip_tmr(void)
+{
+  struct netif *netif;
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    struct autoip *autoip = netif_autoip_data(netif);
+    /* only act on AutoIP configured interfaces */
+    if (autoip != NULL) {
+      if (autoip->lastconflict > 0) {
+        autoip->lastconflict--;
+      }
+
+      LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE,
+                  ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n",
+                   (u16_t)(autoip->state), autoip->ttw));
+
+      if (autoip->ttw > 0) {
+        autoip->ttw--;
+      }
+
+      switch (autoip->state) {
+        case AUTOIP_STATE_PROBING:
+          if (autoip->ttw == 0) {
+            if (autoip->sent_num >= PROBE_NUM) {
+              /* Switch to ANNOUNCING: now we can bind to an IP address and use it */
+              autoip->state = AUTOIP_STATE_ANNOUNCING;
+              autoip_bind(netif);
+              /* autoip_bind() calls netif_set_addr(): this triggers a gratuitous ARP
+                 which counts as an announcement */
+              autoip->sent_num = 1;
+              autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND;
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                          ("autoip_tmr(): changing state to ANNOUNCING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr),
+                           ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr)));
+            } else {
+              autoip_arp_probe(netif);
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_tmr() PROBING Sent Probe\n"));
+              autoip->sent_num++;
+              if (autoip->sent_num == PROBE_NUM) {
+                /* calculate time to wait to for announce */
+                autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND;
+              } else {
+                /* calculate time to wait to next probe */
+                autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) %
+                                       ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) +
+                                      PROBE_MIN * AUTOIP_TICKS_PER_SECOND);
+              }
+            }
+          }
+          break;
+
+        case AUTOIP_STATE_ANNOUNCING:
+          if (autoip->ttw == 0) {
+            autoip_arp_announce(netif);
+            LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_tmr() ANNOUNCING Sent Announce\n"));
+            autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND;
+            autoip->sent_num++;
+
+            if (autoip->sent_num >= ANNOUNCE_NUM) {
+              autoip->state = AUTOIP_STATE_BOUND;
+              autoip->sent_num = 0;
+              autoip->ttw = 0;
+              LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                          ("autoip_tmr(): changing state to BOUND: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr),
+                           ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr)));
+            }
+          }
+          break;
+
+        default:
+          /* nothing to do in other states */
+          break;
+      }
+    }
+  }
+}
+
+/**
+ * Handles every incoming ARP Packet, called by etharp_input().
+ *
+ * @param netif network interface to use for autoip processing
+ * @param hdr Incoming ARP packet
+ */
+void
+autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+
+  LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_arp_reply()\n"));
+  if ((autoip != NULL) && (autoip->state != AUTOIP_STATE_OFF)) {
+    /* when ip.src == llipaddr && hw.src != netif->hwaddr
+     *
+     * when probing  ip.dst == llipaddr && hw.src != netif->hwaddr
+     * we have a conflict and must solve it
+     */
+    ip4_addr_t sipaddr, dipaddr;
+    struct eth_addr netifaddr;
+    SMEMCPY(netifaddr.addr, netif->hwaddr, ETH_HWADDR_LEN);
+
+    /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
+     * structure packing (not using structure copy which breaks strict-aliasing rules).
+     */
+    IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
+    IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
+
+    if (autoip->state == AUTOIP_STATE_PROBING) {
+      /* RFC 3927 Section 2.2.1:
+       * from beginning to after ANNOUNCE_WAIT
+       * seconds we have a conflict if
+       * ip.src == llipaddr OR
+       * ip.dst == llipaddr && hw.src != own hwaddr
+       */
+      if ((ip4_addr_cmp(&sipaddr, &autoip->llipaddr)) ||
+          (ip4_addr_isany_val(sipaddr) &&
+           ip4_addr_cmp(&dipaddr, &autoip->llipaddr) &&
+           !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+                    ("autoip_arp_reply(): Probe Conflict detected\n"));
+        autoip_restart(netif);
+      }
+    } else {
+      /* RFC 3927 Section 2.5:
+       * in any state we have a conflict if
+       * ip.src == llipaddr && hw.src != own hwaddr
+       */
+      if (ip4_addr_cmp(&sipaddr, &autoip->llipaddr) &&
+          !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) {
+        LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+                    ("autoip_arp_reply(): Conflicting ARP-Packet detected\n"));
+        autoip_handle_arp_conflict(netif);
+      }
+    }
+  }
+}
+
+/** check if AutoIP supplied netif->ip_addr
+ *
+ * @param netif the netif to check
+ * @return 1 if AutoIP supplied netif->ip_addr (state BOUND or ANNOUNCING),
+ *         0 otherwise
+ */
+u8_t
+autoip_supplied_address(const struct netif *netif)
+{
+  if ((netif != NULL) && (netif_autoip_data(netif) != NULL)) {
+    struct autoip *autoip = netif_autoip_data(netif);
+    return (autoip->state == AUTOIP_STATE_BOUND) || (autoip->state == AUTOIP_STATE_ANNOUNCING);
+  }
+  return 0;
+}
+
+u8_t
+autoip_accept_packet(struct netif *netif, const ip4_addr_t *addr)
+{
+  struct autoip *autoip = netif_autoip_data(netif);
+  return (autoip != NULL) && ip4_addr_cmp(addr, &(autoip->llipaddr));
+}
+
+#endif /* LWIP_IPV4 && LWIP_AUTOIP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/dhcp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/dhcp.c
new file mode 100644
index 000000000..0d3056434
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/dhcp.c
@@ -0,0 +1,1990 @@
+/**
+ * @file
+ * Dynamic Host Configuration Protocol client
+ *
+ * @defgroup dhcp4 DHCPv4
+ * @ingroup ip4
+ * DHCP (IPv4) related functions
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * @todo:
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Options:
+ * @ref DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * @ref DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * dhcp_start() starts a DHCP client instance which
+ * configures the interface by obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release() to end the lease and use dhcp_stop()
+ * to remove the DHCP client.
+ *
+ * @see LWIP_HOOK_DHCP_APPEND_OPTIONS
+ * @see LWIP_HOOK_DHCP_PARSE_OPTION
+ *
+ * @see netifapi_dhcp4
+ */
+
+/*
+ * Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg <leon.woestenberg@gmx.net>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/def.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/dns.h"
+#include "lwip/etharp.h"
+#include "lwip/prot/dhcp.h"
+#include "lwip/prot/iana.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+#ifndef LWIP_HOOK_DHCP_APPEND_OPTIONS
+#define LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr)
+#endif
+#ifndef LWIP_HOOK_DHCP_PARSE_OPTION
+#define LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, offset) do { LWIP_UNUSED_ARG(msg); } while(0)
+#endif
+
+/** DHCP_CREATE_RAND_XID: if this is set to 1, the xid is created using
+ * LWIP_RAND() (this overrides DHCP_GLOBAL_XID)
+ */
+#ifndef DHCP_CREATE_RAND_XID
+#define DHCP_CREATE_RAND_XID        1
+#endif
+
+/** Default for DHCP_GLOBAL_XID is 0xABCD0000
+ * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g.
+ *  \#define DHCP_GLOBAL_XID_HEADER "stdlib.h"
+ *  \#define DHCP_GLOBAL_XID rand()
+ */
+#ifdef DHCP_GLOBAL_XID_HEADER
+#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */
+#endif
+
+/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU
+ * MTU is checked to be big enough in dhcp_start */
+#define DHCP_MAX_MSG_LEN(netif)        (netif->mtu)
+#define DHCP_MAX_MSG_LEN_MIN_REQUIRED  576
+/** Minimum length for reply before packet is parsed */
+#define DHCP_MIN_REPLY_LEN             44
+
+#define REBOOT_TRIES                2
+
+#if LWIP_DNS && LWIP_DHCP_MAX_DNS_SERVERS
+#if DNS_MAX_SERVERS > LWIP_DHCP_MAX_DNS_SERVERS
+#define LWIP_DHCP_PROVIDE_DNS_SERVERS LWIP_DHCP_MAX_DNS_SERVERS
+#else
+#define LWIP_DHCP_PROVIDE_DNS_SERVERS DNS_MAX_SERVERS
+#endif
+#else
+#define LWIP_DHCP_PROVIDE_DNS_SERVERS 0
+#endif
+
+/** Option handling: options are parsed in dhcp_parse_reply
+ * and saved in an array where other functions can load them from.
+ * This might be moved into the struct dhcp (not necessarily since
+ * lwIP is single-threaded and the array is only used while in recv
+ * callback). */
+enum dhcp_option_idx {
+  DHCP_OPTION_IDX_OVERLOAD = 0,
+  DHCP_OPTION_IDX_MSG_TYPE,
+  DHCP_OPTION_IDX_SERVER_ID,
+  DHCP_OPTION_IDX_LEASE_TIME,
+  DHCP_OPTION_IDX_T1,
+  DHCP_OPTION_IDX_T2,
+  DHCP_OPTION_IDX_SUBNET_MASK,
+  DHCP_OPTION_IDX_ROUTER,
+#if LWIP_DHCP_PROVIDE_DNS_SERVERS
+  DHCP_OPTION_IDX_DNS_SERVER,
+  DHCP_OPTION_IDX_DNS_SERVER_LAST = DHCP_OPTION_IDX_DNS_SERVER + LWIP_DHCP_PROVIDE_DNS_SERVERS - 1,
+#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
+#if LWIP_DHCP_GET_NTP_SRV
+  DHCP_OPTION_IDX_NTP_SERVER,
+  DHCP_OPTION_IDX_NTP_SERVER_LAST = DHCP_OPTION_IDX_NTP_SERVER + LWIP_DHCP_MAX_NTP_SERVERS - 1,
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+  DHCP_OPTION_IDX_MAX
+};
+
+/** Holds the decoded option values, only valid while in dhcp_recv.
+    @todo: move this into struct dhcp? */
+u32_t dhcp_rx_options_val[DHCP_OPTION_IDX_MAX];
+/** Holds a flag which option was received and is contained in dhcp_rx_options_val,
+    only valid while in dhcp_recv.
+    @todo: move this into struct dhcp? */
+u8_t  dhcp_rx_options_given[DHCP_OPTION_IDX_MAX];
+
+static u8_t dhcp_discover_request_options[] = {
+  DHCP_OPTION_SUBNET_MASK,
+  DHCP_OPTION_ROUTER,
+  DHCP_OPTION_BROADCAST
+#if LWIP_DHCP_PROVIDE_DNS_SERVERS
+  , DHCP_OPTION_DNS_SERVER
+#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
+#if LWIP_DHCP_GET_NTP_SRV
+  , DHCP_OPTION_NTP
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+};
+
+#ifdef DHCP_GLOBAL_XID
+static u32_t xid;
+static u8_t xid_initialised;
+#endif /* DHCP_GLOBAL_XID */
+
+#define dhcp_option_given(dhcp, idx)          (dhcp_rx_options_given[idx] != 0)
+#define dhcp_got_option(dhcp, idx)            (dhcp_rx_options_given[idx] = 1)
+#define dhcp_clear_option(dhcp, idx)          (dhcp_rx_options_given[idx] = 0)
+#define dhcp_clear_all_options(dhcp)          (memset(dhcp_rx_options_given, 0, sizeof(dhcp_rx_options_given)))
+#define dhcp_get_option_value(dhcp, idx)      (dhcp_rx_options_val[idx])
+#define dhcp_set_option_value(dhcp, idx, val) (dhcp_rx_options_val[idx] = (val))
+
+static struct udp_pcb *dhcp_pcb;
+static u8_t dhcp_pcb_refcount;
+
+/* DHCP client state machine functions */
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+#if DHCP_DOES_ARP_CHECK
+static err_t dhcp_decline(struct netif *netif);
+#endif /* DHCP_DOES_ARP_CHECK */
+static err_t dhcp_rebind(struct netif *netif);
+static err_t dhcp_reboot(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
+
+/* receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port);
+
+/* set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/* build outgoing messages */
+/* create a DHCP message, fill in common headers */
+static struct pbuf *dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len);
+/* add a DHCP option (type, then length in bytes) */
+static u16_t dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len);
+/* add option values */
+static u16_t dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value);
+static u16_t dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value);
+static u16_t dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value);
+#if LWIP_NETIF_HOSTNAME
+static u16_t dhcp_option_hostname(u16_t options_out_len, u8_t *options, struct netif *netif);
+#endif /* LWIP_NETIF_HOSTNAME */
+/* always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out);
+
+/** Ensure DHCP PCB is allocated and bound */
+static err_t
+dhcp_inc_pcb_refcount(void)
+{
+  if (dhcp_pcb_refcount == 0) {
+    LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL);
+
+    /* allocate UDP PCB */
+    dhcp_pcb = udp_new();
+
+    if (dhcp_pcb == NULL) {
+      return ERR_MEM;
+    }
+
+    ip_set_option(dhcp_pcb, SOF_BROADCAST);
+
+    /* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */
+    udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT);
+    udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER);
+    udp_recv(dhcp_pcb, dhcp_recv, NULL);
+  }
+
+  dhcp_pcb_refcount++;
+
+  return ERR_OK;
+}
+
+/** Free DHCP PCB if the last netif stops using it */
+static void
+dhcp_dec_pcb_refcount(void)
+{
+  LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0));
+  dhcp_pcb_refcount--;
+
+  if (dhcp_pcb_refcount == 0) {
+    udp_remove(dhcp_pcb);
+    dhcp_pcb = NULL;
+  }
+}
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We clear any existing set IP address and restart DHCP negotiation
+ * afresh (as per RFC2131 3.2.3).
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_nak(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
+              (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* Change to a defined state - set this before assigning the address
+     to ensure the callback can use dhcp_supplied_address() */
+  dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
+  /* remove IP address from interface (must no longer be used, as per RFC2131) */
+  netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
+  /* We can immediately restart discovery */
+  dhcp_discover(netif);
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
+              (s16_t)netif->name[1]));
+  dhcp_set_state(dhcp, DHCP_STATE_CHECKING);
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+  msecs = 500;
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
+}
+#endif /* DHCP_DOES_ARP_CHECK */
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
+              (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  /* obtain the server address */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
+    dhcp->request_timeout = 0; /* stop timer */
+
+    ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
+                ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
+    /* remember offered address */
+    ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
+                ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    dhcp_select(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif));
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t
+dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result;
+  u16_t msecs;
+  u8_t i;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;);
+  dhcp = netif_dhcp_data(netif);
+  LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  dhcp_set_state(dhcp, DHCP_STATE_REQUESTING);
+
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
+
+    /* MUST request the offered IP address */
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
+    options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
+    options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
+    for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
+      options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
+    }
+
+#if LWIP_NETIF_HOSTNAME
+    options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    /* send broadcast to any DHCP server */
+    result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
+    pbuf_free(p_out);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
+    result = ERR_MEM;
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+  msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ * Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS).
+ */
+void
+dhcp_coarse_tmr(void)
+{
+  struct netif *netif;
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  NETIF_FOREACH(netif) {
+    /* only act on DHCP configured interfaces */
+    struct dhcp *dhcp = netif_dhcp_data(netif);
+    if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) {
+      /* compare lease time to expire timeout */
+      if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n"));
+        /* this clients' lease time has expired */
+        dhcp_release_and_stop(netif);
+        dhcp_start(netif);
+        /* timer is active (non zero), and triggers (zeroes) now? */
+      } else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+        /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) {
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+  }
+}
+
+/**
+ * DHCP transaction timeout handling (this function must be called every 500ms,
+ * see @ref DHCP_FINE_TIMER_MSECS).
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ */
+void
+dhcp_fine_tmr(void)
+{
+  struct netif *netif;
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    struct dhcp *dhcp = netif_dhcp_data(netif);
+    /* only act on DHCP configured interfaces */
+    if (dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */
+      if (dhcp->request_timeout > 1) {
+        dhcp->request_timeout--;
+      } else if (dhcp->request_timeout == 1) {
+        dhcp->request_timeout--;
+        /* { dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this client's request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+    /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_STATE_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release_and_stop(netif);
+      dhcp_start(netif);
+    }
+#if DHCP_DOES_ARP_CHECK
+    /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_STATE_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+      /* no ARP replies on the offered address,
+         looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+#endif /* DHCP_DOES_ARP_CHECK */
+  } else if (dhcp->state == DHCP_STATE_REBOOTING) {
+    if (dhcp->tries < REBOOT_TRIES) {
+      dhcp_reboot(netif);
+    } else {
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
+      (dhcp->state == DHCP_STATE_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                ("dhcp_t1_timeout(): must renew\n"));
+    /* This slightly different to RFC2131: DHCPREQUEST will be sent from state
+       DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */
+    dhcp_renew(netif);
+    /* Calculate next timeout */
+    if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
+      dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2);
+    }
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
+      (dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                ("dhcp_t2_timeout(): must rebind\n"));
+    /* This slightly different to RFC2131: DHCPREQUEST will be sent from state
+       DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */
+    dhcp_rebind(netif);
+    /* Calculate next timeout */
+    if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
+      dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2);
+    }
+  }
+}
+
+/**
+ * Handle a DHCP ACK packet
+ *
+ * @param netif the netif under DHCP control
+ */
+static void
+dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+#if LWIP_DHCP_PROVIDE_DNS_SERVERS || LWIP_DHCP_GET_NTP_SRV
+  u8_t n;
+#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS || LWIP_DHCP_GET_NTP_SRV */
+#if LWIP_DHCP_GET_NTP_SRV
+  ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS];
+#endif
+
+  /* clear options we might not get from the ACK */
+  ip4_addr_set_zero(&dhcp->offered_sn_mask);
+  ip4_addr_set_zero(&dhcp->offered_gw_addr);
+#if LWIP_DHCP_BOOTP_FILE
+  ip4_addr_set_zero(&dhcp->offered_si_addr);
+#endif /* LWIP_DHCP_BOOTP_FILE */
+
+  /* lease time given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
+  }
+  /* renewal period given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
+  } else {
+    /* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/
+    dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U;
+  }
+
+  /* (y)our internet address */
+  ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
+
+#if LWIP_DHCP_BOOTP_FILE
+  /* copy boot server address,
+     boot file name copied in dhcp_parse_reply if not overloaded */
+  ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr);
+#endif /* LWIP_DHCP_BOOTP_FILE */
+
+  /* subnet mask given? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
+    /* remember given subnet mask */
+    ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
+    dhcp->subnet_mask_given = 1;
+  } else {
+    dhcp->subnet_mask_given = 0;
+  }
+
+  /* gateway router */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
+    ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
+  }
+
+#if LWIP_DHCP_GET_NTP_SRV
+  /* NTP servers */
+  for (n = 0; (n < LWIP_DHCP_MAX_NTP_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n); n++) {
+    ip4_addr_set_u32(&ntp_server_addrs[n], lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n)));
+  }
+  dhcp_set_ntp_servers(n, ntp_server_addrs);
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+
+#if LWIP_DHCP_PROVIDE_DNS_SERVERS
+  /* DNS servers */
+  for (n = 0; (n < LWIP_DHCP_PROVIDE_DNS_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n); n++) {
+    ip_addr_t dns_addr;
+    ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
+    dns_setserver(n, &dns_addr);
+  }
+#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
+}
+
+/**
+ * @ingroup dhcp4
+ * Set a statically allocated struct dhcp to work with.
+ * Using this prevents dhcp_start to allocate it using mem_malloc.
+ *
+ * @param netif the netif for which to set the struct dhcp
+ * @param dhcp (uninitialised) dhcp struct allocated by the application
+ */
+void
+dhcp_set_struct(struct netif *netif, struct dhcp *dhcp)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp != NULL", dhcp != NULL);
+  LWIP_ASSERT("netif already has a struct dhcp set", netif_dhcp_data(netif) == NULL);
+
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
+  netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp);
+}
+
+/**
+ * @ingroup dhcp4
+ * Removes a struct dhcp from a netif.
+ *
+ * ATTENTION: Only use this when not using dhcp_set_struct() to allocate the
+ *            struct dhcp since the memory is passed back to the heap.
+ *
+ * @param netif the netif from which to remove the struct dhcp
+ */
+void dhcp_cleanup(struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+
+  if (netif_dhcp_data(netif) != NULL) {
+    mem_free(netif_dhcp_data(netif));
+    netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL);
+  }
+}
+
+/**
+ * @ingroup dhcp4
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ */
+err_t
+dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
+  LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
+  dhcp = netif_dhcp_data(netif);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* check MTU of the netif */
+  if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
+    return ERR_MEM;
+  }
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n"));
+    dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    
+    /* store this dhcp client in the netif */
+    netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+    /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
+
+    if (dhcp->pcb_allocated != 0) {
+      dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
+    }
+    /* dhcp is cleared below, no need to reset flag*/
+  }
+
+  /* clear data structure */
+  memset(dhcp, 0, sizeof(struct dhcp));
+  /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+
+  if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */
+    return ERR_MEM;
+  }
+  dhcp->pcb_allocated = 1;
+
+  if (!netif_is_link_up(netif)) {
+    /* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */
+    dhcp_set_state(dhcp, DHCP_STATE_INIT);
+    return ERR_OK;
+  }
+
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_release_and_stop(netif);
+    return ERR_MEM;
+  }
+  return result;
+}
+
+/**
+ * @ingroup dhcp4
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ */
+void
+dhcp_inform(struct netif *netif)
+{
+  struct dhcp dhcp;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+
+  if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */
+    return;
+  }
+
+  memset(&dhcp, 0, sizeof(struct dhcp));
+  dhcp_set_state(&dhcp, DHCP_STATE_INFORMING);
+
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, &dhcp, DHCP_INFORM, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
+
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, &dhcp, DHCP_STATE_INFORMING, msg_out, DHCP_INFORM, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n"));
+
+    udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
+
+    pbuf_free(p_out);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  dhcp_dec_pcb_refcount(); /* delete DHCP PCB if not needed any more */
+}
+
+/** Handle a possible change in the network configuration.
+ *
+ * This enters the REBOOTING state to verify that the currently bound
+ * address is still valid.
+ */
+void
+dhcp_network_changed(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+
+  if (!dhcp) {
+    return;
+  }
+  switch (dhcp->state) {
+    case DHCP_STATE_REBINDING:
+    case DHCP_STATE_RENEWING:
+    case DHCP_STATE_BOUND:
+    case DHCP_STATE_REBOOTING:
+      dhcp->tries = 0;
+      dhcp_reboot(netif);
+      break;
+    case DHCP_STATE_OFF:
+      /* stay off */
+      break;
+    default:
+      LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF);
+      /* INIT/REQUESTING/CHECKING/BACKING_OFF restart with new 'rid' because the
+         state changes, SELECTING: continue with current 'rid' as we stay in the
+         same state */
+#if LWIP_DHCP_AUTOIP_COOP
+      if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+        autoip_stop(netif);
+        dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+      }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+      /* ensure we start with short timeouts, even if already discovering */
+      dhcp->tries = 0;
+      dhcp_discover(netif);
+      break;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address:
+ * check whether the offered IP address is not in use using ARP
+ *
+ * @param netif the network interface on which the reply was received
+ * @param addr The IP address we received a reply from
+ */
+void
+dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr)
+{
+  struct dhcp *dhcp;
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+  dhcp = netif_dhcp_data(netif);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
+  /* is a DHCP client doing an ARP check? */
+  if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
+                ip4_addr_get_u32(addr)));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
+                  ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  err_t result;
+  u16_t msecs;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
+    options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    /* per section 4.4.4, broadcast DECLINE messages */
+    result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
+    pbuf_free(p_out);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("dhcp_decline: could not allocate DHCP request\n"));
+    result = ERR_MEM;
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+  msecs = 10 * 1000;
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+#endif /* DHCP_DOES_ARP_CHECK */
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ * @param netif the netif under DHCP control
+ */
+static err_t
+dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  err_t result = ERR_OK;
+  u16_t msecs;
+  u8_t i;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
+
+  ip4_addr_set_any(&dhcp->offered_ip_addr);
+  dhcp_set_state(dhcp, DHCP_STATE_SELECTING);
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
+    for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
+      options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
+    }
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n"));
+    udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    pbuf_free(p_out);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+#if LWIP_DHCP_AUTOIP_COOP
+  if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
+    autoip_start(netif);
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+  msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void
+dhcp_bind(struct netif *netif)
+{
+  u32_t timeout;
+  struct dhcp *dhcp;
+  ip4_addr_t sn_mask, gw_addr;
+  LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
+  dhcp = netif_dhcp_data(netif);
+  LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* reset time used of lease */
+  dhcp->lease_used = 0;
+
+  if (dhcp->offered_t0_lease != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease));
+    timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t0_timeout = (u16_t)timeout;
+    if (dhcp->t0_timeout == 0) {
+      dhcp->t0_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000));
+  }
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
+    timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t1_timeout = (u16_t)timeout;
+    if (dhcp->t1_timeout == 0) {
+      dhcp->t1_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000));
+    dhcp->t1_renew_time = dhcp->t1_timeout;
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
+    timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (timeout > 0xffff) {
+      timeout = 0xffff;
+    }
+    dhcp->t2_timeout = (u16_t)timeout;
+    if (dhcp->t2_timeout == 0) {
+      dhcp->t2_timeout = 1;
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000));
+    dhcp->t2_rebind_time = dhcp->t2_timeout;
+  }
+
+  /* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */
+  if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) {
+    dhcp->t1_timeout = 0;
+  }
+
+  if (dhcp->subnet_mask_given) {
+    /* copy offered network mask */
+    ip4_addr_copy(sn_mask, dhcp->offered_sn_mask);
+  } else {
+    /* subnet mask not given, choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
+    if (first_octet <= 127) {
+      ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
+    } else if (first_octet >= 192) {
+      ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
+    } else {
+      ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
+    }
+  }
+
+  ip4_addr_copy(gw_addr, dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (ip4_addr_isany_val(gw_addr)) {
+    /* copy network address */
+    ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
+    /* use first host address on network as gateway */
+    ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
+  }
+
+#if LWIP_DHCP_AUTOIP_COOP
+  if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+    autoip_stop(netif);
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n",
+              ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr)));
+  /* netif is now bound to DHCP leased address - set this before assigning the address
+     to ensure the callback can use dhcp_supplied_address() */
+  dhcp_set_state(dhcp, DHCP_STATE_BOUND);
+
+  netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr);
+  /* interface is used by routing now that an address is set */
+}
+
+/**
+ * @ingroup dhcp4
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t
+dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  err_t result;
+  u16_t msecs;
+  u8_t i;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_STATE_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
+    for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
+      options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
+    }
+
+#if LWIP_NETIF_HOSTNAME
+    options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
+    pbuf_free(p_out);
+
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
+    result = ERR_MEM;
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000);
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t
+dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  err_t result;
+  u16_t msecs;
+  u8_t i;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_STATE_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
+    for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
+      options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
+    }
+
+#if LWIP_NETIF_HOSTNAME
+    options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    /* broadcast to server */
+    result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
+    pbuf_free(p_out);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
+    result = ERR_MEM;
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+  msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Enter REBOOTING state to verify an existing lease
+ *
+ * @param netif network interface which must reboot
+ */
+static err_t
+dhcp_reboot(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  err_t result;
+  u16_t msecs;
+  u8_t i;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
+  dhcp_set_state(dhcp, DHCP_STATE_REBOOTING);
+
+  /* create and initialize the DHCP message header */
+  p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
+  if (p_out != NULL) {
+    struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED);
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
+    options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
+
+    options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
+    for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
+      options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
+    }
+
+#if LWIP_NETIF_HOSTNAME
+    options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
+#endif /* LWIP_NETIF_HOSTNAME */
+
+    LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len);
+    dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+    /* broadcast to server */
+    result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
+    pbuf_free(p_out);
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
+    result = ERR_MEM;
+  }
+  if (dhcp->tries < 255) {
+    dhcp->tries++;
+  }
+  msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
+  dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * @ingroup dhcp4
+ * Release a DHCP lease and stop DHCP statemachine (and AUTOIP if LWIP_DHCP_AUTOIP_COOP).
+ *
+ * @param netif network interface
+ */
+void
+dhcp_release_and_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  ip_addr_t server_ip_addr;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n"));
+  if (dhcp == NULL) {
+    return;
+  }
+
+  /* already off? -> nothing to do */
+  if (dhcp->state == DHCP_STATE_OFF) {
+    return;
+  }
+
+  ip_addr_copy(server_ip_addr, dhcp->server_ip_addr);
+
+  /* clean old DHCP offer */
+  ip_addr_set_zero_ip4(&dhcp->server_ip_addr);
+  ip4_addr_set_zero(&dhcp->offered_ip_addr);
+  ip4_addr_set_zero(&dhcp->offered_sn_mask);
+  ip4_addr_set_zero(&dhcp->offered_gw_addr);
+#if LWIP_DHCP_BOOTP_FILE
+  ip4_addr_set_zero(&dhcp->offered_si_addr);
+#endif /* LWIP_DHCP_BOOTP_FILE */
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0;
+
+  /* send release message when current IP was assigned via DHCP */
+  if (dhcp_supplied_address(netif)) {
+    /* create and initialize the DHCP message header */
+    struct pbuf *p_out;
+    u16_t options_out_len;
+    p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len);
+    if (p_out != NULL) {
+      struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
+      options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
+      options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr))));
+
+      LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len);
+      dhcp_option_trailer(options_out_len, msg_out->options, p_out);
+
+      udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
+      pbuf_free(p_out);
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_STATE_OFF\n"));
+    } else {
+      /* sending release failed, but that's not a problem since the correct behaviour of dhcp does not rely on release */
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
+    }
+  }
+
+  /* remove IP address from interface (prevents routing from selecting this interface) */
+  netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
+
+#if LWIP_DHCP_AUTOIP_COOP
+  if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
+    autoip_stop(netif);
+    dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
+  }
+#endif /* LWIP_DHCP_AUTOIP_COOP */
+
+  dhcp_set_state(dhcp, DHCP_STATE_OFF);
+
+  if (dhcp->pcb_allocated != 0) {
+    dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
+    dhcp->pcb_allocated = 0;
+  }
+}
+
+/**
+ * @ingroup dhcp4
+ * This function calls dhcp_release_and_stop() internally.
+ * @deprecated Use dhcp_release_and_stop() instead.
+ */
+err_t
+dhcp_release(struct netif *netif)
+{
+  dhcp_release_and_stop(netif);
+  return ERR_OK;
+}
+
+/**
+ * @ingroup dhcp4
+ * This function calls dhcp_release_and_stop() internally.
+ * @deprecated Use dhcp_release_and_stop() instead.
+ */
+void
+dhcp_stop(struct netif *netif)
+{
+  dhcp_release_and_stop(netif);
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ */
+static void
+dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
+{
+  if (new_state != dhcp->state) {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+    dhcp->request_timeout = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static u16_t
+dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
+  options[options_out_len++] = option_type;
+  options[options_out_len++] = option_len;
+  return options_out_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static u16_t
+dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN);
+  options[options_out_len++] = value;
+  return options_out_len;
+}
+
+static u16_t
+dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN);
+  options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
+  options[options_out_len++] = (u8_t) (value & 0x00ffU);
+  return options_out_len;
+}
+
+static u16_t
+dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN);
+  options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
+  options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
+  options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
+  options[options_out_len++] = (u8_t)((value & 0x000000ffUL));
+  return options_out_len;
+}
+
+#if LWIP_NETIF_HOSTNAME
+static u16_t
+dhcp_option_hostname(u16_t options_out_len, u8_t *options, struct netif *netif)
+{
+  if (netif->hostname != NULL) {
+    size_t namelen = strlen(netif->hostname);
+    if (namelen > 0) {
+      size_t len;
+      const char *p = netif->hostname;
+      /* Shrink len to available bytes (need 2 bytes for OPTION_HOSTNAME
+         and 1 byte for trailer) */
+      size_t available = DHCP_OPTIONS_LEN - options_out_len - 3;
+      LWIP_ASSERT("DHCP: hostname is too long!", namelen <= available);
+      len = LWIP_MIN(namelen, available);
+      LWIP_ASSERT("DHCP: hostname is too long!", len <= 0xFF);
+      options_out_len = dhcp_option(options_out_len, options, DHCP_OPTION_HOSTNAME, (u8_t)len);
+      while (len--) {
+        options_out_len = dhcp_option_byte(options_out_len, options, *p++);
+      }
+    }
+  }
+  return options_out_len;
+}
+#endif /* LWIP_NETIF_HOSTNAME */
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a contiguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t
+dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp)
+{
+  u8_t *options;
+  u16_t offset;
+  u16_t offset_max;
+  u16_t options_idx;
+  u16_t options_idx_max;
+  struct pbuf *q;
+  int parse_file_as_options = 0;
+  int parse_sname_as_options = 0;
+  struct dhcp_msg *msg_in;
+#if LWIP_DHCP_BOOTP_FILE
+  int file_overloaded = 0;
+#endif
+
+  LWIP_UNUSED_ARG(dhcp);
+
+  /* clear received options */
+  dhcp_clear_all_options(dhcp);
+  /* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
+  if (p->len < DHCP_SNAME_OFS) {
+    return ERR_BUF;
+  }
+  msg_in = (struct dhcp_msg *)p->payload;
+#if LWIP_DHCP_BOOTP_FILE
+  /* clear boot file name */
+  dhcp->boot_file_name[0] = 0;
+#endif /* LWIP_DHCP_BOOTP_FILE */
+
+  /* parse options */
+
+  /* start with options field */
+  options_idx = DHCP_OPTIONS_OFS;
+  /* parse options to the end of the received packet */
+  options_idx_max = p->tot_len;
+again:
+  q = p;
+  while ((q != NULL) && (options_idx >= q->len)) {
+    options_idx = (u16_t)(options_idx - q->len);
+    options_idx_max = (u16_t)(options_idx_max - q->len);
+    q = q->next;
+  }
+  if (q == NULL) {
+    return ERR_BUF;
+  }
+  offset = options_idx;
+  offset_max = options_idx_max;
+  options = (u8_t *)q->payload;
+  /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+  while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
+    u8_t op = options[offset];
+    u8_t len;
+    u8_t decode_len = 0;
+    int decode_idx = -1;
+    u16_t val_offset = (u16_t)(offset + 2);
+    if (val_offset < offset) {
+      /* overflow */
+      return ERR_BUF;
+    }
+    /* len byte might be in the next pbuf */
+    if ((offset + 1) < q->len) {
+      len = options[offset + 1];
+    } else {
+      len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0);
+    }
+    /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
+    decode_len = len;
+    switch (op) {
+      /* case(DHCP_OPTION_END): handled above */
+      case (DHCP_OPTION_PAD):
+        /* special option: no len encoded */
+        decode_len = len = 0;
+        /* will be increased below */
+        break;
+      case (DHCP_OPTION_SUBNET_MASK):
+        LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
+        break;
+      case (DHCP_OPTION_ROUTER):
+        decode_len = 4; /* only copy the first given router */
+        LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_ROUTER;
+        break;
+#if LWIP_DHCP_PROVIDE_DNS_SERVERS
+      case (DHCP_OPTION_DNS_SERVER):
+        /* special case: there might be more than one server */
+        LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;);
+        /* limit number of DNS servers */
+        decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS);
+        LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
+        break;
+#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
+      case (DHCP_OPTION_LEASE_TIME):
+        LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
+        break;
+#if LWIP_DHCP_GET_NTP_SRV
+      case (DHCP_OPTION_NTP):
+        /* special case: there might be more than one server */
+        LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;);
+        /* limit number of NTP servers */
+        decode_len = LWIP_MIN(len, 4 * LWIP_DHCP_MAX_NTP_SERVERS);
+        LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_NTP_SERVER;
+        break;
+#endif /* LWIP_DHCP_GET_NTP_SRV*/
+      case (DHCP_OPTION_OVERLOAD):
+        LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
+        /* decode overload only in options, not in file/sname: invalid packet */
+        LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_OVERLOAD;
+        break;
+      case (DHCP_OPTION_MESSAGE_TYPE):
+        LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
+        break;
+      case (DHCP_OPTION_SERVER_ID):
+        LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_SERVER_ID;
+        break;
+      case (DHCP_OPTION_T1):
+        LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_T1;
+        break;
+      case (DHCP_OPTION_T2):
+        LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
+        decode_idx = DHCP_OPTION_IDX_T2;
+        break;
+      default:
+        decode_len = 0;
+        LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op));
+        LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in,
+                                    dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0,
+                                    op, len, q, val_offset);
+        break;
+    }
+    if (op == DHCP_OPTION_PAD) {
+      offset++;
+    } else {
+      if (offset + len + 2 > 0xFFFF) {
+        /* overflow */
+        return ERR_BUF;
+      }
+      offset = (u16_t)(offset + len + 2);
+      if (decode_len > 0) {
+        u32_t value = 0;
+        u16_t copy_len;
+decode_next:
+        LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
+        if (!dhcp_option_given(dhcp, decode_idx)) {
+          copy_len = LWIP_MIN(decode_len, 4);
+          if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) {
+            return ERR_BUF;
+          }
+          if (decode_len > 4) {
+            /* decode more than one u32_t */
+            u16_t next_val_offset;
+            LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;);
+            dhcp_got_option(dhcp, decode_idx);
+            dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value));
+            decode_len = (u8_t)(decode_len - 4);
+            next_val_offset = (u16_t)(val_offset + 4);
+            if (next_val_offset < val_offset) {
+              /* overflow */
+              return ERR_BUF;
+            }
+            val_offset = next_val_offset;
+            decode_idx++;
+            goto decode_next;
+          } else if (decode_len == 4) {
+            value = lwip_ntohl(value);
+          } else {
+            LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;);
+            value = ((u8_t *)&value)[0];
+          }
+          dhcp_got_option(dhcp, decode_idx);
+          dhcp_set_option_value(dhcp, decode_idx, value);
+        }
+      }
+    }
+    if (offset >= q->len) {
+      offset = (u16_t)(offset - q->len);
+      offset_max = (u16_t)(offset_max - q->len);
+      if (offset < offset_max) {
+        q = q->next;
+        LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;);
+        options = (u8_t *)q->payload;
+      } else {
+        /* We've run out of bytes, probably no end marker. Don't proceed. */
+        return ERR_BUF;
+      }
+    }
+  }
+  /* is this an overloaded message? */
+  if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
+    u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
+    dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
+    if (overload == DHCP_OVERLOAD_FILE) {
+      parse_file_as_options = 1;
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
+    } else if (overload == DHCP_OVERLOAD_SNAME) {
+      parse_sname_as_options = 1;
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
+    } else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
+      parse_sname_as_options = 1;
+      parse_file_as_options = 1;
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
+    }
+  }
+  if (parse_file_as_options) {
+    /* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
+    parse_file_as_options = 0;
+    options_idx = DHCP_FILE_OFS;
+    options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
+#if LWIP_DHCP_BOOTP_FILE
+    file_overloaded = 1;
+#endif
+    goto again;
+  } else if (parse_sname_as_options) {
+    parse_sname_as_options = 0;
+    options_idx = DHCP_SNAME_OFS;
+    options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
+    goto again;
+  }
+#if LWIP_DHCP_BOOTP_FILE
+  if (!file_overloaded) {
+    /* only do this for ACK messages */
+    if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) &&
+      (dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) == DHCP_ACK))
+    /* copy bootp file name, don't care for sname (server hostname) */
+    if (pbuf_copy_partial(p, dhcp->boot_file_name, DHCP_FILE_LEN-1, DHCP_FILE_OFS) != (DHCP_FILE_LEN-1)) {
+      return ERR_BUF;
+    }
+    /* make sure the string is really NULL-terminated */
+    dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
+  }
+#endif /* LWIP_DHCP_BOOTP_FILE */ 
+  return ERR_OK;
+}
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void
+dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
+{
+  struct netif *netif = ip_current_input_netif();
+  struct dhcp *dhcp = netif_dhcp_data(netif);
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t msg_type;
+  u8_t i;
+  struct dhcp_msg *msg_in;
+
+  LWIP_UNUSED_ARG(arg);
+
+  /* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */
+  if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) {
+    goto free_pbuf_and_return;
+  }
+
+  LWIP_ASSERT("invalid server address type", IP_IS_V4(addr));
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void *)p,
+              ip4_addr1_16(ip_2_ip4(addr)), ip4_addr2_16(ip_2_ip4(addr)), ip4_addr3_16(ip_2_ip4(addr)), ip4_addr4_16(ip_2_ip4(addr)), port));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  if (p->len < DHCP_MIN_REPLY_LEN) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
+    goto free_pbuf_and_return;
+  }
+
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
+    goto free_pbuf_and_return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                  ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
+                   (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
+      goto free_pbuf_and_return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (lwip_ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid));
+    goto free_pbuf_and_return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_parse_reply(p, dhcp) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("problem unfolding DHCP message - too short on memory?\n"));
+    goto free_pbuf_and_return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    goto free_pbuf_and_return;
+  }
+
+  msg_in = (struct dhcp_msg *)p->payload;
+  /* read DHCP message type */
+  msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_STATE_REQUESTING) {
+      dhcp_handle_ack(netif, msg_in);
+#if DHCP_DOES_ARP_CHECK
+      if ((netif->flags & NETIF_FLAG_ETHARP) != 0) {
+        /* check if the acknowledged lease address is already in use */
+        dhcp_check(netif);
+      } else {
+        /* bind interface to the acknowledged lease address */
+        dhcp_bind(netif);
+      }
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
+             (dhcp->state == DHCP_STATE_RENEWING)) {
+      dhcp_handle_ack(netif, msg_in);
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+           ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
+            (dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n"));
+    /* remember offered lease */
+    dhcp_handle_offer(netif, msg_in);
+  }
+
+free_pbuf_and_return:
+  pbuf_free(p);
+}
+
+/**
+ * Create a DHCP request, fill in common headers
+ *
+ * @param netif the netif under DHCP control
+ * @param dhcp dhcp control struct
+ * @param message_type message type of the request
+ */
+static struct pbuf *
+dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len)
+{
+  u16_t i;
+  struct pbuf *p_out;
+  struct dhcp_msg *msg_out;
+  u16_t options_out_len_loc;
+
+#ifndef DHCP_GLOBAL_XID
+  /** default global transaction identifier starting value (easy to match
+   *  with a packet analyser). We simply increment for each new request.
+   *  Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one
+   *  at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */
+#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
+  static u32_t xid;
+#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
+  static u32_t xid = 0xABCD0000;
+#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
+#else
+  if (!xid_initialised) {
+    xid = DHCP_GLOBAL_XID;
+    xid_initialised = !xid_initialised;
+  }
+#endif
+  LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;);
+  LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;);
+  p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("dhcp_create_msg(): could not allocate pbuf\n"));
+    return NULL;
+  }
+  LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
+              (p_out->len >= sizeof(struct dhcp_msg)));
+
+  /* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */
+  if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) {
+    /* reuse transaction identifier in retransmissions */
+    if (dhcp->tries == 0) {
+#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
+      xid = LWIP_RAND();
+#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
+      xid++;
+#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
+    }
+    dhcp->xid = xid;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
+              ("transaction id xid(%"X32_F")\n", xid));
+
+  msg_out = (struct dhcp_msg *)p_out->payload;
+  memset(msg_out, 0, sizeof(struct dhcp_msg));
+
+  msg_out->op = DHCP_BOOTREQUEST;
+  /* @todo: make link layer independent */
+  msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET;
+  msg_out->hlen = netif->hwaddr_len;
+  msg_out->xid = lwip_htonl(dhcp->xid);
+  /* we don't need the broadcast flag since we can receive unicast traffic
+     before being fully configured! */
+  /* set ciaddr to netif->ip_addr based on message_type and state */
+  if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) ||
+      ((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
+       ((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
+    ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif));
+  }
+  for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
+    /* copy netif hardware address (padded with zeroes through memset already) */
+    msg_out->chaddr[i] = netif->hwaddr[i];
+  }
+  msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
+  /* Add option MESSAGE_TYPE */
+  options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+  options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type);
+  if (options_out_len) {
+    *options_out_len = options_out_len_loc;
+  }
+  return p_out;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ */
+static void
+dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out)
+{
+  options[options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
+         (options_out_len < DHCP_OPTIONS_LEN)) {
+    /* add a fill/padding byte */
+    options[options_out_len++] = 0;
+  }
+  /* shrink the pbuf to the actual content length */
+  pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len));
+}
+
+/** check if DHCP supplied netif->ip_addr
+ *
+ * @param netif the netif to check
+ * @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING),
+ *         0 otherwise
+ */
+u8_t
+dhcp_supplied_address(const struct netif *netif)
+{
+  if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) {
+    struct dhcp *dhcp = netif_dhcp_data(netif);
+    return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
+           (dhcp->state == DHCP_STATE_REBINDING);
+  }
+  return 0;
+}
+
+#endif /* LWIP_IPV4 && LWIP_DHCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/etharp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/etharp.c
new file mode 100644
index 000000000..442aac08a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/etharp.c
@@ -0,0 +1,1204 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_gratuitous(our_netif) upon address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/etharp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/prot/iana.h"
+#include "netif/ethernet.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/** Re-request a used ARP entry 1 minute before it would expire to prevent
+ *  breaking a steadily used connection because the ARP entry timed out. */
+#define ARP_AGE_REREQUEST_USED_UNICAST   (ARP_MAXAGE - 30)
+#define ARP_AGE_REREQUEST_USED_BROADCAST (ARP_MAXAGE - 15)
+
+/** the time an ARP entry stays pending after first request,
+ *  for ARP_TMR_INTERVAL = 1000, this is
+ *  10 seconds.
+ *
+ *  @internal Keep this number at least 2, otherwise it might
+ *  run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 5
+
+/** ARP states */
+enum etharp_state {
+  ETHARP_STATE_EMPTY = 0,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE,
+  ETHARP_STATE_STABLE_REREQUESTING_1,
+  ETHARP_STATE_STABLE_REREQUESTING_2
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+  , ETHARP_STATE_STATIC
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** Pointer to queue of pending outgoing packets on this ARP entry. */
+  struct etharp_q_entry *q;
+#else /* ARP_QUEUEING */
+  /** Pointer to a single pending outgoing packet on this ARP entry. */
+  struct pbuf *q;
+#endif /* ARP_QUEUEING */
+  ip4_addr_t ipaddr;
+  struct netif *netif;
+  struct eth_addr ethaddr;
+  u16_t ctime;
+  u8_t state;
+};
+
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+
+#if !LWIP_NETIF_HWADDRHINT
+static netif_addr_idx_t etharp_cached_entry;
+#endif /* !LWIP_NETIF_HWADDRHINT */
+
+/** Try hard to create a new entry - we want the IP address to appear in
+    the cache (even if this means removing an active entry or so). */
+#define ETHARP_FLAG_TRY_HARD     1
+#define ETHARP_FLAG_FIND_ONLY    2
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+#define ETHARP_FLAG_STATIC_ENTRY 4
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+#if LWIP_NETIF_HWADDRHINT
+#define ETHARP_SET_ADDRHINT(netif, addrhint)  do { if (((netif) != NULL) && ((netif)->hints != NULL)) { \
+                                              (netif)->hints->addr_hint = (addrhint); }} while(0)
+#else /* LWIP_NETIF_HWADDRHINT */
+#define ETHARP_SET_ADDRHINT(netif, addrhint)  (etharp_cached_entry = (addrhint))
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+
+/* Check for maximum ARP_TABLE_SIZE */
+#if (ARP_TABLE_SIZE > NETIF_ADDR_IDX_MAX)
+#error "ARP_TABLE_SIZE must fit in an s16_t, you have to reduce it in your lwipopts.h"
+#endif
+
+
+static err_t etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr);
+static err_t etharp_raw(struct netif *netif,
+                        const struct eth_addr *ethsrc_addr, const struct eth_addr *ethdst_addr,
+                        const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
+                        const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
+                        const u16_t opcode);
+
+#if ARP_QUEUEING
+/**
+ * Free a complete queue of etharp entries
+ *
+ * @param q a qeueue of etharp_q_entry's to free
+ */
+static void
+free_etharp_q(struct etharp_q_entry *q)
+{
+  struct etharp_q_entry *r;
+  LWIP_ASSERT("q != NULL", q != NULL);
+  while (q) {
+    r = q;
+    q = q->next;
+    LWIP_ASSERT("r->p != NULL", (r->p != NULL));
+    pbuf_free(r->p);
+    memp_free(MEMP_ARP_QUEUE, r);
+  }
+}
+#else /* ARP_QUEUEING */
+
+/** Compatibility define: free the queued pbuf */
+#define free_etharp_q(q) pbuf_free(q)
+
+#endif /* ARP_QUEUEING */
+
+/** Clean up ARP table entries */
+static void
+etharp_free_entry(int i)
+{
+  /* remove from SNMP ARP index tree */
+  mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
+  /* and empty packet queue */
+  if (arp_table[i].q != NULL) {
+    /* remove all queued packets */
+    LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
+    free_etharp_q(arp_table[i].q);
+    arp_table[i].q = NULL;
+  }
+  /* recycle entry for re-use */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+#ifdef LWIP_DEBUG
+  /* for debugging, clean out the complete entry */
+  arp_table[i].ctime = 0;
+  arp_table[i].netif = NULL;
+  ip4_addr_set_zero(&arp_table[i].ipaddr);
+  arp_table[i].ethaddr = ethzero;
+#endif /* LWIP_DEBUG */
+}
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  int i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    u8_t state = arp_table[i].state;
+    if (state != ETHARP_STATE_EMPTY
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+        && (state != ETHARP_STATE_STATIC)
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+       ) {
+      arp_table[i].ctime++;
+      if ((arp_table[i].ctime >= ARP_MAXAGE) ||
+          ((arp_table[i].state == ETHARP_STATE_PENDING)  &&
+           (arp_table[i].ctime >= ARP_MAXPENDING))) {
+        /* pending or stable entry has become old! */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
+                                   arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
+        /* clean up entries that have just been expired */
+        etharp_free_entry(i);
+      } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
+        /* Don't send more than one request every 2 seconds. */
+        arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
+      } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
+        /* Reset state to stable, so that the next transmitted packet will
+           re-send an ARP request. */
+        arp_table[i].state = ETHARP_STATE_STABLE;
+      } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+        /* still pending, resend an ARP query */
+        etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
+      }
+    }
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ *
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ *
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ *
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_FLAG_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags See @ref etharp_state
+ * @param netif netif related to this address (used for NETIF_HWADDRHINT)
+ *
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s16_t
+etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
+{
+  s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s16_t empty = ARP_TABLE_SIZE;
+  s16_t i = 0;
+  /* oldest entry with packets on queue */
+  s16_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u16_t age_queue = 0, age_pending = 0, age_stable = 0;
+
+  LWIP_UNUSED_ARG(netif);
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    u8_t state = arp_table[i].state;
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
+      /* remember first empty entry */
+      empty = i;
+    } else if (state != ETHARP_STATE_EMPTY) {
+      LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
+                  state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
+#if ETHARP_TABLE_MATCH_NETIF
+          && ((netif == NULL) || (netif == arp_table[i].netif))
+#endif /* ETHARP_TABLE_MATCH_NETIF */
+         ) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+      }
+      /* pending entry? */
+      if (state == ETHARP_STATE_PENDING) {
+        /* pending with queued packets? */
+        if (arp_table[i].q != NULL) {
+          if (arp_table[i].ctime >= age_queue) {
+            old_queue = i;
+            age_queue = arp_table[i].ctime;
+          }
+        } else
+          /* pending without queued packets? */
+        {
+          if (arp_table[i].ctime >= age_pending) {
+            old_pending = i;
+            age_pending = arp_table[i].ctime;
+          }
+        }
+        /* stable entry? */
+      } else if (state >= ETHARP_STATE_STABLE) {
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+        /* don't record old_stable for static entries since they never expire */
+        if (state < ETHARP_STATE_STATIC)
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+        {
+          /* remember entry with oldest stable entry in oldest, its age in maxtime */
+          if (arp_table[i].ctime >= age_stable) {
+            old_stable = i;
+            age_stable = arp_table[i].ctime;
+          }
+        }
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+
+  /* don't create new entry, only search? */
+  if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
+      /* or no empty entry found and not allowed to recycle? */
+      ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
+    return (s16_t)ERR_MEM;
+  }
+
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry with queued packets
+   *
+   * { ETHARP_FLAG_TRY_HARD is set at this point }
+   */
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
+  } else {
+    /* 2) found recyclable stable entry? */
+    if (old_stable < ARP_TABLE_SIZE) {
+      /* recycle oldest stable*/
+      i = old_stable;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
+      /* no queued packets should exist on stable entries */
+      LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
+      /* 3) found recyclable pending entry without queued packets? */
+    } else if (old_pending < ARP_TABLE_SIZE) {
+      /* recycle oldest pending */
+      i = old_pending;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
+      /* 4) found recyclable pending entry with queued packets? */
+    } else if (old_queue < ARP_TABLE_SIZE) {
+      /* recycle oldest pending (queued packets are free in etharp_free_entry) */
+      i = old_queue;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
+      /* no empty or recyclable entries found */
+    } else {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
+      return (s16_t)ERR_MEM;
+    }
+
+    /* { empty or recyclable entry found } */
+    LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+    etharp_free_entry(i);
+  }
+
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+  LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
+              arp_table[i].state == ETHARP_STATE_EMPTY);
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
+  }
+  arp_table[i].ctime = 0;
+#if ETHARP_TABLE_MATCH_NETIF
+  arp_table[i].netif = netif;
+#endif /* ETHARP_TABLE_MATCH_NETIF */
+  return (s16_t)i;
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ *
+ * @param netif netif related to this entry (used for NETIF_ADDRHINT)
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags See @ref etharp_state
+ *
+ * @return
+ * - ERR_OK Successfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_FLAG_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s16_t i;
+  LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+              ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
+              (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
+              (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip4_addr_isany(ipaddr) ||
+      ip4_addr_isbroadcast(ipaddr, netif) ||
+      ip4_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+  i = etharp_find_entry(ipaddr, flags, netif);
+  /* bail out if no entry could be found */
+  if (i < 0) {
+    return (err_t)i;
+  }
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+  if (flags & ETHARP_FLAG_STATIC_ENTRY) {
+    /* record static type */
+    arp_table[i].state = ETHARP_STATE_STATIC;
+  } else if (arp_table[i].state == ETHARP_STATE_STATIC) {
+    /* found entry is a static type, don't overwrite it */
+    return ERR_VAL;
+  } else
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+  {
+    /* mark it stable */
+    arp_table[i].state = ETHARP_STATE_STABLE;
+  }
+
+  /* record network interface */
+  arp_table[i].netif = netif;
+  /* insert in SNMP ARP index tree */
+  mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
+
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
+  /* update address */
+  SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+  /* this is where we will send out queued packets! */
+#if ARP_QUEUEING
+  while (arp_table[i].q != NULL) {
+    struct pbuf *p;
+    /* remember remainder of queue */
+    struct etharp_q_entry *q = arp_table[i].q;
+    /* pop first item off the queue */
+    arp_table[i].q = q->next;
+    /* get the packet pointer */
+    p = q->p;
+    /* now queue entry can be freed */
+    memp_free(MEMP_ARP_QUEUE, q);
+#else /* ARP_QUEUEING */
+  if (arp_table[i].q != NULL) {
+    struct pbuf *p = arp_table[i].q;
+    arp_table[i].q = NULL;
+#endif /* ARP_QUEUEING */
+    /* send the queued IP packet */
+    ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+  return ERR_OK;
+}
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+/** Add a new static entry to the ARP table. If an entry exists for the
+ * specified IP address, this entry is overwritten.
+ * If packets are queued for the specified IP address, they are sent out.
+ *
+ * @param ipaddr IP address for the new static entry
+ * @param ethaddr ethernet address for the new static entry
+ * @return See return values of etharp_add_static_entry
+ */
+err_t
+etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr)
+{
+  struct netif *netif;
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_add_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+              ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
+              (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
+              (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
+
+  netif = ip4_route(ipaddr);
+  if (netif == NULL) {
+    return ERR_RTE;
+  }
+
+  return etharp_update_arp_entry(netif, ipaddr, ethaddr, ETHARP_FLAG_TRY_HARD | ETHARP_FLAG_STATIC_ENTRY);
+}
+
+/** Remove a static entry from the ARP table previously added with a call to
+ * etharp_add_static_entry.
+ *
+ * @param ipaddr IP address of the static entry to remove
+ * @return ERR_OK: entry removed
+ *         ERR_MEM: entry wasn't found
+ *         ERR_ARG: entry wasn't a static entry but a dynamic one
+ */
+err_t
+etharp_remove_static_entry(const ip4_addr_t *ipaddr)
+{
+  s16_t i;
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_remove_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+              ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr)));
+
+  /* find or create ARP entry */
+  i = etharp_find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY, NULL);
+  /* bail out if no entry could be found */
+  if (i < 0) {
+    return (err_t)i;
+  }
+
+  if (arp_table[i].state != ETHARP_STATE_STATIC) {
+    /* entry wasn't a static entry, cannot remove it */
+    return ERR_ARG;
+  }
+  /* entry found, free it */
+  etharp_free_entry(i);
+  return ERR_OK;
+}
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+/**
+ * Remove all ARP table entries of the specified netif.
+ *
+ * @param netif points to a network interface
+ */
+void
+etharp_cleanup_netif(struct netif *netif)
+{
+  int i;
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    u8_t state = arp_table[i].state;
+    if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
+      etharp_free_entry(i);
+    }
+  }
+}
+
+/**
+ * Finds (stable) ethernet/IP address pair from ARP table
+ * using interface and IP address index.
+ * @note the addresses in the ARP table are in network order!
+ *
+ * @param netif points to interface index
+ * @param ipaddr points to the (network order) IP address index
+ * @param eth_ret points to return pointer
+ * @param ip_ret points to return pointer
+ * @return table index if found, -1 otherwise
+ */
+ssize_t
+etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+                 struct eth_addr **eth_ret, const ip4_addr_t **ip_ret)
+{
+  s16_t i;
+
+  LWIP_ASSERT("eth_ret != NULL && ip_ret != NULL",
+              eth_ret != NULL && ip_ret != NULL);
+
+  LWIP_UNUSED_ARG(netif);
+
+  i = etharp_find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY, netif);
+  if ((i >= 0) && (arp_table[i].state >= ETHARP_STATE_STABLE)) {
+    *eth_ret = &arp_table[i].ethaddr;
+    *ip_ret = &arp_table[i].ipaddr;
+    return i;
+  }
+  return -1;
+}
+
+/**
+ * Possibility to iterate over stable ARP table entries
+ *
+ * @param i entry number, 0 to ARP_TABLE_SIZE
+ * @param ipaddr return value: IP address
+ * @param netif return value: points to interface
+ * @param eth_ret return value: ETH address
+ * @return 1 on valid index, 0 otherwise
+ */
+int
+etharp_get_entry(size_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret)
+{
+  LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("eth_ret != NULL", eth_ret != NULL);
+
+  if ((i < ARP_TABLE_SIZE) && (arp_table[i].state >= ETHARP_STATE_STABLE)) {
+    *ipaddr  = &arp_table[i].ipaddr;
+    *netif   = arp_table[i].netif;
+    *eth_ret = &arp_table[i].ethaddr;
+    return 1;
+  } else {
+    return 0;
+  }
+}
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param p The ARP packet that arrived on netif. Is freed by this function.
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_input(struct pbuf *p, struct netif *netif)
+{
+  struct etharp_hdr *hdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  ip4_addr_t sipaddr, dipaddr;
+  u8_t for_us;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif != NULL", (netif != NULL), return;);
+
+  hdr = (struct etharp_hdr *)p->payload;
+
+  /* RFC 826 "Packet Reception": */
+  if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
+      (hdr->hwlen != ETH_HWADDR_LEN) ||
+      (hdr->protolen != sizeof(ip4_addr_t)) ||
+      (hdr->proto != PP_HTONS(ETHTYPE_IP)))  {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
+                 hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    pbuf_free(p);
+    return;
+  }
+  ETHARP_STATS_INC(etharp.recv);
+
+#if LWIP_AUTOIP
+  /* We have to check if a host already has configured our random
+   * created link local address and continuously check if there is
+   * a host with this IP-address so we can detect collisions */
+  autoip_arp_reply(netif, hdr);
+#endif /* LWIP_AUTOIP */
+
+  /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
+   * structure packing (not using structure copy which breaks strict-aliasing rules). */
+  IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
+  IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
+
+  /* this interface is not configured? */
+  if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
+  }
+
+  /* ARP message directed to us?
+      -> add IP address in ARP cache; assume requester wants to talk to us,
+         can result in directly sending the queued packets for this host.
+     ARP message not directed to us?
+      ->  update the source IP address in the cache, if present */
+  etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
+                          for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
+
+  /* now act on the message itself */
+  switch (hdr->opcode) {
+    /* ARP request? */
+    case PP_HTONS(ARP_REQUEST):
+      /* ARP request. If it asked for our address, we send out a
+       * reply. In any case, we time-stamp any existing ARP entry,
+       * and possibly send out an IP packet that was queued on it. */
+
+      LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: incoming ARP request\n"));
+      /* ARP request for our address? */
+      if (for_us) {
+        /* send ARP response */
+        etharp_raw(netif,
+                   (struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
+                   (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
+                   &hdr->shwaddr, &sipaddr,
+                   ARP_REPLY);
+        /* we are not configured? */
+      } else if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+        /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: we are unconfigured, ARP request ignored.\n"));
+        /* request was not directed to us */
+      } else {
+        /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP request was not for us.\n"));
+      }
+      break;
+    case PP_HTONS(ARP_REPLY):
+      /* ARP reply. We already updated the ARP cache earlier. */
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+      /* DHCP wants to know about ARP replies from any host with an
+       * IP address also offered to us by the DHCP server. We do not
+       * want to take a duplicate IP address on a single network.
+       * @todo How should we handle redundant (fail-over) interfaces? */
+      dhcp_arp_reply(netif, &sipaddr);
+#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
+      break;
+    default:
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
+      ETHARP_STATS_INC(etharp.err);
+      break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/** Just a small helper function that sends a pbuf to an ethernet address
+ * in the arp_table specified by the index 'arp_idx'.
+ */
+static err_t
+etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
+{
+  LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
+              arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
+  /* if arp table entry is about to expire: re-request it,
+     but only if its state is ETHARP_STATE_STABLE to prevent flooding the
+     network with ARP requests if this address is used frequently. */
+  if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
+    if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
+      /* issue a standard request using broadcast */
+      if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
+        arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
+      }
+    } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
+      /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
+      if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
+        arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
+      }
+    }
+  }
+
+  return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing IP packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ipaddr The IP address of the packet destination.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or ethernet_output().
+ */
+err_t
+etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
+{
+  const struct eth_addr *dest;
+  struct eth_addr mcastaddr;
+  const ip4_addr_t *dst_addr = ipaddr;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("q != NULL", q != NULL);
+  LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
+
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip4_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (const struct eth_addr *)&ethbroadcast;
+    /* multicast destination IP address? */
+  } else if (ip4_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
+    mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
+    mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+    /* unicast destination IP address? */
+  } else {
+    netif_addr_idx_t i;
+    /* outside local network? if so, this can neither be a global broadcast nor
+       a subnet broadcast. */
+    if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
+        !ip4_addr_islinklocal(ipaddr)) {
+#if LWIP_AUTOIP
+      struct ip_hdr *iphdr = LWIP_ALIGNMENT_CAST(struct ip_hdr *, q->payload);
+      /* According to RFC 3297, chapter 2.6.2 (Forwarding Rules), a packet with
+         a link-local source address must always be "directly to its destination
+         on the same physical link. The host MUST NOT send the packet to any
+         router for forwarding". */
+      if (!ip4_addr_islinklocal(&iphdr->src))
+#endif /* LWIP_AUTOIP */
+      {
+#ifdef LWIP_HOOK_ETHARP_GET_GW
+        /* For advanced routing, a single default gateway might not be enough, so get
+           the IP address of the gateway to handle the current destination address. */
+        dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
+        if (dst_addr == NULL)
+#endif /* LWIP_HOOK_ETHARP_GET_GW */
+        {
+          /* interface has default gateway? */
+          if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
+            /* send to hardware address of default gateway IP address */
+            dst_addr = netif_ip4_gw(netif);
+            /* no default gateway available */
+          } else {
+            /* no route to destination error (default gateway missing) */
+            return ERR_RTE;
+          }
+        }
+      }
+    }
+#if LWIP_NETIF_HWADDRHINT
+    if (netif->hints != NULL) {
+      /* per-pcb cached entry was given */
+      netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
+      if (etharp_cached_entry < ARP_TABLE_SIZE) {
+#endif /* LWIP_NETIF_HWADDRHINT */
+        if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
+#if ETHARP_TABLE_MATCH_NETIF
+            (arp_table[etharp_cached_entry].netif == netif) &&
+#endif
+            (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
+          /* the per-pcb-cached entry is stable and the right one! */
+          ETHARP_STATS_INC(etharp.cachehit);
+          return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
+        }
+#if LWIP_NETIF_HWADDRHINT
+      }
+    }
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+    /* find stable entry: do this here since this is a critical path for
+       throughput and etharp_find_entry() is kind of slow */
+    for (i = 0; i < ARP_TABLE_SIZE; i++) {
+      if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
+#if ETHARP_TABLE_MATCH_NETIF
+          (arp_table[i].netif == netif) &&
+#endif
+          (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
+        /* found an existing, stable entry */
+        ETHARP_SET_ADDRHINT(netif, i);
+        return etharp_output_to_arp_index(netif, q, i);
+      }
+    }
+    /* no stable entry found, use the (slower) query function:
+       queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, dst_addr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  /* send packet directly on the link */
+  return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out.
+ *
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ *
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @note q must only be ONE packet, not a packet queue!
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t
+etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
+{
+  struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  int is_new_entry = 0;
+  s16_t i_err;
+  netif_addr_idx_t i;
+
+  /* non-unicast address? */
+  if (ip4_addr_isbroadcast(ipaddr, netif) ||
+      ip4_addr_ismulticast(ipaddr) ||
+      ip4_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
+
+  /* could not find or create entry? */
+  if (i_err < 0) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) {
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
+      ETHARP_STATS_INC(etharp.memerr);
+    }
+    return (err_t)i_err;
+  }
+  LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
+  i = (netif_addr_idx_t)i_err;
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    is_new_entry = 1;
+    arp_table[i].state = ETHARP_STATE_PENDING;
+    /* record network interface for re-sending arp request in etharp_tmr */
+    arp_table[i].netif = netif;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+              ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+               (arp_table[i].state >= ETHARP_STATE_STABLE)));
+
+  /* do we have a new entry? or an implicit query request? */
+  if (is_new_entry || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+    if (result != ERR_OK) {
+      /* ARP request couldn't be sent */
+      /* We don't re-send arp request in etharp_tmr, but we still queue packets,
+         since this failure could be temporary, and the next packet calling
+         etharp_query again could lead to sending the queued packets. */
+    }
+    if (q == NULL) {
+      return result;
+    }
+  }
+
+  /* packet given? */
+  LWIP_ASSERT("q != NULL", q != NULL);
+  /* stable entry? */
+  if (arp_table[i].state >= ETHARP_STATE_STABLE) {
+    /* we have a valid IP->Ethernet address mapping */
+    ETHARP_SET_ADDRHINT(netif, i);
+    /* send the packet */
+    result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
+    /* pending entry? (either just created or already pending */
+  } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+    /* entry is still pending, queue the given packet 'q' */
+    struct pbuf *p;
+    int copy_needed = 0;
+    /* IF q includes a pbuf that must be copied, copy the whole chain into a
+     * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
+    p = q;
+    while (p) {
+      LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
+      if (PBUF_NEEDS_COPY(p)) {
+        copy_needed = 1;
+        break;
+      }
+      p = p->next;
+    }
+    if (copy_needed) {
+      /* copy the whole packet into new pbufs */
+      p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
+    } else {
+      /* referencing the old pbuf is enough */
+      p = q;
+      pbuf_ref(p);
+    }
+    /* packet could be taken over? */
+    if (p != NULL) {
+      /* queue packet ... */
+#if ARP_QUEUEING
+      struct etharp_q_entry *new_entry;
+      /* allocate a new arp queue entry */
+      new_entry = (struct etharp_q_entry *)memp_malloc(MEMP_ARP_QUEUE);
+      if (new_entry != NULL) {
+        unsigned int qlen = 0;
+        new_entry->next = 0;
+        new_entry->p = p;
+        if (arp_table[i].q != NULL) {
+          /* queue was already existent, append the new entry to the end */
+          struct etharp_q_entry *r;
+          r = arp_table[i].q;
+          qlen++;
+          while (r->next != NULL) {
+            r = r->next;
+            qlen++;
+          }
+          r->next = new_entry;
+        } else {
+          /* queue did not exist, first item in queue */
+          arp_table[i].q = new_entry;
+        }
+#if ARP_QUEUE_LEN
+        if (qlen >= ARP_QUEUE_LEN) {
+          struct etharp_q_entry *old;
+          old = arp_table[i].q;
+          arp_table[i].q = arp_table[i].q->next;
+          pbuf_free(old->p);
+          memp_free(MEMP_ARP_QUEUE, old);
+        }
+#endif
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, i));
+        result = ERR_OK;
+      } else {
+        /* the pool MEMP_ARP_QUEUE is empty */
+        pbuf_free(p);
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        result = ERR_MEM;
+      }
+#else /* ARP_QUEUEING */
+      /* always queue one packet per ARP request only, freeing a previously queued packet */
+      if (arp_table[i].q != NULL) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
+        pbuf_free(arp_table[i].q);
+      }
+      arp_table[i].q = p;
+      result = ERR_OK;
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
+#endif /* ARP_QUEUEING */
+    } else {
+      ETHARP_STATS_INC(etharp.memerr);
+      LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+      result = ERR_MEM;
+    }
+  }
+  return result;
+}
+
+/**
+ * Send a raw ARP packet (opcode and all addresses can be modified)
+ *
+ * @param netif the lwip network interface on which to send the ARP packet
+ * @param ethsrc_addr the source MAC address for the ethernet header
+ * @param ethdst_addr the destination MAC address for the ethernet header
+ * @param hwsrc_addr the source MAC address for the ARP protocol header
+ * @param ipsrc_addr the source IP address for the ARP protocol header
+ * @param hwdst_addr the destination MAC address for the ARP protocol header
+ * @param ipdst_addr the destination IP address for the ARP protocol header
+ * @param opcode the type of the ARP packet
+ * @return ERR_OK if the ARP packet has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+static err_t
+etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
+           const struct eth_addr *ethdst_addr,
+           const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
+           const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
+           const u16_t opcode)
+{
+  struct pbuf *p;
+  err_t result = ERR_OK;
+  struct etharp_hdr *hdr;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p == NULL) {
+    LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("etharp_raw: could not allocate pbuf for ARP request.\n"));
+    ETHARP_STATS_INC(etharp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
+              (p->len >= SIZEOF_ETHARP_HDR));
+
+  hdr = (struct etharp_hdr *)p->payload;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
+  hdr->opcode = lwip_htons(opcode);
+
+  LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
+              (netif->hwaddr_len == ETH_HWADDR_LEN));
+
+  /* Write the ARP MAC-Addresses */
+  SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
+  SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
+  /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
+   * structure packing. */
+  IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
+  IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
+
+  hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
+  hdr->proto = PP_HTONS(ETHTYPE_IP);
+  /* set hwlen and protolen */
+  hdr->hwlen = ETH_HWADDR_LEN;
+  hdr->protolen = sizeof(ip4_addr_t);
+
+  /* send ARP query */
+#if LWIP_AUTOIP
+  /* If we are using Link-Local, all ARP packets that contain a Link-Local
+   * 'sender IP address' MUST be sent using link-layer broadcast instead of
+   * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */
+  if (ip4_addr_islinklocal(ipsrc_addr)) {
+    ethernet_output(netif, p, ethsrc_addr, &ethbroadcast, ETHTYPE_ARP);
+  } else
+#endif /* LWIP_AUTOIP */
+  {
+    ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
+  }
+
+  ETHARP_STATS_INC(etharp.xmit);
+  /* free ARP query packet */
+  pbuf_free(p);
+  p = NULL;
+  /* could not allocate pbuf for ARP request */
+
+  return result;
+}
+
+/**
+ * Send an ARP request packet asking for ipaddr to a specific eth address.
+ * Used to send unicast request to refresh the ARP table just before an entry
+ * times out
+ *
+ * @param netif the lwip network interface on which to send the request
+ * @param ipaddr the IP address for which to ask
+ * @param hw_dst_addr the ethernet address to send this packet to
+ * @return ERR_OK if the request has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+static err_t
+etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
+{
+  return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
+                    (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), &ethzero,
+                    ipaddr, ARP_REQUEST);
+}
+
+/**
+ * Send an ARP request packet asking for ipaddr.
+ *
+ * @param netif the lwip network interface on which to send the request
+ * @param ipaddr the IP address for which to ask
+ * @return ERR_OK if the request has been sent
+ *         ERR_MEM if the ARP packet couldn't be allocated
+ *         any other err_t on failure
+ */
+err_t
+etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
+{
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+  return etharp_request_dst(netif, ipaddr, &ethbroadcast);
+}
+
+#endif /* LWIP_IPV4 && LWIP_ARP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/icmp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/icmp.c
new file mode 100644
index 000000000..a462ccd34
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/icmp.c
@@ -0,0 +1,404 @@
+/**
+ * @file
+ * ICMP - Internet Control Message Protocol
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be
+ * used to modify and send a response packet (and to 1 if this is not the case,
+ * e.g. when link header is stripped off when receiving) */
+#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+
+/* The amount of data from the original packet to return in a dest-unreachable */
+#define ICMP_DEST_UNREACH_DATASIZE 8
+
+static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code);
+
+/**
+ * Processes ICMP input packets, called from ip_input().
+ *
+ * Currently only processes icmp echo requests and sends
+ * out the echo response.
+ *
+ * @param p the icmp echo request packet, p->payload pointing to the icmp header
+ * @param inp the netif on which this packet was received
+ */
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+#ifdef LWIP_DEBUG
+  u8_t code;
+#endif /* LWIP_DEBUG */
+  struct icmp_echo_hdr *iecho;
+  const struct ip_hdr *iphdr_in;
+  u16_t hlen;
+  const ip4_addr_t *src;
+
+  ICMP_STATS_INC(icmp.recv);
+  MIB2_STATS_INC(mib2.icmpinmsgs);
+
+  iphdr_in = ip4_current_header();
+  hlen = IPH_HL_BYTES(iphdr_in);
+  if (hlen < IP_HLEN) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
+    goto lenerr;
+  }
+  if (p->len < sizeof(u16_t) * 2) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    goto lenerr;
+  }
+
+  type = *((u8_t *)p->payload);
+#ifdef LWIP_DEBUG
+  code = *(((u8_t *)p->payload) + 1);
+  /* if debug is enabled but debug statement below is somehow disabled: */
+  LWIP_UNUSED_ARG(code);
+#endif /* LWIP_DEBUG */
+  switch (type) {
+    case ICMP_ER:
+      /* This is OK, echo reply might have been parsed by a raw PCB
+         (as obviously, an echo request has been sent, too). */
+      MIB2_STATS_INC(mib2.icmpinechoreps);
+      break;
+    case ICMP_ECHO:
+      MIB2_STATS_INC(mib2.icmpinechos);
+      src = ip4_current_dest_addr();
+      /* multicast destination address? */
+      if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
+#if LWIP_MULTICAST_PING
+        /* For multicast, use address of receiving interface as source address */
+        src = netif_ip4_addr(inp);
+#else /* LWIP_MULTICAST_PING */
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
+        goto icmperr;
+#endif /* LWIP_MULTICAST_PING */
+      }
+      /* broadcast destination address? */
+      if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
+#if LWIP_BROADCAST_PING
+        /* For broadcast, use address of receiving interface as source address */
+        src = netif_ip4_addr(inp);
+#else /* LWIP_BROADCAST_PING */
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
+        goto icmperr;
+#endif /* LWIP_BROADCAST_PING */
+      }
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+      if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+        LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+        goto lenerr;
+      }
+#if CHECKSUM_CHECK_ICMP
+      IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) {
+        if (inet_chksum_pbuf(p) != 0) {
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+          pbuf_free(p);
+          ICMP_STATS_INC(icmp.chkerr);
+          MIB2_STATS_INC(mib2.icmpinerrors);
+          return;
+        }
+      }
+#endif
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+      if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
+        /* p is not big enough to contain link headers
+         * allocate a new one and copy p into it
+         */
+        struct pbuf *r;
+        u16_t alloc_len = (u16_t)(p->tot_len + hlen);
+        if (alloc_len < p->tot_len) {
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
+          goto icmperr;
+        }
+        /* allocate new packet buffer with space for link headers */
+        r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
+        if (r == NULL) {
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
+          goto icmperr;
+        }
+        if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
+          LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
+          pbuf_free(r);
+          goto icmperr;
+        }
+        /* copy the ip header */
+        MEMCPY(r->payload, iphdr_in, hlen);
+        /* switch r->payload back to icmp header (cannot fail) */
+        if (pbuf_remove_header(r, hlen)) {
+          LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
+          pbuf_free(r);
+          goto icmperr;
+        }
+        /* copy the rest of the packet without ip header */
+        if (pbuf_copy(r, p) != ERR_OK) {
+          LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
+          pbuf_free(r);
+          goto icmperr;
+        }
+        /* free the original p */
+        pbuf_free(p);
+        /* we now have an identical copy of p that has room for link headers */
+        p = r;
+      } else {
+        /* restore p->payload to point to icmp header (cannot fail) */
+        if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
+          LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
+          goto icmperr;
+        }
+      }
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
+      /* At this point, all checks are OK. */
+      /* We generate an answer by switching the dest and src ip addresses,
+       * setting the icmp type to ECHO_RESPONSE and updating the checksum. */
+      iecho = (struct icmp_echo_hdr *)p->payload;
+      if (pbuf_add_header(p, hlen)) {
+        LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
+      } else {
+        err_t ret;
+        struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
+        ip4_addr_copy(iphdr->src, *src);
+        ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
+        ICMPH_TYPE_SET(iecho, ICMP_ER);
+#if CHECKSUM_GEN_ICMP
+        IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP) {
+          /* adjust the checksum */
+          if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) {
+            iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS((u16_t)(ICMP_ECHO << 8)) + 1);
+          } else {
+            iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS(ICMP_ECHO << 8));
+          }
+        }
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+        else {
+          iecho->chksum = 0;
+        }
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+#else /* CHECKSUM_GEN_ICMP */
+        iecho->chksum = 0;
+#endif /* CHECKSUM_GEN_ICMP */
+
+        /* Set the correct TTL and recalculate the header checksum. */
+        IPH_TTL_SET(iphdr, ICMP_TTL);
+        IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+        IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_IP) {
+          IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, hlen));
+        }
+#endif /* CHECKSUM_GEN_IP */
+
+        ICMP_STATS_INC(icmp.xmit);
+        /* increase number of messages attempted to send */
+        MIB2_STATS_INC(mib2.icmpoutmsgs);
+        /* increase number of echo replies attempted to send */
+        MIB2_STATS_INC(mib2.icmpoutechoreps);
+
+        /* send an ICMP packet */
+        ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
+                            ICMP_TTL, 0, IP_PROTO_ICMP, inp);
+        if (ret != ERR_OK) {
+          LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
+        }
+      }
+      break;
+    default:
+      if (type == ICMP_DUR) {
+        MIB2_STATS_INC(mib2.icmpindestunreachs);
+      } else if (type == ICMP_TE) {
+        MIB2_STATS_INC(mib2.icmpintimeexcds);
+      } else if (type == ICMP_PP) {
+        MIB2_STATS_INC(mib2.icmpinparmprobs);
+      } else if (type == ICMP_SQ) {
+        MIB2_STATS_INC(mib2.icmpinsrcquenchs);
+      } else if (type == ICMP_RD) {
+        MIB2_STATS_INC(mib2.icmpinredirects);
+      } else if (type == ICMP_TS) {
+        MIB2_STATS_INC(mib2.icmpintimestamps);
+      } else if (type == ICMP_TSR) {
+        MIB2_STATS_INC(mib2.icmpintimestampreps);
+      } else if (type == ICMP_AM) {
+        MIB2_STATS_INC(mib2.icmpinaddrmasks);
+      } else if (type == ICMP_AMR) {
+        MIB2_STATS_INC(mib2.icmpinaddrmaskreps);
+      }
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
+                               (s16_t)type, (s16_t)code));
+      ICMP_STATS_INC(icmp.proterr);
+      ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+  return;
+lenerr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.lenerr);
+  MIB2_STATS_INC(mib2.icmpinerrors);
+  return;
+#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
+icmperr:
+  pbuf_free(p);
+  ICMP_STATS_INC(icmp.err);
+  MIB2_STATS_INC(mib2.icmpinerrors);
+  return;
+#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
+}
+
+/**
+ * Send an icmp 'destination unreachable' packet, called from ip_input() if
+ * the transport layer protocol is unknown and from udp_input() if the local
+ * port is not bound.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'unreachable' packet
+ */
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  MIB2_STATS_INC(mib2.icmpoutdestunreachs);
+  icmp_send_response(p, ICMP_DUR, t);
+}
+
+#if IP_FORWARD || IP_REASSEMBLY
+/**
+ * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0.
+ *
+ * @param p the input packet for which the 'time exceeded' should be sent,
+ *          p->payload pointing to the IP header
+ * @param t type of the 'time exceeded' packet
+ */
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  MIB2_STATS_INC(mib2.icmpouttimeexcds);
+  icmp_send_response(p, ICMP_TE, t);
+}
+
+#endif /* IP_FORWARD || IP_REASSEMBLY */
+
+/**
+ * Send an icmp packet in response to an incoming packet.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IP header
+ * @param type Type of the ICMP header
+ * @param code Code of the ICMP header
+ */
+static void
+icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  /* we can use the echo header here */
+  struct icmp_echo_hdr *icmphdr;
+  ip4_addr_t iphdr_src;
+  struct netif *netif;
+
+  /* increase number of messages attempted to send */
+  MIB2_STATS_INC(mib2.icmpoutmsgs);
+
+  /* ICMP header + IP header + 8 bytes of data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
+                 PBUF_RAM);
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
+    MIB2_STATS_INC(mib2.icmpouterrors);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp message",
+              (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
+
+  iphdr = (struct ip_hdr *)p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  icmphdr = (struct icmp_echo_hdr *)q->payload;
+  icmphdr->type = type;
+  icmphdr->code = code;
+  icmphdr->id = 0;
+  icmphdr->seqno = 0;
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
+          IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
+
+  ip4_addr_copy(iphdr_src, iphdr->src);
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+  {
+    ip4_addr_t iphdr_dst;
+    ip4_addr_copy(iphdr_dst, iphdr->dest);
+    netif = ip4_route_src(&iphdr_dst, &iphdr_src);
+  }
+#else
+  netif = ip4_route(&iphdr_src);
+#endif
+  if (netif != NULL) {
+    /* calculate checksum */
+    icmphdr->chksum = 0;
+#if CHECKSUM_GEN_ICMP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
+      icmphdr->chksum = inet_chksum(icmphdr, q->len);
+    }
+#endif
+    ICMP_STATS_INC(icmp.xmit);
+    ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
+  }
+  pbuf_free(q);
+}
+
+#endif /* LWIP_IPV4 && LWIP_ICMP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/igmp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/igmp.c
new file mode 100644
index 000000000..b655aa3a4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/igmp.c
@@ -0,0 +1,801 @@
+/**
+ * @file
+ * IGMP - Internet Group Management Protocol
+ *
+ * @defgroup igmp IGMP
+ * @ingroup ip4
+ * To be called from TCPIP thread
+ */
+
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+/*-------------------------------------------------------------
+Note 1)
+Although the rfc requires V1 AND V2 capability
+we will only support v2 since now V1 is very old (August 1989)
+V1 can be added if required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 2)
+A query for a specific group address (as opposed to ALLHOSTS)
+has now been implemented as I am unsure if it is required
+
+a debug print and statistic have been implemented to
+show this up.
+-------------------------------------------------------------
+-------------------------------------------------------------
+Note 3)
+The router alert rfc 2113 is implemented in outgoing packets
+but not checked rigorously incoming
+-------------------------------------------------------------
+Steve Reynolds
+------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * RFC 988  - Host extensions for IP multicasting                         - V0
+ * RFC 1054 - Host extensions for IP multicasting                         -
+ * RFC 1112 - Host extensions for IP multicasting                         - V1
+ * RFC 2236 - Internet Group Management Protocol, Version 2               - V2  <- this code is based on this RFC (it's the "de facto" standard)
+ * RFC 3376 - Internet Group Management Protocol, Version 3               - V3
+ * RFC 4604 - Using Internet Group Management Protocol Version 3...       - V3+
+ * RFC 2113 - IP Router Alert Option                                      -
+ *----------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Includes
+ *----------------------------------------------------------------------------*/
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/igmp.h"
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/stats.h"
+#include "lwip/prot/igmp.h"
+
+#include <string.h>
+
+static struct igmp_group *igmp_lookup_group(struct netif *ifp, const ip4_addr_t *addr);
+static err_t  igmp_remove_group(struct netif *netif, struct igmp_group *group);
+static void   igmp_timeout(struct netif *netif, struct igmp_group *group);
+static void   igmp_start_timer(struct igmp_group *group, u8_t max_time);
+static void   igmp_delaying_member(struct igmp_group *group, u8_t maxresp);
+static err_t  igmp_ip_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, struct netif *netif);
+static void   igmp_send(struct netif *netif, struct igmp_group *group, u8_t type);
+
+static ip4_addr_t     allsystems;
+static ip4_addr_t     allrouters;
+
+/**
+ * Initialize the IGMP module
+ */
+void
+igmp_init(void)
+{
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n"));
+
+  IP4_ADDR(&allsystems, 224, 0, 0, 1);
+  IP4_ADDR(&allrouters, 224, 0, 0, 2);
+}
+
+/**
+ * Start IGMP processing on interface
+ *
+ * @param netif network interface on which start IGMP processing
+ */
+err_t
+igmp_start(struct netif *netif)
+{
+  struct igmp_group *group;
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", (void *)netif));
+
+  group = igmp_lookup_group(netif, &allsystems);
+
+  if (group != NULL) {
+    group->group_state = IGMP_GROUP_IDLE_MEMBER;
+    group->use++;
+
+    /* Allow the igmp messages at the MAC level */
+    if (netif->igmp_mac_filter != NULL) {
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD "));
+      ip4_addr_debug_print_val(IGMP_DEBUG, allsystems);
+      LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif));
+      netif->igmp_mac_filter(netif, &allsystems, NETIF_ADD_MAC_FILTER);
+    }
+
+    return ERR_OK;
+  }
+
+  return ERR_MEM;
+}
+
+/**
+ * Stop IGMP processing on interface
+ *
+ * @param netif network interface on which stop IGMP processing
+ */
+err_t
+igmp_stop(struct netif *netif)
+{
+  struct igmp_group *group = netif_igmp_data(netif);
+
+  netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, NULL);
+
+  while (group != NULL) {
+    struct igmp_group *next = group->next; /* avoid use-after-free below */
+
+    /* disable the group at the MAC level */
+    if (netif->igmp_mac_filter != NULL) {
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL "));
+      ip4_addr_debug_print_val(IGMP_DEBUG, group->group_address);
+      LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif));
+      netif->igmp_mac_filter(netif, &(group->group_address), NETIF_DEL_MAC_FILTER);
+    }
+
+    /* free group */
+    memp_free(MEMP_IGMP_GROUP, group);
+
+    /* move to "next" */
+    group = next;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Report IGMP memberships for this interface
+ *
+ * @param netif network interface on which report IGMP memberships
+ */
+void
+igmp_report_groups(struct netif *netif)
+{
+  struct igmp_group *group = netif_igmp_data(netif);
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", (void *)netif));
+
+  /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */
+  if (group != NULL) {
+    group = group->next;
+  }
+
+  while (group != NULL) {
+    igmp_delaying_member(group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+    group = group->next;
+  }
+}
+
+/**
+ * Search for a group in the netif's igmp group list
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search for
+ * @return a struct igmp_group* if the group has been found,
+ *         NULL if the group wasn't found.
+ */
+struct igmp_group *
+igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr)
+{
+  struct igmp_group *group = netif_igmp_data(ifp);
+
+  while (group != NULL) {
+    if (ip4_addr_cmp(&(group->group_address), addr)) {
+      return group;
+    }
+    group = group->next;
+  }
+
+  /* to be clearer, we return NULL here instead of
+   * 'group' (which is also NULL at this point).
+   */
+  return NULL;
+}
+
+/**
+ * Search for a specific igmp group and create a new one if not found-
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ip address to search
+ * @return a struct igmp_group*,
+ *         NULL on memory error.
+ */
+static struct igmp_group *
+igmp_lookup_group(struct netif *ifp, const ip4_addr_t *addr)
+{
+  struct igmp_group *group;
+  struct igmp_group *list_head = netif_igmp_data(ifp);
+
+  /* Search if the group already exists */
+  group = igmp_lookfor_group(ifp, addr);
+  if (group != NULL) {
+    /* Group already exists. */
+    return group;
+  }
+
+  /* Group doesn't exist yet, create a new one */
+  group = (struct igmp_group *)memp_malloc(MEMP_IGMP_GROUP);
+  if (group != NULL) {
+    ip4_addr_set(&(group->group_address), addr);
+    group->timer              = 0; /* Not running */
+    group->group_state        = IGMP_GROUP_NON_MEMBER;
+    group->last_reporter_flag = 0;
+    group->use                = 0;
+
+    /* Ensure allsystems group is always first in list */
+    if (list_head == NULL) {
+      /* this is the first entry in linked list */
+      LWIP_ASSERT("igmp_lookup_group: first group must be allsystems",
+                  (ip4_addr_cmp(addr, &allsystems) != 0));
+      group->next = NULL;
+      netif_set_client_data(ifp, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, group);
+    } else {
+      /* append _after_ first entry */
+      LWIP_ASSERT("igmp_lookup_group: all except first group must not be allsystems",
+                  (ip4_addr_cmp(addr, &allsystems) == 0));
+      group->next = list_head->next;
+      list_head->next = group;
+    }
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group ? "" : "impossible to ")));
+  ip4_addr_debug_print(IGMP_DEBUG, addr);
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void *)ifp));
+
+  return group;
+}
+
+/**
+ * Remove a group from netif's igmp group list, but don't free it yet
+ *
+ * @param group the group to remove from the netif's igmp group list
+ * @return ERR_OK if group was removed from the list, an err_t otherwise
+ */
+static err_t
+igmp_remove_group(struct netif *netif, struct igmp_group *group)
+{
+  err_t err = ERR_OK;
+  struct igmp_group *tmp_group;
+
+  /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */
+  for (tmp_group = netif_igmp_data(netif); tmp_group != NULL; tmp_group = tmp_group->next) {
+    if (tmp_group->next == group) {
+      tmp_group->next = group->next;
+      break;
+    }
+  }
+  /* Group not found in netif's igmp group list */
+  if (tmp_group == NULL) {
+    err = ERR_ARG;
+  }
+
+  return err;
+}
+
+/**
+ * Called from ip_input() if a new IGMP packet is received.
+ *
+ * @param p received igmp packet, p->payload pointing to the igmp header
+ * @param inp network interface on which the packet was received
+ * @param dest destination ip address of the igmp packet
+ */
+void
+igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest)
+{
+  struct igmp_msg   *igmp;
+  struct igmp_group *group;
+  struct igmp_group *groupref;
+
+  IGMP_STATS_INC(igmp.recv);
+
+  /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */
+  if (p->len < IGMP_MINLEN) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.lenerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n"));
+    return;
+  }
+
+  LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from "));
+  ip4_addr_debug_print_val(IGMP_DEBUG, ip4_current_header()->src);
+  LWIP_DEBUGF(IGMP_DEBUG, (" to address "));
+  ip4_addr_debug_print_val(IGMP_DEBUG, ip4_current_header()->dest);
+  LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void *)inp));
+
+  /* Now calculate and check the checksum */
+  igmp = (struct igmp_msg *)p->payload;
+  if (inet_chksum(igmp, p->len)) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.chkerr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n"));
+    return;
+  }
+
+  /* Packet is ok so find an existing group */
+  group = igmp_lookfor_group(inp, dest); /* use the destination IP address of incoming packet */
+
+  /* If group can be found or create... */
+  if (!group) {
+    pbuf_free(p);
+    IGMP_STATS_INC(igmp.drop);
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n"));
+    return;
+  }
+
+  /* NOW ACT ON THE INCOMING MESSAGE TYPE... */
+  switch (igmp->igmp_msgtype) {
+    case IGMP_MEMB_QUERY:
+      /* IGMP_MEMB_QUERY to the "all systems" address ? */
+      if ((ip4_addr_cmp(dest, &allsystems)) && ip4_addr_isany(&igmp->igmp_group_address)) {
+        /* THIS IS THE GENERAL QUERY */
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+
+        if (igmp->igmp_maxresp == 0) {
+          IGMP_STATS_INC(igmp.rx_v1);
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n"));
+          igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR;
+        } else {
+          IGMP_STATS_INC(igmp.rx_general);
+        }
+
+        groupref = netif_igmp_data(inp);
+
+        /* Do not send messages on the all systems group address! */
+        /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */
+        if (groupref != NULL) {
+          groupref = groupref->next;
+        }
+
+        while (groupref) {
+          igmp_delaying_member(groupref, igmp->igmp_maxresp);
+          groupref = groupref->next;
+        }
+      } else {
+        /* IGMP_MEMB_QUERY to a specific group ? */
+        if (!ip4_addr_isany(&igmp->igmp_group_address)) {
+          LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group "));
+          ip4_addr_debug_print_val(IGMP_DEBUG, igmp->igmp_group_address);
+          if (ip4_addr_cmp(dest, &allsystems)) {
+            ip4_addr_t groupaddr;
+            LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+            /* we first need to re-look for the group since we used dest last time */
+            ip4_addr_copy(groupaddr, igmp->igmp_group_address);
+            group = igmp_lookfor_group(inp, &groupaddr);
+          } else {
+            LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp)));
+          }
+
+          if (group != NULL) {
+            IGMP_STATS_INC(igmp.rx_group);
+            igmp_delaying_member(group, igmp->igmp_maxresp);
+          } else {
+            IGMP_STATS_INC(igmp.drop);
+          }
+        } else {
+          IGMP_STATS_INC(igmp.proterr);
+        }
+      }
+      break;
+    case IGMP_V2_MEMB_REPORT:
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n"));
+      IGMP_STATS_INC(igmp.rx_report);
+      if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) {
+        /* This is on a specific group we have already looked up */
+        group->timer = 0; /* stopped */
+        group->group_state = IGMP_GROUP_IDLE_MEMBER;
+        group->last_reporter_flag = 0;
+      }
+      break;
+    default:
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n",
+                               igmp->igmp_msgtype, group->group_state, (void *)&group, (void *)inp));
+      IGMP_STATS_INC(igmp.proterr);
+      break;
+  }
+
+  pbuf_free(p);
+  return;
+}
+
+/**
+ * @ingroup igmp
+ * Join a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should join a new group
+ * @param groupaddr the ip address of the group which to join
+ * @return ERR_OK if group was joined on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr)
+{
+  err_t err = ERR_VAL; /* no matching interface */
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    /* Should we join this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip4_addr_isany(ifaddr) || ip4_addr_cmp(netif_ip4_addr(netif), ifaddr)))) {
+      err = igmp_joingroup_netif(netif, groupaddr);
+      if (err != ERR_OK) {
+        /* Return an error even if some network interfaces are joined */
+        /** @todo undo any other netif already joined */
+        return err;
+      }
+    }
+  }
+
+  return err;
+}
+
+/**
+ * @ingroup igmp
+ * Join a group on one network interface.
+ *
+ * @param netif the network interface which should join a new group
+ * @param groupaddr the ip address of the group which to join
+ * @return ERR_OK if group was joined on the netif, an err_t otherwise
+ */
+err_t
+igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr)
+{
+  struct igmp_group *group;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_joingroup_netif: attempt to join non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_joingroup_netif: attempt to join allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* make sure it is an igmp-enabled netif */
+  LWIP_ERROR("igmp_joingroup_netif: attempt to join on non-IGMP netif", netif->flags & NETIF_FLAG_IGMP, return ERR_VAL;);
+
+  /* find group or create a new one if not found */
+  group = igmp_lookup_group(netif, groupaddr);
+
+  if (group != NULL) {
+    /* This should create a new group, check the state to make sure */
+    if (group->group_state != IGMP_GROUP_NON_MEMBER) {
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: join to group not in state IGMP_GROUP_NON_MEMBER\n"));
+    } else {
+      /* OK - it was new group */
+      LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: join to new group: "));
+      ip4_addr_debug_print(IGMP_DEBUG, groupaddr);
+      LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+      /* If first use of the group, allow the group at the MAC level */
+      if ((group->use == 0) && (netif->igmp_mac_filter != NULL)) {
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: igmp_mac_filter(ADD "));
+        ip4_addr_debug_print(IGMP_DEBUG, groupaddr);
+        LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif));
+        netif->igmp_mac_filter(netif, groupaddr, NETIF_ADD_MAC_FILTER);
+      }
+
+      IGMP_STATS_INC(igmp.tx_join);
+      igmp_send(netif, group, IGMP_V2_MEMB_REPORT);
+
+      igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR);
+
+      /* Need to work out where this timer comes from */
+      group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+    }
+    /* Increment group use */
+    group->use++;
+    /* Join on this interface */
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: Not enough memory to join to group\n"));
+    return ERR_MEM;
+  }
+}
+
+/**
+ * @ingroup igmp
+ * Leave a group on one network interface.
+ *
+ * @param ifaddr ip address of the network interface which should leave a group
+ * @param groupaddr the ip address of the group which to leave
+ * @return ERR_OK if group was left on the netif(s), an err_t otherwise
+ */
+err_t
+igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr)
+{
+  err_t err = ERR_VAL; /* no matching interface */
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    /* Should we leave this interface ? */
+    if ((netif->flags & NETIF_FLAG_IGMP) && ((ip4_addr_isany(ifaddr) || ip4_addr_cmp(netif_ip4_addr(netif), ifaddr)))) {
+      err_t res = igmp_leavegroup_netif(netif, groupaddr);
+      if (err != ERR_OK) {
+        /* Store this result if we have not yet gotten a success */
+        err = res;
+      }
+    }
+  }
+
+  return err;
+}
+
+/**
+ * @ingroup igmp
+ * Leave a group on one network interface.
+ *
+ * @param netif the network interface which should leave a group
+ * @param groupaddr the ip address of the group which to leave
+ * @return ERR_OK if group was left on the netif, an err_t otherwise
+ */
+err_t
+igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr)
+{
+  struct igmp_group *group;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* make sure it is multicast address */
+  LWIP_ERROR("igmp_leavegroup_netif: attempt to leave non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;);
+  LWIP_ERROR("igmp_leavegroup_netif: attempt to leave allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;);
+
+  /* make sure it is an igmp-enabled netif */
+  LWIP_ERROR("igmp_leavegroup_netif: attempt to leave on non-IGMP netif", netif->flags & NETIF_FLAG_IGMP, return ERR_VAL;);
+
+  /* find group */
+  group = igmp_lookfor_group(netif, groupaddr);
+
+  if (group != NULL) {
+    /* Only send a leave if the flag is set according to the state diagram */
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: Leaving group: "));
+    ip4_addr_debug_print(IGMP_DEBUG, groupaddr);
+    LWIP_DEBUGF(IGMP_DEBUG, ("\n"));
+
+    /* If there is no other use of the group */
+    if (group->use <= 1) {
+      /* Remove the group from the list */
+      igmp_remove_group(netif, group);
+
+      /* If we are the last reporter for this group */
+      if (group->last_reporter_flag) {
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: sending leaving group\n"));
+        IGMP_STATS_INC(igmp.tx_leave);
+        igmp_send(netif, group, IGMP_LEAVE_GROUP);
+      }
+
+      /* Disable the group at the MAC level */
+      if (netif->igmp_mac_filter != NULL) {
+        LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: igmp_mac_filter(DEL "));
+        ip4_addr_debug_print(IGMP_DEBUG, groupaddr);
+        LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif));
+        netif->igmp_mac_filter(netif, groupaddr, NETIF_DEL_MAC_FILTER);
+      }
+
+      /* Free group struct */
+      memp_free(MEMP_IGMP_GROUP, group);
+    } else {
+      /* Decrement group use */
+      group->use--;
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: not member of group\n"));
+    return ERR_VAL;
+  }
+}
+
+/**
+ * The igmp timer function (both for NO_SYS=1 and =0)
+ * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default).
+ */
+void
+igmp_tmr(void)
+{
+  struct netif *netif;
+
+  NETIF_FOREACH(netif) {
+    struct igmp_group *group = netif_igmp_data(netif);
+
+    while (group != NULL) {
+      if (group->timer > 0) {
+        group->timer--;
+        if (group->timer == 0) {
+          igmp_timeout(netif, group);
+        }
+      }
+      group = group->next;
+    }
+  }
+}
+
+/**
+ * Called if a timeout for one group is reached.
+ * Sends a report for this group.
+ *
+ * @param group an igmp_group for which a timeout is reached
+ */
+static void
+igmp_timeout(struct netif *netif, struct igmp_group *group)
+{
+  /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group
+     (unless it is the allsystems group) */
+  if ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) &&
+      (!(ip4_addr_cmp(&(group->group_address), &allsystems)))) {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address "));
+    ip4_addr_debug_print_val(IGMP_DEBUG, group->group_address);
+    LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void *)netif));
+
+    group->group_state = IGMP_GROUP_IDLE_MEMBER;
+
+    IGMP_STATS_INC(igmp.tx_report);
+    igmp_send(netif, group, IGMP_V2_MEMB_REPORT);
+  }
+}
+
+/**
+ * Start a timer for an igmp group
+ *
+ * @param group the igmp_group for which to start a timer
+ * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with
+ *        every call to igmp_tmr())
+ */
+static void
+igmp_start_timer(struct igmp_group *group, u8_t max_time)
+{
+#ifdef LWIP_RAND
+  group->timer = (u16_t)(max_time > 2 ? (LWIP_RAND() % max_time) : 1);
+#else /* LWIP_RAND */
+  /* ATTENTION: use this only if absolutely necessary! */
+  group->timer = max_time / 2;
+#endif /* LWIP_RAND */
+
+  if (group->timer == 0) {
+    group->timer = 1;
+  }
+}
+
+/**
+ * Delaying membership report for a group if necessary
+ *
+ * @param group the igmp_group for which "delaying" membership report
+ * @param maxresp query delay
+ */
+static void
+igmp_delaying_member(struct igmp_group *group, u8_t maxresp)
+{
+  if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) ||
+      ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) &&
+       ((group->timer == 0) || (maxresp < group->timer)))) {
+    igmp_start_timer(group, maxresp);
+    group->group_state = IGMP_GROUP_DELAYING_MEMBER;
+  }
+}
+
+
+/**
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IP header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ */
+static err_t
+igmp_ip_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, struct netif *netif)
+{
+  /* This is the "router alert" option */
+  u16_t ra[2];
+  ra[0] = PP_HTONS(ROUTER_ALERT);
+  ra[1] = 0x0000; /* Router shall examine packet */
+  IGMP_STATS_INC(igmp.xmit);
+  return ip4_output_if_opt(p, src, dest, IGMP_TTL, 0, IP_PROTO_IGMP, netif, ra, ROUTER_ALERTLEN);
+}
+
+/**
+ * Send an igmp packet to a specific group.
+ *
+ * @param group the group to which to send the packet
+ * @param type the type of igmp packet to send
+ */
+static void
+igmp_send(struct netif *netif, struct igmp_group *group, u8_t type)
+{
+  struct pbuf     *p    = NULL;
+  struct igmp_msg *igmp = NULL;
+  ip4_addr_t   src  = *IP4_ADDR_ANY4;
+  ip4_addr_t  *dest = NULL;
+
+  /* IP header + "router alert" option + IGMP header */
+  p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM);
+
+  if (p) {
+    igmp = (struct igmp_msg *)p->payload;
+    LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg",
+                (p->len >= sizeof(struct igmp_msg)));
+    ip4_addr_copy(src, *netif_ip4_addr(netif));
+
+    if (type == IGMP_V2_MEMB_REPORT) {
+      dest = &(group->group_address);
+      ip4_addr_copy(igmp->igmp_group_address, group->group_address);
+      group->last_reporter_flag = 1; /* Remember we were the last to report */
+    } else {
+      if (type == IGMP_LEAVE_GROUP) {
+        dest = &allrouters;
+        ip4_addr_copy(igmp->igmp_group_address, group->group_address);
+      }
+    }
+
+    if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) {
+      igmp->igmp_msgtype  = type;
+      igmp->igmp_maxresp  = 0;
+      igmp->igmp_checksum = 0;
+      igmp->igmp_checksum = inet_chksum(igmp, IGMP_MINLEN);
+
+      igmp_ip_output_if(p, &src, dest, netif);
+    }
+
+    pbuf_free(p);
+  } else {
+    LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n"));
+    IGMP_STATS_INC(igmp.memerr);
+  }
+}
+
+#endif /* LWIP_IPV4 && LWIP_IGMP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4.c
new file mode 100644
index 000000000..26c26a91a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4.c
@@ -0,0 +1,1132 @@
+/**
+ * @file
+ * This is the IPv4 layer implementation for incoming and outgoing IP traffic.
+ *
+ * @see ip_frag.c
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4
+
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip4_frag.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/igmp.h"
+#include "lwip/priv/raw_priv.h"
+#include "lwip/udp.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/autoip.h"
+#include "lwip/stats.h"
+#include "lwip/prot/iana.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/** Set this to 0 in the rare case of wanting to call an extra function to
+ * generate the IP checksum (in contrast to calculating it on-the-fly). */
+#ifndef LWIP_INLINE_IP_CHKSUM
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define LWIP_INLINE_IP_CHKSUM   0
+#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+#define LWIP_INLINE_IP_CHKSUM   1
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+#endif
+
+#if LWIP_INLINE_IP_CHKSUM && CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP_INLINE  1
+#else
+#define CHECKSUM_GEN_IP_INLINE  0
+#endif
+
+#if LWIP_DHCP || defined(LWIP_IP_ACCEPT_UDP_PORT)
+#define IP_ACCEPT_LINK_LAYER_ADDRESSING 1
+
+/** Some defines for DHCP to let link-layer-addressed packets through while the
+ * netif is down.
+ * To use this in your own application/protocol, define LWIP_IP_ACCEPT_UDP_PORT(port)
+ * to return 1 if the port is accepted and 0 if the port is not accepted.
+ */
+#if LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT)
+/* accept DHCP client port and custom port */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (((port) == PP_NTOHS(LWIP_IANA_PORT_DHCP_CLIENT)) \
+         || (LWIP_IP_ACCEPT_UDP_PORT(port)))
+#elif defined(LWIP_IP_ACCEPT_UDP_PORT) /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */
+/* accept custom port only */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (LWIP_IP_ACCEPT_UDP_PORT(port))
+#else /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */
+/* accept DHCP client port only */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) ((port) == PP_NTOHS(LWIP_IANA_PORT_DHCP_CLIENT))
+#endif /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */
+
+#else /* LWIP_DHCP */
+#define IP_ACCEPT_LINK_LAYER_ADDRESSING 0
+#endif /* LWIP_DHCP */
+
+/** The IP header ID of the next outgoing IP packet */
+static u16_t ip_id;
+
+#if LWIP_MULTICAST_TX_OPTIONS
+/** The default netif used for multicast */
+static struct netif *ip4_default_multicast_netif;
+
+/**
+ * @ingroup ip4
+ * Set a default netif for IPv4 multicast. */
+void
+ip4_set_default_multicast_netif(struct netif *default_multicast_netif)
+{
+  ip4_default_multicast_netif = default_multicast_netif;
+}
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+/**
+ * Source based IPv4 routing must be fully implemented in
+ * LWIP_HOOK_IP4_ROUTE_SRC(). This function only provides the parameters.
+ */
+struct netif *
+ip4_route_src(const ip4_addr_t *src, const ip4_addr_t *dest)
+{
+  if (src != NULL) {
+    /* when src==NULL, the hook is called from ip4_route(dest) */
+    struct netif *netif = LWIP_HOOK_IP4_ROUTE_SRC(src, dest);
+    if (netif != NULL) {
+      return netif;
+    }
+  }
+  return ip4_route(dest);
+}
+#endif /* LWIP_HOOK_IP4_ROUTE_SRC */
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ *
+ * @param dest the destination IP address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif *
+ip4_route(const ip4_addr_t *dest)
+{
+#if !LWIP_SINGLE_NETIF
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_MULTICAST_TX_OPTIONS
+  /* Use administratively selected interface for multicast by default */
+  if (ip4_addr_ismulticast(dest) && ip4_default_multicast_netif) {
+    return ip4_default_multicast_netif;
+  }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+  /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
+  LWIP_UNUSED_ARG(dest);
+
+  /* iterate through netifs */
+  NETIF_FOREACH(netif) {
+    /* is the netif up, does it have a link and a valid address? */
+    if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+      /* network mask matches? */
+      if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
+        /* return netif on which to forward IP packet */
+        return netif;
+      }
+      /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
+      if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
+        /* return netif on which to forward IP packet */
+        return netif;
+      }
+    }
+  }
+
+#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF
+  /* loopif is disabled, looopback traffic is passed through any netif */
+  if (ip4_addr_isloopback(dest)) {
+    /* don't check for link on loopback traffic */
+    if (netif_default != NULL && netif_is_up(netif_default)) {
+      return netif_default;
+    }
+    /* default netif is not up, just use any netif for loopback traffic */
+    NETIF_FOREACH(netif) {
+      if (netif_is_up(netif)) {
+        return netif;
+      }
+    }
+    return NULL;
+  }
+#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
+
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+  netif = LWIP_HOOK_IP4_ROUTE_SRC(NULL, dest);
+  if (netif != NULL) {
+    return netif;
+  }
+#elif defined(LWIP_HOOK_IP4_ROUTE)
+  netif = LWIP_HOOK_IP4_ROUTE(dest);
+  if (netif != NULL) {
+    return netif;
+  }
+#endif
+#endif /* !LWIP_SINGLE_NETIF */
+
+  if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
+      ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
+    /* No matching netif found and default netif is not usable.
+       If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    MIB2_STATS_INC(mib2.ipoutnoroutes);
+    return NULL;
+  }
+
+  return netif_default;
+}
+
+#if IP_FORWARD
+/**
+ * Determine whether an IP address is in a reserved set of addresses
+ * that may not be forwarded, or whether datagrams to that destination
+ * may be forwarded.
+ * @param p the packet to forward
+ * @return 1: can forward 0: discard
+ */
+static int
+ip4_canforward(struct pbuf *p)
+{
+  u32_t addr = lwip_htonl(ip4_addr_get_u32(ip4_current_dest_addr()));
+
+#ifdef LWIP_HOOK_IP4_CANFORWARD
+  int ret = LWIP_HOOK_IP4_CANFORWARD(p, addr);
+  if (ret >= 0) {
+    return ret;
+  }
+#endif /* LWIP_HOOK_IP4_CANFORWARD */
+
+  if (p->flags & PBUF_FLAG_LLBCAST) {
+    /* don't route link-layer broadcasts */
+    return 0;
+  }
+  if ((p->flags & PBUF_FLAG_LLMCAST) || IP_MULTICAST(addr)) {
+    /* don't route link-layer multicasts (use LWIP_HOOK_IP4_CANFORWARD instead) */
+    return 0;
+  }
+  if (IP_EXPERIMENTAL(addr)) {
+    return 0;
+  }
+  if (IP_CLASSA(addr)) {
+    u32_t net = addr & IP_CLASSA_NET;
+    if ((net == 0) || (net == ((u32_t)IP_LOOPBACKNET << IP_CLASSA_NSHIFT))) {
+      /* don't route loopback packets */
+      return 0;
+    }
+  }
+  return 1;
+}
+
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ *
+ * @param p the packet to forward (p->payload points to IP header)
+ * @param iphdr the IP header of the input packet
+ * @param inp the netif on which this packet was received
+ */
+static void
+ip4_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  LWIP_UNUSED_ARG(inp);
+
+  if (!ip4_canforward(p)) {
+    goto return_noroute;
+  }
+
+  /* RFC3927 2.7: do not forward link-local addresses */
+  if (ip4_addr_islinklocal(ip4_current_dest_addr())) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: not forwarding LLA %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()),
+                           ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr())));
+    goto return_noroute;
+  }
+
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip4_route_src(ip4_current_src_addr(), ip4_current_dest_addr());
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: no forwarding route for %"U16_F".%"U16_F".%"U16_F".%"U16_F" found\n",
+                           ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()),
+                           ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr())));
+    /* @todo: send ICMP_DUR_NET? */
+    goto return_noroute;
+  }
+#if !IP_FORWARD_ALLOW_TX_ON_RX_NETIF
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: not bouncing packets back on incoming interface.\n"));
+    goto return_noroute;
+  }
+#endif /* IP_FORWARD_ALLOW_TX_ON_RX_NETIF */
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    MIB2_STATS_INC(mib2.ipinhdrerrors);
+#if LWIP_ICMP
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+#endif /* LWIP_ICMP */
+    return;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= PP_HTONS(0xffffU - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, (u16_t)(IPH_CHKSUM(iphdr) + PP_HTONS(0x100) + 1));
+  } else {
+    IPH_CHKSUM_SET(iphdr, (u16_t)(IPH_CHKSUM(iphdr) + PP_HTONS(0x100)));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: forwarding packet to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                         ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()),
+                         ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr())));
+
+  IP_STATS_INC(ip.fw);
+  MIB2_STATS_INC(mib2.ipforwdatagrams);
+  IP_STATS_INC(ip.xmit);
+
+  PERF_STOP("ip4_forward");
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu)) {
+    if ((IPH_OFFSET(iphdr) & PP_NTOHS(IP_DF)) == 0) {
+#if IP_FRAG
+      ip4_frag(p, netif, ip4_current_dest_addr());
+#else /* IP_FRAG */
+      /* @todo: send ICMP Destination Unreachable code 13 "Communication administratively prohibited"? */
+#endif /* IP_FRAG */
+    } else {
+#if LWIP_ICMP
+      /* send ICMP Destination Unreachable code 4: "Fragmentation Needed and DF Set" */
+      icmp_dest_unreach(p, ICMP_DUR_FRAG);
+#endif /* LWIP_ICMP */
+    }
+    return;
+  }
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, ip4_current_dest_addr());
+  return;
+return_noroute:
+  MIB2_STATS_INC(mib2.ipoutnoroutes);
+}
+#endif /* IP_FORWARD */
+
+/** Return true if the current input packet should be accepted on this netif */
+static int
+ip4_input_accept(struct netif *netif)
+{
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
+                         ip4_addr_get_u32(ip4_current_dest_addr()), ip4_addr_get_u32(netif_ip4_addr(netif)),
+                         ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
+                         ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
+                         ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
+
+  /* interface is up and configured? */
+  if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
+    /* unicast to this interface address? */
+    if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
+        /* or broadcast on this interface network address? */
+        ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
+#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF
+        || (ip4_addr_get_u32(ip4_current_dest_addr()) == PP_HTONL(IPADDR_LOOPBACK))
+#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
+       ) {
+      LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
+                             netif->name[0], netif->name[1]));
+      /* accept on this netif */
+      return 1;
+    }
+#if LWIP_AUTOIP
+    /* connections to link-local addresses must persist after changing
+        the netif's address (RFC3927 ch. 1.9) */
+    if (autoip_accept_packet(netif, ip4_current_dest_addr())) {
+      LWIP_DEBUGF(IP_DEBUG, ("ip4_input: LLA packet accepted on interface %c%c\n",
+                             netif->name[0], netif->name[1]));
+      /* accept on this netif */
+      return 1;
+    }
+#endif /* LWIP_AUTOIP */
+  }
+  return 0;
+}
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ *
+ * @param p the received IP packet (p->payload points to IP header)
+ * @param inp the netif on which this packet was received
+ * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
+ *         processed, but currently always returns ERR_OK)
+ */
+err_t
+ip4_input(struct pbuf *p, struct netif *inp)
+{
+  const struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdr_hlen;
+  u16_t iphdr_len;
+#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP
+  int check_ip_src = 1;
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP */
+#if LWIP_RAW
+  raw_input_state_t raw_status;
+#endif /* LWIP_RAW */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  IP_STATS_INC(ip.recv);
+  MIB2_STATS_INC(mib2.ipinreceives);
+
+  /* identify the IP header */
+  iphdr = (struct ip_hdr *)p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
+    ip4_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    MIB2_STATS_INC(mib2.ipinhdrerrors);
+    return ERR_OK;
+  }
+
+#ifdef LWIP_HOOK_IP4_INPUT
+  if (LWIP_HOOK_IP4_INPUT(p, inp)) {
+    /* the packet has been eaten */
+    return ERR_OK;
+  }
+#endif
+
+  /* obtain IP header length in bytes */
+  iphdr_hlen = IPH_HL_BYTES(iphdr);
+  /* obtain ip length in bytes */
+  iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
+
+  /* Trim pbuf. This is especially required for packets < 60 bytes. */
+  if (iphdr_len < p->tot_len) {
+    pbuf_realloc(p, iphdr_len);
+  }
+
+  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
+  if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
+    if (iphdr_hlen < IP_HLEN) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("ip4_input: short IP header (%"U16_F" bytes) received, IP packet dropped\n", iphdr_hlen));
+    }
+    if (iphdr_hlen > p->len) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n",
+                   iphdr_hlen, p->len));
+    }
+    if (iphdr_len > p->tot_len) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
+                   iphdr_len, p->tot_len));
+    }
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    MIB2_STATS_INC(mib2.ipindiscards);
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_IP) {
+    if (inet_chksum(iphdr, iphdr_hlen) != 0) {
+
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                  ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen)));
+      ip4_debug_print(p);
+      pbuf_free(p);
+      IP_STATS_INC(ip.chkerr);
+      IP_STATS_INC(ip.drop);
+      MIB2_STATS_INC(mib2.ipinhdrerrors);
+      return ERR_OK;
+    }
+  }
+#endif
+
+  /* copy IP addresses to aligned ip_addr_t */
+  ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
+  ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
+#if LWIP_IGMP
+    if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, ip4_current_dest_addr()))) {
+      /* IGMP snooping switches need 0.0.0.0 to be allowed as source address (RFC 4541) */
+      ip4_addr_t allsystems;
+      IP4_ADDR(&allsystems, 224, 0, 0, 1);
+      if (ip4_addr_cmp(ip4_current_dest_addr(), &allsystems) &&
+          ip4_addr_isany(ip4_current_src_addr())) {
+        check_ip_src = 0;
+      }
+      netif = inp;
+    } else {
+      netif = NULL;
+    }
+#else /* LWIP_IGMP */
+    if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
+      netif = inp;
+    } else {
+      netif = NULL;
+    }
+#endif /* LWIP_IGMP */
+  } else {
+    /* start trying with inp. if that's not acceptable, start walking the
+       list of configured netifs. */
+    if (ip4_input_accept(inp)) {
+      netif = inp;
+    } else {
+      netif = NULL;
+#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
+      /* Packets sent to the loopback address must not be accepted on an
+       * interface that does not have the loopback address assigned to it,
+       * unless a non-loopback interface is used for loopback traffic. */
+      if (!ip4_addr_isloopback(ip4_current_dest_addr()))
+#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
+      {
+#if !LWIP_SINGLE_NETIF
+        NETIF_FOREACH(netif) {
+          if (netif == inp) {
+            /* we checked that before already */
+            continue;
+          }
+          if (ip4_input_accept(netif)) {
+            break;
+          }
+        }
+#endif /* !LWIP_SINGLE_NETIF */
+      }
+    }
+  }
+
+#if IP_ACCEPT_LINK_LAYER_ADDRESSING
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   *
+   * If you want to accept private broadcast communication while a netif is down,
+   * define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.:
+   *
+   * #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345))
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen);
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n",
+                                              lwip_ntohs(udphdr->dest)));
+      if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n"));
+        netif = inp;
+        check_ip_src = 0;
+      }
+    }
+  }
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+
+  /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
+#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING
+  if (check_ip_src
+#if IP_ACCEPT_LINK_LAYER_ADDRESSING
+      /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
+      && !ip4_addr_isany_val(*ip4_current_src_addr())
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+     )
+#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
+  {
+    if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
+        (ip4_addr_ismulticast(ip4_current_src_addr()))) {
+      /* packet source is not valid */
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
+      /* free (drop) packet pbufs */
+      pbuf_free(p);
+      IP_STATS_INC(ip.drop);
+      MIB2_STATS_INC(mib2.ipinaddrerrors);
+      MIB2_STATS_INC(mib2.ipindiscards);
+      return ERR_OK;
+    }
+  }
+
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip4_forward(p, (struct ip_hdr *)p->payload, inp);
+    } else
+#endif /* IP_FORWARD */
+    {
+      IP_STATS_INC(ip.drop);
+      MIB2_STATS_INC(mib2.ipinaddrerrors);
+      MIB2_STATS_INC(mib2.ipindiscards);
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
+                           lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
+    /* reassemble the packet*/
+    p = ip4_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = (const struct ip_hdr *)p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
+                lwip_ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    MIB2_STATS_INC(mib2.ipinunknownprotos);
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */
+
+#if LWIP_IGMP
+  /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */
+  if ((iphdr_hlen > IP_HLEN) &&  (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) {
+#else
+  if (iphdr_hlen > IP_HLEN) {
+#endif /* LWIP_IGMP */
+    LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    /* unsupported protocol feature */
+    MIB2_STATS_INC(mib2.ipinunknownprotos);
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS_ALLOWED == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
+  ip4_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  ip_data.current_netif = netif;
+  ip_data.current_input_netif = inp;
+  ip_data.current_ip4_header = iphdr;
+  ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  raw_status = raw_input(p, inp);
+  if (raw_status != RAW_INPUT_EATEN)
+#endif /* LWIP_RAW */
+  {
+    pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
+
+    switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+      case IP_PROTO_UDP:
+#if LWIP_UDPLITE
+      case IP_PROTO_UDPLITE:
+#endif /* LWIP_UDPLITE */
+        MIB2_STATS_INC(mib2.ipindelivers);
+        udp_input(p, inp);
+        break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+      case IP_PROTO_TCP:
+        MIB2_STATS_INC(mib2.ipindelivers);
+        tcp_input(p, inp);
+        break;
+#endif /* LWIP_TCP */
+#if LWIP_ICMP
+      case IP_PROTO_ICMP:
+        MIB2_STATS_INC(mib2.ipindelivers);
+        icmp_input(p, inp);
+        break;
+#endif /* LWIP_ICMP */
+#if LWIP_IGMP
+      case IP_PROTO_IGMP:
+        igmp_input(p, inp, ip4_current_dest_addr());
+        break;
+#endif /* LWIP_IGMP */
+      default:
+#if LWIP_RAW
+        if (raw_status == RAW_INPUT_DELIVERED) {
+          MIB2_STATS_INC(mib2.ipindelivers);
+        } else
+#endif /* LWIP_RAW */
+        {
+#if LWIP_ICMP
+          /* send ICMP destination protocol unreachable unless is was a broadcast */
+          if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
+              !ip4_addr_ismulticast(ip4_current_dest_addr())) {
+            pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
+            icmp_dest_unreach(p, ICMP_DUR_PROTO);
+          }
+#endif /* LWIP_ICMP */
+
+          LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", (u16_t)IPH_PROTO(iphdr)));
+
+          IP_STATS_INC(ip.proterr);
+          IP_STATS_INC(ip.drop);
+          MIB2_STATS_INC(mib2.ipinunknownprotos);
+        }
+        pbuf_free(p);
+        break;
+    }
+  }
+
+  /* @todo: this is not really necessary... */
+  ip_data.current_netif = NULL;
+  ip_data.current_input_netif = NULL;
+  ip_data.current_ip4_header = NULL;
+  ip_data.current_ip_header_tot_len = 0;
+  ip4_addr_set_any(ip4_current_src_addr());
+  ip4_addr_set_any(ip4_current_dest_addr());
+
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ * If the destination IP address is LWIP_IP_HDRINCL, p is assumed to already
+ * include an IP header and p->payload points to it instead of the data.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IP header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IP/LINK headers
+ *         returns errors returned by netif->output
+ *
+ * @note ip_id: RFC791 "some host may be able to simply use
+ *  unique identifiers independent of destination"
+ */
+err_t
+ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+              u8_t ttl, u8_t tos,
+              u8_t proto, struct netif *netif)
+{
+#if IP_OPTIONS_SEND
+  return ip4_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0);
+}
+
+/**
+ * Same as ip_output_if() but with the possibility to include IP options:
+ *
+ * @ param ip_options pointer to the IP options, copied into the IP header
+ * @ param optlen length of ip_options
+ */
+err_t
+ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+                  u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+                  u16_t optlen)
+{
+#endif /* IP_OPTIONS_SEND */
+  const ip4_addr_t *src_used = src;
+  if (dest != LWIP_IP_HDRINCL) {
+    if (ip4_addr_isany(src)) {
+      src_used = netif_ip4_addr(netif);
+    }
+  }
+
+#if IP_OPTIONS_SEND
+  return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
+                               ip_options, optlen);
+#else /* IP_OPTIONS_SEND */
+  return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
+#endif /* IP_OPTIONS_SEND */
+}
+
+/**
+ * Same as ip_output_if() but 'src' address is not replaced by netif address
+ * when it is 'any'.
+ */
+err_t
+ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+                  u8_t ttl, u8_t tos,
+                  u8_t proto, struct netif *netif)
+{
+#if IP_OPTIONS_SEND
+  return ip4_output_if_opt_src(p, src, dest, ttl, tos, proto, netif, NULL, 0);
+}
+
+/**
+ * Same as ip_output_if_opt() but 'src' address is not replaced by netif address
+ * when it is 'any'.
+ */
+err_t
+ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+                      u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+                      u16_t optlen)
+{
+#endif /* IP_OPTIONS_SEND */
+  struct ip_hdr *iphdr;
+  ip4_addr_t dest_addr;
+#if CHECKSUM_GEN_IP_INLINE
+  u32_t chk_sum = 0;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+
+  MIB2_STATS_INC(mib2.ipoutrequests);
+
+  /* Should the IP header be generated or is it already included in p? */
+  if (dest != LWIP_IP_HDRINCL) {
+    u16_t ip_hlen = IP_HLEN;
+#if IP_OPTIONS_SEND
+    u16_t optlen_aligned = 0;
+    if (optlen != 0) {
+#if CHECKSUM_GEN_IP_INLINE
+      int i;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+      if (optlen > (IP_HLEN_MAX - IP_HLEN)) {
+        /* optlen too long */
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output_if_opt: optlen too long\n"));
+        IP_STATS_INC(ip.err);
+        MIB2_STATS_INC(mib2.ipoutdiscards);
+        return ERR_VAL;
+      }
+      /* round up to a multiple of 4 */
+      optlen_aligned = (u16_t)((optlen + 3) & ~3);
+      ip_hlen = (u16_t)(ip_hlen + optlen_aligned);
+      /* First write in the IP options */
+      if (pbuf_add_header(p, optlen_aligned)) {
+        LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output_if_opt: not enough room for IP options in pbuf\n"));
+        IP_STATS_INC(ip.err);
+        MIB2_STATS_INC(mib2.ipoutdiscards);
+        return ERR_BUF;
+      }
+      MEMCPY(p->payload, ip_options, optlen);
+      if (optlen < optlen_aligned) {
+        /* zero the remaining bytes */
+        memset(((char *)p->payload) + optlen, 0, (size_t)(optlen_aligned - optlen));
+      }
+#if CHECKSUM_GEN_IP_INLINE
+      for (i = 0; i < optlen_aligned / 2; i++) {
+        chk_sum += ((u16_t *)p->payload)[i];
+      }
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    }
+#endif /* IP_OPTIONS_SEND */
+    /* generate IP header */
+    if (pbuf_add_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      MIB2_STATS_INC(mib2.ipoutdiscards);
+      return ERR_BUF;
+    }
+
+    iphdr = (struct ip_hdr *)p->payload;
+    LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
+                (p->len >= sizeof(struct ip_hdr)));
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += PP_NTOHS(proto | (ttl << 8));
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+    /* dest cannot be NULL here */
+    ip4_addr_copy(iphdr->dest, *dest);
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
+    chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+
+    IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
+    IPH_TOS_SET(iphdr, tos);
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_len;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    IPH_OFFSET_SET(iphdr, 0);
+    IPH_ID_SET(iphdr, lwip_htons(ip_id));
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += iphdr->_id;
+#endif /* CHECKSUM_GEN_IP_INLINE */
+    ++ip_id;
+
+    if (src == NULL) {
+      ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
+    } else {
+      /* src cannot be NULL here */
+      ip4_addr_copy(iphdr->src, *src);
+    }
+
+#if CHECKSUM_GEN_IP_INLINE
+    chk_sum += ip4_addr_get_u32(&iphdr->src) & 0xFFFF;
+    chk_sum += ip4_addr_get_u32(&iphdr->src) >> 16;
+    chk_sum = (chk_sum >> 16) + (chk_sum & 0xFFFF);
+    chk_sum = (chk_sum >> 16) + chk_sum;
+    chk_sum = ~chk_sum;
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) {
+      iphdr->_chksum = (u16_t)chk_sum; /* network order */
+    }
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+    else {
+      IPH_CHKSUM_SET(iphdr, 0);
+    }
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
+#else /* CHECKSUM_GEN_IP_INLINE */
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) {
+      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen));
+    }
+#endif /* CHECKSUM_GEN_IP */
+#endif /* CHECKSUM_GEN_IP_INLINE */
+  } else {
+    /* IP header already included in p */
+    if (p->len < IP_HLEN) {
+      LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
+      IP_STATS_INC(ip.err);
+      MIB2_STATS_INC(mib2.ipoutdiscards);
+      return ERR_BUF;
+    }
+    iphdr = (struct ip_hdr *)p->payload;
+    ip4_addr_copy(dest_addr, iphdr->dest);
+    dest = &dest_addr;
+  }
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], (u16_t)netif->num));
+  ip4_debug_print(p);
+
+#if ENABLE_LOOPBACK
+  if (ip4_addr_cmp(dest, netif_ip4_addr(netif))
+#if !LWIP_HAVE_LOOPIF
+      || ip4_addr_isloopback(dest)
+#endif /* !LWIP_HAVE_LOOPIF */
+     ) {
+    /* Packet to self, enqueue it for loopback */
+    LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()"));
+    return netif_loop_output(netif, p);
+  }
+#if LWIP_MULTICAST_TX_OPTIONS
+  if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) {
+    netif_loop_output(netif, p);
+  }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+#endif /* ENABLE_LOOPBACK */
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu)) {
+    return ip4_frag(p, netif, dest);
+  }
+#endif /* IP_FRAG */
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IP header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+           u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+
+  if ((netif = ip4_route_src(src, dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip4_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  return ip4_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if LWIP_NETIF_USE_HINTS
+/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint
+ *  before calling ip_output_if.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IP header and p->payload points to that IP header)
+ * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the
+ *         IP  address of the netif used to send is used as source address)
+ * @param dest the destination IP address to send the packet to
+ * @param ttl the TTL value to be set in the IP header
+ * @param tos the TOS value to be set in the IP header
+ * @param proto the PROTOCOL to be set in the IP header
+ * @param netif_hint netif output hint pointer set to netif->hint before
+ *        calling ip_output_if()
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+                  u8_t ttl, u8_t tos, u8_t proto, struct netif_hint *netif_hint)
+{
+  struct netif *netif;
+  err_t err;
+
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+
+  if ((netif = ip4_route_src(src, dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip4_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
+    IP_STATS_INC(ip.rterr);
+    return ERR_RTE;
+  }
+
+  NETIF_SET_HINTS(netif, netif_hint);
+  err = ip4_output_if(p, src, dest, ttl, tos, proto, netif);
+  NETIF_RESET_HINTS(netif);
+
+  return err;
+}
+#endif /* LWIP_NETIF_USE_HINTS*/
+
+#if IP_DEBUG
+/* Print an IP header by using LWIP_DEBUGF
+ * @param p an IP packet, p->payload pointing to the IP header
+ */
+void
+ip4_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
+                         (u16_t)IPH_V(iphdr),
+                         (u16_t)IPH_HL(iphdr),
+                         (u16_t)IPH_TOS(iphdr),
+                         lwip_ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
+                         lwip_ntohs(IPH_ID(iphdr)),
+                         (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 15 & 1),
+                         (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 14 & 1),
+                         (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 13 & 1),
+                         (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
+                         (u16_t)IPH_TTL(iphdr),
+                         (u16_t)IPH_PROTO(iphdr),
+                         lwip_ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
+                         ip4_addr1_16_val(iphdr->src),
+                         ip4_addr2_16_val(iphdr->src),
+                         ip4_addr3_16_val(iphdr->src),
+                         ip4_addr4_16_val(iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
+                         ip4_addr1_16_val(iphdr->dest),
+                         ip4_addr2_16_val(iphdr->dest),
+                         ip4_addr3_16_val(iphdr->dest),
+                         ip4_addr4_16_val(iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
+#endif /* LWIP_IPV4 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4_addr.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4_addr.c
new file mode 100644
index 000000000..33204d114
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4_addr.c
@@ -0,0 +1,321 @@
+/**
+ * @file
+ * This is the IPv4 address tools implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+/* used by IP4_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const ip_addr_t ip_addr_any = IPADDR4_INIT(IPADDR_ANY);
+const ip_addr_t ip_addr_broadcast = IPADDR4_INIT(IPADDR_BROADCAST);
+
+/**
+ * Determine if an address is a broadcast address on a network interface
+ *
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ */
+u8_t
+ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
+{
+  ip4_addr_t ipaddr;
+  ip4_addr_set_u32(&ipaddr, addr);
+
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((~addr == IPADDR_ANY) ||
+      (addr == IPADDR_ANY)) {
+    return 1;
+    /* no broadcast support on this network interface? */
+  } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+    /* address matches network interface address exactly? => no broadcast */
+  } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
+    return 0;
+    /*  on the same (sub) network... */
+  } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
+             /* ...and host identifier bits are all ones? =>... */
+             && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
+                 (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
+    /* => network broadcast address */
+    return 1;
+  } else {
+    return 0;
+  }
+}
+
+/** Checks if a netmask is valid (starting with ones, then only zeros)
+ *
+ * @param netmask the IPv4 netmask to check (in network byte order!)
+ * @return 1 if the netmask is valid, 0 if it is not
+ */
+u8_t
+ip4_addr_netmask_valid(u32_t netmask)
+{
+  u32_t mask;
+  u32_t nm_hostorder = lwip_htonl(netmask);
+
+  /* first, check for the first zero */
+  for (mask = 1UL << 31 ; mask != 0; mask >>= 1) {
+    if ((nm_hostorder & mask) == 0) {
+      break;
+    }
+  }
+  /* then check that there is no one */
+  for (; mask != 0; mask >>= 1) {
+    if ((nm_hostorder & mask) != 0) {
+      /* there is a one after the first zero -> invalid */
+      return 0;
+    }
+  }
+  /* no one after the first zero -> valid */
+  return 1;
+}
+
+/**
+ * Ascii internet address interpretation routine.
+ * The value returned is in network order.
+ *
+ * @param cp IP address in ascii representation (e.g. "127.0.0.1")
+ * @return ip address in network order
+ */
+u32_t
+ipaddr_addr(const char *cp)
+{
+  ip4_addr_t val;
+
+  if (ip4addr_aton(cp, &val)) {
+    return ip4_addr_get_u32(&val);
+  }
+  return (IPADDR_NONE);
+}
+
+/**
+ * Check whether "cp" is a valid ascii representation
+ * of an Internet address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ * This replaces inet_addr, the return value from which
+ * cannot distinguish between failure and a local broadcast address.
+ *
+ * @param cp IP address in ascii representation (e.g. "127.0.0.1")
+ * @param addr pointer to which to save the ip address in network order
+ * @return 1 if cp could be converted to addr, 0 on failure
+ */
+int
+ip4addr_aton(const char *cp, ip4_addr_t *addr)
+{
+  u32_t val;
+  u8_t base;
+  char c;
+  u32_t parts[4];
+  u32_t *pp = parts;
+
+  c = *cp;
+  for (;;) {
+    /*
+     * Collect number up to ``.''.
+     * Values are specified as for C:
+     * 0x=hex, 0=octal, 1-9=decimal.
+     */
+    if (!lwip_isdigit(c)) {
+      return 0;
+    }
+    val = 0;
+    base = 10;
+    if (c == '0') {
+      c = *++cp;
+      if (c == 'x' || c == 'X') {
+        base = 16;
+        c = *++cp;
+      } else {
+        base = 8;
+      }
+    }
+    for (;;) {
+      if (lwip_isdigit(c)) {
+        val = (val * base) + (u32_t)(c - '0');
+        c = *++cp;
+      } else if (base == 16 && lwip_isxdigit(c)) {
+        val = (val << 4) | (u32_t)(c + 10 - (lwip_islower(c) ? 'a' : 'A'));
+        c = *++cp;
+      } else {
+        break;
+      }
+    }
+    if (c == '.') {
+      /*
+       * Internet format:
+       *  a.b.c.d
+       *  a.b.c   (with c treated as 16 bits)
+       *  a.b (with b treated as 24 bits)
+       */
+      if (pp >= parts + 3) {
+        return 0;
+      }
+      *pp++ = val;
+      c = *++cp;
+    } else {
+      break;
+    }
+  }
+  /*
+   * Check for trailing characters.
+   */
+  if (c != '\0' && !lwip_isspace(c)) {
+    return 0;
+  }
+  /*
+   * Concoct the address according to
+   * the number of parts specified.
+   */
+  switch (pp - parts + 1) {
+
+    case 0:
+      return 0;       /* initial nondigit */
+
+    case 1:             /* a -- 32 bits */
+      break;
+
+    case 2:             /* a.b -- 8.24 bits */
+      if (val > 0xffffffUL) {
+        return 0;
+      }
+      if (parts[0] > 0xff) {
+        return 0;
+      }
+      val |= parts[0] << 24;
+      break;
+
+    case 3:             /* a.b.c -- 8.8.16 bits */
+      if (val > 0xffff) {
+        return 0;
+      }
+      if ((parts[0] > 0xff) || (parts[1] > 0xff)) {
+        return 0;
+      }
+      val |= (parts[0] << 24) | (parts[1] << 16);
+      break;
+
+    case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+      if (val > 0xff) {
+        return 0;
+      }
+      if ((parts[0] > 0xff) || (parts[1] > 0xff) || (parts[2] > 0xff)) {
+        return 0;
+      }
+      val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+      break;
+    default:
+      LWIP_ASSERT("unhandled", 0);
+      break;
+  }
+  if (addr) {
+    ip4_addr_set_u32(addr, lwip_htonl(val));
+  }
+  return 1;
+}
+
+/**
+ * Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ *
+ * @param addr ip address in network order to convert
+ * @return pointer to a global static (!) buffer that holds the ASCII
+ *         representation of addr
+ */
+char *
+ip4addr_ntoa(const ip4_addr_t *addr)
+{
+  static char str[IP4ADDR_STRLEN_MAX];
+  return ip4addr_ntoa_r(addr, str, IP4ADDR_STRLEN_MAX);
+}
+
+/**
+ * Same as ip4addr_ntoa, but reentrant since a user-supplied buffer is used.
+ *
+ * @param addr ip address in network order to convert
+ * @param buf target buffer where the string is stored
+ * @param buflen length of buf
+ * @return either pointer to buf which now holds the ASCII
+ *         representation of addr or NULL if buf was too small
+ */
+char *
+ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen)
+{
+  u32_t s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+  int len = 0;
+
+  s_addr = ip4_addr_get_u32(addr);
+
+  rp = buf;
+  ap = (u8_t *)&s_addr;
+  for (n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = (char)('0' + rem);
+    } while (*ap);
+    while (i--) {
+      if (len++ >= buflen) {
+        return NULL;
+      }
+      *rp++ = inv[i];
+    }
+    if (len++ >= buflen) {
+      return NULL;
+    }
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return buf;
+}
+
+#endif /* LWIP_IPV4 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4_frag.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4_frag.c
new file mode 100644
index 000000000..a445530e0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv4/ip4_frag.c
@@ -0,0 +1,894 @@
+/**
+ * @file
+ * This is the IPv4 packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses <jani@iv.ro>
+ *         Simon Goldschmidt
+ * original reassembly code by Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4
+
+#include "lwip/ip4_frag.h"
+#include "lwip/def.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/stats.h"
+#include "lwip/icmp.h"
+
+#include <string.h>
+
+#if IP_REASSEMBLY
+/**
+ * The IP reassembly code currently has the following limitations:
+ * - IP header options are not supported
+ * - fragments must not overlap (e.g. due to different routes),
+ *   currently, overlapping or duplicate fragments are thrown away
+ *   if IP_REASS_CHECK_OVERLAP=1 (the default)!
+ *
+ * @todo: work with IP header options
+ */
+
+/** Setting this to 0, you can turn off checking the fragments for overlapping
+ * regions. The code gets a little smaller. Only use this if you know that
+ * overlapping won't occur on your network! */
+#ifndef IP_REASS_CHECK_OVERLAP
+#define IP_REASS_CHECK_OVERLAP 1
+#endif /* IP_REASS_CHECK_OVERLAP */
+
+/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is
+ * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller.
+ * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA
+ * is set to 1, so one datagram can be reassembled at a time, only. */
+#ifndef IP_REASS_FREE_OLDEST
+#define IP_REASS_FREE_OLDEST 1
+#endif /* IP_REASS_FREE_OLDEST */
+
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+#define IP_REASS_VALIDATE_TELEGRAM_FINISHED  1
+#define IP_REASS_VALIDATE_PBUF_QUEUED        0
+#define IP_REASS_VALIDATE_PBUF_DROPPED       -1
+
+/** This is a helper struct which holds the starting
+ * offset and the ending offset of this fragment to
+ * easily chain the fragments.
+ * It has the same packing requirements as the IP header, since it replaces
+ * the IP header in memory in incoming fragments (after copying it) to keep
+ * track of the various fragments. (-> If the IP header doesn't need packing,
+ * this struct doesn't need packing, too.)
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_reass_helper {
+  PACK_STRUCT_FIELD(struct pbuf *next_pbuf);
+  PACK_STRUCT_FIELD(u16_t start);
+  PACK_STRUCT_FIELD(u16_t end);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB)  \
+  (ip4_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \
+   ip4_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \
+   IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0
+
+/* global variables */
+static struct ip_reassdata *reassdatagrams;
+static u16_t ip_reass_pbufcount;
+
+/* function prototypes */
+static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev);
+
+/**
+ * Reassembly timer base function
+ * for both NO_SYS == 0 and 1 (!).
+ *
+ * Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
+ */
+void
+ip_reass_tmr(void)
+{
+  struct ip_reassdata *r, *prev = NULL;
+
+  r = reassdatagrams;
+  while (r != NULL) {
+    /* Decrement the timer. Once it reaches 0,
+     * clean up the incomplete fragment assembly */
+    if (r->timer > 0) {
+      r->timer--;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
+      prev = r;
+      r = r->next;
+    } else {
+      /* reassembly timed out */
+      struct ip_reassdata *tmp;
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
+      tmp = r;
+      /* get the next pointer before freeing */
+      r = r->next;
+      /* free the helper struct and all enqueued pbufs */
+      ip_reass_free_complete_datagram(tmp, prev);
+    }
+  }
+}
+
+/**
+ * Free a datagram (struct ip_reassdata) and all its pbufs.
+ * Updates the total count of enqueued pbufs (ip_reass_pbufcount),
+ * SNMP counters and sends an ICMP time exceeded packet.
+ *
+ * @param ipr datagram to free
+ * @param prev the previous datagram in the linked list
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  u16_t pbufs_freed = 0;
+  u16_t clen;
+  struct pbuf *p;
+  struct ip_reass_helper *iprh;
+
+  LWIP_ASSERT("prev != ipr", prev != ipr);
+  if (prev != NULL) {
+    LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
+  }
+
+  MIB2_STATS_INC(mib2.ipreasmfails);
+#if LWIP_ICMP
+  iprh = (struct ip_reass_helper *)ipr->p->payload;
+  if (iprh->start == 0) {
+    /* The first fragment was received, send ICMP time exceeded. */
+    /* First, de-queue the first pbuf from r->p. */
+    p = ipr->p;
+    ipr->p = iprh->next_pbuf;
+    /* Then, copy the original header into it. */
+    SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
+    icmp_time_exceeded(p, ICMP_TE_FRAG);
+    clen = pbuf_clen(p);
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+    pbufs_freed = (u16_t)(pbufs_freed + clen);
+    pbuf_free(p);
+  }
+#endif /* LWIP_ICMP */
+
+  /* First, free all received pbufs.  The individual pbufs need to be released
+     separately as they have not yet been chained */
+  p = ipr->p;
+  while (p != NULL) {
+    struct pbuf *pcur;
+    iprh = (struct ip_reass_helper *)p->payload;
+    pcur = p;
+    /* get the next pointer before freeing */
+    p = iprh->next_pbuf;
+    clen = pbuf_clen(pcur);
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+    pbufs_freed = (u16_t)(pbufs_freed + clen);
+    pbuf_free(pcur);
+  }
+  /* Then, unchain the struct ip_reassdata from the list and free it. */
+  ip_reass_dequeue_datagram(ipr, prev);
+  LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
+  ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
+
+  return pbufs_freed;
+}
+
+#if IP_REASS_FREE_OLDEST
+/**
+ * Free the oldest datagram to make room for enqueueing new fragments.
+ * The datagram 'fraghdr' belongs to is not freed!
+ *
+ * @param fraghdr IP header of the current fragment
+ * @param pbufs_needed number of pbufs needed to enqueue
+ *        (used for freeing other datagrams if not enough space)
+ * @return the number of pbufs freed
+ */
+static int
+ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
+{
+  /* @todo Can't we simply remove the last datagram in the
+   *       linked list behind reassdatagrams?
+   */
+  struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
+  int pbufs_freed = 0, pbufs_freed_current;
+  int other_datagrams;
+
+  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
+   * but don't free the datagram that 'fraghdr' belongs to! */
+  do {
+    oldest = NULL;
+    prev = NULL;
+    oldest_prev = NULL;
+    other_datagrams = 0;
+    r = reassdatagrams;
+    while (r != NULL) {
+      if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
+        /* Not the same datagram as fraghdr */
+        other_datagrams++;
+        if (oldest == NULL) {
+          oldest = r;
+          oldest_prev = prev;
+        } else if (r->timer <= oldest->timer) {
+          /* older than the previous oldest */
+          oldest = r;
+          oldest_prev = prev;
+        }
+      }
+      if (r->next != NULL) {
+        prev = r;
+      }
+      r = r->next;
+    }
+    if (oldest != NULL) {
+      pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
+      pbufs_freed += pbufs_freed_current;
+    }
+  } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
+  return pbufs_freed;
+}
+#endif /* IP_REASS_FREE_OLDEST */
+
+/**
+ * Enqueues a new fragment into the fragment queue
+ * @param fraghdr points to the new fragments IP hdr
+ * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
+ * @return A pointer to the queue location into which the fragment was enqueued
+ */
+static struct ip_reassdata *
+ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
+{
+  struct ip_reassdata *ipr;
+#if ! IP_REASS_FREE_OLDEST
+  LWIP_UNUSED_ARG(clen);
+#endif
+
+  /* No matching previous fragment found, allocate a new reassdata struct */
+  ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
+  if (ipr == NULL) {
+#if IP_REASS_FREE_OLDEST
+    if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
+      ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
+    }
+    if (ipr == NULL)
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
+      return NULL;
+    }
+  }
+  memset(ipr, 0, sizeof(struct ip_reassdata));
+  ipr->timer = IP_REASS_MAXAGE;
+
+  /* enqueue the new structure to the front of the list */
+  ipr->next = reassdatagrams;
+  reassdatagrams = ipr;
+  /* copy the ip header for later tests and input */
+  /* @todo: no ip options supported? */
+  SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
+  return ipr;
+}
+
+/**
+ * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
+ * @param ipr points to the queue entry to dequeue
+ */
+static void
+ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
+{
+  /* dequeue the reass struct  */
+  if (reassdatagrams == ipr) {
+    /* it was the first in the list */
+    reassdatagrams = ipr->next;
+  } else {
+    /* it wasn't the first, so it must have a valid 'prev' */
+    LWIP_ASSERT("sanity check linked list", prev != NULL);
+    prev->next = ipr->next;
+  }
+
+  /* now we can free the ip_reassdata struct */
+  memp_free(MEMP_REASSDATA, ipr);
+}
+
+/**
+ * Chain a new pbuf into the pbuf list that composes the datagram.  The pbuf list
+ * will grow over time as  new pbufs are rx.
+ * Also checks that the datagram passes basic continuity checks (if the last
+ * fragment was received at least once).
+ * @param ipr points to the reassembly state
+ * @param new_p points to the pbuf for the current fragment
+ * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
+ * @return see IP_REASS_VALIDATE_* defines
+ */
+static int
+ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
+{
+  struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
+  struct pbuf *q;
+  u16_t offset, len;
+  u8_t hlen;
+  struct ip_hdr *fraghdr;
+  int valid = 1;
+
+  /* Extract length and fragment offset from current fragment */
+  fraghdr = (struct ip_hdr *)new_p->payload;
+  len = lwip_ntohs(IPH_LEN(fraghdr));
+  hlen = IPH_HL_BYTES(fraghdr);
+  if (hlen > len) {
+    /* invalid datagram */
+    return IP_REASS_VALIDATE_PBUF_DROPPED;
+  }
+  len = (u16_t)(len - hlen);
+  offset = IPH_OFFSET_BYTES(fraghdr);
+
+  /* overwrite the fragment's ip header from the pbuf with our helper struct,
+   * and setup the embedded helper structure. */
+  /* make sure the struct ip_reass_helper fits into the IP header */
+  LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
+              sizeof(struct ip_reass_helper) <= IP_HLEN);
+  iprh = (struct ip_reass_helper *)new_p->payload;
+  iprh->next_pbuf = NULL;
+  iprh->start = offset;
+  iprh->end = (u16_t)(offset + len);
+  if (iprh->end < offset) {
+    /* u16_t overflow, cannot handle this */
+    return IP_REASS_VALIDATE_PBUF_DROPPED;
+  }
+
+  /* Iterate through until we either get to the end of the list (append),
+   * or we find one with a larger offset (insert). */
+  for (q = ipr->p; q != NULL;) {
+    iprh_tmp = (struct ip_reass_helper *)q->payload;
+    if (iprh->start < iprh_tmp->start) {
+      /* the new pbuf should be inserted before this */
+      iprh->next_pbuf = q;
+      if (iprh_prev != NULL) {
+        /* not the fragment with the lowest offset */
+#if IP_REASS_CHECK_OVERLAP
+        if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
+          /* fragment overlaps with previous or following, throw away */
+          return IP_REASS_VALIDATE_PBUF_DROPPED;
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        iprh_prev->next_pbuf = new_p;
+        if (iprh_prev->end != iprh->start) {
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+        }
+      } else {
+#if IP_REASS_CHECK_OVERLAP
+        if (iprh->end > iprh_tmp->start) {
+          /* fragment overlaps with following, throw away */
+          return IP_REASS_VALIDATE_PBUF_DROPPED;
+        }
+#endif /* IP_REASS_CHECK_OVERLAP */
+        /* fragment with the lowest offset */
+        ipr->p = new_p;
+      }
+      break;
+    } else if (iprh->start == iprh_tmp->start) {
+      /* received the same datagram twice: no need to keep the datagram */
+      return IP_REASS_VALIDATE_PBUF_DROPPED;
+#if IP_REASS_CHECK_OVERLAP
+    } else if (iprh->start < iprh_tmp->end) {
+      /* overlap: no need to keep the new datagram */
+      return IP_REASS_VALIDATE_PBUF_DROPPED;
+#endif /* IP_REASS_CHECK_OVERLAP */
+    } else {
+      /* Check if the fragments received so far have no holes. */
+      if (iprh_prev != NULL) {
+        if (iprh_prev->end != iprh_tmp->start) {
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+        }
+      }
+    }
+    q = iprh_tmp->next_pbuf;
+    iprh_prev = iprh_tmp;
+  }
+
+  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
+  if (q == NULL) {
+    if (iprh_prev != NULL) {
+      /* this is (for now), the fragment with the highest offset:
+       * chain it to the last fragment */
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      iprh_prev->next_pbuf = new_p;
+      if (iprh_prev->end != iprh->start) {
+        valid = 0;
+      }
+    } else {
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
+                  ipr->p == NULL);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* this is the first fragment we ever received for this ip datagram */
+      ipr->p = new_p;
+    }
+  }
+
+  /* At this point, the validation part begins: */
+  /* If we already received the last fragment */
+  if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
+    /* and had no holes so far */
+    if (valid) {
+      /* then check if the rest of the fragments is here */
+      /* Check if the queue starts with the first datagram */
+      if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
+        valid = 0;
+      } else {
+        /* and check that there are no holes after this datagram */
+        iprh_prev = iprh;
+        q = iprh->next_pbuf;
+        while (q != NULL) {
+          iprh = (struct ip_reass_helper *)q->payload;
+          if (iprh_prev->end != iprh->start) {
+            valid = 0;
+            break;
+          }
+          iprh_prev = iprh;
+          q = iprh->next_pbuf;
+        }
+        /* if still valid, all fragments are received
+         * (because to the MF==0 already arrived */
+        if (valid) {
+          LWIP_ASSERT("sanity check", ipr->p != NULL);
+          LWIP_ASSERT("sanity check",
+                      ((struct ip_reass_helper *)ipr->p->payload) != iprh);
+          LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
+                      iprh->next_pbuf == NULL);
+        }
+      }
+    }
+    /* If valid is 0 here, there are some fragments missing in the middle
+     * (since MF == 0 has already arrived). Such datagrams simply time out if
+     * no more fragments are received... */
+    return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
+  }
+  /* If we come here, not all fragments were received, yet! */
+  return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
+}
+
+/**
+ * Reassembles incoming IP fragments into an IP datagram.
+ *
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip4_reass(struct pbuf *p)
+{
+  struct pbuf *r;
+  struct ip_hdr *fraghdr;
+  struct ip_reassdata *ipr;
+  struct ip_reass_helper *iprh;
+  u16_t offset, len, clen;
+  u8_t hlen;
+  int valid;
+  int is_last;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+  MIB2_STATS_INC(mib2.ipreasmreqds);
+
+  fraghdr = (struct ip_hdr *)p->payload;
+
+  if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
+    IPFRAG_STATS_INC(ip_frag.err);
+    goto nullreturn;
+  }
+
+  offset = IPH_OFFSET_BYTES(fraghdr);
+  len = lwip_ntohs(IPH_LEN(fraghdr));
+  hlen = IPH_HL_BYTES(fraghdr);
+  if (hlen > len) {
+    /* invalid datagram */
+    goto nullreturn;
+  }
+  len = (u16_t)(len - hlen);
+
+  /* Check if we are allowed to enqueue more datagrams. */
+  clen = pbuf_clen(p);
+  if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
+#if IP_REASS_FREE_OLDEST
+    if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
+        ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      /* No datagram could be freed and still too many pbufs enqueued */
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n",
+                                   ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS));
+      IPFRAG_STATS_INC(ip_frag.memerr);
+      /* @todo: send ICMP time exceeded here? */
+      /* drop this pbuf */
+      goto nullreturn;
+    }
+  }
+
+  /* Look for the datagram the fragment belongs to in the current datagram queue,
+   * remembering the previous in the queue for later dequeueing. */
+  for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
+    /* Check if the incoming fragment matches the one currently present
+       in the reassembly buffer. If so, we proceed with copying the
+       fragment into the buffer. */
+    if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
+                                   lwip_ntohs(IPH_ID(fraghdr))));
+      IPFRAG_STATS_INC(ip_frag.cachehit);
+      break;
+    }
+  }
+
+  if (ipr == NULL) {
+    /* Enqueue a new datagram into the datagram queue */
+    ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
+    /* Bail if unable to enqueue */
+    if (ipr == NULL) {
+      goto nullreturn;
+    }
+  } else {
+    if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
+        ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
+      /* ipr->iphdr is not the header from the first fragment, but fraghdr is
+       * -> copy fraghdr into ipr->iphdr since we want to have the header
+       * of the first fragment (for ICMP time exceeded and later, for copying
+       * all options, if supported)*/
+      SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
+    }
+  }
+
+  /* At this point, we have either created a new entry or pointing
+   * to an existing one */
+
+  /* check for 'no more fragments', and update queue entry*/
+  is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
+  if (is_last) {
+    u16_t datagram_len = (u16_t)(offset + len);
+    if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
+      /* u16_t overflow, cannot handle this */
+      goto nullreturn_ipr;
+    }
+  }
+  /* find the right place to insert this pbuf */
+  /* @todo: trim pbufs if fragments are overlapping */
+  valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
+  if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
+    goto nullreturn_ipr;
+  }
+  /* if we come here, the pbuf has been enqueued */
+
+  /* Track the current number of pbufs current 'in-flight', in order to limit
+     the number of fragments that may be enqueued at any one time
+     (overflow checked by testing against IP_REASS_MAX_PBUFS) */
+  ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
+  if (is_last) {
+    u16_t datagram_len = (u16_t)(offset + len);
+    ipr->datagram_len = datagram_len;
+    ipr->flags |= IP_REASS_FLAG_LASTFRAG;
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+                ("ip4_reass: last fragment seen, total len %"S16_F"\n",
+                 ipr->datagram_len));
+  }
+
+  if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
+    struct ip_reassdata *ipr_prev;
+    /* the totally last fragment (flag more fragments = 0) was received at least
+     * once AND all fragments are received */
+    u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
+
+    /* save the second pbuf before copying the header over the pointer */
+    r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
+
+    /* copy the original ip header back to the first pbuf */
+    fraghdr = (struct ip_hdr *)(ipr->p->payload);
+    SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
+    IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
+    IPH_OFFSET_SET(fraghdr, 0);
+    IPH_CHKSUM_SET(fraghdr, 0);
+    /* @todo: do we need to set/calculate the correct checksum? */
+#if CHECKSUM_GEN_IP
+    IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
+      IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
+    }
+#endif /* CHECKSUM_GEN_IP */
+
+    p = ipr->p;
+
+    /* chain together the pbufs contained within the reass_data list. */
+    while (r != NULL) {
+      iprh = (struct ip_reass_helper *)r->payload;
+
+      /* hide the ip header for every succeeding fragment */
+      pbuf_remove_header(r, IP_HLEN);
+      pbuf_cat(p, r);
+      r = iprh->next_pbuf;
+    }
+
+    /* find the previous entry in the linked list */
+    if (ipr == reassdatagrams) {
+      ipr_prev = NULL;
+    } else {
+      for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
+        if (ipr_prev->next == ipr) {
+          break;
+        }
+      }
+    }
+
+    /* release the sources allocate for the fragment queue entry */
+    ip_reass_dequeue_datagram(ipr, ipr_prev);
+
+    /* and adjust the number of pbufs currently queued for reassembly. */
+    clen = pbuf_clen(p);
+    LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
+    ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
+
+    MIB2_STATS_INC(mib2.ipreasmoks);
+
+    /* Return the pbuf chain */
+    return p;
+  }
+  /* the datagram is not (yet?) reassembled completely */
+  LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
+  return NULL;
+
+nullreturn_ipr:
+  LWIP_ASSERT("ipr != NULL", ipr != NULL);
+  if (ipr->p == NULL) {
+    /* dropped pbuf after creating a new datagram entry: remove the entry, too */
+    LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
+    ip_reass_dequeue_datagram(ipr, NULL);
+  }
+
+nullreturn:
+  LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+/** Allocate a new struct pbuf_custom_ref */
+static struct pbuf_custom_ref *
+ip_frag_alloc_pbuf_custom_ref(void)
+{
+  return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
+}
+
+/** Free a struct pbuf_custom_ref */
+static void
+ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
+{
+  LWIP_ASSERT("p != NULL", p != NULL);
+  memp_free(MEMP_FRAG_PBUF, p);
+}
+
+/** Free-callback function to free a 'struct pbuf_custom_ref', called by
+ * pbuf_free. */
+static void
+ipfrag_free_pbuf_custom(struct pbuf *p)
+{
+  struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
+  LWIP_ASSERT("pcr != NULL", pcr != NULL);
+  LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
+  if (pcr->original != NULL) {
+    pbuf_free(pcr->original);
+  }
+  ip_frag_free_pbuf_custom_ref(pcr);
+}
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+
+/**
+ * Fragment an IP datagram if too large for the netif.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by pointing PBUF_REFs into p.
+ *
+ * @param p ip packet to send
+ * @param netif the netif on which to send
+ * @param dest destination ip address to which to send
+ *
+ * @return ERR_OK if sent successfully, err_t otherwise
+ */
+err_t
+ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
+{
+  struct pbuf *rambuf;
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+  struct pbuf *newpbuf;
+  u16_t newpbuflen = 0;
+  u16_t left_to_copy;
+#endif
+  struct ip_hdr *original_iphdr;
+  struct ip_hdr *iphdr;
+  const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
+  u16_t left, fragsize;
+  u16_t ofo;
+  int last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+  int mf_set;
+
+  original_iphdr = (struct ip_hdr *)p->payload;
+  iphdr = original_iphdr;
+  if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
+    /* ip4_frag() does not support IP options */
+    return ERR_VAL;
+  }
+  LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
+
+  /* Save original offset */
+  tmp = lwip_ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  /* already fragmented? if so, the last fragment we create must have MF, too */
+  mf_set = tmp & IP_MF;
+
+  left = (u16_t)(p->tot_len - IP_HLEN);
+
+  while (left) {
+    /* Fill this fragment */
+    fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+    rambuf = pbuf_alloc(PBUF_IP, fragsize, PBUF_RAM);
+    if (rambuf == NULL) {
+      goto memerr;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+                (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL));
+    poff += pbuf_copy_partial(p, rambuf->payload, fragsize, poff);
+    /* make room for the IP header */
+    if (pbuf_add_header(rambuf, IP_HLEN)) {
+      pbuf_free(rambuf);
+      goto memerr;
+    }
+    /* fill in the IP header */
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+    iphdr = (struct ip_hdr *)rambuf->payload;
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+    /* When not using a static buffer, create a chain of pbufs.
+     * The first will be a PBUF_RAM holding the link and IP header.
+     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
+     * but limited to the size of an mtu.
+     */
+    rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
+    if (rambuf == NULL) {
+      goto memerr;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+                (rambuf->len >= (IP_HLEN)));
+    SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
+    iphdr = (struct ip_hdr *)rambuf->payload;
+
+    left_to_copy = fragsize;
+    while (left_to_copy) {
+      struct pbuf_custom_ref *pcr;
+      u16_t plen = (u16_t)(p->len - poff);
+      LWIP_ASSERT("p->len >= poff", p->len >= poff);
+      newpbuflen = LWIP_MIN(left_to_copy, plen);
+      /* Is this pbuf already empty? */
+      if (!newpbuflen) {
+        poff = 0;
+        p = p->next;
+        continue;
+      }
+      pcr = ip_frag_alloc_pbuf_custom_ref();
+      if (pcr == NULL) {
+        pbuf_free(rambuf);
+        goto memerr;
+      }
+      /* Mirror this pbuf, although we might not need all of it. */
+      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
+                                    (u8_t *)p->payload + poff, newpbuflen);
+      if (newpbuf == NULL) {
+        ip_frag_free_pbuf_custom_ref(pcr);
+        pbuf_free(rambuf);
+        goto memerr;
+      }
+      pbuf_ref(p);
+      pcr->original = p;
+      pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
+
+      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
+       * so that it is removed when pbuf_dechain is later called on rambuf.
+       */
+      pbuf_cat(rambuf, newpbuf);
+      left_to_copy = (u16_t)(left_to_copy - newpbuflen);
+      if (left_to_copy) {
+        poff = 0;
+        p = p->next;
+      }
+    }
+    poff = (u16_t)(poff + newpbuflen);
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+    /* Correct header */
+    last = (left <= netif->mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    tmp = (IP_OFFMASK & (ofo));
+    if (!last || mf_set) {
+      /* the last fragment has MF set if the input frame had it */
+      tmp = tmp | IP_MF;
+    }
+    IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
+    IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) {
+      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+    }
+#endif /* CHECKSUM_GEN_IP */
+
+    /* No need for separate header pbuf - we allowed room for it in rambuf
+     * when allocated.
+     */
+    netif->output(netif, rambuf, dest);
+    IPFRAG_STATS_INC(ip_frag.xmit);
+
+    /* Unfortunately we can't reuse rambuf - the hardware may still be
+     * using the buffer. Instead we free it (and the ensuing chain) and
+     * recreate it next time round the loop. If we're lucky the hardware
+     * will have already sent the packet, the free will really free, and
+     * there will be zero memory penalty.
+     */
+
+    pbuf_free(rambuf);
+    left = (u16_t)(left - fragsize);
+    ofo = (u16_t)(ofo + nfb);
+  }
+  MIB2_STATS_INC(mib2.ipfragoks);
+  return ERR_OK;
+memerr:
+  MIB2_STATS_INC(mib2.ipfragfails);
+  return ERR_MEM;
+}
+#endif /* IP_FRAG */
+
+#endif /* LWIP_IPV4 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/dhcp6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/dhcp6.c
new file mode 100644
index 000000000..7cf98a521
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/dhcp6.c
@@ -0,0 +1,812 @@
+/**
+ * @file
+ *
+ * @defgroup dhcp6 DHCPv6
+ * @ingroup ip6
+ * DHCPv6 client: IPv6 address autoconfiguration as per
+ * RFC 3315 (stateful DHCPv6) and
+ * RFC 3736 (stateless DHCPv6).
+ *
+ * For now, only stateless DHCPv6 is implemented!
+ *
+ * TODO:
+ * - enable/disable API to not always start when RA is received
+ * - stateful DHCPv6 (for now, only stateless DHCPv6 for DNS and NTP servers works)
+ * - create Client Identifier?
+ * - only start requests if a valid local address is available on the netif
+ * - only start information requests if required (not for every RA)
+ *
+ * dhcp6_enable_stateful() enables stateful DHCPv6 for a netif (stateless disabled)\n
+ * dhcp6_enable_stateless() enables stateless DHCPv6 for a netif (stateful disabled)\n
+ * dhcp6_disable() disable DHCPv6 for a netif
+ *
+ * When enabled, requests are only issued after receipt of RA with the
+ * corresponding bits set.
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_IPV6_DHCP6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/dhcp6.h"
+#include "lwip/prot/dhcp6.h"
+#include "lwip/def.h"
+#include "lwip/udp.h"
+#include "lwip/dns.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+#ifndef LWIP_HOOK_DHCP6_APPEND_OPTIONS
+#define LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len)
+#endif
+#ifndef LWIP_HOOK_DHCP6_PARSE_OPTION
+#define LWIP_HOOK_DHCP6_PARSE_OPTION(netif, dhcp6, state, msg, msg_type, option, len, pbuf, offset) do { LWIP_UNUSED_ARG(msg); } while(0)
+#endif
+
+#if LWIP_DNS && LWIP_DHCP6_MAX_DNS_SERVERS
+#if DNS_MAX_SERVERS > LWIP_DHCP6_MAX_DNS_SERVERS
+#define LWIP_DHCP6_PROVIDE_DNS_SERVERS LWIP_DHCP6_MAX_DNS_SERVERS
+#else
+#define LWIP_DHCP6_PROVIDE_DNS_SERVERS DNS_MAX_SERVERS
+#endif
+#else
+#define LWIP_DHCP6_PROVIDE_DNS_SERVERS 0
+#endif
+
+
+/** Option handling: options are parsed in dhcp6_parse_reply
+ * and saved in an array where other functions can load them from.
+ * This might be moved into the struct dhcp6 (not necessarily since
+ * lwIP is single-threaded and the array is only used while in recv
+ * callback). */
+enum dhcp6_option_idx {
+  DHCP6_OPTION_IDX_CLI_ID = 0,
+  DHCP6_OPTION_IDX_SERVER_ID,
+#if LWIP_DHCP6_PROVIDE_DNS_SERVERS
+  DHCP6_OPTION_IDX_DNS_SERVER,
+  DHCP6_OPTION_IDX_DOMAIN_LIST,
+#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
+#if LWIP_DHCP6_GET_NTP_SRV
+  DHCP6_OPTION_IDX_NTP_SERVER,
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+  DHCP6_OPTION_IDX_MAX
+};
+
+struct dhcp6_option_info {
+  u8_t option_given;
+  u16_t val_start;
+  u16_t val_length;
+};
+
+/** Holds the decoded option info, only valid while in dhcp6_recv. */
+struct dhcp6_option_info dhcp6_rx_options[DHCP6_OPTION_IDX_MAX];
+
+#define dhcp6_option_given(dhcp6, idx)           (dhcp6_rx_options[idx].option_given != 0)
+#define dhcp6_got_option(dhcp6, idx)             (dhcp6_rx_options[idx].option_given = 1)
+#define dhcp6_clear_option(dhcp6, idx)           (dhcp6_rx_options[idx].option_given = 0)
+#define dhcp6_clear_all_options(dhcp6)           (memset(dhcp6_rx_options, 0, sizeof(dhcp6_rx_options)))
+#define dhcp6_get_option_start(dhcp6, idx)       (dhcp6_rx_options[idx].val_start)
+#define dhcp6_get_option_length(dhcp6, idx)      (dhcp6_rx_options[idx].val_length)
+#define dhcp6_set_option(dhcp6, idx, start, len) do { dhcp6_rx_options[idx].val_start = (start); dhcp6_rx_options[idx].val_length = (len); }while(0)
+
+
+const ip_addr_t dhcp6_All_DHCP6_Relay_Agents_and_Servers = IPADDR6_INIT_HOST(0xFF020000, 0, 0, 0x00010002);
+const ip_addr_t dhcp6_All_DHCP6_Servers = IPADDR6_INIT_HOST(0xFF020000, 0, 0, 0x00010003);
+
+static struct udp_pcb *dhcp6_pcb;
+static u8_t dhcp6_pcb_refcount;
+
+
+/* receive, unfold, parse and free incoming messages */
+static void dhcp6_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port);
+
+/** Ensure DHCP PCB is allocated and bound */
+static err_t
+dhcp6_inc_pcb_refcount(void)
+{
+  if (dhcp6_pcb_refcount == 0) {
+    LWIP_ASSERT("dhcp6_inc_pcb_refcount(): memory leak", dhcp6_pcb == NULL);
+
+    /* allocate UDP PCB */
+    dhcp6_pcb = udp_new_ip6();
+
+    if (dhcp6_pcb == NULL) {
+      return ERR_MEM;
+    }
+
+    ip_set_option(dhcp6_pcb, SOF_BROADCAST);
+
+    /* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */
+    udp_bind(dhcp6_pcb, IP6_ADDR_ANY, DHCP6_CLIENT_PORT);
+    udp_recv(dhcp6_pcb, dhcp6_recv, NULL);
+  }
+
+  dhcp6_pcb_refcount++;
+
+  return ERR_OK;
+}
+
+/** Free DHCP PCB if the last netif stops using it */
+static void
+dhcp6_dec_pcb_refcount(void)
+{
+  LWIP_ASSERT("dhcp6_pcb_refcount(): refcount error", (dhcp6_pcb_refcount > 0));
+  dhcp6_pcb_refcount--;
+
+  if (dhcp6_pcb_refcount == 0) {
+    udp_remove(dhcp6_pcb);
+    dhcp6_pcb = NULL;
+  }
+}
+
+/**
+ * @ingroup dhcp6
+ * Set a statically allocated struct dhcp6 to work with.
+ * Using this prevents dhcp6_start to allocate it using mem_malloc.
+ *
+ * @param netif the netif for which to set the struct dhcp
+ * @param dhcp6 (uninitialised) dhcp6 struct allocated by the application
+ */
+void
+dhcp6_set_struct(struct netif *netif, struct dhcp6 *dhcp6)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp6 != NULL", dhcp6 != NULL);
+  LWIP_ASSERT("netif already has a struct dhcp6 set", netif_dhcp6_data(netif) == NULL);
+
+  /* clear data structure */
+  memset(dhcp6, 0, sizeof(struct dhcp6));
+  /* dhcp6_set_state(&dhcp, DHCP6_STATE_OFF); */
+  netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, dhcp6);
+}
+
+/**
+ * @ingroup dhcp6
+ * Removes a struct dhcp6 from a netif.
+ *
+ * ATTENTION: Only use this when not using dhcp6_set_struct() to allocate the
+ *            struct dhcp6 since the memory is passed back to the heap.
+ *
+ * @param netif the netif from which to remove the struct dhcp
+ */
+void dhcp6_cleanup(struct netif *netif)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+
+  if (netif_dhcp6_data(netif) != NULL) {
+    mem_free(netif_dhcp6_data(netif));
+    netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL);
+  }
+}
+
+static struct dhcp6*
+dhcp6_get_struct(struct netif *netif, const char *dbg_requester)
+{
+  struct dhcp6 *dhcp6 = netif_dhcp6_data(netif);
+  if (dhcp6 == NULL) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("%s: mallocing new DHCPv6 client\n", dbg_requester));
+    dhcp6 = (struct dhcp6 *)mem_malloc(sizeof(struct dhcp6));
+    if (dhcp6 == NULL) {
+      LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("%s: could not allocate dhcp6\n", dbg_requester));
+      return NULL;
+    }
+
+    /* clear data structure, this implies DHCP6_STATE_OFF */
+    memset(dhcp6, 0, sizeof(struct dhcp6));
+    /* store this dhcp6 client in the netif */
+    netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, dhcp6);
+  } else {
+    /* already has DHCP6 client attached */
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("%s: using existing DHCPv6 client\n", dbg_requester));
+  }
+
+  if (!dhcp6->pcb_allocated) {
+    if (dhcp6_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP6 PCB is allocated */
+      mem_free(dhcp6);
+      netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL);
+      return NULL;
+    }
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("%s: allocated dhcp6", dbg_requester));
+    dhcp6->pcb_allocated = 1;
+  }
+  return dhcp6;
+}
+
+/*
+ * Set the DHCPv6 state
+ * If the state changed, reset the number of tries.
+ */
+static void
+dhcp6_set_state(struct dhcp6 *dhcp6, u8_t new_state, const char *dbg_caller)
+{
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("DHCPv6 state: %d -> %d (%s)\n",
+    dhcp6->state, new_state, dbg_caller));
+  if (new_state != dhcp6->state) {
+    dhcp6->state = new_state;
+    dhcp6->tries = 0;
+    dhcp6->request_timeout = 0;
+  }
+}
+
+static int
+dhcp6_stateless_enabled(struct dhcp6 *dhcp6)
+{
+  if ((dhcp6->state == DHCP6_STATE_STATELESS_IDLE) ||
+      (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG)) {
+    return 1;
+  }
+  return 0;
+}
+
+/*static int
+dhcp6_stateful_enabled(struct dhcp6 *dhcp6)
+{
+  if (dhcp6->state == DHCP6_STATE_OFF) {
+    return 0;
+  }
+  if (dhcp6_stateless_enabled(dhcp6)) {
+    return 0;
+  }
+  return 1;
+}*/
+
+/**
+ * @ingroup dhcp6
+ * Enable stateful DHCPv6 on this netif
+ * Requests are sent on receipt of an RA message with the
+ * ND6_RA_FLAG_MANAGED_ADDR_CONFIG flag set.
+ *
+ * A struct dhcp6 will be allocated for this netif if not
+ * set via @ref dhcp6_set_struct before.
+ *
+ * @todo: stateful DHCPv6 not supported, yet
+ */
+err_t
+dhcp6_enable_stateful(struct netif *netif)
+{
+  LWIP_UNUSED_ARG(netif);
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("stateful dhcp6 not implemented yet"));
+  return ERR_VAL;
+}
+
+/**
+ * @ingroup dhcp6
+ * Enable stateless DHCPv6 on this netif
+ * Requests are sent on receipt of an RA message with the
+ * ND6_RA_FLAG_OTHER_CONFIG flag set.
+ *
+ * A struct dhcp6 will be allocated for this netif if not
+ * set via @ref dhcp6_set_struct before.
+ */
+err_t
+dhcp6_enable_stateless(struct netif *netif)
+{
+  struct dhcp6 *dhcp6;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_enable_stateless(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  dhcp6 = dhcp6_get_struct(netif, "dhcp6_enable_stateless()");
+  if (dhcp6 == NULL) {
+    return ERR_MEM;
+  }
+  if (dhcp6_stateless_enabled(dhcp6)) {
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_enable_stateless(): stateless DHCPv6 already enabled"));
+    return ERR_OK;
+  } else if (dhcp6->state != DHCP6_STATE_OFF) {
+    /* stateful running */
+    /* @todo: stop stateful once it is implemented */
+    LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_enable_stateless(): switching from stateful to stateless DHCPv6"));
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_enable_stateless(): stateless DHCPv6 enabled\n"));
+  dhcp6_set_state(dhcp6, DHCP6_STATE_STATELESS_IDLE, "dhcp6_enable_stateless");
+  return ERR_OK;
+}
+
+/**
+ * @ingroup dhcp6
+ * Disable stateful or stateless DHCPv6 on this netif
+ * Requests are sent on receipt of an RA message with the
+ * ND6_RA_FLAG_OTHER_CONFIG flag set.
+ */
+void
+dhcp6_disable(struct netif *netif)
+{
+  struct dhcp6 *dhcp6;
+
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_disable(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  dhcp6 = netif_dhcp6_data(netif);
+  if (dhcp6 != NULL) {
+    if (dhcp6->state != DHCP6_STATE_OFF) {
+      LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_disable(): DHCPv6 disabled (old state: %s)\n",
+        (dhcp6_stateless_enabled(dhcp6) ? "stateless" : "stateful")));
+      dhcp6_set_state(dhcp6, DHCP6_STATE_OFF, "dhcp6_disable");
+      if (dhcp6->pcb_allocated != 0) {
+        dhcp6_dec_pcb_refcount(); /* free DHCPv6 PCB if not needed any more */
+        dhcp6->pcb_allocated = 0;
+      }
+    }
+  }
+}
+
+/**
+ * Create a DHCPv6 request, fill in common headers
+ *
+ * @param netif the netif under DHCPv6 control
+ * @param dhcp6 dhcp6 control struct
+ * @param message_type message type of the request
+ * @param opt_len_alloc option length to allocate
+ * @param options_out_len option length on exit
+ * @return a pbuf for the message
+ */
+static struct pbuf *
+dhcp6_create_msg(struct netif *netif, struct dhcp6 *dhcp6, u8_t message_type,
+                 u16_t opt_len_alloc, u16_t *options_out_len)
+{
+  struct pbuf *p_out;
+  struct dhcp6_msg *msg_out;
+
+  LWIP_ERROR("dhcp6_create_msg: netif != NULL", (netif != NULL), return NULL;);
+  LWIP_ERROR("dhcp6_create_msg: dhcp6 != NULL", (dhcp6 != NULL), return NULL;);
+  p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp6_msg) + opt_len_alloc, PBUF_RAM);
+  if (p_out == NULL) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("dhcp6_create_msg(): could not allocate pbuf\n"));
+    return NULL;
+  }
+  LWIP_ASSERT("dhcp6_create_msg: check that first pbuf can hold struct dhcp6_msg",
+              (p_out->len >= sizeof(struct dhcp6_msg) + opt_len_alloc));
+
+  /* @todo: limit new xid for certain message types? */
+  /* reuse transaction identifier in retransmissions */
+  if (dhcp6->tries == 0) {
+    dhcp6->xid = LWIP_RAND() & 0xFFFFFF;
+  }
+
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE,
+              ("transaction id xid(%"X32_F")\n", dhcp6->xid));
+
+  msg_out = (struct dhcp6_msg *)p_out->payload;
+  memset(msg_out, 0, sizeof(struct dhcp6_msg) + opt_len_alloc);
+
+  msg_out->msgtype = message_type;
+  msg_out->transaction_id[0] = (u8_t)(dhcp6->xid >> 16);
+  msg_out->transaction_id[1] = (u8_t)(dhcp6->xid >> 8);
+  msg_out->transaction_id[2] = (u8_t)dhcp6->xid;
+  *options_out_len = 0;
+  return p_out;
+}
+
+static u16_t
+dhcp6_option_short(u16_t options_out_len, u8_t *options, u16_t value)
+{
+  options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
+  options[options_out_len++] = (u8_t) (value & 0x00ffU);
+  return options_out_len;
+}
+
+static u16_t
+dhcp6_option_optionrequest(u16_t options_out_len, u8_t *options, const u16_t *req_options,
+                           u16_t num_req_options, u16_t max_len)
+{
+  size_t i;
+  u16_t ret;
+
+  LWIP_ASSERT("dhcp6_option_optionrequest: options_out_len + sizeof(struct dhcp6_msg) + addlen <= max_len",
+    sizeof(struct dhcp6_msg) + options_out_len + 4U + (2U * num_req_options) <= max_len);
+  LWIP_UNUSED_ARG(max_len);
+
+  ret = dhcp6_option_short(options_out_len, options, DHCP6_OPTION_ORO);
+  ret = dhcp6_option_short(ret, options, 2 * num_req_options);
+  for (i = 0; i < num_req_options; i++) {
+    ret = dhcp6_option_short(ret, options, req_options[i]);
+  }
+  return ret;
+}
+
+/* All options are added, shrink the pbuf to the required size */
+static void
+dhcp6_msg_finalize(u16_t options_out_len, struct pbuf *p_out)
+{
+  /* shrink the pbuf to the actual content length */
+  pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp6_msg) + options_out_len));
+}
+
+
+#if LWIP_IPV6_DHCP6_STATELESS
+static void
+dhcp6_information_request(struct netif *netif, struct dhcp6 *dhcp6)
+{
+  const u16_t requested_options[] = {DHCP6_OPTION_DNS_SERVERS, DHCP6_OPTION_DOMAIN_LIST, DHCP6_OPTION_SNTP_SERVERS};
+  u16_t msecs;
+  struct pbuf *p_out;
+  u16_t options_out_len;
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_information_request()\n"));
+  /* create and initialize the DHCP message header */
+  p_out = dhcp6_create_msg(netif, dhcp6, DHCP6_INFOREQUEST, 4 + sizeof(requested_options), &options_out_len);
+  if (p_out != NULL) {
+    err_t err;
+    struct dhcp6_msg *msg_out = (struct dhcp6_msg *)p_out->payload;
+    u8_t *options = (u8_t *)(msg_out + 1);
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_information_request: making request\n"));
+
+    options_out_len = dhcp6_option_optionrequest(options_out_len, options, requested_options,
+      LWIP_ARRAYSIZE(requested_options), p_out->len);
+    LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, DHCP6_STATE_REQUESTING_CONFIG, msg_out,
+      DHCP6_INFOREQUEST, options_out_len, p_out->len);
+    dhcp6_msg_finalize(options_out_len, p_out);
+
+    err = udp_sendto_if(dhcp6_pcb, p_out, &dhcp6_All_DHCP6_Relay_Agents_and_Servers, DHCP6_SERVER_PORT, netif);
+    pbuf_free(p_out);
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_information_request: INFOREQUESTING -> %d\n", (int)err));
+    LWIP_UNUSED_ARG(err);
+  } else {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp6_information_request: could not allocate DHCP6 request\n"));
+  }
+  dhcp6_set_state(dhcp6, DHCP6_STATE_REQUESTING_CONFIG, "dhcp6_information_request");
+  if (dhcp6->tries < 255) {
+    dhcp6->tries++;
+  }
+  msecs = (u16_t)((dhcp6->tries < 6 ? 1 << dhcp6->tries : 60) * 1000);
+  dhcp6->request_timeout = (u16_t)((msecs + DHCP6_TIMER_MSECS - 1) / DHCP6_TIMER_MSECS);
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_information_request(): set request timeout %"U16_F" msecs\n", msecs));
+}
+
+static err_t
+dhcp6_request_config(struct netif *netif, struct dhcp6 *dhcp6)
+{
+  /* stateless mode enabled and no request running? */
+  if (dhcp6->state == DHCP6_STATE_STATELESS_IDLE) {
+    /* send Information-request and wait for answer; setup receive timeout */
+    dhcp6_information_request(netif, dhcp6);
+  }
+
+  return ERR_OK;
+}
+
+static void
+dhcp6_abort_config_request(struct dhcp6 *dhcp6)
+{
+  if (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG) {
+    /* abort running request */
+    dhcp6_set_state(dhcp6, DHCP6_STATE_STATELESS_IDLE, "dhcp6_abort_config_request");
+  }
+}
+
+/* Handle a REPLY to INFOREQUEST
+ * This parses DNS and NTP server addresses from the reply.
+ */
+static void
+dhcp6_handle_config_reply(struct netif *netif, struct pbuf *p_msg_in)
+{
+  struct dhcp6 *dhcp6 = netif_dhcp6_data(netif);
+
+  LWIP_UNUSED_ARG(dhcp6);
+  LWIP_UNUSED_ARG(p_msg_in);
+
+#if LWIP_DHCP6_PROVIDE_DNS_SERVERS
+  if (dhcp6_option_given(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER)) {
+    ip_addr_t dns_addr;
+    ip6_addr_t *dns_addr6;
+    u16_t op_start = dhcp6_get_option_start(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER);
+    u16_t op_len = dhcp6_get_option_length(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER);
+    u16_t idx;
+    u8_t n;
+
+    memset(&dns_addr, 0, sizeof(dns_addr));
+    dns_addr6 = ip_2_ip6(&dns_addr);
+    for (n = 0, idx = op_start; (idx < op_start + op_len) && (n < LWIP_DHCP6_PROVIDE_DNS_SERVERS);
+         n++, idx += sizeof(struct ip6_addr_packed)) {
+      u16_t copied = pbuf_copy_partial(p_msg_in, dns_addr6, sizeof(struct ip6_addr_packed), idx);
+      if (copied != sizeof(struct ip6_addr_packed)) {
+        /* pbuf length mismatch */
+        return;
+      }
+      ip6_addr_assign_zone(dns_addr6, IP6_UNKNOWN, netif);
+      /* @todo: do we need a different offset than DHCP(v4)? */
+      dns_setserver(n, &dns_addr);
+    }
+  }
+  /* @ todo: parse and set Domain Search List */
+#endif /* LWIP_DHCP6_PROVIDE_DNS_SERVERS */
+
+#if LWIP_DHCP6_GET_NTP_SRV
+  if (dhcp6_option_given(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER)) {
+    ip_addr_t ntp_server_addrs[LWIP_DHCP6_MAX_NTP_SERVERS];
+    u16_t op_start = dhcp6_get_option_start(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER);
+    u16_t op_len = dhcp6_get_option_length(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER);
+    u16_t idx;
+    u8_t n;
+
+    for (n = 0, idx = op_start; (idx < op_start + op_len) && (n < LWIP_DHCP6_MAX_NTP_SERVERS);
+         n++, idx += sizeof(struct ip6_addr_packed)) {
+      u16_t copied;
+      ip6_addr_t *ntp_addr6 = ip_2_ip6(&ntp_server_addrs[n]);
+      ip_addr_set_zero_ip6(&ntp_server_addrs[n]);
+      copied = pbuf_copy_partial(p_msg_in, ntp_addr6, sizeof(struct ip6_addr_packed), idx);
+      if (copied != sizeof(struct ip6_addr_packed)) {
+        /* pbuf length mismatch */
+        return;
+      }
+      ip6_addr_assign_zone(ntp_addr6, IP6_UNKNOWN, netif);
+    }
+    dhcp6_set_ntp_servers(n, ntp_server_addrs);
+  }
+#endif /* LWIP_DHCP6_GET_NTP_SRV */
+}
+#endif /* LWIP_IPV6_DHCP6_STATELESS */
+
+/** This function is called from nd6 module when an RA messsage is received
+ * It triggers DHCPv6 requests (if enabled).
+ */
+void
+dhcp6_nd6_ra_trigger(struct netif *netif, u8_t managed_addr_config, u8_t other_config)
+{
+  struct dhcp6 *dhcp6;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  dhcp6 = netif_dhcp6_data(netif);
+
+  LWIP_UNUSED_ARG(managed_addr_config);
+  LWIP_UNUSED_ARG(other_config);
+  LWIP_UNUSED_ARG(dhcp6);
+
+#if LWIP_IPV6_DHCP6_STATELESS
+  if (dhcp6 != NULL) {
+    if (dhcp6_stateless_enabled(dhcp6)) {
+      if (other_config) {
+        dhcp6_request_config(netif, dhcp6);
+      } else {
+        dhcp6_abort_config_request(dhcp6);
+      }
+    }
+  }
+#endif /* LWIP_IPV6_DHCP6_STATELESS */
+}
+
+/**
+ * Parse the DHCPv6 message and extract the DHCPv6 options.
+ *
+ * Extract the DHCPv6 options (offset + length) so that we can later easily
+ * check for them or extract the contents.
+ */
+static err_t
+dhcp6_parse_reply(struct pbuf *p, struct dhcp6 *dhcp6)
+{
+  u16_t offset;
+  u16_t offset_max;
+  u16_t options_idx;
+  struct dhcp6_msg *msg_in;
+
+  LWIP_UNUSED_ARG(dhcp6);
+
+  /* clear received options */
+  dhcp6_clear_all_options(dhcp6);
+  msg_in = (struct dhcp6_msg *)p->payload;
+
+  /* parse options */
+
+  options_idx = sizeof(struct dhcp6_msg);
+  /* parse options to the end of the received packet */
+  offset_max = p->tot_len;
+
+  offset = options_idx;
+  /* at least 4 byte to read? */
+  while ((offset + 4 <= offset_max)) {
+    u8_t op_len_buf[4];
+    u8_t *op_len;
+    u16_t op;
+    u16_t len;
+    u16_t val_offset = (u16_t)(offset + 4);
+    if (val_offset < offset) {
+      /* overflow */
+      return ERR_BUF;
+    }
+    /* copy option + length, might be split accross pbufs */
+    op_len = (u8_t *)pbuf_get_contiguous(p, op_len_buf, 4, 4, offset);
+    if (op_len == NULL) {
+      /* failed to get option and length */
+      return ERR_VAL;
+    }
+    op = (op_len[0] << 8) | op_len[1];
+    len = (op_len[2] << 8) | op_len[3];
+    offset = val_offset + len;
+    if (offset < val_offset) {
+      /* overflow */
+      return ERR_BUF;
+    }
+
+    switch (op) {
+      case (DHCP6_OPTION_CLIENTID):
+        dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_CLI_ID);
+        dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_CLI_ID, val_offset, len);
+        break;
+      case (DHCP6_OPTION_SERVERID):
+        dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_SERVER_ID);
+        dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_SERVER_ID, val_offset, len);
+        break;
+#if LWIP_DHCP6_PROVIDE_DNS_SERVERS
+      case (DHCP6_OPTION_DNS_SERVERS):
+        dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER);
+        dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER, val_offset, len);
+        break;
+      case (DHCP6_OPTION_DOMAIN_LIST):
+        dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_DOMAIN_LIST);
+        dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_DOMAIN_LIST, val_offset, len);
+        break;
+#endif /* LWIP_DHCP6_PROVIDE_DNS_SERVERS */
+#if LWIP_DHCP6_GET_NTP_SRV
+      case (DHCP6_OPTION_SNTP_SERVERS):
+        dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER);
+        dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER, val_offset, len);
+        break;
+#endif /* LWIP_DHCP6_GET_NTP_SRV*/
+      default:
+        LWIP_DEBUGF(DHCP6_DEBUG, ("skipping option %"U16_F" in options\n", op));
+        LWIP_HOOK_DHCP6_PARSE_OPTION(ip_current_netif(), dhcp6, dhcp6->state, msg_in,
+          msg_in->msgtype, op, len, q, val_offset);
+        break;
+    }
+  }
+  return ERR_OK;
+}
+
+static void
+dhcp6_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
+{
+  struct netif *netif = ip_current_input_netif();
+  struct dhcp6 *dhcp6 = netif_dhcp6_data(netif);
+  struct dhcp6_msg *reply_msg = (struct dhcp6_msg *)p->payload;
+  u8_t msg_type;
+  u32_t xid;
+
+  LWIP_UNUSED_ARG(arg);
+
+  /* Caught DHCPv6 message from netif that does not have DHCPv6 enabled? -> not interested */
+  if ((dhcp6 == NULL) || (dhcp6->pcb_allocated == 0)) {
+    goto free_pbuf_and_return;
+  }
+
+  LWIP_ERROR("invalid server address type", IP_IS_V6(addr), goto free_pbuf_and_return;);
+
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_recv(pbuf = %p) from DHCPv6 server %s port %"U16_F"\n", (void *)p,
+    ipaddr_ntoa(addr), port));
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+
+  if (p->len < sizeof(struct dhcp6_msg)) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCPv6 reply message or pbuf too short\n"));
+    goto free_pbuf_and_return;
+  }
+
+  /* match transaction ID against what we expected */
+  xid = reply_msg->transaction_id[0] << 16;
+  xid |= reply_msg->transaction_id[1] << 8;
+  xid |= reply_msg->transaction_id[2];
+  if (xid != dhcp6->xid) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                ("transaction id mismatch reply_msg->xid(%"X32_F")!= dhcp6->xid(%"X32_F")\n", xid, dhcp6->xid));
+    goto free_pbuf_and_return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp6_parse_reply(p, dhcp6) != ERR_OK) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+                ("problem unfolding DHCPv6 message - too short on memory?\n"));
+    goto free_pbuf_and_return;
+  }
+
+  /* read DHCP message type */
+  msg_type = reply_msg->msgtype;
+  /* message type is DHCP6 REPLY? */
+  if (msg_type == DHCP6_REPLY) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("DHCP6_REPLY received\n"));
+#if LWIP_IPV6_DHCP6_STATELESS
+    /* in info-requesting state? */
+    if (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG) {
+      dhcp6_set_state(dhcp6, DHCP6_STATE_STATELESS_IDLE, "dhcp6_recv");
+      dhcp6_handle_config_reply(netif, p);
+    } else
+#endif /* LWIP_IPV6_DHCP6_STATELESS */
+    {
+      /* @todo: handle reply in other states? */
+    }
+  } else {
+    /* @todo: handle other message types */
+  }
+
+free_pbuf_and_return:
+  pbuf_free(p);
+}
+
+/**
+ * A DHCPv6 request has timed out.
+ *
+ * The timer that was started with the DHCPv6 request has
+ * timed out, indicating no response was received in time.
+ */
+static void
+dhcp6_timeout(struct netif *netif, struct dhcp6 *dhcp6)
+{
+  LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_timeout()\n"));
+
+  LWIP_UNUSED_ARG(netif);
+  LWIP_UNUSED_ARG(dhcp6);
+
+#if LWIP_IPV6_DHCP6_STATELESS
+  /* back-off period has passed, or server selection timed out */
+  if (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG) {
+    LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_timeout(): retrying information request\n"));
+    dhcp6_information_request(netif, dhcp6);
+  }
+#endif /* LWIP_IPV6_DHCP6_STATELESS */
+}
+
+/**
+ * DHCPv6 timeout handling (this function must be called every 500ms,
+ * see @ref DHCP6_TIMER_MSECS).
+ *
+ * A DHCPv6 server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCPv6 request is timed out.
+ */
+void
+dhcp6_tmr(void)
+{
+  struct netif *netif;
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    struct dhcp6 *dhcp6 = netif_dhcp6_data(netif);
+    /* only act on DHCPv6 configured interfaces */
+    if (dhcp6 != NULL) {
+      /* timer is active (non zero), and is about to trigger now */
+      if (dhcp6->request_timeout > 1) {
+        dhcp6->request_timeout--;
+      } else if (dhcp6->request_timeout == 1) {
+        dhcp6->request_timeout--;
+        /* { dhcp6->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_tmr(): request timeout\n"));
+        /* this client's request timeout triggered */
+        dhcp6_timeout(netif, dhcp6);
+      }
+    }
+  }
+}
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_DHCP6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ethip6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ethip6.c
new file mode 100644
index 000000000..fec8b28a9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ethip6.c
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * Ethernet output for IPv6. Uses ND tables for link-layer addressing.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_ETHERNET
+
+#include "lwip/ethip6.h"
+#include "lwip/nd6.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp6.h"
+#include "lwip/prot/ethernet.h"
+#include "netif/ethernet.h"
+
+#include <string.h>
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing IPv6 packet.
+ *
+ * For IPv6 multicast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, ask the ND6 module what to do. It will either let us
+ * send the the packet right away, or queue the packet for later itself, unless
+ * an error occurs.
+ *
+ * @todo anycast addresses
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ip6addr The IP address of the packet destination.
+ *
+ * @return
+ * - ERR_OK or the return value of @ref nd6_get_next_hop_addr_or_queue.
+ */
+err_t
+ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr)
+{
+  struct eth_addr dest;
+  const u8_t *hwaddr;
+  err_t result;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* The destination IP address must be properly zoned from here on down. */
+  IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif);
+
+  /* multicast destination IP address? */
+  if (ip6_addr_ismulticast(ip6addr)) {
+    /* Hash IP multicast address to MAC address.*/
+    dest.addr[0] = 0x33;
+    dest.addr[1] = 0x33;
+    dest.addr[2] = ((const u8_t *)(&(ip6addr->addr[3])))[0];
+    dest.addr[3] = ((const u8_t *)(&(ip6addr->addr[3])))[1];
+    dest.addr[4] = ((const u8_t *)(&(ip6addr->addr[3])))[2];
+    dest.addr[5] = ((const u8_t *)(&(ip6addr->addr[3])))[3];
+
+    /* Send out. */
+    return ethernet_output(netif, q, (const struct eth_addr*)(netif->hwaddr), &dest, ETHTYPE_IPV6);
+  }
+
+  /* We have a unicast destination IP address */
+  /* @todo anycast? */
+
+  /* Ask ND6 what to do with the packet. */
+  result = nd6_get_next_hop_addr_or_queue(netif, q, ip6addr, &hwaddr);
+  if (result != ERR_OK) {
+    return result;
+  }
+
+  /* If no hardware address is returned, nd6 has queued the packet for later. */
+  if (hwaddr == NULL) {
+    return ERR_OK;
+  }
+
+  /* Send out the packet using the returned hardware address. */
+  SMEMCPY(dest.addr, hwaddr, 6);
+  return ethernet_output(netif, q, (const struct eth_addr*)(netif->hwaddr), &dest, ETHTYPE_IPV6);
+}
+
+#endif /* LWIP_IPV6 && LWIP_ETHERNET */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/icmp6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/icmp6.c
new file mode 100644
index 000000000..167738a05
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/icmp6.c
@@ -0,0 +1,425 @@
+/**
+ * @file
+ *
+ * IPv6 version of ICMP, as per RFC 4443.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/icmp6.h"
+#include "lwip/prot/icmp6.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/nd6.h"
+#include "lwip/mld6.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+#if LWIP_ICMP6_DATASIZE == 0
+#undef LWIP_ICMP6_DATASIZE
+#define LWIP_ICMP6_DATASIZE   8
+#endif
+
+/* Forward declarations */
+static void icmp6_send_response(struct pbuf *p, u8_t code, u32_t data, u8_t type);
+static void icmp6_send_response_with_addrs(struct pbuf *p, u8_t code, u32_t data,
+    u8_t type, const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr);
+static void icmp6_send_response_with_addrs_and_netif(struct pbuf *p, u8_t code, u32_t data,
+    u8_t type, const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr, struct netif *netif);
+
+
+/**
+ * Process an input ICMPv6 message. Called by ip6_input.
+ *
+ * Will generate a reply for echo requests. Other messages are forwarded
+ * to nd6_input, or mld6_input.
+ *
+ * @param p the mld packet, p->payload pointing to the icmpv6 header
+ * @param inp the netif on which this packet was received
+ */
+void
+icmp6_input(struct pbuf *p, struct netif *inp)
+{
+  struct icmp6_hdr *icmp6hdr;
+  struct pbuf *r;
+  const ip6_addr_t *reply_src;
+
+  ICMP6_STATS_INC(icmp6.recv);
+
+  /* Check that ICMPv6 header fits in payload */
+  if (p->len < sizeof(struct icmp6_hdr)) {
+    /* drop short packets */
+    pbuf_free(p);
+    ICMP6_STATS_INC(icmp6.lenerr);
+    ICMP6_STATS_INC(icmp6.drop);
+    return;
+  }
+
+  icmp6hdr = (struct icmp6_hdr *)p->payload;
+
+#if CHECKSUM_CHECK_ICMP6
+  IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP6) {
+    if (ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->tot_len, ip6_current_src_addr(),
+                          ip6_current_dest_addr()) != 0) {
+      /* Checksum failed */
+      pbuf_free(p);
+      ICMP6_STATS_INC(icmp6.chkerr);
+      ICMP6_STATS_INC(icmp6.drop);
+      return;
+    }
+  }
+#endif /* CHECKSUM_CHECK_ICMP6 */
+
+  switch (icmp6hdr->type) {
+  case ICMP6_TYPE_NA: /* Neighbor advertisement */
+  case ICMP6_TYPE_NS: /* Neighbor solicitation */
+  case ICMP6_TYPE_RA: /* Router advertisement */
+  case ICMP6_TYPE_RD: /* Redirect */
+  case ICMP6_TYPE_PTB: /* Packet too big */
+    nd6_input(p, inp);
+    return;
+  case ICMP6_TYPE_RS:
+#if LWIP_IPV6_FORWARD
+    /* @todo implement router functionality */
+#endif
+    break;
+#if LWIP_IPV6_MLD
+  case ICMP6_TYPE_MLQ:
+  case ICMP6_TYPE_MLR:
+  case ICMP6_TYPE_MLD:
+    mld6_input(p, inp);
+    return;
+#endif
+  case ICMP6_TYPE_EREQ:
+#if !LWIP_MULTICAST_PING
+    /* multicast destination address? */
+    if (ip6_addr_ismulticast(ip6_current_dest_addr())) {
+      /* drop */
+      pbuf_free(p);
+      ICMP6_STATS_INC(icmp6.drop);
+      return;
+    }
+#endif /* LWIP_MULTICAST_PING */
+
+    /* Allocate reply. */
+    r = pbuf_alloc(PBUF_IP, p->tot_len, PBUF_RAM);
+    if (r == NULL) {
+      /* drop */
+      pbuf_free(p);
+      ICMP6_STATS_INC(icmp6.memerr);
+      return;
+    }
+
+    /* Copy echo request. */
+    if (pbuf_copy(r, p) != ERR_OK) {
+      /* drop */
+      pbuf_free(p);
+      pbuf_free(r);
+      ICMP6_STATS_INC(icmp6.err);
+      return;
+    }
+
+    /* Determine reply source IPv6 address. */
+#if LWIP_MULTICAST_PING
+    if (ip6_addr_ismulticast(ip6_current_dest_addr())) {
+      reply_src = ip_2_ip6(ip6_select_source_address(inp, ip6_current_src_addr()));
+      if (reply_src == NULL) {
+        /* drop */
+        pbuf_free(p);
+        pbuf_free(r);
+        ICMP6_STATS_INC(icmp6.rterr);
+        return;
+      }
+    }
+    else
+#endif /* LWIP_MULTICAST_PING */
+    {
+      reply_src = ip6_current_dest_addr();
+    }
+
+    /* Set fields in reply. */
+    ((struct icmp6_echo_hdr *)(r->payload))->type = ICMP6_TYPE_EREP;
+    ((struct icmp6_echo_hdr *)(r->payload))->chksum = 0;
+#if CHECKSUM_GEN_ICMP6
+    IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP6) {
+      ((struct icmp6_echo_hdr *)(r->payload))->chksum = ip6_chksum_pseudo(r,
+          IP6_NEXTH_ICMP6, r->tot_len, reply_src, ip6_current_src_addr());
+    }
+#endif /* CHECKSUM_GEN_ICMP6 */
+
+    /* Send reply. */
+    ICMP6_STATS_INC(icmp6.xmit);
+    ip6_output_if(r, reply_src, ip6_current_src_addr(),
+        LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, inp);
+    pbuf_free(r);
+
+    break;
+  default:
+    ICMP6_STATS_INC(icmp6.proterr);
+    ICMP6_STATS_INC(icmp6.drop);
+    break;
+  }
+
+  pbuf_free(p);
+}
+
+
+/**
+ * Send an icmpv6 'destination unreachable' packet.
+ *
+ * This function must be used only in direct response to a packet that is being
+ * received right now. Otherwise, address zones would be lost.
+ *
+ * @param p the input packet for which the 'unreachable' should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param c ICMPv6 code for the unreachable type
+ */
+void
+icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c)
+{
+  icmp6_send_response(p, c, 0, ICMP6_TYPE_DUR);
+}
+
+/**
+ * Send an icmpv6 'packet too big' packet.
+ *
+ * This function must be used only in direct response to a packet that is being
+ * received right now. Otherwise, address zones would be lost.
+ *
+ * @param p the input packet for which the 'packet too big' should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param mtu the maximum mtu that we can accept
+ */
+void
+icmp6_packet_too_big(struct pbuf *p, u32_t mtu)
+{
+  icmp6_send_response(p, 0, mtu, ICMP6_TYPE_PTB);
+}
+
+/**
+ * Send an icmpv6 'time exceeded' packet.
+ *
+ * This function must be used only in direct response to a packet that is being
+ * received right now. Otherwise, address zones would be lost.
+ *
+ * @param p the input packet for which the 'time exceeded' should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param c ICMPv6 code for the time exceeded type
+ */
+void
+icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c)
+{
+  icmp6_send_response(p, c, 0, ICMP6_TYPE_TE);
+}
+
+/**
+ * Send an icmpv6 'time exceeded' packet, with explicit source and destination
+ * addresses.
+ *
+ * This function may be used to send a response sometime after receiving the
+ * packet for which this response is meant. The provided source and destination
+ * addresses are used primarily to retain their zone information.
+ *
+ * @param p the input packet for which the 'time exceeded' should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param c ICMPv6 code for the time exceeded type
+ * @param src_addr source address of the original packet, with zone information
+ * @param dest_addr destination address of the original packet, with zone
+ *                  information
+ */
+void
+icmp6_time_exceeded_with_addrs(struct pbuf *p, enum icmp6_te_code c,
+    const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr)
+{
+  icmp6_send_response_with_addrs(p, c, 0, ICMP6_TYPE_TE, src_addr, dest_addr);
+}
+
+/**
+ * Send an icmpv6 'parameter problem' packet.
+ *
+ * This function must be used only in direct response to a packet that is being
+ * received right now. Otherwise, address zones would be lost and the calculated
+ * offset would be wrong (calculated against ip6_current_header()).
+ *
+ * @param p the input packet for which the 'param problem' should be sent,
+ *          p->payload pointing to the IP header
+ * @param c ICMPv6 code for the param problem type
+ * @param pointer the pointer to the byte where the parameter is found
+ */
+void
+icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, const void *pointer)
+{
+  u32_t pointer_u32 = (u32_t)((const u8_t *)pointer - (const u8_t *)ip6_current_header());
+  icmp6_send_response(p, c, pointer_u32, ICMP6_TYPE_PP);
+}
+
+/**
+ * Send an ICMPv6 packet in response to an incoming packet.
+ * The packet is sent *to* ip_current_src_addr() on ip_current_netif().
+ *
+ * @param p the input packet for which the response should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param code Code of the ICMPv6 header
+ * @param data Additional 32-bit parameter in the ICMPv6 header
+ * @param type Type of the ICMPv6 header
+ */
+static void
+icmp6_send_response(struct pbuf *p, u8_t code, u32_t data, u8_t type)
+{
+  const struct ip6_addr *reply_src, *reply_dest;
+  struct netif *netif = ip_current_netif();
+
+  LWIP_ASSERT("icmpv6 packet not a direct response", netif != NULL);
+  reply_dest = ip6_current_src_addr();
+
+  /* Select an address to use as source. */
+  reply_src = ip_2_ip6(ip6_select_source_address(netif, reply_dest));
+  if (reply_src == NULL) {
+    ICMP6_STATS_INC(icmp6.rterr);
+    return;
+  }
+  icmp6_send_response_with_addrs_and_netif(p, code, data, type, reply_src, reply_dest, netif);
+}
+
+/**
+ * Send an ICMPv6 packet in response to an incoming packet.
+ *
+ * Call this function if the packet is NOT sent as a direct response to an
+ * incoming packet, but rather sometime later (e.g. for a fragment reassembly
+ * timeout). The caller must provide the zoned source and destination addresses
+ * from the original packet with the src_addr and dest_addr parameters. The
+ * reason for this approach is that while the addresses themselves are part of
+ * the original packet, their zone information is not, thus possibly resulting
+ * in a link-local response being sent over the wrong link.
+ *
+ * @param p the input packet for which the response should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param code Code of the ICMPv6 header
+ * @param data Additional 32-bit parameter in the ICMPv6 header
+ * @param type Type of the ICMPv6 header
+ * @param src_addr original source address
+ * @param dest_addr original destination address
+ */
+static void
+icmp6_send_response_with_addrs(struct pbuf *p, u8_t code, u32_t data, u8_t type,
+    const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr)
+{
+  const struct ip6_addr *reply_src, *reply_dest;
+  struct netif *netif;
+
+  /* Get the destination address and netif for this ICMP message. */
+  LWIP_ASSERT("must provide both source and destination", src_addr != NULL);
+  LWIP_ASSERT("must provide both source and destination", dest_addr != NULL);
+
+  /* Special case, as ip6_current_xxx is either NULL, or points
+     to a different packet than the one that expired. */
+  IP6_ADDR_ZONECHECK(src_addr);
+  IP6_ADDR_ZONECHECK(dest_addr);
+  /* Swap source and destination for the reply. */
+  reply_dest = src_addr;
+  reply_src = dest_addr;
+  netif = ip6_route(reply_src, reply_dest);
+  if (netif == NULL) {
+    ICMP6_STATS_INC(icmp6.rterr);
+    return;
+  }
+  icmp6_send_response_with_addrs_and_netif(p, code, data, type, reply_src,
+    reply_dest, netif);
+}
+
+/**
+ * Send an ICMPv6 packet (with srd/dst address and netif given).
+ *
+ * @param p the input packet for which the response should be sent,
+ *          p->payload pointing to the IPv6 header
+ * @param code Code of the ICMPv6 header
+ * @param data Additional 32-bit parameter in the ICMPv6 header
+ * @param type Type of the ICMPv6 header
+ * @param reply_src source address of the packet to send
+ * @param reply_dest destination address of the packet to send
+ * @param netif netif to send the packet
+ */
+static void
+icmp6_send_response_with_addrs_and_netif(struct pbuf *p, u8_t code, u32_t data, u8_t type,
+    const ip6_addr_t *reply_src, const ip6_addr_t *reply_dest, struct netif *netif)
+{
+  struct pbuf *q;
+  struct icmp6_hdr *icmp6hdr;
+
+  /* ICMPv6 header + IPv6 header + data */
+  q = pbuf_alloc(PBUF_IP, sizeof(struct icmp6_hdr) + IP6_HLEN + LWIP_ICMP6_DATASIZE,
+                 PBUF_RAM);
+  if (q == NULL) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMPv6 packet.\n"));
+    ICMP6_STATS_INC(icmp6.memerr);
+    return;
+  }
+  LWIP_ASSERT("check that first pbuf can hold icmp 6message",
+             (q->len >= (sizeof(struct icmp6_hdr) + IP6_HLEN + LWIP_ICMP6_DATASIZE)));
+
+  icmp6hdr = (struct icmp6_hdr *)q->payload;
+  icmp6hdr->type = type;
+  icmp6hdr->code = code;
+  icmp6hdr->data = lwip_htonl(data);
+
+  /* copy fields from original packet */
+  SMEMCPY((u8_t *)q->payload + sizeof(struct icmp6_hdr), (u8_t *)p->payload,
+          IP6_HLEN + LWIP_ICMP6_DATASIZE);
+
+  /* calculate checksum */
+  icmp6hdr->chksum = 0;
+#if CHECKSUM_GEN_ICMP6
+  IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) {
+    icmp6hdr->chksum = ip6_chksum_pseudo(q, IP6_NEXTH_ICMP6, q->tot_len,
+      reply_src, reply_dest);
+  }
+#endif /* CHECKSUM_GEN_ICMP6 */
+
+  ICMP6_STATS_INC(icmp6.xmit);
+  ip6_output_if(q, reply_src, reply_dest, LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, netif);
+  pbuf_free(q);
+}
+
+#endif /* LWIP_ICMP6 && LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/inet6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/inet6.c
new file mode 100644
index 000000000..d9a992c22
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/inet6.c
@@ -0,0 +1,53 @@
+/**
+ * @file
+ *
+ * INET v6 addresses.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+/** This variable is initialized by the system to contain the wildcard IPv6 address.
+ */
+const struct in6_addr in6addr_any = IN6ADDR_ANY_INIT;
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6.c
new file mode 100644
index 000000000..eda11dc88
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6.c
@@ -0,0 +1,1492 @@
+/**
+ * @file
+ *
+ * IPv6 layer.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/ip6_frag.h"
+#include "lwip/icmp6.h"
+#include "lwip/priv/raw_priv.h"
+#include "lwip/udp.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/dhcp6.h"
+#include "lwip/nd6.h"
+#include "lwip/mld6.h"
+#include "lwip/debug.h"
+#include "lwip/stats.h"
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/**
+ * Finds the appropriate network interface for a given IPv6 address. It tries to select
+ * a netif following a sequence of heuristics:
+ * 1) if there is only 1 netif, return it
+ * 2) if the destination is a zoned address, match its zone to a netif
+ * 3) if the either the source or destination address is a scoped address,
+ *    match the source address's zone (if set) or address (if not) to a netif
+ * 4) tries to match the destination subnet to a configured address
+ * 5) tries to find a router-announced route
+ * 6) tries to match the (unscoped) source address to the netif
+ * 7) returns the default netif, if configured
+ *
+ * Note that each of the two given addresses may or may not be properly zoned.
+ *
+ * @param src the source IPv6 address, if known
+ * @param dest the destination IPv6 address for which to find the route
+ * @return the netif on which to send to reach dest
+ */
+struct netif *
+ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest)
+{
+#if LWIP_SINGLE_NETIF
+  LWIP_UNUSED_ARG(src);
+  LWIP_UNUSED_ARG(dest);
+#else /* LWIP_SINGLE_NETIF */
+  struct netif *netif;
+  s8_t i;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* If single netif configuration, fast return. */
+  if ((netif_list != NULL) && (netif_list->next == NULL)) {
+    if (!netif_is_up(netif_list) || !netif_is_link_up(netif_list) ||
+        (ip6_addr_has_zone(dest) && !ip6_addr_test_zone(dest, netif_list))) {
+      return NULL;
+    }
+    return netif_list;
+  }
+
+#if LWIP_IPV6_SCOPES
+  /* Special processing for zoned destination addresses. This includes link-
+   * local unicast addresses and interface/link-local multicast addresses. Use
+   * the zone to find a matching netif. If the address is not zoned, then there
+   * is technically no "wrong" netif to choose, and we leave routing to other
+   * rules; in most cases this should be the scoped-source rule below. */
+  if (ip6_addr_has_zone(dest)) {
+    IP6_ADDR_ZONECHECK(dest);
+    /* Find a netif based on the zone. For custom mappings, one zone may map
+     * to multiple netifs, so find one that can actually send a packet. */
+    NETIF_FOREACH(netif) {
+      if (ip6_addr_test_zone(dest, netif) &&
+          netif_is_up(netif) && netif_is_link_up(netif)) {
+        return netif;
+      }
+    }
+    /* No matching netif found. Do no try to route to a different netif,
+     * as that would be a zone violation, resulting in any packets sent to
+     * that netif being dropped on output. */
+    return NULL;
+  }
+#endif /* LWIP_IPV6_SCOPES */
+
+  /* Special processing for scoped source and destination addresses. If we get
+   * here, the destination address does not have a zone, so either way we need
+   * to look at the source address, which may or may not have a zone. If it
+   * does, the zone is restrictive: there is (typically) only one matching
+   * netif for it, and we should avoid routing to any other netif as that would
+   * result in guaranteed zone violations. For scoped source addresses that do
+   * not have a zone, use (only) a netif that has that source address locally
+   * assigned. This case also applies to the loopback source address, which has
+   * an implied link-local scope. If only the destination address is scoped
+   * (but, again, not zoned), we still want to use only the source address to
+   * determine its zone because that's most likely what the user/application
+   * wants, regardless of whether the source address is scoped. Finally, some
+   * of this story also applies if scoping is disabled altogether. */
+#if LWIP_IPV6_SCOPES
+  if (ip6_addr_has_scope(dest, IP6_UNKNOWN) ||
+      ip6_addr_has_scope(src, IP6_UNICAST) ||
+#else /* LWIP_IPV6_SCOPES */
+  if (ip6_addr_islinklocal(dest) || ip6_addr_ismulticast_iflocal(dest) ||
+      ip6_addr_ismulticast_linklocal(dest) || ip6_addr_islinklocal(src) ||
+#endif /* LWIP_IPV6_SCOPES */
+      ip6_addr_isloopback(src)) {
+#if LWIP_IPV6_SCOPES
+    if (ip6_addr_has_zone(src)) {
+      /* Find a netif matching the source zone (relatively cheap). */
+      NETIF_FOREACH(netif) {
+        if (netif_is_up(netif) && netif_is_link_up(netif) &&
+            ip6_addr_test_zone(src, netif)) {
+          return netif;
+        }
+      }
+    } else
+#endif /* LWIP_IPV6_SCOPES */
+    {
+      /* Find a netif matching the source address (relatively expensive). */
+      NETIF_FOREACH(netif) {
+        if (!netif_is_up(netif) || !netif_is_link_up(netif)) {
+          continue;
+        }
+        for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+          if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) &&
+              ip6_addr_cmp_zoneless(src, netif_ip6_addr(netif, i))) {
+            return netif;
+          }
+        }
+      }
+    }
+    /* Again, do not use any other netif in this case, as that could result in
+     * zone boundary violations. */
+    return NULL;
+  }
+
+  /* We come here only if neither source nor destination is scoped. */
+  IP6_ADDR_ZONECHECK(src);
+
+#ifdef LWIP_HOOK_IP6_ROUTE
+  netif = LWIP_HOOK_IP6_ROUTE(src, dest);
+  if (netif != NULL) {
+    return netif;
+  }
+#endif
+
+  /* See if the destination subnet matches a configured address. In accordance
+   * with RFC 5942, dynamically configured addresses do not have an implied
+   * local subnet, and thus should be considered /128 assignments. However, as
+   * such, the destination address may still match a local address, and so we
+   * still need to check for exact matches here. By (lwIP) policy, statically
+   * configured addresses do always have an implied local /64 subnet. */
+  NETIF_FOREACH(netif) {
+    if (!netif_is_up(netif) || !netif_is_link_up(netif)) {
+      continue;
+    }
+    for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+      if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) &&
+          ip6_addr_netcmp(dest, netif_ip6_addr(netif, i)) &&
+          (netif_ip6_addr_isstatic(netif, i) ||
+          ip6_addr_nethostcmp(dest, netif_ip6_addr(netif, i)))) {
+        return netif;
+      }
+    }
+  }
+
+  /* Get the netif for a suitable router-announced route. */
+  netif = nd6_find_route(dest);
+  if (netif != NULL) {
+    return netif;
+  }
+
+  /* Try with the netif that matches the source address. Given the earlier rule
+   * for scoped source addresses, this applies to unscoped addresses only. */
+  if (!ip6_addr_isany(src)) {
+    NETIF_FOREACH(netif) {
+      if (!netif_is_up(netif) || !netif_is_link_up(netif)) {
+        continue;
+      }
+      for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+        if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) &&
+            ip6_addr_cmp(src, netif_ip6_addr(netif, i))) {
+          return netif;
+        }
+      }
+    }
+  }
+
+#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF
+  /* loopif is disabled, loopback traffic is passed through any netif */
+  if (ip6_addr_isloopback(dest)) {
+    /* don't check for link on loopback traffic */
+    if (netif_default != NULL && netif_is_up(netif_default)) {
+      return netif_default;
+    }
+    /* default netif is not up, just use any netif for loopback traffic */
+    NETIF_FOREACH(netif) {
+      if (netif_is_up(netif)) {
+        return netif;
+      }
+    }
+    return NULL;
+  }
+#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
+#endif /* !LWIP_SINGLE_NETIF */
+
+  /* no matching netif found, use default netif, if up */
+  if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default)) {
+    return NULL;
+  }
+  return netif_default;
+}
+
+/**
+ * @ingroup ip6
+ * Select the best IPv6 source address for a given destination IPv6 address.
+ *
+ * This implementation follows RFC 6724 Sec. 5 to the following extent:
+ * - Rules 1, 2, 3: fully implemented
+ * - Rules 4, 5, 5.5: not applicable
+ * - Rule 6: not implemented
+ * - Rule 7: not applicable
+ * - Rule 8: limited to "prefer /64 subnet match over non-match"
+ *
+ * For Rule 2, we deliberately deviate from RFC 6724 Sec. 3.1 by considering
+ * ULAs to be of smaller scope than global addresses, to avoid that a preferred
+ * ULA is picked over a deprecated global address when given a global address
+ * as destination, as that would likely result in broken two-way communication.
+ *
+ * As long as temporary addresses are not supported (as used in Rule 7), a
+ * proper implementation of Rule 8 would obviate the need to implement Rule 6.
+ *
+ * @param netif the netif on which to send a packet
+ * @param dest the destination we are trying to reach (possibly not properly
+ *             zoned)
+ * @return the most suitable source address to use, or NULL if no suitable
+ *         source address is found
+ */
+const ip_addr_t *
+ip6_select_source_address(struct netif *netif, const ip6_addr_t *dest)
+{
+  const ip_addr_t *best_addr;
+  const ip6_addr_t *cand_addr;
+  s8_t dest_scope, cand_scope;
+  s8_t best_scope = IP6_MULTICAST_SCOPE_RESERVED;
+  u8_t i, cand_pref, cand_bits;
+  u8_t best_pref = 0;
+  u8_t best_bits = 0;
+
+  /* Start by determining the scope of the given destination address. These
+   * tests are hopefully (roughly) in order of likeliness to match. */
+  if (ip6_addr_isglobal(dest)) {
+    dest_scope = IP6_MULTICAST_SCOPE_GLOBAL;
+  } else if (ip6_addr_islinklocal(dest) || ip6_addr_isloopback(dest)) {
+    dest_scope = IP6_MULTICAST_SCOPE_LINK_LOCAL;
+  } else if (ip6_addr_isuniquelocal(dest)) {
+    dest_scope = IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL;
+  } else if (ip6_addr_ismulticast(dest)) {
+    dest_scope = ip6_addr_multicast_scope(dest);
+  } else if (ip6_addr_issitelocal(dest)) {
+    dest_scope = IP6_MULTICAST_SCOPE_SITE_LOCAL;
+  } else {
+    /* no match, consider scope global */
+    dest_scope = IP6_MULTICAST_SCOPE_GLOBAL;
+  }
+
+  best_addr = NULL;
+
+  for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    /* Consider only valid (= preferred and deprecated) addresses. */
+    if (!ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) {
+      continue;
+    }
+    /* Determine the scope of this candidate address. Same ordering idea. */
+    cand_addr = netif_ip6_addr(netif, i);
+    if (ip6_addr_isglobal(cand_addr)) {
+      cand_scope = IP6_MULTICAST_SCOPE_GLOBAL;
+    } else if (ip6_addr_islinklocal(cand_addr)) {
+      cand_scope = IP6_MULTICAST_SCOPE_LINK_LOCAL;
+    } else if (ip6_addr_isuniquelocal(cand_addr)) {
+      cand_scope = IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL;
+    } else if (ip6_addr_issitelocal(cand_addr)) {
+      cand_scope = IP6_MULTICAST_SCOPE_SITE_LOCAL;
+    } else {
+      /* no match, treat as low-priority global scope */
+      cand_scope = IP6_MULTICAST_SCOPE_RESERVEDF;
+    }
+    cand_pref = ip6_addr_ispreferred(netif_ip6_addr_state(netif, i));
+    /* @todo compute the actual common bits, for longest matching prefix. */
+    /* We cannot count on the destination address having a proper zone
+     * assignment, so do not compare zones in this case. */
+    cand_bits = ip6_addr_netcmp_zoneless(cand_addr, dest); /* just 1 or 0 for now */
+    if (cand_bits && ip6_addr_nethostcmp(cand_addr, dest)) {
+      return netif_ip_addr6(netif, i); /* Rule 1 */
+    }
+    if ((best_addr == NULL) || /* no alternative yet */
+        ((cand_scope < best_scope) && (cand_scope >= dest_scope)) ||
+        ((cand_scope > best_scope) && (best_scope < dest_scope)) || /* Rule 2 */
+        ((cand_scope == best_scope) && ((cand_pref > best_pref) || /* Rule 3 */
+        ((cand_pref == best_pref) && (cand_bits > best_bits))))) { /* Rule 8 */
+      /* We found a new "winning" candidate. */
+      best_addr = netif_ip_addr6(netif, i);
+      best_scope = cand_scope;
+      best_pref = cand_pref;
+      best_bits = cand_bits;
+    }
+  }
+
+  return best_addr; /* may be NULL */
+}
+
+#if LWIP_IPV6_FORWARD
+/**
+ * Forwards an IPv6 packet. It finds an appropriate route for the
+ * packet, decrements the HL value of the packet, and outputs
+ * the packet on the appropriate interface.
+ *
+ * @param p the packet to forward (p->payload points to IP header)
+ * @param iphdr the IPv6 header of the input packet
+ * @param inp the netif on which this packet was received
+ */
+static void
+ip6_forward(struct pbuf *p, struct ip6_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  /* do not forward link-local or loopback addresses */
+  if (ip6_addr_islinklocal(ip6_current_dest_addr()) ||
+      ip6_addr_isloopback(ip6_current_dest_addr())) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not forwarding link-local address.\n"));
+    IP6_STATS_INC(ip6.rterr);
+    IP6_STATS_INC(ip6.drop);
+    return;
+  }
+
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip6_route(IP6_ADDR_ANY6, ip6_current_dest_addr());
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n",
+        IP6_ADDR_BLOCK1(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK2(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK3(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK4(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK5(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK6(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK7(ip6_current_dest_addr()),
+        IP6_ADDR_BLOCK8(ip6_current_dest_addr())));
+#if LWIP_ICMP6
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) {
+      icmp6_dest_unreach(p, ICMP6_DUR_NO_ROUTE);
+    }
+#endif /* LWIP_ICMP6 */
+    IP6_STATS_INC(ip6.rterr);
+    IP6_STATS_INC(ip6.drop);
+    return;
+  }
+#if LWIP_IPV6_SCOPES
+  /* Do not forward packets with a zoned (e.g., link-local) source address
+   * outside of their zone. We determined the zone a bit earlier, so we know
+   * that the address is properly zoned here, so we can safely use has_zone.
+   * Also skip packets with a loopback source address (link-local implied). */
+  if ((ip6_addr_has_zone(ip6_current_src_addr()) &&
+      !ip6_addr_test_zone(ip6_current_src_addr(), netif)) ||
+      ip6_addr_isloopback(ip6_current_src_addr())) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not forwarding packet beyond its source address zone.\n"));
+    IP6_STATS_INC(ip6.rterr);
+    IP6_STATS_INC(ip6.drop);
+    return;
+  }
+#endif /* LWIP_IPV6_SCOPES */
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not bouncing packets back on incoming interface.\n"));
+    IP6_STATS_INC(ip6.rterr);
+    IP6_STATS_INC(ip6.drop);
+    return;
+  }
+
+  /* decrement HL */
+  IP6H_HOPLIM_SET(iphdr, IP6H_HOPLIM(iphdr) - 1);
+  /* send ICMP6 if HL == 0 */
+  if (IP6H_HOPLIM(iphdr) == 0) {
+#if LWIP_ICMP6
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) {
+      icmp6_time_exceeded(p, ICMP6_TE_HL);
+    }
+#endif /* LWIP_ICMP6 */
+    IP6_STATS_INC(ip6.drop);
+    return;
+  }
+
+  if (netif->mtu && (p->tot_len > netif->mtu)) {
+#if LWIP_ICMP6
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) {
+      icmp6_packet_too_big(p, netif->mtu);
+    }
+#endif /* LWIP_ICMP6 */
+    IP6_STATS_INC(ip6.drop);
+    return;
+  }
+
+  LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: forwarding packet to %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n",
+      IP6_ADDR_BLOCK1(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK2(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK3(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK4(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK5(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK6(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK7(ip6_current_dest_addr()),
+      IP6_ADDR_BLOCK8(ip6_current_dest_addr())));
+
+  /* transmit pbuf on chosen interface */
+  netif->output_ip6(netif, p, ip6_current_dest_addr());
+  IP6_STATS_INC(ip6.fw);
+  IP6_STATS_INC(ip6.xmit);
+  return;
+}
+#endif /* LWIP_IPV6_FORWARD */
+
+/** Return true if the current input packet should be accepted on this netif */
+static int
+ip6_input_accept(struct netif *netif)
+{
+  /* interface is up? */
+  if (netif_is_up(netif)) {
+    u8_t i;
+    /* unicast to this interface address? address configured? */
+    /* If custom scopes are used, the destination zone will be tested as
+      * part of the local-address comparison, but we need to test the source
+      * scope as well (e.g., is this interface on the same link?). */
+    for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+      if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) &&
+          ip6_addr_cmp(ip6_current_dest_addr(), netif_ip6_addr(netif, i))
+#if IPV6_CUSTOM_SCOPES
+          && (!ip6_addr_has_zone(ip6_current_src_addr()) ||
+              ip6_addr_test_zone(ip6_current_src_addr(), netif))
+#endif /* IPV6_CUSTOM_SCOPES */
+      ) {
+        /* accept on this netif */
+        return 1;
+      }
+    }
+  }
+  return 0;
+}
+
+/**
+ * This function is called by the network interface device driver when
+ * an IPv6 packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip6_forward).
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ *
+ * @param p the received IPv6 packet (p->payload points to IPv6 header)
+ * @param inp the netif on which this packet was received
+ * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
+ *         processed, but currently always returns ERR_OK)
+ */
+err_t
+ip6_input(struct pbuf *p, struct netif *inp)
+{
+  struct ip6_hdr *ip6hdr;
+  struct netif *netif;
+  const u8_t *nexth;
+  u16_t hlen, hlen_tot; /* the current header length */
+#if 0 /*IP_ACCEPT_LINK_LAYER_ADDRESSING*/
+  @todo
+  int check_ip_src=1;
+#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
+#if LWIP_RAW
+  raw_input_state_t raw_status;
+#endif /* LWIP_RAW */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  IP6_STATS_INC(ip6.recv);
+
+  /* identify the IP header */
+  ip6hdr = (struct ip6_hdr *)p->payload;
+  if (IP6H_V(ip6hdr) != 6) {
+    LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IPv6 packet dropped due to bad version number %"U32_F"\n",
+        IP6H_V(ip6hdr)));
+    pbuf_free(p);
+    IP6_STATS_INC(ip6.err);
+    IP6_STATS_INC(ip6.drop);
+    return ERR_OK;
+  }
+
+#ifdef LWIP_HOOK_IP6_INPUT
+  if (LWIP_HOOK_IP6_INPUT(p, inp)) {
+    /* the packet has been eaten */
+    return ERR_OK;
+  }
+#endif
+
+  /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
+  if ((IP6_HLEN > p->len) || (IP6H_PLEN(ip6hdr) > (p->tot_len - IP6_HLEN))) {
+    if (IP6_HLEN > p->len) {
+      LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("IPv6 header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n",
+            (u16_t)IP6_HLEN, p->len));
+    }
+    if ((IP6H_PLEN(ip6hdr) + IP6_HLEN) > p->tot_len) {
+      LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+        ("IPv6 (plen %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
+            (u16_t)(IP6H_PLEN(ip6hdr) + IP6_HLEN), p->tot_len));
+    }
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP6_STATS_INC(ip6.lenerr);
+    IP6_STATS_INC(ip6.drop);
+    return ERR_OK;
+  }
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, (u16_t)(IP6_HLEN + IP6H_PLEN(ip6hdr)));
+
+  /* copy IP addresses to aligned ip6_addr_t */
+  ip_addr_copy_from_ip6_packed(ip_data.current_iphdr_dest, ip6hdr->dest);
+  ip_addr_copy_from_ip6_packed(ip_data.current_iphdr_src, ip6hdr->src);
+
+  /* Don't accept virtual IPv4 mapped IPv6 addresses.
+   * Don't accept multicast source addresses. */
+  if (ip6_addr_isipv4mappedipv6(ip_2_ip6(&ip_data.current_iphdr_dest)) ||
+     ip6_addr_isipv4mappedipv6(ip_2_ip6(&ip_data.current_iphdr_src)) ||
+     ip6_addr_ismulticast(ip_2_ip6(&ip_data.current_iphdr_src))) {
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP6_STATS_INC(ip6.err);
+    IP6_STATS_INC(ip6.drop);
+    return ERR_OK;
+  }
+
+  /* Set the appropriate zone identifier on the addresses. */
+  ip6_addr_assign_zone(ip_2_ip6(&ip_data.current_iphdr_dest), IP6_UNKNOWN, inp);
+  ip6_addr_assign_zone(ip_2_ip6(&ip_data.current_iphdr_src), IP6_UNICAST, inp);
+
+  /* current header pointer. */
+  ip_data.current_ip6_header = ip6hdr;
+
+  /* In netif, used in case we need to send ICMPv6 packets back. */
+  ip_data.current_netif = inp;
+  ip_data.current_input_netif = inp;
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  if (ip6_addr_ismulticast(ip6_current_dest_addr())) {
+    /* Always joined to multicast if-local and link-local all-nodes group. */
+    if (ip6_addr_isallnodes_iflocal(ip6_current_dest_addr()) ||
+        ip6_addr_isallnodes_linklocal(ip6_current_dest_addr())) {
+      netif = inp;
+    }
+#if LWIP_IPV6_MLD
+    else if (mld6_lookfor_group(inp, ip6_current_dest_addr())) {
+      netif = inp;
+    }
+#else /* LWIP_IPV6_MLD */
+    else if (ip6_addr_issolicitednode(ip6_current_dest_addr())) {
+      u8_t i;
+      /* Filter solicited node packets when MLD is not enabled
+       * (for Neighbor discovery). */
+      netif = NULL;
+      for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+        if (ip6_addr_isvalid(netif_ip6_addr_state(inp, i)) &&
+            ip6_addr_cmp_solicitednode(ip6_current_dest_addr(), netif_ip6_addr(inp, i))) {
+          netif = inp;
+          LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: solicited node packet accepted on interface %c%c\n",
+              netif->name[0], netif->name[1]));
+          break;
+        }
+      }
+    }
+#endif /* LWIP_IPV6_MLD */
+    else {
+      netif = NULL;
+    }
+  } else {
+    /* start trying with inp. if that's not acceptable, start walking the
+       list of configured netifs. */
+    if (ip6_input_accept(inp)) {
+      netif = inp;
+    } else {
+      netif = NULL;
+#if !IPV6_CUSTOM_SCOPES
+      /* Shortcut: stop looking for other interfaces if either the source or
+        * the destination has a scope constrained to this interface. Custom
+        * scopes may break the 1:1 link/interface mapping, however. */
+      if (ip6_addr_islinklocal(ip6_current_dest_addr()) ||
+          ip6_addr_islinklocal(ip6_current_src_addr())) {
+        goto netif_found;
+      }
+#endif /* !IPV6_CUSTOM_SCOPES */
+#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
+      /* The loopback address is to be considered link-local. Packets to it
+        * should be dropped on other interfaces, as per RFC 4291 Sec. 2.5.3.
+        * Its implied scope means packets *from* the loopback address should
+        * not be accepted on other interfaces, either. These requirements
+        * cannot be implemented in the case that loopback traffic is sent
+        * across a non-loopback interface, however. */
+      if (ip6_addr_isloopback(ip6_current_dest_addr()) ||
+          ip6_addr_isloopback(ip6_current_src_addr())) {
+        goto netif_found;
+      }
+#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
+#if !LWIP_SINGLE_NETIF
+      NETIF_FOREACH(netif) {
+        if (netif == inp) {
+          /* we checked that before already */
+          continue;
+        }
+        if (ip6_input_accept(netif)) {
+          break;
+        }
+      }
+#endif /* !LWIP_SINGLE_NETIF */
+    }
+netif_found:
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet accepted on interface %c%c\n",
+        netif ? netif->name[0] : 'X', netif? netif->name[1] : 'X'));
+  }
+
+  /* "::" packet source address? (used in duplicate address detection) */
+  if (ip6_addr_isany(ip6_current_src_addr()) &&
+      (!ip6_addr_issolicitednode(ip6_current_dest_addr()))) {
+    /* packet source is not valid */
+    /* free (drop) packet pbufs */
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with src ANY_ADDRESS dropped\n"));
+    pbuf_free(p);
+    IP6_STATS_INC(ip6.drop);
+    goto ip6_input_cleanup;
+  }
+
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_TRACE, ("ip6_input: packet not for us.\n"));
+#if LWIP_IPV6_FORWARD
+    /* non-multicast packet? */
+    if (!ip6_addr_ismulticast(ip6_current_dest_addr())) {
+      /* try to forward IP packet on (other) interfaces */
+      ip6_forward(p, ip6hdr, inp);
+    }
+#endif /* LWIP_IPV6_FORWARD */
+    pbuf_free(p);
+    goto ip6_input_cleanup;
+  }
+
+  /* current netif pointer. */
+  ip_data.current_netif = netif;
+
+  /* Save next header type. */
+  nexth = &IP6H_NEXTH(ip6hdr);
+
+  /* Init header length. */
+  hlen = hlen_tot = IP6_HLEN;
+
+  /* Move to payload. */
+  pbuf_remove_header(p, IP6_HLEN);
+
+  /* Process known option extension headers, if present. */
+  while (*nexth != IP6_NEXTH_NONE)
+  {
+    switch (*nexth) {
+    case IP6_NEXTH_HOPBYHOP:
+    {
+      s32_t opt_offset;
+      struct ip6_hbh_hdr *hbh_hdr;
+      struct ip6_opt_hdr *opt_hdr;
+      LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Hop-by-Hop options header\n"));
+
+      /* Get and check the header length, while staying in packet bounds. */
+      hbh_hdr = (struct ip6_hbh_hdr *)p->payload;
+
+      /* Get next header type. */
+      nexth = &IP6_HBH_NEXTH(hbh_hdr);
+
+      /* Get the header length. */
+      hlen = (u16_t)(8 * (1 + hbh_hdr->_hlen));
+
+      if ((p->len < 8) || (hlen > p->len)) {
+        LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+          ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n",
+              hlen, p->len));
+        /* free (drop) packet pbufs */
+        pbuf_free(p);
+        IP6_STATS_INC(ip6.lenerr);
+        IP6_STATS_INC(ip6.drop);
+        goto ip6_input_cleanup;
+      }
+
+      hlen_tot = (u16_t)(hlen_tot + hlen);
+
+      /* The extended option header starts right after Hop-by-Hop header. */
+      opt_offset = IP6_HBH_HLEN;
+      while (opt_offset < hlen)
+      {
+        s32_t opt_dlen = 0;
+
+        opt_hdr = (struct ip6_opt_hdr *)((u8_t *)hbh_hdr + opt_offset);
+
+        switch (IP6_OPT_TYPE(opt_hdr)) {
+        /* @todo: process IPV6 Hop-by-Hop option data */
+        case IP6_PAD1_OPTION:
+          /* PAD1 option doesn't have length and value field */
+          opt_dlen = -1;
+          break;
+        case IP6_PADN_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        case IP6_ROUTER_ALERT_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        case IP6_JUMBO_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        default:
+          /* Check 2 MSB of Hop-by-Hop header type. */
+          switch (IP6_OPT_TYPE_ACTION(opt_hdr)) {
+          case 1:
+            /* Discard the packet. */
+            LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid Hop-by-Hop option type dropped.\n"));
+            pbuf_free(p);
+            IP6_STATS_INC(ip6.drop);
+            goto ip6_input_cleanup;
+          case 2:
+            /* Send ICMP Parameter Problem */
+            icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr);
+            LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid Hop-by-Hop option type dropped.\n"));
+            pbuf_free(p);
+            IP6_STATS_INC(ip6.drop);
+            goto ip6_input_cleanup;
+          case 3:
+            /* Send ICMP Parameter Problem if destination address is not a multicast address */
+            if (!ip6_addr_ismulticast(ip6_current_dest_addr())) {
+              icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr);
+            }
+            LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid Hop-by-Hop option type dropped.\n"));
+            pbuf_free(p);
+            IP6_STATS_INC(ip6.drop);
+            goto ip6_input_cleanup;
+          default:
+            /* Skip over this option. */
+            opt_dlen = IP6_OPT_DLEN(opt_hdr);
+            break;
+          }
+          break;
+        }
+
+        /* Adjust the offset to move to the next extended option header */
+        opt_offset = opt_offset + IP6_OPT_HLEN + opt_dlen;
+      }
+      pbuf_remove_header(p, hlen);
+      break;
+    }
+    case IP6_NEXTH_DESTOPTS:
+    {
+      s32_t opt_offset;
+      struct ip6_dest_hdr *dest_hdr;
+      struct ip6_opt_hdr *opt_hdr;
+      LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Destination options header\n"));
+
+      dest_hdr = (struct ip6_dest_hdr *)p->payload;
+
+      /* Get next header type. */
+      nexth = &IP6_DEST_NEXTH(dest_hdr);
+
+      /* Get the header length. */
+      hlen = 8 * (1 + dest_hdr->_hlen);
+      if ((p->len < 8) || (hlen > p->len)) {
+        LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+          ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n",
+              hlen, p->len));
+        /* free (drop) packet pbufs */
+        pbuf_free(p);
+        IP6_STATS_INC(ip6.lenerr);
+        IP6_STATS_INC(ip6.drop);
+        goto ip6_input_cleanup;
+      }
+
+      hlen_tot = (u16_t)(hlen_tot + hlen);
+
+      /* The extended option header starts right after Destination header. */
+      opt_offset = IP6_DEST_HLEN;
+      while (opt_offset < hlen)
+      {
+        s32_t opt_dlen = 0;
+
+        opt_hdr = (struct ip6_opt_hdr *)((u8_t *)dest_hdr + opt_offset);
+
+        switch (IP6_OPT_TYPE(opt_hdr))
+        {
+        /* @todo: process IPV6 Destination option data */
+        case IP6_PAD1_OPTION:
+          /* PAD1 option deosn't have length and value field */
+          opt_dlen = -1;
+          break;
+        case IP6_PADN_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        case IP6_ROUTER_ALERT_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        case IP6_JUMBO_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        case IP6_HOME_ADDRESS_OPTION:
+          opt_dlen = IP6_OPT_DLEN(opt_hdr);
+          break;
+        default:
+          /* Check 2 MSB of Destination header type. */
+          switch (IP6_OPT_TYPE_ACTION(opt_hdr))
+          {
+          case 1:
+            /* Discard the packet. */
+            LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid destination option type dropped.\n"));
+            pbuf_free(p);
+            IP6_STATS_INC(ip6.drop);
+            goto ip6_input_cleanup;
+          case 2:
+            /* Send ICMP Parameter Problem */
+            icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr);
+            LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid destination option type dropped.\n"));
+            pbuf_free(p);
+            IP6_STATS_INC(ip6.drop);
+            goto ip6_input_cleanup;
+          case 3:
+            /* Send ICMP Parameter Problem if destination address is not a multicast address */
+            if (!ip6_addr_ismulticast(ip6_current_dest_addr())) {
+              icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr);
+            }
+            LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid destination option type dropped.\n"));
+            pbuf_free(p);
+            IP6_STATS_INC(ip6.drop);
+            goto ip6_input_cleanup;
+          default:
+            /* Skip over this option. */
+            opt_dlen = IP6_OPT_DLEN(opt_hdr);
+            break;
+          }
+          break;
+        }
+
+        /* Adjust the offset to move to the next extended option header */
+        opt_offset = opt_offset + IP6_OPT_HLEN + opt_dlen;
+      }
+
+      pbuf_remove_header(p, hlen);
+      break;
+    }
+    case IP6_NEXTH_ROUTING:
+    {
+      struct ip6_rout_hdr *rout_hdr;
+      LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Routing header\n"));
+
+      rout_hdr = (struct ip6_rout_hdr *)p->payload;
+
+      /* Get next header type. */
+      nexth = &IP6_ROUT_NEXTH(rout_hdr);
+
+      /* Get the header length. */
+      hlen = 8 * (1 + rout_hdr->_hlen);
+
+      if ((p->len < 8) || (hlen > p->len)) {
+        LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+          ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n",
+              hlen, p->len));
+        /* free (drop) packet pbufs */
+        pbuf_free(p);
+        IP6_STATS_INC(ip6.lenerr);
+        IP6_STATS_INC(ip6.drop);
+        goto ip6_input_cleanup;
+      }
+
+      /* Skip over this header. */
+      hlen_tot = (u16_t)(hlen_tot + hlen);
+
+      /* if segment left value is 0 in routing header, ignore the option */
+      if (IP6_ROUT_SEG_LEFT(rout_hdr)) {
+        /* The length field of routing option header must be even */
+        if (rout_hdr->_hlen & 0x1) {
+          /* Discard and send parameter field error */
+          icmp6_param_problem(p, ICMP6_PP_FIELD, &rout_hdr->_hlen);
+          LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid routing type dropped\n"));
+          pbuf_free(p);
+          IP6_STATS_INC(ip6.drop);
+          goto ip6_input_cleanup;
+        }
+
+        switch (IP6_ROUT_TYPE(rout_hdr))
+        {
+        /* TODO: process routing by the type */
+        case IP6_ROUT_TYPE2:
+          break;
+        case IP6_ROUT_RPL:
+          break;
+        default:
+          /* Discard unrecognized routing type and send parameter field error */
+          icmp6_param_problem(p, ICMP6_PP_FIELD, &IP6_ROUT_TYPE(rout_hdr));
+          LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid routing type dropped\n"));
+          pbuf_free(p);
+          IP6_STATS_INC(ip6.drop);
+          goto ip6_input_cleanup;
+        }
+      }
+
+      pbuf_remove_header(p, hlen);
+      break;
+    }
+    case IP6_NEXTH_FRAGMENT:
+    {
+      struct ip6_frag_hdr *frag_hdr;
+      LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Fragment header\n"));
+
+      frag_hdr = (struct ip6_frag_hdr *)p->payload;
+
+      /* Get next header type. */
+      nexth = &IP6_FRAG_NEXTH(frag_hdr);
+
+      /* Fragment Header length. */
+      hlen = 8;
+
+      /* Make sure this header fits in current pbuf. */
+      if (hlen > p->len) {
+        LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+          ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n",
+              hlen, p->len));
+        /* free (drop) packet pbufs */
+        pbuf_free(p);
+        IP6_FRAG_STATS_INC(ip6_frag.lenerr);
+        IP6_FRAG_STATS_INC(ip6_frag.drop);
+        goto ip6_input_cleanup;
+      }
+
+      hlen_tot = (u16_t)(hlen_tot + hlen);
+
+      /* check payload length is multiple of 8 octets when mbit is set */
+      if (IP6_FRAG_MBIT(frag_hdr) && (IP6H_PLEN(ip6hdr) & 0x7)) {
+        /* ipv6 payload length is not multiple of 8 octets */
+        icmp6_param_problem(p, ICMP6_PP_FIELD, LWIP_PACKED_CAST(const void *, &ip6hdr->_plen));
+        LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid payload length dropped\n"));
+        pbuf_free(p);
+        IP6_STATS_INC(ip6.drop);
+        goto ip6_input_cleanup;
+      }
+
+      /* Offset == 0 and more_fragments == 0? */
+      if ((frag_hdr->_fragment_offset &
+           PP_HTONS(IP6_FRAG_OFFSET_MASK | IP6_FRAG_MORE_FLAG)) == 0) {
+        /* This is a 1-fragment packet. Skip this header and continue. */
+        pbuf_remove_header(p, hlen);
+      } else {
+#if LWIP_IPV6_REASS
+        /* reassemble the packet */
+        ip_data.current_ip_header_tot_len = hlen_tot;
+        p = ip6_reass(p);
+        /* packet not fully reassembled yet? */
+        if (p == NULL) {
+          goto ip6_input_cleanup;
+        }
+
+        /* Returned p point to IPv6 header.
+         * Update all our variables and pointers and continue. */
+        ip6hdr = (struct ip6_hdr *)p->payload;
+        nexth = &IP6H_NEXTH(ip6hdr);
+        hlen = hlen_tot = IP6_HLEN;
+        pbuf_remove_header(p, IP6_HLEN);
+
+#else /* LWIP_IPV6_REASS */
+        /* free (drop) packet pbufs */
+        LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Fragment header dropped (with LWIP_IPV6_REASS==0)\n"));
+        pbuf_free(p);
+        IP6_STATS_INC(ip6.opterr);
+        IP6_STATS_INC(ip6.drop);
+        goto ip6_input_cleanup;
+#endif /* LWIP_IPV6_REASS */
+      }
+      break;
+    }
+    default:
+      goto options_done;
+    }
+
+    if (*nexth == IP6_NEXTH_HOPBYHOP) {
+      /* Hop-by-Hop header comes only as a first option */
+      icmp6_param_problem(p, ICMP6_PP_HEADER, nexth);
+      LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Hop-by-Hop options header dropped (only valid as a first option)\n"));
+      pbuf_free(p);
+      IP6_STATS_INC(ip6.drop);
+      goto ip6_input_cleanup;
+    }
+  }
+
+options_done:
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: \n"));
+  ip6_debug_print(p);
+  LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+  ip_data.current_ip_header_tot_len = hlen_tot;
+  
+#if LWIP_RAW
+  /* p points to IPv6 header again for raw_input. */
+  pbuf_add_header_force(p, hlen_tot);
+  /* raw input did not eat the packet? */
+  raw_status = raw_input(p, inp);
+  if (raw_status != RAW_INPUT_EATEN)
+  {
+    /* Point to payload. */
+    pbuf_remove_header(p, hlen_tot);
+#else /* LWIP_RAW */
+  {
+#endif /* LWIP_RAW */
+    switch (*nexth) {
+    case IP6_NEXTH_NONE:
+      pbuf_free(p);
+      break;
+#if LWIP_UDP
+    case IP6_NEXTH_UDP:
+#if LWIP_UDPLITE
+    case IP6_NEXTH_UDPLITE:
+#endif /* LWIP_UDPLITE */
+      udp_input(p, inp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case IP6_NEXTH_TCP:
+      tcp_input(p, inp);
+      break;
+#endif /* LWIP_TCP */
+#if LWIP_ICMP6
+    case IP6_NEXTH_ICMP6:
+      icmp6_input(p, inp);
+      break;
+#endif /* LWIP_ICMP */
+    default:
+#if LWIP_RAW
+        if (raw_status == RAW_INPUT_DELIVERED) {
+          /* @todo: ipv6 mib in-delivers? */
+        } else
+#endif /* LWIP_RAW */
+        {
+#if LWIP_ICMP6
+        /* p points to IPv6 header again for raw_input. */
+        pbuf_add_header_force(p, hlen_tot);
+        /* send ICMP parameter problem unless it was a multicast or ICMPv6 */
+        if ((!ip6_addr_ismulticast(ip6_current_dest_addr())) &&
+            (IP6H_NEXTH(ip6hdr) != IP6_NEXTH_ICMP6)) {
+          icmp6_param_problem(p, ICMP6_PP_HEADER, nexth);
+        }
+#endif /* LWIP_ICMP */
+        LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_input: Unsupported transport protocol %"U16_F"\n", (u16_t)IP6H_NEXTH(ip6hdr)));
+        IP6_STATS_INC(ip6.proterr);
+        IP6_STATS_INC(ip6.drop);
+      }
+      pbuf_free(p);
+      break;
+    }
+  }
+
+ip6_input_cleanup:
+  ip_data.current_netif = NULL;
+  ip_data.current_input_netif = NULL;
+  ip_data.current_ip6_header = NULL;
+  ip_data.current_ip_header_tot_len = 0;
+  ip6_addr_set_zero(ip6_current_src_addr());
+  ip6_addr_set_zero(ip6_current_dest_addr());
+
+  return ERR_OK;
+}
+
+
+/**
+ * Sends an IPv6 packet on a network interface. This function constructs
+ * the IPv6 header. If the source IPv6 address is NULL, the IPv6 "ANY" address is
+ * used as source (usually during network startup). If the source IPv6 address it
+ * IP6_ADDR_ANY, the most appropriate IPv6 address of the outgoing network
+ * interface is filled in as source address. If the destination IPv6 address is
+ * LWIP_IP_HDRINCL, p is assumed to already include an IPv6 header and
+ * p->payload points to it instead of the data.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IPv6 header and p->payload points to that IPv6 header)
+ * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an
+ *         IP address of the netif is selected and used as source address.
+ *         if src == NULL, IP6_ADDR_ANY is used as source) (src is possibly not
+ *         properly zoned)
+ * @param dest the destination IPv6 address to send the packet to (possibly not
+ *             properly zoned)
+ * @param hl the Hop Limit value to be set in the IPv6 header
+ * @param tc the Traffic Class value to be set in the IPv6 header
+ * @param nexth the Next Header to be set in the IPv6 header
+ * @param netif the netif on which to send this packet
+ * @return ERR_OK if the packet was sent OK
+ *         ERR_BUF if p doesn't have enough space for IPv6/LINK headers
+ *         returns errors returned by netif->output_ip6
+ */
+err_t
+ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+             u8_t hl, u8_t tc,
+             u8_t nexth, struct netif *netif)
+{
+  const ip6_addr_t *src_used = src;
+  if (dest != LWIP_IP_HDRINCL) {
+    if (src != NULL && ip6_addr_isany(src)) {
+      src_used = ip_2_ip6(ip6_select_source_address(netif, dest));
+      if ((src_used == NULL) || ip6_addr_isany(src_used)) {
+        /* No appropriate source address was found for this packet. */
+        LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_output: No suitable source address for packet.\n"));
+        IP6_STATS_INC(ip6.rterr);
+        return ERR_RTE;
+      }
+    }
+  }
+  return ip6_output_if_src(p, src_used, dest, hl, tc, nexth, netif);
+}
+
+/**
+ * Same as ip6_output_if() but 'src' address is not replaced by netif address
+ * when it is 'any'.
+ */
+err_t
+ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+             u8_t hl, u8_t tc,
+             u8_t nexth, struct netif *netif)
+{
+  struct ip6_hdr *ip6hdr;
+  ip6_addr_t dest_addr;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+
+  /* Should the IPv6 header be generated or is it already included in p? */
+  if (dest != LWIP_IP_HDRINCL) {
+#if LWIP_IPV6_SCOPES
+    /* If the destination address is scoped but lacks a zone, add a zone now,
+     * based on the outgoing interface. The lower layers (e.g., nd6) absolutely
+     * require addresses to be properly zoned for correctness. In some cases,
+     * earlier attempts will have been made to add a zone to the destination,
+     * but this function is the only one that is called in all (other) cases,
+     * so we must do this here. */
+    if (ip6_addr_lacks_zone(dest, IP6_UNKNOWN)) {
+      ip6_addr_copy(dest_addr, *dest);
+      ip6_addr_assign_zone(&dest_addr, IP6_UNKNOWN, netif);
+      dest = &dest_addr;
+    }
+#endif /* LWIP_IPV6_SCOPES */
+
+    /* generate IPv6 header */
+    if (pbuf_add_header(p, IP6_HLEN)) {
+      LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_output: not enough room for IPv6 header in pbuf\n"));
+      IP6_STATS_INC(ip6.err);
+      return ERR_BUF;
+    }
+
+    ip6hdr = (struct ip6_hdr *)p->payload;
+    LWIP_ASSERT("check that first pbuf can hold struct ip6_hdr",
+               (p->len >= sizeof(struct ip6_hdr)));
+
+    IP6H_HOPLIM_SET(ip6hdr, hl);
+    IP6H_NEXTH_SET(ip6hdr, nexth);
+
+    /* dest cannot be NULL here */
+    ip6_addr_copy_to_packed(ip6hdr->dest, *dest);
+
+    IP6H_VTCFL_SET(ip6hdr, 6, tc, 0);
+    IP6H_PLEN_SET(ip6hdr, (u16_t)(p->tot_len - IP6_HLEN));
+
+    if (src == NULL) {
+      src = IP6_ADDR_ANY6;
+    }
+    /* src cannot be NULL here */
+    ip6_addr_copy_to_packed(ip6hdr->src, *src);
+
+  } else {
+    /* IP header already included in p */
+    ip6hdr = (struct ip6_hdr *)p->payload;
+    ip6_addr_copy_from_packed(dest_addr, ip6hdr->dest);
+    ip6_addr_assign_zone(&dest_addr, IP6_UNKNOWN, netif);
+    dest = &dest_addr;
+  }
+
+  IP6_STATS_INC(ip6.xmit);
+
+  LWIP_DEBUGF(IP6_DEBUG, ("ip6_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], (u16_t)netif->num));
+  ip6_debug_print(p);
+
+#if ENABLE_LOOPBACK
+  {
+    int i;
+#if !LWIP_HAVE_LOOPIF
+    if (ip6_addr_isloopback(dest)) {
+      return netif_loop_output(netif, p);
+    }
+#endif /* !LWIP_HAVE_LOOPIF */
+    for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+      if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) &&
+          ip6_addr_cmp(dest, netif_ip6_addr(netif, i))) {
+        /* Packet to self, enqueue it for loopback */
+        LWIP_DEBUGF(IP6_DEBUG, ("netif_loop_output()\n"));
+        return netif_loop_output(netif, p);
+      }
+    }
+  }
+#if LWIP_MULTICAST_TX_OPTIONS
+  if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) {
+    netif_loop_output(netif, p);
+  }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+#endif /* ENABLE_LOOPBACK */
+#if LWIP_IPV6_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif_mtu6(netif) && (p->tot_len > nd6_get_destination_mtu(dest, netif))) {
+    return ip6_frag(p, netif, dest);
+  }
+#endif /* LWIP_IPV6_FRAG */
+
+  LWIP_DEBUGF(IP6_DEBUG, ("netif->output_ip6()\n"));
+  return netif->output_ip6(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip6_output_if. It finds the outgoing network
+ * interface and calls upon ip6_output_if to do the actual work.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IPv6 header and p->payload points to that IPv6 header)
+ * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an
+ *         IP address of the netif is selected and used as source address.
+ *         if src == NULL, IP6_ADDR_ANY is used as source)
+ * @param dest the destination IPv6 address to send the packet to
+ * @param hl the Hop Limit value to be set in the IPv6 header
+ * @param tc the Traffic Class value to be set in the IPv6 header
+ * @param nexth the Next Header to be set in the IPv6 header
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+          u8_t hl, u8_t tc, u8_t nexth)
+{
+  struct netif *netif;
+  struct ip6_hdr *ip6hdr;
+  ip6_addr_t src_addr, dest_addr;
+
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+
+  if (dest != LWIP_IP_HDRINCL) {
+    netif = ip6_route(src, dest);
+  } else {
+    /* IP header included in p, read addresses. */
+    ip6hdr = (struct ip6_hdr *)p->payload;
+    ip6_addr_copy_from_packed(src_addr, ip6hdr->src);
+    ip6_addr_copy_from_packed(dest_addr, ip6hdr->dest);
+    netif = ip6_route(&src_addr, &dest_addr);
+  }
+
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_output: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n",
+        IP6_ADDR_BLOCK1(dest),
+        IP6_ADDR_BLOCK2(dest),
+        IP6_ADDR_BLOCK3(dest),
+        IP6_ADDR_BLOCK4(dest),
+        IP6_ADDR_BLOCK5(dest),
+        IP6_ADDR_BLOCK6(dest),
+        IP6_ADDR_BLOCK7(dest),
+        IP6_ADDR_BLOCK8(dest)));
+    IP6_STATS_INC(ip6.rterr);
+    return ERR_RTE;
+  }
+
+  return ip6_output_if(p, src, dest, hl, tc, nexth, netif);
+}
+
+
+#if LWIP_NETIF_USE_HINTS
+/** Like ip6_output, but takes and addr_hint pointer that is passed on to netif->addr_hint
+ *  before calling ip6_output_if.
+ *
+ * @param p the packet to send (p->payload points to the data, e.g. next
+            protocol header; if dest == LWIP_IP_HDRINCL, p already includes an
+            IPv6 header and p->payload points to that IPv6 header)
+ * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an
+ *         IP address of the netif is selected and used as source address.
+ *         if src == NULL, IP6_ADDR_ANY is used as source)
+ * @param dest the destination IPv6 address to send the packet to
+ * @param hl the Hop Limit value to be set in the IPv6 header
+ * @param tc the Traffic Class value to be set in the IPv6 header
+ * @param nexth the Next Header to be set in the IPv6 header
+ * @param netif_hint netif output hint pointer set to netif->hint before
+ *        calling ip_output_if()
+ *
+ * @return ERR_RTE if no route is found
+ *         see ip_output_if() for more return values
+ */
+err_t
+ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+          u8_t hl, u8_t tc, u8_t nexth, struct netif_hint *netif_hint)
+{
+  struct netif *netif;
+  struct ip6_hdr *ip6hdr;
+  ip6_addr_t src_addr, dest_addr;
+  err_t err;
+
+  LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
+
+  if (dest != LWIP_IP_HDRINCL) {
+    netif = ip6_route(src, dest);
+  } else {
+    /* IP header included in p, read addresses. */
+    ip6hdr = (struct ip6_hdr *)p->payload;
+    ip6_addr_copy_from_packed(src_addr, ip6hdr->src);
+    ip6_addr_copy_from_packed(dest_addr, ip6hdr->dest);
+    netif = ip6_route(&src_addr, &dest_addr);
+  }
+
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_output: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n",
+        IP6_ADDR_BLOCK1(dest),
+        IP6_ADDR_BLOCK2(dest),
+        IP6_ADDR_BLOCK3(dest),
+        IP6_ADDR_BLOCK4(dest),
+        IP6_ADDR_BLOCK5(dest),
+        IP6_ADDR_BLOCK6(dest),
+        IP6_ADDR_BLOCK7(dest),
+        IP6_ADDR_BLOCK8(dest)));
+    IP6_STATS_INC(ip6.rterr);
+    return ERR_RTE;
+  }
+
+  NETIF_SET_HINTS(netif, netif_hint);
+  err = ip6_output_if(p, src, dest, hl, tc, nexth, netif);
+  NETIF_RESET_HINTS(netif);
+
+  return err;
+}
+#endif /* LWIP_NETIF_USE_HINTS*/
+
+#if LWIP_IPV6_MLD
+/**
+ * Add a hop-by-hop options header with a router alert option and padding.
+ *
+ * Used by MLD when sending a Multicast listener report/done message.
+ *
+ * @param p the packet to which we will prepend the options header
+ * @param nexth the next header protocol number (e.g. IP6_NEXTH_ICMP6)
+ * @param value the value of the router alert option data (e.g. IP6_ROUTER_ALERT_VALUE_MLD)
+ * @return ERR_OK if hop-by-hop header was added, ERR_* otherwise
+ */
+err_t
+ip6_options_add_hbh_ra(struct pbuf *p, u8_t nexth, u8_t value)
+{
+  u8_t *opt_data;
+  u32_t offset = 0;
+  struct ip6_hbh_hdr *hbh_hdr;
+  struct ip6_opt_hdr *opt_hdr;
+
+  /* fixed 4 bytes for router alert option and 2 bytes padding */
+  const u8_t hlen = (sizeof(struct ip6_opt_hdr) * 2) + IP6_ROUTER_ALERT_DLEN;
+  /* Move pointer to make room for hop-by-hop options header. */
+  if (pbuf_add_header(p, sizeof(struct ip6_hbh_hdr) + hlen)) {
+    LWIP_DEBUGF(IP6_DEBUG, ("ip6_options: no space for options header\n"));
+    IP6_STATS_INC(ip6.err);
+    return ERR_BUF;
+  }
+
+  /* Set fields of Hop-by-Hop header */
+  hbh_hdr = (struct ip6_hbh_hdr *)p->payload;
+  IP6_HBH_NEXTH(hbh_hdr) = nexth;
+  hbh_hdr->_hlen = 0;
+  offset = IP6_HBH_HLEN;
+
+  /* Set router alert options to Hop-by-Hop extended option header */
+  opt_hdr = (struct ip6_opt_hdr *)((u8_t *)hbh_hdr + offset);
+  IP6_OPT_TYPE(opt_hdr) = IP6_ROUTER_ALERT_OPTION;
+  IP6_OPT_DLEN(opt_hdr) = IP6_ROUTER_ALERT_DLEN;
+  offset += IP6_OPT_HLEN;
+
+  /* Set router alert option data */
+  opt_data = (u8_t *)hbh_hdr + offset;
+  opt_data[0] = value;
+  opt_data[1] = 0;
+  offset += IP6_OPT_DLEN(opt_hdr);
+
+  /* add 2 bytes padding to make 8 bytes Hop-by-Hop header length */
+  opt_hdr = (struct ip6_opt_hdr *)((u8_t *)hbh_hdr + offset);
+  IP6_OPT_TYPE(opt_hdr) = IP6_PADN_OPTION;
+  IP6_OPT_DLEN(opt_hdr) = 0;
+
+  return ERR_OK;
+}
+#endif /* LWIP_IPV6_MLD */
+
+#if IP6_DEBUG
+/* Print an IPv6 header by using LWIP_DEBUGF
+ * @param p an IPv6 packet, p->payload pointing to the IPv6 header
+ */
+void
+ip6_debug_print(struct pbuf *p)
+{
+  struct ip6_hdr *ip6hdr = (struct ip6_hdr *)p->payload;
+
+  LWIP_DEBUGF(IP6_DEBUG, ("IPv6 header:\n"));
+  LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP6_DEBUG, ("| %2"U16_F" |  %3"U16_F"  |      %7"U32_F"     | (ver, class, flow)\n",
+                    IP6H_V(ip6hdr),
+                    IP6H_TC(ip6hdr),
+                    IP6H_FL(ip6hdr)));
+  LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP6_DEBUG, ("|     %5"U16_F"     |  %3"U16_F"  |  %3"U16_F"  | (plen, nexth, hopl)\n",
+                    IP6H_PLEN(ip6hdr),
+                    IP6H_NEXTH(ip6hdr),
+                    IP6H_HOPLIM(ip6hdr)));
+  LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP6_DEBUG, ("|  %4"X32_F" |  %4"X32_F" |  %4"X32_F" |  %4"X32_F" | (src)\n",
+                    IP6_ADDR_BLOCK1(&(ip6hdr->src)),
+                    IP6_ADDR_BLOCK2(&(ip6hdr->src)),
+                    IP6_ADDR_BLOCK3(&(ip6hdr->src)),
+                    IP6_ADDR_BLOCK4(&(ip6hdr->src))));
+  LWIP_DEBUGF(IP6_DEBUG, ("|  %4"X32_F" |  %4"X32_F" |  %4"X32_F" |  %4"X32_F" |\n",
+                    IP6_ADDR_BLOCK5(&(ip6hdr->src)),
+                    IP6_ADDR_BLOCK6(&(ip6hdr->src)),
+                    IP6_ADDR_BLOCK7(&(ip6hdr->src)),
+                    IP6_ADDR_BLOCK8(&(ip6hdr->src))));
+  LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP6_DEBUG, ("|  %4"X32_F" |  %4"X32_F" |  %4"X32_F" |  %4"X32_F" | (dest)\n",
+                    IP6_ADDR_BLOCK1(&(ip6hdr->dest)),
+                    IP6_ADDR_BLOCK2(&(ip6hdr->dest)),
+                    IP6_ADDR_BLOCK3(&(ip6hdr->dest)),
+                    IP6_ADDR_BLOCK4(&(ip6hdr->dest))));
+  LWIP_DEBUGF(IP6_DEBUG, ("|  %4"X32_F" |  %4"X32_F" |  %4"X32_F" |  %4"X32_F" |\n",
+                    IP6_ADDR_BLOCK5(&(ip6hdr->dest)),
+                    IP6_ADDR_BLOCK6(&(ip6hdr->dest)),
+                    IP6_ADDR_BLOCK7(&(ip6hdr->dest)),
+                    IP6_ADDR_BLOCK8(&(ip6hdr->dest))));
+  LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP6_DEBUG */
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6_addr.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6_addr.c
new file mode 100644
index 000000000..687c02f76
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,343 @@
+/**
+ * @file
+ *
+ * IPv6 addresses.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ * Functions for handling IPv6 addresses.
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/def.h"
+
+#include <string.h>
+
+#if LWIP_IPV4
+#include "lwip/ip4_addr.h" /* for ip6addr_aton to handle IPv4-mapped addresses */
+#endif /* LWIP_IPV4 */
+
+/* used by IP6_ADDR_ANY(6) in ip6_addr.h */
+const ip_addr_t ip6_addr_any = IPADDR6_INIT(0ul, 0ul, 0ul, 0ul);
+
+#define lwip_xchar(i)        ((char)((i) < 10 ? '0' + (i) : 'A' + (i) - 10))
+
+/**
+ * Check whether "cp" is a valid ascii representation
+ * of an IPv6 address and convert to a binary address.
+ * Returns 1 if the address is valid, 0 if not.
+ *
+ * @param cp IPv6 address in ascii representation (e.g. "FF01::1")
+ * @param addr pointer to which to save the ip address in network order
+ * @return 1 if cp could be converted to addr, 0 on failure
+ */
+int
+ip6addr_aton(const char *cp, ip6_addr_t *addr)
+{
+  u32_t addr_index, zero_blocks, current_block_index, current_block_value;
+  const char *s;
+#if LWIP_IPV4
+  int check_ipv4_mapped = 0;
+#endif /* LWIP_IPV4 */
+
+  /* Count the number of colons, to count the number of blocks in a "::" sequence
+     zero_blocks may be 1 even if there are no :: sequences */
+  zero_blocks = 8;
+  for (s = cp; *s != 0; s++) {
+    if (*s == ':') {
+      zero_blocks--;
+#if LWIP_IPV4
+    } else if (*s == '.') {
+      if ((zero_blocks == 5) ||(zero_blocks == 2)) {
+        check_ipv4_mapped = 1;
+        /* last block could be the start of an IPv4 address */
+        zero_blocks--;
+      } else {
+        /* invalid format */
+        return 0;
+      }
+      break;
+#endif /* LWIP_IPV4 */
+    } else if (!lwip_isxdigit(*s)) {
+      break;
+    }
+  }
+
+  /* parse each block */
+  addr_index = 0;
+  current_block_index = 0;
+  current_block_value = 0;
+  for (s = cp; *s != 0; s++) {
+    if (*s == ':') {
+      if (addr) {
+        if (current_block_index & 0x1) {
+          addr->addr[addr_index++] |= current_block_value;
+        }
+        else {
+          addr->addr[addr_index] = current_block_value << 16;
+        }
+      }
+      current_block_index++;
+#if LWIP_IPV4
+      if (check_ipv4_mapped) {
+        if (current_block_index == 6) {
+          ip4_addr_t ip4;
+          int ret = ip4addr_aton(s + 1, &ip4);
+          if (ret) {
+            if (addr) {
+              addr->addr[3] = lwip_htonl(ip4.addr);
+              current_block_index++;
+              goto fix_byte_order_and_return;
+            }
+            return 1;
+          }
+        }
+      }
+#endif /* LWIP_IPV4 */
+      current_block_value = 0;
+      if (current_block_index > 7) {
+        /* address too long! */
+        return 0;
+      }
+      if (s[1] == ':') {
+        if (s[2] == ':') {
+          /* invalid format: three successive colons */
+          return 0;
+        }
+        s++;
+        /* "::" found, set zeros */
+        while (zero_blocks > 0) {
+          zero_blocks--;
+          if (current_block_index & 0x1) {
+            addr_index++;
+          } else {
+            if (addr) {
+              addr->addr[addr_index] = 0;
+            }
+          }
+          current_block_index++;
+          if (current_block_index > 7) {
+            /* address too long! */
+            return 0;
+          }
+        }
+      }
+    } else if (lwip_isxdigit(*s)) {
+      /* add current digit */
+      current_block_value = (current_block_value << 4) +
+          (lwip_isdigit(*s) ? (u32_t)(*s - '0') :
+          (u32_t)(10 + (lwip_islower(*s) ? *s - 'a' : *s - 'A')));
+    } else {
+      /* unexpected digit, space? CRLF? */
+      break;
+    }
+  }
+
+  if (addr) {
+    if (current_block_index & 0x1) {
+      addr->addr[addr_index++] |= current_block_value;
+    }
+    else {
+      addr->addr[addr_index] = current_block_value << 16;
+    }
+#if LWIP_IPV4
+fix_byte_order_and_return:
+#endif
+    /* convert to network byte order. */
+    for (addr_index = 0; addr_index < 4; addr_index++) {
+      addr->addr[addr_index] = lwip_htonl(addr->addr[addr_index]);
+    }
+
+    ip6_addr_clear_zone(addr);
+  }
+
+  if (current_block_index != 7) {
+    return 0;
+  }
+
+  return 1;
+}
+
+/**
+ * Convert numeric IPv6 address into ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ *
+ * @param addr ip6 address in network order to convert
+ * @return pointer to a global static (!) buffer that holds the ASCII
+ *         representation of addr
+ */
+char *
+ip6addr_ntoa(const ip6_addr_t *addr)
+{
+  static char str[40];
+  return ip6addr_ntoa_r(addr, str, 40);
+}
+
+/**
+ * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used.
+ *
+ * @param addr ip6 address in network order to convert
+ * @param buf target buffer where the string is stored
+ * @param buflen length of buf
+ * @return either pointer to buf which now holds the ASCII
+ *         representation of addr or NULL if buf was too small
+ */
+char *
+ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen)
+{
+  u32_t current_block_index, current_block_value, next_block_value;
+  s32_t i;
+  u8_t zero_flag, empty_block_flag;
+
+#if LWIP_IPV4
+  if (ip6_addr_isipv4mappedipv6(addr)) {
+    /* This is an IPv4 mapped address */
+    ip4_addr_t addr4;
+    char *ret;
+#define IP4MAPPED_HEADER "::FFFF:"
+    char *buf_ip4 = buf + sizeof(IP4MAPPED_HEADER) - 1;
+    int buflen_ip4 = buflen - sizeof(IP4MAPPED_HEADER) + 1;
+    if (buflen < (int)sizeof(IP4MAPPED_HEADER)) {
+      return NULL;
+    }
+    memcpy(buf, IP4MAPPED_HEADER, sizeof(IP4MAPPED_HEADER));
+    addr4.addr = addr->addr[3];
+    ret = ip4addr_ntoa_r(&addr4, buf_ip4, buflen_ip4);
+    if (ret != buf_ip4) {
+      return NULL;
+    }
+    return buf;
+  }
+#endif /* LWIP_IPV4 */
+  i = 0;
+  empty_block_flag = 0; /* used to indicate a zero chain for "::' */
+
+  for (current_block_index = 0; current_block_index < 8; current_block_index++) {
+    /* get the current 16-bit block */
+    current_block_value = lwip_htonl(addr->addr[current_block_index >> 1]);
+    if ((current_block_index & 0x1) == 0) {
+      current_block_value = current_block_value >> 16;
+    }
+    current_block_value &= 0xffff;
+
+    /* Check for empty block. */
+    if (current_block_value == 0) {
+      if (current_block_index == 7 && empty_block_flag == 1) {
+        /* special case, we must render a ':' for the last block. */
+        buf[i++] = ':';
+        if (i >= buflen) {
+          return NULL;
+        }
+        break;
+      }
+      if (empty_block_flag == 0) {
+        /* generate empty block "::", but only if more than one contiguous zero block,
+         * according to current formatting suggestions RFC 5952. */
+        next_block_value = lwip_htonl(addr->addr[(current_block_index + 1) >> 1]);
+        if ((current_block_index & 0x1) == 0x01) {
+            next_block_value = next_block_value >> 16;
+        }
+        next_block_value &= 0xffff;
+        if (next_block_value == 0) {
+          empty_block_flag = 1;
+          buf[i++] = ':';
+          if (i >= buflen) {
+            return NULL;
+          }
+          continue; /* move on to next block. */
+        }
+      } else if (empty_block_flag == 1) {
+        /* move on to next block. */
+        continue;
+      }
+    } else if (empty_block_flag == 1) {
+      /* Set this flag value so we don't produce multiple empty blocks. */
+      empty_block_flag = 2;
+    }
+
+    if (current_block_index > 0) {
+      buf[i++] = ':';
+      if (i >= buflen) {
+        return NULL;
+      }
+    }
+
+    if ((current_block_value & 0xf000) == 0) {
+      zero_flag = 1;
+    } else {
+      buf[i++] = lwip_xchar(((current_block_value & 0xf000) >> 12));
+      zero_flag = 0;
+      if (i >= buflen) {
+        return NULL;
+      }
+    }
+
+    if (((current_block_value & 0xf00) == 0) && (zero_flag)) {
+      /* do nothing */
+    } else {
+      buf[i++] = lwip_xchar(((current_block_value & 0xf00) >> 8));
+      zero_flag = 0;
+      if (i >= buflen) {
+        return NULL;
+      }
+    }
+
+    if (((current_block_value & 0xf0) == 0) && (zero_flag)) {
+      /* do nothing */
+    }
+    else {
+      buf[i++] = lwip_xchar(((current_block_value & 0xf0) >> 4));
+      zero_flag = 0;
+      if (i >= buflen) {
+        return NULL;
+      }
+    }
+
+    buf[i++] = lwip_xchar((current_block_value & 0xf));
+    if (i >= buflen) {
+      return NULL;
+    }
+  }
+
+  buf[i] = 0;
+
+  return buf;
+}
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6_frag.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6_frag.c
new file mode 100644
index 000000000..d6c5d223c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/ip6_frag.c
@@ -0,0 +1,862 @@
+/**
+ * @file
+ *
+ * IPv6 fragmentation and reassembly.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+#include "lwip/ip6_frag.h"
+#include "lwip/ip6.h"
+#include "lwip/icmp6.h"
+#include "lwip/nd6.h"
+#include "lwip/ip.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/memp.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS  /* don't build if not configured for use in lwipopts.h */
+
+
+/** Setting this to 0, you can turn off checking the fragments for overlapping
+ * regions. The code gets a little smaller. Only use this if you know that
+ * overlapping won't occur on your network! */
+#ifndef IP_REASS_CHECK_OVERLAP
+#define IP_REASS_CHECK_OVERLAP 1
+#endif /* IP_REASS_CHECK_OVERLAP */
+
+/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is
+ * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller.
+ * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA
+ * is set to 1, so one datagram can be reassembled at a time, only. */
+#ifndef IP_REASS_FREE_OLDEST
+#define IP_REASS_FREE_OLDEST 1
+#endif /* IP_REASS_FREE_OLDEST */
+
+#if IPV6_FRAG_COPYHEADER
+/* The number of bytes we need to "borrow" from (i.e., overwrite in) the header
+ * that precedes the fragment header for reassembly pruposes. */
+#define IPV6_FRAG_REQROOM ((s16_t)(sizeof(struct ip6_reass_helper) - IP6_FRAG_HLEN))
+#endif
+
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+/** This is a helper struct which holds the starting
+ * offset and the ending offset of this fragment to
+ * easily chain the fragments.
+ * It has the same packing requirements as the IPv6 header, since it replaces
+ * the Fragment Header in memory in incoming fragments to keep
+ * track of the various fragments.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_reass_helper {
+  PACK_STRUCT_FIELD(struct pbuf *next_pbuf);
+  PACK_STRUCT_FIELD(u16_t start);
+  PACK_STRUCT_FIELD(u16_t end);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* static variables */
+static struct ip6_reassdata *reassdatagrams;
+static u16_t ip6_reass_pbufcount;
+
+/* Forward declarations. */
+static void ip6_reass_free_complete_datagram(struct ip6_reassdata *ipr);
+#if IP_REASS_FREE_OLDEST
+static void ip6_reass_remove_oldest_datagram(struct ip6_reassdata *ipr, int pbufs_needed);
+#endif /* IP_REASS_FREE_OLDEST */
+
+void
+ip6_reass_tmr(void)
+{
+  struct ip6_reassdata *r, *tmp;
+
+#if !IPV6_FRAG_COPYHEADER
+  LWIP_ASSERT("sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN, set IPV6_FRAG_COPYHEADER to 1",
+    sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN);
+#endif /* !IPV6_FRAG_COPYHEADER */
+
+  r = reassdatagrams;
+  while (r != NULL) {
+    /* Decrement the timer. Once it reaches 0,
+     * clean up the incomplete fragment assembly */
+    if (r->timer > 0) {
+      r->timer--;
+      r = r->next;
+    } else {
+      /* reassembly timed out */
+      tmp = r;
+      /* get the next pointer before freeing */
+      r = r->next;
+      /* free the helper struct and all enqueued pbufs */
+      ip6_reass_free_complete_datagram(tmp);
+     }
+   }
+}
+
+/**
+ * Free a datagram (struct ip6_reassdata) and all its pbufs.
+ * Updates the total count of enqueued pbufs (ip6_reass_pbufcount),
+ * sends an ICMP time exceeded packet.
+ *
+ * @param ipr datagram to free
+ */
+static void
+ip6_reass_free_complete_datagram(struct ip6_reassdata *ipr)
+{
+  struct ip6_reassdata *prev;
+  u16_t pbufs_freed = 0;
+  u16_t clen;
+  struct pbuf *p;
+  struct ip6_reass_helper *iprh;
+
+#if LWIP_ICMP6
+  iprh = (struct ip6_reass_helper *)ipr->p->payload;
+  if (iprh->start == 0) {
+    /* The first fragment was received, send ICMP time exceeded. */
+    /* First, de-queue the first pbuf from r->p. */
+    p = ipr->p;
+    ipr->p = iprh->next_pbuf;
+    /* Restore the part that we've overwritten with our helper structure, or we
+     * might send garbage (and disclose a pointer) in the ICMPv6 reply. */
+    MEMCPY(p->payload, ipr->orig_hdr, sizeof(iprh));
+    /* Then, move back to the original ipv6 header (we are now pointing to Fragment header).
+       This cannot fail since we already checked when receiving this fragment. */
+    if (pbuf_header_force(p, (s16_t)((u8_t*)p->payload - (u8_t*)ipr->iphdr))) {
+      LWIP_ASSERT("ip6_reass_free: moving p->payload to ip6 header failed\n", 0);
+    }
+    else {
+      /* Reconstruct the zoned source and destination addresses, so that we do
+       * not end up sending the ICMP response over the wrong link. */
+      ip6_addr_t src_addr, dest_addr;
+      ip6_addr_copy_from_packed(src_addr, IPV6_FRAG_SRC(ipr));
+      ip6_addr_set_zone(&src_addr, ipr->src_zone);
+      ip6_addr_copy_from_packed(dest_addr, IPV6_FRAG_DEST(ipr));
+      ip6_addr_set_zone(&dest_addr, ipr->dest_zone);
+      /* Send the actual ICMP response. */
+      icmp6_time_exceeded_with_addrs(p, ICMP6_TE_FRAG, &src_addr, &dest_addr);
+    }
+    clen = pbuf_clen(p);
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+    pbufs_freed = (u16_t)(pbufs_freed + clen);
+    pbuf_free(p);
+  }
+#endif /* LWIP_ICMP6 */
+
+  /* First, free all received pbufs.  The individual pbufs need to be released
+     separately as they have not yet been chained */
+  p = ipr->p;
+  while (p != NULL) {
+    struct pbuf *pcur;
+    iprh = (struct ip6_reass_helper *)p->payload;
+    pcur = p;
+    /* get the next pointer before freeing */
+    p = iprh->next_pbuf;
+    clen = pbuf_clen(pcur);
+    LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
+    pbufs_freed = (u16_t)(pbufs_freed + clen);
+    pbuf_free(pcur);
+  }
+
+  /* Then, unchain the struct ip6_reassdata from the list and free it. */
+  if (ipr == reassdatagrams) {
+    reassdatagrams = ipr->next;
+  } else {
+    prev = reassdatagrams;
+    while (prev != NULL) {
+      if (prev->next == ipr) {
+        break;
+      }
+      prev = prev->next;
+    }
+    if (prev != NULL) {
+      prev->next = ipr->next;
+    }
+  }
+  memp_free(MEMP_IP6_REASSDATA, ipr);
+
+  /* Finally, update number of pbufs in reassembly queue */
+  LWIP_ASSERT("ip_reass_pbufcount >= clen", ip6_reass_pbufcount >= pbufs_freed);
+  ip6_reass_pbufcount = (u16_t)(ip6_reass_pbufcount - pbufs_freed);
+}
+
+#if IP_REASS_FREE_OLDEST
+/**
+ * Free the oldest datagram to make room for enqueueing new fragments.
+ * The datagram ipr is not freed!
+ *
+ * @param ipr ip6_reassdata for the current fragment
+ * @param pbufs_needed number of pbufs needed to enqueue
+ *        (used for freeing other datagrams if not enough space)
+ */
+static void
+ip6_reass_remove_oldest_datagram(struct ip6_reassdata *ipr, int pbufs_needed)
+{
+  struct ip6_reassdata *r, *oldest;
+
+  /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
+   * but don't free the current datagram! */
+  do {
+    r = oldest = reassdatagrams;
+    while (r != NULL) {
+      if (r != ipr) {
+        if (r->timer <= oldest->timer) {
+          /* older than the previous oldest */
+          oldest = r;
+        }
+      }
+      r = r->next;
+    }
+    if (oldest == ipr) {
+      /* nothing to free, ipr is the only element on the list */
+      return;
+    }
+    if (oldest != NULL) {
+      ip6_reass_free_complete_datagram(oldest);
+    }
+  } while (((ip6_reass_pbufcount + pbufs_needed) > IP_REASS_MAX_PBUFS) && (reassdatagrams != NULL));
+}
+#endif /* IP_REASS_FREE_OLDEST */
+
+/**
+ * Reassembles incoming IPv6 fragments into an IPv6 datagram.
+ *
+ * @param p points to the IPv6 Fragment Header
+ * @return NULL if reassembly is incomplete, pbuf pointing to
+ *         IPv6 Header if reassembly is complete
+ */
+struct pbuf *
+ip6_reass(struct pbuf *p)
+{
+  struct ip6_reassdata *ipr, *ipr_prev;
+  struct ip6_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL;
+  struct ip6_frag_hdr *frag_hdr;
+  u16_t offset, len, start, end;
+  ptrdiff_t hdrdiff;
+  u16_t clen;
+  u8_t valid = 1;
+  struct pbuf *q, *next_pbuf;
+
+  IP6_FRAG_STATS_INC(ip6_frag.recv);
+
+  /* ip6_frag_hdr must be in the first pbuf, not chained. Checked by caller. */
+  LWIP_ASSERT("IPv6 fragment header does not fit in first pbuf",
+    p->len >= sizeof(struct ip6_frag_hdr));
+
+  frag_hdr = (struct ip6_frag_hdr *) p->payload;
+
+  clen = pbuf_clen(p);
+
+  offset = lwip_ntohs(frag_hdr->_fragment_offset);
+
+  /* Calculate fragment length from IPv6 payload length.
+   * Adjust for headers before Fragment Header.
+   * And finally adjust by Fragment Header length. */
+  len = lwip_ntohs(ip6_current_header()->_plen);
+  hdrdiff = (u8_t*)p->payload - (const u8_t*)ip6_current_header();
+  LWIP_ASSERT("not a valid pbuf (ip6_input check missing?)", hdrdiff <= 0xFFFF);
+  LWIP_ASSERT("not a valid pbuf (ip6_input check missing?)", hdrdiff >= IP6_HLEN);
+  hdrdiff -= IP6_HLEN;
+  hdrdiff += IP6_FRAG_HLEN;
+  if (hdrdiff > len) {
+    IP6_FRAG_STATS_INC(ip6_frag.proterr);
+    goto nullreturn;
+  }
+  len = (u16_t)(len - hdrdiff);
+  start = (offset & IP6_FRAG_OFFSET_MASK);
+  if (start > (0xFFFF - len)) {
+    /* u16_t overflow, cannot handle this */
+    IP6_FRAG_STATS_INC(ip6_frag.proterr);
+    goto nullreturn;
+  }
+
+  /* Look for the datagram the fragment belongs to in the current datagram queue,
+   * remembering the previous in the queue for later dequeueing. */
+  for (ipr = reassdatagrams, ipr_prev = NULL; ipr != NULL; ipr = ipr->next) {
+    /* Check if the incoming fragment matches the one currently present
+       in the reassembly buffer. If so, we proceed with copying the
+       fragment into the buffer. */
+    if ((frag_hdr->_identification == ipr->identification) &&
+        ip6_addr_cmp_packed(ip6_current_src_addr(), &(IPV6_FRAG_SRC(ipr)), ipr->src_zone) &&
+        ip6_addr_cmp_packed(ip6_current_dest_addr(), &(IPV6_FRAG_DEST(ipr)), ipr->dest_zone)) {
+      IP6_FRAG_STATS_INC(ip6_frag.cachehit);
+      break;
+    }
+    ipr_prev = ipr;
+  }
+
+  if (ipr == NULL) {
+  /* Enqueue a new datagram into the datagram queue */
+    ipr = (struct ip6_reassdata *)memp_malloc(MEMP_IP6_REASSDATA);
+    if (ipr == NULL) {
+#if IP_REASS_FREE_OLDEST
+      /* Make room and try again. */
+      ip6_reass_remove_oldest_datagram(ipr, clen);
+      ipr = (struct ip6_reassdata *)memp_malloc(MEMP_IP6_REASSDATA);
+      if (ipr != NULL) {
+        /* re-search ipr_prev since it might have been removed */
+        for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
+          if (ipr_prev->next == ipr) {
+            break;
+          }
+        }
+      } else
+#endif /* IP_REASS_FREE_OLDEST */
+      {
+        IP6_FRAG_STATS_INC(ip6_frag.memerr);
+        goto nullreturn;
+      }
+    }
+
+    memset(ipr, 0, sizeof(struct ip6_reassdata));
+    ipr->timer = IPV6_REASS_MAXAGE;
+
+    /* enqueue the new structure to the front of the list */
+    ipr->next = reassdatagrams;
+    reassdatagrams = ipr;
+
+    /* Use the current IPv6 header for src/dest address reference.
+     * Eventually, we will replace it when we get the first fragment
+     * (it might be this one, in any case, it is done later). */
+    /* need to use the none-const pointer here: */
+    ipr->iphdr = ip_data.current_ip6_header;
+#if IPV6_FRAG_COPYHEADER
+    MEMCPY(&ipr->src, &ip6_current_header()->src, sizeof(ipr->src));
+    MEMCPY(&ipr->dest, &ip6_current_header()->dest, sizeof(ipr->dest));
+#endif /* IPV6_FRAG_COPYHEADER */
+#if LWIP_IPV6_SCOPES
+    /* Also store the address zone information.
+     * @todo It is possible that due to netif destruction and recreation, the
+     * stored zones end up resolving to a different interface. In that case, we
+     * risk sending a "time exceeded" ICMP response over the wrong link.
+     * Ideally, netif destruction would clean up matching pending reassembly
+     * structures, but custom zone mappings would make that non-trivial. */
+    ipr->src_zone = ip6_addr_zone(ip6_current_src_addr());
+    ipr->dest_zone = ip6_addr_zone(ip6_current_dest_addr());
+#endif /* LWIP_IPV6_SCOPES */
+    /* copy the fragmented packet id. */
+    ipr->identification = frag_hdr->_identification;
+
+    /* copy the nexth field */
+    ipr->nexth = frag_hdr->_nexth;
+  }
+
+  /* Check if we are allowed to enqueue more datagrams. */
+  if ((ip6_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
+#if IP_REASS_FREE_OLDEST
+    ip6_reass_remove_oldest_datagram(ipr, clen);
+    if ((ip6_reass_pbufcount + clen) <= IP_REASS_MAX_PBUFS) {
+      /* re-search ipr_prev since it might have been removed */
+      for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
+        if (ipr_prev->next == ipr) {
+          break;
+        }
+      }
+    } else
+#endif /* IP_REASS_FREE_OLDEST */
+    {
+      /* @todo: send ICMPv6 time exceeded here? */
+      /* drop this pbuf */
+      IP6_FRAG_STATS_INC(ip6_frag.memerr);
+      goto nullreturn;
+    }
+  }
+
+  /* Overwrite Fragment Header with our own helper struct. */
+#if IPV6_FRAG_COPYHEADER
+  if (IPV6_FRAG_REQROOM > 0) {
+    /* Make room for struct ip6_reass_helper (only required if sizeof(void*) > 4).
+       This cannot fail since we already checked when receiving this fragment. */
+    u8_t hdrerr = pbuf_header_force(p, IPV6_FRAG_REQROOM);
+    LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */
+    LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0);
+  }
+#else /* IPV6_FRAG_COPYHEADER */
+  LWIP_ASSERT("sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN, set IPV6_FRAG_COPYHEADER to 1",
+    sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN);
+#endif /* IPV6_FRAG_COPYHEADER */
+
+  /* Prepare the pointer to the helper structure, and its initial values.
+   * Do not yet write to the structure itself, as we still have to make a
+   * backup of the original data, and we should not do that until we know for
+   * sure that we are going to add this packet to the list. */
+  iprh = (struct ip6_reass_helper *)p->payload;
+  next_pbuf = NULL;
+  end = (u16_t)(start + len);
+
+  /* find the right place to insert this pbuf */
+  /* Iterate through until we either get to the end of the list (append),
+   * or we find on with a larger offset (insert). */
+  for (q = ipr->p; q != NULL;) {
+    iprh_tmp = (struct ip6_reass_helper*)q->payload;
+    if (start < iprh_tmp->start) {
+#if IP_REASS_CHECK_OVERLAP
+      if (end > iprh_tmp->start) {
+        /* fragment overlaps with following, throw away */
+        IP6_FRAG_STATS_INC(ip6_frag.proterr);
+        goto nullreturn;
+      }
+      if (iprh_prev != NULL) {
+        if (start < iprh_prev->end) {
+          /* fragment overlaps with previous, throw away */
+          IP6_FRAG_STATS_INC(ip6_frag.proterr);
+          goto nullreturn;
+        }
+      }
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* the new pbuf should be inserted before this */
+      next_pbuf = q;
+      if (iprh_prev != NULL) {
+        /* not the fragment with the lowest offset */
+        iprh_prev->next_pbuf = p;
+      } else {
+        /* fragment with the lowest offset */
+        ipr->p = p;
+      }
+      break;
+    } else if (start == iprh_tmp->start) {
+      /* received the same datagram twice: no need to keep the datagram */
+      goto nullreturn;
+#if IP_REASS_CHECK_OVERLAP
+    } else if (start < iprh_tmp->end) {
+      /* overlap: no need to keep the new datagram */
+      IP6_FRAG_STATS_INC(ip6_frag.proterr);
+      goto nullreturn;
+#endif /* IP_REASS_CHECK_OVERLAP */
+    } else {
+      /* Check if the fragments received so far have no gaps. */
+      if (iprh_prev != NULL) {
+        if (iprh_prev->end != iprh_tmp->start) {
+          /* There is a fragment missing between the current
+           * and the previous fragment */
+          valid = 0;
+        }
+      }
+    }
+    q = iprh_tmp->next_pbuf;
+    iprh_prev = iprh_tmp;
+  }
+
+  /* If q is NULL, then we made it to the end of the list. Determine what to do now */
+  if (q == NULL) {
+    if (iprh_prev != NULL) {
+      /* this is (for now), the fragment with the highest offset:
+       * chain it to the last fragment */
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= start);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      iprh_prev->next_pbuf = p;
+      if (iprh_prev->end != start) {
+        valid = 0;
+      }
+    } else {
+#if IP_REASS_CHECK_OVERLAP
+      LWIP_ASSERT("no previous fragment, this must be the first fragment!",
+        ipr->p == NULL);
+#endif /* IP_REASS_CHECK_OVERLAP */
+      /* this is the first fragment we ever received for this ip datagram */
+      ipr->p = p;
+    }
+  }
+
+  /* Track the current number of pbufs current 'in-flight', in order to limit
+  the number of fragments that may be enqueued at any one time */
+  ip6_reass_pbufcount = (u16_t)(ip6_reass_pbufcount + clen);
+
+  /* Remember IPv6 header if this is the first fragment. */
+  if (start == 0) {
+    /* need to use the none-const pointer here: */
+    ipr->iphdr = ip_data.current_ip6_header;
+    /* Make a backup of the part of the packet data that we are about to
+     * overwrite, so that we can restore the original later. */
+    MEMCPY(ipr->orig_hdr, p->payload, sizeof(*iprh));
+    /* For IPV6_FRAG_COPYHEADER there is no need to copy src/dst again, as they
+     * will be the same as they were. With LWIP_IPV6_SCOPES, the same applies
+     * to the source/destination zones. */
+  }
+  /* Only after the backup do we get to fill in the actual helper structure. */
+  iprh->next_pbuf = next_pbuf;
+  iprh->start = start;
+  iprh->end = end;
+
+  /* If this is the last fragment, calculate total packet length. */
+  if ((offset & IP6_FRAG_MORE_FLAG) == 0) {
+    ipr->datagram_len = iprh->end;
+  }
+
+  /* Additional validity tests: we have received first and last fragment. */
+  iprh_tmp = (struct ip6_reass_helper*)ipr->p->payload;
+  if (iprh_tmp->start != 0) {
+    valid = 0;
+  }
+  if (ipr->datagram_len == 0) {
+    valid = 0;
+  }
+
+  /* Final validity test: no gaps between current and last fragment. */
+  iprh_prev = iprh;
+  q = iprh->next_pbuf;
+  while ((q != NULL) && valid) {
+    iprh = (struct ip6_reass_helper*)q->payload;
+    if (iprh_prev->end != iprh->start) {
+      valid = 0;
+      break;
+    }
+    iprh_prev = iprh;
+    q = iprh->next_pbuf;
+  }
+
+  if (valid) {
+    /* All fragments have been received */
+    struct ip6_hdr* iphdr_ptr;
+
+    /* chain together the pbufs contained within the ip6_reassdata list. */
+    iprh = (struct ip6_reass_helper*) ipr->p->payload;
+    while (iprh != NULL) {
+      next_pbuf = iprh->next_pbuf;
+      if (next_pbuf != NULL) {
+        /* Save next helper struct (will be hidden in next step). */
+        iprh_tmp = (struct ip6_reass_helper*)next_pbuf->payload;
+
+        /* hide the fragment header for every succeeding fragment */
+        pbuf_remove_header(next_pbuf, IP6_FRAG_HLEN);
+#if IPV6_FRAG_COPYHEADER
+        if (IPV6_FRAG_REQROOM > 0) {
+          /* hide the extra bytes borrowed from ip6_hdr for struct ip6_reass_helper */
+          u8_t hdrerr = pbuf_remove_header(next_pbuf, IPV6_FRAG_REQROOM);
+          LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */
+          LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0);
+        }
+#endif
+        pbuf_cat(ipr->p, next_pbuf);
+      }
+      else {
+        iprh_tmp = NULL;
+      }
+
+      iprh = iprh_tmp;
+    }
+
+    /* Get the first pbuf. */
+    p = ipr->p;
+
+#if IPV6_FRAG_COPYHEADER
+    if (IPV6_FRAG_REQROOM > 0) {
+      u8_t hdrerr;
+      /* Restore (only) the bytes that we overwrote beyond the fragment header.
+       * Those bytes may belong to either the IPv6 header or an extension
+       * header placed before the fragment header. */
+      MEMCPY(p->payload, ipr->orig_hdr, IPV6_FRAG_REQROOM);
+      /* get back room for struct ip6_reass_helper (only required if sizeof(void*) > 4) */
+      hdrerr = pbuf_remove_header(p, IPV6_FRAG_REQROOM);
+      LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */
+      LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0);
+    }
+#endif
+
+    /* We need to get rid of the fragment header itself, which is somewhere in
+     * the middle of the packet (but still in the first pbuf of the chain).
+     * Getting rid of the header is required by RFC 2460 Sec. 4.5 and necessary
+     * in order to be able to reassemble packets that are close to full size
+     * (i.e., around 65535 bytes). We simply move up all the headers before the
+     * fragment header, including the IPv6 header, and adjust the payload start
+     * accordingly. This works because all these headers are in the first pbuf
+     * of the chain, and because the caller adjusts all its pointers on
+     * successful reassembly. */
+    MEMMOVE((u8_t*)ipr->iphdr + sizeof(struct ip6_frag_hdr), ipr->iphdr,
+      (size_t)((u8_t*)p->payload - (u8_t*)ipr->iphdr));
+
+    /* This is where the IPv6 header is now. */
+    iphdr_ptr = (struct ip6_hdr*)((u8_t*)ipr->iphdr +
+      sizeof(struct ip6_frag_hdr));
+
+    /* Adjust datagram length by adding header lengths. */
+    ipr->datagram_len = (u16_t)(ipr->datagram_len + ((u8_t*)p->payload - (u8_t*)iphdr_ptr)
+                         - IP6_HLEN);
+
+    /* Set payload length in ip header. */
+    iphdr_ptr->_plen = lwip_htons(ipr->datagram_len);
+
+    /* With the fragment header gone, we now need to adjust the next-header
+     * field of whatever header was originally before it. Since the packet made
+     * it through the original header processing routines at least up to the
+     * fragment header, we do not need any further sanity checks here. */
+    if (IP6H_NEXTH(iphdr_ptr) == IP6_NEXTH_FRAGMENT) {
+      iphdr_ptr->_nexth = ipr->nexth;
+    } else {
+      u8_t *ptr = (u8_t *)iphdr_ptr + IP6_HLEN;
+      while (*ptr != IP6_NEXTH_FRAGMENT) {
+        ptr += 8 * (1 + ptr[1]);
+      }
+      *ptr = ipr->nexth;
+    }
+
+    /* release the resources allocated for the fragment queue entry */
+    if (reassdatagrams == ipr) {
+      /* it was the first in the list */
+      reassdatagrams = ipr->next;
+    } else {
+      /* it wasn't the first, so it must have a valid 'prev' */
+      LWIP_ASSERT("sanity check linked list", ipr_prev != NULL);
+      ipr_prev->next = ipr->next;
+    }
+    memp_free(MEMP_IP6_REASSDATA, ipr);
+
+    /* adjust the number of pbufs currently queued for reassembly. */
+    clen = pbuf_clen(p);
+    LWIP_ASSERT("ip6_reass_pbufcount >= clen", ip6_reass_pbufcount >= clen);
+    ip6_reass_pbufcount = (u16_t)(ip6_reass_pbufcount - clen);
+
+    /* Move pbuf back to IPv6 header. This should never fail. */
+    if (pbuf_header_force(p, (s16_t)((u8_t*)p->payload - (u8_t*)iphdr_ptr))) {
+      LWIP_ASSERT("ip6_reass: moving p->payload to ip6 header failed\n", 0);
+      pbuf_free(p);
+      return NULL;
+    }
+
+    /* Return the pbuf chain */
+    return p;
+  }
+  /* the datagram is not (yet?) reassembled completely */
+  return NULL;
+
+nullreturn:
+  IP6_FRAG_STATS_INC(ip6_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_FRAG
+
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+/** Allocate a new struct pbuf_custom_ref */
+static struct pbuf_custom_ref*
+ip6_frag_alloc_pbuf_custom_ref(void)
+{
+  return (struct pbuf_custom_ref*)memp_malloc(MEMP_FRAG_PBUF);
+}
+
+/** Free a struct pbuf_custom_ref */
+static void
+ip6_frag_free_pbuf_custom_ref(struct pbuf_custom_ref* p)
+{
+  LWIP_ASSERT("p != NULL", p != NULL);
+  memp_free(MEMP_FRAG_PBUF, p);
+}
+
+/** Free-callback function to free a 'struct pbuf_custom_ref', called by
+ * pbuf_free. */
+static void
+ip6_frag_free_pbuf_custom(struct pbuf *p)
+{
+  struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref*)p;
+  LWIP_ASSERT("pcr != NULL", pcr != NULL);
+  LWIP_ASSERT("pcr == p", (void*)pcr == (void*)p);
+  if (pcr->original != NULL) {
+    pbuf_free(pcr->original);
+  }
+  ip6_frag_free_pbuf_custom_ref(pcr);
+}
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+
+/**
+ * Fragment an IPv6 datagram if too large for the netif or path MTU.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by pointing PBUF_REFs into p
+ *
+ * @param p ipv6 packet to send
+ * @param netif the netif on which to send
+ * @param dest destination ipv6 address to which to send
+ *
+ * @return ERR_OK if sent successfully, err_t otherwise
+ */
+err_t
+ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest)
+{
+  struct ip6_hdr *original_ip6hdr;
+  struct ip6_hdr *ip6hdr;
+  struct ip6_frag_hdr *frag_hdr;
+  struct pbuf *rambuf;
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+  struct pbuf *newpbuf;
+  u16_t newpbuflen = 0;
+  u16_t left_to_copy;
+#endif
+  static u32_t identification;
+  u16_t left, cop;
+  const u16_t mtu = nd6_get_destination_mtu(dest, netif);
+  const u16_t nfb = (u16_t)((mtu - (IP6_HLEN + IP6_FRAG_HLEN)) & IP6_FRAG_OFFSET_MASK);
+  u16_t fragment_offset = 0;
+  u16_t last;
+  u16_t poff = IP6_HLEN;
+
+  identification++;
+
+  original_ip6hdr = (struct ip6_hdr *)p->payload;
+
+  /* @todo we assume there are no options in the unfragmentable part (IPv6 header). */
+  LWIP_ASSERT("p->tot_len >= IP6_HLEN", p->tot_len >= IP6_HLEN);
+  left = (u16_t)(p->tot_len - IP6_HLEN);
+
+  while (left) {
+    last = (left <= nfb);
+
+    /* Fill this fragment */
+    cop = last ? left : nfb;
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+    rambuf = pbuf_alloc(PBUF_IP, cop + IP6_FRAG_HLEN, PBUF_RAM);
+    if (rambuf == NULL) {
+      IP6_FRAG_STATS_INC(ip6_frag.memerr);
+      return ERR_MEM;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+      (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL));
+    poff += pbuf_copy_partial(p, (u8_t*)rambuf->payload + IP6_FRAG_HLEN, cop, poff);
+    /* make room for the IP header */
+    if (pbuf_add_header(rambuf, IP6_HLEN)) {
+      pbuf_free(rambuf);
+      IP6_FRAG_STATS_INC(ip6_frag.memerr);
+      return ERR_MEM;
+    }
+    /* fill in the IP header */
+    SMEMCPY(rambuf->payload, original_ip6hdr, IP6_HLEN);
+    ip6hdr = (struct ip6_hdr *)rambuf->payload;
+    frag_hdr = (struct ip6_frag_hdr *)((u8_t*)rambuf->payload + IP6_HLEN);
+#else
+    /* When not using a static buffer, create a chain of pbufs.
+     * The first will be a PBUF_RAM holding the link, IPv6, and Fragment header.
+     * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
+     * but limited to the size of an mtu.
+     */
+    rambuf = pbuf_alloc(PBUF_LINK, IP6_HLEN + IP6_FRAG_HLEN, PBUF_RAM);
+    if (rambuf == NULL) {
+      IP6_FRAG_STATS_INC(ip6_frag.memerr);
+      return ERR_MEM;
+    }
+    LWIP_ASSERT("this needs a pbuf in one piece!",
+                (p->len >= (IP6_HLEN)));
+    SMEMCPY(rambuf->payload, original_ip6hdr, IP6_HLEN);
+    ip6hdr = (struct ip6_hdr *)rambuf->payload;
+    frag_hdr = (struct ip6_frag_hdr *)((u8_t*)rambuf->payload + IP6_HLEN);
+
+    /* Can just adjust p directly for needed offset. */
+    p->payload = (u8_t *)p->payload + poff;
+    p->len = (u16_t)(p->len - poff);
+    p->tot_len = (u16_t)(p->tot_len - poff);
+
+    left_to_copy = cop;
+    while (left_to_copy) {
+      struct pbuf_custom_ref *pcr;
+      newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len;
+      /* Is this pbuf already empty? */
+      if (!newpbuflen) {
+        p = p->next;
+        continue;
+      }
+      pcr = ip6_frag_alloc_pbuf_custom_ref();
+      if (pcr == NULL) {
+        pbuf_free(rambuf);
+        IP6_FRAG_STATS_INC(ip6_frag.memerr);
+        return ERR_MEM;
+      }
+      /* Mirror this pbuf, although we might not need all of it. */
+      newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, p->payload, newpbuflen);
+      if (newpbuf == NULL) {
+        ip6_frag_free_pbuf_custom_ref(pcr);
+        pbuf_free(rambuf);
+        IP6_FRAG_STATS_INC(ip6_frag.memerr);
+        return ERR_MEM;
+      }
+      pbuf_ref(p);
+      pcr->original = p;
+      pcr->pc.custom_free_function = ip6_frag_free_pbuf_custom;
+
+      /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
+       * so that it is removed when pbuf_dechain is later called on rambuf.
+       */
+      pbuf_cat(rambuf, newpbuf);
+      left_to_copy = (u16_t)(left_to_copy - newpbuflen);
+      if (left_to_copy) {
+        p = p->next;
+      }
+    }
+    poff = newpbuflen;
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+    /* Set headers */
+    frag_hdr->_nexth = original_ip6hdr->_nexth;
+    frag_hdr->reserved = 0;
+    frag_hdr->_fragment_offset = lwip_htons((u16_t)((fragment_offset & IP6_FRAG_OFFSET_MASK) | (last ? 0 : IP6_FRAG_MORE_FLAG)));
+    frag_hdr->_identification = lwip_htonl(identification);
+
+    IP6H_NEXTH_SET(ip6hdr, IP6_NEXTH_FRAGMENT);
+    IP6H_PLEN_SET(ip6hdr, (u16_t)(cop + IP6_FRAG_HLEN));
+
+    /* No need for separate header pbuf - we allowed room for it in rambuf
+     * when allocated.
+     */
+    IP6_FRAG_STATS_INC(ip6_frag.xmit);
+    netif->output_ip6(netif, rambuf, dest);
+
+    /* Unfortunately we can't reuse rambuf - the hardware may still be
+     * using the buffer. Instead we free it (and the ensuing chain) and
+     * recreate it next time round the loop. If we're lucky the hardware
+     * will have already sent the packet, the free will really free, and
+     * there will be zero memory penalty.
+     */
+
+    pbuf_free(rambuf);
+    left = (u16_t)(left - cop);
+    fragment_offset = (u16_t)(fragment_offset + cop);
+  }
+  return ERR_OK;
+}
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/mld6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/mld6.c
new file mode 100644
index 000000000..6387d468c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/mld6.c
@@ -0,0 +1,626 @@
+/**
+ * @file
+ * Multicast listener discovery
+ *
+ * @defgroup mld6 MLD6
+ * @ingroup ip6
+ * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710.
+ * No support for MLDv2.\n
+ * Note: The allnodes (ff01::1, ff02::1) group is assumed be received by your 
+ * netif since it must always be received for correct IPv6 operation (e.g. SLAAC).
+ * Ensure the netif filters are configured accordingly!\n
+ * The netif flags also need NETIF_FLAG_MLD6 flag set to enable MLD6 on a
+ * netif ("netif->flags |= NETIF_FLAG_MLD6;").\n
+ * To be called from TCPIP thread.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+/* Based on igmp.c implementation of igmp v2 protocol */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/mld6.h"
+#include "lwip/prot/mld6.h"
+#include "lwip/icmp6.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/ip.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/memp.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+
+/*
+ * MLD constants
+ */
+#define MLD6_HL                           1
+#define MLD6_JOIN_DELAYING_MEMBER_TMR_MS  (500)
+
+#define MLD6_GROUP_NON_MEMBER             0
+#define MLD6_GROUP_DELAYING_MEMBER        1
+#define MLD6_GROUP_IDLE_MEMBER            2
+
+/* Forward declarations. */
+static struct mld_group *mld6_new_group(struct netif *ifp, const ip6_addr_t *addr);
+static err_t mld6_remove_group(struct netif *netif, struct mld_group *group);
+static void mld6_delayed_report(struct mld_group *group, u16_t maxresp);
+static void mld6_send(struct netif *netif, struct mld_group *group, u8_t type);
+
+
+/**
+ * Stop MLD processing on interface
+ *
+ * @param netif network interface on which stop MLD processing
+ */
+err_t
+mld6_stop(struct netif *netif)
+{
+  struct mld_group *group = netif_mld6_data(netif);
+
+  netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, NULL);
+
+  while (group != NULL) {
+    struct mld_group *next = group->next; /* avoid use-after-free below */
+
+    /* disable the group at the MAC level */
+    if (netif->mld_mac_filter != NULL) {
+      netif->mld_mac_filter(netif, &(group->group_address), NETIF_DEL_MAC_FILTER);
+    }
+
+    /* free group */
+    memp_free(MEMP_MLD6_GROUP, group);
+
+    /* move to "next" */
+    group = next;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Report MLD memberships for this interface
+ *
+ * @param netif network interface on which report MLD memberships
+ */
+void
+mld6_report_groups(struct netif *netif)
+{
+  struct mld_group *group = netif_mld6_data(netif);
+
+  while (group != NULL) {
+    mld6_delayed_report(group, MLD6_JOIN_DELAYING_MEMBER_TMR_MS);
+    group = group->next;
+  }
+}
+
+/**
+ * Search for a group that is joined on a netif
+ *
+ * @param ifp the network interface for which to look
+ * @param addr the group ipv6 address to search for
+ * @return a struct mld_group* if the group has been found,
+ *         NULL if the group wasn't found.
+ */
+struct mld_group *
+mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr)
+{
+  struct mld_group *group = netif_mld6_data(ifp);
+
+  while (group != NULL) {
+    if (ip6_addr_cmp(&(group->group_address), addr)) {
+      return group;
+    }
+    group = group->next;
+  }
+
+  return NULL;
+}
+
+
+/**
+ * create a new group
+ *
+ * @param ifp the network interface for which to create
+ * @param addr the new group ipv6
+ * @return a struct mld_group*,
+ *         NULL on memory error.
+ */
+static struct mld_group *
+mld6_new_group(struct netif *ifp, const ip6_addr_t *addr)
+{
+  struct mld_group *group;
+
+  group = (struct mld_group *)memp_malloc(MEMP_MLD6_GROUP);
+  if (group != NULL) {
+    ip6_addr_set(&(group->group_address), addr);
+    group->timer              = 0; /* Not running */
+    group->group_state        = MLD6_GROUP_IDLE_MEMBER;
+    group->last_reporter_flag = 0;
+    group->use                = 0;
+    group->next               = netif_mld6_data(ifp);
+
+    netif_set_client_data(ifp, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, group);
+  }
+
+  return group;
+}
+
+/**
+ * Remove a group from the mld_group_list, but do not free it yet
+ *
+ * @param group the group to remove
+ * @return ERR_OK if group was removed from the list, an err_t otherwise
+ */
+static err_t
+mld6_remove_group(struct netif *netif, struct mld_group *group)
+{
+  err_t err = ERR_OK;
+
+  /* Is it the first group? */
+  if (netif_mld6_data(netif) == group) {
+    netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, group->next);
+  } else {
+    /* look for group further down the list */
+    struct mld_group *tmpGroup;
+    for (tmpGroup = netif_mld6_data(netif); tmpGroup != NULL; tmpGroup = tmpGroup->next) {
+      if (tmpGroup->next == group) {
+        tmpGroup->next = group->next;
+        break;
+      }
+    }
+    /* Group not find group */
+    if (tmpGroup == NULL) {
+      err = ERR_ARG;
+    }
+  }
+
+  return err;
+}
+
+
+/**
+ * Process an input MLD message. Called by icmp6_input.
+ *
+ * @param p the mld packet, p->payload pointing to the icmpv6 header
+ * @param inp the netif on which this packet was received
+ */
+void
+mld6_input(struct pbuf *p, struct netif *inp)
+{
+  struct mld_header *mld_hdr;
+  struct mld_group *group;
+
+  MLD6_STATS_INC(mld6.recv);
+
+  /* Check that mld header fits in packet. */
+  if (p->len < sizeof(struct mld_header)) {
+    /* @todo debug message */
+    pbuf_free(p);
+    MLD6_STATS_INC(mld6.lenerr);
+    MLD6_STATS_INC(mld6.drop);
+    return;
+  }
+
+  mld_hdr = (struct mld_header *)p->payload;
+
+  switch (mld_hdr->type) {
+  case ICMP6_TYPE_MLQ: /* Multicast listener query. */
+    /* Is it a general query? */
+    if (ip6_addr_isallnodes_linklocal(ip6_current_dest_addr()) &&
+        ip6_addr_isany(&(mld_hdr->multicast_address))) {
+      MLD6_STATS_INC(mld6.rx_general);
+      /* Report all groups, except all nodes group, and if-local groups. */
+      group = netif_mld6_data(inp);
+      while (group != NULL) {
+        if ((!(ip6_addr_ismulticast_iflocal(&(group->group_address)))) &&
+            (!(ip6_addr_isallnodes_linklocal(&(group->group_address))))) {
+          mld6_delayed_report(group, mld_hdr->max_resp_delay);
+        }
+        group = group->next;
+      }
+    } else {
+      /* Have we joined this group?
+       * We use IP6 destination address to have a memory aligned copy.
+       * mld_hdr->multicast_address should be the same. */
+      MLD6_STATS_INC(mld6.rx_group);
+      group = mld6_lookfor_group(inp, ip6_current_dest_addr());
+      if (group != NULL) {
+        /* Schedule a report. */
+        mld6_delayed_report(group, mld_hdr->max_resp_delay);
+      }
+    }
+    break; /* ICMP6_TYPE_MLQ */
+  case ICMP6_TYPE_MLR: /* Multicast listener report. */
+    /* Have we joined this group?
+     * We use IP6 destination address to have a memory aligned copy.
+     * mld_hdr->multicast_address should be the same. */
+    MLD6_STATS_INC(mld6.rx_report);
+    group = mld6_lookfor_group(inp, ip6_current_dest_addr());
+    if (group != NULL) {
+      /* If we are waiting to report, cancel it. */
+      if (group->group_state == MLD6_GROUP_DELAYING_MEMBER) {
+        group->timer = 0; /* stopped */
+        group->group_state = MLD6_GROUP_IDLE_MEMBER;
+        group->last_reporter_flag = 0;
+      }
+    }
+    break; /* ICMP6_TYPE_MLR */
+  case ICMP6_TYPE_MLD: /* Multicast listener done. */
+    /* Do nothing, router will query us. */
+    break; /* ICMP6_TYPE_MLD */
+  default:
+    MLD6_STATS_INC(mld6.proterr);
+    MLD6_STATS_INC(mld6.drop);
+    break;
+  }
+
+  pbuf_free(p);
+}
+
+/**
+ * @ingroup mld6
+ * Join a group on one or all network interfaces.
+ *
+ * If the group is to be joined on all interfaces, the given group address must
+ * not have a zone set (i.e., it must have its zone index set to IP6_NO_ZONE).
+ * If the group is to be joined on one particular interface, the given group
+ * address may or may not have a zone set.
+ *
+ * @param srcaddr ipv6 address (zoned) of the network interface which should
+ *                join a new group. If IP6_ADDR_ANY6, join on all netifs
+ * @param groupaddr the ipv6 address of the group to join (possibly but not
+ *                  necessarily zoned)
+ * @return ERR_OK if group was joined on the netif(s), an err_t otherwise
+ */
+err_t
+mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr)
+{
+  err_t         err = ERR_VAL; /* no matching interface */
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    /* Should we join this interface ? */
+    if (ip6_addr_isany(srcaddr) ||
+        netif_get_ip6_addr_match(netif, srcaddr) >= 0) {
+      err = mld6_joingroup_netif(netif, groupaddr);
+      if (err != ERR_OK) {
+        return err;
+      }
+    }
+  }
+
+  return err;
+}
+
+/**
+ * @ingroup mld6
+ * Join a group on a network interface.
+ *
+ * @param netif the network interface which should join a new group.
+ * @param groupaddr the ipv6 address of the group to join (possibly but not
+ *                  necessarily zoned)
+ * @return ERR_OK if group was joined on the netif, an err_t otherwise
+ */
+err_t
+mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr)
+{
+  struct mld_group *group;
+#if LWIP_IPV6_SCOPES
+  ip6_addr_t ip6addr;
+
+  /* If the address has a particular scope but no zone set, use the netif to
+   * set one now. Within the mld6 module, all addresses are properly zoned. */
+  if (ip6_addr_lacks_zone(groupaddr, IP6_MULTICAST)) {
+    ip6_addr_set(&ip6addr, groupaddr);
+    ip6_addr_assign_zone(&ip6addr, IP6_MULTICAST, netif);
+    groupaddr = &ip6addr;
+  }
+  IP6_ADDR_ZONECHECK_NETIF(groupaddr, netif);
+#endif /* LWIP_IPV6_SCOPES */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* find group or create a new one if not found */
+  group = mld6_lookfor_group(netif, groupaddr);
+
+  if (group == NULL) {
+    /* Joining a new group. Create a new group entry. */
+    group = mld6_new_group(netif, groupaddr);
+    if (group == NULL) {
+      return ERR_MEM;
+    }
+
+    /* Activate this address on the MAC layer. */
+    if (netif->mld_mac_filter != NULL) {
+      netif->mld_mac_filter(netif, groupaddr, NETIF_ADD_MAC_FILTER);
+    }
+
+    /* Report our membership. */
+    MLD6_STATS_INC(mld6.tx_report);
+    mld6_send(netif, group, ICMP6_TYPE_MLR);
+    mld6_delayed_report(group, MLD6_JOIN_DELAYING_MEMBER_TMR_MS);
+  }
+
+  /* Increment group use */
+  group->use++;
+  return ERR_OK;
+}
+
+/**
+ * @ingroup mld6
+ * Leave a group on a network interface.
+ *
+ * Zoning of address follows the same rules as @ref mld6_joingroup.
+ *
+ * @param srcaddr ipv6 address (zoned) of the network interface which should
+ *                leave the group. If IP6_ADDR_ANY6, leave on all netifs
+ * @param groupaddr the ipv6 address of the group to leave (possibly, but not
+ *                  necessarily zoned)
+ * @return ERR_OK if group was left on the netif(s), an err_t otherwise
+ */
+err_t
+mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr)
+{
+  err_t         err = ERR_VAL; /* no matching interface */
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* loop through netif's */
+  NETIF_FOREACH(netif) {
+    /* Should we leave this interface ? */
+    if (ip6_addr_isany(srcaddr) ||
+        netif_get_ip6_addr_match(netif, srcaddr) >= 0) {
+      err_t res = mld6_leavegroup_netif(netif, groupaddr);
+      if (err != ERR_OK) {
+        /* Store this result if we have not yet gotten a success */
+        err = res;
+      }
+    }
+  }
+
+  return err;
+}
+
+/**
+ * @ingroup mld6
+ * Leave a group on a network interface.
+ *
+ * @param netif the network interface which should leave the group.
+ * @param groupaddr the ipv6 address of the group to leave (possibly, but not
+ *                  necessarily zoned)
+ * @return ERR_OK if group was left on the netif, an err_t otherwise
+ */
+err_t
+mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr)
+{
+  struct mld_group *group;
+#if LWIP_IPV6_SCOPES
+  ip6_addr_t ip6addr;
+
+  if (ip6_addr_lacks_zone(groupaddr, IP6_MULTICAST)) {
+    ip6_addr_set(&ip6addr, groupaddr);
+    ip6_addr_assign_zone(&ip6addr, IP6_MULTICAST, netif);
+    groupaddr = &ip6addr;
+  }
+  IP6_ADDR_ZONECHECK_NETIF(groupaddr, netif);
+#endif /* LWIP_IPV6_SCOPES */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* find group */
+  group = mld6_lookfor_group(netif, groupaddr);
+
+  if (group != NULL) {
+    /* Leave if there is no other use of the group */
+    if (group->use <= 1) {
+      /* Remove the group from the list */
+      mld6_remove_group(netif, group);
+
+      /* If we are the last reporter for this group */
+      if (group->last_reporter_flag) {
+        MLD6_STATS_INC(mld6.tx_leave);
+        mld6_send(netif, group, ICMP6_TYPE_MLD);
+      }
+
+      /* Disable the group at the MAC level */
+      if (netif->mld_mac_filter != NULL) {
+        netif->mld_mac_filter(netif, groupaddr, NETIF_DEL_MAC_FILTER);
+      }
+
+      /* free group struct */
+      memp_free(MEMP_MLD6_GROUP, group);
+    } else {
+      /* Decrement group use */
+      group->use--;
+    }
+
+    /* Left group */
+    return ERR_OK;
+  }
+
+  /* Group not found */
+  return ERR_VAL;
+}
+
+
+/**
+ * Periodic timer for mld processing. Must be called every
+ * MLD6_TMR_INTERVAL milliseconds (100).
+ *
+ * When a delaying member expires, a membership report is sent.
+ */
+void
+mld6_tmr(void)
+{
+  struct netif *netif;
+
+  NETIF_FOREACH(netif) {
+    struct mld_group *group = netif_mld6_data(netif);
+
+    while (group != NULL) {
+      if (group->timer > 0) {
+        group->timer--;
+        if (group->timer == 0) {
+          /* If the state is MLD6_GROUP_DELAYING_MEMBER then we send a report for this group */
+          if (group->group_state == MLD6_GROUP_DELAYING_MEMBER) {
+            MLD6_STATS_INC(mld6.tx_report);
+            mld6_send(netif, group, ICMP6_TYPE_MLR);
+            group->group_state = MLD6_GROUP_IDLE_MEMBER;
+          }
+        }
+      }
+      group = group->next;
+    }
+  }
+}
+
+/**
+ * Schedule a delayed membership report for a group
+ *
+ * @param group the mld_group for which "delaying" membership report
+ *              should be sent
+ * @param maxresp_in the max resp delay provided in the query
+ */
+static void
+mld6_delayed_report(struct mld_group *group, u16_t maxresp_in)
+{
+  /* Convert maxresp from milliseconds to tmr ticks */
+  u16_t maxresp = maxresp_in / MLD6_TMR_INTERVAL;
+  if (maxresp == 0) {
+    maxresp = 1;
+  }
+
+#ifdef LWIP_RAND
+  /* Randomize maxresp. (if LWIP_RAND is supported) */
+  maxresp = (u16_t)(LWIP_RAND() % maxresp);
+  if (maxresp == 0) {
+    maxresp = 1;
+  }
+#endif /* LWIP_RAND */
+
+  /* Apply timer value if no report has been scheduled already. */
+  if ((group->group_state == MLD6_GROUP_IDLE_MEMBER) ||
+     ((group->group_state == MLD6_GROUP_DELAYING_MEMBER) &&
+      ((group->timer == 0) || (maxresp < group->timer)))) {
+    group->timer = maxresp;
+    group->group_state = MLD6_GROUP_DELAYING_MEMBER;
+  }
+}
+
+/**
+ * Send a MLD message (report or done).
+ *
+ * An IPv6 hop-by-hop options header with a router alert option
+ * is prepended.
+ *
+ * @param group the group to report or quit
+ * @param type ICMP6_TYPE_MLR (report) or ICMP6_TYPE_MLD (done)
+ */
+static void
+mld6_send(struct netif *netif, struct mld_group *group, u8_t type)
+{
+  struct mld_header *mld_hdr;
+  struct pbuf *p;
+  const ip6_addr_t *src_addr;
+
+  /* Allocate a packet. Size is MLD header + IPv6 Hop-by-hop options header. */
+  p = pbuf_alloc(PBUF_IP, sizeof(struct mld_header) + MLD6_HBH_HLEN, PBUF_RAM);
+  if (p == NULL) {
+    MLD6_STATS_INC(mld6.memerr);
+    return;
+  }
+
+  /* Move to make room for Hop-by-hop options header. */
+  if (pbuf_remove_header(p, MLD6_HBH_HLEN)) {
+    pbuf_free(p);
+    MLD6_STATS_INC(mld6.lenerr);
+    return;
+  }
+
+  /* Select our source address. */
+  if (!ip6_addr_isvalid(netif_ip6_addr_state(netif, 0))) {
+    /* This is a special case, when we are performing duplicate address detection.
+     * We must join the multicast group, but we don't have a valid address yet. */
+    src_addr = IP6_ADDR_ANY6;
+  } else {
+    /* Use link-local address as source address. */
+    src_addr = netif_ip6_addr(netif, 0);
+  }
+
+  /* MLD message header pointer. */
+  mld_hdr = (struct mld_header *)p->payload;
+
+  /* Set fields. */
+  mld_hdr->type = type;
+  mld_hdr->code = 0;
+  mld_hdr->chksum = 0;
+  mld_hdr->max_resp_delay = 0;
+  mld_hdr->reserved = 0;
+  ip6_addr_copy_to_packed(mld_hdr->multicast_address, group->group_address);
+
+#if CHECKSUM_GEN_ICMP6
+  IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) {
+    mld_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len,
+      src_addr, &(group->group_address));
+  }
+#endif /* CHECKSUM_GEN_ICMP6 */
+
+  /* Add hop-by-hop headers options: router alert with MLD value. */
+  ip6_options_add_hbh_ra(p, IP6_NEXTH_ICMP6, IP6_ROUTER_ALERT_VALUE_MLD);
+
+  if (type == ICMP6_TYPE_MLR) {
+    /* Remember we were the last to report */
+    group->last_reporter_flag = 1;
+  }
+
+  /* Send the packet out. */
+  MLD6_STATS_INC(mld6.xmit);
+  ip6_output_if(p, (ip6_addr_isany(src_addr)) ? NULL : src_addr, &(group->group_address),
+      MLD6_HL, 0, IP6_NEXTH_HOPBYHOP, netif);
+  pbuf_free(p);
+}
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/nd6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/nd6.c
new file mode 100644
index 000000000..db0c132e4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/ipv6/nd6.c
@@ -0,0 +1,2434 @@
+/**
+ * @file
+ *
+ * Neighbor discovery and stateless address autoconfiguration for IPv6.
+ * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
+ * (Address autoconfiguration).
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/nd6.h"
+#include "lwip/priv/nd6_priv.h"
+#include "lwip/prot/nd6.h"
+#include "lwip/prot/icmp6.h"
+#include "lwip/pbuf.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/netif.h"
+#include "lwip/icmp6.h"
+#include "lwip/mld6.h"
+#include "lwip/dhcp6.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+#include "lwip/dns.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+#if LWIP_IPV6_DUP_DETECT_ATTEMPTS > IP6_ADDR_TENTATIVE_COUNT_MASK
+#error LWIP_IPV6_DUP_DETECT_ATTEMPTS > IP6_ADDR_TENTATIVE_COUNT_MASK
+#endif
+
+/* Router tables. */
+struct nd6_neighbor_cache_entry neighbor_cache[LWIP_ND6_NUM_NEIGHBORS];
+struct nd6_destination_cache_entry destination_cache[LWIP_ND6_NUM_DESTINATIONS];
+struct nd6_prefix_list_entry prefix_list[LWIP_ND6_NUM_PREFIXES];
+struct nd6_router_list_entry default_router_list[LWIP_ND6_NUM_ROUTERS];
+
+/* Default values, can be updated by a RA message. */
+u32_t reachable_time = LWIP_ND6_REACHABLE_TIME;
+u32_t retrans_timer = LWIP_ND6_RETRANS_TIMER; /* @todo implement this value in timer */
+
+/* Index for cache entries. */
+static u8_t nd6_cached_neighbor_index;
+static netif_addr_idx_t nd6_cached_destination_index;
+
+/* Multicast address holder. */
+static ip6_addr_t multicast_address;
+
+static u8_t nd6_tmr_rs_reduction;
+
+/* Static buffer to parse RA packet options */
+union ra_options {
+  struct lladdr_option  lladdr;
+  struct mtu_option     mtu;
+  struct prefix_option  prefix;
+#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS
+  struct rdnss_option   rdnss;
+#endif
+};
+static union ra_options nd6_ra_buffer;
+
+/* Forward declarations. */
+static s8_t nd6_find_neighbor_cache_entry(const ip6_addr_t *ip6addr);
+static s8_t nd6_new_neighbor_cache_entry(void);
+static void nd6_free_neighbor_cache_entry(s8_t i);
+static s16_t nd6_find_destination_cache_entry(const ip6_addr_t *ip6addr);
+static s16_t nd6_new_destination_cache_entry(void);
+static int nd6_is_prefix_in_netif(const ip6_addr_t *ip6addr, struct netif *netif);
+static s8_t nd6_select_router(const ip6_addr_t *ip6addr, struct netif *netif);
+static s8_t nd6_get_router(const ip6_addr_t *router_addr, struct netif *netif);
+static s8_t nd6_new_router(const ip6_addr_t *router_addr, struct netif *netif);
+static s8_t nd6_get_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif);
+static s8_t nd6_new_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif);
+static s8_t nd6_get_next_hop_entry(const ip6_addr_t *ip6addr, struct netif *netif);
+static err_t nd6_queue_packet(s8_t neighbor_index, struct pbuf *q);
+
+#define ND6_SEND_FLAG_MULTICAST_DEST 0x01
+#define ND6_SEND_FLAG_ALLNODES_DEST 0x02
+#define ND6_SEND_FLAG_ANY_SRC 0x04
+static void nd6_send_ns(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags);
+static void nd6_send_na(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags);
+static void nd6_send_neighbor_cache_probe(struct nd6_neighbor_cache_entry *entry, u8_t flags);
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+static err_t nd6_send_rs(struct netif *netif);
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+
+#if LWIP_ND6_QUEUEING
+static void nd6_free_q(struct nd6_q_entry *q);
+#else /* LWIP_ND6_QUEUEING */
+#define nd6_free_q(q) pbuf_free(q)
+#endif /* LWIP_ND6_QUEUEING */
+static void nd6_send_q(s8_t i);
+
+
+/**
+ * A local address has been determined to be a duplicate. Take the appropriate
+ * action(s) on the address and the interface as a whole.
+ *
+ * @param netif the netif that owns the address
+ * @param addr_idx the index of the address detected to be a duplicate
+ */
+static void
+nd6_duplicate_addr_detected(struct netif *netif, s8_t addr_idx)
+{
+
+  /* Mark the address as duplicate, but leave its lifetimes alone. If this was
+   * a manually assigned address, it will remain in existence as duplicate, and
+   * as such be unusable for any practical purposes until manual intervention.
+   * If this was an autogenerated address, the address will follow normal
+   * expiration rules, and thus disappear once its valid lifetime expires. */
+  netif_ip6_addr_set_state(netif, addr_idx, IP6_ADDR_DUPLICATED);
+
+#if LWIP_IPV6_AUTOCONFIG
+  /* If the affected address was the link-local address that we use to generate
+   * all other addresses, then we should not continue to use those derived
+   * addresses either, so mark them as duplicate as well. For autoconfig-only
+   * setups, this will make the interface effectively unusable, approaching the
+   * intention of RFC 4862 Sec. 5.4.5. @todo implement the full requirements */
+  if (addr_idx == 0) {
+    s8_t i;
+    for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+      if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i)) &&
+          !netif_ip6_addr_isstatic(netif, i)) {
+        netif_ip6_addr_set_state(netif, i, IP6_ADDR_DUPLICATED);
+      }
+    }
+  }
+#endif /* LWIP_IPV6_AUTOCONFIG */
+}
+
+#if LWIP_IPV6_AUTOCONFIG
+/**
+ * We received a router advertisement that contains a prefix with the
+ * autoconfiguration flag set. Add or update an associated autogenerated
+ * address.
+ *
+ * @param netif the netif on which the router advertisement arrived
+ * @param prefix_opt a pointer to the prefix option data
+ * @param prefix_addr an aligned copy of the prefix address
+ */
+static void
+nd6_process_autoconfig_prefix(struct netif *netif,
+  struct prefix_option *prefix_opt, const ip6_addr_t *prefix_addr)
+{
+  ip6_addr_t ip6addr;
+  u32_t valid_life, pref_life;
+  u8_t addr_state;
+  s8_t i, free_idx;
+
+  /* The caller already checks RFC 4862 Sec. 5.5.3 points (a) and (b). We do
+   * the rest, starting with checks for (c) and (d) here. */
+  valid_life = lwip_htonl(prefix_opt->valid_lifetime);
+  pref_life = lwip_htonl(prefix_opt->preferred_lifetime);
+  if (pref_life > valid_life || prefix_opt->prefix_length != 64) {
+    return; /* silently ignore this prefix for autoconfiguration purposes */
+  }
+
+  /* If an autogenerated address already exists for this prefix, update its
+   * lifetimes. An address is considered autogenerated if 1) it is not static
+   * (i.e., manually assigned), and 2) there is an advertised autoconfiguration
+   * prefix for it (the one we are processing here). This does not necessarily
+   * exclude the possibility that the address was actually assigned by, say,
+   * DHCPv6. If that distinction becomes important in the future, more state
+   * must be kept. As explained elsewhere we also update lifetimes of tentative
+   * and duplicate addresses. Skip address slot 0 (the link-local address). */
+  for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    addr_state = netif_ip6_addr_state(netif, i);
+    if (!ip6_addr_isinvalid(addr_state) && !netif_ip6_addr_isstatic(netif, i) &&
+        ip6_addr_netcmp(prefix_addr, netif_ip6_addr(netif, i))) {
+      /* Update the valid lifetime, as per RFC 4862 Sec. 5.5.3 point (e).
+       * The valid lifetime will never drop to zero as a result of this. */
+      u32_t remaining_life = netif_ip6_addr_valid_life(netif, i);
+      if (valid_life > ND6_2HRS || valid_life > remaining_life) {
+        netif_ip6_addr_set_valid_life(netif, i, valid_life);
+      } else if (remaining_life > ND6_2HRS) {
+        netif_ip6_addr_set_valid_life(netif, i, ND6_2HRS);
+      }
+      LWIP_ASSERT("bad valid lifetime", !netif_ip6_addr_isstatic(netif, i));
+      /* Update the preferred lifetime. No bounds checks are needed here. In
+       * rare cases the advertisement may un-deprecate the address, though.
+       * Deprecation is left to the timer code where it is handled anyway. */
+      if (pref_life > 0 && addr_state == IP6_ADDR_DEPRECATED) {
+        netif_ip6_addr_set_state(netif, i, IP6_ADDR_PREFERRED);
+      }
+      netif_ip6_addr_set_pref_life(netif, i, pref_life);
+      return; /* there should be at most one matching address */
+    }
+  }
+
+  /* No autogenerated address exists for this prefix yet. See if we can add a
+   * new one. However, if IPv6 autoconfiguration is administratively disabled,
+   * do not generate new addresses, but do keep updating lifetimes for existing
+   * addresses. Also, when adding new addresses, we must protect explicitly
+   * against a valid lifetime of zero, because again, we use that as a special
+   * value. The generated address would otherwise expire immediately anyway.
+   * Finally, the original link-local address must be usable at all. We start
+   * creating addresses even if the link-local address is still in tentative
+   * state though, and deal with the fallout of that upon DAD collision. */
+  addr_state = netif_ip6_addr_state(netif, 0);
+  if (!netif->ip6_autoconfig_enabled || valid_life == IP6_ADDR_LIFE_STATIC ||
+      ip6_addr_isinvalid(addr_state) || ip6_addr_isduplicated(addr_state)) {
+    return;
+  }
+
+  /* Construct the new address that we intend to use, and then see if that
+   * address really does not exist. It might have been added manually, after
+   * all. As a side effect, find a free slot. Note that we cannot use
+   * netif_add_ip6_address() here, as it would return ERR_OK if the address
+   * already did exist, resulting in that address being given lifetimes. */
+  IP6_ADDR(&ip6addr, prefix_addr->addr[0], prefix_addr->addr[1],
+    netif_ip6_addr(netif, 0)->addr[2], netif_ip6_addr(netif, 0)->addr[3]);
+  ip6_addr_assign_zone(&ip6addr, IP6_UNICAST, netif);
+
+  free_idx = 0;
+  for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i))) {
+      if (ip6_addr_cmp(&ip6addr, netif_ip6_addr(netif, i))) {
+        return; /* formed address already exists */
+      }
+    } else if (free_idx == 0) {
+      free_idx = i;
+    }
+  }
+  if (free_idx == 0) {
+    return; /* no address slots available, try again on next advertisement */
+  }
+
+  /* Assign the new address to the interface. */
+  ip_addr_copy_from_ip6(netif->ip6_addr[free_idx], ip6addr);
+  netif_ip6_addr_set_valid_life(netif, free_idx, valid_life);
+  netif_ip6_addr_set_pref_life(netif, free_idx, pref_life);
+  netif_ip6_addr_set_state(netif, free_idx, IP6_ADDR_TENTATIVE);
+}
+#endif /* LWIP_IPV6_AUTOCONFIG */
+
+/**
+ * Process an incoming neighbor discovery message
+ *
+ * @param p the nd packet, p->payload pointing to the icmpv6 header
+ * @param inp the netif on which this packet was received
+ */
+void
+nd6_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t msg_type;
+  s8_t i;
+  s16_t dest_idx;
+
+  ND6_STATS_INC(nd6.recv);
+
+  msg_type = *((u8_t *)p->payload);
+  switch (msg_type) {
+  case ICMP6_TYPE_NA: /* Neighbor Advertisement. */
+  {
+    struct na_header *na_hdr;
+    struct lladdr_option *lladdr_opt;
+    ip6_addr_t target_address;
+
+    /* Check that na header fits in packet. */
+    if (p->len < (sizeof(struct na_header))) {
+      /* @todo debug message */
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.lenerr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    na_hdr = (struct na_header *)p->payload;
+
+    /* Create an aligned, zoned copy of the target address. */
+    ip6_addr_copy_from_packed(target_address, na_hdr->target_address);
+    ip6_addr_assign_zone(&target_address, IP6_UNICAST, inp);
+
+    /* Check a subset of the other RFC 4861 Sec. 7.1.2 requirements. */
+    if (IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || na_hdr->code != 0 ||
+        ip6_addr_ismulticast(&target_address)) {
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.proterr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    /* @todo RFC MUST: if IP destination is multicast, Solicited flag is zero */
+    /* @todo RFC MUST: all included options have a length greater than zero */
+
+    /* Unsolicited NA?*/
+    if (ip6_addr_ismulticast(ip6_current_dest_addr())) {
+      /* This is an unsolicited NA.
+       * link-layer changed?
+       * part of DAD mechanism? */
+
+#if LWIP_IPV6_DUP_DETECT_ATTEMPTS
+      /* If the target address matches this netif, it is a DAD response. */
+      for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+        if (!ip6_addr_isinvalid(netif_ip6_addr_state(inp, i)) &&
+            !ip6_addr_isduplicated(netif_ip6_addr_state(inp, i)) &&
+            ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) {
+          /* We are using a duplicate address. */
+          nd6_duplicate_addr_detected(inp, i);
+
+          pbuf_free(p);
+          return;
+        }
+      }
+#endif /* LWIP_IPV6_DUP_DETECT_ATTEMPTS */
+
+      /* Check that link-layer address option also fits in packet. */
+      if (p->len < (sizeof(struct na_header) + 2)) {
+        /* @todo debug message */
+        pbuf_free(p);
+        ND6_STATS_INC(nd6.lenerr);
+        ND6_STATS_INC(nd6.drop);
+        return;
+      }
+
+      lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header));
+
+      if (p->len < (sizeof(struct na_header) + (lladdr_opt->length << 3))) {
+        /* @todo debug message */
+        pbuf_free(p);
+        ND6_STATS_INC(nd6.lenerr);
+        ND6_STATS_INC(nd6.drop);
+        return;
+      }
+
+      /* This is an unsolicited NA, most likely there was a LLADDR change. */
+      i = nd6_find_neighbor_cache_entry(&target_address);
+      if (i >= 0) {
+        if (na_hdr->flags & ND6_FLAG_OVERRIDE) {
+          MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len);
+        }
+      }
+    } else {
+      /* This is a solicited NA.
+       * neighbor address resolution response?
+       * neighbor unreachability detection response? */
+
+      /* Find the cache entry corresponding to this na. */
+      i = nd6_find_neighbor_cache_entry(&target_address);
+      if (i < 0) {
+        /* We no longer care about this target address. drop it. */
+        pbuf_free(p);
+        return;
+      }
+
+      /* Update cache entry. */
+      if ((na_hdr->flags & ND6_FLAG_OVERRIDE) ||
+          (neighbor_cache[i].state == ND6_INCOMPLETE)) {
+        /* Check that link-layer address option also fits in packet. */
+        if (p->len < (sizeof(struct na_header) + 2)) {
+          /* @todo debug message */
+          pbuf_free(p);
+          ND6_STATS_INC(nd6.lenerr);
+          ND6_STATS_INC(nd6.drop);
+          return;
+        }
+
+        lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header));
+
+        if (p->len < (sizeof(struct na_header) + (lladdr_opt->length << 3))) {
+          /* @todo debug message */
+          pbuf_free(p);
+          ND6_STATS_INC(nd6.lenerr);
+          ND6_STATS_INC(nd6.drop);
+          return;
+        }
+
+        MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len);
+      }
+
+      neighbor_cache[i].netif = inp;
+      neighbor_cache[i].state = ND6_REACHABLE;
+      neighbor_cache[i].counter.reachable_time = reachable_time;
+
+      /* Send queued packets, if any. */
+      if (neighbor_cache[i].q != NULL) {
+        nd6_send_q(i);
+      }
+    }
+
+    break; /* ICMP6_TYPE_NA */
+  }
+  case ICMP6_TYPE_NS: /* Neighbor solicitation. */
+  {
+    struct ns_header *ns_hdr;
+    struct lladdr_option *lladdr_opt;
+    ip6_addr_t target_address;
+    u8_t accepted;
+
+    /* Check that ns header fits in packet. */
+    if (p->len < sizeof(struct ns_header)) {
+      /* @todo debug message */
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.lenerr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    ns_hdr = (struct ns_header *)p->payload;
+
+    /* Create an aligned, zoned copy of the target address. */
+    ip6_addr_copy_from_packed(target_address, ns_hdr->target_address);
+    ip6_addr_assign_zone(&target_address, IP6_UNICAST, inp);
+
+    /* Check a subset of the other RFC 4861 Sec. 7.1.1 requirements. */
+    if (IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || ns_hdr->code != 0 ||
+       ip6_addr_ismulticast(&target_address)) {
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.proterr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    /* @todo RFC MUST: all included options have a length greater than zero */
+    /* @todo RFC MUST: if IP source is 'any', destination is solicited-node multicast address */
+    /* @todo RFC MUST: if IP source is 'any', there is no source LL address option */
+
+    /* Check if there is a link-layer address provided. Only point to it if in this buffer. */
+    if (p->len >= (sizeof(struct ns_header) + 2)) {
+      lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct ns_header));
+      if (p->len < (sizeof(struct ns_header) + (lladdr_opt->length << 3))) {
+        lladdr_opt = NULL;
+      }
+    } else {
+      lladdr_opt = NULL;
+    }
+
+    /* Check if the target address is configured on the receiving netif. */
+    accepted = 0;
+    for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) {
+      if ((ip6_addr_isvalid(netif_ip6_addr_state(inp, i)) ||
+           (ip6_addr_istentative(netif_ip6_addr_state(inp, i)) &&
+            ip6_addr_isany(ip6_current_src_addr()))) &&
+          ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) {
+        accepted = 1;
+        break;
+      }
+    }
+
+    /* NS not for us? */
+    if (!accepted) {
+      pbuf_free(p);
+      return;
+    }
+
+    /* Check for ANY address in src (DAD algorithm). */
+    if (ip6_addr_isany(ip6_current_src_addr())) {
+      /* Sender is validating this address. */
+      for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) {
+        if (!ip6_addr_isinvalid(netif_ip6_addr_state(inp, i)) &&
+            ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) {
+          /* Send a NA back so that the sender does not use this address. */
+          nd6_send_na(inp, netif_ip6_addr(inp, i), ND6_FLAG_OVERRIDE | ND6_SEND_FLAG_ALLNODES_DEST);
+          if (ip6_addr_istentative(netif_ip6_addr_state(inp, i))) {
+            /* We shouldn't use this address either. */
+            nd6_duplicate_addr_detected(inp, i);
+          }
+        }
+      }
+    } else {
+      /* Sender is trying to resolve our address. */
+      /* Verify that they included their own link-layer address. */
+      if (lladdr_opt == NULL) {
+        /* Not a valid message. */
+        pbuf_free(p);
+        ND6_STATS_INC(nd6.proterr);
+        ND6_STATS_INC(nd6.drop);
+        return;
+      }
+
+      i = nd6_find_neighbor_cache_entry(ip6_current_src_addr());
+      if (i>= 0) {
+        /* We already have a record for the solicitor. */
+        if (neighbor_cache[i].state == ND6_INCOMPLETE) {
+          neighbor_cache[i].netif = inp;
+          MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len);
+
+          /* Delay probe in case we get confirmation of reachability from upper layer (TCP). */
+          neighbor_cache[i].state = ND6_DELAY;
+          neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL;
+        }
+      } else {
+        /* Add their IPv6 address and link-layer address to neighbor cache.
+         * We will need it at least to send a unicast NA message, but most
+         * likely we will also be communicating with this node soon. */
+        i = nd6_new_neighbor_cache_entry();
+        if (i < 0) {
+          /* We couldn't assign a cache entry for this neighbor.
+           * we won't be able to reply. drop it. */
+          pbuf_free(p);
+          ND6_STATS_INC(nd6.memerr);
+          return;
+        }
+        neighbor_cache[i].netif = inp;
+        MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len);
+        ip6_addr_set(&(neighbor_cache[i].next_hop_address), ip6_current_src_addr());
+
+        /* Receiving a message does not prove reachability: only in one direction.
+         * Delay probe in case we get confirmation of reachability from upper layer (TCP). */
+        neighbor_cache[i].state = ND6_DELAY;
+        neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL;
+      }
+
+      /* Send back a NA for us. Allocate the reply pbuf. */
+      nd6_send_na(inp, &target_address, ND6_FLAG_SOLICITED | ND6_FLAG_OVERRIDE);
+    }
+
+    break; /* ICMP6_TYPE_NS */
+  }
+  case ICMP6_TYPE_RA: /* Router Advertisement. */
+  {
+    struct ra_header *ra_hdr;
+    u8_t *buffer; /* Used to copy options. */
+    u16_t offset;
+#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS
+    /* There can be multiple RDNSS options per RA */
+    u8_t rdnss_server_idx = 0;
+#endif /* LWIP_ND6_RDNSS_MAX_DNS_SERVERS */
+
+    /* Check that RA header fits in packet. */
+    if (p->len < sizeof(struct ra_header)) {
+      /* @todo debug message */
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.lenerr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    ra_hdr = (struct ra_header *)p->payload;
+
+    /* Check a subset of the other RFC 4861 Sec. 6.1.2 requirements. */
+    if (!ip6_addr_islinklocal(ip6_current_src_addr()) ||
+        IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || ra_hdr->code != 0) {
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.proterr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    /* @todo RFC MUST: all included options have a length greater than zero */
+
+    /* If we are sending RS messages, stop. */
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+    /* ensure at least one solicitation is sent (see RFC 4861, ch. 6.3.7) */
+    if ((inp->rs_count < LWIP_ND6_MAX_MULTICAST_SOLICIT) ||
+        (nd6_send_rs(inp) == ERR_OK)) {
+      inp->rs_count = 0;
+    } else {
+      inp->rs_count = 1;
+    }
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+
+    /* Get the matching default router entry. */
+    i = nd6_get_router(ip6_current_src_addr(), inp);
+    if (i < 0) {
+      /* Create a new router entry. */
+      i = nd6_new_router(ip6_current_src_addr(), inp);
+    }
+
+    if (i < 0) {
+      /* Could not create a new router entry. */
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.memerr);
+      return;
+    }
+
+    /* Re-set invalidation timer. */
+    default_router_list[i].invalidation_timer = lwip_htons(ra_hdr->router_lifetime);
+
+    /* Re-set default timer values. */
+#if LWIP_ND6_ALLOW_RA_UPDATES
+    if (ra_hdr->retrans_timer > 0) {
+      retrans_timer = lwip_htonl(ra_hdr->retrans_timer);
+    }
+    if (ra_hdr->reachable_time > 0) {
+      reachable_time = lwip_htonl(ra_hdr->reachable_time);
+    }
+#endif /* LWIP_ND6_ALLOW_RA_UPDATES */
+
+    /* @todo set default hop limit... */
+    /* ra_hdr->current_hop_limit;*/
+
+    /* Update flags in local entry (incl. preference). */
+    default_router_list[i].flags = ra_hdr->flags;
+
+#if LWIP_IPV6_DHCP6
+    /* Trigger DHCPv6 if enabled */
+    dhcp6_nd6_ra_trigger(inp, ra_hdr->flags & ND6_RA_FLAG_MANAGED_ADDR_CONFIG,
+      ra_hdr->flags & ND6_RA_FLAG_OTHER_CONFIG);
+#endif
+
+    /* Offset to options. */
+    offset = sizeof(struct ra_header);
+
+    /* Process each option. */
+    while ((p->tot_len - offset) >= 2) {
+      u8_t option_type;
+      u16_t option_len;
+      int option_len8 = pbuf_try_get_at(p, offset + 1);
+      if (option_len8 <= 0) {
+        /* read beyond end or zero length */
+        goto lenerr_drop_free_return;
+      }
+      option_len = ((u8_t)option_len8) << 3;
+      if (option_len > p->tot_len - offset) {
+        /* short packet (option does not fit in) */
+        goto lenerr_drop_free_return;
+      }
+      if (p->len == p->tot_len) {
+        /* no need to copy from contiguous pbuf */
+        buffer = &((u8_t*)p->payload)[offset];
+      } else {
+        /* check if this option fits into our buffer */
+        if (option_len > sizeof(nd6_ra_buffer)) {
+          option_type = pbuf_get_at(p, offset);
+          /* invalid option length */
+          if (option_type != ND6_OPTION_TYPE_RDNSS) {
+            goto lenerr_drop_free_return;
+          }
+          /* we allow RDNSS option to be longer - we'll just drop some servers */
+          option_len = sizeof(nd6_ra_buffer);
+        }
+        buffer = (u8_t*)&nd6_ra_buffer;
+        option_len = pbuf_copy_partial(p, &nd6_ra_buffer, option_len, offset);
+      }
+      option_type = buffer[0];
+      switch (option_type) {
+      case ND6_OPTION_TYPE_SOURCE_LLADDR:
+      {
+        struct lladdr_option *lladdr_opt;
+        if (option_len < sizeof(struct lladdr_option)) {
+          goto lenerr_drop_free_return;
+        }
+        lladdr_opt = (struct lladdr_option *)buffer;
+        if ((default_router_list[i].neighbor_entry != NULL) &&
+            (default_router_list[i].neighbor_entry->state == ND6_INCOMPLETE)) {
+          SMEMCPY(default_router_list[i].neighbor_entry->lladdr, lladdr_opt->addr, inp->hwaddr_len);
+          default_router_list[i].neighbor_entry->state = ND6_REACHABLE;
+          default_router_list[i].neighbor_entry->counter.reachable_time = reachable_time;
+        }
+        break;
+      }
+      case ND6_OPTION_TYPE_MTU:
+      {
+        struct mtu_option *mtu_opt;
+        u32_t mtu32;
+        if (option_len < sizeof(struct mtu_option)) {
+          goto lenerr_drop_free_return;
+        }
+        mtu_opt = (struct mtu_option *)buffer;
+        mtu32 = lwip_htonl(mtu_opt->mtu);
+        if ((mtu32 >= 1280) && (mtu32 <= 0xffff)) {
+#if LWIP_ND6_ALLOW_RA_UPDATES
+          if (inp->mtu) {
+            /* don't set the mtu for IPv6 higher than the netif driver supports */
+            inp->mtu6 = LWIP_MIN(inp->mtu, (u16_t)mtu32);
+          } else {
+            inp->mtu6 = (u16_t)mtu32;
+          }
+#endif /* LWIP_ND6_ALLOW_RA_UPDATES */
+        }
+        break;
+      }
+      case ND6_OPTION_TYPE_PREFIX_INFO:
+      {
+        struct prefix_option *prefix_opt;
+        ip6_addr_t prefix_addr;
+        if (option_len < sizeof(struct prefix_option)) {
+          goto lenerr_drop_free_return;
+        }
+
+        prefix_opt = (struct prefix_option *)buffer;
+
+        /* Get a memory-aligned copy of the prefix. */
+        ip6_addr_copy_from_packed(prefix_addr, prefix_opt->prefix);
+        ip6_addr_assign_zone(&prefix_addr, IP6_UNICAST, inp);
+
+        if (!ip6_addr_islinklocal(&prefix_addr)) {
+          if ((prefix_opt->flags & ND6_PREFIX_FLAG_ON_LINK) &&
+              (prefix_opt->prefix_length == 64)) {
+            /* Add to on-link prefix list. */
+            u32_t valid_life;
+            s8_t prefix;
+
+            valid_life = lwip_htonl(prefix_opt->valid_lifetime);
+
+            /* find cache entry for this prefix. */
+            prefix = nd6_get_onlink_prefix(&prefix_addr, inp);
+            if (prefix < 0 && valid_life > 0) {
+              /* Create a new cache entry. */
+              prefix = nd6_new_onlink_prefix(&prefix_addr, inp);
+            }
+            if (prefix >= 0) {
+              prefix_list[prefix].invalidation_timer = valid_life;
+            }
+          }
+#if LWIP_IPV6_AUTOCONFIG
+          if (prefix_opt->flags & ND6_PREFIX_FLAG_AUTONOMOUS) {
+            /* Perform processing for autoconfiguration. */
+            nd6_process_autoconfig_prefix(inp, prefix_opt, &prefix_addr);
+          }
+#endif /* LWIP_IPV6_AUTOCONFIG */
+        }
+
+        break;
+      }
+      case ND6_OPTION_TYPE_ROUTE_INFO:
+        /* @todo implement preferred routes.
+        struct route_option * route_opt;
+        route_opt = (struct route_option *)buffer;*/
+
+        break;
+#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS
+      case ND6_OPTION_TYPE_RDNSS:
+      {
+        u8_t num, n;
+        u16_t copy_offset = offset + SIZEOF_RDNSS_OPTION_BASE;
+        struct rdnss_option * rdnss_opt;
+        if (option_len < SIZEOF_RDNSS_OPTION_BASE) {
+          goto lenerr_drop_free_return;
+        }
+
+        rdnss_opt = (struct rdnss_option *)buffer;
+        num = (rdnss_opt->length - 1) / 2;
+        for (n = 0; (rdnss_server_idx < DNS_MAX_SERVERS) && (n < num); n++) {
+          ip_addr_t rdnss_address;
+
+          /* Copy directly from pbuf to get an aligned, zoned copy of the prefix. */
+          if (pbuf_copy_partial(p, &rdnss_address, sizeof(ip6_addr_p_t), copy_offset) == sizeof(ip6_addr_p_t)) {
+            IP_SET_TYPE_VAL(rdnss_address, IPADDR_TYPE_V6);
+            ip6_addr_assign_zone(ip_2_ip6(&rdnss_address), IP6_UNKNOWN, inp);
+
+            if (htonl(rdnss_opt->lifetime) > 0) {
+              /* TODO implement Lifetime > 0 */
+              dns_setserver(rdnss_server_idx++, &rdnss_address);
+            } else {
+              /* TODO implement DNS removal in dns.c */
+              u8_t s;
+              for (s = 0; s < DNS_MAX_SERVERS; s++) {
+                const ip_addr_t *addr = dns_getserver(s);
+                if(ip_addr_cmp(addr, &rdnss_address)) {
+                  dns_setserver(s, NULL);
+                }
+              }
+            }
+          }
+        }
+        break;
+      }
+#endif /* LWIP_ND6_RDNSS_MAX_DNS_SERVERS */
+      default:
+        /* Unrecognized option, abort. */
+        ND6_STATS_INC(nd6.proterr);
+        break;
+      }
+      /* option length is checked earlier to be non-zero to make sure loop ends */
+      offset += 8 * (u8_t)option_len8;
+    }
+
+    break; /* ICMP6_TYPE_RA */
+  }
+  case ICMP6_TYPE_RD: /* Redirect */
+  {
+    struct redirect_header *redir_hdr;
+    struct lladdr_option *lladdr_opt;
+    ip6_addr_t destination_address, target_address;
+
+    /* Check that Redir header fits in packet. */
+    if (p->len < sizeof(struct redirect_header)) {
+      /* @todo debug message */
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.lenerr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    redir_hdr = (struct redirect_header *)p->payload;
+
+    /* Create an aligned, zoned copy of the destination address. */
+    ip6_addr_copy_from_packed(destination_address, redir_hdr->destination_address);
+    ip6_addr_assign_zone(&destination_address, IP6_UNICAST, inp);
+
+    /* Check a subset of the other RFC 4861 Sec. 8.1 requirements. */
+    if (!ip6_addr_islinklocal(ip6_current_src_addr()) ||
+        IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM ||
+        redir_hdr->code != 0 || ip6_addr_ismulticast(&destination_address)) {
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.proterr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    /* @todo RFC MUST: IP source address equals first-hop router for destination_address */
+    /* @todo RFC MUST: ICMP target address is either link-local address or same as destination_address */
+    /* @todo RFC MUST: all included options have a length greater than zero */
+
+    if (p->len >= (sizeof(struct redirect_header) + 2)) {
+      lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct redirect_header));
+      if (p->len < (sizeof(struct redirect_header) + (lladdr_opt->length << 3))) {
+        lladdr_opt = NULL;
+      }
+    } else {
+      lladdr_opt = NULL;
+    }
+
+    /* Find dest address in cache */
+    dest_idx = nd6_find_destination_cache_entry(&destination_address);
+    if (dest_idx < 0) {
+      /* Destination not in cache, drop packet. */
+      pbuf_free(p);
+      return;
+    }
+
+    /* Create an aligned, zoned copy of the target address. */
+    ip6_addr_copy_from_packed(target_address, redir_hdr->target_address);
+    ip6_addr_assign_zone(&target_address, IP6_UNICAST, inp);
+
+    /* Set the new target address. */
+    ip6_addr_copy(destination_cache[dest_idx].next_hop_addr, target_address);
+
+    /* If Link-layer address of other router is given, try to add to neighbor cache. */
+    if (lladdr_opt != NULL) {
+      if (lladdr_opt->type == ND6_OPTION_TYPE_TARGET_LLADDR) {
+        i = nd6_find_neighbor_cache_entry(&target_address);
+        if (i < 0) {
+          i = nd6_new_neighbor_cache_entry();
+          if (i >= 0) {
+            neighbor_cache[i].netif = inp;
+            MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len);
+            ip6_addr_copy(neighbor_cache[i].next_hop_address, target_address);
+
+            /* Receiving a message does not prove reachability: only in one direction.
+             * Delay probe in case we get confirmation of reachability from upper layer (TCP). */
+            neighbor_cache[i].state = ND6_DELAY;
+            neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL;
+          }
+        }
+        if (i >= 0) {
+          if (neighbor_cache[i].state == ND6_INCOMPLETE) {
+            MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len);
+            /* Receiving a message does not prove reachability: only in one direction.
+             * Delay probe in case we get confirmation of reachability from upper layer (TCP). */
+            neighbor_cache[i].state = ND6_DELAY;
+            neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL;
+          }
+        }
+      }
+    }
+    break; /* ICMP6_TYPE_RD */
+  }
+  case ICMP6_TYPE_PTB: /* Packet too big */
+  {
+    struct icmp6_hdr *icmp6hdr; /* Packet too big message */
+    struct ip6_hdr *ip6hdr; /* IPv6 header of the packet which caused the error */
+    u32_t pmtu;
+    ip6_addr_t destination_address;
+
+    /* Check that ICMPv6 header + IPv6 header fit in payload */
+    if (p->len < (sizeof(struct icmp6_hdr) + IP6_HLEN)) {
+      /* drop short packets */
+      pbuf_free(p);
+      ND6_STATS_INC(nd6.lenerr);
+      ND6_STATS_INC(nd6.drop);
+      return;
+    }
+
+    icmp6hdr = (struct icmp6_hdr *)p->payload;
+    ip6hdr = (struct ip6_hdr *)((u8_t*)p->payload + sizeof(struct icmp6_hdr));
+
+    /* Create an aligned, zoned copy of the destination address. */
+    ip6_addr_copy_from_packed(destination_address, ip6hdr->dest);
+    ip6_addr_assign_zone(&destination_address, IP6_UNKNOWN, inp);
+
+    /* Look for entry in destination cache. */
+    dest_idx = nd6_find_destination_cache_entry(&destination_address);
+    if (dest_idx < 0) {
+      /* Destination not in cache, drop packet. */
+      pbuf_free(p);
+      return;
+    }
+
+    /* Change the Path MTU. */
+    pmtu = lwip_htonl(icmp6hdr->data);
+    destination_cache[dest_idx].pmtu = (u16_t)LWIP_MIN(pmtu, 0xFFFF);
+
+    break; /* ICMP6_TYPE_PTB */
+  }
+
+  default:
+    ND6_STATS_INC(nd6.proterr);
+    ND6_STATS_INC(nd6.drop);
+    break; /* default */
+  }
+
+  pbuf_free(p);
+  return;
+lenerr_drop_free_return:
+  ND6_STATS_INC(nd6.lenerr);
+  ND6_STATS_INC(nd6.drop);
+  pbuf_free(p);
+}
+
+
+/**
+ * Periodic timer for Neighbor discovery functions:
+ *
+ * - Update neighbor reachability states
+ * - Update destination cache entries age
+ * - Update invalidation timers of default routers and on-link prefixes
+ * - Update lifetimes of our addresses
+ * - Perform duplicate address detection (DAD) for our addresses
+ * - Send router solicitations
+ */
+void
+nd6_tmr(void)
+{
+  s8_t i;
+  struct netif *netif;
+
+  /* Process neighbor entries. */
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    switch (neighbor_cache[i].state) {
+    case ND6_INCOMPLETE:
+      if ((neighbor_cache[i].counter.probes_sent >= LWIP_ND6_MAX_MULTICAST_SOLICIT) &&
+          (!neighbor_cache[i].isrouter)) {
+        /* Retries exceeded. */
+        nd6_free_neighbor_cache_entry(i);
+      } else {
+        /* Send a NS for this entry. */
+        neighbor_cache[i].counter.probes_sent++;
+        nd6_send_neighbor_cache_probe(&neighbor_cache[i], ND6_SEND_FLAG_MULTICAST_DEST);
+      }
+      break;
+    case ND6_REACHABLE:
+      /* Send queued packets, if any are left. Should have been sent already. */
+      if (neighbor_cache[i].q != NULL) {
+        nd6_send_q(i);
+      }
+      if (neighbor_cache[i].counter.reachable_time <= ND6_TMR_INTERVAL) {
+        /* Change to stale state. */
+        neighbor_cache[i].state = ND6_STALE;
+        neighbor_cache[i].counter.stale_time = 0;
+      } else {
+        neighbor_cache[i].counter.reachable_time -= ND6_TMR_INTERVAL;
+      }
+      break;
+    case ND6_STALE:
+      neighbor_cache[i].counter.stale_time++;
+      break;
+    case ND6_DELAY:
+      if (neighbor_cache[i].counter.delay_time <= 1) {
+        /* Change to PROBE state. */
+        neighbor_cache[i].state = ND6_PROBE;
+        neighbor_cache[i].counter.probes_sent = 0;
+      } else {
+        neighbor_cache[i].counter.delay_time--;
+      }
+      break;
+    case ND6_PROBE:
+      if ((neighbor_cache[i].counter.probes_sent >= LWIP_ND6_MAX_MULTICAST_SOLICIT) &&
+          (!neighbor_cache[i].isrouter)) {
+        /* Retries exceeded. */
+        nd6_free_neighbor_cache_entry(i);
+      } else {
+        /* Send a NS for this entry. */
+        neighbor_cache[i].counter.probes_sent++;
+        nd6_send_neighbor_cache_probe(&neighbor_cache[i], 0);
+      }
+      break;
+    case ND6_NO_ENTRY:
+    default:
+      /* Do nothing. */
+      break;
+    }
+  }
+
+  /* Process destination entries. */
+  for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) {
+    destination_cache[i].age++;
+  }
+
+  /* Process router entries. */
+  for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) {
+    if (default_router_list[i].neighbor_entry != NULL) {
+      /* Active entry. */
+      if (default_router_list[i].invalidation_timer <= ND6_TMR_INTERVAL / 1000) {
+        /* No more than 1 second remaining. Clear this entry. Also clear any of
+         * its destination cache entries, as per RFC 4861 Sec. 5.3 and 6.3.5. */
+        s8_t j;
+        for (j = 0; j < LWIP_ND6_NUM_DESTINATIONS; j++) {
+          if (ip6_addr_cmp(&destination_cache[j].next_hop_addr,
+               &default_router_list[i].neighbor_entry->next_hop_address)) {
+             ip6_addr_set_any(&destination_cache[j].destination_addr);
+          }
+        }
+        default_router_list[i].neighbor_entry->isrouter = 0;
+        default_router_list[i].neighbor_entry = NULL;
+        default_router_list[i].invalidation_timer = 0;
+        default_router_list[i].flags = 0;
+      } else {
+        default_router_list[i].invalidation_timer -= ND6_TMR_INTERVAL / 1000;
+      }
+    }
+  }
+
+  /* Process prefix entries. */
+  for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) {
+    if (prefix_list[i].netif != NULL) {
+      if (prefix_list[i].invalidation_timer <= ND6_TMR_INTERVAL / 1000) {
+        /* Entry timed out, remove it */
+        prefix_list[i].invalidation_timer = 0;
+        prefix_list[i].netif = NULL;
+      } else {
+        prefix_list[i].invalidation_timer -= ND6_TMR_INTERVAL / 1000;
+      }
+    }
+  }
+
+  /* Process our own addresses, updating address lifetimes and/or DAD state. */
+  NETIF_FOREACH(netif) {
+    for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) {
+      u8_t addr_state;
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+      /* Step 1: update address lifetimes (valid and preferred). */
+      addr_state = netif_ip6_addr_state(netif, i);
+      /* RFC 4862 is not entirely clear as to whether address lifetimes affect
+       * tentative addresses, and is even less clear as to what should happen
+       * with duplicate addresses. We choose to track and update lifetimes for
+       * both those types, although for different reasons:
+       * - for tentative addresses, the line of thought of Sec. 5.7 combined
+       *   with the potentially long period that an address may be in tentative
+       *   state (due to the interface being down) suggests that lifetimes
+       *   should be independent of external factors which would include DAD;
+       * - for duplicate addresses, retiring them early could result in a new
+       *   but unwanted attempt at marking them as valid, while retiring them
+       *   late/never could clog up address slots on the netif.
+       * As a result, we may end up expiring addresses of either type here.
+       */
+      if (!ip6_addr_isinvalid(addr_state) &&
+          !netif_ip6_addr_isstatic(netif, i)) {
+        u32_t life = netif_ip6_addr_valid_life(netif, i);
+        if (life <= ND6_TMR_INTERVAL / 1000) {
+          /* The address has expired. */
+          netif_ip6_addr_set_valid_life(netif, i, 0);
+          netif_ip6_addr_set_pref_life(netif, i, 0);
+          netif_ip6_addr_set_state(netif, i, IP6_ADDR_INVALID);
+        } else {
+          if (!ip6_addr_life_isinfinite(life)) {
+            life -= ND6_TMR_INTERVAL / 1000;
+            LWIP_ASSERT("bad valid lifetime", life != IP6_ADDR_LIFE_STATIC);
+            netif_ip6_addr_set_valid_life(netif, i, life);
+          }
+          /* The address is still here. Update the preferred lifetime too. */
+          life = netif_ip6_addr_pref_life(netif, i);
+          if (life <= ND6_TMR_INTERVAL / 1000) {
+            /* This case must also trigger if 'life' was already zero, so as to
+             * deal correctly with advertised preferred-lifetime reductions. */
+            netif_ip6_addr_set_pref_life(netif, i, 0);
+            if (addr_state == IP6_ADDR_PREFERRED)
+              netif_ip6_addr_set_state(netif, i, IP6_ADDR_DEPRECATED);
+          } else if (!ip6_addr_life_isinfinite(life)) {
+            life -= ND6_TMR_INTERVAL / 1000;
+            netif_ip6_addr_set_pref_life(netif, i, life);
+          }
+        }
+      }
+      /* The address state may now have changed, so reobtain it next. */
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+      /* Step 2: update DAD state. */
+      addr_state = netif_ip6_addr_state(netif, i);
+      if (ip6_addr_istentative(addr_state)) {
+        if ((addr_state & IP6_ADDR_TENTATIVE_COUNT_MASK) >= LWIP_IPV6_DUP_DETECT_ATTEMPTS) {
+          /* No NA received in response. Mark address as valid. For dynamic
+           * addresses with an expired preferred lifetime, the state is set to
+           * deprecated right away. That should almost never happen, though. */
+          addr_state = IP6_ADDR_PREFERRED;
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+          if (!netif_ip6_addr_isstatic(netif, i) &&
+              netif_ip6_addr_pref_life(netif, i) == 0) {
+            addr_state = IP6_ADDR_DEPRECATED;
+          }
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+          netif_ip6_addr_set_state(netif, i, addr_state);
+        } else if (netif_is_up(netif) && netif_is_link_up(netif)) {
+          /* tentative: set next state by increasing by one */
+          netif_ip6_addr_set_state(netif, i, addr_state + 1);
+          /* Send a NS for this address. Use the unspecified address as source
+           * address in all cases (RFC 4862 Sec. 5.4.2), not in the least
+           * because as it is, we only consider multicast replies for DAD. */
+          nd6_send_ns(netif, netif_ip6_addr(netif, i),
+            ND6_SEND_FLAG_MULTICAST_DEST | ND6_SEND_FLAG_ANY_SRC);
+        }
+      }
+    }
+  }
+
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+  /* Send router solicitation messages, if necessary. */
+  if (!nd6_tmr_rs_reduction) {
+    nd6_tmr_rs_reduction = (ND6_RTR_SOLICITATION_INTERVAL / ND6_TMR_INTERVAL) - 1;
+    NETIF_FOREACH(netif) {
+      if ((netif->rs_count > 0) && netif_is_up(netif) &&
+          netif_is_link_up(netif) &&
+          !ip6_addr_isinvalid(netif_ip6_addr_state(netif, 0)) &&
+          !ip6_addr_isduplicated(netif_ip6_addr_state(netif, 0))) {
+        if (nd6_send_rs(netif) == ERR_OK) {
+          netif->rs_count--;
+        }
+      }
+    }
+  } else {
+    nd6_tmr_rs_reduction--;
+  }
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+
+}
+
+/** Send a neighbor solicitation message for a specific neighbor cache entry
+ *
+ * @param entry the neightbor cache entry for wich to send the message
+ * @param flags one of ND6_SEND_FLAG_*
+ */
+static void
+nd6_send_neighbor_cache_probe(struct nd6_neighbor_cache_entry *entry, u8_t flags)
+{
+  nd6_send_ns(entry->netif, &entry->next_hop_address, flags);
+}
+
+/**
+ * Send a neighbor solicitation message
+ *
+ * @param netif the netif on which to send the message
+ * @param target_addr the IPv6 target address for the ND message
+ * @param flags one of ND6_SEND_FLAG_*
+ */
+static void
+nd6_send_ns(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags)
+{
+  struct ns_header *ns_hdr;
+  struct pbuf *p;
+  const ip6_addr_t *src_addr;
+  u16_t lladdr_opt_len;
+
+  LWIP_ASSERT("target address is required", target_addr != NULL);
+
+  if (!(flags & ND6_SEND_FLAG_ANY_SRC) &&
+      ip6_addr_isvalid(netif_ip6_addr_state(netif,0))) {
+    /* Use link-local address as source address. */
+    src_addr = netif_ip6_addr(netif, 0);
+    /* calculate option length (in 8-byte-blocks) */
+    lladdr_opt_len = ((netif->hwaddr_len + 2) + 7) >> 3;
+  } else {
+    src_addr = IP6_ADDR_ANY6;
+    /* Option "MUST NOT be included when the source IP address is the unspecified address." */
+    lladdr_opt_len = 0;
+  }
+
+  /* Allocate a packet. */
+  p = pbuf_alloc(PBUF_IP, sizeof(struct ns_header) + (lladdr_opt_len << 3), PBUF_RAM);
+  if (p == NULL) {
+    ND6_STATS_INC(nd6.memerr);
+    return;
+  }
+
+  /* Set fields. */
+  ns_hdr = (struct ns_header *)p->payload;
+
+  ns_hdr->type = ICMP6_TYPE_NS;
+  ns_hdr->code = 0;
+  ns_hdr->chksum = 0;
+  ns_hdr->reserved = 0;
+  ip6_addr_copy_to_packed(ns_hdr->target_address, *target_addr);
+
+  if (lladdr_opt_len != 0) {
+    struct lladdr_option *lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct ns_header));
+    lladdr_opt->type = ND6_OPTION_TYPE_SOURCE_LLADDR;
+    lladdr_opt->length = (u8_t)lladdr_opt_len;
+    SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len);
+  }
+
+  /* Generate the solicited node address for the target address. */
+  if (flags & ND6_SEND_FLAG_MULTICAST_DEST) {
+    ip6_addr_set_solicitednode(&multicast_address, target_addr->addr[3]);
+    ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif);
+    target_addr = &multicast_address;
+  }
+
+#if CHECKSUM_GEN_ICMP6
+  IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) {
+    ns_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr,
+      target_addr);
+  }
+#endif /* CHECKSUM_GEN_ICMP6 */
+
+  /* Send the packet out. */
+  ND6_STATS_INC(nd6.xmit);
+  ip6_output_if(p, (src_addr == IP6_ADDR_ANY6) ? NULL : src_addr, target_addr,
+      ND6_HOPLIM, 0, IP6_NEXTH_ICMP6, netif);
+  pbuf_free(p);
+}
+
+/**
+ * Send a neighbor advertisement message
+ *
+ * @param netif the netif on which to send the message
+ * @param target_addr the IPv6 target address for the ND message
+ * @param flags one of ND6_SEND_FLAG_*
+ */
+static void
+nd6_send_na(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags)
+{
+  struct na_header *na_hdr;
+  struct lladdr_option *lladdr_opt;
+  struct pbuf *p;
+  const ip6_addr_t *src_addr;
+  const ip6_addr_t *dest_addr;
+  u16_t lladdr_opt_len;
+
+  LWIP_ASSERT("target address is required", target_addr != NULL);
+
+  /* Use link-local address as source address. */
+  /* src_addr = netif_ip6_addr(netif, 0); */
+  /* Use target address as source address. */
+  src_addr = target_addr;
+
+  /* Allocate a packet. */
+  lladdr_opt_len = ((netif->hwaddr_len + 2) >> 3) + (((netif->hwaddr_len + 2) & 0x07) ? 1 : 0);
+  p = pbuf_alloc(PBUF_IP, sizeof(struct na_header) + (lladdr_opt_len << 3), PBUF_RAM);
+  if (p == NULL) {
+    ND6_STATS_INC(nd6.memerr);
+    return;
+  }
+
+  /* Set fields. */
+  na_hdr = (struct na_header *)p->payload;
+  lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header));
+
+  na_hdr->type = ICMP6_TYPE_NA;
+  na_hdr->code = 0;
+  na_hdr->chksum = 0;
+  na_hdr->flags = flags & 0xf0;
+  na_hdr->reserved[0] = 0;
+  na_hdr->reserved[1] = 0;
+  na_hdr->reserved[2] = 0;
+  ip6_addr_copy_to_packed(na_hdr->target_address, *target_addr);
+
+  lladdr_opt->type = ND6_OPTION_TYPE_TARGET_LLADDR;
+  lladdr_opt->length = (u8_t)lladdr_opt_len;
+  SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len);
+
+  /* Generate the solicited node address for the target address. */
+  if (flags & ND6_SEND_FLAG_MULTICAST_DEST) {
+    ip6_addr_set_solicitednode(&multicast_address, target_addr->addr[3]);
+    ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif);
+    dest_addr = &multicast_address;
+  } else if (flags & ND6_SEND_FLAG_ALLNODES_DEST) {
+    ip6_addr_set_allnodes_linklocal(&multicast_address);
+    ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif);
+    dest_addr = &multicast_address;
+  } else {
+    dest_addr = ip6_current_src_addr();
+  }
+
+#if CHECKSUM_GEN_ICMP6
+  IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) {
+    na_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr,
+      dest_addr);
+  }
+#endif /* CHECKSUM_GEN_ICMP6 */
+
+  /* Send the packet out. */
+  ND6_STATS_INC(nd6.xmit);
+  ip6_output_if(p, src_addr, dest_addr,
+      ND6_HOPLIM, 0, IP6_NEXTH_ICMP6, netif);
+  pbuf_free(p);
+}
+
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+/**
+ * Send a router solicitation message
+ *
+ * @param netif the netif on which to send the message
+ */
+static err_t
+nd6_send_rs(struct netif *netif)
+{
+  struct rs_header *rs_hdr;
+  struct lladdr_option *lladdr_opt;
+  struct pbuf *p;
+  const ip6_addr_t *src_addr;
+  err_t err;
+  u16_t lladdr_opt_len = 0;
+
+  /* Link-local source address, or unspecified address? */
+  if (ip6_addr_isvalid(netif_ip6_addr_state(netif, 0))) {
+    src_addr = netif_ip6_addr(netif, 0);
+  } else {
+    src_addr = IP6_ADDR_ANY6;
+  }
+
+  /* Generate the all routers target address. */
+  ip6_addr_set_allrouters_linklocal(&multicast_address);
+  ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif);
+
+  /* Allocate a packet. */
+  if (src_addr != IP6_ADDR_ANY6) {
+    lladdr_opt_len = ((netif->hwaddr_len + 2) >> 3) + (((netif->hwaddr_len + 2) & 0x07) ? 1 : 0);
+  }
+  p = pbuf_alloc(PBUF_IP, sizeof(struct rs_header) + (lladdr_opt_len << 3), PBUF_RAM);
+  if (p == NULL) {
+    ND6_STATS_INC(nd6.memerr);
+    return ERR_BUF;
+  }
+
+  /* Set fields. */
+  rs_hdr = (struct rs_header *)p->payload;
+
+  rs_hdr->type = ICMP6_TYPE_RS;
+  rs_hdr->code = 0;
+  rs_hdr->chksum = 0;
+  rs_hdr->reserved = 0;
+
+  if (src_addr != IP6_ADDR_ANY6) {
+    /* Include our hw address. */
+    lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct rs_header));
+    lladdr_opt->type = ND6_OPTION_TYPE_SOURCE_LLADDR;
+    lladdr_opt->length = (u8_t)lladdr_opt_len;
+    SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len);
+  }
+
+#if CHECKSUM_GEN_ICMP6
+  IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) {
+    rs_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr,
+      &multicast_address);
+  }
+#endif /* CHECKSUM_GEN_ICMP6 */
+
+  /* Send the packet out. */
+  ND6_STATS_INC(nd6.xmit);
+
+  err = ip6_output_if(p, (src_addr == IP6_ADDR_ANY6) ? NULL : src_addr, &multicast_address,
+      ND6_HOPLIM, 0, IP6_NEXTH_ICMP6, netif);
+  pbuf_free(p);
+
+  return err;
+}
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+
+/**
+ * Search for a neighbor cache entry
+ *
+ * @param ip6addr the IPv6 address of the neighbor
+ * @return The neighbor cache entry index that matched, -1 if no
+ * entry is found
+ */
+static s8_t
+nd6_find_neighbor_cache_entry(const ip6_addr_t *ip6addr)
+{
+  s8_t i;
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if (ip6_addr_cmp(ip6addr, &(neighbor_cache[i].next_hop_address))) {
+      return i;
+    }
+  }
+  return -1;
+}
+
+/**
+ * Create a new neighbor cache entry.
+ *
+ * If no unused entry is found, will try to recycle an old entry
+ * according to ad-hoc "age" heuristic.
+ *
+ * @return The neighbor cache entry index that was created, -1 if no
+ * entry could be created
+ */
+static s8_t
+nd6_new_neighbor_cache_entry(void)
+{
+  s8_t i;
+  s8_t j;
+  u32_t time;
+
+
+  /* First, try to find an empty entry. */
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if (neighbor_cache[i].state == ND6_NO_ENTRY) {
+      return i;
+    }
+  }
+
+  /* We need to recycle an entry. in general, do not recycle if it is a router. */
+
+  /* Next, try to find a Stale entry. */
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if ((neighbor_cache[i].state == ND6_STALE) &&
+        (!neighbor_cache[i].isrouter)) {
+      nd6_free_neighbor_cache_entry(i);
+      return i;
+    }
+  }
+
+  /* Next, try to find a Probe entry. */
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if ((neighbor_cache[i].state == ND6_PROBE) &&
+        (!neighbor_cache[i].isrouter)) {
+      nd6_free_neighbor_cache_entry(i);
+      return i;
+    }
+  }
+
+  /* Next, try to find a Delayed entry. */
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if ((neighbor_cache[i].state == ND6_DELAY) &&
+        (!neighbor_cache[i].isrouter)) {
+      nd6_free_neighbor_cache_entry(i);
+      return i;
+    }
+  }
+
+  /* Next, try to find the oldest reachable entry. */
+  time = 0xfffffffful;
+  j = -1;
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if ((neighbor_cache[i].state == ND6_REACHABLE) &&
+        (!neighbor_cache[i].isrouter)) {
+      if (neighbor_cache[i].counter.reachable_time < time) {
+        j = i;
+        time = neighbor_cache[i].counter.reachable_time;
+      }
+    }
+  }
+  if (j >= 0) {
+    nd6_free_neighbor_cache_entry(j);
+    return j;
+  }
+
+  /* Next, find oldest incomplete entry without queued packets. */
+  time = 0;
+  j = -1;
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if (
+        (neighbor_cache[i].q == NULL) &&
+        (neighbor_cache[i].state == ND6_INCOMPLETE) &&
+        (!neighbor_cache[i].isrouter)) {
+      if (neighbor_cache[i].counter.probes_sent >= time) {
+        j = i;
+        time = neighbor_cache[i].counter.probes_sent;
+      }
+    }
+  }
+  if (j >= 0) {
+    nd6_free_neighbor_cache_entry(j);
+    return j;
+  }
+
+  /* Next, find oldest incomplete entry with queued packets. */
+  time = 0;
+  j = -1;
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if ((neighbor_cache[i].state == ND6_INCOMPLETE) &&
+        (!neighbor_cache[i].isrouter)) {
+      if (neighbor_cache[i].counter.probes_sent >= time) {
+        j = i;
+        time = neighbor_cache[i].counter.probes_sent;
+      }
+    }
+  }
+  if (j >= 0) {
+    nd6_free_neighbor_cache_entry(j);
+    return j;
+  }
+
+  /* No more entries to try. */
+  return -1;
+}
+
+/**
+ * Will free any resources associated with a neighbor cache
+ * entry, and will mark it as unused.
+ *
+ * @param i the neighbor cache entry index to free
+ */
+static void
+nd6_free_neighbor_cache_entry(s8_t i)
+{
+  if ((i < 0) || (i >= LWIP_ND6_NUM_NEIGHBORS)) {
+    return;
+  }
+  if (neighbor_cache[i].isrouter) {
+    /* isrouter needs to be cleared before deleting a neighbor cache entry */
+    return;
+  }
+
+  /* Free any queued packets. */
+  if (neighbor_cache[i].q != NULL) {
+    nd6_free_q(neighbor_cache[i].q);
+    neighbor_cache[i].q = NULL;
+  }
+
+  neighbor_cache[i].state = ND6_NO_ENTRY;
+  neighbor_cache[i].isrouter = 0;
+  neighbor_cache[i].netif = NULL;
+  neighbor_cache[i].counter.reachable_time = 0;
+  ip6_addr_set_zero(&(neighbor_cache[i].next_hop_address));
+}
+
+/**
+ * Search for a destination cache entry
+ *
+ * @param ip6addr the IPv6 address of the destination
+ * @return The destination cache entry index that matched, -1 if no
+ * entry is found
+ */
+static s16_t
+nd6_find_destination_cache_entry(const ip6_addr_t *ip6addr)
+{
+  s16_t i;
+
+  IP6_ADDR_ZONECHECK(ip6addr);
+
+  for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) {
+    if (ip6_addr_cmp(ip6addr, &(destination_cache[i].destination_addr))) {
+      return i;
+    }
+  }
+  return -1;
+}
+
+/**
+ * Create a new destination cache entry. If no unused entry is found,
+ * will recycle oldest entry.
+ *
+ * @return The destination cache entry index that was created, -1 if no
+ * entry was created
+ */
+static s16_t
+nd6_new_destination_cache_entry(void)
+{
+  s16_t i, j;
+  u32_t age;
+
+  /* Find an empty entry. */
+  for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) {
+    if (ip6_addr_isany(&(destination_cache[i].destination_addr))) {
+      return i;
+    }
+  }
+
+  /* Find oldest entry. */
+  age = 0;
+  j = LWIP_ND6_NUM_DESTINATIONS - 1;
+  for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) {
+    if (destination_cache[i].age > age) {
+      j = i;
+    }
+  }
+
+  return j;
+}
+
+/**
+ * Clear the destination cache.
+ *
+ * This operation may be necessary for consistency in the light of changing
+ * local addresses and/or use of the gateway hook.
+ */
+void
+nd6_clear_destination_cache(void)
+{
+  int i;
+
+  for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) {
+    ip6_addr_set_any(&destination_cache[i].destination_addr);
+  }
+}
+
+/**
+ * Determine whether an address matches an on-link prefix or the subnet of a
+ * statically assigned address.
+ *
+ * @param ip6addr the IPv6 address to match
+ * @return 1 if the address is on-link, 0 otherwise
+ */
+static int
+nd6_is_prefix_in_netif(const ip6_addr_t *ip6addr, struct netif *netif)
+{
+  s8_t i;
+
+  /* Check to see if the address matches an on-link prefix. */
+  for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) {
+    if ((prefix_list[i].netif == netif) &&
+        (prefix_list[i].invalidation_timer > 0) &&
+        ip6_addr_netcmp(ip6addr, &(prefix_list[i].prefix))) {
+      return 1;
+    }
+  }
+  /* Check to see if address prefix matches a manually configured (= static)
+   * address. Static addresses have an implied /64 subnet assignment. Dynamic
+   * addresses (from autoconfiguration) have no implied subnet assignment, and
+   * are thus effectively /128 assignments. See RFC 5942 for more on this. */
+  for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) &&
+        netif_ip6_addr_isstatic(netif, i) &&
+        ip6_addr_netcmp(ip6addr, netif_ip6_addr(netif, i))) {
+      return 1;
+    }
+  }
+  return 0;
+}
+
+/**
+ * Select a default router for a destination.
+ *
+ * This function is used both for routing and for finding a next-hop target for
+ * a packet. In the former case, the given netif is NULL, and the returned
+ * router entry must be for a netif suitable for sending packets (up, link up).
+ * In the latter case, the given netif is not NULL and restricts router choice.
+ *
+ * @param ip6addr the destination address
+ * @param netif the netif for the outgoing packet, if known
+ * @return the default router entry index, or -1 if no suitable
+ *         router is found
+ */
+static s8_t
+nd6_select_router(const ip6_addr_t *ip6addr, struct netif *netif)
+{
+  struct netif *router_netif;
+  s8_t i, j, valid_router;
+  static s8_t last_router;
+
+  LWIP_UNUSED_ARG(ip6addr); /* @todo match preferred routes!! (must implement ND6_OPTION_TYPE_ROUTE_INFO) */
+
+  /* @todo: implement default router preference */
+
+  /* Look for valid routers. A reachable router is preferred. */
+  valid_router = -1;
+  for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) {
+    /* Is the router netif both set and apppropriate? */
+    if (default_router_list[i].neighbor_entry != NULL) {
+      router_netif = default_router_list[i].neighbor_entry->netif;
+      if ((router_netif != NULL) && (netif != NULL ? netif == router_netif :
+          (netif_is_up(router_netif) && netif_is_link_up(router_netif)))) {
+        /* Is the router valid, i.e., reachable or probably reachable as per
+         * RFC 4861 Sec. 6.3.6? Note that we will never return a router that
+         * has no neighbor cache entry, due to the netif association tests. */
+        if (default_router_list[i].neighbor_entry->state != ND6_INCOMPLETE) {
+          /* Is the router known to be reachable? */
+          if (default_router_list[i].neighbor_entry->state == ND6_REACHABLE) {
+            return i; /* valid and reachable - done! */
+          } else if (valid_router < 0) {
+            valid_router = i; /* valid but not known to be reachable */
+          }
+        }
+      }
+    }
+  }
+  if (valid_router >= 0) {
+    return valid_router;
+  }
+
+  /* Look for any router for which we have any information at all. */
+  /* last_router is used for round-robin selection of incomplete routers, as
+   * recommended in RFC 4861 Sec. 6.3.6 point (2). Advance only when picking a
+   * route, to select the same router as next-hop target in the common case. */
+  if ((netif == NULL) && (++last_router >= LWIP_ND6_NUM_ROUTERS)) {
+    last_router = 0;
+  }
+  i = last_router;
+  for (j = 0; j < LWIP_ND6_NUM_ROUTERS; j++) {
+    if (default_router_list[i].neighbor_entry != NULL) {
+      router_netif = default_router_list[i].neighbor_entry->netif;
+      if ((router_netif != NULL) && (netif != NULL ? netif == router_netif :
+          (netif_is_up(router_netif) && netif_is_link_up(router_netif)))) {
+        return i;
+      }
+    }
+    if (++i >= LWIP_ND6_NUM_ROUTERS) {
+      i = 0;
+    }
+  }
+
+  /* no suitable router found. */
+  return -1;
+}
+
+/**
+ * Find a router-announced route to the given destination. This route may be
+ * based on an on-link prefix or a default router.
+ *
+ * If a suitable route is found, the returned netif is guaranteed to be in a
+ * suitable state (up, link up) to be used for packet transmission.
+ *
+ * @param ip6addr the destination IPv6 address
+ * @return the netif to use for the destination, or NULL if none found
+ */
+struct netif *
+nd6_find_route(const ip6_addr_t *ip6addr)
+{
+  struct netif *netif;
+  s8_t i;
+
+  /* @todo decide if it makes sense to check the destination cache first */
+
+  /* Check if there is a matching on-link prefix. There may be multiple
+   * matches. Pick the first one that is associated with a suitable netif. */
+  for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) {
+    netif = prefix_list[i].netif;
+    if ((netif != NULL) && ip6_addr_netcmp(&prefix_list[i].prefix, ip6addr) &&
+        netif_is_up(netif) && netif_is_link_up(netif)) {
+      return netif;
+    }
+  }
+
+  /* No on-link prefix match. Find a router that can forward the packet. */
+  i = nd6_select_router(ip6addr, NULL);
+  if (i >= 0) {
+    LWIP_ASSERT("selected router must have a neighbor entry",
+      default_router_list[i].neighbor_entry != NULL);
+    return default_router_list[i].neighbor_entry->netif;
+  }
+
+  return NULL;
+}
+
+/**
+ * Find an entry for a default router.
+ *
+ * @param router_addr the IPv6 address of the router
+ * @param netif the netif on which the router is found, if known
+ * @return the index of the router entry, or -1 if not found
+ */
+static s8_t
+nd6_get_router(const ip6_addr_t *router_addr, struct netif *netif)
+{
+  s8_t i;
+
+  IP6_ADDR_ZONECHECK_NETIF(router_addr, netif);
+
+  /* Look for router. */
+  for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) {
+    if ((default_router_list[i].neighbor_entry != NULL) &&
+        ((netif != NULL) ? netif == default_router_list[i].neighbor_entry->netif : 1) &&
+        ip6_addr_cmp(router_addr, &(default_router_list[i].neighbor_entry->next_hop_address))) {
+      return i;
+    }
+  }
+
+  /* router not found. */
+  return -1;
+}
+
+/**
+ * Create a new entry for a default router.
+ *
+ * @param router_addr the IPv6 address of the router
+ * @param netif the netif on which the router is connected, if known
+ * @return the index on the router table, or -1 if could not be created
+ */
+static s8_t
+nd6_new_router(const ip6_addr_t *router_addr, struct netif *netif)
+{
+  s8_t router_index;
+  s8_t free_router_index;
+  s8_t neighbor_index;
+
+  IP6_ADDR_ZONECHECK_NETIF(router_addr, netif);
+
+  /* Do we have a neighbor entry for this router? */
+  neighbor_index = nd6_find_neighbor_cache_entry(router_addr);
+  if (neighbor_index < 0) {
+    /* Create a neighbor entry for this router. */
+    neighbor_index = nd6_new_neighbor_cache_entry();
+    if (neighbor_index < 0) {
+      /* Could not create neighbor entry for this router. */
+      return -1;
+    }
+    ip6_addr_set(&(neighbor_cache[neighbor_index].next_hop_address), router_addr);
+    neighbor_cache[neighbor_index].netif = netif;
+    neighbor_cache[neighbor_index].q = NULL;
+    neighbor_cache[neighbor_index].state = ND6_INCOMPLETE;
+    neighbor_cache[neighbor_index].counter.probes_sent = 1;
+    nd6_send_neighbor_cache_probe(&neighbor_cache[neighbor_index], ND6_SEND_FLAG_MULTICAST_DEST);
+  }
+
+  /* Mark neighbor as router. */
+  neighbor_cache[neighbor_index].isrouter = 1;
+
+  /* Look for empty entry. */
+  free_router_index = LWIP_ND6_NUM_ROUTERS;
+  for (router_index = LWIP_ND6_NUM_ROUTERS - 1; router_index >= 0; router_index--) {
+    /* check if router already exists (this is a special case for 2 netifs on the same subnet
+       - e.g. wifi and cable) */
+    if(default_router_list[router_index].neighbor_entry == &(neighbor_cache[neighbor_index])){ 
+      return router_index; 
+    } 
+    if (default_router_list[router_index].neighbor_entry == NULL) {
+      /* remember lowest free index to create a new entry */
+      free_router_index = router_index;
+    }
+  }
+  if (free_router_index < LWIP_ND6_NUM_ROUTERS) {
+    default_router_list[free_router_index].neighbor_entry = &(neighbor_cache[neighbor_index]);
+    return free_router_index;
+  }
+
+  /* Could not create a router entry. */
+
+  /* Mark neighbor entry as not-router. Entry might be useful as neighbor still. */
+  neighbor_cache[neighbor_index].isrouter = 0;
+
+  /* router not found. */
+  return -1;
+}
+
+/**
+ * Find the cached entry for an on-link prefix.
+ *
+ * @param prefix the IPv6 prefix that is on-link
+ * @param netif the netif on which the prefix is on-link
+ * @return the index on the prefix table, or -1 if not found
+ */
+static s8_t
+nd6_get_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif)
+{
+  s8_t i;
+
+  /* Look for prefix in list. */
+  for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) {
+    if ((ip6_addr_netcmp(&(prefix_list[i].prefix), prefix)) &&
+        (prefix_list[i].netif == netif)) {
+      return i;
+    }
+  }
+
+  /* Entry not available. */
+  return -1;
+}
+
+/**
+ * Creates a new entry for an on-link prefix.
+ *
+ * @param prefix the IPv6 prefix that is on-link
+ * @param netif the netif on which the prefix is on-link
+ * @return the index on the prefix table, or -1 if not created
+ */
+static s8_t
+nd6_new_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif)
+{
+  s8_t i;
+
+  /* Create new entry. */
+  for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) {
+    if ((prefix_list[i].netif == NULL) ||
+        (prefix_list[i].invalidation_timer == 0)) {
+      /* Found empty prefix entry. */
+      prefix_list[i].netif = netif;
+      ip6_addr_set(&(prefix_list[i].prefix), prefix);
+      return i;
+    }
+  }
+
+  /* Entry not available. */
+  return -1;
+}
+
+/**
+ * Determine the next hop for a destination. Will determine if the
+ * destination is on-link, else a suitable on-link router is selected.
+ *
+ * The last entry index is cached for fast entry search.
+ *
+ * @param ip6addr the destination address
+ * @param netif the netif on which the packet will be sent
+ * @return the neighbor cache entry for the next hop, ERR_RTE if no
+ *         suitable next hop was found, ERR_MEM if no cache entry
+ *         could be created
+ */
+static s8_t
+nd6_get_next_hop_entry(const ip6_addr_t *ip6addr, struct netif *netif)
+{
+#ifdef LWIP_HOOK_ND6_GET_GW
+  const ip6_addr_t *next_hop_addr;
+#endif /* LWIP_HOOK_ND6_GET_GW */
+  s8_t i;
+  s16_t dst_idx;
+
+  IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif);
+
+#if LWIP_NETIF_HWADDRHINT
+  if (netif->hints != NULL) {
+    /* per-pcb cached entry was given */
+    netif_addr_idx_t addr_hint = netif->hints->addr_hint;
+    if (addr_hint < LWIP_ND6_NUM_DESTINATIONS) {
+      nd6_cached_destination_index = addr_hint;
+    }
+  }
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+  /* Look for ip6addr in destination cache. */
+  if (ip6_addr_cmp(ip6addr, &(destination_cache[nd6_cached_destination_index].destination_addr))) {
+    /* the cached entry index is the right one! */
+    /* do nothing. */
+    ND6_STATS_INC(nd6.cachehit);
+  } else {
+    /* Search destination cache. */
+    dst_idx = nd6_find_destination_cache_entry(ip6addr);
+    if (dst_idx >= 0) {
+      /* found destination entry. make it our new cached index. */
+      LWIP_ASSERT("type overflow", (size_t)dst_idx < NETIF_ADDR_IDX_MAX);
+      nd6_cached_destination_index = (netif_addr_idx_t)dst_idx;
+    } else {
+      /* Not found. Create a new destination entry. */
+      dst_idx = nd6_new_destination_cache_entry();
+      if (dst_idx >= 0) {
+        /* got new destination entry. make it our new cached index. */
+        LWIP_ASSERT("type overflow", (size_t)dst_idx < NETIF_ADDR_IDX_MAX);
+        nd6_cached_destination_index = (netif_addr_idx_t)dst_idx;
+      } else {
+        /* Could not create a destination cache entry. */
+        return ERR_MEM;
+      }
+
+      /* Copy dest address to destination cache. */
+      ip6_addr_set(&(destination_cache[nd6_cached_destination_index].destination_addr), ip6addr);
+
+      /* Now find the next hop. is it a neighbor? */
+      if (ip6_addr_islinklocal(ip6addr) ||
+          nd6_is_prefix_in_netif(ip6addr, netif)) {
+        /* Destination in local link. */
+        destination_cache[nd6_cached_destination_index].pmtu = netif_mtu6(netif);
+        ip6_addr_copy(destination_cache[nd6_cached_destination_index].next_hop_addr, destination_cache[nd6_cached_destination_index].destination_addr);
+#ifdef LWIP_HOOK_ND6_GET_GW
+      } else if ((next_hop_addr = LWIP_HOOK_ND6_GET_GW(netif, ip6addr)) != NULL) {
+        /* Next hop for destination provided by hook function. */
+        destination_cache[nd6_cached_destination_index].pmtu = netif->mtu;
+        ip6_addr_set(&destination_cache[nd6_cached_destination_index].next_hop_addr, next_hop_addr);
+#endif /* LWIP_HOOK_ND6_GET_GW */
+      } else {
+        /* We need to select a router. */
+        i = nd6_select_router(ip6addr, netif);
+        if (i < 0) {
+          /* No router found. */
+          ip6_addr_set_any(&(destination_cache[nd6_cached_destination_index].destination_addr));
+          return ERR_RTE;
+        }
+        destination_cache[nd6_cached_destination_index].pmtu = netif_mtu6(netif); /* Start with netif mtu, correct through ICMPv6 if necessary */
+        ip6_addr_copy(destination_cache[nd6_cached_destination_index].next_hop_addr, default_router_list[i].neighbor_entry->next_hop_address);
+      }
+    }
+  }
+
+#if LWIP_NETIF_HWADDRHINT
+  if (netif->hints != NULL) {
+    /* per-pcb cached entry was given */
+    netif->hints->addr_hint = nd6_cached_destination_index;
+  }
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+  /* Look in neighbor cache for the next-hop address. */
+  if (ip6_addr_cmp(&(destination_cache[nd6_cached_destination_index].next_hop_addr),
+                   &(neighbor_cache[nd6_cached_neighbor_index].next_hop_address))) {
+    /* Cache hit. */
+    /* Do nothing. */
+    ND6_STATS_INC(nd6.cachehit);
+  } else {
+    i = nd6_find_neighbor_cache_entry(&(destination_cache[nd6_cached_destination_index].next_hop_addr));
+    if (i >= 0) {
+      /* Found a matching record, make it new cached entry. */
+      nd6_cached_neighbor_index = i;
+    } else {
+      /* Neighbor not in cache. Make a new entry. */
+      i = nd6_new_neighbor_cache_entry();
+      if (i >= 0) {
+        /* got new neighbor entry. make it our new cached index. */
+        nd6_cached_neighbor_index = i;
+      } else {
+        /* Could not create a neighbor cache entry. */
+        return ERR_MEM;
+      }
+
+      /* Initialize fields. */
+      ip6_addr_copy(neighbor_cache[i].next_hop_address,
+                   destination_cache[nd6_cached_destination_index].next_hop_addr);
+      neighbor_cache[i].isrouter = 0;
+      neighbor_cache[i].netif = netif;
+      neighbor_cache[i].state = ND6_INCOMPLETE;
+      neighbor_cache[i].counter.probes_sent = 1;
+      nd6_send_neighbor_cache_probe(&neighbor_cache[i], ND6_SEND_FLAG_MULTICAST_DEST);
+    }
+  }
+
+  /* Reset this destination's age. */
+  destination_cache[nd6_cached_destination_index].age = 0;
+
+  return nd6_cached_neighbor_index;
+}
+
+/**
+ * Queue a packet for a neighbor.
+ *
+ * @param neighbor_index the index in the neighbor cache table
+ * @param q packet to be queued
+ * @return ERR_OK if succeeded, ERR_MEM if out of memory
+ */
+static err_t
+nd6_queue_packet(s8_t neighbor_index, struct pbuf *q)
+{
+  err_t result = ERR_MEM;
+  struct pbuf *p;
+  int copy_needed = 0;
+#if LWIP_ND6_QUEUEING
+  struct nd6_q_entry *new_entry, *r;
+#endif /* LWIP_ND6_QUEUEING */
+
+  if ((neighbor_index < 0) || (neighbor_index >= LWIP_ND6_NUM_NEIGHBORS)) {
+    return ERR_ARG;
+  }
+
+  /* IF q includes a pbuf that must be copied, we have to copy the whole chain
+   * into a new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
+  p = q;
+  while (p) {
+    if (PBUF_NEEDS_COPY(p)) {
+      copy_needed = 1;
+      break;
+    }
+    p = p->next;
+  }
+  if (copy_needed) {
+    /* copy the whole packet into new pbufs */
+    p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
+    while ((p == NULL) && (neighbor_cache[neighbor_index].q != NULL)) {
+      /* Free oldest packet (as per RFC recommendation) */
+#if LWIP_ND6_QUEUEING
+      r = neighbor_cache[neighbor_index].q;
+      neighbor_cache[neighbor_index].q = r->next;
+      r->next = NULL;
+      nd6_free_q(r);
+#else /* LWIP_ND6_QUEUEING */
+      pbuf_free(neighbor_cache[neighbor_index].q);
+      neighbor_cache[neighbor_index].q = NULL;
+#endif /* LWIP_ND6_QUEUEING */
+      p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
+    }
+  } else {
+    /* referencing the old pbuf is enough */
+    p = q;
+    pbuf_ref(p);
+  }
+  /* packet was copied/ref'd? */
+  if (p != NULL) {
+    /* queue packet ... */
+#if LWIP_ND6_QUEUEING
+    /* allocate a new nd6 queue entry */
+    new_entry = (struct nd6_q_entry *)memp_malloc(MEMP_ND6_QUEUE);
+    if ((new_entry == NULL) && (neighbor_cache[neighbor_index].q != NULL)) {
+      /* Free oldest packet (as per RFC recommendation) */
+      r = neighbor_cache[neighbor_index].q;
+      neighbor_cache[neighbor_index].q = r->next;
+      r->next = NULL;
+      nd6_free_q(r);
+      new_entry = (struct nd6_q_entry *)memp_malloc(MEMP_ND6_QUEUE);
+    }
+    if (new_entry != NULL) {
+      new_entry->next = NULL;
+      new_entry->p = p;
+      if (neighbor_cache[neighbor_index].q != NULL) {
+        /* queue was already existent, append the new entry to the end */
+        r = neighbor_cache[neighbor_index].q;
+        while (r->next != NULL) {
+          r = r->next;
+        }
+        r->next = new_entry;
+      } else {
+        /* queue did not exist, first item in queue */
+        neighbor_cache[neighbor_index].q = new_entry;
+      }
+      LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: queued packet %p on neighbor entry %"S16_F"\n", (void *)p, (s16_t)neighbor_index));
+      result = ERR_OK;
+    } else {
+      /* the pool MEMP_ND6_QUEUE is empty */
+      pbuf_free(p);
+      LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: could not queue a copy of packet %p (out of memory)\n", (void *)p));
+      /* { result == ERR_MEM } through initialization */
+    }
+#else /* LWIP_ND6_QUEUEING */
+    /* Queue a single packet. If an older packet is already queued, free it as per RFC. */
+    if (neighbor_cache[neighbor_index].q != NULL) {
+      pbuf_free(neighbor_cache[neighbor_index].q);
+    }
+    neighbor_cache[neighbor_index].q = p;
+    LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: queued packet %p on neighbor entry %"S16_F"\n", (void *)p, (s16_t)neighbor_index));
+    result = ERR_OK;
+#endif /* LWIP_ND6_QUEUEING */
+  } else {
+    LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: could not queue a copy of packet %p (out of memory)\n", (void *)q));
+    /* { result == ERR_MEM } through initialization */
+  }
+
+  return result;
+}
+
+#if LWIP_ND6_QUEUEING
+/**
+ * Free a complete queue of nd6 q entries
+ *
+ * @param q a queue of nd6_q_entry to free
+ */
+static void
+nd6_free_q(struct nd6_q_entry *q)
+{
+  struct nd6_q_entry *r;
+  LWIP_ASSERT("q != NULL", q != NULL);
+  LWIP_ASSERT("q->p != NULL", q->p != NULL);
+  while (q) {
+    r = q;
+    q = q->next;
+    LWIP_ASSERT("r->p != NULL", (r->p != NULL));
+    pbuf_free(r->p);
+    memp_free(MEMP_ND6_QUEUE, r);
+  }
+}
+#endif /* LWIP_ND6_QUEUEING */
+
+/**
+ * Send queued packets for a neighbor
+ *
+ * @param i the neighbor to send packets to
+ */
+static void
+nd6_send_q(s8_t i)
+{
+  struct ip6_hdr *ip6hdr;
+  ip6_addr_t dest;
+#if LWIP_ND6_QUEUEING
+  struct nd6_q_entry *q;
+#endif /* LWIP_ND6_QUEUEING */
+
+  if ((i < 0) || (i >= LWIP_ND6_NUM_NEIGHBORS)) {
+    return;
+  }
+
+#if LWIP_ND6_QUEUEING
+  while (neighbor_cache[i].q != NULL) {
+    /* remember first in queue */
+    q = neighbor_cache[i].q;
+    /* pop first item off the queue */
+    neighbor_cache[i].q = q->next;
+    /* Get ipv6 header. */
+    ip6hdr = (struct ip6_hdr *)(q->p->payload);
+    /* Create an aligned copy. */
+    ip6_addr_copy_from_packed(dest, ip6hdr->dest);
+    /* Restore the zone, if applicable. */
+    ip6_addr_assign_zone(&dest, IP6_UNKNOWN, neighbor_cache[i].netif);
+    /* send the queued IPv6 packet */
+    (neighbor_cache[i].netif)->output_ip6(neighbor_cache[i].netif, q->p, &dest);
+    /* free the queued IP packet */
+    pbuf_free(q->p);
+    /* now queue entry can be freed */
+    memp_free(MEMP_ND6_QUEUE, q);
+  }
+#else /* LWIP_ND6_QUEUEING */
+  if (neighbor_cache[i].q != NULL) {
+    /* Get ipv6 header. */
+    ip6hdr = (struct ip6_hdr *)(neighbor_cache[i].q->payload);
+    /* Create an aligned copy. */
+    ip6_addr_copy_from_packed(dest, ip6hdr->dest);
+    /* Restore the zone, if applicable. */
+    ip6_addr_assign_zone(&dest, IP6_UNKNOWN, neighbor_cache[i].netif);
+    /* send the queued IPv6 packet */
+    (neighbor_cache[i].netif)->output_ip6(neighbor_cache[i].netif, neighbor_cache[i].q, &dest);
+    /* free the queued IP packet */
+    pbuf_free(neighbor_cache[i].q);
+    neighbor_cache[i].q = NULL;
+  }
+#endif /* LWIP_ND6_QUEUEING */
+}
+
+/**
+ * A packet is to be transmitted to a specific IPv6 destination on a specific
+ * interface. Check if we can find the hardware address of the next hop to use
+ * for the packet. If so, give the hardware address to the caller, which should
+ * use it to send the packet right away. Otherwise, enqueue the packet for
+ * later transmission while looking up the hardware address, if possible.
+ *
+ * As such, this function returns one of three different possible results:
+ *
+ * - ERR_OK with a non-NULL 'hwaddrp': the caller should send the packet now.
+ * - ERR_OK with a NULL 'hwaddrp': the packet has been enqueued for later.
+ * - not ERR_OK: something went wrong; forward the error upward in the stack.
+ *
+ * @param netif The lwIP network interface on which the IP packet will be sent.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ip6addr The destination IPv6 address of the packet.
+ * @param hwaddrp On success, filled with a pointer to a HW address or NULL (meaning
+ *        the packet has been queued).
+ * @return
+ * - ERR_OK on success, ERR_RTE if no route was found for the packet,
+ * or ERR_MEM if low memory conditions prohibit sending the packet at all.
+ */
+err_t
+nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp)
+{
+  s8_t i;
+
+  /* Get next hop record. */
+  i = nd6_get_next_hop_entry(ip6addr, netif);
+  if (i < 0) {
+    /* failed to get a next hop neighbor record. */
+    return i;
+  }
+
+  /* Now that we have a destination record, send or queue the packet. */
+  if (neighbor_cache[i].state == ND6_STALE) {
+    /* Switch to delay state. */
+    neighbor_cache[i].state = ND6_DELAY;
+    neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL;
+  }
+  /* @todo should we send or queue if PROBE? send for now, to let unicast NS pass. */
+  if ((neighbor_cache[i].state == ND6_REACHABLE) ||
+      (neighbor_cache[i].state == ND6_DELAY) ||
+      (neighbor_cache[i].state == ND6_PROBE)) {
+
+    /* Tell the caller to send out the packet now. */
+    *hwaddrp = neighbor_cache[i].lladdr;
+    return ERR_OK;
+  }
+
+  /* We should queue packet on this interface. */
+  *hwaddrp = NULL;
+  return nd6_queue_packet(i, q);
+}
+
+
+/**
+ * Get the Path MTU for a destination.
+ *
+ * @param ip6addr the destination address
+ * @param netif the netif on which the packet will be sent
+ * @return the Path MTU, if known, or the netif default MTU
+ */
+u16_t
+nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif)
+{
+  s16_t i;
+
+  i = nd6_find_destination_cache_entry(ip6addr);
+  if (i >= 0) {
+    if (destination_cache[i].pmtu > 0) {
+      return destination_cache[i].pmtu;
+    }
+  }
+
+  if (netif != NULL) {
+    return netif_mtu6(netif);
+  }
+
+  return 1280; /* Minimum MTU */
+}
+
+
+#if LWIP_ND6_TCP_REACHABILITY_HINTS
+/**
+ * Provide the Neighbor discovery process with a hint that a
+ * destination is reachable. Called by tcp_receive when ACKs are
+ * received or sent (as per RFC). This is useful to avoid sending
+ * NS messages every 30 seconds.
+ *
+ * @param ip6addr the destination address which is know to be reachable
+ *                by an upper layer protocol (TCP)
+ */
+void
+nd6_reachability_hint(const ip6_addr_t *ip6addr)
+{
+  s8_t i;
+  s16_t dst_idx;
+
+  /* Find destination in cache. */
+  if (ip6_addr_cmp(ip6addr, &(destination_cache[nd6_cached_destination_index].destination_addr))) {
+    dst_idx = nd6_cached_destination_index;
+    ND6_STATS_INC(nd6.cachehit);
+  } else {
+    dst_idx = nd6_find_destination_cache_entry(ip6addr);
+  }
+  if (dst_idx < 0) {
+    return;
+  }
+
+  /* Find next hop neighbor in cache. */
+  if (ip6_addr_cmp(&(destination_cache[dst_idx].next_hop_addr), &(neighbor_cache[nd6_cached_neighbor_index].next_hop_address))) {
+    i = nd6_cached_neighbor_index;
+    ND6_STATS_INC(nd6.cachehit);
+  } else {
+    i = nd6_find_neighbor_cache_entry(&(destination_cache[dst_idx].next_hop_addr));
+  }
+  if (i < 0) {
+    return;
+  }
+
+  /* For safety: don't set as reachable if we don't have a LL address yet. Misuse protection. */
+  if (neighbor_cache[i].state == ND6_INCOMPLETE || neighbor_cache[i].state == ND6_NO_ENTRY) {
+    return;
+  }
+
+  /* Set reachability state. */
+  neighbor_cache[i].state = ND6_REACHABLE;
+  neighbor_cache[i].counter.reachable_time = reachable_time;
+}
+#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */
+
+/**
+ * Remove all prefix, neighbor_cache and router entries of the specified netif.
+ *
+ * @param netif points to a network interface
+ */
+void
+nd6_cleanup_netif(struct netif *netif)
+{
+  u8_t i;
+  s8_t router_index;
+  for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) {
+    if (prefix_list[i].netif == netif) {
+      prefix_list[i].netif = NULL;
+    }
+  }
+  for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) {
+    if (neighbor_cache[i].netif == netif) {
+      for (router_index = 0; router_index < LWIP_ND6_NUM_ROUTERS; router_index++) {
+        if (default_router_list[router_index].neighbor_entry == &neighbor_cache[i]) {
+          default_router_list[router_index].neighbor_entry = NULL;
+          default_router_list[router_index].flags = 0;
+        }
+      }
+      neighbor_cache[i].isrouter = 0;
+      nd6_free_neighbor_cache_entry(i);
+    }
+  }
+  /* Clear the destination cache, since many entries may now have become
+   * invalid for one of several reasons. As destination cache entries have no
+   * netif association, use a sledgehammer approach (this can be improved). */
+  nd6_clear_destination_cache();
+}
+
+#if LWIP_IPV6_MLD
+/**
+ * The state of a local IPv6 address entry is about to change. If needed, join
+ * or leave the solicited-node multicast group for the address.
+ *
+ * @param netif The netif that owns the address.
+ * @param addr_idx The index of the address.
+ * @param new_state The new (IP6_ADDR_) state for the address.
+ */
+void
+nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state)
+{
+  u8_t old_state, old_member, new_member;
+
+  old_state = netif_ip6_addr_state(netif, addr_idx);
+
+  /* Determine whether we were, and should be, a member of the solicited-node
+   * multicast group for this address. For tentative addresses, the group is
+   * not joined until the address enters the TENTATIVE_1 (or VALID) state. */
+  old_member = (old_state != IP6_ADDR_INVALID && old_state != IP6_ADDR_DUPLICATED && old_state != IP6_ADDR_TENTATIVE);
+  new_member = (new_state != IP6_ADDR_INVALID && new_state != IP6_ADDR_DUPLICATED && new_state != IP6_ADDR_TENTATIVE);
+
+  if (old_member != new_member) {
+    ip6_addr_set_solicitednode(&multicast_address, netif_ip6_addr(netif, addr_idx)->addr[3]);
+    ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif);
+
+    if (new_member) {
+      mld6_joingroup_netif(netif, &multicast_address);
+    } else {
+      mld6_leavegroup_netif(netif, &multicast_address);
+    }
+  }
+}
+#endif /* LWIP_IPV6_MLD */
+
+/** Netif was added, set up, or reconnected (link up) */
+void
+nd6_restart_netif(struct netif *netif)
+{
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+  /* Send Router Solicitation messages (see RFC 4861, ch. 6.3.7). */
+  netif->rs_count = LWIP_ND6_MAX_MULTICAST_SOLICIT;
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+}
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/mem.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/mem.c
new file mode 100644
index 000000000..315fb3c5d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/mem.c
@@ -0,0 +1,1017 @@
+/**
+ * @file
+ * Dynamic memory manager
+ *
+ * This is a lightweight replacement for the standard C library malloc().
+ *
+ * If you want to use the standard C library malloc() instead, define
+ * MEM_LIBC_MALLOC to 1 in your lwipopts.h
+ *
+ * To let mem_malloc() use pools (prevents fragmentation and is much faster than
+ * a heap but might waste some memory), define MEM_USE_POOLS to 1, define
+ * MEMP_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list
+ * of pools like this (more pools can be added between _START and _END):
+ *
+ * Define three pools with sizes 256, 512, and 1512 bytes
+ * LWIP_MALLOC_MEMPOOL_START
+ * LWIP_MALLOC_MEMPOOL(20, 256)
+ * LWIP_MALLOC_MEMPOOL(10, 512)
+ * LWIP_MALLOC_MEMPOOL(5, 1512)
+ * LWIP_MALLOC_MEMPOOL_END
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *         Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/mem.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/err.h"
+
+#include <string.h>
+
+#if MEM_LIBC_MALLOC
+#include <stdlib.h> /* for malloc()/free() */
+#endif
+
+/* This is overridable for tests only... */
+#ifndef LWIP_MEM_ILLEGAL_FREE
+#define LWIP_MEM_ILLEGAL_FREE(msg)         LWIP_ASSERT(msg, 0)
+#endif
+
+#define MEM_STATS_INC_LOCKED(x)         SYS_ARCH_LOCKED(MEM_STATS_INC(x))
+#define MEM_STATS_INC_USED_LOCKED(x, y) SYS_ARCH_LOCKED(MEM_STATS_INC_USED(x, y))
+#define MEM_STATS_DEC_USED_LOCKED(x, y) SYS_ARCH_LOCKED(MEM_STATS_DEC_USED(x, y))
+
+#if MEM_OVERFLOW_CHECK
+#define MEM_SANITY_OFFSET   MEM_SANITY_REGION_BEFORE_ALIGNED
+#define MEM_SANITY_OVERHEAD (MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED)
+#else
+#define MEM_SANITY_OFFSET   0
+#define MEM_SANITY_OVERHEAD 0
+#endif
+
+#if MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK
+/**
+ * Check if a mep element was victim of an overflow or underflow
+ * (e.g. the restricted area after/before it has been altered)
+ *
+ * @param p the mem element to check
+ * @param size allocated size of the element
+ * @param descr1 description of the element source shown on error
+ * @param descr2 description of the element source shown on error
+ */
+void
+mem_overflow_check_raw(void *p, size_t size, const char *descr1, const char *descr2)
+{
+#if MEM_SANITY_REGION_AFTER_ALIGNED || MEM_SANITY_REGION_BEFORE_ALIGNED
+  u16_t k;
+  u8_t *m;
+
+#if MEM_SANITY_REGION_AFTER_ALIGNED > 0
+  m = (u8_t *)p + size;
+  for (k = 0; k < MEM_SANITY_REGION_AFTER_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      char errstr[128];
+      snprintf(errstr, sizeof(errstr), "detected mem overflow in %s%s", descr1, descr2);
+      LWIP_ASSERT(errstr, 0);
+    }
+  }
+#endif /* MEM_SANITY_REGION_AFTER_ALIGNED > 0 */
+
+#if MEM_SANITY_REGION_BEFORE_ALIGNED > 0
+  m = (u8_t *)p - MEM_SANITY_REGION_BEFORE_ALIGNED;
+  for (k = 0; k < MEM_SANITY_REGION_BEFORE_ALIGNED; k++) {
+    if (m[k] != 0xcd) {
+      char errstr[128];
+      snprintf(errstr, sizeof(errstr), "detected mem underflow in %s%s", descr1, descr2);
+      LWIP_ASSERT(errstr, 0);
+    }
+  }
+#endif /* MEM_SANITY_REGION_BEFORE_ALIGNED > 0 */
+#else
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(desc);
+  LWIP_UNUSED_ARG(descr);
+#endif
+}
+
+/**
+ * Initialize the restricted area of a mem element.
+ */
+void
+mem_overflow_init_raw(void *p, size_t size)
+{
+#if MEM_SANITY_REGION_BEFORE_ALIGNED > 0 || MEM_SANITY_REGION_AFTER_ALIGNED > 0
+  u8_t *m;
+#if MEM_SANITY_REGION_BEFORE_ALIGNED > 0
+  m = (u8_t *)p - MEM_SANITY_REGION_BEFORE_ALIGNED;
+  memset(m, 0xcd, MEM_SANITY_REGION_BEFORE_ALIGNED);
+#endif
+#if MEM_SANITY_REGION_AFTER_ALIGNED > 0
+  m = (u8_t *)p + size;
+  memset(m, 0xcd, MEM_SANITY_REGION_AFTER_ALIGNED);
+#endif
+#else /* MEM_SANITY_REGION_BEFORE_ALIGNED > 0 || MEM_SANITY_REGION_AFTER_ALIGNED > 0 */
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(desc);
+#endif /* MEM_SANITY_REGION_BEFORE_ALIGNED > 0 || MEM_SANITY_REGION_AFTER_ALIGNED > 0 */
+}
+#endif /* MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK */
+
+#if MEM_LIBC_MALLOC || MEM_USE_POOLS
+
+/** mem_init is not used when using pools instead of a heap or using
+ * C library malloc().
+ */
+void
+mem_init(void)
+{
+}
+
+/** mem_trim is not used when using pools instead of a heap or using
+ * C library malloc(): we can't free part of a pool element and the stack
+ * support mem_trim() to return a different pointer
+ */
+void *
+mem_trim(void *mem, mem_size_t size)
+{
+  LWIP_UNUSED_ARG(size);
+  return mem;
+}
+#endif /* MEM_LIBC_MALLOC || MEM_USE_POOLS */
+
+#if MEM_LIBC_MALLOC
+/* lwIP heap implemented using C library malloc() */
+
+/* in case C library malloc() needs extra protection,
+ * allow these defines to be overridden.
+ */
+#ifndef mem_clib_free
+#define mem_clib_free free
+#endif
+#ifndef mem_clib_malloc
+#define mem_clib_malloc malloc
+#endif
+#ifndef mem_clib_calloc
+#define mem_clib_calloc calloc
+#endif
+
+#if LWIP_STATS && MEM_STATS
+#define MEM_LIBC_STATSHELPER_SIZE LWIP_MEM_ALIGN_SIZE(sizeof(mem_size_t))
+#else
+#define MEM_LIBC_STATSHELPER_SIZE 0
+#endif
+
+/**
+ * Allocate a block of memory with a minimum of 'size' bytes.
+ *
+ * @param size is the minimum size of the requested block in bytes.
+ * @return pointer to allocated memory or NULL if no free memory was found.
+ *
+ * Note that the returned value must always be aligned (as defined by MEM_ALIGNMENT).
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  void *ret = mem_clib_malloc(size + MEM_LIBC_STATSHELPER_SIZE);
+  if (ret == NULL) {
+    MEM_STATS_INC_LOCKED(err);
+  } else {
+    LWIP_ASSERT("malloc() must return aligned memory", LWIP_MEM_ALIGN(ret) == ret);
+#if LWIP_STATS && MEM_STATS
+    *(mem_size_t *)ret = size;
+    ret = (u8_t *)ret + MEM_LIBC_STATSHELPER_SIZE;
+    MEM_STATS_INC_USED_LOCKED(used, size);
+#endif
+  }
+  return ret;
+}
+
+/** Put memory back on the heap
+ *
+ * @param rmem is the pointer as returned by a previous call to mem_malloc()
+ */
+void
+mem_free(void *rmem)
+{
+  LWIP_ASSERT("rmem != NULL", (rmem != NULL));
+  LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem)));
+#if LWIP_STATS && MEM_STATS
+  rmem = (u8_t *)rmem - MEM_LIBC_STATSHELPER_SIZE;
+  MEM_STATS_DEC_USED_LOCKED(used, *(mem_size_t *)rmem);
+#endif
+  mem_clib_free(rmem);
+}
+
+#elif MEM_USE_POOLS
+
+/* lwIP heap implemented with different sized pools */
+
+/**
+ * Allocate memory: determine the smallest pool that is big enough
+ * to contain an element of 'size' and get an element from that pool.
+ *
+ * @param size the size in bytes of the memory needed
+ * @return a pointer to the allocated memory or NULL if the pool is empty
+ */
+void *
+mem_malloc(mem_size_t size)
+{
+  void *ret;
+  struct memp_malloc_helper *element = NULL;
+  memp_t poolnr;
+  mem_size_t required_size = size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper));
+
+  for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr = (memp_t)(poolnr + 1)) {
+    /* is this pool big enough to hold an element of the required size
+       plus a struct memp_malloc_helper that saves the pool this element came from? */
+    if (required_size <= memp_pools[poolnr]->size) {
+      element = (struct memp_malloc_helper *)memp_malloc(poolnr);
+      if (element == NULL) {
+        /* No need to DEBUGF or ASSERT: This error is already taken care of in memp.c */
+#if MEM_USE_POOLS_TRY_BIGGER_POOL
+        /** Try a bigger pool if this one is empty! */
+        if (poolnr < MEMP_POOL_LAST) {
+          continue;
+        }
+#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */
+        MEM_STATS_INC_LOCKED(err);
+        return NULL;
+      }
+      break;
+    }
+  }
+  if (poolnr > MEMP_POOL_LAST) {
+    LWIP_ASSERT("mem_malloc(): no pool is that big!", 0);
+    MEM_STATS_INC_LOCKED(err);
+    return NULL;
+  }
+
+  /* save the pool number this element came from */
+  element->poolnr = poolnr;
+  /* and return a pointer to the memory directly after the struct memp_malloc_helper */
+  ret = (u8_t *)element + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper));
+
+#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS)
+  /* truncating to u16_t is safe because struct memp_desc::size is u16_t */
+  element->size = (u16_t)size;
+  MEM_STATS_INC_USED_LOCKED(used, element->size);
+#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */
+#if MEMP_OVERFLOW_CHECK
+  /* initialize unused memory (diff between requested size and selected pool's size) */
+  memset((u8_t *)ret + size, 0xcd, memp_pools[poolnr]->size - size);
+#endif /* MEMP_OVERFLOW_CHECK */
+  return ret;
+}
+
+/**
+ * Free memory previously allocated by mem_malloc. Loads the pool number
+ * and calls memp_free with that pool number to put the element back into
+ * its pool
+ *
+ * @param rmem the memory element to free
+ */
+void
+mem_free(void *rmem)
+{
+  struct memp_malloc_helper *hmem;
+
+  LWIP_ASSERT("rmem != NULL", (rmem != NULL));
+  LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem)));
+
+  /* get the original struct memp_malloc_helper */
+  /* cast through void* to get rid of alignment warnings */
+  hmem = (struct memp_malloc_helper *)(void *)((u8_t *)rmem - LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper)));
+
+  LWIP_ASSERT("hmem != NULL", (hmem != NULL));
+  LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem)));
+  LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX));
+
+  MEM_STATS_DEC_USED_LOCKED(used, hmem->size);
+#if MEMP_OVERFLOW_CHECK
+  {
+    u16_t i;
+    LWIP_ASSERT("MEM_USE_POOLS: invalid chunk size",
+                hmem->size <= memp_pools[hmem->poolnr]->size);
+    /* check that unused memory remained untouched (diff between requested size and selected pool's size) */
+    for (i = hmem->size; i < memp_pools[hmem->poolnr]->size; i++) {
+      u8_t data = *((u8_t *)rmem + i);
+      LWIP_ASSERT("MEM_USE_POOLS: mem overflow detected", data == 0xcd);
+    }
+  }
+#endif /* MEMP_OVERFLOW_CHECK */
+
+  /* and put it in the pool we saved earlier */
+  memp_free(hmem->poolnr, hmem);
+}
+
+#else /* MEM_USE_POOLS */
+/* lwIP replacement for your libc malloc() */
+
+/**
+ * The heap is made up as a list of structs of this type.
+ * This does not have to be aligned since for getting its size,
+ * we only use the macro SIZEOF_STRUCT_MEM, which automatically aligns.
+ */
+struct mem {
+  /** index (-> ram[next]) of the next struct */
+  mem_size_t next;
+  /** index (-> ram[prev]) of the previous struct */
+  mem_size_t prev;
+  /** 1: this area is used; 0: this area is unused */
+  u8_t used;
+#if MEM_OVERFLOW_CHECK
+  /** this keeps track of the user allocation size for guard checks */
+  mem_size_t user_size;
+#endif
+};
+
+/** All allocated blocks will be MIN_SIZE bytes big, at least!
+ * MIN_SIZE can be overridden to suit your needs. Smaller values save space,
+ * larger values could prevent too small blocks to fragment the RAM too much. */
+#ifndef MIN_SIZE
+#define MIN_SIZE             12
+#endif /* MIN_SIZE */
+/* some alignment macros: we define them here for better source code layout */
+#define MIN_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MIN_SIZE)
+#define SIZEOF_STRUCT_MEM    LWIP_MEM_ALIGN_SIZE(sizeof(struct mem))
+#define MEM_SIZE_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEM_SIZE)
+
+/** If you want to relocate the heap to external memory, simply define
+ * LWIP_RAM_HEAP_POINTER as a void-pointer to that location.
+ * If so, make sure the memory at that location is big enough (see below on
+ * how that space is calculated). */
+#ifndef LWIP_RAM_HEAP_POINTER
+/** the heap. we need one struct mem at the end and some room for alignment */
+LWIP_DECLARE_MEMORY_ALIGNED(ram_heap, MEM_SIZE_ALIGNED + (2U * SIZEOF_STRUCT_MEM));
+#define LWIP_RAM_HEAP_POINTER ram_heap
+#endif /* LWIP_RAM_HEAP_POINTER */
+
+/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */
+static u8_t *ram;
+/** the last entry, always unused! */
+static struct mem *ram_end;
+
+/** concurrent access protection */
+#if !NO_SYS
+static sys_mutex_t mem_mutex;
+#endif
+
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+
+static volatile u8_t mem_free_count;
+
+/* Allow mem_free from other (e.g. interrupt) context */
+#define LWIP_MEM_FREE_DECL_PROTECT()  SYS_ARCH_DECL_PROTECT(lev_free)
+#define LWIP_MEM_FREE_PROTECT()       SYS_ARCH_PROTECT(lev_free)
+#define LWIP_MEM_FREE_UNPROTECT()     SYS_ARCH_UNPROTECT(lev_free)
+#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc)
+#define LWIP_MEM_ALLOC_PROTECT()      SYS_ARCH_PROTECT(lev_alloc)
+#define LWIP_MEM_ALLOC_UNPROTECT()    SYS_ARCH_UNPROTECT(lev_alloc)
+#define LWIP_MEM_LFREE_VOLATILE       volatile
+
+#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+/* Protect the heap only by using a mutex */
+#define LWIP_MEM_FREE_DECL_PROTECT()
+#define LWIP_MEM_FREE_PROTECT()    sys_mutex_lock(&mem_mutex)
+#define LWIP_MEM_FREE_UNPROTECT()  sys_mutex_unlock(&mem_mutex)
+/* mem_malloc is protected using mutex AND LWIP_MEM_ALLOC_PROTECT */
+#define LWIP_MEM_ALLOC_DECL_PROTECT()
+#define LWIP_MEM_ALLOC_PROTECT()
+#define LWIP_MEM_ALLOC_UNPROTECT()
+#define LWIP_MEM_LFREE_VOLATILE
+
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+/** pointer to the lowest free block, this is used for faster search */
+static struct mem * LWIP_MEM_LFREE_VOLATILE lfree;
+
+#if MEM_SANITY_CHECK
+static void mem_sanity(void);
+#define MEM_SANITY() mem_sanity()
+#else
+#define MEM_SANITY()
+#endif
+
+#if MEM_OVERFLOW_CHECK
+static void
+mem_overflow_init_element(struct mem *mem, mem_size_t user_size)
+{
+  void *p = (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
+  mem->user_size = user_size;
+  mem_overflow_init_raw(p, user_size);
+}
+
+static void
+mem_overflow_check_element(struct mem *mem)
+{
+  void *p = (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
+  mem_overflow_check_raw(p, mem->user_size, "heap", "");
+}
+#else /* MEM_OVERFLOW_CHECK */
+#define mem_overflow_init_element(mem, size)
+#define mem_overflow_check_element(mem)
+#endif /* MEM_OVERFLOW_CHECK */
+
+static struct mem *
+ptr_to_mem(mem_size_t ptr)
+{
+  return (struct mem *)(void *)&ram[ptr];
+}
+
+static mem_size_t
+mem_to_ptr(void *mem)
+{
+  return (mem_size_t)((u8_t *)mem - ram);
+}
+
+/**
+ * "Plug holes" by combining adjacent empty struct mems.
+ * After this function is through, there should not exist
+ * one empty struct mem pointing to another empty struct mem.
+ *
+ * @param mem this points to a struct mem which just has been freed
+ * @internal this function is only called by mem_free() and mem_trim()
+ *
+ * This assumes access to the heap is protected by the calling function
+ * already.
+ */
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
+
+  nmem = ptr_to_mem(mem->next);
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    /* if mem->next is unused and not end of ram, combine mem and mem->next */
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    if (nmem->next != MEM_SIZE_ALIGNED) {
+      ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
+    }
+  }
+
+  /* plug hole backward */
+  pmem = ptr_to_mem(mem->prev);
+  if (pmem != mem && pmem->used == 0) {
+    /* if mem->prev is unused, combine mem and mem->prev */
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    if (mem->next != MEM_SIZE_ALIGNED) {
+      ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
+    }
+  }
+}
+
+/**
+ * Zero the heap and initialize start, end and lowest-free
+ */
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  LWIP_ASSERT("Sanity check alignment",
+              (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
+
+  /* align the heap */
+  ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
+  /* initialize the start of the heap */
+  mem = (struct mem *)(void *)ram;
+  mem->next = MEM_SIZE_ALIGNED;
+  mem->prev = 0;
+  mem->used = 0;
+  /* initialize the end of the heap */
+  ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE_ALIGNED;
+  ram_end->prev = MEM_SIZE_ALIGNED;
+  MEM_SANITY();
+
+  /* initialize the lowest-free pointer to the start of the heap */
+  lfree = (struct mem *)(void *)ram;
+
+  MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
+
+  if (sys_mutex_new(&mem_mutex) != ERR_OK) {
+    LWIP_ASSERT("failed to create mem_mutex", 0);
+  }
+}
+
+/* Check if a struct mem is correctly linked.
+ * If not, double-free is a possible reason.
+ */
+static int
+mem_link_valid(struct mem *mem)
+{
+  struct mem *nmem, *pmem;
+  mem_size_t rmem_idx;
+  rmem_idx = mem_to_ptr(mem);
+  nmem = ptr_to_mem(mem->next);
+  pmem = ptr_to_mem(mem->prev);
+  if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
+      ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
+      ((nmem != ram_end) && (nmem->prev != rmem_idx))) {
+    return 0;
+  }
+  return 1;
+}
+
+#if MEM_SANITY_CHECK
+static void
+mem_sanity(void)
+{
+  struct mem *mem;
+  u8_t last_used;
+
+  /* begin with first element here */
+  mem = (struct mem *)ram;
+  LWIP_ASSERT("heap element used valid", (mem->used == 0) || (mem->used == 1));
+  last_used = mem->used;
+  LWIP_ASSERT("heap element prev ptr valid", mem->prev == 0);
+  LWIP_ASSERT("heap element next ptr valid", mem->next <= MEM_SIZE_ALIGNED);
+  LWIP_ASSERT("heap element next ptr aligned", LWIP_MEM_ALIGN(ptr_to_mem(mem->next) == ptr_to_mem(mem->next)));
+
+  /* check all elements before the end of the heap */
+  for (mem = ptr_to_mem(mem->next);
+       ((u8_t *)mem > ram) && (mem < ram_end);
+       mem = ptr_to_mem(mem->next)) {
+    LWIP_ASSERT("heap element aligned", LWIP_MEM_ALIGN(mem) == mem);
+    LWIP_ASSERT("heap element prev ptr valid", mem->prev <= MEM_SIZE_ALIGNED);
+    LWIP_ASSERT("heap element next ptr valid", mem->next <= MEM_SIZE_ALIGNED);
+    LWIP_ASSERT("heap element prev ptr aligned", LWIP_MEM_ALIGN(ptr_to_mem(mem->prev) == ptr_to_mem(mem->prev)));
+    LWIP_ASSERT("heap element next ptr aligned", LWIP_MEM_ALIGN(ptr_to_mem(mem->next) == ptr_to_mem(mem->next)));
+
+    if (last_used == 0) {
+      /* 2 unused elements in a row? */
+      LWIP_ASSERT("heap element unused?", mem->used == 1);
+    } else {
+      LWIP_ASSERT("heap element unused member", (mem->used == 0) || (mem->used == 1));
+    }
+
+    LWIP_ASSERT("heap element link valid", mem_link_valid(mem));
+
+    /* used/unused altering */
+    last_used = mem->used;
+  }
+  LWIP_ASSERT("heap end ptr sanity", mem == ptr_to_mem(MEM_SIZE_ALIGNED));
+  LWIP_ASSERT("heap element used valid", mem->used == 1);
+  LWIP_ASSERT("heap element prev ptr valid", mem->prev == MEM_SIZE_ALIGNED);
+  LWIP_ASSERT("heap element next ptr valid", mem->next == MEM_SIZE_ALIGNED);
+}
+#endif /* MEM_SANITY_CHECK */
+
+/**
+ * Put a struct mem back on the heap
+ *
+ * @param rmem is the data portion of a struct mem as returned by a previous
+ *             call to mem_malloc()
+ */
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
+    LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+    return;
+  }
+
+  /* Get the corresponding struct mem: */
+  /* cast through void* to get rid of alignment warnings */
+  mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
+
+  if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
+    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+    return;
+  }
+#if MEM_OVERFLOW_CHECK
+  mem_overflow_check_element(mem);
+#endif
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+  /* mem has to be in a used state */
+  if (!mem->used) {
+    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
+    LWIP_MEM_FREE_UNPROTECT();
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+    return;
+  }
+
+  if (!mem_link_valid(mem)) {
+    LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
+    LWIP_MEM_FREE_UNPROTECT();
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+    return;
+  }
+
+  /* mem is now unused. */
+  mem->used = 0;
+
+  if (mem < lfree) {
+    /* the newly freed struct is now the lowest */
+    lfree = mem;
+  }
+
+  MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
+
+  /* finally, see if prev or next are free also */
+  plug_holes(mem);
+  MEM_SANITY();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+}
+
+/**
+ * Shrink memory returned by mem_malloc().
+ *
+ * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked
+ * @param new_size required size after shrinking (needs to be smaller than or
+ *                equal to the previous size)
+ * @return for compatibility reasons: is always == rmem, at the moment
+ *         or NULL if newsize is > old size, in which case rmem is NOT touched
+ *         or freed!
+ */
+void *
+mem_trim(void *rmem, mem_size_t new_size)
+{
+  mem_size_t size, newsize;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+  /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
+  LWIP_MEM_FREE_DECL_PROTECT();
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
+  if (newsize < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    newsize = MIN_SIZE_ALIGNED;
+  }
+#if MEM_OVERFLOW_CHECK
+  newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
+#endif
+  if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
+    return NULL;
+  }
+
+  LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+              (u8_t *)rmem < (u8_t *)ram_end);
+
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
+    /* protect mem stats from concurrent access */
+    MEM_STATS_INC_LOCKED(illegal);
+    return rmem;
+  }
+  /* Get the corresponding struct mem ... */
+  /* cast through void* to get rid of alignment warnings */
+  mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
+#if MEM_OVERFLOW_CHECK
+  mem_overflow_check_element(mem);
+#endif
+  /* ... and its offset pointer */
+  ptr = mem_to_ptr(mem);
+
+  size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
+  LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
+  if (newsize > size) {
+    /* not supported */
+    return NULL;
+  }
+  if (newsize == size) {
+    /* No change in size, simply return */
+    return rmem;
+  }
+
+  /* protect the heap from concurrent access */
+  LWIP_MEM_FREE_PROTECT();
+
+  mem2 = ptr_to_mem(mem->next);
+  if (mem2->used == 0) {
+    /* The next struct is unused, we can simply move it at little */
+    mem_size_t next;
+    LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
+    /* remember the old next pointer */
+    next = mem2->next;
+    /* create new struct mem which is moved directly after the shrinked mem */
+    ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
+    if (lfree == mem2) {
+      lfree = ptr_to_mem(ptr2);
+    }
+    mem2 = ptr_to_mem(ptr2);
+    mem2->used = 0;
+    /* restore the next pointer */
+    mem2->next = next;
+    /* link it back to mem */
+    mem2->prev = ptr;
+    /* link mem to it */
+    mem->next = ptr2;
+    /* last thing to restore linked list: as we have moved mem2,
+     * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
+     * the end of the heap */
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ptr_to_mem(mem2->next)->prev = ptr2;
+    }
+    MEM_STATS_DEC_USED(used, (size - newsize));
+    /* no need to plug holes, we've already done that */
+  } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
+    /* Next struct is used but there's room for another struct mem with
+     * at least MIN_SIZE_ALIGNED of data.
+     * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
+     * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
+     * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+     *       region that couldn't hold data, but when mem->next gets freed,
+     *       the 2 regions would be combined, resulting in more free memory */
+    ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
+    LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
+    mem2 = ptr_to_mem(ptr2);
+    if (mem2 < lfree) {
+      lfree = mem2;
+    }
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE_ALIGNED) {
+      ptr_to_mem(mem2->next)->prev = ptr2;
+    }
+    MEM_STATS_DEC_USED(used, (size - newsize));
+    /* the original mem->next is used, so no need to plug holes! */
+  }
+  /* else {
+    next struct mem is used but size between mem and mem2 is not big enough
+    to create another struct mem
+    -> don't do anyhting.
+    -> the remaining space stays unused since it is too small
+  } */
+#if MEM_OVERFLOW_CHECK
+  mem_overflow_init_element(mem, new_size);
+#endif
+  MEM_SANITY();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  mem_free_count = 1;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_FREE_UNPROTECT();
+  return rmem;
+}
+
+/**
+ * Allocate a block of memory with a minimum of 'size' bytes.
+ *
+ * @param size_in is the minimum size of the requested block in bytes.
+ * @return pointer to allocated memory or NULL if no free memory was found.
+ *
+ * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
+ */
+void *
+mem_malloc(mem_size_t size_in)
+{
+  mem_size_t ptr, ptr2, size;
+  struct mem *mem, *mem2;
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  u8_t local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  LWIP_MEM_ALLOC_DECL_PROTECT();
+
+  if (size_in == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
+  if (size < MIN_SIZE_ALIGNED) {
+    /* every data block must be at least MIN_SIZE_ALIGNED long */
+    size = MIN_SIZE_ALIGNED;
+  }
+#if MEM_OVERFLOW_CHECK
+  size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
+#endif
+  if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
+    return NULL;
+  }
+
+  /* protect the heap from concurrent access */
+  sys_mutex_lock(&mem_mutex);
+  LWIP_MEM_ALLOC_PROTECT();
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+  /* run as long as a mem_free disturbed mem_malloc or mem_trim */
+  do {
+    local_mem_free_count = 0;
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+    /* Scan through the heap searching for a free block that is big enough,
+     * beginning with the lowest free block.
+     */
+    for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
+         ptr = ptr_to_mem(ptr)->next) {
+      mem = ptr_to_mem(ptr);
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+      mem_free_count = 0;
+      LWIP_MEM_ALLOC_UNPROTECT();
+      /* allow mem_free or mem_trim to run */
+      LWIP_MEM_ALLOC_PROTECT();
+      if (mem_free_count != 0) {
+        /* If mem_free or mem_trim have run, we have to restart since they
+           could have altered our current struct mem. */
+        local_mem_free_count = 1;
+        break;
+      }
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+
+      if ((!mem->used) &&
+          (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
+        /* mem is not used and at least perfect fit is possible:
+         * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
+
+        if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
+          /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing
+           * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem')
+           * -> split large block, create empty remainder,
+           * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if
+           * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size,
+           * struct mem would fit in but no data between mem2 and mem2->next
+           * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
+           *       region that couldn't hold data, but when mem->next gets freed,
+           *       the 2 regions would be combined, resulting in more free memory
+           */
+          ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
+          LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
+          /* create mem2 struct */
+          mem2 = ptr_to_mem(ptr2);
+          mem2->used = 0;
+          mem2->next = mem->next;
+          mem2->prev = ptr;
+          /* and insert it between mem and mem->next */
+          mem->next = ptr2;
+          mem->used = 1;
+
+          if (mem2->next != MEM_SIZE_ALIGNED) {
+            ptr_to_mem(mem2->next)->prev = ptr2;
+          }
+          MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM));
+        } else {
+          /* (a mem2 struct does no fit into the user data space of mem and mem->next will always
+           * be used at this point: if not we have 2 unused structs in a row, plug_holes should have
+           * take care of this).
+           * -> near fit or exact fit: do not split, no mem2 creation
+           * also can't move mem->next directly behind mem, since mem->next
+           * will always be used at this point!
+           */
+          mem->used = 1;
+          MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
+        }
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+mem_malloc_adjust_lfree:
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+        if (mem == lfree) {
+          struct mem *cur = lfree;
+          /* Find next free block after mem and update lowest free pointer */
+          while (cur->used && cur != ram_end) {
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+            mem_free_count = 0;
+            LWIP_MEM_ALLOC_UNPROTECT();
+            /* prevent high interrupt latency... */
+            LWIP_MEM_ALLOC_PROTECT();
+            if (mem_free_count != 0) {
+              /* If mem_free or mem_trim have run, we have to restart since they
+                 could have altered our current struct mem or lfree. */
+              goto mem_malloc_adjust_lfree;
+            }
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+            cur = ptr_to_mem(cur->next);
+          }
+          lfree = cur;
+          LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
+        }
+        LWIP_MEM_ALLOC_UNPROTECT();
+        sys_mutex_unlock(&mem_mutex);
+        LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+                    (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+        LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+                    ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+        LWIP_ASSERT("mem_malloc: sanity check alignment",
+                    (((mem_ptr_t)mem) & (MEM_ALIGNMENT - 1)) == 0);
+
+#if MEM_OVERFLOW_CHECK
+        mem_overflow_init_element(mem, size_in);
+#endif
+        MEM_SANITY();
+        return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
+      }
+    }
+#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+    /* if we got interrupted by a mem_free, try again */
+  } while (local_mem_free_count != 0);
+#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
+  MEM_STATS_INC(err);
+  LWIP_MEM_ALLOC_UNPROTECT();
+  sys_mutex_unlock(&mem_mutex);
+  LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+  return NULL;
+}
+
+#endif /* MEM_USE_POOLS */
+
+#if MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS)
+void *
+mem_calloc(mem_size_t count, mem_size_t size)
+{
+  return mem_clib_calloc(count, size);
+}
+
+#else /* MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) */
+/**
+ * Contiguously allocates enough space for count objects that are size bytes
+ * of memory each and returns a pointer to the allocated memory.
+ *
+ * The allocated memory is filled with bytes of value zero.
+ *
+ * @param count number of objects to allocate
+ * @param size size of the objects to allocate
+ * @return pointer to allocated memory / NULL pointer if there is an error
+ */
+void *
+mem_calloc(mem_size_t count, mem_size_t size)
+{
+  void *p;
+  size_t alloc_size = (size_t)count * (size_t)size;
+
+  if ((size_t)(mem_size_t)alloc_size != alloc_size) {
+    LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_calloc: could not allocate %"SZT_F" bytes\n", alloc_size));
+    return NULL;
+  }
+
+  /* allocate 'count' objects of size 'size' */
+  p = mem_malloc((mem_size_t)alloc_size);
+  if (p) {
+    /* zero the memory */
+    memset(p, 0, alloc_size);
+  }
+  return p;
+}
+#endif /* MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/memp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/memp.c
new file mode 100644
index 000000000..352ce5a55
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/memp.c
@@ -0,0 +1,447 @@
+/**
+ * @file
+ * Dynamic pool memory manager
+ *
+ * lwIP has dedicated pools for many structures (netconn, protocol control blocks,
+ * packet buffers, ...). All these pools are managed here.
+ *
+ * @defgroup mempool Memory pools
+ * @ingroup infrastructure
+ * Custom memory pools
+
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+#include <string.h>
+
+/* Make sure we include everything we need for size calculation required by memp_std.h */
+#include "lwip/pbuf.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/altcp.h"
+#include "lwip/ip4_frag.h"
+#include "lwip/netbuf.h"
+#include "lwip/api.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "lwip/priv/api_msg.h"
+#include "lwip/priv/sockets_priv.h"
+#include "lwip/etharp.h"
+#include "lwip/igmp.h"
+#include "lwip/timeouts.h"
+/* needed by default MEMP_NUM_SYS_TIMEOUT */
+#include "netif/ppp/ppp_opts.h"
+#include "lwip/netdb.h"
+#include "lwip/dns.h"
+#include "lwip/priv/nd6_priv.h"
+#include "lwip/ip6_frag.h"
+#include "lwip/mld6.h"
+
+#define LWIP_MEMPOOL(name,num,size,desc) LWIP_MEMPOOL_DECLARE(name,num,size,desc)
+#include "lwip/priv/memp_std.h"
+
+const struct memp_desc *const memp_pools[MEMP_MAX] = {
+#define LWIP_MEMPOOL(name,num,size,desc) &memp_ ## name,
+#include "lwip/priv/memp_std.h"
+};
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+#if MEMP_MEM_MALLOC && MEMP_OVERFLOW_CHECK >= 2
+#undef MEMP_OVERFLOW_CHECK
+/* MEMP_OVERFLOW_CHECK >= 2 does not work with MEMP_MEM_MALLOC, use 1 instead */
+#define MEMP_OVERFLOW_CHECK 1
+#endif
+
+#if MEMP_SANITY_CHECK && !MEMP_MEM_MALLOC
+/**
+ * Check that memp-lists don't form a circle, using "Floyd's cycle-finding algorithm".
+ */
+static int
+memp_sanity(const struct memp_desc *desc)
+{
+  struct memp *t, *h;
+
+  t = *desc->tab;
+  if (t != NULL) {
+    for (h = t->next; (t != NULL) && (h != NULL); t = t->next,
+         h = ((h->next != NULL) ? h->next->next : NULL)) {
+      if (t == h) {
+        return 0;
+      }
+    }
+  }
+
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK && !MEMP_MEM_MALLOC */
+
+#if MEMP_OVERFLOW_CHECK
+/**
+ * Check if a memp element was victim of an overflow or underflow
+ * (e.g. the restricted area after/before it has been altered)
+ *
+ * @param p the memp element to check
+ * @param desc the pool p comes from
+ */
+static void
+memp_overflow_check_element(struct memp *p, const struct memp_desc *desc)
+{
+  mem_overflow_check_raw((u8_t *)p + MEMP_SIZE, desc->size, "pool ", desc->desc);
+}
+
+/**
+ * Initialize the restricted area of on memp element.
+ */
+static void
+memp_overflow_init_element(struct memp *p, const struct memp_desc *desc)
+{
+  mem_overflow_init_raw((u8_t *)p + MEMP_SIZE, desc->size);
+}
+
+#if MEMP_OVERFLOW_CHECK >= 2
+/**
+ * Do an overflow check for all elements in every pool.
+ *
+ * @see memp_overflow_check_element for a description of the check
+ */
+static void
+memp_overflow_check_all(void)
+{
+  u16_t i, j;
+  struct memp *p;
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+
+  for (i = 0; i < MEMP_MAX; ++i) {
+    p = (struct memp *)LWIP_MEM_ALIGN(memp_pools[i]->base);
+    for (j = 0; j < memp_pools[i]->num; ++j) {
+      memp_overflow_check_element(p, memp_pools[i]);
+      p = LWIP_ALIGNMENT_CAST(struct memp *, ((u8_t *)p + MEMP_SIZE + memp_pools[i]->size + MEM_SANITY_REGION_AFTER_ALIGNED));
+    }
+  }
+  SYS_ARCH_UNPROTECT(old_level);
+}
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+#endif /* MEMP_OVERFLOW_CHECK */
+
+/**
+ * Initialize custom memory pool.
+ * Related functions: memp_malloc_pool, memp_free_pool
+ *
+ * @param desc pool to initialize
+ */
+void
+memp_init_pool(const struct memp_desc *desc)
+{
+#if MEMP_MEM_MALLOC
+  LWIP_UNUSED_ARG(desc);
+#else
+  int i;
+  struct memp *memp;
+
+  *desc->tab = NULL;
+  memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
+#if MEMP_MEM_INIT
+  /* force memset on pool memory */
+  memset(memp, 0, (size_t)desc->num * (MEMP_SIZE + desc->size
+#if MEMP_OVERFLOW_CHECK
+                                       + MEM_SANITY_REGION_AFTER_ALIGNED
+#endif
+                                      ));
+#endif
+  /* create a linked list of memp elements */
+  for (i = 0; i < desc->num; ++i) {
+    memp->next = *desc->tab;
+    *desc->tab = memp;
+#if MEMP_OVERFLOW_CHECK
+    memp_overflow_init_element(memp, desc);
+#endif /* MEMP_OVERFLOW_CHECK */
+    /* cast through void* to get rid of alignment warnings */
+    memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
+#if MEMP_OVERFLOW_CHECK
+                                   + MEM_SANITY_REGION_AFTER_ALIGNED
+#endif
+                                  );
+  }
+#if MEMP_STATS
+  desc->stats->avail = desc->num;
+#endif /* MEMP_STATS */
+#endif /* !MEMP_MEM_MALLOC */
+
+#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
+  desc->stats->name  = desc->desc;
+#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
+}
+
+/**
+ * Initializes lwIP built-in pools.
+ * Related functions: memp_malloc, memp_free
+ *
+ * Carves out memp_memory into linked lists for each pool-type.
+ */
+void
+memp_init(void)
+{
+  u16_t i;
+
+  /* for every pool: */
+  for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
+    memp_init_pool(memp_pools[i]);
+
+#if LWIP_STATS && MEMP_STATS
+    lwip_stats.memp[i] = memp_pools[i]->stats;
+#endif
+  }
+
+#if MEMP_OVERFLOW_CHECK >= 2
+  /* check everything a first time to see if it worked */
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+}
+
+static void *
+#if !MEMP_OVERFLOW_CHECK
+do_memp_malloc_pool(const struct memp_desc *desc)
+#else
+do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
+#endif
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+#if MEMP_MEM_MALLOC
+  memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
+  SYS_ARCH_PROTECT(old_level);
+#else /* MEMP_MEM_MALLOC */
+  SYS_ARCH_PROTECT(old_level);
+
+  memp = *desc->tab;
+#endif /* MEMP_MEM_MALLOC */
+
+  if (memp != NULL) {
+#if !MEMP_MEM_MALLOC
+#if MEMP_OVERFLOW_CHECK == 1
+    memp_overflow_check_element(memp, desc);
+#endif /* MEMP_OVERFLOW_CHECK */
+
+    *desc->tab = memp->next;
+#if MEMP_OVERFLOW_CHECK
+    memp->next = NULL;
+#endif /* MEMP_OVERFLOW_CHECK */
+#endif /* !MEMP_MEM_MALLOC */
+#if MEMP_OVERFLOW_CHECK
+    memp->file = file;
+    memp->line = line;
+#if MEMP_MEM_MALLOC
+    memp_overflow_init_element(memp, desc);
+#endif /* MEMP_MEM_MALLOC */
+#endif /* MEMP_OVERFLOW_CHECK */
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+                ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0);
+#if MEMP_STATS
+    desc->stats->used++;
+    if (desc->stats->used > desc->stats->max) {
+      desc->stats->max = desc->stats->used;
+    }
+#endif
+    SYS_ARCH_UNPROTECT(old_level);
+    /* cast through u8_t* to get rid of alignment warnings */
+    return ((u8_t *)memp + MEMP_SIZE);
+  } else {
+#if MEMP_STATS
+    desc->stats->err++;
+#endif
+    SYS_ARCH_UNPROTECT(old_level);
+    LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
+  }
+
+  return NULL;
+}
+
+/**
+ * Get an element from a custom pool.
+ *
+ * @param desc the pool to get an element from
+ *
+ * @return a pointer to the allocated memory or a NULL pointer on error
+ */
+void *
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc_pool(const struct memp_desc *desc)
+#else
+memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
+#endif
+{
+  LWIP_ASSERT("invalid pool desc", desc != NULL);
+  if (desc == NULL) {
+    return NULL;
+  }
+
+#if !MEMP_OVERFLOW_CHECK
+  return do_memp_malloc_pool(desc);
+#else
+  return do_memp_malloc_pool_fn(desc, file, line);
+#endif
+}
+
+/**
+ * Get an element from a specific pool.
+ *
+ * @param type the pool to get an element from
+ *
+ * @return a pointer to the allocated memory or a NULL pointer on error
+ */
+void *
+#if !MEMP_OVERFLOW_CHECK
+memp_malloc(memp_t type)
+#else
+memp_malloc_fn(memp_t type, const char *file, const int line)
+#endif
+{
+  void *memp;
+  LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
+
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+
+#if !MEMP_OVERFLOW_CHECK
+  memp = do_memp_malloc_pool(memp_pools[type]);
+#else
+  memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
+#endif
+
+  return memp;
+}
+
+static void
+do_memp_free_pool(const struct memp_desc *desc, void *mem)
+{
+  struct memp *memp;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("memp_free: mem properly aligned",
+              ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
+
+  /* cast through void* to get rid of alignment warnings */
+  memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
+
+  SYS_ARCH_PROTECT(old_level);
+
+#if MEMP_OVERFLOW_CHECK == 1
+  memp_overflow_check_element(memp, desc);
+#endif /* MEMP_OVERFLOW_CHECK */
+
+#if MEMP_STATS
+  desc->stats->used--;
+#endif
+
+#if MEMP_MEM_MALLOC
+  LWIP_UNUSED_ARG(desc);
+  SYS_ARCH_UNPROTECT(old_level);
+  mem_free(memp);
+#else /* MEMP_MEM_MALLOC */
+  memp->next = *desc->tab;
+  *desc->tab = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity(desc));
+#endif /* MEMP_SANITY_CHECK */
+
+  SYS_ARCH_UNPROTECT(old_level);
+#endif /* !MEMP_MEM_MALLOC */
+}
+
+/**
+ * Put a custom pool element back into its pool.
+ *
+ * @param desc the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free_pool(const struct memp_desc *desc, void *mem)
+{
+  LWIP_ASSERT("invalid pool desc", desc != NULL);
+  if ((desc == NULL) || (mem == NULL)) {
+    return;
+  }
+
+  do_memp_free_pool(desc, mem);
+}
+
+/**
+ * Put an element back into its pool.
+ *
+ * @param type the pool where to put mem
+ * @param mem the memp element to free
+ */
+void
+memp_free(memp_t type, void *mem)
+{
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+  struct memp *old_first;
+#endif
+
+  LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
+
+  if (mem == NULL) {
+    return;
+  }
+
+#if MEMP_OVERFLOW_CHECK >= 2
+  memp_overflow_check_all();
+#endif /* MEMP_OVERFLOW_CHECK >= 2 */
+
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+  old_first = *memp_pools[type]->tab;
+#endif
+
+  do_memp_free_pool(memp_pools[type], mem);
+
+#ifdef LWIP_HOOK_MEMP_AVAILABLE
+  if (old_first == NULL) {
+    LWIP_HOOK_MEMP_AVAILABLE(type);
+  }
+#endif
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/netif.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/netif.c
new file mode 100644
index 000000000..15200a274
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/netif.c
@@ -0,0 +1,1795 @@
+/**
+ * @file
+ * lwIP network interface abstraction
+ *
+ * @defgroup netif Network interface (NETIF)
+ * @ingroup callbackstyle_api
+ *
+ * @defgroup netif_ip4 IPv4 address handling
+ * @ingroup netif
+ *
+ * @defgroup netif_ip6 IPv6 address handling
+ * @ingroup netif
+ *
+ * @defgroup netif_cd Client data handling
+ * Store data (void*) on a netif for application usage.
+ * @see @ref LWIP_NUM_NETIF_CLIENT_DATA
+ * @ingroup netif
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ */
+
+#include "lwip/opt.h"
+
+#include <string.h> /* memset */
+#include <stdlib.h> /* atoi */
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/udp.h"
+#include "lwip/priv/raw_priv.h"
+#include "lwip/snmp.h"
+#include "lwip/igmp.h"
+#include "lwip/etharp.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/ip.h"
+#if ENABLE_LOOPBACK
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+#include "lwip/tcpip.h"
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#include "netif/ethernet.h"
+
+#if LWIP_AUTOIP
+#include "lwip/autoip.h"
+#endif /* LWIP_AUTOIP */
+#if LWIP_DHCP
+#include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+#if LWIP_IPV6_DHCP6
+#include "lwip/dhcp6.h"
+#endif /* LWIP_IPV6_DHCP6 */
+#if LWIP_IPV6_MLD
+#include "lwip/mld6.h"
+#endif /* LWIP_IPV6_MLD */
+#if LWIP_IPV6
+#include "lwip/nd6.h"
+#endif
+
+#if LWIP_NETIF_STATUS_CALLBACK
+#define NETIF_STATUS_CALLBACK(n) do{ if (n->status_callback) { (n->status_callback)(n); }}while(0)
+#else
+#define NETIF_STATUS_CALLBACK(n)
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_LINK_CALLBACK
+#define NETIF_LINK_CALLBACK(n) do{ if (n->link_callback) { (n->link_callback)(n); }}while(0)
+#else
+#define NETIF_LINK_CALLBACK(n)
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+static netif_ext_callback_t *ext_callback;
+#endif
+
+#if !LWIP_SINGLE_NETIF
+struct netif *netif_list;
+#endif /* !LWIP_SINGLE_NETIF */
+struct netif *netif_default;
+
+#define netif_index_to_num(index)   ((index) - 1)
+static u8_t netif_num;
+
+#if LWIP_NUM_NETIF_CLIENT_DATA > 0
+static u8_t netif_client_id;
+#endif
+
+#define NETIF_REPORT_TYPE_IPV4  0x01
+#define NETIF_REPORT_TYPE_IPV6  0x02
+static void netif_issue_reports(struct netif *netif, u8_t report_type);
+
+#if LWIP_IPV6
+static err_t netif_null_output_ip6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr);
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+static err_t netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4 */
+
+#if LWIP_HAVE_LOOPIF
+#if LWIP_IPV4
+static err_t netif_loop_output_ipv4(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr);
+#endif
+#if LWIP_IPV6
+static err_t netif_loop_output_ipv6(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr);
+#endif
+
+
+static struct netif loop_netif;
+
+/**
+ * Initialize a lwip network interface structure for a loopback interface
+ *
+ * @param netif the lwip network interface structure for this loopif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ */
+static err_t
+netif_loopif_init(struct netif *netif)
+{
+  LWIP_ASSERT("netif_loopif_init: invalid netif", netif != NULL);
+
+  /* initialize the snmp variables and counters inside the struct netif
+   * ifSpeed: no assumption can be made!
+   */
+  MIB2_INIT_NETIF(netif, snmp_ifType_softwareLoopback, 0);
+
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+#if LWIP_IPV4
+  netif->output = netif_loop_output_ipv4;
+#endif
+#if LWIP_IPV6
+  netif->output_ip6 = netif_loop_output_ipv6;
+#endif
+#if LWIP_LOOPIF_MULTICAST
+  netif_set_flags(netif, NETIF_FLAG_IGMP);
+#endif
+  NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_DISABLE_ALL);
+  return ERR_OK;
+}
+#endif /* LWIP_HAVE_LOOPIF */
+
+void
+netif_init(void)
+{
+#if LWIP_HAVE_LOOPIF
+#if LWIP_IPV4
+#define LOOPIF_ADDRINIT &loop_ipaddr, &loop_netmask, &loop_gw,
+  ip4_addr_t loop_ipaddr, loop_netmask, loop_gw;
+  IP4_ADDR(&loop_gw, 127, 0, 0, 1);
+  IP4_ADDR(&loop_ipaddr, 127, 0, 0, 1);
+  IP4_ADDR(&loop_netmask, 255, 0, 0, 0);
+#else /* LWIP_IPV4 */
+#define LOOPIF_ADDRINIT
+#endif /* LWIP_IPV4 */
+
+#if NO_SYS
+  netif_add(&loop_netif, LOOPIF_ADDRINIT NULL, netif_loopif_init, ip_input);
+#else  /* NO_SYS */
+  netif_add(&loop_netif, LOOPIF_ADDRINIT NULL, netif_loopif_init, tcpip_input);
+#endif /* NO_SYS */
+
+#if LWIP_IPV6
+  IP_ADDR6_HOST(loop_netif.ip6_addr, 0, 0, 0, 0x00000001UL);
+  loop_netif.ip6_addr_state[0] = IP6_ADDR_VALID;
+#endif /* LWIP_IPV6 */
+
+  netif_set_link_up(&loop_netif);
+  netif_set_up(&loop_netif);
+
+#endif /* LWIP_HAVE_LOOPIF */
+}
+
+/**
+ * @ingroup lwip_nosys
+ * Forwards a received packet for input processing with
+ * ethernet_input() or ip_input() depending on netif flags.
+ * Don't call directly, pass to netif_add() and call
+ * netif->input().
+ * Only works if the netif driver correctly sets
+ * NETIF_FLAG_ETHARP and/or NETIF_FLAG_ETHERNET flag!
+ */
+err_t
+netif_input(struct pbuf *p, struct netif *inp)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("netif_input: invalid pbuf", p != NULL);
+  LWIP_ASSERT("netif_input: invalid netif", inp != NULL);
+
+#if LWIP_ETHERNET
+  if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
+    return ethernet_input(p, inp);
+  } else
+#endif /* LWIP_ETHERNET */
+    return ip_input(p, inp);
+}
+
+/**
+ * @ingroup netif
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * Same as @ref netif_add but without IPv4 addresses
+ */
+struct netif *
+netif_add_noaddr(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input)
+{
+  return netif_add(netif,
+#if LWIP_IPV4
+                   NULL, NULL, NULL,
+#endif /* LWIP_IPV4*/
+                   state, init, input);
+}
+
+/**
+ * @ingroup netif
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.\n
+ * It is recommended to use a function that passes the input directly
+ * to the stack (netif_input(), NO_SYS=1 mode) or via sending a
+ * message to TCPIP thread (tcpip_input(), NO_SYS=0 mode).\n
+ * These functions use netif flags NETIF_FLAG_ETHARP and NETIF_FLAG_ETHERNET
+ * to decide whether to forward to ethernet_input() or ip_input().
+ * In other words, the functions only work when the netif
+ * driver is implemented correctly!\n
+ * Most members of struct netif should be be initialized by the
+ * netif init function = netif driver (init parameter of this function).\n
+ * IPv6: Don't forget to call netif_create_ip6_linklocal_address() after
+ * setting the MAC address in struct netif.hwaddr
+ * (IPv6 requires a link-local address).
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif,
+#if LWIP_IPV4
+          const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+          void *state, netif_init_fn init, netif_input_fn input)
+{
+#if LWIP_IPV6
+  s8_t i;
+#endif
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_SINGLE_NETIF
+  if (netif_default != NULL) {
+    LWIP_ASSERT("single netif already set", 0);
+    return NULL;
+  }
+#endif
+
+  LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
+  LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
+
+#if LWIP_IPV4
+  if (ipaddr == NULL) {
+    ipaddr = ip_2_ip4(IP4_ADDR_ANY);
+  }
+  if (netmask == NULL) {
+    netmask = ip_2_ip4(IP4_ADDR_ANY);
+  }
+  if (gw == NULL) {
+    gw = ip_2_ip4(IP4_ADDR_ANY);
+  }
+
+  /* reset new interface configuration state */
+  ip_addr_set_zero_ip4(&netif->ip_addr);
+  ip_addr_set_zero_ip4(&netif->netmask);
+  ip_addr_set_zero_ip4(&netif->gw);
+  netif->output = netif_null_output_ip4;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    ip_addr_set_zero_ip6(&netif->ip6_addr[i]);
+    netif->ip6_addr_state[i] = IP6_ADDR_INVALID;
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+    netif->ip6_addr_valid_life[i] = IP6_ADDR_LIFE_STATIC;
+    netif->ip6_addr_pref_life[i] = IP6_ADDR_LIFE_STATIC;
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+  }
+  netif->output_ip6 = netif_null_output_ip6;
+#endif /* LWIP_IPV6 */
+  NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
+  netif->mtu = 0;
+  netif->flags = 0;
+#ifdef netif_get_client_data
+  memset(netif->client_data, 0, sizeof(netif->client_data));
+#endif /* LWIP_NUM_NETIF_CLIENT_DATA */
+#if LWIP_IPV6
+#if LWIP_IPV6_AUTOCONFIG
+  /* IPv6 address autoconfiguration not enabled by default */
+  netif->ip6_autoconfig_enabled = 0;
+#endif /* LWIP_IPV6_AUTOCONFIG */
+  nd6_restart_netif(netif);
+#endif /* LWIP_IPV6 */
+#if LWIP_NETIF_STATUS_CALLBACK
+  netif->status_callback = NULL;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  netif->link_callback = NULL;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_IGMP
+  netif->igmp_mac_filter = NULL;
+#endif /* LWIP_IGMP */
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+  netif->mld_mac_filter = NULL;
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+#if ENABLE_LOOPBACK
+  netif->loop_first = NULL;
+  netif->loop_last = NULL;
+#endif /* ENABLE_LOOPBACK */
+
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netif_num;
+  netif->input = input;
+
+  NETIF_RESET_HINTS(netif);
+#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
+  netif->loop_cnt_current = 0;
+#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
+
+#if LWIP_IPV4
+  netif_set_addr(netif, ipaddr, netmask, gw);
+#endif /* LWIP_IPV4 */
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+#if LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES
+  /* Initialize the MTU for IPv6 to the one set by the netif driver.
+     This can be updated later by RA. */
+  netif->mtu6 = netif->mtu;
+#endif /* LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES */
+
+#if !LWIP_SINGLE_NETIF
+  /* Assign a unique netif number in the range [0..254], so that (num+1) can
+     serve as an interface index that fits in a u8_t.
+     We assume that the new netif has not yet been added to the list here.
+     This algorithm is O(n^2), but that should be OK for lwIP.
+     */
+  {
+    struct netif *netif2;
+    int num_netifs;
+    do {
+      if (netif->num == 255) {
+        netif->num = 0;
+      }
+      num_netifs = 0;
+      for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
+        LWIP_ASSERT("netif already added", netif2 != netif);
+        num_netifs++;
+        LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
+        if (netif2->num == netif->num) {
+          netif->num++;
+          break;
+        }
+      }
+    } while (netif2 != NULL);
+  }
+  if (netif->num == 254) {
+    netif_num = 0;
+  } else {
+    netif_num = (u8_t)(netif->num + 1);
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+#endif /* "LWIP_SINGLE_NETIF */
+  mib2_netif_added(netif);
+
+#if LWIP_IGMP
+  /* start IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_start(netif);
+  }
+#endif /* LWIP_IGMP */
+
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP",
+                            netif->name[0], netif->name[1]));
+#if LWIP_IPV4
+  LWIP_DEBUGF(NETIF_DEBUG, (" addr "));
+  ip4_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip4_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip4_addr_debug_print(NETIF_DEBUG, gw);
+#endif /* LWIP_IPV4 */
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+
+  netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
+
+  return netif;
+}
+
+static void
+netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+#if LWIP_TCP
+  tcp_netif_ip_addr_changed(old_addr, new_addr);
+#endif /* LWIP_TCP */
+#if LWIP_UDP
+  udp_netif_ip_addr_changed(old_addr, new_addr);
+#endif /* LWIP_UDP */
+#if LWIP_RAW
+  raw_netif_ip_addr_changed(old_addr, new_addr);
+#endif /* LWIP_RAW */
+}
+
+#if LWIP_IPV4
+static int
+netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
+{
+  LWIP_ASSERT("invalid pointer", ipaddr != NULL);
+  LWIP_ASSERT("invalid pointer", old_addr != NULL);
+
+  /* address is actually being changed? */
+  if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
+    ip_addr_t new_addr;
+    *ip_2_ip4(&new_addr) = *ipaddr;
+    IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
+
+    ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
+
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
+    netif_do_ip_addr_changed(old_addr, &new_addr);
+
+    mib2_remove_ip4(netif);
+    mib2_remove_route_ip4(0, netif);
+    /* set new IP address to netif */
+    ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
+    IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
+    mib2_add_ip4(netif);
+    mib2_add_route_ip4(0, netif);
+
+    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
+
+    NETIF_STATUS_CALLBACK(netif);
+    return 1; /* address changed */
+  }
+  return 0; /* address unchanged */
+}
+
+/**
+ * @ingroup netif_ip4
+ * Change the IP address of a network interface
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ *
+ * @note call netif_set_addr() if you also want to change netmask and
+ * default gateway
+ */
+void
+netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr)
+{
+  ip_addr_t old_addr;
+
+  LWIP_ERROR("netif_set_ipaddr: invalid netif", netif != NULL, return);
+
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+    ipaddr = IP4_ADDR_ANY4;
+  }
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    netif_ext_callback_args_t args;
+    args.ipv4_changed.old_address = &old_addr;
+    netif_invoke_ext_callback(netif, LWIP_NSC_IPV4_ADDRESS_CHANGED, &args);
+#endif
+  }
+}
+
+static int
+netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
+{
+  /* address is actually being changed? */
+  if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    LWIP_ASSERT("invalid pointer", old_nm != NULL);
+    ip_addr_copy(*old_nm, *netif_ip_netmask4(netif));
+#else
+    LWIP_UNUSED_ARG(old_nm);
+#endif
+    mib2_remove_route_ip4(0, netif);
+    /* set new netmask to netif */
+    ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
+    IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4);
+    mib2_add_route_ip4(0, netif);
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                netif->name[0], netif->name[1],
+                ip4_addr1_16(netif_ip4_netmask(netif)),
+                ip4_addr2_16(netif_ip4_netmask(netif)),
+                ip4_addr3_16(netif_ip4_netmask(netif)),
+                ip4_addr4_16(netif_ip4_netmask(netif))));
+    return 1; /* netmask changed */
+  }
+  return 0; /* netmask unchanged */
+}
+
+/**
+ * @ingroup netif_ip4
+ * Change the netmask of a network interface
+ *
+ * @param netif the network interface to change
+ * @param netmask the new netmask
+ *
+ * @note call netif_set_addr() if you also want to change ip address and
+ * default gateway
+ */
+void
+netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask)
+{
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+  ip_addr_t old_nm_val;
+  ip_addr_t *old_nm = &old_nm_val;
+#else
+  ip_addr_t *old_nm = NULL;
+#endif
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_netmask: invalid netif", netif != NULL, return);
+
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (netmask == NULL) {
+    netmask = IP4_ADDR_ANY4;
+  }
+
+  if (netif_do_set_netmask(netif, netmask, old_nm)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    netif_ext_callback_args_t args;
+    args.ipv4_changed.old_netmask = old_nm;
+    netif_invoke_ext_callback(netif, LWIP_NSC_IPV4_NETMASK_CHANGED, &args);
+#endif
+  }
+}
+
+static int
+netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
+{
+  /* address is actually being changed? */
+  if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    LWIP_ASSERT("invalid pointer", old_gw != NULL);
+    ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
+#else
+    LWIP_UNUSED_ARG(old_gw);
+#endif
+
+    ip4_addr_set(ip_2_ip4(&netif->gw), gw);
+    IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4);
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                netif->name[0], netif->name[1],
+                ip4_addr1_16(netif_ip4_gw(netif)),
+                ip4_addr2_16(netif_ip4_gw(netif)),
+                ip4_addr3_16(netif_ip4_gw(netif)),
+                ip4_addr4_16(netif_ip4_gw(netif))));
+    return 1; /* gateway changed */
+  }
+  return 0; /* gateway unchanged */
+}
+
+/**
+ * @ingroup netif_ip4
+ * Change the default gateway for a network interface
+ *
+ * @param netif the network interface to change
+ * @param gw the new default gateway
+ *
+ * @note call netif_set_addr() if you also want to change ip address and netmask
+ */
+void
+netif_set_gw(struct netif *netif, const ip4_addr_t *gw)
+{
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+  ip_addr_t old_gw_val;
+  ip_addr_t *old_gw = &old_gw_val;
+#else
+  ip_addr_t *old_gw = NULL;
+#endif
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_gw: invalid netif", netif != NULL, return);
+
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (gw == NULL) {
+    gw = IP4_ADDR_ANY4;
+  }
+
+  if (netif_do_set_gw(netif, gw, old_gw)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    netif_ext_callback_args_t args;
+    args.ipv4_changed.old_gw = old_gw;
+    netif_invoke_ext_callback(netif, LWIP_NSC_IPV4_GATEWAY_CHANGED, &args);
+#endif
+  }
+}
+
+/**
+ * @ingroup netif_ip4
+ * Change IP address configuration for a network interface (including netmask
+ * and default gateway).
+ *
+ * @param netif the network interface to change
+ * @param ipaddr the new IP address
+ * @param netmask the new netmask
+ * @param gw the new default gateway
+ */
+void
+netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
+               const ip4_addr_t *gw)
+{
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+  netif_nsc_reason_t change_reason = LWIP_NSC_NONE;
+  netif_ext_callback_args_t cb_args;
+  ip_addr_t old_nm_val;
+  ip_addr_t old_gw_val;
+  ip_addr_t *old_nm = &old_nm_val;
+  ip_addr_t *old_gw = &old_gw_val;
+#else
+  ip_addr_t *old_nm = NULL;
+  ip_addr_t *old_gw = NULL;
+#endif
+  ip_addr_t old_addr;
+  int remove;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+    ipaddr = IP4_ADDR_ANY4;
+  }
+  if (netmask == NULL) {
+    netmask = IP4_ADDR_ANY4;
+  }
+  if (gw == NULL) {
+    gw = IP4_ADDR_ANY4;
+  }
+
+  remove = ip4_addr_isany(ipaddr);
+  if (remove) {
+    /* when removing an address, we have to remove it *before* changing netmask/gw
+       to ensure that tcp RST segment can be sent correctly */
+    if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+      change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
+      cb_args.ipv4_changed.old_address = &old_addr;
+#endif
+    }
+  }
+  if (netif_do_set_netmask(netif, netmask, old_nm)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
+    cb_args.ipv4_changed.old_netmask = old_nm;
+#endif
+  }
+  if (netif_do_set_gw(netif, gw, old_gw)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
+    cb_args.ipv4_changed.old_gw = old_gw;
+#endif
+  }
+  if (!remove) {
+    /* set ipaddr last to ensure netmask/gw have been set when status callback is called */
+    if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+      change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
+      cb_args.ipv4_changed.old_address = &old_addr;
+#endif
+    }
+  }
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+  if (change_reason != LWIP_NSC_NONE) {
+    change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
+    netif_invoke_ext_callback(netif, change_reason, &cb_args);
+  }
+#endif
+}
+#endif /* LWIP_IPV4*/
+
+/**
+ * @ingroup netif
+ * Remove a network interface from the list of lwIP netifs.
+ *
+ * @param netif the network interface to remove
+ */
+void
+netif_remove(struct netif *netif)
+{
+#if LWIP_IPV6
+  int i;
+#endif
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif == NULL) {
+    return;
+  }
+
+  netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_REMOVED, NULL);
+
+#if LWIP_IPV4
+  if (!ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+    netif_do_ip_addr_changed(netif_ip_addr4(netif), NULL);
+  }
+
+#if LWIP_IGMP
+  /* stop IGMP processing */
+  if (netif->flags & NETIF_FLAG_IGMP) {
+    igmp_stop(netif);
+  }
+#endif /* LWIP_IGMP */
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+  for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) {
+      netif_do_ip_addr_changed(netif_ip_addr6(netif, i), NULL);
+    }
+  }
+#if LWIP_IPV6_MLD
+  /* stop MLD processing */
+  mld6_stop(netif);
+#endif /* LWIP_IPV6_MLD */
+#endif /* LWIP_IPV6 */
+  if (netif_is_up(netif)) {
+    /* set netif down before removing (call callback function) */
+    netif_set_down(netif);
+  }
+
+  mib2_remove_ip4(netif);
+
+  /* this netif is default? */
+  if (netif_default == netif) {
+    /* reset default netif */
+    netif_set_default(NULL);
+  }
+#if !LWIP_SINGLE_NETIF
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+  } else {
+    /*  look for netif further down the list */
+    struct netif *tmp_netif;
+    NETIF_FOREACH(tmp_netif) {
+      if (tmp_netif->next == netif) {
+        tmp_netif->next = netif->next;
+        break;
+      }
+    }
+    if (tmp_netif == NULL) {
+      return; /* netif is not on the list */
+    }
+  }
+#endif /* !LWIP_SINGLE_NETIF */
+  mib2_netif_removed(netif);
+#if LWIP_NETIF_REMOVE_CALLBACK
+  if (netif->remove_callback) {
+    netif->remove_callback(netif);
+  }
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+/**
+ * @ingroup netif
+ * Set a network interface as the default network interface
+ * (used to output all packets for which no specific route is found)
+ *
+ * @param netif the default network interface
+ */
+void
+netif_set_default(struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif == NULL) {
+    /* remove default route */
+    mib2_remove_route_ip4(1, netif);
+  } else {
+    /* install default route */
+    mib2_add_route_ip4(1, netif);
+  }
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+                            netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * @ingroup netif
+ * Bring an interface up, available for processing
+ * traffic.
+ */
+void
+netif_set_up(struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
+
+  if (!(netif->flags & NETIF_FLAG_UP)) {
+    netif_set_flags(netif, NETIF_FLAG_UP);
+
+    MIB2_COPY_SYSUPTIME_TO(&netif->ts);
+
+    NETIF_STATUS_CALLBACK(netif);
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    {
+      netif_ext_callback_args_t args;
+      args.status_changed.state = 1;
+      netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
+    }
+#endif
+
+    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
+#if LWIP_IPV6
+    nd6_restart_netif(netif);
+#endif /* LWIP_IPV6 */
+  }
+}
+
+/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
+ */
+static void
+netif_issue_reports(struct netif *netif, u8_t report_type)
+{
+  LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
+
+  /* Only send reports when both link and admin states are up */
+  if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
+      !(netif->flags & NETIF_FLAG_UP)) {
+    return;
+  }
+
+#if LWIP_IPV4
+  if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
+      !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
+#if LWIP_ARP
+    /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
+    if (netif->flags & (NETIF_FLAG_ETHARP)) {
+      etharp_gratuitous(netif);
+    }
+#endif /* LWIP_ARP */
+
+#if LWIP_IGMP
+    /* resend IGMP memberships */
+    if (netif->flags & NETIF_FLAG_IGMP) {
+      igmp_report_groups(netif);
+    }
+#endif /* LWIP_IGMP */
+  }
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+  if (report_type & NETIF_REPORT_TYPE_IPV6) {
+#if LWIP_IPV6_MLD
+    /* send mld memberships */
+    mld6_report_groups(netif);
+#endif /* LWIP_IPV6_MLD */
+  }
+#endif /* LWIP_IPV6 */
+}
+
+/**
+ * @ingroup netif
+ * Bring an interface down, disabling any traffic processing.
+ */
+void
+netif_set_down(struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
+
+  if (netif->flags & NETIF_FLAG_UP) {
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    {
+      netif_ext_callback_args_t args;
+      args.status_changed.state = 0;
+      netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
+    }
+#endif
+
+    netif_clear_flags(netif, NETIF_FLAG_UP);
+    MIB2_COPY_SYSUPTIME_TO(&netif->ts);
+
+#if LWIP_IPV4 && LWIP_ARP
+    if (netif->flags & NETIF_FLAG_ETHARP) {
+      etharp_cleanup_netif(netif);
+    }
+#endif /* LWIP_IPV4 && LWIP_ARP */
+
+#if LWIP_IPV6
+    nd6_cleanup_netif(netif);
+#endif /* LWIP_IPV6 */
+
+    NETIF_STATUS_CALLBACK(netif);
+  }
+}
+
+#if LWIP_NETIF_STATUS_CALLBACK
+/**
+ * @ingroup netif
+ * Set callback to be called when interface is brought up/down or address is changed while up
+ */
+void
+netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif) {
+    netif->status_callback = status_callback;
+  }
+}
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+
+#if LWIP_NETIF_REMOVE_CALLBACK
+/**
+ * @ingroup netif
+ * Set callback to be called when the interface has been removed
+ */
+void
+netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif) {
+    netif->remove_callback = remove_callback;
+  }
+}
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+
+/**
+ * @ingroup netif
+ * Called by a driver when its link goes up
+ */
+void
+netif_set_link_up(struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
+
+  if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
+    netif_set_flags(netif, NETIF_FLAG_LINK_UP);
+
+#if LWIP_DHCP
+    dhcp_network_changed(netif);
+#endif /* LWIP_DHCP */
+
+#if LWIP_AUTOIP
+    autoip_network_changed(netif);
+#endif /* LWIP_AUTOIP */
+
+    netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
+#if LWIP_IPV6
+    nd6_restart_netif(netif);
+#endif /* LWIP_IPV6 */
+
+    NETIF_LINK_CALLBACK(netif);
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    {
+      netif_ext_callback_args_t args;
+      args.link_changed.state = 1;
+      netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
+    }
+#endif
+  }
+}
+
+/**
+ * @ingroup netif
+ * Called by a driver when its link goes down
+ */
+void
+netif_set_link_down(struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
+
+  if (netif->flags & NETIF_FLAG_LINK_UP) {
+    netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
+    NETIF_LINK_CALLBACK(netif);
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    {
+      netif_ext_callback_args_t args;
+      args.link_changed.state = 0;
+      netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
+    }
+#endif
+  }
+}
+
+#if LWIP_NETIF_LINK_CALLBACK
+/**
+ * @ingroup netif
+ * Set callback to be called when link is brought up/down
+ */
+void
+netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif) {
+    netif->link_callback = link_callback;
+  }
+}
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if ENABLE_LOOPBACK
+/**
+ * @ingroup netif
+ * Send an IP packet to be received on the same netif (loopif-like).
+ * The pbuf is simply copied and handed back to netif->input.
+ * In multithreaded mode, this is done directly since netif->input must put
+ * the packet on a queue.
+ * In callback mode, the packet is put on an internal queue and is fed to
+ * netif->input by netif_poll().
+ *
+ * @param netif the lwip network interface structure
+ * @param p the (IP) packet to 'send'
+ * @return ERR_OK if the packet has been sent
+ *         ERR_MEM if the pbuf used to copy the packet couldn't be allocated
+ */
+err_t
+netif_loop_output(struct netif *netif, struct pbuf *p)
+{
+  struct pbuf *r;
+  err_t err;
+  struct pbuf *last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u16_t clen = 0;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+  /* If we have a loopif, SNMP counters are adjusted for it,
+   * if not they are adjusted for 'netif'. */
+#if MIB2_STATS
+#if LWIP_HAVE_LOOPIF
+  struct netif *stats_if = &loop_netif;
+#else /* LWIP_HAVE_LOOPIF */
+  struct netif *stats_if = netif;
+#endif /* LWIP_HAVE_LOOPIF */
+#endif /* MIB2_STATS */
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+  u8_t schedule_poll = 0;
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_ASSERT("netif_loop_output: invalid netif", netif != NULL);
+  LWIP_ASSERT("netif_loop_output: invalid pbuf", p != NULL);
+
+  /* Allocate a new pbuf */
+  r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM);
+  if (r == NULL) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards);
+    return ERR_MEM;
+  }
+#if LWIP_LOOPBACK_MAX_PBUFS
+  clen = pbuf_clen(r);
+  /* check for overflow or too many pbuf on queue */
+  if (((netif->loop_cnt_current + clen) < netif->loop_cnt_current) ||
+      ((netif->loop_cnt_current + clen) > LWIP_MIN(LWIP_LOOPBACK_MAX_PBUFS, 0xFFFF))) {
+    pbuf_free(r);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards);
+    return ERR_MEM;
+  }
+  netif->loop_cnt_current = (u16_t)(netif->loop_cnt_current + clen);
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+
+  /* Copy the whole pbuf queue p into the single pbuf r */
+  if ((err = pbuf_copy(r, p)) != ERR_OK) {
+    pbuf_free(r);
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards);
+    return err;
+  }
+
+  /* Put the packet on a linked list which gets emptied through calling
+     netif_poll(). */
+
+  /* let last point to the last pbuf in chain r */
+  for (last = r; last->next != NULL; last = last->next) {
+    /* nothing to do here, just get to the last pbuf */
+  }
+
+  SYS_ARCH_PROTECT(lev);
+  if (netif->loop_first != NULL) {
+    LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL);
+    netif->loop_last->next = r;
+    netif->loop_last = last;
+  } else {
+    netif->loop_first = r;
+    netif->loop_last = last;
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+    /* No existing packets queued, schedule poll */
+    schedule_poll = 1;
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+  }
+  SYS_ARCH_UNPROTECT(lev);
+
+  LINK_STATS_INC(link.xmit);
+  MIB2_STATS_NETIF_ADD(stats_if, ifoutoctets, p->tot_len);
+  MIB2_STATS_NETIF_INC(stats_if, ifoutucastpkts);
+
+#if LWIP_NETIF_LOOPBACK_MULTITHREADING
+  /* For multithreading environment, schedule a call to netif_poll */
+  if (schedule_poll) {
+    tcpip_try_callback((tcpip_callback_fn)netif_poll, netif);
+  }
+#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */
+
+  return ERR_OK;
+}
+
+#if LWIP_HAVE_LOOPIF
+#if LWIP_IPV4
+static err_t
+netif_loop_output_ipv4(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr)
+{
+  LWIP_UNUSED_ARG(addr);
+  return netif_loop_output(netif, p);
+}
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+static err_t
+netif_loop_output_ipv6(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr)
+{
+  LWIP_UNUSED_ARG(addr);
+  return netif_loop_output(netif, p);
+}
+#endif /* LWIP_IPV6 */
+#endif /* LWIP_HAVE_LOOPIF */
+
+
+/**
+ * Call netif_poll() in the main loop of your application. This is to prevent
+ * reentering non-reentrant functions like tcp_input(). Packets passed to
+ * netif_loop_output() are put on a list that is passed to netif->input() by
+ * netif_poll().
+ */
+void
+netif_poll(struct netif *netif)
+{
+  /* If we have a loopif, SNMP counters are adjusted for it,
+   * if not they are adjusted for 'netif'. */
+#if MIB2_STATS
+#if LWIP_HAVE_LOOPIF
+  struct netif *stats_if = &loop_netif;
+#else /* LWIP_HAVE_LOOPIF */
+  struct netif *stats_if = netif;
+#endif /* LWIP_HAVE_LOOPIF */
+#endif /* MIB2_STATS */
+  SYS_ARCH_DECL_PROTECT(lev);
+
+  LWIP_ASSERT("netif_poll: invalid netif", netif != NULL);
+
+  /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */
+  SYS_ARCH_PROTECT(lev);
+  while (netif->loop_first != NULL) {
+    struct pbuf *in, *in_end;
+#if LWIP_LOOPBACK_MAX_PBUFS
+    u8_t clen = 1;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+
+    in = in_end = netif->loop_first;
+    while (in_end->len != in_end->tot_len) {
+      LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL);
+      in_end = in_end->next;
+#if LWIP_LOOPBACK_MAX_PBUFS
+      clen++;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+    }
+#if LWIP_LOOPBACK_MAX_PBUFS
+    /* adjust the number of pbufs on queue */
+    LWIP_ASSERT("netif->loop_cnt_current underflow",
+                ((netif->loop_cnt_current - clen) < netif->loop_cnt_current));
+    netif->loop_cnt_current = (u16_t)(netif->loop_cnt_current - clen);
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+
+    /* 'in_end' now points to the last pbuf from 'in' */
+    if (in_end == netif->loop_last) {
+      /* this was the last pbuf in the list */
+      netif->loop_first = netif->loop_last = NULL;
+    } else {
+      /* pop the pbuf off the list */
+      netif->loop_first = in_end->next;
+      LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL);
+    }
+    /* De-queue the pbuf from its successors on the 'loop_' list. */
+    in_end->next = NULL;
+    SYS_ARCH_UNPROTECT(lev);
+
+    in->if_idx = netif_get_index(netif);
+
+    LINK_STATS_INC(link.recv);
+    MIB2_STATS_NETIF_ADD(stats_if, ifinoctets, in->tot_len);
+    MIB2_STATS_NETIF_INC(stats_if, ifinucastpkts);
+    /* loopback packets are always IP packets! */
+    if (ip_input(in, netif) != ERR_OK) {
+      pbuf_free(in);
+    }
+    SYS_ARCH_PROTECT(lev);
+  }
+  SYS_ARCH_UNPROTECT(lev);
+}
+
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+/**
+ * Calls netif_poll() for every netif on the netif_list.
+ */
+void
+netif_poll_all(void)
+{
+  struct netif *netif;
+  /* loop through netifs */
+  NETIF_FOREACH(netif) {
+    netif_poll(netif);
+  }
+}
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+#if LWIP_NUM_NETIF_CLIENT_DATA > 0
+/**
+ * @ingroup netif_cd
+ * Allocate an index to store data in client_data member of struct netif.
+ * Returned value is an index in mentioned array.
+ * @see LWIP_NUM_NETIF_CLIENT_DATA
+ */
+u8_t
+netif_alloc_client_data_id(void)
+{
+  u8_t result = netif_client_id;
+  netif_client_id++;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_NUM_NETIF_CLIENT_DATA > 256
+#error LWIP_NUM_NETIF_CLIENT_DATA must be <= 256
+#endif
+  LWIP_ASSERT("Increase LWIP_NUM_NETIF_CLIENT_DATA in lwipopts.h", result < LWIP_NUM_NETIF_CLIENT_DATA);
+  return (u8_t)(result + LWIP_NETIF_CLIENT_DATA_INDEX_MAX);
+}
+#endif
+
+#if LWIP_IPV6
+/**
+ * @ingroup netif_ip6
+ * Change an IPv6 address of a network interface
+ *
+ * @param netif the network interface to change
+ * @param addr_idx index of the IPv6 address
+ * @param addr6 the new IPv6 address
+ *
+ * @note call netif_ip6_addr_set_state() to set the address valid/temptative
+ */
+void
+netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("netif_ip6_addr_set: invalid netif", netif != NULL);
+  LWIP_ASSERT("netif_ip6_addr_set: invalid addr6", addr6 != NULL);
+
+  netif_ip6_addr_set_parts(netif, addr_idx, addr6->addr[0], addr6->addr[1],
+                           addr6->addr[2], addr6->addr[3]);
+}
+
+/*
+ * Change an IPv6 address of a network interface (internal version taking 4 * u32_t)
+ *
+ * @param netif the network interface to change
+ * @param addr_idx index of the IPv6 address
+ * @param i0 word0 of the new IPv6 address
+ * @param i1 word1 of the new IPv6 address
+ * @param i2 word2 of the new IPv6 address
+ * @param i3 word3 of the new IPv6 address
+ */
+void
+netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3)
+{
+  ip_addr_t old_addr;
+  ip_addr_t new_ipaddr;
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("invalid index", addr_idx < LWIP_IPV6_NUM_ADDRESSES);
+
+  ip6_addr_copy(*ip_2_ip6(&old_addr), *netif_ip6_addr(netif, addr_idx));
+  IP_SET_TYPE_VAL(old_addr, IPADDR_TYPE_V6);
+
+  /* address is actually being changed? */
+  if ((ip_2_ip6(&old_addr)->addr[0] != i0) || (ip_2_ip6(&old_addr)->addr[1] != i1) ||
+      (ip_2_ip6(&old_addr)->addr[2] != i2) || (ip_2_ip6(&old_addr)->addr[3] != i3)) {
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_ip6_addr_set: netif address being changed\n"));
+
+    IP_ADDR6(&new_ipaddr, i0, i1, i2, i3);
+    ip6_addr_assign_zone(ip_2_ip6(&new_ipaddr), IP6_UNICAST, netif);
+
+    if (ip6_addr_isvalid(netif_ip6_addr_state(netif, addr_idx))) {
+      netif_do_ip_addr_changed(netif_ip_addr6(netif, addr_idx), &new_ipaddr);
+    }
+    /* @todo: remove/readd mib2 ip6 entries? */
+
+    ip_addr_copy(netif->ip6_addr[addr_idx], new_ipaddr);
+
+    if (ip6_addr_isvalid(netif_ip6_addr_state(netif, addr_idx))) {
+      netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV6);
+      NETIF_STATUS_CALLBACK(netif);
+    }
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    {
+      netif_ext_callback_args_t args;
+      args.ipv6_set.addr_index  = addr_idx;
+      args.ipv6_set.old_address = &old_addr;
+      netif_invoke_ext_callback(netif, LWIP_NSC_IPV6_SET, &args);
+    }
+#endif
+  }
+
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IPv6 address %d of interface %c%c set to %s/0x%"X8_F"\n",
+              addr_idx, netif->name[0], netif->name[1], ip6addr_ntoa(netif_ip6_addr(netif, addr_idx)),
+              netif_ip6_addr_state(netif, addr_idx)));
+}
+
+/**
+ * @ingroup netif_ip6
+ * Change the state of an IPv6 address of a network interface
+ * (INVALID, TEMPTATIVE, PREFERRED, DEPRECATED, where TEMPTATIVE
+ * includes the number of checks done, see ip6_addr.h)
+ *
+ * @param netif the network interface to change
+ * @param addr_idx index of the IPv6 address
+ * @param state the new IPv6 address state
+ */
+void
+netif_ip6_addr_set_state(struct netif *netif, s8_t addr_idx, u8_t state)
+{
+  u8_t old_state;
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("invalid index", addr_idx < LWIP_IPV6_NUM_ADDRESSES);
+
+  old_state = netif_ip6_addr_state(netif, addr_idx);
+  /* state is actually being changed? */
+  if (old_state != state) {
+    u8_t old_valid = old_state & IP6_ADDR_VALID;
+    u8_t new_valid = state & IP6_ADDR_VALID;
+    LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_ip6_addr_set_state: netif address state being changed\n"));
+
+#if LWIP_IPV6_MLD
+    /* Reevaluate solicited-node multicast group membership. */
+    if (netif->flags & NETIF_FLAG_MLD6) {
+      nd6_adjust_mld_membership(netif, addr_idx, state);
+    }
+#endif /* LWIP_IPV6_MLD */
+
+    if (old_valid && !new_valid) {
+      /* address about to be removed by setting invalid */
+      netif_do_ip_addr_changed(netif_ip_addr6(netif, addr_idx), NULL);
+      /* @todo: remove mib2 ip6 entries? */
+    }
+    netif->ip6_addr_state[addr_idx] = state;
+
+    if (!old_valid && new_valid) {
+      /* address added by setting valid */
+      /* This is a good moment to check that the address is properly zoned. */
+      IP6_ADDR_ZONECHECK_NETIF(netif_ip6_addr(netif, addr_idx), netif);
+      /* @todo: add mib2 ip6 entries? */
+      netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV6);
+    }
+    if ((old_state & ~IP6_ADDR_TENTATIVE_COUNT_MASK) !=
+        (state     & ~IP6_ADDR_TENTATIVE_COUNT_MASK)) {
+      /* address state has changed -> call the callback function */
+      NETIF_STATUS_CALLBACK(netif);
+    }
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+    {
+      netif_ext_callback_args_t args;
+      args.ipv6_addr_state_changed.addr_index = addr_idx;
+      args.ipv6_addr_state_changed.old_state  = old_state;
+      args.ipv6_addr_state_changed.address    = netif_ip_addr6(netif, addr_idx);
+      netif_invoke_ext_callback(netif, LWIP_NSC_IPV6_ADDR_STATE_CHANGED, &args);
+    }
+#endif
+  }
+  LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IPv6 address %d of interface %c%c set to %s/0x%"X8_F"\n",
+              addr_idx, netif->name[0], netif->name[1], ip6addr_ntoa(netif_ip6_addr(netif, addr_idx)),
+              netif_ip6_addr_state(netif, addr_idx)));
+}
+
+/**
+ * Checks if a specific local address is present on the netif and returns its
+ * index. Depending on its state, it may or may not be assigned to the
+ * interface (as per RFC terminology).
+ *
+ * The given address may or may not be zoned (i.e., have a zone index other
+ * than IP6_NO_ZONE). If the address is zoned, it must have the correct zone
+ * for the given netif, or no match will be found.
+ *
+ * @param netif the netif to check
+ * @param ip6addr the IPv6 address to find
+ * @return >= 0: address found, this is its index
+ *         -1: address not found on this netif
+ */
+s8_t
+netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr)
+{
+  s8_t i;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("netif_get_ip6_addr_match: invalid netif", netif != NULL);
+  LWIP_ASSERT("netif_get_ip6_addr_match: invalid ip6addr", ip6addr != NULL);
+
+#if LWIP_IPV6_SCOPES
+  if (ip6_addr_has_zone(ip6addr) && !ip6_addr_test_zone(ip6addr, netif)) {
+    return -1; /* wrong zone, no match */
+  }
+#endif /* LWIP_IPV6_SCOPES */
+
+  for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i)) &&
+        ip6_addr_cmp_zoneless(netif_ip6_addr(netif, i), ip6addr)) {
+      return i;
+    }
+  }
+  return -1;
+}
+
+/**
+ * @ingroup netif_ip6
+ * Create a link-local IPv6 address on a netif (stored in slot 0)
+ *
+ * @param netif the netif to create the address on
+ * @param from_mac_48bit if != 0, assume hwadr is a 48-bit MAC address (std conversion)
+ *                       if == 0, use hwaddr directly as interface ID
+ */
+void
+netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit)
+{
+  u8_t i, addr_index;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("netif_create_ip6_linklocal_address: invalid netif", netif != NULL);
+
+  /* Link-local prefix. */
+  ip_2_ip6(&netif->ip6_addr[0])->addr[0] = PP_HTONL(0xfe800000ul);
+  ip_2_ip6(&netif->ip6_addr[0])->addr[1] = 0;
+
+  /* Generate interface ID. */
+  if (from_mac_48bit) {
+    /* Assume hwaddr is a 48-bit IEEE 802 MAC. Convert to EUI-64 address. Complement Group bit. */
+    ip_2_ip6(&netif->ip6_addr[0])->addr[2] = lwip_htonl((((u32_t)(netif->hwaddr[0] ^ 0x02)) << 24) |
+        ((u32_t)(netif->hwaddr[1]) << 16) |
+        ((u32_t)(netif->hwaddr[2]) << 8) |
+        (0xff));
+    ip_2_ip6(&netif->ip6_addr[0])->addr[3] = lwip_htonl((u32_t)(0xfeul << 24) |
+        ((u32_t)(netif->hwaddr[3]) << 16) |
+        ((u32_t)(netif->hwaddr[4]) << 8) |
+        (netif->hwaddr[5]));
+  } else {
+    /* Use hwaddr directly as interface ID. */
+    ip_2_ip6(&netif->ip6_addr[0])->addr[2] = 0;
+    ip_2_ip6(&netif->ip6_addr[0])->addr[3] = 0;
+
+    addr_index = 3;
+    for (i = 0; (i < 8) && (i < netif->hwaddr_len); i++) {
+      if (i == 4) {
+        addr_index--;
+      }
+      ip_2_ip6(&netif->ip6_addr[0])->addr[addr_index] |= lwip_htonl(((u32_t)(netif->hwaddr[netif->hwaddr_len - i - 1])) << (8 * (i & 0x03)));
+    }
+  }
+
+  /* Set a link-local zone. Even though the zone is implied by the owning
+   * netif, setting the zone anyway has two important conceptual advantages:
+   * 1) it avoids the need for a ton of exceptions in internal code, allowing
+   *    e.g. ip6_addr_cmp() to be used on local addresses;
+   * 2) the properly zoned address is visible externally, e.g. when any outside
+   *    code enumerates available addresses or uses one to bind a socket.
+   * Any external code unaware of address scoping is likely to just ignore the
+   * zone field, so this should not create any compatibility problems. */
+  ip6_addr_assign_zone(ip_2_ip6(&netif->ip6_addr[0]), IP6_UNICAST, netif);
+
+  /* Set address state. */
+#if LWIP_IPV6_DUP_DETECT_ATTEMPTS
+  /* Will perform duplicate address detection (DAD). */
+  netif_ip6_addr_set_state(netif, 0, IP6_ADDR_TENTATIVE);
+#else
+  /* Consider address valid. */
+  netif_ip6_addr_set_state(netif, 0, IP6_ADDR_PREFERRED);
+#endif /* LWIP_IPV6_AUTOCONFIG */
+}
+
+/**
+ * @ingroup netif_ip6
+ * This function allows for the easy addition of a new IPv6 address to an interface.
+ * It takes care of finding an empty slot and then sets the address tentative
+ * (to make sure that all the subsequent processing happens).
+ *
+ * @param netif netif to add the address on
+ * @param ip6addr address to add
+ * @param chosen_idx if != NULL, the chosen IPv6 address index will be stored here
+ */
+err_t
+netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx)
+{
+  s8_t i;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("netif_add_ip6_address: invalid netif", netif != NULL);
+  LWIP_ASSERT("netif_add_ip6_address: invalid ip6addr", ip6addr != NULL);
+
+  i = netif_get_ip6_addr_match(netif, ip6addr);
+  if (i >= 0) {
+    /* Address already added */
+    if (chosen_idx != NULL) {
+      *chosen_idx = i;
+    }
+    return ERR_OK;
+  }
+
+  /* Find a free slot. The first one is reserved for link-local addresses. */
+  for (i = ip6_addr_islinklocal(ip6addr) ? 0 : 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) {
+    if (ip6_addr_isinvalid(netif_ip6_addr_state(netif, i))) {
+      ip_addr_copy_from_ip6(netif->ip6_addr[i], *ip6addr);
+      ip6_addr_assign_zone(ip_2_ip6(&netif->ip6_addr[i]), IP6_UNICAST, netif);
+      netif_ip6_addr_set_state(netif, i, IP6_ADDR_TENTATIVE);
+      if (chosen_idx != NULL) {
+        *chosen_idx = i;
+      }
+      return ERR_OK;
+    }
+  }
+
+  if (chosen_idx != NULL) {
+    *chosen_idx = -1;
+  }
+  return ERR_VAL;
+}
+
+/** Dummy IPv6 output function for netifs not supporting IPv6
+ */
+static err_t
+netif_null_output_ip6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr)
+{
+  LWIP_UNUSED_ARG(netif);
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(ipaddr);
+
+  return ERR_IF;
+}
+#endif /* LWIP_IPV6 */
+
+#if LWIP_IPV4
+/** Dummy IPv4 output function for netifs not supporting IPv4
+ */
+static err_t
+netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
+{
+  LWIP_UNUSED_ARG(netif);
+  LWIP_UNUSED_ARG(p);
+  LWIP_UNUSED_ARG(ipaddr);
+
+  return ERR_IF;
+}
+#endif /* LWIP_IPV4 */
+
+/**
+* @ingroup netif
+* Return the interface index for the netif with name
+* or NETIF_NO_INDEX if not found/on error
+*
+* @param name the name of the netif
+*/
+u8_t
+netif_name_to_index(const char *name)
+{
+  struct netif *netif = netif_find(name);
+  if (netif != NULL) {
+    return netif_get_index(netif);
+  }
+  /* No name found, return invalid index */
+  return NETIF_NO_INDEX;
+}
+
+/**
+* @ingroup netif
+* Return the interface name for the netif matching index
+* or NULL if not found/on error
+*
+* @param idx the interface index of the netif
+* @param name char buffer of at least NETIF_NAMESIZE bytes
+*/
+char *
+netif_index_to_name(u8_t idx, char *name)
+{
+  struct netif *netif = netif_get_by_index(idx);
+
+  if (netif != NULL) {
+    name[0] = netif->name[0];
+    name[1] = netif->name[1];
+    lwip_itoa(&name[2], NETIF_NAMESIZE - 2, netif_index_to_num(idx));
+    return name;
+  }
+  return NULL;
+}
+
+/**
+* @ingroup netif
+* Return the interface for the netif index
+*
+* @param idx index of netif to find
+*/
+struct netif *
+netif_get_by_index(u8_t idx)
+{
+  struct netif *netif;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (idx != NETIF_NO_INDEX) {
+    NETIF_FOREACH(netif) {
+      if (idx == netif_get_index(netif)) {
+        return netif; /* found! */
+      }
+    }
+  }
+
+  return NULL;
+}
+
+/**
+ * @ingroup netif
+ * Find a network interface by searching for its name
+ *
+ * @param name the name of the netif (like netif->name) plus concatenated number
+ * in ascii representation (e.g. 'en0')
+ */
+struct netif *
+netif_find(const char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = (u8_t)atoi(&name[2]);
+
+  NETIF_FOREACH(netif) {
+    if (num == netif->num &&
+        name[0] == netif->name[0] &&
+        name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+/**
+ * @ingroup netif
+ * Add extended netif events listener
+ * @param callback pointer to listener structure
+ * @param fn callback function
+ */
+void
+netif_add_ext_callback(netif_ext_callback_t *callback, netif_ext_callback_fn fn)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("callback must be != NULL", callback != NULL);
+  LWIP_ASSERT("fn must be != NULL", fn != NULL);
+
+  callback->callback_fn = fn;
+  callback->next        = ext_callback;
+  ext_callback          = callback;
+}
+
+/**
+ * @ingroup netif
+ * Remove extended netif events listener
+ * @param callback pointer to listener structure
+ */
+void
+netif_remove_ext_callback(netif_ext_callback_t* callback)
+{
+  netif_ext_callback_t *last, *iter;
+
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("callback must be != NULL", callback != NULL);
+
+  if (ext_callback == NULL) {
+    return;
+  }
+
+  if (callback == ext_callback) {
+    ext_callback = ext_callback->next;
+  } else {
+    last = ext_callback;
+    for (iter = ext_callback->next; iter != NULL; last = iter, iter = iter->next) {
+      if (iter == callback) {
+        LWIP_ASSERT("last != NULL", last != NULL);
+        last->next = callback->next;
+        callback->next = NULL;
+        return;
+      }
+    }
+  }
+}
+
+/**
+ * Invoke extended netif status event
+ * @param netif netif that is affected by change
+ * @param reason change reason
+ * @param args depends on reason, see reason description
+ */
+void
+netif_invoke_ext_callback(struct netif *netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t *args)
+{
+  netif_ext_callback_t *callback = ext_callback;
+
+  LWIP_ASSERT("netif must be != NULL", netif != NULL);
+
+  while (callback != NULL) {
+    callback->callback_fn(netif, reason, args);
+    callback = callback->next;
+  }
+}
+#endif /* LWIP_NETIF_EXT_STATUS_CALLBACK */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/pbuf.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/pbuf.c
new file mode 100644
index 000000000..a209e0ca8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/pbuf.c
@@ -0,0 +1,1514 @@
+/**
+ * @file
+ * Packet buffer management
+ */
+
+/**
+ * @defgroup pbuf Packet buffers (PBUF)
+ * @ingroup infrastructure
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ *
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE
+ * NOT SUPPORTED!!! Use helper structs to queue multiple packets.
+ *
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle.
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ *
+ * Example of custom pbuf usage: @ref zerocopyrx
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#if LWIP_TCP && TCP_QUEUE_OOSEQ
+#include "lwip/priv/tcp_priv.h"
+#endif
+#if LWIP_CHECKSUM_ON_COPY
+#include "lwip/inet_chksum.h"
+#endif
+
+#include <string.h>
+
+#define SIZEOF_STRUCT_PBUF        LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf))
+/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically
+   aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */
+#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE)
+
+static const struct pbuf *
+pbuf_skip_const(const struct pbuf *in, u16_t in_offset, u16_t *out_offset);
+
+#if !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ
+#define PBUF_POOL_IS_EMPTY()
+#else /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
+
+#if !NO_SYS
+#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
+#include "lwip/tcpip.h"
+#define PBUF_POOL_FREE_OOSEQ_QUEUE_CALL()  do { \
+  if (tcpip_try_callback(pbuf_free_ooseq_callback, NULL) != ERR_OK) { \
+      SYS_ARCH_PROTECT(old_level); \
+      pbuf_free_ooseq_pending = 0; \
+      SYS_ARCH_UNPROTECT(old_level); \
+  } } while(0)
+#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
+#endif /* !NO_SYS */
+
+volatile u8_t pbuf_free_ooseq_pending;
+#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty()
+
+/**
+ * Attempt to reclaim some memory from queued out-of-sequence TCP segments
+ * if we run out of pool pbufs. It's better to give priority to new packets
+ * if we're running out.
+ *
+ * This must be done in the correct thread context therefore this function
+ * can only be used with NO_SYS=0 and through tcpip_callback.
+ */
+#if !NO_SYS
+static
+#endif /* !NO_SYS */
+void
+pbuf_free_ooseq(void)
+{
+  struct tcp_pcb *pcb;
+  SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
+
+  for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
+    if (pcb->ooseq != NULL) {
+      /** Free the ooseq pbufs of one PCB only */
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
+      tcp_free_ooseq(pcb);
+      return;
+    }
+  }
+}
+
+#if !NO_SYS
+/**
+ * Just a callback function for tcpip_callback() that calls pbuf_free_ooseq().
+ */
+static void
+pbuf_free_ooseq_callback(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+  pbuf_free_ooseq();
+}
+#endif /* !NO_SYS */
+
+/** Queue a call to pbuf_free_ooseq if not already queued. */
+static void
+pbuf_pool_is_empty(void)
+{
+#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
+  SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
+#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
+  u8_t queued;
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+  queued = pbuf_free_ooseq_pending;
+  pbuf_free_ooseq_pending = 1;
+  SYS_ARCH_UNPROTECT(old_level);
+
+  if (!queued) {
+    /* queue a call to pbuf_free_ooseq if not already queued */
+    PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
+  }
+#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
+}
+#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
+
+/* Initialize members of struct pbuf after allocation */
+static void
+pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
+{
+  p->next = NULL;
+  p->payload = payload;
+  p->tot_len = tot_len;
+  p->len = len;
+  p->type_internal = (u8_t)type;
+  p->flags = flags;
+  p->ref = 1;
+  p->if_idx = NETIF_NO_INDEX;
+}
+
+/**
+ * @ingroup pbuf
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param layer header size
+ * @param length size of the pbuf's payload
+ * @param type this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
+{
+  struct pbuf *p;
+  u16_t offset = (u16_t)layer;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  switch (type) {
+    case PBUF_REF: /* fall through */
+    case PBUF_ROM:
+      p = pbuf_alloc_reference(NULL, length, type);
+      break;
+    case PBUF_POOL: {
+      struct pbuf *q, *last;
+      u16_t rem_len; /* remaining length */
+      p = NULL;
+      last = NULL;
+      rem_len = length;
+      do {
+        u16_t qlen;
+        q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
+        if (q == NULL) {
+          PBUF_POOL_IS_EMPTY();
+          /* free chain so far allocated */
+          if (p) {
+            pbuf_free(p);
+          }
+          /* bail out unsuccessfully */
+          return NULL;
+        }
+        qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
+        pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
+                               rem_len, qlen, type, 0);
+        LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+                    ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+        LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
+                    (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
+        if (p == NULL) {
+          /* allocated head of pbuf chain (into p) */
+          p = q;
+        } else {
+          /* make previous pbuf point to this pbuf */
+          last->next = q;
+        }
+        last = q;
+        rem_len = (u16_t)(rem_len - qlen);
+        offset = 0;
+      } while (rem_len > 0);
+      break;
+    }
+    case PBUF_RAM: {
+      u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
+      mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
+
+      /* bug #50040: Check for integer overflow when calculating alloc_len */
+      if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
+          (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
+        return NULL;
+      }
+
+      /* If pbuf is to be allocated in RAM, allocate memory for it. */
+      p = (struct pbuf *)mem_malloc(alloc_len);
+      if (p == NULL) {
+        return NULL;
+      }
+      pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
+                             length, length, type, 0);
+      LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+                  ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+      break;
+    }
+    default:
+      LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
+      return NULL;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+}
+
+/**
+ * @ingroup pbuf
+ * Allocates a pbuf for referenced data.
+ * Referenced data can be volatile (PBUF_REF) or long-lived (PBUF_ROM).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param payload referenced payload
+ * @param length size of the pbuf's payload
+ * @param type this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_ROM: It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ *
+ * @return the allocated pbuf.
+ */
+struct pbuf *
+pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
+{
+  struct pbuf *p;
+  LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
+  /* only allocate memory for the pbuf structure */
+  p = (struct pbuf *)memp_malloc(MEMP_PBUF);
+  if (p == NULL) {
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
+                 (type == PBUF_ROM) ? "ROM" : "REF"));
+    return NULL;
+  }
+  pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
+  return p;
+}
+
+
+#if LWIP_SUPPORT_CUSTOM_PBUF
+/**
+ * @ingroup pbuf
+ * Initialize a custom pbuf (already allocated).
+ * Example of custom pbuf usage: @ref zerocopyrx
+ *
+ * @param l header size
+ * @param length size of the pbuf's payload
+ * @param type type of the pbuf (only used to treat the pbuf accordingly, as
+ *        this function allocates no memory)
+ * @param p pointer to the custom pbuf to initialize (already allocated)
+ * @param payload_mem pointer to the buffer that is used for payload and headers,
+ *        must be at least big enough to hold 'length' plus the header size,
+ *        may be NULL if set later.
+ *        ATTENTION: The caller is responsible for correct alignment of this buffer!!
+ * @param payload_mem_len the size of the 'payload_mem' buffer, must be at least
+ *        big enough to hold 'length' plus the header size
+ */
+struct pbuf *
+pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
+                    void *payload_mem, u16_t payload_mem_len)
+{
+  u16_t offset = (u16_t)l;
+  void *payload;
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
+
+  if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
+    return NULL;
+  }
+
+  if (payload_mem != NULL) {
+    payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
+  } else {
+    payload = NULL;
+  }
+  pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
+  return &p->pbuf;
+}
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+
+/**
+ * @ingroup pbuf
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  u16_t shrink;
+
+  LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  shrink = (u16_t)(p->tot_len - new_len);
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len = (u16_t)(rem_len - q->len);
+    /* decrease total length indicator */
+    q->tot_len = (u16_t)(q->tot_len - shrink);
+    /* proceed to next pbuf in chain */
+    q = q->next;
+    LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
+#if LWIP_SUPPORT_CUSTOM_PBUF
+      && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+     ) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
+    LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to reveal headers in the payload.
+ * @see pbuf_add_header.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_increment Number of bytes to increment header size.
+ * @param force Allow 'header_size_increment > 0' for PBUF_REF/PBUF_ROM types
+ *
+ * @return non-zero on failure, zero on success.
+ *
+ */
+static u8_t
+pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
+{
+  u16_t type_internal;
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((p == NULL) || (header_size_increment > 0xFFFF)) {
+    return 1;
+  }
+  if (header_size_increment == 0) {
+    return 0;
+  }
+
+  increment_magnitude = (u16_t)header_size_increment;
+  /* Do not allow tot_len to wrap as a result. */
+  if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
+    return 1;
+  }
+
+  type_internal = p->type_internal;
+
+  /* pbuf types containing payloads? */
+  if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
+    /* set new payload pointer */
+    payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
+                   ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
+                    (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
+      /* bail out unsuccessfully */
+      return 1;
+    }
+    /* pbuf types referring to external payloads? */
+  } else {
+    /* hide a header in the payload? */
+    if (force) {
+      payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccessfully */
+      return 1;
+    }
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
+              (void *)p->payload, (void *)payload, increment_magnitude));
+
+  /* modify pbuf fields */
+  p->payload = payload;
+  p->len = (u16_t)(p->len + increment_magnitude);
+  p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
+
+
+  return 0;
+}
+
+/**
+ * Adjusts the payload pointer to reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_increment Number of bytes to increment header size which
+ *          increases the size of the pbuf. New space is on the front.
+ *          If header_size_increment is 0, this function does nothing and returns successful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ *
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_add_header(struct pbuf *p, size_t header_size_increment)
+{
+  return pbuf_add_header_impl(p, header_size_increment, 0);
+}
+
+/**
+ * Same as @ref pbuf_add_header but does not check if 'header_size > 0' is allowed.
+ * This is used internally only, to allow PBUF_REF for RX.
+ */
+u8_t
+pbuf_add_header_force(struct pbuf *p, size_t header_size_increment)
+{
+  return pbuf_add_header_impl(p, header_size_increment, 1);
+}
+
+/**
+ * Adjusts the payload pointer to hide headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * disappears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_decrement Number of bytes to decrement header size which
+ *          decreases the size of the pbuf.
+ *          If header_size_decrement is 0, this function does nothing and returns successful.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
+{
+  void *payload;
+  u16_t increment_magnitude;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
+    return 1;
+  }
+  if (header_size_decrement == 0) {
+    return 0;
+  }
+
+  increment_magnitude = (u16_t)header_size_decrement;
+  /* Check that we aren't going to move off the end of the pbuf */
+  LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
+
+  /* remember current payload pointer */
+  payload = p->payload;
+  LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
+
+  /* increase payload pointer (guarded by length check above) */
+  p->payload = (u8_t *)p->payload + header_size_decrement;
+  /* modify pbuf length fields */
+  p->len = (u16_t)(p->len - increment_magnitude);
+  p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
+              (void *)payload, (void *)p->payload, increment_magnitude));
+
+  return 0;
+}
+
+static u8_t
+pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
+{
+  if (header_size_increment < 0) {
+    return pbuf_remove_header(p, (size_t) - header_size_increment);
+  } else {
+    return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
+  }
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param p pbuf to change the header size.
+ * @param header_size_increment Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If header_size_increment is 0, this function does nothing and returns successful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  return pbuf_header_impl(p, header_size_increment, 0);
+}
+
+/**
+ * Same as pbuf_header but does not check if 'header_size > 0' is allowed.
+ * This is used internally only, to allow PBUF_REF for RX.
+ */
+u8_t
+pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
+{
+  return pbuf_header_impl(p, header_size_increment, 1);
+}
+
+/** Similar to pbuf_header(-size) but de-refs header pbufs for (size >= p->len)
+ *
+ * @param q pbufs to operate on
+ * @param size The number of bytes to remove from the beginning of the pbuf list.
+ *             While size >= p->len, pbufs are freed.
+ *        ATTENTION: this is the opposite direction as @ref pbuf_header, but
+ *                   takes an u16_t not s16_t!
+ * @return the new head pbuf
+ */
+struct pbuf *
+pbuf_free_header(struct pbuf *q, u16_t size)
+{
+  struct pbuf *p = q;
+  u16_t free_left = size;
+  while (free_left && p) {
+    if (free_left >= p->len) {
+      struct pbuf *f = p;
+      free_left = (u16_t)(free_left - p->len);
+      p = p->next;
+      f->next = 0;
+      pbuf_free(f);
+    } else {
+      pbuf_remove_header(p, free_left);
+      free_left = 0;
+    }
+  }
+  return p;
+}
+
+/**
+ * @ingroup pbuf
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param p The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ *
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  u8_t alloc_src;
+  struct pbuf *q;
+  u8_t count;
+
+  if (p == NULL) {
+    LWIP_ASSERT("p != NULL", p != NULL);
+    /* if assertions are disabled, proceed with debug output */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  count = 0;
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    LWIP_PBUF_REF_T ref;
+    SYS_ARCH_DECL_PROTECT(old_level);
+    /* Since decrementing ref cannot be guaranteed to be a single machine operation
+     * we must protect it. We put the new ref into a local variable to prevent
+     * further protection. */
+    SYS_ARCH_PROTECT(old_level);
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    ref = --(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+    /* this pbuf is no longer referenced to? */
+    if (ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
+      alloc_src = pbuf_get_allocsrc(p);
+#if LWIP_SUPPORT_CUSTOM_PBUF
+      /* is this a custom pbuf? */
+      if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
+        struct pbuf_custom *pc = (struct pbuf_custom *)p;
+        LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
+        pc->custom_free_function(p);
+      } else
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+      {
+        /* is this a pbuf from the pool? */
+        if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
+          memp_free(MEMP_PBUF_POOL, p);
+          /* is this a ROM or RAM referencing pbuf? */
+        } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
+          memp_free(MEMP_PBUF, p);
+          /* type == PBUF_RAM */
+        } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
+          mem_free(p);
+        } else {
+          /* @todo: support freeing other types */
+          LWIP_ASSERT("invalid pbuf type", 0);
+        }
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+      /* p->ref > 0, this pbuf is still referenced to */
+      /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+u16_t
+pbuf_clen(const struct pbuf *p)
+{
+  u16_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * @ingroup pbuf
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
+    LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
+  }
+}
+
+/**
+ * @ingroup pbuf
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ *
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ *
+ * This function explicitly does not check for tot_len overflow to prevent
+ * failing to queue too long pbufs. This can produce invalid pbufs, so
+ * handle with care!
+ *
+ * @see pbuf_chain()
+ */
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
+             ((h != NULL) && (t != NULL)), return;);
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len = (u16_t)(p->tot_len + t->tot_len);
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len = (u16_t)(p->tot_len + t->tot_len);
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * @ingroup pbuf
+ * Chain two pbufs (or pbuf chains) together.
+ *
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ *
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = (u16_t)(p->tot_len - p->len);
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return ((tail_gone > 0) ? NULL : q);
+}
+
+/**
+ * @ingroup pbuf
+ * Create PBUF_RAM copies of pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ *
+ * @note Only one packet is copied, no packet queue!
+ *
+ * @param p_to pbuf destination of the copy
+ * @param p_from pbuf source of the copy
+ *
+ * @return ERR_OK if pbuf was copied
+ *         ERR_ARG if one of the pbufs is NULL or p_to is not big
+ *                 enough to hold p_from
+ */
+err_t
+pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
+{
+  size_t offset_to = 0, offset_from = 0, len;
+
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
+              (const void *)p_to, (const void *)p_from));
+
+  /* is the target big enough to hold the source? */
+  LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
+             (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
+
+  /* iterate through pbuf chain */
+  do {
+    /* copy one part of the original chain */
+    if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
+      /* complete current p_from fits into current p_to */
+      len = p_from->len - offset_from;
+    } else {
+      /* current p_from does not fit into current p_to */
+      len = p_to->len - offset_to;
+    }
+    MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
+    offset_to += len;
+    offset_from += len;
+    LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
+    LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
+    if (offset_from >= p_from->len) {
+      /* on to next p_from (if any) */
+      offset_from = 0;
+      p_from = p_from->next;
+    }
+    if (offset_to == p_to->len) {
+      /* on to next p_to (if any) */
+      offset_to = 0;
+      p_to = p_to->next;
+      LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
+    }
+
+    if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!",
+                 (p_from->next == NULL), return ERR_VAL;);
+    }
+    if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
+      /* don't copy more than one packet! */
+      LWIP_ERROR("pbuf_copy() does not allow packet queues!",
+                 (p_to->next == NULL), return ERR_VAL;);
+    }
+  } while (p_from);
+  LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
+  return ERR_OK;
+}
+
+/**
+ * @ingroup pbuf
+ * Copy (part of) the contents of a packet buffer
+ * to an application supplied buffer.
+ *
+ * @param buf the pbuf from which to copy data
+ * @param dataptr the application supplied buffer
+ * @param len length of data to copy (dataptr must be big enough). No more
+ * than buf->tot_len will be copied, irrespective of len
+ * @param offset offset into the packet buffer from where to begin copying len bytes
+ * @return the number of bytes copied, or 0 on failure
+ */
+u16_t
+pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  const struct pbuf *p;
+  u16_t left = 0;
+  u16_t buf_copy_len;
+  u16_t copied_total = 0;
+
+  LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
+  LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for (p = buf; len != 0 && p != NULL; p = p->next) {
+    if ((offset != 0) && (offset >= p->len)) {
+      /* don't copy from this buffer -> on to the next */
+      offset = (u16_t)(offset - p->len);
+    } else {
+      /* copy from this buffer. maybe only partially. */
+      buf_copy_len = (u16_t)(p->len - offset);
+      if (buf_copy_len > len) {
+        buf_copy_len = len;
+      }
+      /* copy the necessary parts of the buffer */
+      MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
+      copied_total = (u16_t)(copied_total + buf_copy_len);
+      left = (u16_t)(left + buf_copy_len);
+      len = (u16_t)(len - buf_copy_len);
+      offset = 0;
+    }
+  }
+  return copied_total;
+}
+
+/**
+ * @ingroup pbuf
+ * Get part of a pbuf's payload as contiguous memory. The returned memory is
+ * either a pointer into the pbuf's payload or, if split over multiple pbufs,
+ * a copy into the user-supplied buffer.
+ *
+ * @param p the pbuf from which to copy data
+ * @param buffer the application supplied buffer
+ * @param bufsize size of the application supplied buffer
+ * @param len length of data to copy (dataptr must be big enough). No more
+ * than buf->tot_len will be copied, irrespective of len
+ * @param offset offset into the packet buffer from where to begin copying len bytes
+ * @return the number of bytes copied, or 0 on failure
+ */
+void *
+pbuf_get_contiguous(const struct pbuf *p, void *buffer, size_t bufsize, u16_t len, u16_t offset)
+{
+  const struct pbuf *q;
+  u16_t out_offset;
+
+  LWIP_ERROR("pbuf_get_contiguous: invalid buf", (p != NULL), return NULL;);
+  LWIP_ERROR("pbuf_get_contiguous: invalid dataptr", (buffer != NULL), return NULL;);
+  LWIP_ERROR("pbuf_get_contiguous: invalid dataptr", (bufsize >= len), return NULL;);
+
+  q = pbuf_skip_const(p, offset, &out_offset);
+  if (q != NULL) {
+    if (q->len >= (out_offset + len)) {
+      /* all data in this pbuf, return zero-copy */
+      return (u8_t *)q->payload + out_offset;
+    }
+    /* need to copy */
+    if (pbuf_copy_partial(q, buffer, len, out_offset) != len) {
+      /* copying failed: pbuf is too short */
+      return NULL;
+    }
+    return buffer;
+  }
+  /* pbuf is too short (offset does not fit in) */
+  return NULL;
+}
+
+#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+/**
+ * This method modifies a 'pbuf chain', so that its total length is
+ * smaller than 64K. The remainder of the original pbuf chain is stored
+ * in *rest.
+ * This function never creates new pbufs, but splits an existing chain
+ * in two parts. The tot_len of the modified packet queue will likely be
+ * smaller than 64K.
+ * 'packet queues' are not supported by this function.
+ *
+ * @param p the pbuf queue to be split
+ * @param rest pointer to store the remainder (after the first 64K)
+ */
+void pbuf_split_64k(struct pbuf *p, struct pbuf **rest)
+{
+  *rest = NULL;
+  if ((p != NULL) && (p->next != NULL)) {
+    u16_t tot_len_front = p->len;
+    struct pbuf *i = p;
+    struct pbuf *r = p->next;
+
+    /* continue until the total length (summed up as u16_t) overflows */
+    while ((r != NULL) && ((u16_t)(tot_len_front + r->len) >= tot_len_front)) {
+      tot_len_front = (u16_t)(tot_len_front + r->len);
+      i = r;
+      r = r->next;
+    }
+    /* i now points to last packet of the first segment. Set next
+       pointer to NULL */
+    i->next = NULL;
+
+    if (r != NULL) {
+      /* Update the tot_len field in the first part */
+      for (i = p; i != NULL; i = i->next) {
+        i->tot_len = (u16_t)(i->tot_len - r->tot_len);
+        LWIP_ASSERT("tot_len/len mismatch in last pbuf",
+                    (i->next != NULL) || (i->tot_len == i->len));
+      }
+      if (p->flags & PBUF_FLAG_TCP_FIN) {
+        r->flags |= PBUF_FLAG_TCP_FIN;
+      }
+
+      /* tot_len field in rest does not need modifications */
+      /* reference counters do not need modifications */
+      *rest = r;
+    }
+  }
+}
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+/* Actual implementation of pbuf_skip() but returning const pointer... */
+static const struct pbuf *
+pbuf_skip_const(const struct pbuf *in, u16_t in_offset, u16_t *out_offset)
+{
+  u16_t offset_left = in_offset;
+  const struct pbuf *q = in;
+
+  /* get the correct pbuf */
+  while ((q != NULL) && (q->len <= offset_left)) {
+    offset_left = (u16_t)(offset_left - q->len);
+    q = q->next;
+  }
+  if (out_offset != NULL) {
+    *out_offset = offset_left;
+  }
+  return q;
+}
+
+/**
+ * @ingroup pbuf
+ * Skip a number of bytes at the start of a pbuf
+ *
+ * @param in input pbuf
+ * @param in_offset offset to skip
+ * @param out_offset resulting offset in the returned pbuf
+ * @return the pbuf in the queue where the offset is
+ */
+struct pbuf *
+pbuf_skip(struct pbuf *in, u16_t in_offset, u16_t *out_offset)
+{
+  const struct pbuf *out = pbuf_skip_const(in, in_offset, out_offset);
+  return LWIP_CONST_CAST(struct pbuf *, out);
+}
+
+/**
+ * @ingroup pbuf
+ * Copy application supplied data into a pbuf.
+ * This function can only be used to copy the equivalent of buf->tot_len data.
+ *
+ * @param buf pbuf to fill with data
+ * @param dataptr application supplied data buffer
+ * @param len length of the application supplied data buffer
+ *
+ * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough
+ */
+err_t
+pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len)
+{
+  struct pbuf *p;
+  size_t buf_copy_len;
+  size_t total_copy_len = len;
+  size_t copied_total = 0;
+
+  LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return ERR_ARG;);
+  LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return ERR_ARG;);
+  LWIP_ERROR("pbuf_take: buf not large enough", (buf->tot_len >= len), return ERR_MEM;);
+
+  if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) {
+    return ERR_ARG;
+  }
+
+  /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
+  for (p = buf; total_copy_len != 0; p = p->next) {
+    LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL);
+    buf_copy_len = total_copy_len;
+    if (buf_copy_len > p->len) {
+      /* this pbuf cannot hold all remaining data */
+      buf_copy_len = p->len;
+    }
+    /* copy the necessary parts of the buffer */
+    MEMCPY(p->payload, &((const char *)dataptr)[copied_total], buf_copy_len);
+    total_copy_len -= buf_copy_len;
+    copied_total += buf_copy_len;
+  }
+  LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len);
+  return ERR_OK;
+}
+
+/**
+ * @ingroup pbuf
+ * Same as pbuf_take() but puts data at an offset
+ *
+ * @param buf pbuf to fill with data
+ * @param dataptr application supplied data buffer
+ * @param len length of the application supplied data buffer
+ * @param offset offset in pbuf where to copy dataptr to
+ *
+ * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough
+ */
+err_t
+pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset)
+{
+  u16_t target_offset;
+  struct pbuf *q = pbuf_skip(buf, offset, &target_offset);
+
+  /* return requested data if pbuf is OK */
+  if ((q != NULL) && (q->tot_len >= target_offset + len)) {
+    u16_t remaining_len = len;
+    const u8_t *src_ptr = (const u8_t *)dataptr;
+    /* copy the part that goes into the first pbuf */
+    u16_t first_copy_len;
+    LWIP_ASSERT("check pbuf_skip result", target_offset < q->len);
+    first_copy_len = (u16_t)LWIP_MIN(q->len - target_offset, len);
+    MEMCPY(((u8_t *)q->payload) + target_offset, dataptr, first_copy_len);
+    remaining_len = (u16_t)(remaining_len - first_copy_len);
+    src_ptr += first_copy_len;
+    if (remaining_len > 0) {
+      return pbuf_take(q->next, src_ptr, remaining_len);
+    }
+    return ERR_OK;
+  }
+  return ERR_MEM;
+}
+
+/**
+ * @ingroup pbuf
+ * Creates a single pbuf out of a queue of pbufs.
+ *
+ * @remark: Either the source pbuf 'p' is freed by this function or the original
+ *          pbuf 'p' is returned, therefore the caller has to check the result!
+ *
+ * @param p the source pbuf
+ * @param layer pbuf_layer of the new pbuf
+ *
+ * @return a new, single pbuf (p->next is NULL)
+ *         or the old pbuf if allocation fails
+ */
+struct pbuf *
+pbuf_coalesce(struct pbuf *p, pbuf_layer layer)
+{
+  struct pbuf *q;
+  if (p->next == NULL) {
+    return p;
+  }
+  q = pbuf_clone(layer, PBUF_RAM, p);
+  if (q == NULL) {
+    /* @todo: what do we do now? */
+    return p;
+  }
+  pbuf_free(p);
+  return q;
+}
+
+/**
+ * @ingroup pbuf
+ * Allocates a new pbuf of same length (via pbuf_alloc()) and copies the source
+ * pbuf into this new pbuf (using pbuf_copy()).
+ *
+ * @param layer pbuf_layer of the new pbuf
+ * @param type this parameter decides how and where the pbuf should be allocated
+ *             (@see pbuf_alloc())
+ * @param p the source pbuf
+ *
+ * @return a new pbuf or NULL if allocation fails
+ */
+struct pbuf *
+pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
+{
+  struct pbuf *q;
+  err_t err;
+  q = pbuf_alloc(layer, p->tot_len, type);
+  if (q == NULL) {
+    return NULL;
+  }
+  err = pbuf_copy(q, p);
+  LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
+  LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
+  return q;
+}
+
+#if LWIP_CHECKSUM_ON_COPY
+/**
+ * Copies data into a single pbuf (*not* into a pbuf queue!) and updates
+ * the checksum while copying
+ *
+ * @param p the pbuf to copy data into
+ * @param start_offset offset of p->payload where to copy the data to
+ * @param dataptr data to copy into the pbuf
+ * @param len length of data to copy into the pbuf
+ * @param chksum pointer to the checksum which is updated
+ * @return ERR_OK if successful, another error if the data does not fit
+ *         within the (first) pbuf (no pbuf queues!)
+ */
+err_t
+pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
+                 u16_t len, u16_t *chksum)
+{
+  u32_t acc;
+  u16_t copy_chksum;
+  char *dst_ptr;
+  LWIP_ASSERT("p != NULL", p != NULL);
+  LWIP_ASSERT("dataptr != NULL", dataptr != NULL);
+  LWIP_ASSERT("chksum != NULL", chksum != NULL);
+  LWIP_ASSERT("len != 0", len != 0);
+
+  if ((start_offset >= p->len) || (start_offset + len > p->len)) {
+    return ERR_ARG;
+  }
+
+  dst_ptr = ((char *)p->payload) + start_offset;
+  copy_chksum = LWIP_CHKSUM_COPY(dst_ptr, dataptr, len);
+  if ((start_offset & 1) != 0) {
+    copy_chksum = SWAP_BYTES_IN_WORD(copy_chksum);
+  }
+  acc = *chksum;
+  acc += copy_chksum;
+  *chksum = FOLD_U32T(acc);
+  return ERR_OK;
+}
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+/**
+ * @ingroup pbuf
+ * Get one byte from the specified position in a pbuf
+ * WARNING: returns zero for offset >= p->tot_len
+ *
+ * @param p pbuf to parse
+ * @param offset offset into p of the byte to return
+ * @return byte at an offset into p OR ZERO IF 'offset' >= p->tot_len
+ */
+u8_t
+pbuf_get_at(const struct pbuf *p, u16_t offset)
+{
+  int ret = pbuf_try_get_at(p, offset);
+  if (ret >= 0) {
+    return (u8_t)ret;
+  }
+  return 0;
+}
+
+/**
+ * @ingroup pbuf
+ * Get one byte from the specified position in a pbuf
+ *
+ * @param p pbuf to parse
+ * @param offset offset into p of the byte to return
+ * @return byte at an offset into p [0..0xFF] OR negative if 'offset' >= p->tot_len
+ */
+int
+pbuf_try_get_at(const struct pbuf *p, u16_t offset)
+{
+  u16_t q_idx;
+  const struct pbuf *q = pbuf_skip_const(p, offset, &q_idx);
+
+  /* return requested data if pbuf is OK */
+  if ((q != NULL) && (q->len > q_idx)) {
+    return ((u8_t *)q->payload)[q_idx];
+  }
+  return -1;
+}
+
+/**
+ * @ingroup pbuf
+ * Put one byte to the specified position in a pbuf
+ * WARNING: silently ignores offset >= p->tot_len
+ *
+ * @param p pbuf to fill
+ * @param offset offset into p of the byte to write
+ * @param data byte to write at an offset into p
+ */
+void
+pbuf_put_at(struct pbuf *p, u16_t offset, u8_t data)
+{
+  u16_t q_idx;
+  struct pbuf *q = pbuf_skip(p, offset, &q_idx);
+
+  /* write requested data if pbuf is OK */
+  if ((q != NULL) && (q->len > q_idx)) {
+    ((u8_t *)q->payload)[q_idx] = data;
+  }
+}
+
+/**
+ * @ingroup pbuf
+ * Compare pbuf contents at specified offset with memory s2, both of length n
+ *
+ * @param p pbuf to compare
+ * @param offset offset into p at which to start comparing
+ * @param s2 buffer to compare
+ * @param n length of buffer to compare
+ * @return zero if equal, nonzero otherwise
+ *         (0xffff if p is too short, diffoffset+1 otherwise)
+ */
+u16_t
+pbuf_memcmp(const struct pbuf *p, u16_t offset, const void *s2, u16_t n)
+{
+  u16_t start = offset;
+  const struct pbuf *q = p;
+  u16_t i;
+
+  /* pbuf long enough to perform check? */
+  if (p->tot_len < (offset + n)) {
+    return 0xffff;
+  }
+
+  /* get the correct pbuf from chain. We know it succeeds because of p->tot_len check above. */
+  while ((q != NULL) && (q->len <= start)) {
+    start = (u16_t)(start - q->len);
+    q = q->next;
+  }
+
+  /* return requested data if pbuf is OK */
+  for (i = 0; i < n; i++) {
+    /* We know pbuf_get_at() succeeds because of p->tot_len check above. */
+    u8_t a = pbuf_get_at(q, (u16_t)(start + i));
+    u8_t b = ((const u8_t *)s2)[i];
+    if (a != b) {
+      return (u16_t)LWIP_MIN(i + 1, 0xFFFF);
+    }
+  }
+  return 0;
+}
+
+/**
+ * @ingroup pbuf
+ * Find occurrence of mem (with length mem_len) in pbuf p, starting at offset
+ * start_offset.
+ *
+ * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as
+ *        return value 'not found'
+ * @param mem search for the contents of this buffer
+ * @param mem_len length of 'mem'
+ * @param start_offset offset into p at which to start searching
+ * @return 0xFFFF if substr was not found in p or the index where it was found
+ */
+u16_t
+pbuf_memfind(const struct pbuf *p, const void *mem, u16_t mem_len, u16_t start_offset)
+{
+  u16_t i;
+  u16_t max_cmp_start = (u16_t)(p->tot_len - mem_len);
+  if (p->tot_len >= mem_len + start_offset) {
+    for (i = start_offset; i <= max_cmp_start; i++) {
+      u16_t plus = pbuf_memcmp(p, i, mem, mem_len);
+      if (plus == 0) {
+        return i;
+      }
+    }
+  }
+  return 0xFFFF;
+}
+
+/**
+ * Find occurrence of substr with length substr_len in pbuf p, start at offset
+ * start_offset
+ * WARNING: in contrast to strstr(), this one does not stop at the first \0 in
+ * the pbuf/source string!
+ *
+ * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as
+ *        return value 'not found'
+ * @param substr string to search for in p, maximum length is 0xFFFE
+ * @return 0xFFFF if substr was not found in p or the index where it was found
+ */
+u16_t
+pbuf_strstr(const struct pbuf *p, const char *substr)
+{
+  size_t substr_len;
+  if ((substr == NULL) || (substr[0] == 0) || (p->tot_len == 0xFFFF)) {
+    return 0xFFFF;
+  }
+  substr_len = strlen(substr);
+  if (substr_len >= 0xFFFF) {
+    return 0xFFFF;
+  }
+  return pbuf_memfind(p, substr, (u16_t)substr_len, 0);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/raw.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/raw.c
new file mode 100644
index 000000000..3b34544b0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/raw.c
@@ -0,0 +1,671 @@
+/**
+ * @file
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.\n
+ * See also @ref raw_raw
+ *
+ * @defgroup raw_raw RAW
+ * @ingroup callbackstyle_api
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.\n
+ * @see @ref api
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+#include "lwip/priv/raw_priv.h"
+#include "lwip/stats.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/inet_chksum.h"
+
+#include <string.h>
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs;
+
+static u8_t
+raw_input_local_match(struct raw_pcb *pcb, u8_t broadcast)
+{
+  LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
+
+  /* check if PCB is bound to specific netif */
+  if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+      (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+    return 0;
+  }
+
+#if LWIP_IPV4 && LWIP_IPV6
+  /* Dual-stack: PCBs listening to any IP type also listen to any IP address */
+  if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) {
+#if IP_SOF_BROADCAST_RECV
+    if ((broadcast != 0) && !ip_get_option(pcb, SOF_BROADCAST)) {
+      return 0;
+    }
+#endif /* IP_SOF_BROADCAST_RECV */
+    return 1;
+  }
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+  /* Only need to check PCB if incoming IP version matches PCB IP version */
+  if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
+#if LWIP_IPV4
+    /* Special case: IPv4 broadcast: receive all broadcasts
+     * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
+    if (broadcast != 0) {
+#if IP_SOF_BROADCAST_RECV
+      if (ip_get_option(pcb, SOF_BROADCAST))
+#endif /* IP_SOF_BROADCAST_RECV */
+      {
+        if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip))) {
+          return 1;
+        }
+      }
+    } else
+#endif /* LWIP_IPV4 */
+      /* Handle IPv4 and IPv6: catch all or exact match */
+      if (ip_addr_isany(&pcb->local_ip) ||
+          ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+        return 1;
+      }
+  }
+
+  return 0;
+}
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param p pbuf to be demultiplexed to a RAW PCB.
+ * @param inp network interface on which the datagram was received.
+ * @return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+raw_input_state_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb, *prev;
+  s16_t proto;
+  raw_input_state_t ret = RAW_INPUT_NONE;
+  u8_t broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
+
+  LWIP_UNUSED_ARG(inp);
+
+#if LWIP_IPV6
+#if LWIP_IPV4
+  if (IP_HDR_GET_VERSION(p->payload) == 6)
+#endif /* LWIP_IPV4 */
+  {
+    struct ip6_hdr *ip6hdr = (struct ip6_hdr *)p->payload;
+    proto = IP6H_NEXTH(ip6hdr);
+  }
+#if LWIP_IPV4
+  else
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+  {
+    proto = IPH_PROTO((struct ip_hdr *)p->payload);
+  }
+#endif /* LWIP_IPV4 */
+
+  prev = NULL;
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while (pcb != NULL) {
+    if ((pcb->protocol == proto) && raw_input_local_match(pcb, broadcast) &&
+        (((pcb->flags & RAW_FLAGS_CONNECTED) == 0) ||
+         ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
+      /* receive callback function available? */
+      if (pcb->recv != NULL) {
+        u8_t eaten;
+#ifndef LWIP_NOASSERT
+        void *old_payload = p->payload;
+#endif
+        ret = RAW_INPUT_DELIVERED;
+        /* the receive callback function did not eat the packet? */
+        eaten = pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr());
+        if (eaten != 0) {
+          /* receive function ate the packet */
+          p = NULL;
+          if (prev != NULL) {
+            /* move the pcb to the front of raw_pcbs so that is
+               found faster next time */
+            prev->next = pcb->next;
+            pcb->next = raw_pcbs;
+            raw_pcbs = pcb;
+          }
+          return RAW_INPUT_EATEN;
+        } else {
+          /* sanity-check that the receive callback did not alter the pbuf */
+          LWIP_ASSERT("raw pcb recv callback altered pbuf payload pointer without eating packet",
+                      p->payload == old_payload);
+        }
+      }
+      /* no receive callback function was set for this raw PCB */
+    }
+    /* drop the packet */
+    prev = pcb;
+    pcb = pcb->next;
+  }
+  return ret;
+}
+
+/**
+ * @ingroup raw_raw
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP4_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occurred.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, const ip_addr_t *ipaddr)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if ((pcb == NULL) || (ipaddr == NULL)) {
+    return ERR_VAL;
+  }
+  ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  /* If the given IP address should have a zone but doesn't, assign one now.
+   * This is legacy support: scope-aware callers should always provide properly
+   * zoned source addresses. */
+  if (IP_IS_V6(&pcb->local_ip) &&
+      ip6_addr_lacks_zone(ip_2_ip6(&pcb->local_ip), IP6_UNKNOWN)) {
+    ip6_addr_select_zone(ip_2_ip6(&pcb->local_ip), ip_2_ip6(&pcb->local_ip));
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+  return ERR_OK;
+}
+
+/**
+ * @ingroup raw_raw
+ * Bind an RAW PCB to a specific netif.
+ * After calling this function, all packets received via this PCB
+ * are guaranteed to have come in via the specified netif, and all
+ * outgoing packets will go out via the specified netif.
+ *
+ * @param pcb RAW PCB to be bound with netif.
+ * @param netif netif to bind to. Can be NULL.
+ *
+ * @see raw_disconnect()
+ */
+void
+raw_bind_netif(struct raw_pcb *pcb, const struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if (netif != NULL) {
+    pcb->netif_idx = netif_get_index(netif);
+  } else {
+    pcb->netif_idx = NETIF_NO_INDEX;
+  }
+}
+
+/**
+ * @ingroup raw_raw
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, const ip_addr_t *ipaddr)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if ((pcb == NULL) || (ipaddr == NULL)) {
+    return ERR_VAL;
+  }
+  ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  /* If the given IP address should have a zone but doesn't, assign one now,
+   * using the bound address to make a more informed decision when possible. */
+  if (IP_IS_V6(&pcb->remote_ip) &&
+      ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
+    ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+  raw_set_flags(pcb, RAW_FLAGS_CONNECTED);
+  return ERR_OK;
+}
+
+/**
+ * @ingroup raw_raw
+ * Disconnect a RAW PCB.
+ *
+ * @param pcb the raw pcb to disconnect.
+ */
+void
+raw_disconnect(struct raw_pcb *pcb)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  /* reset remote address association */
+#if LWIP_IPV4 && LWIP_IPV6
+  if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) {
+    ip_addr_copy(pcb->remote_ip, *IP_ANY_TYPE);
+  } else {
+#endif
+    ip_addr_set_any(IP_IS_V6_VAL(pcb->remote_ip), &pcb->remote_ip);
+#if LWIP_IPV4 && LWIP_IPV6
+  }
+#endif
+  pcb->netif_idx = NETIF_NO_INDEX;
+  /* mark PCB as unconnected */
+  raw_clear_flags(pcb, RAW_FLAGS_CONNECTED);
+}
+
+/**
+ * @ingroup raw_raw
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding.
+ *
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ */
+void
+raw_recv(struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * @ingroup raw_raw
+ * Send the raw IP packet to the given address. An IP header will be prepended
+ * to the packet, unless the RAW_FLAGS_HDRINCL flag is set on the PCB. In that
+ * case, the packet must include an IP header, which will then be sent as is.
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr)
+{
+  struct netif *netif;
+  const ip_addr_t *src_ip;
+
+  if ((pcb == NULL) || (ipaddr == NULL) || !IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr)) {
+    return ERR_VAL;
+  }
+
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n"));
+
+  if (pcb->netif_idx != NETIF_NO_INDEX) {
+    netif = netif_get_by_index(pcb->netif_idx);
+  } else {
+#if LWIP_MULTICAST_TX_OPTIONS
+    netif = NULL;
+    if (ip_addr_ismulticast(ipaddr)) {
+      /* For multicast-destined packets, use the user-provided interface index to
+       * determine the outgoing interface, if an interface index is set and a
+       * matching netif can be found. Otherwise, fall back to regular routing. */
+      netif = netif_get_by_index(pcb->mcast_ifindex);
+    }
+
+    if (netif == NULL)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+    {
+      netif = ip_route(&pcb->local_ip, ipaddr);
+    }
+  }
+
+  if (netif == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to "));
+    ip_addr_debug_print(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ipaddr);
+    return ERR_RTE;
+  }
+
+  if (ip_addr_isany(&pcb->local_ip) || ip_addr_ismulticast(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = ip_netif_get_local_ip(netif, ipaddr);
+#if LWIP_IPV6
+    if (src_ip == NULL) {
+      return ERR_RTE;
+    }
+#endif /* LWIP_IPV6 */
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &pcb->local_ip;
+  }
+
+  return raw_sendto_if_src(pcb, p, ipaddr, netif, src_ip);
+}
+
+/**
+ * @ingroup raw_raw
+ * Send the raw IP packet to the given address, using a particular outgoing
+ * netif and source IP address. An IP header will be prepended to the packet,
+ * unless the RAW_FLAGS_HDRINCL flag is set on the PCB. In that case, the
+ * packet must include an IP header, which will then be sent as is.
+ *
+ * @param pcb RAW PCB used to send the data
+ * @param p chain of pbufs to be sent
+ * @param dst_ip destination IP address
+ * @param netif the netif used for sending
+ * @param src_ip source IP address
+ */
+err_t
+raw_sendto_if_src(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip,
+                  struct netif *netif, const ip_addr_t *src_ip)
+{
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+  u16_t header_size;
+  u8_t ttl;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if ((pcb == NULL) || (dst_ip == NULL) || (netif == NULL) || (src_ip == NULL) ||
+      !IP_ADDR_PCB_VERSION_MATCH(pcb, src_ip) || !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) {
+    return ERR_VAL;
+  }
+
+  header_size = (
+#if LWIP_IPV4 && LWIP_IPV6
+                  IP_IS_V6(dst_ip) ? IP6_HLEN : IP_HLEN);
+#elif LWIP_IPV4
+                  IP_HLEN);
+#else
+                  IP6_HLEN);
+#endif
+
+  /* Handle the HDRINCL option as an exception: none of the code below applies
+   * to this case, and sending the packet needs to be done differently too. */
+  if (pcb->flags & RAW_FLAGS_HDRINCL) {
+    /* A full header *must* be present in the first pbuf of the chain, as the
+     * output routines may access its fields directly. */
+    if (p->len < header_size) {
+      return ERR_VAL;
+    }
+    /* @todo multicast loop support, if at all desired for this scenario.. */
+    NETIF_SET_HINTS(netif, &pcb->netif_hints);
+    err = ip_output_if_hdrincl(p, src_ip, dst_ip, netif);
+    NETIF_RESET_HINTS(netif);
+    return err;
+  }
+
+  /* packet too large to add an IP header without causing an overflow? */
+  if ((u16_t)(p->tot_len + header_size) < p->tot_len) {
+    return ERR_MEM;
+  }
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_add_header(p, header_size)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    if (p->tot_len != 0) {
+      /* chain header q in front of given pbuf p */
+      pbuf_chain(q, p);
+    }
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  } else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    if (pbuf_remove_header(q, header_size)) {
+      LWIP_ASSERT("Can't restore header we just removed!", 0);
+      return ERR_MEM;
+    }
+  }
+
+#if IP_SOF_BROADCAST
+  if (IP_IS_V4(dst_ip)) {
+    /* broadcast filter? */
+    if (!ip_get_option(pcb, SOF_BROADCAST) && ip_addr_isbroadcast(dst_ip, netif)) {
+      LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb));
+      /* free any temporary header pbuf allocated by pbuf_header() */
+      if (q != p) {
+        pbuf_free(q);
+      }
+      return ERR_VAL;
+    }
+  }
+#endif /* IP_SOF_BROADCAST */
+
+  /* Multicast Loop? */
+#if LWIP_MULTICAST_TX_OPTIONS
+  if (((pcb->flags & RAW_FLAGS_MULTICAST_LOOP) != 0) && ip_addr_ismulticast(dst_ip)) {
+    q->flags |= PBUF_FLAG_MCASTLOOP;
+  }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_IPV6
+  /* If requested, based on the IPV6_CHECKSUM socket option per RFC3542,
+     compute the checksum and update the checksum in the payload. */
+  if (IP_IS_V6(dst_ip) && pcb->chksum_reqd) {
+    u16_t chksum = ip6_chksum_pseudo(p, pcb->protocol, p->tot_len, ip_2_ip6(src_ip), ip_2_ip6(dst_ip));
+    LWIP_ASSERT("Checksum must fit into first pbuf", p->len >= (pcb->chksum_offset + 2));
+    SMEMCPY(((u8_t *)p->payload) + pcb->chksum_offset, &chksum, sizeof(u16_t));
+  }
+#endif
+
+  /* Determine TTL to use */
+#if LWIP_MULTICAST_TX_OPTIONS
+  ttl = (ip_addr_ismulticast(dst_ip) ? raw_get_multicast_ttl(pcb) : pcb->ttl);
+#else /* LWIP_MULTICAST_TX_OPTIONS */
+  ttl = pcb->ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+  NETIF_SET_HINTS(netif, &pcb->netif_hints);
+  err = ip_output_if(q, src_ip, dst_ip, ttl, pcb->tos, pcb->protocol, netif);
+  NETIF_RESET_HINTS(netif);
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * @ingroup raw_raw
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * @ingroup raw_raw
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  LWIP_ASSERT_CORE_LOCKED();
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else {
+    for (pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in raw_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+        break;
+      }
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * @ingroup raw_raw
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u8_t proto)
+{
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n"));
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = (struct raw_pcb *)memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+#if LWIP_MULTICAST_TX_OPTIONS
+    raw_set_multicast_ttl(pcb, RAW_TTL);
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+/**
+ * @ingroup raw_raw
+ * Create a RAW PCB for specific IP type.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param type IP address type, see @ref lwip_ip_addr_type definitions.
+ * If you want to listen to IPv4 and IPv6 (dual-stack) packets,
+ * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE.
+ * @param proto the protocol number (next header) of the IPv6 packet payload
+ *              (e.g. IP6_NEXTH_ICMP6)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new_ip_type(u8_t type, u8_t proto)
+{
+  struct raw_pcb *pcb;
+  LWIP_ASSERT_CORE_LOCKED();
+  pcb = raw_new(proto);
+#if LWIP_IPV4 && LWIP_IPV6
+  if (pcb != NULL) {
+    IP_SET_TYPE_VAL(pcb->local_ip,  type);
+    IP_SET_TYPE_VAL(pcb->remote_ip, type);
+  }
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+  LWIP_UNUSED_ARG(type);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  return pcb;
+}
+
+/** This function is called from netif.c when address is changed
+ *
+ * @param old_addr IP address of the netif before change
+ * @param new_addr IP address of the netif after change
+ */
+void raw_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+  struct raw_pcb *rpcb;
+
+  if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
+    for (rpcb = raw_pcbs; rpcb != NULL; rpcb = rpcb->next) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&rpcb->local_ip, old_addr)) {
+        /* The PCB is bound to the old ipaddr and
+         * is set to bound to the new one instead */
+        ip_addr_copy(rpcb->local_ip, *new_addr);
+      }
+    }
+  }
+}
+
+#endif /* LWIP_RAW */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/stats.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/stats.c
new file mode 100644
index 000000000..34e9b2709
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/stats.c
@@ -0,0 +1,169 @@
+/**
+ * @file
+ * Statistics module
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/debug.h"
+
+#include <string.h>
+
+struct stats_ lwip_stats;
+
+void
+stats_init(void)
+{
+#ifdef LWIP_DEBUG
+#if MEM_STATS
+  lwip_stats.mem.name = "MEM";
+#endif /* MEM_STATS */
+#endif /* LWIP_DEBUG */
+}
+
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, const char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit));
+  LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv));
+  LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw));
+  LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop));
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr));
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr));
+  LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr));
+  LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr));
+  LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr));
+  LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr));
+  LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err));
+  LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit));
+}
+
+#if IGMP_STATS || MLD6_STATS
+void
+stats_display_igmp(struct stats_igmp *igmp, const char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", igmp->xmit));
+  LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", igmp->recv));
+  LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", igmp->drop));
+  LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr));
+  LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr));
+  LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", igmp->memerr));
+  LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", igmp->proterr));
+  LWIP_PLATFORM_DIAG(("rx_v1: %"STAT_COUNTER_F"\n\t", igmp->rx_v1));
+  LWIP_PLATFORM_DIAG(("rx_group: %"STAT_COUNTER_F"\n\t", igmp->rx_group));
+  LWIP_PLATFORM_DIAG(("rx_general: %"STAT_COUNTER_F"\n\t", igmp->rx_general));
+  LWIP_PLATFORM_DIAG(("rx_report: %"STAT_COUNTER_F"\n\t", igmp->rx_report));
+  LWIP_PLATFORM_DIAG(("tx_join: %"STAT_COUNTER_F"\n\t", igmp->tx_join));
+  LWIP_PLATFORM_DIAG(("tx_leave: %"STAT_COUNTER_F"\n\t", igmp->tx_leave));
+  LWIP_PLATFORM_DIAG(("tx_report: %"STAT_COUNTER_F"\n", igmp->tx_report));
+}
+#endif /* IGMP_STATS || MLD6_STATS */
+
+#if MEM_STATS || MEMP_STATS
+void
+stats_display_mem(struct stats_mem *mem, const char *name)
+{
+  LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %"MEM_SIZE_F"\n\t", mem->avail));
+  LWIP_PLATFORM_DIAG(("used: %"MEM_SIZE_F"\n\t", mem->used));
+  LWIP_PLATFORM_DIAG(("max: %"MEM_SIZE_F"\n\t", mem->max));
+  LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n", mem->err));
+}
+
+#if MEMP_STATS
+void
+stats_display_memp(struct stats_mem *mem, int idx)
+{
+  if (idx < MEMP_MAX) {
+    stats_display_mem(mem, mem->name);
+  }
+}
+#endif /* MEMP_STATS */
+#endif /* MEM_STATS || MEMP_STATS */
+
+#if SYS_STATS
+void
+stats_display_sys(struct stats_sys *sys)
+{
+  LWIP_PLATFORM_DIAG(("\nSYS\n\t"));
+  LWIP_PLATFORM_DIAG(("sem.used:  %"STAT_COUNTER_F"\n\t", sys->sem.used));
+  LWIP_PLATFORM_DIAG(("sem.max:   %"STAT_COUNTER_F"\n\t", sys->sem.max));
+  LWIP_PLATFORM_DIAG(("sem.err:   %"STAT_COUNTER_F"\n\t", sys->sem.err));
+  LWIP_PLATFORM_DIAG(("mutex.used: %"STAT_COUNTER_F"\n\t", sys->mutex.used));
+  LWIP_PLATFORM_DIAG(("mutex.max:  %"STAT_COUNTER_F"\n\t", sys->mutex.max));
+  LWIP_PLATFORM_DIAG(("mutex.err:  %"STAT_COUNTER_F"\n\t", sys->mutex.err));
+  LWIP_PLATFORM_DIAG(("mbox.used:  %"STAT_COUNTER_F"\n\t", sys->mbox.used));
+  LWIP_PLATFORM_DIAG(("mbox.max:   %"STAT_COUNTER_F"\n\t", sys->mbox.max));
+  LWIP_PLATFORM_DIAG(("mbox.err:   %"STAT_COUNTER_F"\n", sys->mbox.err));
+}
+#endif /* SYS_STATS */
+
+void
+stats_display(void)
+{
+  s16_t i;
+
+  LINK_STATS_DISPLAY();
+  ETHARP_STATS_DISPLAY();
+  IPFRAG_STATS_DISPLAY();
+  IP6_FRAG_STATS_DISPLAY();
+  IP_STATS_DISPLAY();
+  ND6_STATS_DISPLAY();
+  IP6_STATS_DISPLAY();
+  IGMP_STATS_DISPLAY();
+  MLD6_STATS_DISPLAY();
+  ICMP_STATS_DISPLAY();
+  ICMP6_STATS_DISPLAY();
+  UDP_STATS_DISPLAY();
+  TCP_STATS_DISPLAY();
+  MEM_STATS_DISPLAY();
+  for (i = 0; i < MEMP_MAX; i++) {
+    MEMP_STATS_DISPLAY(i);
+  }
+  SYS_STATS_DISPLAY();
+}
+#endif /* LWIP_STATS_DISPLAY */
+
+#endif /* LWIP_STATS */
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/sys.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/sys.c
new file mode 100644
index 000000000..5f08352bf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/sys.c
@@ -0,0 +1,148 @@
+/**
+ * @file
+ * lwIP Operating System abstraction
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/**
+ * @defgroup sys_layer Porting (system abstraction layer)
+ * @ingroup lwip
+ *
+ * @defgroup sys_os OS abstraction layer
+ * @ingroup sys_layer
+ * No need to implement functions in this section in NO_SYS mode.
+ * The OS-specific code should be implemented in arch/sys_arch.h
+ * and sys_arch.c of your port.
+ * 
+ * The operating system emulation layer provides a common interface
+ * between the lwIP code and the underlying operating system kernel. The
+ * general idea is that porting lwIP to new architectures requires only
+ * small changes to a few header files and a new sys_arch
+ * implementation. It is also possible to do a sys_arch implementation
+ * that does not rely on any underlying operating system.
+ * 
+ * The sys_arch provides semaphores, mailboxes and mutexes to lwIP. For the full
+ * lwIP functionality, multiple threads support can be implemented in the
+ * sys_arch, but this is not required for the basic lwIP
+ * functionality. Timer scheduling is implemented in lwIP, but can be implemented
+ * by the sys_arch port (LWIP_TIMERS_CUSTOM==1).
+ * 
+ * In addition to the source file providing the functionality of sys_arch,
+ * the OS emulation layer must provide several header files defining
+ * macros used throughout lwip.  The files required and the macros they
+ * must define are listed below the sys_arch description.
+ * 
+ * Since lwIP 1.4.0, semaphore, mutexes and mailbox functions are prototyped in a way that
+ * allows both using pointers or actual OS structures to be used. This way, memory
+ * required for such types can be either allocated in place (globally or on the
+ * stack) or on the heap (allocated internally in the "*_new()" functions).
+ * 
+ * Note:
+ * -----
+ * Be careful with using mem_malloc() in sys_arch. When malloc() refers to
+ * mem_malloc() you can run into a circular function call problem. In mem.c
+ * mem_init() tries to allocate a semaphore using mem_malloc, which of course
+ * can't be performed when sys_arch uses mem_malloc.
+ *
+ * @defgroup sys_sem Semaphores
+ * @ingroup sys_os
+ * Semaphores can be either counting or binary - lwIP works with both
+ * kinds.
+ * Semaphores are represented by the type "sys_sem_t" which is typedef'd
+ * in the sys_arch.h file. Mailboxes are equivalently represented by the
+ * type "sys_mbox_t". Mutexes are represented by the type "sys_mutex_t".
+ * lwIP does not place any restrictions on how these types are represented
+ * internally.
+ *
+ * @defgroup sys_mutex Mutexes
+ * @ingroup sys_os
+ * Mutexes are recommended to correctly handle priority inversion,
+ * especially if you use LWIP_CORE_LOCKING .
+ *
+ * @defgroup sys_mbox Mailboxes
+ * @ingroup sys_os
+ * Mailboxes should be implemented as a queue which allows multiple messages
+ * to be posted (implementing as a rendez-vous point where only one message can be
+ * posted at a time can have a highly negative impact on performance). A message
+ * in a mailbox is just a pointer, nothing more. 
+ *
+ * @defgroup sys_time Time
+ * @ingroup sys_layer
+ *
+ * @defgroup sys_prot Critical sections
+ * @ingroup sys_layer
+ * Used to protect short regions of code against concurrent access.
+ * - Your system is a bare-metal system (probably with an RTOS)
+ *   and interrupts are under your control:
+ *   Implement this as LockInterrupts() / UnlockInterrupts()
+ * - Your system uses an RTOS with deferred interrupt handling from a
+ *   worker thread: Implement as a global mutex or lock/unlock scheduler
+ * - Your system uses a high-level OS with e.g. POSIX signals:
+ *   Implement as a global mutex
+ *
+ * @defgroup sys_misc Misc
+ * @ingroup sys_os
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+/* Most of the functions defined in sys.h must be implemented in the
+ * architecture-dependent file sys_arch.c */
+
+#if !NO_SYS
+
+#ifndef sys_msleep
+/**
+ * Sleep for some ms. Timeouts are NOT processed while sleeping.
+ *
+ * @param ms number of milliseconds to sleep
+ */
+void
+sys_msleep(u32_t ms)
+{
+  if (ms > 0) {
+    sys_sem_t delaysem;
+    err_t err = sys_sem_new(&delaysem, 0);
+    if (err == ERR_OK) {
+      sys_arch_sem_wait(&delaysem, ms);
+      sys_sem_free(&delaysem);
+    }
+  }
+}
+#endif /* sys_msleep */
+
+#endif /* !NO_SYS */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp.c
new file mode 100644
index 000000000..bd7d64ec3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp.c
@@ -0,0 +1,2686 @@
+/**
+ * @file
+ * Transmission Control Protocol for IP
+ * See also @ref tcp_raw
+ *
+ * @defgroup tcp_raw TCP
+ * @ingroup callbackstyle_api
+ * Transmission Control Protocol for IP\n
+ * @see @ref api
+ *
+ * Common functions for the TCP implementation, such as functions
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.\n
+ * 
+ * TCP connection setup
+ * --------------------
+ * The functions used for setting up connections is similar to that of
+ * the sequential API and of the BSD socket API. A new TCP connection
+ * identifier (i.e., a protocol control block - PCB) is created with the
+ * tcp_new() function. This PCB can then be either set to listen for new
+ * incoming connections or be explicitly connected to another host.
+ * - tcp_new()
+ * - tcp_bind()
+ * - tcp_listen() and tcp_listen_with_backlog()
+ * - tcp_accept()
+ * - tcp_connect()
+ * 
+ * Sending TCP data
+ * ----------------
+ * TCP data is sent by enqueueing the data with a call to tcp_write() and
+ * triggering to send by calling tcp_output(). When the data is successfully
+ * transmitted to the remote host, the application will be notified with a
+ * call to a specified callback function.
+ * - tcp_write()
+ * - tcp_output()
+ * - tcp_sent()
+ * 
+ * Receiving TCP data
+ * ------------------
+ * TCP data reception is callback based - an application specified
+ * callback function is called when new data arrives. When the
+ * application has taken the data, it has to call the tcp_recved()
+ * function to indicate that TCP can advertise increase the receive
+ * window.
+ * - tcp_recv()
+ * - tcp_recved()
+ * 
+ * Application polling
+ * -------------------
+ * When a connection is idle (i.e., no data is either transmitted or
+ * received), lwIP will repeatedly poll the application by calling a
+ * specified callback function. This can be used either as a watchdog
+ * timer for killing connections that have stayed idle for too long, or
+ * as a method of waiting for memory to become available. For instance,
+ * if a call to tcp_write() has failed because memory wasn't available,
+ * the application may use the polling functionality to call tcp_write()
+ * again when the connection has been idle for a while.
+ * - tcp_poll()
+ *
+ * Closing and aborting connections
+ * --------------------------------
+ * - tcp_close()
+ * - tcp_abort()
+ * - tcp_err()
+ * 
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/tcp.h"
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/debug.h"
+#include "lwip/stats.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/nd6.h"
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+#ifndef TCP_LOCAL_PORT_RANGE_START
+/* From http://www.iana.org/assignments/port-numbers:
+   "The Dynamic and/or Private Ports are those from 49152 through 65535" */
+#define TCP_LOCAL_PORT_RANGE_START        0xc000
+#define TCP_LOCAL_PORT_RANGE_END          0xffff
+#define TCP_ENSURE_LOCAL_PORT_RANGE(port) ((u16_t)(((port) & (u16_t)~TCP_LOCAL_PORT_RANGE_START) + TCP_LOCAL_PORT_RANGE_START))
+#endif
+
+#if LWIP_TCP_KEEPALIVE
+#define TCP_KEEP_DUR(pcb)   ((pcb)->keep_cnt * (pcb)->keep_intvl)
+#define TCP_KEEP_INTVL(pcb) ((pcb)->keep_intvl)
+#else /* LWIP_TCP_KEEPALIVE */
+#define TCP_KEEP_DUR(pcb)   TCP_MAXIDLE
+#define TCP_KEEP_INTVL(pcb) TCP_KEEPINTVL_DEFAULT
+#endif /* LWIP_TCP_KEEPALIVE */
+
+/* As initial send MSS, we use TCP_MSS but limit it to 536. */
+#if TCP_MSS > 536
+#define INITIAL_MSS 536
+#else
+#define INITIAL_MSS TCP_MSS
+#endif
+
+static const char *const tcp_state_str[] = {
+  "CLOSED",
+  "LISTEN",
+  "SYN_SENT",
+  "SYN_RCVD",
+  "ESTABLISHED",
+  "FIN_WAIT_1",
+  "FIN_WAIT_2",
+  "CLOSE_WAIT",
+  "CLOSING",
+  "LAST_ACK",
+  "TIME_WAIT"
+};
+
+/* last local TCP port */
+static u16_t tcp_port = TCP_LOCAL_PORT_RANGE_START;
+
+/* Incremented every coarse grained timer shot (typically every 500 ms). */
+u32_t tcp_ticks;
+static const u8_t tcp_backoff[13] =
+{ 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+/* Times per slowtmr hits */
+static const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 };
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs bound but not yet (connected || listening) */
+struct tcp_pcb *tcp_bound_pcbs;
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+/** An array with all (non-temporary) PCB lists, mainly used for smaller code size */
+struct tcp_pcb **const tcp_pcb_lists[] = {&tcp_listen_pcbs.pcbs, &tcp_bound_pcbs,
+         &tcp_active_pcbs, &tcp_tw_pcbs
+};
+
+u8_t tcp_active_pcbs_changed;
+
+/** Timer counter to handle calling slow-timer from tcp_tmr() */
+static u8_t tcp_timer;
+static u8_t tcp_timer_ctr;
+static u16_t tcp_new_port(void);
+
+static err_t tcp_close_shutdown_fin(struct tcp_pcb *pcb);
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+static void tcp_ext_arg_invoke_callbacks_destroyed(struct tcp_pcb_ext_args *ext_args);
+#endif
+
+/**
+ * Initialize this module.
+ */
+void
+tcp_init(void)
+{
+#ifdef LWIP_RAND
+  tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
+#endif /* LWIP_RAND */
+}
+
+/** Free a tcp pcb */
+void
+tcp_free(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+  tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
+#endif
+  memp_free(MEMP_TCP_PCB, pcb);
+}
+
+/** Free a tcp listen pcb */
+static void
+tcp_free_listen(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+  tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
+#endif
+  memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+}
+
+/**
+ * Called periodically to dispatch TCP timers.
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_slowtmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+/** Called when a listen pcb is closed. Iterates one pcb list and removes the
+ * closed listener pcb from pcb->listener if matching.
+ */
+static void
+tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
+{
+  struct tcp_pcb *pcb;
+
+  LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
+
+  for (pcb = list; pcb != NULL; pcb = pcb->next) {
+    if (pcb->listener == lpcb) {
+      pcb->listener = NULL;
+    }
+  }
+}
+#endif
+
+/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
+ * closed listener pcb from pcb->listener if matching.
+ */
+static void
+tcp_listen_closed(struct tcp_pcb *pcb)
+{
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+  size_t i;
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
+  for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
+    tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
+  }
+#endif
+  LWIP_UNUSED_ARG(pcb);
+}
+
+#if TCP_LISTEN_BACKLOG
+/** @ingroup tcp_raw
+ * Delay accepting a connection in respect to the listen backlog:
+ * the number of outstanding connections is increased until
+ * tcp_backlog_accepted() is called.
+ *
+ * ATTENTION: the caller is responsible for calling tcp_backlog_accepted()
+ * or else the backlog feature will get out of sync!
+ *
+ * @param pcb the connection pcb which is not fully accepted yet
+ */
+void
+tcp_backlog_delayed(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_ASSERT_CORE_LOCKED();
+  if ((pcb->flags & TF_BACKLOGPEND) == 0) {
+    if (pcb->listener != NULL) {
+      pcb->listener->accepts_pending++;
+      LWIP_ASSERT("accepts_pending != 0", pcb->listener->accepts_pending != 0);
+      tcp_set_flags(pcb, TF_BACKLOGPEND);
+    }
+  }
+}
+
+/** @ingroup tcp_raw
+ * A delayed-accept a connection is accepted (or closed/aborted): decreases
+ * the number of outstanding connections after calling tcp_backlog_delayed().
+ *
+ * ATTENTION: the caller is responsible for calling tcp_backlog_accepted()
+ * or else the backlog feature will get out of sync!
+ *
+ * @param pcb the connection pcb which is now fully accepted (or closed/aborted)
+ */
+void
+tcp_backlog_accepted(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_ASSERT_CORE_LOCKED();
+  if ((pcb->flags & TF_BACKLOGPEND) != 0) {
+    if (pcb->listener != NULL) {
+      LWIP_ASSERT("accepts_pending != 0", pcb->listener->accepts_pending != 0);
+      pcb->listener->accepts_pending--;
+      tcp_clear_flags(pcb, TF_BACKLOGPEND);
+    }
+  }
+}
+#endif /* TCP_LISTEN_BACKLOG */
+
+/**
+ * Closes the TX side of a connection held by the PCB.
+ * For tcp_close(), a RST is sent if the application didn't receive all data
+ * (tcp_recved() not called for all data passed to recv callback).
+ *
+ * Listening pcbs are freed and may not be referenced any more.
+ * Connection pcbs are freed if not yet connected and may not be referenced
+ * any more. If a connection is established (at least SYN received or in
+ * a closing state), the connection is closed, and put in a closing state.
+ * The pcb is then automatically freed in tcp_slowtmr(). It is therefore
+ * unsafe to reference it.
+ *
+ * @param pcb the tcp_pcb to close
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+static err_t
+tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
+{
+  LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
+
+  if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
+    if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
+      /* Not all data received by application, send RST to tell the remote
+         side about this. */
+      LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
+
+      /* don't call tcp_abort here: we must not deallocate the pcb since
+         that might not be expected when calling tcp_close */
+      tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+              pcb->local_port, pcb->remote_port);
+
+      tcp_pcb_purge(pcb);
+      TCP_RMV_ACTIVE(pcb);
+      /* Deallocate the pcb since we already sent a RST for it */
+      if (tcp_input_pcb == pcb) {
+        /* prevent using a deallocated pcb: free it from tcp_input later */
+        tcp_trigger_input_pcb_close();
+      } else {
+        tcp_free(pcb);
+      }
+      return ERR_OK;
+    }
+  }
+
+  /* - states which free the pcb are handled here,
+     - states which send FIN and change state are handled in tcp_close_shutdown_fin() */
+  switch (pcb->state) {
+    case CLOSED:
+      /* Closing a pcb in the CLOSED state might seem erroneous,
+       * however, it is in this state once allocated and as yet unused
+       * and the user needs some way to free it should the need arise.
+       * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+       * or for a pcb that has been used and then entered the CLOSED state
+       * is erroneous, but this should never happen as the pcb has in those cases
+       * been freed, and so any remaining handles are bogus. */
+      if (pcb->local_port != 0) {
+        TCP_RMV(&tcp_bound_pcbs, pcb);
+      }
+      tcp_free(pcb);
+      break;
+    case LISTEN:
+      tcp_listen_closed(pcb);
+      tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
+      tcp_free_listen(pcb);
+      break;
+    case SYN_SENT:
+      TCP_PCB_REMOVE_ACTIVE(pcb);
+      tcp_free(pcb);
+      MIB2_STATS_INC(mib2.tcpattemptfails);
+      break;
+    default:
+      return tcp_close_shutdown_fin(pcb);
+  }
+  return ERR_OK;
+}
+
+static err_t
+tcp_close_shutdown_fin(struct tcp_pcb *pcb)
+{
+  err_t err;
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+
+  switch (pcb->state) {
+    case SYN_RCVD:
+      err = tcp_send_fin(pcb);
+      if (err == ERR_OK) {
+        tcp_backlog_accepted(pcb);
+        MIB2_STATS_INC(mib2.tcpattemptfails);
+        pcb->state = FIN_WAIT_1;
+      }
+      break;
+    case ESTABLISHED:
+      err = tcp_send_fin(pcb);
+      if (err == ERR_OK) {
+        MIB2_STATS_INC(mib2.tcpestabresets);
+        pcb->state = FIN_WAIT_1;
+      }
+      break;
+    case CLOSE_WAIT:
+      err = tcp_send_fin(pcb);
+      if (err == ERR_OK) {
+        MIB2_STATS_INC(mib2.tcpestabresets);
+        pcb->state = LAST_ACK;
+      }
+      break;
+    default:
+      /* Has already been closed, do nothing. */
+      return ERR_OK;
+  }
+
+  if (err == ERR_OK) {
+    /* To ensure all data has been sent when tcp_close returns, we have
+       to make sure tcp_output doesn't fail.
+       Since we don't really have to ensure all data has been sent when tcp_close
+       returns (unsent data is sent from tcp timer functions, also), we don't care
+       for the return value of tcp_output for now. */
+    tcp_output(pcb);
+  } else if (err == ERR_MEM) {
+    /* Mark this pcb for closing. Closing is retried from tcp_tmr. */
+    tcp_set_flags(pcb, TF_CLOSEPEND);
+    /* We have to return ERR_OK from here to indicate to the callers that this
+       pcb should not be used any more as it will be freed soon via tcp_tmr.
+       This is OK here since sending FIN does not guarantee a time frime for
+       actually freeing the pcb, either (it is left in closure states for
+       remote ACK or timeout) */
+    return ERR_OK;
+  }
+  return err;
+}
+
+/**
+ * @ingroup tcp_raw
+ * Closes the connection held by the PCB.
+ *
+ * Listening pcbs are freed and may not be referenced any more.
+ * Connection pcbs are freed if not yet connected and may not be referenced
+ * any more. If a connection is established (at least SYN received or in
+ * a closing state), the connection is closed, and put in a closing state.
+ * The pcb is then automatically freed in tcp_slowtmr(). It is therefore
+ * unsafe to reference it (unless an error is returned).
+ * 
+ * The function may return ERR_MEM if no memory
+ * was available for closing the connection. If so, the application
+ * should wait and try again either by using the acknowledgment
+ * callback or the polling functionality. If the close succeeds, the
+ * function returns ERR_OK.
+ *
+ * @param pcb the tcp_pcb to close
+ * @return ERR_OK if connection has been closed
+ *         another err_t if closing failed and pcb is not freed
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
+
+  tcp_debug_print_state(pcb->state);
+
+  if (pcb->state != LISTEN) {
+    /* Set a flag not to receive any more data... */
+    tcp_set_flags(pcb, TF_RXCLOSED);
+  }
+  /* ... and close */
+  return tcp_close_shutdown(pcb, 1);
+}
+
+/**
+ * @ingroup tcp_raw
+ * Causes all or part of a full-duplex connection of this PCB to be shut down.
+ * This doesn't deallocate the PCB unless shutting down both sides!
+ * Shutting down both sides is the same as calling tcp_close, so if it succeds
+ * (i.e. returns ER_OK), the PCB must not be referenced any more!
+ *
+ * @param pcb PCB to shutdown
+ * @param shut_rx shut down receive side if this is != 0
+ * @param shut_tx shut down send side if this is != 0
+ * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down)
+ *         another err_t on error.
+ */
+err_t
+tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_shutdown: invalid pcb", pcb != NULL, return ERR_ARG);
+
+  if (pcb->state == LISTEN) {
+    return ERR_CONN;
+  }
+  if (shut_rx) {
+    /* shut down the receive side: set a flag not to receive any more data... */
+    tcp_set_flags(pcb, TF_RXCLOSED);
+    if (shut_tx) {
+      /* shutting down the tx AND rx side is the same as closing for the raw API */
+      return tcp_close_shutdown(pcb, 1);
+    }
+    /* ... and free buffered data */
+    if (pcb->refused_data != NULL) {
+      pbuf_free(pcb->refused_data);
+      pcb->refused_data = NULL;
+    }
+  }
+  if (shut_tx) {
+    /* This can't happen twice since if it succeeds, the pcb's state is changed.
+       Only close in these states as the others directly deallocate the PCB */
+    switch (pcb->state) {
+      case SYN_RCVD:
+      case ESTABLISHED:
+      case CLOSE_WAIT:
+        return tcp_close_shutdown(pcb, (u8_t)shut_rx);
+      default:
+        /* Not (yet?) connected, cannot shutdown the TX side as that would bring us
+          into CLOSED state, where the PCB is deallocated. */
+        return ERR_CONN;
+    }
+  }
+  return ERR_OK;
+}
+
+/**
+ * Abandons a connection and optionally sends a RST to the remote
+ * host.  Deletes the local protocol control block. This is done when
+ * a connection is killed because of shortage of memory.
+ *
+ * @param pcb the tcp_pcb to abort
+ * @param reset boolean to indicate whether a reset should be sent
+ */
+void
+tcp_abandon(struct tcp_pcb *pcb, int reset)
+{
+  u32_t seqno, ackno;
+#if LWIP_CALLBACK_API
+  tcp_err_fn errf;
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
+
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
+              pcb->state != LISTEN);
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    tcp_free(pcb);
+  } else {
+    int send_rst = 0;
+    u16_t local_port = 0;
+    enum tcp_state last_state;
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    if (pcb->state == CLOSED) {
+      if (pcb->local_port != 0) {
+        /* bound, not yet opened */
+        TCP_RMV(&tcp_bound_pcbs, pcb);
+      }
+    } else {
+      send_rst = reset;
+      local_port = pcb->local_port;
+      TCP_PCB_REMOVE_ACTIVE(pcb);
+    }
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_backlog_accepted(pcb);
+    if (send_rst) {
+      LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
+      tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
+    }
+    last_state = pcb->state;
+    tcp_free(pcb);
+    TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
+  }
+}
+
+/**
+ * @ingroup tcp_raw
+ * Aborts the connection by sending a RST (reset) segment to the remote
+ * host. The pcb is deallocated. This function never fails.
+ *
+ * ATTENTION: When calling this from one of the TCP callbacks, make
+ * sure you always return ERR_ABRT (and never return ERR_ABRT otherwise
+ * or you will risk accessing deallocated memory or memory leaks!
+ *
+ * @param pcb the tcp pcb to abort
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  tcp_abandon(pcb, 1);
+}
+
+/**
+ * @ingroup tcp_raw
+ * Binds the connection to a local port number and IP address. If the
+ * IP address is not given (i.e., ipaddr == IP_ANY_TYPE), the connection is
+ * bound to all local IP addresses.
+ * If another connection is bound to the same port, the function will
+ * return ERR_USE, otherwise ERR_OK is returned.
+ *
+ * @param pcb the tcp_pcb to bind (no check is done whether this pcb is
+ *        already bound!)
+ * @param ipaddr the local ip address to bind to (use IPx_ADDR_ANY to bind
+ *        to any local address
+ * @param port the local port to bind to
+ * @return ERR_USE if the port is already in use
+ *         ERR_VAL if bind failed because the PCB is not in a valid state
+ *         ERR_OK if bound
+ */
+err_t
+tcp_bind(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
+{
+  int i;
+  int max_pcb_list = NUM_TCP_PCB_LISTS;
+  struct tcp_pcb *cpcb;
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  ip_addr_t zoned_ipaddr;
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+    ipaddr = IP4_ADDR_ANY;
+  }
+#else /* LWIP_IPV4 */
+  LWIP_ERROR("tcp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+#endif /* LWIP_IPV4 */
+
+  LWIP_ERROR("tcp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
+
+  LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL);
+
+#if SO_REUSE
+  /* Unless the REUSEADDR flag is set,
+     we have to check the pcbs in TIME-WAIT state, also.
+     We do not dump TIME_WAIT pcb's; they can still be matched by incoming
+     packets using both local and remote IP addresses and ports to distinguish.
+   */
+  if (ip_get_option(pcb, SOF_REUSEADDR)) {
+    max_pcb_list = NUM_TCP_PCB_LISTS_NO_TIME_WAIT;
+  }
+#endif /* SO_REUSE */
+
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  /* If the given IP address should have a zone but doesn't, assign one now.
+   * This is legacy support: scope-aware callers should always provide properly
+   * zoned source addresses. Do the zone selection before the address-in-use
+   * check below; as such we have to make a temporary copy of the address. */
+  if (IP_IS_V6(ipaddr) && ip6_addr_lacks_zone(ip_2_ip6(ipaddr), IP6_UNICAST)) {
+    ip_addr_copy(zoned_ipaddr, *ipaddr);
+    ip6_addr_select_zone(ip_2_ip6(&zoned_ipaddr), ip_2_ip6(&zoned_ipaddr));
+    ipaddr = &zoned_ipaddr;
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  if (port == 0) {
+    port = tcp_new_port();
+    if (port == 0) {
+      return ERR_BUF;
+    }
+  } else {
+    /* Check if the address already is in use (on all lists) */
+    for (i = 0; i < max_pcb_list; i++) {
+      for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) {
+        if (cpcb->local_port == port) {
+#if SO_REUSE
+          /* Omit checking for the same port if both pcbs have REUSEADDR set.
+             For SO_REUSEADDR, the duplicate-check for a 5-tuple is done in
+             tcp_connect. */
+          if (!ip_get_option(pcb, SOF_REUSEADDR) ||
+              !ip_get_option(cpcb, SOF_REUSEADDR))
+#endif /* SO_REUSE */
+          {
+            /* @todo: check accept_any_ip_version */
+            if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) &&
+                (ip_addr_isany(&cpcb->local_ip) ||
+                 ip_addr_isany(ipaddr) ||
+                 ip_addr_cmp(&cpcb->local_ip, ipaddr))) {
+              return ERR_USE;
+            }
+          }
+        }
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)
+#if LWIP_IPV4 && LWIP_IPV6
+      || (IP_GET_TYPE(ipaddr) != IP_GET_TYPE(&pcb->local_ip))
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+     ) {
+    ip_addr_set(&pcb->local_ip, ipaddr);
+  }
+  pcb->local_port = port;
+  TCP_REG(&tcp_bound_pcbs, pcb);
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+}
+
+/**
+ * @ingroup tcp_raw
+ * Binds the connection to a netif and IP address.
+ * After calling this function, all packets received via this PCB
+ * are guaranteed to have come in via the specified netif, and all
+ * outgoing packets will go out via the specified netif.
+ *
+ * @param pcb the tcp_pcb to bind.
+ * @param netif the netif to bind to. Can be NULL.
+ */
+void
+tcp_bind_netif(struct tcp_pcb *pcb, const struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if (netif != NULL) {
+    pcb->netif_idx = netif_get_index(netif);
+  } else {
+    pcb->netif_idx = NETIF_NO_INDEX;
+  }
+}
+
+#if LWIP_CALLBACK_API
+/**
+ * Default accept callback if no accept callback is specified by the user.
+ */
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+  LWIP_UNUSED_ARG(err);
+
+  LWIP_ASSERT("tcp_accept_null: invalid pcb", pcb != NULL);
+
+  tcp_abort(pcb);
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * @ingroup tcp_raw
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ * When an incoming connection is accepted, the function specified with
+ * the tcp_accept() function will be called. The pcb has to be bound
+ * to a local port with the tcp_bind() function.
+ * 
+ * The tcp_listen() function returns a new connection identifier, and
+ * the one passed as an argument to the function will be
+ * deallocated. The reason for this behavior is that less memory is
+ * needed for a connection that is listening, so tcp_listen() will
+ * reclaim the memory needed for the original connection and allocate a
+ * new smaller memory block for the listening connection.
+ *
+ * tcp_listen() may return NULL if no memory was available for the
+ * listening connection. If so, the memory associated with the pcb
+ * passed as an argument to tcp_listen() will not be deallocated.
+ *
+ * The backlog limits the number of outstanding connections
+ * in the listen queue to the value specified by the backlog argument.
+ * To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h.
+ * 
+ * @param pcb the original tcp_pcb
+ * @param backlog the incoming connections queue limit
+ * @return tcp_pcb used for listening, consumes less memory.
+ *
+ * @note The original tcp_pcb is freed. This function therefore has to be
+ *       called like this:
+ *             tpcb = tcp_listen_with_backlog(tpcb, backlog);
+ */
+struct tcp_pcb *
+tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  return tcp_listen_with_backlog_and_err(pcb, backlog, NULL);
+}
+
+/**
+ * @ingroup tcp_raw
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ * @param pcb the original tcp_pcb
+ * @param backlog the incoming connections queue limit
+ * @param err when NULL is returned, this contains the error reason
+ * @return tcp_pcb used for listening, consumes less memory.
+ *
+ * @note The original tcp_pcb is freed. This function therefore has to be
+ *       called like this:
+ *             tpcb = tcp_listen_with_backlog_and_err(tpcb, backlog, &err);
+ */
+struct tcp_pcb *
+tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err)
+{
+  struct tcp_pcb_listen *lpcb = NULL;
+  err_t res;
+
+  LWIP_UNUSED_ARG(backlog);
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_listen_with_backlog_and_err: invalid pcb", pcb != NULL, res = ERR_ARG; goto done);
+  LWIP_ERROR("tcp_listen_with_backlog_and_err: pcb already connected", pcb->state == CLOSED, res = ERR_CLSD; goto done);
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    lpcb = (struct tcp_pcb_listen *)pcb;
+    res = ERR_ALREADY;
+    goto done;
+  }
+#if SO_REUSE
+  if (ip_get_option(pcb, SOF_REUSEADDR)) {
+    /* Since SOF_REUSEADDR allows reusing a local address before the pcb's usage
+       is declared (listen-/connection-pcb), we have to make sure now that
+       this port is only used once for every local IP. */
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((lpcb->local_port == pcb->local_port) &&
+          ip_addr_cmp(&lpcb->local_ip, &pcb->local_ip)) {
+        /* this address/port is already used */
+        lpcb = NULL;
+        res = ERR_USE;
+        goto done;
+      }
+    }
+  }
+#endif /* SO_REUSE */
+  lpcb = (struct tcp_pcb_listen *)memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    res = ERR_MEM;
+    goto done;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->prio = pcb->prio;
+  lpcb->so_options = pcb->so_options;
+  lpcb->netif_idx = NETIF_NO_INDEX;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+#if LWIP_IPV4 && LWIP_IPV6
+  IP_SET_TYPE_VAL(lpcb->remote_ip, pcb->local_ip.type);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  ip_addr_copy(lpcb->local_ip, pcb->local_ip);
+  if (pcb->local_port != 0) {
+    TCP_RMV(&tcp_bound_pcbs, pcb);
+  }
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+  /* copy over ext_args to listening pcb  */
+  memcpy(&lpcb->ext_args, &pcb->ext_args, sizeof(pcb->ext_args));
+#endif
+  tcp_free(pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+#if TCP_LISTEN_BACKLOG
+  lpcb->accepts_pending = 0;
+  tcp_backlog_set(lpcb, backlog);
+#endif /* TCP_LISTEN_BACKLOG */
+  TCP_REG(&tcp_listen_pcbs.pcbs, (struct tcp_pcb *)lpcb);
+  res = ERR_OK;
+done:
+  if (err != NULL) {
+    *err = res;
+  }
+  return (struct tcp_pcb *)lpcb;
+}
+
+/**
+ * Update the state that tracks the available window space to advertise.
+ *
+ * Returns how much extra window would be advertised if we sent an
+ * update now.
+ */
+u32_t
+tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
+{
+  u32_t new_right_edge;
+
+  LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
+  new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
+
+  if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
+    /* we can advertise more window */
+    pcb->rcv_ann_wnd = pcb->rcv_wnd;
+    return new_right_edge - pcb->rcv_ann_right_edge;
+  } else {
+    if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
+      /* Can happen due to other end sending out of advertised window,
+       * but within actual available (but not yet advertised) window */
+      pcb->rcv_ann_wnd = 0;
+    } else {
+      /* keep the right edge of window constant */
+      u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
+#if !LWIP_WND_SCALE
+      LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
+#endif
+      pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
+    }
+    return 0;
+  }
+}
+
+/**
+ * @ingroup tcp_raw
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ * @param pcb the tcp_pcb for which data is read
+ * @param len the amount of bytes that have been read by the application
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  u32_t wnd_inflation;
+  tcpwnd_size_t rcv_wnd;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
+
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
+              pcb->state != LISTEN);
+
+  rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
+  if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
+    /* window got too big or tcpwnd_size_t overflow */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
+    pcb->rcv_wnd = TCP_WND_MAX(pcb);
+  } else  {
+    pcb->rcv_wnd = rcv_wnd;
+  }
+
+  wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
+
+  /* If the change in the right edge of window is significant (default
+   * watermark is TCP_WND/4), then send an explicit update now.
+   * Otherwise wait for a packet to be sent in the normal course of
+   * events (or more window to be available later) */
+  if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
+    tcp_ack_now(pcb);
+    tcp_output(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
+                          len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
+}
+
+/**
+ * Allocate a new local TCP port.
+ *
+ * @return a new (free) local TCP port number
+ */
+static u16_t
+tcp_new_port(void)
+{
+  u8_t i;
+  u16_t n = 0;
+  struct tcp_pcb *pcb;
+
+again:
+  tcp_port++;
+  if (tcp_port == TCP_LOCAL_PORT_RANGE_END) {
+    tcp_port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  /* Check all PCB lists. */
+  for (i = 0; i < NUM_TCP_PCB_LISTS; i++) {
+    for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) {
+      if (pcb->local_port == tcp_port) {
+        n++;
+        if (n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) {
+          return 0;
+        }
+        goto again;
+      }
+    }
+  }
+  return tcp_port;
+}
+
+/**
+ * @ingroup tcp_raw
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *  Sets up the pcb to connect to the remote host and sends the
+ * initial SYN segment which opens the connection. 
+ *
+ * The tcp_connect() function returns immediately; it does not wait for
+ * the connection to be properly setup. Instead, it will call the
+ * function specified as the fourth argument (the "connected" argument)
+ * when the connection is established. If the connection could not be
+ * properly established, either because the other host refused the
+ * connection or because the other host didn't answer, the "err"
+ * callback function of this pcb (registered with tcp_err, see below)
+ * will be called.
+ *
+ * The tcp_connect() function can return ERR_MEM if no memory is
+ * available for enqueueing the SYN segment. If the SYN indeed was
+ * enqueued successfully, the tcp_connect() function returns ERR_OK.
+ *
+ * @param pcb the tcp_pcb used to establish the connection
+ * @param ipaddr the remote ip address to connect to
+ * @param port the remote tcp port to connect to
+ * @param connected callback function to call when connected (on error,
+                    the err calback will be called)
+ * @return ERR_VAL if invalid arguments are given
+ *         ERR_OK if connect request has been sent
+ *         other err_t values if connect request couldn't be sent
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port,
+            tcp_connected_fn connected)
+{
+  struct netif *netif = NULL;
+  err_t ret;
+  u32_t iss;
+  u16_t old_local_port;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("tcp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+
+  LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+
+  if (pcb->netif_idx != NETIF_NO_INDEX) {
+    netif = netif_get_by_index(pcb->netif_idx);
+  } else {
+    /* check if we have a route to the remote host */
+    netif = ip_route(&pcb->local_ip, &pcb->remote_ip);
+  }
+  if (netif == NULL) {
+    /* Don't even try to send a SYN packet if we have no route since that will fail. */
+    return ERR_RTE;
+  }
+
+  /* check if local IP has been assigned to pcb, if not, get one */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, ipaddr);
+    if (local_ip == NULL) {
+      return ERR_RTE;
+    }
+    ip_addr_copy(pcb->local_ip, *local_ip);
+  }
+
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  /* If the given IP address should have a zone but doesn't, assign one now.
+   * Given that we already have the target netif, this is easy and cheap. */
+  if (IP_IS_V6(&pcb->remote_ip) &&
+      ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST)) {
+    ip6_addr_assign_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST, netif);
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  old_local_port = pcb->local_port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+    if (pcb->local_port == 0) {
+      return ERR_BUF;
+    }
+  } else {
+#if SO_REUSE
+    if (ip_get_option(pcb, SOF_REUSEADDR)) {
+      /* Since SOF_REUSEADDR allows reusing a local address, we have to make sure
+         now that the 5-tuple is unique. */
+      struct tcp_pcb *cpcb;
+      int i;
+      /* Don't check listen- and bound-PCBs, check active- and TIME-WAIT PCBs. */
+      for (i = 2; i < NUM_TCP_PCB_LISTS; i++) {
+        for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) {
+          if ((cpcb->local_port == pcb->local_port) &&
+              (cpcb->remote_port == port) &&
+              ip_addr_cmp(&cpcb->local_ip, &pcb->local_ip) &&
+              ip_addr_cmp(&cpcb->remote_ip, ipaddr)) {
+            /* linux returns EISCONN here, but ERR_USE should be OK for us */
+            return ERR_USE;
+          }
+        }
+      }
+    }
+#endif /* SO_REUSE */
+  }
+
+  iss = tcp_next_iss(pcb);
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_wl2 = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  /* Start with a window that does not need scaling. When window scaling is
+     enabled and used, the window is enlarged when both sides agree on scaling. */
+  pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+  pcb->snd_wnd = TCP_WND;
+  /* As initial send MSS, we use TCP_MSS but limit it to 536.
+     The send MSS is updated when an MSS option is received. */
+  pcb->mss = INITIAL_MSS;
+#if TCP_CALCULATE_EFF_SEND_MSS
+  pcb->mss = tcp_eff_send_mss_netif(pcb->mss, netif, &pcb->remote_ip);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+  pcb->cwnd = 1;
+#if LWIP_CALLBACK_API
+  pcb->connected = connected;
+#else /* LWIP_CALLBACK_API */
+  LWIP_UNUSED_ARG(connected);
+#endif /* LWIP_CALLBACK_API */
+
+  /* Send a SYN together with the MSS option. */
+  ret = tcp_enqueue_flags(pcb, TCP_SYN);
+  if (ret == ERR_OK) {
+    /* SYN segment was enqueued, changed the pcbs state now */
+    pcb->state = SYN_SENT;
+    if (old_local_port != 0) {
+      TCP_RMV(&tcp_bound_pcbs, pcb);
+    }
+    TCP_REG_ACTIVE(pcb);
+    MIB2_STATS_INC(mib2.tcpactiveopens);
+
+    tcp_output(pcb);
+  }
+  return ret;
+}
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *prev;
+  tcpwnd_size_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  u8_t pcb_reset;       /* flag if a RST should be sent when removing */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+  ++tcp_timer_ctr;
+
+tcp_slowtmr_start:
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+    if (pcb->last_timer == tcp_timer_ctr) {
+      /* skip this pcb, we have already processed it */
+      prev = pcb;
+      pcb = pcb->next;
+      continue;
+    }
+    pcb->last_timer = tcp_timer_ctr;
+
+    pcb_remove = 0;
+    pcb_reset = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    } else if (pcb->nrtx >= TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      if (pcb->persist_backoff > 0) {
+        LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
+        LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
+        if (pcb->persist_probe >= TCP_MAXRTX) {
+          ++pcb_remove; /* max probes reached */
+        } else {
+          u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
+          if (pcb->persist_cnt < backoff_cnt) {
+            pcb->persist_cnt++;
+          }
+          if (pcb->persist_cnt >= backoff_cnt) {
+            int next_slot = 1; /* increment timer to next slot */
+            /* If snd_wnd is zero, send 1 byte probes */
+            if (pcb->snd_wnd == 0) {
+              if (tcp_zero_window_probe(pcb) != ERR_OK) {
+                next_slot = 0; /* try probe again with current slot */
+              }
+              /* snd_wnd not fully closed, split unsent head and fill window */
+            } else {
+              if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
+                if (tcp_output(pcb) == ERR_OK) {
+                  /* sending will cancel persist timer, else retry with current slot */
+                  next_slot = 0;
+                }
+              }
+            }
+            if (next_slot) {
+              pcb->persist_cnt = 0;
+              if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
+                pcb->persist_backoff++;
+              }
+            }
+          }
+        }
+      } else {
+        /* Increase the retransmission timer if it is running */
+        if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
+          ++pcb->rtime;
+        }
+
+        if (pcb->rtime >= pcb->rto) {
+          /* Time for a retransmission. */
+          LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F
+                                      " pcb->rto %"S16_F"\n",
+                                      pcb->rtime, pcb->rto));
+          /* If prepare phase fails but we have unsent data but no unacked data,
+             still execute the backoff calculations below, as this means we somehow
+             failed to send segment. */
+          if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
+            /* Double retransmission time-out unless we are trying to
+             * connect to somebody (i.e., we are in SYN_SENT). */
+            if (pcb->state != SYN_SENT) {
+              u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
+              int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
+              pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
+            }
+
+            /* Reset the retransmission timer. */
+            pcb->rtime = 0;
+
+            /* Reduce congestion window and ssthresh. */
+            eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+            pcb->ssthresh = eff_wnd >> 1;
+            if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
+              pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
+            }
+            pcb->cwnd = pcb->mss;
+            LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
+                                         " ssthresh %"TCPWNDSIZE_F"\n",
+                                         pcb->cwnd, pcb->ssthresh));
+            pcb->bytes_acked = 0;
+
+            /* The following needs to be called AFTER cwnd is set to one
+               mss - STJ */
+            tcp_rexmit_rto_commit(pcb);
+          }
+        }
+      }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
+      if (pcb->flags & TF_RXCLOSED) {
+        /* PCB was fully closed (either through close() or SHUT_RDWR):
+           normal FIN-WAIT timeout handling. */
+        if ((u32_t)(tcp_ticks - pcb->tmr) >
+            TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+          ++pcb_remove;
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+        }
+      }
+    }
+
+    /* Check if KEEPALIVE should be sent */
+    if (ip_get_option(pcb, SOF_KEEPALIVE) &&
+        ((pcb->state == ESTABLISHED) ||
+         (pcb->state == CLOSE_WAIT))) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
+        ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
+        LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+
+        ++pcb_remove;
+        ++pcb_reset;
+      } else if ((u32_t)(tcp_ticks - pcb->tmr) >
+                 (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
+                 / TCP_SLOW_INTERVAL) {
+        err = tcp_keepalive(pcb);
+        if (err == ERR_OK) {
+          pcb->keep_cnt_sent++;
+        }
+      }
+    }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL &&
+        (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+      tcp_free_ooseq(pcb);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+          TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      struct tcp_pcb *pcb2;
+#if LWIP_CALLBACK_API
+      tcp_err_fn err_fn = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+      void *err_arg;
+      enum tcp_state last_state;
+      tcp_pcb_purge(pcb);
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      if (pcb_reset) {
+        tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
+                pcb->local_port, pcb->remote_port);
+      }
+
+      err_arg = pcb->callback_arg;
+      last_state = pcb->state;
+      pcb2 = pcb;
+      pcb = pcb->next;
+      tcp_free(pcb2);
+
+      tcp_active_pcbs_changed = 0;
+      TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
+      if (tcp_active_pcbs_changed) {
+        goto tcp_slowtmr_start;
+      }
+    } else {
+      /* get the 'next' element now and work with 'prev' below (in case of abort) */
+      prev = pcb;
+      pcb = pcb->next;
+
+      /* We check if we should poll the connection. */
+      ++prev->polltmr;
+      if (prev->polltmr >= prev->pollinterval) {
+        prev->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        tcp_active_pcbs_changed = 0;
+        TCP_EVENT_POLL(prev, err);
+        if (tcp_active_pcbs_changed) {
+          goto tcp_slowtmr_start;
+        }
+        /* if err == ERR_ABRT, 'prev' is already deallocated */
+        if (err == ERR_OK) {
+          tcp_output(prev);
+        }
+      }
+    }
+  }
+
+
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      struct tcp_pcb *pcb2;
+      tcp_pcb_purge(pcb);
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+        LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb;
+      pcb = pcb->next;
+      tcp_free(pcb2);
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously
+ * "refused" by upper layer (application) and sends delayed ACKs or pending FINs.
+ *
+ * Automatically called from tcp_tmr().
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  ++tcp_timer_ctr;
+
+tcp_fasttmr_start:
+  pcb = tcp_active_pcbs;
+
+  while (pcb != NULL) {
+    if (pcb->last_timer != tcp_timer_ctr) {
+      struct tcp_pcb *next;
+      pcb->last_timer = tcp_timer_ctr;
+      /* send delayed ACKs */
+      if (pcb->flags & TF_ACK_DELAY) {
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+        tcp_ack_now(pcb);
+        tcp_output(pcb);
+        tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+      }
+      /* send pending FIN */
+      if (pcb->flags & TF_CLOSEPEND) {
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
+        tcp_clear_flags(pcb, TF_CLOSEPEND);
+        tcp_close_shutdown_fin(pcb);
+      }
+
+      next = pcb->next;
+
+      /* If there is data which was previously "refused" by upper layer */
+      if (pcb->refused_data != NULL) {
+        tcp_active_pcbs_changed = 0;
+        tcp_process_refused_data(pcb);
+        if (tcp_active_pcbs_changed) {
+          /* application callback has changed the pcb list: restart the loop */
+          goto tcp_fasttmr_start;
+        }
+      }
+      pcb = next;
+    } else {
+      pcb = pcb->next;
+    }
+  }
+}
+
+/** Call tcp_output for all active pcbs that have TF_NAGLEMEMERR set */
+void
+tcp_txnow(void)
+{
+  struct tcp_pcb *pcb;
+
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->flags & TF_NAGLEMEMERR) {
+      tcp_output(pcb);
+    }
+  }
+}
+
+/** Pass pcb->refused_data to the recv callback */
+err_t
+tcp_process_refused_data(struct tcp_pcb *pcb)
+{
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+  struct pbuf *rest;
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+  LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
+
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+  while (pcb->refused_data != NULL)
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+  {
+    err_t err;
+    u8_t refused_flags = pcb->refused_data->flags;
+    /* set pcb->refused_data to NULL in case the callback frees it and then
+       closes the pcb */
+    struct pbuf *refused_data = pcb->refused_data;
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+    pbuf_split_64k(refused_data, &rest);
+    pcb->refused_data = rest;
+#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+    pcb->refused_data = NULL;
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+    /* Notify again application with data previously received. */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
+    TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
+    if (err == ERR_OK) {
+      /* did refused_data include a FIN? */
+      if ((refused_flags & PBUF_FLAG_TCP_FIN)
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+          && (rest == NULL)
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+         ) {
+        /* correct rcv_wnd as the application won't call tcp_recved()
+           for the FIN's seqno */
+        if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
+          pcb->rcv_wnd++;
+        }
+        TCP_EVENT_CLOSED(pcb, err);
+        if (err == ERR_ABRT) {
+          return ERR_ABRT;
+        }
+      }
+    } else if (err == ERR_ABRT) {
+      /* if err == ERR_ABRT, 'pcb' is already deallocated */
+      /* Drop incoming packets because pcb is "full" (only if the incoming
+         segment contains data). */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
+      return ERR_ABRT;
+    } else {
+      /* data is still refused, pbuf is still valid (go on for ACK-only packets) */
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+      if (rest != NULL) {
+        pbuf_cat(refused_data, rest);
+      }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+      pcb->refused_data = refused_data;
+      return ERR_INPROGRESS;
+    }
+  }
+  return ERR_OK;
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ * @param seg tcp_seg list of TCP segments to free
+ */
+void
+tcp_segs_free(struct tcp_seg *seg)
+{
+  while (seg != NULL) {
+    struct tcp_seg *next = seg->next;
+    tcp_seg_free(seg);
+    seg = next;
+  }
+}
+
+/**
+ * Frees a TCP segment (tcp_seg structure).
+ *
+ * @param seg single tcp_seg to free
+ */
+void
+tcp_seg_free(struct tcp_seg *seg)
+{
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+}
+
+/**
+ * @ingroup tcp
+ * Sets the priority of a connection.
+ *
+ * @param pcb the tcp_pcb to manipulate
+ * @param prio new priority
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_setprio: invalid pcb", pcb != NULL, return);
+
+  pcb->prio = prio;
+}
+
+#if TCP_QUEUE_OOSEQ
+/**
+ * Returns a copy of the given TCP segment.
+ * The pbuf and data are not copied, only the pointers
+ *
+ * @param seg the old tcp_seg
+ * @return a copy of seg
+ */
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
+
+  cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+/**
+ * Default receive callback that is called if the user didn't register
+ * a recv callback for the pcb.
+ */
+err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
+
+  if (p != NULL) {
+    tcp_recved(pcb, p->tot_len);
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Kills the oldest active connection that has a lower priority than 'prio'.
+ *
+ * @param prio minimum priority
+ */
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+  mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
+
+  /* We want to kill connections with a lower prio, so bail out if 
+   * supplied prio is 0 - there can never be a lower prio
+   */
+  if (mprio == 0) {
+    return;
+  }
+
+  /* We only want kill connections with a lower prio, so decrement prio by one 
+   * and start searching for oldest connection with same or lower priority than mprio.
+   * We want to find the connections with the lowest possible prio, and among
+   * these the one with the longest inactivity time.
+   */
+  mprio--;
+
+  inactivity = 0;
+  inactive = NULL;
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+        /* lower prio is always a kill candidate */
+    if ((pcb->prio < mprio) ||
+        /* longer inactivity is also a kill candidate */
+        ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive   = pcb;
+      mprio      = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+                            (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }
+}
+
+/**
+ * Kills the oldest connection that is in specific state.
+ * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
+ */
+static void
+tcp_kill_state(enum tcp_state state)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
+
+  inactivity = 0;
+  inactive = NULL;
+  /* Go through the list of active pcbs and get the oldest pcb that is in state
+     CLOSING/LAST_ACK. */
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->state == state) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+        inactivity = tcp_ticks - pcb->tmr;
+        inactive = pcb;
+      }
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
+                            tcp_state_str[state], (void *)inactive, inactivity));
+    /* Don't send a RST, since no data is lost. */
+    tcp_abandon(inactive, 0);
+  }
+}
+
+/**
+ * Kills the oldest connection that is in TIME_WAIT state.
+ * Called from tcp_alloc() if no more connections are available.
+ */
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
+  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+                            (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }
+}
+
+/* Called when allocating a pcb fails.
+ * In this case, we want to handle all pcbs that want to close first: if we can
+ * now send the FIN (which failed before), the pcb might be in a state that is
+ * OK for us to now free it.
+ */
+static void
+tcp_handle_closepend(void)
+{
+  struct tcp_pcb *pcb = tcp_active_pcbs;
+
+  while (pcb != NULL) {
+    struct tcp_pcb *next = pcb->next;
+    /* send pending FIN */
+    if (pcb->flags & TF_CLOSEPEND) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
+      tcp_clear_flags(pcb, TF_CLOSEPEND);
+      tcp_close_shutdown_fin(pcb);
+    }
+    pcb = next;
+  }
+}
+
+/**
+ * Allocate a new tcp_pcb structure.
+ *
+ * @param prio priority for the new pcb
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
+    tcp_handle_closepend();
+
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    /* Try to allocate a tcp_pcb again. */
+    pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
+      tcp_kill_state(LAST_ACK);
+      /* Try to allocate a tcp_pcb again. */
+      pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+      if (pcb == NULL) {
+        /* Try killing oldest connection in CLOSING. */
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
+        tcp_kill_state(CLOSING);
+        /* Try to allocate a tcp_pcb again. */
+        pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+        if (pcb == NULL) {
+          /* Try killing oldest active connection with lower priority than the new one. */
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
+          tcp_kill_prio(prio);
+          /* Try to allocate a tcp_pcb again. */
+          pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
+          if (pcb != NULL) {
+            /* adjust err stats: memp_malloc failed multiple times before */
+            MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+          }
+        }
+        if (pcb != NULL) {
+          /* adjust err stats: memp_malloc failed multiple times before */
+          MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+        }
+      }
+      if (pcb != NULL) {
+        /* adjust err stats: memp_malloc failed multiple times before */
+        MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+      }
+    }
+    if (pcb != NULL) {
+      /* adjust err stats: memp_malloc failed above */
+      MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    /* zero out the whole pcb, so there is no need to initialize members to zero */
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = prio;
+    pcb->snd_buf = TCP_SND_BUF;
+    /* Start with a window that does not need scaling. When window scaling is
+       enabled and used, the window is enlarged when both sides agree on scaling. */
+    pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
+    pcb->ttl = TCP_TTL;
+    /* As initial send MSS, we use TCP_MSS but limit it to 536.
+       The send MSS is updated when an MSS option is received. */
+    pcb->mss = INITIAL_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = -1;
+    pcb->cwnd = 1;
+    pcb->tmr = tcp_ticks;
+    pcb->last_timer = tcp_timer_ctr;
+
+    /* RFC 5681 recommends setting ssthresh abritrarily high and gives an example
+    of using the largest advertised receive window.  We've seen complications with
+    receiving TCPs that use window scaling and/or window auto-tuning where the
+    initial advertised window is very small and then grows rapidly once the
+    connection is established. To avoid these complications, we set ssthresh to the
+    largest effective cwnd (amount of in-flight data) that the sender can have. */
+    pcb->ssthresh = TCP_SND_BUF;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */
+
+    /* Init KEEPALIVE timer */
+    pcb->keep_idle  = TCP_KEEPIDLE_DEFAULT;
+
+#if LWIP_TCP_KEEPALIVE
+    pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
+    pcb->keep_cnt   = TCP_KEEPCNT_DEFAULT;
+#endif /* LWIP_TCP_KEEPALIVE */
+  }
+  return pcb;
+}
+
+/**
+ * @ingroup tcp_raw
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ * The pcb is not put on any list until binding using tcp_bind().
+ * If memory is not available for creating the new pcb, NULL is returned.
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. Port reservation using tcp_bind() is implemented but
+ * allocated pcbs that are not bound can't be killed automatically if wanting
+ * to allocate a pcb with higher prio (@see tcp_kill_prio())
+ *
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/**
+ * @ingroup tcp_raw
+ * Creates a new TCP protocol control block but doesn't
+ * place it on any of the TCP PCB lists.
+ * The pcb is not put on any list until binding using tcp_bind().
+ *
+ * @param type IP address type, see @ref lwip_ip_addr_type definitions.
+ * If you want to listen to IPv4 and IPv6 (dual-stack) connections,
+ * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE.
+ * @return a new tcp_pcb that initially is in state CLOSED
+ */
+struct tcp_pcb *
+tcp_new_ip_type(u8_t type)
+{
+  struct tcp_pcb *pcb;
+  pcb = tcp_alloc(TCP_PRIO_NORMAL);
+#if LWIP_IPV4 && LWIP_IPV6
+  if (pcb != NULL) {
+    IP_SET_TYPE_VAL(pcb->local_ip, type);
+    IP_SET_TYPE_VAL(pcb->remote_ip, type);
+  }
+#else
+  LWIP_UNUSED_ARG(type);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  return pcb;
+}
+
+/**
+ * @ingroup tcp_raw
+ * Specifies the program specific state that should be passed to all
+ * other callback functions. The "pcb" argument is the current TCP
+ * connection control block, and the "arg" argument is the argument
+ * that will be passed to the callbacks.
+ *
+ * @param pcb tcp_pcb to set the callback argument
+ * @param arg void pointer argument to pass to callback functions
+ */
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  /* This function is allowed to be called for both listen pcbs and
+     connection pcbs. */
+  if (pcb != NULL) {
+    pcb->callback_arg = arg;
+  }
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * @ingroup tcp_raw
+ * Sets the callback function that will be called when new data
+ * arrives. The callback function will be passed a NULL pbuf to
+ * indicate that the remote host has closed the connection. If the
+ * callback function returns ERR_OK or ERR_ABRT it must have
+ * freed the pbuf, otherwise it must not have freed it.
+ *
+ * @param pcb tcp_pcb to set the recv callback
+ * @param recv callback function to call for this pcb when data is received
+ */
+void
+tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb != NULL) {
+    LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN);
+    pcb->recv = recv;
+  }
+}
+
+/**
+ * @ingroup tcp_raw
+ * Specifies the callback function that should be called when data has
+ * successfully been received (i.e., acknowledged) by the remote
+ * host. The len argument passed to the callback function gives the
+ * amount bytes that was acknowledged by the last acknowledgment.
+ *
+ * @param pcb tcp_pcb to set the sent callback
+ * @param sent callback function to call for this pcb when data is successfully sent
+ */
+void
+tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb != NULL) {
+    LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN);
+    pcb->sent = sent;
+  }
+}
+
+/**
+ * @ingroup tcp_raw
+ * Used to specify the function that should be called when a fatal error
+ * has occurred on the connection.
+ * 
+ * If a connection is aborted because of an error, the application is
+ * alerted of this event by the err callback. Errors that might abort a
+ * connection are when there is a shortage of memory. The callback
+ * function to be called is set using the tcp_err() function.
+ *
+ * @note The corresponding pcb is already freed when this callback is called!
+ *
+ * @param pcb tcp_pcb to set the err callback
+ * @param err callback function to call for this pcb when a fatal error
+ *        has occurred on the connection
+ */
+void
+tcp_err(struct tcp_pcb *pcb, tcp_err_fn err)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb != NULL) {
+    LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN);
+    pcb->errf = err;
+  }
+}
+
+/**
+ * @ingroup tcp_raw
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ * @param pcb tcp_pcb to set the accept callback
+ * @param accept callback function to call for this pcb when LISTENing
+ *        connection has been connected to another host
+ */
+void
+tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if ((pcb != NULL) && (pcb->state == LISTEN)) {
+    struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen *)pcb;
+    lpcb->accept = accept;
+  }
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * @ingroup tcp_raw
+ * Specifies the polling interval and the callback function that should
+ * be called to poll the application. The interval is specified in
+ * number of TCP coarse grained timer shots, which typically occurs
+ * twice a second. An interval of 10 means that the application would
+ * be polled every 5 seconds.
+ * 
+ * When a connection is idle (i.e., no data is either transmitted or
+ * received), lwIP will repeatedly poll the application by calling a
+ * specified callback function. This can be used either as a watchdog
+ * timer for killing connections that have stayed idle for too long, or
+ * as a method of waiting for memory to become available. For instance,
+ * if a call to tcp_write() has failed because memory wasn't available,
+ * the application may use the polling functionality to call tcp_write()
+ * again when the connection has been idle for a while.
+ */
+void
+tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("tcp_poll: invalid pcb", pcb != NULL, return);
+  LWIP_ASSERT("invalid socket state for poll", pcb->state != LISTEN);
+
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#else /* LWIP_CALLBACK_API */
+  LWIP_UNUSED_ARG(poll);
+#endif /* LWIP_CALLBACK_API */
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory
+ * (pcb->ooseq, pcb->unsent and pcb->unacked are freed).
+ *
+ * @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
+
+  if (pcb->state != CLOSED &&
+      pcb->state != TIME_WAIT &&
+      pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+
+    tcp_backlog_accepted(pcb);
+
+    if (pcb->refused_data != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
+      pbuf_free(pcb->refused_data);
+      pcb->refused_data = NULL;
+    }
+    if (pcb->unsent != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ
+    if (pcb->ooseq != NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+      tcp_free_ooseq(pcb);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Stop the retransmission timer as it will expect data on unacked
+       queue if it fires */
+    pcb->rtime = -1;
+
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+#if TCP_OVERSIZE
+    pcb->unsent_oversize = 0;
+#endif /* TCP_OVERSIZE */
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ * @param pcblist PCB list to purge.
+ * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
+  LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
+
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+
+  /* if there is an outstanding delayed ACKs, send it */
+  if ((pcb->state != TIME_WAIT) &&
+      (pcb->state != LISTEN) &&
+      (pcb->flags & TF_ACK_DELAY)) {
+    tcp_ack_now(pcb);
+    tcp_output(pcb);
+  }
+
+  if (pcb->state != LISTEN) {
+    LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
+    LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
+#if TCP_QUEUE_OOSEQ
+    LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
+#endif /* TCP_QUEUE_OOSEQ */
+  }
+
+  pcb->state = CLOSED;
+  /* reset the local port to prevent the pcb from being 'bound' */
+  pcb->local_port = 0;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ * @return u32_t pseudo random sequence number
+ */
+u32_t
+tcp_next_iss(struct tcp_pcb *pcb)
+{
+#ifdef LWIP_HOOK_TCP_ISN
+  LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
+  return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
+#else /* LWIP_HOOK_TCP_ISN */
+  static u32_t iss = 6510;
+
+  LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
+  LWIP_UNUSED_ARG(pcb);
+
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+#endif /* LWIP_HOOK_TCP_ISN */
+}
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+/**
+ * Calculates the effective send mss that can be used for a specific IP address
+ * by calculating the minimum of TCP_MSS and the mtu (if set) of the target
+ * netif (if not NULL).
+ */
+u16_t
+tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
+{
+  u16_t mss_s;
+  u16_t mtu;
+
+  LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
+
+  LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
+
+#if LWIP_IPV6
+#if LWIP_IPV4
+  if (IP_IS_V6(dest))
+#endif /* LWIP_IPV4 */
+  {
+    /* First look in destination cache, to see if there is a Path MTU. */
+    mtu = nd6_get_destination_mtu(ip_2_ip6(dest), outif);
+  }
+#if LWIP_IPV4
+  else
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+  {
+    if (outif == NULL) {
+      return sendmss;
+    }
+    mtu = outif->mtu;
+  }
+#endif /* LWIP_IPV4 */
+
+  if (mtu != 0) {
+    u16_t offset;
+#if LWIP_IPV6
+#if LWIP_IPV4
+    if (IP_IS_V6(dest))
+#endif /* LWIP_IPV4 */
+    {
+      offset = IP6_HLEN + TCP_HLEN;
+    }
+#if LWIP_IPV4
+    else
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+    {
+      offset = IP_HLEN + TCP_HLEN;
+    }
+#endif /* LWIP_IPV4 */
+    mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
+    /* RFC 1122, chap 4.2.2.6:
+     * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
+     * We correct for TCP options in tcp_write(), and don't support IP options.
+     */
+    sendmss = LWIP_MIN(sendmss, mss_s);
+  }
+  return sendmss;
+}
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
+static void
+tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
+{
+  struct tcp_pcb *pcb;
+  pcb = pcb_list;
+
+  LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
+
+  while (pcb != NULL) {
+    /* PCB bound to current local interface address? */
+    if (ip_addr_cmp(&pcb->local_ip, old_addr)
+#if LWIP_AUTOIP
+        /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
+        && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
+#endif /* LWIP_AUTOIP */
+       ) {
+      /* this connection must be aborted */
+      struct tcp_pcb *next = pcb->next;
+      LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+      tcp_abort(pcb);
+      pcb = next;
+    } else {
+      pcb = pcb->next;
+    }
+  }
+}
+
+/** This function is called from netif.c when address is changed or netif is removed
+ *
+ * @param old_addr IP address of the netif before change
+ * @param new_addr IP address of the netif after change or NULL if netif has been removed
+ */
+void
+tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  if (!ip_addr_isany(old_addr)) {
+    tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
+    tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
+
+    if (!ip_addr_isany(new_addr)) {
+      /* PCB bound to current local interface address? */
+      for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+        /* PCB bound to current local interface address? */
+        if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
+          /* The PCB is listening to the old ipaddr and
+            * is set to listen to the new one instead */
+          ip_addr_copy(lpcb->local_ip, *new_addr);
+        }
+      }
+    }
+  }
+}
+
+const char *
+tcp_debug_state_str(enum tcp_state s)
+{
+  return tcp_state_str[s];
+}
+
+err_t
+tcp_tcp_get_tcp_addrinfo(struct tcp_pcb *pcb, int local, ip_addr_t *addr, u16_t *port)
+{
+  if (pcb) {
+    if (local) {
+      if (addr) {
+        *addr = pcb->local_ip;
+      }
+      if (port) {
+        *port = pcb->local_port;
+      }
+    } else {
+      if (addr) {
+        *addr = pcb->remote_ip;
+      }
+      if (port) {
+        *port = pcb->remote_port;
+      }
+    }
+    return ERR_OK;
+  }
+  return ERR_VAL;
+}
+
+#if TCP_QUEUE_OOSEQ
+/* Free all ooseq pbufs (and possibly reset SACK state) */
+void
+tcp_free_ooseq(struct tcp_pcb *pcb)
+{
+  if (pcb->ooseq) {
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#if LWIP_TCP_SACK_OUT
+    memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
+#endif /* LWIP_TCP_SACK_OUT */
+  }
+}
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+/**
+ * Print a tcp header for debugging purposes.
+ *
+ * @param tcphdr pointer to a struct tcp_hdr
+ */
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
+                          lwip_ntohs(tcphdr->src), lwip_ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
+                          lwip_ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
+                          lwip_ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
+                          TCPH_HDRLEN(tcphdr),
+                          (u16_t)(TCPH_FLAGS(tcphdr) >> 5 & 1),
+                          (u16_t)(TCPH_FLAGS(tcphdr) >> 4 & 1),
+                          (u16_t)(TCPH_FLAGS(tcphdr) >> 3 & 1),
+                          (u16_t)(TCPH_FLAGS(tcphdr) >> 2 & 1),
+                          (u16_t)(TCPH_FLAGS(tcphdr) >> 1 & 1),
+                          (u16_t)(TCPH_FLAGS(tcphdr)      & 1),
+                          lwip_ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
+                          lwip_ntohs(tcphdr->chksum), lwip_ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+/**
+ * Print a tcp state for debugging purposes.
+ *
+ * @param s enum tcp_state to print
+ */
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s]));
+}
+
+/**
+ * Print tcp flags for debugging purposes.
+ *
+ * @param flags tcp flags, all active flags are printed
+ */
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+}
+
+/**
+ * Print all tcp_pcbs in every list for debugging purposes.
+ */
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *pcbl;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                            pcb->local_port, pcb->remote_port,
+                            pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for (pcbl = tcp_listen_pcbs.listen_pcbs; pcbl != NULL; pcbl = pcbl->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F" ", pcbl->local_port));
+    tcp_debug_print_state(pcbl->state);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                            pcb->local_port, pcb->remote_port,
+                            pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }
+}
+
+/**
+ * Check state consistency of the tcp_pcb lists.
+ */
+s16_t
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+/**
+ * @defgroup tcp_raw_extargs ext arguments
+ * @ingroup tcp_raw
+ * Additional data storage per tcp pcb\n
+ * @see @ref tcp_raw
+ *
+ * When LWIP_TCP_PCB_NUM_EXT_ARGS is > 0, every tcp pcb (including listen pcb)
+ * includes a number of additional argument entries in an array.
+ *
+ * To support memory management, in addition to a 'void *', callbacks can be
+ * provided to manage transition from listening pcbs to connections and to
+ * deallocate memory when a pcb is deallocated (see struct @ref tcp_ext_arg_callbacks).
+ *
+ * After allocating this index, use @ref tcp_ext_arg_set and @ref tcp_ext_arg_get
+ * to store and load arguments from this index for a given pcb.
+ */
+
+static u8_t tcp_ext_arg_id;
+
+/**
+ * @ingroup tcp_raw_extargs
+ * Allocate an index to store data in ext_args member of struct tcp_pcb.
+ * Returned value is an index in mentioned array.
+ * The index is *global* over all pcbs!
+ *
+ * When @ref LWIP_TCP_PCB_NUM_EXT_ARGS is > 0, every tcp pcb (including listen pcb)
+ * includes a number of additional argument entries in an array.
+ *
+ * To support memory management, in addition to a 'void *', callbacks can be
+ * provided to manage transition from listening pcbs to connections and to
+ * deallocate memory when a pcb is deallocated (see struct @ref tcp_ext_arg_callbacks).
+ *
+ * After allocating this index, use @ref tcp_ext_arg_set and @ref tcp_ext_arg_get
+ * to store and load arguments from this index for a given pcb.
+ *
+ * @return a unique index into struct tcp_pcb.ext_args
+ */
+u8_t
+tcp_ext_arg_alloc_id(void)
+{
+  u8_t result = tcp_ext_arg_id;
+  tcp_ext_arg_id++;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS >= 255
+#error LWIP_TCP_PCB_NUM_EXT_ARGS
+#endif
+  LWIP_ASSERT("Increase LWIP_TCP_PCB_NUM_EXT_ARGS in lwipopts.h", result < LWIP_TCP_PCB_NUM_EXT_ARGS);
+  return result;
+}
+
+/**
+ * @ingroup tcp_raw_extargs
+ * Set callbacks for a given index of ext_args on the specified pcb.
+ *
+ * @param pcb tcp_pcb for which to set the callback
+ * @param id ext_args index to set (allocated via @ref tcp_ext_arg_alloc_id)
+ * @param callbacks callback table (const since it is referenced, not copied!)
+ */
+void
+tcp_ext_arg_set_callbacks(struct tcp_pcb *pcb, uint8_t id, const struct tcp_ext_arg_callbacks * const callbacks)
+{
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_ASSERT("id < LWIP_TCP_PCB_NUM_EXT_ARGS", id < LWIP_TCP_PCB_NUM_EXT_ARGS);
+  LWIP_ASSERT("callbacks != NULL", callbacks != NULL);
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb->ext_args[id].callbacks = callbacks;
+}
+
+/**
+ * @ingroup tcp_raw_extargs
+ * Set data for a given index of ext_args on the specified pcb.
+ *
+ * @param pcb tcp_pcb for which to set the data
+ * @param id ext_args index to set (allocated via @ref tcp_ext_arg_alloc_id)
+ * @param arg data pointer to set
+ */
+void tcp_ext_arg_set(struct tcp_pcb *pcb, uint8_t id, void *arg)
+{
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_ASSERT("id < LWIP_TCP_PCB_NUM_EXT_ARGS", id < LWIP_TCP_PCB_NUM_EXT_ARGS);
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb->ext_args[id].data = arg;
+}
+
+/**
+ * @ingroup tcp_raw_extargs
+ * Set data for a given index of ext_args on the specified pcb.
+ *
+ * @param pcb tcp_pcb for which to set the data
+ * @param id ext_args index to set (allocated via @ref tcp_ext_arg_alloc_id)
+ * @return data pointer at the given index
+ */
+void *tcp_ext_arg_get(const struct tcp_pcb *pcb, uint8_t id)
+{
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_ASSERT("id < LWIP_TCP_PCB_NUM_EXT_ARGS", id < LWIP_TCP_PCB_NUM_EXT_ARGS);
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  return pcb->ext_args[id].data;
+}
+
+/** This function calls the "destroy" callback for all ext_args once a pcb is
+ * freed.
+ */
+static void
+tcp_ext_arg_invoke_callbacks_destroyed(struct tcp_pcb_ext_args *ext_args)
+{
+  int i;
+  LWIP_ASSERT("ext_args != NULL", ext_args != NULL);
+
+  for (i = 0; i < LWIP_TCP_PCB_NUM_EXT_ARGS; i++) {
+    if (ext_args[i].callbacks != NULL) {
+      if (ext_args[i].callbacks->destroy != NULL) {
+        ext_args[i].callbacks->destroy((u8_t)i, ext_args[i].data);
+      }
+    }
+  }
+}
+
+/** This function calls the "passive_open" callback for all ext_args if a connection
+ * is in the process of being accepted. This is called just after the SYN is
+ * received and before a SYN/ACK is sent, to allow to modify the very first
+ * segment sent even on passive open. Naturally, the "accepted" callback of the
+ * pcb has not been called yet!
+ */
+err_t
+tcp_ext_arg_invoke_callbacks_passive_open(struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb)
+{
+  int i;
+  LWIP_ASSERT("lpcb != NULL", lpcb != NULL);
+  LWIP_ASSERT("cpcb != NULL", cpcb != NULL);
+
+  for (i = 0; i < LWIP_TCP_PCB_NUM_EXT_ARGS; i++) {
+    if (lpcb->ext_args[i].callbacks != NULL) {
+      if (lpcb->ext_args[i].callbacks->passive_open != NULL) {
+        err_t err = lpcb->ext_args[i].callbacks->passive_open((u8_t)i, lpcb, cpcb);
+        if (err != ERR_OK) {
+          return err;
+        }
+      }
+    }
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_TCP_PCB_NUM_EXT_ARGS */
+
+#endif /* LWIP_TCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp_in.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp_in.c
new file mode 100644
index 000000000..428a6f48d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp_in.c
@@ -0,0 +1,2178 @@
+/**
+ * @file
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of the TCP layer.
+ *
+ * These functions are generally called in the order (ip_input() ->)
+ * tcp_input() -> * tcp_process() -> tcp_receive() (-> application).
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#if LWIP_ND6_TCP_REACHABILITY_HINTS
+#include "lwip/nd6.h"
+#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/** Initial CWND calculation as defined RFC 2581 */
+#define LWIP_TCP_CALC_INITIAL_CWND(mss) ((tcpwnd_size_t)LWIP_MIN((4U * (mss)), LWIP_MAX((2U * (mss)), 4380U)))
+
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static u16_t tcphdr_optlen;
+static u16_t tcphdr_opt1len;
+static u8_t *tcphdr_opt2;
+static u16_t tcp_optidx;
+static u32_t seqno, ackno;
+static tcpwnd_size_t recv_acked;
+static u16_t tcplen;
+static u8_t flags;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static void tcp_listen_input(struct tcp_pcb_listen *pcb);
+static void tcp_timewait_input(struct tcp_pcb *pcb);
+
+static int tcp_input_delayed_close(struct tcp_pcb *pcb);
+
+#if LWIP_TCP_SACK_OUT
+static void tcp_add_sack(struct tcp_pcb *pcb, u32_t left, u32_t right);
+static void tcp_remove_sacks_lt(struct tcp_pcb *pcb, u32_t seq);
+#if defined(TCP_OOSEQ_BYTES_LIMIT) || defined(TCP_OOSEQ_PBUFS_LIMIT)
+static void tcp_remove_sacks_gt(struct tcp_pcb *pcb, u32_t seq);
+#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
+#endif /* LWIP_TCP_SACK_OUT */
+
+/**
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ *
+ * @param p received TCP segment to process (p->payload pointing to the TCP header)
+ * @param inp network interface on which this segment was received
+ */
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+#if SO_REUSE
+  struct tcp_pcb *lpcb_prev = NULL;
+  struct tcp_pcb_listen *lpcb_any = NULL;
+#endif /* SO_REUSE */
+  u8_t hdrlen_bytes;
+  err_t err;
+
+  LWIP_UNUSED_ARG(inp);
+  LWIP_ASSERT_CORE_LOCKED();
+  LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+  MIB2_STATS_INC(mib2.tcpinsegs);
+
+  tcphdr = (struct tcp_hdr *)p->payload;
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* Check that TCP header fits in payload */
+  if (p->len < TCP_HLEN) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    goto dropped;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
+      ip_addr_ismulticast(ip_current_dest_addr())) {
+    TCP_STATS_INC(tcp.proterr);
+    goto dropped;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_TCP) {
+    /* Verify TCP checksum. */
+    u16_t chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
+                                    ip_current_src_addr(), ip_current_dest_addr());
+    if (chksum != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
+                                    chksum));
+      tcp_debug_print(tcphdr);
+      TCP_STATS_INC(tcp.chkerr);
+      goto dropped;
+    }
+  }
+#endif /* CHECKSUM_CHECK_TCP */
+
+  /* sanity-check header length */
+  hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
+  if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: invalid header length (%"U16_F")\n", (u16_t)hdrlen_bytes));
+    TCP_STATS_INC(tcp.lenerr);
+    goto dropped;
+  }
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
+  tcphdr_opt2 = NULL;
+  if (p->len >= hdrlen_bytes) {
+    /* all options are in the first pbuf */
+    tcphdr_opt1len = tcphdr_optlen;
+    pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
+  } else {
+    u16_t opt2len;
+    /* TCP header fits into first pbuf, options don't - data is in the next pbuf */
+    /* there must be a next pbuf, due to hdrlen_bytes sanity check above */
+    LWIP_ASSERT("p->next != NULL", p->next != NULL);
+
+    /* advance over the TCP header (cannot fail) */
+    pbuf_remove_header(p, TCP_HLEN);
+
+    /* determine how long the first and second parts of the options are */
+    tcphdr_opt1len = p->len;
+    opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
+
+    /* options continue in the next pbuf: set p to zero length and hide the
+        options in the next pbuf (adjusting p->tot_len) */
+    pbuf_remove_header(p, tcphdr_opt1len);
+
+    /* check that the options fit in the second pbuf */
+    if (opt2len > p->next->len) {
+      /* drop short packets */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: options overflow second pbuf (%"U16_F" bytes)\n", p->next->len));
+      TCP_STATS_INC(tcp.lenerr);
+      goto dropped;
+    }
+
+    /* remember the pointer to the second part of the options */
+    tcphdr_opt2 = (u8_t *)p->next->payload;
+
+    /* advance p->next to point after the options, and manually
+        adjust p->tot_len to keep it consistent with the changed p->next */
+    pbuf_remove_header(p->next, opt2len);
+    p->tot_len = (u16_t)(p->tot_len - opt2len);
+
+    LWIP_ASSERT("p->len == 0", p->len == 0);
+    LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
+  }
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = lwip_ntohs(tcphdr->src);
+  tcphdr->dest = lwip_ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
+  tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr);
+  tcplen = p->tot_len;
+  if (flags & (TCP_FIN | TCP_SYN)) {
+    tcplen++;
+    if (tcplen < p->tot_len) {
+      /* u16_t overflow, cannot handle this */
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: length u16_t overflow, cannot handle this\n"));
+      TCP_STATS_INC(tcp.lenerr);
+      goto dropped;
+    }
+  }
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+  for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+
+    /* check if PCB is bound to specific netif */
+    if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+        (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+      prev = pcb;
+      continue;
+    }
+
+    if (pcb->remote_port == tcphdr->src &&
+        pcb->local_port == tcphdr->dest &&
+        ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
+        ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+        prev->next = pcb->next;
+        pcb->next = tcp_active_pcbs;
+        tcp_active_pcbs = pcb;
+      } else {
+        TCP_STATS_INC(tcp.cachehit);
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+    for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+
+      /* check if PCB is bound to specific netif */
+      if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+          (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+        continue;
+      }
+
+      if (pcb->remote_port == tcphdr->src &&
+          pcb->local_port == tcphdr->dest &&
+          ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
+          ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+        /* We don't really care enough to move this PCB to the front
+           of the list since we are not very likely to receive that
+           many segments for connections in TIME-WAIT. */
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+#ifdef LWIP_HOOK_TCP_INPACKET_PCB
+        if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
+                                       tcphdr_opt2, p) == ERR_OK)
+#endif
+        {
+          tcp_timewait_input(pcb);
+        }
+        pbuf_free(p);
+        return;
+      }
+    }
+
+    /* Finally, if we still did not get a match, we check all PCBs that
+       are LISTENing for incoming connections. */
+    prev = NULL;
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* check if PCB is bound to specific netif */
+      if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
+          (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+        prev = (struct tcp_pcb *)lpcb;
+        continue;
+      }
+
+      if (lpcb->local_port == tcphdr->dest) {
+        if (IP_IS_ANY_TYPE_VAL(lpcb->local_ip)) {
+          /* found an ANY TYPE (IPv4/IPv6) match */
+#if SO_REUSE
+          lpcb_any = lpcb;
+          lpcb_prev = prev;
+#else /* SO_REUSE */
+          break;
+#endif /* SO_REUSE */
+        } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
+          if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
+            /* found an exact match */
+            break;
+          } else if (ip_addr_isany(&lpcb->local_ip)) {
+            /* found an ANY-match */
+#if SO_REUSE
+            lpcb_any = lpcb;
+            lpcb_prev = prev;
+#else /* SO_REUSE */
+            break;
+#endif /* SO_REUSE */
+          }
+        }
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+#if SO_REUSE
+    /* first try specific local IP */
+    if (lpcb == NULL) {
+      /* only pass to ANY if no specific local IP has been found */
+      lpcb = lpcb_any;
+      prev = lpcb_prev;
+    }
+#endif /* SO_REUSE */
+    if (lpcb != NULL) {
+      /* Move this PCB to the front of the list so that subsequent
+         lookups will be faster (we exploit locality in TCP segment
+         arrivals). */
+      if (prev != NULL) {
+        ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+        /* our successor is the remainder of the listening list */
+        lpcb->next = tcp_listen_pcbs.listen_pcbs;
+        /* put this listening pcb at the head of the listening list */
+        tcp_listen_pcbs.listen_pcbs = lpcb;
+      } else {
+        TCP_STATS_INC(tcp.cachehit);
+      }
+
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+#ifdef LWIP_HOOK_TCP_INPACKET_PCB
+      if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
+                                     tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
+#endif
+      {
+        tcp_listen_input(lpcb);
+      }
+      pbuf_free(p);
+      return;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+#ifdef LWIP_HOOK_TCP_INPACKET_PCB
+  if ((pcb != NULL) && LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen,
+      tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
+    pbuf_free(p);
+    return;
+  }
+#endif
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+    recv_acked = 0;
+
+    if (flags & TCP_PSH) {
+      p->flags |= PBUF_FLAG_PUSH;
+    }
+
+    /* If there is data which was previously "refused" by upper layer */
+    if (pcb->refused_data != NULL) {
+      if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
+          ((pcb->refused_data != NULL) && (tcplen > 0))) {
+        /* pcb has been aborted or refused data is still refused and the new
+           segment contains data */
+        if (pcb->rcv_ann_wnd == 0) {
+          /* this is a zero-window probe, we respond to it with current RCV.NXT
+          and drop the data segment */
+          tcp_send_empty_ack(pcb);
+        }
+        TCP_STATS_INC(tcp.drop);
+        MIB2_STATS_INC(mib2.tcpinerrs);
+        goto aborted;
+      }
+    }
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+        /* TF_RESET means that the connection was reset by the other
+           end. We then call the error callback to inform the
+           application that the connection is dead before we
+           deallocate the PCB. */
+        TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
+        tcp_pcb_remove(&tcp_active_pcbs, pcb);
+        tcp_free(pcb);
+      } else {
+        err = ERR_OK;
+        /* If the application has registered a "sent" function to be
+           called when new send buffer space is available, we call it
+           now. */
+        if (recv_acked > 0) {
+          u16_t acked16;
+#if LWIP_WND_SCALE
+          /* recv_acked is u32_t but the sent callback only takes a u16_t,
+             so we might have to call it multiple times. */
+          u32_t acked = recv_acked;
+          while (acked > 0) {
+            acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
+            acked -= acked16;
+#else
+          {
+            acked16 = recv_acked;
+#endif
+            TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
+            if (err == ERR_ABRT) {
+              goto aborted;
+            }
+          }
+          recv_acked = 0;
+        }
+        if (tcp_input_delayed_close(pcb)) {
+          goto aborted;
+        }
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+        while (recv_data != NULL) {
+          struct pbuf *rest = NULL;
+          pbuf_split_64k(recv_data, &rest);
+#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+        if (recv_data != NULL) {
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+          LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
+          if (pcb->flags & TF_RXCLOSED) {
+            /* received data although already closed -> abort (send RST) to
+               notify the remote host that not all data has been processed */
+            pbuf_free(recv_data);
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+            if (rest != NULL) {
+              pbuf_free(rest);
+            }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+            tcp_abort(pcb);
+            goto aborted;
+          }
+
+          /* Notify application that data has been received. */
+          TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+          if (err == ERR_ABRT) {
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+            if (rest != NULL) {
+              pbuf_free(rest);
+            }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+            goto aborted;
+          }
+
+          /* If the upper layer can't receive this data, store it */
+          if (err != ERR_OK) {
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+            if (rest != NULL) {
+              pbuf_cat(recv_data, rest);
+            }
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+            pcb->refused_data = recv_data;
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n"));
+#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+            break;
+          } else {
+            /* Upper layer received the data, go on with the rest if > 64K */
+            recv_data = rest;
+#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+          }
+        }
+
+        /* If a FIN segment was received, we call the callback
+           function with a NULL buffer to indicate EOF. */
+        if (recv_flags & TF_GOT_FIN) {
+          if (pcb->refused_data != NULL) {
+            /* Delay this if we have refused data. */
+            pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
+          } else {
+            /* correct rcv_wnd as the application won't call tcp_recved()
+               for the FIN's seqno */
+            if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
+              pcb->rcv_wnd++;
+            }
+            TCP_EVENT_CLOSED(pcb, err);
+            if (err == ERR_ABRT) {
+              goto aborted;
+            }
+          }
+        }
+
+        tcp_input_pcb = NULL;
+        if (tcp_input_delayed_close(pcb)) {
+          goto aborted;
+        }
+        /* Try to send something out. */
+        tcp_output(pcb);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+        tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+      }
+    }
+    /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
+       Below this line, 'pcb' may not be dereferenced! */
+aborted:
+    tcp_input_pcb = NULL;
+    recv_data = NULL;
+
+    /* give up our reference to inseg.p */
+    if (inseg.p != NULL) {
+      pbuf_free(inseg.p);
+      inseg.p = NULL;
+    }
+  } else {
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
+              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+  return;
+dropped:
+  TCP_STATS_INC(tcp.drop);
+  MIB2_STATS_INC(mib2.tcpinerrs);
+  pbuf_free(p);
+}
+
+/** Called from tcp_input to check for TF_CLOSED flag. This results in closing
+ * and deallocating a pcb at the correct place to ensure noone references it
+ * any more.
+ * @returns 1 if the pcb has been closed and deallocated, 0 otherwise
+ */
+static int
+tcp_input_delayed_close(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
+
+  if (recv_flags & TF_CLOSED) {
+    /* The connection has been closed and we will deallocate the
+        PCB. */
+    if (!(pcb->flags & TF_RXCLOSED)) {
+      /* Connection closed although the application has only shut down the
+          tx side: call the PCB's err callback and indicate the closure to
+          ensure the application doesn't continue using the PCB. */
+      TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
+    }
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    tcp_free(pcb);
+    return 1;
+  }
+  return 0;
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection (from tcp_input()).
+ *
+ * @param pcb the tcp_pcb_listen for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static void
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  u32_t iss;
+  err_t rc;
+
+  if (flags & TCP_RST) {
+    /* An incoming RST should be ignored. Return. */
+    return;
+  }
+
+  LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+            ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
+#if TCP_LISTEN_BACKLOG
+    if (pcb->accepts_pending >= pcb->backlog) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest));
+      return;
+    }
+#endif /* TCP_LISTEN_BACKLOG */
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      err_t err;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
+      LWIP_UNUSED_ARG(err); /* err not useful here */
+      return;
+    }
+#if TCP_LISTEN_BACKLOG
+    pcb->accepts_pending++;
+    tcp_set_flags(npcb, TF_BACKLOGPEND);
+#endif /* TCP_LISTEN_BACKLOG */
+    /* Set up the new PCB. */
+    ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
+    ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
+    npcb->local_port = pcb->local_port;
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->rcv_ann_right_edge = npcb->rcv_nxt;
+    iss = tcp_next_iss(npcb);
+    npcb->snd_wl2 = iss;
+    npcb->snd_nxt = iss;
+    npcb->lastack = iss;
+    npcb->snd_lbb = iss;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+    npcb->listener = pcb;
+#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & SOF_INHERITED;
+    npcb->netif_idx = pcb->netif_idx;
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG_ACTIVE(npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->snd_wnd_max = npcb->snd_wnd;
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+    npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+    MIB2_STATS_INC(mib2.tcppassiveopens);
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+    if (tcp_ext_arg_invoke_callbacks_passive_open(pcb, npcb) != ERR_OK) {
+      tcp_abandon(npcb, 0);
+      return;
+    }
+#endif
+
+    /* Send a SYN|ACK together with the MSS option. */
+    rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
+    if (rc != ERR_OK) {
+      tcp_abandon(npcb, 0);
+      return;
+    }
+    tcp_output(npcb);
+  }
+  return;
+}
+
+/**
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static void
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
+  /* RFC 793 3.9 Event Processing - Segment Arrives:
+   * - first check sequence number - we skip that one in TIME_WAIT (always
+   *   acceptable since we only send ACKs)
+   * - second check the RST bit (... return) */
+  if (flags & TCP_RST) {
+    return;
+  }
+
+  LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
+
+  /* - fourth, check the SYN bit, */
+  if (flags & TCP_SYN) {
+    /* If an incoming segment is not acceptable, an acknowledgment
+       should be sent in reply */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
+      /* If the SYN is in the window it is an error, send a reset */
+      tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+              ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+      return;
+    }
+  } else if (flags & TCP_FIN) {
+    /* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
+         Restart the 2 MSL time-wait timeout.*/
+    pcb->tmr = tcp_ticks;
+  }
+
+  if ((tcplen > 0)) {
+    /* Acknowledge data, FIN or out-of-window SYN */
+    tcp_ack_now(pcb);
+    tcp_output(pcb);
+  }
+  return;
+}
+
+/**
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ *
+ * @note the segment which arrived is saved in global variables, therefore only the pcb
+ *       involved is passed as a parameter to this function
+ */
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+
+  err = ERR_OK;
+
+  LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      /* "In the SYN-SENT state (a RST received in response to an initial SYN),
+          the RST is acceptable if the ACK field acknowledges the SYN." */
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      /* "In all states except SYN-SENT, all reset (RST) segments are validated
+          by checking their SEQ-fields." */
+      if (seqno == pcb->rcv_nxt) {
+        acceptable = 1;
+      } else  if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+                                  pcb->rcv_nxt + pcb->rcv_wnd)) {
+        /* If the sequence number is inside the window, we send a challenge ACK
+           and wait for a re-send with matching sequence number.
+           This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
+           (RST spoofing attack), which is present in RFC 793 RST handling. */
+        tcp_ack_now(pcb);
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags |= TF_RESET;
+      tcp_clear_flags(pcb, TF_ACK_DELAY);
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+                                    seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+                              seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
+    /* Cope with new connection attempt after remote end crashed */
+    tcp_ack_now(pcb);
+    return ERR_OK;
+  }
+
+  if ((pcb->flags & TF_RXCLOSED) == 0) {
+    /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
+    pcb->tmr = tcp_ticks;
+  }
+  pcb->keep_cnt_sent = 0;
+  pcb->persist_probe = 0;
+
+  tcp_parseopt(pcb);
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+    case SYN_SENT:
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+                                    pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
+      /* received SYN ACK with expected sequence number? */
+      if ((flags & TCP_ACK) && (flags & TCP_SYN)
+          && (ackno == pcb->lastack + 1)) {
+        pcb->rcv_nxt = seqno + 1;
+        pcb->rcv_ann_right_edge = pcb->rcv_nxt;
+        pcb->lastack = ackno;
+        pcb->snd_wnd = tcphdr->wnd;
+        pcb->snd_wnd_max = pcb->snd_wnd;
+        pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+        pcb->state = ESTABLISHED;
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+        pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+        pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
+        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
+                                     " ssthresh %"TCPWNDSIZE_F"\n",
+                                     pcb->cwnd, pcb->ssthresh));
+        LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
+        --pcb->snd_queuelen;
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
+        rseg = pcb->unacked;
+        if (rseg == NULL) {
+          /* might happen if tcp_output fails in tcp_rexmit_rto()
+             in which case the segment is on the unsent list */
+          rseg = pcb->unsent;
+          LWIP_ASSERT("no segment to free", rseg != NULL);
+          pcb->unsent = rseg->next;
+        } else {
+          pcb->unacked = rseg->next;
+        }
+        tcp_seg_free(rseg);
+
+        /* If there's nothing left to acknowledge, stop the retransmit
+           timer, otherwise reset it to start again */
+        if (pcb->unacked == NULL) {
+          pcb->rtime = -1;
+        } else {
+          pcb->rtime = 0;
+          pcb->nrtx = 0;
+        }
+
+        /* Call the user specified function to call when successfully
+         * connected. */
+        TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+        if (err == ERR_ABRT) {
+          return ERR_ABRT;
+        }
+        tcp_ack_now(pcb);
+      }
+      /* received ACK? possibly a half-open connection */
+      else if (flags & TCP_ACK) {
+        /* send a RST to bring the other side in a non-synchronized state. */
+        tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+                ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+        /* Resend SYN immediately (don't wait for rto timeout) to establish
+          connection faster, but do not send more SYNs than we otherwise would
+          have, or we might get caught in a loop on loopback interfaces. */
+        if (pcb->nrtx < TCP_SYNMAXRTX) {
+          pcb->rtime = 0;
+          tcp_rexmit_rto(pcb);
+        }
+      }
+      break;
+    case SYN_RCVD:
+      if (flags & TCP_ACK) {
+        /* expected ACK number? */
+        if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+          pcb->state = ESTABLISHED;
+          LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+          if (pcb->listener == NULL) {
+            /* listen pcb might be closed by now */
+            err = ERR_VAL;
+          } else
+#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
+          {
+#if LWIP_CALLBACK_API
+            LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
+#endif
+            tcp_backlog_accepted(pcb);
+            /* Call the accept function. */
+            TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
+          }
+          if (err != ERR_OK) {
+            /* If the accept function returns with an error, we abort
+             * the connection. */
+            /* Already aborted? */
+            if (err != ERR_ABRT) {
+              tcp_abort(pcb);
+            }
+            return ERR_ABRT;
+          }
+          /* If there was any data contained within this ACK,
+           * we'd better pass it on to the application as well. */
+          tcp_receive(pcb);
+
+          /* Prevent ACK for SYN to generate a sent event */
+          if (recv_acked != 0) {
+            recv_acked--;
+          }
+
+          pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
+                                       " ssthresh %"TCPWNDSIZE_F"\n",
+                                       pcb->cwnd, pcb->ssthresh));
+
+          if (recv_flags & TF_GOT_FIN) {
+            tcp_ack_now(pcb);
+            pcb->state = CLOSE_WAIT;
+          }
+        } else {
+          /* incorrect ACK number, send RST */
+          tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
+                  ip_current_src_addr(), tcphdr->dest, tcphdr->src);
+        }
+      } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
+        /* Looks like another copy of the SYN - retransmit our SYN-ACK */
+        tcp_rexmit(pcb);
+      }
+      break;
+    case CLOSE_WAIT:
+    /* FALLTHROUGH */
+    case ESTABLISHED:
+      tcp_receive(pcb);
+      if (recv_flags & TF_GOT_FIN) { /* passive close */
+        tcp_ack_now(pcb);
+        pcb->state = CLOSE_WAIT;
+      }
+      break;
+    case FIN_WAIT_1:
+      tcp_receive(pcb);
+      if (recv_flags & TF_GOT_FIN) {
+        if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+            pcb->unsent == NULL) {
+          LWIP_DEBUGF(TCP_DEBUG,
+                      ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+          tcp_ack_now(pcb);
+          tcp_pcb_purge(pcb);
+          TCP_RMV_ACTIVE(pcb);
+          pcb->state = TIME_WAIT;
+          TCP_REG(&tcp_tw_pcbs, pcb);
+        } else {
+          tcp_ack_now(pcb);
+          pcb->state = CLOSING;
+        }
+      } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
+                 pcb->unsent == NULL) {
+        pcb->state = FIN_WAIT_2;
+      }
+      break;
+    case FIN_WAIT_2:
+      tcp_receive(pcb);
+      if (recv_flags & TF_GOT_FIN) {
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+        tcp_pcb_purge(pcb);
+        TCP_RMV_ACTIVE(pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      }
+      break;
+    case CLOSING:
+      tcp_receive(pcb);
+      if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_pcb_purge(pcb);
+        TCP_RMV_ACTIVE(pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      }
+      break;
+    case LAST_ACK:
+      tcp_receive(pcb);
+      if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
+        recv_flags |= TF_CLOSED;
+      }
+      break;
+    default:
+      break;
+  }
+  return ERR_OK;
+}
+
+#if TCP_QUEUE_OOSEQ
+/**
+ * Insert segment into the list (segments covered with new one will be deleted)
+ *
+ * Called from tcp_receive()
+ */
+static void
+tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
+{
+  struct tcp_seg *old_seg;
+
+  LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
+
+  if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+    /* received segment overlaps all following segments */
+    tcp_segs_free(next);
+    next = NULL;
+  } else {
+    /* delete some following segments
+       oos queue may have segments with FIN flag */
+    while (next &&
+           TCP_SEQ_GEQ((seqno + cseg->len),
+                       (next->tcphdr->seqno + next->len))) {
+      /* cseg with FIN already processed */
+      if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+        TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
+      }
+      old_seg = next;
+      next = next->next;
+      tcp_seg_free(old_seg);
+    }
+    if (next &&
+        TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
+      /* We need to trim the incoming segment. */
+      cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
+      pbuf_realloc(cseg->p, cseg->len);
+    }
+  }
+  cseg->next = next;
+}
+#endif /* TCP_QUEUE_OOSEQ */
+
+/** Remove segments from a list if the incoming ACK acknowledges them */
+static struct tcp_seg *
+tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
+                        struct tcp_seg *dbg_other_seg_list)
+{
+  struct tcp_seg *next;
+  u16_t clen;
+
+  LWIP_UNUSED_ARG(dbg_list_name);
+  LWIP_UNUSED_ARG(dbg_other_seg_list);
+
+  while (seg_list != NULL &&
+         TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
+                     TCP_TCPLEN(seg_list), ackno)) {
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
+                                  lwip_ntohl(seg_list->tcphdr->seqno),
+                                  lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
+                                  dbg_list_name));
+
+    next = seg_list;
+    seg_list = seg_list->next;
+
+    clen = pbuf_clen(next->p);
+    LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
+                                 (tcpwnd_size_t)pcb->snd_queuelen));
+    LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
+
+    pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
+    recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
+    tcp_seg_free(next);
+
+    LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
+                                 (tcpwnd_size_t)pcb->snd_queuelen,
+                                 dbg_list_name));
+    if (pcb->snd_queuelen != 0) {
+      LWIP_ASSERT("tcp_receive: valid queue length",
+                  seg_list != NULL || dbg_other_seg_list != NULL);
+    }
+  }
+  return seg_list;
+}
+
+/**
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, it places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ *
+ * Called from tcp_process().
+ */
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+  s16_t m;
+  u32_t right_wnd_edge;
+  int found_dupack = 0;
+
+  LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
+  LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+        (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+        (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
+      pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
+      /* keep track of the biggest window announced by the remote host to calculate
+         the maximum segment size */
+      if (pcb->snd_wnd_max < pcb->snd_wnd) {
+        pcb->snd_wnd_max = pcb->snd_wnd;
+      }
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"TCPWNDSIZE_F"\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != (tcpwnd_size_t)SND_WND_SCALE(pcb, tcphdr->wnd)) {
+        LWIP_DEBUGF(TCP_WND_DEBUG,
+                    ("tcp_receive: no window update lastack %"U32_F" ackno %"
+                     U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
+                     pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+    /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a
+     * duplicate ack if:
+     * 1) It doesn't ACK new data
+     * 2) length of received packet is zero (i.e. no payload)
+     * 3) the advertised window hasn't changed
+     * 4) There is outstanding unacknowledged data (retransmission timer running)
+     * 5) The ACK is == biggest ACK sequence number so far seen (snd_una)
+     *
+     * If it passes all five, should process as a dupack:
+     * a) dupacks < 3: do nothing
+     * b) dupacks == 3: fast retransmit
+     * c) dupacks > 3: increase cwnd
+     *
+     * If it only passes 1-3, should reset dupack counter (and add to
+     * stats, which we don't do in lwIP)
+     *
+     * If it only passes 1, should reset dupack counter
+     *
+     */
+
+    /* Clause 1 */
+    if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
+      /* Clause 2 */
+      if (tcplen == 0) {
+        /* Clause 3 */
+        if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
+          /* Clause 4 */
+          if (pcb->rtime >= 0) {
+            /* Clause 5 */
+            if (pcb->lastack == ackno) {
+              found_dupack = 1;
+              if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
+                ++pcb->dupacks;
+              }
+              if (pcb->dupacks > 3) {
+                /* Inflate the congestion window */
+                TCP_WND_INC(pcb->cwnd, pcb->mss);
+              }
+              if (pcb->dupacks >= 3) {
+                /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
+                tcp_rexmit_fast(pcb);
+              }
+            }
+          }
+        }
+      }
+      /* If Clause (1) or more is true, but not a duplicate ack, reset
+       * count of consecutive duplicate acks */
+      if (!found_dupack) {
+        pcb->dupacks = 0;
+      }
+    } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
+      /* We come here when the ACK acknowledges new data. */
+      tcpwnd_size_t acked;
+
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        tcp_clear_flags(pcb, TF_INFR);
+        pcb->cwnd = pcb->ssthresh;
+        pcb->bytes_acked = 0;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
+
+      /* Record how much data this ACK acks */
+      acked = (tcpwnd_size_t)(ackno - pcb->lastack);
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          tcpwnd_size_t increase;
+          /* limit to 1 SMSS segment during period following RTO */
+          u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
+          /* RFC 3465, section 2.2 Slow Start */
+          increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
+          TCP_WND_INC(pcb->cwnd, increase);
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
+        } else {
+          /* RFC 3465, section 2.1 Congestion Avoidance */
+          TCP_WND_INC(pcb->bytes_acked, acked);
+          if (pcb->bytes_acked >= pcb->cwnd) {
+            pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
+            TCP_WND_INC(pcb->cwnd, pcb->mss);
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
+                                    ackno,
+                                    pcb->unacked != NULL ?
+                                    lwip_ntohl(pcb->unacked->tcphdr->seqno) : 0,
+                                    pcb->unacked != NULL ?
+                                    lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowledges them. */
+      pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
+      /* We go through the ->unsent list to see if any of the segments
+         on the list are acknowledged by the ACK. This may seem
+         strange since an "unsent" segment shouldn't be acked. The
+         rationale is that lwIP puts all outstanding segments on the
+         ->unsent list after a retransmission, so these segments may
+         in fact have been sent once. */
+      pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
+
+      /* If there's nothing left to acknowledge, stop the retransmit
+         timer, otherwise reset it to start again */
+      if (pcb->unacked == NULL) {
+        pcb->rtime = -1;
+      } else {
+        pcb->rtime = 0;
+      }
+
+      pcb->polltmr = 0;
+
+#if TCP_OVERSIZE
+      if (pcb->unsent == NULL) {
+        pcb->unsent_oversize = 0;
+      }
+#endif /* TCP_OVERSIZE */
+
+#if LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS
+      if (ip_current_is_v6()) {
+        /* Inform neighbor reachability of forward progress. */
+        nd6_reachability_hint(ip6_current_src_addr());
+      }
+#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
+
+      pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
+      /* check if this ACK ends our retransmission of in-flight data */
+      if (pcb->flags & TF_RTO) {
+        /* RTO is done if
+            1) both queues are empty or
+            2) unacked is empty and unsent head contains data not part of RTO or
+            3) unacked head contains data not part of RTO */
+        if (pcb->unacked == NULL) {
+          if ((pcb->unsent == NULL) ||
+              (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
+            tcp_clear_flags(pcb, TF_RTO);
+          }
+        } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
+          tcp_clear_flags(pcb, TF_RTO);
+        }
+      }
+      /* End of ACK for new data processing. */
+    } else {
+      /* Out of sequence ACK, didn't really ack anything */
+      tcp_send_empty_ack(pcb);
+    }
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      /* diff between this shouldn't exceed 32K since this are tcp timer ticks
+         and a round-trip shouldn't be that long... */
+      m = (s16_t)(tcp_ticks - pcb->rttest);
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, (u16_t)(m * TCP_SLOW_INTERVAL)));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = (s16_t)(m - (pcb->sa >> 3));
+      pcb->sa = (s16_t)(pcb->sa + m);
+      if (m < 0) {
+        m = (s16_t) - m;
+      }
+      m = (s16_t)(m - (pcb->sv >> 2));
+      pcb->sv = (s16_t)(pcb->sv + m);
+      pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
+                                  pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further unless the pcb already received a FIN.
+     (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
+     LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
+  if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+
+      struct pbuf *p = inseg.p;
+      u32_t off32 = pcb->rcv_nxt - seqno;
+      u16_t new_tot_len, off;
+      LWIP_ASSERT("inseg.p != NULL", inseg.p);
+      LWIP_ASSERT("insane offset!", (off32 < 0xffff));
+      off = (u16_t)off32;
+      LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
+      inseg.len -= off;
+      new_tot_len = (u16_t)(inseg.p->tot_len - off);
+      while (p->len < off) {
+        off -= p->len;
+        /* all pbufs up to and including this one have len==0, so tot_len is equal */
+        p->tot_len = new_tot_len;
+        p->len = 0;
+        p = p->next;
+      }
+      /* cannot fail... */
+      pbuf_remove_header(p, off);
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    } else {
+      if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
+                        pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
+      if (pcb->rcv_nxt == seqno) {
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+        tcplen = TCP_TCPLEN(&inseg);
+
+        if (tcplen > pcb->rcv_wnd) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG,
+                      ("tcp_receive: other end overran receive window"
+                       "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
+                       seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+            /* Must remove the FIN from the header as we're trimming
+             * that byte of sequence-space from the packet */
+            TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
+          }
+          /* Adjust length of segment to fit in the window. */
+          TCPWND_CHECK16(pcb->rcv_wnd);
+          inseg.len = (u16_t)pcb->rcv_wnd;
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+            inseg.len -= 1;
+          }
+          pbuf_realloc(inseg.p, inseg.len);
+          tcplen = TCP_TCPLEN(&inseg);
+          LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+                      (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
+        }
+#if TCP_QUEUE_OOSEQ
+        /* Received in-sequence data, adjust ooseq data if:
+           - FIN has been received or
+           - inseq overlaps with ooseq */
+        if (pcb->ooseq != NULL) {
+          if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG,
+                        ("tcp_receive: received in-order FIN, binning ooseq queue\n"));
+            /* Received in-order FIN means anything that was received
+             * out of order must now have been received in-order, so
+             * bin the ooseq queue */
+            while (pcb->ooseq != NULL) {
+              struct tcp_seg *old_ooseq = pcb->ooseq;
+              pcb->ooseq = pcb->ooseq->next;
+              tcp_seg_free(old_ooseq);
+            }
+          } else {
+            struct tcp_seg *next = pcb->ooseq;
+            /* Remove all segments on ooseq that are covered by inseg already.
+             * FIN is copied from ooseq to inseg if present. */
+            while (next &&
+                   TCP_SEQ_GEQ(seqno + tcplen,
+                               next->tcphdr->seqno + next->len)) {
+              struct tcp_seg *tmp;
+              /* inseg cannot have FIN here (already processed above) */
+              if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
+                  (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
+                TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
+                tcplen = TCP_TCPLEN(&inseg);
+              }
+              tmp = next;
+              next = next->next;
+              tcp_seg_free(tmp);
+            }
+            /* Now trim right side of inseg if it overlaps with the first
+             * segment on ooseq */
+            if (next &&
+                TCP_SEQ_GT(seqno + tcplen,
+                           next->tcphdr->seqno)) {
+              /* inseg cannot have FIN here (already processed above) */
+              inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
+              if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
+                inseg.len -= 1;
+              }
+              pbuf_realloc(inseg.p, inseg.len);
+              tcplen = TCP_TCPLEN(&inseg);
+              LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
+                          (seqno + tcplen) == next->tcphdr->seqno);
+            }
+            pcb->ooseq = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        pcb->rcv_nxt = seqno + tcplen;
+
+        /* Update the receiver's (our) window. */
+        LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
+        pcb->rcv_wnd -= tcplen;
+
+        tcp_update_rcv_ann_wnd(pcb);
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags |= TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           are now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          struct tcp_seg *cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
+                      pcb->rcv_wnd >= TCP_TCPLEN(cseg));
+          pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+
+          tcp_update_rcv_ann_wnd(pcb);
+
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            /* With window scaling, this can overflow recv_data->tot_len, but
+               that's not a problem since we explicitly fix that before passing
+               recv_data to the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags |= TF_GOT_FIN;
+            if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
+              pcb->state = CLOSE_WAIT;
+            }
+          }
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#if LWIP_TCP_SACK_OUT
+        if (pcb->flags & TF_SACK) {
+          if (pcb->ooseq != NULL) {
+            /* Some segments may have been removed from ooseq, let's remove all SACKs that
+               describe anything before the new beginning of that list. */
+            tcp_remove_sacks_lt(pcb, pcb->ooseq->tcphdr->seqno);
+          } else if (LWIP_TCP_SACK_VALID(pcb, 0)) {
+            /* ooseq has been cleared. Nothing to SACK */
+            memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
+          }
+        }
+#endif /* LWIP_TCP_SACK_OUT */
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+#if LWIP_TCP_SACK_OUT
+        if (LWIP_TCP_SACK_VALID(pcb, 0)) {
+          /* Normally the ACK for the data received could be piggy-backed on a data packet,
+             but lwIP currently does not support including SACKs in data packets. So we force
+             it to respond with an empty ACK packet (only if there is at least one SACK to be sent).
+             NOTE: tcp_send_empty_ack() on success clears the ACK flags (set by tcp_ack()) */
+          tcp_send_empty_ack(pcb);
+        }
+#endif /* LWIP_TCP_SACK_OUT */
+
+#if LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS
+        if (ip_current_is_v6()) {
+          /* Inform neighbor reachability of forward progress. */
+          nd6_reachability_hint(ip6_current_src_addr());
+        }
+#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+#if LWIP_TCP_SACK_OUT
+          if (pcb->flags & TF_SACK) {
+            /* All the SACKs should be invalid, so we can simply store the most recent one: */
+            pcb->rcv_sacks[0].left = seqno;
+            pcb->rcv_sacks[0].right = seqno + inseg.len;
+          }
+#endif /* LWIP_TCP_SACK_OUT */
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+#if LWIP_TCP_SACK_OUT
+          /* This is the left edge of the lowest possible SACK range.
+             It may start before the newly received segment (possibly adjusted below). */
+          u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
+#endif /* LWIP_TCP_SACK_OUT */
+          struct tcp_seg *next, *prev = NULL;
+          for (next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace some segments with the new
+                   one. */
+                struct tcp_seg *cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                  tcp_oos_insert_segment(cseg, next);
+                }
+                break;
+              } else {
+                /* Either the lengths are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+                  struct tcp_seg *cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    pcb->ooseq = cseg;
+                    tcp_oos_insert_segment(cseg, next);
+                  }
+                  break;
+                }
+              } else {
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
+                  /* The sequence number of the incoming segment is in
+                     between the sequence numbers of the previous and
+                     the next segment on ->ooseq. We trim trim the previous
+                     segment, delete next segments that included in received segment
+                     and trim received, if needed. */
+                  struct tcp_seg *cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                      /* We need to trim the prev segment. */
+                      prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
+                      pbuf_realloc(prev->p, prev->len);
+                    }
+                    prev->next = cseg;
+                    tcp_oos_insert_segment(cseg, next);
+                  }
+                  break;
+                }
+              }
+
+#if LWIP_TCP_SACK_OUT
+              /* The new segment goes after the 'next' one. If there is a "hole" in sequence numbers
+                 between 'prev' and the beginning of 'next', we want to move sackbeg. */
+              if (prev != NULL && prev->tcphdr->seqno + prev->len != next->tcphdr->seqno) {
+                sackbeg = next->tcphdr->seqno;
+              }
+#endif /* LWIP_TCP_SACK_OUT */
+
+              /* We don't use 'prev' below, so let's set it to current 'next'.
+                 This way even if we break the loop below, 'prev' will be pointing
+                 at the segment right in front of the newly added one. */
+              prev = next;
+
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
+                  /* segment "next" already contains all data */
+                  break;
+                }
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = (u16_t)(seqno - next->tcphdr->seqno);
+                    pbuf_realloc(next->p, next->len);
+                  }
+                  /* check if the remote side overruns our receive window */
+                  if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
+                    LWIP_DEBUGF(TCP_INPUT_DEBUG,
+                                ("tcp_receive: other end overran receive window"
+                                 "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
+                                 seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
+                    if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
+                      /* Must remove the FIN from the header as we're trimming
+                       * that byte of sequence-space from the packet */
+                      TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
+                    }
+                    /* Adjust length of segment to fit in the window. */
+                    next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
+                    pbuf_realloc(next->next->p, next->next->len);
+                    tcplen = TCP_TCPLEN(next->next);
+                    LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
+                                (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
+                  }
+                }
+                break;
+              }
+            }
+          }
+
+#if LWIP_TCP_SACK_OUT
+          if (pcb->flags & TF_SACK) {
+            if (prev == NULL) {
+              /* The new segment is at the beginning. sackbeg should already be set properly.
+                 We need to find the right edge. */
+              next = pcb->ooseq;
+            } else if (prev->next != NULL) {
+              /* The new segment was added after 'prev'. If there is a "hole" between 'prev' and 'prev->next',
+                 we need to move sackbeg. After that we should find the right edge. */
+              next = prev->next;
+              if (prev->tcphdr->seqno + prev->len != next->tcphdr->seqno) {
+                sackbeg = next->tcphdr->seqno;
+              }
+            } else {
+              next = NULL;
+            }
+            if (next != NULL) {
+              u32_t sackend = next->tcphdr->seqno;
+              for ( ; (next != NULL) && (sackend == next->tcphdr->seqno); next = next->next) {
+                sackend += next->len;
+              }
+              tcp_add_sack(pcb, sackbeg, sackend);
+            }
+          }
+#endif /* LWIP_TCP_SACK_OUT */
+        }
+#if defined(TCP_OOSEQ_BYTES_LIMIT) || defined(TCP_OOSEQ_PBUFS_LIMIT)
+        {
+          /* Check that the data on ooseq doesn't exceed one of the limits
+             and throw away everything above that limit. */
+#ifdef TCP_OOSEQ_BYTES_LIMIT
+          const u32_t ooseq_max_blen = TCP_OOSEQ_BYTES_LIMIT(pcb);
+          u32_t ooseq_blen = 0;
+#endif
+#ifdef TCP_OOSEQ_PBUFS_LIMIT
+          const u16_t ooseq_max_qlen = TCP_OOSEQ_PBUFS_LIMIT(pcb);
+          u16_t ooseq_qlen = 0;
+#endif
+          struct tcp_seg *next, *prev = NULL;
+          for (next = pcb->ooseq; next != NULL; prev = next, next = next->next) {
+            struct pbuf *p = next->p;
+            int stop_here = 0;
+#ifdef TCP_OOSEQ_BYTES_LIMIT
+            ooseq_blen += p->tot_len;
+            if (ooseq_blen > ooseq_max_blen) {
+              stop_here = 1;
+            }
+#endif
+#ifdef TCP_OOSEQ_PBUFS_LIMIT
+            ooseq_qlen += pbuf_clen(p);
+            if (ooseq_qlen > ooseq_max_qlen) {
+              stop_here = 1;
+            }
+#endif
+            if (stop_here) {
+#if LWIP_TCP_SACK_OUT
+              if (pcb->flags & TF_SACK) {
+                /* Let's remove all SACKs from next's seqno up. */
+                tcp_remove_sacks_gt(pcb, next->tcphdr->seqno);
+              }
+#endif /* LWIP_TCP_SACK_OUT */
+              /* too much ooseq data, dump this and everything after it */
+              tcp_segs_free(next);
+              if (prev == NULL) {
+                /* first ooseq segment is too much, dump the whole queue */
+                pcb->ooseq = NULL;
+              } else {
+                /* just dump 'next' and everything after it */
+                prev->next = NULL;
+              }
+              break;
+            }
+          }
+        }
+#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
+#endif /* TCP_QUEUE_OOSEQ */
+
+        /* We send the ACK packet after we've (potentially) dealt with SACKs,
+           so they can be included in the acknowledgment. */
+        tcp_send_empty_ack(pcb);
+      }
+    } else {
+      /* The incoming segment is not within the window. */
+      tcp_send_empty_ack(pcb);
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
+      tcp_ack_now(pcb);
+    }
+  }
+}
+
+static u8_t
+tcp_get_next_optbyte(void)
+{
+  u16_t optidx = tcp_optidx++;
+  if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
+    u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
+    return opts[optidx];
+  } else {
+    u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
+    return tcphdr_opt2[idx];
+  }
+}
+
+/**
+ * Parses the options contained in the incoming segment.
+ *
+ * Called from tcp_listen_input() and tcp_process().
+ * Currently, only the MSS option is supported!
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ */
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u8_t data;
+  u16_t mss;
+#if LWIP_TCP_TIMESTAMPS
+  u32_t tsval;
+#endif
+
+  LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
+
+  /* Parse the TCP MSS option, if present. */
+  if (tcphdr_optlen != 0) {
+    for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
+      u8_t opt = tcp_get_next_optbyte();
+      switch (opt) {
+        case LWIP_TCP_OPT_EOL:
+          /* End of options. */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n"));
+          return;
+        case LWIP_TCP_OPT_NOP:
+          /* NOP option. */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
+          break;
+        case LWIP_TCP_OPT_MSS:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
+          if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
+            /* Bad length */
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+            return;
+          }
+          /* An MSS option with the right option length. */
+          mss = (u16_t)(tcp_get_next_optbyte() << 8);
+          mss |= tcp_get_next_optbyte();
+          /* Limit the mss to the configured TCP_MSS and prevent division by zero */
+          pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
+          break;
+#if LWIP_WND_SCALE
+        case LWIP_TCP_OPT_WS:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: WND_SCALE\n"));
+          if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_WS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_WS) > tcphdr_optlen) {
+            /* Bad length */
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+            return;
+          }
+          /* An WND_SCALE option with the right option length. */
+          data = tcp_get_next_optbyte();
+          /* If syn was received with wnd scale option,
+             activate wnd scale opt, but only if this is not a retransmission */
+          if ((flags & TCP_SYN) && !(pcb->flags & TF_WND_SCALE)) {
+            pcb->snd_scale = data;
+            if (pcb->snd_scale > 14U) {
+              pcb->snd_scale = 14U;
+            }
+            pcb->rcv_scale = TCP_RCV_SCALE;
+            tcp_set_flags(pcb, TF_WND_SCALE);
+            /* window scaling is enabled, we can use the full receive window */
+            LWIP_ASSERT("window not at default value", pcb->rcv_wnd == TCPWND_MIN16(TCP_WND));
+            LWIP_ASSERT("window not at default value", pcb->rcv_ann_wnd == TCPWND_MIN16(TCP_WND));
+            pcb->rcv_wnd = pcb->rcv_ann_wnd = TCP_WND;
+          }
+          break;
+#endif /* LWIP_WND_SCALE */
+#if LWIP_TCP_TIMESTAMPS
+        case LWIP_TCP_OPT_TS:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n"));
+          if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_TS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_TS) > tcphdr_optlen) {
+            /* Bad length */
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+            return;
+          }
+          /* TCP timestamp option with valid length */
+          tsval = tcp_get_next_optbyte();
+          tsval |= (tcp_get_next_optbyte() << 8);
+          tsval |= (tcp_get_next_optbyte() << 16);
+          tsval |= (tcp_get_next_optbyte() << 24);
+          if (flags & TCP_SYN) {
+            pcb->ts_recent = lwip_ntohl(tsval);
+            /* Enable sending timestamps in every segment now that we know
+               the remote host supports it. */
+            tcp_set_flags(pcb, TF_TIMESTAMP);
+          } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno + tcplen)) {
+            pcb->ts_recent = lwip_ntohl(tsval);
+          }
+          /* Advance to next option (6 bytes already read) */
+          tcp_optidx += LWIP_TCP_OPT_LEN_TS - 6;
+          break;
+#endif /* LWIP_TCP_TIMESTAMPS */
+#if LWIP_TCP_SACK_OUT
+        case LWIP_TCP_OPT_SACK_PERM:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: SACK_PERM\n"));
+          if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_SACK_PERM || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_SACK_PERM) > tcphdr_optlen) {
+            /* Bad length */
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+            return;
+          }
+          /* TCP SACK_PERM option with valid length */
+          if (flags & TCP_SYN) {
+            /* We only set it if we receive it in a SYN (or SYN+ACK) packet */
+            tcp_set_flags(pcb, TF_SACK);
+          }
+          break;
+#endif /* LWIP_TCP_SACK_OUT */
+        default:
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
+          data = tcp_get_next_optbyte();
+          if (data < 2) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
+            /* If the length field is zero, the options are malformed
+               and we don't process them further. */
+            return;
+          }
+          /* All other options have a length field, so that we easily
+             can skip past them. */
+          tcp_optidx += data - 2;
+      }
+    }
+  }
+}
+
+void
+tcp_trigger_input_pcb_close(void)
+{
+  recv_flags |= TF_CLOSED;
+}
+
+#if LWIP_TCP_SACK_OUT
+/**
+ * Called by tcp_receive() to add new SACK entry.
+ *
+ * The new SACK entry will be placed at the beginning of rcv_sacks[], as the newest one.
+ * Existing SACK entries will be "pushed back", to preserve their order.
+ * This is the behavior described in RFC 2018, section 4.
+ *
+ * @param pcb the tcp_pcb for which a segment arrived
+ * @param left the left side of the SACK (the first sequence number)
+ * @param right the right side of the SACK (the first sequence number past this SACK)
+ */
+static void
+tcp_add_sack(struct tcp_pcb *pcb, u32_t left, u32_t right)
+{
+  u8_t i;
+  u8_t unused_idx;
+
+  if ((pcb->flags & TF_SACK) == 0 || !TCP_SEQ_LT(left, right)) {
+    return;
+  }
+
+  /* First, let's remove all SACKs that are no longer needed (because they overlap with the newest one),
+     while moving all other SACKs forward.
+     We run this loop for all entries, until we find the first invalid one.
+     There is no point checking after that. */
+  for (i = unused_idx = 0; (i < LWIP_TCP_MAX_SACK_NUM) && LWIP_TCP_SACK_VALID(pcb, i); ++i) {
+    /* We only want to use SACK at [i] if it doesn't overlap with left:right range.
+       It does not overlap if its right side is before the newly added SACK,
+       or if its left side is after the newly added SACK.
+       NOTE: The equality should not really happen, but it doesn't hurt. */
+    if (TCP_SEQ_LEQ(pcb->rcv_sacks[i].right, left) || TCP_SEQ_LEQ(right, pcb->rcv_sacks[i].left)) {
+      if (unused_idx != i) {
+        /* We don't need to copy if it's already in the right spot */
+        pcb->rcv_sacks[unused_idx] = pcb->rcv_sacks[i];
+      }
+      ++unused_idx;
+    }
+  }
+
+  /* Now 'unused_idx' is the index of the first invalid SACK entry,
+     anywhere between 0 (no valid entries) and LWIP_TCP_MAX_SACK_NUM (all entries are valid).
+     We want to clear this and all following SACKs.
+     However, we will be adding another one in the front (and shifting everything else back).
+     So let's just iterate from the back, and set each entry to the one to the left if it's valid,
+     or to 0 if it is not. */
+  for (i = LWIP_TCP_MAX_SACK_NUM - 1; i > 0; --i) {
+    /* [i] is the index we are setting, and the value should be at index [i-1],
+       or 0 if that index is unused (>= unused_idx). */
+    if (i - 1 >= unused_idx) {
+      /* [i-1] is unused. Let's clear [i]. */
+      pcb->rcv_sacks[i].left = pcb->rcv_sacks[i].right = 0;
+    } else {
+      pcb->rcv_sacks[i] = pcb->rcv_sacks[i - 1];
+    }
+  }
+
+  /* And now we can store the newest SACK */
+  pcb->rcv_sacks[0].left = left;
+  pcb->rcv_sacks[0].right = right;
+}
+
+/**
+ * Called to remove a range of SACKs.
+ *
+ * SACK entries will be removed or adjusted to not acknowledge any sequence
+ * numbers that are less than 'seq' passed. It not only invalidates entries,
+ * but also moves all entries that are still valid to the beginning.
+ *
+ * @param pcb the tcp_pcb to modify
+ * @param seq the lowest sequence number to keep in SACK entries
+ */
+static void
+tcp_remove_sacks_lt(struct tcp_pcb *pcb, u32_t seq)
+{
+  u8_t i;
+  u8_t unused_idx;
+
+  /* We run this loop for all entries, until we find the first invalid one.
+     There is no point checking after that. */
+  for (i = unused_idx = 0; (i < LWIP_TCP_MAX_SACK_NUM) && LWIP_TCP_SACK_VALID(pcb, i); ++i) {
+    /* We only want to use SACK at index [i] if its right side is > 'seq'. */
+    if (TCP_SEQ_GT(pcb->rcv_sacks[i].right, seq)) {
+      if (unused_idx != i) {
+        /* We only copy it if it's not in the right spot already. */
+        pcb->rcv_sacks[unused_idx] = pcb->rcv_sacks[i];
+      }
+      /* NOTE: It is possible that its left side is < 'seq', in which case we should adjust it. */
+      if (TCP_SEQ_LT(pcb->rcv_sacks[unused_idx].left, seq)) {
+        pcb->rcv_sacks[unused_idx].left = seq;
+      }
+      ++unused_idx;
+    }
+  }
+
+  /* We also need to invalidate everything from 'unused_idx' till the end */
+  for (i = unused_idx; i < LWIP_TCP_MAX_SACK_NUM; ++i) {
+    pcb->rcv_sacks[i].left = pcb->rcv_sacks[i].right = 0;
+  }
+}
+
+#if defined(TCP_OOSEQ_BYTES_LIMIT) || defined(TCP_OOSEQ_PBUFS_LIMIT)
+/**
+ * Called to remove a range of SACKs.
+ *
+ * SACK entries will be removed or adjusted to not acknowledge any sequence
+ * numbers that are greater than (or equal to) 'seq' passed. It not only invalidates entries,
+ * but also moves all entries that are still valid to the beginning.
+ *
+ * @param pcb the tcp_pcb to modify
+ * @param seq the highest sequence number to keep in SACK entries
+ */
+static void
+tcp_remove_sacks_gt(struct tcp_pcb *pcb, u32_t seq)
+{
+  u8_t i;
+  u8_t unused_idx;
+
+  /* We run this loop for all entries, until we find the first invalid one.
+     There is no point checking after that. */
+  for (i = unused_idx = 0; (i < LWIP_TCP_MAX_SACK_NUM) && LWIP_TCP_SACK_VALID(pcb, i); ++i) {
+    /* We only want to use SACK at index [i] if its left side is < 'seq'. */
+    if (TCP_SEQ_LT(pcb->rcv_sacks[i].left, seq)) {
+      if (unused_idx != i) {
+        /* We only copy it if it's not in the right spot already. */
+        pcb->rcv_sacks[unused_idx] = pcb->rcv_sacks[i];
+      }
+      /* NOTE: It is possible that its right side is > 'seq', in which case we should adjust it. */
+      if (TCP_SEQ_GT(pcb->rcv_sacks[unused_idx].right, seq)) {
+        pcb->rcv_sacks[unused_idx].right = seq;
+      }
+      ++unused_idx;
+    }
+  }
+
+  /* We also need to invalidate everything from 'unused_idx' till the end */
+  for (i = unused_idx; i < LWIP_TCP_MAX_SACK_NUM; ++i) {
+    pcb->rcv_sacks[i].left = pcb->rcv_sacks[i].right = 0;
+  }
+}
+#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
+
+#endif /* LWIP_TCP_SACK_OUT */
+
+#endif /* LWIP_TCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp_out.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp_out.c
new file mode 100644
index 000000000..a8c08e4f8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/tcp_out.c
@@ -0,0 +1,2190 @@
+/**
+ * @file
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ * There are two distinct ways for TCP segments to get sent:
+ * - queued data: these are segments transferring data or segments containing
+ *   SYN or FIN (which both count as one sequence number). They are created as
+ *   struct @ref pbuf together with a struct tcp_seg and enqueue to the
+ *   unsent list of the pcb. They are sent by tcp_output:
+ *   - @ref tcp_write : creates data segments
+ *   - @ref tcp_split_unsent_seg : splits a data segment
+ *   - @ref tcp_enqueue_flags : creates SYN-only or FIN-only segments
+ *   - @ref tcp_output / tcp_output_segment : finalize the tcp header
+ *      (e.g. sequence numbers, options, checksum) and output to IP
+ *   - the various tcp_rexmit functions shuffle around segments between the
+ *     unsent an unacked lists to retransmit them
+ *   - tcp_create_segment and tcp_pbuf_prealloc allocate pbuf and
+ *     segment for these functions
+ * - direct send: these segments don't contain data but control the connection
+ *   behaviour. They are created as pbuf only and sent directly without
+ *   enqueueing them:
+ *   - @ref tcp_send_empty_ack sends an ACK-only segment
+ *   - @ref tcp_rst sends a RST segment
+ *   - @ref tcp_keepalive sends a keepalive segment
+ *   - @ref tcp_zero_window_probe sends a window probe segment
+ *   - tcp_output_alloc_header allocates a header-only pbuf for these functions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/priv/tcp_priv.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/stats.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#if LWIP_TCP_TIMESTAMPS
+#include "lwip/sys.h"
+#endif
+
+#include <string.h>
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+/* Allow to add custom TCP header options by defining this hook */
+#ifdef LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH
+#define LWIP_TCP_OPT_LENGTH_SEGMENT(flags, pcb) LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH(pcb, LWIP_TCP_OPT_LENGTH(flags))
+#else
+#define LWIP_TCP_OPT_LENGTH_SEGMENT(flags, pcb) LWIP_TCP_OPT_LENGTH(flags)
+#endif
+
+/* Define some copy-macros for checksum-on-copy so that the code looks
+   nicer by preventing too many ifdef's. */
+#if TCP_CHECKSUM_ON_COPY
+#define TCP_DATA_COPY(dst, src, len, seg) do { \
+  tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), \
+                     len, &seg->chksum, &seg->chksum_swapped); \
+  seg->flags |= TF_SEG_DATA_CHECKSUMMED; } while(0)
+#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped)  \
+  tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), len, chksum, chksum_swapped);
+#else /* TCP_CHECKSUM_ON_COPY*/
+#define TCP_DATA_COPY(dst, src, len, seg)                     MEMCPY(dst, src, len)
+#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) MEMCPY(dst, src, len)
+#endif /* TCP_CHECKSUM_ON_COPY*/
+
+/** Define this to 1 for an extra check that the output checksum is valid
+ * (usefule when the checksum is generated by the application, not the stack) */
+#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK   0
+#endif
+/* Allow to override the failure of sanity check from warning to e.g. hard failure */
+#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL
+#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL(msg) LWIP_DEBUGF(TCP_DEBUG | LWIP_DBG_LEVEL_WARNING, msg)
+#endif
+#endif
+
+#if TCP_OVERSIZE
+/** The size of segment pbufs created when TCP_OVERSIZE is enabled */
+#ifndef TCP_OVERSIZE_CALC_LENGTH
+#define TCP_OVERSIZE_CALC_LENGTH(length) ((length) + TCP_OVERSIZE)
+#endif
+#endif
+
+/* Forward declarations.*/
+static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
+
+/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
+static struct netif *
+tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
+{
+  LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
+
+  if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
+    return netif_get_by_index(pcb->netif_idx);
+  } else {
+    return ip_route(src, dst);
+  }
+}
+
+/**
+ * Create a TCP segment with prefilled header.
+ *
+ * Called by @ref tcp_write, @ref tcp_enqueue_flags and @ref tcp_split_unsent_seg
+ *
+ * @param pcb Protocol control block for the TCP connection.
+ * @param p pbuf that is used to hold the TCP header.
+ * @param hdrflags TCP flags for header.
+ * @param seqno TCP sequence number of this packet
+ * @param optflags options to include in TCP header
+ * @return a new tcp_seg pointing to p, or NULL.
+ * The TCP header is filled in except ackno and wnd.
+ * p is freed on failure.
+ */
+static struct tcp_seg *
+tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
+{
+  struct tcp_seg *seg;
+  u8_t optlen;
+
+  LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
+  LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
+
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
+
+  if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
+    pbuf_free(p);
+    return NULL;
+  }
+  seg->flags = optflags;
+  seg->next = NULL;
+  seg->p = p;
+  LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
+  seg->len = p->tot_len - optlen;
+#if TCP_OVERSIZE_DBGCHECK
+  seg->oversize_left = 0;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+  seg->chksum = 0;
+  seg->chksum_swapped = 0;
+  /* check optflags */
+  LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
+              (optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* build TCP header */
+  if (pbuf_add_header(p, TCP_HLEN)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
+    TCP_STATS_INC(tcp.err);
+    tcp_seg_free(seg);
+    return NULL;
+  }
+  seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
+  seg->tcphdr->src = lwip_htons(pcb->local_port);
+  seg->tcphdr->dest = lwip_htons(pcb->remote_port);
+  seg->tcphdr->seqno = lwip_htonl(seqno);
+  /* ackno is set in tcp_output */
+  TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
+  /* wnd and chksum are set in tcp_output */
+  seg->tcphdr->urgp = 0;
+  return seg;
+}
+
+/**
+ * Allocate a PBUF_RAM pbuf, perhaps with extra space at the end.
+ *
+ * This function is like pbuf_alloc(layer, length, PBUF_RAM) except
+ * there may be extra bytes available at the end.
+ *
+ * Called by @ref tcp_write
+ *
+ * @param layer flag to define header size.
+ * @param length size of the pbuf's payload.
+ * @param max_length maximum usable size of payload+oversize.
+ * @param oversize pointer to a u16_t that will receive the number of usable tail bytes.
+ * @param pcb The TCP connection that will enqueue the pbuf.
+ * @param apiflags API flags given to tcp_write.
+ * @param first_seg true when this pbuf will be used in the first enqueued segment.
+ */
+#if TCP_OVERSIZE
+static struct pbuf *
+tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length,
+                  u16_t *oversize, const struct tcp_pcb *pcb, u8_t apiflags,
+                  u8_t first_seg)
+{
+  struct pbuf *p;
+  u16_t alloc = length;
+
+  LWIP_ASSERT("tcp_pbuf_prealloc: invalid oversize", oversize != NULL);
+  LWIP_ASSERT("tcp_pbuf_prealloc: invalid pcb", pcb != NULL);
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  LWIP_UNUSED_ARG(max_length);
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(apiflags);
+  LWIP_UNUSED_ARG(first_seg);
+  alloc = max_length;
+#else /* LWIP_NETIF_TX_SINGLE_PBUF */
+  if (length < max_length) {
+    /* Should we allocate an oversized pbuf, or just the minimum
+     * length required? If tcp_write is going to be called again
+     * before this segment is transmitted, we want the oversized
+     * buffer. If the segment will be transmitted immediately, we can
+     * save memory by allocating only length. We use a simple
+     * heuristic based on the following information:
+     *
+     * Did the user set TCP_WRITE_FLAG_MORE?
+     *
+     * Will the Nagle algorithm defer transmission of this segment?
+     */
+    if ((apiflags & TCP_WRITE_FLAG_MORE) ||
+        (!(pcb->flags & TF_NODELAY) &&
+         (!first_seg ||
+          pcb->unsent != NULL ||
+          pcb->unacked != NULL))) {
+      alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length)));
+    }
+  }
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+  p = pbuf_alloc(layer, alloc, PBUF_RAM);
+  if (p == NULL) {
+    return NULL;
+  }
+  LWIP_ASSERT("need unchained pbuf", p->next == NULL);
+  *oversize = p->len - length;
+  /* trim p->len to the currently used size */
+  p->len = p->tot_len = length;
+  return p;
+}
+#else /* TCP_OVERSIZE */
+#define tcp_pbuf_prealloc(layer, length, mx, os, pcb, api, fst) pbuf_alloc((layer), (length), PBUF_RAM)
+#endif /* TCP_OVERSIZE */
+
+#if TCP_CHECKSUM_ON_COPY
+/** Add a checksum of newly added data to the segment.
+ *
+ * Called by tcp_write and tcp_split_unsent_seg.
+ */
+static void
+tcp_seg_add_chksum(u16_t chksum, u16_t len, u16_t *seg_chksum,
+                   u8_t *seg_chksum_swapped)
+{
+  u32_t helper;
+  /* add chksum to old chksum and fold to u16_t */
+  helper = chksum + *seg_chksum;
+  chksum = FOLD_U32T(helper);
+  if ((len & 1) != 0) {
+    *seg_chksum_swapped = 1 - *seg_chksum_swapped;
+    chksum = SWAP_BYTES_IN_WORD(chksum);
+  }
+  *seg_chksum = chksum;
+}
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+/** Checks if tcp_write is allowed or not (checks state, snd_buf and snd_queuelen).
+ *
+ * @param pcb the tcp pcb to check for
+ * @param len length of data to send (checked agains snd_buf)
+ * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise
+ */
+static err_t
+tcp_write_checks(struct tcp_pcb *pcb, u16_t len)
+{
+  LWIP_ASSERT("tcp_write_checks: invalid pcb", pcb != NULL);
+
+  /* connection is in invalid state for data transmission? */
+  if ((pcb->state != ESTABLISHED) &&
+      (pcb->state != CLOSE_WAIT) &&
+      (pcb->state != SYN_SENT) &&
+      (pcb->state != SYN_RCVD)) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  } else if (len == 0) {
+    return ERR_OK;
+  }
+
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n",
+                len, pcb->snd_buf));
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+    return ERR_MEM;
+  }
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  /* check for configured max queuelen and possible overflow */
+  if (pcb->snd_queuelen >= LWIP_MIN(TCP_SND_QUEUELEN, (TCP_SNDQUEUELEN_OVERFLOW + 1))) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n",
+                pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+    return ERR_MEM;
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty",
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty",
+                pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+  return ERR_OK;
+}
+
+/**
+ * @ingroup tcp_raw
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ * 
+ * This function enqueues the data pointed to by the argument dataptr. The length of
+ * the data is passed as the len parameter. The apiflags can be one or more of:
+ * - TCP_WRITE_FLAG_COPY: indicates whether the new memory should be allocated
+ *   for the data to be copied into. If this flag is not given, no new memory
+ *   should be allocated and the data should only be referenced by pointer. This
+ *   also means that the memory behind dataptr must not change until the data is
+ *   ACKed by the remote host
+ * - TCP_WRITE_FLAG_MORE: indicates that more data follows. If this is omitted,
+ *   the PSH flag is set in the last segment created by this call to tcp_write.
+ *   If this flag is given, the PSH flag is not set.
+ *
+ * The tcp_write() function will fail and return ERR_MEM if the length
+ * of the data exceeds the current send buffer size or if the length of
+ * the queue of outgoing segment is larger than the upper limit defined
+ * in lwipopts.h. The number of bytes available in the output queue can
+ * be retrieved with the tcp_sndbuf() function.
+ *
+ * The proper way to use this function is to call the function with at
+ * most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+ * the application should wait until some of the currently enqueued
+ * data has been successfully received by the other host and try again.
+ *
+ * @param pcb Protocol control block for the TCP connection to enqueue data for.
+ * @param arg Pointer to the data to be enqueued for sending.
+ * @param len Data length in bytes
+ * @param apiflags combination of following flags :
+ * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack
+ * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent,
+ * @return ERR_OK if enqueued, another err_t on error
+ */
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags)
+{
+  struct pbuf *concat_p = NULL;
+  struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL;
+  u16_t pos = 0; /* position in 'arg' data */
+  u16_t queuelen;
+  u8_t optlen;
+  u8_t optflags = 0;
+#if TCP_OVERSIZE
+  u16_t oversize = 0;
+  u16_t oversize_used = 0;
+#if TCP_OVERSIZE_DBGCHECK
+  u16_t oversize_add = 0;
+#endif /* TCP_OVERSIZE_DBGCHECK*/
+#endif /* TCP_OVERSIZE */
+  u16_t extendlen = 0;
+#if TCP_CHECKSUM_ON_COPY
+  u16_t concat_chksum = 0;
+  u8_t concat_chksum_swapped = 0;
+  u16_t concat_chksummed = 0;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  err_t err;
+  u16_t mss_local;
+
+  LWIP_ERROR("tcp_write: invalid pcb", pcb != NULL, return ERR_ARG);
+
+  /* don't allocate segments bigger than half the maximum window we ever received */
+  mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max / 2));
+  mss_local = mss_local ? mss_local : pcb->mss;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_NETIF_TX_SINGLE_PBUF
+  /* Always copy to try to create single pbufs for TX */
+  apiflags |= TCP_WRITE_FLAG_COPY;
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n",
+                                 (void *)pcb, arg, len, (u16_t)apiflags));
+  LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)",
+             arg != NULL, return ERR_ARG;);
+
+  err = tcp_write_checks(pcb, len);
+  if (err != ERR_OK) {
+    return err;
+  }
+  queuelen = pcb->snd_queuelen;
+
+#if LWIP_TCP_TIMESTAMPS
+  if ((pcb->flags & TF_TIMESTAMP)) {
+    /* Make sure the timestamp option is only included in data segments if we
+       agreed about it with the remote host. */
+    optflags = TF_SEG_OPTS_TS;
+    optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(TF_SEG_OPTS_TS, pcb);
+    /* ensure that segments can hold at least one data byte... */
+    mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1);
+  } else
+#endif /* LWIP_TCP_TIMESTAMPS */
+  {
+    optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+  }
+
+
+  /*
+   * TCP segmentation is done in three phases with increasing complexity:
+   *
+   * 1. Copy data directly into an oversized pbuf.
+   * 2. Chain a new pbuf to the end of pcb->unsent.
+   * 3. Create new segments.
+   *
+   * We may run out of memory at any point. In that case we must
+   * return ERR_MEM and not change anything in pcb. Therefore, all
+   * changes are recorded in local variables and committed at the end
+   * of the function. Some pcb fields are maintained in local copies:
+   *
+   * queuelen = pcb->snd_queuelen
+   * oversize = pcb->unsent_oversize
+   *
+   * These variables are set consistently by the phases:
+   *
+   * seg points to the last segment tampered with.
+   *
+   * pos records progress as data is segmented.
+   */
+
+  /* Find the tail of the unsent queue. */
+  if (pcb->unsent != NULL) {
+    u16_t space;
+    u16_t unsent_optlen;
+
+    /* @todo: this could be sped up by keeping last_unsent in the pcb */
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+         last_unsent = last_unsent->next);
+
+    /* Usable space at the end of the last unsent segment */
+    unsent_optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(last_unsent->flags, pcb);
+    LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen);
+    space = mss_local - (last_unsent->len + unsent_optlen);
+
+    /*
+     * Phase 1: Copy data directly into an oversized pbuf.
+     *
+     * The number of bytes copied is recorded in the oversize_used
+     * variable. The actual copying is done at the bottom of the
+     * function.
+     */
+#if TCP_OVERSIZE
+#if TCP_OVERSIZE_DBGCHECK
+    /* check that pcb->unsent_oversize matches last_unsent->oversize_left */
+    LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)",
+                pcb->unsent_oversize == last_unsent->oversize_left);
+#endif /* TCP_OVERSIZE_DBGCHECK */
+    oversize = pcb->unsent_oversize;
+    if (oversize > 0) {
+      LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space);
+      seg = last_unsent;
+      oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len));
+      pos += oversize_used;
+      oversize -= oversize_used;
+      space -= oversize_used;
+    }
+    /* now we are either finished or oversize is zero */
+    LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len));
+#endif /* TCP_OVERSIZE */
+
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+    /*
+     * Phase 2: Chain a new pbuf to the end of pcb->unsent.
+     *
+     * As an exception when NOT copying the data, if the given data buffer
+     * directly follows the last unsent data buffer in memory, extend the last
+     * ROM pbuf reference to the buffer, thus saving a ROM pbuf allocation.
+     *
+     * We don't extend segments containing SYN/FIN flags or options
+     * (len==0). The new pbuf is kept in concat_p and pbuf_cat'ed at
+     * the end.
+     *
+     * This phase is skipped for LWIP_NETIF_TX_SINGLE_PBUF as we could only execute
+     * it after rexmit puts a segment from unacked to unsent and at this point,
+     * oversize info is lost.
+     */
+    if ((pos < len) && (space > 0) && (last_unsent->len > 0)) {
+      u16_t seglen = LWIP_MIN(space, len - pos);
+      seg = last_unsent;
+
+      /* Create a pbuf with a copy or reference to seglen bytes. We
+       * can use PBUF_RAW here since the data appears in the middle of
+       * a segment. A header will never be prepended. */
+      if (apiflags & TCP_WRITE_FLAG_COPY) {
+        /* Data is copied */
+        if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) {
+          LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                      ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n",
+                       seglen));
+          goto memerr;
+        }
+#if TCP_OVERSIZE_DBGCHECK
+        oversize_add = oversize;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+        TCP_DATA_COPY2(concat_p->payload, (const u8_t *)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped);
+#if TCP_CHECKSUM_ON_COPY
+        concat_chksummed += seglen;
+#endif /* TCP_CHECKSUM_ON_COPY */
+        queuelen += pbuf_clen(concat_p);
+      } else {
+        /* Data is not copied */
+        /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */
+        struct pbuf *p;
+        for (p = last_unsent->p; p->next != NULL; p = p->next);
+        if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) &&
+            (const u8_t *)p->payload + p->len == (const u8_t *)arg) {
+          LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0);
+          extendlen = seglen;
+        } else {
+          if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) {
+            LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                        ("tcp_write: could not allocate memory for zero-copy pbuf\n"));
+            goto memerr;
+          }
+          /* reference the non-volatile payload data */
+          ((struct pbuf_rom *)concat_p)->payload = (const u8_t *)arg + pos;
+          queuelen += pbuf_clen(concat_p);
+        }
+#if TCP_CHECKSUM_ON_COPY
+        /* calculate the checksum of nocopy-data */
+        tcp_seg_add_chksum(~inet_chksum((const u8_t *)arg + pos, seglen), seglen,
+                           &concat_chksum, &concat_chksum_swapped);
+        concat_chksummed += seglen;
+#endif /* TCP_CHECKSUM_ON_COPY */
+      }
+
+      pos += seglen;
+    }
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+  } else {
+#if TCP_OVERSIZE
+    LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)",
+                pcb->unsent_oversize == 0);
+#endif /* TCP_OVERSIZE */
+  }
+
+  /*
+   * Phase 3: Create new segments.
+   *
+   * The new segments are chained together in the local 'queue'
+   * variable, ready to be appended to pcb->unsent.
+   */
+  while (pos < len) {
+    struct pbuf *p;
+    u16_t left = len - pos;
+    u16_t max_len = mss_local - optlen;
+    u16_t seglen = LWIP_MIN(left, max_len);
+#if TCP_CHECKSUM_ON_COPY
+    u16_t chksum = 0;
+    u8_t chksum_swapped = 0;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+    if (apiflags & TCP_WRITE_FLAG_COPY) {
+      /* If copy is set, memory should be allocated and data copied
+       * into pbuf */
+      if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen",
+                  (p->len >= seglen));
+      TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t *)arg + pos, seglen, &chksum, &chksum_swapped);
+    } else {
+      /* Copy is not set: First allocate a pbuf for holding the data.
+       * Since the referenced data is available at least until it is
+       * sent out on the link (as it has to be ACKed by the remote
+       * party) we can safely use PBUF_ROM instead of PBUF_REF here.
+       */
+      struct pbuf *p2;
+#if TCP_OVERSIZE
+      LWIP_ASSERT("oversize == 0", oversize == 0);
+#endif /* TCP_OVERSIZE */
+      if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+#if TCP_CHECKSUM_ON_COPY
+      /* calculate the checksum of nocopy-data */
+      chksum = ~inet_chksum((const u8_t *)arg + pos, seglen);
+      if (seglen & 1) {
+        chksum_swapped = 1;
+        chksum = SWAP_BYTES_IN_WORD(chksum);
+      }
+#endif /* TCP_CHECKSUM_ON_COPY */
+      /* reference the non-volatile payload data */
+      ((struct pbuf_rom *)p2)->payload = (const u8_t *)arg + pos;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p2);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(p/*header*/, p2/*data*/);
+    }
+
+    queuelen += pbuf_clen(p);
+
+    /* Now that there are more segments queued, we check again if the
+     * length of the queue exceeds the configured maximum or
+     * overflows. */
+    if (queuelen > LWIP_MIN(TCP_SND_QUEUELEN, TCP_SNDQUEUELEN_OVERFLOW)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n",
+                  queuelen, (int)TCP_SND_QUEUELEN));
+      pbuf_free(p);
+      goto memerr;
+    }
+
+    if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) {
+      goto memerr;
+    }
+#if TCP_OVERSIZE_DBGCHECK
+    seg->oversize_left = oversize;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+    seg->chksum = chksum;
+    seg->chksum_swapped = chksum_swapped;
+    seg->flags |= TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    } else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL);
+      prev_seg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    prev_seg = seg;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n",
+                lwip_ntohl(seg->tcphdr->seqno),
+                lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg)));
+
+    pos += seglen;
+  }
+
+  /*
+   * All three segmentation phases were successful. We can commit the
+   * transaction.
+   */
+#if TCP_OVERSIZE_DBGCHECK
+  if ((last_unsent != NULL) && (oversize_add != 0)) {
+    last_unsent->oversize_left += oversize_add;
+  }
+#endif /* TCP_OVERSIZE_DBGCHECK */
+
+  /*
+   * Phase 1: If data has been added to the preallocated tail of
+   * last_unsent, we update the length fields of the pbuf chain.
+   */
+#if TCP_OVERSIZE
+  if (oversize_used > 0) {
+    struct pbuf *p;
+    /* Bump tot_len of whole chain, len of tail */
+    for (p = last_unsent->p; p; p = p->next) {
+      p->tot_len += oversize_used;
+      if (p->next == NULL) {
+        TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent);
+        p->len += oversize_used;
+      }
+    }
+    last_unsent->len += oversize_used;
+#if TCP_OVERSIZE_DBGCHECK
+    LWIP_ASSERT("last_unsent->oversize_left >= oversize_used",
+                last_unsent->oversize_left >= oversize_used);
+    last_unsent->oversize_left -= oversize_used;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+  }
+  pcb->unsent_oversize = oversize;
+#endif /* TCP_OVERSIZE */
+
+  /*
+   * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we
+   * determined that the last ROM pbuf can be extended to include the new data.
+   */
+  if (concat_p != NULL) {
+    LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty",
+                (last_unsent != NULL));
+    pbuf_cat(last_unsent->p, concat_p);
+    last_unsent->len += concat_p->tot_len;
+  } else if (extendlen > 0) {
+    struct pbuf *p;
+    LWIP_ASSERT("tcp_write: extension of reference requires reference",
+                last_unsent != NULL && last_unsent->p != NULL);
+    for (p = last_unsent->p; p->next != NULL; p = p->next) {
+      p->tot_len += extendlen;
+    }
+    p->tot_len += extendlen;
+    p->len += extendlen;
+    last_unsent->len += extendlen;
+  }
+
+#if TCP_CHECKSUM_ON_COPY
+  if (concat_chksummed) {
+    LWIP_ASSERT("tcp_write: concat checksum needs concatenated data",
+                concat_p != NULL || extendlen > 0);
+    /*if concat checksumm swapped - swap it back */
+    if (concat_chksum_swapped) {
+      concat_chksum = SWAP_BYTES_IN_WORD(concat_chksum);
+    }
+    tcp_seg_add_chksum(concat_chksum, concat_chksummed, &last_unsent->chksum,
+                       &last_unsent->chksum_swapped);
+    last_unsent->flags |= TF_SEG_DATA_CHECKSUMMED;
+  }
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /*
+   * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that
+   * is harmless
+   */
+  if (last_unsent == NULL) {
+    pcb->unsent = queue;
+  } else {
+    last_unsent->next = queue;
+  }
+
+  /*
+   * Finally update the pcb state.
+   */
+  pcb->snd_lbb += len;
+  pcb->snd_buf -= len;
+  pcb->snd_queuelen = queuelen;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n",
+                               pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_write: valid queue length",
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued. */
+  if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE) == 0)) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+memerr:
+  tcp_set_flags(pcb, TF_NAGLEMEMERR);
+  TCP_STATS_INC(tcp.memerr);
+
+  if (concat_p != NULL) {
+    pbuf_free(concat_p);
+  }
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL ||
+                pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/**
+ * Split segment on the head of the unsent queue.  If return is not
+ * ERR_OK, existing head remains intact
+ *
+ * The split is accomplished by creating a new TCP segment and pbuf
+ * which holds the remainder payload after the split.  The original
+ * pbuf is trimmed to new length.  This allows splitting of read-only
+ * pbufs
+ *
+ * @param pcb the tcp_pcb for which to split the unsent head
+ * @param split the amount of payload to remain in the head
+ */
+err_t
+tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
+{
+  struct tcp_seg *seg = NULL, *useg = NULL;
+  struct pbuf *p = NULL;
+  u8_t optlen;
+  u8_t optflags;
+  u8_t split_flags;
+  u8_t remainder_flags;
+  u16_t remainder;
+  u16_t offset;
+#if TCP_CHECKSUM_ON_COPY
+  u16_t chksum = 0;
+  u8_t chksum_swapped = 0;
+  struct pbuf *q;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
+
+  useg = pcb->unsent;
+  if (useg == NULL) {
+    return ERR_MEM;
+  }
+
+  if (split == 0) {
+    LWIP_ASSERT("Can't split segment into length 0", 0);
+    return ERR_VAL;
+  }
+
+  if (useg->len <= split) {
+    return ERR_OK;
+  }
+
+  LWIP_ASSERT("split <= mss", split <= pcb->mss);
+  LWIP_ASSERT("useg->len > 0", useg->len > 0);
+
+  /* We should check that we don't exceed TCP_SND_QUEUELEN but we need
+   * to split this packet so we may actually exceed the max value by
+   * one!
+   */
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
+
+  optflags = useg->flags;
+#if TCP_CHECKSUM_ON_COPY
+  /* Remove since checksum is not stored until after tcp_create_segment() */
+  optflags &= ~TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  optlen = LWIP_TCP_OPT_LENGTH(optflags);
+  remainder = useg->len - split;
+
+  /* Create new pbuf for the remainder of the split */
+  p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
+  if (p == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
+    goto memerr;
+  }
+
+  /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
+  offset = useg->p->tot_len - useg->len + split;
+  /* Copy remainder into new pbuf, headers and options will not be filled out */
+  if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("tcp_split_unsent_seg: could not copy pbuf remainder %u\n", remainder));
+    goto memerr;
+  }
+#if TCP_CHECKSUM_ON_COPY
+  /* calculate the checksum on remainder data */
+  tcp_seg_add_chksum(~inet_chksum((const u8_t *)p->payload + optlen, remainder), remainder,
+                     &chksum, &chksum_swapped);
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* Options are created when calling tcp_output() */
+
+  /* Migrate flags from original segment */
+  split_flags = TCPH_FLAGS(useg->tcphdr);
+  remainder_flags = 0; /* ACK added in tcp_output() */
+
+  if (split_flags & TCP_PSH) {
+    split_flags &= ~TCP_PSH;
+    remainder_flags |= TCP_PSH;
+  }
+  if (split_flags & TCP_FIN) {
+    split_flags &= ~TCP_FIN;
+    remainder_flags |= TCP_FIN;
+  }
+  /* SYN should be left on split, RST should not be present with data */
+
+  seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("tcp_split_unsent_seg: could not create new TCP segment\n"));
+    goto memerr;
+  }
+
+#if TCP_CHECKSUM_ON_COPY
+  seg->chksum = chksum;
+  seg->chksum_swapped = chksum_swapped;
+  seg->flags |= TF_SEG_DATA_CHECKSUMMED;
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* Remove this segment from the queue since trimming it may free pbufs */
+  pcb->snd_queuelen -= pbuf_clen(useg->p);
+
+  /* Trim the original pbuf into our split size.  At this point our remainder segment must be setup
+  successfully because we are modifying the original segment */
+  pbuf_realloc(useg->p, useg->p->tot_len - remainder);
+  useg->len -= remainder;
+  TCPH_SET_FLAG(useg->tcphdr, split_flags);
+#if TCP_OVERSIZE_DBGCHECK
+  /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
+  useg->oversize_left = 0;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+
+  /* Add back to the queue with new trimmed pbuf */
+  pcb->snd_queuelen += pbuf_clen(useg->p);
+
+#if TCP_CHECKSUM_ON_COPY
+  /* The checksum on the split segment is now incorrect. We need to re-run it over the split */
+  useg->chksum = 0;
+  useg->chksum_swapped = 0;
+  q = useg->p;
+  offset = q->tot_len - useg->len; /* Offset due to exposed headers */
+
+  /* Advance to the pbuf where the offset ends */
+  while (q != NULL && offset > q->len) {
+    offset -= q->len;
+    q = q->next;
+  }
+  LWIP_ASSERT("Found start of payload pbuf", q != NULL);
+  /* Checksum the first payload pbuf accounting for offset, then other pbufs are all payload */
+  for (; q != NULL; offset = 0, q = q->next) {
+    tcp_seg_add_chksum(~inet_chksum((const u8_t *)q->payload + offset, q->len - offset), q->len - offset,
+                       &useg->chksum, &useg->chksum_swapped);
+  }
+#endif /* TCP_CHECKSUM_ON_COPY */
+
+  /* Update number of segments on the queues. Note that length now may
+   * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
+   * because the total amount of data is constant when packet is split */
+  pcb->snd_queuelen += pbuf_clen(seg->p);
+
+  /* Finally insert remainder into queue after split (which stays head) */
+  seg->next = useg->next;
+  useg->next = seg;
+
+#if TCP_OVERSIZE
+  /* If remainder is last segment on the unsent, ensure we clear the oversize amount
+   * because the remainder is always sized to the exact remaining amount */
+  if (seg->next == NULL) {
+    pcb->unsent_oversize = 0;
+  }
+#endif /* TCP_OVERSIZE */
+
+  return ERR_OK;
+memerr:
+  TCP_STATS_INC(tcp.memerr);
+
+  LWIP_ASSERT("seg == NULL", seg == NULL);
+  if (p != NULL) {
+    pbuf_free(p);
+  }
+
+  return ERR_MEM;
+}
+
+/**
+ * Called by tcp_close() to send a segment including FIN flag but not data.
+ * This FIN may be added to an existing segment or a new, otherwise empty
+ * segment is enqueued.
+ *
+ * @param pcb the tcp_pcb over which to send a segment
+ * @return ERR_OK if sent, another err_t otherwise
+ */
+err_t
+tcp_send_fin(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
+
+  /* first, try to add the fin to the last unsent segment */
+  if (pcb->unsent != NULL) {
+    struct tcp_seg *last_unsent;
+    for (last_unsent = pcb->unsent; last_unsent->next != NULL;
+         last_unsent = last_unsent->next);
+
+    if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
+      /* no SYN/FIN/RST flag in the header, we can add the FIN flag */
+      TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
+      tcp_set_flags(pcb, TF_FIN);
+      return ERR_OK;
+    }
+  }
+  /* no data, no length, flags, copy=1, no optdata */
+  return tcp_enqueue_flags(pcb, TCP_FIN);
+}
+
+/**
+ * Enqueue SYN or FIN for transmission.
+ *
+ * Called by @ref tcp_connect, tcp_listen_input, and @ref tcp_close
+ * (via @ref tcp_send_fin)
+ *
+ * @param pcb Protocol control block for the TCP connection.
+ * @param flags TCP header flags to set in the outgoing segment.
+ */
+err_t
+tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg;
+  u8_t optflags = 0;
+  u8_t optlen = 0;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
+              (flags & (TCP_SYN | TCP_FIN)) != 0);
+  LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
+
+  /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
+
+  /* Get options for this segment. This is a special case since this is the
+     only place where a SYN can be sent. */
+  if (flags & TCP_SYN) {
+    optflags = TF_SEG_OPTS_MSS;
+#if LWIP_WND_SCALE
+    if ((pcb->state != SYN_RCVD) || (pcb->flags & TF_WND_SCALE)) {
+      /* In a <SYN,ACK> (sent in state SYN_RCVD), the window scale option may only
+         be sent if we received a window scale option from the remote host. */
+      optflags |= TF_SEG_OPTS_WND_SCALE;
+    }
+#endif /* LWIP_WND_SCALE */
+#if LWIP_TCP_SACK_OUT
+    if ((pcb->state != SYN_RCVD) || (pcb->flags & TF_SACK)) {
+      /* In a <SYN,ACK> (sent in state SYN_RCVD), the SACK_PERM option may only
+         be sent if we received a SACK_PERM option from the remote host. */
+      optflags |= TF_SEG_OPTS_SACK_PERM;
+    }
+#endif /* LWIP_TCP_SACK_OUT */
+  }
+#if LWIP_TCP_TIMESTAMPS
+  if ((pcb->flags & TF_TIMESTAMP) || ((flags & TCP_SYN) && (pcb->state != SYN_RCVD))) {
+    /* Make sure the timestamp option is only included in data segments if we
+       agreed about it with the remote host (and in active open SYN segments). */
+    optflags |= TF_SEG_OPTS_TS;
+  }
+#endif /* LWIP_TCP_TIMESTAMPS */
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
+
+  /* Allocate pbuf with room for TCP header + options */
+  if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
+              (p->len >= optlen));
+
+  /* Allocate memory for tcp_seg, and fill in fields. */
+  if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
+    tcp_set_flags(pcb, TF_NAGLEMEMERR);
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
+  LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE,
+              ("tcp_enqueue_flags: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
+               lwip_ntohl(seg->tcphdr->seqno),
+               lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+               (u16_t)flags));
+
+  /* Now append seg to pcb->unsent queue */
+  if (pcb->unsent == NULL) {
+    pcb->unsent = seg;
+  } else {
+    struct tcp_seg *useg;
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+    useg->next = seg;
+  }
+#if TCP_OVERSIZE
+  /* The new unsent tail has no space */
+  pcb->unsent_oversize = 0;
+#endif /* TCP_OVERSIZE */
+
+  /* SYN and FIN bump the sequence number */
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    pcb->snd_lbb++;
+    /* optlen does not influence snd_buf */
+  }
+  if (flags & TCP_FIN) {
+    tcp_set_flags(pcb, TF_FIN);
+  }
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen += pbuf_clen(seg->p);
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
+                pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  return ERR_OK;
+}
+
+#if LWIP_TCP_TIMESTAMPS
+/* Build a timestamp option (12 bytes long) at the specified options pointer)
+ *
+ * @param pcb tcp_pcb
+ * @param opts option pointer where to store the timestamp option
+ */
+static void
+tcp_build_timestamp_option(const struct tcp_pcb *pcb, u32_t *opts)
+{
+  LWIP_ASSERT("tcp_build_timestamp_option: invalid pcb", pcb != NULL);
+
+  /* Pad with two NOP options to make everything nicely aligned */
+  opts[0] = PP_HTONL(0x0101080A);
+  opts[1] = lwip_htonl(Milliseconds());
+  opts[2] = lwip_htonl(pcb->ts_recent);
+}
+#endif
+
+#if LWIP_TCP_SACK_OUT
+/**
+ * Calculates the number of SACK entries that should be generated.
+ * It takes into account whether TF_SACK flag is set,
+ * the number of SACK entries in tcp_pcb that are valid,
+ * as well as the available options size.
+ *
+ * @param pcb tcp_pcb
+ * @param optlen the length of other TCP options (in bytes)
+ * @return the number of SACK ranges that can be used
+ */
+static u8_t
+tcp_get_num_sacks(const struct tcp_pcb *pcb, u8_t optlen)
+{
+  u8_t num_sacks = 0;
+
+  LWIP_ASSERT("tcp_get_num_sacks: invalid pcb", pcb != NULL);
+
+  if (pcb->flags & TF_SACK) {
+    u8_t i;
+
+    /* The first SACK takes up 12 bytes (it includes SACK header and two NOP options),
+       each additional one - 8 bytes. */
+    optlen += 12;
+
+    /* Max options size = 40, number of SACK array entries = LWIP_TCP_MAX_SACK_NUM */
+    for (i = 0; (i < LWIP_TCP_MAX_SACK_NUM) && (optlen <= TCP_MAX_OPTION_BYTES) &&
+         LWIP_TCP_SACK_VALID(pcb, i); ++i) {
+      ++num_sacks;
+      optlen += 8;
+    }
+  }
+
+  return num_sacks;
+}
+
+/** Build a SACK option (12 or more bytes long) at the specified options pointer)
+ *
+ * @param pcb tcp_pcb
+ * @param opts option pointer where to store the SACK option
+ * @param num_sacks the number of SACKs to store
+ */
+static void
+tcp_build_sack_option(const struct tcp_pcb *pcb, u32_t *opts, u8_t num_sacks)
+{
+  u8_t i;
+
+  LWIP_ASSERT("tcp_build_sack_option: invalid pcb", pcb != NULL);
+  LWIP_ASSERT("tcp_build_sack_option: invalid opts", opts != NULL);
+
+  /* Pad with two NOP options to make everything nicely aligned.
+     We add the length (of just the SACK option, not the NOPs in front of it),
+     which is 2B of header, plus 8B for each SACK. */
+  *(opts++) = PP_HTONL(0x01010500 + 2 + num_sacks * 8);
+
+  for (i = 0; i < num_sacks; ++i) {
+    *(opts++) = lwip_htonl(pcb->rcv_sacks[i].left);
+    *(opts++) = lwip_htonl(pcb->rcv_sacks[i].right);
+  }
+}
+
+#endif
+
+#if LWIP_WND_SCALE
+/** Build a window scale option (3 bytes long) at the specified options pointer)
+ *
+ * @param opts option pointer where to store the window scale option
+ */
+static void
+tcp_build_wnd_scale_option(u32_t *opts)
+{
+  LWIP_ASSERT("tcp_build_wnd_scale_option: invalid opts", opts != NULL);
+
+  /* Pad with one NOP option to make everything nicely aligned */
+  opts[0] = PP_HTONL(0x01030300 | TCP_RCV_SCALE);
+}
+#endif
+
+/**
+ * @ingroup tcp_raw
+ * Find out what we can send and send it
+ *
+ * @param pcb Protocol control block for the TCP connection to send data
+ * @return ERR_OK if data has been sent or nothing to send
+ *         another err_t on error
+ */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg, *useg;
+  u32_t wnd, snd_nxt;
+  err_t err;
+  struct netif *netif;
+#if TCP_CWND_DEBUG
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
+  /* pcb->state LISTEN not allowed here */
+  LWIP_ASSERT("don't call tcp_output for listen-pcbs",
+              pcb->state != LISTEN);
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n",
+                                   (void *)pcb->unsent));
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"TCPWNDSIZE_F
+                                 ", cwnd %"TCPWNDSIZE_F", wnd %"U32_F
+                                 ", seg == NULL, ack %"U32_F"\n",
+                                 pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
+
+    /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
+     * an empty ACK segment and send it. */
+    if (pcb->flags & TF_ACK_NOW) {
+      return tcp_send_empty_ack(pcb);
+    }
+    /* nothing to send: shortcut out of here */
+    goto output_done;
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG,
+                ("tcp_output: snd_wnd %"TCPWNDSIZE_F", cwnd %"TCPWNDSIZE_F", wnd %"U32_F
+                 ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
+                 pcb->snd_wnd, pcb->cwnd, wnd,
+                 lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                 lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+
+  netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
+  if (netif == NULL) {
+    return ERR_RTE;
+  }
+
+  /* If we don't have a local IP address, we get one from netif */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
+    if (local_ip == NULL) {
+      return ERR_RTE;
+    }
+    ip_addr_copy(pcb->local_ip, *local_ip);
+  }
+
+  /* Handle the current segment not fitting within the window */
+  if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
+    /* We need to start the persistent timer when the next unsent segment does not fit
+     * within the remaining (could be 0) send window and RTO timer is not running (we
+     * have no in-flight data). If window is still too small after persist timer fires,
+     * then we split the segment. We don't consider the congestion window since a cwnd
+     * smaller than 1 SMSS implies in-flight data
+     */
+    if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
+      pcb->persist_cnt = 0;
+      pcb->persist_backoff = 1;
+      pcb->persist_probe = 0;
+    }
+    /* We need an ACK, but can't send data now, so send an empty ACK */
+    if (pcb->flags & TF_ACK_NOW) {
+      return tcp_send_empty_ack(pcb);
+    }
+    goto output_done;
+  }
+  /* Stop persist timer, above conditions are not active */
+  pcb->persist_backoff = 0;
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+         lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+    LWIP_ASSERT("RST not expected here!",
+                (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0);
+    /* Stop sending if the nagle algorithm would prevent it
+     * Don't stop:
+     * - if tcp_write had a memory error before (prevent delayed ACK timeout) or
+     * - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
+     *   either seg->next != NULL or pcb->unacked == NULL;
+     *   RST is no sent using tcp_write/tcp_output.
+     */
+    if ((tcp_do_output_nagle(pcb) == 0) &&
+        ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
+      break;
+    }
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"TCPWNDSIZE_F", cwnd %"TCPWNDSIZE_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
+                                 pcb->snd_wnd, pcb->cwnd, wnd,
+                                 lwip_ntohl(seg->tcphdr->seqno) + seg->len -
+                                 pcb->lastack,
+                                 lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+    }
+
+    err = tcp_output_segment(seg, pcb, netif);
+    if (err != ERR_OK) {
+      /* segment could not be sent, for whatever reason */
+      tcp_set_flags(pcb, TF_NAGLEMEMERR);
+      return err;
+    }
+#if TCP_OVERSIZE_DBGCHECK
+    seg->oversize_left = 0;
+#endif /* TCP_OVERSIZE_DBGCHECK */
+    pcb->unsent = seg->next;
+    if (pcb->state != SYN_SENT) {
+      tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+    }
+    snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
+      pcb->snd_nxt = snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+        /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather somewhere before it. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
+          /* add segment to before tail of unacked list, keeping the list sorted */
+          struct tcp_seg **cur_seg = &(pcb->unacked);
+          while (*cur_seg &&
+                 TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
+            cur_seg = &((*cur_seg)->next );
+          }
+          seg->next = (*cur_seg);
+          (*cur_seg) = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+      /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+#if TCP_OVERSIZE
+  if (pcb->unsent == NULL) {
+    /* last unsent has been removed, reset unsent_oversize */
+    pcb->unsent_oversize = 0;
+  }
+#endif /* TCP_OVERSIZE */
+
+output_done:
+  tcp_clear_flags(pcb, TF_NAGLEMEMERR);
+  return ERR_OK;
+}
+
+/** Check if a segment's pbufs are used by someone else than TCP.
+ * This can happen on retransmission if the pbuf of this segment is still
+ * referenced by the netif driver due to deferred transmission.
+ * This is the case (only!) if someone down the TX call path called
+ * pbuf_ref() on one of the pbufs!
+ *
+ * @arg seg the tcp segment to check
+ * @return 1 if ref != 1, 0 if ref == 1
+ */
+static int
+tcp_output_segment_busy(const struct tcp_seg *seg)
+{
+  LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
+
+  /* We only need to check the first pbuf here:
+     If a pbuf is queued for transmission, a driver calls pbuf_ref(),
+     which only changes the ref count of the first pbuf */
+  if (seg->p->ref != 1) {
+    /* other reference found */
+    return 1;
+  }
+  /* no other references found */
+  return 0;
+}
+
+/**
+ * Called by tcp_output() to actually send a TCP segment over IP.
+ *
+ * @param seg the tcp_seg to send
+ * @param pcb the tcp_pcb for the TCP connection used to send the segment
+ * @param netif the netif used to send the segment
+ */
+static err_t
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
+{
+  err_t err;
+  u16_t len;
+  u32_t *opts;
+#if TCP_CHECKSUM_ON_COPY
+  int seg_chksum_was_swapped = 0;
+#endif
+
+  LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
+  LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
+  LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
+
+  if (tcp_output_segment_busy(seg)) {
+    /* This should not happen: rexmit functions should have checked this.
+       However, since this function modifies p->len, we must not continue in this case. */
+    LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
+    return ERR_OK;
+  }
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
+
+  /* advertise our receive window size in this TCP segment */
+#if LWIP_WND_SCALE
+  if (seg->flags & TF_SEG_OPTS_WND_SCALE) {
+    /* The Window field in a SYN segment itself (the only type where we send
+       the window scale option) is never scaled. */
+    seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
+  } else
+#endif /* LWIP_WND_SCALE */
+  {
+    seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
+  }
+
+  pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+
+  /* Add any requested options.  NB MSS option is only set on SYN
+     packets, so ignore it here */
+  /* cast through void* to get rid of alignment warnings */
+  opts = (u32_t *)(void *)(seg->tcphdr + 1);
+  if (seg->flags & TF_SEG_OPTS_MSS) {
+    u16_t mss;
+#if TCP_CALCULATE_EFF_SEND_MSS
+    mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
+#else /* TCP_CALCULATE_EFF_SEND_MSS */
+    mss = TCP_MSS;
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+    *opts = TCP_BUILD_MSS_OPTION(mss);
+    opts += 1;
+  }
+#if LWIP_TCP_TIMESTAMPS
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+
+  if (seg->flags & TF_SEG_OPTS_TS) {
+    tcp_build_timestamp_option(pcb, opts);
+    opts += 3;
+  }
+#endif
+#if LWIP_WND_SCALE
+  if (seg->flags & TF_SEG_OPTS_WND_SCALE) {
+    tcp_build_wnd_scale_option(opts);
+    opts += 1;
+  }
+#endif
+#if LWIP_TCP_SACK_OUT
+  if (seg->flags & TF_SEG_OPTS_SACK_PERM) {
+    /* Pad with two NOP options to make everything nicely aligned
+     * NOTE: When we send both timestamp and SACK_PERM options,
+     * we could use the first two NOPs before the timestamp to store SACK_PERM option,
+     * but that would complicate the code.
+     */
+    *(opts++) = PP_HTONL(0x01010402);
+  }
+#endif
+
+  /* Set retransmission timer running if it is not currently enabled
+     This must be set before checking the route. */
+  if (pcb->rtime < 0) {
+    pcb->rtime = 0;
+  }
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+                                 lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
+                                 seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+  if (len == 0) {
+    /** Exclude retransmitted segments from this count. */
+    MIB2_STATS_INC(mib2.tcpoutsegs);
+  }
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+
+#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
+  opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
+#endif
+  LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
+
+#if CHECKSUM_GEN_TCP
+  IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) {
+#if TCP_CHECKSUM_ON_COPY
+    u32_t acc;
+#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+    u16_t chksum_slow = ip_chksum_pseudo(seg->p, IP_PROTO_TCP,
+                                         seg->p->tot_len, &pcb->local_ip, &pcb->remote_ip);
+#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */
+    if ((seg->flags & TF_SEG_DATA_CHECKSUMMED) == 0) {
+      LWIP_ASSERT("data included but not checksummed",
+                  seg->p->tot_len == TCPH_HDRLEN_BYTES(seg->tcphdr));
+    }
+
+    /* rebuild TCP header checksum (TCP header changes for retransmissions!) */
+    acc = ip_chksum_pseudo_partial(seg->p, IP_PROTO_TCP,
+                                   seg->p->tot_len, TCPH_HDRLEN_BYTES(seg->tcphdr), &pcb->local_ip, &pcb->remote_ip);
+    /* add payload checksum */
+    if (seg->chksum_swapped) {
+      seg_chksum_was_swapped = 1;
+      seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
+      seg->chksum_swapped = 0;
+    }
+    acc = (u16_t)~acc + seg->chksum;
+    seg->tcphdr->chksum = (u16_t)~FOLD_U32T(acc);
+#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK
+    if (chksum_slow != seg->tcphdr->chksum) {
+      TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL(
+        ("tcp_output_segment: calculated checksum is %"X16_F" instead of %"X16_F"\n",
+         seg->tcphdr->chksum, chksum_slow));
+      seg->tcphdr->chksum = chksum_slow;
+    }
+#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */
+#else /* TCP_CHECKSUM_ON_COPY */
+    seg->tcphdr->chksum = ip_chksum_pseudo(seg->p, IP_PROTO_TCP,
+                                           seg->p->tot_len, &pcb->local_ip, &pcb->remote_ip);
+#endif /* TCP_CHECKSUM_ON_COPY */
+  }
+#endif /* CHECKSUM_GEN_TCP */
+  TCP_STATS_INC(tcp.xmit);
+
+  NETIF_SET_HINTS(netif, &(pcb->netif_hints));
+  err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
+                     pcb->tos, IP_PROTO_TCP, netif);
+  NETIF_RESET_HINTS(netif);
+
+#if TCP_CHECKSUM_ON_COPY
+  if (seg_chksum_was_swapped) {
+    /* if data is added to this segment later, chksum needs to be swapped,
+       so restore this now */
+    seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
+    seg->chksum_swapped = 1;
+  }
+#endif
+
+  return err;
+}
+
+/**
+ * Requeue all unacked segments for retransmission
+ *
+ * Called by tcp_slowtmr() for slow retransmission.
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+err_t
+tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
+
+  if (pcb->unacked == NULL) {
+    return ERR_VAL;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue.
+     However, give up if any of the unsent pbufs are still referenced by the
+     netif driver due to deferred transmission. No point loading the link further
+     if it is struggling to flush its buffered writes. */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
+    if (tcp_output_segment_busy(seg)) {
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
+      return ERR_VAL;
+    }
+  }
+  if (tcp_output_segment_busy(seg)) {
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
+    return ERR_VAL;
+  }
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+#if TCP_OVERSIZE_DBGCHECK
+  /* if last unsent changed, we need to update unsent_oversize */
+  if (pcb->unsent == NULL) {
+    pcb->unsent_oversize = seg->oversize_left;
+  }
+#endif /* TCP_OVERSIZE_DBGCHECK */
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  /* Mark RTO in-progress */
+  tcp_set_flags(pcb, TF_RTO);
+  /* Record the next byte following retransmit */
+  pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  return ERR_OK;
+}
+
+/**
+ * Requeue all unacked segments for retransmission
+ *
+ * Called by tcp_slowtmr() for slow retransmission.
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
+
+  /* increment number of retransmissions */
+  if (pcb->nrtx < 0xFF) {
+    ++pcb->nrtx;
+  }
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+/**
+ * Requeue all unacked segments for retransmission
+ *
+ * Called by tcp_process() only, tcp_slowtmr() needs to do some things between
+ * "prepare" and "commit".
+ *
+ * @param pcb the tcp_pcb for which to re-enqueue all unacked segments
+ */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
+
+  if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
+    tcp_rexmit_rto_commit(pcb);
+  }
+}
+
+/**
+ * Requeue the first unacked segment for retransmission
+ *
+ * Called by tcp_receive() for fast retransmit.
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+err_t
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+  struct tcp_seg **cur_seg;
+
+  LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
+
+  if (pcb->unacked == NULL) {
+    return ERR_VAL;
+  }
+
+  seg = pcb->unacked;
+
+  /* Give up if the segment is still referenced by the netif driver
+     due to deferred transmission. */
+  if (tcp_output_segment_busy(seg)) {
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
+    return ERR_VAL;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  /* Keep the unsent queue sorted. */
+  pcb->unacked = seg->next;
+
+  cur_seg = &(pcb->unsent);
+  while (*cur_seg &&
+         TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
+    cur_seg = &((*cur_seg)->next );
+  }
+  seg->next = *cur_seg;
+  *cur_seg = seg;
+#if TCP_OVERSIZE
+  if (seg->next == NULL) {
+    /* the retransmitted segment is last in unsent, so reset unsent_oversize */
+    pcb->unsent_oversize = 0;
+  }
+#endif /* TCP_OVERSIZE */
+
+  if (pcb->nrtx < 0xFF) {
+    ++pcb->nrtx;
+  }
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  MIB2_STATS_INC(mib2.tcpretranssegs);
+  /* No need to call tcp_output: we are always called from tcp_input()
+     and thus tcp_output directly returns. */
+  return ERR_OK;
+}
+
+
+/**
+ * Handle retransmission after three dupacks received
+ *
+ * @param pcb the tcp_pcb for which to retransmit the first unacked segment
+ */
+void
+tcp_rexmit_fast(struct tcp_pcb *pcb)
+{
+  LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
+
+  if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
+    /* This is fast retransmit. Retransmit the first unacked segment. */
+    LWIP_DEBUGF(TCP_FR_DEBUG,
+                ("tcp_receive: dupacks %"U16_F" (%"U32_F
+                 "), fast retransmit %"U32_F"\n",
+                 (u16_t)pcb->dupacks, pcb->lastack,
+                 lwip_ntohl(pcb->unacked->tcphdr->seqno)));
+    if (tcp_rexmit(pcb) == ERR_OK) {
+      /* Set ssthresh to half of the minimum of the current
+       * cwnd and the advertised window */
+      pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
+
+      /* The minimum value for ssthresh should be 2 MSS */
+      if (pcb->ssthresh < (2U * pcb->mss)) {
+        LWIP_DEBUGF(TCP_FR_DEBUG,
+                    ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
+                     " should be min 2 mss %"U16_F"...\n",
+                     pcb->ssthresh, (u16_t)(2 * pcb->mss)));
+        pcb->ssthresh = 2 * pcb->mss;
+      }
+
+      pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+      tcp_set_flags(pcb, TF_INFR);
+
+      /* Reset the retransmission timer to prevent immediate rto retransmissions */
+      pcb->rtime = 0;
+    }
+  }
+}
+
+static struct pbuf *
+tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
+                        u32_t seqno_be /* already in network byte order */,
+                        u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
+{
+  struct tcp_hdr *tcphdr;
+  struct pbuf *p;
+
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
+  if (p != NULL) {
+    LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
+                (p->len >= TCP_HLEN + optlen));
+    tcphdr = (struct tcp_hdr *)p->payload;
+    tcphdr->src = lwip_htons(src_port);
+    tcphdr->dest = lwip_htons(dst_port);
+    tcphdr->seqno = seqno_be;
+    tcphdr->ackno = lwip_htonl(ackno);
+    TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
+    tcphdr->wnd = lwip_htons(wnd);
+    tcphdr->chksum = 0;
+    tcphdr->urgp = 0;
+  }
+  return p;
+}
+
+/** Allocate a pbuf and create a tcphdr at p->payload, used for output
+ * functions other than the default tcp_output -> tcp_output_segment
+ * (e.g. tcp_send_empty_ack, etc.)
+ *
+ * @param pcb tcp pcb for which to send a packet (used to initialize tcp_hdr)
+ * @param optlen length of header-options
+ * @param datalen length of tcp data to reserve in pbuf
+ * @param seqno_be seqno in network byte order (big-endian)
+ * @return pbuf with p->payload being the tcp_hdr
+ */
+static struct pbuf *
+tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
+                        u32_t seqno_be /* already in network byte order */)
+{
+  struct pbuf *p;
+
+  LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
+
+  p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
+    seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
+    TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
+  if (p != NULL) {
+    /* If we're sending a packet, update the announced right window edge */
+    pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
+  }
+  return p;
+}
+
+/* Fill in options for control segments */
+static void
+tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
+{
+  struct tcp_hdr *tcphdr;
+  u32_t *opts;
+  u16_t sacks_len = 0;
+
+  LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
+
+  tcphdr = (struct tcp_hdr *)p->payload;
+  opts = (u32_t *)(void *)(tcphdr + 1);
+
+  /* NB. MSS and window scale options are only sent on SYNs, so ignore them here */
+
+#if LWIP_TCP_TIMESTAMPS
+  if (optflags & TF_SEG_OPTS_TS) {
+    tcp_build_timestamp_option(pcb, opts);
+    opts += 3;
+  }
+#endif
+
+#if LWIP_TCP_SACK_OUT
+  if (pcb && (num_sacks > 0)) {
+    tcp_build_sack_option(pcb, opts, num_sacks);
+    /* 1 word for SACKs header (including 2xNOP), and 2 words for each SACK */
+    sacks_len = 1 + num_sacks * 2;
+    opts += sacks_len;
+  }
+#else
+  LWIP_UNUSED_ARG(num_sacks);
+#endif
+
+#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
+  opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
+#endif
+
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(sacks_len);
+  LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
+  LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
+  LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
+}
+
+/** Output a control segment pbuf to IP.
+ *
+ * Called from tcp_rst, tcp_send_empty_ack, tcp_keepalive and tcp_zero_window_probe,
+ * this function combines selecting a netif for transmission, generating the tcp
+ * header checksum and calling ip_output_if while handling netif hints and stats.
+ */
+static err_t
+tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
+                           const ip_addr_t *src, const ip_addr_t *dst)
+{
+  err_t err;
+  struct netif *netif;
+
+  LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
+
+  netif = tcp_route(pcb, src, dst);
+  if (netif == NULL) {
+    err = ERR_RTE;
+  } else {
+    u8_t ttl, tos;
+#if CHECKSUM_GEN_TCP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) {
+      struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
+      tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
+                                        src, dst);
+    }
+#endif
+    if (pcb != NULL) {
+      NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
+      ttl = pcb->ttl;
+      tos = pcb->tos;
+    } else {
+      /* Send output with hardcoded TTL/HL since we have no access to the pcb */
+      ttl = TCP_TTL;
+      tos = 0;
+    }
+    TCP_STATS_INC(tcp.xmit);
+    err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
+    NETIF_RESET_HINTS(netif);
+  }
+  pbuf_free(p);
+  return err;
+}
+
+/**
+ * Send a TCP RESET packet (empty segment with RST flag set) either to
+ * abort a connection or to show that there is no matching local connection
+ * for a received segment.
+ *
+ * Called by tcp_abort() (to abort a local connection), tcp_input() (if no
+ * matching local pcb was found), tcp_listen_input() (if incoming segment
+ * has ACK flag set) and tcp_process() (received segment in the wrong state)
+ *
+ * Since a RST segment is in most cases not sent for an active connection,
+ * tcp_rst() has a number of arguments that are taken from a tcp_pcb for
+ * most other segment output functions.
+ *
+ * @param pcb TCP pcb (may be NULL if no pcb is available)
+ * @param seqno the sequence number to use for the outgoing segment
+ * @param ackno the acknowledge number to use for the outgoing segment
+ * @param local_ip the local IP address to send the segment from
+ * @param remote_ip the remote IP address to send the segment to
+ * @param local_port the local TCP port to send the segment from
+ * @param remote_port the remote TCP port to send the segment to
+ */
+void
+tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
+        const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
+        u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  u16_t wnd;
+  u8_t optlen;
+
+  LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
+  LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
+
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+
+#if LWIP_WND_SCALE
+  wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
+#else
+  wnd = PP_HTONS(TCP_WND);
+#endif
+
+  p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
+    remote_port, TCP_RST | TCP_ACK, wnd);
+  if (p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+    return;
+  }
+  tcp_output_fill_options(pcb, p, 0, optlen);
+
+  MIB2_STATS_INC(mib2.tcpoutrsts);
+
+  tcp_output_control_segment(pcb, p, local_ip, remote_ip);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+
+/**
+ * Send an ACK without data.
+ *
+ * @param pcb Protocol control block for the TCP connection to send the ACK
+ */
+err_t
+tcp_send_empty_ack(struct tcp_pcb *pcb)
+{
+  err_t err;
+  struct pbuf *p;
+  u8_t optlen, optflags = 0;
+  u8_t num_sacks = 0;
+
+  LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
+
+#if LWIP_TCP_TIMESTAMPS
+  if (pcb->flags & TF_TIMESTAMP) {
+    optflags = TF_SEG_OPTS_TS;
+  }
+#endif
+  optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
+
+#if LWIP_TCP_SACK_OUT
+  /* For now, SACKs are only sent with empty ACKs */
+  if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
+    optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
+  }
+#endif
+
+  p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
+  if (p == NULL) {
+    /* let tcp_fasttmr retry sending this ACK */
+    tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+    return ERR_BUF;
+  }
+  tcp_output_fill_options(pcb, p, optflags, num_sacks);
+
+#if LWIP_TCP_TIMESTAMPS
+  pcb->ts_lastacksent = pcb->rcv_nxt;
+#endif
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
+              ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
+  if (err != ERR_OK) {
+    /* let tcp_fasttmr retry sending this ACK */
+    tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+  } else {
+    /* remove ACK flags from the PCB, as we sent an empty ACK now */
+    tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
+  }
+
+  return err;
+}
+
+/**
+ * Send keepalive packets to keep a connection active although
+ * no data is sent over it.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a keepalive packet
+ */
+err_t
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+  err_t err;
+  struct pbuf *p;
+  u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+
+  LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to "));
+  ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
+                          tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
+
+  p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
+  if (p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG,
+                ("tcp_keepalive: could not allocate memory for pbuf\n"));
+    return ERR_MEM;
+  }
+  tcp_output_fill_options(pcb, p, 0, optlen);
+  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
+  return err;
+}
+
+/**
+ * Send persist timer zero-window probes to keep a connection active
+ * when a window update is lost.
+ *
+ * Called by tcp_slowtmr()
+ *
+ * @param pcb the tcp_pcb for which to send a zero-window probe packet
+ */
+err_t
+tcp_zero_window_probe(struct tcp_pcb *pcb)
+{
+  err_t err;
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg;
+  u16_t len;
+  u8_t is_fin;
+  u32_t snd_nxt;
+  u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
+
+  LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: sending ZERO WINDOW probe to "));
+  ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+
+  LWIP_DEBUGF(TCP_DEBUG,
+              ("tcp_zero_window_probe: tcp_ticks %"U32_F
+               "   pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
+               tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
+
+  /* Only consider unsent, persist timer should be off when there is data in-flight */
+  seg = pcb->unsent;
+  if (seg == NULL) {
+    /* Not expected, persist timer should be off when the send buffer is empty */
+    return ERR_OK;
+  }
+
+  /* increment probe count. NOTE: we record probe even if it fails
+     to actually transmit due to an error. This ensures memory exhaustion/
+     routing problem doesn't leave a zero-window pcb as an indefinite zombie.
+     RTO mechanism has similar behavior, see pcb->nrtx */
+  if (pcb->persist_probe < 0xFF) {
+    ++pcb->persist_probe;
+  }
+
+  is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
+  /* we want to send one seqno: either FIN or data (no options) */
+  len = is_fin ? 0 : 1;
+
+  p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
+  if (p == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
+    return ERR_MEM;
+  }
+  tcphdr = (struct tcp_hdr *)p->payload;
+
+  if (is_fin) {
+    /* FIN segment, no data */
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
+  } else {
+    /* Data segment, copy in one byte from the head of the unacked queue */
+    char *d = ((char *)p->payload + TCP_HLEN);
+    /* Depending on whether the segment has already been sent (unacked) or not
+       (unsent), seg->p->payload points to the IP header or TCP header.
+       Ensure we copy the first TCP data byte: */
+    pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
+  }
+
+  /* The byte may be acknowledged without the window being opened. */
+  snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
+  if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
+    pcb->snd_nxt = snd_nxt;
+  }
+  tcp_output_fill_options(pcb, p, 0, optlen);
+
+  err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
+                          " ackno %"U32_F" err %d.\n",
+                          pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
+  return err;
+}
+#endif /* LWIP_TCP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/timeouts.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/timeouts.c
new file mode 100644
index 000000000..c1fa4a2b5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/timeouts.c
@@ -0,0 +1,451 @@
+/**
+ * @file
+ * Stack-internal timers implementation.
+ * This file includes timer callbacks for stack-internal timers as well as
+ * functions to set up or stop timers and check for expired timers.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *         Simon Goldschmidt
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/timeouts.h"
+#include "lwip/priv/tcp_priv.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#include "lwip/ip4_frag.h"
+#include "lwip/etharp.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/igmp.h"
+#include "lwip/dns.h"
+#include "lwip/nd6.h"
+#include "lwip/ip6_frag.h"
+#include "lwip/mld6.h"
+#include "lwip/dhcp6.h"
+#include "lwip/sys.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_DEBUG_TIMERNAMES
+#define HANDLER(x) x, #x
+#else /* LWIP_DEBUG_TIMERNAMES */
+#define HANDLER(x) x
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+#define LWIP_MAX_TIMEOUT  0x7fffffff
+
+/* Check if timer's expiry time is greater than time and care about u32_t wraparounds */
+#define TIME_LESS_THAN(t, compare_to) ( (((u32_t)((t)-(compare_to))) > LWIP_MAX_TIMEOUT) ? 1 : 0 )
+
+/** This array contains all stack-internal cyclic timers. To get the number of
+ * timers, use LWIP_ARRAYSIZE() */
+const struct lwip_cyclic_timer lwip_cyclic_timers[] = {
+#if LWIP_TCP
+  /* The TCP timer is a special case: it does not have to run always and
+     is triggered to start from TCP using tcp_timer_needed() */
+  {TCP_TMR_INTERVAL, HANDLER(tcp_tmr)},
+#endif /* LWIP_TCP */
+#if LWIP_IPV4
+#if IP_REASSEMBLY
+  {IP_TMR_INTERVAL, HANDLER(ip_reass_tmr)},
+#endif /* IP_REASSEMBLY */
+#if LWIP_ARP
+  {ARP_TMR_INTERVAL, HANDLER(etharp_tmr)},
+#endif /* LWIP_ARP */
+#if LWIP_DHCP
+  {DHCP_COARSE_TIMER_MSECS, HANDLER(dhcp_coarse_tmr)},
+  {DHCP_FINE_TIMER_MSECS, HANDLER(dhcp_fine_tmr)},
+#endif /* LWIP_DHCP */
+#if LWIP_AUTOIP
+  {AUTOIP_TMR_INTERVAL, HANDLER(autoip_tmr)},
+#endif /* LWIP_AUTOIP */
+#if LWIP_IGMP
+  {IGMP_TMR_INTERVAL, HANDLER(igmp_tmr)},
+#endif /* LWIP_IGMP */
+#endif /* LWIP_IPV4 */
+#if LWIP_DNS
+  {DNS_TMR_INTERVAL, HANDLER(dns_tmr)},
+#endif /* LWIP_DNS */
+#if LWIP_IPV6
+  {ND6_TMR_INTERVAL, HANDLER(nd6_tmr)},
+#if LWIP_IPV6_REASS
+  {IP6_REASS_TMR_INTERVAL, HANDLER(ip6_reass_tmr)},
+#endif /* LWIP_IPV6_REASS */
+#if LWIP_IPV6_MLD
+  {MLD6_TMR_INTERVAL, HANDLER(mld6_tmr)},
+#endif /* LWIP_IPV6_MLD */
+#if LWIP_IPV6_DHCP6
+  {DHCP6_TIMER_MSECS, HANDLER(dhcp6_tmr)},
+#endif /* LWIP_IPV6_DHCP6 */
+#endif /* LWIP_IPV6 */
+};
+const int lwip_num_cyclic_timers = LWIP_ARRAYSIZE(lwip_cyclic_timers);
+
+#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM
+
+/** The one and only timeout list */
+static struct sys_timeo *next_timeout;
+
+static u32_t current_timeout_due_time;
+
+#if LWIP_TESTMODE
+struct sys_timeo**
+sys_timeouts_get_next_timeout(void)
+{
+  return &next_timeout;
+}
+#endif
+
+#if LWIP_TCP
+/** global variable that shows if the tcp timer is currently scheduled or not */
+static int tcpip_tcp_timer_active;
+
+/**
+ * Timer callback function that calls tcp_tmr() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+static void
+tcpip_tcp_timer(void *arg)
+{
+  LWIP_UNUSED_ARG(arg);
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+/**
+ * Called from TCP_REG when registering a new PCB:
+ * the reason is to have the TCP timer only running when
+ * there are active (or time-wait) PCBs.
+ */
+void
+tcp_timer_needed(void)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* LWIP_TCP */
+
+static void
+#if LWIP_DEBUG_TIMERNAMES
+sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
+#else /* LWIP_DEBUG_TIMERNAMES */
+sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
+#endif
+{
+  struct sys_timeo *timeout, *t;
+
+  timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
+    return;
+  }
+
+  timeout->next = NULL;
+  timeout->h = handler;
+  timeout->arg = arg;
+  timeout->time = abs_time;
+
+#if LWIP_DEBUG_TIMERNAMES
+  timeout->handler_name = handler_name;
+  LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
+                             (void *)timeout, abs_time, handler_name, (void *)arg));
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+  if (next_timeout == NULL) {
+    next_timeout = timeout;
+    return;
+  }
+  if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
+    timeout->next = next_timeout;
+    next_timeout = timeout;
+  } else {
+    for (t = next_timeout; t != NULL; t = t->next) {
+      if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+}
+
+/**
+ * Timer callback function that calls cyclic->handler() and reschedules itself.
+ *
+ * @param arg unused argument
+ */
+#if !LWIP_TESTMODE
+static
+#endif
+void
+lwip_cyclic_timer(void *arg)
+{
+  u32_t now;
+  u32_t next_timeout_time;
+  const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
+
+#if LWIP_DEBUG_TIMERNAMES
+  LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
+#endif
+  cyclic->handler();
+
+  now = Milliseconds();
+  next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms);  /* overflow handled by TIME_LESS_THAN macro */ 
+  if (TIME_LESS_THAN(next_timeout_time, now)) {
+    /* timer would immediately expire again -> "overload" -> restart without any correction */
+#if LWIP_DEBUG_TIMERNAMES
+    sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
+#else
+    sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
+#endif
+
+  } else {
+    /* correct cyclic interval with handler execution delay and sys_check_timeouts jitter */
+#if LWIP_DEBUG_TIMERNAMES
+    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
+#else
+    sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
+#endif
+  }
+}
+
+/** Initialize this module */
+void sys_timeouts_init(void)
+{
+  size_t i;
+  /* tcp_tmr() at index 0 is started on demand */
+  for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
+    /* we have to cast via size_t to get rid of const warning
+      (this is OK as cyclic_timer() casts back to const* */
+    sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
+  }
+}
+
+/**
+ * Create a one-shot timer (aka timeout). Timeouts are processed in the
+ * following cases:
+ * - while waiting for a message using sys_timeouts_mbox_fetch()
+ * - by calling sys_check_timeouts() (NO_SYS==1 only)
+ *
+ * @param msecs time in milliseconds after that the timer should expire
+ * @param handler callback function to call when msecs have elapsed
+ * @param arg argument to pass to the callback function
+ */
+#if LWIP_DEBUG_TIMERNAMES
+void
+sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void
+sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
+#endif /* LWIP_DEBUG_TIMERNAMES */
+{
+  u32_t next_timeout_time;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
+
+  next_timeout_time = (u32_t)(Milliseconds() + msecs); /* overflow handled by TIME_LESS_THAN macro */ 
+
+#if LWIP_DEBUG_TIMERNAMES
+  sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
+#else
+  sys_timeout_abs(next_timeout_time, handler, arg);
+#endif
+}
+
+/**
+ * Go through timeout list (for this task only) and remove the first matching
+ * entry (subsequent entries remain untouched), even though the timeout has not
+ * triggered yet.
+ *
+ * @param handler callback function that would be called by the timeout
+ * @param arg callback argument that would be passed to handler
+*/
+void
+sys_untimeout(sys_timeout_handler handler, void *arg)
+{
+  struct sys_timeo *prev_t, *t;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (next_timeout == NULL) {
+    return;
+  }
+
+  for (t = next_timeout, prev_t = NULL; t != NULL; prev_t = t, t = t->next) {
+    if ((t->h == handler) && (t->arg == arg)) {
+      /* We have a match */
+      /* Unlink from previous in list */
+      if (prev_t == NULL) {
+        next_timeout = t->next;
+      } else {
+        prev_t->next = t->next;
+      }
+      memp_free(MEMP_SYS_TIMEOUT, t);
+      return;
+    }
+  }
+  return;
+}
+
+/**
+ * @ingroup lwip_nosys
+ * Handle timeouts for NO_SYS==1 (i.e. without using
+ * tcpip_thread/sys_timeouts_mbox_fetch(). Uses Milliseconds() to call timeout
+ * handler functions when timeouts expire.
+ *
+ * Must be called periodically from your main loop.
+ */
+void
+sys_check_timeouts(void)
+{
+  u32_t now;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  /* Process only timers expired at the start of the function. */
+  now = Milliseconds();
+
+  do {
+    struct sys_timeo *tmptimeout;
+    sys_timeout_handler handler;
+    void *arg;
+
+    PBUF_CHECK_FREE_OOSEQ();
+
+    tmptimeout = next_timeout;
+    if (tmptimeout == NULL) {
+      return;
+    }
+
+    if (TIME_LESS_THAN(now, tmptimeout->time)) {
+      return;
+    }
+
+    /* Timeout has expired */
+    next_timeout = tmptimeout->next;
+    handler = tmptimeout->h;
+    arg = tmptimeout->arg;
+    current_timeout_due_time = tmptimeout->time;
+#if LWIP_DEBUG_TIMERNAMES
+    if (handler != NULL) {
+      LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
+                                 tmptimeout->handler_name, Milliseconds() - tmptimeout->time, arg));
+    }
+#endif /* LWIP_DEBUG_TIMERNAMES */
+    memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+    if (handler != NULL) {
+      handler(arg);
+    }
+    LWIP_TCPIP_THREAD_ALIVE();
+
+    /* Repeat until all expired timers have been called */
+  } while (1);
+}
+
+/** Rebase the timeout times to the current time.
+ * This is necessary if sys_check_timeouts() hasn't been called for a long
+ * time (e.g. while saving energy) to prevent all timer functions of that
+ * period being called.
+ */
+void
+sys_restart_timeouts(void)
+{
+  u32_t now;
+  u32_t base;
+  struct sys_timeo *t;
+
+  if (next_timeout == NULL) {
+    return;
+  }
+
+  now = Milliseconds();
+  base = next_timeout->time;
+
+  for (t = next_timeout; t != NULL; t = t->next) {
+    t->time = (t->time - base) + now;
+  }
+}
+
+/** Return the time left before the next timeout is due. If no timeouts are
+ * enqueued, returns 0xffffffff
+ */
+u32_t
+sys_timeouts_sleeptime(void)
+{
+  u32_t now;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (next_timeout == NULL) {
+    return SYS_TIMEOUTS_SLEEPTIME_INFINITE;
+  }
+  now = Milliseconds();
+  if (TIME_LESS_THAN(next_timeout->time, now)) {
+    return 0;
+  } else {
+    u32_t ret = (u32_t)(next_timeout->time - now);
+    LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT);
+    return ret;
+  }
+}
+
+#else /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */
+/* Satisfy the TCP code which calls this function */
+void
+tcp_timer_needed(void)
+{
+}
+#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/udp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/udp.c
new file mode 100644
index 000000000..9d2cb4af7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/core/udp.c
@@ -0,0 +1,1314 @@
+/**
+ * @file
+ * User Datagram Protocol module\n
+ * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828).\n
+ * See also @ref udp_raw
+ *
+ * @defgroup udp_raw UDP
+ * @ingroup callbackstyle_api
+ * User Datagram Protocol module\n
+ * @see @ref api
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'!
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/udp.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet_chksum.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/icmp6.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/dhcp.h"
+
+#include <string.h>
+
+#ifndef UDP_LOCAL_PORT_RANGE_START
+/* From http://www.iana.org/assignments/port-numbers:
+   "The Dynamic and/or Private Ports are those from 49152 through 65535" */
+#define UDP_LOCAL_PORT_RANGE_START  0xc000
+#define UDP_LOCAL_PORT_RANGE_END    0xffff
+#define UDP_ENSURE_LOCAL_PORT_RANGE(port) ((u16_t)(((port) & (u16_t)~UDP_LOCAL_PORT_RANGE_START) + UDP_LOCAL_PORT_RANGE_START))
+#endif
+
+/* last local UDP port */
+static u16_t udp_port = UDP_LOCAL_PORT_RANGE_START;
+
+/* The list of UDP PCBs */
+/* exported in udp.h (was static) */
+struct udp_pcb *udp_pcbs;
+
+/**
+ * Initialize this module.
+ */
+void
+udp_init(void)
+{
+#ifdef LWIP_RAND
+  udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
+#endif /* LWIP_RAND */
+}
+
+/**
+ * Allocate a new local UDP port.
+ *
+ * @return a new (free) local UDP port number
+ */
+static u16_t
+udp_new_port(void)
+{
+  u16_t n = 0;
+  struct udp_pcb *pcb;
+
+again:
+  if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) {
+    udp_port = UDP_LOCAL_PORT_RANGE_START;
+  }
+  /* Check all PCBs. */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == udp_port) {
+      if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) {
+        return 0;
+      }
+      goto again;
+    }
+  }
+  return udp_port;
+}
+
+/** Common code to see if the current input packet matches the pcb
+ * (current input packet is accessed via ip(4/6)_current_* macros)
+ *
+ * @param pcb pcb to check
+ * @param inp network interface on which the datagram was received (only used for IPv4)
+ * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
+ * @return 1 on match, 0 otherwise
+ */
+static u8_t
+udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
+{
+  LWIP_UNUSED_ARG(inp);       /* in IPv6 only case */
+  LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
+
+  LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
+  LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
+
+  /* check if PCB is bound to specific netif */
+  if ((pcb->netif_idx != NETIF_NO_INDEX) &&
+      (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
+    return 0;
+  }
+
+  /* Dual-stack: PCBs listening to any IP type also listen to any IP address */
+  if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) {
+#if LWIP_IPV4 && IP_SOF_BROADCAST_RECV
+    if ((broadcast != 0) && !ip_get_option(pcb, SOF_BROADCAST)) {
+      return 0;
+    }
+#endif /* LWIP_IPV4 && IP_SOF_BROADCAST_RECV */
+    return 1;
+  }
+
+  /* Only need to check PCB if incoming IP version matches PCB IP version */
+  if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
+#if LWIP_IPV4
+    /* Special case: IPv4 broadcast: all or broadcasts in my subnet
+     * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
+    if (broadcast != 0) {
+#if IP_SOF_BROADCAST_RECV
+      if (ip_get_option(pcb, SOF_BROADCAST))
+#endif /* IP_SOF_BROADCAST_RECV */
+      {
+        if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
+            ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
+            ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
+          return 1;
+        }
+      }
+    } else
+#endif /* LWIP_IPV4 */
+      /* Handle IPv4 and IPv6: all or exact match */
+      if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
+        return 1;
+      }
+  }
+
+  return 0;
+}
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and hands over the pbuf to the pcbs
+ * recv function. If no pcb is found or the datagram is incorrect, the
+ * pbuf is freed.
+ *
+ * @param p pbuf to be demultiplexed to a UDP PCB (p->payload pointing to the UDP header)
+ * @param inp network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb, *prev;
+  struct udp_pcb *uncon_pcb;
+  u16_t src, dest;
+  u8_t broadcast;
+  u8_t for_us = 0;
+
+  LWIP_UNUSED_ARG(inp);
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
+  LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
+
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  /* Check minimum length (UDP header) */
+  if (p->len < UDP_HLEN) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    MIB2_STATS_INC(mib2.udpinerrors);
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)p->payload;
+
+  /* is broadcast packet ? */
+  broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  /* convert src and dest ports to host byte order */
+  src = lwip_ntohs(udphdr->src);
+  dest = lwip_ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG, ("udp ("));
+  ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
+  LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
+  ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
+  LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
+
+  pcb = NULL;
+  prev = NULL;
+  uncon_pcb = NULL;
+  /* Iterate through the UDP pcb list for a matching pcb.
+   * 'Perfect match' pcbs (connected to the remote port & ip address) are
+   * preferred. If no perfect match is found, the first unconnected pcb that
+   * matches the local port and ip address gets the datagram. */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+    /* print the PCB local and remote address */
+    LWIP_DEBUGF(UDP_DEBUG, ("pcb ("));
+    ip_addr_debug_print_val(UDP_DEBUG, pcb->local_ip);
+    LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
+    ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
+    LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
+
+    /* compare PCB local addr+port to UDP destination addr+port */
+    if ((pcb->local_port == dest) &&
+        (udp_input_local_match(pcb, inp, broadcast) != 0)) {
+      if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
+        if (uncon_pcb == NULL) {
+          /* the first unconnected matching PCB */
+          uncon_pcb = pcb;
+#if LWIP_IPV4
+        } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
+          /* global broadcast address (only valid for IPv4; match was checked before) */
+          if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
+            /* uncon_pcb does not match the input netif, check this pcb */
+            if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
+              /* better match */
+              uncon_pcb = pcb;
+            }
+          }
+#endif /* LWIP_IPV4 */
+        }
+#if SO_REUSE
+        else if (!ip_addr_isany(&pcb->local_ip)) {
+          /* prefer specific IPs over catch-all */
+          uncon_pcb = pcb;
+        }
+#endif /* SO_REUSE */
+      }
+
+      /* compare PCB remote addr+port to UDP source addr+port */
+      if ((pcb->remote_port == src) &&
+          (ip_addr_isany_val(pcb->remote_ip) ||
+           ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
+        /* the first fully matching PCB */
+        if (prev != NULL) {
+          /* move the pcb to the front of udp_pcbs so that is
+             found faster next time */
+          prev->next = pcb->next;
+          pcb->next = udp_pcbs;
+          udp_pcbs = pcb;
+        } else {
+          UDP_STATS_INC(udp.cachehit);
+        }
+        break;
+      }
+    }
+
+    prev = pcb;
+  }
+  /* no fully matching pcb found? then look for an unconnected pcb */
+  if (pcb == NULL) {
+    pcb = uncon_pcb;
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL) {
+    for_us = 1;
+  } else {
+#if LWIP_IPV6
+    if (ip_current_is_v6()) {
+      for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
+    }
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4
+    if (!ip_current_is_v6()) {
+      for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
+    }
+#endif /* LWIP_IPV4 */
+  }
+
+  if (for_us) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n"));
+#if CHECKSUM_CHECK_UDP
+    IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_UDP) {
+#if LWIP_UDPLITE
+      if (ip_current_header_proto() == IP_PROTO_UDPLITE) {
+        /* Do the UDP Lite checksum */
+        u16_t chklen = lwip_ntohs(udphdr->len);
+        if (chklen < sizeof(struct udp_hdr)) {
+          if (chklen == 0) {
+            /* For UDP-Lite, checksum length of 0 means checksum
+               over the complete packet (See RFC 3828 chap. 3.1) */
+            chklen = p->tot_len;
+          } else {
+            /* At least the UDP-Lite header must be covered by the
+               checksum! (Again, see RFC 3828 chap. 3.1) */
+            goto chkerr;
+          }
+        }
+        if (ip_chksum_pseudo_partial(p, IP_PROTO_UDPLITE,
+                                     p->tot_len, chklen,
+                                     ip_current_src_addr(), ip_current_dest_addr()) != 0) {
+          goto chkerr;
+        }
+      } else
+#endif /* LWIP_UDPLITE */
+      {
+        if (udphdr->chksum != 0) {
+          if (ip_chksum_pseudo(p, IP_PROTO_UDP, p->tot_len,
+                               ip_current_src_addr(),
+                               ip_current_dest_addr()) != 0) {
+            goto chkerr;
+          }
+        }
+      }
+    }
+#endif /* CHECKSUM_CHECK_UDP */
+    if (pbuf_remove_header(p, UDP_HLEN)) {
+      /* Can we cope with this failing? Just assert for now */
+      LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+      UDP_STATS_INC(udp.drop);
+      MIB2_STATS_INC(mib2.udpinerrors);
+      pbuf_free(p);
+      goto end;
+    }
+
+    if (pcb != NULL) {
+      MIB2_STATS_INC(mib2.udpindatagrams);
+#if SO_REUSE && SO_REUSE_RXTOALL
+      if (ip_get_option(pcb, SOF_REUSEADDR) &&
+          (broadcast || ip_addr_ismulticast(ip_current_dest_addr()))) {
+        /* pass broadcast- or multicast packets to all multicast pcbs
+           if SOF_REUSEADDR is set on the first match */
+        struct udp_pcb *mpcb;
+        for (mpcb = udp_pcbs; mpcb != NULL; mpcb = mpcb->next) {
+          if (mpcb != pcb) {
+            /* compare PCB local addr+port to UDP destination addr+port */
+            if ((mpcb->local_port == dest) &&
+                (udp_input_local_match(mpcb, inp, broadcast) != 0)) {
+              /* pass a copy of the packet to all local matches */
+              if (mpcb->recv != NULL) {
+                struct pbuf *q;
+                q = pbuf_clone(PBUF_RAW, PBUF_POOL, p);
+                if (q != NULL) {
+                  mpcb->recv(mpcb->recv_arg, mpcb, q, ip_current_src_addr(), src);
+                }
+              }
+            }
+          }
+        }
+      }
+#endif /* SO_REUSE && SO_REUSE_RXTOALL */
+      /* callback */
+      if (pcb->recv != NULL) {
+        /* now the recv function is responsible for freeing p */
+        pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
+      } else {
+        /* no recv function registered? then we have to free the pbuf! */
+        pbuf_free(p);
+        goto end;
+      }
+    } else {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n"));
+
+#if LWIP_ICMP || LWIP_ICMP6
+      /* No match was found, send ICMP destination port unreachable unless
+         destination address was broadcast/multicast. */
+      if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
+        /* move payload pointer back to ip header */
+        pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
+        icmp_port_unreach(ip_current_is_v6(), p);
+      }
+#endif /* LWIP_ICMP || LWIP_ICMP6 */
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+      MIB2_STATS_INC(mib2.udpnoports);
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+end:
+  PERF_STOP("udp_input");
+  return;
+#if CHECKSUM_CHECK_UDP
+chkerr:
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+              ("udp_input: UDP (or UDP Lite) datagram discarded due to failing checksum\n"));
+  UDP_STATS_INC(udp.chkerr);
+  UDP_STATS_INC(udp.drop);
+  MIB2_STATS_INC(mib2.udpinerrors);
+  pbuf_free(p);
+  PERF_STOP("udp_input");
+#endif /* CHECKSUM_CHECK_UDP */
+}
+
+/**
+ * @ingroup udp_raw
+ * Sends the pbuf p using UDP. The pbuf is not deallocated.
+ *
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ *
+ * The datagram will be sent to the current remote_ip & remote_port
+ * stored in pcb. If the pcb is not bound to a port, it will
+ * automatically be bound to a random port.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occurred.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ * - ERR_VAL. No PCB or PCB is dual-stack
+ * - More errors could be returned by lower protocol layers.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  LWIP_ERROR("udp_send: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_send: invalid pbuf", p != NULL, return ERR_ARG);
+
+  if (IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) {
+    return ERR_VAL;
+  }
+
+  /* send to the packet using remote ip and port stored in the pcb */
+  return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port);
+}
+
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+/** @ingroup udp_raw
+ * Same as udp_send() but with checksum
+ */
+err_t
+udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                u8_t have_chksum, u16_t chksum)
+{
+  LWIP_ERROR("udp_send_chksum: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_send_chksum: invalid pbuf", p != NULL, return ERR_ARG);
+
+  if (IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) {
+    return ERR_VAL;
+  }
+
+  /* send to the packet using remote ip and port stored in the pcb */
+  return udp_sendto_chksum(pcb, p, &pcb->remote_ip, pcb->remote_port,
+                           have_chksum, chksum);
+}
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+
+/**
+ * @ingroup udp_raw
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ *
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+           const ip_addr_t *dst_ip, u16_t dst_port)
+{
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+  return udp_sendto_chksum(pcb, p, dst_ip, dst_port, 0, 0);
+}
+
+/** @ingroup udp_raw
+ * Same as udp_sendto(), but with checksum */
+err_t
+udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip,
+                  u16_t dst_port, u8_t have_chksum, u16_t chksum)
+{
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+  struct netif *netif;
+
+  LWIP_ERROR("udp_sendto: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto: invalid pbuf", p != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
+
+  if (!IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) {
+    return ERR_VAL;
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n"));
+
+  if (pcb->netif_idx != NETIF_NO_INDEX) {
+    netif = netif_get_by_index(pcb->netif_idx);
+  } else {
+#if LWIP_MULTICAST_TX_OPTIONS
+    netif = NULL;
+    if (ip_addr_ismulticast(dst_ip)) {
+      /* For IPv6, the interface to use for packets with a multicast destination
+       * is specified using an interface index. The same approach may be used for
+       * IPv4 as well, in which case it overrides the IPv4 multicast override
+       * address below. Here we have to look up the netif by going through the
+       * list, but by doing so we skip a route lookup. If the interface index has
+       * gone stale, we fall through and do the regular route lookup after all. */
+      if (pcb->mcast_ifindex != NETIF_NO_INDEX) {
+        netif = netif_get_by_index(pcb->mcast_ifindex);
+      }
+#if LWIP_IPV4
+      else
+#if LWIP_IPV6
+        if (IP_IS_V4(dst_ip))
+#endif /* LWIP_IPV6 */
+        {
+          /* IPv4 does not use source-based routing by default, so we use an
+             administratively selected interface for multicast by default.
+             However, this can be overridden by setting an interface address
+             in pcb->mcast_ip4 that is used for routing. If this routing lookup
+             fails, we try regular routing as though no override was set. */
+          if (!ip4_addr_isany_val(pcb->mcast_ip4) &&
+              !ip4_addr_cmp(&pcb->mcast_ip4, IP4_ADDR_BROADCAST)) {
+            netif = ip4_route_src(ip_2_ip4(&pcb->local_ip), &pcb->mcast_ip4);
+          }
+        }
+#endif /* LWIP_IPV4 */
+    }
+
+    if (netif == NULL)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+    {
+      /* find the outgoing network interface for this packet */
+      netif = ip_route(&pcb->local_ip, dst_ip);
+    }
+  }
+
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to "));
+    ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, dst_ip);
+    LWIP_DEBUGF(UDP_DEBUG, ("\n"));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+  return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum);
+#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+  return udp_sendto_if(pcb, p, dst_ip, dst_port, netif);
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+}
+
+/**
+ * @ingroup udp_raw
+ * Send data to a specified address using UDP.
+ * The netif used for sending can be specified.
+ *
+ * This function exists mainly for DHCP, to be able to send UDP packets
+ * on a netif that is still down.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param p chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ * @param netif the netif used for sending.
+ *
+ * dst_ip & dst_port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code (@see udp_send for possible error codes)
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
+              const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif)
+{
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+  return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0);
+}
+
+/** Same as udp_sendto_if(), but with checksum */
+err_t
+udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip,
+                     u16_t dst_port, struct netif *netif, u8_t have_chksum,
+                     u16_t chksum)
+{
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+  const ip_addr_t *src_ip;
+
+  LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG);
+
+  if (!IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) {
+    return ERR_VAL;
+  }
+
+  /* PCB local address is IP_ANY_ADDR or multicast? */
+#if LWIP_IPV6
+  if (IP_IS_V6(dst_ip)) {
+    if (ip6_addr_isany(ip_2_ip6(&pcb->local_ip)) ||
+        ip6_addr_ismulticast(ip_2_ip6(&pcb->local_ip))) {
+      src_ip = ip6_select_source_address(netif, ip_2_ip6(dst_ip));
+      if (src_ip == NULL) {
+        /* No suitable source address was found. */
+        return ERR_RTE;
+      }
+    } else {
+      /* use UDP PCB local IPv6 address as source address, if still valid. */
+      if (netif_get_ip6_addr_match(netif, ip_2_ip6(&pcb->local_ip)) < 0) {
+        /* Address isn't valid anymore. */
+        return ERR_RTE;
+      }
+      src_ip = &pcb->local_ip;
+    }
+  }
+#endif /* LWIP_IPV6 */
+#if LWIP_IPV4 && LWIP_IPV6
+  else
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#if LWIP_IPV4
+    if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
+        ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) {
+      /* if the local_ip is any or multicast
+       * use the outgoing network interface IP address as source address */
+      src_ip = netif_ip_addr4(netif);
+    } else {
+      /* check if UDP PCB local IP address is correct
+       * this could be an old address if netif->ip_addr has changed */
+      if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) {
+        /* local_ip doesn't match, drop the packet */
+        return ERR_RTE;
+      }
+      /* use UDP PCB local IP address as source address */
+      src_ip = &pcb->local_ip;
+    }
+#endif /* LWIP_IPV4 */
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+  return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip);
+#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+  return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip);
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+}
+
+/** @ingroup udp_raw
+ * Same as @ref udp_sendto_if, but with source address */
+err_t
+udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
+                  const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip)
+{
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+  return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0, src_ip);
+}
+
+/** Same as udp_sendto_if_src(), but with checksum */
+err_t
+udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip,
+                         u16_t dst_port, struct netif *netif, u8_t have_chksum,
+                         u16_t chksum, const ip_addr_t *src_ip)
+{
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+  struct udp_hdr *udphdr;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+  u8_t ip_proto;
+  u8_t ttl;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG);
+
+  if (!IP_ADDR_PCB_VERSION_MATCH(pcb, src_ip) ||
+      !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) {
+    return ERR_VAL;
+  }
+
+#if LWIP_IPV4 && IP_SOF_BROADCAST
+  /* broadcast filter? */
+  if (!ip_get_option(pcb, SOF_BROADCAST) &&
+#if LWIP_IPV6
+      IP_IS_V4(dst_ip) &&
+#endif /* LWIP_IPV6 */
+      ip_addr_isbroadcast(dst_ip, netif)) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
+                ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb));
+    return ERR_VAL;
+  }
+#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+
+  /* packet too large to add a UDP header without causing an overflow? */
+  if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) {
+    return ERR_MEM;
+  }
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_add_header(p, UDP_HLEN)) {
+    /* allocate header in a separate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    if (p->tot_len != 0) {
+      /* chain header q in front of given pbuf p (only if p contains data) */
+      pbuf_chain(q, p);
+    }
+    /* first pbuf q points to header pbuf */
+    LWIP_DEBUGF(UDP_DEBUG,
+                ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  } else {
+    /* adding space for header within p succeeded */
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
+              (q->len >= sizeof(struct udp_hdr)));
+  /* q now represents the packet to be sent */
+  udphdr = (struct udp_hdr *)q->payload;
+  udphdr->src = lwip_htons(pcb->local_port);
+  udphdr->dest = lwip_htons(dst_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000;
+
+  /* Multicast Loop? */
+#if LWIP_MULTICAST_TX_OPTIONS
+  if (((pcb->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) && ip_addr_ismulticast(dst_ip)) {
+    q->flags |= PBUF_FLAG_MCASTLOOP;
+  }
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
+
+#if LWIP_UDPLITE
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    u16_t chklen, chklen_hdr;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    chklen_hdr = chklen = pcb->chksum_len_tx;
+    if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) {
+      if (chklen != 0) {
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen));
+      }
+      /* For UDP-Lite, checksum length of 0 means checksum
+         over the complete packet. (See RFC 3828 chap. 3.1)
+         At least the UDP-Lite header must be covered by the
+         checksum, therefore, if chksum_len has an illegal
+         value, we generate the checksum over the complete
+         packet to be safe. */
+      chklen_hdr = 0;
+      chklen = q->tot_len;
+    }
+    udphdr->len = lwip_htons(chklen_hdr);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_UDP) {
+#if LWIP_CHECKSUM_ON_COPY
+      if (have_chksum) {
+        chklen = UDP_HLEN;
+      }
+#endif /* LWIP_CHECKSUM_ON_COPY */
+      udphdr->chksum = ip_chksum_pseudo_partial(q, IP_PROTO_UDPLITE,
+                       q->tot_len, chklen, src_ip, dst_ip);
+#if LWIP_CHECKSUM_ON_COPY
+      if (have_chksum) {
+        u32_t acc;
+        acc = udphdr->chksum + (u16_t)~(chksum);
+        udphdr->chksum = FOLD_U32T(acc);
+      }
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) {
+        udphdr->chksum = 0xffff;
+      }
+    }
+#endif /* CHECKSUM_GEN_UDP */
+
+    ip_proto = IP_PROTO_UDPLITE;
+  } else
+#endif /* LWIP_UDPLITE */
+  {      /* UDP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
+    udphdr->len = lwip_htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_UDP) {
+      /* Checksum is mandatory over IPv6. */
+      if (IP_IS_V6(dst_ip) || (pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+        u16_t udpchksum;
+#if LWIP_CHECKSUM_ON_COPY
+        if (have_chksum) {
+          u32_t acc;
+          udpchksum = ip_chksum_pseudo_partial(q, IP_PROTO_UDP,
+                                               q->tot_len, UDP_HLEN, src_ip, dst_ip);
+          acc = udpchksum + (u16_t)~(chksum);
+          udpchksum = FOLD_U32T(acc);
+        } else
+#endif /* LWIP_CHECKSUM_ON_COPY */
+        {
+          udpchksum = ip_chksum_pseudo(q, IP_PROTO_UDP, q->tot_len,
+                                       src_ip, dst_ip);
+        }
+
+        /* chksum zero must become 0xffff, as zero means 'no checksum' */
+        if (udpchksum == 0x0000) {
+          udpchksum = 0xffff;
+        }
+        udphdr->chksum = udpchksum;
+      }
+    }
+#endif /* CHECKSUM_GEN_UDP */
+    ip_proto = IP_PROTO_UDP;
+  }
+
+  /* Determine TTL to use */
+#if LWIP_MULTICAST_TX_OPTIONS
+  ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl);
+#else /* LWIP_MULTICAST_TX_OPTIONS */
+  ttl = pcb->ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto));
+  /* output to IP */
+  NETIF_SET_HINTS(netif, &(pcb->netif_hints));
+  err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif);
+  NETIF_RESET_HINTS(netif);
+
+  /* @todo: must this be increased even if error occurred? */
+  MIB2_STATS_INC(mib2.udpoutdatagrams);
+
+  /* did we chain a separate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q);
+    q = NULL;
+    /* p is still referenced by the caller, and will live on */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * @ingroup udp_raw
+ * Bind an UDP PCB.
+ * 
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ANY_TYPE to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with. Use 0 to automatically bind
+ * to a random port between UDP_LOCAL_PORT_RANGE_START and
+ * UDP_LOCAL_PORT_RANGE_END.
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occurred.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  ip_addr_t zoned_ipaddr;
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+#if LWIP_IPV4
+  /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
+  if (ipaddr == NULL) {
+    ipaddr = IP4_ADDR_ANY;
+  }
+#else /* LWIP_IPV4 */
+  LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+#endif /* LWIP_IPV4 */
+
+  LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      rebind = 1;
+      break;
+    }
+  }
+
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  /* If the given IP address should have a zone but doesn't, assign one now.
+   * This is legacy support: scope-aware callers should always provide properly
+   * zoned source addresses. Do the zone selection before the address-in-use
+   * check below; as such we have to make a temporary copy of the address. */
+  if (IP_IS_V6(ipaddr) && ip6_addr_lacks_zone(ip_2_ip6(ipaddr), IP6_UNKNOWN)) {
+    ip_addr_copy(zoned_ipaddr, *ipaddr);
+    ip6_addr_select_zone(ip_2_ip6(&zoned_ipaddr), ip_2_ip6(&zoned_ipaddr));
+    ipaddr = &zoned_ipaddr;
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  /* no port specified? */
+  if (port == 0) {
+    port = udp_new_port();
+    if (port == 0) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  } else {
+    for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+      if (pcb != ipcb) {
+        /* By default, we don't allow to bind to a port that any other udp
+           PCB is already bound to, unless *all* PCBs with that port have tha
+           REUSEADDR flag set. */
+#if SO_REUSE
+        if (!ip_get_option(pcb, SOF_REUSEADDR) ||
+            !ip_get_option(ipcb, SOF_REUSEADDR))
+#endif /* SO_REUSE */
+        {
+          /* port matches that of PCB in list and REUSEADDR not set -> reject */
+          if ((ipcb->local_port == port) &&
+              /* IP address matches or any IP used? */
+              (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
+              ip_addr_isany(&ipcb->local_ip))) {
+            /* other PCB already binds to this local IP and port */
+            LWIP_DEBUGF(UDP_DEBUG,
+                        ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+            return ERR_USE;
+          }
+        }
+      }
+    }
+  }
+
+  ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
+
+  pcb->local_port = port;
+  mib2_udp_bind(pcb);
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to "));
+  ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port));
+  return ERR_OK;
+}
+
+/**
+ * @ingroup udp_raw
+ * Bind an UDP PCB to a specific netif.
+ * After calling this function, all packets received via this PCB
+ * are guaranteed to have come in via the specified netif, and all
+ * outgoing packets will go out via the specified netif.
+ *
+ * @param pcb UDP PCB to be bound.
+ * @param netif netif to bind udp pcb to. Can be NULL.
+ *
+ * @see udp_disconnect()
+ */
+void
+udp_bind_netif(struct udp_pcb *pcb, const struct netif *netif)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (netif != NULL) {
+    pcb->netif_idx = netif_get_index(netif);
+  } else {
+    pcb->netif_idx = NETIF_NO_INDEX;
+  }
+}
+
+/**
+ * @ingroup udp_raw
+ * Sets the remote end of the pcb. This function does not generate any
+ * network traffic, but only sets the remote address of the pcb.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * ipaddr & port are expected to be in the same byte order as in the pcb.
+ *
+ * The udp pcb is bound to a random local port if not already bound.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
+  LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      return err;
+    }
+  }
+
+  ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
+#if LWIP_IPV6 && LWIP_IPV6_SCOPES
+  /* If the given IP address should have a zone but doesn't, assign one now,
+   * using the bound address to make a more informed decision when possible. */
+  if (IP_IS_V6(&pcb->remote_ip) &&
+      ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
+    ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
+
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_connect: connected to "));
+  ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
+                          pcb->remote_ip);
+  LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+/**
+ * @ingroup udp_raw
+ * Remove the remote end of the pcb. This function does not generate
+ * any network traffic, but only removes the remote address of the pcb.
+ *
+ * @param pcb the udp pcb to disconnect.
+ */
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_disconnect: invalid pcb", pcb != NULL, return);
+
+  /* reset remote address association */
+#if LWIP_IPV4 && LWIP_IPV6
+  if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) {
+    ip_addr_copy(pcb->remote_ip, *IP_ANY_TYPE);
+  } else {
+#endif
+    ip_addr_set_any(IP_IS_V6_VAL(pcb->remote_ip), &pcb->remote_ip);
+#if LWIP_IPV4 && LWIP_IPV6
+  }
+#endif
+  pcb->remote_port = 0;
+  pcb->netif_idx = NETIF_NO_INDEX;
+  /* mark PCB as unconnected */
+  udp_clear_flags(pcb, UDP_FLAGS_CONNECTED);
+}
+
+/**
+ * @ingroup udp_raw
+ * Set a receive callback for a UDP PCB.
+ * This callback will be called when receiving a datagram for the pcb.
+ *
+ * @param pcb the pcb for which to set the recv callback
+ * @param recv function pointer of the callback function
+ * @param recv_arg additional argument to pass to the callback function
+ */
+void
+udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return);
+
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * @ingroup udp_raw
+ * Removes and deallocates the pcb.  
+ * 
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return);
+
+  mib2_udp_unbind(pcb);
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+    /* pcb not 1st in list */
+  } else {
+    for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+      /* find pcb in udp_pcbs list */
+      if (pcb2->next != NULL && pcb2->next == pcb) {
+        /* remove pcb from list */
+        pcb2->next = pcb->next;
+        break;
+      }
+    }
+  }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+
+/**
+ * @ingroup udp_raw
+ * Creates a new UDP pcb which can be used for UDP communication. The
+ * pcb is not active until it has either been bound to a local address
+ * or connected to a remote address.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void)
+{
+  struct udp_pcb *pcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
+     * which means checksum is generated over the whole datagram per default
+     * (recommended as default by RFC 3828). */
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+#if LWIP_MULTICAST_TX_OPTIONS
+    udp_set_multicast_ttl(pcb, UDP_TTL);
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+  }
+  return pcb;
+}
+
+/**
+ * @ingroup udp_raw
+ * Create a UDP PCB for specific IP type.
+ * The pcb is not active until it has either been bound to a local address
+ * or connected to a remote address.
+ * 
+ * @param type IP address type, see @ref lwip_ip_addr_type definitions.
+ * If you want to listen to IPv4 and IPv6 (dual-stack) packets,
+ * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE.
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new_ip_type(u8_t type)
+{
+  struct udp_pcb *pcb;
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb = udp_new();
+#if LWIP_IPV4 && LWIP_IPV6
+  if (pcb != NULL) {
+    IP_SET_TYPE_VAL(pcb->local_ip,  type);
+    IP_SET_TYPE_VAL(pcb->remote_ip, type);
+  }
+#else
+  LWIP_UNUSED_ARG(type);
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  return pcb;
+}
+
+/** This function is called from netif.c when address is changed
+ *
+ * @param old_addr IP address of the netif before change
+ * @param new_addr IP address of the netif after change
+ */
+void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
+{
+  struct udp_pcb *upcb;
+
+  if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
+    for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
+        /* The PCB is bound to the old ipaddr and
+         * is set to bound to the new one instead */
+        ip_addr_copy(upcb->local_ip, *new_addr);
+      }
+    }
+  }
+}
+
+#if UDP_DEBUG
+/**
+ * Print UDP header information for debug purposes.
+ *
+ * @param udphdr pointer to the udp header in memory.
+ */
+void
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
+                          lwip_ntohs(udphdr->src), lwip_ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
+                          lwip_ntohs(udphdr->len), lwip_ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/arpa/inet.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/arpa/inet.h
new file mode 100644
index 000000000..0ed9baf3d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/arpa/inet.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/sockets.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/sockets.h"
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/net/if.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/net/if.h
new file mode 100644
index 000000000..6b8e63a52
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/net/if.h
@@ -0,0 +1,36 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/if_api.h.
+ */
+
+/*
+ * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. <joel.cunningham@garmin.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/if_api.h"
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/netdb.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/netdb.h
new file mode 100644
index 000000000..12d4c7f56
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/netdb.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/netdb.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/netdb.h"
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/sys/socket.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/sys/socket.h
new file mode 100644
index 000000000..0ed9baf3d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/posix/sys/socket.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix wrapper for lwip/sockets.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/sockets.h"
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/stdc/errno.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/stdc/errno.h
new file mode 100644
index 000000000..98a9aec99
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/compat/stdc/errno.h
@@ -0,0 +1,33 @@
+/**
+ * @file
+ * This file is a posix/stdc wrapper for lwip/errno.h.
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/errno.h"
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp.h
new file mode 100644
index 000000000..97abc54d0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp.h
@@ -0,0 +1,201 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ *
+ * This file contains the generic API.
+ * For more details see @ref altcp_api.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_H
+#define LWIP_HDR_ALTCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpbase.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_pcb;
+struct altcp_functions;
+
+typedef err_t (*altcp_accept_fn)(void *arg, struct altcp_pcb *new_conn, err_t err);
+typedef err_t (*altcp_connected_fn)(void *arg, struct altcp_pcb *conn, err_t err);
+typedef err_t (*altcp_recv_fn)(void *arg, struct altcp_pcb *conn, struct pbuf *p, err_t err);
+typedef err_t (*altcp_sent_fn)(void *arg, struct altcp_pcb *conn, u16_t len);
+typedef err_t (*altcp_poll_fn)(void *arg, struct altcp_pcb *conn);
+typedef void  (*altcp_err_fn)(void *arg, err_t err);
+
+typedef struct altcp_pcb* (*altcp_new_fn)(void *arg, u8_t ip_type);
+
+struct altcp_pcb {
+  const struct altcp_functions *fns;
+  struct altcp_pcb *inner_conn;
+  void *arg;
+  void *state;
+  /* application callbacks */
+  altcp_accept_fn     accept;
+  altcp_connected_fn  connected;
+  altcp_recv_fn       recv;
+  altcp_sent_fn       sent;
+  altcp_poll_fn       poll;
+  altcp_err_fn        err;
+  u8_t pollinterval;
+};
+
+/** @ingroup altcp */
+typedef struct altcp_allocator_s {
+  /** Allocator function */
+  altcp_new_fn  alloc;
+  /** Argument to allocator function */
+  void         *arg;
+} altcp_allocator_t;
+
+struct altcp_pcb *altcp_new(altcp_allocator_t *allocator);
+struct altcp_pcb *altcp_new_ip6(altcp_allocator_t *allocator);
+struct altcp_pcb *altcp_new_ip_type(altcp_allocator_t *allocator, u8_t ip_type);
+
+void altcp_arg(struct altcp_pcb *conn, void *arg);
+void altcp_accept(struct altcp_pcb *conn, altcp_accept_fn accept);
+void altcp_recv(struct altcp_pcb *conn, altcp_recv_fn recv);
+void altcp_sent(struct altcp_pcb *conn, altcp_sent_fn sent);
+void altcp_poll(struct altcp_pcb *conn, altcp_poll_fn poll, u8_t interval);
+void altcp_err(struct altcp_pcb *conn, altcp_err_fn err);
+
+void  altcp_recved(struct altcp_pcb *conn, u16_t len);
+err_t altcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port);
+err_t altcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected);
+
+/* return conn for source code compatibility to tcp callback API only */
+struct altcp_pcb *altcp_listen_with_backlog_and_err(struct altcp_pcb *conn, u8_t backlog, err_t *err);
+#define altcp_listen_with_backlog(conn, backlog) altcp_listen_with_backlog_and_err(conn, backlog, NULL)
+/** @ingroup altcp */
+#define altcp_listen(conn) altcp_listen_with_backlog_and_err(conn, TCP_DEFAULT_LISTEN_BACKLOG, NULL)
+
+void altcp_abort(struct altcp_pcb *conn);
+err_t altcp_close(struct altcp_pcb *conn);
+err_t altcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx);
+
+err_t altcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags);
+err_t altcp_output(struct altcp_pcb *conn);
+
+u16_t altcp_mss(struct altcp_pcb *conn);
+u16_t altcp_sndbuf(struct altcp_pcb *conn);
+u16_t altcp_sndqueuelen(struct altcp_pcb *conn);
+void  altcp_nagle_disable(struct altcp_pcb *conn);
+void  altcp_nagle_enable(struct altcp_pcb *conn);
+int   altcp_nagle_disabled(struct altcp_pcb *conn);
+
+void  altcp_setprio(struct altcp_pcb *conn, u8_t prio);
+
+err_t altcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port);
+ip_addr_t *altcp_get_ip(struct altcp_pcb *conn, int local);
+u16_t altcp_get_port(struct altcp_pcb *conn, int local);
+
+#ifdef LWIP_DEBUG
+enum tcp_state altcp_dbg_get_tcp_state(struct altcp_pcb *conn);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#else /* LWIP_ALTCP */
+
+/* ALTCP disabled, define everything to link against tcp callback API (e.g. to get a small non-ssl httpd) */
+
+#include "lwip/tcp.h"
+
+#define altcp_accept_fn tcp_accept_fn
+#define altcp_connected_fn tcp_connected_fn
+#define altcp_recv_fn tcp_recv_fn
+#define altcp_sent_fn tcp_sent_fn
+#define altcp_poll_fn tcp_poll_fn
+#define altcp_err_fn tcp_err_fn
+
+#define altcp_pcb tcp_pcb
+#define altcp_tcp_new_ip_type tcp_new_ip_type
+#define altcp_tcp_new tcp_new
+#define altcp_tcp_new_ip6 tcp_new_ip6
+
+#define altcp_new(allocator) tcp_new()
+#define altcp_new_ip6(allocator) tcp_new_ip6()
+#define altcp_new_ip_type(allocator, ip_type) tcp_new_ip_type(ip_type)
+
+#define altcp_arg tcp_arg
+#define altcp_accept tcp_accept
+#define altcp_recv tcp_recv
+#define altcp_sent tcp_sent
+#define altcp_poll tcp_poll
+#define altcp_err tcp_err
+
+#define altcp_recved tcp_recved
+#define altcp_bind tcp_bind
+#define altcp_connect tcp_connect
+
+#define altcp_listen_with_backlog_and_err tcp_listen_with_backlog_and_err
+#define altcp_listen_with_backlog tcp_listen_with_backlog
+#define altcp_listen tcp_listen
+
+#define altcp_abort tcp_abort
+#define altcp_close tcp_close
+#define altcp_shutdown tcp_shutdown
+
+#define altcp_write tcp_write
+#define altcp_output tcp_output
+
+#define altcp_mss tcp_mss
+#define altcp_sndbuf tcp_sndbuf
+#define altcp_sndqueuelen tcp_sndqueuelen
+#define altcp_nagle_disable tcp_nagle_disable
+#define altcp_nagle_enable tcp_nagle_enable
+#define altcp_nagle_disabled tcp_nagle_disabled
+#define altcp_setprio tcp_setprio
+
+#define altcp_get_tcp_addrinfo tcp_get_tcp_addrinfo
+#define altcp_get_ip(pcb, local) ((local) ? (&(pcb)->local_ip) : (&(pcb)->remote_ip))
+
+#ifdef LWIP_DEBUG
+#define altcp_dbg_get_tcp_state tcp_dbg_get_tcp_state
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp_tcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp_tcp.h
new file mode 100644
index 000000000..dbde58468
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp_tcp.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ * This interface mimics the tcp callback API to the application while preventing
+ * direct linking (much like virtual functions).
+ * This way, an application can make use of other application layer protocols
+ * on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ *
+ * This file contains the base implementation calling into tcp.
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_TCP_H
+#define LWIP_HDR_ALTCP_TCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_pcb *altcp_tcp_new_ip_type(u8_t ip_type);
+
+#define altcp_tcp_new() altcp_tcp_new_ip_type(IPADDR_TYPE_V4)
+#define altcp_tcp_new_ip6() altcp_tcp_new_ip_type(IPADDR_TYPE_V6)
+
+struct altcp_pcb *altcp_tcp_alloc(void *arg, u8_t ip_type);
+
+struct tcp_pcb;
+struct altcp_pcb *altcp_tcp_wrap(struct tcp_pcb *tpcb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_TCP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp_tls.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp_tls.h
new file mode 100644
index 000000000..7b17c6080
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/altcp_tls.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ * Application layered TCP/TLS connection API (to be used from TCPIP thread)
+ *
+ * @defgroup altcp_tls TLS layer
+ * @ingroup altcp
+ * This file contains function prototypes for a TLS layer.
+ * A port to ARM mbedtls is provided in the apps/ tree
+ * (LWIP_ALTCP_TLS_MBEDTLS option).
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_TLS_H
+#define LWIP_HDR_ALTCP_TLS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#if LWIP_ALTCP_TLS
+
+#include "lwip/altcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup altcp_tls
+ * ALTCP_TLS configuration handle, content depends on port (e.g. mbedtls)
+ */
+struct altcp_tls_config;
+
+/** @ingroup altcp_tls
+ * Create an ALTCP_TLS server configuration handle
+ */
+struct altcp_tls_config *altcp_tls_create_config_server_privkey_cert(const u8_t *privkey, size_t privkey_len,
+                            const u8_t *privkey_pass, size_t privkey_pass_len,
+                            const u8_t *cert, size_t cert_len);
+
+/** @ingroup altcp_tls
+ * Create an ALTCP_TLS client configuration handle
+ */
+struct altcp_tls_config *altcp_tls_create_config_client(const u8_t *cert, size_t cert_len);
+
+/** @ingroup altcp_tls
+ * Create an ALTCP_TLS client configuration handle with two-way server/client authentication
+ */
+struct altcp_tls_config *altcp_tls_create_config_client_2wayauth(const u8_t *ca, size_t ca_len, const u8_t *privkey, size_t privkey_len,
+                            const u8_t *privkey_pass, size_t privkey_pass_len,
+                            const u8_t *cert, size_t cert_len);
+
+/** @ingroup altcp_tls
+ * Free an ALTCP_TLS configuration handle
+ */
+void altcp_tls_free_config(struct altcp_tls_config *conf);
+
+/** @ingroup altcp_tls
+ * Create new ALTCP_TLS layer wrapping an existing pcb as inner connection (e.g. TLS over TCP)
+ */
+struct altcp_pcb *altcp_tls_wrap(struct altcp_tls_config *config, struct altcp_pcb *inner_pcb);
+
+/** @ingroup altcp_tls
+ * Create new ALTCP_TLS pcb and its inner tcp pcb
+ */
+struct altcp_pcb *altcp_tls_new(struct altcp_tls_config *config, u8_t ip_type);
+
+/** @ingroup altcp_tls
+ * Create new ALTCP_TLS layer pcb and its inner tcp pcb.
+ * Same as @ref altcp_tls_new but this allocator function fits to
+ * @ref altcp_allocator_t / @ref altcp_new.\n
+ 'arg' must contain a struct altcp_tls_config *.
+ */
+struct altcp_pcb *altcp_tls_alloc(void *arg, u8_t ip_type);
+
+/** @ingroup altcp_tls
+ * Return pointer to internal TLS context so application can tweak it.
+ * Real type depends on port (e.g. mbedtls)
+ */
+void *altcp_tls_context(struct altcp_pcb *conn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP_TLS */
+#endif /* LWIP_ALTCP */
+#endif /* LWIP_HDR_ALTCP_TLS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/api.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/api.h
new file mode 100644
index 000000000..c2afaf26d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/api.h
@@ -0,0 +1,431 @@
+/**
+ * @file
+ * netconn API (to be used from non-TCPIP threads)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_API_H
+#define LWIP_HDR_API_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include "lwip/arch.h"
+#include "lwip/netbuf.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+
+/* Flags for netconn_write (u8_t) */
+#define NETCONN_NOFLAG      0x00
+#define NETCONN_NOCOPY      0x00 /* Only for source code compatibility */
+#define NETCONN_COPY        0x01
+#define NETCONN_MORE        0x02
+#define NETCONN_DONTBLOCK   0x04
+#define NETCONN_NOAUTORCVD  0x08 /* prevent netconn_recv_data_tcp() from updating the tcp window - must be done manually via netconn_tcp_recvd() */
+#define NETCONN_NOFIN       0x10 /* upper layer already received data, leave FIN in queue until called again */
+
+/* Flags for struct netconn.flags (u8_t) */
+/** This netconn had an error, don't block on recvmbox/acceptmbox any more */
+#define NETCONN_FLAG_MBOXCLOSED               0x01
+/** Should this netconn avoid blocking? */
+#define NETCONN_FLAG_NON_BLOCKING             0x02
+/** Was the last connect action a non-blocking one? */
+#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT   0x04
+#if LWIP_NETCONN_FULLDUPLEX
+  /** The mbox of this netconn is being deallocated, don't use it anymore */
+#define NETCONN_FLAG_MBOXINVALID              0x08
+#endif /* LWIP_NETCONN_FULLDUPLEX */
+/** If a nonblocking write has been rejected before, poll_tcp needs to
+    check if the netconn is writable again */
+#define NETCONN_FLAG_CHECK_WRITESPACE         0x10
+#if LWIP_IPV6
+/** If this flag is set then only IPv6 communication is allowed on the
+    netconn. As per RFC#3493 this features defaults to OFF allowing
+    dual-stack usage by default. */
+#define NETCONN_FLAG_IPV6_V6ONLY              0x20
+#endif /* LWIP_IPV6 */
+#if LWIP_NETBUF_RECVINFO
+/** Received packet info will be recorded for this netconn */
+#define NETCONN_FLAG_PKTINFO                  0x40
+#endif /* LWIP_NETBUF_RECVINFO */
+/** A FIN has been received but not passed to the application yet */
+#define NETCONN_FIN_RX_PENDING                0x80
+
+/* Helpers to process several netconn_types by the same code */
+#define NETCONNTYPE_GROUP(t)         ((t)&0xF0)
+#define NETCONNTYPE_DATAGRAM(t)      ((t)&0xE0)
+#if LWIP_IPV6
+#define NETCONN_TYPE_IPV6            0x08
+#define NETCONNTYPE_ISIPV6(t)        (((t)&NETCONN_TYPE_IPV6) != 0)
+#define NETCONNTYPE_ISUDPLITE(t)     (((t)&0xF3) == NETCONN_UDPLITE)
+#define NETCONNTYPE_ISUDPNOCHKSUM(t) (((t)&0xF3) == NETCONN_UDPNOCHKSUM)
+#else /* LWIP_IPV6 */
+#define NETCONNTYPE_ISIPV6(t)        (0)
+#define NETCONNTYPE_ISUDPLITE(t)     ((t) == NETCONN_UDPLITE)
+#define NETCONNTYPE_ISUDPNOCHKSUM(t) ((t) == NETCONN_UDPNOCHKSUM)
+#endif /* LWIP_IPV6 */
+
+/** @ingroup netconn_common
+ * Protocol family and type of the netconn
+ */
+enum netconn_type {
+  NETCONN_INVALID     = 0,
+  /** TCP IPv4 */
+  NETCONN_TCP         = 0x10,
+#if LWIP_IPV6
+  /** TCP IPv6 */
+  NETCONN_TCP_IPV6    = NETCONN_TCP | NETCONN_TYPE_IPV6 /* 0x18 */,
+#endif /* LWIP_IPV6 */
+  /** UDP IPv4 */
+  NETCONN_UDP         = 0x20,
+  /** UDP IPv4 lite */
+  NETCONN_UDPLITE     = 0x21,
+  /** UDP IPv4 no checksum */
+  NETCONN_UDPNOCHKSUM = 0x22,
+
+#if LWIP_IPV6
+  /** UDP IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+  NETCONN_UDP_IPV6         = NETCONN_UDP | NETCONN_TYPE_IPV6 /* 0x28 */,
+  /** UDP IPv6 lite (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+  NETCONN_UDPLITE_IPV6     = NETCONN_UDPLITE | NETCONN_TYPE_IPV6 /* 0x29 */,
+  /** UDP IPv6 no checksum (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+  NETCONN_UDPNOCHKSUM_IPV6 = NETCONN_UDPNOCHKSUM | NETCONN_TYPE_IPV6 /* 0x2a */,
+#endif /* LWIP_IPV6 */
+
+  /** Raw connection IPv4 */
+  NETCONN_RAW         = 0x40
+#if LWIP_IPV6
+  /** Raw connection IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
+  , NETCONN_RAW_IPV6    = NETCONN_RAW | NETCONN_TYPE_IPV6 /* 0x48 */
+#endif /* LWIP_IPV6 */
+};
+
+/** Current state of the netconn. Non-TCP netconns are always
+ * in state NETCONN_NONE! */
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_LISTEN,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+/** Used to inform the callback function about changes
+ * 
+ * Event explanation:
+ * 
+ * In the netconn implementation, there are three ways to block a client:
+ * 
+ * - accept mbox (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); in netconn_accept())
+ * - receive mbox (sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); in netconn_recv_data())
+ * - send queue is full (sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); in lwip_netconn_do_write())
+ * 
+ * The events have to be seen as events signaling the state of these mboxes/semaphores. For non-blocking
+ * connections, you need to know in advance whether a call to a netconn function call would block or not,
+ * and these events tell you about that.
+ * 
+ * RCVPLUS events say: Safe to perform a potentially blocking call call once more. 
+ * They are counted in sockets - three RCVPLUS events for accept mbox means you are safe
+ * to call netconn_accept 3 times without being blocked.
+ * Same thing for receive mbox.
+ * 
+ * RCVMINUS events say: Your call to to a possibly blocking function is "acknowledged".
+ * Socket implementation decrements the counter.
+ * 
+ * For TX, there is no need to count, its merely a flag. SENDPLUS means you may send something.
+ * SENDPLUS occurs when enough data was delivered to peer so netconn_send() can be called again.
+ * A SENDMINUS event occurs when the next call to a netconn_send() would be blocking.
+ */
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS,
+  NETCONN_EVT_ERROR
+};
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+/** Used for netconn_join_leave_group() */
+enum netconn_igmp {
+  NETCONN_JOIN,
+  NETCONN_LEAVE
+};
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+/* Used for netconn_gethostbyname_addrtype(), these should match the DNS_ADDRTYPE defines in dns.h */
+#define NETCONN_DNS_DEFAULT   NETCONN_DNS_IPV4_IPV6
+#define NETCONN_DNS_IPV4      0
+#define NETCONN_DNS_IPV6      1
+#define NETCONN_DNS_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
+#define NETCONN_DNS_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
+#endif /* LWIP_DNS */
+
+/* forward-declare some structs to avoid to include their headers */
+struct ip_pcb;
+struct tcp_pcb;
+struct udp_pcb;
+struct raw_pcb;
+struct netconn;
+struct api_msg;
+
+/** A callback prototype to inform about events for a netconn */
+typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
+
+/** A netconn descriptor */
+struct netconn {
+  /** type of the netconn (TCP, UDP or RAW) */
+  enum netconn_type type;
+  /** current state of the netconn */
+  enum netconn_state state;
+  /** the lwIP internal protocol control block */
+  union {
+    struct ip_pcb  *ip;
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  /** the last asynchronous unreported error this netconn had */
+  err_t pending_err;
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  /** sem that is used to synchronously execute functions in the core context */
+  sys_sem_t op_completed;
+#endif
+  /** mbox where received packets are stored until they are fetched
+      by the netconn application thread (can grow quite big) */
+  sys_mbox_t recvmbox;
+#if LWIP_TCP
+  /** mbox where new connections are stored until processed
+      by the application thread */
+  sys_mbox_t acceptmbox;
+#endif /* LWIP_TCP */
+#if LWIP_NETCONN_FULLDUPLEX
+  /** number of threads waiting on an mbox. This is required to unblock
+      all threads when closing while threads are waiting. */
+  int mbox_threads_waiting;
+#endif
+  /** only used for socket layer */
+#if LWIP_SOCKET
+  int socket;
+#endif /* LWIP_SOCKET */
+#if LWIP_SO_SNDTIMEO
+  /** timeout to wait for sending data (which means enqueueing data for sending
+      in internal buffers) in milliseconds */
+  s32_t send_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVTIMEO
+  /** timeout in milliseconds to wait for new data to be received
+      (or connections to arrive for listening netconns) */
+  u32_t recv_timeout;
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+  /** maximum amount of bytes queued in recvmbox
+      not used for TCP: adjust TCP_WND instead! */
+  int recv_bufsize;
+  /** number of bytes currently in recvmbox to be received,
+      tested against recv_bufsize to limit bytes on recvmbox
+      for UDP and RAW, used for FIONREAD */
+  int recv_avail;
+#endif /* LWIP_SO_RCVBUF */
+#if LWIP_SO_LINGER
+   /** values <0 mean linger is disabled, values > 0 are seconds to linger */
+  s16_t linger;
+#endif /* LWIP_SO_LINGER */
+  /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */
+  u8_t flags;
+#if LWIP_TCP
+  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
+      this temporarily stores the message.
+      Also used during connect and close. */
+  struct api_msg *current_msg;
+#endif /* LWIP_TCP */
+  /** A callback function that is informed about events for this netconn */
+  netconn_callback callback;
+};
+
+/** This vector type is passed to @ref netconn_write_vectors_partly to send
+ * multiple buffers at once.
+ * ATTENTION: This type has to directly map struct iovec since one is casted
+ *            into the other!
+ */
+struct netvector {
+  /** pointer to the application buffer that contains the data to send */
+  const void *ptr;
+  /** size of the application data to send */
+  size_t len;
+};
+
+/** Register an Network connection event */
+#define API_EVENT(c,e,l) if (c->callback) {         \
+                           (*c->callback)(c, e, l); \
+                         }
+
+/* Network connection functions: */
+
+/** @ingroup netconn_common
+ * Create new netconn connection
+ * @param t @ref netconn_type */
+#define netconn_new(t)                  netconn_new_with_proto_and_callback(t, 0, NULL)
+#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
+struct netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
+                                             netconn_callback callback);
+err_t   netconn_prepare_delete(struct netconn *conn);
+err_t   netconn_delete(struct netconn *conn);
+/** Get the type of a netconn (as enum netconn_type). */
+#define netconn_type(conn) (conn->type)
+
+err_t   netconn_getaddr(struct netconn *conn, ip_addr_t *addr,
+                        u16_t *port, u8_t local);
+/** @ingroup netconn_common */
+#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
+/** @ingroup netconn_common */
+#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
+
+err_t   netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port);
+err_t   netconn_bind_if(struct netconn *conn, u8_t if_idx);
+err_t   netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port);
+err_t   netconn_disconnect (struct netconn *conn);
+err_t   netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
+/** @ingroup netconn_tcp */
+#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
+err_t   netconn_accept(struct netconn *conn, struct netconn **new_conn);
+err_t   netconn_recv(struct netconn *conn, struct netbuf **new_buf);
+err_t   netconn_recv_udp_raw_netbuf(struct netconn *conn, struct netbuf **new_buf);
+err_t   netconn_recv_udp_raw_netbuf_flags(struct netconn *conn, struct netbuf **new_buf, u8_t apiflags);
+err_t   netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf);
+err_t   netconn_recv_tcp_pbuf_flags(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags);
+err_t   netconn_tcp_recvd(struct netconn *conn, size_t len);
+err_t   netconn_sendto(struct netconn *conn, struct netbuf *buf,
+                             const ip_addr_t *addr, u16_t port);
+err_t   netconn_send(struct netconn *conn, struct netbuf *buf);
+err_t   netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size,
+                             u8_t apiflags, size_t *bytes_written);
+err_t   netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt,
+                                     u8_t apiflags, size_t *bytes_written);
+/** @ingroup netconn_tcp */
+#define netconn_write(conn, dataptr, size, apiflags) \
+          netconn_write_partly(conn, dataptr, size, apiflags, NULL)
+err_t   netconn_close(struct netconn *conn);
+err_t   netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx);
+
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+err_t   netconn_join_leave_group(struct netconn *conn, const ip_addr_t *multiaddr,
+                             const ip_addr_t *netif_addr, enum netconn_igmp join_or_leave);
+err_t   netconn_join_leave_group_netif(struct netconn *conn, const ip_addr_t *multiaddr,
+                             u8_t if_idx, enum netconn_igmp join_or_leave);
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+#if LWIP_DNS
+#if LWIP_IPV4 && LWIP_IPV6
+err_t   netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype);
+#define netconn_gethostbyname(name, addr) netconn_gethostbyname_addrtype(name, addr, NETCONN_DNS_DEFAULT)
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+err_t   netconn_gethostbyname(const char *name, ip_addr_t *addr);
+#define netconn_gethostbyname_addrtype(name, addr, dns_addrtype) netconn_gethostbyname(name, addr)
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+#endif /* LWIP_DNS */
+
+err_t   netconn_err(struct netconn *conn);
+#define netconn_recv_bufsize(conn)      ((conn)->recv_bufsize)
+
+#define netconn_set_flags(conn, set_flags)     do { (conn)->flags = (u8_t)((conn)->flags |  (set_flags)); } while(0)
+#define netconn_clear_flags(conn, clr_flags)   do { (conn)->flags = (u8_t)((conn)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define netconn_is_flag_set(conn, flag)        (((conn)->flags & (flag)) != 0)
+
+/** Set the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_set_nonblocking(conn, val)  do { if(val) { \
+  netconn_set_flags(conn, NETCONN_FLAG_NON_BLOCKING); \
+} else { \
+  netconn_clear_flags(conn, NETCONN_FLAG_NON_BLOCKING); }} while(0)
+/** Get the blocking status of netconn calls (@todo: write/send is missing) */
+#define netconn_is_nonblocking(conn)        (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0)
+
+#if LWIP_IPV6
+/** @ingroup netconn_common
+ * TCP: Set the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY)
+ */
+#define netconn_set_ipv6only(conn, val)  do { if(val) { \
+  netconn_set_flags(conn, NETCONN_FLAG_IPV6_V6ONLY); \
+} else { \
+  netconn_clear_flags(conn, NETCONN_FLAG_IPV6_V6ONLY); }} while(0)
+/** @ingroup netconn_common
+ * TCP: Get the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY)
+ */
+#define netconn_get_ipv6only(conn)        (((conn)->flags & NETCONN_FLAG_IPV6_V6ONLY) != 0)
+#endif /* LWIP_IPV6 */
+
+#if LWIP_SO_SNDTIMEO
+/** Set the send timeout in milliseconds */
+#define netconn_set_sendtimeout(conn, timeout)      ((conn)->send_timeout = (timeout))
+/** Get the send timeout in milliseconds */
+#define netconn_get_sendtimeout(conn)               ((conn)->send_timeout)
+#endif /* LWIP_SO_SNDTIMEO */
+#if LWIP_SO_RCVTIMEO
+/** Set the receive timeout in milliseconds */
+#define netconn_set_recvtimeout(conn, timeout)      ((conn)->recv_timeout = (timeout))
+/** Get the receive timeout in milliseconds */
+#define netconn_get_recvtimeout(conn)               ((conn)->recv_timeout)
+#endif /* LWIP_SO_RCVTIMEO */
+#if LWIP_SO_RCVBUF
+/** Set the receive buffer in bytes */
+#define netconn_set_recvbufsize(conn, recvbufsize)  ((conn)->recv_bufsize = (recvbufsize))
+/** Get the receive buffer in bytes */
+#define netconn_get_recvbufsize(conn)               ((conn)->recv_bufsize)
+#endif /* LWIP_SO_RCVBUF*/
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+void netconn_thread_init(void);
+void netconn_thread_cleanup(void);
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define netconn_thread_init()
+#define netconn_thread_cleanup()
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_API_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/arch.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/arch.h
new file mode 100644
index 000000000..a599f688a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/arch.h
@@ -0,0 +1,392 @@
+/**
+ * @file
+ * Support for different processor and compiler architectures
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_ARCH_H
+#define LWIP_HDR_ARCH_H
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+#include <stdlib.h>
+
+/**
+ * @defgroup compiler_abstraction Compiler/platform abstraction
+ * @ingroup sys_layer
+ * All defines related to this section must not be placed in lwipopts.h,
+ * but in arch/cc.h!
+ * If the compiler does not provide memset() this file must include a
+ * definition of it, or include a file which defines it.
+ * These options cannot be \#defined in lwipopts.h since they are not options
+ * of lwIP itself, but options of the lwIP port to your system.
+ * @{
+ */
+
+/** Define the byte order of the system.
+ * Needed for conversion of network data to host byte order.
+ * Allowed values: LITTLE_ENDIAN and BIG_ENDIAN
+ */
+#ifndef BYTE_ORDER
+#define BYTE_ORDER LITTLE_ENDIAN
+#endif
+
+/** Define random number generator function of your system */
+#define LWIP_RAND() ((u32_t)rand())
+
+/** Platform specific diagnostic output.\n
+ * Note the default implementation pulls in printf, which may
+ * in turn pull in a lot of standard libary code. In resource-constrained 
+ * systems, this should be defined to something less resource-consuming.
+ */
+#ifndef LWIP_PLATFORM_DIAG
+#define LWIP_PLATFORM_DIAG(x) do {printf x;} while(0)
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+/** Platform specific assertion handling.\n
+ * Note the default implementation pulls in printf, fflush and abort, which may
+ * in turn pull in a lot of standard libary code. In resource-constrained 
+ * systems, this should be defined to something less resource-consuming.
+ */
+#ifndef LWIP_PLATFORM_ASSERT
+#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \
+                                     x, __LINE__, __FILE__); fflush(NULL); abort();} while(0)
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if you do not want to
+ * include stddef.h header to get size_t. You need to typedef size_t
+ * by yourself in this case.
+ */
+#ifndef LWIP_NO_STDDEF_H
+#define LWIP_NO_STDDEF_H 0
+#endif
+
+#if !LWIP_NO_STDDEF_H
+#include <stddef.h> /* for size_t */
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the stdint.h header. You need to typedef the generic types listed in
+ * lwip/arch.h yourself in this case (u8_t, u16_t...).
+ */
+#ifndef LWIP_NO_STDINT_H
+#define LWIP_NO_STDINT_H 0
+#endif
+
+/* Define generic types used in lwIP */
+#if !LWIP_NO_STDINT_H
+#include <stdint.h>
+/* stdint.h is C99 which should also provide support for 64-bit integers */
+#if !defined(LWIP_HAVE_INT64) && defined(UINT64_MAX)
+#define LWIP_HAVE_INT64 1
+#endif
+typedef uint8_t   u8_t;
+typedef int8_t    s8_t;
+typedef uint16_t  u16_t;
+typedef int16_t   s16_t;
+typedef uint32_t  u32_t;
+typedef int32_t   s32_t;
+#if LWIP_HAVE_INT64
+typedef uint64_t  u64_t;
+typedef int64_t   s64_t;
+#endif
+typedef uintptr_t mem_ptr_t;
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the inttypes.h header. You need to define the format strings listed in
+ * lwip/arch.h yourself in this case (X8_F, U16_F...).
+ */
+#ifndef LWIP_NO_INTTYPES_H
+#define LWIP_NO_INTTYPES_H 0
+#endif
+
+/* Define (sn)printf formatters for these lwIP types */
+#if !LWIP_NO_INTTYPES_H
+#include <inttypes.h>
+#ifndef X8_F
+#define X8_F  "02" PRIx8
+#endif
+#ifndef U16_F
+#define U16_F PRIu16
+#endif
+#ifndef S16_F
+#define S16_F PRId16
+#endif
+#ifndef X16_F
+#define X16_F PRIx16
+#endif
+#ifndef U32_F
+#define U32_F PRIu32
+#endif
+#ifndef S32_F
+#define S32_F PRId32
+#endif
+#ifndef X32_F
+#define X32_F PRIx32
+#endif
+#ifndef SZT_F
+#define SZT_F PRIuPTR
+#endif
+#endif
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the limits.h header. You need to define the type limits yourself in this case
+ * (e.g. INT_MAX, SSIZE_MAX).
+ */
+#ifndef LWIP_NO_LIMITS_H
+#define LWIP_NO_LIMITS_H 0
+#endif
+
+/* Include limits.h? */
+#if !LWIP_NO_LIMITS_H
+#include <limits.h>
+#endif
+
+/* Do we need to define ssize_t? This is a compatibility hack:
+ * Unfortunately, this type seems to be unavailable on some systems (even if
+ * sys/types or unistd.h are available).
+ * Being like that, we define it to 'int' if SSIZE_MAX is not defined.
+ */
+#ifdef SSIZE_MAX
+/* If SSIZE_MAX is defined, unistd.h should provide the type as well */
+#ifndef LWIP_NO_UNISTD_H
+#define LWIP_NO_UNISTD_H 0
+#endif
+#if !LWIP_NO_UNISTD_H
+#include <unistd.h>
+#endif
+#else /* SSIZE_MAX */
+typedef int ssize_t;
+#define SSIZE_MAX INT_MAX
+#endif /* SSIZE_MAX */
+
+/* some maximum values needed in lwip code */
+#define LWIP_UINT32_MAX 0xffffffff
+
+/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
+ * the ctype.h header. If ctype.h is available, a few character functions
+ * are mapped to the appropriate functions (lwip_islower, lwip_isdigit...), if
+ * not, a private implementation is provided.
+ */
+#ifndef LWIP_NO_CTYPE_H
+#define LWIP_NO_CTYPE_H 0
+#endif
+
+#if LWIP_NO_CTYPE_H
+#define lwip_in_range(c, lo, up)  ((u8_t)(c) >= (lo) && (u8_t)(c) <= (up))
+#define lwip_isdigit(c)           lwip_in_range((c), '0', '9')
+#define lwip_isxdigit(c)          (lwip_isdigit(c) || lwip_in_range((c), 'a', 'f') || lwip_in_range((c), 'A', 'F'))
+#define lwip_islower(c)           lwip_in_range((c), 'a', 'z')
+#define lwip_isspace(c)           ((c) == ' ' || (c) == '\f' || (c) == '\n' || (c) == '\r' || (c) == '\t' || (c) == '\v')
+#define lwip_isupper(c)           lwip_in_range((c), 'A', 'Z')
+#define lwip_tolower(c)           (lwip_isupper(c) ? (c) - 'A' + 'a' : c)
+#define lwip_toupper(c)           (lwip_islower(c) ? (c) - 'a' + 'A' : c)
+#else
+#include <ctype.h>
+#define lwip_isdigit(c)           isdigit((unsigned char)(c))
+#define lwip_isxdigit(c)          isxdigit((unsigned char)(c))
+#define lwip_islower(c)           islower((unsigned char)(c))
+#define lwip_isspace(c)           isspace((unsigned char)(c))
+#define lwip_isupper(c)           isupper((unsigned char)(c))
+#define lwip_tolower(c)           tolower((unsigned char)(c))
+#define lwip_toupper(c)           toupper((unsigned char)(c))
+#endif
+
+/** C++ const_cast<target_type>(val) equivalent to remove constness from a value (GCC -Wcast-qual) */
+#ifndef LWIP_CONST_CAST
+#define LWIP_CONST_CAST(target_type, val) ((target_type)((ptrdiff_t)val))
+#endif
+
+/** Get rid of alignment cast warnings (GCC -Wcast-align) */
+#ifndef LWIP_ALIGNMENT_CAST
+#define LWIP_ALIGNMENT_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
+#endif
+
+/** Get rid of warnings related to pointer-to-numeric and vice-versa casts,
+ * e.g. "conversion from 'u8_t' to 'void *' of greater size"
+ */
+#ifndef LWIP_PTR_NUMERIC_CAST
+#define LWIP_PTR_NUMERIC_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
+#endif
+
+/** Avoid warnings/errors related to implicitly casting away packed attributes by doing a explicit cast */
+#ifndef LWIP_PACKED_CAST
+#define LWIP_PACKED_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
+#endif
+
+/** Allocates a memory buffer of specified size that is of sufficient size to align
+ * its start address using LWIP_MEM_ALIGN.
+ * You can declare your own version here e.g. to enforce alignment without adding
+ * trailing padding bytes (see LWIP_MEM_ALIGN_BUFFER) or your own section placement
+ * requirements.\n
+ * e.g. if you use gcc and need 32 bit alignment:\n
+ * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[size] \_\_attribute\_\_((aligned(4)))\n
+ * or more portable:\n
+ * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u32_t variable_name[(size + sizeof(u32_t) - 1) / sizeof(u32_t)]
+ */
+#ifndef LWIP_DECLARE_MEMORY_ALIGNED
+#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[LWIP_MEM_ALIGN_BUFFER(size)]
+#endif
+
+/** Calculate memory size for an aligned buffer - returns the next highest
+ * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and
+ * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4).
+ */
+#ifndef LWIP_MEM_ALIGN_SIZE
+#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1U) & ~(MEM_ALIGNMENT-1U))
+#endif
+
+/** Calculate safe memory size for an aligned buffer when using an unaligned
+ * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the
+ * start (e.g. if buffer is u8_t[] and actual data will be u32_t*)
+ */
+#ifndef LWIP_MEM_ALIGN_BUFFER
+#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1U))
+#endif
+
+/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT
+ * so that ADDR % MEM_ALIGNMENT == 0
+ */
+#ifndef LWIP_MEM_ALIGN
+#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Packed structs support.
+  * Placed BEFORE declaration of a packed struct.\n
+  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+  */
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+/** Packed structs support.
+  * Placed AFTER declaration of a packed struct.\n
+  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+  */
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+/** Packed structs support.
+  * Placed between end of declaration of a packed struct and trailing semicolon.\n
+  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+  */
+#ifndef PACK_STRUCT_STRUCT
+#if defined(__GNUC__) || defined(__clang__)
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#else
+#define PACK_STRUCT_STRUCT
+#endif
+#endif /* PACK_STRUCT_STRUCT */
+
+/** Packed structs support.
+  * Wraps u32_t and u16_t members.\n
+  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+  */
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+/** Packed structs support.
+  * Wraps u8_t members, where some compilers warn that packing is not necessary.\n
+  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+  */
+#ifndef PACK_STRUCT_FLD_8
+#define PACK_STRUCT_FLD_8(x) PACK_STRUCT_FIELD(x)
+#endif /* PACK_STRUCT_FLD_8 */
+
+/** Packed structs support.
+  * Wraps members that are packed structs themselves, where some compilers warn that packing is not necessary.\n
+  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+  */
+#ifndef PACK_STRUCT_FLD_S
+#define PACK_STRUCT_FLD_S(x) PACK_STRUCT_FIELD(x)
+#endif /* PACK_STRUCT_FLD_S */
+
+/** PACK_STRUCT_USE_INCLUDES==1: Packed structs support using \#include files before and after struct to be packed.\n
+ * The file included BEFORE the struct is "arch/bpstruct.h".\n
+ * The file included AFTER the struct is "arch/epstruct.h".\n
+ * This can be used to implement struct packing on MS Visual C compilers, see
+ * the Win32 port in the lwIP contrib repository for reference.
+ * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
+ * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
+ */
+#ifdef __DOXYGEN__
+#define PACK_STRUCT_USE_INCLUDES
+#endif
+
+/** Eliminates compiler warning about unused arguments (GCC -Wextra -Wunused). */
+#ifndef LWIP_UNUSED_ARG
+#define LWIP_UNUSED_ARG(x) (void)x
+#endif /* LWIP_UNUSED_ARG */
+
+/** LWIP_PROVIDE_ERRNO==1: Let lwIP provide ERRNO values and the 'errno' variable.
+ * If this is disabled, cc.h must either define 'errno', include <errno.h>,
+ * define LWIP_ERRNO_STDINCLUDE to get <errno.h> included or
+ * define LWIP_ERRNO_INCLUDE to <errno.h> or equivalent.
+ */
+#if defined __DOXYGEN__
+#define LWIP_PROVIDE_ERRNO
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ARCH_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/autoip.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/autoip.h
new file mode 100644
index 000000000..1d85bccff
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/autoip.h
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies <kontakt@dspies.de>
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ */
+
+#ifndef LWIP_HDR_AUTOIP_H
+#define LWIP_HDR_AUTOIP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+/* #include "lwip/udp.h" */
+#include "lwip/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL      100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/** AutoIP state information per netif */
+struct autoip
+{
+  /** the currently selected, probed, announced or used LL IP-Address */
+  ip4_addr_t llipaddr;
+  /** current AutoIP state machine state */
+  u8_t state;
+  /** sent number of probes or announces, dependent on state */
+  u8_t sent_num;
+  /** ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+  u16_t ttw;
+  /** ticks until a conflict can be solved by defending */
+  u8_t lastconflict;
+  /** total number of probed/used Link Local IP-Addresses */
+  u8_t tried_llipaddr;
+};
+
+
+void autoip_set_struct(struct netif *netif, struct autoip *autoip);
+/** Remove a struct autoip previously set to the netif using autoip_set_struct() */
+#define autoip_remove_struct(netif) do { (netif)->autoip = NULL; } while (0)
+err_t autoip_start(struct netif *netif);
+err_t autoip_stop(struct netif *netif);
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+void autoip_tmr(void);
+void autoip_network_changed(struct netif *netif);
+u8_t autoip_supplied_address(const struct netif *netif);
+
+/* for lwIP internal use by ip4.c */
+u8_t autoip_accept_packet(struct netif *netif, const ip4_addr_t *addr);
+
+#define netif_autoip_data(netif) ((struct autoip*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_AUTOIP */
+
+#endif /* LWIP_HDR_AUTOIP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/debug.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/debug.h
new file mode 100644
index 000000000..baa6a4090
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/debug.h
@@ -0,0 +1,161 @@
+/**
+ * @file
+ * Debug messages infrastructure
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_DEBUG_H
+#define LWIP_HDR_DEBUG_H
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+
+/**
+ * @defgroup debugging_levels LWIP_DBG_MIN_LEVEL and LWIP_DBG_TYPES_ON values
+ * @ingroup lwip_opts_debugmsg
+ * @{
+ */
+
+/** @name Debug level (LWIP_DBG_MIN_LEVEL)
+ * @{
+ */
+/** Debug level: ALL messages*/
+#define LWIP_DBG_LEVEL_ALL     0x00
+/** Debug level: Warnings. bad checksums, dropped packets, ... */
+#define LWIP_DBG_LEVEL_WARNING 0x01
+/** Debug level: Serious. memory allocation failures, ... */
+#define LWIP_DBG_LEVEL_SERIOUS 0x02
+/** Debug level: Severe */
+#define LWIP_DBG_LEVEL_SEVERE  0x03
+/**
+ * @}
+ */
+
+#define LWIP_DBG_MASK_LEVEL    0x03
+/* compatibility define only */
+#define LWIP_DBG_LEVEL_OFF     LWIP_DBG_LEVEL_ALL
+
+/** @name Enable/disable debug messages completely (LWIP_DBG_TYPES_ON)
+ * @{
+ */
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define LWIP_DBG_ON            0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define LWIP_DBG_OFF           0x00U
+/**
+ * @}
+ */
+
+/** @name Debug message types (LWIP_DBG_TYPES_ON)
+ * @{
+ */
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define LWIP_DBG_TRACE         0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define LWIP_DBG_STATE         0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define LWIP_DBG_FRESH         0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define LWIP_DBG_HALT          0x08U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_assertions Assertion handling
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_NOASSERT: Disable LWIP_ASSERT checks:
+ * To disable assertions define LWIP_NOASSERT in arch/cc.h.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_NOASSERT
+#undef LWIP_NOASSERT
+#endif
+/**
+ * @}
+ */
+
+#ifndef LWIP_NOASSERT
+#define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \
+  LWIP_PLATFORM_ASSERT(message); }} while(0)
+#else  /* LWIP_NOASSERT */
+#define LWIP_ASSERT(message, assertion)
+#endif /* LWIP_NOASSERT */
+
+#ifndef LWIP_ERROR
+#ifndef LWIP_NOASSERT
+#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_ASSERT(message)
+#elif defined LWIP_DEBUG
+#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_DIAG((message))
+#else
+#define LWIP_PLATFORM_ERROR(message)
+#endif
+
+/* if "expression" isn't true, then print "message" and execute "handler" expression */
+#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
+  LWIP_PLATFORM_ERROR(message); handler;}} while(0)
+#endif /* LWIP_ERROR */
+
+/** Enable debug message printing, but only if debug message type is enabled
+ *  AND is of correct type AND is at least LWIP_DBG_LEVEL.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_DEBUG
+#undef LWIP_DEBUG
+#endif
+
+#ifdef LWIP_DEBUG
+#define LWIP_DEBUGF(debug, message) do { \
+                               if ( \
+                                   ((debug) & LWIP_DBG_ON) && \
+                                   ((debug) & LWIP_DBG_TYPES_ON) && \
+                                   ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
+                                 LWIP_PLATFORM_DIAG(message); \
+                                 if ((debug) & LWIP_DBG_HALT) { \
+                                   while(1); \
+                                 } \
+                               } \
+                             } while(0)
+
+#else  /* LWIP_DEBUG */
+#define LWIP_DEBUGF(debug, message)
+#endif /* LWIP_DEBUG */
+
+#endif /* LWIP_HDR_DEBUG_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/def.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/def.h
new file mode 100644
index 000000000..dfb266d18
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/def.h
@@ -0,0 +1,152 @@
+/**
+ * @file
+ * various utility macros
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/**
+ * @defgroup perf Performance measurement
+ * @ingroup sys_layer
+ * All defines related to this section must not be placed in lwipopts.h,
+ * but in arch/perf.h!
+ * Measurement calls made throughout lwip, these can be defined to nothing.
+ * - PERF_START: start measuring something.
+ * - PERF_STOP(x): stop measuring something, and record the result.
+ */
+
+#ifndef LWIP_HDR_DEF_H
+#define LWIP_HDR_DEF_H
+
+/* arch.h might define NULL already */
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#if LWIP_PERF
+#include "arch/perf.h"
+#else /* LWIP_PERF */
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+#endif /* LWIP_PERF */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LWIP_MAX(x , y)  (((x) > (y)) ? (x) : (y))
+#define LWIP_MIN(x , y)  (((x) < (y)) ? (x) : (y))
+
+/* Get the number of entries in an array ('x' must NOT be a pointer!) */
+#define LWIP_ARRAYSIZE(x) (sizeof(x)/sizeof((x)[0]))
+
+/** Create u32_t value from bytes */
+#define LWIP_MAKEU32(a,b,c,d) (((u32_t)((a) & 0xff) << 24) | \
+                               ((u32_t)((b) & 0xff) << 16) | \
+                               ((u32_t)((c) & 0xff) << 8)  | \
+                                (u32_t)((d) & 0xff))
+
+#ifndef NULL
+#ifdef __cplusplus
+#define NULL 0
+#else
+#define NULL ((void *)0)
+#endif
+#endif
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define lwip_htons(x) ((u16_t)(x))
+#define lwip_ntohs(x) ((u16_t)(x))
+#define lwip_htonl(x) ((u32_t)(x))
+#define lwip_ntohl(x) ((u32_t)(x))
+#define PP_HTONS(x)   ((u16_t)(x))
+#define PP_NTOHS(x)   ((u16_t)(x))
+#define PP_HTONL(x)   ((u32_t)(x))
+#define PP_NTOHL(x)   ((u32_t)(x))
+#else /* BYTE_ORDER != BIG_ENDIAN */
+#ifndef lwip_htons
+u16_t lwip_htons(u16_t x);
+#endif
+#define lwip_ntohs(x) lwip_htons(x)
+
+#ifndef lwip_htonl
+u32_t lwip_htonl(u32_t x);
+#endif
+#define lwip_ntohl(x) lwip_htonl(x)
+
+/* These macros should be calculated by the preprocessor and are used
+   with compile-time constants only (so that there is no little-endian
+   overhead at runtime). */
+#define PP_HTONS(x) ((u16_t)((((x) & (u16_t)0x00ffU) << 8) | (((x) & (u16_t)0xff00U) >> 8)))
+#define PP_NTOHS(x) PP_HTONS(x)
+#define PP_HTONL(x) ((((x) & (u32_t)0x000000ffUL) << 24) | \
+                     (((x) & (u32_t)0x0000ff00UL) <<  8) | \
+                     (((x) & (u32_t)0x00ff0000UL) >>  8) | \
+                     (((x) & (u32_t)0xff000000UL) >> 24))
+#define PP_NTOHL(x) PP_HTONL(x)
+#endif /* BYTE_ORDER == BIG_ENDIAN */
+
+/* Provide usual function names as macros for users, but this can be turned off */
+#ifndef LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS
+#define htons(x) lwip_htons(x)
+#define ntohs(x) lwip_ntohs(x)
+#define htonl(x) lwip_htonl(x)
+#define ntohl(x) lwip_ntohl(x)
+#endif
+
+/* Functions that are not available as standard implementations.
+ * In cc.h, you can #define these to implementations available on
+ * your platform to save some code bytes if you use these functions
+ * in your application, too.
+ */
+
+#ifndef lwip_itoa
+/* This can be #defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform */
+void  lwip_itoa(char* result, size_t bufsize, int number);
+#endif
+#ifndef lwip_strnicmp
+/* This can be #defined to strnicmp() or strncasecmp() depending on your platform */
+int   lwip_strnicmp(const char* str1, const char* str2, size_t len);
+#endif
+#ifndef lwip_stricmp
+/* This can be #defined to stricmp() or strcasecmp() depending on your platform */
+int   lwip_stricmp(const char* str1, const char* str2);
+#endif
+#ifndef lwip_strnstr
+/* This can be #defined to strnstr() depending on your platform */
+char* lwip_strnstr(const char* buffer, const char* token, size_t n);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_DEF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dhcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dhcp.h
new file mode 100644
index 000000000..c78aa0baf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dhcp.h
@@ -0,0 +1,139 @@
+/**
+ * @file
+ * DHCP client API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg <leon.woestenberg@gmx.net>
+ *
+ */
+#ifndef LWIP_HDR_DHCP_H
+#define LWIP_HDR_DHCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS  60
+/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS   500
+
+#define DHCP_BOOT_FILE_LEN      128U
+
+/* AutoIP cooperation flags (struct dhcp.autoip_coop_state) */
+typedef enum {
+  DHCP_AUTOIP_COOP_STATE_OFF  = 0,
+  DHCP_AUTOIP_COOP_STATE_ON   = 1
+} dhcp_autoip_coop_state_enum_t;
+
+struct dhcp
+{
+  /** transaction identifier of last sent request */
+  u32_t xid;
+  /** track PCB allocation state */
+  u8_t pcb_allocated;
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+#if LWIP_DHCP_AUTOIP_COOP
+  u8_t autoip_coop_state;
+#endif
+  u8_t subnet_mask_given;
+
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  u16_t t1_renew_time;  /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */
+  u16_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */
+  u16_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */
+  u16_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */
+  ip_addr_t server_ip_addr; /* dhcp server address that offered this lease (ip_addr_t because passed to UDP) */
+  ip4_addr_t offered_ip_addr;
+  ip4_addr_t offered_sn_mask;
+  ip4_addr_t offered_gw_addr;
+
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period)  */
+#if LWIP_DHCP_BOOTP_FILE
+  ip4_addr_t offered_si_addr;
+  char boot_file_name[DHCP_BOOT_FILE_LEN];
+#endif /* LWIP_DHCP_BOOTPFILE */
+};
+
+
+void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp);
+/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */
+#define dhcp_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL)
+void dhcp_cleanup(struct netif *netif);
+err_t dhcp_start(struct netif *netif);
+err_t dhcp_renew(struct netif *netif);
+err_t dhcp_release(struct netif *netif);
+void dhcp_stop(struct netif *netif);
+void dhcp_release_and_stop(struct netif *netif);
+void dhcp_inform(struct netif *netif);
+void dhcp_network_changed(struct netif *netif);
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr);
+#endif
+u8_t dhcp_supplied_address(const struct netif *netif);
+/* to be called every minute */
+void dhcp_coarse_tmr(void);
+/* to be called every half second */
+void dhcp_fine_tmr(void);
+
+#if LWIP_DHCP_GET_NTP_SRV
+/** This function must exist, in other to add offered NTP servers to
+ * the NTP (or SNTP) engine.
+ * See LWIP_DHCP_MAX_NTP_SERVERS */
+extern void dhcp_set_ntp_servers(u8_t num_ntp_servers, const ip4_addr_t* ntp_server_addrs);
+#endif /* LWIP_DHCP_GET_NTP_SRV */
+
+#define netif_dhcp_data(netif) ((struct dhcp*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DHCP */
+
+#endif /*LWIP_HDR_DHCP_H*/
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dhcp6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dhcp6.h
new file mode 100644
index 000000000..5cc4a0159
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dhcp6.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * DHCPv6 client: IPv6 address autoconfiguration as per
+ * RFC 3315 (stateful DHCPv6) and
+ * RFC 3736 (stateless DHCPv6).
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ */
+
+#ifndef LWIP_HDR_IP6_DHCP6_H
+#define LWIP_HDR_IP6_DHCP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6_DHCP6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** period (in milliseconds) of the application calling dhcp6_tmr() */
+#define DHCP6_TIMER_MSECS   500
+
+struct dhcp6
+{
+  /** transaction identifier of last sent request */
+  u32_t xid;
+  /** track PCB allocation state */
+  u8_t pcb_allocated;
+  /** current DHCPv6 state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+  /** if request config is triggered while another action is active, this keeps track of it */
+  u8_t request_config_pending;
+  /** #ticks with period DHCP6_TIMER_MSECS for request timeout */
+  u16_t request_timeout;
+#if LWIP_IPV6_DHCP6_STATEFUL
+  /* @todo: add more members here to keep track of stateful DHCPv6 data, like lease times */
+#endif /* LWIP_IPV6_DHCP6_STATEFUL */
+};
+
+void dhcp6_set_struct(struct netif *netif, struct dhcp6 *dhcp6);
+/** Remove a struct dhcp6 previously set to the netif using dhcp6_set_struct() */
+#define dhcp6_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL)
+void dhcp6_cleanup(struct netif *netif);
+
+err_t dhcp6_enable_stateful(struct netif *netif);
+err_t dhcp6_enable_stateless(struct netif *netif);
+void dhcp6_disable(struct netif *netif);
+
+void dhcp6_tmr(void);
+
+void dhcp6_nd6_ra_trigger(struct netif *netif, u8_t managed_addr_config, u8_t other_config);
+
+#if LWIP_DHCP6_GET_NTP_SRV
+/** This function must exist, in other to add offered NTP servers to
+ * the NTP (or SNTP) engine.
+ * See LWIP_DHCP6_MAX_NTP_SERVERS */
+extern void dhcp6_set_ntp_servers(u8_t num_ntp_servers, const ip_addr_t* ntp_server_addrs);
+#endif /* LWIP_DHCP6_GET_NTP_SRV */
+
+#define netif_dhcp6_data(netif) ((struct dhcp6*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6_DHCP6 */
+
+#endif /* LWIP_HDR_IP6_DHCP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dns.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dns.h
new file mode 100644
index 000000000..091341544
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/dns.h
@@ -0,0 +1,131 @@
+/**
+ * @file
+ * DNS API
+ */
+
+/**
+ * lwip DNS resolver header file.
+
+ * Author: Jim Pettinato
+ *   April 2007
+
+ * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LWIP_HDR_DNS_H
+#define LWIP_HDR_DNS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DNS timer period */
+#define DNS_TMR_INTERVAL          1000
+
+/* DNS resolve types: */
+#define LWIP_DNS_ADDRTYPE_IPV4      0
+#define LWIP_DNS_ADDRTYPE_IPV6      1
+#define LWIP_DNS_ADDRTYPE_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
+#define LWIP_DNS_ADDRTYPE_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
+#if LWIP_IPV4 && LWIP_IPV6
+#ifndef LWIP_DNS_ADDRTYPE_DEFAULT
+#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV4_IPV6
+#endif
+#elif LWIP_IPV4
+#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV4
+#else
+#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV6
+#endif
+
+#if DNS_LOCAL_HOSTLIST
+/** struct used for local host-list */
+struct local_hostlist_entry {
+  /** static hostname */
+  const char *name;
+  /** static host address in network byteorder */
+  ip_addr_t addr;
+  struct local_hostlist_entry *next;
+};
+#define DNS_LOCAL_HOSTLIST_ELEM(name, addr_init) {name, addr_init, NULL}
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN
+#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN  DNS_MAX_NAME_LENGTH
+#endif
+#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1))
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#endif /* DNS_LOCAL_HOSTLIST */
+
+#if LWIP_IPV4
+extern const ip_addr_t dns_mquery_v4group;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+extern const ip_addr_t dns_mquery_v6group;
+#endif /* LWIP_IPV6 */
+
+/** Callback which is invoked when a hostname is found.
+ * A function of this type must be implemented by the application using the DNS resolver.
+ * @param name pointer to the name that was looked up.
+ * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname,
+ *        or NULL if the name could not be found (or on any other error).
+ * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
+*/
+typedef void (*dns_found_callback)(const char *name, const ip_addr_t *ipaddr, void *callback_arg);
+
+void             dns_init(void);
+void             dns_tmr(void);
+void             dns_setserver(u8_t numdns, const ip_addr_t *dnsserver);
+const ip_addr_t* dns_getserver(u8_t numdns);
+err_t            dns_gethostbyname(const char *hostname, ip_addr_t *addr,
+                                   dns_found_callback found, void *callback_arg);
+err_t            dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr,
+                                   dns_found_callback found, void *callback_arg,
+                                   u8_t dns_addrtype);
+
+
+#if DNS_LOCAL_HOSTLIST
+size_t         dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg);
+err_t          dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype);
+#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+int            dns_local_removehost(const char *hostname, const ip_addr_t *addr);
+err_t          dns_local_addhost(const char *hostname, const ip_addr_t *addr);
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+#endif /* DNS_LOCAL_HOSTLIST */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS */
+
+#endif /* LWIP_HDR_DNS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/err.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/err.h
new file mode 100644
index 000000000..887d9b3fd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/err.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ * lwIP Error codes
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_ERR_H
+#define LWIP_HDR_ERR_H
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup infrastructure_errors Error codes
+ * @ingroup infrastructure
+ * @{
+ */
+
+/** Definitions for error constants. */
+typedef enum {
+/** No error, everything OK. */
+  ERR_OK         = 0,
+/** Out of memory error.     */
+  ERR_MEM        = -1,
+/** Buffer error.            */
+  ERR_BUF        = -2,
+/** Timeout.                 */
+  ERR_TIMEOUT    = -3,
+/** Routing problem.         */
+  ERR_RTE        = -4,
+/** Operation in progress    */
+  ERR_INPROGRESS = -5,
+/** Illegal value.           */
+  ERR_VAL        = -6,
+/** Operation would block.   */
+  ERR_WOULDBLOCK = -7,
+/** Address in use.          */
+  ERR_USE        = -8,
+/** Already connecting.      */
+  ERR_ALREADY    = -9,
+/** Conn already established.*/
+  ERR_ISCONN     = -10,
+/** Not connected.           */
+  ERR_CONN       = -11,
+/** Low-level netif error    */
+  ERR_IF         = -12,
+
+/** Connection aborted.      */
+  ERR_ABRT       = -13,
+/** Connection reset.        */
+  ERR_RST        = -14,
+/** Connection closed.       */
+  ERR_CLSD       = -15,
+/** Illegal argument.        */
+  ERR_ARG        = -16
+} err_enum_t;
+
+/** Define LWIP_ERR_T in cc.h if you want to use
+ *  a different type for your platform (must be signed). */
+#ifdef LWIP_ERR_T
+typedef LWIP_ERR_T err_t;
+#else /* LWIP_ERR_T */
+typedef s8_t err_t;
+#endif /* LWIP_ERR_T*/
+
+/**
+ * @}
+ */
+
+#ifdef LWIP_DEBUG
+extern const char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+
+#if !NO_SYS
+int err_to_errno(err_t err);
+#endif /* !NO_SYS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ERR_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/errno.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/errno.h
new file mode 100644
index 000000000..48d6b539d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/errno.h
@@ -0,0 +1,198 @@
+/**
+ * @file
+ * Posix Errno defines
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_ERRNO_H
+#define LWIP_HDR_ERRNO_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM            1  /* Operation not permitted */
+#define  ENOENT           2  /* No such file or directory */
+#define  ESRCH            3  /* No such process */
+#define  EINTR            4  /* Interrupted system call */
+#define  EIO              5  /* I/O error */
+#define  ENXIO            6  /* No such device or address */
+#define  E2BIG            7  /* Arg list too long */
+#define  ENOEXEC          8  /* Exec format error */
+#define  EBADF            9  /* Bad file number */
+#define  ECHILD          10  /* No child processes */
+#define  EAGAIN          11  /* Try again */
+#define  ENOMEM          12  /* Out of memory */
+#define  EACCES          13  /* Permission denied */
+#define  EFAULT          14  /* Bad address */
+#define  ENOTBLK         15  /* Block device required */
+#define  EBUSY           16  /* Device or resource busy */
+#define  EEXIST          17  /* File exists */
+#define  EXDEV           18  /* Cross-device link */
+#define  ENODEV          19  /* No such device */
+#define  ENOTDIR         20  /* Not a directory */
+#define  EISDIR          21  /* Is a directory */
+#define  EINVAL          22  /* Invalid argument */
+#define  ENFILE          23  /* File table overflow */
+#define  EMFILE          24  /* Too many open files */
+#define  ENOTTY          25  /* Not a typewriter */
+#define  ETXTBSY         26  /* Text file busy */
+#define  EFBIG           27  /* File too large */
+#define  ENOSPC          28  /* No space left on device */
+#define  ESPIPE          29  /* Illegal seek */
+#define  EROFS           30  /* Read-only file system */
+#define  EMLINK          31  /* Too many links */
+#define  EPIPE           32  /* Broken pipe */
+#define  EDOM            33  /* Math argument out of domain of func */
+#define  ERANGE          34  /* Math result not representable */
+#define  EDEADLK         35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG    36  /* File name too long */
+#define  ENOLCK          37  /* No record locks available */
+#define  ENOSYS          38  /* Function not implemented */
+#define  ENOTEMPTY       39  /* Directory not empty */
+#define  ELOOP           40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define  ENOMSG          42  /* No message of desired type */
+#define  EIDRM           43  /* Identifier removed */
+#define  ECHRNG          44  /* Channel number out of range */
+#define  EL2NSYNC        45  /* Level 2 not synchronized */
+#define  EL3HLT          46  /* Level 3 halted */
+#define  EL3RST          47  /* Level 3 reset */
+#define  ELNRNG          48  /* Link number out of range */
+#define  EUNATCH         49  /* Protocol driver not attached */
+#define  ENOCSI          50  /* No CSI structure available */
+#define  EL2HLT          51  /* Level 2 halted */
+#define  EBADE           52  /* Invalid exchange */
+#define  EBADR           53  /* Invalid request descriptor */
+#define  EXFULL          54  /* Exchange full */
+#define  ENOANO          55  /* No anode */
+#define  EBADRQC         56  /* Invalid request code */
+#define  EBADSLT         57  /* Invalid slot */
+
+#define  EDEADLOCK       EDEADLK
+
+#define  EBFONT          59  /* Bad font file format */
+#define  ENOSTR          60  /* Device not a stream */
+#define  ENODATA         61  /* No data available */
+#define  ETIME           62  /* Timer expired */
+#define  ENOSR           63  /* Out of streams resources */
+#define  ENONET          64  /* Machine is not on the network */
+#define  ENOPKG          65  /* Package not installed */
+#define  EREMOTE         66  /* Object is remote */
+#define  ENOLINK         67  /* Link has been severed */
+#define  EADV            68  /* Advertise error */
+#define  ESRMNT          69  /* Srmount error */
+#define  ECOMM           70  /* Communication error on send */
+#define  EPROTO          71  /* Protocol error */
+#define  EMULTIHOP       72  /* Multihop attempted */
+#define  EDOTDOT         73  /* RFS specific error */
+#define  EBADMSG         74  /* Not a data message */
+#define  EOVERFLOW       75  /* Value too large for defined data type */
+#define  ENOTUNIQ        76  /* Name not unique on network */
+#define  EBADFD          77  /* File descriptor in bad state */
+#define  EREMCHG         78  /* Remote address changed */
+#define  ELIBACC         79  /* Can not access a needed shared library */
+#define  ELIBBAD         80  /* Accessing a corrupted shared library */
+#define  ELIBSCN         81  /* .lib section in a.out corrupted */
+#define  ELIBMAX         82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC        83  /* Cannot exec a shared library directly */
+#define  EILSEQ          84  /* Illegal byte sequence */
+#define  ERESTART        85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE        86  /* Streams pipe error */
+#define  EUSERS          87  /* Too many users */
+#define  ENOTSOCK        88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ    89  /* Destination address required */
+#define  EMSGSIZE        90  /* Message too long */
+#define  EPROTOTYPE      91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT     92  /* Protocol not available */
+#define  EPROTONOSUPPORT 93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT 94  /* Socket type not supported */
+#define  EOPNOTSUPP      95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT    96  /* Protocol family not supported */
+#define  EAFNOSUPPORT    97  /* Address family not supported by protocol */
+#define  EADDRINUSE      98  /* Address already in use */
+#define  EADDRNOTAVAIL   99  /* Cannot assign requested address */
+#define  ENETDOWN       100  /* Network is down */
+#define  ENETUNREACH    101  /* Network is unreachable */
+#define  ENETRESET      102  /* Network dropped connection because of reset */
+#define  ECONNABORTED   103  /* Software caused connection abort */
+#define  ECONNRESET     104  /* Connection reset by peer */
+#define  ENOBUFS        105  /* No buffer space available */
+#define  EISCONN        106  /* Transport endpoint is already connected */
+#define  ENOTCONN       107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN      108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS   109  /* Too many references: cannot splice */
+#define  ETIMEDOUT      110  /* Connection timed out */
+#define  ECONNREFUSED   111  /* Connection refused */
+#define  EHOSTDOWN      112  /* Host is down */
+#define  EHOSTUNREACH   113  /* No route to host */
+#define  EALREADY       114  /* Operation already in progress */
+#define  EINPROGRESS    115  /* Operation now in progress */
+#define  ESTALE         116  /* Stale NFS file handle */
+#define  EUCLEAN        117  /* Structure needs cleaning */
+#define  ENOTNAM        118  /* Not a XENIX named type file */
+#define  ENAVAIL        119  /* No XENIX semaphores available */
+#define  EISNAM         120  /* Is a named type file */
+#define  EREMOTEIO      121  /* Remote I/O error */
+#define  EDQUOT         122  /* Quota exceeded */
+
+#define  ENOMEDIUM      123  /* No medium found */
+#define  EMEDIUMTYPE    124  /* Wrong medium type */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#else /* LWIP_PROVIDE_ERRNO */
+
+/* Define LWIP_ERRNO_STDINCLUDE if you want to include <errno.h> here */
+#ifdef LWIP_ERRNO_STDINCLUDE
+#include <errno.h>
+#else /* LWIP_ERRNO_STDINCLUDE */
+/* Define LWIP_ERRNO_INCLUDE to an equivalent of <errno.h> to include the error defines here */
+#ifdef LWIP_ERRNO_INCLUDE
+#include LWIP_ERRNO_INCLUDE
+#endif /* LWIP_ERRNO_INCLUDE */
+#endif /* LWIP_ERRNO_STDINCLUDE */
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ERRNO_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/etharp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/etharp.h
new file mode 100644
index 000000000..2036b2464
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/etharp.h
@@ -0,0 +1,105 @@
+/**
+ * @file
+ * Ethernet output function - handles OUTGOING ethernet level traffic, implements
+ * ARP resolving.
+ * To be used in most low-level netif implementations
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_ETHARP_H
+#define LWIP_HDR_NETIF_ETHARP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip4_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip4.h"
+#include "lwip/prot/ethernet.h"
+
+#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/prot/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 seconds period */
+#define ARP_TMR_INTERVAL 1000
+
+#if ARP_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct etharp_q_entry {
+  struct etharp_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* ARP_QUEUEING */
+
+#define etharp_init() /* Compatibility define, no init needed. */
+void etharp_tmr(void);
+ssize_t etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+         struct eth_addr **eth_ret, const ip4_addr_t **ip_ret);
+int etharp_get_entry(size_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret);
+err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
+err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr);
+/** For Ethernet network interfaces, we might want to send "gratuitous ARP";
+ *  this is an ARP packet sent by a node in order to spontaneously cause other
+ *  nodes to update an entry in their ARP cache.
+ *  From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */
+#define etharp_gratuitous(netif) etharp_request((netif), netif_ip4_addr(netif))
+void etharp_cleanup_netif(struct netif *netif);
+
+#if ETHARP_SUPPORT_STATIC_ENTRIES
+err_t etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr);
+err_t etharp_remove_static_entry(const ip4_addr_t *ipaddr);
+#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
+
+void etharp_input(struct pbuf *p, struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_ARP */
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#endif /* LWIP_HDR_NETIF_ETHARP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ethip6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ethip6.h
new file mode 100644
index 000000000..5e88dffd0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ethip6.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ *
+ * Ethernet output for IPv6. Uses ND tables for link-layer addressing.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_ETHIP6_H
+#define LWIP_HDR_ETHIP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6 && LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+err_t ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 && LWIP_ETHERNET */
+
+#endif /* LWIP_HDR_ETHIP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/icmp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/icmp.h
new file mode 100644
index 000000000..f5a31fd4c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/icmp.h
@@ -0,0 +1,110 @@
+/**
+ * @file
+ * ICMP API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_ICMP_H
+#define LWIP_HDR_ICMP_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/prot/icmp.h"
+
+#if LWIP_IPV6 && LWIP_ICMP6
+#include "lwip/icmp6.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICMP destination unreachable codes */
+enum icmp_dur_type {
+  /** net unreachable */
+  ICMP_DUR_NET   = 0,
+  /** host unreachable */
+  ICMP_DUR_HOST  = 1,
+  /** protocol unreachable */
+  ICMP_DUR_PROTO = 2,
+  /** port unreachable */
+  ICMP_DUR_PORT  = 3,
+  /** fragmentation needed and DF set */
+  ICMP_DUR_FRAG  = 4,
+  /** source route failed */
+  ICMP_DUR_SR    = 5
+};
+
+/** ICMP time exceeded codes */
+enum icmp_te_type {
+  /** time to live exceeded in transit */
+  ICMP_TE_TTL  = 0,
+  /** fragment reassembly time exceeded */
+  ICMP_TE_FRAG = 1
+};
+
+#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#endif /* LWIP_IPV4 && LWIP_ICMP */
+
+#if LWIP_IPV4 && LWIP_IPV6
+#if LWIP_ICMP && LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \
+                                         icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \
+                                         icmp_dest_unreach(pbuf, ICMP_DUR_PORT))
+#elif LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) do{ if(!(isipv6)) { icmp_dest_unreach(pbuf, ICMP_DUR_PORT);}}while(0)
+#elif LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) do{ if(isipv6) { icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT);}}while(0)
+#else
+#define icmp_port_unreach(isipv6, pbuf)
+#endif
+#elif LWIP_IPV6 && LWIP_ICMP6
+#define icmp_port_unreach(isipv6, pbuf) icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT)
+#elif LWIP_IPV4 && LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT)
+#else /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) */
+#define icmp_port_unreach(isipv6, pbuf)
+#endif /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) LWIP_IPV4*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_ICMP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/icmp6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/icmp6.h
new file mode 100644
index 000000000..0ccb78994
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/icmp6.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * IPv6 version of ICMP, as per RFC 4443.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+#ifndef LWIP_HDR_ICMP6_H
+#define LWIP_HDR_ICMP6_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+#include "lwip/prot/icmp6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+void icmp6_input(struct pbuf *p, struct netif *inp);
+void icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c);
+void icmp6_packet_too_big(struct pbuf *p, u32_t mtu);
+void icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c);
+void icmp6_time_exceeded_with_addrs(struct pbuf *p, enum icmp6_te_code c,
+    const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr);
+void icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, const void *pointer);
+
+#endif /* LWIP_ICMP6 && LWIP_IPV6 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LWIP_HDR_ICMP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/if_api.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/if_api.h
new file mode 100644
index 000000000..39017abd3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/if_api.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ * Interface Identification APIs from:
+ *              RFC 3493: Basic Socket Interface Extensions for IPv6
+ *                  Section 4: Interface Identification
+ */
+
+/*
+ * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. <joel.cunningham@garmin.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Joel Cunningham <joel.cunningham@me.com>
+ *
+ */
+#ifndef LWIP_HDR_IF_H
+#define LWIP_HDR_IF_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IF_NAMESIZE NETIF_NAMESIZE
+
+char * lwip_if_indextoname(unsigned int ifindex, char *ifname);
+unsigned int lwip_if_nametoindex(const char *ifname);
+
+#if LWIP_COMPAT_SOCKETS
+#define if_indextoname(ifindex, ifname)  lwip_if_indextoname(ifindex,ifname)
+#define if_nametoindex(ifname)           lwip_if_nametoindex(ifname)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_IF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/igmp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/igmp.h
new file mode 100644
index 000000000..ffd80e680
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/igmp.h
@@ -0,0 +1,115 @@
+/**
+ * @file
+ * IGMP API
+ */
+
+/*
+ * Copyright (c) 2002 CITEL Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+*/
+
+#ifndef LWIP_HDR_IGMP_H
+#define LWIP_HDR_IGMP_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/pbuf.h"
+
+#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* IGMP timer */
+#define IGMP_TMR_INTERVAL              100 /* Milliseconds */
+#define IGMP_V1_DELAYING_MEMBER_TMR   (1000/IGMP_TMR_INTERVAL)
+#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
+
+/* Compatibility defines (don't use for new code) */
+#define IGMP_DEL_MAC_FILTER            NETIF_DEL_MAC_FILTER
+#define IGMP_ADD_MAC_FILTER            NETIF_ADD_MAC_FILTER
+
+/**
+ * igmp group structure - there is
+ * a list of groups for each interface
+ * these should really be linked from the interface, but
+ * if we keep them separate we will not affect the lwip original code
+ * too much
+ *
+ * There will be a group for the all systems group address but this
+ * will not run the state machine as it is used to kick off reports
+ * from all the other groups
+ */
+struct igmp_group {
+  /** next link */
+  struct igmp_group *next;
+  /** multicast address */
+  ip4_addr_t         group_address;
+  /** signifies we were the last person to report */
+  u8_t               last_reporter_flag;
+  /** current state of the group */
+  u8_t               group_state;
+  /** timer for reporting, negative is OFF */
+  u16_t              timer;
+  /** counter of simultaneous uses */
+  u8_t               use;
+};
+
+/*  Prototypes */
+void   igmp_init(void);
+err_t  igmp_start(struct netif *netif);
+err_t  igmp_stop(struct netif *netif);
+void   igmp_report_groups(struct netif *netif);
+struct igmp_group *igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr);
+void   igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest);
+err_t  igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
+err_t  igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
+err_t  igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
+err_t  igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
+void   igmp_tmr(void);
+
+/** @ingroup igmp 
+ * Get list head of IGMP groups for netif.
+ * Note: The allsystems group IP is contained in the list as first entry.
+ * @see @ref netif_set_igmp_mac_filter()
+ */
+#define netif_igmp_data(netif) ((struct igmp_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+
+#endif /* LWIP_HDR_IGMP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/inet.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/inet.h
new file mode 100644
index 000000000..2982a0f4b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/inet.h
@@ -0,0 +1,169 @@
+/**
+ * @file
+ * This file (together with sockets.h) aims to provide structs and functions from
+ * - arpa/inet.h
+ * - netinet/in.h
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_INET_H
+#define LWIP_HDR_INET_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If your port already typedef's in_addr_t, define IN_ADDR_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(in_addr_t) && !defined(IN_ADDR_T_DEFINED)
+typedef u32_t in_addr_t;
+#endif
+
+struct in_addr {
+  in_addr_t s_addr;
+};
+
+struct in6_addr {
+  union {
+    u32_t u32_addr[4];
+    u8_t  u8_addr[16];
+  } un;
+#define s6_addr  un.u8_addr
+};
+
+/** 255.255.255.255 */
+#define INADDR_NONE         IPADDR_NONE
+/** 127.0.0.1 */
+#define INADDR_LOOPBACK     IPADDR_LOOPBACK
+/** 0.0.0.0 */
+#define INADDR_ANY          IPADDR_ANY
+/** 255.255.255.255 */
+#define INADDR_BROADCAST    IPADDR_BROADCAST
+
+/** This macro can be used to initialize a variable of type struct in6_addr
+    to the IPv6 wildcard address. */
+#define IN6ADDR_ANY_INIT {{{0,0,0,0}}}
+/** This macro can be used to initialize a variable of type struct in6_addr
+    to the IPv6 loopback address. */
+#define IN6ADDR_LOOPBACK_INIT {{{0,0,0,PP_HTONL(1)}}}
+/** This variable is initialized by the system to contain the wildcard IPv6 address. */
+extern const struct in6_addr in6addr_any;
+
+/* Definitions of the bits in an (IPv4) Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+#define IN_CLASSA(a)        IP_CLASSA(a)
+#define IN_CLASSA_NET       IP_CLASSA_NET
+#define IN_CLASSA_NSHIFT    IP_CLASSA_NSHIFT
+#define IN_CLASSA_HOST      IP_CLASSA_HOST
+#define IN_CLASSA_MAX       IP_CLASSA_MAX
+
+#define IN_CLASSB(b)        IP_CLASSB(b)
+#define IN_CLASSB_NET       IP_CLASSB_NET
+#define IN_CLASSB_NSHIFT    IP_CLASSB_NSHIFT
+#define IN_CLASSB_HOST      IP_CLASSB_HOST
+#define IN_CLASSB_MAX       IP_CLASSB_MAX
+
+#define IN_CLASSC(c)        IP_CLASSC(c)
+#define IN_CLASSC_NET       IP_CLASSC_NET
+#define IN_CLASSC_NSHIFT    IP_CLASSC_NSHIFT
+#define IN_CLASSC_HOST      IP_CLASSC_HOST
+#define IN_CLASSC_MAX       IP_CLASSC_MAX
+
+#define IN_CLASSD(d)        IP_CLASSD(d)
+#define IN_CLASSD_NET       IP_CLASSD_NET     /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    IP_CLASSD_NSHIFT  /*   net and host fields, but */
+#define IN_CLASSD_HOST      IP_CLASSD_HOST    /*   routing needn't know. */
+#define IN_CLASSD_MAX       IP_CLASSD_MAX
+
+#define IN_MULTICAST(a)     IP_MULTICAST(a)
+
+#define IN_EXPERIMENTAL(a)  IP_EXPERIMENTAL(a)
+#define IN_BADCLASS(a)      IP_BADCLASS(a)
+
+#define IN_LOOPBACKNET      IP_LOOPBACKNET
+
+
+#ifndef INET_ADDRSTRLEN
+#define INET_ADDRSTRLEN     IP4ADDR_STRLEN_MAX
+#endif
+#if LWIP_IPV6
+#ifndef INET6_ADDRSTRLEN
+#define INET6_ADDRSTRLEN    IP6ADDR_STRLEN_MAX
+#endif
+#endif
+
+#if LWIP_IPV4
+
+#define inet_addr_from_ip4addr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr))
+#define inet_addr_to_ip4addr(target_ipaddr, source_inaddr)   (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr))
+
+/* directly map this to the lwip internal functions */
+#define inet_addr(cp)                   ipaddr_addr(cp)
+#define inet_aton(cp, addr)             ip4addr_aton(cp, (ip4_addr_t*)addr)
+#define inet_ntoa(addr)                 ip4addr_ntoa((const ip4_addr_t*)&(addr))
+#define inet_ntoa_r(addr, buf, buflen)  ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen)
+
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) {(target_in6addr)->un.u32_addr[0] = (source_ip6addr)->addr[0]; \
+                                                                 (target_in6addr)->un.u32_addr[1] = (source_ip6addr)->addr[1]; \
+                                                                 (target_in6addr)->un.u32_addr[2] = (source_ip6addr)->addr[2]; \
+                                                                 (target_in6addr)->un.u32_addr[3] = (source_ip6addr)->addr[3];}
+#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr)   {(target_ip6addr)->addr[0] = (source_in6addr)->un.u32_addr[0]; \
+                                                                 (target_ip6addr)->addr[1] = (source_in6addr)->un.u32_addr[1]; \
+                                                                 (target_ip6addr)->addr[2] = (source_in6addr)->un.u32_addr[2]; \
+                                                                 (target_ip6addr)->addr[3] = (source_in6addr)->un.u32_addr[3]; \
+                                                                 ip6_addr_clear_zone(target_ip6addr);}
+
+/* directly map this to the lwip internal functions */
+#define inet6_aton(cp, addr)            ip6addr_aton(cp, (ip6_addr_t*)addr)
+#define inet6_ntoa(addr)                ip6addr_ntoa((const ip6_addr_t*)&(addr))
+#define inet6_ntoa_r(addr, buf, buflen) ip6addr_ntoa_r((const ip6_addr_t*)&(addr), buf, buflen)
+
+#endif /* LWIP_IPV6 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INET_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/inet_chksum.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/inet_chksum.h
new file mode 100644
index 000000000..76893ef52
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/inet_chksum.h
@@ -0,0 +1,105 @@
+/**
+ * @file
+ * IP checksum calculation functions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_INET_CHKSUM_H
+#define LWIP_HDR_INET_CHKSUM_H
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+/** Swap the bytes in an u16_t: much like lwip_htons() for little-endian */
+#ifndef SWAP_BYTES_IN_WORD
+#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8)
+#endif /* SWAP_BYTES_IN_WORD */
+
+/** Split an u32_t in two u16_ts and add them up */
+#ifndef FOLD_U32T
+#define FOLD_U32T(u)          ((u32_t)(((u) >> 16) + ((u) & 0x0000ffffUL)))
+#endif
+
+#if LWIP_CHECKSUM_ON_COPY
+/** Function-like macro: same as MEMCPY but returns the checksum of copied data
+    as u16_t */
+# ifndef LWIP_CHKSUM_COPY
+#  define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len)
+#  ifndef LWIP_CHKSUM_COPY_ALGORITHM
+#   define LWIP_CHKSUM_COPY_ALGORITHM 1
+#  endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+# else /* LWIP_CHKSUM_COPY */
+#  define LWIP_CHKSUM_COPY_ALGORITHM 0
+# endif /* LWIP_CHKSUM_COPY */
+#else /* LWIP_CHECKSUM_ON_COPY */
+# define LWIP_CHKSUM_COPY_ALGORITHM 0
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+u16_t inet_chksum(const void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+#if LWIP_CHKSUM_COPY_ALGORITHM
+u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len);
+#endif /* LWIP_CHKSUM_COPY_ALGORITHM */
+
+#if LWIP_IPV4
+u16_t inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+       const ip4_addr_t *src, const ip4_addr_t *dest);
+u16_t inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto,
+       u16_t proto_len, u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest);
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+u16_t ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+       const ip6_addr_t *src, const ip6_addr_t *dest);
+u16_t ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+       u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest);
+#endif /* LWIP_IPV6 */
+
+
+u16_t ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
+       const ip_addr_t *src, const ip_addr_t *dest);
+u16_t ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
+       u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INET_H */
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/init.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/init.h
new file mode 100644
index 000000000..a149be184
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/init.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * lwIP initialization API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_INIT_H
+#define LWIP_HDR_INIT_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lwip_version Version
+ * @ingroup lwip
+ * @{
+ */
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR      2
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR      1
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION   2
+/** For release candidates, this is set to 1..254
+  * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+  * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC         LWIP_RC_RELEASE
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE         255
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */
+#define LWIP_RC_DEVELOPMENT     0
+
+#define LWIP_VERSION_IS_RELEASE     (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC          ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/* Some helper defines to get a version string */
+#define LWIP_VERSTR2(x) #x
+#define LWIP_VERSTR(x) LWIP_VERSTR2(x)
+#if LWIP_VERSION_IS_RELEASE
+#define LWIP_VERSION_STRING_SUFFIX ""
+#elif LWIP_VERSION_IS_DEVELOPMENT
+#define LWIP_VERSION_STRING_SUFFIX "d"
+#else
+#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC)
+#endif
+
+/** Provides the version of the stack */
+#define LWIP_VERSION   ((LWIP_VERSION_MAJOR) << 24   | (LWIP_VERSION_MINOR) << 16 | \
+                        (LWIP_VERSION_REVISION) << 8 | (LWIP_VERSION_RC))
+/** Provides the version of the stack as string */
+#define LWIP_VERSION_STRING     LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX
+
+/**
+ * @}
+ */
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INIT_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/init.h.cmake.in b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/init.h.cmake.in
new file mode 100644
index 000000000..9b609b742
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/init.h.cmake.in
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * lwIP initialization API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_INIT_H
+#define LWIP_HDR_INIT_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup lwip_version Version
+ * @ingroup lwip
+ * @{
+ */
+
+/** X.x.x: Major version of the stack */
+#define LWIP_VERSION_MAJOR      ${LWIP_VERSION_MAJOR}
+/** x.X.x: Minor version of the stack */
+#define LWIP_VERSION_MINOR      ${LWIP_VERSION_MINOR}
+/** x.x.X: Revision of the stack */
+#define LWIP_VERSION_REVISION   ${LWIP_VERSION_REVISION}
+/** For release candidates, this is set to 1..254
+  * For official releases, this is set to 255 (LWIP_RC_RELEASE)
+  * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */
+#define LWIP_VERSION_RC         ${LWIP_VERSION_RC}
+
+/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
+#define LWIP_RC_RELEASE         255
+/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */
+#define LWIP_RC_DEVELOPMENT     0
+
+#define LWIP_VERSION_IS_RELEASE     (LWIP_VERSION_RC == LWIP_RC_RELEASE)
+#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
+#define LWIP_VERSION_IS_RC          ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
+
+/* Some helper defines to get a version string */
+#define LWIP_VERSTR2(x) #x
+#define LWIP_VERSTR(x) LWIP_VERSTR2(x)
+#if LWIP_VERSION_IS_RELEASE
+#define LWIP_VERSION_STRING_SUFFIX ""
+#elif LWIP_VERSION_IS_DEVELOPMENT
+#define LWIP_VERSION_STRING_SUFFIX "d"
+#else
+#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC)
+#endif
+
+/** Provides the version of the stack */
+#define LWIP_VERSION   ((LWIP_VERSION_MAJOR) << 24   | (LWIP_VERSION_MINOR) << 16 | \
+                        (LWIP_VERSION_REVISION) << 8 | (LWIP_VERSION_RC))
+/** Provides the version of the stack as string */
+#define LWIP_VERSION_STRING     LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX
+
+/**
+ * @}
+ */
+
+/* Modules initialization */
+void lwip_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_INIT_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip.h
new file mode 100644
index 000000000..653c3b2f4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip.h
@@ -0,0 +1,330 @@
+/**
+ * @file
+ * IP API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_IP_H
+#define LWIP_HDR_IP_H
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+#include "lwip/ip4.h"
+#include "lwip/ip6.h"
+#include "lwip/prot/ip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#define LWIP_IP_HDRINCL  NULL
+
+/** pbufs passed to IP must have a ref-count of 1 as their payload pointer
+    gets altered as the packet is passed down the stack */
+#ifndef LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX
+#define LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p) LWIP_ASSERT("p->ref == 1", (p)->ref == 1)
+#endif
+
+#if LWIP_NETIF_USE_HINTS
+#define IP_PCB_NETIFHINT ;struct netif_hint netif_hints
+#else /* LWIP_NETIF_USE_HINTS */
+#define IP_PCB_NETIFHINT
+#endif /* LWIP_NETIF_USE_HINTS */
+
+/** This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB                             \
+  /* ip addresses in network byte order */ \
+  ip_addr_t local_ip;                      \
+  ip_addr_t remote_ip;                     \
+  /* Bound netif index */                  \
+  u8_t netif_idx;                          \
+  /* Socket options */                     \
+  u8_t so_options;                         \
+  /* Type Of Service */                    \
+  u8_t tos;                                \
+  /* Time To Live */                       \
+  u8_t ttl                                 \
+  /* link layer address resolution hint */ \
+  IP_PCB_NETIFHINT
+
+struct ip_pcb {
+  /* Common members of all PCB types */
+  IP_PCB;
+};
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX in sockets.h
+ */
+#define SOF_REUSEADDR     0x04U  /* allow local address reuse */
+#define SOF_KEEPALIVE     0x08U  /* keep connections alive */
+#define SOF_BROADCAST     0x20U  /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+
+/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */
+#define SOF_INHERITED   (SOF_REUSEADDR|SOF_KEEPALIVE)
+
+/** Global variables of this module, kept in a struct for efficient access using base+index. */
+struct ip_globals
+{
+  /** The interface that accepted the packet for the current callback invocation. */
+  struct netif *current_netif;
+  /** The interface that received the packet for the current callback invocation. */
+  struct netif *current_input_netif;
+#if LWIP_IPV4
+  /** Header of the input packet currently being processed. */
+  const struct ip_hdr *current_ip4_header;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  /** Header of the input IPv6 packet currently being processed. */
+  struct ip6_hdr *current_ip6_header;
+#endif /* LWIP_IPV6 */
+  /** Total header length of current_ip4/6_header (i.e. after this, the UDP/TCP header starts) */
+  u16_t current_ip_header_tot_len;
+  /** Source IP address of current_header */
+  ip_addr_t current_iphdr_src;
+  /** Destination IP address of current_header */
+  ip_addr_t current_iphdr_dest;
+};
+extern struct ip_globals ip_data;
+
+
+/** Get the interface that accepted the current packet.
+ * This may or may not be the receiving netif, depending on your netif/network setup.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_netif()      (ip_data.current_netif)
+/** Get the interface that received the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip_current_input_netif() (ip_data.current_input_netif)
+/** Total header length of ip(6)_current_header() (i.e. after this, the UDP/TCP header starts) */
+#define ip_current_header_tot_len() (ip_data.current_ip_header_tot_len)
+/** Source IP address of current_header */
+#define ip_current_src_addr()   (&ip_data.current_iphdr_src)
+/** Destination IP address of current_header */
+#define ip_current_dest_addr()  (&ip_data.current_iphdr_dest)
+
+#if LWIP_IPV4 && LWIP_IPV6
+/** Get the IPv4 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip4_current_header()     ip_data.current_ip4_header
+/** Get the IPv6 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip6_current_header()      ((const struct ip6_hdr*)(ip_data.current_ip6_header))
+/** Returns TRUE if the current IP input packet is IPv6, FALSE if it is IPv4 */
+#define ip_current_is_v6()        (ip6_current_header() != NULL)
+/** Source IPv6 address of current_header */
+#define ip6_current_src_addr()    (ip_2_ip6(&ip_data.current_iphdr_src))
+/** Destination IPv6 address of current_header */
+#define ip6_current_dest_addr()   (ip_2_ip6(&ip_data.current_iphdr_dest))
+/** Get the transport layer protocol */
+#define ip_current_header_proto() (ip_current_is_v6() ? \
+                                   IP6H_NEXTH(ip6_current_header()) :\
+                                   IPH_PROTO(ip4_current_header()))
+/** Get the transport layer header */
+#define ip_next_header_ptr()     ((const void*)((ip_current_is_v6() ? \
+  (const u8_t*)ip6_current_header() : (const u8_t*)ip4_current_header())  + ip_current_header_tot_len()))
+
+/** Source IP4 address of current_header */
+#define ip4_current_src_addr()     (ip_2_ip4(&ip_data.current_iphdr_src))
+/** Destination IP4 address of current_header */
+#define ip4_current_dest_addr()    (ip_2_ip4(&ip_data.current_iphdr_dest))
+
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** Get the IPv4 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip4_current_header()     ip_data.current_ip4_header
+/** Always returns FALSE when only supporting IPv4 only */
+#define ip_current_is_v6()        0
+/** Get the transport layer protocol */
+#define ip_current_header_proto() IPH_PROTO(ip4_current_header())
+/** Get the transport layer header */
+#define ip_next_header_ptr()     ((const void*)((const u8_t*)ip4_current_header() + ip_current_header_tot_len()))
+/** Source IP4 address of current_header */
+#define ip4_current_src_addr()     (&ip_data.current_iphdr_src)
+/** Destination IP4 address of current_header */
+#define ip4_current_dest_addr()    (&ip_data.current_iphdr_dest)
+
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+
+/** Get the IPv6 header of the current packet.
+ * This function must only be called from a receive callback (udp_recv,
+ * raw_recv, tcp_accept). It will return NULL otherwise. */
+#define ip6_current_header()      ((const struct ip6_hdr*)(ip_data.current_ip6_header))
+/** Always returns TRUE when only supporting IPv6 only */
+#define ip_current_is_v6()        1
+/** Get the transport layer protocol */
+#define ip_current_header_proto() IP6H_NEXTH(ip6_current_header())
+/** Get the transport layer header */
+#define ip_next_header_ptr()     ((const void*)(((const u8_t*)ip6_current_header()) + ip_current_header_tot_len()))
+/** Source IP6 address of current_header */
+#define ip6_current_src_addr()    (&ip_data.current_iphdr_src)
+/** Destination IP6 address of current_header */
+#define ip6_current_dest_addr()   (&ip_data.current_iphdr_dest)
+
+#endif /* LWIP_IPV6 */
+
+/** Union source address of current_header */
+#define ip_current_src_addr()    (&ip_data.current_iphdr_src)
+/** Union destination address of current_header */
+#define ip_current_dest_addr()   (&ip_data.current_iphdr_dest)
+
+/** Gets an IP pcb option (SOF_* flags) */
+#define ip_get_option(pcb, opt)   ((pcb)->so_options & (opt))
+/** Sets an IP pcb option (SOF_* flags) */
+#define ip_set_option(pcb, opt)   ((pcb)->so_options = (u8_t)((pcb)->so_options | (opt)))
+/** Resets an IP pcb option (SOF_* flags) */
+#define ip_reset_option(pcb, opt) ((pcb)->so_options = (u8_t)((pcb)->so_options & ~(opt)))
+
+#if LWIP_IPV4 && LWIP_IPV6
+/**
+ * @ingroup ip
+ * Output IP packet, netif is selected by source address
+ */
+#define ip_output(p, src, dest, ttl, tos, proto) \
+        (IP_IS_V6(dest) ? \
+        ip6_output(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto) : \
+        ip4_output(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto))
+/**
+ * @ingroup ip
+ * Output IP packet to specified interface
+ */
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_if(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
+        ip4_output_if(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
+/**
+ * @ingroup ip
+ * Output IP packet to interface specifying source address
+ */
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_if_src(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
+        ip4_output_if_src(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
+/** Output IP packet that already includes an IP header. */
+#define ip_output_if_hdrincl(p, src, dest, netif) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_if(p, ip_2_ip6(src), LWIP_IP_HDRINCL, 0, 0, 0, netif) : \
+        ip4_output_if(p, ip_2_ip4(src), LWIP_IP_HDRINCL, 0, 0, 0, netif))
+/** Output IP packet with netif_hint */
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \
+        (IP_IS_V6(dest) ? \
+        ip6_output_hinted(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif_hint) : \
+        ip4_output_hinted(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif_hint))
+/**
+ * @ingroup ip
+ * Get netif for address combination. See \ref ip6_route and \ref ip4_route
+ */
+#define ip_route(src, dest) \
+        (IP_IS_V6(dest) ? \
+        ip6_route(ip_2_ip6(src), ip_2_ip6(dest)) : \
+        ip4_route_src(ip_2_ip4(src), ip_2_ip4(dest)))
+/**
+ * @ingroup ip
+ * Get netif for IP.
+ */
+#define ip_netif_get_local_ip(netif, dest) (IP_IS_V6(dest) ? \
+        ip6_netif_get_local_ip(netif, ip_2_ip6(dest)) : \
+        ip4_netif_get_local_ip(netif))
+#define ip_debug_print(is_ipv6, p) ((is_ipv6) ? ip6_debug_print(p) : ip4_debug_print(p))
+
+err_t ip_input(struct pbuf *p, struct netif *inp);
+
+#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define ip_output(p, src, dest, ttl, tos, proto) \
+        ip4_output(p, src, dest, ttl, tos, proto)
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+        ip4_output_if(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+        ip4_output_if_src(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \
+        ip4_output_hinted(p, src, dest, ttl, tos, proto, netif_hint)
+#define ip_output_if_hdrincl(p, src, dest, netif) \
+        ip4_output_if(p, src, LWIP_IP_HDRINCL, 0, 0, 0, netif)
+#define ip_route(src, dest) \
+        ip4_route_src(src, dest)
+#define ip_netif_get_local_ip(netif, dest) \
+        ip4_netif_get_local_ip(netif)
+#define ip_debug_print(is_ipv6, p) ip4_debug_print(p)
+
+#define ip_input ip4_input
+
+#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define ip_output(p, src, dest, ttl, tos, proto) \
+        ip6_output(p, src, dest, ttl, tos, proto)
+#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
+        ip6_output_if(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
+        ip6_output_if_src(p, src, dest, ttl, tos, proto, netif)
+#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \
+        ip6_output_hinted(p, src, dest, ttl, tos, proto, netif_hint)
+#define ip_output_if_hdrincl(p, src, dest, netif) \
+        ip6_output_if(p, src, LWIP_IP_HDRINCL, 0, 0, 0, netif)
+#define ip_route(src, dest) \
+        ip6_route(src, dest)
+#define ip_netif_get_local_ip(netif, dest) \
+        ip6_netif_get_local_ip(netif, dest)
+#define ip_debug_print(is_ipv6, p) ip6_debug_print(p)
+
+#define ip_input ip6_input
+
+#endif /* LWIP_IPV6 */
+
+#define ip_route_get_local_ip(src, dest, netif, ipaddr) do { \
+  (netif) = ip_route(src, dest); \
+  (ipaddr) = ip_netif_get_local_ip(netif, dest); \
+}while(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP_H */
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4.h
new file mode 100644
index 000000000..fd35a3369
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4.h
@@ -0,0 +1,111 @@
+/**
+ * @file
+ * IPv4 API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_IP4_H
+#define LWIP_HDR_IP4_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV4
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip4_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+#include "lwip/prot/ip4.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef LWIP_HOOK_IP4_ROUTE_SRC
+#define LWIP_IPV4_SRC_ROUTING   1
+#else
+#define LWIP_IPV4_SRC_ROUTING   0
+#endif
+
+/** Currently, the function ip_output_if_opt() is only used with IGMP */
+#define IP_OPTIONS_SEND   (LWIP_IPV4 && LWIP_IGMP)
+
+#define ip_init() /* Compatibility define, no init needed. */
+struct netif *ip4_route(const ip4_addr_t *dest);
+#if LWIP_IPV4_SRC_ROUTING
+struct netif *ip4_route_src(const ip4_addr_t *src, const ip4_addr_t *dest);
+#else /* LWIP_IPV4_SRC_ROUTING */
+#define ip4_route_src(src, dest) ip4_route(dest)
+#endif /* LWIP_IPV4_SRC_ROUTING */
+err_t ip4_input(struct pbuf *p, struct netif *inp);
+err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto);
+err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
+#if LWIP_NETIF_USE_HINTS
+err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif_hint *netif_hint);
+#endif /* LWIP_NETIF_USE_HINTS */
+#if IP_OPTIONS_SEND
+err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen);
+err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
+       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
+       u16_t optlen);
+#endif /* IP_OPTIONS_SEND */
+
+#if LWIP_MULTICAST_TX_OPTIONS
+void  ip4_set_default_multicast_netif(struct netif* default_multicast_netif);
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL)
+
+#if IP_DEBUG
+void ip4_debug_print(struct pbuf *p);
+#else
+#define ip4_debug_print(p)
+#endif /* IP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_H */
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4_addr.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4_addr.h
new file mode 100644
index 000000000..f244c4f54
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4_addr.h
@@ -0,0 +1,216 @@
+/**
+ * @file
+ * IPv4 address API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_IP4_ADDR_H
+#define LWIP_HDR_IP4_ADDR_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#if LWIP_IPV4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This is the aligned version of ip4_addr_t,
+   used as local variable, on the stack, etc. */
+struct ip4_addr {
+  u32_t addr;
+};
+
+/** ip4_addr_t uses a struct for convenience only, so that the same defines can
+ * operate both on ip4_addr_t as well as on ip4_addr_p_t. */
+typedef struct ip4_addr ip4_addr_t;
+
+/* Forward declaration to not include netif.h */
+struct netif;
+
+/** 255.255.255.255 */
+#define IPADDR_NONE         ((u32_t)0xffffffffUL)
+/** 127.0.0.1 */
+#define IPADDR_LOOPBACK     ((u32_t)0x7f000001UL)
+/** 0.0.0.0 */
+#define IPADDR_ANY          ((u32_t)0x00000000UL)
+/** 255.255.255.255 */
+#define IPADDR_BROADCAST    ((u32_t)0xffffffffUL)
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+#define IP_CLASSA(a)        ((((u32_t)(a)) & 0x80000000UL) == 0)
+#define IP_CLASSA_NET       0xff000000
+#define IP_CLASSA_NSHIFT    24
+#define IP_CLASSA_HOST      (0xffffffff & ~IP_CLASSA_NET)
+#define IP_CLASSA_MAX       128
+
+#define IP_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
+#define IP_CLASSB_NET       0xffff0000
+#define IP_CLASSB_NSHIFT    16
+#define IP_CLASSB_HOST      (0xffffffff & ~IP_CLASSB_NET)
+#define IP_CLASSB_MAX       65536
+
+#define IP_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
+#define IP_CLASSC_NET       0xffffff00
+#define IP_CLASSC_NSHIFT    8
+#define IP_CLASSC_HOST      (0xffffffff & ~IP_CLASSC_NET)
+
+#define IP_CLASSD(a)        (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
+#define IP_CLASSD_NET       0xf0000000          /* These ones aren't really */
+#define IP_CLASSD_NSHIFT    28                  /*   net and host fields, but */
+#define IP_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
+#define IP_MULTICAST(a)     IP_CLASSD(a)
+
+#define IP_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+#define IP_BADCLASS(a)      (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
+
+#define IP_LOOPBACKNET      127                 /* official! */
+
+/** Set an IP address given by the four byte-parts */
+#define IP4_ADDR(ipaddr, a,b,c,d)  (ipaddr)->addr = PP_HTONL(LWIP_MAKEU32(a,b,c,d))
+
+/** Copy IP address - faster than ip4_addr_set: no NULL check */
+#define ip4_addr_copy(dest, src) ((dest).addr = (src).addr)
+/** Safely copy one IP address to another (src may be NULL) */
+#define ip4_addr_set(dest, src) ((dest)->addr = \
+                                    ((src) == NULL ? 0 : \
+                                    (src)->addr))
+/** Set complete address to zero */
+#define ip4_addr_set_zero(ipaddr)     ((ipaddr)->addr = 0)
+/** Set address to IPADDR_ANY (no need for lwip_htonl()) */
+#define ip4_addr_set_any(ipaddr)      ((ipaddr)->addr = IPADDR_ANY)
+/** Set address to loopback address */
+#define ip4_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK))
+/** Check if an address is in the loopback region */
+#define ip4_addr_isloopback(ipaddr)    (((ipaddr)->addr & PP_HTONL(IP_CLASSA_NET)) == PP_HTONL(((u32_t)IP_LOOPBACKNET) << 24))
+/** Safely copy one IP address to another and change byte order
+ * from host- to network-order. */
+#define ip4_addr_set_hton(dest, src) ((dest)->addr = \
+                               ((src) == NULL ? 0:\
+                               lwip_htonl((src)->addr)))
+/** IPv4 only: set the IP address given as an u32_t */
+#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32))
+/** IPv4 only: get the IP address as an u32_t */
+#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr)
+
+/** Get the network address by combining host address with netmask */
+#define ip4_addr_get_network(target, host, netmask) do { ((target)->addr = ((host)->addr) & ((netmask)->addr)); } while(0)
+
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip4_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip4_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip4_addr_isany_val(addr1)   ((addr1).addr == IPADDR_ANY)
+#define ip4_addr_isany(addr1) ((addr1) == NULL || ip4_addr_isany_val(*(addr1)))
+
+#define ip4_addr_isbroadcast(addr1, netif) ip4_addr_isbroadcast_u32((addr1)->addr, netif)
+u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif);
+
+#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr)
+u8_t ip4_addr_netmask_valid(u32_t netmask);
+
+#define ip4_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL))
+
+#define ip4_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL))
+
+#define ip4_addr_debug_print_parts(debug, a, b, c, d) \
+  LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F, a, b, c, d))
+#define ip4_addr_debug_print(debug, ipaddr) \
+  ip4_addr_debug_print_parts(debug, \
+                      (u16_t)((ipaddr) != NULL ? ip4_addr1_16(ipaddr) : 0),       \
+                      (u16_t)((ipaddr) != NULL ? ip4_addr2_16(ipaddr) : 0),       \
+                      (u16_t)((ipaddr) != NULL ? ip4_addr3_16(ipaddr) : 0),       \
+                      (u16_t)((ipaddr) != NULL ? ip4_addr4_16(ipaddr) : 0))
+#define ip4_addr_debug_print_val(debug, ipaddr) \
+  ip4_addr_debug_print_parts(debug, \
+                      ip4_addr1_16_val(ipaddr),       \
+                      ip4_addr2_16_val(ipaddr),       \
+                      ip4_addr3_16_val(ipaddr),       \
+                      ip4_addr4_16_val(ipaddr))
+
+/* Get one byte from the 4-byte address */
+#define ip4_addr_get_byte(ipaddr, idx) (((const u8_t*)(&(ipaddr)->addr))[idx])
+#define ip4_addr1(ipaddr) ip4_addr_get_byte(ipaddr, 0)
+#define ip4_addr2(ipaddr) ip4_addr_get_byte(ipaddr, 1)
+#define ip4_addr3(ipaddr) ip4_addr_get_byte(ipaddr, 2)
+#define ip4_addr4(ipaddr) ip4_addr_get_byte(ipaddr, 3)
+/* Get one byte from the 4-byte address, but argument is 'ip4_addr_t',
+ * not a pointer */
+#define ip4_addr_get_byte_val(ipaddr, idx) ((u8_t)(((ipaddr).addr >> (idx * 8)) & 0xff))
+#define ip4_addr1_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 0)
+#define ip4_addr2_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 1)
+#define ip4_addr3_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 2)
+#define ip4_addr4_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 3)
+/* These are cast to u16_t, with the intent that they are often arguments
+ * to printf using the U16_F format from cc.h. */
+#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
+#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
+#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
+#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
+#define ip4_addr1_16_val(ipaddr) ((u16_t)ip4_addr1_val(ipaddr))
+#define ip4_addr2_16_val(ipaddr) ((u16_t)ip4_addr2_val(ipaddr))
+#define ip4_addr3_16_val(ipaddr) ((u16_t)ip4_addr3_val(ipaddr))
+#define ip4_addr4_16_val(ipaddr) ((u16_t)ip4_addr4_val(ipaddr))
+
+#define IP4ADDR_STRLEN_MAX  16
+
+/** For backwards compatibility */
+#define ip_ntoa(ipaddr)  ipaddr_ntoa(ipaddr)
+
+u32_t ipaddr_addr(const char *cp);
+int ip4addr_aton(const char *cp, ip4_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ip4addr_ntoa(const ip4_addr_t *addr);
+char *ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4_frag.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4_frag.h
new file mode 100644
index 000000000..ed5bf14a3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip4_frag.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * IP fragmentation/reassembly
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Jani Monoses <jani@iv.ro>
+ *
+ */
+
+#ifndef LWIP_HDR_IP4_FRAG_H
+#define LWIP_HDR_IP4_FRAG_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+
+#if LWIP_IPV4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if IP_REASSEMBLY
+/* The IP reassembly timer interval in milliseconds. */
+#define IP_TMR_INTERVAL 1000
+
+/** IP reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip_reassdata {
+  struct ip_reassdata *next;
+  struct pbuf *p;
+  struct ip_hdr iphdr;
+  u16_t datagram_len;
+  u8_t flags;
+  u8_t timer;
+};
+
+void ip_reass_init(void);
+void ip_reass_tmr(void);
+struct pbuf * ip4_reass(struct pbuf *p);
+#endif /* IP_REASSEMBLY */
+
+#if IP_FRAG
+#if !LWIP_NETIF_TX_SINGLE_PBUF
+#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
+#define LWIP_PBUF_CUSTOM_REF_DEFINED
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+struct pbuf_custom_ref {
+  /** 'base class' */
+  struct pbuf_custom pc;
+  /** pointer to the original pbuf that is referenced */
+  struct pbuf *original;
+};
+#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
+#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
+
+err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest);
+#endif /* IP_FRAG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV4 */
+
+#endif /* LWIP_HDR_IP4_FRAG_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6.h
new file mode 100644
index 000000000..f894e063e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6.h
@@ -0,0 +1,93 @@
+/**
+ * @file
+ *
+ * IPv6 layer.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+#ifndef LWIP_HDR_IP6_H
+#define LWIP_HDR_IP6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/ip6.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netif *ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest);
+const ip_addr_t *ip6_select_source_address(struct netif *netif, const ip6_addr_t * dest);
+err_t         ip6_input(struct pbuf *p, struct netif *inp);
+err_t         ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                         u8_t hl, u8_t tc, u8_t nexth);
+err_t         ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                            u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
+err_t         ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                            u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
+#if LWIP_NETIF_USE_HINTS
+err_t         ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
+                                u8_t hl, u8_t tc, u8_t nexth, struct netif_hint *netif_hint);
+#endif /* LWIP_NETIF_USE_HINTS */
+#if LWIP_IPV6_MLD
+err_t         ip6_options_add_hbh_ra(struct pbuf * p, u8_t nexth, u8_t value);
+#endif /* LWIP_IPV6_MLD */
+
+#define ip6_netif_get_local_ip(netif, dest) (((netif) != NULL) ? \
+  ip6_select_source_address(netif, dest) : NULL)
+
+#if IP6_DEBUG
+void ip6_debug_print(struct pbuf *p);
+#else
+#define ip6_debug_print(p)
+#endif /* IP6_DEBUG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_IP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_addr.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_addr.h
new file mode 100644
index 000000000..29c2a34d9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_addr.h
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * IPv6 addresses.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ * Structs and macros for handling IPv6 addresses.
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+#ifndef LWIP_HDR_IP6_ADDR_H
+#define LWIP_HDR_IP6_ADDR_H
+
+#include "lwip/opt.h"
+#include "def.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_zone.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** This is the aligned version of ip6_addr_t,
+    used as local variable, on the stack, etc. */
+struct ip6_addr {
+  u32_t addr[4];
+#if LWIP_IPV6_SCOPES
+  u8_t zone;
+#endif /* LWIP_IPV6_SCOPES */
+};
+
+/** IPv6 address */
+typedef struct ip6_addr ip6_addr_t;
+
+/** Set an IPv6 partial address given by byte-parts */
+#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \
+  (ip6addr)->addr[index] = PP_HTONL(LWIP_MAKEU32(a,b,c,d))
+
+/** Set a full IPv6 address by passing the 4 u32_t indices in network byte order
+    (use PP_HTONL() for constants) */
+#define IP6_ADDR(ip6addr, idx0, idx1, idx2, idx3) do { \
+  (ip6addr)->addr[0] = idx0; \
+  (ip6addr)->addr[1] = idx1; \
+  (ip6addr)->addr[2] = idx2; \
+  (ip6addr)->addr[3] = idx3; \
+  ip6_addr_clear_zone(ip6addr); } while(0)
+
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK1(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK2(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0])) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK3(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK4(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1])) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK5(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK6(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2])) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK7(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3]) >> 16) & 0xffff))
+/** Access address in 16-bit block */
+#define IP6_ADDR_BLOCK8(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3])) & 0xffff))
+
+/** Copy IPv6 address - faster than ip6_addr_set: no NULL check */
+#define ip6_addr_copy(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+                                    (dest).addr[1] = (src).addr[1]; \
+                                    (dest).addr[2] = (src).addr[2]; \
+                                    (dest).addr[3] = (src).addr[3]; \
+                                    ip6_addr_copy_zone((dest), (src)); }while(0)
+/** Safely copy one IPv6 address to another (src may be NULL) */
+#define ip6_addr_set(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : (src)->addr[0]; \
+                                   (dest)->addr[1] = (src) == NULL ? 0 : (src)->addr[1]; \
+                                   (dest)->addr[2] = (src) == NULL ? 0 : (src)->addr[2]; \
+                                   (dest)->addr[3] = (src) == NULL ? 0 : (src)->addr[3]; \
+                                   ip6_addr_set_zone((dest), (src) == NULL ? IP6_NO_ZONE : ip6_addr_zone(src)); }while(0)
+
+/** Copy packed IPv6 address to unpacked IPv6 address; zone is not set */
+#define ip6_addr_copy_from_packed(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+                                    (dest).addr[1] = (src).addr[1]; \
+                                    (dest).addr[2] = (src).addr[2]; \
+                                    (dest).addr[3] = (src).addr[3]; \
+                                    ip6_addr_clear_zone(&dest); }while(0)
+
+/** Copy unpacked IPv6 address to packed IPv6 address; zone is lost */
+#define ip6_addr_copy_to_packed(dest, src) do{(dest).addr[0] = (src).addr[0]; \
+                                    (dest).addr[1] = (src).addr[1]; \
+                                    (dest).addr[2] = (src).addr[2]; \
+                                    (dest).addr[3] = (src).addr[3]; }while(0)
+
+/** Set complete address to zero */
+#define ip6_addr_set_zero(ip6addr)    do{(ip6addr)->addr[0] = 0; \
+                                         (ip6addr)->addr[1] = 0; \
+                                         (ip6addr)->addr[2] = 0; \
+                                         (ip6addr)->addr[3] = 0; \
+                                         ip6_addr_clear_zone(ip6addr);}while(0)
+
+/** Set address to ipv6 'any' (no need for lwip_htonl()) */
+#define ip6_addr_set_any(ip6addr)       ip6_addr_set_zero(ip6addr)
+/** Set address to ipv6 loopback address */
+#define ip6_addr_set_loopback(ip6addr) do{(ip6addr)->addr[0] = 0; \
+                                          (ip6addr)->addr[1] = 0; \
+                                          (ip6addr)->addr[2] = 0; \
+                                          (ip6addr)->addr[3] = PP_HTONL(0x00000001UL); \
+                                          ip6_addr_clear_zone(ip6addr);}while(0)
+/** Safely copy one IPv6 address to another and change byte order
+ * from host- to network-order. */
+#define ip6_addr_set_hton(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : lwip_htonl((src)->addr[0]); \
+                                        (dest)->addr[1] = (src) == NULL ? 0 : lwip_htonl((src)->addr[1]); \
+                                        (dest)->addr[2] = (src) == NULL ? 0 : lwip_htonl((src)->addr[2]); \
+                                        (dest)->addr[3] = (src) == NULL ? 0 : lwip_htonl((src)->addr[3]); \
+                                        ip6_addr_set_zone((dest), (src) == NULL ? IP6_NO_ZONE : ip6_addr_zone(src));}while(0)
+
+
+/** Compare IPv6 networks, ignoring zone information. To be used sparingly! */
+#define ip6_addr_netcmp_zoneless(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
+                                               ((addr1)->addr[1] == (addr2)->addr[1]))
+
+/**
+ * Determine if two IPv6 address are on the same network.
+ *
+ * @param addr1 IPv6 address 1
+ * @param addr2 IPv6 address 2
+ * @return 1 if the network identifiers of both address match, 0 if not
+ */
+#define ip6_addr_netcmp(addr1, addr2) (ip6_addr_netcmp_zoneless((addr1), (addr2)) && \
+                                       ip6_addr_cmp_zone((addr1), (addr2)))
+
+/* Exact-host comparison *after* ip6_addr_netcmp() succeeded, for efficiency. */
+#define ip6_addr_nethostcmp(addr1, addr2) (((addr1)->addr[2] == (addr2)->addr[2]) && \
+                                           ((addr1)->addr[3] == (addr2)->addr[3]))
+
+/** Compare IPv6 addresses, ignoring zone information. To be used sparingly! */
+#define ip6_addr_cmp_zoneless(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
+                                    ((addr1)->addr[1] == (addr2)->addr[1]) && \
+                                    ((addr1)->addr[2] == (addr2)->addr[2]) && \
+                                    ((addr1)->addr[3] == (addr2)->addr[3]))
+/**
+ * Determine if two IPv6 addresses are the same. In particular, the address
+ * part of both must be the same, and the zone must be compatible.
+ *
+ * @param addr1 IPv6 address 1
+ * @param addr2 IPv6 address 2
+ * @return 1 if the addresses are considered equal, 0 if not
+ */
+#define ip6_addr_cmp(addr1, addr2) (ip6_addr_cmp_zoneless((addr1), (addr2)) && \
+                                    ip6_addr_cmp_zone((addr1), (addr2)))
+
+/** Compare IPv6 address to packed address and zone */
+#define ip6_addr_cmp_packed(ip6addr, paddr, zone_idx) (((ip6addr)->addr[0] == (paddr)->addr[0]) && \
+                                    ((ip6addr)->addr[1] == (paddr)->addr[1]) && \
+                                    ((ip6addr)->addr[2] == (paddr)->addr[2]) && \
+                                    ((ip6addr)->addr[3] == (paddr)->addr[3]) && \
+                                    ip6_addr_equals_zone((ip6addr), (zone_idx)))
+
+#define ip6_get_subnet_id(ip6addr)   (lwip_htonl((ip6addr)->addr[2]) & 0x0000ffffUL)
+
+#define ip6_addr_isany_val(ip6addr) (((ip6addr).addr[0] == 0) && \
+                                     ((ip6addr).addr[1] == 0) && \
+                                     ((ip6addr).addr[2] == 0) && \
+                                     ((ip6addr).addr[3] == 0))
+#define ip6_addr_isany(ip6addr) (((ip6addr) == NULL) || ip6_addr_isany_val(*(ip6addr)))
+
+#define ip6_addr_isloopback(ip6addr) (((ip6addr)->addr[0] == 0UL) && \
+                                      ((ip6addr)->addr[1] == 0UL) && \
+                                      ((ip6addr)->addr[2] == 0UL) && \
+                                      ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+
+#define ip6_addr_isglobal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xe0000000UL)) == PP_HTONL(0x20000000UL))
+
+#define ip6_addr_islinklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfe800000UL))
+
+#define ip6_addr_issitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfec00000UL))
+
+#define ip6_addr_isuniquelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xfe000000UL)) == PP_HTONL(0xfc000000UL))
+
+#define ip6_addr_isipv4mappedipv6(ip6addr) (((ip6addr)->addr[0] == 0) && ((ip6addr)->addr[1] == 0) && (((ip6addr)->addr[2]) == PP_HTONL(0x0000FFFFUL)))
+
+#define ip6_addr_ismulticast(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL))
+#define ip6_addr_multicast_transient_flag(ip6addr)  ((ip6addr)->addr[0] & PP_HTONL(0x00100000UL))
+#define ip6_addr_multicast_prefix_flag(ip6addr)     ((ip6addr)->addr[0] & PP_HTONL(0x00200000UL))
+#define ip6_addr_multicast_rendezvous_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00400000UL))
+#define ip6_addr_multicast_scope(ip6addr) ((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xf)
+#define IP6_MULTICAST_SCOPE_RESERVED            0x0
+#define IP6_MULTICAST_SCOPE_RESERVED0           0x0
+#define IP6_MULTICAST_SCOPE_INTERFACE_LOCAL     0x1
+#define IP6_MULTICAST_SCOPE_LINK_LOCAL          0x2
+#define IP6_MULTICAST_SCOPE_RESERVED3           0x3
+#define IP6_MULTICAST_SCOPE_ADMIN_LOCAL         0x4
+#define IP6_MULTICAST_SCOPE_SITE_LOCAL          0x5
+#define IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL  0x8
+#define IP6_MULTICAST_SCOPE_GLOBAL              0xe
+#define IP6_MULTICAST_SCOPE_RESERVEDF           0xf
+#define ip6_addr_ismulticast_iflocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff010000UL))
+#define ip6_addr_ismulticast_linklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff020000UL))
+#define ip6_addr_ismulticast_adminlocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff040000UL))
+#define ip6_addr_ismulticast_sitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff050000UL))
+#define ip6_addr_ismulticast_orglocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff080000UL))
+#define ip6_addr_ismulticast_global(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff0e0000UL))
+
+/* Scoping note: while interface-local and link-local multicast addresses do
+ * have a scope (i.e., they are meaningful only in the context of a particular
+ * interface), the following functions are not assigning or comparing zone
+ * indices. The reason for this is backward compatibility. Any call site that
+ * produces a non-global multicast address must assign a multicast address as
+ * appropriate itself. */
+
+#define ip6_addr_isallnodes_iflocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff010000UL)) && \
+    ((ip6addr)->addr[1] == 0UL) && \
+    ((ip6addr)->addr[2] == 0UL) && \
+    ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+
+#define ip6_addr_isallnodes_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+    ((ip6addr)->addr[1] == 0UL) && \
+    ((ip6addr)->addr[2] == 0UL) && \
+    ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
+#define ip6_addr_set_allnodes_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+                (ip6addr)->addr[1] = 0; \
+                (ip6addr)->addr[2] = 0; \
+                (ip6addr)->addr[3] = PP_HTONL(0x00000001UL); \
+                ip6_addr_clear_zone(ip6addr); }while(0)
+
+#define ip6_addr_isallrouters_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+    ((ip6addr)->addr[1] == 0UL) && \
+    ((ip6addr)->addr[2] == 0UL) && \
+    ((ip6addr)->addr[3] == PP_HTONL(0x00000002UL)))
+#define ip6_addr_set_allrouters_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+                (ip6addr)->addr[1] = 0; \
+                (ip6addr)->addr[2] = 0; \
+                (ip6addr)->addr[3] = PP_HTONL(0x00000002UL); \
+                ip6_addr_clear_zone(ip6addr); }while(0)
+
+#define ip6_addr_issolicitednode(ip6addr) ( ((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+        ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
+        (((ip6addr)->addr[3] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) )
+
+#define ip6_addr_set_solicitednode(ip6addr, if_id) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
+                (ip6addr)->addr[1] = 0; \
+                (ip6addr)->addr[2] = PP_HTONL(0x00000001UL); \
+                (ip6addr)->addr[3] = (PP_HTONL(0xff000000UL) | (if_id)); \
+                ip6_addr_clear_zone(ip6addr); }while(0)
+
+#define ip6_addr_cmp_solicitednode(ip6addr, sn_addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
+                                    ((ip6addr)->addr[1] == 0) && \
+                                    ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
+                                    ((ip6addr)->addr[3] == (PP_HTONL(0xff000000UL) | (sn_addr)->addr[3])))
+
+/* IPv6 address states. */
+#define IP6_ADDR_INVALID      0x00
+#define IP6_ADDR_TENTATIVE    0x08
+#define IP6_ADDR_TENTATIVE_1  0x09 /* 1 probe sent */
+#define IP6_ADDR_TENTATIVE_2  0x0a /* 2 probes sent */
+#define IP6_ADDR_TENTATIVE_3  0x0b /* 3 probes sent */
+#define IP6_ADDR_TENTATIVE_4  0x0c /* 4 probes sent */
+#define IP6_ADDR_TENTATIVE_5  0x0d /* 5 probes sent */
+#define IP6_ADDR_TENTATIVE_6  0x0e /* 6 probes sent */
+#define IP6_ADDR_TENTATIVE_7  0x0f /* 7 probes sent */
+#define IP6_ADDR_VALID        0x10 /* This bit marks an address as valid (preferred or deprecated) */
+#define IP6_ADDR_PREFERRED    0x30
+#define IP6_ADDR_DEPRECATED   0x10 /* Same as VALID (valid but not preferred) */
+#define IP6_ADDR_DUPLICATED   0x40 /* Failed DAD test, not valid */
+
+#define IP6_ADDR_TENTATIVE_COUNT_MASK 0x07 /* 1-7 probes sent */
+
+#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID)
+#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE)
+#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) /* Include valid, preferred, and deprecated. */
+#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED)
+#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED)
+#define ip6_addr_isduplicated(addr_state) (addr_state == IP6_ADDR_DUPLICATED)
+
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+#define IP6_ADDR_LIFE_STATIC   (0)
+#define IP6_ADDR_LIFE_INFINITE (0xffffffffUL)
+#define ip6_addr_life_isstatic(addr_life) ((addr_life) == IP6_ADDR_LIFE_STATIC)
+#define ip6_addr_life_isinfinite(addr_life) ((addr_life) == IP6_ADDR_LIFE_INFINITE)
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+
+#define ip6_addr_debug_print_parts(debug, a, b, c, d, e, f, g, h) \
+  LWIP_DEBUGF(debug, ("%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F, \
+                      a, b, c, d, e, f, g, h))
+#define ip6_addr_debug_print(debug, ipaddr) \
+  ip6_addr_debug_print_parts(debug, \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK1(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK2(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK3(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK4(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK5(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK6(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK7(ipaddr) : 0),    \
+                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK8(ipaddr) : 0))
+#define ip6_addr_debug_print_val(debug, ipaddr) \
+  ip6_addr_debug_print_parts(debug, \
+                      IP6_ADDR_BLOCK1(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK2(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK3(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK4(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK5(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK6(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK7(&(ipaddr)),    \
+                      IP6_ADDR_BLOCK8(&(ipaddr)))
+
+#define IP6ADDR_STRLEN_MAX    46
+
+int ip6addr_aton(const char *cp, ip6_addr_t *addr);
+/** returns ptr to static buffer; not reentrant! */
+char *ip6addr_ntoa(const ip6_addr_t *addr);
+char *ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_IP6_ADDR_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_frag.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_frag.h
new file mode 100644
index 000000000..87e0e86a6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_frag.h
@@ -0,0 +1,144 @@
+/**
+ * @file
+ *
+ * IPv6 fragmentation and reassembly.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+#ifndef LWIP_HDR_IP6_FRAG_H
+#define LWIP_HDR_IP6_FRAG_H
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/ip6.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS  /* don't build if not configured for use in lwipopts.h */
+
+/** The IPv6 reassembly timer interval in milliseconds. */
+#define IP6_REASS_TMR_INTERVAL 1000
+
+/** IP6_FRAG_COPYHEADER==1: for platforms where sizeof(void*) > 4, "struct
+ * ip6_reass_helper" is too large to be stored in the IPv6 fragment header, and
+ * will bleed into the header before it, which may be the IPv6 header or an
+ * extension header. This means that for each first fragment packet, we need to
+ * 1) make a copy of some IPv6 header fields (src+dest) that we need later on,
+ * just in case we do overwrite part of the IPv6 header, and 2) make a copy of
+ * the header data that we overwrote, so that we can restore it before either
+ * completing reassembly or sending an ICMPv6 reply. The last part is true even
+ * if this setting is disabled, but if it is enabled, we need to save a bit
+ * more data (up to the size of a pointer) because we overwrite more. */
+#ifndef IPV6_FRAG_COPYHEADER
+#define IPV6_FRAG_COPYHEADER   0
+#endif
+
+/* With IPV6_FRAG_COPYHEADER==1, a helper structure may (or, depending on the
+ * presence of extensions, may not) overwrite part of the IP header. Therefore,
+ * we copy the fields that we need from the IP header for as long as the helper
+ * structure may still be in place. This is easier than temporarily restoring
+ * those fields in the IP header each time we need to perform checks on them. */
+#if IPV6_FRAG_COPYHEADER
+#define IPV6_FRAG_SRC(ipr) ((ipr)->src)
+#define IPV6_FRAG_DEST(ipr) ((ipr)->dest)
+#else /* IPV6_FRAG_COPYHEADER */
+#define IPV6_FRAG_SRC(ipr) ((ipr)->iphdr->src)
+#define IPV6_FRAG_DEST(ipr) ((ipr)->iphdr->dest)
+#endif /* IPV6_FRAG_COPYHEADER */
+
+/** IPv6 reassembly helper struct.
+ * This is exported because memp needs to know the size.
+ */
+struct ip6_reassdata {
+  struct ip6_reassdata *next;
+  struct pbuf *p;
+  struct ip6_hdr *iphdr; /* pointer to the first (original) IPv6 header */
+#if IPV6_FRAG_COPYHEADER
+  ip6_addr_p_t src; /* copy of the source address in the IP header */
+  ip6_addr_p_t dest; /* copy of the destination address in the IP header */
+  /* This buffer (for the part of the original header that we overwrite) will
+   * be slightly oversized, but we cannot compute the exact size from here. */
+  u8_t orig_hdr[sizeof(struct ip6_frag_hdr) + sizeof(void*)];
+#else /* IPV6_FRAG_COPYHEADER */
+  /* In this case we still need the buffer, for sending ICMPv6 replies. */
+  u8_t orig_hdr[sizeof(struct ip6_frag_hdr)];
+#endif /* IPV6_FRAG_COPYHEADER */
+  u32_t identification;
+  u16_t datagram_len;
+  u8_t nexth;
+  u8_t timer;
+#if LWIP_IPV6_SCOPES
+  u8_t src_zone; /* zone of original packet's source address */
+  u8_t dest_zone; /* zone of original packet's destination address */
+#endif /* LWIP_IPV6_SCOPES */
+};
+
+#define ip6_reass_init() /* Compatibility define */
+void ip6_reass_tmr(void);
+struct pbuf *ip6_reass(struct pbuf *p);
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_FRAG  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
+#define LWIP_PBUF_CUSTOM_REF_DEFINED
+/** A custom pbuf that holds a reference to another pbuf, which is freed
+ * when this custom pbuf is freed. This is used to create a custom PBUF_REF
+ * that points into the original pbuf. */
+struct pbuf_custom_ref {
+  /** 'base class' */
+  struct pbuf_custom pc;
+  /** pointer to the original pbuf that is referenced */
+  struct pbuf *original;
+};
+#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
+
+err_t ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest);
+
+#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP6_FRAG_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_zone.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_zone.h
new file mode 100644
index 000000000..525790e67
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip6_zone.h
@@ -0,0 +1,304 @@
+/**
+ * @file
+ *
+ * IPv6 address scopes, zones, and scoping policy.
+ *
+ * This header provides the means to implement support for IPv6 address scopes,
+ * as per RFC 4007. An address scope can be either global or more constrained.
+ * In lwIP, we say that an address "has a scope" or "is scoped" when its scope
+ * is constrained, in which case the address is meaningful only in a specific
+ * "zone." For unicast addresses, only link-local addresses have a scope; in
+ * that case, the scope is the link. For multicast addresses, there are various
+ * scopes defined by RFC 4007 and others. For any constrained scope, a system
+ * must establish a (potentially one-to-many) mapping between zones and local
+ * interfaces. For example, a link-local address is valid on only one link (its
+ * zone). That link may be attached to one or more local interfaces. The
+ * decisions on which scopes are constrained and the mapping between zones and
+ * interfaces is together what we refer to as the "scoping policy" - more on
+ * this in a bit.
+ *
+ * In lwIP, each IPv6 address has an associated zone index. This zone index may
+ * be set to "no zone" (IP6_NO_ZONE, 0) or an actual zone. We say that an
+ * address "has a zone" or "is zoned" when its zone index is *not* set to "no
+ * zone." In lwIP, in principle, each address should be "properly zoned," which
+ * means that if the address has a zone if and only if has a scope. As such, it
+ * is a rule that an unscoped (e.g., global) address must never have a zone.
+ * Even though one could argue that there is always one zone even for global
+ * scopes, this rule exists for implementation simplicity. Violation of the
+ * rule will trigger assertions or otherwise result in undesired behavior.
+ *
+ * Backward compatibility prevents us from requiring that applications always
+ * provide properly zoned addresses. We do enforce the rule that the in the
+ * lwIP link layer (everything below netif->output_ip6() and in particular ND6)
+ * *all* addresses are properly zoned. Thus, on the output paths down the
+ * stack, various places deal with the case of addresses that lack a zone.
+ * Some of them are best-effort for efficiency (e.g. the PCB bind and connect
+ * API calls' attempts to add missing zones); ultimately the IPv6 output
+ * handler (@ref ip6_output_if_src) will set a zone if necessary.
+ *
+ * Aside from dealing with scoped addresses lacking a zone, a proper IPv6
+ * implementation must also ensure that a packet with a scoped source and/or
+ * destination address does not leave its zone. This is currently implemented
+ * in the input and forward functions. However, for output, these checks are
+ * deliberately omitted in order to keep the implementation lightweight. The
+ * routing algorithm in @ref ip6_route will take decisions such that it will
+ * not cause zone violations unless the application sets bad addresses, though.
+ *
+ * In terms of scoping policy, lwIP implements the default policy from RFC 4007
+ * using macros in this file. This policy considers link-local unicast
+ * addresses and (only) interface-local and link-local multicast addresses as
+ * having a scope. For all these addresses, the zone is equal to the interface.
+ * As shown below in this file, it is possible to implement a custom policy.
+ */
+
+/*
+ * Copyright (c) 2017 The MINIX 3 Project.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: David van Moolenbroek <david@minix3.org>
+ *
+ */
+#ifndef LWIP_HDR_IP6_ZONE_H
+#define LWIP_HDR_IP6_ZONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup ip6_zones IPv6 Zones
+ * @ingroup ip6
+ * @{
+ */
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+/** Identifier for "no zone". */
+#define IP6_NO_ZONE 0
+
+#if LWIP_IPV6_SCOPES
+
+/** Zone initializer for static IPv6 address initialization, including comma. */
+#define IPADDR6_ZONE_INIT , IP6_NO_ZONE
+
+/** Return the zone index of the given IPv6 address; possibly "no zone". */
+#define ip6_addr_zone(ip6addr) ((ip6addr)->zone)
+
+/** Does the given IPv6 address have a zone set? (0/1) */
+#define ip6_addr_has_zone(ip6addr) (ip6_addr_zone(ip6addr) != IP6_NO_ZONE)
+
+/** Set the zone field of an IPv6 address to a particular value. */
+#define ip6_addr_set_zone(ip6addr, zone_idx) ((ip6addr)->zone = (zone_idx))
+
+/** Clear the zone field of an IPv6 address, setting it to "no zone". */
+#define ip6_addr_clear_zone(ip6addr) ((ip6addr)->zone = IP6_NO_ZONE)
+
+/** Copy the zone field from the second IPv6 address to the first one. */
+#define ip6_addr_copy_zone(ip6addr1, ip6addr2) ((ip6addr1).zone = (ip6addr2).zone)
+
+/** Is the zone field of the given IPv6 address equal to the given zone index? (0/1) */
+#define ip6_addr_equals_zone(ip6addr, zone_idx) ((ip6addr)->zone == (zone_idx))
+
+/** Are the zone fields of the given IPv6 addresses equal? (0/1)
+ * This macro must only be used on IPv6 addresses of the same scope. */
+#define ip6_addr_cmp_zone(ip6addr1, ip6addr2) ((ip6addr1)->zone == (ip6addr2)->zone)
+
+/** Symbolic constants for the 'type' parameters in some of the macros.
+ * These exist for efficiency only, allowing the macros to avoid certain tests
+ * when the address is known not to be of a certain type. Dead code elimination
+ * will do the rest. IP6_MULTICAST is supported but currently not optimized.
+ * @see ip6_addr_has_scope, ip6_addr_assign_zone, ip6_addr_lacks_zone.
+ */
+enum lwip_ipv6_scope_type
+{
+  /** Unknown */
+  IP6_UNKNOWN   = 0,
+  /** Unicast */
+  IP6_UNICAST   = 1,
+  /** Multicast */
+  IP6_MULTICAST = 2
+};
+
+/** IPV6_CUSTOM_SCOPES: together, the following three macro definitions,
+ * @ref ip6_addr_has_scope, @ref ip6_addr_assign_zone, and
+ * @ref ip6_addr_test_zone, completely define the lwIP scoping policy.
+ * The definitions below implement the default policy from RFC 4007 Sec. 6.
+ * Should an implementation desire to implement a different policy, it can
+ * define IPV6_CUSTOM_SCOPES to 1 and supply its own definitions for the three
+ * macros instead.
+ */
+#ifndef IPV6_CUSTOM_SCOPES
+#define IPV6_CUSTOM_SCOPES 0
+#endif /* !IPV6_CUSTOM_SCOPES */
+
+#if !IPV6_CUSTOM_SCOPES
+
+/**
+ * Determine whether an IPv6 address has a constrained scope, and as such is
+ * meaningful only if accompanied by a zone index to identify the scope's zone.
+ * The given address type may be used to eliminate at compile time certain
+ * checks that will evaluate to false at run time anyway.
+ *
+ * This default implementation follows the default model of RFC 4007, where
+ * only interface-local and link-local scopes are defined.
+ *
+ * Even though the unicast loopback address does have an implied link-local
+ * scope, in this implementation it does not have an explicitly assigned zone
+ * index. As such it should not be tested for in this macro.
+ *
+ * @param ip6addr the IPv6 address (const); only its address part is examined.
+ * @param type address type; see @ref lwip_ipv6_scope_type.
+ * @return 1 if the address has a constrained scope, 0 if it does not.
+ */
+#define ip6_addr_has_scope(ip6addr, type) \
+  (ip6_addr_islinklocal(ip6addr) || (((type) != IP6_UNICAST) && \
+   (ip6_addr_ismulticast_iflocal(ip6addr) || \
+    ip6_addr_ismulticast_linklocal(ip6addr))))
+
+/**
+ * Assign a zone index to an IPv6 address, based on a network interface. If the
+ * given address has a scope, the assigned zone index is that scope's zone of
+ * the given netif; otherwise, the assigned zone index is "no zone".
+ *
+ * This default implementation follows the default model of RFC 4007, where
+ * only interface-local and link-local scopes are defined, and the zone index
+ * of both of those scopes always equals the index of the network interface.
+ * As such, this default implementation need not distinguish between different
+ * constrained scopes when assigning the zone.
+ *
+ * @param ip6addr the IPv6 address; its address part is examined, and its zone
+ *                index is assigned.
+ * @param type address type; see @ref lwip_ipv6_scope_type.
+ * @param netif the network interface (const).
+ */
+#define ip6_addr_assign_zone(ip6addr, type, netif) \
+    (ip6_addr_set_zone((ip6addr), \
+      ip6_addr_has_scope((ip6addr), (type)) ? netif_get_index(netif) : 0))
+
+/**
+ * Test whether an IPv6 address is "zone-compatible" with a network interface.
+ * That is, test whether the network interface is part of the zone associated
+ * with the address. For efficiency, this macro is only ever called if the
+ * given address is either scoped or zoned, and thus, it need not test this.
+ * If an address is scoped but not zoned, or zoned and not scoped, it is
+ * considered not zone-compatible with any netif.
+ *
+ * This default implementation follows the default model of RFC 4007, where
+ * only interface-local and link-local scopes are defined, and the zone index
+ * of both of those scopes always equals the index of the network interface.
+ * As such, there is always only one matching netif for a specific zone index,
+ * but all call sites of this macro currently support multiple matching netifs
+ * as well (at no additional expense in the common case).
+ *
+ * @param ip6addr the IPv6 address (const).
+ * @param netif the network interface (const).
+ * @return 1 if the address is scope-compatible with the netif, 0 if not.
+ */
+#define ip6_addr_test_zone(ip6addr, netif) \
+    (ip6_addr_equals_zone((ip6addr), netif_get_index(netif)))
+
+#endif /* !IPV6_CUSTOM_SCOPES */
+
+/** Does the given IPv6 address have a scope, and as such should also have a
+ * zone to be meaningful, but does not actually have a zone? (0/1) */
+#define ip6_addr_lacks_zone(ip6addr, type) \
+    (!ip6_addr_has_zone(ip6addr) && ip6_addr_has_scope((ip6addr), (type)))
+
+/**
+ * Try to select a zone for a scoped address that does not yet have a zone.
+ * Called from PCB bind and connect routines, for two reasons: 1) to save on
+ * this (relatively expensive) selection for every individual packet route
+ * operation and 2) to allow the application to obtain the selected zone from
+ * the PCB as is customary for e.g. getsockname/getpeername BSD socket calls.
+ *
+ * Ideally, callers would always supply a properly zoned address, in which case
+ * this function would not be needed. It exists both for compatibility with the
+ * BSD socket API (which accepts zoneless destination addresses) and for
+ * backward compatibility with pre-scoping lwIP code.
+ *
+ * It may be impossible to select a zone, e.g. if there are no netifs.  In that
+ * case, the address's zone field will be left as is.
+ *
+ * @param dest the IPv6 address for which to select and set a zone.
+ * @param src source IPv6 address (const); may be equal to dest.
+ */
+#define ip6_addr_select_zone(dest, src) do { struct netif *selected_netif; \
+  selected_netif = ip6_route((src), (dest)); \
+  if (selected_netif != NULL) { \
+    ip6_addr_assign_zone((dest), IP6_UNKNOWN, selected_netif); \
+  } } while (0)
+
+/**
+ * @}
+ */
+
+#else /* LWIP_IPV6_SCOPES */
+
+#define IPADDR6_ZONE_INIT
+#define ip6_addr_zone(ip6addr) (IP6_NO_ZONE)
+#define ip6_addr_has_zone(ip6addr) (0)
+#define ip6_addr_set_zone(ip6addr, zone_idx)
+#define ip6_addr_clear_zone(ip6addr)
+#define ip6_addr_copy_zone(ip6addr1, ip6addr2)
+#define ip6_addr_equals_zone(ip6addr, zone_idx) (1)
+#define ip6_addr_cmp_zone(ip6addr1, ip6addr2) (1)
+#define IPV6_CUSTOM_SCOPES 0
+#define ip6_addr_has_scope(ip6addr, type) (0)
+#define ip6_addr_assign_zone(ip6addr, type, netif)
+#define ip6_addr_test_zone(ip6addr, netif) (1)
+#define ip6_addr_lacks_zone(ip6addr, type) (0)
+#define ip6_addr_select_zone(ip6addr, src)
+
+#endif /* LWIP_IPV6_SCOPES */
+
+#if LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG
+
+/** Verify that the given IPv6 address is properly zoned. */
+#define IP6_ADDR_ZONECHECK(ip6addr) LWIP_ASSERT("IPv6 zone check failed", \
+    ip6_addr_has_scope(ip6addr, IP6_UNKNOWN) == ip6_addr_has_zone(ip6addr))
+
+/** Verify that the given IPv6 address is properly zoned for the given netif. */
+#define IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif) LWIP_ASSERT("IPv6 netif zone check failed", \
+    ip6_addr_has_scope(ip6addr, IP6_UNKNOWN) ? \
+    (ip6_addr_has_zone(ip6addr) && \
+     (((netif) == NULL) || ip6_addr_test_zone((ip6addr), (netif)))) : \
+    !ip6_addr_has_zone(ip6addr))
+
+#else /* LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG */
+
+#define IP6_ADDR_ZONECHECK(ip6addr)
+#define IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif)
+
+#endif /* LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG */
+
+#endif /* LWIP_IPV6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP6_ZONE_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip_addr.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip_addr.h
new file mode 100644
index 000000000..2f977709d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/ip_addr.h
@@ -0,0 +1,438 @@
+/**
+ * @file
+ * IP address API (common IPv4 and IPv6)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_IP_ADDR_H
+#define LWIP_HDR_IP_ADDR_H
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+
+#include "lwip/ip4_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup ipaddr
+ * IP address types for use in ip_addr_t.type member.
+ * @see tcp_new_ip_type(), udp_new_ip_type(), raw_new_ip_type().
+ */
+enum lwip_ip_addr_type {
+  /** IPv4 */
+  IPADDR_TYPE_V4 =   0U,
+  /** IPv6 */
+  IPADDR_TYPE_V6 =   6U,
+  /** IPv4+IPv6 ("dual-stack") */
+  IPADDR_TYPE_ANY = 46U
+};
+
+#if LWIP_IPV4 && LWIP_IPV6
+/**
+ * @ingroup ipaddr
+ * A union struct for both IP version's addresses.
+ * ATTENTION: watch out for its size when adding IPv6 address scope!
+ */
+typedef struct ip_addr {
+  union {
+    ip6_addr_t ip6;
+    ip4_addr_t ip4;
+  } u_addr;
+  /** @ref lwip_ip_addr_type */
+  u8_t type;
+} ip_addr_t;
+
+extern const ip_addr_t ip_addr_any_type;
+
+/** @ingroup ip4addr */
+#define IPADDR4_INIT(u32val)          { { { { u32val, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V4 }
+/** @ingroup ip4addr */
+#define IPADDR4_INIT_BYTES(a,b,c,d)   IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d)))
+
+/** @ingroup ip6addr */
+#define IPADDR6_INIT(a, b, c, d)      { { { { a, b, c, d } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V6 }
+/** @ingroup ip6addr */
+#define IPADDR6_INIT_HOST(a, b, c, d) { { { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V6 }
+
+/** @ingroup ipaddr */
+#define IP_IS_ANY_TYPE_VAL(ipaddr)    (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_ANY)
+/** @ingroup ipaddr */
+#define IPADDR_ANY_TYPE_INIT          { { { { 0ul, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_ANY }
+
+/** @ingroup ip4addr */
+#define IP_IS_V4_VAL(ipaddr)          (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4)
+/** @ingroup ip6addr */
+#define IP_IS_V6_VAL(ipaddr)          (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V6)
+/** @ingroup ip4addr */
+#define IP_IS_V4(ipaddr)              (((ipaddr) == NULL) || IP_IS_V4_VAL(*(ipaddr)))
+/** @ingroup ip6addr */
+#define IP_IS_V6(ipaddr)              (((ipaddr) != NULL) && IP_IS_V6_VAL(*(ipaddr)))
+
+#define IP_SET_TYPE_VAL(ipaddr, iptype) do { (ipaddr).type = (iptype); }while(0)
+#define IP_SET_TYPE(ipaddr, iptype)     do { if((ipaddr) != NULL) { IP_SET_TYPE_VAL(*(ipaddr), iptype); }}while(0)
+#define IP_GET_TYPE(ipaddr)           ((ipaddr)->type)
+
+#define IP_ADDR_RAW_SIZE(ipaddr)      (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4 ? sizeof(ip4_addr_t) : sizeof(ip6_addr_t))
+
+#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) (IP_GET_TYPE(&pcb->local_ip) == IP_GET_TYPE(ipaddr))
+#define IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr) (IP_IS_ANY_TYPE_VAL(pcb->local_ip) || IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr))
+
+/** @ingroup ip6addr
+ * Convert generic ip address to specific protocol version
+ */
+#define ip_2_ip6(ipaddr)   (&((ipaddr)->u_addr.ip6))
+/** @ingroup ip4addr
+ * Convert generic ip address to specific protocol version
+ */
+#define ip_2_ip4(ipaddr)   (&((ipaddr)->u_addr.ip4))
+
+/** @ingroup ip4addr */
+#define IP_ADDR4(ipaddr,a,b,c,d)      do { IP4_ADDR(ip_2_ip4(ipaddr),a,b,c,d); \
+                                           IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V4); } while(0)
+/** @ingroup ip6addr */
+#define IP_ADDR6(ipaddr,i0,i1,i2,i3)  do { IP6_ADDR(ip_2_ip6(ipaddr),i0,i1,i2,i3); \
+                                           IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V6); } while(0)
+/** @ingroup ip6addr */
+#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3)  IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3))
+
+#define ip_clear_no4(ipaddr)  do { ip_2_ip6(ipaddr)->addr[1] = \
+                                   ip_2_ip6(ipaddr)->addr[2] = \
+                                   ip_2_ip6(ipaddr)->addr[3] = 0; \
+                                   ip6_addr_clear_zone(ip_2_ip6(ipaddr)); }while(0)
+
+/** @ingroup ipaddr */
+#define ip_addr_copy(dest, src)      do{ IP_SET_TYPE_VAL(dest, IP_GET_TYPE(&src)); if(IP_IS_V6_VAL(src)){ \
+  ip6_addr_copy(*ip_2_ip6(&(dest)), *ip_2_ip6(&(src))); }else{ \
+  ip4_addr_copy(*ip_2_ip4(&(dest)), *ip_2_ip4(&(src))); ip_clear_no4(&dest); }}while(0)
+/** @ingroup ip6addr */
+#define ip_addr_copy_from_ip6(dest, src)      do{ \
+  ip6_addr_copy(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0)
+/** @ingroup ip6addr */
+#define ip_addr_copy_from_ip6_packed(dest, src)      do{ \
+  ip6_addr_copy_from_packed(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0)
+/** @ingroup ip4addr */
+#define ip_addr_copy_from_ip4(dest, src)      do{ \
+  ip4_addr_copy(*ip_2_ip4(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V4); ip_clear_no4(&dest); }while(0)
+/** @ingroup ip4addr */
+#define ip_addr_set_ip4_u32(ipaddr, val)  do{if(ipaddr){ip4_addr_set_u32(ip_2_ip4(ipaddr), val); \
+  IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ip4addr */
+#define ip_addr_set_ip4_u32_val(ipaddr, val)  do{ ip4_addr_set_u32(ip_2_ip4(&(ipaddr)), val); \
+  IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }while(0)
+/** @ingroup ip4addr */
+#define ip_addr_get_ip4_u32(ipaddr)  (((ipaddr) && IP_IS_V4(ipaddr)) ? \
+  ip4_addr_get_u32(ip_2_ip4(ipaddr)) : 0)
+/** @ingroup ipaddr */
+#define ip_addr_set(dest, src) do{ IP_SET_TYPE(dest, IP_GET_TYPE(src)); if(IP_IS_V6(src)){ \
+  ip6_addr_set(ip_2_ip6(dest), ip_2_ip6(src)); }else{ \
+  ip4_addr_set(ip_2_ip4(dest), ip_2_ip4(src)); ip_clear_no4(dest); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_ipaddr(dest, src) ip_addr_set(dest, src)
+/** @ingroup ipaddr */
+#define ip_addr_set_zero(ipaddr)     do{ \
+  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, 0); }while(0)
+/** @ingroup ip5addr */
+#define ip_addr_set_zero_ip4(ipaddr)     do{ \
+  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }while(0)
+/** @ingroup ip6addr */
+#define ip_addr_set_zero_ip6(ipaddr)     do{ \
+  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_any(is_ipv6, ipaddr)      do{if(is_ipv6){ \
+  ip6_addr_set_any(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_any(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_any_val(is_ipv6, ipaddr)      do{if(is_ipv6){ \
+  ip6_addr_set_any(ip_2_ip6(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_any(ip_2_ip4(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_loopback(is_ipv6, ipaddr) do{if(is_ipv6){ \
+  ip6_addr_set_loopback(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_loopback(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_loopback_val(is_ipv6, ipaddr) do{if(is_ipv6){ \
+  ip6_addr_set_loopback(ip_2_ip6(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_loopback(ip_2_ip4(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_set_hton(dest, src)  do{if(IP_IS_V6(src)){ \
+  ip6_addr_set_hton(ip_2_ip6(dest), ip_2_ip6(src)); IP_SET_TYPE(dest, IPADDR_TYPE_V6); }else{ \
+  ip4_addr_set_hton(ip_2_ip4(dest), ip_2_ip4(src)); IP_SET_TYPE(dest, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_get_network(target, host, netmask) do{if(IP_IS_V6(host)){ \
+  ip4_addr_set_zero(ip_2_ip4(target)); IP_SET_TYPE(target, IPADDR_TYPE_V6); } else { \
+  ip4_addr_get_network(ip_2_ip4(target), ip_2_ip4(host), ip_2_ip4(netmask)); IP_SET_TYPE(target, IPADDR_TYPE_V4); }}while(0)
+/** @ingroup ipaddr */
+#define ip_addr_netcmp(addr1, addr2, mask) ((IP_IS_V6(addr1) && IP_IS_V6(addr2)) ? \
+  0 : \
+  ip4_addr_netcmp(ip_2_ip4(addr1), ip_2_ip4(addr2), mask))
+/** @ingroup ipaddr */
+#define ip_addr_cmp(addr1, addr2)    ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \
+  ip6_addr_cmp(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \
+  ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2))))
+/** @ingroup ipaddr */
+#define ip_addr_cmp_zoneless(addr1, addr2)    ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \
+  ip6_addr_cmp_zoneless(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \
+  ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2))))
+/** @ingroup ipaddr */
+#define ip_addr_isany(ipaddr)        (((ipaddr) == NULL) ? 1 : ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_isany(ip_2_ip6(ipaddr)) : \
+  ip4_addr_isany(ip_2_ip4(ipaddr))))
+/** @ingroup ipaddr */
+#define ip_addr_isany_val(ipaddr)        ((IP_IS_V6_VAL(ipaddr)) ? \
+  ip6_addr_isany_val(*ip_2_ip6(&(ipaddr))) : \
+  ip4_addr_isany_val(*ip_2_ip4(&(ipaddr))))
+/** @ingroup ipaddr */
+#define ip_addr_isbroadcast(ipaddr, netif) ((IP_IS_V6(ipaddr)) ? \
+  0 : \
+  ip4_addr_isbroadcast(ip_2_ip4(ipaddr), netif))
+/** @ingroup ipaddr */
+#define ip_addr_ismulticast(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_ismulticast(ip_2_ip6(ipaddr)) : \
+  ip4_addr_ismulticast(ip_2_ip4(ipaddr)))
+/** @ingroup ipaddr */
+#define ip_addr_isloopback(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_isloopback(ip_2_ip6(ipaddr)) : \
+  ip4_addr_isloopback(ip_2_ip4(ipaddr)))
+/** @ingroup ipaddr */
+#define ip_addr_islinklocal(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
+  ip6_addr_islinklocal(ip_2_ip6(ipaddr)) : \
+  ip4_addr_islinklocal(ip_2_ip4(ipaddr)))
+#define ip_addr_debug_print(debug, ipaddr) do { if(IP_IS_V6(ipaddr)) { \
+  ip6_addr_debug_print(debug, ip_2_ip6(ipaddr)); } else { \
+  ip4_addr_debug_print(debug, ip_2_ip4(ipaddr)); }}while(0)
+#define ip_addr_debug_print_val(debug, ipaddr) do { if(IP_IS_V6_VAL(ipaddr)) { \
+  ip6_addr_debug_print_val(debug, *ip_2_ip6(&(ipaddr))); } else { \
+  ip4_addr_debug_print_val(debug, *ip_2_ip4(&(ipaddr))); }}while(0)
+char *ipaddr_ntoa(const ip_addr_t *addr);
+char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen);
+int ipaddr_aton(const char *cp, ip_addr_t *addr);
+
+/** @ingroup ipaddr */
+#define IPADDR_STRLEN_MAX   IP6ADDR_STRLEN_MAX
+
+/** @ingroup ipaddr */
+#define ip4_2_ipv4_mapped_ipv6(ip6addr, ip4addr) do { \
+  (ip6addr)->addr[3] = (ip4addr)->addr; \
+  (ip6addr)->addr[2] = PP_HTONL(0x0000FFFFUL); \
+  (ip6addr)->addr[1] = 0; \
+  (ip6addr)->addr[0] = 0; \
+  ip6_addr_clear_zone(ip6addr); } while(0);
+
+/** @ingroup ipaddr */
+#define unmap_ipv4_mapped_ipv6(ip4addr, ip6addr) \
+  (ip4addr)->addr = (ip6addr)->addr[3];
+
+#define IP46_ADDR_ANY(type) (((type) == IPADDR_TYPE_V6)? IP6_ADDR_ANY : IP4_ADDR_ANY)
+
+#else /* LWIP_IPV4 && LWIP_IPV6 */
+
+#define IP_ADDR_PCB_VERSION_MATCH(addr, pcb)          1
+#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr)  1
+
+#define ip_addr_set_any_val(is_ipv6, ipaddr)          ip_addr_set_any(is_ipv6, &(ipaddr))
+#define ip_addr_set_loopback_val(is_ipv6, ipaddr)     ip_addr_set_loopback(is_ipv6, &(ipaddr))
+
+#if LWIP_IPV4
+
+typedef ip4_addr_t ip_addr_t;
+#define IPADDR4_INIT(u32val)                    { u32val }
+#define IPADDR4_INIT_BYTES(a,b,c,d)             IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d)))
+#define IP_IS_V4_VAL(ipaddr)                    1
+#define IP_IS_V6_VAL(ipaddr)                    0
+#define IP_IS_V4(ipaddr)                        1
+#define IP_IS_V6(ipaddr)                        0
+#define IP_IS_ANY_TYPE_VAL(ipaddr)              0
+#define IP_SET_TYPE_VAL(ipaddr, iptype)
+#define IP_SET_TYPE(ipaddr, iptype)
+#define IP_GET_TYPE(ipaddr)                     IPADDR_TYPE_V4
+#define IP_ADDR_RAW_SIZE(ipaddr)                sizeof(ip4_addr_t)
+#define ip_2_ip4(ipaddr)                        (ipaddr)
+#define IP_ADDR4(ipaddr,a,b,c,d)                IP4_ADDR(ipaddr,a,b,c,d)
+
+#define ip_addr_copy(dest, src)                 ip4_addr_copy(dest, src)
+#define ip_addr_copy_from_ip4(dest, src)        ip4_addr_copy(dest, src)
+#define ip_addr_set_ip4_u32(ipaddr, val)        ip4_addr_set_u32(ip_2_ip4(ipaddr), val)
+#define ip_addr_set_ip4_u32_val(ipaddr, val)    ip_addr_set_ip4_u32(&(ipaddr), val)
+#define ip_addr_get_ip4_u32(ipaddr)             ip4_addr_get_u32(ip_2_ip4(ipaddr))
+#define ip_addr_set(dest, src)                  ip4_addr_set(dest, src)
+#define ip_addr_set_ipaddr(dest, src)           ip4_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr)                ip4_addr_set_zero(ipaddr)
+#define ip_addr_set_zero_ip4(ipaddr)            ip4_addr_set_zero(ipaddr)
+#define ip_addr_set_any(is_ipv6, ipaddr)        ip4_addr_set_any(ipaddr)
+#define ip_addr_set_loopback(is_ipv6, ipaddr)   ip4_addr_set_loopback(ipaddr)
+#define ip_addr_set_hton(dest, src)             ip4_addr_set_hton(dest, src)
+#define ip_addr_get_network(target, host, mask) ip4_addr_get_network(target, host, mask)
+#define ip_addr_netcmp(addr1, addr2, mask)      ip4_addr_netcmp(addr1, addr2, mask)
+#define ip_addr_cmp(addr1, addr2)               ip4_addr_cmp(addr1, addr2)
+#define ip_addr_isany(ipaddr)                   ip4_addr_isany(ipaddr)
+#define ip_addr_isany_val(ipaddr)               ip4_addr_isany_val(ipaddr)
+#define ip_addr_isloopback(ipaddr)              ip4_addr_isloopback(ipaddr)
+#define ip_addr_islinklocal(ipaddr)             ip4_addr_islinklocal(ipaddr)
+#define ip_addr_isbroadcast(addr, netif)        ip4_addr_isbroadcast(addr, netif)
+#define ip_addr_ismulticast(ipaddr)             ip4_addr_ismulticast(ipaddr)
+#define ip_addr_debug_print(debug, ipaddr)      ip4_addr_debug_print(debug, ipaddr)
+#define ip_addr_debug_print_val(debug, ipaddr)  ip4_addr_debug_print_val(debug, ipaddr)
+#define ipaddr_ntoa(ipaddr)                     ip4addr_ntoa(ipaddr)
+#define ipaddr_ntoa_r(ipaddr, buf, buflen)      ip4addr_ntoa_r(ipaddr, buf, buflen)
+#define ipaddr_aton(cp, addr)                   ip4addr_aton(cp, addr)
+
+#define IPADDR_STRLEN_MAX   IP4ADDR_STRLEN_MAX
+
+#define IP46_ADDR_ANY(type) (IP4_ADDR_ANY)
+
+#else /* LWIP_IPV4 */
+
+typedef ip6_addr_t ip_addr_t;
+#define IPADDR6_INIT(a, b, c, d)                { { a, b, c, d } IPADDR6_ZONE_INIT }
+#define IPADDR6_INIT_HOST(a, b, c, d)           { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } IPADDR6_ZONE_INIT }
+#define IP_IS_V4_VAL(ipaddr)                    0
+#define IP_IS_V6_VAL(ipaddr)                    1
+#define IP_IS_V4(ipaddr)                        0
+#define IP_IS_V6(ipaddr)                        1
+#define IP_IS_ANY_TYPE_VAL(ipaddr)              0
+#define IP_SET_TYPE_VAL(ipaddr, iptype)
+#define IP_SET_TYPE(ipaddr, iptype)
+#define IP_GET_TYPE(ipaddr)                     IPADDR_TYPE_V6
+#define IP_ADDR_RAW_SIZE(ipaddr)                sizeof(ip6_addr_t)
+#define ip_2_ip6(ipaddr)                        (ipaddr)
+#define IP_ADDR6(ipaddr,i0,i1,i2,i3)            IP6_ADDR(ipaddr,i0,i1,i2,i3)
+#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3)       IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3))
+
+#define ip_addr_copy(dest, src)                 ip6_addr_copy(dest, src)
+#define ip_addr_copy_from_ip6(dest, src)        ip6_addr_copy(dest, src)
+#define ip_addr_copy_from_ip6_packed(dest, src) ip6_addr_copy_from_packed(dest, src)
+#define ip_addr_set(dest, src)                  ip6_addr_set(dest, src)
+#define ip_addr_set_ipaddr(dest, src)           ip6_addr_set(dest, src)
+#define ip_addr_set_zero(ipaddr)                ip6_addr_set_zero(ipaddr)
+#define ip_addr_set_zero_ip6(ipaddr)            ip6_addr_set_zero(ipaddr)
+#define ip_addr_set_any(is_ipv6, ipaddr)        ip6_addr_set_any(ipaddr)
+#define ip_addr_set_loopback(is_ipv6, ipaddr)   ip6_addr_set_loopback(ipaddr)
+#define ip_addr_set_hton(dest, src)             ip6_addr_set_hton(dest, src)
+#define ip_addr_get_network(target, host, mask) ip6_addr_set_zero(target)
+#define ip_addr_netcmp(addr1, addr2, mask)      0
+#define ip_addr_cmp(addr1, addr2)               ip6_addr_cmp(addr1, addr2)
+#define ip_addr_cmp_zoneless(addr1, addr2)      ip6_addr_cmp_zoneless(addr1, addr2)
+#define ip_addr_isany(ipaddr)                   ip6_addr_isany(ipaddr)
+#define ip_addr_isany_val(ipaddr)               ip6_addr_isany_val(ipaddr)
+#define ip_addr_isloopback(ipaddr)              ip6_addr_isloopback(ipaddr)
+#define ip_addr_islinklocal(ipaddr)             ip6_addr_islinklocal(ipaddr)
+#define ip_addr_isbroadcast(addr, netif)        0
+#define ip_addr_ismulticast(ipaddr)             ip6_addr_ismulticast(ipaddr)
+#define ip_addr_debug_print(debug, ipaddr)      ip6_addr_debug_print(debug, ipaddr)
+#define ip_addr_debug_print_val(debug, ipaddr)  ip6_addr_debug_print_val(debug, ipaddr)
+#define ipaddr_ntoa(ipaddr)                     ip6addr_ntoa(ipaddr)
+#define ipaddr_ntoa_r(ipaddr, buf, buflen)      ip6addr_ntoa_r(ipaddr, buf, buflen)
+#define ipaddr_aton(cp, addr)                   ip6addr_aton(cp, addr)
+
+#define IPADDR_STRLEN_MAX   IP6ADDR_STRLEN_MAX
+
+#define IP46_ADDR_ANY(type) (IP6_ADDR_ANY)
+
+#endif /* LWIP_IPV4 */
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+
+#if LWIP_IPV4
+
+extern const ip_addr_t ip_addr_any;
+extern const ip_addr_t ip_addr_broadcast;
+
+/**
+ * @ingroup ip4addr
+ * Can be used as a fixed/const ip_addr_t
+ * for the IP wildcard.
+ * Defined to @ref IP4_ADDR_ANY when IPv4 is enabled.
+ * Defined to @ref IP6_ADDR_ANY in IPv6 only systems.
+ * Use this if you can handle IPv4 _AND_ IPv6 addresses.
+ * Use @ref IP4_ADDR_ANY or @ref IP6_ADDR_ANY when the IP
+ * type matters.
+ */
+#define IP_ADDR_ANY         IP4_ADDR_ANY
+/**
+ * @ingroup ip4addr
+ * Can be used as a fixed/const ip_addr_t
+ * for the IPv4 wildcard and the broadcast address
+ */
+#define IP4_ADDR_ANY        (&ip_addr_any)
+/**
+ * @ingroup ip4addr
+ * Can be used as a fixed/const ip4_addr_t
+ * for the wildcard and the broadcast address
+ */
+#define IP4_ADDR_ANY4       (ip_2_ip4(&ip_addr_any))
+
+/** @ingroup ip4addr */
+#define IP_ADDR_BROADCAST   (&ip_addr_broadcast)
+/** @ingroup ip4addr */
+#define IP4_ADDR_BROADCAST  (ip_2_ip4(&ip_addr_broadcast))
+
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+
+extern const ip_addr_t ip6_addr_any;
+
+/** 
+ * @ingroup ip6addr
+ * IP6_ADDR_ANY can be used as a fixed ip_addr_t
+ * for the IPv6 wildcard address
+ */
+#define IP6_ADDR_ANY   (&ip6_addr_any)
+/**
+ * @ingroup ip6addr
+ * IP6_ADDR_ANY6 can be used as a fixed ip6_addr_t
+ * for the IPv6 wildcard address
+ */
+#define IP6_ADDR_ANY6  (ip_2_ip6(&ip6_addr_any))
+
+#if !LWIP_IPV4
+/** IPv6-only configurations */
+#define IP_ADDR_ANY IP6_ADDR_ANY
+#endif /* !LWIP_IPV4 */
+
+#endif
+
+#if LWIP_IPV4 && LWIP_IPV6
+/** @ingroup ipaddr */
+#define IP_ANY_TYPE    (&ip_addr_any_type)
+#else
+#define IP_ANY_TYPE    IP_ADDR_ANY
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/mem.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/mem.h
new file mode 100644
index 000000000..ff208d25c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/mem.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ * Heap API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_MEM_H
+#define LWIP_HDR_MEM_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if MEM_LIBC_MALLOC
+
+#include "lwip/arch.h"
+
+typedef size_t mem_size_t;
+#define MEM_SIZE_F SZT_F
+
+#elif MEM_USE_POOLS
+
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+
+#else
+
+/* MEM_SIZE would have to be aligned, but using 64000 here instead of
+ * 65535 leaves some room for alignment...
+ */
+#if MEM_SIZE > 64000L
+typedef u32_t mem_size_t;
+#define MEM_SIZE_F U32_F
+#else
+typedef u16_t mem_size_t;
+#define MEM_SIZE_F U16_F
+#endif /* MEM_SIZE > 64000 */
+#endif
+
+void  mem_init(void);
+void *mem_trim(void *mem, mem_size_t size);
+void *mem_malloc(mem_size_t size);
+void *mem_calloc(mem_size_t count, mem_size_t size);
+void  mem_free(void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEM_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/memp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/memp.h
new file mode 100644
index 000000000..1630b26c2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/memp.h
@@ -0,0 +1,155 @@
+/**
+ * @file
+ * Memory pool API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef LWIP_HDR_MEMP_H
+#define LWIP_HDR_MEMP_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* run once with empty definition to handle all custom includes in lwippools.h */
+#define LWIP_MEMPOOL(name,num,size,desc)
+#include "lwip/priv/memp_std.h"
+
+/** Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
+typedef enum {
+#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_##name,
+#include "lwip/priv/memp_std.h"
+  MEMP_MAX
+} memp_t;
+
+#include "lwip/priv/memp_priv.h"
+#include "lwip/stats.h"
+
+extern const struct memp_desc* const memp_pools[MEMP_MAX];
+
+/**
+ * @ingroup mempool
+ * Declare prototype for private memory pool if it is used in multiple files
+ */
+#define LWIP_MEMPOOL_PROTOTYPE(name) extern const struct memp_desc memp_ ## name
+
+#if MEMP_MEM_MALLOC
+
+#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
+  LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \
+  const struct memp_desc memp_ ## name = { \
+    DECLARE_LWIP_MEMPOOL_DESC(desc) \
+    LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \
+    LWIP_MEM_ALIGN_SIZE(size) \
+  };
+
+#else /* MEMP_MEM_MALLOC */
+
+/**
+ * @ingroup mempool
+ * Declare a private memory pool
+ * Private mempools example:
+ * .h: only when pool is used in multiple .c files: LWIP_MEMPOOL_PROTOTYPE(my_private_pool);
+ * .c:
+ *   - in global variables section: LWIP_MEMPOOL_DECLARE(my_private_pool, 10, sizeof(foo), "Some description")
+ *   - call ONCE before using pool (e.g. in some init() function): LWIP_MEMPOOL_INIT(my_private_pool);
+ *   - allocate: void* my_new_mem = LWIP_MEMPOOL_ALLOC(my_private_pool);
+ *   - free: LWIP_MEMPOOL_FREE(my_private_pool, my_new_mem);
+ *
+ * To relocate a pool, declare it as extern in cc.h. Example for GCC:
+ *   extern u8_t \_\_attribute\_\_((section(".onchip_mem"))) memp_memory_my_private_pool_base[];
+ */
+#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
+  LWIP_DECLARE_MEMORY_ALIGNED(memp_memory_ ## name ## _base, ((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))); \
+    \
+  LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \
+    \
+  static struct memp *memp_tab_ ## name; \
+    \
+  const struct memp_desc memp_ ## name = { \
+    DECLARE_LWIP_MEMPOOL_DESC(desc) \
+    LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \
+    LWIP_MEM_ALIGN_SIZE(size), \
+    (num), \
+    memp_memory_ ## name ## _base, \
+    &memp_tab_ ## name \
+  };
+
+#endif /* MEMP_MEM_MALLOC */
+
+/**
+ * @ingroup mempool
+ * Initialize a private memory pool
+ */
+#define LWIP_MEMPOOL_INIT(name)    memp_init_pool(&memp_ ## name)
+/**
+ * @ingroup mempool
+ * Allocate from a private memory pool
+ */
+#define LWIP_MEMPOOL_ALLOC(name)   memp_malloc_pool(&memp_ ## name)
+/**
+ * @ingroup mempool
+ * Free element from a private memory pool
+ */
+#define LWIP_MEMPOOL_FREE(name, x) memp_free_pool(&memp_ ## name, (x))
+
+#if MEM_USE_POOLS
+/** This structure is used to save the pool one element came from.
+ * This has to be defined here as it is required for pool size calculation. */
+struct memp_malloc_helper
+{
+   memp_t poolnr;
+#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS)
+   u16_t size;
+#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */
+};
+#endif /* MEM_USE_POOLS */
+
+void  memp_init(void);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_fn(memp_t type, const char* file, const int line);
+#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
+#else
+void *memp_malloc(memp_t type);
+#endif
+void  memp_free(memp_t type, void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/mld6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/mld6.h
new file mode 100644
index 000000000..7fa0797f2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/mld6.h
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710.
+ * No support for MLDv2.
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_MLD6_H
+#define LWIP_HDR_MLD6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6_MLD && LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MLD group */
+struct mld_group {
+  /** next link */
+  struct mld_group *next;
+  /** multicast address */
+  ip6_addr_t         group_address;
+  /** signifies we were the last person to report */
+  u8_t               last_reporter_flag;
+  /** current state of the group */
+  u8_t               group_state;
+  /** timer for reporting */
+  u16_t              timer;
+  /** counter of simultaneous uses */
+  u8_t               use;
+};
+
+#define MLD6_TMR_INTERVAL              100 /* Milliseconds */
+
+err_t  mld6_stop(struct netif *netif);
+void   mld6_report_groups(struct netif *netif);
+void   mld6_tmr(void);
+struct mld_group *mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr);
+void   mld6_input(struct pbuf *p, struct netif *inp);
+err_t  mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
+err_t  mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
+err_t  mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
+err_t  mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
+
+/** @ingroup mld6
+ * Get list head of MLD6 groups for netif.
+ * Note: The allnodes group IP is NOT in the list, since it must always 
+ * be received for correct IPv6 operation.
+ * @see @ref netif_set_mld_mac_filter()
+ */
+#define netif_mld6_data(netif) ((struct mld_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6_MLD && LWIP_IPV6 */
+
+#endif /* LWIP_HDR_MLD6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/nd6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/nd6.h
new file mode 100644
index 000000000..c30e624f0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/nd6.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ *
+ * Neighbor discovery and stateless address autoconfiguration for IPv6.
+ * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
+ * (Address autoconfiguration).
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_ND6_H
+#define LWIP_HDR_ND6_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip6_addr.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 second period */
+#define ND6_TMR_INTERVAL 1000
+
+/** Router solicitations are sent in 4 second intervals (see RFC 4861, ch. 6.3.7) */
+#ifndef ND6_RTR_SOLICITATION_INTERVAL
+#define ND6_RTR_SOLICITATION_INTERVAL  4000
+#endif
+
+struct pbuf;
+struct netif;
+
+void nd6_tmr(void);
+void nd6_input(struct pbuf *p, struct netif *inp);
+void nd6_clear_destination_cache(void);
+struct netif *nd6_find_route(const ip6_addr_t *ip6addr);
+err_t nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp);
+u16_t nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif);
+#if LWIP_ND6_TCP_REACHABILITY_HINTS
+void nd6_reachability_hint(const ip6_addr_t *ip6addr);
+#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */
+void nd6_cleanup_netif(struct netif *netif);
+#if LWIP_IPV6_MLD
+void nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state);
+#endif /* LWIP_IPV6_MLD */
+void nd6_restart_netif(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_ND6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netbuf.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netbuf.h
new file mode 100644
index 000000000..42a911bca
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netbuf.h
@@ -0,0 +1,116 @@
+/**
+ * @file
+ * netbuf API (for netconn API)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_NETBUF_H
+#define LWIP_HDR_NETBUF_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This netbuf has dest-addr/port set */
+#define NETBUF_FLAG_DESTADDR    0x01
+/** This netbuf includes a checksum */
+#define NETBUF_FLAG_CHKSUM      0x02
+
+/** "Network buffer" - contains data and addressing info */
+struct netbuf {
+  struct pbuf *p, *ptr;
+  ip_addr_t addr;
+  u16_t port;
+#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY
+  u8_t flags;
+  u16_t toport_chksum;
+#if LWIP_NETBUF_RECVINFO
+  ip_addr_t toaddr;
+#endif /* LWIP_NETBUF_RECVINFO */
+#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+err_t             netbuf_ref      (struct netbuf *buf,
+                                   const void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head, struct netbuf *tail);
+
+err_t             netbuf_data     (struct netbuf *buf,
+                                   void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+
+#define netbuf_copy_partial(buf, dataptr, len, offset) \
+  pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
+#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
+#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len)
+#define netbuf_len(buf)              ((buf)->p->tot_len)
+#define netbuf_fromaddr(buf)         (&((buf)->addr))
+#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set(&((buf)->addr), fromaddr)
+#define netbuf_fromport(buf)         ((buf)->port)
+#if LWIP_NETBUF_RECVINFO
+#define netbuf_destaddr(buf)         (&((buf)->toaddr))
+#define netbuf_set_destaddr(buf, destaddr) ip_addr_set(&((buf)->toaddr), destaddr)
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_destport(buf)         (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0)
+#else /* LWIP_CHECKSUM_ON_COPY */
+#define netbuf_destport(buf)         ((buf)->toport_chksum)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+#endif /* LWIP_NETBUF_RECVINFO */
+#if LWIP_CHECKSUM_ON_COPY
+#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \
+                                            (buf)->toport_chksum = chksum; } while(0)
+#endif /* LWIP_CHECKSUM_ON_COPY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#endif /* LWIP_HDR_NETBUF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netdb.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netdb.h
new file mode 100644
index 000000000..d3d15dfac
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netdb.h
@@ -0,0 +1,150 @@
+/**
+ * @file
+ * NETDB API (sockets)
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_NETDB_H
+#define LWIP_HDR_NETDB_H
+
+#include "lwip/opt.h"
+
+#if LWIP_DNS && LWIP_SOCKET
+
+#include "lwip/arch.h"
+#include "lwip/inet.h"
+#include "lwip/sockets.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* some rarely used options */
+#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
+#define LWIP_DNS_API_DECLARE_H_ERRNO  1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_ERRORS
+#define LWIP_DNS_API_DEFINE_ERRORS    1
+#endif
+
+#ifndef LWIP_DNS_API_DEFINE_FLAGS
+#define LWIP_DNS_API_DEFINE_FLAGS     1
+#endif
+
+#ifndef LWIP_DNS_API_DECLARE_STRUCTS
+#define LWIP_DNS_API_DECLARE_STRUCTS  1
+#endif
+
+#if LWIP_DNS_API_DEFINE_ERRORS
+/** Errors used by the DNS API functions, h_errno can be one of them */
+#define EAI_NONAME      200
+#define EAI_SERVICE     201
+#define EAI_FAIL        202
+#define EAI_MEMORY      203
+#define EAI_FAMILY      204
+
+#define HOST_NOT_FOUND  210
+#define NO_DATA         211
+#define NO_RECOVERY     212
+#define TRY_AGAIN       213
+#endif /* LWIP_DNS_API_DEFINE_ERRORS */
+
+#if LWIP_DNS_API_DEFINE_FLAGS
+/* input flags for struct addrinfo */
+#define AI_PASSIVE      0x01
+#define AI_CANONNAME    0x02
+#define AI_NUMERICHOST  0x04
+#define AI_NUMERICSERV  0x08
+#define AI_V4MAPPED     0x10
+#define AI_ALL          0x20
+#define AI_ADDRCONFIG   0x40
+#endif /* LWIP_DNS_API_DEFINE_FLAGS */
+
+#if LWIP_DNS_API_DECLARE_STRUCTS
+struct hostent {
+    char  *h_name;      /* Official name of the host. */
+    char **h_aliases;   /* A pointer to an array of pointers to alternative host names,
+                           terminated by a null pointer. */
+    int    h_addrtype;  /* Address type. */
+    int    h_length;    /* The length, in bytes, of the address. */
+    char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
+                           network byte order) for the host, terminated by a null pointer. */
+#define h_addr h_addr_list[0] /* for backward compatibility */
+};
+
+struct addrinfo {
+    int               ai_flags;      /* Input flags. */
+    int               ai_family;     /* Address family of socket. */
+    int               ai_socktype;   /* Socket type. */
+    int               ai_protocol;   /* Protocol of socket. */
+    socklen_t         ai_addrlen;    /* Length of socket address. */
+    struct sockaddr  *ai_addr;       /* Socket address of socket. */
+    char             *ai_canonname;  /* Canonical name of service location. */
+    struct addrinfo  *ai_next;       /* Pointer to next in list. */
+};
+#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
+
+#define NETDB_ELEM_SIZE           (sizeof(struct addrinfo) + sizeof(struct sockaddr_storage) + DNS_MAX_NAME_LENGTH + 1)
+
+#if LWIP_DNS_API_DECLARE_H_ERRNO
+/* application accessible error code set by the DNS API functions */
+extern int h_errno;
+#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
+
+struct hostent *lwip_gethostbyname(const char *name);
+int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
+                size_t buflen, struct hostent **result, int *h_errnop);
+void lwip_freeaddrinfo(struct addrinfo *ai);
+int lwip_getaddrinfo(const char *nodename,
+       const char *servname,
+       const struct addrinfo *hints,
+       struct addrinfo **res);
+
+#if LWIP_COMPAT_SOCKETS
+/** @ingroup netdbapi */
+#define gethostbyname(name) lwip_gethostbyname(name)
+/** @ingroup netdbapi */
+#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
+       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
+/** @ingroup netdbapi */
+#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
+/** @ingroup netdbapi */
+#define getaddrinfo(nodname, servname, hints, res) \
+       lwip_getaddrinfo(nodname, servname, hints, res)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_DNS && LWIP_SOCKET */
+
+#endif /* LWIP_HDR_NETDB_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netif.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netif.h
new file mode 100644
index 000000000..911196ab3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netif.h
@@ -0,0 +1,669 @@
+/**
+ * @file
+ * netif API (to be used from TCPIP thread)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_NETIF_H
+#define LWIP_HDR_NETIF_H
+
+#include "lwip/opt.h"
+
+#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF)
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Throughout this file, IP addresses are expected to be in
+ * the same byte order as in IP_PCB. */
+
+/** Must be the maximum of all used hardware address lengths
+    across all types of interfaces in use.
+    This does not have to be changed, normally. */
+#ifndef NETIF_MAX_HWADDR_LEN
+#define NETIF_MAX_HWADDR_LEN 6U
+#endif
+
+/** The size of a fully constructed netif name which the
+ * netif can be identified by in APIs. Composed of
+ * 2 chars, 3 (max) digits, and 1 \0
+ */
+#define NETIF_NAMESIZE 6
+
+/**
+ * @defgroup netif_flags Flags
+ * @ingroup netif
+ * @{
+ */
+
+/** Whether the network interface is 'up'. This is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ * It must be set by the startup code before this netif can be used
+ * (also for dhcp/autoip).
+ */
+#define NETIF_FLAG_UP           0x01U
+/** If set, the netif has broadcast capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_BROADCAST    0x02U
+/** If set, the interface has an active link
+ *  (set by the network interface driver).
+ * Either set by the netif driver in its init function (if the link
+ * is up at that time) or at a later point once the link comes up
+ * (if link detection is supported by the hardware). */
+#define NETIF_FLAG_LINK_UP      0x04U
+/** If set, the netif is an ethernet device using ARP.
+ * Set by the netif driver in its init function.
+ * Used to check input packet types and use of DHCP. */
+#define NETIF_FLAG_ETHARP       0x08U
+/** If set, the netif is an ethernet device. It might not use
+ * ARP or TCP/IP if it is used for PPPoE only.
+ */
+#define NETIF_FLAG_ETHERNET     0x10U
+/** If set, the netif has IGMP capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_IGMP         0x20U
+/** If set, the netif has MLD6 capability.
+ * Set by the netif driver in its init function. */
+#define NETIF_FLAG_MLD6         0x40U
+
+/**
+ * @}
+ */
+
+enum lwip_internal_netif_client_data_index
+{
+#if LWIP_IPV4
+#if LWIP_DHCP
+   LWIP_NETIF_CLIENT_DATA_INDEX_DHCP,
+#endif
+#if LWIP_AUTOIP
+   LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP,
+#endif
+#if LWIP_IGMP
+   LWIP_NETIF_CLIENT_DATA_INDEX_IGMP,
+#endif
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+#if LWIP_IPV6_DHCP6
+   LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6,
+#endif
+#if LWIP_IPV6_MLD
+   LWIP_NETIF_CLIENT_DATA_INDEX_MLD6,
+#endif
+#endif /* LWIP_IPV6 */
+   LWIP_NETIF_CLIENT_DATA_INDEX_MAX
+};
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define NETIF_CHECKSUM_GEN_IP       0x0001
+#define NETIF_CHECKSUM_GEN_UDP      0x0002
+#define NETIF_CHECKSUM_GEN_TCP      0x0004
+#define NETIF_CHECKSUM_GEN_ICMP     0x0008
+#define NETIF_CHECKSUM_GEN_ICMP6    0x0010
+#define NETIF_CHECKSUM_CHECK_IP     0x0100
+#define NETIF_CHECKSUM_CHECK_UDP    0x0200
+#define NETIF_CHECKSUM_CHECK_TCP    0x0400
+#define NETIF_CHECKSUM_CHECK_ICMP   0x0800
+#define NETIF_CHECKSUM_CHECK_ICMP6  0x1000
+#define NETIF_CHECKSUM_ENABLE_ALL   0xFFFF
+#define NETIF_CHECKSUM_DISABLE_ALL  0x0000
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+
+struct netif;
+
+/** MAC Filter Actions, these are passed to a netif's igmp_mac_filter or
+ * mld_mac_filter callback function. */
+enum netif_mac_filter_action {
+  /** Delete a filter entry */
+  NETIF_DEL_MAC_FILTER = 0,
+  /** Add a filter entry */
+  NETIF_ADD_MAC_FILTER = 1
+};
+
+/** Function prototype for netif init functions. Set up flags and output/linkoutput
+ * callback functions in this function.
+ *
+ * @param netif The netif to initialize
+ */
+typedef err_t (*netif_init_fn)(struct netif *netif);
+/** Function prototype for netif->input functions. This function is saved as 'input'
+ * callback function in the netif struct. Call it when a packet has been received.
+ *
+ * @param p The received packet, copied into a pbuf
+ * @param inp The netif which received the packet
+ * @return ERR_OK if the packet was handled
+ *         != ERR_OK is the packet was NOT handled, in this case, the caller has
+ *                   to free the pbuf
+ */
+typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp);
+
+#if LWIP_IPV4
+/** Function prototype for netif->output functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'etharp_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IP address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p,
+       const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4*/
+
+#if LWIP_IPV6
+/** Function prototype for netif->output_ip6 functions. Called by lwIP when a packet
+ * shall be sent. For ethernet netif, set this to 'ethip6_output' and set
+ * 'linkoutput'.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (p->payload points to IP header)
+ * @param ipaddr The IPv6 address to which the packet shall be sent
+ */
+typedef err_t (*netif_output_ip6_fn)(struct netif *netif, struct pbuf *p,
+       const ip6_addr_t *ipaddr);
+#endif /* LWIP_IPV6 */
+
+/** Function prototype for netif->linkoutput functions. Only used for ethernet
+ * netifs. This function is called by ARP when a packet shall be sent.
+ *
+ * @param netif The netif which shall send a packet
+ * @param p The packet to send (raw ethernet packet)
+ */
+typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p);
+/** Function prototype for netif status- or link-callback functions. */
+typedef void (*netif_status_callback_fn)(struct netif *netif);
+#if LWIP_IPV4 && LWIP_IGMP
+/** Function prototype for netif igmp_mac_filter functions */
+typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif,
+       const ip4_addr_t *group, enum netif_mac_filter_action action);
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+/** Function prototype for netif mld_mac_filter functions */
+typedef err_t (*netif_mld_mac_filter_fn)(struct netif *netif,
+       const ip6_addr_t *group, enum netif_mac_filter_action action);
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+#if LWIP_DHCP || LWIP_AUTOIP || LWIP_IGMP || LWIP_IPV6_MLD || LWIP_IPV6_DHCP6 || (LWIP_NUM_NETIF_CLIENT_DATA > 0)
+#if LWIP_NUM_NETIF_CLIENT_DATA > 0
+u8_t netif_alloc_client_data_id(void);
+#endif
+/** @ingroup netif_cd
+ * Set client data. Obtain ID from netif_alloc_client_data_id().
+ */
+#define netif_set_client_data(netif, id, data) netif_get_client_data(netif, id) = (data)
+/** @ingroup netif_cd
+ * Get client data. Obtain ID from netif_alloc_client_data_id().
+ */
+#define netif_get_client_data(netif, id)       (netif)->client_data[(id)]
+#endif
+
+#if (LWIP_IPV4 && LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) || (LWIP_IPV6 && (LWIP_ND6_NUM_DESTINATIONS > 0x7f))
+typedef u16_t netif_addr_idx_t;
+#define NETIF_ADDR_IDX_MAX 0x7FFF
+#else
+typedef u8_t netif_addr_idx_t;
+#define NETIF_ADDR_IDX_MAX 0x7F
+#endif
+
+#if LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_USE_HINTS              1
+struct netif_hint {
+  netif_addr_idx_t addr_hint;
+};
+#else /* LWIP_NETIF_HWADDRHINT */
+#define LWIP_NETIF_USE_HINTS              0
+#endif /* LWIP_NETIF_HWADDRHINT */
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+struct netif {
+#if !LWIP_SINGLE_NETIF
+  /** pointer to next in linked list */
+  struct netif *next;
+#endif
+
+#if LWIP_IPV4
+  /** IP address configuration in network byte order */
+  ip_addr_t ip_addr;
+  ip_addr_t netmask;
+  ip_addr_t gw;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  /** Array of IPv6 addresses for this netif. */
+  ip_addr_t ip6_addr[LWIP_IPV6_NUM_ADDRESSES];
+  /** The state of each IPv6 address (Tentative, Preferred, etc).
+   * @see ip6_addr.h */
+  u8_t ip6_addr_state[LWIP_IPV6_NUM_ADDRESSES];
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+  /** Remaining valid and preferred lifetime of each IPv6 address, in seconds.
+   * For valid lifetimes, the special value of IP6_ADDR_LIFE_STATIC (0)
+   * indicates the address is static and has no lifetimes. */
+  u32_t ip6_addr_valid_life[LWIP_IPV6_NUM_ADDRESSES];
+  u32_t ip6_addr_pref_life[LWIP_IPV6_NUM_ADDRESSES];
+#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
+#endif /* LWIP_IPV6 */
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  netif_input_fn input;
+#if LWIP_IPV4
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet.
+   *  For ethernet physical layer, this is usually etharp_output() */
+  netif_output_fn output;
+#endif /* LWIP_IPV4 */
+  /** This function is called by ethernet_output() when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  netif_linkoutput_fn linkoutput;
+#if LWIP_IPV6
+  /** This function is called by the IPv6 module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet.
+   *  For ethernet physical layer, this is usually ethip6_output() */
+  netif_output_ip6_fn output_ip6;
+#endif /* LWIP_IPV6 */
+#if LWIP_NETIF_STATUS_CALLBACK
+  /** This function is called when the netif state is set to up or down
+   */
+  netif_status_callback_fn status_callback;
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_LINK_CALLBACK
+  /** This function is called when the netif link is set to up or down
+   */
+  netif_status_callback_fn link_callback;
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+#if LWIP_NETIF_REMOVE_CALLBACK
+  /** This function is called when the netif has been removed */
+  netif_status_callback_fn remove_callback;
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#ifdef netif_get_client_data
+  void* client_data[LWIP_NETIF_CLIENT_DATA_INDEX_MAX + LWIP_NUM_NETIF_CLIENT_DATA];
+#endif
+#if LWIP_NETIF_HOSTNAME
+  /* the hostname for this netif, NULL is a valid value */
+  const char*  hostname;
+#endif /* LWIP_NETIF_HOSTNAME */
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+  u16_t chksum_flags;
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+#if LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES
+  /** maximum transfer unit (in bytes), updated by RA */
+  u16_t mtu6;
+#endif /* LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES */
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** flags (@see @ref netif_flags) */
+  u8_t flags;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface. Used for @ref if_api and @ref netifapi_netif, 
+   * as well as for IPv6 zones */
+  u8_t num;
+#if LWIP_IPV6_AUTOCONFIG
+  /** is this netif enabled for IPv6 autoconfiguration */
+  u8_t ip6_autoconfig_enabled;
+#endif /* LWIP_IPV6_AUTOCONFIG */
+#if LWIP_IPV6_SEND_ROUTER_SOLICIT
+  /** Number of Router Solicitation messages that remain to be sent. */
+  u8_t rs_count;
+#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
+#if MIB2_STATS
+  /** link type (from "snmp_ifType" enum from snmp_mib2.h) */
+  u8_t link_type;
+  /** (estimate) link speed */
+  u32_t link_speed;
+  /** timestamp at last change made (up/down) */
+  u32_t ts;
+  /** counters */
+  struct stats_mib2_netif_ctrs mib2_counters;
+#endif /* MIB2_STATS */
+#if LWIP_IPV4 && LWIP_IGMP
+  /** This function could be called to add or delete an entry in the multicast
+      filter table of the ethernet MAC.*/
+  netif_igmp_mac_filter_fn igmp_mac_filter;
+#endif /* LWIP_IPV4 && LWIP_IGMP */
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+  /** This function could be called to add or delete an entry in the IPv6 multicast
+      filter table of the ethernet MAC. */
+  netif_mld_mac_filter_fn mld_mac_filter;
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+#if LWIP_NETIF_USE_HINTS
+  struct netif_hint *hints;
+#endif /* LWIP_NETIF_USE_HINTS */
+#if ENABLE_LOOPBACK
+  /* List of packets to be queued for ourselves. */
+  struct pbuf *loop_first;
+  struct pbuf *loop_last;
+#if LWIP_LOOPBACK_MAX_PBUFS
+  u16_t loop_cnt_current;
+#endif /* LWIP_LOOPBACK_MAX_PBUFS */
+#endif /* ENABLE_LOOPBACK */
+};
+
+#if LWIP_CHECKSUM_CTRL_PER_NETIF
+#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) do { \
+  (netif)->chksum_flags = chksumflags; } while(0)
+#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) if (((netif) == NULL) || (((netif)->chksum_flags & (chksumflag)) != 0))
+#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags)
+#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag)
+#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
+
+#if LWIP_SINGLE_NETIF
+#define NETIF_FOREACH(netif) if (((netif) = netif_default) != NULL)
+#else /* LWIP_SINGLE_NETIF */
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+#define NETIF_FOREACH(netif) for ((netif) = netif_list; (netif) != NULL; (netif) = (netif)->next)
+#endif /* LWIP_SINGLE_NETIF */
+/** The default network interface. */
+extern struct netif *netif_default;
+
+void netif_init(void);
+
+struct netif *netif_add_noaddr(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input);
+
+#if LWIP_IPV4
+struct netif *netif_add(struct netif *netif,
+                            const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+                            void *state, netif_init_fn init, netif_input_fn input);
+void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
+                    const ip4_addr_t *gw);
+#else /* LWIP_IPV4 */
+struct netif *netif_add(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input);
+#endif /* LWIP_IPV4 */
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(const char *name);
+
+void netif_set_default(struct netif *netif);
+
+#if LWIP_IPV4
+void netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr);
+void netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask);
+void netif_set_gw(struct netif *netif, const ip4_addr_t *gw);
+/** @ingroup netif_ip4 */
+#define netif_ip4_addr(netif)    ((const ip4_addr_t*)ip_2_ip4(&((netif)->ip_addr)))
+/** @ingroup netif_ip4 */
+#define netif_ip4_netmask(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->netmask)))
+/** @ingroup netif_ip4 */
+#define netif_ip4_gw(netif)      ((const ip4_addr_t*)ip_2_ip4(&((netif)->gw)))
+/** @ingroup netif_ip4 */
+#define netif_ip_addr4(netif)    ((const ip_addr_t*)&((netif)->ip_addr))
+/** @ingroup netif_ip4 */
+#define netif_ip_netmask4(netif) ((const ip_addr_t*)&((netif)->netmask))
+/** @ingroup netif_ip4 */
+#define netif_ip_gw4(netif)      ((const ip_addr_t*)&((netif)->gw))
+#endif /* LWIP_IPV4 */
+
+#define netif_set_flags(netif, set_flags)     do { (netif)->flags = (u8_t)((netif)->flags |  (set_flags)); } while(0)
+#define netif_clear_flags(netif, clr_flags)   do { (netif)->flags = (u8_t)((netif)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define netif_is_flag_set(nefif, flag)        (((netif)->flags & (flag)) != 0)
+
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+/** @ingroup netif
+ * Ask if an interface is up
+ */
+#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_STATUS_CALLBACK
+void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback);
+#endif /* LWIP_NETIF_STATUS_CALLBACK */
+#if LWIP_NETIF_REMOVE_CALLBACK
+void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback);
+#endif /* LWIP_NETIF_REMOVE_CALLBACK */
+
+void netif_set_link_up(struct netif *netif);
+void netif_set_link_down(struct netif *netif);
+/** Ask if a link is up */
+#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0)
+
+#if LWIP_NETIF_LINK_CALLBACK
+void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback);
+#endif /* LWIP_NETIF_LINK_CALLBACK */
+
+#if LWIP_NETIF_HOSTNAME
+/** @ingroup netif */
+#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0)
+/** @ingroup netif */
+#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL)
+#endif /* LWIP_NETIF_HOSTNAME */
+
+#if LWIP_IGMP
+/** @ingroup netif */
+#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0)
+#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL)
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+/** @ingroup netif */
+#define netif_set_mld_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->mld_mac_filter = function; }}while(0)
+#define netif_get_mld_mac_filter(netif) (((netif) != NULL) ? ((netif)->mld_mac_filter) : NULL)
+#define netif_mld_mac_filter(netif, addr, action) do { if((netif) && (netif)->mld_mac_filter) { (netif)->mld_mac_filter((netif), (addr), (action)); }}while(0)
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+#if ENABLE_LOOPBACK
+err_t netif_loop_output(struct netif *netif, struct pbuf *p);
+void netif_poll(struct netif *netif);
+#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
+void netif_poll_all(void);
+#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
+#endif /* ENABLE_LOOPBACK */
+
+err_t netif_input(struct pbuf *p, struct netif *inp);
+
+#if LWIP_IPV6
+/** @ingroup netif_ip6 */
+#define netif_ip_addr6(netif, i)  ((const ip_addr_t*)(&((netif)->ip6_addr[i])))
+/** @ingroup netif_ip6 */
+#define netif_ip6_addr(netif, i)  ((const ip6_addr_t*)ip_2_ip6(&((netif)->ip6_addr[i])))
+void netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6);
+void netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3);
+#define netif_ip6_addr_state(netif, i)  ((netif)->ip6_addr_state[i])
+void netif_ip6_addr_set_state(struct netif* netif, s8_t addr_idx, u8_t state);
+s8_t netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr);
+void netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit);
+err_t netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx);
+#define netif_set_ip6_autoconfig_enabled(netif, action) do { if(netif) { (netif)->ip6_autoconfig_enabled = (action); }}while(0)
+#if LWIP_IPV6_ADDRESS_LIFETIMES
+#define netif_ip6_addr_valid_life(netif, i)  \
+    (((netif) != NULL) ? ((netif)->ip6_addr_valid_life[i]) : IP6_ADDR_LIFE_STATIC)
+#define netif_ip6_addr_set_valid_life(netif, i, secs) \
+    do { if (netif != NULL) { (netif)->ip6_addr_valid_life[i] = (secs); }} while (0)
+#define netif_ip6_addr_pref_life(netif, i)  \
+    (((netif) != NULL) ? ((netif)->ip6_addr_pref_life[i]) : IP6_ADDR_LIFE_STATIC)
+#define netif_ip6_addr_set_pref_life(netif, i, secs) \
+    do { if (netif != NULL) { (netif)->ip6_addr_pref_life[i] = (secs); }} while (0)
+#define netif_ip6_addr_isstatic(netif, i)  \
+    (netif_ip6_addr_valid_life((netif), (i)) == IP6_ADDR_LIFE_STATIC)
+#else /* !LWIP_IPV6_ADDRESS_LIFETIMES */
+#define netif_ip6_addr_isstatic(netif, i)  (1) /* all addresses are static */
+#endif /* !LWIP_IPV6_ADDRESS_LIFETIMES */
+#if LWIP_ND6_ALLOW_RA_UPDATES
+#define netif_mtu6(netif) ((netif)->mtu6)
+#else /* LWIP_ND6_ALLOW_RA_UPDATES */
+#define netif_mtu6(netif) ((netif)->mtu)
+#endif /* LWIP_ND6_ALLOW_RA_UPDATES */
+#endif /* LWIP_IPV6 */
+
+#if LWIP_NETIF_USE_HINTS
+#define NETIF_SET_HINTS(netif, netifhint)  (netif)->hints = (netifhint)
+#define NETIF_RESET_HINTS(netif)      (netif)->hints = NULL
+#else /* LWIP_NETIF_USE_HINTS */
+#define NETIF_SET_HINTS(netif, netifhint)
+#define NETIF_RESET_HINTS(netif)
+#endif /* LWIP_NETIF_USE_HINTS */
+
+u8_t netif_name_to_index(const char *name);
+char * netif_index_to_name(u8_t idx, char *name);
+struct netif* netif_get_by_index(u8_t idx);
+
+/* Interface indexes always start at 1 per RFC 3493, section 4, num starts at 0 (internal index is 0..254)*/
+#define netif_get_index(netif)      ((u8_t)((netif)->num + 1))
+#define NETIF_NO_INDEX              (0)
+
+/**
+ * @ingroup netif
+ * Extended netif status callback (NSC) reasons flags.
+ * May be extended in the future!
+ */
+typedef u16_t netif_nsc_reason_t;
+
+/* used for initialization only */
+#define LWIP_NSC_NONE                     0x0000
+/** netif was added. arg: NULL. Called AFTER netif was added. */
+#define LWIP_NSC_NETIF_ADDED              0x0001
+/** netif was removed. arg: NULL. Called BEFORE netif is removed. */
+#define LWIP_NSC_NETIF_REMOVED            0x0002
+/** link changed */
+#define LWIP_NSC_LINK_CHANGED             0x0004
+/** netif administrative status changed.\n
+  * up is called AFTER netif is set up.\n
+  * down is called BEFORE the netif is actually set down. */
+#define LWIP_NSC_STATUS_CHANGED           0x0008
+/** IPv4 address has changed */
+#define LWIP_NSC_IPV4_ADDRESS_CHANGED     0x0010
+/** IPv4 gateway has changed */
+#define LWIP_NSC_IPV4_GATEWAY_CHANGED     0x0020
+/** IPv4 netmask has changed */
+#define LWIP_NSC_IPV4_NETMASK_CHANGED     0x0040
+/** called AFTER IPv4 address/gateway/netmask changes have been applied */
+#define LWIP_NSC_IPV4_SETTINGS_CHANGED    0x0080
+/** IPv6 address was added */
+#define LWIP_NSC_IPV6_SET                 0x0100
+/** IPv6 address state has changed */
+#define LWIP_NSC_IPV6_ADDR_STATE_CHANGED  0x0200
+
+/** @ingroup netif
+ * Argument supplied to netif_ext_callback_fn.
+ */
+typedef union
+{
+  /** Args to LWIP_NSC_LINK_CHANGED callback */
+  struct link_changed_s
+  {
+    /** 1: up; 0: down */
+    u8_t state;
+  } link_changed;
+  /** Args to LWIP_NSC_STATUS_CHANGED callback */
+  struct status_changed_s
+  {
+    /** 1: up; 0: down */
+    u8_t state;
+  } status_changed;
+  /** Args to LWIP_NSC_IPV4_ADDRESS_CHANGED|LWIP_NSC_IPV4_GATEWAY_CHANGED|LWIP_NSC_IPV4_NETMASK_CHANGED|LWIP_NSC_IPV4_SETTINGS_CHANGED callback */
+  struct ipv4_changed_s
+  {
+    /** Old IPv4 address */
+    const ip_addr_t* old_address;
+    const ip_addr_t* old_netmask;
+    const ip_addr_t* old_gw;
+  } ipv4_changed;
+  /** Args to LWIP_NSC_IPV6_SET callback */
+  struct ipv6_set_s
+  {
+    /** Index of changed IPv6 address */
+    s8_t addr_index;
+    /** Old IPv6 address */
+    const ip_addr_t* old_address;
+  } ipv6_set;
+  /** Args to LWIP_NSC_IPV6_ADDR_STATE_CHANGED callback */
+  struct ipv6_addr_state_changed_s
+  {
+    /** Index of affected IPv6 address */
+    s8_t addr_index;
+    /** Old IPv6 address state */
+    u8_t old_state;
+    /** Affected IPv6 address */
+    const ip_addr_t* address;
+  } ipv6_addr_state_changed;
+} netif_ext_callback_args_t;
+
+/**
+ * @ingroup netif
+ * Function used for extended netif status callbacks
+ * Note: When parsing reason argument, keep in mind that more reasons may be added in the future!
+ * @param netif netif that is affected by change
+ * @param reason change reason
+ * @param args depends on reason, see reason description
+ */
+typedef void (*netif_ext_callback_fn)(struct netif* netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t* args);
+
+#if LWIP_NETIF_EXT_STATUS_CALLBACK
+struct netif_ext_callback;
+typedef struct netif_ext_callback
+{
+  netif_ext_callback_fn callback_fn;
+  struct netif_ext_callback* next;
+} netif_ext_callback_t;
+
+#define NETIF_DECLARE_EXT_CALLBACK(name) static netif_ext_callback_t name;
+void netif_add_ext_callback(netif_ext_callback_t* callback, netif_ext_callback_fn fn);
+void netif_remove_ext_callback(netif_ext_callback_t* callback);
+void netif_invoke_ext_callback(struct netif* netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t* args);
+#else
+#define NETIF_DECLARE_EXT_CALLBACK(name)
+#define netif_add_ext_callback(callback, fn)
+#define netif_remove_ext_callback(callback)
+#define netif_invoke_ext_callback(netif, reason, args)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netifapi.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netifapi.h
new file mode 100644
index 000000000..e0631791b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/netifapi.h
@@ -0,0 +1,161 @@
+/**
+ * @file
+ * netif API (to be used from non-TCPIP threads)
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+#ifndef LWIP_HDR_NETIFAPI_H
+#define LWIP_HDR_NETIFAPI_H
+
+#include "lwip/opt.h"
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/dhcp.h"
+#include "lwip/autoip.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "lwip/priv/api_msg.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* API for application */
+#if LWIP_ARP && LWIP_IPV4
+/* Used for netfiapi_arp_* APIs */
+enum netifapi_arp_entry {
+  NETIFAPI_ARP_PERM /* Permanent entry */
+  /* Other entry types can be added here */
+};
+
+/** @ingroup netifapi_arp */
+err_t netifapi_arp_add(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, enum netifapi_arp_entry type);
+/** @ingroup netifapi_arp */
+err_t netifapi_arp_remove(const ip4_addr_t *ipaddr, enum netifapi_arp_entry type);
+#endif /* LWIP_ARP && LWIP_IPV4 */
+
+err_t netifapi_netif_add(struct netif *netif,
+#if LWIP_IPV4
+                         const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
+#endif /* LWIP_IPV4 */
+                         void *state, netif_init_fn init, netif_input_fn input);
+
+#if LWIP_IPV4
+err_t netifapi_netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr,
+                              const ip4_addr_t *netmask, const ip4_addr_t *gw);
+#endif /* LWIP_IPV4*/
+
+err_t netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc,
+                            netifapi_errt_fn errtfunc);
+
+/** @ingroup netifapi_netif */
+err_t netifapi_netif_name_to_index(const char *name, u8_t *index);
+/** @ingroup netifapi_netif */
+err_t netifapi_netif_index_to_name(u8_t index, char *name);
+
+/** @ingroup netifapi_netif
+  * @see netif_remove()
+  */
+#define netifapi_netif_remove(n)        netifapi_netif_common(n, netif_remove, NULL)
+/** @ingroup netifapi_netif
+  * @see netif_set_up()
+  */
+#define netifapi_netif_set_up(n)        netifapi_netif_common(n, netif_set_up, NULL)
+/** @ingroup netifapi_netif
+  * @see netif_set_down()
+  */
+#define netifapi_netif_set_down(n)      netifapi_netif_common(n, netif_set_down, NULL)
+/** @ingroup netifapi_netif
+  * @see netif_set_default()
+  */
+#define netifapi_netif_set_default(n)   netifapi_netif_common(n, netif_set_default, NULL)
+/** @ingroup netifapi_netif
+  * @see netif_set_link_up()
+  */
+#define netifapi_netif_set_link_up(n)   netifapi_netif_common(n, netif_set_link_up, NULL)
+/** @ingroup netifapi_netif
+  * @see netif_set_link_down()
+  */
+#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL)
+
+/**
+ * @defgroup netifapi_dhcp4 DHCPv4
+ * @ingroup netifapi
+ * To be called from non-TCPIP threads
+ */
+/** @ingroup netifapi_dhcp4
+  * @see dhcp_start()
+  */
+#define netifapi_dhcp_start(n)            netifapi_netif_common(n, NULL, dhcp_start)
+/**
+ * @ingroup netifapi_dhcp4
+ * @deprecated Use netifapi_dhcp_release_and_stop() instead.
+ */
+#define netifapi_dhcp_stop(n)             netifapi_netif_common(n, dhcp_stop, NULL)
+/** @ingroup netifapi_dhcp4
+  * @see dhcp_inform()
+  */
+#define netifapi_dhcp_inform(n)           netifapi_netif_common(n, dhcp_inform, NULL)
+/** @ingroup netifapi_dhcp4
+  * @see dhcp_renew()
+  */
+#define netifapi_dhcp_renew(n)            netifapi_netif_common(n, NULL, dhcp_renew)
+/**
+ * @ingroup netifapi_dhcp4
+ * @deprecated Use netifapi_dhcp_release_and_stop() instead.
+ */
+#define netifapi_dhcp_release(n)          netifapi_netif_common(n, NULL, dhcp_release)
+/** @ingroup netifapi_dhcp4
+  * @see dhcp_release_and_stop()
+  */
+#define netifapi_dhcp_release_and_stop(n) netifapi_netif_common(n, dhcp_release_and_stop, NULL)
+
+/**
+ * @defgroup netifapi_autoip AUTOIP
+ * @ingroup netifapi
+ * To be called from non-TCPIP threads
+ */
+/** @ingroup netifapi_autoip
+  * @see autoip_start()
+  */
+#define netifapi_autoip_start(n)      netifapi_netif_common(n, NULL, autoip_start)
+/** @ingroup netifapi_autoip
+  * @see autoip_stop()
+  */
+#define netifapi_autoip_stop(n)       netifapi_netif_common(n, NULL, autoip_stop)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_NETIF_API */
+
+#endif /* LWIP_HDR_NETIFAPI_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/opt.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/opt.h
new file mode 100644
index 000000000..82c420c16
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/opt.h
@@ -0,0 +1,3519 @@
+/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/*
+ * NOTE: || defined __DOXYGEN__ is a workaround for doxygen bug -
+ * without this, doxygen does not see the actual #define
+ */
+
+#if !defined LWIP_HDR_OPT_H
+#define LWIP_HDR_OPT_H
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you don't like!
+ */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/**
+ * @defgroup lwip_opts Options (lwipopts.h)
+ * @ingroup lwip
+ *
+ * @defgroup lwip_opts_debug Debugging
+ * @ingroup lwip_opts
+ *
+ * @defgroup lwip_opts_infrastructure Infrastructure
+ * @ingroup lwip_opts
+ *
+ * @defgroup lwip_opts_callback Callback-style APIs
+ * @ingroup lwip_opts
+ *
+ * @defgroup lwip_opts_threadsafe_apis Thread-safe APIs
+ * @ingroup lwip_opts
+ */
+
+ /*
+   ------------------------------------
+   -------------- NO SYS --------------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_nosys NO_SYS
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * NO_SYS==1: Use lwIP without OS-awareness (no thread, semaphores, mutexes or
+ * mboxes). This means threaded APIs cannot be used (socket, netconn,
+ * i.e. everything in the 'api' folder), only the callback-style raw API is
+ * available (and you have to watch out for yourself that you don't access
+ * lwIP functions/structures from more than one context at a time!)
+ */
+#if !defined NO_SYS || defined __DOXYGEN__
+#define NO_SYS                          0
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_timers Timers
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_TIMERS==0: Drop support for sys_timeout and lwip-internal cyclic timers.
+ * (the array of lwip-internal cyclic timers is still provided)
+ * (check NO_SYS_NO_TIMERS for compatibility to old versions)
+ */
+#if !defined LWIP_TIMERS || defined __DOXYGEN__
+#ifdef NO_SYS_NO_TIMERS
+#define LWIP_TIMERS                     (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS))
+#else
+#define LWIP_TIMERS                     1
+#endif
+#endif
+
+/**
+ * LWIP_TIMERS_CUSTOM==1: Provide your own timer implementation.
+ * Function prototypes in timeouts.h and the array of lwip-internal cyclic timers
+ * are still included, but the implementation is not. The following functions
+ * will be required: sys_timeouts_init(), sys_timeout(), sys_untimeout(),
+ *                   sys_timeouts_mbox_fetch()
+ */
+#if !defined LWIP_TIMERS_CUSTOM || defined __DOXYGEN__
+#define LWIP_TIMERS_CUSTOM              0
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_memcpy memcpy
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#if !defined MEMCPY || defined __DOXYGEN__
+#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#if !defined SMEMCPY || defined __DOXYGEN__
+#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
+#endif
+
+/**
+ * MEMMOVE: override this if you have a faster implementation at hand than the
+ * one included in your C library.  lwIP currently uses MEMMOVE only when IPv6
+ * fragmentation support is enabled.
+ */
+#if !defined MEMMOVE || defined __DOXYGEN__
+#define MEMMOVE(dst,src,len)            memmove(dst,src,len)
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------
+   ----------- Core locking -----------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_lock Core locking and MPU
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_MPU_COMPATIBLE: enables special memory management mechanism
+ * which makes lwip able to work on MPU (Memory Protection Unit) system
+ * by not passing stack-pointers to other threads
+ * (this decreases performance as memory is allocated from pools instead
+ * of keeping it on the stack)
+ */
+#if !defined LWIP_MPU_COMPATIBLE || defined __DOXYGEN__
+#define LWIP_MPU_COMPATIBLE             0
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING
+ * Creates a global mutex that is held during TCPIP thread operations.
+ * Can be locked by client code to perform lwIP operations without changing
+ * into TCPIP thread using callbacks. See LOCK_TCPIP_CORE() and
+ * UNLOCK_TCPIP_CORE().
+ * Your system should provide mutexes supporting priority inversion to use this.
+ */
+#if !defined LWIP_TCPIP_CORE_LOCKING || defined __DOXYGEN__
+#define LWIP_TCPIP_CORE_LOCKING         1
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING_INPUT: when LWIP_TCPIP_CORE_LOCKING is enabled,
+ * this lets tcpip_input() grab the mutex for input packets as well,
+ * instead of allocating a message and passing it to tcpip_thread.
+ *
+ * ATTENTION: this does not work when tcpip_input() is called from
+ * interrupt context!
+ */
+#if !defined LWIP_TCPIP_CORE_LOCKING_INPUT || defined __DOXYGEN__
+#define LWIP_TCPIP_CORE_LOCKING_INPUT   0
+#endif
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: enable inter-task protection (and task-vs-interrupt
+ * protection) for certain critical regions during buffer allocation, deallocation
+ * and memory allocation and deallocation.
+ * ATTENTION: This is required when using lwIP from more than one context! If
+ * you disable this, you must be sure what you are doing!
+ */
+#if !defined SYS_LIGHTWEIGHT_PROT || defined __DOXYGEN__
+#define SYS_LIGHTWEIGHT_PROT            1
+#endif
+
+/**
+ * Macro/function to check whether lwIP's threading/locking
+ * requirements are satisfied during current function call.
+ * This macro usually calls a function that is implemented in the OS-dependent
+ * sys layer and performs the following checks:
+ * - Not in ISR (this should be checked for NO_SYS==1, too!)
+ * - If @ref LWIP_TCPIP_CORE_LOCKING = 1: TCPIP core lock is held
+ * - If @ref LWIP_TCPIP_CORE_LOCKING = 0: function is called from TCPIP thread
+ * @see @ref multithreading
+ */
+#if !defined LWIP_ASSERT_CORE_LOCKED || defined __DOXYGEN__
+#define LWIP_ASSERT_CORE_LOCKED()
+#endif
+
+/**
+ * Called as first thing in the lwIP TCPIP thread. Can be used in conjunction
+ * with @ref LWIP_ASSERT_CORE_LOCKED to check core locking.
+ * @see @ref multithreading
+ */
+#if !defined LWIP_MARK_TCPIP_THREAD || defined __DOXYGEN__
+#define LWIP_MARK_TCPIP_THREAD()
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------
+   ---------- Memory options ----------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_mem Heap and memory pools
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#if !defined MEM_LIBC_MALLOC || defined __DOXYGEN__
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/**
+ * MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+ * Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+ * speed (heap alloc can be much slower than pool alloc) and usage from interrupts
+ * (especially if your netif driver allocates PBUF_POOL pbufs for received frames
+ * from interrupt)!
+ * ATTENTION: Currently, this uses the heap for ALL pools (also for private pools,
+ * not only for internal pools defined in memp_std.h)!
+ */
+#if !defined MEMP_MEM_MALLOC || defined __DOXYGEN__
+#define MEMP_MEM_MALLOC                 0
+#endif
+
+/**
+ * MEMP_MEM_INIT==1: Force use of memset to initialize pool memory.
+ * Useful if pool are moved in uninitialized section of memory. This will ensure
+ * default values in pcbs struct are well initialized in all conditions.
+ */
+#if !defined MEMP_MEM_INIT || defined __DOXYGEN__
+#define MEMP_MEM_INIT                   0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ *    4 byte alignment -> \#define MEM_ALIGNMENT 4
+ *    2 byte alignment -> \#define MEM_ALIGNMENT 2
+ */
+#if !defined MEM_ALIGNMENT || defined __DOXYGEN__
+#define MEM_ALIGNMENT                   1
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#if !defined MEM_SIZE || defined __DOXYGEN__
+#define MEM_SIZE                        1600
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ *    MEMP_OVERFLOW_CHECK == 0 no checking
+ *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ *      memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#if !defined MEMP_OVERFLOW_CHECK || defined __DOXYGEN__
+#define MEMP_OVERFLOW_CHECK             0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#if !defined MEMP_SANITY_CHECK || defined __DOXYGEN__
+#define MEMP_SANITY_CHECK               0
+#endif
+
+/**
+ * MEM_OVERFLOW_CHECK: mem overflow protection reserves a configurable
+ * amount of bytes before and after each heap allocation chunk and fills
+ * it with a prominent default value.
+ *    MEM_OVERFLOW_CHECK == 0 no checking
+ *    MEM_OVERFLOW_CHECK == 1 checks each element when it is freed
+ *    MEM_OVERFLOW_CHECK >= 2 checks all heap elements every time
+ *      mem_malloc() or mem_free() is called (useful but slow!)
+ */
+#if !defined MEM_OVERFLOW_CHECK || defined __DOXYGEN__
+#define MEM_OVERFLOW_CHECK              0
+#endif
+
+/**
+ * MEM_SANITY_CHECK==1: run a sanity check after each mem_free() to make
+ * sure that the linked list of heap elements is not corrupted.
+ */
+#if !defined MEM_SANITY_CHECK || defined __DOXYGEN__
+#define MEM_SANITY_CHECK                0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#if !defined MEM_USE_POOLS || defined __DOXYGEN__
+#define MEM_USE_POOLS                   0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#if !defined MEM_USE_POOLS_TRY_BIGGER_POOL || defined __DOXYGEN__
+#define MEM_USE_POOLS_TRY_BIGGER_POOL   0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your
+ * include path somewhere.
+ */
+#if !defined MEMP_USE_CUSTOM_POOLS || defined __DOXYGEN__
+#define MEMP_USE_CUSTOM_POOLS           0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#if !defined LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT || defined __DOXYGEN__
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------------------
+   ---------- Internal Memory Pool Sizes ----------
+   ------------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_memp Internal memory pools
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#if !defined MEMP_NUM_PBUF || defined __DOXYGEN__
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#if !defined MEMP_NUM_RAW_PCB || defined __DOXYGEN__
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#if !defined MEMP_NUM_UDP_PCB || defined __DOXYGEN__
+#define MEMP_NUM_UDP_PCB                4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#if !defined MEMP_NUM_TCP_PCB || defined __DOXYGEN__
+#define MEMP_NUM_TCP_PCB                5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#if !defined MEMP_NUM_TCP_PCB_LISTEN || defined __DOXYGEN__
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#if !defined MEMP_NUM_TCP_SEG || defined __DOXYGEN__
+#define MEMP_NUM_TCP_SEG                16
+#endif
+
+/**
+ * MEMP_NUM_ALTCP_PCB: the number of simultaneously active altcp layer pcbs.
+ * (requires the LWIP_ALTCP option)
+ * Connections with multiple layers require more than one altcp_pcb (e.g. TLS
+ * over TCP requires 2 altcp_pcbs, one for TLS and one for TCP).
+ */
+#if !defined MEMP_NUM_ALTCP_PCB || defined __DOXYGEN__
+#define MEMP_NUM_ALTCP_PCB              MEMP_NUM_TCP_PCB
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#if !defined MEMP_NUM_REASSDATA || defined __DOXYGEN__
+#define MEMP_NUM_REASSDATA              5
+#endif
+
+/**
+ * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
+ * (fragments, not whole packets!).
+ * This is only used with LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1
+ * with DMA-enabled MACs where the packet is not yet sent when netif->output
+ * returns.
+ */
+#if !defined MEMP_NUM_FRAG_PBUF || defined __DOXYGEN__
+#define MEMP_NUM_FRAG_PBUF              15
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#if !defined MEMP_NUM_ARP_QUEUE || defined __DOXYGEN__
+#define MEMP_NUM_ARP_QUEUE              30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members at the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#if !defined MEMP_NUM_IGMP_GROUP || defined __DOXYGEN__
+#define MEMP_NUM_IGMP_GROUP             8
+#endif
+
+/**
+ * The number of sys timeouts used by the core stack (not apps)
+ * The default number of timeouts is calculated here for all enabled modules.
+ */
+#define LWIP_NUM_SYS_TIMEOUT_INTERNAL   (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_NUM_TIMEOUTS + (LWIP_IPV6 * (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD)))
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts.
+ * The default number of timeouts is calculated here for all enabled modules.
+ * The formula expects settings to be either '0' or '1'.
+ */
+#if !defined MEMP_NUM_SYS_TIMEOUT || defined __DOXYGEN__
+#define MEMP_NUM_SYS_TIMEOUT            LWIP_NUM_SYS_TIMEOUT_INTERNAL
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#if !defined MEMP_NUM_NETBUF || defined __DOXYGEN__
+#define MEMP_NUM_NETBUF                 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#if !defined MEMP_NUM_NETCONN || defined __DOXYGEN__
+#define MEMP_NUM_NETCONN                4
+#endif
+
+/**
+ * MEMP_NUM_SELECT_CB: the number of struct lwip_select_cb.
+ * (Only needed if you have LWIP_MPU_COMPATIBLE==1 and use the socket API.
+ * In that case, you need one per thread calling lwip_select.)
+ */
+#if !defined MEMP_NUM_SELECT_CB || defined __DOXYGEN__
+#define MEMP_NUM_SELECT_CB              4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication.
+ * (only needed if you use tcpip.c)
+ */
+#if !defined MEMP_NUM_TCPIP_MSG_API || defined __DOXYGEN__
+#define MEMP_NUM_TCPIP_MSG_API          8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets.
+ * (only needed if you use tcpip.c)
+ */
+#if !defined MEMP_NUM_TCPIP_MSG_INPKT || defined __DOXYGEN__
+#define MEMP_NUM_TCPIP_MSG_INPKT        8
+#endif
+
+/**
+ * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
+ * (before freeing the corresponding memory using lwip_freeaddrinfo()).
+ */
+#if !defined MEMP_NUM_NETDB || defined __DOXYGEN__
+#define MEMP_NUM_NETDB                  1
+#endif
+
+/**
+ * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
+ * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
+ */
+#if !defined MEMP_NUM_LOCALHOSTLIST || defined __DOXYGEN__
+#define MEMP_NUM_LOCALHOSTLIST          1
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
+ */
+#if !defined PBUF_POOL_SIZE || defined __DOXYGEN__
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/** MEMP_NUM_API_MSG: the number of concurrently active calls to various
+ * socket, netconn, and tcpip functions
+ */
+#if !defined MEMP_NUM_API_MSG || defined __DOXYGEN__
+#define MEMP_NUM_API_MSG                MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname
+ */
+#if !defined MEMP_NUM_DNS_API_MSG || defined __DOXYGEN__
+#define MEMP_NUM_DNS_API_MSG            MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls
+ * to getsockopt/setsockopt
+ */
+#if !defined MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA || defined __DOXYGEN__
+#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API
+#endif
+
+/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the
+ * netifapi functions
+ */
+#if !defined MEMP_NUM_NETIFAPI_MSG || defined __DOXYGEN__
+#define MEMP_NUM_NETIFAPI_MSG           MEMP_NUM_TCPIP_MSG_API
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------
+   ---------- ARP options ----------
+   ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_arp ARP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#if !defined LWIP_ARP || defined __DOXYGEN__
+#define LWIP_ARP                        1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#if !defined ARP_TABLE_SIZE || defined __DOXYGEN__
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ *  for ARP_TMR_INTERVAL = 1000, this is
+ *  (60 * 5) seconds = 5 minutes.
+ */
+#if !defined ARP_MAXAGE || defined __DOXYGEN__
+#define ARP_MAXAGE                      300
+#endif
+
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#if !defined ARP_QUEUEING || defined __DOXYGEN__
+#define ARP_QUEUEING                    0
+#endif
+
+/** The maximum number of packets which may be queued for each
+ *  unresolved address by other network layers. Defaults to 3, 0 means disabled.
+ *  Old packets are dropped, new packets are queued.
+ */
+#if !defined ARP_QUEUE_LEN || defined __DOXYGEN__
+#define ARP_QUEUE_LEN                   3
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with
+ * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and
+ * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan)
+ * that returns 1 to accept a packet or 0 to drop a packet.
+ */
+#if !defined ETHARP_SUPPORT_VLAN || defined __DOXYGEN__
+#define ETHARP_SUPPORT_VLAN             0
+#endif
+
+/** LWIP_ETHERNET==1: enable ethernet support even though ARP might be disabled
+ */
+#if !defined LWIP_ETHERNET || defined __DOXYGEN__
+#define LWIP_ETHERNET                   LWIP_ARP
+#endif
+
+/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
+ * alignment of payload after that header. Since the header is 14 bytes long,
+ * without this padding e.g. addresses in the IP header will not be aligned
+ * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
+ */
+#if !defined ETH_PAD_SIZE || defined __DOXYGEN__
+#define ETH_PAD_SIZE                    0
+#endif
+
+/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
+ * entries (using etharp_add_static_entry/etharp_remove_static_entry).
+ */
+#if !defined ETHARP_SUPPORT_STATIC_ENTRIES || defined __DOXYGEN__
+#define ETHARP_SUPPORT_STATIC_ENTRIES   0
+#endif
+
+/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries.
+ * If disabled, duplicate IP address on multiple netifs are not supported
+ * (but this should only occur for AutoIP).
+ */
+#if !defined ETHARP_TABLE_MATCH_NETIF || defined __DOXYGEN__
+#define ETHARP_TABLE_MATCH_NETIF        !LWIP_SINGLE_NETIF
+#endif
+/**
+ * @}
+ */
+
+/*
+   --------------------------------
+   ---------- IP options ----------
+   --------------------------------
+*/
+/**
+ * @defgroup lwip_opts_ipv4 IPv4
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * LWIP_IPV4==1: Enable IPv4
+ */
+#if !defined LWIP_IPV4 || defined __DOXYGEN__
+#define LWIP_IPV4                       1
+#endif
+
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#if !defined IP_FORWARD || defined __DOXYGEN__
+#define IP_FORWARD                      0
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#if !defined IP_REASSEMBLY || defined __DOXYGEN__
+#define IP_REASSEMBLY                   1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#if !defined IP_FRAG || defined __DOXYGEN__
+#define IP_FRAG                         1
+#endif
+
+#if !LWIP_IPV4
+/* disable IPv4 extensions when IPv4 is disabled */
+#undef IP_FORWARD
+#define IP_FORWARD                      0
+#undef IP_REASSEMBLY
+#define IP_REASSEMBLY                   0
+#undef IP_FRAG
+#define IP_FRAG                         0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#if !defined IP_OPTIONS_ALLOWED || defined __DOXYGEN__
+#define IP_OPTIONS_ALLOWED              1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#if !defined IP_REASS_MAXAGE || defined __DOXYGEN__
+#define IP_REASS_MAXAGE                 15
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ * When IPv4 *and* IPv6 are enabled, this even changes to
+ * (PBUF_POOL_SIZE > 2 * IP_REASS_MAX_PBUFS)!
+ */
+#if !defined IP_REASS_MAX_PBUFS || defined __DOXYGEN__
+#define IP_REASS_MAX_PBUFS              10
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#if !defined IP_DEFAULT_TTL || defined __DOXYGEN__
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#if !defined IP_SOF_BROADCAST || defined __DOXYGEN__
+#define IP_SOF_BROADCAST                0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#if !defined IP_SOF_BROADCAST_RECV || defined __DOXYGEN__
+#define IP_SOF_BROADCAST_RECV           0
+#endif
+
+/**
+ * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back
+ * out on the netif where it was received. This should only be used for
+ * wireless networks.
+ * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming
+ * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags!
+ */
+#if !defined IP_FORWARD_ALLOW_TX_ON_RX_NETIF || defined __DOXYGEN__
+#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   ---------- ICMP options ----------
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_icmp ICMP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#if !defined LWIP_ICMP || defined __DOXYGEN__
+#define LWIP_ICMP                       1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#if !defined ICMP_TTL || defined __DOXYGEN__
+#define ICMP_TTL                        IP_DEFAULT_TTL
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#if !defined LWIP_BROADCAST_PING || defined __DOXYGEN__
+#define LWIP_BROADCAST_PING             0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#if !defined LWIP_MULTICAST_PING || defined __DOXYGEN__
+#define LWIP_MULTICAST_PING             0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------
+   ---------- RAW options ----------
+   ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_raw RAW
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#if !defined LWIP_RAW || defined __DOXYGEN__
+#define LWIP_RAW                        0
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#if !defined RAW_TTL || defined __DOXYGEN__
+#define RAW_TTL                         IP_DEFAULT_TTL
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   ---------- DHCP options ----------
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_dhcp DHCP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#if !defined LWIP_DHCP || defined __DOXYGEN__
+#define LWIP_DHCP                       0
+#endif
+#if !LWIP_IPV4
+/* disable DHCP when IPv4 is disabled */
+#undef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#if !defined DHCP_DOES_ARP_CHECK || defined __DOXYGEN__
+#define DHCP_DOES_ARP_CHECK             (LWIP_DHCP && LWIP_ARP)
+#endif
+
+/**
+ * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name.
+ */
+#if !defined LWIP_DHCP_BOOTP_FILE || defined __DOXYGEN__
+#define LWIP_DHCP_BOOTP_FILE            0
+#endif
+
+/**
+ * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each
+ * response packet, an callback is called, which has to be provided by the port:
+ * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs);
+*/
+#if !defined LWIP_DHCP_GET_NTP_SRV || defined __DOXYGEN__
+#define LWIP_DHCP_GET_NTP_SRV           0
+#endif
+
+/**
+ * The maximum of NTP servers requested
+ */
+#if !defined LWIP_DHCP_MAX_NTP_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP_MAX_NTP_SERVERS       1
+#endif
+
+/**
+ * LWIP_DHCP_MAX_DNS_SERVERS > 0: Request DNS servers with discover/select.
+ * DNS servers received in the response are passed to DNS via @ref dns_setserver()
+ * (up to the maximum limit defined here).
+ */
+#if !defined LWIP_DHCP_MAX_DNS_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP_MAX_DNS_SERVERS       DNS_MAX_SERVERS
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------
+   ---------- AUTOIP options ----------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_autoip AUTOIP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#if !defined LWIP_AUTOIP || defined __DOXYGEN__
+#define LWIP_AUTOIP                     0
+#endif
+#if !LWIP_IPV4
+/* disable AUTOIP when IPv4 is disabled */
+#undef LWIP_AUTOIP
+#define LWIP_AUTOIP                     0
+#endif /* !LWIP_IPV4 */
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#if !defined LWIP_DHCP_AUTOIP_COOP || defined __DOXYGEN__
+#define LWIP_DHCP_AUTOIP_COOP           0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP (the DHCP client keeps
+ * running in this case). This can be set as low as 1 to get an AutoIP address
+ * very  quickly, but you should be prepared to handle a changing IP address
+ * when DHCP overrides AutoIP.
+ */
+#if !defined LWIP_DHCP_AUTOIP_COOP_TRIES || defined __DOXYGEN__
+#define LWIP_DHCP_AUTOIP_COOP_TRIES     9
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   ----- SNMP MIB2 support      -----
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_mib2 SNMP MIB2 callbacks
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks.
+ * Turn this on to get callbacks needed to implement MIB2.
+ * Usually MIB2_STATS should be enabled, too.
+ */
+#if !defined LWIP_MIB2_CALLBACKS || defined __DOXYGEN__
+#define LWIP_MIB2_CALLBACKS             0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   -------- Multicast options -------
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_multicast Multicast
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options
+ * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP, as well as (currently only)
+ * core support for the corresponding IPv6 options.
+ */
+#if !defined LWIP_MULTICAST_TX_OPTIONS || defined __DOXYGEN__
+#define LWIP_MULTICAST_TX_OPTIONS       ((LWIP_IGMP || LWIP_IPV6_MLD) && (LWIP_UDP || LWIP_RAW))
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   ---------- IGMP options ----------
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_igmp IGMP
+ * @ingroup lwip_opts_ipv4
+ * @{
+ */
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#if !defined LWIP_IGMP || defined __DOXYGEN__
+#define LWIP_IGMP                       0
+#endif
+#if !LWIP_IPV4
+#undef LWIP_IGMP
+#define LWIP_IGMP                       0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   ---------- DNS options -----------
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_dns DNS
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#if !defined LWIP_DNS || defined __DOXYGEN__
+#define LWIP_DNS                        0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#if !defined DNS_TABLE_SIZE || defined __DOXYGEN__
+#define DNS_TABLE_SIZE                  4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#if !defined DNS_MAX_NAME_LENGTH || defined __DOXYGEN__
+#define DNS_MAX_NAME_LENGTH             256
+#endif
+
+/** The maximum of DNS servers
+ * The first server can be initialized automatically by defining
+ * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*'
+ */
+#if !defined DNS_MAX_SERVERS || defined __DOXYGEN__
+#define DNS_MAX_SERVERS                 2
+#endif
+
+/** DNS maximum number of retries when asking for a name, before "timeout". */
+#if !defined DNS_MAX_RETRIES || defined __DOXYGEN__
+#define DNS_MAX_RETRIES                 4
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#if !defined DNS_DOES_NAME_CHECK || defined __DOXYGEN__
+#define DNS_DOES_NAME_CHECK             1
+#endif
+
+/** LWIP_DNS_SECURE: controls the security level of the DNS implementation
+ * Use all DNS security features by default.
+ * This is overridable but should only be needed by very small targets
+ * or when using against non standard DNS servers. */
+#if !defined LWIP_DNS_SECURE || defined __DOXYGEN__
+#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)
+#endif
+
+/* A list of DNS security features follows */
+#define LWIP_DNS_SECURE_RAND_XID                1
+#define LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING 2
+#define LWIP_DNS_SECURE_RAND_SRC_PORT           4
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, you have to define an initializer:
+ *  \#define DNS_LOCAL_HOSTLIST_INIT {DNS_LOCAL_HOSTLIST_ELEM("host_ip4", IPADDR4_INIT_BYTES(1,2,3,4)), \
+ *                                    DNS_LOCAL_HOSTLIST_ELEM("host_ip6", IPADDR6_INIT_HOST(123, 234, 345, 456)}
+ *
+ *  Instead, you can also use an external function:
+ *  \#define DNS_LOOKUP_LOCAL_EXTERN(x) extern err_t my_lookup_function(const char *name, ip_addr_t *addr, u8_t dns_addrtype)
+ *  that looks up the IP address and returns ERR_OK if found (LWIP_DNS_ADDRTYPE_xxx is passed in dns_addrtype).
+ */
+#if !defined DNS_LOCAL_HOSTLIST || defined __DOXYGEN__
+#define DNS_LOCAL_HOSTLIST              0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ *  at runtime. */
+#if !defined DNS_LOCAL_HOSTLIST_IS_DYNAMIC || defined __DOXYGEN__
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC   0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/** Set this to 1 to enable querying ".local" names via mDNS
+ *  using a One-Shot Multicast DNS Query */
+#if !defined LWIP_DNS_SUPPORT_MDNS_QUERIES || defined __DOXYGEN__
+#define LWIP_DNS_SUPPORT_MDNS_QUERIES   0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------
+   ---------- UDP options ----------
+   ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_udp UDP
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#if !defined LWIP_UDP || defined __DOXYGEN__
+#define LWIP_UDP                        1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#if !defined LWIP_UDPLITE || defined __DOXYGEN__
+#define LWIP_UDPLITE                    0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#if !defined UDP_TTL || defined __DOXYGEN__
+#define UDP_TTL                         IP_DEFAULT_TTL
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#if !defined LWIP_NETBUF_RECVINFO || defined __DOXYGEN__
+#define LWIP_NETBUF_RECVINFO            0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------
+   ---------- TCP options ----------
+   ---------------------------------
+*/
+/**
+ * @defgroup lwip_opts_tcp TCP
+ * @ingroup lwip_opts_callback
+ * @{
+ */
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#if !defined LWIP_TCP || defined __DOXYGEN__
+#define LWIP_TCP                        1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#if !defined TCP_TTL || defined __DOXYGEN__
+#define TCP_TTL                         IP_DEFAULT_TTL
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window.  This must be at least
+ * (2 * TCP_MSS) for things to work well.
+ * ATTENTION: when using TCP_RCV_SCALE, TCP_WND is the total size
+ * with scaling applied. Maximum window value in the TCP header
+ * will be TCP_WND >> TCP_RCV_SCALE
+ */
+#if !defined TCP_WND || defined __DOXYGEN__
+#define TCP_WND                         (4 * TCP_MSS)
+#endif
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#if !defined TCP_MAXRTX || defined __DOXYGEN__
+#define TCP_MAXRTX                      12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#if !defined TCP_SYNMAXRTX || defined __DOXYGEN__
+#define TCP_SYNMAXRTX                   6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#if !defined TCP_QUEUE_OOSEQ || defined __DOXYGEN__
+#define TCP_QUEUE_OOSEQ                 LWIP_TCP
+#endif
+
+/**
+ * LWIP_TCP_SACK_OUT==1: TCP will support sending selective acknowledgements (SACKs).
+ */
+#if !defined LWIP_TCP_SACK_OUT || defined __DOXYGEN__
+#define LWIP_TCP_SACK_OUT               0
+#endif
+
+/**
+ * LWIP_TCP_MAX_SACK_NUM: The maximum number of SACK values to include in TCP segments.
+ * Must be at least 1, but is only used if LWIP_TCP_SACK_OUT is enabled.
+ * NOTE: Even though we never send more than 3 or 4 SACK ranges in a single segment
+ * (depending on other options), setting this option to values greater than 4 is not pointless.
+ * This is basically the max number of SACK ranges we want to keep track of.
+ * As new data is delivered, some of the SACK ranges may be removed or merged.
+ * In that case some of those older SACK ranges may be used again.
+ * The amount of memory used to store SACK ranges is LWIP_TCP_MAX_SACK_NUM * 8 bytes for each TCP PCB.
+ */
+#if !defined LWIP_TCP_MAX_SACK_NUM || defined __DOXYGEN__
+#define LWIP_TCP_MAX_SACK_NUM           4
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#if !defined TCP_MSS || defined __DOXYGEN__
+#define TCP_MSS                         536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#if !defined TCP_CALCULATE_EFF_SEND_MSS || defined __DOXYGEN__
+#define TCP_CALCULATE_EFF_SEND_MSS      1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes).
+ * To achieve good performance, this should be at least 2 * TCP_MSS.
+ */
+#if !defined TCP_SND_BUF || defined __DOXYGEN__
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#if !defined TCP_SND_QUEUELEN || defined __DOXYGEN__
+#define TCP_SND_QUEUELEN                ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
+ * TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
+ */
+#if !defined TCP_SNDLOWAT || defined __DOXYGEN__
+#define TCP_SNDLOWAT                    LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1)
+#endif
+
+/**
+ * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less
+ * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
+ * this number, select returns writable (combined with TCP_SNDLOWAT).
+ */
+#if !defined TCP_SNDQUEUELOWAT || defined __DOXYGEN__
+#define TCP_SNDQUEUELOWAT               LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5)
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_BYTES: The default maximum number of bytes queued on ooseq per
+ * pcb if TCP_OOSEQ_BYTES_LIMIT is not defined. Default is 0 (no limit).
+ * Only valid for TCP_QUEUE_OOSEQ==1.
+ */
+#if !defined TCP_OOSEQ_MAX_BYTES || defined __DOXYGEN__
+#define TCP_OOSEQ_MAX_BYTES             0
+#endif
+
+/**
+ * TCP_OOSEQ_BYTES_LIMIT(pcb): Return the maximum number of bytes to be queued
+ * on ooseq per pcb, given the pcb. Only valid for TCP_QUEUE_OOSEQ==1 &&
+ * TCP_OOSEQ_MAX_BYTES==1.
+ * Use this to override TCP_OOSEQ_MAX_BYTES to a dynamic value per pcb.
+ */
+#if !defined TCP_OOSEQ_BYTES_LIMIT
+#if TCP_OOSEQ_MAX_BYTES
+#define TCP_OOSEQ_BYTES_LIMIT(pcb)      TCP_OOSEQ_MAX_BYTES
+#elif defined __DOXYGEN__
+#define TCP_OOSEQ_BYTES_LIMIT(pcb)
+#endif
+#endif
+
+/**
+ * TCP_OOSEQ_MAX_PBUFS: The default maximum number of pbufs queued on ooseq per
+ * pcb if TCP_OOSEQ_BYTES_LIMIT is not defined. Default is 0 (no limit).
+ * Only valid for TCP_QUEUE_OOSEQ==1.
+ */
+#if !defined TCP_OOSEQ_MAX_PBUFS || defined __DOXYGEN__
+#define TCP_OOSEQ_MAX_PBUFS             0
+#endif
+
+/**
+ * TCP_OOSEQ_PBUFS_LIMIT(pcb): Return the maximum number of pbufs to be queued
+ * on ooseq per pcb, given the pcb.  Only valid for TCP_QUEUE_OOSEQ==1 &&
+ * TCP_OOSEQ_MAX_PBUFS==1.
+ * Use this to override TCP_OOSEQ_MAX_PBUFS to a dynamic value per pcb.
+ */
+#if !defined TCP_OOSEQ_PBUFS_LIMIT
+#if TCP_OOSEQ_MAX_PBUFS
+#define TCP_OOSEQ_PBUFS_LIMIT(pcb)      TCP_OOSEQ_MAX_PBUFS
+#elif defined __DOXYGEN__
+#define TCP_OOSEQ_PBUFS_LIMIT(pcb)
+#endif
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#if !defined TCP_LISTEN_BACKLOG || defined __DOXYGEN__
+#define TCP_LISTEN_BACKLOG              0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#if !defined TCP_DEFAULT_LISTEN_BACKLOG || defined __DOXYGEN__
+#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
+#endif
+
+/**
+ * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
+ * allocate ahead of time in an attempt to create shorter pbuf chains
+ * for transmission. The meaningful range is 0 to TCP_MSS. Some
+ * suggested values are:
+ *
+ * 0:         Disable oversized allocation. Each tcp_write() allocates a new
+              pbuf (old behaviour).
+ * 1:         Allocate size-aligned pbufs with minimal excess. Use this if your
+ *            scatter-gather DMA requires aligned fragments.
+ * 128:       Limit the pbuf/memory overhead to 20%.
+ * TCP_MSS:   Try to create unfragmented TCP packets.
+ * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
+ */
+#if !defined TCP_OVERSIZE || defined __DOXYGEN__
+#define TCP_OVERSIZE                    TCP_MSS
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ * The timestamp option is currently only used to help remote hosts, it is not
+ * really used locally. Therefore, it is only enabled when a TS option is
+ * received in the initial SYN packet from a remote host.
+ */
+#if !defined LWIP_TCP_TIMESTAMPS || defined __DOXYGEN__
+#define LWIP_TCP_TIMESTAMPS             0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#if !defined TCP_WND_UPDATE_THRESHOLD || defined __DOXYGEN__
+#define TCP_WND_UPDATE_THRESHOLD        LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4))
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ *         events (accept, sent, etc) that happen in the system.
+ *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ *         for the event. This is the default.
+ */
+#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) || defined __DOXYGEN__
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#endif
+#ifndef LWIP_CALLBACK_API
+#define LWIP_CALLBACK_API               0
+#endif
+#endif
+
+/**
+ * LWIP_WND_SCALE and TCP_RCV_SCALE:
+ * Set LWIP_WND_SCALE to 1 to enable window scaling.
+ * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the
+ * range of [0..14]).
+ * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large
+ * send window while having a small receive window only.
+ */
+#if !defined LWIP_WND_SCALE || defined __DOXYGEN__
+#define LWIP_WND_SCALE                  0
+#define TCP_RCV_SCALE                   0
+#endif
+
+/**
+ * LWIP_TCP_PCB_NUM_EXT_ARGS:
+ * When this is > 0, every tcp pcb (including listen pcb) includes a number of
+ * additional argument entries in an array (see tcp_ext_arg_alloc_id)
+ */
+#if !defined LWIP_TCP_PCB_NUM_EXT_ARGS || defined __DOXYGEN__
+#define LWIP_TCP_PCB_NUM_EXT_ARGS       0
+#endif
+
+/** LWIP_ALTCP==1: enable the altcp API.
+ * altcp is an abstraction layer that prevents applications linking against the
+ * tcp.h functions but provides the same functionality. It is used to e.g. add
+ * SSL/TLS or proxy-connect support to an application written for the tcp callback
+ * API without that application knowing the protocol details.
+ *
+ * With LWIP_ALTCP==0, applications written against the altcp API can still be
+ * compiled but are directly linked against the tcp.h callback API and then
+ * cannot use layered protocols.
+ *
+ * See @ref altcp_api
+ */
+#if !defined LWIP_ALTCP || defined __DOXYGEN__
+#define LWIP_ALTCP                      0
+#endif
+
+/** LWIP_ALTCP_TLS==1: enable TLS support for altcp API.
+ * This needs a port of the functions in altcp_tls.h to a TLS library.
+ * A port to ARM mbedtls is provided with lwIP, see apps/altcp_tls/ directory
+ * and LWIP_ALTCP_TLS_MBEDTLS option.
+ */
+#if !defined LWIP_ALTCP_TLS || defined __DOXYGEN__
+#define LWIP_ALTCP_TLS                  0
+#endif
+
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------
+   ---------- Pbuf options ----------
+   ----------------------------------
+*/
+/**
+ * @defgroup lwip_opts_pbuf PBUF
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#if !defined PBUF_LINK_HLEN || defined __DOXYGEN__
+#if defined LWIP_HOOK_VLAN_SET && !defined __DOXYGEN__
+#define PBUF_LINK_HLEN                  (18 + ETH_PAD_SIZE)
+#else /* LWIP_HOOK_VLAN_SET */
+#define PBUF_LINK_HLEN                  (14 + ETH_PAD_SIZE)
+#endif /* LWIP_HOOK_VLAN_SET */
+#endif
+
+/**
+ * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated
+ * for an additional encapsulation header before ethernet headers (e.g. 802.11)
+ */
+#if !defined PBUF_LINK_ENCAPSULATION_HLEN || defined __DOXYGEN__
+#define PBUF_LINK_ENCAPSULATION_HLEN    0
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accommodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#if !defined PBUF_POOL_BUFSIZE || defined __DOXYGEN__
+#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN)
+#endif
+
+/**
+ * LWIP_PBUF_REF_T: Refcount type in pbuf.
+ * Default width of u8_t can be increased if 255 refs are not enough for you.
+ */
+#if !defined LWIP_PBUF_REF_T || defined __DOXYGEN__
+#define LWIP_PBUF_REF_T                 u8_t
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------------------
+   ---------- Network Interfaces options ----------
+   ------------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_netif NETIF
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * LWIP_SINGLE_NETIF==1: use a single netif only. This is the common case for
+ * small real-life targets. Some code like routing etc. can be left out.
+ */
+#if !defined LWIP_SINGLE_NETIF || defined __DOXYGEN__
+#define LWIP_SINGLE_NETIF               0
+#endif
+
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#if !defined LWIP_NETIF_HOSTNAME || defined __DOXYGEN__
+#define LWIP_NETIF_HOSTNAME             0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#if !defined LWIP_NETIF_API || defined __DOXYGEN__
+#define LWIP_NETIF_API                  0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquisition)
+ */
+#if !defined LWIP_NETIF_STATUS_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_STATUS_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_EXT_STATUS_CALLBACK==1: Support an extended callback function 
+ * for several netif related event that supports multiple subscribers.
+ * @see netif_ext_status_callback
+ */
+#if !defined LWIP_NETIF_EXT_STATUS_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_EXT_STATUS_CALLBACK  0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#if !defined LWIP_NETIF_LINK_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_LINK_CALLBACK        0
+#endif
+
+/**
+ * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called
+ * when a netif has been removed
+ */
+#if !defined LWIP_NETIF_REMOVE_CALLBACK || defined __DOXYGEN__
+#define LWIP_NETIF_REMOVE_CALLBACK      0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#if !defined LWIP_NETIF_HWADDRHINT || defined __DOXYGEN__
+#define LWIP_NETIF_HWADDRHINT           0
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP *tries* to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * ATTENTION: a driver should *NOT* rely on getting single pbufs but check TX
+ * pbufs for being in one piece. If not, @ref pbuf_clone can be used to get
+ * a single pbuf:
+ *   if (p->next != NULL) {
+ *     struct pbuf *q = pbuf_clone(PBUF_RAW, PBUF_RAM, p);
+ *     if (q == NULL) {
+ *       return ERR_MEM;
+ *     }
+ *     p = q; ATTENTION: do NOT free the old 'p' as the ref belongs to the caller!
+ *   }
+ */
+#if !defined LWIP_NETIF_TX_SINGLE_PBUF || defined __DOXYGEN__
+#define LWIP_NETIF_TX_SINGLE_PBUF       0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/**
+ * LWIP_NUM_NETIF_CLIENT_DATA: Number of clients that may store
+ * data in client_data member array of struct netif (max. 256).
+ */
+#if !defined LWIP_NUM_NETIF_CLIENT_DATA || defined __DOXYGEN__
+#define LWIP_NUM_NETIF_CLIENT_DATA      0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------
+   ---------- LOOPIF options ----------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_loop Loopback interface
+ * @ingroup lwip_opts_netif
+ * @{
+ */
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1).
+ * This is only needed when no real netifs are available. If at least one other
+ * netif is available, loopback traffic uses this netif.
+ */
+#if !defined LWIP_HAVE_LOOPIF || defined __DOXYGEN__
+#define LWIP_HAVE_LOOPIF                (LWIP_NETIF_LOOPBACK && !LWIP_SINGLE_NETIF)
+#endif
+
+/**
+ * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1).
+ */
+#if !defined LWIP_LOOPIF_MULTICAST || defined __DOXYGEN__
+#define LWIP_LOOPIF_MULTICAST           0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#if !defined LWIP_NETIF_LOOPBACK || defined __DOXYGEN__
+#define LWIP_NETIF_LOOPBACK             0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#if !defined LWIP_LOOPBACK_MAX_PBUFS || defined __DOXYGEN__
+#define LWIP_LOOPBACK_MAX_PBUFS         0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ *       multithreaded environment like tcpip.c. In this case, netif->input()
+ *       is called directly.
+ *    LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ *       The packets are put on a list and netif_poll() must be called in
+ *       the main application loop.
+ */
+#if !defined LWIP_NETIF_LOOPBACK_MULTITHREADING || defined __DOXYGEN__
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING    (!NO_SYS)
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------
+   ---------- Thread options ----------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_thread Threading
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#if !defined TCPIP_THREAD_NAME || defined __DOXYGEN__
+#define TCPIP_THREAD_NAME               "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined TCPIP_THREAD_STACKSIZE || defined __DOXYGEN__
+#define TCPIP_THREAD_STACKSIZE          0
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined TCPIP_THREAD_PRIO || defined __DOXYGEN__
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#if !defined TCPIP_MBOX_SIZE || defined __DOXYGEN__
+#define TCPIP_MBOX_SIZE                 0
+#endif
+
+/**
+ * Define this to something that triggers a watchdog. This is called from
+ * tcpip_thread after processing a message.
+ */
+#if !defined LWIP_TCPIP_THREAD_ALIVE || defined __DOXYGEN__
+#define LWIP_TCPIP_THREAD_ALIVE()
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#if !defined SLIPIF_THREAD_NAME || defined __DOXYGEN__
+#define SLIPIF_THREAD_NAME              "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined SLIPIF_THREAD_STACKSIZE || defined __DOXYGEN__
+#define SLIPIF_THREAD_STACKSIZE         0
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined SLIPIF_THREAD_PRIO || defined __DOXYGEN__
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#if !defined DEFAULT_THREAD_NAME || defined __DOXYGEN__
+#define DEFAULT_THREAD_NAME             "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined DEFAULT_THREAD_STACKSIZE || defined __DOXYGEN__
+#define DEFAULT_THREAD_STACKSIZE        0
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#if !defined DEFAULT_THREAD_PRIO || defined __DOXYGEN__
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#if !defined DEFAULT_RAW_RECVMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_RAW_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#if !defined DEFAULT_UDP_RECVMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_UDP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#if !defined DEFAULT_TCP_RECVMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_TCP_RECVMBOX_SIZE       0
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#if !defined DEFAULT_ACCEPTMBOX_SIZE || defined __DOXYGEN__
+#define DEFAULT_ACCEPTMBOX_SIZE         0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------------------
+   ---------- Sequential layer options ----------
+   ----------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_netconn Netconn
+ * @ingroup lwip_opts_threadsafe_apis
+ * @{
+ */
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#if !defined LWIP_NETCONN || defined __DOXYGEN__
+#define LWIP_NETCONN                    1
+#endif
+
+/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create
+ * timers running in tcpip_thread from another thread.
+ */
+#if !defined LWIP_TCPIP_TIMEOUT || defined __DOXYGEN__
+#define LWIP_TCPIP_TIMEOUT              0
+#endif
+
+/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per
+ * thread calling socket/netconn functions instead of allocating one
+ * semaphore per netconn (and per select etc.)
+ * ATTENTION: a thread-local semaphore for API calls is needed:
+ * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t*
+ * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore
+ * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore
+ * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup().
+ * Ports may call these for threads created with sys_thread_new().
+ */
+#if !defined LWIP_NETCONN_SEM_PER_THREAD || defined __DOXYGEN__
+#define LWIP_NETCONN_SEM_PER_THREAD     0
+#endif
+
+/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread,
+ * writing from a 2nd thread and closing from a 3rd thread at the same time.
+ * ATTENTION: This is currently really alpha! Some requirements:
+ * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from
+ *   multiple threads at once
+ * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox
+ *   and prevent a task pending on this during/after deletion
+ */
+#if !defined LWIP_NETCONN_FULLDUPLEX || defined __DOXYGEN__
+#define LWIP_NETCONN_FULLDUPLEX         0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ------------------------------------
+   ---------- Socket options ----------
+   ------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_socket Sockets
+ * @ingroup lwip_opts_threadsafe_apis
+ * @{
+ */
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#if !defined LWIP_SOCKET || defined __DOXYGEN__
+#define LWIP_SOCKET                     1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines.
+ * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created.
+ * While this helps code completion, it might conflict with existing libraries.
+ * (only used if you use sockets.c)
+ */
+#if !defined LWIP_COMPAT_SOCKETS || defined __DOXYGEN__
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#if !defined LWIP_POSIX_SOCKETS_IO_NAMES || defined __DOXYGEN__
+#define LWIP_POSIX_SOCKETS_IO_NAMES     1
+#endif
+
+/**
+ * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n.
+ * This can be useful when there are multiple APIs which create file descriptors.
+ * When they all start with a different offset and you won't make them overlap you can
+ * re implement read/write/close/ioctl/fnctl to send the requested action to the right
+ * library (sharing select will need more work though).
+ */
+#if !defined LWIP_SOCKET_OFFSET || defined __DOXYGEN__
+#define LWIP_SOCKET_OFFSET              0
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#if !defined LWIP_TCP_KEEPALIVE || defined __DOXYGEN__
+#define LWIP_TCP_KEEPALIVE              0
+#endif
+
+/**
+ * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
+ * SO_SNDTIMEO processing.
+ */
+#if !defined LWIP_SO_SNDTIMEO || defined __DOXYGEN__
+#define LWIP_SO_SNDTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
+ * SO_RCVTIMEO processing.
+ */
+#if !defined LWIP_SO_RCVTIMEO || defined __DOXYGEN__
+#define LWIP_SO_RCVTIMEO                0
+#endif
+
+/**
+ * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int
+ * (milliseconds, much like winsock does) instead of a struct timeval (default).
+ */
+#if !defined LWIP_SO_SNDRCVTIMEO_NONSTANDARD || defined __DOXYGEN__
+#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#if !defined LWIP_SO_RCVBUF || defined __DOXYGEN__
+#define LWIP_SO_RCVBUF                  0
+#endif
+
+/**
+ * LWIP_SO_LINGER==1: Enable SO_LINGER processing.
+ */
+#if !defined LWIP_SO_LINGER || defined __DOXYGEN__
+#define LWIP_SO_LINGER                  0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#if !defined RECV_BUFSIZE_DEFAULT || defined __DOXYGEN__
+#define RECV_BUFSIZE_DEFAULT            INT_MAX
+#endif
+
+/**
+ * By default, TCP socket/netconn close waits 20 seconds max to send the FIN
+ */
+#if !defined LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT || defined __DOXYGEN__
+#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ */
+#if !defined SO_REUSE || defined __DOXYGEN__
+#define SO_REUSE                        0
+#endif
+
+/**
+ * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
+ * to all local matches if SO_REUSEADDR is turned on.
+ * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
+ */
+#if !defined SO_REUSE_RXTOALL || defined __DOXYGEN__
+#define SO_REUSE_RXTOALL                0
+#endif
+
+/**
+ * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of
+ * pending data in the network buffer. This is the way windows does it. It's
+ * the default for lwIP since it is smaller.
+ * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next
+ * pending datagram in bytes. This is the way linux does it. This code is only
+ * here for compatibility.
+ */
+#if !defined LWIP_FIONREAD_LINUXMODE || defined __DOXYGEN__
+#define LWIP_FIONREAD_LINUXMODE         0
+#endif
+
+/**
+ * LWIP_SOCKET_SELECT==1 (default): enable select() for sockets (uses a netconn
+ * callback to keep track of events).
+ * This saves RAM (counters per socket) and code (netconn event callback), which
+ * should improve performance a bit).
+ */
+#if !defined LWIP_SOCKET_SELECT || defined __DOXYGEN__
+#define LWIP_SOCKET_SELECT              1
+#endif
+
+/**
+ * LWIP_SOCKET_POLL==1 (default): enable poll() for sockets (including
+ * struct pollfd, nfds_t, and constants)
+ */
+#if !defined LWIP_SOCKET_POLL || defined __DOXYGEN__
+#define LWIP_SOCKET_POLL                1
+#endif
+/**
+ * @}
+ */
+
+/*
+   ----------------------------------------
+   ---------- Statistics options ----------
+   ----------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_stats Statistics
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#if !defined LWIP_STATS || defined __DOXYGEN__
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#if !defined LWIP_STATS_DISPLAY || defined __DOXYGEN__
+#define LWIP_STATS_DISPLAY              0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#if !defined LINK_STATS || defined __DOXYGEN__
+#define LINK_STATS                      1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#if !defined ETHARP_STATS || defined __DOXYGEN__
+#define ETHARP_STATS                    (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#if !defined IP_STATS || defined __DOXYGEN__
+#define IP_STATS                        1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#if !defined IPFRAG_STATS || defined __DOXYGEN__
+#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#if !defined ICMP_STATS || defined __DOXYGEN__
+#define ICMP_STATS                      1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#if !defined IGMP_STATS || defined __DOXYGEN__
+#define IGMP_STATS                      (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#if !defined UDP_STATS || defined __DOXYGEN__
+#define UDP_STATS                       (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#if !defined TCP_STATS || defined __DOXYGEN__
+#define TCP_STATS                       (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#if !defined MEM_STATS || defined __DOXYGEN__
+#define MEM_STATS                       ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#if !defined MEMP_STATS || defined __DOXYGEN__
+#define MEMP_STATS                      (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#if !defined SYS_STATS || defined __DOXYGEN__
+#define SYS_STATS                       (NO_SYS == 0)
+#endif
+
+/**
+ * IP6_STATS==1: Enable IPv6 stats.
+ */
+#if !defined IP6_STATS || defined __DOXYGEN__
+#define IP6_STATS                       (LWIP_IPV6)
+#endif
+
+/**
+ * ICMP6_STATS==1: Enable ICMP for IPv6 stats.
+ */
+#if !defined ICMP6_STATS || defined __DOXYGEN__
+#define ICMP6_STATS                     (LWIP_IPV6 && LWIP_ICMP6)
+#endif
+
+/**
+ * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats.
+ */
+#if !defined IP6_FRAG_STATS || defined __DOXYGEN__
+#define IP6_FRAG_STATS                  (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS))
+#endif
+
+/**
+ * MLD6_STATS==1: Enable MLD for IPv6 stats.
+ */
+#if !defined MLD6_STATS || defined __DOXYGEN__
+#define MLD6_STATS                      (LWIP_IPV6 && LWIP_IPV6_MLD)
+#endif
+
+/**
+ * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats.
+ */
+#if !defined ND6_STATS || defined __DOXYGEN__
+#define ND6_STATS                       (LWIP_IPV6)
+#endif
+
+/**
+ * MIB2_STATS==1: Stats for SNMP MIB2.
+ */
+#if !defined MIB2_STATS || defined __DOXYGEN__
+#define MIB2_STATS                      0
+#endif
+
+#else
+
+#define LINK_STATS                      0
+#define ETHARP_STATS                    0
+#define IP_STATS                        0
+#define IPFRAG_STATS                    0
+#define ICMP_STATS                      0
+#define IGMP_STATS                      0
+#define UDP_STATS                       0
+#define TCP_STATS                       0
+#define MEM_STATS                       0
+#define MEMP_STATS                      0
+#define SYS_STATS                       0
+#define LWIP_STATS_DISPLAY              0
+#define IP6_STATS                       0
+#define ICMP6_STATS                     0
+#define IP6_FRAG_STATS                  0
+#define MLD6_STATS                      0
+#define ND6_STATS                       0
+#define MIB2_STATS                      0
+
+#endif /* LWIP_STATS */
+/**
+ * @}
+ */
+
+/*
+   --------------------------------------
+   ---------- Checksum options ----------
+   --------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_checksum Checksum
+ * @ingroup lwip_opts_infrastructure
+ * @{
+ */
+/**
+ * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled
+ * per netif.
+ * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled!
+ */
+#if !defined LWIP_CHECKSUM_CTRL_PER_NETIF || defined __DOXYGEN__
+#define LWIP_CHECKSUM_CTRL_PER_NETIF    0
+#endif
+
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#if !defined CHECKSUM_GEN_IP || defined __DOXYGEN__
+#define CHECKSUM_GEN_IP                 1
+#endif
+
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#if !defined CHECKSUM_GEN_UDP || defined __DOXYGEN__
+#define CHECKSUM_GEN_UDP                1
+#endif
+
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#if !defined CHECKSUM_GEN_TCP || defined __DOXYGEN__
+#define CHECKSUM_GEN_TCP                1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets.
+ */
+#if !defined CHECKSUM_GEN_ICMP || defined __DOXYGEN__
+#define CHECKSUM_GEN_ICMP               1
+#endif
+
+/**
+ * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets.
+ */
+#if !defined CHECKSUM_GEN_ICMP6 || defined __DOXYGEN__
+#define CHECKSUM_GEN_ICMP6              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#if !defined CHECKSUM_CHECK_IP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_IP               1
+#endif
+
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#if !defined CHECKSUM_CHECK_UDP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#if !defined CHECKSUM_CHECK_TCP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/**
+ * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets.
+ */
+#if !defined CHECKSUM_CHECK_ICMP || defined __DOXYGEN__
+#define CHECKSUM_CHECK_ICMP             1
+#endif
+
+/**
+ * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets
+ */
+#if !defined CHECKSUM_CHECK_ICMP6 || defined __DOXYGEN__
+#define CHECKSUM_CHECK_ICMP6            1
+#endif
+
+/**
+ * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
+ * application buffers to pbufs.
+ */
+#if !defined LWIP_CHECKSUM_ON_COPY || defined __DOXYGEN__
+#define LWIP_CHECKSUM_ON_COPY           0
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------------
+   ---------- IPv6 options ---------------
+   ---------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_ipv6 IPv6
+ * @ingroup lwip_opts
+ * @{
+ */
+/**
+ * LWIP_IPV6==1: Enable IPv6
+ */
+#if !defined LWIP_IPV6 || defined __DOXYGEN__
+#define LWIP_IPV6                       0
+#endif
+
+/**
+ * IPV6_REASS_MAXAGE: Maximum time (in multiples of IP6_REASS_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#if !defined IPV6_REASS_MAXAGE || defined __DOXYGEN__
+#define IPV6_REASS_MAXAGE               60
+#endif
+
+/**
+ * LWIP_IPV6_SCOPES==1: Enable support for IPv6 address scopes, ensuring that
+ * e.g. link-local addresses are really treated as link-local. Disable this
+ * setting only for single-interface configurations.
+ * All addresses that have a scope according to the default policy (link-local
+ * unicast addresses, interface-local and link-local multicast addresses) should
+ * now have a zone set on them before being passed to the core API, although
+ * lwIP will currently attempt to select a zone on the caller's behalf when 
+ * necessary. Applications that directly assign IPv6 addresses to interfaces
+ * (which is NOT recommended) must now ensure that link-local addresses carry
+ * the netif's zone. See the new ip6_zone.h header file for more information and
+ * relevant macros. For now it is still possible to turn off scopes support
+ * through the new LWIP_IPV6_SCOPES option. When upgrading an implementation that
+ * uses the core API directly, it is highly recommended to enable
+ * LWIP_IPV6_SCOPES_DEBUG at least for a while, to ensure e.g. proper address
+ * initialization.
+ */
+#if !defined LWIP_IPV6_SCOPES || defined __DOXYGEN__
+#define LWIP_IPV6_SCOPES                (LWIP_IPV6 && !LWIP_SINGLE_NETIF)
+#endif
+
+/**
+ * LWIP_IPV6_SCOPES_DEBUG==1: Perform run-time checks to verify that addresses
+ * are properly zoned (see ip6_zone.h on what that means) where it matters.
+ * Enabling this setting is highly recommended when upgrading from an existing
+ * installation that is not yet scope-aware; otherwise it may be too expensive.
+ */
+#if !defined LWIP_IPV6_SCOPES_DEBUG || defined __DOXYGEN__
+#define LWIP_IPV6_SCOPES_DEBUG          0
+#endif
+
+/**
+ * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif.
+ */
+#if !defined LWIP_IPV6_NUM_ADDRESSES || defined __DOXYGEN__
+#define LWIP_IPV6_NUM_ADDRESSES         3
+#endif
+
+/**
+ * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs
+ */
+#if !defined LWIP_IPV6_FORWARD || defined __DOXYGEN__
+#define LWIP_IPV6_FORWARD               0
+#endif
+
+/**
+ * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big.
+ */
+#if !defined LWIP_IPV6_FRAG || defined __DOXYGEN__
+#define LWIP_IPV6_FRAG                  1
+#endif
+
+/**
+ * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented
+ */
+#if !defined LWIP_IPV6_REASS || defined __DOXYGEN__
+#define LWIP_IPV6_REASS                 LWIP_IPV6
+#endif
+
+/**
+ * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during
+ * network startup.
+ */
+#if !defined LWIP_IPV6_SEND_ROUTER_SOLICIT || defined __DOXYGEN__
+#define LWIP_IPV6_SEND_ROUTER_SOLICIT   1
+#endif
+
+/**
+ * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862.
+ */
+#if !defined LWIP_IPV6_AUTOCONFIG || defined __DOXYGEN__
+#define LWIP_IPV6_AUTOCONFIG            LWIP_IPV6
+#endif
+
+/**
+ * LWIP_IPV6_ADDRESS_LIFETIMES==1: Keep valid and preferred lifetimes for each
+ * IPv6 address. Required for LWIP_IPV6_AUTOCONFIG. May still be enabled
+ * otherwise, in which case the application may assign address lifetimes with
+ * the appropriate macros. Addresses with no lifetime are assumed to be static.
+ * If this option is disabled, all addresses are assumed to be static.
+ */
+#if !defined LWIP_IPV6_ADDRESS_LIFETIMES || defined __DOXYGEN__
+#define LWIP_IPV6_ADDRESS_LIFETIMES     LWIP_IPV6_AUTOCONFIG
+#endif
+
+/**
+ * LWIP_IPV6_DUP_DETECT_ATTEMPTS=[0..7]: Number of duplicate address detection attempts.
+ */
+#if !defined LWIP_IPV6_DUP_DETECT_ATTEMPTS || defined __DOXYGEN__
+#define LWIP_IPV6_DUP_DETECT_ATTEMPTS   1
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_icmp6 ICMP6
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC)
+ */
+#if !defined LWIP_ICMP6 || defined __DOXYGEN__
+#define LWIP_ICMP6                      LWIP_IPV6
+#endif
+
+/**
+ * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in
+ * ICMPv6 error messages.
+ */
+#if !defined LWIP_ICMP6_DATASIZE || defined __DOXYGEN__
+#define LWIP_ICMP6_DATASIZE             8
+#endif
+
+/**
+ * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages
+ */
+#if !defined LWIP_ICMP6_HL || defined __DOXYGEN__
+#define LWIP_ICMP6_HL                   255
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_mld6 Multicast listener discovery
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol.
+ * If LWIP_IPV6 is enabled but this setting is disabled, the MAC layer must
+ * indiscriminately pass all inbound IPv6 multicast traffic to lwIP.
+ */
+#if !defined LWIP_IPV6_MLD || defined __DOXYGEN__
+#define LWIP_IPV6_MLD                   LWIP_IPV6
+#endif
+
+/**
+ * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast groups that can be joined.
+ * There must be enough groups so that each netif can join the solicited-node
+ * multicast group for each of its local addresses, plus one for MDNS if
+ * applicable, plus any number of groups to be joined on UDP sockets.
+ */
+#if !defined MEMP_NUM_MLD6_GROUP || defined __DOXYGEN__
+#define MEMP_NUM_MLD6_GROUP             4
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_nd6 Neighbor discovery
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address
+ * is being resolved.
+ */
+#if !defined LWIP_ND6_QUEUEING || defined __DOXYGEN__
+#define LWIP_ND6_QUEUEING               LWIP_IPV6
+#endif
+
+/**
+ * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution.
+ */
+#if !defined MEMP_NUM_ND6_QUEUE || defined __DOXYGEN__
+#define MEMP_NUM_ND6_QUEUE              20
+#endif
+
+/**
+ * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache
+ */
+#if !defined LWIP_ND6_NUM_NEIGHBORS || defined __DOXYGEN__
+#define LWIP_ND6_NUM_NEIGHBORS          10
+#endif
+
+/**
+ * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache
+ */
+#if !defined LWIP_ND6_NUM_DESTINATIONS || defined __DOXYGEN__
+#define LWIP_ND6_NUM_DESTINATIONS       10
+#endif
+
+/**
+ * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache
+ */
+#if !defined LWIP_ND6_NUM_PREFIXES || defined __DOXYGEN__
+#define LWIP_ND6_NUM_PREFIXES           5
+#endif
+
+/**
+ * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache
+ */
+#if !defined LWIP_ND6_NUM_ROUTERS || defined __DOXYGEN__
+#define LWIP_ND6_NUM_ROUTERS            3
+#endif
+
+/**
+ * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send
+ * (neighbor solicit and router solicit)
+ */
+#if !defined LWIP_ND6_MAX_MULTICAST_SOLICIT || defined __DOXYGEN__
+#define LWIP_ND6_MAX_MULTICAST_SOLICIT  3
+#endif
+
+/**
+ * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages
+ * to send during neighbor reachability detection.
+ */
+#if !defined LWIP_ND6_MAX_UNICAST_SOLICIT || defined __DOXYGEN__
+#define LWIP_ND6_MAX_UNICAST_SOLICIT    3
+#endif
+
+/**
+ * Unused: See ND RFC (time in milliseconds).
+ */
+#if !defined LWIP_ND6_MAX_ANYCAST_DELAY_TIME || defined __DOXYGEN__
+#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000
+#endif
+
+/**
+ * Unused: See ND RFC
+ */
+#if !defined LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT || defined __DOXYGEN__
+#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT  3
+#endif
+
+/**
+ * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds).
+ * May be updated by router advertisement messages.
+ */
+#if !defined LWIP_ND6_REACHABLE_TIME || defined __DOXYGEN__
+#define LWIP_ND6_REACHABLE_TIME         30000
+#endif
+
+/**
+ * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages
+ */
+#if !defined LWIP_ND6_RETRANS_TIMER || defined __DOXYGEN__
+#define LWIP_ND6_RETRANS_TIMER          1000
+#endif
+
+/**
+ * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation
+ * message is sent, during neighbor reachability detection.
+ */
+#if !defined LWIP_ND6_DELAY_FIRST_PROBE_TIME || defined __DOXYGEN__
+#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000
+#endif
+
+/**
+ * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update
+ * Reachable time and retransmission timers, and netif MTU.
+ */
+#if !defined LWIP_ND6_ALLOW_RA_UPDATES || defined __DOXYGEN__
+#define LWIP_ND6_ALLOW_RA_UPDATES       1
+#endif
+
+/**
+ * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery
+ * with reachability hints for connected destinations. This helps avoid sending
+ * unicast neighbor solicitation messages.
+ */
+#if !defined LWIP_ND6_TCP_REACHABILITY_HINTS || defined __DOXYGEN__
+#define LWIP_ND6_TCP_REACHABILITY_HINTS 1
+#endif
+
+/**
+ * LWIP_ND6_RDNSS_MAX_DNS_SERVERS > 0: Use IPv6 Router Advertisement Recursive
+ * DNS Server Option (as per RFC 6106) to copy a defined maximum number of DNS
+ * servers to the DNS module.
+ */
+#if !defined LWIP_ND6_RDNSS_MAX_DNS_SERVERS || defined __DOXYGEN__
+#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS  0
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup lwip_opts_dhcpv6 DHCPv6
+ * @ingroup lwip_opts_ipv6
+ * @{
+ */
+/**
+ * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful/stateless address autoconfiguration.
+ */
+#if !defined LWIP_IPV6_DHCP6 || defined __DOXYGEN__
+#define LWIP_IPV6_DHCP6                 0
+#endif
+
+/**
+ * LWIP_IPV6_DHCP6_STATEFUL==1: enable DHCPv6 stateful address autoconfiguration.
+ * (not supported, yet!)
+ */
+#if !defined LWIP_IPV6_DHCP6_STATEFUL || defined __DOXYGEN__
+#define LWIP_IPV6_DHCP6_STATEFUL        0
+#endif
+
+/**
+ * LWIP_IPV6_DHCP6_STATELESS==1: enable DHCPv6 stateless address autoconfiguration.
+ */
+#if !defined LWIP_IPV6_DHCP6_STATELESS || defined __DOXYGEN__
+#define LWIP_IPV6_DHCP6_STATELESS       LWIP_IPV6_DHCP6
+#endif
+
+/**
+ * LWIP_DHCP6_GETS_NTP==1: Request NTP servers via DHCPv6. For each
+ * response packet, a callback is called, which has to be provided by the port:
+ * void dhcp6_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs);
+*/
+#if !defined LWIP_DHCP6_GET_NTP_SRV || defined __DOXYGEN__
+#define LWIP_DHCP6_GET_NTP_SRV          0
+#endif
+
+/**
+ * The maximum of NTP servers requested
+ */
+#if !defined LWIP_DHCP6_MAX_NTP_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP6_MAX_NTP_SERVERS      1
+#endif
+
+/**
+ * LWIP_DHCP6_MAX_DNS_SERVERS > 0: Request DNS servers via DHCPv6.
+ * DNS servers received in the response are passed to DNS via @ref dns_setserver()
+ * (up to the maximum limit defined here).
+ */
+#if !defined LWIP_DHCP6_MAX_DNS_SERVERS || defined __DOXYGEN__
+#define LWIP_DHCP6_MAX_DNS_SERVERS      DNS_MAX_SERVERS
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------------
+   ---------- Hook options ---------------
+   ---------------------------------------
+*/
+
+/**
+ * @defgroup lwip_opts_hooks Hooks
+ * @ingroup lwip_opts_infrastructure
+ * Hooks are undefined by default, define them to a function if you need them.
+ * @{
+ */
+
+/**
+ * LWIP_HOOK_FILENAME: Custom filename to \#include in files that provide hooks.
+ * Declare your hook function prototypes in there, you may also \#include all headers
+ * providing data types that are need in this file.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_FILENAME "path/to/my/lwip_hooks.h"
+#endif
+
+/**
+ * LWIP_HOOK_TCP_ISN:
+ * Hook for generation of the Initial Sequence Number (ISN) for a new TCP
+ * connection. The default lwIP ISN generation algorithm is very basic and may
+ * allow for TCP spoofing attacks. This hook provides the means to implement
+ * the standardized ISN generation algorithm from RFC 6528 (see contrib/adons/tcp_isn),
+ * or any other desired algorithm as a replacement.
+ * Called from tcp_connect() and tcp_listen_input() when an ISN is needed for
+ * a new TCP connection, if TCP support (@ref LWIP_TCP) is enabled.\n
+ * Signature:\code{.c}
+ * u32_t my_hook_tcp_isn(const ip_addr_t* local_ip, u16_t local_port, const ip_addr_t* remote_ip, u16_t remote_port);
+ * \endcode
+ * - it may be necessary to use "struct ip_addr" (ip4_addr, ip6_addr) instead of "ip_addr_t" in function declarations\n
+ * Arguments:
+ * - local_ip: pointer to the local IP address of the connection
+ * - local_port: local port number of the connection (host-byte order)
+ * - remote_ip: pointer to the remote IP address of the connection
+ * - remote_port: remote port number of the connection (host-byte order)\n
+ * Return value:
+ * - the 32-bit Initial Sequence Number to use for the new TCP connection.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_ISN(local_ip, local_port, remote_ip, remote_port)
+#endif
+
+/**
+ * LWIP_HOOK_TCP_INPACKET_PCB:
+ * Hook for intercepting incoming packets before they are passed to a pcb. This
+ * allows updating some state or even dropping a packet.
+ * Signature:\code{.c}
+ * err_t my_hook_tcp_inpkt(struct tcp_pcb *pcb, struct tcp_hdr *hdr, u16_t optlen, u16_t opt1len, u8_t *opt2, struct pbuf *p);
+ * \endcode
+ * Arguments:
+ * - pcb: tcp_pcb selected for input of this packet (ATTENTION: this may be
+ *        struct tcp_pcb_listen if pcb->state == LISTEN)
+ * - hdr: pointer to tcp header (ATTENTION: tcp options may not be in one piece!)
+ * - optlen: tcp option length
+ * - opt1len: tcp option length 1st part
+ * - opt2: if this is != NULL, tcp options are split among 2 pbufs. In that case,
+ *         options start at right after the tcp header ('(u8_t*)(hdr + 1)') for
+ *         the first 'opt1len' bytes and the rest starts at 'opt2'. opt2len can
+ *         be simply calculated: 'opt2len = optlen - opt1len;'
+ * - p: input packet, p->payload points to application data (that's why tcp hdr
+ *      and options are passed in seperately)
+ * Return value:
+ * - ERR_OK: continue input of this packet as normal
+ * - != ERR_OK: drop this packet for input (don't continue input processing)
+ *
+ * ATTENTION: don't call any tcp api functions that might change tcp state (pcb
+ * state or any pcb lists) from this callback!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_INPACKET_PCB(pcb, hdr, optlen, opt1len, opt2, p)
+#endif
+
+/**
+ * LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH:
+ * Hook for increasing the size of the options allocated with a tcp header.
+ * Together with LWIP_HOOK_TCP_OUT_ADD_TCPOPTS, this can be used to add custom
+ * options to outgoing tcp segments.
+ * Signature:\code{.c}
+ * u8_t my_hook_tcp_out_tcpopt_length(const struct tcp_pcb *pcb, u8_t internal_option_length);
+ * \endcode
+ * Arguments:
+ * - pcb: tcp_pcb that transmits (ATTENTION: this may be NULL or
+ *        struct tcp_pcb_listen if pcb->state == LISTEN)
+ * - internal_option_length: tcp option length used by the stack internally
+ * Return value:
+ * - a number of bytes to allocate for tcp options (internal_option_length <= ret <= 40)
+ *
+ * ATTENTION: don't call any tcp api functions that might change tcp state (pcb
+ * state or any pcb lists) from this callback!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH(pcb, internal_len)
+#endif
+
+/**
+ * LWIP_HOOK_TCP_OUT_ADD_TCPOPTS:
+ * Hook for adding custom options to outgoing tcp segments.
+ * Space for these custom options has to be reserved via LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH.
+ * Signature:\code{.c}
+ * u32_t *my_hook_tcp_out_add_tcpopts(struct pbuf *p, struct tcp_hdr *hdr, const struct tcp_pcb *pcb, u32_t *opts);
+ * \endcode
+ * Arguments:
+ * - p: output packet, p->payload pointing to tcp header, data follows
+ * - hdr: tcp header
+ * - pcb: tcp_pcb that transmits (ATTENTION: this may be NULL or
+ *        struct tcp_pcb_listen if pcb->state == LISTEN)
+ * - opts: pointer where to add the custom options (there may already be options
+ *         between the header and these)
+ * Return value:
+ * - pointer pointing directly after the inserted options
+ *
+ * ATTENTION: don't call any tcp api functions that might change tcp state (pcb
+ * state or any pcb lists) from this callback!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, hdr, pcb, opts)
+#endif
+
+/**
+ * LWIP_HOOK_IP4_INPUT(pbuf, input_netif):
+ * Called from ip_input() (IPv4)
+ * Signature:\code{.c}
+ *   int my_hook(struct pbuf *pbuf, struct netif *input_netif);
+ * \endcode
+ * Arguments:
+ * - pbuf: received struct pbuf passed to ip_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_INPUT(pbuf, input_netif)
+#endif
+
+/**
+ * LWIP_HOOK_IP4_ROUTE(dest):
+ * Called from ip_route() (IPv4)
+ * Signature:\code{.c}
+ *   struct netif *my_hook(const ip4_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - dest: destination IPv4 address
+ * Returns values:
+ * - the destination netif
+ * - NULL if no destination netif is found. In that case, ip_route() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_ROUTE()
+#endif
+
+/**
+ * LWIP_HOOK_IP4_ROUTE_SRC(src, dest):
+ * Source-based routing for IPv4 - called from ip_route() (IPv4)
+ * Signature:\code{.c}
+ *   struct netif *my_hook(const ip4_addr_t *src, const ip4_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - src: local/source IPv4 address
+ * - dest: destination IPv4 address
+ * Returns values:
+ * - the destination netif
+ * - NULL if no destination netif is found. In that case, ip_route() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_ROUTE_SRC(src, dest)
+#endif
+
+/**
+ * LWIP_HOOK_IP4_CANFORWARD(src, dest):
+ * Check if an IPv4 can be forwarded - called from:
+ * ip4_input() -> ip4_forward() -> ip4_canforward() (IPv4)
+ * - source address is available via ip4_current_src_addr()
+ * - calling an output function in this context (e.g. multicast router) is allowed
+ * Signature:\code{.c}
+ *   int my_hook(struct pbuf *p, u32_t dest_addr_hostorder);
+ * \endcode
+ * Arguments:
+ * - p: packet to forward
+ * - dest: destination IPv4 address
+ * Returns values:
+ * - 1: forward
+ * - 0: don't forward
+ * - -1: no decision. In that case, ip4_canforward() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP4_CANFORWARD(src, dest)
+#endif
+
+/**
+ * LWIP_HOOK_ETHARP_GET_GW(netif, dest):
+ * Called from etharp_output() (IPv4)
+ * Signature:\code{.c}
+ *   const ip4_addr_t *my_hook(struct netif *netif, const ip4_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - netif: the netif used for sending
+ * - dest: the destination IPv4 address
+ * Return values:
+ * - the IPv4 address of the gateway to handle the specified destination IPv4 address
+ * - NULL, in which case the netif's default gateway is used
+ *
+ * The returned address MUST be directly reachable on the specified netif!
+ * This function is meant to implement advanced IPv4 routing together with
+ * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is
+ * not part of lwIP but can e.g. be hidden in the netif's state argument.
+*/
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_ETHARP_GET_GW(netif, dest)
+#endif
+
+/**
+ * LWIP_HOOK_IP6_INPUT(pbuf, input_netif):
+ * Called from ip6_input() (IPv6)
+ * Signature:\code{.c}
+ *   int my_hook(struct pbuf *pbuf, struct netif *input_netif);
+ * \endcode
+ * Arguments:
+ * - pbuf: received struct pbuf passed to ip6_input()
+ * - input_netif: struct netif on which the packet has been received
+ * Return values:
+ * - 0: Hook has not consumed the packet, packet is processed as normal
+ * - != 0: Hook has consumed the packet.
+ * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
+ * (i.e. free it when done).
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP6_INPUT(pbuf, input_netif)
+#endif
+
+/**
+ * LWIP_HOOK_IP6_ROUTE(src, dest):
+ * Called from ip_route() (IPv6)
+ * Signature:\code{.c}
+ *   struct netif *my_hook(const ip6_addr_t *dest, const ip6_addr_t *src);
+ * \endcode
+ * Arguments:
+ * - src: source IPv6 address
+ * - dest: destination IPv6 address
+ * Return values:
+ * - the destination netif
+ * - NULL if no destination netif is found. In that case, ip6_route() continues as normal.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_IP6_ROUTE(src, dest)
+#endif
+
+/**
+ * LWIP_HOOK_ND6_GET_GW(netif, dest):
+ * Called from nd6_get_next_hop_entry() (IPv6)
+ * Signature:\code{.c}
+ *   const ip6_addr_t *my_hook(struct netif *netif, const ip6_addr_t *dest);
+ * \endcode
+ * Arguments:
+ * - netif: the netif used for sending
+ * - dest: the destination IPv6 address
+ * Return values:
+ * - the IPv6 address of the next hop to handle the specified destination IPv6 address
+ * - NULL, in which case a NDP-discovered router is used instead
+ *
+ * The returned address MUST be directly reachable on the specified netif!
+ * This function is meant to implement advanced IPv6 routing together with
+ * LWIP_HOOK_IP6_ROUTE(). The actual routing/gateway table implementation is
+ * not part of lwIP but can e.g. be hidden in the netif's state argument.
+*/
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_ND6_GET_GW(netif, dest)
+#endif
+
+/**
+ * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr):
+ * Called from ethernet_input() if VLAN support is enabled
+ * Signature:\code{.c}
+ *   int my_hook(struct netif *netif, struct eth_hdr *eth_hdr, struct eth_vlan_hdr *vlan_hdr);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif on which the packet has been received
+ * - eth_hdr: struct eth_hdr of the packet
+ * - vlan_hdr: struct eth_vlan_hdr of the packet
+ * Return values:
+ * - 0: Packet must be dropped.
+ * - != 0: Packet must be accepted.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr)
+#endif
+
+/**
+ * LWIP_HOOK_VLAN_SET:
+ * Hook can be used to set prio_vid field of vlan_hdr. If you need to store data
+ * on per-netif basis to implement this callback, see @ref netif_cd.
+ * Called from ethernet_output() if VLAN support (@ref ETHARP_SUPPORT_VLAN) is enabled.\n
+ * Signature:\code{.c}
+ *   s32_t my_hook_vlan_set(struct netif* netif, struct pbuf* pbuf, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);\n
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - p: struct pbuf packet to be sent
+ * - src: source eth address
+ * - dst: destination eth address
+ * - eth_type: ethernet type to packet to be sent\n
+ * 
+ * 
+ * Return values:
+ * - &lt;0: Packet shall not contain VLAN header.
+ * - 0 &lt;= return value &lt;= 0xFFFF: Packet shall contain VLAN header. Return value is prio_vid in host byte order.
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type)
+#endif
+
+/**
+ * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type):
+ * Called from memp_free() when a memp pool was empty and an item is now available
+ * Signature:\code{.c}
+ *   void my_hook(memp_t type);
+ * \endcode
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_MEMP_AVAILABLE(memp_t_type)
+#endif
+
+/**
+ * LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif):
+ * Called from ethernet_input() when an unknown eth type is encountered.
+ * Signature:\code{.c}
+ *   err_t my_hook(struct pbuf* pbuf, struct netif* netif);
+ * \endcode
+ * Arguments:
+ * - p: rx packet with unknown eth type
+ * - netif: netif on which the packet has been received
+ * Return values:
+ * - ERR_OK if packet is accepted (hook function now owns the pbuf)
+ * - any error code otherwise (pbuf is freed)
+ *
+ * Payload points to ethernet header!
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif)
+#endif
+
+/**
+ * LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr):
+ * Called from various dhcp functions when sending a DHCP message.
+ * This hook is called just before the DHCP message trailer is added, so the
+ * options are at the end of a DHCP message.
+ * Signature:\code{.c}
+ *   void my_hook(struct netif *netif, struct dhcp *dhcp, u8_t state, struct dhcp_msg *msg,
+ *                u8_t msg_type, u16_t *options_len_ptr);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - dhcp: struct dhcp on that netif
+ * - state: current dhcp state (dhcp_state_enum_t as an u8_t)
+ * - msg: struct dhcp_msg that will be sent
+ * - msg_type: dhcp message type to be sent (u8_t)
+ * - options_len_ptr: pointer to the current length of options in the dhcp_msg "msg"
+ *                    (must be increased when options are added!)
+ *
+ * Options need to appended like this:
+ *   LWIP_ASSERT("dhcp option overflow", *options_len_ptr + option_len + 2 <= DHCP_OPTIONS_LEN);
+ *   msg->options[(*options_len_ptr)++] = &lt;option_number&gt;;
+ *   msg->options[(*options_len_ptr)++] = &lt;option_len&gt;;
+ *   msg->options[(*options_len_ptr)++] = &lt;option_bytes&gt;;
+ *   [...]
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr)
+#endif
+
+/**
+ * LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, option_value_offset):
+ * Called from dhcp_parse_reply when receiving a DHCP message.
+ * This hook is called for every option in the received message that is not handled internally.
+ * Signature:\code{.c}
+ *   void my_hook(struct netif *netif, struct dhcp *dhcp, u8_t state, struct dhcp_msg *msg,
+ *                u8_t msg_type, u8_t option, u8_t option_len, struct pbuf *pbuf, u16_t option_value_offset);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - dhcp: struct dhcp on that netif
+ * - state: current dhcp state (dhcp_state_enum_t as an u8_t)
+ * - msg: struct dhcp_msg that was received
+ * - msg_type: dhcp message type received (u8_t, ATTENTION: only valid after
+ *             the message type option has been parsed!)
+ * - option: option value (u8_t)
+ * - len: option data length (u8_t)
+ * - pbuf: pbuf where option data is contained
+ * - option_value_offset: offset in pbuf where option data begins
+ *
+ * A nice way to get the option contents is pbuf_get_contiguous():
+ *  u8_t buf[32];
+ *  u8_t *ptr = (u8_t*)pbuf_get_contiguous(p, buf, sizeof(buf), LWIP_MIN(option_len, sizeof(buf)), offset);
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, offset)
+#endif
+
+/**
+ * LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len):
+ * Called from various dhcp6 functions when sending a DHCP6 message.
+ * This hook is called just before the DHCP6 message is sent, so the
+ * options are at the end of a DHCP6 message.
+ * Signature:\code{.c}
+ *   void my_hook(struct netif *netif, struct dhcp6 *dhcp, u8_t state, struct dhcp6_msg *msg,
+ *                u8_t msg_type, u16_t *options_len_ptr);
+ * \endcode
+ * Arguments:
+ * - netif: struct netif that the packet will be sent through
+ * - dhcp6: struct dhcp6 on that netif
+ * - state: current dhcp6 state (dhcp6_state_enum_t as an u8_t)
+ * - msg: struct dhcp6_msg that will be sent
+ * - msg_type: dhcp6 message type to be sent (u8_t)
+ * - options_len_ptr: pointer to the current length of options in the dhcp6_msg "msg"
+ *                    (must be increased when options are added!)
+ *
+ * Options need to appended like this:
+ *   u8_t *options = (u8_t *)(msg + 1);
+ *   LWIP_ASSERT("dhcp option overflow", sizeof(struct dhcp6_msg) + *options_len_ptr + newoptlen <= max_len);
+ *   options[(*options_len_ptr)++] = &lt;option_data&gt;;
+ *   [...]
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len)
+#endif
+
+/**
+ * LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+ * Called from socket API to implement setsockopt() for options not provided by lwIP.
+ * Core lock is held when this hook is called.
+ * Signature:\code{.c}
+ *   int my_hook(int s, struct lwip_sock *sock, int level, int optname, const void *optval, socklen_t optlen, int *err)
+ * \endcode
+ * Arguments:
+ * - s: socket file descriptor
+ * - sock: internal socket descriptor (see lwip/priv/sockets_priv.h)
+ * - level: protocol level at which the option resides
+ * - optname: option to set
+ * - optval: value to set
+ * - optlen: size of optval
+ * - err: output error
+ * Return values:
+ * - 0: Hook has not consumed the option, code continues as normal (to internal options)
+ * - != 0: Hook has consumed the option, 'err' is returned
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+#endif
+
+/**
+ * LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+ * Called from socket API to implement getsockopt() for options not provided by lwIP.
+ * Core lock is held when this hook is called.
+ * Signature:\code{.c}
+ *   int my_hook(int s, struct lwip_sock *sock, int level, int optname, void *optval, socklen_t *optlen, int *err)
+ * \endcode
+ * Arguments:
+ * - s: socket file descriptor
+ * - sock: internal socket descriptor (see lwip/priv/sockets_priv.h)
+ * - level: protocol level at which the option resides
+ * - optname: option to get
+ * - optval: value to get
+ * - optlen: size of optval
+ * - err: output error
+ * Return values:
+ * - 0: Hook has not consumed the option, code continues as normal (to internal options)
+ * - != 0: Hook has consumed the option, 'err' is returned
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, err)
+#endif
+
+/**
+ * LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, addrtype, err)
+ * Called from netconn APIs (not usable with callback apps) allowing an
+ * external DNS resolver (which uses sequential API) to handle the query.
+ * Signature:\code{.c}
+ *   int my_hook(const char *name, ip_addr_t *addr, u8_t addrtype, err_t *err)
+ * \endcode
+ * Arguments:
+ * - name: hostname to resolve
+ * - addr: output host address
+ * - addrtype: type of address to query
+ * - err: output error
+ * Return values:
+ * - 0: Hook has not consumed hostname query, query continues into DNS module
+ * - != 0: Hook has consumed the query
+ *
+ * err must also be checked to determine if the hook consumed the query, but
+ * the query failed
+ */
+#ifdef __DOXYGEN__
+#define LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, addrtype, err)
+#endif
+/**
+ * @}
+ */
+
+/*
+   ---------------------------------------
+   ---------- Debugging options ----------
+   ---------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_debugmsg Debug messages
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ * @see debugging_levels
+ */
+#if !defined LWIP_DBG_MIN_LEVEL || defined __DOXYGEN__
+#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ * @see debugging_levels
+ */
+#if !defined LWIP_DBG_TYPES_ON || defined __DOXYGEN__
+#define LWIP_DBG_TYPES_ON               LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#if !defined ETHARP_DEBUG || defined __DOXYGEN__
+#define ETHARP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#if !defined NETIF_DEBUG || defined __DOXYGEN__
+#define NETIF_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#if !defined PBUF_DEBUG || defined __DOXYGEN__
+#define PBUF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#if !defined API_LIB_DEBUG || defined __DOXYGEN__
+#define API_LIB_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#if !defined API_MSG_DEBUG || defined __DOXYGEN__
+#define API_MSG_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#if !defined SOCKETS_DEBUG || defined __DOXYGEN__
+#define SOCKETS_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#if !defined ICMP_DEBUG || defined __DOXYGEN__
+#define ICMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#if !defined IGMP_DEBUG || defined __DOXYGEN__
+#define IGMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#if !defined INET_DEBUG || defined __DOXYGEN__
+#define INET_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#if !defined IP_DEBUG || defined __DOXYGEN__
+#define IP_DEBUG                        LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#if !defined IP_REASS_DEBUG || defined __DOXYGEN__
+#define IP_REASS_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#if !defined RAW_DEBUG || defined __DOXYGEN__
+#define RAW_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#if !defined MEM_DEBUG || defined __DOXYGEN__
+#define MEM_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#if !defined MEMP_DEBUG || defined __DOXYGEN__
+#define MEMP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#if !defined SYS_DEBUG || defined __DOXYGEN__
+#define SYS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TIMERS_DEBUG: Enable debugging in timers.c.
+ */
+#if !defined TIMERS_DEBUG || defined __DOXYGEN__
+#define TIMERS_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#if !defined TCP_DEBUG || defined __DOXYGEN__
+#define TCP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#if !defined TCP_INPUT_DEBUG || defined __DOXYGEN__
+#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#if !defined TCP_FR_DEBUG || defined __DOXYGEN__
+#define TCP_FR_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#if !defined TCP_RTO_DEBUG || defined __DOXYGEN__
+#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#if !defined TCP_CWND_DEBUG || defined __DOXYGEN__
+#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#if !defined TCP_WND_DEBUG || defined __DOXYGEN__
+#define TCP_WND_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#if !defined TCP_OUTPUT_DEBUG || defined __DOXYGEN__
+#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#if !defined TCP_RST_DEBUG || defined __DOXYGEN__
+#define TCP_RST_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#if !defined TCP_QLEN_DEBUG || defined __DOXYGEN__
+#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#if !defined UDP_DEBUG || defined __DOXYGEN__
+#define UDP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#if !defined TCPIP_DEBUG || defined __DOXYGEN__
+#define TCPIP_DEBUG                     LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#if !defined SLIP_DEBUG || defined __DOXYGEN__
+#define SLIP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#if !defined DHCP_DEBUG || defined __DOXYGEN__
+#define DHCP_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#if !defined AUTOIP_DEBUG || defined __DOXYGEN__
+#define AUTOIP_DEBUG                    LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#if !defined DNS_DEBUG || defined __DOXYGEN__
+#define DNS_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * IP6_DEBUG: Enable debugging for IPv6.
+ */
+#if !defined IP6_DEBUG || defined __DOXYGEN__
+#define IP6_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP6_DEBUG: Enable debugging in dhcp6.c.
+ */
+#if !defined DHCP6_DEBUG || defined __DOXYGEN__
+#define DHCP6_DEBUG                     LWIP_DBG_OFF
+#endif
+/**
+ * @}
+ */
+
+/**
+ * LWIP_TESTMODE: Changes to make unit test possible
+ */
+#if !defined LWIP_TESTMODE
+#define LWIP_TESTMODE                   0
+#endif
+
+/*
+   --------------------------------------------------
+   ---------- Performance tracking options ----------
+   --------------------------------------------------
+*/
+/**
+ * @defgroup lwip_opts_perf Performance
+ * @ingroup lwip_opts_debug
+ * @{
+ */
+/**
+ * LWIP_PERF: Enable performance testing for lwIP
+ * (if enabled, arch/perf.h is included)
+ */
+#if !defined LWIP_PERF || defined __DOXYGEN__
+#define LWIP_PERF                       0
+#endif
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_OPT_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/pbuf.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/pbuf.h
new file mode 100644
index 000000000..82902a4e9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/pbuf.h
@@ -0,0 +1,322 @@
+/**
+ * @file
+ * pbuf API
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef LWIP_HDR_PBUF_H
+#define LWIP_HDR_PBUF_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LWIP_SUPPORT_CUSTOM_PBUF==1: Custom pbufs behave much like their pbuf type
+ * but they are allocated by external code (initialised by calling
+ * pbuf_alloced_custom()) and when pbuf_free gives up their last reference, they
+ * are freed by calling pbuf_custom->custom_free_function().
+ * Currently, the pbuf_custom code is only needed for one specific configuration
+ * of IP_FRAG, unless required by external driver/application code. */
+#ifndef LWIP_SUPPORT_CUSTOM_PBUF
+#define LWIP_SUPPORT_CUSTOM_PBUF ((IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG))
+#endif
+
+/** @ingroup pbuf 
+ * PBUF_NEEDS_COPY(p): return a boolean value indicating whether the given
+ * pbuf needs to be copied in order to be kept around beyond the current call
+ * stack without risking being corrupted. The default setting provides safety:
+ * it will make a copy iof any pbuf chain that does not consist entirely of
+ * PBUF_ROM type pbufs. For setups with zero-copy support, it may be redefined
+ * to evaluate to true in all cases, for example. However, doing so also has an
+ * effect on the application side: any buffers that are *not* copied must also
+ * *not* be reused by the application after passing them to lwIP. For example,
+ * when setting PBUF_NEEDS_COPY to (0), after using udp_send() with a PBUF_RAM
+ * pbuf, the application must free the pbuf immediately, rather than reusing it
+ * for other purposes. For more background information on this, see tasks #6735
+ * and #7896, and bugs #11400 and #49914. */
+#ifndef PBUF_NEEDS_COPY
+#define PBUF_NEEDS_COPY(p)  ((p)->type_internal & PBUF_TYPE_FLAG_DATA_VOLATILE)
+#endif /* PBUF_NEEDS_COPY */
+
+/* @todo: We need a mechanism to prevent wasting memory in every pbuf
+   (TCP vs. UDP, IPv4 vs. IPv6: UDP/IPv4 packets may waste up to 28 bytes) */
+
+#define PBUF_TRANSPORT_HLEN 20
+#if LWIP_IPV6
+#define PBUF_IP_HLEN        40
+#else
+#define PBUF_IP_HLEN        20
+#endif
+
+/**
+ * @ingroup pbuf
+ * Enumeration of pbuf layers
+ */
+typedef enum {
+  /** Includes spare room for transport layer header, e.g. UDP header.
+   * Use this if you intend to pass the pbuf to functions like udp_send().
+   */
+  PBUF_TRANSPORT = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN,
+  /** Includes spare room for IP header.
+   * Use this if you intend to pass the pbuf to functions like raw_send().
+   */
+  PBUF_IP = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN,
+  /** Includes spare room for link layer header (ethernet header).
+   * Use this if you intend to pass the pbuf to functions like ethernet_output().
+   * @see PBUF_LINK_HLEN
+   */
+  PBUF_LINK = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN,
+  /** Includes spare room for additional encapsulation header before ethernet
+   * headers (e.g. 802.11).
+   * Use this if you intend to pass the pbuf to functions like netif->linkoutput().
+   * @see PBUF_LINK_ENCAPSULATION_HLEN
+   */
+  PBUF_RAW_TX = PBUF_LINK_ENCAPSULATION_HLEN,
+  /** Use this for input packets in a netif driver when calling netif->input()
+   * in the most common case - ethernet-layer netif driver. */
+  PBUF_RAW = 0
+} pbuf_layer;
+
+
+/* Base flags for pbuf_type definitions: */
+
+/** Indicates that the payload directly follows the struct pbuf.
+ *  This makes @ref pbuf_header work in both directions. */
+#define PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS       0x80
+/** Indicates the data stored in this pbuf can change. If this pbuf needs
+ * to be queued, it must be copied/duplicated. */
+#define PBUF_TYPE_FLAG_DATA_VOLATILE                0x40
+/** 4 bits are reserved for 16 allocation sources (e.g. heap, pool1, pool2, etc)
+ * Internally, we use: 0=heap, 1=MEMP_PBUF, 2=MEMP_PBUF_POOL -> 13 types free*/
+#define PBUF_TYPE_ALLOC_SRC_MASK                    0x0F
+/** Indicates this pbuf is used for RX (if not set, indicates use for TX).
+ * This information can be used to keep some spare RX buffers e.g. for
+ * receiving TCP ACKs to unblock a connection) */
+#define PBUF_ALLOC_FLAG_RX                          0x0100
+/** Indicates the application needs the pbuf payload to be in one piece */
+#define PBUF_ALLOC_FLAG_DATA_CONTIGUOUS             0x0200
+
+#define PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP           0x00
+#define PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF      0x01
+#define PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL 0x02
+/** First pbuf allocation type for applications */
+#define PBUF_TYPE_ALLOC_SRC_MASK_APP_MIN            0x03
+/** Last pbuf allocation type for applications */
+#define PBUF_TYPE_ALLOC_SRC_MASK_APP_MAX            PBUF_TYPE_ALLOC_SRC_MASK
+
+/**
+ * @ingroup pbuf
+ * Enumeration of pbuf types
+ */
+typedef enum {
+  /** pbuf data is stored in RAM, used for TX mostly, struct pbuf and its payload
+      are allocated in one piece of contiguous memory (so the first payload byte
+      can be calculated from struct pbuf).
+      pbuf_alloc() allocates PBUF_RAM pbufs as unchained pbufs (although that might
+      change in future versions).
+      This should be used for all OUTGOING packets (TX).*/
+  PBUF_RAM = (PBUF_ALLOC_FLAG_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP),
+  /** pbuf data is stored in ROM, i.e. struct pbuf and its payload are located in
+      totally different memory areas. Since it points to ROM, payload does not
+      have to be copied when queued for transmission. */
+  PBUF_ROM = PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF,
+  /** pbuf comes from the pbuf pool. Much like PBUF_ROM but payload might change
+      so it has to be duplicated when queued before transmitting, depending on
+      who has a 'ref' to it. */
+  PBUF_REF = (PBUF_TYPE_FLAG_DATA_VOLATILE | PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF),
+  /** pbuf payload refers to RAM. This one comes from a pool and should be used
+      for RX. Payload can be chained (scatter-gather RX) but like PBUF_RAM, struct
+      pbuf and its payload are allocated in one piece of contiguous memory (so
+      the first payload byte can be calculated from struct pbuf).
+      Don't use this for TX, if the pool becomes empty e.g. because of TCP queuing,
+      you are unable to receive TCP acks! */
+  PBUF_POOL = (PBUF_ALLOC_FLAG_RX | PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL)
+} pbuf_type;
+
+
+/** indicates this packet's data should be immediately passed to the application */
+#define PBUF_FLAG_PUSH      0x01U
+/** indicates this is a custom pbuf: pbuf_free calls pbuf_custom->custom_free_function()
+    when the last reference is released (plus custom PBUF_RAM cannot be trimmed) */
+#define PBUF_FLAG_IS_CUSTOM 0x02U
+/** indicates this pbuf is UDP multicast to be looped back */
+#define PBUF_FLAG_MCASTLOOP 0x04U
+/** indicates this pbuf was received as link-level broadcast */
+#define PBUF_FLAG_LLBCAST   0x08U
+/** indicates this pbuf was received as link-level multicast */
+#define PBUF_FLAG_LLMCAST   0x10U
+/** indicates this pbuf includes a TCP FIN flag */
+#define PBUF_FLAG_TCP_FIN   0x20U
+
+/** Main packet buffer struct */
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+
+  /** length of this buffer */
+  u16_t len;
+
+  /** a bit field indicating pbuf type and allocation sources
+      (see PBUF_TYPE_FLAG_*, PBUF_ALLOC_FLAG_* and PBUF_TYPE_ALLOC_SRC_MASK)
+    */
+  u8_t type_internal;
+
+  /** misc flags */
+  u8_t flags;
+
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  LWIP_PBUF_REF_T ref;
+
+  /** For incoming packets, this contains the input netif's index */
+  u8_t if_idx;
+};
+
+
+/** Helper struct for const-correctness only.
+ * The only meaning of this one is to provide a const payload pointer
+ * for PBUF_ROM type.
+ */
+struct pbuf_rom {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  const void *payload;
+};
+
+#if LWIP_SUPPORT_CUSTOM_PBUF
+/** Prototype for a function to free a custom pbuf */
+typedef void (*pbuf_free_custom_fn)(struct pbuf *p);
+
+/** A custom pbuf: like a pbuf, but following a function pointer to free it. */
+struct pbuf_custom {
+  /** The actual pbuf */
+  struct pbuf pbuf;
+  /** This function is called when pbuf_free deallocates this pbuf(_custom) */
+  pbuf_free_custom_fn custom_free_function;
+};
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+
+/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */
+#ifndef PBUF_POOL_FREE_OOSEQ
+#define PBUF_POOL_FREE_OOSEQ 1
+#endif /* PBUF_POOL_FREE_OOSEQ */
+#if LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ
+extern volatile u8_t pbuf_free_ooseq_pending;
+void pbuf_free_ooseq(void);
+/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ()
+    at regular intervals from main level to check if ooseq pbufs need to be
+    freed! */
+#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \
+  /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \
+     ooseq queued pbufs now */ \
+  pbuf_free_ooseq(); }}while(0)
+#else /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ */
+  /* Otherwise declare an empty PBUF_CHECK_FREE_OOSEQ */
+  #define PBUF_CHECK_FREE_OOSEQ()
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ*/
+
+/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
+#define pbuf_init()
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type);
+struct pbuf *pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type);
+#if LWIP_SUPPORT_CUSTOM_PBUF
+struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type,
+                                 struct pbuf_custom *p, void *payload_mem,
+                                 u16_t payload_mem_len);
+#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
+void pbuf_realloc(struct pbuf *p, u16_t size);
+#define pbuf_get_allocsrc(p)          ((p)->type_internal & PBUF_TYPE_ALLOC_SRC_MASK)
+#define pbuf_match_allocsrc(p, type)  (pbuf_get_allocsrc(p) == ((type) & PBUF_TYPE_ALLOC_SRC_MASK))
+#define pbuf_match_type(p, type)      pbuf_match_allocsrc(p, type)
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+u8_t pbuf_header_force(struct pbuf *p, s16_t header_size);
+u8_t pbuf_add_header(struct pbuf *p, size_t header_size_increment);
+u8_t pbuf_add_header_force(struct pbuf *p, size_t header_size_increment);
+u8_t pbuf_remove_header(struct pbuf *p, size_t header_size);
+struct pbuf *pbuf_free_header(struct pbuf *q, u16_t size);
+void pbuf_ref(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u16_t pbuf_clen(const struct pbuf *p);
+void pbuf_cat(struct pbuf *head, struct pbuf *tail);
+void pbuf_chain(struct pbuf *head, struct pbuf *tail);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+err_t pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from);
+u16_t pbuf_copy_partial(const struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
+void *pbuf_get_contiguous(const struct pbuf *p, void *buffer, size_t bufsize, u16_t len, u16_t offset);
+err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len);
+err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset);
+struct pbuf *pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset);
+struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer);
+struct pbuf *pbuf_clone(pbuf_layer l, pbuf_type type, struct pbuf *p);
+#if LWIP_CHECKSUM_ON_COPY
+err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
+                       u16_t len, u16_t *chksum);
+#endif /* LWIP_CHECKSUM_ON_COPY */
+#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
+void pbuf_split_64k(struct pbuf *p, struct pbuf **rest);
+#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
+
+u8_t pbuf_get_at(const struct pbuf* p, u16_t offset);
+int pbuf_try_get_at(const struct pbuf* p, u16_t offset);
+void pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data);
+u16_t pbuf_memcmp(const struct pbuf* p, u16_t offset, const void* s2, u16_t n);
+u16_t pbuf_memfind(const struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset);
+u16_t pbuf_strstr(const struct pbuf* p, const char* substr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PBUF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/altcp_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/altcp_priv.h
new file mode 100644
index 000000000..2d3b2fdbc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/altcp_priv.h
@@ -0,0 +1,146 @@
+/**
+ * @file
+ * Application layered TCP connection API (to be used from TCPIP thread)\n
+ * This interface mimics the tcp callback API to the application while preventing
+ * direct linking (much like virtual functions).
+ * This way, an application can make use of other application layer protocols
+ * on top of TCP without knowing the details (e.g. TLS, proxy connection).
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_ALTCP_PRIV_H
+#define LWIP_HDR_ALTCP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/altcp.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct altcp_pcb *altcp_alloc(void);
+void altcp_free(struct altcp_pcb *conn);
+
+/* Function prototypes for application layers */
+typedef void (*altcp_set_poll_fn)(struct altcp_pcb *conn, u8_t interval);
+typedef void (*altcp_recved_fn)(struct altcp_pcb *conn, u16_t len);
+typedef err_t (*altcp_bind_fn)(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port);
+typedef err_t (*altcp_connect_fn)(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected);
+
+typedef struct altcp_pcb *(*altcp_listen_fn)(struct altcp_pcb *conn, u8_t backlog, err_t *err);
+
+typedef void  (*altcp_abort_fn)(struct altcp_pcb *conn);
+typedef err_t (*altcp_close_fn)(struct altcp_pcb *conn);
+typedef err_t (*altcp_shutdown_fn)(struct altcp_pcb *conn, int shut_rx, int shut_tx);
+
+typedef err_t (*altcp_write_fn)(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags);
+typedef err_t (*altcp_output_fn)(struct altcp_pcb *conn);
+
+typedef u16_t (*altcp_mss_fn)(struct altcp_pcb *conn);
+typedef u16_t (*altcp_sndbuf_fn)(struct altcp_pcb *conn);
+typedef u16_t (*altcp_sndqueuelen_fn)(struct altcp_pcb *conn);
+typedef void  (*altcp_nagle_disable_fn)(struct altcp_pcb *conn);
+typedef void  (*altcp_nagle_enable_fn)(struct altcp_pcb *conn);
+typedef int   (*altcp_nagle_disabled_fn)(struct altcp_pcb *conn);
+
+typedef void  (*altcp_setprio_fn)(struct altcp_pcb *conn, u8_t prio);
+
+typedef void  (*altcp_dealloc_fn)(struct altcp_pcb *conn);
+
+typedef err_t (*altcp_get_tcp_addrinfo_fn)(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port);
+typedef ip_addr_t *(*altcp_get_ip_fn)(struct altcp_pcb *conn, int local);
+typedef u16_t (*altcp_get_port_fn)(struct altcp_pcb *conn, int local);
+
+#ifdef LWIP_DEBUG
+typedef enum tcp_state (*altcp_dbg_get_tcp_state_fn)(struct altcp_pcb *conn);
+#endif
+
+struct altcp_functions {
+  altcp_set_poll_fn           set_poll;
+  altcp_recved_fn             recved;
+  altcp_bind_fn               bind;
+  altcp_connect_fn            connect;
+  altcp_listen_fn             listen;
+  altcp_abort_fn              abort;
+  altcp_close_fn              close;
+  altcp_shutdown_fn           shutdown;
+  altcp_write_fn              write;
+  altcp_output_fn             output;
+  altcp_mss_fn                mss;
+  altcp_sndbuf_fn             sndbuf;
+  altcp_sndqueuelen_fn        sndqueuelen;
+  altcp_nagle_disable_fn      nagle_disable;
+  altcp_nagle_enable_fn       nagle_enable;
+  altcp_nagle_disabled_fn     nagle_disabled;
+  altcp_setprio_fn            setprio;
+  altcp_dealloc_fn            dealloc;
+  altcp_get_tcp_addrinfo_fn   addrinfo;
+  altcp_get_ip_fn             getip;
+  altcp_get_port_fn           getport;
+#ifdef LWIP_DEBUG
+  altcp_dbg_get_tcp_state_fn  dbg_get_tcp_state;
+#endif
+};
+
+void  altcp_default_set_poll(struct altcp_pcb *conn, u8_t interval);
+void  altcp_default_recved(struct altcp_pcb *conn, u16_t len);
+err_t altcp_default_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port);
+err_t altcp_default_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx);
+err_t altcp_default_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags);
+err_t altcp_default_output(struct altcp_pcb *conn);
+u16_t altcp_default_mss(struct altcp_pcb *conn);
+u16_t altcp_default_sndbuf(struct altcp_pcb *conn);
+u16_t altcp_default_sndqueuelen(struct altcp_pcb *conn);
+void  altcp_default_nagle_disable(struct altcp_pcb *conn);
+void  altcp_default_nagle_enable(struct altcp_pcb *conn);
+int   altcp_default_nagle_disabled(struct altcp_pcb *conn);
+void  altcp_default_setprio(struct altcp_pcb *conn, u8_t prio);
+void  altcp_default_dealloc(struct altcp_pcb *conn);
+err_t altcp_default_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port);
+ip_addr_t *altcp_default_get_ip(struct altcp_pcb *conn, int local);
+u16_t altcp_default_get_port(struct altcp_pcb *conn, int local);
+#ifdef LWIP_DEBUG
+enum tcp_state altcp_default_dbg_get_tcp_state(struct altcp_pcb *conn);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_ALTCP */
+
+#endif /* LWIP_HDR_ALTCP_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/api_msg.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/api_msg.h
new file mode 100644
index 000000000..9e8ffc9ea
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/api_msg.h
@@ -0,0 +1,272 @@
+/**
+ * @file
+ * netconn API lwIP internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_API_MSG_H
+#define LWIP_HDR_API_MSG_H
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/sys.h"
+#include "lwip/igmp.h"
+#include "lwip/api.h"
+#include "lwip/priv/tcpip_priv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+/* Note: Netconn API is always available when sockets are enabled -
+ * sockets are implemented on top of them */
+
+#if LWIP_MPU_COMPATIBLE
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define API_MSG_M_DEF_SEM(m)  *m
+#else
+#define API_MSG_M_DEF_SEM(m)  API_MSG_M_DEF(m)
+#endif
+#else /* LWIP_MPU_COMPATIBLE */
+#define API_MSG_M_DEF_SEM(m)  API_MSG_M_DEF(m)
+#endif /* LWIP_MPU_COMPATIBLE */
+
+/* For the netconn API, these values are use as a bitmask! */
+#define NETCONN_SHUT_RD   1
+#define NETCONN_SHUT_WR   2
+#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR)
+
+/* IP addresses and port numbers are expected to be in
+ * the same byte order as in the corresponding pcb.
+ */
+/** This struct includes everything that is necessary to execute a function
+    for a netconn in another thread context (mainly used to process netconns
+    in the tcpip_thread context to be thread safe). */
+struct api_msg {
+  /** The netconn which to process - always needed: it includes the semaphore
+      which is used to block the application thread until the function finished. */
+  struct netconn *conn;
+  /** The return value of the function executed in tcpip_thread. */
+  err_t err;
+  /** Depending on the executed function, one of these union members is used */
+  union {
+    /** used for lwip_netconn_do_send */
+    struct netbuf *b;
+    /** used for lwip_netconn_do_newconn */
+    struct {
+      u8_t proto;
+    } n;
+    /** used for lwip_netconn_do_bind and lwip_netconn_do_connect */
+    struct {
+      API_MSG_M_DEF_C(ip_addr_t, ipaddr);
+      u16_t port;
+      u8_t if_idx;
+    } bc;
+    /** used for lwip_netconn_do_getaddr */
+    struct {
+      ip_addr_t API_MSG_M_DEF(ipaddr);
+      u16_t API_MSG_M_DEF(port);
+      u8_t local;
+    } ad;
+    /** used for lwip_netconn_do_write */
+    struct {
+      /** current vector to write */
+      const struct netvector *vector;
+      /** number of unwritten vectors */
+      u16_t vector_cnt;
+      /** offset into current vector */
+      size_t vector_off;
+      /** total length across vectors */
+      size_t len;
+      /** offset into total length/output of bytes written when err == ERR_OK */
+      size_t offset;
+      u8_t apiflags;
+#if LWIP_SO_SNDTIMEO
+      u32_t time_started;
+#endif /* LWIP_SO_SNDTIMEO */
+    } w;
+    /** used for lwip_netconn_do_recv */
+    struct {
+      size_t len;
+    } r;
+#if LWIP_TCP
+    /** used for lwip_netconn_do_close (/shutdown) */
+    struct {
+      u8_t shut;
+#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
+      u32_t time_started;
+#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+      u8_t polls_left;
+#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
+    } sd;
+#endif /* LWIP_TCP */
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+    /** used for lwip_netconn_do_join_leave_group */
+    struct {
+      API_MSG_M_DEF_C(ip_addr_t, multiaddr);
+      API_MSG_M_DEF_C(ip_addr_t, netif_addr);
+      u8_t if_idx;
+      enum netconn_igmp join_or_leave;
+    } jl;
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+#if TCP_LISTEN_BACKLOG
+    struct {
+      u8_t backlog;
+    } lb;
+#endif /* TCP_LISTEN_BACKLOG */
+  } msg;
+#if LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_t* op_completed_sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+};
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define LWIP_API_MSG_SEM(msg)          ((msg)->op_completed_sem)
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define LWIP_API_MSG_SEM(msg)          (&(msg)->conn->op_completed)
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+
+#if LWIP_DNS
+/** As lwip_netconn_do_gethostbyname requires more arguments but doesn't require a netconn,
+    it has its own struct (to avoid struct api_msg getting bigger than necessary).
+    lwip_netconn_do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
+    (see netconn_gethostbyname). */
+struct dns_api_msg {
+  /** Hostname to query or dotted IP address string */
+#if LWIP_MPU_COMPATIBLE
+  char name[DNS_MAX_NAME_LENGTH];
+#else /* LWIP_MPU_COMPATIBLE */
+  const char *name;
+#endif /* LWIP_MPU_COMPATIBLE */
+  /** The resolved address is stored here */
+  ip_addr_t API_MSG_M_DEF(addr);
+#if LWIP_IPV4 && LWIP_IPV6
+  /** Type of resolve call */
+  u8_t dns_addrtype;
+#endif /* LWIP_IPV4 && LWIP_IPV6 */
+  /** This semaphore is posted when the name is resolved, the application thread
+      should wait on it. */
+  sys_sem_t API_MSG_M_DEF_SEM(sem);
+  /** Errors are given back here */
+  err_t API_MSG_M_DEF(err);
+};
+#endif /* LWIP_DNS */
+
+#if LWIP_NETCONN_FULLDUPLEX
+int lwip_netconn_is_deallocated_msg(void *msg);
+#endif
+int lwip_netconn_is_err_msg(void *msg, err_t *err);
+void lwip_netconn_do_newconn         (void *m);
+void lwip_netconn_do_delconn         (void *m);
+void lwip_netconn_do_bind            (void *m);
+void lwip_netconn_do_bind_if         (void *m);
+void lwip_netconn_do_connect         (void *m);
+void lwip_netconn_do_disconnect      (void *m);
+void lwip_netconn_do_listen          (void *m);
+void lwip_netconn_do_send            (void *m);
+void lwip_netconn_do_recv            (void *m);
+#if TCP_LISTEN_BACKLOG
+void lwip_netconn_do_accepted        (void *m);
+#endif /* TCP_LISTEN_BACKLOG */
+void lwip_netconn_do_write           (void *m);
+void lwip_netconn_do_getaddr         (void *m);
+void lwip_netconn_do_close           (void *m);
+void lwip_netconn_do_shutdown        (void *m);
+#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
+void lwip_netconn_do_join_leave_group(void *m);
+void lwip_netconn_do_join_leave_group_netif(void *m);
+#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
+
+#if LWIP_DNS
+void lwip_netconn_do_gethostbyname(void *arg);
+#endif /* LWIP_DNS */
+
+struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
+void netconn_free(struct netconn *conn);
+
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
+
+/* netifapi related lwIP internal definitions */
+
+#if LWIP_MPU_COMPATIBLE
+#define NETIFAPI_IPADDR_DEF(type, m)  type m
+#else /* LWIP_MPU_COMPATIBLE */
+#define NETIFAPI_IPADDR_DEF(type, m)  const type * m
+#endif /* LWIP_MPU_COMPATIBLE */
+
+typedef void (*netifapi_void_fn)(struct netif *netif);
+typedef err_t (*netifapi_errt_fn)(struct netif *netif);
+
+struct netifapi_msg {
+  struct tcpip_api_call_data call;
+  struct netif *netif;
+  union {
+    struct {
+#if LWIP_IPV4
+      NETIFAPI_IPADDR_DEF(ip4_addr_t, ipaddr);
+      NETIFAPI_IPADDR_DEF(ip4_addr_t, netmask);
+      NETIFAPI_IPADDR_DEF(ip4_addr_t, gw);
+#endif /* LWIP_IPV4 */
+      void *state;
+      netif_init_fn init;
+      netif_input_fn input;
+    } add;
+    struct {
+      netifapi_void_fn voidfunc;
+      netifapi_errt_fn errtfunc;
+    } common;
+    struct {
+#if LWIP_MPU_COMPATIBLE
+      char name[NETIF_NAMESIZE];
+#else /* LWIP_MPU_COMPATIBLE */
+      char *name;
+#endif /* LWIP_MPU_COMPATIBLE */
+      u8_t index;
+    } ifs;
+  } msg;
+};
+
+#endif /* LWIP_NETIF_API */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_API_MSG_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/mem_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/mem_priv.h
new file mode 100644
index 000000000..8630d7541
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/mem_priv.h
@@ -0,0 +1,84 @@
+/**
+ * @file
+ * lwIP internal memory implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2018 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#ifndef LWIP_HDR_MEM_PRIV_H
+#define LWIP_HDR_MEM_PRIV_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/mem.h"
+
+#if MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK
+/* if MEM_OVERFLOW_CHECK or MEMP_OVERFLOW_CHECK is turned on, we reserve some
+ * bytes at the beginning and at the end of each element, initialize them as
+ * 0xcd and check them later.
+ * If MEM(P)_OVERFLOW_CHECK is >= 2, on every call to mem(p)_malloc or mem(p)_free,
+ * every single element in each pool/heap is checked!
+ * This is VERY SLOW but also very helpful.
+ * MEM_SANITY_REGION_BEFORE and MEM_SANITY_REGION_AFTER can be overridden in
+ * lwipopts.h to change the amount reserved for checking. */
+#ifndef MEM_SANITY_REGION_BEFORE
+#define MEM_SANITY_REGION_BEFORE  16
+#endif /* MEM_SANITY_REGION_BEFORE*/
+#if MEM_SANITY_REGION_BEFORE > 0
+#define MEM_SANITY_REGION_BEFORE_ALIGNED    LWIP_MEM_ALIGN_SIZE(MEM_SANITY_REGION_BEFORE)
+#else
+#define MEM_SANITY_REGION_BEFORE_ALIGNED    0
+#endif /* MEM_SANITY_REGION_BEFORE*/
+#ifndef MEM_SANITY_REGION_AFTER
+#define MEM_SANITY_REGION_AFTER   16
+#endif /* MEM_SANITY_REGION_AFTER*/
+#if MEM_SANITY_REGION_AFTER > 0
+#define MEM_SANITY_REGION_AFTER_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEM_SANITY_REGION_AFTER)
+#else
+#define MEM_SANITY_REGION_AFTER_ALIGNED     0
+#endif /* MEM_SANITY_REGION_AFTER*/
+
+void mem_overflow_init_raw(void *p, size_t size);
+void mem_overflow_check_raw(void *p, size_t size, const char *descr1, const char *descr2);
+
+#endif /* MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/memp_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/memp_priv.h
new file mode 100644
index 000000000..1f14cb162
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/memp_priv.h
@@ -0,0 +1,161 @@
+/**
+ * @file
+ * memory pools lwIP internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef LWIP_HDR_MEMP_PRIV_H
+#define LWIP_HDR_MEMP_PRIV_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lwip/mem.h"
+#include "lwip/priv/mem_priv.h"
+
+#if MEMP_OVERFLOW_CHECK
+
+
+/* MEMP_SIZE: save space for struct memp and for sanity check */
+#define MEMP_SIZE          (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEM_SANITY_REGION_BEFORE_ALIGNED)
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEM_SANITY_REGION_AFTER_ALIGNED)
+
+#else /* MEMP_OVERFLOW_CHECK */
+
+/* No sanity checks
+ * We don't need to preserve the struct memp while not allocated, so we
+ * can save a little space and set MEMP_SIZE to 0.
+ */
+#define MEMP_SIZE           0
+#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
+
+#endif /* MEMP_OVERFLOW_CHECK */
+
+#if !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK
+struct memp {
+  struct memp *next;
+#if MEMP_OVERFLOW_CHECK
+  const char *file;
+  int line;
+#endif /* MEMP_OVERFLOW_CHECK */
+};
+#endif /* !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK */
+
+#if MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS
+/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
+typedef enum {
+    /* Get the first (via:
+       MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
+    MEMP_POOL_HELPER_FIRST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START 1
+#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
+#define LWIP_MALLOC_MEMPOOL_END
+#include "lwip/priv/memp_std.h"
+    ) ,
+    /* Get the last (via:
+       MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
+    MEMP_POOL_HELPER_LAST = ((u8_t)
+#define LWIP_MEMPOOL(name,num,size,desc)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
+#define LWIP_MALLOC_MEMPOOL_END 1
+#include "lwip/priv/memp_std.h"
+    )
+} memp_pool_helper_t;
+
+/* The actual start and stop values are here (cast them over)
+   We use this helper type and these defines so we can avoid using const memp_t values */
+#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
+#define MEMP_POOL_LAST   ((memp_t) MEMP_POOL_HELPER_LAST)
+#endif /* MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS */
+
+/** Memory pool descriptor */
+struct memp_desc {
+#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY
+  /** Textual description */
+  const char *desc;
+#endif /* LWIP_DEBUG || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY */
+#if MEMP_STATS
+  /** Statistics */
+  struct stats_mem *stats;
+#endif
+
+  /** Element size */
+  u16_t size;
+
+#if !MEMP_MEM_MALLOC
+  /** Number of elements */
+  u16_t num;
+
+  /** Base address */
+  u8_t *base;
+
+  /** First free element of each pool. Elements form a linked list. */
+  struct memp **tab;
+#endif /* MEMP_MEM_MALLOC */
+};
+
+#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY
+#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc),
+#else
+#define DECLARE_LWIP_MEMPOOL_DESC(desc)
+#endif
+
+#if MEMP_STATS
+#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) static struct stats_mem name;
+#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) &name,
+#else
+#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name)
+#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name)
+#endif
+
+void memp_init_pool(const struct memp_desc *desc);
+
+#if MEMP_OVERFLOW_CHECK
+void *memp_malloc_pool_fn(const struct memp_desc* desc, const char* file, const int line);
+#define memp_malloc_pool(d) memp_malloc_pool_fn((d), __FILE__, __LINE__)
+#else
+void *memp_malloc_pool(const struct memp_desc *desc);
+#endif
+void  memp_free_pool(const struct memp_desc* desc, void *mem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_MEMP_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/memp_std.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/memp_std.h
new file mode 100644
index 000000000..669ad4d7e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/memp_std.h
@@ -0,0 +1,153 @@
+/**
+ * @file
+ * lwIP internal memory pools (do not use in application code)
+ * This file is deliberately included multiple times: once with empty
+ * definition of LWIP_MEMPOOL() to handle all includes and multiple times
+ * to build up various lists of mem pools.
+ */
+
+/*
+ * SETUP: Make sure we define everything we will need.
+ *
+ * We have create three types of pools:
+ *   1) MEMPOOL - standard pools
+ *   2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
+ *   3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
+ *
+ * If the include'r doesn't require any special treatment of each of the types
+ * above, then will declare #2 & #3 to be just standard mempools.
+ */
+#ifndef LWIP_MALLOC_MEMPOOL
+/* This treats "malloc pools" just like any other pool.
+   The pools are a little bigger to provide 'size' as the amount of user data. */
+#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))), "MALLOC_"#size)
+#define LWIP_MALLOC_MEMPOOL_START
+#define LWIP_MALLOC_MEMPOOL_END
+#endif /* LWIP_MALLOC_MEMPOOL */
+
+#ifndef LWIP_PBUF_MEMPOOL
+/* This treats "pbuf pools" just like any other pool.
+ * Allocates buffers for a pbuf struct AND a payload size */
+#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) + LWIP_MEM_ALIGN_SIZE(payload)), desc)
+#endif /* LWIP_PBUF_MEMPOOL */
+
+
+/*
+ * A list of internal pools used by LWIP.
+ *
+ * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ */
+#if LWIP_RAW
+LWIP_MEMPOOL(RAW_PCB,        MEMP_NUM_RAW_PCB,         sizeof(struct raw_pcb),        "RAW_PCB")
+#endif /* LWIP_RAW */
+
+#if LWIP_UDP
+LWIP_MEMPOOL(UDP_PCB,        MEMP_NUM_UDP_PCB,         sizeof(struct udp_pcb),        "UDP_PCB")
+#endif /* LWIP_UDP */
+
+#if LWIP_TCP
+LWIP_MEMPOOL(TCP_PCB,        MEMP_NUM_TCP_PCB,         sizeof(struct tcp_pcb),        "TCP_PCB")
+LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN,  sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
+LWIP_MEMPOOL(TCP_SEG,        MEMP_NUM_TCP_SEG,         sizeof(struct tcp_seg),        "TCP_SEG")
+#endif /* LWIP_TCP */
+
+#if LWIP_ALTCP && LWIP_TCP
+LWIP_MEMPOOL(ALTCP_PCB,      MEMP_NUM_ALTCP_PCB,       sizeof(struct altcp_pcb),      "ALTCP_PCB")
+#endif /* LWIP_ALTCP && LWIP_TCP */
+
+#if LWIP_IPV4 && IP_REASSEMBLY
+LWIP_MEMPOOL(REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip_reassdata),   "REASSDATA")
+#endif /* LWIP_IPV4 && IP_REASSEMBLY */
+#if (IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG)
+LWIP_MEMPOOL(FRAG_PBUF,      MEMP_NUM_FRAG_PBUF,       sizeof(struct pbuf_custom_ref),"FRAG_PBUF")
+#endif /* IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF || (LWIP_IPV6 && LWIP_IPV6_FRAG) */
+
+#if LWIP_NETCONN || LWIP_SOCKET
+LWIP_MEMPOOL(NETBUF,         MEMP_NUM_NETBUF,          sizeof(struct netbuf),         "NETBUF")
+LWIP_MEMPOOL(NETCONN,        MEMP_NUM_NETCONN,         sizeof(struct netconn),        "NETCONN")
+#endif /* LWIP_NETCONN || LWIP_SOCKET */
+
+#if NO_SYS==0
+LWIP_MEMPOOL(TCPIP_MSG_API,  MEMP_NUM_TCPIP_MSG_API,   sizeof(struct tcpip_msg),      "TCPIP_MSG_API")
+#if LWIP_MPU_COMPATIBLE
+LWIP_MEMPOOL(API_MSG,        MEMP_NUM_API_MSG,         sizeof(struct api_msg),        "API_MSG")
+#if LWIP_DNS
+LWIP_MEMPOOL(DNS_API_MSG,    MEMP_NUM_DNS_API_MSG,     sizeof(struct dns_api_msg),    "DNS_API_MSG")
+#endif
+#if LWIP_SOCKET && !LWIP_TCPIP_CORE_LOCKING
+LWIP_MEMPOOL(SOCKET_SETGETSOCKOPT_DATA, MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA, sizeof(struct lwip_setgetsockopt_data), "SOCKET_SETGETSOCKOPT_DATA")
+#endif
+#if LWIP_SOCKET && (LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL)
+LWIP_MEMPOOL(SELECT_CB,      MEMP_NUM_SELECT_CB,       sizeof(struct lwip_select_cb), "SELECT_CB")
+#endif /* LWIP_SOCKET && (LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL) */
+#if LWIP_NETIF_API
+LWIP_MEMPOOL(NETIFAPI_MSG,   MEMP_NUM_NETIFAPI_MSG,    sizeof(struct netifapi_msg),   "NETIFAPI_MSG")
+#endif
+#endif /* LWIP_MPU_COMPATIBLE */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg),      "TCPIP_MSG_INPKT")
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+#endif /* NO_SYS==0 */
+
+#if LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING
+LWIP_MEMPOOL(ARP_QUEUE,      MEMP_NUM_ARP_QUEUE,       sizeof(struct etharp_q_entry), "ARP_QUEUE")
+#endif /* LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING */
+
+#if LWIP_IGMP
+LWIP_MEMPOOL(IGMP_GROUP,     MEMP_NUM_IGMP_GROUP,      sizeof(struct igmp_group),     "IGMP_GROUP")
+#endif /* LWIP_IGMP */
+
+#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM
+LWIP_MEMPOOL(SYS_TIMEOUT,    MEMP_NUM_SYS_TIMEOUT,     sizeof(struct sys_timeo),      "SYS_TIMEOUT")
+#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */
+
+#if LWIP_DNS && LWIP_SOCKET
+LWIP_MEMPOOL(NETDB,          MEMP_NUM_NETDB,           NETDB_ELEM_SIZE,               "NETDB")
+#endif /* LWIP_DNS && LWIP_SOCKET */
+#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+LWIP_MEMPOOL(LOCALHOSTLIST,  MEMP_NUM_LOCALHOSTLIST,   LOCALHOSTLIST_ELEM_SIZE,       "LOCALHOSTLIST")
+#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+#if LWIP_IPV6 && LWIP_ND6_QUEUEING
+LWIP_MEMPOOL(ND6_QUEUE,      MEMP_NUM_ND6_QUEUE,       sizeof(struct nd6_q_entry),    "ND6_QUEUE")
+#endif /* LWIP_IPV6 && LWIP_ND6_QUEUEING */
+
+#if LWIP_IPV6 && LWIP_IPV6_REASS
+LWIP_MEMPOOL(IP6_REASSDATA,  MEMP_NUM_REASSDATA,       sizeof(struct ip6_reassdata),  "IP6_REASSDATA")
+#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+LWIP_MEMPOOL(MLD6_GROUP,     MEMP_NUM_MLD6_GROUP,      sizeof(struct mld_group),      "MLD6_GROUP")
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+
+/*
+ * A list of pools of pbuf's used by LWIP.
+ *
+ * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
+ *     creates a pool name MEMP_pool_name. description is used in stats.c
+ *     This allocates enough space for the pbuf struct and a payload.
+ *     (Example: pbuf_payload_size=0 allocates only size for the struct)
+ */
+LWIP_MEMPOOL(PBUF,           MEMP_NUM_PBUF,            sizeof(struct pbuf),           "PBUF_REF/ROM")
+LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,           PBUF_POOL_BUFSIZE,             "PBUF_POOL")
+
+
+/*
+ * Allow for user-defined pools; this must be explicitly set in lwipopts.h
+ * since the default is to NOT look for lwippools.h
+ */
+#if MEMP_USE_CUSTOM_POOLS
+#include "lwippools.h"
+#endif /* MEMP_USE_CUSTOM_POOLS */
+
+/*
+ * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
+ * (#undef is ignored for something that is not defined)
+ */
+#undef LWIP_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL
+#undef LWIP_MALLOC_MEMPOOL_START
+#undef LWIP_MALLOC_MEMPOOL_END
+#undef LWIP_PBUF_MEMPOOL
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/nd6_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/nd6_priv.h
new file mode 100644
index 000000000..cc3007d97
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/nd6_priv.h
@@ -0,0 +1,142 @@
+/**
+ * @file
+ *
+ * Neighbor discovery and stateless address autoconfiguration for IPv6.
+ * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
+ * (Address autoconfiguration).
+ */
+
+/*
+ * Copyright (c) 2010 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_ND6_PRIV_H
+#define LWIP_HDR_ND6_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_ND6_QUEUEING
+/** struct for queueing outgoing packets for unknown address
+  * defined here to be accessed by memp.h
+  */
+struct nd6_q_entry {
+  struct nd6_q_entry *next;
+  struct pbuf *p;
+};
+#endif /* LWIP_ND6_QUEUEING */
+
+/** Struct for tables. */
+struct nd6_neighbor_cache_entry {
+  ip6_addr_t next_hop_address;
+  struct netif *netif;
+  u8_t lladdr[NETIF_MAX_HWADDR_LEN];
+  /*u32_t pmtu;*/
+#if LWIP_ND6_QUEUEING
+  /** Pointer to queue of pending outgoing packets on this entry. */
+  struct nd6_q_entry *q;
+#else /* LWIP_ND6_QUEUEING */
+  /** Pointer to a single pending outgoing packet on this entry. */
+  struct pbuf *q;
+#endif /* LWIP_ND6_QUEUEING */
+  u8_t state;
+  u8_t isrouter;
+  union {
+    u32_t reachable_time; /* in seconds */
+    u32_t delay_time;     /* ticks (ND6_TMR_INTERVAL) */
+    u32_t probes_sent;
+    u32_t stale_time;     /* ticks (ND6_TMR_INTERVAL) */
+  } counter;
+};
+
+struct nd6_destination_cache_entry {
+  ip6_addr_t destination_addr;
+  ip6_addr_t next_hop_addr;
+  u16_t pmtu;
+  u32_t age;
+};
+
+struct nd6_prefix_list_entry {
+  ip6_addr_t prefix;
+  struct netif *netif;
+  u32_t invalidation_timer; /* in seconds */
+};
+
+struct nd6_router_list_entry {
+  struct nd6_neighbor_cache_entry *neighbor_entry;
+  u32_t invalidation_timer; /* in seconds */
+  u8_t flags;
+};
+
+enum nd6_neighbor_cache_entry_state {
+  ND6_NO_ENTRY = 0,
+  ND6_INCOMPLETE,
+  ND6_REACHABLE,
+  ND6_STALE,
+  ND6_DELAY,
+  ND6_PROBE
+};
+
+#define ND6_HOPLIM 255 /* maximum hop limit, required in all ND packets */
+
+#define ND6_2HRS 7200 /* two hours, expressed in number of seconds */
+
+/* Router tables. */
+/* @todo make these static? and entries accessible through API? */
+extern struct nd6_neighbor_cache_entry neighbor_cache[];
+extern struct nd6_destination_cache_entry destination_cache[];
+extern struct nd6_prefix_list_entry prefix_list[];
+extern struct nd6_router_list_entry default_router_list[];
+
+/* Default values, can be updated by a RA message. */
+extern u32_t reachable_time;
+extern u32_t retrans_timer;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_ND6_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/raw_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/raw_priv.h
new file mode 100644
index 000000000..d4561d4f3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/raw_priv.h
@@ -0,0 +1,69 @@
+/**
+ * @file
+ * raw API internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_RAW_PRIV_H
+#define LWIP_HDR_RAW_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/raw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** return codes for raw_input */
+typedef enum raw_input_state
+{
+  RAW_INPUT_NONE = 0, /* pbuf did not match any pcbs */
+  RAW_INPUT_EATEN,    /* pbuf handed off and delivered to pcb */
+  RAW_INPUT_DELIVERED /* pbuf only delivered to pcb (pbuf can still be referenced) */
+} raw_input_state_t;
+
+/* The following functions are the lower layer interface to RAW. */
+raw_input_state_t raw_input(struct pbuf *p, struct netif *inp);
+
+void raw_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* LWIP_HDR_RAW_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/sockets_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/sockets_priv.h
new file mode 100644
index 000000000..d8f9904dc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/sockets_priv.h
@@ -0,0 +1,175 @@
+/**
+ * @file
+ * Sockets API internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. <joel.cunningham@garmin.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Joel Cunningham <joel.cunningham@me.com>
+ *
+ */
+#ifndef LWIP_HDR_SOCKETS_PRIV_H
+#define LWIP_HDR_SOCKETS_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/sockets.h"
+#include "lwip/sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+/** This is overridable for the rare case where more than 255 threads
+ * select on the same socket...
+ */
+#ifndef SELWAIT_T
+#define SELWAIT_T u8_t
+#endif
+
+union lwip_sock_lastdata {
+  struct netbuf *netbuf;
+  struct pbuf *pbuf;
+};
+
+/** Contains all internal pointers and states used for a socket */
+struct lwip_sock {
+  /** sockets currently are built on netconns, each socket has one netconn */
+  struct netconn *conn;
+  /** data that was left from the previous read */
+  union lwip_sock_lastdata lastdata;
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+  /** number of times data was received, set by event_callback(),
+      tested by the receive and select functions */
+  s16_t rcvevent;
+  /** number of times data was ACKed (free send buffer), set by event_callback(),
+      tested by select */
+  u16_t sendevent;
+  /** error happened for this socket, set by event_callback(), tested by select */
+  u16_t errevent;
+  /** counter of how many threads are waiting for this socket using select */
+  SELWAIT_T select_waiting;
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+#if LWIP_NETCONN_FULLDUPLEX
+  /* counter of how many threads are using a struct lwip_sock (not the 'int') */
+  u8_t fd_used;
+  /* status of pending close/delete actions */
+  u8_t fd_free_pending;
+#define LWIP_SOCK_FD_FREE_TCP  1
+#define LWIP_SOCK_FD_FREE_FREE 2
+#endif
+};
+
+#ifndef set_errno
+#define set_errno(err) do { if (err) { errno = (err); } } while(0)
+#endif
+
+#if !LWIP_TCPIP_CORE_LOCKING
+/** Maximum optlen used by setsockopt/getsockopt */
+#define LWIP_SETGETSOCKOPT_MAXOPTLEN LWIP_MAX(16, sizeof(struct ifreq))
+
+/** This struct is used to pass data to the set/getsockopt_internal
+ * functions running in tcpip_thread context (only a void* is allowed) */
+struct lwip_setgetsockopt_data {
+  /** socket index for which to change options */
+  int s;
+  /** level of the option to process */
+  int level;
+  /** name of the option to process */
+  int optname;
+  /** set: value to set the option to
+    * get: value of the option is stored here */
+#if LWIP_MPU_COMPATIBLE
+  u8_t optval[LWIP_SETGETSOCKOPT_MAXOPTLEN];
+#else
+  union {
+    void *p;
+    const void *pc;
+  } optval;
+#endif
+  /** size of *optval */
+  socklen_t optlen;
+  /** if an error occurs, it is temporarily stored here */
+  int err;
+  /** semaphore to wake up the calling task */
+  void* completed_sem;
+};
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+
+#ifdef __cplusplus
+}
+#endif
+
+struct lwip_sock* lwip_socket_dbg_get_socket(int fd);
+
+#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL
+
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define SELECT_SEM_T        sys_sem_t*
+#define SELECT_SEM_PTR(sem) (sem)
+#else /* LWIP_NETCONN_SEM_PER_THREAD */
+#define SELECT_SEM_T        sys_sem_t
+#define SELECT_SEM_PTR(sem) (&(sem))
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+
+/** Description for a task waiting in select */
+struct lwip_select_cb {
+  /** Pointer to the next waiting task */
+  struct lwip_select_cb *next;
+  /** Pointer to the previous waiting task */
+  struct lwip_select_cb *prev;
+#if LWIP_SOCKET_SELECT
+  /** readset passed to select */
+  fd_set *readset;
+  /** writeset passed to select */
+  fd_set *writeset;
+  /** unimplemented: exceptset passed to select */
+  fd_set *exceptset;
+#endif /* LWIP_SOCKET_SELECT */
+#if LWIP_SOCKET_POLL
+  /** fds passed to poll; NULL if select */
+  struct pollfd *poll_fds;
+  /** nfds passed to poll; 0 if select */
+  nfds_t poll_nfds;
+#endif /* LWIP_SOCKET_POLL */
+  /** don't signal the same semaphore twice: set to 1 when signalled */
+  int sem_signalled;
+  /** semaphore to wake up a task waiting for select */
+  SELECT_SEM_T sem;
+};
+#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_SOCKETS_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/tcp_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/tcp_priv.h
new file mode 100644
index 000000000..72f9126d4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/tcp_priv.h
@@ -0,0 +1,523 @@
+/**
+ * @file
+ * TCP internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_TCP_PRIV_H
+#define LWIP_HDR_TCP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcp.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/tcp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void             tcp_init    (void);  /* Initialize this module. */
+void             tcp_tmr     (void);  /* Must be called every
+                                         TCP_TMR_INTERVAL
+                                         ms. (Typically 250 ms). */
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+/* Call this from a netif driver (watch out for threading issues!) that has
+   returned a memory error on transmit and now has free buffers to send more.
+   This iterates all active pcbs that had an error and tries to call
+   tcp_output, so use this with care as it might slow down the system. */
+void             tcp_txnow   (void);
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+void             tcp_free    (struct tcp_pcb *pcb);
+void             tcp_abandon (struct tcp_pcb *pcb, int reset);
+err_t            tcp_send_empty_ack(struct tcp_pcb *pcb);
+err_t            tcp_rexmit  (struct tcp_pcb *pcb);
+err_t            tcp_rexmit_rto_prepare(struct tcp_pcb *pcb);
+void             tcp_rexmit_rto_commit(struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+void             tcp_rexmit_fast (struct tcp_pcb *pcb);
+u32_t            tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb);
+err_t            tcp_process_refused_data(struct tcp_pcb *pcb);
+
+/**
+ * This is the Nagle algorithm: try to combine user data to send as few TCP
+ * segments as possible. Only send if
+ * - no previously transmitted data on the connection remains unacknowledged or
+ * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or
+ * - the only unsent segment is at least pcb->mss bytes long (or there is more
+ *   than one unsent segment - with lwIP, this can happen although unsent->len < mss)
+ * - or if we are in fast-retransmit (TF_INFR)
+ */
+#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
+                            ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \
+                            (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \
+                              ((tpcb)->unsent->len >= (tpcb)->mss))) || \
+                            ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \
+                            ) ? 1 : 0)
+#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
+
+#ifndef TCP_MSL
+#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */
+#endif
+
+/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
+#ifndef  TCP_KEEPIDLE_DEFAULT
+#define  TCP_KEEPIDLE_DEFAULT     7200000UL /* Default KEEPALIVE timer in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPINTVL_DEFAULT
+#define  TCP_KEEPINTVL_DEFAULT    75000UL   /* Default Time between KEEPALIVE probes in milliseconds */
+#endif
+
+#ifndef  TCP_KEEPCNT_DEFAULT
+#define  TCP_KEEPCNT_DEFAULT      9U        /* Default Counter for KEEPALIVE probes */
+#endif
+
+#define  TCP_MAXIDLE              TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT  /* Maximum KEEPALIVE probe time */
+
+#define TCP_TCPLEN(seg) ((seg)->len + (((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0) ? 1U : 0U))
+
+/** Flags used on input processing, not on pcb->flags
+*/
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was successfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+
+
+#if LWIP_EVENT_API
+
+#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) ret = lwip_tcp_event(arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, NULL, 0, ERR_OK)
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       do { if ((pcb)->state != SYN_RCVD) {                          \
+                ret = lwip_tcp_event((pcb)->callback_arg, (pcb), LWIP_EVENT_POLL, NULL, 0, ERR_OK); \
+                } else {                                                                            \
+                ret = ERR_ARG; } } while(0)
+/* For event API, last state SYN_RCVD must be excluded here: the application
+   has not seen this pcb, yet! */
+#define TCP_EVENT_ERR(last_state,errf,arg,err)  do { if (last_state != SYN_RCVD) {                \
+                lwip_tcp_event((arg), NULL, LWIP_EVENT_ERR, NULL, 0, (err)); } } while(0)
+
+#else /* LWIP_EVENT_API */
+
+#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret)                 \
+  do {                                                         \
+    if((lpcb)->accept != NULL)                                 \
+      (ret) = (lpcb)->accept((arg),(pcb),(err));               \
+    else (ret) = ERR_ARG;                                      \
+  } while (0)
+
+#define TCP_EVENT_SENT(pcb,space,ret)                          \
+  do {                                                         \
+    if((pcb)->sent != NULL)                                    \
+      (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space));  \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_RECV(pcb,p,err,ret)                          \
+  do {                                                         \
+    if((pcb)->recv != NULL) {                                  \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\
+    } else {                                                   \
+      (ret) = tcp_recv_null(NULL, (pcb), (p), (err));          \
+    }                                                          \
+  } while (0)
+
+#define TCP_EVENT_CLOSED(pcb,ret)                                \
+  do {                                                           \
+    if(((pcb)->recv != NULL)) {                                  \
+      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\
+    } else {                                                     \
+      (ret) = ERR_OK;                                            \
+    }                                                            \
+  } while (0)
+
+#define TCP_EVENT_CONNECTED(pcb,err,ret)                         \
+  do {                                                           \
+    if((pcb)->connected != NULL)                                 \
+      (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \
+    else (ret) = ERR_OK;                                         \
+  } while (0)
+
+#define TCP_EVENT_POLL(pcb,ret)                                \
+  do {                                                         \
+    if((pcb)->poll != NULL)                                    \
+      (ret) = (pcb)->poll((pcb)->callback_arg,(pcb));          \
+    else (ret) = ERR_OK;                                       \
+  } while (0)
+
+#define TCP_EVENT_ERR(last_state,errf,arg,err)                 \
+  do {                                                         \
+    LWIP_UNUSED_ARG(last_state);                               \
+    if((errf) != NULL)                                         \
+      (errf)((arg),(err));                                     \
+  } while (0)
+
+#endif /* LWIP_EVENT_API */
+
+/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */
+#if TCP_OVERSIZE && defined(LWIP_DEBUG)
+#define TCP_OVERSIZE_DBGCHECK 1
+#else
+#define TCP_OVERSIZE_DBGCHECK 0
+#endif
+
+/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */
+#define TCP_CHECKSUM_ON_COPY  (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP)
+
+/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segments on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  u16_t len;               /* the TCP length of this segment */
+#if TCP_OVERSIZE_DBGCHECK
+  u16_t oversize_left;     /* Extra bytes available at the end of the last
+                              pbuf in unsent (used for asserting vs.
+                              tcp_pcb.unsent_oversize only) */
+#endif /* TCP_OVERSIZE_DBGCHECK */
+#if TCP_CHECKSUM_ON_COPY
+  u16_t chksum;
+  u8_t  chksum_swapped;
+#endif /* TCP_CHECKSUM_ON_COPY */
+  u8_t  flags;
+#define TF_SEG_OPTS_MSS         (u8_t)0x01U /* Include MSS option (only used in SYN segments) */
+#define TF_SEG_OPTS_TS          (u8_t)0x02U /* Include timestamp option. */
+#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is
+                                               checksummed into 'chksum' */
+#define TF_SEG_OPTS_WND_SCALE   (u8_t)0x08U /* Include WND SCALE option (only used in SYN segments) */
+#define TF_SEG_OPTS_SACK_PERM   (u8_t)0x10U /* Include SACK Permitted option (only used in SYN segments) */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+#define LWIP_TCP_OPT_EOL        0
+#define LWIP_TCP_OPT_NOP        1
+#define LWIP_TCP_OPT_MSS        2
+#define LWIP_TCP_OPT_WS         3
+#define LWIP_TCP_OPT_SACK_PERM  4
+#define LWIP_TCP_OPT_TS         8
+
+#define LWIP_TCP_OPT_LEN_MSS    4
+#if LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_OPT_LEN_TS     10
+#define LWIP_TCP_OPT_LEN_TS_OUT 12 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_TS_OUT 0
+#endif
+#if LWIP_WND_SCALE
+#define LWIP_TCP_OPT_LEN_WS     3
+#define LWIP_TCP_OPT_LEN_WS_OUT 4 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_WS_OUT 0
+#endif
+
+#if LWIP_TCP_SACK_OUT
+#define LWIP_TCP_OPT_LEN_SACK_PERM     2
+#define LWIP_TCP_OPT_LEN_SACK_PERM_OUT 4 /* aligned for output (includes NOP padding) */
+#else
+#define LWIP_TCP_OPT_LEN_SACK_PERM_OUT 0
+#endif
+
+#define LWIP_TCP_OPT_LENGTH(flags) \
+  ((flags) & TF_SEG_OPTS_MSS       ? LWIP_TCP_OPT_LEN_MSS           : 0) + \
+  ((flags) & TF_SEG_OPTS_TS        ? LWIP_TCP_OPT_LEN_TS_OUT        : 0) + \
+  ((flags) & TF_SEG_OPTS_WND_SCALE ? LWIP_TCP_OPT_LEN_WS_OUT        : 0) + \
+  ((flags) & TF_SEG_OPTS_SACK_PERM ? LWIP_TCP_OPT_LEN_SACK_PERM_OUT : 0)
+
+/** This returns a TCP header option for MSS in an u32_t */
+#define TCP_BUILD_MSS_OPTION(mss) lwip_htonl(0x02040000 | ((mss) & 0xFFFF))
+
+#if LWIP_WND_SCALE
+#define TCPWNDSIZE_F       U32_F
+#define TCPWND_MAX         0xFFFFFFFFU
+#define TCPWND_CHECK16(x)  LWIP_ASSERT("window size > 0xFFFF", (x) <= 0xFFFF)
+#define TCPWND_MIN16(x)    ((u16_t)LWIP_MIN((x), 0xFFFF))
+#else /* LWIP_WND_SCALE */
+#define TCPWNDSIZE_F       U16_F
+#define TCPWND_MAX         0xFFFFU
+#define TCPWND_CHECK16(x)
+#define TCPWND_MIN16(x)    x
+#endif /* LWIP_WND_SCALE */
+
+/* Global variables: */
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+extern u8_t tcp_active_pcbs_changed;
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+  struct tcp_pcb_listen *listen_pcbs;
+  struct tcp_pcb *pcbs;
+};
+extern struct tcp_pcb *tcp_bound_pcbs;
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT  3
+#define NUM_TCP_PCB_LISTS               4
+extern struct tcp_pcb ** const tcp_pcb_lists[NUM_TCP_PCB_LISTS];
+
+/* Axioms about the above lists:
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#ifndef TCP_DEBUG_PCB_LISTS
+#define TCP_DEBUG_PCB_LISTS 0
+#endif
+#if TCP_DEBUG_PCB_LISTS
+#define TCP_REG(pcbs, npcb) do {\
+                            struct tcp_pcb *tcp_tmp_pcb; \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %"U16_F"\n", (void *)(npcb), (npcb)->local_port)); \
+                            for (tcp_tmp_pcb = *(pcbs); \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \
+                            (npcb)->next = *(pcbs); \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \
+                            *(pcbs) = (npcb); \
+                            LWIP_ASSERT("TCP_REG: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            struct tcp_pcb *tcp_tmp_pcb; \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (void *)(npcb), (void *)(*(pcbs)))); \
+                            if(*(pcbs) == (npcb)) { \
+                               *(pcbs) = (*pcbs)->next; \
+                            } else for (tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next == (npcb)) { \
+                                  tcp_tmp_pcb->next = (npcb)->next; \
+                                  break; \
+                               } \
+                            } \
+                            (npcb)->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (void *)(npcb), (void *)(*(pcbs)))); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+
+#define TCP_REG(pcbs, npcb)                        \
+  do {                                             \
+    (npcb)->next = *pcbs;                          \
+    *(pcbs) = (npcb);                              \
+    tcp_timer_needed();                            \
+  } while (0)
+
+#define TCP_RMV(pcbs, npcb)                        \
+  do {                                             \
+    if(*(pcbs) == (npcb)) {                        \
+      (*(pcbs)) = (*pcbs)->next;                   \
+    }                                              \
+    else {                                         \
+      struct tcp_pcb *tcp_tmp_pcb;                 \
+      for (tcp_tmp_pcb = *pcbs;                    \
+          tcp_tmp_pcb != NULL;                     \
+          tcp_tmp_pcb = tcp_tmp_pcb->next) {       \
+        if(tcp_tmp_pcb->next == (npcb)) {          \
+          tcp_tmp_pcb->next = (npcb)->next;        \
+          break;                                   \
+        }                                          \
+      }                                            \
+    }                                              \
+    (npcb)->next = NULL;                           \
+  } while(0)
+
+#endif /* LWIP_DEBUG */
+
+#define TCP_REG_ACTIVE(npcb)                       \
+  do {                                             \
+    TCP_REG(&tcp_active_pcbs, npcb);               \
+    tcp_active_pcbs_changed = 1;                   \
+  } while (0)
+
+#define TCP_RMV_ACTIVE(npcb)                       \
+  do {                                             \
+    TCP_RMV(&tcp_active_pcbs, npcb);               \
+    tcp_active_pcbs_changed = 1;                   \
+  } while (0)
+
+#define TCP_PCB_REMOVE_ACTIVE(pcb)                 \
+  do {                                             \
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);         \
+    tcp_active_pcbs_changed = 1;                   \
+  } while (0)
+
+
+/* Internal functions: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+void tcp_segs_free(struct tcp_seg *seg);
+void tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)                               \
+  do {                                             \
+    if((pcb)->flags & TF_ACK_DELAY) {              \
+      tcp_clear_flags(pcb, TF_ACK_DELAY);          \
+      tcp_ack_now(pcb);                            \
+    }                                              \
+    else {                                         \
+      tcp_set_flags(pcb, TF_ACK_DELAY);            \
+    }                                              \
+  } while (0)
+
+#define tcp_ack_now(pcb)                           \
+  tcp_set_flags(pcb, TF_ACK_NOW)
+
+err_t tcp_send_fin(struct tcp_pcb *pcb);
+err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(const struct tcp_pcb* pcb, u32_t seqno, u32_t ackno,
+       const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(struct tcp_pcb *pcb);
+
+err_t tcp_keepalive(struct tcp_pcb *pcb);
+err_t tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split);
+err_t tcp_zero_window_probe(struct tcp_pcb *pcb);
+void  tcp_trigger_input_pcb_close(void);
+
+#if TCP_CALCULATE_EFF_SEND_MSS
+u16_t tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif,
+                             const ip_addr_t *dest);
+#define tcp_eff_send_mss(sendmss, src, dest) \
+    tcp_eff_send_mss_netif(sendmss, ip_route(src, dest), dest)
+#endif /* TCP_CALCULATE_EFF_SEND_MSS */
+
+#if LWIP_CALLBACK_API
+err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+/** External function (implemented in timers.c), called when TCP detects
+ * that a timer is needed (i.e. active- or time-wait-pcb found). */
+void tcp_timer_needed(void);
+
+void tcp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
+
+#if TCP_QUEUE_OOSEQ
+void tcp_free_ooseq(struct tcp_pcb *pcb);
+#endif
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+err_t tcp_ext_arg_invoke_callbacks_passive_open(struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCP_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/tcpip_priv.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/tcpip_priv.h
new file mode 100644
index 000000000..74be634be
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/priv/tcpip_priv.h
@@ -0,0 +1,170 @@
+/**
+ * @file
+ * TCPIP API internal implementations (do not use in application code)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_TCPIP_PRIV_H
+#define LWIP_HDR_TCPIP_PRIV_H
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpip.h"
+#include "lwip/sys.h"
+#include "lwip/timeouts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pbuf;
+struct netif;
+
+#if LWIP_MPU_COMPATIBLE
+#define API_VAR_REF(name)               (*(name))
+#define API_VAR_DECLARE(type, name)     type * name
+#define API_VAR_ALLOC_EXT(type, pool, name, errorblock) do { \
+                                          name = (type *)memp_malloc(pool); \
+                                          if (name == NULL) { \
+                                            errorblock; \
+                                          } \
+                                        } while(0)
+#define API_VAR_ALLOC(type, pool, name, errorval) API_VAR_ALLOC_EXT(type, pool, name, return errorval)
+#define API_VAR_ALLOC_POOL(type, pool, name, errorval) do { \
+                                          name = (type *)LWIP_MEMPOOL_ALLOC(pool); \
+                                          if (name == NULL) { \
+                                            return errorval; \
+                                          } \
+                                        } while(0)
+#define API_VAR_FREE(pool, name)        memp_free(pool, name)
+#define API_VAR_FREE_POOL(pool, name)   LWIP_MEMPOOL_FREE(pool, name)
+#define API_EXPR_REF(expr)              (&(expr))
+#if LWIP_NETCONN_SEM_PER_THREAD
+#define API_EXPR_REF_SEM(expr)          (expr)
+#else
+#define API_EXPR_REF_SEM(expr)          API_EXPR_REF(expr)
+#endif
+#define API_EXPR_DEREF(expr)            expr
+#define API_MSG_M_DEF(m)                m
+#define API_MSG_M_DEF_C(t, m)           t m
+#else /* LWIP_MPU_COMPATIBLE */
+#define API_VAR_REF(name)               name
+#define API_VAR_DECLARE(type, name)     type name
+#define API_VAR_ALLOC_EXT(type, pool, name, errorblock)
+#define API_VAR_ALLOC(type, pool, name, errorval)
+#define API_VAR_ALLOC_POOL(type, pool, name, errorval)
+#define API_VAR_FREE(pool, name)
+#define API_VAR_FREE_POOL(pool, name)
+#define API_EXPR_REF(expr)              expr
+#define API_EXPR_REF_SEM(expr)          API_EXPR_REF(expr)
+#define API_EXPR_DEREF(expr)            (*(expr))
+#define API_MSG_M_DEF(m)                *m
+#define API_MSG_M_DEF_C(t, m)           const t * m
+#endif /* LWIP_MPU_COMPATIBLE */
+
+err_t tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem);
+
+struct tcpip_api_call_data
+{
+#if !LWIP_TCPIP_CORE_LOCKING
+  err_t err;
+#if !LWIP_NETCONN_SEM_PER_THREAD
+  sys_sem_t sem;
+#endif /* LWIP_NETCONN_SEM_PER_THREAD */
+#else /* !LWIP_TCPIP_CORE_LOCKING */
+  u8_t dummy; /* avoid empty struct :-( */
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+};
+typedef err_t (*tcpip_api_call_fn)(struct tcpip_api_call_data* call);
+err_t tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call);
+
+enum tcpip_msg_type {
+#if !LWIP_TCPIP_CORE_LOCKING
+  TCPIP_MSG_API,
+  TCPIP_MSG_API_CALL,
+#endif /* !LWIP_TCPIP_CORE_LOCKING */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+  TCPIP_MSG_INPKT,
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+  TCPIP_MSG_TIMEOUT,
+  TCPIP_MSG_UNTIMEOUT,
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+  TCPIP_MSG_CALLBACK,
+  TCPIP_MSG_CALLBACK_STATIC
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  union {
+#if !LWIP_TCPIP_CORE_LOCKING
+    struct {
+      tcpip_callback_fn function;
+      void* msg;
+    } api_msg;
+    struct {
+      tcpip_api_call_fn function;
+      struct tcpip_api_call_data *arg;
+      sys_sem_t *sem;
+    } api_call;
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+      netif_input_fn input_fn;
+    } inp;
+#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
+    struct {
+      tcpip_callback_fn function;
+      void *ctx;
+    } cb;
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+    struct {
+      u32_t msecs;
+      sys_timeout_handler h;
+      void *arg;
+    } tmo;
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+  } msg;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* LWIP_HDR_TCPIP_PRIV_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/autoip.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/autoip.h
new file mode 100644
index 000000000..fd3af8a9f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/autoip.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ * AutoIP protocol definitions
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies <kontakt@dspies.de>
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ */
+
+#ifndef LWIP_HDR_PROT_AUTOIP_H
+#define LWIP_HDR_PROT_AUTOIP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 169.254.0.0 */
+#define AUTOIP_NET              0xA9FE0000
+/* 169.254.1.0 */
+#define AUTOIP_RANGE_START      (AUTOIP_NET | 0x0100)
+/* 169.254.254.255 */
+#define AUTOIP_RANGE_END        (AUTOIP_NET | 0xFEFF)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT              1   /* second   (initial random delay)                 */
+#define PROBE_MIN               1   /* second   (minimum delay till repeated probe)    */
+#define PROBE_MAX               2   /* seconds  (maximum delay till repeated probe)    */
+#define PROBE_NUM               3   /*          (number of probe packets)              */
+#define ANNOUNCE_NUM            2   /*          (number of announcement packets)       */
+#define ANNOUNCE_INTERVAL       2   /* seconds  (time between announcement packets)    */
+#define ANNOUNCE_WAIT           2   /* seconds  (delay before announcing)              */
+#define MAX_CONFLICTS           10  /*          (max conflicts before rate limiting)   */
+#define RATE_LIMIT_INTERVAL     60  /* seconds  (delay between successive attempts)    */
+#define DEFEND_INTERVAL         10  /* seconds  (min. wait between defensive ARPs)     */
+
+/* AutoIP client states */
+typedef enum {
+  AUTOIP_STATE_OFF        = 0,
+  AUTOIP_STATE_PROBING    = 1,
+  AUTOIP_STATE_ANNOUNCING = 2,
+  AUTOIP_STATE_BOUND      = 3
+} autoip_state_enum_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_AUTOIP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dhcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dhcp.h
new file mode 100644
index 000000000..ab18dca31
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dhcp.h
@@ -0,0 +1,178 @@
+/**
+ * @file
+ * DHCP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Leon Woestenberg <leon.woestenberg@gmx.net>
+ *
+ */
+#ifndef LWIP_HDR_PROT_DHCP_H
+#define LWIP_HDR_PROT_DHCP_H
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/prot/ip4.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /* DHCP message item offsets and length */
+#define DHCP_CHADDR_LEN   16U
+#define DHCP_SNAME_OFS    44U
+#define DHCP_SNAME_LEN    64U
+#define DHCP_FILE_OFS     108U
+#define DHCP_FILE_LEN     128U
+#define DHCP_MSG_LEN      236U
+#define DHCP_OPTIONS_OFS  (DHCP_MSG_LEN + 4U) /* 4 byte: cookie */
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FLD_8(u8_t op);
+  PACK_STRUCT_FLD_8(u8_t htype);
+  PACK_STRUCT_FLD_8(u8_t hlen);
+  PACK_STRUCT_FLD_8(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t ciaddr);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t yiaddr);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t siaddr);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t giaddr);
+  PACK_STRUCT_FLD_8(u8_t chaddr[DHCP_CHADDR_LEN]);
+  PACK_STRUCT_FLD_8(u8_t sname[DHCP_SNAME_LEN]);
+  PACK_STRUCT_FLD_8(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FLD_8(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+/* DHCP client states */
+typedef enum {
+  DHCP_STATE_OFF             = 0,
+  DHCP_STATE_REQUESTING      = 1,
+  DHCP_STATE_INIT            = 2,
+  DHCP_STATE_REBOOTING       = 3,
+  DHCP_STATE_REBINDING       = 4,
+  DHCP_STATE_RENEWING        = 5,
+  DHCP_STATE_SELECTING       = 6,
+  DHCP_STATE_INFORMING       = 7,
+  DHCP_STATE_CHECKING        = 8,
+  DHCP_STATE_PERMANENT       = 9,  /* not yet implemented */
+  DHCP_STATE_BOUND           = 10,
+  DHCP_STATE_RELEASING       = 11, /* not yet implemented */
+  DHCP_STATE_BACKING_OFF     = 12
+} dhcp_state_enum_t;
+
+/* DHCP op codes */
+#define DHCP_BOOTREQUEST            1
+#define DHCP_BOOTREPLY              2
+
+/* DHCP message types */
+#define DHCP_DISCOVER               1
+#define DHCP_OFFER                  2
+#define DHCP_REQUEST                3
+#define DHCP_DECLINE                4
+#define DHCP_ACK                    5
+#define DHCP_NAK                    6
+#define DHCP_RELEASE                7
+#define DHCP_INFORM                 8
+
+#define DHCP_MAGIC_COOKIE           0x63825363UL
+
+/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */
+
+/* BootP options */
+#define DHCP_OPTION_PAD             0
+#define DHCP_OPTION_SUBNET_MASK     1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER          3
+#define DHCP_OPTION_DNS_SERVER      6
+#define DHCP_OPTION_HOSTNAME        12
+#define DHCP_OPTION_IP_TTL          23
+#define DHCP_OPTION_MTU             26
+#define DHCP_OPTION_BROADCAST       28
+#define DHCP_OPTION_TCP_TTL         37
+#define DHCP_OPTION_NTP             42
+#define DHCP_OPTION_END             255
+
+/* DHCP options */
+#define DHCP_OPTION_REQUESTED_IP    50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME      51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD        52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE    53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+#define DHCP_OPTION_SERVER_ID       54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST  55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE    57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1              58 /* T1 renewal time */
+#define DHCP_OPTION_T2              59 /* T2 rebinding time */
+#define DHCP_OPTION_US              60
+#define DHCP_OPTION_CLIENT_ID       61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE        67
+
+/* possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE          0
+#define DHCP_OVERLOAD_FILE          1
+#define DHCP_OVERLOAD_SNAME         2
+#define DHCP_OVERLOAD_SNAME_FILE    3
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_DHCP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dhcp6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dhcp6.h
new file mode 100644
index 000000000..0754c91b9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dhcp6.h
@@ -0,0 +1,138 @@
+/**
+ * @file
+ * DHCPv6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt <goldsimon@gmx.de>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_PROT_DHCP6_H
+#define LWIP_HDR_PROT_DHCP6_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DHCP6_CLIENT_PORT  546
+#define DHCP6_SERVER_PORT  547
+
+
+ /* DHCPv6 message item offsets and length */
+#define DHCP6_TRANSACTION_ID_LEN   3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCPv6 message */
+struct dhcp6_msg
+{
+  PACK_STRUCT_FLD_8(u8_t msgtype);
+  PACK_STRUCT_FLD_8(u8_t transaction_id[DHCP6_TRANSACTION_ID_LEN]);
+  /* options follow */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+/* DHCP6 client states */
+typedef enum {
+  DHCP6_STATE_OFF               = 0,
+  DHCP6_STATE_STATELESS_IDLE    = 1,
+  DHCP6_STATE_REQUESTING_CONFIG = 2
+} dhcp6_state_enum_t;
+
+/* DHCPv6 message types */
+#define DHCP6_SOLICIT               1
+#define DHCP6_ADVERTISE             2
+#define DHCP6_REQUEST               3
+#define DHCP6_CONFIRM               4
+#define DHCP6_RENEW                 5
+#define DHCP6_REBIND                6
+#define DHCP6_REPLY                 7
+#define DHCP6_RELEASE               8
+#define DHCP6_DECLINE               9
+#define DHCP6_RECONFIGURE           10
+#define DHCP6_INFOREQUEST           11
+#define DHCP6_RELAYFORW             12
+#define DHCP6_RELAYREPL             13
+/* More message types see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */
+
+/** DHCPv6 status codes */
+#define DHCP6_STATUS_SUCCESS        0 /* Success. */
+#define DHCP6_STATUS_UNSPECFAIL     1 /* Failure, reason unspecified; this status code is sent by either a client or a server to indicate a failure not explicitly specified in this document. */
+#define DHCP6_STATUS_NOADDRSAVAIL   2 /* Server has no addresses available to assign to the IA(s). */
+#define DHCP6_STATUS_NOBINDING      3 /* Client record (binding) unavailable. */
+#define DHCP6_STATUS_NOTONLINK      4 /* The prefix for the address is not appropriate for the link to which the client is attached. */
+#define DHCP6_STATUS_USEMULTICAST   5 /* Sent by a server to a client to force the client to send messages to the server using the All_DHCP_Relay_Agents_and_Servers address. */
+/* More status codes see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */
+
+/** DHCPv6 DUID types */
+#define DHCP6_DUID_LLT              1 /* LLT: Link-layer Address Plus Time */
+#define DHCP6_DUID_EN               2 /* EN: Enterprise number */
+#define DHCP6_DUID_LL               3 /* LL: Link-layer Address */
+#define DHCP6_DUID_UUID             4 /* UUID (RFC 6355) */
+
+/* DHCPv6 options */
+#define DHCP6_OPTION_CLIENTID       1
+#define DHCP6_OPTION_SERVERID       2
+#define DHCP6_OPTION_IA_NA          3
+#define DHCP6_OPTION_IA_TA          4
+#define DHCP6_OPTION_IAADDR         5
+#define DHCP6_OPTION_ORO            6
+#define DHCP6_OPTION_PREFERENCE     7
+#define DHCP6_OPTION_ELAPSED_TIME   8
+#define DHCP6_OPTION_RELAY_MSG      9
+#define DHCP6_OPTION_AUTH           11
+#define DHCP6_OPTION_UNICAST        12
+#define DHCP6_OPTION_STATUS_CODE    13
+#define DHCP6_OPTION_RAPID_COMMIT   14
+#define DHCP6_OPTION_USER_CLASS     15
+#define DHCP6_OPTION_VENDOR_CLASS   16
+#define DHCP6_OPTION_VENDOR_OPTS    17
+#define DHCP6_OPTION_INTERFACE_ID   18
+#define DHCP6_OPTION_RECONF_MSG     19
+#define DHCP6_OPTION_RECONF_ACCEPT  20
+/* More options see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */
+#define DHCP6_OPTION_DNS_SERVERS    23 /* RFC 3646 */
+#define DHCP6_OPTION_DOMAIN_LIST    24 /* RFC 3646 */
+#define DHCP6_OPTION_SNTP_SERVERS   31 /* RFC 4075 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_DHCP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dns.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dns.h
new file mode 100644
index 000000000..94782d6e9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/dns.h
@@ -0,0 +1,140 @@
+/**
+ * @file
+ * DNS - host name to IP address resolver.
+ */
+
+/*
+ * Port to lwIP from uIP
+ * by Jim Pettinato April 2007
+ *
+ * security fixes and more by Simon Goldschmidt
+ *
+ * uIP version Copyright (c) 2002-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LWIP_HDR_PROT_DNS_H
+#define LWIP_HDR_PROT_DNS_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DNS server port address */
+#ifndef DNS_SERVER_PORT
+#define DNS_SERVER_PORT           53
+#endif
+
+/* DNS field TYPE used for "Resource Records" */
+#define DNS_RRTYPE_A              1     /* a host address */
+#define DNS_RRTYPE_NS             2     /* an authoritative name server */
+#define DNS_RRTYPE_MD             3     /* a mail destination (Obsolete - use MX) */
+#define DNS_RRTYPE_MF             4     /* a mail forwarder (Obsolete - use MX) */
+#define DNS_RRTYPE_CNAME          5     /* the canonical name for an alias */
+#define DNS_RRTYPE_SOA            6     /* marks the start of a zone of authority */
+#define DNS_RRTYPE_MB             7     /* a mailbox domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_MG             8     /* a mail group member (EXPERIMENTAL) */
+#define DNS_RRTYPE_MR             9     /* a mail rename domain name (EXPERIMENTAL) */
+#define DNS_RRTYPE_NULL           10    /* a null RR (EXPERIMENTAL) */
+#define DNS_RRTYPE_WKS            11    /* a well known service description */
+#define DNS_RRTYPE_PTR            12    /* a domain name pointer */
+#define DNS_RRTYPE_HINFO          13    /* host information */
+#define DNS_RRTYPE_MINFO          14    /* mailbox or mail list information */
+#define DNS_RRTYPE_MX             15    /* mail exchange */
+#define DNS_RRTYPE_TXT            16    /* text strings */
+#define DNS_RRTYPE_AAAA           28    /* IPv6 address */
+#define DNS_RRTYPE_SRV            33    /* service location */
+#define DNS_RRTYPE_ANY            255   /* any type */
+
+/* DNS field CLASS used for "Resource Records" */
+#define DNS_RRCLASS_IN            1     /* the Internet */
+#define DNS_RRCLASS_CS            2     /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */
+#define DNS_RRCLASS_CH            3     /* the CHAOS class */
+#define DNS_RRCLASS_HS            4     /* Hesiod [Dyer 87] */
+#define DNS_RRCLASS_ANY           255   /* any class */
+#define DNS_RRCLASS_FLUSH         0x800 /* Flush bit */
+
+/* DNS protocol flags */
+#define DNS_FLAG1_RESPONSE        0x80
+#define DNS_FLAG1_OPCODE_STATUS   0x10
+#define DNS_FLAG1_OPCODE_INVERSE  0x08
+#define DNS_FLAG1_OPCODE_STANDARD 0x00
+#define DNS_FLAG1_AUTHORATIVE     0x04
+#define DNS_FLAG1_TRUNC           0x02
+#define DNS_FLAG1_RD              0x01
+#define DNS_FLAG2_RA              0x80
+#define DNS_FLAG2_ERR_MASK        0x0f
+#define DNS_FLAG2_ERR_NONE        0x00
+#define DNS_FLAG2_ERR_NAME        0x03
+
+#define DNS_HDR_GET_OPCODE(hdr) ((((hdr)->flags1) >> 3) & 0xF)
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** DNS message header */
+struct dns_hdr {
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FLD_8(u8_t flags1);
+  PACK_STRUCT_FLD_8(u8_t flags2);
+  PACK_STRUCT_FIELD(u16_t numquestions);
+  PACK_STRUCT_FIELD(u16_t numanswers);
+  PACK_STRUCT_FIELD(u16_t numauthrr);
+  PACK_STRUCT_FIELD(u16_t numextrarr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define SIZEOF_DNS_HDR 12
+
+
+/* Multicast DNS definitions */
+
+/** UDP port for multicast DNS queries */
+#ifndef DNS_MQUERY_PORT
+#define DNS_MQUERY_PORT             5353
+#endif
+
+/* IPv4 group for multicast DNS queries: 224.0.0.251 */
+#ifndef DNS_MQUERY_IPV4_GROUP_INIT
+#define DNS_MQUERY_IPV4_GROUP_INIT  IPADDR4_INIT_BYTES(224,0,0,251)
+#endif
+
+/* IPv6 group for multicast DNS queries: FF02::FB */
+#ifndef DNS_MQUERY_IPV6_GROUP_INIT
+#define DNS_MQUERY_IPV6_GROUP_INIT  IPADDR6_INIT_HOST(0xFF020000,0,0,0xFB)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_DNS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/etharp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/etharp.h
new file mode 100644
index 000000000..811c22841
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/etharp.h
@@ -0,0 +1,114 @@
+/**
+ * @file
+ * ARP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_ETHARP_H
+#define LWIP_HDR_PROT_ETHARP_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETHARP_HWADDR_LEN
+#define ETHARP_HWADDR_LEN     ETH_HWADDR_LEN
+#endif
+
+/**
+ * struct ip4_addr_wordaligned is used in the definition of the ARP packet format in
+ * order to support compilers that don't have structure packing.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip4_addr_wordaligned {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** MEMCPY-like copying of IP addresses where addresses are known to be
+ * 16-bit-aligned if the port is correctly configured (so a port could define
+ * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
+#ifndef IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T
+#define IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t))
+#endif
+
+ /** MEMCPY-like copying of IP addresses where addresses are known to be
+ * 16-bit-aligned if the port is correctly configured (so a port could define
+ * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
+#ifndef IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T
+#define IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t))
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message, see RFC 826 ("Packet format") */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FLD_8(u8_t  hwlen);
+  PACK_STRUCT_FLD_8(u8_t  protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FLD_S(struct eth_addr shwaddr);
+  PACK_STRUCT_FLD_S(struct ip4_addr_wordaligned sipaddr);
+  PACK_STRUCT_FLD_S(struct eth_addr dhwaddr);
+  PACK_STRUCT_FLD_S(struct ip4_addr_wordaligned dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETHARP_HDR 28
+
+/* ARP message types (opcodes) */
+enum etharp_opcode {
+  ARP_REQUEST = 1,
+  ARP_REPLY   = 2
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ETHARP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ethernet.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ethernet.h
new file mode 100644
index 000000000..309e57465
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ethernet.h
@@ -0,0 +1,125 @@
+/**
+ * @file
+ * Ethernet protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_ETHERNET_H
+#define LWIP_HDR_PROT_ETHERNET_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ieee.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ETH_HWADDR_LEN
+#ifdef ETHARP_HWADDR_LEN
+#define ETH_HWADDR_LEN    ETHARP_HWADDR_LEN /* compatibility mode */
+#else
+#define ETH_HWADDR_LEN    6
+#endif
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** An Ethernet MAC address */
+struct eth_addr {
+  PACK_STRUCT_FLD_8(u8_t addr[ETH_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Initialize a struct eth_addr with its 6 bytes (takes care of correct braces) */
+#define ETH_ADDR(b0, b1, b2, b3, b4, b5) {{b0, b1, b2, b3, b4, b5}}
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** Ethernet header */
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FLD_8(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FLD_S(struct eth_addr dest);
+  PACK_STRUCT_FLD_S(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE)
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** VLAN header inserted between ethernet header and payload
+ * if 'type' in ethernet header is ETHTYPE_VLAN.
+ * See IEEE802.Q */
+struct eth_vlan_hdr {
+  PACK_STRUCT_FIELD(u16_t prio_vid);
+  PACK_STRUCT_FIELD(u16_t tpid);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_VLAN_HDR 4
+#define VLAN_ID(vlan_hdr) (lwip_htons((vlan_hdr)->prio_vid) & 0xFFF)
+
+/** The 24-bit IANA IPv4-multicast OUI is 01-00-5e: */
+#define LL_IP4_MULTICAST_ADDR_0 0x01
+#define LL_IP4_MULTICAST_ADDR_1 0x00
+#define LL_IP4_MULTICAST_ADDR_2 0x5e
+
+/** IPv6 multicast uses this prefix */
+#define LL_IP6_MULTICAST_ADDR_0 0x33
+#define LL_IP6_MULTICAST_ADDR_1 0x33
+
+#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETH_HWADDR_LEN) == 0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ETHERNET_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/iana.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/iana.h
new file mode 100644
index 000000000..32890cccd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/iana.h
@@ -0,0 +1,97 @@
+/**
+ * @file
+ * IANA assigned numbers (RFC 1700 and successors)
+ *
+ * @defgroup iana IANA assigned numbers
+ * @ingroup infrastructure
+ */
+
+/*
+ * Copyright (c) 2017 Dirk Ziegelmeier.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier <dziegel@gmx.de>
+ *
+ */
+
+#ifndef LWIP_HDR_PROT_IANA_H
+#define LWIP_HDR_PROT_IANA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup iana
+ * Hardware types
+ */
+enum lwip_iana_hwtype {
+  /** Ethernet */
+  LWIP_IANA_HWTYPE_ETHERNET = 1
+};
+
+/**
+ * @ingroup iana
+ * Port numbers
+ * https://www.iana.org/assignments/service-names-port-numbers/service-names-port-numbers.txt
+ */
+enum lwip_iana_port_number {
+  /** SMTP */
+  LWIP_IANA_PORT_SMTP        = 25,
+  /** DHCP server */
+  LWIP_IANA_PORT_DHCP_SERVER = 67,
+  /** DHCP client */
+  LWIP_IANA_PORT_DHCP_CLIENT = 68,
+  /** TFTP */
+  LWIP_IANA_PORT_TFTP        = 69,
+  /** HTTP */
+  LWIP_IANA_PORT_HTTP        = 80,
+  /** SNTP */
+  LWIP_IANA_PORT_SNTP        = 123,
+  /** NETBIOS */
+  LWIP_IANA_PORT_NETBIOS     = 137,
+  /** SNMP */
+  LWIP_IANA_PORT_SNMP        = 161,
+  /** SNMP traps */
+  LWIP_IANA_PORT_SNMP_TRAP   = 162,
+  /** HTTPS */
+  LWIP_IANA_PORT_HTTPS       = 443,
+  /** SMTPS */
+  LWIP_IANA_PORT_SMTPS       = 465,
+  /** MQTT */
+  LWIP_IANA_PORT_MQTT        = 1883,
+  /** MDNS */
+  LWIP_IANA_PORT_MDNS        = 5353,
+  /** Secure MQTT */
+  LWIP_IANA_PORT_SECURE_MQTT = 8883
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IANA_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/icmp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/icmp.h
new file mode 100644
index 000000000..7d19385c7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/icmp.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ * ICMP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_ICMP_H
+#define LWIP_HDR_PROT_ICMP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER   0    /* echo reply */
+#define ICMP_DUR  3    /* destination unreachable */
+#define ICMP_SQ   4    /* source quench */
+#define ICMP_RD   5    /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE  11    /* time exceeded */
+#define ICMP_PP  12    /* parameter problem */
+#define ICMP_TS  13    /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR  16    /* information reply */
+#define ICMP_AM  17    /* address mask request */
+#define ICMP_AMR 18    /* address mask reply */
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+/** This is the standard ICMP header only that the u32_t data
+ *  is split to two u16_t like ICMP echo needs it.
+ *  This header is also used for other ICMP types that do not
+ *  use the data part.
+ */
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Compatibility defines, old versions used to combine type and code to an u16_t */
+#define ICMPH_TYPE(hdr) ((hdr)->type)
+#define ICMPH_CODE(hdr) ((hdr)->code)
+#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
+#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ICMP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/icmp6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/icmp6.h
new file mode 100644
index 000000000..346112042
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/icmp6.h
@@ -0,0 +1,170 @@
+/**
+ * @file
+ * ICMP6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_ICMP6_H
+#define LWIP_HDR_PROT_ICMP6_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICMP type */
+enum icmp6_type {
+  /** Destination unreachable */
+  ICMP6_TYPE_DUR = 1,
+  /** Packet too big */
+  ICMP6_TYPE_PTB = 2,
+  /** Time exceeded */
+  ICMP6_TYPE_TE = 3,
+  /** Parameter problem */
+  ICMP6_TYPE_PP = 4,
+  /** Private experimentation */
+  ICMP6_TYPE_PE1 = 100,
+  /** Private experimentation */
+  ICMP6_TYPE_PE2 = 101,
+  /** Reserved for expansion of error messages */
+  ICMP6_TYPE_RSV_ERR = 127,
+
+  /** Echo request */
+  ICMP6_TYPE_EREQ = 128,
+  /** Echo reply */
+  ICMP6_TYPE_EREP = 129,
+  /** Multicast listener query */
+  ICMP6_TYPE_MLQ = 130,
+  /** Multicast listener report */
+  ICMP6_TYPE_MLR = 131,
+  /** Multicast listener done */
+  ICMP6_TYPE_MLD = 132,
+  /** Router solicitation */
+  ICMP6_TYPE_RS = 133,
+  /** Router advertisement */
+  ICMP6_TYPE_RA = 134,
+  /** Neighbor solicitation */
+  ICMP6_TYPE_NS = 135,
+  /** Neighbor advertisement */
+  ICMP6_TYPE_NA = 136,
+  /** Redirect */
+  ICMP6_TYPE_RD = 137,
+  /** Multicast router advertisement */
+  ICMP6_TYPE_MRA = 151,
+  /** Multicast router solicitation */
+  ICMP6_TYPE_MRS = 152,
+  /** Multicast router termination */
+  ICMP6_TYPE_MRT = 153,
+  /** Private experimentation */
+  ICMP6_TYPE_PE3 = 200,
+  /** Private experimentation */
+  ICMP6_TYPE_PE4 = 201,
+  /** Reserved for expansion of informational messages */
+  ICMP6_TYPE_RSV_INF = 255
+};
+
+/** ICMP destination unreachable codes */
+enum icmp6_dur_code {
+  /** No route to destination */
+  ICMP6_DUR_NO_ROUTE = 0,
+  /** Communication with destination administratively prohibited */
+  ICMP6_DUR_PROHIBITED = 1,
+  /** Beyond scope of source address */
+  ICMP6_DUR_SCOPE = 2,
+  /** Address unreachable */
+  ICMP6_DUR_ADDRESS = 3,
+  /** Port unreachable */
+  ICMP6_DUR_PORT = 4,
+  /** Source address failed ingress/egress policy */
+  ICMP6_DUR_POLICY = 5,
+  /** Reject route to destination */
+  ICMP6_DUR_REJECT_ROUTE = 6
+};
+
+/** ICMP time exceeded codes */
+enum icmp6_te_code {
+  /** Hop limit exceeded in transit */
+  ICMP6_TE_HL = 0,
+  /** Fragment reassembly time exceeded */
+  ICMP6_TE_FRAG = 1
+};
+
+/** ICMP parameter code */
+enum icmp6_pp_code {
+  /** Erroneous header field encountered */
+  ICMP6_PP_FIELD = 0,
+  /** Unrecognized next header type encountered */
+  ICMP6_PP_HEADER = 1,
+  /** Unrecognized IPv6 option encountered */
+  ICMP6_PP_OPTION = 2
+};
+
+/** This is the standard ICMP6 header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp6_hdr {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t data);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** This is the ICMP6 header adapted for echo req/resp. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp6_echo_hdr {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ICMP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ieee.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ieee.h
new file mode 100644
index 000000000..abbb9e31d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ieee.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ * IEEE assigned numbers
+ *
+ * @defgroup ieee IEEE assigned numbers
+ * @ingroup infrastructure
+ */
+
+/*
+ * Copyright (c) 2017 Dirk Ziegelmeier.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier <dziegel@gmx.de>
+ *
+ */
+
+#ifndef LWIP_HDR_PROT_IEEE_H
+#define LWIP_HDR_PROT_IEEE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup ieee
+ * A list of often ethtypes (although lwIP does not use all of them).
+ */
+enum lwip_ieee_eth_type {
+  /** Internet protocol v4 */
+  ETHTYPE_IP        = 0x0800U,
+  /** Address resolution protocol */
+  ETHTYPE_ARP       = 0x0806U, 
+  /** Wake on lan */
+  ETHTYPE_WOL       = 0x0842U,
+  /** RARP */
+  ETHTYPE_RARP      = 0x8035U,
+  /** Virtual local area network */
+  ETHTYPE_VLAN      = 0x8100U,
+  /** Internet protocol v6 */
+  ETHTYPE_IPV6      = 0x86DDU,
+  /** PPP Over Ethernet Discovery Stage */
+  ETHTYPE_PPPOEDISC = 0x8863U,
+  /** PPP Over Ethernet Session Stage */
+  ETHTYPE_PPPOE     = 0x8864U,
+  /** Jumbo Frames */
+  ETHTYPE_JUMBO     = 0x8870U,
+  /** Process field network */
+  ETHTYPE_PROFINET  = 0x8892U,
+  /** Ethernet for control automation technology */
+  ETHTYPE_ETHERCAT  = 0x88A4U,
+  /** Link layer discovery protocol */
+  ETHTYPE_LLDP      = 0x88CCU,
+  /** Serial real-time communication system */
+  ETHTYPE_SERCOS    = 0x88CDU,
+  /** Media redundancy protocol */
+  ETHTYPE_MRP       = 0x88E3U,
+  /** Precision time protocol */
+  ETHTYPE_PTP       = 0x88F7U,
+  /** Q-in-Q, 802.1ad */
+  ETHTYPE_QINQ      = 0x9100U
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IEEE_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/igmp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/igmp.h
new file mode 100644
index 000000000..46b81a9dd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/igmp.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ * IGMP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_IGMP_H
+#define LWIP_HDR_PROT_IGMP_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ip4.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * IGMP constants
+ */
+#define IGMP_TTL                       1
+#define IGMP_MINLEN                    8
+#define ROUTER_ALERT                   0x9404U
+#define ROUTER_ALERTLEN                4
+
+/*
+ * IGMP message types, including version number.
+ */
+#define IGMP_MEMB_QUERY                0x11 /* Membership query         */
+#define IGMP_V1_MEMB_REPORT            0x12 /* Ver. 1 membership report */
+#define IGMP_V2_MEMB_REPORT            0x16 /* Ver. 2 membership report */
+#define IGMP_LEAVE_GROUP               0x17 /* Leave-group message      */
+
+/* Group  membership states */
+#define IGMP_GROUP_NON_MEMBER          0
+#define IGMP_GROUP_DELAYING_MEMBER     1
+#define IGMP_GROUP_IDLE_MEMBER         2
+
+/**
+ * IGMP packet format.
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct igmp_msg {
+  PACK_STRUCT_FLD_8(u8_t         igmp_msgtype);
+  PACK_STRUCT_FLD_8(u8_t         igmp_maxresp);
+  PACK_STRUCT_FIELD(u16_t        igmp_checksum);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t igmp_group_address);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IGMP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip.h
new file mode 100644
index 000000000..223158f5a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip.h
@@ -0,0 +1,59 @@
+/**
+ * @file
+ * IP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_IP_H
+#define LWIP_HDR_PROT_IP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IP_PROTO_ICMP    1
+#define IP_PROTO_IGMP    2
+#define IP_PROTO_UDP     17
+#define IP_PROTO_UDPLITE 136
+#define IP_PROTO_TCP     6
+
+/** This operates on a void* by loading the first byte */
+#define IP_HDR_GET_VERSION(ptr)   ((*(u8_t*)(ptr)) >> 4)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip4.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip4.h
new file mode 100644
index 000000000..934746115
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip4.h
@@ -0,0 +1,131 @@
+/**
+ * @file
+ * IPv4 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_IP4_H
+#define LWIP_HDR_PROT_IP4_H
+
+#include "lwip/arch.h"
+#include "lwip/ip4_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This is the packed version of ip4_addr_t,
+    used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip4_addr_packed {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+typedef struct ip4_addr_packed ip4_addr_p_t;
+
+/* Size of the IPv4 header. Same as 'sizeof(struct ip_hdr)'. */
+#define IP_HLEN 20
+/* Maximum size of the IPv4 header with options. */
+#define IP_HLEN_MAX 60
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/* The IPv4 header */
+struct ip_hdr {
+  /* version / header length */
+  PACK_STRUCT_FLD_8(u8_t _v_hl);
+  /* type of service */
+  PACK_STRUCT_FLD_8(u8_t _tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000U        /* reserved fragment flag */
+#define IP_DF 0x4000U        /* don't fragment flag */
+#define IP_MF 0x2000U        /* more fragments flag */
+#define IP_OFFMASK 0x1fffU   /* mask for fragmenting bits */
+  /* time to live */
+  PACK_STRUCT_FLD_8(u8_t _ttl);
+  /* protocol*/
+  PACK_STRUCT_FLD_8(u8_t _proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FLD_S(ip4_addr_p_t src);
+  PACK_STRUCT_FLD_S(ip4_addr_p_t dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Macros to get struct ip_hdr fields: */
+#define IPH_V(hdr)  ((hdr)->_v_hl >> 4)
+#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f)
+#define IPH_HL_BYTES(hdr) ((u8_t)(IPH_HL(hdr) * 4))
+#define IPH_TOS(hdr) ((hdr)->_tos)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_OFFSET_BYTES(hdr) ((u16_t)((lwip_ntohs(IPH_OFFSET(hdr)) & IP_OFFMASK) * 8U))
+#define IPH_TTL(hdr) ((hdr)->_ttl)
+#define IPH_PROTO(hdr) ((hdr)->_proto)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+/* Macros to set struct ip_hdr fields: */
+#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (u8_t)((((v) << 4) | (hl)))
+#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos)
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl)
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto)
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IP4_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip6.h
new file mode 100644
index 000000000..0f6de4559
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/ip6.h
@@ -0,0 +1,233 @@
+/**
+ * @file
+ * IPv6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_IP6_H
+#define LWIP_HDR_PROT_IP6_H
+
+#include "lwip/arch.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This is the packed version of ip6_addr_t,
+    used in network headers that are itself packed */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_addr_packed {
+  PACK_STRUCT_FIELD(u32_t addr[4]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+typedef struct ip6_addr_packed ip6_addr_p_t;
+
+#define IP6_HLEN 40
+
+#define IP6_NEXTH_HOPBYHOP  0
+#define IP6_NEXTH_TCP       6
+#define IP6_NEXTH_UDP       17
+#define IP6_NEXTH_ENCAPS    41
+#define IP6_NEXTH_ROUTING   43
+#define IP6_NEXTH_FRAGMENT  44
+#define IP6_NEXTH_ICMP6     58
+#define IP6_NEXTH_NONE      59
+#define IP6_NEXTH_DESTOPTS  60
+#define IP6_NEXTH_UDPLITE   136
+
+/** The IPv6 header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_hdr {
+  /** version / traffic class / flow label */
+  PACK_STRUCT_FIELD(u32_t _v_tc_fl);
+  /** payload length */
+  PACK_STRUCT_FIELD(u16_t _plen);
+  /** next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /** hop limit */
+  PACK_STRUCT_FLD_8(u8_t _hoplim);
+  /** source and destination IP addresses */
+  PACK_STRUCT_FLD_S(ip6_addr_p_t src);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t dest);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define IP6H_V(hdr)  ((lwip_ntohl((hdr)->_v_tc_fl) >> 28) & 0x0f)
+#define IP6H_TC(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 20) & 0xff)
+#define IP6H_FL(hdr) (lwip_ntohl((hdr)->_v_tc_fl) & 0x000fffff)
+#define IP6H_PLEN(hdr) (lwip_ntohs((hdr)->_plen))
+#define IP6H_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6H_NEXTH_P(hdr) ((u8_t *)(hdr) + 6)
+#define IP6H_HOPLIM(hdr) ((hdr)->_hoplim)
+#define IP6H_VTCFL_SET(hdr, v, tc, fl) (hdr)->_v_tc_fl = (lwip_htonl((((u32_t)(v)) << 28) | (((u32_t)(tc)) << 20) | (fl)))
+#define IP6H_PLEN_SET(hdr, plen) (hdr)->_plen = lwip_htons(plen)
+#define IP6H_NEXTH_SET(hdr, nexth) (hdr)->_nexth = (nexth)
+#define IP6H_HOPLIM_SET(hdr, hl) (hdr)->_hoplim = (u8_t)(hl)
+
+/* ipv6 extended options header */
+#define IP6_PAD1_OPTION             0
+#define IP6_PADN_OPTION             1
+#define IP6_ROUTER_ALERT_OPTION     5
+#define IP6_JUMBO_OPTION            194
+#define IP6_HOME_ADDRESS_OPTION     201
+#define IP6_ROUTER_ALERT_DLEN       2
+#define IP6_ROUTER_ALERT_VALUE_MLD  0
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_opt_hdr {
+  /* router alert option type */
+  PACK_STRUCT_FLD_8(u8_t _opt_type);
+  /* router alert option data len */
+  PACK_STRUCT_FLD_8(u8_t _opt_dlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define IP6_OPT_HLEN 2
+#define IP6_OPT_TYPE_ACTION(hdr) ((((hdr)->_opt_type) >> 6) & 0x3)
+#define IP6_OPT_TYPE_CHANGE(hdr) ((((hdr)->_opt_type) >> 5) & 0x1)
+#define IP6_OPT_TYPE(hdr) ((hdr)->_opt_type)
+#define IP6_OPT_DLEN(hdr) ((hdr)->_opt_dlen)
+
+/* Hop-by-Hop header. */
+#define IP6_HBH_HLEN    2
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_hbh_hdr {
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* header length in 8-octet units */
+  PACK_STRUCT_FLD_8(u8_t _hlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define IP6_HBH_NEXTH(hdr) ((hdr)->_nexth)
+
+/* Destination header. */
+#define IP6_DEST_HLEN   2
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_dest_hdr {
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* header length in 8-octet units */
+  PACK_STRUCT_FLD_8(u8_t _hlen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define IP6_DEST_NEXTH(hdr) ((hdr)->_nexth)
+
+/* Routing header */
+#define IP6_ROUT_TYPE2  2
+#define IP6_ROUT_RPL    3
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_rout_hdr {
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* reserved */
+  PACK_STRUCT_FLD_8(u8_t _hlen);
+  /* fragment offset */
+  PACK_STRUCT_FIELD(u8_t _routing_type);
+  /* fragmented packet identification */
+  PACK_STRUCT_FIELD(u8_t _segments_left);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define IP6_ROUT_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6_ROUT_TYPE(hdr) ((hdr)->_routing_type)
+#define IP6_ROUT_SEG_LEFT(hdr) ((hdr)->_segments_left)
+
+/* Fragment header. */
+#define IP6_FRAG_HLEN    8
+#define IP6_FRAG_OFFSET_MASK    0xfff8
+#define IP6_FRAG_MORE_FLAG      0x0001
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip6_frag_hdr {
+  /* next header */
+  PACK_STRUCT_FLD_8(u8_t _nexth);
+  /* reserved */
+  PACK_STRUCT_FLD_8(u8_t reserved);
+  /* fragment offset */
+  PACK_STRUCT_FIELD(u16_t _fragment_offset);
+  /* fragmented packet identification */
+  PACK_STRUCT_FIELD(u32_t _identification);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define IP6_FRAG_NEXTH(hdr) ((hdr)->_nexth)
+#define IP6_FRAG_MBIT(hdr) (lwip_ntohs((hdr)->_fragment_offset) & 0x1)
+#define IP6_FRAG_ID(hdr) (lwip_ntohl((hdr)->_identification))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_IP6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/mld6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/mld6.h
new file mode 100644
index 000000000..71f1dcbdc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/mld6.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ * MLD6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_MLD6_H
+#define LWIP_HDR_PROT_MLD6_H
+
+#include "lwip/arch.h"
+#include "lwip/prot/ip6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MLD6_HBH_HLEN 8
+/** Multicast listener report/query/done message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct mld_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t max_resp_delay);
+  PACK_STRUCT_FIELD(u16_t reserved);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t multicast_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_MLD6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/nd6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/nd6.h
new file mode 100644
index 000000000..c270d07c1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/nd6.h
@@ -0,0 +1,274 @@
+/**
+ * @file
+ * ND6 protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_ND6_H
+#define LWIP_HDR_PROT_ND6_H
+
+#include "lwip/arch.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/ip6.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Neighbor solicitation message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ns_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t reserved);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Neighbor advertisement message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct na_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FLD_8(u8_t flags);
+  PACK_STRUCT_FLD_8(u8_t reserved[3]);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#define ND6_FLAG_ROUTER      (0x80)
+#define ND6_FLAG_SOLICITED   (0x40)
+#define ND6_FLAG_OVERRIDE    (0x20)
+
+/** Router solicitation message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct rs_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t reserved);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Router advertisement message header. */
+#define ND6_RA_FLAG_MANAGED_ADDR_CONFIG (0x80)
+#define ND6_RA_FLAG_OTHER_CONFIG (0x40)
+#define ND6_RA_FLAG_HOME_AGENT (0x20)
+#define ND6_RA_PREFERENCE_MASK (0x18)
+#define ND6_RA_PREFERENCE_HIGH (0x08)
+#define ND6_RA_PREFERENCE_MEDIUM (0x00)
+#define ND6_RA_PREFERENCE_LOW (0x18)
+#define ND6_RA_PREFERENCE_DISABLED (0x10)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ra_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FLD_8(u8_t current_hop_limit);
+  PACK_STRUCT_FLD_8(u8_t flags);
+  PACK_STRUCT_FIELD(u16_t router_lifetime);
+  PACK_STRUCT_FIELD(u32_t reachable_time);
+  PACK_STRUCT_FIELD(u32_t retrans_timer);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Redirect message header. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct redirect_header {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t reserved);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t destination_address);
+  /* Options follow. */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Link-layer address option. */
+#define ND6_OPTION_TYPE_SOURCE_LLADDR (0x01)
+#define ND6_OPTION_TYPE_TARGET_LLADDR (0x02)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct lladdr_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t addr[NETIF_MAX_HWADDR_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Prefix information option. */
+#define ND6_OPTION_TYPE_PREFIX_INFO (0x03)
+#define ND6_PREFIX_FLAG_ON_LINK (0x80)
+#define ND6_PREFIX_FLAG_AUTONOMOUS (0x40)
+#define ND6_PREFIX_FLAG_ROUTER_ADDRESS (0x20)
+#define ND6_PREFIX_FLAG_SITE_PREFIX (0x10)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct prefix_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t prefix_length);
+  PACK_STRUCT_FLD_8(u8_t flags);
+  PACK_STRUCT_FIELD(u32_t valid_lifetime);
+  PACK_STRUCT_FIELD(u32_t preferred_lifetime);
+  PACK_STRUCT_FLD_8(u8_t reserved2[3]);
+  PACK_STRUCT_FLD_8(u8_t site_prefix_length);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Redirected header option. */
+#define ND6_OPTION_TYPE_REDIR_HDR (0x04)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct redirected_header_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t reserved[6]);
+  /* Portion of redirected packet follows. */
+  /* PACK_STRUCT_FLD_8(u8_t redirected[8]); */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** MTU option. */
+#define ND6_OPTION_TYPE_MTU (0x05)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct mtu_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FIELD(u16_t reserved);
+  PACK_STRUCT_FIELD(u32_t mtu);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Route information option. */
+#define ND6_OPTION_TYPE_ROUTE_INFO (24)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct route_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FLD_8(u8_t prefix_length);
+  PACK_STRUCT_FLD_8(u8_t preference);
+  PACK_STRUCT_FIELD(u32_t route_lifetime);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** Recursive DNS Server Option. */
+#define ND6_OPTION_TYPE_RDNSS (25)
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct rdnss_option {
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t length);
+  PACK_STRUCT_FIELD(u16_t reserved);
+  PACK_STRUCT_FIELD(u32_t lifetime);
+  PACK_STRUCT_FLD_S(ip6_addr_p_t rdnss_address[1]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define SIZEOF_RDNSS_OPTION_BASE 8 /* size without addresses */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_ND6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/tcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/tcp.h
new file mode 100644
index 000000000..c1d7de1fa
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/tcp.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ * TCP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_TCP_H
+#define LWIP_HDR_PROT_TCP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+/* Fields are (of course) in network byte order.
+ * Some fields are converted to host byte order in tcp_input().
+ */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* TCP header flags bits */
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+/* Valid TCP header flags */
+#define TCP_FLAGS 0x3fU
+
+#define TCP_MAX_OPTION_BYTES 40
+
+#define TCPH_HDRLEN(phdr) ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) >> 12))
+#define TCPH_HDRLEN_BYTES(phdr) ((u8_t)(TCPH_HDRLEN(phdr) << 2))
+#define TCPH_FLAGS(phdr)  ((u8_t)((lwip_ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)))
+
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = lwip_htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS(~TCP_FLAGS)) | lwip_htons(flags))
+#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = (u16_t)(lwip_htons((u16_t)((len) << 12) | (flags)))
+
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | lwip_htons(flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags & ~lwip_htons(flags))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_TCP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/udp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/udp.h
new file mode 100644
index 000000000..664f19a3e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/prot/udp.h
@@ -0,0 +1,68 @@
+/**
+ * @file
+ * UDP protocol definitions
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_PROT_UDP_H
+#define LWIP_HDR_PROT_UDP_H
+
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_HLEN 8
+
+/* Fields are (of course) in network byte order. */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_PROT_UDP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/raw.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/raw.h
new file mode 100644
index 000000000..b129bd3b9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/raw.h
@@ -0,0 +1,143 @@
+/**
+ * @file
+ * raw API (to be used from TCPIP thread)\n
+ * See also @ref raw_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_RAW_H
+#define LWIP_HDR_RAW_H
+
+#include "lwip/opt.h"
+
+#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/def.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RAW_FLAGS_CONNECTED      0x01U
+#define RAW_FLAGS_HDRINCL        0x02U
+#define RAW_FLAGS_MULTICAST_LOOP 0x04U
+
+struct raw_pcb;
+
+/** Function prototype for raw pcb receive callback functions.
+ * @param arg user supplied argument (raw_pcb.recv_arg)
+ * @param pcb the raw_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @return 1 if the packet was 'eaten' (aka. deleted),
+ *         0 if the packet lives on
+ * If returning 1, the callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ */
+typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    const ip_addr_t *addr);
+
+/** the RAW protocol control block */
+struct raw_pcb {
+  /* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u8_t protocol;
+  u8_t flags;
+
+#if LWIP_MULTICAST_TX_OPTIONS
+  /** outgoing network interface for multicast packets, by interface index (if nonzero) */
+  u8_t mcast_ifindex;
+  /** TTL for outgoing multicast packets */
+  u8_t mcast_ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+  /** receive callback function */
+  raw_recv_fn recv;
+  /* user-supplied argument for the recv callback */
+  void *recv_arg;
+#if LWIP_IPV6
+  /* fields for handling checksum computations as per RFC3542. */
+  u16_t chksum_offset;
+  u8_t  chksum_reqd;
+#endif
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u8_t proto);
+struct raw_pcb * raw_new_ip_type(u8_t type, u8_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
+void             raw_bind_netif (struct raw_pcb *pcb, const struct netif *netif);
+err_t            raw_connect    (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
+void             raw_disconnect (struct raw_pcb *pcb);
+
+err_t            raw_sendto     (struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr);
+err_t            raw_sendto_if_src(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, struct netif *netif, const ip_addr_t *src_ip);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+void             raw_recv       (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg);
+
+#define          raw_flags(pcb) ((pcb)->flags)
+#define          raw_setflags(pcb,f)  ((pcb)->flags = (f))
+
+#define          raw_set_flags(pcb, set_flags)     do { (pcb)->flags = (u8_t)((pcb)->flags |  (set_flags)); } while(0)
+#define          raw_clear_flags(pcb, clr_flags)   do { (pcb)->flags = (u8_t)((pcb)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define          raw_is_flag_set(pcb, flag)        (((pcb)->flags & (flag)) != 0)
+
+#define raw_init() /* Compatibility define, no init needed. */
+
+/* for compatibility with older implementation */
+#define raw_new_ip6(proto) raw_new_ip_type(IPADDR_TYPE_V6, proto)
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#define raw_set_multicast_netif_index(pcb, idx) ((pcb)->mcast_ifindex = (idx))
+#define raw_get_multicast_netif_index(pcb)      ((pcb)->mcast_ifindex)
+#define raw_set_multicast_ttl(pcb, value)       ((pcb)->mcast_ttl = (value))
+#define raw_get_multicast_ttl(pcb)              ((pcb)->mcast_ttl)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_RAW */
+
+#endif /* LWIP_HDR_RAW_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sio.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sio.h
new file mode 100644
index 000000000..7643e1956
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sio.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#ifndef SIO_H
+#define SIO_H
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If you want to define sio_fd_t elsewhere or differently,
+   define this in your cc.h file. */
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+/* The following functions can be defined to something else in your cc.h file
+   or be implemented in your custom sio.c file. */
+
+#ifndef sio_open
+/**
+ * Opens a serial device for communication.
+ *
+ * @param devnum device number
+ * @return handle to serial device if successful, NULL otherwise
+ */
+sio_fd_t sio_open(u8_t devnum);
+#endif
+
+#ifndef sio_send
+/**
+ * Sends a single character to the serial device.
+ *
+ * @param c character to send
+ * @param fd serial device handle
+ *
+ * @note This function will block until the character can be sent.
+ */
+void sio_send(u8_t c, sio_fd_t fd);
+#endif
+
+#ifndef sio_recv
+/**
+ * Receives a single character from the serial device.
+ *
+ * @param fd serial device handle
+ *
+ * @note This function will block until a character is received.
+ */
+u8_t sio_recv(sio_fd_t fd);
+#endif
+
+#ifndef sio_read
+/**
+ * Reads from the serial device.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received - may be 0 if aborted by sio_read_abort
+ *
+ * @note This function will block until data can be received. The blocking
+ * can be cancelled by calling sio_read_abort().
+ */
+u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_tryread
+/**
+ * Tries to read from the serial device. Same as sio_read but returns
+ * immediately if no data is available and never blocks.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data buffer for receiving
+ * @param len maximum length (in bytes) of data to receive
+ * @return number of bytes actually received
+ */
+u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_write
+/**
+ * Writes to the serial device.
+ *
+ * @param fd serial device handle
+ * @param data pointer to data to send
+ * @param len length (in bytes) of data to send
+ * @return number of bytes actually sent
+ *
+ * @note This function will block until all data can be sent.
+ */
+u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len);
+#endif
+
+#ifndef sio_read_abort
+/**
+ * Aborts a blocking sio_read() call.
+ *
+ * @param fd serial device handle
+ */
+void sio_read_abort(sio_fd_t fd);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SIO_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/snmp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/snmp.h
new file mode 100644
index 000000000..cdceb7c38
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/snmp.h
@@ -0,0 +1,213 @@
+/**
+ * @file
+ * SNMP support API for implementing netifs and statitics for MIB2
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Dirk Ziegelmeier <dziegel@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_SNMP_H
+#define LWIP_HDR_SNMP_H
+
+#include "lwip/opt.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct udp_pcb;
+struct netif;
+
+/**
+ * @defgroup netif_mib2 MIB2 statistics
+ * @ingroup netif
+ */
+
+/* MIB2 statistics functions */
+#if MIB2_STATS  /* don't build if not configured for use in lwipopts.h */
+/**
+ * @ingroup netif_mib2
+ * @see RFC1213, "MIB-II, 6. Definitions"
+ */
+enum snmp_ifType {
+  snmp_ifType_other=1,                /* none of the following */
+  snmp_ifType_regular1822,
+  snmp_ifType_hdh1822,
+  snmp_ifType_ddn_x25,
+  snmp_ifType_rfc877_x25,
+  snmp_ifType_ethernet_csmacd,
+  snmp_ifType_iso88023_csmacd,
+  snmp_ifType_iso88024_tokenBus,
+  snmp_ifType_iso88025_tokenRing,
+  snmp_ifType_iso88026_man,
+  snmp_ifType_starLan,
+  snmp_ifType_proteon_10Mbit,
+  snmp_ifType_proteon_80Mbit,
+  snmp_ifType_hyperchannel,
+  snmp_ifType_fddi,
+  snmp_ifType_lapb,
+  snmp_ifType_sdlc,
+  snmp_ifType_ds1,                    /* T-1 */
+  snmp_ifType_e1,                     /* european equiv. of T-1 */
+  snmp_ifType_basicISDN,
+  snmp_ifType_primaryISDN,            /* proprietary serial */
+  snmp_ifType_propPointToPointSerial,
+  snmp_ifType_ppp,
+  snmp_ifType_softwareLoopback,
+  snmp_ifType_eon,                    /* CLNP over IP [11] */
+  snmp_ifType_ethernet_3Mbit,
+  snmp_ifType_nsip,                   /* XNS over IP */
+  snmp_ifType_slip,                   /* generic SLIP */
+  snmp_ifType_ultra,                  /* ULTRA technologies */
+  snmp_ifType_ds3,                    /* T-3 */
+  snmp_ifType_sip,                    /* SMDS */
+  snmp_ifType_frame_relay
+};
+
+/** This macro has a precision of ~49 days because Milliseconds returns u32_t. \#define your own if you want ~490 days. */
+#ifndef MIB2_COPY_SYSUPTIME_TO
+#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) (*(ptrToVal) = (Milliseconds() / 10))
+#endif
+
+/**
+ * @ingroup netif_mib2
+ * Increment stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs)
+ */
+#define MIB2_STATS_NETIF_INC(n, x)      do { ++(n)->mib2_counters.x; } while(0)
+/**
+ * @ingroup netif_mib2
+ * Add value to stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs)
+ */
+#define MIB2_STATS_NETIF_ADD(n, x, val) do { (n)->mib2_counters.x += (val); } while(0)
+
+/**
+ * @ingroup netif_mib2
+ * Init MIB2 statistic counters in netif
+ * @param netif Netif to init
+ * @param type one of enum @ref snmp_ifType
+ * @param speed your link speed here (units: bits per second)
+ */
+#define MIB2_INIT_NETIF(netif, type, speed) do { \
+  (netif)->link_type = (type);  \
+  (netif)->link_speed = (speed);\
+  (netif)->ts = 0;              \
+  (netif)->mib2_counters.ifinoctets = 0;      \
+  (netif)->mib2_counters.ifinucastpkts = 0;   \
+  (netif)->mib2_counters.ifinnucastpkts = 0;  \
+  (netif)->mib2_counters.ifindiscards = 0;    \
+  (netif)->mib2_counters.ifinerrors = 0;    \
+  (netif)->mib2_counters.ifinunknownprotos = 0;    \
+  (netif)->mib2_counters.ifoutoctets = 0;     \
+  (netif)->mib2_counters.ifoutucastpkts = 0;  \
+  (netif)->mib2_counters.ifoutnucastpkts = 0; \
+  (netif)->mib2_counters.ifoutdiscards = 0; \
+  (netif)->mib2_counters.ifouterrors = 0; } while(0)
+#else /* MIB2_STATS */
+#ifndef MIB2_COPY_SYSUPTIME_TO
+#define MIB2_COPY_SYSUPTIME_TO(ptrToVal)
+#endif
+#define MIB2_INIT_NETIF(netif, type, speed)
+#define MIB2_STATS_NETIF_INC(n, x)
+#define MIB2_STATS_NETIF_ADD(n, x, val)
+#endif /* MIB2_STATS */
+
+/* LWIP MIB2 callbacks */
+#if LWIP_MIB2_CALLBACKS /* don't build if not configured for use in lwipopts.h */
+/* network interface */
+void mib2_netif_added(struct netif *ni);
+void mib2_netif_removed(struct netif *ni);
+
+#if LWIP_IPV4 && LWIP_ARP
+/* ARP (for atTable and ipNetToMediaTable) */
+void mib2_add_arp_entry(struct netif *ni, ip4_addr_t *ip);
+void mib2_remove_arp_entry(struct netif *ni, ip4_addr_t *ip);
+#else /* LWIP_IPV4 && LWIP_ARP */
+#define mib2_add_arp_entry(ni,ip)
+#define mib2_remove_arp_entry(ni,ip)
+#endif /* LWIP_IPV4 && LWIP_ARP */
+
+/* IP */
+#if LWIP_IPV4
+void mib2_add_ip4(struct netif *ni);
+void mib2_remove_ip4(struct netif *ni);
+void mib2_add_route_ip4(u8_t dflt, struct netif *ni);
+void mib2_remove_route_ip4(u8_t dflt, struct netif *ni);
+#endif /* LWIP_IPV4 */
+
+/* UDP */
+#if LWIP_UDP
+void mib2_udp_bind(struct udp_pcb *pcb);
+void mib2_udp_unbind(struct udp_pcb *pcb);
+#endif /* LWIP_UDP */
+
+#else /* LWIP_MIB2_CALLBACKS */
+/* LWIP_MIB2_CALLBACKS support not available */
+/* define everything to be empty */
+
+/* network interface */
+#define mib2_netif_added(ni)
+#define mib2_netif_removed(ni)
+
+/* ARP */
+#define mib2_add_arp_entry(ni,ip)
+#define mib2_remove_arp_entry(ni,ip)
+
+/* IP */
+#define mib2_add_ip4(ni)
+#define mib2_remove_ip4(ni)
+#define mib2_add_route_ip4(dflt, ni)
+#define mib2_remove_route_ip4(dflt, ni)
+
+/* UDP */
+#define mib2_udp_bind(pcb)
+#define mib2_udp_unbind(pcb)
+#endif /* LWIP_MIB2_CALLBACKS */
+
+/* for source-code compatibility reasons only, can be removed (not used internally) */
+#define NETIF_INIT_SNMP                MIB2_INIT_NETIF
+#define snmp_add_ifinoctets(ni,value)  MIB2_STATS_NETIF_ADD(ni, ifinoctets, value)
+#define snmp_inc_ifinucastpkts(ni)     MIB2_STATS_NETIF_INC(ni, ifinucastpkts)
+#define snmp_inc_ifinnucastpkts(ni)    MIB2_STATS_NETIF_INC(ni, ifinnucastpkts)
+#define snmp_inc_ifindiscards(ni)      MIB2_STATS_NETIF_INC(ni, ifindiscards)
+#define snmp_inc_ifinerrors(ni)        MIB2_STATS_NETIF_INC(ni, ifinerrors)
+#define snmp_inc_ifinunknownprotos(ni) MIB2_STATS_NETIF_INC(ni, ifinunknownprotos)
+#define snmp_add_ifoutoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifoutoctets, value)
+#define snmp_inc_ifoutucastpkts(ni)    MIB2_STATS_NETIF_INC(ni, ifoutucastpkts)
+#define snmp_inc_ifoutnucastpkts(ni)   MIB2_STATS_NETIF_INC(ni, ifoutnucastpkts)
+#define snmp_inc_ifoutdiscards(ni)     MIB2_STATS_NETIF_INC(ni, ifoutdiscards)
+#define snmp_inc_ifouterrors(ni)       MIB2_STATS_NETIF_INC(ni, ifouterrors)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_SNMP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sockets.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sockets.h
new file mode 100644
index 000000000..d70d36c4d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sockets.h
@@ -0,0 +1,688 @@
+/**
+ * @file
+ * Socket API (to be used from non-TCPIP threads)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+
+#ifndef LWIP_HDR_SOCKETS_H
+#define LWIP_HDR_SOCKETS_H
+
+#include "lwip/opt.h"
+
+#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/err.h"
+#include "lwip/inet.h"
+#include "lwip/errno.h"
+
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* If your port already typedef's sa_family_t, define SA_FAMILY_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(sa_family_t) && !defined(SA_FAMILY_T_DEFINED)
+typedef u8_t sa_family_t;
+#endif
+/* If your port already typedef's in_port_t, define IN_PORT_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(in_port_t) && !defined(IN_PORT_T_DEFINED)
+typedef u16_t in_port_t;
+#endif
+
+#if LWIP_IPV4
+/* members are in network byte order */
+struct sockaddr_in {
+  u8_t            sin_len;
+  sa_family_t     sin_family;
+  in_port_t       sin_port;
+  struct in_addr  sin_addr;
+#define SIN_ZERO_LEN 8
+  char            sin_zero[SIN_ZERO_LEN];
+};
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+struct sockaddr_in6 {
+  u8_t            sin6_len;      /* length of this structure    */
+  sa_family_t     sin6_family;   /* AF_INET6                    */
+  in_port_t       sin6_port;     /* Transport layer port #      */
+  u32_t           sin6_flowinfo; /* IPv6 flow information       */
+  struct in6_addr sin6_addr;     /* IPv6 address                */
+  u32_t           sin6_scope_id; /* Set of interfaces for scope */
+};
+#endif /* LWIP_IPV6 */
+
+struct sockaddr {
+  u8_t        sa_len;
+  sa_family_t sa_family;
+  char        sa_data[14];
+};
+
+struct sockaddr_storage {
+  u8_t        s2_len;
+  sa_family_t ss_family;
+  char        s2_data1[2];
+  u32_t       s2_data2[3];
+#if LWIP_IPV6
+  u32_t       s2_data3[3];
+#endif /* LWIP_IPV6 */
+};
+
+/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED
+   to prevent this code from redefining it. */
+#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED)
+typedef u32_t socklen_t;
+#endif
+
+#if !defined IOV_MAX
+#define IOV_MAX 0xFFFF
+#elif IOV_MAX > 0xFFFF
+#error "IOV_MAX larger than supported by LwIP"
+#endif /* IOV_MAX */
+
+#if !defined(iovec)
+struct iovec {
+  void  *iov_base;
+  size_t iov_len;
+};
+#endif
+
+struct msghdr {
+  void         *msg_name;
+  socklen_t     msg_namelen;
+  struct iovec *msg_iov;
+  int           msg_iovlen;
+  void         *msg_control;
+  socklen_t     msg_controllen;
+  int           msg_flags;
+};
+
+/* struct msghdr->msg_flags bit field values */
+#define MSG_TRUNC   0x04
+#define MSG_CTRUNC  0x08
+
+/* RFC 3542, Section 20: Ancillary Data */
+struct cmsghdr {
+  socklen_t  cmsg_len;   /* number of bytes, including header */
+  int        cmsg_level; /* originating protocol */
+  int        cmsg_type;  /* protocol-specific type */
+};
+/* Data section follows header and possible padding, typically referred to as
+      unsigned char cmsg_data[]; */
+
+/* cmsg header/data alignment. NOTE: we align to native word size (double word
+size on 16-bit arch) so structures are not placed at an unaligned address.
+16-bit arch needs double word to ensure 32-bit alignment because socklen_t
+could be 32 bits. If we ever have cmsg data with a 64-bit variable, alignment
+will need to increase long long */
+#define ALIGN_H(size) (((size) + sizeof(long) - 1U) & ~(sizeof(long)-1U))
+#define ALIGN_D(size) ALIGN_H(size)
+
+#define CMSG_FIRSTHDR(mhdr) \
+          ((mhdr)->msg_controllen >= sizeof(struct cmsghdr) ? \
+           (struct cmsghdr *)(mhdr)->msg_control : \
+           (struct cmsghdr *)NULL)
+
+#define CMSG_NXTHDR(mhdr, cmsg) \
+        (((cmsg) == NULL) ? CMSG_FIRSTHDR(mhdr) : \
+         (((u8_t *)(cmsg) + ALIGN_H((cmsg)->cmsg_len) \
+                            + ALIGN_D(sizeof(struct cmsghdr)) > \
+           (u8_t *)((mhdr)->msg_control) + (mhdr)->msg_controllen) ? \
+          (struct cmsghdr *)NULL : \
+          (struct cmsghdr *)((void*)((u8_t *)(cmsg) + \
+                                      ALIGN_H((cmsg)->cmsg_len)))))
+
+#define CMSG_DATA(cmsg) ((void*)((u8_t *)(cmsg) + \
+                         ALIGN_D(sizeof(struct cmsghdr))))
+
+#define CMSG_SPACE(length) (ALIGN_D(sizeof(struct cmsghdr)) + \
+                            ALIGN_H(length))
+
+#define CMSG_LEN(length) (ALIGN_D(sizeof(struct cmsghdr)) + \
+                           length)
+
+/* Set socket options argument */
+#define IFNAMSIZ NETIF_NAMESIZE
+struct ifreq {
+  char ifr_name[IFNAMSIZ]; /* Interface name */
+};
+
+/* Socket protocol types (TCP/UDP/RAW) */
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c)
+ */
+#define SO_REUSEADDR   0x0004 /* Allow local address reuse */
+#define SO_KEEPALIVE   0x0008 /* keep connections alive */
+#define SO_BROADCAST   0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
+
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_DEBUG        0x0001 /* Unimplemented: turn on debugging info recording */
+#define SO_ACCEPTCONN   0x0002 /* socket has had listen() */
+#define SO_DONTROUTE    0x0010 /* Unimplemented: just use interface addresses */
+#define SO_USELOOPBACK  0x0040 /* Unimplemented: bypass hardware when possible */
+#define SO_LINGER       0x0080 /* linger on close if data present */
+#define SO_DONTLINGER   ((int)(~SO_LINGER))
+#define SO_OOBINLINE    0x0100 /* Unimplemented: leave received OOB data in line */
+#define SO_REUSEPORT    0x0200 /* Unimplemented: allow local address & port reuse */
+#define SO_SNDBUF       0x1001 /* Unimplemented: send buffer size */
+#define SO_RCVBUF       0x1002 /* receive buffer size */
+#define SO_SNDLOWAT     0x1003 /* Unimplemented: send low-water mark */
+#define SO_RCVLOWAT     0x1004 /* Unimplemented: receive low-water mark */
+#define SO_SNDTIMEO     0x1005 /* send timeout */
+#define SO_RCVTIMEO     0x1006 /* receive timeout */
+#define SO_ERROR        0x1007 /* get error status and clear */
+#define SO_TYPE         0x1008 /* get socket type */
+#define SO_CONTIMEO     0x1009 /* Unimplemented: connect timeout */
+#define SO_NO_CHECK     0x100a /* don't create UDP checksum */
+#define SO_BINDTODEVICE 0x100b /* bind to device */
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+  int l_onoff;                /* option on/off */
+  int l_linger;               /* linger time in seconds */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#if LWIP_IPV6
+#define AF_INET6        10
+#else /* LWIP_IPV6 */
+#define AF_INET6        AF_UNSPEC
+#endif /* LWIP_IPV6 */
+#define PF_INET         AF_INET
+#define PF_INET6        AF_INET6
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_ICMP    1
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+#if LWIP_IPV6
+#define IPPROTO_IPV6    41
+#define IPPROTO_ICMPV6  58
+#endif /* LWIP_IPV6 */
+#define IPPROTO_UDPLITE 136
+#define IPPROTO_RAW     255
+
+/* Flags we can use with send and recv. */
+#define MSG_PEEK       0x01    /* Peeks at an incoming message */
+#define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
+#define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
+#define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
+#define MSG_MORE       0x10    /* Sender will send more */
+#define MSG_NOSIGNAL   0x20    /* Uninmplemented: Requests not to send the SIGPIPE signal if an attempt to send is made on a stream-oriented socket that is no longer connected. */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS             1
+#define IP_TTL             2
+#define IP_PKTINFO         8
+
+#if LWIP_TCP
+/*
+ * Options for level IPPROTO_TCP
+ */
+#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
+#define TCP_KEEPIDLE   0x03    /* set pcb->keep_idle  - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
+#define TCP_KEEPINTVL  0x04    /* set pcb->keep_intvl - Use seconds for get/setsockopt */
+#define TCP_KEEPCNT    0x05    /* set pcb->keep_cnt   - Use number of probes sent for get/setsockopt */
+#endif /* LWIP_TCP */
+
+#if LWIP_IPV6
+/*
+ * Options for level IPPROTO_IPV6
+ */
+#define IPV6_CHECKSUM       7  /* RFC3542: calculate and insert the ICMPv6 checksum for raw sockets. */
+#define IPV6_V6ONLY         27 /* RFC3493: boolean control to restrict AF_INET6 sockets to IPv6 communications only. */
+#endif /* LWIP_IPV6 */
+
+#if LWIP_UDP && LWIP_UDPLITE
+/*
+ * Options for level IPPROTO_UDPLITE
+ */
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif /* LWIP_UDP && LWIP_UDPLITE*/
+
+
+#if LWIP_MULTICAST_TX_OPTIONS
+/*
+ * Options and types for UDP multicast traffic handling
+ */
+#define IP_MULTICAST_TTL   5
+#define IP_MULTICAST_IF    6
+#define IP_MULTICAST_LOOP  7
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_IGMP
+/*
+ * Options and types related to multicast membership
+ */
+#define IP_ADD_MEMBERSHIP  3
+#define IP_DROP_MEMBERSHIP 4
+
+typedef struct ip_mreq {
+    struct in_addr imr_multiaddr; /* IP multicast address of group */
+    struct in_addr imr_interface; /* local IP address of interface */
+} ip_mreq;
+#endif /* LWIP_IGMP */
+
+#if LWIP_IPV4
+struct in_pktinfo {
+  unsigned int   ipi_ifindex;  /* Interface index */
+  struct in_addr ipi_addr;     /* Destination (from header) address */
+};
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6_MLD
+/*
+ * Options and types related to IPv6 multicast membership
+ */
+#define IPV6_JOIN_GROUP      12
+#define IPV6_ADD_MEMBERSHIP  IPV6_JOIN_GROUP
+#define IPV6_LEAVE_GROUP     13
+#define IPV6_DROP_MEMBERSHIP IPV6_LEAVE_GROUP
+
+typedef struct ipv6_mreq {
+  struct in6_addr ipv6mr_multiaddr; /*  IPv6 multicast addr */
+  unsigned int    ipv6mr_interface; /*  interface index, or 0 */
+} ipv6_mreq;
+#endif /* LWIP_IPV6_MLD */
+
+/*
+ * The Type of Service provides an indication of the abstract
+ * parameters of the quality of service desired.  These parameters are
+ * to be used to guide the selection of the actual service parameters
+ * when transmitting a datagram through a particular network.  Several
+ * networks offer service precedence, which somehow treats high
+ * precedence traffic as more important than other traffic (generally
+ * by accepting only traffic above a certain precedence at time of high
+ * load).  The major choice is a three way tradeoff between low-delay,
+ * high-reliability, and high-throughput.
+ * The use of the Delay, Throughput, and Reliability indications may
+ * increase the cost (in some sense) of the service.  In many networks
+ * better performance for one of these parameters is coupled with worse
+ * performance on another.  Except for very unusual cases at most two
+ * of these three indications should be set.
+ */
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * The Network Control precedence designation is intended to be used
+ * within a network only.  The actual use and control of that
+ * designation is up to each network. The Internetwork Control
+ * designation is intended for use by gateway control originators only.
+ * If the actual use of these precedence designations is of concern to
+ * a particular network, it is the responsibility of that network to
+ * control the access to, and use of, those precedence designations.
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ * lwip_ioctl only supports FIONREAD and FIONBIO, for now
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000UL    /* no parameters */
+#define IOC_OUT         0x40000000UL    /* copy out parameters */
+#define IOC_IN          0x80000000UL    /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        ((long)(IOC_VOID|((x)<<8)|(y)))
+
+#define _IOR(x,y,t)     ((long)(IOC_OUT|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)))
+
+#define _IOW(x,y,t)     ((long)(IOC_IN|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)))
+#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls: unimplemented */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+/* commands for fnctl */
+#ifndef F_GETFL
+#define F_GETFL 3
+#endif
+#ifndef F_SETFL
+#define F_SETFL 4
+#endif
+
+/* File status flags and file access modes for fnctl,
+   these are bits in an int. */
+#ifndef O_NONBLOCK
+#define O_NONBLOCK  1 /* nonblocking I/O */
+#endif
+#ifndef O_NDELAY
+#define O_NDELAY    O_NONBLOCK /* same as O_NONBLOCK, for compatibility */
+#endif
+#ifndef O_RDONLY
+#define O_RDONLY    2
+#endif
+#ifndef O_WRONLY
+#define O_WRONLY    4
+#endif
+#ifndef O_RDWR
+#define O_RDWR      (O_RDONLY|O_WRONLY)
+#endif
+
+#ifndef SHUT_RD
+  #define SHUT_RD   0
+  #define SHUT_WR   1
+  #define SHUT_RDWR 2
+#endif
+
+/* FD_SET used for lwip_select */
+#ifndef FD_SET
+#undef  FD_SETSIZE
+/* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
+#define FD_SETSIZE    MEMP_NUM_NETCONN
+#define LWIP_SELECT_MAXNFDS (FD_SETSIZE + LWIP_SOCKET_OFFSET)
+#define FDSETSAFESET(n, code) do { \
+  if (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0)) { \
+  code; }} while(0)
+#define FDSETSAFEGET(n, code) (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0) ?\
+  (code) : 0)
+#define FD_SET(n, p)  FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] = (u8_t)((p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] |  (1 << (((n)-LWIP_SOCKET_OFFSET) & 7))))
+#define FD_CLR(n, p)  FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] = (u8_t)((p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] & ~(1 << (((n)-LWIP_SOCKET_OFFSET) & 7))))
+#define FD_ISSET(n,p) FDSETSAFEGET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] &   (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
+#define FD_ZERO(p)    memset((void*)(p), 0, sizeof(*(p)))
+
+typedef struct fd_set
+{
+  unsigned char fd_bits [(FD_SETSIZE+7)/8];
+} fd_set;
+
+#elif FD_SETSIZE < (LWIP_SOCKET_OFFSET + MEMP_NUM_NETCONN)
+#error "external FD_SETSIZE too small for number of sockets"
+#else
+#define LWIP_SELECT_MAXNFDS FD_SETSIZE
+#endif /* FD_SET */
+
+/* poll-related defines and types */
+/* @todo: find a better way to guard the definition of these defines and types if already defined */
+#if !defined(POLLIN) && !defined(POLLOUT)
+#define POLLIN     0x1
+#define POLLOUT    0x2
+#define POLLERR    0x4
+#define POLLNVAL   0x8
+/* Below values are unimplemented */
+#define POLLRDNORM 0x10
+#define POLLRDBAND 0x20
+#define POLLPRI    0x40
+#define POLLWRNORM 0x80
+#define POLLWRBAND 0x100
+#define POLLHUP    0x200
+typedef unsigned int nfds_t;
+struct pollfd
+{
+  int fd;
+  short events;
+  short revents;
+};
+#endif
+
+/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
+ * by your system, set this to 0 and include <sys/time.h> in cc.h */
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+struct timeval {
+  long    tv_sec;         /* seconds */
+  long    tv_usec;        /* and microseconds */
+};
+#endif /* LWIP_TIMEVAL_PRIVATE */
+
+#define lwip_socket_init() /* Compatibility define, no init needed. */
+void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */
+void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */
+
+#if LWIP_COMPAT_SOCKETS == 2
+/* This helps code parsers/code completion by not having the COMPAT functions as defines */
+#define lwip_accept       accept
+#define lwip_bind         bind
+#define lwip_shutdown     shutdown
+#define lwip_getpeername  getpeername
+#define lwip_getsockname  getsockname
+#define lwip_setsockopt   setsockopt
+#define lwip_getsockopt   getsockopt
+#define lwip_close        closesocket
+#define lwip_connect      connect
+#define lwip_listen       listen
+#define lwip_recv         recv
+#define lwip_recvmsg      recvmsg
+#define lwip_recvfrom     recvfrom
+#define lwip_send         send
+#define lwip_sendmsg      sendmsg
+#define lwip_sendto       sendto
+#define lwip_socket       socket
+#if LWIP_SOCKET_SELECT
+#define lwip_select       select
+#endif
+#if LWIP_SOCKET_POLL
+#define lwip_poll         poll
+#endif
+#define lwip_ioctl        ioctlsocket
+#define lwip_inet_ntop    inet_ntop
+#define lwip_inet_pton    inet_pton
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+#define lwip_read         read
+#define lwip_readv        readv
+#define lwip_write        write
+#define lwip_writev       writev
+#undef lwip_close
+#define lwip_close        close
+#define closesocket(s)    close(s)
+int fcntl(int s, int cmd, ...);
+#undef lwip_ioctl
+#define lwip_ioctl        ioctl
+#define ioctlsocket       ioctl
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+#endif /* LWIP_COMPAT_SOCKETS == 2 */
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+ int lwip_close(int s);
+int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+ssize_t lwip_recv(int s, void *mem, size_t len, int flags);
+ssize_t lwip_read(int s, void *mem, size_t len);
+ssize_t lwip_readv(int s, const struct iovec *iov, int iovcnt);
+ssize_t lwip_recvfrom(int s, void *mem, size_t len, int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+ssize_t lwip_recvmsg(int s, struct msghdr *message, int flags);
+ssize_t lwip_send(int s, const void *dataptr, size_t size, int flags);
+ssize_t lwip_sendmsg(int s, const struct msghdr *message, int flags);
+ssize_t lwip_sendto(int s, const void *dataptr, size_t size, int flags,
+    const struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+ssize_t lwip_write(int s, const void *dataptr, size_t size);
+ssize_t lwip_writev(int s, const struct iovec *iov, int iovcnt);
+#if LWIP_SOCKET_SELECT
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+#endif
+#if LWIP_SOCKET_POLL
+int lwip_poll(struct pollfd *fds, nfds_t nfds, int timeout);
+#endif
+int lwip_ioctl(int s, long cmd, void *argp);
+int lwip_fcntl(int s, int cmd, int val);
+const char *lwip_inet_ntop(int af, const void *src, char *dst, socklen_t size);
+int lwip_inet_pton(int af, const char *src, void *dst);
+
+#if LWIP_COMPAT_SOCKETS
+#if LWIP_COMPAT_SOCKETS != 2
+/** @ingroup socket */
+#define accept(s,addr,addrlen)                    lwip_accept(s,addr,addrlen)
+/** @ingroup socket */
+#define bind(s,name,namelen)                      lwip_bind(s,name,namelen)
+/** @ingroup socket */
+#define shutdown(s,how)                           lwip_shutdown(s,how)
+/** @ingroup socket */
+#define getpeername(s,name,namelen)               lwip_getpeername(s,name,namelen)
+/** @ingroup socket */
+#define getsockname(s,name,namelen)               lwip_getsockname(s,name,namelen)
+/** @ingroup socket */
+#define setsockopt(s,level,optname,opval,optlen)  lwip_setsockopt(s,level,optname,opval,optlen)
+/** @ingroup socket */
+#define getsockopt(s,level,optname,opval,optlen)  lwip_getsockopt(s,level,optname,opval,optlen)
+/** @ingroup socket */
+#define closesocket(s)                            lwip_close(s)
+/** @ingroup socket */
+#define connect(s,name,namelen)                   lwip_connect(s,name,namelen)
+/** @ingroup socket */
+#define listen(s,backlog)                         lwip_listen(s,backlog)
+/** @ingroup socket */
+#define recv(s,mem,len,flags)                     lwip_recv(s,mem,len,flags)
+/** @ingroup socket */
+#define recvmsg(s,message,flags)                  lwip_recvmsg(s,message,flags)
+/** @ingroup socket */
+#define recvfrom(s,mem,len,flags,from,fromlen)    lwip_recvfrom(s,mem,len,flags,from,fromlen)
+/** @ingroup socket */
+#define send(s,dataptr,size,flags)                lwip_send(s,dataptr,size,flags)
+/** @ingroup socket */
+#define sendmsg(s,message,flags)                  lwip_sendmsg(s,message,flags)
+/** @ingroup socket */
+#define sendto(s,dataptr,size,flags,to,tolen)     lwip_sendto(s,dataptr,size,flags,to,tolen)
+/** @ingroup socket */
+#define socket(domain,type,protocol)              lwip_socket(domain,type,protocol)
+#if LWIP_SOCKET_SELECT
+/** @ingroup socket */
+#define select(maxfdp1,readset,writeset,exceptset,timeout)     lwip_select(maxfdp1,readset,writeset,exceptset,timeout)
+#endif
+#if LWIP_SOCKET_POLL
+/** @ingroup socket */
+#define poll(fds,nfds,timeout)                    lwip_poll(fds,nfds,timeout)
+#endif
+/** @ingroup socket */
+#define ioctlsocket(s,cmd,argp)                   lwip_ioctl(s,cmd,argp)
+/** @ingroup socket */
+#define inet_ntop(af,src,dst,size)                lwip_inet_ntop(af,src,dst,size)
+/** @ingroup socket */
+#define inet_pton(af,src,dst)                     lwip_inet_pton(af,src,dst)
+
+#if LWIP_POSIX_SOCKETS_IO_NAMES
+/** @ingroup socket */
+#define read(s,mem,len)                           lwip_read(s,mem,len)
+/** @ingroup socket */
+#define readv(s,iov,iovcnt)                       lwip_readv(s,iov,iovcnt)
+/** @ingroup socket */
+#define write(s,dataptr,len)                      lwip_write(s,dataptr,len)
+/** @ingroup socket */
+#define writev(s,iov,iovcnt)                      lwip_writev(s,iov,iovcnt)
+/** @ingroup socket */
+#define close(s)                                  lwip_close(s)
+/** @ingroup socket */
+#define fcntl(s,cmd,val)                          lwip_fcntl(s,cmd,val)
+/** @ingroup socket */
+#define ioctl(s,cmd,argp)                         lwip_ioctl(s,cmd,argp)
+#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
+#endif /* LWIP_COMPAT_SOCKETS != 2 */
+
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_SOCKET */
+
+#endif /* LWIP_HDR_SOCKETS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/stats.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/stats.h
new file mode 100644
index 000000000..b570dbacf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/stats.h
@@ -0,0 +1,491 @@
+/**
+ * @file
+ * Statistics API (to be used from TCPIP thread)
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_STATS_H
+#define LWIP_HDR_STATS_H
+
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_LARGE
+#define LWIP_STATS_LARGE 0
+#endif
+
+#if LWIP_STATS_LARGE
+#define STAT_COUNTER     u32_t
+#define STAT_COUNTER_F   U32_F
+#else
+#define STAT_COUNTER     u16_t
+#define STAT_COUNTER_F   U16_F
+#endif
+
+/** Protocol related stats */
+struct stats_proto {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER fw;               /* Forwarded packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER rterr;            /* Routing error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER opterr;           /* Error in options. */
+  STAT_COUNTER err;              /* Misc error. */
+  STAT_COUNTER cachehit;
+};
+
+/** IGMP stats */
+struct stats_igmp {
+  STAT_COUNTER xmit;             /* Transmitted packets. */
+  STAT_COUNTER recv;             /* Received packets. */
+  STAT_COUNTER drop;             /* Dropped packets. */
+  STAT_COUNTER chkerr;           /* Checksum error. */
+  STAT_COUNTER lenerr;           /* Invalid length error. */
+  STAT_COUNTER memerr;           /* Out of memory error. */
+  STAT_COUNTER proterr;          /* Protocol error. */
+  STAT_COUNTER rx_v1;            /* Received v1 frames. */
+  STAT_COUNTER rx_group;         /* Received group-specific queries. */
+  STAT_COUNTER rx_general;       /* Received general queries. */
+  STAT_COUNTER rx_report;        /* Received reports. */
+  STAT_COUNTER tx_join;          /* Sent joins. */
+  STAT_COUNTER tx_leave;         /* Sent leaves. */
+  STAT_COUNTER tx_report;        /* Sent reports. */
+};
+
+/** Memory stats */
+struct stats_mem {
+#if defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY
+  const char *name;
+#endif /* defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY */
+  STAT_COUNTER err;
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;
+  STAT_COUNTER illegal;
+};
+
+/** System element stats */
+struct stats_syselem {
+  STAT_COUNTER used;
+  STAT_COUNTER max;
+  STAT_COUNTER err;
+};
+
+/** System stats */
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mutex;
+  struct stats_syselem mbox;
+};
+
+/** SNMP MIB2 stats */
+struct stats_mib2 {
+  /* IP */
+  u32_t ipinhdrerrors;
+  u32_t ipinaddrerrors;
+  u32_t ipinunknownprotos;
+  u32_t ipindiscards;
+  u32_t ipindelivers;
+  u32_t ipoutrequests;
+  u32_t ipoutdiscards;
+  u32_t ipoutnoroutes;
+  u32_t ipreasmoks;
+  u32_t ipreasmfails;
+  u32_t ipfragoks;
+  u32_t ipfragfails;
+  u32_t ipfragcreates;
+  u32_t ipreasmreqds;
+  u32_t ipforwdatagrams;
+  u32_t ipinreceives;
+
+  /* TCP */
+  u32_t tcpactiveopens;
+  u32_t tcppassiveopens;
+  u32_t tcpattemptfails;
+  u32_t tcpestabresets;
+  u32_t tcpoutsegs;
+  u32_t tcpretranssegs;
+  u32_t tcpinsegs;
+  u32_t tcpinerrs;
+  u32_t tcpoutrsts;
+
+  /* UDP */
+  u32_t udpindatagrams;
+  u32_t udpnoports;
+  u32_t udpinerrors;
+  u32_t udpoutdatagrams;
+
+  /* ICMP */
+  u32_t icmpinmsgs;
+  u32_t icmpinerrors;
+  u32_t icmpindestunreachs;
+  u32_t icmpintimeexcds;
+  u32_t icmpinparmprobs;
+  u32_t icmpinsrcquenchs;
+  u32_t icmpinredirects;
+  u32_t icmpinechos;
+  u32_t icmpinechoreps;
+  u32_t icmpintimestamps;
+  u32_t icmpintimestampreps;
+  u32_t icmpinaddrmasks;
+  u32_t icmpinaddrmaskreps;
+  u32_t icmpoutmsgs;
+  u32_t icmpouterrors;
+  u32_t icmpoutdestunreachs;
+  u32_t icmpouttimeexcds;
+  u32_t icmpoutechos; /* can be incremented by user application ('ping') */
+  u32_t icmpoutechoreps;
+};
+
+/**
+ * @ingroup netif_mib2
+ * SNMP MIB2 interface stats
+ */
+struct stats_mib2_netif_ctrs {
+  /** The total number of octets received on the interface, including framing characters */
+  u32_t ifinoctets;
+  /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
+   * not addressed to a multicast or broadcast address at this sub-layer */
+  u32_t ifinucastpkts;
+  /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
+   * addressed to a multicast or broadcast address at this sub-layer */
+  u32_t ifinnucastpkts;
+  /** The number of inbound packets which were chosen to be discarded even though no errors had
+   * been detected to prevent their being deliverable to a higher-layer protocol. One possible
+   * reason for discarding such a packet could be to free up buffer space */
+  u32_t ifindiscards;
+  /** For packet-oriented interfaces, the number of inbound packets that contained errors
+   * preventing them from being deliverable to a higher-layer protocol.  For character-
+   * oriented or fixed-length interfaces, the number of inbound transmission units that
+   * contained errors preventing them from being deliverable to a higher-layer protocol. */
+  u32_t ifinerrors;
+  /** For packet-oriented interfaces, the number of packets received via the interface which
+   * were discarded because of an unknown or unsupported protocol.  For character-oriented
+   * or fixed-length interfaces that support protocol multiplexing the number of transmission
+   * units received via the interface which were discarded because of an unknown or unsupported
+   * protocol. For any interface that does not support protocol multiplexing, this counter will
+   * always be 0 */
+  u32_t ifinunknownprotos;
+  /** The total number of octets transmitted out of the interface, including framing characters. */
+  u32_t ifoutoctets;
+  /** The total number of packets that higher-level protocols requested be transmitted, and
+   * which were not addressed to a multicast or broadcast address at this sub-layer, including
+   * those that were discarded or not sent. */
+  u32_t ifoutucastpkts;
+  /** The total number of packets that higher-level protocols requested be transmitted, and which
+   * were addressed to a multicast or broadcast address at this sub-layer, including
+   * those that were discarded or not sent. */
+  u32_t ifoutnucastpkts;
+  /** The number of outbound packets which were chosen to be discarded even though no errors had
+   * been detected to prevent their being transmitted.  One possible reason for discarding
+   * such a packet could be to free up buffer space. */
+  u32_t ifoutdiscards;
+  /** For packet-oriented interfaces, the number of outbound packets that could not be transmitted
+   * because of errors. For character-oriented or fixed-length interfaces, the number of outbound
+   * transmission units that could not be transmitted because of errors. */
+  u32_t ifouterrors;
+};
+
+/** lwIP stats container */
+struct stats_ {
+#if LINK_STATS
+  /** Link level */
+  struct stats_proto link;
+#endif
+#if ETHARP_STATS
+  /** ARP */
+  struct stats_proto etharp;
+#endif
+#if IPFRAG_STATS
+  /** Fragmentation */
+  struct stats_proto ip_frag;
+#endif
+#if IP_STATS
+  /** IP */
+  struct stats_proto ip;
+#endif
+#if ICMP_STATS
+  /** ICMP */
+  struct stats_proto icmp;
+#endif
+#if IGMP_STATS
+  /** IGMP */
+  struct stats_igmp igmp;
+#endif
+#if UDP_STATS
+  /** UDP */
+  struct stats_proto udp;
+#endif
+#if TCP_STATS
+  /** TCP */
+  struct stats_proto tcp;
+#endif
+#if MEM_STATS
+  /** Heap */
+  struct stats_mem mem;
+#endif
+#if MEMP_STATS
+  /** Internal memory pools */
+  struct stats_mem *memp[MEMP_MAX];
+#endif
+#if SYS_STATS
+  /** System */
+  struct stats_sys sys;
+#endif
+#if IP6_STATS
+  /** IPv6 */
+  struct stats_proto ip6;
+#endif
+#if ICMP6_STATS
+  /** ICMP6 */
+  struct stats_proto icmp6;
+#endif
+#if IP6_FRAG_STATS
+  /** IPv6 fragmentation */
+  struct stats_proto ip6_frag;
+#endif
+#if MLD6_STATS
+  /** Multicast listener discovery */
+  struct stats_igmp mld6;
+#endif
+#if ND6_STATS
+  /** Neighbor discovery */
+  struct stats_proto nd6;
+#endif
+#if MIB2_STATS
+  /** SNMP MIB2 */
+  struct stats_mib2 mib2;
+#endif
+};
+
+/** Global variable containing lwIP internal statistics. Add this to your debugger's watchlist. */
+extern struct stats_ lwip_stats;
+
+/** Init statistics */
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#define STATS_DEC(x) --lwip_stats.x
+#define STATS_INC_USED(x, y, type) do { lwip_stats.x.used = (type)(lwip_stats.x.used + y); \
+                                if (lwip_stats.x.max < lwip_stats.x.used) { \
+                                    lwip_stats.x.max = lwip_stats.x.used; \
+                                } \
+                             } while(0)
+#define STATS_GET(x) lwip_stats.x
+#else /* LWIP_STATS */
+#define stats_init()
+#define STATS_INC(x)
+#define STATS_DEC(x)
+#define STATS_INC_USED(x, y, type)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP")
+#else
+#define TCP_STATS_INC(x)
+#define TCP_STATS_DISPLAY()
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP")
+#else
+#define UDP_STATS_INC(x)
+#define UDP_STATS_DISPLAY()
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP")
+#else
+#define ICMP_STATS_INC(x)
+#define ICMP_STATS_DISPLAY()
+#endif
+
+#if IGMP_STATS
+#define IGMP_STATS_INC(x) STATS_INC(x)
+#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp, "IGMP")
+#else
+#define IGMP_STATS_INC(x)
+#define IGMP_STATS_DISPLAY()
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP")
+#else
+#define IP_STATS_INC(x)
+#define IP_STATS_DISPLAY()
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG")
+#else
+#define IPFRAG_STATS_INC(x)
+#define IPFRAG_STATS_DISPLAY()
+#endif
+
+#if ETHARP_STATS
+#define ETHARP_STATS_INC(x) STATS_INC(x)
+#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP")
+#else
+#define ETHARP_STATS_INC(x)
+#define ETHARP_STATS_DISPLAY()
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK")
+#else
+#define LINK_STATS_INC(x)
+#define LINK_STATS_DISPLAY()
+#endif
+
+#if MEM_STATS
+#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y
+#define MEM_STATS_INC(x) STATS_INC(mem.x)
+#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y, mem_size_t)
+#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x = (mem_size_t)((lwip_stats.mem.x) - (y))
+#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP")
+#else
+#define MEM_STATS_AVAIL(x, y)
+#define MEM_STATS_INC(x)
+#define MEM_STATS_INC_USED(x, y)
+#define MEM_STATS_DEC_USED(x, y)
+#define MEM_STATS_DISPLAY()
+#endif
+
+ #if MEMP_STATS
+#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i]->x)
+#define MEMP_STATS_DISPLAY(i) stats_display_memp(lwip_stats.memp[i], i)
+#define MEMP_STATS_GET(x, i) STATS_GET(memp[i]->x)
+ #else
+#define MEMP_STATS_DEC(x, i)
+#define MEMP_STATS_DISPLAY(i)
+#define MEMP_STATS_GET(x, i) 0
+#endif
+
+#if SYS_STATS
+#define SYS_STATS_INC(x) STATS_INC(sys.x)
+#define SYS_STATS_DEC(x) STATS_DEC(sys.x)
+#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1, STAT_COUNTER)
+#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys)
+#else
+#define SYS_STATS_INC(x)
+#define SYS_STATS_DEC(x)
+#define SYS_STATS_INC_USED(x)
+#define SYS_STATS_DISPLAY()
+#endif
+
+#if IP6_STATS
+#define IP6_STATS_INC(x) STATS_INC(x)
+#define IP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6, "IPv6")
+#else
+#define IP6_STATS_INC(x)
+#define IP6_STATS_DISPLAY()
+#endif
+
+#if ICMP6_STATS
+#define ICMP6_STATS_INC(x) STATS_INC(x)
+#define ICMP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp6, "ICMPv6")
+#else
+#define ICMP6_STATS_INC(x)
+#define ICMP6_STATS_DISPLAY()
+#endif
+
+#if IP6_FRAG_STATS
+#define IP6_FRAG_STATS_INC(x) STATS_INC(x)
+#define IP6_FRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6_frag, "IPv6 FRAG")
+#else
+#define IP6_FRAG_STATS_INC(x)
+#define IP6_FRAG_STATS_DISPLAY()
+#endif
+
+#if MLD6_STATS
+#define MLD6_STATS_INC(x) STATS_INC(x)
+#define MLD6_STATS_DISPLAY() stats_display_igmp(&lwip_stats.mld6, "MLDv1")
+#else
+#define MLD6_STATS_INC(x)
+#define MLD6_STATS_DISPLAY()
+#endif
+
+#if ND6_STATS
+#define ND6_STATS_INC(x) STATS_INC(x)
+#define ND6_STATS_DISPLAY() stats_display_proto(&lwip_stats.nd6, "ND")
+#else
+#define ND6_STATS_INC(x)
+#define ND6_STATS_DISPLAY()
+#endif
+
+#if MIB2_STATS
+#define MIB2_STATS_INC(x) STATS_INC(x)
+#else
+#define MIB2_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+void stats_display_proto(struct stats_proto *proto, const char *name);
+void stats_display_igmp(struct stats_igmp *igmp, const char *name);
+void stats_display_mem(struct stats_mem *mem, const char *name);
+void stats_display_memp(struct stats_mem *mem, int index);
+void stats_display_sys(struct stats_sys *sys);
+#else /* LWIP_STATS_DISPLAY */
+#define stats_display()
+#define stats_display_proto(proto, name)
+#define stats_display_igmp(igmp, name)
+#define stats_display_mem(mem, name)
+#define stats_display_memp(mem, index)
+#define stats_display_sys(sys)
+#endif /* LWIP_STATS_DISPLAY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_STATS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sys.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sys.h
new file mode 100644
index 000000000..85f50aad7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/sys.h
@@ -0,0 +1,560 @@
+/**
+ * @file
+ * OS abstraction layer
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ */
+
+#ifndef LWIP_HDR_SYS_H
+#define LWIP_HDR_SYS_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mutex_t;
+typedef u8_t sys_mbox_t;
+
+#define sys_sem_new(s, c) ERR_OK
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_arch_sem_wait(s,t)
+#define sys_sem_free(s)
+#define sys_sem_valid(s) 0
+#define sys_sem_valid_val(s) 0
+#define sys_sem_set_invalid(s)
+#define sys_sem_set_invalid_val(s)
+#define sys_mutex_new(mu) ERR_OK
+#define sys_mutex_lock(mu)
+#define sys_mutex_unlock(mu)
+#define sys_mutex_free(mu)
+#define sys_mutex_valid(mu) 0
+#define sys_mutex_set_invalid(mu)
+#define sys_mbox_new(m, s) ERR_OK
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_tryfetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_trypost(m,d)
+#define sys_mbox_free(m)
+#define sys_mbox_valid(m)
+#define sys_mbox_valid_val(m)
+#define sys_mbox_set_invalid(m)
+#define sys_mbox_set_invalid_val(m)
+
+#define sys_thread_new(n,t,a,s,p)
+
+#define sys_msleep(t)
+
+#else /* NO_SYS */
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffffUL
+
+/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate.
+ * For now we use the same magic value, but we allow this to change in future.
+ */
+#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT
+
+#include "lwip/err.h"
+#include "arch/sys_arch.h"
+
+/** Function prototype for thread functions */
+typedef void (*lwip_thread_fn)(void *arg);
+
+/* Function prototypes for functions to be implemented by platform ports
+   (in sys_arch.c) */
+
+/* Mutex functions: */
+
+/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
+    should be used instead */
+#ifndef LWIP_COMPAT_MUTEX
+#define LWIP_COMPAT_MUTEX 0
+#endif
+
+#if LWIP_COMPAT_MUTEX
+/* for old ports that don't have mutexes: define them to binary semaphores */
+#define sys_mutex_t                   sys_sem_t
+#define sys_mutex_new(mutex)          sys_sem_new(mutex, 1)
+#define sys_mutex_lock(mutex)         sys_sem_wait(mutex)
+#define sys_mutex_unlock(mutex)       sys_sem_signal(mutex)
+#define sys_mutex_free(mutex)         sys_sem_free(mutex)
+#define sys_mutex_valid(mutex)        sys_sem_valid(mutex)
+#define sys_mutex_set_invalid(mutex)  sys_sem_set_invalid(mutex)
+
+#else /* LWIP_COMPAT_MUTEX */
+
+/**
+ * @ingroup sys_mutex
+ * Create a new mutex.
+ * Note that mutexes are expected to not be taken recursively by the lwIP code,
+ * so both implementation types (recursive or non-recursive) should work.
+ * The mutex is allocated to the memory that 'mutex'
+ * points to (which can be both a pointer or the actual OS structure).
+ * If the mutex has been created, ERR_OK should be returned. Returning any
+ * other error will provide a hint what went wrong, but except for assertions,
+ * no real error handling is implemented.
+ * 
+ * @param mutex pointer to the mutex to create
+ * @return ERR_OK if successful, another err_t otherwise
+ */
+err_t sys_mutex_new(sys_mutex_t *mutex);
+/**
+ * @ingroup sys_mutex
+ * Blocks the thread until the mutex can be grabbed.
+ * @param mutex the mutex to lock
+ */
+void sys_mutex_lock(sys_mutex_t *mutex);
+/**
+ * @ingroup sys_mutex
+ * Releases the mutex previously locked through 'sys_mutex_lock()'.
+ * @param mutex the mutex to unlock
+ */
+void sys_mutex_unlock(sys_mutex_t *mutex);
+/**
+ * @ingroup sys_mutex
+ * Deallocates a mutex.
+ * @param mutex the mutex to delete
+ */
+void sys_mutex_free(sys_mutex_t *mutex);
+#ifndef sys_mutex_valid
+/**
+ * @ingroup sys_mutex
+ * Returns 1 if the mutes is valid, 0 if it is not valid.
+ * When using pointers, a simple way is to check the pointer for != NULL.
+ * When directly using OS structures, implementing this may be more complex.
+ * This may also be a define, in which case the function is not prototyped.
+ */
+int sys_mutex_valid(sys_mutex_t *mutex);
+#endif
+#ifndef sys_mutex_set_invalid
+/**
+ * @ingroup sys_mutex
+ * Invalidate a mutex so that sys_mutex_valid() returns 0.
+ * ATTENTION: This does NOT mean that the mutex shall be deallocated:
+ * sys_mutex_free() is always called before calling this function!
+ * This may also be a define, in which case the function is not prototyped.
+ */
+void sys_mutex_set_invalid(sys_mutex_t *mutex);
+#endif
+#endif /* LWIP_COMPAT_MUTEX */
+
+/* Semaphore functions: */
+
+/**
+ * @ingroup sys_sem
+ * Create a new semaphore
+ * Creates a new semaphore. The semaphore is allocated to the memory that 'sem'
+ * points to (which can be both a pointer or the actual OS structure).
+ * The "count" argument specifies the initial state of the semaphore (which is
+ * either 0 or 1).
+ * If the semaphore has been created, ERR_OK should be returned. Returning any
+ * other error will provide a hint what went wrong, but except for assertions,
+ * no real error handling is implemented.
+ *
+ * @param sem pointer to the semaphore to create
+ * @param count initial count of the semaphore
+ * @return ERR_OK if successful, another err_t otherwise
+ */
+err_t sys_sem_new(sys_sem_t *sem, u8_t count);
+/**
+ * @ingroup sys_sem
+ * Signals a semaphore
+ * @param sem the semaphore to signal
+ */
+void sys_sem_signal(sys_sem_t *sem);
+/**
+ * @ingroup sys_sem
+ *  Blocks the thread while waiting for the semaphore to be signaled. If the
+ * "timeout" argument is non-zero, the thread should only be blocked for the
+ * specified time (measured in milliseconds). If the "timeout" argument is zero,
+ * the thread should be blocked until the semaphore is signalled.
+ * 
+ * The return value is SYS_ARCH_TIMEOUT if the semaphore wasn't signaled within
+ * the specified time or any other value if it was signaled (with or without
+ * waiting).
+ * Notice that lwIP implements a function with a similar name,
+ * sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+ * 
+ * @param sem the semaphore to wait for
+ * @param timeout timeout in milliseconds to wait (0 = wait forever)
+ * @return SYS_ARCH_TIMEOUT on timeout, any other value on success
+ */
+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout);
+/**
+ * @ingroup sys_sem
+ * Deallocates a semaphore.
+ * @param sem semaphore to delete
+ */
+void sys_sem_free(sys_sem_t *sem);
+/** Wait for a semaphore - forever/no timeout */
+#define sys_sem_wait(sem)                  sys_arch_sem_wait(sem, 0)
+#ifndef sys_sem_valid
+/**
+ * @ingroup sys_sem
+ * Returns 1 if the semaphore is valid, 0 if it is not valid.
+ * When using pointers, a simple way is to check the pointer for != NULL.
+ * When directly using OS structures, implementing this may be more complex.
+ * This may also be a define, in which case the function is not prototyped.
+ */
+int sys_sem_valid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_set_invalid
+/**
+ * @ingroup sys_sem
+ * Invalidate a semaphore so that sys_sem_valid() returns 0.
+ * ATTENTION: This does NOT mean that the semaphore shall be deallocated:
+ * sys_sem_free() is always called before calling this function!
+ * This may also be a define, in which case the function is not prototyped.
+ */
+void sys_sem_set_invalid(sys_sem_t *sem);
+#endif
+#ifndef sys_sem_valid_val
+/**
+ * Same as sys_sem_valid() but taking a value, not a pointer
+ */
+#define sys_sem_valid_val(sem)       sys_sem_valid(&(sem))
+#endif
+#ifndef sys_sem_set_invalid_val
+/**
+ * Same as sys_sem_set_invalid() but taking a value, not a pointer
+ */
+#define sys_sem_set_invalid_val(sem) sys_sem_set_invalid(&(sem))
+#endif
+
+#ifndef sys_msleep
+/**
+ * @ingroup sys_misc
+ * Sleep for specified number of ms
+ */
+void sys_msleep(u32_t ms); /* only has a (close to) 1 ms resolution. */
+#endif
+
+/* Mailbox functions. */
+
+/**
+ * @ingroup sys_mbox
+ * Creates an empty mailbox for maximum "size" elements. Elements stored
+ * in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+ * in your lwipopts.h, or ignore this parameter in your implementation
+ * and use a default size.
+ * If the mailbox has been created, ERR_OK should be returned. Returning any
+ * other error will provide a hint what went wrong, but except for assertions,
+ * no real error handling is implemented.
+ * 
+ * @param mbox pointer to the mbox to create
+ * @param size (minimum) number of messages in this mbox
+ * @return ERR_OK if successful, another err_t otherwise
+ */
+err_t sys_mbox_new(sys_mbox_t *mbox, int size);
+/**
+ * @ingroup sys_mbox
+ * Post a message to an mbox - may not fail
+ * -> blocks if full, only to be used from tasks NOT from ISR!
+ * 
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL)
+ */
+void sys_mbox_post(sys_mbox_t *mbox, void *msg);
+/**
+ * @ingroup sys_mbox
+ * Try to post a message to an mbox - may fail if full.
+ * Can be used from ISR (if the sys arch layer allows this).
+ * Returns ERR_MEM if it is full, else, ERR_OK if the "msg" is posted.
+ * 
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL)
+ */
+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg);
+/**
+ * @ingroup sys_mbox
+ * Try to post a message to an mbox - may fail if full.
+ * To be be used from ISR.
+ * Returns ERR_MEM if it is full, else, ERR_OK if the "msg" is posted.
+ * 
+ * @param mbox mbox to posts the message
+ * @param msg message to post (ATTENTION: can be NULL)
+ */
+err_t sys_mbox_trypost_fromisr(sys_mbox_t *mbox, void *msg);
+/**
+ * @ingroup sys_mbox
+ * Blocks the thread until a message arrives in the mailbox, but does
+ * not block the thread longer than "timeout" milliseconds (similar to
+ * the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+ * be blocked until a message arrives. The "msg" argument is a result
+ * parameter that is set by the function (i.e., by doing "*msg =
+ * ptr"). The "msg" parameter maybe NULL to indicate that the message
+ * should be dropped.
+ * The return values are the same as for the sys_arch_sem_wait() function:
+ * SYS_ARCH_TIMEOUT if there was a timeout, any other value if a messages
+ * is received.
+ * 
+ * Note that a function with a similar name, sys_mbox_fetch(), is
+ * implemented by lwIP. 
+ * 
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @param timeout maximum time (in milliseconds) to wait for a message (0 = wait forever)
+ * @return SYS_ARCH_TIMEOUT on timeout, any other value if a message has been received
+ */
+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout);
+/* Allow port to override with a macro, e.g. special timeout for sys_arch_mbox_fetch() */
+#ifndef sys_arch_mbox_tryfetch
+/**
+ * @ingroup sys_mbox
+ * This is similar to sys_arch_mbox_fetch, however if a message is not
+ * present in the mailbox, it immediately returns with the code
+ * SYS_MBOX_EMPTY. On success 0 is returned.
+ * To allow for efficient implementations, this can be defined as a
+ * function-like macro in sys_arch.h instead of a normal function. For
+ * example, a naive implementation could be:
+ * \#define sys_arch_mbox_tryfetch(mbox,msg) sys_arch_mbox_fetch(mbox,msg,1)
+ * although this would introduce unnecessary delays.
+ * 
+ * @param mbox mbox to get a message from
+ * @param msg pointer where the message is stored
+ * @return 0 (milliseconds) if a message has been received
+ *         or SYS_MBOX_EMPTY if the mailbox is empty
+ */
+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg);
+#endif
+/**
+ * For now, we map straight to sys_arch implementation.
+ */
+#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
+/**
+ * @ingroup sys_mbox
+ * Deallocates a mailbox. If there are messages still present in the
+ * mailbox when the mailbox is deallocated, it is an indication of a
+ * programming error in lwIP and the developer should be notified.
+ * 
+ * @param mbox mbox to delete
+ */
+void sys_mbox_free(sys_mbox_t *mbox);
+#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0)
+#ifndef sys_mbox_valid
+/**
+ * @ingroup sys_mbox
+ * Returns 1 if the mailbox is valid, 0 if it is not valid.
+ * When using pointers, a simple way is to check the pointer for != NULL.
+ * When directly using OS structures, implementing this may be more complex.
+ * This may also be a define, in which case the function is not prototyped.
+ */
+int sys_mbox_valid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_set_invalid
+/**
+ * @ingroup sys_mbox
+ * Invalidate a mailbox so that sys_mbox_valid() returns 0.
+ * ATTENTION: This does NOT mean that the mailbox shall be deallocated:
+ * sys_mbox_free() is always called before calling this function!
+ * This may also be a define, in which case the function is not prototyped.
+ */
+void sys_mbox_set_invalid(sys_mbox_t *mbox);
+#endif
+#ifndef sys_mbox_valid_val
+/**
+ * Same as sys_mbox_valid() but taking a value, not a pointer
+ */
+#define sys_mbox_valid_val(mbox)       sys_mbox_valid(&(mbox))
+#endif
+#ifndef sys_mbox_set_invalid_val
+/**
+ * Same as sys_mbox_set_invalid() but taking a value, not a pointer
+ */
+#define sys_mbox_set_invalid_val(mbox) sys_mbox_set_invalid(&(mbox))
+#endif
+
+
+/**
+ * @ingroup sys_misc
+ * The only thread function:
+ * Starts a new thread named "name" with priority "prio" that will begin its
+ * execution in the function "thread()". The "arg" argument will be passed as an
+ * argument to the thread() function. The stack size to used for this thread is
+ * the "stacksize" parameter. The id of the new thread is returned. Both the id
+ * and the priority are system dependent.
+ * ATTENTION: although this function returns a value, it MUST NOT FAIL (ports have to assert this!)
+ * 
+ * @param name human-readable name for the thread (used for debugging purposes)
+ * @param thread thread-function
+ * @param arg parameter passed to 'thread'
+ * @param stacksize stack size in bytes for the new thread (may be ignored by ports)
+ * @param prio priority of the new thread (may be ignored by ports) */
+sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio);
+
+#endif /* NO_SYS */
+
+/**
+ * @ingroup sys_misc
+ * sys_init() must be called before anything else.
+ * Initialize the sys_arch layer.
+ */
+void sys_init(void);
+
+#ifndef sys_jiffies
+/**
+ * Ticks/jiffies since power up.
+ */
+u32_t sys_jiffies(void);
+#endif
+
+/**
+ * @ingroup sys_time
+ * Returns the current time in milliseconds,
+ * may be the same as sys_jiffies or at least based on it.
+ * Don't care for wraparound, this is only used for time diffs.
+ * Not implementing this function means you cannot use some modules (e.g. TCP
+ * timestamps, internal timeouts for NO_SYS==1).
+ */
+u32_t Milliseconds(void);
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/**
+ * @ingroup sys_prot
+ * SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/**
+ * @ingroup sys_prot
+ * SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/**
+ * @ingroup sys_prot
+ * SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+/*
+ * Macros to set/get and increase/decrease variables in a thread-safe way.
+ * Use these for accessing variable that are used from more than one thread.
+ */
+
+#ifndef SYS_ARCH_INC
+#define SYS_ARCH_INC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var += val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_INC */
+
+#ifndef SYS_ARCH_DEC
+#define SYS_ARCH_DEC(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var -= val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_DEC */
+
+#ifndef SYS_ARCH_GET
+#define SYS_ARCH_GET(var, ret) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                ret = var; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_GET */
+
+#ifndef SYS_ARCH_SET
+#define SYS_ARCH_SET(var, val) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                var = val; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_SET */
+
+#ifndef SYS_ARCH_LOCKED
+#define SYS_ARCH_LOCKED(code) do { \
+                                SYS_ARCH_DECL_PROTECT(old_level); \
+                                SYS_ARCH_PROTECT(old_level); \
+                                code; \
+                                SYS_ARCH_UNPROTECT(old_level); \
+                              } while(0)
+#endif /* SYS_ARCH_LOCKED */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_SYS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcp.h
new file mode 100644
index 000000000..daf759946
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcp.h
@@ -0,0 +1,500 @@
+/**
+ * @file
+ * TCP API (to be used from TCPIP thread)\n
+ * See also @ref tcp_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_TCP_H
+#define LWIP_HDR_TCP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/tcpbase.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+#include "lwip/err.h"
+#include "lwip/ip6.h"
+#include "lwip/ip6_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tcp_pcb;
+struct tcp_pcb_listen;
+
+/** Function prototype for tcp accept callback functions. Called when a new
+ * connection can be accepted on a listening pcb.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param newpcb The new connection pcb
+ * @param err An error code if there has been an error accepting.
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+/** Function prototype for tcp receive callback functions. Called when data has
+ * been received.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which received data
+ * @param p The received data (or NULL when the connection has been closed!)
+ * @param err An error code if there has been an error receiving
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb,
+                             struct pbuf *p, err_t err);
+
+/** Function prototype for tcp sent callback functions. Called when sent data has
+ * been acknowledged by the remote side. Use it to free corresponding resources.
+ * This also means that the pcb has now space available to send new data.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb for which data has been acknowledged
+ * @param len The amount of bytes acknowledged
+ * @return ERR_OK: try to send some data by calling tcp_output
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb,
+                              u16_t len);
+
+/** Function prototype for tcp poll callback functions. Called periodically as
+ * specified by @see tcp_poll.
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb tcp pcb
+ * @return ERR_OK: try to send some data by calling tcp_output
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ */
+typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb);
+
+/** Function prototype for tcp error callback functions. Called when the pcb
+ * receives a RST or is unexpectedly closed for any other reason.
+ *
+ * @note The corresponding pcb is already freed when this callback is called!
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param err Error code to indicate why the pcb has been closed
+ *            ERR_ABRT: aborted through tcp_abort or by a TCP timer
+ *            ERR_RST: the connection was reset by the remote host
+ */
+typedef void  (*tcp_err_fn)(void *arg, err_t err);
+
+/** Function prototype for tcp connected callback functions. Called when a pcb
+ * is connected to the remote side after initiating a connection attempt by
+ * calling tcp_connect().
+ *
+ * @param arg Additional argument to pass to the callback function (@see tcp_arg())
+ * @param tpcb The connection pcb which is connected
+ * @param err An unused error code, always ERR_OK currently ;-) @todo!
+ *            Only return ERR_ABRT if you have called tcp_abort from within the
+ *            callback function!
+ *
+ * @note When a connection attempt fails, the error callback is currently called!
+ */
+typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err);
+
+#if LWIP_WND_SCALE
+#define RCV_WND_SCALE(pcb, wnd) (((wnd) >> (pcb)->rcv_scale))
+#define SND_WND_SCALE(pcb, wnd) (((wnd) << (pcb)->snd_scale))
+#define TCPWND16(x)             ((u16_t)LWIP_MIN((x), 0xFFFF))
+#define TCP_WND_MAX(pcb)        ((tcpwnd_size_t)(((pcb)->flags & TF_WND_SCALE) ? TCP_WND : TCPWND16(TCP_WND)))
+#else
+#define RCV_WND_SCALE(pcb, wnd) (wnd)
+#define SND_WND_SCALE(pcb, wnd) (wnd)
+#define TCPWND16(x)             (x)
+#define TCP_WND_MAX(pcb)        TCP_WND
+#endif
+/* Increments a tcpwnd_size_t and holds at max value rather than rollover */
+#define TCP_WND_INC(wnd, inc)   do { \
+                                  if ((tcpwnd_size_t)(wnd + inc) >= wnd) { \
+                                    wnd = (tcpwnd_size_t)(wnd + inc); \
+                                  } else { \
+                                    wnd = (tcpwnd_size_t)-1; \
+                                  } \
+                                } while(0)
+
+#if LWIP_TCP_SACK_OUT
+/** SACK ranges to include in ACK packets.
+ * SACK entry is invalid if left==right. */
+struct tcp_sack_range {
+  /** Left edge of the SACK: the first acknowledged sequence number. */
+  u32_t left;
+  /** Right edge of the SACK: the last acknowledged sequence number +1 (so first NOT acknowledged). */
+  u32_t right;
+};
+#endif /* LWIP_TCP_SACK_OUT */
+
+/** Function prototype for deallocation of arguments. Called *just before* the
+ * pcb is freed, so don't expect to be able to do anything with this pcb!
+ *
+ * @param id ext arg id (allocated via @ref tcp_ext_arg_alloc_id)
+ * @param data pointer to the data (set via @ref tcp_ext_arg_set before)
+ */
+typedef void (*tcp_extarg_callback_pcb_destroyed_fn)(u8_t id, void *data);
+
+/** Function prototype to transition arguments from a listening pcb to an accepted pcb
+ *
+ * @param id ext arg id (allocated via @ref tcp_ext_arg_alloc_id)
+ * @param lpcb the listening pcb accepting a connection
+ * @param cpcb the newly allocated connection pcb
+ * @return ERR_OK if OK, any error if connection should be dropped
+ */
+typedef err_t (*tcp_extarg_callback_passive_open_fn)(u8_t id, struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb);
+
+/** A table of callback functions that is invoked for ext arguments */
+struct tcp_ext_arg_callbacks {
+  /** @ref tcp_extarg_callback_pcb_destroyed_fn */
+  tcp_extarg_callback_pcb_destroyed_fn destroy;
+  /** @ref tcp_extarg_callback_passive_open_fn */
+  tcp_extarg_callback_passive_open_fn passive_open;
+};
+
+#define LWIP_TCP_PCB_NUM_EXT_ARG_ID_INVALID 0xFF
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+/* This is the structure for ext args in tcp pcbs (used as array) */
+struct tcp_pcb_ext_args {
+  const struct tcp_ext_arg_callbacks *callbacks;
+  void *data;
+};
+/* This is a helper define to prevent zero size arrays if disabled */
+#define TCP_PCB_EXTARGS struct tcp_pcb_ext_args ext_args[LWIP_TCP_PCB_NUM_EXT_ARGS];
+#else
+#define TCP_PCB_EXTARGS
+#endif
+
+typedef u16_t tcpflags_t;
+#define TCP_ALLFLAGS 0xffffU
+
+/**
+ * members common to struct tcp_pcb and struct tcp_listen_pcb
+ */
+#define TCP_PCB_COMMON(type) \
+  type *next; /* for the linked list */ \
+  void *callback_arg; \
+  TCP_PCB_EXTARGS \
+  enum tcp_state state; /* TCP state */ \
+  u8_t prio; \
+  /* ports are in host byte order */ \
+  u16_t local_port
+
+
+/** the TCP protocol control block for listening pcbs */
+struct tcp_pcb_listen {
+/** Common members of all PCB types */
+  IP_PCB;
+/** Protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb_listen);
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected. */
+  tcp_accept_fn accept;
+#endif /* LWIP_CALLBACK_API */
+
+#if TCP_LISTEN_BACKLOG
+  u8_t backlog;
+  u8_t accepts_pending;
+#endif /* TCP_LISTEN_BACKLOG */
+};
+
+
+/** the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  TCP_PCB_COMMON(struct tcp_pcb);
+
+  /* ports are in host byte order */
+  u16_t remote_port;
+
+  tcpflags_t flags;
+#define TF_ACK_DELAY   0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW     0x02U   /* Immediate ACK. */
+#define TF_INFR        0x04U   /* In fast recovery. */
+#define TF_CLOSEPEND   0x08U   /* If this is set, tcp_close failed to enqueue the FIN (retried in tcp_tmr) */
+#define TF_RXCLOSED    0x10U   /* rx closed by tcp_shutdown */
+#define TF_FIN         0x20U   /* Connection was closed locally (FIN segment enqueued). */
+#define TF_NODELAY     0x40U   /* Disable Nagle algorithm */
+#define TF_NAGLEMEMERR 0x80U   /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
+#if LWIP_WND_SCALE
+#define TF_WND_SCALE   0x0100U /* Window Scale option enabled */
+#endif
+#if TCP_LISTEN_BACKLOG
+#define TF_BACKLOGPEND 0x0200U /* If this is set, a connection pcb has increased the backlog on its listener */
+#endif
+#if LWIP_TCP_TIMESTAMPS
+#define TF_TIMESTAMP   0x0400U   /* Timestamp option enabled */
+#endif
+#define TF_RTO         0x0800U /* RTO timer has fired, in-flight data moved to unsent and being retransmitted */
+#if LWIP_TCP_SACK_OUT
+#define TF_SACK        0x1000U /* Selective ACKs enabled */
+#endif
+
+  /* the rest of the fields are in host byte order
+     as we have to do some math with them */
+
+  /* Timers */
+  u8_t polltmr, pollinterval;
+  u8_t last_timer;
+  u32_t tmr;
+
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  tcpwnd_size_t rcv_wnd;   /* receiver window available */
+  tcpwnd_size_t rcv_ann_wnd; /* receiver window to announce */
+  u32_t rcv_ann_right_edge; /* announced right edge of window */
+
+#if LWIP_TCP_SACK_OUT
+  /* SACK ranges to include in ACK packets (entry is invalid if left==right) */
+  struct tcp_sack_range rcv_sacks[LWIP_TCP_MAX_SACK_NUM];
+#define LWIP_TCP_SACK_VALID(pcb, idx) ((pcb)->rcv_sacks[idx].left != (pcb)->rcv_sacks[idx].right)
+#endif /* LWIP_TCP_SACK_OUT */
+
+  /* Retransmission timer. */
+  s16_t rtime;
+
+  u16_t mss;   /* maximum segment size */
+
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @see "Congestion Avoidance and Control" by Van Jacobson and Karels */
+
+  s16_t rto;    /* retransmission time-out (in ticks of TCP_SLOW_INTERVAL) */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u8_t dupacks;
+  u32_t lastack; /* Highest acknowledged seqno. */
+
+  /* congestion avoidance/control variables */
+  tcpwnd_size_t cwnd;
+  tcpwnd_size_t ssthresh;
+
+  /* first byte following last rto byte */
+  u32_t rto_end;
+
+  /* sender variables */
+  u32_t snd_nxt;   /* next new seqno to be sent */
+  u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last
+                             window update. */
+  u32_t snd_lbb;       /* Sequence number of next byte to be buffered. */
+  tcpwnd_size_t snd_wnd;   /* sender window */
+  tcpwnd_size_t snd_wnd_max; /* the maximum sender window announced by the remote host */
+
+  tcpwnd_size_t snd_buf;   /* Available buffer space for sending (in bytes). */
+#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3)
+  u16_t snd_queuelen; /* Number of pbufs currently in the send buffer. */
+
+#if TCP_OVERSIZE
+  /* Extra bytes available at the end of the last pbuf in unsent. */
+  u16_t unsent_oversize;
+#endif /* TCP_OVERSIZE */
+
+  tcpwnd_size_t bytes_acked;
+
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+  struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
+
+#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
+  struct tcp_pcb_listen* listener;
+#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  tcp_sent_fn sent;
+  /* Function to be called when (in-sequence) data has arrived. */
+  tcp_recv_fn recv;
+  /* Function to be called when a connection has been set up. */
+  tcp_connected_fn connected;
+  /* Function which is called periodically. */
+  tcp_poll_fn poll;
+  /* Function to be called whenever a fatal error occurs. */
+  tcp_err_fn errf;
+#endif /* LWIP_CALLBACK_API */
+
+#if LWIP_TCP_TIMESTAMPS
+  u32_t ts_lastacksent;
+  u32_t ts_recent;
+#endif /* LWIP_TCP_TIMESTAMPS */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keep_idle;
+#if LWIP_TCP_KEEPALIVE
+  u32_t keep_intvl;
+  u32_t keep_cnt;
+#endif /* LWIP_TCP_KEEPALIVE */
+
+  /* Persist timer counter */
+  u8_t persist_cnt;
+  /* Persist timer back-off */
+  u8_t persist_backoff;
+  /* Number of persist probes */
+  u8_t persist_probe;
+
+  /* KEEPALIVE counter */
+  u8_t keep_cnt_sent;
+
+#if LWIP_WND_SCALE
+  u8_t snd_scale;
+  u8_t rcv_scale;
+#endif
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#endif /* LWIP_EVENT_API */
+
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_new_ip_type (u8_t type);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+#if LWIP_CALLBACK_API
+void             tcp_recv    (struct tcp_pcb *pcb, tcp_recv_fn recv);
+void             tcp_sent    (struct tcp_pcb *pcb, tcp_sent_fn sent);
+void             tcp_err     (struct tcp_pcb *pcb, tcp_err_fn err);
+void             tcp_accept  (struct tcp_pcb *pcb, tcp_accept_fn accept);
+#endif /* LWIP_CALLBACK_API */
+void             tcp_poll    (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval);
+
+#define          tcp_set_flags(pcb, set_flags)     do { (pcb)->flags = (tcpflags_t)((pcb)->flags |  (set_flags)); } while(0)
+#define          tcp_clear_flags(pcb, clr_flags)   do { (pcb)->flags = (tcpflags_t)((pcb)->flags & (tcpflags_t)(~(clr_flags) & TCP_ALLFLAGS)); } while(0)
+#define          tcp_is_flag_set(pcb, flag)        (((pcb)->flags & (flag)) != 0)
+
+#if LWIP_TCP_TIMESTAMPS
+#define          tcp_mss(pcb)             (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12)  : (pcb)->mss)
+#else /* LWIP_TCP_TIMESTAMPS */
+/** @ingroup tcp_raw */
+#define          tcp_mss(pcb)             ((pcb)->mss)
+#endif /* LWIP_TCP_TIMESTAMPS */
+/** @ingroup tcp_raw */
+#define          tcp_sndbuf(pcb)          (TCPWND16((pcb)->snd_buf))
+/** @ingroup tcp_raw */
+#define          tcp_sndqueuelen(pcb)     ((pcb)->snd_queuelen)
+/** @ingroup tcp_raw */
+#define          tcp_nagle_disable(pcb)   tcp_set_flags(pcb, TF_NODELAY)
+/** @ingroup tcp_raw */
+#define          tcp_nagle_enable(pcb)    tcp_clear_flags(pcb, TF_NODELAY)
+/** @ingroup tcp_raw */
+#define          tcp_nagle_disabled(pcb)  tcp_is_flag_set(pcb, TF_NODELAY)
+
+#if TCP_LISTEN_BACKLOG
+#define          tcp_backlog_set(pcb, new_backlog) do { \
+  LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", (pcb)->state == LISTEN); \
+  ((struct tcp_pcb_listen *)(pcb))->backlog = ((new_backlog) ? (new_backlog) : 1); } while(0)
+void             tcp_backlog_delayed(struct tcp_pcb* pcb);
+void             tcp_backlog_accepted(struct tcp_pcb* pcb);
+#else  /* TCP_LISTEN_BACKLOG */
+#define          tcp_backlog_set(pcb, new_backlog)
+#define          tcp_backlog_delayed(pcb)
+#define          tcp_backlog_accepted(pcb)
+#endif /* TCP_LISTEN_BACKLOG */
+#define          tcp_accepted(pcb) do { LWIP_UNUSED_ARG(pcb); } while(0) /* compatibility define, not needed any more */
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
+                              u16_t port);
+void             tcp_bind_netif(struct tcp_pcb *pcb, const struct netif *netif);
+err_t            tcp_connect (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
+                              u16_t port, tcp_connected_fn connected);
+
+struct tcp_pcb * tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err);
+struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
+/** @ingroup tcp_raw */
+#define          tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
+
+void             tcp_abort (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx);
+
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+                              u8_t apiflags);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+err_t            tcp_output  (struct tcp_pcb *pcb);
+
+err_t            tcp_tcp_get_tcp_addrinfo(struct tcp_pcb *pcb, int local, ip_addr_t *addr, u16_t *port);
+
+#define tcp_dbg_get_tcp_state(pcb) ((pcb)->state)
+
+/* for compatibility with older implementation */
+#define tcp_new_ip6() tcp_new_ip_type(IPADDR_TYPE_V6)
+
+#if LWIP_TCP_PCB_NUM_EXT_ARGS
+u8_t tcp_ext_arg_alloc_id(void);
+void tcp_ext_arg_set_callbacks(struct tcp_pcb *pcb, uint8_t id, const struct tcp_ext_arg_callbacks * const callbacks);
+void tcp_ext_arg_set(struct tcp_pcb *pcb, uint8_t id, void *arg);
+void *tcp_ext_arg_get(const struct tcp_pcb *pcb, uint8_t id);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcpbase.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcpbase.h
new file mode 100644
index 000000000..002307465
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcpbase.h
@@ -0,0 +1,88 @@
+/**
+ * @file
+ * Base TCP API definitions shared by TCP and ALTCP\n
+ * See also @ref tcp_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_TCPBASE_H
+#define LWIP_HDR_TCPBASE_H
+
+#include "lwip/opt.h"
+
+#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if LWIP_WND_SCALE
+typedef u32_t tcpwnd_size_t;
+#else
+typedef u16_t tcpwnd_size_t;
+#endif
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+/* ATTENTION: this depends on state number ordering! */
+#define TCP_STATE_IS_CLOSING(state) ((state) >= FIN_WAIT_1)
+
+/* Flags for "apiflags" parameter in tcp_write */
+#define TCP_WRITE_FLAG_COPY 0x01
+#define TCP_WRITE_FLAG_MORE 0x02
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+const char* tcp_debug_state_str(enum tcp_state s);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_TCP */
+
+#endif /* LWIP_HDR_TCPBASE_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcpip.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcpip.h
new file mode 100644
index 000000000..0b8880a9f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/tcpip.h
@@ -0,0 +1,113 @@
+/**
+ * @file
+ * Functions to sync with TCPIP thread
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_TCPIP_H
+#define LWIP_HDR_TCPIP_H
+
+#include "lwip/opt.h"
+
+#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/timeouts.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_TCPIP_CORE_LOCKING
+/** The global semaphore to lock the stack. */
+extern sys_mutex_t lock_tcpip_core;
+#if !defined LOCK_TCPIP_CORE || defined __DOXYGEN__
+/** Lock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */
+#define LOCK_TCPIP_CORE()     sys_mutex_lock(&lock_tcpip_core)
+/** Unlock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */
+#define UNLOCK_TCPIP_CORE()   sys_mutex_unlock(&lock_tcpip_core)
+#endif /* LOCK_TCPIP_CORE */
+#else /* LWIP_TCPIP_CORE_LOCKING */
+#define LOCK_TCPIP_CORE()
+#define UNLOCK_TCPIP_CORE()
+#endif /* LWIP_TCPIP_CORE_LOCKING */
+
+struct pbuf;
+struct netif;
+
+/** Function prototype for the init_done function passed to tcpip_init */
+typedef void (*tcpip_init_done_fn)(void *arg);
+/** Function prototype for functions passed to tcpip_callback() */
+typedef void (*tcpip_callback_fn)(void *ctx);
+
+/* Forward declarations */
+struct tcpip_callback_msg;
+
+void   tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg);
+
+err_t  tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn);
+err_t  tcpip_input(struct pbuf *p, struct netif *inp);
+
+err_t  tcpip_try_callback(tcpip_callback_fn function, void *ctx);
+err_t  tcpip_callback(tcpip_callback_fn function, void *ctx);
+/**  @ingroup lwip_os
+ * @deprecated use tcpip_try_callback() or tcpip_callback() instead
+ */
+#define tcpip_callback_with_block(function, ctx, block) ((block != 0)? tcpip_callback(function, ctx) : tcpip_try_callback(function, ctx))
+
+struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx);
+void   tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg);
+err_t  tcpip_callbackmsg_trycallback(struct tcpip_callback_msg* msg);
+err_t  tcpip_callbackmsg_trycallback_fromisr(struct tcpip_callback_msg* msg);
+
+/* free pbufs or heap memory from another context without blocking */
+err_t  pbuf_free_callback(struct pbuf *p);
+err_t  mem_free_callback(void *m);
+
+#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
+err_t  tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+err_t  tcpip_untimeout(sys_timeout_handler h, void *arg);
+#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
+
+#ifdef TCPIP_THREAD_TEST
+int tcpip_thread_poll_one(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !NO_SYS */
+
+#endif /* LWIP_HDR_TCPIP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/timeouts.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/timeouts.h
new file mode 100644
index 000000000..b601f9eb3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/timeouts.h
@@ -0,0 +1,128 @@
+/**
+ * @file
+ * Timer implementations
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *         Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_TIMEOUTS_H
+#define LWIP_HDR_TIMEOUTS_H
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#if !NO_SYS
+#include "lwip/sys.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef LWIP_DEBUG_TIMERNAMES
+#ifdef LWIP_DEBUG
+#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG
+#else /* LWIP_DEBUG */
+#define LWIP_DEBUG_TIMERNAMES 0
+#endif /* LWIP_DEBUG*/
+#endif
+
+/** Returned by sys_timeouts_sleeptime() to indicate there is no timer, so we
+ * can sleep forever.
+ */
+#define SYS_TIMEOUTS_SLEEPTIME_INFINITE 0xFFFFFFFF
+
+/** Function prototype for a stack-internal timer function that has to be
+ * called at a defined interval */
+typedef void (* lwip_cyclic_timer_handler)(void);
+
+/** This struct contains information about a stack-internal timer function
+ that has to be called at a defined interval */
+struct lwip_cyclic_timer {
+  u32_t interval_ms;
+  lwip_cyclic_timer_handler handler;
+#if LWIP_DEBUG_TIMERNAMES
+  const char* handler_name;
+#endif /* LWIP_DEBUG_TIMERNAMES */
+};
+
+/** This array contains all stack-internal cyclic timers. To get the number of
+ * timers, use lwip_num_cyclic_timers */
+extern const struct lwip_cyclic_timer lwip_cyclic_timers[];
+/** Array size of lwip_cyclic_timers[] */
+extern const int lwip_num_cyclic_timers;
+
+#if LWIP_TIMERS
+
+/** Function prototype for a timeout callback function. Register such a function
+ * using sys_timeout().
+ *
+ * @param arg Additional argument to pass to the function - set up by sys_timeout()
+ */
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeo {
+  struct sys_timeo *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+#if LWIP_DEBUG_TIMERNAMES
+  const char* handler_name;
+#endif /* LWIP_DEBUG_TIMERNAMES */
+};
+
+void sys_timeouts_init(void);
+
+#if LWIP_DEBUG_TIMERNAMES
+void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name);
+#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler)
+#else /* LWIP_DEBUG_TIMERNAMES */
+void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg);
+#endif /* LWIP_DEBUG_TIMERNAMES */
+
+void sys_untimeout(sys_timeout_handler handler, void *arg);
+void sys_restart_timeouts(void);
+void sys_check_timeouts(void);
+u32_t sys_timeouts_sleeptime(void);
+
+#if LWIP_TESTMODE
+struct sys_timeo** sys_timeouts_get_next_timeout(void);
+void lwip_cyclic_timer(void *arg);
+#endif
+
+#endif /* LWIP_TIMERS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_TIMEOUTS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/udp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/udp.h
new file mode 100644
index 000000000..b1c78e58d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/lwip/udp.h
@@ -0,0 +1,195 @@
+/**
+ * @file
+ * UDP API (to be used from TCPIP thread)\n
+ * See also @ref udp_raw
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_UDP_H
+#define LWIP_HDR_UDP_H
+
+#include "lwip/opt.h"
+
+#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+#include "lwip/ip.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/prot/udp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UDP_FLAGS_NOCHKSUM       0x01U
+#define UDP_FLAGS_UDPLITE        0x02U
+#define UDP_FLAGS_CONNECTED      0x04U
+#define UDP_FLAGS_MULTICAST_LOOP 0x08U
+
+struct udp_pcb;
+
+/** Function prototype for udp pcb receive callback functions
+ * addr and port are in same byte order as in the pcb
+ * The callback is responsible for freeing the pbuf
+ * if it's not used any more.
+ *
+ * ATTENTION: Be aware that 'addr' might point into the pbuf 'p' so freeing this pbuf
+ *            can make 'addr' invalid, too.
+ *
+ * @param arg user supplied argument (udp_pcb.recv_arg)
+ * @param pcb the udp_pcb which received data
+ * @param p the packet buffer that was received
+ * @param addr the remote IP address from which the packet was received
+ * @param port the remote port from which the packet was received
+ */
+typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    const ip_addr_t *addr, u16_t port);
+
+/** the UDP protocol control block */
+struct udp_pcb {
+/** Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  /** ports are in host byte order */
+  u16_t local_port, remote_port;
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#if LWIP_IPV4
+  /** outgoing network interface for multicast packets, by IPv4 address (if not 'any') */
+  ip4_addr_t mcast_ip4;
+#endif /* LWIP_IPV4 */
+  /** outgoing network interface for multicast packets, by interface index (if nonzero) */
+  u8_t mcast_ifindex;
+  /** TTL for outgoing multicast packets */
+  u8_t mcast_ttl;
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if LWIP_UDPLITE
+  /** used for UDP_LITE only */
+  u16_t chksum_len_rx, chksum_len_tx;
+#endif /* LWIP_UDPLITE */
+
+  /** receive callback function */
+  udp_recv_fn recv;
+  /** user-supplied argument for the recv callback */
+  void *recv_arg;
+};
+/* udp_pcbs export for external reference (e.g. SNMP agent) */
+extern struct udp_pcb *udp_pcbs;
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+struct udp_pcb * udp_new_ip_type(u8_t type);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
+                                 u16_t port);
+void             udp_bind_netif (struct udp_pcb *pcb, const struct netif* netif);
+err_t            udp_connect    (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
+                                 u16_t port);
+void             udp_disconnect (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb, udp_recv_fn recv,
+                                 void *recv_arg);
+err_t            udp_sendto_if  (struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif);
+err_t            udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif, const ip_addr_t *src_ip);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
+err_t            udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 struct netif *netif, u8_t have_chksum,
+                                 u16_t chksum);
+err_t            udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port,
+                                 u8_t have_chksum, u16_t chksum);
+err_t            udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 u8_t have_chksum, u16_t chksum);
+err_t            udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p,
+                                 const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif,
+                                 u8_t have_chksum, u16_t chksum, const ip_addr_t *src_ip);
+#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
+
+#define          udp_flags(pcb) ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+#define          udp_set_flags(pcb, set_flags)     do { (pcb)->flags = (u8_t)((pcb)->flags |  (set_flags)); } while(0)
+#define          udp_clear_flags(pcb, clr_flags)   do { (pcb)->flags = (u8_t)((pcb)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0)
+#define          udp_is_flag_set(pcb, flag)        (((pcb)->flags & (flag)) != 0)
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+
+void             udp_init       (void);
+
+/* for compatibility with older implementation */
+#define udp_new_ip6() udp_new_ip_type(IPADDR_TYPE_V6)
+
+#if LWIP_MULTICAST_TX_OPTIONS
+#if LWIP_IPV4
+#define udp_set_multicast_netif_addr(pcb, ip4addr) ip4_addr_copy((pcb)->mcast_ip4, *(ip4addr))
+#define udp_get_multicast_netif_addr(pcb)          (&(pcb)->mcast_ip4)
+#endif /* LWIP_IPV4 */
+#define udp_set_multicast_netif_index(pcb, idx)    ((pcb)->mcast_ifindex = (idx))
+#define udp_get_multicast_netif_index(pcb)         ((pcb)->mcast_ifindex)
+#define udp_set_multicast_ttl(pcb, value)          ((pcb)->mcast_ttl = (value))
+#define udp_get_multicast_ttl(pcb)                 ((pcb)->mcast_ttl)
+#endif /* LWIP_MULTICAST_TX_OPTIONS */
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+
+void udp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_UDP */
+
+#endif /* LWIP_HDR_UDP_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/bridgeif.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/bridgeif.h
new file mode 100644
index 000000000..f4f8cf144
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/bridgeif.h
@@ -0,0 +1,127 @@
+/**
+ * @file
+ * lwIP netif implementing an IEEE 802.1D MAC Bridge
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_NETIF_BRIDGEIF_H
+#define LWIP_HDR_NETIF_BRIDGEIF_H
+
+#include "netif/bridgeif_opts.h"
+
+#include "lwip/err.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct netif;
+
+#if (BRIDGEIF_MAX_PORTS < 0) || (BRIDGEIF_MAX_PORTS >= 64)
+#error BRIDGEIF_MAX_PORTS must be [1..63]
+#elif BRIDGEIF_MAX_PORTS < 8
+typedef u8_t bridgeif_portmask_t;
+#elif BRIDGEIF_MAX_PORTS < 16
+typedef u16_t bridgeif_portmask_t;
+#elif BRIDGEIF_MAX_PORTS < 32
+typedef u32_t bridgeif_portmask_t;
+#elif BRIDGEIF_MAX_PORTS < 64
+typedef u64_t bridgeif_portmask_t;
+#endif
+
+#define BR_FLOOD ((bridgeif_portmask_t)-1)
+
+/** @ingroup bridgeif
+ * Initialisation data for @ref bridgeif_init.
+ * An instance of this type must be passed as parameter 'state' to @ref netif_add
+ * when the bridge is added.
+ */
+typedef struct bridgeif_initdata_s {
+  /** MAC address of the bridge (cannot use the netif's addresses) */
+  struct eth_addr ethaddr;
+  /** Maximum number of ports in the bridge (ports are stored in an array, this
+      influences memory allocated for netif->state of the bridge netif). */
+  u8_t            max_ports;
+  /** Maximum number of dynamic/learning entries in the bridge's forwarding database.
+      In the default implementation, this controls memory consumption only. */
+  u16_t           max_fdb_dynamic_entries;
+  /** Maximum number of static forwarding entries. Influences memory consumption! */
+  u16_t           max_fdb_static_entries;
+} bridgeif_initdata_t;
+
+/** @ingroup bridgeif
+ * Use this for constant initialization of a bridgeif_initdat_t
+ * (ethaddr must be passed as ETH_ADDR())
+ */
+#define BRIDGEIF_INITDATA1(max_ports, max_fdb_dynamic_entries, max_fdb_static_entries, ethaddr) {ethaddr, max_ports, max_fdb_dynamic_entries, max_fdb_static_entries}
+/** @ingroup bridgeif
+ * Use this for constant initialization of a bridgeif_initdat_t
+ * (each byte of ethaddr must be passed)
+ */
+#define BRIDGEIF_INITDATA2(max_ports, max_fdb_dynamic_entries, max_fdb_static_entries, e0, e1, e2, e3, e4, e5) {{e0, e1, e2, e3, e4, e5}, max_ports, max_fdb_dynamic_entries, max_fdb_static_entries}
+
+err_t bridgeif_init(struct netif *netif);
+err_t bridgeif_add_port(struct netif *bridgeif, struct netif *portif);
+err_t bridgeif_fdb_add(struct netif *bridgeif, const struct eth_addr *addr, bridgeif_portmask_t ports);
+err_t bridgeif_fdb_remove(struct netif *bridgeif, const struct eth_addr *addr);
+
+/* FDB interface, can be replaced by own implementation */
+void                bridgeif_fdb_update_src(void *fdb_ptr, struct eth_addr *src_addr, u8_t port_idx);
+bridgeif_portmask_t bridgeif_fdb_get_dst_ports(void *fdb_ptr, struct eth_addr *dst_addr);
+void*               bridgeif_fdb_init(u16_t max_fdb_entries);
+
+#if BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+#ifndef BRIDGEIF_DECL_PROTECT
+/* define bridgeif protection to sys_arch_protect... */
+#include "lwip/sys.h"
+#define BRIDGEIF_DECL_PROTECT(lev)    SYS_ARCH_DECL_PROTECT(lev)
+#define BRIDGEIF_READ_PROTECT(lev)    SYS_ARCH_PROTECT(lev)
+#define BRIDGEIF_READ_UNPROTECT(lev)  SYS_ARCH_UNPROTECT(lev)
+#define BRIDGEIF_WRITE_PROTECT(lev)
+#define BRIDGEIF_WRITE_UNPROTECT(lev)
+#endif
+#else /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */
+#include "lwip/tcpip.h"
+#define BRIDGEIF_DECL_PROTECT(lev)
+#define BRIDGEIF_READ_PROTECT(lev)
+#define BRIDGEIF_READ_UNPROTECT(lev)
+#define BRIDGEIF_WRITE_PROTECT(lev)
+#define BRIDGEIF_WRITE_UNPROTECT(lev)
+#endif /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_BRIDGEIF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/bridgeif_opts.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/bridgeif_opts.h
new file mode 100644
index 000000000..b85c30174
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/bridgeif_opts.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ * lwIP netif implementing an IEEE 802.1D MAC Bridge
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_BRIDGEIF_OPTS_H
+#define LWIP_HDR_NETIF_BRIDGEIF_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * @defgroup bridgeif_opts Options
+ * @ingroup bridgeif
+ * @{
+ */
+
+/** BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT==1: set port netif's 'input' function
+ * to call directly into bridgeif code and on top of that, directly call into
+ * the selected forwarding port's 'linkoutput' function.
+ * This means that the bridgeif input/output path is protected from concurrent access
+ * but as well, *all* bridge port netif's drivers must correctly handle concurrent access!
+ * == 0: get into tcpip_thread for every input packet (no multithreading)
+ * ATTENTION: as ==0 relies on tcpip.h, the default depends on NO_SYS setting
+ */
+#ifndef BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+#define BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT  NO_SYS
+#endif
+
+/** BRIDGEIF_MAX_PORTS: this is used to create a typedef used for forwarding
+ * bit-fields: the number of bits required is this + 1 (for the internal/cpu port)
+ * (63 is the maximum, resulting in an u64_t for the bit mask)
+ * ATTENTION: this controls the maximum number of the implementation only!
+ * The max. number of ports per bridge must still be passed via netif_add parameter!
+ */
+#ifndef BRIDGEIF_MAX_PORTS
+#define BRIDGEIF_MAX_PORTS                  7
+#endif
+
+/** BRIDGEIF_DEBUG: Enable generic debugging in bridgeif.c. */
+#ifndef BRIDGEIF_DEBUG
+#define BRIDGEIF_DEBUG                      LWIP_DBG_OFF
+#endif
+
+/** BRIDGEIF_DEBUG: Enable FDB debugging in bridgeif.c. */
+#ifndef BRIDGEIF_FDB_DEBUG
+#define BRIDGEIF_FDB_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/** BRIDGEIF_DEBUG: Enable forwarding debugging in bridgeif.c. */
+#ifndef BRIDGEIF_FW_DEBUG
+#define BRIDGEIF_FW_DEBUG                   LWIP_DBG_OFF
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LWIP_HDR_NETIF_BRIDGEIF_OPTS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/etharp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/etharp.h
new file mode 100644
index 000000000..b536fd280
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/etharp.h
@@ -0,0 +1,3 @@
+/* ARP has been moved to core/ipv4, provide this #include for compatibility only */
+#include "lwip/etharp.h"
+#include "netif/ethernet.h"
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ethernet.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ethernet.h
new file mode 100644
index 000000000..49649cbf8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ethernet.h
@@ -0,0 +1,77 @@
+/**
+ * @file
+ * Ethernet input function - handles INCOMING ethernet level traffic
+ * To be used in most low-level netif implementations
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#ifndef LWIP_HDR_NETIF_ETHERNET_H
+#define LWIP_HDR_NETIF_ETHERNET_H
+
+#include "lwip/opt.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/prot/ethernet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if LWIP_ARP || LWIP_ETHERNET
+
+/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type)
+ * to a filter function that returns the correct netif when using multiple
+ * netifs on one hardware interface where the netif's low-level receive
+ * routine cannot decide for the correct netif (e.g. when mapping multiple
+ * IP addresses to one hardware interface).
+ */
+#ifndef LWIP_ARP_FILTER_NETIF
+#define LWIP_ARP_FILTER_NETIF 0
+#endif
+
+err_t ethernet_input(struct pbuf *p, struct netif *netif);
+err_t ethernet_output(struct netif* netif, struct pbuf* p, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);
+
+extern const struct eth_addr ethbroadcast, ethzero;
+
+#endif /* LWIP_ARP || LWIP_ETHERNET */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_ETHERNET_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ieee802154.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ieee802154.h
new file mode 100644
index 000000000..54e019fd0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ieee802154.h
@@ -0,0 +1,112 @@
+/**
+ * @file
+ * Definitions for IEEE 802.15.4 MAC frames
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+#ifndef LWIP_HDR_NETIF_IEEE802154_H
+#define LWIP_HDR_NETIF_IEEE802154_H
+
+#include "lwip/opt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** General MAC frame format
+ * This shows the full featured header, mainly for documentation.
+ * Some fields are omitted or shortened to achieve frame compression.
+ */
+struct ieee_802154_hdr {
+  /** See IEEE_802154_FC_* defines */
+  PACK_STRUCT_FIELD(u16_t frame_control);
+  /** Sequence number is omitted if IEEE_802154_FC_SEQNO_SUPPR is set in frame_control */
+  PACK_STRUCT_FLD_8(u8_t  sequence_number);
+  /** Destination PAN ID is omitted if Destination Addressing Mode is 0 */
+  PACK_STRUCT_FIELD(u16_t destination_pan_id);
+  /** Destination Address is omitted if Destination Addressing Mode is 0 */
+  PACK_STRUCT_FLD_8(u8_t destination_address[8]);
+  /** Source PAN ID is omitted if Source Addressing Mode is 0
+      or if IEEE_802154_FC_PANID_COMPR is set in frame control*/
+  PACK_STRUCT_FIELD(u16_t source_pan_id);
+  /** Source Address is omitted if Source Addressing Mode is 0 */
+  PACK_STRUCT_FLD_8(u8_t source_address[8]);
+  /* The rest is variable */
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* Addressing modes (2 bits) */
+#define IEEE_802154_ADDR_MODE_NO_ADDR   0x00 /* PAN ID and address fields are not present */
+#define IEEE_802154_ADDR_MODE_RESERVED  0x01 /* Reserved */
+#define IEEE_802154_ADDR_MODE_SHORT     0x02 /* Address field contains a short address (16 bit) */
+#define IEEE_802154_ADDR_MODE_EXT       0x03 /* Address field contains an extended address (64 bit) */
+
+/* IEEE 802.15.4 Frame Control definitions (2 bytes; see IEEE 802.15.4-2015 ch. 7.2.1) */
+#define IEEE_802154_FC_FT_MASK             0x0007 /* bits 0..2: Frame Type */
+#define IEEE_802154_FC_FT_BEACON               0x00
+#define IEEE_802154_FC_FT_DATA                 0x01
+#define IEEE_802154_FC_FT_ACK                  0x02
+#define IEEE_802154_FC_FT_MAC_CMD              0x03
+#define IEEE_802154_FC_FT_RESERVED             0x04
+#define IEEE_802154_FC_FT_MULTIPURPOSE         0x05
+#define IEEE_802154_FC_FT_FRAG                 0x06
+#define IEEE_802154_FC_FT_EXT                  0x07
+#define IEEE_802154_FC_SEC_EN              0x0008 /* bit 3: Security Enabled */
+#define IEEE_802154_FC_FRAME_PEND          0x0010 /* bit 4: Frame Pending */
+#define IEEE_802154_FC_ACK_REQ             0x0020 /* bit 5: AR (ACK required) */
+#define IEEE_802154_FC_PANID_COMPR         0x0040 /* bit 6: PAN ID Compression (src and dst are equal, src PAN ID omitted) */
+#define IEEE_802154_FC_RESERVED            0x0080
+#define IEEE_802154_FC_SEQNO_SUPPR         0x0100 /* bit 8: Sequence Number Suppression */
+#define IEEE_802154_FC_IE_PRESENT          0x0200 /* bit 9: IE Present */
+#define IEEE_802154_FC_DST_ADDR_MODE_MASK  0x0c00 /* bits 10..11: Destination Addressing Mode */
+#define IEEE_802154_FC_DST_ADDR_MODE_NO_ADDR   (IEEE_802154_ADDR_MODE_NO_ADDR << 10)
+#define IEEE_802154_FC_DST_ADDR_MODE_SHORT     (IEEE_802154_ADDR_MODE_SHORT << 10)
+#define IEEE_802154_FC_DST_ADDR_MODE_EXT       (IEEE_802154_ADDR_MODE_EXT << 10)
+#define IEEE_802154_FC_FRAME_VERSION_MASK  0x3000 /* bits 12..13: Frame Version */
+#define IEEE_802154_FC_FRAME_VERSION_GET(x)    (((x) & IEEE_802154_FC_FRAME_VERSION_MASK) >> 12)
+#define IEEE_802154_FC_SRC_ADDR_MODE_MASK  0xc000 /* bits 14..15: Source Addressing Mode */
+#define IEEE_802154_FC_SRC_ADDR_MODE_SHORT     (IEEE_802154_ADDR_MODE_SHORT << 14)
+#define IEEE_802154_FC_SRC_ADDR_MODE_EXT       (IEEE_802154_ADDR_MODE_EXT << 14)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_IEEE802154_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6.h
new file mode 100644
index 000000000..ecff24ba6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_H
+#define LWIP_HDR_LOWPAN6_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6
+
+#include "netif/lowpan6_common.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** 1 second period for reassembly */
+#define LOWPAN6_TMR_INTERVAL 1000
+
+void lowpan6_tmr(void);
+
+err_t lowpan6_set_context(u8_t idx, const ip6_addr_t * context);
+err_t lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low);
+
+#if LWIP_IPV4
+err_t lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
+#endif /* LWIP_IPV4 */
+err_t lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+err_t lowpan6_input(struct pbuf * p, struct netif *netif);
+err_t lowpan6_if_init(struct netif *netif);
+
+/* pan_id in network byte order. */
+err_t lowpan6_set_pan_id(u16_t pan_id);
+
+u16_t lowpan6_calc_crc(const void *buf, u16_t len);
+
+#if !NO_SYS
+err_t tcpip_6lowpan_input(struct pbuf *p, struct netif *inp);
+#endif /* !NO_SYS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_LOWPAN6_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_ble.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_ble.h
new file mode 100644
index 000000000..01896a7ff
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_ble.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ * 6LowPAN over BLE for IPv6 (RFC7668).
+ */
+
+/*
+ * Copyright (c) 2017 Benjamin Aigner
+ * Copyright (c) 2015 Inico Technologies Ltd. , Author: Ivan Delamer <delamer@inicotech.com>
+ * 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Benjamin Aigner <aignerb@technikum-wien.at>
+ * 
+ * Based on the original 6lowpan implementation of lwIP ( @see 6lowpan.c)
+ */
+ 
+#ifndef LWIP_HDR_LOWPAN6_BLE_H
+#define LWIP_HDR_LOWPAN6_BLE_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/lowpan6_common.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t rfc7668_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
+err_t rfc7668_input(struct pbuf * p, struct netif *netif);
+err_t rfc7668_set_local_addr_eui64(struct netif *netif, const u8_t *local_addr, size_t local_addr_len);
+err_t rfc7668_set_local_addr_mac48(struct netif *netif, const u8_t *local_addr, size_t local_addr_len, int is_public_addr);
+err_t rfc7668_set_peer_addr_eui64(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len);
+err_t rfc7668_set_peer_addr_mac48(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len, int is_public_addr);
+err_t rfc7668_set_context(u8_t index, const ip6_addr_t * context);
+err_t rfc7668_if_init(struct netif *netif);
+
+#if !NO_SYS
+err_t tcpip_rfc7668_input(struct pbuf *p, struct netif *inp);
+#endif
+
+void ble_addr_to_eui64(uint8_t *dst, const uint8_t *src, int public_addr);
+void eui64_to_ble_addr(uint8_t *dst, const uint8_t *src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_LOWPAN6_BLE_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_common.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_common.h
new file mode 100644
index 000000000..0dc13ab5b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_common.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * Common 6LowPAN routines for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_COMMON_H
+#define LWIP_HDR_LOWPAN6_COMMON_H
+
+#include "netif/lowpan6_opts.h"
+
+#if LWIP_IPV6 /* don't build if IPv6 is disabled in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/ip.h"
+#include "lwip/ip6_addr.h"
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Helper define for a link layer address, which can be encoded as 0, 2 or 8 bytes */
+struct lowpan6_link_addr {
+  /* encoded length of the address */
+  u8_t addr_len;
+  /* address bytes */
+  u8_t addr[8];
+};
+
+s8_t lowpan6_get_address_mode(const ip6_addr_t *ip6addr, const struct lowpan6_link_addr *mac_addr);
+
+#if LWIP_6LOWPAN_IPHC
+err_t lowpan6_compress_headers(struct netif *netif, u8_t *inbuf, size_t inbuf_size, u8_t *outbuf, size_t outbuf_size,
+                               u8_t *lowpan6_header_len_out, u8_t *hidden_header_len_out, ip6_addr_t *lowpan6_contexts,
+                               const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst);
+struct pbuf *lowpan6_decompress(struct pbuf *p, u16_t datagram_size, ip6_addr_t *lowpan6_contexts,
+                                struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest);
+#endif /* LWIP_6LOWPAN_IPHC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 */
+
+#endif /* LWIP_HDR_LOWPAN6_COMMON_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_opts.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_opts.h
new file mode 100644
index 000000000..17d46cdcc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/lowpan6_opts.h
@@ -0,0 +1,122 @@
+/**
+ * @file
+ * 6LowPAN options list
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+#ifndef LWIP_HDR_LOWPAN6_OPTS_H
+#define LWIP_HDR_LOWPAN6_OPTS_H
+
+#include "lwip/opt.h"
+
+/** LWIP_6LOWPAN_NUM_CONTEXTS: define the number of compression
+ * contexts per netif type
+ */
+#ifndef LWIP_6LOWPAN_NUM_CONTEXTS
+#define LWIP_6LOWPAN_NUM_CONTEXTS        10
+#endif
+
+/** LWIP_6LOWPAN_INFER_SHORT_ADDRESS: set this to 0 to disable creating
+ * short addresses for matching addresses (debug only)
+ */
+#ifndef LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+#define LWIP_6LOWPAN_INFER_SHORT_ADDRESS 1
+#endif
+
+/** LWIP_6LOWPAN_IPHC: set this to 0 to disable IP header compression as per
+ * RFC 6282 (which is mandatory for BLE)
+ */
+#ifndef LWIP_6LOWPAN_IPHC
+#define LWIP_6LOWPAN_IPHC                1
+#endif
+
+/** Set this to 1 if your IEEE 802.15.4 interface can calculate and check the
+ * CRC in hardware. This means TX packets get 2 zero bytes added on transmission
+ * which are to be filled with the CRC.
+ */
+#ifndef LWIP_6LOWPAN_802154_HW_CRC
+#define LWIP_6LOWPAN_802154_HW_CRC       0
+#endif
+
+/** If LWIP_6LOWPAN_802154_HW_CRC==0, this can override the default slow
+ * implementation of the CRC used for 6LoWPAN over IEEE 802.15.4 (which uses
+ * a shift register).
+ */
+#ifndef LWIP_6LOWPAN_CALC_CRC
+#define LWIP_6LOWPAN_CALC_CRC(buf, len)  lowpan6_calc_crc(buf, len)
+#endif
+
+/** Debug level for 6LoWPAN in general */
+#ifndef LWIP_LOWPAN6_DEBUG
+#define LWIP_LOWPAN6_DEBUG               LWIP_DBG_OFF
+#endif
+
+/** Debug level for 6LoWPAN over IEEE 802.15.4 */
+#ifndef LWIP_LOWPAN6_802154_DEBUG
+#define LWIP_LOWPAN6_802154_DEBUG        LWIP_DBG_OFF
+#endif
+
+/** LWIP_LOWPAN6_IP_COMPRESSED_DEBUG: enable compressed IP frame
+ * output debugging
+ */
+#ifndef LWIP_LOWPAN6_IP_COMPRESSED_DEBUG
+#define LWIP_LOWPAN6_IP_COMPRESSED_DEBUG      LWIP_DBG_OFF
+#endif
+
+/** LWIP_LOWPAN6_DECOMPRESSION_DEBUG: enable decompression debug output
+ */
+#ifndef LWIP_LOWPAN6_DECOMPRESSION_DEBUG
+#define LWIP_LOWPAN6_DECOMPRESSION_DEBUG      LWIP_DBG_OFF
+#endif
+
+/** LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG: enable decompressed IP frame
+ * output debugging */
+#ifndef LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG
+#define LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG    LWIP_DBG_OFF
+#endif
+
+/** LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS: 
+ * Currently, the linux kernel driver for 6lowpan sets/clears a bit in
+ * the address, depending on the BD address (either public or not).
+ * Might not be RFC7668 conform, so you may select to do that (=1) or
+ * not (=0) */
+#ifndef LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS
+#define LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS 1
+#endif
+
+
+#endif /* LWIP_HDR_LOWPAN6_OPTS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ccp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ccp.h
new file mode 100644
index 000000000..b2285228b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ccp.h
@@ -0,0 +1,164 @@
+/*
+ * ccp.h - Definitions for PPP Compression Control Protocol.
+ *
+ * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ccp.h,v 1.12 2004/11/04 10:02:26 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CCP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CCP_H
+#define CCP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CCP codes.
+ */
+
+#define CCP_CONFREQ	1
+#define CCP_CONFACK	2
+#define CCP_TERMREQ	5
+#define CCP_TERMACK	6
+#define CCP_RESETREQ	14
+#define CCP_RESETACK	15
+
+/*
+ * Max # bytes for a CCP option
+ */
+
+#define CCP_MAX_OPTION_LENGTH	32
+
+/*
+ * Parts of a CCP packet.
+ */
+
+#define CCP_CODE(dp)		((dp)[0])
+#define CCP_ID(dp)		((dp)[1])
+#define CCP_LENGTH(dp)		(((dp)[2] << 8) + (dp)[3])
+#define CCP_HDRLEN		4
+
+#define CCP_OPT_CODE(dp)	((dp)[0])
+#define CCP_OPT_LENGTH(dp)	((dp)[1])
+#define CCP_OPT_MINLEN		2
+
+#if BSDCOMPRESS_SUPPORT
+/*
+ * Definitions for BSD-Compress.
+ */
+
+#define CI_BSD_COMPRESS		21	/* config. option for BSD-Compress */
+#define CILEN_BSD_COMPRESS	3	/* length of config. option */
+
+/* Macros for handling the 3rd byte of the BSD-Compress config option. */
+#define BSD_NBITS(x)		((x) & 0x1F)	/* number of bits requested */
+#define BSD_VERSION(x)		((x) >> 5)	/* version of option format */
+#define BSD_CURRENT_VERSION	1		/* current version number */
+#define BSD_MAKE_OPT(v, n)	(((v) << 5) | (n))
+
+#define BSD_MIN_BITS		9	/* smallest code size supported */
+#define BSD_MAX_BITS		15	/* largest code size supported */
+#endif /* BSDCOMPRESS_SUPPORT */
+
+#if DEFLATE_SUPPORT
+/*
+ * Definitions for Deflate.
+ */
+
+#define CI_DEFLATE		26	/* config option for Deflate */
+#define CI_DEFLATE_DRAFT	24	/* value used in original draft RFC */
+#define CILEN_DEFLATE		4	/* length of its config option */
+
+#define DEFLATE_MIN_SIZE	9
+#define DEFLATE_MAX_SIZE	15
+#define DEFLATE_METHOD_VAL	8
+#define DEFLATE_SIZE(x)		(((x) >> 4) + 8)
+#define DEFLATE_METHOD(x)	((x) & 0x0F)
+#define DEFLATE_MAKE_OPT(w)	((((w) - 8) << 4) + DEFLATE_METHOD_VAL)
+#define DEFLATE_CHK_SEQUENCE	0
+#endif /* DEFLATE_SUPPORT */
+
+#if MPPE_SUPPORT
+/*
+ * Definitions for MPPE.
+ */
+
+#define CI_MPPE                18      /* config option for MPPE */
+#define CILEN_MPPE              6      /* length of config option */
+#endif /* MPPE_SUPPORT */
+
+#if PREDICTOR_SUPPORT
+/*
+ * Definitions for other, as yet unsupported, compression methods.
+ */
+
+#define CI_PREDICTOR_1		1	/* config option for Predictor-1 */
+#define CILEN_PREDICTOR_1	2	/* length of its config option */
+#define CI_PREDICTOR_2		2	/* config option for Predictor-2 */
+#define CILEN_PREDICTOR_2	2	/* length of its config option */
+#endif /* PREDICTOR_SUPPORT */
+
+typedef struct ccp_options {
+#if DEFLATE_SUPPORT
+    unsigned int deflate          :1; /* do Deflate? */
+    unsigned int deflate_correct  :1; /* use correct code for deflate? */
+    unsigned int deflate_draft    :1; /* use draft RFC code for deflate? */
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    unsigned int bsd_compress     :1; /* do BSD Compress? */
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+    unsigned int predictor_1      :1; /* do Predictor-1? */
+    unsigned int predictor_2      :1; /* do Predictor-2? */
+#endif /* PREDICTOR_SUPPORT */
+
+#if MPPE_SUPPORT
+    u8_t mppe;			/* MPPE bitfield */
+#endif /* MPPE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    u_short bsd_bits;		/* # bits/code for BSD Compress */
+#endif /* BSDCOMPRESS_SUPPORT */
+#if DEFLATE_SUPPORT
+    u_short deflate_size;	/* lg(window size) for Deflate */
+#endif /* DEFLATE_SUPPORT */
+    u8_t method;		/* code for chosen compression method */
+} ccp_options;
+
+extern const struct protent ccp_protent;
+
+void ccp_resetrequest(ppp_pcb *pcb);  /* Issue a reset-request. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CCP_H */
+#endif /* PPP_SUPPORT && CCP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap-md5.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap-md5.h
new file mode 100644
index 000000000..eb0269fe5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap-md5.h
@@ -0,0 +1,36 @@
+/*
+ * chap-md5.h - New CHAP/MD5 implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+extern const struct chap_digest_type md5_digest;
+
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap-new.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap-new.h
new file mode 100644
index 000000000..2d8cd9ca9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap-new.h
@@ -0,0 +1,200 @@
+/*
+ * chap-new.c - New CHAP implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CHAP packets begin with a standard header with code, id, len (2 bytes).
+ */
+#define CHAP_HDRLEN	4
+
+/*
+ * Values for the code field.
+ */
+#define CHAP_CHALLENGE	1
+#define CHAP_RESPONSE	2
+#define CHAP_SUCCESS	3
+#define CHAP_FAILURE	4
+
+/*
+ * CHAP digest codes.
+ */
+#define CHAP_MD5		5
+#if MSCHAP_SUPPORT
+#define CHAP_MICROSOFT		0x80
+#define CHAP_MICROSOFT_V2	0x81
+#endif /* MSCHAP_SUPPORT */
+
+/*
+ * Semi-arbitrary limits on challenge and response fields.
+ */
+#define MAX_CHALLENGE_LEN	64
+#define MAX_RESPONSE_LEN	64
+
+/*
+ * These limits apply to challenge and response packets we send.
+ * The +4 is the +1 that we actually need rounded up.
+ */
+#define CHAL_MAX_PKTLEN	(PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_CHALLENGE_LEN + MAXNAMELEN)
+#define RESP_MAX_PKTLEN	(PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_RESPONSE_LEN + MAXNAMELEN)
+
+/* bitmask of supported algorithms */
+#if MSCHAP_SUPPORT
+#define MDTYPE_MICROSOFT_V2	0x1
+#define MDTYPE_MICROSOFT	0x2
+#endif /* MSCHAP_SUPPORT */
+#define MDTYPE_MD5		0x4
+#define MDTYPE_NONE		0
+
+#if MSCHAP_SUPPORT
+/* Return the digest alg. ID for the most preferred digest type. */
+#define CHAP_DIGEST(mdtype) \
+    ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
+    ((mdtype) & MDTYPE_MICROSOFT_V2)? CHAP_MICROSOFT_V2: \
+    ((mdtype) & MDTYPE_MICROSOFT)? CHAP_MICROSOFT: \
+    0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_DIGEST(mdtype) \
+    ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
+    0
+#endif /* MSCHAP_SUPPORT */
+
+/* Return the bit flag (lsb set) for our most preferred digest type. */
+#define CHAP_MDTYPE(mdtype) ((mdtype) ^ ((mdtype) - 1)) & (mdtype)
+
+/* Return the bit flag for a given digest algorithm ID. */
+#if MSCHAP_SUPPORT
+#define CHAP_MDTYPE_D(digest) \
+    ((digest) == CHAP_MICROSOFT_V2)? MDTYPE_MICROSOFT_V2: \
+    ((digest) == CHAP_MICROSOFT)? MDTYPE_MICROSOFT: \
+    ((digest) == CHAP_MD5)? MDTYPE_MD5: \
+    0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_MDTYPE_D(digest) \
+    ((digest) == CHAP_MD5)? MDTYPE_MD5: \
+    0
+#endif /* MSCHAP_SUPPORT */
+
+/* Can we do the requested digest? */
+#if MSCHAP_SUPPORT
+#define CHAP_CANDIGEST(mdtype, digest) \
+    ((digest) == CHAP_MICROSOFT_V2)? (mdtype) & MDTYPE_MICROSOFT_V2: \
+    ((digest) == CHAP_MICROSOFT)? (mdtype) & MDTYPE_MICROSOFT: \
+    ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
+    0
+#else /* !MSCHAP_SUPPORT */
+#define CHAP_CANDIGEST(mdtype, digest) \
+    ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
+    0
+#endif /* MSCHAP_SUPPORT */
+
+/*
+ * The code for each digest type has to supply one of these.
+ */
+struct chap_digest_type {
+	int code;
+
+#if PPP_SERVER
+	/*
+	 * Note: challenge and response arguments below are formatted as
+	 * a length byte followed by the actual challenge/response data.
+	 */
+	void (*generate_challenge)(ppp_pcb *pcb, unsigned char *challenge);
+	int (*verify_response)(ppp_pcb *pcb, int id, const char *name,
+		const unsigned char *secret, int secret_len,
+		const unsigned char *challenge, const unsigned char *response,
+		char *message, int message_space);
+#endif /* PPP_SERVER */
+	void (*make_response)(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
+		const unsigned char *challenge, const char *secret, int secret_len,
+		unsigned char *priv);
+	int (*check_success)(ppp_pcb *pcb, unsigned char *pkt, int len, unsigned char *priv);
+	void (*handle_failure)(ppp_pcb *pcb, unsigned char *pkt, int len);
+};
+
+/*
+ * Each interface is described by chap structure.
+ */
+#if CHAP_SUPPORT
+typedef struct chap_client_state {
+	u8_t flags;
+	const char *name;
+	const struct chap_digest_type *digest;
+	unsigned char priv[64];		/* private area for digest's use */
+} chap_client_state;
+
+#if PPP_SERVER
+typedef struct chap_server_state {
+	u8_t flags;
+	u8_t id;
+	const char *name;
+	const struct chap_digest_type *digest;
+	int challenge_xmits;
+	int challenge_pktlen;
+	unsigned char challenge[CHAL_MAX_PKTLEN];
+} chap_server_state;
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPORT */
+
+#if 0 /* UNUSED */
+/* Hook for a plugin to validate CHAP challenge */
+extern int (*chap_verify_hook)(char *name, char *ourname, int id,
+			const struct chap_digest_type *digest,
+			unsigned char *challenge, unsigned char *response,
+			char *message, int message_space);
+#endif /* UNUSED */
+
+#if PPP_SERVER
+/* Called by authentication code to start authenticating the peer. */
+extern void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
+#endif /* PPP_SERVER */
+
+/* Called by auth. code to start authenticating us to the peer. */
+extern void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
+
+/* Represents the CHAP protocol to the main pppd code */
+extern const struct protent chap_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CHAP_H */
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap_ms.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap_ms.h
new file mode 100644
index 000000000..079529115
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/chap_ms.h
@@ -0,0 +1,44 @@
+/*
+ * chap_ms.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: chap_ms.h,v 1.13 2004/11/15 22:13:26 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MSCHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef CHAPMS_INCLUDE
+#define CHAPMS_INCLUDE
+
+extern const struct chap_digest_type chapms_digest;
+extern const struct chap_digest_type chapms2_digest;
+
+#endif /* CHAPMS_INCLUDE */
+
+#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/eap.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/eap.h
new file mode 100644
index 000000000..3ee9aaf81
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/eap.h
@@ -0,0 +1,169 @@
+/*
+ * eap.h - Extensible Authentication Protocol for PPP (RFC 2284)
+ *
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ *
+ * Non-exclusive rights to redistribute, modify, translate, and use
+ * this software in source and binary forms, in whole or in part, is
+ * hereby granted, provided that the above copyright notice is
+ * duplicated in any source form, and that neither the name of the
+ * copyright holder nor the author is used to endorse or promote
+ * products derived from this software.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Original version by James Carlson
+ *
+ * $Id: eap.h,v 1.2 2003/06/11 23:56:26 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && EAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_EAP_H
+#define	PPP_EAP_H
+
+#include "ppp.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define	EAP_HEADERLEN	4
+
+
+/* EAP message codes. */
+#define	EAP_REQUEST	1
+#define	EAP_RESPONSE	2
+#define	EAP_SUCCESS	3
+#define	EAP_FAILURE	4
+
+/* EAP types */
+#define	EAPT_IDENTITY		1
+#define	EAPT_NOTIFICATION	2
+#define	EAPT_NAK		3	/* (response only) */
+#define	EAPT_MD5CHAP		4
+#define	EAPT_OTP		5	/* One-Time Password; RFC 1938 */
+#define	EAPT_TOKEN		6	/* Generic Token Card */
+/* 7 and 8 are unassigned. */
+#define	EAPT_RSA		9	/* RSA Public Key Authentication */
+#define	EAPT_DSS		10	/* DSS Unilateral */
+#define	EAPT_KEA		11	/* KEA */
+#define	EAPT_KEA_VALIDATE	12	/* KEA-VALIDATE	*/
+#define	EAPT_TLS		13	/* EAP-TLS */
+#define	EAPT_DEFENDER		14	/* Defender Token (AXENT) */
+#define	EAPT_W2K		15	/* Windows 2000 EAP */
+#define	EAPT_ARCOT		16	/* Arcot Systems */
+#define	EAPT_CISCOWIRELESS	17	/* Cisco Wireless */
+#define	EAPT_NOKIACARD		18	/* Nokia IP smart card */
+#define	EAPT_SRP		19	/* Secure Remote Password */
+/* 20 is deprecated */
+
+/* EAP SRP-SHA1 Subtypes */
+#define	EAPSRP_CHALLENGE	1	/* Request 1 - Challenge */
+#define	EAPSRP_CKEY		1	/* Response 1 - Client Key */
+#define	EAPSRP_SKEY		2	/* Request 2 - Server Key */
+#define	EAPSRP_CVALIDATOR	2	/* Response 2 - Client Validator */
+#define	EAPSRP_SVALIDATOR	3	/* Request 3 - Server Validator */
+#define	EAPSRP_ACK		3	/* Response 3 - final ack */
+#define	EAPSRP_LWRECHALLENGE	4	/* Req/resp 4 - Lightweight rechal */
+
+#define	SRPVAL_EBIT	0x00000001	/* Use shared key for ECP */
+
+#define	SRP_PSEUDO_ID	"pseudo_"
+#define	SRP_PSEUDO_LEN	7
+
+#define MD5_SIGNATURE_SIZE	16
+#define EAP_MIN_CHALLENGE_LENGTH	17
+#define EAP_MAX_CHALLENGE_LENGTH	24
+#define EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH     3   /* 2^3-1 = 7, 17+7 = 24 */
+
+#define	EAP_STATES	\
+	"Initial", "Pending", "Closed", "Listen", "Identify", \
+	"SRP1", "SRP2", "SRP3", "MD5Chall", "Open", "SRP4", "BadAuth"
+
+#define	eap_client_active(pcb)	((pcb)->eap.es_client.ea_state == eapListen)
+#if PPP_SERVER
+#define	eap_server_active(pcb)	\
+	((pcb)->eap.es_server.ea_state >= eapIdentify && \
+	 (pcb)->eap.es_server.ea_state <= eapMD5Chall)
+#endif /* PPP_SERVER */
+
+/*
+ * Complete EAP state for one PPP session.
+ */
+enum eap_state_code {
+	eapInitial = 0,	/* No EAP authentication yet requested */
+	eapPending,	/* Waiting for LCP (no timer) */
+	eapClosed,	/* Authentication not in use */
+	eapListen,	/* Client ready (and timer running) */
+	eapIdentify,	/* EAP Identify sent */
+	eapSRP1,	/* Sent EAP SRP-SHA1 Subtype 1 */
+	eapSRP2,	/* Sent EAP SRP-SHA1 Subtype 2 */
+	eapSRP3,	/* Sent EAP SRP-SHA1 Subtype 3 */
+	eapMD5Chall,	/* Sent MD5-Challenge */
+	eapOpen,	/* Completed authentication */
+	eapSRP4,	/* Sent EAP SRP-SHA1 Subtype 4 */
+	eapBadAuth	/* Failed authentication */
+};
+
+struct eap_auth {
+	const char *ea_name;	/* Our name */
+	char ea_peer[MAXNAMELEN +1];	/* Peer's name */
+	void *ea_session;	/* Authentication library linkage */
+	u_char *ea_skey;	/* Shared encryption key */
+	u_short ea_namelen;	/* Length of our name */
+	u_short ea_peerlen;	/* Length of peer's name */
+	enum eap_state_code ea_state;
+	u_char ea_id;		/* Current id */
+	u_char ea_requests;	/* Number of Requests sent/received */
+	u_char ea_responses;	/* Number of Responses */
+	u_char ea_type;		/* One of EAPT_* */
+	u32_t ea_keyflags;	/* SRP shared key usage flags */
+};
+
+#ifndef EAP_MAX_CHALLENGE_LENGTH
+#define EAP_MAX_CHALLENGE_LENGTH	24
+#endif
+typedef struct eap_state {
+	struct eap_auth es_client;	/* Client (authenticatee) data */
+#if PPP_SERVER
+	struct eap_auth es_server;	/* Server (authenticator) data */
+#endif /* PPP_SERVER */
+	int es_savedtime;		/* Saved timeout */
+	int es_rechallenge;		/* EAP rechallenge interval */
+	int es_lwrechallenge;		/* SRP lightweight rechallenge inter */
+	u8_t es_usepseudo;		/* Use SRP Pseudonym if offered one */
+	int es_usedpseudo;		/* Set if we already sent PN */
+	int es_challen;			/* Length of challenge string */
+	u_char es_challenge[EAP_MAX_CHALLENGE_LENGTH];
+} eap_state;
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to ppp_opts.h */
+#define	EAP_DEFTIMEOUT		3	/* Timeout (seconds) for rexmit */
+#define	EAP_DEFTRANSMITS	10	/* max # times to transmit */
+#define	EAP_DEFREQTIME		20	/* Time to wait for peer request */
+#define	EAP_DEFALLOWREQ		20	/* max # times to accept requests */
+#endif /* moved to ppp_opts.h */
+
+void eap_authwithpeer(ppp_pcb *pcb, const char *localname);
+void eap_authpeer(ppp_pcb *pcb, const char *localname);
+
+extern const struct protent eap_protent;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* PPP_EAP_H */
+
+#endif /* PPP_SUPPORT && EAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ecp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ecp.h
new file mode 100644
index 000000000..d8808c3ab
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ecp.h
@@ -0,0 +1,62 @@
+/*
+ * ecp.h - Definitions for PPP Encryption Control Protocol.
+ *
+ * Copyright (c) 2002 Google, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ecp.h,v 1.2 2003/01/10 07:12:36 fcusack Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && ECP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef ECP_H
+#define ECP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct ecp_options {
+    bool required;		/* Is ECP required? */
+    unsigned enctype;		/* Encryption type */
+} ecp_options;
+
+extern fsm ecp_fsm[];
+extern ecp_options ecp_wantoptions[];
+extern ecp_options ecp_gotoptions[];
+extern ecp_options ecp_allowoptions[];
+extern ecp_options ecp_hisoptions[];
+
+extern const struct protent ecp_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ECP_H */
+#endif /* PPP_SUPPORT && ECP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/eui64.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/eui64.h
new file mode 100644
index 000000000..5adeb482a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/eui64.h
@@ -0,0 +1,102 @@
+/*
+ * eui64.h - EUI64 routines for IPv6CP.
+ *
+ * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Tommi Komulainen
+ *     <Tommi.Komulainen@iki.fi>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: eui64.h,v 1.6 2002/12/04 23:03:32 paulus Exp $
+*/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef EUI64_H
+#define EUI64_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * @todo:
+ *
+ * Maybe this should be done by processing struct in6_addr directly...
+ */
+typedef union
+{
+    u8_t e8[8];
+    u16_t e16[4];
+    u32_t e32[2];
+} eui64_t;
+
+#define eui64_iszero(e)		(((e).e32[0] | (e).e32[1]) == 0)
+#define eui64_equals(e, o)	(((e).e32[0] == (o).e32[0]) && \
+				((e).e32[1] == (o).e32[1]))
+#define eui64_zero(e)		(e).e32[0] = (e).e32[1] = 0;
+
+#define eui64_copy(s, d)	memcpy(&(d), &(s), sizeof(eui64_t))
+
+#define eui64_magic(e)		do {			\
+				(e).e32[0] = magic();	\
+				(e).e32[1] = magic();	\
+				(e).e8[0] &= ~2;	\
+				} while (0)
+#define eui64_magic_nz(x)	do {				\
+				eui64_magic(x);			\
+				} while (eui64_iszero(x))
+#define eui64_magic_ne(x, y)	do {				\
+				eui64_magic(x);			\
+				} while (eui64_equals(x, y))
+
+#define eui64_get(ll, cp)	do {				\
+				eui64_copy((*cp), (ll));	\
+				(cp) += sizeof(eui64_t);	\
+				} while (0)
+
+#define eui64_put(ll, cp)	do {				\
+				eui64_copy((ll), (*cp));	\
+				(cp) += sizeof(eui64_t);	\
+				} while (0)
+
+#define eui64_set32(e, l)	do {			\
+				(e).e32[0] = 0;		\
+				(e).e32[1] = lwip_htonl(l);	\
+				} while (0)
+#define eui64_setlo32(e, l)	eui64_set32(e, l)
+
+char *eui64_ntoa(eui64_t);	/* Returns ascii representation of id */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EUI64_H */
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/fsm.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/fsm.h
new file mode 100644
index 000000000..8dec700e0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/fsm.h
@@ -0,0 +1,182 @@
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: fsm.h,v 1.10 2004/11/13 02:28:15 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef FSM_H
+#define	FSM_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define HEADERLEN	4
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ		1	/* Configuration Request */
+#define CONFACK		2	/* Configuration Ack */
+#define CONFNAK		3	/* Configuration Nak */
+#define CONFREJ		4	/* Configuration Reject */
+#define TERMREQ		5	/* Termination Request */
+#define TERMACK		6	/* Termination Ack */
+#define CODEREJ		7	/* Code Reject */
+
+
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+    ppp_pcb *pcb;		/* PPP Interface */
+    const struct fsm_callbacks *callbacks;	/* Callback routines */
+    const char *term_reason;	/* Reason for closing protocol */
+    u8_t seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
+				  /* -- This is our only flag, we might use u_int :1 if we have more flags */
+    u16_t protocol;		/* Data Link Layer Protocol field value */
+    u8_t state;			/* State */
+    u8_t flags;			/* Contains option bits */
+    u8_t id;			/* Current id */
+    u8_t reqid;			/* Current request id */
+    u8_t retransmits;		/* Number of retransmissions left */
+    u8_t nakloops;		/* Number of nak loops since last ack */
+    u8_t rnakloops;		/* Number of naks received */
+    u8_t maxnakloops;		/* Maximum number of nak loops tolerated
+				   (necessary because IPCP require a custom large max nak loops value) */
+    u8_t term_reason_len;	/* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+    void (*resetci)		/* Reset our Configuration Information */
+		(fsm *);
+    int  (*cilen)		/* Length of our Configuration Information */
+		(fsm *);
+    void (*addci) 		/* Add our Configuration Information */
+		(fsm *, u_char *, int *);
+    int  (*ackci)		/* ACK our Configuration Information */
+		(fsm *, u_char *, int);
+    int  (*nakci)		/* NAK our Configuration Information */
+		(fsm *, u_char *, int, int);
+    int  (*rejci)		/* Reject our Configuration Information */
+		(fsm *, u_char *, int);
+    int  (*reqci)		/* Request peer's Configuration Information */
+		(fsm *, u_char *, int *, int);
+    void (*up)			/* Called when fsm reaches PPP_FSM_OPENED state */
+		(fsm *);
+    void (*down)		/* Called when fsm leaves PPP_FSM_OPENED state */
+		(fsm *);
+    void (*starting)		/* Called when we want the lower layer */
+		(fsm *);
+    void (*finished)		/* Called when we don't want the lower layer */
+		(fsm *);
+    void (*protreject)		/* Called when Protocol-Reject received */
+		(int);
+    void (*retransmit)		/* Retransmission is necessary */
+		(fsm *);
+    int  (*extcode)		/* Called when unknown code received */
+		(fsm *, int, int, u_char *, int);
+    const char *proto_name;	/* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*
+ * Link states.
+ */
+#define PPP_FSM_INITIAL		0	/* Down, hasn't been opened */
+#define PPP_FSM_STARTING	1	/* Down, been opened */
+#define PPP_FSM_CLOSED		2	/* Up, hasn't been opened */
+#define PPP_FSM_STOPPED		3	/* Open, waiting for down event */
+#define PPP_FSM_CLOSING		4	/* Terminating the connection, not open */
+#define PPP_FSM_STOPPING	5	/* Terminating, but open */
+#define PPP_FSM_REQSENT		6	/* We've sent a Config Request */
+#define PPP_FSM_ACKRCVD		7	/* We've received a Config Ack */
+#define PPP_FSM_ACKSENT		8	/* We've sent a Config Ack */
+#define PPP_FSM_OPENED		9	/* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE	1	/* Don't die if we don't get a response */
+#define OPT_RESTART	2	/* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT	4	/* Wait for peer to speak first */
+
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to ppp_opts.h */
+#define DEFTIMEOUT	3	/* Timeout time in seconds */
+#define DEFMAXTERMREQS	2	/* Maximum Terminate-Request transmissions */
+#define DEFMAXCONFREQS	10	/* Maximum Configure-Request transmissions */
+#define DEFMAXNAKLOOPS	5	/* Maximum number of nak loops */
+#endif /* moved to ppp_opts.h */
+
+
+/*
+ * Prototypes
+ */
+void fsm_init(fsm *f);
+void fsm_lowerup(fsm *f);
+void fsm_lowerdown(fsm *f);
+void fsm_open(fsm *f);
+void fsm_close(fsm *f, const char *reason);
+void fsm_input(fsm *f, u_char *inpacket, int l);
+void fsm_protreject(fsm *f);
+void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FSM_H */
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ipcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ipcp.h
new file mode 100644
index 000000000..32fdd1c64
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ipcp.h
@@ -0,0 +1,134 @@
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipcp.h,v 1.14 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef IPCP_H
+#define	IPCP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Options.
+ */
+#define CI_ADDRS	1	/* IP Addresses */
+#if VJ_SUPPORT
+#define CI_COMPRESSTYPE	2	/* Compression Type */
+#endif /* VJ_SUPPORT */
+#define	CI_ADDR		3
+
+#if LWIP_DNS
+#define CI_MS_DNS1      129	/* Primary DNS value */
+#define CI_MS_DNS2      131     /* Secondary DNS value */
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+#define CI_MS_WINS1     130     /* Primary WINS value */
+#define CI_MS_WINS2     132	/* Secondary WINS value */
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+#define MAX_STATES 16		/* from slcompress.h */
+
+#define IPCP_VJMODE_OLD 1	/* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
+                                /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d	/* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
+				/* compression option*/ 
+#endif /* VJ_SUPPORT */
+
+typedef struct ipcp_options {
+    unsigned int neg_addr               :1; /* Negotiate IP Address? */
+    unsigned int old_addrs              :1; /* Use old (IP-Addresses) option? */
+    unsigned int req_addr               :1; /* Ask peer to send IP address? */
+#if 0 /* UNUSED */
+    unsigned int default_route          :1; /* Assign default route through interface? */
+    unsigned int replace_default_route  :1; /* Replace default route through interface? */
+#endif /* UNUSED */
+#if 0 /* UNUSED - PROXY ARP */
+    unsigned int proxy_arp              :1; /* Make proxy ARP entry for peer? */
+#endif /* UNUSED - PROXY ARP */
+#if VJ_SUPPORT
+    unsigned int neg_vj                 :1; /* Van Jacobson Compression? */
+    unsigned int old_vj                 :1; /* use old (short) form of VJ option? */
+    unsigned int cflag                  :1;
+#endif /* VJ_SUPPORT */
+    unsigned int accept_local           :1; /* accept peer's value for ouraddr */
+    unsigned int accept_remote          :1; /* accept peer's value for hisaddr */
+#if LWIP_DNS
+    unsigned int req_dns1               :1; /* Ask peer to send primary DNS address? */
+    unsigned int req_dns2               :1; /* Ask peer to send secondary DNS address? */
+#endif /* LWIP_DNS */
+
+    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
+#if LWIP_DNS
+    u32_t dnsaddr[2];	/* Primary and secondary MS DNS entries */
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+    u32_t winsaddr[2];	/* Primary and secondary MS WINS entries */
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+    u16_t vj_protocol;		/* protocol value to use in VJ option */
+    u8_t  maxslotindex;		/* values for RFC1332 VJ compression neg. */
+#endif /* VJ_SUPPORT */
+} ipcp_options;
+
+#if 0 /* UNUSED, already defined by lwIP */
+char *ip_ntoa (u32_t);
+#endif /* UNUSED, already defined by lwIP */
+
+extern const struct protent ipcp_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPCP_H */
+#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ipv6cp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ipv6cp.h
new file mode 100644
index 000000000..909997386
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ipv6cp.h
@@ -0,0 +1,191 @@
+/*
+ * ipv6cp.h - PPP IPV6 Control Protocol.
+ *
+ * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Tommi Komulainen
+ *     <Tommi.Komulainen@iki.fi>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/*  Original version, based on RFC2023 :
+
+    Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt,
+    Alain.Durand@imag.fr, IMAG,
+    Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+    Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE,
+    Alain.Durand@imag.fr, IMAG,
+    Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+    Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt
+    Économique ayant pour membres BULL S.A. et l'INRIA).
+
+    Ce logiciel informatique est disponible aux conditions
+    usuelles dans la recherche, c'est-à-dire qu'il peut
+    être utilisé, copié, modifié, distribué à l'unique
+    condition que ce texte soit conservé afin que
+    l'origine de ce logiciel soit reconnue.
+
+    Le nom de l'Institut National de Recherche en Informatique
+    et en Automatique (INRIA), de l'IMAG, ou d'une personne morale
+    ou physique ayant participé à l'élaboration de ce logiciel ne peut
+    être utilisé sans son accord préalable explicite.
+
+    Ce logiciel est fourni tel quel sans aucune garantie,
+    support ou responsabilité d'aucune sorte.
+    Ce logiciel est dérivé de sources d'origine
+    "University of California at Berkeley" et
+    "Digital Equipment Corporation" couvertes par des copyrights.
+
+    L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG)
+    est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National
+    Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant
+    sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR).
+
+    This work has been done in the context of GIE DYADE (joint R & D venture
+    between BULL S.A. and INRIA).
+
+    This software is available with usual "research" terms
+    with the aim of retain credits of the software. 
+    Permission to use, copy, modify and distribute this software for any
+    purpose and without fee is hereby granted, provided that the above
+    copyright notice and this permission notice appear in all copies,
+    and the name of INRIA, IMAG, or any contributor not be used in advertising
+    or publicity pertaining to this material without the prior explicit
+    permission. The software is provided "as is" without any
+    warranties, support or liabilities of any kind.
+    This software is derived from source code from
+    "University of California at Berkeley" and
+    "Digital Equipment Corporation" protected by copyrights.
+
+    Grenoble's Institute of Computer Science and Applied Mathematics (IMAG)
+    is a federation of seven research units funded by the CNRS, National
+    Polytechnic Institute of Grenoble and University Joseph Fourier.
+    The research unit in Software, Systems, Networks (LSR) is member of IMAG.
+*/
+
+/*
+ * Derived from :
+ *
+ *
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipv6cp.h,v 1.7 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef IPV6CP_H
+#define	IPV6CP_H
+
+#include "eui64.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Options.
+ */
+#define CI_IFACEID	1	/* Interface Identifier */
+#ifdef IPV6CP_COMP
+#define CI_COMPRESSTYPE	2	/* Compression Type     */
+#endif /* IPV6CP_COMP */
+
+/* No compression types yet defined.
+ *#define IPV6CP_COMP	0x004f
+ */
+typedef struct ipv6cp_options {
+    unsigned int neg_ifaceid    :1;  /* Negotiate interface identifier? */
+    unsigned int req_ifaceid    :1;  /* Ask peer to send interface identifier? */
+    unsigned int accept_local   :1;  /* accept peer's value for iface id? */
+    unsigned int opt_local      :1;  /* ourtoken set by option */
+    unsigned int opt_remote     :1;  /* histoken set by option */
+    unsigned int use_ip         :1;  /* use IP as interface identifier */
+#if 0
+    unsigned int use_persistent :1;  /* use uniquely persistent value for address */
+#endif
+#ifdef IPV6CP_COMP
+    unsigned int neg_vj         :1;  /* Van Jacobson Compression? */
+#endif /* IPV6CP_COMP */
+
+#ifdef IPV6CP_COMP
+    u_short vj_protocol;        /* protocol value to use in VJ option */
+#endif /* IPV6CP_COMP */
+    eui64_t ourid, hisid;       /* Interface identifiers */
+} ipv6cp_options;
+
+extern const struct protent ipv6cp_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IPV6CP_H */
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/lcp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/lcp.h
new file mode 100644
index 000000000..18ad1cb23
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/lcp.h
@@ -0,0 +1,179 @@
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: lcp.h,v 1.20 2004/11/14 22:53:42 carlsonj Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef LCP_H
+#define	LCP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Options.
+ */
+#define CI_VENDOR	0	/* Vendor Specific */
+#define CI_MRU		1	/* Maximum Receive Unit */
+#define CI_ASYNCMAP	2	/* Async Control Character Map */
+#define CI_AUTHTYPE	3	/* Authentication Type */
+#define CI_QUALITY	4	/* Quality Protocol */
+#define CI_MAGICNUMBER	5	/* Magic Number */
+#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
+#define CI_FCSALTERN	9	/* FCS-Alternatives */
+#define CI_SDP		10	/* Self-Describing-Pad */
+#define CI_NUMBERED	11	/* Numbered-Mode */
+#define CI_CALLBACK	13	/* callback */
+#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
+#define CI_SSNHF	18	/* short sequence numbers for multilink */
+#define CI_EPDISC	19	/* endpoint discriminator */
+#define CI_MPPLUS	22	/* Multi-Link-Plus-Procedure */
+#define CI_LDISC	23	/* Link-Discriminator */
+#define CI_LCPAUTH	24	/* LCP Authentication */
+#define CI_COBS		25	/* Consistent Overhead Byte Stuffing */
+#define CI_PREFELIS	26	/* Prefix Elision */
+#define CI_MPHDRFMT	27	/* MP Header Format */
+#define CI_I18N		28	/* Internationalization */
+#define CI_SDL		29	/* Simple Data Link */
+
+/*
+ * LCP-specific packet types (code numbers).
+ */
+#define PROTREJ		8	/* Protocol Reject */
+#define ECHOREQ		9	/* Echo Request */
+#define ECHOREP		10	/* Echo Reply */
+#define DISCREQ		11	/* Discard Request */
+#define IDENTIF		12	/* Identification */
+#define TIMEREM		13	/* Time Remaining */
+
+/* Value used as data for CI_CALLBACK option */
+#define CBCP_OPT	6	/* Use callback control protocol */
+
+#if 0 /* moved to ppp_opts.h */
+#define DEFMRU	1500		/* Try for this */
+#define MINMRU	128		/* No MRUs below this */
+#define MAXMRU	16384		/* Normally limit MRU to this */
+#endif /* moved to ppp_opts.h */
+
+/* An endpoint discriminator, used with multilink. */
+#define MAX_ENDP_LEN	20	/* maximum length of discriminator value */
+struct epdisc {
+    unsigned char	class_; /* -- The word "class" is reserved in C++. */
+    unsigned char	length;
+    unsigned char	value[MAX_ENDP_LEN];
+};
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    unsigned int passive           :1; /* Don't die if we don't get a response */
+    unsigned int silent            :1; /* Wait for the other end to start first */
+#if 0 /* UNUSED */
+    unsigned int restart           :1; /* Restart vs. exit after close */
+#endif /* UNUSED */
+    unsigned int neg_mru           :1; /* Negotiate the MRU? */
+    unsigned int neg_asyncmap      :1; /* Negotiate the async map? */
+#if PAP_SUPPORT
+    unsigned int neg_upap          :1; /* Ask for UPAP authentication? */
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+    unsigned int neg_chap          :1; /* Ask for CHAP authentication? */
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+    unsigned int neg_eap           :1; /* Ask for EAP authentication? */
+#endif /* EAP_SUPPORT */
+    unsigned int neg_magicnumber   :1; /* Ask for magic number? */
+    unsigned int neg_pcompression  :1; /* HDLC Protocol Field Compression? */
+    unsigned int neg_accompression :1; /* HDLC Address/Control Field Compression? */
+#if LQR_SUPPORT
+    unsigned int neg_lqr           :1; /* Negotiate use of Link Quality Reports */
+#endif /* LQR_SUPPORT */
+    unsigned int neg_cbcp          :1; /* Negotiate use of CBCP */
+#ifdef HAVE_MULTILINK
+    unsigned int neg_mrru          :1; /* negotiate multilink MRRU */
+#endif /* HAVE_MULTILINK */
+    unsigned int neg_ssnhf         :1; /* negotiate short sequence numbers */
+    unsigned int neg_endpoint      :1; /* negotiate endpoint discriminator */
+
+    u16_t mru;			/* Value of MRU */
+#ifdef HAVE_MULTILINK
+    u16_t mrru;			/* Value of MRRU, and multilink enable */
+#endif /* MULTILINK */
+#if CHAP_SUPPORT
+    u8_t chap_mdtype;		/* which MD types (hashing algorithm) */
+#endif /* CHAP_SUPPORT */
+    u32_t asyncmap;		/* Value of async map */
+    u32_t magicnumber;
+    u8_t  numloops;		/* Number of loops during magic number neg. */
+#if LQR_SUPPORT
+    u32_t lqr_period;	/* Reporting period for LQR 1/100ths second */
+#endif /* LQR_SUPPORT */
+    struct epdisc endpoint;	/* endpoint discriminator */
+} lcp_options;
+
+void lcp_open(ppp_pcb *pcb);
+void lcp_close(ppp_pcb *pcb, const char *reason);
+void lcp_lowerup(ppp_pcb *pcb);
+void lcp_lowerdown(ppp_pcb *pcb);
+void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len);    /* send protocol reject */
+
+extern const struct protent lcp_protent;
+
+#if 0 /* moved to ppp_opts.h */
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL	10
+#endif /* moved to ppp_opts.h */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LCP_H */
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/magic.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/magic.h
new file mode 100644
index 000000000..a165e18fa
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/magic.h
@@ -0,0 +1,130 @@
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: magic.h,v 1.5 2003/06/11 23:56:26 paulus Exp $
+ */
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/*
+ * Initialize the random number generator.
+ */
+void magic_init(void);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+void magic_randomize(void);
+
+/*
+ * Return a new random number.
+ */
+u32_t magic(void);	/* Returns the next magic number */
+
+/*
+ * Fill buffer with random bytes
+ *
+ * Use the random pool to generate random data.  This degrades to pseudo
+ * random when used faster than randomness is supplied using magic_churnrand().
+ * Thus it's important to make sure that the results of this are not
+ * published directly because one could predict the next result to at
+ * least some degree.  Also, it's important to get a good seed before
+ * the first use.
+ */
+void magic_random_bytes(unsigned char *buf, u32_t buf_len);
+
+/*
+ * Return a new random number between 0 and (2^pow)-1 included.
+ */
+u32_t magic_pow(u8_t pow);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MAGIC_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/mppe.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/mppe.h
new file mode 100644
index 000000000..5de112847
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/mppe.h
@@ -0,0 +1,181 @@
+/*
+ * mppe.h - Definitions for MPPE
+ *
+ * Copyright (c) 2008 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MPPE_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef MPPE_H
+#define MPPE_H
+
+#include "netif/ppp/pppcrypt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MPPE_PAD		4	/* MPPE growth per frame */
+#define MPPE_MAX_KEY_LEN	16	/* largest key length (128-bit) */
+
+/* option bits for ccp_options.mppe */
+#define MPPE_OPT_40		0x01	/* 40 bit */
+#define MPPE_OPT_128		0x02	/* 128 bit */
+#define MPPE_OPT_STATEFUL	0x04	/* stateful mode */
+/* unsupported opts */
+#define MPPE_OPT_56		0x08	/* 56 bit */
+#define MPPE_OPT_MPPC		0x10	/* MPPC compression */
+#define MPPE_OPT_D		0x20	/* Unknown */
+#define MPPE_OPT_UNSUPPORTED (MPPE_OPT_56|MPPE_OPT_MPPC|MPPE_OPT_D)
+#define MPPE_OPT_UNKNOWN	0x40	/* Bits !defined in RFC 3078 were set */
+
+/*
+ * This is not nice ... the alternative is a bitfield struct though.
+ * And unfortunately, we cannot share the same bits for the option
+ * names above since C and H are the same bit.  We could do a u_int32
+ * but then we have to do a lwip_htonl() all the time and/or we still need
+ * to know which octet is which.
+ */
+#define MPPE_C_BIT		0x01	/* MPPC */
+#define MPPE_D_BIT		0x10	/* Obsolete, usage unknown */
+#define MPPE_L_BIT		0x20	/* 40-bit */
+#define MPPE_S_BIT		0x40	/* 128-bit */
+#define MPPE_M_BIT		0x80	/* 56-bit, not supported */
+#define MPPE_H_BIT		0x01	/* Stateless (in a different byte) */
+
+/* Does not include H bit; used for least significant octet only. */
+#define MPPE_ALL_BITS (MPPE_D_BIT|MPPE_L_BIT|MPPE_S_BIT|MPPE_M_BIT|MPPE_H_BIT)
+
+/* Build a CI from mppe opts (see RFC 3078) */
+#define MPPE_OPTS_TO_CI(opts, ci)		\
+    do {					\
+	u_char *ptr = ci; /* u_char[4] */	\
+						\
+	/* H bit */				\
+	if (opts & MPPE_OPT_STATEFUL)		\
+	    *ptr++ = 0x0;			\
+	else					\
+	    *ptr++ = MPPE_H_BIT;		\
+	*ptr++ = 0;				\
+	*ptr++ = 0;				\
+						\
+	/* S,L bits */				\
+	*ptr = 0;				\
+	if (opts & MPPE_OPT_128)		\
+	    *ptr |= MPPE_S_BIT;			\
+	if (opts & MPPE_OPT_40)			\
+	    *ptr |= MPPE_L_BIT;			\
+	/* M,D,C bits not supported */		\
+    } while (/* CONSTCOND */ 0)
+
+/* The reverse of the above */
+#define MPPE_CI_TO_OPTS(ci, opts)		\
+    do {					\
+	const u_char *ptr = ci; /* u_char[4] */	\
+						\
+	opts = 0;				\
+						\
+	/* H bit */				\
+	if (!(ptr[0] & MPPE_H_BIT))		\
+	    opts |= MPPE_OPT_STATEFUL;		\
+						\
+	/* S,L bits */				\
+	if (ptr[3] & MPPE_S_BIT)		\
+	    opts |= MPPE_OPT_128;		\
+	if (ptr[3] & MPPE_L_BIT)		\
+	    opts |= MPPE_OPT_40;		\
+						\
+	/* M,D,C bits */			\
+	if (ptr[3] & MPPE_M_BIT)		\
+	    opts |= MPPE_OPT_56;		\
+	if (ptr[3] & MPPE_D_BIT)		\
+	    opts |= MPPE_OPT_D;			\
+	if (ptr[3] & MPPE_C_BIT)		\
+	    opts |= MPPE_OPT_MPPC;		\
+						\
+	/* Other bits */			\
+	if (ptr[0] & ~MPPE_H_BIT)		\
+	    opts |= MPPE_OPT_UNKNOWN;		\
+	if (ptr[1] || ptr[2])			\
+	    opts |= MPPE_OPT_UNKNOWN;		\
+	if (ptr[3] & ~MPPE_ALL_BITS)		\
+	    opts |= MPPE_OPT_UNKNOWN;		\
+    } while (/* CONSTCOND */ 0)
+
+/* Shared MPPE padding between MSCHAP and MPPE */
+#define SHA1_PAD_SIZE 40
+
+static const u8_t mppe_sha1_pad1[SHA1_PAD_SIZE] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+static const u8_t mppe_sha1_pad2[SHA1_PAD_SIZE] = {
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
+  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2
+};
+
+/*
+ * State for an MPPE (de)compressor.
+ */
+typedef struct ppp_mppe_state {
+	lwip_arc4_context arc4;
+	u8_t master_key[MPPE_MAX_KEY_LEN];
+	u8_t session_key[MPPE_MAX_KEY_LEN];
+	u8_t keylen;                /* key length in bytes */
+	/* NB: 128-bit == 16, 40-bit == 8!
+	 * If we want to support 56-bit, the unit has to change to bits
+	 */
+	u8_t bits;                  /* MPPE control bits */
+	u16_t ccount;               /* 12-bit coherency count (seqno)  */
+	u16_t sanity_errors;        /* take down LCP if too many */
+	unsigned int stateful  :1;  /* stateful mode flag */
+	unsigned int discard   :1;  /* stateful mode packet loss flag */
+} ppp_mppe_state;
+
+void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key);
+void mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options);
+void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
+err_t mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol);
+void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
+err_t mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MPPE_H */
+#endif /* PPP_SUPPORT && MPPE_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/arc4.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/arc4.h
new file mode 100644
index 000000000..4af724cd9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/arc4.h
@@ -0,0 +1,81 @@
+/**
+ * \file arc4.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_ARC4
+
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4_H
+#define LWIP_INCLUDED_POLARSSL_ARC4_H
+
+/**
+ * \brief          ARC4 context structure
+ */
+typedef struct
+{
+    int x;                      /*!< permutation index */
+    int y;                      /*!< permutation index */
+    unsigned char m[256];       /*!< permutation table */
+}
+arc4_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          ARC4 key schedule
+ *
+ * \param ctx      ARC4 context to be initialized
+ * \param key      the secret key
+ * \param keylen   length of the key
+ */
+void arc4_setup( arc4_context *ctx, unsigned char *key, int keylen );
+
+/**
+ * \brief          ARC4 cipher function
+ *
+ * \param ctx      ARC4 context
+ * \param buf      buffer to be processed
+ * \param buflen   amount of data in buf
+ */
+void arc4_crypt( arc4_context *ctx, unsigned char *buf, int buflen );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/des.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/des.h
new file mode 100644
index 000000000..e893890ed
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/des.h
@@ -0,0 +1,92 @@
+/**
+ * \file des.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_DES
+
+#ifndef LWIP_INCLUDED_POLARSSL_DES_H
+#define LWIP_INCLUDED_POLARSSL_DES_H
+
+#define DES_ENCRYPT     1
+#define DES_DECRYPT     0
+
+/**
+ * \brief          DES context structure
+ */
+typedef struct
+{
+    int mode;                   /*!<  encrypt/decrypt   */
+    unsigned long sk[32];       /*!<  DES subkeys       */
+}
+des_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          DES key schedule (56-bit, encryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ */
+void des_setkey_enc( des_context *ctx, unsigned char key[8] );
+
+/**
+ * \brief          DES key schedule (56-bit, decryption)
+ *
+ * \param ctx      DES context to be initialized
+ * \param key      8-byte secret key
+ */
+void des_setkey_dec( des_context *ctx, unsigned char key[8] );
+
+/**
+ * \brief          DES-ECB block encryption/decryption
+ *
+ * \param ctx      DES context
+ * \param input    64-bit input block
+ * \param output   64-bit output block
+ */
+void des_crypt_ecb( des_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_DES_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/md4.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/md4.h
new file mode 100644
index 000000000..570445687
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/md4.h
@@ -0,0 +1,97 @@
+/**
+ * \file md4.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_MD4
+
+#ifndef LWIP_INCLUDED_POLARSSL_MD4_H
+#define LWIP_INCLUDED_POLARSSL_MD4_H
+
+/**
+ * \brief          MD4 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];     /*!< number of bytes processed  */
+    unsigned long state[4];     /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+md4_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD4 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void md4_starts( md4_context *ctx );
+
+/**
+ * \brief          MD4 process buffer
+ *
+ * \param ctx      MD4 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void md4_update( md4_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief          MD4 final digest
+ *
+ * \param ctx      MD4 context
+ * \param output   MD4 checksum result
+ */
+void md4_finish( md4_context *ctx, unsigned char output[16] );
+
+/**
+ * \brief          Output = MD4( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD4 checksum result
+ */
+void md4( unsigned char *input, int ilen, unsigned char output[16] );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD4_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/md5.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/md5.h
new file mode 100644
index 000000000..124401189
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/md5.h
@@ -0,0 +1,96 @@
+/**
+ * \file md5.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_MD5
+
+#ifndef LWIP_INCLUDED_POLARSSL_MD5_H
+#define LWIP_INCLUDED_POLARSSL_MD5_H
+
+/**
+ * \brief          MD5 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];     /*!< number of bytes processed  */
+    unsigned long state[4];     /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+md5_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          MD5 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void md5_starts( md5_context *ctx );
+
+/**
+ * \brief          MD5 process buffer
+ *
+ * \param ctx      MD5 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void md5_update( md5_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief          MD5 final digest
+ *
+ * \param ctx      MD5 context
+ * \param output   MD5 checksum result
+ */
+void md5_finish( md5_context *ctx, unsigned char output[16] );
+
+/**
+ * \brief          Output = MD5( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   MD5 checksum result
+ */
+void md5( unsigned char *input, int ilen, unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD5_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/sha1.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/sha1.h
new file mode 100644
index 000000000..a4c53e07c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/polarssl/sha1.h
@@ -0,0 +1,96 @@
+/**
+ * \file sha1.h
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if LWIP_INCLUDED_POLARSSL_SHA1
+
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1_H
+#define LWIP_INCLUDED_POLARSSL_SHA1_H
+
+/**
+ * \brief          SHA-1 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];     /*!< number of bytes processed  */
+    unsigned long state[5];     /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+sha1_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void sha1_starts( sha1_context *ctx );
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void sha1_update( sha1_context *ctx, const unsigned char *input, int ilen );
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] );
+
+/**
+ * \brief          Output = SHA-1( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ * \param output   SHA-1 checksum result
+ */
+void sha1( unsigned char *input, int ilen, unsigned char output[20] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1_H */
+
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp.h
new file mode 100644
index 000000000..3d73c3657
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp.h
@@ -0,0 +1,698 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/netif.h"
+#include "lwip/sys.h"
+#include "lwip/timeouts.h"
+#if PPP_IPV6_SUPPORT
+#include "lwip/ip6_addr.h"
+#endif /* PPP_IPV6_SUPPORT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Disable non-working or rarely used PPP feature, so rarely that we don't want to bloat ppp_opts.h with them */
+#ifndef PPP_OPTIONS
+#define PPP_OPTIONS         0
+#endif
+
+#ifndef PPP_NOTIFY
+#define PPP_NOTIFY          0
+#endif
+
+#ifndef PPP_REMOTENAME
+#define PPP_REMOTENAME      0
+#endif
+
+#ifndef PPP_IDLETIMELIMIT
+#define PPP_IDLETIMELIMIT   0
+#endif
+
+#ifndef PPP_LCP_ADAPTIVE
+#define PPP_LCP_ADAPTIVE    0
+#endif
+
+#ifndef PPP_MAXCONNECT
+#define PPP_MAXCONNECT      0
+#endif
+
+#ifndef PPP_ALLOWED_ADDRS
+#define PPP_ALLOWED_ADDRS   0
+#endif
+
+#ifndef PPP_PROTOCOLNAME
+#define PPP_PROTOCOLNAME    0
+#endif
+
+#ifndef PPP_STATS_SUPPORT
+#define PPP_STATS_SUPPORT   0
+#endif
+
+#ifndef DEFLATE_SUPPORT
+#define DEFLATE_SUPPORT     0
+#endif
+
+#ifndef BSDCOMPRESS_SUPPORT
+#define BSDCOMPRESS_SUPPORT 0
+#endif
+
+#ifndef PREDICTOR_SUPPORT
+#define PREDICTOR_SUPPORT   0
+#endif
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN	4	/* octets for standard ppp header */
+#define PPP_FCSLEN	2	/* octets for FCS */
+
+/*
+ * Values for phase.
+ */
+#define PPP_PHASE_DEAD          0
+#define PPP_PHASE_MASTER        1
+#define PPP_PHASE_HOLDOFF       2
+#define PPP_PHASE_INITIALIZE    3
+#define PPP_PHASE_SERIALCONN    4
+#define PPP_PHASE_DORMANT       5
+#define PPP_PHASE_ESTABLISH     6
+#define PPP_PHASE_AUTHENTICATE  7
+#define PPP_PHASE_CALLBACK      8
+#define PPP_PHASE_NETWORK       9
+#define PPP_PHASE_RUNNING       10
+#define PPP_PHASE_TERMINATE     11
+#define PPP_PHASE_DISCONNECT    12
+
+/* Error codes. */
+#define PPPERR_NONE         0  /* No error. */
+#define PPPERR_PARAM        1  /* Invalid parameter. */
+#define PPPERR_OPEN         2  /* Unable to open PPP session. */
+#define PPPERR_DEVICE       3  /* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC        4  /* Unable to allocate resources. */
+#define PPPERR_USER         5  /* User interrupt. */
+#define PPPERR_CONNECT      6  /* Connection lost. */
+#define PPPERR_AUTHFAIL     7  /* Failed authentication challenge. */
+#define PPPERR_PROTOCOL     8  /* Failed to meet protocol. */
+#define PPPERR_PEERDEAD     9  /* Connection timeout */
+#define PPPERR_IDLETIMEOUT  10 /* Idle Timeout */
+#define PPPERR_CONNECTTIME  11 /* Max connect time reached */
+#define PPPERR_LOOPBACK     12 /* Loopback detected */
+
+/* Whether auth support is enabled at all */
+#define PPP_AUTH_SUPPORT (PAP_SUPPORT || CHAP_SUPPORT || EAP_SUPPORT)
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Other headers require ppp_pcb definition for prototypes, but ppp_pcb
+ * require some structure definition from other headers as well, we are
+ * fixing the dependency loop here by declaring the ppp_pcb type then
+ * by including headers containing necessary struct definition for ppp_pcb
+ */
+typedef struct ppp_pcb_s ppp_pcb;
+
+/* Type definitions for BSD code. */
+#ifndef __u_char_defined
+typedef unsigned long  u_long;
+typedef unsigned int   u_int;
+typedef unsigned short u_short;
+typedef unsigned char  u_char;
+#endif
+
+#include "fsm.h"
+#include "lcp.h"
+#if CCP_SUPPORT
+#include "ccp.h"
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+#include "mppe.h"
+#endif /* MPPE_SUPPORT */
+#if PPP_IPV4_SUPPORT
+#include "ipcp.h"
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#include "ipv6cp.h"
+#endif /* PPP_IPV6_SUPPORT */
+#if PAP_SUPPORT
+#include "upap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "chap-new.h"
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#include "eap.h"
+#endif /* EAP_SUPPORT */
+#if VJ_SUPPORT
+#include "vj.h"
+#endif /* VJ_SUPPORT */
+
+/* Link status callback function prototype */
+typedef void (*ppp_link_status_cb_fn)(ppp_pcb *pcb, int err_code, void *ctx);
+
+/*
+ * PPP configuration.
+ */
+typedef struct ppp_settings_s {
+
+#if PPP_SERVER && PPP_AUTH_SUPPORT
+  unsigned int  auth_required       :1;      /* Peer is required to authenticate */
+  unsigned int  null_login          :1;      /* Username of "" and a password of "" are acceptable */
+#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */
+#if PPP_REMOTENAME
+  unsigned int  explicit_remote     :1;      /* remote_name specified with remotename opt */
+#endif /* PPP_REMOTENAME */
+#if PAP_SUPPORT
+  unsigned int  refuse_pap          :1;      /* Don't proceed auth. with PAP */
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  unsigned int  refuse_chap         :1;      /* Don't proceed auth. with CHAP */
+#endif /* CHAP_SUPPORT */
+#if MSCHAP_SUPPORT
+  unsigned int  refuse_mschap       :1;      /* Don't proceed auth. with MS-CHAP */
+  unsigned int  refuse_mschap_v2    :1;      /* Don't proceed auth. with MS-CHAPv2 */
+#endif /* MSCHAP_SUPPORT */
+#if EAP_SUPPORT
+  unsigned int  refuse_eap          :1;      /* Don't proceed auth. with EAP */
+#endif /* EAP_SUPPORT */
+#if LWIP_DNS
+  unsigned int  usepeerdns          :1;      /* Ask peer for DNS adds */
+#endif /* LWIP_DNS */
+  unsigned int  persist             :1;      /* Persist mode, always try to open the connection */
+#if PRINTPKT_SUPPORT
+  unsigned int  hide_password       :1;      /* Hide password in dumped packets */
+#endif /* PRINTPKT_SUPPORT */
+  unsigned int  noremoteip          :1;      /* Let him have no IP address */
+  unsigned int  lax_recv            :1;      /* accept control chars in asyncmap */
+  unsigned int  noendpoint          :1;      /* don't send/accept endpoint discriminator */
+#if PPP_LCP_ADAPTIVE
+  unsigned int lcp_echo_adaptive    :1;      /* request echo only if the link was idle */
+#endif /* PPP_LCP_ADAPTIVE */
+#if MPPE_SUPPORT
+  unsigned int require_mppe         :1;      /* Require MPPE (Microsoft Point to Point Encryption) */
+  unsigned int refuse_mppe_40       :1;      /* Allow MPPE 40-bit mode? */
+  unsigned int refuse_mppe_128      :1;      /* Allow MPPE 128-bit mode? */
+  unsigned int refuse_mppe_stateful :1;      /* Allow MPPE stateful mode? */
+#endif /* MPPE_SUPPORT */
+
+  u16_t  listen_time;                 /* time to listen first (ms), waiting for peer to send LCP packet */
+
+#if PPP_IDLETIMELIMIT
+  u16_t  idle_time_limit;             /* Disconnect if idle for this many seconds */
+#endif /* PPP_IDLETIMELIMIT */
+#if PPP_MAXCONNECT
+  u32_t  maxconnect;                  /* Maximum connect time (seconds) */
+#endif /* PPP_MAXCONNECT */
+
+#if PPP_AUTH_SUPPORT
+  /* auth data */
+  const char  *user;                   /* Username for PAP */
+  const char  *passwd;                 /* Password for PAP, secret for CHAP */
+#if PPP_REMOTENAME
+  char  remote_name[MAXNAMELEN   + 1]; /* Peer's name for authentication */
+#endif /* PPP_REMOTENAME */
+
+#if PAP_SUPPORT
+  u8_t  pap_timeout_time;        /* Timeout (seconds) for auth-req retrans. */
+  u8_t  pap_max_transmits;       /* Number of auth-reqs sent */
+#if PPP_SERVER
+  u8_t  pap_req_timeout;         /* Time to wait for auth-req from peer */
+#endif /* PPP_SERVER */
+#endif /* PAP_SUPPPORT */
+
+#if CHAP_SUPPORT
+  u8_t  chap_timeout_time;       /* Timeout (seconds) for retransmitting req */
+  u8_t  chap_max_transmits;      /* max # times to send challenge */
+#if PPP_SERVER
+  u8_t  chap_rechallenge_time;   /* Time to wait for auth-req from peer */
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPPORT */
+
+#if EAP_SUPPORT
+  u8_t  eap_req_time;            /* Time to wait (for retransmit/fail) */
+  u8_t  eap_allow_req;           /* Max Requests allowed */
+#if PPP_SERVER
+  u8_t  eap_timeout_time;        /* Time to wait (for retransmit/fail) */
+  u8_t  eap_max_transmits;       /* Max Requests allowed */
+#endif /* PPP_SERVER */
+#endif /* EAP_SUPPORT */
+
+#endif /* PPP_AUTH_SUPPORT */
+
+  u8_t  fsm_timeout_time;            /* Timeout time in seconds */
+  u8_t  fsm_max_conf_req_transmits;  /* Maximum Configure-Request transmissions */
+  u8_t  fsm_max_term_transmits;      /* Maximum Terminate-Request transmissions */
+  u8_t  fsm_max_nak_loops;           /* Maximum number of nak loops tolerated */
+
+  u8_t  lcp_loopbackfail;     /* Number of times we receive our magic number from the peer
+                                 before deciding the link is looped-back. */
+  u8_t  lcp_echo_interval;    /* Interval between LCP echo-requests */
+  u8_t  lcp_echo_fails;       /* Tolerance to unanswered echo-requests */
+
+} ppp_settings;
+
+#if PPP_SERVER
+struct ppp_addrs {
+#if PPP_IPV4_SUPPORT
+  ip4_addr_t our_ipaddr, his_ipaddr, netmask;
+#if LWIP_DNS
+  ip4_addr_t dns1, dns2;
+#endif /* LWIP_DNS */
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+  ip6_addr_t our6_ipaddr, his6_ipaddr;
+#endif /* PPP_IPV6_SUPPORT */
+};
+#endif /* PPP_SERVER */
+
+/*
+ * PPP interface control block.
+ */
+struct ppp_pcb_s {
+  ppp_settings settings;
+  const struct link_callbacks *link_cb;
+  void *link_ctx_cb;
+  void (*link_status_cb)(ppp_pcb *pcb, int err_code, void *ctx);  /* Status change callback */
+#if PPP_NOTIFY_PHASE
+  void (*notify_phase_cb)(ppp_pcb *pcb, u8_t phase, void *ctx);   /* Notify phase callback */
+#endif /* PPP_NOTIFY_PHASE */
+  void *ctx_cb;                  /* Callbacks optional pointer */
+  struct netif *netif;           /* PPP interface */
+  u8_t phase;                    /* where the link is at */
+  u8_t err_code;                 /* Code indicating why interface is down. */
+
+  /* flags */
+#if PPP_IPV4_SUPPORT
+  unsigned int ask_for_local           :1; /* request our address from peer */
+  unsigned int ipcp_is_open            :1; /* haven't called np_finished() */
+  unsigned int ipcp_is_up              :1; /* have called ipcp_up() */
+  unsigned int if4_up                  :1; /* True when the IPv4 interface is up. */
+#if 0 /* UNUSED - PROXY ARP */
+  unsigned int proxy_arp_set           :1; /* Have created proxy arp entry */
+#endif /* UNUSED - PROXY ARP */
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+  unsigned int ipv6cp_is_up            :1; /* have called ip6cp_up() */
+  unsigned int if6_up                  :1; /* True when the IPv6 interface is up. */
+#endif /* PPP_IPV6_SUPPORT */
+  unsigned int lcp_echo_timer_running  :1; /* set if a timer is running */
+#if VJ_SUPPORT
+  unsigned int vj_enabled              :1; /* Flag indicating VJ compression enabled. */
+#endif /* VJ_SUPPORT */
+#if CCP_SUPPORT
+  unsigned int ccp_all_rejected        :1; /* we rejected all peer's options */
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+  unsigned int mppe_keys_set           :1; /* Have the MPPE keys been set? */
+#endif /* MPPE_SUPPORT */
+
+#if PPP_AUTH_SUPPORT
+  /* auth data */
+#if PPP_SERVER && defined(HAVE_MULTILINK)
+  char peer_authname[MAXNAMELEN + 1]; /* The name by which the peer authenticated itself to us. */
+#endif /* PPP_SERVER && defined(HAVE_MULTILINK) */
+  u16_t auth_pending;        /* Records which authentication operations haven't completed yet. */
+  u16_t auth_done;           /* Records which authentication operations have been completed. */
+
+#if PAP_SUPPORT
+  upap_state upap;           /* PAP data */
+#endif /* PAP_SUPPORT */
+
+#if CHAP_SUPPORT
+  chap_client_state chap_client;  /* CHAP client data */
+#if PPP_SERVER
+  chap_server_state chap_server;  /* CHAP server data */
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPORT */
+
+#if EAP_SUPPORT
+  eap_state eap;            /* EAP data */
+#endif /* EAP_SUPPORT */
+#endif /* PPP_AUTH_SUPPORT */
+
+  fsm lcp_fsm;                   /* LCP fsm structure */
+  lcp_options lcp_wantoptions;   /* Options that we want to request */
+  lcp_options lcp_gotoptions;    /* Options that peer ack'd */
+  lcp_options lcp_allowoptions;  /* Options we allow peer to request */
+  lcp_options lcp_hisoptions;    /* Options that we ack'd */
+  u16_t peer_mru;                /* currently negotiated peer MRU */
+  u8_t lcp_echos_pending;        /* Number of outstanding echo msgs */
+  u8_t lcp_echo_number;          /* ID number of next echo frame */
+
+  u8_t num_np_open;              /* Number of network protocols which we have opened. */
+  u8_t num_np_up;                /* Number of network protocols which have come up. */
+
+#if VJ_SUPPORT
+  struct vjcompress vj_comp;     /* Van Jacobson compression header. */
+#endif /* VJ_SUPPORT */
+
+#if CCP_SUPPORT
+  fsm ccp_fsm;                   /* CCP fsm structure */
+  ccp_options ccp_wantoptions;   /* what to request the peer to use */
+  ccp_options ccp_gotoptions;    /* what the peer agreed to do */
+  ccp_options ccp_allowoptions;  /* what we'll agree to do */
+  ccp_options ccp_hisoptions;    /* what we agreed to do */
+  u8_t ccp_localstate;           /* Local state (mainly for handling reset-reqs and reset-acks). */
+  u8_t ccp_receive_method;       /* Method chosen on receive path */
+  u8_t ccp_transmit_method;      /* Method chosen on transmit path */
+#if MPPE_SUPPORT
+  ppp_mppe_state mppe_comp;      /* MPPE "compressor" structure */
+  ppp_mppe_state mppe_decomp;    /* MPPE "decompressor" structure */
+#endif /* MPPE_SUPPORT */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IPV4_SUPPORT
+  fsm ipcp_fsm;                   /* IPCP fsm structure */
+  ipcp_options ipcp_wantoptions;  /* Options that we want to request */
+  ipcp_options ipcp_gotoptions;   /* Options that peer ack'd */
+  ipcp_options ipcp_allowoptions; /* Options we allow peer to request */
+  ipcp_options ipcp_hisoptions;   /* Options that we ack'd */
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+  fsm ipv6cp_fsm;                     /* IPV6CP fsm structure */
+  ipv6cp_options ipv6cp_wantoptions;  /* Options that we want to request */
+  ipv6cp_options ipv6cp_gotoptions;   /* Options that peer ack'd */
+  ipv6cp_options ipv6cp_allowoptions; /* Options we allow peer to request */
+  ipv6cp_options ipv6cp_hisoptions;   /* Options that we ack'd */
+#endif /* PPP_IPV6_SUPPORT */
+};
+
+/************************
+ *** PUBLIC FUNCTIONS ***
+ ************************/
+
+/*
+ * WARNING: For multi-threads environment, all ppp_set_* functions most
+ * only be called while the PPP is in the dead phase (i.e. disconnected).
+ */
+
+#if PPP_AUTH_SUPPORT
+/*
+ * Set PPP authentication.
+ *
+ * Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ * Default is none auth type, unset (NULL) user and passwd.
+ */
+#define PPPAUTHTYPE_NONE      0x00
+#define PPPAUTHTYPE_PAP       0x01
+#define PPPAUTHTYPE_CHAP      0x02
+#define PPPAUTHTYPE_MSCHAP    0x04
+#define PPPAUTHTYPE_MSCHAP_V2 0x08
+#define PPPAUTHTYPE_EAP       0x10
+#define PPPAUTHTYPE_ANY       0xff
+void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd);
+
+/*
+ * If set, peer is required to authenticate. This is mostly necessary for PPP server support.
+ *
+ * Default is false.
+ */
+#define ppp_set_auth_required(ppp, boolval) (ppp->settings.auth_required = boolval)
+#endif /* PPP_AUTH_SUPPORT */
+
+#if PPP_IPV4_SUPPORT
+/*
+ * Set PPP interface "our" and "his" IPv4 addresses. This is mostly necessary for PPP server
+ * support but it can also be used on a PPP link where each side choose its own IP address.
+ *
+ * Default is unset (0.0.0.0).
+ */
+#define ppp_set_ipcp_ouraddr(ppp, addr) do { ppp->ipcp_wantoptions.ouraddr = ip4_addr_get_u32(addr); \
+                                             ppp->ask_for_local = ppp->ipcp_wantoptions.ouraddr != 0; } while(0)
+#define ppp_set_ipcp_hisaddr(ppp, addr) (ppp->ipcp_wantoptions.hisaddr = ip4_addr_get_u32(addr))
+#if LWIP_DNS
+/*
+ * Set DNS server addresses that are sent if the peer asks for them. This is mostly necessary
+ * for PPP server support.
+ *
+ * Default is unset (0.0.0.0).
+ */
+#define ppp_set_ipcp_dnsaddr(ppp, index, addr) (ppp->ipcp_allowoptions.dnsaddr[index] = ip4_addr_get_u32(addr))
+
+/*
+ * If set, we ask the peer for up to 2 DNS server addresses. Received DNS server addresses are
+ * registered using the dns_setserver() function.
+ *
+ * Default is false.
+ */
+#define ppp_set_usepeerdns(ppp, boolval) (ppp->settings.usepeerdns = boolval)
+#endif /* LWIP_DNS */
+#endif /* PPP_IPV4_SUPPORT */
+
+#if MPPE_SUPPORT
+/* Disable MPPE (Microsoft Point to Point Encryption). This parameter is exclusive. */
+#define PPP_MPPE_DISABLE           0x00
+/* Require the use of MPPE (Microsoft Point to Point Encryption). */
+#define PPP_MPPE_ENABLE            0x01
+/* Allow MPPE to use stateful mode. Stateless mode is still attempted first. */
+#define PPP_MPPE_ALLOW_STATEFUL    0x02
+/* Refuse the use of MPPE with 40-bit encryption. Conflict with PPP_MPPE_REFUSE_128. */
+#define PPP_MPPE_REFUSE_40         0x04
+/* Refuse the use of MPPE with 128-bit encryption. Conflict with PPP_MPPE_REFUSE_40. */
+#define PPP_MPPE_REFUSE_128        0x08
+/*
+ * Set MPPE configuration
+ *
+ * Default is disabled.
+ */
+void ppp_set_mppe(ppp_pcb *pcb, u8_t flags);
+#endif /* MPPE_SUPPORT */
+
+/*
+ * Wait for up to intval milliseconds for a valid PPP packet from the peer.
+ * At the end of this  time, or when a valid PPP packet is received from the
+ * peer, we commence negotiation by sending our first LCP packet.
+ *
+ * Default is 0.
+ */
+#define ppp_set_listen_time(ppp, intval) (ppp->settings.listen_time = intval)
+
+/*
+ * If set, we will attempt to initiate a connection but if no reply is received from
+ * the peer, we will then just wait passively for a valid LCP packet from the peer.
+ *
+ * Default is false.
+ */
+#define ppp_set_passive(ppp, boolval) (ppp->lcp_wantoptions.passive = boolval)
+
+/*
+ * If set, we will not transmit LCP packets to initiate a connection until a valid
+ * LCP packet is received from the peer. This is what we usually call the server mode.
+ *
+ * Default is false.
+ */
+#define ppp_set_silent(ppp, boolval) (ppp->lcp_wantoptions.silent = boolval)
+
+/*
+ * If set, enable protocol field compression negotiation in both the receive and
+ * the transmit direction.
+ *
+ * Default is true.
+ */
+#define ppp_set_neg_pcomp(ppp, boolval) (ppp->lcp_wantoptions.neg_pcompression = \
+                                         ppp->lcp_allowoptions.neg_pcompression = boolval)
+
+/*
+ * If set, enable Address/Control compression in both the receive and the transmit
+ * direction.
+ *
+ * Default is true.
+ */
+#define ppp_set_neg_accomp(ppp, boolval) (ppp->lcp_wantoptions.neg_accompression = \
+                                          ppp->lcp_allowoptions.neg_accompression = boolval)
+
+/*
+ * If set, enable asyncmap negotiation. Otherwise forcing all control characters to
+ * be escaped for both the transmit and the receive direction.
+ *
+ * Default is true.
+ */
+#define ppp_set_neg_asyncmap(ppp, boolval) (ppp->lcp_wantoptions.neg_asyncmap = \
+                                            ppp->lcp_allowoptions.neg_asyncmap = boolval)
+
+/*
+ * This option sets the Async-Control-Character-Map (ACCM) for this end of the link.
+ * The ACCM is a set of 32 bits, one for each of the ASCII control characters with
+ * values from 0 to 31, where a 1 bit  indicates that the corresponding control
+ * character should not be used in PPP packets sent to this system. The map is
+ * an unsigned 32 bits integer where the least significant bit (00000001) represents
+ * character 0 and the most significant bit (80000000) represents character 31.
+ * We will then ask the peer to send these characters as a 2-byte escape sequence.
+ *
+ * Default is 0.
+ */
+#define ppp_set_asyncmap(ppp, intval) (ppp->lcp_wantoptions.asyncmap = intval)
+
+/*
+ * Set a PPP interface as the default network interface
+ * (used to output all packets for which no specific route is found).
+ */
+#define ppp_set_default(ppp)         netif_set_default(ppp->netif)
+
+#if PPP_NOTIFY_PHASE
+/*
+ * Set a PPP notify phase callback.
+ *
+ * This can be used for example to set a LED pattern depending on the
+ * current phase of the PPP session.
+ */
+typedef void (*ppp_notify_phase_cb_fn)(ppp_pcb *pcb, u8_t phase, void *ctx);
+void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
+#endif /* PPP_NOTIFY_PHASE */
+
+/*
+ * Initiate a PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * Holdoff is the time to wait (in seconds) before initiating
+ * the connection.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff);
+
+#if PPP_SERVER
+/*
+ * Listen for an incoming PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_listen(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+
+/*
+ * Initiate the end of a PPP connection.
+ * Any outstanding packets in the queues are dropped.
+ *
+ * Setting nocarrier to 1 close the PPP connection without initiating the
+ * shutdown procedure. Always using nocarrier = 0 is still recommended,
+ * this is going to take a little longer time if your link is down, but
+ * is a safer choice for the PPP state machine.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_close(ppp_pcb *pcb, u8_t nocarrier);
+
+/*
+ * Release the control block.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * You must use ppp_close() before if you wish to terminate
+ * an established PPP session.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_free(ppp_pcb *pcb);
+
+/*
+ * PPP IOCTL commands.
+ *
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 0
+
+/*
+ * Get the PPP error code.  The argument must point to an int.
+ * Returns a PPPERR_* value.
+ */
+#define PPPCTLG_ERRCODE  1
+
+/*
+ * Get the fd associated with a PPP over serial
+ */
+#define PPPCTLG_FD       2
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
+
+/* Get the PPP netif interface */
+#define ppp_netif(ppp)               (ppp->netif)
+
+/* Set an lwIP-style status-callback for the selected PPP device */
+#define ppp_set_netif_statuscallback(ppp, status_cb)       \
+        netif_set_status_callback(ppp->netif, status_cb);
+
+/* Set an lwIP-style link-callback for the selected PPP device */
+#define ppp_set_netif_linkcallback(ppp, link_cb)           \
+        netif_set_link_callback(ppp->netif, link_cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp_impl.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp_impl.h
new file mode 100644
index 000000000..40843d5a0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp_impl.h
@@ -0,0 +1,722 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+#ifndef LWIP_HDR_PPP_IMPL_H
+#define LWIP_HDR_PPP_IMPL_H
+
+#include "netif/ppp/ppp_opts.h"
+
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifdef PPP_INCLUDE_SETTINGS_HEADER
+#include "ppp_settings.h"
+#endif
+
+#include <stdio.h> /* formats */
+#include <stdarg.h>
+#include <string.h>
+#include <stdlib.h> /* strtol() */
+
+#include "lwip/netif.h"
+#include "lwip/def.h"
+#include "lwip/timeouts.h"
+
+#include "ppp.h"
+#include "pppdebug.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Memory used for control packets.
+ *
+ * PPP_CTRL_PBUF_MAX_SIZE is the amount of memory we allocate when we
+ * cannot figure out how much we are going to use before filling the buffer.
+ */
+#if PPP_USE_PBUF_RAM
+#define PPP_CTRL_PBUF_TYPE       PBUF_RAM
+#define PPP_CTRL_PBUF_MAX_SIZE   512
+#else /* PPP_USE_PBUF_RAM */
+#define PPP_CTRL_PBUF_TYPE       PBUF_POOL
+#define PPP_CTRL_PBUF_MAX_SIZE   PBUF_POOL_BUFSIZE
+#endif /* PPP_USE_PBUF_RAM */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)	(((u_char *)(p))[0])
+#define PPP_CONTROL(p)	(((u_char *)(p))[1])
+#define PPP_PROTOCOL(p)	((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/*
+ * Significant octet values.
+ */
+#define	PPP_ALLSTATIONS	0xff	/* All-Stations broadcast address */
+#define	PPP_UI		0x03	/* Unnumbered Information */
+#define	PPP_FLAG	0x7e	/* Flag Sequence */
+#define	PPP_ESCAPE	0x7d	/* Asynchronous Control Escape */
+#define	PPP_TRANS	0x20	/* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP		0x21	/* Internet Protocol */
+#if 0 /* UNUSED */
+#define PPP_AT		0x29	/* AppleTalk Protocol */
+#define PPP_IPX		0x2b	/* IPX protocol */
+#endif /* UNUSED */
+#if VJ_SUPPORT
+#define	PPP_VJC_COMP	0x2d	/* VJ compressed TCP */
+#define	PPP_VJC_UNCOMP	0x2f	/* VJ uncompressed TCP */
+#endif /* VJ_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#define PPP_IPV6	0x57	/* Internet Protocol Version 6 */
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+#define PPP_COMP	0xfd	/* compressed packet */
+#endif /* CCP_SUPPORT */
+#define PPP_IPCP	0x8021	/* IP Control Protocol */
+#if 0 /* UNUSED */
+#define PPP_ATCP	0x8029	/* AppleTalk Control Protocol */
+#define PPP_IPXCP	0x802b	/* IPX Control Protocol */
+#endif /* UNUSED */
+#if PPP_IPV6_SUPPORT
+#define PPP_IPV6CP	0x8057	/* IPv6 Control Protocol */
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+#define PPP_CCP		0x80fd	/* Compression Control Protocol */
+#endif /* CCP_SUPPORT */
+#if ECP_SUPPORT
+#define PPP_ECP		0x8053	/* Encryption Control Protocol */
+#endif /* ECP_SUPPORT */
+#define PPP_LCP		0xc021	/* Link Control Protocol */
+#if PAP_SUPPORT
+#define PPP_PAP		0xc023	/* Password Authentication Protocol */
+#endif /* PAP_SUPPORT */
+#if LQR_SUPPORT
+#define PPP_LQR		0xc025	/* Link Quality Report protocol */
+#endif /* LQR_SUPPORT */
+#if CHAP_SUPPORT
+#define PPP_CHAP	0xc223	/* Cryptographic Handshake Auth. Protocol */
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+#define PPP_CBCP	0xc029	/* Callback Control Protocol */
+#endif /* CBCP_SUPPORT */
+#if EAP_SUPPORT
+#define PPP_EAP		0xc227	/* Extensible Authentication Protocol */
+#endif /* EAP_SUPPORT */
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular lower link level protocol.
+ */
+struct link_callbacks {
+  /* Start a connection (e.g. Initiate discovery phase) */
+  void (*connect) (ppp_pcb *pcb, void *ctx);
+#if PPP_SERVER
+  /* Listen for an incoming connection (Passive mode) */
+  void (*listen) (ppp_pcb *pcb, void *ctx);
+#endif /* PPP_SERVER */
+  /* End a connection (i.e. initiate disconnect phase) */
+  void (*disconnect) (ppp_pcb *pcb, void *ctx);
+  /* Free lower protocol control block */
+  err_t (*free) (ppp_pcb *pcb, void *ctx);
+  /* Write a pbuf to a ppp link, only used from PPP functions to send PPP packets. */
+  err_t (*write)(ppp_pcb *pcb, void *ctx, struct pbuf *p);
+  /* Send a packet from lwIP core (IPv4 or IPv6) */
+  err_t (*netif_output)(ppp_pcb *pcb, void *ctx, struct pbuf *p, u_short protocol);
+  /* configure the transmit-side characteristics of the PPP interface */
+  void (*send_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
+  /* confire the receive-side characteristics of the PPP interface */
+  void (*recv_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
+};
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+    NPMODE_PASS,		/* pass the packet through */
+    NPMODE_DROP,		/* silently drop the packet */
+    NPMODE_ERROR,		/* return an error */
+    NPMODE_QUEUE		/* save it up for later. */
+};
+
+/*
+ * Statistics.
+ */
+#if PPP_STATS_SUPPORT
+struct pppstat	{
+    unsigned int ppp_ibytes;	/* bytes received */
+    unsigned int ppp_ipackets;	/* packets received */
+    unsigned int ppp_ierrors;	/* receive errors */
+    unsigned int ppp_obytes;	/* bytes sent */
+    unsigned int ppp_opackets;	/* packets sent */
+    unsigned int ppp_oerrors;	/* transmit errors */
+};
+
+#if VJ_SUPPORT
+struct vjstat {
+    unsigned int vjs_packets;	/* outbound packets */
+    unsigned int vjs_compressed; /* outbound compressed packets */
+    unsigned int vjs_searches;	/* searches for connection state */
+    unsigned int vjs_misses;	/* times couldn't find conn. state */
+    unsigned int vjs_uncompressedin; /* inbound uncompressed packets */
+    unsigned int vjs_compressedin; /* inbound compressed packets */
+    unsigned int vjs_errorin;	/* inbound unknown type packets */
+    unsigned int vjs_tossed;	/* inbound packets tossed because of error */
+};
+#endif /* VJ_SUPPORT */
+
+struct ppp_stats {
+    struct pppstat p;		/* basic PPP statistics */
+#if VJ_SUPPORT
+    struct vjstat vj;		/* VJ header compression statistics */
+#endif /* VJ_SUPPORT */
+};
+
+#if CCP_SUPPORT
+struct compstat {
+    unsigned int unc_bytes;	/* total uncompressed bytes */
+    unsigned int unc_packets;	/* total uncompressed packets */
+    unsigned int comp_bytes;	/* compressed bytes */
+    unsigned int comp_packets;	/* compressed packets */
+    unsigned int inc_bytes;	/* incompressible bytes */
+    unsigned int inc_packets;	/* incompressible packets */
+    unsigned int ratio;		/* recent compression ratio << 8 */
+};
+
+struct ppp_comp_stats {
+    struct compstat c;		/* packet compression statistics */
+    struct compstat d;		/* packet decompression statistics */
+};
+#endif /* CCP_SUPPORT */
+
+#endif /* PPP_STATS_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+    time_t xmit_idle;		/* time since last NP packet sent */
+    time_t recv_idle;		/* time since last NP packet received */
+};
+#endif /* PPP_IDLETIMELIMIT */
+
+/* values for epdisc.class */
+#define EPD_NULL	0	/* null discriminator, no data */
+#define EPD_LOCAL	1
+#define EPD_IP		2
+#define EPD_MAC		3
+#define EPD_MAGIC	4
+#define EPD_PHONENUM	5
+
+/*
+ * Global variables.
+ */
+#ifdef HAVE_MULTILINK
+extern u8_t	multilink;	/* enable multilink operation */
+extern u8_t	doing_multilink;
+extern u8_t	multilink_master;
+extern u8_t	bundle_eof;
+extern u8_t	bundle_terminating;
+#endif
+
+#ifdef MAXOCTETS
+extern unsigned int maxoctets;	     /* Maximum octetes per session (in bytes) */
+extern int       maxoctets_dir;      /* Direction :
+				      0 - in+out (default)
+				      1 - in
+				      2 - out
+				      3 - max(in,out) */
+extern int       maxoctets_timeout;  /* Timeout for check of octets limit */
+#define PPP_OCTETS_DIRECTION_SUM        0
+#define PPP_OCTETS_DIRECTION_IN         1
+#define PPP_OCTETS_DIRECTION_OUT        2
+#define PPP_OCTETS_DIRECTION_MAXOVERAL  3
+/* same as previos, but little different on RADIUS side */
+#define PPP_OCTETS_DIRECTION_MAXSESSION 4
+#endif
+
+/* Data input may be used by CCP and ECP, remove this entry
+ * from struct protent to save some flash
+ */
+#define PPP_DATAINPUT 0
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;		/* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (ppp_pcb *pcb);
+    /* Process a received packet */
+    void (*input) (ppp_pcb *pcb, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (ppp_pcb *pcb);
+    /* Lower layer has come up */
+    void (*lowerup) (ppp_pcb *pcb);
+    /* Lower layer has gone down */
+    void (*lowerdown) (ppp_pcb *pcb);
+    /* Open the protocol */
+    void (*open) (ppp_pcb *pcb);
+    /* Close the protocol */
+    void (*close) (ppp_pcb *pcb, const char *reason);
+#if PRINTPKT_SUPPORT
+    /* Print a packet in readable form */
+    int  (*printpkt) (const u_char *pkt, int len,
+			  void (*printer) (void *, const char *, ...),
+			  void *arg);
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    /* Process a received data packet */
+    void (*datainput) (ppp_pcb *pcb, u_char *pkt, int len);
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    const char *name;		/* Text name of protocol */
+    const char *data_name;	/* Text name of corresponding data protocol */
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    option_t *options;		/* List of command-line options */
+    /* Check requested options, assign defaults */
+    void (*check_options) (void);
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif /* DEMAND_SUPPORT */
+};
+
+/* Table of pointers to supported protocols */
+extern const struct protent* const protocols[];
+
+
+/* Values for auth_pending, auth_done */
+#if PAP_SUPPORT
+#define PAP_WITHPEER	0x1
+#define PAP_PEER	0x2
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#define CHAP_WITHPEER	0x4
+#define CHAP_PEER	0x8
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#define EAP_WITHPEER	0x10
+#define EAP_PEER	0x20
+#endif /* EAP_SUPPORT */
+
+/* Values for auth_done only */
+#if CHAP_SUPPORT
+#define CHAP_MD5_WITHPEER	0x40
+#define CHAP_MD5_PEER		0x80
+#if MSCHAP_SUPPORT
+#define CHAP_MS_SHIFT		8	/* LSB position for MS auths */
+#define CHAP_MS_WITHPEER	0x100
+#define CHAP_MS_PEER		0x200
+#define CHAP_MS2_WITHPEER	0x400
+#define CHAP_MS2_PEER		0x800
+#endif /* MSCHAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+
+/* Supported CHAP protocols */
+#if CHAP_SUPPORT
+
+#if MSCHAP_SUPPORT
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MICROSOFT_V2 | MDTYPE_MICROSOFT | MDTYPE_MD5)
+#else /* MSCHAP_SUPPORT */
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MD5)
+#endif /* MSCHAP_SUPPORT */
+
+#else /* CHAP_SUPPORT */
+#define CHAP_MDTYPE_SUPPORTED (MDTYPE_NONE)
+#endif /* CHAP_SUPPORT */
+
+#if PPP_STATS_SUPPORT
+/*
+ * PPP statistics structure
+ */
+struct pppd_stats {
+    unsigned int	bytes_in;
+    unsigned int	bytes_out;
+    unsigned int	pkts_in;
+    unsigned int	pkts_out;
+};
+#endif /* PPP_STATS_SUPPORT */
+
+
+/*
+ * PPP private functions
+ */
+
+ 
+/*
+ * Functions called from lwIP core.
+ */
+
+/* initialize the PPP subsystem */
+int ppp_init(void);
+
+/*
+ * Functions called from PPP link protocols.
+ */
+
+/* Create a new PPP control block */
+ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb,
+                 ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+/* Initiate LCP open request */
+void ppp_start(ppp_pcb *pcb);
+
+/* Called when link failed to setup */
+void ppp_link_failed(ppp_pcb *pcb);
+
+/* Called when link is normally down (i.e. it was asked to end) */
+void ppp_link_end(ppp_pcb *pcb);
+
+/* function called to process input packet */
+void ppp_input(ppp_pcb *pcb, struct pbuf *pb);
+
+
+/*
+ * Functions called by PPP protocols.
+ */
+
+/* function called by all PPP subsystems to send packets */
+err_t ppp_write(ppp_pcb *pcb, struct pbuf *p);
+
+/* functions called by auth.c link_terminated() */
+void ppp_link_terminated(ppp_pcb *pcb);
+
+void new_phase(ppp_pcb *pcb, int p);
+
+int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp);
+int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp);
+
+#if PPP_IPV4_SUPPORT
+int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask);
+int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr);
+#if 0 /* UNUSED - PROXY ARP */
+int sifproxyarp(ppp_pcb *pcb, u32_t his_adr);
+int cifproxyarp(ppp_pcb *pcb, u32_t his_adr);
+#endif /* UNUSED - PROXY ARP */
+#if LWIP_DNS
+int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
+int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
+#endif /* LWIP_DNS */
+#if VJ_SUPPORT
+int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid);
+#endif /* VJ_SUPPORT */
+int sifup(ppp_pcb *pcb);
+int sifdown (ppp_pcb *pcb);
+u32_t get_mask(u32_t addr);
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
+int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
+int sif6up(ppp_pcb *pcb);
+int sif6down (ppp_pcb *pcb);
+#endif /* PPP_IPV6_SUPPORT */
+
+#if DEMAND_SUPPORT
+int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode);
+#endif /* DEMAND_SUPPORt */
+
+void netif_set_mtu(ppp_pcb *pcb, int mtu);
+int netif_get_mtu(ppp_pcb *pcb);
+
+#if CCP_SUPPORT
+#if 0 /* unused */
+int ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit);
+#endif /* unused */
+void ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method);
+void ccp_reset_comp(ppp_pcb *pcb);
+void ccp_reset_decomp(ppp_pcb *pcb);
+#if 0 /* unused */
+int ccp_fatal_error(ppp_pcb *pcb);
+#endif /* unused */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip);
+#endif /* PPP_IDLETIMELIMIT */
+
+#if DEMAND_SUPPORT
+int get_loop_output(void);
+#endif /* DEMAND_SUPPORT */
+
+/* Optional protocol names list, to make our messages a little more informative. */
+#if PPP_PROTOCOLNAME
+const char * protocol_name(int proto);
+#endif /* PPP_PROTOCOLNAME  */
+
+/* Optional stats support, to get some statistics on the PPP interface */
+#if PPP_STATS_SUPPORT
+void print_link_stats(void); /* Print stats, if available */
+void reset_link_stats(int u); /* Reset (init) stats when link goes up */
+void update_link_stats(int u); /* Get stats at link termination */
+#endif /* PPP_STATS_SUPPORT */
+
+
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+	(c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+	*(cp)++ = (u_char) (c); \
+}
+#define GETSHORT(s, cp) { \
+	(s) = *(cp)++ << 8; \
+	(s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+	*(cp)++ = (u_char) ((s) >> 8); \
+	*(cp)++ = (u_char) (s); \
+}
+#define GETLONG(l, cp) { \
+	(l) = *(cp)++ << 8; \
+	(l) |= *(cp)++; (l) <<= 8; \
+	(l) |= *(cp)++; (l) <<= 8; \
+	(l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+	*(cp)++ = (u_char) ((l) >> 24); \
+	*(cp)++ = (u_char) ((l) >> 16); \
+	*(cp)++ = (u_char) ((l) >> 8); \
+	*(cp)++ = (u_char) (l); \
+}
+
+#define INCPTR(n, cp)	((cp) += (n))
+#define DECPTR(n, cp)	((cp) -= (n))
+
+/*
+ * System dependent definitions for user-level 4.3BSD UNIX implementation.
+ */
+#define TIMEOUT(f, a, t)        do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0)
+#define TIMEOUTMS(f, a, t)      do { sys_untimeout((f), (a)); sys_timeout((t), (f), (a)); } while(0)
+#define UNTIMEOUT(f, a)         sys_untimeout((f), (a))
+
+#define BZERO(s, n)		memset(s, 0, n)
+#define	BCMP(s1, s2, l)		memcmp(s1, s2, l)
+
+#define PRINTMSG(m, l)		{ ppp_info("Remote message: %0.*v", l, m); }
+
+/*
+ * MAKEHEADER - Add Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/* Procedures exported from auth.c */
+void link_required(ppp_pcb *pcb);     /* we are starting to use the link */
+void link_terminated(ppp_pcb *pcb);   /* we are finished with the link */
+void link_down(ppp_pcb *pcb);	      /* the LCP layer has left the Opened state */
+void upper_layers_down(ppp_pcb *pcb); /* take all NCPs down */
+void link_established(ppp_pcb *pcb);  /* the link is up; authenticate now */
+void start_networks(ppp_pcb *pcb);    /* start all the network control protos */
+void continue_networks(ppp_pcb *pcb); /* start network [ip, etc] control protos */
+#if PPP_AUTH_SUPPORT
+#if PPP_SERVER
+int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen);
+                                /* check the user name and passwd against configuration */
+void auth_peer_fail(ppp_pcb *pcb, int protocol);
+				/* peer failed to authenticate itself */
+void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen);
+				/* peer successfully authenticated itself */
+#endif /* PPP_SERVER */
+void auth_withpeer_fail(ppp_pcb *pcb, int protocol);
+				/* we failed to authenticate ourselves */
+void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor);
+				/* we successfully authenticated ourselves */
+#endif /* PPP_AUTH_SUPPORT */
+void np_up(ppp_pcb *pcb, int proto);    /* a network protocol has come up */
+void np_down(ppp_pcb *pcb, int proto);  /* a network protocol has gone down */
+void np_finished(ppp_pcb *pcb, int proto); /* a network protocol no longer needs link */
+#if PPP_AUTH_SUPPORT
+int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server);
+				/* get "secret" for chap */
+#endif /* PPP_AUTH_SUPPORT */
+
+/* Procedures exported from ipcp.c */
+/* int parse_dotted_ip (char *, u32_t *); */
+
+/* Procedures exported from demand.c */
+#if DEMAND_SUPPORT
+void demand_conf (void);	/* config interface(s) for demand-dial */
+void demand_block (void);	/* set all NPs to queue up packets */
+void demand_unblock (void); /* set all NPs to pass packets */
+void demand_discard (void); /* set all NPs to discard packets */
+void demand_rexmit (int, u32_t); /* retransmit saved frames for an NP*/
+int  loop_chars (unsigned char *, int); /* process chars from loopback */
+int  loop_frame (unsigned char *, int); /* should we bring link up? */
+#endif /* DEMAND_SUPPORT */
+
+/* Procedures exported from multilink.c */
+#ifdef HAVE_MULTILINK
+void mp_check_options (void); /* Check multilink-related options */
+int  mp_join_bundle (void);  /* join our link to an appropriate bundle */
+void mp_exit_bundle (void);  /* have disconnected our link from bundle */
+void mp_bundle_terminated (void);
+char *epdisc_to_str (struct epdisc *); /* string from endpoint discrim. */
+int  str_to_epdisc (struct epdisc *, char *); /* endpt disc. from str */
+#else
+#define mp_bundle_terminated()	/* nothing */
+#define mp_exit_bundle()	/* nothing */
+#define doing_multilink		0
+#define multilink_master	0
+#endif
+
+/* Procedures exported from utils.c. */
+void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg);   /* Format a string for output */
+int ppp_slprintf(char *buf, int buflen, const char *fmt, ...);            /* sprintf++ */
+int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args);  /* vsprintf++ */
+size_t ppp_strlcpy(char *dest, const char *src, size_t len);        /* safe strcpy */
+size_t ppp_strlcat(char *dest, const char *src, size_t len);        /* safe strncpy */
+void ppp_dbglog(const char *fmt, ...);    /* log a debug message */
+void ppp_info(const char *fmt, ...);      /* log an informational message */
+void ppp_notice(const char *fmt, ...);    /* log a notice-level message */
+void ppp_warn(const char *fmt, ...);      /* log a warning message */
+void ppp_error(const char *fmt, ...);     /* log an error message */
+void ppp_fatal(const char *fmt, ...);     /* log an error message and die(1) */
+#if PRINTPKT_SUPPORT
+void ppp_dump_packet(ppp_pcb *pcb, const char *tag, unsigned char *p, int len);
+                                /* dump packet to debug log if interesting */
+#endif /* PRINTPKT_SUPPORT */
+
+/*
+ * Number of necessary timers analysis.
+ *
+ * PPP use at least one timer per each of its protocol, but not all protocols are
+ * active at the same time, thus the number of necessary timeouts is actually
+ * lower than enabled protocols. Here is the actual necessary timeouts based
+ * on code analysis.
+ *
+ * Note that many features analysed here are not working at all and are only
+ * there for a comprehensive analysis of necessary timers in order to prevent
+ * having to redo that each time we add a feature.
+ *
+ * Timer list
+ *
+ * | holdoff timeout
+ *  | low level protocol timeout (PPPoE or PPPoL2P)
+ *   | LCP delayed UP
+ *    | LCP retransmit (FSM)
+ *     | LCP Echo timer
+ *     .| PAP or CHAP or EAP authentication
+ *     . | ECP retransmit (FSM)
+ *     .  | CCP retransmit (FSM) when MPPE is enabled
+ *     .   | CCP retransmit (FSM) when MPPE is NOT enabled
+ *     .    | IPCP retransmit (FSM)
+ *     .    .| IP6CP retransmit (FSM)
+ *     .    . | Idle time limit
+ *     .    .  | Max connect time
+ *     .    .   | Max octets
+ *     .    .    | CCP RACK timeout
+ *     .    .    .
+ * PPP_PHASE_DEAD
+ * PPP_PHASE_HOLDOFF
+ * |   .    .    .
+ * PPP_PHASE_INITIALIZE
+ *  |  .    .    .
+ * PPP_PHASE_ESTABLISH
+ *   | .    .    .
+ *    |.    .    .
+ *     |    .    .
+ * PPP_PHASE_AUTHENTICATE
+ *     |    .    .
+ *     ||   .    .
+ * PPP_PHASE_NETWORK
+ *     | || .    .
+ *     |   |||   .
+ * PPP_PHASE_RUNNING
+ *     |    .|||||
+ *     |    . ||||
+ * PPP_PHASE_TERMINATE
+ *     |    . ||||
+ * PPP_PHASE_NETWORK
+ *    |.         .
+ * PPP_PHASE_ESTABLISH
+ * PPP_PHASE_DISCONNECT
+ * PPP_PHASE_DEAD
+ *
+ * Alright, PPP basic retransmission and LCP Echo consume one timer.
+ *  1
+ *
+ * If authentication is enabled one timer is necessary during authentication.
+ *  1 + PPP_AUTH_SUPPORT
+ *
+ * If ECP is enabled one timer is necessary before IPCP and/or IP6CP, one more
+ * is necessary if CCP is enabled (only with MPPE support but we don't care much
+ * up to this detail level).
+ *  1 + ECP_SUPPORT + CCP_SUPPORT
+ *
+ * If CCP is enabled it might consume a timer during IPCP or IP6CP, thus
+ * we might use IPCP, IP6CP and CCP timers simultaneously.
+ *  1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT
+ *
+ * When entering running phase, IPCP or IP6CP is still running. If idle time limit
+ * is enabled one more timer is necessary. Same for max connect time and max
+ * octets features. Furthermore CCP RACK might be used past this point.
+ *  1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS + CCP_SUPPORT
+ *
+ * IPv4 or IPv6 must be enabled, therefore we don't need to take care the authentication
+ * and the CCP + ECP case, thus reducing overall complexity.
+ * 1 + LWIP_MAX(PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT, PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS + CCP_SUPPORT)
+ *
+ * We don't support PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS features
+ * and adding those defines to ppp_opts.h just for having the value always
+ * defined to 0 isn't worth it.
+ * 1 + LWIP_MAX(PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT, PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + CCP_SUPPORT)
+ *
+ * Thus, the following is enough for now.
+ * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_SUPPORT */
+#endif /* LWIP_HDR_PPP_IMPL_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp_opts.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp_opts.h
new file mode 100644
index 000000000..6702bec61
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/ppp_opts.h
@@ -0,0 +1,610 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef LWIP_PPP_OPTS_H
+#define LWIP_PPP_OPTS_H
+
+#include "lwip/opt.h"
+
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT                   0
+#endif
+
+/**
+ * PPPOL2TP_SUPPORT==1: Enable PPP Over L2TP
+ */
+#ifndef PPPOL2TP_SUPPORT
+#define PPPOL2TP_SUPPORT                0
+#endif
+
+/**
+ * PPPOL2TP_AUTH_SUPPORT==1: Enable PPP Over L2TP Auth (enable MD5 support)
+ */
+#ifndef PPPOL2TP_AUTH_SUPPORT
+#define PPPOL2TP_AUTH_SUPPORT           PPPOL2TP_SUPPORT
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT                   PPP_SUPPORT
+#endif
+
+/**
+ * LWIP_PPP_API==1: Enable PPP API (in pppapi.c)
+ */
+#ifndef LWIP_PPP_API
+#define LWIP_PPP_API                    (PPP_SUPPORT && (NO_SYS == 0))
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * MEMP_NUM_PPP_PCB: the number of simultaneously active PPP
+ * connections (requires the PPP_SUPPORT option)
+ */
+#ifndef MEMP_NUM_PPP_PCB
+#define MEMP_NUM_PPP_PCB                1
+#endif
+
+/**
+ * PPP_NUM_TIMEOUTS_PER_PCB: the number of sys_timeouts running in parallel per
+ * ppp_pcb. See the detailed explanation at the end of ppp_impl.h about simultaneous
+ * timers analysis.
+ */
+#ifndef PPP_NUM_TIMEOUTS_PER_PCB
+#define PPP_NUM_TIMEOUTS_PER_PCB        (1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT)
+#endif
+
+/* The number of sys_timeouts required for the PPP module */
+#define PPP_NUM_TIMEOUTS                (PPP_SUPPORT * PPP_NUM_TIMEOUTS_PER_PCB * MEMP_NUM_PPP_PCB)
+
+/**
+ * MEMP_NUM_PPPOS_INTERFACES: the number of concurrently active PPPoS
+ * interfaces (only used with PPPOS_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOS_INTERFACES
+#define MEMP_NUM_PPPOS_INTERFACES       MEMP_NUM_PPP_PCB
+#endif
+
+/**
+ * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
+ * interfaces (only used with PPPOE_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOE_INTERFACES
+#define MEMP_NUM_PPPOE_INTERFACES       1
+#endif
+
+/**
+ * MEMP_NUM_PPPOL2TP_INTERFACES: the number of concurrently active PPPoL2TP
+ * interfaces (only used with PPPOL2TP_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOL2TP_INTERFACES
+#define MEMP_NUM_PPPOL2TP_INTERFACES       1
+#endif
+
+/**
+ * MEMP_NUM_PPP_API_MSG: Number of concurrent PPP API messages (in pppapi.c)
+ */
+#ifndef MEMP_NUM_PPP_API_MSG
+#define MEMP_NUM_PPP_API_MSG 5
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG                       LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_INPROC_IRQ_SAFE==1 call pppos_input() using tcpip_callback().
+ *
+ * Please read the "PPPoS input path" chapter in the PPP documentation about this option.
+ */
+#ifndef PPP_INPROC_IRQ_SAFE
+#define PPP_INPROC_IRQ_SAFE             0
+#endif
+
+/**
+ * PRINTPKT_SUPPORT==1: Enable PPP print packet support
+ *
+ * Mandatory for debugging, it displays exchanged packet content in debug trace.
+ */
+#ifndef PRINTPKT_SUPPORT
+#define PRINTPKT_SUPPORT                0
+#endif
+
+/**
+ * PPP_IPV4_SUPPORT==1: Enable PPP IPv4 support
+ */
+#ifndef PPP_IPV4_SUPPORT
+#define PPP_IPV4_SUPPORT                (LWIP_IPV4)
+#endif
+
+/**
+ * PPP_IPV6_SUPPORT==1: Enable PPP IPv6 support
+ */
+#ifndef PPP_IPV6_SUPPORT
+#define PPP_IPV6_SUPPORT                (LWIP_IPV6)
+#endif
+
+/**
+ * PPP_NOTIFY_PHASE==1: Support PPP notify phase support
+ *
+ * PPP notify phase support allows you to set a callback which is
+ * called on change of the internal PPP state machine.
+ *
+ * This can be used for example to set a LED pattern depending on the
+ * current phase of the PPP session.
+ */
+#ifndef PPP_NOTIFY_PHASE
+#define PPP_NOTIFY_PHASE                0
+#endif
+
+/**
+ * pbuf_type PPP is using for LCP, PAP, CHAP, EAP, CCP, IPCP and IP6CP packets.
+ *
+ * Memory allocated must be single buffered for PPP to works, it requires pbuf
+ * that are not going to be chained when allocated. This requires setting
+ * PBUF_POOL_BUFSIZE to at least 512 bytes, which is quite huge for small systems.
+ *
+ * Setting PPP_USE_PBUF_RAM to 1 makes PPP use memory from heap where continuous
+ * buffers are required, allowing you to use a smaller PBUF_POOL_BUFSIZE.
+ */
+#ifndef PPP_USE_PBUF_RAM
+#define PPP_USE_PBUF_RAM                0
+#endif
+
+/**
+ * PPP_FCS_TABLE: Keep a 256*2 byte table to speed up FCS calculation for PPPoS
+ */
+#ifndef PPP_FCS_TABLE
+#define PPP_FCS_TABLE                   1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP.
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  0
+#endif
+#if MSCHAP_SUPPORT
+/* MSCHAP requires CHAP support */
+#undef CHAP_SUPPORT
+#define CHAP_SUPPORT                    1
+#endif /* MSCHAP_SUPPORT */
+
+/**
+ * EAP_SUPPORT==1: Support EAP.
+ */
+#ifndef EAP_SUPPORT
+#define EAP_SUPPORT                     0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP.
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT                     0
+#endif
+
+/**
+ * MPPE_SUPPORT==1: Support MPPE.
+ */
+#ifndef MPPE_SUPPORT
+#define MPPE_SUPPORT                    0
+#endif
+#if MPPE_SUPPORT
+/* MPPE requires CCP support */
+#undef CCP_SUPPORT
+#define CCP_SUPPORT                     1
+/* MPPE requires MSCHAP support */
+#undef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT                  1
+/* MSCHAP requires CHAP support */
+#undef CHAP_SUPPORT
+#define CHAP_SUPPORT                    1
+#endif /* MPPE_SUPPORT */
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT                    0
+#endif
+
+/**
+ * ECP_SUPPORT==1: Support ECP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef ECP_SUPPORT
+#define ECP_SUPPORT                     0
+#endif
+
+/**
+ * DEMAND_SUPPORT==1: Support dial on demand. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef DEMAND_SUPPORT
+#define DEMAND_SUPPORT                  0
+#endif
+
+/**
+ * LQR_SUPPORT==1: Support Link Quality Report. Do nothing except exchanging some LCP packets.
+ */
+#ifndef LQR_SUPPORT
+#define LQR_SUPPORT                     0
+#endif
+
+/**
+ * PPP_SERVER==1: Enable PPP server support (waiting for incoming PPP session).
+ *
+ * Currently only supported for PPPoS.
+ */
+#ifndef PPP_SERVER
+#define PPP_SERVER                      0
+#endif
+
+#if PPP_SERVER
+/*
+ * PPP_OUR_NAME: Our name for authentication purposes
+ */
+#ifndef PPP_OUR_NAME
+#define PPP_OUR_NAME                    "lwIP"
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      1
+#endif
+/* VJ compression is only supported for TCP over IPv4 over PPPoS. */
+#if !PPPOS_SUPPORT || !PPP_IPV4_SUPPORT || !LWIP_TCP
+#undef VJ_SUPPORT
+#define VJ_SUPPORT                      0
+#endif /* !PPPOS_SUPPORT */
+
+/**
+ * PPP_MD5_RANDM==1: Use MD5 for better randomness.
+ * Enabled by default if CHAP, EAP, or L2TP AUTH support is enabled.
+ */
+#ifndef PPP_MD5_RANDM
+#define PPP_MD5_RANDM                   (CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT)
+#endif
+
+/**
+ * PolarSSL embedded library
+ *
+ *
+ * lwIP contains some files fetched from the latest BSD release of
+ * the PolarSSL project (PolarSSL 0.10.1-bsd) for ciphers and encryption
+ * methods we need for lwIP PPP support.
+ *
+ * The PolarSSL files were cleaned to contain only the necessary struct
+ * fields and functions needed for lwIP.
+ *
+ * The PolarSSL API was not changed at all, so if you are already using
+ * PolarSSL you can choose to skip the compilation of the included PolarSSL
+ * library into lwIP.
+ *
+ * If you are not using the embedded copy you must include external
+ * libraries into your arch/cc.h port file.
+ *
+ * Beware of the stack requirements which can be a lot larger if you are not
+ * using our cleaned PolarSSL library.
+ */
+
+/**
+ * LWIP_USE_EXTERNAL_POLARSSL: Use external PolarSSL library
+ */
+#ifndef LWIP_USE_EXTERNAL_POLARSSL
+#define LWIP_USE_EXTERNAL_POLARSSL      0
+#endif
+
+/**
+ * LWIP_USE_EXTERNAL_MBEDTLS: Use external mbed TLS library
+ */
+#ifndef LWIP_USE_EXTERNAL_MBEDTLS
+#define LWIP_USE_EXTERNAL_MBEDTLS       0
+#endif
+
+/*
+ * PPP Timeouts
+ */
+
+/**
+ * FSM_DEFTIMEOUT: Timeout time in seconds
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT                  6
+#endif
+
+/**
+ * FSM_DEFMAXTERMREQS: Maximum Terminate-Request transmissions
+ */
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS              2
+#endif
+
+/**
+ * FSM_DEFMAXCONFREQS: Maximum Configure-Request transmissions
+ */
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS              10
+#endif
+
+/**
+ * FSM_DEFMAXNAKLOOPS: Maximum number of nak loops
+ */
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS              5
+#endif
+
+/**
+ * UPAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
+ */
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT                 6
+#endif
+
+/**
+ * UPAP_DEFTRANSMITS: Maximum number of auth-reqs to send
+ */
+#ifndef UPAP_DEFTRANSMITS
+#define UPAP_DEFTRANSMITS               10
+#endif
+
+#if PPP_SERVER
+/**
+ * UPAP_DEFREQTIME: Time to wait for auth-req from peer
+ */
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME                 30
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * CHAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
+ */
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT                 6
+#endif
+
+/**
+ * CHAP_DEFTRANSMITS: max # times to send challenge
+ */
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS               10
+#endif
+
+#if PPP_SERVER
+/**
+ * CHAP_DEFRECHALLENGETIME: If this option is > 0, rechallenge the peer every n seconds
+ */
+#ifndef CHAP_DEFRECHALLENGETIME
+#define CHAP_DEFRECHALLENGETIME         0
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * EAP_DEFREQTIME: Time to wait for peer request
+ */
+#ifndef EAP_DEFREQTIME
+#define EAP_DEFREQTIME                  6
+#endif
+
+/**
+ * EAP_DEFALLOWREQ: max # times to accept requests
+ */
+#ifndef EAP_DEFALLOWREQ
+#define EAP_DEFALLOWREQ                 10
+#endif
+
+#if PPP_SERVER
+/**
+ * EAP_DEFTIMEOUT: Timeout (seconds) for rexmit
+ */
+#ifndef EAP_DEFTIMEOUT
+#define EAP_DEFTIMEOUT                  6
+#endif
+
+/**
+ * EAP_DEFTRANSMITS: max # times to transmit
+ */
+#ifndef EAP_DEFTRANSMITS
+#define EAP_DEFTRANSMITS                10
+#endif
+#endif /* PPP_SERVER */
+
+/**
+ * LCP_DEFLOOPBACKFAIL: Default number of times we receive our magic number from the peer
+ * before deciding the link is looped-back.
+ */
+#ifndef LCP_DEFLOOPBACKFAIL
+#define LCP_DEFLOOPBACKFAIL             10
+#endif
+
+/**
+ * LCP_ECHOINTERVAL: Interval in seconds between keepalive echo requests, 0 to disable.
+ */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL                0
+#endif
+
+/**
+ * LCP_MAXECHOFAILS: Number of unanswered echo requests before failure.
+ */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS                3
+#endif
+
+/**
+ * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char.
+ */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG                 100
+#endif
+
+/**
+ * PPP Packet sizes
+ */
+
+/**
+ * PPP_MRU: Default MRU
+ */
+#ifndef PPP_MRU
+#define PPP_MRU                         1500
+#endif
+
+/**
+ * PPP_DEFMRU: Default MRU to try
+ */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU                      1500
+#endif
+
+/**
+ * PPP_MAXMRU: Normally limit MRU to this (pppd default = 16384)
+ */
+#ifndef PPP_MAXMRU
+#define PPP_MAXMRU                      1500
+#endif
+
+/**
+ * PPP_MINMRU: No MRUs below this
+ */
+#ifndef PPP_MINMRU
+#define PPP_MINMRU                      128
+#endif
+
+/**
+ * PPPOL2TP_DEFMRU: Default MTU and MRU for L2TP
+ * Default = 1500 - PPPoE(6) - PPP Protocol(2) - IPv4 header(20) - UDP Header(8)
+ * - L2TP Header(6) - HDLC Header(2) - PPP Protocol(2) - MPPE Header(2) - PPP Protocol(2)
+ */
+#if PPPOL2TP_SUPPORT
+#ifndef PPPOL2TP_DEFMRU
+#define PPPOL2TP_DEFMRU                 1450
+#endif
+#endif /* PPPOL2TP_SUPPORT */
+
+/**
+ * MAXNAMELEN: max length of hostname or name for auth
+ */
+#ifndef MAXNAMELEN
+#define MAXNAMELEN                      256
+#endif
+
+/**
+ * MAXSECRETLEN: max length of password or secret
+ */
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN                    256
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Build triggers for embedded PolarSSL
+ */
+#if !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS
+
+/* CHAP, EAP, L2TP AUTH and MD5 Random require MD5 support */
+#if CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM
+#define LWIP_INCLUDED_POLARSSL_MD5      1
+#endif /* CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM */
+
+#if MSCHAP_SUPPORT
+
+/* MSCHAP require MD4 support */
+#define LWIP_INCLUDED_POLARSSL_MD4      1
+/* MSCHAP require SHA1 support */
+#define LWIP_INCLUDED_POLARSSL_SHA1     1
+/* MSCHAP require DES support */
+#define LWIP_INCLUDED_POLARSSL_DES      1
+
+/* MS-CHAP support is required for MPPE */
+#if MPPE_SUPPORT
+/* MPPE require ARC4 support */
+#define LWIP_INCLUDED_POLARSSL_ARC4     1
+#endif /* MPPE_SUPPORT */
+
+#endif /* MSCHAP_SUPPORT */
+
+#endif /* !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS */
+
+/* Default value if unset */
+#ifndef LWIP_INCLUDED_POLARSSL_MD4
+#define LWIP_INCLUDED_POLARSSL_MD4      0
+#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
+#ifndef LWIP_INCLUDED_POLARSSL_MD5
+#define LWIP_INCLUDED_POLARSSL_MD5      0
+#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
+#ifndef LWIP_INCLUDED_POLARSSL_SHA1
+#define LWIP_INCLUDED_POLARSSL_SHA1     0
+#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
+#ifndef LWIP_INCLUDED_POLARSSL_DES
+#define LWIP_INCLUDED_POLARSSL_DES      0
+#endif /* LWIP_INCLUDED_POLARSSL_DES */
+#ifndef LWIP_INCLUDED_POLARSSL_ARC4
+#define LWIP_INCLUDED_POLARSSL_ARC4     0
+#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
+
+#endif /* PPP_SUPPORT */
+
+/* Default value if unset */
+#ifndef PPP_NUM_TIMEOUTS
+#define PPP_NUM_TIMEOUTS                0
+#endif /* PPP_NUM_TIMEOUTS */
+
+#endif /* LWIP_PPP_OPTS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppapi.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppapi.h
new file mode 100644
index 000000000..913d93f74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppapi.h
@@ -0,0 +1,137 @@
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#ifndef LWIP_PPPAPI_H
+#define LWIP_PPPAPI_H
+
+#include "netif/ppp/ppp_opts.h"
+
+#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/sys.h"
+#include "lwip/netif.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "netif/ppp/ppp.h"
+#if PPPOS_SUPPORT
+#include "netif/ppp/pppos.h"
+#endif /* PPPOS_SUPPORT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pppapi_msg_msg {
+  ppp_pcb *ppp;
+  union {
+#if PPP_NOTIFY_PHASE
+    struct {
+      ppp_notify_phase_cb_fn notify_phase_cb;
+    } setnotifyphasecb;
+#endif /* PPP_NOTIFY_PHASE */
+#if PPPOS_SUPPORT
+    struct {
+      struct netif *pppif;
+      pppos_output_cb_fn output_cb;
+      ppp_link_status_cb_fn link_status_cb;
+      void *ctx_cb;
+    } serialcreate;
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+    struct {
+      struct netif *pppif;
+      struct netif *ethif;
+      const char *service_name;
+      const char *concentrator_name;
+      ppp_link_status_cb_fn link_status_cb;
+      void *ctx_cb;
+    } ethernetcreate;
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+    struct {
+      struct netif *pppif;
+      struct netif *netif;
+      API_MSG_M_DEF_C(ip_addr_t, ipaddr);
+      u16_t port;
+#if PPPOL2TP_AUTH_SUPPORT
+      const u8_t *secret;
+      u8_t secret_len;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+      ppp_link_status_cb_fn link_status_cb;
+      void *ctx_cb;
+    } l2tpcreate;
+#endif /* PPPOL2TP_SUPPORT */
+    struct {
+      u16_t holdoff;
+    } connect;
+    struct {
+      u8_t nocarrier;
+    } close;
+    struct {
+      u8_t cmd;
+      void *arg;
+    } ioctl;
+  } msg;
+};
+
+struct pppapi_msg {
+  struct tcpip_api_call_data call;
+  struct pppapi_msg_msg msg;
+};
+
+/* API for application */
+err_t pppapi_set_default(ppp_pcb *pcb);
+#if PPP_NOTIFY_PHASE
+err_t pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
+#endif /* PPP_NOTIFY_PHASE */
+#if PPPOS_SUPPORT
+ppp_pcb *pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+#endif /* PPPOS_SUPPORT */
+#if PPPOE_SUPPORT
+ppp_pcb *pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name,
+                                const char *concentrator_name, ppp_link_status_cb_fn link_status_cb,
+                                void *ctx_cb);
+#endif /* PPPOE_SUPPORT */
+#if PPPOL2TP_SUPPORT
+ppp_pcb *pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port,
+                            const u8_t *secret, u8_t secret_len,
+                            ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+#endif /* PPPOL2TP_SUPPORT */
+err_t pppapi_connect(ppp_pcb *pcb, u16_t holdoff);
+#if PPP_SERVER
+err_t pppapi_listen(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+err_t pppapi_close(ppp_pcb *pcb, u8_t nocarrier);
+err_t pppapi_free(ppp_pcb *pcb);
+err_t pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_PPP_API */
+
+#endif /* LWIP_PPPAPI_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppcrypt.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppcrypt.h
new file mode 100644
index 000000000..c0230bbcb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppcrypt.h
@@ -0,0 +1,144 @@
+/*
+ * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1
+ *
+ * Extracted from chap_ms.c by James Carlson.
+ *
+ * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/* This header file is included in all PPP modules needing hashes and/or ciphers */
+
+#ifndef PPPCRYPT_H
+#define	PPPCRYPT_H
+
+/*
+ * If included PolarSSL copy is not used, user is expected to include
+ * external libraries in arch/cc.h (which is included by lwip/arch.h).
+ */
+#include "lwip/arch.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Map hashes and ciphers functions to PolarSSL
+ */
+#if !LWIP_USE_EXTERNAL_MBEDTLS
+
+#include "netif/ppp/polarssl/md4.h"
+#define lwip_md4_context md4_context
+#define lwip_md4_init(context)
+#define lwip_md4_starts md4_starts
+#define lwip_md4_update md4_update
+#define lwip_md4_finish md4_finish
+#define lwip_md4_free(context)
+
+#include "netif/ppp/polarssl/md5.h"
+#define lwip_md5_context md5_context
+#define lwip_md5_init(context)
+#define lwip_md5_starts md5_starts
+#define lwip_md5_update md5_update
+#define lwip_md5_finish md5_finish
+#define lwip_md5_free(context)
+
+#include "netif/ppp/polarssl/sha1.h"
+#define lwip_sha1_context sha1_context
+#define lwip_sha1_init(context)
+#define lwip_sha1_starts sha1_starts
+#define lwip_sha1_update sha1_update
+#define lwip_sha1_finish sha1_finish
+#define lwip_sha1_free(context)
+
+#include "netif/ppp/polarssl/des.h"
+#define lwip_des_context des_context
+#define lwip_des_init(context)
+#define lwip_des_setkey_enc des_setkey_enc
+#define lwip_des_crypt_ecb des_crypt_ecb
+#define lwip_des_free(context)
+
+#include "netif/ppp/polarssl/arc4.h"
+#define lwip_arc4_context arc4_context
+#define lwip_arc4_init(context)
+#define lwip_arc4_setup arc4_setup
+#define lwip_arc4_crypt arc4_crypt
+#define lwip_arc4_free(context)
+
+#endif /* !LWIP_USE_EXTERNAL_MBEDTLS */
+
+/*
+ * Map hashes and ciphers functions to mbed TLS
+ */
+#if LWIP_USE_EXTERNAL_MBEDTLS
+
+#define lwip_md4_context mbedtls_md4_context
+#define lwip_md4_init mbedtls_md4_init
+#define lwip_md4_starts mbedtls_md4_starts
+#define lwip_md4_update mbedtls_md4_update
+#define lwip_md4_finish mbedtls_md4_finish
+#define lwip_md4_free mbedtls_md4_free
+
+#define lwip_md5_context mbedtls_md5_context
+#define lwip_md5_init mbedtls_md5_init
+#define lwip_md5_starts mbedtls_md5_starts
+#define lwip_md5_update mbedtls_md5_update
+#define lwip_md5_finish mbedtls_md5_finish
+#define lwip_md5_free mbedtls_md5_free
+
+#define lwip_sha1_context mbedtls_sha1_context
+#define lwip_sha1_init mbedtls_sha1_init
+#define lwip_sha1_starts mbedtls_sha1_starts
+#define lwip_sha1_update mbedtls_sha1_update
+#define lwip_sha1_finish mbedtls_sha1_finish
+#define lwip_sha1_free mbedtls_sha1_free
+
+#define lwip_des_context mbedtls_des_context
+#define lwip_des_init mbedtls_des_init
+#define lwip_des_setkey_enc mbedtls_des_setkey_enc
+#define lwip_des_crypt_ecb mbedtls_des_crypt_ecb
+#define lwip_des_free mbedtls_des_free
+
+#define lwip_arc4_context mbedtls_arc4_context
+#define lwip_arc4_init mbedtls_arc4_init
+#define lwip_arc4_setup mbedtls_arc4_setup
+#define lwip_arc4_crypt(context, buffer, length) mbedtls_arc4_crypt(context, length, buffer, buffer)
+#define lwip_arc4_free mbedtls_arc4_free
+
+#endif /* LWIP_USE_EXTERNAL_MBEDTLS */
+
+void pppcrypt_56_to_64_bit_key(u_char *key, u_char *des_key);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPCRYPT_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppdebug.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppdebug.h
new file mode 100644
index 000000000..36ee4f9bf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppdebug.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+*   Original.
+*
+*****************************************************************************
+*/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Trace levels. */
+#define LOG_CRITICAL  (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_ERR       (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
+#define LOG_NOTICE    (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_WARNING   (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
+#define LOG_INFO      (PPP_DEBUG)
+#define LOG_DETAIL    (PPP_DEBUG)
+#define LOG_DEBUG     (PPP_DEBUG)
+
+#if PPP_DEBUG
+
+#define MAINDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define SYSDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define FSMDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define LCPDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define IPCPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define IPV6CPDEBUG(a)  LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define UPAPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define CHAPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
+#define PPPDEBUG(a, b)  LWIP_DEBUGF(a, b)
+
+#else /* PPP_DEBUG */
+
+#define MAINDEBUG(a)
+#define SYSDEBUG(a)
+#define FSMDEBUG(a)
+#define LCPDEBUG(a)
+#define IPCPDEBUG(a)
+#define IPV6CPDEBUG(a)
+#define UPAPDEBUG(a)
+#define CHAPDEBUG(a)
+#define PPPDEBUG(a, b)
+
+#endif /* PPP_DEBUG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPDEBUG_H */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppoe.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppoe.h
new file mode 100644
index 000000000..08ab7ab54
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppoe.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* pppoe.h - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann <martin@NetBSD.org>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPP_OE_H
+#define PPP_OE_H
+
+#include "ppp.h"
+#include "lwip/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoehdr {
+  PACK_STRUCT_FLD_8(u8_t vertype);
+  PACK_STRUCT_FLD_8(u8_t code);
+  PACK_STRUCT_FIELD(u16_t session);
+  PACK_STRUCT_FIELD(u16_t plen);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppoetag {
+  PACK_STRUCT_FIELD(u16_t tag);
+  PACK_STRUCT_FIELD(u16_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+
+#define PPPOE_STATE_INITIAL   0
+#define PPPOE_STATE_PADI_SENT 1
+#define PPPOE_STATE_PADR_SENT 2
+#define PPPOE_STATE_SESSION   3
+/* passive */
+#define PPPOE_STATE_PADO_SENT 1
+
+#define PPPOE_HEADERLEN       sizeof(struct pppoehdr)
+#define PPPOE_VERTYPE         0x11    /* VER=1, TYPE = 1 */
+
+#define PPPOE_TAG_EOL         0x0000  /* end of list */
+#define PPPOE_TAG_SNAME       0x0101  /* service name */
+#define PPPOE_TAG_ACNAME      0x0102  /* access concentrator name */
+#define PPPOE_TAG_HUNIQUE     0x0103  /* host unique */
+#define PPPOE_TAG_ACCOOKIE    0x0104  /* AC cookie */
+#define PPPOE_TAG_VENDOR      0x0105  /* vendor specific */
+#define PPPOE_TAG_RELAYSID    0x0110  /* relay session id */
+#define PPPOE_TAG_SNAME_ERR   0x0201  /* service name error */
+#define PPPOE_TAG_ACSYS_ERR   0x0202  /* AC system error */
+#define PPPOE_TAG_GENERIC_ERR 0x0203  /* gerneric error */
+
+#define PPPOE_CODE_PADI       0x09    /* Active Discovery Initiation */
+#define PPPOE_CODE_PADO       0x07    /* Active Discovery Offer */
+#define PPPOE_CODE_PADR       0x19    /* Active Discovery Request */
+#define PPPOE_CODE_PADS       0x65    /* Active Discovery Session confirmation */
+#define PPPOE_CODE_PADT       0xA7    /* Active Discovery Terminate */
+
+#ifndef PPPOE_MAX_AC_COOKIE_LEN
+#define PPPOE_MAX_AC_COOKIE_LEN   64
+#endif
+
+struct pppoe_softc {
+  struct pppoe_softc *next;
+  struct netif *sc_ethif;      /* ethernet interface we are using */
+  ppp_pcb *pcb;                /* PPP PCB */
+
+  struct eth_addr sc_dest;     /* hardware address of concentrator */
+  u16_t sc_session;            /* PPPoE session id */
+  u8_t sc_state;               /* discovery phase or session connected */
+
+#ifdef PPPOE_TODO
+  u8_t *sc_service_name;       /* if != NULL: requested name of service */
+  u8_t *sc_concentrator_name;  /* if != NULL: requested concentrator id */
+#endif /* PPPOE_TODO */
+  u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */
+  u8_t sc_ac_cookie_len;       /* length of cookie data */
+#ifdef PPPOE_SERVER
+  u8_t *sc_hunique;            /* content of host unique we must echo back */
+  u8_t sc_hunique_len;         /* length of host unique */
+#endif
+  u8_t sc_padi_retried;        /* number of PADI retries already done */
+  u8_t sc_padr_retried;        /* number of PADR retries already done */
+};
+
+
+#define pppoe_init() /* compatibility define, no initialization needed */
+
+ppp_pcb *pppoe_create(struct netif *pppif,
+       struct netif *ethif,
+       const char *service_name, const char *concentrator_name,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+/*
+ * Functions called from lwIP
+ * DO NOT CALL FROM lwIP USER APPLICATION.
+ */
+void pppoe_disc_input(struct netif *netif, struct pbuf *p);
+void pppoe_data_input(struct netif *netif, struct pbuf *p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPP_OE_H */
+
+#endif /* PPP_SUPPORT && PPPOE_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppol2tp.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppol2tp.h
new file mode 100644
index 000000000..1221ca15b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppol2tp.h
@@ -0,0 +1,209 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Layer 2 Tunneling Protocol header file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPOL2TP_H
+#define PPPOL2TP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Timeout */
+#define PPPOL2TP_CONTROL_TIMEOUT         (5*1000)  /* base for quick timeout calculation */
+#define PPPOL2TP_SLOW_RETRY              (60*1000) /* persistent retry interval */
+
+#define PPPOL2TP_MAXSCCRQ                4         /* retry SCCRQ four times (quickly) */
+#define PPPOL2TP_MAXICRQ                 4         /* retry IRCQ four times */
+#define PPPOL2TP_MAXICCN                 4         /* retry ICCN four times */
+
+/* L2TP header flags */
+#define PPPOL2TP_HEADERFLAG_CONTROL      0x8000
+#define PPPOL2TP_HEADERFLAG_LENGTH       0x4000
+#define PPPOL2TP_HEADERFLAG_SEQUENCE     0x0800
+#define PPPOL2TP_HEADERFLAG_OFFSET       0x0200
+#define PPPOL2TP_HEADERFLAG_PRIORITY     0x0100
+#define PPPOL2TP_HEADERFLAG_VERSION      0x0002
+
+/* Mandatory bits for control: Control, Length, Sequence, Version 2 */
+#define PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY     (PPPOL2TP_HEADERFLAG_CONTROL|PPPOL2TP_HEADERFLAG_LENGTH|PPPOL2TP_HEADERFLAG_SEQUENCE|PPPOL2TP_HEADERFLAG_VERSION)
+/* Forbidden bits for control: Offset, Priority */
+#define PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN     (PPPOL2TP_HEADERFLAG_OFFSET|PPPOL2TP_HEADERFLAG_PRIORITY)
+
+/* Mandatory bits for data: Version 2 */
+#define PPPOL2TP_HEADERFLAG_DATA_MANDATORY        (PPPOL2TP_HEADERFLAG_VERSION)
+
+/* AVP (Attribute Value Pair) header */
+#define PPPOL2TP_AVPHEADERFLAG_MANDATORY  0x8000
+#define PPPOL2TP_AVPHEADERFLAG_HIDDEN     0x4000
+#define PPPOL2TP_AVPHEADERFLAG_LENGTHMASK 0x03ff
+
+/* -- AVP - Message type */
+#define PPPOL2TP_AVPTYPE_MESSAGE      0 /* Message type */
+
+/* Control Connection Management */
+#define PPPOL2TP_MESSAGETYPE_SCCRQ    1 /* Start Control Connection Request */
+#define PPPOL2TP_MESSAGETYPE_SCCRP    2 /* Start Control Connection Reply */
+#define PPPOL2TP_MESSAGETYPE_SCCCN    3 /* Start Control Connection Connected */
+#define PPPOL2TP_MESSAGETYPE_STOPCCN  4 /* Stop Control Connection Notification */
+#define PPPOL2TP_MESSAGETYPE_HELLO    6 /* Hello */
+/* Call Management */
+#define PPPOL2TP_MESSAGETYPE_OCRQ     7 /* Outgoing Call Request */
+#define PPPOL2TP_MESSAGETYPE_OCRP     8 /* Outgoing Call Reply */
+#define PPPOL2TP_MESSAGETYPE_OCCN     9 /* Outgoing Call Connected */
+#define PPPOL2TP_MESSAGETYPE_ICRQ    10 /* Incoming Call Request */
+#define PPPOL2TP_MESSAGETYPE_ICRP    11 /* Incoming Call Reply */
+#define PPPOL2TP_MESSAGETYPE_ICCN    12 /* Incoming Call Connected */
+#define PPPOL2TP_MESSAGETYPE_CDN     14 /* Call Disconnect Notify */
+/* Error reporting */
+#define PPPOL2TP_MESSAGETYPE_WEN     15 /* WAN Error Notify */
+/* PPP Session Control */
+#define PPPOL2TP_MESSAGETYPE_SLI     16 /* Set Link Info */
+
+/* -- AVP - Result code */
+#define PPPOL2TP_AVPTYPE_RESULTCODE   1 /* Result code */
+#define PPPOL2TP_RESULTCODE           1 /* General request to clear control connection */
+
+/* -- AVP - Protocol version (!= L2TP Header version) */
+#define PPPOL2TP_AVPTYPE_VERSION      2
+#define PPPOL2TP_VERSION         0x0100 /* L2TP Protocol version 1, revision 0 */
+
+/* -- AVP - Framing capabilities */
+#define PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES           3 /* Bearer capabilities */
+#define PPPOL2TP_FRAMINGCAPABILITIES          0x00000003 /* Async + Sync framing */
+
+/* -- AVP - Bearer capabilities */
+#define PPPOL2TP_AVPTYPE_BEARERCAPABILITIES           4 /* Bearer capabilities */
+#define PPPOL2TP_BEARERCAPABILITIES          0x00000003 /* Analog + Digital Access */
+
+/* -- AVP - Tie breaker */
+#define PPPOL2TP_AVPTYPE_TIEBREAKER   5
+
+/* -- AVP - Host name */
+#define PPPOL2TP_AVPTYPE_HOSTNAME     7 /* Host name */
+#define PPPOL2TP_HOSTNAME        "lwIP" /* FIXME: make it configurable */
+
+/* -- AVP - Vendor name */
+#define PPPOL2TP_AVPTYPE_VENDORNAME   8 /* Vendor name */
+#define PPPOL2TP_VENDORNAME      "lwIP" /* FIXME: make it configurable */
+
+/* -- AVP - Assign tunnel ID */
+#define PPPOL2TP_AVPTYPE_TUNNELID     9 /* Assign Tunnel ID */
+
+/* -- AVP - Receive window size */
+#define PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE  10 /* Receive window size */
+#define PPPOL2TP_RECEIVEWINDOWSIZE           8 /* FIXME: make it configurable */
+
+/* -- AVP - Challenge */
+#define PPPOL2TP_AVPTYPE_CHALLENGE   11 /* Challenge */
+
+/* -- AVP - Cause code */
+#define PPPOL2TP_AVPTYPE_CAUSECODE   12 /* Cause code*/
+
+/* -- AVP - Challenge response */
+#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE   13 /* Challenge response */
+#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE  16
+
+/* -- AVP - Assign session ID */
+#define PPPOL2TP_AVPTYPE_SESSIONID   14 /* Assign Session ID */
+
+/* -- AVP - Call serial number */
+#define PPPOL2TP_AVPTYPE_CALLSERIALNUMBER   15 /* Call Serial Number */
+
+/* -- AVP - Framing type */
+#define PPPOL2TP_AVPTYPE_FRAMINGTYPE         19 /* Framing Type */
+#define PPPOL2TP_FRAMINGTYPE         0x00000001 /* Sync framing */
+
+/* -- AVP - TX Connect Speed */
+#define PPPOL2TP_AVPTYPE_TXCONNECTSPEED      24 /* TX Connect Speed */
+#define PPPOL2TP_TXCONNECTSPEED       100000000 /* Connect speed: 100 Mbits/s */
+
+/* L2TP Session state */
+#define PPPOL2TP_STATE_INITIAL     0
+#define PPPOL2TP_STATE_SCCRQ_SENT  1
+#define PPPOL2TP_STATE_ICRQ_SENT   2
+#define PPPOL2TP_STATE_ICCN_SENT   3
+#define PPPOL2TP_STATE_DATA        4
+
+#define PPPOL2TP_OUTPUT_DATA_HEADER_LEN   6 /* Our data header len */
+
+/*
+ * PPPoL2TP interface control block.
+ */
+typedef struct pppol2tp_pcb_s pppol2tp_pcb;
+struct pppol2tp_pcb_s {
+  ppp_pcb *ppp;                /* PPP PCB */
+  u8_t phase;                  /* L2TP phase */
+  struct udp_pcb *udp;         /* UDP L2TP Socket */
+  struct netif *netif;         /* Output interface, used as a default route */
+  ip_addr_t remote_ip;         /* LNS IP Address */
+  u16_t remote_port;           /* LNS port */
+#if PPPOL2TP_AUTH_SUPPORT
+  const u8_t *secret;          /* Secret string */
+  u8_t secret_len;             /* Secret string length */
+  u8_t secret_rv[16];          /* Random vector */
+  u8_t challenge_hash[16];     /* Challenge response */
+  u8_t send_challenge;         /* Boolean whether the next sent packet should contains a challenge response */
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  u16_t tunnel_port;           /* Tunnel port */
+  u16_t our_ns;                /* NS to peer */
+  u16_t peer_nr;               /* NR from peer */
+  u16_t peer_ns;               /* Expected NS from peer */
+  u16_t source_tunnel_id;      /* Tunnel ID assigned by peer */
+  u16_t remote_tunnel_id;      /* Tunnel ID assigned to peer */
+  u16_t source_session_id;     /* Session ID assigned by peer */
+  u16_t remote_session_id;     /* Session ID assigned to peer */
+
+  u8_t sccrq_retried;          /* number of SCCRQ retries already done */
+  u8_t icrq_retried;           /* number of ICRQ retries already done */
+  u8_t iccn_retried;           /* number of ICCN retries already done */
+};
+
+
+/* Create a new L2TP session. */
+ppp_pcb *pppol2tp_create(struct netif *pppif,
+       struct netif *netif, const ip_addr_t *ipaddr, u16_t port,
+       const u8_t *secret, u8_t secret_len,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPOL2TP_H */
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppos.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppos.h
new file mode 100644
index 000000000..380a965ce
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/pppos.h
@@ -0,0 +1,126 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Serial header file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef PPPOS_H
+#define PPPOS_H
+
+#include "lwip/sys.h"
+
+#include "ppp.h"
+#include "vj.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+enum {
+  PDIDLE = 0,  /* Idle state - waiting. */
+  PDSTART,     /* Process start flag. */
+  PDADDRESS,   /* Process address field. */
+  PDCONTROL,   /* Process control field. */
+  PDPROTOCOL1, /* Process protocol field 1. */
+  PDPROTOCOL2, /* Process protocol field 2. */
+  PDDATA       /* Process data byte. */
+};
+
+/* PPPoS serial output callback function prototype */
+typedef u32_t (*pppos_output_cb_fn)(ppp_pcb *pcb, u8_t *data, u32_t len, void *ctx);
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u8_t ext_accm[32];
+
+/*
+ * PPPoS interface control block.
+ */
+typedef struct pppos_pcb_s pppos_pcb;
+struct pppos_pcb_s {
+  /* -- below are data that will NOT be cleared between two sessions */
+  ppp_pcb *ppp;                    /* PPP PCB */
+  pppos_output_cb_fn output_cb;    /* PPP serial output callback */
+
+  /* -- below are data that will be cleared between two sessions
+   *
+   * last_xmit must be the first member of cleared members, because it is
+   * used to know which part must not be cleared.
+   */
+  u32_t last_xmit;                 /* Time of last transmission. */
+  ext_accm out_accm;               /* Async-Ctl-Char-Map for output. */
+
+  /* flags */
+  unsigned int open            :1; /* Set if PPPoS is open */
+  unsigned int pcomp           :1; /* Does peer accept protocol compression? */
+  unsigned int accomp          :1; /* Does peer accept addr/ctl compression? */
+
+  /* PPPoS rx */
+  ext_accm in_accm;                /* Async-Ctl-Char-Map for input. */
+  struct pbuf *in_head, *in_tail;  /* The input packet. */
+  u16_t in_protocol;               /* The input protocol code. */
+  u16_t in_fcs;                    /* Input Frame Check Sequence value. */
+  u8_t in_state;                   /* The input process state. */
+  u8_t in_escaped;                 /* Escape next character. */
+};
+
+/* Create a new PPPoS session. */
+ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
+
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+/* Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread. */
+err_t pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l);
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+/* PPP over Serial: this is the input function to be called for received data. */
+void pppos_input(ppp_pcb *ppp, u8_t* data, int len);
+
+
+/*
+ * Functions called from lwIP
+ * DO NOT CALL FROM lwIP USER APPLICATION.
+ */
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+err_t pppos_input_sys(struct pbuf *p, struct netif *inp);
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PPPOS_H */
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/upap.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/upap.h
new file mode 100644
index 000000000..540d98149
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/upap.h
@@ -0,0 +1,131 @@
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: upap.h,v 1.8 2002/12/04 23:03:33 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#ifndef UPAP_H
+#define UPAP_H
+
+#include "ppp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN	4
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ	1	/* Authenticate-Request */
+#define UPAP_AUTHACK	2	/* Authenticate-Ack */
+#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
+
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL	0	/* Connection down */
+#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN	4	/* We've received an Ack */
+#define UPAPCS_BADAUTH	5	/* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL	0	/* Connection down */
+#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
+#define UPAPSS_OPEN	4	/* We've sent an Ack */
+#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
+
+
+/*
+ * Timeouts.
+ */
+#if 0 /* moved to ppp_opts.h */
+#define UPAP_DEFTIMEOUT	3	/* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME	30	/* Time to wait for auth-req from peer */
+#endif /* moved to ppp_opts.h */
+
+/*
+ * Each interface is described by upap structure.
+ */
+#if PAP_SUPPORT
+typedef struct upap_state {
+    const char *us_user;	/* User */
+    u8_t us_userlen;		/* User length */
+    const char *us_passwd;	/* Password */
+    u8_t us_passwdlen;		/* Password length */
+    u8_t us_clientstate;	/* Client state */
+#if PPP_SERVER
+    u8_t us_serverstate;	/* Server state */
+#endif /* PPP_SERVER */
+    u8_t us_id;		        /* Current id */
+    u8_t us_transmits;		/* Number of auth-reqs sent */
+} upap_state;
+#endif /* PAP_SUPPORT */
+
+
+void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password);
+#if PPP_SERVER
+void upap_authpeer(ppp_pcb *pcb);
+#endif /* PPP_SERVER */
+
+extern const struct protent pap_protent;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UPAP_H */
+#endif /* PPP_SUPPORT && PAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/vj.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/vj.h
new file mode 100644
index 000000000..77d9976c5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/ppp/vj.h
@@ -0,0 +1,169 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ * - Initial distribution.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "lwip/ip.h"
+#include "lwip/priv/tcp_priv.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_SLOTS 16 /* must be > 2 and < 256 */
+#define MAX_HDR   128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ *
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP               0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP   0x80
+#define TYPE_ERROR            0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C 0x40 /* flag bits for what changed in a packet */
+#define NEW_I 0x20
+#define NEW_S 0x08
+#define NEW_A 0x04
+#define NEW_W 0x02
+#define NEW_U 0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+  struct cstate *cs_next; /* next most recently used state (xmit only) */
+  u16_t cs_hlen;        /* size of hdr (receive only) */
+  u8_t cs_id;           /* connection # associated with this state */
+  u8_t cs_filler;
+  union {
+    char csu_hdr[MAX_HDR];
+    struct ip_hdr csu_ip;     /* ip/tcp hdr from most recent packet */
+  } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+  u32_t vjs_packets;        /* outbound packets */
+  u32_t vjs_compressed;     /* outbound compressed packets */
+  u32_t vjs_searches;       /* searches for connection state */
+  u32_t vjs_misses;         /* times couldn't find conn. state */
+  u32_t vjs_uncompressedin; /* inbound uncompressed packets */
+  u32_t vjs_compressedin;   /* inbound compressed packets */
+  u32_t vjs_errorin;        /* inbound unknown type packets */
+  u32_t vjs_tossed;         /* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+  struct cstate *last_cs;          /* most recently used tstate */
+  u8_t last_recv;                /* last rcvd conn. id */
+  u8_t last_xmit;                /* last sent conn. id */
+  u16_t flags;
+  u8_t maxSlotIndex;
+  u8_t compressSlot;             /* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+  struct vjstat stats;
+#endif
+  struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
+  struct cstate rstate[MAX_SLOTS]; /* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init    (struct vjcompress *comp);
+extern u8_t  vj_compress_tcp     (struct vjcompress *comp, struct pbuf **pb);
+extern void  vj_uncompress_err   (struct vjcompress *comp);
+extern int   vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int   vj_uncompress_tcp   (struct pbuf **nb, struct vjcompress *comp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* VJ_H */
+
+#endif /* PPP_SUPPORT && VJ_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/slipif.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/slipif.h
new file mode 100644
index 000000000..65ba31f83
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/slipif.h
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * SLIP netif API
+ */
+
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef LWIP_HDR_NETIF_SLIPIF_H
+#define LWIP_HDR_NETIF_SLIPIF_H
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+
+/** Set this to 1 to start a thread that blocks reading on the serial line
+ * (using sio_read()).
+ */
+#ifndef SLIP_USE_RX_THREAD
+#define SLIP_USE_RX_THREAD !NO_SYS
+#endif
+
+/** Set this to 1 to enable functions to pass in RX bytes from ISR context.
+ * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled
+ * packets on a queue, which is fed into lwIP from slipif_poll().
+ * If disabled, slipif_poll() polls the serial line (using sio_tryread()).
+ */
+#ifndef SLIP_RX_FROM_ISR
+#define SLIP_RX_FROM_ISR 0
+#endif
+
+/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets
+ * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available.
+ * If disabled, packets will be dropped if more than one packet is received.
+ */
+#ifndef SLIP_RX_QUEUE
+#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t slipif_init(struct netif * netif);
+void slipif_poll(struct netif *netif);
+#if SLIP_RX_FROM_ISR
+void slipif_process_rxqueue(struct netif *netif);
+void slipif_received_byte(struct netif *netif, u8_t data);
+void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len);
+#endif /* SLIP_RX_FROM_ISR */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_NETIF_SLIPIF_H */
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/zepif.h b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/zepif.h
new file mode 100644
index 000000000..2a801b4c4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/include/netif/zepif.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * A netif implementing the ZigBee Eencapsulation Protocol (ZEP).
+ * This is used to tunnel 6LowPAN over UDP.
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#ifndef LWIP_HDR_ZEPIF_H
+#define LWIP_HDR_ZEPIF_H
+
+#include "lwip/opt.h"
+#include "netif/lowpan6.h"
+
+#if LWIP_IPV6 && LWIP_UDP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ZEPIF_DEFAULT_UDP_PORT  17754
+
+/** Pass this struct as 'state' to netif_add to control the behaviour
+ * of this netif. If NULL is passed, default behaviour is chosen */
+struct zepif_init {
+  /** The UDP port used to ZEP frames from (0 = default) */
+  u16_t               zep_src_udp_port;
+  /** The UDP port used to ZEP frames to (0 = default) */
+  u16_t               zep_dst_udp_port;
+  /** The IP address to sed ZEP frames from (NULL = ANY) */
+  const ip_addr_t    *zep_src_ip_addr;
+  /** The IP address to sed ZEP frames to (NULL = BROADCAST) */
+  const ip_addr_t    *zep_dst_ip_addr;
+  /** If != NULL, the udp pcb is bound to this netif */
+  const struct netif *zep_netif;
+  /** MAC address of the 6LowPAN device */
+  u8_t                addr[6];
+};
+
+err_t zepif_init(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_IPV6 && LWIP_UDP */
+
+#endif /* LWIP_HDR_ZEPIF_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/bridgeif.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/bridgeif.c
new file mode 100644
index 000000000..8a97bce39
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/bridgeif.c
@@ -0,0 +1,563 @@
+/**
+ * @file
+ * lwIP netif implementing an IEEE 802.1D MAC Bridge
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+/**
+ * @defgroup bridgeif IEEE 802.1D bridge
+ * @ingroup netifs
+ * This file implements an IEEE 802.1D bridge by using a multilayer netif approach
+ * (one hardware-independent netif for the bridge that uses hardware netifs for its ports).
+ * On transmit, the bridge selects the outgoing port(s).
+ * On receive, the port netif calls into the bridge (via its netif->input function) and
+ * the bridge selects the port(s) (and/or its netif->input function) to pass the received pbuf to.
+ *
+ * Usage:
+ * - add the port netifs just like you would when using them as dedicated netif without a bridge
+ *   - only NETIF_FLAG_ETHARP/NETIF_FLAG_ETHERNET netifs are supported as bridge ports
+ *   - add the bridge port netifs without IPv4 addresses (i.e. pass 'NULL, NULL, NULL')
+ *   - don't add IPv6 addresses to the port netifs!
+ * - set up the bridge configuration in a global variable of type 'bridgeif_initdata_t' that contains
+ *   - the MAC address of the bridge
+ *   - some configuration options controlling the memory consumption (maximum number of ports
+ *     and FDB entries)
+ *   - e.g. for a bridge MAC address 00-01-02-03-04-05, 2 bridge ports, 1024 FDB entries + 16 static MAC entries:
+ *     bridgeif_initdata_t mybridge_initdata = BRIDGEIF_INITDATA1(2, 1024, 16, ETH_ADDR(0, 1, 2, 3, 4, 5));
+ * - add the bridge netif (with IPv4 config):
+ *   struct netif bridge_netif;
+ *   netif_add(&bridge_netif, &my_ip, &my_netmask, &my_gw, &mybridge_initdata, bridgeif_init, tcpip_input);
+ *   NOTE: the passed 'input' function depends on BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT setting,
+ *         which controls where the forwarding is done (netif low level input context vs. tcpip_thread)
+ * - set up all ports netifs and the bridge netif
+ *
+ * - When adding a port netif, NETIF_FLAG_ETHARP flag will be removed from a port
+ *   to prevent ETHARP working on that port netif (we only want one IP per bridge not per port).
+ * - When adding a port netif, its input function is changed to call into the bridge.
+ *
+ *
+ * @todo:
+ * - compact static FDB entries (instead of walking the whole array)
+ * - add FDB query/read access
+ * - add FDB change callback (when learning or dropping auto-learned entries)
+ * - prefill FDB with MAC classes that should never be forwarded
+ * - multicast snooping? (and only forward group addresses to interested ports)
+ * - support removing ports
+ * - check SNMP integration
+ * - VLAN handling / trunk ports
+ * - priority handling? (although that largely depends on TX queue limitations and lwIP doesn't provide tx-done handling)
+ */
+
+#include "netif/bridgeif.h"
+#include "lwip/netif.h"
+#include "lwip/sys.h"
+#include "lwip/etharp.h"
+#include "lwip/ethip6.h"
+#include "lwip/snmp.h"
+#include "lwip/timeouts.h"
+#include <string.h>
+
+#if LWIP_NUM_NETIF_CLIENT_DATA
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'b'
+#define IFNAME1 'r'
+
+struct bridgeif_private_s;
+typedef struct bridgeif_port_private_s {
+  struct bridgeif_private_s *bridge;
+  struct netif *port_netif;
+  u8_t port_num;
+} bridgeif_port_t;
+
+typedef struct bridgeif_fdb_static_entry_s {
+  u8_t used;
+  bridgeif_portmask_t dst_ports;
+  struct eth_addr addr;
+} bridgeif_fdb_static_entry_t;
+
+typedef struct bridgeif_private_s {
+  struct netif     *netif;
+  struct eth_addr   ethaddr;
+  u8_t              max_ports;
+  u8_t              num_ports;
+  bridgeif_port_t  *ports;
+  u16_t             max_fdbs_entries;
+  bridgeif_fdb_static_entry_t *fdbs;
+  u16_t             max_fdbd_entries;
+  void             *fdbd;
+} bridgeif_private_t;
+
+/* netif data index to get the bridge on input */
+u8_t bridgeif_netif_client_id = 0xff;
+
+/**
+ * @ingroup bridgeif
+ * Add a static entry to the forwarding database.
+ * A static entry marks where frames to a specific eth address (unicast or group address) are
+ * forwarded.
+ * bits [0..(BRIDGEIF_MAX_PORTS-1)]: hw ports
+ * bit [BRIDGEIF_MAX_PORTS]: cpu port
+ * 0: drop
+ */
+err_t
+bridgeif_fdb_add(struct netif *bridgeif, const struct eth_addr *addr, bridgeif_portmask_t ports)
+{
+  int i;
+  bridgeif_private_t *br;
+  BRIDGEIF_DECL_PROTECT(lev);
+  LWIP_ASSERT("invalid netif", bridgeif != NULL);
+  br = (bridgeif_private_t *)bridgeif->state;
+  LWIP_ASSERT("invalid state", br != NULL);
+
+  BRIDGEIF_READ_PROTECT(lev);
+  for (i = 0; i < br->max_fdbs_entries; i++) {
+    if (!br->fdbs[i].used) {
+      BRIDGEIF_WRITE_PROTECT(lev);
+      if (!br->fdbs[i].used) {
+        br->fdbs[i].used = 1;
+        br->fdbs[i].dst_ports = ports;
+        memcpy(&br->fdbs[i].addr, addr, sizeof(struct eth_addr));
+        BRIDGEIF_WRITE_UNPROTECT(lev);
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return ERR_OK;
+      }
+      BRIDGEIF_WRITE_UNPROTECT(lev);
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  return ERR_MEM;
+}
+
+/**
+ * @ingroup bridgeif
+ * Remove a static entry from the forwarding database
+ */
+err_t
+bridgeif_fdb_remove(struct netif *bridgeif, const struct eth_addr *addr)
+{
+  int i;
+  bridgeif_private_t *br;
+  BRIDGEIF_DECL_PROTECT(lev);
+  LWIP_ASSERT("invalid netif", bridgeif != NULL);
+  br = (bridgeif_private_t *)bridgeif->state;
+  LWIP_ASSERT("invalid state", br != NULL);
+
+  BRIDGEIF_READ_PROTECT(lev);
+  for (i = 0; i < br->max_fdbs_entries; i++) {
+    if (br->fdbs[i].used && !memcmp(&br->fdbs[i].addr, addr, sizeof(struct eth_addr))) {
+      BRIDGEIF_WRITE_PROTECT(lev);
+      if (br->fdbs[i].used && !memcmp(&br->fdbs[i].addr, addr, sizeof(struct eth_addr))) {
+        memset(&br->fdbs[i], 0, sizeof(bridgeif_fdb_static_entry_t));
+        BRIDGEIF_WRITE_UNPROTECT(lev);
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return ERR_OK;
+      }
+      BRIDGEIF_WRITE_UNPROTECT(lev);
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  return ERR_VAL;
+}
+
+/** Get the forwarding port(s) (as bit mask) for the specified destination mac address */
+static bridgeif_portmask_t
+bridgeif_find_dst_ports(bridgeif_private_t *br, struct eth_addr *dst_addr)
+{
+  int i;
+  BRIDGEIF_DECL_PROTECT(lev);
+  BRIDGEIF_READ_PROTECT(lev);
+  /* first check for static entries */
+  for (i = 0; i < br->max_fdbs_entries; i++) {
+    if (br->fdbs[i].used) {
+      if (!memcmp(&br->fdbs[i].addr, dst_addr, sizeof(struct eth_addr))) {
+        bridgeif_portmask_t ret = br->fdbs[i].dst_ports;
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return ret;
+      }
+    }
+  }
+  if (dst_addr->addr[0] & 1) {
+    /* no match found: flood remaining group address */
+    BRIDGEIF_READ_UNPROTECT(lev);
+    return BR_FLOOD;
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  /* no match found: check dynamic fdb for port or fall back to flooding */
+  return bridgeif_fdb_get_dst_ports(br->fdbd, dst_addr);
+}
+
+/** Helper function to see if a destination mac belongs to the bridge
+ * (bridge netif or one of the port netifs), in which case the frame
+ * is sent to the cpu only.
+ */
+static int
+bridgeif_is_local_mac(bridgeif_private_t *br, struct eth_addr *addr)
+{
+  int i;
+  BRIDGEIF_DECL_PROTECT(lev);
+  if (!memcmp(br->netif->hwaddr, addr, sizeof(struct eth_addr))) {
+    return 1;
+  }
+  BRIDGEIF_READ_PROTECT(lev);
+  for (i = 0; i < br->num_ports; i++) {
+    struct netif *portif = br->ports[i].port_netif;
+    if (portif != NULL) {
+      if (!memcmp(portif->hwaddr, addr, sizeof(struct eth_addr))) {
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return 1;
+      }
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  return 0;
+}
+
+/* Output helper function */
+static err_t
+bridgeif_send_to_port(bridgeif_private_t *br, struct pbuf *p, u8_t dstport_idx)
+{
+  if (dstport_idx < BRIDGEIF_MAX_PORTS) {
+    /* possibly an external port */
+    if (dstport_idx < br->max_ports) {
+      struct netif *portif = br->ports[dstport_idx].port_netif;
+      if ((portif != NULL) && (portif->linkoutput != NULL)) {
+        /* prevent sending out to rx port */
+        if (netif_get_index(portif) != p->if_idx) {
+          if (netif_is_link_up(portif)) {
+            LWIP_DEBUGF(BRIDGEIF_FW_DEBUG, ("br -> flood(%p:%d) -> %d\n", (void *)p, p->if_idx, netif_get_index(portif)));
+            return portif->linkoutput(portif, p);
+          }
+        }
+      }
+    }
+  } else {
+    LWIP_ASSERT("invalid port index", dstport_idx == BRIDGEIF_MAX_PORTS);
+  }
+  return ERR_OK;
+}
+
+/** Helper function to pass a pbuf to all ports marked in 'dstports'
+ */
+static err_t
+bridgeif_send_to_ports(bridgeif_private_t *br, struct pbuf *p, bridgeif_portmask_t dstports)
+{
+  err_t err, ret_err = ERR_OK;
+  u8_t i;
+  bridgeif_portmask_t mask = 1;
+  BRIDGEIF_DECL_PROTECT(lev);
+  BRIDGEIF_READ_PROTECT(lev);
+  for (i = 0; i < BRIDGEIF_MAX_PORTS; i++, mask = (bridgeif_portmask_t)(mask << 1)) {
+    if (dstports & mask) {
+      err = bridgeif_send_to_port(br, p, i);
+      if (err != ERR_OK) {
+        ret_err = err;
+      }
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  return ret_err;
+}
+
+/** Output function of the application port of the bridge (the one with an ip address).
+ * The forwarding port(s) where this pbuf is sent on is/are automatically selected
+ * from the FDB.
+ */
+static err_t
+bridgeif_output(struct netif *netif, struct pbuf *p)
+{
+  err_t err;
+  bridgeif_private_t *br = (bridgeif_private_t *)netif->state;
+  struct eth_addr *dst = (struct eth_addr *)(p->payload);
+
+  bridgeif_portmask_t dstports = bridgeif_find_dst_ports(br, dst);
+  err = bridgeif_send_to_ports(br, p, dstports);
+
+  MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len);
+  if (((u8_t *)p->payload)[0] & 1) {
+    /* broadcast or multicast packet*/
+    MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts);
+  } else {
+    /* unicast packet */
+    MIB2_STATS_NETIF_INC(netif, ifoutucastpkts);
+  }
+  /* increase ifoutdiscards or ifouterrors on error */
+
+  LINK_STATS_INC(link.xmit);
+
+  return err;
+}
+
+/** The actual bridge input function. Port netif's input is changed to call
+ * here. This function decides where the frame is forwarded.
+ */
+static err_t
+bridgeif_input(struct pbuf *p, struct netif *netif)
+{
+  u8_t rx_idx;
+  bridgeif_portmask_t dstports;
+  struct eth_addr *src, *dst;
+  bridgeif_private_t *br;
+  bridgeif_port_t *port;
+  if (p == NULL || netif == NULL) {
+    return ERR_VAL;
+  }
+  port = (bridgeif_port_t *)netif_get_client_data(netif, bridgeif_netif_client_id);
+  LWIP_ASSERT("port data not set", port != NULL);
+  if (port == NULL || port->bridge == NULL) {
+    return ERR_VAL;
+  }
+  br = (bridgeif_private_t *)port->bridge;
+  rx_idx = netif_get_index(netif);
+  /* store receive index in pbuf */
+  p->if_idx = rx_idx;
+
+  dst = (struct eth_addr *)p->payload;
+  src = (struct eth_addr *)(((u8_t *)p->payload) + sizeof(struct eth_addr));
+
+  if ((src->addr[0] & 1) == 0) {
+    /* update src for all non-group addresses */
+    bridgeif_fdb_update_src(br->fdbd, src, port->port_num);
+  }
+
+  if (dst->addr[0] & 1) {
+    /* group address -> flood + cpu? */
+    dstports = bridgeif_find_dst_ports(br, dst);
+    bridgeif_send_to_ports(br, p, dstports);
+    if (dstports & (1 << BRIDGEIF_MAX_PORTS)) {
+      /* we pass the reference to ->input or have to free it */
+      LWIP_DEBUGF(BRIDGEIF_FW_DEBUG, ("br -> input(%p)\n", (void *)p));
+      if (br->netif->input(p, br->netif) != ERR_OK) {
+        pbuf_free(p);
+      }
+    } else {
+      /* all references done */
+      pbuf_free(p);
+    }
+    /* always return ERR_OK here to prevent the caller freeing the pbuf */
+    return ERR_OK;
+  } else {
+    /* is this for one of the local ports? */
+    if (bridgeif_is_local_mac(br, dst)) {
+      /* yes, send to cpu port only */
+      LWIP_DEBUGF(BRIDGEIF_FW_DEBUG, ("br -> input(%p)\n", (void *)p));
+      return br->netif->input(p, br->netif);
+    }
+
+    /* get dst port */
+    dstports = bridgeif_find_dst_ports(br, dst);
+    bridgeif_send_to_ports(br, p, dstports);
+    /* no need to send to cpu, flooding is for external ports only */
+    /* by  this, we consumed the pbuf */
+    pbuf_free(p);
+    /* always return ERR_OK here to prevent the caller freeing the pbuf */
+    return ERR_OK;
+  }
+}
+
+#if !BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+/** Input function for port netifs used to synchronize into tcpip_thread.
+ */
+static err_t
+bridgeif_tcpip_input(struct pbuf *p, struct netif *netif)
+{
+  return tcpip_inpkt(p, netif, bridgeif_input);
+}
+#endif /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */
+
+/**
+ * @ingroup bridgeif
+ * Initialization function passed to netif_add().
+ *
+ * ATTENTION: A pointer to a @ref bridgeif_initdata_t must be passed as 'state'
+ *            to @ref netif_add when adding the bridge. I supplies MAC address
+ *            and controls memory allocation (number of ports, FDB size).
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t
+bridgeif_init(struct netif *netif)
+{
+  bridgeif_initdata_t *init_data;
+  bridgeif_private_t *br;
+  size_t alloc_len_sizet;
+  mem_size_t alloc_len;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("bridgeif needs an input callback", (netif->input != NULL));
+#if !BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+  if (netif->input == tcpip_input) {
+    LWIP_DEBUGF(BRIDGEIF_DEBUG | LWIP_DBG_ON, ("bridgeif does not need tcpip_input, use netif_input/ethernet_input instead"));
+  }
+#endif
+
+  if (bridgeif_netif_client_id == 0xFF) {
+    bridgeif_netif_client_id = netif_alloc_client_data_id();
+  }
+
+  init_data = (bridgeif_initdata_t *)netif->state;
+  LWIP_ASSERT("init_data != NULL", (init_data != NULL));
+  LWIP_ASSERT("init_data->max_ports <= BRIDGEIF_MAX_PORTS",
+              init_data->max_ports <= BRIDGEIF_MAX_PORTS);
+
+  alloc_len_sizet = sizeof(bridgeif_private_t) + (init_data->max_ports * sizeof(bridgeif_port_t) + (init_data->max_fdb_static_entries * sizeof(bridgeif_fdb_static_entry_t)));
+  alloc_len = (mem_size_t)alloc_len_sizet;
+  LWIP_ASSERT("alloc_len == alloc_len_sizet", alloc_len == alloc_len_sizet);
+  LWIP_DEBUGF(BRIDGEIF_DEBUG, ("bridgeif_init: allocating %d bytes for private data\n", (int)alloc_len));
+  br = (bridgeif_private_t *)mem_calloc(1, alloc_len);
+  if (br == NULL) {
+    LWIP_DEBUGF(NETIF_DEBUG, ("bridgeif_init: out of memory\n"));
+    return ERR_MEM;
+  }
+  memcpy(&br->ethaddr, &init_data->ethaddr, sizeof(br->ethaddr));
+  br->netif = netif;
+
+  br->max_ports = init_data->max_ports;
+  br->ports = (bridgeif_port_t *)(br + 1);
+
+  br->max_fdbs_entries = init_data->max_fdb_static_entries;
+  br->fdbs = (bridgeif_fdb_static_entry_t *)(((u8_t *)(br + 1)) + (init_data->max_ports * sizeof(bridgeif_port_t)));
+
+  br->max_fdbd_entries = init_data->max_fdb_dynamic_entries;
+  br->fdbd = bridgeif_fdb_init(init_data->max_fdb_dynamic_entries);
+  if (br->fdbd == NULL) {
+    LWIP_DEBUGF(NETIF_DEBUG, ("bridgeif_init: out of memory in fdb_init\n"));
+    mem_free(br);
+    return ERR_MEM;
+  }
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+  netif->hostname = "lwip";
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 0);
+
+  netif->state = br;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  /* We directly use etharp_output() here to save a function call.
+   * You can instead declare your own function an call etharp_output()
+   * from it if you have to do some checks before sending (e.g. if link
+   * is available...) */
+#if LWIP_IPV4
+  netif->output = etharp_output;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  netif->output_ip6 = ethip6_output;
+#endif /* LWIP_IPV6 */
+  netif->linkoutput = bridgeif_output;
+
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETH_HWADDR_LEN;
+
+  /* set MAC hardware address */
+  memcpy(netif->hwaddr, &br->ethaddr, ETH_HWADDR_LEN);
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+
+  /* device capabilities */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP | NETIF_FLAG_MLD6 | NETIF_FLAG_LINK_UP;
+
+#if LWIP_IPV6 && LWIP_IPV6_MLD
+  /*
+   * For hardware/netifs that implement MAC filtering.
+   * All-nodes link-local is handled by default, so we must let the hardware know
+   * to allow multicast packets in.
+   * Should set mld_mac_filter previously. */
+  if (netif->mld_mac_filter != NULL) {
+    ip6_addr_t ip6_allnodes_ll;
+    ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll);
+    netif->mld_mac_filter(netif, &ip6_allnodes_ll, NETIF_ADD_MAC_FILTER);
+  }
+#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
+
+  return ERR_OK;
+}
+
+/**
+ * @ingroup bridgeif
+ * Add a port to the bridge
+ */
+err_t
+bridgeif_add_port(struct netif *bridgeif, struct netif *portif)
+{
+  bridgeif_private_t *br;
+  bridgeif_port_t *port;
+
+  LWIP_ASSERT("bridgeif != NULL", bridgeif != NULL);
+  LWIP_ASSERT("bridgeif->state != NULL", bridgeif->state != NULL);
+  LWIP_ASSERT("portif != NULL", portif != NULL);
+
+  if (!(portif->flags & NETIF_FLAG_ETHARP) || !(portif->flags & NETIF_FLAG_ETHERNET)) {
+    /* can only add ETHERNET/ETHARP interfaces */
+    return ERR_VAL;
+  }
+
+  br = (bridgeif_private_t *)bridgeif->state;
+
+  if (br->num_ports >= br->max_ports) {
+    return ERR_VAL;
+  }
+  port = &br->ports[br->num_ports];
+  port->port_netif = portif;
+  port->port_num = br->num_ports;
+  port->bridge = br;
+  br->num_ports++;
+
+  /* let the port call us on input */
+#if BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT
+  portif->input = bridgeif_input;
+#else
+  portif->input = bridgeif_tcpip_input;
+#endif
+  /* store pointer to bridge in netif */
+  netif_set_client_data(portif, bridgeif_netif_client_id, port);
+  /* remove ETHARP flag to prevent sending report events on netif-up */
+  netif_clear_flags(portif, NETIF_FLAG_ETHARP);
+
+  return ERR_OK;
+}
+
+#endif /* LWIP_NUM_NETIF_CLIENT_DATA */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/bridgeif_fdb.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/bridgeif_fdb.c
new file mode 100644
index 000000000..6739fc247
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/bridgeif_fdb.c
@@ -0,0 +1,212 @@
+/**
+ * @file
+ * lwIP netif implementing an FDB for IEEE 802.1D MAC Bridge
+ */
+
+/*
+ * Copyright (c) 2017 Simon Goldschmidt.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+/**
+ * @defgroup bridgeif_fdb FDB example code
+ * @ingroup bridgeif
+ * This file implements an example for an FDB (Forwarding DataBase)
+ */
+
+#include "netif/bridgeif.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/timeouts.h"
+#include <string.h>
+
+#define BRIDGEIF_AGE_TIMER_MS 1000
+
+#define BR_FDB_TIMEOUT_SEC  (60*5) /* 5 minutes FDB timeout */
+
+typedef struct bridgeif_dfdb_entry_s {
+  u8_t used;
+  u8_t port;
+  u32_t ts;
+  struct eth_addr addr;
+} bridgeif_dfdb_entry_t;
+
+typedef struct bridgeif_dfdb_s {
+  u16_t max_fdb_entries;
+  bridgeif_dfdb_entry_t *fdb;
+} bridgeif_dfdb_t;
+
+/**
+ * @ingroup bridgeif_fdb
+ * A real simple and slow implementation of an auto-learning forwarding database that
+ * remembers known src mac addresses to know which port to send frames destined for that
+ * mac address.
+ *
+ * ATTENTION: This is meant as an example only, in real-world use, you should 
+ * provide a better implementation :-)
+ */
+void
+bridgeif_fdb_update_src(void *fdb_ptr, struct eth_addr *src_addr, u8_t port_idx)
+{
+  int i;
+  bridgeif_dfdb_t *fdb = (bridgeif_dfdb_t *)fdb_ptr;
+  BRIDGEIF_DECL_PROTECT(lev);
+  BRIDGEIF_READ_PROTECT(lev);
+  for (i = 0; i < fdb->max_fdb_entries; i++) {
+    bridgeif_dfdb_entry_t *e = &fdb->fdb[i];
+    if (e->used && e->ts) {
+      if (!memcmp(&e->addr, src_addr, sizeof(struct eth_addr))) {
+        LWIP_DEBUGF(BRIDGEIF_FDB_DEBUG, ("br: update src %02x:%02x:%02x:%02x:%02x:%02x (from %d) @ idx %d\n",
+                                         src_addr->addr[0], src_addr->addr[1], src_addr->addr[2], src_addr->addr[3], src_addr->addr[4], src_addr->addr[5],
+                                         port_idx, i));
+        BRIDGEIF_WRITE_PROTECT(lev);
+        e->ts = BR_FDB_TIMEOUT_SEC;
+        e->port = port_idx;
+        BRIDGEIF_WRITE_UNPROTECT(lev);
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return;
+      }
+    }
+  }
+  /* not found, allocate new entry from free */
+  for (i = 0; i < fdb->max_fdb_entries; i++) {
+    bridgeif_dfdb_entry_t *e = &fdb->fdb[i];
+    if (!e->used || !e->ts) {
+      BRIDGEIF_WRITE_PROTECT(lev);
+      /* check again when protected */
+      if (!e->used || !e->ts) {
+        LWIP_DEBUGF(BRIDGEIF_FDB_DEBUG, ("br: create src %02x:%02x:%02x:%02x:%02x:%02x (from %d) @ idx %d\n",
+                                         src_addr->addr[0], src_addr->addr[1], src_addr->addr[2], src_addr->addr[3], src_addr->addr[4], src_addr->addr[5],
+                                         port_idx, i));
+        memcpy(&e->addr, src_addr, sizeof(struct eth_addr));
+        e->ts = BR_FDB_TIMEOUT_SEC;
+        e->port = port_idx;
+        e->used = 1;
+        BRIDGEIF_WRITE_UNPROTECT(lev);
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return;
+      }
+      BRIDGEIF_WRITE_UNPROTECT(lev);
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  /* not found, no free entry -> flood */
+}
+
+/** 
+ * @ingroup bridgeif_fdb
+ * Walk our list of auto-learnt fdb entries and return a port to forward or BR_FLOOD if unknown 
+ */
+bridgeif_portmask_t
+bridgeif_fdb_get_dst_ports(void *fdb_ptr, struct eth_addr *dst_addr)
+{
+  int i;
+  bridgeif_dfdb_t *fdb = (bridgeif_dfdb_t *)fdb_ptr;
+  BRIDGEIF_DECL_PROTECT(lev);
+  BRIDGEIF_READ_PROTECT(lev);
+  for (i = 0; i < fdb->max_fdb_entries; i++) {
+    bridgeif_dfdb_entry_t *e = &fdb->fdb[i];
+    if (e->used && e->ts) {
+      if (!memcmp(&e->addr, dst_addr, sizeof(struct eth_addr))) {
+        bridgeif_portmask_t ret = (bridgeif_portmask_t)(1 << e->port);
+        BRIDGEIF_READ_UNPROTECT(lev);
+        return ret;
+      }
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+  return BR_FLOOD;
+}
+
+/**
+ * @ingroup bridgeif_fdb
+ * Aging implementation of our simple fdb
+ */
+static void
+bridgeif_fdb_age_one_second(void *fdb_ptr)
+{
+  int i;
+  bridgeif_dfdb_t *fdb;
+  BRIDGEIF_DECL_PROTECT(lev);
+
+  fdb = (bridgeif_dfdb_t *)fdb_ptr;
+  BRIDGEIF_READ_PROTECT(lev);
+
+  for (i = 0; i < fdb->max_fdb_entries; i++) {
+    bridgeif_dfdb_entry_t *e = &fdb->fdb[i];
+    if (e->used && e->ts) {
+      BRIDGEIF_WRITE_PROTECT(lev);
+      /* check again when protected */
+      if (e->used && e->ts) {
+        if (--e->ts == 0) {
+          e->used = 0;
+        }
+      }
+      BRIDGEIF_WRITE_UNPROTECT(lev);
+    }
+  }
+  BRIDGEIF_READ_UNPROTECT(lev);
+}
+
+/** Timer callback for fdb aging, called once per second */
+static void
+bridgeif_age_tmr(void *arg)
+{
+  bridgeif_dfdb_t *fdb = (bridgeif_dfdb_t *)arg;
+
+  LWIP_ASSERT("invalid arg", arg != NULL);
+
+  bridgeif_fdb_age_one_second(fdb);
+  sys_timeout(BRIDGEIF_AGE_TIMER_MS, bridgeif_age_tmr, arg);
+}
+
+/**
+ * @ingroup bridgeif_fdb
+ * Init our simple fdb list
+ */
+void *
+bridgeif_fdb_init(u16_t max_fdb_entries)
+{
+  bridgeif_dfdb_t *fdb;
+  size_t alloc_len_sizet = sizeof(bridgeif_dfdb_t) + (max_fdb_entries * sizeof(bridgeif_dfdb_entry_t));
+  mem_size_t alloc_len = (mem_size_t)alloc_len_sizet;
+  LWIP_ASSERT("alloc_len == alloc_len_sizet", alloc_len == alloc_len_sizet);
+  LWIP_DEBUGF(BRIDGEIF_DEBUG, ("bridgeif_fdb_init: allocating %d bytes for private FDB data\n", (int)alloc_len));
+  fdb = (bridgeif_dfdb_t *)mem_calloc(1, alloc_len);
+  if (fdb == NULL) {
+    return NULL;
+  }
+  fdb->max_fdb_entries = max_fdb_entries;
+  fdb->fdb = (bridgeif_dfdb_entry_t *)(fdb + 1);
+
+  sys_timeout(BRIDGEIF_AGE_TIMER_MS, bridgeif_age_tmr, fdb);
+
+  return fdb;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ethernet.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ethernet.c
new file mode 100644
index 000000000..dd171e280
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ethernet.c
@@ -0,0 +1,321 @@
+/**
+ * @file
+ * Ethernet common functions
+ *
+ * @defgroup ethernet Ethernet
+ * @ingroup callbackstyle_api
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+
+#if LWIP_ARP || LWIP_ETHERNET
+
+#include "netif/ethernet.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/etharp.h"
+#include "lwip/ip.h"
+#include "lwip/snmp.h"
+
+#include <string.h>
+
+#include "netif/ppp/ppp_opts.h"
+#if PPPOE_SUPPORT
+#include "netif/ppp/pppoe.h"
+#endif /* PPPOE_SUPPORT */
+
+#ifdef LWIP_HOOK_FILENAME
+#include LWIP_HOOK_FILENAME
+#endif
+
+const struct eth_addr ethbroadcast = {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
+const struct eth_addr ethzero = {{0, 0, 0, 0, 0, 0}};
+
+/**
+ * @ingroup lwip_nosys
+ * Process received ethernet frames. Using this function instead of directly
+ * calling ip_input and passing ARP frames through etharp in ethernetif_input,
+ * the ARP cache is protected from concurrent access.\n
+ * Don't call directly, pass to netif_add() and call netif->input().
+ *
+ * @param p the received packet, p->payload pointing to the ethernet header
+ * @param netif the network interface on which the packet was received
+ *
+ * @see LWIP_HOOK_UNKNOWN_ETH_PROTOCOL
+ * @see ETHARP_SUPPORT_VLAN
+ * @see LWIP_HOOK_VLAN_CHECK
+ */
+err_t
+ethernet_input(struct pbuf *p, struct netif *netif)
+{
+  struct eth_hdr *ethhdr;
+  u16_t type;
+#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
+  u16_t next_hdr_offset = SIZEOF_ETH_HDR;
+#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  if (p->len <= SIZEOF_ETH_HDR) {
+    /* a packet with only an ethernet header (or less) is not valid for us */
+    ETHARP_STATS_INC(etharp.proterr);
+    ETHARP_STATS_INC(etharp.drop);
+    MIB2_STATS_NETIF_INC(netif, ifinerrors);
+    goto free_and_return;
+  }
+
+  if (p->if_idx == NETIF_NO_INDEX) {
+    p->if_idx = netif_get_index(netif);
+  }
+
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = (struct eth_hdr *)p->payload;
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
+              ("ethernet_input: dest:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", src:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", type:%"X16_F"\n",
+               (unsigned char)ethhdr->dest.addr[0], (unsigned char)ethhdr->dest.addr[1], (unsigned char)ethhdr->dest.addr[2],
+               (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
+               (unsigned char)ethhdr->src.addr[0],  (unsigned char)ethhdr->src.addr[1],  (unsigned char)ethhdr->src.addr[2],
+               (unsigned char)ethhdr->src.addr[3],  (unsigned char)ethhdr->src.addr[4],  (unsigned char)ethhdr->src.addr[5],
+               lwip_htons(ethhdr->type)));
+
+  type = ethhdr->type;
+#if ETHARP_SUPPORT_VLAN
+  if (type == PP_HTONS(ETHTYPE_VLAN)) {
+    struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr *)(((char *)ethhdr) + SIZEOF_ETH_HDR);
+    next_hdr_offset = SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR;
+    if (p->len <= SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) {
+      /* a packet with only an ethernet/vlan header (or less) is not valid for us */
+      ETHARP_STATS_INC(etharp.proterr);
+      ETHARP_STATS_INC(etharp.drop);
+      MIB2_STATS_NETIF_INC(netif, ifinerrors);
+      goto free_and_return;
+    }
+#if defined(LWIP_HOOK_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK_FN) /* if not, allow all VLANs */
+#ifdef LWIP_HOOK_VLAN_CHECK
+    if (!LWIP_HOOK_VLAN_CHECK(netif, ethhdr, vlan)) {
+#elif defined(ETHARP_VLAN_CHECK_FN)
+    if (!ETHARP_VLAN_CHECK_FN(ethhdr, vlan)) {
+#elif defined(ETHARP_VLAN_CHECK)
+    if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) {
+#endif
+      /* silently ignore this packet: not for our VLAN */
+      pbuf_free(p);
+      return ERR_OK;
+    }
+#endif /* defined(LWIP_HOOK_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK_FN) */
+    type = vlan->tpid;
+  }
+#endif /* ETHARP_SUPPORT_VLAN */
+
+#if LWIP_ARP_FILTER_NETIF
+  netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
+#endif /* LWIP_ARP_FILTER_NETIF*/
+
+  if (ethhdr->dest.addr[0] & 1) {
+    /* this might be a multicast or broadcast packet */
+    if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
+#if LWIP_IPV4
+      if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
+          (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
+        /* mark the pbuf as link-layer multicast */
+        p->flags |= PBUF_FLAG_LLMCAST;
+      }
+#endif /* LWIP_IPV4 */
+    }
+#if LWIP_IPV6
+    else if ((ethhdr->dest.addr[0] == LL_IP6_MULTICAST_ADDR_0) &&
+             (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
+      /* mark the pbuf as link-layer multicast */
+      p->flags |= PBUF_FLAG_LLMCAST;
+    }
+#endif /* LWIP_IPV6 */
+    else if (eth_addr_cmp(&ethhdr->dest, &ethbroadcast)) {
+      /* mark the pbuf as link-layer broadcast */
+      p->flags |= PBUF_FLAG_LLBCAST;
+    }
+  }
+
+  switch (type) {
+#if LWIP_IPV4 && LWIP_ARP
+    /* IP packet? */
+    case PP_HTONS(ETHTYPE_IP):
+      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
+        goto free_and_return;
+      }
+      /* skip Ethernet header (min. size checked above) */
+      if (pbuf_remove_header(p, next_hdr_offset)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                    ("ethernet_input: IPv4 packet dropped, too short (%"U16_F"/%"U16_F")\n",
+                     p->tot_len, next_hdr_offset));
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("Can't move over header in packet"));
+        goto free_and_return;
+      } else {
+        /* pass to IP layer */
+        ip4_input(p, netif);
+      }
+      break;
+
+    case PP_HTONS(ETHTYPE_ARP):
+      if (!(netif->flags & NETIF_FLAG_ETHARP)) {
+        goto free_and_return;
+      }
+      /* skip Ethernet header (min. size checked above) */
+      if (pbuf_remove_header(p, next_hdr_offset)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                    ("ethernet_input: ARP response packet dropped, too short (%"U16_F"/%"U16_F")\n",
+                     p->tot_len, next_hdr_offset));
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("Can't move over header in packet"));
+        ETHARP_STATS_INC(etharp.lenerr);
+        ETHARP_STATS_INC(etharp.drop);
+        goto free_and_return;
+      } else {
+        /* pass p to ARP module */
+        etharp_input(p, netif);
+      }
+      break;
+#endif /* LWIP_IPV4 && LWIP_ARP */
+#if PPPOE_SUPPORT
+    case PP_HTONS(ETHTYPE_PPPOEDISC): /* PPP Over Ethernet Discovery Stage */
+      pppoe_disc_input(netif, p);
+      break;
+
+    case PP_HTONS(ETHTYPE_PPPOE): /* PPP Over Ethernet Session Stage */
+      pppoe_data_input(netif, p);
+      break;
+#endif /* PPPOE_SUPPORT */
+
+#if LWIP_IPV6
+    case PP_HTONS(ETHTYPE_IPV6): /* IPv6 */
+      /* skip Ethernet header */
+      if ((p->len < next_hdr_offset) || pbuf_remove_header(p, next_hdr_offset)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
+                    ("ethernet_input: IPv6 packet dropped, too short (%"U16_F"/%"U16_F")\n",
+                     p->tot_len, next_hdr_offset));
+        goto free_and_return;
+      } else {
+        /* pass to IPv6 layer */
+        ip6_input(p, netif);
+      }
+      break;
+#endif /* LWIP_IPV6 */
+
+    default:
+#ifdef LWIP_HOOK_UNKNOWN_ETH_PROTOCOL
+      if (LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(p, netif) == ERR_OK) {
+        break;
+      }
+#endif
+      ETHARP_STATS_INC(etharp.proterr);
+      ETHARP_STATS_INC(etharp.drop);
+      MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
+      goto free_and_return;
+  }
+
+  /* This means the pbuf is freed or consumed,
+     so the caller doesn't have to free it again */
+  return ERR_OK;
+
+free_and_return:
+  pbuf_free(p);
+  return ERR_OK;
+}
+
+/**
+ * @ingroup ethernet
+ * Send an ethernet packet on the network using netif->linkoutput().
+ * The ethernet header is filled in before sending.
+ *
+ * @see LWIP_HOOK_VLAN_SET
+ *
+ * @param netif the lwIP network interface on which to send the packet
+ * @param p the packet to send. pbuf layer must be @ref PBUF_LINK.
+ * @param src the source MAC address to be copied into the ethernet header
+ * @param dst the destination MAC address to be copied into the ethernet header
+ * @param eth_type ethernet type (@ref lwip_ieee_eth_type)
+ * @return ERR_OK if the packet was sent, any other err_t on failure
+ */
+err_t
+ethernet_output(struct netif * netif, struct pbuf * p,
+                const struct eth_addr * src, const struct eth_addr * dst,
+                u16_t eth_type) {
+  struct eth_hdr *ethhdr;
+  u16_t eth_type_be = lwip_htons(eth_type);
+
+#if ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET)
+  s32_t vlan_prio_vid = LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type);
+  if (vlan_prio_vid >= 0) {
+    struct eth_vlan_hdr *vlanhdr;
+
+    LWIP_ASSERT("prio_vid must be <= 0xFFFF", vlan_prio_vid <= 0xFFFF);
+
+    if (pbuf_add_header(p, SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) != 0) {
+      goto pbuf_header_failed;
+    }
+    vlanhdr = (struct eth_vlan_hdr *)(((u8_t *)p->payload) + SIZEOF_ETH_HDR);
+    vlanhdr->tpid     = eth_type_be;
+    vlanhdr->prio_vid = lwip_htons((u16_t)vlan_prio_vid);
+
+    eth_type_be = PP_HTONS(ETHTYPE_VLAN);
+  } else
+#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
+  {
+    if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
+      goto pbuf_header_failed;
+    }
+  }
+
+  LWIP_ASSERT_CORE_LOCKED();
+
+  ethhdr = (struct eth_hdr *)p->payload;
+  ethhdr->type = eth_type_be;
+  SMEMCPY(&ethhdr->dest, dst, ETH_HWADDR_LEN);
+  SMEMCPY(&ethhdr->src,  src, ETH_HWADDR_LEN);
+
+  LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
+              (netif->hwaddr_len == ETH_HWADDR_LEN));
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
+              ("ethernet_output: sending packet %p\n", (void *)p));
+
+  /* send the packet */
+  return netif->linkoutput(netif, p);
+
+pbuf_header_failed:
+  LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
+              ("ethernet_output: could not allocate room for header.\n"));
+  LINK_STATS_INC(link.lenerr);
+  return ERR_BUF;
+}
+
+#endif /* LWIP_ARP || LWIP_ETHERNET */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6.c
new file mode 100644
index 000000000..7f0d27676
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6.c
@@ -0,0 +1,920 @@
+/**
+ * @file
+ *
+ * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ *
+ * This implementation aims to conform to IEEE 802.15.4(-2015), RFC 4944 and RFC 6282.
+ * @todo: RFC 6775.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+/**
+ * @defgroup sixlowpan 6LoWPAN (RFC4944)
+ * @ingroup netifs
+ * 6LowPAN netif implementation
+ */
+
+#include "netif/lowpan6.h"
+
+#if LWIP_IPV6
+
+#include "lwip/ip.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/nd6.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/tcpip.h"
+#include "lwip/snmp.h"
+#include "netif/ieee802154.h"
+
+#include <string.h>
+
+#if LWIP_6LOWPAN_802154_HW_CRC
+#define LWIP_6LOWPAN_DO_CALC_CRC(buf, len) 0
+#else
+#define LWIP_6LOWPAN_DO_CALC_CRC(buf, len) LWIP_6LOWPAN_CALC_CRC(buf, len)
+#endif
+
+/** This is a helper struct for reassembly of fragments
+ * (IEEE 802.15.4 limits to 127 bytes)
+ */
+struct lowpan6_reass_helper {
+  struct lowpan6_reass_helper *next_packet;
+  struct pbuf *reass;
+  struct pbuf *frags;
+  u8_t timer;
+  struct lowpan6_link_addr sender_addr;
+  u16_t datagram_size;
+  u16_t datagram_tag;
+};
+
+/** This struct keeps track of per-netif state */
+struct lowpan6_ieee802154_data {
+  /** fragment reassembly list */
+  struct lowpan6_reass_helper *reass_list;
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+  /** address context for compression */
+  ip6_addr_t lowpan6_context[LWIP_6LOWPAN_NUM_CONTEXTS];
+#endif
+  /** Datagram Tag for fragmentation */
+  u16_t tx_datagram_tag;
+  /** local PAN ID for IEEE 802.15.4 header */
+  u16_t ieee_802154_pan_id;
+  /** Sequence Number for IEEE 802.15.4 transmission */
+  u8_t tx_frame_seq_num;
+};
+
+/* Maximum frame size is 127 bytes minus CRC size */
+#define LOWPAN6_MAX_PAYLOAD (127 - 2)
+
+/** Currently, this state is global, since there's only one 6LoWPAN netif */
+static struct lowpan6_ieee802154_data lowpan6_data;
+
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+#define LWIP_6LOWPAN_CONTEXTS(netif) lowpan6_data.lowpan6_context
+#else
+#define LWIP_6LOWPAN_CONTEXTS(netif) NULL
+#endif
+
+static const struct lowpan6_link_addr ieee_802154_broadcast = {2, {0xff, 0xff}};
+
+#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+static struct lowpan6_link_addr short_mac_addr = {2, {0, 0}};
+#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */
+
+/* IEEE 802.15.4 specific functions: */
+
+/** Write the IEEE 802.15.4 header that encapsulates the 6LoWPAN frame.
+ * Src and dst PAN IDs are filled with the ID set by @ref lowpan6_set_pan_id.
+ *
+ * Since the length is variable:
+ * @returns the header length
+ */
+static u8_t
+lowpan6_write_iee802154_header(struct ieee_802154_hdr *hdr, const struct lowpan6_link_addr *src,
+                               const struct lowpan6_link_addr *dst)
+{
+  u8_t ieee_header_len;
+  u8_t *buffer;
+  u8_t i;
+  u16_t fc;
+
+  fc = IEEE_802154_FC_FT_DATA; /* send data packet (2003 frame version) */
+  fc |= IEEE_802154_FC_PANID_COMPR; /* set PAN ID compression, for now src and dst PANs are equal */
+  if (dst != &ieee_802154_broadcast) {
+    fc |= IEEE_802154_FC_ACK_REQ; /* data packet, no broadcast: ack required. */
+  }
+  if (dst->addr_len == 2) {
+    fc |= IEEE_802154_FC_DST_ADDR_MODE_SHORT;
+  } else {
+    LWIP_ASSERT("invalid dst address length", dst->addr_len == 8);
+    fc |= IEEE_802154_FC_DST_ADDR_MODE_EXT;
+  }
+  if (src->addr_len == 2) {
+    fc |= IEEE_802154_FC_SRC_ADDR_MODE_SHORT;
+  } else {
+    LWIP_ASSERT("invalid src address length", src->addr_len == 8);
+    fc |= IEEE_802154_FC_SRC_ADDR_MODE_EXT;
+  }
+  hdr->frame_control = fc;
+  hdr->sequence_number = lowpan6_data.tx_frame_seq_num++;
+  hdr->destination_pan_id = lowpan6_data.ieee_802154_pan_id; /* pan id */
+
+  buffer = (u8_t *)hdr;
+  ieee_header_len = 5;
+  i = dst->addr_len;
+  /* reverse memcpy of dst addr */
+  while (i-- > 0) {
+    buffer[ieee_header_len++] = dst->addr[i];
+  }
+  /* Source PAN ID skipped due to PAN ID Compression */
+  i = src->addr_len;
+  /* reverse memcpy of src addr */
+  while (i-- > 0) {
+    buffer[ieee_header_len++] = src->addr[i];
+  }
+  return ieee_header_len;
+}
+
+/** Parse the IEEE 802.15.4 header from a pbuf.
+ * If successful, the header is hidden from the pbuf.
+ *
+ * PAN IDs and seuqence number are not checked
+ *
+ * @param p input pbuf, p->payload pointing at the IEEE 802.15.4 header
+ * @param src pointer to source address filled from the header
+ * @param dest pointer to destination address filled from the header
+ * @returns ERR_OK if successful
+ */
+static err_t
+lowpan6_parse_iee802154_header(struct pbuf *p, struct lowpan6_link_addr *src,
+                               struct lowpan6_link_addr *dest)
+{
+  u8_t *puc;
+  s8_t i;
+  u16_t frame_control, addr_mode;
+  u16_t datagram_offset;
+
+  /* Parse IEEE 802.15.4 header */
+  puc = (u8_t *)p->payload;
+  frame_control = puc[0] | (puc[1] << 8);
+  datagram_offset = 2;
+  if (frame_control & IEEE_802154_FC_SEQNO_SUPPR) {
+    if (IEEE_802154_FC_FRAME_VERSION_GET(frame_control) <= 1) {
+      /* sequence number suppressed, this is not valid for versions 0/1 */
+      return ERR_VAL;
+    }
+  } else {
+    datagram_offset++;
+  }
+  datagram_offset += 2; /* Skip destination PAN ID */
+  addr_mode = frame_control & IEEE_802154_FC_DST_ADDR_MODE_MASK;
+  if (addr_mode == IEEE_802154_FC_DST_ADDR_MODE_EXT) {
+    /* extended address (64 bit) */
+    dest->addr_len = 8;
+    /* reverse memcpy: */
+    for (i = 0; i < 8; i++) {
+      dest->addr[i] = puc[datagram_offset + 7 - i];
+    }
+    datagram_offset += 8;
+  } else if (addr_mode == IEEE_802154_FC_DST_ADDR_MODE_SHORT) {
+    /* short address (16 bit) */
+    dest->addr_len = 2;
+    /* reverse memcpy: */
+    dest->addr[0] = puc[datagram_offset + 1];
+    dest->addr[1] = puc[datagram_offset];
+    datagram_offset += 2;
+  } else {
+    /* unsupported address mode (do we need "no address"?) */
+    return ERR_VAL;
+  }
+
+  if (!(frame_control & IEEE_802154_FC_PANID_COMPR)) {
+    /* No PAN ID compression, skip source PAN ID */
+    datagram_offset += 2;
+  }
+
+  addr_mode = frame_control & IEEE_802154_FC_SRC_ADDR_MODE_MASK;
+  if (addr_mode == IEEE_802154_FC_SRC_ADDR_MODE_EXT) {
+    /* extended address (64 bit) */
+    src->addr_len = 8;
+    /* reverse memcpy: */
+    for (i = 0; i < 8; i++) {
+      src->addr[i] = puc[datagram_offset + 7 - i];
+    }
+    datagram_offset += 8;
+  } else if (addr_mode == IEEE_802154_FC_DST_ADDR_MODE_SHORT) {
+    /* short address (16 bit) */
+    src->addr_len = 2;
+    src->addr[0] = puc[datagram_offset + 1];
+    src->addr[1] = puc[datagram_offset];
+    datagram_offset += 2;
+  } else {
+    /* unsupported address mode (do we need "no address"?) */
+    return ERR_VAL;
+  }
+
+  /* hide IEEE802.15.4 header. */
+  if (pbuf_remove_header(p, datagram_offset)) {
+    return ERR_VAL;
+  }
+  return ERR_OK;
+}
+
+/** Calculate the 16-bit CRC as required by IEEE 802.15.4 */
+u16_t
+lowpan6_calc_crc(const void* buf, u16_t len)
+{
+#define CCITT_POLY_16 0x8408U
+  u16_t i;
+  u8_t b;
+  u16_t crc = 0;
+  const u8_t* p = (const u8_t*)buf;
+
+  for (i = 0; i < len; i++) {
+    u8_t data = *p;
+    for (b = 0U; b < 8U; b++) {
+      if (((data ^ crc) & 1) != 0) {
+        crc = (u16_t)((crc >> 1) ^ CCITT_POLY_16);
+      } else {
+        crc = (u16_t)(crc >> 1);
+      }
+      data = (u8_t)(data >> 1);
+    }
+    p++;
+  }
+  return crc;
+}
+
+/* Fragmentation specific functions: */
+
+static void
+free_reass_datagram(struct lowpan6_reass_helper *lrh)
+{
+  if (lrh->reass) {
+    pbuf_free(lrh->reass);
+  }
+  if (lrh->frags) {
+    pbuf_free(lrh->frags);
+  }
+  mem_free(lrh);
+}
+
+/**
+ * Removes a datagram from the reassembly queue.
+ **/
+static void
+dequeue_datagram(struct lowpan6_reass_helper *lrh, struct lowpan6_reass_helper *prev)
+{
+  if (lowpan6_data.reass_list == lrh) {
+    lowpan6_data.reass_list = lowpan6_data.reass_list->next_packet;
+  } else {
+    /* it wasn't the first, so it must have a valid 'prev' */
+    LWIP_ASSERT("sanity check linked list", prev != NULL);
+    prev->next_packet = lrh->next_packet;
+  }
+}
+
+/**
+ * Periodic timer for 6LowPAN functions:
+ *
+ * - Remove incomplete/old packets
+ */
+void
+lowpan6_tmr(void)
+{
+  struct lowpan6_reass_helper *lrh, *lrh_next, *lrh_prev = NULL;
+
+  lrh = lowpan6_data.reass_list;
+  while (lrh != NULL) {
+    lrh_next = lrh->next_packet;
+    if ((--lrh->timer) == 0) {
+      dequeue_datagram(lrh, lrh_prev);
+      free_reass_datagram(lrh);
+    } else {
+      lrh_prev = lrh;
+    }
+    lrh = lrh_next;
+  }
+}
+
+/*
+ * Encapsulates data into IEEE 802.15.4 frames.
+ * Fragments an IPv6 datagram into 6LowPAN units, which fit into IEEE 802.15.4 frames.
+ * If configured, will compress IPv6 and or UDP headers.
+ * */
+static err_t
+lowpan6_frag(struct netif *netif, struct pbuf *p, const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst)
+{
+  struct pbuf *p_frag;
+  u16_t frag_len, remaining_len, max_data_len;
+  u8_t *buffer;
+  u8_t ieee_header_len;
+  u8_t lowpan6_header_len;
+  u8_t hidden_header_len;
+  u16_t crc;
+  u16_t datagram_offset;
+  err_t err = ERR_IF;
+
+  LWIP_ASSERT("lowpan6_frag: netif->linkoutput not set", netif->linkoutput != NULL);
+
+  /* We'll use a dedicated pbuf for building 6LowPAN fragments. */
+  p_frag = pbuf_alloc(PBUF_RAW, 127, PBUF_RAM);
+  if (p_frag == NULL) {
+    MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("this needs a pbuf in one piece", p_frag->len == p_frag->tot_len);
+
+  /* Write IEEE 802.15.4 header. */
+  buffer = (u8_t *)p_frag->payload;
+  ieee_header_len = lowpan6_write_iee802154_header((struct ieee_802154_hdr *)buffer, src, dst);
+  LWIP_ASSERT("ieee_header_len < p_frag->len", ieee_header_len < p_frag->len);
+
+#if LWIP_6LOWPAN_IPHC
+  /* Perform 6LowPAN IPv6 header compression according to RFC 6282 */
+  /* do the header compression (this does NOT copy any non-compressed data) */
+  err = lowpan6_compress_headers(netif, (u8_t *)p->payload, p->len,
+    &buffer[ieee_header_len], p_frag->len - ieee_header_len, &lowpan6_header_len,
+    &hidden_header_len, LWIP_6LOWPAN_CONTEXTS(netif), src, dst);
+  if (err != ERR_OK) {
+    MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+    pbuf_free(p_frag);
+    return err;
+  }
+  pbuf_remove_header(p, hidden_header_len);
+
+#else /* LWIP_6LOWPAN_IPHC */
+  /* Send uncompressed IPv6 header with appropriate dispatch byte. */
+  lowpan6_header_len = 1;
+  buffer[ieee_header_len] = 0x41; /* IPv6 dispatch */
+#endif /* LWIP_6LOWPAN_IPHC */
+
+  /* Calculate remaining packet length */
+  remaining_len = p->tot_len;
+
+  if (remaining_len > 0x7FF) {
+    MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+    /* datagram_size must fit into 11 bit */
+    pbuf_free(p_frag);
+    return ERR_VAL;
+  }
+
+  /* Fragment, or 1 packet? */
+  max_data_len = LOWPAN6_MAX_PAYLOAD - ieee_header_len - lowpan6_header_len;
+  if (remaining_len > max_data_len) {
+    u16_t data_len;
+    /* We must move the 6LowPAN header to make room for the FRAG header. */
+    memmove(&buffer[ieee_header_len + 4], &buffer[ieee_header_len], lowpan6_header_len);
+
+    /* Now we need to fragment the packet. FRAG1 header first */
+    buffer[ieee_header_len] = 0xc0 | (((p->tot_len + hidden_header_len) >> 8) & 0x7);
+    buffer[ieee_header_len + 1] = (p->tot_len + hidden_header_len) & 0xff;
+
+    lowpan6_data.tx_datagram_tag++;
+    buffer[ieee_header_len + 2] = (lowpan6_data.tx_datagram_tag >> 8) & 0xff;
+    buffer[ieee_header_len + 3] = lowpan6_data.tx_datagram_tag & 0xff;
+
+    /* Fragment follows. */
+    data_len = (max_data_len - 4) & 0xf8;
+    frag_len = data_len + lowpan6_header_len;
+
+    pbuf_copy_partial(p, buffer + ieee_header_len + lowpan6_header_len + 4, frag_len - lowpan6_header_len, 0);
+    remaining_len -= frag_len - lowpan6_header_len;
+    /* datagram offset holds the offset before compression */
+    datagram_offset = frag_len - lowpan6_header_len + hidden_header_len;
+    LWIP_ASSERT("datagram offset must be a multiple of 8", (datagram_offset & 7) == 0);
+
+    /* Calculate frame length */
+    p_frag->len = p_frag->tot_len = ieee_header_len + 4 + frag_len + 2; /* add 2 bytes for crc*/
+
+    /* 2 bytes CRC */
+    crc = LWIP_6LOWPAN_DO_CALC_CRC(p_frag->payload, p_frag->len - 2);
+    pbuf_take_at(p_frag, &crc, 2, p_frag->len - 2);
+
+    /* send the packet */
+    MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len);
+    LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p));
+    err = netif->linkoutput(netif, p_frag);
+
+    while ((remaining_len > 0) && (err == ERR_OK)) {
+      struct ieee_802154_hdr *hdr = (struct ieee_802154_hdr *)buffer;
+      /* new frame, new seq num for ACK */
+      hdr->sequence_number = lowpan6_data.tx_frame_seq_num++;
+
+      buffer[ieee_header_len] |= 0x20; /* Change FRAG1 to FRAGN */
+
+      LWIP_ASSERT("datagram offset must be a multiple of 8", (datagram_offset & 7) == 0);
+      buffer[ieee_header_len + 4] = (u8_t)(datagram_offset >> 3); /* datagram offset in FRAGN header (datagram_offset is max. 11 bit) */
+
+      frag_len = (127 - ieee_header_len - 5 - 2) & 0xf8;
+      if (frag_len > remaining_len) {
+        frag_len = remaining_len;
+      }
+
+      pbuf_copy_partial(p, buffer + ieee_header_len + 5, frag_len, p->tot_len - remaining_len);
+      remaining_len -= frag_len;
+      datagram_offset += frag_len;
+
+      /* Calculate frame length */
+      p_frag->len = p_frag->tot_len = frag_len + 5 + ieee_header_len + 2;
+
+      /* 2 bytes CRC */
+      crc = LWIP_6LOWPAN_DO_CALC_CRC(p_frag->payload, p_frag->len - 2);
+      pbuf_take_at(p_frag, &crc, 2, p_frag->len - 2);
+
+      /* send the packet */
+      MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len);
+      LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p));
+      err = netif->linkoutput(netif, p_frag);
+    }
+  } else {
+    /* It fits in one frame. */
+    frag_len = remaining_len;
+
+    /* Copy IPv6 packet */
+    pbuf_copy_partial(p, buffer + ieee_header_len + lowpan6_header_len, frag_len, 0);
+    remaining_len = 0;
+
+    /* Calculate frame length */
+    p_frag->len = p_frag->tot_len = frag_len + lowpan6_header_len + ieee_header_len + 2;
+    LWIP_ASSERT("", p_frag->len <= 127);
+
+    /* 2 bytes CRC */
+    crc = LWIP_6LOWPAN_DO_CALC_CRC(p_frag->payload, p_frag->len - 2);
+    pbuf_take_at(p_frag, &crc, 2, p_frag->len - 2);
+
+    /* send the packet */
+    MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len);
+    LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p));
+    err = netif->linkoutput(netif, p_frag);
+  }
+
+  pbuf_free(p_frag);
+
+  return err;
+}
+
+/**
+ * @ingroup sixlowpan
+ * Set context
+ */
+err_t
+lowpan6_set_context(u8_t idx, const ip6_addr_t *context)
+{
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+  if (idx >= LWIP_6LOWPAN_NUM_CONTEXTS) {
+    return ERR_ARG;
+  }
+
+  IP6_ADDR_ZONECHECK(context);
+
+  ip6_addr_set(&lowpan6_data.lowpan6_context[idx], context);
+
+  return ERR_OK;
+#else
+  LWIP_UNUSED_ARG(idx);
+  LWIP_UNUSED_ARG(context);
+  return ERR_ARG;
+#endif
+}
+
+#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+/**
+ * @ingroup sixlowpan
+ * Set short address
+ */
+err_t
+lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low)
+{
+  short_mac_addr.addr[0] = addr_high;
+  short_mac_addr.addr[1] = addr_low;
+
+  return ERR_OK;
+}
+#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */
+
+/* Create IEEE 802.15.4 address from netif address */
+static err_t
+lowpan6_hwaddr_to_addr(struct netif *netif, struct lowpan6_link_addr *addr)
+{
+  addr->addr_len = 8;
+  if (netif->hwaddr_len == 8) {
+    LWIP_ERROR("NETIF_MAX_HWADDR_LEN >= 8 required", sizeof(netif->hwaddr) >= 8, return ERR_VAL;);
+    SMEMCPY(addr->addr, netif->hwaddr, 8);
+  } else if (netif->hwaddr_len == 6) {
+    /* Copy from MAC-48 */
+    SMEMCPY(addr->addr, netif->hwaddr, 3);
+    addr->addr[3] = addr->addr[4] = 0xff;
+    SMEMCPY(&addr->addr[5], &netif->hwaddr[3], 3);
+  } else {
+    /* Invalid address length, don't know how to convert this */
+    return ERR_VAL;
+  }
+  return ERR_OK;
+}
+
+/**
+ * @ingroup sixlowpan
+ * Resolve and fill-in IEEE 802.15.4 address header for outgoing IPv6 packet.
+ *
+ * Perform Header Compression and fragment if necessary.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ip6addr The IP address of the packet destination.
+ *
+ * @return err_t
+ */
+err_t
+lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr)
+{
+  err_t result;
+  const u8_t *hwaddr;
+  struct lowpan6_link_addr src, dest;
+#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+  ip6_addr_t ip6_src;
+  struct ip6_hdr *ip6_hdr;
+#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */
+
+#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+  /* Check if we can compress source address (use aligned copy) */
+  ip6_hdr = (struct ip6_hdr *)q->payload;
+  ip6_addr_copy_from_packed(ip6_src, ip6_hdr->src);
+  ip6_addr_assign_zone(&ip6_src, IP6_UNICAST, netif);
+  if (lowpan6_get_address_mode(&ip6_src, &short_mac_addr) == 3) {
+    src.addr_len = 2;
+    src.addr[0] = short_mac_addr.addr[0];
+    src.addr[1] = short_mac_addr.addr[1];
+  } else
+#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */
+  {
+    result = lowpan6_hwaddr_to_addr(netif, &src);
+    if (result != ERR_OK) {
+      MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+      return result;
+    }
+  }
+
+  /* multicast destination IP address? */
+  if (ip6_addr_ismulticast(ip6addr)) {
+    MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts);
+    /* We need to send to the broadcast address.*/
+    return lowpan6_frag(netif, q, &src, &ieee_802154_broadcast);
+  }
+
+  /* We have a unicast destination IP address */
+  /* @todo anycast? */
+
+#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS
+  if (src.addr_len == 2) {
+    /* If source address was compressable to short_mac_addr, and dest has same subnet and
+     * is also compressable to 2-bytes, assume we can infer dest as a short address too. */
+    dest.addr_len = 2;
+    dest.addr[0] = ((u8_t *)q->payload)[38];
+    dest.addr[1] = ((u8_t *)q->payload)[39];
+    if ((src.addr_len == 2) && (ip6_addr_netcmp_zoneless(&ip6_hdr->src, &ip6_hdr->dest)) &&
+        (lowpan6_get_address_mode(ip6addr, &dest) == 3)) {
+      MIB2_STATS_NETIF_INC(netif, ifoutucastpkts);
+      return lowpan6_frag(netif, q, &src, &dest);
+    }
+  }
+#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */
+
+  /* Ask ND6 what to do with the packet. */
+  result = nd6_get_next_hop_addr_or_queue(netif, q, ip6addr, &hwaddr);
+  if (result != ERR_OK) {
+    MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+    return result;
+  }
+
+  /* If no hardware address is returned, nd6 has queued the packet for later. */
+  if (hwaddr == NULL) {
+    return ERR_OK;
+  }
+
+  /* Send out the packet using the returned hardware address. */
+  dest.addr_len = netif->hwaddr_len;
+  /* XXX: Inferring the length of the source address from the destination address
+   * is not correct for IEEE 802.15.4, but currently we don't get this information
+   * from the neighbor cache */
+  SMEMCPY(dest.addr, hwaddr, netif->hwaddr_len);
+  MIB2_STATS_NETIF_INC(netif, ifoutucastpkts);
+  return lowpan6_frag(netif, q, &src, &dest);
+}
+/**
+ * @ingroup sixlowpan
+ * NETIF input function: don't free the input pbuf when returning != ERR_OK!
+ */
+err_t
+lowpan6_input(struct pbuf *p, struct netif *netif)
+{
+  u8_t *puc, b;
+  s8_t i;
+  struct lowpan6_link_addr src, dest;
+  u16_t datagram_size = 0;
+  u16_t datagram_offset, datagram_tag;
+  struct lowpan6_reass_helper *lrh, *lrh_next, *lrh_prev = NULL;
+
+  if (p == NULL) {
+    return ERR_OK;
+  }
+
+  MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len);
+
+  if (p->len != p->tot_len) {
+    /* for now, this needs a pbuf in one piece */
+    goto lowpan6_input_discard;
+  }
+
+  if (lowpan6_parse_iee802154_header(p, &src, &dest) != ERR_OK) {
+    goto lowpan6_input_discard;
+  }
+
+  /* Check dispatch. */
+  puc = (u8_t *)p->payload;
+
+  b = *puc;
+  if ((b & 0xf8) == 0xc0) {
+    /* FRAG1 dispatch. add this packet to reassembly list. */
+    datagram_size = ((u16_t)(puc[0] & 0x07) << 8) | (u16_t)puc[1];
+    datagram_tag = ((u16_t)puc[2] << 8) | (u16_t)puc[3];
+
+    /* check for duplicate */
+    lrh = lowpan6_data.reass_list;
+    while (lrh != NULL) {
+      uint8_t discard = 0;
+      lrh_next = lrh->next_packet;
+      if ((lrh->sender_addr.addr_len == src.addr_len) &&
+          (memcmp(lrh->sender_addr.addr, src.addr, src.addr_len) == 0)) {
+        /* address match with packet in reassembly. */
+        if ((datagram_tag == lrh->datagram_tag) && (datagram_size == lrh->datagram_size)) {
+          /* duplicate fragment. */
+          goto lowpan6_input_discard;
+        } else {
+          /* We are receiving the start of a new datagram. Discard old one (incomplete). */
+          discard = 1;
+        }
+      }
+      if (discard) {
+        dequeue_datagram(lrh, lrh_prev);
+        free_reass_datagram(lrh);
+      } else {
+        lrh_prev = lrh;
+      }
+      /* Check next datagram in queue. */
+      lrh = lrh_next;
+    }
+
+    pbuf_remove_header(p, 4); /* hide frag1 dispatch */
+
+    lrh = (struct lowpan6_reass_helper *) mem_malloc(sizeof(struct lowpan6_reass_helper));
+    if (lrh == NULL) {
+      goto lowpan6_input_discard;
+    }
+
+    lrh->sender_addr.addr_len = src.addr_len;
+    for (i = 0; i < src.addr_len; i++) {
+      lrh->sender_addr.addr[i] = src.addr[i];
+    }
+    lrh->datagram_size = datagram_size;
+    lrh->datagram_tag = datagram_tag;
+    lrh->frags = NULL;
+    if (*(u8_t *)p->payload == 0x41) {
+      /* This is a complete IPv6 packet, just skip dispatch byte. */
+      pbuf_remove_header(p, 1); /* hide dispatch byte. */
+      lrh->reass = p;
+    } else if ((*(u8_t *)p->payload & 0xe0 ) == 0x60) {
+      lrh->reass = lowpan6_decompress(p, datagram_size, LWIP_6LOWPAN_CONTEXTS(netif), &src, &dest);
+      if (lrh->reass == NULL) {
+        /* decompression failed */
+        mem_free(lrh);
+        goto lowpan6_input_discard;
+      }
+    }
+    /* TODO: handle the case where we already have FRAGN received */
+    lrh->next_packet = lowpan6_data.reass_list;
+    lrh->timer = 2;
+    lowpan6_data.reass_list = lrh;
+
+    return ERR_OK;
+  } else if ((b & 0xf8) == 0xe0) {
+    /* FRAGN dispatch, find packet being reassembled. */
+    datagram_size = ((u16_t)(puc[0] & 0x07) << 8) | (u16_t)puc[1];
+    datagram_tag = ((u16_t)puc[2] << 8) | (u16_t)puc[3];
+    datagram_offset = (u16_t)puc[4] << 3;
+    pbuf_remove_header(p, 4); /* hide frag1 dispatch but keep datagram offset for reassembly */
+
+    for (lrh = lowpan6_data.reass_list; lrh != NULL; lrh_prev = lrh, lrh = lrh->next_packet) {
+      if ((lrh->sender_addr.addr_len == src.addr_len) &&
+          (memcmp(lrh->sender_addr.addr, src.addr, src.addr_len) == 0) &&
+          (datagram_tag == lrh->datagram_tag) &&
+          (datagram_size == lrh->datagram_size)) {
+        break;
+      }
+    }
+    if (lrh == NULL) {
+      /* rogue fragment */
+      goto lowpan6_input_discard;
+    }
+    /* Insert new pbuf into list of fragments. Each fragment is a pbuf,
+       this only works for unchained pbufs. */
+    LWIP_ASSERT("p->next == NULL", p->next == NULL);
+    if (lrh->reass != NULL) {
+      /* FRAG1 already received, check this offset against first len */
+      if (datagram_offset < lrh->reass->len) {
+        /* fragment overlap, discard old fragments */
+        dequeue_datagram(lrh, lrh_prev);
+        free_reass_datagram(lrh);
+        goto lowpan6_input_discard;
+      }
+    }
+    if (lrh->frags == NULL) {
+      /* first FRAGN */
+      lrh->frags = p;
+    } else {
+      /* find the correct place to insert */
+      struct pbuf *q, *last;
+      u16_t new_frag_len = p->len - 1; /* p->len includes datagram_offset byte */
+      for (q = lrh->frags, last = NULL; q != NULL; last = q, q = q->next) {
+        u16_t q_datagram_offset = ((u8_t *)q->payload)[0] << 3;
+        u16_t q_frag_len = q->len - 1;
+        if (datagram_offset < q_datagram_offset) {
+          if (datagram_offset + new_frag_len > q_datagram_offset) {
+            /* overlap, discard old fragments */
+            dequeue_datagram(lrh, lrh_prev);
+            free_reass_datagram(lrh);
+            goto lowpan6_input_discard;
+          }
+          /* insert here */
+          break;
+        } else if (datagram_offset == q_datagram_offset) {
+          if (q_frag_len != new_frag_len) {
+            /* fragment mismatch, discard old fragments */
+            dequeue_datagram(lrh, lrh_prev);
+            free_reass_datagram(lrh);
+            goto lowpan6_input_discard;
+          }
+          /* duplicate, ignore */
+          pbuf_free(p);
+          return ERR_OK;
+        }
+      }
+      /* insert fragment */
+      if (last == NULL) {
+        lrh->frags = p;
+      } else {
+        last->next = p;
+        p->next = q;
+      }
+    }
+    /* check if all fragments were received */
+    if (lrh->reass) {
+      u16_t offset = lrh->reass->len;
+      struct pbuf *q;
+      for (q = lrh->frags; q != NULL; q = q->next) {
+        u16_t q_datagram_offset = ((u8_t *)q->payload)[0] << 3;
+        if (q_datagram_offset != offset) {
+          /* not complete, wait for more fragments */
+          return ERR_OK;
+        }
+        offset += q->len - 1;
+      }
+      if (offset == datagram_size) {
+        /* all fragments received, combine pbufs */
+        u16_t datagram_left = datagram_size - lrh->reass->len;
+        for (q = lrh->frags; q != NULL; q = q->next) {
+          /* hide datagram_offset byte now */
+          pbuf_remove_header(q, 1);
+          q->tot_len = datagram_left;
+          datagram_left -= q->len;
+        }
+        LWIP_ASSERT("datagram_left == 0", datagram_left == 0);
+        q = lrh->reass;
+        q->tot_len = datagram_size;
+        q->next = lrh->frags;
+        lrh->frags = NULL;
+        lrh->reass = NULL;
+        dequeue_datagram(lrh, lrh_prev);
+        mem_free(lrh);
+
+        /* @todo: distinguish unicast/multicast */
+        MIB2_STATS_NETIF_INC(netif, ifinucastpkts);
+        return ip6_input(q, netif);
+      }
+    }
+    /* pbuf enqueued, waiting for more fragments */
+    return ERR_OK;
+  } else {
+    if (b == 0x41) {
+      /* This is a complete IPv6 packet, just skip dispatch byte. */
+      pbuf_remove_header(p, 1); /* hide dispatch byte. */
+    } else if ((b & 0xe0 ) == 0x60) {
+      /* IPv6 headers are compressed using IPHC. */
+      p = lowpan6_decompress(p, datagram_size, LWIP_6LOWPAN_CONTEXTS(netif), &src, &dest);
+      if (p == NULL) {
+        MIB2_STATS_NETIF_INC(netif, ifindiscards);
+        return ERR_OK;
+      }
+    } else {
+      goto lowpan6_input_discard;
+    }
+
+    /* @todo: distinguish unicast/multicast */
+    MIB2_STATS_NETIF_INC(netif, ifinucastpkts);
+
+    return ip6_input(p, netif);
+  }
+lowpan6_input_discard:
+  MIB2_STATS_NETIF_INC(netif, ifindiscards);
+  pbuf_free(p);
+  /* always return ERR_OK here to prevent the caller freeing the pbuf */
+  return ERR_OK;
+}
+
+/**
+ * @ingroup sixlowpan
+ */
+err_t
+lowpan6_if_init(struct netif *netif)
+{
+  netif->name[0] = 'L';
+  netif->name[1] = '6';
+  netif->output_ip6 = lowpan6_output;
+
+  MIB2_INIT_NETIF(netif, snmp_ifType_other, 0);
+
+  /* maximum transfer unit */
+  netif->mtu = 1280;
+
+  /* broadcast capability */
+  netif->flags = NETIF_FLAG_BROADCAST /* | NETIF_FLAG_LOWPAN6 */;
+
+  return ERR_OK;
+}
+
+/**
+ * @ingroup sixlowpan
+ * Set PAN ID
+ */
+err_t
+lowpan6_set_pan_id(u16_t pan_id)
+{
+  lowpan6_data.ieee_802154_pan_id = pan_id;
+
+  return ERR_OK;
+}
+
+#if !NO_SYS
+/**
+ * @ingroup sixlowpan
+ * Pass a received packet to tcpip_thread for input processing
+ *
+ * @param p the received packet, p->payload pointing to the
+ *          IEEE 802.15.4 header.
+ * @param inp the network interface on which the packet was received
+ */
+err_t
+tcpip_6lowpan_input(struct pbuf *p, struct netif *inp)
+{
+  return tcpip_inpkt(p, inp, lowpan6_input);
+}
+#endif /* !NO_SYS */
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6_ble.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6_ble.c
new file mode 100644
index 000000000..d89816d3b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6_ble.c
@@ -0,0 +1,447 @@
+/**
+ * @file
+ * 6LowPAN over BLE output for IPv6 (RFC7668).
+*/
+
+/*
+ * Copyright (c) 2017 Benjamin Aigner
+ * Copyright (c) 2015 Inico Technologies Ltd. , Author: Ivan Delamer <delamer@inicotech.com>
+ * 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Benjamin Aigner <aignerb@technikum-wien.at>
+ * 
+ * Based on the original 6lowpan implementation of lwIP ( @see 6lowpan.c)
+ */
+
+
+/**
+ * @defgroup rfc7668if 6LoWPAN over BLE (RFC7668)
+ * @ingroup netifs
+ * This file implements a RFC7668 implementation for 6LoWPAN over
+ * Bluetooth Low Energy. The specification is very similar to 6LoWPAN,
+ * so most of the code is re-used.
+ * Compared to 6LoWPAN, much functionality is already implemented in
+ * lower BLE layers (fragmenting, session management,...).
+ *
+ * Usage:
+ * - add this netif
+ *   - don't add IPv4 addresses (no IPv4 support in RFC7668), pass 'NULL','NULL','NULL'
+ *   - use the BLE to EUI64 conversation util to create an IPv6 link-local address from the BLE MAC (@ref ble_addr_to_eui64)
+ *   - input function: @ref rfc7668_input
+ * - set the link output function, which transmits output data to an established L2CAP channel
+ * - If data arrives (HCI event "L2CAP_DATA_PACKET"):
+ *   - allocate a @ref PBUF_RAW buffer
+ *   - let the pbuf struct point to the incoming data or copy it to the buffer
+ *   - call netif->input
+ *
+ * @todo:
+ * - further testing
+ * - support compression contexts
+ * - support multiple addresses
+ * - support multicast
+ * - support neighbor discovery
+ */
+
+
+#include "netif/lowpan6_ble.h"
+
+#if LWIP_IPV6
+
+#include "lwip/ip.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/nd6.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/tcpip.h"
+#include "lwip/snmp.h"
+
+#include <string.h>
+
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+/** context memory, containing IPv6 addresses */
+static ip6_addr_t rfc7668_context[LWIP_6LOWPAN_NUM_CONTEXTS];
+#else
+#define rfc7668_context NULL
+#endif
+
+static struct lowpan6_link_addr rfc7668_local_addr;
+static struct lowpan6_link_addr rfc7668_peer_addr;
+
+/**
+ * @ingroup rfc7668if
+ *  convert BT address to EUI64 addr
+ * 
+ * This method converts a Bluetooth MAC address to an EUI64 address,
+ * which is used within IPv6 communication
+ * 
+ * @param dst IPv6 destination space
+ * @param src BLE MAC address source
+ * @param public_addr If the LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS
+ * option is set, bit 0x02 will be set if param=0 (no public addr); cleared otherwise
+ * 
+ * @see LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS
+ */
+void
+ble_addr_to_eui64(uint8_t *dst, const uint8_t *src, int public_addr)
+{
+  /* according to RFC7668 ch 3.2.2. */
+  memcpy(dst, src, 3);
+  dst[3] = 0xFF;
+  dst[4] = 0xFE;
+  memcpy(&dst[5], &src[3], 3);
+#if LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS
+  if(public_addr) {
+    dst[0] &= ~0x02;
+  } else {
+    dst[0] |= 0x02;
+  }
+#else
+  LWIP_UNUSED_ARG(public_addr);
+#endif
+}
+
+/**
+ * @ingroup rfc7668if
+ *  convert EUI64 address to Bluetooth MAC addr
+ * 
+ * This method converts an EUI64 address to a Bluetooth MAC address,
+ * 
+ * @param dst BLE MAC address destination
+ * @param src IPv6 source
+ * 
+ */
+void
+eui64_to_ble_addr(uint8_t *dst, const uint8_t *src)
+{
+  /* according to RFC7668 ch 3.2.2. */
+  memcpy(dst,src,3);
+  memcpy(&dst[3],&src[5],3);
+}
+
+/** Set an address used for stateful compression.
+ * This expects an address of 6 or 8 bytes.
+ */
+static err_t
+rfc7668_set_addr(struct lowpan6_link_addr *addr, const u8_t *in_addr, size_t in_addr_len, int is_mac_48, int is_public_addr)
+{
+  if ((in_addr == NULL) || (addr == NULL)) {
+    return ERR_VAL;
+  }
+  if (is_mac_48) {
+    if (in_addr_len != 6) {
+      return ERR_VAL;
+    }
+    addr->addr_len = 8;
+    ble_addr_to_eui64(addr->addr, in_addr, is_public_addr);
+  } else {
+    if (in_addr_len != 8) {
+      return ERR_VAL;
+    }
+    addr->addr_len = 8;
+    memcpy(addr->addr, in_addr, 8);
+  }
+  return ERR_OK;
+}
+
+
+/** Set the local address used for stateful compression.
+ * This expects an address of 8 bytes.
+ */
+err_t
+rfc7668_set_local_addr_eui64(struct netif *netif, const u8_t *local_addr, size_t local_addr_len)
+{
+  /* netif not used for now, the address is stored globally... */
+  LWIP_UNUSED_ARG(netif);
+  return rfc7668_set_addr(&rfc7668_local_addr, local_addr, local_addr_len, 0, 0);
+}
+
+/** Set the local address used for stateful compression.
+ * This expects an address of 6 bytes.
+ */
+err_t
+rfc7668_set_local_addr_mac48(struct netif *netif, const u8_t *local_addr, size_t local_addr_len, int is_public_addr)
+{
+  /* netif not used for now, the address is stored globally... */
+  LWIP_UNUSED_ARG(netif);
+  return rfc7668_set_addr(&rfc7668_local_addr, local_addr, local_addr_len, 1, is_public_addr);
+}
+
+/** Set the peer address used for stateful compression.
+ * This expects an address of 8 bytes.
+ */
+err_t
+rfc7668_set_peer_addr_eui64(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len)
+{
+  /* netif not used for now, the address is stored globally... */
+  LWIP_UNUSED_ARG(netif);
+  return rfc7668_set_addr(&rfc7668_peer_addr, peer_addr, peer_addr_len, 0, 0);
+}
+
+/** Set the peer address used for stateful compression.
+ * This expects an address of 6 bytes.
+ */
+err_t
+rfc7668_set_peer_addr_mac48(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len, int is_public_addr)
+{
+  /* netif not used for now, the address is stored globally... */
+  LWIP_UNUSED_ARG(netif);
+  return rfc7668_set_addr(&rfc7668_peer_addr, peer_addr, peer_addr_len, 1, is_public_addr);
+}
+
+/** Encapsulate IPv6 frames for BLE transmission
+ * 
+ * This method implements the IPv6 header compression:
+ *  *) According to RFC6282
+ *  *) See Figure 2, contains base format of bit positions
+ *  *) Fragmentation not necessary (done at L2CAP layer of BLE)
+ * @note Currently the pbuf allocation uses 256 bytes. If longer packets are used (possible due to MTU=1480Bytes), increase it here!
+ * 
+ * @param p Pbuf struct, containing the payload data
+ * @param netif Output network interface. Should be of RFC7668 type
+ * 
+ * @return Same as netif->output.
+ */
+static err_t
+rfc7668_compress(struct netif *netif, struct pbuf *p)
+{
+  struct pbuf *p_frag;
+  u16_t remaining_len;
+  u8_t *buffer;
+  u8_t lowpan6_header_len;
+  u8_t hidden_header_len;
+  err_t err;
+
+  LWIP_ASSERT("lowpan6_frag: netif->linkoutput not set", netif->linkoutput != NULL);
+
+#if LWIP_6LOWPAN_IPHC
+
+  /* We'll use a dedicated pbuf for building BLE fragments.
+   * We'll over-allocate it by the bytes saved for header compression.
+   */
+  p_frag = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if (p_frag == NULL) {
+    MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("this needs a pbuf in one piece", p_frag->len == p_frag->tot_len);
+
+  /* Write IP6 header (with IPHC). */
+  buffer = (u8_t*)p_frag->payload;
+
+  err = lowpan6_compress_headers(netif, (u8_t *)p->payload, p->len, buffer, p_frag->len,
+    &lowpan6_header_len, &hidden_header_len, rfc7668_context, &rfc7668_local_addr, &rfc7668_peer_addr);
+  if (err != ERR_OK) {
+    MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+    pbuf_free(p_frag);
+    return err;
+  }
+  pbuf_remove_header(p, hidden_header_len);
+
+  /* Calculate remaining packet length */
+  remaining_len = p->tot_len;
+
+  /* Copy IPv6 packet */
+  pbuf_copy_partial(p, buffer + lowpan6_header_len, remaining_len, 0);
+
+  /* Calculate frame length */
+  p_frag->len = p_frag->tot_len = remaining_len + lowpan6_header_len;
+
+  /* send the packet */
+  MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len);
+  LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG|LWIP_DBG_TRACE, ("rfc7668_output: sending packet %p\n", (void *)p));
+  err = netif->linkoutput(netif, p_frag);
+
+  pbuf_free(p_frag);
+
+  return err;
+#else /* LWIP_6LOWPAN_IPHC */
+  /* 6LoWPAN over BLE requires IPHC! */
+  return ERR_IF;
+#endif/* LWIP_6LOWPAN_IPHC */
+}
+
+/**
+ * @ingroup rfc7668if
+ * Set context id IPv6 address
+ *
+ * Store one IPv6 address to a given context id.
+ *
+ * @param idx Context id
+ * @param context IPv6 addr for this context
+ *
+ * @return ERR_OK (if everything is fine), ERR_ARG (if the context id is out of range), ERR_VAL (if contexts disabled)
+ */
+err_t
+rfc7668_set_context(u8_t idx, const ip6_addr_t *context)
+{
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+  /* check if the ID is possible */
+  if (idx >= LWIP_6LOWPAN_NUM_CONTEXTS) {
+    return ERR_ARG;
+  }
+  /* copy IPv6 address to context storage */
+  ip6_addr_set(&rfc7668_context[idx], context);
+  return ERR_OK;
+#else
+  LWIP_UNUSED_ARG(idx);
+  LWIP_UNUSED_ARG(context);
+  return ERR_VAL;
+#endif
+}
+
+/**
+ * @ingroup rfc7668if
+ * Compress outgoing IPv6 packet and pass it on to netif->linkoutput
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param q The pbuf(s) containing the IP packet to be sent.
+ * @param ip6addr The IP address of the packet destination.
+ *
+ * @return See rfc7668_compress
+ */
+err_t
+rfc7668_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr)
+{
+  /* dst ip6addr is not used here, we only have one peer */
+  LWIP_UNUSED_ARG(ip6addr);
+
+  return rfc7668_compress(netif, q);
+}
+
+/**
+ * @ingroup rfc7668if
+ * Process a received raw payload from an L2CAP channel
+ *
+ * @param p the received packet, p->payload pointing to the
+ *        IPv6 header (maybe compressed)
+ * @param netif the network interface on which the packet was received
+ * 
+ * @return ERR_OK if everything was fine
+ */
+err_t
+rfc7668_input(struct pbuf * p, struct netif *netif)
+{
+  u8_t * puc;
+
+  MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len);
+
+  /* Load first header byte */
+  puc = (u8_t*)p->payload;
+  
+  /* no IP header compression */
+  if (*puc == 0x41) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Completed packet, removing dispatch: 0x%2x \n", *puc));
+    /* This is a complete IPv6 packet, just skip header byte. */
+    pbuf_remove_header(p, 1);
+  /* IPHC header compression */
+  } else if ((*puc & 0xe0 )== 0x60) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Completed packet, decompress dispatch: 0x%2x \n", *puc));
+    /* IPv6 headers are compressed using IPHC. */
+    p = lowpan6_decompress(p, 0, rfc7668_context, &rfc7668_peer_addr, &rfc7668_local_addr);
+    /* if no pbuf is returned, handle as discarded packet */
+    if (p == NULL) {
+      MIB2_STATS_NETIF_INC(netif, ifindiscards);
+      return ERR_OK;
+    }
+  /* invalid header byte, discard */
+  } else {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Completed packet, discarding: 0x%2x \n", *puc));
+    MIB2_STATS_NETIF_INC(netif, ifindiscards);
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* @todo: distinguish unicast/multicast */
+  MIB2_STATS_NETIF_INC(netif, ifinucastpkts);
+
+#if LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG
+  {
+    u16_t i;
+    LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("IPv6 payload:\n"));
+    for (i = 0; i < p->len; i++) {
+      if ((i%4)==0) {
+        LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("\n"));
+      }
+      LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("%2X ", *((uint8_t *)p->payload+i)));
+    }
+    LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("\np->len: %d\n", p->len));
+  }
+#endif
+  /* pass data to ip6_input */
+  return ip6_input(p, netif);
+}
+
+/**
+ * @ingroup rfc7668if
+ * Initialize the netif
+ * 
+ * No flags are used (broadcast not possible, not ethernet, ...)
+ * The shortname for this netif is "BT"
+ *
+ * @param netif the network interface to be initialized as RFC7668 netif
+ * 
+ * @return ERR_OK if everything went fine
+ */
+err_t
+rfc7668_if_init(struct netif *netif)
+{
+  netif->name[0] = 'b';
+  netif->name[1] = 't';
+  /* local function as IPv6 output */
+  netif->output_ip6 = rfc7668_output;
+
+  MIB2_INIT_NETIF(netif, snmp_ifType_other, 0);
+
+  /* maximum transfer unit, set according to RFC7668 ch2.4 */
+  netif->mtu = 1280;
+
+  /* no flags set (no broadcast, ethernet,...)*/
+  netif->flags = 0;
+
+  /* everything fine */
+  return ERR_OK;
+}
+
+#if !NO_SYS
+/**
+ * Pass a received packet to tcpip_thread for input processing
+ *
+ * @param p the received packet, p->payload pointing to the
+ *          IEEE 802.15.4 header.
+ * @param inp the network interface on which the packet was received
+ * 
+ * @return see @ref tcpip_inpkt, same return values
+ */
+err_t
+tcpip_rfc7668_input(struct pbuf *p, struct netif *inp)
+{
+  /* send data to upper layer, return the result */
+  return tcpip_inpkt(p, inp, rfc7668_input);
+}
+#endif /* !NO_SYS */
+
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6_common.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6_common.c
new file mode 100644
index 000000000..baea206a7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/lowpan6_common.c
@@ -0,0 +1,841 @@
+/**
+ * @file
+ *
+ * Common 6LowPAN routines for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
+ *
+ * This implementation aims to conform to IEEE 802.15.4(-2015), RFC 4944 and RFC 6282.
+ * @todo: RFC 6775.
+ */
+
+/*
+ * Copyright (c) 2015 Inico Technologies Ltd.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Ivan Delamer <delamer@inicotech.com>
+ *
+ *
+ * Please coordinate changes and requests with Ivan Delamer
+ * <delamer@inicotech.com>
+ */
+
+/**
+ * @defgroup sixlowpan 6LoWPAN (RFC4944)
+ * @ingroup netifs
+ * 6LowPAN netif implementation
+ */
+
+#include "netif/lowpan6_common.h"
+
+#if LWIP_IPV6
+
+#include "lwip/ip.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+#include <string.h>
+
+/* Determine compression mode for unicast address. */
+s8_t
+lowpan6_get_address_mode(const ip6_addr_t *ip6addr, const struct lowpan6_link_addr *mac_addr)
+{
+  if (mac_addr->addr_len == 2) {
+    if ((ip6addr->addr[2] == (u32_t)PP_HTONL(0x000000ff)) &&
+        ((ip6addr->addr[3]  & PP_HTONL(0xffff0000)) == PP_NTOHL(0xfe000000))) {
+      if ((ip6addr->addr[3]  & PP_HTONL(0x0000ffff)) == lwip_ntohl((mac_addr->addr[0] << 8) | mac_addr->addr[1])) {
+        return 3;
+      }
+    }
+  } else if (mac_addr->addr_len == 8) {
+    if ((ip6addr->addr[2] == lwip_ntohl(((mac_addr->addr[0] ^ 2) << 24) | (mac_addr->addr[1] << 16) | mac_addr->addr[2] << 8 | mac_addr->addr[3])) &&
+        (ip6addr->addr[3] == lwip_ntohl((mac_addr->addr[4] << 24) | (mac_addr->addr[5] << 16) | mac_addr->addr[6] << 8 | mac_addr->addr[7]))) {
+      return 3;
+    }
+  }
+
+  if ((ip6addr->addr[2] == PP_HTONL(0x000000ffUL)) &&
+      ((ip6addr->addr[3]  & PP_HTONL(0xffff0000)) == PP_NTOHL(0xfe000000UL))) {
+    return 2;
+  }
+
+  return 1;
+}
+
+#if LWIP_6LOWPAN_IPHC
+
+/* Determine compression mode for multicast address. */
+static s8_t
+lowpan6_get_address_mode_mc(const ip6_addr_t *ip6addr)
+{
+  if ((ip6addr->addr[0] == PP_HTONL(0xff020000)) &&
+      (ip6addr->addr[1] == 0) &&
+      (ip6addr->addr[2] == 0) &&
+      ((ip6addr->addr[3]  & PP_HTONL(0xffffff00)) == 0)) {
+    return 3;
+  } else if (((ip6addr->addr[0] & PP_HTONL(0xff00ffff)) == PP_HTONL(0xff000000)) &&
+             (ip6addr->addr[1] == 0)) {
+    if ((ip6addr->addr[2] == 0) &&
+        ((ip6addr->addr[3]  & PP_HTONL(0xff000000)) == 0)) {
+      return 2;
+    } else if ((ip6addr->addr[2]  & PP_HTONL(0xffffff00)) == 0) {
+      return 1;
+    }
+  }
+
+  return 0;
+}
+
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+static s8_t
+lowpan6_context_lookup(const ip6_addr_t *lowpan6_contexts, const ip6_addr_t *ip6addr)
+{
+  s8_t i;
+
+  for (i = 0; i < LWIP_6LOWPAN_NUM_CONTEXTS; i++) {
+    if (ip6_addr_netcmp(&lowpan6_contexts[i], ip6addr)) {
+      return i;
+    }
+  }
+  return -1;
+}
+#endif /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */
+
+/*
+ * Compress IPv6 and/or UDP headers.
+ * */
+err_t
+lowpan6_compress_headers(struct netif *netif, u8_t *inbuf, size_t inbuf_size, u8_t *outbuf, size_t outbuf_size,
+                         u8_t *lowpan6_header_len_out, u8_t *hidden_header_len_out, ip6_addr_t *lowpan6_contexts,
+                         const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst)
+{
+  u8_t *buffer, *inptr;
+  u8_t lowpan6_header_len;
+  u8_t hidden_header_len = 0;
+  s8_t i;
+  struct ip6_hdr *ip6hdr;
+  ip_addr_t ip6src, ip6dst;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_ASSERT("inbuf != NULL", inbuf != NULL);
+  LWIP_ASSERT("outbuf != NULL", outbuf != NULL);
+  LWIP_ASSERT("lowpan6_header_len_out != NULL", lowpan6_header_len_out != NULL);
+  LWIP_ASSERT("hidden_header_len_out != NULL", hidden_header_len_out != NULL);
+
+  /* Perform 6LowPAN IPv6 header compression according to RFC 6282 */
+  buffer = outbuf;
+  inptr = inbuf;
+
+  if (inbuf_size < IP6_HLEN) {
+    /* input buffer too short */
+    return ERR_VAL;
+  }
+  if (outbuf_size < IP6_HLEN) {
+    /* output buffer too short for worst case */
+    return ERR_MEM;
+  }
+
+  /* Point to ip6 header and align copies of src/dest addresses. */
+  ip6hdr = (struct ip6_hdr *)inptr;
+  ip_addr_copy_from_ip6_packed(ip6dst, ip6hdr->dest);
+  ip6_addr_assign_zone(ip_2_ip6(&ip6dst), IP6_UNKNOWN, netif);
+  ip_addr_copy_from_ip6_packed(ip6src, ip6hdr->src);
+  ip6_addr_assign_zone(ip_2_ip6(&ip6src), IP6_UNKNOWN, netif);
+
+  /* Basic length of 6LowPAN header, set dispatch and clear fields. */
+  lowpan6_header_len = 2;
+  buffer[0] = 0x60;
+  buffer[1] = 0;
+
+  /* Determine whether there will be a Context Identifier Extension byte or not.
+   * If so, set it already. */
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+  buffer[2] = 0;
+
+  i = lowpan6_context_lookup(lowpan6_contexts, ip_2_ip6(&ip6src));
+  if (i >= 0) {
+    /* Stateful source address compression. */
+    buffer[1] |= 0x40;
+    buffer[2] |= (i & 0x0f) << 4;
+  }
+
+  i = lowpan6_context_lookup(lowpan6_contexts, ip_2_ip6(&ip6dst));
+  if (i >= 0) {
+    /* Stateful destination address compression. */
+    buffer[1] |= 0x04;
+    buffer[2] |= i & 0x0f;
+  }
+
+  if (buffer[2] != 0x00) {
+    /* Context identifier extension byte is appended. */
+    buffer[1] |= 0x80;
+    lowpan6_header_len++;
+  }
+#else /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */
+  LWIP_UNUSED_ARG(lowpan6_contexts);
+#endif /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */
+
+  /* Determine TF field: Traffic Class, Flow Label */
+  if (IP6H_FL(ip6hdr) == 0) {
+    /* Flow label is elided. */
+    buffer[0] |= 0x10;
+    if (IP6H_TC(ip6hdr) == 0) {
+      /* Traffic class (ECN+DSCP) elided too. */
+      buffer[0] |= 0x08;
+    } else {
+      /* Traffic class (ECN+DSCP) appended. */
+      buffer[lowpan6_header_len++] = IP6H_TC(ip6hdr);
+    }
+  } else {
+    if (((IP6H_TC(ip6hdr) & 0x3f) == 0)) {
+      /* DSCP portion of Traffic Class is elided, ECN and FL are appended (3 bytes) */
+      buffer[0] |= 0x08;
+
+      buffer[lowpan6_header_len] = IP6H_TC(ip6hdr) & 0xc0;
+      buffer[lowpan6_header_len++] |= (IP6H_FL(ip6hdr) >> 16) & 0x0f;
+      buffer[lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 8) & 0xff;
+      buffer[lowpan6_header_len++] = IP6H_FL(ip6hdr) & 0xff;
+    } else {
+      /* Traffic class and flow label are appended (4 bytes) */
+      buffer[lowpan6_header_len++] = IP6H_TC(ip6hdr);
+      buffer[lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 16) & 0x0f;
+      buffer[lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 8) & 0xff;
+      buffer[lowpan6_header_len++] = IP6H_FL(ip6hdr) & 0xff;
+    }
+  }
+
+  /* Compress NH?
+  * Only if UDP for now. @todo support other NH compression. */
+  if (IP6H_NEXTH(ip6hdr) == IP6_NEXTH_UDP) {
+    buffer[0] |= 0x04;
+  } else {
+    /* append nexth. */
+    buffer[lowpan6_header_len++] = IP6H_NEXTH(ip6hdr);
+  }
+
+  /* Compress hop limit? */
+  if (IP6H_HOPLIM(ip6hdr) == 255) {
+    buffer[0] |= 0x03;
+  } else if (IP6H_HOPLIM(ip6hdr) == 64) {
+    buffer[0] |= 0x02;
+  } else if (IP6H_HOPLIM(ip6hdr) == 1) {
+    buffer[0] |= 0x01;
+  } else {
+    /* append hop limit */
+    buffer[lowpan6_header_len++] = IP6H_HOPLIM(ip6hdr);
+  }
+
+  /* Compress source address */
+  if (((buffer[1] & 0x40) != 0) ||
+      (ip6_addr_islinklocal(ip_2_ip6(&ip6src)))) {
+    /* Context-based or link-local source address compression. */
+    i = lowpan6_get_address_mode(ip_2_ip6(&ip6src), src);
+    buffer[1] |= (i & 0x03) << 4;
+    if (i == 1) {
+      MEMCPY(buffer + lowpan6_header_len, inptr + 16, 8);
+      lowpan6_header_len += 8;
+    } else if (i == 2) {
+      MEMCPY(buffer + lowpan6_header_len, inptr + 22, 2);
+      lowpan6_header_len += 2;
+    }
+  } else if (ip6_addr_isany(ip_2_ip6(&ip6src))) {
+    /* Special case: mark SAC and leave SAM=0 */
+    buffer[1] |= 0x40;
+  } else {
+    /* Append full address. */
+    MEMCPY(buffer + lowpan6_header_len, inptr + 8, 16);
+    lowpan6_header_len += 16;
+  }
+
+  /* Compress destination address */
+  if (ip6_addr_ismulticast(ip_2_ip6(&ip6dst))) {
+    /* @todo support stateful multicast address compression */
+
+    buffer[1] |= 0x08;
+
+    i = lowpan6_get_address_mode_mc(ip_2_ip6(&ip6dst));
+    buffer[1] |= i & 0x03;
+    if (i == 0) {
+      MEMCPY(buffer + lowpan6_header_len, inptr + 24, 16);
+      lowpan6_header_len += 16;
+    } else if (i == 1) {
+      buffer[lowpan6_header_len++] = inptr[25];
+      MEMCPY(buffer + lowpan6_header_len, inptr + 35, 5);
+      lowpan6_header_len += 5;
+    } else if (i == 2) {
+      buffer[lowpan6_header_len++] = inptr[25];
+      MEMCPY(buffer + lowpan6_header_len, inptr + 37, 3);
+      lowpan6_header_len += 3;
+    } else if (i == 3) {
+      buffer[lowpan6_header_len++] = (inptr)[39];
+    }
+  } else if (((buffer[1] & 0x04) != 0) ||
+              (ip6_addr_islinklocal(ip_2_ip6(&ip6dst)))) {
+    /* Context-based or link-local destination address compression. */
+    i = lowpan6_get_address_mode(ip_2_ip6(&ip6dst), dst);
+    buffer[1] |= i & 0x03;
+    if (i == 1) {
+      MEMCPY(buffer + lowpan6_header_len, inptr + 32, 8);
+      lowpan6_header_len += 8;
+    } else if (i == 2) {
+      MEMCPY(buffer + lowpan6_header_len, inptr + 38, 2);
+      lowpan6_header_len += 2;
+    }
+  } else {
+    /* Append full address. */
+    MEMCPY(buffer + lowpan6_header_len, inptr + 24, 16);
+    lowpan6_header_len += 16;
+  }
+
+  /* Move to payload. */
+  inptr += IP6_HLEN;
+  hidden_header_len += IP6_HLEN;
+
+#if LWIP_UDP
+  /* Compress UDP header? */
+  if (IP6H_NEXTH(ip6hdr) == IP6_NEXTH_UDP) {
+    /* @todo support optional checksum compression */
+
+    if (inbuf_size < IP6_HLEN + UDP_HLEN) {
+      /* input buffer too short */
+      return ERR_VAL;
+    }
+    if (outbuf_size < (size_t)(hidden_header_len + 7)) {
+      /* output buffer too short for worst case */
+      return ERR_MEM;
+    }
+
+    buffer[lowpan6_header_len] = 0xf0;
+
+    /* determine port compression mode. */
+    if ((inptr[0] == 0xf0) && ((inptr[1] & 0xf0) == 0xb0) &&
+        (inptr[2] == 0xf0) && ((inptr[3] & 0xf0) == 0xb0)) {
+      /* Compress source and dest ports. */
+      buffer[lowpan6_header_len++] |= 0x03;
+      buffer[lowpan6_header_len++] = ((inptr[1] & 0x0f) << 4) | (inptr[3] & 0x0f);
+    } else if (inptr[0] == 0xf0) {
+      /* Compress source port. */
+      buffer[lowpan6_header_len++] |= 0x02;
+      buffer[lowpan6_header_len++] = inptr[1];
+      buffer[lowpan6_header_len++] = inptr[2];
+      buffer[lowpan6_header_len++] = inptr[3];
+    } else if (inptr[2] == 0xf0) {
+      /* Compress dest port. */
+      buffer[lowpan6_header_len++] |= 0x01;
+      buffer[lowpan6_header_len++] = inptr[0];
+      buffer[lowpan6_header_len++] = inptr[1];
+      buffer[lowpan6_header_len++] = inptr[3];
+    } else {
+      /* append full ports. */
+      lowpan6_header_len++;
+      buffer[lowpan6_header_len++] = inptr[0];
+      buffer[lowpan6_header_len++] = inptr[1];
+      buffer[lowpan6_header_len++] = inptr[2];
+      buffer[lowpan6_header_len++] = inptr[3];
+    }
+
+    /* elide length and copy checksum */
+    buffer[lowpan6_header_len++] = inptr[6];
+    buffer[lowpan6_header_len++] = inptr[7];
+
+    hidden_header_len += UDP_HLEN;
+  }
+#endif /* LWIP_UDP */
+
+  *lowpan6_header_len_out = lowpan6_header_len;
+  *hidden_header_len_out = hidden_header_len;
+
+  return ERR_OK;
+}
+
+/** Decompress IPv6 and UDP headers compressed according to RFC 6282
+ *
+ * @param lowpan6_buffer compressed headers, first byte is the dispatch byte
+ * @param lowpan6_bufsize size of lowpan6_buffer (may include data after headers)
+ * @param decomp_buffer buffer where the decompressed headers are stored
+ * @param decomp_bufsize size of decomp_buffer
+ * @param hdr_size_comp returns the size of the compressed headers (skip to get to data)
+ * @param hdr_size_decomp returns the size of the decompressed headers (IPv6 + UDP)
+ * @param datagram_size datagram size from fragments or 0 if unfragmented
+ * @param compressed_size compressed datagram size (for unfragmented rx)
+ * @param lowpan6_contexts context addresses
+ * @param src source address of the outer layer, used for address compression
+ * @param dest destination address of the outer layer, used for address compression
+ * @return ERR_OK if decompression succeeded, an error otherwise
+ */
+static err_t
+lowpan6_decompress_hdr(u8_t *lowpan6_buffer, size_t lowpan6_bufsize,
+                       u8_t *decomp_buffer, size_t decomp_bufsize,
+                       u16_t *hdr_size_comp, u16_t *hdr_size_decomp,
+                       u16_t datagram_size, u16_t compressed_size,
+                       ip6_addr_t *lowpan6_contexts,
+                       struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest)
+{
+  u16_t lowpan6_offset;
+  struct ip6_hdr *ip6hdr;
+  s8_t i;
+  u32_t header_temp;
+  u16_t ip6_offset = IP6_HLEN;
+
+  LWIP_ASSERT("lowpan6_buffer != NULL", lowpan6_buffer != NULL);
+  LWIP_ASSERT("decomp_buffer != NULL", decomp_buffer != NULL);
+  LWIP_ASSERT("src != NULL", src != NULL);
+  LWIP_ASSERT("dest != NULL", dest != NULL);
+  LWIP_ASSERT("hdr_size_comp != NULL", hdr_size_comp != NULL);
+  LWIP_ASSERT("dehdr_size_decompst != NULL", hdr_size_decomp != NULL);
+
+  ip6hdr = (struct ip6_hdr *)decomp_buffer;
+  if (decomp_bufsize < IP6_HLEN) {
+    return ERR_MEM;
+  }
+
+  /* output the full compressed packet, if set in @see lowpan6_opts.h */
+#if LWIP_LOWPAN6_IP_COMPRESSED_DEBUG
+  {
+    u16_t j;
+    LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("lowpan6_decompress_hdr: IP6 payload (compressed): \n"));
+    for (j = 0; j < lowpan6_bufsize; j++) {
+      if ((j % 4) == 0) {
+        LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("\n"));
+      }
+      LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("%2X ", lowpan6_buffer[j]));
+    }
+    LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("\np->len: %d", lowpan6_bufsize));
+  }
+#endif
+
+  /* offset for inline IP headers (RFC 6282 ch3)*/
+  lowpan6_offset = 2;
+  /* if CID is set (context identifier), the context byte 
+   * follows immediately after the header, so other IPHC fields are @+3 */
+  if (lowpan6_buffer[1] & 0x80) {
+    lowpan6_offset++;
+  }
+
+  /* Set IPv6 version, traffic class and flow label. (RFC6282, ch 3.1.1.)*/
+  if ((lowpan6_buffer[0] & 0x18) == 0x00) {
+    header_temp = ((lowpan6_buffer[lowpan6_offset+1] & 0x0f) << 16) | \
+      (lowpan6_buffer[lowpan6_offset + 2] << 8) | lowpan6_buffer[lowpan6_offset+3];
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 00, ECN: 0x%2x, Flowlabel+DSCP: 0x%8X\n", \
+      lowpan6_buffer[lowpan6_offset],header_temp));
+    IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset], header_temp);
+    /* increase offset, processed 4 bytes here:
+     * TF=00:  ECN + DSCP + 4-bit Pad + Flow Label (4 bytes)*/
+    lowpan6_offset += 4;
+  } else if ((lowpan6_buffer[0] & 0x18) == 0x08) {
+    header_temp = ((lowpan6_buffer[lowpan6_offset] & 0x0f) << 16) | (lowpan6_buffer[lowpan6_offset + 1] << 8) | lowpan6_buffer[lowpan6_offset+2];
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 01, ECN: 0x%2x, Flowlabel: 0x%2X, DSCP ignored\n", \
+      lowpan6_buffer[lowpan6_offset] & 0xc0,header_temp));
+    IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset] & 0xc0, header_temp);
+    /* increase offset, processed 3 bytes here:
+     * TF=01:  ECN + 2-bit Pad + Flow Label (3 bytes), DSCP is elided.*/
+    lowpan6_offset += 3;
+  } else if ((lowpan6_buffer[0] & 0x18) == 0x10) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 10, DCSP+ECN: 0x%2x, Flowlabel ignored\n", lowpan6_buffer[lowpan6_offset]));
+    IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset],0);
+    /* increase offset, processed 1 byte here:
+     * ECN + DSCP (1 byte), Flow Label is elided.*/
+    lowpan6_offset += 1;
+  } else if ((lowpan6_buffer[0] & 0x18) == 0x18) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 11, DCSP/ECN & Flowlabel ignored\n"));
+    /* don't increase offset, no bytes processed here */
+    IP6H_VTCFL_SET(ip6hdr, 6, 0, 0);
+  }
+
+  /* Set Next Header (NH) */
+  if ((lowpan6_buffer[0] & 0x04) == 0x00) {
+    /* 0: full next header byte carried inline (increase offset)*/
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NH: 0x%2X\n", lowpan6_buffer[lowpan6_offset+1]));
+    IP6H_NEXTH_SET(ip6hdr, lowpan6_buffer[lowpan6_offset++]);
+  } else {
+    /* 1: NH compression, LOWPAN_NHC (RFC6282, ch 4.1) */
+    /* We should fill this later with NHC decoding */
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NH: skipped, later done with NHC\n"));
+    IP6H_NEXTH_SET(ip6hdr, 0);
+  }
+
+  /* Set Hop Limit, either carried inline or 3 different hops (1,64,255) */
+  if ((lowpan6_buffer[0] & 0x03) == 0x00) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: full value: %d\n", lowpan6_buffer[lowpan6_offset+1]));
+    IP6H_HOPLIM_SET(ip6hdr, lowpan6_buffer[lowpan6_offset++]);
+  } else if ((lowpan6_buffer[0] & 0x03) == 0x01) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: compressed: 1\n"));
+    IP6H_HOPLIM_SET(ip6hdr, 1);
+  } else if ((lowpan6_buffer[0] & 0x03) == 0x02) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: compressed: 64\n"));
+    IP6H_HOPLIM_SET(ip6hdr, 64);
+  } else if ((lowpan6_buffer[0] & 0x03) == 0x03) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: compressed: 255\n"));
+    IP6H_HOPLIM_SET(ip6hdr, 255);
+  }
+
+  /* Source address decoding. */
+  if ((lowpan6_buffer[1] & 0x40) == 0x00) {
+    /* Source address compression (SAC) = 0 -> stateless compression */
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAC == 0, no context byte\n"));
+    /* Stateless compression */
+    if ((lowpan6_buffer[1] & 0x30) == 0x00) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 00, no src compression, fetching 128bits inline\n"));
+      /* copy full address, increase offset by 16 Bytes */
+      MEMCPY(&ip6hdr->src.addr[0], lowpan6_buffer + lowpan6_offset, 16);
+      lowpan6_offset += 16;
+    } else if ((lowpan6_buffer[1] & 0x30) == 0x10) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 01, src compression, 64bits inline\n"));
+      /* set 64 bits to link local */
+      ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL);
+      ip6hdr->src.addr[1] = 0;
+      /* copy 8 Bytes, increase offset */
+      MEMCPY(&ip6hdr->src.addr[2], lowpan6_buffer + lowpan6_offset, 8);
+      lowpan6_offset += 8;
+    } else if ((lowpan6_buffer[1] & 0x30) == 0x20) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 10, src compression, 16bits inline\n"));
+      /* set 96 bits to link local */
+      ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL);
+      ip6hdr->src.addr[1] = 0;
+      ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL);
+      /* extract remaining 16bits from inline bytes, increase offset */
+      ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) |
+                                       lowpan6_buffer[lowpan6_offset + 1]);
+      lowpan6_offset += 2;
+    } else if ((lowpan6_buffer[1] & 0x30) == 0x30) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 11, src compression, 0bits inline, using other headers\n"));
+      /* no information avalaible, using other layers, see RFC6282 ch 3.2.2 */
+      ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL);
+      ip6hdr->src.addr[1] = 0;
+      if (src->addr_len == 2) {
+        ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL);
+        ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (src->addr[0] << 8) | src->addr[1]);
+      } else if (src->addr_len == 8) {
+        ip6hdr->src.addr[2] = lwip_htonl(((src->addr[0] ^ 2) << 24) | (src->addr[1] << 16) |
+                                         (src->addr[2] << 8) | src->addr[3]);
+        ip6hdr->src.addr[3] = lwip_htonl((src->addr[4] << 24) | (src->addr[5] << 16) |
+                                         (src->addr[6] << 8) | src->addr[7]);
+      } else {
+        /* invalid source address length */
+        LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Invalid source address length\n"));
+        return ERR_VAL;
+      }
+    }
+  } else {
+    /* Source address compression (SAC) = 1 -> stateful/context-based compression */
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAC == 1, additional context byte\n"));
+    if ((lowpan6_buffer[1] & 0x30) == 0x00) {
+      /* SAM=00, address=> :: (ANY) */
+      ip6hdr->src.addr[0] = 0;
+      ip6hdr->src.addr[1] = 0;
+      ip6hdr->src.addr[2] = 0;
+      ip6hdr->src.addr[3] = 0;
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 00, context compression, ANY (::)\n"));
+    } else {
+      /* Set prefix from context info */
+      if (lowpan6_buffer[1] & 0x80) {
+        i = (lowpan6_buffer[2] >> 4) & 0x0f;
+      } else {
+        i = 0;
+      }
+      if (i >= LWIP_6LOWPAN_NUM_CONTEXTS) {
+        /* Error */
+        return ERR_VAL;
+      }
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+      ip6hdr->src.addr[0] = lowpan6_contexts[i].addr[0];
+      ip6hdr->src.addr[1] = lowpan6_contexts[i].addr[1];
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == xx, context compression found @%d: %8X, %8X\n", (int)i, ip6hdr->src.addr[0], ip6hdr->src.addr[1]));
+#else
+      LWIP_UNUSED_ARG(lowpan6_contexts);
+#endif
+    }
+
+    /* determine further address bits */
+    if ((lowpan6_buffer[1] & 0x30) == 0x10) {
+      /* SAM=01, load additional 64bits */
+      MEMCPY(&ip6hdr->src.addr[2], lowpan6_buffer + lowpan6_offset, 8);
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 01, context compression, 64bits inline\n"));
+      lowpan6_offset += 8;
+    } else if ((lowpan6_buffer[1] & 0x30) == 0x20) {
+      /* SAM=01, load additional 16bits */
+      ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL);
+      ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | lowpan6_buffer[lowpan6_offset + 1]);
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 10, context compression, 16bits inline\n"));
+      lowpan6_offset += 2;
+    } else if ((lowpan6_buffer[1] & 0x30) == 0x30) {
+      /* SAM=11, address is fully elided, load from other layers */
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 11, context compression, 0bits inline, using other headers\n"));
+      if (src->addr_len == 2) {
+        ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL);
+        ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (src->addr[0] << 8) | src->addr[1]);
+      } else if (src->addr_len == 8) {
+        ip6hdr->src.addr[2] = lwip_htonl(((src->addr[0] ^ 2) << 24) | (src->addr[1] << 16) | (src->addr[2] << 8) | src->addr[3]);
+        ip6hdr->src.addr[3] = lwip_htonl((src->addr[4] << 24) | (src->addr[5] << 16) | (src->addr[6] << 8) | src->addr[7]);
+      } else {
+        /* invalid source address length */
+        LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Invalid source address length\n"));
+        return ERR_VAL;
+      }
+    }
+  }
+
+  /* Destination address decoding. */
+  if (lowpan6_buffer[1] & 0x08) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("M=1: multicast\n"));
+    /* Multicast destination */
+    if (lowpan6_buffer[1] & 0x04) {
+      LWIP_DEBUGF(LWIP_DBG_ON,("DAC == 1, context multicast: unsupported!!!\n"));
+      /* @todo support stateful multicast addressing */
+      return ERR_VAL;
+    }
+
+    if ((lowpan6_buffer[1] & 0x03) == 0x00) {
+      /* DAM = 00, copy full address (128bits) */
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 00, no dst compression, fetching 128bits inline\n"));
+      MEMCPY(&ip6hdr->dest.addr[0], lowpan6_buffer + lowpan6_offset, 16);
+      lowpan6_offset += 16;
+    } else if ((lowpan6_buffer[1] & 0x03) == 0x01) {
+      /* DAM = 01, copy 4 bytes (32bits) */
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 01, dst address form (48bits): ffXX::00XX:XXXX:XXXX\n"));
+      ip6hdr->dest.addr[0] = lwip_htonl(0xff000000UL | (lowpan6_buffer[lowpan6_offset++] << 16));
+      ip6hdr->dest.addr[1] = 0;
+      ip6hdr->dest.addr[2] = lwip_htonl(lowpan6_buffer[lowpan6_offset++]);
+      ip6hdr->dest.addr[3] = lwip_htonl((lowpan6_buffer[lowpan6_offset] << 24) | (lowpan6_buffer[lowpan6_offset + 1] << 16) | (lowpan6_buffer[lowpan6_offset + 2] << 8) | lowpan6_buffer[lowpan6_offset + 3]);
+      lowpan6_offset += 4;
+    } else if ((lowpan6_buffer[1] & 0x03) == 0x02) {
+      /* DAM = 10, copy 3 bytes (24bits) */
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 10, dst address form (32bits): ffXX::00XX:XXXX\n"));
+      ip6hdr->dest.addr[0] = lwip_htonl(0xff000000UL | (lowpan6_buffer[lowpan6_offset++] << 16));
+      ip6hdr->dest.addr[1] = 0;
+      ip6hdr->dest.addr[2] = 0;
+      ip6hdr->dest.addr[3] = lwip_htonl((lowpan6_buffer[lowpan6_offset] << 16) | (lowpan6_buffer[lowpan6_offset + 1] << 8) | lowpan6_buffer[lowpan6_offset + 2]);
+      lowpan6_offset += 3;
+    } else if ((lowpan6_buffer[1] & 0x03) == 0x03) {
+      /* DAM = 11, copy 1 byte (8bits) */
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 11, dst address form (8bits): ff02::00XX\n"));
+      ip6hdr->dest.addr[0] = PP_HTONL(0xff020000UL);
+      ip6hdr->dest.addr[1] = 0;
+      ip6hdr->dest.addr[2] = 0;
+      ip6hdr->dest.addr[3] = lwip_htonl(lowpan6_buffer[lowpan6_offset++]);
+    }
+
+  } else {
+    /* no Multicast (M=0) */
+    if (lowpan6_buffer[1] & 0x04) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAC == 1, stateful compression\n"));
+      /* Stateful destination compression */
+      /* Set prefix from context info */
+      if (lowpan6_buffer[1] & 0x80) {
+        i = lowpan6_buffer[2] & 0x0f;
+      } else {
+        i = 0;
+      }
+      if (i >= LWIP_6LOWPAN_NUM_CONTEXTS) {
+        /* Error */
+        return ERR_VAL;
+      }
+#if LWIP_6LOWPAN_NUM_CONTEXTS > 0
+      ip6hdr->dest.addr[0] = lowpan6_contexts[i].addr[0];
+      ip6hdr->dest.addr[1] = lowpan6_contexts[i].addr[1];
+#endif
+    } else {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAC == 0, stateless compression, setting link local prefix\n"));
+      /* Link local address compression */
+      ip6hdr->dest.addr[0] = PP_HTONL(0xfe800000UL);
+      ip6hdr->dest.addr[1] = 0;
+    }
+
+    /* M=0, DAC=0, determining destination address length via DAM=xx */
+    if ((lowpan6_buffer[1] & 0x03) == 0x00) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 00, no dst compression, fetching 128bits inline"));
+      /* DAM=00, copy full address */
+      MEMCPY(&ip6hdr->dest.addr[0], lowpan6_buffer + lowpan6_offset, 16);
+      lowpan6_offset += 16;
+    } else if ((lowpan6_buffer[1] & 0x03) == 0x01) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 01, dst compression, 64bits inline\n"));
+      /* DAM=01, copy 64 inline bits, increase offset */
+      MEMCPY(&ip6hdr->dest.addr[2], lowpan6_buffer + lowpan6_offset, 8);
+      lowpan6_offset += 8;
+    } else if ((lowpan6_buffer[1] & 0x03) == 0x02) {
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 01, dst compression, 16bits inline\n"));
+      /* DAM=10, copy 16 inline bits, increase offset */
+      ip6hdr->dest.addr[2] = PP_HTONL(0x000000ffUL);
+      ip6hdr->dest.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | lowpan6_buffer[lowpan6_offset + 1]);
+      lowpan6_offset += 2;
+    } else if ((lowpan6_buffer[1] & 0x03) == 0x03) {
+      /* DAM=11, no bits available, use other headers (not done here) */
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG,("DAM == 01, dst compression, 0bits inline, using other headers\n"));
+      if (dest->addr_len == 2) {
+        ip6hdr->dest.addr[2] = PP_HTONL(0x000000ffUL);
+        ip6hdr->dest.addr[3] = lwip_htonl(0xfe000000UL | (dest->addr[0] << 8) | dest->addr[1]);
+      } else if (dest->addr_len == 8) {
+        ip6hdr->dest.addr[2] = lwip_htonl(((dest->addr[0] ^ 2) << 24) | (dest->addr[1] << 16) | dest->addr[2] << 8 | dest->addr[3]);
+        ip6hdr->dest.addr[3] = lwip_htonl((dest->addr[4] << 24) | (dest->addr[5] << 16) | dest->addr[6] << 8 | dest->addr[7]);
+      } else {
+        /* invalid destination address length */
+        LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Invalid destination address length\n"));
+        return ERR_VAL;
+      }
+    }
+  }
+
+
+  /* Next Header Compression (NHC) decoding? */
+  if (lowpan6_buffer[0] & 0x04) {
+    LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NHC decoding\n"));
+#if LWIP_UDP
+    if ((lowpan6_buffer[lowpan6_offset] & 0xf8) == 0xf0) {
+      /* NHC: UDP */
+      struct udp_hdr *udphdr;
+      LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NHC: UDP\n"));
+
+      /* UDP compression */
+      IP6H_NEXTH_SET(ip6hdr, IP6_NEXTH_UDP);
+      udphdr = (struct udp_hdr *)((u8_t *)decomp_buffer + ip6_offset);
+      if (decomp_bufsize < IP6_HLEN + UDP_HLEN) {
+        return ERR_MEM;
+      }
+
+      /* Checksum decompression */
+      if (lowpan6_buffer[lowpan6_offset] & 0x04) {
+        /* @todo support checksum decompress */
+        LWIP_DEBUGF(LWIP_DBG_ON, ("NHC: UDP chechsum decompression UNSUPPORTED\n"));
+        return ERR_VAL;
+      }
+
+      /* Decompress ports, according to RFC4944 */
+      i = lowpan6_buffer[lowpan6_offset++] & 0x03;
+      if (i == 0) {
+        udphdr->src = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]);
+        udphdr->dest = lwip_htons(lowpan6_buffer[lowpan6_offset + 2] << 8 | lowpan6_buffer[lowpan6_offset + 3]);
+        lowpan6_offset += 4;
+      } else if (i == 0x01) {
+        udphdr->src = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]);
+        udphdr->dest = lwip_htons(0xf000 | lowpan6_buffer[lowpan6_offset + 2]);
+        lowpan6_offset += 3;
+      } else if (i == 0x02) {
+        udphdr->src = lwip_htons(0xf000 | lowpan6_buffer[lowpan6_offset]);
+        udphdr->dest = lwip_htons(lowpan6_buffer[lowpan6_offset + 1] << 8 | lowpan6_buffer[lowpan6_offset + 2]);
+        lowpan6_offset += 3;
+      } else if (i == 0x03) {
+        udphdr->src = lwip_htons(0xf0b0 | ((lowpan6_buffer[lowpan6_offset] >> 4) & 0x0f));
+        udphdr->dest = lwip_htons(0xf0b0 | (lowpan6_buffer[lowpan6_offset] & 0x0f));
+        lowpan6_offset += 1;
+      }
+
+      udphdr->chksum = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]);
+      lowpan6_offset += 2;
+      ip6_offset += UDP_HLEN;
+      if (datagram_size == 0) {
+        datagram_size = compressed_size - lowpan6_offset + ip6_offset;
+      }
+      udphdr->len = lwip_htons(datagram_size - IP6_HLEN);
+
+    } else
+#endif /* LWIP_UDP */
+    {
+      LWIP_DEBUGF(LWIP_DBG_ON,("NHC: unsupported protocol!\n"));
+      /* @todo support NHC other than UDP */
+      return ERR_VAL;
+    }
+  }
+  if (datagram_size == 0) {
+    datagram_size = compressed_size - lowpan6_offset + ip6_offset;
+  }
+  /* Infer IPv6 payload length for header */
+  IP6H_PLEN_SET(ip6hdr, datagram_size - IP6_HLEN);
+
+  if (lowpan6_offset > lowpan6_bufsize) {
+    /* input buffer overflow */
+    return ERR_VAL;
+  }
+  *hdr_size_comp = lowpan6_offset;
+  *hdr_size_decomp = ip6_offset;
+
+  return ERR_OK;
+}
+
+struct pbuf *
+lowpan6_decompress(struct pbuf *p, u16_t datagram_size, ip6_addr_t *lowpan6_contexts,
+                   struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest)
+{
+  struct pbuf *q;
+  u16_t lowpan6_offset, ip6_offset;
+  err_t err;
+
+#if LWIP_UDP
+#define UDP_HLEN_ALLOC UDP_HLEN
+#else
+#define UDP_HLEN_ALLOC 0
+#endif
+
+  /* Allocate a buffer for decompression. This buffer will be too big and will be
+     trimmed once the final size is known. */
+  q = pbuf_alloc(PBUF_IP, p->len + IP6_HLEN + UDP_HLEN_ALLOC, PBUF_POOL);
+  if (q == NULL) {
+    pbuf_free(p);
+    return NULL;
+  }
+  if (q->len < IP6_HLEN + UDP_HLEN_ALLOC) {
+    /* The headers need to fit into the first pbuf */
+    pbuf_free(p);
+    pbuf_free(q);
+    return NULL;
+  }
+
+  /* Decompress the IPv6 (and possibly UDP) header(s) into the new pbuf */
+  err = lowpan6_decompress_hdr((u8_t *)p->payload, p->len, (u8_t *)q->payload, q->len,
+    &lowpan6_offset, &ip6_offset, datagram_size, p->tot_len, lowpan6_contexts, src, dest);
+  if (err != ERR_OK) {
+    pbuf_free(p);
+    pbuf_free(q);
+    return NULL;
+  }
+
+  /* Now we copy leftover contents from p to q, so we have all L2 and L3 headers
+     (and L4?) in a single pbuf: */
+
+  /* Hide the compressed headers in p */
+  pbuf_remove_header(p, lowpan6_offset);
+  /* Temporarily hide the headers in q... */
+  pbuf_remove_header(q, ip6_offset);
+  /* ... copy the rest of p into q... */
+  pbuf_copy(q, p);
+  /* ... and reveal the headers again... */
+  pbuf_add_header_force(q, ip6_offset);
+  /* ... trim the pbuf to its correct size... */
+  pbuf_realloc(q, ip6_offset + p->len);
+  /* ... and cat possibly remaining (data-only) pbufs */
+  if (p->next != NULL) {
+    pbuf_cat(q, p->next);
+  }
+  /* the original (first) pbuf can now be freed */
+  p->next = NULL;
+  pbuf_free(p);
+
+  /* all done */
+  return q;
+}
+
+#endif /* LWIP_6LOWPAN_IPHC */
+#endif /* LWIP_IPV6 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/auth.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/auth.c
new file mode 100644
index 000000000..c8673ad0f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/auth.c
@@ -0,0 +1,2510 @@
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * Derived from main.c, which is:
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <errno.h>
+#include <pwd.h>
+#include <grp.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/socket.h>
+#include <utmp.h>
+#include <fcntl.h>
+#if defined(_PATH_LASTLOG) && defined(__linux__)
+#include <lastlog.h>
+#endif
+
+#include <netdb.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+
+#ifdef HAS_SHADOW
+#include <shadow.h>
+#ifndef PW_PPP
+#define PW_PPP PW_LOGIN
+#endif
+#endif
+
+#include <time.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/lcp.h"
+#if CCP_SUPPORT
+#include "netif/ppp/ccp.h"
+#endif /* CCP_SUPPORT */
+#if ECP_SUPPORT
+#include "netif/ppp/ecp.h"
+#endif /* ECP_SUPPORT */
+#include "netif/ppp/ipcp.h"
+#if PAP_SUPPORT
+#include "netif/ppp/upap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "netif/ppp/chap-new.h"
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#include "netif/ppp/eap.h"
+#endif /* EAP_SUPPORT */
+#if CBCP_SUPPORT
+#include "netif/ppp/cbcp.h"
+#endif
+
+#if 0 /* UNUSED */
+#include "session.h"
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+/* Bits in scan_authfile return value */
+#define NONWILD_SERVER	1
+#define NONWILD_CLIENT	2
+
+#define ISWILD(word)	(word[0] == '*' && word[1] == 0)
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+/* List of addresses which the peer may use. */
+static struct permitted_ip *addresses[NUM_PPP];
+
+/* Wordlist giving addresses which the peer may use
+   without authenticating itself. */
+static struct wordlist *noauth_addrs;
+
+/* Remote telephone number, if available */
+char remote_number[MAXNAMELEN];
+
+/* Wordlist giving remote telephone numbers which may connect. */
+static struct wordlist *permitted_numbers;
+
+/* Extra options to apply, from the secrets file entry for the peer. */
+static struct wordlist *extra_options;
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+/* Set if we require authentication only because we have a default route. */
+static bool default_auth;
+
+/* Hook to enable a plugin to control the idle time limit */
+int (*idle_time_hook) (struct ppp_idle *) = NULL;
+
+/* Hook for a plugin to say whether we can possibly authenticate any peer */
+int (*pap_check_hook) (void) = NULL;
+
+/* Hook for a plugin to check the PAP user and password */
+int (*pap_auth_hook) (char *user, char *passwd, char **msgp,
+			  struct wordlist **paddrs,
+			  struct wordlist **popts) = NULL;
+
+/* Hook for a plugin to know about the PAP user logout */
+void (*pap_logout_hook) (void) = NULL;
+
+/* Hook for a plugin to get the PAP password for authenticating us */
+int (*pap_passwd_hook) (char *user, char *passwd) = NULL;
+
+/* Hook for a plugin to say if we can possibly authenticate a peer using CHAP */
+int (*chap_check_hook) (void) = NULL;
+
+/* Hook for a plugin to get the CHAP password for authenticating us */
+int (*chap_passwd_hook) (char *user, char *passwd) = NULL;
+
+/* Hook for a plugin to say whether it is OK if the peer
+   refuses to authenticate. */
+int (*null_auth_hook) (struct wordlist **paddrs,
+			   struct wordlist **popts) = NULL;
+
+int (*allowed_address_hook) (u32_t addr) = NULL;
+#endif /* UNUSED */
+
+#ifdef HAVE_MULTILINK
+/* Hook for plugin to hear when an interface joins a multilink bundle */
+void (*multilink_join_hook) (void) = NULL;
+#endif
+
+#if PPP_NOTIFY
+/* A notifier for when the peer has authenticated itself,
+   and we are proceeding to the network phase. */
+struct notifier *auth_up_notifier = NULL;
+
+/* A notifier for when the link goes down. */
+struct notifier *link_down_notifier = NULL;
+#endif /* PPP_NOTIFY */
+
+/*
+ * Option variables.
+ */
+#if 0 /* MOVED TO ppp_settings */
+bool uselogin = 0;		/* Use /etc/passwd for checking PAP */
+bool session_mgmt = 0;		/* Do session management (login records) */
+bool cryptpap = 0;		/* Passwords in pap-secrets are encrypted */
+bool refuse_pap = 0;		/* Don't wanna auth. ourselves with PAP */
+bool refuse_chap = 0;		/* Don't wanna auth. ourselves with CHAP */
+bool refuse_eap = 0;		/* Don't wanna auth. ourselves with EAP */
+#if MSCHAP_SUPPORT
+bool refuse_mschap = 0;		/* Don't wanna auth. ourselves with MS-CHAP */
+bool refuse_mschap_v2 = 0;	/* Don't wanna auth. ourselves with MS-CHAPv2 */
+#else /* MSCHAP_SUPPORT */
+bool refuse_mschap = 1;		/* Don't wanna auth. ourselves with MS-CHAP */
+bool refuse_mschap_v2 = 1;	/* Don't wanna auth. ourselves with MS-CHAPv2 */
+#endif /* MSCHAP_SUPPORT */
+bool usehostname = 0;		/* Use hostname for our_name */
+bool auth_required = 0;		/* Always require authentication from peer */
+bool allow_any_ip = 0;		/* Allow peer to use any IP address */
+bool explicit_remote = 0;	/* User specified explicit remote name */
+bool explicit_user = 0;		/* Set if "user" option supplied */
+bool explicit_passwd = 0;	/* Set if "password" option supplied */
+char remote_name[MAXNAMELEN];	/* Peer's name for authentication */
+static char *uafname;		/* name of most recent +ua file */
+
+extern char *crypt (const char *, const char *);
+#endif /* UNUSED */
+/* Prototypes for procedures local to this file. */
+
+static void network_phase(ppp_pcb *pcb);
+#if PPP_IDLETIMELIMIT
+static void check_idle(void *arg);
+#endif /* PPP_IDLETIMELIMIT */
+#if PPP_MAXCONNECT
+static void connect_time_expired(void *arg);
+#endif /* PPP_MAXCONNECT */
+#if 0 /* UNUSED */
+static int  null_login (int);
+/* static int  get_pap_passwd (char *); */
+static int  have_pap_secret (int *);
+static int  have_chap_secret (char *, char *, int, int *);
+static int  have_srp_secret (char *client, char *server, int need_ip,
+    int *lacks_ipp);
+static int  ip_addr_check (u32_t, struct permitted_ip *);
+static int  scan_authfile (FILE *, char *, char *, char *,
+			       struct wordlist **, struct wordlist **,
+			       char *, int);
+static void free_wordlist (struct wordlist *);
+static void set_allowed_addrs (int, struct wordlist *, struct wordlist *);
+static int  some_ip_ok (struct wordlist *);
+static int  setupapfile (char **);
+static int  privgroup (char **);
+static int  set_noauth_addr (char **);
+static int  set_permitted_number (char **);
+static void check_access (FILE *, char *);
+static int  wordlist_count (struct wordlist *);
+#endif /* UNUSED */
+
+#ifdef MAXOCTETS
+static void check_maxoctets (void *);
+#endif
+
+#if PPP_OPTIONS
+/*
+ * Authentication-related options.
+ */
+option_t auth_options[] = {
+    { "auth", o_bool, &auth_required,
+      "Require authentication from peer", OPT_PRIO | 1 },
+    { "noauth", o_bool, &auth_required,
+      "Don't require peer to authenticate", OPT_PRIOSUB | OPT_PRIV,
+      &allow_any_ip },
+    { "require-pap", o_bool, &lcp_wantoptions[0].neg_upap,
+      "Require PAP authentication from peer",
+      OPT_PRIOSUB | 1, &auth_required },
+    { "+pap", o_bool, &lcp_wantoptions[0].neg_upap,
+      "Require PAP authentication from peer",
+      OPT_ALIAS | OPT_PRIOSUB | 1, &auth_required },
+    { "require-chap", o_bool, &auth_required,
+      "Require CHAP authentication from peer",
+      OPT_PRIOSUB | OPT_A2OR | MDTYPE_MD5,
+      &lcp_wantoptions[0].chap_mdtype },
+    { "+chap", o_bool, &auth_required,
+      "Require CHAP authentication from peer",
+      OPT_ALIAS | OPT_PRIOSUB | OPT_A2OR | MDTYPE_MD5,
+      &lcp_wantoptions[0].chap_mdtype },
+#if MSCHAP_SUPPORT
+    { "require-mschap", o_bool, &auth_required,
+      "Require MS-CHAP authentication from peer",
+      OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT,
+      &lcp_wantoptions[0].chap_mdtype },
+    { "+mschap", o_bool, &auth_required,
+      "Require MS-CHAP authentication from peer",
+      OPT_ALIAS | OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT,
+      &lcp_wantoptions[0].chap_mdtype },
+    { "require-mschap-v2", o_bool, &auth_required,
+      "Require MS-CHAPv2 authentication from peer",
+      OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT_V2,
+      &lcp_wantoptions[0].chap_mdtype },
+    { "+mschap-v2", o_bool, &auth_required,
+      "Require MS-CHAPv2 authentication from peer",
+      OPT_ALIAS | OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT_V2,
+      &lcp_wantoptions[0].chap_mdtype },
+#endif /* MSCHAP_SUPPORT */
+#if 0
+    { "refuse-pap", o_bool, &refuse_pap,
+      "Don't agree to auth to peer with PAP", 1 },
+    { "-pap", o_bool, &refuse_pap,
+      "Don't allow PAP authentication with peer", OPT_ALIAS | 1 },
+    { "refuse-chap", o_bool, &refuse_chap,
+      "Don't agree to auth to peer with CHAP",
+      OPT_A2CLRB | MDTYPE_MD5,
+      &lcp_allowoptions[0].chap_mdtype },
+    { "-chap", o_bool, &refuse_chap,
+      "Don't allow CHAP authentication with peer",
+      OPT_ALIAS | OPT_A2CLRB | MDTYPE_MD5,
+      &lcp_allowoptions[0].chap_mdtype },
+#endif
+#if MSCHAP_SUPPORT
+#if 0
+    { "refuse-mschap", o_bool, &refuse_mschap,
+      "Don't agree to auth to peer with MS-CHAP",
+      OPT_A2CLRB | MDTYPE_MICROSOFT,
+      &lcp_allowoptions[0].chap_mdtype },
+    { "-mschap", o_bool, &refuse_mschap,
+      "Don't allow MS-CHAP authentication with peer",
+      OPT_ALIAS | OPT_A2CLRB | MDTYPE_MICROSOFT,
+      &lcp_allowoptions[0].chap_mdtype },
+    { "refuse-mschap-v2", o_bool, &refuse_mschap_v2,
+      "Don't agree to auth to peer with MS-CHAPv2",
+      OPT_A2CLRB | MDTYPE_MICROSOFT_V2,
+      &lcp_allowoptions[0].chap_mdtype },
+    { "-mschap-v2", o_bool, &refuse_mschap_v2,
+      "Don't allow MS-CHAPv2 authentication with peer",
+      OPT_ALIAS | OPT_A2CLRB | MDTYPE_MICROSOFT_V2,
+      &lcp_allowoptions[0].chap_mdtype },
+#endif
+#endif /* MSCHAP_SUPPORT*/
+#if EAP_SUPPORT
+    { "require-eap", o_bool, &lcp_wantoptions[0].neg_eap,
+      "Require EAP authentication from peer", OPT_PRIOSUB | 1,
+      &auth_required },
+#if 0
+    { "refuse-eap", o_bool, &refuse_eap,
+      "Don't agree to authenticate to peer with EAP", 1 },
+#endif
+#endif /* EAP_SUPPORT */
+    { "name", o_string, our_name,
+      "Set local name for authentication",
+      OPT_PRIO | OPT_PRIV | OPT_STATIC, NULL, MAXNAMELEN },
+
+    { "+ua", o_special, (void *)setupapfile,
+      "Get PAP user and password from file",
+      OPT_PRIO | OPT_A2STRVAL, &uafname },
+
+#if 0
+    { "user", o_string, user,
+      "Set name for auth with peer", OPT_PRIO | OPT_STATIC,
+      &explicit_user, MAXNAMELEN },
+
+    { "password", o_string, passwd,
+      "Password for authenticating us to the peer",
+      OPT_PRIO | OPT_STATIC | OPT_HIDE,
+      &explicit_passwd, MAXSECRETLEN },
+#endif
+
+    { "usehostname", o_bool, &usehostname,
+      "Must use hostname for authentication", 1 },
+
+    { "remotename", o_string, remote_name,
+      "Set remote name for authentication", OPT_PRIO | OPT_STATIC,
+      &explicit_remote, MAXNAMELEN },
+
+    { "login", o_bool, &uselogin,
+      "Use system password database for PAP", OPT_A2COPY | 1 ,
+      &session_mgmt },
+    { "enable-session", o_bool, &session_mgmt,
+      "Enable session accounting for remote peers", OPT_PRIV | 1 },
+
+    { "papcrypt", o_bool, &cryptpap,
+      "PAP passwords are encrypted", 1 },
+
+    { "privgroup", o_special, (void *)privgroup,
+      "Allow group members to use privileged options", OPT_PRIV | OPT_A2LIST },
+
+    { "allow-ip", o_special, (void *)set_noauth_addr,
+      "Set IP address(es) which can be used without authentication",
+      OPT_PRIV | OPT_A2LIST },
+
+    { "remotenumber", o_string, remote_number,
+      "Set remote telephone number for authentication", OPT_PRIO | OPT_STATIC,
+      NULL, MAXNAMELEN },
+
+    { "allow-number", o_special, (void *)set_permitted_number,
+      "Set telephone number(s) which are allowed to connect",
+      OPT_PRIV | OPT_A2LIST },
+
+    { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+#if 0 /* UNUSED */
+/*
+ * setupapfile - specifies UPAP info for authenticating with peer.
+ */
+static int
+setupapfile(argv)
+    char **argv;
+{
+    FILE *ufile;
+    int l;
+    uid_t euid;
+    char u[MAXNAMELEN], p[MAXSECRETLEN];
+    char *fname;
+
+    lcp_allowoptions[0].neg_upap = 1;
+
+    /* open user info file */
+    fname = strdup(*argv);
+    if (fname == NULL)
+	novm("+ua file name");
+    euid = geteuid();
+    if (seteuid(getuid()) == -1) {
+	option_error("unable to reset uid before opening %s: %m", fname);
+	return 0;
+    }
+    ufile = fopen(fname, "r");
+    if (seteuid(euid) == -1)
+	fatal("unable to regain privileges: %m");
+    if (ufile == NULL) {
+	option_error("unable to open user login data file %s", fname);
+	return 0;
+    }
+    check_access(ufile, fname);
+    uafname = fname;
+
+    /* get username */
+    if (fgets(u, MAXNAMELEN - 1, ufile) == NULL
+	|| fgets(p, MAXSECRETLEN - 1, ufile) == NULL) {
+	fclose(ufile);
+	option_error("unable to read user login data file %s", fname);
+	return 0;
+    }
+    fclose(ufile);
+
+    /* get rid of newlines */
+    l = strlen(u);
+    if (l > 0 && u[l-1] == '\n')
+	u[l-1] = 0;
+    l = strlen(p);
+    if (l > 0 && p[l-1] == '\n')
+	p[l-1] = 0;
+
+    if (override_value("user", option_priority, fname)) {
+	strlcpy(ppp_settings.user, u, sizeof(ppp_settings.user));
+	explicit_user = 1;
+    }
+    if (override_value("passwd", option_priority, fname)) {
+	strlcpy(ppp_settings.passwd, p, sizeof(ppp_settings.passwd));
+	explicit_passwd = 1;
+    }
+
+    return (1);
+}
+
+/*
+ * privgroup - allow members of the group to have privileged access.
+ */
+static int
+privgroup(argv)
+    char **argv;
+{
+    struct group *g;
+    int i;
+
+    g = getgrnam(*argv);
+    if (g == 0) {
+	option_error("group %s is unknown", *argv);
+	return 0;
+    }
+    for (i = 0; i < ngroups; ++i) {
+	if (groups[i] == g->gr_gid) {
+	    privileged = 1;
+	    break;
+	}
+    }
+    return 1;
+}
+
+
+/*
+ * set_noauth_addr - set address(es) that can be used without authentication.
+ * Equivalent to specifying an entry like `"" * "" addr' in pap-secrets.
+ */
+static int
+set_noauth_addr(argv)
+    char **argv;
+{
+    char *addr = *argv;
+    int l = strlen(addr) + 1;
+    struct wordlist *wp;
+
+    wp = (struct wordlist *) malloc(sizeof(struct wordlist) + l);
+    if (wp == NULL)
+	novm("allow-ip argument");
+    wp->word = (char *) (wp + 1);
+    wp->next = noauth_addrs;
+    MEMCPY(wp->word, addr, l);
+    noauth_addrs = wp;
+    return 1;
+}
+
+
+/*
+ * set_permitted_number - set remote telephone number(s) that may connect.
+ */
+static int
+set_permitted_number(argv)
+    char **argv;
+{
+    char *number = *argv;
+    int l = strlen(number) + 1;
+    struct wordlist *wp;
+
+    wp = (struct wordlist *) malloc(sizeof(struct wordlist) + l);
+    if (wp == NULL)
+	novm("allow-number argument");
+    wp->word = (char *) (wp + 1);
+    wp->next = permitted_numbers;
+    MEMCPY(wp->word, number, l);
+    permitted_numbers = wp;
+    return 1;
+}
+#endif
+
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ */
+void link_required(ppp_pcb *pcb) {
+    LWIP_UNUSED_ARG(pcb);
+}
+
+#if 0
+/*
+ * Bring the link up to the point of being able to do ppp.
+ */
+void start_link(unit)
+    int unit;
+{
+    ppp_pcb *pcb = &ppp_pcb_list[unit];
+    char *msg;
+
+    status = EXIT_NEGOTIATION_FAILED;
+    new_phase(pcb, PPP_PHASE_SERIALCONN);
+
+    hungup = 0;
+    devfd = the_channel->connect();
+    msg = "Connect script failed";
+    if (devfd < 0)
+	goto fail;
+
+    /* set up the serial device as a ppp interface */
+    /*
+     * N.B. we used to do tdb_writelock/tdb_writeunlock around this
+     * (from establish_ppp to set_ifunit).  However, we won't be
+     * doing the set_ifunit in multilink mode, which is the only time
+     * we need the atomicity that the tdb_writelock/tdb_writeunlock
+     * gives us.  Thus we don't need the tdb_writelock/tdb_writeunlock.
+     */
+    fd_ppp = the_channel->establish_ppp(devfd);
+    msg = "ppp establishment failed";
+    if (fd_ppp < 0) {
+	status = EXIT_FATAL_ERROR;
+	goto disconnect;
+    }
+
+    if (!demand && ifunit >= 0)
+	set_ifunit(1);
+
+    /*
+     * Start opening the connection and wait for
+     * incoming events (reply, timeout, etc.).
+     */
+    if (ifunit >= 0)
+	ppp_notice("Connect: %s <--> %s", ifname, ppp_devnam);
+    else
+	ppp_notice("Starting negotiation on %s", ppp_devnam);
+    add_fd(fd_ppp);
+
+    new_phase(pcb, PPP_PHASE_ESTABLISH);
+
+    lcp_lowerup(pcb);
+    return;
+
+ disconnect:
+    new_phase(pcb, PPP_PHASE_DISCONNECT);
+    if (the_channel->disconnect)
+	the_channel->disconnect();
+
+ fail:
+    new_phase(pcb, PPP_PHASE_DEAD);
+    if (the_channel->cleanup)
+	(*the_channel->cleanup)();
+}
+#endif
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void link_terminated(ppp_pcb *pcb) {
+    if (pcb->phase == PPP_PHASE_DEAD
+#ifdef HAVE_MULTILINK
+    || pcb->phase == PPP_PHASE_MASTER
+#endif /* HAVE_MULTILINK */
+    )
+	return;
+    new_phase(pcb, PPP_PHASE_DISCONNECT);
+
+#if 0 /* UNUSED */
+    if (pap_logout_hook) {
+	pap_logout_hook();
+    }
+    session_end(devnam);
+#endif /* UNUSED */
+
+    if (!doing_multilink) {
+	ppp_notice("Connection terminated.");
+#if PPP_STATS_SUPPORT
+	print_link_stats();
+#endif /* PPP_STATS_SUPPORT */
+    } else
+	ppp_notice("Link terminated.");
+
+    lcp_lowerdown(pcb);
+
+    ppp_link_terminated(pcb);
+#if 0
+    /*
+     * Delete pid files before disestablishing ppp.  Otherwise it
+     * can happen that another pppd gets the same unit and then
+     * we delete its pid file.
+     */
+    if (!doing_multilink && !demand)
+	remove_pidfiles();
+
+    /*
+     * If we may want to bring the link up again, transfer
+     * the ppp unit back to the loopback.  Set the
+     * real serial device back to its normal mode of operation.
+     */
+    if (fd_ppp >= 0) {
+	remove_fd(fd_ppp);
+	clean_check();
+	the_channel->disestablish_ppp(devfd);
+	if (doing_multilink)
+	    mp_exit_bundle();
+	fd_ppp = -1;
+    }
+    if (!hungup)
+	lcp_lowerdown(pcb);
+    if (!doing_multilink && !demand)
+	script_unsetenv("IFNAME");
+
+    /*
+     * Run disconnector script, if requested.
+     * XXX we may not be able to do this if the line has hung up!
+     */
+    if (devfd >= 0 && the_channel->disconnect) {
+	the_channel->disconnect();
+	devfd = -1;
+    }
+    if (the_channel->cleanup)
+	(*the_channel->cleanup)();
+
+    if (doing_multilink && multilink_master) {
+	if (!bundle_terminating)
+	    new_phase(pcb, PPP_PHASE_MASTER);
+	else
+	    mp_bundle_terminated();
+    } else
+	new_phase(pcb, PPP_PHASE_DEAD);
+#endif
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void link_down(ppp_pcb *pcb) {
+#if PPP_NOTIFY
+    notify(link_down_notifier, 0);
+#endif /* PPP_NOTIFY */
+
+    if (!doing_multilink) {
+	upper_layers_down(pcb);
+	if (pcb->phase != PPP_PHASE_DEAD
+#ifdef HAVE_MULTILINK
+	&& pcb->phase != PPP_PHASE_MASTER
+#endif /* HAVE_MULTILINK */
+	)
+	    new_phase(pcb, PPP_PHASE_ESTABLISH);
+    }
+    /* XXX if doing_multilink, should do something to stop
+       network-layer traffic on the link */
+}
+
+void upper_layers_down(ppp_pcb *pcb) {
+    int i;
+    const struct protent *protp;
+
+    for (i = 0; (protp = protocols[i]) != NULL; ++i) {
+        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
+	    (*protp->lowerdown)(pcb);
+        if (protp->protocol < 0xC000 && protp->close != NULL)
+	    (*protp->close)(pcb, "LCP down");
+    }
+    pcb->num_np_open = 0;
+    pcb->num_np_up = 0;
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void link_established(ppp_pcb *pcb) {
+#if PPP_AUTH_SUPPORT
+    int auth;
+#if PPP_SERVER
+#if PAP_SUPPORT
+    lcp_options *wo = &pcb->lcp_wantoptions;
+#endif /* PAP_SUPPORT */
+    lcp_options *go = &pcb->lcp_gotoptions;
+#endif /* PPP_SERVER */
+    lcp_options *ho = &pcb->lcp_hisoptions;
+#endif /* PPP_AUTH_SUPPORT */
+    int i;
+    const struct protent *protp;
+
+    /*
+     * Tell higher-level protocols that LCP is up.
+     */
+    if (!doing_multilink) {
+	for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	    if (protp->protocol != PPP_LCP
+		&& protp->lowerup != NULL)
+		(*protp->lowerup)(pcb);
+    }
+
+#if PPP_AUTH_SUPPORT
+#if PPP_SERVER
+#if PPP_ALLOWED_ADDRS
+    if (!auth_required && noauth_addrs != NULL)
+	set_allowed_addrs(unit, NULL, NULL);
+#endif /* PPP_ALLOWED_ADDRS */
+
+    if (pcb->settings.auth_required && !(0
+#if PAP_SUPPORT
+	|| go->neg_upap
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+	|| go->neg_chap
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+	|| go->neg_eap
+#endif /* EAP_SUPPORT */
+	)) {
+
+#if PPP_ALLOWED_ADDRS
+	/*
+	 * We wanted the peer to authenticate itself, and it refused:
+	 * if we have some address(es) it can use without auth, fine,
+	 * otherwise treat it as though it authenticated with PAP using
+	 * a username of "" and a password of "".  If that's not OK,
+	 * boot it out.
+	 */
+	if (noauth_addrs != NULL) {
+	    set_allowed_addrs(unit, NULL, NULL);
+	} else
+#endif /* PPP_ALLOWED_ADDRS */
+	if (!pcb->settings.null_login
+#if PAP_SUPPORT
+	    || !wo->neg_upap
+#endif /* PAP_SUPPORT */
+	    ) {
+	    ppp_warn("peer refused to authenticate: terminating link");
+#if 0 /* UNUSED */
+	    status = EXIT_PEER_AUTH_FAILED;
+#endif /* UNUSED */
+	    pcb->err_code = PPPERR_AUTHFAIL;
+	    lcp_close(pcb, "peer refused to authenticate");
+	    return;
+	}
+    }
+#endif /* PPP_SERVER */
+
+    new_phase(pcb, PPP_PHASE_AUTHENTICATE);
+    auth = 0;
+#if PPP_SERVER
+#if EAP_SUPPORT
+    if (go->neg_eap) {
+	eap_authpeer(pcb, PPP_OUR_NAME);
+	auth |= EAP_PEER;
+    } else
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT
+    if (go->neg_chap) {
+	chap_auth_peer(pcb, PPP_OUR_NAME, CHAP_DIGEST(go->chap_mdtype));
+	auth |= CHAP_PEER;
+    } else
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+    if (go->neg_upap) {
+	upap_authpeer(pcb);
+	auth |= PAP_PEER;
+    } else
+#endif /* PAP_SUPPORT */
+    {}
+#endif /* PPP_SERVER */
+
+#if EAP_SUPPORT
+    if (ho->neg_eap) {
+	eap_authwithpeer(pcb, pcb->settings.user);
+	auth |= EAP_WITHPEER;
+    } else
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT
+    if (ho->neg_chap) {
+	chap_auth_with_peer(pcb, pcb->settings.user, CHAP_DIGEST(ho->chap_mdtype));
+	auth |= CHAP_WITHPEER;
+    } else
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+    if (ho->neg_upap) {
+	upap_authwithpeer(pcb, pcb->settings.user, pcb->settings.passwd);
+	auth |= PAP_WITHPEER;
+    } else
+#endif /* PAP_SUPPORT */
+    {}
+
+    pcb->auth_pending = auth;
+    pcb->auth_done = 0;
+
+    if (!auth)
+#endif /* PPP_AUTH_SUPPORT */
+	network_phase(pcb);
+}
+
+/*
+ * Proceed to the network phase.
+ */
+static void network_phase(ppp_pcb *pcb) {
+#if CBCP_SUPPORT
+    ppp_pcb *pcb = &ppp_pcb_list[unit];
+#endif
+#if 0 /* UNUSED */
+    lcp_options *go = &lcp_gotoptions[unit];
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+    /* Log calling number. */
+    if (*remote_number)
+	ppp_notice("peer from calling number %q authorized", remote_number);
+#endif /* UNUSED */
+
+#if PPP_NOTIFY
+    /*
+     * If the peer had to authenticate, notify it now.
+     */
+    if (0
+#if CHAP_SUPPORT
+	|| go->neg_chap
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	|| go->neg_upap
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+	|| go->neg_eap
+#endif /* EAP_SUPPORT */
+	) {
+	notify(auth_up_notifier, 0);
+    }
+#endif /* PPP_NOTIFY */
+
+#if CBCP_SUPPORT
+    /*
+     * If we negotiated callback, do it now.
+     */
+    if (go->neg_cbcp) {
+	new_phase(pcb, PPP_PHASE_CALLBACK);
+	(*cbcp_protent.open)(pcb);
+	return;
+    }
+#endif
+
+#if PPP_OPTIONS
+    /*
+     * Process extra options from the secrets file
+     */
+    if (extra_options) {
+	options_from_list(extra_options, 1);
+	free_wordlist(extra_options);
+	extra_options = 0;
+    }
+#endif /* PPP_OPTIONS */
+    start_networks(pcb);
+}
+
+void start_networks(ppp_pcb *pcb) {
+#if CCP_SUPPORT || ECP_SUPPORT
+    int i;
+    const struct protent *protp;
+#endif /* CCP_SUPPORT || ECP_SUPPORT */
+
+    new_phase(pcb, PPP_PHASE_NETWORK);
+
+#ifdef HAVE_MULTILINK
+    if (multilink) {
+	if (mp_join_bundle()) {
+	    if (multilink_join_hook)
+		(*multilink_join_hook)();
+	    if (updetach && !nodetach)
+		detach();
+	    return;
+	}
+    }
+#endif /* HAVE_MULTILINK */
+
+#ifdef PPP_FILTER
+    if (!demand)
+	set_filters(&pass_filter, &active_filter);
+#endif
+#if CCP_SUPPORT || ECP_SUPPORT
+    /* Start CCP and ECP */
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (
+	    (0
+#if ECP_SUPPORT
+	    || protp->protocol == PPP_ECP
+#endif /* ECP_SUPPORT */
+#if CCP_SUPPORT
+	    || protp->protocol == PPP_CCP
+#endif /* CCP_SUPPORT */
+	    )
+	    && protp->open != NULL)
+	    (*protp->open)(pcb);
+#endif /* CCP_SUPPORT || ECP_SUPPORT */
+
+    /*
+     * Bring up other network protocols iff encryption is not required.
+     */
+    if (1
+#if ECP_SUPPORT
+        && !ecp_gotoptions[unit].required
+#endif /* ECP_SUPPORT */
+#if MPPE_SUPPORT
+        && !pcb->ccp_gotoptions.mppe
+#endif /* MPPE_SUPPORT */
+        )
+	continue_networks(pcb);
+}
+
+void continue_networks(ppp_pcb *pcb) {
+    int i;
+    const struct protent *protp;
+
+    /*
+     * Start the "real" network protocols.
+     */
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (protp->protocol < 0xC000
+#if CCP_SUPPORT
+	    && protp->protocol != PPP_CCP
+#endif /* CCP_SUPPORT */
+#if ECP_SUPPORT
+	    && protp->protocol != PPP_ECP
+#endif /* ECP_SUPPORT */
+	    && protp->open != NULL) {
+	    (*protp->open)(pcb);
+	    ++pcb->num_np_open;
+	}
+
+    if (pcb->num_np_open == 0)
+	/* nothing to do */
+	lcp_close(pcb, "No network protocols running");
+}
+
+#if PPP_AUTH_SUPPORT
+#if PPP_SERVER
+/*
+ * auth_check_passwd - Check the user name and passwd against configuration.
+ *
+ * returns:
+ *      0: Authentication failed.
+ *      1: Authentication succeeded.
+ * In either case, msg points to an appropriate message and msglen to the message len.
+ */
+int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen) {
+  int secretuserlen;
+  int secretpasswdlen;
+
+  if (pcb->settings.user && pcb->settings.passwd) {
+    secretuserlen = (int)strlen(pcb->settings.user);
+    secretpasswdlen = (int)strlen(pcb->settings.passwd);
+    if (secretuserlen == userlen
+        && secretpasswdlen == passwdlen
+        && !memcmp(auser, pcb->settings.user, userlen)
+        && !memcmp(apasswd, pcb->settings.passwd, passwdlen) ) {
+      *msg = "Login ok";
+      *msglen = sizeof("Login ok")-1;
+      return 1;
+    }
+  }
+
+  *msg = "Login incorrect";
+  *msglen = sizeof("Login incorrect")-1;
+  return 0;
+}
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void auth_peer_fail(ppp_pcb *pcb, int protocol) {
+    LWIP_UNUSED_ARG(protocol);
+    /*
+     * Authentication failure: take the link down
+     */
+#if 0 /* UNUSED */
+    status = EXIT_PEER_AUTH_FAILED;
+#endif /* UNUSED */
+    pcb->err_code = PPPERR_AUTHFAIL;
+    lcp_close(pcb, "Authentication failed");
+}
+
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen) {
+    int bit;
+#ifndef HAVE_MULTILINK
+    LWIP_UNUSED_ARG(name);
+    LWIP_UNUSED_ARG(namelen);
+#endif /* HAVE_MULTILINK */
+
+    switch (protocol) {
+#if CHAP_SUPPORT
+    case PPP_CHAP:
+	bit = CHAP_PEER;
+	switch (prot_flavor) {
+	case CHAP_MD5:
+	    bit |= CHAP_MD5_PEER;
+	    break;
+#if MSCHAP_SUPPORT
+	case CHAP_MICROSOFT:
+	    bit |= CHAP_MS_PEER;
+	    break;
+	case CHAP_MICROSOFT_V2:
+	    bit |= CHAP_MS2_PEER;
+	    break;
+#endif /* MSCHAP_SUPPORT */
+	default:
+	    break;
+	}
+	break;
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+    case PPP_PAP:
+	bit = PAP_PEER;
+	break;
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+    case PPP_EAP:
+	bit = EAP_PEER;
+	break;
+#endif /* EAP_SUPPORT */
+    default:
+	ppp_warn("auth_peer_success: unknown protocol %x", protocol);
+	return;
+    }
+
+#ifdef HAVE_MULTILINK
+    /*
+     * Save the authenticated name of the peer for later.
+     */
+    if (namelen > (int)sizeof(pcb->peer_authname) - 1)
+	namelen = (int)sizeof(pcb->peer_authname) - 1;
+    MEMCPY(pcb->peer_authname, name, namelen);
+    pcb->peer_authname[namelen] = 0;
+#endif /* HAVE_MULTILINK */
+#if 0 /* UNUSED */
+    script_setenv("PEERNAME", , 0);
+#endif /* UNUSED */
+
+    /* Save the authentication method for later. */
+    pcb->auth_done |= bit;
+
+    /*
+     * If there is no more authentication still to be done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((pcb->auth_pending &= ~bit) == 0)
+        network_phase(pcb);
+}
+#endif /* PPP_SERVER */
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void auth_withpeer_fail(ppp_pcb *pcb, int protocol) {
+    LWIP_UNUSED_ARG(protocol);
+    /*
+     * We've failed to authenticate ourselves to our peer.
+     *
+     * Some servers keep sending CHAP challenges, but there
+     * is no point in persisting without any way to get updated
+     * authentication secrets.
+     *
+     * He'll probably take the link down, and there's not much
+     * we can do except wait for that.
+     */
+    pcb->err_code = PPPERR_AUTHFAIL;
+    lcp_close(pcb, "Failed to authenticate ourselves to peer");
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor) {
+    int bit;
+    const char *prot = "";
+
+    switch (protocol) {
+#if CHAP_SUPPORT
+    case PPP_CHAP:
+	bit = CHAP_WITHPEER;
+	prot = "CHAP";
+	switch (prot_flavor) {
+	case CHAP_MD5:
+	    bit |= CHAP_MD5_WITHPEER;
+	    break;
+#if MSCHAP_SUPPORT
+	case CHAP_MICROSOFT:
+	    bit |= CHAP_MS_WITHPEER;
+	    break;
+	case CHAP_MICROSOFT_V2:
+	    bit |= CHAP_MS2_WITHPEER;
+	    break;
+#endif /* MSCHAP_SUPPORT */
+	default:
+	    break;
+	}
+	break;
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+    case PPP_PAP:
+	bit = PAP_WITHPEER;
+	prot = "PAP";
+	break;
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+    case PPP_EAP:
+	bit = EAP_WITHPEER;
+	prot = "EAP";
+	break;
+#endif /* EAP_SUPPORT */
+    default:
+	ppp_warn("auth_withpeer_success: unknown protocol %x", protocol);
+	bit = 0;
+	/* no break */
+    }
+
+    ppp_notice("%s authentication succeeded", prot);
+
+    /* Save the authentication method for later. */
+    pcb->auth_done |= bit;
+
+    /*
+     * If there is no more authentication still being done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((pcb->auth_pending &= ~bit) == 0)
+	network_phase(pcb);
+}
+#endif /* PPP_AUTH_SUPPORT */
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void np_up(ppp_pcb *pcb, int proto) {
+#if PPP_IDLETIMELIMIT
+    int tlim;
+#endif /* PPP_IDLETIMELIMIT */
+    LWIP_UNUSED_ARG(proto);
+
+    if (pcb->num_np_up == 0) {
+	/*
+	 * At this point we consider that the link has come up successfully.
+	 */
+	new_phase(pcb, PPP_PHASE_RUNNING);
+
+#if PPP_IDLETIMELIMIT
+#if 0 /* UNUSED */
+	if (idle_time_hook != 0)
+	    tlim = (*idle_time_hook)(NULL);
+	else
+#endif /* UNUSED */
+	    tlim = pcb->settings.idle_time_limit;
+	if (tlim > 0)
+	    TIMEOUT(check_idle, (void*)pcb, tlim);
+#endif /* PPP_IDLETIMELIMIT */
+
+#if PPP_MAXCONNECT
+	/*
+	 * Set a timeout to close the connection once the maximum
+	 * connect time has expired.
+	 */
+	if (pcb->settings.maxconnect > 0)
+	    TIMEOUT(connect_time_expired, (void*)pcb, pcb->settings.maxconnect);
+#endif /* PPP_MAXCONNECT */
+
+#ifdef MAXOCTETS
+	if (maxoctets > 0)
+	    TIMEOUT(check_maxoctets, NULL, maxoctets_timeout);
+#endif
+
+#if 0 /* Unused */
+	/*
+	 * Detach now, if the updetach option was given.
+	 */
+	if (updetach && !nodetach)
+	    detach();
+#endif /* Unused */
+    }
+    ++pcb->num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void np_down(ppp_pcb *pcb, int proto) {
+    LWIP_UNUSED_ARG(proto);
+    if (--pcb->num_np_up == 0) {
+#if PPP_IDLETIMELIMIT
+	UNTIMEOUT(check_idle, (void*)pcb);
+#endif /* PPP_IDLETIMELIMIT */
+#if PPP_MAXCONNECT
+	UNTIMEOUT(connect_time_expired, NULL);
+#endif /* PPP_MAXCONNECT */
+#ifdef MAXOCTETS
+	UNTIMEOUT(check_maxoctets, NULL);
+#endif
+	new_phase(pcb, PPP_PHASE_NETWORK);
+    }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void np_finished(ppp_pcb *pcb, int proto) {
+    LWIP_UNUSED_ARG(proto);
+    if (--pcb->num_np_open <= 0) {
+	/* no further use for the link: shut up shop. */
+	lcp_close(pcb, "No network protocols running");
+    }
+}
+
+#ifdef MAXOCTETS
+static void
+check_maxoctets(arg)
+    void *arg;
+{
+#if PPP_STATS_SUPPORT
+    unsigned int used;
+
+    update_link_stats(ifunit);
+    link_stats_valid=0;
+
+    switch(maxoctets_dir) {
+	case PPP_OCTETS_DIRECTION_IN:
+	    used = link_stats.bytes_in;
+	    break;
+	case PPP_OCTETS_DIRECTION_OUT:
+	    used = link_stats.bytes_out;
+	    break;
+	case PPP_OCTETS_DIRECTION_MAXOVERAL:
+	case PPP_OCTETS_DIRECTION_MAXSESSION:
+	    used = (link_stats.bytes_in > link_stats.bytes_out) ? link_stats.bytes_in : link_stats.bytes_out;
+	    break;
+	default:
+	    used = link_stats.bytes_in+link_stats.bytes_out;
+	    break;
+    }
+    if (used > maxoctets) {
+	ppp_notice("Traffic limit reached. Limit: %u Used: %u", maxoctets, used);
+	status = EXIT_TRAFFIC_LIMIT;
+	lcp_close(pcb, "Traffic limit");
+#if 0 /* UNUSED */
+	need_holdoff = 0;
+#endif /* UNUSED */
+    } else {
+        TIMEOUT(check_maxoctets, NULL, maxoctets_timeout);
+    }
+#endif /* PPP_STATS_SUPPORT */
+}
+#endif /* MAXOCTETS */
+
+#if PPP_IDLETIMELIMIT
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void check_idle(void *arg) {
+    ppp_pcb *pcb = (ppp_pcb*)arg;
+    struct ppp_idle idle;
+    time_t itime;
+    int tlim;
+
+    if (!get_idle_time(pcb, &idle))
+	return;
+#if 0 /* UNUSED */
+    if (idle_time_hook != 0) {
+	tlim = idle_time_hook(&idle);
+    } else {
+#endif /* UNUSED */
+	itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+	tlim = pcb->settings.idle_time_limit - itime;
+#if 0 /* UNUSED */
+    }
+#endif /* UNUSED */
+    if (tlim <= 0) {
+	/* link is idle: shut it down. */
+	ppp_notice("Terminating connection due to lack of activity.");
+	pcb->err_code = PPPERR_IDLETIMEOUT;
+	lcp_close(pcb, "Link inactive");
+#if 0 /* UNUSED */
+	need_holdoff = 0;
+#endif /* UNUSED */
+    } else {
+	TIMEOUT(check_idle, (void*)pcb, tlim);
+    }
+}
+#endif /* PPP_IDLETIMELIMIT */
+
+#if PPP_MAXCONNECT
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void connect_time_expired(void *arg) {
+    ppp_pcb *pcb = (ppp_pcb*)arg;
+    ppp_info("Connect time expired");
+    pcb->err_code = PPPERR_CONNECTTIME;
+    lcp_close(pcb, "Connect time expired");	/* Close connection */
+}
+#endif /* PPP_MAXCONNECT */
+
+#if PPP_OPTIONS
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void
+auth_check_options()
+{
+    lcp_options *wo = &lcp_wantoptions[0];
+    int can_auth;
+    int lacks_ip;
+
+    /* Default our_name to hostname, and user to our_name */
+    if (our_name[0] == 0 || usehostname)
+	strlcpy(our_name, hostname, sizeof(our_name));
+    /* If a blank username was explicitly given as an option, trust
+       the user and don't use our_name */
+    if (ppp_settings.user[0] == 0 && !explicit_user)
+	strlcpy(ppp_settings.user, our_name, sizeof(ppp_settings.user));
+
+    /*
+     * If we have a default route, require the peer to authenticate
+     * unless the noauth option was given or the real user is root.
+     */
+    if (!auth_required && !allow_any_ip && have_route_to(0) && !privileged) {
+	auth_required = 1;
+	default_auth = 1;
+    }
+
+#if CHAP_SUPPORT
+    /* If we selected any CHAP flavors, we should probably negotiate it. :-) */
+    if (wo->chap_mdtype)
+	wo->neg_chap = 1;
+#endif /* CHAP_SUPPORT */
+
+    /* If authentication is required, ask peer for CHAP, PAP, or EAP. */
+    if (auth_required) {
+	allow_any_ip = 0;
+	if (1
+#if CHAP_SUPPORT
+	    && !wo->neg_chap
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	    && !wo->neg_upap
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+	    && !wo->neg_eap
+#endif /* EAP_SUPPORT */
+	    ) {
+#if CHAP_SUPPORT
+	    wo->neg_chap = CHAP_MDTYPE_SUPPORTED != MDTYPE_NONE;
+	    wo->chap_mdtype = CHAP_MDTYPE_SUPPORTED;
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	    wo->neg_upap = 1;
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+	    wo->neg_eap = 1;
+#endif /* EAP_SUPPORT */
+	}
+    } else {
+#if CHAP_SUPPORT
+	wo->neg_chap = 0;
+	wo->chap_mdtype = MDTYPE_NONE;
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	wo->neg_upap = 0;
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+	wo->neg_eap = 0;
+#endif /* EAP_SUPPORT */
+    }
+
+    /*
+     * Check whether we have appropriate secrets to use
+     * to authenticate the peer.  Note that EAP can authenticate by way
+     * of a CHAP-like exchanges as well as SRP.
+     */
+    lacks_ip = 0;
+#if PAP_SUPPORT
+    can_auth = wo->neg_upap && (uselogin || have_pap_secret(&lacks_ip));
+#else
+    can_auth = 0;
+#endif /* PAP_SUPPORT */
+    if (!can_auth && (0
+#if CHAP_SUPPORT
+	|| wo->neg_chap
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+	|| wo->neg_eap
+#endif /* EAP_SUPPORT */
+	)) {
+#if CHAP_SUPPORT
+	can_auth = have_chap_secret((explicit_remote? remote_name: NULL),
+				    our_name, 1, &lacks_ip);
+#else
+	can_auth = 0;
+#endif
+    }
+    if (!can_auth
+#if EAP_SUPPORT
+	&& wo->neg_eap
+#endif /* EAP_SUPPORT */
+	) {
+	can_auth = have_srp_secret((explicit_remote? remote_name: NULL),
+				    our_name, 1, &lacks_ip);
+    }
+
+    if (auth_required && !can_auth && noauth_addrs == NULL) {
+	if (default_auth) {
+	    option_error(
+"By default the remote system is required to authenticate itself");
+	    option_error(
+"(because this system has a default route to the internet)");
+	} else if (explicit_remote)
+	    option_error(
+"The remote system (%s) is required to authenticate itself",
+			 remote_name);
+	else
+	    option_error(
+"The remote system is required to authenticate itself");
+	option_error(
+"but I couldn't find any suitable secret (password) for it to use to do so.");
+	if (lacks_ip)
+	    option_error(
+"(None of the available passwords would let it use an IP address.)");
+
+	exit(1);
+    }
+
+    /*
+     * Early check for remote number authorization.
+     */
+    if (!auth_number()) {
+	ppp_warn("calling number %q is not authorized", remote_number);
+	exit(EXIT_CNID_AUTH_FAILED);
+    }
+}
+#endif /* PPP_OPTIONS */
+
+#if 0 /* UNUSED */
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void
+auth_reset(unit)
+    int unit;
+{
+    lcp_options *go = &lcp_gotoptions[unit];
+    lcp_options *ao = &lcp_allowoptions[unit];
+    int hadchap;
+
+    hadchap = -1;
+    ao->neg_upap = !refuse_pap && (passwd[0] != 0 || get_pap_passwd(NULL));
+    ao->neg_chap = (!refuse_chap || !refuse_mschap || !refuse_mschap_v2)
+	&& (passwd[0] != 0 ||
+	    (hadchap = have_chap_secret(user, (explicit_remote? remote_name:
+					       NULL), 0, NULL)));
+    ao->neg_eap = !refuse_eap && (
+	passwd[0] != 0 ||
+	(hadchap == 1 || (hadchap == -1 && have_chap_secret(user,
+	    (explicit_remote? remote_name: NULL), 0, NULL))) ||
+	have_srp_secret(user, (explicit_remote? remote_name: NULL), 0, NULL));
+
+    hadchap = -1;
+    if (go->neg_upap && !uselogin && !have_pap_secret(NULL))
+	go->neg_upap = 0;
+    if (go->neg_chap) {
+	if (!(hadchap = have_chap_secret((explicit_remote? remote_name: NULL),
+			      our_name, 1, NULL)))
+	    go->neg_chap = 0;
+    }
+    if (go->neg_eap &&
+	(hadchap == 0 || (hadchap == -1 &&
+	    !have_chap_secret((explicit_remote? remote_name: NULL), our_name,
+		1, NULL))) &&
+	!have_srp_secret((explicit_remote? remote_name: NULL), our_name, 1,
+	    NULL))
+	go->neg_eap = 0;
+}
+
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *	UPAP_AUTHNAK: Authentication failed.
+ *	UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int
+check_passwd(unit, auser, userlen, apasswd, passwdlen, msg)
+    int unit;
+    char *auser;
+    int userlen;
+    char *apasswd;
+    int passwdlen;
+    char **msg;
+{
+  return UPAP_AUTHNAK;
+    int ret;
+    char *filename;
+    FILE *f;
+    struct wordlist *addrs = NULL, *opts = NULL;
+    char passwd[256], user[256];
+    char secret[MAXWORDLEN];
+    static int attempts = 0;
+
+    /*
+     * Make copies of apasswd and auser, then null-terminate them.
+     * If there are unprintable characters in the password, make
+     * them visible.
+     */
+    slprintf(ppp_settings.passwd, sizeof(ppp_settings.passwd), "%.*v", passwdlen, apasswd);
+    slprintf(ppp_settings.user, sizeof(ppp_settings.user), "%.*v", userlen, auser);
+    *msg = "";
+
+    /*
+     * Check if a plugin wants to handle this.
+     */
+    if (pap_auth_hook) {
+	ret = (*pap_auth_hook)(ppp_settings.user, ppp_settings.passwd, msg, &addrs, &opts);
+	if (ret >= 0) {
+	    /* note: set_allowed_addrs() saves opts (but not addrs):
+	       don't free it! */
+	    if (ret)
+		set_allowed_addrs(unit, addrs, opts);
+	    else if (opts != 0)
+		free_wordlist(opts);
+	    if (addrs != 0)
+		free_wordlist(addrs);
+	    BZERO(ppp_settings.passwd, sizeof(ppp_settings.passwd));
+	    return ret? UPAP_AUTHACK: UPAP_AUTHNAK;
+	}
+    }
+
+    /*
+     * Open the file of pap secrets and scan for a suitable secret
+     * for authenticating this user.
+     */
+    filename = _PATH_UPAPFILE;
+    addrs = opts = NULL;
+    ret = UPAP_AUTHNAK;
+    f = fopen(filename, "r");
+    if (f == NULL) {
+	ppp_error("Can't open PAP password file %s: %m", filename);
+
+    } else {
+	check_access(f, filename);
+	if (scan_authfile(f, ppp_settings.user, our_name, secret, &addrs, &opts, filename, 0) < 0) {
+	    ppp_warn("no PAP secret found for %s", user);
+	} else {
+	    /*
+	     * If the secret is "@login", it means to check
+	     * the password against the login database.
+	     */
+	    int login_secret = strcmp(secret, "@login") == 0;
+	    ret = UPAP_AUTHACK;
+	    if (uselogin || login_secret) {
+		/* login option or secret is @login */
+		if (session_full(ppp_settings.user, ppp_settings.passwd, devnam, msg) == 0) {
+		    ret = UPAP_AUTHNAK;
+		}
+	    } else if (session_mgmt) {
+		if (session_check(ppp_settings.user, NULL, devnam, NULL) == 0) {
+		    ppp_warn("Peer %q failed PAP Session verification", user);
+		    ret = UPAP_AUTHNAK;
+		}
+	    }
+	    if (secret[0] != 0 && !login_secret) {
+		/* password given in pap-secrets - must match */
+		if ((cryptpap || strcmp(ppp_settings.passwd, secret) != 0)
+		    && strcmp(crypt(ppp_settings.passwd, secret), secret) != 0)
+		    ret = UPAP_AUTHNAK;
+	    }
+	}
+	fclose(f);
+    }
+
+    if (ret == UPAP_AUTHNAK) {
+        if (**msg == 0)
+	    *msg = "Login incorrect";
+	/*
+	 * XXX can we ever get here more than once??
+	 * Frustrate passwd stealer programs.
+	 * Allow 10 tries, but start backing off after 3 (stolen from login).
+	 * On 10'th, drop the connection.
+	 */
+	if (attempts++ >= 10) {
+	    ppp_warn("%d LOGIN FAILURES ON %s, %s", attempts, devnam, user);
+	    lcp_close(pcb, "login failed");
+	}
+	if (attempts > 3)
+	    sleep((u_int) (attempts - 3) * 5);
+	if (opts != NULL)
+	    free_wordlist(opts);
+
+    } else {
+	attempts = 0;			/* Reset count */
+	if (**msg == 0)
+	    *msg = "Login ok";
+	set_allowed_addrs(unit, addrs, opts);
+    }
+
+    if (addrs != NULL)
+	free_wordlist(addrs);
+    BZERO(ppp_settings.passwd, sizeof(ppp_settings.passwd));
+    BZERO(secret, sizeof(secret));
+
+    return ret;
+}
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int
+null_login(unit)
+    int unit;
+{
+    char *filename;
+    FILE *f;
+    int i, ret;
+    struct wordlist *addrs, *opts;
+    char secret[MAXWORDLEN];
+
+    /*
+     * Check if a plugin wants to handle this.
+     */
+    ret = -1;
+    if (null_auth_hook)
+	ret = (*null_auth_hook)(&addrs, &opts);
+
+    /*
+     * Open the file of pap secrets and scan for a suitable secret.
+     */
+    if (ret <= 0) {
+	filename = _PATH_UPAPFILE;
+	addrs = NULL;
+	f = fopen(filename, "r");
+	if (f == NULL)
+	    return 0;
+	check_access(f, filename);
+
+	i = scan_authfile(f, "", our_name, secret, &addrs, &opts, filename, 0);
+	ret = i >= 0 && secret[0] == 0;
+	BZERO(secret, sizeof(secret));
+	fclose(f);
+    }
+
+    if (ret)
+	set_allowed_addrs(unit, addrs, opts);
+    else if (opts != 0)
+	free_wordlist(opts);
+    if (addrs != 0)
+	free_wordlist(addrs);
+
+    return ret;
+}
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ * Assumes passwd points to MAXSECRETLEN bytes of space (if non-null).
+ */
+static int
+get_pap_passwd(passwd)
+    char *passwd;
+{
+    char *filename;
+    FILE *f;
+    int ret;
+    char secret[MAXWORDLEN];
+
+    /*
+     * Check whether a plugin wants to supply this.
+     */
+    if (pap_passwd_hook) {
+	ret = (*pap_passwd_hook)(ppp_settings,user, ppp_settings.passwd);
+	if (ret >= 0)
+	    return ret;
+    }
+
+    filename = _PATH_UPAPFILE;
+    f = fopen(filename, "r");
+    if (f == NULL)
+	return 0;
+    check_access(f, filename);
+    ret = scan_authfile(f, user,
+			(remote_name[0]? remote_name: NULL),
+			secret, NULL, NULL, filename, 0);
+    fclose(f);
+    if (ret < 0)
+	return 0;
+    if (passwd != NULL)
+	strlcpy(passwd, secret, MAXSECRETLEN);
+    BZERO(secret, sizeof(secret));
+    return 1;
+}
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int
+have_pap_secret(lacks_ipp)
+    int *lacks_ipp;
+{
+    FILE *f;
+    int ret;
+    char *filename;
+    struct wordlist *addrs;
+
+    /* let the plugin decide, if there is one */
+    if (pap_check_hook) {
+	ret = (*pap_check_hook)();
+	if (ret >= 0)
+	    return ret;
+    }
+
+    filename = _PATH_UPAPFILE;
+    f = fopen(filename, "r");
+    if (f == NULL)
+	return 0;
+
+    ret = scan_authfile(f, (explicit_remote? remote_name: NULL), our_name,
+			NULL, &addrs, NULL, filename, 0);
+    fclose(f);
+    if (ret >= 0 && !some_ip_ok(addrs)) {
+	if (lacks_ipp != 0)
+	    *lacks_ipp = 1;
+	ret = -1;
+    }
+    if (addrs != 0)
+	free_wordlist(addrs);
+
+    return ret >= 0;
+}
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int
+have_chap_secret(client, server, need_ip, lacks_ipp)
+    char *client;
+    char *server;
+    int need_ip;
+    int *lacks_ipp;
+{
+    FILE *f;
+    int ret;
+    char *filename;
+    struct wordlist *addrs;
+
+    if (chap_check_hook) {
+	ret = (*chap_check_hook)();
+	if (ret >= 0) {
+	    return ret;
+	}
+    }
+
+    filename = _PATH_CHAPFILE;
+    f = fopen(filename, "r");
+    if (f == NULL)
+	return 0;
+
+    if (client != NULL && client[0] == 0)
+	client = NULL;
+    else if (server != NULL && server[0] == 0)
+	server = NULL;
+
+    ret = scan_authfile(f, client, server, NULL, &addrs, NULL, filename, 0);
+    fclose(f);
+    if (ret >= 0 && need_ip && !some_ip_ok(addrs)) {
+	if (lacks_ipp != 0)
+	    *lacks_ipp = 1;
+	ret = -1;
+    }
+    if (addrs != 0)
+	free_wordlist(addrs);
+
+    return ret >= 0;
+}
+
+/*
+ * have_srp_secret - check whether we have a SRP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int
+have_srp_secret(client, server, need_ip, lacks_ipp)
+    char *client;
+    char *server;
+    int need_ip;
+    int *lacks_ipp;
+{
+    FILE *f;
+    int ret;
+    char *filename;
+    struct wordlist *addrs;
+
+    filename = _PATH_SRPFILE;
+    f = fopen(filename, "r");
+    if (f == NULL)
+	return 0;
+
+    if (client != NULL && client[0] == 0)
+	client = NULL;
+    else if (server != NULL && server[0] == 0)
+	server = NULL;
+
+    ret = scan_authfile(f, client, server, NULL, &addrs, NULL, filename, 0);
+    fclose(f);
+    if (ret >= 0 && need_ip && !some_ip_ok(addrs)) {
+	if (lacks_ipp != 0)
+	    *lacks_ipp = 1;
+	ret = -1;
+    }
+    if (addrs != 0)
+	free_wordlist(addrs);
+
+    return ret >= 0;
+}
+#endif /* UNUSED */
+
+#if PPP_AUTH_SUPPORT
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server) {
+  int len;
+  LWIP_UNUSED_ARG(server);
+  LWIP_UNUSED_ARG(am_server);
+
+  if (!client || !client[0] || !pcb->settings.user || !pcb->settings.passwd || strcmp(client, pcb->settings.user)) {
+    return 0;
+  }
+
+  len = (int)strlen(pcb->settings.passwd);
+  if (len > MAXSECRETLEN) {
+    ppp_error("Secret for %s on %s is too long", client, server);
+    len = MAXSECRETLEN;
+  }
+
+  MEMCPY(secret, pcb->settings.passwd, len);
+  *secret_len = len;
+  return 1;
+
+#if 0 /* UNUSED */
+    FILE *f;
+    int ret, len;
+    char *filename;
+    struct wordlist *addrs, *opts;
+    char secbuf[MAXWORDLEN];
+    struct wordlist *addrs;
+    addrs = NULL;
+
+    if (!am_server && ppp_settings.passwd[0] != 0) {
+	strlcpy(secbuf, ppp_settings.passwd, sizeof(secbuf));
+    } else if (!am_server && chap_passwd_hook) {
+	if ( (*chap_passwd_hook)(client, secbuf) < 0) {
+	    ppp_error("Unable to obtain CHAP password for %s on %s from plugin",
+		  client, server);
+	    return 0;
+	}
+    } else {
+	filename = _PATH_CHAPFILE;
+	addrs = NULL;
+	secbuf[0] = 0;
+
+	f = fopen(filename, "r");
+	if (f == NULL) {
+	    ppp_error("Can't open chap secret file %s: %m", filename);
+	    return 0;
+	}
+	check_access(f, filename);
+
+	ret = scan_authfile(f, client, server, secbuf, &addrs, &opts, filename, 0);
+	fclose(f);
+	if (ret < 0)
+	    return 0;
+
+	if (am_server)
+	    set_allowed_addrs(unit, addrs, opts);
+	else if (opts != 0)
+	    free_wordlist(opts);
+	if (addrs != 0)
+	    free_wordlist(addrs);
+    }
+
+    len = strlen(secbuf);
+    if (len > MAXSECRETLEN) {
+	ppp_error("Secret for %s on %s is too long", client, server);
+	len = MAXSECRETLEN;
+    }
+    MEMCPY(secret, secbuf, len);
+    BZERO(secbuf, sizeof(secbuf));
+    *secret_len = len;
+
+    return 1;
+#endif /* UNUSED */
+}
+#endif /* PPP_AUTH_SUPPORT */
+
+
+#if 0 /* UNUSED */
+/*
+ * get_srp_secret - open the SRP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int
+get_srp_secret(unit, client, server, secret, am_server)
+    int unit;
+    char *client;
+    char *server;
+    char *secret;
+    int am_server;
+{
+    FILE *fp;
+    int ret;
+    char *filename;
+    struct wordlist *addrs, *opts;
+
+    if (!am_server && ppp_settings.passwd[0] != '\0') {
+	strlcpy(secret, ppp_settings.passwd, MAXWORDLEN);
+    } else {
+	filename = _PATH_SRPFILE;
+	addrs = NULL;
+
+	fp = fopen(filename, "r");
+	if (fp == NULL) {
+	    ppp_error("Can't open srp secret file %s: %m", filename);
+	    return 0;
+	}
+	check_access(fp, filename);
+
+	secret[0] = '\0';
+	ret = scan_authfile(fp, client, server, secret, &addrs, &opts,
+	    filename, am_server);
+	fclose(fp);
+	if (ret < 0)
+	    return 0;
+
+	if (am_server)
+	    set_allowed_addrs(unit, addrs, opts);
+	else if (opts != NULL)
+	    free_wordlist(opts);
+	if (addrs != NULL)
+	    free_wordlist(addrs);
+    }
+
+    return 1;
+}
+
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ * Also looks for `--' indicating options to apply for this peer
+ * and leaves the following words in extra_options.
+ */
+static void
+set_allowed_addrs(unit, addrs, opts)
+    int unit;
+    struct wordlist *addrs;
+    struct wordlist *opts;
+{
+    int n;
+    struct wordlist *ap, **plink;
+    struct permitted_ip *ip;
+    char *ptr_word, *ptr_mask;
+    struct hostent *hp;
+    struct netent *np;
+    u32_t a, mask, ah, offset;
+    struct ipcp_options *wo = &ipcp_wantoptions[unit];
+    u32_t suggested_ip = 0;
+
+    if (addresses[unit] != NULL)
+	free(addresses[unit]);
+    addresses[unit] = NULL;
+    if (extra_options != NULL)
+	free_wordlist(extra_options);
+    extra_options = opts;
+
+    /*
+     * Count the number of IP addresses given.
+     */
+    n = wordlist_count(addrs) + wordlist_count(noauth_addrs);
+    if (n == 0)
+	return;
+    ip = (struct permitted_ip *) malloc((n + 1) * sizeof(struct permitted_ip));
+    if (ip == 0)
+	return;
+
+    /* temporarily append the noauth_addrs list to addrs */
+    for (plink = &addrs; *plink != NULL; plink = &(*plink)->next)
+	;
+    *plink = noauth_addrs;
+
+    n = 0;
+    for (ap = addrs; ap != NULL; ap = ap->next) {
+	/* "-" means no addresses authorized, "*" means any address allowed */
+	ptr_word = ap->word;
+	if (strcmp(ptr_word, "-") == 0)
+	    break;
+	if (strcmp(ptr_word, "*") == 0) {
+	    ip[n].permit = 1;
+	    ip[n].base = ip[n].mask = 0;
+	    ++n;
+	    break;
+	}
+
+	ip[n].permit = 1;
+	if (*ptr_word == '!') {
+	    ip[n].permit = 0;
+	    ++ptr_word;
+	}
+
+	mask = ~ (u32_t) 0;
+	offset = 0;
+	ptr_mask = strchr (ptr_word, '/');
+	if (ptr_mask != NULL) {
+	    int bit_count;
+	    char *endp;
+
+	    bit_count = (int) strtol (ptr_mask+1, &endp, 10);
+	    if (bit_count <= 0 || bit_count > 32) {
+		ppp_warn("invalid address length %v in auth. address list",
+		     ptr_mask+1);
+		continue;
+	    }
+	    bit_count = 32 - bit_count;	/* # bits in host part */
+	    if (*endp == '+') {
+		offset = ifunit + 1;
+		++endp;
+	    }
+	    if (*endp != 0) {
+		ppp_warn("invalid address length syntax: %v", ptr_mask+1);
+		continue;
+	    }
+	    *ptr_mask = '\0';
+	    mask <<= bit_count;
+	}
+
+	hp = gethostbyname(ptr_word);
+	if (hp != NULL && hp->h_addrtype == AF_INET) {
+	    a = *(u32_t *)hp->h_addr;
+	} else {
+	    np = getnetbyname (ptr_word);
+	    if (np != NULL && np->n_addrtype == AF_INET) {
+		a = lwip_htonl ((u32_t)np->n_net);
+		if (ptr_mask == NULL) {
+		    /* calculate appropriate mask for net */
+		    ah = lwip_ntohl(a);
+		    if (IN_CLASSA(ah))
+			mask = IN_CLASSA_NET;
+		    else if (IN_CLASSB(ah))
+			mask = IN_CLASSB_NET;
+		    else if (IN_CLASSC(ah))
+			mask = IN_CLASSC_NET;
+		}
+	    } else {
+		a = inet_addr (ptr_word);
+	    }
+	}
+
+	if (ptr_mask != NULL)
+	    *ptr_mask = '/';
+
+	if (a == (u32_t)-1L) {
+	    ppp_warn("unknown host %s in auth. address list", ap->word);
+	    continue;
+	}
+	if (offset != 0) {
+	    if (offset >= ~mask) {
+		ppp_warn("interface unit %d too large for subnet %v",
+		     ifunit, ptr_word);
+		continue;
+	    }
+	    a = lwip_htonl((lwip_ntohl(a) & mask) + offset);
+	    mask = ~(u32_t)0;
+	}
+	ip[n].mask = lwip_htonl(mask);
+	ip[n].base = a & ip[n].mask;
+	++n;
+	if (~mask == 0 && suggested_ip == 0)
+	    suggested_ip = a;
+    }
+    *plink = NULL;
+
+    ip[n].permit = 0;		/* make the last entry forbid all addresses */
+    ip[n].base = 0;		/* to terminate the list */
+    ip[n].mask = 0;
+
+    addresses[unit] = ip;
+
+    /*
+     * If the address given for the peer isn't authorized, or if
+     * the user hasn't given one, AND there is an authorized address
+     * which is a single host, then use that if we find one.
+     */
+    if (suggested_ip != 0
+	&& (wo->hisaddr == 0 || !auth_ip_addr(unit, wo->hisaddr))) {
+	wo->hisaddr = suggested_ip;
+	/*
+	 * Do we insist on this address?  No, if there are other
+	 * addresses authorized than the suggested one.
+	 */
+	if (n > 1)
+	    wo->accept_remote = 1;
+    }
+}
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int
+auth_ip_addr(unit, addr)
+    int unit;
+    u32_t addr;
+{
+    int ok;
+
+    /* don't allow loopback or multicast address */
+    if (bad_ip_adrs(addr))
+	return 0;
+
+    if (allowed_address_hook) {
+	ok = allowed_address_hook(addr);
+	if (ok >= 0) return ok;
+    }
+
+    if (addresses[unit] != NULL) {
+	ok = ip_addr_check(addr, addresses[unit]);
+	if (ok >= 0)
+	    return ok;
+    }
+
+    if (auth_required)
+	return 0;		/* no addresses authorized */
+    return allow_any_ip || privileged || !have_route_to(addr);
+}
+
+static int
+ip_addr_check(addr, addrs)
+    u32_t addr;
+    struct permitted_ip *addrs;
+{
+    for (; ; ++addrs)
+	if ((addr & addrs->mask) == addrs->base)
+	    return addrs->permit;
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int
+bad_ip_adrs(addr)
+    u32_t addr;
+{
+    addr = lwip_ntohl(addr);
+    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+	|| IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+/*
+ * some_ip_ok - check a wordlist to see if it authorizes any
+ * IP address(es).
+ */
+static int
+some_ip_ok(addrs)
+    struct wordlist *addrs;
+{
+    for (; addrs != 0; addrs = addrs->next) {
+	if (addrs->word[0] == '-')
+	    break;
+	if (addrs->word[0] != '!')
+	    return 1;		/* some IP address is allowed */
+    }
+    return 0;
+}
+
+/*
+ * auth_number - check whether the remote number is allowed to connect.
+ * Returns 1 if authorized, 0 otherwise.
+ */
+int
+auth_number()
+{
+    struct wordlist *wp = permitted_numbers;
+    int l;
+
+    /* Allow all if no authorization list. */
+    if (!wp)
+	return 1;
+
+    /* Allow if we have a match in the authorization list. */
+    while (wp) {
+	/* trailing '*' wildcard */
+	l = strlen(wp->word);
+	if ((wp->word)[l - 1] == '*')
+	    l--;
+	if (!strncasecmp(wp->word, remote_number, l))
+	    return 1;
+	wp = wp->next;
+    }
+
+    return 0;
+}
+
+/*
+ * check_access - complain if a secret file has too-liberal permissions.
+ */
+static void
+check_access(f, filename)
+    FILE *f;
+    char *filename;
+{
+    struct stat sbuf;
+
+    if (fstat(fileno(f), &sbuf) < 0) {
+	ppp_warn("cannot stat secret file %s: %m", filename);
+    } else if ((sbuf.st_mode & (S_IRWXG | S_IRWXO)) != 0) {
+	ppp_warn("Warning - secret file %s has world and/or group access",
+	     filename);
+    }
+}
+
+/*
+ * scan_authfile - Scan an authorization file for a secret suitable
+ * for authenticating `client' on `server'.  The return value is -1
+ * if no secret is found, otherwise >= 0.  The return value has
+ * NONWILD_CLIENT set if the secret didn't have "*" for the client, and
+ * NONWILD_SERVER set if the secret didn't have "*" for the server.
+ * Any following words on the line up to a "--" (i.e. address authorization
+ * info) are placed in a wordlist and returned in *addrs.  Any
+ * following words (extra options) are placed in a wordlist and
+ * returned in *opts.
+ * We assume secret is NULL or points to MAXWORDLEN bytes of space.
+ * Flags are non-zero if we need two colons in the secret in order to
+ * match.
+ */
+static int
+scan_authfile(f, client, server, secret, addrs, opts, filename, flags)
+    FILE *f;
+    char *client;
+    char *server;
+    char *secret;
+    struct wordlist **addrs;
+    struct wordlist **opts;
+    char *filename;
+    int flags;
+{
+    int newline, xxx;
+    int got_flag, best_flag;
+    FILE *sf;
+    struct wordlist *ap, *addr_list, *alist, **app;
+    char word[MAXWORDLEN];
+    char atfile[MAXWORDLEN];
+    char lsecret[MAXWORDLEN];
+    char *cp;
+
+    if (addrs != NULL)
+	*addrs = NULL;
+    if (opts != NULL)
+	*opts = NULL;
+    addr_list = NULL;
+    if (!getword(f, word, &newline, filename))
+	return -1;		/* file is empty??? */
+    newline = 1;
+    best_flag = -1;
+    for (;;) {
+	/*
+	 * Skip until we find a word at the start of a line.
+	 */
+	while (!newline && getword(f, word, &newline, filename))
+	    ;
+	if (!newline)
+	    break;		/* got to end of file */
+
+	/*
+	 * Got a client - check if it's a match or a wildcard.
+	 */
+	got_flag = 0;
+	if (client != NULL && strcmp(word, client) != 0 && !ISWILD(word)) {
+	    newline = 0;
+	    continue;
+	}
+	if (!ISWILD(word))
+	    got_flag = NONWILD_CLIENT;
+
+	/*
+	 * Now get a server and check if it matches.
+	 */
+	if (!getword(f, word, &newline, filename))
+	    break;
+	if (newline)
+	    continue;
+	if (!ISWILD(word)) {
+	    if (server != NULL && strcmp(word, server) != 0)
+		continue;
+	    got_flag |= NONWILD_SERVER;
+	}
+
+	/*
+	 * Got some sort of a match - see if it's better than what
+	 * we have already.
+	 */
+	if (got_flag <= best_flag)
+	    continue;
+
+	/*
+	 * Get the secret.
+	 */
+	if (!getword(f, word, &newline, filename))
+	    break;
+	if (newline)
+	    continue;
+
+	/*
+	 * SRP-SHA1 authenticator should never be reading secrets from
+	 * a file.  (Authenticatee may, though.)
+	 */
+	if (flags && ((cp = strchr(word, ':')) == NULL ||
+	    strchr(cp + 1, ':') == NULL))
+	    continue;
+
+	if (secret != NULL) {
+	    /*
+	     * Special syntax: @/pathname means read secret from file.
+	     */
+	    if (word[0] == '@' && word[1] == '/') {
+		strlcpy(atfile, word+1, sizeof(atfile));
+		if ((sf = fopen(atfile, "r")) == NULL) {
+		    ppp_warn("can't open indirect secret file %s", atfile);
+		    continue;
+		}
+		check_access(sf, atfile);
+		if (!getword(sf, word, &xxx, atfile)) {
+		    ppp_warn("no secret in indirect secret file %s", atfile);
+		    fclose(sf);
+		    continue;
+		}
+		fclose(sf);
+	    }
+	    strlcpy(lsecret, word, sizeof(lsecret));
+	}
+
+	/*
+	 * Now read address authorization info and make a wordlist.
+	 */
+	app = &alist;
+	for (;;) {
+	    if (!getword(f, word, &newline, filename) || newline)
+		break;
+	    ap = (struct wordlist *)
+		    malloc(sizeof(struct wordlist) + strlen(word) + 1);
+	    if (ap == NULL)
+		novm("authorized addresses");
+	    ap->word = (char *) (ap + 1);
+	    strcpy(ap->word, word);
+	    *app = ap;
+	    app = &ap->next;
+	}
+	*app = NULL;
+
+	/*
+	 * This is the best so far; remember it.
+	 */
+	best_flag = got_flag;
+	if (addr_list)
+	    free_wordlist(addr_list);
+	addr_list = alist;
+	if (secret != NULL)
+	    strlcpy(secret, lsecret, MAXWORDLEN);
+
+	if (!newline)
+	    break;
+    }
+
+    /* scan for a -- word indicating the start of options */
+    for (app = &addr_list; (ap = *app) != NULL; app = &ap->next)
+	if (strcmp(ap->word, "--") == 0)
+	    break;
+    /* ap = start of options */
+    if (ap != NULL) {
+	ap = ap->next;		/* first option */
+	free(*app);			/* free the "--" word */
+	*app = NULL;		/* terminate addr list */
+    }
+    if (opts != NULL)
+	*opts = ap;
+    else if (ap != NULL)
+	free_wordlist(ap);
+    if (addrs != NULL)
+	*addrs = addr_list;
+    else if (addr_list != NULL)
+	free_wordlist(addr_list);
+
+    return best_flag;
+}
+
+/*
+ * wordlist_count - return the number of items in a wordlist
+ */
+static int
+wordlist_count(wp)
+    struct wordlist *wp;
+{
+    int n;
+
+    for (n = 0; wp != NULL; wp = wp->next)
+	++n;
+    return n;
+}
+
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void
+free_wordlist(wp)
+    struct wordlist *wp;
+{
+    struct wordlist *next;
+
+    while (wp != NULL) {
+	next = wp->next;
+	free(wp);
+	wp = next;
+    }
+}
+#endif /* UNUSED */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ccp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ccp.c
new file mode 100644
index 000000000..f8519ebec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ccp.c
@@ -0,0 +1,1740 @@
+/*
+ * ccp.c - PPP Compression Control Protocol.
+ *
+ * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CCP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/ccp.h"
+
+#if MPPE_SUPPORT
+#include "netif/ppp/lcp.h"	/* lcp_close(), lcp_fsm */
+#include "netif/ppp/mppe.h"	/* mppe_init() */
+#endif /* MPPE_SUPPORT */
+
+/*
+ * Unfortunately there is a bug in zlib which means that using a
+ * size of 8 (window size = 256) for Deflate compression will cause
+ * buffer overruns and kernel crashes in the deflate module.
+ * Until this is fixed we only accept sizes in the range 9 .. 15.
+ * Thanks to James Carlson for pointing this out.
+ */
+#define DEFLATE_MIN_WORKS	9
+
+/*
+ * Command-line options.
+ */
+#if PPP_OPTIONS
+static int setbsdcomp (char **);
+static int setdeflate (char **);
+static char bsd_value[8];
+static char deflate_value[8];
+
+/*
+ * Option variables.
+ */
+#if MPPE_SUPPORT
+bool refuse_mppe_stateful = 1;		/* Allow stateful mode? */
+#endif /* MPPE_SUPPORT */
+
+static option_t ccp_option_list[] = {
+    { "noccp", o_bool, &ccp_protent.enabled_flag,
+      "Disable CCP negotiation" },
+    { "-ccp", o_bool, &ccp_protent.enabled_flag,
+      "Disable CCP negotiation", OPT_ALIAS },
+
+    { "bsdcomp", o_special, (void *)setbsdcomp,
+      "Request BSD-Compress packet compression",
+      OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, bsd_value },
+    { "nobsdcomp", o_bool, &ccp_wantoptions[0].bsd_compress,
+      "don't allow BSD-Compress", OPT_PRIOSUB | OPT_A2CLR,
+      &ccp_allowoptions[0].bsd_compress },
+    { "-bsdcomp", o_bool, &ccp_wantoptions[0].bsd_compress,
+      "don't allow BSD-Compress", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR,
+      &ccp_allowoptions[0].bsd_compress },
+
+    { "deflate", o_special, (void *)setdeflate,
+      "request Deflate compression",
+      OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, deflate_value },
+    { "nodeflate", o_bool, &ccp_wantoptions[0].deflate,
+      "don't allow Deflate compression", OPT_PRIOSUB | OPT_A2CLR,
+      &ccp_allowoptions[0].deflate },
+    { "-deflate", o_bool, &ccp_wantoptions[0].deflate,
+      "don't allow Deflate compression", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR,
+      &ccp_allowoptions[0].deflate },
+
+    { "nodeflatedraft", o_bool, &ccp_wantoptions[0].deflate_draft,
+      "don't use draft deflate #", OPT_A2COPY,
+      &ccp_allowoptions[0].deflate_draft },
+
+    { "predictor1", o_bool, &ccp_wantoptions[0].predictor_1,
+      "request Predictor-1", OPT_PRIO | 1 },
+    { "nopredictor1", o_bool, &ccp_wantoptions[0].predictor_1,
+      "don't allow Predictor-1", OPT_PRIOSUB | OPT_A2CLR,
+      &ccp_allowoptions[0].predictor_1 },
+    { "-predictor1", o_bool, &ccp_wantoptions[0].predictor_1,
+      "don't allow Predictor-1", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR,
+      &ccp_allowoptions[0].predictor_1 },
+
+#if MPPE_SUPPORT
+    /* MPPE options are symmetrical ... we only set wantoptions here */
+    { "require-mppe", o_bool, &ccp_wantoptions[0].mppe,
+      "require MPPE encryption",
+      OPT_PRIO | MPPE_OPT_40 | MPPE_OPT_128 },
+    { "+mppe", o_bool, &ccp_wantoptions[0].mppe,
+      "require MPPE encryption",
+      OPT_ALIAS | OPT_PRIO | MPPE_OPT_40 | MPPE_OPT_128 },
+    { "nomppe", o_bool, &ccp_wantoptions[0].mppe,
+      "don't allow MPPE encryption", OPT_PRIO },
+    { "-mppe", o_bool, &ccp_wantoptions[0].mppe,
+      "don't allow MPPE encryption", OPT_ALIAS | OPT_PRIO },
+
+    /* We use ccp_allowoptions[0].mppe as a junk var ... it is reset later */
+    { "require-mppe-40", o_bool, &ccp_allowoptions[0].mppe,
+      "require MPPE 40-bit encryption", OPT_PRIO | OPT_A2OR | MPPE_OPT_40,
+      &ccp_wantoptions[0].mppe },
+    { "+mppe-40", o_bool, &ccp_allowoptions[0].mppe,
+      "require MPPE 40-bit encryption", OPT_PRIO | OPT_A2OR | MPPE_OPT_40,
+      &ccp_wantoptions[0].mppe },
+    { "nomppe-40", o_bool, &ccp_allowoptions[0].mppe,
+      "don't allow MPPE 40-bit encryption",
+      OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_40, &ccp_wantoptions[0].mppe },
+    { "-mppe-40", o_bool, &ccp_allowoptions[0].mppe,
+      "don't allow MPPE 40-bit encryption",
+      OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_40,
+      &ccp_wantoptions[0].mppe },
+
+    { "require-mppe-128", o_bool, &ccp_allowoptions[0].mppe,
+      "require MPPE 128-bit encryption", OPT_PRIO | OPT_A2OR | MPPE_OPT_128,
+      &ccp_wantoptions[0].mppe },
+    { "+mppe-128", o_bool, &ccp_allowoptions[0].mppe,
+      "require MPPE 128-bit encryption",
+      OPT_ALIAS | OPT_PRIO | OPT_A2OR | MPPE_OPT_128,
+      &ccp_wantoptions[0].mppe },
+    { "nomppe-128", o_bool, &ccp_allowoptions[0].mppe,
+      "don't allow MPPE 128-bit encryption",
+      OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_128, &ccp_wantoptions[0].mppe },
+    { "-mppe-128", o_bool, &ccp_allowoptions[0].mppe,
+      "don't allow MPPE 128-bit encryption",
+      OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_128,
+      &ccp_wantoptions[0].mppe },
+
+    /* strange one; we always request stateless, but will we allow stateful? */
+    { "mppe-stateful", o_bool, &refuse_mppe_stateful,
+      "allow MPPE stateful mode", OPT_PRIO },
+    { "nomppe-stateful", o_bool, &refuse_mppe_stateful,
+      "disallow MPPE stateful mode", OPT_PRIO | 1 },
+#endif /* MPPE_SUPPORT */
+
+    { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ccp_init(ppp_pcb *pcb);
+static void ccp_open(ppp_pcb *pcb);
+static void ccp_close(ppp_pcb *pcb, const char *reason);
+static void ccp_lowerup(ppp_pcb *pcb);
+static void ccp_lowerdown(ppp_pcb *pcb);
+static void ccp_input(ppp_pcb *pcb, u_char *pkt, int len);
+static void ccp_protrej(ppp_pcb *pcb);
+#if PRINTPKT_SUPPORT
+static int ccp_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+static void ccp_datainput(ppp_pcb *pcb, u_char *pkt, int len);
+#endif /* PPP_DATAINPUT */
+
+const struct protent ccp_protent = {
+    PPP_CCP,
+    ccp_init,
+    ccp_input,
+    ccp_protrej,
+    ccp_lowerup,
+    ccp_lowerdown,
+    ccp_open,
+    ccp_close,
+#if PRINTPKT_SUPPORT
+    ccp_printpkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    ccp_datainput,
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    "CCP",
+    "Compressed",
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    ccp_option_list,
+    NULL,
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    NULL,
+    NULL
+#endif /* DEMAND_SUPPORT */
+};
+
+/*
+ * Callbacks for fsm code.
+ */
+static void ccp_resetci (fsm *);
+static int  ccp_cilen (fsm *);
+static void ccp_addci (fsm *, u_char *, int *);
+static int  ccp_ackci (fsm *, u_char *, int);
+static int  ccp_nakci (fsm *, u_char *, int, int);
+static int  ccp_rejci (fsm *, u_char *, int);
+static int  ccp_reqci (fsm *, u_char *, int *, int);
+static void ccp_up (fsm *);
+static void ccp_down (fsm *);
+static int  ccp_extcode (fsm *, int, int, u_char *, int);
+static void ccp_rack_timeout (void *);
+static const char *method_name (ccp_options *, ccp_options *);
+
+static const fsm_callbacks ccp_callbacks = {
+    ccp_resetci,
+    ccp_cilen,
+    ccp_addci,
+    ccp_ackci,
+    ccp_nakci,
+    ccp_rejci,
+    ccp_reqci,
+    ccp_up,
+    ccp_down,
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    ccp_extcode,
+    "CCP"
+};
+
+/*
+ * Do we want / did we get any compression?
+ */
+static int ccp_anycompress(ccp_options *opt) {
+    return (0
+#if DEFLATE_SUPPORT
+	|| (opt)->deflate
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+	|| (opt)->bsd_compress
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+	|| (opt)->predictor_1 || (opt)->predictor_2
+#endif /* PREDICTOR_SUPPORT */
+#if MPPE_SUPPORT
+	|| (opt)->mppe
+#endif /* MPPE_SUPPORT */
+	);
+}
+
+/*
+ * Local state (mainly for handling reset-reqs and reset-acks).
+ */
+#define RACK_PENDING	1	/* waiting for reset-ack */
+#define RREQ_REPEAT	2	/* send another reset-req if no reset-ack */
+
+#define RACKTIMEOUT	1	/* second */
+
+#if PPP_OPTIONS
+/*
+ * Option parsing
+ */
+static int
+setbsdcomp(argv)
+    char **argv;
+{
+    int rbits, abits;
+    char *str, *endp;
+
+    str = *argv;
+    abits = rbits = strtol(str, &endp, 0);
+    if (endp != str && *endp == ',') {
+	str = endp + 1;
+	abits = strtol(str, &endp, 0);
+    }
+    if (*endp != 0 || endp == str) {
+	option_error("invalid parameter '%s' for bsdcomp option", *argv);
+	return 0;
+    }
+    if ((rbits != 0 && (rbits < BSD_MIN_BITS || rbits > BSD_MAX_BITS))
+	|| (abits != 0 && (abits < BSD_MIN_BITS || abits > BSD_MAX_BITS))) {
+	option_error("bsdcomp option values must be 0 or %d .. %d",
+		     BSD_MIN_BITS, BSD_MAX_BITS);
+	return 0;
+    }
+    if (rbits > 0) {
+	ccp_wantoptions[0].bsd_compress = 1;
+	ccp_wantoptions[0].bsd_bits = rbits;
+    } else
+	ccp_wantoptions[0].bsd_compress = 0;
+    if (abits > 0) {
+	ccp_allowoptions[0].bsd_compress = 1;
+	ccp_allowoptions[0].bsd_bits = abits;
+    } else
+	ccp_allowoptions[0].bsd_compress = 0;
+    ppp_slprintf(bsd_value, sizeof(bsd_value),
+	     rbits == abits? "%d": "%d,%d", rbits, abits);
+
+    return 1;
+}
+
+static int
+setdeflate(argv)
+    char **argv;
+{
+    int rbits, abits;
+    char *str, *endp;
+
+    str = *argv;
+    abits = rbits = strtol(str, &endp, 0);
+    if (endp != str && *endp == ',') {
+	str = endp + 1;
+	abits = strtol(str, &endp, 0);
+    }
+    if (*endp != 0 || endp == str) {
+	option_error("invalid parameter '%s' for deflate option", *argv);
+	return 0;
+    }
+    if ((rbits != 0 && (rbits < DEFLATE_MIN_SIZE || rbits > DEFLATE_MAX_SIZE))
+	|| (abits != 0 && (abits < DEFLATE_MIN_SIZE
+			  || abits > DEFLATE_MAX_SIZE))) {
+	option_error("deflate option values must be 0 or %d .. %d",
+		     DEFLATE_MIN_SIZE, DEFLATE_MAX_SIZE);
+	return 0;
+    }
+    if (rbits == DEFLATE_MIN_SIZE || abits == DEFLATE_MIN_SIZE) {
+	if (rbits == DEFLATE_MIN_SIZE)
+	    rbits = DEFLATE_MIN_WORKS;
+	if (abits == DEFLATE_MIN_SIZE)
+	    abits = DEFLATE_MIN_WORKS;
+	warn("deflate option value of %d changed to %d to avoid zlib bug",
+	     DEFLATE_MIN_SIZE, DEFLATE_MIN_WORKS);
+    }
+    if (rbits > 0) {
+	ccp_wantoptions[0].deflate = 1;
+	ccp_wantoptions[0].deflate_size = rbits;
+    } else
+	ccp_wantoptions[0].deflate = 0;
+    if (abits > 0) {
+	ccp_allowoptions[0].deflate = 1;
+	ccp_allowoptions[0].deflate_size = abits;
+    } else
+	ccp_allowoptions[0].deflate = 0;
+    ppp_slprintf(deflate_value, sizeof(deflate_value),
+	     rbits == abits? "%d": "%d,%d", rbits, abits);
+
+    return 1;
+}
+#endif /* PPP_OPTIONS */
+
+/*
+ * ccp_init - initialize CCP.
+ */
+static void ccp_init(ppp_pcb *pcb) {
+    fsm *f = &pcb->ccp_fsm;
+
+    f->pcb = pcb;
+    f->protocol = PPP_CCP;
+    f->callbacks = &ccp_callbacks;
+    fsm_init(f);
+
+#if 0 /* Not necessary, everything is cleared in ppp_new() */
+    memset(wo, 0, sizeof(*wo));
+    memset(go, 0, sizeof(*go));
+    memset(ao, 0, sizeof(*ao));
+    memset(ho, 0, sizeof(*ho));
+#endif /* 0 */
+
+#if DEFLATE_SUPPORT
+    wo->deflate = 1;
+    wo->deflate_size = DEFLATE_MAX_SIZE;
+    wo->deflate_correct = 1;
+    wo->deflate_draft = 1;
+    ao->deflate = 1;
+    ao->deflate_size = DEFLATE_MAX_SIZE;
+    ao->deflate_correct = 1;
+    ao->deflate_draft = 1;
+#endif /* DEFLATE_SUPPORT */
+
+#if BSDCOMPRESS_SUPPORT
+    wo->bsd_compress = 1;
+    wo->bsd_bits = BSD_MAX_BITS;
+    ao->bsd_compress = 1;
+    ao->bsd_bits = BSD_MAX_BITS;
+#endif /* BSDCOMPRESS_SUPPORT */
+
+#if PREDICTOR_SUPPORT
+    ao->predictor_1 = 1;
+#endif /* PREDICTOR_SUPPORT */
+}
+
+/*
+ * ccp_open - CCP is allowed to come up.
+ */
+static void ccp_open(ppp_pcb *pcb) {
+    fsm *f = &pcb->ccp_fsm;
+    ccp_options *go = &pcb->ccp_gotoptions;
+
+    if (f->state != PPP_FSM_OPENED)
+	ccp_set(pcb, 1, 0, 0, 0);
+
+    /*
+     * Find out which compressors the kernel supports before
+     * deciding whether to open in silent mode.
+     */
+    ccp_resetci(f);
+    if (!ccp_anycompress(go))
+	f->flags |= OPT_SILENT;
+
+    fsm_open(f);
+}
+
+/*
+ * ccp_close - Terminate CCP.
+ */
+static void ccp_close(ppp_pcb *pcb, const char *reason) {
+    fsm *f = &pcb->ccp_fsm;
+    ccp_set(pcb, 0, 0, 0, 0);
+    fsm_close(f, reason);
+}
+
+/*
+ * ccp_lowerup - we may now transmit CCP packets.
+ */
+static void ccp_lowerup(ppp_pcb *pcb) {
+    fsm *f = &pcb->ccp_fsm;
+    fsm_lowerup(f);
+}
+
+/*
+ * ccp_lowerdown - we may not transmit CCP packets.
+ */
+static void ccp_lowerdown(ppp_pcb *pcb) {
+    fsm *f = &pcb->ccp_fsm;
+    fsm_lowerdown(f);
+}
+
+/*
+ * ccp_input - process a received CCP packet.
+ */
+static void ccp_input(ppp_pcb *pcb, u_char *p, int len) {
+    fsm *f = &pcb->ccp_fsm;
+    ccp_options *go = &pcb->ccp_gotoptions;
+    int oldstate;
+
+    /*
+     * Check for a terminate-request so we can print a message.
+     */
+    oldstate = f->state;
+    fsm_input(f, p, len);
+    if (oldstate == PPP_FSM_OPENED && p[0] == TERMREQ && f->state != PPP_FSM_OPENED) {
+	ppp_notice("Compression disabled by peer.");
+#if MPPE_SUPPORT
+	if (go->mppe) {
+	    ppp_error("MPPE disabled, closing LCP");
+	    lcp_close(pcb, "MPPE disabled by peer");
+	}
+#endif /* MPPE_SUPPORT */
+    }
+
+    /*
+     * If we get a terminate-ack and we're not asking for compression,
+     * close CCP.
+     */
+    if (oldstate == PPP_FSM_REQSENT && p[0] == TERMACK
+	&& !ccp_anycompress(go))
+	ccp_close(pcb, "No compression negotiated");
+}
+
+/*
+ * Handle a CCP-specific code.
+ */
+static int ccp_extcode(fsm *f, int code, int id, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    LWIP_UNUSED_ARG(p);
+    LWIP_UNUSED_ARG(len);
+
+    switch (code) {
+    case CCP_RESETREQ:
+	if (f->state != PPP_FSM_OPENED)
+	    break;
+	ccp_reset_comp(pcb);
+	/* send a reset-ack, which the transmitter will see and
+	   reset its compression state. */
+	fsm_sdata(f, CCP_RESETACK, id, NULL, 0);
+	break;
+
+    case CCP_RESETACK:
+	if ((pcb->ccp_localstate & RACK_PENDING) && id == f->reqid) {
+	    pcb->ccp_localstate &= ~(RACK_PENDING | RREQ_REPEAT);
+	    UNTIMEOUT(ccp_rack_timeout, f);
+	    ccp_reset_decomp(pcb);
+	}
+	break;
+
+    default:
+	return 0;
+    }
+
+    return 1;
+}
+
+/*
+ * ccp_protrej - peer doesn't talk CCP.
+ */
+static void ccp_protrej(ppp_pcb *pcb) {
+    fsm *f = &pcb->ccp_fsm;
+#if MPPE_SUPPORT
+    ccp_options *go = &pcb->ccp_gotoptions;
+#endif /* MPPE_SUPPORT */
+
+    ccp_set(pcb, 0, 0, 0, 0);
+    fsm_lowerdown(f);
+
+#if MPPE_SUPPORT
+    if (go->mppe) {
+	ppp_error("MPPE required but peer negotiation failed");
+	lcp_close(pcb, "MPPE required but peer negotiation failed");
+    }
+#endif /* MPPE_SUPPORT */
+
+}
+
+/*
+ * ccp_resetci - initialize at start of negotiation.
+ */
+static void ccp_resetci(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+    ccp_options *wo = &pcb->ccp_wantoptions;
+#if MPPE_SUPPORT
+    ccp_options *ao = &pcb->ccp_allowoptions;
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT
+    u_char opt_buf[CCP_MAX_OPTION_LENGTH];
+#endif /* DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT */
+#if DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT
+    int res;
+#endif /* DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT */
+
+#if MPPE_SUPPORT
+    if (pcb->settings.require_mppe) {
+	wo->mppe = ao->mppe =
+		    (pcb->settings.refuse_mppe_40 ? 0 : MPPE_OPT_40)
+		  | (pcb->settings.refuse_mppe_128 ? 0 : MPPE_OPT_128);
+    }
+#endif /* MPPE_SUPPORT */
+
+    *go = *wo;
+    pcb->ccp_all_rejected = 0;
+
+#if MPPE_SUPPORT
+    if (go->mppe) {
+	int auth_mschap_bits = pcb->auth_done;
+	int numbits;
+
+	/*
+	 * Start with a basic sanity check: mschap[v2] auth must be in
+	 * exactly one direction.  RFC 3079 says that the keys are
+	 * 'derived from the credentials of the peer that initiated the call',
+	 * however the PPP protocol doesn't have such a concept, and pppd
+	 * cannot get this info externally.  Instead we do the best we can.
+	 * NB: If MPPE is required, all other compression opts are invalid.
+	 *     So, we return right away if we can't do it.
+	 */
+
+	/* Leave only the mschap auth bits set */
+	auth_mschap_bits &= (CHAP_MS_WITHPEER  | CHAP_MS_PEER |
+			     CHAP_MS2_WITHPEER | CHAP_MS2_PEER);
+	/* Count the mschap auths */
+	auth_mschap_bits >>= CHAP_MS_SHIFT;
+	numbits = 0;
+	do {
+	    numbits += auth_mschap_bits & 1;
+	    auth_mschap_bits >>= 1;
+	} while (auth_mschap_bits);
+	if (numbits > 1) {
+	    ppp_error("MPPE required, but auth done in both directions.");
+	    lcp_close(pcb, "MPPE required but not available");
+	    return;
+	}
+	if (!numbits) {
+	    ppp_error("MPPE required, but MS-CHAP[v2] auth not performed.");
+	    lcp_close(pcb, "MPPE required but not available");
+	    return;
+	}
+
+	/* A plugin (eg radius) may not have obtained key material. */
+	if (!pcb->mppe_keys_set) {
+	    ppp_error("MPPE required, but keys are not available.  "
+		  "Possible plugin problem?");
+	    lcp_close(pcb, "MPPE required but not available");
+	    return;
+	}
+
+	/* LM auth not supported for MPPE */
+	if (pcb->auth_done & (CHAP_MS_WITHPEER | CHAP_MS_PEER)) {
+	    /* This might be noise */
+	    if (go->mppe & MPPE_OPT_40) {
+		ppp_notice("Disabling 40-bit MPPE; MS-CHAP LM not supported");
+		go->mppe &= ~MPPE_OPT_40;
+		wo->mppe &= ~MPPE_OPT_40;
+	    }
+	}
+
+	/* Last check: can we actually negotiate something? */
+	if (!(go->mppe & (MPPE_OPT_40 | MPPE_OPT_128))) {
+	    /* Could be misconfig, could be 40-bit disabled above. */
+	    ppp_error("MPPE required, but both 40-bit and 128-bit disabled.");
+	    lcp_close(pcb, "MPPE required but not available");
+	    return;
+	}
+
+	/* sync options */
+	ao->mppe = go->mppe;
+	/* MPPE is not compatible with other compression types */
+#if BSDCOMPRESS_SUPPORT
+	ao->bsd_compress = go->bsd_compress = 0;
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+	ao->predictor_1  = go->predictor_1  = 0;
+	ao->predictor_2  = go->predictor_2  = 0;
+#endif /* PREDICTOR_SUPPORT */
+#if DEFLATE_SUPPORT
+	ao->deflate      = go->deflate      = 0;
+#endif /* DEFLATE_SUPPORT */
+    }
+#endif /* MPPE_SUPPORT */
+
+    /*
+     * Check whether the kernel knows about the various
+     * compression methods we might request.
+     */
+#if BSDCOMPRESS_SUPPORT
+    /* FIXME: we don't need to test if BSD compress is available
+     * if BSDCOMPRESS_SUPPORT is set, it is.
+     */
+    if (go->bsd_compress) {
+	opt_buf[0] = CI_BSD_COMPRESS;
+	opt_buf[1] = CILEN_BSD_COMPRESS;
+	for (;;) {
+	    if (go->bsd_bits < BSD_MIN_BITS) {
+		go->bsd_compress = 0;
+		break;
+	    }
+	    opt_buf[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits);
+	    res = ccp_test(pcb, opt_buf, CILEN_BSD_COMPRESS, 0);
+	    if (res > 0) {
+		break;
+	    } else if (res < 0) {
+		go->bsd_compress = 0;
+		break;
+	    }
+	    go->bsd_bits--;
+	}
+    }
+#endif /* BSDCOMPRESS_SUPPORT */
+#if DEFLATE_SUPPORT
+    /* FIXME: we don't need to test if deflate is available
+     * if DEFLATE_SUPPORT is set, it is.
+     */
+    if (go->deflate) {
+	if (go->deflate_correct) {
+	    opt_buf[0] = CI_DEFLATE;
+	    opt_buf[1] = CILEN_DEFLATE;
+	    opt_buf[3] = DEFLATE_CHK_SEQUENCE;
+	    for (;;) {
+		if (go->deflate_size < DEFLATE_MIN_WORKS) {
+		    go->deflate_correct = 0;
+		    break;
+		}
+		opt_buf[2] = DEFLATE_MAKE_OPT(go->deflate_size);
+		res = ccp_test(pcb, opt_buf, CILEN_DEFLATE, 0);
+		if (res > 0) {
+		    break;
+		} else if (res < 0) {
+		    go->deflate_correct = 0;
+		    break;
+		}
+		go->deflate_size--;
+	    }
+	}
+	if (go->deflate_draft) {
+	    opt_buf[0] = CI_DEFLATE_DRAFT;
+	    opt_buf[1] = CILEN_DEFLATE;
+	    opt_buf[3] = DEFLATE_CHK_SEQUENCE;
+	    for (;;) {
+		if (go->deflate_size < DEFLATE_MIN_WORKS) {
+		    go->deflate_draft = 0;
+		    break;
+		}
+		opt_buf[2] = DEFLATE_MAKE_OPT(go->deflate_size);
+		res = ccp_test(pcb, opt_buf, CILEN_DEFLATE, 0);
+		if (res > 0) {
+		    break;
+		} else if (res < 0) {
+		    go->deflate_draft = 0;
+		    break;
+		}
+		go->deflate_size--;
+	    }
+	}
+	if (!go->deflate_correct && !go->deflate_draft)
+	    go->deflate = 0;
+    }
+#endif /* DEFLATE_SUPPORT */
+#if PREDICTOR_SUPPORT
+    /* FIXME: we don't need to test if predictor is available,
+     * if PREDICTOR_SUPPORT is set, it is.
+     */
+    if (go->predictor_1) {
+	opt_buf[0] = CI_PREDICTOR_1;
+	opt_buf[1] = CILEN_PREDICTOR_1;
+	if (ccp_test(pcb, opt_buf, CILEN_PREDICTOR_1, 0) <= 0)
+	    go->predictor_1 = 0;
+    }
+    if (go->predictor_2) {
+	opt_buf[0] = CI_PREDICTOR_2;
+	opt_buf[1] = CILEN_PREDICTOR_2;
+	if (ccp_test(pcb, opt_buf, CILEN_PREDICTOR_2, 0) <= 0)
+	    go->predictor_2 = 0;
+    }
+#endif /* PREDICTOR_SUPPORT */
+}
+
+/*
+ * ccp_cilen - Return total length of our configuration info.
+ */
+static int ccp_cilen(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+
+    return 0
+#if BSDCOMPRESS_SUPPORT
+	+ (go->bsd_compress? CILEN_BSD_COMPRESS: 0)
+#endif /* BSDCOMPRESS_SUPPORT */
+#if DEFLATE_SUPPORT
+	+ (go->deflate && go->deflate_correct? CILEN_DEFLATE: 0)
+	+ (go->deflate && go->deflate_draft? CILEN_DEFLATE: 0)
+#endif /* DEFLATE_SUPPORT */
+#if PREDICTOR_SUPPORT
+	+ (go->predictor_1? CILEN_PREDICTOR_1: 0)
+	+ (go->predictor_2? CILEN_PREDICTOR_2: 0)
+#endif /* PREDICTOR_SUPPORT */
+#if MPPE_SUPPORT
+	+ (go->mppe? CILEN_MPPE: 0)
+#endif /* MPPE_SUPPORT */
+	;
+}
+
+/*
+ * ccp_addci - put our requests in a packet.
+ */
+static void ccp_addci(fsm *f, u_char *p, int *lenp) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+    u_char *p0 = p;
+
+    /*
+     * Add the compression types that we can receive, in decreasing
+     * preference order.
+     */
+#if MPPE_SUPPORT
+    if (go->mppe) {
+	p[0] = CI_MPPE;
+	p[1] = CILEN_MPPE;
+	MPPE_OPTS_TO_CI(go->mppe, &p[2]);
+	mppe_init(pcb, &pcb->mppe_decomp, go->mppe);
+	p += CILEN_MPPE;
+    }
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+    if (go->deflate) {
+	if (go->deflate_correct) {
+	    p[0] = CI_DEFLATE;
+	    p[1] = CILEN_DEFLATE;
+	    p[2] = DEFLATE_MAKE_OPT(go->deflate_size);
+	    p[3] = DEFLATE_CHK_SEQUENCE;
+	    p += CILEN_DEFLATE;
+	}
+	if (go->deflate_draft) {
+	    p[0] = CI_DEFLATE_DRAFT;
+	    p[1] = CILEN_DEFLATE;
+	    p[2] = p[2 - CILEN_DEFLATE];
+	    p[3] = DEFLATE_CHK_SEQUENCE;
+	    p += CILEN_DEFLATE;
+	}
+    }
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    if (go->bsd_compress) {
+	p[0] = CI_BSD_COMPRESS;
+	p[1] = CILEN_BSD_COMPRESS;
+	p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits);
+	p += CILEN_BSD_COMPRESS;
+    }
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+    /* XXX Should Predictor 2 be preferable to Predictor 1? */
+    if (go->predictor_1) {
+	p[0] = CI_PREDICTOR_1;
+	p[1] = CILEN_PREDICTOR_1;
+	p += CILEN_PREDICTOR_1;
+    }
+    if (go->predictor_2) {
+	p[0] = CI_PREDICTOR_2;
+	p[1] = CILEN_PREDICTOR_2;
+	p += CILEN_PREDICTOR_2;
+    }
+#endif /* PREDICTOR_SUPPORT */
+
+    go->method = (p > p0)? p0[0]: 0;
+
+    *lenp = p - p0;
+}
+
+/*
+ * ccp_ackci - process a received configure-ack, and return
+ * 1 iff the packet was OK.
+ */
+static int ccp_ackci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+#if BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT
+    u_char *p0 = p;
+#endif /* BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT */
+
+#if MPPE_SUPPORT
+    if (go->mppe) {
+	u_char opt_buf[CILEN_MPPE];
+
+	opt_buf[0] = CI_MPPE;
+	opt_buf[1] = CILEN_MPPE;
+	MPPE_OPTS_TO_CI(go->mppe, &opt_buf[2]);
+	if (len < CILEN_MPPE || memcmp(opt_buf, p, CILEN_MPPE))
+	    return 0;
+	p += CILEN_MPPE;
+	len -= CILEN_MPPE;
+	/* XXX Cope with first/fast ack */
+	if (len == 0)
+	    return 1;
+    }
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+    if (go->deflate) {
+	if (len < CILEN_DEFLATE
+	    || p[0] != (go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT)
+	    || p[1] != CILEN_DEFLATE
+	    || p[2] != DEFLATE_MAKE_OPT(go->deflate_size)
+	    || p[3] != DEFLATE_CHK_SEQUENCE)
+	    return 0;
+	p += CILEN_DEFLATE;
+	len -= CILEN_DEFLATE;
+	/* XXX Cope with first/fast ack */
+	if (len == 0)
+	    return 1;
+	if (go->deflate_correct && go->deflate_draft) {
+	    if (len < CILEN_DEFLATE
+		|| p[0] != CI_DEFLATE_DRAFT
+		|| p[1] != CILEN_DEFLATE
+		|| p[2] != DEFLATE_MAKE_OPT(go->deflate_size)
+		|| p[3] != DEFLATE_CHK_SEQUENCE)
+		return 0;
+	    p += CILEN_DEFLATE;
+	    len -= CILEN_DEFLATE;
+	}
+    }
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    if (go->bsd_compress) {
+	if (len < CILEN_BSD_COMPRESS
+	    || p[0] != CI_BSD_COMPRESS || p[1] != CILEN_BSD_COMPRESS
+	    || p[2] != BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits))
+	    return 0;
+	p += CILEN_BSD_COMPRESS;
+	len -= CILEN_BSD_COMPRESS;
+	/* XXX Cope with first/fast ack */
+	if (p == p0 && len == 0)
+	    return 1;
+    }
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+    if (go->predictor_1) {
+	if (len < CILEN_PREDICTOR_1
+	    || p[0] != CI_PREDICTOR_1 || p[1] != CILEN_PREDICTOR_1)
+	    return 0;
+	p += CILEN_PREDICTOR_1;
+	len -= CILEN_PREDICTOR_1;
+	/* XXX Cope with first/fast ack */
+	if (p == p0 && len == 0)
+	    return 1;
+    }
+    if (go->predictor_2) {
+	if (len < CILEN_PREDICTOR_2
+	    || p[0] != CI_PREDICTOR_2 || p[1] != CILEN_PREDICTOR_2)
+	    return 0;
+	p += CILEN_PREDICTOR_2;
+	len -= CILEN_PREDICTOR_2;
+	/* XXX Cope with first/fast ack */
+	if (p == p0 && len == 0)
+	    return 1;
+    }
+#endif /* PREDICTOR_SUPPORT */
+
+    if (len != 0)
+	return 0;
+    return 1;
+}
+
+/*
+ * ccp_nakci - process received configure-nak.
+ * Returns 1 iff the nak was OK.
+ */
+static int ccp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+    ccp_options no;		/* options we've seen already */
+    ccp_options try_;		/* options to ask for next time */
+    LWIP_UNUSED_ARG(treat_as_reject);
+#if !MPPE_SUPPORT && !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT
+    LWIP_UNUSED_ARG(p);
+    LWIP_UNUSED_ARG(len);
+#endif /* !MPPE_SUPPORT && !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT */
+
+    memset(&no, 0, sizeof(no));
+    try_ = *go;
+
+#if MPPE_SUPPORT
+    if (go->mppe && len >= CILEN_MPPE
+	&& p[0] == CI_MPPE && p[1] == CILEN_MPPE) {
+	no.mppe = 1;
+	/*
+	 * Peer wants us to use a different strength or other setting.
+	 * Fail if we aren't willing to use his suggestion.
+	 */
+	MPPE_CI_TO_OPTS(&p[2], try_.mppe);
+	if ((try_.mppe & MPPE_OPT_STATEFUL) && pcb->settings.refuse_mppe_stateful) {
+	    ppp_error("Refusing MPPE stateful mode offered by peer");
+	    try_.mppe = 0;
+	} else if (((go->mppe | MPPE_OPT_STATEFUL) & try_.mppe) != try_.mppe) {
+	    /* Peer must have set options we didn't request (suggest) */
+	    try_.mppe = 0;
+	}
+
+	if (!try_.mppe) {
+	    ppp_error("MPPE required but peer negotiation failed");
+	    lcp_close(pcb, "MPPE required but peer negotiation failed");
+	}
+    }
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+    if (go->deflate && len >= CILEN_DEFLATE
+	&& p[0] == (go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT)
+	&& p[1] == CILEN_DEFLATE) {
+	no.deflate = 1;
+	/*
+	 * Peer wants us to use a different code size or something.
+	 * Stop asking for Deflate if we don't understand his suggestion.
+	 */
+	if (DEFLATE_METHOD(p[2]) != DEFLATE_METHOD_VAL
+	    || DEFLATE_SIZE(p[2]) < DEFLATE_MIN_WORKS
+	    || p[3] != DEFLATE_CHK_SEQUENCE)
+	    try_.deflate = 0;
+	else if (DEFLATE_SIZE(p[2]) < go->deflate_size)
+	    try_.deflate_size = DEFLATE_SIZE(p[2]);
+	p += CILEN_DEFLATE;
+	len -= CILEN_DEFLATE;
+	if (go->deflate_correct && go->deflate_draft
+	    && len >= CILEN_DEFLATE && p[0] == CI_DEFLATE_DRAFT
+	    && p[1] == CILEN_DEFLATE) {
+	    p += CILEN_DEFLATE;
+	    len -= CILEN_DEFLATE;
+	}
+    }
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    if (go->bsd_compress && len >= CILEN_BSD_COMPRESS
+	&& p[0] == CI_BSD_COMPRESS && p[1] == CILEN_BSD_COMPRESS) {
+	no.bsd_compress = 1;
+	/*
+	 * Peer wants us to use a different number of bits
+	 * or a different version.
+	 */
+	if (BSD_VERSION(p[2]) != BSD_CURRENT_VERSION)
+	    try_.bsd_compress = 0;
+	else if (BSD_NBITS(p[2]) < go->bsd_bits)
+	    try_.bsd_bits = BSD_NBITS(p[2]);
+	p += CILEN_BSD_COMPRESS;
+	len -= CILEN_BSD_COMPRESS;
+    }
+#endif /* BSDCOMPRESS_SUPPORT */
+
+    /*
+     * Predictor-1 and 2 have no options, so they can't be Naked.
+     *
+     * There may be remaining options but we ignore them.
+     */
+
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+    return 1;
+}
+
+/*
+ * ccp_rejci - reject some of our suggested compression methods.
+ */
+static int ccp_rejci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+    ccp_options try_;		/* options to request next time */
+
+    try_ = *go;
+
+    /*
+     * Cope with empty configure-rejects by ceasing to send
+     * configure-requests.
+     */
+    if (len == 0 && pcb->ccp_all_rejected)
+	return -1;
+
+#if MPPE_SUPPORT
+    if (go->mppe && len >= CILEN_MPPE
+	&& p[0] == CI_MPPE && p[1] == CILEN_MPPE) {
+	ppp_error("MPPE required but peer refused");
+	lcp_close(pcb, "MPPE required but peer refused");
+	p += CILEN_MPPE;
+	len -= CILEN_MPPE;
+    }
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+    if (go->deflate_correct && len >= CILEN_DEFLATE
+	&& p[0] == CI_DEFLATE && p[1] == CILEN_DEFLATE) {
+	if (p[2] != DEFLATE_MAKE_OPT(go->deflate_size)
+	    || p[3] != DEFLATE_CHK_SEQUENCE)
+	    return 0;		/* Rej is bad */
+	try_.deflate_correct = 0;
+	p += CILEN_DEFLATE;
+	len -= CILEN_DEFLATE;
+    }
+    if (go->deflate_draft && len >= CILEN_DEFLATE
+	&& p[0] == CI_DEFLATE_DRAFT && p[1] == CILEN_DEFLATE) {
+	if (p[2] != DEFLATE_MAKE_OPT(go->deflate_size)
+	    || p[3] != DEFLATE_CHK_SEQUENCE)
+	    return 0;		/* Rej is bad */
+	try_.deflate_draft = 0;
+	p += CILEN_DEFLATE;
+	len -= CILEN_DEFLATE;
+    }
+    if (!try_.deflate_correct && !try_.deflate_draft)
+	try_.deflate = 0;
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    if (go->bsd_compress && len >= CILEN_BSD_COMPRESS
+	&& p[0] == CI_BSD_COMPRESS && p[1] == CILEN_BSD_COMPRESS) {
+	if (p[2] != BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits))
+	    return 0;
+	try_.bsd_compress = 0;
+	p += CILEN_BSD_COMPRESS;
+	len -= CILEN_BSD_COMPRESS;
+    }
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+    if (go->predictor_1 && len >= CILEN_PREDICTOR_1
+	&& p[0] == CI_PREDICTOR_1 && p[1] == CILEN_PREDICTOR_1) {
+	try_.predictor_1 = 0;
+	p += CILEN_PREDICTOR_1;
+	len -= CILEN_PREDICTOR_1;
+    }
+    if (go->predictor_2 && len >= CILEN_PREDICTOR_2
+	&& p[0] == CI_PREDICTOR_2 && p[1] == CILEN_PREDICTOR_2) {
+	try_.predictor_2 = 0;
+	p += CILEN_PREDICTOR_2;
+	len -= CILEN_PREDICTOR_2;
+    }
+#endif /* PREDICTOR_SUPPORT */
+
+    if (len != 0)
+	return 0;
+
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+
+    return 1;
+}
+
+/*
+ * ccp_reqci - processed a received configure-request.
+ * Returns CONFACK, CONFNAK or CONFREJ and the packet modified
+ * appropriately.
+ */
+static int ccp_reqci(fsm *f, u_char *p, int *lenp, int dont_nak) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *ho = &pcb->ccp_hisoptions;
+    ccp_options *ao = &pcb->ccp_allowoptions;
+    int ret, newret;
+#if DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT
+    int res;
+    int nb;
+#endif /* DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT */
+    u_char *p0, *retp;
+    int len, clen, type;
+#if MPPE_SUPPORT
+    u8_t rej_for_ci_mppe = 1;	/* Are we rejecting based on a bad/missing */
+				/* CI_MPPE, or due to other options?       */
+#endif /* MPPE_SUPPORT */
+
+    ret = CONFACK;
+    retp = p0 = p;
+    len = *lenp;
+
+    memset(ho, 0, sizeof(ccp_options));
+    ho->method = (len > 0)? p[0]: 0;
+
+    while (len > 0) {
+	newret = CONFACK;
+	if (len < 2 || p[1] < 2 || p[1] > len) {
+	    /* length is bad */
+	    clen = len;
+	    newret = CONFREJ;
+
+	} else {
+	    type = p[0];
+	    clen = p[1];
+
+	    switch (type) {
+#if MPPE_SUPPORT
+	    case CI_MPPE:
+		if (!ao->mppe || clen != CILEN_MPPE) {
+		    newret = CONFREJ;
+		    break;
+		}
+		MPPE_CI_TO_OPTS(&p[2], ho->mppe);
+
+		/* Nak if anything unsupported or unknown are set. */
+		if (ho->mppe & MPPE_OPT_UNSUPPORTED) {
+		    newret = CONFNAK;
+		    ho->mppe &= ~MPPE_OPT_UNSUPPORTED;
+		}
+		if (ho->mppe & MPPE_OPT_UNKNOWN) {
+		    newret = CONFNAK;
+		    ho->mppe &= ~MPPE_OPT_UNKNOWN;
+		}
+
+		/* Check state opt */
+		if (ho->mppe & MPPE_OPT_STATEFUL) {
+		    /*
+		     * We can Nak and request stateless, but it's a
+		     * lot easier to just assume the peer will request
+		     * it if he can do it; stateful mode is bad over
+		     * the Internet -- which is where we expect MPPE.
+		     */
+		   if (pcb->settings.refuse_mppe_stateful) {
+			ppp_error("Refusing MPPE stateful mode offered by peer");
+			newret = CONFREJ;
+			break;
+		    }
+		}
+
+		/* Find out which of {S,L} are set. */
+		if ((ho->mppe & MPPE_OPT_128)
+		     && (ho->mppe & MPPE_OPT_40)) {
+		    /* Both are set, negotiate the strongest. */
+		    newret = CONFNAK;
+		    if (ao->mppe & MPPE_OPT_128)
+			ho->mppe &= ~MPPE_OPT_40;
+		    else if (ao->mppe & MPPE_OPT_40)
+			ho->mppe &= ~MPPE_OPT_128;
+		    else {
+			newret = CONFREJ;
+			break;
+		    }
+		} else if (ho->mppe & MPPE_OPT_128) {
+		    if (!(ao->mppe & MPPE_OPT_128)) {
+			newret = CONFREJ;
+			break;
+		    }
+		} else if (ho->mppe & MPPE_OPT_40) {
+		    if (!(ao->mppe & MPPE_OPT_40)) {
+			newret = CONFREJ;
+			break;
+		    }
+		} else {
+		    /* Neither are set. */
+		    /* We cannot accept this.  */
+		    newret = CONFNAK;
+		    /* Give the peer our idea of what can be used,
+		       so it can choose and confirm */
+		    ho->mppe = ao->mppe;
+		}
+
+		/* rebuild the opts */
+		MPPE_OPTS_TO_CI(ho->mppe, &p[2]);
+		if (newret == CONFACK) {
+		    int mtu;
+
+		    mppe_init(pcb, &pcb->mppe_comp, ho->mppe);
+		    /*
+		     * We need to decrease the interface MTU by MPPE_PAD
+		     * because MPPE frames **grow**.  The kernel [must]
+		     * allocate MPPE_PAD extra bytes in xmit buffers.
+		     */
+		    mtu = netif_get_mtu(pcb);
+		    if (mtu)
+			netif_set_mtu(pcb, mtu - MPPE_PAD);
+		    else
+			newret = CONFREJ;
+		}
+
+		/*
+		 * We have accepted MPPE or are willing to negotiate
+		 * MPPE parameters.  A CONFREJ is due to subsequent
+		 * (non-MPPE) processing.
+		 */
+		rej_for_ci_mppe = 0;
+		break;
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+	    case CI_DEFLATE:
+	    case CI_DEFLATE_DRAFT:
+		if (!ao->deflate || clen != CILEN_DEFLATE
+		    || (!ao->deflate_correct && type == CI_DEFLATE)
+		    || (!ao->deflate_draft && type == CI_DEFLATE_DRAFT)) {
+		    newret = CONFREJ;
+		    break;
+		}
+
+		ho->deflate = 1;
+		ho->deflate_size = nb = DEFLATE_SIZE(p[2]);
+		if (DEFLATE_METHOD(p[2]) != DEFLATE_METHOD_VAL
+		    || p[3] != DEFLATE_CHK_SEQUENCE
+		    || nb > ao->deflate_size || nb < DEFLATE_MIN_WORKS) {
+		    newret = CONFNAK;
+		    if (!dont_nak) {
+			p[2] = DEFLATE_MAKE_OPT(ao->deflate_size);
+			p[3] = DEFLATE_CHK_SEQUENCE;
+			/* fall through to test this #bits below */
+		    } else
+			break;
+		}
+
+		/*
+		 * Check whether we can do Deflate with the window
+		 * size they want.  If the window is too big, reduce
+		 * it until the kernel can cope and nak with that.
+		 * We only check this for the first option.
+		 */
+		if (p == p0) {
+		    for (;;) {
+			res = ccp_test(pcb, p, CILEN_DEFLATE, 1);
+			if (res > 0)
+			    break;		/* it's OK now */
+			if (res < 0 || nb == DEFLATE_MIN_WORKS || dont_nak) {
+			    newret = CONFREJ;
+			    p[2] = DEFLATE_MAKE_OPT(ho->deflate_size);
+			    break;
+			}
+			newret = CONFNAK;
+			--nb;
+			p[2] = DEFLATE_MAKE_OPT(nb);
+		    }
+		}
+		break;
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+	    case CI_BSD_COMPRESS:
+		if (!ao->bsd_compress || clen != CILEN_BSD_COMPRESS) {
+		    newret = CONFREJ;
+		    break;
+		}
+
+		ho->bsd_compress = 1;
+		ho->bsd_bits = nb = BSD_NBITS(p[2]);
+		if (BSD_VERSION(p[2]) != BSD_CURRENT_VERSION
+		    || nb > ao->bsd_bits || nb < BSD_MIN_BITS) {
+		    newret = CONFNAK;
+		    if (!dont_nak) {
+			p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, ao->bsd_bits);
+			/* fall through to test this #bits below */
+		    } else
+			break;
+		}
+
+		/*
+		 * Check whether we can do BSD-Compress with the code
+		 * size they want.  If the code size is too big, reduce
+		 * it until the kernel can cope and nak with that.
+		 * We only check this for the first option.
+		 */
+		if (p == p0) {
+		    for (;;) {
+			res = ccp_test(pcb, p, CILEN_BSD_COMPRESS, 1);
+			if (res > 0)
+			    break;
+			if (res < 0 || nb == BSD_MIN_BITS || dont_nak) {
+			    newret = CONFREJ;
+			    p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION,
+						ho->bsd_bits);
+			    break;
+			}
+			newret = CONFNAK;
+			--nb;
+			p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, nb);
+		    }
+		}
+		break;
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+	    case CI_PREDICTOR_1:
+		if (!ao->predictor_1 || clen != CILEN_PREDICTOR_1) {
+		    newret = CONFREJ;
+		    break;
+		}
+
+		ho->predictor_1 = 1;
+		if (p == p0
+		    && ccp_test(pcb, p, CILEN_PREDICTOR_1, 1) <= 0) {
+		    newret = CONFREJ;
+		}
+		break;
+
+	    case CI_PREDICTOR_2:
+		if (!ao->predictor_2 || clen != CILEN_PREDICTOR_2) {
+		    newret = CONFREJ;
+		    break;
+		}
+
+		ho->predictor_2 = 1;
+		if (p == p0
+		    && ccp_test(pcb, p, CILEN_PREDICTOR_2, 1) <= 0) {
+		    newret = CONFREJ;
+		}
+		break;
+#endif /* PREDICTOR_SUPPORT */
+
+	    default:
+		newret = CONFREJ;
+	    }
+	}
+
+	if (newret == CONFNAK && dont_nak)
+	    newret = CONFREJ;
+	if (!(newret == CONFACK || (newret == CONFNAK && ret == CONFREJ))) {
+	    /* we're returning this option */
+	    if (newret == CONFREJ && ret == CONFNAK)
+		retp = p0;
+	    ret = newret;
+	    if (p != retp)
+		MEMCPY(retp, p, clen);
+	    retp += clen;
+	}
+
+	p += clen;
+	len -= clen;
+    }
+
+    if (ret != CONFACK) {
+	if (ret == CONFREJ && *lenp == retp - p0)
+	    pcb->ccp_all_rejected = 1;
+	else
+	    *lenp = retp - p0;
+    }
+#if MPPE_SUPPORT
+    if (ret == CONFREJ && ao->mppe && rej_for_ci_mppe) {
+	ppp_error("MPPE required but peer negotiation failed");
+	lcp_close(pcb, "MPPE required but peer negotiation failed");
+    }
+#endif /* MPPE_SUPPORT */
+    return ret;
+}
+
+/*
+ * Make a string name for a compression method (or 2).
+ */
+static const char *method_name(ccp_options *opt, ccp_options *opt2) {
+    static char result[64];
+#if !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT
+    LWIP_UNUSED_ARG(opt2);
+#endif /* !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT */
+
+    if (!ccp_anycompress(opt))
+	return "(none)";
+    switch (opt->method) {
+#if MPPE_SUPPORT
+    case CI_MPPE:
+    {
+	char *p = result;
+	char *q = result + sizeof(result); /* 1 past result */
+
+	ppp_slprintf(p, q - p, "MPPE ");
+	p += 5;
+	if (opt->mppe & MPPE_OPT_128) {
+	    ppp_slprintf(p, q - p, "128-bit ");
+	    p += 8;
+	}
+	if (opt->mppe & MPPE_OPT_40) {
+	    ppp_slprintf(p, q - p, "40-bit ");
+	    p += 7;
+	}
+	if (opt->mppe & MPPE_OPT_STATEFUL)
+	    ppp_slprintf(p, q - p, "stateful");
+	else
+	    ppp_slprintf(p, q - p, "stateless");
+
+	break;
+    }
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+    case CI_DEFLATE:
+    case CI_DEFLATE_DRAFT:
+	if (opt2 != NULL && opt2->deflate_size != opt->deflate_size)
+	    ppp_slprintf(result, sizeof(result), "Deflate%s (%d/%d)",
+		     (opt->method == CI_DEFLATE_DRAFT? "(old#)": ""),
+		     opt->deflate_size, opt2->deflate_size);
+	else
+	    ppp_slprintf(result, sizeof(result), "Deflate%s (%d)",
+		     (opt->method == CI_DEFLATE_DRAFT? "(old#)": ""),
+		     opt->deflate_size);
+	break;
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+    case CI_BSD_COMPRESS:
+	if (opt2 != NULL && opt2->bsd_bits != opt->bsd_bits)
+	    ppp_slprintf(result, sizeof(result), "BSD-Compress (%d/%d)",
+		     opt->bsd_bits, opt2->bsd_bits);
+	else
+	    ppp_slprintf(result, sizeof(result), "BSD-Compress (%d)",
+		     opt->bsd_bits);
+	break;
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+    case CI_PREDICTOR_1:
+	return "Predictor 1";
+    case CI_PREDICTOR_2:
+	return "Predictor 2";
+#endif /* PREDICTOR_SUPPORT */
+    default:
+	ppp_slprintf(result, sizeof(result), "Method %d", opt->method);
+    }
+    return result;
+}
+
+/*
+ * CCP has come up - inform the kernel driver and log a message.
+ */
+static void ccp_up(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ccp_options *go = &pcb->ccp_gotoptions;
+    ccp_options *ho = &pcb->ccp_hisoptions;
+    char method1[64];
+
+    ccp_set(pcb, 1, 1, go->method, ho->method);
+    if (ccp_anycompress(go)) {
+	if (ccp_anycompress(ho)) {
+	    if (go->method == ho->method) {
+		ppp_notice("%s compression enabled", method_name(go, ho));
+	    } else {
+		ppp_strlcpy(method1, method_name(go, NULL), sizeof(method1));
+		ppp_notice("%s / %s compression enabled",
+		       method1, method_name(ho, NULL));
+	    }
+	} else
+	    ppp_notice("%s receive compression enabled", method_name(go, NULL));
+    } else if (ccp_anycompress(ho))
+	ppp_notice("%s transmit compression enabled", method_name(ho, NULL));
+#if MPPE_SUPPORT
+    if (go->mppe) {
+	continue_networks(pcb);		/* Bring up IP et al */
+    }
+#endif /* MPPE_SUPPORT */
+}
+
+/*
+ * CCP has gone down - inform the kernel driver.
+ */
+static void ccp_down(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+#if MPPE_SUPPORT
+    ccp_options *go = &pcb->ccp_gotoptions;
+#endif /* MPPE_SUPPORT */
+
+    if (pcb->ccp_localstate & RACK_PENDING)
+	UNTIMEOUT(ccp_rack_timeout, f);
+    pcb->ccp_localstate = 0;
+    ccp_set(pcb, 1, 0, 0, 0);
+#if MPPE_SUPPORT
+    if (go->mppe) {
+	go->mppe = 0;
+	if (pcb->lcp_fsm.state == PPP_FSM_OPENED) {
+	    /* If LCP is not already going down, make sure it does. */
+	    ppp_error("MPPE disabled");
+	    lcp_close(pcb, "MPPE disabled");
+	}
+    }
+#endif /* MPPE_SUPPORT */
+}
+
+#if PRINTPKT_SUPPORT
+/*
+ * Print the contents of a CCP packet.
+ */
+static const char* const ccp_codenames[] = {
+    "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+    "TermReq", "TermAck", "CodeRej",
+    NULL, NULL, NULL, NULL, NULL, NULL,
+    "ResetReq", "ResetAck",
+};
+
+static int ccp_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg) {
+    const u_char *p0, *optend;
+    int code, id, len;
+    int optlen;
+
+    p0 = p;
+    if (plen < HEADERLEN)
+	return 0;
+    code = p[0];
+    id = p[1];
+    len = (p[2] << 8) + p[3];
+    if (len < HEADERLEN || len > plen)
+	return 0;
+
+    if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(ccp_codenames) && ccp_codenames[code-1] != NULL)
+	printer(arg, " %s", ccp_codenames[code-1]);
+    else
+	printer(arg, " code=0x%x", code);
+    printer(arg, " id=0x%x", id);
+    len -= HEADERLEN;
+    p += HEADERLEN;
+
+    switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+	/* print list of possible compression methods */
+	while (len >= 2) {
+	    code = p[0];
+	    optlen = p[1];
+	    if (optlen < 2 || optlen > len)
+		break;
+	    printer(arg, " <");
+	    len -= optlen;
+	    optend = p + optlen;
+	    switch (code) {
+#if MPPE_SUPPORT
+	    case CI_MPPE:
+		if (optlen >= CILEN_MPPE) {
+		    u_char mppe_opts;
+
+		    MPPE_CI_TO_OPTS(&p[2], mppe_opts);
+		    printer(arg, "mppe %s %s %s %s %s %s%s",
+			    (p[2] & MPPE_H_BIT)? "+H": "-H",
+			    (p[5] & MPPE_M_BIT)? "+M": "-M",
+			    (p[5] & MPPE_S_BIT)? "+S": "-S",
+			    (p[5] & MPPE_L_BIT)? "+L": "-L",
+			    (p[5] & MPPE_D_BIT)? "+D": "-D",
+			    (p[5] & MPPE_C_BIT)? "+C": "-C",
+			    (mppe_opts & MPPE_OPT_UNKNOWN)? " +U": "");
+		    if (mppe_opts & MPPE_OPT_UNKNOWN)
+			printer(arg, " (%.2x %.2x %.2x %.2x)",
+				p[2], p[3], p[4], p[5]);
+		    p += CILEN_MPPE;
+		}
+		break;
+#endif /* MPPE_SUPPORT */
+#if DEFLATE_SUPPORT
+	    case CI_DEFLATE:
+	    case CI_DEFLATE_DRAFT:
+		if (optlen >= CILEN_DEFLATE) {
+		    printer(arg, "deflate%s %d",
+			    (code == CI_DEFLATE_DRAFT? "(old#)": ""),
+			    DEFLATE_SIZE(p[2]));
+		    if (DEFLATE_METHOD(p[2]) != DEFLATE_METHOD_VAL)
+			printer(arg, " method %d", DEFLATE_METHOD(p[2]));
+		    if (p[3] != DEFLATE_CHK_SEQUENCE)
+			printer(arg, " check %d", p[3]);
+		    p += CILEN_DEFLATE;
+		}
+		break;
+#endif /* DEFLATE_SUPPORT */
+#if BSDCOMPRESS_SUPPORT
+	    case CI_BSD_COMPRESS:
+		if (optlen >= CILEN_BSD_COMPRESS) {
+		    printer(arg, "bsd v%d %d", BSD_VERSION(p[2]),
+			    BSD_NBITS(p[2]));
+		    p += CILEN_BSD_COMPRESS;
+		}
+		break;
+#endif /* BSDCOMPRESS_SUPPORT */
+#if PREDICTOR_SUPPORT
+	    case CI_PREDICTOR_1:
+		if (optlen >= CILEN_PREDICTOR_1) {
+		    printer(arg, "predictor 1");
+		    p += CILEN_PREDICTOR_1;
+		}
+		break;
+	    case CI_PREDICTOR_2:
+		if (optlen >= CILEN_PREDICTOR_2) {
+		    printer(arg, "predictor 2");
+		    p += CILEN_PREDICTOR_2;
+		}
+		break;
+#endif /* PREDICTOR_SUPPORT */
+	    default:
+                break;
+	    }
+	    while (p < optend)
+		printer(arg, " %.2x", *p++);
+	    printer(arg, ">");
+	}
+	break;
+
+    case TERMACK:
+    case TERMREQ:
+	if (len > 0 && *p >= ' ' && *p < 0x7f) {
+	    ppp_print_string(p, len, printer, arg);
+	    p += len;
+	    len = 0;
+	}
+	break;
+    default:
+        break;
+    }
+
+    /* dump out the rest of the packet in hex */
+    while (--len >= 0)
+	printer(arg, " %.2x", *p++);
+
+    return p - p0;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#if PPP_DATAINPUT
+/*
+ * We have received a packet that the decompressor failed to
+ * decompress.  Here we would expect to issue a reset-request, but
+ * Motorola has a patent on resetting the compressor as a result of
+ * detecting an error in the decompressed data after decompression.
+ * (See US patent 5,130,993; international patent publication number
+ * WO 91/10289; Australian patent 73296/91.)
+ *
+ * So we ask the kernel whether the error was detected after
+ * decompression; if it was, we take CCP down, thus disabling
+ * compression :-(, otherwise we issue the reset-request.
+ */
+static void ccp_datainput(ppp_pcb *pcb, u_char *pkt, int len) {
+    fsm *f;
+#if MPPE_SUPPORT
+    ccp_options *go = &pcb->ccp_gotoptions;
+#endif /* MPPE_SUPPORT */
+    LWIP_UNUSED_ARG(pkt);
+    LWIP_UNUSED_ARG(len);
+
+    f = &pcb->ccp_fsm;
+    if (f->state == PPP_FSM_OPENED) {
+	if (ccp_fatal_error(pcb)) {
+	    /*
+	     * Disable compression by taking CCP down.
+	     */
+	    ppp_error("Lost compression sync: disabling compression");
+	    ccp_close(pcb, "Lost compression sync");
+#if MPPE_SUPPORT
+	    /*
+	     * If we were doing MPPE, we must also take the link down.
+	     */
+	    if (go->mppe) {
+		ppp_error("Too many MPPE errors, closing LCP");
+		lcp_close(pcb, "Too many MPPE errors");
+	    }
+#endif /* MPPE_SUPPORT */
+	} else {
+	    /*
+	     * Send a reset-request to reset the peer's compressor.
+	     * We don't do that if we are still waiting for an
+	     * acknowledgement to a previous reset-request.
+	     */
+	    if (!(pcb->ccp_localstate & RACK_PENDING)) {
+		fsm_sdata(f, CCP_RESETREQ, f->reqid = ++f->id, NULL, 0);
+		TIMEOUT(ccp_rack_timeout, f, RACKTIMEOUT);
+		pcb->ccp_localstate |= RACK_PENDING;
+	    } else
+		pcb->ccp_localstate |= RREQ_REPEAT;
+	}
+    }
+}
+#endif /* PPP_DATAINPUT */
+
+/*
+ * We have received a packet that the decompressor failed to
+ * decompress. Issue a reset-request.
+ */
+void ccp_resetrequest(ppp_pcb *pcb) {
+    fsm *f = &pcb->ccp_fsm;
+
+    if (f->state != PPP_FSM_OPENED)
+	return;
+
+    /*
+     * Send a reset-request to reset the peer's compressor.
+     * We don't do that if we are still waiting for an
+     * acknowledgement to a previous reset-request.
+     */
+    if (!(pcb->ccp_localstate & RACK_PENDING)) {
+	fsm_sdata(f, CCP_RESETREQ, f->reqid = ++f->id, NULL, 0);
+	TIMEOUT(ccp_rack_timeout, f, RACKTIMEOUT);
+	pcb->ccp_localstate |= RACK_PENDING;
+    } else
+	pcb->ccp_localstate |= RREQ_REPEAT;
+}
+
+/*
+ * Timeout waiting for reset-ack.
+ */
+static void ccp_rack_timeout(void *arg) {
+    fsm *f = (fsm*)arg;
+    ppp_pcb *pcb = f->pcb;
+
+    if (f->state == PPP_FSM_OPENED && (pcb->ccp_localstate & RREQ_REPEAT)) {
+	fsm_sdata(f, CCP_RESETREQ, f->reqid, NULL, 0);
+	TIMEOUT(ccp_rack_timeout, f, RACKTIMEOUT);
+	pcb->ccp_localstate &= ~RREQ_REPEAT;
+    } else
+	pcb->ccp_localstate &= ~RACK_PENDING;
+}
+
+#endif /* PPP_SUPPORT && CCP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap-md5.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap-md5.c
new file mode 100644
index 000000000..88f069f03
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap-md5.c
@@ -0,0 +1,126 @@
+/*
+ * chap-md5.c - New CHAP/MD5 implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <stdlib.h>
+#include <string.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/chap-new.h"
+#include "netif/ppp/chap-md5.h"
+#include "netif/ppp/magic.h"
+#include "netif/ppp/pppcrypt.h"
+
+#define MD5_HASH_SIZE		16
+#define MD5_MIN_CHALLENGE	17
+#define MD5_MAX_CHALLENGE	24
+#define MD5_MIN_MAX_POWER_OF_TWO_CHALLENGE     3   /* 2^3-1 = 7, 17+7 = 24 */
+
+#if PPP_SERVER
+static void chap_md5_generate_challenge(ppp_pcb *pcb, unsigned char *cp) {
+	int clen;
+	LWIP_UNUSED_ARG(pcb);
+
+	clen = MD5_MIN_CHALLENGE + magic_pow(MD5_MIN_MAX_POWER_OF_TWO_CHALLENGE);
+	*cp++ = clen;
+	magic_random_bytes(cp, clen);
+}
+
+static int chap_md5_verify_response(ppp_pcb *pcb, int id, const char *name,
+			 const unsigned char *secret, int secret_len,
+			 const unsigned char *challenge, const unsigned char *response,
+			 char *message, int message_space) {
+	lwip_md5_context ctx;
+	unsigned char idbyte = id;
+	unsigned char hash[MD5_HASH_SIZE];
+	int challenge_len, response_len;
+	LWIP_UNUSED_ARG(name);
+	LWIP_UNUSED_ARG(pcb);
+
+	challenge_len = *challenge++;
+	response_len = *response++;
+	if (response_len == MD5_HASH_SIZE) {
+		/* Generate hash of ID, secret, challenge */
+		lwip_md5_init(&ctx);
+		lwip_md5_starts(&ctx);
+		lwip_md5_update(&ctx, &idbyte, 1);
+		lwip_md5_update(&ctx, secret, secret_len);
+		lwip_md5_update(&ctx, challenge, challenge_len);
+		lwip_md5_finish(&ctx, hash);
+		lwip_md5_free(&ctx);
+
+		/* Test if our hash matches the peer's response */
+		if (memcmp(hash, response, MD5_HASH_SIZE) == 0) {
+			ppp_slprintf(message, message_space, "Access granted");
+			return 1;
+		}
+	}
+	ppp_slprintf(message, message_space, "Access denied");
+	return 0;
+}
+#endif /* PPP_SERVER */
+
+static void chap_md5_make_response(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
+		       const unsigned char *challenge, const char *secret, int secret_len,
+		       unsigned char *private_) {
+	lwip_md5_context ctx;
+	unsigned char idbyte = id;
+	int challenge_len = *challenge++;
+	LWIP_UNUSED_ARG(our_name);
+	LWIP_UNUSED_ARG(private_);
+	LWIP_UNUSED_ARG(pcb);
+
+	lwip_md5_init(&ctx);
+	lwip_md5_starts(&ctx);
+	lwip_md5_update(&ctx, &idbyte, 1);
+	lwip_md5_update(&ctx, (const u_char *)secret, secret_len);
+	lwip_md5_update(&ctx, challenge, challenge_len);
+	lwip_md5_finish(&ctx, &response[1]);
+	lwip_md5_free(&ctx);
+	response[0] = MD5_HASH_SIZE;
+}
+
+const struct chap_digest_type md5_digest = {
+	CHAP_MD5,		/* code */
+#if PPP_SERVER
+	chap_md5_generate_challenge,
+	chap_md5_verify_response,
+#endif /* PPP_SERVER */
+	chap_md5_make_response,
+	NULL,			/* check_success */
+	NULL,			/* handle_failure */
+};
+
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap-new.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap-new.c
new file mode 100644
index 000000000..485122d27
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap-new.c
@@ -0,0 +1,677 @@
+/*
+ * chap-new.c - New CHAP implementation.
+ *
+ * Copyright (c) 2003 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <stdlib.h>
+#include <string.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#if 0 /* UNUSED */
+#include "session.h"
+#endif /* UNUSED */
+
+#include "netif/ppp/chap-new.h"
+#include "netif/ppp/chap-md5.h"
+#if MSCHAP_SUPPORT
+#include "netif/ppp/chap_ms.h"
+#endif
+#include "netif/ppp/magic.h"
+
+#if 0 /* UNUSED */
+/* Hook for a plugin to validate CHAP challenge */
+int (*chap_verify_hook)(const char *name, const char *ourname, int id,
+			const struct chap_digest_type *digest,
+			const unsigned char *challenge, const unsigned char *response,
+			char *message, int message_space) = NULL;
+#endif /* UNUSED */
+
+#if PPP_OPTIONS
+/*
+ * Command-line options.
+ */
+static option_t chap_option_list[] = {
+	{ "chap-restart", o_int, &chap_timeout_time,
+	  "Set timeout for CHAP", OPT_PRIO },
+	{ "chap-max-challenge", o_int, &pcb->settings.chap_max_transmits,
+	  "Set max #xmits for challenge", OPT_PRIO },
+	{ "chap-interval", o_int, &pcb->settings.chap_rechallenge_time,
+	  "Set interval for rechallenge", OPT_PRIO },
+	{ NULL }
+};
+#endif /* PPP_OPTIONS */
+
+
+/* Values for flags in chap_client_state and chap_server_state */
+#define LOWERUP			1
+#define AUTH_STARTED		2
+#define AUTH_DONE		4
+#define AUTH_FAILED		8
+#define TIMEOUT_PENDING		0x10
+#define CHALLENGE_VALID		0x20
+
+/*
+ * Prototypes.
+ */
+static void chap_init(ppp_pcb *pcb);
+static void chap_lowerup(ppp_pcb *pcb);
+static void chap_lowerdown(ppp_pcb *pcb);
+#if PPP_SERVER
+static void chap_timeout(void *arg);
+static void chap_generate_challenge(ppp_pcb *pcb);
+static void chap_handle_response(ppp_pcb *pcb, int code,
+		unsigned char *pkt, int len);
+static int chap_verify_response(ppp_pcb *pcb, const char *name, const char *ourname, int id,
+		const struct chap_digest_type *digest,
+		const unsigned char *challenge, const unsigned char *response,
+		char *message, int message_space);
+#endif /* PPP_SERVER */
+static void chap_respond(ppp_pcb *pcb, int id,
+		unsigned char *pkt, int len);
+static void chap_handle_status(ppp_pcb *pcb, int code, int id,
+		unsigned char *pkt, int len);
+static void chap_protrej(ppp_pcb *pcb);
+static void chap_input(ppp_pcb *pcb, unsigned char *pkt, int pktlen);
+#if PRINTPKT_SUPPORT
+static int chap_print_pkt(const unsigned char *p, int plen,
+		void (*printer) (void *, const char *, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+
+/* List of digest types that we know about */
+static const struct chap_digest_type* const chap_digests[] = {
+    &md5_digest,
+#if MSCHAP_SUPPORT
+    &chapms_digest,
+    &chapms2_digest,
+#endif /* MSCHAP_SUPPORT */
+    NULL
+};
+
+/*
+ * chap_init - reset to initial state.
+ */
+static void chap_init(ppp_pcb *pcb) {
+	LWIP_UNUSED_ARG(pcb);
+
+#if 0 /* Not necessary, everything is cleared in ppp_new() */
+	memset(&pcb->chap_client, 0, sizeof(chap_client_state));
+#if PPP_SERVER
+	memset(&pcb->chap_server, 0, sizeof(chap_server_state));
+#endif /* PPP_SERVER */
+#endif /* 0 */
+}
+
+/*
+ * chap_lowerup - we can start doing stuff now.
+ */
+static void chap_lowerup(ppp_pcb *pcb) {
+
+	pcb->chap_client.flags |= LOWERUP;
+#if PPP_SERVER
+	pcb->chap_server.flags |= LOWERUP;
+	if (pcb->chap_server.flags & AUTH_STARTED)
+		chap_timeout(pcb);
+#endif /* PPP_SERVER */
+}
+
+static void chap_lowerdown(ppp_pcb *pcb) {
+
+	pcb->chap_client.flags = 0;
+#if PPP_SERVER
+	if (pcb->chap_server.flags & TIMEOUT_PENDING)
+		UNTIMEOUT(chap_timeout, pcb);
+	pcb->chap_server.flags = 0;
+#endif /* PPP_SERVER */
+}
+
+#if PPP_SERVER
+/*
+ * chap_auth_peer - Start authenticating the peer.
+ * If the lower layer is already up, we start sending challenges,
+ * otherwise we wait for the lower layer to come up.
+ */
+void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code) {
+	const struct chap_digest_type *dp;
+	int i;
+
+	if (pcb->chap_server.flags & AUTH_STARTED) {
+		ppp_error("CHAP: peer authentication already started!");
+		return;
+	}
+	for (i = 0; (dp = chap_digests[i]) != NULL; ++i)
+		if (dp->code == digest_code)
+			break;
+	if (dp == NULL)
+		ppp_fatal("CHAP digest 0x%x requested but not available",
+		      digest_code);
+
+	pcb->chap_server.digest = dp;
+	pcb->chap_server.name = our_name;
+	/* Start with a random ID value */
+	pcb->chap_server.id = magic();
+	pcb->chap_server.flags |= AUTH_STARTED;
+	if (pcb->chap_server.flags & LOWERUP)
+		chap_timeout(pcb);
+}
+#endif /* PPP_SERVER */
+
+/*
+ * chap_auth_with_peer - Prepare to authenticate ourselves to the peer.
+ * There isn't much to do until we receive a challenge.
+ */
+void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code) {
+	const struct chap_digest_type *dp;
+	int i;
+
+	if(NULL == our_name)
+		return;
+
+	if (pcb->chap_client.flags & AUTH_STARTED) {
+		ppp_error("CHAP: authentication with peer already started!");
+		return;
+	}
+	for (i = 0; (dp = chap_digests[i]) != NULL; ++i)
+		if (dp->code == digest_code)
+			break;
+
+	if (dp == NULL)
+		ppp_fatal("CHAP digest 0x%x requested but not available",
+		      digest_code);
+
+	pcb->chap_client.digest = dp;
+	pcb->chap_client.name = our_name;
+	pcb->chap_client.flags |= AUTH_STARTED;
+}
+
+#if PPP_SERVER
+/*
+ * chap_timeout - It's time to send another challenge to the peer.
+ * This could be either a retransmission of a previous challenge,
+ * or a new challenge to start re-authentication.
+ */
+static void chap_timeout(void *arg) {
+	ppp_pcb *pcb = (ppp_pcb*)arg;
+	struct pbuf *p;
+
+	pcb->chap_server.flags &= ~TIMEOUT_PENDING;
+	if ((pcb->chap_server.flags & CHALLENGE_VALID) == 0) {
+		pcb->chap_server.challenge_xmits = 0;
+		chap_generate_challenge(pcb);
+		pcb->chap_server.flags |= CHALLENGE_VALID;
+	} else if (pcb->chap_server.challenge_xmits >= pcb->settings.chap_max_transmits) {
+		pcb->chap_server.flags &= ~CHALLENGE_VALID;
+		pcb->chap_server.flags |= AUTH_DONE | AUTH_FAILED;
+		auth_peer_fail(pcb, PPP_CHAP);
+		return;
+	}
+
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(pcb->chap_server.challenge_pktlen), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+	MEMCPY(p->payload, pcb->chap_server.challenge, pcb->chap_server.challenge_pktlen);
+	ppp_write(pcb, p);
+	++pcb->chap_server.challenge_xmits;
+	pcb->chap_server.flags |= TIMEOUT_PENDING;
+	TIMEOUT(chap_timeout, arg, pcb->settings.chap_timeout_time);
+}
+
+/*
+ * chap_generate_challenge - generate a challenge string and format
+ * the challenge packet in pcb->chap_server.challenge_pkt.
+ */
+static void chap_generate_challenge(ppp_pcb *pcb) {
+	int clen = 1, nlen, len;
+	unsigned char *p;
+
+	p = pcb->chap_server.challenge;
+	MAKEHEADER(p, PPP_CHAP);
+	p += CHAP_HDRLEN;
+	pcb->chap_server.digest->generate_challenge(pcb, p);
+	clen = *p;
+	nlen = strlen(pcb->chap_server.name);
+	memcpy(p + 1 + clen, pcb->chap_server.name, nlen);
+
+	len = CHAP_HDRLEN + 1 + clen + nlen;
+	pcb->chap_server.challenge_pktlen = PPP_HDRLEN + len;
+
+	p = pcb->chap_server.challenge + PPP_HDRLEN;
+	p[0] = CHAP_CHALLENGE;
+	p[1] = ++pcb->chap_server.id;
+	p[2] = len >> 8;
+	p[3] = len;
+}
+
+/*
+ * chap_handle_response - check the response to our challenge.
+ */
+static void  chap_handle_response(ppp_pcb *pcb, int id,
+		     unsigned char *pkt, int len) {
+	int response_len, ok, mlen;
+	const unsigned char *response;
+	unsigned char *outp;
+	struct pbuf *p;
+	const char *name = NULL;	/* initialized to shut gcc up */
+#if 0 /* UNUSED */
+	int (*verifier)(const char *, const char *, int, const struct chap_digest_type *,
+		const unsigned char *, const unsigned char *, char *, int);
+#endif /* UNUSED */
+	char rname[MAXNAMELEN+1];
+	char message[256];
+
+	if ((pcb->chap_server.flags & LOWERUP) == 0)
+		return;
+	if (id != pcb->chap_server.challenge[PPP_HDRLEN+1] || len < 2)
+		return;
+	if (pcb->chap_server.flags & CHALLENGE_VALID) {
+		response = pkt;
+		GETCHAR(response_len, pkt);
+		len -= response_len + 1;	/* length of name */
+		name = (char *)pkt + response_len;
+		if (len < 0)
+			return;
+
+		if (pcb->chap_server.flags & TIMEOUT_PENDING) {
+			pcb->chap_server.flags &= ~TIMEOUT_PENDING;
+			UNTIMEOUT(chap_timeout, pcb);
+		}
+#if PPP_REMOTENAME
+		if (pcb->settings.explicit_remote) {
+			name = pcb->remote_name;
+		} else
+#endif /* PPP_REMOTENAME */
+		{
+			/* Null terminate and clean remote name. */
+			ppp_slprintf(rname, sizeof(rname), "%.*v", len, name);
+			name = rname;
+		}
+
+#if 0 /* UNUSED */
+		if (chap_verify_hook)
+			verifier = chap_verify_hook;
+		else
+			verifier = chap_verify_response;
+		ok = (*verifier)(name, pcb->chap_server.name, id, pcb->chap_server.digest,
+				 pcb->chap_server.challenge + PPP_HDRLEN + CHAP_HDRLEN,
+				 response, pcb->chap_server.message, sizeof(pcb->chap_server.message));
+#endif /* UNUSED */
+		ok = chap_verify_response(pcb, name, pcb->chap_server.name, id, pcb->chap_server.digest,
+                    pcb->chap_server.challenge + PPP_HDRLEN + CHAP_HDRLEN,
+                    response, message, sizeof(message));
+#if 0 /* UNUSED */
+		if (!ok || !auth_number()) {
+#endif /* UNUSED */
+		if (!ok) {
+			pcb->chap_server.flags |= AUTH_FAILED;
+			ppp_warn("Peer %q failed CHAP authentication", name);
+		}
+	} else if ((pcb->chap_server.flags & AUTH_DONE) == 0)
+		return;
+
+	/* send the response */
+	mlen = strlen(message);
+	len = CHAP_HDRLEN + mlen;
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN +len), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (unsigned char *)p->payload;
+	MAKEHEADER(outp, PPP_CHAP);
+
+	outp[0] = (pcb->chap_server.flags & AUTH_FAILED)? CHAP_FAILURE: CHAP_SUCCESS;
+	outp[1] = id;
+	outp[2] = len >> 8;
+	outp[3] = len;
+	if (mlen > 0)
+		memcpy(outp + CHAP_HDRLEN, message, mlen);
+	ppp_write(pcb, p);
+
+	if (pcb->chap_server.flags & CHALLENGE_VALID) {
+		pcb->chap_server.flags &= ~CHALLENGE_VALID;
+		if (!(pcb->chap_server.flags & AUTH_DONE) && !(pcb->chap_server.flags & AUTH_FAILED)) {
+
+#if 0 /* UNUSED */
+		    /*
+		     * Auth is OK, so now we need to check session restrictions
+		     * to ensure everything is OK, but only if we used a
+		     * plugin, and only if we're configured to check.  This
+		     * allows us to do PAM checks on PPP servers that
+		     * authenticate against ActiveDirectory, and use AD for
+		     * account info (like when using Winbind integrated with
+		     * PAM).
+		     */
+		    if (session_mgmt &&
+			session_check(name, NULL, devnam, NULL) == 0) {
+			pcb->chap_server.flags |= AUTH_FAILED;
+			ppp_warn("Peer %q failed CHAP Session verification", name);
+		    }
+#endif /* UNUSED */
+
+		}
+		if (pcb->chap_server.flags & AUTH_FAILED) {
+			auth_peer_fail(pcb, PPP_CHAP);
+		} else {
+			if ((pcb->chap_server.flags & AUTH_DONE) == 0)
+				auth_peer_success(pcb, PPP_CHAP,
+						  pcb->chap_server.digest->code,
+						  name, strlen(name));
+			if (pcb->settings.chap_rechallenge_time) {
+				pcb->chap_server.flags |= TIMEOUT_PENDING;
+				TIMEOUT(chap_timeout, pcb,
+					pcb->settings.chap_rechallenge_time);
+			}
+		}
+		pcb->chap_server.flags |= AUTH_DONE;
+	}
+}
+
+/*
+ * chap_verify_response - check whether the peer's response matches
+ * what we think it should be.  Returns 1 if it does (authentication
+ * succeeded), or 0 if it doesn't.
+ */
+static int chap_verify_response(ppp_pcb *pcb, const char *name, const char *ourname, int id,
+		     const struct chap_digest_type *digest,
+		     const unsigned char *challenge, const unsigned char *response,
+		     char *message, int message_space) {
+	int ok;
+	unsigned char secret[MAXSECRETLEN];
+	int secret_len;
+
+	/* Get the secret that the peer is supposed to know */
+	if (!get_secret(pcb, name, ourname, (char *)secret, &secret_len, 1)) {
+		ppp_error("No CHAP secret found for authenticating %q", name);
+		return 0;
+	}
+	ok = digest->verify_response(pcb, id, name, secret, secret_len, challenge,
+				     response, message, message_space);
+	memset(secret, 0, sizeof(secret));
+
+	return ok;
+}
+#endif /* PPP_SERVER */
+
+/*
+ * chap_respond - Generate and send a response to a challenge.
+ */
+static void chap_respond(ppp_pcb *pcb, int id,
+	     unsigned char *pkt, int len) {
+	int clen, nlen;
+	int secret_len;
+	struct pbuf *p;
+	u_char *outp;
+	char rname[MAXNAMELEN+1];
+	char secret[MAXSECRETLEN+1];
+
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(RESP_MAX_PKTLEN), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	if ((pcb->chap_client.flags & (LOWERUP | AUTH_STARTED)) != (LOWERUP | AUTH_STARTED))
+		return;		/* not ready */
+	if (len < 2 || len < pkt[0] + 1)
+		return;		/* too short */
+	clen = pkt[0];
+	nlen = len - (clen + 1);
+
+	/* Null terminate and clean remote name. */
+	ppp_slprintf(rname, sizeof(rname), "%.*v", nlen, pkt + clen + 1);
+
+#if PPP_REMOTENAME
+	/* Microsoft doesn't send their name back in the PPP packet */
+	if (pcb->settings.explicit_remote || (pcb->settings.remote_name[0] != 0 && rname[0] == 0))
+		strlcpy(rname, pcb->settings.remote_name, sizeof(rname));
+#endif /* PPP_REMOTENAME */
+
+	/* get secret for authenticating ourselves with the specified host */
+	if (!get_secret(pcb, pcb->chap_client.name, rname, secret, &secret_len, 0)) {
+		secret_len = 0;	/* assume null secret if can't find one */
+		ppp_warn("No CHAP secret found for authenticating us to %q", rname);
+	}
+
+	outp = (u_char*)p->payload;
+	MAKEHEADER(outp, PPP_CHAP);
+	outp += CHAP_HDRLEN;
+
+	pcb->chap_client.digest->make_response(pcb, outp, id, pcb->chap_client.name, pkt,
+				  secret, secret_len, pcb->chap_client.priv);
+	memset(secret, 0, secret_len);
+
+	clen = *outp;
+	nlen = strlen(pcb->chap_client.name);
+	memcpy(outp + clen + 1, pcb->chap_client.name, nlen);
+
+	outp = (u_char*)p->payload + PPP_HDRLEN;
+	len = CHAP_HDRLEN + clen + 1 + nlen;
+	outp[0] = CHAP_RESPONSE;
+	outp[1] = id;
+	outp[2] = len >> 8;
+	outp[3] = len;
+
+	pbuf_realloc(p, PPP_HDRLEN + len);
+	ppp_write(pcb, p);
+}
+
+static void chap_handle_status(ppp_pcb *pcb, int code, int id,
+		   unsigned char *pkt, int len) {
+	const char *msg = NULL;
+	LWIP_UNUSED_ARG(id);
+
+	if ((pcb->chap_client.flags & (AUTH_DONE|AUTH_STARTED|LOWERUP))
+	    != (AUTH_STARTED|LOWERUP))
+		return;
+	pcb->chap_client.flags |= AUTH_DONE;
+
+	if (code == CHAP_SUCCESS) {
+		/* used for MS-CHAP v2 mutual auth, yuck */
+		if (pcb->chap_client.digest->check_success != NULL) {
+			if (!(*pcb->chap_client.digest->check_success)(pcb, pkt, len, pcb->chap_client.priv))
+				code = CHAP_FAILURE;
+		} else
+			msg = "CHAP authentication succeeded";
+	} else {
+		if (pcb->chap_client.digest->handle_failure != NULL)
+			(*pcb->chap_client.digest->handle_failure)(pcb, pkt, len);
+		else
+			msg = "CHAP authentication failed";
+	}
+	if (msg) {
+		if (len > 0)
+			ppp_info("%s: %.*v", msg, len, pkt);
+		else
+			ppp_info("%s", msg);
+	}
+	if (code == CHAP_SUCCESS)
+		auth_withpeer_success(pcb, PPP_CHAP, pcb->chap_client.digest->code);
+	else {
+		pcb->chap_client.flags |= AUTH_FAILED;
+		ppp_error("CHAP authentication failed");
+		auth_withpeer_fail(pcb, PPP_CHAP);
+	}
+}
+
+static void chap_input(ppp_pcb *pcb, unsigned char *pkt, int pktlen) {
+	unsigned char code, id;
+	int len;
+
+	if (pktlen < CHAP_HDRLEN)
+		return;
+	GETCHAR(code, pkt);
+	GETCHAR(id, pkt);
+	GETSHORT(len, pkt);
+	if (len < CHAP_HDRLEN || len > pktlen)
+		return;
+	len -= CHAP_HDRLEN;
+
+	switch (code) {
+	case CHAP_CHALLENGE:
+		chap_respond(pcb, id, pkt, len);
+		break;
+#if PPP_SERVER
+	case CHAP_RESPONSE:
+		chap_handle_response(pcb, id, pkt, len);
+		break;
+#endif /* PPP_SERVER */
+	case CHAP_FAILURE:
+	case CHAP_SUCCESS:
+		chap_handle_status(pcb, code, id, pkt, len);
+		break;
+	default:
+		break;
+	}
+}
+
+static void chap_protrej(ppp_pcb *pcb) {
+
+#if PPP_SERVER
+	if (pcb->chap_server.flags & TIMEOUT_PENDING) {
+		pcb->chap_server.flags &= ~TIMEOUT_PENDING;
+		UNTIMEOUT(chap_timeout, pcb);
+	}
+	if (pcb->chap_server.flags & AUTH_STARTED) {
+		pcb->chap_server.flags = 0;
+		auth_peer_fail(pcb, PPP_CHAP);
+	}
+#endif /* PPP_SERVER */
+	if ((pcb->chap_client.flags & (AUTH_STARTED|AUTH_DONE)) == AUTH_STARTED) {
+		pcb->chap_client.flags &= ~AUTH_STARTED;
+		ppp_error("CHAP authentication failed due to protocol-reject");
+		auth_withpeer_fail(pcb, PPP_CHAP);
+	}
+}
+
+#if PRINTPKT_SUPPORT
+/*
+ * chap_print_pkt - print the contents of a CHAP packet.
+ */
+static const char* const chap_code_names[] = {
+	"Challenge", "Response", "Success", "Failure"
+};
+
+static int chap_print_pkt(const unsigned char *p, int plen,
+	       void (*printer) (void *, const char *, ...), void *arg) {
+	int code, id, len;
+	int clen, nlen;
+	unsigned char x;
+
+	if (plen < CHAP_HDRLEN)
+		return 0;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < CHAP_HDRLEN || len > plen)
+		return 0;
+
+	if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(chap_code_names))
+		printer(arg, " %s", chap_code_names[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= CHAP_HDRLEN;
+	switch (code) {
+	case CHAP_CHALLENGE:
+	case CHAP_RESPONSE:
+		if (len < 1)
+			break;
+		clen = p[0];
+		if (len < clen + 1)
+			break;
+		++p;
+		nlen = len - clen - 1;
+		printer(arg, " <");
+		for (; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, "%.2x", x);
+		}
+		printer(arg, ">, name = ");
+		ppp_print_string(p, nlen, printer, arg);
+		break;
+	case CHAP_FAILURE:
+	case CHAP_SUCCESS:
+		printer(arg, " ");
+		ppp_print_string(p, len, printer, arg);
+		break;
+	default:
+		for (clen = len; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, " %.2x", x);
+		}
+		/* no break */
+	}
+
+	return len + CHAP_HDRLEN;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+const struct protent chap_protent = {
+	PPP_CHAP,
+	chap_init,
+	chap_input,
+	chap_protrej,
+	chap_lowerup,
+	chap_lowerdown,
+	NULL,		/* open */
+	NULL,		/* close */
+#if PRINTPKT_SUPPORT
+	chap_print_pkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+	NULL,		/* datainput */
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+	"CHAP",		/* name */
+	NULL,		/* data_name */
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+	chap_option_list,
+	NULL,		/* check_options */
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+	NULL,
+	NULL
+#endif /* DEMAND_SUPPORT */
+};
+
+#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap_ms.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap_ms.c
new file mode 100644
index 000000000..5a989c9b7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/chap_ms.c
@@ -0,0 +1,962 @@
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+/*
+ * Modifications by Frank Cusack, frank@google.com, March 2002.
+ *
+ *   Implemented MS-CHAPv2 functionality, heavily based on sample
+ *   implementation in RFC 2759.  Implemented MPPE functionality,
+ *   heavily based on sample implementation in RFC 3079.
+ *
+ * Copyright (c) 2002 Google, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MSCHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <sys/types.h>
+#include <sys/time.h>
+#include <unistd.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/chap-new.h"
+#include "netif/ppp/chap_ms.h"
+#include "netif/ppp/pppcrypt.h"
+#include "netif/ppp/magic.h"
+#if MPPE_SUPPORT
+#include "netif/ppp/mppe.h" /* For mppe_sha1_pad*, mppe_set_key() */
+#endif /* MPPE_SUPPORT */
+
+#define SHA1_SIGNATURE_SIZE	20
+#define MD4_SIGNATURE_SIZE	16	/* 16 bytes in a MD4 message digest */
+#define MAX_NT_PASSWORD		256	/* Max (Unicode) chars in an NT pass */
+
+#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
+#define MS_CHAP2_RESPONSE_LEN	49	/* Response length for MS-CHAPv2 */
+#define MS_AUTH_RESPONSE_LENGTH	40	/* MS-CHAPv2 authenticator response, */
+					/* as ASCII */
+
+/* Error codes for MS-CHAP failure messages. */
+#define MS_CHAP_ERROR_RESTRICTED_LOGON_HOURS	646
+#define MS_CHAP_ERROR_ACCT_DISABLED		647
+#define MS_CHAP_ERROR_PASSWD_EXPIRED		648
+#define MS_CHAP_ERROR_NO_DIALIN_PERMISSION	649
+#define MS_CHAP_ERROR_AUTHENTICATION_FAILURE	691
+#define MS_CHAP_ERROR_CHANGING_PASSWORD		709
+
+/*
+ * Offsets within the response field for MS-CHAP
+ */
+#define MS_CHAP_LANMANRESP	0
+#define MS_CHAP_LANMANRESP_LEN	24
+#define MS_CHAP_NTRESP		24
+#define MS_CHAP_NTRESP_LEN	24
+#define MS_CHAP_USENT		48
+
+/*
+ * Offsets within the response field for MS-CHAP2
+ */
+#define MS_CHAP2_PEER_CHALLENGE	0
+#define MS_CHAP2_PEER_CHAL_LEN	16
+#define MS_CHAP2_RESERVED_LEN	8
+#define MS_CHAP2_NTRESP		24
+#define MS_CHAP2_NTRESP_LEN	24
+#define MS_CHAP2_FLAGS		48
+
+#if MPPE_SUPPORT
+#if 0 /* UNUSED */
+/* These values are the RADIUS attribute values--see RFC 2548. */
+#define MPPE_ENC_POL_ENC_ALLOWED 1
+#define MPPE_ENC_POL_ENC_REQUIRED 2
+#define MPPE_ENC_TYPES_RC4_40 2
+#define MPPE_ENC_TYPES_RC4_128 4
+
+/* used by plugins (using above values) */
+extern void set_mppe_enc_types(int, int);
+#endif /* UNUSED */
+#endif /* MPPE_SUPPORT */
+
+/* Are we the authenticator or authenticatee?  For MS-CHAPv2 key derivation. */
+#define MS_CHAP2_AUTHENTICATEE 0
+#define MS_CHAP2_AUTHENTICATOR 1
+
+static void	ascii2unicode (const char[], int, u_char[]);
+static void	NTPasswordHash (u_char *, int, u_char[MD4_SIGNATURE_SIZE]);
+static void	ChallengeResponse (const u_char *, const u_char *, u_char[24]);
+static void	ChallengeHash (const u_char[16], const u_char *, const char *, u_char[8]);
+static void	ChapMS_NT (const u_char *, const char *, int, u_char[24]);
+static void	ChapMS2_NT (const u_char *, const u_char[16], const char *, const char *, int,
+				u_char[24]);
+static void	GenerateAuthenticatorResponsePlain
+			(const char*, int, u_char[24], const u_char[16], const u_char *,
+			     const char *, u_char[41]);
+#ifdef MSLANMAN
+static void	ChapMS_LANMan (u_char *, char *, int, u_char *);
+#endif
+
+static void GenerateAuthenticatorResponse(const u_char PasswordHashHash[MD4_SIGNATURE_SIZE],
+			u_char NTResponse[24], const u_char PeerChallenge[16],
+			const u_char *rchallenge, const char *username,
+			u_char authResponse[MS_AUTH_RESPONSE_LENGTH+1]);
+
+#if MPPE_SUPPORT
+static void	Set_Start_Key (ppp_pcb *pcb, const u_char *, const char *, int);
+static void	SetMasterKeys (ppp_pcb *pcb, const char *, int, u_char[24], int);
+#endif /* MPPE_SUPPORT */
+
+static void ChapMS (ppp_pcb *pcb, const u_char *, const char *, int, u_char *);
+static void ChapMS2 (ppp_pcb *pcb, const u_char *, const u_char *, const char *, const char *, int,
+		  u_char *, u_char[MS_AUTH_RESPONSE_LENGTH+1], int);
+
+#ifdef MSLANMAN
+bool	ms_lanman = 0;    	/* Use LanMan password instead of NT */
+			  	/* Has meaning only with MS-CHAP challenges */
+#endif
+
+#if MPPE_SUPPORT
+#ifdef DEBUGMPPEKEY
+/* For MPPE debug */
+/* Use "[]|}{?/><,`!2&&(" (sans quotes) for RFC 3079 MS-CHAPv2 test value */
+static char *mschap_challenge = NULL;
+/* Use "!@\#$%^&*()_+:3|~" (sans quotes, backslash is to escape #) for ... */
+static char *mschap2_peer_challenge = NULL;
+#endif
+
+#include "netif/ppp/fsm.h"		/* Need to poke MPPE options */
+#include "netif/ppp/ccp.h"
+#endif /* MPPE_SUPPORT */
+
+#if PPP_OPTIONS
+/*
+ * Command-line options.
+ */
+static option_t chapms_option_list[] = {
+#ifdef MSLANMAN
+	{ "ms-lanman", o_bool, &ms_lanman,
+	  "Use LanMan passwd when using MS-CHAP", 1 },
+#endif
+#ifdef DEBUGMPPEKEY
+	{ "mschap-challenge", o_string, &mschap_challenge,
+	  "specify CHAP challenge" },
+	{ "mschap2-peer-challenge", o_string, &mschap2_peer_challenge,
+	  "specify CHAP peer challenge" },
+#endif
+	{ NULL }
+};
+#endif /* PPP_OPTIONS */
+
+#if PPP_SERVER
+/*
+ * chapms_generate_challenge - generate a challenge for MS-CHAP.
+ * For MS-CHAP the challenge length is fixed at 8 bytes.
+ * The length goes in challenge[0] and the actual challenge starts
+ * at challenge[1].
+ */
+static void chapms_generate_challenge(ppp_pcb *pcb, unsigned char *challenge) {
+	LWIP_UNUSED_ARG(pcb);
+
+	*challenge++ = 8;
+#ifdef DEBUGMPPEKEY
+	if (mschap_challenge && strlen(mschap_challenge) == 8)
+		memcpy(challenge, mschap_challenge, 8);
+	else
+#endif
+		magic_random_bytes(challenge, 8);
+}
+
+static void chapms2_generate_challenge(ppp_pcb *pcb, unsigned char *challenge) {
+	LWIP_UNUSED_ARG(pcb);
+
+	*challenge++ = 16;
+#ifdef DEBUGMPPEKEY
+	if (mschap_challenge && strlen(mschap_challenge) == 16)
+		memcpy(challenge, mschap_challenge, 16);
+	else
+#endif
+		magic_random_bytes(challenge, 16);
+}
+
+static int chapms_verify_response(ppp_pcb *pcb, int id, const char *name,
+		       const unsigned char *secret, int secret_len,
+		       const unsigned char *challenge, const unsigned char *response,
+		       char *message, int message_space) {
+	unsigned char md[MS_CHAP_RESPONSE_LEN];
+	int diff;
+	int challenge_len, response_len;
+	LWIP_UNUSED_ARG(id);
+	LWIP_UNUSED_ARG(name);
+
+	challenge_len = *challenge++;	/* skip length, is 8 */
+	response_len = *response++;
+	if (response_len != MS_CHAP_RESPONSE_LEN)
+		goto bad;
+
+#ifndef MSLANMAN
+	if (!response[MS_CHAP_USENT]) {
+		/* Should really propagate this into the error packet. */
+		ppp_notice("Peer request for LANMAN auth not supported");
+		goto bad;
+	}
+#endif
+
+	/* Generate the expected response. */
+	ChapMS(pcb, (const u_char *)challenge, (const char *)secret, secret_len, md);
+
+#ifdef MSLANMAN
+	/* Determine which part of response to verify against */
+	if (!response[MS_CHAP_USENT])
+		diff = memcmp(&response[MS_CHAP_LANMANRESP],
+			      &md[MS_CHAP_LANMANRESP], MS_CHAP_LANMANRESP_LEN);
+	else
+#endif
+		diff = memcmp(&response[MS_CHAP_NTRESP], &md[MS_CHAP_NTRESP],
+			      MS_CHAP_NTRESP_LEN);
+
+	if (diff == 0) {
+		ppp_slprintf(message, message_space, "Access granted");
+		return 1;
+	}
+
+ bad:
+	/* See comments below for MS-CHAP V2 */
+	ppp_slprintf(message, message_space, "E=691 R=1 C=%0.*B V=0",
+		 challenge_len, challenge);
+	return 0;
+}
+
+static int chapms2_verify_response(ppp_pcb *pcb, int id, const char *name,
+			const unsigned char *secret, int secret_len,
+			const unsigned char *challenge, const unsigned char *response,
+			char *message, int message_space) {
+	unsigned char md[MS_CHAP2_RESPONSE_LEN];
+	char saresponse[MS_AUTH_RESPONSE_LENGTH+1];
+	int challenge_len, response_len;
+	LWIP_UNUSED_ARG(id);
+
+	challenge_len = *challenge++;	/* skip length, is 16 */
+	response_len = *response++;
+	if (response_len != MS_CHAP2_RESPONSE_LEN)
+		goto bad;	/* not even the right length */
+
+	/* Generate the expected response and our mutual auth. */
+	ChapMS2(pcb, (const u_char*)challenge, (const u_char*)&response[MS_CHAP2_PEER_CHALLENGE], name,
+		(const char *)secret, secret_len, md,
+		(unsigned char *)saresponse, MS_CHAP2_AUTHENTICATOR);
+
+	/* compare MDs and send the appropriate status */
+	/*
+	 * Per RFC 2759, success message must be formatted as
+	 *     "S=<auth_string> M=<message>"
+	 * where
+	 *     <auth_string> is the Authenticator Response (mutual auth)
+	 *     <message> is a text message
+	 *
+	 * However, some versions of Windows (win98 tested) do not know
+	 * about the M=<message> part (required per RFC 2759) and flag
+	 * it as an error (reported incorrectly as an encryption error
+	 * to the user).  Since the RFC requires it, and it can be
+	 * useful information, we supply it if the peer is a conforming
+	 * system.  Luckily (?), win98 sets the Flags field to 0x04
+	 * (contrary to RFC requirements) so we can use that to
+	 * distinguish between conforming and non-conforming systems.
+	 *
+	 * Special thanks to Alex Swiridov <say@real.kharkov.ua> for
+	 * help debugging this.
+	 */
+	if (memcmp(&md[MS_CHAP2_NTRESP], &response[MS_CHAP2_NTRESP],
+		   MS_CHAP2_NTRESP_LEN) == 0) {
+		if (response[MS_CHAP2_FLAGS])
+			ppp_slprintf(message, message_space, "S=%s", saresponse);
+		else
+			ppp_slprintf(message, message_space, "S=%s M=%s",
+				 saresponse, "Access granted");
+		return 1;
+	}
+
+ bad:
+	/*
+	 * Failure message must be formatted as
+	 *     "E=e R=r C=c V=v M=m"
+	 * where
+	 *     e = error code (we use 691, ERROR_AUTHENTICATION_FAILURE)
+	 *     r = retry (we use 1, ok to retry)
+	 *     c = challenge to use for next response, we reuse previous
+	 *     v = Change Password version supported, we use 0
+	 *     m = text message
+	 *
+	 * The M=m part is only for MS-CHAPv2.  Neither win2k nor
+	 * win98 (others untested) display the message to the user anyway.
+	 * They also both ignore the E=e code.
+	 *
+	 * Note that it's safe to reuse the same challenge as we don't
+	 * actually accept another response based on the error message
+	 * (and no clients try to resend a response anyway).
+	 *
+	 * Basically, this whole bit is useless code, even the small
+	 * implementation here is only because of overspecification.
+	 */
+	ppp_slprintf(message, message_space, "E=691 R=1 C=%0.*B V=0 M=%s",
+		 challenge_len, challenge, "Access denied");
+	return 0;
+}
+#endif /* PPP_SERVER */
+
+static void chapms_make_response(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
+		     const unsigned char *challenge, const char *secret, int secret_len,
+		     unsigned char *private_) {
+	LWIP_UNUSED_ARG(id);
+	LWIP_UNUSED_ARG(our_name);
+	LWIP_UNUSED_ARG(private_);
+	challenge++;	/* skip length, should be 8 */
+	*response++ = MS_CHAP_RESPONSE_LEN;
+	ChapMS(pcb, challenge, secret, secret_len, response);
+}
+
+static void chapms2_make_response(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
+		      const unsigned char *challenge, const char *secret, int secret_len,
+		      unsigned char *private_) {
+	LWIP_UNUSED_ARG(id);
+	challenge++;	/* skip length, should be 16 */
+	*response++ = MS_CHAP2_RESPONSE_LEN;
+	ChapMS2(pcb, challenge,
+#ifdef DEBUGMPPEKEY
+		mschap2_peer_challenge,
+#else
+		NULL,
+#endif
+		our_name, secret, secret_len, response, private_,
+		MS_CHAP2_AUTHENTICATEE);
+}
+
+static int chapms2_check_success(ppp_pcb *pcb, unsigned char *msg, int len, unsigned char *private_) {
+	LWIP_UNUSED_ARG(pcb);
+
+	if ((len < MS_AUTH_RESPONSE_LENGTH + 2) ||
+	    strncmp((char *)msg, "S=", 2) != 0) {
+		/* Packet does not start with "S=" */
+		ppp_error("MS-CHAPv2 Success packet is badly formed.");
+		return 0;
+	}
+	msg += 2;
+	len -= 2;
+	if (len < MS_AUTH_RESPONSE_LENGTH
+	    || memcmp(msg, private_, MS_AUTH_RESPONSE_LENGTH)) {
+		/* Authenticator Response did not match expected. */
+		ppp_error("MS-CHAPv2 mutual authentication failed.");
+		return 0;
+	}
+	/* Authenticator Response matches. */
+	msg += MS_AUTH_RESPONSE_LENGTH; /* Eat it */
+	len -= MS_AUTH_RESPONSE_LENGTH;
+	if ((len >= 3) && !strncmp((char *)msg, " M=", 3)) {
+		msg += 3; /* Eat the delimiter */
+	} else if (len) {
+		/* Packet has extra text which does not begin " M=" */
+		ppp_error("MS-CHAPv2 Success packet is badly formed.");
+		return 0;
+	}
+	return 1;
+}
+
+static void chapms_handle_failure(ppp_pcb *pcb, unsigned char *inp, int len) {
+	int err;
+	const char *p;
+	char msg[64];
+	LWIP_UNUSED_ARG(pcb);
+
+	/* We want a null-terminated string for strxxx(). */
+	len = LWIP_MIN(len, 63);
+	MEMCPY(msg, inp, len);
+	msg[len] = 0;
+	p = msg;
+
+	/*
+	 * Deal with MS-CHAP formatted failure messages; just print the
+	 * M=<message> part (if any).  For MS-CHAP we're not really supposed
+	 * to use M=<message>, but it shouldn't hurt.  See
+	 * chapms[2]_verify_response.
+	 */
+	if (!strncmp(p, "E=", 2))
+		err = strtol(p+2, NULL, 10); /* Remember the error code. */
+	else
+		goto print_msg; /* Message is badly formatted. */
+
+	if (len && ((p = strstr(p, " M=")) != NULL)) {
+		/* M=<message> field found. */
+		p += 3;
+	} else {
+		/* No M=<message>; use the error code. */
+		switch (err) {
+		case MS_CHAP_ERROR_RESTRICTED_LOGON_HOURS:
+			p = "E=646 Restricted logon hours";
+			break;
+
+		case MS_CHAP_ERROR_ACCT_DISABLED:
+			p = "E=647 Account disabled";
+			break;
+
+		case MS_CHAP_ERROR_PASSWD_EXPIRED:
+			p = "E=648 Password expired";
+			break;
+
+		case MS_CHAP_ERROR_NO_DIALIN_PERMISSION:
+			p = "E=649 No dialin permission";
+			break;
+
+		case MS_CHAP_ERROR_AUTHENTICATION_FAILURE:
+			p = "E=691 Authentication failure";
+			break;
+
+		case MS_CHAP_ERROR_CHANGING_PASSWORD:
+			/* Should never see this, we don't support Change Password. */
+			p = "E=709 Error changing password";
+			break;
+
+		default:
+			ppp_error("Unknown MS-CHAP authentication failure: %.*v",
+			      len, inp);
+			return;
+		}
+	}
+print_msg:
+	if (p != NULL)
+		ppp_error("MS-CHAP authentication failed: %v", p);
+}
+
+static void ChallengeResponse(const u_char *challenge,
+		  const u_char PasswordHash[MD4_SIGNATURE_SIZE],
+		  u_char response[24]) {
+    u_char    ZPasswordHash[21];
+    lwip_des_context des;
+    u_char des_key[8];
+
+    BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+    MEMCPY(ZPasswordHash, PasswordHash, MD4_SIGNATURE_SIZE);
+
+#if 0
+    dbglog("ChallengeResponse - ZPasswordHash %.*B",
+	   sizeof(ZPasswordHash), ZPasswordHash);
+#endif
+
+    pppcrypt_56_to_64_bit_key(ZPasswordHash + 0, des_key);
+    lwip_des_init(&des);
+    lwip_des_setkey_enc(&des, des_key);
+    lwip_des_crypt_ecb(&des, challenge, response +0);
+    lwip_des_free(&des);
+
+    pppcrypt_56_to_64_bit_key(ZPasswordHash + 7, des_key);
+    lwip_des_init(&des);
+    lwip_des_setkey_enc(&des, des_key);
+    lwip_des_crypt_ecb(&des, challenge, response +8);
+    lwip_des_free(&des);
+
+    pppcrypt_56_to_64_bit_key(ZPasswordHash + 14, des_key);
+    lwip_des_init(&des);
+    lwip_des_setkey_enc(&des, des_key);
+    lwip_des_crypt_ecb(&des, challenge, response +16);
+    lwip_des_free(&des);
+
+#if 0
+    dbglog("ChallengeResponse - response %.24B", response);
+#endif
+}
+
+static void ChallengeHash(const u_char PeerChallenge[16], const u_char *rchallenge,
+	      const char *username, u_char Challenge[8]) {
+    lwip_sha1_context	sha1Context;
+    u_char	sha1Hash[SHA1_SIGNATURE_SIZE];
+    const char	*user;
+
+    /* remove domain from "domain\username" */
+    if ((user = strrchr(username, '\\')) != NULL)
+	++user;
+    else
+	user = username;
+
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, PeerChallenge, 16);
+    lwip_sha1_update(&sha1Context, rchallenge, 16);
+    lwip_sha1_update(&sha1Context, (const unsigned char*)user, strlen(user));
+    lwip_sha1_finish(&sha1Context, sha1Hash);
+    lwip_sha1_free(&sha1Context);
+
+    MEMCPY(Challenge, sha1Hash, 8);
+}
+
+/*
+ * Convert the ASCII version of the password to Unicode.
+ * This implicitly supports 8-bit ISO8859/1 characters.
+ * This gives us the little-endian representation, which
+ * is assumed by all M$ CHAP RFCs.  (Unicode byte ordering
+ * is machine-dependent.)
+ */
+static void ascii2unicode(const char ascii[], int ascii_len, u_char unicode[]) {
+    int i;
+
+    BZERO(unicode, ascii_len * 2);
+    for (i = 0; i < ascii_len; i++)
+	unicode[i * 2] = (u_char) ascii[i];
+}
+
+static void NTPasswordHash(u_char *secret, int secret_len, u_char hash[MD4_SIGNATURE_SIZE]) {
+    lwip_md4_context		md4Context;
+
+    lwip_md4_init(&md4Context);
+    lwip_md4_starts(&md4Context);
+    lwip_md4_update(&md4Context, secret, secret_len);
+    lwip_md4_finish(&md4Context, hash);
+    lwip_md4_free(&md4Context);
+}
+
+static void ChapMS_NT(const u_char *rchallenge, const char *secret, int secret_len,
+	  u_char NTResponse[24]) {
+    u_char	unicodePassword[MAX_NT_PASSWORD * 2];
+    u_char	PasswordHash[MD4_SIGNATURE_SIZE];
+
+    /* Hash the Unicode version of the secret (== password). */
+    ascii2unicode(secret, secret_len, unicodePassword);
+    NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash);
+
+    ChallengeResponse(rchallenge, PasswordHash, NTResponse);
+}
+
+static void ChapMS2_NT(const u_char *rchallenge, const u_char PeerChallenge[16], const char *username,
+	   const char *secret, int secret_len, u_char NTResponse[24]) {
+    u_char	unicodePassword[MAX_NT_PASSWORD * 2];
+    u_char	PasswordHash[MD4_SIGNATURE_SIZE];
+    u_char	Challenge[8];
+
+    ChallengeHash(PeerChallenge, rchallenge, username, Challenge);
+
+    /* Hash the Unicode version of the secret (== password). */
+    ascii2unicode(secret, secret_len, unicodePassword);
+    NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash);
+
+    ChallengeResponse(Challenge, PasswordHash, NTResponse);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static void ChapMS_LANMan(u_char *rchallenge, char *secret, int secret_len,
+	      unsigned char *response) {
+    int			i;
+    u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+    u_char		PasswordHash[MD4_SIGNATURE_SIZE];
+    lwip_des_context des;
+    u_char des_key[8];
+
+    /* LANMan password is case insensitive */
+    BZERO(UcasePassword, sizeof(UcasePassword));
+    for (i = 0; i < secret_len; i++)
+       UcasePassword[i] = (u_char)toupper(secret[i]);
+
+    pppcrypt_56_to_64_bit_key(UcasePassword +0, des_key);
+    lwip_des_init(&des);
+    lwip_des_setkey_enc(&des, des_key);
+    lwip_des_crypt_ecb(&des, StdText, PasswordHash +0);
+    lwip_des_free(&des);
+
+    pppcrypt_56_to_64_bit_key(UcasePassword +7, des_key);
+    lwip_des_init(&des);
+    lwip_des_setkey_enc(&des, des_key);
+    lwip_des_crypt_ecb(&des, StdText, PasswordHash +8);
+    lwip_des_free(&des);
+
+    ChallengeResponse(rchallenge, PasswordHash, &response[MS_CHAP_LANMANRESP]);
+}
+#endif
+
+
+static void GenerateAuthenticatorResponse(const u_char PasswordHashHash[MD4_SIGNATURE_SIZE],
+			      u_char NTResponse[24], const u_char PeerChallenge[16],
+			      const u_char *rchallenge, const char *username,
+			      u_char authResponse[MS_AUTH_RESPONSE_LENGTH+1]) {
+    /*
+     * "Magic" constants used in response generation, from RFC 2759.
+     */
+    static const u_char Magic1[39] = /* "Magic server to client signing constant" */
+	{ 0x4D, 0x61, 0x67, 0x69, 0x63, 0x20, 0x73, 0x65, 0x72, 0x76,
+	  0x65, 0x72, 0x20, 0x74, 0x6F, 0x20, 0x63, 0x6C, 0x69, 0x65,
+	  0x6E, 0x74, 0x20, 0x73, 0x69, 0x67, 0x6E, 0x69, 0x6E, 0x67,
+	  0x20, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x61, 0x6E, 0x74 };
+    static const u_char Magic2[41] = /* "Pad to make it do more than one iteration" */
+	{ 0x50, 0x61, 0x64, 0x20, 0x74, 0x6F, 0x20, 0x6D, 0x61, 0x6B,
+	  0x65, 0x20, 0x69, 0x74, 0x20, 0x64, 0x6F, 0x20, 0x6D, 0x6F,
+	  0x72, 0x65, 0x20, 0x74, 0x68, 0x61, 0x6E, 0x20, 0x6F, 0x6E,
+	  0x65, 0x20, 0x69, 0x74, 0x65, 0x72, 0x61, 0x74, 0x69, 0x6F,
+	  0x6E };
+
+    int		i;
+    lwip_sha1_context	sha1Context;
+    u_char	Digest[SHA1_SIGNATURE_SIZE];
+    u_char	Challenge[8];
+
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE);
+    lwip_sha1_update(&sha1Context, NTResponse, 24);
+    lwip_sha1_update(&sha1Context, Magic1, sizeof(Magic1));
+    lwip_sha1_finish(&sha1Context, Digest);
+    lwip_sha1_free(&sha1Context);
+
+    ChallengeHash(PeerChallenge, rchallenge, username, Challenge);
+
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, Digest, sizeof(Digest));
+    lwip_sha1_update(&sha1Context, Challenge, sizeof(Challenge));
+    lwip_sha1_update(&sha1Context, Magic2, sizeof(Magic2));
+    lwip_sha1_finish(&sha1Context, Digest);
+    lwip_sha1_free(&sha1Context);
+
+    /* Convert to ASCII hex string. */
+    for (i = 0; i < LWIP_MAX((MS_AUTH_RESPONSE_LENGTH / 2), (int)sizeof(Digest)); i++)
+	sprintf((char *)&authResponse[i * 2], "%02X", Digest[i]);
+}
+
+
+static void GenerateAuthenticatorResponsePlain(
+		 const char *secret, int secret_len,
+		 u_char NTResponse[24], const u_char PeerChallenge[16],
+		 const u_char *rchallenge, const char *username,
+		 u_char authResponse[MS_AUTH_RESPONSE_LENGTH+1]) {
+    u_char	unicodePassword[MAX_NT_PASSWORD * 2];
+    u_char	PasswordHash[MD4_SIGNATURE_SIZE];
+    u_char	PasswordHashHash[MD4_SIGNATURE_SIZE];
+
+    /* Hash (x2) the Unicode version of the secret (== password). */
+    ascii2unicode(secret, secret_len, unicodePassword);
+    NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash);
+    NTPasswordHash(PasswordHash, sizeof(PasswordHash),
+		   PasswordHashHash);
+
+    GenerateAuthenticatorResponse(PasswordHashHash, NTResponse, PeerChallenge,
+				  rchallenge, username, authResponse);
+}
+
+
+#if MPPE_SUPPORT
+/*
+ * Set mppe_xxxx_key from MS-CHAP credentials. (see RFC 3079)
+ */
+static void Set_Start_Key(ppp_pcb *pcb, const u_char *rchallenge, const char *secret, int secret_len) {
+    u_char	unicodePassword[MAX_NT_PASSWORD * 2];
+    u_char	PasswordHash[MD4_SIGNATURE_SIZE];
+    u_char	PasswordHashHash[MD4_SIGNATURE_SIZE];
+    lwip_sha1_context	sha1Context;
+    u_char	Digest[SHA1_SIGNATURE_SIZE];	/* >= MPPE_MAX_KEY_LEN */
+
+    /* Hash (x2) the Unicode version of the secret (== password). */
+    ascii2unicode(secret, secret_len, unicodePassword);
+    NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash);
+    NTPasswordHash(PasswordHash, sizeof(PasswordHash), PasswordHashHash);
+
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE);
+    lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE);
+    lwip_sha1_update(&sha1Context, rchallenge, 8);
+    lwip_sha1_finish(&sha1Context, Digest);
+    lwip_sha1_free(&sha1Context);
+
+    /* Same key in both directions. */
+    mppe_set_key(pcb, &pcb->mppe_comp, Digest);
+    mppe_set_key(pcb, &pcb->mppe_decomp, Digest);
+
+    pcb->mppe_keys_set = 1;
+}
+
+/*
+ * Set mppe_xxxx_key from MS-CHAPv2 credentials. (see RFC 3079)
+ */
+static void SetMasterKeys(ppp_pcb *pcb, const char *secret, int secret_len, u_char NTResponse[24], int IsServer) {
+    u_char	unicodePassword[MAX_NT_PASSWORD * 2];
+    u_char	PasswordHash[MD4_SIGNATURE_SIZE];
+    u_char	PasswordHashHash[MD4_SIGNATURE_SIZE];
+    lwip_sha1_context	sha1Context;
+    u_char	MasterKey[SHA1_SIGNATURE_SIZE];	/* >= MPPE_MAX_KEY_LEN */
+    u_char	Digest[SHA1_SIGNATURE_SIZE];	/* >= MPPE_MAX_KEY_LEN */
+    const u_char *s;
+
+    /* "This is the MPPE Master Key" */
+    static const u_char Magic1[27] =
+	{ 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x74,
+	  0x68, 0x65, 0x20, 0x4d, 0x50, 0x50, 0x45, 0x20, 0x4d,
+	  0x61, 0x73, 0x74, 0x65, 0x72, 0x20, 0x4b, 0x65, 0x79 };
+    /* "On the client side, this is the send key; "
+       "on the server side, it is the receive key." */
+    static const u_char Magic2[84] =
+	{ 0x4f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6c, 0x69,
+	  0x65, 0x6e, 0x74, 0x20, 0x73, 0x69, 0x64, 0x65, 0x2c, 0x20,
+	  0x74, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x74, 0x68,
+	  0x65, 0x20, 0x73, 0x65, 0x6e, 0x64, 0x20, 0x6b, 0x65, 0x79,
+	  0x3b, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x73,
+	  0x65, 0x72, 0x76, 0x65, 0x72, 0x20, 0x73, 0x69, 0x64, 0x65,
+	  0x2c, 0x20, 0x69, 0x74, 0x20, 0x69, 0x73, 0x20, 0x74, 0x68,
+	  0x65, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x20,
+	  0x6b, 0x65, 0x79, 0x2e };
+    /* "On the client side, this is the receive key; "
+       "on the server side, it is the send key." */
+    static const u_char Magic3[84] =
+	{ 0x4f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6c, 0x69,
+	  0x65, 0x6e, 0x74, 0x20, 0x73, 0x69, 0x64, 0x65, 0x2c, 0x20,
+	  0x74, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x74, 0x68,
+	  0x65, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x20,
+	  0x6b, 0x65, 0x79, 0x3b, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68,
+	  0x65, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x20, 0x73,
+	  0x69, 0x64, 0x65, 0x2c, 0x20, 0x69, 0x74, 0x20, 0x69, 0x73,
+	  0x20, 0x74, 0x68, 0x65, 0x20, 0x73, 0x65, 0x6e, 0x64, 0x20,
+	  0x6b, 0x65, 0x79, 0x2e };
+
+    /* Hash (x2) the Unicode version of the secret (== password). */
+    ascii2unicode(secret, secret_len, unicodePassword);
+    NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash);
+    NTPasswordHash(PasswordHash, sizeof(PasswordHash), PasswordHashHash);
+
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE);
+    lwip_sha1_update(&sha1Context, NTResponse, 24);
+    lwip_sha1_update(&sha1Context, Magic1, sizeof(Magic1));
+    lwip_sha1_finish(&sha1Context, MasterKey);
+    lwip_sha1_free(&sha1Context);
+
+    /*
+     * generate send key
+     */
+    if (IsServer)
+	s = Magic3;
+    else
+	s = Magic2;
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, MasterKey, 16);
+    lwip_sha1_update(&sha1Context, mppe_sha1_pad1, SHA1_PAD_SIZE);
+    lwip_sha1_update(&sha1Context, s, 84);
+    lwip_sha1_update(&sha1Context, mppe_sha1_pad2, SHA1_PAD_SIZE);
+    lwip_sha1_finish(&sha1Context, Digest);
+    lwip_sha1_free(&sha1Context);
+
+    mppe_set_key(pcb, &pcb->mppe_comp, Digest);
+
+    /*
+     * generate recv key
+     */
+    if (IsServer)
+	s = Magic2;
+    else
+	s = Magic3;
+    lwip_sha1_init(&sha1Context);
+    lwip_sha1_starts(&sha1Context);
+    lwip_sha1_update(&sha1Context, MasterKey, 16);
+    lwip_sha1_update(&sha1Context, mppe_sha1_pad1, SHA1_PAD_SIZE);
+    lwip_sha1_update(&sha1Context, s, 84);
+    lwip_sha1_update(&sha1Context, mppe_sha1_pad2, SHA1_PAD_SIZE);
+    lwip_sha1_finish(&sha1Context, Digest);
+    lwip_sha1_free(&sha1Context);
+
+    mppe_set_key(pcb, &pcb->mppe_decomp, Digest);
+
+    pcb->mppe_keys_set = 1;
+}
+
+#endif /* MPPE_SUPPORT */
+
+
+static void ChapMS(ppp_pcb *pcb, const u_char *rchallenge, const char *secret, int secret_len,
+       unsigned char *response) {
+#if !MPPE_SUPPORT
+    LWIP_UNUSED_ARG(pcb);
+#endif /* !MPPE_SUPPORT */
+    BZERO(response, MS_CHAP_RESPONSE_LEN);
+
+    ChapMS_NT(rchallenge, secret, secret_len, &response[MS_CHAP_NTRESP]);
+
+#ifdef MSLANMAN
+    ChapMS_LANMan(rchallenge, secret, secret_len,
+		  &response[MS_CHAP_LANMANRESP]);
+
+    /* preferred method is set by option  */
+    response[MS_CHAP_USENT] = !ms_lanman;
+#else
+    response[MS_CHAP_USENT] = 1;
+#endif
+
+#if MPPE_SUPPORT
+    Set_Start_Key(pcb, rchallenge, secret, secret_len);
+#endif /* MPPE_SUPPORT */
+}
+
+
+/*
+ * If PeerChallenge is NULL, one is generated and the PeerChallenge
+ * field of response is filled in.  Call this way when generating a response.
+ * If PeerChallenge is supplied, it is copied into the PeerChallenge field.
+ * Call this way when verifying a response (or debugging).
+ * Do not call with PeerChallenge = response.
+ *
+ * The PeerChallenge field of response is then used for calculation of the
+ * Authenticator Response.
+ */
+static void ChapMS2(ppp_pcb *pcb, const u_char *rchallenge, const u_char *PeerChallenge,
+	const char *user, const char *secret, int secret_len, unsigned char *response,
+	u_char authResponse[], int authenticator) {
+    /* ARGSUSED */
+    LWIP_UNUSED_ARG(authenticator);
+#if !MPPE_SUPPORT
+    LWIP_UNUSED_ARG(pcb);
+#endif /* !MPPE_SUPPORT */
+
+    BZERO(response, MS_CHAP2_RESPONSE_LEN);
+
+    /* Generate the Peer-Challenge if requested, or copy it if supplied. */
+    if (!PeerChallenge)
+	magic_random_bytes(&response[MS_CHAP2_PEER_CHALLENGE], MS_CHAP2_PEER_CHAL_LEN);
+    else
+	MEMCPY(&response[MS_CHAP2_PEER_CHALLENGE], PeerChallenge,
+	      MS_CHAP2_PEER_CHAL_LEN);
+
+    /* Generate the NT-Response */
+    ChapMS2_NT(rchallenge, &response[MS_CHAP2_PEER_CHALLENGE], user,
+	       secret, secret_len, &response[MS_CHAP2_NTRESP]);
+
+    /* Generate the Authenticator Response. */
+    GenerateAuthenticatorResponsePlain(secret, secret_len,
+				       &response[MS_CHAP2_NTRESP],
+				       &response[MS_CHAP2_PEER_CHALLENGE],
+				       rchallenge, user, authResponse);
+
+#if MPPE_SUPPORT
+    SetMasterKeys(pcb, secret, secret_len,
+		  &response[MS_CHAP2_NTRESP], authenticator);
+#endif /* MPPE_SUPPORT */
+}
+
+#if 0 /* UNUSED */
+#if MPPE_SUPPORT
+/*
+ * Set MPPE options from plugins.
+ */
+void set_mppe_enc_types(int policy, int types) {
+    /* Early exit for unknown policies. */
+    if (policy != MPPE_ENC_POL_ENC_ALLOWED ||
+	policy != MPPE_ENC_POL_ENC_REQUIRED)
+	return;
+
+    /* Don't modify MPPE if it's optional and wasn't already configured. */
+    if (policy == MPPE_ENC_POL_ENC_ALLOWED && !ccp_wantoptions[0].mppe)
+	return;
+
+    /*
+     * Disable undesirable encryption types.  Note that we don't ENABLE
+     * any encryption types, to avoid overriding manual configuration.
+     */
+    switch(types) {
+	case MPPE_ENC_TYPES_RC4_40:
+	    ccp_wantoptions[0].mppe &= ~MPPE_OPT_128;	/* disable 128-bit */
+	    break;
+	case MPPE_ENC_TYPES_RC4_128:
+	    ccp_wantoptions[0].mppe &= ~MPPE_OPT_40;	/* disable 40-bit */
+	    break;
+	default:
+	    break;
+    }
+}
+#endif /* MPPE_SUPPORT */
+#endif /* UNUSED */
+
+const struct chap_digest_type chapms_digest = {
+	CHAP_MICROSOFT,		/* code */
+#if PPP_SERVER
+	chapms_generate_challenge,
+	chapms_verify_response,
+#endif /* PPP_SERVER */
+	chapms_make_response,
+	NULL,			/* check_success */
+	chapms_handle_failure,
+};
+
+const struct chap_digest_type chapms2_digest = {
+	CHAP_MICROSOFT_V2,	/* code */
+#if PPP_SERVER
+	chapms2_generate_challenge,
+	chapms2_verify_response,
+#endif /* PPP_SERVER */
+	chapms2_make_response,
+	chapms2_check_success,
+	chapms_handle_failure,
+};
+
+#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/demand.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/demand.c
new file mode 100644
index 000000000..26c6c30db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/demand.c
@@ -0,0 +1,465 @@
+/*
+ * demand.c - Support routines for demand-dialling.
+ *
+ * Copyright (c) 1996-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && DEMAND_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <netdb.h>
+#include <unistd.h>
+#include <syslog.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <sys/time.h>
+#include <sys/resource.h>
+#include <sys/stat.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#ifdef PPP_FILTER
+#include <pcap-bpf.h>
+#endif
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/ipcp.h"
+#include "netif/ppp/lcp.h"
+
+char *frame;
+int framelen;
+int framemax;
+int escape_flag;
+int flush_flag;
+int fcs;
+
+struct packet {
+    int length;
+    struct packet *next;
+    unsigned char data[1];
+};
+
+struct packet *pend_q;
+struct packet *pend_qtail;
+
+static int active_packet (unsigned char *, int);
+
+/*
+ * demand_conf - configure the interface for doing dial-on-demand.
+ */
+void
+demand_conf()
+{
+    int i;
+    const struct protent *protp;
+
+/*    framemax = lcp_allowoptions[0].mru;
+    if (framemax < PPP_MRU) */
+	framemax = PPP_MRU;
+    framemax += PPP_HDRLEN + PPP_FCSLEN;
+    frame = malloc(framemax);
+    if (frame == NULL)
+	novm("demand frame");
+    framelen = 0;
+    pend_q = NULL;
+    escape_flag = 0;
+    flush_flag = 0;
+    fcs = PPP_INITFCS;
+
+    netif_set_mtu(pcb, LWIP_MIN(lcp_allowoptions[0].mru, PPP_MRU));
+    if (ppp_send_config(pcb, PPP_MRU, (u32_t) 0, 0, 0) < 0
+	|| ppp_recv_config(pcb, PPP_MRU, (u32_t) 0, 0, 0) < 0)
+	    fatal("Couldn't set up demand-dialled PPP interface: %m");
+
+#ifdef PPP_FILTER
+    set_filters(&pass_filter, &active_filter);
+#endif
+
+    /*
+     * Call the demand_conf procedure for each protocol that's got one.
+     */
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (protp->demand_conf != NULL)
+	    ((*protp->demand_conf)(pcb));
+/* FIXME: find a way to die() here */
+#if 0
+	    if (!((*protp->demand_conf)(pcb)))
+		die(1);
+#endif
+}
+
+
+/*
+ * demand_block - set each network protocol to block further packets.
+ */
+void
+demand_block()
+{
+    int i;
+    const struct protent *protp;
+
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (protp->demand_conf != NULL)
+	    sifnpmode(pcb, protp->protocol & ~0x8000, NPMODE_QUEUE);
+    get_loop_output();
+}
+
+/*
+ * demand_discard - set each network protocol to discard packets
+ * with an error.
+ */
+void
+demand_discard()
+{
+    struct packet *pkt, *nextpkt;
+    int i;
+    const struct protent *protp;
+
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (protp->demand_conf != NULL)
+	    sifnpmode(pcb, protp->protocol & ~0x8000, NPMODE_ERROR);
+    get_loop_output();
+
+    /* discard all saved packets */
+    for (pkt = pend_q; pkt != NULL; pkt = nextpkt) {
+	nextpkt = pkt->next;
+	free(pkt);
+    }
+    pend_q = NULL;
+    framelen = 0;
+    flush_flag = 0;
+    escape_flag = 0;
+    fcs = PPP_INITFCS;
+}
+
+/*
+ * demand_unblock - set each enabled network protocol to pass packets.
+ */
+void
+demand_unblock()
+{
+    int i;
+    const struct protent *protp;
+
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (protp->demand_conf != NULL)
+	    sifnpmode(pcb, protp->protocol & ~0x8000, NPMODE_PASS);
+}
+
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static u_short fcstab[256] = {
+	0x0000,	0x1189,	0x2312,	0x329b,	0x4624,	0x57ad,	0x6536,	0x74bf,
+	0x8c48,	0x9dc1,	0xaf5a,	0xbed3,	0xca6c,	0xdbe5,	0xe97e,	0xf8f7,
+	0x1081,	0x0108,	0x3393,	0x221a,	0x56a5,	0x472c,	0x75b7,	0x643e,
+	0x9cc9,	0x8d40,	0xbfdb,	0xae52,	0xdaed,	0xcb64,	0xf9ff,	0xe876,
+	0x2102,	0x308b,	0x0210,	0x1399,	0x6726,	0x76af,	0x4434,	0x55bd,
+	0xad4a,	0xbcc3,	0x8e58,	0x9fd1,	0xeb6e,	0xfae7,	0xc87c,	0xd9f5,
+	0x3183,	0x200a,	0x1291,	0x0318,	0x77a7,	0x662e,	0x54b5,	0x453c,
+	0xbdcb,	0xac42,	0x9ed9,	0x8f50,	0xfbef,	0xea66,	0xd8fd,	0xc974,
+	0x4204,	0x538d,	0x6116,	0x709f,	0x0420,	0x15a9,	0x2732,	0x36bb,
+	0xce4c,	0xdfc5,	0xed5e,	0xfcd7,	0x8868,	0x99e1,	0xab7a,	0xbaf3,
+	0x5285,	0x430c,	0x7197,	0x601e,	0x14a1,	0x0528,	0x37b3,	0x263a,
+	0xdecd,	0xcf44,	0xfddf,	0xec56,	0x98e9,	0x8960,	0xbbfb,	0xaa72,
+	0x6306,	0x728f,	0x4014,	0x519d,	0x2522,	0x34ab,	0x0630,	0x17b9,
+	0xef4e,	0xfec7,	0xcc5c,	0xddd5,	0xa96a,	0xb8e3,	0x8a78,	0x9bf1,
+	0x7387,	0x620e,	0x5095,	0x411c,	0x35a3,	0x242a,	0x16b1,	0x0738,
+	0xffcf,	0xee46,	0xdcdd,	0xcd54,	0xb9eb,	0xa862,	0x9af9,	0x8b70,
+	0x8408,	0x9581,	0xa71a,	0xb693,	0xc22c,	0xd3a5,	0xe13e,	0xf0b7,
+	0x0840,	0x19c9,	0x2b52,	0x3adb,	0x4e64,	0x5fed,	0x6d76,	0x7cff,
+	0x9489,	0x8500,	0xb79b,	0xa612,	0xd2ad,	0xc324,	0xf1bf,	0xe036,
+	0x18c1,	0x0948,	0x3bd3,	0x2a5a,	0x5ee5,	0x4f6c,	0x7df7,	0x6c7e,
+	0xa50a,	0xb483,	0x8618,	0x9791,	0xe32e,	0xf2a7,	0xc03c,	0xd1b5,
+	0x2942,	0x38cb,	0x0a50,	0x1bd9,	0x6f66,	0x7eef,	0x4c74,	0x5dfd,
+	0xb58b,	0xa402,	0x9699,	0x8710,	0xf3af,	0xe226,	0xd0bd,	0xc134,
+	0x39c3,	0x284a,	0x1ad1,	0x0b58,	0x7fe7,	0x6e6e,	0x5cf5,	0x4d7c,
+	0xc60c,	0xd785,	0xe51e,	0xf497,	0x8028,	0x91a1,	0xa33a,	0xb2b3,
+	0x4a44,	0x5bcd,	0x6956,	0x78df,	0x0c60,	0x1de9,	0x2f72,	0x3efb,
+	0xd68d,	0xc704,	0xf59f,	0xe416,	0x90a9,	0x8120,	0xb3bb,	0xa232,
+	0x5ac5,	0x4b4c,	0x79d7,	0x685e,	0x1ce1,	0x0d68,	0x3ff3,	0x2e7a,
+	0xe70e,	0xf687,	0xc41c,	0xd595,	0xa12a,	0xb0a3,	0x8238,	0x93b1,
+	0x6b46,	0x7acf,	0x4854,	0x59dd,	0x2d62,	0x3ceb,	0x0e70,	0x1ff9,
+	0xf78f,	0xe606,	0xd49d,	0xc514,	0xb1ab,	0xa022,	0x92b9,	0x8330,
+	0x7bc7,	0x6a4e,	0x58d5,	0x495c,	0x3de3,	0x2c6a,	0x1ef1,	0x0f78
+};
+
+/*
+ * loop_chars - process characters received from the loopback.
+ * Calls loop_frame when a complete frame has been accumulated.
+ * Return value is 1 if we need to bring up the link, 0 otherwise.
+ */
+int
+loop_chars(p, n)
+    unsigned char *p;
+    int n;
+{
+    int c, rv;
+
+    rv = 0;
+
+/* check for synchronous connection... */
+
+    if ( (p[0] == 0xFF) && (p[1] == 0x03) ) {
+        rv = loop_frame(p,n);
+        return rv;
+    }
+
+    for (; n > 0; --n) {
+	c = *p++;
+	if (c == PPP_FLAG) {
+	    if (!escape_flag && !flush_flag
+		&& framelen > 2 && fcs == PPP_GOODFCS) {
+		framelen -= 2;
+		if (loop_frame((unsigned char *)frame, framelen))
+		    rv = 1;
+	    }
+	    framelen = 0;
+	    flush_flag = 0;
+	    escape_flag = 0;
+	    fcs = PPP_INITFCS;
+	    continue;
+	}
+	if (flush_flag)
+	    continue;
+	if (escape_flag) {
+	    c ^= PPP_TRANS;
+	    escape_flag = 0;
+	} else if (c == PPP_ESCAPE) {
+	    escape_flag = 1;
+	    continue;
+	}
+	if (framelen >= framemax) {
+	    flush_flag = 1;
+	    continue;
+	}
+	frame[framelen++] = c;
+	fcs = PPP_FCS(fcs, c);
+    }
+    return rv;
+}
+
+/*
+ * loop_frame - given a frame obtained from the loopback,
+ * decide whether to bring up the link or not, and, if we want
+ * to transmit this frame later, put it on the pending queue.
+ * Return value is 1 if we need to bring up the link, 0 otherwise.
+ * We assume that the kernel driver has already applied the
+ * pass_filter, so we won't get packets it rejected.
+ * We apply the active_filter to see if we want this packet to
+ * bring up the link.
+ */
+int
+loop_frame(frame, len)
+    unsigned char *frame;
+    int len;
+{
+    struct packet *pkt;
+
+    /* dbglog("from loop: %P", frame, len); */
+    if (len < PPP_HDRLEN)
+	return 0;
+    if ((PPP_PROTOCOL(frame) & 0x8000) != 0)
+	return 0;		/* shouldn't get any of these anyway */
+    if (!active_packet(frame, len))
+	return 0;
+
+    pkt = (struct packet *) malloc(sizeof(struct packet) + len);
+    if (pkt != NULL) {
+	pkt->length = len;
+	pkt->next = NULL;
+	memcpy(pkt->data, frame, len);
+	if (pend_q == NULL)
+	    pend_q = pkt;
+	else
+	    pend_qtail->next = pkt;
+	pend_qtail = pkt;
+    }
+    return 1;
+}
+
+/*
+ * demand_rexmit - Resend all those frames which we got via the
+ * loopback, now that the real serial link is up.
+ */
+void
+demand_rexmit(proto, newip)
+    int proto;
+    u32_t newip;
+{
+    struct packet *pkt, *prev, *nextpkt;
+    unsigned short checksum;
+    unsigned short pkt_checksum = 0;
+    unsigned iphdr;
+    struct timeval tv;
+    char cv = 0;
+    char ipstr[16];
+
+    prev = NULL;
+    pkt = pend_q;
+    pend_q = NULL;
+    tv.tv_sec = 1;
+    tv.tv_usec = 0;
+    select(0,NULL,NULL,NULL,&tv);	/* Sleep for 1 Seconds */
+    for (; pkt != NULL; pkt = nextpkt) {
+	nextpkt = pkt->next;
+	if (PPP_PROTOCOL(pkt->data) == proto) {
+            if ( (proto == PPP_IP) && newip ) {
+		/* Get old checksum */
+
+		iphdr = (pkt->data[4] & 15) << 2;
+		checksum = *((unsigned short *) (pkt->data+14));
+                if (checksum == 0xFFFF) {
+                    checksum = 0;
+                }
+
+ 
+                if (pkt->data[13] == 17) {
+                    pkt_checksum =  *((unsigned short *) (pkt->data+10+iphdr));
+		    if (pkt_checksum) {
+                        cv = 1;
+                        if (pkt_checksum == 0xFFFF) {
+                            pkt_checksum = 0;
+                        }
+                    }
+                    else {
+                       cv = 0;
+                    }
+                }
+
+		if (pkt->data[13] == 6) {
+		    pkt_checksum = *((unsigned short *) (pkt->data+20+iphdr));
+		    cv = 1;
+                    if (pkt_checksum == 0xFFFF) {
+                        pkt_checksum = 0;
+                    }
+		}
+
+		/* Delete old Source-IP-Address */
+                checksum -= *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;
+                checksum -= *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;
+
+		pkt_checksum -= *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;
+		pkt_checksum -= *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;
+
+		/* Change Source-IP-Address */
+                * ((u32_t *) (pkt->data + 16)) = newip;
+
+		/* Add new Source-IP-Address */
+                checksum += *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;
+                checksum += *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;
+
+                pkt_checksum += *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;
+                pkt_checksum += *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;
+
+		/* Write new checksum */
+                if (!checksum) {
+                    checksum = 0xFFFF;
+                }
+                *((unsigned short *) (pkt->data+14)) = checksum;
+		if (pkt->data[13] == 6) {
+		    *((unsigned short *) (pkt->data+20+iphdr)) = pkt_checksum;
+		}
+		if (cv && (pkt->data[13] == 17) ) {
+		    *((unsigned short *) (pkt->data+10+iphdr)) = pkt_checksum;
+		}
+
+		/* Log Packet */
+		strcpy(ipstr,inet_ntoa(*( (struct in_addr *) (pkt->data+16))));
+		if (pkt->data[13] == 1) {
+		    syslog(LOG_INFO,"Open ICMP %s -> %s\n",
+			ipstr,
+			inet_ntoa(*( (struct in_addr *) (pkt->data+20))));
+		} else {
+		    syslog(LOG_INFO,"Open %s %s:%d -> %s:%d\n",
+			pkt->data[13] == 6 ? "TCP" : "UDP",
+			ipstr,
+			ntohs(*( (short *) (pkt->data+iphdr+4))),
+			inet_ntoa(*( (struct in_addr *) (pkt->data+20))),
+			ntohs(*( (short *) (pkt->data+iphdr+6))));
+                }
+            }
+	    output(pcb, pkt->data, pkt->length);
+	    free(pkt);
+	} else {
+	    if (prev == NULL)
+		pend_q = pkt;
+	    else
+		prev->next = pkt;
+	    prev = pkt;
+	}
+    }
+    pend_qtail = prev;
+    if (prev != NULL)
+	prev->next = NULL;
+}
+
+/*
+ * Scan a packet to decide whether it is an "active" packet,
+ * that is, whether it is worth bringing up the link for.
+ */
+static int
+active_packet(p, len)
+    unsigned char *p;
+    int len;
+{
+    int proto, i;
+    const struct protent *protp;
+
+    if (len < PPP_HDRLEN)
+	return 0;
+    proto = PPP_PROTOCOL(p);
+#ifdef PPP_FILTER
+    p[0] = 1;		/* outbound packet indicator */
+    if ((pass_filter.bf_len != 0
+	 && bpf_filter(pass_filter.bf_insns, p, len, len) == 0)
+	|| (active_filter.bf_len != 0
+	    && bpf_filter(active_filter.bf_insns, p, len, len) == 0)) {
+	p[0] = 0xff;
+	return 0;
+    }
+    p[0] = 0xff;
+#endif
+    for (i = 0; (protp = protocols[i]) != NULL; ++i) {
+	if (protp->protocol < 0xC000 && (protp->protocol & ~0x8000) == proto) {
+	    if (protp->active_pkt == NULL)
+		return 1;
+	    return (*protp->active_pkt)(p, len);
+	}
+    }
+    return 0;			/* not a supported protocol !!?? */
+}
+
+#endif /* PPP_SUPPORT && DEMAND_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/eap.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/eap.c
new file mode 100644
index 000000000..8fb56368e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/eap.c
@@ -0,0 +1,2423 @@
+/*
+ * eap.c - Extensible Authentication Protocol for PPP (RFC 2284)
+ *
+ * Copyright (c) 2001 by Sun Microsystems, Inc.
+ * All rights reserved.
+ *
+ * Non-exclusive rights to redistribute, modify, translate, and use
+ * this software in source and binary forms, in whole or in part, is
+ * hereby granted, provided that the above copyright notice is
+ * duplicated in any source form, and that neither the name of the
+ * copyright holder nor the author is used to endorse or promote
+ * products derived from this software.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Original version by James Carlson
+ *
+ * This implementation of EAP supports MD5-Challenge and SRP-SHA1
+ * authentication styles.  Note that support of MD5-Challenge is a
+ * requirement of RFC 2284, and that it's essentially just a
+ * reimplementation of regular RFC 1994 CHAP using EAP messages.
+ *
+ * As an authenticator ("server"), there are multiple phases for each
+ * style.  In the first phase of each style, the unauthenticated peer
+ * name is queried using the EAP Identity request type.  If the
+ * "remotename" option is used, then this phase is skipped, because
+ * the peer's name is presumed to be known.
+ *
+ * For MD5-Challenge, there are two phases, and the second phase
+ * consists of sending the challenge itself and handling the
+ * associated response.
+ *
+ * For SRP-SHA1, there are four phases.  The second sends 's', 'N',
+ * and 'g'.  The reply contains 'A'.  The third sends 'B', and the
+ * reply contains 'M1'.  The forth sends the 'M2' value.
+ *
+ * As an authenticatee ("client"), there's just a single phase --
+ * responding to the queries generated by the peer.  EAP is an
+ * authenticator-driven protocol.
+ *
+ * Based on draft-ietf-pppext-eap-srp-03.txt.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && EAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/eap.h"
+#include "netif/ppp/magic.h"
+#include "netif/ppp/pppcrypt.h"
+
+#ifdef USE_SRP
+#include <t_pwd.h>
+#include <t_server.h>
+#include <t_client.h>
+#endif /* USE_SRP */
+
+#ifndef SHA_DIGESTSIZE
+#define	SHA_DIGESTSIZE 20
+#endif
+
+#ifdef USE_SRP
+static char *pn_secret = NULL;		/* Pseudonym generating secret */
+#endif
+
+#if PPP_OPTIONS
+/*
+ * Command-line options.
+ */
+static option_t eap_option_list[] = {
+    { "eap-restart", o_int, &eap_states[0].es_server.ea_timeout,
+      "Set retransmit timeout for EAP Requests (server)" },
+    { "eap-max-sreq", o_int, &eap_states[0].es_server.ea_maxrequests,
+      "Set max number of EAP Requests sent (server)" },
+    { "eap-timeout", o_int, &eap_states[0].es_client.ea_timeout,
+      "Set time limit for peer EAP authentication" },
+    { "eap-max-rreq", o_int, &eap_states[0].es_client.ea_maxrequests,
+      "Set max number of EAP Requests allows (client)" },
+    { "eap-interval", o_int, &eap_states[0].es_rechallenge,
+      "Set interval for EAP rechallenge" },
+#ifdef USE_SRP
+    { "srp-interval", o_int, &eap_states[0].es_lwrechallenge,
+      "Set interval for SRP lightweight rechallenge" },
+    { "srp-pn-secret", o_string, &pn_secret,
+      "Long term pseudonym generation secret" },
+    { "srp-use-pseudonym", o_bool, &eap_states[0].es_usepseudo,
+      "Use pseudonym if offered one by server", 1 },
+#endif
+    { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Protocol entry points.
+ */
+static void eap_init(ppp_pcb *pcb);
+static void eap_input(ppp_pcb *pcb, u_char *inp, int inlen);
+static void eap_protrej(ppp_pcb *pcb);
+static void eap_lowerup(ppp_pcb *pcb);
+static void eap_lowerdown(ppp_pcb *pcb);
+#if PRINTPKT_SUPPORT
+static int  eap_printpkt(const u_char *inp, int inlen,
+    void (*)(void *arg, const char *fmt, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+
+const struct protent eap_protent = {
+	PPP_EAP,		/* protocol number */
+	eap_init,		/* initialization procedure */
+	eap_input,		/* process a received packet */
+	eap_protrej,		/* process a received protocol-reject */
+	eap_lowerup,		/* lower layer has gone up */
+	eap_lowerdown,		/* lower layer has gone down */
+	NULL,			/* open the protocol */
+	NULL,			/* close the protocol */
+#if PRINTPKT_SUPPORT
+	eap_printpkt,		/* print a packet in readable form */
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+	NULL,			/* process a received data packet */
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+	"EAP",			/* text name of protocol */
+	NULL,			/* text name of corresponding data protocol */
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+	eap_option_list,	/* list of command-line options */
+	NULL,			/* check requested options; assign defaults */
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+	NULL,			/* configure interface for demand-dial */
+	NULL			/* say whether to bring up link for this pkt */
+#endif /* DEMAND_SUPPORT */
+};
+
+#ifdef USE_SRP
+/*
+ * A well-known 2048 bit modulus.
+ */
+static const u_char wkmodulus[] = {
+	0xAC, 0x6B, 0xDB, 0x41, 0x32, 0x4A, 0x9A, 0x9B,
+	0xF1, 0x66, 0xDE, 0x5E, 0x13, 0x89, 0x58, 0x2F,
+	0xAF, 0x72, 0xB6, 0x65, 0x19, 0x87, 0xEE, 0x07,
+	0xFC, 0x31, 0x92, 0x94, 0x3D, 0xB5, 0x60, 0x50,
+	0xA3, 0x73, 0x29, 0xCB, 0xB4, 0xA0, 0x99, 0xED,
+	0x81, 0x93, 0xE0, 0x75, 0x77, 0x67, 0xA1, 0x3D,
+	0xD5, 0x23, 0x12, 0xAB, 0x4B, 0x03, 0x31, 0x0D,
+	0xCD, 0x7F, 0x48, 0xA9, 0xDA, 0x04, 0xFD, 0x50,
+	0xE8, 0x08, 0x39, 0x69, 0xED, 0xB7, 0x67, 0xB0,
+	0xCF, 0x60, 0x95, 0x17, 0x9A, 0x16, 0x3A, 0xB3,
+	0x66, 0x1A, 0x05, 0xFB, 0xD5, 0xFA, 0xAA, 0xE8,
+	0x29, 0x18, 0xA9, 0x96, 0x2F, 0x0B, 0x93, 0xB8,
+	0x55, 0xF9, 0x79, 0x93, 0xEC, 0x97, 0x5E, 0xEA,
+	0xA8, 0x0D, 0x74, 0x0A, 0xDB, 0xF4, 0xFF, 0x74,
+	0x73, 0x59, 0xD0, 0x41, 0xD5, 0xC3, 0x3E, 0xA7,
+	0x1D, 0x28, 0x1E, 0x44, 0x6B, 0x14, 0x77, 0x3B,
+	0xCA, 0x97, 0xB4, 0x3A, 0x23, 0xFB, 0x80, 0x16,
+	0x76, 0xBD, 0x20, 0x7A, 0x43, 0x6C, 0x64, 0x81,
+	0xF1, 0xD2, 0xB9, 0x07, 0x87, 0x17, 0x46, 0x1A,
+	0x5B, 0x9D, 0x32, 0xE6, 0x88, 0xF8, 0x77, 0x48,
+	0x54, 0x45, 0x23, 0xB5, 0x24, 0xB0, 0xD5, 0x7D,
+	0x5E, 0xA7, 0x7A, 0x27, 0x75, 0xD2, 0xEC, 0xFA,
+	0x03, 0x2C, 0xFB, 0xDB, 0xF5, 0x2F, 0xB3, 0x78,
+	0x61, 0x60, 0x27, 0x90, 0x04, 0xE5, 0x7A, 0xE6,
+	0xAF, 0x87, 0x4E, 0x73, 0x03, 0xCE, 0x53, 0x29,
+	0x9C, 0xCC, 0x04, 0x1C, 0x7B, 0xC3, 0x08, 0xD8,
+	0x2A, 0x56, 0x98, 0xF3, 0xA8, 0xD0, 0xC3, 0x82,
+	0x71, 0xAE, 0x35, 0xF8, 0xE9, 0xDB, 0xFB, 0xB6,
+	0x94, 0xB5, 0xC8, 0x03, 0xD8, 0x9F, 0x7A, 0xE4,
+	0x35, 0xDE, 0x23, 0x6D, 0x52, 0x5F, 0x54, 0x75,
+	0x9B, 0x65, 0xE3, 0x72, 0xFC, 0xD6, 0x8E, 0xF2,
+	0x0F, 0xA7, 0x11, 0x1F, 0x9E, 0x4A, 0xFF, 0x73
+};
+#endif
+
+#if PPP_SERVER
+/* Local forward declarations. */
+static void eap_server_timeout(void *arg);
+#endif /* PPP_SERVER */
+
+/*
+ * Convert EAP state code to printable string for debug.
+ */
+static const char * eap_state_name(enum eap_state_code esc)
+{
+	static const char *state_names[] = { EAP_STATES };
+
+	return (state_names[(int)esc]);
+}
+
+/*
+ * eap_init - Initialize state for an EAP user.  This is currently
+ * called once by main() during start-up.
+ */
+static void eap_init(ppp_pcb *pcb) {
+
+	BZERO(&pcb->eap, sizeof(eap_state));
+#if PPP_SERVER
+	pcb->eap.es_server.ea_id = magic();
+#endif /* PPP_SERVER */
+}
+
+/*
+ * eap_client_timeout - Give up waiting for the peer to send any
+ * Request messages.
+ */
+static void eap_client_timeout(void *arg) {
+	ppp_pcb *pcb = (ppp_pcb*)arg;
+
+	if (!eap_client_active(pcb))
+		return;
+
+	ppp_error("EAP: timeout waiting for Request from peer");
+	auth_withpeer_fail(pcb, PPP_EAP);
+	pcb->eap.es_client.ea_state = eapBadAuth;
+}
+
+/*
+ * eap_authwithpeer - Authenticate to our peer (behave as client).
+ *
+ * Start client state and wait for requests.  This is called only
+ * after eap_lowerup.
+ */
+void eap_authwithpeer(ppp_pcb *pcb, const char *localname) {
+
+	if(NULL == localname)
+		return;
+
+	/* Save the peer name we're given */
+	pcb->eap.es_client.ea_name = localname;
+	pcb->eap.es_client.ea_namelen = strlen(localname);
+
+	pcb->eap.es_client.ea_state = eapListen;
+
+	/*
+	 * Start a timer so that if the other end just goes
+	 * silent, we don't sit here waiting forever.
+	 */
+	if (pcb->settings.eap_req_time > 0)
+		TIMEOUT(eap_client_timeout, pcb,
+		    pcb->settings.eap_req_time);
+}
+
+#if PPP_SERVER
+/*
+ * Format a standard EAP Failure message and send it to the peer.
+ * (Server operation)
+ */
+static void eap_send_failure(ppp_pcb *pcb) {
+	struct pbuf *p;
+	u_char *outp;
+
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + EAP_HEADERLEN), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (u_char*)p->payload;
+
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_FAILURE, outp);
+	pcb->eap.es_server.ea_id++;
+	PUTCHAR(pcb->eap.es_server.ea_id, outp);
+	PUTSHORT(EAP_HEADERLEN, outp);
+
+	ppp_write(pcb, p);
+
+	pcb->eap.es_server.ea_state = eapBadAuth;
+	auth_peer_fail(pcb, PPP_EAP);
+}
+
+/*
+ * Format a standard EAP Success message and send it to the peer.
+ * (Server operation)
+ */
+static void eap_send_success(ppp_pcb *pcb) {
+	struct pbuf *p;
+	u_char *outp;
+
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + EAP_HEADERLEN), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (u_char*)p->payload;
+    
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_SUCCESS, outp);
+	pcb->eap.es_server.ea_id++;
+	PUTCHAR(pcb->eap.es_server.ea_id, outp);
+	PUTSHORT(EAP_HEADERLEN, outp);
+
+	ppp_write(pcb, p);
+
+	auth_peer_success(pcb, PPP_EAP, 0,
+	    pcb->eap.es_server.ea_peer, pcb->eap.es_server.ea_peerlen);
+}
+#endif /* PPP_SERVER */
+
+#ifdef USE_SRP
+/*
+ * Set DES key according to pseudonym-generating secret and current
+ * date.
+ */
+static bool
+pncrypt_setkey(int timeoffs)
+{
+	struct tm *tp;
+	char tbuf[9];
+	SHA1_CTX ctxt;
+	u_char dig[SHA_DIGESTSIZE];
+	time_t reftime;
+
+	if (pn_secret == NULL)
+		return (0);
+	reftime = time(NULL) + timeoffs;
+	tp = localtime(&reftime);
+	SHA1Init(&ctxt);
+	SHA1Update(&ctxt, pn_secret, strlen(pn_secret));
+	strftime(tbuf, sizeof (tbuf), "%Y%m%d", tp);
+	SHA1Update(&ctxt, tbuf, strlen(tbuf));
+	SHA1Final(dig, &ctxt);
+	/* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */
+	return (DesSetkey(dig));
+}
+
+static char base64[] =
+"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
+
+struct b64state {
+	u32_t bs_bits;
+	int bs_offs;
+};
+
+static int
+b64enc(bs, inp, inlen, outp)
+struct b64state *bs;
+u_char *inp;
+int inlen;
+u_char *outp;
+{
+	int outlen = 0;
+
+	while (inlen > 0) {
+		bs->bs_bits = (bs->bs_bits << 8) | *inp++;
+		inlen--;
+		bs->bs_offs += 8;
+		if (bs->bs_offs >= 24) {
+			*outp++ = base64[(bs->bs_bits >> 18) & 0x3F];
+			*outp++ = base64[(bs->bs_bits >> 12) & 0x3F];
+			*outp++ = base64[(bs->bs_bits >> 6) & 0x3F];
+			*outp++ = base64[bs->bs_bits & 0x3F];
+			outlen += 4;
+			bs->bs_offs = 0;
+			bs->bs_bits = 0;
+		}
+	}
+	return (outlen);
+}
+
+static int
+b64flush(bs, outp)
+struct b64state *bs;
+u_char *outp;
+{
+	int outlen = 0;
+
+	if (bs->bs_offs == 8) {
+		*outp++ = base64[(bs->bs_bits >> 2) & 0x3F];
+		*outp++ = base64[(bs->bs_bits << 4) & 0x3F];
+		outlen = 2;
+	} else if (bs->bs_offs == 16) {
+		*outp++ = base64[(bs->bs_bits >> 10) & 0x3F];
+		*outp++ = base64[(bs->bs_bits >> 4) & 0x3F];
+		*outp++ = base64[(bs->bs_bits << 2) & 0x3F];
+		outlen = 3;
+	}
+	bs->bs_offs = 0;
+	bs->bs_bits = 0;
+	return (outlen);
+}
+
+static int
+b64dec(bs, inp, inlen, outp)
+struct b64state *bs;
+u_char *inp;
+int inlen;
+u_char *outp;
+{
+	int outlen = 0;
+	char *cp;
+
+	while (inlen > 0) {
+		if ((cp = strchr(base64, *inp++)) == NULL)
+			break;
+		bs->bs_bits = (bs->bs_bits << 6) | (cp - base64);
+		inlen--;
+		bs->bs_offs += 6;
+		if (bs->bs_offs >= 8) {
+			*outp++ = bs->bs_bits >> (bs->bs_offs - 8);
+			outlen++;
+			bs->bs_offs -= 8;
+		}
+	}
+	return (outlen);
+}
+#endif /* USE_SRP */
+
+#if PPP_SERVER
+/*
+ * Assume that current waiting server state is complete and figure
+ * next state to use based on available authentication data.  'status'
+ * indicates if there was an error in handling the last query.  It is
+ * 0 for success and non-zero for failure.
+ */
+static void eap_figure_next_state(ppp_pcb *pcb, int status) {
+#ifdef USE_SRP
+	unsigned char secbuf[MAXSECRETLEN], clear[8], *sp, *dp;
+	struct t_pw tpw;
+	struct t_confent *tce, mytce;
+	char *cp, *cp2;
+	struct t_server *ts;
+	int id, i, plen, toffs;
+	u_char vals[2];
+	struct b64state bs;
+#endif /* USE_SRP */
+
+	pcb->settings.eap_timeout_time = pcb->eap.es_savedtime;
+	switch (pcb->eap.es_server.ea_state) {
+	case eapBadAuth:
+		return;
+
+	case eapIdentify:
+#ifdef USE_SRP
+		/* Discard any previous session. */
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		if (ts != NULL) {
+			t_serverclose(ts);
+			pcb->eap.es_server.ea_session = NULL;
+			pcb->eap.es_server.ea_skey = NULL;
+		}
+#endif /* USE_SRP */
+		if (status != 0) {
+			pcb->eap.es_server.ea_state = eapBadAuth;
+			break;
+		}
+#ifdef USE_SRP
+		/* If we've got a pseudonym, try to decode to real name. */
+		if (pcb->eap.es_server.ea_peerlen > SRP_PSEUDO_LEN &&
+		    strncmp(pcb->eap.es_server.ea_peer, SRP_PSEUDO_ID,
+			SRP_PSEUDO_LEN) == 0 &&
+		    (pcb->eap.es_server.ea_peerlen - SRP_PSEUDO_LEN) * 3 / 4 <
+		    sizeof (secbuf)) {
+			BZERO(&bs, sizeof (bs));
+			plen = b64dec(&bs,
+			    pcb->eap.es_server.ea_peer + SRP_PSEUDO_LEN,
+			    pcb->eap.es_server.ea_peerlen - SRP_PSEUDO_LEN,
+			    secbuf);
+			toffs = 0;
+			for (i = 0; i < 5; i++) {
+				pncrypt_setkey(toffs);
+				toffs -= 86400;
+				/* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */
+				if (!DesDecrypt(secbuf, clear)) {
+					ppp_dbglog("no DES here; cannot decode "
+					    "pseudonym");
+					return;
+				}
+				id = *(unsigned char *)clear;
+				if (id + 1 <= plen && id + 9 > plen)
+					break;
+			}
+			if (plen % 8 == 0 && i < 5) {
+				/*
+				 * Note that this is always shorter than the
+				 * original stored string, so there's no need
+				 * to realloc.
+				 */
+				if ((i = plen = *(unsigned char *)clear) > 7)
+					i = 7;
+				pcb->eap.es_server.ea_peerlen = plen;
+				dp = (unsigned char *)pcb->eap.es_server.ea_peer;
+				MEMCPY(dp, clear + 1, i);
+				plen -= i;
+				dp += i;
+				sp = secbuf + 8;
+				while (plen > 0) {
+					/* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */
+					(void) DesDecrypt(sp, dp);
+					sp += 8;
+					dp += 8;
+					plen -= 8;
+				}
+				pcb->eap.es_server.ea_peer[
+					pcb->eap.es_server.ea_peerlen] = '\0';
+				ppp_dbglog("decoded pseudonym to \"%.*q\"",
+				    pcb->eap.es_server.ea_peerlen,
+				    pcb->eap.es_server.ea_peer);
+			} else {
+				ppp_dbglog("failed to decode real name");
+				/* Stay in eapIdentfy state; requery */
+				break;
+			}
+		}
+		/* Look up user in secrets database. */
+		if (get_srp_secret(pcb->eap.es_unit, pcb->eap.es_server.ea_peer,
+		    pcb->eap.es_server.ea_name, (char *)secbuf, 1) != 0) {
+			/* Set up default in case SRP entry is bad */
+			pcb->eap.es_server.ea_state = eapMD5Chall;
+			/* Get t_confent based on index in srp-secrets */
+			id = strtol((char *)secbuf, &cp, 10);
+			if (*cp++ != ':' || id < 0)
+				break;
+			if (id == 0) {
+				mytce.index = 0;
+				mytce.modulus.data = (u_char *)wkmodulus;
+				mytce.modulus.len = sizeof (wkmodulus);
+				mytce.generator.data = (u_char *)"\002";
+				mytce.generator.len = 1;
+				tce = &mytce;
+			} else if ((tce = gettcid(id)) != NULL) {
+				/*
+				 * Client will have to verify this modulus/
+				 * generator combination, and that will take
+				 * a while.  Lengthen the timeout here.
+				 */
+				if (pcb->settings.eap_timeout_time > 0 &&
+				    pcb->settings.eap_timeout_time < 30)
+					pcb->settings.eap_timeout_time = 30;
+			} else {
+				break;
+			}
+			if ((cp2 = strchr(cp, ':')) == NULL)
+				break;
+			*cp2++ = '\0';
+			tpw.pebuf.name = pcb->eap.es_server.ea_peer;
+			tpw.pebuf.password.len = t_fromb64((char *)tpw.pwbuf,
+			    cp);
+			tpw.pebuf.password.data = tpw.pwbuf;
+			tpw.pebuf.salt.len = t_fromb64((char *)tpw.saltbuf,
+			    cp2);
+			tpw.pebuf.salt.data = tpw.saltbuf;
+			if ((ts = t_serveropenraw(&tpw.pebuf, tce)) == NULL)
+				break;
+			pcb->eap.es_server.ea_session = (void *)ts;
+			pcb->eap.es_server.ea_state = eapSRP1;
+			vals[0] = pcb->eap.es_server.ea_id + 1;
+			vals[1] = EAPT_SRP;
+			t_serveraddexdata(ts, vals, 2);
+			/* Generate B; must call before t_servergetkey() */
+			t_servergenexp(ts);
+			break;
+		}
+#endif /* USE_SRP */
+		pcb->eap.es_server.ea_state = eapMD5Chall;
+		break;
+
+	case eapSRP1:
+#ifdef USE_SRP
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		if (ts != NULL && status != 0) {
+			t_serverclose(ts);
+			pcb->eap.es_server.ea_session = NULL;
+			pcb->eap.es_server.ea_skey = NULL;
+		}
+#endif /* USE_SRP */
+		if (status == 1) {
+			pcb->eap.es_server.ea_state = eapMD5Chall;
+		} else if (status != 0 || pcb->eap.es_server.ea_session == NULL) {
+			pcb->eap.es_server.ea_state = eapBadAuth;
+		} else {
+			pcb->eap.es_server.ea_state = eapSRP2;
+		}
+		break;
+
+	case eapSRP2:
+#ifdef USE_SRP
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		if (ts != NULL && status != 0) {
+			t_serverclose(ts);
+			pcb->eap.es_server.ea_session = NULL;
+			pcb->eap.es_server.ea_skey = NULL;
+		}
+#endif /* USE_SRP */
+		if (status != 0 || pcb->eap.es_server.ea_session == NULL) {
+			pcb->eap.es_server.ea_state = eapBadAuth;
+		} else {
+			pcb->eap.es_server.ea_state = eapSRP3;
+		}
+		break;
+
+	case eapSRP3:
+	case eapSRP4:
+#ifdef USE_SRP
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		if (ts != NULL && status != 0) {
+			t_serverclose(ts);
+			pcb->eap.es_server.ea_session = NULL;
+			pcb->eap.es_server.ea_skey = NULL;
+		}
+#endif /* USE_SRP */
+		if (status != 0 || pcb->eap.es_server.ea_session == NULL) {
+			pcb->eap.es_server.ea_state = eapBadAuth;
+		} else {
+			pcb->eap.es_server.ea_state = eapOpen;
+		}
+		break;
+
+	case eapMD5Chall:
+		if (status != 0) {
+			pcb->eap.es_server.ea_state = eapBadAuth;
+		} else {
+			pcb->eap.es_server.ea_state = eapOpen;
+		}
+		break;
+
+	default:
+		pcb->eap.es_server.ea_state = eapBadAuth;
+		break;
+	}
+	if (pcb->eap.es_server.ea_state == eapBadAuth)
+		eap_send_failure(pcb);
+}
+
+/*
+ * Format an EAP Request message and send it to the peer.  Message
+ * type depends on current state.  (Server operation)
+ */
+static void eap_send_request(ppp_pcb *pcb) {
+	struct pbuf *p;
+	u_char *outp;
+	u_char *lenloc;
+	int outlen;
+	int len;
+	const char *str;
+#ifdef USE_SRP
+	struct t_server *ts;
+	u_char clear[8], cipher[8], dig[SHA_DIGESTSIZE], *optr, *cp;
+	int i, j;
+	struct b64state b64;
+	SHA1_CTX ctxt;
+#endif /* USE_SRP */
+
+	/* Handle both initial auth and restart */
+	if (pcb->eap.es_server.ea_state < eapIdentify &&
+	    pcb->eap.es_server.ea_state != eapInitial) {
+		pcb->eap.es_server.ea_state = eapIdentify;
+#if PPP_REMOTENAME
+		if (pcb->settings.explicit_remote && pcb->remote_name) {
+			/*
+			 * If we already know the peer's
+			 * unauthenticated name, then there's no
+			 * reason to ask.  Go to next state instead.
+			 */
+			int len = (int)strlen(pcb->remote_name);
+			if (len > MAXNAMELEN) {
+				len = MAXNAMELEN;
+			}
+			MEMCPY(pcb->eap.es_server.ea_peer, pcb->remote_name, len);
+			pcb->eap.es_server.ea_peer[len] = '\0';
+			pcb->eap.es_server.ea_peerlen = len;
+			eap_figure_next_state(pcb, 0);
+		}
+#endif /* PPP_REMOTENAME */
+	}
+
+	if (pcb->settings.eap_max_transmits > 0 &&
+	    pcb->eap.es_server.ea_requests >= pcb->settings.eap_max_transmits) {
+		if (pcb->eap.es_server.ea_responses > 0)
+			ppp_error("EAP: too many Requests sent");
+		else
+			ppp_error("EAP: no response to Requests");
+		eap_send_failure(pcb);
+		return;
+	}
+
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_CTRL_PBUF_MAX_SIZE), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (u_char*)p->payload;
+    
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_REQUEST, outp);
+	PUTCHAR(pcb->eap.es_server.ea_id, outp);
+	lenloc = outp;
+	INCPTR(2, outp);
+
+	switch (pcb->eap.es_server.ea_state) {
+	case eapIdentify:
+		PUTCHAR(EAPT_IDENTITY, outp);
+		str = "Name";
+		len = strlen(str);
+		MEMCPY(outp, str, len);
+		INCPTR(len, outp);
+		break;
+
+	case eapMD5Chall:
+		PUTCHAR(EAPT_MD5CHAP, outp);
+		/*
+		 * pick a random challenge length between
+		 * EAP_MIN_CHALLENGE_LENGTH and EAP_MAX_CHALLENGE_LENGTH
+		 */
+		pcb->eap.es_challen = EAP_MIN_CHALLENGE_LENGTH +
+		    magic_pow(EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH);
+		PUTCHAR(pcb->eap.es_challen, outp);
+		magic_random_bytes(pcb->eap.es_challenge, pcb->eap.es_challen);
+		MEMCPY(outp, pcb->eap.es_challenge, pcb->eap.es_challen);
+		INCPTR(pcb->eap.es_challen, outp);
+		MEMCPY(outp, pcb->eap.es_server.ea_name, pcb->eap.es_server.ea_namelen);
+		INCPTR(pcb->eap.es_server.ea_namelen, outp);
+		break;
+
+#ifdef USE_SRP
+	case eapSRP1:
+		PUTCHAR(EAPT_SRP, outp);
+		PUTCHAR(EAPSRP_CHALLENGE, outp);
+
+		PUTCHAR(pcb->eap.es_server.ea_namelen, outp);
+		MEMCPY(outp, pcb->eap.es_server.ea_name, pcb->eap.es_server.ea_namelen);
+		INCPTR(pcb->eap.es_server.ea_namelen, outp);
+
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		assert(ts != NULL);
+		PUTCHAR(ts->s.len, outp);
+		MEMCPY(outp, ts->s.data, ts->s.len);
+		INCPTR(ts->s.len, outp);
+
+		if (ts->g.len == 1 && ts->g.data[0] == 2) {
+			PUTCHAR(0, outp);
+		} else {
+			PUTCHAR(ts->g.len, outp);
+			MEMCPY(outp, ts->g.data, ts->g.len);
+			INCPTR(ts->g.len, outp);
+		}
+
+		if (ts->n.len != sizeof (wkmodulus) ||
+		    BCMP(ts->n.data, wkmodulus, sizeof (wkmodulus)) != 0) {
+			MEMCPY(outp, ts->n.data, ts->n.len);
+			INCPTR(ts->n.len, outp);
+		}
+		break;
+
+	case eapSRP2:
+		PUTCHAR(EAPT_SRP, outp);
+		PUTCHAR(EAPSRP_SKEY, outp);
+
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		assert(ts != NULL);
+		MEMCPY(outp, ts->B.data, ts->B.len);
+		INCPTR(ts->B.len, outp);
+		break;
+
+	case eapSRP3:
+		PUTCHAR(EAPT_SRP, outp);
+		PUTCHAR(EAPSRP_SVALIDATOR, outp);
+		PUTLONG(SRPVAL_EBIT, outp);
+		ts = (struct t_server *)pcb->eap.es_server.ea_session;
+		assert(ts != NULL);
+		MEMCPY(outp, t_serverresponse(ts), SHA_DIGESTSIZE);
+		INCPTR(SHA_DIGESTSIZE, outp);
+
+		if (pncrypt_setkey(0)) {
+			/* Generate pseudonym */
+			optr = outp;
+			cp = (unsigned char *)pcb->eap.es_server.ea_peer;
+			if ((j = i = pcb->eap.es_server.ea_peerlen) > 7)
+				j = 7;
+			clear[0] = i;
+			MEMCPY(clear + 1, cp, j);
+			i -= j;
+			cp += j;
+			/* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */
+			if (!DesEncrypt(clear, cipher)) {
+				ppp_dbglog("no DES here; not generating pseudonym");
+				break;
+			}
+			BZERO(&b64, sizeof (b64));
+			outp++;		/* space for pseudonym length */
+			outp += b64enc(&b64, cipher, 8, outp);
+			while (i >= 8) {
+				/* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */
+				(void) DesEncrypt(cp, cipher);
+				outp += b64enc(&b64, cipher, 8, outp);
+				cp += 8;
+				i -= 8;
+			}
+			if (i > 0) {
+				MEMCPY(clear, cp, i);
+				cp += i;
+				magic_random_bytes(cp, 8-i);
+				/* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */
+				(void) DesEncrypt(clear, cipher);
+				outp += b64enc(&b64, cipher, 8, outp);
+			}
+			outp += b64flush(&b64, outp);
+
+			/* Set length and pad out to next 20 octet boundary */
+			i = outp - optr - 1;
+			*optr = i;
+			i %= SHA_DIGESTSIZE;
+			if (i != 0) {
+				magic_random_bytes(outp, SHA_DIGESTSIZE-i);
+				INCPTR(SHA_DIGESTSIZE-i, outp);
+			}
+
+			/* Obscure the pseudonym with SHA1 hash */
+			SHA1Init(&ctxt);
+			SHA1Update(&ctxt, &pcb->eap.es_server.ea_id, 1);
+			SHA1Update(&ctxt, pcb->eap.es_server.ea_skey,
+			    SESSION_KEY_LEN);
+			SHA1Update(&ctxt, pcb->eap.es_server.ea_peer,
+			    pcb->eap.es_server.ea_peerlen);
+			while (optr < outp) {
+				SHA1Final(dig, &ctxt);
+				cp = dig;
+				while (cp < dig + SHA_DIGESTSIZE)
+					*optr++ ^= *cp++;
+				SHA1Init(&ctxt);
+				SHA1Update(&ctxt, &pcb->eap.es_server.ea_id, 1);
+				SHA1Update(&ctxt, pcb->eap.es_server.ea_skey,
+				    SESSION_KEY_LEN);
+				SHA1Update(&ctxt, optr - SHA_DIGESTSIZE,
+				    SHA_DIGESTSIZE);
+			}
+		}
+		break;
+
+	case eapSRP4:
+		PUTCHAR(EAPT_SRP, outp);
+		PUTCHAR(EAPSRP_LWRECHALLENGE, outp);
+		pcb->eap.es_challen = EAP_MIN_CHALLENGE_LENGTH +
+		    magic_pow(EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH);
+		magic_random_bytes(pcb->eap.es_challenge, pcb->eap.es_challen);
+		MEMCPY(outp, pcb->eap.es_challenge, pcb->eap.es_challen);
+		INCPTR(pcb->eap.es_challen, outp);
+		break;
+#endif /* USE_SRP */
+
+	default:
+		return;
+	}
+
+	outlen = (outp - (unsigned char*)p->payload) - PPP_HDRLEN;
+	PUTSHORT(outlen, lenloc);
+
+	pbuf_realloc(p, outlen + PPP_HDRLEN);
+	ppp_write(pcb, p);
+
+	pcb->eap.es_server.ea_requests++;
+
+	if (pcb->settings.eap_timeout_time > 0)
+		TIMEOUT(eap_server_timeout, pcb, pcb->settings.eap_timeout_time);
+}
+
+/*
+ * eap_authpeer - Authenticate our peer (behave as server).
+ *
+ * Start server state and send first request.  This is called only
+ * after eap_lowerup.
+ */
+void eap_authpeer(ppp_pcb *pcb, const char *localname) {
+
+	/* Save the name we're given. */
+	pcb->eap.es_server.ea_name = localname;
+	pcb->eap.es_server.ea_namelen = strlen(localname);
+
+	pcb->eap.es_savedtime = pcb->settings.eap_timeout_time;
+
+	/* Lower layer up yet? */
+	if (pcb->eap.es_server.ea_state == eapInitial ||
+	    pcb->eap.es_server.ea_state == eapPending) {
+		pcb->eap.es_server.ea_state = eapPending;
+		return;
+	}
+
+	pcb->eap.es_server.ea_state = eapPending;
+
+	/* ID number not updated here intentionally; hashed into M1 */
+	eap_send_request(pcb);
+}
+
+/*
+ * eap_server_timeout - Retransmission timer for sending Requests
+ * expired.
+ */
+static void eap_server_timeout(void *arg) {
+	ppp_pcb *pcb = (ppp_pcb*)arg;
+
+	if (!eap_server_active(pcb))
+		return;
+
+	/* EAP ID number must not change on timeout. */
+	eap_send_request(pcb);
+}
+
+/*
+ * When it's time to send rechallenge the peer, this timeout is
+ * called.  Once the rechallenge is successful, the response handler
+ * will restart the timer.  If it fails, then the link is dropped.
+ */
+static void eap_rechallenge(void *arg) {
+	ppp_pcb *pcb = (ppp_pcb*)arg;
+
+	if (pcb->eap.es_server.ea_state != eapOpen &&
+	    pcb->eap.es_server.ea_state != eapSRP4)
+		return;
+
+	pcb->eap.es_server.ea_requests = 0;
+	pcb->eap.es_server.ea_state = eapIdentify;
+	eap_figure_next_state(pcb, 0);
+	pcb->eap.es_server.ea_id++;
+	eap_send_request(pcb);
+}
+
+static void srp_lwrechallenge(void *arg) {
+	ppp_pcb *pcb = (ppp_pcb*)arg;
+
+	if (pcb->eap.es_server.ea_state != eapOpen ||
+	    pcb->eap.es_server.ea_type != EAPT_SRP)
+		return;
+
+	pcb->eap.es_server.ea_requests = 0;
+	pcb->eap.es_server.ea_state = eapSRP4;
+	pcb->eap.es_server.ea_id++;
+	eap_send_request(pcb);
+}
+#endif /* PPP_SERVER */
+
+/*
+ * eap_lowerup - The lower layer is now up.
+ *
+ * This is called before either eap_authpeer or eap_authwithpeer.  See
+ * link_established() in auth.c.  All that's necessary here is to
+ * return to closed state so that those two routines will do the right
+ * thing.
+ */
+static void eap_lowerup(ppp_pcb *pcb) {
+	pcb->eap.es_client.ea_state = eapClosed;
+#if PPP_SERVER
+	pcb->eap.es_server.ea_state = eapClosed;
+#endif /* PPP_SERVER */
+}
+
+/*
+ * eap_lowerdown - The lower layer is now down.
+ *
+ * Cancel all timeouts and return to initial state.
+ */
+static void eap_lowerdown(ppp_pcb *pcb) {
+
+	if (eap_client_active(pcb) && pcb->settings.eap_req_time > 0) {
+		UNTIMEOUT(eap_client_timeout, pcb);
+	}
+#if PPP_SERVER
+	if (eap_server_active(pcb)) {
+		if (pcb->settings.eap_timeout_time > 0) {
+			UNTIMEOUT(eap_server_timeout, pcb);
+		}
+	} else {
+		if ((pcb->eap.es_server.ea_state == eapOpen ||
+		    pcb->eap.es_server.ea_state == eapSRP4) &&
+		    pcb->eap.es_rechallenge > 0) {
+			UNTIMEOUT(eap_rechallenge, (void *)pcb);
+		}
+		if (pcb->eap.es_server.ea_state == eapOpen &&
+		    pcb->eap.es_lwrechallenge > 0) {
+			UNTIMEOUT(srp_lwrechallenge, (void *)pcb);
+		}
+	}
+
+	pcb->eap.es_client.ea_state = pcb->eap.es_server.ea_state = eapInitial;
+	pcb->eap.es_client.ea_requests = pcb->eap.es_server.ea_requests = 0;
+#endif /* PPP_SERVER */
+}
+
+/*
+ * eap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  If it does, it represents authentication
+ * failure.
+ */
+static void eap_protrej(ppp_pcb *pcb) {
+
+	if (eap_client_active(pcb)) {
+		ppp_error("EAP authentication failed due to Protocol-Reject");
+		auth_withpeer_fail(pcb, PPP_EAP);
+	}
+#if PPP_SERVER
+	if (eap_server_active(pcb)) {
+		ppp_error("EAP authentication of peer failed on Protocol-Reject");
+		auth_peer_fail(pcb, PPP_EAP);
+	}
+#endif /* PPP_SERVER */
+	eap_lowerdown(pcb);
+}
+
+/*
+ * Format and send a regular EAP Response message.
+ */
+static void eap_send_response(ppp_pcb *pcb, u_char id, u_char typenum, const u_char *str, int lenstr) {
+	struct pbuf *p;
+	u_char *outp;
+	int msglen;
+
+	msglen = EAP_HEADERLEN + sizeof (u_char) + lenstr;
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (u_char*)p->payload;
+
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_RESPONSE, outp);
+	PUTCHAR(id, outp);
+	pcb->eap.es_client.ea_id = id;
+	PUTSHORT(msglen, outp);
+	PUTCHAR(typenum, outp);
+	if (lenstr > 0) {
+		MEMCPY(outp, str, lenstr);
+	}
+
+	ppp_write(pcb, p);
+}
+
+/*
+ * Format and send an MD5-Challenge EAP Response message.
+ */
+static void eap_chap_response(ppp_pcb *pcb, u_char id, u_char *hash, const char *name, int namelen) {
+	struct pbuf *p;
+	u_char *outp;
+	int msglen;
+
+	msglen = EAP_HEADERLEN + 2 * sizeof (u_char) + MD5_SIGNATURE_SIZE +
+	    namelen;
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (u_char*)p->payload;
+    
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_RESPONSE, outp);
+	PUTCHAR(id, outp);
+	pcb->eap.es_client.ea_id = id;
+	PUTSHORT(msglen, outp);
+	PUTCHAR(EAPT_MD5CHAP, outp);
+	PUTCHAR(MD5_SIGNATURE_SIZE, outp);
+	MEMCPY(outp, hash, MD5_SIGNATURE_SIZE);
+	INCPTR(MD5_SIGNATURE_SIZE, outp);
+	if (namelen > 0) {
+		MEMCPY(outp, name, namelen);
+	}
+
+	ppp_write(pcb, p);
+}
+
+#ifdef USE_SRP
+/*
+ * Format and send a SRP EAP Response message.
+ */
+static void
+eap_srp_response(esp, id, subtypenum, str, lenstr)
+eap_state *esp;
+u_char id;
+u_char subtypenum;
+u_char *str;
+int lenstr;
+{
+	ppp_pcb *pcb = &ppp_pcb_list[pcb->eap.es_unit];
+	struct pbuf *p;
+	u_char *outp;
+	int msglen;
+
+	msglen = EAP_HEADERLEN + 2 * sizeof (u_char) + lenstr;
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = p->payload;
+
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_RESPONSE, outp);
+	PUTCHAR(id, outp);
+	pcb->eap.es_client.ea_id = id;
+	PUTSHORT(msglen, outp);
+	PUTCHAR(EAPT_SRP, outp);
+	PUTCHAR(subtypenum, outp);
+	if (lenstr > 0) {
+		MEMCPY(outp, str, lenstr);
+	}
+
+	ppp_write(pcb, p);
+}
+
+/*
+ * Format and send a SRP EAP Client Validator Response message.
+ */
+static void
+eap_srpval_response(esp, id, flags, str)
+eap_state *esp;
+u_char id;
+u32_t flags;
+u_char *str;
+{
+	ppp_pcb *pcb = &ppp_pcb_list[pcb->eap.es_unit];
+	struct pbuf *p;
+	u_char *outp;
+	int msglen;
+
+	msglen = EAP_HEADERLEN + 2 * sizeof (u_char) + sizeof (u32_t) +
+	    SHA_DIGESTSIZE;
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = p->payload;
+
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_RESPONSE, outp);
+	PUTCHAR(id, outp);
+	pcb->eap.es_client.ea_id = id;
+	PUTSHORT(msglen, outp);
+	PUTCHAR(EAPT_SRP, outp);
+	PUTCHAR(EAPSRP_CVALIDATOR, outp);
+	PUTLONG(flags, outp);
+	MEMCPY(outp, str, SHA_DIGESTSIZE);
+
+	ppp_write(pcb, p);
+}
+#endif /* USE_SRP */
+
+static void eap_send_nak(ppp_pcb *pcb, u_char id, u_char type) {
+	struct pbuf *p;
+	u_char *outp;
+	int msglen;
+
+	msglen = EAP_HEADERLEN + 2 * sizeof (u_char);
+	p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE);
+	if(NULL == p)
+		return;
+	if(p->tot_len != p->len) {
+		pbuf_free(p);
+		return;
+	}
+
+	outp = (u_char*)p->payload;
+
+	MAKEHEADER(outp, PPP_EAP);
+
+	PUTCHAR(EAP_RESPONSE, outp);
+	PUTCHAR(id, outp);
+	pcb->eap.es_client.ea_id = id;
+	PUTSHORT(msglen, outp);
+	PUTCHAR(EAPT_NAK, outp);
+	PUTCHAR(type, outp);
+
+	ppp_write(pcb, p);
+}
+
+#ifdef USE_SRP
+static char *
+name_of_pn_file()
+{
+	char *user, *path, *file;
+	struct passwd *pw;
+	size_t pl;
+	static bool pnlogged = 0;
+
+	pw = getpwuid(getuid());
+	if (pw == NULL || (user = pw->pw_dir) == NULL || user[0] == 0) {
+		errno = EINVAL;
+		return (NULL);
+	}
+	file = _PATH_PSEUDONYM;
+	pl = strlen(user) + strlen(file) + 2;
+	path = malloc(pl);
+	if (path == NULL)
+		return (NULL);
+	(void) slprintf(path, pl, "%s/%s", user, file);
+	if (!pnlogged) {
+		ppp_dbglog("pseudonym file: %s", path);
+		pnlogged = 1;
+	}
+	return (path);
+}
+
+static int
+open_pn_file(modebits)
+mode_t modebits;
+{
+	char *path;
+	int fd, err;
+
+	if ((path = name_of_pn_file()) == NULL)
+		return (-1);
+	fd = open(path, modebits, S_IRUSR | S_IWUSR);
+	err = errno;
+	free(path);
+	errno = err;
+	return (fd);
+}
+
+static void
+remove_pn_file()
+{
+	char *path;
+
+	if ((path = name_of_pn_file()) != NULL) {
+		(void) unlink(path);
+		(void) free(path);
+	}
+}
+
+static void
+write_pseudonym(esp, inp, len, id)
+eap_state *esp;
+u_char *inp;
+int len, id;
+{
+	u_char val;
+	u_char *datp, *digp;
+	SHA1_CTX ctxt;
+	u_char dig[SHA_DIGESTSIZE];
+	int dsize, fd, olen = len;
+
+	/*
+	 * Do the decoding by working backwards.  This eliminates the need
+	 * to save the decoded output in a separate buffer.
+	 */
+	val = id;
+	while (len > 0) {
+		if ((dsize = len % SHA_DIGESTSIZE) == 0)
+			dsize = SHA_DIGESTSIZE;
+		len -= dsize;
+		datp = inp + len;
+		SHA1Init(&ctxt);
+		SHA1Update(&ctxt, &val, 1);
+		SHA1Update(&ctxt, pcb->eap.es_client.ea_skey, SESSION_KEY_LEN);
+		if (len > 0) {
+			SHA1Update(&ctxt, datp, SHA_DIGESTSIZE);
+		} else {
+			SHA1Update(&ctxt, pcb->eap.es_client.ea_name,
+			    pcb->eap.es_client.ea_namelen);
+		}
+		SHA1Final(dig, &ctxt);
+		for (digp = dig; digp < dig + SHA_DIGESTSIZE; digp++)
+			*datp++ ^= *digp;
+	}
+
+	/* Now check that the result is sane */
+	if (olen <= 0 || *inp + 1 > olen) {
+		ppp_dbglog("EAP: decoded pseudonym is unusable <%.*B>", olen, inp);
+		return;
+	}
+
+	/* Save it away */
+	fd = open_pn_file(O_WRONLY | O_CREAT | O_TRUNC);
+	if (fd < 0) {
+		ppp_dbglog("EAP: error saving pseudonym: %m");
+		return;
+	}
+	len = write(fd, inp + 1, *inp);
+	if (close(fd) != -1 && len == *inp) {
+		ppp_dbglog("EAP: saved pseudonym");
+		pcb->eap.es_usedpseudo = 0;
+	} else {
+		ppp_dbglog("EAP: failed to save pseudonym");
+		remove_pn_file();
+	}
+}
+#endif /* USE_SRP */
+
+/*
+ * eap_request - Receive EAP Request message (client mode).
+ */
+static void eap_request(ppp_pcb *pcb, u_char *inp, int id, int len) {
+	u_char typenum;
+	u_char vallen;
+	int secret_len;
+	char secret[MAXSECRETLEN];
+	char rhostname[MAXNAMELEN];
+	lwip_md5_context mdContext;
+	u_char hash[MD5_SIGNATURE_SIZE];
+#ifdef USE_SRP
+	struct t_client *tc;
+	struct t_num sval, gval, Nval, *Ap, Bval;
+	u_char vals[2];
+	SHA1_CTX ctxt;
+	u_char dig[SHA_DIGESTSIZE];
+	int fd;
+#endif /* USE_SRP */
+
+	/*
+	 * Note: we update es_client.ea_id *only if* a Response
+	 * message is being generated.  Otherwise, we leave it the
+	 * same for duplicate detection purposes.
+	 */
+
+	pcb->eap.es_client.ea_requests++;
+	if (pcb->settings.eap_allow_req != 0 &&
+	    pcb->eap.es_client.ea_requests > pcb->settings.eap_allow_req) {
+		ppp_info("EAP: received too many Request messages");
+		if (pcb->settings.eap_req_time > 0) {
+			UNTIMEOUT(eap_client_timeout, pcb);
+		}
+		auth_withpeer_fail(pcb, PPP_EAP);
+		return;
+	}
+
+	if (len <= 0) {
+		ppp_error("EAP: empty Request message discarded");
+		return;
+	}
+
+	GETCHAR(typenum, inp);
+	len--;
+
+	switch (typenum) {
+	case EAPT_IDENTITY:
+		if (len > 0)
+			ppp_info("EAP: Identity prompt \"%.*q\"", len, inp);
+#ifdef USE_SRP
+		if (pcb->eap.es_usepseudo &&
+		    (pcb->eap.es_usedpseudo == 0 ||
+			(pcb->eap.es_usedpseudo == 1 &&
+			    id == pcb->eap.es_client.ea_id))) {
+			pcb->eap.es_usedpseudo = 1;
+			/* Try to get a pseudonym */
+			if ((fd = open_pn_file(O_RDONLY)) >= 0) {
+				strcpy(rhostname, SRP_PSEUDO_ID);
+				len = read(fd, rhostname + SRP_PSEUDO_LEN,
+				    sizeof (rhostname) - SRP_PSEUDO_LEN);
+				/* XXX NAI unsupported */
+				if (len > 0) {
+					eap_send_response(pcb, id, typenum,
+					    rhostname, len + SRP_PSEUDO_LEN);
+				}
+				(void) close(fd);
+				if (len > 0)
+					break;
+			}
+		}
+		/* Stop using pseudonym now. */
+		if (pcb->eap.es_usepseudo && pcb->eap.es_usedpseudo != 2) {
+			remove_pn_file();
+			pcb->eap.es_usedpseudo = 2;
+		}
+#endif /* USE_SRP */
+		eap_send_response(pcb, id, typenum, (const u_char*)pcb->eap.es_client.ea_name,
+		    pcb->eap.es_client.ea_namelen);
+		break;
+
+	case EAPT_NOTIFICATION:
+		if (len > 0)
+			ppp_info("EAP: Notification \"%.*q\"", len, inp);
+		eap_send_response(pcb, id, typenum, NULL, 0);
+		break;
+
+	case EAPT_NAK:
+		/*
+		 * Avoid the temptation to send Response Nak in reply
+		 * to Request Nak here.  It can only lead to trouble.
+		 */
+		ppp_warn("EAP: unexpected Nak in Request; ignored");
+		/* Return because we're waiting for something real. */
+		return;
+
+	case EAPT_MD5CHAP:
+		if (len < 1) {
+			ppp_error("EAP: received MD5-Challenge with no data");
+			/* Bogus request; wait for something real. */
+			return;
+		}
+		GETCHAR(vallen, inp);
+		len--;
+		if (vallen < 8 || vallen > len) {
+			ppp_error("EAP: MD5-Challenge with bad length %d (8..%d)",
+			    vallen, len);
+			/* Try something better. */
+			eap_send_nak(pcb, id, EAPT_SRP);
+			break;
+		}
+
+		/* Not so likely to happen. */
+		if (vallen >= len + sizeof (rhostname)) {
+			ppp_dbglog("EAP: trimming really long peer name down");
+			MEMCPY(rhostname, inp + vallen, sizeof (rhostname) - 1);
+			rhostname[sizeof (rhostname) - 1] = '\0';
+		} else {
+			MEMCPY(rhostname, inp + vallen, len - vallen);
+			rhostname[len - vallen] = '\0';
+		}
+
+#if PPP_REMOTENAME
+		/* In case the remote doesn't give us his name. */
+		if (pcb->settings.explicit_remote ||
+		    (pcb->settings.remote_name[0] != '\0' && vallen == len))
+			strlcpy(rhostname, pcb->settings.remote_name, sizeof (rhostname));
+#endif /* PPP_REMOTENAME */
+
+		/*
+		 * Get the secret for authenticating ourselves with
+		 * the specified host.
+		 */
+		if (!get_secret(pcb, pcb->eap.es_client.ea_name,
+		    rhostname, secret, &secret_len, 0)) {
+			ppp_dbglog("EAP: no MD5 secret for auth to %q", rhostname);
+			eap_send_nak(pcb, id, EAPT_SRP);
+			break;
+		}
+		lwip_md5_init(&mdContext);
+		lwip_md5_starts(&mdContext);
+		typenum = id;
+		lwip_md5_update(&mdContext, &typenum, 1);
+		lwip_md5_update(&mdContext, (u_char *)secret, secret_len);
+		BZERO(secret, sizeof (secret));
+		lwip_md5_update(&mdContext, inp, vallen);
+		lwip_md5_finish(&mdContext, hash);
+		lwip_md5_free(&mdContext);
+		eap_chap_response(pcb, id, hash, pcb->eap.es_client.ea_name,
+		    pcb->eap.es_client.ea_namelen);
+		break;
+
+#ifdef USE_SRP
+	case EAPT_SRP:
+		if (len < 1) {
+			ppp_error("EAP: received empty SRP Request");
+			/* Bogus request; wait for something real. */
+			return;
+		}
+
+		/* Get subtype */
+		GETCHAR(vallen, inp);
+		len--;
+		switch (vallen) {
+		case EAPSRP_CHALLENGE:
+			tc = NULL;
+			if (pcb->eap.es_client.ea_session != NULL) {
+				tc = (struct t_client *)pcb->eap.es_client.
+				    ea_session;
+				/*
+				 * If this is a new challenge, then start
+				 * over with a new client session context.
+				 * Otherwise, just resend last response.
+				 */
+				if (id != pcb->eap.es_client.ea_id) {
+					t_clientclose(tc);
+					pcb->eap.es_client.ea_session = NULL;
+					tc = NULL;
+				}
+			}
+			/* No session key just yet */
+			pcb->eap.es_client.ea_skey = NULL;
+			if (tc == NULL) {
+				int rhostnamelen;
+
+				GETCHAR(vallen, inp);
+				len--;
+				if (vallen >= len) {
+					ppp_error("EAP: badly-formed SRP Challenge"
+					    " (name)");
+					/* Ignore badly-formed messages */
+					return;
+				}
+				MEMCPY(rhostname, inp, vallen);
+				rhostname[vallen] = '\0';
+				INCPTR(vallen, inp);
+				len -= vallen;
+
+				/*
+				 * In case the remote doesn't give us his name,
+				 * use configured name.
+				 */
+				if (explicit_remote ||
+				    (remote_name[0] != '\0' && vallen == 0)) {
+					strlcpy(rhostname, remote_name,
+					    sizeof (rhostname));
+				}
+
+				rhostnamelen = (int)strlen(rhostname);
+				if (rhostnamelen > MAXNAMELEN) {
+					rhostnamelen = MAXNAMELEN;
+				}
+				MEMCPY(pcb->eap.es_client.ea_peer, rhostname, rhostnamelen);
+				pcb->eap.es_client.ea_peer[rhostnamelen] = '\0';
+				pcb->eap.es_client.ea_peerlen = rhostnamelen;
+
+				GETCHAR(vallen, inp);
+				len--;
+				if (vallen >= len) {
+					ppp_error("EAP: badly-formed SRP Challenge"
+					    " (s)");
+					/* Ignore badly-formed messages */
+					return;
+				}
+				sval.data = inp;
+				sval.len = vallen;
+				INCPTR(vallen, inp);
+				len -= vallen;
+
+				GETCHAR(vallen, inp);
+				len--;
+				if (vallen > len) {
+					ppp_error("EAP: badly-formed SRP Challenge"
+					    " (g)");
+					/* Ignore badly-formed messages */
+					return;
+				}
+				/* If no generator present, then use value 2 */
+				if (vallen == 0) {
+					gval.data = (u_char *)"\002";
+					gval.len = 1;
+				} else {
+					gval.data = inp;
+					gval.len = vallen;
+				}
+				INCPTR(vallen, inp);
+				len -= vallen;
+
+				/*
+				 * If no modulus present, then use well-known
+				 * value.
+				 */
+				if (len == 0) {
+					Nval.data = (u_char *)wkmodulus;
+					Nval.len = sizeof (wkmodulus);
+				} else {
+					Nval.data = inp;
+					Nval.len = len;
+				}
+				tc = t_clientopen(pcb->eap.es_client.ea_name,
+				    &Nval, &gval, &sval);
+				if (tc == NULL) {
+					eap_send_nak(pcb, id, EAPT_MD5CHAP);
+					break;
+				}
+				pcb->eap.es_client.ea_session = (void *)tc;
+
+				/* Add Challenge ID & type to verifier */
+				vals[0] = id;
+				vals[1] = EAPT_SRP;
+				t_clientaddexdata(tc, vals, 2);
+			}
+			Ap = t_clientgenexp(tc);
+			eap_srp_response(esp, id, EAPSRP_CKEY, Ap->data,
+			    Ap->len);
+			break;
+
+		case EAPSRP_SKEY:
+			tc = (struct t_client *)pcb->eap.es_client.ea_session;
+			if (tc == NULL) {
+				ppp_warn("EAP: peer sent Subtype 2 without 1");
+				eap_send_nak(pcb, id, EAPT_MD5CHAP);
+				break;
+			}
+			if (pcb->eap.es_client.ea_skey != NULL) {
+				/*
+				 * ID number should not change here.  Warn
+				 * if it does (but otherwise ignore).
+				 */
+				if (id != pcb->eap.es_client.ea_id) {
+					ppp_warn("EAP: ID changed from %d to %d "
+					    "in SRP Subtype 2 rexmit",
+					    pcb->eap.es_client.ea_id, id);
+				}
+			} else {
+				if (get_srp_secret(pcb->eap.es_unit,
+				    pcb->eap.es_client.ea_name,
+				    pcb->eap.es_client.ea_peer, secret, 0) == 0) {
+					/*
+					 * Can't work with this peer because
+					 * the secret is missing.  Just give
+					 * up.
+					 */
+					eap_send_nak(pcb, id, EAPT_MD5CHAP);
+					break;
+				}
+				Bval.data = inp;
+				Bval.len = len;
+				t_clientpasswd(tc, secret);
+				BZERO(secret, sizeof (secret));
+				pcb->eap.es_client.ea_skey =
+				    t_clientgetkey(tc, &Bval);
+				if (pcb->eap.es_client.ea_skey == NULL) {
+					/* Server is rogue; stop now */
+					ppp_error("EAP: SRP server is rogue");
+					goto client_failure;
+				}
+			}
+			eap_srpval_response(esp, id, SRPVAL_EBIT,
+			    t_clientresponse(tc));
+			break;
+
+		case EAPSRP_SVALIDATOR:
+			tc = (struct t_client *)pcb->eap.es_client.ea_session;
+			if (tc == NULL || pcb->eap.es_client.ea_skey == NULL) {
+				ppp_warn("EAP: peer sent Subtype 3 without 1/2");
+				eap_send_nak(pcb, id, EAPT_MD5CHAP);
+				break;
+			}
+			/*
+			 * If we're already open, then this ought to be a
+			 * duplicate.  Otherwise, check that the server is
+			 * who we think it is.
+			 */
+			if (pcb->eap.es_client.ea_state == eapOpen) {
+				if (id != pcb->eap.es_client.ea_id) {
+					ppp_warn("EAP: ID changed from %d to %d "
+					    "in SRP Subtype 3 rexmit",
+					    pcb->eap.es_client.ea_id, id);
+				}
+			} else {
+				len -= sizeof (u32_t) + SHA_DIGESTSIZE;
+				if (len < 0 || t_clientverify(tc, inp +
+					sizeof (u32_t)) != 0) {
+					ppp_error("EAP: SRP server verification "
+					    "failed");
+					goto client_failure;
+				}
+				GETLONG(pcb->eap.es_client.ea_keyflags, inp);
+				/* Save pseudonym if user wants it. */
+				if (len > 0 && pcb->eap.es_usepseudo) {
+					INCPTR(SHA_DIGESTSIZE, inp);
+					write_pseudonym(esp, inp, len, id);
+				}
+			}
+			/*
+			 * We've verified our peer.  We're now mostly done,
+			 * except for waiting on the regular EAP Success
+			 * message.
+			 */
+			eap_srp_response(esp, id, EAPSRP_ACK, NULL, 0);
+			break;
+
+		case EAPSRP_LWRECHALLENGE:
+			if (len < 4) {
+				ppp_warn("EAP: malformed Lightweight rechallenge");
+				return;
+			}
+			SHA1Init(&ctxt);
+			vals[0] = id;
+			SHA1Update(&ctxt, vals, 1);
+			SHA1Update(&ctxt, pcb->eap.es_client.ea_skey,
+			    SESSION_KEY_LEN);
+			SHA1Update(&ctxt, inp, len);
+			SHA1Update(&ctxt, pcb->eap.es_client.ea_name,
+			    pcb->eap.es_client.ea_namelen);
+			SHA1Final(dig, &ctxt);
+			eap_srp_response(esp, id, EAPSRP_LWRECHALLENGE, dig,
+			    SHA_DIGESTSIZE);
+			break;
+
+		default:
+			ppp_error("EAP: unknown SRP Subtype %d", vallen);
+			eap_send_nak(pcb, id, EAPT_MD5CHAP);
+			break;
+		}
+		break;
+#endif /* USE_SRP */
+
+	default:
+		ppp_info("EAP: unknown authentication type %d; Naking", typenum);
+		eap_send_nak(pcb, id, EAPT_SRP);
+		break;
+	}
+
+	if (pcb->settings.eap_req_time > 0) {
+		UNTIMEOUT(eap_client_timeout, pcb);
+		TIMEOUT(eap_client_timeout, pcb,
+		    pcb->settings.eap_req_time);
+	}
+	return;
+
+#ifdef USE_SRP
+client_failure:
+	pcb->eap.es_client.ea_state = eapBadAuth;
+	if (pcb->settings.eap_req_time > 0) {
+		UNTIMEOUT(eap_client_timeout, (void *)esp);
+	}
+	pcb->eap.es_client.ea_session = NULL;
+	t_clientclose(tc);
+	auth_withpeer_fail(pcb, PPP_EAP);
+#endif /* USE_SRP */
+}
+
+#if PPP_SERVER
+/*
+ * eap_response - Receive EAP Response message (server mode).
+ */
+static void eap_response(ppp_pcb *pcb, u_char *inp, int id, int len) {
+	u_char typenum;
+	u_char vallen;
+	int secret_len;
+	char secret[MAXSECRETLEN];
+	char rhostname[MAXNAMELEN];
+	lwip_md5_context mdContext;
+	u_char hash[MD5_SIGNATURE_SIZE];
+#ifdef USE_SRP
+	struct t_server *ts;
+	struct t_num A;
+	SHA1_CTX ctxt;
+	u_char dig[SHA_DIGESTSIZE];
+#endif /* USE_SRP */
+
+	if (pcb->eap.es_server.ea_id != id) {
+		ppp_dbglog("EAP: discarding Response %d; expected ID %d", id,
+		    pcb->eap.es_server.ea_id);
+		return;
+	}
+
+	pcb->eap.es_server.ea_responses++;
+
+	if (len <= 0) {
+		ppp_error("EAP: empty Response message discarded");
+		return;
+	}
+
+	GETCHAR(typenum, inp);
+	len--;
+
+	switch (typenum) {
+	case EAPT_IDENTITY:
+		if (pcb->eap.es_server.ea_state != eapIdentify) {
+			ppp_dbglog("EAP discarding unwanted Identify \"%.q\"", len,
+			    inp);
+			break;
+		}
+		ppp_info("EAP: unauthenticated peer name \"%.*q\"", len, inp);
+		if (len > MAXNAMELEN) {
+		  len = MAXNAMELEN;
+		}
+		MEMCPY(pcb->eap.es_server.ea_peer, inp, len);
+		pcb->eap.es_server.ea_peer[len] = '\0';
+		pcb->eap.es_server.ea_peerlen = len;
+		eap_figure_next_state(pcb, 0);
+		break;
+
+	case EAPT_NOTIFICATION:
+		ppp_dbglog("EAP unexpected Notification; response discarded");
+		break;
+
+	case EAPT_NAK:
+		if (len < 1) {
+			ppp_info("EAP: Nak Response with no suggested protocol");
+			eap_figure_next_state(pcb, 1);
+			break;
+		}
+
+		GETCHAR(vallen, inp);
+		len--;
+
+		if (
+#if PPP_REMOTENAME
+		!pcb->explicit_remote &&
+#endif /* PPP_REMOTENAME */
+		pcb->eap.es_server.ea_state == eapIdentify){
+			/* Peer cannot Nak Identify Request */
+			eap_figure_next_state(pcb, 1);
+			break;
+		}
+
+		switch (vallen) {
+		case EAPT_SRP:
+			/* Run through SRP validator selection again. */
+			pcb->eap.es_server.ea_state = eapIdentify;
+			eap_figure_next_state(pcb, 0);
+			break;
+
+		case EAPT_MD5CHAP:
+			pcb->eap.es_server.ea_state = eapMD5Chall;
+			break;
+
+		default:
+			ppp_dbglog("EAP: peer requesting unknown Type %d", vallen);
+			switch (pcb->eap.es_server.ea_state) {
+			case eapSRP1:
+			case eapSRP2:
+			case eapSRP3:
+				pcb->eap.es_server.ea_state = eapMD5Chall;
+				break;
+			case eapMD5Chall:
+			case eapSRP4:
+				pcb->eap.es_server.ea_state = eapIdentify;
+				eap_figure_next_state(pcb, 0);
+				break;
+			default:
+				break;
+			}
+			break;
+		}
+		break;
+
+	case EAPT_MD5CHAP:
+		if (pcb->eap.es_server.ea_state != eapMD5Chall) {
+			ppp_error("EAP: unexpected MD5-Response");
+			eap_figure_next_state(pcb, 1);
+			break;
+		}
+		if (len < 1) {
+			ppp_error("EAP: received MD5-Response with no data");
+			eap_figure_next_state(pcb, 1);
+			break;
+		}
+		GETCHAR(vallen, inp);
+		len--;
+		if (vallen != 16 || vallen > len) {
+			ppp_error("EAP: MD5-Response with bad length %d", vallen);
+			eap_figure_next_state(pcb, 1);
+			break;
+		}
+
+		/* Not so likely to happen. */
+		if (vallen >= len + sizeof (rhostname)) {
+			ppp_dbglog("EAP: trimming really long peer name down");
+			MEMCPY(rhostname, inp + vallen, sizeof (rhostname) - 1);
+			rhostname[sizeof (rhostname) - 1] = '\0';
+		} else {
+			MEMCPY(rhostname, inp + vallen, len - vallen);
+			rhostname[len - vallen] = '\0';
+		}
+
+#if PPP_REMOTENAME
+		/* In case the remote doesn't give us his name. */
+		if (explicit_remote ||
+		    (remote_name[0] != '\0' && vallen == len))
+			strlcpy(rhostname, remote_name, sizeof (rhostname));
+#endif /* PPP_REMOTENAME */
+
+		/*
+		 * Get the secret for authenticating the specified
+		 * host.
+		 */
+		if (!get_secret(pcb, rhostname,
+		    pcb->eap.es_server.ea_name, secret, &secret_len, 1)) {
+			ppp_dbglog("EAP: no MD5 secret for auth of %q", rhostname);
+			eap_send_failure(pcb);
+			break;
+		}
+		lwip_md5_init(&mdContext);
+		lwip_md5_starts(&mdContext);
+		lwip_md5_update(&mdContext, &pcb->eap.es_server.ea_id, 1);
+		lwip_md5_update(&mdContext, (u_char *)secret, secret_len);
+		BZERO(secret, sizeof (secret));
+		lwip_md5_update(&mdContext, pcb->eap.es_challenge, pcb->eap.es_challen);
+		lwip_md5_finish(&mdContext, hash);
+		lwip_md5_free(&mdContext);
+		if (BCMP(hash, inp, MD5_SIGNATURE_SIZE) != 0) {
+			eap_send_failure(pcb);
+			break;
+		}
+		pcb->eap.es_server.ea_type = EAPT_MD5CHAP;
+		eap_send_success(pcb);
+		eap_figure_next_state(pcb, 0);
+		if (pcb->eap.es_rechallenge != 0)
+			TIMEOUT(eap_rechallenge, pcb, pcb->eap.es_rechallenge);
+		break;
+
+#ifdef USE_SRP
+	case EAPT_SRP:
+		if (len < 1) {
+			ppp_error("EAP: empty SRP Response");
+			eap_figure_next_state(pcb, 1);
+			break;
+		}
+		GETCHAR(typenum, inp);
+		len--;
+		switch (typenum) {
+		case EAPSRP_CKEY:
+			if (pcb->eap.es_server.ea_state != eapSRP1) {
+				ppp_error("EAP: unexpected SRP Subtype 1 Response");
+				eap_figure_next_state(pcb, 1);
+				break;
+			}
+			A.data = inp;
+			A.len = len;
+			ts = (struct t_server *)pcb->eap.es_server.ea_session;
+			assert(ts != NULL);
+			pcb->eap.es_server.ea_skey = t_servergetkey(ts, &A);
+			if (pcb->eap.es_server.ea_skey == NULL) {
+				/* Client's A value is bogus; terminate now */
+				ppp_error("EAP: bogus A value from client");
+				eap_send_failure(pcb);
+			} else {
+				eap_figure_next_state(pcb, 0);
+			}
+			break;
+
+		case EAPSRP_CVALIDATOR:
+			if (pcb->eap.es_server.ea_state != eapSRP2) {
+				ppp_error("EAP: unexpected SRP Subtype 2 Response");
+				eap_figure_next_state(pcb, 1);
+				break;
+			}
+			if (len < sizeof (u32_t) + SHA_DIGESTSIZE) {
+				ppp_error("EAP: M1 length %d < %d", len,
+				    sizeof (u32_t) + SHA_DIGESTSIZE);
+				eap_figure_next_state(pcb, 1);
+				break;
+			}
+			GETLONG(pcb->eap.es_server.ea_keyflags, inp);
+			ts = (struct t_server *)pcb->eap.es_server.ea_session;
+			assert(ts != NULL);
+			if (t_serververify(ts, inp)) {
+				ppp_info("EAP: unable to validate client identity");
+				eap_send_failure(pcb);
+				break;
+			}
+			eap_figure_next_state(pcb, 0);
+			break;
+
+		case EAPSRP_ACK:
+			if (pcb->eap.es_server.ea_state != eapSRP3) {
+				ppp_error("EAP: unexpected SRP Subtype 3 Response");
+				eap_send_failure(esp);
+				break;
+			}
+			pcb->eap.es_server.ea_type = EAPT_SRP;
+			eap_send_success(pcb, esp);
+			eap_figure_next_state(pcb, 0);
+			if (pcb->eap.es_rechallenge != 0)
+				TIMEOUT(eap_rechallenge, pcb,
+				    pcb->eap.es_rechallenge);
+			if (pcb->eap.es_lwrechallenge != 0)
+				TIMEOUT(srp_lwrechallenge, pcb,
+				    pcb->eap.es_lwrechallenge);
+			break;
+
+		case EAPSRP_LWRECHALLENGE:
+			if (pcb->eap.es_server.ea_state != eapSRP4) {
+				ppp_info("EAP: unexpected SRP Subtype 4 Response");
+				return;
+			}
+			if (len != SHA_DIGESTSIZE) {
+				ppp_error("EAP: bad Lightweight rechallenge "
+				    "response");
+				return;
+			}
+			SHA1Init(&ctxt);
+			vallen = id;
+			SHA1Update(&ctxt, &vallen, 1);
+			SHA1Update(&ctxt, pcb->eap.es_server.ea_skey,
+			    SESSION_KEY_LEN);
+			SHA1Update(&ctxt, pcb->eap.es_challenge, pcb->eap.es_challen);
+			SHA1Update(&ctxt, pcb->eap.es_server.ea_peer,
+			    pcb->eap.es_server.ea_peerlen);
+			SHA1Final(dig, &ctxt);
+			if (BCMP(dig, inp, SHA_DIGESTSIZE) != 0) {
+				ppp_error("EAP: failed Lightweight rechallenge");
+				eap_send_failure(pcb);
+				break;
+			}
+			pcb->eap.es_server.ea_state = eapOpen;
+			if (pcb->eap.es_lwrechallenge != 0)
+				TIMEOUT(srp_lwrechallenge, esp,
+				    pcb->eap.es_lwrechallenge);
+			break;
+		}
+		break;
+#endif /* USE_SRP */
+
+	default:
+		/* This can't happen. */
+		ppp_error("EAP: unknown Response type %d; ignored", typenum);
+		return;
+	}
+
+	if (pcb->settings.eap_timeout_time > 0) {
+		UNTIMEOUT(eap_server_timeout, pcb);
+	}
+
+	if (pcb->eap.es_server.ea_state != eapBadAuth &&
+	    pcb->eap.es_server.ea_state != eapOpen) {
+		pcb->eap.es_server.ea_id++;
+		eap_send_request(pcb);
+	}
+}
+#endif /* PPP_SERVER */
+
+/*
+ * eap_success - Receive EAP Success message (client mode).
+ */
+static void eap_success(ppp_pcb *pcb, u_char *inp, int id, int len) {
+	LWIP_UNUSED_ARG(id);
+
+	if (pcb->eap.es_client.ea_state != eapOpen && !eap_client_active(pcb)) {
+		ppp_dbglog("EAP unexpected success message in state %s (%d)",
+		    eap_state_name(pcb->eap.es_client.ea_state),
+		    pcb->eap.es_client.ea_state);
+		return;
+	}
+
+	if (pcb->settings.eap_req_time > 0) {
+		UNTIMEOUT(eap_client_timeout, pcb);
+	}
+
+	if (len > 0) {
+		/* This is odd.  The spec doesn't allow for this. */
+		PRINTMSG(inp, len);
+	}
+
+	pcb->eap.es_client.ea_state = eapOpen;
+	auth_withpeer_success(pcb, PPP_EAP, 0);
+}
+
+/*
+ * eap_failure - Receive EAP Failure message (client mode).
+ */
+static void eap_failure(ppp_pcb *pcb, u_char *inp, int id, int len) {
+	LWIP_UNUSED_ARG(id);
+
+	if (!eap_client_active(pcb)) {
+		ppp_dbglog("EAP unexpected failure message in state %s (%d)",
+		    eap_state_name(pcb->eap.es_client.ea_state),
+		    pcb->eap.es_client.ea_state);
+	}
+
+	if (pcb->settings.eap_req_time > 0) {
+		UNTIMEOUT(eap_client_timeout, pcb);
+	}
+
+	if (len > 0) {
+		/* This is odd.  The spec doesn't allow for this. */
+		PRINTMSG(inp, len);
+	}
+
+	pcb->eap.es_client.ea_state = eapBadAuth;
+
+	ppp_error("EAP: peer reports authentication failure");
+	auth_withpeer_fail(pcb, PPP_EAP);
+}
+
+/*
+ * eap_input - Handle received EAP message.
+ */
+static void eap_input(ppp_pcb *pcb, u_char *inp, int inlen) {
+	u_char code, id;
+	int len;
+
+	/*
+	 * Parse header (code, id and length).  If packet too short,
+	 * drop it.
+	 */
+	if (inlen < EAP_HEADERLEN) {
+		ppp_error("EAP: packet too short: %d < %d", inlen, EAP_HEADERLEN);
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < EAP_HEADERLEN || len > inlen) {
+		ppp_error("EAP: packet has illegal length field %d (%d..%d)", len,
+		    EAP_HEADERLEN, inlen);
+		return;
+	}
+	len -= EAP_HEADERLEN;
+
+	/* Dispatch based on message code */
+	switch (code) {
+	case EAP_REQUEST:
+		eap_request(pcb, inp, id, len);
+		break;
+
+#if PPP_SERVER
+	case EAP_RESPONSE:
+		eap_response(pcb, inp, id, len);
+		break;
+#endif /* PPP_SERVER */
+
+	case EAP_SUCCESS:
+		eap_success(pcb, inp, id, len);
+		break;
+
+	case EAP_FAILURE:
+		eap_failure(pcb, inp, id, len);
+		break;
+
+	default:				/* XXX Need code reject */
+		/* Note: it's not legal to send EAP Nak here. */
+		ppp_warn("EAP: unknown code %d received", code);
+		break;
+	}
+}
+
+#if PRINTPKT_SUPPORT
+/*
+ * eap_printpkt - print the contents of an EAP packet.
+ */
+static const char* const eap_codenames[] = {
+	"Request", "Response", "Success", "Failure"
+};
+
+static const char* const eap_typenames[] = {
+	"Identity", "Notification", "Nak", "MD5-Challenge",
+	"OTP", "Generic-Token", NULL, NULL,
+	"RSA", "DSS", "KEA", "KEA-Validate",
+	"TLS", "Defender", "Windows 2000", "Arcot",
+	"Cisco", "Nokia", "SRP"
+};
+
+static int eap_printpkt(const u_char *inp, int inlen, void (*printer) (void *, const char *, ...), void *arg) {
+	int code, id, len, rtype, vallen;
+	const u_char *pstart;
+	u32_t uval;
+
+	if (inlen < EAP_HEADERLEN)
+		return (0);
+	pstart = inp;
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < EAP_HEADERLEN || len > inlen)
+		return (0);
+
+	if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(eap_codenames))
+		printer(arg, " %s", eap_codenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= EAP_HEADERLEN;
+	switch (code) {
+	case EAP_REQUEST:
+		if (len < 1) {
+			printer(arg, " <missing type>");
+			break;
+		}
+		GETCHAR(rtype, inp);
+		len--;
+		if (rtype >= 1 && rtype <= (int)LWIP_ARRAYSIZE(eap_typenames))
+			printer(arg, " %s", eap_typenames[rtype-1]);
+		else
+			printer(arg, " type=0x%x", rtype);
+		switch (rtype) {
+		case EAPT_IDENTITY:
+		case EAPT_NOTIFICATION:
+			if (len > 0) {
+				printer(arg, " <Message ");
+				ppp_print_string(inp, len, printer, arg);
+				printer(arg, ">");
+				INCPTR(len, inp);
+				len = 0;
+			} else {
+				printer(arg, " <No message>");
+			}
+			break;
+
+		case EAPT_MD5CHAP:
+			if (len <= 0)
+				break;
+			GETCHAR(vallen, inp);
+			len--;
+			if (vallen > len)
+				goto truncated;
+			printer(arg, " <Value%.*B>", vallen, inp);
+			INCPTR(vallen, inp);
+			len -= vallen;
+			if (len > 0) {
+				printer(arg, " <Name ");
+				ppp_print_string(inp, len, printer, arg);
+				printer(arg, ">");
+				INCPTR(len, inp);
+				len = 0;
+			} else {
+				printer(arg, " <No name>");
+			}
+			break;
+
+		case EAPT_SRP:
+			if (len < 3)
+				goto truncated;
+			GETCHAR(vallen, inp);
+			len--;
+			printer(arg, "-%d", vallen);
+			switch (vallen) {
+			case EAPSRP_CHALLENGE:
+				GETCHAR(vallen, inp);
+				len--;
+				if (vallen >= len)
+					goto truncated;
+				if (vallen > 0) {
+					printer(arg, " <Name ");
+					ppp_print_string(inp, vallen, printer,
+					    arg);
+					printer(arg, ">");
+				} else {
+					printer(arg, " <No name>");
+				}
+				INCPTR(vallen, inp);
+				len -= vallen;
+				GETCHAR(vallen, inp);
+				len--;
+				if (vallen >= len)
+					goto truncated;
+				printer(arg, " <s%.*B>", vallen, inp);
+				INCPTR(vallen, inp);
+				len -= vallen;
+				GETCHAR(vallen, inp);
+				len--;
+				if (vallen > len)
+					goto truncated;
+				if (vallen == 0) {
+					printer(arg, " <Default g=2>");
+				} else {
+					printer(arg, " <g%.*B>", vallen, inp);
+				}
+				INCPTR(vallen, inp);
+				len -= vallen;
+				if (len == 0) {
+					printer(arg, " <Default N>");
+				} else {
+					printer(arg, " <N%.*B>", len, inp);
+					INCPTR(len, inp);
+					len = 0;
+				}
+				break;
+
+			case EAPSRP_SKEY:
+				printer(arg, " <B%.*B>", len, inp);
+				INCPTR(len, inp);
+				len = 0;
+				break;
+
+			case EAPSRP_SVALIDATOR:
+				if (len < (int)sizeof (u32_t))
+					break;
+				GETLONG(uval, inp);
+				len -= sizeof (u32_t);
+				if (uval & SRPVAL_EBIT) {
+					printer(arg, " E");
+					uval &= ~SRPVAL_EBIT;
+				}
+				if (uval != 0) {
+					printer(arg, " f<%X>", uval);
+				}
+				if ((vallen = len) > SHA_DIGESTSIZE)
+					vallen = SHA_DIGESTSIZE;
+				printer(arg, " <M2%.*B%s>", len, inp,
+				    len < SHA_DIGESTSIZE ? "?" : "");
+				INCPTR(vallen, inp);
+				len -= vallen;
+				if (len > 0) {
+					printer(arg, " <PN%.*B>", len, inp);
+					INCPTR(len, inp);
+					len = 0;
+				}
+				break;
+
+			case EAPSRP_LWRECHALLENGE:
+				printer(arg, " <Challenge%.*B>", len, inp);
+				INCPTR(len, inp);
+				len = 0;
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case EAP_RESPONSE:
+		if (len < 1)
+			break;
+		GETCHAR(rtype, inp);
+		len--;
+		if (rtype >= 1 && rtype <= (int)LWIP_ARRAYSIZE(eap_typenames))
+			printer(arg, " %s", eap_typenames[rtype-1]);
+		else
+			printer(arg, " type=0x%x", rtype);
+		switch (rtype) {
+		case EAPT_IDENTITY:
+			if (len > 0) {
+				printer(arg, " <Name ");
+				ppp_print_string(inp, len, printer, arg);
+				printer(arg, ">");
+				INCPTR(len, inp);
+				len = 0;
+			}
+			break;
+
+		case EAPT_NAK:
+			if (len <= 0) {
+				printer(arg, " <missing hint>");
+				break;
+			}
+			GETCHAR(rtype, inp);
+			len--;
+			printer(arg, " <Suggested-type %02X", rtype);
+			if (rtype >= 1 && rtype < (int)LWIP_ARRAYSIZE(eap_typenames))
+				printer(arg, " (%s)", eap_typenames[rtype-1]);
+			printer(arg, ">");
+			break;
+
+		case EAPT_MD5CHAP:
+			if (len <= 0) {
+				printer(arg, " <missing length>");
+				break;
+			}
+			GETCHAR(vallen, inp);
+			len--;
+			if (vallen > len)
+				goto truncated;
+			printer(arg, " <Value%.*B>", vallen, inp);
+			INCPTR(vallen, inp);
+			len -= vallen;
+			if (len > 0) {
+				printer(arg, " <Name ");
+				ppp_print_string(inp, len, printer, arg);
+				printer(arg, ">");
+				INCPTR(len, inp);
+				len = 0;
+			} else {
+				printer(arg, " <No name>");
+			}
+			break;
+
+		case EAPT_SRP:
+			if (len < 1)
+				goto truncated;
+			GETCHAR(vallen, inp);
+			len--;
+			printer(arg, "-%d", vallen);
+			switch (vallen) {
+			case EAPSRP_CKEY:
+				printer(arg, " <A%.*B>", len, inp);
+				INCPTR(len, inp);
+				len = 0;
+				break;
+
+			case EAPSRP_CVALIDATOR:
+				if (len < (int)sizeof (u32_t))
+					break;
+				GETLONG(uval, inp);
+				len -= sizeof (u32_t);
+				if (uval & SRPVAL_EBIT) {
+					printer(arg, " E");
+					uval &= ~SRPVAL_EBIT;
+				}
+				if (uval != 0) {
+					printer(arg, " f<%X>", uval);
+				}
+				printer(arg, " <M1%.*B%s>", len, inp,
+				    len == SHA_DIGESTSIZE ? "" : "?");
+				INCPTR(len, inp);
+				len = 0;
+				break;
+
+			case EAPSRP_ACK:
+				break;
+
+			case EAPSRP_LWRECHALLENGE:
+				printer(arg, " <Response%.*B%s>", len, inp,
+				    len == SHA_DIGESTSIZE ? "" : "?");
+				if ((vallen = len) > SHA_DIGESTSIZE)
+					vallen = SHA_DIGESTSIZE;
+				INCPTR(vallen, inp);
+				len -= vallen;
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case EAP_SUCCESS:	/* No payload expected for these! */
+	case EAP_FAILURE:
+	default:
+		break;
+
+	truncated:
+		printer(arg, " <truncated>");
+		break;
+	}
+
+	if (len > 8)
+		printer(arg, "%8B...", inp);
+	else if (len > 0)
+		printer(arg, "%.*B", len, inp);
+	INCPTR(len, inp);
+
+	return (inp - pstart);
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#endif /* PPP_SUPPORT && EAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ecp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ecp.c
new file mode 100644
index 000000000..4d84f6093
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ecp.c
@@ -0,0 +1,191 @@
+/*
+ * ecp.c - PPP Encryption Control Protocol.
+ *
+ * Copyright (c) 2002 Google, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * Derived from ccp.c, which is:
+ *
+ * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && ECP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#include <string.h>
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/ecp.h"
+
+#if PPP_OPTIONS
+static option_t ecp_option_list[] = {
+    { "noecp", o_bool, &ecp_protent.enabled_flag,
+      "Disable ECP negotiation" },
+    { "-ecp", o_bool, &ecp_protent.enabled_flag,
+      "Disable ECP negotiation", OPT_ALIAS },
+
+    { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ecp_init (int unit);
+/*
+static void ecp_open (int unit);
+static void ecp_close (int unit, char *);
+static void ecp_lowerup (int unit);
+static void ecp_lowerdown (int);
+static void ecp_input (int unit, u_char *pkt, int len);
+static void ecp_protrej (int unit);
+*/
+#if PRINTPKT_SUPPORT
+static int  ecp_printpkt (const u_char *pkt, int len,
+			      void (*printer) (void *, char *, ...),
+			      void *arg);
+#endif /* PRINTPKT_SUPPORT */
+/*
+static void ecp_datainput (int unit, u_char *pkt, int len);
+*/
+
+const struct protent ecp_protent = {
+    PPP_ECP,
+    ecp_init,
+    NULL, /* ecp_input, */
+    NULL, /* ecp_protrej, */
+    NULL, /* ecp_lowerup, */
+    NULL, /* ecp_lowerdown, */
+    NULL, /* ecp_open, */
+    NULL, /* ecp_close, */
+#if PRINTPKT_SUPPORT
+    ecp_printpkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    NULL, /* ecp_datainput, */
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    "ECP",
+    "Encrypted",
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    ecp_option_list,
+    NULL,
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    NULL,
+    NULL
+#endif /* DEMAND_SUPPORT */
+};
+
+fsm ecp_fsm[NUM_PPP];
+ecp_options ecp_wantoptions[NUM_PPP];	/* what to request the peer to use */
+ecp_options ecp_gotoptions[NUM_PPP];	/* what the peer agreed to do */
+ecp_options ecp_allowoptions[NUM_PPP];	/* what we'll agree to do */
+ecp_options ecp_hisoptions[NUM_PPP];	/* what we agreed to do */
+
+static const fsm_callbacks ecp_callbacks = {
+    NULL, /* ecp_resetci, */
+    NULL, /* ecp_cilen, */
+    NULL, /* ecp_addci, */
+    NULL, /* ecp_ackci, */
+    NULL, /* ecp_nakci, */
+    NULL, /* ecp_rejci, */
+    NULL, /* ecp_reqci, */
+    NULL, /* ecp_up, */
+    NULL, /* ecp_down, */
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL, /* ecp_extcode, */
+    "ECP"
+};
+
+/*
+ * ecp_init - initialize ECP.
+ */
+static void
+ecp_init(unit)
+    int unit;
+{
+    fsm *f = &ecp_fsm[unit];
+
+    f->unit = unit;
+    f->protocol = PPP_ECP;
+    f->callbacks = &ecp_callbacks;
+    fsm_init(f);
+
+#if 0 /* Not necessary, everything is cleared in ppp_new() */
+    memset(&ecp_wantoptions[unit],  0, sizeof(ecp_options));
+    memset(&ecp_gotoptions[unit],   0, sizeof(ecp_options));
+    memset(&ecp_allowoptions[unit], 0, sizeof(ecp_options));
+    memset(&ecp_hisoptions[unit],   0, sizeof(ecp_options));
+#endif /* 0 */
+
+}
+
+
+#if PRINTPKT_SUPPORT
+static int
+ecp_printpkt(p, plen, printer, arg)
+    const u_char *p;
+    int plen;
+    void (*printer) (void *, char *, ...);
+    void *arg;
+{
+    return 0;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#endif /* PPP_SUPPORT && ECP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/eui64.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/eui64.c
new file mode 100644
index 000000000..01493bc1f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/eui64.c
@@ -0,0 +1,56 @@
+/*
+ * eui64.c - EUI64 routines for IPv6CP.
+ *
+ * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Tommi Komulainen
+ *     <Tommi.Komulainen@iki.fi>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: eui64.c,v 1.6 2002/12/04 23:03:32 paulus Exp $
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/eui64.h"
+
+/*
+ * eui64_ntoa - Make an ascii representation of an interface identifier
+ */
+char *eui64_ntoa(eui64_t e) {
+    static char buf[20];
+
+    sprintf(buf, "%02x%02x:%02x%02x:%02x%02x:%02x%02x",
+	     e.e8[0], e.e8[1], e.e8[2], e.e8[3], 
+	     e.e8[4], e.e8[5], e.e8[6], e.e8[7]);
+    return buf;
+}
+
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/fsm.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/fsm.c
new file mode 100644
index 000000000..b1f08afff
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/fsm.c
@@ -0,0 +1,799 @@
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/*
+ * @todo:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+
+static void fsm_timeout (void *);
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len);
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len);
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len);
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len);
+static void fsm_rtermack(fsm *f);
+static void fsm_rcoderej(fsm *f, u_char *inp, int len);
+static void fsm_sconfreq(fsm *f, int retransmit);
+
+#define PROTO_NAME(f)	((f)->callbacks->proto_name)
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void fsm_init(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    f->state = PPP_FSM_INITIAL;
+    f->flags = 0;
+    f->id = 0;				/* XXX Start with random id? */
+    f->maxnakloops = pcb->settings.fsm_max_nak_loops;
+    f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void fsm_lowerup(fsm *f) {
+    switch( f->state ){
+    case PPP_FSM_INITIAL:
+	f->state = PPP_FSM_CLOSED;
+	break;
+
+    case PPP_FSM_STARTING:
+	if( f->flags & OPT_SILENT )
+	    f->state = PPP_FSM_STOPPED;
+	else {
+	    /* Send an initial configure-request */
+	    fsm_sconfreq(f, 0);
+	    f->state = PPP_FSM_REQSENT;
+	}
+	break;
+
+    default:
+	FSMDEBUG(("%s: Up event in state %d!", PROTO_NAME(f), f->state));
+	/* no break */
+    }
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void fsm_lowerdown(fsm *f) {
+    switch( f->state ){
+    case PPP_FSM_CLOSED:
+	f->state = PPP_FSM_INITIAL;
+	break;
+
+    case PPP_FSM_STOPPED:
+	f->state = PPP_FSM_STARTING;
+	if( f->callbacks->starting )
+	    (*f->callbacks->starting)(f);
+	break;
+
+    case PPP_FSM_CLOSING:
+	f->state = PPP_FSM_INITIAL;
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	break;
+
+    case PPP_FSM_STOPPING:
+    case PPP_FSM_REQSENT:
+    case PPP_FSM_ACKRCVD:
+    case PPP_FSM_ACKSENT:
+	f->state = PPP_FSM_STARTING;
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	break;
+
+    case PPP_FSM_OPENED:
+	if( f->callbacks->down )
+	    (*f->callbacks->down)(f);
+	f->state = PPP_FSM_STARTING;
+	break;
+
+    default:
+	FSMDEBUG(("%s: Down event in state %d!", PROTO_NAME(f), f->state));
+	/* no break */
+    }
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void fsm_open(fsm *f) {
+    switch( f->state ){
+    case PPP_FSM_INITIAL:
+	f->state = PPP_FSM_STARTING;
+	if( f->callbacks->starting )
+	    (*f->callbacks->starting)(f);
+	break;
+
+    case PPP_FSM_CLOSED:
+	if( f->flags & OPT_SILENT )
+	    f->state = PPP_FSM_STOPPED;
+	else {
+	    /* Send an initial configure-request */
+	    fsm_sconfreq(f, 0);
+	    f->state = PPP_FSM_REQSENT;
+	}
+	break;
+
+    case PPP_FSM_CLOSING:
+	f->state = PPP_FSM_STOPPING;
+	/* fall through */
+	/* no break */
+    case PPP_FSM_STOPPED:
+    case PPP_FSM_OPENED:
+	if( f->flags & OPT_RESTART ){
+	    fsm_lowerdown(f);
+	    fsm_lowerup(f);
+	}
+	break;
+    default:
+	break;
+    }
+}
+
+/*
+ * terminate_layer - Start process of shutting down the FSM
+ *
+ * Cancel any timeout running, notify upper layers we're done, and
+ * send a terminate-request message as configured.
+ */
+static void terminate_layer(fsm *f, int nextstate) {
+    ppp_pcb *pcb = f->pcb;
+
+    if( f->state != PPP_FSM_OPENED )
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+    else if( f->callbacks->down )
+	(*f->callbacks->down)(f);	/* Inform upper layers we're down */
+
+    /* Init restart counter and send Terminate-Request */
+    f->retransmits = pcb->settings.fsm_max_term_transmits;
+    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+	      (const u_char *) f->term_reason, f->term_reason_len);
+
+    if (f->retransmits == 0) {
+	/*
+	 * User asked for no terminate requests at all; just close it.
+	 * We've already fired off one Terminate-Request just to be nice
+	 * to the peer, but we're not going to wait for a reply.
+	 */
+	f->state = nextstate == PPP_FSM_CLOSING ? PPP_FSM_CLOSED : PPP_FSM_STOPPED;
+	if( f->callbacks->finished )
+	    (*f->callbacks->finished)(f);
+	return;
+    }
+
+    TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time);
+    --f->retransmits;
+
+    f->state = nextstate;
+}
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the PPP_FSM_CLOSED state.
+ */
+void fsm_close(fsm *f, const char *reason) {
+    f->term_reason = reason;
+    f->term_reason_len = (reason == NULL? 0: (u8_t)LWIP_MIN(strlen(reason), 0xFF) );
+    switch( f->state ){
+    case PPP_FSM_STARTING:
+	f->state = PPP_FSM_INITIAL;
+	break;
+    case PPP_FSM_STOPPED:
+	f->state = PPP_FSM_CLOSED;
+	break;
+    case PPP_FSM_STOPPING:
+	f->state = PPP_FSM_CLOSING;
+	break;
+
+    case PPP_FSM_REQSENT:
+    case PPP_FSM_ACKRCVD:
+    case PPP_FSM_ACKSENT:
+    case PPP_FSM_OPENED:
+	terminate_layer(f, PPP_FSM_CLOSING);
+	break;
+    default:
+	break;
+    }
+}
+
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void fsm_timeout(void *arg) {
+    fsm *f = (fsm *) arg;
+    ppp_pcb *pcb = f->pcb;
+
+    switch (f->state) {
+    case PPP_FSM_CLOSING:
+    case PPP_FSM_STOPPING:
+	if( f->retransmits <= 0 ){
+	    /*
+	     * We've waited for an ack long enough.  Peer probably heard us.
+	     */
+	    f->state = (f->state == PPP_FSM_CLOSING)? PPP_FSM_CLOSED: PPP_FSM_STOPPED;
+	    if( f->callbacks->finished )
+		(*f->callbacks->finished)(f);
+	} else {
+	    /* Send Terminate-Request */
+	    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+		      (const u_char *) f->term_reason, f->term_reason_len);
+	    TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time);
+	    --f->retransmits;
+	}
+	break;
+
+    case PPP_FSM_REQSENT:
+    case PPP_FSM_ACKRCVD:
+    case PPP_FSM_ACKSENT:
+	if (f->retransmits <= 0) {
+	    ppp_warn("%s: timeout sending Config-Requests", PROTO_NAME(f));
+	    f->state = PPP_FSM_STOPPED;
+	    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
+		(*f->callbacks->finished)(f);
+
+	} else {
+	    /* Retransmit the configure-request */
+	    if (f->callbacks->retransmit)
+		(*f->callbacks->retransmit)(f);
+	    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
+	    if( f->state == PPP_FSM_ACKRCVD )
+		f->state = PPP_FSM_REQSENT;
+	}
+	break;
+
+    default:
+	FSMDEBUG(("%s: Timeout event in state %d!", PROTO_NAME(f), f->state));
+	/* no break */
+    }
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void fsm_input(fsm *f, u_char *inpacket, int l) {
+    u_char *inp;
+    u_char code, id;
+    int len;
+
+    /*
+     * Parse header (code, id and length).
+     * If packet too short, drop it.
+     */
+    inp = inpacket;
+    if (l < HEADERLEN) {
+	FSMDEBUG(("fsm_input(%x): Rcvd short header.", f->protocol));
+	return;
+    }
+    GETCHAR(code, inp);
+    GETCHAR(id, inp);
+    GETSHORT(len, inp);
+    if (len < HEADERLEN) {
+	FSMDEBUG(("fsm_input(%x): Rcvd illegal length.", f->protocol));
+	return;
+    }
+    if (len > l) {
+	FSMDEBUG(("fsm_input(%x): Rcvd short packet.", f->protocol));
+	return;
+    }
+    len -= HEADERLEN;		/* subtract header length */
+
+    if( f->state == PPP_FSM_INITIAL || f->state == PPP_FSM_STARTING ){
+	FSMDEBUG(("fsm_input(%x): Rcvd packet in state %d.",
+		  f->protocol, f->state));
+	return;
+    }
+
+    /*
+     * Action depends on code.
+     */
+    switch (code) {
+    case CONFREQ:
+	fsm_rconfreq(f, id, inp, len);
+	break;
+    
+    case CONFACK:
+	fsm_rconfack(f, id, inp, len);
+	break;
+    
+    case CONFNAK:
+    case CONFREJ:
+	fsm_rconfnakrej(f, code, id, inp, len);
+	break;
+    
+    case TERMREQ:
+	fsm_rtermreq(f, id, inp, len);
+	break;
+    
+    case TERMACK:
+	fsm_rtermack(f);
+	break;
+    
+    case CODEREJ:
+	fsm_rcoderej(f, inp, len);
+	break;
+    
+    default:
+	if( !f->callbacks->extcode
+	   || !(*f->callbacks->extcode)(f, code, id, inp, len) )
+	    fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+	break;
+    }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) {
+    int code, reject_if_disagree;
+
+    switch( f->state ){
+    case PPP_FSM_CLOSED:
+	/* Go away, we're closed */
+	fsm_sdata(f, TERMACK, id, NULL, 0);
+	return;
+    case PPP_FSM_CLOSING:
+    case PPP_FSM_STOPPING:
+	return;
+
+    case PPP_FSM_OPENED:
+	/* Go down and restart negotiation */
+	if( f->callbacks->down )
+	    (*f->callbacks->down)(f);	/* Inform upper layers */
+	fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+	f->state = PPP_FSM_REQSENT;
+	break;
+
+    case PPP_FSM_STOPPED:
+	/* Negotiation started by our peer */
+	fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+	f->state = PPP_FSM_REQSENT;
+	break;
+    default:
+	break;
+    }
+
+    /*
+     * Pass the requested configuration options
+     * to protocol-specific code for checking.
+     */
+    if (f->callbacks->reqci){		/* Check CI */
+	reject_if_disagree = (f->nakloops >= f->maxnakloops);
+	code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+    } else if (len)
+	code = CONFREJ;			/* Reject all CI */
+    else
+	code = CONFACK;
+
+    /* send the Ack, Nak or Rej to the peer */
+    fsm_sdata(f, code, id, inp, len);
+
+    if (code == CONFACK) {
+	if (f->state == PPP_FSM_ACKRCVD) {
+	    UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	    f->state = PPP_FSM_OPENED;
+	    if (f->callbacks->up)
+		(*f->callbacks->up)(f);	/* Inform upper layers */
+	} else
+	    f->state = PPP_FSM_ACKSENT;
+	f->nakloops = 0;
+
+    } else {
+	/* we sent CONFACK or CONFREJ */
+	if (f->state != PPP_FSM_ACKRCVD)
+	    f->state = PPP_FSM_REQSENT;
+	if( code == CONFNAK )
+	    ++f->nakloops;
+    }
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len) {
+    ppp_pcb *pcb = f->pcb;
+
+    if (id != f->reqid || f->seen_ack)		/* Expected id? */
+	return;					/* Nope, toss... */
+    if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
+	  (len == 0)) ){
+	/* Ack is bad - ignore it */
+	ppp_error("Received bad configure-ack: %P", inp, len);
+	return;
+    }
+    f->seen_ack = 1;
+    f->rnakloops = 0;
+
+    switch (f->state) {
+    case PPP_FSM_CLOSED:
+    case PPP_FSM_STOPPED:
+	fsm_sdata(f, TERMACK, id, NULL, 0);
+	break;
+
+    case PPP_FSM_REQSENT:
+	f->state = PPP_FSM_ACKRCVD;
+	f->retransmits = pcb->settings.fsm_max_conf_req_transmits;
+	break;
+
+    case PPP_FSM_ACKRCVD:
+	/* Huh? an extra valid Ack? oh well... */
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	fsm_sconfreq(f, 0);
+	f->state = PPP_FSM_REQSENT;
+	break;
+
+    case PPP_FSM_ACKSENT:
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	f->state = PPP_FSM_OPENED;
+	f->retransmits = pcb->settings.fsm_max_conf_req_transmits;
+	if (f->callbacks->up)
+	    (*f->callbacks->up)(f);	/* Inform upper layers */
+	break;
+
+    case PPP_FSM_OPENED:
+	/* Go down and restart negotiation */
+	if (f->callbacks->down)
+	    (*f->callbacks->down)(f);	/* Inform upper layers */
+	fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+	f->state = PPP_FSM_REQSENT;
+	break;
+    default:
+	break;
+    }
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) {
+    int ret;
+    int treat_as_reject;
+
+    if (id != f->reqid || f->seen_ack)	/* Expected id? */
+	return;				/* Nope, toss... */
+
+    if (code == CONFNAK) {
+	++f->rnakloops;
+	treat_as_reject = (f->rnakloops >= f->maxnakloops);
+	if (f->callbacks->nakci == NULL
+	    || !(ret = f->callbacks->nakci(f, inp, len, treat_as_reject))) {
+	    ppp_error("Received bad configure-nak: %P", inp, len);
+	    return;
+	}
+    } else {
+	f->rnakloops = 0;
+	if (f->callbacks->rejci == NULL
+	    || !(ret = f->callbacks->rejci(f, inp, len))) {
+	    ppp_error("Received bad configure-rej: %P", inp, len);
+	    return;
+	}
+    }
+
+    f->seen_ack = 1;
+
+    switch (f->state) {
+    case PPP_FSM_CLOSED:
+    case PPP_FSM_STOPPED:
+	fsm_sdata(f, TERMACK, id, NULL, 0);
+	break;
+
+    case PPP_FSM_REQSENT:
+    case PPP_FSM_ACKSENT:
+	/* They didn't agree to what we wanted - try another request */
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	if (ret < 0)
+	    f->state = PPP_FSM_STOPPED;		/* kludge for stopping CCP */
+	else
+	    fsm_sconfreq(f, 0);		/* Send Configure-Request */
+	break;
+
+    case PPP_FSM_ACKRCVD:
+	/* Got a Nak/reject when we had already had an Ack?? oh well... */
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	fsm_sconfreq(f, 0);
+	f->state = PPP_FSM_REQSENT;
+	break;
+
+    case PPP_FSM_OPENED:
+	/* Go down and restart negotiation */
+	if (f->callbacks->down)
+	    (*f->callbacks->down)(f);	/* Inform upper layers */
+	fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+	f->state = PPP_FSM_REQSENT;
+	break;
+    default:
+	break;
+    }
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+
+    switch (f->state) {
+    case PPP_FSM_ACKRCVD:
+    case PPP_FSM_ACKSENT:
+	f->state = PPP_FSM_REQSENT;		/* Start over but keep trying */
+	break;
+
+    case PPP_FSM_OPENED:
+	if (len > 0) {
+	    ppp_info("%s terminated by peer (%0.*v)", PROTO_NAME(f), len, p);
+	} else
+	    ppp_info("%s terminated by peer", PROTO_NAME(f));
+	f->retransmits = 0;
+	f->state = PPP_FSM_STOPPING;
+	if (f->callbacks->down)
+	    (*f->callbacks->down)(f);	/* Inform upper layers */
+	TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time);
+	break;
+    default:
+	break;
+    }
+
+    fsm_sdata(f, TERMACK, id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void fsm_rtermack(fsm *f) {
+    switch (f->state) {
+    case PPP_FSM_CLOSING:
+	UNTIMEOUT(fsm_timeout, f);
+	f->state = PPP_FSM_CLOSED;
+	if( f->callbacks->finished )
+	    (*f->callbacks->finished)(f);
+	break;
+    case PPP_FSM_STOPPING:
+	UNTIMEOUT(fsm_timeout, f);
+	f->state = PPP_FSM_STOPPED;
+	if( f->callbacks->finished )
+	    (*f->callbacks->finished)(f);
+	break;
+
+    case PPP_FSM_ACKRCVD:
+	f->state = PPP_FSM_REQSENT;
+	break;
+
+    case PPP_FSM_OPENED:
+	if (f->callbacks->down)
+	    (*f->callbacks->down)(f);	/* Inform upper layers */
+	fsm_sconfreq(f, 0);
+	f->state = PPP_FSM_REQSENT;
+	break;
+    default:
+	break;
+    }
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void fsm_rcoderej(fsm *f, u_char *inp, int len) {
+    u_char code, id;
+
+    if (len < HEADERLEN) {
+	FSMDEBUG(("fsm_rcoderej: Rcvd short Code-Reject packet!"));
+	return;
+    }
+    GETCHAR(code, inp);
+    GETCHAR(id, inp);
+    ppp_warn("%s: Rcvd Code-Reject for code %d, id %d", PROTO_NAME(f), code, id);
+
+    if( f->state == PPP_FSM_ACKRCVD )
+	f->state = PPP_FSM_REQSENT;
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void fsm_protreject(fsm *f) {
+    switch( f->state ){
+    case PPP_FSM_CLOSING:
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	/* fall through */
+	/* no break */
+    case PPP_FSM_CLOSED:
+	f->state = PPP_FSM_CLOSED;
+	if( f->callbacks->finished )
+	    (*f->callbacks->finished)(f);
+	break;
+
+    case PPP_FSM_STOPPING:
+    case PPP_FSM_REQSENT:
+    case PPP_FSM_ACKRCVD:
+    case PPP_FSM_ACKSENT:
+	UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+	/* fall through */
+	/* no break */
+    case PPP_FSM_STOPPED:
+	f->state = PPP_FSM_STOPPED;
+	if( f->callbacks->finished )
+	    (*f->callbacks->finished)(f);
+	break;
+
+    case PPP_FSM_OPENED:
+	terminate_layer(f, PPP_FSM_STOPPING);
+	break;
+
+    default:
+	FSMDEBUG(("%s: Protocol-reject event in state %d!",
+		  PROTO_NAME(f), f->state));
+	/* no break */
+    }
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void fsm_sconfreq(fsm *f, int retransmit) {
+    ppp_pcb *pcb = f->pcb;
+    struct pbuf *p;
+    u_char *outp;
+    int cilen;
+
+    if( f->state != PPP_FSM_REQSENT && f->state != PPP_FSM_ACKRCVD && f->state != PPP_FSM_ACKSENT ){
+	/* Not currently negotiating - reset options */
+	if( f->callbacks->resetci )
+	    (*f->callbacks->resetci)(f);
+	f->nakloops = 0;
+	f->rnakloops = 0;
+    }
+
+    if( !retransmit ){
+	/* New request - reset retransmission counter, use new ID */
+	f->retransmits = pcb->settings.fsm_max_conf_req_transmits;
+	f->reqid = ++f->id;
+    }
+
+    f->seen_ack = 0;
+
+    /*
+     * Make up the request packet
+     */
+    if( f->callbacks->cilen && f->callbacks->addci ){
+	cilen = (*f->callbacks->cilen)(f);
+	if( cilen > pcb->peer_mru - HEADERLEN )
+	    cilen = pcb->peer_mru - HEADERLEN;
+    } else
+	cilen = 0;
+
+    p = pbuf_alloc(PBUF_RAW, (u16_t)(cilen + HEADERLEN + PPP_HDRLEN), PPP_CTRL_PBUF_TYPE);
+    if(NULL == p)
+        return;
+    if(p->tot_len != p->len) {
+        pbuf_free(p);
+        return;
+    }
+
+    /* send the request to our peer */
+    outp = (u_char*)p->payload;
+    MAKEHEADER(outp, f->protocol);
+    PUTCHAR(CONFREQ, outp);
+    PUTCHAR(f->reqid, outp);
+    PUTSHORT(cilen + HEADERLEN, outp);
+    if (cilen != 0) {
+	(*f->callbacks->addci)(f, outp, &cilen);
+	LWIP_ASSERT("cilen == p->len - HEADERLEN - PPP_HDRLEN", cilen == p->len - HEADERLEN - PPP_HDRLEN);
+    }
+
+    ppp_write(pcb, p);
+
+    /* start the retransmit timer */
+    --f->retransmits;
+    TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time);
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen) {
+    ppp_pcb *pcb = f->pcb;
+    struct pbuf *p;
+    u_char *outp;
+    int outlen;
+
+    /* Adjust length to be smaller than MTU */
+    if (datalen > pcb->peer_mru - HEADERLEN)
+	datalen = pcb->peer_mru - HEADERLEN;
+    outlen = datalen + HEADERLEN;
+
+    p = pbuf_alloc(PBUF_RAW, (u16_t)(outlen + PPP_HDRLEN), PPP_CTRL_PBUF_TYPE);
+    if(NULL == p)
+        return;
+    if(p->tot_len != p->len) {
+        pbuf_free(p);
+        return;
+    }
+
+    outp = (u_char*)p->payload;
+    if (datalen) /* && data != outp + PPP_HDRLEN + HEADERLEN)  -- was only for fsm_sconfreq() */
+	MEMCPY(outp + PPP_HDRLEN + HEADERLEN, data, datalen);
+    MAKEHEADER(outp, f->protocol);
+    PUTCHAR(code, outp);
+    PUTCHAR(id, outp);
+    PUTSHORT(outlen, outp);
+    ppp_write(pcb, p);
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ipcp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ipcp.c
new file mode 100644
index 000000000..b7c766eb0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ipcp.c
@@ -0,0 +1,2418 @@
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/*
+ * @todo:
+ */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <netdb.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/ipcp.h"
+
+#if 0 /* UNUSED */
+/* global vars */
+u32_t netmask = 0;		/* IP netmask to set on interface */
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+bool	disable_defaultip = 0;	/* Don't use hostname for default IP adrs */
+#endif /* UNUSED */
+
+#if 0 /* moved to ppp_settings */
+bool	noremoteip = 0;		/* Let him have no IP address */
+#endif /* moved to ppp_setting */
+
+#if 0 /* UNUSED */
+/* Hook for a plugin to know when IP protocol has come up */
+void (*ip_up_hook) (void) = NULL;
+
+/* Hook for a plugin to know when IP protocol has come down */
+void (*ip_down_hook) (void) = NULL;
+
+/* Hook for a plugin to choose the remote IP address */
+void (*ip_choose_hook) (u32_t *) = NULL;
+#endif /* UNUSED */
+
+#if PPP_NOTIFY
+/* Notifiers for when IPCP goes up and down */
+struct notifier *ip_up_notifier = NULL;
+struct notifier *ip_down_notifier = NULL;
+#endif /* PPP_NOTIFY */
+
+/* local vars */
+#if 0 /* moved to ppp_pcb */
+static int default_route_set[NUM_PPP];	/* Have set up a default route */
+static int proxy_arp_set[NUM_PPP];	/* Have created proxy arp entry */
+static int ipcp_is_up;			/* have called np_up() */
+static int ipcp_is_open;		/* haven't called np_finished() */
+static bool ask_for_local;		/* request our address from peer */
+#endif /* moved to ppp_pcb */
+#if 0 /* UNUSED */
+static char vj_value[8];		/* string form of vj option value */
+static char netmask_str[20];		/* string form of netmask value */
+#endif /* UNUSED */
+
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci(fsm *f);	/* Reset our CI */
+static int  ipcp_cilen(fsm *f);	        /* Return length of our CI */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp); /* Add our CI */
+static int  ipcp_ackci(fsm *f, u_char *p, int len);	/* Peer ack'd our CI */
+static int  ipcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject);/* Peer nak'd our CI */
+static int  ipcp_rejci(fsm *f, u_char *p, int len);	/* Peer rej'd our CI */
+static int  ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree); /* Rcv CI */
+static void ipcp_up(fsm *f);		/* We're UP */
+static void ipcp_down(fsm *f);		/* We're DOWN */
+static void ipcp_finished(fsm *f);	/* Don't need lower layer */
+
+static const fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+    ipcp_resetci,		/* Reset our Configuration Information */
+    ipcp_cilen,			/* Length of our Configuration Information */
+    ipcp_addci,			/* Add our Configuration Information */
+    ipcp_ackci,			/* ACK our Configuration Information */
+    ipcp_nakci,			/* NAK our Configuration Information */
+    ipcp_rejci,			/* Reject our Configuration Information */
+    ipcp_reqci,			/* Request peer's Configuration Information */
+    ipcp_up,			/* Called when fsm reaches OPENED state */
+    ipcp_down,			/* Called when fsm leaves OPENED state */
+    NULL,			/* Called when we want the lower layer up */
+    ipcp_finished,		/* Called when we want the lower layer down */
+    NULL,			/* Called when Protocol-Reject received */
+    NULL,			/* Retransmission is necessary */
+    NULL,			/* Called to handle protocol-specific codes */
+    "IPCP"			/* String name of protocol */
+};
+
+/*
+ * Command-line options.
+ */
+#if PPP_OPTIONS
+static int setvjslots (char **);
+static int setdnsaddr (char **);
+static int setwinsaddr (char **);
+static int setnetmask (char **);
+int setipaddr (char *, char **, int);
+
+static void printipaddr (option_t *, void (*)(void *, char *,...),void *);
+
+static option_t ipcp_option_list[] = {
+    { "noip", o_bool, &ipcp_protent.enabled_flag,
+      "Disable IP and IPCP" },
+    { "-ip", o_bool, &ipcp_protent.enabled_flag,
+      "Disable IP and IPCP", OPT_ALIAS },
+
+    { "novj", o_bool, &ipcp_wantoptions[0].neg_vj,
+      "Disable VJ compression", OPT_A2CLR, &ipcp_allowoptions[0].neg_vj },
+    { "-vj", o_bool, &ipcp_wantoptions[0].neg_vj,
+      "Disable VJ compression", OPT_ALIAS | OPT_A2CLR,
+      &ipcp_allowoptions[0].neg_vj },
+
+    { "novjccomp", o_bool, &ipcp_wantoptions[0].cflag,
+      "Disable VJ connection-ID compression", OPT_A2CLR,
+      &ipcp_allowoptions[0].cflag },
+    { "-vjccomp", o_bool, &ipcp_wantoptions[0].cflag,
+      "Disable VJ connection-ID compression", OPT_ALIAS | OPT_A2CLR,
+      &ipcp_allowoptions[0].cflag },
+
+    { "vj-max-slots", o_special, (void *)setvjslots,
+      "Set maximum VJ header slots",
+      OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, vj_value },
+
+    { "ipcp-accept-local", o_bool, &ipcp_wantoptions[0].accept_local,
+      "Accept peer's address for us", 1 },
+    { "ipcp-accept-remote", o_bool, &ipcp_wantoptions[0].accept_remote,
+      "Accept peer's address for it", 1 },
+
+    { "ipparam", o_string, &ipparam,
+      "Set ip script parameter", OPT_PRIO },
+
+    { "noipdefault", o_bool, &disable_defaultip,
+      "Don't use name for default IP adrs", 1 },
+
+    { "ms-dns", 1, (void *)setdnsaddr,
+      "DNS address for the peer's use" },
+    { "ms-wins", 1, (void *)setwinsaddr,
+      "Nameserver for SMB over TCP/IP for peer" },
+
+    { "ipcp-restart", o_int, &ipcp_fsm[0].timeouttime,
+      "Set timeout for IPCP", OPT_PRIO },
+    { "ipcp-max-terminate", o_int, &ipcp_fsm[0].maxtermtransmits,
+      "Set max #xmits for term-reqs", OPT_PRIO },
+    { "ipcp-max-configure", o_int, &ipcp_fsm[0].maxconfreqtransmits,
+      "Set max #xmits for conf-reqs", OPT_PRIO },
+    { "ipcp-max-failure", o_int, &ipcp_fsm[0].maxnakloops,
+      "Set max #conf-naks for IPCP", OPT_PRIO },
+
+    { "defaultroute", o_bool, &ipcp_wantoptions[0].default_route,
+      "Add default route", OPT_ENABLE|1, &ipcp_allowoptions[0].default_route },
+    { "nodefaultroute", o_bool, &ipcp_allowoptions[0].default_route,
+      "disable defaultroute option", OPT_A2CLR,
+      &ipcp_wantoptions[0].default_route },
+    { "-defaultroute", o_bool, &ipcp_allowoptions[0].default_route,
+      "disable defaultroute option", OPT_ALIAS | OPT_A2CLR,
+      &ipcp_wantoptions[0].default_route },
+
+    { "replacedefaultroute", o_bool,
+				&ipcp_wantoptions[0].replace_default_route,
+      "Replace default route", 1
+    },
+    { "noreplacedefaultroute", o_bool,
+				&ipcp_allowoptions[0].replace_default_route,
+      "Never replace default route", OPT_A2COPY,
+				&ipcp_wantoptions[0].replace_default_route },
+    { "proxyarp", o_bool, &ipcp_wantoptions[0].proxy_arp,
+      "Add proxy ARP entry", OPT_ENABLE|1, &ipcp_allowoptions[0].proxy_arp },
+    { "noproxyarp", o_bool, &ipcp_allowoptions[0].proxy_arp,
+      "disable proxyarp option", OPT_A2CLR,
+      &ipcp_wantoptions[0].proxy_arp },
+    { "-proxyarp", o_bool, &ipcp_allowoptions[0].proxy_arp,
+      "disable proxyarp option", OPT_ALIAS | OPT_A2CLR,
+      &ipcp_wantoptions[0].proxy_arp },
+
+    { "usepeerdns", o_bool, &usepeerdns,
+      "Ask peer for DNS address(es)", 1 },
+
+    { "netmask", o_special, (void *)setnetmask,
+      "set netmask", OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, netmask_str },
+
+    { "ipcp-no-addresses", o_bool, &ipcp_wantoptions[0].old_addrs,
+      "Disable old-style IP-Addresses usage", OPT_A2CLR,
+      &ipcp_allowoptions[0].old_addrs },
+    { "ipcp-no-address", o_bool, &ipcp_wantoptions[0].neg_addr,
+      "Disable IP-Address usage", OPT_A2CLR,
+      &ipcp_allowoptions[0].neg_addr },
+
+    { "noremoteip", o_bool, &noremoteip,
+      "Allow peer to have no IP address", 1 },
+
+    { "nosendip", o_bool, &ipcp_wantoptions[0].neg_addr,
+      "Don't send our IP address to peer", OPT_A2CLR,
+      &ipcp_wantoptions[0].old_addrs},
+
+    { "IP addresses", o_wild, (void *) &setipaddr,
+      "set local and remote IP addresses",
+      OPT_NOARG | OPT_A2PRINTER, (void *) &printipaddr },
+
+    { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init(ppp_pcb *pcb);
+static void ipcp_open(ppp_pcb *pcb);
+static void ipcp_close(ppp_pcb *pcb, const char *reason);
+static void ipcp_lowerup(ppp_pcb *pcb);
+static void ipcp_lowerdown(ppp_pcb *pcb);
+static void ipcp_input(ppp_pcb *pcb, u_char *p, int len);
+static void ipcp_protrej(ppp_pcb *pcb);
+#if PRINTPKT_SUPPORT
+static int ipcp_printpkt(const u_char *p, int plen,
+		void (*printer) (void *, const char *, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+static void ip_check_options (void);
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+static int  ip_demand_conf (int);
+static int  ip_active_pkt (u_char *, int);
+#endif /* DEMAND_SUPPORT */
+#if 0 /* UNUSED */
+static void create_resolv (u32_t, u32_t);
+#endif /* UNUSED */
+
+const struct protent ipcp_protent = {
+    PPP_IPCP,
+    ipcp_init,
+    ipcp_input,
+    ipcp_protrej,
+    ipcp_lowerup,
+    ipcp_lowerdown,
+    ipcp_open,
+    ipcp_close,
+#if PRINTPKT_SUPPORT
+    ipcp_printpkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    NULL,
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    "IPCP",
+    "IP",
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    ipcp_option_list,
+    ip_check_options,
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    ip_demand_conf,
+    ip_active_pkt
+#endif /* DEMAND_SUPPORT */
+};
+
+static void ipcp_clear_addrs(ppp_pcb *pcb, u32_t ouraddr, u32_t hisaddr, u8_t replacedefaultroute);
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID	2
+#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
+#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR	6	/* new-style single address option */
+#define CILEN_ADDRS	10	/* old-style dual address option */
+
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+#if 0 /* UNUSED, already defined by lwIP */
+/*
+ * Make a string representation of a network IP address.
+ */
+char *
+ip_ntoa(ipaddr)
+u32_t ipaddr;
+{
+    static char b[64];
+
+    slprintf(b, sizeof(b), "%I", ipaddr);
+    return b;
+}
+#endif /* UNUSED, already defined by lwIP */
+
+/*
+ * Option parsing.
+ */
+#if PPP_OPTIONS
+/*
+ * setvjslots - set maximum number of connection slots for VJ compression
+ */
+static int
+setvjslots(argv)
+    char **argv;
+{
+    int value;
+
+    if (!int_option(*argv, &value))
+	return 0;
+
+    if (value < 2 || value > 16) {
+	option_error("vj-max-slots value must be between 2 and 16");
+	return 0;
+    }
+    ipcp_wantoptions [0].maxslotindex =
+        ipcp_allowoptions[0].maxslotindex = value - 1;
+    slprintf(vj_value, sizeof(vj_value), "%d", value);
+    return 1;
+}
+
+/*
+ * setdnsaddr - set the dns address(es)
+ */
+static int
+setdnsaddr(argv)
+    char **argv;
+{
+    u32_t dns;
+    struct hostent *hp;
+
+    dns = inet_addr(*argv);
+    if (dns == (u32_t) -1) {
+	if ((hp = gethostbyname(*argv)) == NULL) {
+	    option_error("invalid address parameter '%s' for ms-dns option",
+			 *argv);
+	    return 0;
+	}
+	dns = *(u32_t *)hp->h_addr;
+    }
+
+    /* We take the last 2 values given, the 2nd-last as the primary
+       and the last as the secondary.  If only one is given it
+       becomes both primary and secondary. */
+    if (ipcp_allowoptions[0].dnsaddr[1] == 0)
+	ipcp_allowoptions[0].dnsaddr[0] = dns;
+    else
+	ipcp_allowoptions[0].dnsaddr[0] = ipcp_allowoptions[0].dnsaddr[1];
+
+    /* always set the secondary address value. */
+    ipcp_allowoptions[0].dnsaddr[1] = dns;
+
+    return (1);
+}
+
+/*
+ * setwinsaddr - set the wins address(es)
+ * This is primrarly used with the Samba package under UNIX or for pointing
+ * the caller to the existing WINS server on a Windows NT platform.
+ */
+static int
+setwinsaddr(argv)
+    char **argv;
+{
+    u32_t wins;
+    struct hostent *hp;
+
+    wins = inet_addr(*argv);
+    if (wins == (u32_t) -1) {
+	if ((hp = gethostbyname(*argv)) == NULL) {
+	    option_error("invalid address parameter '%s' for ms-wins option",
+			 *argv);
+	    return 0;
+	}
+	wins = *(u32_t *)hp->h_addr;
+    }
+
+    /* We take the last 2 values given, the 2nd-last as the primary
+       and the last as the secondary.  If only one is given it
+       becomes both primary and secondary. */
+    if (ipcp_allowoptions[0].winsaddr[1] == 0)
+	ipcp_allowoptions[0].winsaddr[0] = wins;
+    else
+	ipcp_allowoptions[0].winsaddr[0] = ipcp_allowoptions[0].winsaddr[1];
+
+    /* always set the secondary address value. */
+    ipcp_allowoptions[0].winsaddr[1] = wins;
+
+    return (1);
+}
+
+/*
+ * setipaddr - Set the IP address
+ * If doit is 0, the call is to check whether this option is
+ * potentially an IP address specification.
+ * Not static so that plugins can call it to set the addresses
+ */
+int
+setipaddr(arg, argv, doit)
+    char *arg;
+    char **argv;
+    int doit;
+{
+    struct hostent *hp;
+    char *colon;
+    u32_t local, remote;
+    ipcp_options *wo = &ipcp_wantoptions[0];
+    static int prio_local = 0, prio_remote = 0;
+
+    /*
+     * IP address pair separated by ":".
+     */
+    if ((colon = strchr(arg, ':')) == NULL)
+	return 0;
+    if (!doit)
+	return 1;
+  
+    /*
+     * If colon first character, then no local addr.
+     */
+    if (colon != arg && option_priority >= prio_local) {
+	*colon = '\0';
+	if ((local = inet_addr(arg)) == (u32_t) -1) {
+	    if ((hp = gethostbyname(arg)) == NULL) {
+		option_error("unknown host: %s", arg);
+		return 0;
+	    }
+	    local = *(u32_t *)hp->h_addr;
+	}
+	if (bad_ip_adrs(local)) {
+	    option_error("bad local IP address %s", ip_ntoa(local));
+	    return 0;
+	}
+	if (local != 0)
+	    wo->ouraddr = local;
+	*colon = ':';
+	prio_local = option_priority;
+    }
+  
+    /*
+     * If colon last character, then no remote addr.
+     */
+    if (*++colon != '\0' && option_priority >= prio_remote) {
+	if ((remote = inet_addr(colon)) == (u32_t) -1) {
+	    if ((hp = gethostbyname(colon)) == NULL) {
+		option_error("unknown host: %s", colon);
+		return 0;
+	    }
+	    remote = *(u32_t *)hp->h_addr;
+	    if (remote_name[0] == 0)
+		strlcpy(remote_name, colon, sizeof(remote_name));
+	}
+	if (bad_ip_adrs(remote)) {
+	    option_error("bad remote IP address %s", ip_ntoa(remote));
+	    return 0;
+	}
+	if (remote != 0)
+	    wo->hisaddr = remote;
+	prio_remote = option_priority;
+    }
+
+    return 1;
+}
+
+static void
+printipaddr(opt, printer, arg)
+    option_t *opt;
+    void (*printer) (void *, char *, ...);
+    void *arg;
+{
+	ipcp_options *wo = &ipcp_wantoptions[0];
+
+	if (wo->ouraddr != 0)
+		printer(arg, "%I", wo->ouraddr);
+	printer(arg, ":");
+	if (wo->hisaddr != 0)
+		printer(arg, "%I", wo->hisaddr);
+}
+
+/*
+ * setnetmask - set the netmask to be used on the interface.
+ */
+static int
+setnetmask(argv)
+    char **argv;
+{
+    u32_t mask;
+    int n;
+    char *p;
+
+    /*
+     * Unfortunately, if we use inet_addr, we can't tell whether
+     * a result of all 1s is an error or a valid 255.255.255.255.
+     */
+    p = *argv;
+    n = parse_dotted_ip(p, &mask);
+
+    mask = lwip_htonl(mask);
+
+    if (n == 0 || p[n] != 0 || (netmask & ~mask) != 0) {
+	option_error("invalid netmask value '%s'", *argv);
+	return 0;
+    }
+
+    netmask = mask;
+    slprintf(netmask_str, sizeof(netmask_str), "%I", mask);
+
+    return (1);
+}
+
+int
+parse_dotted_ip(p, vp)
+    char *p;
+    u32_t *vp;
+{
+    int n;
+    u32_t v, b;
+    char *endp, *p0 = p;
+
+    v = 0;
+    for (n = 3;; --n) {
+	b = strtoul(p, &endp, 0);
+	if (endp == p)
+	    return 0;
+	if (b > 255) {
+	    if (n < 3)
+		return 0;
+	    /* accept e.g. 0xffffff00 */
+	    *vp = b;
+	    return endp - p0;
+	}
+	v |= b << (n * 8);
+	p = endp;
+	if (n == 0)
+	    break;
+	if (*p != '.')
+	    return 0;
+	++p;
+    }
+    *vp = v;
+    return p - p0;
+}
+#endif /* PPP_OPTIONS */
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void ipcp_init(ppp_pcb *pcb) {
+    fsm *f = &pcb->ipcp_fsm;
+
+    ipcp_options *wo = &pcb->ipcp_wantoptions;
+    ipcp_options *ao = &pcb->ipcp_allowoptions;
+
+    f->pcb = pcb;
+    f->protocol = PPP_IPCP;
+    f->callbacks = &ipcp_callbacks;
+    fsm_init(f);
+
+    /*
+     * Some 3G modems use repeated IPCP NAKs as a way of stalling
+     * until they can contact a server on the network, so we increase
+     * the default number of NAKs we accept before we start treating
+     * them as rejects.
+     */
+    f->maxnakloops = 100;
+
+#if 0 /* Not necessary, everything is cleared in ppp_new() */
+    memset(wo, 0, sizeof(*wo));
+    memset(ao, 0, sizeof(*ao));
+#endif /* 0 */
+
+    wo->neg_addr = wo->old_addrs = 1;
+#if VJ_SUPPORT
+    wo->neg_vj = 1;
+    wo->vj_protocol = IPCP_VJ_COMP;
+    wo->maxslotindex = MAX_STATES - 1; /* really max index */
+    wo->cflag = 1;
+#endif /* VJ_SUPPORT */
+
+#if 0 /* UNUSED */
+    /* wanting default route by default */
+    wo->default_route = 1;
+#endif /* UNUSED */
+
+    ao->neg_addr = ao->old_addrs = 1;
+#if VJ_SUPPORT
+    /* max slots and slot-id compression are currently hardwired in */
+    /* ppp_if.c to 16 and 1, this needs to be changed (among other */
+    /* things) gmc */
+
+    ao->neg_vj = 1;
+    ao->maxslotindex = MAX_STATES - 1;
+    ao->cflag = 1;
+#endif /* #if VJ_SUPPORT */
+
+#if 0 /* UNUSED */
+    /*
+     * XXX These control whether the user may use the proxyarp
+     * and defaultroute options.
+     */
+    ao->proxy_arp = 1;
+    ao->default_route = 1;
+#endif /* UNUSED */
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void ipcp_open(ppp_pcb *pcb) {
+    fsm *f = &pcb->ipcp_fsm;
+    fsm_open(f);
+    pcb->ipcp_is_open = 1;
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void ipcp_close(ppp_pcb *pcb, const char *reason) {
+    fsm *f = &pcb->ipcp_fsm;
+    fsm_close(f, reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void ipcp_lowerup(ppp_pcb *pcb) {
+    fsm *f = &pcb->ipcp_fsm;
+    fsm_lowerup(f);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void ipcp_lowerdown(ppp_pcb *pcb) {
+    fsm *f = &pcb->ipcp_fsm;
+    fsm_lowerdown(f);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void ipcp_input(ppp_pcb *pcb, u_char *p, int len) {
+    fsm *f = &pcb->ipcp_fsm;
+    fsm_input(f, p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipcp_protrej(ppp_pcb *pcb) {
+    fsm *f = &pcb->ipcp_fsm;
+    fsm_lowerdown(f);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ * Called by fsm_sconfreq, Send Configure Request.
+ */
+static void ipcp_resetci(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *wo = &pcb->ipcp_wantoptions;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+    ipcp_options *ao = &pcb->ipcp_allowoptions;
+
+    wo->req_addr = (wo->neg_addr || wo->old_addrs) &&
+	(ao->neg_addr || ao->old_addrs);
+    if (wo->ouraddr == 0)
+	wo->accept_local = 1;
+    if (wo->hisaddr == 0)
+	wo->accept_remote = 1;
+#if LWIP_DNS
+    wo->req_dns1 = wo->req_dns2 = pcb->settings.usepeerdns;	/* Request DNS addresses from the peer */
+#endif /* LWIP_DNS */
+    *go = *wo;
+    if (!pcb->ask_for_local)
+	go->ouraddr = 0;
+#if 0 /* UNUSED */
+    if (ip_choose_hook) {
+	ip_choose_hook(&wo->hisaddr);
+	if (wo->hisaddr) {
+	    wo->accept_remote = 0;
+	}
+    }
+#endif /* UNUSED */
+    BZERO(&pcb->ipcp_hisoptions, sizeof(ipcp_options));
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ * Called by fsm_sconfreq, Send Configure Request.
+ */
+static int ipcp_cilen(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+#if VJ_SUPPORT
+    ipcp_options *wo = &pcb->ipcp_wantoptions;
+#endif /* VJ_SUPPORT */
+    ipcp_options *ho = &pcb->ipcp_hisoptions;
+
+#define LENCIADDRS(neg)		(neg ? CILEN_ADDRS : 0)
+#if VJ_SUPPORT
+#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#endif /* VJ_SUPPORT */
+#define LENCIADDR(neg)		(neg ? CILEN_ADDR : 0)
+#if LWIP_DNS
+#define LENCIDNS(neg)		LENCIADDR(neg)
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+#define LENCIWINS(neg)		LENCIADDR(neg)
+#endif /* UNUSED - WINS */
+
+    /*
+     * First see if we want to change our options to the old
+     * forms because we have received old forms from the peer.
+     */
+    if (go->neg_addr && go->old_addrs && !ho->neg_addr && ho->old_addrs)
+	go->neg_addr = 0;
+
+#if VJ_SUPPORT
+    if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+	/* try an older style of VJ negotiation */
+	/* use the old style only if the peer did */
+	if (ho->neg_vj && ho->old_vj) {
+	    go->neg_vj = 1;
+	    go->old_vj = 1;
+	    go->vj_protocol = ho->vj_protocol;
+	}
+    }
+#endif /* VJ_SUPPORT */
+
+    return (LENCIADDRS(!go->neg_addr && go->old_addrs) +
+#if VJ_SUPPORT
+	    LENCIVJ(go->neg_vj, go->old_vj) +
+#endif /* VJ_SUPPORT */
+	    LENCIADDR(go->neg_addr) +
+#if LWIP_DNS
+	    LENCIDNS(go->req_dns1) +
+	    LENCIDNS(go->req_dns2) +
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+	    LENCIWINS(go->winsaddr[0]) +
+	    LENCIWINS(go->winsaddr[1]) +
+#endif /* UNUSED - WINS */
+	    0);
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ * Called by fsm_sconfreq, Send Configure Request.
+ */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+    int len = *lenp;
+
+#define ADDCIADDRS(opt, neg, val1, val2) \
+    if (neg) { \
+	if (len >= CILEN_ADDRS) { \
+	    u32_t l; \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(CILEN_ADDRS, ucp); \
+	    l = lwip_ntohl(val1); \
+	    PUTLONG(l, ucp); \
+	    l = lwip_ntohl(val2); \
+	    PUTLONG(l, ucp); \
+	    len -= CILEN_ADDRS; \
+	} else \
+	    go->old_addrs = 0; \
+    }
+
+#if VJ_SUPPORT
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+    if (neg) { \
+	int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+	if (len >= vjlen) { \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(vjlen, ucp); \
+	    PUTSHORT(val, ucp); \
+	    if (!old) { \
+		PUTCHAR(maxslotindex, ucp); \
+		PUTCHAR(cflag, ucp); \
+	    } \
+	    len -= vjlen; \
+	} else \
+	    neg = 0; \
+    }
+#endif /* VJ_SUPPORT */
+
+#define ADDCIADDR(opt, neg, val) \
+    if (neg) { \
+	if (len >= CILEN_ADDR) { \
+	    u32_t l; \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(CILEN_ADDR, ucp); \
+	    l = lwip_ntohl(val); \
+	    PUTLONG(l, ucp); \
+	    len -= CILEN_ADDR; \
+	} else \
+	    neg = 0; \
+    }
+
+#if LWIP_DNS
+#define ADDCIDNS(opt, neg, addr) \
+    if (neg) { \
+	if (len >= CILEN_ADDR) { \
+	    u32_t l; \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(CILEN_ADDR, ucp); \
+	    l = lwip_ntohl(addr); \
+	    PUTLONG(l, ucp); \
+	    len -= CILEN_ADDR; \
+	} else \
+	    neg = 0; \
+    }
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+#define ADDCIWINS(opt, addr) \
+    if (addr) { \
+	if (len >= CILEN_ADDR) { \
+	    u32_t l; \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(CILEN_ADDR, ucp); \
+	    l = lwip_ntohl(addr); \
+	    PUTLONG(l, ucp); \
+	    len -= CILEN_ADDR; \
+	} else \
+	    addr = 0; \
+    }
+#endif /* UNUSED - WINS */
+
+    ADDCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs, go->ouraddr,
+	       go->hisaddr);
+
+#if VJ_SUPPORT
+    ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+	    go->maxslotindex, go->cflag);
+#endif /* VJ_SUPPORT */
+
+    ADDCIADDR(CI_ADDR, go->neg_addr, go->ouraddr);
+
+#if LWIP_DNS
+    ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+    ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+    ADDCIWINS(CI_MS_WINS1, go->winsaddr[0]);
+
+    ADDCIWINS(CI_MS_WINS2, go->winsaddr[1]);
+#endif /* UNUSED - WINS */
+    
+    *lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ * Called by fsm_rconfack, Receive Configure ACK.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int ipcp_ackci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+    u_short cilen, citype;
+    u32_t cilong;
+#if VJ_SUPPORT
+    u_short cishort;
+    u_char cimaxslotindex, cicflag;
+#endif /* VJ_SUPPORT */
+
+    /*
+     * CIs must be in exactly the same order that we sent...
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+
+#define ACKCIADDRS(opt, neg, val1, val2) \
+    if (neg) { \
+	u32_t l; \
+	if ((len -= CILEN_ADDRS) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_ADDRS || \
+	    citype != opt) \
+	    goto bad; \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	if (val1 != cilong) \
+	    goto bad; \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	if (val2 != cilong) \
+	    goto bad; \
+    }
+
+#if VJ_SUPPORT
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+    if (neg) { \
+	int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+	if ((len -= vjlen) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != vjlen || \
+	    citype != opt)  \
+	    goto bad; \
+	GETSHORT(cishort, p); \
+	if (cishort != val) \
+	    goto bad; \
+	if (!old) { \
+	    GETCHAR(cimaxslotindex, p); \
+	    if (cimaxslotindex != maxslotindex) \
+		goto bad; \
+	    GETCHAR(cicflag, p); \
+	    if (cicflag != cflag) \
+		goto bad; \
+	} \
+    }
+#endif /* VJ_SUPPORT */
+
+#define ACKCIADDR(opt, neg, val) \
+    if (neg) { \
+	u32_t l; \
+	if ((len -= CILEN_ADDR) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_ADDR || \
+	    citype != opt) \
+	    goto bad; \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	if (val != cilong) \
+	    goto bad; \
+    }
+
+#if LWIP_DNS
+#define ACKCIDNS(opt, neg, addr) \
+    if (neg) { \
+	u32_t l; \
+	if ((len -= CILEN_ADDR) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_ADDR || citype != opt) \
+	    goto bad; \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	if (addr != cilong) \
+	    goto bad; \
+    }
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+#define ACKCIWINS(opt, addr) \
+    if (addr) { \
+	u32_t l; \
+	if ((len -= CILEN_ADDR) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_ADDR || citype != opt) \
+	    goto bad; \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	if (addr != cilong) \
+	    goto bad; \
+    }
+#endif /* UNUSED - WINS */
+
+    ACKCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs, go->ouraddr,
+	       go->hisaddr);
+
+#if VJ_SUPPORT
+    ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+	    go->maxslotindex, go->cflag);
+#endif /* VJ_SUPPORT */
+
+    ACKCIADDR(CI_ADDR, go->neg_addr, go->ouraddr);
+
+#if LWIP_DNS
+    ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+    ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+    ACKCIWINS(CI_MS_WINS1, go->winsaddr[0]);
+
+    ACKCIWINS(CI_MS_WINS2, go->winsaddr[1]);
+#endif /* UNUSED - WINS */
+
+    /*
+     * If there are any remaining CIs, then this packet is bad.
+     */
+    if (len != 0)
+	goto bad;
+    return (1);
+
+bad:
+    IPCPDEBUG(("ipcp_ackci: received bad Ack!"));
+    return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the OPENED state.
+ * Calback from fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int ipcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+    u_char citype, cilen, *next;
+#if VJ_SUPPORT
+    u_char cimaxslotindex, cicflag;
+    u_short cishort;
+#endif /* VJ_SUPPORT */
+    u32_t ciaddr1, ciaddr2, l;
+#if LWIP_DNS
+    u32_t cidnsaddr;
+#endif /* LWIP_DNS */
+    ipcp_options no;		/* options we've seen Naks for */
+    ipcp_options try_;		/* options to request next time */
+
+    BZERO(&no, sizeof(no));
+    try_ = *go;
+
+    /*
+     * Any Nak'd CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define NAKCIADDRS(opt, neg, code) \
+    if ((neg) && \
+	(cilen = p[1]) == CILEN_ADDRS && \
+	len >= cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	ciaddr1 = lwip_htonl(l); \
+	GETLONG(l, p); \
+	ciaddr2 = lwip_htonl(l); \
+	no.old_addrs = 1; \
+	code \
+    }
+
+#if VJ_SUPPORT
+#define NAKCIVJ(opt, neg, code) \
+    if (go->neg && \
+	((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+	len >= cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	no.neg = 1; \
+        code \
+    }
+#endif /* VJ_SUPPORT */
+
+#define NAKCIADDR(opt, neg, code) \
+    if (go->neg && \
+	(cilen = p[1]) == CILEN_ADDR && \
+	len >= cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	ciaddr1 = lwip_htonl(l); \
+	no.neg = 1; \
+	code \
+    }
+
+#if LWIP_DNS
+#define NAKCIDNS(opt, neg, code) \
+    if (go->neg && \
+	((cilen = p[1]) == CILEN_ADDR) && \
+	len >= cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	cidnsaddr = lwip_htonl(l); \
+	no.neg = 1; \
+	code \
+    }
+#endif /* LWIP_DNS */
+
+    /*
+     * Accept the peer's idea of {our,his} address, if different
+     * from our idea, only if the accept_{local,remote} flag is set.
+     */
+    NAKCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs,
+	       if (treat_as_reject) {
+		   try_.old_addrs = 0;
+	       } else {
+		   if (go->accept_local && ciaddr1) {
+		       /* take his idea of our address */
+		       try_.ouraddr = ciaddr1;
+		   }
+		   if (go->accept_remote && ciaddr2) {
+		       /* take his idea of his address */
+		       try_.hisaddr = ciaddr2;
+		   }
+	       }
+	);
+
+#if VJ_SUPPORT
+    /*
+     * Accept the peer's value of maxslotindex provided that it
+     * is less than what we asked for.  Turn off slot-ID compression
+     * if the peer wants.  Send old-style compress-type option if
+     * the peer wants.
+     */
+    NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+	    if (treat_as_reject) {
+		try_.neg_vj = 0;
+	    } else if (cilen == CILEN_VJ) {
+		GETCHAR(cimaxslotindex, p);
+		GETCHAR(cicflag, p);
+		if (cishort == IPCP_VJ_COMP) {
+		    try_.old_vj = 0;
+		    if (cimaxslotindex < go->maxslotindex)
+			try_.maxslotindex = cimaxslotindex;
+		    if (!cicflag)
+			try_.cflag = 0;
+		} else {
+		    try_.neg_vj = 0;
+		}
+	    } else {
+		if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+		    try_.old_vj = 1;
+		    try_.vj_protocol = cishort;
+		} else {
+		    try_.neg_vj = 0;
+		}
+	    }
+	    );
+#endif /* VJ_SUPPORT */
+
+    NAKCIADDR(CI_ADDR, neg_addr,
+	      if (treat_as_reject) {
+		  try_.neg_addr = 0;
+		  try_.old_addrs = 0;
+	      } else if (go->accept_local && ciaddr1) {
+		  /* take his idea of our address */
+		  try_.ouraddr = ciaddr1;
+	      }
+	      );
+
+#if LWIP_DNS
+    NAKCIDNS(CI_MS_DNS1, req_dns1,
+	     if (treat_as_reject) {
+		 try_.req_dns1 = 0;
+	     } else {
+		 try_.dnsaddr[0] = cidnsaddr;
+	     }
+	     );
+
+    NAKCIDNS(CI_MS_DNS2, req_dns2,
+	     if (treat_as_reject) {
+		 try_.req_dns2 = 0;
+	     } else {
+		 try_.dnsaddr[1] = cidnsaddr;
+	     }
+	     );
+#endif /* #if LWIP_DNS */
+
+    /*
+     * There may be remaining CIs, if the peer is requesting negotiation
+     * on an option that we didn't include in our request packet.
+     * If they want to negotiate about IP addresses, we comply.
+     * If they want us to ask for compression, we refuse.
+     * If they want us to ask for ms-dns, we do that, since some
+     * peers get huffy if we don't.
+     */
+    while (len >= CILEN_VOID) {
+	GETCHAR(citype, p);
+	GETCHAR(cilen, p);
+	if ( cilen < CILEN_VOID || (len -= cilen) < 0 )
+	    goto bad;
+	next = p + cilen - 2;
+
+	switch (citype) {
+#if VJ_SUPPORT
+	case CI_COMPRESSTYPE:
+	    if (go->neg_vj || no.neg_vj ||
+		(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
+		goto bad;
+	    no.neg_vj = 1;
+	    break;
+#endif /* VJ_SUPPORT */
+	case CI_ADDRS:
+	    if ((!go->neg_addr && go->old_addrs) || no.old_addrs
+		|| cilen != CILEN_ADDRS)
+		goto bad;
+	    try_.neg_addr = 0;
+	    GETLONG(l, p);
+	    ciaddr1 = lwip_htonl(l);
+	    if (ciaddr1 && go->accept_local)
+		try_.ouraddr = ciaddr1;
+	    GETLONG(l, p);
+	    ciaddr2 = lwip_htonl(l);
+	    if (ciaddr2 && go->accept_remote)
+		try_.hisaddr = ciaddr2;
+	    no.old_addrs = 1;
+	    break;
+	case CI_ADDR:
+	    if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
+		goto bad;
+	    try_.old_addrs = 0;
+	    GETLONG(l, p);
+	    ciaddr1 = lwip_htonl(l);
+	    if (ciaddr1 && go->accept_local)
+		try_.ouraddr = ciaddr1;
+	    if (try_.ouraddr != 0)
+		try_.neg_addr = 1;
+	    no.neg_addr = 1;
+	    break;
+#if LWIP_DNS
+	case CI_MS_DNS1:
+	    if (go->req_dns1 || no.req_dns1 || cilen != CILEN_ADDR)
+		goto bad;
+	    GETLONG(l, p);
+	    try_.dnsaddr[0] = lwip_htonl(l);
+	    try_.req_dns1 = 1;
+	    no.req_dns1 = 1;
+	    break;
+	case CI_MS_DNS2:
+	    if (go->req_dns2 || no.req_dns2 || cilen != CILEN_ADDR)
+		goto bad;
+	    GETLONG(l, p);
+	    try_.dnsaddr[1] = lwip_htonl(l);
+	    try_.req_dns2 = 1;
+	    no.req_dns2 = 1;
+	    break;
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+	case CI_MS_WINS1:
+	case CI_MS_WINS2:
+	    if (cilen != CILEN_ADDR)
+		goto bad;
+	    GETLONG(l, p);
+	    ciaddr1 = lwip_htonl(l);
+	    if (ciaddr1)
+		try_.winsaddr[citype == CI_MS_WINS2] = ciaddr1;
+	    break;
+#endif /* UNUSED - WINS */
+	default:
+	    break;
+	}
+	p = next;
+    }
+
+    /*
+     * OK, the Nak is good.  Now we can update state.
+     * If there are any remaining options, we ignore them.
+     */
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+
+    return 1;
+
+bad:
+    IPCPDEBUG(("ipcp_nakci: received bad Nak!"));
+    return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ * Callback from fsm_rconfnakrej.
+ */
+static int ipcp_rejci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+    u_char cilen;
+#if VJ_SUPPORT
+    u_char cimaxslotindex, ciflag;
+    u_short cishort;
+#endif /* VJ_SUPPORT */
+    u32_t cilong;
+    ipcp_options try_;		/* options to request next time */
+
+    try_ = *go;
+    /*
+     * Any Rejected CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define REJCIADDRS(opt, neg, val1, val2) \
+    if ((neg) && \
+	(cilen = p[1]) == CILEN_ADDRS && \
+	len >= cilen && \
+	p[0] == opt) { \
+	u32_t l; \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	/* Check rejected value. */ \
+	if (cilong != val1) \
+	    goto bad; \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	/* Check rejected value. */ \
+	if (cilong != val2) \
+	    goto bad; \
+	try_.old_addrs = 0; \
+    }
+
+#if VJ_SUPPORT
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+    if (go->neg && \
+	p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+	len >= p[1] && \
+	p[0] == opt) { \
+	len -= p[1]; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	/* Check rejected value. */  \
+	if (cishort != val) \
+	    goto bad; \
+	if (!old) { \
+	   GETCHAR(cimaxslotindex, p); \
+	   if (cimaxslotindex != maxslot) \
+	     goto bad; \
+	   GETCHAR(ciflag, p); \
+	   if (ciflag != cflag) \
+	     goto bad; \
+        } \
+	try_.neg = 0; \
+     }
+#endif /* VJ_SUPPORT */
+
+#define REJCIADDR(opt, neg, val) \
+    if (go->neg && \
+	(cilen = p[1]) == CILEN_ADDR && \
+	len >= cilen && \
+	p[0] == opt) { \
+	u32_t l; \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	/* Check rejected value. */ \
+	if (cilong != val) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+
+#if LWIP_DNS
+#define REJCIDNS(opt, neg, dnsaddr) \
+    if (go->neg && \
+	((cilen = p[1]) == CILEN_ADDR) && \
+	len >= cilen && \
+	p[0] == opt) { \
+	u32_t l; \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	/* Check rejected value. */ \
+	if (cilong != dnsaddr) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+#define REJCIWINS(opt, addr) \
+    if (addr && \
+	((cilen = p[1]) == CILEN_ADDR) && \
+	len >= cilen && \
+	p[0] == opt) { \
+	u32_t l; \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETLONG(l, p); \
+	cilong = lwip_htonl(l); \
+	/* Check rejected value. */ \
+	if (cilong != addr) \
+	    goto bad; \
+	try_.winsaddr[opt == CI_MS_WINS2] = 0; \
+    }
+#endif /* UNUSED - WINS */
+
+    REJCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs,
+	       go->ouraddr, go->hisaddr);
+
+#if VJ_SUPPORT
+    REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+	    go->maxslotindex, go->cflag);
+#endif /* VJ_SUPPORT */
+
+    REJCIADDR(CI_ADDR, neg_addr, go->ouraddr);
+
+#if LWIP_DNS
+    REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+    REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+    REJCIWINS(CI_MS_WINS1, go->winsaddr[0]);
+
+    REJCIWINS(CI_MS_WINS2, go->winsaddr[1]);
+#endif /* UNUSED - WINS */
+
+    /*
+     * If there are any remaining CIs, then this packet is bad.
+     */
+    if (len != 0)
+	goto bad;
+    /*
+     * Now we can update state.
+     */
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+    return 1;
+
+bad:
+    IPCPDEBUG(("ipcp_rejci: received bad Reject!"));
+    return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ * Callback from fsm_rconfreq, Receive Configure Request
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ *
+ * inp = Requested CIs
+ * len = Length of requested CIs
+ */
+static int ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *wo = &pcb->ipcp_wantoptions;
+    ipcp_options *ho = &pcb->ipcp_hisoptions;
+    ipcp_options *ao = &pcb->ipcp_allowoptions;
+    u_char *cip, *next;		/* Pointer to current and next CIs */
+    u_short cilen, citype;	/* Parsed len, type */
+#if VJ_SUPPORT
+    u_short cishort;		/* Parsed short value */
+#endif /* VJ_SUPPORT */
+    u32_t tl, ciaddr1, ciaddr2;/* Parsed address values */
+    int rc = CONFACK;		/* Final packet return code */
+    int orc;			/* Individual option return code */
+    u_char *p;			/* Pointer to next char to parse */
+    u_char *ucp = inp;		/* Pointer to current output char */
+    int l = *len;		/* Length left */
+#if VJ_SUPPORT
+    u_char maxslotindex, cflag;
+#endif /* VJ_SUPPORT */
+#if LWIP_DNS
+    int d;
+#endif /* LWIP_DNS */
+
+    /*
+     * Reset all his options.
+     */
+    BZERO(ho, sizeof(*ho));
+    
+    /*
+     * Process all his options.
+     */
+    next = inp;
+    while (l) {
+	orc = CONFACK;			/* Assume success */
+	cip = p = next;			/* Remember begining of CI */
+	if (l < 2 ||			/* Not enough data for CI header or */
+	    p[1] < 2 ||			/*  CI length too small or */
+	    p[1] > l) {			/*  CI length too big? */
+	    IPCPDEBUG(("ipcp_reqci: bad CI length!"));
+	    orc = CONFREJ;		/* Reject bad CI */
+	    cilen = l;			/* Reject till end of packet */
+	    l = 0;			/* Don't loop again */
+	    goto endswitch;
+	}
+	GETCHAR(citype, p);		/* Parse CI type */
+	GETCHAR(cilen, p);		/* Parse CI length */
+	l -= cilen;			/* Adjust remaining length */
+	next += cilen;			/* Step to next CI */
+
+	switch (citype) {		/* Check CI type */
+	case CI_ADDRS:
+	    if (!ao->old_addrs || ho->neg_addr ||
+		cilen != CILEN_ADDRS) {	/* Check CI length */
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+
+	    /*
+	     * If he has no address, or if we both have his address but
+	     * disagree about it, then NAK it with our idea.
+	     * In particular, if we don't know his address, but he does,
+	     * then accept it.
+	     */
+	    GETLONG(tl, p);		/* Parse source address (his) */
+	    ciaddr1 = lwip_htonl(tl);
+	    if (ciaddr1 != wo->hisaddr
+		&& (ciaddr1 == 0 || !wo->accept_remote)) {
+		orc = CONFNAK;
+		if (!reject_if_disagree) {
+		    DECPTR(sizeof(u32_t), p);
+		    tl = lwip_ntohl(wo->hisaddr);
+		    PUTLONG(tl, p);
+		}
+	    } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+		/*
+		 * If neither we nor he knows his address, reject the option.
+		 */
+		orc = CONFREJ;
+		wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+		break;
+	    }
+
+	    /*
+	     * If he doesn't know our address, or if we both have our address
+	     * but disagree about it, then NAK it with our idea.
+	     */
+	    GETLONG(tl, p);		/* Parse desination address (ours) */
+	    ciaddr2 = lwip_htonl(tl);
+	    if (ciaddr2 != wo->ouraddr) {
+		if (ciaddr2 == 0 || !wo->accept_local) {
+		    orc = CONFNAK;
+		    if (!reject_if_disagree) {
+			DECPTR(sizeof(u32_t), p);
+			tl = lwip_ntohl(wo->ouraddr);
+			PUTLONG(tl, p);
+		    }
+		} else {
+		    wo->ouraddr = ciaddr2;	/* accept peer's idea */
+		}
+	    }
+
+	    ho->old_addrs = 1;
+	    ho->hisaddr = ciaddr1;
+	    ho->ouraddr = ciaddr2;
+	    break;
+
+	case CI_ADDR:
+	    if (!ao->neg_addr || ho->old_addrs ||
+		cilen != CILEN_ADDR) {	/* Check CI length */
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+
+	    /*
+	     * If he has no address, or if we both have his address but
+	     * disagree about it, then NAK it with our idea.
+	     * In particular, if we don't know his address, but he does,
+	     * then accept it.
+	     */
+	    GETLONG(tl, p);	/* Parse source address (his) */
+	    ciaddr1 = lwip_htonl(tl);
+	    if (ciaddr1 != wo->hisaddr
+		&& (ciaddr1 == 0 || !wo->accept_remote)) {
+		orc = CONFNAK;
+		if (!reject_if_disagree) {
+		    DECPTR(sizeof(u32_t), p);
+		    tl = lwip_ntohl(wo->hisaddr);
+		    PUTLONG(tl, p);
+		}
+	    } else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+		/*
+		 * Don't ACK an address of 0.0.0.0 - reject it instead.
+		 */
+		orc = CONFREJ;
+		wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+		break;
+	    }
+	
+	    ho->neg_addr = 1;
+	    ho->hisaddr = ciaddr1;
+	    break;
+
+#if LWIP_DNS
+	case CI_MS_DNS1:
+	case CI_MS_DNS2:
+	    /* Microsoft primary or secondary DNS request */
+	    d = citype == CI_MS_DNS2;
+
+	    /* If we do not have a DNS address then we cannot send it */
+	    if (ao->dnsaddr[d] == 0 ||
+		cilen != CILEN_ADDR) {	/* Check CI length */
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+	    GETLONG(tl, p);
+	    if (lwip_htonl(tl) != ao->dnsaddr[d]) {
+                DECPTR(sizeof(u32_t), p);
+		tl = lwip_ntohl(ao->dnsaddr[d]);
+		PUTLONG(tl, p);
+		orc = CONFNAK;
+            }
+            break;
+#endif /* LWIP_DNS */
+
+#if 0 /* UNUSED - WINS */
+	case CI_MS_WINS1:
+	case CI_MS_WINS2:
+	    /* Microsoft primary or secondary WINS request */
+	    d = citype == CI_MS_WINS2;
+
+	    /* If we do not have a DNS address then we cannot send it */
+	    if (ao->winsaddr[d] == 0 ||
+		cilen != CILEN_ADDR) {	/* Check CI length */
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+	    GETLONG(tl, p);
+	    if (lwip_htonl(tl) != ao->winsaddr[d]) {
+                DECPTR(sizeof(u32_t), p);
+		tl = lwip_ntohl(ao->winsaddr[d]);
+		PUTLONG(tl, p);
+		orc = CONFNAK;
+            }
+            break;
+#endif /* UNUSED - WINS */
+
+#if VJ_SUPPORT
+	case CI_COMPRESSTYPE:
+	    if (!ao->neg_vj ||
+		(cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) {
+		orc = CONFREJ;
+		break;
+	    }
+	    GETSHORT(cishort, p);
+
+	    if (!(cishort == IPCP_VJ_COMP ||
+		  (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+		orc = CONFREJ;
+		break;
+	    }
+
+	    ho->neg_vj = 1;
+	    ho->vj_protocol = cishort;
+	    if (cilen == CILEN_VJ) {
+		GETCHAR(maxslotindex, p);
+		if (maxslotindex > ao->maxslotindex) { 
+		    orc = CONFNAK;
+		    if (!reject_if_disagree){
+			DECPTR(1, p);
+			PUTCHAR(ao->maxslotindex, p);
+		    }
+		}
+		GETCHAR(cflag, p);
+		if (cflag && !ao->cflag) {
+		    orc = CONFNAK;
+		    if (!reject_if_disagree){
+			DECPTR(1, p);
+			PUTCHAR(wo->cflag, p);
+		    }
+		}
+		ho->maxslotindex = maxslotindex;
+		ho->cflag = cflag;
+	    } else {
+		ho->old_vj = 1;
+		ho->maxslotindex = MAX_STATES - 1;
+		ho->cflag = 1;
+	    }
+	    break;
+#endif /* VJ_SUPPORT */
+
+	default:
+	    orc = CONFREJ;
+	    break;
+	}
+endswitch:
+	if (orc == CONFACK &&		/* Good CI */
+	    rc != CONFACK)		/*  but prior CI wasnt? */
+	    continue;			/* Don't send this one */
+
+	if (orc == CONFNAK) {		/* Nak this CI? */
+	    if (reject_if_disagree)	/* Getting fed up with sending NAKs? */
+		orc = CONFREJ;		/* Get tough if so */
+	    else {
+		if (rc == CONFREJ)	/* Rejecting prior CI? */
+		    continue;		/* Don't send this one */
+		if (rc == CONFACK) {	/* Ack'd all prior CIs? */
+		    rc = CONFNAK;	/* Not anymore... */
+		    ucp = inp;		/* Backup */
+		}
+	    }
+	}
+
+	if (orc == CONFREJ &&		/* Reject this CI */
+	    rc != CONFREJ) {		/*  but no prior ones? */
+	    rc = CONFREJ;
+	    ucp = inp;			/* Backup */
+	}
+
+	/* Need to move CI? */
+	if (ucp != cip)
+	    MEMCPY(ucp, cip, cilen);	/* Move it */
+
+	/* Update output pointer */
+	INCPTR(cilen, ucp);
+    }
+
+    /*
+     * If we aren't rejecting this packet, and we want to negotiate
+     * their address, and they didn't send their address, then we
+     * send a NAK with a CI_ADDR option appended.  We assume the
+     * input buffer is long enough that we can append the extra
+     * option safely.
+     */
+    if (rc != CONFREJ && !ho->neg_addr && !ho->old_addrs &&
+	wo->req_addr && !reject_if_disagree && !pcb->settings.noremoteip) {
+	if (rc == CONFACK) {
+	    rc = CONFNAK;
+	    ucp = inp;			/* reset pointer */
+	    wo->req_addr = 0;		/* don't ask again */
+	}
+	PUTCHAR(CI_ADDR, ucp);
+	PUTCHAR(CILEN_ADDR, ucp);
+	tl = lwip_ntohl(wo->hisaddr);
+	PUTLONG(tl, ucp);
+    }
+
+    *len = ucp - inp;			/* Compute output length */
+    IPCPDEBUG(("ipcp: returning Configure-%s", CODENAME(rc)));
+    return (rc);			/* Return final code */
+}
+
+
+#if 0 /* UNUSED */
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void
+ip_check_options()
+{
+    struct hostent *hp;
+    u32_t local;
+    ipcp_options *wo = &ipcp_wantoptions[0];
+
+    /*
+     * Default our local IP address based on our hostname.
+     * If local IP address already given, don't bother.
+     */
+    if (wo->ouraddr == 0 && !disable_defaultip) {
+	/*
+	 * Look up our hostname (possibly with domain name appended)
+	 * and take the first IP address as our local IP address.
+	 * If there isn't an IP address for our hostname, too bad.
+	 */
+	wo->accept_local = 1;	/* don't insist on this default value */
+	if ((hp = gethostbyname(hostname)) != NULL) {
+	    local = *(u32_t *)hp->h_addr;
+	    if (local != 0 && !bad_ip_adrs(local))
+		wo->ouraddr = local;
+	}
+    }
+    ask_for_local = wo->ouraddr != 0 || !disable_defaultip;
+}
+#endif /* UNUSED */
+
+#if DEMAND_SUPPORT
+/*
+ * ip_demand_conf - configure the interface as though
+ * IPCP were up, for use with dial-on-demand.
+ */
+static int
+ip_demand_conf(u)
+    int u;
+{
+    ppp_pcb *pcb = &ppp_pcb_list[u];
+    ipcp_options *wo = &ipcp_wantoptions[u];
+
+    if (wo->hisaddr == 0 && !pcb->settings.noremoteip) {
+	/* make up an arbitrary address for the peer */
+	wo->hisaddr = lwip_htonl(0x0a707070 + ifunit);
+	wo->accept_remote = 1;
+    }
+    if (wo->ouraddr == 0) {
+	/* make up an arbitrary address for us */
+	wo->ouraddr = lwip_htonl(0x0a404040 + ifunit);
+	wo->accept_local = 1;
+	ask_for_local = 0;	/* don't tell the peer this address */
+    }
+    if (!sifaddr(pcb, wo->ouraddr, wo->hisaddr, get_mask(wo->ouraddr)))
+	return 0;
+    if (!sifup(pcb))
+	return 0;
+    if (!sifnpmode(pcb, PPP_IP, NPMODE_QUEUE))
+	return 0;
+#if 0 /* UNUSED */
+    if (wo->default_route)
+	if (sifdefaultroute(pcb, wo->ouraddr, wo->hisaddr,
+		wo->replace_default_route))
+	    default_route_set[u] = 1;
+#endif /* UNUSED */
+#if 0 /* UNUSED - PROXY ARP */
+    if (wo->proxy_arp)
+	if (sifproxyarp(pcb, wo->hisaddr))
+	    proxy_arp_set[u] = 1;
+#endif /* UNUSED - PROXY ARP */
+
+    ppp_notice("local  IP address %I", wo->ouraddr);
+    if (wo->hisaddr)
+	ppp_notice("remote IP address %I", wo->hisaddr);
+
+    return 1;
+}
+#endif /* DEMAND_SUPPORT */
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void ipcp_up(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    u32_t mask;
+    ipcp_options *ho = &pcb->ipcp_hisoptions;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+    ipcp_options *wo = &pcb->ipcp_wantoptions;
+
+    IPCPDEBUG(("ipcp: up"));
+
+    /*
+     * We must have a non-zero IP address for both ends of the link.
+     */
+    if (!ho->neg_addr && !ho->old_addrs)
+	ho->hisaddr = wo->hisaddr;
+
+    if (!(go->neg_addr || go->old_addrs) && (wo->neg_addr || wo->old_addrs)
+	&& wo->ouraddr != 0) {
+	ppp_error("Peer refused to agree to our IP address");
+	ipcp_close(f->pcb, "Refused our IP address");
+	return;
+    }
+    if (go->ouraddr == 0) {
+	ppp_error("Could not determine local IP address");
+	ipcp_close(f->pcb, "Could not determine local IP address");
+	return;
+    }
+    if (ho->hisaddr == 0 && !pcb->settings.noremoteip) {
+	ho->hisaddr = lwip_htonl(0x0a404040);
+	ppp_warn("Could not determine remote IP address: defaulting to %I",
+	     ho->hisaddr);
+    }
+#if 0 /* UNUSED */
+    script_setenv("IPLOCAL", ip_ntoa(go->ouraddr), 0);
+    if (ho->hisaddr != 0)
+	script_setenv("IPREMOTE", ip_ntoa(ho->hisaddr), 1);
+#endif /* UNUSED */
+
+#if LWIP_DNS
+    if (!go->req_dns1)
+	    go->dnsaddr[0] = 0;
+    if (!go->req_dns2)
+	    go->dnsaddr[1] = 0;
+#if 0 /* UNUSED */
+    if (go->dnsaddr[0])
+	script_setenv("DNS1", ip_ntoa(go->dnsaddr[0]), 0);
+    if (go->dnsaddr[1])
+	script_setenv("DNS2", ip_ntoa(go->dnsaddr[1]), 0);
+#endif /* UNUSED */
+    if (pcb->settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+	sdns(pcb, go->dnsaddr[0], go->dnsaddr[1]);
+#if 0 /* UNUSED */
+	script_setenv("USEPEERDNS", "1", 0);
+	create_resolv(go->dnsaddr[0], go->dnsaddr[1]);
+#endif /* UNUSED */
+    }
+#endif /* LWIP_DNS */
+
+    /*
+     * Check that the peer is allowed to use the IP address it wants.
+     */
+    if (ho->hisaddr != 0) {
+	u32_t addr = lwip_ntohl(ho->hisaddr);
+	if ((addr >> IP_CLASSA_NSHIFT) == IP_LOOPBACKNET
+	    || IP_MULTICAST(addr) || IP_BADCLASS(addr)
+	    /*
+	     * For now, consider that PPP in server mode with peer required
+	     * to authenticate must provide the peer IP address, reject any
+	     * IP address wanted by peer different than the one we wanted.
+	     */
+#if PPP_SERVER && PPP_AUTH_SUPPORT
+	    || (pcb->settings.auth_required && wo->hisaddr != ho->hisaddr)
+#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */
+	    ) {
+		ppp_error("Peer is not authorized to use remote address %I", ho->hisaddr);
+		ipcp_close(pcb, "Unauthorized remote IP address");
+		return;
+	}
+    }
+#if 0 /* Unused */
+    /* Upstream checking code */
+    if (ho->hisaddr != 0 && !auth_ip_addr(f->unit, ho->hisaddr)) {
+	ppp_error("Peer is not authorized to use remote address %I", ho->hisaddr);
+	ipcp_close(f->unit, "Unauthorized remote IP address");
+	return;
+    }
+#endif /* Unused */
+
+#if VJ_SUPPORT
+    /* set tcp compression */
+    sifvjcomp(pcb, ho->neg_vj, ho->cflag, ho->maxslotindex);
+#endif /* VJ_SUPPORT */
+
+#if DEMAND_SUPPORT
+    /*
+     * If we are doing dial-on-demand, the interface is already
+     * configured, so we put out any saved-up packets, then set the
+     * interface to pass IP packets.
+     */
+    if (demand) {
+	if (go->ouraddr != wo->ouraddr || ho->hisaddr != wo->hisaddr) {
+	    ipcp_clear_addrs(f->unit, wo->ouraddr, wo->hisaddr,
+				      wo->replace_default_route);
+	    if (go->ouraddr != wo->ouraddr) {
+		ppp_warn("Local IP address changed to %I", go->ouraddr);
+		script_setenv("OLDIPLOCAL", ip_ntoa(wo->ouraddr), 0);
+		wo->ouraddr = go->ouraddr;
+	    } else
+		script_unsetenv("OLDIPLOCAL");
+	    if (ho->hisaddr != wo->hisaddr && wo->hisaddr != 0) {
+		ppp_warn("Remote IP address changed to %I", ho->hisaddr);
+		script_setenv("OLDIPREMOTE", ip_ntoa(wo->hisaddr), 0);
+		wo->hisaddr = ho->hisaddr;
+	    } else
+		script_unsetenv("OLDIPREMOTE");
+
+	    /* Set the interface to the new addresses */
+	    mask = get_mask(go->ouraddr);
+	    if (!sifaddr(pcb, go->ouraddr, ho->hisaddr, mask)) {
+#if PPP_DEBUG
+		ppp_warn("Interface configuration failed");
+#endif /* PPP_DEBUG */
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	    }
+
+	    /* assign a default route through the interface if required */
+	    if (ipcp_wantoptions[f->unit].default_route) 
+		if (sifdefaultroute(pcb, go->ouraddr, ho->hisaddr,
+			wo->replace_default_route))
+		    default_route_set[f->unit] = 1;
+
+#if 0 /* UNUSED - PROXY ARP */
+	    /* Make a proxy ARP entry if requested. */
+	    if (ho->hisaddr != 0 && ipcp_wantoptions[f->unit].proxy_arp)
+		if (sifproxyarp(pcb, ho->hisaddr))
+		    proxy_arp_set[f->unit] = 1;
+#endif /* UNUSED - PROXY ARP */
+
+	}
+	demand_rexmit(PPP_IP,go->ouraddr);
+	sifnpmode(pcb, PPP_IP, NPMODE_PASS);
+
+    } else
+#endif /* DEMAND_SUPPORT */
+    {
+	/*
+	 * Set IP addresses and (if specified) netmask.
+	 */
+	mask = get_mask(go->ouraddr);
+
+#if !(defined(SVR4) && (defined(SNI) || defined(__USLC__)))
+	if (!sifaddr(pcb, go->ouraddr, ho->hisaddr, mask)) {
+#if PPP_DEBUG
+	    ppp_warn("Interface configuration failed");
+#endif /* PPP_DEBUG */
+	    ipcp_close(f->pcb, "Interface configuration failed");
+	    return;
+	}
+#endif
+
+	/* bring the interface up for IP */
+	if (!sifup(pcb)) {
+#if PPP_DEBUG
+	    ppp_warn("Interface failed to come up");
+#endif /* PPP_DEBUG */
+	    ipcp_close(f->pcb, "Interface configuration failed");
+	    return;
+	}
+
+#if (defined(SVR4) && (defined(SNI) || defined(__USLC__)))
+	if (!sifaddr(pcb, go->ouraddr, ho->hisaddr, mask)) {
+#if PPP_DEBUG
+	    ppp_warn("Interface configuration failed");
+#endif /* PPP_DEBUG */
+	    ipcp_close(f->unit, "Interface configuration failed");
+	    return;
+	}
+#endif
+#if DEMAND_SUPPORT
+	sifnpmode(pcb, PPP_IP, NPMODE_PASS);
+#endif /* DEMAND_SUPPORT */
+
+#if 0 /* UNUSED */
+	/* assign a default route through the interface if required */
+	if (wo->default_route)
+	    if (sifdefaultroute(pcb, go->ouraddr, ho->hisaddr,
+		    wo->replace_default_route))
+		    pcb->default_route_set = 1;
+#endif /* UNUSED */
+
+#if 0 /* UNUSED - PROXY ARP */
+	/* Make a proxy ARP entry if requested. */
+	if (ho->hisaddr != 0 && wo->proxy_arp)
+	    if (sifproxyarp(pcb, ho->hisaddr))
+		pcb->proxy_arp_set = 1;
+#endif /* UNUSED - PROXY ARP */
+
+	wo->ouraddr = go->ouraddr;
+
+	ppp_notice("local  IP address %I", go->ouraddr);
+	if (ho->hisaddr != 0)
+	    ppp_notice("remote IP address %I", ho->hisaddr);
+#if LWIP_DNS
+	if (go->dnsaddr[0])
+	    ppp_notice("primary   DNS address %I", go->dnsaddr[0]);
+	if (go->dnsaddr[1])
+	    ppp_notice("secondary DNS address %I", go->dnsaddr[1]);
+#endif /* LWIP_DNS */
+    }
+
+#if PPP_STATS_SUPPORT
+    reset_link_stats(f->unit);
+#endif /* PPP_STATS_SUPPORT */
+
+    np_up(pcb, PPP_IP);
+    pcb->ipcp_is_up = 1;
+
+#if PPP_NOTIFY
+    notify(ip_up_notifier, 0);
+#endif /* PPP_NOTIFY */
+#if 0 /* UNUSED */
+    if (ip_up_hook)
+	ip_up_hook();
+#endif /* UNUSED */
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipcp_down(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipcp_options *ho = &pcb->ipcp_hisoptions;
+    ipcp_options *go = &pcb->ipcp_gotoptions;
+
+    IPCPDEBUG(("ipcp: down"));
+#if PPP_STATS_SUPPORT
+    /* XXX a bit IPv4-centric here, we only need to get the stats
+     * before the interface is marked down. */
+    /* XXX more correct: we must get the stats before running the notifiers,
+     * at least for the radius plugin */
+    update_link_stats(f->unit);
+#endif /* PPP_STATS_SUPPORT */
+#if PPP_NOTIFY
+    notify(ip_down_notifier, 0);
+#endif /* PPP_NOTIFY */
+#if 0 /* UNUSED */
+    if (ip_down_hook)
+	ip_down_hook();
+#endif /* UNUSED */
+    if (pcb->ipcp_is_up) {
+	pcb->ipcp_is_up = 0;
+	np_down(pcb, PPP_IP);
+    }
+#if VJ_SUPPORT
+    sifvjcomp(pcb, 0, 0, 0);
+#endif /* VJ_SUPPORT */
+
+#if PPP_STATS_SUPPORT
+    print_link_stats(); /* _after_ running the notifiers and ip_down_hook(),
+			 * because print_link_stats() sets link_stats_valid
+			 * to 0 (zero) */
+#endif /* PPP_STATS_SUPPORT */
+
+#if DEMAND_SUPPORT
+    /*
+     * If we are doing dial-on-demand, set the interface
+     * to queue up outgoing packets (for now).
+     */
+    if (demand) {
+	sifnpmode(pcb, PPP_IP, NPMODE_QUEUE);
+    } else
+#endif /* DEMAND_SUPPORT */
+    {
+#if DEMAND_SUPPORT
+	sifnpmode(pcb, PPP_IP, NPMODE_DROP);
+#endif /* DEMAND_SUPPORT */
+	sifdown(pcb);
+	ipcp_clear_addrs(pcb, go->ouraddr,
+			 ho->hisaddr, 0);
+#if LWIP_DNS
+	cdns(pcb, go->dnsaddr[0], go->dnsaddr[1]);
+#endif /* LWIP_DNS */
+    }
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes,
+ * proxy arp entries, etc.
+ */
+static void ipcp_clear_addrs(ppp_pcb *pcb, u32_t ouraddr, u32_t hisaddr, u8_t replacedefaultroute) {
+    LWIP_UNUSED_ARG(replacedefaultroute);
+
+#if 0 /* UNUSED - PROXY ARP */
+    if (pcb->proxy_arp_set) {
+	cifproxyarp(pcb, hisaddr);
+	pcb->proxy_arp_set = 0;
+    }
+#endif /* UNUSED - PROXY ARP */
+#if 0 /* UNUSED */
+    /* If replacedefaultroute, sifdefaultroute will be called soon
+     * with replacedefaultroute set and that will overwrite the current
+     * default route. This is the case only when doing demand, otherwise
+     * during demand, this cifdefaultroute would restore the old default
+     * route which is not what we want in this case. In the non-demand
+     * case, we'll delete the default route and restore the old if there
+     * is one saved by an sifdefaultroute with replacedefaultroute.
+     */
+    if (!replacedefaultroute && pcb->default_route_set) {
+	cifdefaultroute(pcb, ouraddr, hisaddr);
+	pcb->default_route_set = 0;
+    }
+#endif /* UNUSED */
+    cifaddr(pcb, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void ipcp_finished(fsm *f) {
+	ppp_pcb *pcb = f->pcb;
+	if (pcb->ipcp_is_open) {
+		pcb->ipcp_is_open = 0;
+		np_finished(pcb, PPP_IP);
+	}
+}
+
+
+#if 0 /* UNUSED */
+/*
+ * create_resolv - create the replacement resolv.conf file
+ */
+static void
+create_resolv(peerdns1, peerdns2)
+    u32_t peerdns1, peerdns2;
+{
+
+}
+#endif /* UNUSED */
+
+#if PRINTPKT_SUPPORT
+/*
+ * ipcp_printpkt - print the contents of an IPCP packet.
+ */
+static const char* const ipcp_codenames[] = {
+    "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+    "TermReq", "TermAck", "CodeRej"
+};
+
+static int ipcp_printpkt(const u_char *p, int plen,
+		void (*printer) (void *, const char *, ...), void *arg) {
+    int code, id, len, olen;
+    const u_char *pstart, *optend;
+#if VJ_SUPPORT
+    u_short cishort;
+#endif /* VJ_SUPPORT */
+    u32_t cilong;
+
+    if (plen < HEADERLEN)
+	return 0;
+    pstart = p;
+    GETCHAR(code, p);
+    GETCHAR(id, p);
+    GETSHORT(len, p);
+    if (len < HEADERLEN || len > plen)
+	return 0;
+
+    if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(ipcp_codenames))
+	printer(arg, " %s", ipcp_codenames[code-1]);
+    else
+	printer(arg, " code=0x%x", code);
+    printer(arg, " id=0x%x", id);
+    len -= HEADERLEN;
+    switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+	/* print option list */
+	while (len >= 2) {
+	    GETCHAR(code, p);
+	    GETCHAR(olen, p);
+	    p -= 2;
+	    if (olen < 2 || olen > len) {
+		break;
+	    }
+	    printer(arg, " <");
+	    len -= olen;
+	    optend = p + olen;
+	    switch (code) {
+	    case CI_ADDRS:
+		if (olen == CILEN_ADDRS) {
+		    p += 2;
+		    GETLONG(cilong, p);
+		    printer(arg, "addrs %I", lwip_htonl(cilong));
+		    GETLONG(cilong, p);
+		    printer(arg, " %I", lwip_htonl(cilong));
+		}
+		break;
+#if VJ_SUPPORT
+	    case CI_COMPRESSTYPE:
+		if (olen >= CILEN_COMPRESS) {
+		    p += 2;
+		    GETSHORT(cishort, p);
+		    printer(arg, "compress ");
+		    switch (cishort) {
+		    case IPCP_VJ_COMP:
+			printer(arg, "VJ");
+			break;
+		    case IPCP_VJ_COMP_OLD:
+			printer(arg, "old-VJ");
+			break;
+		    default:
+			printer(arg, "0x%x", cishort);
+		    }
+		}
+		break;
+#endif /* VJ_SUPPORT */
+	    case CI_ADDR:
+		if (olen == CILEN_ADDR) {
+		    p += 2;
+		    GETLONG(cilong, p);
+		    printer(arg, "addr %I", lwip_htonl(cilong));
+		}
+		break;
+#if LWIP_DNS
+	    case CI_MS_DNS1:
+	    case CI_MS_DNS2:
+	        p += 2;
+		GETLONG(cilong, p);
+		printer(arg, "ms-dns%d %I", (code == CI_MS_DNS1? 1: 2),
+			htonl(cilong));
+		break;
+#endif /* LWIP_DNS */
+#if 0 /* UNUSED - WINS */
+	    case CI_MS_WINS1:
+	    case CI_MS_WINS2:
+	        p += 2;
+		GETLONG(cilong, p);
+		printer(arg, "ms-wins %I", lwip_htonl(cilong));
+		break;
+#endif /* UNUSED - WINS */
+	    default:
+		break;
+	    }
+	    while (p < optend) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	    }
+	    printer(arg, ">");
+	}
+	break;
+
+    case TERMACK:
+    case TERMREQ:
+	if (len > 0 && *p >= ' ' && *p < 0x7f) {
+	    printer(arg, " ");
+	    ppp_print_string(p, len, printer, arg);
+	    p += len;
+	    len = 0;
+	}
+	break;
+    default:
+	break;
+    }
+
+    /* print the rest of the bytes in the packet */
+    for (; len > 0; --len) {
+	GETCHAR(code, p);
+	printer(arg, " %.2x", code);
+    }
+
+    return p - pstart;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#if DEMAND_SUPPORT
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN	20	/* bytes */
+#define IP_OFFMASK	0x1fff
+#ifndef IPPROTO_TCP
+#define IPPROTO_TCP	6
+#endif
+#define TCP_HDRLEN	20
+#define TH_FIN		0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)	(((x)[0] << 8) + (x)[1])
+#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)	(((unsigned char *)(x))[9])
+#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x)	(((unsigned char *)(x))[13])
+
+static int
+ip_active_pkt(pkt, len)
+    u_char *pkt;
+    int len;
+{
+    u_char *tcp;
+    int hlen;
+
+    len -= PPP_HDRLEN;
+    pkt += PPP_HDRLEN;
+    if (len < IP_HDRLEN)
+	return 0;
+    if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
+	return 0;
+    if (get_ipproto(pkt) != IPPROTO_TCP)
+	return 1;
+    hlen = get_iphl(pkt) * 4;
+    if (len < hlen + TCP_HDRLEN)
+	return 0;
+    tcp = pkt + hlen;
+    if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
+	return 0;
+    return 1;
+}
+#endif /* DEMAND_SUPPORT */
+
+#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ipv6cp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ipv6cp.c
new file mode 100644
index 000000000..11c18df74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ipv6cp.c
@@ -0,0 +1,1533 @@
+/*
+ * ipv6cp.c - PPP IPV6 Control Protocol.
+ *
+ * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Tommi Komulainen
+ *     <Tommi.Komulainen@iki.fi>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/*  Original version, based on RFC2023 :
+
+    Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt,
+    Alain.Durand@imag.fr, IMAG,
+    Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+    Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE,
+    Alain.Durand@imag.fr, IMAG,
+    Jean-Luc.Richier@imag.fr, IMAG-LSR.
+
+    Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt
+    Économique ayant pour membres BULL S.A. et l'INRIA).
+
+    Ce logiciel informatique est disponible aux conditions
+    usuelles dans la recherche, c'est-à-dire qu'il peut
+    être utilisé, copié, modifié, distribué à l'unique
+    condition que ce texte soit conservé afin que
+    l'origine de ce logiciel soit reconnue.
+
+    Le nom de l'Institut National de Recherche en Informatique
+    et en Automatique (INRIA), de l'IMAG, ou d'une personne morale
+    ou physique ayant participé à l'élaboration de ce logiciel ne peut
+    être utilisé sans son accord préalable explicite.
+
+    Ce logiciel est fourni tel quel sans aucune garantie,
+    support ou responsabilité d'aucune sorte.
+    Ce logiciel est dérivé de sources d'origine
+    "University of California at Berkeley" et
+    "Digital Equipment Corporation" couvertes par des copyrights.
+
+    L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG)
+    est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National
+    Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant
+    sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR).
+
+    This work has been done in the context of GIE DYADE (joint R & D venture
+    between BULL S.A. and INRIA).
+
+    This software is available with usual "research" terms
+    with the aim of retain credits of the software. 
+    Permission to use, copy, modify and distribute this software for any
+    purpose and without fee is hereby granted, provided that the above
+    copyright notice and this permission notice appear in all copies,
+    and the name of INRIA, IMAG, or any contributor not be used in advertising
+    or publicity pertaining to this material without the prior explicit
+    permission. The software is provided "as is" without any
+    warranties, support or liabilities of any kind.
+    This software is derived from source code from
+    "University of California at Berkeley" and
+    "Digital Equipment Corporation" protected by copyrights.
+
+    Grenoble's Institute of Computer Science and Applied Mathematics (IMAG)
+    is a federation of seven research units funded by the CNRS, National
+    Polytechnic Institute of Grenoble and University Joseph Fourier.
+    The research unit in Software, Systems, Networks (LSR) is member of IMAG.
+*/
+
+/*
+ * Derived from :
+ *
+ *
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ipv6cp.c,v 1.21 2005/08/25 23:59:34 paulus Exp $ 
+ */
+
+/*
+ * @todo: 
+ *
+ * Proxy Neighbour Discovery.
+ *
+ * Better defines for selecting the ordering of
+ *   interface up / set address.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <netdb.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/ipcp.h"
+#include "netif/ppp/ipv6cp.h"
+#include "netif/ppp/magic.h"
+
+/* global vars */
+#if 0 /* UNUSED */
+int no_ifaceid_neg = 0;
+#endif /* UNUSED */
+
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipv6cp_resetci(fsm *f); /* Reset our CI */
+static int  ipv6cp_cilen(fsm *f); /* Return length of our CI */
+static void ipv6cp_addci(fsm *f, u_char *ucp, int *lenp); /* Add our CI */
+static int  ipv6cp_ackci(fsm *f, u_char *p, int len); /* Peer ack'd our CI */
+static int  ipv6cp_nakci(fsm *f, u_char *p, int len, int treat_as_reject); /* Peer nak'd our CI */
+static int  ipv6cp_rejci(fsm *f, u_char *p, int len); /* Peer rej'd our CI */
+static int  ipv6cp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree); /* Rcv CI */
+static void ipv6cp_up(fsm *f); /* We're UP */
+static void ipv6cp_down(fsm *f); /* We're DOWN */
+static void ipv6cp_finished(fsm *f); /* Don't need lower layer */
+
+static const fsm_callbacks ipv6cp_callbacks = { /* IPV6CP callback routines */
+    ipv6cp_resetci,		/* Reset our Configuration Information */
+    ipv6cp_cilen,		/* Length of our Configuration Information */
+    ipv6cp_addci,		/* Add our Configuration Information */
+    ipv6cp_ackci,		/* ACK our Configuration Information */
+    ipv6cp_nakci,		/* NAK our Configuration Information */
+    ipv6cp_rejci,		/* Reject our Configuration Information */
+    ipv6cp_reqci,		/* Request peer's Configuration Information */
+    ipv6cp_up,			/* Called when fsm reaches OPENED state */
+    ipv6cp_down,		/* Called when fsm leaves OPENED state */
+    NULL,			/* Called when we want the lower layer up */
+    ipv6cp_finished,		/* Called when we want the lower layer down */
+    NULL,			/* Called when Protocol-Reject received */
+    NULL,			/* Retransmission is necessary */
+    NULL,			/* Called to handle protocol-specific codes */
+    "IPV6CP"			/* String name of protocol */
+};
+
+#if PPP_OPTIONS
+/*
+ * Command-line options.
+ */
+static int setifaceid(char **arg));
+static void printifaceid(option_t *,
+			      void (*)(void *, char *, ...), void *));
+
+static option_t ipv6cp_option_list[] = {
+    { "ipv6", o_special, (void *)setifaceid,
+      "Set interface identifiers for IPV6",
+      OPT_A2PRINTER, (void *)printifaceid },
+
+    { "+ipv6", o_bool, &ipv6cp_protent.enabled_flag,
+      "Enable IPv6 and IPv6CP", OPT_PRIO | 1 },
+    { "noipv6", o_bool, &ipv6cp_protent.enabled_flag,
+      "Disable IPv6 and IPv6CP", OPT_PRIOSUB },
+    { "-ipv6", o_bool, &ipv6cp_protent.enabled_flag,
+      "Disable IPv6 and IPv6CP", OPT_PRIOSUB | OPT_ALIAS },
+
+    { "ipv6cp-accept-local", o_bool, &ipv6cp_allowoptions[0].accept_local,
+      "Accept peer's interface identifier for us", 1 },
+
+    { "ipv6cp-use-ipaddr", o_bool, &ipv6cp_allowoptions[0].use_ip,
+      "Use (default) IPv4 address as interface identifier", 1 },
+
+    { "ipv6cp-use-persistent", o_bool, &ipv6cp_wantoptions[0].use_persistent,
+      "Use uniquely-available persistent value for link local address", 1 },
+
+    { "ipv6cp-restart", o_int, &ipv6cp_fsm[0].timeouttime,
+      "Set timeout for IPv6CP", OPT_PRIO },
+    { "ipv6cp-max-terminate", o_int, &ipv6cp_fsm[0].maxtermtransmits,
+      "Set max #xmits for term-reqs", OPT_PRIO },
+    { "ipv6cp-max-configure", o_int, &ipv6cp_fsm[0].maxconfreqtransmits,
+      "Set max #xmits for conf-reqs", OPT_PRIO },
+    { "ipv6cp-max-failure", o_int, &ipv6cp_fsm[0].maxnakloops,
+      "Set max #conf-naks for IPv6CP", OPT_PRIO },
+
+   { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipv6cp_init(ppp_pcb *pcb);
+static void ipv6cp_open(ppp_pcb *pcb);
+static void ipv6cp_close(ppp_pcb *pcb, const char *reason);
+static void ipv6cp_lowerup(ppp_pcb *pcb);
+static void ipv6cp_lowerdown(ppp_pcb *pcb);
+static void ipv6cp_input(ppp_pcb *pcb, u_char *p, int len);
+static void ipv6cp_protrej(ppp_pcb *pcb);
+#if PPP_OPTIONS
+static void ipv6_check_options(void);
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+static int  ipv6_demand_conf(int u);
+#endif /* DEMAND_SUPPORT */
+#if PRINTPKT_SUPPORT
+static int ipv6cp_printpkt(const u_char *p, int plen,
+		void (*printer)(void *, const char *, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+#if DEMAND_SUPPORT
+static int ipv6_active_pkt(u_char *pkt, int len);
+#endif /* DEMAND_SUPPORT */
+
+const struct protent ipv6cp_protent = {
+    PPP_IPV6CP,
+    ipv6cp_init,
+    ipv6cp_input,
+    ipv6cp_protrej,
+    ipv6cp_lowerup,
+    ipv6cp_lowerdown,
+    ipv6cp_open,
+    ipv6cp_close,
+#if PRINTPKT_SUPPORT
+    ipv6cp_printpkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    NULL,
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    "IPV6CP",
+    "IPV6",
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    ipv6cp_option_list,
+    ipv6_check_options,
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    ipv6_demand_conf,
+    ipv6_active_pkt
+#endif /* DEMAND_SUPPORT */
+};
+
+static void ipv6cp_clear_addrs(ppp_pcb *pcb, eui64_t ourid, eui64_t hisid);
+#if 0 /* UNUSED */
+static void ipv6cp_script(char *));
+static void ipv6cp_script_done(void *));
+#endif /* UNUSED */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID	2
+#define CILEN_COMPRESS	4	/* length for RFC2023 compress opt. */
+#define CILEN_IFACEID   10	/* RFC2472, interface identifier    */
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+#if 0 /* UNUSED */
+/*
+ * This state variable is used to ensure that we don't
+ * run an ipcp-up/down script while one is already running.
+ */
+static enum script_state {
+    s_down,
+    s_up,
+} ipv6cp_script_state;
+static pid_t ipv6cp_script_pid;
+#endif /* UNUSED */
+
+static char *llv6_ntoa(eui64_t ifaceid);
+
+#if PPP_OPTIONS
+/*
+ * setifaceid - set the interface identifiers manually
+ */
+static int
+setifaceid(argv)
+    char **argv;
+{
+    char *comma, *arg, c;
+    ipv6cp_options *wo = &ipv6cp_wantoptions[0];
+    struct in6_addr addr;
+    static int prio_local, prio_remote;
+
+#define VALIDID(a) ( (((a).s6_addr32[0] == 0) && ((a).s6_addr32[1] == 0)) && \
+			(((a).s6_addr32[2] != 0) || ((a).s6_addr32[3] != 0)) )
+    
+    arg = *argv;
+    if ((comma = strchr(arg, ',')) == NULL)
+	comma = arg + strlen(arg);
+    
+    /* 
+     * If comma first character, then no local identifier
+     */
+    if (comma != arg) {
+	c = *comma;
+	*comma = '\0';
+
+	if (inet_pton(AF_INET6, arg, &addr) == 0 || !VALIDID(addr)) {
+	    option_error("Illegal interface identifier (local): %s", arg);
+	    return 0;
+	}
+
+	if (option_priority >= prio_local) {
+	    eui64_copy(addr.s6_addr32[2], wo->ourid);
+	    wo->opt_local = 1;
+	    prio_local = option_priority;
+	}
+	*comma = c;
+    }
+    
+    /*
+     * If comma last character, the no remote identifier
+     */
+    if (*comma != 0 && *++comma != '\0') {
+	if (inet_pton(AF_INET6, comma, &addr) == 0 || !VALIDID(addr)) {
+	    option_error("Illegal interface identifier (remote): %s", comma);
+	    return 0;
+	}
+	if (option_priority >= prio_remote) {
+	    eui64_copy(addr.s6_addr32[2], wo->hisid);
+	    wo->opt_remote = 1;
+	    prio_remote = option_priority;
+	}
+    }
+
+    if (override_value("+ipv6", option_priority, option_source))
+	ipv6cp_protent.enabled_flag = 1;
+    return 1;
+}
+
+static void
+printifaceid(opt, printer, arg)
+    option_t *opt;
+    void (*printer)(void *, char *, ...));
+    void *arg;
+{
+	ipv6cp_options *wo = &ipv6cp_wantoptions[0];
+
+	if (wo->opt_local)
+		printer(arg, "%s", llv6_ntoa(wo->ourid));
+	printer(arg, ",");
+	if (wo->opt_remote)
+		printer(arg, "%s", llv6_ntoa(wo->hisid));
+}
+#endif /* PPP_OPTIONS */
+
+/*
+ * Make a string representation of a network address.
+ */
+static char *
+llv6_ntoa(eui64_t ifaceid)
+{
+    static char b[26];
+
+    sprintf(b, "fe80::%02x%02x:%02x%02x:%02x%02x:%02x%02x",
+      ifaceid.e8[0], ifaceid.e8[1], ifaceid.e8[2], ifaceid.e8[3],
+      ifaceid.e8[4], ifaceid.e8[5], ifaceid.e8[6], ifaceid.e8[7]);
+
+    return b;
+}
+
+
+/*
+ * ipv6cp_init - Initialize IPV6CP.
+ */
+static void ipv6cp_init(ppp_pcb *pcb) {
+    fsm *f = &pcb->ipv6cp_fsm;
+    ipv6cp_options *wo = &pcb->ipv6cp_wantoptions;
+    ipv6cp_options *ao = &pcb->ipv6cp_allowoptions;
+
+    f->pcb = pcb;
+    f->protocol = PPP_IPV6CP;
+    f->callbacks = &ipv6cp_callbacks;
+    fsm_init(f);
+
+#if 0 /* Not necessary, everything is cleared in ppp_new() */
+    memset(wo, 0, sizeof(*wo));
+    memset(ao, 0, sizeof(*ao));
+#endif /* 0 */
+
+    wo->accept_local = 1;
+    wo->neg_ifaceid = 1;
+    ao->neg_ifaceid = 1;
+
+#ifdef IPV6CP_COMP
+    wo->neg_vj = 1;
+    ao->neg_vj = 1;
+    wo->vj_protocol = IPV6CP_COMP;
+#endif
+
+}
+
+
+/*
+ * ipv6cp_open - IPV6CP is allowed to come up.
+ */
+static void ipv6cp_open(ppp_pcb *pcb) {
+    fsm_open(&pcb->ipv6cp_fsm);
+}
+
+
+/*
+ * ipv6cp_close - Take IPV6CP down.
+ */
+static void ipv6cp_close(ppp_pcb *pcb, const char *reason) {
+    fsm_close(&pcb->ipv6cp_fsm, reason);
+}
+
+
+/*
+ * ipv6cp_lowerup - The lower layer is up.
+ */
+static void ipv6cp_lowerup(ppp_pcb *pcb) {
+    fsm_lowerup(&pcb->ipv6cp_fsm);
+}
+
+
+/*
+ * ipv6cp_lowerdown - The lower layer is down.
+ */
+static void ipv6cp_lowerdown(ppp_pcb *pcb) {
+    fsm_lowerdown(&pcb->ipv6cp_fsm);
+}
+
+
+/*
+ * ipv6cp_input - Input IPV6CP packet.
+ */
+static void ipv6cp_input(ppp_pcb *pcb, u_char *p, int len) {
+    fsm_input(&pcb->ipv6cp_fsm, p, len);
+}
+
+
+/*
+ * ipv6cp_protrej - A Protocol-Reject was received for IPV6CP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipv6cp_protrej(ppp_pcb *pcb) {
+    fsm_lowerdown(&pcb->ipv6cp_fsm);
+}
+
+
+/*
+ * ipv6cp_resetci - Reset our CI.
+ */
+static void ipv6cp_resetci(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *wo = &pcb->ipv6cp_wantoptions;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    ipv6cp_options *ao = &pcb->ipv6cp_allowoptions;
+
+    wo->req_ifaceid = wo->neg_ifaceid && ao->neg_ifaceid;
+    
+    if (!wo->opt_local) {
+	eui64_magic_nz(wo->ourid);
+    }
+    
+    *go = *wo;
+    eui64_zero(go->hisid);	/* last proposed interface identifier */
+}
+
+
+/*
+ * ipv6cp_cilen - Return length of our CI.
+ */
+static int ipv6cp_cilen(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+
+#ifdef IPV6CP_COMP
+#define LENCIVJ(neg)		(neg ? CILEN_COMPRESS : 0)
+#endif /* IPV6CP_COMP */
+#define LENCIIFACEID(neg)	(neg ? CILEN_IFACEID : 0)
+
+    return (LENCIIFACEID(go->neg_ifaceid) +
+#ifdef IPV6CP_COMP
+	    LENCIVJ(go->neg_vj) +
+#endif /* IPV6CP_COMP */
+	    0);
+}
+
+
+/*
+ * ipv6cp_addci - Add our desired CIs to a packet.
+ */
+static void ipv6cp_addci(fsm *f, u_char *ucp, int *lenp) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    int len = *lenp;
+
+#ifdef IPV6CP_COMP
+#define ADDCIVJ(opt, neg, val) \
+    if (neg) { \
+	int vjlen = CILEN_COMPRESS; \
+	if (len >= vjlen) { \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(vjlen, ucp); \
+	    PUTSHORT(val, ucp); \
+	    len -= vjlen; \
+	} else \
+	    neg = 0; \
+    }
+#endif /* IPV6CP_COMP */
+
+#define ADDCIIFACEID(opt, neg, val1) \
+    if (neg) { \
+	int idlen = CILEN_IFACEID; \
+	if (len >= idlen) { \
+	    PUTCHAR(opt, ucp); \
+	    PUTCHAR(idlen, ucp); \
+	    eui64_put(val1, ucp); \
+	    len -= idlen; \
+	} else \
+	    neg = 0; \
+    }
+
+    ADDCIIFACEID(CI_IFACEID, go->neg_ifaceid, go->ourid);
+
+#ifdef IPV6CP_COMP
+    ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol);
+#endif /* IPV6CP_COMP */
+
+    *lenp -= len;
+}
+
+
+/*
+ * ipv6cp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int ipv6cp_ackci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    u_short cilen, citype;
+#ifdef IPV6CP_COMP
+    u_short cishort;
+#endif /* IPV6CP_COMP */
+    eui64_t ifaceid;
+
+    /*
+     * CIs must be in exactly the same order that we sent...
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+
+#ifdef IPV6CP_COMP
+#define ACKCIVJ(opt, neg, val) \
+    if (neg) { \
+	int vjlen = CILEN_COMPRESS; \
+	if ((len -= vjlen) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != vjlen || \
+	    citype != opt)  \
+	    goto bad; \
+	GETSHORT(cishort, p); \
+	if (cishort != val) \
+	    goto bad; \
+    }
+#endif /* IPV6CP_COMP */
+
+#define ACKCIIFACEID(opt, neg, val1) \
+    if (neg) { \
+	int idlen = CILEN_IFACEID; \
+	if ((len -= idlen) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != idlen || \
+	    citype != opt) \
+	    goto bad; \
+	eui64_get(ifaceid, p); \
+	if (! eui64_equals(val1, ifaceid)) \
+	    goto bad; \
+    }
+
+    ACKCIIFACEID(CI_IFACEID, go->neg_ifaceid, go->ourid);
+
+#ifdef IPV6CP_COMP
+    ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol);
+#endif /* IPV6CP_COMP */
+
+    /*
+     * If there are any remaining CIs, then this packet is bad.
+     */
+    if (len != 0)
+	goto bad;
+    return (1);
+
+bad:
+    IPV6CPDEBUG(("ipv6cp_ackci: received bad Ack!"));
+    return (0);
+}
+
+/*
+ * ipv6cp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPV6CP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int ipv6cp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    u_char citype, cilen, *next;
+#ifdef IPV6CP_COMP
+    u_short cishort;
+#endif /* IPV6CP_COMP */
+    eui64_t ifaceid;
+    ipv6cp_options no;		/* options we've seen Naks for */
+    ipv6cp_options try_;	/* options to request next time */
+
+    BZERO(&no, sizeof(no));
+    try_ = *go;
+
+    /*
+     * Any Nak'd CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define NAKCIIFACEID(opt, neg, code) \
+    if (go->neg && \
+	len >= (cilen = CILEN_IFACEID) && \
+	p[1] == cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	eui64_get(ifaceid, p); \
+	no.neg = 1; \
+	code \
+    }
+
+#ifdef IPV6CP_COMP
+#define NAKCIVJ(opt, neg, code) \
+    if (go->neg && \
+	((cilen = p[1]) == CILEN_COMPRESS) && \
+	len >= cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	no.neg = 1; \
+        code \
+    }
+#endif /* IPV6CP_COMP */
+
+    /*
+     * Accept the peer's idea of {our,his} interface identifier, if different
+     * from our idea, only if the accept_{local,remote} flag is set.
+     */
+    NAKCIIFACEID(CI_IFACEID, neg_ifaceid,
+		 if (treat_as_reject) {
+		     try_.neg_ifaceid = 0;
+		 } else if (go->accept_local) {
+		     while (eui64_iszero(ifaceid) || 
+			    eui64_equals(ifaceid, go->hisid)) /* bad luck */
+			 eui64_magic(ifaceid);
+		     try_.ourid = ifaceid;
+		     IPV6CPDEBUG(("local LL address %s", llv6_ntoa(ifaceid)));
+		 }
+		 );
+
+#ifdef IPV6CP_COMP
+    NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+	    {
+		if (cishort == IPV6CP_COMP && !treat_as_reject) {
+		    try_.vj_protocol = cishort;
+		} else {
+		    try_.neg_vj = 0;
+		}
+	    }
+	    );
+#endif /* IPV6CP_COMP */
+
+    /*
+     * There may be remaining CIs, if the peer is requesting negotiation
+     * on an option that we didn't include in our request packet.
+     * If they want to negotiate about interface identifier, we comply.
+     * If they want us to ask for compression, we refuse.
+     */
+    while (len >= CILEN_VOID) {
+	GETCHAR(citype, p);
+	GETCHAR(cilen, p);
+	if ( cilen < CILEN_VOID || (len -= cilen) < 0 )
+	    goto bad;
+	next = p + cilen - 2;
+
+	switch (citype) {
+#ifdef IPV6CP_COMP
+	case CI_COMPRESSTYPE:
+	    if (go->neg_vj || no.neg_vj ||
+		(cilen != CILEN_COMPRESS))
+		goto bad;
+	    no.neg_vj = 1;
+	    break;
+#endif /* IPV6CP_COMP */
+	case CI_IFACEID:
+	    if (go->neg_ifaceid || no.neg_ifaceid || cilen != CILEN_IFACEID)
+		goto bad;
+	    try_.neg_ifaceid = 1;
+	    eui64_get(ifaceid, p);
+	    if (go->accept_local) {
+		while (eui64_iszero(ifaceid) || 
+		       eui64_equals(ifaceid, go->hisid)) /* bad luck */
+		    eui64_magic(ifaceid);
+		try_.ourid = ifaceid;
+	    }
+	    no.neg_ifaceid = 1;
+	    break;
+	default:
+	    break;
+	}
+	p = next;
+    }
+
+    /* If there is still anything left, this packet is bad. */
+    if (len != 0)
+	goto bad;
+
+    /*
+     * OK, the Nak is good.  Now we can update state.
+     */
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+
+    return 1;
+
+bad:
+    IPV6CPDEBUG(("ipv6cp_nakci: received bad Nak!"));
+    return 0;
+}
+
+
+/*
+ * ipv6cp_rejci - Reject some of our CIs.
+ */
+static int ipv6cp_rejci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    u_char cilen;
+#ifdef IPV6CP_COMP
+    u_short cishort;
+#endif /* IPV6CP_COMP */
+    eui64_t ifaceid;
+    ipv6cp_options try_;		/* options to request next time */
+
+    try_ = *go;
+    /*
+     * Any Rejected CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define REJCIIFACEID(opt, neg, val1) \
+    if (go->neg && \
+	len >= (cilen = CILEN_IFACEID) && \
+	p[1] == cilen && \
+	p[0] == opt) { \
+	len -= cilen; \
+	INCPTR(2, p); \
+	eui64_get(ifaceid, p); \
+	/* Check rejected value. */ \
+	if (! eui64_equals(ifaceid, val1)) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+
+#ifdef IPV6CP_COMP
+#define REJCIVJ(opt, neg, val) \
+    if (go->neg && \
+	p[1] == CILEN_COMPRESS && \
+	len >= p[1] && \
+	p[0] == opt) { \
+	len -= p[1]; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	/* Check rejected value. */  \
+	if (cishort != val) \
+	    goto bad; \
+	try_.neg = 0; \
+     }
+#endif /* IPV6CP_COMP */
+
+    REJCIIFACEID(CI_IFACEID, neg_ifaceid, go->ourid);
+
+#ifdef IPV6CP_COMP
+    REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol);
+#endif /* IPV6CP_COMP */
+
+    /*
+     * If there are any remaining CIs, then this packet is bad.
+     */
+    if (len != 0)
+	goto bad;
+    /*
+     * Now we can update state.
+     */
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+    return 1;
+
+bad:
+    IPV6CPDEBUG(("ipv6cp_rejci: received bad Reject!"));
+    return 0;
+}
+
+
+/*
+ * ipv6cp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ *
+ * inp = Requested CIs
+ * len = Length of requested CIs
+ *
+ */
+static int ipv6cp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *wo = &pcb->ipv6cp_wantoptions;
+    ipv6cp_options *ho = &pcb->ipv6cp_hisoptions;
+    ipv6cp_options *ao = &pcb->ipv6cp_allowoptions;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    u_char *cip, *next;		/* Pointer to current and next CIs */
+    u_short cilen, citype;	/* Parsed len, type */
+#ifdef IPV6CP_COMP
+    u_short cishort;		/* Parsed short value */
+#endif /* IPV6CP_COMP */
+    eui64_t ifaceid;		/* Parsed interface identifier */
+    int rc = CONFACK;		/* Final packet return code */
+    int orc;			/* Individual option return code */
+    u_char *p;			/* Pointer to next char to parse */
+    u_char *ucp = inp;		/* Pointer to current output char */
+    int l = *len;		/* Length left */
+
+    /*
+     * Reset all his options.
+     */
+    BZERO(ho, sizeof(*ho));
+    
+    /*
+     * Process all his options.
+     */
+    next = inp;
+    while (l) {
+	orc = CONFACK;			/* Assume success */
+	cip = p = next;			/* Remember begining of CI */
+	if (l < 2 ||			/* Not enough data for CI header or */
+	    p[1] < 2 ||			/*  CI length too small or */
+	    p[1] > l) {			/*  CI length too big? */
+	    IPV6CPDEBUG(("ipv6cp_reqci: bad CI length!"));
+	    orc = CONFREJ;		/* Reject bad CI */
+	    cilen = l;			/* Reject till end of packet */
+	    l = 0;			/* Don't loop again */
+	    goto endswitch;
+	}
+	GETCHAR(citype, p);		/* Parse CI type */
+	GETCHAR(cilen, p);		/* Parse CI length */
+	l -= cilen;			/* Adjust remaining length */
+	next += cilen;			/* Step to next CI */
+
+	switch (citype) {		/* Check CI type */
+	case CI_IFACEID:
+	    IPV6CPDEBUG(("ipv6cp: received interface identifier "));
+
+	    if (!ao->neg_ifaceid ||
+		cilen != CILEN_IFACEID) {	/* Check CI length */
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+
+	    /*
+	     * If he has no interface identifier, or if we both have same 
+	     * identifier then NAK it with new idea.
+	     * In particular, if we don't know his identifier, but he does,
+	     * then accept it.
+	     */
+	    eui64_get(ifaceid, p);
+	    IPV6CPDEBUG(("(%s)", llv6_ntoa(ifaceid)));
+	    if (eui64_iszero(ifaceid) && eui64_iszero(go->ourid)) {
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+	    if (!eui64_iszero(wo->hisid) && 
+		!eui64_equals(ifaceid, wo->hisid) && 
+		eui64_iszero(go->hisid)) {
+		    
+		orc = CONFNAK;
+		ifaceid = wo->hisid;
+		go->hisid = ifaceid;
+		DECPTR(sizeof(ifaceid), p);
+		eui64_put(ifaceid, p);
+	    } else
+	    if (eui64_iszero(ifaceid) || eui64_equals(ifaceid, go->ourid)) {
+		orc = CONFNAK;
+		if (eui64_iszero(go->hisid))	/* first time, try option */
+		    ifaceid = wo->hisid;
+		while (eui64_iszero(ifaceid) || 
+		       eui64_equals(ifaceid, go->ourid)) /* bad luck */
+		    eui64_magic(ifaceid);
+		go->hisid = ifaceid;
+		DECPTR(sizeof(ifaceid), p);
+		eui64_put(ifaceid, p);
+	    }
+
+	    ho->neg_ifaceid = 1;
+	    ho->hisid = ifaceid;
+	    break;
+
+#ifdef IPV6CP_COMP
+	case CI_COMPRESSTYPE:
+	    IPV6CPDEBUG(("ipv6cp: received COMPRESSTYPE "));
+	    if (!ao->neg_vj ||
+		(cilen != CILEN_COMPRESS)) {
+		orc = CONFREJ;
+		break;
+	    }
+	    GETSHORT(cishort, p);
+	    IPV6CPDEBUG(("(%d)", cishort));
+
+	    if (!(cishort == IPV6CP_COMP)) {
+		orc = CONFREJ;
+		break;
+	    }
+
+	    ho->neg_vj = 1;
+	    ho->vj_protocol = cishort;
+	    break;
+#endif /* IPV6CP_COMP */
+
+	default:
+	    orc = CONFREJ;
+	    break;
+	}
+
+endswitch:
+	IPV6CPDEBUG((" (%s)\n", CODENAME(orc)));
+
+	if (orc == CONFACK &&		/* Good CI */
+	    rc != CONFACK)		/*  but prior CI wasnt? */
+	    continue;			/* Don't send this one */
+
+	if (orc == CONFNAK) {		/* Nak this CI? */
+	    if (reject_if_disagree)	/* Getting fed up with sending NAKs? */
+		orc = CONFREJ;		/* Get tough if so */
+	    else {
+		if (rc == CONFREJ)	/* Rejecting prior CI? */
+		    continue;		/* Don't send this one */
+		if (rc == CONFACK) {	/* Ack'd all prior CIs? */
+		    rc = CONFNAK;	/* Not anymore... */
+		    ucp = inp;		/* Backup */
+		}
+	    }
+	}
+
+	if (orc == CONFREJ &&		/* Reject this CI */
+	    rc != CONFREJ) {		/*  but no prior ones? */
+	    rc = CONFREJ;
+	    ucp = inp;			/* Backup */
+	}
+
+	/* Need to move CI? */
+	if (ucp != cip)
+	    MEMCPY(ucp, cip, cilen);	/* Move it */
+
+	/* Update output pointer */
+	INCPTR(cilen, ucp);
+    }
+
+    /*
+     * If we aren't rejecting this packet, and we want to negotiate
+     * their identifier and they didn't send their identifier, then we
+     * send a NAK with a CI_IFACEID option appended.  We assume the
+     * input buffer is long enough that we can append the extra
+     * option safely.
+     */
+    if (rc != CONFREJ && !ho->neg_ifaceid &&
+	wo->req_ifaceid && !reject_if_disagree) {
+	if (rc == CONFACK) {
+	    rc = CONFNAK;
+	    ucp = inp;				/* reset pointer */
+	    wo->req_ifaceid = 0;		/* don't ask again */
+	}
+	PUTCHAR(CI_IFACEID, ucp);
+	PUTCHAR(CILEN_IFACEID, ucp);
+	eui64_put(wo->hisid, ucp);
+    }
+
+    *len = ucp - inp;			/* Compute output length */
+    IPV6CPDEBUG(("ipv6cp: returning Configure-%s", CODENAME(rc)));
+    return (rc);			/* Return final code */
+}
+
+#if PPP_OPTIONS
+/*
+ * ipv6_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void ipv6_check_options() {
+    ipv6cp_options *wo = &ipv6cp_wantoptions[0];
+
+    if (!ipv6cp_protent.enabled_flag)
+	return;
+
+    /*
+     * Persistent link-local id is only used when user has not explicitly
+     * configure/hard-code the id
+     */
+    if ((wo->use_persistent) && (!wo->opt_local) && (!wo->opt_remote)) {
+
+	/* 
+	 * On systems where there are no Ethernet interfaces used, there
+	 * may be other ways to obtain a persistent id. Right now, it
+	 * will fall back to using magic [see eui64_magic] below when
+	 * an EUI-48 from MAC address can't be obtained. Other possibilities
+	 * include obtaining EEPROM serial numbers, or some other unique
+	 * yet persistent number. On Sparc platforms, this is possible,
+	 * but too bad there's no standards yet for x86 machines.
+	 */
+	if (ether_to_eui64(&wo->ourid)) {
+	    wo->opt_local = 1;
+	}
+    }
+
+    if (!wo->opt_local) {	/* init interface identifier */
+	if (wo->use_ip && eui64_iszero(wo->ourid)) {
+	    eui64_setlo32(wo->ourid, lwip_ntohl(ipcp_wantoptions[0].ouraddr));
+	    if (!eui64_iszero(wo->ourid))
+		wo->opt_local = 1;
+	}
+	
+	while (eui64_iszero(wo->ourid))
+	    eui64_magic(wo->ourid);
+    }
+
+    if (!wo->opt_remote) {
+	if (wo->use_ip && eui64_iszero(wo->hisid)) {
+	    eui64_setlo32(wo->hisid, lwip_ntohl(ipcp_wantoptions[0].hisaddr));
+	    if (!eui64_iszero(wo->hisid))
+		wo->opt_remote = 1;
+	}
+    }
+
+    if (demand && (eui64_iszero(wo->ourid) || eui64_iszero(wo->hisid))) {
+	option_error("local/remote LL address required for demand-dialling\n");
+	exit(1);
+    }
+}
+#endif /* PPP_OPTIONS */
+
+#if DEMAND_SUPPORT
+/*
+ * ipv6_demand_conf - configure the interface as though
+ * IPV6CP were up, for use with dial-on-demand.
+ */
+static int ipv6_demand_conf(int u) {
+    ipv6cp_options *wo = &ipv6cp_wantoptions[u];
+
+    if (!sif6up(u))
+	return 0;
+
+    if (!sif6addr(u, wo->ourid, wo->hisid))
+	return 0;
+
+    if (!sifnpmode(u, PPP_IPV6, NPMODE_QUEUE))
+	return 0;
+
+    ppp_notice("ipv6_demand_conf");
+    ppp_notice("local  LL address %s", llv6_ntoa(wo->ourid));
+    ppp_notice("remote LL address %s", llv6_ntoa(wo->hisid));
+
+    return 1;
+}
+#endif /* DEMAND_SUPPORT */
+
+
+/*
+ * ipv6cp_up - IPV6CP has come UP.
+ *
+ * Configure the IPv6 network interface appropriately and bring it up.
+ */
+static void ipv6cp_up(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *wo = &pcb->ipv6cp_wantoptions;
+    ipv6cp_options *ho = &pcb->ipv6cp_hisoptions;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+
+    IPV6CPDEBUG(("ipv6cp: up"));
+
+    /*
+     * We must have a non-zero LL address for both ends of the link.
+     */
+    if (!ho->neg_ifaceid)
+	ho->hisid = wo->hisid;
+
+#if 0 /* UNUSED */
+    if(!no_ifaceid_neg) {
+#endif /* UNUSED */
+	if (eui64_iszero(ho->hisid)) {
+	    ppp_error("Could not determine remote LL address");
+	    ipv6cp_close(f->pcb, "Could not determine remote LL address");
+	    return;
+	}
+	if (eui64_iszero(go->ourid)) {
+	    ppp_error("Could not determine local LL address");
+	    ipv6cp_close(f->pcb, "Could not determine local LL address");
+	    return;
+	}
+	if (eui64_equals(go->ourid, ho->hisid)) {
+	    ppp_error("local and remote LL addresses are equal");
+	    ipv6cp_close(f->pcb, "local and remote LL addresses are equal");
+	    return;
+	}
+#if 0 /* UNUSED */
+    }
+#endif /* UNUSED */
+#if 0 /* UNUSED */
+    script_setenv("LLLOCAL", llv6_ntoa(go->ourid), 0);
+    script_setenv("LLREMOTE", llv6_ntoa(ho->hisid), 0);
+#endif /* UNUSED */
+
+#ifdef IPV6CP_COMP
+    /* set tcp compression */
+    sif6comp(f->unit, ho->neg_vj);
+#endif
+
+#if DEMAND_SUPPORT
+    /*
+     * If we are doing dial-on-demand, the interface is already
+     * configured, so we put out any saved-up packets, then set the
+     * interface to pass IPv6 packets.
+     */
+    if (demand) {
+	if (! eui64_equals(go->ourid, wo->ourid) || 
+	    ! eui64_equals(ho->hisid, wo->hisid)) {
+	    if (! eui64_equals(go->ourid, wo->ourid))
+		warn("Local LL address changed to %s", 
+		     llv6_ntoa(go->ourid));
+	    if (! eui64_equals(ho->hisid, wo->hisid))
+		warn("Remote LL address changed to %s", 
+		     llv6_ntoa(ho->hisid));
+	    ipv6cp_clear_addrs(f->pcb, go->ourid, ho->hisid);
+
+	    /* Set the interface to the new addresses */
+	    if (!sif6addr(f->pcb, go->ourid, ho->hisid)) {
+		if (debug)
+		    warn("sif6addr failed");
+		ipv6cp_close(f->unit, "Interface configuration failed");
+		return;
+	    }
+
+	}
+	demand_rexmit(PPP_IPV6);
+	sifnpmode(f->unit, PPP_IPV6, NPMODE_PASS);
+
+    } else
+#endif /* DEMAND_SUPPORT */
+    {
+	/*
+	 * Set LL addresses
+	 */
+	if (!sif6addr(f->pcb, go->ourid, ho->hisid)) {
+	    PPPDEBUG(LOG_DEBUG, ("sif6addr failed"));
+	    ipv6cp_close(f->pcb, "Interface configuration failed");
+	    return;
+	}
+
+	/* bring the interface up for IPv6 */
+	if (!sif6up(f->pcb)) {
+	    PPPDEBUG(LOG_DEBUG, ("sif6up failed (IPV6)"));
+	    ipv6cp_close(f->pcb, "Interface configuration failed");
+	    return;
+	}
+#if DEMAND_SUPPORT
+	sifnpmode(f->pcb, PPP_IPV6, NPMODE_PASS);
+#endif /* DEMAND_SUPPORT */
+
+	ppp_notice("local  LL address %s", llv6_ntoa(go->ourid));
+	ppp_notice("remote LL address %s", llv6_ntoa(ho->hisid));
+    }
+
+    np_up(f->pcb, PPP_IPV6);
+    pcb->ipv6cp_is_up = 1;
+
+#if 0 /* UNUSED */
+    /*
+     * Execute the ipv6-up script, like this:
+     *	/etc/ppp/ipv6-up interface tty speed local-LL remote-LL
+     */
+    if (ipv6cp_script_state == s_down && ipv6cp_script_pid == 0) {
+	ipv6cp_script_state = s_up;
+	ipv6cp_script(_PATH_IPV6UP);
+    }
+#endif /* UNUSED */
+}
+
+
+/*
+ * ipv6cp_down - IPV6CP has gone DOWN.
+ *
+ * Take the IPv6 network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipv6cp_down(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    ipv6cp_options *go = &pcb->ipv6cp_gotoptions;
+    ipv6cp_options *ho = &pcb->ipv6cp_hisoptions;
+
+    IPV6CPDEBUG(("ipv6cp: down"));
+#if PPP_STATS_SUPPORT
+    update_link_stats(f->unit);
+#endif /* PPP_STATS_SUPPORT */
+    if (pcb->ipv6cp_is_up) {
+	pcb->ipv6cp_is_up = 0;
+	np_down(f->pcb, PPP_IPV6);
+    }
+#ifdef IPV6CP_COMP
+    sif6comp(f->unit, 0);
+#endif
+
+#if DEMAND_SUPPORT
+    /*
+     * If we are doing dial-on-demand, set the interface
+     * to queue up outgoing packets (for now).
+     */
+    if (demand) {
+	sifnpmode(f->pcb, PPP_IPV6, NPMODE_QUEUE);
+    } else
+#endif /* DEMAND_SUPPORT */
+    {
+#if DEMAND_SUPPORT
+	sifnpmode(f->pcb, PPP_IPV6, NPMODE_DROP);
+#endif /* DEMAND_SUPPORT */
+	ipv6cp_clear_addrs(f->pcb,
+			   go->ourid,
+			   ho->hisid);
+	sif6down(f->pcb);
+    }
+
+#if 0 /* UNUSED */
+    /* Execute the ipv6-down script */
+    if (ipv6cp_script_state == s_up && ipv6cp_script_pid == 0) {
+	ipv6cp_script_state = s_down;
+	ipv6cp_script(_PATH_IPV6DOWN);
+    }
+#endif /* UNUSED */
+}
+
+
+/*
+ * ipv6cp_clear_addrs() - clear the interface addresses, routes,
+ * proxy neighbour discovery entries, etc.
+ */
+static void ipv6cp_clear_addrs(ppp_pcb *pcb, eui64_t ourid, eui64_t hisid) {
+    cif6addr(pcb, ourid, hisid);
+}
+
+
+/*
+ * ipv6cp_finished - possibly shut down the lower layers.
+ */
+static void ipv6cp_finished(fsm *f) {
+    np_finished(f->pcb, PPP_IPV6);
+}
+
+
+#if 0 /* UNUSED */
+/*
+ * ipv6cp_script_done - called when the ipv6-up or ipv6-down script
+ * has finished.
+ */
+static void
+ipv6cp_script_done(arg)
+    void *arg;
+{
+    ipv6cp_script_pid = 0;
+    switch (ipv6cp_script_state) {
+    case s_up:
+	if (ipv6cp_fsm[0].state != PPP_FSM_OPENED) {
+	    ipv6cp_script_state = s_down;
+	    ipv6cp_script(_PATH_IPV6DOWN);
+	}
+	break;
+    case s_down:
+	if (ipv6cp_fsm[0].state == PPP_FSM_OPENED) {
+	    ipv6cp_script_state = s_up;
+	    ipv6cp_script(_PATH_IPV6UP);
+	}
+	break;
+    }
+}
+
+
+/*
+ * ipv6cp_script - Execute a script with arguments
+ * interface-name tty-name speed local-LL remote-LL.
+ */
+static void
+ipv6cp_script(script)
+    char *script;
+{
+    char strspeed[32], strlocal[32], strremote[32];
+    char *argv[8];
+
+    sprintf(strspeed, "%d", baud_rate);
+    strcpy(strlocal, llv6_ntoa(ipv6cp_gotoptions[0].ourid));
+    strcpy(strremote, llv6_ntoa(ipv6cp_hisoptions[0].hisid));
+
+    argv[0] = script;
+    argv[1] = ifname;
+    argv[2] = devnam;
+    argv[3] = strspeed;
+    argv[4] = strlocal;
+    argv[5] = strremote;
+    argv[6] = ipparam;
+    argv[7] = NULL;
+
+    ipv6cp_script_pid = run_program(script, argv, 0, ipv6cp_script_done,
+				    NULL, 0);
+}
+#endif /* UNUSED */
+
+#if PRINTPKT_SUPPORT
+/*
+ * ipv6cp_printpkt - print the contents of an IPV6CP packet.
+ */
+static const char* const ipv6cp_codenames[] = {
+    "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+    "TermReq", "TermAck", "CodeRej"
+};
+
+static int ipv6cp_printpkt(const u_char *p, int plen,
+		void (*printer)(void *, const char *, ...), void *arg) {
+    int code, id, len, olen;
+    const u_char *pstart, *optend;
+#ifdef IPV6CP_COMP
+    u_short cishort;
+#endif /* IPV6CP_COMP */
+    eui64_t ifaceid;
+
+    if (plen < HEADERLEN)
+	return 0;
+    pstart = p;
+    GETCHAR(code, p);
+    GETCHAR(id, p);
+    GETSHORT(len, p);
+    if (len < HEADERLEN || len > plen)
+	return 0;
+
+    if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(ipv6cp_codenames))
+	printer(arg, " %s", ipv6cp_codenames[code-1]);
+    else
+	printer(arg, " code=0x%x", code);
+    printer(arg, " id=0x%x", id);
+    len -= HEADERLEN;
+    switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+	/* print option list */
+	while (len >= 2) {
+	    GETCHAR(code, p);
+	    GETCHAR(olen, p);
+	    p -= 2;
+	    if (olen < 2 || olen > len) {
+		break;
+	    }
+	    printer(arg, " <");
+	    len -= olen;
+	    optend = p + olen;
+	    switch (code) {
+#ifdef IPV6CP_COMP
+	    case CI_COMPRESSTYPE:
+		if (olen >= CILEN_COMPRESS) {
+		    p += 2;
+		    GETSHORT(cishort, p);
+		    printer(arg, "compress ");
+		    printer(arg, "0x%x", cishort);
+		}
+		break;
+#endif /* IPV6CP_COMP */
+	    case CI_IFACEID:
+		if (olen == CILEN_IFACEID) {
+		    p += 2;
+		    eui64_get(ifaceid, p);
+		    printer(arg, "addr %s", llv6_ntoa(ifaceid));
+		}
+		break;
+	    default:
+		break;
+	    }
+	    while (p < optend) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	    }
+	    printer(arg, ">");
+	}
+	break;
+
+    case TERMACK:
+    case TERMREQ:
+	if (len > 0 && *p >= ' ' && *p < 0x7f) {
+	    printer(arg, " ");
+	    ppp_print_string(p, len, printer, arg);
+	    p += len;
+	    len = 0;
+	}
+	break;
+    default:
+	break;
+    }
+
+    /* print the rest of the bytes in the packet */
+    for (; len > 0; --len) {
+	GETCHAR(code, p);
+	printer(arg, " %.2x", code);
+    }
+
+    return p - pstart;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#if DEMAND_SUPPORT
+/*
+ * ipv6_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP6_HDRLEN	40	/* bytes */
+#define IP6_NHDR_FRAG	44	/* fragment IPv6 header */
+#define TCP_HDRLEN	20
+#define TH_FIN		0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define get_ip6nh(x)	(((unsigned char *)(x))[6])
+#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x)	(((unsigned char *)(x))[13])
+
+static int ipv6_active_pkt(u_char *pkt, int len) {
+    u_char *tcp;
+
+    len -= PPP_HDRLEN;
+    pkt += PPP_HDRLEN;
+    if (len < IP6_HDRLEN)
+	return 0;
+    if (get_ip6nh(pkt) == IP6_NHDR_FRAG)
+	return 0;
+    if (get_ip6nh(pkt) != IPPROTO_TCP)
+	return 1;
+    if (len < IP6_HDRLEN + TCP_HDRLEN)
+	return 0;
+    tcp = pkt + IP6_HDRLEN;
+    if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == IP6_HDRLEN + get_tcpoff(tcp) * 4)
+	return 0;
+    return 1;
+}
+#endif /* DEMAND_SUPPORT */
+
+#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/lcp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/lcp.c
new file mode 100644
index 000000000..90ed183b7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/lcp.c
@@ -0,0 +1,2790 @@
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+/*
+ * @todo:
+ */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/lcp.h"
+#if CHAP_SUPPORT
+#include "netif/ppp/chap-new.h"
+#endif /* CHAP_SUPPORT */
+#include "netif/ppp/magic.h"
+
+/*
+ * When the link comes up we want to be able to wait for a short while,
+ * or until seeing some input from the peer, before starting to send
+ * configure-requests.  We do this by delaying the fsm_lowerup call.
+ */
+/* steal a bit in fsm flags word */
+#define DELAYED_UP	0x80
+
+static void lcp_delayed_up(void *arg);
+
+/*
+ * LCP-related command-line options.
+ */
+#if 0 /* UNUSED */
+int	lcp_echo_interval = 0; 	/* Interval between LCP echo-requests */
+int	lcp_echo_fails = 0;	/* Tolerance to unanswered echo-requests */
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+/* options */
+static u_int lcp_echo_interval      = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int lcp_echo_fails         = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+#endif /* UNUSED */
+
+#if 0 /* UNUSED */
+#if PPP_LCP_ADAPTIVE
+bool	lcp_echo_adaptive = 0;	/* request echo only if the link was idle */
+#endif
+bool	lax_recv = 0;		/* accept control chars in asyncmap */
+bool	noendpoint = 0;		/* don't send/accept endpoint discriminator */
+#endif /* UNUSED */
+
+#if PPP_OPTIONS
+static int noopt (char **);
+#endif /* PPP_OPTIONS */
+
+#ifdef HAVE_MULTILINK
+static int setendpoint (char **);
+static void printendpoint (option_t *, void (*)(void *, char *, ...),
+			       void *);
+#endif /* HAVE_MULTILINK */
+
+#if PPP_OPTIONS
+static option_t lcp_option_list[] = {
+    /* LCP options */
+    { "-all", o_special_noarg, (void *)noopt,
+      "Don't request/allow any LCP options" },
+
+    { "noaccomp", o_bool, &lcp_wantoptions[0].neg_accompression,
+      "Disable address/control compression",
+      OPT_A2CLR, &lcp_allowoptions[0].neg_accompression },
+    { "-ac", o_bool, &lcp_wantoptions[0].neg_accompression,
+      "Disable address/control compression",
+      OPT_ALIAS | OPT_A2CLR, &lcp_allowoptions[0].neg_accompression },
+
+    { "asyncmap", o_uint32, &lcp_wantoptions[0].asyncmap,
+      "Set asyncmap (for received packets)",
+      OPT_OR, &lcp_wantoptions[0].neg_asyncmap },
+    { "-as", o_uint32, &lcp_wantoptions[0].asyncmap,
+      "Set asyncmap (for received packets)",
+      OPT_ALIAS | OPT_OR, &lcp_wantoptions[0].neg_asyncmap },
+    { "default-asyncmap", o_uint32, &lcp_wantoptions[0].asyncmap,
+      "Disable asyncmap negotiation",
+      OPT_OR | OPT_NOARG | OPT_VAL(~0U) | OPT_A2CLR,
+      &lcp_allowoptions[0].neg_asyncmap },
+    { "-am", o_uint32, &lcp_wantoptions[0].asyncmap,
+      "Disable asyncmap negotiation",
+      OPT_ALIAS | OPT_OR | OPT_NOARG | OPT_VAL(~0U) | OPT_A2CLR,
+      &lcp_allowoptions[0].neg_asyncmap },
+
+    { "nomagic", o_bool, &lcp_wantoptions[0].neg_magicnumber,
+      "Disable magic number negotiation (looped-back line detection)",
+      OPT_A2CLR, &lcp_allowoptions[0].neg_magicnumber },
+    { "-mn", o_bool, &lcp_wantoptions[0].neg_magicnumber,
+      "Disable magic number negotiation (looped-back line detection)",
+      OPT_ALIAS | OPT_A2CLR, &lcp_allowoptions[0].neg_magicnumber },
+
+    { "mru", o_int, &lcp_wantoptions[0].mru,
+      "Set MRU (maximum received packet size) for negotiation",
+      OPT_PRIO, &lcp_wantoptions[0].neg_mru },
+    { "default-mru", o_bool, &lcp_wantoptions[0].neg_mru,
+      "Disable MRU negotiation (use default 1500)",
+      OPT_PRIOSUB | OPT_A2CLR, &lcp_allowoptions[0].neg_mru },
+    { "-mru", o_bool, &lcp_wantoptions[0].neg_mru,
+      "Disable MRU negotiation (use default 1500)",
+      OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR, &lcp_allowoptions[0].neg_mru },
+
+    { "mtu", o_int, &lcp_allowoptions[0].mru,
+      "Set our MTU", OPT_LIMITS, NULL, MAXMRU, MINMRU },
+
+    { "nopcomp", o_bool, &lcp_wantoptions[0].neg_pcompression,
+      "Disable protocol field compression",
+      OPT_A2CLR, &lcp_allowoptions[0].neg_pcompression },
+    { "-pc", o_bool, &lcp_wantoptions[0].neg_pcompression,
+      "Disable protocol field compression",
+      OPT_ALIAS | OPT_A2CLR, &lcp_allowoptions[0].neg_pcompression },
+
+    { "passive", o_bool, &lcp_wantoptions[0].passive,
+      "Set passive mode", 1 },
+    { "-p", o_bool, &lcp_wantoptions[0].passive,
+      "Set passive mode", OPT_ALIAS | 1 },
+
+    { "silent", o_bool, &lcp_wantoptions[0].silent,
+      "Set silent mode", 1 },
+
+    { "lcp-echo-failure", o_int, &lcp_echo_fails,
+      "Set number of consecutive echo failures to indicate link failure",
+      OPT_PRIO },
+    { "lcp-echo-interval", o_int, &lcp_echo_interval,
+      "Set time in seconds between LCP echo requests", OPT_PRIO },
+#if PPP_LCP_ADAPTIVE
+    { "lcp-echo-adaptive", o_bool, &lcp_echo_adaptive,
+      "Suppress LCP echo requests if traffic was received", 1 },
+#endif
+    { "lcp-restart", o_int, &lcp_fsm[0].timeouttime,
+      "Set time in seconds between LCP retransmissions", OPT_PRIO },
+    { "lcp-max-terminate", o_int, &lcp_fsm[0].maxtermtransmits,
+      "Set maximum number of LCP terminate-request transmissions", OPT_PRIO },
+    { "lcp-max-configure", o_int, &lcp_fsm[0].maxconfreqtransmits,
+      "Set maximum number of LCP configure-request transmissions", OPT_PRIO },
+    { "lcp-max-failure", o_int, &lcp_fsm[0].maxnakloops,
+      "Set limit on number of LCP configure-naks", OPT_PRIO },
+
+    { "receive-all", o_bool, &lax_recv,
+      "Accept all received control characters", 1 },
+
+#ifdef HAVE_MULTILINK
+    { "mrru", o_int, &lcp_wantoptions[0].mrru,
+      "Maximum received packet size for multilink bundle",
+      OPT_PRIO, &lcp_wantoptions[0].neg_mrru },
+
+    { "mpshortseq", o_bool, &lcp_wantoptions[0].neg_ssnhf,
+      "Use short sequence numbers in multilink headers",
+      OPT_PRIO | 1, &lcp_allowoptions[0].neg_ssnhf },
+    { "nompshortseq", o_bool, &lcp_wantoptions[0].neg_ssnhf,
+      "Don't use short sequence numbers in multilink headers",
+      OPT_PRIOSUB | OPT_A2CLR, &lcp_allowoptions[0].neg_ssnhf },
+
+    { "endpoint", o_special, (void *) setendpoint,
+      "Endpoint discriminator for multilink",
+      OPT_PRIO | OPT_A2PRINTER, (void *) printendpoint },
+#endif /* HAVE_MULTILINK */
+
+    { "noendpoint", o_bool, &noendpoint,
+      "Don't send or accept multilink endpoint discriminator", 1 },
+
+    {NULL}
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci(fsm *f);	/* Reset our CI */
+static int  lcp_cilen(fsm *f);		/* Return length of our CI */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp); /* Add our CI to pkt */
+static int  lcp_ackci(fsm *f, u_char *p, int len); /* Peer ack'd our CI */
+static int  lcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject); /* Peer nak'd our CI */
+static int  lcp_rejci(fsm *f, u_char *p, int len); /* Peer rej'd our CI */
+static int  lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree); /* Rcv peer CI */
+static void lcp_up(fsm *f);		/* We're UP */
+static void lcp_down(fsm *f);		/* We're DOWN */
+static void lcp_starting (fsm *);	/* We need lower layer up */
+static void lcp_finished (fsm *);	/* We need lower layer down */
+static int  lcp_extcode(fsm *f, int code, int id, u_char *inp, int len);
+static void lcp_rprotrej(fsm *f, u_char *inp, int len);
+
+/*
+ * routines to send LCP echos to peer
+ */
+
+static void lcp_echo_lowerup(ppp_pcb *pcb);
+static void lcp_echo_lowerdown(ppp_pcb *pcb);
+static void LcpEchoTimeout(void *arg);
+static void lcp_received_echo_reply(fsm *f, int id, u_char *inp, int len);
+static void LcpSendEchoRequest(fsm *f);
+static void LcpLinkFailure(fsm *f);
+static void LcpEchoCheck(fsm *f);
+
+static const fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
+    lcp_resetci,		/* Reset our Configuration Information */
+    lcp_cilen,			/* Length of our Configuration Information */
+    lcp_addci,			/* Add our Configuration Information */
+    lcp_ackci,			/* ACK our Configuration Information */
+    lcp_nakci,			/* NAK our Configuration Information */
+    lcp_rejci,			/* Reject our Configuration Information */
+    lcp_reqci,			/* Request peer's Configuration Information */
+    lcp_up,			/* Called when fsm reaches OPENED state */
+    lcp_down,			/* Called when fsm leaves OPENED state */
+    lcp_starting,		/* Called when we want the lower layer up */
+    lcp_finished,		/* Called when we want the lower layer down */
+    NULL,			/* Called when Protocol-Reject received */
+    NULL,			/* Retransmission is necessary */
+    lcp_extcode,		/* Called to handle LCP-specific codes */
+    "LCP"			/* String name of protocol */
+};
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+
+static void lcp_init(ppp_pcb *pcb);
+static void lcp_input(ppp_pcb *pcb, u_char *p, int len);
+static void lcp_protrej(ppp_pcb *pcb);
+#if PRINTPKT_SUPPORT
+static int lcp_printpkt(const u_char *p, int plen,
+		void (*printer) (void *, const char *, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+
+const struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if PRINTPKT_SUPPORT
+    lcp_printpkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    NULL,
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    "LCP",
+    NULL,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    lcp_option_list,
+    NULL,
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    NULL,
+    NULL
+#endif /* DEMAND_SUPPORT */
+};
+
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID	2
+#define CILEN_CHAR	3
+#define CILEN_SHORT	4	/* CILEN_VOID + 2 */
+#if CHAP_SUPPORT
+#define CILEN_CHAP	5	/* CILEN_VOID + 2 + 1 */
+#endif /* CHAP_SUPPORT */
+#define CILEN_LONG	6	/* CILEN_VOID + 4 */
+#if LQR_SUPPORT
+#define CILEN_LQR	8	/* CILEN_VOID + 2 + 4 */
+#endif /* LQR_SUPPORT */
+#define CILEN_CBCP	3
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+#if PPP_OPTIONS
+/*
+ * noopt - Disable all options (why?).
+ */
+static int
+noopt(argv)
+    char **argv;
+{
+    BZERO((char *) &lcp_wantoptions[0], sizeof (struct lcp_options));
+    BZERO((char *) &lcp_allowoptions[0], sizeof (struct lcp_options));
+
+    return (1);
+}
+#endif /* PPP_OPTIONS */
+
+#ifdef HAVE_MULTILINK
+static int
+setendpoint(argv)
+    char **argv;
+{
+    if (str_to_epdisc(&lcp_wantoptions[0].endpoint, *argv)) {
+	lcp_wantoptions[0].neg_endpoint = 1;
+	return 1;
+    }
+    option_error("Can't parse '%s' as an endpoint discriminator", *argv);
+    return 0;
+}
+
+static void
+printendpoint(opt, printer, arg)
+    option_t *opt;
+    void (*printer) (void *, char *, ...);
+    void *arg;
+{
+	printer(arg, "%s", epdisc_to_str(&lcp_wantoptions[0].endpoint));
+}
+#endif /* HAVE_MULTILINK */
+
+/*
+ * lcp_init - Initialize LCP.
+ */
+static void lcp_init(ppp_pcb *pcb) {
+    fsm *f = &pcb->lcp_fsm;
+    lcp_options *wo = &pcb->lcp_wantoptions;
+    lcp_options *ao = &pcb->lcp_allowoptions;
+
+    f->pcb = pcb;
+    f->protocol = PPP_LCP;
+    f->callbacks = &lcp_callbacks;
+
+    fsm_init(f);
+
+    BZERO(wo, sizeof(*wo));
+    wo->neg_mru = 1;
+    wo->mru = PPP_DEFMRU;
+    wo->neg_asyncmap = 1;
+    wo->neg_magicnumber = 1;
+    wo->neg_pcompression = 1;
+    wo->neg_accompression = 1;
+
+    BZERO(ao, sizeof(*ao));
+    ao->neg_mru = 1;
+    ao->mru = PPP_MAXMRU;
+    ao->neg_asyncmap = 1;
+#if CHAP_SUPPORT
+    ao->neg_chap = 1;
+    ao->chap_mdtype = CHAP_MDTYPE_SUPPORTED;
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+    ao->neg_upap = 1;
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+    ao->neg_eap = 1;
+#endif /* EAP_SUPPORT */
+    ao->neg_magicnumber = 1;
+    ao->neg_pcompression = 1;
+    ao->neg_accompression = 1;
+    ao->neg_endpoint = 1;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void lcp_open(ppp_pcb *pcb) {
+    fsm *f = &pcb->lcp_fsm;
+    lcp_options *wo = &pcb->lcp_wantoptions;
+
+    f->flags &= ~(OPT_PASSIVE | OPT_SILENT);
+    if (wo->passive)
+	f->flags |= OPT_PASSIVE;
+    if (wo->silent)
+	f->flags |= OPT_SILENT;
+    fsm_open(f);
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void lcp_close(ppp_pcb *pcb, const char *reason) {
+    fsm *f = &pcb->lcp_fsm;
+    int oldstate;
+
+    if (pcb->phase != PPP_PHASE_DEAD
+#ifdef HAVE_MULTILINK
+    && pcb->phase != PPP_PHASE_MASTER
+#endif /* HAVE_MULTILINK */
+    )
+	new_phase(pcb, PPP_PHASE_TERMINATE);
+
+    if (f->flags & DELAYED_UP) {
+	UNTIMEOUT(lcp_delayed_up, f);
+	f->state = PPP_FSM_STOPPED;
+    }
+    oldstate = f->state;
+
+    fsm_close(f, reason);
+    if (oldstate == PPP_FSM_STOPPED && (f->flags & (OPT_PASSIVE|OPT_SILENT|DELAYED_UP))) {
+	/*
+	 * This action is not strictly according to the FSM in RFC1548,
+	 * but it does mean that the program terminates if you do a
+	 * lcp_close() when a connection hasn't been established
+	 * because we are in passive/silent mode or because we have
+	 * delayed the fsm_lowerup() call and it hasn't happened yet.
+	 */
+	f->flags &= ~DELAYED_UP;
+	lcp_finished(f);
+    }
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void lcp_lowerup(ppp_pcb *pcb) {
+    lcp_options *wo = &pcb->lcp_wantoptions;
+    fsm *f = &pcb->lcp_fsm;
+    /*
+     * Don't use A/C or protocol compression on transmission,
+     * but accept A/C and protocol compressed packets
+     * if we are going to ask for A/C and protocol compression.
+     */
+    if (ppp_send_config(pcb, PPP_MRU, 0xffffffff, 0, 0) < 0
+	|| ppp_recv_config(pcb, PPP_MRU, (pcb->settings.lax_recv? 0: 0xffffffff),
+			   wo->neg_pcompression, wo->neg_accompression) < 0)
+	    return;
+    pcb->peer_mru = PPP_MRU;
+
+    if (pcb->settings.listen_time != 0) {
+	f->flags |= DELAYED_UP;
+	TIMEOUTMS(lcp_delayed_up, f, pcb->settings.listen_time);
+    } else
+	fsm_lowerup(f);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void lcp_lowerdown(ppp_pcb *pcb) {
+    fsm *f = &pcb->lcp_fsm;
+
+    if (f->flags & DELAYED_UP) {
+	f->flags &= ~DELAYED_UP;
+	UNTIMEOUT(lcp_delayed_up, f);
+    } else
+	fsm_lowerdown(f);
+}
+
+
+/*
+ * lcp_delayed_up - Bring the lower layer up now.
+ */
+static void lcp_delayed_up(void *arg) {
+    fsm *f = (fsm*)arg;
+
+    if (f->flags & DELAYED_UP) {
+	f->flags &= ~DELAYED_UP;
+	fsm_lowerup(f);
+    }
+}
+
+
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void lcp_input(ppp_pcb *pcb, u_char *p, int len) {
+    fsm *f = &pcb->lcp_fsm;
+
+    if (f->flags & DELAYED_UP) {
+	f->flags &= ~DELAYED_UP;
+	UNTIMEOUT(lcp_delayed_up, f);
+	fsm_lowerup(f);
+    }
+    fsm_input(f, p, len);
+}
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int lcp_extcode(fsm *f, int code, int id, u_char *inp, int len) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    u_char *magp;
+
+    switch( code ){
+    case PROTREJ:
+	lcp_rprotrej(f, inp, len);
+	break;
+    
+    case ECHOREQ:
+	if (f->state != PPP_FSM_OPENED)
+	    break;
+	magp = inp;
+	PUTLONG(go->magicnumber, magp);
+	fsm_sdata(f, ECHOREP, id, inp, len);
+	break;
+    
+    case ECHOREP:
+	lcp_received_echo_reply(f, id, inp, len);
+	break;
+
+    case DISCREQ:
+    case IDENTIF:
+    case TIMEREM:
+	break;
+
+    default:
+	return 0;
+    }
+    return 1;
+}
+
+    
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void lcp_rprotrej(fsm *f, u_char *inp, int len) {
+    int i;
+    const struct protent *protp;
+    u_short prot;
+#if PPP_PROTOCOLNAME
+    const char *pname;
+#endif /* PPP_PROTOCOLNAME */
+
+    if (len < 2) {
+	LCPDEBUG(("lcp_rprotrej: Rcvd short Protocol-Reject packet!"));
+	return;
+    }
+
+    GETSHORT(prot, inp);
+
+    /*
+     * Protocol-Reject packets received in any state other than the LCP
+     * OPENED state SHOULD be silently discarded.
+     */
+    if( f->state != PPP_FSM_OPENED ){
+	LCPDEBUG(("Protocol-Reject discarded: LCP in state %d", f->state));
+	return;
+    }
+
+#if PPP_PROTOCOLNAME
+    pname = protocol_name(prot);
+#endif /* PPP_PROTOCOLNAME */
+
+    /*
+     * Upcall the proper Protocol-Reject routine.
+     */
+    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	if (protp->protocol == prot) {
+#if PPP_PROTOCOLNAME
+	    if (pname != NULL)
+		ppp_dbglog("Protocol-Reject for '%s' (0x%x) received", pname,
+		       prot);
+	    else
+#endif /* PPP_PROTOCOLNAME */
+		ppp_dbglog("Protocol-Reject for 0x%x received", prot);
+	    (*protp->protrej)(f->pcb);
+	    return;
+	}
+
+#if PPP_PROTOCOLNAME
+    if (pname != NULL)
+	ppp_warn("Protocol-Reject for unsupported protocol '%s' (0x%x)", pname,
+	     prot);
+    else
+#endif /* #if PPP_PROTOCOLNAME */
+	ppp_warn("Protocol-Reject for unsupported protocol 0x%x", prot);
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+/*ARGSUSED*/
+static void lcp_protrej(ppp_pcb *pcb) {
+    /*
+     * Can't reject LCP!
+     */
+    ppp_error("Received Protocol-Reject for LCP!");
+    fsm_protreject(&pcb->lcp_fsm);
+}
+
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len) {
+    fsm *f = &pcb->lcp_fsm;
+    /*
+     * Send back the protocol and the information field of the
+     * rejected packet.  We only get here if LCP is in the OPENED state.
+     */
+#if 0
+    p += 2;
+    len -= 2;
+#endif
+
+    fsm_sdata(f, PROTREJ, ++f->id,
+	      p, len);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void lcp_resetci(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *wo = &pcb->lcp_wantoptions;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    lcp_options *ao = &pcb->lcp_allowoptions;
+
+#if PPP_AUTH_SUPPORT
+
+    /* note: default value is true for allow options */
+    if (pcb->settings.user && pcb->settings.passwd) {
+#if PAP_SUPPORT
+      if (pcb->settings.refuse_pap) {
+        ao->neg_upap = 0;
+      }
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+      if (pcb->settings.refuse_chap) {
+        ao->chap_mdtype &= ~MDTYPE_MD5;
+      }
+#if MSCHAP_SUPPORT
+      if (pcb->settings.refuse_mschap) {
+        ao->chap_mdtype &= ~MDTYPE_MICROSOFT;
+      }
+      if (pcb->settings.refuse_mschap_v2) {
+        ao->chap_mdtype &= ~MDTYPE_MICROSOFT_V2;
+      }
+#endif /* MSCHAP_SUPPORT */
+      ao->neg_chap = (ao->chap_mdtype != MDTYPE_NONE);
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+      if (pcb->settings.refuse_eap) {
+        ao->neg_eap = 0;
+      }
+#endif /* EAP_SUPPORT */
+
+#if PPP_SERVER
+      /* note: default value is false for wanted options */
+      if (pcb->settings.auth_required) {
+#if PAP_SUPPORT
+        if (!pcb->settings.refuse_pap) {
+          wo->neg_upap = 1;
+        }
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+        if (!pcb->settings.refuse_chap) {
+          wo->chap_mdtype |= MDTYPE_MD5;
+        }
+#if MSCHAP_SUPPORT
+        if (!pcb->settings.refuse_mschap) {
+          wo->chap_mdtype |= MDTYPE_MICROSOFT;
+        }
+        if (!pcb->settings.refuse_mschap_v2) {
+          wo->chap_mdtype |= MDTYPE_MICROSOFT_V2;
+        }
+#endif /* MSCHAP_SUPPORT */
+        wo->neg_chap = (wo->chap_mdtype != MDTYPE_NONE);
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+        if (!pcb->settings.refuse_eap) {
+          wo->neg_eap = 1;
+        }
+#endif /* EAP_SUPPORT */
+      }
+#endif /* PPP_SERVER */
+
+    } else {
+#if PAP_SUPPORT
+      ao->neg_upap = 0;
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+      ao->neg_chap = 0;
+      ao->chap_mdtype = MDTYPE_NONE;
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+      ao->neg_eap = 0;
+#endif /* EAP_SUPPORT */
+    }
+
+    PPPDEBUG(LOG_DEBUG, ("ppp: auth protocols:"));
+#if PAP_SUPPORT
+    PPPDEBUG(LOG_DEBUG, (" PAP=%d", ao->neg_upap));
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+    PPPDEBUG(LOG_DEBUG, (" CHAP=%d CHAP_MD5=%d", ao->neg_chap, !!(ao->chap_mdtype&MDTYPE_MD5)));
+#if MSCHAP_SUPPORT
+    PPPDEBUG(LOG_DEBUG, (" CHAP_MS=%d CHAP_MS2=%d", !!(ao->chap_mdtype&MDTYPE_MICROSOFT), !!(ao->chap_mdtype&MDTYPE_MICROSOFT_V2)));
+#endif /* MSCHAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+    PPPDEBUG(LOG_DEBUG, (" EAP=%d", ao->neg_eap));
+#endif /* EAP_SUPPORT */
+    PPPDEBUG(LOG_DEBUG, ("\n"));
+
+#endif /* PPP_AUTH_SUPPORT */
+
+    wo->magicnumber = magic();
+    wo->numloops = 0;
+    *go = *wo;
+#ifdef HAVE_MULTILINK
+    if (!multilink) {
+	go->neg_mrru = 0;
+#endif /* HAVE_MULTILINK */
+	go->neg_ssnhf = 0;
+	go->neg_endpoint = 0;
+#ifdef HAVE_MULTILINK
+    }
+#endif /* HAVE_MULTILINK */
+    if (pcb->settings.noendpoint)
+	ao->neg_endpoint = 0;
+    pcb->peer_mru = PPP_MRU;
+#if 0 /* UNUSED */
+    auth_reset(pcb);
+#endif /* UNUSED */
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+
+#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
+#if CHAP_SUPPORT
+#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
+#endif /* CHAP_SUPPORT */
+#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
+#if LQR_SUPPORT
+#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
+#endif /* LQR_SUPPORT */
+#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
+    /*
+     * NB: we only ask for one of CHAP, UPAP, or EAP, even if we will
+     * accept more than one.  We prefer EAP first, then CHAP, then
+     * PAP.
+     */
+    return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+	    LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF) +
+#if EAP_SUPPORT
+	    LENCISHORT(go->neg_eap) +
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */
+#if EAP_SUPPORT
+	    LENCICHAP(!go->neg_eap && go->neg_chap) +
+#endif /* EAP_SUPPORT */
+#if !EAP_SUPPORT
+	    LENCICHAP(go->neg_chap) +
+#endif /* !EAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */
+#if EAP_SUPPORT && CHAP_SUPPORT
+	    LENCISHORT(!go->neg_eap && !go->neg_chap && go->neg_upap) +
+#endif /* EAP_SUPPORT && CHAP_SUPPORT */
+#if EAP_SUPPORT && !CHAP_SUPPORT
+	    LENCISHORT(!go->neg_eap && go->neg_upap) +
+#endif /* EAP_SUPPORT && !CHAP_SUPPORT */
+#if !EAP_SUPPORT && CHAP_SUPPORT
+	    LENCISHORT(!go->neg_chap && go->neg_upap) +
+#endif /* !EAP_SUPPORT && CHAP_SUPPORT */
+#if !EAP_SUPPORT && !CHAP_SUPPORT
+	    LENCISHORT(go->neg_upap) +
+#endif /* !EAP_SUPPORT && !CHAP_SUPPORT */
+#endif /* PAP_SUPPORT */
+#if LQR_SUPPORT
+	    LENCILQR(go->neg_lqr) +
+#endif /* LQR_SUPPORT */
+	    LENCICBCP(go->neg_cbcp) +
+	    LENCILONG(go->neg_magicnumber) +
+	    LENCIVOID(go->neg_pcompression) +
+	    LENCIVOID(go->neg_accompression) +
+#ifdef HAVE_MULTILINK
+	    LENCISHORT(go->neg_mrru) +
+#endif /* HAVE_MULTILINK */
+	    LENCIVOID(go->neg_ssnhf) +
+	    (go->neg_endpoint? CILEN_CHAR + go->endpoint.length: 0));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    u_char *start_ucp = ucp;
+
+#define ADDCIVOID(opt, neg) \
+    if (neg) { \
+	PUTCHAR(opt, ucp); \
+	PUTCHAR(CILEN_VOID, ucp); \
+    }
+#define ADDCISHORT(opt, neg, val) \
+    if (neg) { \
+	PUTCHAR(opt, ucp); \
+	PUTCHAR(CILEN_SHORT, ucp); \
+	PUTSHORT(val, ucp); \
+    }
+#if CHAP_SUPPORT
+#define ADDCICHAP(opt, neg, val) \
+    if (neg) { \
+	PUTCHAR((opt), ucp); \
+	PUTCHAR(CILEN_CHAP, ucp); \
+	PUTSHORT(PPP_CHAP, ucp); \
+	PUTCHAR((CHAP_DIGEST(val)), ucp); \
+    }
+#endif /* CHAP_SUPPORT */
+#define ADDCILONG(opt, neg, val) \
+    if (neg) { \
+	PUTCHAR(opt, ucp); \
+	PUTCHAR(CILEN_LONG, ucp); \
+	PUTLONG(val, ucp); \
+    }
+#if LQR_SUPPORT
+#define ADDCILQR(opt, neg, val) \
+    if (neg) { \
+	PUTCHAR(opt, ucp); \
+	PUTCHAR(CILEN_LQR, ucp); \
+	PUTSHORT(PPP_LQR, ucp); \
+	PUTLONG(val, ucp); \
+    }
+#endif /* LQR_SUPPORT */
+#define ADDCICHAR(opt, neg, val) \
+    if (neg) { \
+	PUTCHAR(opt, ucp); \
+	PUTCHAR(CILEN_CHAR, ucp); \
+	PUTCHAR(val, ucp); \
+    }
+#define ADDCIENDP(opt, neg, class, val, len) \
+    if (neg) { \
+	int i; \
+	PUTCHAR(opt, ucp); \
+	PUTCHAR(CILEN_CHAR + len, ucp); \
+	PUTCHAR(class, ucp); \
+	for (i = 0; i < len; ++i) \
+	    PUTCHAR(val[i], ucp); \
+    }
+
+    ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+    ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF,
+	      go->asyncmap);
+#if EAP_SUPPORT
+    ADDCISHORT(CI_AUTHTYPE, go->neg_eap, PPP_EAP);
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */
+#if EAP_SUPPORT
+    ADDCICHAP(CI_AUTHTYPE, !go->neg_eap && go->neg_chap, go->chap_mdtype);
+#endif /* EAP_SUPPORT */
+#if !EAP_SUPPORT
+    ADDCICHAP(CI_AUTHTYPE, go->neg_chap, go->chap_mdtype);
+#endif /* !EAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */
+#if EAP_SUPPORT && CHAP_SUPPORT
+    ADDCISHORT(CI_AUTHTYPE, !go->neg_eap && !go->neg_chap && go->neg_upap, PPP_PAP);
+#endif /* EAP_SUPPORT && CHAP_SUPPORT */
+#if EAP_SUPPORT && !CHAP_SUPPORT
+    ADDCISHORT(CI_AUTHTYPE, !go->neg_eap && go->neg_upap, PPP_PAP);
+#endif /* EAP_SUPPORT && !CHAP_SUPPORT */
+#if !EAP_SUPPORT && CHAP_SUPPORT
+    ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+#endif /* !EAP_SUPPORT && CHAP_SUPPORT */
+#if !EAP_SUPPORT && !CHAP_SUPPORT
+    ADDCISHORT(CI_AUTHTYPE, go->neg_upap, PPP_PAP);
+#endif /* !EAP_SUPPORT && !CHAP_SUPPORT */
+#endif /* PAP_SUPPORT */
+#if LQR_SUPPORT
+    ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+#endif /* LQR_SUPPORT */
+    ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+    ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+    ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+    ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+#ifdef HAVE_MULTILINK
+    ADDCISHORT(CI_MRRU, go->neg_mrru, go->mrru);
+#endif
+    ADDCIVOID(CI_SSNHF, go->neg_ssnhf);
+    ADDCIENDP(CI_EPDISC, go->neg_endpoint, go->endpoint.class_,
+	      go->endpoint.value, go->endpoint.length);
+
+    if (ucp - start_ucp != *lenp) {
+	/* this should never happen, because peer_mtu should be 1500 */
+	ppp_error("Bug in lcp_addci: wrong length");
+    }
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int lcp_ackci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    u_char cilen, citype, cichar;
+    u_short cishort;
+    u32_t cilong;
+
+    /*
+     * CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define ACKCIVOID(opt, neg) \
+    if (neg) { \
+	if ((len -= CILEN_VOID) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_VOID || \
+	    citype != opt) \
+	    goto bad; \
+    }
+#define ACKCISHORT(opt, neg, val) \
+    if (neg) { \
+	if ((len -= CILEN_SHORT) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_SHORT || \
+	    citype != opt) \
+	    goto bad; \
+	GETSHORT(cishort, p); \
+	if (cishort != val) \
+	    goto bad; \
+    }
+#define ACKCICHAR(opt, neg, val) \
+    if (neg) { \
+	if ((len -= CILEN_CHAR) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_CHAR || \
+	    citype != opt) \
+	    goto bad; \
+	GETCHAR(cichar, p); \
+	if (cichar != val) \
+	    goto bad; \
+    }
+#if CHAP_SUPPORT
+#define ACKCICHAP(opt, neg, val) \
+    if (neg) { \
+	if ((len -= CILEN_CHAP) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_CHAP || \
+	    citype != (opt)) \
+	    goto bad; \
+	GETSHORT(cishort, p); \
+	if (cishort != PPP_CHAP) \
+	    goto bad; \
+	GETCHAR(cichar, p); \
+	if (cichar != (CHAP_DIGEST(val))) \
+	  goto bad; \
+    }
+#endif /* CHAP_SUPPORT */
+#define ACKCILONG(opt, neg, val) \
+    if (neg) { \
+	if ((len -= CILEN_LONG) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_LONG || \
+	    citype != opt) \
+	    goto bad; \
+	GETLONG(cilong, p); \
+	if (cilong != val) \
+	    goto bad; \
+    }
+#if LQR_SUPPORT
+#define ACKCILQR(opt, neg, val) \
+    if (neg) { \
+	if ((len -= CILEN_LQR) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_LQR || \
+	    citype != opt) \
+	    goto bad; \
+	GETSHORT(cishort, p); \
+	if (cishort != PPP_LQR) \
+	    goto bad; \
+	GETLONG(cilong, p); \
+	if (cilong != val) \
+	  goto bad; \
+    }
+#endif /* LQR_SUPPORT */
+#define ACKCIENDP(opt, neg, class, val, vlen) \
+    if (neg) { \
+	int i; \
+	if ((len -= CILEN_CHAR + vlen) < 0) \
+	    goto bad; \
+	GETCHAR(citype, p); \
+	GETCHAR(cilen, p); \
+	if (cilen != CILEN_CHAR + vlen || \
+	    citype != opt) \
+	    goto bad; \
+	GETCHAR(cichar, p); \
+	if (cichar != class) \
+	    goto bad; \
+	for (i = 0; i < vlen; ++i) { \
+	    GETCHAR(cichar, p); \
+	    if (cichar != val[i]) \
+		goto bad; \
+	} \
+    }
+
+    ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+    ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF,
+	      go->asyncmap);
+#if EAP_SUPPORT
+    ACKCISHORT(CI_AUTHTYPE, go->neg_eap, PPP_EAP);
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */
+#if EAP_SUPPORT
+    ACKCICHAP(CI_AUTHTYPE, !go->neg_eap && go->neg_chap, go->chap_mdtype);
+#endif /* EAP_SUPPORT */
+#if !EAP_SUPPORT
+    ACKCICHAP(CI_AUTHTYPE, go->neg_chap, go->chap_mdtype);
+#endif /* !EAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */
+#if EAP_SUPPORT && CHAP_SUPPORT
+    ACKCISHORT(CI_AUTHTYPE, !go->neg_eap && !go->neg_chap && go->neg_upap, PPP_PAP);
+#endif /* EAP_SUPPORT && CHAP_SUPPORT */
+#if EAP_SUPPORT && !CHAP_SUPPORT
+    ACKCISHORT(CI_AUTHTYPE, !go->neg_eap && go->neg_upap, PPP_PAP);
+#endif /* EAP_SUPPORT && !CHAP_SUPPORT */
+#if !EAP_SUPPORT && CHAP_SUPPORT
+    ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+#endif /* !EAP_SUPPORT && CHAP_SUPPORT */
+#if !EAP_SUPPORT && !CHAP_SUPPORT
+    ACKCISHORT(CI_AUTHTYPE, go->neg_upap, PPP_PAP);
+#endif /* !EAP_SUPPORT && !CHAP_SUPPORT */
+#endif /* PAP_SUPPORT */
+#if LQR_SUPPORT
+    ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+#endif /* LQR_SUPPORT */
+    ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+    ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+    ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+    ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+#ifdef HAVE_MULTILINK
+    ACKCISHORT(CI_MRRU, go->neg_mrru, go->mrru);
+#endif /* HAVE_MULTILINK */
+    ACKCIVOID(CI_SSNHF, go->neg_ssnhf);
+    ACKCIENDP(CI_EPDISC, go->neg_endpoint, go->endpoint.class_,
+	      go->endpoint.value, go->endpoint.length);
+
+    /*
+     * If there are any remaining CIs, then this packet is bad.
+     */
+    if (len != 0)
+	goto bad;
+    return (1);
+bad:
+    LCPDEBUG(("lcp_acki: received bad Ack!"));
+    return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int lcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    lcp_options *wo = &pcb->lcp_wantoptions;
+    u_char citype, cichar, *next;
+    u_short cishort;
+    u32_t cilong;
+    lcp_options no;		/* options we've seen Naks for */
+    lcp_options try_;		/* options to request next time */
+    int looped_back = 0;
+    int cilen;
+
+    BZERO(&no, sizeof(no));
+    try_ = *go;
+
+    /*
+     * Any Nak'd CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define NAKCIVOID(opt, neg) \
+    if (go->neg && \
+	len >= CILEN_VOID && \
+	p[1] == CILEN_VOID && \
+	p[0] == opt) { \
+	len -= CILEN_VOID; \
+	INCPTR(CILEN_VOID, p); \
+	no.neg = 1; \
+	try_.neg = 0; \
+    }
+#if CHAP_SUPPORT
+#define NAKCICHAP(opt, neg, code) \
+    if (go->neg && \
+	len >= CILEN_CHAP && \
+	p[1] == CILEN_CHAP && \
+	p[0] == opt) { \
+	len -= CILEN_CHAP; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETCHAR(cichar, p); \
+	no.neg = 1; \
+	code \
+    }
+#endif /* CHAP_SUPPORT */
+#define NAKCICHAR(opt, neg, code) \
+    if (go->neg && \
+	len >= CILEN_CHAR && \
+	p[1] == CILEN_CHAR && \
+	p[0] == opt) { \
+	len -= CILEN_CHAR; \
+	INCPTR(2, p); \
+	GETCHAR(cichar, p); \
+	no.neg = 1; \
+	code \
+    }
+#define NAKCISHORT(opt, neg, code) \
+    if (go->neg && \
+	len >= CILEN_SHORT && \
+	p[1] == CILEN_SHORT && \
+	p[0] == opt) { \
+	len -= CILEN_SHORT; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	no.neg = 1; \
+	code \
+    }
+#define NAKCILONG(opt, neg, code) \
+    if (go->neg && \
+	len >= CILEN_LONG && \
+	p[1] == CILEN_LONG && \
+	p[0] == opt) { \
+	len -= CILEN_LONG; \
+	INCPTR(2, p); \
+	GETLONG(cilong, p); \
+	no.neg = 1; \
+	code \
+    }
+#if LQR_SUPPORT
+#define NAKCILQR(opt, neg, code) \
+    if (go->neg && \
+	len >= CILEN_LQR && \
+	p[1] == CILEN_LQR && \
+	p[0] == opt) { \
+	len -= CILEN_LQR; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETLONG(cilong, p); \
+	no.neg = 1; \
+	code \
+    }
+#endif /* LQR_SUPPORT */
+#define NAKCIENDP(opt, neg) \
+    if (go->neg && \
+	len >= CILEN_CHAR && \
+	p[0] == opt && \
+	p[1] >= CILEN_CHAR && \
+	p[1] <= len) { \
+	len -= p[1]; \
+	INCPTR(p[1], p); \
+	no.neg = 1; \
+	try_.neg = 0; \
+    }
+
+    /*
+     * NOTE!  There must be no assignments to individual fields of *go in
+     * the code below.  Any such assignment is a BUG!
+     */
+    /*
+     * We don't care if they want to send us smaller packets than
+     * we want.  Therefore, accept any MRU less than what we asked for,
+     * but then ignore the new value when setting the MRU in the kernel.
+     * If they send us a bigger MRU than what we asked, accept it, up to
+     * the limit of the default MRU we'd get if we didn't negotiate.
+     */
+    if (go->neg_mru && go->mru != PPP_DEFMRU) {
+	NAKCISHORT(CI_MRU, neg_mru,
+		   if (cishort <= wo->mru || cishort <= PPP_DEFMRU)
+		       try_.mru = cishort;
+		   );
+    }
+
+    /*
+     * Add any characters they want to our (receive-side) asyncmap.
+     */
+    if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF) {
+	NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+		  try_.asyncmap = go->asyncmap | cilong;
+		  );
+    }
+
+    /*
+     * If they've nak'd our authentication-protocol, check whether
+     * they are proposing a different protocol, or a different
+     * hash algorithm for CHAP.
+     */
+    if ((0
+#if CHAP_SUPPORT
+        || go->neg_chap
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+        || go->neg_upap
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+        || go->neg_eap
+#endif /* EAP_SUPPORT */
+        )
+	&& len >= CILEN_SHORT
+	&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+	cilen = p[1];
+	len -= cilen;
+#if CHAP_SUPPORT
+	no.neg_chap = go->neg_chap;
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	no.neg_upap = go->neg_upap;
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+	no.neg_eap = go->neg_eap;
+#endif /* EAP_SUPPORT */
+	INCPTR(2, p);
+	GETSHORT(cishort, p);
+
+#if PAP_SUPPORT
+	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+#if EAP_SUPPORT
+	    /* If we were asking for EAP, then we need to stop that. */
+	    if (go->neg_eap)
+		try_.neg_eap = 0;
+	    else
+#endif /* EAP_SUPPORT */
+
+#if CHAP_SUPPORT
+	    /* If we were asking for CHAP, then we need to stop that. */
+	    if (go->neg_chap)
+		try_.neg_chap = 0;
+	    else
+#endif /* CHAP_SUPPORT */
+
+	    /*
+	     * If we weren't asking for CHAP or EAP, then we were asking for
+	     * PAP, in which case this Nak is bad.
+	     */
+		goto bad;
+	} else
+#endif /* PAP_SUPPORT */
+
+#if CHAP_SUPPORT
+	if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+	    GETCHAR(cichar, p);
+#if EAP_SUPPORT
+	    /* Stop asking for EAP, if we were. */
+	    if (go->neg_eap) {
+		try_.neg_eap = 0;
+		/* Try to set up to use their suggestion, if possible */
+		if (CHAP_CANDIGEST(go->chap_mdtype, cichar))
+		    try_.chap_mdtype = CHAP_MDTYPE_D(cichar);
+	    } else
+#endif /* EAP_SUPPORT */
+	    if (go->neg_chap) {
+		/*
+		 * We were asking for our preferred algorithm, they must
+		 * want something different.
+		 */
+		if (cichar != CHAP_DIGEST(go->chap_mdtype)) {
+		    if (CHAP_CANDIGEST(go->chap_mdtype, cichar)) {
+			/* Use their suggestion if we support it ... */
+			try_.chap_mdtype = CHAP_MDTYPE_D(cichar);
+		    } else {
+			/* ... otherwise, try our next-preferred algorithm. */
+			try_.chap_mdtype &= ~(CHAP_MDTYPE(try_.chap_mdtype));
+			if (try_.chap_mdtype == MDTYPE_NONE) /* out of algos */
+			    try_.neg_chap = 0;
+		    }
+		} else {
+		    /*
+		     * Whoops, they Nak'd our algorithm of choice
+		     * but then suggested it back to us.
+		     */
+		    goto bad;
+		}
+	    } else {
+		/*
+		 * Stop asking for PAP if we were asking for it.
+		 */
+#if PAP_SUPPORT
+		try_.neg_upap = 0;
+#endif /* PAP_SUPPORT */
+	    }
+
+	} else
+#endif /* CHAP_SUPPORT */
+	{
+
+#if EAP_SUPPORT
+	    /*
+	     * If we were asking for EAP, and they're Conf-Naking EAP,
+	     * well, that's just strange.  Nobody should do that.
+	     */
+	    if (cishort == PPP_EAP && cilen == CILEN_SHORT && go->neg_eap)
+		ppp_dbglog("Unexpected Conf-Nak for EAP");
+
+	    /*
+	     * We don't recognize what they're suggesting.
+	     * Stop asking for what we were asking for.
+	     */
+	    if (go->neg_eap)
+		try_.neg_eap = 0;
+	    else
+#endif /* EAP_SUPPORT */
+
+#if CHAP_SUPPORT
+	    if (go->neg_chap)
+		try_.neg_chap = 0;
+	    else
+#endif /* CHAP_SUPPORT */
+
+#if PAP_SUPPORT
+	    if(1)
+		try_.neg_upap = 0;
+	    else
+#endif /* PAP_SUPPORT */
+	    {}
+
+	    p += cilen - CILEN_SHORT;
+	}
+    }
+
+#if LQR_SUPPORT
+    /*
+     * If they can't cope with our link quality protocol, we'll have
+     * to stop asking for LQR.  We haven't got any other protocol.
+     * If they Nak the reporting period, take their value XXX ?
+     */
+    NAKCILQR(CI_QUALITY, neg_lqr,
+	     if (cishort != PPP_LQR)
+		 try_.neg_lqr = 0;
+	     else
+		 try_.lqr_period = cilong;
+	     );
+#endif /* LQR_SUPPORT */
+
+    /*
+     * Only implementing CBCP...not the rest of the callback options
+     */
+    NAKCICHAR(CI_CALLBACK, neg_cbcp,
+              try_.neg_cbcp = 0;
+              (void)cichar; /* if CHAP support is not compiled, cichar is set but not used, which makes some compilers complaining */
+              );
+
+    /*
+     * Check for a looped-back line.
+     */
+    NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+	      try_.magicnumber = magic();
+	      looped_back = 1;
+	      );
+
+    /*
+     * Peer shouldn't send Nak for protocol compression or
+     * address/control compression requests; they should send
+     * a Reject instead.  If they send a Nak, treat it as a Reject.
+     */
+    NAKCIVOID(CI_PCOMPRESSION, neg_pcompression);
+    NAKCIVOID(CI_ACCOMPRESSION, neg_accompression);
+
+#ifdef HAVE_MULTILINK
+    /*
+     * Nak for MRRU option - accept their value if it is smaller
+     * than the one we want.
+     */
+    if (go->neg_mrru) {
+	NAKCISHORT(CI_MRRU, neg_mrru,
+		   if (treat_as_reject)
+		       try_.neg_mrru = 0;
+		   else if (cishort <= wo->mrru)
+		       try_.mrru = cishort;
+		   );
+    }
+#else /* HAVE_MULTILINK */
+    LWIP_UNUSED_ARG(treat_as_reject);
+#endif /* HAVE_MULTILINK */
+
+    /*
+     * Nak for short sequence numbers shouldn't be sent, treat it
+     * like a reject.
+     */
+    NAKCIVOID(CI_SSNHF, neg_ssnhf);
+
+    /*
+     * Nak of the endpoint discriminator option is not permitted,
+     * treat it like a reject.
+     */
+    NAKCIENDP(CI_EPDISC, neg_endpoint);
+
+    /*
+     * There may be remaining CIs, if the peer is requesting negotiation
+     * on an option that we didn't include in our request packet.
+     * If we see an option that we requested, or one we've already seen
+     * in this packet, then this packet is bad.
+     * If we wanted to respond by starting to negotiate on the requested
+     * option(s), we could, but we don't, because except for the
+     * authentication type and quality protocol, if we are not negotiating
+     * an option, it is because we were told not to.
+     * For the authentication type, the Nak from the peer means
+     * `let me authenticate myself with you' which is a bit pointless.
+     * For the quality protocol, the Nak means `ask me to send you quality
+     * reports', but if we didn't ask for them, we don't want them.
+     * An option we don't recognize represents the peer asking to
+     * negotiate some option we don't support, so ignore it.
+     */
+    while (len >= CILEN_VOID) {
+	GETCHAR(citype, p);
+	GETCHAR(cilen, p);
+	if (cilen < CILEN_VOID || (len -= cilen) < 0)
+	    goto bad;
+	next = p + cilen - 2;
+
+	switch (citype) {
+	case CI_MRU:
+	    if ((go->neg_mru && go->mru != PPP_DEFMRU)
+		|| no.neg_mru || cilen != CILEN_SHORT)
+		goto bad;
+	    GETSHORT(cishort, p);
+	    if (cishort < PPP_DEFMRU) {
+		try_.neg_mru = 1;
+		try_.mru = cishort;
+	    }
+	    break;
+	case CI_ASYNCMAP:
+	    if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF)
+		|| no.neg_asyncmap || cilen != CILEN_LONG)
+		goto bad;
+	    break;
+	case CI_AUTHTYPE:
+	    if (0
+#if CHAP_SUPPORT
+                || go->neg_chap || no.neg_chap
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+                || go->neg_upap || no.neg_upap
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+		|| go->neg_eap || no.neg_eap
+#endif /* EAP_SUPPORT */
+		)
+		goto bad;
+	    break;
+	case CI_MAGICNUMBER:
+	    if (go->neg_magicnumber || no.neg_magicnumber ||
+		cilen != CILEN_LONG)
+		goto bad;
+	    break;
+	case CI_PCOMPRESSION:
+	    if (go->neg_pcompression || no.neg_pcompression
+		|| cilen != CILEN_VOID)
+		goto bad;
+	    break;
+	case CI_ACCOMPRESSION:
+	    if (go->neg_accompression || no.neg_accompression
+		|| cilen != CILEN_VOID)
+		goto bad;
+	    break;
+#if LQR_SUPPORT
+	case CI_QUALITY:
+	    if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
+		goto bad;
+	    break;
+#endif /* LQR_SUPPORT */
+#ifdef HAVE_MULTILINK
+	case CI_MRRU:
+	    if (go->neg_mrru || no.neg_mrru || cilen != CILEN_SHORT)
+		goto bad;
+	    break;
+#endif /* HAVE_MULTILINK */
+	case CI_SSNHF:
+	    if (go->neg_ssnhf || no.neg_ssnhf || cilen != CILEN_VOID)
+		goto bad;
+	    try_.neg_ssnhf = 1;
+	    break;
+	case CI_EPDISC:
+	    if (go->neg_endpoint || no.neg_endpoint || cilen < CILEN_CHAR)
+		goto bad;
+	    break;
+	default:
+	    break;
+	}
+	p = next;
+    }
+
+    /*
+     * OK, the Nak is good.  Now we can update state.
+     * If there are any options left we ignore them.
+     */
+    if (f->state != PPP_FSM_OPENED) {
+	if (looped_back) {
+	    if (++try_.numloops >= pcb->settings.lcp_loopbackfail) {
+		ppp_notice("Serial line is looped back.");
+		pcb->err_code = PPPERR_LOOPBACK;
+		lcp_close(f->pcb, "Loopback detected");
+	    }
+	} else
+	    try_.numloops = 0;
+	*go = try_;
+    }
+
+    return 1;
+
+bad:
+    LCPDEBUG(("lcp_nakci: received bad Nak!"));
+    return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Reject was bad.
+ *	1 - Reject was good.
+ */
+static int lcp_rejci(fsm *f, u_char *p, int len) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    u_char cichar;
+    u_short cishort;
+    u32_t cilong;
+    lcp_options try_;		/* options to request next time */
+
+    try_ = *go;
+
+    /*
+     * Any Rejected CIs must be in exactly the same order that we sent.
+     * Check packet length and CI length at each step.
+     * If we find any deviations, then this packet is bad.
+     */
+#define REJCIVOID(opt, neg) \
+    if (go->neg && \
+	len >= CILEN_VOID && \
+	p[1] == CILEN_VOID && \
+	p[0] == opt) { \
+	len -= CILEN_VOID; \
+	INCPTR(CILEN_VOID, p); \
+	try_.neg = 0; \
+    }
+#define REJCISHORT(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_SHORT && \
+	p[1] == CILEN_SHORT && \
+	p[0] == opt) { \
+	len -= CILEN_SHORT; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	/* Check rejected value. */ \
+	if (cishort != val) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+
+#if CHAP_SUPPORT && EAP_SUPPORT && PAP_SUPPORT
+#define REJCICHAP(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_CHAP && \
+	p[1] == CILEN_CHAP && \
+	p[0] == opt) { \
+	len -= CILEN_CHAP; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETCHAR(cichar, p); \
+	/* Check rejected value. */ \
+	if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \
+	    goto bad; \
+	try_.neg = 0; \
+	try_.neg_eap = try_.neg_upap = 0; \
+    }
+#endif /* CHAP_SUPPORT && EAP_SUPPORT && PAP_SUPPORT */
+
+#if CHAP_SUPPORT && !EAP_SUPPORT && PAP_SUPPORT
+#define REJCICHAP(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_CHAP && \
+	p[1] == CILEN_CHAP && \
+	p[0] == opt) { \
+	len -= CILEN_CHAP; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETCHAR(cichar, p); \
+	/* Check rejected value. */ \
+	if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \
+	    goto bad; \
+	try_.neg = 0; \
+	try_.neg_upap = 0; \
+    }
+#endif /* CHAP_SUPPORT && !EAP_SUPPORT && PAP_SUPPORT */
+
+#if CHAP_SUPPORT && EAP_SUPPORT && !PAP_SUPPORT
+#define REJCICHAP(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_CHAP && \
+	p[1] == CILEN_CHAP && \
+	p[0] == opt) { \
+	len -= CILEN_CHAP; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETCHAR(cichar, p); \
+	/* Check rejected value. */ \
+	if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \
+	    goto bad; \
+	try_.neg = 0; \
+	try_.neg_eap = 0; \
+    }
+#endif /* CHAP_SUPPORT && EAP_SUPPORT && !PAP_SUPPORT */
+
+#if CHAP_SUPPORT && !EAP_SUPPORT && !PAP_SUPPORT
+#define REJCICHAP(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_CHAP && \
+	p[1] == CILEN_CHAP && \
+	p[0] == opt) { \
+	len -= CILEN_CHAP; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETCHAR(cichar, p); \
+	/* Check rejected value. */ \
+	if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+#endif /* CHAP_SUPPORT && !EAP_SUPPORT && !PAP_SUPPORT */
+
+#define REJCILONG(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_LONG && \
+	p[1] == CILEN_LONG && \
+	p[0] == opt) { \
+	len -= CILEN_LONG; \
+	INCPTR(2, p); \
+	GETLONG(cilong, p); \
+	/* Check rejected value. */ \
+	if (cilong != val) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+#if LQR_SUPPORT
+#define REJCILQR(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_LQR && \
+	p[1] == CILEN_LQR && \
+	p[0] == opt) { \
+	len -= CILEN_LQR; \
+	INCPTR(2, p); \
+	GETSHORT(cishort, p); \
+	GETLONG(cilong, p); \
+	/* Check rejected value. */ \
+	if (cishort != PPP_LQR || cilong != val) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+#endif /* LQR_SUPPORT */
+#define REJCICBCP(opt, neg, val) \
+    if (go->neg && \
+	len >= CILEN_CBCP && \
+	p[1] == CILEN_CBCP && \
+	p[0] == opt) { \
+	len -= CILEN_CBCP; \
+	INCPTR(2, p); \
+	GETCHAR(cichar, p); \
+	/* Check rejected value. */ \
+	if (cichar != val) \
+	    goto bad; \
+	try_.neg = 0; \
+    }
+#define REJCIENDP(opt, neg, class, val, vlen) \
+    if (go->neg && \
+	len >= CILEN_CHAR + vlen && \
+	p[0] == opt && \
+	p[1] == CILEN_CHAR + vlen) { \
+	int i; \
+	len -= CILEN_CHAR + vlen; \
+	INCPTR(2, p); \
+	GETCHAR(cichar, p); \
+	if (cichar != class) \
+	    goto bad; \
+	for (i = 0; i < vlen; ++i) { \
+	    GETCHAR(cichar, p); \
+	    if (cichar != val[i]) \
+		goto bad; \
+	} \
+	try_.neg = 0; \
+    }
+
+    REJCISHORT(CI_MRU, neg_mru, go->mru);
+    REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+#if EAP_SUPPORT
+    REJCISHORT(CI_AUTHTYPE, neg_eap, PPP_EAP);
+    if (!go->neg_eap) {
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT
+	REJCICHAP(CI_AUTHTYPE, neg_chap, go->chap_mdtype);
+	if (!go->neg_chap) {
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	    REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+	}
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+    }
+#endif /* EAP_SUPPORT */
+#if LQR_SUPPORT
+    REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+#endif /* LQR_SUPPORT */
+    REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+    REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+    REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+    REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+#ifdef HAVE_MULTILINK
+    REJCISHORT(CI_MRRU, neg_mrru, go->mrru);
+#endif /* HAVE_MULTILINK */
+    REJCIVOID(CI_SSNHF, neg_ssnhf);
+    REJCIENDP(CI_EPDISC, neg_endpoint, go->endpoint.class_,
+	      go->endpoint.value, go->endpoint.length);
+
+    /*
+     * If there are any remaining CIs, then this packet is bad.
+     */
+    if (len != 0)
+	goto bad;
+    /*
+     * Now we can update state.
+     */
+    if (f->state != PPP_FSM_OPENED)
+	*go = try_;
+    return 1;
+
+bad:
+    LCPDEBUG(("lcp_rejci: received bad Reject!"));
+    return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ *
+ * inp = Requested CIs
+ * lenp = Length of requested CIs
+ */
+static int lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    lcp_options *ho = &pcb->lcp_hisoptions;
+    lcp_options *ao = &pcb->lcp_allowoptions;
+    u_char *cip, *next;		/* Pointer to current and next CIs */
+    int cilen, citype, cichar;	/* Parsed len, type, char value */
+    u_short cishort;		/* Parsed short value */
+    u32_t cilong;		/* Parse long value */
+    int rc = CONFACK;		/* Final packet return code */
+    int orc;			/* Individual option return code */
+    u_char *p;			/* Pointer to next char to parse */
+    u_char *rejp;		/* Pointer to next char in reject frame */
+    struct pbuf *nakp;          /* Nak buffer */
+    u_char *nakoutp;		/* Pointer to next char in Nak frame */
+    int l = *lenp;		/* Length left */
+
+    /*
+     * Reset all his options.
+     */
+    BZERO(ho, sizeof(*ho));
+
+    /*
+     * Process all his options.
+     */
+    next = inp;
+    nakp = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_CTRL_PBUF_MAX_SIZE), PPP_CTRL_PBUF_TYPE);
+    if(NULL == nakp)
+        return 0;
+    if(nakp->tot_len != nakp->len) {
+        pbuf_free(nakp);
+        return 0;
+    }
+
+    nakoutp = (u_char*)nakp->payload;
+    rejp = inp;
+    while (l) {
+	orc = CONFACK;			/* Assume success */
+	cip = p = next;			/* Remember begining of CI */
+	if (l < 2 ||			/* Not enough data for CI header or */
+	    p[1] < 2 ||			/*  CI length too small or */
+	    p[1] > l) {			/*  CI length too big? */
+	    LCPDEBUG(("lcp_reqci: bad CI length!"));
+	    orc = CONFREJ;		/* Reject bad CI */
+	    cilen = l;			/* Reject till end of packet */
+	    l = 0;			/* Don't loop again */
+	    citype = 0;
+	    goto endswitch;
+	}
+	GETCHAR(citype, p);		/* Parse CI type */
+	GETCHAR(cilen, p);		/* Parse CI length */
+	l -= cilen;			/* Adjust remaining length */
+	next += cilen;			/* Step to next CI */
+
+	switch (citype) {		/* Check CI type */
+	case CI_MRU:
+	    if (!ao->neg_mru ||		/* Allow option? */
+		cilen != CILEN_SHORT) {	/* Check CI length */
+		orc = CONFREJ;		/* Reject CI */
+		break;
+	    }
+	    GETSHORT(cishort, p);	/* Parse MRU */
+
+	    /*
+	     * He must be able to receive at least our minimum.
+	     * No need to check a maximum.  If he sends a large number,
+	     * we'll just ignore it.
+	     */
+	    if (cishort < PPP_MINMRU) {
+		orc = CONFNAK;		/* Nak CI */
+		PUTCHAR(CI_MRU, nakoutp);
+		PUTCHAR(CILEN_SHORT, nakoutp);
+		PUTSHORT(PPP_MINMRU, nakoutp);	/* Give him a hint */
+		break;
+	    }
+	    ho->neg_mru = 1;		/* Remember he sent MRU */
+	    ho->mru = cishort;		/* And remember value */
+	    break;
+
+	case CI_ASYNCMAP:
+	    if (!ao->neg_asyncmap ||
+		cilen != CILEN_LONG) {
+		orc = CONFREJ;
+		break;
+	    }
+	    GETLONG(cilong, p);
+
+	    /*
+	     * Asyncmap must have set at least the bits
+	     * which are set in lcp_allowoptions[unit].asyncmap.
+	     */
+	    if ((ao->asyncmap & ~cilong) != 0) {
+		orc = CONFNAK;
+		PUTCHAR(CI_ASYNCMAP, nakoutp);
+		PUTCHAR(CILEN_LONG, nakoutp);
+		PUTLONG(ao->asyncmap | cilong, nakoutp);
+		break;
+	    }
+	    ho->neg_asyncmap = 1;
+	    ho->asyncmap = cilong;
+	    break;
+
+	case CI_AUTHTYPE:
+	    if (cilen < CILEN_SHORT ||
+		!(0
+#if PAP_SUPPORT
+		|| ao->neg_upap
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+		|| ao->neg_chap
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+		|| ao->neg_eap
+#endif /* EAP_SUPPORT */
+		)) {
+		/*
+		 * Reject the option if we're not willing to authenticate.
+		 */
+		ppp_dbglog("No auth is possible");
+		orc = CONFREJ;
+		break;
+	    }
+	    GETSHORT(cishort, p);
+
+	    /*
+	     * Authtype must be PAP, CHAP, or EAP.
+	     *
+	     * Note: if more than one of ao->neg_upap, ao->neg_chap, and
+	     * ao->neg_eap are set, and the peer sends a Configure-Request
+	     * with two or more authenticate-protocol requests, then we will
+	     * reject the second request.
+	     * Whether we end up doing CHAP, UPAP, or EAP depends then on
+	     * the ordering of the CIs in the peer's Configure-Request.
+             */
+
+#if PAP_SUPPORT
+	    if (cishort == PPP_PAP) {
+		/* we've already accepted CHAP or EAP */
+		if (0
+#if CHAP_SUPPORT
+		    || ho->neg_chap
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+		    || ho->neg_eap
+#endif /* EAP_SUPPORT */
+		    || cilen != CILEN_SHORT) {
+		    LCPDEBUG(("lcp_reqci: rcvd AUTHTYPE PAP, rejecting..."));
+		    orc = CONFREJ;
+		    break;
+		}
+		if (!ao->neg_upap) {	/* we don't want to do PAP */
+		    orc = CONFNAK;	/* NAK it and suggest CHAP or EAP */
+		    PUTCHAR(CI_AUTHTYPE, nakoutp);
+#if EAP_SUPPORT
+		    if (ao->neg_eap) {
+			PUTCHAR(CILEN_SHORT, nakoutp);
+			PUTSHORT(PPP_EAP, nakoutp);
+		    } else {
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT
+			PUTCHAR(CILEN_CHAP, nakoutp);
+			PUTSHORT(PPP_CHAP, nakoutp);
+			PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp);
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+		    }
+#endif /* EAP_SUPPORT */
+		    break;
+		}
+		ho->neg_upap = 1;
+		break;
+	    }
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+	    if (cishort == PPP_CHAP) {
+		/* we've already accepted PAP or EAP */
+		if (
+#if PAP_SUPPORT
+		    ho->neg_upap ||
+#endif /* PAP_SUPPORT */
+#if EAP_SUPPORT
+		    ho->neg_eap ||
+#endif /* EAP_SUPPORT */
+		    cilen != CILEN_CHAP) {
+		    LCPDEBUG(("lcp_reqci: rcvd AUTHTYPE CHAP, rejecting..."));
+		    orc = CONFREJ;
+		    break;
+		}
+		if (!ao->neg_chap) {	/* we don't want to do CHAP */
+		    orc = CONFNAK;	/* NAK it and suggest EAP or PAP */
+		    PUTCHAR(CI_AUTHTYPE, nakoutp);
+		    PUTCHAR(CILEN_SHORT, nakoutp);
+#if EAP_SUPPORT
+		    if (ao->neg_eap) {
+			PUTSHORT(PPP_EAP, nakoutp);
+		    } else
+#endif /* EAP_SUPPORT */
+#if PAP_SUPPORT
+		    if(1) {
+			PUTSHORT(PPP_PAP, nakoutp);
+		    }
+		    else
+#endif /* PAP_SUPPORT */
+		    {}
+		    break;
+		}
+		GETCHAR(cichar, p);	/* get digest type */
+		if (!(CHAP_CANDIGEST(ao->chap_mdtype, cichar))) {
+		    /*
+		     * We can't/won't do the requested type,
+		     * suggest something else.
+		     */
+		    orc = CONFNAK;
+		    PUTCHAR(CI_AUTHTYPE, nakoutp);
+		    PUTCHAR(CILEN_CHAP, nakoutp);
+		    PUTSHORT(PPP_CHAP, nakoutp);
+		    PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp);
+		    break;
+		}
+		ho->chap_mdtype = CHAP_MDTYPE_D(cichar); /* save md type */
+		ho->neg_chap = 1;
+		break;
+	    }
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+	    if (cishort == PPP_EAP) {
+		/* we've already accepted CHAP or PAP */
+		if (
+#if CHAP_SUPPORT
+		    ho->neg_chap ||
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+		    ho->neg_upap ||
+#endif /* PAP_SUPPORT */
+		    cilen != CILEN_SHORT) {
+		    LCPDEBUG(("lcp_reqci: rcvd AUTHTYPE EAP, rejecting..."));
+		    orc = CONFREJ;
+		    break;
+		}
+		if (!ao->neg_eap) {	/* we don't want to do EAP */
+		    orc = CONFNAK;	/* NAK it and suggest CHAP or PAP */
+		    PUTCHAR(CI_AUTHTYPE, nakoutp);
+#if CHAP_SUPPORT
+		    if (ao->neg_chap) {
+			PUTCHAR(CILEN_CHAP, nakoutp);
+			PUTSHORT(PPP_CHAP, nakoutp);
+			PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp);
+		    } else
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+		    if(1) {
+			PUTCHAR(CILEN_SHORT, nakoutp);
+			PUTSHORT(PPP_PAP, nakoutp);
+		    } else
+#endif /* PAP_SUPPORT */
+		    {}
+		    break;
+		}
+		ho->neg_eap = 1;
+		break;
+	    }
+#endif /* EAP_SUPPORT */
+
+	    /*
+	     * We don't recognize the protocol they're asking for.
+	     * Nak it with something we're willing to do.
+	     * (At this point we know ao->neg_upap || ao->neg_chap ||
+	     * ao->neg_eap.)
+	     */
+	    orc = CONFNAK;
+	    PUTCHAR(CI_AUTHTYPE, nakoutp);
+
+#if EAP_SUPPORT
+	    if (ao->neg_eap) {
+		PUTCHAR(CILEN_SHORT, nakoutp);
+		PUTSHORT(PPP_EAP, nakoutp);
+	    } else
+#endif /* EAP_SUPPORT */
+#if CHAP_SUPPORT
+	    if (ao->neg_chap) {
+		PUTCHAR(CILEN_CHAP, nakoutp);
+		PUTSHORT(PPP_CHAP, nakoutp);
+		PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp);
+	    } else
+#endif /* CHAP_SUPPORT */
+#if PAP_SUPPORT
+	    if(1) {
+		PUTCHAR(CILEN_SHORT, nakoutp);
+		PUTSHORT(PPP_PAP, nakoutp);
+	    } else
+#endif /* PAP_SUPPORT */
+	    {}
+	    break;
+
+#if LQR_SUPPORT
+	case CI_QUALITY:
+	    if (!ao->neg_lqr ||
+		cilen != CILEN_LQR) {
+		orc = CONFREJ;
+		break;
+	    }
+
+	    GETSHORT(cishort, p);
+	    GETLONG(cilong, p);
+
+	    /*
+	     * Check the protocol and the reporting period.
+	     * XXX When should we Nak this, and what with?
+	     */
+	    if (cishort != PPP_LQR) {
+		orc = CONFNAK;
+		PUTCHAR(CI_QUALITY, nakoutp);
+		PUTCHAR(CILEN_LQR, nakoutp);
+		PUTSHORT(PPP_LQR, nakoutp);
+		PUTLONG(ao->lqr_period, nakoutp);
+		break;
+	    }
+	    break;
+#endif /* LQR_SUPPORT */
+
+	case CI_MAGICNUMBER:
+	    if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+		cilen != CILEN_LONG) {
+		orc = CONFREJ;
+		break;
+	    }
+	    GETLONG(cilong, p);
+
+	    /*
+	     * He must have a different magic number.
+	     */
+	    if (go->neg_magicnumber &&
+		cilong == go->magicnumber) {
+		cilong = magic();	/* Don't put magic() inside macro! */
+		orc = CONFNAK;
+		PUTCHAR(CI_MAGICNUMBER, nakoutp);
+		PUTCHAR(CILEN_LONG, nakoutp);
+		PUTLONG(cilong, nakoutp);
+		break;
+	    }
+	    ho->neg_magicnumber = 1;
+	    ho->magicnumber = cilong;
+	    break;
+
+
+	case CI_PCOMPRESSION:
+	    if (!ao->neg_pcompression ||
+		cilen != CILEN_VOID) {
+		orc = CONFREJ;
+		break;
+	    }
+	    ho->neg_pcompression = 1;
+	    break;
+
+	case CI_ACCOMPRESSION:
+	    if (!ao->neg_accompression ||
+		cilen != CILEN_VOID) {
+		orc = CONFREJ;
+		break;
+	    }
+	    ho->neg_accompression = 1;
+	    break;
+
+#ifdef HAVE_MULTILINK
+	case CI_MRRU:
+	    if (!ao->neg_mrru
+		|| !multilink
+		|| cilen != CILEN_SHORT) {
+		orc = CONFREJ;
+		break;
+	    }
+
+	    GETSHORT(cishort, p);
+	    /* possibly should insist on a minimum/maximum MRRU here */
+	    ho->neg_mrru = 1;
+	    ho->mrru = cishort;
+	    break;
+#endif /* HAVE_MULTILINK */
+
+	case CI_SSNHF:
+	    if (!ao->neg_ssnhf
+#ifdef HAVE_MULTILINK
+		|| !multilink
+#endif /* HAVE_MULTILINK */
+		|| cilen != CILEN_VOID) {
+		orc = CONFREJ;
+		break;
+	    }
+	    ho->neg_ssnhf = 1;
+	    break;
+
+	case CI_EPDISC:
+	    if (!ao->neg_endpoint ||
+		cilen < CILEN_CHAR ||
+		cilen > CILEN_CHAR + MAX_ENDP_LEN) {
+		orc = CONFREJ;
+		break;
+	    }
+	    GETCHAR(cichar, p);
+	    cilen -= CILEN_CHAR;
+	    ho->neg_endpoint = 1;
+	    ho->endpoint.class_ = cichar;
+	    ho->endpoint.length = cilen;
+	    MEMCPY(ho->endpoint.value, p, cilen);
+	    INCPTR(cilen, p);
+	    break;
+
+	default:
+	    LCPDEBUG(("lcp_reqci: rcvd unknown option %d", citype));
+	    orc = CONFREJ;
+	    break;
+	}
+
+endswitch:
+	if (orc == CONFACK &&		/* Good CI */
+	    rc != CONFACK)		/*  but prior CI wasnt? */
+	    continue;			/* Don't send this one */
+
+	if (orc == CONFNAK) {		/* Nak this CI? */
+	    if (reject_if_disagree	/* Getting fed up with sending NAKs? */
+		&& citype != CI_MAGICNUMBER) {
+		orc = CONFREJ;		/* Get tough if so */
+	    } else {
+		if (rc == CONFREJ)	/* Rejecting prior CI? */
+		    continue;		/* Don't send this one */
+		rc = CONFNAK;
+	    }
+	}
+	if (orc == CONFREJ) {		/* Reject this CI */
+	    rc = CONFREJ;
+	    if (cip != rejp)		/* Need to move rejected CI? */
+		MEMCPY(rejp, cip, cilen); /* Move it */
+	    INCPTR(cilen, rejp);	/* Update output pointer */
+	}
+    }
+
+    /*
+     * If we wanted to send additional NAKs (for unsent CIs), the
+     * code would go here.  The extra NAKs would go at *nakoutp.
+     * At present there are no cases where we want to ask the
+     * peer to negotiate an option.
+     */
+
+    switch (rc) {
+    case CONFACK:
+	*lenp = next - inp;
+	break;
+    case CONFNAK:
+	/*
+	 * Copy the Nak'd options from the nak buffer to the caller's buffer.
+	 */
+	*lenp = nakoutp - (u_char*)nakp->payload;
+	MEMCPY(inp, nakp->payload, *lenp);
+	break;
+    case CONFREJ:
+	*lenp = rejp - inp;
+	break;
+    default:
+	break;
+    }
+
+    pbuf_free(nakp);
+    LCPDEBUG(("lcp_reqci: returning CONF%s.", CODENAME(rc)));
+    return (rc);			/* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void lcp_up(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *wo = &pcb->lcp_wantoptions;
+    lcp_options *ho = &pcb->lcp_hisoptions;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    lcp_options *ao = &pcb->lcp_allowoptions;
+    int mtu, mru;
+
+    if (!go->neg_magicnumber)
+	go->magicnumber = 0;
+    if (!ho->neg_magicnumber)
+	ho->magicnumber = 0;
+
+    /*
+     * Set our MTU to the smaller of the MTU we wanted and
+     * the MRU our peer wanted.  If we negotiated an MRU,
+     * set our MRU to the larger of value we wanted and
+     * the value we got in the negotiation.
+     * Note on the MTU: the link MTU can be the MRU the peer wanted,
+     * the interface MTU is set to the lowest of that, the
+     * MTU we want to use, and our link MRU.
+     */
+    mtu = ho->neg_mru? ho->mru: PPP_MRU;
+    mru = go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU;
+#ifdef HAVE_MULTILINK
+    if (!(multilink && go->neg_mrru && ho->neg_mrru))
+#endif /* HAVE_MULTILINK */
+	netif_set_mtu(pcb, LWIP_MIN(LWIP_MIN(mtu, mru), ao->mru));
+    ppp_send_config(pcb, mtu,
+		    (ho->neg_asyncmap? ho->asyncmap: 0xffffffff),
+		    ho->neg_pcompression, ho->neg_accompression);
+    ppp_recv_config(pcb, mru,
+		    (pcb->settings.lax_recv? 0: go->neg_asyncmap? go->asyncmap: 0xffffffff),
+		    go->neg_pcompression, go->neg_accompression);
+
+    if (ho->neg_mru)
+	pcb->peer_mru = ho->mru;
+
+    lcp_echo_lowerup(f->pcb);  /* Enable echo messages */
+
+    link_established(pcb);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void lcp_down(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+
+    lcp_echo_lowerdown(f->pcb);
+
+    link_down(pcb);
+
+    ppp_send_config(pcb, PPP_MRU, 0xffffffff, 0, 0);
+    ppp_recv_config(pcb, PPP_MRU,
+		    (go->neg_asyncmap? go->asyncmap: 0xffffffff),
+		    go->neg_pcompression, go->neg_accompression);
+    pcb->peer_mru = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void lcp_starting(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    link_required(pcb);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void lcp_finished(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    link_terminated(pcb);
+}
+
+
+#if PRINTPKT_SUPPORT
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static const char* const lcp_codenames[] = {
+    "ConfReq", "ConfAck", "ConfNak", "ConfRej",
+    "TermReq", "TermAck", "CodeRej", "ProtRej",
+    "EchoReq", "EchoRep", "DiscReq", "Ident",
+    "TimeRem"
+};
+
+static int lcp_printpkt(const u_char *p, int plen,
+		void (*printer) (void *, const char *, ...), void *arg) {
+    int code, id, len, olen, i;
+    const u_char *pstart, *optend;
+    u_short cishort;
+    u32_t cilong;
+
+    if (plen < HEADERLEN)
+	return 0;
+    pstart = p;
+    GETCHAR(code, p);
+    GETCHAR(id, p);
+    GETSHORT(len, p);
+    if (len < HEADERLEN || len > plen)
+	return 0;
+
+   if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(lcp_codenames))
+	printer(arg, " %s", lcp_codenames[code-1]);
+    else
+	printer(arg, " code=0x%x", code);
+    printer(arg, " id=0x%x", id);
+    len -= HEADERLEN;
+    switch (code) {
+    case CONFREQ:
+    case CONFACK:
+    case CONFNAK:
+    case CONFREJ:
+	/* print option list */
+	while (len >= 2) {
+	    GETCHAR(code, p);
+	    GETCHAR(olen, p);
+	    p -= 2;
+	    if (olen < 2 || olen > len) {
+		break;
+	    }
+	    printer(arg, " <");
+	    len -= olen;
+	    optend = p + olen;
+	    switch (code) {
+	    case CI_MRU:
+		if (olen == CILEN_SHORT) {
+		    p += 2;
+		    GETSHORT(cishort, p);
+		    printer(arg, "mru %d", cishort);
+		}
+		break;
+	    case CI_ASYNCMAP:
+		if (olen == CILEN_LONG) {
+		    p += 2;
+		    GETLONG(cilong, p);
+		    printer(arg, "asyncmap 0x%x", cilong);
+		}
+		break;
+	    case CI_AUTHTYPE:
+		if (olen >= CILEN_SHORT) {
+		    p += 2;
+		    printer(arg, "auth ");
+		    GETSHORT(cishort, p);
+		    switch (cishort) {
+#if PAP_SUPPORT
+		    case PPP_PAP:
+			printer(arg, "pap");
+			break;
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+		    case PPP_CHAP:
+			printer(arg, "chap");
+			if (p < optend) {
+			    switch (*p) {
+			    case CHAP_MD5:
+				printer(arg, " MD5");
+				++p;
+				break;
+#if MSCHAP_SUPPORT
+			    case CHAP_MICROSOFT:
+				printer(arg, " MS");
+				++p;
+				break;
+
+			    case CHAP_MICROSOFT_V2:
+				printer(arg, " MS-v2");
+				++p;
+				break;
+#endif /* MSCHAP_SUPPORT */
+			    default:
+				break;
+			    }
+			}
+			break;
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+		    case PPP_EAP:
+			printer(arg, "eap");
+			break;
+#endif /* EAP_SUPPORT */
+		    default:
+			printer(arg, "0x%x", cishort);
+		    }
+		}
+		break;
+#if LQR_SUPPORT
+	    case CI_QUALITY:
+		if (olen >= CILEN_SHORT) {
+		    p += 2;
+		    printer(arg, "quality ");
+		    GETSHORT(cishort, p);
+		    switch (cishort) {
+		    case PPP_LQR:
+			printer(arg, "lqr");
+			break;
+		    default:
+			printer(arg, "0x%x", cishort);
+		    }
+		}
+		break;
+#endif /* LQR_SUPPORT */
+	    case CI_CALLBACK:
+		if (olen >= CILEN_CHAR) {
+		    p += 2;
+		    printer(arg, "callback ");
+		    GETCHAR(cishort, p);
+		    switch (cishort) {
+		    case CBCP_OPT:
+			printer(arg, "CBCP");
+			break;
+		    default:
+			printer(arg, "0x%x", cishort);
+		    }
+		}
+		break;
+	    case CI_MAGICNUMBER:
+		if (olen == CILEN_LONG) {
+		    p += 2;
+		    GETLONG(cilong, p);
+		    printer(arg, "magic 0x%x", cilong);
+		}
+		break;
+	    case CI_PCOMPRESSION:
+		if (olen == CILEN_VOID) {
+		    p += 2;
+		    printer(arg, "pcomp");
+		}
+		break;
+	    case CI_ACCOMPRESSION:
+		if (olen == CILEN_VOID) {
+		    p += 2;
+		    printer(arg, "accomp");
+		}
+		break;
+	    case CI_MRRU:
+		if (olen == CILEN_SHORT) {
+		    p += 2;
+		    GETSHORT(cishort, p);
+		    printer(arg, "mrru %d", cishort);
+		}
+		break;
+	    case CI_SSNHF:
+		if (olen == CILEN_VOID) {
+		    p += 2;
+		    printer(arg, "ssnhf");
+		}
+		break;
+	    case CI_EPDISC:
+#ifdef HAVE_MULTILINK
+		if (olen >= CILEN_CHAR) {
+		    struct epdisc epd;
+		    p += 2;
+		    GETCHAR(epd.class, p);
+		    epd.length = olen - CILEN_CHAR;
+		    if (epd.length > MAX_ENDP_LEN)
+			epd.length = MAX_ENDP_LEN;
+		    if (epd.length > 0) {
+			MEMCPY(epd.value, p, epd.length);
+			p += epd.length;
+		    }
+		    printer(arg, "endpoint [%s]", epdisc_to_str(&epd));
+		}
+#else
+		printer(arg, "endpoint");
+#endif
+		break;
+	    default:
+		break;
+	    }
+	    while (p < optend) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	    }
+	    printer(arg, ">");
+	}
+	break;
+
+    case TERMACK:
+    case TERMREQ:
+	if (len > 0 && *p >= ' ' && *p < 0x7f) {
+	    printer(arg, " ");
+	    ppp_print_string(p, len, printer, arg);
+	    p += len;
+	    len = 0;
+	}
+	break;
+
+    case ECHOREQ:
+    case ECHOREP:
+    case DISCREQ:
+	if (len >= 4) {
+	    GETLONG(cilong, p);
+	    printer(arg, " magic=0x%x", cilong);
+	    len -= 4;
+	}
+	break;
+
+    case IDENTIF:
+    case TIMEREM:
+	if (len >= 4) {
+	    GETLONG(cilong, p);
+	    printer(arg, " magic=0x%x", cilong);
+	    len -= 4;
+	}
+	if (code == TIMEREM) {
+	    if (len < 4)
+		break;
+	    GETLONG(cilong, p);
+	    printer(arg, " seconds=%u", cilong);
+	    len -= 4;
+	}
+	if (len > 0) {
+	    printer(arg, " ");
+	    ppp_print_string(p, len, printer, arg);
+	    p += len;
+	    len = 0;
+	}
+	break;
+    default:
+	break;
+    }
+
+    /* print the rest of the bytes in the packet */
+    for (i = 0; i < len && i < 32; ++i) {
+	GETCHAR(code, p);
+	printer(arg, " %.2x", code);
+    }
+    if (i < len) {
+	printer(arg, " ...");
+	p += len - i;
+    }
+
+    return p - pstart;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+
+static void LcpLinkFailure(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    if (f->state == PPP_FSM_OPENED) {
+	ppp_info("No response to %d echo-requests", pcb->lcp_echos_pending);
+        ppp_notice("Serial link appears to be disconnected.");
+	pcb->err_code = PPPERR_PEERDEAD;
+	lcp_close(pcb, "Peer not responding");
+    }
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+
+static void LcpEchoCheck(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+
+    LcpSendEchoRequest (f);
+    if (f->state != PPP_FSM_OPENED)
+	return;
+
+    /*
+     * Start the timer for the next interval.
+     */
+    if (pcb->lcp_echo_timer_running)
+	ppp_warn("assertion lcp_echo_timer_running==0 failed");
+    TIMEOUT (LcpEchoTimeout, f, pcb->settings.lcp_echo_interval);
+    pcb->lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+
+static void LcpEchoTimeout(void *arg) {
+    fsm *f = (fsm*)arg;
+    ppp_pcb *pcb = f->pcb;
+    if (pcb->lcp_echo_timer_running != 0) {
+        pcb->lcp_echo_timer_running = 0;
+        LcpEchoCheck ((fsm *) arg);
+    }
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+
+static void lcp_received_echo_reply(fsm *f, int id, u_char *inp, int len) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    u32_t magic_val;
+    LWIP_UNUSED_ARG(id);
+
+    /* Check the magic number - don't count replies from ourselves. */
+    if (len < 4) {
+	ppp_dbglog("lcp: received short Echo-Reply, length %d", len);
+	return;
+    }
+    GETLONG(magic_val, inp);
+    if (go->neg_magicnumber
+	&& magic_val == go->magicnumber) {
+	ppp_warn("appear to have received our own echo-reply!");
+	return;
+    }
+
+    /* Reset the number of outstanding echo frames */
+    pcb->lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+
+static void LcpSendEchoRequest(fsm *f) {
+    ppp_pcb *pcb = f->pcb;
+    lcp_options *go = &pcb->lcp_gotoptions;
+    u32_t lcp_magic;
+    u_char pkt[4], *pktp;
+
+    /*
+     * Detect the failure of the peer at this point.
+     */
+    if (pcb->settings.lcp_echo_fails != 0) {
+        if (pcb->lcp_echos_pending >= pcb->settings.lcp_echo_fails) {
+            LcpLinkFailure(f);
+            pcb->lcp_echos_pending = 0;
+	}
+    }
+
+#if PPP_LCP_ADAPTIVE
+    /*
+     * If adaptive echos have been enabled, only send the echo request if
+     * no traffic was received since the last one.
+     */
+    if (pcb->settings.lcp_echo_adaptive) {
+	static unsigned int last_pkts_in = 0;
+
+#if PPP_STATS_SUPPORT
+	update_link_stats(f->unit);
+	link_stats_valid = 0;
+#endif /* PPP_STATS_SUPPORT */
+
+	if (link_stats.pkts_in != last_pkts_in) {
+	    last_pkts_in = link_stats.pkts_in;
+	    return;
+	}
+    }
+#endif
+
+    /*
+     * Make and send the echo request frame.
+     */
+    if (f->state == PPP_FSM_OPENED) {
+        lcp_magic = go->magicnumber;
+	pktp = pkt;
+	PUTLONG(lcp_magic, pktp);
+        fsm_sdata(f, ECHOREQ, pcb->lcp_echo_number++, pkt, pktp - pkt);
+	++pcb->lcp_echos_pending;
+    }
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerup(ppp_pcb *pcb) {
+    fsm *f = &pcb->lcp_fsm;
+
+    /* Clear the parameters for generating echo frames */
+    pcb->lcp_echos_pending      = 0;
+    pcb->lcp_echo_number        = 0;
+    pcb->lcp_echo_timer_running = 0;
+  
+    /* If a timeout interval is specified then start the timer */
+    if (pcb->settings.lcp_echo_interval != 0)
+        LcpEchoCheck (f);
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerdown(ppp_pcb *pcb) {
+    fsm *f = &pcb->lcp_fsm;
+
+    if (pcb->lcp_echo_timer_running != 0) {
+        UNTIMEOUT (LcpEchoTimeout, f);
+        pcb->lcp_echo_timer_running = 0;
+    }
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/magic.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/magic.c
new file mode 100644
index 000000000..d0d87c5e5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/magic.c
@@ -0,0 +1,294 @@
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/magic.h"
+
+#if PPP_MD5_RANDM /* Using MD5 for better randomness if enabled */
+
+#include "netif/ppp/pppcrypt.h"
+
+#define MD5_HASH_SIZE 16
+static char magic_randpool[MD5_HASH_SIZE];   /* Pool of randomness. */
+static long magic_randcount;      /* Pseudo-random incrementer */
+static u32_t magic_randomseed;    /* Seed used for random number generation. */
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+static void magic_churnrand(char *rand_data, u32_t rand_len) {
+  lwip_md5_context md5_ctx;
+
+  /* LWIP_DEBUGF(LOG_INFO, ("magic_churnrand: %u@%P\n", rand_len, rand_data)); */
+  lwip_md5_init(&md5_ctx);
+  lwip_md5_starts(&md5_ctx);
+  lwip_md5_update(&md5_ctx, (u_char *)magic_randpool, sizeof(magic_randpool));
+  if (rand_data) {
+    lwip_md5_update(&md5_ctx, (u_char *)rand_data, rand_len);
+  } else {
+    struct {
+      /* INCLUDE fields for any system sources of randomness */
+      u32_t jiffies;
+#ifdef LWIP_RAND
+      u32_t rand;
+#endif /* LWIP_RAND */
+    } sys_data;
+    magic_randomseed += sys_jiffies();
+    sys_data.jiffies = magic_randomseed;
+#ifdef LWIP_RAND
+    sys_data.rand = LWIP_RAND();
+#endif /* LWIP_RAND */
+    /* Load sys_data fields here. */
+    lwip_md5_update(&md5_ctx, (u_char *)&sys_data, sizeof(sys_data));
+  }
+  lwip_md5_finish(&md5_ctx, (u_char *)magic_randpool);
+  lwip_md5_free(&md5_ctx);
+/*  LWIP_DEBUGF(LOG_INFO, ("magic_churnrand: -> 0\n")); */
+}
+
+/*
+ * Initialize the random number generator.
+ */
+void magic_init(void) {
+  magic_churnrand(NULL, 0);
+}
+
+/*
+ * Randomize our random seed value.
+ */
+void magic_randomize(void) {
+  magic_churnrand(NULL, 0);
+}
+
+/*
+ * magic_random_bytes - Fill a buffer with random bytes.
+ *
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using magic_churnrand().
+ * Note: It's important that there be sufficient randomness in magic_randpool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call magic_churnrand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  magic_randcount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void magic_random_bytes(unsigned char *buf, u32_t buf_len) {
+  lwip_md5_context md5_ctx;
+  u_char tmp[MD5_HASH_SIZE];
+  u32_t n;
+
+  while (buf_len > 0) {
+    lwip_md5_init(&md5_ctx);
+    lwip_md5_starts(&md5_ctx);
+    lwip_md5_update(&md5_ctx, (u_char *)magic_randpool, sizeof(magic_randpool));
+    lwip_md5_update(&md5_ctx, (u_char *)&magic_randcount, sizeof(magic_randcount));
+    lwip_md5_finish(&md5_ctx, tmp);
+    lwip_md5_free(&md5_ctx);
+    magic_randcount++;
+    n = LWIP_MIN(buf_len, MD5_HASH_SIZE);
+    MEMCPY(buf, tmp, n);
+    buf += n;
+    buf_len -= n;
+  }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t magic(void) {
+  u32_t new_rand;
+
+  magic_random_bytes((unsigned char *)&new_rand, sizeof(new_rand));
+
+  return new_rand;
+}
+
+#else /* PPP_MD5_RANDM */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#ifndef LWIP_RAND
+static int  magic_randomized;       /* Set when truely randomized. */
+#endif /* LWIP_RAND */
+static u32_t magic_randomseed;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void magic_init(void) {
+  magic_randomseed += sys_jiffies();
+#ifndef LWIP_RAND
+  /* Initialize the Borland random number generator. */
+  srand((unsigned)magic_randomseed);
+#endif /* LWIP_RAND */
+}
+
+/*
+ * magic_init - Initialize the magic number generator.
+ *
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void magic_randomize(void) {
+#ifndef LWIP_RAND
+  if (!magic_randomized) {
+    magic_randomized = !0;
+    magic_init();
+    /* The initialization function also updates the seed. */
+  } else {
+#endif /* LWIP_RAND */
+    magic_randomseed += sys_jiffies();
+#ifndef LWIP_RAND
+  }
+#endif /* LWIP_RAND */
+}
+
+/*
+ * Return a new random number.
+ *
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events.
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t magic(void) {
+#ifdef LWIP_RAND
+  return LWIP_RAND() + magic_randomseed;
+#else /* LWIP_RAND */
+  return ((u32_t)rand() << 16) + (u32_t)rand() + magic_randomseed;
+#endif /* LWIP_RAND */
+}
+
+/*
+ * magic_random_bytes - Fill a buffer with random bytes.
+ */
+void magic_random_bytes(unsigned char *buf, u32_t buf_len) {
+  u32_t new_rand, n;
+
+  while (buf_len > 0) {
+    new_rand = magic();
+    n = LWIP_MIN(buf_len, sizeof(new_rand));
+    MEMCPY(buf, &new_rand, n);
+    buf += n;
+    buf_len -= n;
+  }
+}
+#endif /* PPP_MD5_RANDM */
+
+/*
+ * Return a new random number between 0 and (2^pow)-1 included.
+ */
+u32_t magic_pow(u8_t pow) {
+  return magic() & ~(~0UL<<pow);
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/mppe.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/mppe.c
new file mode 100644
index 000000000..4cca89dec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/mppe.c
@@ -0,0 +1,412 @@
+/*
+ * mppe.c - interface MPPE to the PPP code.
+ *
+ * By Frank Cusack <fcusack@fcusack.com>.
+ * Copyright (c) 2002,2003,2004 Google, Inc.
+ * All rights reserved.
+ *
+ * License:
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied.
+ *
+ * Changelog:
+ *      08/12/05 - Matt Domsch <Matt_Domsch@dell.com>
+ *                 Only need extra skb padding on transmit, not receive.
+ *      06/18/04 - Matt Domsch <Matt_Domsch@dell.com>, Oleg Makarenko <mole@quadra.ru>
+ *                 Use Linux kernel 2.6 arc4 and sha1 routines rather than
+ *                 providing our own.
+ *      2/15/04 - TS: added #include <version.h> and testing for Kernel
+ *                    version before using
+ *                    MOD_DEC_USAGE_COUNT/MOD_INC_USAGE_COUNT which are
+ *                    deprecated in 2.6
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MPPE_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+#include <string.h>
+
+#include "lwip/err.h"
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/ccp.h"
+#include "netif/ppp/mppe.h"
+#include "netif/ppp/pppdebug.h"
+#include "netif/ppp/pppcrypt.h"
+
+#define SHA1_SIGNATURE_SIZE 20
+
+/* ppp_mppe_state.bits definitions */
+#define MPPE_BIT_A	0x80	/* Encryption table were (re)inititalized */
+#define MPPE_BIT_B	0x40	/* MPPC only (not implemented) */
+#define MPPE_BIT_C	0x20	/* MPPC only (not implemented) */
+#define MPPE_BIT_D	0x10	/* This is an encrypted frame */
+
+#define MPPE_BIT_FLUSHED	MPPE_BIT_A
+#define MPPE_BIT_ENCRYPTED	MPPE_BIT_D
+
+#define MPPE_BITS(p) ((p)[0] & 0xf0)
+#define MPPE_CCOUNT(p) ((((p)[0] & 0x0f) << 8) + (p)[1])
+#define MPPE_CCOUNT_SPACE 0x1000	/* The size of the ccount space */
+
+#define MPPE_OVHD	2	/* MPPE overhead/packet */
+#define SANITY_MAX	1600	/* Max bogon factor we will tolerate */
+
+/*
+ * Perform the MPPE rekey algorithm, from RFC 3078, sec. 7.3.
+ * Well, not what's written there, but rather what they meant.
+ */
+static void mppe_rekey(ppp_mppe_state * state, int initial_key)
+{
+	lwip_sha1_context sha1_ctx;
+	u8_t sha1_digest[SHA1_SIGNATURE_SIZE];
+
+	/*
+	 * Key Derivation, from RFC 3078, RFC 3079.
+	 * Equivalent to Get_Key() for MS-CHAP as described in RFC 3079.
+	 */
+	lwip_sha1_init(&sha1_ctx);
+	lwip_sha1_starts(&sha1_ctx);
+	lwip_sha1_update(&sha1_ctx, state->master_key, state->keylen);
+	lwip_sha1_update(&sha1_ctx, mppe_sha1_pad1, SHA1_PAD_SIZE);
+	lwip_sha1_update(&sha1_ctx, state->session_key, state->keylen);
+	lwip_sha1_update(&sha1_ctx, mppe_sha1_pad2, SHA1_PAD_SIZE);
+	lwip_sha1_finish(&sha1_ctx, sha1_digest);
+	lwip_sha1_free(&sha1_ctx);
+	MEMCPY(state->session_key, sha1_digest, state->keylen);
+
+	if (!initial_key) {
+		lwip_arc4_init(&state->arc4);
+		lwip_arc4_setup(&state->arc4, sha1_digest, state->keylen);
+		lwip_arc4_crypt(&state->arc4, state->session_key, state->keylen);
+		lwip_arc4_free(&state->arc4);
+	}
+	if (state->keylen == 8) {
+		/* See RFC 3078 */
+		state->session_key[0] = 0xd1;
+		state->session_key[1] = 0x26;
+		state->session_key[2] = 0x9e;
+	}
+	lwip_arc4_init(&state->arc4);
+	lwip_arc4_setup(&state->arc4, state->session_key, state->keylen);
+}
+
+/*
+ * Set key, used by MSCHAP before mppe_init() is actually called by CCP so we
+ * don't have to keep multiple copies of keys.
+ */
+void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key) {
+	LWIP_UNUSED_ARG(pcb);
+	MEMCPY(state->master_key, key, MPPE_MAX_KEY_LEN);
+}
+
+/*
+ * Initialize (de)compressor state.
+ */
+void
+mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options)
+{
+#if PPP_DEBUG
+	const u8_t *debugstr = (const u8_t*)"mppe_comp_init";
+	if (&pcb->mppe_decomp == state) {
+	    debugstr = (const u8_t*)"mppe_decomp_init";
+	}
+#endif /* PPP_DEBUG */
+
+	/* Save keys. */
+	MEMCPY(state->session_key, state->master_key, sizeof(state->master_key));
+
+	if (options & MPPE_OPT_128)
+		state->keylen = 16;
+	else if (options & MPPE_OPT_40)
+		state->keylen = 8;
+	else {
+		PPPDEBUG(LOG_DEBUG, ("%s[%d]: unknown key length\n", debugstr,
+			pcb->netif->num));
+		lcp_close(pcb, "MPPE required but peer negotiation failed");
+		return;
+	}
+	if (options & MPPE_OPT_STATEFUL)
+		state->stateful = 1;
+
+	/* Generate the initial session key. */
+	mppe_rekey(state, 1);
+
+#if PPP_DEBUG
+	{
+		int i;
+		char mkey[sizeof(state->master_key) * 2 + 1];
+		char skey[sizeof(state->session_key) * 2 + 1];
+
+		PPPDEBUG(LOG_DEBUG, ("%s[%d]: initialized with %d-bit %s mode\n",
+		       debugstr, pcb->netif->num, (state->keylen == 16) ? 128 : 40,
+		       (state->stateful) ? "stateful" : "stateless"));
+
+		for (i = 0; i < (int)sizeof(state->master_key); i++)
+			sprintf(mkey + i * 2, "%02x", state->master_key[i]);
+		for (i = 0; i < (int)sizeof(state->session_key); i++)
+			sprintf(skey + i * 2, "%02x", state->session_key[i]);
+		PPPDEBUG(LOG_DEBUG,
+		       ("%s[%d]: keys: master: %s initial session: %s\n",
+		       debugstr, pcb->netif->num, mkey, skey));
+	}
+#endif /* PPP_DEBUG */
+
+	/*
+	 * Initialize the coherency count.  The initial value is not specified
+	 * in RFC 3078, but we can make a reasonable assumption that it will
+	 * start at 0.  Setting it to the max here makes the comp/decomp code
+	 * do the right thing (determined through experiment).
+	 */
+	state->ccount = MPPE_CCOUNT_SPACE - 1;
+
+	/*
+	 * Note that even though we have initialized the key table, we don't
+	 * set the FLUSHED bit.  This is contrary to RFC 3078, sec. 3.1.
+	 */
+	state->bits = MPPE_BIT_ENCRYPTED;
+}
+
+/*
+ * We received a CCP Reset-Request (actually, we are sending a Reset-Ack),
+ * tell the compressor to rekey.  Note that we MUST NOT rekey for
+ * every CCP Reset-Request; we only rekey on the next xmit packet.
+ * We might get multiple CCP Reset-Requests if our CCP Reset-Ack is lost.
+ * So, rekeying for every CCP Reset-Request is broken as the peer will not
+ * know how many times we've rekeyed.  (If we rekey and THEN get another
+ * CCP Reset-Request, we must rekey again.)
+ */
+void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state)
+{
+	LWIP_UNUSED_ARG(pcb);
+	state->bits |= MPPE_BIT_FLUSHED;
+}
+
+/*
+ * Compress (encrypt) a packet.
+ * It's strange to call this a compressor, since the output is always
+ * MPPE_OVHD + 2 bytes larger than the input.
+ */
+err_t
+mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol)
+{
+	struct pbuf *n, *np;
+	u8_t *pl;
+	err_t err;
+
+	LWIP_UNUSED_ARG(pcb);
+
+	/* TCP stack requires that we don't change the packet payload, therefore we copy
+	 * the whole packet before encryption.
+	 */
+	np = pbuf_alloc(PBUF_RAW, MPPE_OVHD + sizeof(protocol) + (*pb)->tot_len, PBUF_RAM);
+	if (!np) {
+		return ERR_MEM;
+	}
+
+	/* Hide MPPE header + protocol */
+	pbuf_remove_header(np, MPPE_OVHD + sizeof(protocol));
+
+	if ((err = pbuf_copy(np, *pb)) != ERR_OK) {
+		pbuf_free(np);
+		return err;
+	}
+
+	/* Reveal MPPE header + protocol */
+	pbuf_add_header(np, MPPE_OVHD + sizeof(protocol));
+
+	*pb = np;
+	pl = (u8_t*)np->payload;
+
+	state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE;
+	PPPDEBUG(LOG_DEBUG, ("mppe_compress[%d]: ccount %d\n", pcb->netif->num, state->ccount));
+	/* FIXME: use PUT* macros */
+	pl[0] = state->ccount>>8;
+	pl[1] = state->ccount;
+
+	if (!state->stateful ||	/* stateless mode     */
+	    ((state->ccount & 0xff) == 0xff) ||	/* "flag" packet      */
+	    (state->bits & MPPE_BIT_FLUSHED)) {	/* CCP Reset-Request  */
+		/* We must rekey */
+		if (state->stateful) {
+			PPPDEBUG(LOG_DEBUG, ("mppe_compress[%d]: rekeying\n", pcb->netif->num));
+		}
+		mppe_rekey(state, 0);
+		state->bits |= MPPE_BIT_FLUSHED;
+	}
+	pl[0] |= state->bits;
+	state->bits &= ~MPPE_BIT_FLUSHED;	/* reset for next xmit */
+	pl += MPPE_OVHD;
+
+	/* Add protocol */
+	/* FIXME: add PFC support */
+	pl[0] = protocol >> 8;
+	pl[1] = protocol;
+
+	/* Hide MPPE header */
+	pbuf_remove_header(np, MPPE_OVHD);
+
+	/* Encrypt packet */
+	for (n = np; n != NULL; n = n->next) {
+		lwip_arc4_crypt(&state->arc4, (u8_t*)n->payload, n->len);
+		if (n->tot_len == n->len) {
+			break;
+		}
+	}
+
+	/* Reveal MPPE header */
+	pbuf_add_header(np, MPPE_OVHD);
+
+	return ERR_OK;
+}
+
+/*
+ * We received a CCP Reset-Ack.  Just ignore it.
+ */
+void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state)
+{
+	LWIP_UNUSED_ARG(pcb);
+	LWIP_UNUSED_ARG(state);
+	return;
+}
+
+/*
+ * Decompress (decrypt) an MPPE packet.
+ */
+err_t
+mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb)
+{
+	struct pbuf *n0 = *pb, *n;
+	u8_t *pl;
+	u16_t ccount;
+	u8_t flushed;
+
+	/* MPPE Header */
+	if (n0->len < MPPE_OVHD) {
+		PPPDEBUG(LOG_DEBUG,
+		       ("mppe_decompress[%d]: short pkt (%d)\n",
+		       pcb->netif->num, n0->len));
+		state->sanity_errors += 100;
+		goto sanity_error;
+	}
+
+	pl = (u8_t*)n0->payload;
+	flushed = MPPE_BITS(pl) & MPPE_BIT_FLUSHED;
+	ccount = MPPE_CCOUNT(pl);
+	PPPDEBUG(LOG_DEBUG, ("mppe_decompress[%d]: ccount %d\n",
+	       pcb->netif->num, ccount));
+
+	/* sanity checks -- terminate with extreme prejudice */
+	if (!(MPPE_BITS(pl) & MPPE_BIT_ENCRYPTED)) {
+		PPPDEBUG(LOG_DEBUG,
+		       ("mppe_decompress[%d]: ENCRYPTED bit not set!\n",
+		       pcb->netif->num));
+		state->sanity_errors += 100;
+		goto sanity_error;
+	}
+	if (!state->stateful && !flushed) {
+		PPPDEBUG(LOG_DEBUG, ("mppe_decompress[%d]: FLUSHED bit not set in "
+		       "stateless mode!\n", pcb->netif->num));
+		state->sanity_errors += 100;
+		goto sanity_error;
+	}
+	if (state->stateful && ((ccount & 0xff) == 0xff) && !flushed) {
+		PPPDEBUG(LOG_DEBUG, ("mppe_decompress[%d]: FLUSHED bit not set on "
+		       "flag packet!\n", pcb->netif->num));
+		state->sanity_errors += 100;
+		goto sanity_error;
+	}
+
+	/*
+	 * Check the coherency count.
+	 */
+
+	if (!state->stateful) {
+		/* Discard late packet */
+		if ((ccount - state->ccount) % MPPE_CCOUNT_SPACE > MPPE_CCOUNT_SPACE / 2) {
+			state->sanity_errors++;
+			goto sanity_error;
+		}
+
+		/* RFC 3078, sec 8.1.  Rekey for every packet. */
+		while (state->ccount != ccount) {
+			mppe_rekey(state, 0);
+			state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE;
+		}
+	} else {
+		/* RFC 3078, sec 8.2. */
+		if (!state->discard) {
+			/* normal state */
+			state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE;
+			if (ccount != state->ccount) {
+				/*
+				 * (ccount > state->ccount)
+				 * Packet loss detected, enter the discard state.
+				 * Signal the peer to rekey (by sending a CCP Reset-Request).
+				 */
+				state->discard = 1;
+				ccp_resetrequest(pcb);
+				return ERR_BUF;
+			}
+		} else {
+			/* discard state */
+			if (!flushed) {
+				/* ccp.c will be silent (no additional CCP Reset-Requests). */
+				return ERR_BUF;
+			} else {
+				/* Rekey for every missed "flag" packet. */
+				while ((ccount & ~0xff) !=
+				       (state->ccount & ~0xff)) {
+					mppe_rekey(state, 0);
+					state->ccount =
+					    (state->ccount +
+					     256) % MPPE_CCOUNT_SPACE;
+				}
+
+				/* reset */
+				state->discard = 0;
+				state->ccount = ccount;
+				/*
+				 * Another problem with RFC 3078 here.  It implies that the
+				 * peer need not send a Reset-Ack packet.  But RFC 1962
+				 * requires it.  Hopefully, M$ does send a Reset-Ack; even
+				 * though it isn't required for MPPE synchronization, it is
+				 * required to reset CCP state.
+				 */
+			}
+		}
+		if (flushed)
+			mppe_rekey(state, 0);
+	}
+
+	/* Hide MPPE header */
+	pbuf_remove_header(n0, MPPE_OVHD);
+
+	/* Decrypt the packet. */
+	for (n = n0; n != NULL; n = n->next) {
+		lwip_arc4_crypt(&state->arc4, (u8_t*)n->payload, n->len);
+		if (n->tot_len == n->len) {
+			break;
+		}
+	}
+
+	/* good packet credit */
+	state->sanity_errors >>= 1;
+
+	return ERR_OK;
+
+sanity_error:
+	if (state->sanity_errors >= SANITY_MAX) {
+		/*
+		 * Take LCP down if the peer is sending too many bogons.
+		 * We don't want to do this for a single or just a few
+		 * instances since it could just be due to packet corruption.
+		 */
+		lcp_close(pcb, "Too many MPPE errors");
+	}
+	return ERR_BUF;
+}
+
+#endif /* PPP_SUPPORT && MPPE_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/multilink.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/multilink.c
new file mode 100644
index 000000000..62014e8c8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/multilink.c
@@ -0,0 +1,609 @@
+/*
+ * multilink.c - support routines for multilink.
+ *
+ * Copyright (c) 2000-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && defined(HAVE_MULTILINK) /* don't build if not configured for use in lwipopts.h */
+
+/* Multilink support
+ *
+ * Multilink uses Samba TDB (Trivial Database Library), which
+ * we cannot port, because it needs a filesystem.
+ *
+ * We have to choose between doing a memory-shared TDB-clone,
+ * or dropping multilink support at all.
+ */
+
+#include <string.h>
+#include <ctype.h>
+#include <stdlib.h>
+#include <netdb.h>
+#include <errno.h>
+#include <signal.h>
+#include <netinet/in.h>
+#include <unistd.h>
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/lcp.h"
+#include "netif/ppp/tdb.h"
+
+bool endpoint_specified;	/* user gave explicit endpoint discriminator */
+char *bundle_id;		/* identifier for our bundle */
+char *blinks_id;		/* key for the list of links */
+bool doing_multilink;		/* multilink was enabled and agreed to */
+bool multilink_master;		/* we own the multilink bundle */
+
+extern TDB_CONTEXT *pppdb;
+extern char db_key[];
+
+static void make_bundle_links (int append);
+static void remove_bundle_link (void);
+static void iterate_bundle_links (void (*func) (char *));
+
+static int get_default_epdisc (struct epdisc *);
+static int parse_num (char *str, const char *key, int *valp);
+static int owns_unit (TDB_DATA pid, int unit);
+
+#define set_ip_epdisc(ep, addr) do {	\
+	ep->length = 4;			\
+	ep->value[0] = addr >> 24;	\
+	ep->value[1] = addr >> 16;	\
+	ep->value[2] = addr >> 8;	\
+	ep->value[3] = addr;		\
+} while (0)
+
+#define LOCAL_IP_ADDR(addr)						  \
+	(((addr) & 0xff000000) == 0x0a000000		/* 10.x.x.x */	  \
+	 || ((addr) & 0xfff00000) == 0xac100000		/* 172.16.x.x */  \
+	 || ((addr) & 0xffff0000) == 0xc0a80000)	/* 192.168.x.x */
+
+#define process_exists(n)	(kill((n), 0) == 0 || errno != ESRCH)
+
+void
+mp_check_options()
+{
+	lcp_options *wo = &lcp_wantoptions[0];
+	lcp_options *ao = &lcp_allowoptions[0];
+
+	doing_multilink = 0;
+	if (!multilink)
+		return;
+	/* if we're doing multilink, we have to negotiate MRRU */
+	if (!wo->neg_mrru) {
+		/* mrru not specified, default to mru */
+		wo->mrru = wo->mru;
+		wo->neg_mrru = 1;
+	}
+	ao->mrru = ao->mru;
+	ao->neg_mrru = 1;
+
+	if (!wo->neg_endpoint && !noendpoint) {
+		/* get a default endpoint value */
+		wo->neg_endpoint = get_default_epdisc(&wo->endpoint);
+	}
+}
+
+/*
+ * Make a new bundle or join us to an existing bundle
+ * if we are doing multilink.
+ */
+int
+mp_join_bundle()
+{
+	lcp_options *go = &lcp_gotoptions[0];
+	lcp_options *ho = &lcp_hisoptions[0];
+	lcp_options *ao = &lcp_allowoptions[0];
+	int unit, pppd_pid;
+	int l, mtu;
+	char *p;
+	TDB_DATA key, pid, rec;
+
+	if (doing_multilink) {
+		/* have previously joined a bundle */
+		if (!go->neg_mrru || !ho->neg_mrru) {
+			notice("oops, didn't get multilink on renegotiation");
+			lcp_close(pcb, "multilink required");
+			return 0;
+		}
+		/* XXX should check the peer_authname and ho->endpoint
+		   are the same as previously */
+		return 0;
+	}
+
+	if (!go->neg_mrru || !ho->neg_mrru) {
+		/* not doing multilink */
+		if (go->neg_mrru)
+			notice("oops, multilink negotiated only for receive");
+		mtu = ho->neg_mru? ho->mru: PPP_MRU;
+		if (mtu > ao->mru)
+			mtu = ao->mru;
+		if (demand) {
+			/* already have a bundle */
+			cfg_bundle(0, 0, 0, 0);
+			netif_set_mtu(pcb, mtu);
+			return 0;
+		}
+		make_new_bundle(0, 0, 0, 0);
+		set_ifunit(1);
+		netif_set_mtu(pcb, mtu);
+		return 0;
+	}
+
+	doing_multilink = 1;
+
+	/*
+	 * Find the appropriate bundle or join a new one.
+	 * First we make up a name for the bundle.
+	 * The length estimate is worst-case assuming every
+	 * character has to be quoted.
+	 */
+	l = 4 * strlen(peer_authname) + 10;
+	if (ho->neg_endpoint)
+		l += 3 * ho->endpoint.length + 8;
+	if (bundle_name)
+		l += 3 * strlen(bundle_name) + 2;
+	bundle_id = malloc(l);
+	if (bundle_id == 0)
+		novm("bundle identifier");
+
+	p = bundle_id;
+	p += slprintf(p, l-1, "BUNDLE=\"%q\"", peer_authname);
+	if (ho->neg_endpoint || bundle_name)
+		*p++ = '/';
+	if (ho->neg_endpoint)
+		p += slprintf(p, bundle_id+l-p, "%s",
+			      epdisc_to_str(&ho->endpoint));
+	if (bundle_name)
+		p += slprintf(p, bundle_id+l-p, "/%v", bundle_name);
+
+	/* Make the key for the list of links belonging to the bundle */
+	l = p - bundle_id;
+	blinks_id = malloc(l + 7);
+	if (blinks_id == NULL)
+		novm("bundle links key");
+	slprintf(blinks_id, l + 7, "BUNDLE_LINKS=%s", bundle_id + 7);
+
+	/*
+	 * For demand mode, we only need to configure the bundle
+	 * and attach the link.
+	 */
+	mtu = LWIP_MIN(ho->mrru, ao->mru);
+	if (demand) {
+		cfg_bundle(go->mrru, ho->mrru, go->neg_ssnhf, ho->neg_ssnhf);
+		netif_set_mtu(pcb, mtu);
+		script_setenv("BUNDLE", bundle_id + 7, 1);
+		return 0;
+	}
+
+	/*
+	 * Check if the bundle ID is already in the database.
+	 */
+	unit = -1;
+	lock_db();
+	key.dptr = bundle_id;
+	key.dsize = p - bundle_id;
+	pid = tdb_fetch(pppdb, key);
+	if (pid.dptr != NULL) {
+		/* bundle ID exists, see if the pppd record exists */
+		rec = tdb_fetch(pppdb, pid);
+		if (rec.dptr != NULL && rec.dsize > 0) {
+			/* make sure the string is null-terminated */
+			rec.dptr[rec.dsize-1] = 0;
+			/* parse the interface number */
+			parse_num(rec.dptr, "IFNAME=ppp", &unit);
+			/* check the pid value */
+			if (!parse_num(rec.dptr, "PPPD_PID=", &pppd_pid)
+			    || !process_exists(pppd_pid)
+			    || !owns_unit(pid, unit))
+				unit = -1;
+			free(rec.dptr);
+		}
+		free(pid.dptr);
+	}
+
+	if (unit >= 0) {
+		/* attach to existing unit */
+		if (bundle_attach(unit)) {
+			set_ifunit(0);
+			script_setenv("BUNDLE", bundle_id + 7, 0);
+			make_bundle_links(1);
+			unlock_db();
+			info("Link attached to %s", ifname);
+			return 1;
+		}
+		/* attach failed because bundle doesn't exist */
+	}
+
+	/* we have to make a new bundle */
+	make_new_bundle(go->mrru, ho->mrru, go->neg_ssnhf, ho->neg_ssnhf);
+	set_ifunit(1);
+	netif_set_mtu(pcb, mtu);
+	script_setenv("BUNDLE", bundle_id + 7, 1);
+	make_bundle_links(pcb);
+	unlock_db();
+	info("New bundle %s created", ifname);
+	multilink_master = 1;
+	return 0;
+}
+
+void mp_exit_bundle()
+{
+	lock_db();
+	remove_bundle_link();
+	unlock_db();
+}
+
+static void sendhup(char *str)
+{
+	int pid;
+
+	if (parse_num(str, "PPPD_PID=", &pid) && pid != getpid()) {
+		if (debug)
+			dbglog("sending SIGHUP to process %d", pid);
+		kill(pid, SIGHUP);
+	}
+}
+
+void mp_bundle_terminated()
+{
+	TDB_DATA key;
+
+	bundle_terminating = 1;
+	upper_layers_down(pcb);
+	notice("Connection terminated.");
+#if PPP_STATS_SUPPORT
+	print_link_stats();
+#endif /* PPP_STATS_SUPPORT */
+	if (!demand) {
+		remove_pidfiles();
+		script_unsetenv("IFNAME");
+	}
+
+	lock_db();
+	destroy_bundle();
+	iterate_bundle_links(sendhup);
+	key.dptr = blinks_id;
+	key.dsize = strlen(blinks_id);
+	tdb_delete(pppdb, key);
+	unlock_db();
+
+	new_phase(PPP_PHASE_DEAD);
+
+	doing_multilink = 0;
+	multilink_master = 0;
+}
+
+static void make_bundle_links(int append)
+{
+	TDB_DATA key, rec;
+	char *p;
+	char entry[32];
+	int l;
+
+	key.dptr = blinks_id;
+	key.dsize = strlen(blinks_id);
+	slprintf(entry, sizeof(entry), "%s;", db_key);
+	p = entry;
+	if (append) {
+		rec = tdb_fetch(pppdb, key);
+		if (rec.dptr != NULL && rec.dsize > 0) {
+			rec.dptr[rec.dsize-1] = 0;
+			if (strstr(rec.dptr, db_key) != NULL) {
+				/* already in there? strange */
+				warn("link entry already exists in tdb");
+				return;
+			}
+			l = rec.dsize + strlen(entry);
+			p = malloc(l);
+			if (p == NULL)
+				novm("bundle link list");
+			slprintf(p, l, "%s%s", rec.dptr, entry);
+		} else {
+			warn("bundle link list not found");
+		}
+		if (rec.dptr != NULL)
+			free(rec.dptr);
+	}
+	rec.dptr = p;
+	rec.dsize = strlen(p) + 1;
+	if (tdb_store(pppdb, key, rec, TDB_REPLACE))
+		error("couldn't %s bundle link list",
+		      append? "update": "create");
+	if (p != entry)
+		free(p);
+}
+
+static void remove_bundle_link()
+{
+	TDB_DATA key, rec;
+	char entry[32];
+	char *p, *q;
+	int l;
+
+	key.dptr = blinks_id;
+	key.dsize = strlen(blinks_id);
+	slprintf(entry, sizeof(entry), "%s;", db_key);
+
+	rec = tdb_fetch(pppdb, key);
+	if (rec.dptr == NULL || rec.dsize <= 0) {
+		if (rec.dptr != NULL)
+			free(rec.dptr);
+		return;
+	}
+	rec.dptr[rec.dsize-1] = 0;
+	p = strstr(rec.dptr, entry);
+	if (p != NULL) {
+		q = p + strlen(entry);
+		l = strlen(q) + 1;
+		memmove(p, q, l);
+		rec.dsize = p - rec.dptr + l;
+		if (tdb_store(pppdb, key, rec, TDB_REPLACE))
+			error("couldn't update bundle link list (removal)");
+	}
+	free(rec.dptr);
+}
+
+static void iterate_bundle_links(void (*func)(char *))
+{
+	TDB_DATA key, rec, pp;
+	char *p, *q;
+
+	key.dptr = blinks_id;
+	key.dsize = strlen(blinks_id);
+	rec = tdb_fetch(pppdb, key);
+	if (rec.dptr == NULL || rec.dsize <= 0) {
+		error("bundle link list not found (iterating list)");
+		if (rec.dptr != NULL)
+			free(rec.dptr);
+		return;
+	}
+	p = rec.dptr;
+	p[rec.dsize-1] = 0;
+	while ((q = strchr(p, ';')) != NULL) {
+		*q = 0;
+		key.dptr = p;
+		key.dsize = q - p;
+		pp = tdb_fetch(pppdb, key);
+		if (pp.dptr != NULL && pp.dsize > 0) {
+			pp.dptr[pp.dsize-1] = 0;
+			func(pp.dptr);
+		}
+		if (pp.dptr != NULL)
+			free(pp.dptr);
+		p = q + 1;
+	}
+	free(rec.dptr);
+}
+
+static int
+parse_num(str, key, valp)
+     char *str;
+     const char *key;
+     int *valp;
+{
+	char *p, *endp;
+	int i;
+
+	p = strstr(str, key);
+	if (p != 0) {
+		p += strlen(key);
+		i = strtol(p, &endp, 10);
+		if (endp != p && (*endp == 0 || *endp == ';')) {
+			*valp = i;
+			return 1;
+		}
+	}
+	return 0;
+}
+
+/*
+ * Check whether the pppd identified by `key' still owns ppp unit `unit'.
+ */
+static int
+owns_unit(key, unit)
+     TDB_DATA key;
+     int unit;
+{
+	char ifkey[32];
+	TDB_DATA kd, vd;
+	int ret = 0;
+
+	slprintf(ifkey, sizeof(ifkey), "IFNAME=ppp%d", unit);
+	kd.dptr = ifkey;
+	kd.dsize = strlen(ifkey);
+	vd = tdb_fetch(pppdb, kd);
+	if (vd.dptr != NULL) {
+		ret = vd.dsize == key.dsize
+			&& memcmp(vd.dptr, key.dptr, vd.dsize) == 0;
+		free(vd.dptr);
+	}
+	return ret;
+}
+
+static int
+get_default_epdisc(ep)
+     struct epdisc *ep;
+{
+	char *p;
+	struct hostent *hp;
+	u32_t addr;
+
+	/* First try for an ethernet MAC address */
+	p = get_first_ethernet();
+	if (p != 0 && get_if_hwaddr(ep->value, p) >= 0) {
+		ep->class = EPD_MAC;
+		ep->length = 6;
+		return 1;
+	}
+
+	/* see if our hostname corresponds to a reasonable IP address */
+	hp = gethostbyname(hostname);
+	if (hp != NULL) {
+		addr = *(u32_t *)hp->h_addr;
+		if (!bad_ip_adrs(addr)) {
+			addr = lwip_ntohl(addr);
+			if (!LOCAL_IP_ADDR(addr)) {
+				ep->class = EPD_IP;
+				set_ip_epdisc(ep, addr);
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * epdisc_to_str - make a printable string from an endpoint discriminator.
+ */
+
+static char *endp_class_names[] = {
+    "null", "local", "IP", "MAC", "magic", "phone"
+};
+
+char *
+epdisc_to_str(ep)
+     struct epdisc *ep;
+{
+	static char str[MAX_ENDP_LEN*3+8];
+	u_char *p = ep->value;
+	int i, mask = 0;
+	char *q, c, c2;
+
+	if (ep->class == EPD_NULL && ep->length == 0)
+		return "null";
+	if (ep->class == EPD_IP && ep->length == 4) {
+		u32_t addr;
+
+		GETLONG(addr, p);
+		slprintf(str, sizeof(str), "IP:%I", lwip_htonl(addr));
+		return str;
+	}
+
+	c = ':';
+	c2 = '.';
+	if (ep->class == EPD_MAC && ep->length == 6)
+		c2 = ':';
+	else if (ep->class == EPD_MAGIC && (ep->length % 4) == 0)
+		mask = 3;
+	q = str;
+	if (ep->class <= EPD_PHONENUM)
+		q += slprintf(q, sizeof(str)-1, "%s",
+			      endp_class_names[ep->class]);
+	else
+		q += slprintf(q, sizeof(str)-1, "%d", ep->class);
+	c = ':';
+	for (i = 0; i < ep->length && i < MAX_ENDP_LEN; ++i) {
+		if ((i & mask) == 0) {
+			*q++ = c;
+			c = c2;
+		}
+		q += slprintf(q, str + sizeof(str) - q, "%.2x", ep->value[i]);
+	}
+	return str;
+}
+
+static int hexc_val(int c)
+{
+	if (c >= 'a')
+		return c - 'a' + 10;
+	if (c >= 'A')
+		return c - 'A' + 10;
+	return c - '0';
+}
+
+int
+str_to_epdisc(ep, str)
+     struct epdisc *ep;
+     char *str;
+{
+	int i, l;
+	char *p, *endp;
+
+	for (i = EPD_NULL; i <= EPD_PHONENUM; ++i) {
+		int sl = strlen(endp_class_names[i]);
+		if (strncasecmp(str, endp_class_names[i], sl) == 0) {
+			str += sl;
+			break;
+		}
+	}
+	if (i > EPD_PHONENUM) {
+		/* not a class name, try a decimal class number */
+		i = strtol(str, &endp, 10);
+		if (endp == str)
+			return 0;	/* can't parse class number */
+		str = endp;
+	}
+	ep->class = i;
+	if (*str == 0) {
+		ep->length = 0;
+		return 1;
+	}
+	if (*str != ':' && *str != '.')
+		return 0;
+	++str;
+
+	if (i == EPD_IP) {
+		u32_t addr;
+		i = parse_dotted_ip(str, &addr);
+		if (i == 0 || str[i] != 0)
+			return 0;
+		set_ip_epdisc(ep, addr);
+		return 1;
+	}
+	if (i == EPD_MAC && get_if_hwaddr(ep->value, str) >= 0) {
+		ep->length = 6;
+		return 1;
+	}
+
+	p = str;
+	for (l = 0; l < MAX_ENDP_LEN; ++l) {
+		if (*str == 0)
+			break;
+		if (p <= str)
+			for (p = str; isxdigit(*p); ++p)
+				;
+		i = p - str;
+		if (i == 0)
+			return 0;
+		ep->value[l] = hexc_val(*str++);
+		if ((i & 1) == 0)
+			ep->value[l] = (ep->value[l] << 4) + hexc_val(*str++);
+		if (*str == ':' || *str == '.')
+			++str;
+	}
+	if (*str != 0 || (ep->class == EPD_MAC && l != 6))
+		return 0;
+	ep->length = l;
+	return 1;
+}
+
+#endif /* PPP_SUPPORT && HAVE_MULTILINK */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/arc4.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/arc4.c
new file mode 100644
index 000000000..6e17ec421
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/arc4.c
@@ -0,0 +1,101 @@
+/*
+ *  An implementation of the ARCFOUR algorithm
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  The ARCFOUR algorithm was publicly disclosed on 94/09.
+ *
+ *  http://groups.google.com/group/sci.crypt/msg/10a300c9d21afca0
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_ARC4
+
+#include "netif/ppp/polarssl/arc4.h"
+/*
+ * ARC4 key schedule
+ */
+void arc4_setup( arc4_context *ctx, unsigned char *key, int keylen )
+{
+    int i, j, k, a;
+    unsigned char *m;
+
+    ctx->x = 0;
+    ctx->y = 0;
+    m = ctx->m;
+
+    for( i = 0; i < 256; i++ )
+        m[i] = (unsigned char) i;
+
+    j = k = 0;
+
+    for( i = 0; i < 256; i++, k++ )
+    {
+        if( k >= keylen ) k = 0;
+
+        a = m[i];
+        j = ( j + a + key[k] ) & 0xFF;
+        m[i] = m[j];
+        m[j] = (unsigned char) a;
+    }
+}
+
+/*
+ * ARC4 cipher function
+ */
+void arc4_crypt( arc4_context *ctx, unsigned char *buf, int buflen )
+{
+    int i, x, y, a, b;
+    unsigned char *m;
+
+    x = ctx->x;
+    y = ctx->y;
+    m = ctx->m;
+
+    for( i = 0; i < buflen; i++ )
+    {
+        x = ( x + 1 ) & 0xFF; a = m[x];
+        y = ( y + a ) & 0xFF; b = m[y];
+
+        m[x] = (unsigned char) b;
+        m[y] = (unsigned char) a;
+
+        buf[i] = (unsigned char)
+            ( buf[i] ^ m[(unsigned char)( a + b )] );
+    }
+
+    ctx->x = x;
+    ctx->y = y;
+}
+
+#endif /* PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_DES */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/des.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/des.c
new file mode 100644
index 000000000..9a89d007b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/des.c
@@ -0,0 +1,422 @@
+/*
+ *  FIPS-46-3 compliant Triple-DES implementation
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  DES, on which TDES is based, was originally designed by Horst Feistel
+ *  at IBM in 1974, and was adopted as a standard by NIST (formerly NBS).
+ *
+ *  http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_DES
+
+#include "netif/ppp/polarssl/des.h"
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_ULONG_BE
+#define GET_ULONG_BE(n,b,i)                             \
+{                                                       \
+    (n) = ( (unsigned long) (b)[(i)    ] << 24 )        \
+        | ( (unsigned long) (b)[(i) + 1] << 16 )        \
+        | ( (unsigned long) (b)[(i) + 2] <<  8 )        \
+        | ( (unsigned long) (b)[(i) + 3]       );       \
+}
+#endif
+
+#ifndef PUT_ULONG_BE
+#define PUT_ULONG_BE(n,b,i)                             \
+{                                                       \
+    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
+}
+#endif
+
+/*
+ * Expanded DES S-boxes
+ */
+static const unsigned long SB1[64] =
+{
+    0x01010400, 0x00000000, 0x00010000, 0x01010404,
+    0x01010004, 0x00010404, 0x00000004, 0x00010000,
+    0x00000400, 0x01010400, 0x01010404, 0x00000400,
+    0x01000404, 0x01010004, 0x01000000, 0x00000004,
+    0x00000404, 0x01000400, 0x01000400, 0x00010400,
+    0x00010400, 0x01010000, 0x01010000, 0x01000404,
+    0x00010004, 0x01000004, 0x01000004, 0x00010004,
+    0x00000000, 0x00000404, 0x00010404, 0x01000000,
+    0x00010000, 0x01010404, 0x00000004, 0x01010000,
+    0x01010400, 0x01000000, 0x01000000, 0x00000400,
+    0x01010004, 0x00010000, 0x00010400, 0x01000004,
+    0x00000400, 0x00000004, 0x01000404, 0x00010404,
+    0x01010404, 0x00010004, 0x01010000, 0x01000404,
+    0x01000004, 0x00000404, 0x00010404, 0x01010400,
+    0x00000404, 0x01000400, 0x01000400, 0x00000000,
+    0x00010004, 0x00010400, 0x00000000, 0x01010004
+};
+
+static const unsigned long SB2[64] =
+{
+    0x80108020, 0x80008000, 0x00008000, 0x00108020,
+    0x00100000, 0x00000020, 0x80100020, 0x80008020,
+    0x80000020, 0x80108020, 0x80108000, 0x80000000,
+    0x80008000, 0x00100000, 0x00000020, 0x80100020,
+    0x00108000, 0x00100020, 0x80008020, 0x00000000,
+    0x80000000, 0x00008000, 0x00108020, 0x80100000,
+    0x00100020, 0x80000020, 0x00000000, 0x00108000,
+    0x00008020, 0x80108000, 0x80100000, 0x00008020,
+    0x00000000, 0x00108020, 0x80100020, 0x00100000,
+    0x80008020, 0x80100000, 0x80108000, 0x00008000,
+    0x80100000, 0x80008000, 0x00000020, 0x80108020,
+    0x00108020, 0x00000020, 0x00008000, 0x80000000,
+    0x00008020, 0x80108000, 0x00100000, 0x80000020,
+    0x00100020, 0x80008020, 0x80000020, 0x00100020,
+    0x00108000, 0x00000000, 0x80008000, 0x00008020,
+    0x80000000, 0x80100020, 0x80108020, 0x00108000
+};
+
+static const unsigned long SB3[64] =
+{
+    0x00000208, 0x08020200, 0x00000000, 0x08020008,
+    0x08000200, 0x00000000, 0x00020208, 0x08000200,
+    0x00020008, 0x08000008, 0x08000008, 0x00020000,
+    0x08020208, 0x00020008, 0x08020000, 0x00000208,
+    0x08000000, 0x00000008, 0x08020200, 0x00000200,
+    0x00020200, 0x08020000, 0x08020008, 0x00020208,
+    0x08000208, 0x00020200, 0x00020000, 0x08000208,
+    0x00000008, 0x08020208, 0x00000200, 0x08000000,
+    0x08020200, 0x08000000, 0x00020008, 0x00000208,
+    0x00020000, 0x08020200, 0x08000200, 0x00000000,
+    0x00000200, 0x00020008, 0x08020208, 0x08000200,
+    0x08000008, 0x00000200, 0x00000000, 0x08020008,
+    0x08000208, 0x00020000, 0x08000000, 0x08020208,
+    0x00000008, 0x00020208, 0x00020200, 0x08000008,
+    0x08020000, 0x08000208, 0x00000208, 0x08020000,
+    0x00020208, 0x00000008, 0x08020008, 0x00020200
+};
+
+static const unsigned long SB4[64] =
+{
+    0x00802001, 0x00002081, 0x00002081, 0x00000080,
+    0x00802080, 0x00800081, 0x00800001, 0x00002001,
+    0x00000000, 0x00802000, 0x00802000, 0x00802081,
+    0x00000081, 0x00000000, 0x00800080, 0x00800001,
+    0x00000001, 0x00002000, 0x00800000, 0x00802001,
+    0x00000080, 0x00800000, 0x00002001, 0x00002080,
+    0x00800081, 0x00000001, 0x00002080, 0x00800080,
+    0x00002000, 0x00802080, 0x00802081, 0x00000081,
+    0x00800080, 0x00800001, 0x00802000, 0x00802081,
+    0x00000081, 0x00000000, 0x00000000, 0x00802000,
+    0x00002080, 0x00800080, 0x00800081, 0x00000001,
+    0x00802001, 0x00002081, 0x00002081, 0x00000080,
+    0x00802081, 0x00000081, 0x00000001, 0x00002000,
+    0x00800001, 0x00002001, 0x00802080, 0x00800081,
+    0x00002001, 0x00002080, 0x00800000, 0x00802001,
+    0x00000080, 0x00800000, 0x00002000, 0x00802080
+};
+
+static const unsigned long SB5[64] =
+{
+    0x00000100, 0x02080100, 0x02080000, 0x42000100,
+    0x00080000, 0x00000100, 0x40000000, 0x02080000,
+    0x40080100, 0x00080000, 0x02000100, 0x40080100,
+    0x42000100, 0x42080000, 0x00080100, 0x40000000,
+    0x02000000, 0x40080000, 0x40080000, 0x00000000,
+    0x40000100, 0x42080100, 0x42080100, 0x02000100,
+    0x42080000, 0x40000100, 0x00000000, 0x42000000,
+    0x02080100, 0x02000000, 0x42000000, 0x00080100,
+    0x00080000, 0x42000100, 0x00000100, 0x02000000,
+    0x40000000, 0x02080000, 0x42000100, 0x40080100,
+    0x02000100, 0x40000000, 0x42080000, 0x02080100,
+    0x40080100, 0x00000100, 0x02000000, 0x42080000,
+    0x42080100, 0x00080100, 0x42000000, 0x42080100,
+    0x02080000, 0x00000000, 0x40080000, 0x42000000,
+    0x00080100, 0x02000100, 0x40000100, 0x00080000,
+    0x00000000, 0x40080000, 0x02080100, 0x40000100
+};
+
+static const unsigned long SB6[64] =
+{
+    0x20000010, 0x20400000, 0x00004000, 0x20404010,
+    0x20400000, 0x00000010, 0x20404010, 0x00400000,
+    0x20004000, 0x00404010, 0x00400000, 0x20000010,
+    0x00400010, 0x20004000, 0x20000000, 0x00004010,
+    0x00000000, 0x00400010, 0x20004010, 0x00004000,
+    0x00404000, 0x20004010, 0x00000010, 0x20400010,
+    0x20400010, 0x00000000, 0x00404010, 0x20404000,
+    0x00004010, 0x00404000, 0x20404000, 0x20000000,
+    0x20004000, 0x00000010, 0x20400010, 0x00404000,
+    0x20404010, 0x00400000, 0x00004010, 0x20000010,
+    0x00400000, 0x20004000, 0x20000000, 0x00004010,
+    0x20000010, 0x20404010, 0x00404000, 0x20400000,
+    0x00404010, 0x20404000, 0x00000000, 0x20400010,
+    0x00000010, 0x00004000, 0x20400000, 0x00404010,
+    0x00004000, 0x00400010, 0x20004010, 0x00000000,
+    0x20404000, 0x20000000, 0x00400010, 0x20004010
+};
+
+static const unsigned long SB7[64] =
+{
+    0x00200000, 0x04200002, 0x04000802, 0x00000000,
+    0x00000800, 0x04000802, 0x00200802, 0x04200800,
+    0x04200802, 0x00200000, 0x00000000, 0x04000002,
+    0x00000002, 0x04000000, 0x04200002, 0x00000802,
+    0x04000800, 0x00200802, 0x00200002, 0x04000800,
+    0x04000002, 0x04200000, 0x04200800, 0x00200002,
+    0x04200000, 0x00000800, 0x00000802, 0x04200802,
+    0x00200800, 0x00000002, 0x04000000, 0x00200800,
+    0x04000000, 0x00200800, 0x00200000, 0x04000802,
+    0x04000802, 0x04200002, 0x04200002, 0x00000002,
+    0x00200002, 0x04000000, 0x04000800, 0x00200000,
+    0x04200800, 0x00000802, 0x00200802, 0x04200800,
+    0x00000802, 0x04000002, 0x04200802, 0x04200000,
+    0x00200800, 0x00000000, 0x00000002, 0x04200802,
+    0x00000000, 0x00200802, 0x04200000, 0x00000800,
+    0x04000002, 0x04000800, 0x00000800, 0x00200002
+};
+
+static const unsigned long SB8[64] =
+{
+    0x10001040, 0x00001000, 0x00040000, 0x10041040,
+    0x10000000, 0x10001040, 0x00000040, 0x10000000,
+    0x00040040, 0x10040000, 0x10041040, 0x00041000,
+    0x10041000, 0x00041040, 0x00001000, 0x00000040,
+    0x10040000, 0x10000040, 0x10001000, 0x00001040,
+    0x00041000, 0x00040040, 0x10040040, 0x10041000,
+    0x00001040, 0x00000000, 0x00000000, 0x10040040,
+    0x10000040, 0x10001000, 0x00041040, 0x00040000,
+    0x00041040, 0x00040000, 0x10041000, 0x00001000,
+    0x00000040, 0x10040040, 0x00001000, 0x00041040,
+    0x10001000, 0x00000040, 0x10000040, 0x10040000,
+    0x10040040, 0x10000000, 0x00040000, 0x10001040,
+    0x00000000, 0x10041040, 0x00040040, 0x10000040,
+    0x10040000, 0x10001000, 0x10001040, 0x00000000,
+    0x10041040, 0x00041000, 0x00041000, 0x00001040,
+    0x00001040, 0x00040040, 0x10000000, 0x10041000
+};
+
+/*
+ * PC1: left and right halves bit-swap
+ */
+static const unsigned long LHs[16] =
+{
+    0x00000000, 0x00000001, 0x00000100, 0x00000101,
+    0x00010000, 0x00010001, 0x00010100, 0x00010101,
+    0x01000000, 0x01000001, 0x01000100, 0x01000101,
+    0x01010000, 0x01010001, 0x01010100, 0x01010101
+};
+
+static const unsigned long RHs[16] =
+{
+    0x00000000, 0x01000000, 0x00010000, 0x01010000,
+    0x00000100, 0x01000100, 0x00010100, 0x01010100,
+    0x00000001, 0x01000001, 0x00010001, 0x01010001,
+    0x00000101, 0x01000101, 0x00010101, 0x01010101,
+};
+
+/*
+ * Initial Permutation macro
+ */
+#define DES_IP(X,Y)                                             \
+{                                                               \
+    T = ((X >>  4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T <<  4);   \
+    T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16);   \
+    T = ((Y >>  2) ^ X) & 0x33333333; X ^= T; Y ^= (T <<  2);   \
+    T = ((Y >>  8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T <<  8);   \
+    Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF;                    \
+    T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T;                   \
+    X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF;                    \
+}
+
+/*
+ * Final Permutation macro
+ */
+#define DES_FP(X,Y)                                             \
+{                                                               \
+    X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF;                    \
+    T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T;                   \
+    Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF;                    \
+    T = ((Y >>  8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T <<  8);   \
+    T = ((Y >>  2) ^ X) & 0x33333333; X ^= T; Y ^= (T <<  2);   \
+    T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16);   \
+    T = ((X >>  4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T <<  4);   \
+}
+
+/*
+ * DES round macro
+ */
+#define DES_ROUND(X,Y)                          \
+{                                               \
+    T = *SK++ ^ X;                              \
+    Y ^= SB8[ (T      ) & 0x3F ] ^              \
+         SB6[ (T >>  8) & 0x3F ] ^              \
+         SB4[ (T >> 16) & 0x3F ] ^              \
+         SB2[ (T >> 24) & 0x3F ];               \
+                                                \
+    T = *SK++ ^ ((X << 28) | (X >> 4));         \
+    Y ^= SB7[ (T      ) & 0x3F ] ^              \
+         SB5[ (T >>  8) & 0x3F ] ^              \
+         SB3[ (T >> 16) & 0x3F ] ^              \
+         SB1[ (T >> 24) & 0x3F ];               \
+}
+
+#define SWAP(a,b) { unsigned long t = a; a = b; b = t; t = 0; }
+
+static void des_setkey( unsigned long SK[32], unsigned char key[8] )
+{
+    int i;
+    unsigned long X, Y, T;
+
+    GET_ULONG_BE( X, key, 0 );
+    GET_ULONG_BE( Y, key, 4 );
+
+    /*
+     * Permuted Choice 1
+     */
+    T =  ((Y >>  4) ^ X) & 0x0F0F0F0F;  X ^= T; Y ^= (T <<  4);
+    T =  ((Y      ) ^ X) & 0x10101010;  X ^= T; Y ^= (T      );
+
+    X =   (LHs[ (X      ) & 0xF] << 3) | (LHs[ (X >>  8) & 0xF ] << 2)
+        | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ]     )
+        | (LHs[ (X >>  5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6)
+        | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4);
+
+    Y =   (RHs[ (Y >>  1) & 0xF] << 3) | (RHs[ (Y >>  9) & 0xF ] << 2)
+        | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ]     )
+        | (RHs[ (Y >>  4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6)
+        | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4);
+
+    X &= 0x0FFFFFFF;
+    Y &= 0x0FFFFFFF;
+
+    /*
+     * calculate subkeys
+     */
+    for( i = 0; i < 16; i++ )
+    {
+        if( i < 2 || i == 8 || i == 15 )
+        {
+            X = ((X <<  1) | (X >> 27)) & 0x0FFFFFFF;
+            Y = ((Y <<  1) | (Y >> 27)) & 0x0FFFFFFF;
+        }
+        else
+        {
+            X = ((X <<  2) | (X >> 26)) & 0x0FFFFFFF;
+            Y = ((Y <<  2) | (Y >> 26)) & 0x0FFFFFFF;
+        }
+
+        *SK++ =   ((X <<  4) & 0x24000000) | ((X << 28) & 0x10000000)
+                | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000)
+                | ((X <<  6) & 0x01000000) | ((X <<  9) & 0x00200000)
+                | ((X >>  1) & 0x00100000) | ((X << 10) & 0x00040000)
+                | ((X <<  2) & 0x00020000) | ((X >> 10) & 0x00010000)
+                | ((Y >> 13) & 0x00002000) | ((Y >>  4) & 0x00001000)
+                | ((Y <<  6) & 0x00000800) | ((Y >>  1) & 0x00000400)
+                | ((Y >> 14) & 0x00000200) | ((Y      ) & 0x00000100)
+                | ((Y >>  5) & 0x00000020) | ((Y >> 10) & 0x00000010)
+                | ((Y >>  3) & 0x00000008) | ((Y >> 18) & 0x00000004)
+                | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001);
+
+        *SK++ =   ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000)
+                | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000)
+                | ((X >>  2) & 0x02000000) | ((X <<  1) & 0x01000000)
+                | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000)
+                | ((X <<  3) & 0x00080000) | ((X >>  6) & 0x00040000)
+                | ((X << 15) & 0x00020000) | ((X >>  4) & 0x00010000)
+                | ((Y >>  2) & 0x00002000) | ((Y <<  8) & 0x00001000)
+                | ((Y >> 14) & 0x00000808) | ((Y >>  9) & 0x00000400)
+                | ((Y      ) & 0x00000200) | ((Y <<  7) & 0x00000100)
+                | ((Y >>  7) & 0x00000020) | ((Y >>  3) & 0x00000011)
+                | ((Y <<  2) & 0x00000004) | ((Y >> 21) & 0x00000002);
+    }
+}
+
+/*
+ * DES key schedule (56-bit, encryption)
+ */
+void des_setkey_enc( des_context *ctx, unsigned char key[8] )
+{
+    des_setkey( ctx->sk, key );
+}
+
+/*
+ * DES key schedule (56-bit, decryption)
+ */
+void des_setkey_dec( des_context *ctx, unsigned char key[8] )
+{
+    int i;
+
+    des_setkey( ctx->sk, key );
+
+    for( i = 0; i < 16; i += 2 )
+    {
+        SWAP( ctx->sk[i    ], ctx->sk[30 - i] );
+        SWAP( ctx->sk[i + 1], ctx->sk[31 - i] );
+    }
+}
+
+/*
+ * DES-ECB block encryption/decryption
+ */
+void des_crypt_ecb( des_context *ctx,
+                    const unsigned char input[8],
+                    unsigned char output[8] )
+{
+    int i;
+    unsigned long X, Y, T, *SK;
+
+    SK = ctx->sk;
+
+    GET_ULONG_BE( X, input, 0 );
+    GET_ULONG_BE( Y, input, 4 );
+
+    DES_IP( X, Y );
+
+    for( i = 0; i < 8; i++ )
+    {
+        DES_ROUND( Y, X );
+        DES_ROUND( X, Y );
+    }
+
+    DES_FP( Y, X );
+
+    PUT_ULONG_BE( Y, output, 0 );
+    PUT_ULONG_BE( X, output, 4 );
+}
+
+#endif /* PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_DES */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/md4.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/md4.c
new file mode 100644
index 000000000..b1701a07b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/md4.c
@@ -0,0 +1,281 @@
+/*
+ *  RFC 1186/1320 compliant MD4 implementation
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  The MD4 algorithm was designed by Ron Rivest in 1990.
+ *
+ *  http://www.ietf.org/rfc/rfc1186.txt
+ *  http://www.ietf.org/rfc/rfc1320.txt
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_MD4
+
+#include "netif/ppp/polarssl/md4.h"
+
+#include <string.h>
+
+/*
+ * 32-bit integer manipulation macros (little endian)
+ */
+#ifndef GET_ULONG_LE
+#define GET_ULONG_LE(n,b,i)                             \
+{                                                       \
+    (n) = ( (unsigned long) (b)[(i)    ]       )        \
+        | ( (unsigned long) (b)[(i) + 1] <<  8 )        \
+        | ( (unsigned long) (b)[(i) + 2] << 16 )        \
+        | ( (unsigned long) (b)[(i) + 3] << 24 );       \
+}
+#endif
+
+#ifndef PUT_ULONG_LE
+#define PUT_ULONG_LE(n,b,i)                             \
+{                                                       \
+    (b)[(i)    ] = (unsigned char) ( (n)       );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n) >> 24 );       \
+}
+#endif
+
+/*
+ * MD4 context setup
+ */
+void md4_starts( md4_context *ctx )
+{
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+
+    ctx->state[0] = 0x67452301;
+    ctx->state[1] = 0xEFCDAB89;
+    ctx->state[2] = 0x98BADCFE;
+    ctx->state[3] = 0x10325476;
+}
+
+static void md4_process( md4_context *ctx, const unsigned char data[64] )
+{
+    unsigned long X[16], A, B, C, D;
+
+    GET_ULONG_LE( X[ 0], data,  0 );
+    GET_ULONG_LE( X[ 1], data,  4 );
+    GET_ULONG_LE( X[ 2], data,  8 );
+    GET_ULONG_LE( X[ 3], data, 12 );
+    GET_ULONG_LE( X[ 4], data, 16 );
+    GET_ULONG_LE( X[ 5], data, 20 );
+    GET_ULONG_LE( X[ 6], data, 24 );
+    GET_ULONG_LE( X[ 7], data, 28 );
+    GET_ULONG_LE( X[ 8], data, 32 );
+    GET_ULONG_LE( X[ 9], data, 36 );
+    GET_ULONG_LE( X[10], data, 40 );
+    GET_ULONG_LE( X[11], data, 44 );
+    GET_ULONG_LE( X[12], data, 48 );
+    GET_ULONG_LE( X[13], data, 52 );
+    GET_ULONG_LE( X[14], data, 56 );
+    GET_ULONG_LE( X[15], data, 60 );
+
+#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
+
+    A = ctx->state[0];
+    B = ctx->state[1];
+    C = ctx->state[2];
+    D = ctx->state[3];
+
+#define F(x, y, z) ((x & y) | ((~x) & z))
+#define P(a,b,c,d,x,s) { a += F(b,c,d) + x; a = S(a,s); }
+
+    P( A, B, C, D, X[ 0],  3 );
+    P( D, A, B, C, X[ 1],  7 );
+    P( C, D, A, B, X[ 2], 11 );
+    P( B, C, D, A, X[ 3], 19 );
+    P( A, B, C, D, X[ 4],  3 );
+    P( D, A, B, C, X[ 5],  7 );
+    P( C, D, A, B, X[ 6], 11 );
+    P( B, C, D, A, X[ 7], 19 );
+    P( A, B, C, D, X[ 8],  3 );
+    P( D, A, B, C, X[ 9],  7 );
+    P( C, D, A, B, X[10], 11 );
+    P( B, C, D, A, X[11], 19 );
+    P( A, B, C, D, X[12],  3 );
+    P( D, A, B, C, X[13],  7 );
+    P( C, D, A, B, X[14], 11 );
+    P( B, C, D, A, X[15], 19 );
+
+#undef P
+#undef F
+
+#define F(x,y,z) ((x & y) | (x & z) | (y & z))
+#define P(a,b,c,d,x,s) { a += F(b,c,d) + x + 0x5A827999; a = S(a,s); }
+
+    P( A, B, C, D, X[ 0],  3 );
+    P( D, A, B, C, X[ 4],  5 );
+    P( C, D, A, B, X[ 8],  9 );
+    P( B, C, D, A, X[12], 13 );
+    P( A, B, C, D, X[ 1],  3 );
+    P( D, A, B, C, X[ 5],  5 );
+    P( C, D, A, B, X[ 9],  9 );
+    P( B, C, D, A, X[13], 13 );
+    P( A, B, C, D, X[ 2],  3 );
+    P( D, A, B, C, X[ 6],  5 );
+    P( C, D, A, B, X[10],  9 );
+    P( B, C, D, A, X[14], 13 );
+    P( A, B, C, D, X[ 3],  3 );
+    P( D, A, B, C, X[ 7],  5 );
+    P( C, D, A, B, X[11],  9 );
+    P( B, C, D, A, X[15], 13 );
+
+#undef P
+#undef F
+
+#define F(x,y,z) (x ^ y ^ z)
+#define P(a,b,c,d,x,s) { a += F(b,c,d) + x + 0x6ED9EBA1; a = S(a,s); }
+
+    P( A, B, C, D, X[ 0],  3 );
+    P( D, A, B, C, X[ 8],  9 );
+    P( C, D, A, B, X[ 4], 11 );
+    P( B, C, D, A, X[12], 15 );
+    P( A, B, C, D, X[ 2],  3 );
+    P( D, A, B, C, X[10],  9 );
+    P( C, D, A, B, X[ 6], 11 );
+    P( B, C, D, A, X[14], 15 );
+    P( A, B, C, D, X[ 1],  3 );
+    P( D, A, B, C, X[ 9],  9 );
+    P( C, D, A, B, X[ 5], 11 );
+    P( B, C, D, A, X[13], 15 );
+    P( A, B, C, D, X[ 3],  3 );
+    P( D, A, B, C, X[11],  9 );
+    P( C, D, A, B, X[ 7], 11 );
+    P( B, C, D, A, X[15], 15 );
+
+#undef F
+#undef P
+
+    ctx->state[0] += A;
+    ctx->state[1] += B;
+    ctx->state[2] += C;
+    ctx->state[3] += D;
+}
+
+/*
+ * MD4 process buffer
+ */
+void md4_update( md4_context *ctx, const unsigned char *input, int ilen )
+{
+    int fill;
+    unsigned long left;
+
+    if( ilen <= 0 )
+        return;
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (unsigned long) ilen )
+        ctx->total[1]++;
+
+    if( left && ilen >= fill )
+    {
+        MEMCPY( (void *) (ctx->buffer + left),
+                input, fill );
+        md4_process( ctx, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 )
+    {
+        md4_process( ctx, input );
+        input += 64;
+        ilen  -= 64;
+    }
+
+    if( ilen > 0 )
+    {
+        MEMCPY( (void *) (ctx->buffer + left),
+                input, ilen );
+    }
+}
+
+static const unsigned char md4_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*
+ * MD4 final digest
+ */
+void md4_finish( md4_context *ctx, unsigned char output[16] )
+{
+    unsigned long last, padn;
+    unsigned long high, low;
+    unsigned char msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_ULONG_LE( low,  msglen, 0 );
+    PUT_ULONG_LE( high, msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    md4_update( ctx, md4_padding, padn );
+    md4_update( ctx, msglen, 8 );
+
+    PUT_ULONG_LE( ctx->state[0], output,  0 );
+    PUT_ULONG_LE( ctx->state[1], output,  4 );
+    PUT_ULONG_LE( ctx->state[2], output,  8 );
+    PUT_ULONG_LE( ctx->state[3], output, 12 );
+}
+
+/*
+ * output = MD4( input buffer )
+ */
+void md4( unsigned char *input, int ilen, unsigned char output[16] )
+{
+    md4_context ctx;
+
+    md4_starts( &ctx );
+    md4_update( &ctx, input, ilen );
+    md4_finish( &ctx, output );
+}
+
+#endif /* PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_MD4 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/md5.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/md5.c
new file mode 100644
index 000000000..1ec4d81a6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/md5.c
@@ -0,0 +1,300 @@
+/*
+ *  RFC 1321 compliant MD5 implementation
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  The MD5 algorithm was designed by Ron Rivest in 1991.
+ *
+ *  http://www.ietf.org/rfc/rfc1321.txt
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_MD5
+
+#include "netif/ppp/polarssl/md5.h"
+
+#include <string.h>
+
+/*
+ * 32-bit integer manipulation macros (little endian)
+ */
+#ifndef GET_ULONG_LE
+#define GET_ULONG_LE(n,b,i)                             \
+{                                                       \
+    (n) = ( (unsigned long) (b)[(i)    ]       )        \
+        | ( (unsigned long) (b)[(i) + 1] <<  8 )        \
+        | ( (unsigned long) (b)[(i) + 2] << 16 )        \
+        | ( (unsigned long) (b)[(i) + 3] << 24 );       \
+}
+#endif
+
+#ifndef PUT_ULONG_LE
+#define PUT_ULONG_LE(n,b,i)                             \
+{                                                       \
+    (b)[(i)    ] = (unsigned char) ( (n)       );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n) >> 24 );       \
+}
+#endif
+
+/*
+ * MD5 context setup
+ */
+void md5_starts( md5_context *ctx )
+{
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+
+    ctx->state[0] = 0x67452301;
+    ctx->state[1] = 0xEFCDAB89;
+    ctx->state[2] = 0x98BADCFE;
+    ctx->state[3] = 0x10325476;
+}
+
+static void md5_process( md5_context *ctx, const unsigned char data[64] )
+{
+    unsigned long X[16], A, B, C, D;
+
+    GET_ULONG_LE( X[ 0], data,  0 );
+    GET_ULONG_LE( X[ 1], data,  4 );
+    GET_ULONG_LE( X[ 2], data,  8 );
+    GET_ULONG_LE( X[ 3], data, 12 );
+    GET_ULONG_LE( X[ 4], data, 16 );
+    GET_ULONG_LE( X[ 5], data, 20 );
+    GET_ULONG_LE( X[ 6], data, 24 );
+    GET_ULONG_LE( X[ 7], data, 28 );
+    GET_ULONG_LE( X[ 8], data, 32 );
+    GET_ULONG_LE( X[ 9], data, 36 );
+    GET_ULONG_LE( X[10], data, 40 );
+    GET_ULONG_LE( X[11], data, 44 );
+    GET_ULONG_LE( X[12], data, 48 );
+    GET_ULONG_LE( X[13], data, 52 );
+    GET_ULONG_LE( X[14], data, 56 );
+    GET_ULONG_LE( X[15], data, 60 );
+
+#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
+
+#define P(a,b,c,d,k,s,t)                                \
+{                                                       \
+    a += F(b,c,d) + X[k] + t; a = S(a,s) + b;           \
+}
+
+    A = ctx->state[0];
+    B = ctx->state[1];
+    C = ctx->state[2];
+    D = ctx->state[3];
+
+#define F(x,y,z) (z ^ (x & (y ^ z)))
+
+    P( A, B, C, D,  0,  7, 0xD76AA478 );
+    P( D, A, B, C,  1, 12, 0xE8C7B756 );
+    P( C, D, A, B,  2, 17, 0x242070DB );
+    P( B, C, D, A,  3, 22, 0xC1BDCEEE );
+    P( A, B, C, D,  4,  7, 0xF57C0FAF );
+    P( D, A, B, C,  5, 12, 0x4787C62A );
+    P( C, D, A, B,  6, 17, 0xA8304613 );
+    P( B, C, D, A,  7, 22, 0xFD469501 );
+    P( A, B, C, D,  8,  7, 0x698098D8 );
+    P( D, A, B, C,  9, 12, 0x8B44F7AF );
+    P( C, D, A, B, 10, 17, 0xFFFF5BB1 );
+    P( B, C, D, A, 11, 22, 0x895CD7BE );
+    P( A, B, C, D, 12,  7, 0x6B901122 );
+    P( D, A, B, C, 13, 12, 0xFD987193 );
+    P( C, D, A, B, 14, 17, 0xA679438E );
+    P( B, C, D, A, 15, 22, 0x49B40821 );
+
+#undef F
+
+#define F(x,y,z) (y ^ (z & (x ^ y)))
+
+    P( A, B, C, D,  1,  5, 0xF61E2562 );
+    P( D, A, B, C,  6,  9, 0xC040B340 );
+    P( C, D, A, B, 11, 14, 0x265E5A51 );
+    P( B, C, D, A,  0, 20, 0xE9B6C7AA );
+    P( A, B, C, D,  5,  5, 0xD62F105D );
+    P( D, A, B, C, 10,  9, 0x02441453 );
+    P( C, D, A, B, 15, 14, 0xD8A1E681 );
+    P( B, C, D, A,  4, 20, 0xE7D3FBC8 );
+    P( A, B, C, D,  9,  5, 0x21E1CDE6 );
+    P( D, A, B, C, 14,  9, 0xC33707D6 );
+    P( C, D, A, B,  3, 14, 0xF4D50D87 );
+    P( B, C, D, A,  8, 20, 0x455A14ED );
+    P( A, B, C, D, 13,  5, 0xA9E3E905 );
+    P( D, A, B, C,  2,  9, 0xFCEFA3F8 );
+    P( C, D, A, B,  7, 14, 0x676F02D9 );
+    P( B, C, D, A, 12, 20, 0x8D2A4C8A );
+
+#undef F
+    
+#define F(x,y,z) (x ^ y ^ z)
+
+    P( A, B, C, D,  5,  4, 0xFFFA3942 );
+    P( D, A, B, C,  8, 11, 0x8771F681 );
+    P( C, D, A, B, 11, 16, 0x6D9D6122 );
+    P( B, C, D, A, 14, 23, 0xFDE5380C );
+    P( A, B, C, D,  1,  4, 0xA4BEEA44 );
+    P( D, A, B, C,  4, 11, 0x4BDECFA9 );
+    P( C, D, A, B,  7, 16, 0xF6BB4B60 );
+    P( B, C, D, A, 10, 23, 0xBEBFBC70 );
+    P( A, B, C, D, 13,  4, 0x289B7EC6 );
+    P( D, A, B, C,  0, 11, 0xEAA127FA );
+    P( C, D, A, B,  3, 16, 0xD4EF3085 );
+    P( B, C, D, A,  6, 23, 0x04881D05 );
+    P( A, B, C, D,  9,  4, 0xD9D4D039 );
+    P( D, A, B, C, 12, 11, 0xE6DB99E5 );
+    P( C, D, A, B, 15, 16, 0x1FA27CF8 );
+    P( B, C, D, A,  2, 23, 0xC4AC5665 );
+
+#undef F
+
+#define F(x,y,z) (y ^ (x | ~z))
+
+    P( A, B, C, D,  0,  6, 0xF4292244 );
+    P( D, A, B, C,  7, 10, 0x432AFF97 );
+    P( C, D, A, B, 14, 15, 0xAB9423A7 );
+    P( B, C, D, A,  5, 21, 0xFC93A039 );
+    P( A, B, C, D, 12,  6, 0x655B59C3 );
+    P( D, A, B, C,  3, 10, 0x8F0CCC92 );
+    P( C, D, A, B, 10, 15, 0xFFEFF47D );
+    P( B, C, D, A,  1, 21, 0x85845DD1 );
+    P( A, B, C, D,  8,  6, 0x6FA87E4F );
+    P( D, A, B, C, 15, 10, 0xFE2CE6E0 );
+    P( C, D, A, B,  6, 15, 0xA3014314 );
+    P( B, C, D, A, 13, 21, 0x4E0811A1 );
+    P( A, B, C, D,  4,  6, 0xF7537E82 );
+    P( D, A, B, C, 11, 10, 0xBD3AF235 );
+    P( C, D, A, B,  2, 15, 0x2AD7D2BB );
+    P( B, C, D, A,  9, 21, 0xEB86D391 );
+
+#undef F
+
+    ctx->state[0] += A;
+    ctx->state[1] += B;
+    ctx->state[2] += C;
+    ctx->state[3] += D;
+}
+
+/*
+ * MD5 process buffer
+ */
+void md5_update( md5_context *ctx, const unsigned char *input, int ilen )
+{
+    int fill;
+    unsigned long left;
+
+    if( ilen <= 0 )
+        return;
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (unsigned long) ilen )
+        ctx->total[1]++;
+
+    if( left && ilen >= fill )
+    {
+        MEMCPY( (void *) (ctx->buffer + left),
+                input, fill );
+        md5_process( ctx, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 )
+    {
+        md5_process( ctx, input );
+        input += 64;
+        ilen  -= 64;
+    }
+
+    if( ilen > 0 )
+    {
+        MEMCPY( (void *) (ctx->buffer + left),
+                input, ilen );
+    }
+}
+
+static const unsigned char md5_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*
+ * MD5 final digest
+ */
+void md5_finish( md5_context *ctx, unsigned char output[16] )
+{
+    unsigned long last, padn;
+    unsigned long high, low;
+    unsigned char msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_ULONG_LE( low,  msglen, 0 );
+    PUT_ULONG_LE( high, msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    md5_update( ctx, md5_padding, padn );
+    md5_update( ctx, msglen, 8 );
+
+    PUT_ULONG_LE( ctx->state[0], output,  0 );
+    PUT_ULONG_LE( ctx->state[1], output,  4 );
+    PUT_ULONG_LE( ctx->state[2], output,  8 );
+    PUT_ULONG_LE( ctx->state[3], output, 12 );
+}
+
+/*
+ * output = MD5( input buffer )
+ */
+void md5( unsigned char *input, int ilen, unsigned char output[16] )
+{
+    md5_context ctx;
+
+    md5_starts( &ctx );
+    md5_update( &ctx, input, ilen );
+    md5_finish( &ctx, output );
+}
+
+#endif /* PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_MD5 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/sha1.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/sha1.c
new file mode 100644
index 000000000..c2192eac5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/polarssl/sha1.c
@@ -0,0 +1,335 @@
+/*
+ *  FIPS-180-1 compliant SHA-1 implementation
+ *
+ *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
+ *
+ *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
+ *
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *  
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *  
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  The SHA-1 standard was published by NIST in 1993.
+ *
+ *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_SHA1
+
+#include "netif/ppp/polarssl/sha1.h"
+
+#include <string.h>
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_ULONG_BE
+#define GET_ULONG_BE(n,b,i)                             \
+{                                                       \
+    (n) = ( (unsigned long) (b)[(i)    ] << 24 )        \
+        | ( (unsigned long) (b)[(i) + 1] << 16 )        \
+        | ( (unsigned long) (b)[(i) + 2] <<  8 )        \
+        | ( (unsigned long) (b)[(i) + 3]       );       \
+}
+#endif
+
+#ifndef PUT_ULONG_BE
+#define PUT_ULONG_BE(n,b,i)                             \
+{                                                       \
+    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
+}
+#endif
+
+/*
+ * SHA-1 context setup
+ */
+void sha1_starts( sha1_context *ctx )
+{
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+
+    ctx->state[0] = 0x67452301;
+    ctx->state[1] = 0xEFCDAB89;
+    ctx->state[2] = 0x98BADCFE;
+    ctx->state[3] = 0x10325476;
+    ctx->state[4] = 0xC3D2E1F0;
+}
+
+static void sha1_process( sha1_context *ctx, const unsigned char data[64] )
+{
+    unsigned long temp, W[16], A, B, C, D, E;
+
+    GET_ULONG_BE( W[ 0], data,  0 );
+    GET_ULONG_BE( W[ 1], data,  4 );
+    GET_ULONG_BE( W[ 2], data,  8 );
+    GET_ULONG_BE( W[ 3], data, 12 );
+    GET_ULONG_BE( W[ 4], data, 16 );
+    GET_ULONG_BE( W[ 5], data, 20 );
+    GET_ULONG_BE( W[ 6], data, 24 );
+    GET_ULONG_BE( W[ 7], data, 28 );
+    GET_ULONG_BE( W[ 8], data, 32 );
+    GET_ULONG_BE( W[ 9], data, 36 );
+    GET_ULONG_BE( W[10], data, 40 );
+    GET_ULONG_BE( W[11], data, 44 );
+    GET_ULONG_BE( W[12], data, 48 );
+    GET_ULONG_BE( W[13], data, 52 );
+    GET_ULONG_BE( W[14], data, 56 );
+    GET_ULONG_BE( W[15], data, 60 );
+
+#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
+
+#define R(t)                                            \
+(                                                       \
+    temp = W[(t -  3) & 0x0F] ^ W[(t - 8) & 0x0F] ^     \
+           W[(t - 14) & 0x0F] ^ W[ t      & 0x0F],      \
+    ( W[t & 0x0F] = S(temp,1) )                         \
+)
+
+#define P(a,b,c,d,e,x)                                  \
+{                                                       \
+    e += S(a,5) + F(b,c,d) + K + x; b = S(b,30);        \
+}
+
+    A = ctx->state[0];
+    B = ctx->state[1];
+    C = ctx->state[2];
+    D = ctx->state[3];
+    E = ctx->state[4];
+
+#define F(x,y,z) (z ^ (x & (y ^ z)))
+#define K 0x5A827999
+
+    P( A, B, C, D, E, W[0]  );
+    P( E, A, B, C, D, W[1]  );
+    P( D, E, A, B, C, W[2]  );
+    P( C, D, E, A, B, W[3]  );
+    P( B, C, D, E, A, W[4]  );
+    P( A, B, C, D, E, W[5]  );
+    P( E, A, B, C, D, W[6]  );
+    P( D, E, A, B, C, W[7]  );
+    P( C, D, E, A, B, W[8]  );
+    P( B, C, D, E, A, W[9]  );
+    P( A, B, C, D, E, W[10] );
+    P( E, A, B, C, D, W[11] );
+    P( D, E, A, B, C, W[12] );
+    P( C, D, E, A, B, W[13] );
+    P( B, C, D, E, A, W[14] );
+    P( A, B, C, D, E, W[15] );
+    P( E, A, B, C, D, R(16) );
+    P( D, E, A, B, C, R(17) );
+    P( C, D, E, A, B, R(18) );
+    P( B, C, D, E, A, R(19) );
+
+#undef K
+#undef F
+
+#define F(x,y,z) (x ^ y ^ z)
+#define K 0x6ED9EBA1
+
+    P( A, B, C, D, E, R(20) );
+    P( E, A, B, C, D, R(21) );
+    P( D, E, A, B, C, R(22) );
+    P( C, D, E, A, B, R(23) );
+    P( B, C, D, E, A, R(24) );
+    P( A, B, C, D, E, R(25) );
+    P( E, A, B, C, D, R(26) );
+    P( D, E, A, B, C, R(27) );
+    P( C, D, E, A, B, R(28) );
+    P( B, C, D, E, A, R(29) );
+    P( A, B, C, D, E, R(30) );
+    P( E, A, B, C, D, R(31) );
+    P( D, E, A, B, C, R(32) );
+    P( C, D, E, A, B, R(33) );
+    P( B, C, D, E, A, R(34) );
+    P( A, B, C, D, E, R(35) );
+    P( E, A, B, C, D, R(36) );
+    P( D, E, A, B, C, R(37) );
+    P( C, D, E, A, B, R(38) );
+    P( B, C, D, E, A, R(39) );
+
+#undef K
+#undef F
+
+#define F(x,y,z) ((x & y) | (z & (x | y)))
+#define K 0x8F1BBCDC
+
+    P( A, B, C, D, E, R(40) );
+    P( E, A, B, C, D, R(41) );
+    P( D, E, A, B, C, R(42) );
+    P( C, D, E, A, B, R(43) );
+    P( B, C, D, E, A, R(44) );
+    P( A, B, C, D, E, R(45) );
+    P( E, A, B, C, D, R(46) );
+    P( D, E, A, B, C, R(47) );
+    P( C, D, E, A, B, R(48) );
+    P( B, C, D, E, A, R(49) );
+    P( A, B, C, D, E, R(50) );
+    P( E, A, B, C, D, R(51) );
+    P( D, E, A, B, C, R(52) );
+    P( C, D, E, A, B, R(53) );
+    P( B, C, D, E, A, R(54) );
+    P( A, B, C, D, E, R(55) );
+    P( E, A, B, C, D, R(56) );
+    P( D, E, A, B, C, R(57) );
+    P( C, D, E, A, B, R(58) );
+    P( B, C, D, E, A, R(59) );
+
+#undef K
+#undef F
+
+#define F(x,y,z) (x ^ y ^ z)
+#define K 0xCA62C1D6
+
+    P( A, B, C, D, E, R(60) );
+    P( E, A, B, C, D, R(61) );
+    P( D, E, A, B, C, R(62) );
+    P( C, D, E, A, B, R(63) );
+    P( B, C, D, E, A, R(64) );
+    P( A, B, C, D, E, R(65) );
+    P( E, A, B, C, D, R(66) );
+    P( D, E, A, B, C, R(67) );
+    P( C, D, E, A, B, R(68) );
+    P( B, C, D, E, A, R(69) );
+    P( A, B, C, D, E, R(70) );
+    P( E, A, B, C, D, R(71) );
+    P( D, E, A, B, C, R(72) );
+    P( C, D, E, A, B, R(73) );
+    P( B, C, D, E, A, R(74) );
+    P( A, B, C, D, E, R(75) );
+    P( E, A, B, C, D, R(76) );
+    P( D, E, A, B, C, R(77) );
+    P( C, D, E, A, B, R(78) );
+    P( B, C, D, E, A, R(79) );
+
+#undef K
+#undef F
+
+    ctx->state[0] += A;
+    ctx->state[1] += B;
+    ctx->state[2] += C;
+    ctx->state[3] += D;
+    ctx->state[4] += E;
+}
+
+/*
+ * SHA-1 process buffer
+ */
+void sha1_update( sha1_context *ctx, const unsigned char *input, int ilen )
+{
+    int fill;
+    unsigned long left;
+
+    if( ilen <= 0 )
+        return;
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (unsigned long) ilen )
+        ctx->total[1]++;
+
+    if( left && ilen >= fill )
+    {
+        MEMCPY( (void *) (ctx->buffer + left),
+                input, fill );
+        sha1_process( ctx, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 )
+    {
+        sha1_process( ctx, input );
+        input += 64;
+        ilen  -= 64;
+    }
+
+    if( ilen > 0 )
+    {
+        MEMCPY( (void *) (ctx->buffer + left),
+                input, ilen );
+    }
+}
+
+static const unsigned char sha1_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*
+ * SHA-1 final digest
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] )
+{
+    unsigned long last, padn;
+    unsigned long high, low;
+    unsigned char msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_ULONG_BE( high, msglen, 0 );
+    PUT_ULONG_BE( low,  msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    sha1_update( ctx, sha1_padding, padn );
+    sha1_update( ctx, msglen, 8 );
+
+    PUT_ULONG_BE( ctx->state[0], output,  0 );
+    PUT_ULONG_BE( ctx->state[1], output,  4 );
+    PUT_ULONG_BE( ctx->state[2], output,  8 );
+    PUT_ULONG_BE( ctx->state[3], output, 12 );
+    PUT_ULONG_BE( ctx->state[4], output, 16 );
+}
+
+/*
+ * output = SHA-1( input buffer )
+ */
+void sha1( unsigned char *input, int ilen, unsigned char output[20] )
+{
+    sha1_context ctx;
+
+    sha1_starts( &ctx );
+    sha1_update( &ctx, input, ilen );
+    sha1_finish( &ctx, output );
+}
+
+#endif /* PPP_SUPPORT && LWIP_INCLUDED_POLARSSL_SHA1 */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ppp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ppp.c
new file mode 100644
index 000000000..a9c18e304
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/ppp.c
@@ -0,0 +1,1628 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/**
+ * @defgroup ppp PPP
+ * @ingroup netifs
+ * @verbinclude "ppp.txt"
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+#include "lwip/sys.h"
+#include "lwip/tcpip.h"
+#include "lwip/api.h"
+#include "lwip/snmp.h"
+#include "lwip/ip4.h" /* for ip4_input() */
+#if PPP_IPV6_SUPPORT
+#include "lwip/ip6.h" /* for ip6_input() */
+#endif /* PPP_IPV6_SUPPORT */
+#include "lwip/dns.h"
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/pppos.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/lcp.h"
+#include "netif/ppp/magic.h"
+
+#if PAP_SUPPORT
+#include "netif/ppp/upap.h"
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+#include "netif/ppp/chap-new.h"
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+#include "netif/ppp/eap.h"
+#endif /* EAP_SUPPORT */
+#if CCP_SUPPORT
+#include "netif/ppp/ccp.h"
+#endif /* CCP_SUPPORT */
+#if MPPE_SUPPORT
+#include "netif/ppp/mppe.h"
+#endif /* MPPE_SUPPORT */
+#if ECP_SUPPORT
+#include "netif/ppp/ecp.h"
+#endif /* EAP_SUPPORT */
+#if VJ_SUPPORT
+#include "netif/ppp/vj.h"
+#endif /* VJ_SUPPORT */
+#if PPP_IPV4_SUPPORT
+#include "netif/ppp/ipcp.h"
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+#include "netif/ppp/ipv6cp.h"
+#endif /* PPP_IPV6_SUPPORT */
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Memory pools */
+#if PPPOS_SUPPORT
+LWIP_MEMPOOL_PROTOTYPE(PPPOS_PCB);
+#endif
+#if PPPOE_SUPPORT
+LWIP_MEMPOOL_PROTOTYPE(PPPOE_IF);
+#endif
+#if PPPOL2TP_SUPPORT
+LWIP_MEMPOOL_PROTOTYPE(PPPOL2TP_PCB);
+#endif
+#if LWIP_PPP_API && LWIP_MPU_COMPATIBLE
+LWIP_MEMPOOL_PROTOTYPE(PPPAPI_MSG);
+#endif
+LWIP_MEMPOOL_DECLARE(PPP_PCB, MEMP_NUM_PPP_PCB, sizeof(ppp_pcb), "PPP_PCB")
+
+/* FIXME: add stats per PPP session */
+#if PPP_STATS_SUPPORT
+static struct timeval start_time; /* Time when link was started. */
+static struct pppd_stats old_link_stats;
+struct pppd_stats link_stats;
+unsigned link_connect_time;
+int link_stats_valid;
+#endif /* PPP_STATS_SUPPORT */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+const struct protent* const protocols[] = {
+    &lcp_protent,
+#if PAP_SUPPORT
+    &pap_protent,
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+    &chap_protent,
+#endif /* CHAP_SUPPORT */
+#if CBCP_SUPPORT
+    &cbcp_protent,
+#endif /* CBCP_SUPPORT */
+#if PPP_IPV4_SUPPORT
+    &ipcp_protent,
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+    &ipv6cp_protent,
+#endif /* PPP_IPV6_SUPPORT */
+#if CCP_SUPPORT
+    &ccp_protent,
+#endif /* CCP_SUPPORT */
+#if ECP_SUPPORT
+    &ecp_protent,
+#endif /* ECP_SUPPORT */
+#ifdef AT_CHANGE
+    &atcp_protent,
+#endif /* AT_CHANGE */
+#if EAP_SUPPORT
+    &eap_protent,
+#endif /* EAP_SUPPORT */
+    NULL
+};
+
+/* Prototypes for procedures local to this file. */
+static void ppp_do_connect(void *arg);
+static err_t ppp_netif_init_cb(struct netif *netif);
+#if PPP_IPV4_SUPPORT
+static err_t ppp_netif_output_ip4(struct netif *netif, struct pbuf *pb, const ip4_addr_t *ipaddr);
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+static err_t ppp_netif_output_ip6(struct netif *netif, struct pbuf *pb, const ip6_addr_t *ipaddr);
+#endif /* PPP_IPV6_SUPPORT */
+static err_t ppp_netif_output(struct netif *netif, struct pbuf *pb, u16_t protocol);
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+#if PPP_AUTH_SUPPORT
+void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd) {
+  LWIP_ASSERT_CORE_LOCKED();
+#if PAP_SUPPORT
+  pcb->settings.refuse_pap = !(authtype & PPPAUTHTYPE_PAP);
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+  pcb->settings.refuse_chap = !(authtype & PPPAUTHTYPE_CHAP);
+#if MSCHAP_SUPPORT
+  pcb->settings.refuse_mschap = !(authtype & PPPAUTHTYPE_MSCHAP);
+  pcb->settings.refuse_mschap_v2 = !(authtype & PPPAUTHTYPE_MSCHAP_V2);
+#endif /* MSCHAP_SUPPORT */
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+  pcb->settings.refuse_eap = !(authtype & PPPAUTHTYPE_EAP);
+#endif /* EAP_SUPPORT */
+  pcb->settings.user = user;
+  pcb->settings.passwd = passwd;
+}
+#endif /* PPP_AUTH_SUPPORT */
+
+#if MPPE_SUPPORT
+/* Set MPPE configuration */
+void ppp_set_mppe(ppp_pcb *pcb, u8_t flags) {
+  if (flags == PPP_MPPE_DISABLE) {
+    pcb->settings.require_mppe = 0;
+    return;
+  }
+
+  pcb->settings.require_mppe = 1;
+  pcb->settings.refuse_mppe_stateful = !(flags & PPP_MPPE_ALLOW_STATEFUL);
+  pcb->settings.refuse_mppe_40 = !!(flags & PPP_MPPE_REFUSE_40);
+  pcb->settings.refuse_mppe_128 = !!(flags & PPP_MPPE_REFUSE_128);
+}
+#endif /* MPPE_SUPPORT */
+
+#if PPP_NOTIFY_PHASE
+void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb) {
+  pcb->notify_phase_cb = notify_phase_cb;
+  notify_phase_cb(pcb, pcb->phase, pcb->ctx_cb);
+}
+#endif /* PPP_NOTIFY_PHASE */
+
+/*
+ * Initiate a PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * Holdoff is the time to wait (in seconds) before initiating
+ * the connection.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff) {
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb->phase != PPP_PHASE_DEAD) {
+    return ERR_ALREADY;
+  }
+
+  PPPDEBUG(LOG_DEBUG, ("ppp_connect[%d]: holdoff=%d\n", pcb->netif->num, holdoff));
+
+  magic_randomize();
+
+  if (holdoff == 0) {
+    ppp_do_connect(pcb);
+    return ERR_OK;
+  }
+
+  new_phase(pcb, PPP_PHASE_HOLDOFF);
+  sys_timeout((u32_t)(holdoff*1000), ppp_do_connect, pcb);
+  return ERR_OK;
+}
+
+#if PPP_SERVER
+/*
+ * Listen for an incoming PPP connection.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * If this port connects to a modem, the modem connection must be
+ * established before calling this.
+ */
+err_t ppp_listen(ppp_pcb *pcb) {
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb->phase != PPP_PHASE_DEAD) {
+    return ERR_ALREADY;
+  }
+
+  PPPDEBUG(LOG_DEBUG, ("ppp_listen[%d]\n", pcb->netif->num));
+
+  magic_randomize();
+
+  if (pcb->link_cb->listen) {
+    new_phase(pcb, PPP_PHASE_INITIALIZE);
+    pcb->link_cb->listen(pcb, pcb->link_ctx_cb);
+    return ERR_OK;
+  }
+  return ERR_IF;
+}
+#endif /* PPP_SERVER */
+
+/*
+ * Initiate the end of a PPP connection.
+ * Any outstanding packets in the queues are dropped.
+ *
+ * Setting nocarrier to 1 close the PPP connection without initiating the
+ * shutdown procedure. Always using nocarrier = 0 is still recommended,
+ * this is going to take a little longer time if your link is down, but
+ * is a safer choice for the PPP state machine.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t
+ppp_close(ppp_pcb *pcb, u8_t nocarrier)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pcb->err_code = PPPERR_USER;
+
+  /* holdoff phase, cancel the reconnection */
+  if (pcb->phase == PPP_PHASE_HOLDOFF) {
+    sys_untimeout(ppp_do_connect, pcb);
+    new_phase(pcb, PPP_PHASE_DEAD);
+  }
+
+  /* dead phase, nothing to do, call the status callback to be consistent */
+  if (pcb->phase == PPP_PHASE_DEAD) {
+    pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb);
+    return ERR_OK;
+  }
+
+  /* Already terminating, nothing to do */
+  if (pcb->phase >= PPP_PHASE_TERMINATE) {
+    return ERR_INPROGRESS;
+  }
+
+  /* LCP not open, close link protocol */
+  if (pcb->phase < PPP_PHASE_ESTABLISH) {
+    new_phase(pcb, PPP_PHASE_DISCONNECT);
+    ppp_link_terminated(pcb);
+    return ERR_OK;
+  }
+
+  /*
+   * Only accept carrier lost signal on the stable running phase in order
+   * to prevent changing the PPP phase FSM in transition phases.
+   *
+   * Always using nocarrier = 0 is still recommended, this is going to
+   * take a little longer time, but is a safer choice from FSM point of view.
+   */
+  if (nocarrier && pcb->phase == PPP_PHASE_RUNNING) {
+    PPPDEBUG(LOG_DEBUG, ("ppp_close[%d]: carrier lost -> lcp_lowerdown\n", pcb->netif->num));
+    lcp_lowerdown(pcb);
+    /* forced link termination, this will force link protocol to disconnect. */
+    link_terminated(pcb);
+    return ERR_OK;
+  }
+
+  /* Disconnect */
+  PPPDEBUG(LOG_DEBUG, ("ppp_close[%d]: kill_link -> lcp_close\n", pcb->netif->num));
+  /* LCP soft close request. */
+  lcp_close(pcb, "User request");
+  return ERR_OK;
+}
+
+/*
+ * Release the control block.
+ *
+ * This can only be called if PPP is in the dead phase.
+ *
+ * You must use ppp_close() before if you wish to terminate
+ * an established PPP session.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+err_t ppp_free(ppp_pcb *pcb) {
+  err_t err;
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb->phase != PPP_PHASE_DEAD) {
+    return ERR_CONN;
+  }
+
+  PPPDEBUG(LOG_DEBUG, ("ppp_free[%d]\n", pcb->netif->num));
+
+  netif_remove(pcb->netif);
+
+  err = pcb->link_cb->free(pcb, pcb->link_ctx_cb);
+
+  LWIP_MEMPOOL_FREE(PPP_PCB, pcb);
+  return err;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+err_t
+ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg)
+{
+  LWIP_ASSERT_CORE_LOCKED();
+  if (pcb == NULL) {
+    return ERR_VAL;
+  }
+
+  switch(cmd) {
+    case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+      if (!arg) {
+        goto fail;
+      }
+      *(int *)arg = (int)(0
+#if PPP_IPV4_SUPPORT
+           || pcb->if4_up
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+           || pcb->if6_up
+#endif /* PPP_IPV6_SUPPORT */
+           );
+      return ERR_OK;
+
+    case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+      if (!arg) {
+        goto fail;
+      }
+      *(int *)arg = (int)(pcb->err_code);
+      return ERR_OK;
+
+    default:
+      goto fail;
+  }
+
+fail:
+  return ERR_VAL;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+static void ppp_do_connect(void *arg) {
+  ppp_pcb *pcb = (ppp_pcb*)arg;
+
+  LWIP_ASSERT("pcb->phase == PPP_PHASE_DEAD || pcb->phase == PPP_PHASE_HOLDOFF", pcb->phase == PPP_PHASE_DEAD || pcb->phase == PPP_PHASE_HOLDOFF);
+
+  new_phase(pcb, PPP_PHASE_INITIALIZE);
+  pcb->link_cb->connect(pcb, pcb->link_ctx_cb);
+}
+
+/*
+ * ppp_netif_init_cb - netif init callback
+ */
+static err_t ppp_netif_init_cb(struct netif *netif) {
+  netif->name[0] = 'p';
+  netif->name[1] = 'p';
+#if PPP_IPV4_SUPPORT
+  netif->output = ppp_netif_output_ip4;
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+  netif->output_ip6 = ppp_netif_output_ip6;
+#endif /* PPP_IPV6_SUPPORT */
+  netif->flags = NETIF_FLAG_UP;
+#if LWIP_NETIF_HOSTNAME
+  /* @todo: Initialize interface hostname */
+  /* netif_set_hostname(netif, "lwip"); */
+#endif /* LWIP_NETIF_HOSTNAME */
+  return ERR_OK;
+}
+
+#if PPP_IPV4_SUPPORT
+/*
+ * Send an IPv4 packet on the given connection.
+ */
+static err_t ppp_netif_output_ip4(struct netif *netif, struct pbuf *pb, const ip4_addr_t *ipaddr) {
+  LWIP_UNUSED_ARG(ipaddr);
+  return ppp_netif_output(netif, pb, PPP_IP);
+}
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+/*
+ * Send an IPv6 packet on the given connection.
+ */
+static err_t ppp_netif_output_ip6(struct netif *netif, struct pbuf *pb, const ip6_addr_t *ipaddr) {
+  LWIP_UNUSED_ARG(ipaddr);
+  return ppp_netif_output(netif, pb, PPP_IPV6);
+}
+#endif /* PPP_IPV6_SUPPORT */
+
+static err_t ppp_netif_output(struct netif *netif, struct pbuf *pb, u16_t protocol) {
+  ppp_pcb *pcb = (ppp_pcb*)netif->state;
+  err_t err;
+  struct pbuf *fpb = NULL;
+
+  /* Check that the link is up. */
+  if (0
+#if PPP_IPV4_SUPPORT
+      || (protocol == PPP_IP && !pcb->if4_up)
+#endif /* PPP_IPV4_SUPPORT */
+#if PPP_IPV6_SUPPORT
+      || (protocol == PPP_IPV6 && !pcb->if6_up)
+#endif /* PPP_IPV6_SUPPORT */
+      ) {
+    PPPDEBUG(LOG_ERR, ("ppp_netif_output[%d]: link not up\n", pcb->netif->num));
+    goto err_rte_drop;
+  }
+
+#if MPPE_SUPPORT
+  /* If MPPE is required, refuse any IP packet until we are able to crypt them. */
+  if (pcb->settings.require_mppe && pcb->ccp_transmit_method != CI_MPPE) {
+    PPPDEBUG(LOG_ERR, ("ppp_netif_output[%d]: MPPE required, not up\n", pcb->netif->num));
+    goto err_rte_drop;
+  }
+#endif /* MPPE_SUPPORT */
+
+#if VJ_SUPPORT
+  /*
+   * Attempt Van Jacobson header compression if VJ is configured and
+   * this is an IP packet.
+   */
+  if (protocol == PPP_IP && pcb->vj_enabled) {
+    switch (vj_compress_tcp(&pcb->vj_comp, &pb)) {
+      case TYPE_IP:
+        /* No change...
+           protocol = PPP_IP; */
+        break;
+      case TYPE_COMPRESSED_TCP:
+        /* vj_compress_tcp() returns a new allocated pbuf, indicate we should free
+         * our duplicated pbuf later */
+        fpb = pb;
+        protocol = PPP_VJC_COMP;
+        break;
+      case TYPE_UNCOMPRESSED_TCP:
+        /* vj_compress_tcp() returns a new allocated pbuf, indicate we should free
+         * our duplicated pbuf later */
+        fpb = pb;
+        protocol = PPP_VJC_UNCOMP;
+        break;
+      default:
+        PPPDEBUG(LOG_WARNING, ("ppp_netif_output[%d]: bad IP packet\n", pcb->netif->num));
+        LINK_STATS_INC(link.proterr);
+        LINK_STATS_INC(link.drop);
+        MIB2_STATS_NETIF_INC(pcb->netif, ifoutdiscards);
+        return ERR_VAL;
+    }
+  }
+#endif /* VJ_SUPPORT */
+
+#if CCP_SUPPORT
+  switch (pcb->ccp_transmit_method) {
+  case 0:
+    break; /* Don't compress */
+#if MPPE_SUPPORT
+  case CI_MPPE:
+    if ((err = mppe_compress(pcb, &pcb->mppe_comp, &pb, protocol)) != ERR_OK) {
+      LINK_STATS_INC(link.memerr);
+      LINK_STATS_INC(link.drop);
+      MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+      goto err;
+    }
+    /* if VJ compressor returned a new allocated pbuf, free it */
+    if (fpb) {
+      pbuf_free(fpb);
+    }
+    /* mppe_compress() returns a new allocated pbuf, indicate we should free
+     * our duplicated pbuf later */
+    fpb = pb;
+    protocol = PPP_COMP;
+    break;
+#endif /* MPPE_SUPPORT */
+  default:
+    PPPDEBUG(LOG_ERR, ("ppp_netif_output[%d]: bad CCP transmit method\n", pcb->netif->num));
+    goto err_rte_drop; /* Cannot really happen, we only negotiate what we are able to do */
+  }
+#endif /* CCP_SUPPORT */
+
+  err = pcb->link_cb->netif_output(pcb, pcb->link_ctx_cb, pb, protocol);
+  goto err;
+
+err_rte_drop:
+  err = ERR_RTE;
+  LINK_STATS_INC(link.rterr);
+  LINK_STATS_INC(link.drop);
+  MIB2_STATS_NETIF_INC(netif, ifoutdiscards);
+err:
+  if (fpb) {
+    pbuf_free(fpb);
+  }
+  return err;
+}
+
+/************************************/
+/*** PRIVATE FUNCTION DEFINITIONS ***/
+/************************************/
+
+/* Initialize the PPP subsystem. */
+int ppp_init(void)
+{
+#if PPPOS_SUPPORT
+  LWIP_MEMPOOL_INIT(PPPOS_PCB);
+#endif
+#if PPPOE_SUPPORT
+  LWIP_MEMPOOL_INIT(PPPOE_IF);
+#endif
+#if PPPOL2TP_SUPPORT
+  LWIP_MEMPOOL_INIT(PPPOL2TP_PCB);
+#endif
+#if LWIP_PPP_API && LWIP_MPU_COMPATIBLE
+  LWIP_MEMPOOL_INIT(PPPAPI_MSG);
+#endif
+
+  LWIP_MEMPOOL_INIT(PPP_PCB);
+
+  /*
+   * Initialize magic number generator now so that protocols may
+   * use magic numbers in initialization.
+   */
+  magic_init();
+
+  return 0;
+}
+ 
+/*
+ * Create a new PPP control block.
+ *
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ *
+ * Return a new PPP connection control block pointer
+ * on success or a null pointer on failure.
+ */
+ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb) {
+  ppp_pcb *pcb;
+  const struct protent *protp;
+  int i;
+
+  /* PPP is single-threaded: without a callback,
+   * there is no way to know when the link is up. */
+  if (link_status_cb == NULL) {
+    return NULL;
+  }
+
+  pcb = (ppp_pcb*)LWIP_MEMPOOL_ALLOC(PPP_PCB);
+  if (pcb == NULL) {
+    return NULL;
+  }
+
+  memset(pcb, 0, sizeof(ppp_pcb));
+
+  /* default configuration */
+#if PAP_SUPPORT
+  pcb->settings.pap_timeout_time = UPAP_DEFTIMEOUT;
+  pcb->settings.pap_max_transmits = UPAP_DEFTRANSMITS;
+#if PPP_SERVER
+  pcb->settings.pap_req_timeout = UPAP_DEFREQTIME;
+#endif /* PPP_SERVER */
+#endif /* PAP_SUPPORT */
+
+#if CHAP_SUPPORT
+  pcb->settings.chap_timeout_time = CHAP_DEFTIMEOUT;
+  pcb->settings.chap_max_transmits = CHAP_DEFTRANSMITS;
+#if PPP_SERVER
+  pcb->settings.chap_rechallenge_time = CHAP_DEFRECHALLENGETIME;
+#endif /* PPP_SERVER */
+#endif /* CHAP_SUPPPORT */
+
+#if EAP_SUPPORT
+  pcb->settings.eap_req_time = EAP_DEFREQTIME;
+  pcb->settings.eap_allow_req = EAP_DEFALLOWREQ;
+#if PPP_SERVER
+  pcb->settings.eap_timeout_time = EAP_DEFTIMEOUT;
+  pcb->settings.eap_max_transmits = EAP_DEFTRANSMITS;
+#endif /* PPP_SERVER */
+#endif /* EAP_SUPPORT */
+
+  pcb->settings.lcp_loopbackfail = LCP_DEFLOOPBACKFAIL;
+  pcb->settings.lcp_echo_interval = LCP_ECHOINTERVAL;
+  pcb->settings.lcp_echo_fails = LCP_MAXECHOFAILS;
+
+  pcb->settings.fsm_timeout_time = FSM_DEFTIMEOUT;
+  pcb->settings.fsm_max_conf_req_transmits = FSM_DEFMAXCONFREQS;
+  pcb->settings.fsm_max_term_transmits = FSM_DEFMAXTERMREQS;
+  pcb->settings.fsm_max_nak_loops = FSM_DEFMAXNAKLOOPS;
+
+  pcb->netif = pppif;
+  MIB2_INIT_NETIF(pppif, snmp_ifType_ppp, 0);
+  if (!netif_add(pcb->netif,
+#if LWIP_IPV4
+                 IP4_ADDR_ANY4, IP4_ADDR_BROADCAST, IP4_ADDR_ANY4,
+#endif /* LWIP_IPV4 */
+                 (void *)pcb, ppp_netif_init_cb, NULL)) {
+    LWIP_MEMPOOL_FREE(PPP_PCB, pcb);
+    PPPDEBUG(LOG_ERR, ("ppp_new: netif_add failed\n"));
+    return NULL;
+  }
+
+  pcb->link_cb = callbacks;
+  pcb->link_ctx_cb = link_ctx_cb;
+  pcb->link_status_cb = link_status_cb;
+  pcb->ctx_cb = ctx_cb;
+
+  /*
+   * Initialize each protocol.
+   */
+  for (i = 0; (protp = protocols[i]) != NULL; ++i) {
+      (*protp->init)(pcb);
+  }
+
+  new_phase(pcb, PPP_PHASE_DEAD);
+  return pcb;
+}
+
+/** Initiate LCP open request */
+void ppp_start(ppp_pcb *pcb) {
+  PPPDEBUG(LOG_DEBUG, ("ppp_start[%d]\n", pcb->netif->num));
+
+  /* Clean data not taken care by anything else, mostly shared data. */
+#if PPP_STATS_SUPPORT
+  link_stats_valid = 0;
+#endif /* PPP_STATS_SUPPORT */
+#if MPPE_SUPPORT
+  pcb->mppe_keys_set = 0;
+  memset(&pcb->mppe_comp, 0, sizeof(pcb->mppe_comp));
+  memset(&pcb->mppe_decomp, 0, sizeof(pcb->mppe_decomp));
+#endif /* MPPE_SUPPORT */
+#if VJ_SUPPORT
+  vj_compress_init(&pcb->vj_comp);
+#endif /* VJ_SUPPORT */
+
+  /* Start protocol */
+  new_phase(pcb, PPP_PHASE_ESTABLISH);
+  lcp_open(pcb);
+  lcp_lowerup(pcb);
+  PPPDEBUG(LOG_DEBUG, ("ppp_start[%d]: finished\n", pcb->netif->num));
+}
+
+/** Called when link failed to setup */
+void ppp_link_failed(ppp_pcb *pcb) {
+  PPPDEBUG(LOG_DEBUG, ("ppp_link_failed[%d]\n", pcb->netif->num));
+  new_phase(pcb, PPP_PHASE_DEAD);
+  pcb->err_code = PPPERR_OPEN;
+  pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb);
+}
+
+/** Called when link is normally down (i.e. it was asked to end) */
+void ppp_link_end(ppp_pcb *pcb) {
+  PPPDEBUG(LOG_DEBUG, ("ppp_link_end[%d]\n", pcb->netif->num));
+  new_phase(pcb, PPP_PHASE_DEAD);
+  if (pcb->err_code == PPPERR_NONE) {
+    pcb->err_code = PPPERR_CONNECT;
+  }
+  pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb);
+}
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+void ppp_input(ppp_pcb *pcb, struct pbuf *pb) {
+  u16_t protocol;
+#if PPP_DEBUG && PPP_PROTOCOLNAME
+    const char *pname;
+#endif /* PPP_DEBUG && PPP_PROTOCOLNAME */
+
+  magic_randomize();
+
+  if (pb->len < 2) {
+    PPPDEBUG(LOG_ERR, ("ppp_input[%d]: packet too short\n", pcb->netif->num));
+    goto drop;
+  }
+  protocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1];
+
+#if PRINTPKT_SUPPORT
+  ppp_dump_packet(pcb, "rcvd", (unsigned char *)pb->payload, pb->len);
+#endif /* PRINTPKT_SUPPORT */
+
+  pbuf_remove_header(pb, sizeof(protocol));
+
+  LINK_STATS_INC(link.recv);
+  MIB2_STATS_NETIF_INC(pcb->netif, ifinucastpkts);
+  MIB2_STATS_NETIF_ADD(pcb->netif, ifinoctets, pb->tot_len);
+
+  /*
+   * Toss all non-LCP packets unless LCP is OPEN.
+   */
+  if (protocol != PPP_LCP && pcb->lcp_fsm.state != PPP_FSM_OPENED) {
+    ppp_dbglog("Discarded non-LCP packet when LCP not open");
+    goto drop;
+  }
+
+  /*
+   * Until we get past the authentication phase, toss all packets
+   * except LCP, LQR and authentication packets.
+   */
+  if (pcb->phase <= PPP_PHASE_AUTHENTICATE
+   && !(protocol == PPP_LCP
+#if LQR_SUPPORT
+   || protocol == PPP_LQR
+#endif /* LQR_SUPPORT */
+#if PAP_SUPPORT
+   || protocol == PPP_PAP
+#endif /* PAP_SUPPORT */
+#if CHAP_SUPPORT
+   || protocol == PPP_CHAP
+#endif /* CHAP_SUPPORT */
+#if EAP_SUPPORT
+   || protocol == PPP_EAP
+#endif /* EAP_SUPPORT */
+   )) {
+    ppp_dbglog("discarding proto 0x%x in phase %d", protocol, pcb->phase);
+    goto drop;
+  }
+
+#if CCP_SUPPORT
+#if MPPE_SUPPORT
+  /*
+   * MPPE is required and unencrypted data has arrived (this
+   * should never happen!). We should probably drop the link if
+   * the protocol is in the range of what should be encrypted.
+   * At the least, we drop this packet.
+   */
+  if (pcb->settings.require_mppe && protocol != PPP_COMP && protocol < 0x8000) {
+    PPPDEBUG(LOG_ERR, ("ppp_input[%d]: MPPE required, received unencrypted data!\n", pcb->netif->num));
+    goto drop;
+  }
+#endif /* MPPE_SUPPORT */
+
+  if (protocol == PPP_COMP) {
+    u8_t *pl;
+
+    switch (pcb->ccp_receive_method) {
+#if MPPE_SUPPORT
+    case CI_MPPE:
+      if (mppe_decompress(pcb, &pcb->mppe_decomp, &pb) != ERR_OK) {
+        goto drop;
+      }
+      break;
+#endif /* MPPE_SUPPORT */
+    default:
+      PPPDEBUG(LOG_ERR, ("ppp_input[%d]: bad CCP receive method\n", pcb->netif->num));
+      goto drop; /* Cannot really happen, we only negotiate what we are able to do */
+    }
+
+    /* Assume no PFC */
+    if (pb->len < 2) {
+      goto drop;
+    }
+
+    /* Extract and hide protocol (do PFC decompression if necessary) */
+    pl = (u8_t*)pb->payload;
+    if (pl[0] & 0x01) {
+      protocol = pl[0];
+      pbuf_remove_header(pb, 1);
+    } else {
+      protocol = (pl[0] << 8) | pl[1];
+      pbuf_remove_header(pb, 2);
+    }
+  }
+#endif /* CCP_SUPPORT */
+
+  switch(protocol) {
+
+#if PPP_IPV4_SUPPORT
+    case PPP_IP:            /* Internet Protocol */
+      PPPDEBUG(LOG_INFO, ("ppp_input[%d]: ip in pbuf len=%d\n", pcb->netif->num, pb->tot_len));
+      ip4_input(pb, pcb->netif);
+      return;
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+    case PPP_IPV6:          /* Internet Protocol Version 6 */
+      PPPDEBUG(LOG_INFO, ("ppp_input[%d]: ip6 in pbuf len=%d\n", pcb->netif->num, pb->tot_len));
+      ip6_input(pb, pcb->netif);
+      return;
+#endif /* PPP_IPV6_SUPPORT */
+
+#if VJ_SUPPORT
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+      /*
+       * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+       * pass the result to IP.
+       */
+      PPPDEBUG(LOG_INFO, ("ppp_input[%d]: vj_comp in pbuf len=%d\n", pcb->netif->num, pb->tot_len));
+      if (pcb->vj_enabled && vj_uncompress_tcp(&pb, &pcb->vj_comp) >= 0) {
+        ip4_input(pb, pcb->netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG(LOG_WARNING, ("ppp_input[%d]: Dropping VJ compressed\n", pcb->netif->num));
+      break;
+
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+      /*
+       * Process the TCP/IP header for VJ header compression and then pass
+       * the packet to IP.
+       */
+      PPPDEBUG(LOG_INFO, ("ppp_input[%d]: vj_un in pbuf len=%d\n", pcb->netif->num, pb->tot_len));
+      if (pcb->vj_enabled && vj_uncompress_uncomp(pb, &pcb->vj_comp) >= 0) {
+        ip4_input(pb, pcb->netif);
+        return;
+      }
+      /* Something's wrong so drop it. */
+      PPPDEBUG(LOG_WARNING, ("ppp_input[%d]: Dropping VJ uncompressed\n", pcb->netif->num));
+      break;
+#endif /* VJ_SUPPORT */
+
+    default: {
+      int i;
+      const struct protent *protp;
+
+      /*
+       * Upcall the proper protocol input routine.
+       */
+      for (i = 0; (protp = protocols[i]) != NULL; ++i) {
+        if (protp->protocol == protocol) {
+          pb = pbuf_coalesce(pb, PBUF_RAW);
+          (*protp->input)(pcb, (u8_t*)pb->payload, pb->len);
+          goto out;
+        }
+#if 0   /* UNUSED
+         *
+         * This is actually a (hacked?) way for the Linux kernel to pass a data
+         * packet to pppd. pppd in normal condition only do signaling
+         * (LCP, PAP, CHAP, IPCP, ...) and does not handle any data packet at all.
+         *
+         * We don't even need this interface, which is only there because of PPP
+         * interface limitation between Linux kernel and pppd. For MPPE, which uses
+         * CCP to negotiate although it is not really a (de)compressor, we added
+         * ccp_resetrequest() in CCP and MPPE input data flow is calling either
+         * ccp_resetrequest() or lcp_close() if the issue is, respectively, non-fatal
+         * or fatal, this is what ccp_datainput() really do.
+         */
+        if (protocol == (protp->protocol & ~0x8000)
+          && protp->datainput != NULL) {
+          (*protp->datainput)(pcb, pb->payload, pb->len);
+          goto out;
+        }
+#endif /* UNUSED */
+      }
+
+#if PPP_DEBUG
+#if PPP_PROTOCOLNAME
+      pname = protocol_name(protocol);
+      if (pname != NULL) {
+        ppp_warn("Unsupported protocol '%s' (0x%x) received", pname, protocol);
+      } else
+#endif /* PPP_PROTOCOLNAME */
+        ppp_warn("Unsupported protocol 0x%x received", protocol);
+#endif /* PPP_DEBUG */
+        if (pbuf_add_header(pb, sizeof(protocol))) {
+          PPPDEBUG(LOG_WARNING, ("ppp_input[%d]: Dropping (pbuf_add_header failed)\n", pcb->netif->num));
+          goto drop;
+        }
+        lcp_sprotrej(pcb, (u8_t*)pb->payload, pb->len);
+      }
+      break;
+  }
+
+drop:
+  LINK_STATS_INC(link.drop);
+  MIB2_STATS_NETIF_INC(pcb->netif, ifindiscards);
+
+out:
+  pbuf_free(pb);
+}
+
+/*
+ * Write a pbuf to a ppp link, only used from PPP functions
+ * to send PPP packets.
+ *
+ * IPv4 and IPv6 packets from lwIP are sent, respectively,
+ * with ppp_netif_output_ip4() and ppp_netif_output_ip6()
+ * functions (which are callbacks of the netif PPP interface).
+ */
+err_t ppp_write(ppp_pcb *pcb, struct pbuf *p) {
+#if PRINTPKT_SUPPORT
+  ppp_dump_packet(pcb, "sent", (unsigned char *)p->payload+2, p->len-2);
+#endif /* PRINTPKT_SUPPORT */
+  return pcb->link_cb->write(pcb, pcb->link_ctx_cb, p);
+}
+
+void ppp_link_terminated(ppp_pcb *pcb) {
+  PPPDEBUG(LOG_DEBUG, ("ppp_link_terminated[%d]\n", pcb->netif->num));
+  pcb->link_cb->disconnect(pcb, pcb->link_ctx_cb);
+  PPPDEBUG(LOG_DEBUG, ("ppp_link_terminated[%d]: finished.\n", pcb->netif->num));
+}
+
+
+/************************************************************************
+ * Functions called by various PPP subsystems to configure
+ * the PPP interface or change the PPP phase.
+ */
+
+/*
+ * new_phase - signal the start of a new phase of pppd's operation.
+ */
+void new_phase(ppp_pcb *pcb, int p) {
+  pcb->phase = p;
+  PPPDEBUG(LOG_DEBUG, ("ppp phase changed[%d]: phase=%d\n", pcb->netif->num, pcb->phase));
+#if PPP_NOTIFY_PHASE
+  if (pcb->notify_phase_cb != NULL) {
+    pcb->notify_phase_cb(pcb, p, pcb->ctx_cb);
+  }
+#endif /* PPP_NOTIFY_PHASE */
+}
+
+/*
+ * ppp_send_config - configure the transmit-side characteristics of
+ * the ppp interface.
+ */
+int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp) {
+  LWIP_UNUSED_ARG(mtu);
+  /* pcb->mtu = mtu; -- set correctly with netif_set_mtu */
+
+  if (pcb->link_cb->send_config) {
+    pcb->link_cb->send_config(pcb, pcb->link_ctx_cb, accm, pcomp, accomp);
+  }
+
+  PPPDEBUG(LOG_INFO, ("ppp_send_config[%d]\n", pcb->netif->num) );
+  return 0;
+}
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp) {
+  LWIP_UNUSED_ARG(mru);
+
+  if (pcb->link_cb->recv_config) {
+    pcb->link_cb->recv_config(pcb, pcb->link_ctx_cb, accm, pcomp, accomp);
+  }
+
+  PPPDEBUG(LOG_INFO, ("ppp_recv_config[%d]\n", pcb->netif->num));
+  return 0;
+}
+
+#if PPP_IPV4_SUPPORT
+/*
+ * sifaddr - Config the interface IP addresses and netmask.
+ */
+int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask) {
+  ip4_addr_t ip, nm, gw;
+
+  ip4_addr_set_u32(&ip, our_adr);
+  ip4_addr_set_u32(&nm, netmask);
+  ip4_addr_set_u32(&gw, his_adr);
+  netif_set_addr(pcb->netif, &ip, &nm, &gw);
+  return 1;
+}
+
+/********************************************************************
+ *
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ */
+int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr) {
+  LWIP_UNUSED_ARG(our_adr);
+  LWIP_UNUSED_ARG(his_adr);
+
+  netif_set_addr(pcb->netif, IP4_ADDR_ANY4, IP4_ADDR_BROADCAST, IP4_ADDR_ANY4);
+  return 1;
+}
+
+#if 0 /* UNUSED - PROXY ARP */
+/********************************************************************
+ *
+ * sifproxyarp - Make a proxy ARP entry for the peer.
+ */
+
+int sifproxyarp(ppp_pcb *pcb, u32_t his_adr) {
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(his_adr);
+  return 0;
+}
+
+/********************************************************************
+ *
+ * cifproxyarp - Delete the proxy ARP entry for the peer.
+ */
+
+int cifproxyarp(ppp_pcb *pcb, u32_t his_adr) {
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(his_adr);
+  return 0;
+}
+#endif /* UNUSED - PROXY ARP */
+
+#if LWIP_DNS
+/*
+ * sdns - Config the DNS servers
+ */
+int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2) {
+  ip_addr_t ns;
+  LWIP_UNUSED_ARG(pcb);
+
+  ip_addr_set_ip4_u32_val(ns, ns1);
+  dns_setserver(0, &ns);
+  ip_addr_set_ip4_u32_val(ns, ns2);
+  dns_setserver(1, &ns);
+  return 1;
+}
+
+/********************************************************************
+ *
+ * cdns - Clear the DNS servers
+ */
+int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2) {
+  const ip_addr_t *nsa;
+  ip_addr_t nsb;
+  LWIP_UNUSED_ARG(pcb);
+
+  nsa = dns_getserver(0);
+  ip_addr_set_ip4_u32_val(nsb, ns1);
+  if (ip_addr_cmp(nsa, &nsb)) {
+    dns_setserver(0, IP_ADDR_ANY);
+  }
+  nsa = dns_getserver(1);
+  ip_addr_set_ip4_u32_val(nsb, ns2);
+  if (ip_addr_cmp(nsa, &nsb)) {
+    dns_setserver(1, IP_ADDR_ANY);
+  }
+  return 1;
+}
+#endif /* LWIP_DNS */
+
+#if VJ_SUPPORT
+/********************************************************************
+ *
+ * sifvjcomp - config tcp header compression
+ */
+int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid) {
+  pcb->vj_enabled = vjcomp;
+  pcb->vj_comp.compressSlot = cidcomp;
+  pcb->vj_comp.maxSlotIndex = maxcid;
+  PPPDEBUG(LOG_INFO, ("sifvjcomp[%d]: VJ compress enable=%d slot=%d max slot=%d\n",
+            pcb->netif->num, vjcomp, cidcomp, maxcid));
+  return 0;
+}
+#endif /* VJ_SUPPORT */
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int sifup(ppp_pcb *pcb) {
+  pcb->if4_up = 1;
+  pcb->err_code = PPPERR_NONE;
+  netif_set_link_up(pcb->netif);
+
+  PPPDEBUG(LOG_DEBUG, ("sifup[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code));
+  pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb);
+  return 1;
+}
+
+/********************************************************************
+ *
+ * sifdown - Disable the indicated protocol and config the interface
+ *           down if there are no remaining protocols.
+ */
+int sifdown(ppp_pcb *pcb) {
+
+  pcb->if4_up = 0;
+
+  if (1
+#if PPP_IPV6_SUPPORT
+   /* set the interface down if IPv6 is down as well */
+   && !pcb->if6_up
+#endif /* PPP_IPV6_SUPPORT */
+  ) {
+    /* make sure the netif link callback is called */
+    netif_set_link_down(pcb->netif);
+  }
+  PPPDEBUG(LOG_DEBUG, ("sifdown[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code));
+  return 1;
+}
+
+/********************************************************************
+ *
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t get_mask(u32_t addr) {
+#if 0
+  u32_t mask, nmask;
+
+  addr = lwip_htonl(addr);
+  if (IP_CLASSA(addr)) { /* determine network mask for address class */
+    nmask = IP_CLASSA_NET;
+  } else if (IP_CLASSB(addr)) {
+    nmask = IP_CLASSB_NET;
+  } else {
+    nmask = IP_CLASSC_NET;
+  }
+
+  /* class D nets are disallowed by bad_ip_adrs */
+  mask = PP_HTONL(0xffffff00UL) | lwip_htonl(nmask);
+
+  /* XXX
+   * Scan through the system's network interfaces.
+   * Get each netmask and OR them into our mask.
+   */
+  /* return mask; */
+  return mask;
+#endif /* 0 */
+  LWIP_UNUSED_ARG(addr);
+  return IPADDR_BROADCAST;
+}
+#endif /* PPP_IPV4_SUPPORT */
+
+#if PPP_IPV6_SUPPORT
+#define IN6_LLADDR_FROM_EUI64(ip6, eui64) do {    \
+  ip6.addr[0] = PP_HTONL(0xfe800000);             \
+  ip6.addr[1] = 0;                                \
+  eui64_copy(eui64, ip6.addr[2]);                 \
+  } while (0)
+
+/********************************************************************
+ *
+ * sif6addr - Config the interface with an IPv6 link-local address
+ */
+int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64) {
+  ip6_addr_t ip6;
+  LWIP_UNUSED_ARG(his_eui64);
+
+  IN6_LLADDR_FROM_EUI64(ip6, our_eui64);
+  netif_ip6_addr_set(pcb->netif, 0, &ip6);
+  netif_ip6_addr_set_state(pcb->netif, 0, IP6_ADDR_PREFERRED);
+  /* FIXME: should we add an IPv6 static neighbor using his_eui64 ? */
+  return 1;
+}
+
+/********************************************************************
+ *
+ * cif6addr - Remove IPv6 address from interface
+ */
+int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64) {
+  LWIP_UNUSED_ARG(our_eui64);
+  LWIP_UNUSED_ARG(his_eui64);
+
+  netif_ip6_addr_set_state(pcb->netif, 0, IP6_ADDR_INVALID);
+  netif_ip6_addr_set(pcb->netif, 0, IP6_ADDR_ANY6);
+  return 1;
+}
+
+/*
+ * sif6up - Config the interface up and enable IPv6 packets to pass.
+ */
+int sif6up(ppp_pcb *pcb) {
+
+  pcb->if6_up = 1;
+  pcb->err_code = PPPERR_NONE;
+  netif_set_link_up(pcb->netif);
+
+  PPPDEBUG(LOG_DEBUG, ("sif6up[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code));
+  pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb);
+  return 1;
+}
+
+/********************************************************************
+ *
+ * sif6down - Disable the indicated protocol and config the interface
+ *            down if there are no remaining protocols.
+ */
+int sif6down(ppp_pcb *pcb) {
+
+  pcb->if6_up = 0;
+
+  if (1
+#if PPP_IPV4_SUPPORT
+   /* set the interface down if IPv4 is down as well */
+   && !pcb->if4_up
+#endif /* PPP_IPV4_SUPPORT */
+  ) {
+    /* make sure the netif link callback is called */
+    netif_set_link_down(pcb->netif);
+  }
+  PPPDEBUG(LOG_DEBUG, ("sif6down[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code));
+  return 1;
+}
+#endif /* PPP_IPV6_SUPPORT */
+
+#if DEMAND_SUPPORT
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode) {
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(proto);
+  LWIP_UNUSED_ARG(mode);
+  return 0;
+}
+#endif /* DEMAND_SUPPORT */
+
+/*
+ * netif_set_mtu - set the MTU on the PPP network interface.
+ */
+void netif_set_mtu(ppp_pcb *pcb, int mtu) {
+
+  pcb->netif->mtu = mtu;
+  PPPDEBUG(LOG_INFO, ("netif_set_mtu[%d]: mtu=%d\n", pcb->netif->num, mtu));
+}
+
+/*
+ * netif_get_mtu - get PPP interface MTU
+ */
+int netif_get_mtu(ppp_pcb *pcb) {
+
+  return pcb->netif->mtu;
+}
+
+#if CCP_SUPPORT
+#if 0 /* unused */
+/*
+ * ccp_test - whether a given compression method is acceptable for use.
+ */
+int
+ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit)
+{
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(opt_ptr);
+  LWIP_UNUSED_ARG(opt_len);
+  LWIP_UNUSED_ARG(for_transmit);
+  return -1;
+}
+#endif /* unused */
+
+/*
+ * ccp_set - inform about the current state of CCP.
+ */
+void
+ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method)
+{
+  LWIP_UNUSED_ARG(isopen);
+  LWIP_UNUSED_ARG(isup);
+  pcb->ccp_receive_method = receive_method;
+  pcb->ccp_transmit_method = transmit_method;
+  PPPDEBUG(LOG_DEBUG, ("ccp_set[%d]: is_open=%d, is_up=%d, receive_method=%u, transmit_method=%u\n",
+           pcb->netif->num, isopen, isup, receive_method, transmit_method));
+}
+
+void
+ccp_reset_comp(ppp_pcb *pcb)
+{
+  switch (pcb->ccp_transmit_method) {
+#if MPPE_SUPPORT
+  case CI_MPPE:
+    mppe_comp_reset(pcb, &pcb->mppe_comp);
+    break;
+#endif /* MPPE_SUPPORT */
+  default:
+    break;
+  }
+}
+
+void
+ccp_reset_decomp(ppp_pcb *pcb)
+{
+  switch (pcb->ccp_receive_method) {
+#if MPPE_SUPPORT
+  case CI_MPPE:
+    mppe_decomp_reset(pcb, &pcb->mppe_decomp);
+    break;
+#endif /* MPPE_SUPPORT */
+  default:
+    break;
+  }
+}
+
+#if 0 /* unused */
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int
+ccp_fatal_error(ppp_pcb *pcb)
+{
+  LWIP_UNUSED_ARG(pcb);
+  return 1;
+}
+#endif /* unused */
+#endif /* CCP_SUPPORT */
+
+#if PPP_IDLETIMELIMIT
+/********************************************************************
+ *
+ * get_idle_time - return how long the link has been idle.
+ */
+int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip) {
+  /* FIXME: add idle time support and make it optional */
+  LWIP_UNUSED_ARG(pcb);
+  LWIP_UNUSED_ARG(ip);
+  return 1;
+}
+#endif /* PPP_IDLETIMELIMIT */
+
+#if DEMAND_SUPPORT
+/********************************************************************
+ *
+ * get_loop_output - get outgoing packets from the ppp device,
+ * and detect when we want to bring the real link up.
+ * Return value is 1 if we need to bring up the link, 0 otherwise.
+ */
+int get_loop_output(void) {
+  return 0;
+}
+#endif /* DEMAND_SUPPORT */
+
+#if PPP_PROTOCOLNAME
+/* List of protocol names, to make our messages a little more informative. */
+struct protocol_list {
+  u_short proto;
+  const char *name;
+} const protocol_list[] = {
+  { 0x21, "IP" },
+  { 0x23, "OSI Network Layer" },
+  { 0x25, "Xerox NS IDP" },
+  { 0x27, "DECnet Phase IV" },
+  { 0x29, "Appletalk" },
+  { 0x2b, "Novell IPX" },
+  { 0x2d, "VJ compressed TCP/IP" },
+  { 0x2f, "VJ uncompressed TCP/IP" },
+  { 0x31, "Bridging PDU" },
+  { 0x33, "Stream Protocol ST-II" },
+  { 0x35, "Banyan Vines" },
+  { 0x39, "AppleTalk EDDP" },
+  { 0x3b, "AppleTalk SmartBuffered" },
+  { 0x3d, "Multi-Link" },
+  { 0x3f, "NETBIOS Framing" },
+  { 0x41, "Cisco Systems" },
+  { 0x43, "Ascom Timeplex" },
+  { 0x45, "Fujitsu Link Backup and Load Balancing (LBLB)" },
+  { 0x47, "DCA Remote Lan" },
+  { 0x49, "Serial Data Transport Protocol (PPP-SDTP)" },
+  { 0x4b, "SNA over 802.2" },
+  { 0x4d, "SNA" },
+  { 0x4f, "IP6 Header Compression" },
+  { 0x51, "KNX Bridging Data" },
+  { 0x53, "Encryption" },
+  { 0x55, "Individual Link Encryption" },
+  { 0x57, "IPv6" },
+  { 0x59, "PPP Muxing" },
+  { 0x5b, "Vendor-Specific Network Protocol" },
+  { 0x61, "RTP IPHC Full Header" },
+  { 0x63, "RTP IPHC Compressed TCP" },
+  { 0x65, "RTP IPHC Compressed non-TCP" },
+  { 0x67, "RTP IPHC Compressed UDP 8" },
+  { 0x69, "RTP IPHC Compressed RTP 8" },
+  { 0x6f, "Stampede Bridging" },
+  { 0x73, "MP+" },
+  { 0xc1, "NTCITS IPI" },
+  { 0xfb, "single-link compression" },
+  { 0xfd, "Compressed Datagram" },
+  { 0x0201, "802.1d Hello Packets" },
+  { 0x0203, "IBM Source Routing BPDU" },
+  { 0x0205, "DEC LANBridge100 Spanning Tree" },
+  { 0x0207, "Cisco Discovery Protocol" },
+  { 0x0209, "Netcs Twin Routing" },
+  { 0x020b, "STP - Scheduled Transfer Protocol" },
+  { 0x020d, "EDP - Extreme Discovery Protocol" },
+  { 0x0211, "Optical Supervisory Channel Protocol" },
+  { 0x0213, "Optical Supervisory Channel Protocol" },
+  { 0x0231, "Luxcom" },
+  { 0x0233, "Sigma Network Systems" },
+  { 0x0235, "Apple Client Server Protocol" },
+  { 0x0281, "MPLS Unicast" },
+  { 0x0283, "MPLS Multicast" },
+  { 0x0285, "IEEE p1284.4 standard - data packets" },
+  { 0x0287, "ETSI TETRA Network Protocol Type 1" },
+  { 0x0289, "Multichannel Flow Treatment Protocol" },
+  { 0x2063, "RTP IPHC Compressed TCP No Delta" },
+  { 0x2065, "RTP IPHC Context State" },
+  { 0x2067, "RTP IPHC Compressed UDP 16" },
+  { 0x2069, "RTP IPHC Compressed RTP 16" },
+  { 0x4001, "Cray Communications Control Protocol" },
+  { 0x4003, "CDPD Mobile Network Registration Protocol" },
+  { 0x4005, "Expand accelerator protocol" },
+  { 0x4007, "ODSICP NCP" },
+  { 0x4009, "DOCSIS DLL" },
+  { 0x400B, "Cetacean Network Detection Protocol" },
+  { 0x4021, "Stacker LZS" },
+  { 0x4023, "RefTek Protocol" },
+  { 0x4025, "Fibre Channel" },
+  { 0x4027, "EMIT Protocols" },
+  { 0x405b, "Vendor-Specific Protocol (VSP)" },
+  { 0x8021, "Internet Protocol Control Protocol" },
+  { 0x8023, "OSI Network Layer Control Protocol" },
+  { 0x8025, "Xerox NS IDP Control Protocol" },
+  { 0x8027, "DECnet Phase IV Control Protocol" },
+  { 0x8029, "Appletalk Control Protocol" },
+  { 0x802b, "Novell IPX Control Protocol" },
+  { 0x8031, "Bridging NCP" },
+  { 0x8033, "Stream Protocol Control Protocol" },
+  { 0x8035, "Banyan Vines Control Protocol" },
+  { 0x803d, "Multi-Link Control Protocol" },
+  { 0x803f, "NETBIOS Framing Control Protocol" },
+  { 0x8041, "Cisco Systems Control Protocol" },
+  { 0x8043, "Ascom Timeplex" },
+  { 0x8045, "Fujitsu LBLB Control Protocol" },
+  { 0x8047, "DCA Remote Lan Network Control Protocol (RLNCP)" },
+  { 0x8049, "Serial Data Control Protocol (PPP-SDCP)" },
+  { 0x804b, "SNA over 802.2 Control Protocol" },
+  { 0x804d, "SNA Control Protocol" },
+  { 0x804f, "IP6 Header Compression Control Protocol" },
+  { 0x8051, "KNX Bridging Control Protocol" },
+  { 0x8053, "Encryption Control Protocol" },
+  { 0x8055, "Individual Link Encryption Control Protocol" },
+  { 0x8057, "IPv6 Control Protocol" },
+  { 0x8059, "PPP Muxing Control Protocol" },
+  { 0x805b, "Vendor-Specific Network Control Protocol (VSNCP)" },
+  { 0x806f, "Stampede Bridging Control Protocol" },
+  { 0x8073, "MP+ Control Protocol" },
+  { 0x80c1, "NTCITS IPI Control Protocol" },
+  { 0x80fb, "Single Link Compression Control Protocol" },
+  { 0x80fd, "Compression Control Protocol" },
+  { 0x8207, "Cisco Discovery Protocol Control" },
+  { 0x8209, "Netcs Twin Routing" },
+  { 0x820b, "STP - Control Protocol" },
+  { 0x820d, "EDPCP - Extreme Discovery Protocol Ctrl Prtcl" },
+  { 0x8235, "Apple Client Server Protocol Control" },
+  { 0x8281, "MPLSCP" },
+  { 0x8285, "IEEE p1284.4 standard - Protocol Control" },
+  { 0x8287, "ETSI TETRA TNP1 Control Protocol" },
+  { 0x8289, "Multichannel Flow Treatment Protocol" },
+  { 0xc021, "Link Control Protocol" },
+  { 0xc023, "Password Authentication Protocol" },
+  { 0xc025, "Link Quality Report" },
+  { 0xc027, "Shiva Password Authentication Protocol" },
+  { 0xc029, "CallBack Control Protocol (CBCP)" },
+  { 0xc02b, "BACP Bandwidth Allocation Control Protocol" },
+  { 0xc02d, "BAP" },
+  { 0xc05b, "Vendor-Specific Authentication Protocol (VSAP)" },
+  { 0xc081, "Container Control Protocol" },
+  { 0xc223, "Challenge Handshake Authentication Protocol" },
+  { 0xc225, "RSA Authentication Protocol" },
+  { 0xc227, "Extensible Authentication Protocol" },
+  { 0xc229, "Mitsubishi Security Info Exch Ptcl (SIEP)" },
+  { 0xc26f, "Stampede Bridging Authorization Protocol" },
+  { 0xc281, "Proprietary Authentication Protocol" },
+  { 0xc283, "Proprietary Authentication Protocol" },
+  { 0xc481, "Proprietary Node ID Authentication Protocol" },
+  { 0, NULL },
+};
+
+/*
+ * protocol_name - find a name for a PPP protocol.
+ */
+const char * protocol_name(int proto) {
+  const struct protocol_list *lp;
+
+  for (lp = protocol_list; lp->proto != 0; ++lp) {
+    if (proto == lp->proto) {
+      return lp->name;
+    }
+  }
+  return NULL;
+}
+#endif /* PPP_PROTOCOLNAME */
+
+#if PPP_STATS_SUPPORT
+
+/* ---- Note on PPP Stats support ----
+ *
+ * The one willing link stats support should add the get_ppp_stats()
+ * to fetch statistics from lwIP.
+ */
+
+/*
+ * reset_link_stats - "reset" stats when link goes up.
+ */
+void reset_link_stats(int u) {
+  if (!get_ppp_stats(u, &old_link_stats)) {
+    return;
+  }
+  gettimeofday(&start_time, NULL);
+}
+
+/*
+ * update_link_stats - get stats at link termination.
+ */
+void update_link_stats(int u) {
+  struct timeval now;
+  char numbuf[32];
+
+  if (!get_ppp_stats(u, &link_stats) || gettimeofday(&now, NULL) < 0) {
+    return;
+  }
+  link_connect_time = now.tv_sec - start_time.tv_sec;
+  link_stats_valid = 1;
+
+  link_stats.bytes_in  -= old_link_stats.bytes_in;
+  link_stats.bytes_out -= old_link_stats.bytes_out;
+  link_stats.pkts_in   -= old_link_stats.pkts_in;
+  link_stats.pkts_out  -= old_link_stats.pkts_out;
+}
+
+void print_link_stats() {
+  /*
+   * Print connect time and statistics.
+   */
+  if (link_stats_valid) {
+    int t = (link_connect_time + 5) / 6;    /* 1/10ths of minutes */
+    info("Connect time %d.%d minutes.", t/10, t%10);
+    info("Sent %u bytes, received %u bytes.", link_stats.bytes_out, link_stats.bytes_in);
+    link_stats_valid = 0;
+  }
+}
+#endif /* PPP_STATS_SUPPORT */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppapi.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppapi.c
new file mode 100644
index 000000000..947f7ba8c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppapi.c
@@ -0,0 +1,427 @@
+/**
+ * @file
+ * Point To Point Protocol Sequential API module
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+
+#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/ppp/pppapi.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "netif/ppp/pppoe.h"
+#include "netif/ppp/pppol2tp.h"
+#include "netif/ppp/pppos.h"
+
+#if LWIP_MPU_COMPATIBLE
+LWIP_MEMPOOL_DECLARE(PPPAPI_MSG, MEMP_NUM_PPP_API_MSG, sizeof(struct pppapi_msg), "PPPAPI_MSG")
+#endif
+
+#define PPPAPI_VAR_REF(name)               API_VAR_REF(name)
+#define PPPAPI_VAR_DECLARE(name)           API_VAR_DECLARE(struct pppapi_msg, name)
+#define PPPAPI_VAR_ALLOC(name)             API_VAR_ALLOC_POOL(struct pppapi_msg, PPPAPI_MSG, name, ERR_MEM)
+#define PPPAPI_VAR_ALLOC_RETURN_NULL(name) API_VAR_ALLOC_POOL(struct pppapi_msg, PPPAPI_MSG, name, NULL)
+#define PPPAPI_VAR_FREE(name)              API_VAR_FREE_POOL(PPPAPI_MSG, name)
+
+/**
+ * Call ppp_set_default() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_set_default(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+  
+  ppp_set_default(msg->msg.ppp);
+  return ERR_OK;
+}
+
+/**
+ * Call ppp_set_default() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_set_default(ppp_pcb *pcb)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  err = tcpip_api_call(pppapi_do_ppp_set_default, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+
+
+#if PPP_NOTIFY_PHASE
+/**
+ * Call ppp_set_notify_phase_callback() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_set_notify_phase_callback(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+   struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  ppp_set_notify_phase_callback(msg->msg.ppp, msg->msg.msg.setnotifyphasecb.notify_phase_cb);
+  return ERR_OK;
+}
+
+/**
+ * Call ppp_set_notify_phase_callback() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  PPPAPI_VAR_REF(msg).msg.msg.setnotifyphasecb.notify_phase_cb = notify_phase_cb;
+  err = tcpip_api_call(pppapi_do_ppp_set_notify_phase_callback, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+#endif /* PPP_NOTIFY_PHASE */
+
+
+#if PPPOS_SUPPORT
+/**
+ * Call pppos_create() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_pppos_create(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  msg->msg.ppp = pppos_create(msg->msg.msg.serialcreate.pppif, msg->msg.msg.serialcreate.output_cb,
+    msg->msg.msg.serialcreate.link_status_cb, msg->msg.msg.serialcreate.ctx_cb);
+  return ERR_OK;
+}
+
+/**
+ * Call pppos_create() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+ppp_pcb*
+pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb,
+               ppp_link_status_cb_fn link_status_cb, void *ctx_cb)
+{
+  ppp_pcb* result;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC_RETURN_NULL(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = NULL;
+  PPPAPI_VAR_REF(msg).msg.msg.serialcreate.pppif = pppif;
+  PPPAPI_VAR_REF(msg).msg.msg.serialcreate.output_cb = output_cb;
+  PPPAPI_VAR_REF(msg).msg.msg.serialcreate.link_status_cb = link_status_cb;
+  PPPAPI_VAR_REF(msg).msg.msg.serialcreate.ctx_cb = ctx_cb;
+  tcpip_api_call(pppapi_do_pppos_create, &PPPAPI_VAR_REF(msg).call);
+  result = PPPAPI_VAR_REF(msg).msg.ppp;
+  PPPAPI_VAR_FREE(msg);
+  return result;
+}
+#endif /* PPPOS_SUPPORT */
+
+
+#if PPPOE_SUPPORT
+/**
+ * Call pppoe_create() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_pppoe_create(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  msg->msg.ppp = pppoe_create(msg->msg.msg.ethernetcreate.pppif, msg->msg.msg.ethernetcreate.ethif,
+    msg->msg.msg.ethernetcreate.service_name, msg->msg.msg.ethernetcreate.concentrator_name,
+    msg->msg.msg.ethernetcreate.link_status_cb, msg->msg.msg.ethernetcreate.ctx_cb);
+  return ERR_OK;
+}
+
+/**
+ * Call pppoe_create() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+ppp_pcb*
+pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name,
+                            const char *concentrator_name, ppp_link_status_cb_fn link_status_cb,
+                            void *ctx_cb)
+{
+  ppp_pcb* result;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC_RETURN_NULL(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = NULL;
+  PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.pppif = pppif;
+  PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.ethif = ethif;
+  PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.service_name = service_name;
+  PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.concentrator_name = concentrator_name;
+  PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.link_status_cb = link_status_cb;
+  PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.ctx_cb = ctx_cb;
+  tcpip_api_call(pppapi_do_pppoe_create, &PPPAPI_VAR_REF(msg).call);
+  result = PPPAPI_VAR_REF(msg).msg.ppp;
+  PPPAPI_VAR_FREE(msg);
+  return result;
+}
+#endif /* PPPOE_SUPPORT */
+
+
+#if PPPOL2TP_SUPPORT
+/**
+ * Call pppol2tp_create() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_pppol2tp_create(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  msg->msg.ppp = pppol2tp_create(msg->msg.msg.l2tpcreate.pppif,
+    msg->msg.msg.l2tpcreate.netif, API_EXPR_REF(msg->msg.msg.l2tpcreate.ipaddr), msg->msg.msg.l2tpcreate.port,
+#if PPPOL2TP_AUTH_SUPPORT
+    msg->msg.msg.l2tpcreate.secret,
+    msg->msg.msg.l2tpcreate.secret_len,
+#else /* PPPOL2TP_AUTH_SUPPORT */
+    NULL,
+    0,
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+    msg->msg.msg.l2tpcreate.link_status_cb, msg->msg.msg.l2tpcreate.ctx_cb);
+  return ERR_OK;
+}
+
+/**
+ * Call pppol2tp_create() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+ppp_pcb*
+pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port,
+                        const u8_t *secret, u8_t secret_len,
+                        ppp_link_status_cb_fn link_status_cb, void *ctx_cb)
+{
+  ppp_pcb* result;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC_RETURN_NULL(msg);
+#if !PPPOL2TP_AUTH_SUPPORT
+  LWIP_UNUSED_ARG(secret);
+  LWIP_UNUSED_ARG(secret_len);
+#endif /* !PPPOL2TP_AUTH_SUPPORT */
+
+  PPPAPI_VAR_REF(msg).msg.ppp = NULL;
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.pppif = pppif;
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.netif = netif;
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.ipaddr = PPPAPI_VAR_REF(ipaddr);
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.port = port;
+#if PPPOL2TP_AUTH_SUPPORT
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.secret = secret;
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.secret_len = secret_len;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.link_status_cb = link_status_cb;
+  PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.ctx_cb = ctx_cb;
+  tcpip_api_call(pppapi_do_pppol2tp_create, &PPPAPI_VAR_REF(msg).call);
+  result = PPPAPI_VAR_REF(msg).msg.ppp;
+  PPPAPI_VAR_FREE(msg);
+  return result;
+}
+#endif /* PPPOL2TP_SUPPORT */
+
+
+/**
+ * Call ppp_connect() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_connect(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  return ppp_connect(msg->msg.ppp, msg->msg.msg.connect.holdoff);
+}
+
+/**
+ * Call ppp_connect() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_connect(ppp_pcb *pcb, u16_t holdoff)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  PPPAPI_VAR_REF(msg).msg.msg.connect.holdoff = holdoff;
+  err = tcpip_api_call(pppapi_do_ppp_connect, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+
+
+#if PPP_SERVER
+/**
+ * Call ppp_listen() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_listen(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  return ppp_listen(msg->msg.ppp);
+}
+
+/**
+ * Call ppp_listen() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_listen(ppp_pcb *pcb)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  err = tcpip_api_call(pppapi_do_ppp_listen, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+#endif /* PPP_SERVER */
+
+
+/**
+ * Call ppp_close() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_close(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  return ppp_close(msg->msg.ppp, msg->msg.msg.close.nocarrier);
+}
+
+/**
+ * Call ppp_close() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_close(ppp_pcb *pcb, u8_t nocarrier)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  PPPAPI_VAR_REF(msg).msg.msg.close.nocarrier = nocarrier;
+  err = tcpip_api_call(pppapi_do_ppp_close, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+
+
+/**
+ * Call ppp_free() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_free(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  return ppp_free(msg->msg.ppp);
+}
+
+/**
+ * Call ppp_free() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_free(ppp_pcb *pcb)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  err = tcpip_api_call(pppapi_do_ppp_free, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+
+
+/**
+ * Call ppp_ioctl() inside the tcpip_thread context.
+ */
+static err_t
+pppapi_do_ppp_ioctl(struct tcpip_api_call_data *m)
+{
+  /* cast through void* to silence alignment warnings. 
+   * We know it works because the structs have been instantiated as struct pppapi_msg */
+  struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m;
+
+  return ppp_ioctl(msg->msg.ppp, msg->msg.msg.ioctl.cmd, msg->msg.msg.ioctl.arg);
+}
+
+/**
+ * Call ppp_ioctl() in a thread-safe way by running that function inside the
+ * tcpip_thread context.
+ */
+err_t
+pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg)
+{
+  err_t err;
+  PPPAPI_VAR_DECLARE(msg);
+  PPPAPI_VAR_ALLOC(msg);
+
+  PPPAPI_VAR_REF(msg).msg.ppp = pcb;
+  PPPAPI_VAR_REF(msg).msg.msg.ioctl.cmd = cmd;
+  PPPAPI_VAR_REF(msg).msg.msg.ioctl.arg = arg;
+  err = tcpip_api_call(pppapi_do_ppp_ioctl, &PPPAPI_VAR_REF(msg).call);
+  PPPAPI_VAR_FREE(msg);
+  return err;
+}
+
+#endif /* LWIP_PPP_API */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppcrypt.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppcrypt.c
new file mode 100644
index 000000000..82d78c13a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppcrypt.c
@@ -0,0 +1,66 @@
+/*
+ * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1
+ *
+ * Extracted from chap_ms.c by James Carlson.
+ *
+ * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && MSCHAP_SUPPORT /* don't build if not necessary */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/pppcrypt.h"
+
+
+static u_char pppcrypt_get_7bits(u_char *input, int startBit) {
+	unsigned int word;
+
+	word  = (unsigned)input[startBit / 8] << 8;
+	word |= (unsigned)input[startBit / 8 + 1];
+
+	word >>= 15 - (startBit % 8 + 7);
+
+	return word & 0xFE;
+}
+
+/* IN  56 bit DES key missing parity bits
+ * OUT 64 bit DES key with parity bits added
+ */
+void pppcrypt_56_to_64_bit_key(u_char *key, u_char * des_key) {
+	des_key[0] = pppcrypt_get_7bits(key,  0);
+	des_key[1] = pppcrypt_get_7bits(key,  7);
+	des_key[2] = pppcrypt_get_7bits(key, 14);
+	des_key[3] = pppcrypt_get_7bits(key, 21);
+	des_key[4] = pppcrypt_get_7bits(key, 28);
+	des_key[5] = pppcrypt_get_7bits(key, 35);
+	des_key[6] = pppcrypt_get_7bits(key, 42);
+	des_key[7] = pppcrypt_get_7bits(key, 49);
+}
+
+#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppoe.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppoe.c
new file mode 100644
index 000000000..8ed2d638f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppoe.c
@@ -0,0 +1,1201 @@
+/*****************************************************************************
+* pppoe.c - PPP Over Ethernet implementation for lwIP.
+*
+* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 06-01-01 Marc Boucher <marc@mbsi.ca>
+*   Ported to lwIP.
+*****************************************************************************/
+
+
+
+/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Martin Husemann <martin@NetBSD.org>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <string.h>
+#include <stdio.h>
+#endif /* UNUSED */
+
+#include "lwip/timeouts.h"
+#include "lwip/memp.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+#include "netif/ethernet.h"
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/lcp.h"
+#include "netif/ppp/ipcp.h"
+#include "netif/ppp/pppoe.h"
+
+/* Memory pool */
+LWIP_MEMPOOL_DECLARE(PPPOE_IF, MEMP_NUM_PPPOE_INTERFACES, sizeof(struct pppoe_softc), "PPPOE_IF")
+
+/* Add a 16 bit unsigned value to a buffer pointed to by PTR */
+#define PPPOE_ADD_16(PTR, VAL) \
+    *(PTR)++ = (u8_t)((VAL) / 256);    \
+    *(PTR)++ = (u8_t)((VAL) % 256)
+
+/* Add a complete PPPoE header to the buffer pointed to by PTR */
+#define PPPOE_ADD_HEADER(PTR, CODE, SESS, LEN)  \
+    *(PTR)++ = PPPOE_VERTYPE;  \
+    *(PTR)++ = (CODE);         \
+    PPPOE_ADD_16(PTR, SESS);   \
+    PPPOE_ADD_16(PTR, LEN)
+
+#define PPPOE_DISC_TIMEOUT (5*1000)  /* base for quick timeout calculation */
+#define PPPOE_SLOW_RETRY   (60*1000) /* persistent retry interval */
+#define PPPOE_DISC_MAXPADI  4        /* retry PADI four times (quickly) */
+#define PPPOE_DISC_MAXPADR  2        /* retry PADR twice */
+
+#ifdef PPPOE_SERVER
+#error "PPPOE_SERVER is not yet supported under lwIP!"
+/* from if_spppsubr.c */
+#define IFF_PASSIVE IFF_LINK0 /* wait passively for connection */
+#endif
+
+#define PPPOE_ERRORSTRING_LEN     64
+
+
+/* callbacks called from PPP core */
+static err_t pppoe_write(ppp_pcb *ppp, void *ctx, struct pbuf *p);
+static err_t pppoe_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol);
+static void pppoe_connect(ppp_pcb *ppp, void *ctx);
+static void pppoe_disconnect(ppp_pcb *ppp, void *ctx);
+static err_t pppoe_destroy(ppp_pcb *ppp, void *ctx);
+
+/* management routines */
+static void pppoe_abort_connect(struct pppoe_softc *);
+#if 0 /* UNUSED */
+static void pppoe_clear_softc(struct pppoe_softc *, const char *);
+#endif /* UNUSED */
+
+/* internal timeout handling */
+static void pppoe_timeout(void *);
+
+/* sending actual protocol controll packets */
+static err_t pppoe_send_padi(struct pppoe_softc *);
+static err_t pppoe_send_padr(struct pppoe_softc *);
+#ifdef PPPOE_SERVER
+static err_t pppoe_send_pado(struct pppoe_softc *);
+static err_t pppoe_send_pads(struct pppoe_softc *);
+#endif
+static err_t pppoe_send_padt(struct netif *, u_int, const u8_t *);
+
+/* internal helper functions */
+static err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb);
+static struct pppoe_softc* pppoe_find_softc_by_session(u_int session, struct netif *rcvif);
+static struct pppoe_softc* pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif);
+
+/** linked list of created pppoe interfaces */
+static struct pppoe_softc *pppoe_softc_list;
+
+/* Callbacks structure for PPP core */
+static const struct link_callbacks pppoe_callbacks = {
+  pppoe_connect,
+#if PPP_SERVER
+  NULL,
+#endif /* PPP_SERVER */
+  pppoe_disconnect,
+  pppoe_destroy,
+  pppoe_write,
+  pppoe_netif_output,
+  NULL,
+  NULL
+};
+
+/*
+ * Create a new PPP Over Ethernet (PPPoE) connection.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+ppp_pcb *pppoe_create(struct netif *pppif,
+       struct netif *ethif,
+       const char *service_name, const char *concentrator_name,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb)
+{
+  ppp_pcb *ppp;
+  struct pppoe_softc *sc;
+  LWIP_UNUSED_ARG(service_name);
+  LWIP_UNUSED_ARG(concentrator_name);
+  LWIP_ASSERT_CORE_LOCKED();
+
+  sc = (struct pppoe_softc *)LWIP_MEMPOOL_ALLOC(PPPOE_IF);
+  if (sc == NULL) {
+    return NULL;
+  }
+
+  ppp = ppp_new(pppif, &pppoe_callbacks, sc, link_status_cb, ctx_cb);
+  if (ppp == NULL) {
+    LWIP_MEMPOOL_FREE(PPPOE_IF, sc);
+    return NULL;
+  }
+
+  memset(sc, 0, sizeof(struct pppoe_softc));
+  sc->pcb = ppp;
+  sc->sc_ethif = ethif;
+  /* put the new interface at the head of the list */
+  sc->next = pppoe_softc_list;
+  pppoe_softc_list = sc;
+  return ppp;
+}
+
+/* Called by PPP core */
+static err_t pppoe_write(ppp_pcb *ppp, void *ctx, struct pbuf *p) {
+  struct pppoe_softc *sc = (struct pppoe_softc *)ctx;
+  struct pbuf *ph; /* Ethernet + PPPoE header */
+  err_t ret;
+#if MIB2_STATS
+  u16_t tot_len;
+#else /* MIB2_STATS */
+  LWIP_UNUSED_ARG(ppp);
+#endif /* MIB2_STATS */
+
+  /* skip address & flags */
+  pbuf_remove_header(p, 2);
+
+  ph = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN), PBUF_RAM);
+  if(!ph) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    pbuf_free(p);
+    return ERR_MEM;
+  }
+
+  pbuf_remove_header(ph, PPPOE_HEADERLEN); /* hide PPPoE header */
+  pbuf_cat(ph, p);
+#if MIB2_STATS
+  tot_len = ph->tot_len;
+#endif /* MIB2_STATS */
+
+  ret = pppoe_xmit(sc, ph);
+  if (ret != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return ret;
+  }
+
+  MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, (u16_t)tot_len);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts);
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+
+/* Called by PPP core */
+static err_t pppoe_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol) {
+  struct pppoe_softc *sc = (struct pppoe_softc *)ctx;
+  struct pbuf *pb;
+  u8_t *pl;
+  err_t err;
+#if MIB2_STATS
+  u16_t tot_len;
+#else /* MIB2_STATS */
+  LWIP_UNUSED_ARG(ppp);
+#endif /* MIB2_STATS */
+
+  /* @todo: try to use pbuf_header() here! */
+  pb = pbuf_alloc(PBUF_LINK, PPPOE_HEADERLEN + sizeof(protocol), PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return ERR_MEM;
+  }
+
+  pbuf_remove_header(pb, PPPOE_HEADERLEN);
+
+  pl = (u8_t*)pb->payload;
+  PUTSHORT(protocol, pl);
+
+  pbuf_chain(pb, p);
+#if MIB2_STATS
+  tot_len = pb->tot_len;
+#endif /* MIB2_STATS */
+
+  if( (err = pppoe_xmit(sc, pb)) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return err;
+  }
+
+  MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, tot_len);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts);
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+
+static err_t
+pppoe_destroy(ppp_pcb *ppp, void *ctx)
+{
+  struct pppoe_softc *sc = (struct pppoe_softc *)ctx;
+  struct pppoe_softc **copp, *freep;
+  LWIP_UNUSED_ARG(ppp);
+
+  sys_untimeout(pppoe_timeout, sc);
+
+  /* remove interface from list */
+  for (copp = &pppoe_softc_list; (freep = *copp); copp = &freep->next) {
+    if (freep == sc) {
+       *copp = freep->next;
+       break;
+    }
+  }
+
+#ifdef PPPOE_TODO
+  if (sc->sc_concentrator_name) {
+    mem_free(sc->sc_concentrator_name);
+  }
+  if (sc->sc_service_name) {
+    mem_free(sc->sc_service_name);
+  }
+#endif /* PPPOE_TODO */
+  LWIP_MEMPOOL_FREE(PPPOE_IF, sc);
+
+  return ERR_OK;
+}
+
+/*
+ * Find the interface handling the specified session.
+ * Note: O(number of sessions open), this is a client-side only, mean
+ * and lean implementation, so number of open sessions typically should
+ * be 1.
+ */
+static struct pppoe_softc* pppoe_find_softc_by_session(u_int session, struct netif *rcvif) {
+  struct pppoe_softc *sc;
+
+  for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) {
+    if (sc->sc_state == PPPOE_STATE_SESSION
+        && sc->sc_session == session
+         && sc->sc_ethif == rcvif) {
+           return sc;
+      }
+  }
+  return NULL;
+}
+
+/* Check host unique token passed and return appropriate softc pointer,
+ * or NULL if token is bogus. */
+static struct pppoe_softc* pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif) {
+  struct pppoe_softc *sc, *t;
+
+  if (len != sizeof sc) {
+    return NULL;
+  }
+  MEMCPY(&t, token, len);
+
+  for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) {
+    if (sc == t) {
+      break;
+    }
+  }
+
+  if (sc == NULL) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: alien host unique tag, no session found\n"));
+    return NULL;
+  }
+
+  /* should be safe to access *sc now */
+  if (sc->sc_state < PPPOE_STATE_PADI_SENT || sc->sc_state >= PPPOE_STATE_SESSION) {
+    PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": host unique tag found, but it belongs to a connection in state %d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_state));
+    return NULL;
+  }
+  if (sc->sc_ethif != rcvif) {
+    PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": wrong interface, not accepting host unique\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    return NULL;
+  }
+  return sc;
+}
+
+/* analyze and handle a single received packet while not in session state */
+void
+pppoe_disc_input(struct netif *netif, struct pbuf *pb)
+{
+  u16_t tag, len, off;
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+#if PPP_DEBUG
+  const char *err_msg = NULL;
+#endif /* PPP_DEBUG */
+  u8_t *ac_cookie;
+  u16_t ac_cookie_len;
+#ifdef PPPOE_SERVER
+  u8_t *hunique;
+  size_t hunique_len;
+#endif
+  struct pppoehdr *ph;
+  struct pppoetag pt;
+  int err;
+  struct eth_hdr *ethhdr;
+
+  /* don't do anything if there is not a single PPPoE instance */
+  if (pppoe_softc_list == NULL) {
+    pbuf_free(pb);
+    return;
+  }
+
+  pb = pbuf_coalesce(pb, PBUF_RAW);
+
+  ethhdr = (struct eth_hdr *)pb->payload;
+
+  ac_cookie = NULL;
+  ac_cookie_len = 0;
+#ifdef PPPOE_SERVER
+  hunique = NULL;
+  hunique_len = 0;
+#endif
+  session = 0;
+  off = sizeof(struct eth_hdr) + sizeof(struct pppoehdr);
+  if (pb->len < off) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: packet too short: %d\n", pb->len));
+    goto done;
+  }
+
+  ph = (struct pppoehdr *) (ethhdr + 1);
+  if (ph->vertype != PPPOE_VERTYPE) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: unknown version/type packet: 0x%x\n", ph->vertype));
+    goto done;
+  }
+  session = lwip_ntohs(ph->session);
+  plen = lwip_ntohs(ph->plen);
+
+  if (plen > (pb->len - off)) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: packet content does not fit: data available = %d, packet size = %u\n",
+        pb->len - off, plen));
+    goto done;
+  }
+  if(pb->tot_len == pb->len) {
+    u16_t framelen = off + plen;
+    if (framelen < pb->len) {
+      /* ignore trailing garbage */
+      pb->tot_len = pb->len = framelen;
+    }
+  }
+  tag = 0;
+  len = 0;
+  sc = NULL;
+  while (off + sizeof(pt) <= pb->len) {
+    MEMCPY(&pt, (u8_t*)pb->payload + off, sizeof(pt));
+    tag = lwip_ntohs(pt.tag);
+    len = lwip_ntohs(pt.len);
+    if (off + sizeof(pt) + len > pb->len) {
+      PPPDEBUG(LOG_DEBUG, ("pppoe: tag 0x%x len 0x%x is too long\n", tag, len));
+      goto done;
+    }
+    switch (tag) {
+      case PPPOE_TAG_EOL:
+        goto breakbreak;
+      case PPPOE_TAG_SNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_ACNAME:
+        break;  /* ignored */
+      case PPPOE_TAG_HUNIQUE:
+        if (sc != NULL) {
+          break;
+        }
+#ifdef PPPOE_SERVER
+        hunique = (u8_t*)pb->payload + off + sizeof(pt);
+        hunique_len = len;
+#endif
+        sc = pppoe_find_softc_by_hunique((u8_t*)pb->payload + off + sizeof(pt), len, netif);
+        break;
+      case PPPOE_TAG_ACCOOKIE:
+        if (ac_cookie == NULL) {
+          if (len > PPPOE_MAX_AC_COOKIE_LEN) {
+            PPPDEBUG(LOG_DEBUG, ("pppoe: AC cookie is too long: len = %d, max = %d\n", len, PPPOE_MAX_AC_COOKIE_LEN));
+            goto done;
+          }
+          ac_cookie = (u8_t*)pb->payload + off + sizeof(pt);
+          ac_cookie_len = len;
+        }
+        break;
+#if PPP_DEBUG
+      case PPPOE_TAG_SNAME_ERR:
+        err_msg = "SERVICE NAME ERROR";
+        break;
+      case PPPOE_TAG_ACSYS_ERR:
+        err_msg = "AC SYSTEM ERROR";
+        break;
+      case PPPOE_TAG_GENERIC_ERR:
+        err_msg = "GENERIC ERROR";
+        break;
+#endif /* PPP_DEBUG */
+      default:
+        break;
+    }
+#if PPP_DEBUG
+    if (err_msg != NULL) {
+      char error_tmp[PPPOE_ERRORSTRING_LEN];
+      u16_t error_len = LWIP_MIN(len, sizeof(error_tmp)-1);
+      strncpy(error_tmp, (char*)pb->payload + off + sizeof(pt), error_len);
+      error_tmp[error_len] = '\0';
+      if (sc) {
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": %s: %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err_msg, error_tmp));
+      } else {
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %s: %s\n", err_msg, error_tmp));
+      }
+    }
+#endif /* PPP_DEBUG */
+    off += sizeof(pt) + len;
+  }
+
+breakbreak:;
+  switch (ph->code) {
+    case PPPOE_CODE_PADI:
+#ifdef PPPOE_SERVER
+      /*
+       * got service name, concentrator name, and/or host unique.
+       * ignore if we have no interfaces with IFF_PASSIVE|IFF_UP.
+       */
+      if (LIST_EMPTY(&pppoe_softc_list)) {
+        goto done;
+      }
+      LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_UP)) {
+          continue;
+        }
+        if (!(sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+          continue;
+        }
+        if (sc->sc_state == PPPOE_STATE_INITIAL) {
+          break;
+        }
+      }
+      if (sc == NULL) {
+        /* PPPDEBUG(LOG_DEBUG, ("pppoe: free passive interface is not found\n")); */
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      MEMCPY(&sc->sc_dest, eh->ether_shost, sizeof sc->sc_dest);
+      sc->sc_state = PPPOE_STATE_PADO_SENT;
+      pppoe_send_pado(sc);
+      break;
+#endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADR:
+#ifdef PPPOE_SERVER
+      /*
+       * get sc from ac_cookie if IFF_PASSIVE
+       */
+      if (ac_cookie == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        PPPDEBUG(LOG_DEBUG, ("pppoe: received PADR but not includes ac_cookie\n"));
+        goto done;
+      }
+      sc = pppoe_find_softc_by_hunique(ac_cookie, ac_cookie_len, netif);
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (!LIST_EMPTY(&pppoe_softc_list)) {
+          PPPDEBUG(LOG_DEBUG, ("pppoe: received PADR but could not find request for it\n"));
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADO_SENT) {
+        PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": received unexpected PADR\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+        goto done;
+      }
+      if (hunique) {
+        if (sc->sc_hunique) {
+          mem_free(sc->sc_hunique);
+        }
+        sc->sc_hunique = mem_malloc(hunique_len);
+        if (sc->sc_hunique == NULL) {
+          goto done;
+        }
+        sc->sc_hunique_len = hunique_len;
+        MEMCPY(sc->sc_hunique, hunique, hunique_len);
+      }
+      pppoe_send_pads(sc);
+      sc->sc_state = PPPOE_STATE_SESSION;
+      ppp_start(sc->pcb); /* notify upper layers */
+      break;
+#else
+      /* ignore, we are no access concentrator */
+      goto done;
+#endif /* PPPOE_SERVER */
+    case PPPOE_CODE_PADO:
+      if (sc == NULL) {
+        /* be quiet if there is not a single pppoe instance */
+        if (pppoe_softc_list != NULL) {
+          PPPDEBUG(LOG_DEBUG, ("pppoe: received PADO but could not find request for it\n"));
+        }
+        goto done;
+      }
+      if (sc->sc_state != PPPOE_STATE_PADI_SENT) {
+        PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": received unexpected PADO\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+        goto done;
+      }
+      if (ac_cookie) {
+        sc->sc_ac_cookie_len = ac_cookie_len;
+        MEMCPY(sc->sc_ac_cookie, ac_cookie, ac_cookie_len);
+      }
+      MEMCPY(&sc->sc_dest, ethhdr->src.addr, sizeof(sc->sc_dest.addr));
+      sys_untimeout(pppoe_timeout, sc);
+      sc->sc_padr_retried = 0;
+      sc->sc_state = PPPOE_STATE_PADR_SENT;
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    case PPPOE_CODE_PADS:
+      if (sc == NULL) {
+        goto done;
+      }
+      sc->sc_session = session;
+      sys_untimeout(pppoe_timeout, sc);
+      PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x connected\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, session));
+      sc->sc_state = PPPOE_STATE_SESSION;
+      ppp_start(sc->pcb); /* notify upper layers */
+      break;
+    case PPPOE_CODE_PADT:
+      /* Don't disconnect here, we let the LCP Echo/Reply find the fact
+       * that PPP session is down. Asking the PPP stack to end the session
+       * require strict checking about the PPP phase to prevent endless
+       * disconnection loops.
+       */
+#if 0 /* UNUSED */
+      if (sc == NULL) { /* PADT frames are rarely sent with a hunique tag, this is actually almost always true */
+        goto done;
+      }
+      pppoe_clear_softc(sc, "received PADT");
+#endif /* UNUSED */
+      break;
+    default:
+      if(sc) {
+        PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": unknown code (0x%"X16_F") session = 0x%"X16_F"\n",
+            sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+            (u16_t)ph->code, session));
+      } else {
+        PPPDEBUG(LOG_DEBUG, ("pppoe: unknown code (0x%"X16_F") session = 0x%"X16_F"\n", (u16_t)ph->code, session));
+      }
+      break;
+  }
+
+done:
+  pbuf_free(pb);
+  return;
+}
+
+void
+pppoe_data_input(struct netif *netif, struct pbuf *pb)
+{
+  u16_t session, plen;
+  struct pppoe_softc *sc;
+  struct pppoehdr *ph;
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  u8_t shost[ETHER_ADDR_LEN];
+#endif
+
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+  MEMCPY(shost, ((struct eth_hdr *)pb->payload)->src.addr, sizeof(shost));
+#endif
+  if (pbuf_remove_header(pb, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_remove_header failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  if (pb->len < sizeof(*ph)) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe_data_input: could not get PPPoE header\n"));
+    goto drop;
+  }
+  ph = (struct pppoehdr *)pb->payload;
+
+  if (ph->vertype != PPPOE_VERTYPE) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe (data): unknown version/type packet: 0x%x\n", ph->vertype));
+    goto drop;
+  }
+  if (ph->code != 0) {
+    goto drop;
+  }
+
+  session = lwip_ntohs(ph->session);
+  sc = pppoe_find_softc_by_session(session, netif);
+  if (sc == NULL) {
+#ifdef PPPOE_TERM_UNKNOWN_SESSIONS
+    PPPDEBUG(LOG_DEBUG, ("pppoe: input for unknown session 0x%x, sending PADT\n", session));
+    pppoe_send_padt(netif, session, shost);
+#endif
+    goto drop;
+  }
+
+  plen = lwip_ntohs(ph->plen);
+
+  if (pbuf_remove_header(pb, PPPOE_HEADERLEN) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_remove_header PPPOE_HEADERLEN failed\n"));
+    LINK_STATS_INC(link.lenerr);
+    goto drop;
+  } 
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe_data_input: %c%c%"U16_F": pkthdr.len=%d, pppoe.len=%d\n",
+        sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num,
+        pb->len, plen));
+
+  if (pb->tot_len < plen) {
+    goto drop;
+  }
+
+  /* Dispatch the packet thereby consuming it. */
+  ppp_input(sc->pcb, pb);
+  return;
+
+drop:
+  pbuf_free(pb);
+}
+
+static err_t
+pppoe_output(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  struct eth_hdr *ethhdr;
+  u16_t etype;
+  err_t res;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_add_header(pb, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe: %c%c%"U16_F": pppoe_output: could not allocate room for Ethernet header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  }
+  ethhdr = (struct eth_hdr *)pb->payload;
+  etype = sc->sc_state == PPPOE_STATE_SESSION ? ETHTYPE_PPPOE : ETHTYPE_PPPOEDISC;
+  ethhdr->type = lwip_htons(etype);
+  MEMCPY(&ethhdr->dest.addr, &sc->sc_dest.addr, sizeof(ethhdr->dest.addr));
+  MEMCPY(&ethhdr->src.addr, &sc->sc_ethif->hwaddr, sizeof(ethhdr->src.addr));
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F" (%x) state=%d, session=0x%x output -> %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F", len=%d\n",
+      sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, etype,
+      sc->sc_state, sc->sc_session,
+      sc->sc_dest.addr[0], sc->sc_dest.addr[1], sc->sc_dest.addr[2], sc->sc_dest.addr[3], sc->sc_dest.addr[4], sc->sc_dest.addr[5],
+      pb->tot_len));
+
+  res = sc->sc_ethif->linkoutput(sc->sc_ethif, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+static err_t
+pppoe_send_padi(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  int len;
+#ifdef PPPOE_TODO
+  int l1 = 0, l2 = 0; /* XXX: gcc */
+#endif /* PPPOE_TODO */
+
+  /* calculate length of frame (excluding ethernet header + pppoe header) */
+  len = 2 + 2 + 2 + 2 + sizeof sc;  /* service name tag is required, host unique is send too */
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {
+    l1 = (int)strlen(sc->sc_service_name);
+    len += l1;
+  }
+  if (sc->sc_concentrator_name != NULL) {
+    l2 = (int)strlen(sc->sc_concentrator_name);
+    len += 2 + 2 + l2;
+  }
+#endif /* PPPOE_TODO */
+  LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff",
+    sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff);
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADI, 0, (u16_t)len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else
+#endif /* PPPOE_TODO */
+  {
+    PPPOE_ADD_16(p, 0);
+  }
+#ifdef PPPOE_TODO
+  if (sc->sc_concentrator_name != NULL) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACNAME);
+    PPPOE_ADD_16(p, l2);
+    MEMCPY(p, sc->sc_concentrator_name, l2);
+    p += l2;
+  }
+#endif /* PPPOE_TODO */
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  /* send pkt */
+  return pppoe_output(sc, pb);
+}
+
+static void
+pppoe_timeout(void *arg)
+{
+  u32_t retry_wait;
+  int err;
+  struct pppoe_softc *sc = (struct pppoe_softc*)arg;
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": timeout\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+
+  switch (sc->sc_state) {
+    case PPPOE_STATE_PADI_SENT:
+      /*
+       * We have two basic ways of retrying:
+       *  - Quick retry mode: try a few times in short sequence
+       *  - Slow retry mode: we already had a connection successfully
+       *    established and will try infinitely (without user
+       *    intervention)
+       * We only enter slow retry mode if IFF_LINK1 (aka autodial)
+       * is not set.
+       */
+      if (sc->sc_padi_retried < 0xff) {
+        sc->sc_padi_retried++;
+      }
+      if (!sc->pcb->settings.persist && sc->sc_padi_retried >= PPPOE_DISC_MAXPADI) {
+#if 0
+        if ((sc->sc_sppp.pp_if.if_flags & IFF_LINK1) == 0) {
+          /* slow retry mode */
+          retry_wait = PPPOE_SLOW_RETRY;
+        } else
+#endif
+        {
+          pppoe_abort_connect(sc);
+          return;
+        }
+      }
+      /* initialize for quick retry mode */
+      retry_wait = LWIP_MIN(PPPOE_DISC_TIMEOUT * sc->sc_padi_retried, PPPOE_SLOW_RETRY);
+      if ((err = pppoe_send_padi(sc)) != 0) {
+        sc->sc_padi_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to transmit PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_timeout(retry_wait, pppoe_timeout, sc);
+      break;
+
+    case PPPOE_STATE_PADR_SENT:
+      sc->sc_padr_retried++;
+      if (sc->sc_padr_retried >= PPPOE_DISC_MAXPADR) {
+        MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+        sc->sc_state = PPPOE_STATE_PADI_SENT;
+        sc->sc_padr_retried = 0;
+        if ((err = pppoe_send_padi(sc)) != 0) {
+          PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+          LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+        }
+        sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried), pppoe_timeout, sc);
+        return;
+      }
+      if ((err = pppoe_send_padr(sc)) != 0) {
+        sc->sc_padr_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc);
+      break;
+    default:
+      return;  /* all done, work in peace */
+  }
+}
+
+/* Start a connection (i.e. initiate discovery phase) */
+static void
+pppoe_connect(ppp_pcb *ppp, void *ctx)
+{
+  err_t err;
+  struct pppoe_softc *sc = (struct pppoe_softc *)ctx;
+  lcp_options *lcp_wo;
+  lcp_options *lcp_ao;
+#if PPP_IPV4_SUPPORT && VJ_SUPPORT
+  ipcp_options *ipcp_wo;
+  ipcp_options *ipcp_ao;
+#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */
+
+  sc->sc_session = 0;
+  sc->sc_ac_cookie_len = 0;
+  sc->sc_padi_retried = 0;
+  sc->sc_padr_retried = 0;
+  /* changed to real address later */
+  MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest));
+#ifdef PPPOE_SERVER
+  /* wait PADI if IFF_PASSIVE */
+  if ((sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) {
+    return 0;
+  }
+#endif
+
+  lcp_wo = &ppp->lcp_wantoptions;
+  lcp_wo->mru = sc->sc_ethif->mtu-PPPOE_HEADERLEN-2; /* two byte PPP protocol discriminator, then IP data */
+  lcp_wo->neg_asyncmap = 0;
+  lcp_wo->neg_pcompression = 0;
+  lcp_wo->neg_accompression = 0;
+  lcp_wo->passive = 0;
+  lcp_wo->silent = 0;
+
+  lcp_ao = &ppp->lcp_allowoptions;
+  lcp_ao->mru = sc->sc_ethif->mtu-PPPOE_HEADERLEN-2; /* two byte PPP protocol discriminator, then IP data */
+  lcp_ao->neg_asyncmap = 0;
+  lcp_ao->neg_pcompression = 0;
+  lcp_ao->neg_accompression = 0;
+
+#if PPP_IPV4_SUPPORT && VJ_SUPPORT
+  ipcp_wo = &ppp->ipcp_wantoptions;
+  ipcp_wo->neg_vj = 0;
+  ipcp_wo->old_vj = 0;
+
+  ipcp_ao = &ppp->ipcp_allowoptions;
+  ipcp_ao->neg_vj = 0;
+  ipcp_ao->old_vj = 0;
+#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */
+
+  /* save state, in case we fail to send PADI */
+  sc->sc_state = PPPOE_STATE_PADI_SENT;
+  if ((err = pppoe_send_padi(sc)) != 0) {
+    PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err));
+  }
+  sys_timeout(PPPOE_DISC_TIMEOUT, pppoe_timeout, sc);
+}
+
+/* disconnect */
+static void
+pppoe_disconnect(ppp_pcb *ppp, void *ctx)
+{
+  struct pppoe_softc *sc = (struct pppoe_softc *)ctx;
+
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": disconnecting\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+  if (sc->sc_state == PPPOE_STATE_SESSION) {
+    pppoe_send_padt(sc->sc_ethif, sc->sc_session, (const u8_t *)&sc->sc_dest);
+  }
+
+  /* stop any timer, disconnect can be called while initiating is in progress */
+  sys_untimeout(pppoe_timeout, sc);
+  sc->sc_state = PPPOE_STATE_INITIAL;
+#ifdef PPPOE_SERVER
+  if (sc->sc_hunique) {
+    mem_free(sc->sc_hunique);
+    sc->sc_hunique = NULL; /* probably not necessary, if state is initial we shouldn't have to access hunique anyway  */
+  }
+  sc->sc_hunique_len = 0; /* probably not necessary, if state is initial we shouldn't have to access hunique anyway  */
+#endif
+  ppp_link_end(ppp); /* notify upper layers */
+  return;
+}
+
+/* Connection attempt aborted */
+static void
+pppoe_abort_connect(struct pppoe_softc *sc)
+{
+  PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": could not establish connection\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+  sc->sc_state = PPPOE_STATE_INITIAL;
+  ppp_link_failed(sc->pcb); /* notify upper layers */
+}
+
+/* Send a PADR packet */
+static err_t
+pppoe_send_padr(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len;
+#ifdef PPPOE_TODO
+  size_t l1 = 0; /* XXX: gcc */
+#endif /* PPPOE_TODO */
+
+  len = 2 + 2 + 2 + 2 + sizeof(sc);    /* service name, host unique */
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+#endif /* PPPOE_TODO */
+  if (sc->sc_ac_cookie_len > 0) {
+    len += 2 + 2 + sc->sc_ac_cookie_len;  /* AC cookie */
+  }
+  LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff",
+    sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff);
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+  p = (u8_t*)pb->payload;
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADR, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+#ifdef PPPOE_TODO
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else
+#endif /* PPPOE_TODO */
+  {
+    PPPOE_ADD_16(p, 0);
+  }
+  if (sc->sc_ac_cookie_len > 0) {
+    PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+    PPPOE_ADD_16(p, sc->sc_ac_cookie_len);
+    MEMCPY(p, sc->sc_ac_cookie, sc->sc_ac_cookie_len);
+    p += sc->sc_ac_cookie_len;
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof sc);
+
+  return pppoe_output(sc, pb);
+}
+
+/* send a PADT packet */
+static err_t
+pppoe_send_padt(struct netif *outgoing_if, u_int session, const u8_t *dest)
+{
+  struct pbuf *pb;
+  struct eth_hdr *ethhdr;
+  err_t res;
+  u8_t *p;
+
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  if (pbuf_add_header(pb, sizeof(struct eth_hdr))) {
+    PPPDEBUG(LOG_ERR, ("pppoe: pppoe_send_padt: could not allocate room for PPPoE header\n"));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  }
+  ethhdr = (struct eth_hdr *)pb->payload;
+  ethhdr->type = PP_HTONS(ETHTYPE_PPPOEDISC);
+  MEMCPY(&ethhdr->dest.addr, dest, sizeof(ethhdr->dest.addr));
+  MEMCPY(&ethhdr->src.addr, &outgoing_if->hwaddr, sizeof(ethhdr->src.addr));
+
+  p = (u8_t*)(ethhdr + 1);
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADT, session, 0);
+
+  res = outgoing_if->linkoutput(outgoing_if, pb);
+
+  pbuf_free(pb);
+
+  return res;
+}
+
+#ifdef PPPOE_SERVER
+static err_t
+pppoe_send_pado(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len;
+
+  /* calc length */
+  len = 0;
+  /* include ac_cookie */
+  len += 2 + 2 + sizeof(sc);
+  /* include hunique */
+  len += 2 + 2 + sc->sc_hunique_len;
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+  p = (u8_t*)pb->payload;
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADO, 0, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE);
+  PPPOE_ADD_16(p, sizeof(sc));
+  MEMCPY(p, &sc, sizeof(sc));
+  p += sizeof(sc);
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+
+static err_t
+pppoe_send_pads(struct pppoe_softc *sc)
+{
+  struct pbuf *pb;
+  u8_t *p;
+  size_t len, l1 = 0;  /* XXX: gcc */
+
+  sc->sc_session = mono_time.tv_sec % 0xff + 1;
+  /* calc length */
+  len = 0;
+  /* include hunique */
+  len += 2 + 2 + 2 + 2 + sc->sc_hunique_len;  /* service name, host unique*/
+  if (sc->sc_service_name != NULL) {    /* service name tag maybe empty */
+    l1 = strlen(sc->sc_service_name);
+    len += l1;
+  }
+  pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM);
+  if (!pb) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+  p = (u8_t*)pb->payload;
+  PPPOE_ADD_HEADER(p, PPPOE_CODE_PADS, sc->sc_session, len);
+  PPPOE_ADD_16(p, PPPOE_TAG_SNAME);
+  if (sc->sc_service_name != NULL) {
+    PPPOE_ADD_16(p, l1);
+    MEMCPY(p, sc->sc_service_name, l1);
+    p += l1;
+  } else {
+    PPPOE_ADD_16(p, 0);
+  }
+  PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE);
+  PPPOE_ADD_16(p, sc->sc_hunique_len);
+  MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len);
+  return pppoe_output(sc, pb);
+}
+#endif
+
+static err_t
+pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb)
+{
+  u8_t *p;
+  size_t len;
+
+  len = pb->tot_len;
+
+  /* make room for PPPoE header - should not fail */
+  if (pbuf_add_header(pb, PPPOE_HEADERLEN) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppoe: %c%c%"U16_F": pppoe_xmit: could not allocate room for PPPoE header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  }
+
+  p = (u8_t*)pb->payload;
+  PPPOE_ADD_HEADER(p, 0, sc->sc_session, len);
+
+  return pppoe_output(sc, pb);
+}
+
+#if 0 /*def PFIL_HOOKS*/
+static int
+pppoe_ifattach_hook(void *arg, struct pbuf **mp, struct netif *ifp, int dir)
+{
+  struct pppoe_softc *sc;
+  int s;
+
+  if (mp != (struct pbuf **)PFIL_IFNET_DETACH) {
+    return 0;
+  }
+
+  LIST_FOREACH(sc, &pppoe_softc_list, sc_list) {
+    if (sc->sc_ethif != ifp) {
+      continue;
+    }
+    if (sc->sc_sppp.pp_if.if_flags & IFF_UP) {
+      sc->sc_sppp.pp_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
+      PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": ethernet interface detached, going down\n",
+          sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num));
+    }
+    sc->sc_ethif = NULL;
+    pppoe_clear_softc(sc, "ethernet interface detached");
+  }
+
+  return 0;
+}
+#endif
+
+#if 0 /* UNUSED */
+static void
+pppoe_clear_softc(struct pppoe_softc *sc, const char *message)
+{
+  LWIP_UNUSED_ARG(message);
+
+  /* stop timer */
+  sys_untimeout(pppoe_timeout, sc);
+  PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x terminated, %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_session, message));
+  sc->sc_state = PPPOE_STATE_INITIAL;
+  ppp_link_end(sc->pcb);  /* notify upper layers - /!\ dangerous /!\ - see pppoe_disc_input() */
+}
+#endif /* UNUSED */
+#endif /* PPP_SUPPORT && PPPOE_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppol2tp.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppol2tp.c
new file mode 100644
index 000000000..4c4557fca
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppol2tp.c
@@ -0,0 +1,1159 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Layer 2 Tunneling Protocol program file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+/*
+ * L2TP Support status:
+ *
+ * Supported:
+ * - L2TPv2 (PPP over L2TP, a.k.a. UDP tunnels)
+ * - LAC
+ *
+ * Not supported:
+ * - LNS (require PPP server support)
+ * - L2TPv3 ethernet pseudowires
+ * - L2TPv3 VLAN pseudowire
+ * - L2TPv3 PPP pseudowires
+ * - L2TPv3 IP encapsulation
+ * - L2TPv3 IP pseudowire
+ * - L2TP tunnel switching - http://tools.ietf.org/html/draft-ietf-l2tpext-tunnel-switching-08
+ * - Multiple tunnels per UDP socket, as well as multiple sessions per tunnel
+ * - Hidden AVPs
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/err.h"
+#include "lwip/memp.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "lwip/snmp.h"
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/lcp.h"
+#include "netif/ppp/ipcp.h"
+#include "netif/ppp/pppol2tp.h"
+#include "netif/ppp/pppcrypt.h"
+#include "netif/ppp/magic.h"
+
+/* Memory pool */
+LWIP_MEMPOOL_DECLARE(PPPOL2TP_PCB, MEMP_NUM_PPPOL2TP_INTERFACES, sizeof(pppol2tp_pcb), "PPPOL2TP_PCB")
+
+/* callbacks called from PPP core */
+static err_t pppol2tp_write(ppp_pcb *ppp, void *ctx, struct pbuf *p);
+static err_t pppol2tp_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol);
+static err_t pppol2tp_destroy(ppp_pcb *ppp, void *ctx);    /* Destroy a L2TP control block */
+static void pppol2tp_connect(ppp_pcb *ppp, void *ctx);    /* Be a LAC, connect to a LNS. */
+static void pppol2tp_disconnect(ppp_pcb *ppp, void *ctx);  /* Disconnect */
+
+ /* Prototypes for procedures local to this file. */
+static void pppol2tp_input(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port);
+static void pppol2tp_dispatch_control_packet(pppol2tp_pcb *l2tp, u16_t port, struct pbuf *p, u16_t ns, u16_t nr);
+static void pppol2tp_timeout(void *arg);
+static void pppol2tp_abort_connect(pppol2tp_pcb *l2tp);
+static err_t pppol2tp_send_sccrq(pppol2tp_pcb *l2tp);
+static err_t pppol2tp_send_scccn(pppol2tp_pcb *l2tp, u16_t ns);
+static err_t pppol2tp_send_icrq(pppol2tp_pcb *l2tp, u16_t ns);
+static err_t pppol2tp_send_iccn(pppol2tp_pcb *l2tp, u16_t ns);
+static err_t pppol2tp_send_zlb(pppol2tp_pcb *l2tp, u16_t ns, u16_t nr);
+static err_t pppol2tp_send_stopccn(pppol2tp_pcb *l2tp, u16_t ns);
+static err_t pppol2tp_xmit(pppol2tp_pcb *l2tp, struct pbuf *pb);
+static err_t pppol2tp_udp_send(pppol2tp_pcb *l2tp, struct pbuf *pb);
+
+/* Callbacks structure for PPP core */
+static const struct link_callbacks pppol2tp_callbacks = {
+  pppol2tp_connect,
+#if PPP_SERVER
+  NULL,
+#endif /* PPP_SERVER */
+  pppol2tp_disconnect,
+  pppol2tp_destroy,
+  pppol2tp_write,
+  pppol2tp_netif_output,
+  NULL,
+  NULL
+};
+
+
+/* Create a new L2TP session. */
+ppp_pcb *pppol2tp_create(struct netif *pppif,
+       struct netif *netif, const ip_addr_t *ipaddr, u16_t port,
+       const u8_t *secret, u8_t secret_len,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb) {
+  ppp_pcb *ppp;
+  pppol2tp_pcb *l2tp;
+  struct udp_pcb *udp;
+#if !PPPOL2TP_AUTH_SUPPORT
+  LWIP_UNUSED_ARG(secret);
+  LWIP_UNUSED_ARG(secret_len);
+#endif /* !PPPOL2TP_AUTH_SUPPORT */
+
+  if (ipaddr == NULL) {
+    goto ipaddr_check_failed;
+  }
+
+  l2tp = (pppol2tp_pcb *)LWIP_MEMPOOL_ALLOC(PPPOL2TP_PCB);
+  if (l2tp == NULL) {
+    goto memp_malloc_l2tp_failed;
+  }
+
+  udp = udp_new_ip_type(IP_GET_TYPE(ipaddr));
+  if (udp == NULL) {
+    goto udp_new_failed;
+  }
+  udp_recv(udp, pppol2tp_input, l2tp);
+
+  ppp = ppp_new(pppif, &pppol2tp_callbacks, l2tp, link_status_cb, ctx_cb);
+  if (ppp == NULL) {
+    goto ppp_new_failed;
+  }
+
+  memset(l2tp, 0, sizeof(pppol2tp_pcb));
+  l2tp->phase = PPPOL2TP_STATE_INITIAL;
+  l2tp->ppp = ppp;
+  l2tp->udp = udp;
+  l2tp->netif = netif;
+  ip_addr_copy(l2tp->remote_ip, *ipaddr);
+  l2tp->remote_port = port;
+#if PPPOL2TP_AUTH_SUPPORT
+  l2tp->secret = secret;
+  l2tp->secret_len = secret_len;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  return ppp;
+
+ppp_new_failed:
+  udp_remove(udp);
+udp_new_failed:
+  LWIP_MEMPOOL_FREE(PPPOL2TP_PCB, l2tp);
+memp_malloc_l2tp_failed:
+ipaddr_check_failed:
+  return NULL;
+}
+
+/* Called by PPP core */
+static err_t pppol2tp_write(ppp_pcb *ppp, void *ctx, struct pbuf *p) {
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx;
+  struct pbuf *ph; /* UDP + L2TP header */
+  err_t ret;
+#if MIB2_STATS
+  u16_t tot_len;
+#else /* MIB2_STATS */
+  LWIP_UNUSED_ARG(ppp);
+#endif /* MIB2_STATS */
+
+  ph = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(PPPOL2TP_OUTPUT_DATA_HEADER_LEN), PBUF_RAM);
+  if(!ph) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    pbuf_free(p);
+    return ERR_MEM;
+  }
+
+  pbuf_remove_header(ph, PPPOL2TP_OUTPUT_DATA_HEADER_LEN); /* hide L2TP header */
+  pbuf_cat(ph, p);
+#if MIB2_STATS
+  tot_len = ph->tot_len;
+#endif /* MIB2_STATS */
+
+  ret = pppol2tp_xmit(l2tp, ph);
+  if (ret != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return ret;
+  }
+
+  MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, (u16_t)tot_len);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts);
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+
+/* Called by PPP core */
+static err_t pppol2tp_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol) {
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx;
+  struct pbuf *pb;
+  u8_t *pl;
+  err_t err;
+#if MIB2_STATS
+  u16_t tot_len;
+#else /* MIB2_STATS */
+  LWIP_UNUSED_ARG(ppp);
+#endif /* MIB2_STATS */
+
+  /* @todo: try to use pbuf_header() here! */
+  pb = pbuf_alloc(PBUF_TRANSPORT, PPPOL2TP_OUTPUT_DATA_HEADER_LEN + sizeof(protocol), PBUF_RAM);
+  if(!pb) {
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.proterr);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return ERR_MEM;
+  }
+
+  pbuf_remove_header(pb, PPPOL2TP_OUTPUT_DATA_HEADER_LEN);
+
+  pl = (u8_t*)pb->payload;
+  PUTSHORT(protocol, pl);
+
+  pbuf_chain(pb, p);
+#if MIB2_STATS
+  tot_len = pb->tot_len;
+#endif /* MIB2_STATS */
+
+  if( (err = pppol2tp_xmit(l2tp, pb)) != ERR_OK) {
+    LINK_STATS_INC(link.err);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return err;
+  }
+
+  MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, tot_len);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts);
+  LINK_STATS_INC(link.xmit);
+  return ERR_OK;
+}
+
+/* Destroy a L2TP control block */
+static err_t pppol2tp_destroy(ppp_pcb *ppp, void *ctx) {
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx;
+  LWIP_UNUSED_ARG(ppp);
+
+  sys_untimeout(pppol2tp_timeout, l2tp);
+  udp_remove(l2tp->udp);
+  LWIP_MEMPOOL_FREE(PPPOL2TP_PCB, l2tp);
+  return ERR_OK;
+}
+
+/* Be a LAC, connect to a LNS. */
+static void pppol2tp_connect(ppp_pcb *ppp, void *ctx) {
+  err_t err;
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx;
+  lcp_options *lcp_wo;
+  lcp_options *lcp_ao;
+#if PPP_IPV4_SUPPORT && VJ_SUPPORT
+  ipcp_options *ipcp_wo;
+  ipcp_options *ipcp_ao;
+#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */
+
+  l2tp->tunnel_port = l2tp->remote_port;
+  l2tp->our_ns = 0;
+  l2tp->peer_nr = 0;
+  l2tp->peer_ns = 0;
+  l2tp->source_tunnel_id = 0;
+  l2tp->remote_tunnel_id = 0;
+  l2tp->source_session_id = 0;
+  l2tp->remote_session_id = 0;
+  /* l2tp->*_retried are cleared when used */
+
+  lcp_wo = &ppp->lcp_wantoptions;
+  lcp_wo->mru = PPPOL2TP_DEFMRU;
+  lcp_wo->neg_asyncmap = 0;
+  lcp_wo->neg_pcompression = 0;
+  lcp_wo->neg_accompression = 0;
+  lcp_wo->passive = 0;
+  lcp_wo->silent = 0;
+
+  lcp_ao = &ppp->lcp_allowoptions;
+  lcp_ao->mru = PPPOL2TP_DEFMRU;
+  lcp_ao->neg_asyncmap = 0;
+  lcp_ao->neg_pcompression = 0;
+  lcp_ao->neg_accompression = 0;
+
+#if PPP_IPV4_SUPPORT && VJ_SUPPORT
+  ipcp_wo = &ppp->ipcp_wantoptions;
+  ipcp_wo->neg_vj = 0;
+  ipcp_wo->old_vj = 0;
+
+  ipcp_ao = &ppp->ipcp_allowoptions;
+  ipcp_ao->neg_vj = 0;
+  ipcp_ao->old_vj = 0;
+#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */
+
+  /* Listen to a random source port, we need to do that instead of using udp_connect()
+   * because the L2TP LNS might answer with its own random source port (!= 1701)
+   */
+#if LWIP_IPV6
+  if (IP_IS_V6_VAL(l2tp->udp->local_ip)) {
+    udp_bind(l2tp->udp, IP6_ADDR_ANY, 0);
+  } else
+#endif /* LWIP_IPV6 */
+  udp_bind(l2tp->udp, IP_ADDR_ANY, 0);
+
+#if PPPOL2TP_AUTH_SUPPORT
+  /* Generate random vector */
+  if (l2tp->secret != NULL) {
+    magic_random_bytes(l2tp->secret_rv, sizeof(l2tp->secret_rv));
+  }
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  do {
+    l2tp->remote_tunnel_id = magic();
+  } while(l2tp->remote_tunnel_id == 0);
+  /* save state, in case we fail to send SCCRQ */
+  l2tp->sccrq_retried = 0;
+  l2tp->phase = PPPOL2TP_STATE_SCCRQ_SENT;
+  if ((err = pppol2tp_send_sccrq(l2tp)) != 0) {
+    PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCRQ, error=%d\n", err));
+  }
+  sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp);
+}
+
+/* Disconnect */
+static void pppol2tp_disconnect(ppp_pcb *ppp, void *ctx) {
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx;
+
+  l2tp->our_ns++;
+  pppol2tp_send_stopccn(l2tp, l2tp->our_ns);
+
+  /* stop any timer, disconnect can be called while initiating is in progress */
+  sys_untimeout(pppol2tp_timeout, l2tp);
+  l2tp->phase = PPPOL2TP_STATE_INITIAL;
+  ppp_link_end(ppp); /* notify upper layers */
+}
+
+/* UDP Callback for incoming IPv4 L2TP frames */
+static void pppol2tp_input(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) {
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb*)arg;
+  u16_t hflags, hlen, len=0, tunnel_id=0, session_id=0, ns=0, nr=0, offset=0;
+  u8_t *inp;
+  LWIP_UNUSED_ARG(pcb);
+
+  /* we can't unbound a UDP pcb, thus we can still receive UDP frames after the link is closed */
+  if (l2tp->phase < PPPOL2TP_STATE_SCCRQ_SENT) {
+    goto free_and_return;
+  }
+
+  if (!ip_addr_cmp(&l2tp->remote_ip, addr)) {
+    goto free_and_return;
+  }
+
+  /* discard packet if port mismatch, but only if we received a SCCRP */
+  if (l2tp->phase > PPPOL2TP_STATE_SCCRQ_SENT && l2tp->tunnel_port != port) {
+    goto free_and_return;
+  }
+
+  /* printf("-----------\nL2TP INPUT, %d\n", p->len); */
+
+  /* L2TP header */
+  if (p->len < sizeof(hflags) + sizeof(tunnel_id) + sizeof(session_id) ) {
+    goto packet_too_short;
+  }
+
+  inp = (u8_t*)p->payload;
+  GETSHORT(hflags, inp);
+
+  if (hflags & PPPOL2TP_HEADERFLAG_CONTROL) {
+    /* check mandatory flags for a control packet */
+    if ( (hflags & PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY) != PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY ) {
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: mandatory header flags for control packet not set\n"));
+      goto free_and_return;
+    }
+    /* check forbidden flags for a control packet */
+    if (hflags & PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN) {
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: forbidden header flags for control packet found\n"));
+      goto free_and_return;
+    }
+  } else {
+    /* check mandatory flags for a data packet */
+    if ( (hflags & PPPOL2TP_HEADERFLAG_DATA_MANDATORY) != PPPOL2TP_HEADERFLAG_DATA_MANDATORY) {
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: mandatory header flags for data packet not set\n"));
+      goto free_and_return;
+    }
+  }
+
+  /* Expected header size  */
+  hlen = sizeof(hflags) + sizeof(tunnel_id) + sizeof(session_id);
+  if (hflags & PPPOL2TP_HEADERFLAG_LENGTH) {
+    hlen += sizeof(len);
+  }
+  if (hflags & PPPOL2TP_HEADERFLAG_SEQUENCE) {
+    hlen += sizeof(ns) + sizeof(nr);
+  }
+  if (hflags & PPPOL2TP_HEADERFLAG_OFFSET) {
+    hlen += sizeof(offset);
+  }
+  if (p->len < hlen) {
+    goto packet_too_short;
+  }
+
+  if (hflags & PPPOL2TP_HEADERFLAG_LENGTH) {
+    GETSHORT(len, inp);
+    if (p->len < len || len < hlen) {
+      goto packet_too_short;
+    }
+  }
+  GETSHORT(tunnel_id, inp);
+  GETSHORT(session_id, inp);
+  if (hflags & PPPOL2TP_HEADERFLAG_SEQUENCE) {
+    GETSHORT(ns, inp);
+    GETSHORT(nr, inp);
+  }
+  if (hflags & PPPOL2TP_HEADERFLAG_OFFSET) {
+    GETSHORT(offset, inp)
+    if (offset > 4096) { /* don't be fooled with large offset which might overflow hlen */
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: strange packet received, offset=%d\n", offset));
+      goto free_and_return;
+    }
+    hlen += offset;
+    if (p->len < hlen) {
+      goto packet_too_short;
+    }
+    INCPTR(offset, inp);
+  }
+
+  /* printf("HLEN = %d\n", hlen); */
+
+  /* skip L2TP header */
+  if (pbuf_remove_header(p, hlen) != 0) {
+    goto free_and_return;
+  }
+
+  /* printf("LEN=%d, TUNNEL_ID=%d, SESSION_ID=%d, NS=%d, NR=%d, OFFSET=%d\n", len, tunnel_id, session_id, ns, nr, offset); */
+  PPPDEBUG(LOG_DEBUG, ("pppol2tp: input packet, len=%"U16_F", tunnel=%"U16_F", session=%"U16_F", ns=%"U16_F", nr=%"U16_F"\n",
+    len, tunnel_id, session_id, ns, nr));
+
+  /* Control packet */
+  if (hflags & PPPOL2TP_HEADERFLAG_CONTROL) {
+    pppol2tp_dispatch_control_packet(l2tp, port, p, ns, nr);
+    goto free_and_return;
+  }
+
+  /* Data packet */
+  if(l2tp->phase != PPPOL2TP_STATE_DATA) {
+    goto free_and_return;
+  }
+  if(tunnel_id != l2tp->remote_tunnel_id) {
+     PPPDEBUG(LOG_DEBUG, ("pppol2tp: tunnel ID mismatch, assigned=%d, received=%d\n", l2tp->remote_tunnel_id, tunnel_id));
+     goto free_and_return;
+  }
+  if(session_id != l2tp->remote_session_id) {
+     PPPDEBUG(LOG_DEBUG, ("pppol2tp: session ID mismatch, assigned=%d, received=%d\n", l2tp->remote_session_id, session_id));
+     goto free_and_return;
+  }
+  /*
+   * skip address & flags if necessary
+   *
+   * RFC 2661 does not specify whether the PPP frame in the L2TP payload should
+   * have a HDLC header or not. We handle both cases for compatibility.
+   */
+  if (p->len >= 2) {
+    GETSHORT(hflags, inp);
+    if (hflags == 0xff03) {
+      pbuf_remove_header(p, 2);
+    }
+  }
+  /* Dispatch the packet thereby consuming it. */
+  ppp_input(l2tp->ppp, p);
+  return;
+
+packet_too_short:
+  PPPDEBUG(LOG_DEBUG, ("pppol2tp: packet too short: %d\n", p->len));
+free_and_return:
+  pbuf_free(p);
+}
+
+/* L2TP Control packet entry point */
+static void pppol2tp_dispatch_control_packet(pppol2tp_pcb *l2tp, u16_t port, struct pbuf *p, u16_t ns, u16_t nr) {
+  u8_t *inp;
+  u16_t avplen, avpflags, vendorid, attributetype, messagetype=0;
+  err_t err;
+#if PPPOL2TP_AUTH_SUPPORT
+  lwip_md5_context md5_ctx;
+  u8_t md5_hash[16];
+  u8_t challenge_id = 0;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  /* printf("L2TP CTRL INPUT, ns=%d, nr=%d, len=%d\n", ns, nr, p->len); */
+
+  /* Drop unexpected packet */
+  if (ns != l2tp->peer_ns) {
+    PPPDEBUG(LOG_DEBUG, ("pppol2tp: drop unexpected packet: received NS=%d, expected NS=%d\n", ns, l2tp->peer_ns));
+    /*
+     * In order to ensure that all messages are acknowledged properly
+     * (particularly in the case of a lost ZLB ACK message), receipt
+     * of duplicate messages MUST be acknowledged.
+     *
+     * In this very special case we Ack a packet we previously received.
+     * Therefore our NS is the NR we just received. And our NR is the
+     * NS we just received plus one.
+     */
+    if ((s16_t)(ns - l2tp->peer_ns) < 0) {
+      pppol2tp_send_zlb(l2tp, nr, ns+1);
+    }
+    return;
+  }
+
+  l2tp->peer_nr = nr;
+
+  /* Handle the special case of the ICCN acknowledge */
+  if (l2tp->phase == PPPOL2TP_STATE_ICCN_SENT && (s16_t)(l2tp->peer_nr - l2tp->our_ns) > 0) {
+    l2tp->phase = PPPOL2TP_STATE_DATA;
+    sys_untimeout(pppol2tp_timeout, l2tp);
+    ppp_start(l2tp->ppp); /* notify upper layers */
+  }
+
+  /* ZLB packets */
+  if (p->tot_len == 0) {
+    return;
+  }
+  /* A ZLB packet does not consume a NS slot thus we don't record the NS value for ZLB packets */
+  l2tp->peer_ns = ns+1;
+
+  p = pbuf_coalesce(p, PBUF_RAW);
+  inp = (u8_t*)p->payload;
+  /* Decode AVPs */
+  while (p->len > 0) {
+    if (p->len < sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype) ) {
+      goto packet_too_short;
+    }
+    GETSHORT(avpflags, inp);
+    avplen = avpflags & PPPOL2TP_AVPHEADERFLAG_LENGTHMASK;
+    /* printf("AVPLEN = %d\n", avplen); */
+    if (p->len < avplen || avplen < sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype)) {
+      goto packet_too_short;
+    }
+    GETSHORT(vendorid, inp);
+    GETSHORT(attributetype, inp);
+    avplen -= sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype);
+
+    /* Message type must be the first AVP */
+    if (messagetype == 0) {
+      if (attributetype != 0 || vendorid != 0 || avplen != sizeof(messagetype) ) {
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: message type must be the first AVP\n"));
+        return;
+      }
+      GETSHORT(messagetype, inp);
+      /* printf("Message type = %d\n", messagetype); */
+      switch(messagetype) {
+        /* Start Control Connection Reply */
+        case PPPOL2TP_MESSAGETYPE_SCCRP:
+          /* Only accept SCCRP packet if we sent a SCCRQ */
+          if (l2tp->phase != PPPOL2TP_STATE_SCCRQ_SENT) {
+            goto send_zlb;
+          }
+          break;
+        /* Incoming Call Reply */
+        case PPPOL2TP_MESSAGETYPE_ICRP:
+          /* Only accept ICRP packet if we sent a IRCQ */
+          if (l2tp->phase != PPPOL2TP_STATE_ICRQ_SENT) {
+            goto send_zlb;
+          }
+          break;
+        /* Stop Control Connection Notification */
+        case PPPOL2TP_MESSAGETYPE_STOPCCN:
+          pppol2tp_send_zlb(l2tp, l2tp->our_ns+1, l2tp->peer_ns); /* Ack the StopCCN before we switch to down state */
+          if (l2tp->phase < PPPOL2TP_STATE_DATA) {
+            pppol2tp_abort_connect(l2tp);
+          } else if (l2tp->phase == PPPOL2TP_STATE_DATA) {
+            /* Don't disconnect here, we let the LCP Echo/Reply find the fact
+             * that PPP session is down. Asking the PPP stack to end the session
+             * require strict checking about the PPP phase to prevent endless
+             * disconnection loops.
+             */
+          }
+          return;
+        default:
+          break;
+      }
+      goto nextavp;
+    }
+
+    /* Skip proprietary L2TP extensions */
+    if (vendorid != 0) {
+      goto skipavp;
+    }
+
+    switch (messagetype) {
+      /* Start Control Connection Reply */
+      case PPPOL2TP_MESSAGETYPE_SCCRP:
+       switch (attributetype) {
+          case PPPOL2TP_AVPTYPE_TUNNELID:
+            if (avplen != sizeof(l2tp->source_tunnel_id) ) {
+               PPPDEBUG(LOG_DEBUG, ("pppol2tp: AVP Assign tunnel ID length check failed\n"));
+               return;
+            }
+            GETSHORT(l2tp->source_tunnel_id, inp);
+            PPPDEBUG(LOG_DEBUG, ("pppol2tp: Assigned tunnel ID %"U16_F"\n", l2tp->source_tunnel_id));
+            goto nextavp;
+#if PPPOL2TP_AUTH_SUPPORT
+          case PPPOL2TP_AVPTYPE_CHALLENGE:
+            if (avplen == 0) {
+               PPPDEBUG(LOG_DEBUG, ("pppol2tp: Challenge length check failed\n"));
+               return;
+            }
+            if (l2tp->secret == NULL) {
+              PPPDEBUG(LOG_DEBUG, ("pppol2tp: Received challenge from peer and no secret key available\n"));
+              pppol2tp_abort_connect(l2tp);
+              return;
+            }
+            /* Generate hash of ID, secret, challenge */
+            lwip_md5_init(&md5_ctx);
+            lwip_md5_starts(&md5_ctx);
+            challenge_id = PPPOL2TP_MESSAGETYPE_SCCCN;
+            lwip_md5_update(&md5_ctx, &challenge_id, 1);
+            lwip_md5_update(&md5_ctx, l2tp->secret, l2tp->secret_len);
+            lwip_md5_update(&md5_ctx, inp, avplen);
+            lwip_md5_finish(&md5_ctx, l2tp->challenge_hash);
+            lwip_md5_free(&md5_ctx);
+            l2tp->send_challenge = 1;
+            goto skipavp;
+          case PPPOL2TP_AVPTYPE_CHALLENGERESPONSE:
+            if (avplen != PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE) {
+               PPPDEBUG(LOG_DEBUG, ("pppol2tp: AVP Challenge Response length check failed\n"));
+               return;
+            }
+            /* Generate hash of ID, secret, challenge */
+            lwip_md5_init(&md5_ctx);
+            lwip_md5_starts(&md5_ctx);
+            challenge_id = PPPOL2TP_MESSAGETYPE_SCCRP;
+            lwip_md5_update(&md5_ctx, &challenge_id, 1);
+            lwip_md5_update(&md5_ctx, l2tp->secret, l2tp->secret_len);
+            lwip_md5_update(&md5_ctx, l2tp->secret_rv, sizeof(l2tp->secret_rv));
+            lwip_md5_finish(&md5_ctx, md5_hash);
+            lwip_md5_free(&md5_ctx);
+            if ( memcmp(inp, md5_hash, sizeof(md5_hash)) ) {
+              PPPDEBUG(LOG_DEBUG, ("pppol2tp: Received challenge response from peer and secret key do not match\n"));
+              pppol2tp_abort_connect(l2tp);
+              return;
+            }
+            goto skipavp;
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+          default:
+            break;
+        }
+        break;
+      /* Incoming Call Reply */
+      case PPPOL2TP_MESSAGETYPE_ICRP:
+        switch (attributetype) {
+         case PPPOL2TP_AVPTYPE_SESSIONID:
+            if (avplen != sizeof(l2tp->source_session_id) ) {
+               PPPDEBUG(LOG_DEBUG, ("pppol2tp: AVP Assign session ID length check failed\n"));
+               return;
+            }
+            GETSHORT(l2tp->source_session_id, inp);
+            PPPDEBUG(LOG_DEBUG, ("pppol2tp: Assigned session ID %"U16_F"\n", l2tp->source_session_id));
+            goto nextavp;
+          default:
+            break;
+        }
+        break;
+      default:
+        break;
+    }
+
+skipavp:
+    INCPTR(avplen, inp);
+nextavp:
+    /* printf("AVP Found, vendor=%d, attribute=%d, len=%d\n", vendorid, attributetype, avplen); */
+    /* next AVP */
+    if (pbuf_remove_header(p, avplen + sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype)) != 0) {
+      return;
+    }
+  }
+
+  switch(messagetype) {
+    /* Start Control Connection Reply */
+    case PPPOL2TP_MESSAGETYPE_SCCRP:
+      do {
+        l2tp->remote_session_id = magic();
+      } while(l2tp->remote_session_id == 0);
+      l2tp->tunnel_port = port; /* LNS server might have chosen its own local port */
+      l2tp->icrq_retried = 0;
+      l2tp->phase = PPPOL2TP_STATE_ICRQ_SENT;
+      l2tp->our_ns++;
+      if ((err = pppol2tp_send_scccn(l2tp, l2tp->our_ns)) != 0) {
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCCN, error=%d\n", err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      l2tp->our_ns++;
+      if ((err = pppol2tp_send_icrq(l2tp, l2tp->our_ns)) != 0) {
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICRQ, error=%d\n", err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_untimeout(pppol2tp_timeout, l2tp);
+      sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp);
+      break;
+    /* Incoming Call Reply */
+    case PPPOL2TP_MESSAGETYPE_ICRP:
+      l2tp->iccn_retried = 0;
+      l2tp->phase = PPPOL2TP_STATE_ICCN_SENT;
+      l2tp->our_ns++;
+      if ((err = pppol2tp_send_iccn(l2tp, l2tp->our_ns)) != 0) {
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICCN, error=%d\n", err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_untimeout(pppol2tp_timeout, l2tp);
+      sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp);
+      break;
+    /* Unhandled packet, send ZLB ACK */
+    default:
+      goto send_zlb;
+  }
+  return;
+
+send_zlb:
+  pppol2tp_send_zlb(l2tp, l2tp->our_ns+1, l2tp->peer_ns);
+  return;
+packet_too_short:
+  PPPDEBUG(LOG_DEBUG, ("pppol2tp: packet too short: %d\n", p->len));
+}
+
+/* L2TP Timeout handler */
+static void pppol2tp_timeout(void *arg) {
+  pppol2tp_pcb *l2tp = (pppol2tp_pcb*)arg;
+  err_t err;
+  u32_t retry_wait;
+
+  PPPDEBUG(LOG_DEBUG, ("pppol2tp: timeout\n"));
+
+  switch (l2tp->phase) {
+    case PPPOL2TP_STATE_SCCRQ_SENT:
+      /* backoff wait */
+      if (l2tp->sccrq_retried < 0xff) {
+        l2tp->sccrq_retried++;
+      }
+      if (!l2tp->ppp->settings.persist && l2tp->sccrq_retried >= PPPOL2TP_MAXSCCRQ) {
+        pppol2tp_abort_connect(l2tp);
+        return;
+      }
+      retry_wait = LWIP_MIN(PPPOL2TP_CONTROL_TIMEOUT * l2tp->sccrq_retried, PPPOL2TP_SLOW_RETRY);
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: sccrq_retried=%d\n", l2tp->sccrq_retried));
+      if ((err = pppol2tp_send_sccrq(l2tp)) != 0) {
+        l2tp->sccrq_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCRQ, error=%d\n", err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_timeout(retry_wait, pppol2tp_timeout, l2tp);
+      break;
+
+    case PPPOL2TP_STATE_ICRQ_SENT:
+      l2tp->icrq_retried++;
+      if (l2tp->icrq_retried >= PPPOL2TP_MAXICRQ) {
+        pppol2tp_abort_connect(l2tp);
+        return;
+      }
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: icrq_retried=%d\n", l2tp->icrq_retried));
+      if ((s16_t)(l2tp->peer_nr - l2tp->our_ns) < 0) { /* the SCCCN was not acknowledged */
+        if ((err = pppol2tp_send_scccn(l2tp, l2tp->our_ns -1)) != 0) {
+          l2tp->icrq_retried--;
+          PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCCN, error=%d\n", err));
+          LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+          sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp);
+          break;
+        }
+      }
+      if ((err = pppol2tp_send_icrq(l2tp, l2tp->our_ns)) != 0) {
+        l2tp->icrq_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICRQ, error=%d\n", err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp);
+      break;
+
+    case PPPOL2TP_STATE_ICCN_SENT:
+      l2tp->iccn_retried++;
+      if (l2tp->iccn_retried >= PPPOL2TP_MAXICCN) {
+        pppol2tp_abort_connect(l2tp);
+        return;
+      }
+      PPPDEBUG(LOG_DEBUG, ("pppol2tp: iccn_retried=%d\n", l2tp->iccn_retried));
+      if ((err = pppol2tp_send_iccn(l2tp, l2tp->our_ns)) != 0) {
+        l2tp->iccn_retried--;
+        PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICCN, error=%d\n", err));
+        LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */
+      }
+      sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp);
+      break;
+
+    default:
+      return;  /* all done, work in peace */
+  }
+}
+
+/* Connection attempt aborted */
+static void pppol2tp_abort_connect(pppol2tp_pcb *l2tp) {
+  PPPDEBUG(LOG_DEBUG, ("pppol2tp: could not establish connection\n"));
+  l2tp->phase = PPPOL2TP_STATE_INITIAL;
+  ppp_link_failed(l2tp->ppp); /* notify upper layers */
+}
+
+/* Initiate a new tunnel */
+static err_t pppol2tp_send_sccrq(pppol2tp_pcb *l2tp) {
+  struct pbuf *pb;
+  u8_t *p;
+  u16_t len;
+
+  /* calculate UDP packet length */
+  len = 12 +8 +8 +10 +10 +6+sizeof(PPPOL2TP_HOSTNAME)-1 +6+sizeof(PPPOL2TP_VENDORNAME)-1 +8 +8;
+#if PPPOL2TP_AUTH_SUPPORT
+  if (l2tp->secret != NULL) {
+    len += 6 + sizeof(l2tp->secret_rv);
+  }
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pb == NULL) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  /* L2TP control header */
+  PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p);
+  PUTSHORT(len, p); /* Length */
+  PUTSHORT(0, p); /* Tunnel Id */
+  PUTSHORT(0, p); /* Session Id */
+  PUTSHORT(0, p); /* NS Sequence number - to peer */
+  PUTSHORT(0, p); /* NR Sequence number - expected for peer */
+
+  /* AVP - Message type */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */
+  PUTSHORT(PPPOL2TP_MESSAGETYPE_SCCRQ, p); /* Attribute value: Message type: SCCRQ */
+
+  /* AVP - L2TP Version */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_VERSION, p); /* Attribute type: Version */
+  PUTSHORT(PPPOL2TP_VERSION, p); /* Attribute value: L2TP Version */
+
+  /* AVP - Framing capabilities */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES, p); /* Attribute type: Framing capabilities */
+  PUTLONG(PPPOL2TP_FRAMINGCAPABILITIES, p); /* Attribute value: Framing capabilities */
+
+  /* AVP - Bearer capabilities */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_BEARERCAPABILITIES, p); /* Attribute type: Bearer capabilities */
+  PUTLONG(PPPOL2TP_BEARERCAPABILITIES, p); /* Attribute value: Bearer capabilities */
+
+  /* AVP - Host name */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 6+sizeof(PPPOL2TP_HOSTNAME)-1, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_HOSTNAME, p); /* Attribute type: Hostname */
+  MEMCPY(p, PPPOL2TP_HOSTNAME, sizeof(PPPOL2TP_HOSTNAME)-1); /* Attribute value: Hostname */
+  INCPTR(sizeof(PPPOL2TP_HOSTNAME)-1, p);
+
+  /* AVP - Vendor name */
+  PUTSHORT(6+sizeof(PPPOL2TP_VENDORNAME)-1, p); /* len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_VENDORNAME, p); /* Attribute type: Vendor name */
+  MEMCPY(p, PPPOL2TP_VENDORNAME, sizeof(PPPOL2TP_VENDORNAME)-1); /* Attribute value: Vendor name */
+  INCPTR(sizeof(PPPOL2TP_VENDORNAME)-1, p);
+
+  /* AVP - Assign tunnel ID */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_TUNNELID, p); /* Attribute type: Tunnel ID */
+  PUTSHORT(l2tp->remote_tunnel_id, p); /* Attribute value: Tunnel ID */
+
+  /* AVP - Receive window size */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE, p); /* Attribute type: Receive window size */
+  PUTSHORT(PPPOL2TP_RECEIVEWINDOWSIZE, p); /* Attribute value: Receive window size */
+
+#if PPPOL2TP_AUTH_SUPPORT
+  /* AVP - Challenge */
+  if (l2tp->secret != NULL) {
+    PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 6 + sizeof(l2tp->secret_rv), p); /* Mandatory flag + len field */
+    PUTSHORT(0, p); /* Vendor ID */
+    PUTSHORT(PPPOL2TP_AVPTYPE_CHALLENGE, p); /* Attribute type: Challenge */
+    MEMCPY(p, l2tp->secret_rv, sizeof(l2tp->secret_rv)); /* Attribute value: Random vector */
+    INCPTR(sizeof(l2tp->secret_rv), p);
+  }
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+/* Complete tunnel establishment */
+static err_t pppol2tp_send_scccn(pppol2tp_pcb *l2tp, u16_t ns) {
+  struct pbuf *pb;
+  u8_t *p;
+  u16_t len;
+
+  /* calculate UDP packet length */
+  len = 12 +8;
+#if PPPOL2TP_AUTH_SUPPORT
+  if (l2tp->send_challenge) {
+    len += 6 + sizeof(l2tp->challenge_hash);
+  }
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pb == NULL) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  /* L2TP control header */
+  PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p);
+  PUTSHORT(len, p); /* Length */
+  PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */
+  PUTSHORT(0, p); /* Session Id */
+  PUTSHORT(ns, p); /* NS Sequence number - to peer */
+  PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */
+
+  /* AVP - Message type */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */
+  PUTSHORT(PPPOL2TP_MESSAGETYPE_SCCCN, p); /* Attribute value: Message type: SCCCN */
+
+#if PPPOL2TP_AUTH_SUPPORT
+  /* AVP - Challenge response */
+  if (l2tp->send_challenge) {
+    PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 6 + sizeof(l2tp->challenge_hash), p); /* Mandatory flag + len field */
+    PUTSHORT(0, p); /* Vendor ID */
+    PUTSHORT(PPPOL2TP_AVPTYPE_CHALLENGERESPONSE, p); /* Attribute type: Challenge response */
+    MEMCPY(p, l2tp->challenge_hash, sizeof(l2tp->challenge_hash)); /* Attribute value: Computed challenge */
+    INCPTR(sizeof(l2tp->challenge_hash), p);
+  }
+#endif /* PPPOL2TP_AUTH_SUPPORT */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+/* Initiate a new session */
+static err_t pppol2tp_send_icrq(pppol2tp_pcb *l2tp, u16_t ns) {
+  struct pbuf *pb;
+  u8_t *p;
+  u16_t len;
+  u32_t serialnumber;
+
+  /* calculate UDP packet length */
+  len = 12 +8 +8 +10;
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pb == NULL) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  /* L2TP control header */
+  PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p);
+  PUTSHORT(len, p); /* Length */
+  PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */
+  PUTSHORT(0, p); /* Session Id */
+  PUTSHORT(ns, p); /* NS Sequence number - to peer */
+  PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */
+
+  /* AVP - Message type */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */
+  PUTSHORT(PPPOL2TP_MESSAGETYPE_ICRQ, p); /* Attribute value: Message type: ICRQ */
+
+  /* AVP - Assign session ID */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_SESSIONID, p); /* Attribute type: Session ID */
+  PUTSHORT(l2tp->remote_session_id, p); /* Attribute value: Session ID */
+
+  /* AVP - Call Serial Number */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_CALLSERIALNUMBER, p); /* Attribute type: Serial number */
+  serialnumber = magic();
+  PUTLONG(serialnumber, p); /* Attribute value: Serial number */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+/* Complete tunnel establishment */
+static err_t pppol2tp_send_iccn(pppol2tp_pcb *l2tp, u16_t ns) {
+  struct pbuf *pb;
+  u8_t *p;
+  u16_t len;
+
+  /* calculate UDP packet length */
+  len = 12 +8 +10 +10;
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pb == NULL) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  /* L2TP control header */
+  PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p);
+  PUTSHORT(len, p); /* Length */
+  PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */
+  PUTSHORT(l2tp->source_session_id, p); /* Session Id */
+  PUTSHORT(ns, p); /* NS Sequence number - to peer */
+  PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */
+
+  /* AVP - Message type */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */
+  PUTSHORT(PPPOL2TP_MESSAGETYPE_ICCN, p); /* Attribute value: Message type: ICCN */
+
+  /* AVP - Framing type */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_FRAMINGTYPE, p); /* Attribute type: Framing type */
+  PUTLONG(PPPOL2TP_FRAMINGTYPE, p); /* Attribute value: Framing type */
+
+  /* AVP - TX Connect speed */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_TXCONNECTSPEED, p); /* Attribute type: TX Connect speed */
+  PUTLONG(PPPOL2TP_TXCONNECTSPEED, p); /* Attribute value: TX Connect speed */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+/* Send a ZLB ACK packet */
+static err_t pppol2tp_send_zlb(pppol2tp_pcb *l2tp, u16_t ns, u16_t nr) {
+  struct pbuf *pb;
+  u8_t *p;
+  u16_t len;
+
+  /* calculate UDP packet length */
+  len = 12;
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pb == NULL) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  /* L2TP control header */
+  PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p);
+  PUTSHORT(len, p); /* Length */
+  PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */
+  PUTSHORT(0, p); /* Session Id */
+  PUTSHORT(ns, p); /* NS Sequence number - to peer */
+  PUTSHORT(nr, p); /* NR Sequence number - expected for peer */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+/* Send a StopCCN packet */
+static err_t pppol2tp_send_stopccn(pppol2tp_pcb *l2tp, u16_t ns) {
+  struct pbuf *pb;
+  u8_t *p;
+  u16_t len;
+
+  /* calculate UDP packet length */
+  len = 12 +8 +8 +8;
+
+  /* allocate a buffer */
+  pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pb == NULL) {
+    return ERR_MEM;
+  }
+  LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len);
+
+  p = (u8_t*)pb->payload;
+  /* fill in pkt */
+  /* L2TP control header */
+  PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p);
+  PUTSHORT(len, p); /* Length */
+  PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */
+  PUTSHORT(0, p); /* Session Id */
+  PUTSHORT(ns, p); /* NS Sequence number - to peer */
+  PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */
+
+  /* AVP - Message type */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */
+  PUTSHORT(PPPOL2TP_MESSAGETYPE_STOPCCN, p); /* Attribute value: Message type: StopCCN */
+
+  /* AVP - Assign tunnel ID */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_TUNNELID, p); /* Attribute type: Tunnel ID */
+  PUTSHORT(l2tp->remote_tunnel_id, p); /* Attribute value: Tunnel ID */
+
+  /* AVP - Result code */
+  PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */
+  PUTSHORT(0, p); /* Vendor ID */
+  PUTSHORT(PPPOL2TP_AVPTYPE_RESULTCODE, p); /* Attribute type: Result code */
+  PUTSHORT(PPPOL2TP_RESULTCODE, p); /* Attribute value: Result code */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+static err_t pppol2tp_xmit(pppol2tp_pcb *l2tp, struct pbuf *pb) {
+  u8_t *p;
+
+  /* make room for L2TP header - should not fail */
+  if (pbuf_add_header(pb, PPPOL2TP_OUTPUT_DATA_HEADER_LEN) != 0) {
+    /* bail out */
+    PPPDEBUG(LOG_ERR, ("pppol2tp: pppol2tp_pcb: could not allocate room for L2TP header\n"));
+    LINK_STATS_INC(link.lenerr);
+    pbuf_free(pb);
+    return ERR_BUF;
+  }
+
+  p = (u8_t*)pb->payload;
+  PUTSHORT(PPPOL2TP_HEADERFLAG_DATA_MANDATORY, p);
+  PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */
+  PUTSHORT(l2tp->source_session_id, p); /* Session Id */
+
+  return pppol2tp_udp_send(l2tp, pb);
+}
+
+static err_t pppol2tp_udp_send(pppol2tp_pcb *l2tp, struct pbuf *pb) {
+  err_t err;
+  if (l2tp->netif) {
+    err = udp_sendto_if(l2tp->udp, pb, &l2tp->remote_ip, l2tp->tunnel_port, l2tp->netif);
+  } else {
+    err = udp_sendto(l2tp->udp, pb, &l2tp->remote_ip, l2tp->tunnel_port);
+  }
+  pbuf_free(pb);
+  return err;
+}
+
+#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppos.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppos.c
new file mode 100644
index 000000000..c2fc6fae3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/pppos.c
@@ -0,0 +1,895 @@
+/**
+ * @file
+ * Network Point to Point Protocol over Serial file.
+ *
+ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include <string.h>
+
+#include "lwip/arch.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/memp.h"
+#include "lwip/netif.h"
+#include "lwip/snmp.h"
+#include "lwip/priv/tcpip_priv.h"
+#include "lwip/api.h"
+#include "lwip/ip4.h" /* for ip4_input() */
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/pppos.h"
+#include "netif/ppp/vj.h"
+
+/* Memory pool */
+LWIP_MEMPOOL_DECLARE(PPPOS_PCB, MEMP_NUM_PPPOS_INTERFACES, sizeof(pppos_pcb), "PPPOS_PCB")
+
+/* callbacks called from PPP core */
+static err_t pppos_write(ppp_pcb *ppp, void *ctx, struct pbuf *p);
+static err_t pppos_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *pb, u16_t protocol);
+static void pppos_connect(ppp_pcb *ppp, void *ctx);
+#if PPP_SERVER
+static void pppos_listen(ppp_pcb *ppp, void *ctx);
+#endif /* PPP_SERVER */
+static void pppos_disconnect(ppp_pcb *ppp, void *ctx);
+static err_t pppos_destroy(ppp_pcb *ppp, void *ctx);
+static void pppos_send_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp);
+static void pppos_recv_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp);
+
+/* Prototypes for procedures local to this file. */
+#if PPP_INPROC_IRQ_SAFE
+static void pppos_input_callback(void *arg);
+#endif /* PPP_INPROC_IRQ_SAFE */
+static void pppos_input_free_current_packet(pppos_pcb *pppos);
+static void pppos_input_drop(pppos_pcb *pppos);
+static err_t pppos_output_append(pppos_pcb *pppos, err_t err, struct pbuf *nb, u8_t c, u8_t accm, u16_t *fcs);
+static err_t pppos_output_last(pppos_pcb *pppos, err_t err, struct pbuf *nb, u16_t *fcs);
+
+/* Callbacks structure for PPP core */
+static const struct link_callbacks pppos_callbacks = {
+  pppos_connect,
+#if PPP_SERVER
+  pppos_listen,
+#endif /* PPP_SERVER */
+  pppos_disconnect,
+  pppos_destroy,
+  pppos_write,
+  pppos_netif_output,
+  pppos_send_config,
+  pppos_recv_config
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & 1 << (c & 0x07))
+
+#if PPP_FCS_TABLE
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u16_t fcstab[256] = {
+  0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+  0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+  0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+  0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+  0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+  0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+  0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+  0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+  0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+  0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+  0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+  0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+  0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+  0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+  0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+  0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+  0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+  0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+  0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+  0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+  0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+  0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+  0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+  0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+  0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+  0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+  0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+  0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+  0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+  0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+  0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+  0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+#else /* PPP_FCS_TABLE */
+/* The HDLC polynomial: X**0 + X**5 + X**12 + X**16 (0x8408) */
+#define PPP_FCS_POLYNOMIAL 0x8408
+static u16_t
+ppp_get_fcs(u8_t byte)
+{
+  unsigned int octet;
+  int bit;
+  octet = byte;
+  for (bit = 8; bit-- > 0; ) {
+    octet = (octet & 0x01) ? ((octet >> 1) ^ PPP_FCS_POLYNOMIAL) : (octet >> 1);
+  }
+  return octet & 0xffff;
+}
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ ppp_get_fcs(((fcs) ^ (c)) & 0xff))
+#endif /* PPP_FCS_TABLE */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS     0xffff  /* Initial FCS value */
+#define PPP_GOODFCS     0xf0b8  /* Good final FCS value */
+
+#if PPP_INPROC_IRQ_SAFE
+#define PPPOS_DECL_PROTECT(lev) SYS_ARCH_DECL_PROTECT(lev)
+#define PPPOS_PROTECT(lev) SYS_ARCH_PROTECT(lev)
+#define PPPOS_UNPROTECT(lev) SYS_ARCH_UNPROTECT(lev)
+#else
+#define PPPOS_DECL_PROTECT(lev)
+#define PPPOS_PROTECT(lev)
+#define PPPOS_UNPROTECT(lev)
+#endif /* PPP_INPROC_IRQ_SAFE */
+
+
+/*
+ * Create a new PPP connection using the given serial I/O device.
+ *
+ * Return 0 on success, an error code on failure.
+ */
+ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb,
+       ppp_link_status_cb_fn link_status_cb, void *ctx_cb)
+{
+  pppos_pcb *pppos;
+  ppp_pcb *ppp;
+  LWIP_ASSERT_CORE_LOCKED();
+
+  pppos = (pppos_pcb *)LWIP_MEMPOOL_ALLOC(PPPOS_PCB);
+  if (pppos == NULL) {
+    return NULL;
+  }
+
+  ppp = ppp_new(pppif, &pppos_callbacks, pppos, link_status_cb, ctx_cb);
+  if (ppp == NULL) {
+    LWIP_MEMPOOL_FREE(PPPOS_PCB, pppos);
+    return NULL;
+  }
+
+  memset(pppos, 0, sizeof(pppos_pcb));
+  pppos->ppp = ppp;
+  pppos->output_cb = output_cb;
+  return ppp;
+}
+
+/* Called by PPP core */
+static err_t
+pppos_write(ppp_pcb *ppp, void *ctx, struct pbuf *p)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  u8_t *s;
+  struct pbuf *nb;
+  u16_t n;
+  u16_t fcs_out;
+  err_t err;
+  LWIP_UNUSED_ARG(ppp);
+
+  /* Grab an output buffer. Using PBUF_POOL here for tx is ok since the pbuf
+     gets freed by 'pppos_output_last' before this function returns and thus
+     cannot starve rx. */
+  nb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (nb == NULL) {
+    PPPDEBUG(LOG_WARNING, ("pppos_write[%d]: alloc fail\n", ppp->netif->num));
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    pbuf_free(p);
+    return ERR_MEM;
+  }
+
+  /* Set nb->tot_len to actual payload length */
+  nb->tot_len = p->len;
+
+  /* If the link has been idle, we'll send a fresh flag character to
+   * flush any noise. */
+  err = ERR_OK;
+  if ((Milliseconds() - pppos->last_xmit) >= PPP_MAXIDLEFLAG) {
+    err = pppos_output_append(pppos, err,  nb, PPP_FLAG, 0, NULL);
+  }
+
+  /* Load output buffer. */
+  fcs_out = PPP_INITFCS;
+  s = (u8_t*)p->payload;
+  n = p->len;
+  while (n-- > 0) {
+    err = pppos_output_append(pppos, err,  nb, *s++, 1, &fcs_out);
+  }
+
+  err = pppos_output_last(pppos, err, nb, &fcs_out);
+  if (err == ERR_OK) {
+    PPPDEBUG(LOG_INFO, ("pppos_write[%d]: len=%d\n", ppp->netif->num, p->len));
+  } else {
+    PPPDEBUG(LOG_WARNING, ("pppos_write[%d]: output failed len=%d\n", ppp->netif->num, p->len));
+  }
+  pbuf_free(p);
+  return err;
+}
+
+/* Called by PPP core */
+static err_t
+pppos_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *pb, u16_t protocol)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  struct pbuf *nb, *p;
+  u16_t fcs_out;
+  err_t err;
+  LWIP_UNUSED_ARG(ppp);
+
+  /* Grab an output buffer. Using PBUF_POOL here for tx is ok since the pbuf
+     gets freed by 'pppos_output_last' before this function returns and thus
+     cannot starve rx. */
+  nb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+  if (nb == NULL) {
+    PPPDEBUG(LOG_WARNING, ("pppos_netif_output[%d]: alloc fail\n", ppp->netif->num));
+    LINK_STATS_INC(link.memerr);
+    LINK_STATS_INC(link.drop);
+    MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+    return ERR_MEM;
+  }
+
+  /* Set nb->tot_len to actual payload length */
+  nb->tot_len = pb->tot_len;
+
+  /* If the link has been idle, we'll send a fresh flag character to
+   * flush any noise. */
+  err = ERR_OK;
+  if ((Milliseconds() - pppos->last_xmit) >= PPP_MAXIDLEFLAG) {
+    err = pppos_output_append(pppos, err,  nb, PPP_FLAG, 0, NULL);
+  }
+
+  fcs_out = PPP_INITFCS;
+  if (!pppos->accomp) {
+    err = pppos_output_append(pppos, err,  nb, PPP_ALLSTATIONS, 1, &fcs_out);
+    err = pppos_output_append(pppos, err,  nb, PPP_UI, 1, &fcs_out);
+  }
+  if (!pppos->pcomp || protocol > 0xFF) {
+    err = pppos_output_append(pppos, err,  nb, (protocol >> 8) & 0xFF, 1, &fcs_out);
+  }
+  err = pppos_output_append(pppos, err,  nb, protocol & 0xFF, 1, &fcs_out);
+
+  /* Load packet. */
+  for(p = pb; p; p = p->next) {
+    u16_t n = p->len;
+    u8_t *s = (u8_t*)p->payload;
+
+    while (n-- > 0) {
+      err = pppos_output_append(pppos, err,  nb, *s++, 1, &fcs_out);
+    }
+  }
+
+  err = pppos_output_last(pppos, err, nb, &fcs_out);
+  if (err == ERR_OK) {
+    PPPDEBUG(LOG_INFO, ("pppos_netif_output[%d]: proto=0x%"X16_F", len = %d\n", ppp->netif->num, protocol, pb->tot_len));
+  } else {
+    PPPDEBUG(LOG_WARNING, ("pppos_netif_output[%d]: output failed proto=0x%"X16_F", len = %d\n", ppp->netif->num, protocol, pb->tot_len));
+  }
+  return err;
+}
+
+static void
+pppos_connect(ppp_pcb *ppp, void *ctx)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  PPPOS_DECL_PROTECT(lev);
+
+#if PPP_INPROC_IRQ_SAFE
+  /* input pbuf left over from last session? */
+  pppos_input_free_current_packet(pppos);
+#endif /* PPP_INPROC_IRQ_SAFE */
+
+  /* reset PPPoS control block to its initial state */
+  memset(&pppos->last_xmit, 0, sizeof(pppos_pcb) - offsetof(pppos_pcb, last_xmit));
+
+  /*
+   * Default the in and out accm so that escape and flag characters
+   * are always escaped.
+   */
+  pppos->in_accm[15] = 0x60; /* no need to protect since RX is not running */
+  pppos->out_accm[15] = 0x60;
+  PPPOS_PROTECT(lev);
+  pppos->open = 1;
+  PPPOS_UNPROTECT(lev);
+
+  /*
+   * Start the connection and handle incoming events (packet or timeout).
+   */
+  PPPDEBUG(LOG_INFO, ("pppos_connect: unit %d: connecting\n", ppp->netif->num));
+  ppp_start(ppp); /* notify upper layers */
+}
+
+#if PPP_SERVER
+static void
+pppos_listen(ppp_pcb *ppp, void *ctx)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  PPPOS_DECL_PROTECT(lev);
+
+#if PPP_INPROC_IRQ_SAFE
+  /* input pbuf left over from last session? */
+  pppos_input_free_current_packet(pppos);
+#endif /* PPP_INPROC_IRQ_SAFE */
+
+  /* reset PPPoS control block to its initial state */
+  memset(&pppos->last_xmit, 0, sizeof(pppos_pcb) - offsetof(pppos_pcb, last_xmit));
+
+  /*
+   * Default the in and out accm so that escape and flag characters
+   * are always escaped.
+   */
+  pppos->in_accm[15] = 0x60; /* no need to protect since RX is not running */
+  pppos->out_accm[15] = 0x60;
+  PPPOS_PROTECT(lev);
+  pppos->open = 1;
+  PPPOS_UNPROTECT(lev);
+
+  /*
+   * Wait for something to happen.
+   */
+  PPPDEBUG(LOG_INFO, ("pppos_listen: unit %d: listening\n", ppp->netif->num));
+  ppp_start(ppp); /* notify upper layers */
+}
+#endif /* PPP_SERVER */
+
+static void
+pppos_disconnect(ppp_pcb *ppp, void *ctx)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  PPPOS_DECL_PROTECT(lev);
+
+  PPPOS_PROTECT(lev);
+  pppos->open = 0;
+  PPPOS_UNPROTECT(lev);
+
+  /* If PPP_INPROC_IRQ_SAFE is used we cannot call
+   * pppos_input_free_current_packet() here because
+   * rx IRQ might still call pppos_input().
+   */
+#if !PPP_INPROC_IRQ_SAFE
+  /* input pbuf left ? */
+  pppos_input_free_current_packet(pppos);
+#endif /* !PPP_INPROC_IRQ_SAFE */
+
+  ppp_link_end(ppp); /* notify upper layers */
+}
+
+static err_t
+pppos_destroy(ppp_pcb *ppp, void *ctx)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  LWIP_UNUSED_ARG(ppp);
+
+#if PPP_INPROC_IRQ_SAFE
+  /* input pbuf left ? */
+  pppos_input_free_current_packet(pppos);
+#endif /* PPP_INPROC_IRQ_SAFE */
+
+  LWIP_MEMPOOL_FREE(PPPOS_PCB, pppos);
+  return ERR_OK;
+}
+
+#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
+/** Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread.
+ *
+ * This is one of the only functions that may be called outside of the TCPIP thread!
+ *
+ * @param ppp PPP descriptor index, returned by pppos_create()
+ * @param s received data
+ * @param l length of received data
+ */
+err_t
+pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l)
+{
+  struct pbuf *p;
+  err_t err;
+
+  p = pbuf_alloc(PBUF_RAW, l, PBUF_POOL);
+  if (!p) {
+    return ERR_MEM;
+  }
+  pbuf_take(p, s, l);
+
+  err = tcpip_inpkt(p, ppp_netif(ppp), pppos_input_sys);
+  if (err != ERR_OK) {
+     pbuf_free(p);
+  }
+  return err;
+}
+
+/* called from TCPIP thread */
+err_t pppos_input_sys(struct pbuf *p, struct netif *inp) {
+  ppp_pcb *ppp = (ppp_pcb*)inp->state;
+  struct pbuf *n;
+  LWIP_ASSERT_CORE_LOCKED();
+
+  for (n = p; n; n = n->next) {
+    pppos_input(ppp, (u8_t*)n->payload, n->len);
+  }
+  pbuf_free(p);
+  return ERR_OK;
+}
+#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
+
+/** PPPoS input helper struct, must be packed since it is stored
+ * to pbuf->payload, which might be unaligned. */
+#if PPP_INPROC_IRQ_SAFE
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct pppos_input_header {
+  PACK_STRUCT_FIELD(ppp_pcb *ppp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+#endif /* PPP_INPROC_IRQ_SAFE */
+
+/** Pass received raw characters to PPPoS to be decoded.
+ *
+ * @param ppp PPP descriptor index, returned by pppos_create()
+ * @param s received data
+ * @param l length of received data
+ */
+void
+pppos_input(ppp_pcb *ppp, u8_t *s, int l)
+{
+  pppos_pcb *pppos = (pppos_pcb *)ppp->link_ctx_cb;
+  struct pbuf *next_pbuf;
+  u8_t cur_char;
+  u8_t escaped;
+  PPPOS_DECL_PROTECT(lev);
+#if !PPP_INPROC_IRQ_SAFE
+  LWIP_ASSERT_CORE_LOCKED();
+#endif
+
+  PPPDEBUG(LOG_DEBUG, ("pppos_input[%d]: got %d bytes\n", ppp->netif->num, l));
+  while (l-- > 0) {
+    cur_char = *s++;
+
+    PPPOS_PROTECT(lev);
+    /* ppp_input can disconnect the interface, we need to abort to prevent a memory
+     * leak if there are remaining bytes because pppos_connect and pppos_listen
+     * functions expect input buffer to be free. Furthermore there are no real
+     * reason to continue reading bytes if we are disconnected.
+     */
+    if (!pppos->open) {
+      PPPOS_UNPROTECT(lev);
+      return;
+    }
+    escaped = ESCAPE_P(pppos->in_accm, cur_char);
+    PPPOS_UNPROTECT(lev);
+    /* Handle special characters. */
+    if (escaped) {
+      /* Check for escape sequences. */
+      /* XXX Note that this does not handle an escaped 0x5d character which
+       * would appear as an escape character.  Since this is an ASCII ']'
+       * and there is no reason that I know of to escape it, I won't complicate
+       * the code to handle this case. GLL */
+      if (cur_char == PPP_ESCAPE) {
+        pppos->in_escaped = 1;
+      /* Check for the flag character. */
+      } else if (cur_char == PPP_FLAG) {
+        /* If this is just an extra flag character, ignore it. */
+        if (pppos->in_state <= PDADDRESS) {
+          /* ignore it */;
+        /* If we haven't received the packet header, drop what has come in. */
+        } else if (pppos->in_state < PDDATA) {
+          PPPDEBUG(LOG_WARNING,
+                   ("pppos_input[%d]: Dropping incomplete packet %d\n",
+                    ppp->netif->num, pppos->in_state));
+          LINK_STATS_INC(link.lenerr);
+          pppos_input_drop(pppos);
+        /* If the fcs is invalid, drop the packet. */
+        } else if (pppos->in_fcs != PPP_GOODFCS) {
+          PPPDEBUG(LOG_INFO,
+                   ("pppos_input[%d]: Dropping bad fcs 0x%"X16_F" proto=0x%"X16_F"\n",
+                    ppp->netif->num, pppos->in_fcs, pppos->in_protocol));
+          /* Note: If you get lots of these, check for UART frame errors or try different baud rate */
+          LINK_STATS_INC(link.chkerr);
+          pppos_input_drop(pppos);
+        /* Otherwise it's a good packet so pass it on. */
+        } else {
+          struct pbuf *inp;
+          /* Trim off the checksum. */
+          if(pppos->in_tail->len > 2) {
+            pppos->in_tail->len -= 2;
+
+            pppos->in_tail->tot_len = pppos->in_tail->len;
+            if (pppos->in_tail != pppos->in_head) {
+              pbuf_cat(pppos->in_head, pppos->in_tail);
+            }
+          } else {
+            pppos->in_tail->tot_len = pppos->in_tail->len;
+            if (pppos->in_tail != pppos->in_head) {
+              pbuf_cat(pppos->in_head, pppos->in_tail);
+            }
+
+            pbuf_realloc(pppos->in_head, pppos->in_head->tot_len - 2);
+          }
+
+          /* Dispatch the packet thereby consuming it. */
+          inp = pppos->in_head;
+          /* Packet consumed, release our references. */
+          pppos->in_head = NULL;
+          pppos->in_tail = NULL;
+#if IP_FORWARD || LWIP_IPV6_FORWARD
+          /* hide the room for Ethernet forwarding header */
+          pbuf_remove_header(inp, PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN);
+#endif /* IP_FORWARD || LWIP_IPV6_FORWARD */
+#if PPP_INPROC_IRQ_SAFE
+          if(tcpip_try_callback(pppos_input_callback, inp) != ERR_OK) {
+            PPPDEBUG(LOG_ERR, ("pppos_input[%d]: tcpip_callback() failed, dropping packet\n", ppp->netif->num));
+            pbuf_free(inp);
+            LINK_STATS_INC(link.drop);
+            MIB2_STATS_NETIF_INC(ppp->netif, ifindiscards);
+          }
+#else /* PPP_INPROC_IRQ_SAFE */
+          ppp_input(ppp, inp);
+#endif /* PPP_INPROC_IRQ_SAFE */
+        }
+
+        /* Prepare for a new packet. */
+        pppos->in_fcs = PPP_INITFCS;
+        pppos->in_state = PDADDRESS;
+        pppos->in_escaped = 0;
+      /* Other characters are usually control characters that may have
+       * been inserted by the physical layer so here we just drop them. */
+      } else {
+        PPPDEBUG(LOG_WARNING,
+                 ("pppos_input[%d]: Dropping ACCM char <%d>\n", ppp->netif->num, cur_char));
+      }
+    /* Process other characters. */
+    } else {
+      /* Unencode escaped characters. */
+      if (pppos->in_escaped) {
+        pppos->in_escaped = 0;
+        cur_char ^= PPP_TRANS;
+      }
+
+      /* Process character relative to current state. */
+      switch(pppos->in_state) {
+        case PDIDLE:                    /* Idle state - waiting. */
+          /* Drop the character if it's not 0xff
+           * we would have processed a flag character above. */
+          if (cur_char != PPP_ALLSTATIONS) {
+            break;
+          }
+          /* no break */
+          /* Fall through */
+
+        case PDSTART:                   /* Process start flag. */
+          /* Prepare for a new packet. */
+          pppos->in_fcs = PPP_INITFCS;
+          /* no break */
+          /* Fall through */
+
+        case PDADDRESS:                 /* Process address field. */
+          if (cur_char == PPP_ALLSTATIONS) {
+            pppos->in_state = PDCONTROL;
+            break;
+          }
+          /* no break */
+
+          /* Else assume compressed address and control fields so
+           * fall through to get the protocol... */
+          /* Fall through */
+        case PDCONTROL:                 /* Process control field. */
+          /* If we don't get a valid control code, restart. */
+          if (cur_char == PPP_UI) {
+            pppos->in_state = PDPROTOCOL1;
+            break;
+          }
+          /* no break */
+
+#if 0
+          else {
+            PPPDEBUG(LOG_WARNING,
+                     ("pppos_input[%d]: Invalid control <%d>\n", ppp->netif->num, cur_char));
+            pppos->in_state = PDSTART;
+          }
+#endif
+          /* Fall through */
+
+      case PDPROTOCOL1:               /* Process protocol field 1. */
+          /* If the lower bit is set, this is the end of the protocol
+           * field. */
+          if (cur_char & 1) {
+            pppos->in_protocol = cur_char;
+            pppos->in_state = PDDATA;
+          } else {
+            pppos->in_protocol = (u16_t)cur_char << 8;
+            pppos->in_state = PDPROTOCOL2;
+          }
+          break;
+        case PDPROTOCOL2:               /* Process protocol field 2. */
+          pppos->in_protocol |= cur_char;
+          pppos->in_state = PDDATA;
+          break;
+        case PDDATA:                    /* Process data byte. */
+          /* Make space to receive processed data. */
+          if (pppos->in_tail == NULL || pppos->in_tail->len == PBUF_POOL_BUFSIZE) {
+            u16_t pbuf_alloc_len;
+            if (pppos->in_tail != NULL) {
+              pppos->in_tail->tot_len = pppos->in_tail->len;
+              if (pppos->in_tail != pppos->in_head) {
+                pbuf_cat(pppos->in_head, pppos->in_tail);
+                /* give up the in_tail reference now */
+                pppos->in_tail = NULL;
+              }
+            }
+            /* If we haven't started a packet, we need a packet header. */
+            pbuf_alloc_len = 0;
+#if IP_FORWARD || LWIP_IPV6_FORWARD
+            /* If IP forwarding is enabled we are reserving PBUF_LINK_ENCAPSULATION_HLEN
+             * + PBUF_LINK_HLEN bytes so the packet is being allocated with enough header
+             * space to be forwarded (to Ethernet for example).
+             */
+            if (pppos->in_head == NULL) {
+              pbuf_alloc_len = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN;
+            }
+#endif /* IP_FORWARD || LWIP_IPV6_FORWARD */
+            next_pbuf = pbuf_alloc(PBUF_RAW, pbuf_alloc_len, PBUF_POOL);
+            if (next_pbuf == NULL) {
+              /* No free buffers.  Drop the input packet and let the
+               * higher layers deal with it.  Continue processing
+               * the received pbuf chain in case a new packet starts. */
+              PPPDEBUG(LOG_ERR, ("pppos_input[%d]: NO FREE PBUFS!\n", ppp->netif->num));
+              LINK_STATS_INC(link.memerr);
+              pppos_input_drop(pppos);
+              pppos->in_state = PDSTART;  /* Wait for flag sequence. */
+              break;
+            }
+            if (pppos->in_head == NULL) {
+              u8_t *payload = ((u8_t*)next_pbuf->payload) + pbuf_alloc_len;
+#if PPP_INPROC_IRQ_SAFE
+              ((struct pppos_input_header*)payload)->ppp = ppp;
+              payload += sizeof(struct pppos_input_header);
+              next_pbuf->len += sizeof(struct pppos_input_header);
+#endif /* PPP_INPROC_IRQ_SAFE */
+              next_pbuf->len += sizeof(pppos->in_protocol);
+              *(payload++) = pppos->in_protocol >> 8;
+              *(payload) = pppos->in_protocol & 0xFF;
+              pppos->in_head = next_pbuf;
+            }
+            pppos->in_tail = next_pbuf;
+          }
+          /* Load character into buffer. */
+          ((u8_t*)pppos->in_tail->payload)[pppos->in_tail->len++] = cur_char;
+          break;
+        default:
+          break;
+      }
+
+      /* update the frame check sequence number. */
+      pppos->in_fcs = PPP_FCS(pppos->in_fcs, cur_char);
+    }
+  } /* while (l-- > 0), all bytes processed */
+}
+
+#if PPP_INPROC_IRQ_SAFE
+/* PPPoS input callback using one input pointer
+ */
+static void pppos_input_callback(void *arg) {
+  struct pbuf *pb = (struct pbuf*)arg;
+  ppp_pcb *ppp;
+
+  ppp = ((struct pppos_input_header*)pb->payload)->ppp;
+  if(pbuf_remove_header(pb, sizeof(struct pppos_input_header))) {
+    LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+    goto drop;
+  }
+
+  /* Dispatch the packet thereby consuming it. */
+  ppp_input(ppp, pb);
+  return;
+
+drop:
+  LINK_STATS_INC(link.drop);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifindiscards);
+  pbuf_free(pb);
+}
+#endif /* PPP_INPROC_IRQ_SAFE */
+
+static void
+pppos_send_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp)
+{
+  int i;
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  LWIP_UNUSED_ARG(ppp);
+
+  pppos->pcomp = pcomp;
+  pppos->accomp = accomp;
+
+  /* Load the ACCM bits for the 32 control codes. */
+  for (i = 0; i < 32/8; i++) {
+    pppos->out_accm[i] = (u8_t)((accm >> (8 * i)) & 0xFF);
+  }
+
+  PPPDEBUG(LOG_INFO, ("pppos_send_config[%d]: out_accm=%X %X %X %X\n",
+            pppos->ppp->netif->num,
+            pppos->out_accm[0], pppos->out_accm[1], pppos->out_accm[2], pppos->out_accm[3]));
+}
+
+static void
+pppos_recv_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp)
+{
+  int i;
+  pppos_pcb *pppos = (pppos_pcb *)ctx;
+  PPPOS_DECL_PROTECT(lev);
+  LWIP_UNUSED_ARG(ppp);
+  LWIP_UNUSED_ARG(pcomp);
+  LWIP_UNUSED_ARG(accomp);
+
+  /* Load the ACCM bits for the 32 control codes. */
+  PPPOS_PROTECT(lev);
+  for (i = 0; i < 32 / 8; i++) {
+    pppos->in_accm[i] = (u8_t)(accm >> (i * 8));
+  }
+  PPPOS_UNPROTECT(lev);
+
+  PPPDEBUG(LOG_INFO, ("pppos_recv_config[%d]: in_accm=%X %X %X %X\n",
+            pppos->ppp->netif->num,
+            pppos->in_accm[0], pppos->in_accm[1], pppos->in_accm[2], pppos->in_accm[3]));
+}
+
+/*
+ * Drop the input packet.
+ */
+static void
+pppos_input_free_current_packet(pppos_pcb *pppos)
+{
+  if (pppos->in_head != NULL) {
+    if (pppos->in_tail && (pppos->in_tail != pppos->in_head)) {
+      pbuf_free(pppos->in_tail);
+    }
+    pbuf_free(pppos->in_head);
+    pppos->in_head = NULL;
+  }
+  pppos->in_tail = NULL;
+}
+
+/*
+ * Drop the input packet and increase error counters.
+ */
+static void
+pppos_input_drop(pppos_pcb *pppos)
+{
+  if (pppos->in_head != NULL) {
+#if 0
+    PPPDEBUG(LOG_INFO, ("pppos_input_drop: %d:%.*H\n", pppos->in_head->len, min(60, pppos->in_head->len * 2), pppos->in_head->payload));
+#endif
+    PPPDEBUG(LOG_INFO, ("pppos_input_drop: pbuf len=%d, addr %p\n", pppos->in_head->len, (void*)pppos->in_head));
+  }
+  pppos_input_free_current_packet(pppos);
+#if VJ_SUPPORT
+  vj_uncompress_err(&pppos->ppp->vj_comp);
+#endif /* VJ_SUPPORT */
+
+  LINK_STATS_INC(link.drop);
+  MIB2_STATS_NETIF_INC(pppos->ppp->netif, ifindiscards);
+}
+
+/*
+ * pppos_output_append - append given character to end of given pbuf.
+ * If out_accm is not 0 and the character needs to be escaped, do so.
+ * If pbuf is full, send the pbuf and reuse it.
+ * Return the current pbuf.
+ */
+static err_t
+pppos_output_append(pppos_pcb *pppos, err_t err, struct pbuf *nb, u8_t c, u8_t accm, u16_t *fcs)
+{
+  if (err != ERR_OK) {
+    return err;
+  }
+
+  /* Make sure there is room for the character and an escape code.
+   * Sure we don't quite fill the buffer if the character doesn't
+   * get escaped but is one character worth complicating this? */
+  if ((PBUF_POOL_BUFSIZE - nb->len) < 2) {
+    u32_t l = pppos->output_cb(pppos->ppp, (u8_t*)nb->payload, nb->len, pppos->ppp->ctx_cb);
+    if (l != nb->len) {
+      return ERR_IF;
+    }
+    nb->len = 0;
+  }
+
+  /* Update FCS before checking for special characters. */
+  if (fcs) {
+    *fcs = PPP_FCS(*fcs, c);
+  }
+
+  /* Copy to output buffer escaping special characters. */
+  if (accm && ESCAPE_P(pppos->out_accm, c)) {
+    *((u8_t*)nb->payload + nb->len++) = PPP_ESCAPE;
+    *((u8_t*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+  } else {
+    *((u8_t*)nb->payload + nb->len++) = c;
+  }
+
+  return ERR_OK;
+}
+
+static err_t
+pppos_output_last(pppos_pcb *pppos, err_t err, struct pbuf *nb, u16_t *fcs)
+{
+  ppp_pcb *ppp = pppos->ppp;
+
+  /* Add FCS and trailing flag. */
+  err = pppos_output_append(pppos, err,  nb, ~(*fcs) & 0xFF, 1, NULL);
+  err = pppos_output_append(pppos, err,  nb, (~(*fcs) >> 8) & 0xFF, 1, NULL);
+  err = pppos_output_append(pppos, err,  nb, PPP_FLAG, 0, NULL);
+
+  if (err != ERR_OK) {
+    goto failed;
+  }
+
+  /* Send remaining buffer if not empty */
+  if (nb->len > 0) {
+    u32_t l = pppos->output_cb(ppp, (u8_t*)nb->payload, nb->len, ppp->ctx_cb);
+    if (l != nb->len) {
+      err = ERR_IF;
+      goto failed;
+    }
+  }
+
+  pppos->last_xmit = Milliseconds();
+  MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, nb->tot_len);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts);
+  LINK_STATS_INC(link.xmit);
+  pbuf_free(nb);
+  return ERR_OK;
+
+failed:
+  pppos->last_xmit = 0; /* prepend PPP_FLAG to next packet */
+  LINK_STATS_INC(link.err);
+  LINK_STATS_INC(link.drop);
+  MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards);
+  pbuf_free(nb);
+  return err;
+}
+
+#endif /* PPP_SUPPORT && PPPOS_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/upap.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/upap.c
new file mode 100644
index 000000000..3b2399dc2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/upap.c
@@ -0,0 +1,677 @@
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * 3. The name "Carnegie Mellon University" must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission. For permission or any legal
+ *    details, please contact
+ *      Office of Technology Transfer
+ *      Carnegie Mellon University
+ *      5000 Forbes Avenue
+ *      Pittsburgh, PA  15213-3890
+ *      (412) 268-4387, fax: (412) 268-7395
+ *      tech-transfer@andrew.cmu.edu
+ *
+ * 4. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Computing Services
+ *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
+ *
+ * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
+ * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && PAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
+
+/*
+ * @todo:
+ */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <string.h>
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/upap.h"
+
+#if PPP_OPTIONS
+/*
+ * Command-line options.
+ */
+static option_t pap_option_list[] = {
+    { "hide-password", o_bool, &hide_password,
+      "Don't output passwords to log", OPT_PRIO | 1 },
+    { "show-password", o_bool, &hide_password,
+      "Show password string in debug log messages", OPT_PRIOSUB | 0 },
+
+    { "pap-restart", o_int, &upap[0].us_timeouttime,
+      "Set retransmit timeout for PAP", OPT_PRIO },
+    { "pap-max-authreq", o_int, &upap[0].us_maxtransmits,
+      "Set max number of transmissions for auth-reqs", OPT_PRIO },
+    { "pap-timeout", o_int, &upap[0].us_reqtimeout,
+      "Set time limit for peer PAP authentication", OPT_PRIO },
+
+    { NULL }
+};
+#endif /* PPP_OPTIONS */
+
+/*
+ * Protocol entry points.
+ */
+static void upap_init(ppp_pcb *pcb);
+static void upap_lowerup(ppp_pcb *pcb);
+static void upap_lowerdown(ppp_pcb *pcb);
+static void upap_input(ppp_pcb *pcb, u_char *inpacket, int l);
+static void upap_protrej(ppp_pcb *pcb);
+#if PRINTPKT_SUPPORT
+static int upap_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg);
+#endif /* PRINTPKT_SUPPORT */
+
+const struct protent pap_protent = {
+    PPP_PAP,
+    upap_init,
+    upap_input,
+    upap_protrej,
+    upap_lowerup,
+    upap_lowerdown,
+    NULL,
+    NULL,
+#if PRINTPKT_SUPPORT
+    upap_printpkt,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_DATAINPUT
+    NULL,
+#endif /* PPP_DATAINPUT */
+#if PRINTPKT_SUPPORT
+    "PAP",
+    NULL,
+#endif /* PRINTPKT_SUPPORT */
+#if PPP_OPTIONS
+    pap_option_list,
+    NULL,
+#endif /* PPP_OPTIONS */
+#if DEMAND_SUPPORT
+    NULL,
+    NULL
+#endif /* DEMAND_SUPPORT */
+};
+
+static void upap_timeout(void *arg);
+#if PPP_SERVER
+static void upap_reqtimeout(void *arg);
+static void upap_rauthreq(ppp_pcb *pcb, u_char *inp, int id, int len);
+#endif /* PPP_SERVER */
+static void upap_rauthack(ppp_pcb *pcb, u_char *inp, int id, int len);
+static void upap_rauthnak(ppp_pcb *pcb, u_char *inp, int id, int len);
+static void upap_sauthreq(ppp_pcb *pcb);
+#if PPP_SERVER
+static void upap_sresp(ppp_pcb *pcb, u_char code, u_char id, const char *msg, int msglen);
+#endif /* PPP_SERVER */
+
+
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void upap_init(ppp_pcb *pcb) {
+    pcb->upap.us_user = NULL;
+    pcb->upap.us_userlen = 0;
+    pcb->upap.us_passwd = NULL;
+    pcb->upap.us_passwdlen = 0;
+    pcb->upap.us_clientstate = UPAPCS_INITIAL;
+#if PPP_SERVER
+    pcb->upap.us_serverstate = UPAPSS_INITIAL;
+#endif /* PPP_SERVER */
+    pcb->upap.us_id = 0;
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password) {
+
+    if(!user || !password)
+        return;
+
+    /* Save the username and password we're given */
+    pcb->upap.us_user = user;
+    pcb->upap.us_userlen = (u8_t)LWIP_MIN(strlen(user), 0xff);
+    pcb->upap.us_passwd = password;
+    pcb->upap.us_passwdlen = (u8_t)LWIP_MIN(strlen(password), 0xff);
+    pcb->upap.us_transmits = 0;
+
+    /* Lower layer up yet? */
+    if (pcb->upap.us_clientstate == UPAPCS_INITIAL ||
+	pcb->upap.us_clientstate == UPAPCS_PENDING) {
+	pcb->upap.us_clientstate = UPAPCS_PENDING;
+	return;
+    }
+
+    upap_sauthreq(pcb);		/* Start protocol */
+}
+
+#if PPP_SERVER
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void upap_authpeer(ppp_pcb *pcb) {
+
+    /* Lower layer up yet? */
+    if (pcb->upap.us_serverstate == UPAPSS_INITIAL ||
+	pcb->upap.us_serverstate == UPAPSS_PENDING) {
+	pcb->upap.us_serverstate = UPAPSS_PENDING;
+	return;
+    }
+
+    pcb->upap.us_serverstate = UPAPSS_LISTEN;
+    if (pcb->settings.pap_req_timeout > 0)
+	TIMEOUT(upap_reqtimeout, pcb, pcb->settings.pap_req_timeout);
+}
+#endif /* PPP_SERVER */
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void upap_timeout(void *arg) {
+    ppp_pcb *pcb = (ppp_pcb*)arg;
+
+    if (pcb->upap.us_clientstate != UPAPCS_AUTHREQ)
+	return;
+
+    if (pcb->upap.us_transmits >= pcb->settings.pap_max_transmits) {
+	/* give up in disgust */
+	ppp_error("No response to PAP authenticate-requests");
+	pcb->upap.us_clientstate = UPAPCS_BADAUTH;
+	auth_withpeer_fail(pcb, PPP_PAP);
+	return;
+    }
+
+    upap_sauthreq(pcb);		/* Send Authenticate-Request */
+}
+
+
+#if PPP_SERVER
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void upap_reqtimeout(void *arg) {
+    ppp_pcb *pcb = (ppp_pcb*)arg;
+
+    if (pcb->upap.us_serverstate != UPAPSS_LISTEN)
+	return;			/* huh?? */
+
+    auth_peer_fail(pcb, PPP_PAP);
+    pcb->upap.us_serverstate = UPAPSS_BADAUTH;
+}
+#endif /* PPP_SERVER */
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void upap_lowerup(ppp_pcb *pcb) {
+
+    if (pcb->upap.us_clientstate == UPAPCS_INITIAL)
+	pcb->upap.us_clientstate = UPAPCS_CLOSED;
+    else if (pcb->upap.us_clientstate == UPAPCS_PENDING) {
+	upap_sauthreq(pcb);	/* send an auth-request */
+    }
+
+#if PPP_SERVER
+    if (pcb->upap.us_serverstate == UPAPSS_INITIAL)
+	pcb->upap.us_serverstate = UPAPSS_CLOSED;
+    else if (pcb->upap.us_serverstate == UPAPSS_PENDING) {
+	pcb->upap.us_serverstate = UPAPSS_LISTEN;
+	if (pcb->settings.pap_req_timeout > 0)
+	    TIMEOUT(upap_reqtimeout, pcb, pcb->settings.pap_req_timeout);
+    }
+#endif /* PPP_SERVER */
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void upap_lowerdown(ppp_pcb *pcb) {
+
+    if (pcb->upap.us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
+	UNTIMEOUT(upap_timeout, pcb);		/* Cancel timeout */
+#if PPP_SERVER
+    if (pcb->upap.us_serverstate == UPAPSS_LISTEN && pcb->settings.pap_req_timeout > 0)
+	UNTIMEOUT(upap_reqtimeout, pcb);
+#endif /* PPP_SERVER */
+
+    pcb->upap.us_clientstate = UPAPCS_INITIAL;
+#if PPP_SERVER
+    pcb->upap.us_serverstate = UPAPSS_INITIAL;
+#endif /* PPP_SERVER */
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void upap_protrej(ppp_pcb *pcb) {
+
+    if (pcb->upap.us_clientstate == UPAPCS_AUTHREQ) {
+	ppp_error("PAP authentication failed due to protocol-reject");
+	auth_withpeer_fail(pcb, PPP_PAP);
+    }
+#if PPP_SERVER
+    if (pcb->upap.us_serverstate == UPAPSS_LISTEN) {
+	ppp_error("PAP authentication of peer failed (protocol-reject)");
+	auth_peer_fail(pcb, PPP_PAP);
+    }
+#endif /* PPP_SERVER */
+    upap_lowerdown(pcb);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void upap_input(ppp_pcb *pcb, u_char *inpacket, int l) {
+    u_char *inp;
+    u_char code, id;
+    int len;
+
+    /*
+     * Parse header (code, id and length).
+     * If packet too short, drop it.
+     */
+    inp = inpacket;
+    if (l < UPAP_HEADERLEN) {
+	UPAPDEBUG(("pap_input: rcvd short header."));
+	return;
+    }
+    GETCHAR(code, inp);
+    GETCHAR(id, inp);
+    GETSHORT(len, inp);
+    if (len < UPAP_HEADERLEN) {
+	UPAPDEBUG(("pap_input: rcvd illegal length."));
+	return;
+    }
+    if (len > l) {
+	UPAPDEBUG(("pap_input: rcvd short packet."));
+	return;
+    }
+    len -= UPAP_HEADERLEN;
+
+    /*
+     * Action depends on code.
+     */
+    switch (code) {
+    case UPAP_AUTHREQ:
+#if PPP_SERVER
+	upap_rauthreq(pcb, inp, id, len);
+#endif /* PPP_SERVER */
+	break;
+
+    case UPAP_AUTHACK:
+	upap_rauthack(pcb, inp, id, len);
+	break;
+
+    case UPAP_AUTHNAK:
+	upap_rauthnak(pcb, inp, id, len);
+	break;
+
+    default:				/* XXX Need code reject */
+	break;
+    }
+}
+
+#if PPP_SERVER
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void upap_rauthreq(ppp_pcb *pcb, u_char *inp, int id, int len) {
+    u_char ruserlen, rpasswdlen;
+    char *ruser;
+    char *rpasswd;
+    char rhostname[256];
+    int retcode;
+    const char *msg;
+    int msglen;
+
+    if (pcb->upap.us_serverstate < UPAPSS_LISTEN)
+	return;
+
+    /*
+     * If we receive a duplicate authenticate-request, we are
+     * supposed to return the same status as for the first request.
+     */
+    if (pcb->upap.us_serverstate == UPAPSS_OPEN) {
+	upap_sresp(pcb, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
+	return;
+    }
+    if (pcb->upap.us_serverstate == UPAPSS_BADAUTH) {
+	upap_sresp(pcb, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
+	return;
+    }
+
+    /*
+     * Parse user/passwd.
+     */
+    if (len < 1) {
+	UPAPDEBUG(("pap_rauth: rcvd short packet."));
+	return;
+    }
+    GETCHAR(ruserlen, inp);
+    len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+    if (len < 0) {
+	UPAPDEBUG(("pap_rauth: rcvd short packet."));
+	return;
+    }
+    ruser = (char *) inp;
+    INCPTR(ruserlen, inp);
+    GETCHAR(rpasswdlen, inp);
+    if (len < rpasswdlen) {
+	UPAPDEBUG(("pap_rauth: rcvd short packet."));
+	return;
+    }
+
+    rpasswd = (char *) inp;
+
+    /*
+     * Check the username and password given.
+     */
+    retcode = UPAP_AUTHNAK;
+    if (auth_check_passwd(pcb, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen)) {
+      retcode = UPAP_AUTHACK;
+    }
+    BZERO(rpasswd, rpasswdlen);
+
+#if 0 /* UNUSED */
+    /*
+     * Check remote number authorization.  A plugin may have filled in
+     * the remote number or added an allowed number, and rather than
+     * return an authenticate failure, is leaving it for us to verify.
+     */
+    if (retcode == UPAP_AUTHACK) {
+	if (!auth_number()) {
+	    /* We do not want to leak info about the pap result. */
+	    retcode = UPAP_AUTHNAK; /* XXX exit value will be "wrong" */
+	    warn("calling number %q is not authorized", remote_number);
+	}
+    }
+
+    msglen = strlen(msg);
+    if (msglen > 255)
+	msglen = 255;
+#endif /* UNUSED */
+
+    upap_sresp(pcb, retcode, id, msg, msglen);
+
+    /* Null terminate and clean remote name. */
+    ppp_slprintf(rhostname, sizeof(rhostname), "%.*v", ruserlen, ruser);
+
+    if (retcode == UPAP_AUTHACK) {
+	pcb->upap.us_serverstate = UPAPSS_OPEN;
+	ppp_notice("PAP peer authentication succeeded for %q", rhostname);
+	auth_peer_success(pcb, PPP_PAP, 0, ruser, ruserlen);
+    } else {
+	pcb->upap.us_serverstate = UPAPSS_BADAUTH;
+	ppp_warn("PAP peer authentication failed for %q", rhostname);
+	auth_peer_fail(pcb, PPP_PAP);
+    }
+
+    if (pcb->settings.pap_req_timeout > 0)
+	UNTIMEOUT(upap_reqtimeout, pcb);
+}
+#endif /* PPP_SERVER */
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void upap_rauthack(ppp_pcb *pcb, u_char *inp, int id, int len) {
+    u_char msglen;
+    char *msg;
+    LWIP_UNUSED_ARG(id);
+
+    if (pcb->upap.us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+	return;
+
+    /*
+     * Parse message.
+     */
+    if (len < 1) {
+	UPAPDEBUG(("pap_rauthack: ignoring missing msg-length."));
+    } else {
+	GETCHAR(msglen, inp);
+	if (msglen > 0) {
+	    len -= sizeof (u_char);
+	    if (len < msglen) {
+		UPAPDEBUG(("pap_rauthack: rcvd short packet."));
+		return;
+	    }
+	    msg = (char *) inp;
+	    PRINTMSG(msg, msglen);
+	}
+    }
+
+    pcb->upap.us_clientstate = UPAPCS_OPEN;
+
+    auth_withpeer_success(pcb, PPP_PAP, 0);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nak.
+ */
+static void upap_rauthnak(ppp_pcb *pcb, u_char *inp, int id, int len) {
+    u_char msglen;
+    char *msg;
+    LWIP_UNUSED_ARG(id);
+
+    if (pcb->upap.us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+	return;
+
+    /*
+     * Parse message.
+     */
+    if (len < 1) {
+	UPAPDEBUG(("pap_rauthnak: ignoring missing msg-length."));
+    } else {
+	GETCHAR(msglen, inp);
+	if (msglen > 0) {
+	    len -= sizeof (u_char);
+	    if (len < msglen) {
+		UPAPDEBUG(("pap_rauthnak: rcvd short packet."));
+		return;
+	    }
+	    msg = (char *) inp;
+	    PRINTMSG(msg, msglen);
+	}
+    }
+
+    pcb->upap.us_clientstate = UPAPCS_BADAUTH;
+
+    ppp_error("PAP authentication failed");
+    auth_withpeer_fail(pcb, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void upap_sauthreq(ppp_pcb *pcb) {
+    struct pbuf *p;
+    u_char *outp;
+    int outlen;
+
+    outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) +
+	pcb->upap.us_userlen + pcb->upap.us_passwdlen;
+    p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN +outlen), PPP_CTRL_PBUF_TYPE);
+    if(NULL == p)
+        return;
+    if(p->tot_len != p->len) {
+        pbuf_free(p);
+        return;
+    }
+
+    outp = (u_char*)p->payload;
+    MAKEHEADER(outp, PPP_PAP);
+
+    PUTCHAR(UPAP_AUTHREQ, outp);
+    PUTCHAR(++pcb->upap.us_id, outp);
+    PUTSHORT(outlen, outp);
+    PUTCHAR(pcb->upap.us_userlen, outp);
+    MEMCPY(outp, pcb->upap.us_user, pcb->upap.us_userlen);
+    INCPTR(pcb->upap.us_userlen, outp);
+    PUTCHAR(pcb->upap.us_passwdlen, outp);
+    MEMCPY(outp, pcb->upap.us_passwd, pcb->upap.us_passwdlen);
+
+    ppp_write(pcb, p);
+
+    TIMEOUT(upap_timeout, pcb, pcb->settings.pap_timeout_time);
+    ++pcb->upap.us_transmits;
+    pcb->upap.us_clientstate = UPAPCS_AUTHREQ;
+}
+
+#if PPP_SERVER
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void upap_sresp(ppp_pcb *pcb, u_char code, u_char id, const char *msg, int msglen) {
+    struct pbuf *p;
+    u_char *outp;
+    int outlen;
+
+    outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+    p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN +outlen), PPP_CTRL_PBUF_TYPE);
+    if(NULL == p)
+        return;
+    if(p->tot_len != p->len) {
+        pbuf_free(p);
+        return;
+    }
+
+    outp = (u_char*)p->payload;
+    MAKEHEADER(outp, PPP_PAP);
+
+    PUTCHAR(code, outp);
+    PUTCHAR(id, outp);
+    PUTSHORT(outlen, outp);
+    PUTCHAR(msglen, outp);
+    MEMCPY(outp, msg, msglen);
+
+    ppp_write(pcb, p);
+}
+#endif /* PPP_SERVER */
+
+#if PRINTPKT_SUPPORT
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static const char* const upap_codenames[] = {
+    "AuthReq", "AuthAck", "AuthNak"
+};
+
+static int upap_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg) {
+    int code, id, len;
+    int mlen, ulen, wlen;
+    const u_char *user, *pwd, *msg;
+    const u_char *pstart;
+
+    if (plen < UPAP_HEADERLEN)
+	return 0;
+    pstart = p;
+    GETCHAR(code, p);
+    GETCHAR(id, p);
+    GETSHORT(len, p);
+    if (len < UPAP_HEADERLEN || len > plen)
+	return 0;
+
+    if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(upap_codenames))
+	printer(arg, " %s", upap_codenames[code-1]);
+    else
+	printer(arg, " code=0x%x", code);
+    printer(arg, " id=0x%x", id);
+    len -= UPAP_HEADERLEN;
+    switch (code) {
+    case UPAP_AUTHREQ:
+	if (len < 1)
+	    break;
+	ulen = p[0];
+	if (len < ulen + 2)
+	    break;
+	wlen = p[ulen + 1];
+	if (len < ulen + wlen + 2)
+	    break;
+	user = (const u_char *) (p + 1);
+	pwd = (const u_char *) (p + ulen + 2);
+	p += ulen + wlen + 2;
+	len -= ulen + wlen + 2;
+	printer(arg, " user=");
+	ppp_print_string(user, ulen, printer, arg);
+	printer(arg, " password=");
+/* FIXME: require ppp_pcb struct as printpkt() argument */
+#if 0
+	if (!pcb->settings.hide_password)
+#endif
+	    ppp_print_string(pwd, wlen, printer, arg);
+#if 0
+	else
+	    printer(arg, "<hidden>");
+#endif
+	break;
+    case UPAP_AUTHACK:
+    case UPAP_AUTHNAK:
+	if (len < 1)
+	    break;
+	mlen = p[0];
+	if (len < mlen + 1)
+	    break;
+	msg = (const u_char *) (p + 1);
+	p += mlen + 1;
+	len -= mlen + 1;
+	printer(arg, " ");
+	ppp_print_string(msg, mlen, printer, arg);
+	break;
+    default:
+	break;
+    }
+
+    /* print the rest of the bytes in the packet */
+    for (; len > 0; --len) {
+	GETCHAR(code, p);
+	printer(arg, " %.2x", code);
+    }
+
+    return p - pstart;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#endif /* PPP_SUPPORT && PAP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/utils.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/utils.c
new file mode 100644
index 000000000..f1366dae4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/utils.c
@@ -0,0 +1,957 @@
+/*
+ * utils.c - various utility functions used in pppd.
+ *
+ * Copyright (c) 1999-2002 Paul Mackerras. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. The name(s) of the authors of this software must not be used to
+ *    endorse or promote products derived from this software without
+ *    prior written permission.
+ *
+ * 3. Redistributions of any form whatsoever must retain the following
+ *    acknowledgment:
+ *    "This product includes software developed by Paul Mackerras
+ *     <paulus@samba.org>".
+ *
+ * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
+ * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
+ * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#if 0 /* UNUSED */
+#include <stdio.h>
+#include <ctype.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <signal.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <syslog.h>
+#include <netdb.h>
+#include <time.h>
+#include <utmp.h>
+#include <pwd.h>
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <sys/time.h>
+#include <sys/resource.h>
+#include <sys/stat.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#ifdef SVR4
+#include <sys/mkdev.h>
+#endif
+#endif /* UNUSED */
+
+#include "netif/ppp/ppp_impl.h"
+
+#include "netif/ppp/fsm.h"
+#include "netif/ppp/lcp.h"
+
+#if defined(SUNOS4)
+extern char *strerror();
+#endif
+
+static void ppp_logit(int level, const char *fmt, va_list args);
+static void ppp_log_write(int level, char *buf);
+#if PRINTPKT_SUPPORT
+static void ppp_vslp_printer(void *arg, const char *fmt, ...);
+static void ppp_format_packet(const u_char *p, int len,
+		void (*printer) (void *, const char *, ...), void *arg);
+
+struct buffer_info {
+    char *ptr;
+    int len;
+};
+#endif /* PRINTPKT_SUPPORT */
+
+/*
+ * ppp_strlcpy - like strcpy/strncpy, doesn't overflow destination buffer,
+ * always leaves destination null-terminated (for len > 0).
+ */
+size_t ppp_strlcpy(char *dest, const char *src, size_t len) {
+    size_t ret = strlen(src);
+
+    if (len != 0) {
+	if (ret < len)
+	    strcpy(dest, src);
+	else {
+	    strncpy(dest, src, len - 1);
+	    dest[len-1] = 0;
+	}
+    }
+    return ret;
+}
+
+/*
+ * ppp_strlcat - like strcat/strncat, doesn't overflow destination buffer,
+ * always leaves destination null-terminated (for len > 0).
+ */
+size_t ppp_strlcat(char *dest, const char *src, size_t len) {
+    size_t dlen = strlen(dest);
+
+    return dlen + ppp_strlcpy(dest + dlen, src, (len > dlen? len - dlen: 0));
+}
+
+
+/*
+ * ppp_slprintf - format a message into a buffer.  Like sprintf except we
+ * also specify the length of the output buffer, and we handle
+ * %m (error message), %v (visible string),
+ * %q (quoted string), %t (current time) and %I (IP address) formats.
+ * Doesn't do floating-point formats.
+ * Returns the number of chars put into buf.
+ */
+int ppp_slprintf(char *buf, int buflen, const char *fmt, ...) {
+    va_list args;
+    int n;
+
+    va_start(args, fmt);
+    n = ppp_vslprintf(buf, buflen, fmt, args);
+    va_end(args);
+    return n;
+}
+
+/*
+ * ppp_vslprintf - like ppp_slprintf, takes a va_list instead of a list of args.
+ */
+#define OUTCHAR(c)	(buflen > 0? (--buflen, *buf++ = (c)): 0)
+
+int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args) {
+    int c, i, n;
+    int width, prec, fillch;
+    int base, len, neg, quoted;
+    unsigned long val = 0;
+    const char *f;
+    char *str, *buf0;
+    const unsigned char *p;
+    char num[32];
+#if 0 /* need port */
+    time_t t;
+#endif /* need port */
+    u32_t ip;
+    static char hexchars[] = "0123456789abcdef";
+#if PRINTPKT_SUPPORT
+    struct buffer_info bufinfo;
+#endif /* PRINTPKT_SUPPORT */
+
+    buf0 = buf;
+    --buflen;
+    while (buflen > 0) {
+	for (f = fmt; *f != '%' && *f != 0; ++f)
+	    ;
+	if (f > fmt) {
+	    len = f - fmt;
+	    if (len > buflen)
+		len = buflen;
+	    memcpy(buf, fmt, len);
+	    buf += len;
+	    buflen -= len;
+	    fmt = f;
+	}
+	if (*fmt == 0)
+	    break;
+	c = *++fmt;
+	width = 0;
+	prec = -1;
+	fillch = ' ';
+	if (c == '0') {
+	    fillch = '0';
+	    c = *++fmt;
+	}
+	if (c == '*') {
+	    width = va_arg(args, int);
+	    c = *++fmt;
+	} else {
+	    while (lwip_isdigit(c)) {
+		width = width * 10 + c - '0';
+		c = *++fmt;
+	    }
+	}
+	if (c == '.') {
+	    c = *++fmt;
+	    if (c == '*') {
+		prec = va_arg(args, int);
+		c = *++fmt;
+	    } else {
+		prec = 0;
+		while (lwip_isdigit(c)) {
+		    prec = prec * 10 + c - '0';
+		    c = *++fmt;
+		}
+	    }
+	}
+	str = 0;
+	base = 0;
+	neg = 0;
+	++fmt;
+	switch (c) {
+	case 'l':
+	    c = *fmt++;
+	    switch (c) {
+	    case 'd':
+		val = va_arg(args, long);
+		if ((long)val < 0) {
+		    neg = 1;
+		    val = (unsigned long)-(long)val;
+		}
+		base = 10;
+		break;
+	    case 'u':
+		val = va_arg(args, unsigned long);
+		base = 10;
+		break;
+	    default:
+		OUTCHAR('%');
+		OUTCHAR('l');
+		--fmt;		/* so %lz outputs %lz etc. */
+		continue;
+	    }
+	    break;
+	case 'd':
+	    i = va_arg(args, int);
+	    if (i < 0) {
+		neg = 1;
+		val = -i;
+	    } else
+		val = i;
+	    base = 10;
+	    break;
+	case 'u':
+	    val = va_arg(args, unsigned int);
+	    base = 10;
+	    break;
+	case 'o':
+	    val = va_arg(args, unsigned int);
+	    base = 8;
+	    break;
+	case 'x':
+	case 'X':
+	    val = va_arg(args, unsigned int);
+	    base = 16;
+	    break;
+#if 0 /* unused (and wrong on LLP64 systems) */
+	case 'p':
+	    val = (unsigned long) va_arg(args, void *);
+	    base = 16;
+	    neg = 2;
+	    break;
+#endif /* unused (and wrong on LLP64 systems) */
+	case 's':
+	    str = va_arg(args, char *);
+	    break;
+	case 'c':
+	    num[0] = va_arg(args, int);
+	    num[1] = 0;
+	    str = num;
+	    break;
+#if 0 /* do we always have strerror() in embedded ? */
+	case 'm':
+	    str = strerror(errno);
+	    break;
+#endif /* do we always have strerror() in embedded ? */
+	case 'I':
+	    ip = va_arg(args, u32_t);
+	    ip = lwip_ntohl(ip);
+	    ppp_slprintf(num, sizeof(num), "%d.%d.%d.%d", (ip >> 24) & 0xff,
+		     (ip >> 16) & 0xff, (ip >> 8) & 0xff, ip & 0xff);
+	    str = num;
+	    break;
+#if 0 /* need port */
+	case 't':
+	    time(&t);
+	    str = ctime(&t);
+	    str += 4;		/* chop off the day name */
+	    str[15] = 0;	/* chop off year and newline */
+	    break;
+#endif /* need port */
+	case 'v':		/* "visible" string */
+	case 'q':		/* quoted string */
+	    quoted = c == 'q';
+	    p = va_arg(args, unsigned char *);
+	    if (p == NULL)
+		p = (const unsigned char *)"<NULL>";
+	    if (fillch == '0' && prec >= 0) {
+		n = prec;
+	    } else {
+		n = strlen((const char *)p);
+		if (prec >= 0 && n > prec)
+		    n = prec;
+	    }
+	    while (n > 0 && buflen > 0) {
+		c = *p++;
+		--n;
+		if (!quoted && c >= 0x80) {
+		    OUTCHAR('M');
+		    OUTCHAR('-');
+		    c -= 0x80;
+		}
+		if (quoted && (c == '"' || c == '\\'))
+		    OUTCHAR('\\');
+		if (c < 0x20 || (0x7f <= c && c < 0xa0)) {
+		    if (quoted) {
+			OUTCHAR('\\');
+			switch (c) {
+			case '\t':	OUTCHAR('t');	break;
+			case '\n':	OUTCHAR('n');	break;
+			case '\b':	OUTCHAR('b');	break;
+			case '\f':	OUTCHAR('f');	break;
+			default:
+			    OUTCHAR('x');
+			    OUTCHAR(hexchars[c >> 4]);
+			    OUTCHAR(hexchars[c & 0xf]);
+			}
+		    } else {
+			if (c == '\t')
+			    OUTCHAR(c);
+			else {
+			    OUTCHAR('^');
+			    OUTCHAR(c ^ 0x40);
+			}
+		    }
+		} else
+		    OUTCHAR(c);
+	    }
+	    continue;
+#if PRINTPKT_SUPPORT
+	case 'P':		/* print PPP packet */
+	    bufinfo.ptr = buf;
+	    bufinfo.len = buflen + 1;
+	    p = va_arg(args, unsigned char *);
+	    n = va_arg(args, int);
+	    ppp_format_packet(p, n, ppp_vslp_printer, &bufinfo);
+	    buf = bufinfo.ptr;
+	    buflen = bufinfo.len - 1;
+	    continue;
+#endif /* PRINTPKT_SUPPORT */
+	case 'B':
+	    p = va_arg(args, unsigned char *);
+	    for (n = prec; n > 0; --n) {
+		c = *p++;
+		if (fillch == ' ')
+		    OUTCHAR(' ');
+		OUTCHAR(hexchars[(c >> 4) & 0xf]);
+		OUTCHAR(hexchars[c & 0xf]);
+	    }
+	    continue;
+	default:
+	    *buf++ = '%';
+	    if (c != '%')
+		--fmt;		/* so %z outputs %z etc. */
+	    --buflen;
+	    continue;
+	}
+	if (base != 0) {
+	    str = num + sizeof(num);
+	    *--str = 0;
+	    while (str > num + neg) {
+		*--str = hexchars[val % base];
+		val = val / base;
+		if (--prec <= 0 && val == 0)
+		    break;
+	    }
+	    switch (neg) {
+	    case 1:
+		*--str = '-';
+		break;
+	    case 2:
+		*--str = 'x';
+		*--str = '0';
+		break;
+	    default:
+		break;
+	    }
+	    len = num + sizeof(num) - 1 - str;
+	} else {
+	    len = strlen(str);
+	    if (prec >= 0 && len > prec)
+		len = prec;
+	}
+	if (width > 0) {
+	    if (width > buflen)
+		width = buflen;
+	    if ((n = width - len) > 0) {
+		buflen -= n;
+		for (; n > 0; --n)
+		    *buf++ = fillch;
+	    }
+	}
+	if (len > buflen)
+	    len = buflen;
+	memcpy(buf, str, len);
+	buf += len;
+	buflen -= len;
+    }
+    *buf = 0;
+    return buf - buf0;
+}
+
+#if PRINTPKT_SUPPORT
+/*
+ * vslp_printer - used in processing a %P format
+ */
+static void ppp_vslp_printer(void *arg, const char *fmt, ...) {
+    int n;
+    va_list pvar;
+    struct buffer_info *bi;
+
+    va_start(pvar, fmt);
+    bi = (struct buffer_info *) arg;
+    n = ppp_vslprintf(bi->ptr, bi->len, fmt, pvar);
+    va_end(pvar);
+
+    bi->ptr += n;
+    bi->len -= n;
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#if 0 /* UNUSED */
+/*
+ * log_packet - format a packet and log it.
+ */
+
+void
+log_packet(p, len, prefix, level)
+    u_char *p;
+    int len;
+    char *prefix;
+    int level;
+{
+	init_pr_log(prefix, level);
+	ppp_format_packet(p, len, pr_log, &level);
+	end_pr_log();
+}
+#endif /* UNUSED */
+
+#if PRINTPKT_SUPPORT
+/*
+ * ppp_format_packet - make a readable representation of a packet,
+ * calling `printer(arg, format, ...)' to output it.
+ */
+static void ppp_format_packet(const u_char *p, int len,
+		void (*printer) (void *, const char *, ...), void *arg) {
+    int i, n;
+    u_short proto;
+    const struct protent *protp;
+
+    if (len >= 2) {
+	GETSHORT(proto, p);
+	len -= 2;
+	for (i = 0; (protp = protocols[i]) != NULL; ++i)
+	    if (proto == protp->protocol)
+		break;
+	if (protp != NULL) {
+	    printer(arg, "[%s", protp->name);
+	    n = (*protp->printpkt)(p, len, printer, arg);
+	    printer(arg, "]");
+	    p += n;
+	    len -= n;
+	} else {
+	    for (i = 0; (protp = protocols[i]) != NULL; ++i)
+		if (proto == (protp->protocol & ~0x8000))
+		    break;
+	    if (protp != 0 && protp->data_name != 0) {
+		printer(arg, "[%s data]", protp->data_name);
+		if (len > 8)
+		    printer(arg, "%.8B ...", p);
+		else
+		    printer(arg, "%.*B", len, p);
+		len = 0;
+	    } else
+		printer(arg, "[proto=0x%x]", proto);
+	}
+    }
+
+    if (len > 32)
+	printer(arg, "%.32B ...", p);
+    else
+	printer(arg, "%.*B", len, p);
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#if 0 /* UNUSED */
+/*
+ * init_pr_log, end_pr_log - initialize and finish use of pr_log.
+ */
+
+static char line[256];		/* line to be logged accumulated here */
+static char *linep;		/* current pointer within line */
+static int llevel;		/* level for logging */
+
+void
+init_pr_log(prefix, level)
+     const char *prefix;
+     int level;
+{
+	linep = line;
+	if (prefix != NULL) {
+		ppp_strlcpy(line, prefix, sizeof(line));
+		linep = line + strlen(line);
+	}
+	llevel = level;
+}
+
+void
+end_pr_log()
+{
+	if (linep != line) {
+		*linep = 0;
+		ppp_log_write(llevel, line);
+	}
+}
+
+/*
+ * pr_log - printer routine for outputting to log
+ */
+void
+pr_log (void *arg, const char *fmt, ...)
+{
+	int l, n;
+	va_list pvar;
+	char *p, *eol;
+	char buf[256];
+
+	va_start(pvar, fmt);
+	n = ppp_vslprintf(buf, sizeof(buf), fmt, pvar);
+	va_end(pvar);
+
+	p = buf;
+	eol = strchr(buf, '\n');
+	if (linep != line) {
+		l = (eol == NULL)? n: eol - buf;
+		if (linep + l < line + sizeof(line)) {
+			if (l > 0) {
+				memcpy(linep, buf, l);
+				linep += l;
+			}
+			if (eol == NULL)
+				return;
+			p = eol + 1;
+			eol = strchr(p, '\n');
+		}
+		*linep = 0;
+		ppp_log_write(llevel, line);
+		linep = line;
+	}
+
+	while (eol != NULL) {
+		*eol = 0;
+		ppp_log_write(llevel, p);
+		p = eol + 1;
+		eol = strchr(p, '\n');
+	}
+
+	/* assumes sizeof(buf) <= sizeof(line) */
+	l = buf + n - p;
+	if (l > 0) {
+		memcpy(line, p, n);
+		linep = line + l;
+	}
+}
+#endif /* UNUSED */
+
+/*
+ * ppp_print_string - print a readable representation of a string using
+ * printer.
+ */
+void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg) {
+    int c;
+
+    printer(arg, "\"");
+    for (; len > 0; --len) {
+	c = *p++;
+	if (' ' <= c && c <= '~') {
+	    if (c == '\\' || c == '"')
+		printer(arg, "\\");
+	    printer(arg, "%c", c);
+	} else {
+	    switch (c) {
+	    case '\n':
+		printer(arg, "\\n");
+		break;
+	    case '\r':
+		printer(arg, "\\r");
+		break;
+	    case '\t':
+		printer(arg, "\\t");
+		break;
+	    default:
+		printer(arg, "\\%.3o", (u8_t)c);
+		/* no break */
+	    }
+	}
+    }
+    printer(arg, "\"");
+}
+
+/*
+ * ppp_logit - does the hard work for fatal et al.
+ */
+static void ppp_logit(int level, const char *fmt, va_list args) {
+    char buf[1024];
+
+    ppp_vslprintf(buf, sizeof(buf), fmt, args);
+    ppp_log_write(level, buf);
+}
+
+static void ppp_log_write(int level, char *buf) {
+    LWIP_UNUSED_ARG(level); /* necessary if PPPDEBUG is defined to an empty function */
+    LWIP_UNUSED_ARG(buf);
+    PPPDEBUG(level, ("%s\n", buf) );
+#if 0
+    if (log_to_fd >= 0 && (level != LOG_DEBUG || debug)) {
+	int n = strlen(buf);
+
+	if (n > 0 && buf[n-1] == '\n')
+	    --n;
+	if (write(log_to_fd, buf, n) != n
+	    || write(log_to_fd, "\n", 1) != 1)
+	    log_to_fd = -1;
+    }
+#endif
+}
+
+/*
+ * ppp_fatal - log an error message and die horribly.
+ */
+void ppp_fatal(const char *fmt, ...) {
+    va_list pvar;
+
+    va_start(pvar, fmt);
+    ppp_logit(LOG_ERR, fmt, pvar);
+    va_end(pvar);
+
+    LWIP_ASSERT("ppp_fatal", 0);   /* as promised */
+}
+
+/*
+ * ppp_error - log an error message.
+ */
+void ppp_error(const char *fmt, ...) {
+    va_list pvar;
+
+    va_start(pvar, fmt);
+    ppp_logit(LOG_ERR, fmt, pvar);
+    va_end(pvar);
+#if 0 /* UNUSED */
+    ++error_count;
+#endif /* UNUSED */
+}
+
+/*
+ * ppp_warn - log a warning message.
+ */
+void ppp_warn(const char *fmt, ...) {
+    va_list pvar;
+
+    va_start(pvar, fmt);
+    ppp_logit(LOG_WARNING, fmt, pvar);
+    va_end(pvar);
+}
+
+/*
+ * ppp_notice - log a notice-level message.
+ */
+void ppp_notice(const char *fmt, ...) {
+    va_list pvar;
+
+    va_start(pvar, fmt);
+    ppp_logit(LOG_NOTICE, fmt, pvar);
+    va_end(pvar);
+}
+
+/*
+ * ppp_info - log an informational message.
+ */
+void ppp_info(const char *fmt, ...) {
+    va_list pvar;
+
+    va_start(pvar, fmt);
+    ppp_logit(LOG_INFO, fmt, pvar);
+    va_end(pvar);
+}
+
+/*
+ * ppp_dbglog - log a debug message.
+ */
+void ppp_dbglog(const char *fmt, ...) {
+    va_list pvar;
+
+    va_start(pvar, fmt);
+    ppp_logit(LOG_DEBUG, fmt, pvar);
+    va_end(pvar);
+}
+
+#if PRINTPKT_SUPPORT
+/*
+ * ppp_dump_packet - print out a packet in readable form if it is interesting.
+ * Assumes len >= PPP_HDRLEN.
+ */
+void ppp_dump_packet(ppp_pcb *pcb, const char *tag, unsigned char *p, int len) {
+    int proto;
+
+    /*
+     * don't print data packets, i.e. IPv4, IPv6, VJ, and compressed packets.
+     */
+    proto = (p[0] << 8) + p[1];
+    if (proto < 0xC000 && (proto & ~0x8000) == proto)
+	return;
+
+    /*
+     * don't print valid LCP echo request/reply packets if the link is up.
+     */
+    if (proto == PPP_LCP && pcb->phase == PPP_PHASE_RUNNING && len >= 2 + HEADERLEN) {
+	unsigned char *lcp = p + 2;
+	int l = (lcp[2] << 8) + lcp[3];
+
+	if ((lcp[0] == ECHOREQ || lcp[0] == ECHOREP)
+	    && l >= HEADERLEN && l <= len - 2)
+	    return;
+    }
+
+    ppp_dbglog("%s %P", tag, p, len);
+}
+#endif /* PRINTPKT_SUPPORT */
+
+#if 0 /* Unused */
+
+/*
+ * complete_read - read a full `count' bytes from fd,
+ * unless end-of-file or an error other than EINTR is encountered.
+ */
+ssize_t
+complete_read(int fd, void *buf, size_t count)
+{
+	size_t done;
+	ssize_t nb;
+	char *ptr = buf;
+
+	for (done = 0; done < count; ) {
+		nb = read(fd, ptr, count - done);
+		if (nb < 0) {
+			if (errno == EINTR)
+				continue;
+			return -1;
+		}
+		if (nb == 0)
+			break;
+		done += nb;
+		ptr += nb;
+	}
+	return done;
+}
+
+/* Procedures for locking the serial device using a lock file. */
+#ifndef LOCK_DIR
+#ifdef __linux__
+#define LOCK_DIR	"/var/lock"
+#else
+#ifdef SVR4
+#define LOCK_DIR	"/var/spool/locks"
+#else
+#define LOCK_DIR	"/var/spool/lock"
+#endif
+#endif
+#endif /* LOCK_DIR */
+
+static char lock_file[MAXPATHLEN];
+
+/*
+ * lock - create a lock file for the named device
+ */
+int
+lock(dev)
+    char *dev;
+{
+#ifdef LOCKLIB
+    int result;
+
+    result = mklock (dev, (void *) 0);
+    if (result == 0) {
+	ppp_strlcpy(lock_file, dev, sizeof(lock_file));
+	return 0;
+    }
+
+    if (result > 0)
+        ppp_notice("Device %s is locked by pid %d", dev, result);
+    else
+	ppp_error("Can't create lock file %s", lock_file);
+    return -1;
+
+#else /* LOCKLIB */
+
+    char lock_buffer[12];
+    int fd, pid, n;
+
+#ifdef SVR4
+    struct stat sbuf;
+
+    if (stat(dev, &sbuf) < 0) {
+	ppp_error("Can't get device number for %s: %m", dev);
+	return -1;
+    }
+    if ((sbuf.st_mode & S_IFMT) != S_IFCHR) {
+	ppp_error("Can't lock %s: not a character device", dev);
+	return -1;
+    }
+    ppp_slprintf(lock_file, sizeof(lock_file), "%s/LK.%03d.%03d.%03d",
+	     LOCK_DIR, major(sbuf.st_dev),
+	     major(sbuf.st_rdev), minor(sbuf.st_rdev));
+#else
+    char *p;
+    char lockdev[MAXPATHLEN];
+
+    if ((p = strstr(dev, "dev/")) != NULL) {
+	dev = p + 4;
+	strncpy(lockdev, dev, MAXPATHLEN-1);
+	lockdev[MAXPATHLEN-1] = 0;
+	while ((p = strrchr(lockdev, '/')) != NULL) {
+	    *p = '_';
+	}
+	dev = lockdev;
+    } else
+	if ((p = strrchr(dev, '/')) != NULL)
+	    dev = p + 1;
+
+    ppp_slprintf(lock_file, sizeof(lock_file), "%s/LCK..%s", LOCK_DIR, dev);
+#endif
+
+    while ((fd = open(lock_file, O_EXCL | O_CREAT | O_RDWR, 0644)) < 0) {
+	if (errno != EEXIST) {
+	    ppp_error("Can't create lock file %s: %m", lock_file);
+	    break;
+	}
+
+	/* Read the lock file to find out who has the device locked. */
+	fd = open(lock_file, O_RDONLY, 0);
+	if (fd < 0) {
+	    if (errno == ENOENT) /* This is just a timing problem. */
+		continue;
+	    ppp_error("Can't open existing lock file %s: %m", lock_file);
+	    break;
+	}
+#ifndef LOCK_BINARY
+	n = read(fd, lock_buffer, 11);
+#else
+	n = read(fd, &pid, sizeof(pid));
+#endif /* LOCK_BINARY */
+	close(fd);
+	fd = -1;
+	if (n <= 0) {
+	    ppp_error("Can't read pid from lock file %s", lock_file);
+	    break;
+	}
+
+	/* See if the process still exists. */
+#ifndef LOCK_BINARY
+	lock_buffer[n] = 0;
+	pid = atoi(lock_buffer);
+#endif /* LOCK_BINARY */
+	if (pid == getpid())
+	    return 1;		/* somebody else locked it for us */
+	if (pid == 0
+	    || (kill(pid, 0) == -1 && errno == ESRCH)) {
+	    if (unlink (lock_file) == 0) {
+		ppp_notice("Removed stale lock on %s (pid %d)", dev, pid);
+		continue;
+	    }
+	    ppp_warn("Couldn't remove stale lock on %s", dev);
+	} else
+	    ppp_notice("Device %s is locked by pid %d", dev, pid);
+	break;
+    }
+
+    if (fd < 0) {
+	lock_file[0] = 0;
+	return -1;
+    }
+
+    pid = getpid();
+#ifndef LOCK_BINARY
+    ppp_slprintf(lock_buffer, sizeof(lock_buffer), "%10d\n", pid);
+    write (fd, lock_buffer, 11);
+#else
+    write(fd, &pid, sizeof (pid));
+#endif
+    close(fd);
+    return 0;
+
+#endif
+}
+
+/*
+ * relock - called to update our lockfile when we are about to detach,
+ * thus changing our pid (we fork, the child carries on, and the parent dies).
+ * Note that this is called by the parent, with pid equal to the pid
+ * of the child.  This avoids a potential race which would exist if
+ * we had the child rewrite the lockfile (the parent might die first,
+ * and another process could think the lock was stale if it checked
+ * between when the parent died and the child rewrote the lockfile).
+ */
+int
+relock(pid)
+    int pid;
+{
+#ifdef LOCKLIB
+    /* XXX is there a way to do this? */
+    return -1;
+#else /* LOCKLIB */
+
+    int fd;
+    char lock_buffer[12];
+
+    if (lock_file[0] == 0)
+	return -1;
+    fd = open(lock_file, O_WRONLY, 0);
+    if (fd < 0) {
+	ppp_error("Couldn't reopen lock file %s: %m", lock_file);
+	lock_file[0] = 0;
+	return -1;
+    }
+
+#ifndef LOCK_BINARY
+    ppp_slprintf(lock_buffer, sizeof(lock_buffer), "%10d\n", pid);
+    write (fd, lock_buffer, 11);
+#else
+    write(fd, &pid, sizeof(pid));
+#endif /* LOCK_BINARY */
+    close(fd);
+    return 0;
+
+#endif /* LOCKLIB */
+}
+
+/*
+ * unlock - remove our lockfile
+ */
+void
+unlock()
+{
+    if (lock_file[0]) {
+#ifdef LOCKLIB
+	(void) rmlock(lock_file, (void *) 0);
+#else
+	unlink(lock_file);
+#endif
+	lock_file[0] = 0;
+    }
+}
+
+#endif /* Unused */
+
+#endif /* PPP_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/vj.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/vj.c
new file mode 100644
index 000000000..3fecba699
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/ppp/vj.c
@@ -0,0 +1,685 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *   Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include "netif/ppp/ppp_opts.h"
+#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */
+
+#include "netif/ppp/ppp_impl.h"
+#include "netif/ppp/pppdebug.h"
+
+#include "netif/ppp/vj.h"
+
+#include <string.h>
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+void
+vj_compress_init(struct vjcompress *comp)
+{
+  u8_t i;
+  struct cstate *tstate = comp->tstate;
+
+#if MAX_SLOTS == 0
+  memset((char *)comp, 0, sizeof(*comp));
+#endif
+  comp->maxSlotIndex = MAX_SLOTS - 1;
+  comp->compressSlot = 0;    /* Disable slot ID compression by default. */
+  for (i = MAX_SLOTS - 1; i > 0; --i) {
+    tstate[i].cs_id = i;
+    tstate[i].cs_next = &tstate[i - 1];
+  }
+  tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+  tstate[0].cs_id = 0;
+  comp->last_cs = &tstate[0];
+  comp->last_recv = 255;
+  comp->last_xmit = 255;
+  comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+  if ((u16_t)(n) >= 256) { \
+    *cp++ = 0; \
+    cp[1] = (u8_t)(n); \
+    cp[0] = (u8_t)((n) >> 8); \
+    cp += 2; \
+  } else { \
+    *cp++ = (u8_t)(n); \
+  } \
+}
+#define ENCODEZ(n) { \
+  if ((u16_t)(n) >= 256 || (u16_t)(n) == 0) { \
+    *cp++ = 0; \
+    cp[1] = (u8_t)(n); \
+    cp[0] = (u8_t)((n) >> 8); \
+    cp += 2; \
+  } else { \
+    *cp++ = (u8_t)(n); \
+  } \
+}
+
+#define DECODEL(f) { \
+  if (*cp == 0) {\
+    u32_t tmp_ = lwip_ntohl(f) + ((cp[1] << 8) | cp[2]); \
+    (f) = lwip_htonl(tmp_); \
+    cp += 3; \
+  } else { \
+    u32_t tmp_ = lwip_ntohl(f) + (u32_t)*cp++; \
+    (f) = lwip_htonl(tmp_); \
+  } \
+}
+
+#define DECODES(f) { \
+  if (*cp == 0) {\
+    u16_t tmp_ = lwip_ntohs(f) + (((u16_t)cp[1] << 8) | cp[2]); \
+    (f) = lwip_htons(tmp_); \
+    cp += 3; \
+  } else { \
+    u16_t tmp_ = lwip_ntohs(f) + (u16_t)*cp++; \
+    (f) = lwip_htons(tmp_); \
+  } \
+}
+
+#define DECODEU(f) { \
+  if (*cp == 0) {\
+    (f) = lwip_htons(((u16_t)cp[1] << 8) | cp[2]); \
+    cp += 3; \
+  } else { \
+    (f) = lwip_htons((u16_t)*cp++); \
+  } \
+}
+
+/* Helper structures for unaligned *u32_t and *u16_t accesses */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct vj_u32_t {
+  PACK_STRUCT_FIELD(u32_t v);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct vj_u16_t {
+  PACK_STRUCT_FIELD(u16_t v);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobson header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u8_t
+vj_compress_tcp(struct vjcompress *comp, struct pbuf **pb)
+{
+  struct pbuf *np = *pb;
+  struct ip_hdr *ip = (struct ip_hdr *)np->payload;
+  struct cstate *cs = comp->last_cs->cs_next;
+  u16_t ilen = IPH_HL(ip);
+  u16_t hlen;
+  struct tcp_hdr *oth;
+  struct tcp_hdr *th;
+  u16_t deltaS, deltaA = 0;
+  u32_t deltaL;
+  u32_t changes = 0;
+  u8_t new_seq[16];
+  u8_t *cp = new_seq;
+
+  /*
+   * Check that the packet is IP proto TCP.
+   */
+  if (IPH_PROTO(ip) != IP_PROTO_TCP) {
+    return (TYPE_IP);
+  }
+
+  /*
+   * Bail if this is an IP fragment or if the TCP packet isn't
+   * `compressible' (i.e., ACK isn't set or some other control bit is
+   * set).
+   */
+  if ((IPH_OFFSET(ip) & PP_HTONS(0x3fff)) || np->tot_len < 40) {
+    return (TYPE_IP);
+  }
+  th = (struct tcp_hdr *)&((struct vj_u32_t*)ip)[ilen];
+  if ((TCPH_FLAGS(th) & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) {
+    return (TYPE_IP);
+  }
+
+  /* Check that the TCP/IP headers are contained in the first buffer. */
+  hlen = ilen + TCPH_HDRLEN(th);
+  hlen <<= 2;
+  if (np->len < hlen) {
+    PPPDEBUG(LOG_INFO, ("vj_compress_tcp: header len %d spans buffers\n", hlen));
+    return (TYPE_IP);
+  }
+
+  /* TCP stack requires that we don't change the packet payload, therefore we copy
+   * the whole packet before compression. */
+  np = pbuf_clone(PBUF_RAW, PBUF_RAM, *pb);
+  if (!np) {
+    return (TYPE_IP);
+  }
+
+  *pb = np;
+  ip = (struct ip_hdr *)np->payload;
+
+  /*
+   * Packet is compressible -- we're going to send either a
+   * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+   * to locate (or create) the connection state.  Special case the
+   * most recently used connection since it's most likely to be used
+   * again & we don't have to do any reordering if it's used.
+   */
+  INCR(vjs_packets);
+  if (!ip4_addr_cmp(&ip->src, &cs->cs_ip.src)
+      || !ip4_addr_cmp(&ip->dest, &cs->cs_ip.dest)
+      || (*(struct vj_u32_t*)th).v != (((struct vj_u32_t*)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]).v) {
+    /*
+     * Wasn't the first -- search for it.
+     *
+     * States are kept in a circularly linked list with
+     * last_cs pointing to the end of the list.  The
+     * list is kept in lru order by moving a state to the
+     * head of the list whenever it is referenced.  Since
+     * the list is short and, empirically, the connection
+     * we want is almost always near the front, we locate
+     * states via linear search.  If we don't find a state
+     * for the datagram, the oldest state is (re-)used.
+     */
+    struct cstate *lcs;
+    struct cstate *lastcs = comp->last_cs;
+
+    do {
+      lcs = cs; cs = cs->cs_next;
+      INCR(vjs_searches);
+      if (ip4_addr_cmp(&ip->src, &cs->cs_ip.src)
+          && ip4_addr_cmp(&ip->dest, &cs->cs_ip.dest)
+          && (*(struct vj_u32_t*)th).v == (((struct vj_u32_t*)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]).v) {
+        goto found;
+      }
+    } while (cs != lastcs);
+
+    /*
+     * Didn't find it -- re-use oldest cstate.  Send an
+     * uncompressed packet that tells the other side what
+     * connection number we're using for this conversation.
+     * Note that since the state list is circular, the oldest
+     * state points to the newest and we only need to set
+     * last_cs to update the lru linkage.
+     */
+    INCR(vjs_misses);
+    comp->last_cs = lcs;
+    goto uncompressed;
+
+    found:
+    /*
+     * Found it -- move to the front on the connection list.
+     */
+    if (cs == lastcs) {
+      comp->last_cs = lcs;
+    } else {
+      lcs->cs_next = cs->cs_next;
+      cs->cs_next = lastcs->cs_next;
+      lastcs->cs_next = cs;
+    }
+  }
+
+  oth = (struct tcp_hdr *)&((struct vj_u32_t*)&cs->cs_ip)[ilen];
+  deltaS = ilen;
+
+  /*
+   * Make sure that only what we expect to change changed. The first
+   * line of the `if' checks the IP protocol version, header length &
+   * type of service.  The 2nd line checks the "Don't fragment" bit.
+   * The 3rd line checks the time-to-live and protocol (the protocol
+   * check is unnecessary but costless).  The 4th line checks the TCP
+   * header length.  The 5th line checks IP options, if any.  The 6th
+   * line checks TCP options, if any.  If any of these things are
+   * different between the previous & current datagram, we send the
+   * current datagram `uncompressed'.
+   */
+  if ((((struct vj_u16_t*)ip)[0]).v != (((struct vj_u16_t*)&cs->cs_ip)[0]).v
+      || (((struct vj_u16_t*)ip)[3]).v != (((struct vj_u16_t*)&cs->cs_ip)[3]).v
+      || (((struct vj_u16_t*)ip)[4]).v != (((struct vj_u16_t*)&cs->cs_ip)[4]).v
+      || TCPH_HDRLEN(th) != TCPH_HDRLEN(oth)
+      || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2))
+      || (TCPH_HDRLEN(th) > 5 && BCMP(th + 1, oth + 1, (TCPH_HDRLEN(th) - 5) << 2))) {
+    goto uncompressed;
+  }
+
+  /*
+   * Figure out which of the changing fields changed.  The
+   * receiver expects changes in the order: urgent, window,
+   * ack, seq (the order minimizes the number of temporaries
+   * needed in this section of code).
+   */
+  if (TCPH_FLAGS(th) & TCP_URG) {
+    deltaS = lwip_ntohs(th->urgp);
+    ENCODEZ(deltaS);
+    changes |= NEW_U;
+  } else if (th->urgp != oth->urgp) {
+    /* argh! URG not set but urp changed -- a sensible
+     * implementation should never do this but RFC793
+     * doesn't prohibit the change so we have to deal
+     * with it. */
+    goto uncompressed;
+  }
+
+  if ((deltaS = (u16_t)(lwip_ntohs(th->wnd) - lwip_ntohs(oth->wnd))) != 0) {
+    ENCODE(deltaS);
+    changes |= NEW_W;
+  }
+
+  if ((deltaL = lwip_ntohl(th->ackno) - lwip_ntohl(oth->ackno)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaA = (u16_t)deltaL;
+    ENCODE(deltaA);
+    changes |= NEW_A;
+  }
+
+  if ((deltaL = lwip_ntohl(th->seqno) - lwip_ntohl(oth->seqno)) != 0) {
+    if (deltaL > 0xffff) {
+      goto uncompressed;
+    }
+    deltaS = (u16_t)deltaL;
+    ENCODE(deltaS);
+    changes |= NEW_S;
+  }
+
+  switch(changes) {
+  case 0:
+    /*
+     * Nothing changed. If this packet contains data and the
+     * last one didn't, this is probably a data packet following
+     * an ack (normal on an interactive connection) and we send
+     * it compressed.  Otherwise it's probably a retransmit,
+     * retransmitted ack or window probe.  Send it uncompressed
+     * in case the other side missed the compressed version.
+     */
+    if (IPH_LEN(ip) != IPH_LEN(&cs->cs_ip) &&
+      lwip_ntohs(IPH_LEN(&cs->cs_ip)) == hlen) {
+      break;
+    }
+    /* no break */
+    /* fall through */
+
+  case SPECIAL_I:
+  case SPECIAL_D:
+    /*
+     * actual changes match one of our special case encodings --
+     * send packet uncompressed.
+     */
+    goto uncompressed;
+
+  case NEW_S|NEW_A:
+    if (deltaS == deltaA && deltaS == lwip_ntohs(IPH_LEN(&cs->cs_ip)) - hlen) {
+      /* special case for echoed terminal traffic */
+      changes = SPECIAL_I;
+      cp = new_seq;
+    }
+    break;
+
+  case NEW_S:
+    if (deltaS == lwip_ntohs(IPH_LEN(&cs->cs_ip)) - hlen) {
+      /* special case for data xfer */
+      changes = SPECIAL_D;
+      cp = new_seq;
+    }
+    break;
+  default:
+     break;
+  }
+
+  deltaS = (u16_t)(lwip_ntohs(IPH_ID(ip)) - lwip_ntohs(IPH_ID(&cs->cs_ip)));
+  if (deltaS != 1) {
+    ENCODEZ(deltaS);
+    changes |= NEW_I;
+  }
+  if (TCPH_FLAGS(th) & TCP_PSH) {
+    changes |= TCP_PUSH_BIT;
+  }
+  /*
+   * Grab the cksum before we overwrite it below.  Then update our
+   * state with this packet's header.
+   */
+  deltaA = lwip_ntohs(th->chksum);
+  MEMCPY(&cs->cs_ip, ip, hlen);
+
+  /*
+   * We want to use the original packet as our compressed packet.
+   * (cp - new_seq) is the number of bytes we need for compressed
+   * sequence numbers.  In addition we need one byte for the change
+   * mask, one for the connection id and two for the tcp checksum.
+   * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+   * many bytes of the original packet to toss so subtract the two to
+   * get the new packet size.
+   */
+  deltaS = (u16_t)(cp - new_seq);
+  if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+    comp->last_xmit = cs->cs_id;
+    hlen -= deltaS + 4;
+    if (pbuf_remove_header(np, hlen)){
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+    }
+    cp = (u8_t*)np->payload;
+    *cp++ = (u8_t)(changes | NEW_C);
+    *cp++ = cs->cs_id;
+  } else {
+    hlen -= deltaS + 3;
+    if (pbuf_remove_header(np, hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+    }
+    cp = (u8_t*)np->payload;
+    *cp++ = (u8_t)changes;
+  }
+  *cp++ = (u8_t)(deltaA >> 8);
+  *cp++ = (u8_t)deltaA;
+  MEMCPY(cp, new_seq, deltaS);
+  INCR(vjs_compressed);
+  return (TYPE_COMPRESSED_TCP);
+
+  /*
+   * Update connection state cs & send uncompressed packet (that is,
+   * a regular ip/tcp packet but with the 'conversation id' we hope
+   * to use on future compressed packets in the protocol field).
+   */
+uncompressed:
+  MEMCPY(&cs->cs_ip, ip, hlen);
+  IPH_PROTO_SET(ip, cs->cs_id);
+  comp->last_xmit = cs->cs_id;
+  return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void
+vj_uncompress_err(struct vjcompress *comp)
+{
+  comp->flags |= VJF_TOSS;
+  INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int
+vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp)
+{
+  u32_t hlen;
+  struct cstate *cs;
+  struct ip_hdr *ip;
+
+  ip = (struct ip_hdr *)nb->payload;
+  hlen = IPH_HL(ip) << 2;
+  if (IPH_PROTO(ip) >= MAX_SLOTS
+      || hlen + sizeof(struct tcp_hdr) > nb->len
+      || (hlen += TCPH_HDRLEN_BYTES((struct tcp_hdr *)&((char *)ip)[hlen]))
+          > nb->len
+      || hlen > MAX_HDR) {
+    PPPDEBUG(LOG_INFO, ("vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n",
+      IPH_PROTO(ip), hlen, nb->len));
+    vj_uncompress_err(comp);
+    return -1;
+  }
+  cs = &comp->rstate[comp->last_recv = IPH_PROTO(ip)];
+  comp->flags &=~ VJF_TOSS;
+  IPH_PROTO_SET(ip, IP_PROTO_TCP);
+  /* copy from/to bigger buffers checked above instead of cs->cs_ip and ip
+     just to help static code analysis to see this is correct ;-) */
+  MEMCPY(&cs->cs_hdr, nb->payload, hlen);
+  cs->cs_hlen = (u16_t)hlen;
+  INCR(vjs_uncompressedin);
+  return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header.
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int
+vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp)
+{
+  u8_t *cp;
+  struct tcp_hdr *th;
+  struct cstate *cs;
+  struct vj_u16_t *bp;
+  struct pbuf *n0 = *nb;
+  u32_t tmp;
+  u32_t vjlen, hlen, changes;
+
+  INCR(vjs_compressedin);
+  cp = (u8_t*)n0->payload;
+  changes = *cp++;
+  if (changes & NEW_C) {
+    /*
+     * Make sure the state index is in range, then grab the state.
+     * If we have a good state index, clear the 'discard' flag.
+     */
+    if (*cp >= MAX_SLOTS) {
+      PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: bad cid=%d\n", *cp));
+      goto bad;
+    }
+
+    comp->flags &=~ VJF_TOSS;
+    comp->last_recv = *cp++;
+  } else {
+    /*
+     * this packet has an implicit state index.  If we've
+     * had a line error since the last time we got an
+     * explicit state index, we have to toss the packet.
+     */
+    if (comp->flags & VJF_TOSS) {
+      PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: tossing\n"));
+      INCR(vjs_tossed);
+      return (-1);
+    }
+  }
+  cs = &comp->rstate[comp->last_recv];
+  hlen = IPH_HL(&cs->cs_ip) << 2;
+  th = (struct tcp_hdr *)&((u8_t*)&cs->cs_ip)[hlen];
+  th->chksum = lwip_htons((*cp << 8) | cp[1]);
+  cp += 2;
+  if (changes & TCP_PUSH_BIT) {
+    TCPH_SET_FLAG(th, TCP_PSH);
+  } else {
+    TCPH_UNSET_FLAG(th, TCP_PSH);
+  }
+
+  switch (changes & SPECIALS_MASK) {
+  case SPECIAL_I:
+    {
+      u32_t i = lwip_ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen;
+      /* some compilers can't nest inline assembler.. */
+      tmp = lwip_ntohl(th->ackno) + i;
+      th->ackno = lwip_htonl(tmp);
+      tmp = lwip_ntohl(th->seqno) + i;
+      th->seqno = lwip_htonl(tmp);
+    }
+    break;
+
+  case SPECIAL_D:
+    /* some compilers can't nest inline assembler.. */
+    tmp = lwip_ntohl(th->seqno) + lwip_ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen;
+    th->seqno = lwip_htonl(tmp);
+    break;
+
+  default:
+    if (changes & NEW_U) {
+      TCPH_SET_FLAG(th, TCP_URG);
+      DECODEU(th->urgp);
+    } else {
+      TCPH_UNSET_FLAG(th, TCP_URG);
+    }
+    if (changes & NEW_W) {
+      DECODES(th->wnd);
+    }
+    if (changes & NEW_A) {
+      DECODEL(th->ackno);
+    }
+    if (changes & NEW_S) {
+      DECODEL(th->seqno);
+    }
+    break;
+  }
+  if (changes & NEW_I) {
+    DECODES(cs->cs_ip._id);
+  } else {
+    IPH_ID_SET(&cs->cs_ip, lwip_ntohs(IPH_ID(&cs->cs_ip)) + 1);
+    IPH_ID_SET(&cs->cs_ip, lwip_htons(IPH_ID(&cs->cs_ip)));
+  }
+
+  /*
+   * At this point, cp points to the first byte of data in the
+   * packet.  Fill in the IP total length and update the IP
+   * header checksum.
+   */
+  vjlen = (u16_t)(cp - (u8_t*)n0->payload);
+  if (n0->len < vjlen) {
+    /*
+     * We must have dropped some characters (crc should detect
+     * this but the old slip framing won't)
+     */
+    PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: head buffer %d too short %d\n",
+          n0->len, vjlen));
+    goto bad;
+  }
+
+#if BYTE_ORDER == LITTLE_ENDIAN
+  tmp = n0->tot_len - vjlen + cs->cs_hlen;
+  IPH_LEN_SET(&cs->cs_ip, lwip_htons((u16_t)tmp));
+#else
+  IPH_LEN_SET(&cs->cs_ip, lwip_htons(n0->tot_len - vjlen + cs->cs_hlen));
+#endif
+
+  /* recompute the ip header checksum */
+  bp = (struct vj_u16_t*) &cs->cs_ip;
+  IPH_CHKSUM_SET(&cs->cs_ip, 0);
+  for (tmp = 0; hlen > 0; hlen -= 2) {
+    tmp += (*bp++).v;
+  }
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  tmp = (tmp & 0xffff) + (tmp >> 16);
+  IPH_CHKSUM_SET(&cs->cs_ip,  (u16_t)(~tmp));
+
+  /* Remove the compressed header and prepend the uncompressed header. */
+  if (pbuf_remove_header(n0, vjlen)) {
+    /* Can we cope with this failing?  Just assert for now */
+    LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+    goto bad;
+  }
+
+  if(LWIP_MEM_ALIGN(n0->payload) != n0->payload) {
+    struct pbuf *np;
+
+#if IP_FORWARD
+    /* If IP forwarding is enabled we are using a PBUF_LINK packet type so
+     * the packet is being allocated with enough header space to be
+     * forwarded (to Ethernet for example).
+     */
+    np = pbuf_alloc(PBUF_LINK, n0->len + cs->cs_hlen, PBUF_POOL);
+#else /* IP_FORWARD */
+    np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+#endif /* IP_FORWARD */
+    if(!np) {
+      PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: realign failed\n"));
+      goto bad;
+    }
+
+    if (pbuf_remove_header(np, cs->cs_hlen)) {
+      /* Can we cope with this failing?  Just assert for now */
+      LWIP_ASSERT("pbuf_remove_header failed\n", 0);
+      goto bad;
+    }
+
+    pbuf_take(np, n0->payload, n0->len);
+
+    if(n0->next) {
+      pbuf_chain(np, n0->next);
+      pbuf_dechain(n0);
+    }
+    pbuf_free(n0);
+    n0 = np;
+  }
+
+  if (pbuf_add_header(n0, cs->cs_hlen)) {
+    struct pbuf *np;
+
+    LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+    np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+    if(!np) {
+      PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: prepend failed\n"));
+      goto bad;
+    }
+    pbuf_cat(np, n0);
+    n0 = np;
+  }
+  LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+  MEMCPY(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+  *nb = n0;
+
+  return vjlen;
+
+bad:
+  vj_uncompress_err(comp);
+  return (-1);
+}
+
+#endif /* PPP_SUPPORT && VJ_SUPPORT */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/slipif.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/slipif.c
new file mode 100644
index 000000000..9b175dc3e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/slipif.c
@@ -0,0 +1,558 @@
+/**
+ * @file
+ * SLIP Interface
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson <magnus.ivarsson(at)volvo.com>
+ *         Simon Goldschmidt
+ */
+
+
+/**
+ * @defgroup slipif SLIP
+ * @ingroup netifs
+ *
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send
+ *
+ * Usage: This netif can be used in three ways:\n
+ *        1) For NO_SYS==0, an RX thread can be used which blocks on sio_read()
+ *           until data is received.\n
+ *        2) In your main loop, call slipif_poll() to check for new RX bytes,
+ *           completed packets are fed into netif->input().\n
+ *        3) Call slipif_received_byte[s]() from your serial RX ISR and
+ *           slipif_process_rxqueue() from your main loop. ISR level decodes
+ *           packets and puts completed packets on a queue which is fed into
+ *           the stack from the main loop (needs SYS_LIGHTWEIGHT_PROT for
+ *           pbuf_alloc to work on ISR level!).
+ *
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/sys.h"
+#include "lwip/sio.h"
+
+#define SLIP_END     0xC0 /* 0300: start and end of every packet */
+#define SLIP_ESC     0xDB /* 0333: escape start (one byte escaped data follows) */
+#define SLIP_ESC_END 0xDC /* 0334: following escape: original byte is 0xC0 (END) */
+#define SLIP_ESC_ESC 0xDD /* 0335: following escape: original byte is 0xDB (ESC) */
+
+/** Maximum packet size that is received by this netif */
+#ifndef SLIP_MAX_SIZE
+#define SLIP_MAX_SIZE 1500
+#endif
+
+/** Define this to the interface speed for SNMP
+ * (sio_fd is the sio_fd_t returned by sio_open).
+ * The default value of zero means 'unknown'.
+ */
+#ifndef SLIP_SIO_SPEED
+#define SLIP_SIO_SPEED(sio_fd) 0
+#endif
+
+enum slipif_recv_state {
+  SLIP_RECV_NORMAL,
+  SLIP_RECV_ESCAPE
+};
+
+struct slipif_priv {
+  sio_fd_t sd;
+  /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */
+  struct pbuf *p, *q;
+  u8_t state;
+  u16_t i, recved;
+#if SLIP_RX_FROM_ISR
+  struct pbuf *rxpackets;
+#endif
+};
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param p the pbuf chain packet to send
+ * @return always returns ERR_OK since the serial layer does not provide return values
+ */
+static err_t
+slipif_output(struct netif *netif, struct pbuf *p)
+{
+  struct slipif_priv *priv;
+  struct pbuf *q;
+  u16_t i;
+  u8_t c;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+  LWIP_ASSERT("p != NULL", (p != NULL));
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_output: sending %"U16_F" bytes\n", p->tot_len));
+  priv = (struct slipif_priv *)netif->state;
+
+  /* Send pbuf out on the serial I/O device. */
+  /* Start with packet delimiter. */
+  sio_send(SLIP_END, priv->sd);
+
+  for (q = p; q != NULL; q = q->next) {
+    for (i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+        case SLIP_END:
+          /* need to escape this byte (0xC0 -> 0xDB, 0xDC) */
+          sio_send(SLIP_ESC, priv->sd);
+          sio_send(SLIP_ESC_END, priv->sd);
+          break;
+        case SLIP_ESC:
+          /* need to escape this byte (0xDB -> 0xDB, 0xDD) */
+          sio_send(SLIP_ESC, priv->sd);
+          sio_send(SLIP_ESC_ESC, priv->sd);
+          break;
+        default:
+          /* normal byte - no need for escaping */
+          sio_send(c, priv->sd);
+          break;
+      }
+    }
+  }
+  /* End with packet delimiter. */
+  sio_send(SLIP_END, priv->sd);
+  return ERR_OK;
+}
+
+#if LWIP_IPV4
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param p the pbuf chain packet to send
+ * @param ipaddr the ip address to send the packet to (not used for slipif)
+ * @return always returns ERR_OK since the serial layer does not provide return values
+ */
+static err_t
+slipif_output_v4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
+{
+  LWIP_UNUSED_ARG(ipaddr);
+  return slipif_output(netif, p);
+}
+#endif /* LWIP_IPV4 */
+
+#if LWIP_IPV6
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send()
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param p the pbuf chain packet to send
+ * @param ipaddr the ip address to send the packet to (not used for slipif)
+ * @return always returns ERR_OK since the serial layer does not provide return values
+ */
+static err_t
+slipif_output_v6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr)
+{
+  LWIP_UNUSED_ARG(ipaddr);
+  return slipif_output(netif, p);
+}
+#endif /* LWIP_IPV6 */
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @param c received character (multiple calls to this function will
+ *        return a complete packet, NULL is returned before - used for polling)
+ * @return The IP packet when SLIP_END is received
+ */
+static struct pbuf *
+slipif_rxbyte(struct netif *netif, u8_t c)
+{
+  struct slipif_priv *priv;
+  struct pbuf *t;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = (struct slipif_priv *)netif->state;
+
+  switch (priv->state) {
+    case SLIP_RECV_NORMAL:
+      switch (c) {
+        case SLIP_END:
+          if (priv->recved > 0) {
+            /* Received whole packet. */
+            /* Trim the pbuf to the size of the received packet. */
+            pbuf_realloc(priv->q, priv->recved);
+
+            LINK_STATS_INC(link.recv);
+
+            LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet (%"U16_F" bytes)\n", priv->recved));
+            t = priv->q;
+            priv->p = priv->q = NULL;
+            priv->i = priv->recved = 0;
+            return t;
+          }
+          return NULL;
+        case SLIP_ESC:
+          priv->state = SLIP_RECV_ESCAPE;
+          return NULL;
+        default:
+          break;
+      } /* end switch (c) */
+      break;
+    case SLIP_RECV_ESCAPE:
+      /* un-escape END or ESC bytes, leave other bytes
+         (although that would be a protocol error) */
+      switch (c) {
+        case SLIP_ESC_END:
+          c = SLIP_END;
+          break;
+        case SLIP_ESC_ESC:
+          c = SLIP_ESC;
+          break;
+        default:
+          break;
+      }
+      priv->state = SLIP_RECV_NORMAL;
+      break;
+    default:
+      break;
+  } /* end switch (priv->state) */
+
+  /* byte received, packet not yet completely received */
+  if (priv->p == NULL) {
+    /* allocate a new pbuf */
+    LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+    priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - PBUF_LINK_ENCAPSULATION_HLEN), PBUF_POOL);
+
+    if (priv->p == NULL) {
+      LINK_STATS_INC(link.drop);
+      LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+      /* don't process any further since we got no pbuf to receive to */
+      return NULL;
+    }
+
+    if (priv->q != NULL) {
+      /* 'chain' the pbuf to the existing chain */
+      pbuf_cat(priv->q, priv->p);
+    } else {
+      /* p is the first pbuf in the chain */
+      priv->q = priv->p;
+    }
+  }
+
+  /* this automatically drops bytes if > SLIP_MAX_SIZE */
+  if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) {
+    ((u8_t *)priv->p->payload)[priv->i] = c;
+    priv->recved++;
+    priv->i++;
+    if (priv->i >= priv->p->len) {
+      /* on to the next pbuf */
+      priv->i = 0;
+      if (priv->p->next != NULL && priv->p->next->len > 0) {
+        /* p is a chain, on to the next in the chain */
+        priv->p = priv->p->next;
+      } else {
+        /* p is a single pbuf, set it to NULL so next time a new
+         * pbuf is allocated */
+        priv->p = NULL;
+      }
+    }
+  }
+  return NULL;
+}
+
+/** Like slipif_rxbyte, but passes completed packets to netif->input
+ *
+ * @param netif The lwip network interface structure for this slipif
+ * @param c received character
+ */
+static void
+slipif_rxbyte_input(struct netif *netif, u8_t c)
+{
+  struct pbuf *p;
+  p = slipif_rxbyte(netif, c);
+  if (p != NULL) {
+    if (netif->input(p, netif) != ERR_OK) {
+      pbuf_free(p);
+    }
+  }
+}
+
+#if SLIP_USE_RX_THREAD
+/**
+ * The SLIP input thread.
+ *
+ * Feed the IP layer with incoming packets
+ *
+ * @param nf the lwip network interface structure for this slipif
+ */
+static void
+slipif_loop_thread(void *nf)
+{
+  u8_t c;
+  struct netif *netif = (struct netif *)nf;
+  struct slipif_priv *priv = (struct slipif_priv *)netif->state;
+
+  while (1) {
+    if (sio_read(priv->sd, &c, 1) > 0) {
+      slipif_rxbyte_input(netif, c);
+    }
+  }
+}
+#endif /* SLIP_USE_RX_THREAD */
+
+/**
+ * @ingroup slipif
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ *
+ * @param netif the lwip network interface structure for this slipif
+ * @return ERR_OK if serial line could be opened,
+ *         ERR_MEM if no memory could be allocated,
+ *         ERR_IF is serial line couldn't be opened
+ *
+ * @note If netif->state is interpreted as an u8_t serial port number.
+ *
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+  struct slipif_priv *priv;
+  u8_t sio_num;
+
+  LWIP_ASSERT("slipif needs an input callback", netif->input != NULL);
+
+  /* netif->state contains serial port number */
+  sio_num = LWIP_PTR_NUMERIC_CAST(u8_t, netif->state);
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)sio_num));
+
+  /* Allocate private data */
+  priv = (struct slipif_priv *)mem_malloc(sizeof(struct slipif_priv));
+  if (!priv) {
+    return ERR_MEM;
+  }
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+#if LWIP_IPV4
+  netif->output = slipif_output_v4;
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+  netif->output_ip6 = slipif_output_v6;
+#endif /* LWIP_IPV6 */
+  netif->mtu = SLIP_MAX_SIZE;
+
+  /* Try to open the serial port. */
+  priv->sd = sio_open(sio_num);
+  if (!priv->sd) {
+    /* Opening the serial port failed. */
+    mem_free(priv);
+    return ERR_IF;
+  }
+
+  /* Initialize private data */
+  priv->p = NULL;
+  priv->q = NULL;
+  priv->state = SLIP_RECV_NORMAL;
+  priv->i = 0;
+  priv->recved = 0;
+#if SLIP_RX_FROM_ISR
+  priv->rxpackets = NULL;
+#endif
+
+  netif->state = priv;
+
+  /* initialize the snmp variables and counters inside the struct netif */
+  MIB2_INIT_NETIF(netif, snmp_ifType_slip, SLIP_SIO_SPEED(priv->sd));
+
+#if SLIP_USE_RX_THREAD
+  /* Create a thread to poll the serial line. */
+  sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif,
+                 SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO);
+#endif /* SLIP_USE_RX_THREAD */
+  return ERR_OK;
+}
+
+/**
+ * @ingroup slipif
+ * Polls the serial device and feeds the IP layer with incoming packets.
+ *
+ * @param netif The lwip network interface structure for this slipif
+ */
+void
+slipif_poll(struct netif *netif)
+{
+  u8_t c;
+  struct slipif_priv *priv;
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = (struct slipif_priv *)netif->state;
+
+  while (sio_tryread(priv->sd, &c, 1) > 0) {
+    slipif_rxbyte_input(netif, c);
+  }
+}
+
+#if SLIP_RX_FROM_ISR
+/**
+ * @ingroup slipif
+ * Feeds the IP layer with incoming packets that were receive
+ *
+ * @param netif The lwip network interface structure for this slipif
+ */
+void
+slipif_process_rxqueue(struct netif *netif)
+{
+  struct slipif_priv *priv;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  priv = (struct slipif_priv *)netif->state;
+
+  SYS_ARCH_PROTECT(old_level);
+  while (priv->rxpackets != NULL) {
+    struct pbuf *p = priv->rxpackets;
+#if SLIP_RX_QUEUE
+    /* dequeue packet */
+    struct pbuf *q = p;
+    while ((q->len != q->tot_len) && (q->next != NULL)) {
+      q = q->next;
+    }
+    priv->rxpackets = q->next;
+    q->next = NULL;
+#else /* SLIP_RX_QUEUE */
+    priv->rxpackets = NULL;
+#endif /* SLIP_RX_QUEUE */
+    SYS_ARCH_UNPROTECT(old_level);
+    if (netif->input(p, netif) != ERR_OK) {
+      pbuf_free(p);
+    }
+    SYS_ARCH_PROTECT(old_level);
+  }
+  SYS_ARCH_UNPROTECT(old_level);
+}
+
+/** Like slipif_rxbyte, but queues completed packets.
+ *
+ * @param netif The lwip network interface structure for this slipif
+ * @param data Received serial byte
+ */
+static void
+slipif_rxbyte_enqueue(struct netif *netif, u8_t data)
+{
+  struct pbuf *p;
+  struct slipif_priv *priv = (struct slipif_priv *)netif->state;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  p = slipif_rxbyte(netif, data);
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    if (priv->rxpackets != NULL) {
+#if SLIP_RX_QUEUE
+      /* queue multiple pbufs */
+      struct pbuf *q = p;
+      while (q->next != NULL) {
+        q = q->next;
+      }
+      q->next = p;
+    } else {
+#else /* SLIP_RX_QUEUE */
+      pbuf_free(priv->rxpackets);
+    }
+    {
+#endif /* SLIP_RX_QUEUE */
+      priv->rxpackets = p;
+    }
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * @ingroup slipif
+ * Process a received byte, completed packets are put on a queue that is
+ * fed into IP through slipif_process_rxqueue().
+ *
+ * This function can be called from ISR if SYS_LIGHTWEIGHT_PROT is enabled.
+ *
+ * @param netif The lwip network interface structure for this slipif
+ * @param data received character
+ */
+void
+slipif_received_byte(struct netif *netif, u8_t data)
+{
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+  slipif_rxbyte_enqueue(netif, data);
+}
+
+/**
+ * @ingroup slipif
+ * Process multiple received byte, completed packets are put on a queue that is
+ * fed into IP through slipif_process_rxqueue().
+ *
+ * This function can be called from ISR if SYS_LIGHTWEIGHT_PROT is enabled.
+ *
+ * @param netif The lwip network interface structure for this slipif
+ * @param data received character
+ * @param len Number of received characters
+ */
+void
+slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len)
+{
+  u8_t i;
+  u8_t *rxdata = data;
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+  LWIP_ASSERT("netif->state != NULL", (netif->state != NULL));
+
+  for (i = 0; i < len; i++, rxdata++) {
+    slipif_rxbyte_enqueue(netif, *rxdata);
+  }
+}
+#endif /* SLIP_RX_FROM_ISR */
diff --git a/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/zepif.c b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/zepif.c
new file mode 100644
index 000000000..b4033030b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/LwIP/LwIP/src/netif/zepif.c
@@ -0,0 +1,300 @@
+/**
+ * @file
+ *
+ * @defgroup zepif ZEP - ZigBee Encapsulation Protocol
+ * @ingroup netifs
+ * A netif implementing the ZigBee Encapsulation Protocol (ZEP).
+ * This is used to tunnel 6LowPAN over UDP.
+ *
+ * Usage (there must be a default netif before!):
+ * @code{.c}
+ *   netif_add(&zep_netif, NULL, NULL, NULL, NULL, zepif_init, tcpip_6lowpan_input);
+ *   netif_create_ip6_linklocal_address(&zep_netif, 1);
+ *   netif_set_up(&zep_netif);
+ *   netif_set_link_up(&zep_netif);
+ * @endcode
+ */
+
+/*
+ * Copyright (c) 2018 Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Simon Goldschmidt <goldsimon@gmx.de>
+ *
+ */
+
+#include "netif/zepif.h"
+
+#if LWIP_IPV6 && LWIP_UDP
+
+#include "netif/lowpan6.h"
+#include "lwip/udp.h"
+#include "lwip/timeouts.h"
+#include <string.h>
+
+/** Define this to 1 to loop back TX packets for testing */
+#ifndef ZEPIF_LOOPBACK
+#define ZEPIF_LOOPBACK    0
+#endif
+
+#define ZEP_MAX_DATA_LEN  127
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct zep_hdr {
+  PACK_STRUCT_FLD_8(u8_t prot_id[2]);
+  PACK_STRUCT_FLD_8(u8_t prot_version);
+  PACK_STRUCT_FLD_8(u8_t type);
+  PACK_STRUCT_FLD_8(u8_t channel_id);
+  PACK_STRUCT_FIELD(u16_t device_id);
+  PACK_STRUCT_FLD_8(u8_t crc_mode);
+  PACK_STRUCT_FLD_8(u8_t unknown_1);
+  PACK_STRUCT_FIELD(u32_t timestamp[2]);
+  PACK_STRUCT_FIELD(u32_t seq_num);
+  PACK_STRUCT_FLD_8(u8_t unknown_2[10]);
+  PACK_STRUCT_FLD_8(u8_t len);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+struct zepif_state {
+  struct zepif_init init;
+  struct udp_pcb *pcb;
+  u32_t seqno;
+};
+
+static u8_t zep_lowpan_timer_running;
+
+/* Helper function that calls the 6LoWPAN timer and reschedules itself */
+static void
+zep_lowpan_timer(void *arg)
+{
+  lowpan6_tmr();
+  if (zep_lowpan_timer_running) {
+    sys_timeout(LOWPAN6_TMR_INTERVAL, zep_lowpan_timer, arg);
+  }
+}
+
+/* Pass received pbufs into 6LowPAN netif */
+static void
+zepif_udp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+               const ip_addr_t *addr, u16_t port)
+{
+  err_t err;
+  struct netif *netif_lowpan6 = (struct netif *)arg;
+  struct zep_hdr *zep;
+
+  LWIP_ASSERT("arg != NULL", arg != NULL);
+  LWIP_ASSERT("pcb != NULL", pcb != NULL);
+  LWIP_UNUSED_ARG(pcb); /* for LWIP_NOASSERT */
+  LWIP_UNUSED_ARG(addr);
+  LWIP_UNUSED_ARG(port);
+  if (p == NULL) {
+    return;
+  }
+
+  /* Parse and hide the ZEP header */
+  if (p->len < sizeof(struct zep_hdr)) {
+    /* need the zep_hdr in one piece */
+    goto err_return;
+  }
+  zep = (struct zep_hdr *)p->payload;
+  if (zep->prot_id[0] != 'E') {
+    goto err_return;
+  }
+  if (zep->prot_id[1] != 'X') {
+    goto err_return;
+  }
+  if (zep->prot_version != 2) {
+    /* we only support this version for now */
+    goto err_return;
+  }
+  if (zep->type != 1) {
+    goto err_return;
+  }
+  if (zep->crc_mode != 1) {
+    goto err_return;
+  }
+  if (zep->len != p->tot_len - sizeof(struct zep_hdr)) {
+    goto err_return;
+  }
+  /* everything seems to be OK, hide the ZEP header */
+  if (pbuf_remove_header(p, sizeof(struct zep_hdr))) {
+    goto err_return;
+  }
+  /* TODO Check CRC? */
+  /* remove CRC trailer */
+  pbuf_realloc(p, p->tot_len - 2);
+
+  /* Call into 6LoWPAN code. */
+  err = netif_lowpan6->input(p, netif_lowpan6);
+  if (err == ERR_OK) {
+    return;
+  }
+err_return:
+  pbuf_free(p);
+}
+
+/* Send 6LoWPAN TX packets as UDP broadcast */
+static err_t
+zepif_linkoutput(struct netif *netif, struct pbuf *p)
+{
+  err_t err;
+  struct pbuf *q;
+  struct zep_hdr *zep;
+  struct zepif_state *state;
+
+  LWIP_ASSERT("invalid netif", netif != NULL);
+  LWIP_ASSERT("invalid pbuf", p != NULL);
+
+  if (p->tot_len > ZEP_MAX_DATA_LEN) {
+    return ERR_VAL;
+  }
+  LWIP_ASSERT("TODO: support chained pbufs", p->next == NULL);
+
+  state = (struct zepif_state *)netif->state;
+  LWIP_ASSERT("state->pcb != NULL", state->pcb != NULL);
+
+  q = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct zep_hdr) + p->tot_len, PBUF_RAM);
+  if (q == NULL) {
+    return ERR_MEM;
+  }
+  zep = (struct zep_hdr *)q->payload;
+  memset(zep, 0, sizeof(struct zep_hdr));
+  zep->prot_id[0] = 'E';
+  zep->prot_id[1] = 'X';
+  zep->prot_version = 2;
+  zep->type = 1; /* Data */
+  zep->channel_id = 0; /* whatever */
+  zep->device_id = lwip_htons(1); /* whatever */
+  zep->crc_mode = 1;
+  zep->unknown_1 = 0xff;
+  zep->seq_num = lwip_htonl(state->seqno);
+  state->seqno++;
+  zep->len = (u8_t)p->tot_len;
+
+  err = pbuf_take_at(q, p->payload, p->tot_len, sizeof(struct zep_hdr));
+  if (err == ERR_OK) {
+#if ZEPIF_LOOPBACK
+    zepif_udp_recv(netif, state->pcb, pbuf_clone(PBUF_RAW, PBUF_RAM, q), NULL, 0);
+#endif
+    err = udp_sendto(state->pcb, q, state->init.zep_dst_ip_addr, state->init.zep_dst_udp_port);
+  }
+  pbuf_free(q);
+
+  return err;
+}
+
+/**
+ * @ingroup zepif
+ * Set up a raw 6LowPAN netif and surround it with input- and output
+ * functions for ZEP
+ */
+err_t
+zepif_init(struct netif *netif)
+{
+  err_t err;
+  struct zepif_init *init_state = (struct zepif_init *)netif->state;
+  struct zepif_state *state = (struct zepif_state *)mem_malloc(sizeof(struct zepif_state));
+
+  LWIP_ASSERT("zepif needs an input callback", netif->input != NULL);
+
+  if (state == NULL) {
+    return ERR_MEM;
+  }
+  memset(state, 0, sizeof(struct zepif_state));
+  if (init_state != NULL) {
+    memcpy(&state->init, init_state, sizeof(struct zepif_init));
+  }
+  if (state->init.zep_src_udp_port == 0) {
+    state->init.zep_src_udp_port = ZEPIF_DEFAULT_UDP_PORT;
+  }
+  if (state->init.zep_dst_udp_port == 0) {
+    state->init.zep_dst_udp_port = ZEPIF_DEFAULT_UDP_PORT;
+  }
+#if LWIP_IPV4
+  if (state->init.zep_dst_ip_addr == NULL) {
+    /* With IPv4 enabled, default to broadcasting packets if no address is set */
+    state->init.zep_dst_ip_addr = IP_ADDR_BROADCAST;
+  }
+#endif /* LWIP_IPV4 */
+
+  netif->state = NULL;
+
+  state->pcb = udp_new_ip_type(IPADDR_TYPE_ANY);
+  if (state->pcb == NULL) {
+    err = ERR_MEM;
+    goto err_ret;
+  }
+  err = udp_bind(state->pcb, state->init.zep_src_ip_addr, state->init.zep_src_udp_port);
+  if (err != ERR_OK) {
+    goto err_ret;
+  }
+  if (state->init.zep_netif != NULL) {
+    udp_bind_netif(state->pcb, state->init.zep_netif);
+  }
+  LWIP_ASSERT("udp_bind(lowpan6_broadcast_pcb) failed", err == ERR_OK);
+  ip_set_option(state->pcb, SOF_BROADCAST);
+  udp_recv(state->pcb, zepif_udp_recv, netif);
+
+  err = lowpan6_if_init(netif);
+  LWIP_ASSERT("lowpan6_if_init set a state", netif->state == NULL);
+  if (err == ERR_OK) {
+    netif->state = state;
+    netif->hwaddr_len = 6;
+    if (init_state != NULL) {
+      memcpy(netif->hwaddr, init_state->addr, 6);
+    } else {
+      u8_t i;
+      for (i = 0; i < 6; i++) {
+        netif->hwaddr[i] = i;
+      }
+      netif->hwaddr[0] &= 0xfc;
+    }
+    netif->linkoutput = zepif_linkoutput;
+
+    if (!zep_lowpan_timer_running) {
+      sys_timeout(LOWPAN6_TMR_INTERVAL, zep_lowpan_timer, NULL);
+      zep_lowpan_timer_running = 1;
+    }
+
+    return ERR_OK;
+  }
+
+err_ret:
+  if (state->pcb != NULL) {
+    udp_remove(state->pcb);
+  }
+  mem_free(state);
+  return err;
+}
+
+#endif /* LWIP_IPV6 && LWIP_UDP */
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/AnalogIOExamples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/AnalogIOExamples.atsln
new file mode 100644
index 000000000..31ee84b97
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/AnalogIOExamples.atsln
@@ -0,0 +1,44 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ReadAnalogInput", "ReadAnalogInput\ReadAnalogInput.cppproj", "{2FB82D7F-5764-4F0C-9056-2579531D256C}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WriteAnalogCurrentOutput", "WriteAnalogCurrentOutput\WriteAnalogCurrentOutput.cppproj", "{96490400-80FE-478E-86E0-0CBBFF5C1651}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{2FB82D7F-5764-4F0C-9056-2579531D256C}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2FB82D7F-5764-4F0C-9056-2579531D256C}.Debug|ARM.Build.0 = Debug|ARM
+		{2FB82D7F-5764-4F0C-9056-2579531D256C}.Release|ARM.ActiveCfg = Release|ARM
+		{2FB82D7F-5764-4F0C-9056-2579531D256C}.Release|ARM.Build.0 = Release|ARM
+		{96490400-80FE-478E-86E0-0CBBFF5C1651}.Debug|ARM.ActiveCfg = Debug|ARM
+		{96490400-80FE-478E-86E0-0CBBFF5C1651}.Debug|ARM.Build.0 = Debug|ARM
+		{96490400-80FE-478E-86E0-0CBBFF5C1651}.Release|ARM.ActiveCfg = Release|ARM
+		{96490400-80FE-478E-86E0-0CBBFF5C1651}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cpp
new file mode 100644
index 000000000..3665cdbbd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cpp
@@ -0,0 +1,137 @@
+/*
+ * Title: ReadAnalogInput
+ *
+ * Objective:
+ *    This example demonstrates how to read the analog voltage of an analog
+ *    input. ClearCore analog inputs are natively compatible with 0-10V signals,
+ *    and 0-20mA signals with addition of an external resistor (see ClearCore
+ *    manual link below for wiring).
+ *
+ * Description:
+ *    This example sets up pin A-12 as an analog input, queries the value on
+ *    that connector every second, and calculates the input voltage. This
+ *    calculated voltage is written/displayed to the USB serial port.
+ *    Connectors IO-0 through IO-5 will act as a coarse meter of the voltage
+ *    read-in by turning on their outputs and LEDs (with more than 0V and less
+ *    than 2V, IO-0 will be on as an output. With ~2V and less than 4V, IO-0 and
+ *    IO-1 will be on; and so on until, with near 10V read in, IO-0 through IO-5
+ *    will be turned on).
+ *
+ * Requirements:
+ * ** An analog input source connected to A-12.
+ * ** Optional: LEDs connected to IO-0 through IO-5 to act as a more prominent
+ *    voltage meter than the ClearCore's onboard LEDs.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the bit-depth of the ADC readings (8-bit, 10-bit, or 12-bit)
+// Supported adcResolution values are 8, 10, and 12
+#define adcResolution 12
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial connector to use:
+//   ConnectorUsb, ConnectorCOM0, or ConnectorCOM1
+#define SerialPort ConnectorUsb
+
+int main() {
+    // Initialize the serial port for printing analog voltage readings and wait
+    // up to 5 seconds for a port to open. Serial communication is not required
+    // for this example to run, however without it only the coarse LED meter
+    // can be used to read the analog signal.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Make a voltage meter display with the I/O pins.
+    ConnectorIO0.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO1.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO2.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO3.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO4.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO5.Mode(Connector::OUTPUT_DIGITAL);
+
+    // Clear out the state of our voltage meter to start.
+    ConnectorIO0.State(false);
+    ConnectorIO1.State(false);
+    ConnectorIO2.State(false);
+    ConnectorIO3.State(false);
+    ConnectorIO4.State(false);
+    ConnectorIO5.State(false);
+
+    // Since analog inputs default to analog input mode, there's no need to
+    // call Mode().
+
+    // Set the resolution of the ADC.
+    AdcMgr.AdcResolution(adcResolution);
+
+    while (true) {
+        // Read the analog input (A-9 through A-12 may be configured as analog
+        // inputs).
+        int16_t adcResult = ConnectorA12.State();
+        // Convert the reading to a voltage.
+        double inputVoltage = 10.0 * adcResult / ((1 << adcResolution) - 1);
+
+        // Display the voltage reading to the serial port.
+        SerialPort.Send("A-12 input voltage: ");
+        SerialPort.Send(inputVoltage);
+        SerialPort.SendLine("V.");
+
+        // Write the voltage reading to the voltage meter display pins
+        // (IO-0 through IO-5).
+        if (inputVoltage > 0.1) {
+            ConnectorIO0.State(true);
+        }
+        else {
+            ConnectorIO0.State(false);
+        }
+        if (inputVoltage > 2.0) {
+            ConnectorIO1.State(true);
+        }
+        else {
+            ConnectorIO1.State(false);
+        }
+        if (inputVoltage > 4.0) {
+            ConnectorIO2.State(true);
+        }
+        else {
+            ConnectorIO2.State(false);
+        }
+        if (inputVoltage > 6.0) {
+            ConnectorIO3.State(true);
+        }
+        else {
+            ConnectorIO3.State(false);
+        }
+        if (inputVoltage > 8.0) {
+            ConnectorIO4.State(true);
+        }
+        else {
+            ConnectorIO4.State(false);
+        }
+        if (inputVoltage >= 9.9) {
+            ConnectorIO5.State(true);
+        }
+        else {
+            ConnectorIO5.State(false);
+        }
+
+        // Wait a second before the next reading.
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cppproj
new file mode 100644
index 000000000..cadca7cc0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
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+    <avrdevice>ATSAME53N19A</avrdevice>
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+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>ReadAnalogInput</Name>
+    <RootNamespace>Examples</RootNamespace>
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+    <OverrideVtor>false</OverrideVtor>
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+    <EraseKey />
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+  </PropertyGroup>
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+    <ToolchainSettings>
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+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ReadAnalogInput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cpp
new file mode 100644
index 000000000..eb26dd843
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cpp
@@ -0,0 +1,48 @@
+/*
+ * Title: WriteAnalogCurrentOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write analog current values to an analog
+ *    current output connector.
+ *
+ * Description:
+ *    This example configures pin IO-0 as an analog current output. It outputs
+ *    a repeating analog signal, starting at 0mA, increasing to 20mA, and
+ *    decreasing back to 0mA.
+ *
+ * Requirements:
+ * ** Connect a device to IO-0 which takes in analog current.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+
+int main() {
+    // Set up connector IO-0 in analog output mode.
+    // Note that only connector IO-0 is capable of analog current output.
+    ConnectorIO0.Mode(Connector::OUTPUT_ANALOG);
+
+    while (true) {
+        // Ramp the current output of IO-0 up to 20 mA (20,000 uA). If using an
+        // operating range of 4-20 mA, change the lower bounds of the loops
+        // below to 4000 instead of 0.
+        for (uint16_t microAmps = 0; microAmps < 20000; microAmps += 10) {
+            ConnectorIO0.OutputCurrent(microAmps);
+            Delay_ms(2);
+        }
+
+        // Ramp the current output of IO-0 back down.
+        for (uint16_t microAmps = 20000; microAmps > 0; microAmps -= 10) {
+            ConnectorIO0.OutputCurrent(microAmps);
+            Delay_ms(2);
+        }
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cppproj
new file mode 100644
index 000000000..ab399f77f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>WriteAnalogCurrentOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
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+    <OverrideVtor>false</OverrideVtor>
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+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
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+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
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+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
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+    </AsfFrameworkConfig>
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+    <avrtoolserialnumber>
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+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
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+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
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+    <com_atmel_avrdbg_tool_samice>
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+      <ToolName>J-Link</ToolName>
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+  </armgcc.compiler.directories.IncludePaths>
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+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
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+  <armgcccpp.compiler.symbols.DefSymbols>
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+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
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+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
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+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
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+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
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+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
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+      <Value>../../../../LwIP/LwIP/src/include</Value>
+      <Value>../../../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
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+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
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+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+</ArmGccCpp>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="WriteAnalogCurrentOutput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
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+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/CCIO8Examples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/CCIO8Examples.atsln
new file mode 100644
index 000000000..3200a7a65
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/CCIO8Examples.atsln
@@ -0,0 +1,52 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCoreIOExpansionBoard", "ClearCoreIOExpansionBoard\ClearCoreIOExpansionBoard.cppproj", "{1E4E3CD7-ED5D-4003-9E24-DCCF30DED5B1}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ReadCCIODigitalInput", "ReadCCIODigitalInput\ReadCCIODigitalInput.cppproj", "{1B9FA3E4-1CB9-4E4A-A259-F6FE98878256}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WriteCCIODigitalOutput", "WriteCCIODigitalOutput\WriteCCIODigitalOutput.cppproj", "{9E409DB5-FB85-4708-AB6F-E22F6B12FCCA}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WriteCCIODigitalOutputPulses", "WriteCCIODigitalOutputPulses\WriteCCIODigitalOutputPulses.cppproj", "{AEDBBEDD-EF5D-4AAB-9403-5C93C3BBF566}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
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diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cpp
new file mode 100644
index 000000000..fd7b89c59
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cpp
@@ -0,0 +1,182 @@
+/*
+ * Title: ClearCoreIOExpansionBoard
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    read from or write to it. Up to 8 total CCIO-8 boards can be used.
+ *
+ * Description:
+ *    This example sets up COM-0 to control up to 8 CCIO-8 Expansion Boards,
+ *    sets all CCIO-8 connectors to be either inputs or outputs depending on the
+ *    selected mode. In input mode, pin statuses are printed to the USB serial
+ *    port. In output mode, all pins outputs are sequentially turned on then off.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board, with power wired, and connected to COM-0. Any
+ *    other CCIO-8 boards should be chained off of this first board
+ * ** Edit the value of "inputMode" below to select input mode or output mode
+ * ** (For input mode) A number of inputs, like switches, wired to CCIO-8
+ *    connectors.
+ * ** (For output mode) A number of outputs, like LEDs, wired to CCIO-8
+ *    connectors.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which ClearCore serial COM port is connected to the "COM IN" port
+// of the CCIO-8 board. COM-1 may also be used.
+#define CcioPort ConnectorCOM0
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// Set this flag to true to use the CCIO-8 connectors as digital inputs.
+// Set it to false to use the CCIO-8 connectors as digital outputs.
+const bool inputMode = true;
+
+uint8_t ccioBoardCount;     // Store the number of connected CCIO-8 boards here.
+uint8_t ccioPinCount;       // Store the number of connected CCIO-8 pins here.
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// These will be used to format the text that is printed to the serial port.
+#define MAX_MSG_LEN 80
+char msg[MAX_MSG_LEN + 1];
+
+int main() {
+    // Set up serial communication to display CCIO-8 state.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Initialize the CCIO-8 board.
+    ccioBoardCount = CcioMgr.CcioCount();
+    // CCIO_PINS_PER_BOARD is a constant defined in the main ClearCore library
+    // that evaluates to 8.
+    ccioPinCount = ccioBoardCount * CCIO_PINS_PER_BOARD;
+
+    // Print the number of discovered CCIO-8 boards to the serial port.
+    snprintf(msg, MAX_MSG_LEN, "Discovered %d CCIO-8 board", ccioBoardCount);
+    SerialPort.Send(msg);
+
+    if (ccioBoardCount != 1) {
+        SerialPort.Send("s");
+    }
+    SerialPort.SendLine("...");
+    SerialPort.SendLine();
+
+    if (!inputMode) {
+        // Set each CCIO-8 pin to the correct mode. The CCIO-8 pins default to
+        // being an input so the pin mode doesn't need to be set for input mode.
+        for (uint8_t ccioPinIndex = 0; ccioPinIndex < ccioPinCount; ccioPinIndex++) {
+            CcioMgr.PinByIndex(static_cast<ClearCorePins>(CLEARCORE_PIN_CCIOA0 +
+                               ccioPinIndex))->Mode(Connector::OUTPUT_DIGITAL);
+        }
+    }
+
+    while (true) {
+        // Make sure the CCIO-8 link is established.
+        if (CcioMgr.LinkBroken()) {
+            uint32_t lastStatusTime = Milliseconds();
+            SerialPort.SendLine("The CCIO-8 link is broken!");
+            // Make sure the CCIO-8 link is established.
+            while (CcioMgr.LinkBroken()) {
+                if (Milliseconds() - lastStatusTime > 1000) {
+                    SerialPort.SendLine("The CCIO-8 link is still broken!");
+                    lastStatusTime = Milliseconds();
+                }
+            }
+            SerialPort.SendLine("The CCIO-8 link is online again!");
+        }
+
+        // ClearCore can automatically detect when the number of attached CCIO-8
+        // boards changes. Check to see if there's been a change.
+        uint8_t newBoardCount = CcioMgr.CcioCount();
+        if (ccioBoardCount != newBoardCount) {
+            snprintf(msg, MAX_MSG_LEN, "CCIO-8 board count changed from %d to %d.",
+                     ccioBoardCount, newBoardCount);
+            SerialPort.SendLine(msg);
+            ccioPinCount = newBoardCount * CCIO_PINS_PER_BOARD;
+            ccioBoardCount = newBoardCount;
+        }
+
+        // With one CCIO-8 board attached, we have control over eight additional
+        // digital I/O connectors. On these connectors, we can perform digital
+        // reads and non-PWM digital writes.
+        if (inputMode) {
+            // Read the digital state of CCIO-8 connectors 0 through 7 as inputs.
+            for (uint8_t ccioPinIndex = 0; ccioPinIndex < CCIO_PINS_PER_BOARD;
+                    ccioPinIndex++) {
+                uint16_t state = CcioMgr.PinByIndex(static_cast<ClearCorePins>
+                                     (CLEARCORE_PIN_CCIOA0 + ccioPinIndex))->State();
+
+                snprintf(msg, MAX_MSG_LEN, "CCIO-A%d:   ", ccioPinIndex);
+                SerialPort.Send(msg);
+
+                if (state) {
+                    SerialPort.SendLine("ON");
+                }
+                else {
+                    SerialPort.SendLine("OFF");
+                }
+            }
+
+            // If you have multiple CCIO-8 boards attached, individual printouts
+            // become hard to read. We can access all of the CCIO-8 bits at once
+            // and print them out in hex.
+            snprintf(msg, MAX_MSG_LEN, "All CCIO-8 Inputs:   0x%0*llX",
+                     ccioBoardCount * 2, CcioMgr.InputState());
+            SerialPort.SendLine(msg);
+
+            // The application may be only interested in the transitions of an
+            // input. We can read the rise and fall registers and print them out.
+            snprintf(msg, MAX_MSG_LEN, "CCIO-8 Input Rise:   0x%0*llX",
+                     ccioBoardCount * 2, CcioMgr.InputsRisen());
+            SerialPort.SendLine(msg);
+            snprintf(msg, MAX_MSG_LEN, "CCIO-8 Input Fall:   0x%0*llX",
+                     ccioBoardCount * 2, CcioMgr.InputsFallen());
+            SerialPort.SendLine(msg);
+
+            SerialPort.SendLine("---------------------");
+
+            Delay_ms(1000);
+        }
+        else {
+            // Write digital HIGH then digital LOW to each CCIO-8 connector.
+
+            SerialPort.SendLine("Writing digital HIGH to each CCIO-8 connector...");
+
+            for (uint8_t ccioPinIndex = 0; ccioPinIndex < ccioPinCount; ccioPinIndex++) {
+                CcioMgr.PinByIndex(static_cast<ClearCorePins>(
+                    CLEARCORE_PIN_CCIOA0 + ccioPinIndex))->State(true);
+                Delay_ms(500);
+            }
+
+            SerialPort.SendLine("Writing digital LOW to each CCIO-8 connector...");
+
+            for (int8_t ccioPinIndex = ccioPinCount - 1; ccioPinIndex >= 0; ccioPinIndex--) {
+                CcioMgr.PinByIndex(static_cast<ClearCorePins>(
+                    CLEARCORE_PIN_CCIOA0 + ccioPinIndex))->State(false);
+                Delay_ms(500);
+            }
+        }
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cppproj
new file mode 100644
index 000000000..823c3b38f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cppproj
@@ -0,0 +1,279 @@
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+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ClearCoreIOExpansionBoard.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cpp
new file mode 100644
index 000000000..c1388cfaa
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cpp
@@ -0,0 +1,74 @@
+/*
+ * Title: ReadCCIODigitalInput
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    read from one of its inputs.
+ *
+ * Description:
+ *    This example sets up COM-0 to control a CCIO-8 Expansion Board then reads
+ *    the state of an input on the CCIO-8's connector 0. During operation, the
+ *    state of the input is printed to the USB serial port.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board powered and connected to COM-0.
+ * ** An digital input device such as a switch connected to the CCIO-8's
+ *    connector 0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// Specify which ClearCore serial COM port is connected to the COM IN port
+// of the CCIO-8 board: ConnectorCOM0 or ConnectorCOM1.
+#define CcioPort ConnectorCOM0
+
+// Select the baud rate to match the target serial device.
+#define baudRate 9600
+
+int main() {
+    // Set up serial communication to display CCIO-8 state.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Make sure the input connector is in input mode (the default for all
+    // CCIO-8 pins).
+    CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->Mode(Connector::INPUT_DIGITAL);
+
+    while (true) {
+        // Read the state of the input connector
+        int16_t state = CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->State();
+
+        // Display the state of the input connector.
+        SerialPort.Send("CCIOA0 Input state: ");
+        if (state) {
+            SerialPort.SendLine("ON");
+        }
+        else {
+            SerialPort.SendLine("OFF");
+        }
+
+        // Wait a second then repeat...
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cppproj
new file mode 100644
index 000000000..a25dd307f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
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+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
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+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>ReadCCIODigitalInput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
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+        <documentation help="" />
+        <offline-documentation help="" />
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+        </dependencies>
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+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
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+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
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+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
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+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
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+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
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+    </ListValues>
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+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
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+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../../../libClearCore/inc</Value>
+      <Value>../../../../LwIP/LwIP/src/include</Value>
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+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../../../libClearCore/inc</Value>
+      <Value>../../../../LwIP/LwIP/src/include</Value>
+      <Value>../../../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
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+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
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+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
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+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ReadCCIODigitalInput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cpp
new file mode 100644
index 000000000..fea9640fb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cpp
@@ -0,0 +1,71 @@
+/*
+ * Title: WriteCCIODigitalOutput
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    write to its outputs.
+ *
+ * Description:
+ *    This example sets up COM-0 to control a CCIO-8 Expansion Board then
+ *    toggles the state of all of the CCIO-8's outputs from true to false.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board powered and connected to COM-0.
+ * ** An output such as an LED connected to one or more of the CCIO-8's
+ *    connectors.
+ *      Note: You can leave the I/O points disconnected and still see the
+ *      built-in I/O LEDs toggle with the connector state.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which ClearCore serial COM port is connected to the COM IN port
+// of the CCIO-8 board: ConnectorCOM0 or ConnectorCOM1.
+#define CcioPort ConnectorCOM0
+
+// The state to be written to each output connector.
+bool outputState;
+
+int main() {
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Using the CCIO-8 Board Manager, configure each connector on a single
+    // ClearCore I/O Expansion Board as an output. They can be either digital
+    // inputs or digital outputs.
+    // Note: If there is more than one CCIO-8 in the link, you may want to
+    // to change the limit of the for-loop from "CLEARCORE_PIN_CCIOA7" to the
+    // value of the last CCIO-8 connector to accommodate the additional boards.
+    // For example, if you are using three CCIO-8 boards, change this value to
+    // "CLEARCORE_PIN_CCIOC7", and do the same for the for-loop in the loop()
+    // function below.
+    for (int16_t pin = CLEARCORE_PIN_CCIOA0; pin <= CLEARCORE_PIN_CCIOA7; pin++) {
+        CcioMgr.PinByIndex(static_cast<ClearCorePins>(pin))->Mode(
+            Connector::OUTPUT_DIGITAL);
+    }
+
+    // The connectors are all set up; start the loop with turning them all on.
+    outputState = true;
+
+    while (true) {
+        // Send the current state to each of the outputs.
+        for (int16_t pin = CLEARCORE_PIN_CCIOA0; pin <= CLEARCORE_PIN_CCIOA7; pin++) {
+            CcioMgr.PinByIndex(static_cast<ClearCorePins>(pin))->State(outputState);
+        }
+
+        // Toggle the state to be written next time.
+        outputState = !outputState;
+
+        // Wait 1 second.
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cppproj
new file mode 100644
index 000000000..adbbdb95c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{9e409db5-fb85-4708-ab6f-e22f6b12fcca}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>WriteCCIODigitalOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
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+    <Compile Include="WriteCCIODigitalOutput.cpp">
+      <SubType>compile</SubType>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cpp
new file mode 100644
index 000000000..5bfdb61fd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cpp
@@ -0,0 +1,73 @@
+/*
+ * Title: WriteCCIODigitalOutputPulses
+ *
+ * Objective:
+ *    This example demonstrates how to initialize a CCIO-8 Expansion Board and
+ *    write digital pulses to its outputs.
+ *
+ * Description:
+ *    This example sets up COM-0 to control a CCIO-8 Expansion Board then
+ *    writes a series of digital pulses to the defined connector.
+ *
+ * Requirements:
+ * ** A CCIO-8 Expansion Board powered and connected to COM-0.
+ * ** An output such as an LED connected to defined connector (CCIO-0).
+ *      Note: You can leave the I/O point disconnected and still see the
+ *      built-in I/O LED toggle with the connector state.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which ClearCore serial COM port is connected to the COM IN port
+// of the CCIO-8 board: ConnectorCOM0 or ConnectorCOM1.
+#define CcioPort ConnectorCOM0
+
+// Specify which output pin to write digital output pulses.
+// All connectors on the ClearCore I/O Expansion Board are capable of
+// pulsing the output.
+#define OutputPin CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)
+
+int main() {
+    // Set up the CCIO-8 COM port.
+    CcioPort.Mode(Connector::CCIO);
+    CcioPort.PortOpen();
+
+    // Set up the output connector in output mode.
+    OutputPin->Mode(Connector::OUTPUT_DIGITAL);
+
+    while (true) {
+        // Generate a 100ms on/100ms off pulse that runs until
+        // the stop function is called.
+        OutputPin->OutputPulsesStart(100, 100);
+        Delay_ms(1000);
+
+        // Stop any further pulses on the pin. The second argument controls how
+        // output pulses are stopped. If true, the output pulses will be stopped
+        // immediately (this is the default behavior); if false, the active
+        // pulse cycle will be completed first.
+        OutputPin->OutputPulsesStop(true);
+
+        // Generate a 250ms on/50ms off pulse that continues until
+        // 20 on/off cycles are complete or until the stop function
+        // is called.
+        OutputPin->OutputPulsesStart(250, 50, 20);
+        Delay_ms(6000);
+
+        // Pulses should be complete, but call stop to be safe.
+        OutputPin->OutputPulsesStop(true);
+
+        // Generate a 300ms on/500ms off pulse that runs for 5 complete cycles.
+        // With the final true argument, the sketch will pause here until all
+        // the pulse cycles are complete.
+        OutputPin->OutputPulsesStart(300, 500, 5, true);
+        Delay_ms(3000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cppproj
new file mode 100644
index 000000000..07912b3a0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cppproj
@@ -0,0 +1,279 @@
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+  <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../../../libClearCore/inc</Value>
+      <Value>../../../../LwIP/LwIP/src/include</Value>
+      <Value>../../../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="WriteCCIODigitalOutputPulses.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreBoardStatus.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreBoardStatus.atsln
new file mode 100644
index 000000000..5d01cd2eb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreBoardStatus.atsln
@@ -0,0 +1,34 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCoreStatusRegister", "ClearCoreStatusRegister\ClearCoreStatusRegister.cppproj", "{5E16EF6E-B771-419A-9A3C-6EE5369378A3}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{5E16EF6E-B771-419A-9A3C-6EE5369378A3}.Debug|ARM.ActiveCfg = Debug|ARM
+		{5E16EF6E-B771-419A-9A3C-6EE5369378A3}.Debug|ARM.Build.0 = Debug|ARM
+		{5E16EF6E-B771-419A-9A3C-6EE5369378A3}.Release|ARM.ActiveCfg = Release|ARM
+		{5E16EF6E-B771-419A-9A3C-6EE5369378A3}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cpp
new file mode 100644
index 000000000..9082bd6d6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cpp
@@ -0,0 +1,155 @@
+/*
+ * Title: ClearCoreStatusRegister
+ *
+ * Objective:
+ *    This example demonstrates how to read and display bits in the ClearCore
+ *    Status Register.
+ *
+ * Description:
+ *    This example gets a snapshot of the ClearCore's real-time status register
+ *    and prints the state of the status register bits to the USB serial port.
+ *
+ * Requirements:
+ * ** None
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+int main() {
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        // Get a copy of the real-time status register.
+        StatusManager::StatusRegister statusReg = StatusMgr.StatusRT();
+
+        SerialPort.SendLine("Status Register:");
+
+        SerialPort.Send("Vsupply over-voltage:\t\t");
+        if (statusReg.bit.VSupplyOverVoltage) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("Vsupply under-voltage:\t\t");
+        if (statusReg.bit.VSupplyUnderVoltage) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("H-Bridge output overloaded:\t");
+        if (statusReg.bit.HBridgeOverloaded) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("H-Bridge resetting:\t\t");
+        if (statusReg.bit.HBridgeReset) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        // This status bit denotes the state of the 5 volt supply for off-board
+        // items
+        SerialPort.Send("Offboard 5V overloaded:\t\t");
+        if (statusReg.bit.Overloaded5V) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("Output overloaded:\t\t");
+        if (statusReg.bit.OutputOverloaded) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("CCIO-8 output overloaded:\t");
+        if (statusReg.bit.CcioOverloaded) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("CCIO-8 link broken:\t\t");
+        if (statusReg.bit.CcioLinkBroken) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("ADC in timeout:\t\t\t");
+        if (statusReg.bit.AdcTimeout) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("Ethernet disconnect:\t\t");
+        if (statusReg.bit.EthernetDisconnect) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("Ethernet remote fault:\t\t");
+        if (statusReg.bit.EthernetRemoteFault) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.Send("SD card error:\t\t\t");
+        if (statusReg.bit.SdCardError) {
+            SerialPort.SendLine('1');
+        }
+        else {
+            SerialPort.SendLine('0');
+        }
+
+        SerialPort.SendLine("------------------------");
+
+        // Wait a couple seconds then repeat...
+        Delay_ms(2000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cppproj
new file mode 100644
index 000000000..77e7790f3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{5e16ef6e-b771-419a-9a3c-6ee5369378a3}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>ClearCoreStatusRegister</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../../../libClearCore/inc</Value>
+      <Value>../../../../LwIP/LwIP/src/include</Value>
+      <Value>../../../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../../../libClearCore/inc</Value>
+      <Value>../../../../LwIP/LwIP/src/include</Value>
+      <Value>../../../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>../../Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ClearCoreStatusRegister.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearCoreBoardStatus/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cpp
new file mode 100644
index 000000000..a01076753
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cpp
@@ -0,0 +1,262 @@
+/*
+ * Title: 16PositionsHomeToHardStop
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move To Absolute Position, 16 Positions (Home to Hard Stop).
+ *
+ * Description:
+ *    This example enables, homes, and then moves a ClearPath motor between
+ *    preprogrammed absolute positions as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move To Absolute Position, 16 Positions (Home to Hard Stop) mode (In
+ *    MSP select Mode>>Position>>Move to Absolute Position, then with "16
+ *    Positions (Home to Hard Stop)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Absolute Position Selections through
+ *    the MSP software (On the main MSP window fill in the textboxes labeled
+ *    1-16 found under "Position Selection Setup (cnts)").
+ * 5. Homing must be configured in the MSP software for your mechanical
+ *    system (e.g. homing direction, torque limit, etc.). To configure, click
+ *    the "Setup..." button found under the "Homing" label on the MSP's main
+ *    window.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode14
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveToPosition(uint8_t positionNum);
+void HandleMotorFaults();
+
+int main() {
+    // Sets all motor connectors to the correct mode for Absolute Position mode
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    // the motor.
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move to Position 1 defined in MSP.
+        MoveToPosition(1);    // See below for the detailed function definition.
+        // Wait 1000ms.
+        Delay_ms(1000);
+        MoveToPosition(2);
+        Delay_ms(1000);
+        MoveToPosition(3);
+        Delay_ms(1000);
+        MoveToPosition(4);
+        Delay_ms(1000);
+
+        MoveToPosition(5);
+        Delay_ms(1000);
+        MoveToPosition(6);
+        Delay_ms(1000);
+        MoveToPosition(7);
+        Delay_ms(1000);
+        MoveToPosition(8);
+        Delay_ms(1000);
+
+        MoveToPosition(9);
+        Delay_ms(1000);
+        MoveToPosition(10);
+        Delay_ms(1000);
+        MoveToPosition(11);
+        Delay_ms(1000);
+        MoveToPosition(12);
+        Delay_ms(1000);
+
+        MoveToPosition(13);
+        Delay_ms(1000);
+        MoveToPosition(14);
+        Delay_ms(1000);
+        MoveToPosition(15);
+        Delay_ms(1000);
+        MoveToPosition(16);
+        Delay_ms(1000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveToPosition
+ *
+ *    Move to position number positionNum (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int positionNum  - The position number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether the position was successfully
+ *    commanded.
+ */
+bool MoveToPosition(uint8_t positionNum) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Moving to position: ");
+    SerialPort.SendLine(positionNum);
+
+    if (positionNum < 17 && positionNum > 0) {
+        // Sends pulses on Input B based on positionNum
+        for (uint8_t i = 0; i < positionNum; i++) {
+            motor.MotorInBState(true);
+            Delay_ms(1);
+            motor.MotorInBState(false);
+            Delay_ms(1);
+        }
+
+        // Triggers the command
+        motor.MotorInAState(true);
+        Delay_ms(1);
+        motor.MotorInAState(false);
+    }
+    else {
+        // If an invalid positionNum has been entered, returns a failure
+        return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    Delay_ms(2 );
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cppproj
new file mode 100644
index 000000000..8cac5385e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cppproj
@@ -0,0 +1,284 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>Abs16PositionsHomeToHardStop</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
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+        </armgcccpp.preprocessingassembler.general.IncludePaths>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="Abs16PositionsHomeToHardStop.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
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+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
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+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
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+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cpp
new file mode 100644
index 000000000..9f1c18a01
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cpp
@@ -0,0 +1,257 @@
+/*
+ * Title: 2PositionsHomeToSwitch
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Move To Absolute Position, 2 Positions (Home to Switch).
+ *
+ * Description:
+ *    This example enables, homes, and then moves a ClearPath motor between
+ *    preprogrammed absolute positions as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move To Absolute Position, 2 Positions (Home to Switch) mode (In MSP
+ *    select Mode>>Position>>Move to Absolute Position, then with "2 Positions
+ *    (Home to Switch)" selected hit the OK button).
+ * 3. Homing must be configured in the MSP software for your mechanical system
+ *    (e.g. homing direction, switch polarity, etc.). To configure, click the
+ *    "Setup..." button found under the "Homing" label on the MSP's main window.
+ * 4. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 5. Wire the homing sensor to Connector DI-6.
+ * 6. The ClearPath must have defined Absolute Position Selections set up in the
+ *    MSP software (On the main MSP window check the "Position Selection Setup
+ *    (cnts)" box and fill in the two text boxes labeled "A off" and "A on").
+ * 7. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode2
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Specifies the home sensor connector
+#define HomingSensor ConnectorDI6
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+void HomingSensorCallback();
+bool MoveToPosition(uint8_t positionNum);
+void HandleMotorFaults();
+
+int main() {
+    // This section attaches the interrupt callback to the homing sensor pin,
+    // set to trigger on any change of sensor state.
+    HomingSensor.Mode(Connector::INPUT_DIGITAL);
+    HomingSensor.InterruptHandlerSet(HomingSensorCallback, InputManager::CHANGE);
+
+    // Sets all motor connectors to the correct mode for Absolute Position mode
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's Input A before enabling the motor
+    motor.MotorInAState(false);
+    // Set input B to match the initial state of the sensor.
+    motor.MotorInBState(HomingSensor.State());
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move to Position 1 defined in MSP.
+        MoveToPosition(1);    // See below for the detailed function definition.
+        // Wait 1000ms.
+        Delay_ms(1000);
+        MoveToPosition(2);
+        Delay_ms(1000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveToPosition
+ *
+ *    Move to position number positionNum (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int positionNum  - The position number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether a valid position was
+ *    successfully commanded and reached.
+ */
+bool MoveToPosition(uint8_t positionNum) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Moving to position: ");
+    SerialPort.Send(positionNum);
+
+    switch (positionNum) {
+        case 1:
+            // Sets Input A "off" for position 1
+            motor.MotorInAState(false);
+            SerialPort.SendLine(" (Input A Off)");
+            break;
+        case 2:
+            // Sets Input A "on" for position 2
+            motor.MotorInAState(true);
+            SerialPort.SendLine(" (Input A On)");
+            break;
+        default:
+            // If this case is reached then an incorrect positionNum was entered
+            return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    Delay_ms(2 + INPUT_A_B_FILTER);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * HomingSensorCallback
+ *
+ *    Reads the state of the homing sensor and passes the state to the motor.
+ */
+void HomingSensorCallback() {
+    // A 1 ms delay is required in order to pass the correct filtered sensor
+    // state.
+    Delay_ms(1);
+    motor.MotorInBState(HomingSensor.State());
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cppproj
new file mode 100644
index 000000000..9e43ffd84
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cppproj
@@ -0,0 +1,279 @@
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+    <AssemblyName>Examples</AssemblyName>
+    <Name>Abs2PositionsHomeToSwitch</Name>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="Abs2PositionsHomeToSwitch.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cpp
new file mode 100644
index 000000000..8b1324c71
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cpp
@@ -0,0 +1,266 @@
+/*
+ * Title: 4PositionsHomeToHardStop
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move To Absolute Position, 4 Positions (Home to Hard Stop).
+ *
+ * Description:
+ *    This example enables, homes, and then moves a ClearPath motor between
+ *    preprogrammed absolute positions as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move To Absolute Position, 4 Positions (Home to Hard Stop) mode (In
+ *    MSP select Mode>>Position>>Move to Absolute Position, then with "4
+ *    Positions (Home to Hard Stop)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Absolute Position Selections through
+ *    the MSP software (On the main MSP window check the "Position Selection
+ *    Setup (cnts)" box and fill in the four text boxes labeled "A off B off",
+ *    "A on B off", "A off B on" and "A on B on").
+ * 5. Homing must be configured in the MSP software for your mechanical
+ *    system (e.g. homing direction, torque limit, etc.). To configure, click
+ *    the "Setup..." button found under the "Homing" label on the MSP's main
+ *    window.
+ * 6. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode3
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveToPosition(uint8_t positionNum);
+void HandleMotorFaults();
+
+int main() {
+    // Sets all motor connectors to the correct mode for Absolute Position mode
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    // the motor.
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move to Position 1 defined in MSP.
+        MoveToPosition(1);    // See below for the detailed function definition.
+        // Wait 1000ms.
+        Delay_ms(1000);
+        MoveToPosition(2);
+        Delay_ms(1000);
+        MoveToPosition(3);
+        Delay_ms(1000);
+        MoveToPosition(4);
+        Delay_ms(1000);
+
+        // Alternatively, if you'd like to control the ClearPath servo's inputs
+        // externally using ClearCore inputs, consider doing something like this:
+        /*
+        // Sets ClearPath's InA to DI6's state
+         motor.MotorInAState(ConnectorDI6.State());
+         // Sets ClearPath's InB to DI7's state
+         motor.MotorInBState(ConnectorDI7.State());
+        */
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveToPosition
+ *
+ *    Move to position number positionNum (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int positionNum  - The position number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether the position was successfully
+ *    commanded.
+ */
+bool MoveToPosition(uint8_t positionNum) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+	
+	SerialPort.Send("Moving to position: ");
+    SerialPort.Send(positionNum);
+
+    switch (positionNum) {
+        case 1:
+            // Sets Input A and B for position 1
+            motor.MotorInAState(false);
+            motor.MotorInBState(false);
+            SerialPort.SendLine(" (Inputs A Off/B Off)");
+            break;
+        case 2:
+            // Sets Input A and B for position 2
+            motor.MotorInAState(true);
+            motor.MotorInBState(false);
+            SerialPort.SendLine(" (Inputs A On/B Off)");
+            break;
+        case 3:
+            // Sets Input A and B for position 3
+            motor.MotorInAState(false);
+            motor.MotorInBState(true);
+            SerialPort.SendLine(" (Inputs A Off/B On)");
+            break;
+        case 4:
+            // Sets Input A and B for position 4
+            motor.MotorInAState(true);
+            motor.MotorInBState(true);
+            SerialPort.SendLine(" (Inputs A On/B On)");
+            break;
+        default:
+            // If this case is reached then an incorrect positionNum was entered
+            return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    Delay_ms(2 + INPUT_A_B_FILTER);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------
+ 
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cppproj
new file mode 100644
index 000000000..312d2fc34
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{fd4139d0-ed7f-4626-a513-2542a8a921cf}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>Abs4PositionsHomeToHardStop</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../../libClearCore/inc</Value>
+            <Value>../../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="Abs4PositionsHomeToHardStop.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ClearPath-MC_Series_Examples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ClearPath-MC_Series_Examples.atsln
new file mode 100644
index 000000000..fb92a3cd5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ClearPath-MC_Series_Examples.atsln
@@ -0,0 +1,151 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "FollowDigitalPosition", "FollowDigitalPosition\FollowDigitalPosition.cppproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "Abs16PositionsHomeToHardStop", "Abs16PositionsHomeToHardStop\Abs16PositionsHomeToHardStop.cppproj", "{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "Abs2PositionsHomeToSwitch", "Abs2PositionsHomeToSwitch\Abs2PositionsHomeToSwitch.cppproj", "{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "Abs4PositionsHomeToHardStop", "Abs4PositionsHomeToHardStop\Abs4PositionsHomeToHardStop.cppproj", "{FD4139D0-ED7F-4626-A513-2542A8A921CF}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "FollowDigitalTorque", "FollowDigitalTorque\FollowDigitalTorque.cppproj", "{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "FollowDigitalVelocity", "FollowDigitalVelocity\FollowDigitalVelocity.cppproj", "{EDFC51AB-F02A-4C04-9176-B33E06040E95}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "FollowDigitalVelocityWithVariableTorque", "FollowDigitalVelocityWithVariableTorque\FollowDigitalVelocityWithVariableTorque.cppproj", "{3C7B1CEB-17C5-4007-8729-EFEF36976508}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ManualVelocity", "ManualVelocity\ManualVelocity.cppproj", "{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "Move2IncrementsHomeToSwitch", "Move2IncrementsHomeToSwitch\Move2IncrementsHomeToSwitch.cppproj", "{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "Move4IncrementsHomeToHardStop", "Move4IncrementsHomeToHardStop\Move4IncrementsHomeToHardStop.cppproj", "{94B53311-1B36-4569-B2AE-CD4E004C22B3}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "PulseBurstPositioning", "PulseBurstPositioning\PulseBurstPositioning.cppproj", "{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "RampUpDownToSelectedVelocity", "RampUpDownToSelectedVelocity\RampUpDownToSelectedVelocity.cppproj", "{12385F85-B107-40D7-A55B-2FB5094C4402}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+		Test|ARM = Test|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Test|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Test|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Test|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Test|ARM.Build.0 = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Test|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Test|ARM.Build.0 = Debug|ARM
+		{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}.Debug|ARM.ActiveCfg = Debug|ARM
+		{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}.Debug|ARM.Build.0 = Debug|ARM
+		{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}.Release|ARM.ActiveCfg = Release|ARM
+		{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}.Release|ARM.Build.0 = Release|ARM
+		{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}.Test|ARM.ActiveCfg = Debug|ARM
+		{F62A036D-0AD1-423F-B667-5AE0DB9C3AD7}.Test|ARM.Build.0 = Debug|ARM
+		{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}.Debug|ARM.ActiveCfg = Debug|ARM
+		{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}.Debug|ARM.Build.0 = Debug|ARM
+		{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}.Release|ARM.ActiveCfg = Release|ARM
+		{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}.Release|ARM.Build.0 = Release|ARM
+		{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}.Test|ARM.ActiveCfg = Debug|ARM
+		{3865646A-D96B-4E7A-BF7E-A26EB85A9B99}.Test|ARM.Build.0 = Debug|ARM
+		{FD4139D0-ED7F-4626-A513-2542A8A921CF}.Debug|ARM.ActiveCfg = Debug|ARM
+		{FD4139D0-ED7F-4626-A513-2542A8A921CF}.Debug|ARM.Build.0 = Debug|ARM
+		{FD4139D0-ED7F-4626-A513-2542A8A921CF}.Release|ARM.ActiveCfg = Release|ARM
+		{FD4139D0-ED7F-4626-A513-2542A8A921CF}.Release|ARM.Build.0 = Release|ARM
+		{FD4139D0-ED7F-4626-A513-2542A8A921CF}.Test|ARM.ActiveCfg = Debug|ARM
+		{FD4139D0-ED7F-4626-A513-2542A8A921CF}.Test|ARM.Build.0 = Debug|ARM
+		{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}.Debug|ARM.ActiveCfg = Debug|ARM
+		{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}.Debug|ARM.Build.0 = Debug|ARM
+		{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}.Release|ARM.ActiveCfg = Release|ARM
+		{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}.Release|ARM.Build.0 = Release|ARM
+		{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}.Test|ARM.ActiveCfg = Debug|ARM
+		{401A58BB-74A3-425A-90FE-C4E35AFCCA7F}.Test|ARM.Build.0 = Debug|ARM
+		{EDFC51AB-F02A-4C04-9176-B33E06040E95}.Debug|ARM.ActiveCfg = Debug|ARM
+		{EDFC51AB-F02A-4C04-9176-B33E06040E95}.Debug|ARM.Build.0 = Debug|ARM
+		{EDFC51AB-F02A-4C04-9176-B33E06040E95}.Release|ARM.ActiveCfg = Release|ARM
+		{EDFC51AB-F02A-4C04-9176-B33E06040E95}.Release|ARM.Build.0 = Release|ARM
+		{EDFC51AB-F02A-4C04-9176-B33E06040E95}.Test|ARM.ActiveCfg = Debug|ARM
+		{EDFC51AB-F02A-4C04-9176-B33E06040E95}.Test|ARM.Build.0 = Debug|ARM
+		{3C7B1CEB-17C5-4007-8729-EFEF36976508}.Debug|ARM.ActiveCfg = Debug|ARM
+		{3C7B1CEB-17C5-4007-8729-EFEF36976508}.Debug|ARM.Build.0 = Debug|ARM
+		{3C7B1CEB-17C5-4007-8729-EFEF36976508}.Release|ARM.ActiveCfg = Release|ARM
+		{3C7B1CEB-17C5-4007-8729-EFEF36976508}.Release|ARM.Build.0 = Release|ARM
+		{3C7B1CEB-17C5-4007-8729-EFEF36976508}.Test|ARM.ActiveCfg = Debug|ARM
+		{3C7B1CEB-17C5-4007-8729-EFEF36976508}.Test|ARM.Build.0 = Debug|ARM
+		{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}.Debug|ARM.ActiveCfg = Debug|ARM
+		{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}.Debug|ARM.Build.0 = Debug|ARM
+		{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}.Release|ARM.ActiveCfg = Release|ARM
+		{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}.Release|ARM.Build.0 = Release|ARM
+		{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}.Test|ARM.ActiveCfg = Debug|ARM
+		{8E27B935-12EA-4FA1-8A5F-53EB06696B1A}.Test|ARM.Build.0 = Debug|ARM
+		{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}.Debug|ARM.Build.0 = Debug|ARM
+		{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}.Release|ARM.ActiveCfg = Release|ARM
+		{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}.Release|ARM.Build.0 = Release|ARM
+		{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}.Test|ARM.ActiveCfg = Debug|ARM
+		{C5F6BD12-D7B5-4F94-8698-BF36F981F9AD}.Test|ARM.Build.0 = Debug|ARM
+		{94B53311-1B36-4569-B2AE-CD4E004C22B3}.Debug|ARM.ActiveCfg = Debug|ARM
+		{94B53311-1B36-4569-B2AE-CD4E004C22B3}.Debug|ARM.Build.0 = Debug|ARM
+		{94B53311-1B36-4569-B2AE-CD4E004C22B3}.Release|ARM.ActiveCfg = Release|ARM
+		{94B53311-1B36-4569-B2AE-CD4E004C22B3}.Release|ARM.Build.0 = Release|ARM
+		{94B53311-1B36-4569-B2AE-CD4E004C22B3}.Test|ARM.ActiveCfg = Debug|ARM
+		{94B53311-1B36-4569-B2AE-CD4E004C22B3}.Test|ARM.Build.0 = Debug|ARM
+		{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}.Debug|ARM.ActiveCfg = Debug|ARM
+		{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}.Debug|ARM.Build.0 = Debug|ARM
+		{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}.Release|ARM.ActiveCfg = Release|ARM
+		{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}.Release|ARM.Build.0 = Release|ARM
+		{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}.Test|ARM.ActiveCfg = Debug|ARM
+		{BCA000A4-3662-464A-ACBE-B3CB690CDEDD}.Test|ARM.Build.0 = Debug|ARM
+		{12385F85-B107-40D7-A55B-2FB5094C4402}.Debug|ARM.ActiveCfg = Debug|ARM
+		{12385F85-B107-40D7-A55B-2FB5094C4402}.Debug|ARM.Build.0 = Debug|ARM
+		{12385F85-B107-40D7-A55B-2FB5094C4402}.Release|ARM.ActiveCfg = Release|ARM
+		{12385F85-B107-40D7-A55B-2FB5094C4402}.Release|ARM.Build.0 = Release|ARM
+		{12385F85-B107-40D7-A55B-2FB5094C4402}.Test|ARM.ActiveCfg = Debug|ARM
+		{12385F85-B107-40D7-A55B-2FB5094C4402}.Test|ARM.Build.0 = Debug|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cpp
new file mode 100644
index 000000000..8235f90ae
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cpp
@@ -0,0 +1,246 @@
+/*
+ * Title: FollowDigitalPosition
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Follow Digital Position Command, Unipolar PWM Command.
+ *
+ * Description:
+ *    This example enables and then moves a ClearPath motor between various
+ *    positions within a range defined in the MSP software based on the state
+ *    of an analog input. During operation, various move statuses are written
+ *    to the USB serial port.
+ *    To achieve better positioning resolution (i.e. more commandable positions),  
+ *    consider using the ClearPath operational modes "Pulse Burst Positioning"
+ *    or "Move Incremental Distance" instead.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Position Command, Unipolar PWM Command mode (In MSP
+ *    select Mode>>Position>>Follow Digital Position Command, then with
+ *    "Unipolar PWM Command" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined positions for 0% and 100% PWM (On the
+ *    main MSP window check the "Position Range Setup (cnts)" box and fill in
+ *    the two text boxes labeled "Posn at 0% PWM" and "Posn at 100% PWM").
+ *    Change the "PositionZeroPWM" and "PositionMaxPWM" variables in the example
+ *    below to match.
+ * 5. Homing must be configured in the MSP software for your mechanical
+ *    system (e.g. homing direction, torque limit, etc.). This example does
+ *    not use the ClearPath's Input A as a homing sensor, although that may
+ *    be configured in this mode through MSP.
+ * 6. An analog input source (0-10V) connected to Connector A-9 to control motor 
+ *    position.
+ * 7. (Optional) An input source, such as a switch, connected to DI-6 to control
+ *    the Command Lock or Home Sensor (configured in MSP).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode12
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector
+#define motor ConnectorM0
+
+// Defines the command lock sensor connector
+#define LockSensor ConnectorDI6
+
+// Defines the analog input to control commanded position
+#define AnalogSensor ConnectorA9
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+double positionZeroPWM = 0;
+double positionMaxPWM = 10000;
+void HandleMotorFaults();
+
+// Declares our user-defined functions, which are used to pass the Command Lock
+// sensor state and send position commands to the motor. The implementations of
+// these functions are at the bottom of the sketch.
+void LockSensorCallback();
+bool CommandPosition(int32_t commandedPosition);
+
+int main() {
+    // Set up an analog sensor to control commanded position.
+    AnalogSensor.Mode(Connector::INPUT_ANALOG);
+
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Position mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_PWM);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // This section attaches the interrupt callback to the locking sensor pin,
+    // set to trigger on any change of sensor state.
+    LockSensor.Mode(Connector::INPUT_DIGITAL);
+    LockSensor.InterruptHandlerSet(LockSensorCallback, InputManager::CHANGE, true);
+    // Set input A to match the initial state of the sensor.
+    motor.MotorInAState(LockSensor.State());
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if applicable
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Read the voltage on the analog sensor (0-10V).
+        float analogVoltage = AnalogSensor.AnalogVoltage();
+        // Convert the voltage measured to a position within the valid range.
+        int32_t commandedPosition =
+            static_cast<int32_t>(round(analogVoltage / 10 * positionMaxPWM));
+        CommandPosition(commandedPosition);    // See below for the detailed function definition.
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * CommandPosition
+ *
+ *    Move to position number commandedPosition (counts in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns whether the command has been updated.
+ *
+ * Parameters:
+ *    int commandedPosition  - The position, in counts, to command
+ *
+ */
+bool CommandPosition(int32_t commandedPosition) {
+    if (abs(commandedPosition) > abs(positionMaxPWM) ||
+        abs(commandedPosition) < abs(positionZeroPWM)) {
+        SerialPort.SendLine("Move rejected, invalid position requested");
+        return false;
+    }
+
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Moving to position: ");
+    SerialPort.SendLine(commandedPosition);
+
+    // Find the scaling factor of our position range mapped to the PWM duty
+    // cycle range (255 is the max duty cycle).
+    double scaleFactor = 255 / abs(positionMaxPWM - positionZeroPWM);
+
+    // Scale the position command to our duty cycle range.
+    uint8_t dutyRequest = abs(commandedPosition - positionZeroPWM) * scaleFactor;
+
+    // Command the move.
+    motor.MotorInBDuty(dutyRequest);
+
+    return true;
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * LockSensorCallback
+ *
+ *    Reads the state of the locking sensor and passes the state to the motor.
+ *
+ * Parameters:
+ *    None
+ *
+ * Returns: None
+ */
+void LockSensorCallback() {
+    // A 1 ms delay is required in order to pass the correct filtered sensor
+    // state.
+    Delay_ms(1);
+    motor.MotorInAState(LockSensor.State());
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cppproj
new file mode 100644
index 000000000..bc9aedf78
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cppproj
@@ -0,0 +1,274 @@
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+    </Compile>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cpp
new file mode 100644
index 000000000..9358b9dea
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cpp
@@ -0,0 +1,182 @@
+/*
+ * Title: FollowDigitalTorque
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Follow Digital Torque Command, Unipolar PWM Command.
+ *
+ * Description:
+ *    This example enables and then commands a ClearPath motor to output various
+ *    torques. in both the clockwise and counterclockwise directions.
+ *    During operation, various move statuses are written to the USB serial
+ *    port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Torque Command, Unipolar PWM Command mode  (In MSP
+ *    select Mode>>Torque>>Follow Digital Torque Command, then with
+ *    "Unipolar PWM Command" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Torque"
+ *    through the MSP software (select Advanced>>High Level Feedback [Mode]...
+ *    then choose "All Systems Go (ASG) - Torque" from the dropdown and hit
+ *    the OK button).
+ * 4. The ClearPath must have a defined Max Torque Command configured through
+ *    the MSP software. This value must match the "maxTorque" variable defined
+ *    below.
+ * 5. Ensure the Input A filter in MSP is set to 20ms (In MSP select
+ *    Advanced>>Input A, B Filtering... then in the Settings box fill in the
+ *    textbox labeled "Input A Filter Time Constant (msec)" then hit the OK
+ *    button).
+ * 6. Set your Max Speed and Over-Speed Timeout in MSP according to your
+ *    mechanical system. Note you may notice any of the following if this max
+ *    speed is reached: motor shutdown, speed limit cycling at the max speed,
+ *    HLFB not signaling ASG/move done.
+ * 7. Ensure the "Invert PWM Input" box is unchecked in MSP.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode9
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_FILTER must match the Input A filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// Defines the limit of the torque command, as a percent of the motor's peak
+// torque rating (must match the value used in MSP)
+double maxTorque = 100;
+
+// Declares our user-defined helper function, which is used to command torque.
+// The definition/implementation of this function is at the bottom of the sketch.
+bool CommandTorque(int8_t commandedTorque);
+
+int main() {
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Torque mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_PWM);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+    SerialPort.SendLine("Motor Ready");
+
+    while (true) {
+        // Output 15% of the motor's peak torque in the positive (CCW) direction.
+        CommandTorque(15);    // See below for the detailed function definition.
+        // Wait 2000ms.
+        Delay_ms(2000);
+
+        CommandTorque(-75); // Output 75% peak torque in the negative (CW) direction.
+        Delay_ms(2000);
+
+        CommandTorque(5); // Output 5% peak torque in the positive (CCW) direction.
+        Delay_ms(2000);
+
+        CommandTorque(-35); // Output 35% peak torque in the negative (CW) direction.
+        Delay_ms(2000);
+
+        CommandTorque(10); // Output 10% peak torque in the positive (CCW) direction.
+        Delay_ms(2000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * CommandTorque
+ *
+ *    Command the motor to move using a torque of commandedTorque
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    torque)
+ *
+ * Parameters:
+ *    int commandedTorque  - The torque to command
+ *
+ * Returns: True/False depending on whether the torque was successfully
+ *    commanded.
+ */
+bool CommandTorque(int8_t commandedTorque) {
+    if (abs(commandedTorque) > abs(maxTorque)) {
+        SerialPort.SendLine("Move rejected, invalid torque requested");
+        return false;
+    }
+
+    // Check if an alert is currently preventing motion
+    if (motor.StatusReg().bit.AlertsPresent) {
+        SerialPort.SendLine("Motor status: 'In Alert'. Move Canceled.");
+        return false;
+    }
+
+    SerialPort.Send("Commanding torque: ");
+    SerialPort.SendLine(commandedTorque);
+
+    // Find the scaling factor of our torque range mapped to the PWM duty cycle
+    // range (255 is the max duty cycle).
+    double scaleFactor = 255 / maxTorque;
+
+    // Scale the torque command to our duty cycle range.
+    uint8_t dutyRequest = abs(commandedTorque) * scaleFactor;
+
+    // Set input A to match the direction of torque.
+    if (commandedTorque < 0) {
+        motor.MotorInAState(true);
+    }
+    else {
+        motor.MotorInAState(false);
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A filter
+    // setting in MSP
+    Delay_ms(2 + INPUT_A_FILTER);
+
+    // Command the move
+    motor.MotorInBDuty(dutyRequest);
+
+    // Waits for HLFB to assert (signaling a successful new torque output)
+    SerialPort.SendLine("Moving... Waiting for HLFB");
+    // Allow some time for HLFB to transition.
+    Delay_ms(1);
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+
+    SerialPort.SendLine("Move Done");
+    return true;
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cppproj
new file mode 100644
index 000000000..acd3310d9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cppproj
@@ -0,0 +1,279 @@
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+    <Compile Include="..\Device_Startup\startup_same53.c">
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+    <Compile Include="FollowDigitalTorque.cpp">
+      <SubType>compile</SubType>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cpp
new file mode 100644
index 000000000..8cc4920b0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cpp
@@ -0,0 +1,166 @@
+/* 
+ * Title: FollowDigitalVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Follow Digital Velocity Command, Unipolar PWM Command.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes velocity moves based
+ *    on the state of an analog input sensor. During operation, various move
+ *    statuses are written to the USB serial port.
+ *    Consider using Manual Velocity Control mode instead if you do not wish to 
+ *    use an analog sensor to command velocity, if you require greater velocity 
+ *    command resolution (i.e. more commandable positions), or if HLFB is needed 
+ *    for "move done/at speed" status feedback.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Velocity Command, Unipolar PWM Command mode (In MSP
+ *    select Mode>>Velocity>>Follow Digital Velocity Command, then with
+ *    "Unipolar PWM Command" selected hit the OK button).
+ * 3. The ClearPath must have a defined Max Speed configured through the MSP
+ *    software (On the main MSP window fill in the "Max Speed (RPM)" box with
+ *    your desired maximum speed). Ensure the value of maxSpeed below matches
+ *    this Max Speed.
+ * 4. Ensure the "Invert PWM Input" checkbox found on the MSP's main window is
+ *    unchecked.
+ * 5. Ensure the Input A filter in MSP is set to 20ms, (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textbox labeled "Input A Filter Time Constant (msec)" then hit the OK
+ *    button).
+ * 6. An analog input source (0-10V) connected to ConnectorA9 to control
+ *    motor velocity.
+ *
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode8
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Defines the analog input to control commanded velocity
+#define AnalogSensor ConnectorA9
+
+// The INPUT_A_FILTER must match the Input A filter setting in MSP
+// (Advanced >> Input A, B Filtering...)
+#define INPUT_A_FILTER 20
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This is the commanded speed limit in RPM (must match the MSP value). This speed
+// cannot actually be commanded, so use something slightly higher than your real
+// max speed here and in MSP
+double maxSpeed = 510;
+
+// Declares our user-defined helper function, which is used to command speed and
+// direction. The definition/implementation of this function is at the bottom of
+// the sketch.
+bool CommandVelocity(int32_t commandedVelocity);
+
+int main() {
+    // Set up an analog sensor to control commanded velocity.
+    AnalogSensor.Mode(Connector::INPUT_ANALOG);
+
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Velocity, Unipolar PWM mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_PWM);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    while (true) {
+        // Read the voltage on the analog sensor (0-10V).
+        float analogVoltage = AnalogSensor.AnalogVoltage();
+        // Convert the voltage measured to a velocity within the valid range.
+        int32_t commandedVelocity =
+            static_cast<int32_t>(round(analogVoltage / 10 * maxSpeed));
+
+        // Move at the commanded velocity.
+        CommandVelocity(commandedVelocity);    // See below for the detailed function definition.
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * CommandVelocity
+ *
+ *    Command the motor to move using a velocity of commandedVelocity
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int commandedVelocity  - The velocity to command
+ *
+ * Returns: True/False depending on whether the velocity was successfully
+ *    commanded.
+ */
+bool CommandVelocity(int32_t commandedVelocity) {
+    if (abs(commandedVelocity) >= abs(maxSpeed)) {
+        SerialPort.SendLine("Move rejected, requested velocity at or over the limit.");
+        return false;
+    }
+
+    // Check if an alert is currently preventing motion
+    if (motor.StatusReg().bit.AlertsPresent) {
+        SerialPort.SendLine("Motor status: 'In Alert'. Move Canceled.");
+        return false;
+    }
+
+    SerialPort.Send("Commanding velocity: ");
+    SerialPort.SendLine(commandedVelocity);
+
+    // Change ClearPath's Input A state to change direction.
+    // Note: this section of code was included so this commandVelocity function 
+    // could be used to command negative (opposite direction) velocity. However the 
+    // analog signal used by this example only commands positive velocities.
+    if (commandedVelocity >= 0) {
+        motor.MotorInAState(false);
+    }
+    else {
+        motor.MotorInAState(true);
+    }
+
+    // Delays to send the correct filtered direction.
+    Delay_ms(2 + INPUT_A_FILTER);
+
+    // Find the scaling factor of our velocity range mapped to the PWM duty
+    // cycle range (255 is the max duty cycle).
+    double scaleFactor = 255 / maxSpeed;
+
+    // Scale the velocity command to our duty cycle range.
+    uint8_t dutyRequest = abs(commandedVelocity) * scaleFactor;
+
+    // Command the move.
+    motor.MotorInBDuty(dutyRequest);
+
+    return true;
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cppproj
new file mode 100644
index 000000000..195767c20
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cppproj
@@ -0,0 +1,282 @@
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+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="FollowDigitalVelocity.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
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+  <ItemGroup>
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+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
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+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cpp
new file mode 100644
index 000000000..86326021f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cpp
@@ -0,0 +1,219 @@
+/*
+ * Title: FollowDigitalVelocityWithVariableTorque
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Follow Digital Velocity Command, Bipolar PWM Command with Variable Torque.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    bidirectional velocity moves and torque limits. During operation, various
+ *    move statuses are written to the USB serial port.
+ *    The resolution for PWM outputs is 8-bit, meaning only 256 discrete speeds
+ *    and torque limits can be commanded. The motor's actual commanded speed
+ *    and torque limit may differ slightly from what you input below because
+ *    of this.
+ *    Consider using Manual Velocity Control mode if greater velocity command
+ *    resolution is required, or if HLFB is needed for "move done/at speed"
+ *    status feedback.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Follow Digital Velocity Command, Bipolar PWM Command with Variable
+ *    Torque mode (In MSP select Mode>>Velocity>>Follow Digital Velocity
+ *    Command, then with "Bipolar PWM Command w/ Variable Torque")
+ * 3. The ClearPath must have a defined Max Speed configured through the MSP
+ *    software (On the main MSP window fill in the "Max Speed (RPM)" box with
+ *    your desired maximum speed). Ensure the value of maxSpeed below matches
+ *    this Max Speed.
+ * 4. Set the PWM Deadband in MSP to 2.
+ * 5. In MSP, ensure the two checkboxes for "Invert Torque PWM Input" and
+ *    "Invert Speed PWM Input" are unchecked.
+ * 6. A primary Torque Limit and Alternate Torque Limit must be defined using
+ *    the Torque Limit setup window through the MSP software (To configure,
+ *    click the "Setup..." button found under the "Torque Limit" label. Then
+ *    fill in the textbox labeled "Alt Torque Limit (% of max)" and hit the
+ *    Apply button). Use only symmetric limits. These limits must match the
+ *    "torqueLimit" and "torqueLimitAlternate" variables defined below.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This is the commanded speed limit (must match the MSP value). This speed
+// cannot actually be commanded, so use something slightly higher than your real
+// max speed here and in MSP.
+double maxVelocity = 2000;
+
+// Defines the default torque limit and the alternate torque limit
+// (must match MSP values)
+double torqueLimit = 100.0;
+double torqueLimitAlternate = 10.0;
+
+// A PWM deadband of 2% prevents signal jitter from effecting a 0 RPM command
+// (must match MSP value)
+double pwmDeadBand = 2.0;
+
+// Declares our user-defined helper functions, which are used to command
+// velocity and limit torque. The definitions/implementations of these functions
+// are at the bottom of the sketch.
+bool CommandVelocity(int32_t commandedVelocity);
+bool LimitTorque(double limit);
+
+int main() {
+    // Sets all motor connectors to the correct mode for Follow Digital
+    // Velocity, Bipolar PWM mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_PWM_B_PWM);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for 5 seconds to allow the motor to come up to speed
+    SerialPort.SendLine("Waiting for motor to reach speed...");
+    startTime = Milliseconds();
+    while (Milliseconds() - startTime < timeout) {
+        continue;
+    }
+    SerialPort.SendLine("Motor Ready");
+
+    while (true) {
+        // Move at +100 RPM (CCW).
+        CommandVelocity(100);    // See below for the detailed function definition.
+        // Wait 5000ms
+        Delay_ms(5000);
+
+        CommandVelocity(300);    // Move at +300 RPM (CCW).
+        Delay_ms(5000);
+
+        // Limit the torque to 70%.
+        LimitTorque(70);         // See below for the detailed function definition.
+        CommandVelocity(-200);   // Move at -200 RPM (CW).
+        Delay_ms(5000);
+
+        LimitTorque(15);         // Limit the torque to 15%.
+        CommandVelocity(-300);   // Move at -300 RPM (CW).
+        Delay_ms(5000);
+
+        LimitTorque(100);        // Increase torque limit to 100%.
+        CommandVelocity(100);    // Move at +100 RPM (CCW).
+        Delay_ms(5000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * CommandVelocity
+ *
+ *    Command the motor to move using a velocity of commandedVelocity
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int commandedVelocity  - The velocity to command
+ *
+ * Returns: True/False depending on whether the velocity was successfully
+ *    commanded.
+ */
+bool CommandVelocity(int32_t commandedVelocity) {
+    if (abs(commandedVelocity) > maxVelocity) {
+        SerialPort.SendLine("Move rejected, invalid velocity requested.");
+        return false;
+    }
+
+    SerialPort.Send("Commanding velocity: ");
+    SerialPort.SendLine(commandedVelocity);
+
+    // If there is a deadband defined, the range of the PWM scale is reduced.
+    double rangeUnsigned = 127.5 - (pwmDeadBand / 100 * 255);
+
+    // Find the scaling factor of our velocity range mapped to the PWM duty cycle
+    // range (the PWM to the ClearPath is bipolar, so the range starts at a 50%
+    // duty cycle).
+    double scaleFactor = rangeUnsigned / maxVelocity;
+
+    // Scale the velocity command to our duty cycle range.
+    double dutyRequest;
+    if (commandedVelocity < 0) {
+        dutyRequest = 127.5 - (pwmDeadBand / 100 * 255)
+                        + (commandedVelocity * scaleFactor);
+    }
+    else if (commandedVelocity > 0) {
+        dutyRequest = 127.5 + (pwmDeadBand / 100 * 255)
+                        + (commandedVelocity * scaleFactor);
+    }
+    else {
+        dutyRequest = 128.0;
+    }
+
+    // Command the move.
+    motor.MotorInBDuty(dutyRequest);
+
+    SerialPort.SendLine("Velocity Commanded");
+    return true;
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * LimitTorque
+ *
+ *    Command the motor to limit the maximum applied torque to (limit)%
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int limit  - The torque level to command
+ *
+ * Returns: True/False depending on whether the torque limit was successfully
+ * commanded.
+ */
+bool LimitTorque(double limit) {
+    if (limit > torqueLimit || limit < torqueLimitAlternate) {
+        SerialPort.SendLine("Torque limiting rejected, invalid torque requested.");
+        return false;
+    }
+    SerialPort.Send("Limit torque to: ");
+    SerialPort.Send(limit);
+    SerialPort.SendLine("%.");
+
+    // Find the scaling factor of our torque range mapped to the PWM duty cycle
+    // range (255 is the max duty cycle).
+    double scaleFactor = 255 / (torqueLimit - torqueLimitAlternate);
+
+    // Scale the torque limit command to our duty cycle range.
+    uint8_t dutyRequest = (torqueLimit - limit) * scaleFactor;
+
+    // Command the new torque limit.
+    motor.MotorInADuty(dutyRequest);
+
+    return true;
+}
+//------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cppproj
new file mode 100644
index 000000000..596e45314
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cppproj
@@ -0,0 +1,279 @@
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+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="FollowDigitalVelocityWithVariableTorque.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
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+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
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+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
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+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
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diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cpp
new file mode 100644
index 000000000..cd4ec1cf8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cpp
@@ -0,0 +1,293 @@
+/*
+ * Title: ManualVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Manual Velocity Control.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    bidirectional velocity moves. During operation, various move statuses are
+ *    written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Manual Velocity Control mode (In MSP select Mode>>Velocity>>Manual
+ *    Velocity Control, then hit the OK button).
+ * 3. In the MSP software:
+ *    * Define a Max Clockwise and Counter-Clockwise (CW/CCW) Velocity (On the
+ *      main MSP window fill in the textboxes labeled "Max CW Velocity (RPM)"
+ *      and "Max CCW Velocity (RPM)"). Any velocity commanded outside of this
+ *      range will be rejected.
+ *    * Set the Velocity Resolution to 2 (On the main MSP window check the
+ *      textbox labeled "Velocity Resolution (RPM per knob count)" 2 is
+ *      default). This means the commanded velocity will always be a multiple
+ *      of 2. For finer resolution, lower this value and change
+ *      velocityResolution in the sketch below to match.
+ *    * Set Knob Direction to As-Wired, and check the Has Detents box (On the
+ *      main MSP window check the dropdown labeled "Knob Direction" and the
+ *      checkbox directly below it labeled "Has Detents").
+ *    * On the main MSP window set the dropdown labeled "On Enable..." to be
+ *      "Zero Velocity".
+ *    * Set the HLFB mode to "ASG-Velocity w/Measured Torque" with a PWM carrier
+ *      frequency of 482 Hz through the MSP software (select Advanced>>High
+ *      Level Feedback [Mode]... then choose "ASG-Velocity w/Measured Torque" 
+ *      from the dropdown, make sure that 482 Hz is selected in the "PWM Carrier
+ *      Frequency" dropdown, and hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode6
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// This is the variable used to keep track of the current commanded velocity
+double commandedVelocity = 0;
+
+// A reference to the maximum clockwise and counter-clockwise velocities set in
+// the MSP software. These must match the values in MSP
+int32_t maxVelocityCW = 1000;
+int32_t maxVelocityCCW = 1000;
+
+// Each velocity commanded will be a multiple of this value, which must match
+// the Velocity Resolution value in MSP. Use a lower value here (and in MSP) to
+// command velocity with a finer resolution
+double velocityResolution = 2.0;
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveAtVelocity(double velocity);
+void HandleMotorFaults();
+
+int main() {
+    // Set all motor connectors to the correct mode for Manual Velocity
+    // mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    // the motor.
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert
+    SerialPort.SendLine("Waiting for HLFB...");
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Spin at 500 RPM in the CCW direction.
+        MoveAtVelocity(500);    // See below for the detailed function definition.
+        // Hold the velocity for 5 seconds before issuing a new command.
+        Delay_ms(5000);
+
+        // Spin at 100 RPM in the CW direction.
+        MoveAtVelocity(-100);
+        Delay_ms(5000);
+
+        // Spin at 750 RPM in the CW direction.
+        MoveAtVelocity(-750);
+        Delay_ms(5000);
+
+        // Spin at 1000 RPM in the CCW direction.
+        MoveAtVelocity(1000);
+        Delay_ms(5000);
+
+        // Command 0 RPM, the motor shaft is stationary.
+        MoveAtVelocity(0);
+        Delay_ms(5000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveAtVelocity
+ *
+ *    Triggers a quadrature output commanding the desired velocity.
+ *    Prints the velocity and move status to the USB serial port.
+ *    Returns when HLFB asserts (indicating move has successfully completed).
+ *
+ * Parameters:
+ *    double velocity  - The velocity in RPM to command
+ *
+ * Returns: True/False depending on whether a new velocity was reached
+ */
+bool MoveAtVelocity(double velocity) {
+    // If the same velocity is commanded there's nothing to do.
+    if (velocity == commandedVelocity) {
+        return false;
+    }
+
+    // Check to see if the requested velocity exceeds the valid range.
+    if (velocity > maxVelocityCCW || velocity < -maxVelocityCW) {
+        SerialPort.Send("An invalid velocity of ");
+        SerialPort.Send(velocity);
+        SerialPort.SendLine(" RPM has been requested.");
+        return false;
+    }
+
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Commanding ");
+    SerialPort.Send(velocity);
+    SerialPort.SendLine(" RPM");
+
+    // Determine which order the quadrature must be sent by determining if the
+    // new velocity is greater or less than the previously commanded velocity
+    // If greater, Input A begins the quadrature. If less, Input B begins the
+    // quadrature.
+    int32_t currentVelocityRounded = round(commandedVelocity / velocityResolution);
+    int32_t targetVelocityRounded = round(velocity / velocityResolution);
+    int32_t velocityDifference = labs(targetVelocityRounded - currentVelocityRounded);
+    for (int32_t i = 0; i < velocityDifference; i++) {
+        if (velocity > commandedVelocity) {
+            // Toggle Input A to begin the quadrature signal.
+            motor.MotorInAState(true);
+            // Command a 5 microsecond delay to ensure proper signal timing.
+            Delay_us(5);
+            motor.MotorInBState(true);
+            Delay_us(5);
+            motor.MotorInAState(false);
+            Delay_us(5);
+            motor.MotorInBState(false);
+            Delay_us(5);
+        }
+        else {
+            motor.MotorInBState(true);
+            Delay_us(5);
+            motor.MotorInAState(true);
+            Delay_us(5);
+            motor.MotorInBState(false);
+            Delay_us(5);
+            motor.MotorInAState(false);
+            Delay_us(5);
+        }
+    }
+
+    // Keeps track of the new commanded velocity
+    commandedVelocity = velocity;
+
+    // Waits for HLFB to assert (signaling the motor has successfully reached
+    // its target velocity).
+    SerialPort.SendLine("Ramping Speed... Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+
+    SerialPort.SendLine("Target Velocity Reached");
+    return true;
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------ 
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cppproj
new file mode 100644
index 000000000..4c2d1a1c3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cppproj
@@ -0,0 +1,279 @@
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+    <AssemblyName>Examples</AssemblyName>
+    <Name>ManualVelocity</Name>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ManualVelocity.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
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+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cpp
new file mode 100644
index 000000000..7b2994feb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cpp
@@ -0,0 +1,300 @@
+/*
+ * Title: 2IncrementsHomeToSwitch
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move Incremental Distance, 2 Increments (Home to Switch).
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    incremental moves. During operation, various move statuses are written to
+ *    the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move Incremental Distance, 2 Increments (Home to Switch) mode (In MSP
+ *    select Mode>>Position>>Move Incremental Distance, then with "2 Increments
+ *    (Home to Switch)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. If the ClearPath is configured for sensor-based homing, ensure that the
+ *    homing sensor is wired to Connector DI-6 (homing is optional, not required
+ *    in this operational mode or in this example).
+ * 5. The ClearPath must have defined Position Increments through the MSP
+ *    software which match the #define values below (On the main MSP window
+ *    check the "Position Increment Setup (cnts)" box and fill in the two text
+ *    boxes labeled "A off" and "A on").
+ * 6. Ensure the Trigger Pulse Time in MSP is set to 20ms. To configure, click
+ *    the "Setup..." button found under the "Trigger Pulse" label on the MSP's
+ *    main window, fill in the text box, and hit the OK button. Setting this to 
+ *    20ms allows trigger pulses to be as long as 60ms, which will accommodate 
+ *    our 25ms pulses used later.
+ * 7. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction or there are no
+ *    end of travel limits
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode4
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Define the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// The TRIGGER_PULSE_TIME is set to 25ms to ensure it is within the
+// Trigger Pulse Range defined in the MSP software (Default is 20-60ms)
+#define TRIGGER_PULSE_TIME 25
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Increments defined below must be set identically to the position increments
+// set in MSP
+#define POSITION_INCREMENT_1 1000  // Input A "off" setup selection, 1000 counts (CCW)
+#define POSITION_INCREMENT_2 -1000 // Input A "on" setup selection, -1000 counts (CW)
+
+// Specify the home sensor connector
+#define HomingSensor ConnectorDI6
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+void HomingSensorCallback();
+bool MoveIncrements(uint32_t numberOfIncrements, int32_t positionIncrement);
+void HandleMotorFaults();
+
+int main() {
+    // Sets all motor connectors to the correct mode for Incremental Distance
+    // mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // This section attaches the interrupt callback to the homing sensor pin,
+    // set to trigger on any change of sensor state.
+    HomingSensor.Mode(Connector::INPUT_DIGITAL);
+    HomingSensor.InterruptHandlerSet(HomingSensorCallback, InputManager::CHANGE);
+    // Set input B to match the initial state of the sensor.
+    motor.MotorInBState(HomingSensor.State());
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if homing is enabled
+    // in MSP.
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+	
+    while (true) {
+        // Move a distance equal to 1 * POSITION_INCREMENT_1 = 1000 counts.
+        // See below for the detailed function definition.
+        MoveIncrements(1, POSITION_INCREMENT_1);
+        // Stay settled for 1 second before moving again.
+        Delay_ms(1000);
+
+        // Move a distance equal to 1 * POSITION_INCREMENT_2 = -1000 counts.
+        MoveIncrements(1, POSITION_INCREMENT_2);
+        Delay_ms(1000);
+
+        // Note: If another incremental move is triggered in the same direction as
+        // an active move before deceleration begins, then the moves will be
+        // seamlessly combined into one continuous move
+
+        // Move a distance equal to 4 * POSITION_INCREMENT_1 = 4000 counts.
+        MoveIncrements(4, POSITION_INCREMENT_1);
+        Delay_ms(1000);
+
+        // Move a distance equal to 4 * POSITION_INCREMENT_2 = -4000 counts.
+        MoveIncrements(4, POSITION_INCREMENT_2);
+        Delay_ms(1000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveIncrements
+ *
+ *    Triggers an incremental move of length numberOfIncrements *
+ *    positionIncrement.
+ *    Prints the distance and move status to the USB serial port.
+ *    Returns when HLFB asserts (indicating move has successfully completed).
+ *
+ * Parameters:
+ *    int numberOfIncrements  - The number of increments to command
+ *    int positionIncrement   - The position increment commanded
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveIncrements(uint32_t numberOfIncrements, int32_t positionIncrement) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Moving ");
+    SerialPort.Send(numberOfIncrements);
+    SerialPort.Send(" * ");
+
+    switch (positionIncrement) {
+        case POSITION_INCREMENT_1:
+            // Sets Input A to position increment 1
+            SerialPort.SendLine(POSITION_INCREMENT_1);
+            motor.MotorInAState(false);
+            break;
+        case POSITION_INCREMENT_2:
+            // Sets Input A to position increment 2
+            SerialPort.SendLine(POSITION_INCREMENT_2);
+            motor.MotorInAState(true);
+            break;
+        default:
+            // If this case is reached then an incorrect positionIncrement was
+            // entered
+            return false;
+    }
+
+    // Delays for 2ms longer than the Input A, B filter setting in MSP
+    Delay_ms(2 + INPUT_A_B_FILTER);
+
+    // Sends trigger pulses to the motor
+    motor.EnableTriggerPulse(numberOfIncrements, TRIGGER_PULSE_TIME, true);
+
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+
+    SerialPort.SendLine("Move Done");
+    return true;
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * HomingSensorCallback
+ *
+ *    Reads the state of the homing sensor and passes the state to the motor.
+ */
+void HomingSensorCallback() {
+    // A 1 ms delay is required in order to pass the correct filtered sensor
+    // state.
+    Delay_ms(1);
+    motor.MotorInBState(HomingSensor.State());
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+    Delay_ms(3*TRIGGER_PULSE_TIME);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------ 
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cppproj
new file mode 100644
index 000000000..e0c44e362
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
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+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="Move2IncrementsHomeToSwitch.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
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+      <SubType>compile</SubType>
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+  <ItemGroup>
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+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
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+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cpp
new file mode 100644
index 000000000..dca375b82
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cpp
@@ -0,0 +1,287 @@
+/*
+ * Title: 4IncrementsHomeToHardStop
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Move Incremental Distance, 4 Increments (Home to Hard Stop).
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    incremental moves. During operation, various move statuses are written to
+ *    the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Move Incremental Distance, 4 Increments (Home to Hard Stop) mode (In
+ *    MSP select Mode>>Position>>Move Incremental Distance, then with "4
+ *    Increments (Home to Hard Stop)" selected hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Position Increments through the MSP
+ *    software which match the #define values below (On the main MSP window
+ *    check the "Position Increment Setup (cnts)" box and fill in the four text
+ *    boxes labeled "A off B off", "A on B off", "A off B on", and "A on B on").
+ * 5. Ensure the Trigger Pulse Time in MSP is set to 20ms. To configure, click
+ *    the "Setup..." button found under the "Trigger Pulse" label on the MSP's
+ *    main window, fill in the text box, and hit the OK button. Setting this to 
+ *    20ms allows trigger pulses to be as long as 60ms, which will accommodate 
+ *    our 25ms pulses used later.
+ * 6. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode4
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Define the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// The TRIGGER_PULSE_TIME is set to 25ms to ensure it is within the
+// Trigger Pulse Range defined in the MSP software (Default is 20-60ms)
+#define TRIGGER_PULSE_TIME 25
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Increments defined below must be set identically to the position increments
+// set in MSP
+#define POSITION_INCREMENT_1 750   // Inputs A off / B off, 750 counts (CCW)
+#define POSITION_INCREMENT_2 -750  // Inputs A on / B off, -750 counts (CW)
+#define POSITION_INCREMENT_3 1666  // Inputs A off / B on, 1666 counts (CCW)
+#define POSITION_INCREMENT_4 -1666 // Inputs A on / B on, -1666 counts (CW)
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveIncrements(uint32_t NumberOfIncrements, int32_t PositionIncrement);
+void HandleMotorFaults();
+
+int main() {
+    // Sets all motor connectors to the correct mode for Incremental Distance
+    // mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    // the motor.
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if homing is enabled
+    // in MSP.
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move a distance equal to 1 * POSITION_INCREMENT_1 = 750 counts
+        MoveIncrements(1, POSITION_INCREMENT_1);    // See below for the detailed
+                                                    // function definition
+        // Stay settled for 1 second before moving again.
+        Delay_ms(1000);
+
+        // Move a distance equal to 1 * POSITION_INCREMENT_2 = -750 counts
+        MoveIncrements(1, POSITION_INCREMENT_2);
+        Delay_ms(1000);
+
+        // Note: If another incremental move is triggered in the same direction as
+        // an active move before deceleration begins, then the moves will be
+        // seamlessly combined into one continuous move.
+
+        // Move a distance equal to 2 * POSITION_INCREMENT_3 = 3332 counts
+        MoveIncrements(2, POSITION_INCREMENT_3);
+        Delay_ms(1000);
+
+        // Move a distance equal to 2 * POSITION_INCREMENT_4 = -3332 counts
+        MoveIncrements(2, POSITION_INCREMENT_4);
+        Delay_ms(1000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveIncrements
+ *
+ *    Triggers an incremental move of length numberOfIncrements *
+ *    positionIncrement.
+ *    Prints the distance and move status to the USB serial port.
+ *    Returns when HLFB asserts (indicating move has successfully completed).
+ *
+ * Parameters:
+ *    int numberOfIncrements  - The number of increments to command
+ *    int positionIncrement   - The position increment commanded
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveIncrements(uint32_t numberOfIncrements, int32_t positionIncrement) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Moving ");
+    SerialPort.Send(numberOfIncrements);
+    SerialPort.Send(" * ");
+
+    switch (positionIncrement) {
+        case POSITION_INCREMENT_1:
+            // Sets Input A and B to position increment 1
+            SerialPort.SendLine(POSITION_INCREMENT_1);
+            motor.MotorInAState(false);
+            motor.MotorInBState(false);
+            break;
+        case POSITION_INCREMENT_2:
+            // Sets Input A and B to position increment 2
+            SerialPort.SendLine(POSITION_INCREMENT_2);
+            motor.MotorInAState(true);
+            motor.MotorInBState(false);
+            break;
+        case POSITION_INCREMENT_3:
+            // Sets Input A and B to position increment 3
+            SerialPort.SendLine(POSITION_INCREMENT_3);
+            motor.MotorInAState(false);
+            motor.MotorInBState(true);
+            break;
+        case POSITION_INCREMENT_4:
+            // Sets Input A and B to position increment 4
+            SerialPort.SendLine(POSITION_INCREMENT_4);
+            motor.MotorInAState(true);
+            motor.MotorInBState(true);
+            break;
+        default:
+            // If this case is reached then an incorrect positionIncrement was
+            // entered
+            return false;
+    }
+
+    // Delays 2ms longer than the Input A, B filter setting in MSP
+    Delay_ms(2 + INPUT_A_B_FILTER);
+
+    // Sends trigger pulses to the motor
+    motor.EnableTriggerPulse(numberOfIncrements, TRIGGER_PULSE_TIME, true);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+    Delay_ms(3*TRIGGER_PULSE_TIME);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------ 
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cppproj
new file mode 100644
index 000000000..96cc671c5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>Move4IncrementsHomeToHardStop</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
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+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+    <ToolchainSettings>
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+        </armgcccpp.compiler.symbols.DefSymbols>
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+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
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+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="Move4IncrementsHomeToHardStop.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cpp
new file mode 100644
index 000000000..6026caa51
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cpp
@@ -0,0 +1,289 @@
+/*
+ * Title: PulseBurstPositioning
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MCPV operational mode
+ *    Pulse Burst Positioning.
+ *
+ * Description:
+ *    This example enables a ClearPath motor and executes a repeating pattern of
+ *    positional move commands. During operation, various move statuses are
+ *    written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Pulse Burst Positioning mode (In MSP select Mode>>Position>>Pulse
+ *    Burst Positioning, then hit the OK button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Ensure the Trigger Pulse Time in MSP is set to 20ms. To configure, click
+ *    the "Setup..." button found under the "Trigger Pulse" label on the MSP's
+ *    main window, fill in the text box, and hit the OK button. Setting this to 
+ *    20ms allows trigger pulses to be as long as 60ms, which will accommodate 
+ *    our 25ms pulses used later.
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode10
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// The TRIGGER_PULSE_TIME is set to 25ms to ensure it is within the
+// Trigger Pulse Range defined in the MSP software (Default is 20ms, which 
+// allows a range of pulses up to 60ms)
+#define TRIGGER_PULSE_TIME 25
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveDistance(int32_t pulseNum);
+void PrintAlerts();
+void HandleAlerts();
+
+int main() {
+    // To command for Pulse Burst Positioning, use the step and direction
+    // interface with the acceleration and velocity limits set to their
+    // maximum values. The ClearPath will then take the pulses and enforce
+    // the motion profile constraints.
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity and acceleration for each command.
+    // The move profile in this mode is determined by ClearPath, so the two
+    // lines below should be left as is. Set your desired speed and accel in MSP
+    motor.VelMax(INT32_MAX);
+    motor.AccelMax(INT32_MAX);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if homing is enabled
+    // in MSP.
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move 6400 counts (positive direction) then wait 1000ms
+        MoveDistance(6400);
+        Delay_ms(1000);
+        // Move 19200 counts farther positive, then wait 1000ms
+        MoveDistance(19200);
+        Delay_ms(1000);
+
+        // Generates a trigger pulse on the enable line so the next move uses the
+        // Alt Speed Limit.
+        motor.EnableTriggerPulse(1, TRIGGER_PULSE_TIME, true);
+
+        // Move back 12800 counts (negative direction), then wait 1000ms
+        MoveDistance(-12800);
+        Delay_ms(1000);
+        // Move back 6400 counts (negative direction), then wait 1000ms
+        MoveDistance(-6400);
+        Delay_ms(1000);
+        // Move back to the start (negative 6400 pulses), then wait 1000ms
+        MoveDistance(-6400);
+        Delay_ms(1000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveDistance
+ *
+ *    Command "distance" number of step pulses away from the current position
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int distance  - The distance, in step pulses, to move
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveDistance(int32_t distance) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Move canceled.");		
+		SerialPort.SendLine();
+        return false;
+    }
+
+    SerialPort.Send("Commanding ");
+    SerialPort.Send(distance);
+    SerialPort.SendLine(" pulses");
+
+    // Command the move of incremental distance
+    motor.Move(distance);
+
+    // Add a short delay to allow HLFB to update
+    Delay_ms(2);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+   SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while ( (!motor.StepsComplete() || motor.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	SerialPort.SendLine("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		SerialPort.SendLine("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		SerialPort.SendLine("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		SerialPort.SendLine("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		SerialPort.SendLine("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		SerialPort.SendLine("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		SerialPort.SendLine("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(3*TRIGGER_PULSE_TIME);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	SerialPort.SendLine("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cppproj
new file mode 100644
index 000000000..cf381fdd2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cppproj
@@ -0,0 +1,279 @@
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+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cpp
new file mode 100644
index 000000000..b3141a4b7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cpp
@@ -0,0 +1,265 @@
+/*
+ * Title: RampUpDownToSelectedVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of the ClearPath-MC operational mode
+ *    Ramp Up/Down To Selected Velocity.
+ *
+ * Description:
+ *    This example enables and then moves a ClearPath motor between
+ *    preprogrammed velocity selections as defined in the MSP software. During
+ *    operation, various move statuses are written to the USB serial port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Ramp Up/Down to Selected Velocity mode (In MSP
+ *    select Mode>>Velocity>>Ramp Up/Down to Selected Velocity, then hit the OK
+ *    button).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Velocity
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Velocity w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have defined Velocity Selections through the MSP
+ *    software (On the main MSP window check the "Velocity Selection Setup
+ *    (RPM)" box and fill in the four text boxes labeled "A off B off", "A on B
+ *    off", "A off B on", and "A on B on").
+ * 5. Ensure the Input A & B filters in MSP are both set to 20ms (In MSP
+ *    select Advanced>>Input A, B Filtering... then in the Settings box fill in
+ *    the textboxes labeled "Input A Filter Time Constant (msec)" and "Input B
+ *    Filter Time Constant (msec)" then hit the OK button).
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * ** ClearPath Mode Informational Video: https://www.teknic.com/watch-video/#OpMode5
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// The INPUT_A_B_FILTER must match the Input A, B filter setting in
+// MSP (Advanced >> Input A, B Filtering...)
+#define INPUT_A_B_FILTER 20
+
+// Defines the motor's connector as ConnectorM0
+#define motor ConnectorM0
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor faults. 
+//	Any uncleared fault will cancel and disallow motion.
+// WARNING: enabling automatic fault handling will clear faults immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic fault handling, #define HANDLE_MOTOR_FAULTS (1)
+// To disable automatic fault handling, #define HANDLE_MOTOR_FAULTS (0)
+#define HANDLE_MOTOR_FAULTS (0)
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool RampToVelocitySelection(uint8_t velocityIndex);
+void HandleMotorFaults();
+
+int main() {
+    // Sets all motor connectors to the correct mode for Ramp Up/Down to
+    // Selected Velocity mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Enforces the state of the motor's A and B inputs before enabling
+    // the motor.
+    motor.MotorInAState(false);
+    motor.MotorInBState(false);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during enabling
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move to Velocity 1 defined in MSP (Inputs A off, B off).
+        // See below for the detailed function definition.
+        RampToVelocitySelection(1);
+
+        // Wait 1000ms.
+        Delay_ms(1000);
+        RampToVelocitySelection(2); // Inputs A on, B off
+        Delay_ms(1000);
+        RampToVelocitySelection(3); // Inputs A off, B on
+        Delay_ms(1000);
+        RampToVelocitySelection(4); // Inputs A on, B on
+        Delay_ms(1000);
+
+        // Alternatively, if you'd like to control the ClearPath motor's inputs
+        // directly using ClearCore inputs consider doing something like this:
+        /*
+        // Sets ClearPath's InA to DI6's state
+        motor.MotorInAState(ConnectorDI6.State());
+
+        // Sets ClearPath's InB to DI7's state
+        motor.MotorInBState(ConnectorDI7.State());
+        */
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * RampToVelocitySelection
+ *
+ *    Move to Velocity Selection number velocityIndex (defined in MSP)
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the target
+ *    velocity)
+ *
+ * Parameters:
+ *    int velocityIndex  - The velocity number to command (defined in MSP)
+ *
+ * Returns: True/False depending on whether the velocity selection was
+ *    successfully commanded.
+ */
+bool RampToVelocitySelection(uint8_t velocityIndex) {
+    // Check if a motor fault is currently preventing motion
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		if(HANDLE_MOTOR_FAULTS){
+			SerialPort.SendLine("Motor fault detected. Move canceled.");
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Motor fault detected. Move canceled. Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+        return false;
+    }
+
+    SerialPort.Send("Moving to Velocity Selection: ");
+    SerialPort.Send(velocityIndex);
+
+    switch (velocityIndex) {
+        case 1:
+            // Sets Input A and B for velocity 1
+            motor.MotorInAState(false);
+            motor.MotorInBState(false);
+            SerialPort.SendLine(" (Inputs A Off/B Off)");
+            break;
+        case 2:
+            // Sets Input A and B for velocity 2
+            motor.MotorInAState(true);
+            motor.MotorInBState(false);
+            SerialPort.SendLine(" (Inputs A On/B Off)");
+            break;
+        case 3:
+            // Sets Input A and B for velocity 3
+            motor.MotorInAState(false);
+            motor.MotorInBState(true);
+            SerialPort.SendLine(" (Inputs A Off/B On)");
+            break;
+        case 4:
+            // Sets Input A and B for velocity 4
+            motor.MotorInAState(true);
+            motor.MotorInBState(true);
+            SerialPort.SendLine(" (Inputs A On/B On)");
+            break;
+        default:
+            // If this case is reached then an incorrect velocityIndex was
+            // entered
+            return false;
+    }
+
+    // Ensures this delay is at least 2ms longer than the Input A, B filter
+    // setting in MSP
+    Delay_ms(2 + INPUT_A_B_FILTER);
+
+    // Waits for HLFB to assert (signaling the move has successfully reached its
+    // target velocity)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.MotorInFault) {
+        continue;
+    }
+	// Check if a motor faulted during move
+	// Clear fault if configured to do so 
+    if (motor.StatusReg().bit.MotorInFault) {
+		SerialPort.SendLine("Motor fault detected.");		
+		if(HANDLE_MOTOR_FAULTS){
+			HandleMotorFaults();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_MOTOR_FAULTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+ 
+/*------------------------------------------------------------------------------
+ * HandleMotorFaults
+ *
+ *    Clears motor faults by cycling enable to the motor.
+ *    Assumes motor is in fault 
+ *      (this function is called when motor.StatusReg.MotorInFault == true)
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleMotorFaults(){
+ 	SerialPort.SendLine("Handling fault: clearing faults by cycling enable signal to motor.");
+	motor.EnableRequest(false);
+	Delay_ms(10);
+	motor.EnableRequest(true);
+	Delay_ms(100);
+ }
+//------------------------------------------------------------------------------ 
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cppproj
new file mode 100644
index 000000000..ab393e4b6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cppproj
@@ -0,0 +1,280 @@
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+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="RampUpDownToSelectedVelocity.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/ClearPath-SD_Series_Examples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/ClearPath-SD_Series_Examples.atsln
new file mode 100644
index 000000000..3595c03bf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/ClearPath-SD_Series_Examples.atsln
@@ -0,0 +1,93 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "DualAxisSynchronized", "DualAxisSynchronized\DualAxisSynchronized.cppproj", "{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "MotorStatusRegister", "MotorStatusRegister\MotorStatusRegister.cppproj", "{DC2C88D6-AE42-4694-8134-CE5D6925C143}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "UserSeeksHome", "UserSeeksHome\UserSeeksHome.cppproj", "{C6D900F4-D840-4083-8D19-255372DE1887}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "MovePositionAbsolute", "MovePositionAbsolute\MovePositionAbsolute.cppproj", "{04316C86-F95D-4457-8A31-FE796F2995B9}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "MoveVelocity", "MoveVelocity\MoveVelocity.cppproj", "{2C78C43B-9124-4376-8C30-62CC21ACF892}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "MovePositionRelative", "MovePositionRelative\MovePositionRelative.cppproj", "{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+		Test|ARM = Test|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}.Debug|ARM.ActiveCfg = Debug|ARM
+		{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}.Debug|ARM.Build.0 = Debug|ARM
+		{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}.Release|ARM.ActiveCfg = Release|ARM
+		{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}.Release|ARM.Build.0 = Release|ARM
+		{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}.Test|ARM.ActiveCfg = Release|ARM
+		{42B2FF4D-A119-4C0C-A4A3-B2C9B7A5AC39}.Test|ARM.Build.0 = Release|ARM
+		{DC2C88D6-AE42-4694-8134-CE5D6925C143}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DC2C88D6-AE42-4694-8134-CE5D6925C143}.Debug|ARM.Build.0 = Debug|ARM
+		{DC2C88D6-AE42-4694-8134-CE5D6925C143}.Release|ARM.ActiveCfg = Release|ARM
+		{DC2C88D6-AE42-4694-8134-CE5D6925C143}.Release|ARM.Build.0 = Release|ARM
+		{DC2C88D6-AE42-4694-8134-CE5D6925C143}.Test|ARM.ActiveCfg = Release|ARM
+		{DC2C88D6-AE42-4694-8134-CE5D6925C143}.Test|ARM.Build.0 = Release|ARM
+		{C6D900F4-D840-4083-8D19-255372DE1887}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C6D900F4-D840-4083-8D19-255372DE1887}.Debug|ARM.Build.0 = Debug|ARM
+		{C6D900F4-D840-4083-8D19-255372DE1887}.Release|ARM.ActiveCfg = Release|ARM
+		{C6D900F4-D840-4083-8D19-255372DE1887}.Release|ARM.Build.0 = Release|ARM
+		{C6D900F4-D840-4083-8D19-255372DE1887}.Test|ARM.ActiveCfg = Release|ARM
+		{C6D900F4-D840-4083-8D19-255372DE1887}.Test|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Test|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Test|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Test|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Test|ARM.Build.0 = Release|ARM
+		{04316C86-F95D-4457-8A31-FE796F2995B9}.Debug|ARM.ActiveCfg = Debug|ARM
+		{04316C86-F95D-4457-8A31-FE796F2995B9}.Debug|ARM.Build.0 = Debug|ARM
+		{04316C86-F95D-4457-8A31-FE796F2995B9}.Release|ARM.ActiveCfg = Release|ARM
+		{04316C86-F95D-4457-8A31-FE796F2995B9}.Release|ARM.Build.0 = Release|ARM
+		{04316C86-F95D-4457-8A31-FE796F2995B9}.Test|ARM.ActiveCfg = Debug|ARM
+		{04316C86-F95D-4457-8A31-FE796F2995B9}.Test|ARM.Build.0 = Debug|ARM
+		{2C78C43B-9124-4376-8C30-62CC21ACF892}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2C78C43B-9124-4376-8C30-62CC21ACF892}.Debug|ARM.Build.0 = Debug|ARM
+		{2C78C43B-9124-4376-8C30-62CC21ACF892}.Release|ARM.ActiveCfg = Release|ARM
+		{2C78C43B-9124-4376-8C30-62CC21ACF892}.Release|ARM.Build.0 = Release|ARM
+		{2C78C43B-9124-4376-8C30-62CC21ACF892}.Test|ARM.ActiveCfg = Debug|ARM
+		{2C78C43B-9124-4376-8C30-62CC21ACF892}.Test|ARM.Build.0 = Debug|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Debug|ARM.ActiveCfg = Debug|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Debug|ARM.Build.0 = Debug|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Release|ARM.ActiveCfg = Release|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Release|ARM.Build.0 = Release|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Test|ARM.ActiveCfg = Debug|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Test|ARM.Build.0 = Debug|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cpp
new file mode 100644
index 000000000..095453e79
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cpp
@@ -0,0 +1,324 @@
+/*
+ * Title: DualAxisSynchronized
+ *
+ * Objective:
+ *    This example demonstrates control of two ClearPath-SD motors synchronously
+ *    in Step and Direction mode. Use this example when two motors must follow
+ *    identical commands (e.g. a mechanically connected dual-axis or gantry).
+ *
+ * Description:
+ *    This example enables two motors then commands a repeating series of
+ *    synchronized moves. Move status is printed to the USB serial port. This
+ *    example commands a max travel of 25600 pulses.
+ *
+ * Requirements:
+ * 1. Two ClearPath motors must be connected, one to Connector M-0 the other to
+ *    Connector M-1.
+ * 2. The connected ClearPath motors must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motors must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. If the two motors must spin in opposite directions (i.e. they are mounted
+ *    facing different directions), check the "Reverse Direction" checkbox of
+ *    one motor in MSP.
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motors to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor0 ConnectorM0
+#define motor1 ConnectorM1
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial connector to use: ConnectorUsb, ConnectorCOM0, or
+// ConnectorCOM1
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int32_t velocityLimit = 10000; // pulses per sec
+int32_t accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool SynchronizedMove(int32_t distance);
+void PrintAlerts();
+void HandleAlerts();
+
+int main() {
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Put the motor connectors into the HLFB mode to read bipolar PWM (the
+    // correct mode for ASG w/ Measured Torque)
+    motor0.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    motor1.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+
+    // Set the HFLB carrier frequencies to 482 Hz
+    motor0.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+    motor1.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity for each move.
+    motor0.VelMax(velocityLimit);
+    motor1.VelMax(velocityLimit);
+
+    // Sets the maximum acceleration for each move.
+    motor0.AccelMax(accelerationLimit);
+    motor1.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motors; homing will begin automatically if enabled in MSP.
+    motor0.EnableRequest(true);
+    SerialPort.SendLine("Motor 0 Enabled");
+    motor1.EnableRequest(true);
+    SerialPort.SendLine("Motor 1 Enabled");
+
+    // Waits for both motors to finish enabling.
+    uint32_t lastStatusTime = Milliseconds();
+    SerialPort.SendLine("Waiting for HLFB...");
+    while ( (motor0.HlfbState() != MotorDriver::HLFB_ASSERTED ||
+            motor1.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+            !motor0.StatusReg().bit.AlertsPresent && 
+            !motor1.StatusReg().bit.AlertsPresent) {
+        // Periodically prints out why the application is waiting.
+        if (Milliseconds() - lastStatusTime > 1000) {
+            SerialPort.SendLine("Waiting for HLFB to assert on both motors");
+            lastStatusTime = Milliseconds();
+        }
+    }
+    // Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor0.StatusReg().bit.AlertsPresent || 
+		motor1.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move 6400 counts (positive direction) then wait 2000ms.
+        SynchronizedMove(6400);
+        Delay_ms(2000);
+        // Move 19200 counts farther positive, then wait 2000ms.
+        SynchronizedMove(19200);
+        Delay_ms(2000);
+        // Move back 12800 counts (negative direction), then wait 2000ms.
+        SynchronizedMove(-12800);
+        Delay_ms(2000);
+        // Move back 6400 counts (negative direction), then wait 2000ms.
+        SynchronizedMove(-6400);
+        Delay_ms(2000);
+        // Move back to the start (negative 6400 pulses), then wait 2000ms.
+        SynchronizedMove(-6400);
+        Delay_ms(2000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * SynchronizedMove
+ *
+ *    Moves two motors an incremental distance synchronously.
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int distance  - The distance, in counts, to move
+ *
+ * Returns:  True/False depending on whether the moves were successfully
+ *    triggered.
+ */
+bool SynchronizedMove(int32_t distance) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor0.StatusReg().bit.AlertsPresent || motor1.StatusReg().bit.AlertsPresent ) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Move canceled.");		
+		SerialPort.SendLine();
+        return false;
+    }
+
+    SerialPort.Send("Moving distance: ");
+    SerialPort.SendLine(distance);
+
+    // Move both motors the same distance.
+    motor0.Move(distance);
+    motor1.Move(distance);
+
+    // Wait until both motors complete their moves.
+    uint32_t lastStatusTime = Milliseconds();
+    while ( (!motor0.StepsComplete() || motor0.HlfbState() != MotorDriver::HLFB_ASSERTED ||
+           !motor1.StepsComplete() || motor1.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+		   !motor0.StatusReg().bit.AlertsPresent && !motor1.StatusReg().bit.AlertsPresent ){
+        // Periodically print out why the application is waiting.
+        if (Milliseconds() - lastStatusTime > 1000) {
+            SerialPort.SendLine("Waiting for HLFB to assert on both motors");
+            lastStatusTime = Milliseconds();
+        }
+
+        // Check if motor alert occurred during move
+		// Clear alert if configured to do so 
+        if (motor0.StatusReg().bit.AlertsPresent || motor1.StatusReg().bit.AlertsPresent){
+            motor0.MoveStopAbrupt();
+            motor1.MoveStopAbrupt();
+			SerialPort.SendLine("Motor alert detected.");		
+			PrintAlerts();
+			if(HANDLE_ALERTS){
+				HandleAlerts();
+			} else {
+				SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+			}
+			SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+			SerialPort.SendLine();
+			return false;
+		} 
+    }
+
+    SerialPort.SendLine("Move Done");
+    return true;
+}
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor0" and "motor1" to be defined as ClearCore motor connectors
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts on motor0
+ 	SerialPort.SendLine("Alerts present on motor0: ");
+	if(motor0.AlertReg().bit.MotionCanceledInAlert){
+		SerialPort.SendLine("    MotionCanceledInAlert "); }
+	if(motor0.AlertReg().bit.MotionCanceledPositiveLimit){
+		SerialPort.SendLine("    MotionCanceledPositiveLimit "); }
+	if(motor0.AlertReg().bit.MotionCanceledNegativeLimit){
+		SerialPort.SendLine("    MotionCanceledNegativeLimit "); }
+	if(motor0.AlertReg().bit.MotionCanceledSensorEStop){
+		SerialPort.SendLine("    MotionCanceledSensorEStop "); }
+	if(motor0.AlertReg().bit.MotionCanceledMotorDisabled){
+		SerialPort.SendLine("    MotionCanceledMotorDisabled "); }
+	if(motor0.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("    MotorFaulted ");
+	}
+	
+	// report status of alerts on motor1
+ 	SerialPort.SendLine("Alerts present on motor1: ");
+	if(motor1.AlertReg().bit.MotionCanceledInAlert){
+		SerialPort.SendLine("    MotionCanceledInAlert "); }
+	if(motor1.AlertReg().bit.MotionCanceledPositiveLimit){
+		SerialPort.SendLine("    MotionCanceledPositiveLimit "); }
+	if(motor1.AlertReg().bit.MotionCanceledNegativeLimit){
+		SerialPort.SendLine("    MotionCanceledNegativeLimit "); }
+	if(motor1.AlertReg().bit.MotionCanceledSensorEStop){
+		SerialPort.SendLine("    MotionCanceledSensorEStop "); }
+	if(motor1.AlertReg().bit.MotionCanceledMotorDisabled){
+		SerialPort.SendLine("    MotionCanceledMotorDisabled "); }
+	if(motor1.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor0" and "motor1" to be defined as ClearCore motor connectors
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	// for each motor, if a motor fault is present, clear it by cycling enable
+	if(motor0.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("Faults present on motor0. Cycling enable signal to motor to clear faults.");
+		motor0.EnableRequest(false);
+		Delay_ms(10);
+		motor0.EnableRequest(true);
+	}
+	if(motor1.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("Faults present on motor1. Cycling enable signal to motor to clear faults.");
+		motor1.EnableRequest(false);
+		Delay_ms(10);
+		motor1.EnableRequest(true);
+	}
+	// clear alerts
+	SerialPort.SendLine("Clearing alerts on both motors.");
+	motor0.ClearAlerts();
+	motor1.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cppproj
new file mode 100644
index 000000000..f50169f9c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{42b2ff4d-a119-4c0c-a4a3-b2c9b7a5ac39}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>DualAxisSynchronized</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
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+        </armgcccpp.compiler.symbols.DefSymbols>
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+            <Value>libm</Value>
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+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="DualAxisSynchronized.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cpp
new file mode 100644
index 000000000..9dc45eecc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cpp
@@ -0,0 +1,213 @@
+/*
+ * Title: MotorStatusRegister
+ *
+ * Objective:
+ *    This example demonstrates how to read and display bits in the ClearCore's
+ *    MotorDriver status register.
+ *
+ * Description:
+ *    This example gets a snapshot of the status register for each MotorDriver
+ *    connector with an attached motor. Then, the state of the status register
+ *    bits is printed to the USB serial port.
+ *
+ * Requirements:
+ * ** A ClearPath motor must be connected to Connector M-0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// The containers for our motor objects. If only some of the motor connectors
+// are being used, remove the unused entries from the following arrays and
+// reduce motorConnectorCount.
+MotorDriver *motorConnectors[] = {&ConnectorM0, &ConnectorM1,
+                                  &ConnectorM2, &ConnectorM3
+                                 };
+char motorConnectorNames[][4] = { "M-0", "M-1", "M-2", "M-3" };
+uint8_t motorConnectorCount = 4;
+
+// Hold a string representation of each motor's ready state.
+char *readyStateStr;
+
+// Declare our helper function so that it may be used before it is defined.
+char *ReadyStateString(MotorDriver::MotorReadyStates readyState);
+
+int main() {
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        // Get a copy of the motor status register for each motor connector.
+        for (uint8_t i = 0; i < motorConnectorCount; i++) {
+            MotorDriver *motor = motorConnectors[i];
+            volatile const MotorDriver::StatusRegMotor &statusReg = motor->StatusReg();
+			volatile const MotorDriver::AlertRegMotor &alertReg = motor->AlertReg();
+
+            SerialPort.Send("Motor status register for motor M");
+			SerialPort.Send(i);
+			SerialPort.Send(": ");
+			SerialPort.SendLine(statusReg.reg, 2); // prints the status register in binary
+	
+			SerialPort.Send("AtTargetPosition:	");
+			SerialPort.SendLine(statusReg.bit.AtTargetPosition);
+
+			SerialPort.Send("StepsActive:     	");
+			SerialPort.SendLine(statusReg.bit.StepsActive);
+
+			SerialPort.Send("AtTargetVelocity:	");
+			SerialPort.SendLine(statusReg.bit.AtTargetVelocity);
+		
+			SerialPort.Send("MoveDirection:   	");
+			SerialPort.SendLine(statusReg.bit.MoveDirection);
+
+			SerialPort.Send("MotorInFault:    	");
+			SerialPort.SendLine(statusReg.bit.MotorInFault);
+
+			SerialPort.Send("Enabled:         	");
+			SerialPort.SendLine(statusReg.bit.Enabled);
+
+			SerialPort.Send("PositionalMove:  	");
+			SerialPort.SendLine(statusReg.bit.PositionalMove);
+
+			SerialPort.Send("HLFB State:		");
+			switch (statusReg.bit.HlfbState) {
+				case 0:
+					SerialPort.SendLine("HLFB_DEASSERTED");
+					break;
+				case 1:
+					SerialPort.SendLine("HLFB_ASSERTED");
+					break;
+				case 2:
+					SerialPort.SendLine("HLFB_HAS_MEASUREMENT");
+					break;
+				case 3:
+					SerialPort.SendLine("HLFB_UNKNOWN");
+					break;
+				default:
+					// something has gone wrong if this is printed
+					SerialPort.SendLine("???");
+			}
+
+			SerialPort.Send("AlertsPresent:   	");
+			SerialPort.SendLine(statusReg.bit.AlertsPresent);
+
+			SerialPort.Send("Ready state:		");
+			switch (statusReg.bit.ReadyState) {
+				case MotorDriver::MOTOR_DISABLED:
+					SerialPort.SendLine("Disabled");
+					break;
+				case MotorDriver::MOTOR_ENABLING:
+					SerialPort.SendLine("Enabling");
+					break;
+				case MotorDriver::MOTOR_FAULTED:
+					SerialPort.SendLine("Faulted");
+					break;
+				case MotorDriver::MOTOR_READY:
+					SerialPort.SendLine("Ready");
+					break;
+				case MotorDriver::MOTOR_MOVING:
+					SerialPort.SendLine("Moving");
+					break;
+				default:
+					// something has gone wrong if this is printed
+					SerialPort.SendLine("???");
+			}
+	
+			SerialPort.Send("Triggering:      	");
+			SerialPort.SendLine(statusReg.bit.Triggering);
+
+			SerialPort.Send("InPositiveLimit: 	");
+			SerialPort.SendLine(statusReg.bit.InPositiveLimit);
+
+			SerialPort.Send("InNegativeLimit: 	");
+			SerialPort.SendLine(statusReg.bit.InNegativeLimit);
+
+			SerialPort.Send("InEStopSensor:   	");
+			SerialPort.SendLine(statusReg.bit.InEStopSensor);	
+
+			SerialPort.SendLine("--------------------------------");
+	
+		
+			if (statusReg.bit.AlertsPresent){
+				SerialPort.Send("Alert register:	");
+				SerialPort.SendLine(alertReg.reg, 2); // prints the alert register in binary
+
+				SerialPort.Send("MotionCanceledInAlert:         ");
+				SerialPort.SendLine(alertReg.bit.MotionCanceledInAlert);
+
+				SerialPort.Send("MotionCanceledPositiveLimit:   ");
+				SerialPort.SendLine(alertReg.bit.MotionCanceledPositiveLimit);
+
+				SerialPort.Send("MotionCanceledNegativeLimit:   ");
+				SerialPort.SendLine(alertReg.bit.MotionCanceledNegativeLimit);
+
+				SerialPort.Send("MotionCanceledSensorEStop:     ");
+				SerialPort.SendLine(alertReg.bit.MotionCanceledSensorEStop);
+
+				SerialPort.Send("MotionCanceledMotorDisabled:   ");
+				SerialPort.SendLine(alertReg.bit.MotionCanceledMotorDisabled);
+
+				SerialPort.Send("MotorFaulted:                  ");
+				SerialPort.SendLine(alertReg.bit.MotorFaulted);
+
+				SerialPort.SendLine("--------------------------------");
+			}
+        }
+
+        // Wait a few seconds then repeat...
+        Delay_ms(5000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * ReadyStateString
+ *
+ *    Converts the state of a motor status register bit into a user-readable
+ *    format so it may be printed to a serial port.
+ *
+ * Parameters:
+ *    MotorReadyStates readyState  - The current state of the ReadyState bit
+ *
+ * Returns: Text describing the state of the status bit.
+ */
+char *ReadyStateString(MotorDriver::MotorReadyStates readyState) {
+    switch (readyState) {
+        case MotorDriver::MOTOR_DISABLED:
+            return (char *)"Disabled";
+        case MotorDriver::MOTOR_ENABLING:
+            return (char *)"Enabling";
+        case MotorDriver::MOTOR_FAULTED:
+            return (char *)"Faulted";
+        case MotorDriver::MOTOR_READY:
+            return (char *)"Ready";
+        case MotorDriver::MOTOR_MOVING:
+            return (char *)"Moving";
+        default:
+            // Something has gone wrong if this is printed
+            return (char *)"???";
+    }
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cppproj
new file mode 100644
index 000000000..fdd3b6e96
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{dc2c88d6-ae42-4694-8134-ce5d6925c143}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
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+    <Compile Include="..\Device_Startup\startup_same53.c">
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+      <Link>Device_Startup\startup_same53.c</Link>
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+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
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+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
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+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cpp
new file mode 100644
index 000000000..54c639ac6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cpp
@@ -0,0 +1,269 @@
+/*
+ * Title: MovePositionAbsolute
+ *
+ * Objective:
+ *    This example demonstrates control of a ClearPath motor in Step and
+ *    Direction mode.
+ *
+ * Description:
+ *    This example enables a ClearPath then commands a series of repeating
+ *    absolute position moves to the motor.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes positive absolute position moves,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int32_t velocityLimit = 10000; // pulses per sec
+int32_t accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveAbsolutePosition(int32_t position);
+void PrintAlerts();
+void HandleAlerts();
+
+int main() {
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(velocityLimit);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if enabled
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move to +10000 counts (positive direction), then wait 2000ms
+        MoveAbsolutePosition(10000);
+        Delay_ms(2000);
+        // Move to 19200 counts, then wait 2000ms
+        MoveAbsolutePosition(19200);
+        Delay_ms(2000);
+        // Move to 12800 counts, then wait 2000ms
+        MoveAbsolutePosition(12800);
+        Delay_ms(2000);
+        // Move back to "home", then wait 2000ms
+        MoveAbsolutePosition(0);
+        Delay_ms(2000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveAbsolutePosition
+ *
+ *    Command step pulses to move the motor's current position to the absolute
+ *    position specified by "position"
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int position  - The absolute position, in step pulses, to move to
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveAbsolutePosition(int32_t position) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Move canceled.");		
+		SerialPort.SendLine();
+        return false;
+    }
+	
+    SerialPort.Send("Moving to absolute position: ");
+    SerialPort.SendLine(position);
+
+    // Command the move of absolute distance
+    motor.Move(position, MotorDriver::MOVE_TARGET_ABSOLUTE);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while ( (!motor.StepsComplete() || motor.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	SerialPort.SendLine("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		SerialPort.SendLine("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		SerialPort.SendLine("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		SerialPort.SendLine("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		SerialPort.SendLine("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		SerialPort.SendLine("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		SerialPort.SendLine("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(10);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	SerialPort.SendLine("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cppproj
new file mode 100644
index 000000000..dae33edb6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cppproj
@@ -0,0 +1,279 @@
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+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>MovePositionAbsolute</Name>
+    <RootNamespace>Examples</RootNamespace>
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+          <ListValues>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="MovePositionAbsolute.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
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+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cpp
new file mode 100644
index 000000000..9de1632e4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cpp
@@ -0,0 +1,271 @@
+/*
+ * Title: MovePositionRelative
+ *
+ * Objective:
+ *    This example demonstrates control of a ClearPath motor in Step and
+ *    Direction mode.
+ *
+ * Description:
+ *    This example enables a ClearPath then commands a series of repeating
+ *    moves to the motor.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ *
+ * ** Note: Homing is optional, and not required in this operational mode or in
+ *    this example. This example makes its first move in the positive direction,
+ *    assuming any homing move occurs in the negative direction.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the velocity and acceleration limits to be used for each move
+int32_t velocityLimit = 10000; // pulses per sec
+int32_t accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveDistance(int32_t distance);
+void PrintAlerts();
+void HandleAlerts();
+
+int main() {
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(velocityLimit);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if enabled
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move 6400 counts (positive direction), then wait 2000ms
+        MoveDistance(6400);
+        Delay_ms(2000);
+        // Move 19200 counts farther positive, then wait 2000ms
+        MoveDistance(19200);
+        Delay_ms(2000);
+        // Move back 12800 counts (negative direction), then wait 2000ms
+        MoveDistance(-12800);
+        Delay_ms(2000);
+        // Move back 6400 counts (negative direction), then wait 2000ms
+        MoveDistance(-6400);
+        Delay_ms(2000);
+        // Move back to the start (negative 6400 pulses), then wait 2000ms
+        MoveDistance(-6400);
+        Delay_ms(2000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveDistance
+ *
+ *    Command "distance" number of step pulses away from the current position
+ *    Prints the move status to the USB serial port
+ *    Returns when HLFB asserts (indicating the motor has reached the commanded
+ *    position)
+ *
+ * Parameters:
+ *    int distance  - The distance, in step pulses, to move
+ *
+ * Returns: True/False depending on whether the move was successfully triggered.
+ */
+bool MoveDistance(int32_t distance) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Move canceled.");		
+		SerialPort.SendLine();
+        return false;
+    }
+
+    SerialPort.Send("Moving distance: ");
+    SerialPort.SendLine(distance);
+
+    // Command the move of incremental distance
+    motor.Move(distance);
+
+    // Waits for HLFB to assert (signaling the move has successfully completed)
+    SerialPort.SendLine("Moving.. Waiting for HLFB");
+    while ( (!motor.StepsComplete() || motor.HlfbState() != MotorDriver::HLFB_ASSERTED) &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	SerialPort.SendLine("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		SerialPort.SendLine("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		SerialPort.SendLine("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		SerialPort.SendLine("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		SerialPort.SendLine("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		SerialPort.SendLine("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		SerialPort.SendLine("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(10);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	SerialPort.SendLine("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cppproj
new file mode 100644
index 000000000..7b25e245c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
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+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>MovePositionRelative</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
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+          <ListValues>
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+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
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+        <armgcccpp.linker.libraries.LibrarySearchPaths>
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+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="MovePositionRelative.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
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+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
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+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
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+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cpp
new file mode 100644
index 000000000..5dc07eb73
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cpp
@@ -0,0 +1,262 @@
+/*
+ * Title: MoveVelocity
+ *
+ * Objective:
+ *    This example demonstrates control of a ClearPath motor in Step and
+ *    Direction mode, making velocity moves.
+ *
+ * Description:
+ *    This example enables a ClearPath then commands a series of repeating
+ *    velocity moves to the motor.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulse frequency sent by ClearCore to 
+ *    command the same frequency in motor encoder counts/sec, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// This example has built-in functionality to automatically clear motor alerts, 
+//	including motor shutdowns. Any uncleared alert will cancel and disallow motion.
+// WARNING: enabling automatic alert handling will clear alerts immediately when 
+//	encountered and return a motor to a state in which motion is allowed. Before 
+//	enabling this functionality, be sure to understand this behavior and ensure 
+//	your system will not enter an unsafe state. 
+// To enable automatic alert handling, #define HANDLE_ALERTS (1)
+// To disable automatic alert handling, #define HANDLE_ALERTS (0)
+#define HANDLE_ALERTS (0)
+
+// Define the acceleration limit to be used for each move
+int32_t accelerationLimit = 100000; // pulses per sec^2
+
+// Declares user-defined helper functions.
+// The definition/implementations of these functions are at the bottom of the sketch.
+bool MoveAtVelocity(int32_t velocity);
+void PrintAlerts();
+void HandleAlerts();
+
+int main() {
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor; homing will begin automatically if enabled
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    SerialPort.SendLine("Waiting for HLFB...");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED &&
+			!motor.StatusReg().bit.AlertsPresent) {
+        continue;
+    }
+	// Check if motor alert occurred during enabling
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Enabling may not have completed as expected. Proceed with caution.");		
+ 		SerialPort.SendLine();
+	} else {
+		SerialPort.SendLine("Motor Ready");	
+	}
+
+    while (true) {
+        // Move at 1,000 steps/sec for 2000ms
+        MoveAtVelocity(1000);
+        Delay_ms(2000);
+        // Move at -5,000 steps/sec for 2000ms
+        MoveAtVelocity(-5000);
+        Delay_ms(2000);
+        // Move at 10,000 steps/sec for 2000ms
+        MoveAtVelocity(10000);
+        Delay_ms(2000);
+        // Move at -10,000 steps/sec for 2000ms
+        MoveAtVelocity(-10000);
+        Delay_ms(2000);
+        // Command a 0 steps/sec velocity to stop motion for 2000ms
+        MoveAtVelocity(0);
+        Delay_ms(2000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveAtVelocity
+ *
+ *    Command the motor to move at the specified "velocity", in steps/second.
+ *    Prints the move status to the USB serial port
+ *
+ * Parameters:
+ *    int velocity  - The velocity, in step steps/sec, to command
+ *
+ * Returns: None
+ */
+bool MoveAtVelocity(int32_t velocity) {
+    // Check if a motor alert is currently preventing motion
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic alert handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Move canceled.");		
+		SerialPort.SendLine();
+        return false;
+    }
+
+    SerialPort.Send("Commanding velocity: ");
+    SerialPort.SendLine(velocity);
+
+    // Command the velocity move
+    motor.MoveVelocity(velocity);
+
+    // Waits for the step command to ramp up/down to the commanded velocity. 
+    // This time will depend on your Acceleration Limit.
+    SerialPort.SendLine("Ramping to speed...");
+    while (!motor.StatusReg().bit.AtTargetVelocity) {
+        continue;
+    }
+	// Check if motor alert occurred during move
+	// Clear alert if configured to do so 
+    if (motor.StatusReg().bit.AlertsPresent) {
+		SerialPort.SendLine("Motor alert detected.");		
+		PrintAlerts();
+		if(HANDLE_ALERTS){
+			HandleAlerts();
+		} else {
+			SerialPort.SendLine("Enable automatic fault handling by setting HANDLE_ALERTS to 1.");
+		}
+		SerialPort.SendLine("Motion may not have completed as expected. Proceed with caution.");
+		SerialPort.SendLine();
+		return false;
+    } else {
+		SerialPort.SendLine("Move Done");
+		return true;
+	}
+}
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * PrintAlerts
+ *
+ *    Prints active alerts.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void PrintAlerts(){
+	// report status of alerts
+ 	SerialPort.SendLine("Alerts present: ");
+	if(motor.AlertReg().bit.MotionCanceledInAlert){
+		SerialPort.SendLine("    MotionCanceledInAlert "); }
+	if(motor.AlertReg().bit.MotionCanceledPositiveLimit){
+		SerialPort.SendLine("    MotionCanceledPositiveLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledNegativeLimit){
+		SerialPort.SendLine("    MotionCanceledNegativeLimit "); }
+	if(motor.AlertReg().bit.MotionCanceledSensorEStop){
+		SerialPort.SendLine("    MotionCanceledSensorEStop "); }
+	if(motor.AlertReg().bit.MotionCanceledMotorDisabled){
+		SerialPort.SendLine("    MotionCanceledMotorDisabled "); }
+	if(motor.AlertReg().bit.MotorFaulted){
+		SerialPort.SendLine("    MotorFaulted ");
+	}
+ }
+//------------------------------------------------------------------------------
+
+
+/*------------------------------------------------------------------------------
+ * HandleAlerts
+ *
+ *    Clears alerts, including motor faults. 
+ *    Faults are cleared by cycling enable to the motor.
+ *    Alerts are cleared by clearing the ClearCore alert register directly.
+ *
+ * Parameters:
+ *    requires "motor" to be defined as a ClearCore motor connector
+ *
+ * Returns: 
+ *    none
+ */
+ void HandleAlerts(){
+	if(motor.AlertReg().bit.MotorFaulted){
+		// if a motor fault is present, clear it by cycling enable
+		SerialPort.SendLine("Faults present. Cycling enable signal to motor to clear faults.");
+		motor.EnableRequest(false);
+		Delay_ms(10);
+		motor.EnableRequest(true);
+	}
+	// clear alerts
+	SerialPort.SendLine("Clearing alerts.");
+	motor.ClearAlerts();
+ }
+//------------------------------------------------------------------------------
+
+ 
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cppproj
new file mode 100644
index 000000000..659a28d6c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cppproj
@@ -0,0 +1,279 @@
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cpp
new file mode 100644
index 000000000..1e79c2f60
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cpp
@@ -0,0 +1,175 @@
+/*
+ * Title: UserSeeksHome
+ *
+ * Objective:
+ *    This example demonstrates control of the "User Seeks Home" homing feature
+ *    of a ClearPath-SD motor (this feature is also available in ClearPath-MCPV
+ *    Pulse Burst Positioning Mode, but this example is only for Step and
+ *    Direction mode). "User Seeks Home" should be used when more flexibility is
+ *    required during a homing sequence (e.g. to move at multiple velocities,
+ *    stopping to perform other tasks, manually exiting a homing sequence, or
+ *    using sensor-based homing).
+ *
+ * Description:
+ *    This example enables the motor, moves towards a hardstop at a velocity for
+ *    2 seconds, then with a slower velocity until clamping into the hardstop.
+ *    An offset position move is then commanded away from the hardstop to
+ *    complete the homing sequence. Homing status is printed to the USB serial
+ *    port.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. The ClearPath must have homing enabled and configured. To configure, look
+ *    under the "Homing" label on the MSP's main window, check the "Enabled"
+ *    radial button, then click the "Setup..." button. Set the Homing Style set
+ *    to "User seeks home; ClearPath ASG signals when homing is complete" then
+ *    hit the OK button.
+ * 5. A hardstop for homing must be installed on your mechanics. Set the homing
+ *    torque limit accordingly. This torque will be used to move toward and
+ *    clamp up against the hardstop.
+ *
+ * ** IMPORTANT: This examples homes in the Positive (CCW) direction, assuming
+ *    the hardstop is on the positive end of travel
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ *
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Selects the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial connector to use: ConnectorUsb, ConnectorCOM0, or
+// ConnectorCOM1
+#define SerialPort ConnectorUsb
+
+int main() {
+    // Sets the input clocking rate. This normal rate is ideal for ClearPath
+    // step and direction applications.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Sets the maximum velocity in step pulses/sec.
+    motor.VelMax(10000);
+    // Sets the maximum acceleration in step pulses/sec^2.
+    motor.AccelMax(100000);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor
+    motor.EnableRequest(true);
+    SerialPort.SendLine("Motor Enabled");
+
+    // Check if an alert would prevent motion
+    if (motor.StatusReg().bit.AlertsPresent) {
+        // In this case, we can't proceed with homing.
+        SerialPort.SendLine("Motor status: 'In Alert'. Move Canceled.");
+        // The end...
+        while (true) {
+            continue;
+        }
+    }
+
+    // Commands a speed of 5000 pulses/sec towards the hardstop for 2 seconds
+    SerialPort.SendLine("Moving toward hardstop... Waiting for HLFB");
+    motor.MoveVelocity(5000);
+    Delay_ms(2000);
+    // Then slows down to 1000 pulses/sec until clamping into the hard stop
+    motor.MoveVelocity(1000);
+	
+	// Check if an alert occurred during motion
+    if (motor.StatusReg().bit.AlertsPresent) {
+        // In this case, we can't proceed with homing. Print the alert and bail.
+        SerialPort.SendLine("Motor alert occurred during motion. Homing canceled.");
+        // The end...
+        while (true) {
+            continue;
+        }
+    }	
+
+
+    // Delay so HLFB has time to deassert
+    Delay_ms(10);
+    // Waits for HLFB to assert again, meaning the hardstop has been reached
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        if (motor.StatusReg().bit.AlertsPresent) {
+			// In this case, we can't proceed with homing. Print the alert and bail.
+			SerialPort.SendLine("Motor alert detected. Homing canceled.");
+			// The end...
+			while (true) {
+				continue;
+			}
+		}
+    }
+
+    // Stop the velocity move now that the hardstop is reached
+    motor.MoveStopAbrupt();
+
+    // Move away from the hard stop. Any move away from the hardstop will
+    // conclude the homing sequence.
+    motor.Move(-1000);
+
+    // Delay so HLFB has time to deassert
+    Delay_ms(10);
+    // Waits for HLFB to assert, meaning homing is complete
+    SerialPort.SendLine("Moving away from hardstop... Waiting for HLFB");
+    while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+	
+	// Check if an alert occurred during offset move
+    if (motor.StatusReg().bit.AlertsPresent) {
+        // In this case, we can't proceed with homing. Print the alert and bail.
+        SerialPort.SendLine("Motor alert occurred during offset move. Homing canceled.");
+        // The end...
+        while (true) {
+            continue;
+        }
+    } else {
+		SerialPort.SendLine("Homing Complete. Motor Ready.");
+	}
+    // Zero the motor's reference position after homing to allow for accurate
+    // absolute position moves
+    motor.PositionRefSet(0);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cppproj
new file mode 100644
index 000000000..e23b46954
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cppproj
@@ -0,0 +1,279 @@
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+    <Name>UserSeeksHome</Name>
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+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cpp
new file mode 100644
index 000000000..fa9451631
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cpp
@@ -0,0 +1,96 @@
+/*
+ * Title: AsgWithMeasuredTorque
+ *
+ * Objective:
+ *    This example demonstrates how to configure and read the High-Level
+ *    Feedback output mode "ASG-Position with Measured Torque" or "ASG-Velocity
+ *    with Measured Torque" from a ClearPath motor.
+ *
+ *    Note: There are two different versions of the ASG with Measured Torque
+ *    HLFB mode, one for Position modes and one for Velocity modes. See the
+ *    ClearPath MC/SD manual for a full description of all HLFB modes.
+ *
+ * Description:
+ *    This example reads the state of an attached ClearPath motor's HLFB output
+ *    in All Systems Go with Measured Torque mode. During operation, the state
+ *    of the HLFB is written to the USB serial port.
+ *
+ *    This example does not enable the motor or command any motion. Use the
+ *    Motion Generator in MSP to easily exercise the full features of this
+ *    example and see HLFB change state and give a torque measurement.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2. To command motion, the connected ClearPath motor must be configured for
+ *    the Motion Generator mode through the MSP software (In MSP select Mode>>
+ *    Motion Generator).
+ * 3. The connected ClearPath motor must have its HLFB mode set to ASG with
+ *    measured torque through the MSP software (select Advanced>>High Level
+ *    Feedback [Mode]... then choose "ASG-Position, w/Measured Torque" or
+ *    "ASG-Velocity, w/ Measured Torque" and hit the OK button).
+ *    Select a 482 Hz PWM Carrier Frequency in this menu.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+int main() {
+    // Put the motor connector into the HLFB mode to read bipolar PWM (the
+    // correct mode for ASG w/ Measured Torque)
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set up serial communication and wait up to 5 seconds for a port to open
+    // HLFB states are written to the serial port
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        SerialPort.Send("HLFB state: ");
+
+        // Check the current state of the ClearPath's HLFB.
+        MotorDriver::HlfbStates hlfbState = motor.HlfbState();
+
+        // Write the HLFB state to the serial port
+        if (hlfbState == MotorDriver::HLFB_HAS_MEASUREMENT) {
+            // Writes the torque measured, as a percent of motor peak torque rating
+            SerialPort.Send(int8_t(round(motor.HlfbPercent())));
+            SerialPort.SendLine("% torque");
+        }
+        else if (hlfbState == MotorDriver::HLFB_ASSERTED) {
+            // Asserted indicates either "Move Done" for position modes, or
+            // "At Target Velocity" for velocity moves
+            SerialPort.SendLine("ASSERTED");
+        }
+        else {
+            SerialPort.SendLine("DISABLED or SHUTDOWN");
+        }
+
+        // Wait before reading HLFB again
+        Delay_ms(500);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cppproj
new file mode 100644
index 000000000..e9adfc37f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{67623477-9c59-4f5b-8468-4e0d0f0fb6ce}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>AsgWithMeasuredTorque</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
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+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
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+    </AsfFrameworkConfig>
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+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
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+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
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+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
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+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
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+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
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+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
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+          <ListValues>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
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+          </ListValues>
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+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
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+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
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+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../../libClearCore/inc</Value>
+            <Value>../../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../../LwIP/LwIP/port/include</Value>
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+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
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+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
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+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="AsgWithMeasuredTorque.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/High-Level_Feedback_HLFB_Examples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/High-Level_Feedback_HLFB_Examples.atsln
new file mode 100644
index 000000000..59473e66d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/High-Level_Feedback_HLFB_Examples.atsln
@@ -0,0 +1,53 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "SpeedOutput", "SpeedOutput\SpeedOutput.cppproj", "{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}"
+	ProjectSection(ProjectDependencies) = postProject
+		{C373696C-5D45-4B91-AD62-A21552361596} = {C373696C-5D45-4B91-AD62-A21552361596}
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088} = {2530D5B1-8A40-4A55-95CA-2EC0B63E2088}
+	EndProjectSection
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "AsgWithMeasuredTorque", "AsgWithMeasuredTorque\AsgWithMeasuredTorque.cppproj", "{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+		Test|ARM = Test|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}.Debug|ARM.Build.0 = Debug|ARM
+		{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}.Release|ARM.ActiveCfg = Release|ARM
+		{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}.Release|ARM.Build.0 = Release|ARM
+		{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}.Test|ARM.ActiveCfg = Release|ARM
+		{2B9BCDB3-E27A-481B-8C46-225B4B2FD14E}.Test|ARM.Build.0 = Release|ARM
+		{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}.Debug|ARM.ActiveCfg = Debug|ARM
+		{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}.Debug|ARM.Build.0 = Debug|ARM
+		{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}.Release|ARM.ActiveCfg = Release|ARM
+		{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}.Release|ARM.Build.0 = Release|ARM
+		{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}.Test|ARM.ActiveCfg = Release|ARM
+		{67623477-9C59-4F5B-8468-4E0D0F0FB6CE}.Test|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Test|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Test|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Test|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Test|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cpp
new file mode 100644
index 000000000..f39e14446
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cpp
@@ -0,0 +1,100 @@
+/*
+ * Title: SpeedOutput
+ *
+ * Objective:
+ *    This example demonstrates how to configure and read-in the High-Level
+ *    Feedback mode "Speed Output" of a ClearPath motor.
+ *
+ *    This HLFB mode is available in ClearPath-MC series servos, in every
+ *    ClearPath-MC operational mode except Ramp Up/Down to Selected Velocity.
+ *
+ * Description:
+ *    This example reads the state of an attached ClearPath motor's HLFB output
+ *    when configured for "Speed Output". During operation, the state of HLFB
+ *    and calculated measured speed are written to the USB serial port.
+ *
+ *    This example does not enable the motor or command motion. Use the
+ *    "Override Inputs" feature in MSP to command motion and see changes in the
+ *    HLFB measurement.
+ *
+ * Requirements:
+ * 1. A ClearPath motor must be connected to Connector M-0.
+ * 2.  The connected ClearPath motor must be configured through the MSP software
+ *    for an operational mode compatible with Speed Output HLFB mode (see above)
+ * 3. The connected ClearPath motor must have its HLFB mode set to "Speed Output"
+ *    (select Advanced>>High Level Feedback [Mode]... then choose "Speed Output"
+ *    from the dropdown and hit the OK button).
+ *    Select a 482 Hz PWM Carrier Frequency in this menu.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+int main() {
+    // Put the motor connector into the correct HLFB mode to read the Speed
+    // Output PWM signal and convert it to percent of Max Speed.
+    motor.HlfbMode(MotorDriver::HLFB_MODE_HAS_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    motor.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set up serial communication at a baud rate of baudRate (9600 bps) then
+    // wait up to 5 seconds for a port to open.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        // Use the MSP application to enable and move the motor. The duty cycle of
+        // the HFLB output will be refreshed and displayed every 0.5 seconds.
+
+        // Check the state of the HLFB.
+        MotorDriver::HlfbStates hlfbState = motor.HlfbState();
+
+        // Print the HLFB state.
+        if (hlfbState == MotorDriver::HLFB_HAS_MEASUREMENT) {
+            // Get the measured speed as a percent of Max Speed.
+            float hlfbPercent = motor.HlfbPercent();
+
+            SerialPort.Send("Speed output: ");
+
+            if (hlfbPercent == MotorDriver::HLFB_DUTY_UNKNOWN) {
+                SerialPort.SendLine("UNKNOWN");
+            }
+            else {
+                char hlfbPercentStr[10];
+                // Convert the floating point duty cycle into a string representation.
+                snprintf(hlfbPercentStr, sizeof(hlfbPercentStr), "%.0f%%", hlfbPercent);
+                SerialPort.Send(hlfbPercentStr);
+                SerialPort.SendLine(" of maximum speed");
+            }
+        }
+        else if (hlfbState == MotorDriver::HLFB_DEASSERTED) {
+            SerialPort.SendLine("Disabled or Shutdown");
+        }
+
+        // Wait 0.5 secs before reading the HLFB again.
+        Delay_ms(500);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cppproj
new file mode 100644
index 000000000..1622bc129
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{2b9bcdb3-e27a-481b-8c46-225b4b2fd14e}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>SpeedOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../../libClearCore/inc</Value>
+            <Value>../../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="SpeedOutput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/DigitalIOExamples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/DigitalIOExamples.atsln
new file mode 100644
index 000000000..ca0c777d0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/DigitalIOExamples.atsln
@@ -0,0 +1,76 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "InputInterrupts", "InputInterrupts\InputInterrupts.cppproj", "{7A616192-7406-4B83-8A8E-E23636ADDD1A}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "PlayTone", "PlayTone\PlayTone.cppproj", "{B3DDBC7F-7604-44B7-ADB7-65C4DF6B70C9}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ReadDigitalInput", "ReadDigitalInput\ReadDigitalInput.cppproj", "{BE495490-B70F-4B25-8076-5356DB0087B5}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ReadDigitalInputRiseFall", "ReadDigitalInputRiseFall\ReadDigitalInputRiseFall.cppproj", "{E1663362-F31D-45B2-86F4-FBCC4DFDEC0E}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WriteDigitalOutput", "WriteDigitalOutput\WriteDigitalOutput.cppproj", "{1EE9571F-30C5-47AA-A260-EEC0F0C4B672}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WriteHBridgeOutput", "WriteHBridgeOutput\WriteHBridgeOutput.cppproj", "{3FE5E45E-D672-47BC-BD99-6843C006B002}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WritePwmOutput", "WritePwmOutput\WritePwmOutput.cppproj", "{B8C6043B-49F1-43EB-9F30-E8C131F0B59F}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "PeriodicInterrupt", "PeriodicInterrupt\PeriodicInterrupt.cppproj", "{BC799FB3-5751-404E-9AC3-1F78CEC17147}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Debug|ARM.ActiveCfg = Debug|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Debug|ARM.Build.0 = Debug|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Release|ARM.ActiveCfg = Release|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Release|ARM.Build.0 = Release|ARM
+		{B3DDBC7F-7604-44B7-ADB7-65C4DF6B70C9}.Debug|ARM.ActiveCfg = Debug|ARM
+		{B3DDBC7F-7604-44B7-ADB7-65C4DF6B70C9}.Debug|ARM.Build.0 = Debug|ARM
+		{B3DDBC7F-7604-44B7-ADB7-65C4DF6B70C9}.Release|ARM.ActiveCfg = Release|ARM
+		{B3DDBC7F-7604-44B7-ADB7-65C4DF6B70C9}.Release|ARM.Build.0 = Release|ARM
+		{BE495490-B70F-4B25-8076-5356DB0087B5}.Debug|ARM.ActiveCfg = Debug|ARM
+		{BE495490-B70F-4B25-8076-5356DB0087B5}.Debug|ARM.Build.0 = Debug|ARM
+		{BE495490-B70F-4B25-8076-5356DB0087B5}.Release|ARM.ActiveCfg = Release|ARM
+		{BE495490-B70F-4B25-8076-5356DB0087B5}.Release|ARM.Build.0 = Release|ARM
+		{E1663362-F31D-45B2-86F4-FBCC4DFDEC0E}.Debug|ARM.ActiveCfg = Debug|ARM
+		{E1663362-F31D-45B2-86F4-FBCC4DFDEC0E}.Debug|ARM.Build.0 = Debug|ARM
+		{E1663362-F31D-45B2-86F4-FBCC4DFDEC0E}.Release|ARM.ActiveCfg = Release|ARM
+		{E1663362-F31D-45B2-86F4-FBCC4DFDEC0E}.Release|ARM.Build.0 = Release|ARM
+		{1EE9571F-30C5-47AA-A260-EEC0F0C4B672}.Debug|ARM.ActiveCfg = Debug|ARM
+		{1EE9571F-30C5-47AA-A260-EEC0F0C4B672}.Debug|ARM.Build.0 = Debug|ARM
+		{1EE9571F-30C5-47AA-A260-EEC0F0C4B672}.Release|ARM.ActiveCfg = Release|ARM
+		{1EE9571F-30C5-47AA-A260-EEC0F0C4B672}.Release|ARM.Build.0 = Release|ARM
+		{3FE5E45E-D672-47BC-BD99-6843C006B002}.Debug|ARM.ActiveCfg = Debug|ARM
+		{3FE5E45E-D672-47BC-BD99-6843C006B002}.Debug|ARM.Build.0 = Debug|ARM
+		{3FE5E45E-D672-47BC-BD99-6843C006B002}.Release|ARM.ActiveCfg = Release|ARM
+		{3FE5E45E-D672-47BC-BD99-6843C006B002}.Release|ARM.Build.0 = Release|ARM
+		{B8C6043B-49F1-43EB-9F30-E8C131F0B59F}.Debug|ARM.ActiveCfg = Debug|ARM
+		{B8C6043B-49F1-43EB-9F30-E8C131F0B59F}.Debug|ARM.Build.0 = Debug|ARM
+		{B8C6043B-49F1-43EB-9F30-E8C131F0B59F}.Release|ARM.ActiveCfg = Release|ARM
+		{B8C6043B-49F1-43EB-9F30-E8C131F0B59F}.Release|ARM.Build.0 = Release|ARM
+		{BC799FB3-5751-404E-9AC3-1F78CEC17147}.Debug|ARM.ActiveCfg = Debug|ARM
+		{BC799FB3-5751-404E-9AC3-1F78CEC17147}.Debug|ARM.Build.0 = Debug|ARM
+		{BC799FB3-5751-404E-9AC3-1F78CEC17147}.Release|ARM.ActiveCfg = Release|ARM
+		{BC799FB3-5751-404E-9AC3-1F78CEC17147}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/InputInterrupts/InputInterrupts.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/InputInterrupts/InputInterrupts.cpp
new file mode 100644
index 000000000..1e728cd3a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/InputInterrupts/InputInterrupts.cpp
@@ -0,0 +1,115 @@
+/*
+ * Title: InputInterrupts
+ *
+ * Objective:
+ *    This example demonstrates how to configure a digital interrupt on a
+ *    ClearCore input.
+ *
+ * Description:
+ *    This example sets up and attaches a callback function to be triggered by
+ *    a digital interrupt. Interrupts are useful when a function needs to be
+ *    called asynchronously from the rest of the code's execution.
+ *
+ *    This example's interrupt blinks the on-board user LED when the interrupt
+ *    pin goes from on to off (aka "falling"). You may notice multiple blinks
+ *    depending on how much bounce the input device has.
+ *
+ *    The interrupt callback function's ability to run is turned on and off
+ *    periodically by this example. The callback function can only run when
+ *    interrupts are turned "on", regardless of the interrupt pin state. If the
+ *    interrupt pin is triggered while interrupts are "off", the callback will
+ *    execute when interrupts are next turned on. This on/off state is printed
+ *    to the USB serial port.
+ *
+ * Requirements:
+ * ** A digital signal source, such as a switch or sensor, connected to DI-6 to
+ *    trigger the interrupt
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Connectors that support digital interrupts are:
+// DI-6, DI-7, DI-8, A-9, A-10, A-11, A-12
+#define interruptConnector ConnectorDI6
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify the serial connector to use: ConnectorUsb, ConnectorCOM0, or
+// ConnectorCOM1
+#define SerialPort ConnectorUsb
+
+// Declare the signature for our interrupt service routine (ISR). The function
+// is defined below
+void MyCallback();
+
+int main() {
+    // Set up the interrupt connector in digital input mode.
+    interruptConnector.Mode(Connector::INPUT_DIGITAL);
+
+    // Set an ISR to be called when the state of the interrupt pin goes from
+    // true to false.
+    interruptConnector.InterruptHandlerSet(MyCallback, InputManager::FALLING,
+                                           false);
+
+    // Set up serial communication and wait up to 5 seconds for a port to open
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        // Enable digital interrupts.
+        interruptConnector.InterruptEnable(true);
+
+        SerialPort.SendLine("Interrupts are turned on.");
+
+        // Test that the ISR is triggered when the state of the interrupt connector
+        // transitions from true to false by toggling your switch.
+
+        // Wait while the interrupt is triggered.
+        Delay_ms(5000);
+
+        // Disable digital interrupts.
+        interruptConnector.InterruptEnable(false);
+
+        SerialPort.SendLine("Interrupts are turned off.");
+
+        // Test that the ISR does not get triggered when the state of the interrupt
+        // connector transitions from true to false by toggling your switch.
+        Delay_ms(5000);
+    }
+}
+
+// The function to be triggered on an interrupt.
+// This function blinks the user-controlled LED once.
+/*------------------------------------------------------------------------------
+ * MyCallback
+ *
+ *    Flashes the ClearCore's built-in LED (next to the USB port) on and off.
+ *
+ * Parameters:
+ *    None
+ *
+ * Returns: None
+ */
+void MyCallback() {
+    ConnectorLed.State(true);
+    Delay_ms(100);
+    ConnectorLed.State(false);
+    Delay_ms(100);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/InputInterrupts/InputInterrupts.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/InputInterrupts/InputInterrupts.cppproj
new file mode 100644
index 000000000..3cc43da41
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/InputInterrupts/InputInterrupts.cppproj
@@ -0,0 +1,282 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="InputInterrupts.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
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+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cpp
new file mode 100644
index 000000000..907db35f4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cpp
@@ -0,0 +1,139 @@
+/*
+ * PeriodicInterrupt
+ * Configure a user-defined periodic interrupt.
+ */
+ /*
+ * Title: PeriodicInterrupt
+ *
+ * Objective:
+ *    This example demonstrates how to generate a user defined periodic
+ * interrupt.
+ *
+ * Description:
+ *    This example configures a periodic interrupt handler that turns the
+ * user LED on and off during each call to the interrupt. Once configured,
+ * The interrupt will execute at the requested frequency without having to
+ * be called from the main program.
+ *
+ * Requirements:
+ * ** None
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 6/11/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+/**
+    \brief Start a periodic interrupt
+
+    Configures the TCC2 clock prescaler and period to generate an interrupt
+    at the requested frequency. If the requested frequency is zero, the
+    interrupt will not be configured. TCC2 is not used by any ClearCore
+    hardware or core libraries.
+
+    \param [in] frequencyHz The rate which the interrupt should occur.
+**/
+void ConfigurePeriodicInterrupt(uint32_t frequencyHz);
+
+/// Make an alias for the ISR handler so that the user code does not need
+/// to know which IRQ it is being fired from
+extern "C" void TCC2_0_Handler(void) __attribute__((
+            alias("PeriodicInterrupt")));
+
+// Periodic interrupt priority
+// 0 is highest priority, 7 is lowest priority
+// Recommended priority is >= 4 to not interfere with other processing
+#define PERIODIC_INTERRUPT_PRIORITY     4
+#define ACK_PERIODIC_INTERRUPT  TCC2->INTFLAG.reg = TCC_INTFLAG_MASK
+
+// State currently written to LED_BUILTIN
+bool ledState = false;
+uint32_t interruptFreqHz = 4;
+
+/**
+    \brief The periodic interrupt handler
+
+    This is the function where your code to periodically execute should live.
+
+    \note ACK_PERIODIC_INTERRUPT must be called to clear the interrupt.
+**/
+extern "C" void PeriodicInterrupt(void) {
+    // Perform periodic processing here.
+    ledState = !ledState;
+    ConnectorLed.State(ledState);
+
+    // Acknowledge the interrupt to clear the flag and wait for the next interrupt.
+    ACK_PERIODIC_INTERRUPT;
+}
+
+int main() {
+    ConfigurePeriodicInterrupt(interruptFreqHz);
+}
+
+void ConfigurePeriodicInterrupt(uint32_t frequencyHz) {
+    // Enable the TCC2 peripheral.
+    // TCC2 and TCC3 share their clock configuration and they
+    // are already configured to be clocked at 120 MHz from GCLK0.
+    CLOCK_ENABLE(APBCMASK, TCC2_);
+
+    // Disable TCC2.
+    TCC2->CTRLA.bit.ENABLE = 0;
+    SYNCBUSY_WAIT(TCC2, TCC_SYNCBUSY_ENABLE);
+
+    // Reset the TCC module so we know we are starting from a clean state.
+    TCC2->CTRLA.bit.SWRST = 1;
+    while (TCC2->CTRLA.bit.SWRST) {
+        continue;
+    }
+
+    // If the frequency requested is zero, disable the interrupt and bail out.
+    if (!frequencyHz) {
+        NVIC_DisableIRQ(TCC2_0_IRQn);
+        return;
+    }
+
+    // Determine the clock prescaler and period value needed to achieve the
+    // requested frequency.
+    uint32_t period = (CPU_CLK + frequencyHz / 2) / frequencyHz;
+    uint8_t prescale;
+    // Make sure period is >= 1.
+    period = max(period, 1U);
+
+    // Prescale values 0-4 map to prescale divisors of 1-16,
+    // dividing by 2 each increment.
+    for (prescale = TCC_CTRLA_PRESCALER_DIV1_Val;
+            prescale < TCC_CTRLA_PRESCALER_DIV16_Val && (period - 1) > UINT16_MAX;
+            prescale++) {
+        period = period >> 1;
+    }
+    // Prescale values 5-7 map to prescale divisors of 64-1024,
+    // dividing by 4 each increment.
+    for (; prescale < TCC_CTRLA_PRESCALER_DIV1024_Val && (period - 1) > UINT16_MAX;
+            prescale++) {
+        period = period >> 2;
+    }
+    // If we have maxed out the prescaler and the period is still too big,
+    // use the maximum period. This results in a ~1.788 Hz interrupt.
+    if (period > UINT16_MAX) {
+        TCC2->PER.reg = UINT16_MAX;
+    }
+    else {
+        TCC2->PER.reg = period - 1;
+    }
+    TCC2->CTRLA.bit.PRESCALER = prescale;
+
+    // Interrupt every period on counter overflow.
+    TCC2->INTENSET.bit.OVF = 1;
+    // Enable TCC2.
+    TCC2->CTRLA.bit.ENABLE = 1;
+
+    // Set the interrupt priority and enable it.
+    NVIC_SetPriority(TCC2_0_IRQn, PERIODIC_INTERRUPT_PRIORITY);
+    NVIC_EnableIRQ(TCC2_0_IRQn);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cppproj
new file mode 100644
index 000000000..08656dfef
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
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+    <Name>PeriodicInterrupt</Name>
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+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/PlayTone.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/PlayTone.cpp
new file mode 100644
index 000000000..25b40b68e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/PlayTone.cpp
@@ -0,0 +1,66 @@
+/*
+ * Title: PlayTone
+ *
+ * Objective:
+ *    This example demonstrates how to play a sequence of tones on the
+ *    ClearCore's H-Bridge connectors using the musical frequency values defined
+ *    in the pitches.h header file.
+ *
+ * Description:
+ *    This example sets up an H-Bridge connector into output mode, sets the
+ *    volume, and plays a melodic sequence of tones of equal duration.
+ *
+ * Requirements:
+ * ** A speaker or other audio output device connected to IO-4
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+#include "pitches.h"
+
+// Notes to be played in sequence as part of a melody.
+// The maximum tone frequency is 1/4 of the tone interrupt rate, i.e. 5512 Hz.
+// Any commanded frequency above 5512 Hz will get clipped to 5512 Hz.
+// See the "pitches.h" file for the frequency definitions of these notes.
+const uint16_t melody[] = {NOTE_C4, NOTE_E4, NOTE_G4, NOTE_C5,
+                           NOTE_CS4, NOTE_FS4, NOTE_AS4, NOTE_CS5,
+                           NOTE_E4, NOTE_G4, NOTE_C5, NOTE_E5,
+                           NOTE_FS4, NOTE_AS4, NOTE_CS5, NOTE_FS5
+                          };
+const uint32_t noteCount = sizeof(melody) / sizeof(melody[0]);
+
+const uint32_t toneDuration = 200;              // in milliseconds
+const int16_t toneAmplitude = INT16_MAX / 100;  // max volume is INT16_MAX
+
+// Tone output is supported on connectors IO-4 and IO-5 only.
+#define tonePin ConnectorIO4
+
+int main() {
+    // Set the tone connector into output mode.
+    tonePin.Mode(Connector::OUTPUT_TONE);
+
+    // Set the volume of the tone connector to the value specified
+    // by toneAmplitude.
+    tonePin.ToneAmplitude(toneAmplitude);
+
+    while (true) {
+        // Play the melody in order with equal note durations.
+        for (uint8_t note = 0; note < noteCount; note++) {
+            tonePin.ToneContinuous(melody[note]);
+            Delay_ms(toneDuration);
+        }
+
+        // Stop the tone generation.
+        tonePin.ToneStop();
+
+        // Wait a second, then repeat...
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/PlayTone.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/PlayTone.cppproj
new file mode 100644
index 000000000..c6cf6748a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/PlayTone.cppproj
@@ -0,0 +1,282 @@
+<?xml version="1.0" encoding="utf-8"?>
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+    <Name>PlayTone</Name>
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+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
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+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
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+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
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+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
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+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
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+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
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+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
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+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="pitches.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="PlayTone.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/pitches.h b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/pitches.h
new file mode 100644
index 000000000..9f16b4d6c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/PlayTone/pitches.h
@@ -0,0 +1,93 @@
+/*************************************************
+ * Public Constants
+ *************************************************/
+
+#define NOTE_B0  31
+#define NOTE_C1  33
+#define NOTE_CS1 35
+#define NOTE_D1  37
+#define NOTE_DS1 39
+#define NOTE_E1  41
+#define NOTE_F1  44
+#define NOTE_FS1 46
+#define NOTE_G1  49
+#define NOTE_GS1 52
+#define NOTE_A1  55
+#define NOTE_AS1 58
+#define NOTE_B1  62
+#define NOTE_C2  65
+#define NOTE_CS2 69
+#define NOTE_D2  73
+#define NOTE_DS2 78
+#define NOTE_E2  82
+#define NOTE_F2  87
+#define NOTE_FS2 93
+#define NOTE_G2  98
+#define NOTE_GS2 104
+#define NOTE_A2  110
+#define NOTE_AS2 117
+#define NOTE_B2  123
+#define NOTE_C3  131
+#define NOTE_CS3 139
+#define NOTE_D3  147
+#define NOTE_DS3 156
+#define NOTE_E3  165
+#define NOTE_F3  175
+#define NOTE_FS3 185
+#define NOTE_G3  196
+#define NOTE_GS3 208
+#define NOTE_A3  220
+#define NOTE_AS3 233
+#define NOTE_B3  247
+#define NOTE_C4  262
+#define NOTE_CS4 277
+#define NOTE_D4  294
+#define NOTE_DS4 311
+#define NOTE_E4  330
+#define NOTE_F4  349
+#define NOTE_FS4 370
+#define NOTE_G4  392
+#define NOTE_GS4 415
+#define NOTE_A4  440
+#define NOTE_AS4 466
+#define NOTE_B4  494
+#define NOTE_C5  523
+#define NOTE_CS5 554
+#define NOTE_D5  587
+#define NOTE_DS5 622
+#define NOTE_E5  659
+#define NOTE_F5  698
+#define NOTE_FS5 740
+#define NOTE_G5  784
+#define NOTE_GS5 831
+#define NOTE_A5  880
+#define NOTE_AS5 932
+#define NOTE_B5  988
+#define NOTE_C6  1047
+#define NOTE_CS6 1109
+#define NOTE_D6  1175
+#define NOTE_DS6 1245
+#define NOTE_E6  1319
+#define NOTE_F6  1397
+#define NOTE_FS6 1480
+#define NOTE_G6  1568
+#define NOTE_GS6 1661
+#define NOTE_A6  1760
+#define NOTE_AS6 1865
+#define NOTE_B6  1976
+#define NOTE_C7  2093
+#define NOTE_CS7 2217
+#define NOTE_D7  2349
+#define NOTE_DS7 2489
+#define NOTE_E7  2637
+#define NOTE_F7  2794
+#define NOTE_FS7 2960
+#define NOTE_G7  3136
+#define NOTE_GS7 3322
+#define NOTE_A7  3520
+#define NOTE_AS7 3729
+#define NOTE_B7  3951
+#define NOTE_C8  4186
+#define NOTE_CS8 4435
+#define NOTE_D8  4699
+#define NOTE_DS8 4978
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cpp
new file mode 100644
index 000000000..615e5a503
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cpp
@@ -0,0 +1,72 @@
+/*
+ * Title: ReadDigitalInput
+ *
+ * Objective:
+ *    This example demonstrates how to read the state of a ClearCore digital
+ *    input.
+ *
+ * Description:
+ *    This example repeatedly reads the state of a defined digital input. During
+ *    operation, the state of the input is printed to the USB serial port.
+ *
+ * Requirements:
+ * ** A digital input device, such as a switch or sensor, connected to DI-6
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which input pin to read from.
+// IO-0 through A-12 are all available as digital inputs.
+#define inputPin ConnectorDI6
+
+// The current state of the input pin
+int16_t state;
+
+// Select the baud rate to match the target serial device.
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+int main() {
+
+	inputPin.Mode(Connector::INPUT_DIGITAL);  //Set the input as a digital Input
+
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        // Read the state of the input connector.
+        state = inputPin.State();
+
+        // Display the state of the input connector.
+        SerialPort.Send("DI-6 Input state: ");
+        if (state) {
+            SerialPort.SendLine("ON");
+        }
+        else {
+            SerialPort.SendLine("OFF");
+        }
+
+        // Wait a second then repeat...
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cppproj
new file mode 100644
index 000000000..47c45385d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
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+    <ProjectGuid>{be495490-b70f-4b25-8076-5356db0087b5}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>ReadDigitalInput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
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+      <framework-data>
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+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
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+    <custom>
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+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
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+      <ToolName xmlns="">Custom Programming Tool</ToolName>
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+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
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+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
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+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
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+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
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+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
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+        </armgcccpp.compiler.symbols.DefSymbols>
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+        </armgcccpp.preprocessingassembler.general.IncludePaths>
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ReadDigitalInput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
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+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cpp
new file mode 100644
index 000000000..1de18f336
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cpp
@@ -0,0 +1,82 @@
+/*
+ * Title: ReadDigitalInputRiseFall
+ *
+ * Objective:
+ *    This example demonstrates how to read the transition state (risen or
+ *    fallen since last checked) of a ClearCore digital input.
+ *
+ * Description:
+ *    This example repeatedly reads the transition state of a defined digital
+ *    input. Information on how the input state has transitioned is printed
+ *    to the USB serial port every 2 seconds.
+ *
+ * Requirements:
+ * ** An input device, such as a switch or sensor, connected to DI-6.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which input connector to use.
+// ConnectorIO0 through ConnectorA12 all have digital input capability.
+#define InputConnector ConnectorDI6
+
+// Declares two boolean variables used to hold information on whether the input
+// has risen or fallen
+bool risen, fallen;
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+int main() {
+
+	InputConnector.Mode(Connector::INPUT_DIGITAL);  //Set the input as a digital Input
+
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    while (true) {
+        // Check whether the digital input has risen, fallen, or is unchanged
+        // since the last time we checked.
+        risen = InputConnector.InputRisen();
+        fallen = InputConnector.InputFallen();
+
+        SerialPort.Send("DI-6 Transitions: ");
+
+        if (risen && fallen) {
+            SerialPort.SendLine("RISEN and FALLEN");
+        }
+        else if (risen) {
+            SerialPort.SendLine("RISEN");
+        }
+        else if (fallen) {
+            SerialPort.SendLine("FALLEN");
+        }
+        else {
+            SerialPort.SendLine("NO CHANGE");
+        }
+
+        // Wait a couple seconds then repeat...
+        Delay_ms(2000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cppproj
new file mode 100644
index 000000000..7f2883835
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cppproj
@@ -0,0 +1,279 @@
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+  <offline-documentation help="" />
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+        <InterfaceName>SWD</InterfaceName>
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+      <ToolNumber xmlns="">
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+            <Value>../../../../LwIP/LwIP/src/include</Value>
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+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
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+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ReadDigitalInputRiseFall.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
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+  <ItemGroup>
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+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cpp
new file mode 100644
index 000000000..8398c8377
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cpp
@@ -0,0 +1,71 @@
+/*
+ * Title: WriteDigitalOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write the state of a ClearCore digital
+ *    output.
+ *
+ * Description:
+ *    This example repeatedly toggles the state of the ClearCore's six digital
+ *    outputs, IO-0 through IO-5.
+ *
+ * Requirements:
+ * ** A device that takes in a digital signal connected to any of the I/O's,
+ *    IO-0 through IO-5.
+ *      Note: You can leave the I/O points disconnected and still see the
+ *      built-in I/O LEDs toggle with the connector state.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Declares a variable used to write new states to the output. We will toggle
+// this true/false.
+bool outputState;
+
+int main() {
+    // Configure pins IO-0 through IO-5 as digital outputs. These are the only
+    // pins that support digital output mode.
+    ConnectorIO0.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO1.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO2.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO3.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO4.Mode(Connector::OUTPUT_DIGITAL);
+    ConnectorIO5.Mode(Connector::OUTPUT_DIGITAL);
+
+    // The connectors are all set up; start the loop with turning them all on.
+    outputState = true;
+
+    while (true) {
+        // Toggle the digital output state.
+        if (outputState) {
+            ConnectorIO0.State(true);
+            ConnectorIO1.State(true);
+            ConnectorIO2.State(true);
+            ConnectorIO3.State(true);
+            ConnectorIO4.State(true);
+            ConnectorIO5.State(true);
+        }
+        else {
+            ConnectorIO0.State(false);
+            ConnectorIO1.State(false);
+            ConnectorIO2.State(false);
+            ConnectorIO3.State(false);
+            ConnectorIO4.State(false);
+            ConnectorIO5.State(false);
+        }
+
+        // Toggle the state to write in the next loop.
+        outputState = !outputState;
+
+        // Wait a second, then repeat.
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cppproj
new file mode 100644
index 000000000..a57f58963
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
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+    <Name>WriteDigitalOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
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+    <EraseKey />
+    <AsfFrameworkConfig>
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+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
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+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
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+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
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+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cpp
new file mode 100644
index 000000000..b004b4b73
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cpp
@@ -0,0 +1,101 @@
+/*
+ * Title: WriteHBridgeOutput
+ *
+ * Objective:
+ *    This example demonstrates how to output a differential/bi-directional PWM
+ *    signal from a ClearCore H-Bridge connector.
+ *
+ * Description:
+ *    This example sets up a ClearCore H-Bridge connector for H-Bridge output,
+ *    then repeatedly ramps the PWM duty cycle output up and down, both sourcing
+ *    and sinking current.
+ *
+ * Requirements:
+ * ** A device capable of receiving an H-Bridge bi-directional PWM signal, like
+ *    a bi-directional brushed DC motor, connected to IO-4. Refer to the
+ *    ClearCore System Diagram on how to wire a device to the H-Bridge capable
+ *    connectors.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Defines which H-Bridge capable connector to use: ConnectorIO4 or ConnectorIO5
+#define HBridgeConnector ConnectorIO4
+
+// Declares our user-defined helper function, which is used to check for
+// overloads and reset the H-Bridge output as necessary. The definition/
+// implementation of this function is at the bottom of the example.
+void CheckHBridgeOverload();
+
+int main() {
+    // H-Bridge output is supported on connectors IO-4 and IO-5 only.
+    // Set the H-Bridge connector into H-Bridge output mode.
+    HBridgeConnector.Mode(Connector::OUTPUT_H_BRIDGE);
+
+    while (true) {
+        // Output bi-directional PWM on the H-Bridge connector over the full range
+        // of output values/duty cycles (-INT16_MAX-1 to INT16_MAX).
+
+        // Positive values (between 1 and INT16_MAX) will sink current into the
+        // signal pin.
+        // Negative values (between -1 and -INT16_MAX-1) will source current
+        // from the signal pin.
+
+        for (int16_t i = 0; i < INT16_MAX; i++) {
+            // Check for overloads and reset if needed
+            CheckHBridgeOverload();
+
+            // Write to the output.
+            HBridgeConnector.State(i);
+            Delay_us(125);
+        }
+
+        for (int16_t i = 0; i < INT16_MAX; i++) {
+            CheckHBridgeOverload();
+
+            HBridgeConnector.State(INT16_MAX - i);
+            Delay_us(125);
+        }
+
+        for (int16_t i = 0; i < INT16_MAX; i++) {
+            CheckHBridgeOverload();
+
+            HBridgeConnector.State(-i);
+            Delay_us(125);
+        }
+
+        for (int16_t i = 0; i < INT16_MAX; i++) {
+            CheckHBridgeOverload();
+
+            HBridgeConnector.State(-INT16_MAX + i);
+            Delay_us(125);
+        }
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * CheckHBridgeOverload
+ *
+ *    Checks whether any of the ClearCore's H-Bridge connectors are experiencing
+ *    an overload. If an overload is detected the H-Bridge connectors are reset.
+ *
+ * Parameters:
+ *    None
+ *
+ * Returns: None
+ */
+void CheckHBridgeOverload() {
+    if (StatusMgr.StatusRT().bit.HBridgeOverloaded) {
+        StatusMgr.HBridgeReset();
+        Delay_ms(10);
+    }
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cppproj
new file mode 100644
index 000000000..ba71a6e16
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
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+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>WriteHBridgeOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
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+      <ToolName xmlns="">Custom Programming Tool</ToolName>
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+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
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+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
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+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
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+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
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+        <armgcccpp.compiler.symbols.DefSymbols>
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+        </armgcccpp.compiler.symbols.DefSymbols>
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+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
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+        </armgcccpp.compiler.directories.IncludePaths>
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+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
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+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
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+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
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+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
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+        <armgcccpp.compiler.directories.IncludePaths>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
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+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
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+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
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+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="WriteHBridgeOutput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WritePwmOutput/WritePwmOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WritePwmOutput/WritePwmOutput.cpp
new file mode 100644
index 000000000..3c082f052
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WritePwmOutput/WritePwmOutput.cpp
@@ -0,0 +1,53 @@
+/*
+ * Title: WritePwmOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write a digital PWM signal to a ClearCore
+ *    digital output.
+ *
+ * Description:
+ *    This example sets the defined pin as an output then writes a series of
+ *    PWM signals with varying duty cycles to the output.
+ *
+ * Requirements:
+ * ** Connect a device that takes in a PWM signal to IO-1.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specify which output pin to write digital PWM to.
+// PWM-capable pins: IO-0 through IO-5.
+// Note: IO-4 and IO-5 are capable of bi-directional and higher-current PWM
+//       output using an H-Bridge. See the WriteHBridgeOutput example.
+#define outputPin ConnectorIO1
+
+int main() {
+    // Set up the output pin for PWM output mode.
+    outputPin.Mode(Connector::OUTPUT_PWM);
+
+    while (true) {
+        // Write some digital PWM signals to the output connector.
+        // Valid values range from 0 (0% duty cycle / always off)
+        // to 255 (100% duty cycle / always on).
+
+        // Output a low duty cycle for 1 second.
+        outputPin.PwmDuty(10);
+        Delay_ms(1000);
+
+        // Output a medium duty cycle for 1 second.
+        outputPin.PwmDuty(120);
+        Delay_ms(1000);
+
+        // Output a high duty cycle for 1 second.
+        outputPin.PwmDuty(230);
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WritePwmOutput/WritePwmOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WritePwmOutput/WritePwmOutput.cppproj
new file mode 100644
index 000000000..c3a88061a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/DigitalIOExamples/WritePwmOutput/WritePwmOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
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+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
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+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>WritePwmOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="WritePwmOutput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/EncoderInputExamples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/EncoderInputExamples.atsln
new file mode 100644
index 000000000..4a3bc3171
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/EncoderInputExamples.atsln
@@ -0,0 +1,34 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.25420.1
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "FollowEncoder", "FollowEncoder\FollowEncoder.cppproj", "{7A616192-7406-4B83-8A8E-E23636ADDD1A}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Debug|ARM.ActiveCfg = Debug|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Debug|ARM.Build.0 = Debug|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Release|ARM.ActiveCfg = Release|ARM
+		{7A616192-7406-4B83-8A8E-E23636ADDD1A}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/FollowEncoder/FollowEncoder.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/FollowEncoder/FollowEncoder.cpp
new file mode 100644
index 000000000..0b25949f4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/FollowEncoder/FollowEncoder.cpp
@@ -0,0 +1,167 @@
+/*
+ * Title: FollowEncoder
+ *
+ * Objective:
+ *    This example demonstrates the ClearCore's Encoder Input module
+ *    functionality.
+ *
+ * Description:
+ *    This example takes input signals from an external encoder through the 
+ *    CL-ENCRD-DFIN Encoder Adapter Board, and uses the encoder position
+ *    or velocity to control a ClearPath-SD servo.
+ *
+ * Requirements:
+ * 1. A ClearPath-SD motor must be connected to Connector M-0.
+ * 2. The connected ClearPath motor must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 3. The ClearPath motor must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 4. Set the Input Format in MSP for "Step + Direction".
+ * 5. An external encoder much be wired to the CL-ENCRD-DFIN Encoder Adapter Board, 
+ *    and the board connected to the ClearCore I/O Header. See the ClearCore User 
+ *    Manaual for connector pinouts.
+ *
+ * ** Reminder: When using the CL-ENCRD-DFIN Encoder Adapter Board, ClearCore 
+ *    connectors DI-6, DI-7, and DI-8 are unavailable and should be left Not  
+ *    Connected to any external device.
+ *
+ * ** Note: Homing is optional and not required in this operational mode or in
+ *    this example.
+ *
+ * ** Note: Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power): https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power): https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+
+// Set the operational mode of this example:
+// If true, the motor will faithfully follow the encoder's position.
+// If false, the motor will faithfully follow the encoder's velocity instead.
+bool followPosition = false;
+
+// Define the velocity and acceleration limits to be used for positional moves
+int32_t velocityLimit = 100000; // pulses per sec
+int32_t accelerationLimit = 1000000; // pulses per sec^2
+
+// Set to true if the sense of encoder direction should be inverted.
+bool swapDirection = false;
+// Set to true if index detection should occur on the falling edge,
+// rather than the rising edge.
+bool indexInverted = false;
+
+int main(void) {
+    // Set up serial communication and wait up to 5 seconds for a port to open
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    ConnectorUsb.PortOpen();
+    while (!ConnectorUsb && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enable the encoder input feature
+    EncoderIn.Enable(true);
+    // Zero the position to start
+    EncoderIn.Position(0);
+    // Set the encoder direction
+    EncoderIn.SwapDirection(swapDirection);
+    // Set the sense of index detection (true = rising edge, false = falling edge)
+    EncoderIn.IndexInverted(indexInverted);
+
+    // Motor setup:
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL, Connector::CPM_MODE_STEP_AND_DIR);
+
+    // Set the motor's HLFB mode to bipolar PWM
+    ConnectorM0.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+    // Set the HFLB carrier frequency to 482 Hz
+    ConnectorM0.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+
+    // Set velocity and acceleration limits for each move
+    ConnectorM0.VelMax(velocityLimit);
+    ConnectorM0.AccelMax(accelerationLimit);
+
+    // Enables the motor; homing will begin automatically if enabled
+    ConnectorM0.EnableRequest(true);
+    ConnectorUsb.SendLine("Motor Enabled");
+
+    // Waits for HLFB to assert (waits for homing to complete if applicable)
+    ConnectorUsb.SendLine("Waiting for HLFB...");
+    while (ConnectorM0.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+        continue;
+    }
+    ConnectorUsb.SendLine("Motor Ready");
+
+    // Variables to store encoder state
+    int32_t position = 0;
+    int32_t velocity = 0;
+    int32_t indexPosition = 0;
+    int32_t lastIndexPosition = 0;
+    bool quadratureError = false;
+
+    // Use a timeout to print out encoder information every 500 ms.
+    char info[100];
+    timeout = 500;
+    startTime = Milliseconds();
+
+    while (!quadratureError) {
+        position = EncoderIn.Position();
+        velocity = EncoderIn.Velocity();
+        indexPosition = EncoderIn.IndexPosition();
+        quadratureError = EncoderIn.QuadratureError();
+
+        // Print out encoder info at a fixed timeout rate
+        if (Milliseconds() - startTime >= timeout) {
+            if (followPosition) {
+                snprintf(info, 100, "Encoder position: %ld counts", position);
+            }
+            else {
+                snprintf(info, 100, "Encoder velocity: %ld counts/sec", velocity);
+            }
+            ConnectorUsb.SendLine(info);
+            startTime = Milliseconds();
+        }
+
+        if (indexPosition != lastIndexPosition) {
+            snprintf(info, 100, "Detected index at position: %ld",
+            EncoderIn.IndexPosition());
+            ConnectorUsb.SendLine(info);
+        }
+
+        lastIndexPosition = indexPosition;
+
+        // Check if an alert is currently preventing motion
+        if (ConnectorM0.StatusReg().bit.AlertsPresent) {
+            ConnectorUsb.SendLine("Motor status: 'In Alert'. Move Canceled.");
+            continue;
+        }
+
+        if (followPosition) {
+            // Move the motor to the current position read by the encoder
+            ConnectorM0.Move(position, MotorDriver::MOVE_TARGET_ABSOLUTE);
+        }
+        else {
+            // Command the motor to follow the encoder's velocity
+            ConnectorM0.MoveVelocity(velocity);
+        }
+    }
+
+    // We detected a quadrature error!
+    ConnectorM0.MoveVelocity(0);
+    ConnectorM0.EnableRequest(false);
+    ConnectorUsb.SendLine("Quadrature error detected. Stopping motion...");
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/FollowEncoder/FollowEncoder.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/FollowEncoder/FollowEncoder.cppproj
new file mode 100644
index 000000000..5a5adf144
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EncoderInputExamples/FollowEncoder/FollowEncoder.cppproj
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{7a616192-7406-4b83-8a8e-e23636addd1a}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>InputInterrupts</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800082633</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>custom</ToolType>
+      <ToolNumber>
+      </ToolNumber>
+      <ToolName>Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>4000000</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="FollowEncoder.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetExamples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetExamples.atsln
new file mode 100644
index 000000000..65e7fc7c7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetExamples.atsln
@@ -0,0 +1,52 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "EthernetUdpHelloWorld", "EthernetUdpHelloWorld\EthernetUdpHelloWorld.cppproj", "{550B0E05-B621-4032-B7A8-3A17D156FC44}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "EthernetTcpServerHelloWorld_manual", "EthernetTcpServerHelloWorld_manual\EthernetTcpServerHelloWorld_manual.cppproj", "{AA02A8C2-2672-456F-BBD9-2D87195F8292}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "EthernetTcpClientHelloWorld", "EthernetTcpClientHelloWorld\EthernetTcpClientHelloWorld.cppproj", "{EB373D13-2EC0-42DA-BDE8-EB9F90421805}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "EthernetTcpServerHelloWorld_automatic", "EthernetTcpServerHelloWorld_automatic\EthernetTcpServerHelloWorld_automatic.cppproj", "{5A820189-8BE3-4E9B-BD9B-1D1EA7B11099}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{550B0E05-B621-4032-B7A8-3A17D156FC44}.Debug|ARM.ActiveCfg = Debug|ARM
+		{550B0E05-B621-4032-B7A8-3A17D156FC44}.Debug|ARM.Build.0 = Debug|ARM
+		{550B0E05-B621-4032-B7A8-3A17D156FC44}.Release|ARM.ActiveCfg = Release|ARM
+		{550B0E05-B621-4032-B7A8-3A17D156FC44}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{AA02A8C2-2672-456F-BBD9-2D87195F8292}.Debug|ARM.ActiveCfg = Debug|ARM
+		{AA02A8C2-2672-456F-BBD9-2D87195F8292}.Debug|ARM.Build.0 = Debug|ARM
+		{AA02A8C2-2672-456F-BBD9-2D87195F8292}.Release|ARM.ActiveCfg = Release|ARM
+		{AA02A8C2-2672-456F-BBD9-2D87195F8292}.Release|ARM.Build.0 = Release|ARM
+		{EB373D13-2EC0-42DA-BDE8-EB9F90421805}.Debug|ARM.ActiveCfg = Debug|ARM
+		{EB373D13-2EC0-42DA-BDE8-EB9F90421805}.Debug|ARM.Build.0 = Debug|ARM
+		{EB373D13-2EC0-42DA-BDE8-EB9F90421805}.Release|ARM.ActiveCfg = Release|ARM
+		{EB373D13-2EC0-42DA-BDE8-EB9F90421805}.Release|ARM.Build.0 = Release|ARM
+		{5A820189-8BE3-4E9B-BD9B-1D1EA7B11099}.Debug|ARM.ActiveCfg = Debug|ARM
+		{5A820189-8BE3-4E9B-BD9B-1D1EA7B11099}.Debug|ARM.Build.0 = Debug|ARM
+		{5A820189-8BE3-4E9B-BD9B-1D1EA7B11099}.Release|ARM.ActiveCfg = Release|ARM
+		{5A820189-8BE3-4E9B-BD9B-1D1EA7B11099}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpClientHelloWorld/EthernetTcpClientHelloWorld.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpClientHelloWorld/EthernetTcpClientHelloWorld.cpp
new file mode 100644
index 000000000..52e7df528
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpClientHelloWorld/EthernetTcpClientHelloWorld.cpp
@@ -0,0 +1,183 @@
+/*
+ * Title: EthernetTcpClient  
+ *
+ * Objective:
+ *    This example demonstrates how to configure a ClearCore as a TCP client to 
+ *    send and receive TCP datagrams (packets).
+ *
+ * Description:
+ *    This example configures a ClearCore device to act as a TCP client. This client 
+ *    connects to another device acting as a TCP server to exchange data over 
+ *    ethernet TCP. This simple example connects to a server, sends a simple "Hello server"
+ *	  message, and receives and prints incoming data from the server.
+ *
+ *    Partner projects, EthernetTcpServer_autoClientManagement and EthernetTcpServer_manualClientManagement 
+ *    are available to configure another ClearCore to act as a server.
+ *
+ * Setup:
+ * 1. Identify the IP address of the server and specify it (as serverIp) below. When 
+ *    using either of the EthernetTcpServer examples, the server's IP address will print to a 
+ *    connected serial terminal upon startup.
+ * 2. Set the usingDhcp boolean as appropriate. If not using DHCP, specify static 
+ *    IP address and network information.
+ * 3. The server and client must be connected to the same network.
+ *    If server and client devices are connected to each other directly (as opposed to connection through a switch)
+ *	  an ethernet crossover cable may be required.  
+ * 4. It may be helpful to use a terminal application such as PuTTY to view serial output from each device. https://www.putty.org/
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * 
+ * Copyright (c) 2022 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */ 
+
+ 
+#include "ClearCore.h"
+#include "EthernetTcpClient.h"
+#include "SysTiming.h"
+
+// The IP address of the server you want to connect to
+IpAddress serverIp = IpAddress(192, 168, 0, 123);
+
+// The port number over which packets will be sent/received
+#define PORT_NUM 8888
+
+// The maximum number of characters allowed per incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets.
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+
+// Set usingDhcp to false to use user defined network settings
+bool usingDhcp = true;
+
+
+int main(void) {
+	// Set up serial communication between ClearCore and PC serial terminal
+	ConnectorUsb.Mode(Connector::USB_CDC);
+	ConnectorUsb.Speed(9600);
+	ConnectorUsb.PortOpen();
+	uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    while (!ConnectorUsb && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+	
+	// Set connector IO0 as a digital output
+	// When IO0 state is true, its associated LED will turn on
+	// indicating a successful connection to a server 
+	ConnectorIO0.Mode(Connector::OUTPUT_DIGITAL);
+
+	// Make sure the physical link is active before continuing 
+	while (!EthernetMgr.PhyLinkActive()) {
+		ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+		Delay_ms(1000);
+	}
+	
+	// Configure with an IP address assigned via DHCP
+	EthernetMgr.Setup();
+	if (usingDhcp) {
+		// Use DHCP to configure the local IP address
+		bool dhcpSuccess = EthernetMgr.DhcpBegin();
+		if (dhcpSuccess) {
+			ConnectorUsb.Send("DHCP successfully assigned an IP address: ");
+			ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+		} else {
+			ConnectorUsb.SendLine("DHCP configuration was unsuccessful!");
+			while (true) {
+				// TCP will not work without a configured IP address
+				continue;
+			}
+		}
+	} else {
+		// Configure with a manually assigned IP address
+	
+		// Set ClearCore IP address
+		IpAddress ip = IpAddress(192, 168, 0, 103);
+		EthernetMgr.LocalIp(ip);
+		ConnectorUsb.Send("Assigned manual IP address: ");
+		ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+		
+		// Optional: set additional network addresses if needed
+		
+		//IpAddress gateway = IpAddress(192, 168, 1, 1);
+		//IpAddress netmask = IpAddress(255, 255, 255, 0);
+		//EthernetMgr.GatewayIp(gateway);
+		//EthernetMgr.NetmaskIp(netmask);
+	}
+	
+	// Initialize a client object
+	// The ClearCore will operate as a TCP client using this object
+	EthernetTcpClient client;
+	
+	// Attempt to connect to a server
+	if (!client.Connect(serverIp, PORT_NUM)) {
+				ConnectorUsb.SendLine("Failed to connect to server. Retrying...");
+			}
+	
+	// Connect to server, and send/receive packets
+	while(true){
+		
+		// Make sure the physical link is active before continuing
+		while (!EthernetMgr.PhyLinkActive()) {
+			ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+			Delay_ms(1000);
+		}
+		
+		// Attempt to connect to server
+		if(!client.Connected()){
+			// Turn off LED if the client is not connected
+			ConnectorIO0.State(false);	
+			
+			uint32_t delay = 1000;
+			if (!client.Connect(serverIp, PORT_NUM)) {
+				if(Milliseconds() - startTime > delay){
+					ConnectorUsb.SendLine("Failed to connect to server. Retrying...");
+					startTime = Milliseconds();
+				}
+			}
+		} else {
+			// Turn on LED if client is connected
+			ConnectorIO0.State(true);
+			
+			// If connection was successful, send and receive packets
+			if( client.Send("Hello server") >0)
+			{
+				ConnectorUsb.Send("Sent 'Hello server'. Response from server: ");
+				bool receivedMessage = false;
+				
+				// Read any incoming packets from the server over the next second
+				uint32_t delay = 1000;
+				startTime = Milliseconds();
+				while((Milliseconds() - startTime) < delay){
+					if (client.Read(packetReceived, MAX_PACKET_LENGTH) > 0)
+					{
+						receivedMessage = true;
+						ConnectorUsb.Send((char *)packetReceived);
+						
+						// Clear the message buffer for the next iteration of the loop
+						for(int i=0; i<MAX_PACKET_LENGTH; i++){
+							packetReceived[i]=NULL;
+						}
+					}
+					EthernetMgr.Refresh();
+				}
+				// If no packets were received, inform the user via serial message
+				if (!receivedMessage){
+					ConnectorUsb.SendLine("Didn't receive message.");
+				}else{
+					ConnectorUsb.SendLine();
+				}
+			}
+			else
+			{
+				client.Close();
+			}
+		}
+		// Perform any necessary periodic ethernet updates
+		// Must be called regularly when actively using ethernet
+		EthernetMgr.Refresh();
+	}
+		
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpClientHelloWorld/EthernetTcpClientHelloWorld.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpClientHelloWorld/EthernetTcpClientHelloWorld.cppproj
new file mode 100644
index 000000000..8359ee604
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpClientHelloWorld/EthernetTcpClientHelloWorld.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{eb373d13-2ec0-42da-bde8-eb9f90421805}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>EthernetTcpHelloWorld</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="EthernetTcpClientHelloWorld.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
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+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
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+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
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+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_automatic/EthernetTcpServerHelloWorld_automatic.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_automatic/EthernetTcpServerHelloWorld_automatic.cpp
new file mode 100644
index 000000000..1ba51fff6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_automatic/EthernetTcpServerHelloWorld_automatic.cpp
@@ -0,0 +1,176 @@
+/*
+ * Title: EthernetTCPServer_autoClientManagement
+ *
+ * Objective:
+ *    This example demonstrates how to configure a ClearCore as a TCP server to 
+ *    send and receive TCP datagrams (packets). 
+ *    
+ * Description:
+ *    This example configures a ClearCore device to act as a TCP server. 
+ *    This server can receive connections from another device acting as a TCP 
+ *    client to exchange data over ethernet TCP. 
+ *    This simple example accepts connection requests from clients, receives and
+ *    prints incoming data from connected devices, and sends a simple "Hello 
+ *    client" response.
+ *    A partner project, EthernetTcpClientHelloWorld, is available to configure 
+ *    another ClearCore as a client.
+ *
+ * Setup:
+ * 1. Set the usingDhcp boolean as appropriate. If not using DHCP, specify static 
+ *    IP and network information.
+ * 2. Ensure the server and client are set up to communicate on the same network.
+ *    If both devices are directly connected (as opposed to connected through a switch) an ethernet crossover cable may be required. 												  
+ * 3. It may be helpful to use a terminal application such as PuTTY to view serial output from each device. https://www.putty.org/
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * 
+ * Copyright (c) 2022 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+#include "EthernetTcpServer.h"
+
+// The port number on the server over which packets will be sent/received 
+#define PORT_NUM 8888
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+
+// Set usingDhcp to false to use user defined network settings
+bool usingDhcp = true;
+
+int main(void) {
+	// Set up serial communication between ClearCore and PC serial terminal 
+	ConnectorUsb.Mode(Connector::USB_CDC);
+	ConnectorUsb.Speed(9600);
+	ConnectorUsb.PortOpen();
+	uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    while (!ConnectorUsb && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+	// Set connector IO0 as a digital output
+	// When IO0 state is true, a LED will light on the
+	// ClearCore indicating a successful connection to a client
+	ConnectorIO0.Mode(Connector::OUTPUT_DIGITAL);
+	
+	// Make sure the physical link is active before continuing
+	while (!EthernetMgr.PhyLinkActive()) {
+		ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+		Delay_ms(1000);
+	}
+	
+	// To configure with an IP address assigned via DHCP
+	EthernetMgr.Setup();
+	if (usingDhcp) {
+		// Use DHCP to configure the local IP address
+		
+		bool dhcpSuccess = EthernetMgr.DhcpBegin();
+		if (dhcpSuccess) {
+			ConnectorUsb.Send("DHCP successfully assigned an IP address: ");
+			ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+		}
+		else {
+			ConnectorUsb.SendLine("DHCP configuration was unsuccessful!");
+			while (true) {
+				// TCP will not work without a configured IP address
+				continue;
+			}
+		}
+	} else {
+		// Configure with a manually assigned IP address
+		
+		// Set ClearCore's IP address
+		IpAddress ip = IpAddress(192, 168, 0, 109);
+		EthernetMgr.LocalIp(ip);
+		ConnectorUsb.Send("Assigned manual IP address: ");
+		ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+		
+		// Optionally set additional network addresses if needed
+		
+		//IpAddress gateway = IpAddress(192, 168, 1, 1);
+		//IpAddress netmask = IpAddress(255, 255, 255, 0);
+		//EthernetMgr.GatewayIp(gateway);
+		//EthernetMgr.NetmaskIp(netmask);
+	}
+	
+
+	// Initialize the ClearCore as a server that will listen for  
+	// incoming client connections on specified port (8888 by default)
+	EthernetTcpServer server = EthernetTcpServer(PORT_NUM);
+	
+	// Initialize a client object
+	// This object will hold a connected client's information 
+	// allowing the server to interact with the client 
+	EthernetTcpClient client;
+	
+	// Start listening for TCP connections
+	server.Begin();
+
+	ConnectorUsb.SendLine("Server now listening for client connections...");
+
+	// Connect to clients, and send/receive packets
+	while(true){
+		// Obtain a reference to a connected client with incoming data available
+		// This function will only return a valid reference if the connected device
+		// has data available to read
+		client = server.Available();
+		
+		// Check if the server has returned a connected client with incoming data available
+		if (client.Connected() || client.BytesAvailable() > 0) {
+			// Flash on LED if a client has sent a message
+			ConnectorIO0.State(true);
+			
+			// Delay to allow user to see the LED
+			// This example will flash the LED each time a message from a client is received
+			Delay_ms(100); 
+			
+			// Read packet from the client
+			ConnectorUsb.Send("Read the following from the client: ");
+			while (client.BytesAvailable() > 0) {
+				// Send the data received from the client over a serial port
+				client.Read(packetReceived, MAX_PACKET_LENGTH);
+				ConnectorUsb.Send((char *)packetReceived);
+				
+				// Clear the message buffer for the next iteration of the loop
+				for(int i=0; i<MAX_PACKET_LENGTH; i++){
+					packetReceived[i]= NULL;
+				}
+			}
+			ConnectorUsb.SendLine();
+			
+			// Send response message to client
+			if (client.Send("Hello client ")>0){
+				ConnectorUsb.SendLine("Sent 'Hello Client' response");
+			}
+			else{
+				ConnectorUsb.SendLine("Unable to send reply");
+			}
+		} else{
+			// Turn off LED if a message has not been received
+			ConnectorIO0.State(false);
+			if(client.ConnectionState()->state == CLOSING){
+				client.Close();
+			}
+   
+			// Make sure the physical link is active before continuing
+			while (!EthernetMgr.PhyLinkActive()) {
+				ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+				Delay_ms(1000);
+			}
+		}
+		// Broadcast message to all clients
+		//server.Send("Hello all clients ");
+		
+		// Perform any necessary periodic ethernet updates
+		// Must be called regularly when actively using ethernet
+		EthernetMgr.Refresh();
+	}
+	
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_automatic/EthernetTcpServerHelloWorld_automatic.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_automatic/EthernetTcpServerHelloWorld_automatic.cppproj
new file mode 100644
index 000000000..745ba09ef
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_automatic/EthernetTcpServerHelloWorld_automatic.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>EthernetTcpServerHelloWorld_automatic</Name>
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+        <armgcccpp.compiler.symbols.DefSymbols>
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+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="EthernetTcpServerHelloWorld_automatic.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_manual/EthernetTcpServerHelloWorld_manual.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_manual/EthernetTcpServerHelloWorld_manual.cpp
new file mode 100644
index 000000000..ff64a8bc8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_manual/EthernetTcpServerHelloWorld_manual.cpp
@@ -0,0 +1,252 @@
+/*
+ * Title: EthernetTCPServer_manualClientManagement 
+ *
+ * Objective:
+ *    This example demonstrates how to configure a ClearCore as a TCP server to 
+ *    send and receive TCP datagrams (packets).
+ *    
+ * Description:
+ *    This example configures a ClearCore device to act as a TCP server. 
+ *    This server can receive connections from several other devices acting as TCP 
+ *    clients to exchange data over ethernet TCP. 
+ *    This simple example accepts connection requests from clients, checks for
+ *    incoming data from connected devices, and sends a simple "Hello 
+ *    client" response.
+ *    A partner project, EthernetTcpClientHelloWorld, can be used to configure 
+ *    another ClearCore as a client device.
+ *
+ * Setup:
+ * 1. Set the usingDhcp boolean as appropriate. If not using DHCP, specify static 
+ *    IP and network information.
+ * 2. Ensure the server and client are setup to communicate on the same network.
+ *    If server and client devices are directly connected (as opposed to through a switch)
+ *    an ethernet crossover cable may be required. 
+ * 3. It may be helpful to use another application to view serial output from 
+ *    each device. PuTTY is one such application: https://www.putty.org/
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * 
+ * Copyright (c) 2022 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+#include "EthernetTcpServer.h"
+
+// The port number on the server over which packets will be sent/received 
+#define PORT_NUM 8888
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+// Buffer for holding packets to send
+char packetToSend[MAX_PACKET_LENGTH]; 
+
+// Set total number of clients the server will accept
+#define NUMBER_OF_CLIENTS 6
+
+// Set usingDhcp to false to use user defined network settings
+bool usingDhcp = true;
+
+// Array of output LEDs to indicate client connections
+// NOTE: only connectors IO0 through IO5 can be configured as digital outputs (LEDs) 
+Connector *const outputLEDs[6] = {
+	&ConnectorIO0, &ConnectorIO1, &ConnectorIO2, &ConnectorIO3, &ConnectorIO4, &ConnectorIO5
+};
+
+
+int main(void) {
+	// Set up serial communication between ClearCore and PC serial terminal 
+	ConnectorUsb.Mode(Connector::USB_CDC);
+	ConnectorUsb.Speed(9600);
+	ConnectorUsb.PortOpen();
+	uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    while (!ConnectorUsb && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+	// Set connectors IO0-IO5 as a digital outputs 
+	// When an outputLED's state is true, a LED will light on the
+	// ClearCore indicating a successful connection to a client
+	for(int i=0; i<6; i++){
+	outputLEDs[i]->Mode(Connector::OUTPUT_DIGITAL);
+	}
+	
+	// Make sure the physical link is active before continuing
+	while (!EthernetMgr.PhyLinkActive()) {
+		ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+		Delay_ms(1000);
+	}
+	
+	//To configure with an IP address assigned via DHCP
+	EthernetMgr.Setup();
+	if (usingDhcp) {
+		// Use DHCP to configure the local IP address
+		bool dhcpSuccess = EthernetMgr.DhcpBegin();
+		if (dhcpSuccess) {
+			ConnectorUsb.Send("DHCP successfully assigned an IP address: ");
+			ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+		}
+		else {
+			ConnectorUsb.SendLine("DHCP configuration was unsuccessful!");
+			while (true) {
+				// TCP will not work without a configured IP address
+				continue;
+			}
+		}
+	} else {
+		// Configure with a manually assigned IP address
+		
+		// Set ClearCore's IP address
+		IpAddress ip = IpAddress(192, 168, 0, 100);
+		EthernetMgr.LocalIp(ip);
+		ConnectorUsb.Send("Assigned manual IP address: ");
+		ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+		
+		// Optionally, set additional network addresses if needed
+		
+		//IpAddress gateway = IpAddress(192, 168, 1, 1);
+		//IpAddress netmask = IpAddress(255, 255, 255, 0);
+		//EthernetMgr.GatewayIp(gateway);
+		//EthernetMgr.NetmaskIp(netmask);
+	}
+	
+
+	// Initialize the ClearCore as a server 
+	// Clients connect on specified port (8888 by default)
+	EthernetTcpServer server = EthernetTcpServer(PORT_NUM);
+	
+	// Initialize an array of clients
+	// This array holds the information of any client that
+	// is currently connected to the server, and is used by the
+	// server to interact with these clients
+	EthernetTcpClient clients[NUMBER_OF_CLIENTS];
+	// Initialize an temporary client for client management
+	EthernetTcpClient tempClient;
+	
+	bool newClient = 0;
+
+	// Start listening for TCP connections
+	server.Begin();
+
+	ConnectorUsb.SendLine("Server now listening for client connections...");
+
+	// Resets a timer used to display a list of connected clients
+	startTime = 0;
+	
+	// Connect to clients, and send/receive packets
+	while(true){
+		
+		// Obtain a reference to a connected client
+		// This function returns a specific client once per connection attempt
+		// To maintain a connection with a client using Accept() 
+		// some basic client management must be performed
+		tempClient = server.Accept();
+		
+		// Checks if server.Accept() has returned a new client
+		if(tempClient.Connected()){
+			newClient = 1; 
+			
+			for(int i=0; i<NUMBER_OF_CLIENTS; i++){
+				//Checks for an available location to store a new client
+				if(!clients[i].Connected()){
+					clients[i].Close();
+					clients[i] = tempClient;
+					ConnectorUsb.Send(clients[i].RemoteIp().StringValue());
+					ConnectorUsb.SendLine(" has been connected");
+					newClient = 0;
+					break;
+				}
+			}
+			// Rejects client if the client list is full 
+			if(newClient == 1){
+				newClient = 0;
+				tempClient.Send("This server has reached its max number of clients. Closing connection.");
+				sprintf(packetToSend, "This server has reached its max number of clients. Closing connection to (%s).", tempClient.RemoteIp().StringValue());
+				ConnectorUsb.SendLine(packetToSend);
+				tempClient.Close();
+			}
+		}
+		
+		// Loops through list of clients to receive/send messages
+		for(int i=0; i<NUMBER_OF_CLIENTS; i++){
+			if (clients[i].Connected()) {
+				
+				// Indicate connection on corresponding output LED
+				outputLEDs[i]->State(true);
+				
+				// Check if client has incoming data available	
+				if(clients[i].BytesAvailable()){
+					sprintf(packetToSend, "Read the following from the client(%s): ", clients[i].RemoteIp().StringValue());
+					ConnectorUsb.Send(packetToSend);
+					// Read packet from the client
+					while (clients[i].BytesAvailable()) {
+						// Send the data received from the client over a serial port
+						clients[i].Read(packetReceived, MAX_PACKET_LENGTH);
+						ConnectorUsb.Send((char *)packetReceived);
+
+						// Clear the message buffer for the next iteration of the loop
+						for(int i=0; i<MAX_PACKET_LENGTH; i++){
+							packetReceived[i]=NULL;
+						}
+					}
+					ConnectorUsb.SendLine();
+					
+					//Sends unique response to the client
+					sprintf(packetToSend, "Hello client %s",clients[i].RemoteIp().StringValue());
+					if(clients[i].Send(packetToSend) == 0){
+						// If the message was unable to send, close the client connection
+						clients[i].Close();
+						sprintf(packetToSend, "Client (%s) has been removed from client list. ", clients[i].RemoteIp().StringValue());
+						ConnectorUsb.Send(packetToSend);
+						clients[i] = EthernetTcpClient();
+						
+						// Indicate loss of connection by turning off corresponding LED
+						outputLEDs[i]->State(false);
+					}
+
+				}
+				
+			} else{
+				// Removes any disconnected clients
+				if(clients[i].RemoteIp() != IpAddress(0,0,0,0)){
+					sprintf(packetToSend, "Client (%s) has been removed from client list. ", clients[i].RemoteIp().StringValue());
+					ConnectorUsb.Send(packetToSend);
+					clients[i].Close();
+					clients[i] = EthernetTcpClient();
+
+					// Indicate loss of connection by turning off corresponding LED
+					outputLEDs[i]->State(false);
+				}
+			}
+		}
+		
+		// Make sure the physical link is active before continuing
+		while (!EthernetMgr.PhyLinkActive()) {
+			ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+			Delay_ms(1000);
+		}
+		
+		// Print out a list of current clients
+		int delay = 5000;
+		if(Milliseconds()- startTime > delay){
+			ConnectorUsb.SendLine("List of current clients: ");
+			for(int i=0; i<NUMBER_OF_CLIENTS; i++){
+				if(clients[i].RemoteIp() != IpAddress(0,0,0,0)){
+					sprintf(packetToSend, "Client %i = %s", i, clients[i].RemoteIp().StringValue());
+					ConnectorUsb.SendLine(packetToSend);
+				}
+			}
+			startTime = Milliseconds();
+		}
+		
+		// Perform any necessary periodic ethernet updates
+		// Must be called regularly when actively using ethernet
+		EthernetMgr.Refresh();
+	}
+}
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_manual/EthernetTcpServerHelloWorld_manual.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_manual/EthernetTcpServerHelloWorld_manual.cppproj
new file mode 100644
index 000000000..63f7e2a0e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetTcpServerHelloWorld_manual/EthernetTcpServerHelloWorld_manual.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>EthernetTcpServerHelloWorld_manual</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="EthernetTcpServerHelloWorld_manual.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cpp
new file mode 100644
index 000000000..885fa68ec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cpp
@@ -0,0 +1,224 @@
+/*
+ * Title: EthernetUdpHelloWorld
+ *
+ * Objective:
+ *    This example demonstrates how to enable Ethernet functionality to send and
+ *    receive UDP datagrams (packets).
+ *
+ * Description:
+ *    This example will set up ethernet communications between a ClearCore and
+ *    another Ethernet source (a PC or ClearCore). The example then prints the
+ *    contents of the packets received to the specified serial port and sends
+ *    a "Hello World" response to the sender.
+ *
+ * Requirements:
+ * ** Setup 1 (ClearCore and a PC): The PC should be running software capable
+ *    of sending and receiving UDP packets. PacketSender is highly recommended
+ *    as a free, cross-platform software. Configure PacketSender to send a UDP
+ *    packet to the ClearCore by specifying the IP address and port provided to
+ *    EthernetMgr.LocalIp(). Your firewall or network settings may need to be
+ *    adjusted in order to receive the response back from the ClearCore.
+ * ** Setup 2 (ClearCore to a ClearCore): A partner sketch is included at the
+ *    end of this file that can be used on the other ClearCore. The MAC address
+ *    and IP address values set up for each ClearCore must be unique. The remote
+ *    IP address and port used in the partner sketch must match the IP address
+ *    and port used to setup the ClearCore in this sketch.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+#include "ClearCore.h"
+#include "EthernetUdp.h"
+
+// Change the IP address below to match your ClearCore's IP address.
+IpAddress ip = IpAddress(192, 168, 1, 177);
+
+// The local port to listen for connections on.
+uint16_t localPort = 8888;
+
+// The maximum number of characters to receive from an incoming packet
+#define MAX_PACKET_LENGTH 100
+// Buffer for holding received packets.
+unsigned char packetReceived[MAX_PACKET_LENGTH];
+
+// The Ethernet UDP object to let us send and receive packets over UDP
+EthernetUdp Udp;
+
+// Set this false if not using DHCP to configure the local IP address.
+bool usingDhcp = true;
+
+int main() {
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    ConnectorUsb.Mode(Connector::USB_CDC);
+    ConnectorUsb.Speed(9600);
+    ConnectorUsb.PortOpen();
+
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    while (!ConnectorUsb && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Make sure the physical link is up before continuing.
+    while (!EthernetMgr.PhyLinkActive()) {
+        ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+        Delay_ms(1000);
+    }
+
+    // Run the setup for the ClearCore Ethernet manager.
+    EthernetMgr.Setup();
+
+    if (usingDhcp) {
+        // Use DHCP to configure the local IP address.
+        bool dhcpSuccess = EthernetMgr.DhcpBegin();
+        if (dhcpSuccess) {
+            ConnectorUsb.Send("DHCP successfully assigned an IP address: ");
+            ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+        }
+        else {
+            ConnectorUsb.SendLine("DHCP configuration was unsuccessful!");
+            while (true) {
+                // UDP will not work without a configured IP address.
+                continue;
+            }
+        }
+    }
+    else {
+        EthernetMgr.LocalIp(ip);
+    }
+
+    // Begin listening on the local port for UDP datagrams
+    Udp.Begin(localPort);
+
+    // This loop will wait to receive a packet from a remote source, then reply
+    // back with a packet containing a "Hello, world!" message.
+    while (true) {
+        // Look for a received packet.
+        uint16_t packetSize = Udp.PacketParse();
+
+        if (packetSize > 0) {
+            ConnectorUsb.Send("Received packet of size ");
+            ConnectorUsb.Send(packetSize);
+            ConnectorUsb.SendLine(" bytes.");
+
+            ConnectorUsb.Send("Remote IP: ");
+            ConnectorUsb.SendLine(Udp.RemoteIp().StringValue());
+
+            ConnectorUsb.Send("Remote port: ");
+            ConnectorUsb.SendLine(Udp.RemotePort());
+
+            // Read the packet.
+            int32_t bytesRead = Udp.PacketRead(packetReceived, MAX_PACKET_LENGTH);
+            ConnectorUsb.Send("Number of bytes read from packet: ");
+            ConnectorUsb.SendLine(bytesRead);
+
+            ConnectorUsb.Send("Packet contents: ");
+            ConnectorUsb.SendLine((char *)packetReceived);
+            ConnectorUsb.SendLine();
+
+            // Send a "Hello, world!" reply packet back to the sender.
+            Udp.Connect(Udp.RemoteIp(), Udp.RemotePort());
+            Udp.PacketWrite("Hello, world!");
+            Udp.PacketSend();
+        }
+
+        Delay_ms(10);
+    }
+}
+
+
+/*
+  // ---------------------------------
+  // Partner ClearCore Example Sketch
+  // ---------------------------------
+
+#include "ClearCore.h"
+#include "EthernetUdp.h"
+
+// Change the IP address below to match this ClearCore's IP address.
+IpAddress ip = IpAddress(192, 168, 1, 178);
+
+// The local port to listen for connections on.
+uint16_t localPort = 8888;
+
+// The remote ClearCore's IP address and port
+IpAddress remoteIp = IpAddress(192, 168, 1, 177);
+uint16_t remotePort = 8888;
+
+// The last time you sent a packet to the remote device, in milliseconds.
+uint32_t lastSendTime = 0;
+// Delay between sending packets, in milliseconds
+const uint32_t sendingInterval = 10 * 1000;
+
+// An EthernetUDP instance to let us send and receive packets over UDP
+EthernetUdp Udp;
+
+// Set this false if not using DHCP to configure the local IP address.
+bool usingDhcp = true;
+
+int main() {
+    // Set up serial communication at a baud rate of 9600 bps then wait up to
+    // 5 seconds for a port to open.
+    // Serial communication is not required for this example to run, however the
+    // example will appear to do nothing without serial output.
+    ConnectorUsb.Mode(Connector::USB_CDC);
+    ConnectorUsb.Speed(9600);
+    ConnectorUsb.PortOpen();
+
+    // Run the setup for the ClearCore Ethernet manager.
+    EthernetMgr.Setup();
+
+    if (usingDhcp) {
+        // Use DHCP to configure the local IP address
+        bool dhcpSuccess = EthernetMgr.DhcpBegin();
+        if (dhcpSuccess) {
+            ConnectorUsb.Send("DHCP successfully assigned an IP address: ");
+            ConnectorUsb.SendLine(EthernetMgr.LocalIp().StringValue());
+        }
+        else {
+            ConnectorUsb.SendLine("DHCP configuration was unsuccessful!");
+            ConnectorUsb.SendLine("Try again using a manual configuration...");
+            while (true) {
+                // UDP will not work without a configured IP address.
+                continue;
+            }
+        }
+    }
+    else {
+        EthernetMgr.LocalIp(ip);
+    }
+
+    // Make sure the physical link is up before continuing.
+    while (!EthernetMgr.PhyLinkActive()) {
+        ConnectorUsb.SendLine("The Ethernet cable is unplugged...");
+        Delay_ms(1000);
+    }
+
+    // Begin listening on the local port for UDP datagrams
+    Udp.Begin(localPort);
+
+    // This loop will send a packet to the remote IP and port specified every
+    // 10 seconds.
+    while (true) {
+        // Wait for 10 seconds.
+        if (Milliseconds() - lastSendTime > sendingInterval) {
+            Udp.Connect(remoteIp, remotePort);
+            Udp.PacketWrite("Hello ClearCore.");
+            Udp.PacketSend();
+            lastSendTime = Milliseconds();
+        }
+
+        // Keep the connection alive.
+        EthernetMgr.Refresh();
+    }
+}
+
+*/
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cppproj
new file mode 100644
index 000000000..64aca61bd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{550b0e05-b621-4032-b7a8-3a17d156fc44}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="EthernetUdpHelloWorld.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
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+      <SubType>compile</SubType>
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+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
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+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol.cpp
new file mode 100644
index 000000000..1e29f79fd
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol.cpp
@@ -0,0 +1,871 @@
+/*
+ * Title: ClearCoreCommandProtocol
+ *
+ * Objective:
+ *    This example demonstrates control of various functionality of the Teknic 
+ *     ClearCoreI/O and motion controller, including controlling ClearPath-SD 
+ *     motors instep and direction mode.
+ *
+ * Description:
+ *    This example processes strings of characters formatted according to the
+ *     specifications below and commands the corresponding action on a ClearCore device. 
+ *    This example is designed to be highly configurable to meet the requirements
+ *     of a variety of applications. The protocol accepts input and sends output
+ *     via USB connection by default but can be configured to accept commands from
+ *     other streams - such as ClearCore's COM ports, ethernet port, or XBee
+ *     connection - and sources - such as manual user input, input from a text
+ *     file, or control from another device sending text commands to ClearCore.
+ *    
+ * Setup:
+ * 0. Consult the accompanying ClearCore Command Protocol User Guide for more
+ *     information on using this example project.
+ *		https://teknic.com/files/downloads/ClearCoreCommandProtocol_UserGuide.pdf
+ * 1. Connect ClearCore via USB to a terminal that can send and receive ASCII
+ *     (standard text encoding) messages, or modify the code and connect to a
+ *     different source of messages. Other ClearCore examples demonstrate
+ *     communication via these alternate connection options. 
+ * 2. ClearPath-SD motors can be connected to connector M-0, M-1, M-2, and/or M-3.
+ * 3. The connected ClearPath-SD motor(s) must be configured through the MSP software
+ *    for Step and Direction mode (In MSP select Mode>>Step and Direction).
+ * 4. The ClearPath-SD motor(s) must be set to use the HLFB mode "ASG-Position
+ *    w/Measured Torque" with a PWM carrier frequency of 482 Hz through the MSP
+ *    software (select Advanced>>High Level Feedback [Mode]... then choose
+ *    "ASG-Position w/Measured Torque" from the dropdown, make sure that 482 Hz
+ *    is selected in the "PWM Carrier Frequency" dropdown, and hit the OK
+ *    button).
+ * 5. Set the Input Format in MSP for "Step + Direction".  
+ * 6. Set the Input Resolution in MSP the same as your motor's Positioning
+ *    Resolution spec if you'd like the pulses sent by ClearCore to command a
+ *    move of the same number of Encoder Counts, a 1:1 ratio.
+ * 7. Input and output devices can be wired to connectors IO0-IO5, DI6-DI8, and/or
+ *     AI9-AI12. A table summarizing the acceptable connector modes for each
+ *     ClearCore connector can be found in the ClearCore manual and in the User
+ *     Guide for this example. This example explicitly sets the operational mode
+ *     for each connector, but these modes can be reconfigured according to the
+ *     table in the manual. Be sure to consult the ClearCore manual and
+ *     supplemental wiring and connection diagrams to view the operating modes
+ *     for each pin and corresponding connection setups.
+ *    
+ * Example Command Sequences
+ *	The following provides an example command sequence and corresponding behavior:
+ *		e1			//enable motor1
+ *		e2			//enable motor2
+ *		m1 1000		// if ABSOLUTE_MOVE==1, move motor1 to absolute position 1000 steps 
+ *					// if ABSOLUTE_MOVE==0, move motor1 1000 steps in the positive direction 
+ *		v2 -200		//move motor2 at -200 steps/s in the negative direction
+ *		q2s			//query the status of motor2
+ *		l3v	100		//limit motor3's velocity (of positional moves only) to 100 steps/s
+ *		z1			//zero Clear's position reference for motor1 (no motion is commanded to the motor)  
+ *		i6			//read the current state of connector6 (DI6)
+ *		o5 1		//output a value of 1 (digital high) to connector5 (IO5)
+ *		h 			//display the help message
+ *		
+ *	The following example command sequence highlights special cases and notable behavior:
+ *		v0 1000		//since motor0 has not yet been enabled, no motion will be commanded
+ *		e0			//enable motor0
+ *		v0 1000		//move motor0 at 1000 steps/s
+ *		d0			//disable motor0. since motor0 was actively moving, motor0 will fault
+ *		v0 1000		//since motor0 is in fault (disabled during motion), no motion will be commanded
+ *		q1s			//query the status of motor0. since the motor is in alert, the alert status will also print
+ *		f 0			//disable verbose feedback 
+ *		q1s			//with verbose feedback disabled, only the numerical status (and alert, in this case) 
+ *					//	register(s) will print, not the full status (and alert) message
+ *		c0			//clear alerts on motor0
+ *		v0 1000		//move motor0 at 1000 steps/s
+ *		
+ *		m1 2000		//assuming ABSOLUTE_MOVE is left as default, move motor1 to absolute position 2000 steps
+ *		m1 2000		//since motor1 is already at absolute position 2000 steps, no motion will be commanded
+ *		z1			//define motor1's current position as the zero position 
+ *		m1 2000		//move motor1 to absolute position 2000, which is 2000 steps  
+ *					//	away from its freshly-zeroed current position
+ *    
+ * Additional Resources:
+ * ** ClearCore Command Protocol User Guide:
+ *     https://teknic.com/files/downloads/ClearCoreCommandProtocol_UserGuide.pdf
+ * ** ClearCore Documentation:
+ * 		https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual:
+ * 		 https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearCore System Diagram and Connection Diagrams:
+ * 		https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ * ** ClearPath Manual (DC Power):
+ * 		https://www.teknic.com/files/downloads/clearpath_user_manual.pdf
+ * ** ClearPath Manual (AC Power):
+ * 		https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+#include <stdint.h>
+#include <stdlib.h> //for atoi (ASCII to Integer) parsing utility
+
+// specify which serial interface to use as input/output
+#define ioPort ConnectorUsb
+// select the baud rate to match the target device.
+#define ioPortBaudRate  115200
+// specify whether the target serial interface uses CTS/RTS flow control
+// 	set to true if your target device uses CTS/RTS flow control
+// this is only necessary if using COM ports or XBee module (not necessary for USB)
+#define ioFlowControl false
+
+// structure to hold information on the feedback messages
+struct FeedbackMessage{
+	uint32_t number;
+	char *message; 
+};
+
+// feedback message numbers
+#define FB_COMMAND_OK									( 0)	
+#define FB_ERR_BUFFER_OVERRUN                   		( 1)
+#define FB_ERR_INPUT_INVALID_NONLETTER          		( 2)
+#define FB_ERR_MOTOR_NUM_INVALID						( 3)	
+#define FB_ERR_CONNECTOR_NUM_INVALID					( 4)	
+#define FB_ERR_CONNECTOR_MODE_INCOMPATIBLE				( 5)
+#define FB_ENABLED_WAITING_ON_HLFB						( 6)
+#define FB_ENABLE_FAILURE								( 7)
+#define FB_ERR_IO_OUTPUT								( 8)
+#define FB_ERR_MOVE_NOT_ENABLED							( 9)	
+#define FB_ERR_MOVE_IN_ALERT                    		(10)
+#define FB_ERR_INVALID_QUERY_REQUEST            		(11)
+#define FB_ERR_LIMIT_OUT_OF_BOUNDS						(12)				
+#define FB_ERR_INVALID_LIMIT_REQUEST            		(13)
+#define FB_ERR_INVALID_FEEDBACK_OPTION          		(14)
+#define FB_ERR_UNRECOGNIZED_COMMAND             		(15)
+#define FB_HELP                                 		(16)
+
+// verbose feedback messages						
+char *msg_command_ok = 
+	"Command received";
+char *msg_err_buffer_overrun = 
+	"Error: input buffer overrun.";
+char *msg_err_input_invalid_nonletter = 
+	"Error: invalid input. Commands begin with a single letter character.";
+char *msg_err_motor_num_invalid = 
+	"Error: a required motor was not specified or specified incorrectly. Acceptable motor numbers are 0, 1, 2, and 3.";
+char *msg_err_connector_num_invalid = 
+	"Error: a required connector was not specified or specified incorrectly. Acceptable connector numbers are 0 through 12, inclusive.";
+char *msg_err_io_output = 
+	"Error: an I/O output parameter is invalid. Ensure the output value is appropriate for the type of output pin.";
+char *msg_err_connector_mode_incompatible = 
+	"Error: a specified connector is of an inappropriate mode. Verify the I/O connector is configured as necessary."; 
+char *msg_enabled_waiting_on_hlfb = 
+	"Motor enabled; waiting on HLFB to assert before accepting other commands.";
+char *msg_enable_failure = 
+	"Motor failed to enable due to motor fault, loss of power, or loss/absence of connection. Motor disabled.";
+char *msg_err_move_not_enabled = 
+	"Error: motion commanded while motor not enabled. Command e# to enable motor number #.";
+char *msg_err_move_in_alert = 
+	"Error: motion commanded while motor in fault. Command c# to clear alerts on motor number #.";
+char *msg_err_invalid_query_request = 
+	"Error: invalid query request. Command h for more information.";
+char *msg_err_limit_out_of_bounds = 
+	"Error: commanded limit falls outside the acceptable bounds for this limit.";
+char *msg_err_invalid_limit_request = 
+	"Error: invalid limit request. Command h for more information.";
+char *msg_err_invalid_feedback_option = 
+	"Error: invalid feedback request. Command h for more information.";
+char *msg_err_unrecognized_command = 
+	"Error: unrecognized command. Command h for more information.";
+char *msg_help = 
+      "ClearCore Command Protocol\n"
+      "Acceptable commands, where # specifies a motor number* (0, 1, 2, or 3): \n"
+      "    e#              | enable specified motor\n"
+      "    d#              | disable specified motor\n"
+      "    m# distance     | if(ABSOLUTE_MOVE==1) move to the specified position\n"
+      "                      if(ABSOLUTE_MOVE==0) move the specified number of steps\n"
+      "    v# velocity     | move at the specified velocity (steps/s)\n"
+      "    q#<p/v/s>       | query specified motor's position/velocity/status\n"
+      "    l#<v/a> limit   | set specified motor's velocity/acceleration limit\n"
+      "    c#              | clear alerts\n"
+      "    z#              | set the zero position for motor # to the current commanded position\n"
+	  "    i#              | read input on pin #\n"
+	  "                        Digital pins return 1 or 0; analog pins return [0,4095] corresponding to [0,10]V\n"
+	  "                        (*note that # for this command can be 0 through 5)\n"
+	  "    o# outputVal    | write output on pin #\n"
+	  "                        Digital pins allow 1 or 0; analog pins allow [409,2047] corresponding to [4,20]mA\n"
+	  "                        (*note that # for this command can be 0 through 12)\n"
+      "    f fdbkType      | specify the type of feedback printed:\n"
+      "                        0  : send message number only\n"
+      "                        1  : send verbose message\n"
+      "    h               | print this help message\n";
+
+// array of feedback messages, accessed by SendFeedback() when feedback is sent 
+FeedbackMessage FeedbackMessages[17] = {
+	{FB_COMMAND_OK					, 	msg_command_ok						},
+	{FB_ERR_BUFFER_OVERRUN          ,  	msg_err_buffer_overrun				},
+	{FB_ERR_INPUT_INVALID_NONLETTER	,   msg_err_input_invalid_nonletter		},
+	{FB_ERR_MOTOR_NUM_INVALID		, 	msg_err_motor_num_invalid			},
+	{FB_ERR_CONNECTOR_NUM_INVALID	, 	msg_err_connector_num_invalid		},
+	{FB_ERR_CONNECTOR_MODE_INCOMPATIBLE, 	
+										msg_err_connector_mode_incompatible	},
+	{FB_ENABLED_WAITING_ON_HLFB		, 	msg_enabled_waiting_on_hlfb			},
+	{FB_ENABLE_FAILURE				, 	msg_enable_failure					},
+	{FB_ERR_IO_OUTPUT				, 	msg_err_io_output					},
+	{FB_ERR_MOVE_NOT_ENABLED		, 	msg_err_move_not_enabled			},
+	{FB_ERR_MOVE_IN_ALERT           ,  	msg_err_move_in_alert				},
+	{FB_ERR_INVALID_QUERY_REQUEST   ,  	msg_err_invalid_query_request		},
+	{FB_ERR_LIMIT_OUT_OF_BOUNDS		,  	msg_err_limit_out_of_bounds			},
+	{FB_ERR_INVALID_LIMIT_REQUEST   ,  	msg_err_invalid_limit_request		},
+	{FB_ERR_INVALID_FEEDBACK_OPTION ,  	msg_err_invalid_feedback_option		},
+	{FB_ERR_UNRECOGNIZED_COMMAND    ,	msg_err_unrecognized_command		},
+	{FB_HELP                        ,  	msg_help							}
+};
+
+// global variable to select between printing only feedback number or verbose feedback message
+bool verboseFeedback = true;
+
+// macro to select between commanding absolute positional moves or relative 
+//	positional moves. See User Guide for more information.											
+#define ABSOLUTE_MOVE (1)
+
+// container for the char stream to be read-in. 
+//	allows for IN_BUFFER_LEN characters to be stored followed by a NULL terminator 
+//todo thoughts on this?
+#define IN_BUFFER_LEN 32
+char input[IN_BUFFER_LEN+1];
+
+// motor connectors
+MotorDriver *const motors[MOTOR_CON_CNT] = {
+	&ConnectorM0, &ConnectorM1, &ConnectorM2, &ConnectorM3
+};
+
+// I/O connectors
+Connector *const connectors[13] = {
+	&ConnectorIO0, &ConnectorIO1, &ConnectorIO2, &ConnectorIO3, &ConnectorIO4, &ConnectorIO5, 
+	&ConnectorDI6, &ConnectorDI7, &ConnectorDI8,
+	&ConnectorA9, &ConnectorA10, &ConnectorA11, &ConnectorA12
+};
+
+// acceleration and velocity limit bounds 
+// (note that velocity limits take effect only on positional moves)
+#define DEFAULT_ACCEL_LIMIT (100000) // pulses per sec^2
+#define MAX_ACCEL_LIMIT	(1000000000) 
+#define MIN_ACCEL_LIMIT	(1)
+#define DEFAULT_VEL_LIMIT (10000) // pulses per sec
+#define MAX_VEL_LIMIT	(500000)
+#define MIN_VEL_LIMIT	(1)
+
+// helper functions to print feedback and status information
+// the implementations of these functions are at the bottom of this example
+void SendFeedback(int32_t messageNumber);
+void SendVerboseStatus(int32_t motorNumber);
+
+
+int main() {
+
+	// configure serial communication to USB port and wait for the port to open
+	ioPort.Mode(Connector::USB_CDC);	
+	ioPort.Speed(ioPortBaudRate);
+	// ioPort.FlowControl(ioFlowControl); //only necessary if using COM ports or XBee module
+	ioPort.PortOpen();
+	while (!ioPort) {
+		continue;
+	}
+	
+	// configure input clocking rate
+	// this normal rate is ideal for ClearPath step and direction applications
+	MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+	// set all motor connectors into step and direction mode
+	MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL, Connector::CPM_MODE_STEP_AND_DIR);
+	
+	// local storage for velocity and acceleration limits
+	// (note that velocity limits only take effect on positional moves)
+	uint32_t accelerationLimits[MOTOR_CON_CNT] = { 
+		DEFAULT_ACCEL_LIMIT, DEFAULT_ACCEL_LIMIT, DEFAULT_ACCEL_LIMIT, DEFAULT_ACCEL_LIMIT
+	};
+	uint32_t velocityLimits[MOTOR_CON_CNT] = { 
+		DEFAULT_VEL_LIMIT, DEFAULT_VEL_LIMIT, DEFAULT_VEL_LIMIT, DEFAULT_VEL_LIMIT
+	};
+
+	// generic iterator
+	uint32_t i;
+	
+	// configure all motor connectors for bipolar PWM HLFB mode at 482Hz, and set 
+	//	velocity and acceleration limits
+	for (i=0; i<MOTOR_CON_CNT; i++){
+		motors[i]->HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+		motors[i]->HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+		motors[i]->VelMax(velocityLimits[i]);
+		motors[i]->AccelMax(accelerationLimits[i]);
+	}
+
+	// configure I/O pins
+	//	these defaults can be modified according to application needs
+	//	for more information and to view a list of configurable modes for each pin, 
+	//	see the ClearCore manual or the User Guide for this example
+	ConnectorIO0.Mode(Connector::OUTPUT_ANALOG );
+	ConnectorIO1.Mode(Connector::OUTPUT_DIGITAL);
+	ConnectorIO2.Mode(Connector::OUTPUT_DIGITAL);
+	ConnectorIO3.Mode(Connector::OUTPUT_DIGITAL);
+	ConnectorIO4.Mode(Connector::OUTPUT_DIGITAL);
+	ConnectorIO5.Mode(Connector::OUTPUT_DIGITAL);
+	ConnectorDI6.Mode(Connector::INPUT_DIGITAL );
+	ConnectorDI7.Mode(Connector::INPUT_DIGITAL );
+	ConnectorDI8.Mode(Connector::INPUT_DIGITAL );
+	ConnectorA9 .Mode(Connector::INPUT_ANALOG  );
+	ConnectorA10.Mode(Connector::INPUT_ANALOG  );
+	ConnectorA11.Mode(Connector::INPUT_ANALOG  );
+	ConnectorA12.Mode(Connector::INPUT_ANALOG  );
+	
+	// program control variables
+	bool inputValid;
+	bool motorNumValid;
+	bool connectorNumValid;
+	bool motorEnabledBeforeClearingAlerts;
+	
+	// parsing variables
+	int32_t motorNum_in; 
+	int32_t connectorNum_in; 
+	int32_t moveDistance_in;
+	int32_t velocity_in;
+	int32_t limit_in; 
+	int32_t queriedValue;
+	int16_t inputConnectorValue;
+	int16_t outputConnectorValue_in;
+
+	ioPort.SendLine("Setup successful");
+	ioPort.SendLine("Send 'h' to receive a list of valid commands"); 
+
+	// main loop to read and process input
+	while (true) {
+
+		// reset the input buffer by populating each index with a NULL character
+		for (i = 0; i<IN_BUFFER_LEN+1; i++){
+			input[i] = (char) NULL;
+		}
+		
+		// read and store the input character by character
+		// input buffer has a default maximum size, defined by IN_BUFFER_LEN, of 32. 
+		// if more characters are provided by the user, program will reject input.
+		inputValid = true;
+		i = 0;
+		while(i<IN_BUFFER_LEN && ioPort.CharPeek() != -1){
+			input[i] = (char) ioPort.CharGet();
+			i++;
+			Delay_ms(1);
+		}
+		
+		//-------------------------
+		// This line divides the command reading and storing section of the code from 
+		//	the command parsing section of the code. To use this protocol to accept commands
+		//	from another source than the default USB input, ensure that the command is stored
+		//	in a character array called "input" and is ready to be parsed after this line.
+		//-------------------------
+
+		// echo nonempty input when in verbose feedback mode
+		if(verboseFeedback && i!=0){
+			ioPort.SendLine(input);
+		}
+		
+		if (i==0){
+			// user did not input any characters. input invalid, but no need to report 
+			inputValid = false;
+		} else if (ioPort.CharPeek()!=-1){ 
+			// buffer overflow (there is no space left in the buffer, but there are still characters to read from ioPort)
+			// report error, reject input, and flush input stream (so the leftover characters aren't read as part of the next command)
+			SendFeedback(FB_ERR_BUFFER_OVERRUN);
+			inputValid = false;
+			while(ioPort.CharPeek()!=-1){
+				ioPort.FlushInput();
+				Delay_ms(10);
+			}
+		}
+		
+		// verify first character of command is a letter
+		if (inputValid){
+			if (('A' <= input[0] && input[0] <= 'Z') || ('a' <= input[0] && input[0] <= 'z')){
+				// if letter is uppercase, convert to lowercase
+				if ('A' <= input[0] && input[0] <= 'Z'){
+					// to convert an ASCII character from upper to lower case, add 32 to the character
+					input[0] += 32; 
+				}
+			} else {
+				// if first letter of command is not letter, reject input
+				SendFeedback(FB_ERR_INPUT_INVALID_NONLETTER);
+				inputValid = false;
+				ioPort.FlushInput();
+			}
+		}
+		
+		if (inputValid){
+
+			// store and validate motor number input from command
+			motorNum_in = atoi(&input[1]); 
+			motorNumValid = (0<=motorNum_in && motorNum_in<=3 && input[1]!=NULL);
+			
+			// store and validate connector number input from command
+			connectorNum_in = atoi(&input[1]); 
+			connectorNumValid = (0<=connectorNum_in && connectorNum_in<=12 && input[1]!=NULL);
+			
+			// status register for accessing motor status information
+			volatile const MotorDriver::StatusRegMotor &statusReg = motors[motorNum_in]->StatusReg();
+			volatile const MotorDriver::AlertRegMotor  &alertReg  = motors[motorNum_in]->AlertReg();
+
+
+			// process the command based on the command letter (first character of input)
+			switch(input[0]){
+							
+				// enable 
+				case 'e':
+					// verify motor number valid
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+					} else {
+						// enable the motor
+						motors[motorNum_in]->EnableRequest(true);
+						SendFeedback(FB_ENABLED_WAITING_ON_HLFB);
+						// wait until motor is ready before accepting other commands 
+						//	(allows any automatic homing move to complete if configured)
+						//	(loop will exit on fault during homing, or if motor is disconnected or loses power)
+						while (statusReg.bit.HlfbState != MotorDriver::HLFB_ASSERTED &&
+								!statusReg.bit.MotorInFault){
+							continue;
+						}
+						if(statusReg.bit.MotorInFault){
+							// if there is a fault while trying to enable, disable and report
+							motors[motorNum_in]->EnableRequest(false);
+							SendFeedback(FB_ENABLE_FAILURE);
+						} else {
+							SendFeedback(FB_COMMAND_OK);
+						}
+					}
+					break; 
+
+				// disable
+				case 'd':
+					// verify motor number valid
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+					} else {
+						// disable the motor
+						motors[motorNum_in]->EnableRequest(false);
+						SendFeedback(FB_COMMAND_OK);
+					}
+					break;
+					
+				// position move 
+				case 'm': 
+					// verify motor number valid, motor enabled, and no faults present
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+					} else if ( statusReg.bit.ReadyState==MotorDriver::MOTOR_DISABLED || 
+									statusReg.bit.ReadyState==MotorDriver::MOTOR_ENABLING){
+						SendFeedback(FB_ERR_MOVE_NOT_ENABLED);
+					} else if (motors[motorNum_in]->StatusReg().bit.AlertsPresent) {
+						SendFeedback(FB_ERR_MOVE_IN_ALERT);
+					} else {
+						// command the move
+						// #define ABSOLUTE_MOVE (0) commands absolute moves.
+						// #define ABSOLUTE_MOVE (1) commands relative moves.
+						// absolute moves are configured by default.
+						// See User Guide for more information.
+						moveDistance_in = atoi(&input[2]);		
+						if (ABSOLUTE_MOVE){
+							motors[motorNum_in]->Move(moveDistance_in, MotorDriver::MOVE_TARGET_ABSOLUTE);
+						} else {
+							motors[motorNum_in]->Move(moveDistance_in);
+						}				
+						SendFeedback(FB_COMMAND_OK);
+					}
+					break;
+
+				// velocity move 
+				case 'v': 
+					// verify motor number valid, motor enabled, and no faults present
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+					} else if ( statusReg.bit.ReadyState==MotorDriver::MOTOR_DISABLED ||
+									statusReg.bit.ReadyState==MotorDriver::MOTOR_ENABLING){
+						SendFeedback(FB_ERR_MOVE_NOT_ENABLED);
+					} else if (motors[motorNum_in]->StatusReg().bit.AlertsPresent) {
+						SendFeedback(FB_ERR_MOVE_IN_ALERT);
+					} else {
+						// command the move
+						velocity_in = atoi(&input[2]);
+						motors[motorNum_in]->MoveVelocity(velocity_in);
+						SendFeedback(FB_COMMAND_OK);
+					}
+					break;
+				
+				// query position, velocity, or status
+				case 'q':
+					// verify motor number valid
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+						break;
+					}
+					switch(input[2]){
+						// query commanded position 
+						case 'p':
+						case 'P':
+							// send commanded position. 
+							// this can differ from the position counter in MSP if the ClearCore 
+							//	position reference has not been synced with ClearPath's position
+							queriedValue = (int32_t) motors[motorNum_in]->PositionRefCommanded();
+							if (verboseFeedback){
+								ioPort.Send("Motor ");
+								ioPort.Send(motorNum_in);
+								ioPort.Send(" is in position (steps) ");
+							}
+							ioPort.SendLine(queriedValue);
+							break;
+							
+						// query velocity
+						case 'v':
+						case 'V':
+							// send motor velocity
+							queriedValue = motors[motorNum_in]->VelocityRefCommanded();
+							if (verboseFeedback){
+								ioPort.Send("Motor ");
+								ioPort.Send(motorNum_in);
+								ioPort.Send(" is at velocity (steps/s) ");
+							}
+							ioPort.SendLine(queriedValue);
+							break;
+							
+						// query status 
+						case 's':
+						case 'S':
+							// send motor status
+							if (verboseFeedback){
+								SendVerboseStatus(motorNum_in);
+							} else {
+								ioPort.SendLine(statusReg.reg, 2);	// prints the status register in binary
+								if (statusReg.bit.AlertsPresent){
+									ioPort.SendLine(alertReg.reg, 2); // prints the alert register in binary
+								}
+							}
+							break;
+						
+						// invalid query request
+						default:
+							SendFeedback(FB_ERR_INVALID_QUERY_REQUEST);
+					}
+					break;
+				
+				// set acceleration or velocity limit
+				case 'l': 
+					// verify motor number valid
+					if ( !motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+						break;
+					}
+					// store limit input from command
+					limit_in = atoi(&input[3]);
+					
+					switch(input[2]){
+						// velocity limit
+						case 'v':
+						case 'V':
+							//verify limit is valid, store, then propagate the change to the motor
+							if (MIN_VEL_LIMIT<=limit_in && limit_in<=MAX_VEL_LIMIT){
+								velocityLimits[motorNum_in] = limit_in;
+								motors[motorNum_in]->VelMax(velocityLimits[motorNum_in]);
+								SendFeedback(FB_COMMAND_OK);
+							} else {
+								SendFeedback(FB_ERR_LIMIT_OUT_OF_BOUNDS);
+							}
+							break;
+							
+						// acceleration limit
+						case 'a':
+						case 'A':
+							//verify limit is valid, store, then propagate the change to the motor
+							if (MIN_ACCEL_LIMIT<=limit_in && limit_in<=MAX_ACCEL_LIMIT){
+								accelerationLimits[motorNum_in] = limit_in;
+								motors[motorNum_in]->AccelMax(velocityLimits[motorNum_in]);
+								SendFeedback(FB_COMMAND_OK);
+							} else {
+								SendFeedback(FB_ERR_LIMIT_OUT_OF_BOUNDS);
+							}
+							break;
+							
+						// invalid limit request
+						default:
+							SendFeedback(FB_ERR_INVALID_LIMIT_REQUEST);
+							break;
+					}
+					break;
+
+				// clear alerts
+				case 'c':
+					// verify motor number valid
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+						break;
+					}
+					
+					// capture the current state of enable 
+					//	this value will be restored after alerts are cleared
+					motorEnabledBeforeClearingAlerts = motors[motorNum_in]->EnableRequest();
+					
+					// to clear all ClearCore alerts (which can include motor faults): 
+					//	- cycle enable if faults present (clears faults, if any)
+					//	- clear alert register (clears alerts)
+					// this command clears both ClearCore motor alerts and motor faults
+					if (statusReg.bit.MotorInFault){ 
+						motors[motorNum_in]->EnableRequest(false);
+						Delay_ms(10);
+						if(motorEnabledBeforeClearingAlerts){
+							motors[motorNum_in]->EnableRequest(true);
+						}
+					}
+					motors[motorNum_in]->ClearAlerts();
+					SendFeedback(FB_COMMAND_OK);
+					break;
+					
+				// set the zero position for motor # to the current commanded position
+				case 'z':
+					// verify motor number valid
+					if (!motorNumValid){
+						SendFeedback(FB_ERR_MOTOR_NUM_INVALID);
+						break;
+					}
+					// zero position
+					motors[motorNum_in]->PositionRefSet(0);
+					SendFeedback(FB_COMMAND_OK);
+					break;
+
+				// read input from ClearCore connector 
+				case 'i':
+					// verify connector number valid
+					if (!connectorNumValid){
+						SendFeedback(FB_ERR_CONNECTOR_NUM_INVALID);
+						break;
+					}
+					// verify connector mode valid
+					if (connectors[connectorNum_in]->Mode() != Connector::INPUT_DIGITAL && 
+						connectors[connectorNum_in]->Mode() != Connector::INPUT_ANALOG){
+						SendFeedback(FB_ERR_CONNECTOR_MODE_INCOMPATIBLE); 
+						break;
+					}
+					inputConnectorValue = connectors[connectorNum_in]->State();
+					if(verboseFeedback){
+						ioPort.Send("Connector ");
+						ioPort.Send(connectorNum_in);
+						ioPort.Send(" value: ");
+					}
+					ioPort.SendLine(inputConnectorValue);
+					break;
+				
+				
+				// write digital output to ClearCore digital output connector 
+				case 'o':
+					// verify connector number valid
+					if (!connectorNumValid){
+						SendFeedback(FB_ERR_CONNECTOR_NUM_INVALID); 
+						break;
+					}
+					// verify connector type valid
+					if (connectors[connectorNum_in]->Mode() != Connector::OUTPUT_DIGITAL && 
+						connectors[connectorNum_in]->Mode() != Connector::OUTPUT_ANALOG){
+						SendFeedback(FB_ERR_CONNECTOR_MODE_INCOMPATIBLE); 
+						break;
+					}
+					// store and write value
+					outputConnectorValue_in = atoi(&input[3]);
+					if(!connectors[connectorNum_in]->State(outputConnectorValue_in)){
+						SendFeedback(FB_ERR_IO_OUTPUT);
+					} else {
+						SendFeedback(FB_COMMAND_OK);
+					}
+					break;
+				
+				
+				// change feedback type 
+				case 'f':
+					switch(atoi(&input[1])){
+						
+						// feedback number only
+						case 0:
+							verboseFeedback = false;
+							SendFeedback(FB_COMMAND_OK);
+						break;
+						
+						// verbose feedback messages
+						case 1:
+							verboseFeedback = true;
+							SendFeedback(FB_COMMAND_OK);
+							break;
+						
+						// invalid feedback request
+						default:
+							SendFeedback(FB_ERR_INVALID_FEEDBACK_OPTION);
+						break;
+					}
+					break;
+
+				// help
+				case 'h':
+					SendFeedback(FB_HELP);
+					break;
+
+				// invalid command letter
+				default:
+					SendFeedback(FB_ERR_UNRECOGNIZED_COMMAND);
+					break;
+
+			} // switch(command letter)
+		} // if (inputValid)
+	} // while(true)
+} // main()
+
+
+/*------------------------------------------------------------------------------
+ * SendFeedback
+ *
+ *    Helper function to send feedback for specified feedback message.
+ *   
+ * Parameters:
+ *    int messageNumber	- The feedback identification number corresponding the 
+ *			feedback struct array index
+ *
+ * Returns: None (feedback message is sent directly to output)
+*/
+ void SendFeedback(int32_t messageNumber){
+	// send either the verbose message or only the message number, based on verboseFeedback bool
+	if (verboseFeedback){
+		ioPort.SendLine(FeedbackMessages[messageNumber].message);
+	} else {
+		ioPort.SendLine(FeedbackMessages[messageNumber].number);
+	}
+ } // SendFeedback()
+//------------------------------------------------------------------------------
+
+
+
+/*------------------------------------------------------------------------------
+ * SendVerboseStatus
+ *
+ *    Outputs verbose status information. 
+ *    Functionality adapted from MotorStatusRegister example project
+ *
+ * Parameters:
+ *    int motorNumber  - The motor whose status should be printed
+ *
+ * Returns: None (status message is sent directly to output)
+ */
+void SendVerboseStatus(int32_t motorNumber) {
+	// status register for accessing motor status information
+	volatile const MotorDriver::StatusRegMotor &statusReg = motors[motorNumber]->StatusReg();
+	volatile const MotorDriver::AlertRegMotor &alertReg = motors[motorNumber]->AlertReg();
+	
+	ioPort.Send("Motor status register for motor M");
+	ioPort.Send(motorNumber);
+	ioPort.Send(": ");
+	ioPort.SendLine(statusReg.reg, 2); // prints the status register in binary
+	
+	ioPort.Send("AtTargetPosition:	");
+	ioPort.SendLine(statusReg.bit.AtTargetPosition);
+
+	ioPort.Send("StepsActive:     	");
+	ioPort.SendLine(statusReg.bit.StepsActive);
+
+	ioPort.Send("AtTargetVelocity:	");
+	ioPort.SendLine(statusReg.bit.AtTargetVelocity);
+		
+	ioPort.Send("MoveDirection:   	");
+	ioPort.SendLine(statusReg.bit.MoveDirection);
+
+	ioPort.Send("MotorInFault:    	");
+	ioPort.SendLine(statusReg.bit.MotorInFault);
+
+	ioPort.Send("Enabled:         	");
+	ioPort.SendLine(statusReg.bit.Enabled);
+
+	ioPort.Send("PositionalMove:  	");
+	ioPort.SendLine(statusReg.bit.PositionalMove);
+
+	ioPort.Send("HLFB State:		");
+	switch (statusReg.bit.HlfbState) {
+		case 0:
+			ioPort.SendLine("HLFB_DEASSERTED");
+			break;
+		case 1:
+			ioPort.SendLine("HLFB_ASSERTED");
+			break;
+		case 2:
+			ioPort.SendLine("HLFB_HAS_MEASUREMENT");
+			break;
+		case 3:
+			ioPort.SendLine("HLFB_UNKNOWN");
+			break;
+		default:
+			// something has gone wrong if this is printed
+			ioPort.SendLine("???");
+	}
+
+	ioPort.Send("AlertsPresent:   	");
+	ioPort.SendLine(statusReg.bit.AlertsPresent);
+
+	ioPort.Send("Ready state:		");
+	switch (statusReg.bit.ReadyState) {
+		case MotorDriver::MOTOR_DISABLED:
+			ioPort.SendLine("Disabled");
+			break;
+		case MotorDriver::MOTOR_ENABLING:
+			ioPort.SendLine("Enabling");
+			break;
+		case MotorDriver::MOTOR_FAULTED:
+			ioPort.SendLine("Faulted");
+			break;
+		case MotorDriver::MOTOR_READY:
+			ioPort.SendLine("Ready");
+			break;
+		case MotorDriver::MOTOR_MOVING:
+			ioPort.SendLine("Moving");
+			break;
+		default:
+			// something has gone wrong if this is printed
+			ioPort.SendLine("???");
+	}
+	
+	ioPort.Send("Triggering:      	");
+	ioPort.SendLine(statusReg.bit.Triggering);
+
+	ioPort.Send("InPositiveLimit: 	");
+	ioPort.SendLine(statusReg.bit.InPositiveLimit);
+
+	ioPort.Send("InNegativeLimit: 	");
+	ioPort.SendLine(statusReg.bit.InNegativeLimit);
+
+	ioPort.Send("InEStopSensor:   	");
+	ioPort.SendLine(statusReg.bit.InEStopSensor);	
+
+	ioPort.SendLine("--------------------------------");
+	
+		
+	if (statusReg.bit.AlertsPresent){
+		ioPort.Send("Alert register:	");
+		ioPort.SendLine(alertReg.reg, 2); // prints the alert register in binary
+
+		ioPort.Send("MotionCanceledInAlert:         ");
+		ioPort.SendLine(alertReg.bit.MotionCanceledInAlert);
+
+		ioPort.Send("MotionCanceledPositiveLimit:   ");
+		ioPort.SendLine(alertReg.bit.MotionCanceledPositiveLimit);
+
+		ioPort.Send("MotionCanceledNegativeLimit:   ");
+		ioPort.SendLine(alertReg.bit.MotionCanceledNegativeLimit);
+
+		ioPort.Send("MotionCanceledSensorEStop:     ");
+		ioPort.SendLine(alertReg.bit.MotionCanceledSensorEStop);
+
+		ioPort.Send("MotionCanceledMotorDisabled:   ");
+		ioPort.SendLine(alertReg.bit.MotionCanceledMotorDisabled);
+
+		ioPort.Send("MotorFaulted:                  ");
+		ioPort.SendLine(alertReg.bit.MotorFaulted);
+
+		ioPort.SendLine("--------------------------------");
+	}
+
+
+}// SendVerboseStatus()
+//------------------------------------------------------------------------------
+
+
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol.cppproj
new file mode 100644
index 000000000..eb3ef34ce
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{0687b856-a7e3-4044-8f64-54dc5bcebd7d}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>ClearCoreCommandProtocol</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ClearCoreCommandProtocol.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol_UserGuide.pdf b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol_UserGuide.pdf
new file mode 100644
index 000000000..79a77f1d2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ClearCoreCommandProtocol/ClearCoreCommandProtocol_UserGuide.pdf
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:3fa8827741d2cc5bde4b4b225b1250693b1860d02e7ce3cd5132ae752f7d25aa
+size 130505
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ReadSerialInput/ReadSerialInput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ReadSerialInput/ReadSerialInput.cpp
new file mode 100644
index 000000000..0e2338f71
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ReadSerialInput/ReadSerialInput.cpp
@@ -0,0 +1,82 @@
+/*
+ * Title: ReadSerialInput
+ *
+ * Objective:
+ *    This example demonstrates how to read and display incoming data from a
+ *    serial port.
+ *
+ * Description:
+ *    This example will read one byte per second from the serial input buffer.
+ *    During operation, if a byte has been received, it will be printed to the
+ *    USB serial port as a character.
+ *
+ * Requirements:
+ * ** A serial input source connected to COM-0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Select the baud rate to match the target device.
+#define baudRateSerialPort 115200
+#define baudRateInputPort  115200
+
+// When using COM ports, is the device TTL or RS232?
+#define isTtlInputPort  false
+
+// Specify which serial interface to use as output.
+#define SerialPort ConnectorUsb
+
+// Specify which serial interface to use as input.
+#define InputPort ConnectorCOM0
+
+// Container for the byte to be read-in
+int16_t input;
+
+int main() {
+    // Set up serial communication to print out the serial input.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRateSerialPort);
+    SerialPort.PortOpen();
+    while (!SerialPort) {
+        continue;
+    }
+
+    // Set up serial communication to send serial input over.
+    if (isTtlInputPort) {
+        InputPort.Mode(Connector::TTL);
+    }
+    else {
+        InputPort.Mode(Connector::RS232);
+    }
+    InputPort.Speed(baudRateInputPort);
+    InputPort.PortOpen();
+    while (!InputPort) {
+        continue;
+    }
+
+    while (true) {
+        // Read the input.
+        input = InputPort.CharGet();
+
+        // If there was a valid byte read-in, print it.
+        if (input != -1) {
+            // Display the input character received.
+            SerialPort.Send("Received: ");
+            SerialPort.SendLine((char)input);
+        }
+        else {
+            SerialPort.SendLine("No data received...");
+        }
+
+        // Wait a second then repeat...
+        Delay_ms(1000);
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ReadSerialInput/ReadSerialInput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ReadSerialInput/ReadSerialInput.cppproj
new file mode 100644
index 000000000..607b58529
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/ReadSerialInput/ReadSerialInput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{2630f666-8b81-463c-8daa-f5cb4831c71b}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>ReadSerialInput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
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+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
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+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
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+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="ReadSerialInput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialCommExamples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialCommExamples.atsln
new file mode 100644
index 000000000..e11d5139a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialCommExamples.atsln
@@ -0,0 +1,64 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ReadSerialInput", "ReadSerialInput\ReadSerialInput.cppproj", "{2630F666-8B81-463C-8DAA-F5CB4831C71B}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "SerialPrint", "SerialPrint\SerialPrint.cppproj", "{3197A468-29D1-4575-9EA9-9A8E9A3E3F90}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "SpiComPortInitialization", "SpiComPortInitialization\SpiComPortInitialization.cppproj", "{8A5A00B6-E15B-4E0E-8910-EF433F51821D}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "SpiSerialDisplay", "SpiSerialDisplay\SpiSerialDisplay.cppproj", "{3A539E7C-898A-4370-AFEE-AE65D0E60C36}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "TtlSerialDisplay", "TtlSerialDisplay\TtlSerialDisplay.cppproj", "{E5B0EFC0-FE9A-4370-AD2D-6A4C4FFED11D}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCoreCommandProtocol", "ClearCoreCommandProtocol\ClearCoreCommandProtocol.cppproj", "{0687B856-A7E3-4044-8F64-54DC5BCEBD7D}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{2630F666-8B81-463C-8DAA-F5CB4831C71B}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2630F666-8B81-463C-8DAA-F5CB4831C71B}.Debug|ARM.Build.0 = Debug|ARM
+		{2630F666-8B81-463C-8DAA-F5CB4831C71B}.Release|ARM.ActiveCfg = Release|ARM
+		{2630F666-8B81-463C-8DAA-F5CB4831C71B}.Release|ARM.Build.0 = Release|ARM
+		{3197A468-29D1-4575-9EA9-9A8E9A3E3F90}.Debug|ARM.ActiveCfg = Debug|ARM
+		{3197A468-29D1-4575-9EA9-9A8E9A3E3F90}.Debug|ARM.Build.0 = Debug|ARM
+		{3197A468-29D1-4575-9EA9-9A8E9A3E3F90}.Release|ARM.ActiveCfg = Release|ARM
+		{3197A468-29D1-4575-9EA9-9A8E9A3E3F90}.Release|ARM.Build.0 = Release|ARM
+		{8A5A00B6-E15B-4E0E-8910-EF433F51821D}.Debug|ARM.ActiveCfg = Debug|ARM
+		{8A5A00B6-E15B-4E0E-8910-EF433F51821D}.Debug|ARM.Build.0 = Debug|ARM
+		{8A5A00B6-E15B-4E0E-8910-EF433F51821D}.Release|ARM.ActiveCfg = Release|ARM
+		{8A5A00B6-E15B-4E0E-8910-EF433F51821D}.Release|ARM.Build.0 = Release|ARM
+		{3A539E7C-898A-4370-AFEE-AE65D0E60C36}.Debug|ARM.ActiveCfg = Debug|ARM
+		{3A539E7C-898A-4370-AFEE-AE65D0E60C36}.Debug|ARM.Build.0 = Debug|ARM
+		{3A539E7C-898A-4370-AFEE-AE65D0E60C36}.Release|ARM.ActiveCfg = Release|ARM
+		{3A539E7C-898A-4370-AFEE-AE65D0E60C36}.Release|ARM.Build.0 = Release|ARM
+		{E5B0EFC0-FE9A-4370-AD2D-6A4C4FFED11D}.Debug|ARM.ActiveCfg = Debug|ARM
+		{E5B0EFC0-FE9A-4370-AD2D-6A4C4FFED11D}.Debug|ARM.Build.0 = Debug|ARM
+		{E5B0EFC0-FE9A-4370-AD2D-6A4C4FFED11D}.Release|ARM.ActiveCfg = Release|ARM
+		{E5B0EFC0-FE9A-4370-AD2D-6A4C4FFED11D}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{0687B856-A7E3-4044-8F64-54DC5BCEBD7D}.Debug|ARM.ActiveCfg = Debug|ARM
+		{0687B856-A7E3-4044-8F64-54DC5BCEBD7D}.Debug|ARM.Build.0 = Debug|ARM
+		{0687B856-A7E3-4044-8F64-54DC5BCEBD7D}.Release|ARM.ActiveCfg = Release|ARM
+		{0687B856-A7E3-4044-8F64-54DC5BCEBD7D}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialPrint/SerialPrint.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialPrint/SerialPrint.cpp
new file mode 100644
index 000000000..9926c4301
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialPrint/SerialPrint.cpp
@@ -0,0 +1,43 @@
+/*
+ * Title: SerialPrint
+ *
+ * Objective:
+ *    This example demonstrates how to print text using serial output.
+ *
+ * Description:
+ *    This example will print the basic "Hello World" message to the USB serial
+ *    port.
+ *
+ * Requirements:
+ * ** None
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// ClearCore provides three separate serial interfaces for communications.
+// The three options are ConnectorUsb, ConnectorCOM0, or ConnectorCOM1
+#define SerialPort ConnectorUsb
+
+// Select the baud rate to match the target device.
+#define baudRate 9600
+
+int main() {
+    // Set up serial communication to print.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    SerialPort.PortOpen();
+    while (!SerialPort) {
+        continue;
+    }
+
+    // The port is open and ready to talk.
+    SerialPort.SendLine("Hello World!");
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialPrint/SerialPrint.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialPrint/SerialPrint.cppproj
new file mode 100644
index 000000000..625fb6c55
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SerialPrint/SerialPrint.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <Name>SerialPrint</Name>
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+    <ResetRule>0</ResetRule>
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+    <AsfFrameworkConfig>
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+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
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+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
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+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
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+    <custom>
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+        </InterfaceProperties>
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+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
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+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cpp
new file mode 100644
index 000000000..60947746f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cpp
@@ -0,0 +1,72 @@
+/*
+ * Title: SpiComPortInitialization
+ *
+ * Objective:
+ *    This example demonstrates how to configure a COM port for use with an
+ *    SPI device.
+ *
+ * Description:
+ *    This example will explain the basic configuration settings of an SPI
+ *    device then perform a brief transaction with the SPI device connected to
+ *    COM-0.
+ *
+ * Requirements:
+ * ** An SPI device connected to COM-0.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Select the baud rate to match the target device.
+#define baudRate 80000
+
+// Select the clock polarity to match the target device. The clock polarity
+// setting indicates whether the device expects a low signal when idle or a
+// high signal when idle. It also indicates whether the leading or trailing
+// edge of the clock cycle are rising or falling edges.
+// Selecting SCK_LOW indicates that SCK is low when idle and the leading edge
+// of the clock cycle is a rising edge while the trailing edge is a falling
+// edge.
+// Selecting SCK_HIGH indicates that SCK is high when idle and the leading edge
+// of the clock cycle is a falling edge while the trailing edge is a rising
+// edge.
+// The default value for a COM connector's clock polarity is SCK_LOW.
+#define clockPolarity SerialDriver::SCK_LOW
+
+// Select the clock phase setting to match the target device. The clock phase
+// setting indicates whether data is sampled or changed on the leading or
+// trailing edge in the clock cycle.
+// Selecting LEAD_SAMPLE indicates that data is sampled on the leading edge and
+// changed on the trailing edge.
+// Selecting LEAD_CHANGE indicates that data is sampled on the trailing edge
+// and changed on the leading edge.
+// The default value for a COM connector's clock phase is LEAD_CHANGE.
+#define clockPhase SerialDriver::LEAD_CHANGE
+
+// Define which COM serial port connector to use: ConnectorCOM0 or ConnectorCOM1
+#define SpiPort ConnectorCOM0
+
+int main() {
+    // Configure the COM port for our SPI device then open the port.
+    SpiPort.Mode(Connector::SPI);
+    SpiPort.Speed(baudRate);
+    SpiPort.SpiClock(clockPolarity, clockPhase);
+    SpiPort.PortOpen();
+
+    // Open the SPI port on ConnectorCOM0.
+    SpiPort.SpiSsMode(SerialDriver::LINE_ON);
+    // Output some arbitrary sample data to the SPI device. This data is not
+    // required for set up, just to demonstrate the transfer process.
+    SpiPort.SpiTransferData('a');
+    SpiPort.SpiTransferData(98);
+    SpiPort.SpiTransferData(0x63);
+    // Close the port.
+    SpiPort.SpiSsMode(SerialDriver::LINE_OFF);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cppproj
new file mode 100644
index 000000000..9be001007
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
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+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="SpiComPortInitialization.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
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+  <ItemGroup>
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+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cpp
new file mode 100644
index 000000000..f9891201f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cpp
@@ -0,0 +1,152 @@
+/*
+ * Title: SpiSerialDisplay
+ *
+ * Objective:
+ *    This example demonstrates how to write data to an SPI device.
+ *
+ * Description:
+ *    This example will set up SPI communications on COM-0 then write various
+ *    data to the device.
+ *
+ * Requirements:
+ * ** A NHD-0420D3Z LCD display in SPI mode connected to COM-0
+ *    Datasheet: http://www.newhavendisplay.com/specs/NHD-0420D3Z-NSW-BBW-V3.pdf
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Data bounds of the device
+#define NUM_ROWS 4
+#define NUM_COLUMNS 20
+
+// Select the baud rate to match the target device.
+#define baudRate 80000
+
+// Select the clock polarity to match the target device. The clock polarity
+// setting indicates whether the device expects a low signal when idle or a
+// high signal when idle. It also indicates whether the leading or trailing
+// edge of the clock cycle are rising or falling edges.
+// Selecting SCK_LOW indicates that SCK is low when idle and the leading edge
+// of the clock cycle is a rising edge while the trailing edge is a falling
+// edge.
+// Selecting SCK_HIGH indicates that SCK is high when idle and the leading edge
+// of the clock cycle is a falling edge while the trailing edge is a rising
+// edge.
+// The default value for a COM connector's clock polarity is SCK_LOW.
+#define clockPolarity SerialDriver::SCK_HIGH
+
+// Select the clock phase setting to match the target device. The clock phase
+// setting indicates whether data is sampled or changed on the leading or
+// trailing edge in the clock cycle.
+// Selecting LEAD_SAMPLE indicates that data is sampled on the leading edge and
+// changed on the trailing edge.
+// Selecting LEAD_CHANGE indicates that data is sampled on the trailing edge
+// and changed on the leading edge.
+// The default value for a COM connector's clock phase is LEAD_CHANGE.
+#define clockPhase SerialDriver::LEAD_CHANGE
+
+// Define which COM serial port connector to use: ConnectorCOM0 or ConnectorCOM1
+#define SpiPort ConnectorCOM0
+
+// Sample data to write to the display
+const uint8_t line1[21] = "abcdefghijklmnopqrst";
+const uint8_t line2[21] = "ABCDEFGHIJKLMNOPQRST";
+const uint8_t line3[21] = "01234567890123456789";
+const uint8_t line4[21] = "98765432109876543210";
+
+// Declare our helper functions so that they may be used before they are defined
+void SetBrightness(uint8_t level);
+void SetCursor(uint8_t row, uint8_t column);
+
+int main() {
+    // Configure the COM port for our SPI device then open the port.
+    SpiPort.Mode(Connector::SPI);
+    SpiPort.Speed(baudRate);
+    SpiPort.DataOrder(SerialDriver::COM_MSB_FIRST);
+    SpiPort.SpiClock(clockPolarity, clockPhase);
+    SpiPort.PortOpen();
+
+    // The COM port is now configured and ready to send commands and
+    // data to the display.
+
+    // Set the display brightness level.
+    // The maximum value for full brightness is 8.
+    SetBrightness(4);
+
+    // Set the cursor position to the top-left corner.
+    SetCursor(0, 0);
+
+    // Open the SPI port on ConnectorCOM0.
+    SpiPort.SpiSsMode(SerialDriver::LINE_ON);
+
+    // Send the lines "out of order" (1, 3, 2, 4) to the display.
+    // Without resetting the cursor position for each line, this is the order
+    // in which lines must be sent to be displayed correctly.
+    SpiPort.SpiTransferData(line1, NULL, 20);
+    SpiPort.SpiTransferData(line3, NULL, 20);
+    SpiPort.SpiTransferData(line2, NULL, 20);
+    SpiPort.SpiTransferData(line4, NULL, 20);
+
+    // Close the port.
+    SpiPort.SpiSsMode(SerialDriver::LINE_OFF);
+}
+
+/*------------------------------------------------------------------------------
+ * SetBrightness
+ *
+ *    Sends a short SPI transaction to control the brightness of the attached
+ *    LCD screen. See the device's datasheet for a full set of commands and
+ *    syntax.
+ *
+ * Parameters:
+ *    uint8_t level  - The brightness level to be set
+ *
+ * Returns: None
+ */
+void SetBrightness(uint8_t level) {
+    SpiPort.SpiSsMode(SerialDriver::LINE_ON);
+    SpiPort.SpiTransferData(0xfe);
+    SpiPort.SpiTransferData(0x53);
+    SpiPort.SpiTransferData(level);
+    SpiPort.SpiSsMode(SerialDriver::LINE_OFF);
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * SetCursor
+ *
+ *    Sends a short SPI transaction to control the position of the device's
+ *    internal cursor that controls where characters are printed on the LCD
+ *    screen. See the device's datasheet for a full set of commands and syntax.
+ *
+ * Parameters:
+ *    uint8_t row  - The character row to move the cursor to.
+ *    uint8_t column  - The character column to move the cursor to.
+ *
+ * Returns: None
+ */
+void SetCursor(uint8_t row, uint8_t column) {
+    // Bounds-check the passed-in row and column
+    if (row >= NUM_ROWS) {
+        row = 0;
+    }
+    if (column >= NUM_COLUMNS) {
+        column = 0;
+    }
+
+    uint8_t position = row * NUM_COLUMNS + column;
+    SpiPort.SpiSsMode(SerialDriver::LINE_ON);
+    SpiPort.SpiTransferData(0xfe);
+    SpiPort.SpiTransferData(0x45);
+    SpiPort.SpiTransferData(position);
+    SpiPort.SpiSsMode(SerialDriver::LINE_OFF);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cppproj
new file mode 100644
index 000000000..7ee96a6e9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
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+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
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+    <Compile Include="SpiSerialDisplay.cpp">
+      <SubType>compile</SubType>
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cpp
new file mode 100644
index 000000000..c3b992b0b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cpp
@@ -0,0 +1,117 @@
+/*
+ * Title: TtlSerialDisplay
+ *
+ * Objective:
+ *    This example demonstrates how to write data to a TTL device.
+ *
+ * Description:
+ *    This example will set up TTL communications on COM-0 then write various
+ *    data to the device.
+ *
+ * Requirements:
+ * ** A NHD-0420D3Z LCD display in TTL mode connected to COM-0.
+ *    Datasheet: http://www.newhavendisplay.com/specs/NHD-0420D3Z-NSW-BBW-V3.pdf
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Data bounds of the device
+#define NUM_ROWS 4
+#define NUM_COLUMNS 20
+
+// Select the baud rate to match the target device.
+#define baudRate 57600
+
+// Specify which serial to use: ConnectorCOM0 or ConnectorCOM1
+#define SerialPort ConnectorCOM0
+
+// Sample data to write to the display
+const uint8_t line1[21] = "abcdefghijklmnopqrst";
+const uint8_t line2[21] = "ABCDEFGHIJKLMNOPQRST";
+const uint8_t line3[21] = "01234567890123456789";
+const uint8_t line4[21] = "98765432109876543210";
+
+// Declare our helper functions so that they may be used before they are defined
+void SetBrightness(uint8_t level);
+void SetCursor(uint8_t row, uint8_t column);
+
+int main() {
+    SerialPort.Mode(Connector::TTL);
+    SerialPort.Speed(baudRate);
+    SerialPort.PortOpen();
+
+    // The COM port is now configured and ready to send commands and
+    // data to the display.
+
+    // Set the display brightness level.
+    // The maximum value for full brightness is 8.
+    SetBrightness(4);
+
+    // Set the cursor position to the top-left corner.
+    SetCursor(0, 0);
+
+    // Send the lines "out of order" (1, 3, 2, 4) to the display.
+    // Without resetting the cursor position for each line, this is the order
+    // in which lines must be sent to be displayed correctly.
+    SerialPort.Send((char *)line1);
+    SerialPort.Send((char *)line3);
+    SerialPort.Send((char *)line2);
+    SerialPort.Send((char *)line4);
+}
+
+/*------------------------------------------------------------------------------
+ * SetBrightness
+ *
+ *    Sends a short group of data to control the brightness of the attached
+ *    LCD screen. See the device's datasheet for a full set of commands and
+ *    syntax.
+ *
+ * Parameters:
+ *    uint8_t level  - The brightness level to be set
+ *
+ * Returns: None
+ */
+void SetBrightness(uint8_t level) {
+    SerialPort.SendChar(0xfe);
+    SerialPort.SendChar(0x53);
+    SerialPort.SendChar(level);
+}
+//------------------------------------------------------------------------------
+
+/*------------------------------------------------------------------------------
+ * SetCursor
+ *
+ *    Sends a short group of data to control the position of the device's
+ *    internal cursor that controls where characters are printed on the LCD
+ *    screen. See the device's datasheet for a full set of commands and syntax.
+ *
+ * Parameters:
+ *    uint8_t row  - The character row to move the cursor to.
+ *    uint8_t column  - The character column to move the cursor to.
+ *
+ * Returns: None
+ */
+void SetCursor(uint8_t row, uint8_t column) {
+    // Bounds-check the passed-in row and column
+    if (row >= NUM_ROWS) {
+        row = 0;
+    }
+
+    if (column >= NUM_COLUMNS) {
+        column = 0;
+    }
+
+    uint8_t position = row * NUM_COLUMNS + column;
+    SerialPort.SendChar(0xfe);
+    SerialPort.SendChar(0x45);
+    SerialPort.SendChar(position);
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cppproj
new file mode 100644
index 000000000..7de98ef01
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cppproj
@@ -0,0 +1,279 @@
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+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="TtlSerialDisplay.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionExamplesNonClearPath.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionExamplesNonClearPath.atsln
new file mode 100644
index 000000000..8a0284ec3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionExamplesNonClearPath.atsln
@@ -0,0 +1,34 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "StepAndDirection (non-ClearPath)", "StepAndDirectionNonClearPath\StepAndDirectionNonClearPath.cppproj", "{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Debug|ARM.ActiveCfg = Debug|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Debug|ARM.Build.0 = Debug|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Release|ARM.ActiveCfg = Release|ARM
+		{92CA1B77-8EFE-4ED5-A822-E17D8B8BD833}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
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+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
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+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirection.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirection.cpp
new file mode 100644
index 000000000..d6d9da33c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirection.cpp
@@ -0,0 +1,138 @@
+/*
+ * Title: StepAndDirection
+ *
+ * Objective:
+ *    This example demonstrates control of a third party Step and
+ *    Direction motor using a ClearCore motor connector.
+ *    This example is NOT intended to be used with ClearPath servos.
+ *    There are other examples created specifically for ClearPath.
+ *
+ * Description:
+ *    This example enables a motor then commands a series of repeating
+ *    moves to the motor.
+ *
+ * Requirements:
+ * 1. A motor capable of step and direction must be connected to Connector M-0.
+ * 2. The motor may optionally be connected to the MotorDriver's HLFB line if
+ *    the motor has a "servo on" type feedback feature.
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * 
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// Specifies which motor to move.
+// Options are: ConnectorM0, ConnectorM1, ConnectorM2, or ConnectorM3.
+#define motor ConnectorM0
+
+// Select the baud rate to match the target serial device
+#define baudRate 9600
+
+// Specify which serial to use: ConnectorUsb, ConnectorCOM0, or ConnectorCOM1.
+#define SerialPort ConnectorUsb
+
+// Define the velocity and acceleration limits to be used for each move
+int32_t velocityLimit = 10000; // pulses per sec
+int32_t accelerationLimit = 100000; // pulses per sec^2
+
+// Declares our user-defined helper function, which is used to command moves to
+// the motor. The definition/implementation of this function is at the  bottom
+// of the example.
+void MoveDistance(int32_t distance);
+
+int main() {
+    // Sets the input clocking rate.
+    MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+
+    // Sets all motor connectors into step and direction mode.
+    MotorMgr.MotorModeSet(MotorManager::MOTOR_ALL,
+                          Connector::CPM_MODE_STEP_AND_DIR);
+
+    // These lines may be uncommented to invert the output signals of the
+    // Enable, Direction, and HLFB lines. Some motors may have input polarities
+    // that are inverted from the ClearCore's polarity.
+    //motor.PolarityInvertSDEnable(true);
+    //motor.PolarityInvertSDDirection(true);
+    //motor.PolarityInvertSDHlfb(true);
+
+    // Sets the maximum velocity for each move
+    motor.VelMax(velocityLimit);
+
+    // Set the maximum acceleration for each move
+    motor.AccelMax(accelerationLimit);
+
+    // Sets up serial communication and waits up to 5 seconds for a port to open.
+    // Serial communication is not required for this example to run.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(baudRate);
+    uint32_t timeout = 5000;
+    uint32_t startTime = Milliseconds();
+    SerialPort.PortOpen();
+    while (!SerialPort && Milliseconds() - startTime < timeout) {
+        continue;
+    }
+
+    // Enables the motor.
+    motor.EnableRequest(true);
+
+    // Waits for HLFB to assert. Uncomment these lines if your motor has a
+    // "servo on" feature and it is wired to the HLFB line on the connector.
+    //SerialPort.SendLine("Waiting for HLFB...");
+    //while (motor.HlfbState() != MotorDriver::HLFB_ASSERTED) {
+    //    continue;
+    //}
+    SerialPort.SendLine("Motor Ready");
+
+    while (true) {
+        // Move 6400 counts (positive direction), then wait 2000ms
+        MoveDistance(6400);
+        Delay_ms(2000);
+        // Move 19200 counts farther positive, then wait 2000ms
+        MoveDistance(19200);
+        Delay_ms(2000);
+        // Move back 12800 counts (negative direction), then wait 2000ms
+        MoveDistance(-12800);
+        Delay_ms(2000);
+        // Move back 6400 counts (negative direction), then wait 2000ms
+        MoveDistance(-6400);
+        Delay_ms(2000);
+        // Move back to the start (negative 6400 pulses), then wait 2000ms
+        MoveDistance(-6400);
+        Delay_ms(2000);
+    }
+}
+
+/*------------------------------------------------------------------------------
+ * MoveDistance
+ *
+ *    Command "distance" number of step pulses away from the current position
+ *    Prints the move status to the USB serial port
+ *    Returns when step pulses have completed
+ *
+ * Parameters:
+ *    int distance  - The distance, in step pulses, to move
+ *
+ * Returns: None
+ */
+void MoveDistance(int32_t distance) {
+    SerialPort.Send("Moving distance: ");
+    SerialPort.SendLine(distance);
+
+    // Command the move of incremental distance
+    motor.Move(distance);
+
+    // Waits for all step pulses to output
+    SerialPort.SendLine("Moving... Waiting for the step output to finish...");
+    while (!motor.StepsComplete()) {
+        continue;
+    }
+
+    SerialPort.SendLine("Steps Complete");
+}
+//------------------------------------------------------------------------------
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirectionNonClearPath.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirectionNonClearPath.cppproj
new file mode 100644
index 000000000..2c2bfd643
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirectionNonClearPath.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{92ca1b77-8efe-4ed5-a822-e17d8b8bd833}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>StepAndDirection (non-ClearPath)</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
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+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
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+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
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+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
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+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
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+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
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+            <Value>../../../../libClearCore/inc</Value>
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+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
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+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
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+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
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+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
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+        </armgcccpp.linker.libraries.LibrarySearchPaths>
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+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
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+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="StepAndDirection.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..6145690bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/Device_Startup/startup_same53.c
@@ -0,0 +1,505 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+            continue;
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/WriteXBeeOutput/WriteXbeeOutput.cpp b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/WriteXBeeOutput/WriteXbeeOutput.cpp
new file mode 100644
index 000000000..f0fd55511
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/WriteXBeeOutput/WriteXbeeOutput.cpp
@@ -0,0 +1,67 @@
+/*
+ * Title: WriteXBeeOutput
+ *
+ * Objective:
+ *    This example demonstrates how to write data to an XBee device connected to
+ *    the ClearCore's XBee port.
+ *
+ * Description:   
+ *    This example sets up the XBee connector and writes data to the XBee 
+ *    device. Any data received is then read-in and written to the USB serial 
+ *    port.
+ *
+ * Requirements:
+ * ** An XBee device connected to ClearCore's XBee connector. Use the XBee in 
+ *    Transparent Mode to simply send and receive data without packet structuring.
+ * ** Another remote XBee, also in transparent mode and configured to communicate 
+ *    with the first.  
+ *
+ * Links:
+ * ** ClearCore Documentation: https://teknic-inc.github.io/ClearCore-library/
+ * ** ClearCore Manual: https://www.teknic.com/files/downloads/clearcore_user_manual.pdf
+ *
+ * Last Modified: 1/21/2020
+ * Copyright (c) 2020 Teknic Inc. This work is free to use, copy and distribute under the terms of
+ * the standard MIT permissive software license which can be found at https://opensource.org/licenses/MIT
+ */
+
+#include "ClearCore.h"
+
+// ClearCore provides three separate serial interfaces to send communications.
+// The three options are ConnectorUsb, ConnectorCOM0, or ConnectorCOM1
+#define SerialPort ConnectorUsb
+
+// Select the baud rate to match the target device.
+#define serialBaudRate 9600
+
+int main() {
+    // Put your setup code here, it will run once:
+
+    // Set up serial communication to print.
+    // A port must be open to continue and view incoming data.
+    // Set up serial communication to print.
+    SerialPort.Mode(Connector::USB_CDC);
+    SerialPort.Speed(serialBaudRate);
+    SerialPort.PortOpen();
+    while (!SerialPort) {
+        continue;
+    }
+
+    //Uncomment the line below if you have turned RTS flow control on in the XBee's parameters
+    //XBee.FlowControl(true);
+
+    // Set the XBee communication speed and open the XBee port
+    XBee.Speed(115200);
+    XBee.PortOpen();
+
+    // Send a message to the XBee.
+    XBee.Send("Hello XBee");
+
+    while (true) {
+        // As long as there are characters to be read-in, print the character at the
+        // top of the receive buffer.
+        if (XBee.AvailableForRead()) {
+            SerialPort.SendLine(XBee.CharGet());
+        }
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/WriteXBeeOutput/WriteXbeeOutput.cppproj b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/WriteXBeeOutput/WriteXbeeOutput.cppproj
new file mode 100644
index 000000000..61d9a95df
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/WriteXBeeOutput/WriteXbeeOutput.cppproj
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{8481377d-e2f1-4293-9aba-44a8d3b0c8e3}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>Examples</AssemblyName>
+    <Name>WriteXBeeOutput</Name>
+    <RootNamespace>Examples</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+        <options />
+        <configurations />
+        <files />
+        <documentation help="" />
+        <offline-documentation help="" />
+        <dependencies>
+          <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.39.0" />
+        </dependencies>
+      </framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\..\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+    <com_atmel_avrdbg_tool_samice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.samice</ToolType>
+      <ToolNumber>504501883</ToolNumber>
+      <ToolName>J-Link</ToolName>
+    </com_atmel_avrdbg_tool_samice>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>NDEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+        <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+        <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+        <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+        <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+        <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+        <armgcc.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcc.compiler.symbols.DefSymbols>
+        <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+        <armgcc.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcc.compiler.directories.IncludePaths>
+        <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+        <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+        <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+        <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+        <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+        <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu99 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.compiler.symbols.DefSymbols>
+          <ListValues>
+            <Value>DEBUG</Value>
+          </ListValues>
+        </armgcccpp.compiler.symbols.DefSymbols>
+        <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+        <armgcccpp.compiler.directories.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>../../../../libClearCore/inc</Value>
+            <Value>../../../../LwIP/LwIP/src/include</Value>
+            <Value>../../../../LwIP/LwIP/port/include</Value>
+          </ListValues>
+        </armgcccpp.compiler.directories.IncludePaths>
+        <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+        <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+        <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+        <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+        <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+        <armgcccpp.compiler.miscellaneous.OtherFlags>-mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+        <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+        <armgcccpp.linker.libraries.Libraries>
+          <ListValues>
+            <Value>libm</Value>
+            <Value>arm_cortexM4lf_math</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.Libraries>
+        <armgcccpp.linker.libraries.LibrarySearchPaths>
+          <ListValues>
+            <Value>../../Device_Startup</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+          </ListValues>
+        </armgcccpp.linker.libraries.LibrarySearchPaths>
+        <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+        <armgcccpp.linker.memorysettings.ExternalRAM />
+        <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+        <armgcccpp.assembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.assembler.general.IncludePaths>
+        <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+        <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+        <armgcccpp.preprocessingassembler.general.IncludePaths>
+          <ListValues>
+            <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+            <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+          </ListValues>
+        </armgcccpp.preprocessingassembler.general.IncludePaths>
+        <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+      </ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="..\Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\startup_same53.c</Link>
+    </Compile>
+    <Compile Include="WriteXBeeOutput.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="..\Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_without_bootloader.ld</Link>
+    </None>
+    <None Include="..\Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+      <Link>Device_Startup\flash_with_bootloader.ld</Link>
+    </None>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/XBeeExamples.atsln b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/XBeeExamples.atsln
new file mode 100644
index 000000000..4e34a3879
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Microchip_Examples/XBeeExamples/XBeeExamples.atsln
@@ -0,0 +1,34 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "WriteXbeeOutput", "WriteXbeeOutput\WriteXBeeOutput.cppproj", "{8481377D-E2F1-4293-9ABA-44A8D3B0C8E3}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+		{8481377D-E2F1-4293-9ABA-44A8D3B0C8E3}.Debug|ARM.ActiveCfg = Debug|ARM
+		{8481377D-E2F1-4293-9ABA-44A8D3B0C8E3}.Debug|ARM.Build.0 = Debug|ARM
+		{8481377D-E2F1-4293-9ABA-44A8D3B0C8E3}.Release|ARM.ActiveCfg = Release|ARM
+		{8481377D-E2F1-4293-9ABA-44A8D3B0C8E3}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/flash_with_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/flash_with_bootloader.ld
new file mode 100644
index 000000000..6e8ea0a74
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/flash_with_bootloader.ld
@@ -0,0 +1,217 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000+0x4000, LENGTH = 0x80000-0x4000 /* First 16KB used by bootloader */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		KEEP(*(.sketch_boot))
+
+		. = ALIGN(0x4000);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/flash_without_bootloader.ld b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/flash_without_bootloader.ld
new file mode 100644
index 000000000..a114cd1db
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/flash_without_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+  Copyright (c) 2014-2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x30000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __ram_end__
+ */
+ENTRY(Reset_Handler)
+EXTERN(exception_table)
+
+SECTIONS
+{
+	.text :
+	{
+		__text_start__ = .;
+
+		. = ALIGN(4);
+		KEEP(*(.vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(16);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	__ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/startup_same53.c b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/startup_same53.c
new file mode 100644
index 000000000..23d94fce6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/Device_Startup/startup_same53.c
@@ -0,0 +1,504 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAME53
+ *
+ * Copyright (c) 2019 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "same53.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t __StackTop;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NonMaskableInt_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManagement_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVCall_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMonitor_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MCLK_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void OSCCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+void OSCCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+void OSCCTRL_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+void OSCCTRL_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+void OSCCTRL_4_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+void OSC32KCTRL_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SUPC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+void SUPC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */
+void EIC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */
+void EIC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */
+void EIC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */
+void EIC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */
+void EIC_5_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */
+void EIC_6_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */
+void EIC_7_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */
+void EIC_8_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */
+void EIC_9_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */
+void EIC_10_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */
+void EIC_11_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */
+void EIC_12_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */
+void EIC_13_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */
+void EIC_14_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */
+void EIC_15_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */
+void FREQM_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+void NVMCTRL_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+void DMAC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+void DMAC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+void DMAC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+void DMAC_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+void DMAC_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+void EVSYS_0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */
+void EVSYS_1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */
+void EVSYS_2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */
+void EVSYS_3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */
+void EVSYS_4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+void PAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RAMECC_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */
+void SERCOM0_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */
+void SERCOM0_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */
+void SERCOM0_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+void SERCOM1_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */
+void SERCOM1_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */
+void SERCOM1_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */
+void SERCOM1_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+void SERCOM2_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */
+void SERCOM2_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */
+void SERCOM2_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */
+void SERCOM2_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+void SERCOM3_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */
+void SERCOM3_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */
+void SERCOM3_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */
+void SERCOM3_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+void SERCOM4_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */
+void SERCOM4_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */
+void SERCOM4_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */
+void SERCOM4_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */
+void SERCOM5_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */
+void SERCOM5_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */
+void SERCOM5_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#endif
+#ifdef ID_SERCOM6
+void SERCOM6_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */
+void SERCOM6_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */
+void SERCOM6_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */
+void SERCOM6_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#endif
+#ifdef ID_SERCOM7
+void SERCOM7_0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */
+void SERCOM7_1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */
+void SERCOM7_2_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */
+void SERCOM7_3_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#endif
+#ifdef ID_CAN0
+void CAN0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_CAN1
+void CAN1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_USB
+void USB_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+void USB_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */
+void USB_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+void USB_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#endif
+#ifdef ID_GMAC
+void GMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+void TCC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */
+void TCC0_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */
+void TCC0_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */
+void TCC0_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */
+void TCC0_5_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */
+void TCC0_6_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */
+void TCC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+void TCC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */
+void TCC1_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */
+void TCC1_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */
+void TCC1_4_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */
+void TCC2_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+void TCC2_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */
+void TCC2_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */
+void TCC2_3_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */
+#ifdef ID_TCC3
+void TCC3_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+void TCC3_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */
+void TCC3_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */
+#endif
+#ifdef ID_TCC4
+void TCC4_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+void TCC4_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */
+void TCC4_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */
+#endif
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC4
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC5
+void TC5_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC6
+void TC6_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PDEC_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+void PDEC_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */
+void PDEC_2_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */
+void ADC0_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */
+void ADC0_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */
+void ADC1_0_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */
+void ADC1_1_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+void DAC_1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */
+void DAC_2_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */
+void DAC_3_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */
+void DAC_4_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */
+#ifdef ID_I2S
+void I2S_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void PCC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ICM
+void ICM_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PUKCC
+void PUKCC_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void QSPI_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SDHC0
+void SDHC0_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SDHC1
+void SDHC1_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+        /* Configure Initial Stack Pointer, using linker-generated symbols */
+        .pvStack                = (void*) (&__StackTop),
+
+        .pfnReset_Handler       = (void*) Reset_Handler,
+        .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
+        .pfnHardFault_Handler   = (void*) HardFault_Handler,
+        .pfnMemManagement_Handler = (void*) MemManagement_Handler,
+        .pfnBusFault_Handler    = (void*) BusFault_Handler,
+        .pfnUsageFault_Handler  = (void*) UsageFault_Handler,
+        .pvReservedM9           = (void*) (0UL), /* Reserved */
+        .pvReservedM8           = (void*) (0UL), /* Reserved */
+        .pvReservedM7           = (void*) (0UL), /* Reserved */
+        .pvReservedM6           = (void*) (0UL), /* Reserved */
+        .pfnSVCall_Handler      = (void*) SVCall_Handler,
+        .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
+        .pvReservedM3           = (void*) (0UL), /* Reserved */
+        .pfnPendSV_Handler      = (void*) PendSV_Handler,
+        .pfnSysTick_Handler     = (void*) SysTick_Handler,
+
+        /* Configurable interrupts */
+        .pfnPM_Handler          = (void*) PM_Handler,             /*  0 Power Manager */
+        .pfnMCLK_Handler        = (void*) MCLK_Handler,           /*  1 Main Clock */
+        .pfnOSCCTRL_0_Handler   = (void*) OSCCTRL_0_Handler,      /*  2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
+        .pfnOSCCTRL_1_Handler   = (void*) OSCCTRL_1_Handler,      /*  3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
+        .pfnOSCCTRL_2_Handler   = (void*) OSCCTRL_2_Handler,      /*  4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
+        .pfnOSCCTRL_3_Handler   = (void*) OSCCTRL_3_Handler,      /*  5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
+        .pfnOSCCTRL_4_Handler   = (void*) OSCCTRL_4_Handler,      /*  6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
+        .pfnOSC32KCTRL_Handler  = (void*) OSC32KCTRL_Handler,     /*  7 32kHz Oscillators Control */
+        .pfnSUPC_0_Handler      = (void*) SUPC_0_Handler,         /*  8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
+        .pfnSUPC_1_Handler      = (void*) SUPC_1_Handler,         /*  9 SUPC_BOD12DET, SUPC_BOD33DET */
+        .pfnWDT_Handler         = (void*) WDT_Handler,            /* 10 Watchdog Timer */
+        .pfnRTC_Handler         = (void*) RTC_Handler,            /* 11 Real-Time Counter */
+        .pfnEIC_0_Handler       = (void*) EIC_0_Handler,          /* 12 EIC_EXTINT_0 */
+        .pfnEIC_1_Handler       = (void*) EIC_1_Handler,          /* 13 EIC_EXTINT_1 */
+        .pfnEIC_2_Handler       = (void*) EIC_2_Handler,          /* 14 EIC_EXTINT_2 */
+        .pfnEIC_3_Handler       = (void*) EIC_3_Handler,          /* 15 EIC_EXTINT_3 */
+        .pfnEIC_4_Handler       = (void*) EIC_4_Handler,          /* 16 EIC_EXTINT_4 */
+        .pfnEIC_5_Handler       = (void*) EIC_5_Handler,          /* 17 EIC_EXTINT_5 */
+        .pfnEIC_6_Handler       = (void*) EIC_6_Handler,          /* 18 EIC_EXTINT_6 */
+        .pfnEIC_7_Handler       = (void*) EIC_7_Handler,          /* 19 EIC_EXTINT_7 */
+        .pfnEIC_8_Handler       = (void*) EIC_8_Handler,          /* 20 EIC_EXTINT_8 */
+        .pfnEIC_9_Handler       = (void*) EIC_9_Handler,          /* 21 EIC_EXTINT_9 */
+        .pfnEIC_10_Handler      = (void*) EIC_10_Handler,         /* 22 EIC_EXTINT_10 */
+        .pfnEIC_11_Handler      = (void*) EIC_11_Handler,         /* 23 EIC_EXTINT_11 */
+        .pfnEIC_12_Handler      = (void*) EIC_12_Handler,         /* 24 EIC_EXTINT_12 */
+        .pfnEIC_13_Handler      = (void*) EIC_13_Handler,         /* 25 EIC_EXTINT_13 */
+        .pfnEIC_14_Handler      = (void*) EIC_14_Handler,         /* 26 EIC_EXTINT_14 */
+        .pfnEIC_15_Handler      = (void*) EIC_15_Handler,         /* 27 EIC_EXTINT_15 */
+        .pfnFREQM_Handler       = (void*) FREQM_Handler,          /* 28 Frequency Meter */
+        .pfnNVMCTRL_0_Handler   = (void*) NVMCTRL_0_Handler,      /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
+        .pfnNVMCTRL_1_Handler   = (void*) NVMCTRL_1_Handler,      /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
+        .pfnDMAC_0_Handler      = (void*) DMAC_0_Handler,         /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
+        .pfnDMAC_1_Handler      = (void*) DMAC_1_Handler,         /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
+        .pfnDMAC_2_Handler      = (void*) DMAC_2_Handler,         /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
+        .pfnDMAC_3_Handler      = (void*) DMAC_3_Handler,         /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
+        .pfnDMAC_4_Handler      = (void*) DMAC_4_Handler,         /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
+        .pfnEVSYS_0_Handler     = (void*) EVSYS_0_Handler,        /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */
+        .pfnEVSYS_1_Handler     = (void*) EVSYS_1_Handler,        /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */
+        .pfnEVSYS_2_Handler     = (void*) EVSYS_2_Handler,        /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */
+        .pfnEVSYS_3_Handler     = (void*) EVSYS_3_Handler,        /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */
+        .pfnEVSYS_4_Handler     = (void*) EVSYS_4_Handler,        /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
+        .pfnPAC_Handler         = (void*) PAC_Handler,            /* 41 Peripheral Access Controller */
+        .pvReserved42           = (void*) (0UL),                  /* 42 Reserved */
+        .pvReserved43           = (void*) (0UL),                  /* 43 Reserved */
+        .pvReserved44           = (void*) (0UL),                  /* 44 Reserved */
+        .pfnRAMECC_Handler      = (void*) RAMECC_Handler,         /* 45 RAM ECC */
+        .pfnSERCOM0_0_Handler   = (void*) SERCOM0_0_Handler,      /* 46 SERCOM0_0 */
+        .pfnSERCOM0_1_Handler   = (void*) SERCOM0_1_Handler,      /* 47 SERCOM0_1 */
+        .pfnSERCOM0_2_Handler   = (void*) SERCOM0_2_Handler,      /* 48 SERCOM0_2 */
+        .pfnSERCOM0_3_Handler   = (void*) SERCOM0_3_Handler,      /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
+        .pfnSERCOM1_0_Handler   = (void*) SERCOM1_0_Handler,      /* 50 SERCOM1_0 */
+        .pfnSERCOM1_1_Handler   = (void*) SERCOM1_1_Handler,      /* 51 SERCOM1_1 */
+        .pfnSERCOM1_2_Handler   = (void*) SERCOM1_2_Handler,      /* 52 SERCOM1_2 */
+        .pfnSERCOM1_3_Handler   = (void*) SERCOM1_3_Handler,      /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
+        .pfnSERCOM2_0_Handler   = (void*) SERCOM2_0_Handler,      /* 54 SERCOM2_0 */
+        .pfnSERCOM2_1_Handler   = (void*) SERCOM2_1_Handler,      /* 55 SERCOM2_1 */
+        .pfnSERCOM2_2_Handler   = (void*) SERCOM2_2_Handler,      /* 56 SERCOM2_2 */
+        .pfnSERCOM2_3_Handler   = (void*) SERCOM2_3_Handler,      /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
+        .pfnSERCOM3_0_Handler   = (void*) SERCOM3_0_Handler,      /* 58 SERCOM3_0 */
+        .pfnSERCOM3_1_Handler   = (void*) SERCOM3_1_Handler,      /* 59 SERCOM3_1 */
+        .pfnSERCOM3_2_Handler   = (void*) SERCOM3_2_Handler,      /* 60 SERCOM3_2 */
+        .pfnSERCOM3_3_Handler   = (void*) SERCOM3_3_Handler,      /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
+#ifdef ID_SERCOM4
+        .pfnSERCOM4_0_Handler   = (void*) SERCOM4_0_Handler,      /* 62 SERCOM4_0 */
+        .pfnSERCOM4_1_Handler   = (void*) SERCOM4_1_Handler,      /* 63 SERCOM4_1 */
+        .pfnSERCOM4_2_Handler   = (void*) SERCOM4_2_Handler,      /* 64 SERCOM4_2 */
+        .pfnSERCOM4_3_Handler   = (void*) SERCOM4_3_Handler,      /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
+#else
+        .pvReserved62           = (void*) (0UL),                  /* 62 Reserved */
+        .pvReserved63           = (void*) (0UL),                  /* 63 Reserved */
+        .pvReserved64           = (void*) (0UL),                  /* 64 Reserved */
+        .pvReserved65           = (void*) (0UL),                  /* 65 Reserved */
+#endif
+#ifdef ID_SERCOM5
+        .pfnSERCOM5_0_Handler   = (void*) SERCOM5_0_Handler,      /* 66 SERCOM5_0 */
+        .pfnSERCOM5_1_Handler   = (void*) SERCOM5_1_Handler,      /* 67 SERCOM5_1 */
+        .pfnSERCOM5_2_Handler   = (void*) SERCOM5_2_Handler,      /* 68 SERCOM5_2 */
+        .pfnSERCOM5_3_Handler   = (void*) SERCOM5_3_Handler,      /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
+#else
+        .pvReserved66           = (void*) (0UL),                  /* 66 Reserved */
+        .pvReserved67           = (void*) (0UL),                  /* 67 Reserved */
+        .pvReserved68           = (void*) (0UL),                  /* 68 Reserved */
+        .pvReserved69           = (void*) (0UL),                  /* 69 Reserved */
+#endif
+#ifdef ID_SERCOM6
+        .pfnSERCOM6_0_Handler   = (void*) SERCOM6_0_Handler,      /* 70 SERCOM6_0 */
+        .pfnSERCOM6_1_Handler   = (void*) SERCOM6_1_Handler,      /* 71 SERCOM6_1 */
+        .pfnSERCOM6_2_Handler   = (void*) SERCOM6_2_Handler,      /* 72 SERCOM6_2 */
+        .pfnSERCOM6_3_Handler   = (void*) SERCOM6_3_Handler,      /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */
+#else
+        .pvReserved70           = (void*) (0UL),                  /* 70 Reserved */
+        .pvReserved71           = (void*) (0UL),                  /* 71 Reserved */
+        .pvReserved72           = (void*) (0UL),                  /* 72 Reserved */
+        .pvReserved73           = (void*) (0UL),                  /* 73 Reserved */
+#endif
+#ifdef ID_SERCOM7
+        .pfnSERCOM7_0_Handler   = (void*) SERCOM7_0_Handler,      /* 74 SERCOM7_0 */
+        .pfnSERCOM7_1_Handler   = (void*) SERCOM7_1_Handler,      /* 75 SERCOM7_1 */
+        .pfnSERCOM7_2_Handler   = (void*) SERCOM7_2_Handler,      /* 76 SERCOM7_2 */
+        .pfnSERCOM7_3_Handler   = (void*) SERCOM7_3_Handler,      /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */
+#else
+        .pvReserved74           = (void*) (0UL),                  /* 74 Reserved */
+        .pvReserved75           = (void*) (0UL),                  /* 75 Reserved */
+        .pvReserved76           = (void*) (0UL),                  /* 76 Reserved */
+        .pvReserved77           = (void*) (0UL),                  /* 77 Reserved */
+#endif
+#ifdef ID_CAN0
+        .pfnCAN0_Handler        = (void*) CAN0_Handler,           /* 78 Control Area Network 0 */
+#else
+        .pvReserved78           = (void*) (0UL),                  /* 78 Reserved */
+#endif
+#ifdef ID_CAN1
+        .pfnCAN1_Handler        = (void*) CAN1_Handler,           /* 79 Control Area Network 1 */
+#else
+        .pvReserved79           = (void*) (0UL),                  /* 79 Reserved */
+#endif
+#ifdef ID_USB
+        .pfnUSB_0_Handler       = (void*) USB_0_Handler,          /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
+        .pfnUSB_1_Handler       = (void*) USB_1_Handler,          /* 81 USB_SOF_HSOF */
+        .pfnUSB_2_Handler       = (void*) USB_2_Handler,          /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
+        .pfnUSB_3_Handler       = (void*) USB_3_Handler,          /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
+#else
+        .pvReserved80           = (void*) (0UL),                  /* 80 Reserved */
+        .pvReserved81           = (void*) (0UL),                  /* 81 Reserved */
+        .pvReserved82           = (void*) (0UL),                  /* 82 Reserved */
+        .pvReserved83           = (void*) (0UL),                  /* 83 Reserved */
+#endif
+#ifdef ID_GMAC
+        .pfnGMAC_Handler        = (void*) GMAC_Handler,           /* 84 Ethernet MAC */
+#else
+        .pvReserved84           = (void*) (0UL),                  /* 84 Reserved */
+#endif
+        .pfnTCC0_0_Handler      = (void*) TCC0_0_Handler,         /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
+        .pfnTCC0_1_Handler      = (void*) TCC0_1_Handler,         /* 86 TCC0_MC_0 */
+        .pfnTCC0_2_Handler      = (void*) TCC0_2_Handler,         /* 87 TCC0_MC_1 */
+        .pfnTCC0_3_Handler      = (void*) TCC0_3_Handler,         /* 88 TCC0_MC_2 */
+        .pfnTCC0_4_Handler      = (void*) TCC0_4_Handler,         /* 89 TCC0_MC_3 */
+        .pfnTCC0_5_Handler      = (void*) TCC0_5_Handler,         /* 90 TCC0_MC_4 */
+        .pfnTCC0_6_Handler      = (void*) TCC0_6_Handler,         /* 91 TCC0_MC_5 */
+        .pfnTCC1_0_Handler      = (void*) TCC1_0_Handler,         /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
+        .pfnTCC1_1_Handler      = (void*) TCC1_1_Handler,         /* 93 TCC1_MC_0 */
+        .pfnTCC1_2_Handler      = (void*) TCC1_2_Handler,         /* 94 TCC1_MC_1 */
+        .pfnTCC1_3_Handler      = (void*) TCC1_3_Handler,         /* 95 TCC1_MC_2 */
+        .pfnTCC1_4_Handler      = (void*) TCC1_4_Handler,         /* 96 TCC1_MC_3 */
+        .pfnTCC2_0_Handler      = (void*) TCC2_0_Handler,         /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
+        .pfnTCC2_1_Handler      = (void*) TCC2_1_Handler,         /* 98 TCC2_MC_0 */
+        .pfnTCC2_2_Handler      = (void*) TCC2_2_Handler,         /* 99 TCC2_MC_1 */
+        .pfnTCC2_3_Handler      = (void*) TCC2_3_Handler,         /* 100 TCC2_MC_2 */
+#ifdef ID_TCC3
+        .pfnTCC3_0_Handler      = (void*) TCC3_0_Handler,         /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
+        .pfnTCC3_1_Handler      = (void*) TCC3_1_Handler,         /* 102 TCC3_MC_0 */
+        .pfnTCC3_2_Handler      = (void*) TCC3_2_Handler,         /* 103 TCC3_MC_1 */
+#else
+        .pvReserved101          = (void*) (0UL),                  /* 101 Reserved */
+        .pvReserved102          = (void*) (0UL),                  /* 102 Reserved */
+        .pvReserved103          = (void*) (0UL),                  /* 103 Reserved */
+#endif
+#ifdef ID_TCC4
+        .pfnTCC4_0_Handler      = (void*) TCC4_0_Handler,         /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
+        .pfnTCC4_1_Handler      = (void*) TCC4_1_Handler,         /* 105 TCC4_MC_0 */
+        .pfnTCC4_2_Handler      = (void*) TCC4_2_Handler,         /* 106 TCC4_MC_1 */
+#else
+        .pvReserved104          = (void*) (0UL),                  /* 104 Reserved */
+        .pvReserved105          = (void*) (0UL),                  /* 105 Reserved */
+        .pvReserved106          = (void*) (0UL),                  /* 106 Reserved */
+#endif
+        .pfnTC0_Handler         = (void*) TC0_Handler,            /* 107 Basic Timer Counter 0 */
+        .pfnTC1_Handler         = (void*) TC1_Handler,            /* 108 Basic Timer Counter 1 */
+        .pfnTC2_Handler         = (void*) TC2_Handler,            /* 109 Basic Timer Counter 2 */
+        .pfnTC3_Handler         = (void*) TC3_Handler,            /* 110 Basic Timer Counter 3 */
+#ifdef ID_TC4
+        .pfnTC4_Handler         = (void*) TC4_Handler,            /* 111 Basic Timer Counter 4 */
+#else
+        .pvReserved111          = (void*) (0UL),                  /* 111 Reserved */
+#endif
+#ifdef ID_TC5
+        .pfnTC5_Handler         = (void*) TC5_Handler,            /* 112 Basic Timer Counter 5 */
+#else
+        .pvReserved112          = (void*) (0UL),                  /* 112 Reserved */
+#endif
+#ifdef ID_TC6
+        .pfnTC6_Handler         = (void*) TC6_Handler,            /* 113 Basic Timer Counter 6 */
+#else
+        .pvReserved113          = (void*) (0UL),                  /* 113 Reserved */
+#endif
+#ifdef ID_TC7
+        .pfnTC7_Handler         = (void*) TC7_Handler,            /* 114 Basic Timer Counter 7 */
+#else
+        .pvReserved114          = (void*) (0UL),                  /* 114 Reserved */
+#endif
+        .pfnPDEC_0_Handler      = (void*) PDEC_0_Handler,         /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
+        .pfnPDEC_1_Handler      = (void*) PDEC_1_Handler,         /* 116 PDEC_MC_0 */
+        .pfnPDEC_2_Handler      = (void*) PDEC_2_Handler,         /* 117 PDEC_MC_1 */
+        .pfnADC0_0_Handler      = (void*) ADC0_0_Handler,         /* 118 ADC0_OVERRUN, ADC0_WINMON */
+        .pfnADC0_1_Handler      = (void*) ADC0_1_Handler,         /* 119 ADC0_RESRDY */
+        .pfnADC1_0_Handler      = (void*) ADC1_0_Handler,         /* 120 ADC1_OVERRUN, ADC1_WINMON */
+        .pfnADC1_1_Handler      = (void*) ADC1_1_Handler,         /* 121 ADC1_RESRDY */
+        .pfnAC_Handler          = (void*) AC_Handler,             /* 122 Analog Comparators */
+        .pfnDAC_0_Handler       = (void*) DAC_0_Handler,          /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
+        .pfnDAC_1_Handler       = (void*) DAC_1_Handler,          /* 124 DAC_EMPTY_0 */
+        .pfnDAC_2_Handler       = (void*) DAC_2_Handler,          /* 125 DAC_EMPTY_1 */
+        .pfnDAC_3_Handler       = (void*) DAC_3_Handler,          /* 126 DAC_RESRDY_0 */
+        .pfnDAC_4_Handler       = (void*) DAC_4_Handler,          /* 127 DAC_RESRDY_1 */
+#ifdef ID_I2S
+        .pfnI2S_Handler         = (void*) I2S_Handler,            /* 128 Inter-IC Sound Interface */
+#else
+        .pvReserved128          = (void*) (0UL),                  /* 128 Reserved */
+#endif
+        .pfnPCC_Handler         = (void*) PCC_Handler,            /* 129 Parallel Capture Controller */
+        .pfnAES_Handler         = (void*) AES_Handler,            /* 130 Advanced Encryption Standard */
+        .pfnTRNG_Handler        = (void*) TRNG_Handler,           /* 131 True Random Generator */
+#ifdef ID_ICM
+        .pfnICM_Handler         = (void*) ICM_Handler,            /* 132 Integrity Check Monitor */
+#else
+        .pvReserved132          = (void*) (0UL),                  /* 132 Reserved */
+#endif
+#ifdef ID_PUKCC
+        .pfnPUKCC_Handler       = (void*) PUKCC_Handler,          /* 133 PUblic-Key Cryptography Controller */
+#else
+        .pvReserved133          = (void*) (0UL),                  /* 133 Reserved */
+#endif
+        .pfnQSPI_Handler        = (void*) QSPI_Handler,           /* 134 Quad SPI interface */
+#ifdef ID_SDHC0
+        .pfnSDHC0_Handler       = (void*) SDHC0_Handler,          /* 135 SD/MMC Host Controller 0 */
+#else
+        .pvReserved135          = (void*) (0UL),                  /* 135 Reserved */
+#endif
+#ifdef ID_SDHC1
+        .pfnSDHC1_Handler       = (void*) SDHC1_Handler           /* 136 SD/MMC Host Controller 1 */
+#else
+        .pvReserved136          = (void*) (0UL)                   /* 136 Reserved */
+#endif
+};
+
+
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+        while (1) {
+        }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/ProjectTemplate.atsln b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/ProjectTemplate.atsln
new file mode 100644
index 000000000..e25dc8989
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/ProjectTemplate.atsln
@@ -0,0 +1,34 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.25420.1
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ProjectTemplate", "ProjectTemplate.cppproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ClearCore", "..\libClearCore\ClearCore.cppproj", "{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "LwIP", "..\LwIP\LwIP.cppproj", "{C373696C-5D45-4B91-AD62-A21552361596}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.ActiveCfg = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Debug|ARM.Build.0 = Debug|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.ActiveCfg = Release|ARM
+		{2530D5B1-8A40-4A55-95CA-2EC0B63E2088}.Release|ARM.Build.0 = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.ActiveCfg = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Debug|ARM.Build.0 = Debug|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.ActiveCfg = Release|ARM
+		{C373696C-5D45-4B91-AD62-A21552361596}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/ProjectTemplate.cppproj b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/ProjectTemplate.cppproj
new file mode 100644
index 000000000..9a1ba25a3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/ProjectTemplate.cppproj
@@ -0,0 +1,265 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>Executable</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.elf</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AssemblyName>ProjectTemplate</AssemblyName>
+    <Name>ProjectTemplate</Name>
+    <RootNamespace>ProjectTemplate</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>4</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.34.1" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>custom</avrtool>
+    <avrtoolserialnumber>
+    </avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>SWD</avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>0</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+      <ToolNumber>J41800072707</ToolNumber>
+      <ToolName>Atmel-ICE</ToolName>
+    </com_atmel_avrdbg_tool_atmelice>
+    <avrtoolinterfaceclock>0</avrtoolinterfaceclock>
+    <custom>
+      <ToolOptions xmlns="">
+        <InterfaceProperties>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
+      <ToolType xmlns="">custom</ToolType>
+      <ToolNumber xmlns="">
+      </ToolNumber>
+      <ToolName xmlns="">Custom Programming Tool</ToolName>
+    </custom>
+    <CustomProgrammingToolCommand>"$(MSBuildProjectDirectory)\..\Tools\flash_clearcore.cmd" "$(OutputDirectory)\$(OutputFileName).bin"</CustomProgrammingToolCommand>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>NDEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../libClearCore/inc</Value>
+      <Value>../../LwIP/LwIP/src/include</Value>
+      <Value>../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>%24(ProjectDir)\Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+    <ToolchainSettings>
+      <ArmGccCpp>
+  <armgcc.common.outputfiles.hex>False</armgcc.common.outputfiles.hex>
+  <armgcc.common.outputfiles.lss>False</armgcc.common.outputfiles.lss>
+  <armgcc.common.outputfiles.eep>False</armgcc.common.outputfiles.eep>
+  <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+  <armgcc.common.outputfiles.srec>False</armgcc.common.outputfiles.srec>
+  <armgcc.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcc.compiler.symbols.DefSymbols>
+  <armgcc.compiler.directories.DefaultIncludePath>False</armgcc.compiler.directories.DefaultIncludePath>
+  <armgcc.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcc.compiler.directories.IncludePaths>
+  <armgcc.compiler.optimization.level>Optimize most (-O3)</armgcc.compiler.optimization.level>
+  <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+  <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+  <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+  <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>
+  <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=50 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcc.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.compiler.symbols.DefSymbols>
+    <ListValues>
+      <Value>DEBUG</Value>
+    </ListValues>
+  </armgcccpp.compiler.symbols.DefSymbols>
+  <armgcccpp.compiler.directories.DefaultIncludePath>False</armgcccpp.compiler.directories.DefaultIncludePath>
+  <armgcccpp.compiler.directories.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>../../libClearCore/inc</Value>
+      <Value>../../LwIP/LwIP/src/include</Value>
+      <Value>../../LwIP/LwIP/port/include</Value>
+    </ListValues>
+  </armgcccpp.compiler.directories.IncludePaths>
+  <armgcccpp.compiler.optimization.level>Optimize most (-O3)</armgcccpp.compiler.optimization.level>
+  <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+  <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+  <armgcccpp.compiler.optimization.DebugLevel>Default (-g2)</armgcccpp.compiler.optimization.DebugLevel>
+  <armgcccpp.compiler.warnings.AllWarnings>True</armgcccpp.compiler.warnings.AllWarnings>
+  <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 -fno-threadsafe-statics -nostdlib --param max-inline-insns-single=500 -MMD -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.compiler.miscellaneous.OtherFlags>
+  <armgcccpp.linker.general.AdditionalSpecs>Use rdimon (semihosting) library (--specs=rdimon.specs)</armgcccpp.linker.general.AdditionalSpecs>
+  <armgcccpp.linker.libraries.Libraries>
+    <ListValues>
+      <Value>libm</Value>
+      <Value>arm_cortexM4lf_math</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.Libraries>
+  <armgcccpp.linker.libraries.LibrarySearchPaths>
+    <ListValues>
+      <Value>%24(ProjectDir)\Device_Startup</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Lib\GCC</Value>
+    </ListValues>
+  </armgcccpp.linker.libraries.LibrarySearchPaths>
+  <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+  <armgcccpp.linker.memorysettings.ExternalRAM />
+  <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_with_bootloader.ld -mfloat-abi=hard -mfpu=fpv4-sp-d16</armgcccpp.linker.miscellaneous.LinkerFlags>
+  <armgcccpp.assembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.assembler.general.IncludePaths>
+  <armgcccpp.assembler.debugging.DebugLevel>Default (-g)</armgcccpp.assembler.debugging.DebugLevel>
+  <armgcccpp.preprocessingassembler.general.DefaultIncludePath>False</armgcccpp.preprocessingassembler.general.DefaultIncludePath>
+  <armgcccpp.preprocessingassembler.general.IncludePaths>
+    <ListValues>
+      <Value>%24(PackRepoDir)\atmel\SAME53_DFP\1.1.118\include</Value>
+      <Value>%24(PackRepoDir)\arm\CMSIS\4.5.0\CMSIS\Include\</Value>
+    </ListValues>
+  </armgcccpp.preprocessingassembler.general.IncludePaths>
+  <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+</ArmGccCpp>
+    </ToolchainSettings>
+    <PostBuildEvent>"$(SolutionDir)\..\Tools\uf2-builder\Release\uf2-builder.exe" "$(OutputDirectory)\$(OutputFileName).bin" "$(OutputDirectory)\$(OutputFileName).uf2"</PostBuildEvent>
+  </PropertyGroup>
+  <ItemGroup>
+    <Compile Include="Device_Startup\flash_with_bootloader.ld">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="Device_Startup\startup_same53.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <None Include="Device_Startup\flash_without_bootloader.ld">
+      <SubType>compile</SubType>
+    </None>
+    <Compile Include="main.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+  </ItemGroup>
+  <ItemGroup>
+    <Folder Include="Device_Startup\" />
+  </ItemGroup>
+  <ItemGroup>
+    <ProjectReference Include="..\..\libClearCore\ClearCore.cppproj">
+      <Name>ClearCore</Name>
+      <Project>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+    <ProjectReference Include="..\..\LwIP\LwIP.cppproj">
+      <Name>LwIP</Name>
+      <Project>{c373696c-5d45-4b91-ad62-a21552361596}</Project>
+      <Private>True</Private>
+    </ProjectReference>
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/README.md b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/README.md
new file mode 100644
index 000000000..c466bdf7a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/README.md
@@ -0,0 +1,4 @@
+# ProjectTemplate
+
+This repository contains a basic ClearCore project that can be used as a template for new application development.
+Place this repository rooted in the same parent directory as libClearCore and LwIP to properly find include files and libraries.
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/main.cpp b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/main.cpp
new file mode 100644
index 000000000..8306fcda9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/ProjectTemplate/main.cpp
@@ -0,0 +1,13 @@
+
+#include "ClearCore.h"
+
+int main(void) {
+    /* Replace with your application code */
+    bool ledState = true;
+    while (1)
+    {
+        ConnectorLed.State(ledState);
+        ledState = !ledState;
+        Delay_ms(1000);
+    }
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/README.md b/vendor/teknic/clear-core/ClearCore-library/README.md
new file mode 100644
index 000000000..affb365e8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/README.md
@@ -0,0 +1,46 @@
+# ClearCore-library 
+
+This repository contains the ClearCore Motion and I/O Library, providing a foundation to build ClearCore applications. Also included are Atmel Studio example programs that demonstrate various features of the ClearCore, and an Atmel Studio template project that can be used to start building your own application.
+
+#### Atmel Studio requirements
+
+The included Atmel Studio projects require Atmel Studio version 7.0.1645 or later (latest version is recommended).
+
+From the Atmel Studio Tools menu, open the Device Pack Manager. Ensure the following packs are installed:
+* SAME53_DFP version 1.1.118
+* CMSIS version 4.5.0
+
+#### Installers and Resources
+
+https://www.teknic.com/downloads/
+
+### libClearCore
+
+libClearCore provides a C++ object oriented API to interface with the ClearCore hardware. Each connector of the ClearCore has an associated object to use in your application. A Doxygen reference manual for the libClearCore API is available at https://teknic-inc.github.io/ClearCore-library/.
+
+There is an Atmel Studio project file (*.cppproj) included to load and compile this library in Atmel Studio.
+
+### LwIP
+
+The ClearCore Ethernet implementation is based off of the LwIP stack. Ethernet applications should be developed using the ethernet API provided by libClearCore. The LwIP source code is included for completeness.
+
+There is an Atmel Studio project file (*.cppproj) included to load and compile this library in Atmel Studio.
+
+### Atmel_Examples
+
+This folder contains example applications for a variety of ClearCore features. To run a provided example, first choose which subdirectory describes the feature that you want to run. Within each subdirectory is an Atmel solution file (*.atsln) that contains various examples related to that feature, as well as the required interface libraries. After the solution is loaded in Atmel Studio, browse for the project with the example that you wish to run within the solution explorer panel. Right click on the project and select "Set as Startup Project". 
+
+The example programs are configured with a custom firmware loading script that will search for a connected ClearCore USB port and load the example programs on the ClearCore hardware. Simply click "Start Without Debugging (Ctrl+Alt+F5)" and the example program will compile, load the firmware, and start executing.
+
+### Project Template
+The Project Template directory is included as a starting point for writing your own application. Simply open the Atmel Studio solution file (*.atsln), and put your application code in main.cpp.
+
+### Tools
+
+We have included Windows tools for loading the firmware onto the ClearCore using the USB connector. 
+
+**bossac** A command line flashing application
+
+**flash_clearcore.cmd** A script that searches for a connected ClearCore USB port and uses bossac to load the firmware
+
+**uf2-builder** Converts the compiled firmware binary file into a UF2 file that allows drag and drop flashing onto the bootloader's mass storage drive.
diff --git a/vendor/teknic/clear-core/ClearCore-library/Tools/README.md b/vendor/teknic/clear-core/ClearCore-library/Tools/README.md
new file mode 100644
index 000000000..451b8dc24
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Tools/README.md
@@ -0,0 +1,9 @@
+# Tools
+
+**bossac.exe** Flash programming utility. See https://github.com/shumatech/BOSSA
+
+**uf2-builder.exe** .bin to .uf2 conversion program. See https://github.com/microsoft/uf2
+
+**flash_clearcore.cmd** Windows script that searches for the ClearCore USB port and uploads a given firmware image.
+
+**flash_clearcore_loop.cmd** Windows script that repeatedly searches for the ClearCore USB port and uploads a given firmware image.
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Tools/flash_clearcore.cmd b/vendor/teknic/clear-core/ClearCore-library/Tools/flash_clearcore.cmd
new file mode 100644
index 000000000..8ba71815d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Tools/flash_clearcore.cmd
@@ -0,0 +1,204 @@
+:: Name:     flash_clearcore.cmd
+:: Purpose:  Flash a connected ClearCore device with a compiled binary file.
+:: Author:   Zachary Lebold
+:: Revision: January 2020 - initial version
+
+@echo off
+
+set versionNumber=1.0.11
+
+rem ---------------------------------------------------------------------------
+rem An awful but necessary hack because timeout causes redirection issues, even
+rem with the /nobreak argument that prevents user input from interrupting
+rem the wait time.
+rem Problem: The timeout command causes the input to get redirected in order to
+rem wait for user input to optionally interrupt the wait time. When a batch
+rem script with timeout commands runs in the background, the input cannot be
+rem redirected to allow for user input and we fail with the following error:
+rem "ERROR: Input redirection is not supported, exiting the process immediately"
+rem
+rem The sleep command would be great, but it is not available on all systems.
+rem
+rem Solution: We're using ping simply as a timeout because it seems to be the
+rem only way...
+rem IP addresses of the form 192.0.2.x are reserved under RFC 3330. Therefore
+rem pinging this kind of IP will never succeed. We ping once, so we will
+rem just end up waiting for the specified timeout (in milliseconds).
+rem ------------------------------------------------------------------------
+set "waitOneSecond=ping 192.0.2.2 -n 1 -w 1000 > nul"
+set "waitTwoSeconds=ping 192.0.2.2 -n 1 -w 2000 > nul"
+set "waitFiveSeconds=ping 192.0.2.2 -n 1 -w 5000 > nul"
+
+set isComPort="PNPDeviceID LIKE 'USB\\VID_2890&PID_8022%%'"
+set isBootPort="PNPDeviceID LIKE 'USB\\VID_2890&PID_0022%%'"
+
+set inBootloader=0
+
+set maxComPortFindAttempts=10
+set comPortFindAttempt=0
+
+:find_binary
+rem ---------------------------------------------------------
+rem Try to grab the binary file from a command line argument.
+rem ---------------------------------------------------------
+
+if "%~1"=="" (
+    echo Error: You must supply the location of a binary file as the argument to this script.
+    %waitFiveSeconds%
+    exit /b 1
+)
+if not exist "%~f1" (
+    echo Error: The supplied filepath "%~f1" does not exist! Please provide a valid path to a binary file.
+    %waitFiveSeconds%
+    exit /b 2
+)
+if not "%~x1"==".bin" (
+    echo Error: You must supply a binary file ^(.bin^)! Supplied file is of extension: %~x1.
+    %waitFiveSeconds%
+    exit /b 3
+)
+    
+echo Using binary file at: %~f1
+echo.
+
+
+:find_bossac
+rem ------------
+rem Find bossac.
+rem ------------
+
+set "bossacPath=%~dp0\bossac\bossac.exe"
+
+if not exist "%bossacPath%" (
+    echo Error: Could not find bossac uploader!
+    %waitFiveSeconds%
+    exit /b 4
+)
+
+echo Found bossac at: %bossacPath%
+echo.
+
+:find_boot_port
+rem ----------------------------
+rem Find the ClearCore COM port.
+rem ----------------------------
+
+if %comPortFindAttempt% gtr 0 (
+    echo Finding ClearCore bootloader COM port... ^(Attempt %comPortFindAttempt%/%maxComPortFindAttempts%^)
+) else (
+    echo Finding ClearCore bootloader COM port... 
+)
+echo.
+
+set comPort=
+
+rem ----------------------------------------------------------------------------
+rem Enumerate the COM ports and grab the one with the VID/PID for a ClearCore bootloader.
+rem ----------------------------------------------------------------------------
+for /f "usebackq" %%B in (`wmic path Win32_SerialPort Where %isBootPort% Get DeviceID 2^> nul ^| FINDSTR "COM"`) do set comPort=%%B
+
+if not defined comPort (
+    if %comPortFindAttempt% equ 0 (
+        echo Couldn't find the bootloader port. Searching for a regular ClearCore port...
+        goto find_com_port
+    ) else if %comPortFindAttempt% lss %maxComPortFindAttempts% (
+        set /a comPortFindAttempt=%comPortFindAttempt%+1
+        echo Couldn't find the port. Trying again...
+        %waitTwoSeconds%
+        goto find_boot_port
+    ) else (
+        echo Got error code: %errorlevel%
+        echo Error: Couldn't find a ClearCore on one of the COM ports!
+        %waitOneSecond%
+        exit /b 5
+    )
+) else (
+    echo Found ClearCore bootloader device on %comPort%.
+    echo.
+    goto chip_flash
+)
+
+:find_com_port
+rem ----------------------------
+rem Find the ClearCore COM port.
+rem ----------------------------
+
+echo Finding ClearCore COM port...
+echo.
+
+set comPort=
+
+rem ----------------------------------------------------------------------------
+rem Enumerate the COM ports and grab the one with the VID/PID for a ClearCore device.
+rem ----------------------------------------------------------------------------
+for /f "usebackq" %%B in (`wmic path Win32_SerialPort Where %isComPort% Get DeviceID 2^> nul ^| FINDSTR "COM"`) do set comPort=%%B
+
+if not defined comPort (
+    echo Got error code: %errorlevel%
+    echo Error: Couldn't find a ClearCore on one of the COM ports!
+    %waitOneSecond%
+    exit /b 6
+) else (
+    set inBootloader=1
+)
+
+echo Found ClearCore device on %comPort%.
+echo.
+
+rem ---------------
+rem Enter bootloader mode.
+rem ---------------
+
+echo Enter bootloader mode...
+echo.
+
+"%bossacPath%" --info --debug --arduino-erase --port=%comPort%
+
+rem ----------------------------------------------------------------------------
+rem In case we get a "Failed to open port at 1200bps" error as the ClearCore 
+rem switches from the running application to bootloader mode, this will give  
+rem us enough time for the port to become available again.
+rem Otherwise, if we don't wait here, we won't find the port and the subsequent
+rem flash will fail.
+rem ----------------------------------------------------------------------------
+if %errorlevel% neq 0 (
+    %waitOneSecond%
+)
+
+set inBootloader=1
+set comPortFindAttempt=1
+set portRemovalAttempt=0
+goto find_boot_port
+
+:chip_flash
+rem ----------------------
+rem Flash the binary file.
+rem ----------------------
+
+"%bossacPath%" --info --debug --port=%comPort% --usb-port --write --erase --verify --offset=0x4000 --reset "%~f1"
+
+if %errorlevel% equ 0 (
+    echo Success!
+    %waitOneSecond%
+    goto boot_port_removal
+) else (
+    echo Got error code: %errorlevel%
+    echo Error: Failed to flash!
+    exit /b 7
+)
+
+:boot_port_removal
+set testPort=
+for /f "usebackq" %%B in (`wmic path Win32_SerialPort Where "DeviceID LIKE '%comPort%'" Get DeviceID 2^> nul ^| FINDSTR "COM"`) do set testPort=%%B
+
+if defined testPort (
+    set /a portRemovalAttempt = %portRemovalAttempt%+1
+    if %portRemovalAttempt% gtr 15 (
+        echo Timed out waiting for bootloader port removal
+        exit /b 8
+    )
+    %waitOneSecond%
+    goto boot_port_removal
+) else (
+    exit /b 0
+)
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/Tools/flash_clearcore_loop.cmd b/vendor/teknic/clear-core/ClearCore-library/Tools/flash_clearcore_loop.cmd
new file mode 100644
index 000000000..9476defc9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/Tools/flash_clearcore_loop.cmd
@@ -0,0 +1,56 @@
+:: Name:     flash_clearcore_loop.cmd
+:: Purpose:  Flash a connected ClearCore device with a compiled binary file.
+::           Do this in a loop until an upload error is discovered.
+:: Author:   Zachary Lebold
+:: Revision: February 2020 - initial version
+
+@echo off
+
+set versionNumber=1.0.11
+
+rem ----------------------------------------------------------------------------
+rem An awful but necessary hack because timeout causes redirection issues, even
+rem with the /nobreak argument that prevents user input from interrupting
+rem the wait time.
+rem Problem: The timeout command causes the input to get redirected in order to
+rem wait for user input to optionally interrupt the wait time. When a batch
+rem script with timeout commands runs in the background, the input cannot be
+rem redirected to allow for user input and we fail with the following error:
+rem "ERROR: Input redirection is not supported, exiting the process immediately"
+rem
+rem The sleep command would be great, but it is not available on all systems.
+rem
+rem Solution: We're using ping simply as a timeout because it seems to be the
+rem only way...
+rem IP addresses of the form 192.0.2.x are reserved under RFC 3330. Therefore
+rem pinging this kind of IP will never succeed. We ping once, so we will
+rem just end up waiting for the specified timeout (in milliseconds).
+rem ----------------------------------------------------------------------------
+set "waitOneSecond=ping 192.0.2.2 -n 1 -w 1000 > nul"
+set "waitTwoSeconds=ping 192.0.2.2 -n 1 -w 2000 > nul"
+set "waitFiveSeconds=ping 192.0.2.2 -n 1 -w 5000 > nul"
+
+set inBootloader=0
+
+set flashCount=1
+
+if not exist "%~dp0\flash_clearcore.cmd" (
+    echo Error: Could not find flash_clearcore.cmd script! 
+    echo.
+    %waitFiveSeconds%
+    exit /b 404
+)
+
+:flash
+echo Starting flash attempt %flashCount%...
+
+call "%~dp0\flash_clearcore.cmd" %1
+
+echo %errorlevel%
+if %errorlevel% equ 0 (
+    set /a flashCount=%flashCount%+1
+    goto flash
+) else (
+    echo Exiting for error %errorlevel% on flash attempt %flashCount%
+    exit /b %errorlevel%
+)
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/.gitlab-ci.yml b/vendor/teknic/clear-core/ClearCore-library/libClearCore/.gitlab-ci.yml
new file mode 100644
index 000000000..d4d37972e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/.gitlab-ci.yml
@@ -0,0 +1,33 @@
+stages:
+  - ClearCore
+
+ClearCore:
+  stage: ClearCore
+  script:
+  - cd %USERPROFILE%\AppData\Local\Arduino15\packages\ClearCore
+  - rmdir /S /Q hardware\sam\1.0.1
+  - rmdir /S /Q hardware\sam\1.0.2
+  - rmdir /S /Q hardware\sam\1.0.3
+  - rmdir /S /Q hardware\sam\1.0.4
+  - rmdir /S /Q hardware\sam\1.0.5
+  - rmdir /S /Q hardware\sam\1.0.6
+  - rmdir /S /Q hardware\sam\1.0.7
+  - rmdir /S /Q hardware\sam\1.0.8
+  - rmdir /S /Q hardware\sam\1.0.9
+  - rmdir /S /Q tools\LwIP
+  - rmdir /S /Q tools\libClearCore
+  - rmdir /S /Q hardware\sam\1.0.10
+  - rmdir /S /Q hardware\sam\1.0.11
+  - rmdir /S /Q hardware\sam\1.0.12
+  - rmdir /S /Q hardware\sam\1.0.13
+                                  
+  - git clone git@git-server.teknic.com:CustomerPackages/ClearCore_Arduino.git --branch "%CI_COMMIT_REF_NAME%" --single-branch "hardware\sam\1.0.13" || ( git clone git@git-server.teknic.com:CustomerPackages/ClearCore_Arduino.git --branch "develop" --single-branch "hardware\sam\1.0.13" )
+  - git clone git@git-server.teknic.com:CustomerPackages/libClearCore.git --branch "%CI_COMMIT_REF_NAME%" --single-branch "hardware\sam\1.0.13\Teknic\libClearCore" || ( git clone git@git-server.teknic.com:CustomerPackages/libClearCore.git --branch "develop" --single-branch "hardware\sam\1.0.13\Teknic\libClearCore" )
+  - git clone git@git-server.teknic.com:CustomerPackages/same53.git --branch "master" --single-branch "hardware\sam\1.0.13\variants\clearcore\Third Party\SAME53"
+  - git clone git@git-server.teknic.com:CustomerPackages/LwIP.git --branch "master" --single-branch "hardware\sam\1.0.13\Teknic\LwIP"
+  - git clone git@git-server.teknic.com:CustomerPackages/uf2-builder.git --branch "master" --single-branch "hardware\sam\1.0.13\Teknic\Tools\uf2-builder"
+  - cd "hardware\sam\1.0.13"
+  - mkdir TestSketch
+  - echo void setup(){} void loop(){} > TestSketch/TestSketch.ino
+  - atmelstudio.exe ClearCore.atsln /build debug /out output.txt || ( type output.txt & EXIT /B 1 )
+  - python build.py -c -b
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/ClearCore.cppproj b/vendor/teknic/clear-core/ClearCore-library/libClearCore/ClearCore.cppproj
new file mode 100644
index 000000000..6a6bac688
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/ClearCore.cppproj
@@ -0,0 +1,850 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+  <PropertyGroup>
+    <SchemaVersion>2.0</SchemaVersion>
+    <ProjectVersion>7.0</ProjectVersion>
+    <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+    <ProjectGuid>{2530d5b1-8a40-4a55-95ca-2ec0b63e2088}</ProjectGuid>
+    <avrdevice>ATSAME53N19A</avrdevice>
+    <avrdeviceseries>none</avrdeviceseries>
+    <OutputType>StaticLibrary</OutputType>
+    <Language>CPP</Language>
+    <OutputFileName>lib$(MSBuildProjectName)</OutputFileName>
+    <OutputFileExtension>.a</OutputFileExtension>
+    <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+    <AvrGccProjectExtensions>
+    </AvrGccProjectExtensions>
+    <AssemblyName>ClearCore</AssemblyName>
+    <Name>ClearCore</Name>
+    <RootNamespace>ClearCore</RootNamespace>
+    <ToolchainFlavour>Native</ToolchainFlavour>
+    <KeepTimersRunning>true</KeepTimersRunning>
+    <OverrideVtor>false</OverrideVtor>
+    <CacheFlash>true</CacheFlash>
+    <ProgFlashFromRam>true</ProgFlashFromRam>
+    <RamSnippetAddress>0x20000000</RamSnippetAddress>
+    <UncachedRange />
+    <preserveEEPROM>true</preserveEEPROM>
+    <OverrideVtorValue>exception_table</OverrideVtorValue>
+    <BootSegment>2</BootSegment>
+    <ResetRule>0</ResetRule>
+    <eraseonlaunchrule>0</eraseonlaunchrule>
+    <EraseKey />
+    <AsfFrameworkConfig>
+      <framework-data>
+  <options />
+  <configurations />
+  <files />
+  <documentation help="" />
+  <offline-documentation help="" />
+  <dependencies>
+    <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.42.0" />
+  </dependencies>
+</framework-data>
+    </AsfFrameworkConfig>
+    <avrtool>com.atmel.avrdbg.tool.samice</avrtool>
+    <avrtoolserialnumber>504502241</avrtoolserialnumber>
+    <avrdeviceexpectedsignature>0x61830303</avrdeviceexpectedsignature>
+    <avrtoolinterface>
+    </avrtoolinterface>
+    <com_atmel_avrdbg_tool_atmelice>
+      <ToolOptions>
+        <InterfaceProperties>
+          <SwdClock>2000000</SwdClock>
+        </InterfaceProperties>
+        <InterfaceName>SWD</InterfaceName>
+      </ToolOptions>
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+    <Compile Include="hri\hri_mclk_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_nvmctrl_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_osc32kctrl_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_oscctrl_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pac_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pcc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pdec_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_pm_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_port_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_qspi_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_ramecc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_rstc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_rtc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_sdhc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_sercom_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_supc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_tcc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_tc_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_trng_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_usb_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="hri\hri_wdt_e53.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\AdcManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\DigitalInOutAnalogOut.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\DigitalInAnalogIn.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\BlinkCodeDriver.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\ClearCore.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\Connector.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\DigitalInOut.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\DigitalIn.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\DigitalInOutHBridge.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\DmaManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetTcp.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetTcpClient.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetTcpServer.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetUdp.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetUtils.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\CcioBoardManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\atomic_utils.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\CcioPin.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\InputManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\IpAddress.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\ISerial.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\MotorDriver.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\PeripheralRoute.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\Phy.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SdCardDriver.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SerialBase.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SerialDriver.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SerialUsb.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\LedDriver.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\StatusManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SysConnectors.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\UsbManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\XBeeDriver.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SysManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\NvmManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SysTiming.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\SysUtils.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetApi.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\EthernetManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\HardwareMapping.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\IirFilter.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\ShiftRegister.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\MotorManager.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="inc\StepGenerator.h">
+      <SubType>compile</SubType>
+    </Compile>
+    <Folder Include="config" />
+    <Folder Include="hal" />
+    <Folder Include="hpl" />
+    <Folder Include="hri" />
+    <Folder Include="usb" />
+    <Folder Include="src\" />
+    <Content Include="src\**\*.*" />
+    <Compile Include="src\AdcManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\DigitalInOutAnalogOut.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\DigitalInAnalogIn.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\BlinkCodeDriver.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\DigitalInOut.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\DigitalIn.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\DigitalInOutHBridge.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\DmaManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\EthernetTcp.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\EthernetTcpClient.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\EthernetTcpServer.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\EthernetUdp.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\EthernetUtils.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\CcioBoardManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\CcioPin.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\InputManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\MotorDriver.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\SdCardDriver.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\SerialBase.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\SerialDriver.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\SerialUsb.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\LedDriver.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\StatusManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\UsbManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\XBeeDriver.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\SysManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\NvmManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\SysTiming.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\EthernetManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\ShiftRegister.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\MotorManager.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\StepGenerator.cpp">
+      <SubType>compile</SubType>
+    </Compile>
+    <Compile Include="src\system_same53.c">
+      <SubType>compile</SubType>
+    </Compile>
+    <Folder Include="usb\class" />
+    <Folder Include="usb\class\cdc" />
+    <Folder Include="usb\class\cdc\device" />
+    <Folder Include="usb\device" />
+  </ItemGroup>
+  <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/Doxygen COND List.txt b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/Doxygen COND List.txt
new file mode 100644
index 000000000..c6a02da64
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/Doxygen COND List.txt	
@@ -0,0 +1,35 @@
+Doxygen Master COND list
+
+Prefix meanings:
+----------------
+ISC - Meridian ISC
+IEX - IEX Related
+CPM - ClearPath-SC Related
+INFC- Net Layer related low level functionality
+
+
+Suffix meanings:
+----------------
+DOC - TOC, general content
+ADV - Advanced topic
+FLIB - C-Function Library content
+CLIB - Class Library content
+
+General
+-------
+INTERNAL_DOC
+SFND1	- Version 1 S-Foundation content (Meridian)
+SFND2 	- Version 2 S-Foundation content (ClearPath-SC only)
+
+Meridian/ISC Related
+--------------------
+ISC_DOC
+IEX_DOC
+ISC_ADV
+ISC_FLIB
+
+ClearPath-SC Related
+--------------------
+CPM_CLIB
+CPM_FLIB
+CPM_ADV
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/DoxygenLayout.xml b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/DoxygenLayout.xml
new file mode 100644
index 000000000..e40e93b02
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/DoxygenLayout.xml
@@ -0,0 +1,182 @@
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+      <tab type="files" visible="yes" title="" intro="" />
+      <tab type="globals" visible="yes" title="" intro="" />
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+    <tab type="user" visible="yes" title="SDK Examples"url="@ref SdkExamples">
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\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/customdoxygen.css b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/customdoxygen.css
new file mode 100644
index 000000000..daacab908
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/customdoxygen.css
@@ -0,0 +1,173 @@
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+}
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+    width:800px; 
+}
+div.image img[src="SC_Status_Reg.png"]{ 
+    width:800px; 
+}
+div.dynheader {
+    user-select: auto;
+}
+
+<style type="text/css">
+	table.tableizer-table {
+		font-size: 12px;
+		border: 3px solid #CCC; 
+		font-family: "Times New Roman", Times, serif;
+	} 
+	.tableizer-table td {
+		padding: 4px;
+		margin: 3px;
+		border: 2px solid #CCC;
+	}
+	.tableizer-table th {
+		background-color: #FFFFFF; 
+		border: 3px solid #CCC;
+		font-weight: bold;
+	}
+</style>
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/footer.html b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/footer.html
new file mode 100644
index 000000000..3fda0093e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/footer.html
@@ -0,0 +1,13 @@
+<!--BEGIN GENERATE_TREEVIEW-->
+    <li class="footer">Generated on $datetime for $projectname by
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> $doxygenversion </li>
+   </ul>
+ </div>
+<!--END GENERATE_TREEVIEW-->
+<!--BEGIN !GENERATE_TREEVIEW-->
+<hr class="footer"/><address class="footer"><small>
+Generated on $datetime for $projectname by&#160;<a href="http://www.doxygen.org/index.html"><img class="footer" src="$relpath$doxygen.png" alt="doxygen"/></a> $doxygenversion</small></address>
+<!--END !GENERATE_TREEVIEW-->
+</body>
+</html>
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/header.html b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/header.html
new file mode 100644
index 000000000..ff55badfb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/doxygen/header.html
@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>$title</title>
+<link href="$relpath$tabs.css" rel="stylesheet" type="text/css"/>
+<link href="$relpath$customdoxygen.css" rel="stylesheet" type="text/css" />
+$treeview
+$search
+$mathjax
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+<!--BEGIN TITLEAREA-->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 56px;">
+  <!--BEGIN PROJECT_LOGO-->
+  <td id="projectlogo"><img alt="Logo" src="$relpath$$projectlogo"></td>
+  <!--END PROJECT_LOGO-->
+  <!--BEGIN PROJECT_NAME-->
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">$projectname
+   <!--BEGIN PROJECT_NUMBER-->&#160;<span id="projectnumber">$projectnumber</span><!--END PROJECT_NUMBER-->
+   </div>
+   <!--BEGIN PROJECT_BRIEF--><div id="projectbrief">$projectbrief</div><!--END PROJECT_BRIEF-->
+  </td>
+  <!--END PROJECT_NAME-->
+  <!--BEGIN !PROJECT_NAME-->
+   <!--BEGIN PROJECT_BRIEF-->
+    <td style="padding-left: 0.5em;">
+    <div id="projectbrief">$projectbrief</div>
+    </td>
+   <!--END PROJECT_BRIEF-->
+  <!--END !PROJECT_NAME-->
+  <!--BEGIN DISABLE_INDEX-->
+   <!--BEGIN SEARCHENGINE-->
+   <td>$searchbox</td>
+   <!--END SEARCHENGINE-->
+  <!--END DISABLE_INDEX-->
+ </tr>
+ </tbody>
+</table>
+</div>
+<!--END TITLEAREA-->
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/libClearCore.cfg b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/libClearCore.cfg
new file mode 100644
index 000000000..7040564d6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/Doc/libClearCore.cfg
@@ -0,0 +1,2447 @@
+# Doxyfile 1.8.11
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all text
+# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv
+# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv
+# for the list of possible encodings.
+# The default value is: UTF-8.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME           = "ClearCore Library"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
+
+PROJECT_NUMBER         = 
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          = 
+
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
+# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy
+# the logo to the output directory.
+
+PROJECT_LOGO           = 
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
+# entered, it will be relative to the location where doxygen was started. If
+# left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       = 
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
+# directories (in 2 levels) under the output directory of each output format and
+# will distribute the generated files over these directories. Enabling this
+# option can be useful when feeding doxygen a huge amount of source files, where
+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system.
+# The default value is: NO.
+
+CREATE_SUBDIRS         = NO
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# characters to appear in the names of generated files. If set to NO, non-ASCII
+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+ALLOW_UNICODE_NAMES    = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,
+# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),
+# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,
+# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),
+# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,
+# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,
+# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,
+# Ukrainian and Vietnamese.
+# The default value is: English.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
+# The default value is: YES.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# description of a member or function before the detailed description
+#
+# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+# The default value is: YES.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator that is
+# used to form the text in various listings. Each string in this list, if found
+# as the leading text of the brief description, will be stripped from the text
+# and the result, after processing the whole list, is used as the annotated
+# text. Otherwise, the brief description is used as-is. If left blank, the
+# following values are used ($name is automatically replaced with the name of
+# the entity):The $name class, The $name widget, The $name file, is, provides,
+# specifies, contains, represents, a, an and the.
+
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# doxygen will generate a detailed section even if there is only a brief
+# description.
+# The default value is: NO.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+# The default value is: NO.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# before files name in the file list and in the header files. If set to NO the
+# shortest path that makes the file name unique will be used
+# The default value is: YES.
+
+FULL_PATH_NAMES        = NO
+
+# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
+# Stripping is only done if one of the specified strings matches the left-hand
+# part of the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the path to
+# strip.
+#
+# Note that you can specify absolute paths here, but also relative paths, which
+# will be relative from the directory where doxygen is started.
+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
+
+STRIP_FROM_PATH        = 
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the
+# path mentioned in the documentation of a class, which tells the reader which
+# header file to include in order to use a class. If left blank only the name of
+# the header file containing the class definition is used. Otherwise one should
+# specify the list of include paths that are normally passed to the compiler
+# using the -I flag.
+
+STRIP_FROM_INC_PATH    = 
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# less readable) file names. This can be useful is your file systems doesn't
+# support long names like on DOS, Mac, or CD-ROM.
+# The default value is: NO.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# first line (until the first dot) of a Javadoc-style comment as the brief
+# description. If set to NO, the Javadoc-style will behave just like regular Qt-
+# style comments (thus requiring an explicit @brief command for a brief
+# description.)
+# The default value is: NO.
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
+
+MULTILINE_CPP_IS_BRIEF = YES
+
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
+
+TAB_SIZE               = 4
+
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:\n"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". You can put \n's in the value part of an alias to insert
+# newlines.
+
+ALIASES                = "CODE_SAMPLE_HDR=<b>Coding Example</b>\n\code"
+
+# This tag can be used to specify a number of word-keyword mappings (TCL only).
+# A mapping has the form "name=value". For example adding "class=itcl::class"
+# will allow you to use the command class in the itcl::class meaning.
+
+TCL_SUBST              = 
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_FOR_C  = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, Javascript,
+# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran:
+# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran:
+# Fortran. In the later case the parser tries to guess whether the code is fixed
+# or free formatted code, this is the default for Fortran type files), VHDL. For
+# instance to make doxygen treat .inc files as Fortran files (default is PHP),
+# and .f files as C (default is Fortran), use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen.
+
+EXTENSION_MAPPING      = 
+
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
+# documentation. See http://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
+
+MARKDOWN_SUPPORT       = YES
+
+# When enabled doxygen tries to link words that correspond to documented
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+# be prevented in individual cases by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
+
+AUTOLINK_SUPPORT       = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+# The default value is: NO.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+# The default value is: NO.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# If one adds a struct or class to a group and this option is enabled, then also
+# any nested class or struct is added to the same group. By default this option
+# is disabled and one has to add nested compounds explicitly via \ingroup.
+# The default value is: NO.
+
+GROUP_NESTED_COMPOUNDS = NO
+
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
+
+INLINE_SIMPLE_STRUCTS  = NO
+
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
+
+LOOKUP_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
+
+EXTRACT_ALL            = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
+# scope will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PACKAGE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
+
+EXTRACT_STATIC         = NO
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+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
+
+EXTRACT_LOCAL_METHODS  = YES
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
+
+EXTRACT_ANON_NSPACES   = YES
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# (class|struct|union) declarations. If set to NO, these declarations will be
+# included in the documentation.
+# The default value is: NO.
+
+HIDE_FRIEND_COMPOUNDS  = YES
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file
+# names in lower-case letters. If set to YES, upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+# The default value is: system dependent.
+
+CASE_SENSE_NAMES       = NO
+
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
+
+HIDE_COMPOUND_REFERENCE= NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
+
+SHOW_GROUPED_MEMB_INC  = NO
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TODOLIST      = NO
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if <section_label> ... \endif and \cond <section_label>
+# ... \endcond blocks.
+
+ENABLED_SECTIONS       = 
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
+# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
+
+SHOW_USED_FILES        = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
+
+FILE_VERSION_FILTER    = 
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
+
+LAYOUT_FILE            = doxygen/DoxygenLayout.xml
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
+
+CITE_BIB_FILES         = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
+
+WARNINGS               = YES
+
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some parameters
+# in a documented function, or documenting parameters that don't exist or using
+# markup commands wrongly.
+# The default value is: YES.
+
+WARN_IF_DOC_ERROR      = YES
+
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong or incomplete
+# parameter documentation, but not about the absence of documentation.
+# The default value is: NO.
+
+WARN_NO_PARAMDOC       = NO
+
+# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# a warning is encountered.
+# The default value is: NO.
+
+WARN_AS_ERROR          = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr).
+
+WARN_LOGFILE           = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING
+# Note: If this tag is empty the current directory is searched.
+
+INPUT                  = ../inc \
+                         ../inc-doc
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see: http://www.gnu.org/software/libiconv) for the list of
+# possible encodings.
+# The default value is: UTF-8.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# read by doxygen.
+#
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
+# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
+# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc,
+# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f, *.for, *.tcl,
+# *.vhd, *.vhdl, *.ucf, *.qsf, *.as and *.js.
+
+FILE_PATTERNS          = *.h \
+                         *.doc
+
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE                = 
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+# The default value is: NO.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       = 
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
+
+EXCLUDE_SYMBOLS        = 
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
+
+EXAMPLE_PATH           = ../../Microchip_Examples
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
+
+EXAMPLE_PATTERNS       = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
+
+IMAGE_PATH             = 
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command:
+#
+# <filter> <input-file>
+#
+# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+INPUT_FILTER           = 
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+FILTER_PATTERNS        = 
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
+
+FILTER_SOURCE_PATTERNS = 
+
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
+
+SOURCE_BROWSER         = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# function all documented functions referencing it will be listed.
+# The default value is: NO.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+SOURCE_TOOLTIPS        = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see http://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the config file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS       = YES
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the
+# cost of reduced performance. This can be particularly helpful with template
+# rich C++ code for which doxygen's built-in parser lacks the necessary type
+# information.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse-libclang=ON option for CMake.
+# The default value is: NO.
+
+CLANG_ASSISTED_PARSING = NO
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_OPTIONS          = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
+
+ALPHABETICAL_INDEX     = YES
+
+# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in
+# which the alphabetical index list will be split.
+# Minimum value: 1, maximum value: 20, default value: 5.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+IGNORE_PREFIX          = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_HEADER            = 
+
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FOOTER            = 
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_STYLESHEET        = 
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_STYLESHEET  = doxygen/customdoxygen.css
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_FILES       = ../inc-doc/img/assets.jpg \
+                         ../inc-doc/img/blink_code_timing_diagram_1_4.png \
+                         ../inc-doc/img/blink_code_timing_diagram_3_2.png \
+                         ../inc-doc/img/boards_manager_installed.png \
+                         ../inc-doc/img/boards_manager_select_version.png \
+                         ../inc-doc/img/boards_manager_update.png \
+                         ../inc-doc/img/examples.png \
+                         ../inc-doc/img/installed_versions.jpg
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a colorwheel, see
+# http://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_HUE    = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use grayscales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_SAT    = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_GAMMA  = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting this
+# to YES can help to show when doxygen was last run and thus if the
+# documentation is up to date.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_TIMESTAMP         = NO
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_SECTIONS  = YES
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see: http://developer.apple.com/tools/xcode/), introduced with
+# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a
+# Makefile in the HTML output directory. Running make will produce the docset in
+# that directory and running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_DOCSET        = NO
+
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on
+# Windows.
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_HTMLHELP      = NO
+
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
+# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_FILE               = ..\libClearCore.chm
+
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+HHC_LOCATION           = "C:\Program Files (x86)\HTML Help Workshop\hhc.exe"
+
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the master .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+GENERATE_CHI           = NO
+
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_INDEX_ENCODING     = 
+
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QCH_FILE               = 
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-
+# folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
+# filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_NAME   = 
+
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
+# filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_ATTRS  = 
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_SECT_FILTER_ATTRS  = 
+
+# The QHG_LOCATION tag can be used to specify the location of Qt's
+# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the
+# generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHG_LOCATION           = 
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+DISABLE_INDEX          = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine-tune the look of the index. As an example, the default style
+# sheet generated by doxygen has an example that shows how to put an image at
+# the root of the tree instead of the PROJECT_NAME. Since the tree basically has
+# the same information as the tab index, you could consider setting
+# DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_TREEVIEW      = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+TREEVIEW_WIDTH         = 250
+
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_FONTSIZE       = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are not
+# supported properly for IE 6.0, but are supported on all modern browsers.
+#
+# Note that when changing this option you need to delete any form_*.png files in
+# the HTML output directory before the changes have effect.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_TRANSPARENT    = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# http://www.mathjax.org) which uses client side Javascript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+USE_MATHJAX            = NO
+
+# When MathJax is enabled you can set the default output format to be used for
+# the MathJax output. See the MathJax site (see:
+# http://docs.mathjax.org/en/latest/output.html) for more details.
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility), NativeMML (i.e. MathML) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_FORMAT         = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from http://www.mathjax.org before deployment.
+# The default value is: http://cdn.mathjax.org/mathjax/latest.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_EXTENSIONS     = 
+
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_CODEFILE       = 
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use <access key> + S
+# (what the <access key> is depends on the OS and browser, but it is typically
+# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down
+# key> to jump into the search results window, the results can be navigated
+# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel
+# the search. The filter options can be selected when the cursor is inside the
+# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>
+# to select a filter and <Enter> or <escape> to activate or cancel the filter
+# option.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a web server instead of a web client using Javascript. There
+# are two flavors of web server based searching depending on the EXTERNAL_SEARCH
+# setting. When disabled, doxygen will generate a PHP script for searching and
+# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing
+# and searching needs to be provided by external tools. See the section
+# "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SERVER_BASED_SEARCH    = NO
+
+# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
+# script for searching. Instead the search results are written to an XML file
+# which needs to be processed by an external indexer. Doxygen will invoke an
+# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
+# search results.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: http://xapian.org/).
+#
+# See the section "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH        = NO
+
+# The SEARCHENGINE_URL should point to a search engine hosted by a web server
+# which will return the search results when EXTERNAL_SEARCH is enabled.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: http://xapian.org/). See the section "External Indexing and
+# Searching" for details.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHENGINE_URL       = 
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed
+# search data is written to a file for indexing by an external tool. With the
+# SEARCHDATA_FILE tag the name of this file can be specified.
+# The default file is: searchdata.xml.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHDATA_FILE        = searchdata.xml
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the
+# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is
+# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple
+# projects and redirect the results back to the right project.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH_ID     = 
+
+# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
+# projects other than the one defined by this configuration file, but that are
+# all added to the same external search index. Each project needs to have a
+# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
+# to a relative location where the documentation can be found. The format is:
+# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTRA_SEARCH_MAPPINGS  = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.
+# The default value is: YES.
+
+GENERATE_LATEX         = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked.
+#
+# Note that when enabling USE_PDFLATEX this option is only used for generating
+# bitmaps for formulas in the HTML output, but not in the Makefile that is
+# written to the output directory.
+# The default file is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate
+# index for LaTeX.
+# The default file is: makeindex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used by the
+# printer.
+# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x
+# 14 inches) and executive (7.25 x 10.5 inches).
+# The default value is: a4.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PAPER_TYPE             = letter
+
+# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names
+# that should be included in the LaTeX output. The package can be specified just
+# by its name or with the correct syntax as to be used with the LaTeX
+# \usepackage command. To get the times font for instance you can specify :
+# EXTRA_PACKAGES=times or EXTRA_PACKAGES={times}
+# To use the option intlimits with the amsmath package you can specify:
+# EXTRA_PACKAGES=[intlimits]{amsmath}
+# If left blank no extra packages will be included.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+EXTRA_PACKAGES         = 
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the
+# generated LaTeX document. The header should contain everything until the first
+# chapter. If it is left blank doxygen will generate a standard header. See
+# section "Doxygen usage" for information on how to let doxygen write the
+# default header to a separate file.
+#
+# Note: Only use a user-defined header if you know what you are doing! The
+# following commands have a special meaning inside the header: $title,
+# $datetime, $date, $doxygenversion, $projectname, $projectnumber,
+# $projectbrief, $projectlogo. Doxygen will replace $title with the empty
+# string, for the replacement values of the other commands the user is referred
+# to HTML_HEADER.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HEADER           = 
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the
+# generated LaTeX document. The footer should contain everything after the last
+# chapter. If it is left blank doxygen will generate a standard footer. See
+# LATEX_HEADER for more information on how to generate a default footer and what
+# special commands can be used inside the footer.
+#
+# Note: Only use a user-defined footer if you know what you are doing!
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_FOOTER           = 
+
+# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# LaTeX style sheets that are included after the standard style sheets created
+# by doxygen. Using this option one can overrule certain style aspects. Doxygen
+# will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list).
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_STYLESHEET = 
+
+# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the LATEX_OUTPUT output
+# directory. Note that the files will be copied as-is; there are no commands or
+# markers available.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_FILES      = 
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is
+# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will
+# contain links (just like the HTML output) instead of page references. This
+# makes the output suitable for online browsing using a PDF viewer.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate
+# the PDF file directly from the LaTeX files. Set this option to YES, to get a
+# higher quality PDF documentation.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
+# command to the generated LaTeX files. This will instruct LaTeX to keep running
+# if errors occur, instead of asking the user for help. This option is also used
+# when generating formulas in HTML.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BATCHMODE        = NO
+
+# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
+# index chapters (such as File Index, Compound Index, etc.) in the output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HIDE_INDICES     = NO
+
+# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source
+# code with syntax highlighting in the LaTeX output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_SOURCE_CODE      = NO
+
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
+# bibliography, e.g. plainnat, or ieeetr. See
+# http://en.wikipedia.org/wiki/BibTeX and \cite for more info.
+# The default value is: plain.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BIB_STYLE        = plain
+
+# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated
+# page will contain the date and time when the page was generated. Setting this
+# to NO can help when comparing the output of multiple runs.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_TIMESTAMP        = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The
+# RTF output is optimized for Word 97 and may not look too pretty with other RTF
+# readers/editors.
+# The default value is: NO.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: rtf.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will
+# contain hyperlink fields. The RTF file will contain links (just like the HTML
+# output) instead of page references. This makes the output suitable for online
+# browsing using Word or some other Word compatible readers that support those
+# fields.
+#
+# Note: WordPad (write) and others do not support links.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_HYPERLINKS         = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's config
+# file, i.e. a series of assignments. You only have to provide replacements,
+# missing definitions are set to their default value.
+#
+# See also section "Doxygen usage" for information on how to generate the
+# default style sheet that doxygen normally uses.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_STYLESHEET_FILE    = 
+
+# Set optional variables used in the generation of an RTF document. Syntax is
+# similar to doxygen's config file. A template extensions file can be generated
+# using doxygen -e rtf extensionFile.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_EXTENSIONS_FILE    = 
+
+# If the RTF_SOURCE_CODE tag is set to YES then doxygen will include source code
+# with syntax highlighting in the RTF output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_SOURCE_CODE        = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for
+# classes and files.
+# The default value is: NO.
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it. A directory man3 will be created inside the directory specified by
+# MAN_OUTPUT.
+# The default directory is: man.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to the generated
+# man pages. In case the manual section does not start with a number, the number
+# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is
+# optional.
+# The default value is: .3.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_EXTENSION          = .3
+
+# The MAN_SUBDIR tag determines the name of the directory created within
+# MAN_OUTPUT in which the man pages are placed. If defaults to man followed by
+# MAN_EXTENSION with the initial . removed.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_SUBDIR             = 
+
+# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+# will generate one additional man file for each entity documented in the real
+# man page(s). These additional files only source the real man page, but without
+# them the man command would be unable to find the correct page.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that
+# captures the structure of the code including all documentation.
+# The default value is: NO.
+
+GENERATE_XML           = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: xml.
+# This tag requires that the tag GENERATE_XML is set to YES.
+
+XML_OUTPUT             = xml
+
+# If the XML_PROGRAMLISTING tag is set to YES, doxygen will dump the program
+# listings (including syntax highlighting and cross-referencing information) to
+# the XML output. Note that enabling this will significantly increase the size
+# of the XML output.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_XML is set to YES.
+
+XML_PROGRAMLISTING     = YES
+
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_DOCBOOK tag is set to YES, doxygen will generate Docbook files
+# that can be used to generate PDF.
+# The default value is: NO.
+
+GENERATE_DOCBOOK       = NO
+
+# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in
+# front of it.
+# The default directory is: docbook.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+DOCBOOK_OUTPUT         = docbook
+
+# If the DOCBOOK_PROGRAMLISTING tag is set to YES, doxygen will include the
+# program listings (including syntax highlighting and cross-referencing
+# information) to the DOCBOOK output. Note that enabling this will significantly
+# increase the size of the DOCBOOK output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+DOCBOOK_PROGRAMLISTING = NO
+
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an
+# AutoGen Definitions (see http://autogen.sf.net) file that captures the
+# structure of the code including all documentation. Note that this feature is
+# still experimental and incomplete at the moment.
+# The default value is: NO.
+
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES, doxygen will generate a Perl module
+# file that captures the structure of the code including all documentation.
+#
+# Note that this feature is still experimental and incomplete at the moment.
+# The default value is: NO.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES, doxygen will generate the necessary
+# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI
+# output from the Perl module output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES, the Perl module output will be nicely
+# formatted so it can be parsed by a human reader. This is useful if you want to
+# understand what is going on. On the other hand, if this tag is set to NO, the
+# size of the Perl module output will be much smaller and Perl will parse it
+# just the same.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_PRETTY         = YES
+
+# The names of the make variables in the generated doxyrules.make file are
+# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful
+# so different doxyrules.make files included by the same Makefile don't
+# overwrite each other's variables.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_MAKEVAR_PREFIX = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES, doxygen will evaluate all
+# C-preprocessor directives found in the sources and include files.
+# The default value is: YES.
+
+ENABLE_PREPROCESSING   = YES
+
+# If the MACRO_EXPANSION tag is set to YES, doxygen will expand all macro names
+# in the source code. If set to NO, only conditional compilation will be
+# performed. Macro expansion can be done in a controlled way by setting
+# EXPAND_ONLY_PREDEF to YES.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+MACRO_EXPANSION        = YES
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then
+# the macro expansion is limited to the macros specified with the PREDEFINED and
+# EXPAND_AS_DEFINED tags.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+EXPAND_ONLY_PREDEF     = YES
+
+# If the SEARCH_INCLUDES tag is set to YES, the include files in the
+# INCLUDE_PATH will be searched if a #include is found.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+SEARCH_INCLUDES        = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by the
+# preprocessor.
+# This tag requires that the tag SEARCH_INCLUDES is set to YES.
+
+INCLUDE_PATH           = 
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will be
+# used.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+INCLUDE_FILE_PATTERNS  = 
+
+# The PREDEFINED tag can be used to specify one or more macro names that are
+# defined before the preprocessor is started (similar to the -D option of e.g.
+# gcc). The argument of the tag is a list of macros of the form: name or
+# name=definition (no spaces). If the definition and the "=" are omitted, "=1"
+# is assumed. To prevent a macro definition from being undefined via #undef or
+# recursively expanded use the := operator instead of the = operator.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+PREDEFINED             = __attribute__(x)= \
+                         HIDE_FROM_DOXYGEN \
+                         __cplusplus \
+                         protected=private
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
+# tag can be used to specify a list of macro names that should be expanded. The
+# macro definition that is found in the sources will be used. Use the PREDEFINED
+# tag if you want to use a different macro definition that overrules the
+# definition found in the source code.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+EXPAND_AS_DEFINED      = 
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
+# remove all references to function-like macros that are alone on a line, have
+# an all uppercase name, and do not end with a semicolon. Such function macros
+# are typically used for boiler-plate code, and will confuse the parser if not
+# removed.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+SKIP_FUNCTION_MACROS   = YES
+
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES tag can be used to specify one or more tag files. For each tag
+# file the location of the external documentation should be added. The format of
+# a tag file without this location is as follows:
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where loc1 and loc2 can be relative or absolute paths or URLs. See the
+# section "Linking to external documentation" for more information about the use
+# of tag files.
+# Note: Each tag file must have a unique name (where the name does NOT include
+# the path). If a tag file is not located in the directory in which doxygen is
+# run, you must also specify the path to the tagfile here.
+
+TAGFILES               = 
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create a
+# tag file that is based on the input files it reads. See section "Linking to
+# external documentation" for more information about the usage of tag files.
+
+GENERATE_TAGFILE       = 
+
+# If the ALLEXTERNALS tag is set to YES, all external class will be listed in
+# the class index. If set to NO, only the inherited external classes will be
+# listed.
+# The default value is: NO.
+
+ALLEXTERNALS           = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES, all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will be
+# listed.
+# The default value is: YES.
+
+EXTERNAL_GROUPS        = YES
+
+# If the EXTERNAL_PAGES tag is set to YES, all external pages will be listed in
+# the related pages index. If set to NO, only the current project's pages will
+# be listed.
+# The default value is: YES.
+
+EXTERNAL_PAGES         = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of 'which perl').
+# The default file (with absolute path) is: /usr/bin/perl.
+
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES, doxygen will generate a class diagram
+# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to
+# NO turns the diagrams off. Note that this option also works with HAVE_DOT
+# disabled, but it is recommended to install and use dot, since it yields more
+# powerful graphs.
+# The default value is: YES.
+
+CLASS_DIAGRAMS         = NO
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see:
+# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH            = 
+
+# You can include diagrams made with dia in doxygen documentation. Doxygen will
+# then run dia to produce the diagram and insert it in the documentation. The
+# DIA_PATH tag allows you to specify the directory where the dia binary resides.
+# If left empty dia is assumed to be found in the default search path.
+
+DIA_PATH               = 
+
+# If set to YES the inheritance and collaboration graphs will hide inheritance
+# and usage relations if the target is undocumented or is not a class.
+# The default value is: YES.
+
+HIDE_UNDOC_RELATIONS   = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz (see:
+# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
+# Bell Labs. The other options in this section have no effect if this option is
+# set to NO
+# The default value is: NO.
+
+HAVE_DOT               = YES
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed
+# to run in parallel. When set to 0 doxygen will base this on the number of
+# processors available in the system. You can set it explicitly to a value
+# larger than 0 to get control over the balance between CPU load and processing
+# speed.
+# Minimum value: 0, maximum value: 32, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_NUM_THREADS        = 0
+
+# When you want a differently looking font in the dot files that doxygen
+# generates you can specify the font name using DOT_FONTNAME. You need to make
+# sure dot is able to find the font, which can be done by putting it in a
+# standard location or by setting the DOTFONTPATH environment variable or by
+# setting DOT_FONTPATH to the directory containing the font.
+# The default value is: Helvetica.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTNAME           = Helvetica
+
+# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of
+# dot graphs.
+# Minimum value: 4, maximum value: 24, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTSIZE           = 10
+
+# By default doxygen will tell dot to use the default font as specified with
+# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set
+# the path where dot can find it using this tag.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTPATH           = 
+
+# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for
+# each documented class showing the direct and indirect inheritance relations.
+# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
+# graph for each documented class showing the direct and indirect implementation
+# dependencies (inheritance, containment, and class references variables) of the
+# class with other documented classes.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+COLLABORATION_GRAPH    = YES
+
+# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
+# groups, showing the direct groups dependencies.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES, doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LOOK               = NO
+
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside the
+# class node. If there are many fields or methods and many nodes the graph may
+# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the
+# number of items for each type to make the size more manageable. Set this to 0
+# for no limit. Note that the threshold may be exceeded by 50% before the limit
+# is enforced. So when you set the threshold to 10, up to 15 fields may appear,
+# but if the number exceeds 15, the total amount of fields shown is limited to
+# 10.
+# Minimum value: 0, maximum value: 100, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LIMIT_NUM_FIELDS   = 10
+
+# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and
+# collaboration graphs will show the relations between templates and their
+# instances.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to
+# YES then doxygen will generate a graph for each documented file showing the
+# direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDE_GRAPH          = YES
+
+# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are
+# set to YES then doxygen will generate a graph for each documented file showing
+# the direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH tag is set to YES then doxygen will generate a call
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable call graphs for selected
+# functions only using the \callgraph command. Disabling a call graph can be
+# accomplished by means of the command \hidecallgraph.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALL_GRAPH             = NO
+
+# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable caller graphs for selected
+# functions only using the \callergraph command. Disabling a caller graph can be
+# accomplished by means of the command \hidecallergraph.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALLER_GRAPH           = NO
+
+# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical
+# hierarchy of all classes instead of a textual one.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the
+# dependencies a directory has on other directories in a graphical way. The
+# dependency relations are determined by the #include relations between the
+# files in the directories.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DIRECTORY_GRAPH        = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. For an explanation of the image formats see the section
+# output formats in the documentation of the dot tool (Graphviz (see:
+# http://www.graphviz.org/)).
+# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order
+# to make the SVG files visible in IE 9+ (other browsers do not have this
+# requirement).
+# Possible values are: png, jpg, gif, svg, png:gd, png:gd:gd, png:cairo,
+# png:cairo:gd, png:cairo:cairo, png:cairo:gdiplus, png:gdiplus and
+# png:gdiplus:gdiplus.
+# The default value is: png.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_IMAGE_FORMAT       = png
+
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
+# enable generation of interactive SVG images that allow zooming and panning.
+#
+# Note that this requires a modern browser other than Internet Explorer. Tested
+# and working are Firefox, Chrome, Safari, and Opera.
+# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make
+# the SVG files visible. Older versions of IE do not have SVG support.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INTERACTIVE_SVG        = NO
+
+# The DOT_PATH tag can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_PATH               = 
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the \dotfile
+# command).
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOTFILE_DIRS           = 
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the \mscfile
+# command).
+
+MSCFILE_DIRS           = 
+
+# The DIAFILE_DIRS tag can be used to specify one or more directories that
+# contain dia files that are included in the documentation (see the \diafile
+# command).
+
+DIAFILE_DIRS           = 
+
+# When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the
+# path where java can find the plantuml.jar file. If left blank, it is assumed
+# PlantUML is not used or called during a preprocessing step. Doxygen will
+# generate a warning when it encounters a \startuml command in this case and
+# will not generate output for the diagram.
+
+PLANTUML_JAR_PATH      = 
+
+# When using plantuml, the specified paths are searched for files specified by
+# the !include statement in a plantuml block.
+
+PLANTUML_INCLUDE_PATH  = 
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes
+# that will be shown in the graph. If the number of nodes in a graph becomes
+# larger than this value, doxygen will truncate the graph, which is visualized
+# by representing a node as a red box. Note that doxygen if the number of direct
+# children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that
+# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+# Minimum value: 0, maximum value: 10000, default value: 50.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs
+# generated by dot. A depth value of 3 means that only nodes reachable from the
+# root by following a path via at most 3 edges will be shown. Nodes that lay
+# further from the root node will be omitted. Note that setting this option to 1
+# or 2 may greatly reduce the computation time needed for large code bases. Also
+# note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+# Minimum value: 0, maximum value: 1000, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not seem
+# to support this out of the box.
+#
+# Warning: Depending on the platform used, enabling this option may lead to
+# badly anti-aliased labels on the edges of a graph (i.e. they become hard to
+# read).
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_TRANSPARENT        = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10) support
+# this, this feature is disabled by default.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_MULTI_TARGETS      = NO
+
+# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page
+# explaining the meaning of the various boxes and arrows in the dot generated
+# graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate dot
+# files that are used to generate the various graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
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+DOT_CLEANUP            = YES
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/README.md b/vendor/teknic/clear-core/ClearCore-library/libClearCore/README.md
new file mode 100644
index 000000000..c95199caf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/README.md
@@ -0,0 +1,3 @@
+# libClearCore
+
+Library for ClearCore board support.
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_cmcc_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_cmcc_config.h
new file mode 100644
index 000000000..859073611
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_cmcc_config.h
@@ -0,0 +1,54 @@
+/* Auto-generated config file hpl_cmcc_config.h */
+#ifndef HPL_CMCC_CONFIG_H
+#define HPL_CMCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Configuration
+
+// <q> Cache enable
+//<i> Defines the cache should be enabled or not.
+// <id> cmcc_enable
+#ifndef CONF_CMCC_ENABLE
+#define CONF_CMCC_ENABLE 0x0
+#endif
+
+// <o> Cache Size
+//<i> Defines the cache memory size to be configured.
+// <0x0=>1 KB
+// <0x1=>2 KB
+// <0x2=>4 KB
+// <id> cache_size
+#ifndef CONF_CMCC_CACHE_SIZE
+#define CONF_CMCC_CACHE_SIZE 0x2
+#endif
+
+// <e> Advanced Configuration
+// <id> cmcc_advanced_configuration
+// <q> Data cache disable
+//<i> Defines the data cache should be disabled or not.
+// <id> cmcc_data_cache_disable
+#ifndef CONF_CMCC_DATA_CACHE_DISABLE
+#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
+#endif
+
+// <q> Instruction cache disable
+//<i> Defines the Instruction cache should be disabled or not.
+// <id> cmcc_inst_cache_disable
+#ifndef CONF_CMCC_INST_CACHE_DISABLE
+#define CONF_CMCC_INST_CACHE_DISABLE 0x0
+#endif
+
+// <q> Clock Gating disable
+//<i> Defines the clock gating should be disabled or not.
+// <id> cmcc_clock_gating_disable
+#ifndef CONF_CMCC_CLK_GATING_DISABLE
+#define CONF_CMCC_CLK_GATING_DISABLE 0x0
+#endif
+
+// </e>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CMCC_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_dmac_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_dmac_config.h
new file mode 100644
index 000000000..90499fc27
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_dmac_config.h
@@ -0,0 +1,7277 @@
+/* Auto-generated config file hpl_dmac_config.h */
+#ifndef HPL_DMAC_CONFIG_H
+#define HPL_DMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> DMAC enable
+// <i> Indicates whether dmac is enabled or not
+// <id> dmac_enable
+#ifndef CONF_DMAC_ENABLE
+#define CONF_DMAC_ENABLE 0
+#endif
+
+// <q> Priority Level 0
+// <i> Indicates whether Priority Level 0 is enabled or not
+// <id> dmac_lvlen0
+#ifndef CONF_DMAC_LVLEN0
+#define CONF_DMAC_LVLEN0 1
+#endif
+
+// <o> Level 0 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 0
+// <1=> Round-robin arbitration scheme for channel with priority 0
+// <i> Defines Level 0 Arbitration for DMA channels
+// <id> dmac_rrlvlen0
+#ifndef CONF_DMAC_RRLVLEN0
+#define CONF_DMAC_RRLVLEN0 0
+#endif
+
+// <o> Level 0 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri0
+#ifndef CONF_DMAC_LVLPRI0
+#define CONF_DMAC_LVLPRI0 0
+#endif
+// <q> Priority Level 1
+// <i> Indicates whether Priority Level 1 is enabled or not
+// <id> dmac_lvlen1
+#ifndef CONF_DMAC_LVLEN1
+#define CONF_DMAC_LVLEN1 1
+#endif
+
+// <o> Level 1 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 1
+// <1=> Round-robin arbitration scheme for channel with priority 1
+// <i> Defines Level 1 Arbitration for DMA channels
+// <id> dmac_rrlvlen1
+#ifndef CONF_DMAC_RRLVLEN1
+#define CONF_DMAC_RRLVLEN1 0
+#endif
+
+// <o> Level 1 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri1
+#ifndef CONF_DMAC_LVLPRI1
+#define CONF_DMAC_LVLPRI1 0
+#endif
+// <q> Priority Level 2
+// <i> Indicates whether Priority Level 2 is enabled or not
+// <id> dmac_lvlen2
+#ifndef CONF_DMAC_LVLEN2
+#define CONF_DMAC_LVLEN2 1
+#endif
+
+// <o> Level 2 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 2
+// <1=> Round-robin arbitration scheme for channel with priority 2
+// <i> Defines Level 2 Arbitration for DMA channels
+// <id> dmac_rrlvlen2
+#ifndef CONF_DMAC_RRLVLEN2
+#define CONF_DMAC_RRLVLEN2 0
+#endif
+
+// <o> Level 2 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri2
+#ifndef CONF_DMAC_LVLPRI2
+#define CONF_DMAC_LVLPRI2 0
+#endif
+// <q> Priority Level 3
+// <i> Indicates whether Priority Level 3 is enabled or not
+// <id> dmac_lvlen3
+#ifndef CONF_DMAC_LVLEN3
+#define CONF_DMAC_LVLEN3 1
+#endif
+
+// <o> Level 3 Round-Robin Arbitration
+// <0=> Static arbitration scheme for channel with priority 3
+// <1=> Round-robin arbitration scheme for channel with priority 3
+// <i> Defines Level 3 Arbitration for DMA channels
+// <id> dmac_rrlvlen3
+#ifndef CONF_DMAC_RRLVLEN3
+#define CONF_DMAC_RRLVLEN3 0
+#endif
+
+// <o> Level 3 Channel Priority Number <0x00-0xFF>
+// <id> dmac_lvlpri3
+#ifndef CONF_DMAC_LVLPRI3
+#define CONF_DMAC_LVLPRI3 0
+#endif
+// <q> Debug Run
+// <i> Indicates whether Debug Run is enabled or not
+// <id> dmac_dbgrun
+#ifndef CONF_DMAC_DBGRUN
+#define CONF_DMAC_DBGRUN 0
+#endif
+
+// <e> Channel 0 settings
+// <id> dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 0 is running in standby mode or not
+// <id> dmac_runstdby_0
+#ifndef CONF_DMAC_RUNSTDBY_0
+#define CONF_DMAC_RUNSTDBY_0 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_0
+#ifndef CONF_DMAC_TRIGACT_0
+#define CONF_DMAC_TRIGACT_0 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_0
+#ifndef CONF_DMAC_LVL_0
+#define CONF_DMAC_LVL_0 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_0
+#ifndef CONF_DMAC_EVOE_0
+#define CONF_DMAC_EVOE_0 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_0
+#ifndef CONF_DMAC_EVIE_0
+#define CONF_DMAC_EVIE_0 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_0
+#ifndef CONF_DMAC_EVACT_0
+#define CONF_DMAC_EVACT_0 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_0
+#ifndef CONF_DMAC_STEPSIZE_0
+#define CONF_DMAC_STEPSIZE_0 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_0
+#ifndef CONF_DMAC_STEPSEL_0
+#define CONF_DMAC_STEPSEL_0 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_0
+#ifndef CONF_DMAC_BLOCKACT_0
+#define CONF_DMAC_BLOCKACT_0 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_0
+#ifndef CONF_DMAC_EVOSEL_0
+#define CONF_DMAC_EVOSEL_0 0
+#endif
+// </e>
+
+// <e> Channel 1 settings
+// <id> dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 1 is running in standby mode or not
+// <id> dmac_runstdby_1
+#ifndef CONF_DMAC_RUNSTDBY_1
+#define CONF_DMAC_RUNSTDBY_1 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_1
+#ifndef CONF_DMAC_TRIGACT_1
+#define CONF_DMAC_TRIGACT_1 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_1
+#ifndef CONF_DMAC_LVL_1
+#define CONF_DMAC_LVL_1 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_1
+#ifndef CONF_DMAC_EVOE_1
+#define CONF_DMAC_EVOE_1 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_1
+#ifndef CONF_DMAC_EVIE_1
+#define CONF_DMAC_EVIE_1 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_1
+#ifndef CONF_DMAC_EVACT_1
+#define CONF_DMAC_EVACT_1 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_1
+#ifndef CONF_DMAC_STEPSIZE_1
+#define CONF_DMAC_STEPSIZE_1 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_1
+#ifndef CONF_DMAC_STEPSEL_1
+#define CONF_DMAC_STEPSEL_1 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_1
+#ifndef CONF_DMAC_BLOCKACT_1
+#define CONF_DMAC_BLOCKACT_1 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_1
+#ifndef CONF_DMAC_EVOSEL_1
+#define CONF_DMAC_EVOSEL_1 0
+#endif
+// </e>
+
+// <e> Channel 2 settings
+// <id> dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 2 is running in standby mode or not
+// <id> dmac_runstdby_2
+#ifndef CONF_DMAC_RUNSTDBY_2
+#define CONF_DMAC_RUNSTDBY_2 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_2
+#ifndef CONF_DMAC_TRIGACT_2
+#define CONF_DMAC_TRIGACT_2 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_2
+#ifndef CONF_DMAC_LVL_2
+#define CONF_DMAC_LVL_2 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_2
+#ifndef CONF_DMAC_EVOE_2
+#define CONF_DMAC_EVOE_2 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_2
+#ifndef CONF_DMAC_EVIE_2
+#define CONF_DMAC_EVIE_2 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_2
+#ifndef CONF_DMAC_EVACT_2
+#define CONF_DMAC_EVACT_2 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_2
+#ifndef CONF_DMAC_STEPSIZE_2
+#define CONF_DMAC_STEPSIZE_2 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_2
+#ifndef CONF_DMAC_STEPSEL_2
+#define CONF_DMAC_STEPSEL_2 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_2
+#ifndef CONF_DMAC_BLOCKACT_2
+#define CONF_DMAC_BLOCKACT_2 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_2
+#ifndef CONF_DMAC_EVOSEL_2
+#define CONF_DMAC_EVOSEL_2 0
+#endif
+// </e>
+
+// <e> Channel 3 settings
+// <id> dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 3 is running in standby mode or not
+// <id> dmac_runstdby_3
+#ifndef CONF_DMAC_RUNSTDBY_3
+#define CONF_DMAC_RUNSTDBY_3 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_3
+#ifndef CONF_DMAC_TRIGACT_3
+#define CONF_DMAC_TRIGACT_3 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_3
+#ifndef CONF_DMAC_LVL_3
+#define CONF_DMAC_LVL_3 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_3
+#ifndef CONF_DMAC_EVOE_3
+#define CONF_DMAC_EVOE_3 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_3
+#ifndef CONF_DMAC_EVIE_3
+#define CONF_DMAC_EVIE_3 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_3
+#ifndef CONF_DMAC_EVACT_3
+#define CONF_DMAC_EVACT_3 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_3
+#ifndef CONF_DMAC_STEPSIZE_3
+#define CONF_DMAC_STEPSIZE_3 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_3
+#ifndef CONF_DMAC_STEPSEL_3
+#define CONF_DMAC_STEPSEL_3 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_3
+#ifndef CONF_DMAC_BLOCKACT_3
+#define CONF_DMAC_BLOCKACT_3 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_3
+#ifndef CONF_DMAC_EVOSEL_3
+#define CONF_DMAC_EVOSEL_3 0
+#endif
+// </e>
+
+// <e> Channel 4 settings
+// <id> dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 4 is running in standby mode or not
+// <id> dmac_runstdby_4
+#ifndef CONF_DMAC_RUNSTDBY_4
+#define CONF_DMAC_RUNSTDBY_4 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_4
+#ifndef CONF_DMAC_TRIGACT_4
+#define CONF_DMAC_TRIGACT_4 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_4
+#ifndef CONF_DMAC_LVL_4
+#define CONF_DMAC_LVL_4 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_4
+#ifndef CONF_DMAC_EVOE_4
+#define CONF_DMAC_EVOE_4 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_4
+#ifndef CONF_DMAC_EVIE_4
+#define CONF_DMAC_EVIE_4 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_4
+#ifndef CONF_DMAC_EVACT_4
+#define CONF_DMAC_EVACT_4 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_4
+#ifndef CONF_DMAC_STEPSIZE_4
+#define CONF_DMAC_STEPSIZE_4 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_4
+#ifndef CONF_DMAC_STEPSEL_4
+#define CONF_DMAC_STEPSEL_4 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_4
+#ifndef CONF_DMAC_BLOCKACT_4
+#define CONF_DMAC_BLOCKACT_4 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_4
+#ifndef CONF_DMAC_EVOSEL_4
+#define CONF_DMAC_EVOSEL_4 0
+#endif
+// </e>
+
+// <e> Channel 5 settings
+// <id> dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 5 is running in standby mode or not
+// <id> dmac_runstdby_5
+#ifndef CONF_DMAC_RUNSTDBY_5
+#define CONF_DMAC_RUNSTDBY_5 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_5
+#ifndef CONF_DMAC_TRIGACT_5
+#define CONF_DMAC_TRIGACT_5 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_5
+#ifndef CONF_DMAC_LVL_5
+#define CONF_DMAC_LVL_5 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_5
+#ifndef CONF_DMAC_EVOE_5
+#define CONF_DMAC_EVOE_5 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_5
+#ifndef CONF_DMAC_EVIE_5
+#define CONF_DMAC_EVIE_5 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_5
+#ifndef CONF_DMAC_EVACT_5
+#define CONF_DMAC_EVACT_5 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_5
+#ifndef CONF_DMAC_STEPSIZE_5
+#define CONF_DMAC_STEPSIZE_5 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_5
+#ifndef CONF_DMAC_STEPSEL_5
+#define CONF_DMAC_STEPSEL_5 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_5
+#ifndef CONF_DMAC_BLOCKACT_5
+#define CONF_DMAC_BLOCKACT_5 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_5
+#ifndef CONF_DMAC_EVOSEL_5
+#define CONF_DMAC_EVOSEL_5 0
+#endif
+// </e>
+
+// <e> Channel 6 settings
+// <id> dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 6 is running in standby mode or not
+// <id> dmac_runstdby_6
+#ifndef CONF_DMAC_RUNSTDBY_6
+#define CONF_DMAC_RUNSTDBY_6 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_6
+#ifndef CONF_DMAC_TRIGACT_6
+#define CONF_DMAC_TRIGACT_6 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_6
+#ifndef CONF_DMAC_LVL_6
+#define CONF_DMAC_LVL_6 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_6
+#ifndef CONF_DMAC_EVOE_6
+#define CONF_DMAC_EVOE_6 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_6
+#ifndef CONF_DMAC_EVIE_6
+#define CONF_DMAC_EVIE_6 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_6
+#ifndef CONF_DMAC_EVACT_6
+#define CONF_DMAC_EVACT_6 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_6
+#ifndef CONF_DMAC_STEPSIZE_6
+#define CONF_DMAC_STEPSIZE_6 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_6
+#ifndef CONF_DMAC_STEPSEL_6
+#define CONF_DMAC_STEPSEL_6 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_6
+#ifndef CONF_DMAC_BLOCKACT_6
+#define CONF_DMAC_BLOCKACT_6 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_6
+#ifndef CONF_DMAC_EVOSEL_6
+#define CONF_DMAC_EVOSEL_6 0
+#endif
+// </e>
+
+// <e> Channel 7 settings
+// <id> dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 7 is running in standby mode or not
+// <id> dmac_runstdby_7
+#ifndef CONF_DMAC_RUNSTDBY_7
+#define CONF_DMAC_RUNSTDBY_7 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_7
+#ifndef CONF_DMAC_TRIGACT_7
+#define CONF_DMAC_TRIGACT_7 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_7
+#ifndef CONF_DMAC_LVL_7
+#define CONF_DMAC_LVL_7 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_7
+#ifndef CONF_DMAC_EVOE_7
+#define CONF_DMAC_EVOE_7 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_7
+#ifndef CONF_DMAC_EVIE_7
+#define CONF_DMAC_EVIE_7 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_7
+#ifndef CONF_DMAC_EVACT_7
+#define CONF_DMAC_EVACT_7 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_7
+#ifndef CONF_DMAC_STEPSIZE_7
+#define CONF_DMAC_STEPSIZE_7 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_7
+#ifndef CONF_DMAC_STEPSEL_7
+#define CONF_DMAC_STEPSEL_7 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_7
+#ifndef CONF_DMAC_BLOCKACT_7
+#define CONF_DMAC_BLOCKACT_7 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_7
+#ifndef CONF_DMAC_EVOSEL_7
+#define CONF_DMAC_EVOSEL_7 0
+#endif
+// </e>
+
+// <e> Channel 8 settings
+// <id> dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 8 is running in standby mode or not
+// <id> dmac_runstdby_8
+#ifndef CONF_DMAC_RUNSTDBY_8
+#define CONF_DMAC_RUNSTDBY_8 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_8
+#ifndef CONF_DMAC_TRIGACT_8
+#define CONF_DMAC_TRIGACT_8 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_8
+#ifndef CONF_DMAC_LVL_8
+#define CONF_DMAC_LVL_8 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_8
+#ifndef CONF_DMAC_EVOE_8
+#define CONF_DMAC_EVOE_8 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_8
+#ifndef CONF_DMAC_EVIE_8
+#define CONF_DMAC_EVIE_8 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_8
+#ifndef CONF_DMAC_EVACT_8
+#define CONF_DMAC_EVACT_8 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_8
+#ifndef CONF_DMAC_STEPSIZE_8
+#define CONF_DMAC_STEPSIZE_8 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_8
+#ifndef CONF_DMAC_STEPSEL_8
+#define CONF_DMAC_STEPSEL_8 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_8
+#ifndef CONF_DMAC_BLOCKACT_8
+#define CONF_DMAC_BLOCKACT_8 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_8
+#ifndef CONF_DMAC_EVOSEL_8
+#define CONF_DMAC_EVOSEL_8 0
+#endif
+// </e>
+
+// <e> Channel 9 settings
+// <id> dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 9 is running in standby mode or not
+// <id> dmac_runstdby_9
+#ifndef CONF_DMAC_RUNSTDBY_9
+#define CONF_DMAC_RUNSTDBY_9 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_9
+#ifndef CONF_DMAC_TRIGACT_9
+#define CONF_DMAC_TRIGACT_9 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_9
+#ifndef CONF_DMAC_LVL_9
+#define CONF_DMAC_LVL_9 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_9
+#ifndef CONF_DMAC_EVOE_9
+#define CONF_DMAC_EVOE_9 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_9
+#ifndef CONF_DMAC_EVIE_9
+#define CONF_DMAC_EVIE_9 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_9
+#ifndef CONF_DMAC_EVACT_9
+#define CONF_DMAC_EVACT_9 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_9
+#ifndef CONF_DMAC_STEPSIZE_9
+#define CONF_DMAC_STEPSIZE_9 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_9
+#ifndef CONF_DMAC_STEPSEL_9
+#define CONF_DMAC_STEPSEL_9 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_9
+#ifndef CONF_DMAC_BLOCKACT_9
+#define CONF_DMAC_BLOCKACT_9 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_9
+#ifndef CONF_DMAC_EVOSEL_9
+#define CONF_DMAC_EVOSEL_9 0
+#endif
+// </e>
+
+// <e> Channel 10 settings
+// <id> dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 10 is running in standby mode or not
+// <id> dmac_runstdby_10
+#ifndef CONF_DMAC_RUNSTDBY_10
+#define CONF_DMAC_RUNSTDBY_10 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_10
+#ifndef CONF_DMAC_TRIGACT_10
+#define CONF_DMAC_TRIGACT_10 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_10
+#ifndef CONF_DMAC_LVL_10
+#define CONF_DMAC_LVL_10 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_10
+#ifndef CONF_DMAC_EVOE_10
+#define CONF_DMAC_EVOE_10 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_10
+#ifndef CONF_DMAC_EVIE_10
+#define CONF_DMAC_EVIE_10 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_10
+#ifndef CONF_DMAC_EVACT_10
+#define CONF_DMAC_EVACT_10 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_10
+#ifndef CONF_DMAC_STEPSIZE_10
+#define CONF_DMAC_STEPSIZE_10 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_10
+#ifndef CONF_DMAC_STEPSEL_10
+#define CONF_DMAC_STEPSEL_10 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_10
+#ifndef CONF_DMAC_BLOCKACT_10
+#define CONF_DMAC_BLOCKACT_10 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_10
+#ifndef CONF_DMAC_EVOSEL_10
+#define CONF_DMAC_EVOSEL_10 0
+#endif
+// </e>
+
+// <e> Channel 11 settings
+// <id> dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 11 is running in standby mode or not
+// <id> dmac_runstdby_11
+#ifndef CONF_DMAC_RUNSTDBY_11
+#define CONF_DMAC_RUNSTDBY_11 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_11
+#ifndef CONF_DMAC_TRIGACT_11
+#define CONF_DMAC_TRIGACT_11 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_11
+#ifndef CONF_DMAC_LVL_11
+#define CONF_DMAC_LVL_11 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_11
+#ifndef CONF_DMAC_EVOE_11
+#define CONF_DMAC_EVOE_11 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_11
+#ifndef CONF_DMAC_EVIE_11
+#define CONF_DMAC_EVIE_11 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_11
+#ifndef CONF_DMAC_EVACT_11
+#define CONF_DMAC_EVACT_11 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_11
+#ifndef CONF_DMAC_STEPSIZE_11
+#define CONF_DMAC_STEPSIZE_11 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_11
+#ifndef CONF_DMAC_STEPSEL_11
+#define CONF_DMAC_STEPSEL_11 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_11
+#ifndef CONF_DMAC_BLOCKACT_11
+#define CONF_DMAC_BLOCKACT_11 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_11
+#ifndef CONF_DMAC_EVOSEL_11
+#define CONF_DMAC_EVOSEL_11 0
+#endif
+// </e>
+
+// <e> Channel 12 settings
+// <id> dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 12 is running in standby mode or not
+// <id> dmac_runstdby_12
+#ifndef CONF_DMAC_RUNSTDBY_12
+#define CONF_DMAC_RUNSTDBY_12 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_12
+#ifndef CONF_DMAC_TRIGACT_12
+#define CONF_DMAC_TRIGACT_12 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_12
+#ifndef CONF_DMAC_LVL_12
+#define CONF_DMAC_LVL_12 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_12
+#ifndef CONF_DMAC_EVOE_12
+#define CONF_DMAC_EVOE_12 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_12
+#ifndef CONF_DMAC_EVIE_12
+#define CONF_DMAC_EVIE_12 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_12
+#ifndef CONF_DMAC_EVACT_12
+#define CONF_DMAC_EVACT_12 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_12
+#ifndef CONF_DMAC_STEPSIZE_12
+#define CONF_DMAC_STEPSIZE_12 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_12
+#ifndef CONF_DMAC_STEPSEL_12
+#define CONF_DMAC_STEPSEL_12 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_12
+#ifndef CONF_DMAC_BLOCKACT_12
+#define CONF_DMAC_BLOCKACT_12 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_12
+#ifndef CONF_DMAC_EVOSEL_12
+#define CONF_DMAC_EVOSEL_12 0
+#endif
+// </e>
+
+// <e> Channel 13 settings
+// <id> dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 13 is running in standby mode or not
+// <id> dmac_runstdby_13
+#ifndef CONF_DMAC_RUNSTDBY_13
+#define CONF_DMAC_RUNSTDBY_13 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_13
+#ifndef CONF_DMAC_TRIGACT_13
+#define CONF_DMAC_TRIGACT_13 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_13
+#ifndef CONF_DMAC_LVL_13
+#define CONF_DMAC_LVL_13 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_13
+#ifndef CONF_DMAC_EVOE_13
+#define CONF_DMAC_EVOE_13 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_13
+#ifndef CONF_DMAC_EVIE_13
+#define CONF_DMAC_EVIE_13 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_13
+#ifndef CONF_DMAC_EVACT_13
+#define CONF_DMAC_EVACT_13 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_13
+#ifndef CONF_DMAC_STEPSIZE_13
+#define CONF_DMAC_STEPSIZE_13 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_13
+#ifndef CONF_DMAC_STEPSEL_13
+#define CONF_DMAC_STEPSEL_13 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_13
+#ifndef CONF_DMAC_BLOCKACT_13
+#define CONF_DMAC_BLOCKACT_13 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_13
+#ifndef CONF_DMAC_EVOSEL_13
+#define CONF_DMAC_EVOSEL_13 0
+#endif
+// </e>
+
+// <e> Channel 14 settings
+// <id> dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 14 is running in standby mode or not
+// <id> dmac_runstdby_14
+#ifndef CONF_DMAC_RUNSTDBY_14
+#define CONF_DMAC_RUNSTDBY_14 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_14
+#ifndef CONF_DMAC_TRIGACT_14
+#define CONF_DMAC_TRIGACT_14 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_14
+#ifndef CONF_DMAC_LVL_14
+#define CONF_DMAC_LVL_14 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_14
+#ifndef CONF_DMAC_EVOE_14
+#define CONF_DMAC_EVOE_14 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_14
+#ifndef CONF_DMAC_EVIE_14
+#define CONF_DMAC_EVIE_14 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_14
+#ifndef CONF_DMAC_EVACT_14
+#define CONF_DMAC_EVACT_14 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_14
+#ifndef CONF_DMAC_STEPSIZE_14
+#define CONF_DMAC_STEPSIZE_14 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_14
+#ifndef CONF_DMAC_STEPSEL_14
+#define CONF_DMAC_STEPSEL_14 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_14
+#ifndef CONF_DMAC_BLOCKACT_14
+#define CONF_DMAC_BLOCKACT_14 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_14
+#ifndef CONF_DMAC_EVOSEL_14
+#define CONF_DMAC_EVOSEL_14 0
+#endif
+// </e>
+
+// <e> Channel 15 settings
+// <id> dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 15 is running in standby mode or not
+// <id> dmac_runstdby_15
+#ifndef CONF_DMAC_RUNSTDBY_15
+#define CONF_DMAC_RUNSTDBY_15 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_15
+#ifndef CONF_DMAC_TRIGACT_15
+#define CONF_DMAC_TRIGACT_15 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_15
+#ifndef CONF_DMAC_LVL_15
+#define CONF_DMAC_LVL_15 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_15
+#ifndef CONF_DMAC_EVOE_15
+#define CONF_DMAC_EVOE_15 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_15
+#ifndef CONF_DMAC_EVIE_15
+#define CONF_DMAC_EVIE_15 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_15
+#ifndef CONF_DMAC_EVACT_15
+#define CONF_DMAC_EVACT_15 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_15
+#ifndef CONF_DMAC_STEPSIZE_15
+#define CONF_DMAC_STEPSIZE_15 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_15
+#ifndef CONF_DMAC_STEPSEL_15
+#define CONF_DMAC_STEPSEL_15 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_15
+#ifndef CONF_DMAC_BLOCKACT_15
+#define CONF_DMAC_BLOCKACT_15 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_15
+#ifndef CONF_DMAC_EVOSEL_15
+#define CONF_DMAC_EVOSEL_15 0
+#endif
+// </e>
+
+// <e> Channel 16 settings
+// <id> dmac_channel_16_settings
+#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
+#define CONF_DMAC_CHANNEL_16_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 16 is running in standby mode or not
+// <id> dmac_runstdby_16
+#ifndef CONF_DMAC_RUNSTDBY_16
+#define CONF_DMAC_RUNSTDBY_16 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_16
+#ifndef CONF_DMAC_TRIGACT_16
+#define CONF_DMAC_TRIGACT_16 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_16
+#ifndef CONF_DMAC_TRIGSRC_16
+#define CONF_DMAC_TRIGSRC_16 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_16
+#ifndef CONF_DMAC_LVL_16
+#define CONF_DMAC_LVL_16 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_16
+#ifndef CONF_DMAC_EVOE_16
+#define CONF_DMAC_EVOE_16 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_16
+#ifndef CONF_DMAC_EVIE_16
+#define CONF_DMAC_EVIE_16 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_16
+#ifndef CONF_DMAC_EVACT_16
+#define CONF_DMAC_EVACT_16 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_16
+#ifndef CONF_DMAC_STEPSIZE_16
+#define CONF_DMAC_STEPSIZE_16 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_16
+#ifndef CONF_DMAC_STEPSEL_16
+#define CONF_DMAC_STEPSEL_16 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_16
+#ifndef CONF_DMAC_SRCINC_16
+#define CONF_DMAC_SRCINC_16 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_16
+#ifndef CONF_DMAC_DSTINC_16
+#define CONF_DMAC_DSTINC_16 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_16
+#ifndef CONF_DMAC_BEATSIZE_16
+#define CONF_DMAC_BEATSIZE_16 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_16
+#ifndef CONF_DMAC_BLOCKACT_16
+#define CONF_DMAC_BLOCKACT_16 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_16
+#ifndef CONF_DMAC_EVOSEL_16
+#define CONF_DMAC_EVOSEL_16 0
+#endif
+// </e>
+
+// <e> Channel 17 settings
+// <id> dmac_channel_17_settings
+#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
+#define CONF_DMAC_CHANNEL_17_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 17 is running in standby mode or not
+// <id> dmac_runstdby_17
+#ifndef CONF_DMAC_RUNSTDBY_17
+#define CONF_DMAC_RUNSTDBY_17 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_17
+#ifndef CONF_DMAC_TRIGACT_17
+#define CONF_DMAC_TRIGACT_17 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_17
+#ifndef CONF_DMAC_TRIGSRC_17
+#define CONF_DMAC_TRIGSRC_17 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_17
+#ifndef CONF_DMAC_LVL_17
+#define CONF_DMAC_LVL_17 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_17
+#ifndef CONF_DMAC_EVOE_17
+#define CONF_DMAC_EVOE_17 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_17
+#ifndef CONF_DMAC_EVIE_17
+#define CONF_DMAC_EVIE_17 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_17
+#ifndef CONF_DMAC_EVACT_17
+#define CONF_DMAC_EVACT_17 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_17
+#ifndef CONF_DMAC_STEPSIZE_17
+#define CONF_DMAC_STEPSIZE_17 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_17
+#ifndef CONF_DMAC_STEPSEL_17
+#define CONF_DMAC_STEPSEL_17 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_17
+#ifndef CONF_DMAC_SRCINC_17
+#define CONF_DMAC_SRCINC_17 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_17
+#ifndef CONF_DMAC_DSTINC_17
+#define CONF_DMAC_DSTINC_17 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_17
+#ifndef CONF_DMAC_BEATSIZE_17
+#define CONF_DMAC_BEATSIZE_17 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_17
+#ifndef CONF_DMAC_BLOCKACT_17
+#define CONF_DMAC_BLOCKACT_17 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_17
+#ifndef CONF_DMAC_EVOSEL_17
+#define CONF_DMAC_EVOSEL_17 0
+#endif
+// </e>
+
+// <e> Channel 18 settings
+// <id> dmac_channel_18_settings
+#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
+#define CONF_DMAC_CHANNEL_18_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 18 is running in standby mode or not
+// <id> dmac_runstdby_18
+#ifndef CONF_DMAC_RUNSTDBY_18
+#define CONF_DMAC_RUNSTDBY_18 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_18
+#ifndef CONF_DMAC_TRIGACT_18
+#define CONF_DMAC_TRIGACT_18 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_18
+#ifndef CONF_DMAC_TRIGSRC_18
+#define CONF_DMAC_TRIGSRC_18 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_18
+#ifndef CONF_DMAC_LVL_18
+#define CONF_DMAC_LVL_18 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_18
+#ifndef CONF_DMAC_EVOE_18
+#define CONF_DMAC_EVOE_18 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_18
+#ifndef CONF_DMAC_EVIE_18
+#define CONF_DMAC_EVIE_18 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_18
+#ifndef CONF_DMAC_EVACT_18
+#define CONF_DMAC_EVACT_18 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_18
+#ifndef CONF_DMAC_STEPSIZE_18
+#define CONF_DMAC_STEPSIZE_18 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_18
+#ifndef CONF_DMAC_STEPSEL_18
+#define CONF_DMAC_STEPSEL_18 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_18
+#ifndef CONF_DMAC_SRCINC_18
+#define CONF_DMAC_SRCINC_18 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_18
+#ifndef CONF_DMAC_DSTINC_18
+#define CONF_DMAC_DSTINC_18 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_18
+#ifndef CONF_DMAC_BEATSIZE_18
+#define CONF_DMAC_BEATSIZE_18 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_18
+#ifndef CONF_DMAC_BLOCKACT_18
+#define CONF_DMAC_BLOCKACT_18 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_18
+#ifndef CONF_DMAC_EVOSEL_18
+#define CONF_DMAC_EVOSEL_18 0
+#endif
+// </e>
+
+// <e> Channel 19 settings
+// <id> dmac_channel_19_settings
+#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
+#define CONF_DMAC_CHANNEL_19_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 19 is running in standby mode or not
+// <id> dmac_runstdby_19
+#ifndef CONF_DMAC_RUNSTDBY_19
+#define CONF_DMAC_RUNSTDBY_19 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_19
+#ifndef CONF_DMAC_TRIGACT_19
+#define CONF_DMAC_TRIGACT_19 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_19
+#ifndef CONF_DMAC_TRIGSRC_19
+#define CONF_DMAC_TRIGSRC_19 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_19
+#ifndef CONF_DMAC_LVL_19
+#define CONF_DMAC_LVL_19 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_19
+#ifndef CONF_DMAC_EVOE_19
+#define CONF_DMAC_EVOE_19 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_19
+#ifndef CONF_DMAC_EVIE_19
+#define CONF_DMAC_EVIE_19 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_19
+#ifndef CONF_DMAC_EVACT_19
+#define CONF_DMAC_EVACT_19 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_19
+#ifndef CONF_DMAC_STEPSIZE_19
+#define CONF_DMAC_STEPSIZE_19 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_19
+#ifndef CONF_DMAC_STEPSEL_19
+#define CONF_DMAC_STEPSEL_19 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_19
+#ifndef CONF_DMAC_SRCINC_19
+#define CONF_DMAC_SRCINC_19 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_19
+#ifndef CONF_DMAC_DSTINC_19
+#define CONF_DMAC_DSTINC_19 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_19
+#ifndef CONF_DMAC_BEATSIZE_19
+#define CONF_DMAC_BEATSIZE_19 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_19
+#ifndef CONF_DMAC_BLOCKACT_19
+#define CONF_DMAC_BLOCKACT_19 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_19
+#ifndef CONF_DMAC_EVOSEL_19
+#define CONF_DMAC_EVOSEL_19 0
+#endif
+// </e>
+
+// <e> Channel 20 settings
+// <id> dmac_channel_20_settings
+#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
+#define CONF_DMAC_CHANNEL_20_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 20 is running in standby mode or not
+// <id> dmac_runstdby_20
+#ifndef CONF_DMAC_RUNSTDBY_20
+#define CONF_DMAC_RUNSTDBY_20 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_20
+#ifndef CONF_DMAC_TRIGACT_20
+#define CONF_DMAC_TRIGACT_20 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_20
+#ifndef CONF_DMAC_TRIGSRC_20
+#define CONF_DMAC_TRIGSRC_20 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_20
+#ifndef CONF_DMAC_LVL_20
+#define CONF_DMAC_LVL_20 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_20
+#ifndef CONF_DMAC_EVOE_20
+#define CONF_DMAC_EVOE_20 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_20
+#ifndef CONF_DMAC_EVIE_20
+#define CONF_DMAC_EVIE_20 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_20
+#ifndef CONF_DMAC_EVACT_20
+#define CONF_DMAC_EVACT_20 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_20
+#ifndef CONF_DMAC_STEPSIZE_20
+#define CONF_DMAC_STEPSIZE_20 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_20
+#ifndef CONF_DMAC_STEPSEL_20
+#define CONF_DMAC_STEPSEL_20 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_20
+#ifndef CONF_DMAC_SRCINC_20
+#define CONF_DMAC_SRCINC_20 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_20
+#ifndef CONF_DMAC_DSTINC_20
+#define CONF_DMAC_DSTINC_20 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_20
+#ifndef CONF_DMAC_BEATSIZE_20
+#define CONF_DMAC_BEATSIZE_20 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_20
+#ifndef CONF_DMAC_BLOCKACT_20
+#define CONF_DMAC_BLOCKACT_20 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_20
+#ifndef CONF_DMAC_EVOSEL_20
+#define CONF_DMAC_EVOSEL_20 0
+#endif
+// </e>
+
+// <e> Channel 21 settings
+// <id> dmac_channel_21_settings
+#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
+#define CONF_DMAC_CHANNEL_21_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 21 is running in standby mode or not
+// <id> dmac_runstdby_21
+#ifndef CONF_DMAC_RUNSTDBY_21
+#define CONF_DMAC_RUNSTDBY_21 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_21
+#ifndef CONF_DMAC_TRIGACT_21
+#define CONF_DMAC_TRIGACT_21 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_21
+#ifndef CONF_DMAC_TRIGSRC_21
+#define CONF_DMAC_TRIGSRC_21 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_21
+#ifndef CONF_DMAC_LVL_21
+#define CONF_DMAC_LVL_21 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_21
+#ifndef CONF_DMAC_EVOE_21
+#define CONF_DMAC_EVOE_21 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_21
+#ifndef CONF_DMAC_EVIE_21
+#define CONF_DMAC_EVIE_21 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_21
+#ifndef CONF_DMAC_EVACT_21
+#define CONF_DMAC_EVACT_21 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_21
+#ifndef CONF_DMAC_STEPSIZE_21
+#define CONF_DMAC_STEPSIZE_21 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_21
+#ifndef CONF_DMAC_STEPSEL_21
+#define CONF_DMAC_STEPSEL_21 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_21
+#ifndef CONF_DMAC_SRCINC_21
+#define CONF_DMAC_SRCINC_21 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_21
+#ifndef CONF_DMAC_DSTINC_21
+#define CONF_DMAC_DSTINC_21 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_21
+#ifndef CONF_DMAC_BEATSIZE_21
+#define CONF_DMAC_BEATSIZE_21 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_21
+#ifndef CONF_DMAC_BLOCKACT_21
+#define CONF_DMAC_BLOCKACT_21 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_21
+#ifndef CONF_DMAC_EVOSEL_21
+#define CONF_DMAC_EVOSEL_21 0
+#endif
+// </e>
+
+// <e> Channel 22 settings
+// <id> dmac_channel_22_settings
+#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
+#define CONF_DMAC_CHANNEL_22_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 22 is running in standby mode or not
+// <id> dmac_runstdby_22
+#ifndef CONF_DMAC_RUNSTDBY_22
+#define CONF_DMAC_RUNSTDBY_22 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_22
+#ifndef CONF_DMAC_TRIGACT_22
+#define CONF_DMAC_TRIGACT_22 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_22
+#ifndef CONF_DMAC_TRIGSRC_22
+#define CONF_DMAC_TRIGSRC_22 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_22
+#ifndef CONF_DMAC_LVL_22
+#define CONF_DMAC_LVL_22 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_22
+#ifndef CONF_DMAC_EVOE_22
+#define CONF_DMAC_EVOE_22 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_22
+#ifndef CONF_DMAC_EVIE_22
+#define CONF_DMAC_EVIE_22 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_22
+#ifndef CONF_DMAC_EVACT_22
+#define CONF_DMAC_EVACT_22 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_22
+#ifndef CONF_DMAC_STEPSIZE_22
+#define CONF_DMAC_STEPSIZE_22 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_22
+#ifndef CONF_DMAC_STEPSEL_22
+#define CONF_DMAC_STEPSEL_22 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_22
+#ifndef CONF_DMAC_SRCINC_22
+#define CONF_DMAC_SRCINC_22 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_22
+#ifndef CONF_DMAC_DSTINC_22
+#define CONF_DMAC_DSTINC_22 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_22
+#ifndef CONF_DMAC_BEATSIZE_22
+#define CONF_DMAC_BEATSIZE_22 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_22
+#ifndef CONF_DMAC_BLOCKACT_22
+#define CONF_DMAC_BLOCKACT_22 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_22
+#ifndef CONF_DMAC_EVOSEL_22
+#define CONF_DMAC_EVOSEL_22 0
+#endif
+// </e>
+
+// <e> Channel 23 settings
+// <id> dmac_channel_23_settings
+#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
+#define CONF_DMAC_CHANNEL_23_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 23 is running in standby mode or not
+// <id> dmac_runstdby_23
+#ifndef CONF_DMAC_RUNSTDBY_23
+#define CONF_DMAC_RUNSTDBY_23 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_23
+#ifndef CONF_DMAC_TRIGACT_23
+#define CONF_DMAC_TRIGACT_23 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_23
+#ifndef CONF_DMAC_TRIGSRC_23
+#define CONF_DMAC_TRIGSRC_23 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_23
+#ifndef CONF_DMAC_LVL_23
+#define CONF_DMAC_LVL_23 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_23
+#ifndef CONF_DMAC_EVOE_23
+#define CONF_DMAC_EVOE_23 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_23
+#ifndef CONF_DMAC_EVIE_23
+#define CONF_DMAC_EVIE_23 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_23
+#ifndef CONF_DMAC_EVACT_23
+#define CONF_DMAC_EVACT_23 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_23
+#ifndef CONF_DMAC_STEPSIZE_23
+#define CONF_DMAC_STEPSIZE_23 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_23
+#ifndef CONF_DMAC_STEPSEL_23
+#define CONF_DMAC_STEPSEL_23 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_23
+#ifndef CONF_DMAC_SRCINC_23
+#define CONF_DMAC_SRCINC_23 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_23
+#ifndef CONF_DMAC_DSTINC_23
+#define CONF_DMAC_DSTINC_23 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_23
+#ifndef CONF_DMAC_BEATSIZE_23
+#define CONF_DMAC_BEATSIZE_23 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_23
+#ifndef CONF_DMAC_BLOCKACT_23
+#define CONF_DMAC_BLOCKACT_23 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_23
+#ifndef CONF_DMAC_EVOSEL_23
+#define CONF_DMAC_EVOSEL_23 0
+#endif
+// </e>
+
+// <e> Channel 24 settings
+// <id> dmac_channel_24_settings
+#ifndef CONF_DMAC_CHANNEL_24_SETTINGS
+#define CONF_DMAC_CHANNEL_24_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 24 is running in standby mode or not
+// <id> dmac_runstdby_24
+#ifndef CONF_DMAC_RUNSTDBY_24
+#define CONF_DMAC_RUNSTDBY_24 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_24
+#ifndef CONF_DMAC_TRIGACT_24
+#define CONF_DMAC_TRIGACT_24 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_24
+#ifndef CONF_DMAC_TRIGSRC_24
+#define CONF_DMAC_TRIGSRC_24 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_24
+#ifndef CONF_DMAC_LVL_24
+#define CONF_DMAC_LVL_24 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_24
+#ifndef CONF_DMAC_EVOE_24
+#define CONF_DMAC_EVOE_24 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_24
+#ifndef CONF_DMAC_EVIE_24
+#define CONF_DMAC_EVIE_24 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_24
+#ifndef CONF_DMAC_EVACT_24
+#define CONF_DMAC_EVACT_24 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_24
+#ifndef CONF_DMAC_STEPSIZE_24
+#define CONF_DMAC_STEPSIZE_24 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_24
+#ifndef CONF_DMAC_STEPSEL_24
+#define CONF_DMAC_STEPSEL_24 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_24
+#ifndef CONF_DMAC_SRCINC_24
+#define CONF_DMAC_SRCINC_24 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_24
+#ifndef CONF_DMAC_DSTINC_24
+#define CONF_DMAC_DSTINC_24 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_24
+#ifndef CONF_DMAC_BEATSIZE_24
+#define CONF_DMAC_BEATSIZE_24 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_24
+#ifndef CONF_DMAC_BLOCKACT_24
+#define CONF_DMAC_BLOCKACT_24 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_24
+#ifndef CONF_DMAC_EVOSEL_24
+#define CONF_DMAC_EVOSEL_24 0
+#endif
+// </e>
+
+// <e> Channel 25 settings
+// <id> dmac_channel_25_settings
+#ifndef CONF_DMAC_CHANNEL_25_SETTINGS
+#define CONF_DMAC_CHANNEL_25_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 25 is running in standby mode or not
+// <id> dmac_runstdby_25
+#ifndef CONF_DMAC_RUNSTDBY_25
+#define CONF_DMAC_RUNSTDBY_25 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_25
+#ifndef CONF_DMAC_TRIGACT_25
+#define CONF_DMAC_TRIGACT_25 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_25
+#ifndef CONF_DMAC_TRIGSRC_25
+#define CONF_DMAC_TRIGSRC_25 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_25
+#ifndef CONF_DMAC_LVL_25
+#define CONF_DMAC_LVL_25 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_25
+#ifndef CONF_DMAC_EVOE_25
+#define CONF_DMAC_EVOE_25 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_25
+#ifndef CONF_DMAC_EVIE_25
+#define CONF_DMAC_EVIE_25 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_25
+#ifndef CONF_DMAC_EVACT_25
+#define CONF_DMAC_EVACT_25 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_25
+#ifndef CONF_DMAC_STEPSIZE_25
+#define CONF_DMAC_STEPSIZE_25 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_25
+#ifndef CONF_DMAC_STEPSEL_25
+#define CONF_DMAC_STEPSEL_25 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_25
+#ifndef CONF_DMAC_SRCINC_25
+#define CONF_DMAC_SRCINC_25 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_25
+#ifndef CONF_DMAC_DSTINC_25
+#define CONF_DMAC_DSTINC_25 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_25
+#ifndef CONF_DMAC_BEATSIZE_25
+#define CONF_DMAC_BEATSIZE_25 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_25
+#ifndef CONF_DMAC_BLOCKACT_25
+#define CONF_DMAC_BLOCKACT_25 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_25
+#ifndef CONF_DMAC_EVOSEL_25
+#define CONF_DMAC_EVOSEL_25 0
+#endif
+// </e>
+
+// <e> Channel 26 settings
+// <id> dmac_channel_26_settings
+#ifndef CONF_DMAC_CHANNEL_26_SETTINGS
+#define CONF_DMAC_CHANNEL_26_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 26 is running in standby mode or not
+// <id> dmac_runstdby_26
+#ifndef CONF_DMAC_RUNSTDBY_26
+#define CONF_DMAC_RUNSTDBY_26 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_26
+#ifndef CONF_DMAC_TRIGACT_26
+#define CONF_DMAC_TRIGACT_26 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_26
+#ifndef CONF_DMAC_TRIGSRC_26
+#define CONF_DMAC_TRIGSRC_26 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_26
+#ifndef CONF_DMAC_LVL_26
+#define CONF_DMAC_LVL_26 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_26
+#ifndef CONF_DMAC_EVOE_26
+#define CONF_DMAC_EVOE_26 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_26
+#ifndef CONF_DMAC_EVIE_26
+#define CONF_DMAC_EVIE_26 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_26
+#ifndef CONF_DMAC_EVACT_26
+#define CONF_DMAC_EVACT_26 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_26
+#ifndef CONF_DMAC_STEPSIZE_26
+#define CONF_DMAC_STEPSIZE_26 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_26
+#ifndef CONF_DMAC_STEPSEL_26
+#define CONF_DMAC_STEPSEL_26 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_26
+#ifndef CONF_DMAC_SRCINC_26
+#define CONF_DMAC_SRCINC_26 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_26
+#ifndef CONF_DMAC_DSTINC_26
+#define CONF_DMAC_DSTINC_26 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_26
+#ifndef CONF_DMAC_BEATSIZE_26
+#define CONF_DMAC_BEATSIZE_26 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_26
+#ifndef CONF_DMAC_BLOCKACT_26
+#define CONF_DMAC_BLOCKACT_26 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_26
+#ifndef CONF_DMAC_EVOSEL_26
+#define CONF_DMAC_EVOSEL_26 0
+#endif
+// </e>
+
+// <e> Channel 27 settings
+// <id> dmac_channel_27_settings
+#ifndef CONF_DMAC_CHANNEL_27_SETTINGS
+#define CONF_DMAC_CHANNEL_27_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 27 is running in standby mode or not
+// <id> dmac_runstdby_27
+#ifndef CONF_DMAC_RUNSTDBY_27
+#define CONF_DMAC_RUNSTDBY_27 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_27
+#ifndef CONF_DMAC_TRIGACT_27
+#define CONF_DMAC_TRIGACT_27 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_27
+#ifndef CONF_DMAC_TRIGSRC_27
+#define CONF_DMAC_TRIGSRC_27 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_27
+#ifndef CONF_DMAC_LVL_27
+#define CONF_DMAC_LVL_27 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_27
+#ifndef CONF_DMAC_EVOE_27
+#define CONF_DMAC_EVOE_27 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_27
+#ifndef CONF_DMAC_EVIE_27
+#define CONF_DMAC_EVIE_27 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_27
+#ifndef CONF_DMAC_EVACT_27
+#define CONF_DMAC_EVACT_27 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_27
+#ifndef CONF_DMAC_STEPSIZE_27
+#define CONF_DMAC_STEPSIZE_27 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_27
+#ifndef CONF_DMAC_STEPSEL_27
+#define CONF_DMAC_STEPSEL_27 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_27
+#ifndef CONF_DMAC_SRCINC_27
+#define CONF_DMAC_SRCINC_27 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_27
+#ifndef CONF_DMAC_DSTINC_27
+#define CONF_DMAC_DSTINC_27 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_27
+#ifndef CONF_DMAC_BEATSIZE_27
+#define CONF_DMAC_BEATSIZE_27 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_27
+#ifndef CONF_DMAC_BLOCKACT_27
+#define CONF_DMAC_BLOCKACT_27 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_27
+#ifndef CONF_DMAC_EVOSEL_27
+#define CONF_DMAC_EVOSEL_27 0
+#endif
+// </e>
+
+// <e> Channel 28 settings
+// <id> dmac_channel_28_settings
+#ifndef CONF_DMAC_CHANNEL_28_SETTINGS
+#define CONF_DMAC_CHANNEL_28_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 28 is running in standby mode or not
+// <id> dmac_runstdby_28
+#ifndef CONF_DMAC_RUNSTDBY_28
+#define CONF_DMAC_RUNSTDBY_28 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_28
+#ifndef CONF_DMAC_TRIGACT_28
+#define CONF_DMAC_TRIGACT_28 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_28
+#ifndef CONF_DMAC_TRIGSRC_28
+#define CONF_DMAC_TRIGSRC_28 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_28
+#ifndef CONF_DMAC_LVL_28
+#define CONF_DMAC_LVL_28 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_28
+#ifndef CONF_DMAC_EVOE_28
+#define CONF_DMAC_EVOE_28 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_28
+#ifndef CONF_DMAC_EVIE_28
+#define CONF_DMAC_EVIE_28 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_28
+#ifndef CONF_DMAC_EVACT_28
+#define CONF_DMAC_EVACT_28 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_28
+#ifndef CONF_DMAC_STEPSIZE_28
+#define CONF_DMAC_STEPSIZE_28 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_28
+#ifndef CONF_DMAC_STEPSEL_28
+#define CONF_DMAC_STEPSEL_28 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_28
+#ifndef CONF_DMAC_SRCINC_28
+#define CONF_DMAC_SRCINC_28 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_28
+#ifndef CONF_DMAC_DSTINC_28
+#define CONF_DMAC_DSTINC_28 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_28
+#ifndef CONF_DMAC_BEATSIZE_28
+#define CONF_DMAC_BEATSIZE_28 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_28
+#ifndef CONF_DMAC_BLOCKACT_28
+#define CONF_DMAC_BLOCKACT_28 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_28
+#ifndef CONF_DMAC_EVOSEL_28
+#define CONF_DMAC_EVOSEL_28 0
+#endif
+// </e>
+
+// <e> Channel 29 settings
+// <id> dmac_channel_29_settings
+#ifndef CONF_DMAC_CHANNEL_29_SETTINGS
+#define CONF_DMAC_CHANNEL_29_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 29 is running in standby mode or not
+// <id> dmac_runstdby_29
+#ifndef CONF_DMAC_RUNSTDBY_29
+#define CONF_DMAC_RUNSTDBY_29 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_29
+#ifndef CONF_DMAC_TRIGACT_29
+#define CONF_DMAC_TRIGACT_29 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_29
+#ifndef CONF_DMAC_TRIGSRC_29
+#define CONF_DMAC_TRIGSRC_29 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_29
+#ifndef CONF_DMAC_LVL_29
+#define CONF_DMAC_LVL_29 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_29
+#ifndef CONF_DMAC_EVOE_29
+#define CONF_DMAC_EVOE_29 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_29
+#ifndef CONF_DMAC_EVIE_29
+#define CONF_DMAC_EVIE_29 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_29
+#ifndef CONF_DMAC_EVACT_29
+#define CONF_DMAC_EVACT_29 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_29
+#ifndef CONF_DMAC_STEPSIZE_29
+#define CONF_DMAC_STEPSIZE_29 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_29
+#ifndef CONF_DMAC_STEPSEL_29
+#define CONF_DMAC_STEPSEL_29 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_29
+#ifndef CONF_DMAC_SRCINC_29
+#define CONF_DMAC_SRCINC_29 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_29
+#ifndef CONF_DMAC_DSTINC_29
+#define CONF_DMAC_DSTINC_29 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_29
+#ifndef CONF_DMAC_BEATSIZE_29
+#define CONF_DMAC_BEATSIZE_29 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_29
+#ifndef CONF_DMAC_BLOCKACT_29
+#define CONF_DMAC_BLOCKACT_29 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_29
+#ifndef CONF_DMAC_EVOSEL_29
+#define CONF_DMAC_EVOSEL_29 0
+#endif
+// </e>
+
+// <e> Channel 30 settings
+// <id> dmac_channel_30_settings
+#ifndef CONF_DMAC_CHANNEL_30_SETTINGS
+#define CONF_DMAC_CHANNEL_30_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 30 is running in standby mode or not
+// <id> dmac_runstdby_30
+#ifndef CONF_DMAC_RUNSTDBY_30
+#define CONF_DMAC_RUNSTDBY_30 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_30
+#ifndef CONF_DMAC_TRIGACT_30
+#define CONF_DMAC_TRIGACT_30 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_30
+#ifndef CONF_DMAC_TRIGSRC_30
+#define CONF_DMAC_TRIGSRC_30 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_30
+#ifndef CONF_DMAC_LVL_30
+#define CONF_DMAC_LVL_30 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_30
+#ifndef CONF_DMAC_EVOE_30
+#define CONF_DMAC_EVOE_30 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_30
+#ifndef CONF_DMAC_EVIE_30
+#define CONF_DMAC_EVIE_30 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_30
+#ifndef CONF_DMAC_EVACT_30
+#define CONF_DMAC_EVACT_30 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_30
+#ifndef CONF_DMAC_STEPSIZE_30
+#define CONF_DMAC_STEPSIZE_30 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_30
+#ifndef CONF_DMAC_STEPSEL_30
+#define CONF_DMAC_STEPSEL_30 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_30
+#ifndef CONF_DMAC_SRCINC_30
+#define CONF_DMAC_SRCINC_30 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_30
+#ifndef CONF_DMAC_DSTINC_30
+#define CONF_DMAC_DSTINC_30 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_30
+#ifndef CONF_DMAC_BEATSIZE_30
+#define CONF_DMAC_BEATSIZE_30 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_30
+#ifndef CONF_DMAC_BLOCKACT_30
+#define CONF_DMAC_BLOCKACT_30 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_30
+#ifndef CONF_DMAC_EVOSEL_30
+#define CONF_DMAC_EVOSEL_30 0
+#endif
+// </e>
+
+// <e> Channel 31 settings
+// <id> dmac_channel_31_settings
+#ifndef CONF_DMAC_CHANNEL_31_SETTINGS
+#define CONF_DMAC_CHANNEL_31_SETTINGS 0
+#endif
+
+// <q> Channel Run in Standby
+// <i> Indicates whether channel 31 is running in standby mode or not
+// <id> dmac_runstdby_31
+#ifndef CONF_DMAC_RUNSTDBY_31
+#define CONF_DMAC_RUNSTDBY_31 0
+#endif
+
+// <o> Trigger action
+// <0=> One trigger required for each block transfer
+// <2=> One trigger required for each beat transfer
+// <3=> One trigger required for each transaction
+// <i> Defines the trigger action used for a transfer
+// <id> dmac_trigact_31
+#ifndef CONF_DMAC_TRIGACT_31
+#define CONF_DMAC_TRIGACT_31 0
+#endif
+
+// <o> Trigger source
+// <0x00=> Only software/event triggers
+// <0x01=> RTC Time Stamp Trigger
+// <0x02=> DSU Debug Communication Channel 0 Trigger
+// <0x03=> DSU Debug Communication Channel 1 Trigger
+// <0x04=> SERCOM0 RX Trigger
+// <0x05=> SERCOM0 TX Trigger
+// <0x06=> SERCOM1 RX Trigger
+// <0x07=> SERCOM1 TX Trigger
+// <0x08=> SERCOM2 RX Trigger
+// <0x09=> SERCOM2 TX Trigger
+// <0x0A=> SERCOM3 RX Trigger
+// <0x0B=> SERCOM3 TX Trigger
+// <0x0C=> SERCOM4 RX Trigger
+// <0x0D=> SERCOM4 TX Trigger
+// <0x0E=> SERCOM5 RX Trigger
+// <0x0F=> SERCOM5 TX Trigger
+// <0x10=> SERCOM6 RX Trigger
+// <0x11=> SERCOM6 TX Trigger
+// <0x12=> SERCOM7 RX Trigger
+// <0x13=> SERCOM7 TX Trigger
+// <0x14=> CAN0 DEBUG Trigger
+// <0x15=> CAN1 DEBUG Trigger
+// <0x16=> TCC0 Overflow Trigger Trigger
+// <0x17=> TCC0 Match/Compare 0 Trigger Trigger
+// <0x18=> TCC0 Match/Compare 1 Trigger Trigger
+// <0x19=> TCC0 Match/Compare 2 Trigger Trigger
+// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger
+// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger
+// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger
+// <0x1D=> TCC1 Overflow Trigger Trigger
+// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger
+// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger
+// <0x20=> TCC1 Match/Compare 2 Trigger Trigger
+// <0x21=> TCC1 Match/Compare 3 Trigger Trigger
+// <0x22=> TCC2 Overflow Trigger Trigger
+// <0x23=> TCC2 Match/Compare 0 Trigger Trigger
+// <0x24=> TCC2 Match/Compare 1 Trigger Trigger
+// <0x25=> TCC2 Match/Compare 2 Trigger Trigger
+// <0x26=> TCC3 Overflow Trigger Trigger
+// <0x27=> TCC3 Match/Compare 0 Trigger Trigger
+// <0x28=> TCC3 Match/Compare 1 Trigger Trigger
+// <0x29=> TCC4 Overflow Trigger Trigger
+// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger
+// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger
+// <0x2C=> TC0 Overflow Trigger
+// <0x2D=> TC0 Match/Compare 0 Trigger
+// <0x2E=> TC0 Match/Compare 1 Trigger
+// <0x2F=> TC1 Overflow Trigger
+// <0x30=> TC1 Match/Compare 0 Trigger
+// <0x31=> TC1 Match/Compare 1 Trigger
+// <0x32=> TC2 Overflow Trigger
+// <0x33=> TC2 Match/Compare 0 Trigger
+// <0x34=> TC2 Match/Compare 1 Trigger
+// <0x35=> TC3 Overflow Trigger
+// <0x36=> TC3 Match/Compare 0 Trigger
+// <0x37=> TC3 Match/Compare 1 Trigger
+// <0x38=> TC4 Overflow Trigger
+// <0x39=> TC4 Match/Compare 0 Trigger
+// <0x3A=> TC4 Match/Compare 1 Trigger
+// <0x3B=> TC5 Overflow Trigger
+// <0x3C=> TC5 Match/Compare 0 Trigger
+// <0x3D=> TC5 Match/Compare 1 Trigger
+// <0x3E=> TC6 Overflow Trigger
+// <0x3F=> TC6 Match/Compare 0 Trigger
+// <0x40=> TC6 Match/Compare 1 Trigger
+// <0x41=> TC7 Overflow Trigger
+// <0x42=> TC7 Match/Compare 0 Trigger
+// <0x43=> TC7 Match/Compare 1 Trigger
+// <0x44=> ADC0 Result Ready Trigger
+// <0x45=> ADC0 Sequencing Trigger
+// <0x46=> ADC1 Result Ready Trigger
+// <0x47=> ADC1 Sequencing Trigger
+// <0x48=> DAC Empty 0 Trigger
+// <0x49=> DAC Empty 1 Trigger
+// <0x4A=> DAC Result Ready 0 Trigger
+// <0x4B=> DAC Result Ready 1 Trigger
+// <0x4C=> I2S Rx 0 Trigger
+// <0x4D=> I2S Rx 1 Trigger
+// <0x4E=> I2S Tx 0 Trigger
+// <0x4F=> I2S Tx 1 Trigger
+// <0x50=> PCC RX Trigger
+// <0x51=> AES Write Trigger
+// <0x52=> AES Read Trigger
+// <0x53=> QSPI Rx Trigger
+// <0x54=> QSPI Tx Trigger
+// <i> Defines the peripheral trigger which is source of the transfer
+// <id> dmac_trifsrc_31
+#ifndef CONF_DMAC_TRIGSRC_31
+#define CONF_DMAC_TRIGSRC_31 0
+#endif
+
+// <o> Channel Arbitration Level
+// <0=> Channel priority 0
+// <1=> Channel priority 1
+// <2=> Channel priority 2
+// <3=> Channel priority 3
+// <i> Defines the arbitration level for this channel
+// <id> dmac_lvl_31
+#ifndef CONF_DMAC_LVL_31
+#define CONF_DMAC_LVL_31 0
+#endif
+
+// <q> Channel Event Output
+// <i> Indicates whether channel event generation is enabled or not
+// <id> dmac_evoe_31
+#ifndef CONF_DMAC_EVOE_31
+#define CONF_DMAC_EVOE_31 0
+#endif
+
+// <q> Channel Event Input
+// <i> Indicates whether channel event reception is enabled or not
+// <id> dmac_evie_31
+#ifndef CONF_DMAC_EVIE_31
+#define CONF_DMAC_EVIE_31 0
+#endif
+
+// <o> Event Input Action
+// <0=> No action
+// <1=> Normal transfer and conditional transfer on strobe trigger
+// <2=> Conditional transfer trigger
+// <3=> Conditional block transfer
+// <4=> Channel suspend operation
+// <5=> Channel resume operation
+// <6=> Skip next block suspend action
+// <i> Defines the event input action
+// <id> dmac_evact_31
+#ifndef CONF_DMAC_EVACT_31
+#define CONF_DMAC_EVACT_31 0
+#endif
+
+// <o> Address Increment Step Size
+// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1
+// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2
+// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4
+// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8
+// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16
+// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32
+// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64
+// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128
+// <i> Defines the address increment step size, applies to source or destination address
+// <id> dmac_stepsize_31
+#ifndef CONF_DMAC_STEPSIZE_31
+#define CONF_DMAC_STEPSIZE_31 0
+#endif
+
+// <o> Step Selection
+// <0=> Step size settings apply to the destination address
+// <1=> Step size settings apply to the source address
+// <i> Defines whether source or destination addresses are using the step size settings
+// <id> dmac_stepsel_31
+#ifndef CONF_DMAC_STEPSEL_31
+#define CONF_DMAC_STEPSEL_31 0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incrementation is enabled or not
+// <id> dmac_srcinc_31
+#ifndef CONF_DMAC_SRCINC_31
+#define CONF_DMAC_SRCINC_31 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incrementation is enabled or not
+// <id> dmac_dstinc_31
+#ifndef CONF_DMAC_DSTINC_31
+#define CONF_DMAC_DSTINC_31 0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_31
+#ifndef CONF_DMAC_BEATSIZE_31
+#define CONF_DMAC_BEATSIZE_31 0
+#endif
+
+// <o> Block Action
+// <0=> Channel will be disabled if it is the last block transfer in the transaction
+// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt
+// <2=> Channel suspend operation is complete
+// <3=> Both channel suspend operation and block interrupt
+// <i> Defines the the DMAC should take after a block transfer has completed
+// <id> dmac_blockact_31
+#ifndef CONF_DMAC_BLOCKACT_31
+#define CONF_DMAC_BLOCKACT_31 0
+#endif
+
+// <o> Event Output Selection
+// <0=> Event generation disabled
+// <1=> Event strobe when block transfer complete
+// <3=> Event strobe when beat transfer complete
+// <i> Defines the event output selection
+// <id> dmac_evosel_31
+#ifndef CONF_DMAC_EVOSEL_31
+#define CONF_DMAC_EVOSEL_31 0
+#endif
+// </e>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_DMAC_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_gclk_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_gclk_config.h
new file mode 100644
index 000000000..73a8a00bf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_gclk_config.h
@@ -0,0 +1,920 @@
+/* Auto-generated config file hpl_gclk_config.h */
+#ifndef HPL_GCLK_CONFIG_H
+#define HPL_GCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> Generic clock generator 0 configuration
+// <i> Indicates whether generic clock 0 configuration is enabled or not
+// <id> enable_gclk_gen_0
+#ifndef CONF_GCLK_GENERATOR_0_CONFIG
+#define CONF_GCLK_GENERATOR_0_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 0 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 0
+// <id> gclk_gen_0_oscillator
+#ifndef CONF_GCLK_GEN_0_SOURCE
+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_0_runstdby
+#ifndef CONF_GCLK_GEN_0_RUNSTDBY
+#define CONF_GCLK_GEN_0_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_0_div_sel
+#ifndef CONF_GCLK_GEN_0_DIVSEL
+#define CONF_GCLK_GEN_0_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_0_oe
+#ifndef CONF_GCLK_GEN_0_OE
+#define CONF_GCLK_GEN_0_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_0_oov
+#ifndef CONF_GCLK_GEN_0_OOV
+#define CONF_GCLK_GEN_0_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_0_idc
+#ifndef CONF_GCLK_GEN_0_IDC
+#define CONF_GCLK_GEN_0_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_0_enable
+#ifndef CONF_GCLK_GEN_0_GENEN
+#define CONF_GCLK_GEN_0_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 0 division <0x0000-0xFFFF>
+// <id> gclk_gen_0_div
+#ifndef CONF_GCLK_GEN_0_DIV
+#define CONF_GCLK_GEN_0_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 1 configuration
+// <i> Indicates whether generic clock 1 configuration is enabled or not
+// <id> enable_gclk_gen_1
+#ifndef CONF_GCLK_GENERATOR_1_CONFIG
+#define CONF_GCLK_GENERATOR_1_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 1 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 1
+// <id> gclk_gen_1_oscillator
+#ifndef CONF_GCLK_GEN_1_SOURCE
+#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_1_runstdby
+#ifndef CONF_GCLK_GEN_1_RUNSTDBY
+#define CONF_GCLK_GEN_1_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_1_div_sel
+#ifndef CONF_GCLK_GEN_1_DIVSEL
+#define CONF_GCLK_GEN_1_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_1_oe
+#ifndef CONF_GCLK_GEN_1_OE
+#define CONF_GCLK_GEN_1_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_1_oov
+#ifndef CONF_GCLK_GEN_1_OOV
+#define CONF_GCLK_GEN_1_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_1_idc
+#ifndef CONF_GCLK_GEN_1_IDC
+#define CONF_GCLK_GEN_1_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_1_enable
+#ifndef CONF_GCLK_GEN_1_GENEN
+#define CONF_GCLK_GEN_1_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 1 division <0x0000-0xFFFF>
+// <id> gclk_gen_1_div
+#ifndef CONF_GCLK_GEN_1_DIV
+#define CONF_GCLK_GEN_1_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 2 configuration
+// <i> Indicates whether generic clock 2 configuration is enabled or not
+// <id> enable_gclk_gen_2
+#ifndef CONF_GCLK_GENERATOR_2_CONFIG
+#define CONF_GCLK_GENERATOR_2_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 2 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 2
+// <id> gclk_gen_2_oscillator
+#ifndef CONF_GCLK_GEN_2_SOURCE
+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_2_runstdby
+#ifndef CONF_GCLK_GEN_2_RUNSTDBY
+#define CONF_GCLK_GEN_2_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_2_div_sel
+#ifndef CONF_GCLK_GEN_2_DIVSEL
+#define CONF_GCLK_GEN_2_DIVSEL 1
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_2_oe
+#ifndef CONF_GCLK_GEN_2_OE
+#define CONF_GCLK_GEN_2_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_2_oov
+#ifndef CONF_GCLK_GEN_2_OOV
+#define CONF_GCLK_GEN_2_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_2_idc
+#ifndef CONF_GCLK_GEN_2_IDC
+#define CONF_GCLK_GEN_2_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_2_enable
+#ifndef CONF_GCLK_GEN_2_GENEN
+#define CONF_GCLK_GEN_2_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 2 division <0x0000-0xFFFF>
+// <id> gclk_gen_2_div
+#ifndef CONF_GCLK_GEN_2_DIV
+#define CONF_GCLK_GEN_2_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 3 configuration
+// <i> Indicates whether generic clock 3 configuration is enabled or not
+// <id> enable_gclk_gen_3
+#ifndef CONF_GCLK_GENERATOR_3_CONFIG
+#define CONF_GCLK_GENERATOR_3_CONFIG 1
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 3 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 3
+// <id> gclk_gen_3_oscillator
+#ifndef CONF_GCLK_GEN_3_SOURCE
+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_3_runstdby
+#ifndef CONF_GCLK_GEN_3_RUNSTDBY
+#define CONF_GCLK_GEN_3_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_3_div_sel
+#ifndef CONF_GCLK_GEN_3_DIVSEL
+#define CONF_GCLK_GEN_3_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_3_oe
+#ifndef CONF_GCLK_GEN_3_OE
+#define CONF_GCLK_GEN_3_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_3_oov
+#ifndef CONF_GCLK_GEN_3_OOV
+#define CONF_GCLK_GEN_3_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_3_idc
+#ifndef CONF_GCLK_GEN_3_IDC
+#define CONF_GCLK_GEN_3_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_3_enable
+#ifndef CONF_GCLK_GEN_3_GENEN
+#define CONF_GCLK_GEN_3_GENEN 1
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 3 division <0x0000-0xFFFF>
+// <id> gclk_gen_3_div
+#ifndef CONF_GCLK_GEN_3_DIV
+#define CONF_GCLK_GEN_3_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 4 configuration
+// <i> Indicates whether generic clock 4 configuration is enabled or not
+// <id> enable_gclk_gen_4
+#ifndef CONF_GCLK_GENERATOR_4_CONFIG
+#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 4 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 4
+// <id> gclk_gen_4_oscillator
+#ifndef CONF_GCLK_GEN_4_SOURCE
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_4_runstdby
+#ifndef CONF_GCLK_GEN_4_RUNSTDBY
+#define CONF_GCLK_GEN_4_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_4_div_sel
+#ifndef CONF_GCLK_GEN_4_DIVSEL
+#define CONF_GCLK_GEN_4_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_4_oe
+#ifndef CONF_GCLK_GEN_4_OE
+#define CONF_GCLK_GEN_4_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_4_oov
+#ifndef CONF_GCLK_GEN_4_OOV
+#define CONF_GCLK_GEN_4_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_4_idc
+#ifndef CONF_GCLK_GEN_4_IDC
+#define CONF_GCLK_GEN_4_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_4_enable
+#ifndef CONF_GCLK_GEN_4_GENEN
+#define CONF_GCLK_GEN_4_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 4 division <0x0000-0xFFFF>
+// <id> gclk_gen_4_div
+#ifndef CONF_GCLK_GEN_4_DIV
+#define CONF_GCLK_GEN_4_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 5 configuration
+// <i> Indicates whether generic clock 5 configuration is enabled or not
+// <id> enable_gclk_gen_5
+#ifndef CONF_GCLK_GENERATOR_5_CONFIG
+#define CONF_GCLK_GENERATOR_5_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 5 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 5
+// <id> gclk_gen_5_oscillator
+#ifndef CONF_GCLK_GEN_5_SOURCE
+#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_5_runstdby
+#ifndef CONF_GCLK_GEN_5_RUNSTDBY
+#define CONF_GCLK_GEN_5_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_5_div_sel
+#ifndef CONF_GCLK_GEN_5_DIVSEL
+#define CONF_GCLK_GEN_5_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_5_oe
+#ifndef CONF_GCLK_GEN_5_OE
+#define CONF_GCLK_GEN_5_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_5_oov
+#ifndef CONF_GCLK_GEN_5_OOV
+#define CONF_GCLK_GEN_5_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_5_idc
+#ifndef CONF_GCLK_GEN_5_IDC
+#define CONF_GCLK_GEN_5_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_5_enable
+#ifndef CONF_GCLK_GEN_5_GENEN
+#define CONF_GCLK_GEN_5_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 5 division <0x0000-0xFFFF>
+// <id> gclk_gen_5_div
+#ifndef CONF_GCLK_GEN_5_DIV
+#define CONF_GCLK_GEN_5_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 6 configuration
+// <i> Indicates whether generic clock 6 configuration is enabled or not
+// <id> enable_gclk_gen_6
+#ifndef CONF_GCLK_GENERATOR_6_CONFIG
+#define CONF_GCLK_GENERATOR_6_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 6 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 6
+// <id> gclk_gen_6_oscillator
+#ifndef CONF_GCLK_GEN_6_SOURCE
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_6_runstdby
+#ifndef CONF_GCLK_GEN_6_RUNSTDBY
+#define CONF_GCLK_GEN_6_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_6_div_sel
+#ifndef CONF_GCLK_GEN_6_DIVSEL
+#define CONF_GCLK_GEN_6_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_6_oe
+#ifndef CONF_GCLK_GEN_6_OE
+#define CONF_GCLK_GEN_6_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_6_oov
+#ifndef CONF_GCLK_GEN_6_OOV
+#define CONF_GCLK_GEN_6_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_6_idc
+#ifndef CONF_GCLK_GEN_6_IDC
+#define CONF_GCLK_GEN_6_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_6_enable
+#ifndef CONF_GCLK_GEN_6_GENEN
+#define CONF_GCLK_GEN_6_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 6 division <0x0000-0xFFFF>
+// <id> gclk_gen_6_div
+#ifndef CONF_GCLK_GEN_6_DIV
+#define CONF_GCLK_GEN_6_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 7 configuration
+// <i> Indicates whether generic clock 7 configuration is enabled or not
+// <id> enable_gclk_gen_7
+#ifndef CONF_GCLK_GENERATOR_7_CONFIG
+#define CONF_GCLK_GENERATOR_7_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 7 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 7
+// <id> gclk_gen_7_oscillator
+#ifndef CONF_GCLK_GEN_7_SOURCE
+#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_7_runstdby
+#ifndef CONF_GCLK_GEN_7_RUNSTDBY
+#define CONF_GCLK_GEN_7_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_7_div_sel
+#ifndef CONF_GCLK_GEN_7_DIVSEL
+#define CONF_GCLK_GEN_7_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_7_oe
+#ifndef CONF_GCLK_GEN_7_OE
+#define CONF_GCLK_GEN_7_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_7_oov
+#ifndef CONF_GCLK_GEN_7_OOV
+#define CONF_GCLK_GEN_7_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_7_idc
+#ifndef CONF_GCLK_GEN_7_IDC
+#define CONF_GCLK_GEN_7_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_7_enable
+#ifndef CONF_GCLK_GEN_7_GENEN
+#define CONF_GCLK_GEN_7_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 7 division <0x0000-0xFFFF>
+// <id> gclk_gen_7_div
+#ifndef CONF_GCLK_GEN_7_DIV
+#define CONF_GCLK_GEN_7_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 8 configuration
+// <i> Indicates whether generic clock 8 configuration is enabled or not
+// <id> enable_gclk_gen_8
+#ifndef CONF_GCLK_GENERATOR_8_CONFIG
+#define CONF_GCLK_GENERATOR_8_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 8 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 8
+// <id> gclk_gen_8_oscillator
+#ifndef CONF_GCLK_GEN_8_SOURCE
+#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_8_runstdby
+#ifndef CONF_GCLK_GEN_8_RUNSTDBY
+#define CONF_GCLK_GEN_8_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_8_div_sel
+#ifndef CONF_GCLK_GEN_8_DIVSEL
+#define CONF_GCLK_GEN_8_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_8_oe
+#ifndef CONF_GCLK_GEN_8_OE
+#define CONF_GCLK_GEN_8_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_8_oov
+#ifndef CONF_GCLK_GEN_8_OOV
+#define CONF_GCLK_GEN_8_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_8_idc
+#ifndef CONF_GCLK_GEN_8_IDC
+#define CONF_GCLK_GEN_8_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_8_enable
+#ifndef CONF_GCLK_GEN_8_GENEN
+#define CONF_GCLK_GEN_8_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 8 division <0x0000-0xFFFF>
+// <id> gclk_gen_8_div
+#ifndef CONF_GCLK_GEN_8_DIV
+#define CONF_GCLK_GEN_8_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 9 configuration
+// <i> Indicates whether generic clock 9 configuration is enabled or not
+// <id> enable_gclk_gen_9
+#ifndef CONF_GCLK_GENERATOR_9_CONFIG
+#define CONF_GCLK_GENERATOR_9_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 9 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 9
+// <id> gclk_gen_9_oscillator
+#ifndef CONF_GCLK_GEN_9_SOURCE
+#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_9_runstdby
+#ifndef CONF_GCLK_GEN_9_RUNSTDBY
+#define CONF_GCLK_GEN_9_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_9_div_sel
+#ifndef CONF_GCLK_GEN_9_DIVSEL
+#define CONF_GCLK_GEN_9_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_9_oe
+#ifndef CONF_GCLK_GEN_9_OE
+#define CONF_GCLK_GEN_9_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_9_oov
+#ifndef CONF_GCLK_GEN_9_OOV
+#define CONF_GCLK_GEN_9_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_9_idc
+#ifndef CONF_GCLK_GEN_9_IDC
+#define CONF_GCLK_GEN_9_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_9_enable
+#ifndef CONF_GCLK_GEN_9_GENEN
+#define CONF_GCLK_GEN_9_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 9 division <0x0000-0xFFFF>
+// <id> gclk_gen_9_div
+#ifndef CONF_GCLK_GEN_9_DIV
+#define CONF_GCLK_GEN_9_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 10 configuration
+// <i> Indicates whether generic clock 10 configuration is enabled or not
+// <id> enable_gclk_gen_10
+#ifndef CONF_GCLK_GENERATOR_10_CONFIG
+#define CONF_GCLK_GENERATOR_10_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 10 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 10
+// <id> gclk_gen_10_oscillator
+#ifndef CONF_GCLK_GEN_10_SOURCE
+#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_10_runstdby
+#ifndef CONF_GCLK_GEN_10_RUNSTDBY
+#define CONF_GCLK_GEN_10_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_10_div_sel
+#ifndef CONF_GCLK_GEN_10_DIVSEL
+#define CONF_GCLK_GEN_10_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_10_oe
+#ifndef CONF_GCLK_GEN_10_OE
+#define CONF_GCLK_GEN_10_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_10_oov
+#ifndef CONF_GCLK_GEN_10_OOV
+#define CONF_GCLK_GEN_10_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_10_idc
+#ifndef CONF_GCLK_GEN_10_IDC
+#define CONF_GCLK_GEN_10_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_10_enable
+#ifndef CONF_GCLK_GEN_10_GENEN
+#define CONF_GCLK_GEN_10_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 10 division <0x0000-0xFFFF>
+// <id> gclk_gen_10_div
+#ifndef CONF_GCLK_GEN_10_DIV
+#define CONF_GCLK_GEN_10_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> Generic clock generator 11 configuration
+// <i> Indicates whether generic clock 11 configuration is enabled or not
+// <id> enable_gclk_gen_11
+#ifndef CONF_GCLK_GENERATOR_11_CONFIG
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
+#endif
+
+// <h> Generic Clock Generator Control
+// <y> Generic clock generator 11 source
+// <GCLK_GENCTRL_SRC_XOSC0"> External Crystal Oscillator 8-48MHz (XOSC0)
+// <GCLK_GENCTRL_SRC_XOSC1"> External Crystal Oscillator 8-48MHz (XOSC1)
+// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
+// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
+// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
+// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+// <GCLK_GENCTRL_SRC_DFLL"> Digital Frequency Locked Loop (DFLL48M)
+// <GCLK_GENCTRL_SRC_DPLL0"> Digital Phase Locked Loop (DPLL0)
+// <GCLK_GENCTRL_SRC_DPLL1"> Digital Phase Locked Loop (DPLL1)
+// <i> This defines the clock source for generic clock generator 11
+// <id> gclk_gen_11_oscillator
+#ifndef CONF_GCLK_GEN_11_SOURCE
+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#endif
+
+// <q> Run in Standby
+// <i> Indicates whether Run in Standby is enabled or not
+// <id> gclk_arch_gen_11_runstdby
+#ifndef CONF_GCLK_GEN_11_RUNSTDBY
+#define CONF_GCLK_GEN_11_RUNSTDBY 0
+#endif
+
+// <q> Divide Selection
+// <i> Indicates whether Divide Selection is enabled or not
+//<id> gclk_gen_11_div_sel
+#ifndef CONF_GCLK_GEN_11_DIVSEL
+#define CONF_GCLK_GEN_11_DIVSEL 0
+#endif
+
+// <q> Output Enable
+// <i> Indicates whether Output Enable is enabled or not
+// <id> gclk_arch_gen_11_oe
+#ifndef CONF_GCLK_GEN_11_OE
+#define CONF_GCLK_GEN_11_OE 0
+#endif
+
+// <q> Output Off Value
+// <i> Indicates whether Output Off Value is enabled or not
+// <id> gclk_arch_gen_11_oov
+#ifndef CONF_GCLK_GEN_11_OOV
+#define CONF_GCLK_GEN_11_OOV 0
+#endif
+
+// <q> Improve Duty Cycle
+// <i> Indicates whether Improve Duty Cycle is enabled or not
+// <id> gclk_arch_gen_11_idc
+#ifndef CONF_GCLK_GEN_11_IDC
+#define CONF_GCLK_GEN_11_IDC 0
+#endif
+
+// <q> Generic Clock Generator Enable
+// <i> Indicates whether Generic Clock Generator Enable is enabled or not
+// <id> gclk_arch_gen_11_enable
+#ifndef CONF_GCLK_GEN_11_GENEN
+#define CONF_GCLK_GEN_11_GENEN 0
+#endif
+// </h>
+
+//<h> Generic Clock Generator Division
+//<o> Generic clock generator 11 division <0x0000-0xFFFF>
+// <id> gclk_gen_11_div
+#ifndef CONF_GCLK_GEN_11_DIV
+#define CONF_GCLK_GEN_11_DIV 1
+#endif
+// </h>
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GCLK_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_mclk_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_mclk_config.h
new file mode 100644
index 000000000..a5a7de53c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_mclk_config.h
@@ -0,0 +1,104 @@
+/* Auto-generated config file hpl_mclk_config.h */
+#ifndef HPL_MCLK_CONFIG_H
+#define HPL_MCLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_cpu_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Basic settings
+// <y> CPU Clock source
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+// <i> This defines the clock source for the CPU
+// <id> cpu_clock_source
+#ifndef CONF_CPU_SRC
+#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> CPU Clock Division Factor
+// <MCLK_CPUDIV_DIV_DIV1_Val"> 1
+// <MCLK_CPUDIV_DIV_DIV2_Val"> 2
+// <MCLK_CPUDIV_DIV_DIV4_Val"> 4
+// <MCLK_CPUDIV_DIV_DIV8_Val"> 8
+// <MCLK_CPUDIV_DIV_DIV16_Val"> 16
+// <MCLK_CPUDIV_DIV_DIV32_Val"> 32
+// <MCLK_CPUDIV_DIV_DIV64_Val"> 64
+// <MCLK_CPUDIV_DIV_DIV128_Val"> 128
+// <i> Prescalar for CPU clock
+// <id> cpu_div
+#ifndef CONF_MCLK_CPUDIV
+#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val
+#endif
+// <y> Low Power Clock Division
+// <MCLK_LPDIV_LPDIV_DIV1_Val"> Divide by 1
+// <MCLK_LPDIV_LPDIV_DIV2_Val"> Divide by 2
+// <MCLK_LPDIV_LPDIV_DIV4_Val"> Divide by 4
+// <MCLK_LPDIV_LPDIV_DIV8_Val"> Divide by 8
+// <MCLK_LPDIV_LPDIV_DIV16_Val"> Divide by 16
+// <MCLK_LPDIV_LPDIV_DIV32_Val"> Divide by 32
+// <MCLK_LPDIV_LPDIV_DIV64_Val"> Divide by 64
+// <MCLK_LPDIV_LPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_lpdiv
+#ifndef CONF_MCLK_LPDIV
+#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val
+#endif
+
+// <y> Backup Clock Division
+// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
+// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
+// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
+// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
+// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
+// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
+// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
+// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
+// <id> mclk_arch_bupdiv
+#ifndef CONF_MCLK_BUPDIV
+#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val
+#endif
+// <y> High-Speed Clock Division
+// <MCLK_HSDIV_DIV_DIV1_Val"> Divide by 1
+// <id> mclk_arch_hsdiv
+#ifndef CONF_MCLK_HSDIV
+#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val
+#endif
+// </h>
+
+// <h> NVM Settings
+// <o> NVM Wait States
+// <i> These bits select the number of wait states for a read operation.
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <id> nvm_wait_states
+#ifndef CONF_NVM_WAIT_STATE
+#define CONF_NVM_WAIT_STATE 0
+#endif
+
+// </h>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_MCLK_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_port_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_port_config.h
new file mode 100644
index 000000000..a7bd37973
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_port_config.h
@@ -0,0 +1,403 @@
+/* Auto-generated config file hpl_port_config.h */
+#ifndef HPL_PORT_CONFIG_H
+#define HPL_PORT_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> PORT Input Event 0 configuration
+// <id> enable_port_input_event_0
+#ifndef CONF_PORT_EVCTRL_PORT_0
+#define CONF_PORT_EVCTRL_PORT_0 0
+#endif
+
+// <h> PORT Input Event 0 configuration on PORT A
+
+// <q> PORTA Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
+// <id> porta_input_event_enable_0
+#ifndef CONF_PORTA_EVCTRL_PORTEI_0
+#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_0
+#ifndef CONF_PORTA_EVCTRL_PID_0
+#define CONF_PORTA_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTA Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 0
+// <id> porta_event_action_0
+#ifndef CONF_PORTA_EVCTRL_EVACT_0
+#define CONF_PORTA_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+// <h> PORT Input Event 0 configuration on PORT B
+
+// <q> PORTB Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
+// <id> portb_input_event_enable_0
+#ifndef CONF_PORTB_EVCTRL_PORTEI_0
+#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_0
+#ifndef CONF_PORTB_EVCTRL_PID_0
+#define CONF_PORTB_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTB Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 0
+// <id> portb_event_action_0
+#ifndef CONF_PORTB_EVCTRL_EVACT_0
+#define CONF_PORTB_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+// <h> PORT Input Event 0 configuration on PORT C
+
+// <q> PORTC Input Event 0 Enable
+// <i> The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled
+// <id> portc_input_event_enable_0
+#ifndef CONF_PORTC_EVCTRL_PORTEI_0
+#define CONF_PORTC_EVCTRL_PORTEI_0 0x0
+#endif
+
+// <o> PORTC Event 0 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port C on which the event action will be performed
+// <id> portc_event_pin_identifier_0
+#ifndef CONF_PORTC_EVCTRL_PID_0
+#define CONF_PORTC_EVCTRL_PID_0 0x0
+#endif
+
+// <o> PORTC Event 0 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT C will perform on event input 0
+// <id> portc_event_action_0
+#ifndef CONF_PORTC_EVCTRL_EVACT_0
+#define CONF_PORTC_EVCTRL_EVACT_0 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 1 configuration
+// <id> enable_port_input_event_1
+#ifndef CONF_PORT_EVCTRL_PORT_1
+#define CONF_PORT_EVCTRL_PORT_1 0
+#endif
+
+// <h> PORT Input Event 1 configuration on PORT A
+
+// <q> PORTA Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
+// <id> porta_input_event_enable_1
+#ifndef CONF_PORTA_EVCTRL_PORTEI_1
+#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_1
+#ifndef CONF_PORTA_EVCTRL_PID_1
+#define CONF_PORTA_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTA Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 1
+// <id> porta_event_action_1
+#ifndef CONF_PORTA_EVCTRL_EVACT_1
+#define CONF_PORTA_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+// <h> PORT Input Event 1 configuration on PORT B
+
+// <q> PORTB Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
+// <id> portb_input_event_enable_1
+#ifndef CONF_PORTB_EVCTRL_PORTEI_1
+#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_1
+#ifndef CONF_PORTB_EVCTRL_PID_1
+#define CONF_PORTB_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTB Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 1
+// <id> portb_event_action_1
+#ifndef CONF_PORTB_EVCTRL_EVACT_1
+#define CONF_PORTB_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+// <h> PORT Input Event 1 configuration on PORT C
+
+// <q> PORTC Input Event 1 Enable
+// <i> The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled
+// <id> portc_input_event_enable_1
+#ifndef CONF_PORTC_EVCTRL_PORTEI_1
+#define CONF_PORTC_EVCTRL_PORTEI_1 0x0
+#endif
+
+// <o> PORTC Event 1 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port C on which the event action will be performed
+// <id> portc_event_pin_identifier_1
+#ifndef CONF_PORTC_EVCTRL_PID_1
+#define CONF_PORTC_EVCTRL_PID_1 0x0
+#endif
+
+// <o> PORTC Event 1 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT C will perform on event input 1
+// <id> portc_event_action_1
+#ifndef CONF_PORTC_EVCTRL_EVACT_1
+#define CONF_PORTC_EVCTRL_EVACT_1 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 2 configuration
+// <id> enable_port_input_event_2
+#ifndef CONF_PORT_EVCTRL_PORT_2
+#define CONF_PORT_EVCTRL_PORT_2 0
+#endif
+
+// <h> PORT Input Event 2 configuration on PORT A
+
+// <q> PORTA Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
+// <id> porta_input_event_enable_2
+#ifndef CONF_PORTA_EVCTRL_PORTEI_2
+#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_2
+#ifndef CONF_PORTA_EVCTRL_PID_2
+#define CONF_PORTA_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTA Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 2
+// <id> porta_event_action_2
+#ifndef CONF_PORTA_EVCTRL_EVACT_2
+#define CONF_PORTA_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+// <h> PORT Input Event 2 configuration on PORT B
+
+// <q> PORTB Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
+// <id> portb_input_event_enable_2
+#ifndef CONF_PORTB_EVCTRL_PORTEI_2
+#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_2
+#ifndef CONF_PORTB_EVCTRL_PID_2
+#define CONF_PORTB_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTB Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 2
+// <id> portb_event_action_2
+#ifndef CONF_PORTB_EVCTRL_EVACT_2
+#define CONF_PORTB_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+// <h> PORT Input Event 2 configuration on PORT C
+
+// <q> PORTC Input Event 2 Enable
+// <i> The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled
+// <id> portc_input_event_enable_2
+#ifndef CONF_PORTC_EVCTRL_PORTEI_2
+#define CONF_PORTC_EVCTRL_PORTEI_2 0x0
+#endif
+
+// <o> PORTC Event 2 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port C on which the event action will be performed
+// <id> portc_event_pin_identifier_2
+#ifndef CONF_PORTC_EVCTRL_PID_2
+#define CONF_PORTC_EVCTRL_PID_2 0x0
+#endif
+
+// <o> PORTC Event 2 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT C will perform on event input 2
+// <id> portc_event_action_2
+#ifndef CONF_PORTC_EVCTRL_EVACT_2
+#define CONF_PORTC_EVCTRL_EVACT_2 0
+#endif
+
+// </h>
+
+// </e>
+
+// <e> PORT Input Event 3 configuration
+// <id> enable_port_input_event_3
+#ifndef CONF_PORT_EVCTRL_PORT_3
+#define CONF_PORT_EVCTRL_PORT_3 0
+#endif
+
+// <h> PORT Input Event 3 configuration on PORT A
+
+// <q> PORTA Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
+// <id> porta_input_event_enable_3
+#ifndef CONF_PORTA_EVCTRL_PORTEI_3
+#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port A on which the event action will be performed
+// <id> porta_event_pin_identifier_3
+#ifndef CONF_PORTA_EVCTRL_PID_3
+#define CONF_PORTA_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTA Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT A will perform on event input 3
+// <id> porta_event_action_3
+#ifndef CONF_PORTA_EVCTRL_EVACT_3
+#define CONF_PORTA_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+// <h> PORT Input Event 3 configuration on PORT B
+
+// <q> PORTB Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
+// <id> portb_input_event_enable_3
+#ifndef CONF_PORTB_EVCTRL_PORTEI_3
+#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port B on which the event action will be performed
+// <id> portb_event_pin_identifier_3
+#ifndef CONF_PORTB_EVCTRL_PID_3
+#define CONF_PORTB_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTB Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT B will perform on event input 3
+// <id> portb_event_action_3
+#ifndef CONF_PORTB_EVCTRL_EVACT_3
+#define CONF_PORTB_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+// <h> PORT Input Event 3 configuration on PORT C
+
+// <q> PORTC Input Event 3 Enable
+// <i> The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled
+// <id> portc_input_event_enable_3
+#ifndef CONF_PORTC_EVCTRL_PORTEI_3
+#define CONF_PORTC_EVCTRL_PORTEI_3 0x0
+#endif
+
+// <o> PORTC Event 3 Pin Identifier <0x00-0x1F>
+// <i> These bits define the I/O pin from port C on which the event action will be performed
+// <id> portc_event_pin_identifier_3
+#ifndef CONF_PORTC_EVCTRL_PID_3
+#define CONF_PORTC_EVCTRL_PID_3 0x0
+#endif
+
+// <o> PORTC Event 3 Action
+// <0=> Output register of pin will be set to level of event
+// <1=> Set output register of pin on event
+// <2=> Clear output register of pin on event
+// <3=> Toggle output register of pin on event
+// <i> These bits define the event action the PORT C will perform on event input 3
+// <id> portc_event_action_3
+#ifndef CONF_PORTC_EVCTRL_EVACT_3
+#define CONF_PORTC_EVCTRL_EVACT_3 0
+#endif
+
+// </h>
+
+// </e>
+
+#define CONF_PORTA_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
+#define CONF_PORTB_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
+#define CONF_PORTC_EVCTRL                                                                                              \
+	(0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos         \
+	 | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1)                       \
+	 | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1)               \
+	 | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos           \
+	 | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3)                       \
+	 | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3))
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PORT_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_usb_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_usb_config.h
new file mode 100644
index 000000000..600264ac7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/hpl_usb_config.h
@@ -0,0 +1,355 @@
+/* Auto-generated config file hpl_usb_config.h */
+#ifndef HPL_USB_CONFIG_H
+#define HPL_USB_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#define CONF_USB_N_0 0
+#define CONF_USB_N_1 1
+#define CONF_USB_N_2 2
+#define CONF_USB_N_3 3
+#define CONF_USB_N_4 4
+#define CONF_USB_N_5 5
+#define CONF_USB_N_6 6
+#define CONF_USB_N_7 7
+#define CONF_USB_N_8 8
+#define CONF_USB_N_9 9
+#define CONF_USB_N_10 10
+#define CONF_USB_N_11 11
+#define CONF_USB_N_12 12
+#define CONF_USB_N_13 13
+#define CONF_USB_N_14 14
+#define CONF_USB_N_15 15
+
+#define CONF_USB_D_EP_N_MAX (7)
+#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1)
+
+// <h> USB Device HAL Configuration
+
+// <y> Max number of endpoints supported
+// <i> Limits the number of endpoints (described by EP address) can be used in app.
+// <CONF_USB_N_1"> 1 (EP0 only)
+// <CONF_USB_N_2"> 2 (EP0 + 1 endpoint)
+// <CONF_USB_N_3"> 3 (EP0 + 2 endpoints)
+// <CONF_USB_N_4"> 4 (EP0 + 3 endpoints)
+// <CONF_USB_N_5"> 5 (EP0 + 4 endpoints)
+// <CONF_USB_N_6"> 6 (EP0 + 5 endpoints)
+// <CONF_USB_N_7"> 7 (EP0 + 6 endpoints)
+// <CONF_USB_N_8"> 8 (EP0 + 7 endpoints)
+// <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config)
+// <id> usbd_num_ep_sp
+#ifndef CONF_USB_D_NUM_EP_SP
+#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX
+#endif
+
+// </h>
+
+// <y> Max Endpoint Number supported
+// <i> Limits the max endpoint number.
+// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1.
+// <i> Reduce the value according to specific device design, to cut-off memory usage.
+// <CONF_USB_N_0"> 0 (only EP0)
+// <CONF_USB_N_1"> 1 (EP 0x81 or 0x01)
+// <CONF_USB_N_2"> 2 (EP 0x82 or 0x02)
+// <CONF_USB_N_3"> 3 (EP 0x83 or 0x03)
+// <CONF_USB_N_4"> 4 (EP 0x84 or 0x04)
+// <CONF_USB_N_5"> 5 (EP 0x85 or 0x05)
+// <CONF_USB_N_6"> 6 (EP 0x86 or 0x06)
+// <CONF_USB_N_7"> 7 (EP 0x87 or 0x07)
+// <CONF_USB_EP_N_MAX"> Max possible (by HW)
+// <i> The number of physical endpoints - 1
+// <id> usbd_arch_max_ep_n
+#ifndef CONF_USB_D_MAX_EP_N
+#define CONF_USB_D_MAX_EP_N CONF_USB_N_2
+#endif
+
+// <y> USB Speed Limit
+// <i> Limits the working speed of the device.
+// <USB_SPEED_FS"> Full speed
+// <USB_SPEED_LS"> Low Speed
+// <id> usbd_arch_speed
+#ifndef CONF_USB_D_SPEED
+#define CONF_USB_D_SPEED USB_SPEED_FS
+#endif
+
+// <o> Cache buffer size for EP0
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time.
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <id> usb_arch_ep0_cache
+#ifndef CONF_USB_EP0_CACHE
+#define CONF_USB_EP0_CACHE 64
+#endif
+
+// <h> Cache configuration EP1
+// <o> Cache buffer size for EP1 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep1_cache
+#ifndef CONF_USB_EP1_CACHE
+#define CONF_USB_EP1_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP1 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep1_I_CACHE
+#ifndef CONF_USB_EP1_I_CACHE
+#define CONF_USB_EP1_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP2
+// <o> Cache buffer size for EP2 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep2_cache
+#ifndef CONF_USB_EP2_CACHE
+#define CONF_USB_EP2_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP2 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep2_I_CACHE
+#ifndef CONF_USB_EP2_I_CACHE
+#define CONF_USB_EP2_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP3
+// <o> Cache buffer size for EP3 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep3_cache
+#ifndef CONF_USB_EP3_CACHE
+#define CONF_USB_EP3_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP3 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep3_I_CACHE
+#ifndef CONF_USB_EP3_I_CACHE
+#define CONF_USB_EP3_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP4
+// <o> Cache buffer size for EP4 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep4_cache
+#ifndef CONF_USB_EP4_CACHE
+#define CONF_USB_EP4_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP4 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep4_I_CACHE
+#ifndef CONF_USB_EP4_I_CACHE
+#define CONF_USB_EP4_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP5
+// <o> Cache buffer size for EP5 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep5_cache
+#ifndef CONF_USB_EP5_CACHE
+#define CONF_USB_EP5_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP5 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep5_I_CACHE
+#ifndef CONF_USB_EP5_I_CACHE
+#define CONF_USB_EP5_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP6
+// <o> Cache buffer size for EP6 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep6_cache
+#ifndef CONF_USB_EP6_CACHE
+#define CONF_USB_EP6_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP6 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep6_I_CACHE
+#ifndef CONF_USB_EP6_I_CACHE
+#define CONF_USB_EP6_I_CACHE 0
+#endif
+// </h>
+
+// <h> Cache configuration EP7
+// <o> Cache buffer size for EP7 OUT
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_arch_ep7_cache
+#ifndef CONF_USB_EP7_CACHE
+#define CONF_USB_EP7_CACHE 64
+#endif
+
+// <o> Cache buffer size for EP7 IN
+// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
+// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
+// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
+// <0=> No cache
+// <8=> Cached by 8 bytes buffer
+// <16=> Cached by 16 bytes buffer
+// <32=> Cached by 32 bytes buffer
+// <64=> Cached by 64 bytes buffer
+// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
+// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
+// <id> usb_ep7_I_CACHE
+#ifndef CONF_USB_EP7_I_CACHE
+#define CONF_USB_EP7_I_CACHE 0
+#endif
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_USB_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/peripheral_clk_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/peripheral_clk_config.h
new file mode 100644
index 000000000..73c7fecb8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/peripheral_clk_config.h
@@ -0,0 +1,58 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 10000000
+#endif
+
+// <y> USB Clock Source
+// <id> usb_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for USB.
+#ifndef CONF_GCLK_USB_SRC
+#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+
+#endif
+
+/**
+ * \def CONF_GCLK_USB_FREQUENCY
+ * \brief USB's Clock frequency
+ */
+#ifndef CONF_GCLK_USB_FREQUENCY
+#define CONF_GCLK_USB_FREQUENCY 48000000
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/usbd_config.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/usbd_config.h
new file mode 100644
index 000000000..d9dfecdbb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/config/usbd_config.h
@@ -0,0 +1,364 @@
+/* Auto-generated config file usbd_config.h */
+#ifndef USBD_CONFIG_H
+#define USBD_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// ---- USB Device Stack Core Options ----
+
+// <q> High Speed Support
+// <i> Enable high speed specific descriptors support, e.g., DeviceQualifierDescriptor and OtherSpeedConfiguration Descriptor.
+// <i> High speed support require descriptors description array on start, for LS/FS and HS support in first and second place.
+// <id> usbd_hs_sp
+#ifndef CONF_USBD_HS_SP
+#define CONF_USBD_HS_SP 0
+#endif
+
+// ---- USB Device Stack CDC ACM Options ----
+
+// <e> Enable String Descriptors
+// <id> usb_cdcd_acm_str_en
+#ifndef CONF_USB_CDCD_ACM_STR_EN
+#define CONF_USB_CDCD_ACM_STR_EN 1
+#endif
+// <s> Language IDs
+// <i> Language IDs in c format, split by comma (E.g., 0x0409 ...)
+// <id> usb_cdcd_acm_langid
+#ifndef CONF_USB_CDCD_ACM_LANGID
+#define CONF_USB_CDCD_ACM_LANGID "0x0409"
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_LANGID_DESC
+#define CONF_USB_CDCD_ACM_LANGID_DESC 4, 0x03, 0x09, 0x04,
+#endif
+// </e>
+
+// <h> CDC ACM Device Descriptor
+
+// <o> bcdUSB
+// <0x0200=> USB 2.0 version
+// <0x0210=> USB 2.1 version
+// <id> usb_cdcd_acm_bcdusb
+#ifndef CONF_USB_CDCD_ACM_BCDUSB
+#define CONF_USB_CDCD_ACM_BCDUSB 0x200
+#endif
+
+// <o> bMaxPackeSize0
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <id> usb_cdcd_acm_bmaxpksz0
+#ifndef CONF_USB_CDCD_ACM_BMAXPKSZ0
+#define CONF_USB_CDCD_ACM_BMAXPKSZ0 0x40
+#endif
+
+// <o> idVender <0x0000-0xFFFF>
+// <id> usb_cdcd_acm_idvender
+#ifndef CONF_USB_CDCD_ACM_IDVENDER
+//#define CONF_USB_CDCD_ACM_IDVENDER 0x03eb
+#define CONF_USB_CDCD_ACM_IDVENDER 0x2890
+#endif
+
+// <o> idProduct <0x0000-0xFFFF>
+// <id> usb_cdcd_acm_idproduct
+#ifndef CONF_USB_CDCD_ACM_IDPRODUCT
+//#define CONF_USB_CDCD_ACM_IDPRODUCT 0x2404
+#define CONF_USB_CDCD_ACM_IDPRODUCT 0x8022
+#endif
+
+// <o> bcdDevice <0x0000-0xFFFF>
+// <id> usb_cdcd_acm_bcddevice
+#ifndef CONF_USB_CDCD_ACM_BCDDEVICE
+#define CONF_USB_CDCD_ACM_BCDDEVICE 0x100
+#endif
+
+// <e> Enable string descriptor of iManufact
+// <id> usb_cdcd_acm_imanufact_en
+#ifndef CONF_USB_CDCD_ACM_IMANUFACT_EN
+#define CONF_USB_CDCD_ACM_IMANUFACT_EN 1
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_IMANUFACT
+#define CONF_USB_CDCD_ACM_IMANUFACT (CONF_USB_CDCD_ACM_IMANUFACT_EN * (CONF_USB_CDCD_ACM_IMANUFACT_EN))
+#endif
+
+// <s> Unicode string of iManufact
+// <id> usb_cdcd_acm_imanufact_str
+#ifndef CONF_USB_CDCD_ACM_IMANUFACT_STR
+#define CONF_USB_CDCD_ACM_IMANUFACT_STR "Teknic, Inc."
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_IMANUFACT_STR_DESC
+#define CONF_USB_CDCD_ACM_IMANUFACT_STR_DESC                                                   \
+        26, 0x03, 'T', 0x00, 'e', 0x00, 'k', 0x00, 'n', 0x00, 'i', 0x00, 'c', 0x00, ',', 0x00, \
+        ' ', 0x00, 'I', 0x00, 'n', 0x00, 'c', 0x00, '.', 0x00,
+#endif
+#if !CONF_USB_CDCD_ACM_IMANUFACT_EN
+#undef CONF_USB_CDCD_ACM_IMANUFACT_STR_DESC
+#define CONF_USB_CDCD_ACM_IMANUFACT_STR_DESC
+#endif
+
+// </e>
+
+// <e> Enable string descriptor of iProduct
+// <id> usb_cdcd_acm_iproduct_en
+#ifndef CONF_USB_CDCD_ACM_IPRODUCT_EN
+#define CONF_USB_CDCD_ACM_IPRODUCT_EN 1
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_IPRODUCT
+#define CONF_USB_CDCD_ACM_IPRODUCT                                                                                     \
+	(CONF_USB_CDCD_ACM_IPRODUCT_EN * (CONF_USB_CDCD_ACM_IMANUFACT_EN + CONF_USB_CDCD_ACM_IPRODUCT_EN))
+#endif
+
+// <s> Unicode string of iProduct
+// <id> usb_cdcd_acm_iproduct_str
+#ifndef CONF_USB_CDCD_ACM_IPRODUCT_STR
+#define CONF_USB_CDCD_ACM_IPRODUCT_STR "Teknic ClearCore"
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_IPRODUCT_STR_DESC
+#define CONF_USB_CDCD_ACM_IPRODUCT_STR_DESC                                                                                \
+        34, 0x03, 'T', 0x00, 'e', 0x00, 'k', 0x00, 'n', 0x00, 'i', 0x00, 'c', 0x00, ' ', 0x00, 'C', 0x00, 'l', 0x00, 'e',  \
+        0x00, 'a', 0x00, 'r', 0x00, 'C', 0x00, 'o', 0x00, 'r', 0x00, 'e', 0x00,
+#endif
+#if !CONF_USB_CDCD_ACM_IPRODUCT_EN
+#undef CONF_USB_CDCD_ACM_IPRODUCT_STR_DESC
+#define CONF_USB_CDCD_ACM_IPRODUCT_STR_DESC
+#endif
+
+// </e>
+
+// <e> Enable string descriptor of iSerialNum
+// <id> usb_cdcd_acm_iserialnum_en
+#ifndef CONF_USB_CDCD_ACM_ISERIALNUM_EN
+#define CONF_USB_CDCD_ACM_ISERIALNUM_EN 1
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_ISERIALNUM
+#define CONF_USB_CDCD_ACM_ISERIALNUM                                                                                   \
+	(CONF_USB_CDCD_ACM_ISERIALNUM_EN                                                                                   \
+	 * (CONF_USB_CDCD_ACM_IMANUFACT_EN + CONF_USB_CDCD_ACM_IPRODUCT_EN + CONF_USB_CDCD_ACM_ISERIALNUM_EN))
+#endif
+
+// <s> Unicode string of iSerialNum
+// <id> usb_cdcd_acm_iserialnum_str
+#ifndef CONF_USB_CDCD_ACM_ISERIALNUM_STR
+#define CONF_USB_CDCD_ACM_ISERIALNUM_STR "123456789ABCDEF0123456789ABCDEF0"
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_ISERIALNUM_STR_DESC
+#define CONF_USB_CDCD_ACM_ISERIALNUM_STR_DESC                                                                             \
+        66, 0x03, '1', 0x00, '2', 0x00, '3', 0x00, '4', 0x00, '5', 0x00, '6', 0x00, '7', 0x00, '8', 0x00, '9', 0x00, 'A', \
+        0x00, 'B', 0x00, 'C', 0x00, 'D', 0x00, 'E', 0x00, 'F', 0x00, '0', 0x00, '1', 0x00, '2', 0x00, '3', 0x00, '4', 0x00, \
+        '5', 0x00, '6', 0x00, '7', 0x00, '8', 0x00, '9', 0x00, 'A', 0x00, 'B', 0x00, 'C', 0x00, 'D', 0x00, 'E', 0x00,     \
+        'F', 0x00, '0', 0x00,
+#endif
+#if !CONF_USB_CDCD_ACM_ISERIALNUM_EN
+#undef CONF_USB_CDCD_ACM_ISERIALNUM_STR_DESC
+#define CONF_USB_CDCD_ACM_ISERIALNUM_STR_DESC
+#endif
+
+// </e>
+
+// <o> bNumConfigurations <0x01-0xFF>
+// <id> usb_cdcd_acm_bnumconfig
+#ifndef CONF_USB_CDCD_ACM_BNUMCONFIG
+#define CONF_USB_CDCD_ACM_BNUMCONFIG 0x1
+#endif
+
+// </h>
+
+// <h> CDC ACM Configuration Descriptor
+// <o> bConfigurationValue <0x01-0xFF>
+// <id> usb_cdcd_acm_bconfigval
+#ifndef CONF_USB_CDCD_ACM_BCONFIGVAL
+#define CONF_USB_CDCD_ACM_BCONFIGVAL 0x1
+#endif
+// <e> Enable string descriptor of iConfig
+// <id> usb_cdcd_acm_iconfig_en
+#ifndef CONF_USB_CDCD_ACM_ICONFIG_EN
+#define CONF_USB_CDCD_ACM_ICONFIG_EN 0
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_ICONFIG
+#define CONF_USB_CDCD_ACM_ICONFIG                                                                                      \
+	(CONF_USB_CDCD_ACM_ICONFIG_EN                                                                                      \
+	 * (CONF_USB_CDCD_ACM_IMANUFACT_EN + CONF_USB_CDCD_ACM_IPRODUCT_EN + CONF_USB_CDCD_ACM_ISERIALNUM_EN               \
+	    + CONF_USB_CDCD_ACM_ICONFIG_EN))
+#endif
+
+// <s> Unicode string of iConfig
+// <id> usb_cdcd_acm_iconfig_str
+#ifndef CONF_USB_CDCD_ACM_ICONFIG_STR
+#define CONF_USB_CDCD_ACM_ICONFIG_STR ""
+#endif
+
+#ifndef CONF_USB_CDCD_ACM_ICONFIG_STR_DESC
+#define CONF_USB_CDCD_ACM_ICONFIG_STR_DESC
+#endif
+
+// </e>
+
+// <o> bmAttributes
+// <0x80=> Bus power supply, not support for remote wakeup
+// <0xA0=> Bus power supply, support for remote wakeup
+// <0xC0=> Self powered, not support for remote wakeup
+// <0xE0=> Self powered, support for remote wakeup
+// <id> usb_cdcd_acm_bmattri
+#ifndef CONF_USB_CDCD_ACM_BMATTRI
+#define CONF_USB_CDCD_ACM_BMATTRI 0x80
+#endif
+
+// <o> bMaxPower <0x00-0xFF>
+// <id> usb_cdcd_acm_bmaxpower
+#ifndef CONF_USB_CDCD_ACM_BMAXPOWER
+#define CONF_USB_CDCD_ACM_BMAXPOWER 0xFA
+#endif
+// </h>
+
+// <h> CDC ACM Communication Interface Descriptor
+
+// <o> bInterfaceNumber <0x00-0xFF>
+// <id> usb_cdcd_acm_comm_bifcnum
+#ifndef CONF_USB_CDCD_ACM_COMM_BIFCNUM
+#define CONF_USB_CDCD_ACM_COMM_BIFCNUM 0x0
+#endif
+// <o> bAlternateSetting <0x00-0xFF>
+// <id> usb_cdcd_acm_comm_baltset
+#ifndef CONF_USB_CDCD_ACM_COMM_BALTSET
+#define CONF_USB_CDCD_ACM_COMM_BALTSET 0x0
+#endif
+
+// <o> iInterface <0x00-0xFF>
+// <id> usb_cdcd_acm_comm_iifc
+#ifndef CONF_USB_CDCD_ACM_COMM_IIFC
+#define CONF_USB_CDCD_ACM_COMM_IIFC 0x0
+#endif
+
+// <o> Interrupt IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <id> usb_cdcd_acm_epaddr
+#ifndef CONF_USB_CDCD_ACM_COMM_INT_EPADDR
+#define CONF_USB_CDCD_ACM_COMM_INT_EPADDR 0x82
+#endif
+
+// <o> Interrupt IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <id> usb_cdcd_acm_comm_int_maxpksz
+#ifndef CONF_USB_CDCD_ACM_COMM_INT_MAXPKSZ
+#define CONF_USB_CDCD_ACM_COMM_INT_MAXPKSZ 0x40
+#endif
+
+// <o> Interrupt IN Endpoint Interval <0x00-0xFF>
+// <id> usb_cdcd_acm_comm_int_interval
+#ifndef CONF_USB_CDCD_ACM_COMM_INT_INTERVAL
+#define CONF_USB_CDCD_ACM_COMM_INT_INTERVAL 0xa
+#endif
+// </h>
+
+// <h> CDC ACM Data Interface Descriptor
+
+// <o> bInterfaceNumber <0x00-0xFF>
+// <id> usb_cdcd_acm_data_bifcnum
+#ifndef CONF_USB_CDCD_ACM_DATA_BIFCNUM
+#define CONF_USB_CDCD_ACM_DATA_BIFCNUM 0x1
+#endif
+// <o> bAlternateSetting <0x00-0xFF>
+// <id> usb_cdcd_acm_data_baltset
+#ifndef CONF_USB_CDCD_ACM_DATA_BALTSET
+#define CONF_USB_CDCD_ACM_DATA_BALTSET 0x0
+#endif
+
+// <o> iInterface <0x00-0xFF>
+// <id> usb_cdcd_acm_data_iifc
+#ifndef CONF_USB_CDCD_ACM_DATA_IIFC
+#define CONF_USB_CDCD_ACM_DATA_IIFC 0x0
+#endif
+
+// <o> BULK IN Endpoint Address
+// <0x81=> EndpointAddress = 0x81
+// <0x82=> EndpointAddress = 0x82
+// <0x83=> EndpointAddress = 0x83
+// <0x84=> EndpointAddress = 0x84
+// <0x85=> EndpointAddress = 0x85
+// <0x86=> EndpointAddress = 0x86
+// <0x87=> EndpointAddress = 0x87
+// <id> usb_cdcd_acm_data_bulkin_epaddr
+#ifndef CONF_USB_CDCD_ACM_DATA_BULKIN_EPADDR
+#define CONF_USB_CDCD_ACM_DATA_BULKIN_EPADDR 0x81
+#endif
+
+// <o> BULK IN Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <id> usb_cdcd_acm_data_builin_maxpksz
+#ifndef CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ
+#define CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ 0x40
+#endif
+
+// <o> BULK IN Endpoint wMaxPacketSize for High Speed
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <0x0080=> 128 bytes
+// <0x0100=> 256 bytes
+// <0x0200=> 512 bytes
+// <id> usb_cdcd_acm_data_builin_maxpksz_hs
+#ifndef CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ_HS
+#define CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ_HS 0x200
+#endif
+
+// <o> BULK OUT Endpoint Address
+// <0x01=> EndpointAddress = 0x01
+// <0x02=> EndpointAddress = 0x02
+// <0x03=> EndpointAddress = 0x03
+// <0x04=> EndpointAddress = 0x04
+// <0x05=> EndpointAddress = 0x05
+// <0x06=> EndpointAddress = 0x06
+// <0x07=> EndpointAddress = 0x07
+// <id> usb_cdcd_acm_data_bulkout_epaddr
+#ifndef CONF_USB_CDCD_ACM_DATA_BULKOUT_EPADDR
+#define CONF_USB_CDCD_ACM_DATA_BULKOUT_EPADDR 0x1
+#endif
+
+// <o> BULK OUT Endpoint wMaxPacketSize
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <id> usb_cdcd_acm_data_buckout_maxpksz
+#ifndef CONF_USB_CDCD_ACM_DATA_BULKOUT_MAXPKSZ
+#define CONF_USB_CDCD_ACM_DATA_BULKOUT_MAXPKSZ 0x40
+#endif
+
+// <o> BULK OUT Endpoint wMaxPacketSize for High Speed
+// <0x0008=> 8 bytes
+// <0x0010=> 16 bytes
+// <0x0020=> 32 bytes
+// <0x0040=> 64 bytes
+// <0x0080=> 128 bytes
+// <0x0100=> 256 bytes
+// <0x0200=> 512 bytes
+// <id> usb_cdcd_acm_data_buckout_maxpksz_hs
+#ifndef CONF_USB_CDCD_ACM_DATA_BULKOUT_MAXPKSZ_HS
+#define CONF_USB_CDCD_ACM_DATA_BULKOUT_MAXPKSZ_HS 0x200
+#endif
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // USBD_CONFIG_H
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_atomic.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_atomic.h
new file mode 100644
index 000000000..82151fc5d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_atomic.h
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ATOMIC_H_INCLUDED
+#define _HAL_ATOMIC_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_atomic
+ *
+ *@{
+ */
+
+/**
+ * \brief Type for the register holding global interrupt enable flag
+ */
+typedef uint32_t hal_atomic_t;
+
+/**
+ * \brief Helper macro for entering critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_enterCritical() function to enter critical
+ * sections. No semicolon is required after the macro.
+ *
+ * \section atomic_usage Usage Example
+ * \code
+ * CRITICAL_SECTION_ENTER()
+ * Critical code
+ * CRITICAL_SECTION_LEAVE()
+ * \endcode
+ */
+#define CRITICAL_SECTION_ENTER()                                                                                       \
+	{                                                                                                                  \
+		volatile hal_atomic_t __atomic;                                                                                \
+		atomic_enter_critical(&__atomic);
+
+/**
+ * \brief Helper macro for leaving critical sections
+ *
+ * This macro is recommended to be used instead of a direct call
+ * hal_leaveCritical() function to leave critical
+ * sections. No semicolon is required after the macro.
+ */
+#define CRITICAL_SECTION_LEAVE()                                                                                       \
+	atomic_leave_critical(&__atomic);                                                                                  \
+	}
+
+/**
+ * \brief Disable interrupts, enter critical section
+ *
+ * Disables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[out] atomic The pointer to a variable to store the value of global
+ * interrupt enable flag
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Exit atomic section
+ *
+ * Enables global interrupts. Supports nested critical sections,
+ * so that global interrupts are only re-enabled
+ * upon leaving the outermost nested critical section.
+ *
+ * \param[in] atomic The pointer to a variable, which stores the latest stored
+ * value of the global interrupt enable flag
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t atomic_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_ATOMIC_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_cache.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_cache.h
new file mode 100644
index 000000000..071486b7c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_cache.h
@@ -0,0 +1,96 @@
+/**
+ * \file
+ *
+ * \brief HAL cache functionality implementation.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef HAL_CACHE_H_
+#define HAL_CACHE_H_
+
+#include <hpl_cmcc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Enable cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_enable(const void *hw);
+
+/**
+ * \brief Disable cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_disable(const void *hw);
+
+/**
+ * \brief Initialize cache module
+ *
+ * This function initialize cache module configuration.
+ *
+ * \return status of operation
+ */
+int32_t cache_init(void);
+
+/**
+ * \brief Configure cache module
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ * \param[in] cache configuration structure pointer
+ *
+ * \return status of operation
+ */
+int32_t cache_configure(const void *hw, struct _cache_cfg *cache);
+
+/**
+ * \brief Invalidate entire cache entries
+ *
+ * \param[in] pointer pointing to the starting address of cache module
+ *
+ * \return status of operation
+ */
+int32_t cache_invalidate_all(const void *hw);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_CACHE_H_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_gpio.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_gpio.h
new file mode 100644
index 000000000..fbfa2d4ae
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_gpio.h
@@ -0,0 +1,201 @@
+/**
+ * \file
+ *
+ * \brief Port
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+#ifndef _HAL_GPIO_INCLUDED_
+#define _HAL_GPIO_INCLUDED_
+
+#include <hpl_gpio.h>
+#include <utils_assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Set gpio pull mode
+ *
+ * Set pin pull mode, non existing pull modes throws an fatal assert
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
+ *                      GPIO_PULL_UP   = Pull pin high with internal resistor
+ *                      GPIO_PULL_OFF  = Disable pin pull mode
+ */
+static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
+{
+	_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
+}
+
+/**
+ * \brief Set pin function
+ *
+ * Select which function a pin will be used for
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] function  The pin function is given by a 32-bit wide bitfield
+ *                      found in the header files for the device
+ *
+ */
+static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
+{
+	_gpio_set_pin_function(pin, function);
+}
+
+/**
+ * \brief Set port data direction
+ *
+ * Select if the pin data direction is input, output or disabled.
+ * If disabled state is not possible, this function throws an assert.
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask      Bit mask where 1 means apply direction setting to the
+ *                      corresponding pin
+ * \param[in] direction GPIO_DIRECTION_IN  = Data direction in
+ *                      GPIO_DIRECTION_OUT = Data direction out
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
+                                           const enum gpio_direction direction)
+{
+	_gpio_set_direction(port, mask, direction);
+}
+
+/**
+ * \brief Set gpio data direction
+ *
+ * Select if the pin data direction is input, output or disabled.
+ * If disabled state is not possible, this function throws an assert.
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] direction GPIO_DIRECTION_IN  = Data direction in
+ *                      GPIO_DIRECTION_OUT = Data direction out
+ *                      GPIO_DIRECTION_OFF = Disables the pin
+ *                      (low power state)
+ */
+static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
+{
+	_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
+}
+
+/**
+ * \brief Set port level
+ *
+ * Sets output level on the pins defined by the bit mask
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply port level to the corresponding
+ *                  pin
+ * \param[in] level true  = Pin levels set to "high" state
+ *                  false = Pin levels set to "low" state
+ */
+static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
+{
+	_gpio_set_level(port, mask, level);
+}
+
+/**
+ * \brief Set gpio level
+ *
+ * Sets output level on a pin
+ *
+ * \param[in] pin       The pin number for device
+ * \param[in] level true  = Pin level set to "high" state
+ *                  false = Pin level set to "low" state
+ */
+static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
+{
+	_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
+}
+
+/**
+ * \brief Toggle out level on pins
+ *
+ * Toggle the pin levels on pins defined by bit mask
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means toggle pin level to the corresponding
+ *                  pin
+ */
+static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
+{
+	_gpio_toggle_level(port, mask);
+}
+
+/**
+ * \brief Toggle output level on pin
+ *
+ * Toggle the pin levels on pins defined by bit mask
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline void gpio_toggle_pin_level(const uint8_t pin)
+{
+	_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
+}
+
+/**
+ * \brief Get input level on pins
+ *
+ * Read the input level on pins connected to a port
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ */
+static inline uint32_t gpio_get_port_level(const enum gpio_port port)
+{
+	return _gpio_get_level(port);
+}
+
+/**
+ * \brief Get level on pin
+ *
+ * Reads the level on pins connected to a port
+ *
+ * \param[in] pin       The pin number for device
+ */
+static inline bool gpio_get_pin_level(const uint8_t pin)
+{
+	return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
+}
+/**
+ * \brief Get current driver version
+ */
+uint32_t gpio_get_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_init.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_init.h
new file mode 100644
index 000000000..d7bc6fe20
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_init.h
@@ -0,0 +1,72 @@
+/**
+ * \file
+ *
+ * \brief HAL initialization related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_INIT_H_INCLUDED
+#define _HAL_INIT_H_INCLUDED
+
+#include <hpl_init.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_init Init Driver
+ *
+ *@{
+ */
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ *
+ * This function calls the various initialization functions.
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization
+ */
+static inline void init_mcu(void)
+{
+	_init_chip();
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t init_get_version(void);
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_INIT_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_io.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_io.h
new file mode 100644
index 000000000..f50401d7a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_io.h
@@ -0,0 +1,110 @@
+/**
+ * \file
+ *
+ * \brief I/O related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_IO_INCLUDED
+#define _HAL_IO_INCLUDED
+
+/**
+ * \addtogroup doc_driver_hal_helper_io I/O Driver
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief I/O descriptor
+ *
+ * The I/O descriptor forward declaration.
+ */
+struct io_descriptor;
+
+/**
+ * \brief I/O write function pointer type
+ */
+typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O read function pointer type
+ */
+typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O descriptor
+ */
+struct io_descriptor {
+	io_write_t write; /*! The write function pointer. */
+	io_read_t  read;  /*! The read function pointer. */
+};
+
+/**
+ * \brief I/O write interface
+ *
+ * This function writes up to \p length of bytes to a given I/O descriptor.
+ * It returns the number of bytes actually write.
+ *
+ * \param[in] descr  An I/O descriptor to write
+ * \param[in] buf    The buffer pointer to story the write data
+ * \param[in] length The number of bytes to write
+ *
+ * \return The number of bytes written
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+
+/**
+ * \brief I/O read interface
+ *
+ * This function reads up to \p length bytes from a given I/O descriptor, and
+ * stores it in the buffer pointed to by \p buf. It returns the number of bytes
+ * actually read.
+ *
+ * \param[in] descr  An I/O descriptor to read
+ * \param[in] buf    The buffer pointer to story the read data
+ * \param[in] length The number of bytes to read
+ *
+ * \return The number of bytes actually read. This number can be less than the
+ *         requested length. E.g., in a driver that uses ring buffer for
+ *         reception, it may depend on the availability of data in the
+ *         ring buffer.
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HAL_IO_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_sleep.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_sleep.h
new file mode 100644
index 000000000..b90ef6a5b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_sleep.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_SLEEP_H_INCLUDED
+#define _HAL_SLEEP_H_INCLUDED
+
+#include <hpl_sleep.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_helper_sleep
+ *
+ *@{
+ */
+
+/**
+ * \brief Set the sleep mode of the device and put the MCU to sleep
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see the data sheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return The status of a sleep request
+ * \retval -1 The requested sleep mode was invalid or not available
+ * \retval  0 The operation completed successfully, returned after leaving the
+ *            sleep
+ */
+int sleep(const uint8_t mode);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t sleep_get_version(void);
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* _HAL_SLEEP_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_usb_device.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_usb_device.h
new file mode 100644
index 000000000..7e19f68fc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hal_usb_device.h
@@ -0,0 +1,295 @@
+/**
+ * \file
+ *
+ * \brief SAM USB device HAL
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_USB_DEVICE_H_INCLUDED
+#define _HAL_USB_DEVICE_H_INCLUDED
+
+#include <hpl_usb_device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_usb_device
+ *
+ * @{
+ */
+
+/** USB device endpoint status structure. */
+struct usb_d_ep_status {
+	/** Endpoint address, including direction. */
+	uint8_t ep;
+	/** Endpoint transfer status code that triggers the callback.
+	 *  \ref usb_xfer_code. */
+	uint8_t code;
+	/** Endpoint error, if \c code is \ref USB_TRANS_ERROR. */
+	uint8_t error;
+	/** Transfer state, \ref usb_ep_state. */
+	uint8_t state;
+	/** Transfer count. */
+	uint32_t count;
+	/** Transfer size. */
+	uint32_t size;
+};
+
+/** Prototype function for callback that is invoked on USB device SOF. */
+typedef void (*usb_d_sof_cb_t)(void);
+
+/** Prototype function for callback that is invoked on USB device events. */
+typedef void (*usb_d_event_cb_t)(const enum usb_event event, const uint32_t param);
+
+/** USB device callbacks. */
+struct usb_d_callbacks {
+	/** Callback that is invoked on SOF. */
+	usb_d_sof_cb_t sof;
+	/** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */
+	usb_d_event_cb_t event;
+};
+
+/** Callback that is invoked when setup packet is received.
+ *  Return \c true if request has been handled, or control endpoint will
+ *  stall IN/OUT transactions.
+ */
+typedef bool (*usb_d_ep_cb_setup_t)(const uint8_t ep, const uint8_t *req);
+
+/** Callback that is invoked when buffer is done without error, but last packet
+ *  is full size packet without ZLP.
+ *  Return \c true if more data has been requested.
+ */
+typedef bool (*usb_d_ep_cb_more_t)(const uint8_t ep, const uint32_t count);
+
+/** Callback that is invoked when all data is finished, including background
+ *  transfer, or error happens.
+ *  In control transfer data stage, return value is checked,
+ *  return \c false if no error happens.
+ */
+typedef bool (*usb_d_ep_cb_xfer_t)(const uint8_t ep, const enum usb_xfer_code code, void *param);
+
+/**
+ *  \brief Initialize the USB device driver
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_init(void);
+
+/**
+ *  \brief Deinitialize the USB device driver
+ */
+void usb_d_deinit(void);
+
+/**
+ *  \brief Register the USB device callback
+ *  \param[in] type The callback type to register.
+ *  \param[in] func The callback function, NULL to disable callback.
+ */
+void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func);
+
+/**
+ *  \brief Enable the USB device driver
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_enable(void);
+
+/**
+ *  \brief Disable the USB device driver
+ */
+void usb_d_disable(void);
+
+/**
+ *  \brief Attach the USB device
+ */
+void usb_d_attach(void);
+
+/**
+ *  \brief Detach the USB device
+ */
+void usb_d_detach(void);
+
+/**
+ *  \brief Retrieve current USB working speed.
+ *  \return USB Speed. See \ref usb_speed.
+ */
+enum usb_speed usb_d_get_speed(void);
+
+/**
+ *  \brief Retrieve current USB frame number.
+ *  \return Frame number.
+ */
+uint16_t usb_d_get_frame_num(void);
+
+/**
+ *  \brief Retrieve current USB micro frame number.
+ *  \return Micro frame number inside a frame (0~7).
+ *          0 if not available (not HS).
+ */
+uint8_t usb_d_get_uframe_num(void);
+
+/**
+ *  \brief Set the USB address that is used.
+ *  \param[in] addr The address to set.
+ */
+void usb_d_set_address(const uint8_t addr);
+
+/**
+ *  \brief Send remote wakeup to host
+ *  \return Operation status.
+ */
+void usb_d_send_remotewakeup(void);
+
+/**
+ *  \brief Initialize the endpoint 0.
+ *
+ *  Note that endpoint 0 must be initialized as control endpoint.
+ *
+ *  \param[in] max_pkt_size Max. packet size of EP0.
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_ep0_init(const uint8_t max_pkt_size);
+
+/**
+ *  \brief Initialize the endpoint.
+ *
+ *  \param[in] ep The endpoint address.
+ *  \param[in] attr The endpoint attributes.
+ *  \param[in] max_pkt_size Max. packet size of EP0.
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size);
+
+/**
+ *  \brief Disable and deinitialize the endpoint.
+ *  \param[in] ep The endpoint address to deinitialize.
+ */
+void usb_d_ep_deinit(const uint8_t ep);
+
+/**
+ *  \brief Register the USB device endpoint callback on initialized endpoint.
+ *
+ *  \param[in] ep The endpoint address.
+ *  \param[in] type The callback type to register.
+ *  \param[in] func The callback function, NULL to disable callback.
+ */
+void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func);
+
+/**
+ *  \brief Enabled the initialized endpoint.
+ *
+ *  Setup request will be monitored after enabling a control endpoint.
+ *
+ *  \param[in] ep The endpoint address.
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_ep_enable(const uint8_t ep);
+
+/**
+ *  \brief Disable the initialized endpoint.
+ *  \param[in] ep The endpoint address.
+ */
+void usb_d_ep_disable(const uint8_t ep);
+
+/**
+ *  \brief Get request data pointer to access received setup request packet
+ *  \param[in] ep The endpoint address.
+ *  \return Pointer to the request data.
+ *  \retval NULL The endpoint is not a control endpoint.
+ */
+uint8_t *usb_d_ep_get_req(const uint8_t ep);
+
+/**
+ *  \brief Endpoint transfer.
+ *
+ *  For control endpoints, start the transfer according to the direction in the bmRequest
+ *  type, and finish with STATUS stage.
+ *  For non-control endpoints, the transfer will be unique direction. Defined by
+ *  bit 8 of the endpoint address.
+ *
+ *  \param[in] xfer Pointer to the transfer description.
+ *  \return Operation status.
+ *  \retval 0 Success.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer);
+
+/**
+ *  \brief Abort an on-going transfer on a specific endpoint.
+ *
+ *  \param[in] ep The endpoint address.
+ */
+void usb_d_ep_abort(const uint8_t ep);
+
+/**
+ *  \brief Retrieve the endpoint status.
+ *
+ *  \param[in] ep The endpoint address.
+ *  \param[out] stat Pointer to the buffer to fill the status description.
+ *
+ *  \return Endpoint status.
+ *  \retval 1 Busy.
+ *  \retval 0 Idle.
+ *  \retval <0 Error code.
+ */
+int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat);
+
+/**
+ *  \brief Endpoint halt control.
+ *
+ *  \param[in] ep The endpoint address.
+ *  \param[in] ctrl Control code (SET/CLEAR/GET).
+ *
+ *  \return Operation status or HALT state (if \c ctrl is \ref USB_EP_HALT_GET).
+ */
+int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl);
+
+/** \brief Retrieve the current driver version
+ *
+ *  \return Current driver version.
+ */
+uint32_t usb_d_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_USB_DEVICE_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_cmcc.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_cmcc.h
new file mode 100644
index 000000000..cb260913b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_cmcc.h
@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief Generic CMCC(Cortex M Cache Controller) related functionality.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef HPL_CMCC_H_
+#define HPL_CMCC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * \Cache driver MACROS
+ */
+#define CMCC_DISABLE 0U
+#define CMCC_ENABLE 1U
+#define IS_CMCC_DISABLED 0U
+#define IS_CMCC_ENABLED 1U
+#define CMCC_WAY_NOS 4U
+#define CMCC_LINE_NOS 64U
+#define CMCC_MONITOR_DISABLE 0U
+
+/**
+ * \brief Cache size configurations
+ */
+enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB };
+
+/**
+ * \brief Way Numbers
+ */
+enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 };
+
+/**
+ * \brief Cache monitor configurations
+ */
+enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT };
+
+/**
+ * \brief Cache configuration structure
+ */
+struct _cache_cfg {
+	enum conf_cache_size cache_size;
+	bool                 data_cache_disable;
+	bool                 inst_cache_disable;
+	bool                 gclk_gate_disable;
+};
+
+/**
+ * \brief Cache enable status
+ */
+static inline bool _is_cache_enabled(const void *hw)
+{
+	return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false);
+}
+
+/**
+ * \brief Cache disable status
+ */
+static inline bool _is_cache_disabled(const void *hw)
+{
+	return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false);
+}
+
+/**
+ * \brief Cache enable
+ */
+static inline int32_t _cmcc_enable(const void *hw)
+{
+	int32_t return_value;
+
+	if (_is_cache_disabled(hw)) {
+		hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN);
+		return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE;
+	} else {
+		return_value = ERR_NO_CHANGE;
+	}
+
+	return return_value;
+}
+
+/**
+ * \brief Cache disable
+ */
+static inline int32_t _cmcc_disable(const void *hw)
+{
+	hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos));
+	while (!(_is_cache_disabled(hw)))
+		;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize Cache Module
+ *
+ * This function initialize low level cmcc module configuration.
+ *
+ * \return initialize status
+ */
+int32_t _cmcc_init(void);
+
+/**
+ * \brief Configure CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] cache configuration structure pointer
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl);
+
+/**
+ * \brief Enable data cache in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_data_cache(const void *hw, bool value);
+
+/**
+ * \brief Enable instruction cache in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_inst_cache(const void *hw, bool value);
+
+/**
+ * \brief Enable clock gating in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_clock_gating(const void *hw, bool value);
+
+/**
+ * \brief Configure the cache size in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from cache size configuration enumerator
+ *				0->1K, 1->2K, 2->4K(default)
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size);
+
+/**
+ * \brief Lock the mentioned WAY in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num_index" enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_lock_way(const void *hw, enum way_num_index);
+
+/**
+ * \brief Unlock the mentioned WAY in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num_index" enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_unlock_way(const void *hw, enum way_num_index);
+
+/**
+ * \brief Invalidate the mentioned cache line in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from "way_num" enumerator (valid arg is 0-3)
+ * \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num);
+
+/**
+ * \brief Invalidate entire cache entries in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_invalidate_all(const void *hw);
+
+/**
+ * \brief Configure cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ * \param[in] element from cache monitor configurations enumerator
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg);
+
+/**
+ * \brief Enable cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_enable_monitor(const void *hw);
+
+/**
+ * \brief Disable cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_disable_monitor(const void *hw);
+
+/**
+ * \brief Reset cache monitor in CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return status of operation
+ */
+int32_t _cmcc_reset_monitor(const void *hw);
+
+/**
+ * \brief Get cache monitor event counter value from CMCC module
+ *
+ * \param[in] pointer pointing to the starting address of CMCC module
+ *
+ * \return event counter value
+ */
+uint32_t _cmcc_get_monitor_event_count(const void *hw);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* HPL_CMCC_H_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_core.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_core.h
new file mode 100644
index 000000000..9324c43e7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_core.h
@@ -0,0 +1,56 @@
+/**
+ * \file
+ *
+ * \brief CPU core related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CORE_H_INCLUDED
+#define _HPL_CORE_H_INCLUDED
+
+/**
+ * \addtogroup HPL Core
+ *
+ * \section hpl_core_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_core_port.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_CORE_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_dma.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_dma.h
new file mode 100644
index 000000000..1e08434a1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_dma.h
@@ -0,0 +1,176 @@
+/**
+ * \file
+ *
+ * \brief DMA related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_DMA_H_INCLUDED
+#define _HPL_DMA_H_INCLUDED
+
+/**
+ * \addtogroup HPL DMA
+ *
+ * \section hpl_dma_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct _dma_resource;
+
+/**
+ * \brief DMA callback types
+ */
+enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
+
+/**
+ * \brief DMA interrupt callbacks
+ */
+struct _dma_callbacks {
+	void (*transfer_done)(struct _dma_resource *resource);
+	void (*error)(struct _dma_resource *resource);
+};
+
+/**
+ * \brief DMA resource structure
+ */
+struct _dma_resource {
+	struct _dma_callbacks dma_cb;
+	void *                back;
+};
+
+/**
+ * \brief Initialize DMA
+ *
+ * This function does low level DMA configuration.
+ *
+ * \return initialize status
+ */
+int32_t _dma_init(void);
+
+/**
+ * \brief Set destination address
+ *
+ * \param[in] channel DMA channel to set destination address for
+ * \param[in] dst Destination address
+ *
+ * \return setting status
+ */
+int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
+
+/**
+ * \brief Set source address
+ *
+ * \param[in] channel DMA channel to set source address for
+ * \param[in] src Source address
+ *
+ * \return setting status
+ */
+int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
+
+/**
+ * \brief Set next descriptor address
+ *
+ * \param[in] current_channel Current DMA channel to set next descriptor address
+ * \param[in] next_channel Next DMA channel used as next descriptor
+ *
+ * \return setting status
+ */
+int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
+
+/**
+ * \brief Enable/disable source address incrementation during DMA transaction
+ *
+ * \param[in] channel DMA channel to set source address for
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return status of operation
+ */
+int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
+
+/**
+ * \brief Enable/disable Destination address incrementation during DMA transaction
+ *
+ * \param[in] channel DMA channel to set destination address for
+ * \param[in] enable True to enable, false to disable
+ *
+ * \return status of operation
+ */
+int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
+/**
+ * \brief Set the amount of data to be transfered per transaction
+ *
+ * \param[in] channel DMA channel to set data amount for
+ * \param[in] amount Data amount
+ *
+ * \return status of operation
+ */
+int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
+
+/**
+ * \brief Trigger DMA transaction on the given channel
+ *
+ * \param[in] channel DMA channel to trigger transaction on
+ *
+ * \return status of operation
+ */
+int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
+
+/**
+ * \brief Retrieves DMA resource structure
+ *
+ * \param[out] resource The resource to be retrieved
+ * \param[in] channel DMA channel to retrieve structure for
+ *
+ * \return status of operation
+ */
+int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
+
+/**
+ * \brief Enable/disable DMA interrupt
+ *
+ * \param[in] channel DMA channel to enable/disable interrupt for
+ * \param[in] type The type of interrupt to disable/enable if applicable
+ * \param[in] state Enable or disable
+ */
+void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HPL_DMA_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_gpio.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_gpio.h
new file mode 100644
index 000000000..5cdd387b8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_gpio.h
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief Port related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_GPIO_H_INCLUDED
+#define _HPL_GPIO_H_INCLUDED
+
+/**
+ * \addtogroup HPL Port
+ *
+ * \section hpl_port_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * \brief Macros for the pin and port group, lower 5
+ * bits stands for pin number in the group, higher 3
+ * bits stands for port group
+ */
+#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
+#define GPIO_PORT(n) ((n) >> 5)
+#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
+#define GPIO_PIN_FUNCTION_OFF 0xffffffff
+
+/**
+ * \brief PORT pull mode settings
+ */
+enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
+
+/**
+ * \brief PORT direction settins
+ */
+enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
+
+/**
+ * \brief PORT group abstraction
+ */
+
+enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Port initialization function
+ *
+ * Port initialization function should setup the port module based
+ * on a static configuration file, this function should normally
+ * not be called directly, but is a part of hal_init()
+ */
+void _gpio_init(void);
+
+/**
+ * \brief Set direction on port with mask
+ *
+ * Set data direction for each pin, or disable the pin
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask      Bit mask where 1 means apply direction setting to the
+ *                      corresponding pin
+ * \param[in] direction GPIO_DIRECTION_OFF  = set pin direction to input
+ *                      and disable input buffer to disable the pin
+ *                      GPIO_DIRECTION_IN   = set pin direction to input
+ *                      and enable input buffer to enable the pin
+ *                      GPIO_DIRECTION_OUT  = set pin direction to output
+ *                      and disable input buffer
+ */
+static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
+                                       const enum gpio_direction direction);
+
+/**
+ * \brief Set output level on port with mask
+ *
+ * Sets output state on pin to high or low with pin masking
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply direction setting to
+ *                  the corresponding pin
+ * \param[in] level true  = pin level is set to 1
+ *                  false = pin level is set to 0
+ */
+static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
+
+/**
+ * \brief Change output level to the opposite with mask
+ *
+ * Change pin output level to the opposite with pin masking
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] mask  Bit mask where 1 means apply direction setting to
+ *                  the corresponding pin
+ */
+static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
+
+/**
+ * \brief Get input levels on all port pins
+ *
+ * Get input level on all port pins, will read IN register if configured to
+ * input and OUT register if configured as output
+ *
+ * \param[in] port  Ports are grouped into groups of maximum 32 pins,
+ *                  GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port);
+
+/**
+ * \brief Set pin pull mode
+ *
+ * Set pull mode on a single pin
+ *
+ * \notice This function will automatically change pin direction to input
+ *
+ * \param[in] port      Ports are grouped into groups of maximum 32 pins,
+ *                      GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
+ * \param[in] pin       The pin in the group that pull mode should be selected
+ *                      for
+ * \param[in] pull_mode GPIO_PULL_OFF  = pull resistor on pin is disabled
+ *                      GPIO_PULL_DOWN = pull resistor on pin will pull pin
+ *                      level to ground level
+ *                      GPIO_PULL_UP   = pull resistor on pin will pull pin
+ *                      level to VCC
+ */
+static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
+                                           const enum gpio_pull_mode pull_mode);
+
+/**
+ * \brief Set gpio function
+ *
+ * Select which function a gpio is used for
+ *
+ * \param[in] gpio     The gpio to set function for
+ * \param[in] function The gpio function is given by a 32-bit wide bitfield
+ *                     found in the header files for the device
+ *
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
+
+#include <hpl_gpio_base.h>
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_GPIO_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_init.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_init.h
new file mode 100644
index 000000000..71bf49c98
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_init.h
@@ -0,0 +1,124 @@
+/**
+ * \file
+ *
+ * \brief Init related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_INIT_H_INCLUDED
+#define _HPL_INIT_H_INCLUDED
+
+/**
+ * \addtogroup HPL Init
+ *
+ * \section hpl_init_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initializes clock sources
+ */
+void _sysctrl_init_sources(void);
+
+/**
+ * \brief Initializes Power Manager
+ */
+void _pm_init(void);
+
+/**
+ * \brief Initialize generators
+ */
+void _gclk_init_generators(void);
+
+/**
+ * \brief Initialize 32 kHz clock sources
+ */
+void _osc32kctrl_init_sources(void);
+
+/**
+ * \brief Initialize clock sources
+ */
+void _oscctrl_init_sources(void);
+
+/**
+ * \brief Initialize clock sources that need input reference clocks
+ */
+void _sysctrl_init_referenced_generators(void);
+
+/**
+ * \brief Initialize clock sources that need input reference clocks
+ */
+void _oscctrl_init_referenced_generators(void);
+
+/**
+ * \brief Initialize master clock generator
+ */
+void _mclk_init(void);
+
+/**
+ * \brief Initialize clock generator
+ */
+void _lpmcu_misc_regs_init(void);
+
+/**
+ * \brief Initialize clock generator
+ */
+void _pmc_init(void);
+
+/**
+ * \brief Set performance level
+ *
+ * \param[in] level The performance level to set
+ */
+void _set_performance_level(const uint8_t level);
+
+/**
+ * \brief Initialize the chip
+ */
+void _init_chip(void);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_INIT_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_irq.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_irq.h
new file mode 100644
index 000000000..2894944a0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_irq.h
@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief IRQ related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_IRQ_H_INCLUDED
+#define _HPL_IRQ_H_INCLUDED
+
+/**
+ * \addtogroup HPL IRQ
+ *
+ * \section hpl_irq_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief IRQ descriptor
+ */
+struct _irq_descriptor {
+	void (*handler)(void *parameter);
+	void *parameter;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Retrieve current IRQ number
+ *
+ * \return The current IRQ number
+ */
+uint8_t _irq_get_current(void);
+
+/**
+ * \brief Disable the given IRQ
+ *
+ * \param[in] n The number of IRQ to disable
+ */
+void _irq_disable(uint8_t n);
+
+/**
+ * \brief Set the given IRQ
+ *
+ * \param[in] n The number of IRQ to set
+ */
+void _irq_set(uint8_t n);
+
+/**
+ * \brief Clear the given IRQ
+ *
+ * \param[in] n The number of IRQ to clear
+ */
+void _irq_clear(uint8_t n);
+
+/**
+ * \brief Enable the given IRQ
+ *
+ * \param[in] n The number of IRQ to enable
+ */
+void _irq_enable(uint8_t n);
+
+/**
+ * \brief Register IRQ handler
+ *
+ * \param[in] number The number registered IRQ
+ * \param[in] irq The pointer to irq handler to register
+ *
+ * \return The status of IRQ handler registering
+ * \retval -1 Passed parameters were invalid
+ * \retval 0 The registering is completed successfully
+ */
+void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_IRQ_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_missing_features.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_missing_features.h
new file mode 100644
index 000000000..7071db297
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_missing_features.h
@@ -0,0 +1,37 @@
+/**
+ * \file
+ *
+ * \brief Family-dependent missing features expected by HAL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_MISSING_FEATURES
+#define _HPL_MISSING_FEATURES
+
+#endif /* _HPL_MISSING_FEATURES */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_ramecc.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_ramecc.h
new file mode 100644
index 000000000..d79d51418
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_ramecc.h
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief RAMECC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_RAMECC_H_INCLUDED
+#define _HPL_RAMECC_H_INCLUDED
+
+/**
+ * \addtogroup HPL RAMECC
+ *
+ * \section hpl_ramecc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <compiler.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief RAMECC callback type
+ */
+typedef void (*ramecc_cb_t)(const uint32_t data);
+
+/**
+ * \brief RAMECC callback types
+ */
+enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB };
+
+/**
+ * \brief RAMECC interrupt callbacks
+ */
+struct _ramecc_callbacks {
+	ramecc_cb_t dual_bit_err;
+	ramecc_cb_t single_bit_err;
+};
+
+/**
+ * \brief RAMECC device structure
+ */
+struct _ramecc_device {
+	struct _ramecc_callbacks ramecc_cb;
+	struct _irq_descriptor   irq;
+};
+
+/**
+ * \brief Initialize RAMECC
+ *
+ * This function does low level RAMECC configuration.
+ *
+ * \return initialize status
+ */
+int32_t _ramecc_init(void);
+
+/**
+ * \brief Register RAMECC callback
+ *
+ * \param[in] type The type of callback
+ * \param[in] cb A callback function
+ */
+void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_RAMECC_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_reset.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_reset.h
new file mode 100644
index 000000000..d627ea650
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_reset.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief Reset related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_RESET_H_INCLUDED
+#define _HPL_RESET_H_INCLUDED
+
+/**
+ * \addtogroup HPL Reset
+ *
+ * \section hpl_reset_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Reset reason enumeration
+ *
+ * The list of possible reset reasons.
+ */
+enum reset_reason {
+	RESET_REASON_POR    = 1,
+	RESET_REASON_BOD12  = 2,
+	RESET_REASON_BOD33  = 4,
+	RESET_REASON_NVM    = 8,
+	RESET_REASON_EXT    = 16,
+	RESET_REASON_WDT    = 32,
+	RESET_REASON_SYST   = 64,
+	RESET_REASON_BACKUP = 128
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Retrieve the reset reason
+ *
+ * Retrieves the reset reason of the last MCU reset.
+ *
+ *\return An enum value indicating the reason of the last reset.
+ */
+enum reset_reason _get_reset_reason(void);
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_RESET_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_sleep.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_sleep.h
new file mode 100644
index 000000000..6731ec30e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_sleep.h
@@ -0,0 +1,88 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_SLEEP_H_INCLUDED
+#define _HPL_SLEEP_H_INCLUDED
+
+/**
+ * \addtogroup HPL Sleep
+ *
+ * \section hpl_sleep_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Set the sleep mode for the device
+ *
+ * This function sets the sleep mode for the device.
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes see datasheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return the status of a sleep request
+ * \retval -1 The requested sleep mode was invalid
+ * \retval  0 The operation completed successfully, sleep mode is set
+ */
+int32_t _set_sleep_mode(const uint8_t mode);
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void);
+
+/**
+ * \brief Put MCU to sleep
+ */
+void _go_to_sleep(void);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_SLEEP_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb.h
new file mode 100644
index 000000000..2e165d7ac
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb.h
@@ -0,0 +1,270 @@
+/**
+ * \file
+ *
+ * \brief SAM USB HPL
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USB_H_INCLUDED
+#define _HPL_USB_H_INCLUDED
+
+#include <compiler.h>
+#include <utils.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \name USB Spec definitions */
+/*@{*/
+
+/** Return 8-bit unsigned USB data. */
+#define USB_GET_U8(addr, offset) (((uint8_t *)(addr))[(offset)])
+
+/** Return 16-bit unsigned USB data. */
+#define USB_GET_U16(addr, offset) ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8))
+
+/** Return 32-bit unsigned USB data. */
+#define USB_GET_U32(addr, offset)                                                                                      \
+	((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8)                               \
+	 + (((uint8_t *)(addr))[(offset) + 2] << 16) + (((uint8_t *)(addr))[(offset) + 3] << 32))
+
+/** Offset of bmRequestType in USB request buffer. */
+#define USB_bmRequestType_Offset 0
+
+/** Offset of bRequest in USB request buffer. */
+#define USB_bRequest_Offset 1
+
+/** Offset of wValue in USB request buffer. */
+#define USB_wValue_Offset 2
+
+/** Offset of wIndex in USB request buffer. */
+#define USB_wIndex_Offset 4
+
+/** Offset of wLength in USB request buffer. */
+#define USB_wLength_Offset 6
+
+/** Get value of bmRequestType from USB request. */
+#define USB_GET_bmRequestType(req) USB_GET_U8((req), USB_bmRequestType_Offset)
+
+/** Get value of bRequest from USB request. */
+#define USB_GET_bRequest(req) USB_GET_U8((req), USB_bRequest_Offset)
+
+/** Get value of wValue from USB request. */
+#define USB_GET_wValue(req) USB_GET_U16((req), USB_wValue_Offset)
+
+/** Get value of wIndex from USB request. */
+#define USB_GET_wIndex(req) USB_GET_U16((req), USB_wIndex_Offset)
+
+/** Get value of wLength from USB request. */
+#define USB_GET_wLength(req) USB_GET_U16((req), USB_wLength_Offset)
+
+/** USB request IN indication of bmRequestType. */
+#define USB_REQ_TYPE_IN 0x80u
+
+/** USB endpoint number mask of bEndpointAddress. */
+#define USB_EP_N_MASK 0x0Fu
+
+/** USB endpoint direction bit of bEndpointAddress. */
+#define USB_EP_DIR 0x80u
+
+/** Get USB endpoint direction from endpoint address. */
+#define USB_EP_GET_DIR(ep_addr) ((ep_addr)&USB_EP_DIR)
+
+/** Get USB endpoint number from endpoint address. */
+#define USB_EP_GET_N(ep_addr) ((ep_addr)&USB_EP_N_MASK)
+
+/** Transfer type in EP descriptor bmAttributes: Control. */
+#define USB_EP_XTYPE_CTRL 0x0
+
+/** Transfer type in EP descriptor bmAttributes: Isochronous. */
+#define USB_EP_XTYPE_ISOCH 0x1
+
+/** Transfer type in EP descriptor bmAttributes: Bulk. */
+#define USB_EP_XTYPE_BULK 0x2
+
+/** Transfer type in EP descriptor bmAttributes: Interrupt. */
+#define USB_EP_XTYPE_INTERRUPT 0x3
+
+/** Transfer type mask in EP descriptor bmAttributes. */
+#define USB_EP_XTYPE_MASK 0x3u
+
+/*@}*/
+
+/** \name USB status codes
+ *@{
+ */
+/** USB operation is done successfully. */
+#define USB_OK 0
+/** USB (endpoint) is busy. */
+#define USB_BUSY 1
+/** USB (endpoint) is halted. */
+#define USB_HALTED 2
+
+/** General error. */
+#define USB_ERROR 0x10
+/** Operation is denied by hardware (e.g., syncing). */
+#define USB_ERR_DENIED 0x11
+/** Input parameter error. */
+#define USB_ERR_PARAM 0x12
+/** Functionality is not supported (e.g., initialize endpoint without cache to be control). */
+#define USB_ERR_FUNC 0x13
+/** Re-initialize, re-enable ... */
+#define USB_ERR_REDO 0x14
+/** Not enough resource (memory, endpoints ...). */
+#define USB_ERR_ALLOC_FAIL 0x15
+/*@}*/
+
+/** USB speed. */
+enum usb_speed {
+	/** USB Low Speed. */
+	USB_SPEED_LS,
+	/** USB Full Speed. */
+	USB_SPEED_FS,
+	/** USB High Speed. */
+	USB_SPEED_HS,
+	/** USB Super Speed. */
+	USB_SPEED_SS
+};
+
+/** USB transaction type. */
+enum usb_trans_type {
+	/** USB SETUP transaction. */
+	USB_TRANS_SETUP,
+	/** USB IN transaction. */
+	USB_TRANS_IN,
+	/** USB OUT transaction. */
+	USB_TRANS_OUT
+};
+
+/** USB events that generates the device callbacks. */
+enum usb_event {
+	/** USB VBus changed, with parameter as present/not present. */
+	USB_EV_VBUS,
+	/** USB RESET detected on bus. */
+	USB_EV_RESET,
+	/** USB wakeup. */
+	USB_EV_WAKEUP,
+	/** USB LPM suspend, with parameter as \ref usb_lpm_attributes. */
+	USB_EV_LPM_SUSPEND,
+	/** USB suspend. */
+	USB_EV_SUSPEND,
+	/** USB error, with parameter as error code. */
+	USB_EV_ERROR,
+	/** Number of USB event types. */
+	USB_EV_N
+};
+
+/** Control action for USB device endpoint stall. */
+enum usb_ep_stall_ctrl {
+	/** Clear stall of the endpoint. */
+	USB_EP_STALL_CLR,
+	/** Stall the endpoint. */
+	USB_EP_STALL_SET,
+	/** Return the stall status. */
+	USB_EP_STALL_GET
+};
+
+/** Control action for USB device endpoint halt. */
+enum usb_ep_halt_ctrl {
+	/** Clear halt of the endpoint. */
+	USB_EP_HALT_CLR = USB_EP_STALL_CLR,
+	/** Stall the endpoint. */
+	USB_EP_HALT_SET = USB_EP_STALL_SET,
+	/** Return the halt status. */
+	USB_EP_HALT_GET = USB_EP_STALL_GET
+};
+
+/** USB transactions status codes. */
+enum usb_trans_code {
+	/** TX or RX has been done without error. */
+	USB_TRANS_DONE,
+	/** The endpoint is stalled. */
+	USB_TRANS_STALL,
+	/** The endpoint transactions are aborted (cancel, control setup/status). */
+	USB_TRANS_ABORT,
+	/** The endpoint transactions are aborted by reset/disable. */
+	USB_TRANS_RESET,
+	/** Error is reported on the endpoint. */
+	USB_TRANS_ERROR
+};
+
+/** Transfer status codes. */
+enum usb_xfer_code {
+	/** Transfer is done without error, for ctrl it means status packet done. */
+	USB_XFER_DONE,
+	/** For control transfer only, data stage is done without error. */
+	USB_XFER_DATA,
+	/** Endpoint stall is set. */
+	USB_XFER_HALT,
+	/** Endpoint stall is cleared. */
+	USB_XFER_UNHALT,
+	/** Transfer is aborted. */
+	USB_XFER_ABORT,
+	/** Transfer is aborted because endpoint reset/disable. */
+	USB_XFER_RESET,
+	/** There was an error. */
+	USB_XFER_ERROR
+};
+
+/** USB endpoint errors. */
+enum usb_ep_error {
+	/** No error. */
+	USB_EP_NO_ERROR,
+	/** CRC error. */
+	USB_EP_ERR_CRC,
+	/** Endpoint transfer overflow. */
+	USB_EP_ERR_OVERFLOW,
+	/** Other endpoint errors. */
+	USB_EP_ERR_GENERAL
+};
+
+/** Endpoint transfer state. */
+enum usb_ep_state {
+	/** Endpoint is disabled. */
+	USB_EP_S_DISABLED,
+	/** Endpoint is not busy. */
+	USB_EP_S_IDLE,
+	/** Control transfer only, endpoint is transferring setup packet. */
+	USB_EP_S_X_SETUP,
+	/** Endpoint is transferring data. */
+	USB_EP_S_X_DATA,
+	/** Control transfer only, endpoint is in status stage. */
+	USB_EP_S_X_STATUS,
+	/** Endpoint is halted. */
+	USB_EP_S_HALTED,
+	/** Endpoint error. */
+	USB_EP_S_ERROR
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_USB_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb_device.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb_device.h
new file mode 100644
index 000000000..43dd17fb3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb_device.h
@@ -0,0 +1,377 @@
+/**
+ * \file
+ *
+ * \brief SAM USB HPL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USB_DEVICE_H_INCLUDED
+#define _HPL_USB_DEVICE_H_INCLUDED
+
+#include <hpl_usb.h>
+#include "hpl_usb_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB Device callback type. */
+enum usb_d_cb_type {
+	/** USB device SOF callback. */
+	USB_D_CB_SOF,
+	/** USB device events callbacks. */
+	USB_D_CB_EVENT,
+	/** Number of types of USB device callback types. */
+	USB_D_CB_N
+};
+
+/** USB Device endpoint callback type. */
+enum usb_d_ep_cb_type {
+	/** USB device endpoint setup callback. */
+	USB_D_EP_CB_SETUP,
+	/** USB device endpoint more data callback. */
+	USB_D_EP_CB_MORE,
+	/** USB device endpoint transaction done or error callback. */
+	USB_D_EP_CB_XFER,
+	/** Number of types of USB device endpoint callback types. */
+	USB_D_EP_CB_N
+};
+
+/** Control action for USB device LPM handshake. */
+enum usb_d_lpm_ctrl {
+	/** No LPM handshake, not supported. */
+	USB_D_LPM_DISABLE,
+	/** ACK the LPM transaction. */
+	USB_D_LPM_ACK,
+	/** NYET the LPM transaction. */
+	USB_D_LPM_NYET
+};
+
+/**
+ *  USB device transfer descriptor.
+ */
+struct usb_d_transfer {
+	/** Pointer to data buffer to transfer.
+	 *  Note that it's recommended that the buffer is 32-bit aligned since
+	 *  some of USB peripheral require this.
+	 */
+	uint8_t *buf;
+	/** Transfer size, in number of bytes.
+	 *  Note that it's recommended that the buffer size is 32-bit aligned
+	 *  (modeled by 4) since some of USB peripheral require this.
+	 */
+	uint32_t size;
+	/** Endpoint address. */
+	uint8_t ep;
+	/** Append ZLP for IN transfer, wait ZLP for OUT transfer. */
+	uint8_t zlp;
+};
+
+/** USB device transactions status structure. */
+struct usb_d_trans_status {
+	/** Total data size. */
+	uint32_t size;
+	/** Total transfered data count. */
+	uint32_t count;
+	/** Endpoint address. */
+	uint8_t ep;
+	/** Endpoint type - CTRL/ISO/INT/BULK. */
+	uint8_t xtype : 2;
+	/** Transactions state, busy or not. */
+	uint8_t busy : 1;
+	/** Transactions state, setup received or not. */
+	uint8_t setup : 1;
+	/** Transactions state, stall or not. */
+	uint8_t stall : 1;
+	/** Transactions direction. */
+	uint8_t dir : 1;
+};
+
+/** Prototype function for callback that is invoked on USB device SOF. */
+typedef void (*_usb_d_dev_sof_cb_t)(void);
+
+/** Prototype function for callback that is invoked on USB device events. */
+typedef void (*_usb_d_dev_event_cb_t)(const enum usb_event, const uint32_t param);
+
+/** HPL USB device callbacks. */
+struct _usb_d_dev_callbacks {
+	/** Callback that is invoked on SOF. */
+	_usb_d_dev_sof_cb_t sof;
+	/** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */
+	_usb_d_dev_event_cb_t event;
+};
+
+/** USB device endpoint callbacks. */
+enum usb_d_dev_ep_cb_type {
+	/** Setup packet is received. */
+	USB_D_DEV_EP_CB_SETUP,
+	/** Try to require more data. */
+	USB_D_DEV_EP_CB_MORE,
+	/** Transaction done OK/ERROR. */
+	USB_D_DEV_EP_CB_DONE,
+	/** Number of device endpoint callbacks. */
+	USB_D_DEV_EP_CB_N
+};
+
+/**
+ *  Callback that is invoked when control SETUP packet has bee received.
+ *  \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and allow
+ *  IN/OUT transactions on control endpoint.
+ */
+typedef void (*_usb_d_dev_ep_cb_setup_t)(const uint8_t ep);
+
+/** Callback that is invoked when buffer is done, but last packet is full size
+ *  packet without ZLP. Return \c true if more data has been requested. */
+typedef bool (*_usb_d_dev_ep_cb_more_t)(const uint8_t ep, const uint32_t transfered);
+
+/** Callback that is invoked when all data is finished, including background
+ *  transfer, or error happens. */
+typedef void (*_usb_d_dev_ep_cb_done_t)(const uint8_t ep, const int32_t code, const uint32_t transfered);
+
+/** Callbacks for HPL USB device endpoint. */
+struct _usb_d_dev_ep_callbacks {
+	/** Callback that is invoked when SETUP packet is received.
+	 *  \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and
+	 *  allow IN/OUT transactions on control endpoint.
+	 */
+	_usb_d_dev_ep_cb_setup_t setup;
+	/** Callback that is invoked to check if buffer is NULL and more data is
+	 *  required.
+	 *  It's called when last packet is full size packet, without
+	 *  auto ZLP enabled.
+	 *  It could be called when background transfer is still in progress.
+	 */
+	_usb_d_dev_ep_cb_more_t more;
+	/** Callback that is invoked when transaction is done, including background
+	 *  transfer, or error occurs.
+	 */
+	_usb_d_dev_ep_cb_done_t done;
+};
+
+/**
+ * \brief Initialize the USB device instance
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_init(void);
+
+/**
+ * \brief Deinitialize the USB device instance
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+void _usb_d_dev_deinit(void);
+
+/**
+ * \brief Register callback to handle USB device events
+ * \param[in] type Callback type. See \ref usb_d_cb_type.
+ * \param[in] func Pointer to callback function.
+ *         Refer to \ref _usb_d_dev_callbacks for the prototypes.
+ */
+void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func);
+
+/**
+ * \brief Register callback to handle USB device endpoint events
+ * \param[in] type Callback type. See \ref usb_d_dev_ep_cb_type.
+ * \param[in] func Pointer to callback function.
+ *         Refer to \ref _usb_d_dev_ep_callbacks for the prototypes.
+ */
+void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func);
+
+/**
+ * \brief Enable the USB device
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_enable(void);
+
+/**
+ * \brief Disable the USB device
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_disable(void);
+
+/**
+ * \brief Attach the USB device
+ */
+void _usb_d_dev_attach(void);
+
+/**
+ * \brief Detach the USB device
+ */
+void _usb_d_dev_detach(void);
+
+/**
+ * \brief Send the USB device remote wakeup to host
+ */
+void _usb_d_dev_send_remotewakeup(void);
+
+/**
+ * \brief Get the USB device working speed
+ * \return USB speed. See \ref usb_speed.
+ */
+enum usb_speed _usb_d_dev_get_speed(void);
+
+/**
+ * \brief Set the USB device address
+ * \param[in] addr Address to be used.
+ */
+void _usb_d_dev_set_address(const uint8_t addr);
+
+/**
+ * \brief Get the USB device address
+ * \return Address that is used.
+ */
+uint8_t _usb_d_dev_get_address(void);
+
+/**
+ * \brief Get the USB device frame number
+ * \return The frame number.
+ */
+uint16_t _usb_d_dev_get_frame_n(void);
+
+/**
+ * \brief Get the USB device micro frame number
+ * \return The micro frame number inside one frame (0~7).
+ */
+uint8_t _usb_d_dev_get_uframe_n(void);
+
+/**
+ * \brief Initialize and enable the USB device default endpoint 0
+ * \param[in] max_pkt_siz Max endpoint size.
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz);
+
+/**
+ * \brief Initialize and enable the USB device endpoint
+ * \param[in] ep Endpoint address,
+ *               see endpoint descriptor details in USB spec.
+ * \param[in] attr Endpoint attributes,
+ *                 see endpoint descriptor details in USB spec.
+ * \param[in] max_pkt_siz Endpoint size,
+ *                        see endpoint descriptor details in USB spec.
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, uint16_t max_pkt_siz);
+
+/**
+ * \brief Disable and deinitialize the USB device endpoint
+
+ * \param[in] ep The endpoint to deinitialize.
+ */
+void _usb_d_dev_ep_deinit(const uint8_t ep);
+
+/**
+ * \brief Enable the endpoint
+ * \param[in] ep The endpoint to enable.
+ * \return Operation result status.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_ep_enable(const uint8_t ep);
+
+/**
+ * \brief Disable the endpoint
+ * \param[in] ep The endpoint to disable.
+ */
+void _usb_d_dev_ep_disable(const uint8_t ep);
+
+/**
+ * \brief Set/Clear/Get USB device endpoint stall status
+ * \param[in] ep Endpoint address.
+ * \param[in] ctrl Operation selector. See \ref usb_ep_stall_ctrl.
+ * \return Operation result or stall status.
+ * \retval 0 Success or not stall.
+ * \retval 1 Endpoint is stalled.
+ * \retval -1 error.
+ */
+int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl);
+
+/**
+ * \brief Read setup request data from specific endpoint
+ * \param[in] ep Endpoint address.
+ * \param[out] req_buf Pointer to buffer to locate the setup packet.
+ * \return Number of bytes or error code.
+ * \retval <0 error code.
+ * \retval 0 No setup packet ready for read.
+ * \retval >0 Size of bytes read, and ready to start IN/OUT. Note that if
+ *         this number is over 8, only first 8 bytes will be copied.
+ */
+int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf);
+
+/**
+ * \brief Start USB device transfer
+ *
+ * On different USB peripheral hardware the transaction buffer address and size
+ * may have different constraints. E.g., some hardware may require input address
+ * 32-bit aligned, and input size 32-bit aligned. Refer to the corresponding
+ * hardware usage reference documents.
+ * The constraints are checked in implementation, with error code returned.
+ *
+ * \param[in] trans Pointer to the transaction description.
+ * \return Operation result status.
+ * \retval 1 Busy.
+ * \retval 0 Success.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans);
+
+/**
+ * \brief Abort pending USB device transaction on specific endpoint
+ * \param[in] ep Endpoint address to abort.
+ */
+void _usb_d_dev_ep_abort(const uint8_t ep);
+
+/**
+ * \brief Retrieve endpoint status.
+ * \param[in] ep Endpoint address.
+ * \param[out] stat Pointer to buffer to fill status description.
+ * \return Status.
+ * \retval 2 Packet writing.
+ * \retval 1 Busy.
+ * \retval 0 Ready.
+ * \retval <0 Error code.
+ */
+int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_USB_DEVICE_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb_host.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb_host.h
new file mode 100644
index 000000000..635950be6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/include/hpl_usb_host.h
@@ -0,0 +1,618 @@
+/**
+ * \file
+ *
+ * \brief SAM USB host HPL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_USB_HOST_H_INCLUDED
+#define _HPL_USB_HOST_H_INCLUDED
+
+#include <hpl_usb.h>
+#include <hpl_irq.h>
+#include "hpl_usb_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Driver version */
+#define USB_H_VERSION 0x00000001
+
+/**
+ * @brief      USB HCD callback types
+ */
+enum usb_h_cb_type {
+	/** SOF generated */
+	USB_H_CB_SOF,
+	/** Root Hub change detected */
+	USB_H_CB_ROOTHUB_CHANGE,
+	/** Number of USB HCD callback types */
+	USB_H_CB_N
+};
+
+/**
+ * @brief      USB HCD resource strategy
+ */
+enum usb_h_rsc_strategy {
+	/** Normal resource allocation, e.g.,
+	 *  1 bank for interrupt endpoint,
+	 *  2 bank for bulk endpoint and normal iso endpoint,
+	 *  3 bank for iso high bandwidth endpoint.
+	 */
+	USB_H_RSC_NORMAL = false,
+	/** Minimal resource allocation, e.g., only 1 bank for bulk endpoints */
+	USB_H_RSC_MINIMAL = true
+};
+
+/**
+ * @brief      USB HCD pipe states
+ */
+enum usb_h_pipe_state {
+	/** Pipe is free to allocate */
+	USB_H_PIPE_S_FREE = 0x00,
+	/** Pipe is in configuration */
+	USB_H_PIPE_S_CFG = 0x01,
+	/** Pipe is allocated and idle */
+	USB_H_PIPE_S_IDLE = 0x02,
+	/** Pipe in control setup stage */
+	USB_H_PIPE_S_SETUP = 0x03,
+	/** Pipe in data IN stage */
+	USB_H_PIPE_S_DATI = 0x05,
+	/** Pipe in data OUT stage */
+	USB_H_PIPE_S_DATO = 0x06,
+	/** Pipe in data IN ZLP stage */
+	USB_H_PIPE_S_ZLPI = 0x07,
+	/** Pipe in data OUT ZLP stage */
+	USB_H_PIPE_S_ZLPO = 0x08,
+	/** Pipe in control status IN stage */
+	USB_H_PIPE_S_STATI = 0x09,
+	/** Pipe in control status OUT stage */
+	USB_H_PIPE_S_STATO = 0x0A,
+	/** Taken by physical pipe (in process) */
+	USB_H_PIPE_S_TAKEN = 0x10
+};
+
+/**
+ * @brief      USB HCD status code
+ */
+enum usb_h_status {
+	/** OK */
+	USB_H_OK = ERR_NONE,
+	/** Busy */
+	USB_H_BUSY = ERR_BUSY,
+	/** Denied */
+	USB_H_DENIED = ERR_DENIED,
+	/** Timeout */
+	USB_H_TIMEOUT = ERR_TIMEOUT,
+	/** Abort */
+	USB_H_ABORT = ERR_ABORTED,
+	/** Stall protocol */
+	USB_H_STALL = ERR_PROTOCOL,
+	/** Transfer reset by pipe re-configure */
+	USB_H_RESET = ERR_REQ_FLUSHED,
+	/** Argument error */
+	USB_H_ERR_ARG = ERR_INVALID_ARG,
+	/** Operation not supported */
+	USB_H_ERR_UNSP_OP = ERR_UNSUPPORTED_OP,
+	/** No resource */
+	USB_H_ERR_NO_RSC = ERR_NO_RESOURCE,
+	/** Not initialized */
+	USB_H_ERR_NOT_INIT = ERR_NOT_INITIALIZED,
+	/** Some general error */
+	USB_H_ERR = ERR_IO
+};
+
+/** Forward declare for pipe structure */
+struct usb_h_pipe;
+
+/** Forward declare for driver descriptor structure */
+struct usb_h_desc;
+
+/**
+ * \brief Prototyping USB HCD callback of SOF
+ */
+typedef void (*usb_h_cb_sof_t)(struct usb_h_desc *drv);
+
+/**
+ * \brief Prototyping USB HCD callback of root hub changing.
+ * According to the bitmap size, max port number is 31.
+ */
+typedef void (*usb_h_cb_roothub_t)(struct usb_h_desc *drv, uint8_t port, uint8_t ftr);
+
+/**
+ * Prototyping USB HCD callback of pipe transfer done.
+ * For control pipe, it's forced to call even if there is no transfer
+ * in progress, since the pipe size could be changed at run time.
+ */
+typedef void (*usb_h_pipe_cb_xfer_t)(struct usb_h_pipe *pipe);
+
+/** Access to max packet size of a pipe */
+#define usb_h_pipe_max_pkt_size(p) (p->max_pkt_size)
+
+/** Access to device address of a pipe */
+#define usb_h_pipe_dev_addr(p) (p->dev)
+
+/** Access to endpoint address of a pipe */
+#define usb_h_pipe_ep_addr(p) (p->ep)
+
+/** Access to state of a pipe */
+#define usb_h_pipe_state(p) (p->x.general.state)
+
+/** Access to status of a pipe */
+#define usb_h_pipe_status(p) (p->x.general.status)
+
+/**
+ * @brief      USB Host Controller device structure
+ */
+struct usb_h_desc {
+	/** Pointer to hardware base */
+	void *hw;
+	/** Pointer to private data for Host Controller driver */
+	void *prvt;
+	/** Interrupt handling descriptor */
+	struct _irq_descriptor irq;
+	/** Callback of SOF */
+	usb_h_cb_sof_t sof_cb;
+	/** Callback of root hub change */
+	usb_h_cb_roothub_t rh_cb;
+#if CONF_USB_H_INST_OWNER_SP
+	/** Extension for the driver owner (upper layer user) */
+	void *owner;
+#endif
+};
+
+/**
+ * @brief      Transfer descriptor for control transfer
+ *
+ * Timing in USB 2.0 spec.:
+ * - 9.2.6.1 : USB sets an upper limit of 5 seconds as the upper limit for any
+ *             command to be processed.
+ * - 9.2.6.3 : if a device receives a SetAddress() request, the device must be
+ *             able to complete processing of the request and be able to
+ *             successfully complete the Status stage of the request within
+ *             50 ms.
+ *             After successful completion of the Status stage, the device is
+ *             allowed a SetAddress() recovery interval of 2 ms. At the end of
+ *             this interval, the device must be able to accept Setup packets
+ *             addressed to the new address.
+ * - 9.2.6.4 : For standard device requests that require no Data stage, a device
+ *             must be able to complete the request and be able to successfully
+ *             complete the Status stage of the request within 50 ms of receipt
+ *             of the request. This limitation applies to requests to the
+ *             device, interface, or endpoint.
+ *             For standard device requests that require data stage transfer to
+ *             the host, the device must be able to return the first data packet
+ *             to the host within 500 ms of receipt of the request. For
+ *             subsequent data packets, if any, the device must be able to
+ *             return them within 500 ms of successful completion of the
+ *             transmission of the previous packet. The device must then be
+ *             able to successfully complete the status stage within 50 ms after
+ *             returning the last data packet.
+ *             For standard device requests that require a data stage transfer
+ *             to the device, the 5-second limit applies.
+ * - 9.2.6.5 : Unless specifically exempted in the class document, all
+ *             class-specific requests must meet the timing limitations for
+ *             standard device requests.
+ *
+ * Conclusion:
+ * 1. Whole request with data: 5 seconds
+ * 2. Whole request without data: 50 ms
+ * 3. Data packets: 500 ms
+ */
+struct usb_h_ctrl_xfer {
+	/** Pointer to transfer data */
+	uint8_t *data;
+	/** Pointer to setup packet */
+	uint8_t *setup;
+	/** Expected transfer size */
+	uint16_t size;
+	/** Transfer count */
+	uint16_t count;
+	/** Timeout for request, -1 if disable timeout */
+	int16_t req_timeout;
+	/** Timeout between packets
+	 *  (500ms for data and 50ms for status), -1 if disabled */
+	int16_t pkt_timeout;
+	/** Packet size during transfer (<= allocate max packet size) */
+	uint16_t pkt_size;
+
+	/** Transfer state */
+	uint8_t state;
+	/** Last transfer status */
+	int8_t status;
+};
+
+/**
+ * @brief      Transfer descriptor for bulk / interrupt / iso transfer
+ */
+struct usb_h_bulk_int_iso_xfer {
+	/** Expected transfer size */
+	uint32_t size;
+	/** Transfer count */
+	uint32_t count;
+	/** Pointer to transfer data */
+	uint8_t *data;
+	/** Reserved */
+	uint16_t reserved[3];
+
+	/** Transfer state */
+	uint8_t state;
+	/** Last transfer status */
+	int8_t status;
+};
+
+/**
+ * @brief      Transfer descriptor for periodic high bandwidth transfer
+ */
+struct usb_h_high_bw_xfer {
+	/** Expected transfer size */
+	uint32_t size;
+	/** Transfer count */
+	uint32_t count;
+	/** Pointer to transfer data */
+	uint8_t *data;
+	/** Micro frame packet sizes */
+	uint16_t pkt_size[3];
+
+	/** Transfer state */
+	uint8_t state;
+	/** Last transfer status */
+	int8_t status;
+};
+
+/**
+ * @brief General transfer descriptor
+ */
+struct usb_h_xfer {
+	/** Reserved for different transfer */
+	union {
+		uint16_t u16[9];
+		uint8_t  u8[18];
+	} reserved;
+	/** Transfer state */
+	uint8_t state;
+	/** Last transfer status */
+	int8_t status;
+};
+
+/**
+ * @brief      USB Host Controller Driver Pipe structure
+ */
+struct usb_h_pipe {
+	/** Pointer to the USB Host Controller Driver */
+	struct usb_h_desc *hcd;
+	/** Pointer to the callback for transfer done */
+	usb_h_pipe_cb_xfer_t done;
+#if CONF_USB_H_INST_OWNER_SP
+	/** Pointer to the pipe owner */
+	void *owner;
+#endif
+
+	/** Endpoint max packet size (bits 10..0) */
+	uint16_t max_pkt_size;
+	/** Device address */
+	uint8_t dev;
+	/** Endpoint address */
+	uint8_t ep;
+
+	/** Endpoint interval */
+	uint8_t interval;
+	/** Endpoint type: Control, Isochronous, Bulk or Interrupt */
+	uint8_t type;
+	/** Current toggle (driver dependent) */
+	uint8_t toggle;
+	/** Endpoint number of banks (HW dependent) */
+	uint8_t bank : 2;
+	/** Transfer speed (HW dependent) */
+	uint8_t speed : 2;
+	/** High bandwidth periodic out */
+	uint8_t high_bw_out : 1;
+	/** Uses DMA (on transfer) */
+	uint8_t dma : 1;
+	/** Transfer ZLP support */
+	uint8_t zlp : 1;
+	/** Transfer periodic */
+	uint8_t periodic_start : 1;
+
+	/** Transfer status */
+	union {
+		/** General transfer info */
+		struct usb_h_xfer general;
+		/** Control transfer status */
+		struct usb_h_ctrl_xfer ctrl;
+		/** Bulk interrupt iso transfer status */
+		struct usb_h_bulk_int_iso_xfer bii;
+		/** Periodic high bandwidth transfer status */
+		struct usb_h_high_bw_xfer hbw;
+	} x;
+};
+
+/**
+ * @brief      USB HCD Initialization
+ *
+ * @param      drv     Pointer to the HCD driver instance
+ * @param[in]  hw      Pointer to hardware base
+ * @param[in]  prvt    The private driver data (implement specific)
+ *
+ * @return     Operation result status
+ * @retval     ERR_DENIED Hardware has been enabled
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_init(struct usb_h_desc *drv, void *hw, void *prvt);
+
+/**
+ * @brief      USB HCD de-initialization
+ *
+ * @param      drv   The driver
+ */
+void _usb_h_deinit(struct usb_h_desc *drv);
+
+/**
+ * @brief      USB HCD enable
+ *
+ * @param      drv   The driver
+ */
+void _usb_h_enable(struct usb_h_desc *drv);
+
+/**
+ * @brief      USB HCD disable
+ *
+ * @param      drv   The driver
+ */
+void _usb_h_disable(struct usb_h_desc *drv);
+
+/**
+ * @brief      Register callbacks for USB HCD
+ *
+ * @param      drv   The driver
+ * @param[in]  type  The callback type
+ * @param[in]  cb    The callback function entry
+ *
+ * @return     Operation result status
+ * @retval     ERR_INVALID_ARG Argument error
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_register_callback(struct usb_h_desc *drv, enum usb_h_cb_type type, FUNC_PTR cb);
+
+/**
+ * @brief      Return current frame number
+ *
+ * @param      drv   The driver
+ *
+ * @return     current frame number
+ */
+uint16_t _usb_h_get_frame_n(struct usb_h_desc *drv);
+
+/**
+ * @brief      Return current micro frame number
+ *
+ * @param      drv   The driver
+ *
+ * @return     current micro frame number
+ */
+uint8_t _usb_h_get_microframe_n(struct usb_h_desc *drv);
+
+/**
+ * @brief Suspend the USB bus
+ *
+ * @param drv The driver
+ */
+void _usb_h_suspend(struct usb_h_desc *drv);
+
+/**
+ * @brief Resume the USB bus
+ *
+ * @param drv The driver
+ */
+void _usb_h_resume(struct usb_h_desc *drv);
+
+/* Root hub related APIs */
+
+/**
+ * \brief Reset the root hub port
+ *
+ * \param[in,out] drv  Pointer to the USB HCD driver
+ * \param[in]     port Root hub port, ignored if there is only one port
+ */
+void _usb_h_rh_reset(struct usb_h_desc *drv, uint8_t port);
+
+/**
+ * \brief Suspend the root hub port
+ *
+ * \param[in,out] drv  Pointer to the USB HCD driver
+ * \param[in]     port Root hub port, ignored if there is only one port
+ */
+void _usb_h_rh_suspend(struct usb_h_desc *drv, uint8_t port);
+
+/**
+ * \brief Resume the root hub port
+ *
+ * \param[in,out] drv  Pointer to the USB HCD driver
+ * \param[in]     port Root hub port, ignored if there is only one port
+ */
+void _usb_h_rh_resume(struct usb_h_desc *drv, uint8_t port);
+
+/**
+ * \brief Root hub or port feature status check
+ *
+ * Check USB Spec. for hub status and feature selectors.
+ *
+ * \param[in] drv  Pointer to the USB HCD driver
+ * \param[in] port Set to 0 to get hub status, otherwise to get port status
+ * \param[in] ftr  Hub feature/status selector
+ *                 (0: connection, 2: suspend, 4: reset, 9: LS, 10: HS)
+ *
+ * \return     \c true if the status bit is 1
+ */
+bool _usb_h_rh_check_status(struct usb_h_desc *drv, uint8_t port, uint8_t ftr);
+
+/* Pipe transfer functions */
+
+/**
+ * @brief      Allocate a pipe for USB host communication
+ *
+ * @param      drv           The USB HCD driver
+ * @param[in]  dev           The device address
+ * @param[in]  ep            The endpoint address
+ * @param[in]  max_pkt_size  The endpoint maximum packet size
+ * @param[in]  attr          The endpoint attribute
+ * @param[in]  interval      The endpoint interval
+ *                           (bInterval of USB Endpoint Descriptor)
+ * @param[in]  speed         The transfer speed of the endpoint
+ * @param[in]  minimum_rsc   Minimum the resource usage, \sa usb_h_rsc_strategy
+ *
+ * @return     Pointer to allocated pipe structure instance
+ * @retval     NULL allocation fail
+ */
+struct usb_h_pipe *_usb_h_pipe_allocate(struct usb_h_desc *drv, uint8_t dev, uint8_t ep, uint16_t max_pkt_size,
+                                        uint8_t attr, uint8_t interval, uint8_t speed, bool minimum_rsc);
+
+/**
+ * @brief      Free an allocated pipe
+ *
+ * @param      pipe  The pipe
+ *
+ * @return     Operation result status
+ * @retval     ERR_BUSY Pipe is busy, use \ref _usb_h_pipe_abort to abort
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_pipe_free(struct usb_h_pipe *pipe);
+
+/**
+ * @brief      Modify parameters of an allocated control pipe
+ *
+ * @param      pipe          The pipe
+ * @param[in]  dev           The device address
+ * @param[in]  ep            The endpoint address
+ * @param[in]  max_pkt_size  The maximum packet size, must be equal or
+ *                           less than allocated size
+ * @param[in]  speed         The working speed
+ *
+ * @return     Operation result status
+ * @retval     ERR_NOT_INITIALIZED Pipe is not allocated
+ * @retval     ERR_BUSY Pipe is busy transferring
+ * @retval     ERR_INVALID_ARG Argument error
+ * @retval     ERR_UNSUPPORTED_OP Pipe is not control pipe
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_pipe_set_control_param(struct usb_h_pipe *pipe, uint8_t dev, uint8_t ep, uint16_t max_pkt_size,
+                                      uint8_t speed);
+
+/**
+ * @brief      Register transfer callback on a pipe
+ *
+ * @param      pipe  The pipe
+ * @param[in]  cb    Transfer callback function
+ *
+ * @return     Operation result status
+ * @retval     ERR_INVALID_ARG Argument error
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_pipe_register_callback(struct usb_h_pipe *pipe, usb_h_pipe_cb_xfer_t cb);
+
+/**
+ * @brief      Issue a control transfer (request) on a pipe
+ *
+ * \note When there is data stage, timeout between data packets is 500ms, the
+ *       timeout between last data packet and the status packet is 50ms.
+ *
+ * @param         pipe    The pipe
+ * @param[in]     setup   Pointer to the setup packet
+ * @param[in,out] data    Pointer to the data buffer
+ * @param[in]     length  The data length
+ * @param[in]     timeout Timeout for whole request in ms
+ *
+ * @return     Operation result status
+ * @retval     ERR_NOT_INITIALIZED Pipe is not allocated
+ * @retval     ERR_BUSY Pipe is busy transferring
+ * @retval     ERR_INVALID_ARG Argument error
+ * @retval     ERR_UNSUPPORTED_OP Pipe is not control pipe
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_control_xfer(struct usb_h_pipe *pipe, uint8_t *setup, uint8_t *data, uint16_t length, int16_t timeout);
+
+/**
+ * @brief      Issue a bulk / interrupt / iso transfer on a pipe
+ *
+ * @param         pipe     The pipe
+ * @param[in,out] data     Pointer to the data buffer
+ * @param[in]     length   The data length
+ * @param[in]     auto_zlp Auto append ZLP for OUT
+ *
+ * @return     Operation result status
+ * @retval     ERR_NOT_INITIALIZED Pipe is not allocated
+ * @retval     ERR_BUSY Pipe is busy transferring
+ * @retval     ERR_INVALID_ARG Argument error
+ * @retval     ERR_UNSUPPORTED_OP Pipe is control pipe
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_bulk_int_iso_xfer(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, bool auto_zlp);
+
+/**
+ * @brief      Issue a periodic high bandwidth output on a pipe
+ *
+ * @param         pipe             The pipe
+ * @param[in,out] data             Pointer to the data buffer
+ * @param[in]     length           The data length
+ * @param[in]     trans_pkt_size   The transaction packet sizes in a micro frame,
+ *                                 0 to use endpoint max packet size
+ *
+ * @return     Operation result status
+ * @retval     ERR_NOT_INITIALIZED Pipe is not allocated
+ * @retval     ERR_BUSY Pipe is busy transferring
+ * @retval     ERR_INVALID_ARG Argument error
+ * @retval     ERR_UNSUPPORTED_OP Pipe is not high bandwidth periodic pipe, or
+ *                                DMA feature not enabled, or
+ *                                high bandwidth not enabled
+ * @retval     ERR_NONE Operation done successfully
+ */
+int32_t _usb_h_high_bw_out(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, uint16_t trans_pkt_size[3]);
+
+/**
+ * @brief      Check if pipe is busy transferring
+ *
+ * @param      pipe  The pipe
+ *
+ * @return     \c true if pipe is busy
+ */
+bool _usb_h_pipe_is_busy(struct usb_h_pipe *pipe);
+
+/**
+ * @brief      Abort pending transfer on a pipe
+ *
+ * @param      pipe  The pipe
+ */
+void _usb_h_pipe_abort(struct usb_h_pipe *pipe);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_USB_HOST_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_atomic.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_atomic.c
new file mode 100644
index 000000000..f56418ee6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_atomic.c
@@ -0,0 +1,66 @@
+/**
+ * \file
+ *
+ * \brief Critical sections related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_atomic.h"
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Disable interrupts, enter critical section
+ */
+void atomic_enter_critical(hal_atomic_t volatile *atomic)
+{
+	*atomic = __get_PRIMASK();
+	__disable_irq();
+	__DMB();
+}
+
+/**
+ * \brief Exit atomic section
+ */
+void atomic_leave_critical(hal_atomic_t volatile *atomic)
+{
+	__DMB();
+	__set_PRIMASK(*atomic);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t atomic_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_cache.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_cache.c
new file mode 100644
index 000000000..b2e75aa72
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_cache.c
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief HAL cache functionality implementation.
+ *
+ * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <compiler.h>
+#include <hpl_cmcc.h>
+
+/**
+ * \brief Initialize cache module
+ */
+int32_t cache_init(void)
+{
+	return _cmcc_init();
+}
+
+/**
+ * \brief Enable cache module
+ */
+int32_t cache_enable(const void *hw)
+{
+	return _cmcc_enable(hw);
+}
+
+/**
+ * \brief Disable cache module
+ */
+int32_t cache_disable(const void *hw)
+{
+	return _cmcc_disable(hw);
+}
+
+/**
+ * \brief Configure cache module
+ */
+int32_t cache_configure(const void *hw, struct _cache_cfg *cache)
+{
+	return _cmcc_configure(hw, cache);
+}
+
+/**
+ * \brief Invalidate entire cache entries
+ */
+int32_t cache_invalidate_all(const void *hw)
+{
+	return _cmcc_invalidate_all(hw);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_gpio.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_gpio.c
new file mode 100644
index 000000000..00dfea6f7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_gpio.c
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief Port
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_gpio.h"
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+uint32_t gpio_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_init.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_init.c
new file mode 100644
index 000000000..fb65341fb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_init.c
@@ -0,0 +1,47 @@
+/**
+ * \file
+ *
+ * \brief HAL initialization related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_init.h"
+
+/**
+ * \brief Driver version
+ */
+#define HAL_INIT_VERSION 0x00000001u
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t init_get_version(void)
+{
+	return HAL_INIT_VERSION;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_io.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_io.c
new file mode 100644
index 000000000..7e8feb045
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_io.c
@@ -0,0 +1,63 @@
+/**
+ * \file
+ *
+ * \brief I/O functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hal_io.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+uint32_t io_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/**
+ * \brief I/O write interface
+ */
+int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io_descr && buf);
+	return io_descr->write(io_descr, buf, length);
+}
+
+/**
+ * \brief I/O read interface
+ */
+int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+	ASSERT(io_descr && buf);
+	return io_descr->read(io_descr, buf, length);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_sleep.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_sleep.c
new file mode 100644
index 000000000..89472f156
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_sleep.c
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Sleep related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_sleep.h"
+#include <hpl_sleep.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Set the sleep mode of the device and put the MCU to sleep
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see the data sheet.
+ *
+ * \param[in] mode Sleep mode to use
+ *
+ * \return The status of a sleep request
+ * \retval -1 The requested sleep mode was invalid or not available
+ * \retval  0 The operation completed successfully, returned after leaving the
+ *            sleep
+ */
+int sleep(const uint8_t mode)
+{
+	if (ERR_NONE != _set_sleep_mode(mode))
+		return ERR_INVALID_ARG;
+
+	_go_to_sleep();
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version
+ */
+uint32_t sleep_get_version(void)
+{
+	return DRIVER_VERSION;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_usb_device.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_usb_device.c
new file mode 100644
index 000000000..aa80edeed
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/src/hal_usb_device.c
@@ -0,0 +1,592 @@
+/**
+ * \file
+ *
+ * \brief SAM USB device HAL
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_usb_device.h"
+#include "hal_atomic.h"
+
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB device HAL driver version. */
+#define USB_D_VERSION 0x00000001u
+
+/**
+ *  Endpoint callbacks for data transfer.
+ */
+struct usb_d_ep_callbacks {
+	/** Callback that is invoked when setup packet is received. */
+	usb_d_ep_cb_setup_t req;
+	/** Callback invoked when buffer is done, but last packet is full size
+	 *  packet without ZLP. Return \c true if new transfer has been submitted.
+	 */
+	usb_d_ep_cb_more_t more;
+	/** Callback invoked when transfer is finished/halted/aborted or error
+	 *  occurs.
+	 */
+	usb_d_ep_cb_xfer_t xfer;
+};
+
+/**
+ *  Endpoint transfer descriptor header.
+ */
+struct usb_ep_xfer_hdr {
+	/** Transfer type, reuse \ref usb_ep_type. */
+	uint8_t type;
+	/** Endpoint address. */
+	uint8_t ep;
+	/** Endpoint state. */
+	uint8_t state;
+	/** Last status code. */
+	uint8_t status;
+};
+
+/**
+ *  Transfer descriptor.
+ */
+struct usb_ep_xfer {
+	/** General transfer descriptor. */
+	struct usb_ep_xfer_hdr hdr;
+	/** Pointer to data buffer. */
+	uint8_t *buf;
+	/** Transfer size. */
+	uint32_t size;
+	/** Control request packet. */
+	uint8_t req[8];
+};
+
+/**
+ *  USB device endpoint descriptor.
+ */
+struct usb_d_ep {
+	/** On-going transfer on the endpoint. */
+	struct usb_ep_xfer xfer;
+	/** Endpoint callbacks. */
+	struct usb_d_ep_callbacks callbacks;
+};
+
+/**
+ *  USB device HAL driver descriptor.
+ */
+struct usb_d_descriptor {
+	/** USB device endpoints. */
+	struct usb_d_ep ep[CONF_USB_D_NUM_EP_SP];
+};
+
+/** The USB HAL driver descriptor instance. */
+static struct usb_d_descriptor usb_d_inst;
+
+/** \brief Find the endpoint.
+ * \param[in] ep Endpoint address.
+ * \return Index of endpoint descriptor.
+ * \retval >=0 The index.
+ * \retval <0 Not found (endpoint is not initialized).
+ */
+static int8_t _usb_d_find_ep(const uint8_t ep)
+{
+	int8_t i;
+	for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) {
+		if (usb_d_inst.ep[i].xfer.hdr.ep == ep) {
+			return i;
+		}
+		if (usb_d_inst.ep[i].xfer.hdr.type == USB_EP_XTYPE_CTRL
+		    && (ep & USB_EP_N_MASK) == usb_d_inst.ep[i].xfer.hdr.ep) {
+			return i;
+		}
+	}
+	return -1;
+}
+
+/**
+ * \brief Start transactions
+ * \param[in] ep Endpoint address.
+ * \param[in] dir Endpoint transfer direction.
+ * \param[in] buf Pointer to transfer buffer.
+ * \param[in] size Transfer size.
+ * \param[in] zlp Auto append ZLP for IN, or wait ZLP for OUT.
+ */
+static inline int32_t _usb_d_trans(const uint8_t ep, const bool dir, const uint8_t *buf, const uint32_t size,
+                                   const uint8_t zlp)
+{
+	struct usb_d_transfer trans
+	    = {(uint8_t *)buf, size, dir ? (uint8_t)(ep | USB_EP_DIR) : (uint8_t)(ep & USB_EP_N_MASK), zlp};
+
+	return _usb_d_dev_ep_trans(&trans);
+}
+
+/**
+ * \brief Dummy callback that returns false
+ * \param[in] unused0 Unused parameter.
+ * \param[in] unused1 Unused parameter.
+ * \param[in] unused2 Unused parameter.
+ * \return Always \c false.
+ */
+static bool usb_d_dummy_cb_false(uint32_t unused0, uint32_t unused1, uint32_t unused2)
+{
+	(void)unused0;
+	(void)unused1;
+	(void)unused2;
+	return false;
+}
+
+/**
+ * \brief Callback invoked when SETUP packet is ready
+ * \param[in] ep Endpoint number with transfer direction on bit 8.
+ */
+static void usb_d_cb_trans_setup(const uint8_t ep)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	uint8_t *        req      = ept->xfer.req;
+
+	uint8_t n = _usb_d_dev_ep_read_req(ep, req);
+	if (n != 8) {
+		_usb_d_dev_ep_stall(ep, USB_EP_STALL_SET);
+		_usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET);
+		return;
+	}
+
+	_usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR);
+	_usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_CLR);
+	ept->xfer.hdr.state = USB_EP_S_IDLE;
+	if (!ept->callbacks.req(ep, req)) {
+		ept->xfer.hdr.state = USB_EP_S_HALTED;
+		_usb_d_dev_ep_stall(ep, USB_EP_STALL_SET);
+		_usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET);
+	}
+}
+
+/**
+ * \brief Callback invoked when request more data
+ * \param[in] ep Endpoint number with transfer direction on bit 8.
+ * \param[in] transfered Number of bytes transfered.
+ */
+static bool usb_d_cb_trans_more(const uint8_t ep, const uint32_t transfered)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	if (ept->xfer.hdr.state == USB_EP_S_X_DATA) {
+		return ept->callbacks.more(ep, transfered);
+	}
+	return false;
+}
+
+/**
+ * \brief Handles the case that control endpoint transactions are done
+ * \param[in,out] ept Pointer to endpoint information.
+ */
+static inline void usb_d_ctrl_trans_done(struct usb_d_ep *ept)
+{
+	uint8_t state   = ept->xfer.hdr.state;
+	bool    req_dir = USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN;
+
+	if (state == USB_EP_S_X_DATA) {
+		/* Data stage -> Status stage */
+		bool err = ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DATA, ept->xfer.req);
+		if (err) {
+			ept->xfer.hdr.state  = USB_EP_S_HALTED;
+			ept->xfer.hdr.status = USB_XFER_HALT;
+			_usb_d_dev_ep_stall(req_dir ? ept->xfer.hdr.ep : (ept->xfer.hdr.ep | USB_EP_DIR), USB_EP_STALL_SET);
+		} else {
+			ept->xfer.hdr.state = USB_EP_S_X_STATUS;
+			_usb_d_trans(ept->xfer.hdr.ep, !req_dir, NULL, 0, 1);
+		}
+	} else {
+		/* Status stage done */
+		ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DONE, ept->xfer.req);
+		ept->xfer.hdr.state = USB_EP_S_X_SETUP;
+	}
+}
+
+/**
+ * Callback when USB transactions are finished.
+ */
+static void _usb_d_cb_trans_done(const uint8_t ep, const int32_t code, const uint32_t transferred)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+
+	if (code == USB_TRANS_DONE) {
+		ept->xfer.hdr.status = USB_XFER_DONE;
+		if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) {
+			usb_d_ctrl_trans_done(ept);
+			return;
+		}
+		ept->xfer.hdr.state = USB_EP_S_IDLE;
+	} else if (code == USB_TRANS_STALL) {
+		ept->xfer.hdr.status = USB_XFER_HALT;
+		if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) {
+			ept->xfer.hdr.state = USB_EP_S_X_SETUP;
+			_usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR);
+		} else {
+			ept->xfer.hdr.state = USB_EP_S_HALTED;
+		}
+	} else if (code == USB_TRANS_ABORT) {
+		ept->xfer.hdr.status = USB_XFER_ABORT;
+		if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) {
+			ept->xfer.hdr.state = USB_EP_S_X_SETUP;
+			return;
+		}
+		ept->xfer.hdr.state = USB_EP_S_IDLE;
+	} else if (code == USB_TRANS_RESET) {
+		ept->xfer.hdr.state  = USB_EP_S_DISABLED;
+		ept->xfer.hdr.status = USB_XFER_RESET;
+	} else {
+		ept->xfer.hdr.state  = USB_EP_S_ERROR;
+		ept->xfer.hdr.status = USB_XFER_ERROR;
+	}
+
+	ept->callbacks.xfer(ep, (enum usb_xfer_code)ept->xfer.hdr.status, (void *)transferred);
+}
+
+int32_t usb_d_init(void)
+{
+	int32_t rc = _usb_d_dev_init();
+	uint8_t i;
+	if (rc < 0) {
+		return rc;
+	}
+	memset(usb_d_inst.ep, 0x00, sizeof(struct usb_d_ep) * CONF_USB_D_NUM_EP_SP);
+	for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) {
+		usb_d_inst.ep[i].xfer.hdr.ep    = 0xFF;
+		usb_d_inst.ep[i].callbacks.req  = (usb_d_ep_cb_setup_t)usb_d_dummy_cb_false;
+		usb_d_inst.ep[i].callbacks.more = (usb_d_ep_cb_more_t)usb_d_dummy_cb_false;
+		usb_d_inst.ep[i].callbacks.xfer = (usb_d_ep_cb_xfer_t)usb_d_dummy_cb_false;
+	}
+	/* Handles device driver endpoint callbacks to build transfer. */
+	_usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_SETUP, (FUNC_PTR)usb_d_cb_trans_setup);
+	_usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_MORE, (FUNC_PTR)usb_d_cb_trans_more);
+	_usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_DONE, (FUNC_PTR)_usb_d_cb_trans_done);
+	return ERR_NONE;
+}
+
+void usb_d_deinit(void)
+{
+	_usb_d_dev_deinit();
+}
+
+void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func)
+{
+	/* Directly uses device driver callback. */
+	_usb_d_dev_register_callback(type, func);
+}
+
+int32_t usb_d_enable(void)
+{
+	return _usb_d_dev_enable();
+}
+
+void usb_d_disable(void)
+{
+	_usb_d_dev_disable();
+}
+
+void usb_d_attach(void)
+{
+	_usb_d_dev_attach();
+}
+
+void usb_d_detach(void)
+{
+	_usb_d_dev_detach();
+}
+
+enum usb_speed usb_d_get_speed(void)
+{
+	return _usb_d_dev_get_speed();
+}
+
+uint16_t usb_d_get_frame_num(void)
+{
+	return _usb_d_dev_get_frame_n();
+}
+
+uint8_t usb_d_get_uframe_num(void)
+{
+	return _usb_d_dev_get_uframe_n();
+}
+
+void usb_d_set_address(const uint8_t addr)
+{
+	_usb_d_dev_set_address(addr);
+}
+
+void usb_d_send_remotewakeup(void)
+{
+	_usb_d_dev_send_remotewakeup();
+}
+
+int32_t usb_d_ep0_init(const uint8_t max_pkt_size)
+{
+	return usb_d_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_size);
+}
+
+int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size)
+{
+	int32_t          rc;
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	if (ep_index >= 0) {
+		return -USB_ERR_REDO;
+	} else {
+		ep_index = _usb_d_find_ep(0xFF);
+		if (ep_index < 0) {
+			return -USB_ERR_ALLOC_FAIL;
+		}
+		ept = &usb_d_inst.ep[ep_index];
+	}
+	rc = _usb_d_dev_ep_init(ep, attr, max_pkt_size);
+	if (rc < 0) {
+		return rc;
+	}
+	ept->xfer.hdr.ep   = ep;
+	ept->xfer.hdr.type = attr & USB_EP_XTYPE_MASK;
+	return ERR_NONE;
+}
+
+void usb_d_ep_deinit(const uint8_t ep)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	if (ep_index < 0) {
+		return;
+	}
+	_usb_d_dev_ep_deinit(ep);
+	ept->xfer.hdr.ep = 0xFF;
+}
+
+int32_t usb_d_ep_enable(const uint8_t ep)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	int32_t          rc;
+	if (ep_index < 0) {
+		return -USB_ERR_PARAM;
+	}
+	ept->xfer.hdr.state = (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) ? USB_EP_S_X_SETUP : USB_EP_S_IDLE;
+	rc                  = _usb_d_dev_ep_enable(ep);
+	if (rc < 0) {
+		ept->xfer.hdr.state = USB_EP_S_DISABLED;
+	}
+	return rc;
+}
+
+void usb_d_ep_disable(const uint8_t ep)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	if (ep_index < 0) {
+		return;
+	}
+	_usb_d_dev_ep_disable(ep);
+	ept->xfer.hdr.state = USB_EP_S_DISABLED;
+}
+
+uint8_t *usb_d_ep_get_req(const uint8_t ep)
+{
+	int8_t ep_index = _usb_d_find_ep(ep);
+	if (ep_index < 0) {
+		return NULL;
+	}
+	return usb_d_inst.ep[ep_index].xfer.req;
+}
+
+int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer)
+{
+	int8_t                ep_index = _usb_d_find_ep(xfer->ep);
+	struct usb_d_ep *     ept      = &usb_d_inst.ep[ep_index];
+	bool                  dir = USB_EP_GET_DIR(xfer->ep), zlp = xfer->zlp;
+	uint32_t              len = xfer->size;
+	int32_t               rc;
+	volatile uint8_t      state;
+	volatile hal_atomic_t flags;
+
+	if (ep_index < 0) {
+		return -USB_ERR_PARAM;
+	}
+
+	atomic_enter_critical(&flags);
+	state = ept->xfer.hdr.state;
+	if (state == USB_EP_S_IDLE) {
+		ept->xfer.hdr.state = USB_EP_S_X_DATA;
+		atomic_leave_critical(&flags);
+	} else {
+		atomic_leave_critical(&flags);
+		switch (state) {
+		case USB_EP_S_HALTED:
+			return USB_HALTED;
+		case USB_EP_S_ERROR:
+			return -USB_ERROR;
+		case USB_EP_S_DISABLED:
+			return -USB_ERR_FUNC;
+		default: /* USB_EP_S_X_xxxx  */
+			return USB_BUSY;
+		}
+	}
+
+	if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) {
+		uint16_t req_len = USB_GET_wLength(ept->xfer.req);
+		/* SETUP without data: ZLP IN as status. */
+		if (req_len == 0) {
+			dir                 = true;
+			len                 = 0;
+			zlp                 = true;
+			ept->xfer.hdr.state = USB_EP_S_X_STATUS;
+		} else {
+			dir = (USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN);
+			/* Data length not exceed requested. */
+			if (len > req_len) {
+				len = req_len;
+			}
+			if (dir) {
+				/* Setup -> In */
+				zlp = (req_len > len);
+			} else {
+				zlp = false;
+			}
+		}
+	}
+
+	rc = _usb_d_trans(xfer->ep, dir, xfer->buf, len, zlp);
+	return rc;
+}
+
+void usb_d_ep_abort(const uint8_t ep)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	if (ep_index < 0) {
+		return;
+	}
+	_usb_d_dev_ep_abort(ep);
+	ept->xfer.hdr.state  = USB_EP_S_IDLE;
+	ept->xfer.hdr.status = USB_XFER_ABORT;
+}
+
+int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat)
+{
+	int8_t                    ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *         ept      = &usb_d_inst.ep[ep_index];
+	struct usb_d_trans_status tmp;
+	uint8_t                   state = ept->xfer.hdr.state;
+	if (ep_index < 0) {
+		return -USB_ERR_PARAM;
+	}
+	if (stat) {
+		/* Check transaction status if transferring data. */
+		_usb_d_dev_ep_get_status(ep, &tmp);
+		stat->ep    = ep;
+		stat->state = state;
+		stat->code  = ept->xfer.hdr.status;
+		stat->count = tmp.count;
+		stat->size  = tmp.size;
+	}
+	switch (state) {
+	case USB_EP_S_IDLE:
+		return USB_OK;
+	case USB_EP_S_HALTED:
+		return USB_HALTED;
+	case USB_EP_S_ERROR:
+		return -USB_ERROR;
+	case USB_EP_S_DISABLED:
+		return -USB_ERR_FUNC;
+	default:
+		/* Busy */
+		return USB_BUSY;
+	}
+}
+
+static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	int32_t          rc;
+	if (ep_index < 0) {
+		return -USB_ERR_PARAM;
+	}
+	if (_usb_d_dev_ep_stall(ep, USB_EP_STALL_GET)) {
+		rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR);
+		if (rc < 0) {
+			return rc;
+		}
+		ept->xfer.hdr.state  = USB_EP_S_IDLE;
+		ept->xfer.hdr.status = USB_XFER_UNHALT;
+		ept->callbacks.xfer(ep, USB_XFER_UNHALT, NULL);
+	}
+	return ERR_NONE;
+}
+
+int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl)
+{
+	if (ctrl == USB_EP_HALT_CLR) {
+		return _usb_d_ep_halt_clr(ep);
+	} else if (ctrl == USB_EP_HALT_SET) {
+		return _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET);
+	} else {
+		return _usb_d_dev_ep_stall(ep, USB_EP_STALL_GET);
+	}
+}
+
+void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func)
+{
+	int8_t           ep_index = _usb_d_find_ep(ep);
+	struct usb_d_ep *ept      = &usb_d_inst.ep[ep_index];
+	FUNC_PTR         f        = func ? (FUNC_PTR)func : (FUNC_PTR)usb_d_dummy_cb_false;
+	if (ep_index < 0) {
+		return;
+	}
+	switch (type) {
+	case USB_D_EP_CB_SETUP:
+		ept->callbacks.req = (usb_d_ep_cb_setup_t)f;
+		break;
+	case USB_D_EP_CB_MORE:
+		ept->callbacks.more = (usb_d_ep_cb_more_t)f;
+		break;
+	case USB_D_EP_CB_XFER:
+		ept->callbacks.xfer = (usb_d_ep_cb_xfer_t)f;
+		break;
+	default:
+		break;
+	}
+}
+
+uint32_t usb_d_get_version(void)
+{
+	return USB_D_VERSION;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/compiler.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/compiler.h
new file mode 100644
index 000000000..f35db3df8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/compiler.h
@@ -0,0 +1,64 @@
+/**
+ * \file
+ *
+ * \brief Header
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+/******************************************************************************
+ * compiler.h
+ *
+ * Created: 05.05.2014
+ * Author: N. Fomin
+ ******************************************************************************/
+
+#ifndef _COMPILER_H
+#define _COMPILER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifndef _UNIT_TEST_
+#include "parts.h"
+#endif
+#include "err_codes.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _COMPILER_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/err_codes.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/err_codes.h
new file mode 100644
index 000000000..a7aff0189
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/err_codes.h
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief Error code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ERROR_CODES_H_INCLUDED
+#define ERROR_CODES_H_INCLUDED
+
+#define ERR_NONE 0
+#define ERR_INVALID_DATA -1
+#define ERR_NO_CHANGE -2
+#define ERR_ABORTED -3
+#define ERR_BUSY -4
+#define ERR_SUSPEND -5
+#define ERR_IO -6
+#define ERR_REQ_FLUSHED -7
+#define ERR_TIMEOUT -8
+#define ERR_BAD_DATA -9
+#define ERR_NOT_FOUND -10
+#define ERR_UNSUPPORTED_DEV -11
+#define ERR_NO_MEMORY -12
+#define ERR_INVALID_ARG -13
+#define ERR_BAD_ADDRESS -14
+#define ERR_BAD_FORMAT -15
+#define ERR_BAD_FRQ -16
+#define ERR_DENIED -17
+#define ERR_ALREADY_INITIALIZED -18
+#define ERR_OVERFLOW -19
+#define ERR_NOT_INITIALIZED -20
+#define ERR_SAMPLERATE_UNAVAILABLE -21
+#define ERR_RESOLUTION_UNAVAILABLE -22
+#define ERR_BAUDRATE_UNAVAILABLE -23
+#define ERR_PACKET_COLLISION -24
+#define ERR_PROTOCOL -25
+#define ERR_PIN_MUX_INVALID -26
+#define ERR_UNSUPPORTED_OP -27
+#define ERR_NO_RESOURCE -28
+#define ERR_NOT_READY -29
+#define ERR_FAILURE -30
+#define ERR_WRONG_LENGTH -31
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/events.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/events.h
new file mode 100644
index 000000000..3ee891a73
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/events.h
@@ -0,0 +1,54 @@
+/**
+ * \file
+ *
+ * \brief Events declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _EVENTS_H_INCLUDED
+#define _EVENTS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+/**
+ * \brief List of events. Must start with 0, be unique and follow numerical order.
+ */
+#define EVENT_IS_READY_TO_SLEEP_ID 0
+#define EVENT_PREPARE_TO_SLEEP_ID 1
+#define EVENT_WOKEN_UP_ID 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _EVENTS_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/parts.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/parts.h
new file mode 100644
index 000000000..763d76cc7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/parts.h
@@ -0,0 +1,41 @@
+/**
+ * \file
+ *
+ * \brief Atmel part identification macros
+ *
+ * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ATMEL_PARTS_H
+#define ATMEL_PARTS_H
+
+#include "same53.h"
+
+#include "hri_e53.h"
+
+#endif /* ATMEL_PARTS_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils.h
new file mode 100644
index 000000000..821e26dbc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils.h
@@ -0,0 +1,370 @@
+/**
+ * \file
+ *
+ * \brief Different macros.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef UTILS_H_INCLUDED
+#define UTILS_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_macro
+ *
+ * @{
+ */
+
+/**
+ * \brief Retrieve pointer to parent structure
+ */
+#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name)))
+
+/**
+ * \brief Retrieve array size
+ */
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param[in] arg  The pragma directive as it would appear after \e \#pragma
+ *             (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if defined __GNUC__
+#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#elif defined __ICCARM__
+#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
+#elif defined __CC_ARM
+#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#endif
+
+/**
+ * \brief Flash located data macros
+ */
+#if defined __GNUC__
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#elif defined __ICCARM__
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#elif defined __CC_ARM
+#define PROGMEM_DECLARE(type, name) const type name
+#define PROGMEM_T const
+#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x))
+#define PROGMEM_PTR_T const *
+#define PROGMEM_STRING_T const uint8_t *
+#endif
+
+/**
+ * \brief Optimization
+ */
+#if defined __GNUC__
+#define OPTIMIZE_HIGH __attribute__((optimize(s)))
+#elif defined __CC_ARM
+#define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined __ICCARM__
+#define OPTIMIZE_HIGH _Pragma("optimize=high")
+#endif
+
+/**
+ * \brief RAM located function attribute
+ */
+#if defined(__CC_ARM) /* Keil ?Vision 4 */
+#define RAMFUNC __attribute__((section(".ramfunc")))
+#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
+#define RAMFUNC __ramfunc
+#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
+#define RAMFUNC __attribute__((section(".ramfunc")))
+#endif
+
+/**
+ * \brief No-init section.
+ * Place a data object or a function in a no-init section.
+ */
+#if defined(__CC_ARM)
+#define NO_INIT(a) __attribute__((zero_init))
+#elif defined(__ICCARM__)
+#define NO_INIT(a) __no_init
+#elif defined(__GNUC__)
+#define NO_INIT(a) __attribute__((section(".no_init")))
+#endif
+
+/**
+ * \brief Set user-defined section.
+ * Place a data object or a function in a user-defined section.
+ */
+#if defined(__CC_ARM)
+#define COMPILER_SECTION(a) __attribute__((__section__(a)))
+#elif defined(__ICCARM__)
+#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a)
+#elif defined(__GNUC__)
+#define COMPILER_SECTION(a) __attribute__((__section__(a)))
+#endif
+
+/**
+ * \brief Define WEAK attribute.
+ */
+#if defined(__CC_ARM) /* Keil ?Vision 4 */
+#define WEAK __attribute__((weak))
+#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */
+#define WEAK __weak
+#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */
+#define WEAK __attribute__((weak))
+#endif
+
+/**
+ * \brief Pointer to function
+ */
+typedef void (*FUNC_PTR)(void);
+
+#define LE_BYTE0(a) ((uint8_t)(a))
+#define LE_BYTE1(a) ((uint8_t)((a) >> 8))
+#define LE_BYTE2(a) ((uint8_t)((a) >> 16))
+#define LE_BYTE3(a) ((uint8_t)((a) >> 24))
+
+#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8))
+#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24))
+
+/** \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ *
+ * @{ */
+
+/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define clz(u) __builtin_clz(u)
+#else
+#define clz(u)                                                                                                                                                                                                                                                                                                                                                                                     \
+	(                                                                                                                                                                                                                                                                                                                                                                                              \
+	    ((u) == 0)                                                                                                                                                                                                                                                                                                                                                                                 \
+	        ? 32                                                                                                                                                                                                                                                                                                                                                                                   \
+	        : ((u) & (1ul << 31))                                                                                                                                                                                                                                                                                                                                                                  \
+	              ? 0                                                                                                                                                                                                                                                                                                                                                                              \
+	              : ((u) & (1ul << 30))                                                                                                                                                                                                                                                                                                                                                            \
+	                    ? 1                                                                                                                                                                                                                                                                                                                                                                        \
+	                    : ((u) & (1ul << 29))                                                                                                                                                                                                                                                                                                                                                      \
+	                          ? 2                                                                                                                                                                                                                                                                                                                                                                  \
+	                          : ((u) & (1ul << 28))                                                                                                                                                                                                                                                                                                                                                \
+	                                ? 3                                                                                                                                                                                                                                                                                                                                                            \
+	                                : ((u) & (1ul << 27))                                                                                                                                                                                                                                                                                                                                          \
+	                                      ? 4                                                                                                                                                                                                                                                                                                                                                      \
+	                                      : ((u) & (1ul << 26))                                                                                                                                                                                                                                                                                                                                    \
+	                                            ? 5                                                                                                                                                                                                                                                                                                                                                \
+	                                            : ((u) & (1ul << 25))                                                                                                                                                                                                                                                                                                                              \
+	                                                  ? 6                                                                                                                                                                                                                                                                                                                                          \
+	                                                  : ((u) & (1ul << 24))                                                                                                                                                                                                                                                                                                                        \
+	                                                        ? 7                                                                                                                                                                                                                                                                                                                                    \
+	                                                        : ((u) & (1ul << 23))                                                                                                                                                                                                                                                                                                                  \
+	                                                              ? 8                                                                                                                                                                                                                                                                                                                              \
+	                                                              : ((u) & (1ul << 22))                                                                                                                                                                                                                                                                                                            \
+	                                                                    ? 9                                                                                                                                                                                                                                                                                                                        \
+	                                                                    : ((u) & (1ul << 21))                                                                                                                                                                                                                                                                                                      \
+	                                                                          ? 10                                                                                                                                                                                                                                                                                                                 \
+	                                                                          : ((u) & (1ul << 20))                                                                                                                                                                                                                                                                                                \
+	                                                                                ? 11                                                                                                                                                                                                                                                                                                           \
+	                                                                                : ((u) & (1ul << 19))                                                                                                                                                                                                                                                                                          \
+	                                                                                      ? 12                                                                                                                                                                                                                                                                                                     \
+	                                                                                      : ((u) & (1ul << 18))                                                                                                                                                                                                                                                                                    \
+	                                                                                            ? 13                                                                                                                                                                                                                                                                                               \
+	                                                                                            : ((u) & (1ul << 17)) ? 14                                                                                                                                                                                                                                                                         \
+	                                                                                                                  : ((u) & (1ul << 16)) ? 15                                                                                                                                                                                                                                                   \
+	                                                                                                                                        : ((u) & (1ul << 15)) ? 16                                                                                                                                                                                                                             \
+	                                                                                                                                                              : ((u) & (1ul << 14)) ? 17                                                                                                                                                                                                       \
+	                                                                                                                                                                                    : ((u) & (1ul << 13)) ? 18                                                                                                                                                                                 \
+	                                                                                                                                                                                                          : ((u) & (1ul << 12)) ? 19                                                                                                                                                           \
+	                                                                                                                                                                                                                                : ((u)                                                                                                                                                         \
+	                                                                                                                                                                                                                                   & (1ul                                                                                                                                                      \
+	                                                                                                                                                                                                                                      << 11))                                                                                                                                                  \
+	                                                                                                                                                                                                                                      ? 20                                                                                                                                                     \
+	                                                                                                                                                                                                                                      : ((u)                                                                                                                                                   \
+	                                                                                                                                                                                                                                         & (1ul                                                                                                                                                \
+	                                                                                                                                                                                                                                            << 10))                                                                                                                                            \
+	                                                                                                                                                                                                                                            ? 21                                                                                                                                               \
+	                                                                                                                                                                                                                                            : ((u)                                                                                                                                             \
+	                                                                                                                                                                                                                                               & (1ul                                                                                                                                          \
+	                                                                                                                                                                                                                                                  << 9))                                                                                                                                       \
+	                                                                                                                                                                                                                                                  ? 22                                                                                                                                         \
+	                                                                                                                                                                                                                                                  : ((u)                                                                                                                                       \
+	                                                                                                                                                                                                                                                     & (1ul                                                                                                                                    \
+	                                                                                                                                                                                                                                                        << 8))                                                                                                                                 \
+	                                                                                                                                                                                                                                                        ? 23                                                                                                                                   \
+	                                                                                                                                                                                                                                                        : ((u) & (1ul << 7)) ? 24                                                                                                              \
+	                                                                                                                                                                                                                                                                             : ((u) & (1ul << 6)) ? 25                                                                                         \
+	                                                                                                                                                                                                                                                                                                  : ((u)                                                                                       \
+	                                                                                                                                                                                                                                                                                                     & (1ul                                                                                    \
+	                                                                                                                                                                                                                                                                                                        << 5))                                                                                 \
+	                                                                                                                                                                                                                                                                                                        ? 26                                                                                   \
+	                                                                                                                                                                                                                                                                                                        : ((u) & (1ul << 4)) ? 27                                                              \
+	                                                                                                                                                                                                                                                                                                                             : ((u) & (1ul << 3)) ? 28                                         \
+	                                                                                                                                                                                                                                                                                                                                                  : ((u) & (1ul << 2)) ? 29                    \
+	                                                                                                                                                                                                                                                                                                                                                                       : (                     \
+	                                                                                                                                                                                                                                                                                                                                                                             (u) & (1ul << 1)) \
+	                                                                                                                                                                                                                                                                                                                                                                             ? 30              \
+	                                                                                                                                                                                                                                                                                                                                                                             : 31)
+#endif
+
+/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param[in] u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define ctz(u) __builtin_ctz(u)
+#else
+#define ctz(u)                                                                                                                                                                                                                                                                                                   \
+	(                                                                                                                                                                                                                                                                                                            \
+	    (u) & (1ul << 0)                                                                                                                                                                                                                                                                                         \
+	        ? 0                                                                                                                                                                                                                                                                                                  \
+	        : (u) & (1ul << 1)                                                                                                                                                                                                                                                                                   \
+	              ? 1                                                                                                                                                                                                                                                                                            \
+	              : (u) & (1ul << 2)                                                                                                                                                                                                                                                                             \
+	                    ? 2                                                                                                                                                                                                                                                                                      \
+	                    : (u) & (1ul << 3)                                                                                                                                                                                                                                                                       \
+	                          ? 3                                                                                                                                                                                                                                                                                \
+	                          : (u) & (1ul << 4)                                                                                                                                                                                                                                                                 \
+	                                ? 4                                                                                                                                                                                                                                                                          \
+	                                : (u) & (1ul << 5)                                                                                                                                                                                                                                                           \
+	                                      ? 5                                                                                                                                                                                                                                                                    \
+	                                      : (u) & (1ul << 6)                                                                                                                                                                                                                                                     \
+	                                            ? 6                                                                                                                                                                                                                                                              \
+	                                            : (u) & (1ul << 7)                                                                                                                                                                                                                                               \
+	                                                  ? 7                                                                                                                                                                                                                                                        \
+	                                                  : (u) & (1ul << 8)                                                                                                                                                                                                                                         \
+	                                                        ? 8                                                                                                                                                                                                                                                  \
+	                                                        : (u) & (1ul << 9)                                                                                                                                                                                                                                   \
+	                                                              ? 9                                                                                                                                                                                                                                            \
+	                                                              : (u) & (1ul << 10)                                                                                                                                                                                                                            \
+	                                                                    ? 10                                                                                                                                                                                                                                     \
+	                                                                    : (u) & (1ul << 11)                                                                                                                                                                                                                      \
+	                                                                          ? 11                                                                                                                                                                                                                               \
+	                                                                          : (u) & (1ul << 12)                                                                                                                                                                                                                \
+	                                                                                ? 12                                                                                                                                                                                                                         \
+	                                                                                : (u) & (1ul << 13)                                                                                                                                                                                                          \
+	                                                                                      ? 13                                                                                                                                                                                                                   \
+	                                                                                      : (u) & (1ul << 14)                                                                                                                                                                                                    \
+	                                                                                            ? 14                                                                                                                                                                                                             \
+	                                                                                            : (u) & (1ul << 15)                                                                                                                                                                                              \
+	                                                                                                  ? 15                                                                                                                                                                                                       \
+	                                                                                                  : (u) & (1ul << 16)                                                                                                                                                                                        \
+	                                                                                                        ? 16                                                                                                                                                                                                 \
+	                                                                                                        : (u) & (1ul << 17)                                                                                                                                                                                  \
+	                                                                                                              ? 17                                                                                                                                                                                           \
+	                                                                                                              : (u) & (1ul << 18)                                                                                                                                                                            \
+	                                                                                                                    ? 18                                                                                                                                                                                     \
+	                                                                                                                    : (u) & (1ul << 19) ? 19                                                                                                                                                                 \
+	                                                                                                                                        : (u) & (1ul << 20) ? 20                                                                                                                                             \
+	                                                                                                                                                            : (u) & (1ul << 21) ? 21                                                                                                                         \
+	                                                                                                                                                                                : (u) & (1ul << 22) ? 22                                                                                                     \
+	                                                                                                                                                                                                    : (u) & (1ul << 23) ? 23                                                                                 \
+	                                                                                                                                                                                                                        : (u) & (1ul << 24) ? 24                                                             \
+	                                                                                                                                                                                                                                            : (u) & (1ul << 25) ? 25                                         \
+	                                                                                                                                                                                                                                                                : (u) & (1ul << 26) ? 26                     \
+	                                                                                                                                                                                                                                                                                    : (u) & (1ul << 27) ? 27 \
+	                                                                                                                                                                                                                                                                                                        : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32)
+#endif
+/** @} */
+
+/**
+ * \brief Counts the number of bits in a mask (no more than 32 bits)
+ * \param[in] mask Mask of which to count the bits.
+ */
+#define size_of_mask(mask) (32 - clz(mask) - ctz(mask))
+
+/**
+ * \brief Retrieve the start position of bits mask (no more than 32 bits)
+ * \param[in] mask Mask of which to retrieve the start position.
+ */
+#define pos_of_mask(mask) ctz(mask)
+
+/**
+ * \brief Return division result of a/b and round up the result to the closest
+ *        number divisible by "b"
+ */
+#define round_up(a, b) (((a)-1) / (b) + 1)
+
+/**
+ * \brief Get the minimum of x and y
+ */
+#ifndef min
+#define min(x, y) ((x) > (y) ? (y) : (x))
+#endif
+/**
+ * \brief Get the maximum of x and y
+ */
+#ifndef max
+#define max(x, y) ((x) > (y) ? (x) : (y))
+#endif
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* UTILS_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_assert.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_assert.h
new file mode 100644
index 000000000..c2328d6c3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_assert.h
@@ -0,0 +1,93 @@
+/**
+ * \file
+ *
+ * \brief Asserts related functionality.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _ASSERT_H_INCLUDED
+#define _ASSERT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+#ifndef USE_SIMPLE_ASSERT
+//# define USE_SIMPLE_ASSERT
+#endif
+
+/**
+ * \brief Assert macro
+ *
+ * This macro is used to throw asserts. It can be mapped to different function
+ * based on debug level.
+ *
+ * \param[in] condition A condition to be checked;
+ *                      assert is thrown if the given condition is false
+ */
+#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__)
+
+#ifdef DEBUG
+
+#ifdef USE_SIMPLE_ASSERT
+#define ASSERT_IMPL(condition, file, line)                                                                             \
+	if (!(condition))                                                                                                  \
+		__asm("BKPT #0");
+#else
+#define ASSERT_IMPL(condition, file, line) assert((condition), file, line)
+#endif
+
+#else /* DEBUG */
+
+#ifdef USE_SIMPLE_ASSERT
+#define ASSERT_IMPL(condition, file, line) ((void)0)
+#else
+#define ASSERT_IMPL(condition, file, line) ((void)0)
+#endif
+
+#endif /* DEBUG */
+
+/**
+ * \brief Assert function
+ *
+ * This function is used to throw asserts.
+ *
+ * \param[in] condition A condition to be checked; assert is thrown if the given
+ *                      condition is false
+ * \param[in] file File name
+ * \param[in] line Line number
+ */
+void assert(const bool condition, const char *const file, const int line);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _ASSERT_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_event.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_event.h
new file mode 100644
index 000000000..13067c4fe
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_event.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Events declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_EVENT_H_INCLUDED
+#define _UTILS_EVENT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <utils.h>
+#include <utils_list.h>
+#include <events.h>
+
+/**
+ * \brief The maximum amount of events
+ */
+#define EVENT_MAX_AMOUNT 8
+
+/**
+ * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the
+ *        closest number divisible by 8.
+ */
+#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8))
+
+/**
+ * \brief The type of event ID. IDs should start with 0 and be in numerical order.
+ */
+typedef uint8_t event_id_t;
+
+/**
+ * \brief The type of returned parameter. This type is big enough to contain
+ *        pointer to data on any platform.
+ */
+typedef uintptr_t event_data_t;
+
+/**
+ * \brief The type of returned parameter. This type is big enough to contain
+ *        pointer to data on any platform.
+ */
+typedef void (*event_cb_t)(event_id_t id, event_data_t data);
+
+/**
+ * \brief Event structure
+ */
+struct event {
+	struct list_element elem;                  /*! The pointer to next event */
+	uint8_t             mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */
+	event_cb_t          cb;                    /*! Callback to be called when an event occurs */
+};
+
+/**
+ * \brief Subscribe to event
+ *
+ * \param[in] event The pointer to event structure
+ * \param[in] id The event ID to subscribe to
+ * \param[in] cb The callback function to call when the given event occurs
+ *
+ * \return The status of subscription
+ */
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb);
+
+/**
+ * \brief Remove event from subscription
+ *
+ * \param[in] event The pointer to event structure
+ * \param[in] id The event ID to remove subscription from
+ *
+ * \return The status of subscription removing
+ */
+int32_t event_unsubscribe(struct event *const event, const event_id_t id);
+
+/**
+ * \brief Post event
+ *
+ * \param[in] id The event ID to post
+ * \param[in] data The event data to be passed to event subscribers
+ */
+void event_post(const event_id_t id, const event_data_t data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UTILS_EVENT_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_increment_macro.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_increment_macro.h
new file mode 100644
index 000000000..464c6cbb7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_increment_macro.h
@@ -0,0 +1,308 @@
+/**
+ * \file
+ *
+ * \brief Increment macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_INCREMENT_MACRO_H
+#define _UTILS_INCREMENT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Compile time increment, result value is entire integer literal
+ *
+ * \param[in] val - value to be incremented (254 max)
+ */
+#define INC_VALUE(val) SP_INC_##val
+
+// Preprocessor increment implementation
+#define SP_INC_0 1
+#define SP_INC_1 2
+#define SP_INC_2 3
+#define SP_INC_3 4
+#define SP_INC_4 5
+#define SP_INC_5 6
+#define SP_INC_6 7
+#define SP_INC_7 8
+#define SP_INC_8 9
+#define SP_INC_9 10
+#define SP_INC_10 11
+#define SP_INC_11 12
+#define SP_INC_12 13
+#define SP_INC_13 14
+#define SP_INC_14 15
+#define SP_INC_15 16
+#define SP_INC_16 17
+#define SP_INC_17 18
+#define SP_INC_18 19
+#define SP_INC_19 20
+#define SP_INC_20 21
+#define SP_INC_21 22
+#define SP_INC_22 23
+#define SP_INC_23 24
+#define SP_INC_24 25
+#define SP_INC_25 26
+#define SP_INC_26 27
+#define SP_INC_27 28
+#define SP_INC_28 29
+#define SP_INC_29 30
+#define SP_INC_30 31
+#define SP_INC_31 32
+#define SP_INC_32 33
+#define SP_INC_33 34
+#define SP_INC_34 35
+#define SP_INC_35 36
+#define SP_INC_36 37
+#define SP_INC_37 38
+#define SP_INC_38 39
+#define SP_INC_39 40
+#define SP_INC_40 41
+#define SP_INC_41 42
+#define SP_INC_42 43
+#define SP_INC_43 44
+#define SP_INC_44 45
+#define SP_INC_45 46
+#define SP_INC_46 47
+#define SP_INC_47 48
+#define SP_INC_48 49
+#define SP_INC_49 50
+#define SP_INC_50 51
+#define SP_INC_51 52
+#define SP_INC_52 53
+#define SP_INC_53 54
+#define SP_INC_54 55
+#define SP_INC_55 56
+#define SP_INC_56 57
+#define SP_INC_57 58
+#define SP_INC_58 59
+#define SP_INC_59 60
+#define SP_INC_60 61
+#define SP_INC_61 62
+#define SP_INC_62 63
+#define SP_INC_63 64
+#define SP_INC_64 65
+#define SP_INC_65 66
+#define SP_INC_66 67
+#define SP_INC_67 68
+#define SP_INC_68 69
+#define SP_INC_69 70
+#define SP_INC_70 71
+#define SP_INC_71 72
+#define SP_INC_72 73
+#define SP_INC_73 74
+#define SP_INC_74 75
+#define SP_INC_75 76
+#define SP_INC_76 77
+#define SP_INC_77 78
+#define SP_INC_78 79
+#define SP_INC_79 80
+#define SP_INC_80 81
+#define SP_INC_81 82
+#define SP_INC_82 83
+#define SP_INC_83 84
+#define SP_INC_84 85
+#define SP_INC_85 86
+#define SP_INC_86 87
+#define SP_INC_87 88
+#define SP_INC_88 89
+#define SP_INC_89 90
+#define SP_INC_90 91
+#define SP_INC_91 92
+#define SP_INC_92 93
+#define SP_INC_93 94
+#define SP_INC_94 95
+#define SP_INC_95 96
+#define SP_INC_96 97
+#define SP_INC_97 98
+#define SP_INC_98 99
+#define SP_INC_99 100
+#define SP_INC_100 101
+#define SP_INC_101 102
+#define SP_INC_102 103
+#define SP_INC_103 104
+#define SP_INC_104 105
+#define SP_INC_105 106
+#define SP_INC_106 107
+#define SP_INC_107 108
+#define SP_INC_108 109
+#define SP_INC_109 110
+#define SP_INC_110 111
+#define SP_INC_111 112
+#define SP_INC_112 113
+#define SP_INC_113 114
+#define SP_INC_114 115
+#define SP_INC_115 116
+#define SP_INC_116 117
+#define SP_INC_117 118
+#define SP_INC_118 119
+#define SP_INC_119 120
+#define SP_INC_120 121
+#define SP_INC_121 122
+#define SP_INC_122 123
+#define SP_INC_123 124
+#define SP_INC_124 125
+#define SP_INC_125 126
+#define SP_INC_126 127
+#define SP_INC_127 128
+#define SP_INC_128 129
+#define SP_INC_129 130
+#define SP_INC_130 131
+#define SP_INC_131 132
+#define SP_INC_132 133
+#define SP_INC_133 134
+#define SP_INC_134 135
+#define SP_INC_135 136
+#define SP_INC_136 137
+#define SP_INC_137 138
+#define SP_INC_138 139
+#define SP_INC_139 140
+#define SP_INC_140 141
+#define SP_INC_141 142
+#define SP_INC_142 143
+#define SP_INC_143 144
+#define SP_INC_144 145
+#define SP_INC_145 146
+#define SP_INC_146 147
+#define SP_INC_147 148
+#define SP_INC_148 149
+#define SP_INC_149 150
+#define SP_INC_150 151
+#define SP_INC_151 152
+#define SP_INC_152 153
+#define SP_INC_153 154
+#define SP_INC_154 155
+#define SP_INC_155 156
+#define SP_INC_156 157
+#define SP_INC_157 158
+#define SP_INC_158 159
+#define SP_INC_159 160
+#define SP_INC_160 161
+#define SP_INC_161 162
+#define SP_INC_162 163
+#define SP_INC_163 164
+#define SP_INC_164 165
+#define SP_INC_165 166
+#define SP_INC_166 167
+#define SP_INC_167 168
+#define SP_INC_168 169
+#define SP_INC_169 170
+#define SP_INC_170 171
+#define SP_INC_171 172
+#define SP_INC_172 173
+#define SP_INC_173 174
+#define SP_INC_174 175
+#define SP_INC_175 176
+#define SP_INC_176 177
+#define SP_INC_177 178
+#define SP_INC_178 179
+#define SP_INC_179 180
+#define SP_INC_180 181
+#define SP_INC_181 182
+#define SP_INC_182 183
+#define SP_INC_183 184
+#define SP_INC_184 185
+#define SP_INC_185 186
+#define SP_INC_186 187
+#define SP_INC_187 188
+#define SP_INC_188 189
+#define SP_INC_189 190
+#define SP_INC_190 191
+#define SP_INC_191 192
+#define SP_INC_192 193
+#define SP_INC_193 194
+#define SP_INC_194 195
+#define SP_INC_195 196
+#define SP_INC_196 197
+#define SP_INC_197 198
+#define SP_INC_198 199
+#define SP_INC_199 200
+#define SP_INC_200 201
+#define SP_INC_201 202
+#define SP_INC_202 203
+#define SP_INC_203 204
+#define SP_INC_204 205
+#define SP_INC_205 206
+#define SP_INC_206 207
+#define SP_INC_207 208
+#define SP_INC_208 209
+#define SP_INC_209 210
+#define SP_INC_210 211
+#define SP_INC_211 212
+#define SP_INC_212 213
+#define SP_INC_213 214
+#define SP_INC_214 215
+#define SP_INC_215 216
+#define SP_INC_216 217
+#define SP_INC_217 218
+#define SP_INC_218 219
+#define SP_INC_219 220
+#define SP_INC_220 221
+#define SP_INC_221 222
+#define SP_INC_222 223
+#define SP_INC_223 224
+#define SP_INC_224 225
+#define SP_INC_225 226
+#define SP_INC_226 227
+#define SP_INC_227 228
+#define SP_INC_228 229
+#define SP_INC_229 230
+#define SP_INC_230 231
+#define SP_INC_231 232
+#define SP_INC_232 233
+#define SP_INC_233 234
+#define SP_INC_234 235
+#define SP_INC_235 236
+#define SP_INC_236 237
+#define SP_INC_237 238
+#define SP_INC_238 239
+#define SP_INC_239 240
+#define SP_INC_240 241
+#define SP_INC_241 242
+#define SP_INC_242 243
+#define SP_INC_243 244
+#define SP_INC_244 245
+#define SP_INC_245 246
+#define SP_INC_246 247
+#define SP_INC_247 248
+#define SP_INC_248 249
+#define SP_INC_249 250
+#define SP_INC_250 251
+#define SP_INC_251 252
+#define SP_INC_252 253
+#define SP_INC_253 254
+#define SP_INC_254 255
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_INCREMENT_MACRO_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_list.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_list.h
new file mode 100644
index 000000000..977e8ccad
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_list.h
@@ -0,0 +1,164 @@
+/**
+ * \file
+ *
+ * \brief List declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_LIST_H_INCLUDED
+#define _UTILS_LIST_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_list
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+/**
+ * \brief List element type
+ */
+struct list_element {
+	struct list_element *next;
+};
+
+/**
+ * \brief List head type
+ */
+struct list_descriptor {
+	struct list_element *head;
+};
+
+/**
+ * \brief Reset list
+ *
+ * \param[in] list The pointer to a list descriptor
+ */
+static inline void list_reset(struct list_descriptor *const list)
+{
+	list->head = NULL;
+}
+
+/**
+ * \brief Retrieve list head
+ *
+ * \param[in] list The pointer to a list descriptor
+ *
+ * \return A pointer to the head of the given list or NULL if the list is
+ * empty
+ */
+static inline void *list_get_head(const struct list_descriptor *const list)
+{
+	return (void *)list->head;
+}
+
+/**
+ * \brief Retrieve next list head
+ *
+ * \param[in] list The pointer to a list element
+ *
+ * \return A pointer to the next list element or NULL if there is not next
+ * element
+ */
+static inline void *list_get_next_element(const void *const element)
+{
+	return element ? ((struct list_element *)element)->next : NULL;
+}
+
+/**
+ * \brief Insert an element as list head
+ *
+ * \param[in] list The pointer to a list element
+ * \param[in] element An element to insert to the given list
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element);
+
+/**
+ * \brief Insert an element after the given list element
+ *
+ * \param[in] after An element to insert after
+ * \param[in] element Element to insert to the given list
+ */
+void list_insert_after(void *const after, void *const element);
+
+/**
+ * \brief Insert an element at list end
+ *
+ * \param[in] after An element to insert after
+ * \param[in] element Element to insert to the given list
+ */
+void list_insert_at_end(struct list_descriptor *const list, void *const element);
+
+/**
+ * \brief Check whether an element belongs to a list
+ *
+ * \param[in] list The pointer to a list
+ * \param[in] element An element to check
+ *
+ * \return The result of checking
+ * \retval true If the given element is an element of the given list
+ * \retval false Otherwise
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element);
+
+/**
+ * \brief Removes list head
+ *
+ * This function removes the list head and sets the next element after the list
+ * head as a new list head.
+ *
+ * \param[in] list The pointer to a list
+ *
+ * \return The pointer to the new list head of NULL if the list head is NULL
+ */
+void *list_remove_head(struct list_descriptor *const list);
+
+/**
+ * \brief Removes the list element
+ *
+ * \param[in] list The pointer to a list
+ * \param[in] element An element to remove
+ *
+ * \return The result of element removing
+ * \retval true The given element is removed from the given list
+ * \retval false The given element is not an element of the given list
+ */
+bool list_delete_element(struct list_descriptor *const list, const void *const element);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_LIST_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_repeat_macro.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_repeat_macro.h
new file mode 100644
index 000000000..89e6f52d5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/include/utils_repeat_macro.h
@@ -0,0 +1,322 @@
+/**
+ * \file
+ *
+ * \brief Repeat macro.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _UTILS_REPEAT_MACRO_H
+#define _UTILS_REPEAT_MACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief Sequently repeates specified macro for n times (255 max).
+ *
+ * Specified macro shall have two arguments:  macro(arg, i)
+ *   arg - user defined argument, which have the same value for all iterations.
+ *   i - iteration number; numbering begins from zero and increments on each
+ *   iteration.
+ *
+ * \param[in] macro - macro to be repeated
+ * \param[in] arg - user defined argument for repeated macro
+ * \param[in] n - total number of iterations (255 max)
+ */
+#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n)
+
+/*
+ * \brief Second level is needed to get integer literal from "n" if it is
+ *        defined as macro
+ */
+#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0)
+
+#define REPEAT1(macro, arg, n) macro(arg, n)
+#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n))
+#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n))
+#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n))
+#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n))
+#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n))
+#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n))
+#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n))
+#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n))
+#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n))
+#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n))
+#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n))
+#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n))
+#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n))
+#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n))
+#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n))
+#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n))
+#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n))
+#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n))
+#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n))
+#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n))
+#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n))
+#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n))
+#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n))
+#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n))
+#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n))
+#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n))
+#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n))
+#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n))
+#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n))
+#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n))
+#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n))
+#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n))
+#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n))
+#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n))
+#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n))
+#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n))
+#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n))
+#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n))
+#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n))
+#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n))
+#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n))
+#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n))
+#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n))
+#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n))
+#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n))
+#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n))
+#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n))
+#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n))
+#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n))
+#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n))
+#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n))
+#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n))
+#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n))
+#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n))
+#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n))
+#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n))
+#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n))
+#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n))
+#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n))
+#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n))
+#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n))
+#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n))
+#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n))
+#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n))
+#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n))
+#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n))
+#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n))
+#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n))
+#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n))
+#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n))
+#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n))
+#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n))
+#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n))
+#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n))
+#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n))
+#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n))
+#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n))
+#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n))
+#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n))
+#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n))
+#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n))
+#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n))
+#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n))
+#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n))
+#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n))
+#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n))
+#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n))
+#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n))
+#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n))
+#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n))
+#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n))
+#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n))
+#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n))
+#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n))
+#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n))
+#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n))
+#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n))
+#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n))
+#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n))
+#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n))
+#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n))
+#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n))
+#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n))
+#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n))
+#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n))
+#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n))
+#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n))
+#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n))
+#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n))
+#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n))
+#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n))
+#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n))
+#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n))
+#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n))
+#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n))
+#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n))
+#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n))
+#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n))
+#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n))
+#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n))
+#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n))
+#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n))
+#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n))
+#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n))
+#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n))
+#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n))
+#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n))
+#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n))
+#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n))
+#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n))
+#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n))
+#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n))
+#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n))
+#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n))
+#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n))
+#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n))
+#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n))
+#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n))
+#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n))
+#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n))
+#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n))
+#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n))
+#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n))
+#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n))
+#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n))
+#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n))
+#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n))
+#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n))
+#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n))
+#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n))
+#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n))
+#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n))
+#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n))
+#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n))
+#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n))
+#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n))
+#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n))
+#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n))
+#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n))
+#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n))
+#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n))
+#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n))
+#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n))
+#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n))
+#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n))
+#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n))
+#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n))
+#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n))
+#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n))
+#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n))
+#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n))
+#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n))
+#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n))
+#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n))
+#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n))
+#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n))
+#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n))
+#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n))
+#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n))
+#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n))
+#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n))
+#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n))
+#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n))
+#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n))
+#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n))
+#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n))
+#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n))
+#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n))
+#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n))
+#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n))
+#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n))
+#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n))
+#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n))
+#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n))
+#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n))
+#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n))
+#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n))
+#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n))
+#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n))
+#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n))
+#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n))
+#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n))
+#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n))
+#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n))
+#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n))
+#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n))
+#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n))
+#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n))
+#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n))
+#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n))
+#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n))
+#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n))
+#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n))
+#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n))
+#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n))
+#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n))
+#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n))
+#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n))
+#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n))
+#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n))
+#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n))
+#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n))
+#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n))
+#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n))
+#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n))
+#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n))
+#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n))
+#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n))
+#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n))
+#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n))
+#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n))
+#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n))
+#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n))
+#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n))
+#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n))
+#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n))
+#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n))
+#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n))
+#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n))
+#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n))
+#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n))
+#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n))
+#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n))
+#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n))
+#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n))
+#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n))
+#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n))
+#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n))
+#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n))
+#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n))
+#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n))
+#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n))
+#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n))
+#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <utils_increment_macro.h>
+#endif /* _UTILS_REPEAT_MACRO_H */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_assert.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_assert.c
new file mode 100644
index 000000000..b376c9700
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_assert.c
@@ -0,0 +1,46 @@
+/**
+ * \file
+ *
+ * \brief Asserts related functionality.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_assert.h>
+
+/**
+ * \brief Assert function
+ */
+void assert(const bool condition, const char *const file, const int line)
+{
+	if (!(condition)) {
+		__asm("BKPT #0");
+	}
+	(void)file;
+	(void)line;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_event.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_event.c
new file mode 100644
index 000000000..d1af9d0cf
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_event.c
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * \brief Events implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_event.h>
+#include <utils_assert.h>
+#include <string.h>
+
+#define EVENT_WORD_BITS (sizeof(event_word_t) * 8)
+
+static struct list_descriptor events;
+static uint8_t                subscribed[EVENT_MASK_SIZE];
+
+int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t position = id >> 3;
+	const uint8_t mask     = 1 << (id & 0x7);
+
+	ASSERT(event && cb && (id < EVENT_MAX_AMOUNT));
+
+	if (event->mask[position] & mask) {
+		return ERR_NO_CHANGE; /* Already subscribed */
+	}
+
+	if (!is_list_element(&events, event)) {
+		memset(event->mask, 0, EVENT_MASK_SIZE);
+		list_insert_as_head(&events, event);
+	}
+	event->cb = cb;
+	event->mask[position] |= mask;
+
+	subscribed[position] |= mask;
+
+	return ERR_NONE;
+}
+
+int32_t event_unsubscribe(struct event *const event, const event_id_t id)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t       position = id >> 3;
+	const uint8_t       mask     = 1 << (id & 0x7);
+	const struct event *current;
+	uint8_t             i;
+
+	ASSERT(event && (id < EVENT_MAX_AMOUNT));
+
+	if (!(event->mask[position] & mask)) {
+		return ERR_NO_CHANGE; /* Already unsubscribed */
+	}
+
+	event->mask[position] &= ~mask;
+
+	/* Check if there are more subscribers */
+	for ((current = (const struct event *)list_get_head(&events)); current;
+	     current = (const struct event *)list_get_next_element(current)) {
+		if (current->mask[position] & mask) {
+			break;
+		}
+	}
+	if (!current) {
+		subscribed[position] &= ~mask;
+	}
+
+	/* Remove event from the list. Can be unsave, document it! */
+	for (i = 0; i < ARRAY_SIZE(event->mask); i++) {
+		if (event->mask[i]) {
+			return ERR_NONE;
+		}
+	}
+	list_delete_element(&events, event);
+
+	return ERR_NONE;
+}
+
+void event_post(const event_id_t id, const event_data_t data)
+{
+	/* get byte and bit number of the given event in the event mask */
+	const uint8_t       position = id >> 3;
+	const uint8_t       mask     = 1 << (id & 0x7);
+	const struct event *current;
+
+	ASSERT((id < EVENT_MAX_AMOUNT));
+
+	if (!(subscribed[position] & mask)) {
+		return; /* No subscribers */
+	}
+
+	/* Find all subscribers */
+	for ((current = (const struct event *)list_get_head(&events)); current;
+	     current = (const struct event *)list_get_next_element(current)) {
+		if (current->mask[position] & mask) {
+			current->cb(id, data);
+		}
+	}
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_list.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_list.c
new file mode 100644
index 000000000..4006a0193
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_list.c
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief List functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <utils_list.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Check whether element belongs to list
+ */
+bool is_list_element(const struct list_descriptor *const list, const void *const element)
+{
+	struct list_element *it;
+	for (it = list->head; it; it = it->next) {
+		if (it == element) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+/**
+ * \brief Insert an element as list head
+ */
+void list_insert_as_head(struct list_descriptor *const list, void *const element)
+{
+	ASSERT(!is_list_element(list, element));
+
+	((struct list_element *)element)->next = list->head;
+	list->head                             = (struct list_element *)element;
+}
+
+/**
+ * \brief Insert an element after the given list element
+ */
+void list_insert_after(void *const after, void *const element)
+{
+	((struct list_element *)element)->next = ((struct list_element *)after)->next;
+	((struct list_element *)after)->next   = (struct list_element *)element;
+}
+
+/**
+ * \brief Insert an element at list end
+ */
+void list_insert_at_end(struct list_descriptor *const list, void *const element)
+{
+	struct list_element *it = list->head;
+
+	ASSERT(!is_list_element(list, element));
+
+	if (!list->head) {
+		list->head                             = (struct list_element *)element;
+		((struct list_element *)element)->next = NULL;
+		return;
+	}
+
+	while (it->next) {
+		it = it->next;
+	}
+	it->next                               = (struct list_element *)element;
+	((struct list_element *)element)->next = NULL;
+}
+
+/**
+ * \brief Removes list head
+ */
+void *list_remove_head(struct list_descriptor *const list)
+{
+	if (list->head) {
+		struct list_element *tmp = list->head;
+
+		list->head = list->head->next;
+		return (void *)tmp;
+	}
+
+	return NULL;
+}
+
+/**
+ * \brief Removes list element
+ */
+bool list_delete_element(struct list_descriptor *const list, const void *const element)
+{
+	if (!element) {
+		return false;
+	}
+
+	if (list->head == element) {
+		list->head = list->head->next;
+		return true;
+	} else {
+		struct list_element *it = list->head;
+
+		while (it && it->next != element) {
+			it = it->next;
+		}
+		if (it) {
+			it->next = ((struct list_element *)element)->next;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+//@}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_syscalls.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_syscalls.c
new file mode 100644
index 000000000..79e2f1fe4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hal/utils/src/utils_syscalls.c
@@ -0,0 +1,152 @@
+/**
+ * \file
+ *
+ * \brief Syscalls for SAM0 (GCC).
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#undef errno
+extern int errno;
+extern int _end;
+
+extern caddr_t _sbrk(int incr);
+extern int     link(char *old, char *_new);
+extern int     _close(int file);
+extern int     _fstat(int file, struct stat *st);
+extern int     _isatty(int file);
+extern int     _lseek(int file, int ptr, int dir);
+extern void    _exit(int status);
+extern void    _kill(int pid, int sig);
+extern int     _getpid(void);
+
+/**
+ * \brief Replacement of C library of _sbrk
+ */
+extern caddr_t _sbrk(int incr)
+{
+	static unsigned char *heap = NULL;
+	unsigned char *       prev_heap;
+
+	if (heap == NULL) {
+		heap = (unsigned char *)&_end;
+	}
+	prev_heap = heap;
+
+	heap += incr;
+
+	return (caddr_t)prev_heap;
+}
+
+/**
+ * \brief Replacement of C library of link
+ */
+extern int link(char *old, char *_new)
+{
+	(void)old, (void)_new;
+	return -1;
+}
+
+/**
+ * \brief Replacement of C library of _close
+ */
+extern int _close(int file)
+{
+	(void)file;
+	return -1;
+}
+
+/**
+ * \brief Replacement of C library of _fstat
+ */
+extern int _fstat(int file, struct stat *st)
+{
+	(void)file;
+	st->st_mode = S_IFCHR;
+
+	return 0;
+}
+
+/**
+ * \brief Replacement of C library of _isatty
+ */
+extern int _isatty(int file)
+{
+	(void)file;
+	return 1;
+}
+
+/**
+ * \brief Replacement of C library of _lseek
+ */
+extern int _lseek(int file, int ptr, int dir)
+{
+	(void)file, (void)ptr, (void)dir;
+	return 0;
+}
+
+/**
+ * \brief Replacement of C library of _exit
+ */
+extern void _exit(int status)
+{
+	printf("Exiting with status %d.\n", status);
+
+	for (;;)
+		;
+}
+
+/**
+ * \brief Replacement of C library of _kill
+ */
+extern void _kill(int pid, int sig)
+{
+	(void)pid, (void)sig;
+	return;
+}
+
+/**
+ * \brief Replacement of C library of _getpid
+ */
+extern int _getpid(void)
+{
+	return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_core_m4.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_core_m4.c
new file mode 100644
index 000000000..4680ec310
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_core_m4.c
@@ -0,0 +1,241 @@
+/**
+ * \file
+ *
+ * \brief Core related functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_core.h>
+#include <hpl_irq.h>
+#ifndef _UNIT_TEST_
+#include <utils.h>
+#endif
+#include <utils_assert.h>
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 1000000
+#endif
+
+#if CONF_CPU_FREQUENCY < 1000
+#define CPU_FREQ_POWER 3
+#elif CONF_CPU_FREQUENCY < 10000
+#define CPU_FREQ_POWER 4
+#elif CONF_CPU_FREQUENCY < 100000
+#define CPU_FREQ_POWER 5
+#elif CONF_CPU_FREQUENCY < 1000000
+#define CPU_FREQ_POWER 6
+#elif CONF_CPU_FREQUENCY < 10000000
+#define CPU_FREQ_POWER 7
+#elif CONF_CPU_FREQUENCY < 100000000
+#define CPU_FREQ_POWER 8
+#elif CONF_CPU_FREQUENCY < 1000000000
+#define CPU_FREQ_POWER 9
+#endif
+
+/**
+ * \brief The array of interrupt handlers
+ */
+struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn];
+
+/**
+ * \brief Reset MCU
+ */
+void _reset_mcu(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Put MCU to sleep
+ */
+void _go_to_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * \brief Retrieve current IRQ number
+ */
+uint8_t _irq_get_current(void)
+{
+	return (uint8_t)__get_IPSR() - 16;
+}
+
+/**
+ * \brief Disable the given IRQ
+ */
+void _irq_disable(uint8_t n)
+{
+	NVIC_DisableIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Set the given IRQ
+ */
+void _irq_set(uint8_t n)
+{
+	NVIC_SetPendingIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Clear the given IRQ
+ */
+void _irq_clear(uint8_t n)
+{
+	NVIC_ClearPendingIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Enable the given IRQ
+ */
+void _irq_enable(uint8_t n)
+{
+	NVIC_EnableIRQ((IRQn_Type)n);
+}
+
+/**
+ * \brief Register IRQ handler
+ */
+void _irq_register(const uint8_t n, struct _irq_descriptor *const irq)
+{
+	ASSERT(n < PERIPH_COUNT_IRQn);
+
+	_irq_table[n] = irq;
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Default_Handler(void)
+{
+	while (1) {
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ */
+static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power)
+{
+	switch (power) {
+	case 9:
+		return (us * (freq / 1000000) + 2) / 3;
+	case 8:
+		return (us * (freq / 100000) + 29) / 30;
+	case 7:
+		return (us * (freq / 10000) + 299) / 300;
+	case 6:
+		return (us * (freq / 1000) + 2999) / 3000;
+	case 5:
+		return (us * (freq / 100) + 29999) / 30000;
+	case 4:
+		return (us * (freq / 10) + 299999) / 300000;
+	default:
+		return (us * freq + 2999999) / 3000000;
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of us
+ */
+uint32_t _get_cycles_for_us(const uint16_t us)
+{
+	return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ */
+static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power)
+{
+	switch (power) {
+	case 9:
+		return (ms * (freq / 1000000) + 2) / 3 * 1000;
+	case 8:
+		return (ms * (freq / 100000) + 2) / 3 * 100;
+	case 7:
+		return (ms * (freq / 10000) + 2) / 3 * 10;
+	case 6:
+		return (ms * (freq / 1000) + 2) / 3;
+	case 5:
+		return (ms * (freq / 100) + 29) / 30;
+	case 4:
+		return (ms * (freq / 10) + 299) / 300;
+	default:
+		return (ms * (freq / 1) + 2999) / 3000;
+	}
+}
+
+/**
+ * \brief Retrieve the amount of cycles to delay for the given amount of ms
+ */
+uint32_t _get_cycles_for_ms(const uint16_t ms)
+{
+	return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER);
+}
+/**
+ * \brief Initialize delay functionality
+ */
+void _delay_init(void *const hw)
+{
+	(void)hw;
+}
+/**
+ * \brief Delay loop to delay n number of cycles
+ */
+void _delay_cycles(void *const hw, uint32_t cycles)
+{
+#ifndef _UNIT_TEST_
+	(void)hw;
+	(void)cycles;
+#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /*  Keil MDK with ARM Compiler 6 */
+	__asm(".align 3 \n"
+	      "__delay:\n"
+	      "subs r1, r1, #1\n"
+	      "bhi __delay\n");
+#elif defined __GNUC__
+	__asm(".syntax unified\n"
+	      ".align 3 \n"
+	      "__delay:\n"
+	      "subs r1, r1, #1\n"
+	      "bhi __delay\n"
+	      ".syntax divided");
+#elif defined __CC_ARM
+	__asm("__delay:\n"
+	      "subs cycles, cycles, #1\n"
+	      "bhi __delay\n");
+#elif defined __ICCARM__
+	__asm("__delay:\n"
+	      "subs r1, r1, #1\n"
+	      "bhi.n __delay\n");
+#endif
+#endif
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_core_port.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_core_port.h
new file mode 100644
index 000000000..3f3e8f282
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_core_port.h
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief Core related functionality implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_CORE_PORT_H_INCLUDED
+#define _HPL_CORE_PORT_H_INCLUDED
+
+#include <peripheral_clk_config.h>
+
+/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR
+ * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h),
+ * there will be assembling errors.
+ * So the following things are not included for assembling.
+ */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+
+#ifndef _UNIT_TEST_
+#include <compiler.h>
+#endif
+
+/**
+ * \brief Check if it's in ISR handling
+ * \return \c true if it's in ISR
+ */
+static inline bool _is_in_isr(void)
+{
+	return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+}
+
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _HPL_CORE_PORT_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_init.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_init.c
new file mode 100644
index 000000000..be0db930f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/core/hpl_init.c
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief HPL initialization related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_gpio.h>
+#include <hpl_init.h>
+#include <hpl_gclk_base.h>
+#include <hpl_mclk_config.h>
+
+#include <hpl_dma.h>
+#include <hpl_dmac_config.h>
+#include <hpl_cmcc_config.h>
+#include <hal_cache.h>
+
+/* Referenced GCLKs (out of 0~11), should be initialized firstly
+ */
+#define _GCLK_INIT_1ST 0x00000000
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST 0x00000FFF
+
+/**
+ * \brief Initialize the hardware abstraction layer
+ */
+void _init_chip(void)
+{
+	hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+	_osc32kctrl_init_sources();
+	_oscctrl_init_sources();
+	_mclk_init();
+#if _GCLK_INIT_1ST
+	_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+	_oscctrl_init_referenced_generators();
+	_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+#if CONF_DMAC_ENABLE
+	hri_mclk_set_AHBMASK_DMAC_bit(MCLK);
+	_dma_init();
+#endif
+
+#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
+	_port_event_init();
+#endif
+
+#if CONF_CMCC_ENABLE
+	cache_init();
+#endif
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/gclk/hpl_gclk.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/gclk/hpl_gclk.c
new file mode 100644
index 000000000..211ccc3ff
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/gclk/hpl_gclk.c
@@ -0,0 +1,312 @@
+
+/**
+ * \file
+ *
+ * \brief Generic Clock Controller related functionality.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_gclk_config.h>
+#include <hpl_init.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Initializes generators
+ */
+void _gclk_init_generators(void)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    0,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_1_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    1,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_2_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    2,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    3,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_4_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    4,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_5_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    5,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_6_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    6,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_7_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    7,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_8_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    8,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_9_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    9,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_10_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    10,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE);
+#endif
+
+#if CONF_GCLK_GENERATOR_11_CONFIG == 1
+	hri_gclk_write_GENCTRL_reg(
+	    GCLK,
+	    11,
+	    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+	        | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
+	        | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
+	        | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
+#endif
+}
+
+void _gclk_init_generators_by_fref(uint32_t bm)
+{
+
+#if CONF_GCLK_GENERATOR_0_CONFIG == 1
+	if (bm & (1ul << 0)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    0,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_1_CONFIG == 1
+	if (bm & (1ul << 1)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    1,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_2_CONFIG == 1
+	if (bm & (1ul << 2)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    2,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_3_CONFIG == 1
+	if (bm & (1ul << 3)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    3,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_4_CONFIG == 1
+	if (bm & (1ul << 4)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    4,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_5_CONFIG == 1
+	if (bm & (1ul << 5)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    5,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_6_CONFIG == 1
+	if (bm & (1ul << 6)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    6,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_7_CONFIG == 1
+	if (bm & (1ul << 7)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    7,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_8_CONFIG == 1
+	if (bm & (1ul << 8)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    8,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_9_CONFIG == 1
+	if (bm & (1ul << 9)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    9,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_10_CONFIG == 1
+	if (bm & (1ul << 10)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    10,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE);
+	}
+#endif
+
+#if CONF_GCLK_GENERATOR_11_CONFIG == 1
+	if (bm & (1ul << 11)) {
+		hri_gclk_write_GENCTRL_reg(
+		    GCLK,
+		    11,
+		    GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
+		        | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
+		        | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
+		        | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
+	}
+#endif
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/gclk/hpl_gclk_base.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/gclk/hpl_gclk_base.h
new file mode 100644
index 000000000..3e7d28257
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/gclk/hpl_gclk_base.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Generic Clock Controller.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_GCLK_H_INCLUDED
+#define _HPL_GCLK_H_INCLUDED
+
+#include <compiler.h>
+#ifdef _UNIT_TEST_
+#include <hri_gclk1_v210_mock.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup gclk_group GCLK Hardware Proxy Layer
+ *
+ * \section gclk_hpl_rev Revision History
+ * - v0.0.0.1 Initial Commit
+ *
+ *@{
+ */
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Enable clock on the given channel with the given clock source
+ *
+ * This function maps the given clock source to the given clock channel
+ * and enables channel.
+ *
+ * \param[in] channel The channel to enable clock for
+ * \param[in] source The clock source for the given channel
+ */
+static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source)
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN);
+}
+
+/**
+ * \brief Initialize GCLK generators by function references
+ * \param[in] bm Bit mapping for referenced generators,
+ *               a bit 1 in position triggers generator initialization.
+ */
+void _gclk_init_generators_by_fref(uint32_t bm);
+
+//@}
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HPL_GCLK_H_INCLUDED */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/mclk/hpl_mclk.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/mclk/hpl_mclk.c
new file mode 100644
index 000000000..66843205b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/mclk/hpl_mclk.c
@@ -0,0 +1,44 @@
+/**
+ * \file
+ *
+ * \brief SAM Main Clock.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <hpl_mclk_config.h>
+
+/**
+ * \brief Initialize master clock generator
+ */
+void _mclk_init(void)
+{
+	void *hw = (void *)MCLK;
+	hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/port/hpl_gpio_base.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/port/hpl_gpio_base.h
new file mode 100644
index 000000000..12ff6f74f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/port/hpl_gpio_base.h
@@ -0,0 +1,171 @@
+
+/**
+ * \file
+ *
+ * \brief SAM PORT.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <compiler.h>
+#include <hpl_gpio.h>
+#include <utils_assert.h>
+#include <hpl_port_config.h>
+
+/**
+ * \brief Set direction on port with mask
+ */
+static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
+                                       const enum gpio_direction direction)
+{
+	switch (direction) {
+	case GPIO_DIRECTION_OFF:
+		hri_port_clear_DIR_reg(PORT, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_IN:
+		hri_port_clear_DIR_reg(PORT, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(PORT,
+		                            port,
+		                            PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN
+		                                | ((mask & 0xffff0000) >> 16));
+		break;
+
+	case GPIO_DIRECTION_OUT:
+		hri_port_set_DIR_reg(PORT, port, mask);
+		hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
+		hri_port_write_WRCONFIG_reg(
+		    PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
+		break;
+
+	default:
+		ASSERT(false);
+	}
+}
+
+/**
+ * \brief Set output level on port with mask
+ */
+static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level)
+{
+	if (level) {
+		hri_port_set_OUT_reg(PORT, port, mask);
+	} else {
+		hri_port_clear_OUT_reg(PORT, port, mask);
+	}
+}
+
+/**
+ * \brief Change output level to the opposite with mask
+ */
+static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask)
+{
+	hri_port_toggle_OUT_reg(PORT, port, mask);
+}
+
+/**
+ * \brief Get input levels on all port pins
+ */
+static inline uint32_t _gpio_get_level(const enum gpio_port port)
+{
+	uint32_t tmp;
+
+	CRITICAL_SECTION_ENTER();
+
+	uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port);
+
+	tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp;
+	tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp;
+
+	CRITICAL_SECTION_LEAVE();
+
+	return tmp;
+}
+
+/**
+ * \brief Set pin pull mode
+ */
+static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
+                                           const enum gpio_pull_mode pull_mode)
+{
+	switch (pull_mode) {
+	case GPIO_PULL_OFF:
+		hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin);
+		break;
+
+	case GPIO_PULL_UP:
+		hri_port_clear_DIR_reg(PORT, port, 1U << pin);
+		hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
+		hri_port_set_OUT_reg(PORT, port, 1U << pin);
+		break;
+
+	case GPIO_PULL_DOWN:
+		hri_port_clear_DIR_reg(PORT, port, 1U << pin);
+		hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin);
+		hri_port_clear_OUT_reg(PORT, port, 1U << pin);
+		break;
+
+	default:
+		ASSERT(false);
+		break;
+	}
+}
+
+/**
+ * \brief Set gpio pin function
+ */
+static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
+{
+	uint8_t port = GPIO_PORT(gpio);
+	uint8_t pin  = GPIO_PIN(gpio);
+
+	if (function == GPIO_PIN_FUNCTION_OFF) {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false);
+
+	} else {
+		hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
+
+		if (pin & 1) {
+			// Odd numbered pin
+			hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
+		} else {
+			// Even numbered pin
+			hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
+		}
+	}
+}
+
+static inline void _port_event_init()
+{
+	hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
+	hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
+	hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL);
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/usb/hpl_usb.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/usb/hpl_usb.c
new file mode 100644
index 000000000..65f594934
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hpl/usb/hpl_usb.c
@@ -0,0 +1,2078 @@
+/**
+ * \file
+ *
+ * \brief SAM USB HPL
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <compiler.h>
+#include <hal_atomic.h>
+#include <hpl_usb.h>
+#include <hpl_usb_device.h>
+
+#include <hpl_usb_config.h>
+#include <string.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Dummy callback function
+ * \return Always false.
+ */
+static bool _dummy_func_no_return(uint32_t unused0, uint32_t unused1)
+{
+	(void)unused0;
+	(void)unused1;
+	return false;
+}
+
+/**
+ * \brief Load USB calibration value from NVM
+ */
+static void _usb_load_calib(void)
+{
+#define NVM_USB_PAD_TRANSN_POS 32
+#define NVM_USB_PAD_TRANSN_SIZE 5
+#define NVM_USB_PAD_TRANSP_POS 37
+#define NVM_USB_PAD_TRANSP_SIZE 5
+#define NVM_USB_PAD_TRIM_POS 42
+#define NVM_USB_PAD_TRIM_SIZE 3
+	Usb *    hw = USB;
+	uint32_t pad_transn
+	    = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRANSN_POS / 32)) >> (NVM_USB_PAD_TRANSN_POS % 32))
+	      & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+	uint32_t pad_transp
+	    = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRANSP_POS / 32)) >> (NVM_USB_PAD_TRANSP_POS % 32))
+	      & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+	uint32_t pad_trim = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRIM_POS / 32)) >> (NVM_USB_PAD_TRIM_POS % 32))
+	                    & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+	if (pad_transn == 0 || pad_transn == 0x1F) {
+		pad_transn = 9;
+	}
+	if (pad_transp == 0 || pad_transp == 0x1F) {
+		pad_transp = 25;
+	}
+	if (pad_trim == 0 || pad_trim == 0x7) {
+		pad_trim = 6;
+	}
+
+	hw->DEVICE.PADCAL.reg = USB_PADCAL_TRANSN(pad_transn) | USB_PADCAL_TRANSP(pad_transp) | USB_PADCAL_TRIM(pad_trim);
+
+	hw->DEVICE.QOSCTRL.bit.CQOS = 3;
+	hw->DEVICE.QOSCTRL.bit.DQOS = 3;
+}
+
+/** \name USB clock source management */
+/*@{*/
+
+/** USB clock is generated by DFLL. */
+#define USB_CLK_SRC_DFLL 0
+
+/** USB clock is generated by DPLL. */
+#define USB_CLK_SRC_DPLL 1
+
+/** Uses DFLL as USB clock source. */
+#define CONF_USB_D_CLK_SRC USB_CLK_SRC_DPLL
+
+/** Retry for USB remote wakeup sending. */
+#define CONF_USB_RMT_WKUP_RETRY 5
+
+/**
+ * \brief Wait DPLL clock to be ready
+ */
+static inline void _usb_d_dev_wait_dpll_rdy(void)
+{
+#define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)
+	while (hri_oscctrl_get_DPLLSTATUS_reg(OSCCTRL, 0, DPLL_READY_FLAG) != DPLL_READY_FLAG)
+		;
+}
+
+/**
+ * \brief Wait DFLL clock to be ready
+ */
+static inline void _usb_d_dev_wait_dfll_rdy(void)
+{
+	if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(OSCCTRL)) {
+		while (hri_oscctrl_get_STATUS_reg(OSCCTRL, (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC))
+		       != (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC))
+			;
+	} else {
+		while (hri_oscctrl_get_STATUS_reg(OSCCTRL, OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY)
+			;
+	}
+}
+
+/**
+ * \brief Wait USB source clock to be ready
+ * \param[in] clk_src Clock source, could be \ref USB_CLK_SRC_DFLL or
+ *                    \ref USB_CLK_SRC_DPLL.
+ */
+static inline void _usb_d_dev_wait_clk_rdy(const uint8_t clk_src)
+{
+	if (clk_src == USB_CLK_SRC_DFLL) {
+		_usb_d_dev_wait_dfll_rdy();
+	} else if (clk_src == USB_CLK_SRC_DPLL) {
+		_usb_d_dev_wait_dpll_rdy();
+	}
+}
+
+/*@}*/
+
+/** \name USB general settings */
+/*@{*/
+
+/** Increase the value to be aligned. */
+#define _usb_align_up(val) (((val)&0x3) ? (((val) + 4 - ((val)&0x3))) : (val))
+
+/** Check if the buffer is in RAM (can DMA), or cache needed
+ *  \param[in] a Buffer start address.
+ *  \param[in] s Buffer size, in number of bytes.
+ *  \return \c true If the buffer is in RAM.
+ */
+#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < (0x20000000 + 0x00032000)))
+
+/** Check if the address should be placed in RAM. */
+#define _usb_is_addr4dma(addr, size) _IN_RAM((addr), (size))
+
+/** Check if the address is 32-bit aligned. */
+#define _usb_is_aligned(val) (((uint32_t)(val)&0x3) == 0)
+/*@}*/
+
+/* Cache static configurations.
+ * By default, all OUT endpoint have 64 bytes cache. */
+#ifndef CONF_USB_EP0_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP0_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP0_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP0_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP1_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP1_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP1_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP1_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP2_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP2_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP2_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP2_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP3_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP3_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP3_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP3_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP4_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP4_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP4_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP4_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP5_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP5_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP5_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP5_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP6_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP6_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP6_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP6_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP7_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP7_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP7_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP7_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP8_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP8_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP8_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP8_I_CACHE 0
+#endif
+
+#ifndef CONF_USB_EP9_CACHE
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#define CONF_USB_EP9_CACHE 64
+#endif
+
+#ifndef CONF_USB_EP9_I_CACHE
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define CONF_USB_EP9_I_CACHE 0
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP0_CACHE
+static uint32_t _usb_ep0_cache[_usb_align_up(CONF_USB_EP0_CACHE) / 4];
+#else
+#define _usb_ep0_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#define _usb_ep0_i_cache NULL
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1
+static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4];
+#else
+#define _usb_ep1_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1
+static uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4];
+#else
+#define _usb_ep1_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP2_CACHE && CONF_USB_D_MAX_EP_N >= 2
+static uint32_t _usb_ep2_cache[_usb_align_up(CONF_USB_EP2_CACHE) / 4];
+#else
+#define _usb_ep2_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP2_I_CACHE && CONF_USB_D_MAX_EP_N >= 2
+static uint32_t _usb_ep2_i_cache[_usb_align_up(CONF_USB_EP2_I_CACHE) / 4];
+#else
+#define _usb_ep2_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP3_CACHE && CONF_USB_D_MAX_EP_N >= 3
+static uint32_t _usb_ep3_cache[_usb_align_up(CONF_USB_EP3_CACHE) / 4];
+#else
+#define _usb_ep3_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP3_I_CACHE && CONF_USB_D_MAX_EP_N >= 3
+static uint32_t _usb_ep3_i_cache[_usb_align_up(CONF_USB_EP3_I_CACHE) / 4];
+#else
+#define _usb_ep3_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP4_CACHE && CONF_USB_D_MAX_EP_N >= 4
+static uint32_t _usb_ep4_cache[_usb_align_up(CONF_USB_EP4_CACHE) / 4];
+#else
+#define _usb_ep4_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP4_I_CACHE && CONF_USB_D_MAX_EP_N >= 4
+static uint32_t _usb_ep4_i_cache[_usb_align_up(CONF_USB_EP4_I_CACHE) / 4];
+#else
+#define _usb_ep4_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP5_CACHE && CONF_USB_D_MAX_EP_N >= 5
+static uint32_t _usb_ep5_cache[_usb_align_up(CONF_USB_EP5_CACHE) / 4];
+#else
+#define _usb_ep5_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP5_I_CACHE && CONF_USB_D_MAX_EP_N >= 5
+static uint32_t _usb_ep5_i_cache[_usb_align_up(CONF_USB_EP5_I_CACHE) / 4];
+#else
+#define _usb_ep5_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP6_CACHE && CONF_USB_D_MAX_EP_N >= 6
+static uint32_t _usb_ep6_cache[_usb_align_up(CONF_USB_EP6_CACHE) / 4];
+#else
+#define _usb_ep6_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP6_I_CACHE && CONF_USB_D_MAX_EP_N >= 6
+static uint32_t _usb_ep6_i_cache[_usb_align_up(CONF_USB_EP6_I_CACHE) / 4];
+#else
+#define _usb_ep6_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP7_CACHE && CONF_USB_D_MAX_EP_N >= 7
+static uint32_t _usb_ep7_cache[_usb_align_up(CONF_USB_EP7_CACHE) / 4];
+#else
+#define _usb_ep7_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP7_I_CACHE && CONF_USB_D_MAX_EP_N >= 7
+static uint32_t _usb_ep7_i_cache[_usb_align_up(CONF_USB_EP7_I_CACHE) / 4];
+#else
+#define _usb_ep7_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP8_CACHE && CONF_USB_D_MAX_EP_N >= 8
+static uint32_t _usb_ep8_cache[_usb_align_up(CONF_USB_EP8_CACHE) / 4];
+#else
+#define _usb_ep8_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP8_I_CACHE && CONF_USB_D_MAX_EP_N >= 8
+static uint32_t _usb_ep8_i_cache[_usb_align_up(CONF_USB_EP8_I_CACHE) / 4];
+#else
+#define _usb_ep8_i_cache NULL
+#endif
+
+/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT
+ *  transactions (control). */
+#if CONF_USB_EP9_CACHE && CONF_USB_D_MAX_EP_N >= 9
+static uint32_t _usb_ep9_cache[_usb_align_up(CONF_USB_EP9_CACHE) / 4];
+#else
+#define _usb_ep9_cache NULL
+#endif
+
+/** Endpoint cache buffer for IN transactions (none-control). */
+#if CONF_USB_EP9_I_CACHE && CONF_USB_D_MAX_EP_N >= 9
+static uint32_t _usb_ep9_i_cache[_usb_align_up(CONF_USB_EP9_I_CACHE) / 4];
+#else
+#define _usb_ep9_i_cache NULL
+#endif
+
+/** Access endpoint cache buffer for OUT transactions (none-control) or
+ *  SETUP/IN/OUT transactions (control). */
+#define _USB_EP_CACHE(n) ((void *)_usb_ep##n##_cache)
+
+/** Access endpoint cache buffer for IN transactions (none-control). */
+#define _USB_EP_I_CACHE(n) ((void *)_usb_ep##n##_i_cache)
+
+/** The configuration settings for one of the endpoint hardware. */
+struct _usb_ep_cfg_item {
+	/* Endpoint cache buffer for OUT transactions (none-control) or
+	 * SETUP/IN/OUT transactions (control). */
+	void *cache;
+	/* endpoint cache buffer for IN transactions (none-control). */
+	void *i_cache;
+	/* Cache buffer size for OUT transactions (none-control) or
+	 * SETUP/IN/OUT transactions (control). */
+	uint16_t size;
+	/* Cache buffer size for IN transactions (none-control). */
+	uint16_t i_size;
+};
+
+/** Build the endpoint configuration settings for one endpoint. */
+#define _USB_EP_CFG_ITEM(n)                                                                                            \
+	{                                                                                                                  \
+		_USB_EP_CACHE(n), _USB_EP_I_CACHE(n), CONF_USB_EP##n##_CACHE, CONF_USB_EP##n##_I_CACHE,                        \
+	}
+
+/** The configuration settings for all endpoint. */
+static const struct _usb_ep_cfg_item _usb_ep_cfgs[] = {_USB_EP_CFG_ITEM(0)
+#if CONF_USB_D_MAX_EP_N >= 1
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(1)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 2
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(2)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 3
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(3)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 4
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(4)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 5
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(5)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 6
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(6)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 7
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(7)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 8
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(8)
+#endif
+#if CONF_USB_D_MAX_EP_N >= 9
+                                                           ,
+                                                       _USB_EP_CFG_ITEM(9)
+#endif
+};
+
+/** \name HW specific settings and implements */
+/*@{*/
+
+/** Number of endpoints supported. */
+#define USB_D_N_EP (1 + CONF_USB_D_NUM_EP_SP * 2)
+
+/** HPL USB device endpoint struct. */
+struct _usb_d_dev_ep {
+	/** Pointer to transaction buffer. */
+	uint8_t *trans_buf;
+	/** Transaction size. */
+	uint32_t trans_size;
+	/** Transaction transferred count. */
+	uint32_t trans_count;
+
+	/** Pointer to cache buffer, must be aligned. */
+	uint8_t *cache;
+
+	/** Endpoint size. */
+	uint16_t size;
+	/** Endpoint address. */
+	uint8_t ep;
+	/** Feature flags. */
+	union {
+		/** Interpreted by bit fields. */
+		struct {
+			/** EPCFG.ETYPE. */
+			uint8_t eptype : 3;
+			/** Stall status. */
+			uint8_t is_stalled : 1;
+			/** Transaction auto ZLP. */
+			uint8_t need_zlp : 1;
+			/** Transaction with cache */
+			uint8_t use_cache : 1;
+			/** Endpoint is busy. */
+			uint8_t is_busy : 1;
+			/** Transaction direction. */
+			uint8_t dir : 1;
+		} bits;
+		uint8_t u8;
+	} flags;
+};
+
+/** Check if the endpoint is used. */
+#define _usb_d_dev_ep_is_used(ept) ((ept)->ep != 0xFF)
+
+/** Check if the endpoint is busy doing transactions. */
+#define _usb_d_dev_ep_is_busy(ept) ((ept)->flags.bits.is_busy)
+
+/** Check if the endpoint is control endpoint. */
+#define _usb_d_dev_ep_is_ctrl(ept) ((ept)->flags.bits.eptype == USB_D_EPTYPE_CTRL)
+
+/** Check if the endpoint transactions are IN. */
+#define _usb_d_dev_ep_is_in(ept) ((ept)->flags.bits.dir)
+
+/** Interrupt flags for SETUP transaction. */
+#define USB_D_SETUP_INT_FLAGS (USB_DEVICE_EPINTFLAG_RXSTP)
+
+/** Interrupt flags for BANK1 transactions. */
+#define USB_D_BANK1_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT1 | USB_DEVICE_EPINTFLAG_TRFAIL1 | USB_DEVICE_EPINTFLAG_STALL1)
+
+/** Interrupt flags for BANK0 transactions. */
+#define USB_D_BANK0_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT0 | USB_DEVICE_EPINTFLAG_TRFAIL0 | USB_DEVICE_EPINTFLAG_STALL0)
+
+/** Interrupt flags for SETUP/IN/OUT transactions. */
+#define USB_D_ALL_INT_FLAGS (0x7F)
+
+/** Interrupt flags for WAKEUP event. */
+#define USB_D_WAKEUP_INT_FLAGS (USB_DEVICE_INTFLAG_UPRSM | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_WAKEUP)
+
+/** Interrupt flags for SUSPEND event. */
+#define USB_D_SUSPEND_INT_FLAGS (USB_DEVICE_INTFLAG_LPMSUSP | USB_DEVICE_INTFLAG_SUSPEND)
+
+/** Max data bytes for a single DMA transfer. */
+#define USB_D_DEV_TRANS_MAX 8192 /* 14-bits, uses 13-bits. */
+
+/** Endpoint type setting to disable. */
+#define USB_D_EPTYPE_DISABLE 0
+
+/** Endpoint type setting to work as control endpoint. */
+#define USB_D_EPTYPE_CTRL 1
+
+/** Endpoint type setting to work as isochronous endpoint. */
+#define USB_D_EPTYPE_ISOCH 2
+
+/** Endpoint type setting to work as interrupt endpoint. */
+#define USB_D_EPTYPE_INT 3
+
+/** Endpoint type setting to work as bulk endpoint. */
+#define USB_D_EPTYPE_BULK 4
+
+/** Endpoint type setting for dual bank endpoint. */
+#define USB_D_EPTYPE_DUAL 5
+
+/** EPCFG register value for control endpoints. */
+#define USB_D_EPCFG_CTRL 0x11
+
+/** HPL USB device struct. */
+struct _usb_d_dev {
+	/** Callbacks of USB device. */
+	struct _usb_d_dev_callbacks callbacks;
+	/** Endpoint transaction callbacks. */
+	struct _usb_d_dev_ep_callbacks ep_callbacks;
+	/** Endpoints (ep0 + others). */
+	struct _usb_d_dev_ep ep[USB_D_N_EP];
+};
+
+/** Private data for SAM0 USB peripheral.
+ */
+typedef struct _usb_d_dev_prvt {
+	/** USB device descriptor table for peripheral to work. */
+	UsbDeviceDescriptor desc_table[CONF_USB_D_MAX_EP_N + 1];
+} usb_d_dev_prvt_t;
+
+/*@}*/
+
+/** USB device driver instance. */
+static struct _usb_d_dev dev_inst;
+
+/** USB device driver private data instance. */
+static struct _usb_d_dev_prvt prvt_inst;
+
+static void _usb_d_dev_reset_epts(void);
+
+static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t status);
+static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code);
+
+static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr);
+static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr);
+
+static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept);
+
+/** \brief ACK the endpoint interrupt
+ * \param[in] epn Endpoint number.
+ * \param[in] flags Interrupt flags.
+ */
+static inline void _usbd_ep_int_ack(uint8_t epn, uint32_t flags)
+{
+	hri_usbendpoint_clear_EPINTFLAG_reg(USB, epn, flags);
+}
+
+/** \brief Enable the endpoint interrupt
+ * \param[in] epn Endpoint number.
+ * \param[in] flags Interrupt flags.
+ */
+static inline void _usbd_ep_int_en(uint8_t epn, uint32_t flags)
+{
+	hri_usbendpoint_set_EPINTEN_reg(USB, epn, flags);
+}
+
+/** \brief Disable the endpoint interrupt
+ * \param[in] epn Endpoint number.
+ * \param[in] flags Interrupt flags.
+ */
+static inline void _usbd_ep_int_dis(uint8_t epn, uint32_t flags)
+{
+	hri_usbendpoint_clear_EPINTEN_reg(USB, epn, flags);
+}
+
+/** \brief Check if endpoint is control endpoint
+ * \param[in] epn Endpoint number.
+ */
+static inline bool _usbd_ep_is_ctrl(uint8_t epn)
+{
+	return (hri_usbendpoint_read_EPCFG_reg(USB, epn) == USB_D_EPCFG_CTRL);
+}
+
+/** \brief Set endpoint stall
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] st Stall status.
+ */
+static inline void _usbd_ep_set_stall(uint8_t epn, uint8_t bank_n, bool st)
+{
+	if (st) {
+		hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n));
+	} else {
+		hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n));
+	}
+}
+
+/** \brief Check if the endpoint is stalled
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \return \c true if it's stalled.
+ */
+static inline bool _usbd_ep_is_stalled(uint8_t epn, uint8_t bank_n)
+{
+	Usb *hw = USB;
+	return (hri_usbendpoint_read_EPSTATUS_reg(hw, epn) & (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n));
+}
+
+/** \brief Check if stall has been sent from the endpoint
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \return \c true if it's sent.
+ */
+static inline bool _usbd_ep_is_stall_sent(uint8_t epn, uint8_t bank_n)
+{
+	Usb *hw = USB;
+	return (hri_usbendpoint_read_EPINTFLAG_reg(hw, epn) & (USB_DEVICE_EPINTFLAG_STALL0 << bank_n));
+}
+
+/** \brief ACK endpoint STALL interrupt
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ */
+static inline void _usbd_ep_ack_stall(uint8_t epn, uint8_t bank_n)
+{
+	_usbd_ep_int_ack(epn, (USB_DEVICE_EPINTFLAG_STALL0 << bank_n));
+}
+
+/** \brief Enable/disable endpoint STALL interrupt
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] en \c true to enable, \c false to disable.
+ */
+static inline void _usbd_ep_int_stall_en(uint8_t epn, uint8_t bank_n, const bool en)
+{
+	if (en) {
+		_usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n);
+	} else {
+		_usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n);
+	}
+}
+
+/** \brief Stop SETUP transactions
+ * \param[in] epn Endpoint number.
+ */
+static inline void _usbd_ep_stop_setup(uint8_t epn)
+{
+	hri_usbendpoint_clear_EPINTEN_RXSTP_bit(USB, epn);
+}
+
+/** \brief Check if SETUP packet is ready in cache
+ * \param[in] epn Endpoint number.
+ */
+static inline bool _usbd_ep_is_setup(uint8_t epn)
+{
+	return hri_usbendpoint_get_EPINTFLAG_reg(USB, epn, USB_DEVICE_EPINTFLAG_RXSTP);
+}
+
+/** \brief ACK endpoint SETUP interrupt
+ * \param[in] epn Endpoint number.
+ */
+static inline void _usbd_ep_ack_setup(uint8_t epn)
+{
+	_usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_RXSTP);
+}
+
+/** \brief Set endpoint toggle value
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] tgl Toggle value.
+ */
+static inline void _usbd_ep_set_toggle(uint8_t epn, uint8_t bank_n, uint8_t tgl)
+{
+	if (tgl) {
+		hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n));
+	} else {
+		hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n));
+	}
+}
+
+/** \brief ACK IN/OUT complete interrupt
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ */
+static inline void _usbd_ep_ack_io_cpt(uint8_t epn, uint8_t bank_n)
+{
+	_usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_TRCPT0 << bank_n);
+}
+
+/** \brief Set DMA buffer used for bank data
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] addr DMA buffer address to set.
+ */
+static inline void _usbd_ep_set_buf(uint8_t epn, uint8_t bank_n, uint32_t addr)
+{
+	UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n];
+	bank->ADDR.reg          = addr;
+}
+
+/** \brief Set bank count for IN transactions
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] count Data count for IN.
+ */
+static inline void _usbd_ep_set_in_count(uint8_t epn, uint8_t bank_n, uint16_t count)
+{
+	UsbDeviceDescBank *bank             = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n];
+	bank->PCKSIZE.bit.MULTI_PACKET_SIZE = count;
+}
+
+/** \brief Set bank size for IN transactions
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] size Data size for IN.
+ */
+static inline void _usbd_ep_set_in_size(uint8_t epn, uint8_t bank_n, uint16_t size)
+{
+	UsbDeviceDescBank *bank      = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n];
+	bank->PCKSIZE.bit.BYTE_COUNT = size;
+}
+
+/** \brief Set bank count for OUT transaction
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] count Data count for OUT.
+ */
+static inline void _usbd_ep_set_out_count(uint8_t epn, uint8_t bank_n, uint16_t count)
+{
+	UsbDeviceDescBank *bank      = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n];
+	bank->PCKSIZE.bit.BYTE_COUNT = count;
+}
+
+/** \brief Set bank size for OUT transactions
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] size Data size for OUT.
+ */
+static inline void _usbd_ep_set_out_size(uint8_t epn, uint8_t bank_n, uint16_t size)
+{
+	UsbDeviceDescBank *bank             = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n];
+	bank->PCKSIZE.bit.MULTI_PACKET_SIZE = size;
+}
+
+/** Set bank size and count for IN transactions
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] size Data size.
+ * \param[in] count Initial data count.
+ */
+static inline void _usbd_ep_set_in_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count)
+{
+	_usbd_ep_set_in_size(epn, bank_n, size);
+	_usbd_ep_set_in_count(epn, bank_n, count);
+}
+
+/** \brief Set bank size and count for OUT transaction
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] size Data size.
+ * \param[in] count Initial data count.
+ */
+static inline void _usbd_ep_set_out_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count)
+{
+	_usbd_ep_set_out_size(epn, bank_n, size);
+	_usbd_ep_set_out_count(epn, bank_n, count);
+}
+
+/** \brief Clear bank status
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ */
+static inline void _usbd_ep_clear_bank_status(uint8_t epn, uint8_t bank_n)
+{
+	UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n];
+	bank->STATUS_BK.reg     = 0;
+}
+
+/** Set IN ready for IN transactions
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] rdy Set to \c true to indicate IN packet ready to TX.
+ */
+static inline void _usbd_ep_set_in_rdy(uint8_t epn, uint8_t bank_n, const bool rdy)
+{
+	if (rdy) {
+		hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n);
+	} else {
+		hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n);
+	}
+}
+
+/** \brief Set bank ready for OUT transactions
+ * \param[in] epn Endpoint number.
+ * \param[in] bank_n Endpoint bank number.
+ * \param[in] rdy Set to \c true to indicate OUT bank ready to RX.
+ */
+static inline void _usbd_ep_set_out_rdy(uint8_t epn, uint8_t bank_n, const bool rdy)
+{
+	if (rdy) {
+		hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n);
+	} else {
+		hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n);
+	}
+}
+
+/**
+ *  \brief Convert USB endpoint size to HW PCKSIZE.SIZE
+ * \param[in] n Number of bytes of endpoint size.
+ */
+static inline uint8_t _usbd_ep_pcksize_size(uint16_t n)
+{
+	return (
+	    (n > 512)
+	        ? 7
+	        : ((n > 256) ? 6 : ((n > 128) ? 5 : ((n > 64) ? 4 : ((n > 32) ? 3 : ((n > 16) ? 2 : ((n > 8) ? 1 : 0)))))));
+}
+
+/**
+ *  \brief Obtain endpoint descriptor pointer
+ * \param[in] epn Endpoint number.
+ * \param[in] dir Endpoint direction.
+ */
+static inline struct _usb_d_dev_ep *_usb_d_dev_ept(uint8_t epn, bool dir)
+{
+	uint8_t ep_index = (epn == 0) ? 0 : (dir ? (epn + CONF_USB_D_MAX_EP_N) : epn);
+	return &dev_inst.ep[ep_index];
+}
+
+/**
+ * \brief Handles USB SOF interrupt
+ */
+static inline void _usb_d_dev_sof(void)
+{
+	/* ACK SOF interrupt. */
+	hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_SOF);
+	dev_inst.callbacks.sof();
+}
+
+/**
+ * \brief Handles USB LPM Suspend interrupt
+ */
+static inline void _usb_d_dev_lpmsusp(void)
+{
+	uint8_t  i;
+	uint32_t lpm_variable = 0;
+
+	/* ACK LPMSUSP interrupt. */
+	hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS);
+	/* Change interrupt masks */
+	hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS);
+	hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS);
+
+	/* Find LPM data */
+	for (i = 0; i < CONF_USB_D_MAX_EP_N; i++) {
+		UsbDeviceDescBank *bank = &prvt_inst.desc_table[i].DeviceDescBank[0];
+		if (bank->EXTREG.bit.SUBPID == 0x3) {
+			/* Save LPM variable */
+			lpm_variable = bank->EXTREG.bit.VARIABLE;
+			/* Clear */
+			bank->EXTREG.reg = 0;
+			break;
+		}
+	}
+	dev_inst.callbacks.event(USB_EV_LPM_SUSPEND, lpm_variable);
+}
+
+/**
+ * \brief Handles USB RAM Error interrupt
+ */
+static inline void _usb_d_dev_ramerr(void)
+{
+	hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_RAMACER);
+	dev_inst.callbacks.event(USB_EV_ERROR, 0);
+}
+
+/**
+ * \brief Handles USB resume/wakeup interrupts
+ */
+static inline void _usb_d_dev_wakeup(void)
+{
+	hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_WAKEUP_INT_FLAGS);
+	hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS);
+	hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS);
+
+	_usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC);
+	dev_inst.callbacks.event(USB_EV_WAKEUP, 0);
+}
+
+/**
+ * \brief Handles USB signal reset interrupt
+ */
+static inline void _usb_d_dev_reset(void)
+{
+	/* EP0 will not be reseted by USB RESET, disable manually. */
+	hri_usbendpoint_write_EPCFG_reg(USB, 0, 0);
+
+	hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_EORST);
+	hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS);
+	hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS);
+
+	_usb_d_dev_reset_epts();
+	dev_inst.callbacks.event(USB_EV_RESET, 0);
+}
+
+static inline void _usb_d_dev_suspend(void)
+{
+	hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS);
+	hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS);
+	hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS);
+
+	dev_inst.callbacks.event(USB_EV_SUSPEND, 0);
+}
+
+/**
+ * \brief Handles USB non-endpoint interrupt
+ */
+static inline bool _usb_d_dev_handle_nep(void)
+{
+	bool     rc    = true;
+	uint16_t flags = hri_usbdevice_read_INTFLAG_reg(USB);
+	flags &= hri_usbdevice_read_INTEN_reg(USB);
+
+	if (flags & USB_DEVICE_INTFLAG_SOF) {
+		_usb_d_dev_sof();
+		return true;
+	}
+	if (flags & USB_DEVICE_INTFLAG_LPMSUSP) {
+		_usb_d_dev_lpmsusp();
+	} else if (flags & USB_DEVICE_INTFLAG_RAMACER) {
+		_usb_d_dev_ramerr();
+	} else if (flags & USB_D_WAKEUP_INT_FLAGS) {
+		_usb_d_dev_wakeup();
+	} else if (flags & USB_DEVICE_INTFLAG_EORST) {
+		_usb_d_dev_reset();
+	} else if (flags & USB_DEVICE_INTFLAG_SUSPEND) {
+		_usb_d_dev_suspend();
+	} else {
+		rc = false;
+	}
+	return rc;
+}
+
+/**
+ * \brief Prepare next IN transactions
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] isr Invoked from ISR.
+ */
+static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr)
+{
+	Usb *              hw          = USB;
+	uint8_t            epn         = USB_EP_GET_N(ept->ep);
+	UsbDeviceDescBank *bank        = &prvt_inst.desc_table[epn].DeviceDescBank[0];
+	uint16_t           trans_count = isr ? bank[1].PCKSIZE.bit.BYTE_COUNT : 0;
+	uint16_t           trans_next;
+	uint16_t           last_pkt = trans_count & ((ept->size == 1023) ? ept->size : (ept->size - 1));
+	uint8_t            inten    = 0;
+	bool               is_ctrl  = _usb_d_dev_ep_is_ctrl(ept);
+
+	if (isr) {
+		_usbd_ep_ack_io_cpt(epn, 1);
+	}
+
+	ept->trans_count += trans_count;
+	/* Send more data. */
+	if (ept->trans_count < ept->trans_size) {
+		trans_next = ept->trans_size - ept->trans_count;
+		if (ept->flags.bits.use_cache) {
+			if (trans_next > ept->size) {
+				trans_next = ept->size;
+			}
+			memcpy(ept->cache, &ept->trans_buf[ept->trans_count], trans_next);
+			_usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache);
+		} else {
+			if (trans_next > USB_D_DEV_TRANS_MAX) {
+				trans_next = USB_D_DEV_TRANS_MAX;
+			}
+			_usbd_ep_set_buf(epn, 1, (uint32_t)&ept->trans_buf[ept->trans_count]);
+		}
+		_usbd_ep_set_in_trans(epn, 1, trans_next, 0);
+		goto _in_tx_exec;
+	} else if (ept->flags.bits.need_zlp) {
+		ept->flags.bits.need_zlp = 0;
+		_usbd_ep_set_in_trans(epn, 1, 0, 0);
+		goto _in_tx_exec;
+	}
+	/* Complete. */
+	if (is_ctrl) {
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRCPT0);
+	} else {
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS);
+	}
+
+	/* No ping-pong, so ask more data without background transfer. */
+	if (last_pkt == ept->size) {
+		ept->flags.bits.is_busy = 0;
+		if (dev_inst.ep_callbacks.more(ept->ep, ept->trans_count)) {
+			/* More data added. */
+			return;
+		}
+		ept->flags.bits.is_busy = 1;
+	}
+	/* Finish normally. */
+	_usb_d_dev_trans_done(ept, USB_TRANS_DONE);
+	return;
+
+_in_tx_exec:
+	if (!isr) {
+		if (is_ctrl) {
+			/* Control endpoint: SETUP or OUT will abort IN transaction.
+			 * SETUP: terminate the IN without any notification. Trigger
+			 *        SETUP callback.
+			 * OUT NAK: terminate IN.
+			 */
+			inten = USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL0;
+		} else {
+			/* Initialize normal IN transaction. */
+			inten = USB_D_BANK1_INT_FLAGS;
+		}
+		hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten);
+	}
+	_usbd_ep_set_in_rdy(epn, 1, true);
+}
+
+/**
+ * \brief Prepare next OUT transactions
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] isr Invoked from ISR.
+ */
+static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr)
+{
+	Usb *              hw         = USB;
+	uint8_t            epn        = USB_EP_GET_N(ept->ep);
+	UsbDeviceDescBank *bank       = &prvt_inst.desc_table[epn].DeviceDescBank[0];
+	uint16_t           trans_size = isr ? bank->PCKSIZE.bit.MULTI_PACKET_SIZE : 0;
+	uint16_t           last_trans = isr ? bank->PCKSIZE.bit.BYTE_COUNT : 0;
+	uint16_t           size_mask  = (ept->size == 1023) ? 1023 : (ept->size - 1);
+	uint16_t           last_pkt   = last_trans & size_mask;
+	uint16_t           trans_next;
+	uint8_t            inten;
+	bool               is_ctrl = _usb_d_dev_ep_is_ctrl(ept);
+
+	if (isr) {
+		_usbd_ep_ack_io_cpt(epn, 0);
+	}
+
+	/* If cache is used, copy data to buffer. */
+	if (ept->flags.bits.use_cache && ept->trans_size) {
+		uint16_t buf_remain = ept->trans_size - ept->trans_count;
+		memcpy(&ept->trans_buf[ept->trans_count], ept->cache, (buf_remain > last_pkt) ? last_pkt : buf_remain);
+	}
+
+	/* Force wait ZLP */
+	if (ept->trans_size == 0 && ept->flags.bits.need_zlp) {
+		ept->flags.bits.need_zlp  = 0;
+		ept->flags.bits.use_cache = 1;
+		_usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache);
+		_usbd_ep_set_out_trans(epn, 0, ept->size, 0);
+		goto _out_rx_exec;
+	} else if (isr && last_pkt < ept->size) {
+		/* Short packet. */
+		ept->flags.bits.need_zlp = 0;
+		ept->trans_count += last_trans;
+	} else {
+		/* Full packets. */
+		ept->trans_count += trans_size;
+
+		/* Wait more data */
+		if (ept->trans_count < ept->trans_size) {
+			/* Continue OUT */
+			trans_next = ept->trans_size - ept->trans_count;
+			if (ept->flags.bits.use_cache) {
+				/* Expect single packet each time. */
+				if (trans_next > ept->size) {
+					trans_next = ept->size;
+				}
+				_usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache);
+			} else {
+				/* Multiple packets each time. */
+				if (trans_next > ept->size) {
+					if (trans_next > USB_D_DEV_TRANS_MAX) {
+						trans_next = USB_D_DEV_TRANS_MAX;
+					} else {
+						/* Must expect multiple of ep size. */
+						trans_next -= trans_next & size_mask;
+					}
+				} else if (trans_next < ept->size) {
+					/* Last un-aligned packet should be cached. */
+					ept->flags.bits.use_cache = 1;
+				}
+				_usbd_ep_set_buf(epn, 0, (uint32_t)&ept->trans_buf[ept->trans_count]);
+			}
+			_usbd_ep_set_out_trans(epn, 0, trans_next, 0);
+			goto _out_rx_exec;
+		}
+	}
+	/* Finish normally. */
+	if (is_ctrl) {
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1);
+	} else {
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS);
+	}
+	/* Use ep0 out cache for next setup packets */
+	if (0 == epn) {
+		_usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache);
+	}
+	_usb_d_dev_trans_done(ept, USB_TRANS_DONE);
+	return;
+
+_out_rx_exec:
+	if (!isr) {
+		if (is_ctrl) {
+			/* Initialize control OUT transaction. */
+
+			/* Control transfer: SETUP or IN request will abort the
+			 *                   OUT transactions.
+			 * SETUP: terminate OUT without any notification.
+			 *        Trigger SETUP notification.
+			 * IN NAK: finish OUT normally. Notify data done.
+			 */
+			_usbd_ep_clear_bank_status(epn, 1);
+			/* Detect OUT, SETUP, NAK IN */
+			inten = USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1;
+		} else {
+			/* Initialize normal OUT transaction. */
+			inten = USB_D_BANK0_INT_FLAGS;
+		}
+		hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten);
+	}
+	_usbd_ep_set_out_rdy(epn, 0, true);
+}
+
+/**
+ * \brief Handles setup received interrupt
+ * \param[in] ept Pointer to endpoint information.
+ */
+static void _usb_d_dev_handle_setup(struct _usb_d_dev_ep *ept)
+{
+	uint8_t epn     = USB_EP_GET_N(ept->ep);
+	bool    is_ctrl = _usb_d_dev_ep_is_ctrl(ept);
+
+	if (!is_ctrl) {
+		/* Should never be here! */
+		_usbd_ep_ack_setup(epn);
+		_usbd_ep_stop_setup(epn);
+		return;
+	}
+	/* Control transfer:
+	 * SETUP transaction will terminate IN/OUT transaction,
+	 * and start new transaction with received SETUP packet.
+	 */
+	if (_usb_d_dev_ep_is_busy(ept)) {
+		ept->flags.bits.is_busy = 0;
+
+		/* Stop transfer on either direction. */
+		_usbd_ep_set_in_rdy(epn, 1, false);
+		_usbd_ep_set_out_rdy(epn, 0, false);
+	}
+	ept->flags.bits.is_stalled = 0;
+
+	/* Clear status and notify SETUP */
+	_usbd_ep_clear_bank_status(epn, 0);
+	_usbd_ep_clear_bank_status(epn, 1);
+	_usbd_ep_int_ack(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS);
+	_usbd_ep_int_dis(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS);
+	/* Invoke callback. */
+	dev_inst.ep_callbacks.setup(ept->ep);
+}
+
+/**
+ * \brief Handles stall sent interrupt
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] bank_n Bank number.
+ */
+static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t bank_n)
+{
+	uint8_t epn = USB_EP_GET_N(ept->ep);
+	/* Clear interrupt enable. Leave status there for status check. */
+	_usbd_ep_int_stall_en(epn, bank_n, false);
+	dev_inst.ep_callbacks.done(ept->ep, USB_TRANS_STALL, ept->trans_count);
+}
+
+/**
+ * \brief Handles transaction fail interrupt
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] bank_n Bank number.
+ */
+static void _usb_d_dev_handle_trfail(struct _usb_d_dev_ep *ept, const uint8_t bank_n)
+{
+	Usb *              hw      = USB;
+	uint8_t            epn     = USB_EP_GET_N(ept->ep);
+	const uint8_t      fail[2] = {USB_DEVICE_EPINTFLAG_TRFAIL0, USB_DEVICE_EPINTFLAG_TRFAIL1};
+	UsbDeviceDescBank *bank    = prvt_inst.desc_table[epn].DeviceDescBank;
+	uint8_t            eptype
+	    = bank_n ? hri_usbendpoint_read_EPCFG_EPTYPE1_bf(hw, epn) : hri_usbendpoint_read_EPCFG_EPTYPE0_bf(hw, epn);
+	bool                      is_ctrl = _usb_d_dev_ep_is_ctrl(ept);
+	USB_DEVICE_STATUS_BK_Type st;
+	st.reg = bank[bank_n].STATUS_BK.reg;
+
+	if ((eptype == USB_D_EPTYPE_ISOCH) && st.bit.CRCERR) {
+		bank[bank_n].STATUS_BK.bit.CRCERR = 0;
+		hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]);
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]);
+		_usb_d_dev_trans_stop(ept, bank_n, USB_TRANS_ERROR);
+	} else if (st.bit.ERRORFLOW) {
+		bank[bank_n].STATUS_BK.bit.ERRORFLOW = 0;
+		hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]);
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]);
+		/* Abort control transfer. */
+		if (is_ctrl && _usb_d_dev_ep_is_busy(ept)) {
+			if (bank_n != _usb_d_dev_ep_is_in(ept)) {
+				_usb_d_dev_trans_stop(ept, _usb_d_dev_ep_is_in(ept), USB_TRANS_DONE);
+			}
+		}
+	} else {
+		_usbd_ep_clear_bank_status(epn, bank_n);
+		hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]);
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]);
+	}
+}
+
+/**
+ * \brief Analyze flags for setup transaction
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] flags Endpoint interrupt flags.
+ */
+static inline void _usb_d_dev_trans_setup_isr(struct _usb_d_dev_ep *ept, const uint8_t flags)
+{
+	/*
+	 * SETPU is automatically ACKed by hardware
+	 * OUT & IN should be set to NAK when checking SETUP
+	 * No need to check OUT & IN status.
+	 */
+	if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
+		_usb_d_dev_handle_setup(ept);
+	} else if (flags & USB_DEVICE_EPINTFLAG_STALL1) {
+		_usb_d_dev_handle_stall(ept, 1);
+	} else if (flags & USB_DEVICE_EPINTFLAG_STALL0) {
+		_usb_d_dev_handle_stall(ept, 0);
+	}
+}
+
+/**
+ * \brief Analyze flags for IN transactions
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] flags Endpoint interrupt flags.
+ */
+static inline void _usb_d_dev_trans_in_isr(struct _usb_d_dev_ep *ept, const uint8_t flags)
+{
+	/*
+	 * Check IN flags
+	 * If control endpoint, SETUP & OUT is checked to see if abort
+	 */
+	if (flags & USB_DEVICE_EPINTFLAG_STALL1) {
+		_usb_d_dev_handle_stall(ept, 1);
+	} else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) {
+		_usb_d_dev_handle_trfail(ept, 1);
+	} else if (flags & USB_DEVICE_EPINTFLAG_TRCPT1) {
+		_usb_d_dev_in_next(ept, true);
+	} else if (_usb_d_dev_ep_is_ctrl(ept)) {
+		/* Check OUT NAK
+		 * Check SETUP
+		 */
+		if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) {
+			_usb_d_dev_handle_trfail(ept, 0);
+		} else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
+			_usb_d_dev_handle_setup(ept);
+		}
+	}
+}
+
+/**
+ * \brief Analyze flags for OUT transactions
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] flags Endpoint interrupt flags.
+ */
+static inline void _usb_d_dev_trans_out_isr(struct _usb_d_dev_ep *ept, const uint8_t flags)
+{
+	/*
+	 * Check OUT flags.
+	 * If control endpoint, SETUP & IN NAK is checked to see if abort
+	 */
+	if (flags & USB_DEVICE_EPINTFLAG_STALL0) {
+		_usb_d_dev_handle_stall(ept, 0);
+	} else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) {
+		_usb_d_dev_handle_trfail(ept, 0);
+	} else if (flags & USB_DEVICE_EPINTFLAG_TRCPT0) {
+		_usb_d_dev_out_next(ept, true);
+	} else if (_usb_d_dev_ep_is_ctrl(ept)) {
+		/* Check IN NAK
+		 * Check SETUP
+		 */
+		if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) {
+			_usb_d_dev_handle_trfail(ept, 1);
+		} else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
+			_usb_d_dev_handle_setup(ept);
+		}
+	}
+}
+
+/**
+ * \brief Handles the endpoint interrupts.
+ * \param[in] epint Endpoint interrupt summary (by bits).
+ * \param[in] ept Pointer to endpoint information.
+ */
+static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *ept)
+{
+	Usb *hw = USB;
+
+	uint8_t flags, mask;
+	uint8_t epn = USB_EP_GET_N(ept->ep);
+
+	if (!(epint & (1u << epn))) {
+		return;
+	}
+	flags = hw->DEVICE.DeviceEndpoint[epn].EPINTFLAG.reg;
+	mask  = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg;
+	flags &= mask;
+	if (flags) {
+		if ((ept->flags.bits.eptype == 0x1) && !_usb_d_dev_ep_is_busy(ept)) {
+			_usb_d_dev_trans_setup_isr(ept, flags);
+		} else if (_usb_d_dev_ep_is_in(ept)) {
+			_usb_d_dev_trans_in_isr(ept, flags);
+		} else {
+			_usb_d_dev_trans_out_isr(ept, flags);
+		}
+	}
+}
+
+/**
+ * \brief USB device interrupt handler
+ * \param[in] unused The parameter is not used
+ */
+static void _usb_d_dev_handler(void)
+{
+	Usb *   hw = USB;
+	uint8_t i;
+
+	uint16_t epint = hw->DEVICE.EPINTSMRY.reg;
+	if (0 == epint) {
+		if (_usb_d_dev_handle_nep()) {
+			return;
+		}
+	}
+	/* Handle endpoints */
+	for (i = 0; i < USB_D_N_EP; i++) {
+		struct _usb_d_dev_ep *ept = &dev_inst.ep[i];
+		if (ept->ep == 0xFF) {
+			continue;
+		}
+		_usb_d_dev_handle_eps(epint, ept);
+	}
+}
+
+/**
+ * \brief Reset all endpoint software instances
+ */
+static void _usb_d_dev_reset_epts(void)
+{
+	uint8_t i;
+	for (i = 0; i < USB_D_N_EP; i++) {
+		_usb_d_dev_trans_done(&dev_inst.ep[i], USB_TRANS_RESET);
+		dev_inst.ep[i].ep       = 0xFF;
+		dev_inst.ep[i].flags.u8 = 0;
+	}
+	memset(prvt_inst.desc_table, 0, sizeof(UsbDeviceDescriptor) * (CONF_USB_D_MAX_EP_N + 1));
+}
+
+int32_t _usb_d_dev_init(void)
+{
+	Usb *         hw         = USB;
+	uint8_t       speed      = CONF_USB_D_SPEED;
+	const uint8_t spdconf[4] = {
+	    USB_DEVICE_CTRLB_SPDCONF(1), /* LS */
+	    USB_DEVICE_CTRLB_SPDCONF(0), /* FS */
+	    0,
+	    0 /* Reserved */
+	};
+
+	if (!hri_usbdevice_is_syncing(hw, USB_SYNCBUSY_SWRST)) {
+		if (hri_usbdevice_get_CTRLA_reg(hw, USB_CTRLA_ENABLE)) {
+			hri_usbdevice_clear_CTRLA_ENABLE_bit(hw);
+			hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_ENABLE);
+		}
+		hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_SWRST);
+	}
+	hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+
+	dev_inst.callbacks.sof   = (_usb_d_dev_sof_cb_t)_dummy_func_no_return;
+	dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)_dummy_func_no_return;
+
+	dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)_dummy_func_no_return;
+	dev_inst.ep_callbacks.more  = (_usb_d_dev_ep_cb_more_t)_dummy_func_no_return;
+	dev_inst.ep_callbacks.done  = (_usb_d_dev_ep_cb_done_t)_dummy_func_no_return;
+
+	_usb_d_dev_reset_epts();
+
+	_usb_load_calib();
+
+	hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_RUNSTDBY);
+	hri_usbdevice_write_DESCADD_reg(hw, (uint32_t)prvt_inst.desc_table);
+	hri_usbdevice_write_CTRLB_reg(hw, spdconf[speed] | USB_DEVICE_CTRLB_DETACH);
+
+	return ERR_NONE;
+}
+
+void _usb_d_dev_deinit(void)
+{
+	Usb *hw = USB;
+
+	while (_usb_d_dev_disable() < 0)
+		;
+
+	hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_SWRST);
+
+	NVIC_DisableIRQ(USB_0_IRQn);
+	NVIC_ClearPendingIRQ(USB_0_IRQn);
+	NVIC_DisableIRQ(USB_1_IRQn);
+	NVIC_ClearPendingIRQ(USB_1_IRQn);
+	NVIC_DisableIRQ(USB_2_IRQn);
+	NVIC_ClearPendingIRQ(USB_2_IRQn);
+	NVIC_DisableIRQ(USB_3_IRQn);
+	NVIC_ClearPendingIRQ(USB_3_IRQn);
+}
+
+int32_t _usb_d_dev_enable(void)
+{
+	Usb *   hw = USB;
+	uint8_t ctrla;
+
+	if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) {
+		return -USB_ERR_DENIED;
+	}
+	ctrla = hri_usbdevice_read_CTRLA_reg(hw);
+	if ((ctrla & USB_CTRLA_ENABLE) == 0) {
+		hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE);
+	}
+
+	NVIC_EnableIRQ(USB_0_IRQn);
+	NVIC_EnableIRQ(USB_1_IRQn);
+	NVIC_EnableIRQ(USB_2_IRQn);
+	NVIC_EnableIRQ(USB_3_IRQn);
+
+	hri_usbdevice_set_INTEN_reg(hw,
+	                            USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER
+	                                | USB_D_SUSPEND_INT_FLAGS);
+
+	return ERR_NONE;
+}
+
+int32_t _usb_d_dev_disable(void)
+{
+	Usb *   hw = USB;
+	uint8_t ctrla;
+
+	if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) {
+		return -USB_ERR_DENIED;
+	}
+
+	ctrla = hri_usbdevice_read_CTRLA_reg(hw);
+	if (ctrla & USB_CTRLA_ENABLE) {
+		hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE);
+	}
+
+	NVIC_DisableIRQ(USB_0_IRQn);
+	NVIC_DisableIRQ(USB_1_IRQn);
+	NVIC_DisableIRQ(USB_2_IRQn);
+	NVIC_DisableIRQ(USB_3_IRQn);
+
+	hri_usbdevice_clear_INTEN_reg(hw,
+	                              USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER
+	                                  | USB_D_SUSPEND_INT_FLAGS | USB_D_WAKEUP_INT_FLAGS);
+
+	return ERR_NONE;
+}
+
+void _usb_d_dev_attach(void)
+{
+	hri_usbdevice_clear_CTRLB_DETACH_bit(USB);
+}
+
+void _usb_d_dev_detach(void)
+{
+	hri_usbdevice_set_CTRLB_DETACH_bit(USB);
+}
+
+#ifndef USB_FSMSTATUS_FSMSTATE_ON
+#define USB_FSMSTATUS_FSMSTATE_ON USB_FSMSTATUS_FSMSTATE(2ul)
+#endif
+void _usb_d_dev_send_remotewakeup(void)
+{
+	uint32_t retry = CONF_USB_RMT_WKUP_RETRY;
+	_usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC);
+	while ((USB_FSMSTATUS_FSMSTATE_ON != hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(USB)) && (retry--)) {
+		USB->DEVICE.CTRLB.bit.UPRSM = 1;
+	}
+}
+
+enum usb_speed _usb_d_dev_get_speed(void)
+{
+	uint8_t              sp       = (enum usb_speed)hri_usbdevice_read_STATUS_SPEED_bf(USB);
+	const enum usb_speed speed[2] = {USB_SPEED_FS, USB_SPEED_LS};
+
+	return speed[sp];
+}
+
+void _usb_d_dev_set_address(uint8_t addr)
+{
+	hri_usbdevice_write_DADD_reg(USB, USB_DEVICE_DADD_ADDEN | USB_DEVICE_DADD_DADD(addr));
+}
+
+uint8_t _usb_d_dev_get_address(void)
+{
+	uint8_t addr = hri_usbdevice_read_DADD_DADD_bf(USB);
+	return addr;
+}
+
+uint16_t _usb_d_dev_get_frame_n(void)
+{
+	uint16_t fn = hri_usbdevice_read_FNUM_FNUM_bf(USB);
+	return fn;
+}
+
+uint8_t _usb_d_dev_get_uframe_n(void)
+{
+	uint8_t ufn = hri_usbdevice_read_FNUM_MFNUM_bf(USB);
+	return ufn;
+}
+
+/**
+ *  \brief Start a setup transaction
+ *  \param[in] ept Endpoint information.
+ */
+static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept)
+{
+	Usb *   hw  = USB;
+	uint8_t epn = USB_EP_GET_N(ept->ep);
+
+	_usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache);
+	_usbd_ep_set_out_trans(epn, 0, ept->size, 0);
+
+	hri_usbendpoint_clear_EPSTATUS_reg(hw, epn, USB_DEVICE_EPSTATUS_STALLRQ(0x3) | USB_DEVICE_EPSTATUS_BK1RDY);
+	_usbd_ep_set_out_rdy(epn, 0, false);
+
+	hri_usbendpoint_set_EPINTEN_reg(hw, epn, USB_D_SETUP_INT_FLAGS);
+}
+
+int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz)
+{
+	return _usb_d_dev_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_siz);
+}
+
+int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_siz)
+{
+	uint8_t               epn = USB_EP_GET_N(ep);
+	bool                  dir = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+
+	uint8_t                        ep_type = attr & USB_EP_XTYPE_MASK;
+	const struct _usb_ep_cfg_item *pcfg    = &_usb_ep_cfgs[epn];
+
+	if (epn > CONF_USB_D_MAX_EP_N) {
+		return -USB_ERR_PARAM;
+	}
+	if (ept->ep != 0xFF) {
+		return -USB_ERR_REDO;
+	}
+	if (ep_type == USB_EP_XTYPE_CTRL) {
+		struct _usb_d_dev_ep *ept_in = _usb_d_dev_ept(epn, !dir);
+		if (ept_in->ep != 0xFF) {
+			return -USB_ERR_REDO;
+		}
+		if (pcfg->cache == NULL) {
+			return -USB_ERR_FUNC;
+		}
+	}
+	if ((dir ? pcfg->i_cache : pcfg->cache) && ((dir ? pcfg->i_size : pcfg->size) < max_pkt_siz)) {
+		return -USB_ERR_FUNC;
+	}
+
+	/* Initialize EP n settings */
+	ept->cache    = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache);
+	ept->size     = max_pkt_siz;
+	ept->flags.u8 = (ep_type + 1);
+	ept->ep       = ep;
+
+	return USB_OK;
+}
+
+void _usb_d_dev_ep_deinit(uint8_t ep)
+{
+	Usb *                 hw  = USB;
+	uint8_t               epn = USB_EP_GET_N(ep);
+	bool                  dir = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+
+	if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) {
+		return;
+	}
+
+	/* Finish pending transactions. */
+	_usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET);
+
+	/* Disable the endpoint. */
+	if (_usb_d_dev_ep_is_ctrl(ept)) {
+		hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg = 0;
+	} else if (USB_EP_GET_DIR(ep)) {
+		hw->DEVICE.DeviceEndpoint[USB_EP_GET_N(ep)].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	} else {
+		hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	}
+	ept->flags.u8 = 0;
+	ept->ep       = 0xFF;
+}
+
+int32_t _usb_d_dev_ep_enable(const uint8_t ep)
+{
+	Usb *                 hw    = USB;
+	uint8_t               epn   = USB_EP_GET_N(ep);
+	bool                  dir   = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept   = _usb_d_dev_ept(epn, dir);
+	uint8_t               epcfg = hri_usbendpoint_read_EPCFG_reg(hw, epn);
+	UsbDeviceDescBank *   bank;
+
+	if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) {
+		return -USB_ERR_PARAM;
+	}
+
+	bank = prvt_inst.desc_table[epn].DeviceDescBank;
+	if (ept->flags.bits.eptype == USB_D_EPTYPE_CTRL) {
+		if (epcfg & (USB_DEVICE_EPCFG_EPTYPE1_Msk | USB_DEVICE_EPCFG_EPTYPE0_Msk)) {
+			return -USB_ERR_REDO;
+		}
+		hri_usbendpoint_write_EPCFG_reg(hw, epn, USB_D_EPCFG_CTRL);
+		bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size)
+		                      | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size));
+		bank[1].PCKSIZE.reg
+		    = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size));
+		/* By default, control endpoint accept SETUP and NAK all other token. */
+		_usbd_ep_set_out_rdy(epn, 0, false);
+		_usbd_ep_set_in_rdy(epn, 1, false);
+
+		_usbd_ep_clear_bank_status(epn, 0);
+		_usbd_ep_clear_bank_status(epn, 1);
+
+		/* Enable SETUP reception for control endpoint. */
+		_usb_d_dev_trans_setup(ept);
+
+	} else if (dir) {
+		if (epcfg & USB_DEVICE_EPCFG_EPTYPE1_Msk) {
+			return -USB_ERR_REDO;
+		}
+		epcfg |= USB_DEVICE_EPCFG_EPTYPE1(ept->flags.bits.eptype);
+		hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg);
+
+		bank[1].PCKSIZE.reg
+		    = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size));
+
+		/* By default, IN endpoint will NAK all token. */
+		_usbd_ep_set_in_rdy(epn, 1, false);
+		_usbd_ep_clear_bank_status(epn, 1);
+
+	} else {
+
+		if (epcfg & USB_DEVICE_EPCFG_EPTYPE0_Msk) {
+			return -USB_ERR_REDO;
+		}
+		epcfg |= USB_DEVICE_EPCFG_EPTYPE0(ept->flags.bits.eptype);
+		hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg);
+
+		bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size)
+		                      | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size));
+
+		/* By default, OUT endpoint will NAK all token. */
+		_usbd_ep_set_out_rdy(epn, 0, false);
+		_usbd_ep_clear_bank_status(epn, 0);
+	}
+
+	return USB_OK;
+}
+
+void _usb_d_dev_ep_disable(const uint8_t ep)
+{
+	Usb *                 hw  = USB;
+	uint8_t               epn = USB_EP_GET_N(ep);
+	bool                  dir = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+
+	_usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET);
+	if (_usb_d_dev_ep_is_ctrl(ept)) {
+		hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_ALL_INT_FLAGS);
+	}
+}
+
+/**
+ * \brief Get endpoint stall status
+ * \param[in] ept Pointer to endpoint information.
+ * \param[in] dir Endpoint direction.
+ * \return Stall status.
+ * \retval \c true Endpoint is stalled.
+ * \retval \c false Endpoint is not stalled.
+ */
+static inline int32_t _usb_d_dev_ep_stall_get(struct _usb_d_dev_ep *ept, bool dir)
+{
+	uint8_t epn = USB_EP_GET_N(ept->ep);
+	return _usbd_ep_is_stalled(epn, dir);
+}
+
+/**
+ * \brief Set endpoint stall
+ * \param[in, out] ept Pointer to endpoint information.
+ * \param[in] dir Endpoint direction.
+ * \return Always 0, success.
+ */
+static inline int32_t _usb_d_dev_ep_stall_set(struct _usb_d_dev_ep *ept, bool dir)
+{
+	uint8_t epn = USB_EP_GET_N(ept->ep);
+	_usbd_ep_set_stall(epn, dir, true);
+	_usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir);
+	ept->flags.bits.is_stalled = 1;
+	/* In stall interrupt abort the transfer. */
+	return ERR_NONE;
+}
+
+/**
+ * \brief Clear endpoint stall
+ * \param[in, out] ept Pointer to endpoint information.
+ * \param[in] dir Endpoint direction.
+ * \return Always 0, success.
+ */
+static inline int32_t _usb_d_dev_ep_stall_clr(struct _usb_d_dev_ep *ept, bool dir)
+{
+	uint8_t epn        = USB_EP_GET_N(ept->ep);
+	bool    is_stalled = _usbd_ep_is_stalled(epn, dir);
+	if (!is_stalled) {
+		return ERR_NONE;
+	}
+	_usbd_ep_set_stall(epn, dir, false);
+	_usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir);
+	if (_usbd_ep_is_stall_sent(epn, dir)) {
+		_usbd_ep_ack_stall(epn, dir);
+		_usbd_ep_set_toggle(epn, dir, 0);
+	}
+	if (_usb_d_dev_ep_is_ctrl(ept)) {
+		if ((hri_usbendpoint_read_EPSTATUS_reg(USB, epn) & USB_DEVICE_EPSTATUS_STALLRQ_Msk) == 0) {
+			ept->flags.bits.is_stalled = 0;
+		}
+	} else {
+		ept->flags.bits.is_stalled = 0;
+	}
+	return ERR_NONE;
+}
+
+int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl)
+{
+	uint8_t               epn = USB_EP_GET_N(ep);
+	bool                  dir = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+	int32_t               rc;
+
+	if (epn > CONF_USB_D_MAX_EP_N) {
+		return -USB_ERR_PARAM;
+	}
+
+	if (USB_EP_STALL_SET == ctrl) {
+		rc = _usb_d_dev_ep_stall_set(ept, dir);
+	} else if (USB_EP_STALL_CLR == ctrl) {
+		rc = _usb_d_dev_ep_stall_clr(ept, dir);
+	} else {
+		rc = _usb_d_dev_ep_stall_get(ept, dir);
+	}
+	return rc;
+}
+
+/**
+ *  \brief Finish the transaction and invoke callback
+ * \param[in, out] ept Pointer to endpoint information.
+ * \param[in] code Information code passed.
+ */
+static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t code)
+{
+	if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) {
+		return;
+	}
+	ept->flags.bits.is_busy = 0;
+	dev_inst.ep_callbacks.done(ept->ep, code, ept->trans_count);
+}
+
+/**
+ *  \brief Terminate the transaction with specific status code
+ * \param[in, out] ept Pointer to endpoint information.
+ * \param[in] dir Endpoint direction.
+ * \param[in] code Information code passed.
+ */
+static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code)
+{
+	uint8_t epn = USB_EP_GET_N(ept->ep);
+	;
+	const uint8_t intflags[2] = {USB_D_BANK0_INT_FLAGS, USB_D_BANK1_INT_FLAGS};
+	if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) {
+		return;
+	}
+	/* Stop transfer */
+	if (dir) {
+		/* NAK IN */
+		_usbd_ep_set_in_rdy(epn, 1, false);
+	} else {
+		/* NAK OUT */
+		_usbd_ep_set_out_rdy(epn, 0, false);
+	}
+	_usbd_ep_int_ack(epn, intflags[dir]);
+	_usbd_ep_int_dis(epn, intflags[dir]);
+	_usb_d_dev_trans_done(ept, code);
+}
+
+int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf)
+{
+	uint8_t            epn   = USB_EP_GET_N(ep);
+	UsbDeviceDescBank *bank  = prvt_inst.desc_table[epn].DeviceDescBank;
+	uint32_t           addr  = bank[0].ADDR.reg;
+	uint16_t           bytes = bank[0].PCKSIZE.bit.BYTE_COUNT;
+
+	if (epn > CONF_USB_D_MAX_EP_N || !req_buf) {
+		return -USB_ERR_PARAM;
+	}
+	if (!_usbd_ep_is_ctrl(epn)) {
+		return -USB_ERR_FUNC;
+	}
+	if (!_usbd_ep_is_setup(epn)) {
+		return ERR_NONE;
+	}
+	memcpy(req_buf, (void *)addr, 8);
+	_usbd_ep_ack_setup(epn);
+
+	return bytes;
+}
+
+int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans)
+{
+	uint8_t               epn = USB_EP_GET_N(trans->ep);
+	bool                  dir = USB_EP_GET_DIR(trans->ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+
+	uint16_t size_mask      = (ept->size == 1023) ? 1023 : (ept->size - 1);
+	bool     size_n_aligned = (trans->size & size_mask);
+
+	bool use_cache = false;
+
+	volatile hal_atomic_t flags;
+
+	if (epn > CONF_USB_D_MAX_EP_N) {
+		return -USB_ERR_PARAM;
+	}
+
+	/* Cases that needs cache:
+	 * 1. Buffer not in RAM (cache all).
+	 * 2. IN/OUT with unaligned buffer (cache all).
+	 * 3. OUT with unaligned packet size (cache last packet).
+	 * 4. OUT size < 8 (sub-case for 3).
+	 */
+	if (!_usb_is_addr4dma(trans->buf, trans->size) || (!_usb_is_aligned(trans->buf))
+	    || (!dir && (trans->size < ept->size))) {
+		if (!ept->cache) {
+			return -USB_ERR_FUNC;
+		}
+		/* Use cache all the time. */
+		use_cache = true;
+	}
+	if (!dir && size_n_aligned) {
+		if (!ept->cache) {
+			return -USB_ERR_PARAM;
+		}
+		/* Set 'use_cache' on last packet. */
+	}
+
+	/* Check halt */
+	if (ept->flags.bits.is_stalled) {
+		return USB_HALTED;
+	}
+
+	/* Try to start transactions. */
+
+	atomic_enter_critical(&flags);
+	if (_usb_d_dev_ep_is_busy(ept)) {
+		atomic_leave_critical(&flags);
+		return USB_BUSY;
+	}
+	ept->flags.bits.is_busy = 1;
+	atomic_leave_critical(&flags);
+
+	/* Copy transaction information. */
+	ept->trans_buf   = trans->buf;
+	ept->trans_size  = trans->size;
+	ept->trans_count = 0;
+
+	ept->flags.bits.dir       = dir;
+	ept->flags.bits.use_cache = use_cache;
+	ept->flags.bits.need_zlp  = (trans->zlp && (!size_n_aligned));
+
+	if (dir) {
+		_usb_d_dev_in_next(ept, false);
+	} else {
+		_usb_d_dev_out_next(ept, false);
+	}
+
+	return ERR_NONE;
+}
+
+void _usb_d_dev_ep_abort(const uint8_t ep)
+{
+	uint8_t               epn = USB_EP_GET_N(ep);
+	bool                  dir = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+	if (epn > CONF_USB_D_MAX_EP_N) {
+		return;
+	}
+	_usb_d_dev_trans_stop(ept, dir, USB_TRANS_ABORT);
+}
+
+int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat)
+{
+	uint8_t               epn = USB_EP_GET_N(ep);
+	bool                  dir = USB_EP_GET_DIR(ep);
+	struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir);
+	bool                  busy, stall;
+
+	if (epn > CONF_USB_D_MAX_EP_N) {
+		return USB_ERR_PARAM;
+	}
+	busy  = ept->flags.bits.is_busy;
+	stall = ept->flags.bits.is_stalled;
+	if (stat) {
+		stat->stall = stall;
+		stat->busy  = busy;
+		stat->setup = USB->DEVICE.DeviceEndpoint[epn].EPINTFLAG.bit.RXSTP;
+		stat->dir   = ept->flags.bits.dir;
+		stat->size  = ept->trans_size;
+		stat->count = ept->trans_count;
+		stat->ep    = ep;
+		stat->xtype = ept->flags.bits.eptype - 1;
+	}
+	if (stall) {
+		return USB_HALTED;
+	}
+	if (busy) {
+		return USB_BUSY;
+	}
+	return USB_OK;
+}
+
+void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func)
+{
+	FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func;
+	if (type == USB_D_CB_EVENT) {
+		dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)f;
+	} else if (type == USB_D_CB_SOF) {
+		dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)f;
+	}
+}
+
+void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func)
+{
+	FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func;
+	if (type == USB_D_DEV_EP_CB_SETUP) {
+		dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)f;
+	} else if (type == USB_D_DEV_EP_CB_MORE) {
+		dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)f;
+	} else if (type == USB_D_DEV_EP_CB_DONE) {
+		dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)f;
+	}
+}
+
+/**
+ * \brief USB interrupt handler
+ */
+void USB_0_Handler(void)
+{
+
+	_usb_d_dev_handler();
+}
+/**
+ * \brief USB interrupt handler
+ */
+void USB_1_Handler(void)
+{
+
+	_usb_d_dev_handler();
+}
+/**
+ * \brief USB interrupt handler
+ */
+void USB_2_Handler(void)
+{
+
+	_usb_d_dev_handler();
+}
+/**
+ * \brief USB interrupt handler
+ */
+void USB_3_Handler(void)
+{
+
+	_usb_d_dev_handler();
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ac_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ac_e53.h
new file mode 100644
index 000000000..a7e8a5f15
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ac_e53.h
@@ -0,0 +1,1836 @@
+/**
+ * \file
+ *
+ * \brief SAM AC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_AC_COMPONENT_
+#ifndef _HRI_AC_E53_H_INCLUDED_
+#define _HRI_AC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AC_CRITICAL_SECTIONS)
+#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AC_CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_ac_calib_reg_t;
+typedef uint16_t hri_ac_evctrl_reg_t;
+typedef uint32_t hri_ac_compctrl_reg_t;
+typedef uint32_t hri_ac_syncbusy_reg_t;
+typedef uint8_t  hri_ac_ctrla_reg_t;
+typedef uint8_t  hri_ac_ctrlb_reg_t;
+typedef uint8_t  hri_ac_dbgctrl_reg_t;
+typedef uint8_t  hri_ac_intenset_reg_t;
+typedef uint8_t  hri_ac_intflag_reg_t;
+typedef uint8_t  hri_ac_scaler_reg_t;
+typedef uint8_t  hri_ac_statusa_reg_t;
+typedef uint8_t  hri_ac_statusb_reg_t;
+typedef uint8_t  hri_ac_winctrl_reg_t;
+
+static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	while (((Ac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	((Ac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+}
+
+static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+}
+
+static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+}
+
+static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+}
+
+static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+}
+
+static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+}
+
+static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
+{
+	((Ac *)hw)->INTENSET.reg = data;
+	((Ac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_ENABLE;
+	tmp |= value << AC_CTRLA_ENABLE_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO0;
+	tmp |= value << AC_EVCTRL_COMPEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO1;
+	tmp |= value << AC_EVCTRL_COMPEO1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_WINEO0;
+	tmp |= value << AC_EVCTRL_WINEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI0;
+	tmp |= value << AC_EVCTRL_COMPEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI1;
+	tmp |= value << AC_EVCTRL_COMPEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI0;
+	tmp |= value << AC_EVCTRL_INVEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI1;
+	tmp |= value << AC_EVCTRL_INVEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= ~AC_DBGCTRL_DBGRUN;
+	tmp |= value << AC_DBGCTRL_DBGRUN_Pos;
+	((Ac *)hw)->DBGCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WEN0;
+	tmp |= value << AC_WINCTRL_WEN0_Pos;
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
+	tmp |= AC_WINCTRL_WINTSEL0(data);
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	return ((Ac *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
+                                                             hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= ~AC_SCALER_VALUE_Msk;
+	tmp |= AC_SCALER_VALUE(data);
+	((Ac *)hw)->SCALER[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->SCALER[index].reg;
+}
+
+static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_ENABLE;
+	tmp |= value << AC_COMPCTRL_ENABLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SINGLE;
+	tmp |= value << AC_COMPCTRL_SINGLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_RUNSTDBY;
+	tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SWAP;
+	tmp |= value << AC_COMPCTRL_SWAP_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYSTEN;
+	tmp |= value << AC_COMPCTRL_HYSTEN_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_INTSEL_Msk;
+	tmp |= AC_COMPCTRL_INTSEL(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
+	tmp |= AC_COMPCTRL_MUXNEG(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
+	tmp |= AC_COMPCTRL_MUXPOS(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
+                                                                 hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SPEED_Msk;
+	tmp |= AC_COMPCTRL_SPEED(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYST_Msk;
+	tmp |= AC_COMPCTRL_HYST(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_FLEN_Msk;
+	tmp |= AC_COMPCTRL_FLEN(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
+                                                               hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_OUT_Msk;
+	tmp |= AC_COMPCTRL_OUT(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->COMPCTRL[index].reg;
+}
+
+static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp &= ~AC_CALIB_BIAS0_Msk;
+	tmp |= AC_CALIB_BIAS0(data);
+	((Ac *)hw)->CALIB.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->CALIB.reg;
+}
+
+static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AC_E53_H_INCLUDED */
+#endif /* _SAME53_AC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_adc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_adc_e53.h
new file mode 100644
index 000000000..f03915144
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_adc_e53.h
@@ -0,0 +1,3663 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_ADC_COMPONENT_
+#ifndef _HRI_ADC_E53_H_INCLUDED_
+#define _HRI_ADC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ADC_CRITICAL_SECTIONS)
+#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ADC_CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_adc_calib_reg_t;
+typedef uint16_t hri_adc_ctrla_reg_t;
+typedef uint16_t hri_adc_ctrlb_reg_t;
+typedef uint16_t hri_adc_gaincorr_reg_t;
+typedef uint16_t hri_adc_inputctrl_reg_t;
+typedef uint16_t hri_adc_offsetcorr_reg_t;
+typedef uint16_t hri_adc_ress_reg_t;
+typedef uint16_t hri_adc_result_reg_t;
+typedef uint16_t hri_adc_winlt_reg_t;
+typedef uint16_t hri_adc_winut_reg_t;
+typedef uint32_t hri_adc_dseqctrl_reg_t;
+typedef uint32_t hri_adc_dseqdata_reg_t;
+typedef uint32_t hri_adc_dseqstat_reg_t;
+typedef uint32_t hri_adc_syncbusy_reg_t;
+typedef uint8_t  hri_adc_avgctrl_reg_t;
+typedef uint8_t  hri_adc_dbgctrl_reg_t;
+typedef uint8_t  hri_adc_evctrl_reg_t;
+typedef uint8_t  hri_adc_intenset_reg_t;
+typedef uint8_t  hri_adc_intflag_reg_t;
+typedef uint8_t  hri_adc_refctrl_reg_t;
+typedef uint8_t  hri_adc_sampctrl_reg_t;
+typedef uint8_t  hri_adc_status_reg_t;
+typedef uint8_t  hri_adc_swtrig_reg_t;
+
+static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	((Adc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos;
+}
+
+static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+}
+
+static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos;
+}
+
+static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+}
+
+static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data)
+{
+	((Adc *)hw)->INTENSET.reg = data;
+	((Adc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->STATUS.reg;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos;
+}
+
+static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQSTAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->DSEQSTAT.reg;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESULT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESULT.reg;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask)
+{
+	return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESS.reg;
+}
+
+static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ENABLE;
+	tmp |= value << ADC_CTRLA_ENABLE_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_SLAVEEN;
+	tmp |= value << ADC_CTRLA_SLAVEEN_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_RUNSTDBY;
+	tmp |= value << ADC_CTRLA_RUNSTDBY_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ONDEMAND;
+	tmp |= value << ADC_CTRLA_ONDEMAND_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_R2R;
+	tmp |= value << ADC_CTRLA_R2R_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_DUALSEL_Msk;
+	tmp |= ADC_CTRLA_DUALSEL(data);
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_PRESCALER_Msk;
+	tmp |= ADC_CTRLA_PRESCALER(data);
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	return ((Adc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHEI;
+	tmp |= value << ADC_EVCTRL_FLUSHEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTEI;
+	tmp |= value << ADC_EVCTRL_STARTEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHINV;
+	tmp |= value << ADC_EVCTRL_FLUSHINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTINV;
+	tmp |= value << ADC_EVCTRL_STARTINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_RESRDYEO;
+	tmp |= value << ADC_EVCTRL_RESRDYEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_WINMONEO;
+	tmp |= value << ADC_EVCTRL_WINMONEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= ~ADC_DBGCTRL_DBGRUN;
+	tmp |= value << ADC_DBGCTRL_DBGRUN_Pos;
+	((Adc *)hw)->DBGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_DIFFMODE;
+	tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos;
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_DSEQSTOP;
+	tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos;
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk;
+	tmp |= ADC_INPUTCTRL_MUXPOS(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk;
+	tmp |= ADC_INPUTCTRL_MUXNEG(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->INPUTCTRL.reg;
+}
+
+static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_LEFTADJ;
+	tmp |= value << ADC_CTRLB_LEFTADJ_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_FREERUN;
+	tmp |= value << ADC_CTRLB_FREERUN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_CORREN;
+	tmp |= value << ADC_CTRLB_CORREN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_WINSS;
+	tmp |= value << ADC_CTRLB_WINSS_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_RESSEL_Msk;
+	tmp |= ADC_CTRLB_RESSEL(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_WINMODE_Msk;
+	tmp |= ADC_CTRLB_WINMODE(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->CTRLB.reg;
+}
+
+static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFCOMP;
+	tmp |= value << ADC_REFCTRL_REFCOMP_Pos;
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFSEL_Msk;
+	tmp |= ADC_REFCTRL_REFSEL(data);
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->REFCTRL.reg;
+}
+
+static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk;
+	tmp |= ADC_AVGCTRL_SAMPLENUM(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_ADJRES_Msk;
+	tmp |= ADC_AVGCTRL_ADJRES(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->AVGCTRL.reg;
+}
+
+static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_OFFCOMP;
+	tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos;
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk;
+	tmp |= ADC_SAMPCTRL_SAMPLEN(data);
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SAMPCTRL.reg;
+}
+
+static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= ~ADC_WINLT_WINLT_Msk;
+	tmp |= ADC_WINLT_WINLT(data);
+	((Adc *)hw)->WINLT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	return ((Adc *)hw)->WINLT.reg;
+}
+
+static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= ~ADC_WINUT_WINUT_Msk;
+	tmp |= ADC_WINUT_WINUT(data);
+	((Adc *)hw)->WINUT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	return ((Adc *)hw)->WINUT.reg;
+}
+
+static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= ~ADC_GAINCORR_GAINCORR_Msk;
+	tmp |= ADC_GAINCORR_GAINCORR(data);
+	((Adc *)hw)->GAINCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	return ((Adc *)hw)->GAINCORR.reg;
+}
+
+static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const        hw,
+                                                                            hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk;
+	tmp |= ADC_OFFSETCORR_OFFSETCORR(data);
+	((Adc *)hw)->OFFSETCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->OFFSETCORR.reg;
+}
+
+static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_FLUSH;
+	tmp |= value << ADC_SWTRIG_FLUSH_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_START;
+	tmp |= value << ADC_SWTRIG_START_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SWTRIG.reg;
+}
+
+static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_INPUTCTRL;
+	tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_CTRLB;
+	tmp |= value << ADC_DSEQCTRL_CTRLB_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_REFCTRL;
+	tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_AVGCTRL;
+	tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_SAMPCTRL;
+	tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_WINLT;
+	tmp |= value << ADC_DSEQCTRL_WINLT_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_WINUT;
+	tmp |= value << ADC_DSEQCTRL_WINUT_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_GAINCORR;
+	tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_OFFSETCORR;
+	tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_AUTOSTART;
+	tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg = data;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->DSEQCTRL.reg;
+}
+
+static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASCOMP_Msk;
+	tmp |= ADC_CALIB_BIASCOMP(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASR2R_Msk;
+	tmp |= ADC_CALIB_BIASR2R(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASREFBUF_Msk;
+	tmp |= ADC_CALIB_BIASREFBUF(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CALIB.reg;
+}
+
+static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQDATA.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ADC_E53_H_INCLUDED */
+#endif /* _SAME53_ADC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_aes_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_aes_e53.h
new file mode 100644
index 000000000..6f7d67654
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_aes_e53.h
@@ -0,0 +1,1287 @@
+/**
+ * \file
+ *
+ * \brief SAM AES
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_AES_COMPONENT_
+#ifndef _HRI_AES_E53_H_INCLUDED_
+#define _HRI_AES_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AES_CRITICAL_SECTIONS)
+#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AES_CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_aes_ciplen_reg_t;
+typedef uint32_t hri_aes_ctrla_reg_t;
+typedef uint32_t hri_aes_ghash_reg_t;
+typedef uint32_t hri_aes_hashkey_reg_t;
+typedef uint32_t hri_aes_indata_reg_t;
+typedef uint32_t hri_aes_intvectv_reg_t;
+typedef uint32_t hri_aes_keyword_reg_t;
+typedef uint32_t hri_aes_randseed_reg_t;
+typedef uint8_t  hri_aes_ctrlb_reg_t;
+typedef uint8_t  hri_aes_databufptr_reg_t;
+typedef uint8_t  hri_aes_dbgctrl_reg_t;
+typedef uint8_t  hri_aes_intenset_reg_t;
+typedef uint8_t  hri_aes_intflag_reg_t;
+
+static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	((Aes *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTENSET.reg;
+}
+
+static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data)
+{
+	((Aes *)hw)->INTENSET.reg = data;
+	((Aes *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_ENABLE;
+	tmp |= value << AES_CTRLA_ENABLE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CIPHER;
+	tmp |= value << AES_CTRLA_CIPHER_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_STARTMODE;
+	tmp |= value << AES_CTRLA_STARTMODE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_LOD;
+	tmp |= value << AES_CTRLA_LOD_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYGEN;
+	tmp |= value << AES_CTRLA_KEYGEN_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_XORKEY;
+	tmp |= value << AES_CTRLA_XORKEY_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_AESMODE_Msk;
+	tmp |= AES_CTRLA_AESMODE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CFBS_Msk;
+	tmp |= AES_CTRLA_CFBS(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYSIZE_Msk;
+	tmp |= AES_CTRLA_KEYSIZE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CTYPE_Msk;
+	tmp |= AES_CTRLA_CTYPE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLA.reg;
+}
+
+static inline void hri_aes_set_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_START;
+	tmp |= value << AES_CTRLB_START_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_NEWMSG;
+	tmp |= value << AES_CTRLB_NEWMSG_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_EOM;
+	tmp |= value << AES_CTRLB_EOM_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_GFMUL;
+	tmp |= value << AES_CTRLB_GFMUL_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLB.reg;
+}
+
+static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const        hw,
+                                                                           hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk;
+	tmp |= AES_DATABUFPTR_INDATAPTR(data);
+	((Aes *)hw)->DATABUFPTR.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DATABUFPTR.reg;
+}
+
+static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp &= ~AES_DBGCTRL_DBGRUN;
+	tmp |= value << AES_DBGCTRL_DBGRUN_Pos;
+	((Aes *)hw)->DBGCTRL.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->INDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INDATA.reg;
+}
+
+static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index,
+                                                            hri_aes_hashkey_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->HASHKEY[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->HASHKEY[index].reg;
+}
+
+static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->GHASH[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->GHASH[index].reg;
+}
+
+static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CIPLEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CIPLEN.reg;
+}
+
+static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->RANDSEED.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw)
+{
+	return ((Aes *)hw)->RANDSEED.reg;
+}
+
+static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->KEYWORD[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INTVECTV[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AES_E53_H_INCLUDED */
+#endif /* _SAME53_AES_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ccl_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ccl_e53.h
new file mode 100644
index 000000000..12138d7b4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ccl_e53.h
@@ -0,0 +1,776 @@
+/**
+ * \file
+ *
+ * \brief SAM CCL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_CCL_COMPONENT_
+#ifndef _HRI_CCL_E53_H_INCLUDED_
+#define _HRI_CCL_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CCL_CRITICAL_SECTIONS)
+#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CCL_CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ccl_lutctrl_reg_t;
+typedef uint8_t  hri_ccl_ctrl_reg_t;
+typedef uint8_t  hri_ccl_seqctrl_reg_t;
+
+static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_ENABLE;
+	tmp |= value << CCL_CTRL_ENABLE_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_RUNSTDBY;
+	tmp |= value << CCL_CTRL_RUNSTDBY_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw)
+{
+	return ((Ccl *)hw)->CTRL.reg;
+}
+
+static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= ~CCL_SEQCTRL_SEQSEL_Msk;
+	tmp |= CCL_SEQCTRL_SEQSEL(data);
+	((Ccl *)hw)->SEQCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->SEQCTRL[index].reg;
+}
+
+static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_ENABLE;
+	tmp |= value << CCL_LUTCTRL_ENABLE_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_EDGESEL;
+	tmp |= value << CCL_LUTCTRL_EDGESEL_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INVEI;
+	tmp |= value << CCL_LUTCTRL_INVEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEI;
+	tmp |= value << CCL_LUTCTRL_LUTEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEO;
+	tmp |= value << CCL_LUTCTRL_LUTEO_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index,
+                                                                   hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_FILTSEL_Msk;
+	tmp |= CCL_LUTCTRL_FILTSEL(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL0_Msk;
+	tmp |= CCL_LUTCTRL_INSEL0(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL1_Msk;
+	tmp |= CCL_LUTCTRL_INSEL1(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL2_Msk;
+	tmp |= CCL_LUTCTRL_INSEL2(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index,
+                                                                 hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_TRUTH_Msk;
+	tmp |= CCL_LUTCTRL_TRUTH(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->LUTCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CCL_E53_H_INCLUDED */
+#endif /* _SAME53_CCL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_cmcc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_cmcc_e53.h
new file mode 100644
index 000000000..e8e577b02
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_cmcc_e53.h
@@ -0,0 +1,361 @@
+/**
+ * \file
+ *
+ * \brief SAM CMCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_CMCC_COMPONENT_
+#ifndef _HRI_CMCC_E53_H_INCLUDED_
+#define _HRI_CMCC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CMCC_CRITICAL_SECTIONS)
+#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CMCC_CRITICAL_SECTION_ENTER()
+#define CMCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_cmcc_cfg_reg_t;
+typedef uint32_t hri_cmcc_ctrl_reg_t;
+typedef uint32_t hri_cmcc_lckway_reg_t;
+typedef uint32_t hri_cmcc_maint0_reg_t;
+typedef uint32_t hri_cmcc_maint1_reg_t;
+typedef uint32_t hri_cmcc_mcfg_reg_t;
+typedef uint32_t hri_cmcc_mctrl_reg_t;
+typedef uint32_t hri_cmcc_men_reg_t;
+typedef uint32_t hri_cmcc_msr_reg_t;
+typedef uint32_t hri_cmcc_sr_reg_t;
+typedef uint32_t hri_cmcc_type_reg_t;
+
+static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos;
+}
+
+static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos;
+}
+
+static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->TYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->TYPE.reg;
+}
+
+static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos;
+}
+
+static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->SR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->SR.reg;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask)
+{
+	return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MSR.reg;
+}
+
+static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->CFG.reg;
+}
+
+static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->LCKWAY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->LCKWAY.reg;
+}
+
+static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MCFG.reg;
+}
+
+static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MEN.reg;
+}
+
+static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CTRL.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MAINT0.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MAINT1.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCTRL.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CMCC_E53_H_INCLUDED */
+#endif /* _SAME53_CMCC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dac_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dac_e53.h
new file mode 100644
index 000000000..38670055f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dac_e53.h
@@ -0,0 +1,1706 @@
+/**
+ * \file
+ *
+ * \brief SAM DAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_DAC_COMPONENT_
+#ifndef _HRI_DAC_E53_H_INCLUDED_
+#define _HRI_DAC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DAC_CRITICAL_SECTIONS)
+#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DAC_CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dac_dacctrl_reg_t;
+typedef uint16_t hri_dac_data_reg_t;
+typedef uint16_t hri_dac_databuf_reg_t;
+typedef uint16_t hri_dac_result_reg_t;
+typedef uint32_t hri_dac_syncbusy_reg_t;
+typedef uint8_t  hri_dac_ctrla_reg_t;
+typedef uint8_t  hri_dac_ctrlb_reg_t;
+typedef uint8_t  hri_dac_dbgctrl_reg_t;
+typedef uint8_t  hri_dac_evctrl_reg_t;
+typedef uint8_t  hri_dac_intenset_reg_t;
+typedef uint8_t  hri_dac_intflag_reg_t;
+typedef uint8_t  hri_dac_status_reg_t;
+
+static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg)
+{
+	while (((Dac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg)
+{
+	return ((Dac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+}
+
+static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0;
+}
+
+static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1;
+}
+
+static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0;
+}
+
+static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+}
+
+static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0;
+}
+
+static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1;
+}
+
+static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0;
+}
+
+static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	((Dac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1;
+}
+
+static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0;
+}
+
+static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0;
+}
+
+static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1;
+}
+
+static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1;
+}
+
+static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0;
+}
+
+static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0;
+}
+
+static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1;
+}
+
+static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1;
+}
+
+static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data)
+{
+	((Dac *)hw)->INTENSET.reg = data;
+	((Dac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos;
+}
+
+static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw)
+{
+	return ((Dac *)hw)->STATUS.reg;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos;
+}
+
+static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Dac *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index,
+                                                                hri_dac_result_reg_t mask)
+{
+	return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos;
+}
+
+static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index)
+{
+	return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos;
+}
+
+static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index,
+                                                          hri_dac_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->RESULT[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index)
+{
+	return ((Dac *)hw)->RESULT[index].reg;
+}
+
+static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= ~DAC_CTRLA_ENABLE;
+	tmp |= value << DAC_CTRLA_ENABLE_Pos;
+	((Dac *)hw)->CTRLA.reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw)
+{
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	return ((Dac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_DIFF;
+	tmp |= value << DAC_CTRLB_DIFF_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_REFSEL_Msk;
+	tmp |= DAC_CTRLB_REFSEL(data);
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw)
+{
+	return ((Dac *)hw)->CTRLB.reg;
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI0;
+	tmp |= value << DAC_EVCTRL_STARTEI0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI1;
+	tmp |= value << DAC_EVCTRL_STARTEI1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO0;
+	tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO1;
+	tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_INVEI0;
+	tmp |= value << DAC_EVCTRL_INVEI0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_INVEI1;
+	tmp |= value << DAC_EVCTRL_INVEI1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_RESRDYEO0;
+	tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_RESRDYEO1;
+	tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_LEFTADJ;
+	tmp |= value << DAC_DACCTRL_LEFTADJ_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_ENABLE;
+	tmp |= value << DAC_DACCTRL_ENABLE_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_FEXT;
+	tmp |= value << DAC_DACCTRL_FEXT_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_RUNSTDBY;
+	tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_DITHER;
+	tmp |= value << DAC_DACCTRL_DITHER_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index,
+                                                                 hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_CCTRL_Msk;
+	tmp |= DAC_DACCTRL_CCTRL(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index,
+                                                                   hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_REFRESH_Msk;
+	tmp |= DAC_DACCTRL_REFRESH(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index,
+                                                               hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_OSR_Msk;
+	tmp |= DAC_DACCTRL_OSR(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	return ((Dac *)hw)->DACCTRL[index].reg;
+}
+
+static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp &= ~DAC_DBGCTRL_DBGRUN;
+	tmp |= value << DAC_DBGCTRL_DBGRUN_Pos;
+	((Dac *)hw)->DBGCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DAC_E53_H_INCLUDED */
+#endif /* _SAME53_DAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dmac_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dmac_e53.h
new file mode 100644
index 000000000..f614acd92
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dmac_e53.h
@@ -0,0 +1,6800 @@
+/**
+ * \file
+ *
+ * \brief SAM DMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_DMAC_COMPONENT_
+#ifndef _HRI_DMAC_E53_H_INCLUDED_
+#define _HRI_DMAC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
+#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DMAC_CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dmac_crcctrl_reg_t;
+typedef uint16_t hri_dmac_ctrl_reg_t;
+typedef uint16_t hri_dmac_intpend_reg_t;
+typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
+typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
+typedef uint32_t hri_dmac_active_reg_t;
+typedef uint32_t hri_dmac_baseaddr_reg_t;
+typedef uint32_t hri_dmac_busych_reg_t;
+typedef uint32_t hri_dmac_chctrla_reg_t;
+typedef uint32_t hri_dmac_crcchksum_reg_t;
+typedef uint32_t hri_dmac_crcdatain_reg_t;
+typedef uint32_t hri_dmac_intstatus_reg_t;
+typedef uint32_t hri_dmac_pendch_reg_t;
+typedef uint32_t hri_dmac_prictrl0_reg_t;
+typedef uint32_t hri_dmac_swtrigctrl_reg_t;
+typedef uint32_t hri_dmac_wrbaddr_reg_t;
+typedef uint32_t hri_dmacchannel_chctrla_reg_t;
+typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
+typedef uint8_t  hri_dmac_chctrlb_reg_t;
+typedef uint8_t  hri_dmac_chevctrl_reg_t;
+typedef uint8_t  hri_dmac_chintenset_reg_t;
+typedef uint8_t  hri_dmac_chintflag_reg_t;
+typedef uint8_t  hri_dmac_chprilvl_reg_t;
+typedef uint8_t  hri_dmac_chstatus_reg_t;
+typedef uint8_t  hri_dmac_crcstatus_reg_t;
+typedef uint8_t  hri_dmac_dbgctrl_reg_t;
+typedef uint8_t  hri_dmacchannel_chctrlb_reg_t;
+typedef uint8_t  hri_dmacchannel_chevctrl_reg_t;
+typedef uint8_t  hri_dmacchannel_chintenset_reg_t;
+typedef uint8_t  hri_dmacchannel_chintflag_reg_t;
+typedef uint8_t  hri_dmacchannel_chprilvl_reg_t;
+typedef uint8_t  hri_dmacchannel_chstatus_reg_t;
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PENDCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PENDCH.reg;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->ACTIVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->ACTIVE.reg;
+}
+
+static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_DMAENABLE;
+	tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN0;
+	tmp |= value << DMAC_CTRL_LVLEN0_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN1;
+	tmp |= value << DMAC_CTRL_LVLEN1_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN2;
+	tmp |= value << DMAC_CTRL_LVLEN2_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN3;
+	tmp |= value << DMAC_CTRL_LVLEN3_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const      hw,
+                                                                         hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
+	tmp |= DMAC_CRCCTRL_CRCPOLY(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
+	tmp |= DMAC_CRCCTRL_CRCSRC(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCMODE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const        hw,
+                                                                           hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
+	tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
+	((Dmac *)hw)->CRCDATAIN.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCDATAIN.reg;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const        hw,
+                                                                           hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
+	tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
+	((Dmac *)hw)->CRCCHKSUM.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCHKSUM.reg;
+}
+
+static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= ~DMAC_DBGCTRL_DBGRUN;
+	tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
+	((Dmac *)hw)->DBGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const         hw,
+                                                                    hri_dmac_swtrigctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->SWTRIGCTRL.reg;
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS0_Msk;
+	tmp |= DMAC_PRICTRL0_QOS0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS1_Msk;
+	tmp |= DMAC_PRICTRL0_QOS1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS2_Msk;
+	tmp |= DMAC_PRICTRL0_QOS2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS3_Msk;
+	tmp |= DMAC_PRICTRL0_QOS3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PRICTRL0.reg;
+}
+
+static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TERR;
+	tmp |= value << DMAC_INTPEND_TERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TCMPL;
+	tmp |= value << DMAC_INTPEND_TCMPL_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_SUSP;
+	tmp |= value << DMAC_INTPEND_SUSP_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_CRCERR;
+	tmp |= value << DMAC_INTPEND_CRCERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_FERR;
+	tmp |= value << DMAC_INTPEND_FERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_BUSY;
+	tmp |= value << DMAC_INTPEND_BUSY_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_PEND;
+	tmp |= value << DMAC_INTPEND_PEND_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_ID_Msk;
+	tmp |= DMAC_INTPEND_ID(data);
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTPEND.reg;
+}
+
+static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const       hw,
+                                                                        hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
+	tmp |= DMAC_BASEADDR_BASEADDR(data);
+	((Dmac *)hw)->BASEADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BASEADDR.reg;
+}
+
+static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
+	tmp |= DMAC_WRBADDR_WRBADDR(data);
+	((Dmac *)hw)->WRBADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->WRBADDR.reg;
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CRCSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCSTATUS.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_VALID;
+	tmp |= value << DMAC_BTCTRL_VALID_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_SRCINC;
+	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_DSTINC;
+	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSEL;
+	tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
+	tmp |= DMAC_BTCTRL_EVOSEL(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const               hw,
+                                                              hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
+	tmp |= DMAC_BTCTRL_BLOCKACT(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
+	tmp |= DMAC_BTCTRL_BEATSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
+	tmp |= DMAC_BTCTRL_STEPSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const               hw,
+                                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCTRL.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const              hw,
+                                                                                   hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= ~DMAC_BTCNT_BTCNT_Msk;
+	tmp |= DMAC_BTCNT_BTCNT(data);
+	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const              hw,
+                                                                              hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCNT.reg;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t
+hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
+	tmp |= DMAC_SRCADDR_SRCADDR(data);
+	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->SRCADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                 hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                   hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk;
+	tmp |= DMAC_DSTADDR_CRC_CHKINIT(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                   hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                    hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
+	tmp |= DMAC_DSTADDR_DSTADDR(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DSTADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                               hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
+	tmp |= DMAC_DESCADDR_DESCADDR(data);
+	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                  hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DESCADDR.reg;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const        hw,
+                                                                         hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const         hw,
+                                                                        hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = data;
+	((DmacChannel *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const      hw,
+                                                                            hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGSRC(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const      hw,
+                                                                            hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGACT(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const      hw,
+                                                                             hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk;
+	tmp |= DMAC_CHCTRLA_BURSTLEN(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const      hw,
+                                                                              hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk;
+	tmp |= DMAC_CHCTRLA_THRESHOLD(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHCTRLA.reg;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const      hw,
+                                                                        hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((DmacChannel *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHCTRLB.reg;
+}
+
+static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const       hw,
+                                                                             hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp &= ~DMAC_CHPRILVL_PRILVL_Msk;
+	tmp |= DMAC_CHPRILVL_PRILVL(data);
+	((DmacChannel *)hw)->CHPRILVL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const       hw,
+                                                                       hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHPRILVL.reg;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVIE;
+	tmp |= value << DMAC_CHEVCTRL_EVIE_Pos;
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOE;
+	tmp |= value << DMAC_CHEVCTRL_EVOE_Pos;
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const       hw,
+                                                                            hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVACT_Msk;
+	tmp |= DMAC_CHEVCTRL_EVACT(data);
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const       hw,
+                                                                              hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk;
+	tmp |= DMAC_CHEVCTRL_EVOMODE(data);
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const       hw,
+                                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHEVCTRL.reg;
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const       hw,
+                                                                       hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chintflag_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                            hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                 hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg;
+}
+
+static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chintenset_reg_t data)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask;
+}
+
+static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGSRC(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGACT(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk;
+	tmp |= DMAC_CHCTRLA_BURSTLEN(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk;
+	tmp |= DMAC_CHCTRLA_THRESHOLD(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_dmac_chctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+}
+
+static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chprilvl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp &= ~DMAC_CHPRILVL_PRILVL_Msk;
+	tmp |= DMAC_CHPRILVL_PRILVL(data);
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chprilvl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVIE;
+	tmp |= value << DMAC_CHEVCTRL_EVIE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOE;
+	tmp |= value << DMAC_CHEVCTRL_EVOE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVACT_Msk;
+	tmp |= DMAC_CHEVCTRL_EVACT(data);
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk;
+	tmp |= DMAC_CHEVCTRL_EVOMODE(data);
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chevctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DMAC_E53_H_INCLUDED */
+#endif /* _SAME53_DMAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dsu_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dsu_e53.h
new file mode 100644
index 000000000..9a61ba42a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_dsu_e53.h
@@ -0,0 +1,1256 @@
+/**
+ * \file
+ *
+ * \brief SAM DSU
+ *
+ * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_DSU_COMPONENT_
+#ifndef _HRI_DSU_E53_H_INCLUDED_
+#define _HRI_DSU_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DSU_CRITICAL_SECTIONS)
+#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DSU_CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_dsu_addr_reg_t;
+typedef uint32_t hri_dsu_cfg_reg_t;
+typedef uint32_t hri_dsu_cid0_reg_t;
+typedef uint32_t hri_dsu_cid1_reg_t;
+typedef uint32_t hri_dsu_cid2_reg_t;
+typedef uint32_t hri_dsu_cid3_reg_t;
+typedef uint32_t hri_dsu_data_reg_t;
+typedef uint32_t hri_dsu_dcc_reg_t;
+typedef uint32_t hri_dsu_did_reg_t;
+typedef uint32_t hri_dsu_end_reg_t;
+typedef uint32_t hri_dsu_entry0_reg_t;
+typedef uint32_t hri_dsu_entry1_reg_t;
+typedef uint32_t hri_dsu_length_reg_t;
+typedef uint32_t hri_dsu_memtype_reg_t;
+typedef uint32_t hri_dsu_pid0_reg_t;
+typedef uint32_t hri_dsu_pid1_reg_t;
+typedef uint32_t hri_dsu_pid2_reg_t;
+typedef uint32_t hri_dsu_pid3_reg_t;
+typedef uint32_t hri_dsu_pid4_reg_t;
+typedef uint32_t hri_dsu_pid5_reg_t;
+typedef uint32_t hri_dsu_pid6_reg_t;
+typedef uint32_t hri_dsu_pid7_reg_t;
+typedef uint8_t  hri_dsu_ctrl_reg_t;
+typedef uint8_t  hri_dsu_statusa_reg_t;
+typedef uint8_t  hri_dsu_statusb_reg_t;
+
+static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSB.reg;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DID.reg;
+}
+
+static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos;
+}
+
+static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY0.reg;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY1.reg;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->END.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->END.reg;
+}
+
+static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->MEMTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->MEMTYPE.reg;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID4.reg;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID5.reg;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID6.reg;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID7.reg;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID0.reg;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID1.reg;
+}
+
+static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID2.reg;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID3.reg;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID0.reg;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID1.reg;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID2.reg;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID3.reg;
+}
+
+static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_AMOD_Msk;
+	tmp |= DSU_ADDR_AMOD(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_ADDR_Msk;
+	tmp |= DSU_ADDR_ADDR(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ADDR.reg;
+}
+
+static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= ~DSU_LENGTH_LENGTH_Msk;
+	tmp |= DSU_LENGTH_LENGTH(data);
+	((Dsu *)hw)->LENGTH.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->LENGTH.reg;
+}
+
+static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= ~DSU_DATA_DATA_Msk;
+	tmp |= DSU_DATA_DATA(data);
+	((Dsu *)hw)->DATA.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DATA.reg;
+}
+
+static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= ~DSU_DCC_DATA_Msk;
+	tmp |= DSU_DCC_DATA(data);
+	((Dsu *)hw)->DCC[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCC[index].reg;
+}
+
+static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_ETBRAMEN;
+	tmp |= value << DSU_CFG_ETBRAMEN_Pos;
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_LQOS_Msk;
+	tmp |= DSU_CFG_LQOS(data);
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_DCCDMALEVEL_Msk;
+	tmp |= DSU_CFG_DCCDMALEVEL(data);
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CFG.reg;
+}
+
+static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSA.reg;
+}
+
+static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CTRL.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DSU_E53_H_INCLUDED */
+#endif /* _SAME53_DSU_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_e53.h
new file mode 100644
index 000000000..850159dea
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_e53.h
@@ -0,0 +1,75 @@
+/**
+ * \file
+ *
+ * \brief SAM E53 HRI top-level header file
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HRI_E53_H_INCLUDED_
+#define _HRI_E53_H_INCLUDED_
+
+#include <sam.h>
+#include <hri_ac_e53.h>
+#include <hri_adc_e53.h>
+#include <hri_aes_e53.h>
+#include <hri_ccl_e53.h>
+#include <hri_cmcc_e53.h>
+#include <hri_dac_e53.h>
+#include <hri_dmac_e53.h>
+#include <hri_dsu_e53.h>
+#include <hri_eic_e53.h>
+#include <hri_evsys_e53.h>
+#include <hri_freqm_e53.h>
+#include <hri_gclk_e53.h>
+#include <hri_gmac_e53.h>
+#include <hri_hmatrixb_e53.h>
+#include <hri_i2s_e53.h>
+#include <hri_icm_e53.h>
+#include <hri_mclk_e53.h>
+#include <hri_nvmctrl_e53.h>
+#include <hri_osc32kctrl_e53.h>
+#include <hri_oscctrl_e53.h>
+#include <hri_pac_e53.h>
+#include <hri_pcc_e53.h>
+#include <hri_pdec_e53.h>
+#include <hri_pm_e53.h>
+#include <hri_port_e53.h>
+#include <hri_qspi_e53.h>
+#include <hri_ramecc_e53.h>
+#include <hri_rstc_e53.h>
+#include <hri_rtc_e53.h>
+#include <hri_sdhc_e53.h>
+#include <hri_sercom_e53.h>
+#include <hri_supc_e53.h>
+#include <hri_tc_e53.h>
+#include <hri_tcc_e53.h>
+#include <hri_trng_e53.h>
+#include <hri_usb_e53.h>
+#include <hri_wdt_e53.h>
+
+#endif /* _HRI_E53_H_INCLUDED_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_eic_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_eic_e53.h
new file mode 100644
index 000000000..38a467ac8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_eic_e53.h
@@ -0,0 +1,1838 @@
+/**
+ * \file
+ *
+ * \brief SAM EIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_EIC_COMPONENT_
+#ifndef _HRI_EIC_E53_H_INCLUDED_
+#define _HRI_EIC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
+#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EIC_CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_eic_nmiflag_reg_t;
+typedef uint32_t hri_eic_asynch_reg_t;
+typedef uint32_t hri_eic_config_reg_t;
+typedef uint32_t hri_eic_debouncen_reg_t;
+typedef uint32_t hri_eic_dprescaler_reg_t;
+typedef uint32_t hri_eic_evctrl_reg_t;
+typedef uint32_t hri_eic_intenset_reg_t;
+typedef uint32_t hri_eic_intflag_reg_t;
+typedef uint32_t hri_eic_pinstate_reg_t;
+typedef uint32_t hri_eic_syncbusy_reg_t;
+typedef uint8_t  hri_eic_ctrla_reg_t;
+typedef uint8_t  hri_eic_nmictrl_reg_t;
+
+static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
+{
+	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
+}
+
+static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
+{
+	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Eic *)hw)->NMIFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMIFLAG.reg;
+}
+
+static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	((Eic *)hw)->NMIFLAG.reg = mask;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
+	((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTENSET.reg;
+}
+
+static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = data;
+	((Eic *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask)
+{
+	return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw)
+{
+	return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->PINSTATE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw)
+{
+	return ((Eic *)hw)->PINSTATE.reg;
+}
+
+static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_ENABLE;
+	tmp |= value << EIC_CTRLA_ENABLE_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_CKSEL;
+	tmp |= value << EIC_CTRLA_CKSEL_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg = data;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
+{
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	return ((Eic *)hw)->CTRLA.reg;
+}
+
+static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIFILTEN;
+	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIASYNCH;
+	tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
+	tmp |= EIC_NMICTRL_NMISENSE(data);
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMICTRL.reg;
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
+	tmp |= EIC_EVCTRL_EXTINTEO(data);
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
+	tmp |= EIC_ASYNCH_ASYNCH(data);
+	((Eic *)hw)->ASYNCH.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
+{
+	return ((Eic *)hw)->ASYNCH.reg;
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN0;
+	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN1;
+	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN2;
+	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN3;
+	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN4;
+	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN5;
+	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN6;
+	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN7;
+	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE0_Msk;
+	tmp |= EIC_CONFIG_SENSE0(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE1_Msk;
+	tmp |= EIC_CONFIG_SENSE1(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE2_Msk;
+	tmp |= EIC_CONFIG_SENSE2(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE3_Msk;
+	tmp |= EIC_CONFIG_SENSE3(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE4_Msk;
+	tmp |= EIC_CONFIG_SENSE4(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE5_Msk;
+	tmp |= EIC_CONFIG_SENSE5(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE6_Msk;
+	tmp |= EIC_CONFIG_SENSE6(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE7_Msk;
+	tmp |= EIC_CONFIG_SENSE7(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
+                                                          hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
+{
+	return ((Eic *)hw)->CONFIG[index].reg;
+}
+
+static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const       hw,
+                                                                         hri_eic_debouncen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk;
+	tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data);
+	((Eic *)hw)->DEBOUNCEN.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->DEBOUNCEN.reg;
+}
+
+static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_STATES0;
+	tmp |= value << EIC_DPRESCALER_STATES0_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_STATES1;
+	tmp |= value << EIC_DPRESCALER_STATES1_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_TICKON;
+	tmp |= value << EIC_DPRESCALER_TICKON_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const        hw,
+                                                                            hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk;
+	tmp |= EIC_DPRESCALER_PRESCALER0(data);
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const        hw,
+                                                                            hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk;
+	tmp |= EIC_DPRESCALER_PRESCALER1(data);
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw)
+{
+	return ((Eic *)hw)->DPRESCALER.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EIC_E53_H_INCLUDED */
+#endif /* _SAME53_EIC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_evsys_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_evsys_e53.h
new file mode 100644
index 000000000..b64517fcb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_evsys_e53.h
@@ -0,0 +1,1707 @@
+/**
+ * \file
+ *
+ * \brief SAM EVSYS
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_EVSYS_COMPONENT_
+#ifndef _HRI_EVSYS_E53_H_INCLUDED_
+#define _HRI_EVSYS_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS)
+#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EVSYS_CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_evsys_intpend_reg_t;
+typedef uint32_t hri_evsys_busych_reg_t;
+typedef uint32_t hri_evsys_channel_reg_t;
+typedef uint32_t hri_evsys_intstatus_reg_t;
+typedef uint32_t hri_evsys_readyusr_reg_t;
+typedef uint32_t hri_evsys_swevt_reg_t;
+typedef uint32_t hri_evsys_user_reg_t;
+typedef uint32_t hri_evsyschannel_channel_reg_t;
+typedef uint8_t  hri_evsys_chintenset_reg_t;
+typedef uint8_t  hri_evsys_chintflag_reg_t;
+typedef uint8_t  hri_evsys_chstatus_reg_t;
+typedef uint8_t  hri_evsys_ctrla_reg_t;
+typedef uint8_t  hri_evsys_prictrl_reg_t;
+typedef uint8_t  hri_evsyschannel_chintenset_reg_t;
+typedef uint8_t  hri_evsyschannel_chintflag_reg_t;
+typedef uint8_t  hri_evsyschannel_chstatus_reg_t;
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos;
+}
+
+static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const         hw,
+                                                                    hri_evsys_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos;
+}
+
+static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->READYUSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->READYUSR.reg;
+}
+
+static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CTRLA.reg;
+}
+
+static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= ~EVSYS_PRICTRL_RREN;
+	tmp |= value << EVSYS_PRICTRL_RREN_Pos;
+	((Evsys *)hw)->PRICTRL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data)
+{
+	uint8_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= ~EVSYS_PRICTRL_PRI_Msk;
+	tmp |= EVSYS_PRICTRL_PRI(data);
+	((Evsys *)hw)->PRICTRL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->PRICTRL.reg;
+}
+
+static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_OVR;
+	tmp |= value << EVSYS_INTPEND_OVR_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_EVD;
+	tmp |= value << EVSYS_INTPEND_EVD_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_READY;
+	tmp |= value << EVSYS_INTPEND_READY_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_BUSY;
+	tmp |= value << EVSYS_INTPEND_BUSY_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_ID_Msk;
+	tmp |= EVSYS_INTPEND_ID(data);
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTPEND.reg;
+}
+
+static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index,
+                                                                 hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= ~EVSYS_USER_CHANNEL_Msk;
+	tmp |= EVSYS_USER_CHANNEL(data);
+	((Evsys *)hw)->USER[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index,
+                                                          hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->USER[index].reg;
+}
+
+static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->SWEVT.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const         hw,
+                                                                           hri_evsys_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+	} else {
+		((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+	}
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+	} else {
+		((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+	}
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const          hw,
+                                                                          hri_evsys_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = data;
+	((EvsysChannel *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos;
+}
+
+static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const        hw,
+                                                                         hri_evsys_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const       hw,
+                                                                            hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const       hw,
+                                                                           hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const       hw,
+                                                                             hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const       hw,
+                                                                       hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHANNEL.reg;
+}
+
+static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_evsys_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_evsys_chintflag_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask;
+}
+
+static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos;
+}
+
+static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+	} else {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+	}
+}
+
+static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos;
+}
+
+static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+	} else {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+	}
+}
+
+static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_evsys_chintenset_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                   hri_evsys_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg;
+}
+
+static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_chintenset_reg_t data)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_chintenset_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_evsys_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg;
+}
+
+static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EVSYS_E53_H_INCLUDED */
+#endif /* _SAME53_EVSYS_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_freqm_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_freqm_e53.h
new file mode 100644
index 000000000..b44acaba1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_freqm_e53.h
@@ -0,0 +1,464 @@
+/**
+ * \file
+ *
+ * \brief SAM FREQM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_FREQM_COMPONENT_
+#ifndef _HRI_FREQM_E53_H_INCLUDED_
+#define _HRI_FREQM_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
+#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define FREQM_CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_freqm_cfga_reg_t;
+typedef uint32_t hri_freqm_syncbusy_reg_t;
+typedef uint32_t hri_freqm_value_reg_t;
+typedef uint8_t  hri_freqm_ctrla_reg_t;
+typedef uint8_t  hri_freqm_ctrlb_reg_t;
+typedef uint8_t  hri_freqm_intenset_reg_t;
+typedef uint8_t  hri_freqm_intflag_reg_t;
+typedef uint8_t  hri_freqm_status_reg_t;
+
+static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	((Freqm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+}
+
+static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
+}
+
+static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+	} else {
+		((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+	}
+}
+
+static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+}
+
+static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
+{
+	((Freqm *)hw)->INTENSET.reg = data;
+	((Freqm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->VALUE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->VALUE.reg;
+}
+
+static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= ~FREQM_CTRLA_ENABLE;
+	tmp |= value << FREQM_CTRLA_ENABLE_Pos;
+	((Freqm *)hw)->CTRLA.reg = tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg = data;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
+{
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	return ((Freqm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	uint16_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= ~FREQM_CFGA_REFNUM_Msk;
+	tmp |= FREQM_CFGA_REFNUM(data);
+	((Freqm *)hw)->CFGA.reg = tmp;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->CFGA.reg;
+}
+
+static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->STATUS.reg;
+}
+
+static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLB.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_FREQM_E53_H_INCLUDED */
+#endif /* _SAME53_FREQM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_gclk_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_gclk_e53.h
new file mode 100644
index 000000000..58e2b983b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_gclk_e53.h
@@ -0,0 +1,805 @@
+/**
+ * \file
+ *
+ * \brief SAM GCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_GCLK_COMPONENT_
+#ifndef _HRI_GCLK_E53_H_INCLUDED_
+#define _HRI_GCLK_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
+#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GCLK_CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gclk_genctrl_reg_t;
+typedef uint32_t hri_gclk_pchctrl_reg_t;
+typedef uint32_t hri_gclk_syncbusy_reg_t;
+typedef uint8_t  hri_gclk_ctrla_reg_t;
+
+static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	return ((Gclk *)hw)->CTRLA.reg;
+}
+
+static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_GENEN;
+	tmp |= value << GCLK_GENCTRL_GENEN_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_IDC;
+	tmp |= value << GCLK_GENCTRL_IDC_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OOV;
+	tmp |= value << GCLK_GENCTRL_OOV_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OE;
+	tmp |= value << GCLK_GENCTRL_OE_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIVSEL;
+	tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_RUNSTDBY;
+	tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_SRC_Msk;
+	tmp |= GCLK_GENCTRL_SRC(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIV_Msk;
+	tmp |= GCLK_GENCTRL_DIV(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	return ((Gclk *)hw)->GENCTRL[index].reg;
+}
+
+static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_CHEN;
+	tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_WRTLOCK;
+	tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_GEN_Msk;
+	tmp |= GCLK_PCHCTRL_GEN(data);
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Gclk *)hw)->PCHCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GCLK_E53_H_INCLUDED */
+#endif /* _SAME53_GCLK_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_gmac_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_gmac_e53.h
new file mode 100644
index 000000000..7ba41b021
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_gmac_e53.h
@@ -0,0 +1,3766 @@
+/**
+ * \file
+ *
+ * \brief SAM GMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_GMAC_COMPONENT_
+#ifndef _HRI_GMAC_E53_H_INCLUDED_
+#define _HRI_GMAC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GMAC_CRITICAL_SECTIONS)
+#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GMAC_CRITICAL_SECTION_ENTER()
+#define GMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gmac_ae_reg_t;
+typedef uint32_t hri_gmac_bcfr_reg_t;
+typedef uint32_t hri_gmac_bcft_reg_t;
+typedef uint32_t hri_gmac_bfr64_reg_t;
+typedef uint32_t hri_gmac_bft64_reg_t;
+typedef uint32_t hri_gmac_cse_reg_t;
+typedef uint32_t hri_gmac_dcfgr_reg_t;
+typedef uint32_t hri_gmac_dtf_reg_t;
+typedef uint32_t hri_gmac_ec_reg_t;
+typedef uint32_t hri_gmac_efrn_reg_t;
+typedef uint32_t hri_gmac_efrsh_reg_t;
+typedef uint32_t hri_gmac_efrsl_reg_t;
+typedef uint32_t hri_gmac_eftn_reg_t;
+typedef uint32_t hri_gmac_eftsh_reg_t;
+typedef uint32_t hri_gmac_eftsl_reg_t;
+typedef uint32_t hri_gmac_fcse_reg_t;
+typedef uint32_t hri_gmac_fr_reg_t;
+typedef uint32_t hri_gmac_ft_reg_t;
+typedef uint32_t hri_gmac_gtbft1518_reg_t;
+typedef uint32_t hri_gmac_hrb_reg_t;
+typedef uint32_t hri_gmac_hrt_reg_t;
+typedef uint32_t hri_gmac_ihce_reg_t;
+typedef uint32_t hri_gmac_imr_reg_t;
+typedef uint32_t hri_gmac_ipgs_reg_t;
+typedef uint32_t hri_gmac_isr_reg_t;
+typedef uint32_t hri_gmac_jr_reg_t;
+typedef uint32_t hri_gmac_lc_reg_t;
+typedef uint32_t hri_gmac_lffe_reg_t;
+typedef uint32_t hri_gmac_man_reg_t;
+typedef uint32_t hri_gmac_mcf_reg_t;
+typedef uint32_t hri_gmac_mfr_reg_t;
+typedef uint32_t hri_gmac_mft_reg_t;
+typedef uint32_t hri_gmac_ncfgr_reg_t;
+typedef uint32_t hri_gmac_ncr_reg_t;
+typedef uint32_t hri_gmac_nsc_reg_t;
+typedef uint32_t hri_gmac_nsr_reg_t;
+typedef uint32_t hri_gmac_ofr_reg_t;
+typedef uint32_t hri_gmac_orhi_reg_t;
+typedef uint32_t hri_gmac_orlo_reg_t;
+typedef uint32_t hri_gmac_othi_reg_t;
+typedef uint32_t hri_gmac_otlo_reg_t;
+typedef uint32_t hri_gmac_pefrn_reg_t;
+typedef uint32_t hri_gmac_pefrsh_reg_t;
+typedef uint32_t hri_gmac_pefrsl_reg_t;
+typedef uint32_t hri_gmac_peftn_reg_t;
+typedef uint32_t hri_gmac_peftsh_reg_t;
+typedef uint32_t hri_gmac_peftsl_reg_t;
+typedef uint32_t hri_gmac_pfr_reg_t;
+typedef uint32_t hri_gmac_pft_reg_t;
+typedef uint32_t hri_gmac_rbqb_reg_t;
+typedef uint32_t hri_gmac_rjfml_reg_t;
+typedef uint32_t hri_gmac_rlpiti_reg_t;
+typedef uint32_t hri_gmac_rlpitr_reg_t;
+typedef uint32_t hri_gmac_roe_reg_t;
+typedef uint32_t hri_gmac_rpq_reg_t;
+typedef uint32_t hri_gmac_rpsf_reg_t;
+typedef uint32_t hri_gmac_rre_reg_t;
+typedef uint32_t hri_gmac_rse_reg_t;
+typedef uint32_t hri_gmac_rsr_reg_t;
+typedef uint32_t hri_gmac_sab_reg_t;
+typedef uint32_t hri_gmac_samb1_reg_t;
+typedef uint32_t hri_gmac_samt1_reg_t;
+typedef uint32_t hri_gmac_sat_reg_t;
+typedef uint32_t hri_gmac_scf_reg_t;
+typedef uint32_t hri_gmac_sch_reg_t;
+typedef uint32_t hri_gmac_scl_reg_t;
+typedef uint32_t hri_gmac_svlan_reg_t;
+typedef uint32_t hri_gmac_ta_reg_t;
+typedef uint32_t hri_gmac_tbfr1023_reg_t;
+typedef uint32_t hri_gmac_tbfr127_reg_t;
+typedef uint32_t hri_gmac_tbfr1518_reg_t;
+typedef uint32_t hri_gmac_tbfr255_reg_t;
+typedef uint32_t hri_gmac_tbfr511_reg_t;
+typedef uint32_t hri_gmac_tbft1023_reg_t;
+typedef uint32_t hri_gmac_tbft127_reg_t;
+typedef uint32_t hri_gmac_tbft1518_reg_t;
+typedef uint32_t hri_gmac_tbft255_reg_t;
+typedef uint32_t hri_gmac_tbft511_reg_t;
+typedef uint32_t hri_gmac_tbqb_reg_t;
+typedef uint32_t hri_gmac_tce_reg_t;
+typedef uint32_t hri_gmac_ti_reg_t;
+typedef uint32_t hri_gmac_tidm_reg_t;
+typedef uint32_t hri_gmac_tisubn_reg_t;
+typedef uint32_t hri_gmac_tlpiti_reg_t;
+typedef uint32_t hri_gmac_tlpitr_reg_t;
+typedef uint32_t hri_gmac_tmxbfr_reg_t;
+typedef uint32_t hri_gmac_tn_reg_t;
+typedef uint32_t hri_gmac_tpfcp_reg_t;
+typedef uint32_t hri_gmac_tpq_reg_t;
+typedef uint32_t hri_gmac_tpsf_reg_t;
+typedef uint32_t hri_gmac_tsh_reg_t;
+typedef uint32_t hri_gmac_tsl_reg_t;
+typedef uint32_t hri_gmac_tsr_reg_t;
+typedef uint32_t hri_gmac_tssn_reg_t;
+typedef uint32_t hri_gmac_tsssl_reg_t;
+typedef uint32_t hri_gmac_tur_reg_t;
+typedef uint32_t hri_gmac_uce_reg_t;
+typedef uint32_t hri_gmac_ufr_reg_t;
+typedef uint32_t hri_gmac_ur_reg_t;
+typedef uint32_t hri_gmac_wol_reg_t;
+typedef uint32_t hri_gmacsa_sab_reg_t;
+typedef uint32_t hri_gmacsa_sat_reg_t;
+
+static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((GmacSa *)hw)->SAB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw)
+{
+	return ((GmacSa *)hw)->SAB.reg;
+}
+
+static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((GmacSa *)hw)->SAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw)
+{
+	return ((GmacSa *)hw)->SAT.reg;
+}
+
+static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_gmac_sab_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Gmac *)hw)->Sa[submodule_index].SAB.reg;
+}
+
+static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_gmac_sat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Gmac *)hw)->Sa[submodule_index].SAT.reg;
+}
+
+static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_MFS;
+}
+
+static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos;
+}
+
+static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_MFS;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS;
+}
+
+static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP;
+}
+
+static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP;
+}
+
+static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR;
+}
+
+static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR;
+}
+
+static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR;
+}
+
+static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR;
+}
+
+static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TUR;
+}
+
+static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TUR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR;
+}
+
+static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX;
+}
+
+static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos;
+}
+
+static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX;
+}
+
+static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TFC;
+}
+
+static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TFC;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC;
+}
+
+static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP;
+}
+
+static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP;
+}
+
+static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR;
+}
+
+static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR;
+}
+
+static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP;
+}
+
+static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP;
+}
+
+static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ;
+}
+
+static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ;
+}
+
+static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ;
+}
+
+static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ;
+}
+
+static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR;
+}
+
+static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR;
+}
+
+static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT;
+}
+
+static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT;
+}
+
+static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR;
+}
+
+static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR;
+}
+
+static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_SFR;
+}
+
+static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_SFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR;
+}
+
+static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT;
+}
+
+static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT;
+}
+
+static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_SFT;
+}
+
+static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_SFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT;
+}
+
+static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR;
+}
+
+static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR;
+}
+
+static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR;
+}
+
+static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR;
+}
+
+static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT;
+}
+
+static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT;
+}
+
+static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT;
+}
+
+static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT;
+}
+
+static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_SRI;
+}
+
+static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos;
+}
+
+static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_SRI;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI;
+}
+
+static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_WOL;
+}
+
+static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos;
+}
+
+static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_WOL;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL;
+}
+
+static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP;
+}
+
+static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP;
+}
+
+static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask)
+{
+	((Gmac *)hw)->IER.reg = mask;
+}
+
+static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->IMR.reg;
+}
+
+static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data)
+{
+	((Gmac *)hw)->IER.reg = data;
+	((Gmac *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask)
+{
+	((Gmac *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos;
+}
+
+static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos;
+}
+
+static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NSR.reg;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask)
+{
+	return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RPQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RPQ.reg;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask)
+{
+	return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFTSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFTSH.reg;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask)
+{
+	return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFRSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFRSH.reg;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFTSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFTSH.reg;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFRSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFRSH.reg;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask)
+{
+	return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->OTLO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->OTLO.reg;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask)
+{
+	return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->OTHI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->OTHI.reg;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask)
+{
+	return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->FT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->FT.reg;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask)
+{
+	return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BCFT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BCFT.reg;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask)
+{
+	return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MFT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MFT.reg;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask)
+{
+	return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PFT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PFT.reg;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask)
+{
+	return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BFT64.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BFT64.reg;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT127.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT127.reg;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT255.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT255.reg;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT511.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT511.reg;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT1023.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT1023.reg;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT1518.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT1518.reg;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const        hw,
+                                                                      hri_gmac_gtbft1518_reg_t mask)
+{
+	return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->GTBFT1518.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->GTBFT1518.reg;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask)
+{
+	return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TUR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TUR.reg;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask)
+{
+	return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SCF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SCF.reg;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask)
+{
+	return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MCF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MCF.reg;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask)
+{
+	return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EC.reg;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask)
+{
+	return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->LC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->LC.reg;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask)
+{
+	return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->DTF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->DTF.reg;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask)
+{
+	return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->CSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->CSE.reg;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask)
+{
+	return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ORLO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ORLO.reg;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask)
+{
+	return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ORHI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ORHI.reg;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask)
+{
+	return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->FR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->FR.reg;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask)
+{
+	return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BCFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BCFR.reg;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask)
+{
+	return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MFR.reg;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask)
+{
+	return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PFR.reg;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask)
+{
+	return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BFR64.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BFR64.reg;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR127.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR127.reg;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR255.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR255.reg;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR511.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR511.reg;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR1023.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR1023.reg;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR1518.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR1518.reg;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask)
+{
+	return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TMXBFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TMXBFR.reg;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask)
+{
+	return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->UFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->UFR.reg;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask)
+{
+	return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->OFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->OFR.reg;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask)
+{
+	return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->JR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->JR.reg;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask)
+{
+	return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->FCSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->FCSE.reg;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask)
+{
+	return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->LFFE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->LFFE.reg;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask)
+{
+	return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RSE.reg;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask)
+{
+	return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->AE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->AE.reg;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask)
+{
+	return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RRE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RRE.reg;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask)
+{
+	return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ROE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ROE.reg;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask)
+{
+	return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->IHCE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->IHCE.reg;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask)
+{
+	return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TCE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TCE.reg;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask)
+{
+	return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->UCE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->UCE.reg;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask)
+{
+	return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFTSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFTSL.reg;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask)
+{
+	return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFTN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFTN.reg;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask)
+{
+	return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFRSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFRSL.reg;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask)
+{
+	return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFRN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFRN.reg;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFTSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFTSL.reg;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFTN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFTN.reg;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFRSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFRSL.reg;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFRN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFRN.reg;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask)
+{
+	return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RLPITR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RLPITR.reg;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask)
+{
+	return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RLPITI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RLPITI.reg;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask)
+{
+	return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TLPITR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TLPITR.reg;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask)
+{
+	return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TLPITI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TLPITI.reg;
+}
+
+static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NCR.reg;
+}
+
+static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NCFGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NCFGR.reg;
+}
+
+static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->UR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->UR.reg;
+}
+
+static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->DCFGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->DCFGR.reg;
+}
+
+static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSR.reg;
+}
+
+static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RBQB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RBQB.reg;
+}
+
+static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBQB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBQB.reg;
+}
+
+static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RSR.reg;
+}
+
+static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ISR.reg;
+}
+
+static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MAN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MAN.reg;
+}
+
+static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TPQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TPQ.reg;
+}
+
+static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TPSF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TPSF.reg;
+}
+
+static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RPSF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RPSF.reg;
+}
+
+static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RJFML.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RJFML.reg;
+}
+
+static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->HRB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->HRB.reg;
+}
+
+static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->HRT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->HRT.reg;
+}
+
+static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TIDM[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index)
+{
+	return ((Gmac *)hw)->TIDM[index].reg;
+}
+
+static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->WOL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->WOL.reg;
+}
+
+static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->IPGS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->IPGS.reg;
+}
+
+static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SVLAN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SVLAN.reg;
+}
+
+static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TPFCP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TPFCP.reg;
+}
+
+static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SAMB1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SAMB1.reg;
+}
+
+static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SAMT1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SAMT1.reg;
+}
+
+static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NSC.reg;
+}
+
+static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SCL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SCL.reg;
+}
+
+static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SCH.reg;
+}
+
+static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TISUBN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TISUBN.reg;
+}
+
+static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSH.reg;
+}
+
+static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSSSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSSSL.reg;
+}
+
+static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSSN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSSN.reg;
+}
+
+static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSL.reg;
+}
+
+static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TN.reg;
+}
+
+static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TI.reg;
+}
+
+static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TA.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GMAC_E53_H_INCLUDED */
+#endif /* _SAME53_GMAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_hmatrixb_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_hmatrixb_e53.h
new file mode 100644
index 000000000..45f3d53a1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_hmatrixb_e53.h
@@ -0,0 +1,237 @@
+/**
+ * \file
+ *
+ * \brief SAM HMATRIXB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_HMATRIXB_COMPONENT_
+#ifndef _HRI_HMATRIXB_E53_H_INCLUDED_
+#define _HRI_HMATRIXB_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS)
+#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define HMATRIXB_CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_hmatrixb_pras_reg_t;
+typedef uint32_t hri_hmatrixb_prbs_reg_t;
+typedef uint32_t hri_hmatrixbprs_pras_reg_t;
+typedef uint32_t hri_hmatrixbprs_prbs_reg_t;
+
+static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRAS.reg;
+}
+
+static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRBS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_HMATRIXB_E53_H_INCLUDED */
+#endif /* _SAME53_HMATRIXB_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_i2s_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_i2s_e53.h
new file mode 100644
index 000000000..5a9eba18a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_i2s_e53.h
@@ -0,0 +1,3032 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_I2S_COMPONENT_
+#ifndef _HRI_I2S_E53_H_INCLUDED_
+#define _HRI_I2S_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_I2S_CRITICAL_SECTIONS)
+#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define I2S_CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_i2s_intenset_reg_t;
+typedef uint16_t hri_i2s_intflag_reg_t;
+typedef uint16_t hri_i2s_syncbusy_reg_t;
+typedef uint32_t hri_i2s_clkctrl_reg_t;
+typedef uint32_t hri_i2s_rxctrl_reg_t;
+typedef uint32_t hri_i2s_rxdata_reg_t;
+typedef uint32_t hri_i2s_txctrl_reg_t;
+typedef uint32_t hri_i2s_txdata_reg_t;
+typedef uint8_t  hri_i2s_ctrla_reg_t;
+
+static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	while (((I2s *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	((I2s *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTENSET.reg;
+}
+
+static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data)
+{
+	((I2s *)hw)->INTENSET.reg = data;
+	((I2s *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask)
+{
+	uint32_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->RXDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return ((I2s *)hw)->RXDATA.reg;
+}
+
+static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_ENABLE;
+	tmp |= value << I2S_CTRLA_ENABLE_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN0;
+	tmp |= value << I2S_CTRLA_CKEN0_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN1;
+	tmp |= value << I2S_CTRLA_CKEN1_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_TXEN;
+	tmp |= value << I2S_CTRLA_TXEN_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_RXEN;
+	tmp |= value << I2S_CTRLA_RXEN_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg = data;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	return ((I2s *)hw)->CTRLA.reg;
+}
+
+static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_BITDELAY;
+	tmp |= value << I2S_CLKCTRL_BITDELAY_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSSEL;
+	tmp |= value << I2S_CLKCTRL_FSSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSINV;
+	tmp |= value << I2S_CLKCTRL_FSINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSOUTINV;
+	tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKSEL;
+	tmp |= value << I2S_CLKCTRL_SCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKSEL;
+	tmp |= value << I2S_CLKCTRL_MCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKEN;
+	tmp |= value << I2S_CLKCTRL_MCKEN_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index,
+                                                                    hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk;
+	tmp |= I2S_CLKCTRL_SLOTSIZE(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk;
+	tmp |= I2S_CLKCTRL_NBSLOTS(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk;
+	tmp |= I2S_CLKCTRL_FSWIDTH(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index,
+                                                                  hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index,
+                                                                     hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKOUTDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((I2s *)hw)->CLKCTRL[index].reg;
+}
+
+static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_TXSAME;
+	tmp |= value << I2S_TXCTRL_TXSAME_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTADJ;
+	tmp |= value << I2S_TXCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_WORDADJ;
+	tmp |= value << I2S_TXCTRL_WORDADJ_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_BITREV;
+	tmp |= value << I2S_TXCTRL_BITREV_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS0;
+	tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS1;
+	tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS2;
+	tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS3;
+	tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS4;
+	tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS5;
+	tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS6;
+	tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS7;
+	tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_MONO;
+	tmp |= value << I2S_TXCTRL_MONO_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_DMA;
+	tmp |= value << I2S_TXCTRL_DMA_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk;
+	tmp |= I2S_TXCTRL_TXDEFAULT(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_DATASIZE_Msk;
+	tmp |= I2S_TXCTRL_DATASIZE(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_EXTEND_Msk;
+	tmp |= I2S_TXCTRL_EXTEND(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw)
+{
+	return ((I2s *)hw)->TXCTRL.reg;
+}
+
+static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_CLKSEL;
+	tmp |= value << I2S_RXCTRL_CLKSEL_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTADJ;
+	tmp |= value << I2S_RXCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_WORDADJ;
+	tmp |= value << I2S_RXCTRL_WORDADJ_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_BITREV;
+	tmp |= value << I2S_RXCTRL_BITREV_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS0;
+	tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS1;
+	tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS2;
+	tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS3;
+	tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS4;
+	tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS5;
+	tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS6;
+	tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS7;
+	tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_MONO;
+	tmp |= value << I2S_RXCTRL_MONO_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_DMA;
+	tmp |= value << I2S_RXCTRL_DMA_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_RXLOOP;
+	tmp |= value << I2S_RXCTRL_RXLOOP_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SERMODE_Msk;
+	tmp |= I2S_RXCTRL_SERMODE(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_DATASIZE_Msk;
+	tmp |= I2S_RXCTRL_DATASIZE(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_EXTEND_Msk;
+	tmp |= I2S_RXCTRL_EXTEND(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw)
+{
+	return ((I2s *)hw)->RXCTRL.reg;
+}
+
+static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXDATA.reg = data;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_I2S_E53_H_INCLUDED */
+#endif /* _SAME53_I2S_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_icm_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_icm_e53.h
new file mode 100644
index 000000000..32490785e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_icm_e53.h
@@ -0,0 +1,761 @@
+/**
+ * \file
+ *
+ * \brief SAM ICM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_ICM_COMPONENT_
+#ifndef _HRI_ICM_E53_H_INCLUDED_
+#define _HRI_ICM_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ICM_CRITICAL_SECTIONS)
+#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ICM_CRITICAL_SECTION_ENTER()
+#define ICM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_icm_cfg_reg_t;
+typedef uint32_t hri_icm_ctrl_reg_t;
+typedef uint32_t hri_icm_dscr_reg_t;
+typedef uint32_t hri_icm_hash_reg_t;
+typedef uint32_t hri_icm_imr_reg_t;
+typedef uint32_t hri_icm_isr_reg_t;
+typedef uint32_t hri_icm_sr_reg_t;
+typedef uint32_t hri_icm_uasr_reg_t;
+typedef uint32_t hri_icm_uihval_reg_t;
+typedef uint32_t hri_icmdescriptor_raddr_reg_t;
+typedef uint32_t hri_icmdescriptor_rcfg_reg_t;
+typedef uint32_t hri_icmdescriptor_rctrl_reg_t;
+typedef uint32_t hri_icmdescriptor_rnext_reg_t;
+
+static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_raddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RADDR.reg;
+}
+
+static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const            hw,
+                                                                          hri_icmdescriptor_rcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RCFG.reg;
+}
+
+static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_rctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RCTRL.reg;
+}
+
+static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_rnext_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RNEXT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RNEXT.reg;
+}
+
+static inline void hri_icm_set_IMR_URAD_bit(const void *const hw)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_URAD;
+}
+
+static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw)
+{
+	return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos;
+}
+
+static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
+	} else {
+		((Icm *)hw)->IER.reg = ICM_IMR_URAD;
+	}
+}
+
+static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
+}
+
+static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RHC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data);
+}
+
+static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask);
+}
+
+static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RDM(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data);
+}
+
+static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask);
+}
+
+static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RBE(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data);
+}
+
+static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask);
+}
+
+static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RWC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data);
+}
+
+static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask);
+}
+
+static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_REC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_REC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data);
+}
+
+static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask);
+}
+
+static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RSU(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data);
+}
+
+static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask);
+}
+
+static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = mask;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->IMR.reg;
+}
+
+static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = data;
+	((Icm *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->SR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->SR.reg;
+}
+
+static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->ISR.reg;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask)
+{
+	return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw)
+{
+	return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->UASR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->UASR.reg;
+}
+
+static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw)
+{
+	return ((Icm *)hw)->CFG.reg;
+}
+
+static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->DSCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->DSCR.reg;
+}
+
+static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->HASH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw)
+{
+	return ((Icm *)hw)->HASH.reg;
+}
+
+static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CTRL.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->UIHVAL[index].reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ICM_E53_H_INCLUDED */
+#endif /* _SAME53_ICM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_mclk_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_mclk_e53.h
new file mode 100644
index 000000000..6c92d91d1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_mclk_e53.h
@@ -0,0 +1,3476 @@
+/**
+ * \file
+ *
+ * \brief SAM MCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_MCLK_COMPONENT_
+#ifndef _HRI_MCLK_E53_H_INCLUDED_
+#define _HRI_MCLK_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
+#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MCLK_CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mclk_ahbmask_reg_t;
+typedef uint32_t hri_mclk_apbamask_reg_t;
+typedef uint32_t hri_mclk_apbbmask_reg_t;
+typedef uint32_t hri_mclk_apbcmask_reg_t;
+typedef uint32_t hri_mclk_apbdmask_reg_t;
+typedef uint8_t  hri_mclk_cpudiv_reg_t;
+typedef uint8_t  hri_mclk_hsdiv_reg_t;
+typedef uint8_t  hri_mclk_intenset_reg_t;
+typedef uint8_t  hri_mclk_intflag_reg_t;
+
+static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	((Mclk *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
+}
+
+static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+	} else {
+		((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+	}
+}
+
+static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTENSET.reg;
+}
+
+static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
+{
+	((Mclk *)hw)->INTENSET.reg = data;
+	((Mclk *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask)
+{
+	return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw)
+{
+	return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->HSDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->HSDIV.reg;
+}
+
+static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= ~MCLK_CPUDIV_DIV_Msk;
+	tmp |= MCLK_CPUDIV_DIV(data);
+	((Mclk *)hw)->CPUDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->CPUDIV.reg;
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB0;
+	tmp |= value << MCLK_AHBMASK_HPB0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB1;
+	tmp |= value << MCLK_AHBMASK_HPB1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB2;
+	tmp |= value << MCLK_AHBMASK_HPB2_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB3;
+	tmp |= value << MCLK_AHBMASK_HPB3_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DSU;
+	tmp |= value << MCLK_AHBMASK_DSU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HMATRIX;
+	tmp |= value << MCLK_AHBMASK_HMATRIX_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HSRAM;
+	tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_CMCC;
+	tmp |= value << MCLK_AHBMASK_CMCC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DMAC;
+	tmp |= value << MCLK_AHBMASK_DMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_USB;
+	tmp |= value << MCLK_AHBMASK_USB_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_BKUPRAM;
+	tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PAC;
+	tmp |= value << MCLK_AHBMASK_PAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_QSPI;
+	tmp |= value << MCLK_AHBMASK_QSPI_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_GMAC;
+	tmp |= value << MCLK_AHBMASK_GMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_SDHC0;
+	tmp |= value << MCLK_AHBMASK_SDHC0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_SDHC1;
+	tmp |= value << MCLK_AHBMASK_SDHC1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_ICM;
+	tmp |= value << MCLK_AHBMASK_ICM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PUKCC;
+	tmp |= value << MCLK_AHBMASK_PUKCC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_QSPI_2X;
+	tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->AHBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PAC;
+	tmp |= value << MCLK_APBAMASK_PAC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PM;
+	tmp |= value << MCLK_APBAMASK_PM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_MCLK;
+	tmp |= value << MCLK_APBAMASK_MCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RSTC;
+	tmp |= value << MCLK_APBAMASK_RSTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSCCTRL;
+	tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
+	tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SUPC;
+	tmp |= value << MCLK_APBAMASK_SUPC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_GCLK;
+	tmp |= value << MCLK_APBAMASK_GCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_WDT;
+	tmp |= value << MCLK_APBAMASK_WDT_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RTC;
+	tmp |= value << MCLK_APBAMASK_RTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_EIC;
+	tmp |= value << MCLK_APBAMASK_EIC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_FREQM;
+	tmp |= value << MCLK_APBAMASK_FREQM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SERCOM0;
+	tmp |= value << MCLK_APBAMASK_SERCOM0_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SERCOM1;
+	tmp |= value << MCLK_APBAMASK_SERCOM1_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_TC0;
+	tmp |= value << MCLK_APBAMASK_TC0_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_TC1;
+	tmp |= value << MCLK_APBAMASK_TC1_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBAMASK.reg;
+}
+
+static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_USB;
+	tmp |= value << MCLK_APBBMASK_USB_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_DSU;
+	tmp |= value << MCLK_APBBMASK_DSU_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_NVMCTRL;
+	tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_PORT;
+	tmp |= value << MCLK_APBBMASK_PORT_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_HMATRIX;
+	tmp |= value << MCLK_APBBMASK_HMATRIX_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_EVSYS;
+	tmp |= value << MCLK_APBBMASK_EVSYS_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_SERCOM2;
+	tmp |= value << MCLK_APBBMASK_SERCOM2_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_SERCOM3;
+	tmp |= value << MCLK_APBBMASK_SERCOM3_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TCC0;
+	tmp |= value << MCLK_APBBMASK_TCC0_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TCC1;
+	tmp |= value << MCLK_APBBMASK_TCC1_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TC2;
+	tmp |= value << MCLK_APBBMASK_TC2_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TC3;
+	tmp |= value << MCLK_APBBMASK_TC3_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_RAMECC;
+	tmp |= value << MCLK_APBBMASK_RAMECC_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_GMAC;
+	tmp |= value << MCLK_APBCMASK_GMAC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC2;
+	tmp |= value << MCLK_APBCMASK_TCC2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC3;
+	tmp |= value << MCLK_APBCMASK_TCC3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC4;
+	tmp |= value << MCLK_APBCMASK_TC4_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC5;
+	tmp |= value << MCLK_APBCMASK_TC5_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_PDEC;
+	tmp |= value << MCLK_APBCMASK_PDEC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AC;
+	tmp |= value << MCLK_APBCMASK_AC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AES;
+	tmp |= value << MCLK_APBCMASK_AES_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TRNG;
+	tmp |= value << MCLK_APBCMASK_TRNG_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_ICM;
+	tmp |= value << MCLK_APBCMASK_ICM_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_QSPI;
+	tmp |= value << MCLK_APBCMASK_QSPI_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_CCL;
+	tmp |= value << MCLK_APBCMASK_CCL_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBCMASK.reg;
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM4;
+	tmp |= value << MCLK_APBDMASK_SERCOM4_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM5;
+	tmp |= value << MCLK_APBDMASK_SERCOM5_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM6;
+	tmp |= value << MCLK_APBDMASK_SERCOM6_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM7;
+	tmp |= value << MCLK_APBDMASK_SERCOM7_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TCC4;
+	tmp |= value << MCLK_APBDMASK_TCC4_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TC6;
+	tmp |= value << MCLK_APBDMASK_TC6_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TC7;
+	tmp |= value << MCLK_APBDMASK_TC7_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_ADC0;
+	tmp |= value << MCLK_APBDMASK_ADC0_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_ADC1;
+	tmp |= value << MCLK_APBDMASK_ADC1_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_DAC;
+	tmp |= value << MCLK_APBDMASK_DAC_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_I2S;
+	tmp |= value << MCLK_APBDMASK_I2S_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_PCC;
+	tmp |= value << MCLK_APBDMASK_PCC_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBDMASK.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MCLK_E53_H_INCLUDED */
+#endif /* _SAME53_MCLK_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_nvmctrl_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_nvmctrl_e53.h
new file mode 100644
index 000000000..9c836ac7c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_nvmctrl_e53.h
@@ -0,0 +1,1618 @@
+/**
+ * \file
+ *
+ * \brief SAM NVMCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_NVMCTRL_COMPONENT_
+#ifndef _HRI_NVMCTRL_E53_H_INCLUDED_
+#define _HRI_NVMCTRL_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
+#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVMCTRL_CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_nvmctrl_ctrla_reg_t;
+typedef uint16_t hri_nvmctrl_ctrlb_reg_t;
+typedef uint16_t hri_nvmctrl_intenset_reg_t;
+typedef uint16_t hri_nvmctrl_intflag_reg_t;
+typedef uint16_t hri_nvmctrl_status_reg_t;
+typedef uint32_t hri_nvmctrl_addr_reg_t;
+typedef uint32_t hri_nvmctrl_eccerr_reg_t;
+typedef uint32_t hri_nvmctrl_param_reg_t;
+typedef uint32_t hri_nvmctrl_pbldata_reg_t;
+typedef uint32_t hri_nvmctrl_runlock_reg_t;
+typedef uint32_t hri_nvmctrl_seestat_reg_t;
+typedef uint8_t  hri_nvmctrl_dbgctrl_reg_t;
+typedef uint8_t  hri_nvmctrl_seecfg_reg_t;
+
+static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_nvmctrl_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC;
+}
+
+static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_nvmctrl_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = data;
+	((Nvmctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->PARAM.reg;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const        hw,
+                                                                          hri_nvmctrl_status_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->STATUS.reg;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const         hw,
+                                                                           hri_nvmctrl_runlock_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const         hw,
+                                                                    hri_nvmctrl_runlock_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->RUNLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->RUNLOCK.reg;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index,
+                                                                        hri_nvmctrl_pbldata_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index)
+{
+	return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index,
+                                                                    hri_nvmctrl_pbldata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvmctrl *)hw)->PBLDATA[index].reg;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const        hw,
+                                                                      hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const        hw,
+                                                                       hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const        hw,
+                                                                       hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ECCERR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ECCERR.reg;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const         hw,
+                                                                        hri_nvmctrl_seestat_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const         hw,
+                                                                       hri_nvmctrl_seestat_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const         hw,
+                                                                    hri_nvmctrl_seestat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEESTAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->SEESTAT.reg;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AUTOWS;
+	tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_SUSPEN;
+	tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AHBNS0;
+	tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AHBNS1;
+	tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CACHEDIS0;
+	tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CACHEDIS1;
+	tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_WMODE_Msk;
+	tmp |= NVMCTRL_CTRLA_WMODE(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_PRM_Msk;
+	tmp |= NVMCTRL_CTRLA_PRM(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_RWS_Msk;
+	tmp |= NVMCTRL_CTRLA_RWS(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLA.reg;
+}
+
+static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
+	tmp |= NVMCTRL_ADDR_ADDR(data);
+	((Nvmctrl *)hw)->ADDR.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ADDR.reg;
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= ~NVMCTRL_DBGCTRL_ECCDIS;
+	tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos;
+	((Nvmctrl *)hw)->DBGCTRL.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= ~NVMCTRL_DBGCTRL_ECCELOG;
+	tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos;
+	((Nvmctrl *)hw)->DBGCTRL.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const         hw,
+                                                                    hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= ~NVMCTRL_SEECFG_WMODE;
+	tmp |= value << NVMCTRL_SEECFG_WMODE_Pos;
+	((Nvmctrl *)hw)->SEECFG.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= ~NVMCTRL_SEECFG_APRDIS;
+	tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos;
+	((Nvmctrl *)hw)->SEECFG.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->SEECFG.reg;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVMCTRL_E53_H_INCLUDED */
+#endif /* _SAME53_NVMCTRL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_osc32kctrl_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_osc32kctrl_e53.h
new file mode 100644
index 000000000..db3b4c1e7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_osc32kctrl_e53.h
@@ -0,0 +1,1199 @@
+/**
+ * \file
+ *
+ * \brief SAM OSC32KCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_OSC32KCTRL_COMPONENT_
+#ifndef _HRI_OSC32KCTRL_E53_H_INCLUDED_
+#define _HRI_OSC32KCTRL_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS)
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_osc32kctrl_xosc32k_reg_t;
+typedef uint32_t hri_osc32kctrl_intenset_reg_t;
+typedef uint32_t hri_osc32kctrl_intflag_reg_t;
+typedef uint32_t hri_osc32kctrl_osculp32k_reg_t;
+typedef uint32_t hri_osc32kctrl_status_reg_t;
+typedef uint8_t  hri_osc32kctrl_cfdctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_evctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_rtcctrl_reg_t;
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const             hw,
+                                                                         hri_osc32kctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = data;
+	((Osc32kctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const            hw,
+                                                                                hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk;
+	tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data);
+	((Osc32kctrl *)hw)->RTCCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->RTCCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN32K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN1K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const            hw,
+                                                                                 hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_STARTUP(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const            hw,
+                                                                             hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_CGM(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->XOSC32K.reg;
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->CFDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	((Osc32kctrl *)hw)->EVCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const              hw,
+                                                                                   hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk;
+	tmp |= OSC32KCTRL_OSCULP32K_CALIB(data);
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const              hw,
+                                                                              hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->OSCULP32K.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSC32KCTRL_E53_H_INCLUDED */
+#endif /* _SAME53_OSC32KCTRL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_oscctrl_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_oscctrl_e53.h
new file mode 100644
index 000000000..0637ba29b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_oscctrl_e53.h
@@ -0,0 +1,4441 @@
+/**
+ * \file
+ *
+ * \brief SAM OSCCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_OSCCTRL_COMPONENT_
+#ifndef _HRI_OSCCTRL_E53_H_INCLUDED_
+#define _HRI_OSCCTRL_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS)
+#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSCCTRL_CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_oscctrl_dfllmul_reg_t;
+typedef uint32_t hri_oscctrl_dfllval_reg_t;
+typedef uint32_t hri_oscctrl_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrl_dpllratio_reg_t;
+typedef uint32_t hri_oscctrl_dpllstatus_reg_t;
+typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t;
+typedef uint32_t hri_oscctrl_intenset_reg_t;
+typedef uint32_t hri_oscctrl_intflag_reg_t;
+typedef uint32_t hri_oscctrl_status_reg_t;
+typedef uint32_t hri_oscctrl_xoscctrl_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllratio_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t;
+typedef uint8_t  hri_oscctrl_dfllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_dfllctrlb_reg_t;
+typedef uint8_t  hri_oscctrl_dfllsync_reg_t;
+typedef uint8_t  hri_oscctrl_dpllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_evctrl_reg_t;
+typedef uint8_t  hri_oscctrldpll_dpllctrla_reg_t;
+
+static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg;
+}
+
+static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index,
+                                             hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index,
+                                          hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)
+	       >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const              hw,
+                                                                                  hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const            hw,
+                                                                              hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = data;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw)
+{
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const           hw,
+                                                                                   hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = data;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw)
+{
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const           hw,
+                                                                                  hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const           hw,
+                                                                                  hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const           hw,
+                                                                                 hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const           hw,
+                                                                                     hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE)
+	       >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)
+	       >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t
+hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+	       >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+	       >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index)
+{
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t
+hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t
+hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index)
+{
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw,
+                                                                              uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw,
+                                                                                  uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_oscctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_oscctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data)
+{
+	((Oscctrl *)hw)->INTENSET.reg = data;
+	((Oscctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO0;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO1;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENALC;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                     hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_IPTAT(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                     hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_IMULT(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                                             hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                         hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_STARTUP(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                         hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                                              hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index,
+                                                                      hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const           hw,
+                                                                        hri_oscctrl_dfllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_MODE;
+	tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_STABLE;
+	tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_LLAW;
+	tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM;
+	tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS;
+	tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS;
+	tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC;
+	tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK;
+	tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const           hw,
+                                                                        hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLCTRLB.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_FINE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const         hw,
+                                                                          hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_COARSE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk;
+	tmp |= OSCCTRL_DFLLVAL_DIFF(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLVAL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const         hw,
+                                                                       hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk;
+	tmp |= OSCCTRL_DFLLMUL_MUL(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_FSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_CSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLMUL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_ENABLE;
+	tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllsync_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLSYNC.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSCCTRL_E53_H_INCLUDED */
+#endif /* _SAME53_OSCCTRL_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pac_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pac_e53.h
new file mode 100644
index 000000000..6849792e7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pac_e53.h
@@ -0,0 +1,1484 @@
+/**
+ * \file
+ *
+ * \brief SAM PAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_PAC_COMPONENT_
+#ifndef _HRI_PAC_E53_H_INCLUDED_
+#define _HRI_PAC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PAC_CRITICAL_SECTIONS)
+#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PAC_CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pac_intflaga_reg_t;
+typedef uint32_t hri_pac_intflagahb_reg_t;
+typedef uint32_t hri_pac_intflagb_reg_t;
+typedef uint32_t hri_pac_intflagc_reg_t;
+typedef uint32_t hri_pac_intflagd_reg_t;
+typedef uint32_t hri_pac_statusa_reg_t;
+typedef uint32_t hri_pac_statusb_reg_t;
+typedef uint32_t hri_pac_statusc_reg_t;
+typedef uint32_t hri_pac_statusd_reg_t;
+typedef uint32_t hri_pac_wrctrl_reg_t;
+typedef uint8_t  hri_pac_evctrl_reg_t;
+typedef uint8_t  hri_pac_intenset_reg_t;
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGAHB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGAHB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1;
+}
+
+static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0;
+}
+
+static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGA.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGA.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU;
+}
+
+static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX;
+}
+
+static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS;
+}
+
+static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2;
+}
+
+static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3;
+}
+
+static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG;
+}
+
+static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGC.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGC.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7;
+}
+
+static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0;
+}
+
+static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1;
+}
+
+static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC;
+}
+
+static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S;
+}
+
+static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC;
+}
+
+static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGD.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGD.reg = mask;
+}
+
+static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+}
+
+static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+	} else {
+		((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+}
+
+static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data)
+{
+	((Pac *)hw)->INTENSET.reg = data;
+	((Pac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSC.reg;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos;
+}
+
+static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSD.reg;
+}
+
+static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_PERID_Msk;
+	tmp |= PAC_WRCTRL_PERID(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_KEY_Msk;
+	tmp |= PAC_WRCTRL_KEY(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->WRCTRL.reg;
+}
+
+static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= ~PAC_EVCTRL_ERREO;
+	tmp |= value << PAC_EVCTRL_ERREO_Pos;
+	((Pac *)hw)->EVCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PAC_E53_H_INCLUDED */
+#endif /* _SAME53_PAC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pcc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pcc_e53.h
new file mode 100644
index 000000000..b0952faf0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pcc_e53.h
@@ -0,0 +1,298 @@
+/**
+ * \file
+ *
+ * \brief SAM PCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_PCC_COMPONENT_
+#ifndef _HRI_PCC_E53_H_INCLUDED_
+#define _HRI_PCC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PCC_CRITICAL_SECTIONS)
+#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PCC_CRITICAL_SECTION_ENTER()
+#define PCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pcc_imr_reg_t;
+typedef uint32_t hri_pcc_isr_reg_t;
+typedef uint32_t hri_pcc_mr_reg_t;
+typedef uint32_t hri_pcc_rhr_reg_t;
+typedef uint32_t hri_pcc_wpmr_reg_t;
+typedef uint32_t hri_pcc_wpsr_reg_t;
+
+static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw)
+{
+	((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
+}
+
+static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos;
+}
+
+static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
+	} else {
+		((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
+	}
+}
+
+static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw)
+{
+	((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
+}
+
+static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw)
+{
+	((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
+}
+
+static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos;
+}
+
+static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
+	} else {
+		((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
+	}
+}
+
+static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw)
+{
+	((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
+}
+
+static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	((Pcc *)hw)->IER.reg = mask;
+}
+
+static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->IMR.reg;
+}
+
+static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data)
+{
+	((Pcc *)hw)->IER.reg = data;
+	((Pcc *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	((Pcc *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos;
+}
+
+static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos;
+}
+
+static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->ISR.reg;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask)
+{
+	return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw)
+{
+	return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->RHR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->RHR.reg;
+}
+
+static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->WPSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->WPSR.reg;
+}
+
+static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg |= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->MR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg = data;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg &= ~mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg ^= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->MR.reg;
+}
+
+static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg |= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->WPMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg = data;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg &= ~mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg ^= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->WPMR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PCC_E53_H_INCLUDED */
+#endif /* _SAME53_PCC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pdec_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pdec_e53.h
new file mode 100644
index 000000000..89acdf568
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pdec_e53.h
@@ -0,0 +1,2684 @@
+/**
+ * \file
+ *
+ * \brief SAM PDEC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_PDEC_COMPONENT_
+#ifndef _HRI_PDEC_E53_H_INCLUDED_
+#define _HRI_PDEC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PDEC_CRITICAL_SECTIONS)
+#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PDEC_CRITICAL_SECTION_ENTER()
+#define PDEC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_pdec_evctrl_reg_t;
+typedef uint16_t hri_pdec_status_reg_t;
+typedef uint32_t hri_pdec_cc_reg_t;
+typedef uint32_t hri_pdec_ccbuf_reg_t;
+typedef uint32_t hri_pdec_count_reg_t;
+typedef uint32_t hri_pdec_ctrla_reg_t;
+typedef uint32_t hri_pdec_syncbusy_reg_t;
+typedef uint8_t  hri_pdec_ctrlbset_reg_t;
+typedef uint8_t  hri_pdec_dbgctrl_reg_t;
+typedef uint8_t  hri_pdec_filter_reg_t;
+typedef uint8_t  hri_pdec_filterbuf_reg_t;
+typedef uint8_t  hri_pdec_intenset_reg_t;
+typedef uint8_t  hri_pdec_intflag_reg_t;
+typedef uint8_t  hri_pdec_presc_reg_t;
+typedef uint8_t  hri_pdec_prescbuf_reg_t;
+
+static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg)
+{
+	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg)
+{
+	return ((Pdec *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
+}
+
+static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
+}
+
+static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
+}
+
+static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
+}
+
+static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0;
+}
+
+static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1;
+}
+
+static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
+}
+
+static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
+}
+
+static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
+}
+
+static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
+}
+
+static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0;
+}
+
+static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1;
+}
+
+static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask)
+{
+	((Pdec *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD;
+	} else {
+		((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD;
+}
+
+static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data);
+	((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data)
+{
+	((Pdec *)hw)->CTRLBSET.reg = data;
+	((Pdec *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF;
+}
+
+static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF;
+}
+
+static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR;
+}
+
+static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR;
+}
+
+static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR;
+}
+
+static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR;
+}
+
+static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC;
+}
+
+static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC;
+}
+
+static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0;
+}
+
+static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0;
+}
+
+static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1;
+}
+
+static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1;
+}
+
+static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	((Pdec *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data)
+{
+	((Pdec *)hw)->INTENSET.reg = data;
+	((Pdec *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	((Pdec *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ENABLE;
+	tmp |= value << PDEC_CTRLA_ENABLE_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_RUNSTDBY;
+	tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ALOCK;
+	tmp |= value << PDEC_CTRLA_ALOCK_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_SWAP;
+	tmp |= value << PDEC_CTRLA_SWAP_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PEREN;
+	tmp |= value << PDEC_CTRLA_PEREN_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN0;
+	tmp |= value << PDEC_CTRLA_PINEN0_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN1;
+	tmp |= value << PDEC_CTRLA_PINEN1_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN2;
+	tmp |= value << PDEC_CTRLA_PINEN2_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN0;
+	tmp |= value << PDEC_CTRLA_PINVEN0_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN1;
+	tmp |= value << PDEC_CTRLA_PINVEN1_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN2;
+	tmp |= value << PDEC_CTRLA_PINVEN2_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_MODE_Msk;
+	tmp |= PDEC_CTRLA_MODE(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_CONF_Msk;
+	tmp |= PDEC_CTRLA_CONF(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ANGULAR_Msk;
+	tmp |= PDEC_CTRLA_ANGULAR(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_MAXCMP_Msk;
+	tmp |= PDEC_CTRLA_MAXCMP(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	return ((Pdec *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_OVFEO;
+	tmp |= value << PDEC_EVCTRL_OVFEO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_ERREO;
+	tmp |= value << PDEC_EVCTRL_ERREO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_DIREO;
+	tmp |= value << PDEC_EVCTRL_DIREO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_VLCEO;
+	tmp |= value << PDEC_EVCTRL_VLCEO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_MCEO0;
+	tmp |= value << PDEC_EVCTRL_MCEO0_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_MCEO1;
+	tmp |= value << PDEC_EVCTRL_MCEO1_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVACT_Msk;
+	tmp |= PDEC_EVCTRL_EVACT(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVINV_Msk;
+	tmp |= PDEC_EVCTRL_EVINV(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVEI_Msk;
+	tmp |= PDEC_EVCTRL_EVEI(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg = data;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp &= ~PDEC_DBGCTRL_DBGRUN;
+	tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos;
+	((Pdec *)hw)->DBGCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg |= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg = data;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg &= ~mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg ^= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp &= ~PDEC_PRESC_PRESC_Msk;
+	tmp |= PDEC_PRESC_PRESC(data);
+	((Pdec *)hw)->PRESC.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	return ((Pdec *)hw)->PRESC.reg;
+}
+
+static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp &= ~PDEC_FILTER_FILTER_Msk;
+	tmp |= PDEC_FILTER_FILTER(data);
+	((Pdec *)hw)->FILTER.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	return ((Pdec *)hw)->FILTER.reg;
+}
+
+static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const       hw,
+                                                                        hri_pdec_prescbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk;
+	tmp |= PDEC_PRESCBUF_PRESCBUF(data);
+	((Pdec *)hw)->PRESCBUF.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->PRESCBUF.reg;
+}
+
+static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const        hw,
+                                                                           hri_pdec_filterbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk;
+	tmp |= PDEC_FILTERBUF_FILTERBUF(data);
+	((Pdec *)hw)->FILTERBUF.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->FILTERBUF.reg;
+}
+
+static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp &= ~PDEC_COUNT_COUNT_Msk;
+	tmp |= PDEC_COUNT_COUNT(data);
+	((Pdec *)hw)->COUNT.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	return ((Pdec *)hw)->COUNT.reg;
+}
+
+static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp &= ~PDEC_CC_CC_Msk;
+	tmp |= PDEC_CC_CC(data);
+	((Pdec *)hw)->CC[index].reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	return ((Pdec *)hw)->CC[index].reg;
+}
+
+static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                               hri_pdec_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp &= ~PDEC_CCBUF_CCBUF_Msk;
+	tmp |= PDEC_CCBUF_CCBUF(data);
+	((Pdec *)hw)->CCBUF[index].reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                          hri_pdec_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PDEC_E53_H_INCLUDED */
+#endif /* _SAME53_PDEC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pm_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pm_e53.h
new file mode 100644
index 000000000..f938ffa5b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_pm_e53.h
@@ -0,0 +1,820 @@
+/**
+ * \file
+ *
+ * \brief SAM PM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_PM_COMPONENT_
+#ifndef _HRI_PM_E53_H_INCLUDED_
+#define _HRI_PM_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PM_CRITICAL_SECTIONS)
+#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PM_CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_pm_bkupcfg_reg_t;
+typedef uint8_t hri_pm_ctrla_reg_t;
+typedef uint8_t hri_pm_hibcfg_reg_t;
+typedef uint8_t hri_pm_intenset_reg_t;
+typedef uint8_t hri_pm_intflag_reg_t;
+typedef uint8_t hri_pm_pwsakdly_reg_t;
+typedef uint8_t hri_pm_sleepcfg_reg_t;
+typedef uint8_t hri_pm_stdbycfg_reg_t;
+
+static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY;
+}
+
+static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	((Pm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY;
+}
+
+static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY;
+	} else {
+		((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY;
+	}
+}
+
+static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY;
+}
+
+static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
+{
+	((Pm *)hw)->INTENSET.reg = data;
+	((Pm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= ~PM_CTRLA_IORET;
+	tmp |= value << PM_CTRLA_IORET_Pos;
+	((Pm *)hw)->CTRLA.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
+	tmp |= PM_SLEEPCFG_SLEEPMODE(data);
+	((Pm *)hw)->SLEEPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->SLEEPCFG.reg;
+}
+
+static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_RAMCFG_Msk;
+	tmp |= PM_STDBYCFG_RAMCFG(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_FASTWKUP_Msk;
+	tmp |= PM_STDBYCFG_FASTWKUP(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->STDBYCFG.reg;
+}
+
+static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= ~PM_HIBCFG_RAMCFG_Msk;
+	tmp |= PM_HIBCFG_RAMCFG(data);
+	((Pm *)hw)->HIBCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= ~PM_HIBCFG_BRAMCFG_Msk;
+	tmp |= PM_HIBCFG_BRAMCFG(data);
+	((Pm *)hw)->HIBCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->HIBCFG.reg;
+}
+
+static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp &= ~PM_BKUPCFG_BRAMCFG_Msk;
+	tmp |= PM_BKUPCFG_BRAMCFG(data);
+	((Pm *)hw)->BKUPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->BKUPCFG.reg;
+}
+
+static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= ~PM_PWSAKDLY_IGNACK;
+	tmp |= value << PM_PWSAKDLY_IGNACK_Pos;
+	((Pm *)hw)->PWSAKDLY.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= ~PM_PWSAKDLY_DLYVAL_Msk;
+	tmp |= PM_PWSAKDLY_DLYVAL(data);
+	((Pm *)hw)->PWSAKDLY.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw)
+{
+	return ((Pm *)hw)->PWSAKDLY.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PM_E53_H_INCLUDED */
+#endif /* _SAME53_PM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_port_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_port_e53.h
new file mode 100644
index 000000000..d2be04d03
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_port_e53.h
@@ -0,0 +1,2528 @@
+/**
+ * \file
+ *
+ * \brief SAM PORT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_PORT_COMPONENT_
+#ifndef _HRI_PORT_E53_H_INCLUDED_
+#define _HRI_PORT_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
+#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PORT_CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_port_ctrl_reg_t;
+typedef uint32_t hri_port_dir_reg_t;
+typedef uint32_t hri_port_evctrl_reg_t;
+typedef uint32_t hri_port_in_reg_t;
+typedef uint32_t hri_port_out_reg_t;
+typedef uint32_t hri_port_wrconfig_reg_t;
+typedef uint32_t hri_portgroup_ctrl_reg_t;
+typedef uint32_t hri_portgroup_dir_reg_t;
+typedef uint32_t hri_portgroup_evctrl_reg_t;
+typedef uint32_t hri_portgroup_in_reg_t;
+typedef uint32_t hri_portgroup_out_reg_t;
+typedef uint32_t hri_portgroup_wrconfig_reg_t;
+typedef uint8_t  hri_port_pincfg_reg_t;
+typedef uint8_t  hri_port_pmux_reg_t;
+typedef uint8_t  hri_portgroup_pincfg_reg_t;
+typedef uint8_t  hri_portgroup_pmux_reg_t;
+
+static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data);
+	((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->DIR.reg;
+}
+
+static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = data;
+	((PortGroup *)hw)->DIRCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = mask;
+}
+
+static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data);
+	((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->OUT.reg;
+}
+
+static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = data;
+	((PortGroup *)hw)->OUTCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->IN.reg;
+}
+
+static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((PortGroup *)hw)->CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->CTRL.reg;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
+                                                             hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PMUX[index].reg;
+}
+
+static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
+                                                                 hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PINCFG[index].reg;
+}
+
+static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data);
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+}
+
+static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
+}
+
+static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data);
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+}
+
+static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_in_reg_t mask)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+}
+
+static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].CTRL.reg;
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+}
+
+static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                         hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                        hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                            hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+}
+
+static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                  bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                            uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+}
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PORT_E53_H_INCLUDED */
+#endif /* _SAME53_PORT_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_qspi_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_qspi_e53.h
new file mode 100644
index 000000000..0455eb3f1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_qspi_e53.h
@@ -0,0 +1,2058 @@
+/**
+ * \file
+ *
+ * \brief SAM QSPI
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_QSPI_COMPONENT_
+#ifndef _HRI_QSPI_E53_H_INCLUDED_
+#define _HRI_QSPI_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_QSPI_CRITICAL_SECTIONS)
+#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define QSPI_CRITICAL_SECTION_ENTER()
+#define QSPI_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_qspi_baud_reg_t;
+typedef uint32_t hri_qspi_ctrla_reg_t;
+typedef uint32_t hri_qspi_ctrlb_reg_t;
+typedef uint32_t hri_qspi_instraddr_reg_t;
+typedef uint32_t hri_qspi_instrctrl_reg_t;
+typedef uint32_t hri_qspi_instrframe_reg_t;
+typedef uint32_t hri_qspi_intenset_reg_t;
+typedef uint32_t hri_qspi_intflag_reg_t;
+typedef uint32_t hri_qspi_rxdata_reg_t;
+typedef uint32_t hri_qspi_scrambctrl_reg_t;
+typedef uint32_t hri_qspi_scrambkey_reg_t;
+typedef uint32_t hri_qspi_status_reg_t;
+typedef uint32_t hri_qspi_txdata_reg_t;
+
+static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC;
+}
+
+static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE;
+}
+
+static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC;
+}
+
+static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE;
+}
+
+static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
+}
+
+static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC;
+}
+
+static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE;
+}
+
+static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC;
+}
+
+static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE;
+}
+
+static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
+}
+
+static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask)
+{
+	((Qspi *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC;
+}
+
+static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC;
+}
+
+static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE;
+}
+
+static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE;
+}
+
+static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC;
+}
+
+static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC;
+}
+
+static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR;
+}
+
+static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR;
+}
+
+static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE;
+}
+
+static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE;
+}
+
+static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND;
+}
+
+static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND;
+}
+
+static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	((Qspi *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INTENSET.reg;
+}
+
+static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data)
+{
+	((Qspi *)hw)->INTENSET.reg = data;
+	((Qspi *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	((Qspi *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask)
+{
+	return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw)
+{
+	return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->RXDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->RXDATA.reg;
+}
+
+static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos;
+}
+
+static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos;
+}
+
+static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->STATUS.reg;
+}
+
+static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= ~QSPI_CTRLA_ENABLE;
+	tmp |= value << QSPI_CTRLA_ENABLE_Pos;
+	((Qspi *)hw)->CTRLA.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= ~QSPI_CTRLA_LASTXFER;
+	tmp |= value << QSPI_CTRLA_LASTXFER_Pos;
+	((Qspi *)hw)->CTRLA.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->CTRLA.reg;
+}
+
+static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_MODE;
+	tmp |= value << QSPI_CTRLB_MODE_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_LOOPEN;
+	tmp |= value << QSPI_CTRLB_LOOPEN_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_WDRBT;
+	tmp |= value << QSPI_CTRLB_WDRBT_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_SMEMREG;
+	tmp |= value << QSPI_CTRLB_SMEMREG_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_CSMODE_Msk;
+	tmp |= QSPI_CTRLB_CSMODE(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DATALEN_Msk;
+	tmp |= QSPI_CTRLB_DATALEN(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DLYBCT_Msk;
+	tmp |= QSPI_CTRLB_DLYBCT(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DLYCS_Msk;
+	tmp |= QSPI_CTRLB_DLYCS(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->CTRLB.reg;
+}
+
+static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_CPOL;
+	tmp |= value << QSPI_BAUD_CPOL_Pos;
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_CPHA;
+	tmp |= value << QSPI_BAUD_CPHA_Pos;
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_BAUD_Msk;
+	tmp |= QSPI_BAUD_BAUD(data);
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_DLYBS_Msk;
+	tmp |= QSPI_BAUD_DLYBS(data);
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->BAUD.reg;
+}
+
+static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_qspi_instraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp &= ~QSPI_INSTRADDR_ADDR_Msk;
+	tmp |= QSPI_INSTRADDR_ADDR(data);
+	((Qspi *)hw)->INSTRADDR.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRADDR.reg;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const        hw,
+                                                                       hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= ~QSPI_INSTRCTRL_INSTR_Msk;
+	tmp |= QSPI_INSTRCTRL_INSTR(data);
+	((Qspi *)hw)->INSTRCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const        hw,
+                                                                         hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk;
+	tmp |= QSPI_INSTRCTRL_OPTCODE(data);
+	((Qspi *)hw)->INSTRCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRCTRL.reg;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_INSTREN;
+	tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_ADDREN;
+	tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_OPTCODEEN;
+	tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DATAEN;
+	tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_ADDRLEN;
+	tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_CRMODE;
+	tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DDREN;
+	tmp |= value << QSPI_INSTRFRAME_DDREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const         hw,
+                                                                         hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk;
+	tmp |= QSPI_INSTRFRAME_WIDTH(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const         hw,
+                                                                              hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk;
+	tmp |= QSPI_INSTRFRAME_OPTCODELEN(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const         hw,
+                                                                           hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk;
+	tmp |= QSPI_INSTRFRAME_TFRTYPE(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const         hw,
+                                                                            hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk;
+	tmp |= QSPI_INSTRFRAME_DUMMYLEN(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const         hw,
+                                                                    hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRFRAME.reg;
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= ~QSPI_SCRAMBCTRL_ENABLE;
+	tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos;
+	((Qspi *)hw)->SCRAMBCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS;
+	tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos;
+	((Qspi *)hw)->SCRAMBCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const         hw,
+                                                                    hri_qspi_scrambctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->SCRAMBCTRL.reg;
+}
+
+static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->TXDATA.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBKEY.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_QSPI_E53_H_INCLUDED */
+#endif /* _SAME53_QSPI_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ramecc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ramecc_e53.h
new file mode 100644
index 000000000..863a6c95d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_ramecc_e53.h
@@ -0,0 +1,362 @@
+/**
+ * \file
+ *
+ * \brief SAM RAMECC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_RAMECC_COMPONENT_
+#ifndef _HRI_RAMECC_E53_H_INCLUDED_
+#define _HRI_RAMECC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS)
+#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RAMECC_CRITICAL_SECTION_ENTER()
+#define RAMECC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ramecc_erraddr_reg_t;
+typedef uint8_t  hri_ramecc_dbgctrl_reg_t;
+typedef uint8_t  hri_ramecc_intenset_reg_t;
+typedef uint8_t  hri_ramecc_intflag_reg_t;
+typedef uint8_t  hri_ramecc_status_reg_t;
+
+static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
+}
+
+static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
+}
+
+static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
+{
+	((Ramecc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
+	} else {
+		((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
+	}
+}
+
+static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
+}
+
+static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
+}
+
+static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos;
+}
+
+static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
+	} else {
+		((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
+	}
+}
+
+static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
+}
+
+static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	((Ramecc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data)
+{
+	((Ramecc *)hw)->INTENSET.reg = data;
+	((Ramecc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	((Ramecc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos;
+}
+
+static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->STATUS.reg;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const        hw,
+                                                                         hri_ramecc_erraddr_reg_t mask)
+{
+	return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw)
+{
+	return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ramecc *)hw)->ERRADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->ERRADDR.reg;
+}
+
+static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RAMECC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= ~RAMECC_DBGCTRL_ECCDIS;
+	tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos;
+	((Ramecc *)hw)->DBGCTRL.reg = tmp;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RAMECC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= ~RAMECC_DBGCTRL_ECCELOG;
+	tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos;
+	((Ramecc *)hw)->DBGCTRL.reg = tmp;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg = data;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->DBGCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RAMECC_E53_H_INCLUDED */
+#endif /* _SAME53_RAMECC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_rstc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_rstc_e53.h
new file mode 100644
index 000000000..63db08cb5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_rstc_e53.h
@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief SAM RSTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_RSTC_COMPONENT_
+#ifndef _HRI_RSTC_E53_H_INCLUDED_
+#define _HRI_RSTC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
+#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RSTC_CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_rstc_bkupexit_reg_t;
+typedef uint8_t hri_rstc_rcause_reg_t;
+
+static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->RCAUSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->RCAUSE.reg;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->BKUPEXIT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->BKUPEXIT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RSTC_E53_H_INCLUDED */
+#endif /* _SAME53_RSTC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_rtc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_rtc_e53.h
new file mode 100644
index 000000000..d117eb4c8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_rtc_e53.h
@@ -0,0 +1,10139 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_RTC_COMPONENT_
+#ifndef _HRI_RTC_E53_H_INCLUDED_
+#define _HRI_RTC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RTC_CRITICAL_SECTIONS)
+#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RTC_CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_rtcmode0_ctrla_reg_t;
+typedef uint16_t hri_rtcmode0_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode0_intenset_reg_t;
+typedef uint16_t hri_rtcmode0_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_comp_reg_t;
+typedef uint16_t hri_rtcmode1_count_reg_t;
+typedef uint16_t hri_rtcmode1_ctrla_reg_t;
+typedef uint16_t hri_rtcmode1_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode1_intenset_reg_t;
+typedef uint16_t hri_rtcmode1_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_per_reg_t;
+typedef uint16_t hri_rtcmode2_ctrla_reg_t;
+typedef uint16_t hri_rtcmode2_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode2_intenset_reg_t;
+typedef uint16_t hri_rtcmode2_intflag_reg_t;
+typedef uint32_t hri_rtc_bkup_reg_t;
+typedef uint32_t hri_rtc_gp_reg_t;
+typedef uint32_t hri_rtc_tampctrl_reg_t;
+typedef uint32_t hri_rtc_tampid_reg_t;
+typedef uint32_t hri_rtcalarm_alarm_reg_t;
+typedef uint32_t hri_rtcmode0_comp_reg_t;
+typedef uint32_t hri_rtcmode0_count_reg_t;
+typedef uint32_t hri_rtcmode0_evctrl_reg_t;
+typedef uint32_t hri_rtcmode0_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode0_timestamp_reg_t;
+typedef uint32_t hri_rtcmode1_evctrl_reg_t;
+typedef uint32_t hri_rtcmode1_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode1_timestamp_reg_t;
+typedef uint32_t hri_rtcmode2_alarm_reg_t;
+typedef uint32_t hri_rtcmode2_clock_reg_t;
+typedef uint32_t hri_rtcmode2_evctrl_reg_t;
+typedef uint32_t hri_rtcmode2_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode2_timestamp_reg_t;
+typedef uint8_t  hri_rtc_dbgctrl_reg_t;
+typedef uint8_t  hri_rtc_freqcorr_reg_t;
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode0_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode1_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode2_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode0_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+}
+
+static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = data;
+	((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode1_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTENSET.reg;
+}
+
+static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = data;
+	((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode2_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTENSET.reg;
+}
+
+static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = data;
+	((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode0_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode1_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode2_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode0_timestamp_reg_t mask)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode0_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode1_timestamp_reg_t mask)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode1_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const            hw,
+                                                                             hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const            hw,
+                                                                               hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode2_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE0_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE0_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE0.CTRLA.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE1_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE1_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE1.CTRLA.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLKREP;
+	tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE2_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE2_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	return ((Rtc *)hw)->MODE2.CTRLA.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE0_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE0_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.CTRLB.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE1_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE1_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.CTRLB.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE2_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE2_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CTRLB.reg;
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode0_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO2;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO3;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode1_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode2_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.EVCTRL.reg;
+}
+
+static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+}
+
+static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	return ((Rtc *)hw)->MODE0.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE0_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE0.COUNT.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+}
+
+static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE1_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE1.COUNT.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.COUNT.reg;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
+	tmp |= RTC_MODE2_CLOCK_SECOND(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
+	tmp |= RTC_MODE2_CLOCK_MINUTE(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
+	tmp |= RTC_MODE2_CLOCK_HOUR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const        hw,
+                                                                     hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
+	tmp |= RTC_MODE2_CLOCK_DAY(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const        hw,
+                                                                       hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
+	tmp |= RTC_MODE2_CLOCK_MONTH(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
+	tmp |= RTC_MODE2_CLOCK_YEAR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.CLOCK.reg;
+}
+
+static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= ~RTC_MODE1_PER_PER_Msk;
+	tmp |= RTC_MODE1_PER_PER(data);
+	((Rtc *)hw)->MODE1.PER.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	return ((Rtc *)hw)->MODE1.PER.reg;
+}
+
+static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= ~RTC_MODE0_COMP_COMP_Msk;
+	tmp |= RTC_MODE0_COMP_COMP(data);
+	((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	return ((Rtc *)hw)->MODE0.COMP[index].reg;
+}
+
+static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= ~RTC_MODE1_COMP_COMP_Msk;
+	tmp |= RTC_MODE1_COMP_COMP(data);
+	((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg = data;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	return ((Rtc *)hw)->MODE1.COMP[index].reg;
+}
+
+static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= ~RTC_GP_GP_Msk;
+	tmp |= RTC_GP_GP(data);
+	((Rtc *)hw)->MODE0.GP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	return ((Rtc *)hw)->MODE0.GP[index].reg;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL0;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL1;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL2;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL3;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL4;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC0;
+	tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC1;
+	tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC2;
+	tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC3;
+	tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC4;
+	tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN0ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN1ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN2ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN3ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN4ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID0;
+	tmp |= value << RTC_TAMPID_TAMPID0_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID1;
+	tmp |= value << RTC_TAMPID_TAMPID1_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID2;
+	tmp |= value << RTC_TAMPID_TAMPID2_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID3;
+	tmp |= value << RTC_TAMPID_TAMPID3_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID4;
+	tmp |= value << RTC_TAMPID_TAMPID4_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPEVT;
+	tmp |= value << RTC_TAMPID_TAMPEVT_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPID.reg;
+}
+
+static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= ~RTC_BKUP_BKUP_Msk;
+	tmp |= RTC_BKUP_BKUP(data);
+	((Rtc *)hw)->MODE0.BKUP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE0.BKUP[index].reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RTC_E53_H_INCLUDED */
+#endif /* _SAME53_RTC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_sdhc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_sdhc_e53.h
new file mode 100644
index 000000000..1bc5b4cf7
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_sdhc_e53.h
@@ -0,0 +1,7477 @@
+/**
+ * \file
+ *
+ * \brief SAM SDHC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_SDHC_COMPONENT_
+#ifndef _HRI_SDHC_E53_H_INCLUDED_
+#define _HRI_SDHC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SDHC_CRITICAL_SECTIONS)
+#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SDHC_CRITICAL_SECTION_ENTER()
+#define SDHC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sdhc_acesr_reg_t;
+typedef uint16_t hri_sdhc_bcr_reg_t;
+typedef uint16_t hri_sdhc_bsr_reg_t;
+typedef uint16_t hri_sdhc_ccr_reg_t;
+typedef uint16_t hri_sdhc_cr_reg_t;
+typedef uint16_t hri_sdhc_eisier_reg_t;
+typedef uint16_t hri_sdhc_eister_reg_t;
+typedef uint16_t hri_sdhc_eistr_reg_t;
+typedef uint16_t hri_sdhc_feraces_reg_t;
+typedef uint16_t hri_sdhc_fereis_reg_t;
+typedef uint16_t hri_sdhc_hc2r_reg_t;
+typedef uint16_t hri_sdhc_hcvr_reg_t;
+typedef uint16_t hri_sdhc_nisier_reg_t;
+typedef uint16_t hri_sdhc_nister_reg_t;
+typedef uint16_t hri_sdhc_nistr_reg_t;
+typedef uint16_t hri_sdhc_pvr_reg_t;
+typedef uint16_t hri_sdhc_sisr_reg_t;
+typedef uint16_t hri_sdhc_tmr_reg_t;
+typedef uint32_t hri_sdhc_acr_reg_t;
+typedef uint32_t hri_sdhc_arg1r_reg_t;
+typedef uint32_t hri_sdhc_asar_reg_t;
+typedef uint32_t hri_sdhc_bdpr_reg_t;
+typedef uint32_t hri_sdhc_ca0r_reg_t;
+typedef uint32_t hri_sdhc_ca1r_reg_t;
+typedef uint32_t hri_sdhc_cacr_reg_t;
+typedef uint32_t hri_sdhc_cc2r_reg_t;
+typedef uint32_t hri_sdhc_mccar_reg_t;
+typedef uint32_t hri_sdhc_psr_reg_t;
+typedef uint32_t hri_sdhc_rr_reg_t;
+typedef uint32_t hri_sdhc_ssar_reg_t;
+typedef uint8_t  hri_sdhc_aesr_reg_t;
+typedef uint8_t  hri_sdhc_bgcr_reg_t;
+typedef uint8_t  hri_sdhc_dbgr_reg_t;
+typedef uint8_t  hri_sdhc_hc1r_reg_t;
+typedef uint8_t  hri_sdhc_mc1r_reg_t;
+typedef uint8_t  hri_sdhc_mc2r_reg_t;
+typedef uint8_t  hri_sdhc_pcr_reg_t;
+typedef uint8_t  hri_sdhc_srr_reg_t;
+typedef uint8_t  hri_sdhc_tcr_reg_t;
+typedef uint8_t  hri_sdhc_wcr_reg_t;
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask)
+{
+	return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index)
+{
+	return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->RR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->RR[index].reg;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->PSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->PSR.reg;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos;
+}
+
+static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->ACESR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ACESR.reg;
+}
+
+static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CA0R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CA0R.reg;
+}
+
+static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CA1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CA1R.reg;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->MCCAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->MCCAR.reg;
+}
+
+static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->AESR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->AESR.reg;
+}
+
+static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos;
+}
+
+static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->SISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SISR.reg;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HCVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HCVR.reg;
+}
+
+static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= ~SDHC_SSAR_ADDR_Msk;
+	tmp |= SDHC_SSAR_ADDR(data);
+	((Sdhc *)hw)->SSAR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk;
+	tmp |= SDHC_SSAR_CMD23_ARG2(data);
+	((Sdhc *)hw)->SSAR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SSAR.reg;
+}
+
+static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= ~SDHC_BSR_BLOCKSIZE_Msk;
+	tmp |= SDHC_BSR_BLOCKSIZE(data);
+	((Sdhc *)hw)->BSR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= ~SDHC_BSR_BOUNDARY_Msk;
+	tmp |= SDHC_BSR_BOUNDARY(data);
+	((Sdhc *)hw)->BSR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BSR.reg;
+}
+
+static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp &= ~SDHC_BCR_BCNT_Msk;
+	tmp |= SDHC_BCR_BCNT(data);
+	((Sdhc *)hw)->BCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BCR.reg;
+}
+
+static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp &= ~SDHC_ARG1R_ARG_Msk;
+	tmp |= SDHC_ARG1R_ARG(data);
+	((Sdhc *)hw)->ARG1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ARG1R.reg;
+}
+
+static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_DMAEN;
+	tmp |= value << SDHC_TMR_DMAEN_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_BCEN;
+	tmp |= value << SDHC_TMR_BCEN_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_DTDSEL;
+	tmp |= value << SDHC_TMR_DTDSEL_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_MSBSEL;
+	tmp |= value << SDHC_TMR_MSBSEL_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_ACMDEN_Msk;
+	tmp |= SDHC_TMR_ACMDEN(data);
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->TMR.reg;
+}
+
+static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDCCEN;
+	tmp |= value << SDHC_CR_CMDCCEN_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDICEN;
+	tmp |= value << SDHC_CR_CMDICEN_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_DPSEL;
+	tmp |= value << SDHC_CR_DPSEL_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_RESPTYP_Msk;
+	tmp |= SDHC_CR_RESPTYP(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDTYP_Msk;
+	tmp |= SDHC_CR_CMDTYP(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDIDX_Msk;
+	tmp |= SDHC_CR_CMDIDX(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CR.reg;
+}
+
+static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp &= ~SDHC_BDPR_BUFDATA_Msk;
+	tmp |= SDHC_BDPR_BUFDATA(data);
+	((Sdhc *)hw)->BDPR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BDPR.reg;
+}
+
+static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_LEDCTRL;
+	tmp |= value << SDHC_HC1R_LEDCTRL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_DW;
+	tmp |= value << SDHC_HC1R_DW_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_HSEN;
+	tmp |= value << SDHC_HC1R_HSEN_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_CARDDTL;
+	tmp |= value << SDHC_HC1R_CARDDTL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_CARDDSEL;
+	tmp |= value << SDHC_HC1R_CARDDSEL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_DMASEL_Msk;
+	tmp |= SDHC_HC1R_DMASEL(data);
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HC1R.reg;
+}
+
+static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= ~SDHC_PCR_SDBPWR;
+	tmp |= value << SDHC_PCR_SDBPWR_Pos;
+	((Sdhc *)hw)->PCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= ~SDHC_PCR_SDBVSEL_Msk;
+	tmp |= SDHC_PCR_SDBVSEL(data);
+	((Sdhc *)hw)->PCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->PCR.reg;
+}
+
+static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_STPBGR;
+	tmp |= value << SDHC_BGCR_STPBGR_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_CONTR;
+	tmp |= value << SDHC_BGCR_CONTR_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_RWCTRL;
+	tmp |= value << SDHC_BGCR_RWCTRL_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_INTBG;
+	tmp |= value << SDHC_BGCR_INTBG_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BGCR.reg;
+}
+
+static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCINT;
+	tmp |= value << SDHC_WCR_WKENCINT_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCINS;
+	tmp |= value << SDHC_WCR_WKENCINS_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCREM;
+	tmp |= value << SDHC_WCR_WKENCREM_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->WCR.reg;
+}
+
+static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_INTCLKEN;
+	tmp |= value << SDHC_CCR_INTCLKEN_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_INTCLKS;
+	tmp |= value << SDHC_CCR_INTCLKS_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_SDCLKEN;
+	tmp |= value << SDHC_CCR_SDCLKEN_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_CLKGSEL;
+	tmp |= value << SDHC_CCR_CLKGSEL_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_USDCLKFSEL_Msk;
+	tmp |= SDHC_CCR_USDCLKFSEL(data);
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_SDCLKFSEL_Msk;
+	tmp |= SDHC_CCR_SDCLKFSEL(data);
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CCR.reg;
+}
+
+static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp &= ~SDHC_TCR_DTCVAL_Msk;
+	tmp |= SDHC_TCR_DTCVAL(data);
+	((Sdhc *)hw)->TCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->TCR.reg;
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTALL;
+	tmp |= value << SDHC_SRR_SWRSTALL_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTCMD;
+	tmp |= value << SDHC_SRR_SWRSTCMD_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTDAT;
+	tmp |= value << SDHC_SRR_SWRSTDAT_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SRR.reg;
+}
+
+static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CMDC;
+	tmp |= value << SDHC_NISTR_CMDC_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_TRFC;
+	tmp |= value << SDHC_NISTR_TRFC_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BLKGE;
+	tmp |= value << SDHC_NISTR_BLKGE_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_DMAINT;
+	tmp |= value << SDHC_NISTR_DMAINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BWRRDY;
+	tmp |= value << SDHC_NISTR_BWRRDY_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BRDRDY;
+	tmp |= value << SDHC_NISTR_BRDRDY_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CINS;
+	tmp |= value << SDHC_NISTR_CINS_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CREM;
+	tmp |= value << SDHC_NISTR_CREM_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CINT;
+	tmp |= value << SDHC_NISTR_CINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_ERRINT;
+	tmp |= value << SDHC_NISTR_ERRINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISTR.reg;
+}
+
+static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDTEO;
+	tmp |= value << SDHC_EISTR_CMDTEO_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDCRC;
+	tmp |= value << SDHC_EISTR_CMDCRC_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDEND;
+	tmp |= value << SDHC_EISTR_CMDEND_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDIDX;
+	tmp |= value << SDHC_EISTR_CMDIDX_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATTEO;
+	tmp |= value << SDHC_EISTR_DATTEO_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATCRC;
+	tmp |= value << SDHC_EISTR_DATCRC_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATEND;
+	tmp |= value << SDHC_EISTR_DATEND_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CURLIM;
+	tmp |= value << SDHC_EISTR_CURLIM_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_ACMD;
+	tmp |= value << SDHC_EISTR_ACMD_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_ADMA;
+	tmp |= value << SDHC_EISTR_ADMA_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISTR.reg;
+}
+
+static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CMDC;
+	tmp |= value << SDHC_NISTER_CMDC_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_TRFC;
+	tmp |= value << SDHC_NISTER_TRFC_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BLKGE;
+	tmp |= value << SDHC_NISTER_BLKGE_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_DMAINT;
+	tmp |= value << SDHC_NISTER_DMAINT_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BWRRDY;
+	tmp |= value << SDHC_NISTER_BWRRDY_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BRDRDY;
+	tmp |= value << SDHC_NISTER_BRDRDY_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CINS;
+	tmp |= value << SDHC_NISTER_CINS_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CREM;
+	tmp |= value << SDHC_NISTER_CREM_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CINT;
+	tmp |= value << SDHC_NISTER_CINT_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISTER.reg;
+}
+
+static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDTEO;
+	tmp |= value << SDHC_EISTER_CMDTEO_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDCRC;
+	tmp |= value << SDHC_EISTER_CMDCRC_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDEND;
+	tmp |= value << SDHC_EISTER_CMDEND_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDIDX;
+	tmp |= value << SDHC_EISTER_CMDIDX_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATTEO;
+	tmp |= value << SDHC_EISTER_DATTEO_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATCRC;
+	tmp |= value << SDHC_EISTER_DATCRC_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATEND;
+	tmp |= value << SDHC_EISTER_DATEND_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CURLIM;
+	tmp |= value << SDHC_EISTER_CURLIM_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_ACMD;
+	tmp |= value << SDHC_EISTER_ACMD_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_ADMA;
+	tmp |= value << SDHC_EISTER_ADMA_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISTER.reg;
+}
+
+static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CMDC;
+	tmp |= value << SDHC_NISIER_CMDC_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_TRFC;
+	tmp |= value << SDHC_NISIER_TRFC_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BLKGE;
+	tmp |= value << SDHC_NISIER_BLKGE_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_DMAINT;
+	tmp |= value << SDHC_NISIER_DMAINT_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BWRRDY;
+	tmp |= value << SDHC_NISIER_BWRRDY_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BRDRDY;
+	tmp |= value << SDHC_NISIER_BRDRDY_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CINS;
+	tmp |= value << SDHC_NISIER_CINS_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CREM;
+	tmp |= value << SDHC_NISIER_CREM_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CINT;
+	tmp |= value << SDHC_NISIER_CINT_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISIER.reg;
+}
+
+static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDTEO;
+	tmp |= value << SDHC_EISIER_CMDTEO_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDCRC;
+	tmp |= value << SDHC_EISIER_CMDCRC_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDEND;
+	tmp |= value << SDHC_EISIER_CMDEND_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDIDX;
+	tmp |= value << SDHC_EISIER_CMDIDX_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATTEO;
+	tmp |= value << SDHC_EISIER_DATTEO_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATCRC;
+	tmp |= value << SDHC_EISIER_DATCRC_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATEND;
+	tmp |= value << SDHC_EISIER_DATEND_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CURLIM;
+	tmp |= value << SDHC_EISIER_CURLIM_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_ACMD;
+	tmp |= value << SDHC_EISIER_ACMD_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_ADMA;
+	tmp |= value << SDHC_EISIER_ADMA_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISIER.reg;
+}
+
+static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_VS18EN;
+	tmp |= value << SDHC_HC2R_VS18EN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_EXTUN;
+	tmp |= value << SDHC_HC2R_EXTUN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_SLCKSEL;
+	tmp |= value << SDHC_HC2R_SLCKSEL_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_ASINTEN;
+	tmp |= value << SDHC_HC2R_ASINTEN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_PVALEN;
+	tmp |= value << SDHC_HC2R_PVALEN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_UHSMS_Msk;
+	tmp |= SDHC_HC2R_UHSMS(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk;
+	tmp |= SDHC_HC2R_EMMC_HS200EN(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_DRVSEL_Msk;
+	tmp |= SDHC_HC2R_DRVSEL(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HC2R.reg;
+}
+
+static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index,
+                                                              hri_sdhc_asar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp &= ~SDHC_ASAR_ADMASA_Msk;
+	tmp |= SDHC_ASAR_ADMASA(data);
+	((Sdhc *)hw)->ASAR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->ASAR[index].reg;
+}
+
+static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_CLKGSEL;
+	tmp |= value << SDHC_PVR_CLKGSEL_Pos;
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index,
+                                                               hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_SDCLKFSEL_Msk;
+	tmp |= SDHC_PVR_SDCLKFSEL(data);
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index,
+                                                            hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_DRVSEL_Msk;
+	tmp |= SDHC_PVR_DRVSEL(data);
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->PVR[index].reg;
+}
+
+static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_DDR;
+	tmp |= value << SDHC_MC1R_DDR_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_OPD;
+	tmp |= value << SDHC_MC1R_OPD_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_BOOTA;
+	tmp |= value << SDHC_MC1R_BOOTA_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_RSTN;
+	tmp |= value << SDHC_MC1R_RSTN_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_FCD;
+	tmp |= value << SDHC_MC1R_FCD_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_CMDTYP_Msk;
+	tmp |= SDHC_MC1R_CMDTYP(data);
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->MC1R.reg;
+}
+
+static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp &= ~SDHC_ACR_BMAX_Msk;
+	tmp |= SDHC_ACR_BMAX(data);
+	((Sdhc *)hw)->ACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ACR.reg;
+}
+
+static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp &= ~SDHC_CC2R_FSDCLKD;
+	tmp |= value << SDHC_CC2R_FSDCLKD_Pos;
+	((Sdhc *)hw)->CC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CC2R.reg;
+}
+
+static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= ~SDHC_CACR_CAPWREN;
+	tmp |= value << SDHC_CACR_CAPWREN_Pos;
+	((Sdhc *)hw)->CACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= ~SDHC_CACR_KEY_Msk;
+	tmp |= SDHC_CACR_KEY(data);
+	((Sdhc *)hw)->CACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CACR.reg;
+}
+
+static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp &= ~SDHC_DBGR_NIDBG;
+	tmp |= value << SDHC_DBGR_NIDBG_Pos;
+	((Sdhc *)hw)->DBGR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->DBGR.reg;
+}
+
+static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->FERACES.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->FEREIS.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b)
+#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b)
+#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b)
+#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b)
+#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b)
+#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a)
+#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a)
+#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a)
+#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a)
+#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a)
+#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a)
+#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a)
+#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a)
+#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a)
+#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a)
+#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b)
+#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b)
+#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b)
+#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b)
+#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a)
+#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a)
+#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a)
+#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a)
+#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a)
+#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a)
+#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a)
+#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a)
+#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a)
+#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b)
+#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b)
+#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b)
+#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b)
+#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a)
+#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b)
+#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b)
+#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b)
+#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b)
+#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b)
+#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b)
+#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b)
+#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b)
+#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a)
+#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b)
+#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b)
+#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b)
+#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b)
+#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b)
+#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b)
+#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b)
+#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b)
+#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a)
+#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b)
+#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b)
+#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b)
+#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b)
+#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b)
+#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b)
+#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b)
+#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b)
+#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a)
+#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a)
+#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b)
+#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b)
+#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b)
+#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b)
+#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SDHC_E53_H_INCLUDED */
+#endif /* _SAME53_SDHC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_sercom_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_sercom_e53.h
new file mode 100644
index 000000000..f71304d9f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_sercom_e53.h
@@ -0,0 +1,8892 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_SERCOM_COMPONENT_
+#ifndef _HRI_SERCOM_E53_H_INCLUDED_
+#define _HRI_SERCOM_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
+#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SERCOM_CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sercomi2cm_status_reg_t;
+typedef uint16_t hri_sercomi2cs_length_reg_t;
+typedef uint16_t hri_sercomi2cs_status_reg_t;
+typedef uint16_t hri_sercomspi_length_reg_t;
+typedef uint16_t hri_sercomspi_status_reg_t;
+typedef uint16_t hri_sercomusart_baud_reg_t;
+typedef uint16_t hri_sercomusart_length_reg_t;
+typedef uint16_t hri_sercomusart_status_reg_t;
+typedef uint32_t hri_sercomi2cm_addr_reg_t;
+typedef uint32_t hri_sercomi2cm_baud_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlc_reg_t;
+typedef uint32_t hri_sercomi2cm_data_reg_t;
+typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
+typedef uint32_t hri_sercomi2cs_addr_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlc_reg_t;
+typedef uint32_t hri_sercomi2cs_data_reg_t;
+typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
+typedef uint32_t hri_sercomspi_addr_reg_t;
+typedef uint32_t hri_sercomspi_ctrla_reg_t;
+typedef uint32_t hri_sercomspi_ctrlb_reg_t;
+typedef uint32_t hri_sercomspi_ctrlc_reg_t;
+typedef uint32_t hri_sercomspi_data_reg_t;
+typedef uint32_t hri_sercomspi_syncbusy_reg_t;
+typedef uint32_t hri_sercomusart_ctrla_reg_t;
+typedef uint32_t hri_sercomusart_ctrlb_reg_t;
+typedef uint32_t hri_sercomusart_ctrlc_reg_t;
+typedef uint32_t hri_sercomusart_data_reg_t;
+typedef uint32_t hri_sercomusart_syncbusy_reg_t;
+typedef uint8_t  hri_sercomi2cm_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomi2cm_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cm_intflag_reg_t;
+typedef uint8_t  hri_sercomi2cs_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cs_intflag_reg_t;
+typedef uint8_t  hri_sercomspi_baud_reg_t;
+typedef uint8_t  hri_sercomspi_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomspi_intenset_reg_t;
+typedef uint8_t  hri_sercomspi_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomusart_intenset_reg_t;
+typedef uint8_t  hri_sercomusart_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_rxerrcnt_reg_t;
+typedef uint8_t  hri_sercomusart_rxpl_reg_t;
+
+static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cs_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_sercomspi_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const             hw,
+                                                                            hri_sercomusart_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTFLAG.reg;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = data;
+	((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cs_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = data;
+	((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = mask;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const            hw,
+                                                                       hri_sercomspi_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTENSET.reg;
+}
+
+static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = data;
+	((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = mask;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const              hw,
+                                                                           hri_sercomusart_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTENSET.reg;
+}
+
+static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = data;
+	((Sercom *)hw)->USART.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cs_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_sercomspi_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const              hw,
+                                                                              hri_sercomusart_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const              hw,
+                                                                              hri_sercomusart_rxerrcnt_reg_t mask)
+{
+	uint8_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.RXERRCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.RXERRCNT.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const          hw,
+                                                                              hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CM.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CS.CTRLA.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
+	tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_IBON;
+	tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPHA;
+	tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPOL;
+	tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DORD;
+	tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
+	tmp |= SERCOM_SPI_CTRLA_MODE(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DOPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DIPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
+	tmp |= SERCOM_SPI_CTRLA_FORM(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->SPI.CTRLA.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_ENABLE;
+	tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_IBON;
+	tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXINV;
+	tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXINV;
+	tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CMODE;
+	tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CPOL;
+	tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_DORD;
+	tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
+	tmp |= SERCOM_USART_CTRLA_MODE(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPR(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_TXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_RXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPA(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
+	tmp |= SERCOM_USART_CTRLA_FORM(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->USART.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CM_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
+	tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLB.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_SSDE;
+	tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
+	tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_RXEN;
+	tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const         hw,
+                                                                          hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const         hw,
+                                                                         hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_AMODE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SBMODE;
+	tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_COLDEN;
+	tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SFDE;
+	tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_ENC;
+	tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_PMODE;
+	tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_TXEN;
+	tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_RXEN;
+	tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk;
+	tmp |= SERCOM_USART_CTRLB_LINCMD(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp &= ~SERCOM_I2CM_CTRLC_DATA32B;
+	tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->I2CM.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= ~SERCOM_I2CS_CTRLC_DATA32B;
+	tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->I2CS.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const          hw,
+                                                                              hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk;
+	tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data);
+	((Sercom *)hw)->I2CS.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLC.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= ~SERCOM_SPI_CTRLC_DATA32B;
+	tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->SPI.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const         hw,
+                                                                           hri_sercomspi_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk;
+	tmp |= SERCOM_SPI_CTRLC_ICSPACE(data);
+	((Sercom *)hw)->SPI.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.CTRLC.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_INACK;
+	tmp |= value << SERCOM_USART_CTRLC_INACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DSNACK;
+	tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk;
+	tmp |= SERCOM_USART_CTRLC_GTIME(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk;
+	tmp |= SERCOM_USART_CTRLC_BRKLEN(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk;
+	tmp |= SERCOM_USART_CTRLC_HDRDLY(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk;
+	tmp |= SERCOM_USART_CTRLC_MAXITER(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk;
+	tmp |= SERCOM_USART_CTRLC_DATA32B(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const         hw,
+                                                                           hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const         hw,
+                                                                          hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const         hw,
+                                                                             hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.BAUD.reg;
+}
+
+static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const        hw,
+                                                                      hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
+	tmp |= SERCOM_SPI_BAUD_BAUD(data);
+	((Sercom *)hw)->SPI.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const          hw,
+                                                                                 hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const          hw,
+                                                                          hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const          hw,
+                                                                                  hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const          hw,
+                                                                      hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const          hw,
+                                                                          hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
+	tmp |= SERCOM_USART_RXPL_RXPL(data);
+	((Sercom *)hw)->USART.RXPL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const          hw,
+                                                                      hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXPL.reg;
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= ~SERCOM_I2CS_LENGTH_LENEN;
+	tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos;
+	((Sercom *)hw)->I2CS.LENGTH.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const           hw,
+                                                                           hri_sercomi2cs_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk;
+	tmp |= SERCOM_I2CS_LENGTH_LEN(data);
+	((Sercom *)hw)->I2CS.LENGTH.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->I2CS.LENGTH.reg;
+}
+
+static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= ~SERCOM_SPI_LENGTH_LENEN;
+	tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos;
+	((Sercom *)hw)->SPI.LENGTH.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const          hw,
+                                                                         hri_sercomspi_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk;
+	tmp |= SERCOM_SPI_LENGTH_LEN(data);
+	((Sercom *)hw)->SPI.LENGTH.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const          hw,
+                                                                      hri_sercomspi_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.LENGTH.reg;
+}
+
+static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const            hw,
+                                                                             hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= ~SERCOM_USART_LENGTH_LEN_Msk;
+	tmp |= SERCOM_USART_LENGTH_LEN(data);
+	((Sercom *)hw)->USART.LENGTH.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const            hw,
+                                                                               hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk;
+	tmp |= SERCOM_USART_LENGTH_LENEN(data);
+	((Sercom *)hw)->USART.LENGTH.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const            hw,
+                                                                          hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.LENGTH.reg;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LENEN;
+	tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CM_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const         hw,
+                                                                       hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
+	tmp |= SERCOM_I2CM_ADDR_LEN(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
+	tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const         hw,
+                                                                            hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.ADDR.reg;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDR(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const        hw,
+                                                                          hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.ADDR.reg;
+}
+
+static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= ~SERCOM_I2CM_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CM_DATA_DATA(data);
+	((Sercom *)hw)->I2CM.DATA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_data_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+}
+
+static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= ~SERCOM_I2CS_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CS_DATA_DATA(data);
+	((Sercom *)hw)->I2CS.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.DATA.reg;
+}
+
+static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const        hw,
+                                                                      hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= ~SERCOM_SPI_DATA_DATA_Msk;
+	tmp |= SERCOM_SPI_DATA_DATA(data);
+	((Sercom *)hw)->SPI.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DATA.reg;
+}
+
+static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const          hw,
+                                                                          hri_sercomusart_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= ~SERCOM_USART_DATA_DATA_Msk;
+	tmp |= SERCOM_USART_DATA_DATA(data);
+	((Sercom *)hw)->USART.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const          hw,
+                                                                      hri_sercomusart_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DATA.reg;
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const           hw,
+                                                                        hri_sercomspi_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DBGCTRL.reg;
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const             hw,
+                                                                            hri_sercomusart_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.STATUS.reg;
+}
+
+static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const          hw,
+                                                                      hri_sercomspi_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.STATUS.reg;
+}
+
+static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const            hw,
+                                                                          hri_sercomusart_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
+	tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
+	tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
+	tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
+	tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LENERR;
+	tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const           hw,
+                                                                                hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
+	tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cm_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg |= mask;
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg = data;
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a)
+#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a)
+#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SERCOM_E53_H_INCLUDED */
+#endif /* _SAME53_SERCOM_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_supc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_supc_e53.h
new file mode 100644
index 000000000..4dcaeecf0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_supc_e53.h
@@ -0,0 +1,1769 @@
+/**
+ * \file
+ *
+ * \brief SAM SUPC
+ *
+ * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_SUPC_COMPONENT_
+#ifndef _HRI_SUPC_E53_H_INCLUDED_
+#define _HRI_SUPC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SUPC_CRITICAL_SECTIONS)
+#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SUPC_CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_supc_bbps_reg_t;
+typedef uint32_t hri_supc_bkin_reg_t;
+typedef uint32_t hri_supc_bkout_reg_t;
+typedef uint32_t hri_supc_bod33_reg_t;
+typedef uint32_t hri_supc_intenset_reg_t;
+typedef uint32_t hri_supc_intflag_reg_t;
+typedef uint32_t hri_supc_status_reg_t;
+typedef uint32_t hri_supc_vref_reg_t;
+typedef uint32_t hri_supc_vreg_reg_t;
+
+static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	((Supc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data)
+{
+	((Supc *)hw)->INTENSET.reg = data;
+	((Supc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos;
+}
+
+static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->STATUS.reg;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKIN.reg;
+}
+
+static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ENABLE;
+	tmp |= value << SUPC_BOD33_ENABLE_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_STDBYCFG;
+	tmp |= value << SUPC_BOD33_STDBYCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNSTDBY;
+	tmp |= value << SUPC_BOD33_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNHIB;
+	tmp |= value << SUPC_BOD33_RUNHIB_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNBKUP;
+	tmp |= value << SUPC_BOD33_RUNBKUP_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTION_Msk;
+	tmp |= SUPC_BOD33_ACTION(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_HYST_Msk;
+	tmp |= SUPC_BOD33_HYST(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_PSEL_Msk;
+	tmp |= SUPC_BOD33_PSEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_LEVEL_Msk;
+	tmp |= SUPC_BOD33_LEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_VBATLEVEL_Msk;
+	tmp |= SUPC_BOD33_VBATLEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD33.reg;
+}
+
+static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_ENABLE;
+	tmp |= value << SUPC_VREG_ENABLE_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_SEL;
+	tmp |= value << SUPC_VREG_SEL_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_RUNBKUP;
+	tmp |= value << SUPC_VREG_RUNBKUP_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSEN;
+	tmp |= value << SUPC_VREG_VSEN_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSPER_Msk;
+	tmp |= SUPC_VREG_VSPER(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREG.reg;
+}
+
+static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSEN;
+	tmp |= value << SUPC_VREF_TSEN_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_VREFOE;
+	tmp |= value << SUPC_VREF_VREFOE_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSSEL;
+	tmp |= value << SUPC_VREF_TSSEL_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_RUNSTDBY;
+	tmp |= value << SUPC_VREF_RUNSTDBY_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_ONDEMAND;
+	tmp |= value << SUPC_VREF_ONDEMAND_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_SEL_Msk;
+	tmp |= SUPC_VREF_SEL(data);
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREF.reg;
+}
+
+static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_CONF;
+	tmp |= value << SUPC_BBPS_CONF_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_WAKEEN;
+	tmp |= value << SUPC_BBPS_WAKEEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BBPS.reg;
+}
+
+static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_EN_Msk;
+	tmp |= SUPC_BKOUT_EN(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_CLR_Msk;
+	tmp |= SUPC_BKOUT_CLR(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_SET_Msk;
+	tmp |= SUPC_BKOUT_SET(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_RTCTGL_Msk;
+	tmp |= SUPC_BKOUT_RTCTGL(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKOUT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SUPC_E53_H_INCLUDED */
+#endif /* _SAME53_SUPC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_tc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_tc_e53.h
new file mode 100644
index 000000000..cddb696ec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_tc_e53.h
@@ -0,0 +1,3003 @@
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_TC_COMPONENT_
+#ifndef _HRI_TC_E53_H_INCLUDED_
+#define _HRI_TC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TC_CRITICAL_SECTIONS)
+#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TC_CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tc_evctrl_reg_t;
+typedef uint16_t hri_tccount16_cc_reg_t;
+typedef uint16_t hri_tccount16_ccbuf_reg_t;
+typedef uint16_t hri_tccount16_count_reg_t;
+typedef uint32_t hri_tc_ctrla_reg_t;
+typedef uint32_t hri_tc_syncbusy_reg_t;
+typedef uint32_t hri_tccount32_cc_reg_t;
+typedef uint32_t hri_tccount32_ccbuf_reg_t;
+typedef uint32_t hri_tccount32_count_reg_t;
+typedef uint8_t  hri_tc_ctrlbset_reg_t;
+typedef uint8_t  hri_tc_dbgctrl_reg_t;
+typedef uint8_t  hri_tc_drvctrl_reg_t;
+typedef uint8_t  hri_tc_intenset_reg_t;
+typedef uint8_t  hri_tc_intflag_reg_t;
+typedef uint8_t  hri_tc_status_reg_t;
+typedef uint8_t  hri_tc_wave_reg_t;
+typedef uint8_t  hri_tccount8_cc_reg_t;
+typedef uint8_t  hri_tccount8_ccbuf_reg_t;
+typedef uint8_t  hri_tccount8_count_reg_t;
+typedef uint8_t  hri_tccount8_per_reg_t;
+typedef uint8_t  hri_tccount8_perbuf_reg_t;
+
+static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTFLAG.reg;
+}
+
+static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = mask;
+}
+
+static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+}
+
+static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = mask;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+}
+
+static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+}
+
+static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+}
+
+static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+}
+
+static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+}
+
+static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+}
+
+static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+}
+
+static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+}
+
+static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+}
+
+static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = mask;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTENSET.reg;
+}
+
+static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = data;
+	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = mask;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+}
+
+static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ENABLE;
+	tmp |= value << TC_CTRLA_ENABLE_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_RUNSTDBY;
+	tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ONDEMAND;
+	tmp |= value << TC_CTRLA_ONDEMAND_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ALOCK;
+	tmp |= value << TC_CTRLA_ALOCK_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN0;
+	tmp |= value << TC_CTRLA_CAPTEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN1;
+	tmp |= value << TC_CTRLA_CAPTEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN0;
+	tmp |= value << TC_CTRLA_COPEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN1;
+	tmp |= value << TC_CTRLA_COPEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_MODE_Msk;
+	tmp |= TC_CTRLA_MODE(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TC_CTRLA_PRESCSYNC(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCALER_Msk;
+	tmp |= TC_CTRLA_PRESCALER(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTMODE0_Msk;
+	tmp |= TC_CTRLA_CAPTMODE0(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTMODE1_Msk;
+	tmp |= TC_CTRLA_CAPTMODE1(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	return ((Tc *)hw)->COUNT16.CTRLA.reg;
+}
+
+static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCINV;
+	tmp |= value << TC_EVCTRL_TCINV_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCEI;
+	tmp |= value << TC_EVCTRL_TCEI_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_OVFEO;
+	tmp |= value << TC_EVCTRL_OVFEO_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO0;
+	tmp |= value << TC_EVCTRL_MCEO0_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO1;
+	tmp |= value << TC_EVCTRL_MCEO1_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_EVACT_Msk;
+	tmp |= TC_EVCTRL_EVACT(data);
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.EVCTRL.reg;
+}
+
+static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= ~TC_WAVE_WAVEGEN_Msk;
+	tmp |= TC_WAVE_WAVEGEN(data);
+	((Tc *)hw)->COUNT16.WAVE.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.WAVE.reg;
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN0;
+	tmp |= value << TC_DRVCTRL_INVEN0_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN1;
+	tmp |= value << TC_DRVCTRL_INVEN1_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+}
+
+static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= ~TC_DBGCTRL_DBGRUN;
+	tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+}
+
+static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT8_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT8.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT8.COUNT.reg;
+}
+
+static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT16_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT16.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT16.COUNT.reg;
+}
+
+static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT32_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT32.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT32.COUNT.reg;
+}
+
+static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= ~TC_COUNT8_PER_PER_Msk;
+	tmp |= TC_COUNT8_PER_PER(data);
+	((Tc *)hw)->COUNT8.PER.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	return ((Tc *)hw)->COUNT8.PER.reg;
+}
+
+static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                              hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= ~TC_COUNT8_CC_CC_Msk;
+	tmp |= TC_COUNT8_CC_CC(data);
+	((Tc *)hw)->COUNT8.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index,
+                                                            hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT8.CC[index].reg;
+}
+
+static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= ~TC_COUNT16_CC_CC_Msk;
+	tmp |= TC_COUNT16_CC_CC(data);
+	((Tc *)hw)->COUNT16.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+}
+
+static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= ~TC_COUNT32_CC_CC_Msk;
+	tmp |= TC_COUNT32_CC_CC(data);
+	((Tc *)hw)->COUNT32.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+}
+
+static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const         hw,
+                                                                          hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk;
+	tmp |= TC_COUNT8_PERBUF_PERBUF(data);
+	((Tc *)hw)->COUNT8.PERBUF.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const         hw,
+                                                                    hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.PERBUF.reg;
+}
+
+static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT8_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                  hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+}
+
+static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT16_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+}
+
+static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT32_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+}
+
+static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b)
+#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b)
+#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b)
+#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b)
+#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b)
+#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a)
+#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b)
+#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b)
+#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b)
+#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b)
+#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b)
+#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a)
+#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a)
+#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b)
+#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b)
+#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b)
+#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b)
+#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b)
+#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TC_E53_H_INCLUDED */
+#endif /* _SAME53_TC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_tcc_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_tcc_e53.h
new file mode 100644
index 000000000..f634aba40
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_tcc_e53.h
@@ -0,0 +1,9992 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_TCC_COMPONENT_
+#ifndef _HRI_TCC_E53_H_INCLUDED_
+#define _HRI_TCC_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TCC_CRITICAL_SECTIONS)
+#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TCC_CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tcc_patt_reg_t;
+typedef uint16_t hri_tcc_pattbuf_reg_t;
+typedef uint32_t hri_tcc_cc_reg_t;
+typedef uint32_t hri_tcc_ccbuf_reg_t;
+typedef uint32_t hri_tcc_count_reg_t;
+typedef uint32_t hri_tcc_ctrla_reg_t;
+typedef uint32_t hri_tcc_drvctrl_reg_t;
+typedef uint32_t hri_tcc_evctrl_reg_t;
+typedef uint32_t hri_tcc_fctrla_reg_t;
+typedef uint32_t hri_tcc_fctrlb_reg_t;
+typedef uint32_t hri_tcc_intenset_reg_t;
+typedef uint32_t hri_tcc_intflag_reg_t;
+typedef uint32_t hri_tcc_per_reg_t;
+typedef uint32_t hri_tcc_perbuf_reg_t;
+typedef uint32_t hri_tcc_status_reg_t;
+typedef uint32_t hri_tcc_syncbusy_reg_t;
+typedef uint32_t hri_tcc_wave_reg_t;
+typedef uint32_t hri_tcc_wexctrl_reg_t;
+typedef uint8_t  hri_tcc_ctrlbset_reg_t;
+typedef uint8_t  hri_tcc_dbgctrl_reg_t;
+
+static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4;
+}
+
+static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	((Tcc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = data;
+	((Tcc *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+}
+
+static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+}
+
+static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+}
+
+static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+}
+
+static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+}
+
+static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+}
+
+static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+}
+
+static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+}
+
+static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+}
+
+static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+}
+
+static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+}
+
+static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+}
+
+static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+}
+
+static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+}
+
+static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+}
+
+static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+}
+
+static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+}
+
+static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+}
+
+static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4;
+}
+
+static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4;
+}
+
+static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5;
+}
+
+static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5;
+}
+
+static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
+{
+	((Tcc *)hw)->INTENSET.reg = data;
+	((Tcc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ENABLE;
+	tmp |= value << TCC_CTRLA_ENABLE_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RUNSTDBY;
+	tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ALOCK;
+	tmp |= value << TCC_CTRLA_ALOCK_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_MSYNC;
+	tmp |= value << TCC_CTRLA_MSYNC_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_DMAOS;
+	tmp |= value << TCC_CTRLA_DMAOS_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN0;
+	tmp |= value << TCC_CTRLA_CPTEN0_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN1;
+	tmp |= value << TCC_CTRLA_CPTEN1_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN2;
+	tmp |= value << TCC_CTRLA_CPTEN2_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN3;
+	tmp |= value << TCC_CTRLA_CPTEN3_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN4;
+	tmp |= value << TCC_CTRLA_CPTEN4_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN5;
+	tmp |= value << TCC_CTRLA_CPTEN5_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
+	tmp |= TCC_CTRLA_RESOLUTION(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCALER_Msk;
+	tmp |= TCC_CTRLA_PRESCALER(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TCC_CTRLA_PRESCSYNC(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	return ((Tcc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_KEEP;
+	tmp |= value << TCC_FCTRLA_KEEP_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_QUAL;
+	tmp |= value << TCC_FCTRLA_QUAL_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_RESTART;
+	tmp |= value << TCC_FCTRLA_RESTART_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKPRESC;
+	tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_SRC_Msk;
+	tmp |= TCC_FCTRLA_SRC(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANK_Msk;
+	tmp |= TCC_FCTRLA_BLANK(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_HALT_Msk;
+	tmp |= TCC_FCTRLA_HALT(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CHSEL_Msk;
+	tmp |= TCC_FCTRLA_CHSEL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
+	tmp |= TCC_FCTRLA_CAPTURE(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLA_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLA_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_KEEP;
+	tmp |= value << TCC_FCTRLB_KEEP_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_QUAL;
+	tmp |= value << TCC_FCTRLB_QUAL_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_RESTART;
+	tmp |= value << TCC_FCTRLB_RESTART_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKPRESC;
+	tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_SRC_Msk;
+	tmp |= TCC_FCTRLB_SRC(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANK_Msk;
+	tmp |= TCC_FCTRLB_BLANK(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_HALT_Msk;
+	tmp |= TCC_FCTRLB_HALT(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CHSEL_Msk;
+	tmp |= TCC_FCTRLB_CHSEL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
+	tmp |= TCC_FCTRLB_CAPTURE(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLB_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLB_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLB.reg;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN0;
+	tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN1;
+	tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN2;
+	tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN3;
+	tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_OTMX_Msk;
+	tmp |= TCC_WEXCTRL_OTMX(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTLS_Msk;
+	tmp |= TCC_WEXCTRL_DTLS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTHS_Msk;
+	tmp |= TCC_WEXCTRL_DTHS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WEXCTRL.reg;
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE0;
+	tmp |= value << TCC_DRVCTRL_NRE0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE1;
+	tmp |= value << TCC_DRVCTRL_NRE1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE2;
+	tmp |= value << TCC_DRVCTRL_NRE2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE3;
+	tmp |= value << TCC_DRVCTRL_NRE3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE4;
+	tmp |= value << TCC_DRVCTRL_NRE4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE5;
+	tmp |= value << TCC_DRVCTRL_NRE5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE6;
+	tmp |= value << TCC_DRVCTRL_NRE6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE7;
+	tmp |= value << TCC_DRVCTRL_NRE7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV0;
+	tmp |= value << TCC_DRVCTRL_NRV0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV1;
+	tmp |= value << TCC_DRVCTRL_NRV1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV2;
+	tmp |= value << TCC_DRVCTRL_NRV2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV3;
+	tmp |= value << TCC_DRVCTRL_NRV3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV4;
+	tmp |= value << TCC_DRVCTRL_NRV4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV5;
+	tmp |= value << TCC_DRVCTRL_NRV5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV6;
+	tmp |= value << TCC_DRVCTRL_NRV6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV7;
+	tmp |= value << TCC_DRVCTRL_NRV7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN0;
+	tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN1;
+	tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN2;
+	tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN3;
+	tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN4;
+	tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN5;
+	tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN6;
+	tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN7;
+	tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL0(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL1(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DRVCTRL.reg;
+}
+
+static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_DBGRUN;
+	tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_FDDBD;
+	tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_OVFEO;
+	tmp |= value << TCC_EVCTRL_OVFEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TRGEO;
+	tmp |= value << TCC_EVCTRL_TRGEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTEO;
+	tmp |= value << TCC_EVCTRL_CNTEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV0;
+	tmp |= value << TCC_EVCTRL_TCINV0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV1;
+	tmp |= value << TCC_EVCTRL_TCINV1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI0;
+	tmp |= value << TCC_EVCTRL_TCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI1;
+	tmp |= value << TCC_EVCTRL_TCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI0;
+	tmp |= value << TCC_EVCTRL_MCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI1;
+	tmp |= value << TCC_EVCTRL_MCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI2;
+	tmp |= value << TCC_EVCTRL_MCEI2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI3;
+	tmp |= value << TCC_EVCTRL_MCEI3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI4;
+	tmp |= value << TCC_EVCTRL_MCEI4_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI5;
+	tmp |= value << TCC_EVCTRL_MCEI5_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO0;
+	tmp |= value << TCC_EVCTRL_MCEO0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO1;
+	tmp |= value << TCC_EVCTRL_MCEO1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO2;
+	tmp |= value << TCC_EVCTRL_MCEO2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO3;
+	tmp |= value << TCC_EVCTRL_MCEO3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO4;
+	tmp |= value << TCC_EVCTRL_MCEO4_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO5;
+	tmp |= value << TCC_EVCTRL_MCEO5_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT0_Msk;
+	tmp |= TCC_EVCTRL_EVACT0(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT1_Msk;
+	tmp |= TCC_EVCTRL_EVACT1(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
+	tmp |= TCC_EVCTRL_CNTSEL(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE0;
+	tmp |= value << TCC_PATT_PGE0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE1;
+	tmp |= value << TCC_PATT_PGE1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE2;
+	tmp |= value << TCC_PATT_PGE2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE3;
+	tmp |= value << TCC_PATT_PGE3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE4;
+	tmp |= value << TCC_PATT_PGE4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE5;
+	tmp |= value << TCC_PATT_PGE5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE6;
+	tmp |= value << TCC_PATT_PGE6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE7;
+	tmp |= value << TCC_PATT_PGE7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV0;
+	tmp |= value << TCC_PATT_PGV0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV1;
+	tmp |= value << TCC_PATT_PGV1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV2;
+	tmp |= value << TCC_PATT_PGV2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV3;
+	tmp |= value << TCC_PATT_PGV3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV4;
+	tmp |= value << TCC_PATT_PGV4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV5;
+	tmp |= value << TCC_PATT_PGV5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV6;
+	tmp |= value << TCC_PATT_PGV6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV7;
+	tmp |= value << TCC_PATT_PGV7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->PATT.reg;
+}
+
+static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CIPEREN;
+	tmp |= value << TCC_WAVE_CIPEREN_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN0;
+	tmp |= value << TCC_WAVE_CICCEN0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN1;
+	tmp |= value << TCC_WAVE_CICCEN1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN2;
+	tmp |= value << TCC_WAVE_CICCEN2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN3;
+	tmp |= value << TCC_WAVE_CICCEN3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL0;
+	tmp |= value << TCC_WAVE_POL0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL1;
+	tmp |= value << TCC_WAVE_POL1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL2;
+	tmp |= value << TCC_WAVE_POL2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL3;
+	tmp |= value << TCC_WAVE_POL3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL4;
+	tmp |= value << TCC_WAVE_POL4_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL5;
+	tmp |= value << TCC_WAVE_POL5_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP0;
+	tmp |= value << TCC_WAVE_SWAP0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP1;
+	tmp |= value << TCC_WAVE_SWAP1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP2;
+	tmp |= value << TCC_WAVE_SWAP2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP3;
+	tmp |= value << TCC_WAVE_SWAP3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_WAVEGEN_Msk;
+	tmp |= TCC_WAVE_WAVEGEN(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_RAMP_Msk;
+	tmp |= TCC_WAVE_RAMP(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->WAVE.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_DITHER_Msk;
+	tmp |= TCC_PER_DITH4_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_DITHER_Msk;
+	tmp |= TCC_PER_DITH5_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_DITHER_Msk;
+	tmp |= TCC_PER_DITH6_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_DITHER_Msk;
+	tmp |= TCC_CC_DITH4_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_DITHER_Msk;
+	tmp |= TCC_CC_DITH5_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_DITHER_Msk;
+	tmp |= TCC_CC_DITH6_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB0;
+	tmp |= value << TCC_PATTBUF_PGEB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB1;
+	tmp |= value << TCC_PATTBUF_PGEB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB2;
+	tmp |= value << TCC_PATTBUF_PGEB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB3;
+	tmp |= value << TCC_PATTBUF_PGEB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB4;
+	tmp |= value << TCC_PATTBUF_PGEB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB5;
+	tmp |= value << TCC_PATTBUF_PGEB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB6;
+	tmp |= value << TCC_PATTBUF_PGEB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB7;
+	tmp |= value << TCC_PATTBUF_PGEB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB0;
+	tmp |= value << TCC_PATTBUF_PGVB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB1;
+	tmp |= value << TCC_PATTBUF_PGVB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB2;
+	tmp |= value << TCC_PATTBUF_PGVB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB3;
+	tmp |= value << TCC_PATTBUF_PGVB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB4;
+	tmp |= value << TCC_PATTBUF_PGVB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB5;
+	tmp |= value << TCC_PATTBUF_PGVB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB6;
+	tmp |= value << TCC_PATTBUF_PGVB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB7;
+	tmp |= value << TCC_PATTBUF_PGVB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATTBUF.reg;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERBUF.reg;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TCC_E53_H_INCLUDED */
+#endif /* _SAME53_TCC_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_trng_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_trng_e53.h
new file mode 100644
index 000000000..2a1cf2034
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_trng_e53.h
@@ -0,0 +1,380 @@
+/**
+ * \file
+ *
+ * \brief SAM TRNG
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_TRNG_COMPONENT_
+#ifndef _HRI_TRNG_E53_H_INCLUDED_
+#define _HRI_TRNG_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TRNG_CRITICAL_SECTIONS)
+#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TRNG_CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_trng_data_reg_t;
+typedef uint8_t  hri_trng_ctrla_reg_t;
+typedef uint8_t  hri_trng_evctrl_reg_t;
+typedef uint8_t  hri_trng_intenset_reg_t;
+typedef uint8_t  hri_trng_intflag_reg_t;
+
+static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	((Trng *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos;
+}
+
+static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+	} else {
+		((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+	}
+}
+
+static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTENSET.reg;
+}
+
+static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data)
+{
+	((Trng *)hw)->INTENSET.reg = data;
+	((Trng *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Trng *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->DATA.reg;
+}
+
+static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_ENABLE;
+	tmp |= value << TRNG_CTRLA_ENABLE_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_RUNSTDBY;
+	tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->CTRLA.reg;
+}
+
+static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= ~TRNG_EVCTRL_DATARDYEO;
+	tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos;
+	((Trng *)hw)->EVCTRL.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Trng *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TRNG_E53_H_INCLUDED */
+#endif /* _SAME53_TRNG_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_usb_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_usb_e53.h
new file mode 100644
index 000000000..e55813591
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_usb_e53.h
@@ -0,0 +1,9335 @@
+/**
+ * \file
+ *
+ * \brief SAM USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_USB_COMPONENT_
+#ifndef _HRI_USB_E53_H_INCLUDED_
+#define _HRI_USB_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_USB_CRITICAL_SECTIONS)
+#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define USB_CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_usb_padcal_reg_t;
+typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdesc_bank_extreg_reg_t;
+typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t;
+typedef uint16_t hri_usbdescriptordevice_extreg_reg_t;
+typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdescriptorhost_extreg_reg_t;
+typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t;
+typedef uint16_t hri_usbdevice_ctrlb_reg_t;
+typedef uint16_t hri_usbdevice_epintsmry_reg_t;
+typedef uint16_t hri_usbdevice_fnum_reg_t;
+typedef uint16_t hri_usbdevice_intenset_reg_t;
+typedef uint16_t hri_usbdevice_intflag_reg_t;
+typedef uint16_t hri_usbhost_ctrlb_reg_t;
+typedef uint16_t hri_usbhost_fnum_reg_t;
+typedef uint16_t hri_usbhost_intenset_reg_t;
+typedef uint16_t hri_usbhost_intflag_reg_t;
+typedef uint16_t hri_usbhost_pintsmry_reg_t;
+typedef uint32_t hri_usb_descadd_reg_t;
+typedef uint32_t hri_usbdesc_bank_addr_reg_t;
+typedef uint32_t hri_usbdesc_bank_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptordevice_addr_reg_t;
+typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptorhost_addr_reg_t;
+typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t;
+typedef uint8_t  hri_usb_ctrla_reg_t;
+typedef uint8_t  hri_usb_fsmstatus_reg_t;
+typedef uint8_t  hri_usb_qosctrl_reg_t;
+typedef uint8_t  hri_usb_syncbusy_reg_t;
+typedef uint8_t  hri_usbdesc_bank_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptordevice_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptorhost_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_dadd_reg_t;
+typedef uint8_t  hri_usbdevice_epcfg_reg_t;
+typedef uint8_t  hri_usbdevice_epintenset_reg_t;
+typedef uint8_t  hri_usbdevice_epintflag_reg_t;
+typedef uint8_t  hri_usbdevice_epstatus_reg_t;
+typedef uint8_t  hri_usbdevice_status_reg_t;
+typedef uint8_t  hri_usbendpoint_epcfg_reg_t;
+typedef uint8_t  hri_usbendpoint_epintenset_reg_t;
+typedef uint8_t  hri_usbendpoint_epintflag_reg_t;
+typedef uint8_t  hri_usbendpoint_epstatus_reg_t;
+typedef uint8_t  hri_usbhost_binterval_reg_t;
+typedef uint8_t  hri_usbhost_flenhigh_reg_t;
+typedef uint8_t  hri_usbhost_hsofc_reg_t;
+typedef uint8_t  hri_usbhost_pcfg_reg_t;
+typedef uint8_t  hri_usbhost_pintenset_reg_t;
+typedef uint8_t  hri_usbhost_pintflag_reg_t;
+typedef uint8_t  hri_usbhost_pstatus_reg_t;
+typedef uint8_t  hri_usbhost_status_reg_t;
+typedef uint8_t  hri_usbpipe_binterval_reg_t;
+typedef uint8_t  hri_usbpipe_pcfg_reg_t;
+typedef uint8_t  hri_usbpipe_pintenset_reg_t;
+typedef uint8_t  hri_usbpipe_pintflag_reg_t;
+typedef uint8_t  hri_usbpipe_pstatus_reg_t;
+
+static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbpipe_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pintflag_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbpipe_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbhost_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pintflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbhost_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                               hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const           hw,
+                                                                           hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                    hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                        hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                           hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                                     hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const             hw,
+                                                                               hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->EXTREG.reg;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const                  hw,
+                                                                  hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const                  hw,
+                                                             hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptorhost_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw,
+                                                                                   uint8_t           submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                    bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                             uint8_t           submodule_index,
+                                                                             hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                      hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                         uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                           hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptorhost_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw,
+                                                                                               uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR)
+	       >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW)
+	       >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_bk_reg_t
+hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptorhost_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER)
+	       >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER)
+	       >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER)
+	       >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t
+hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw,
+                                                                                 uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbendpoint_epintflag_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t
+hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t
+hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbdevice_epintflag_reg_t
+hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw,
+                                                                             uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbdevice_epintflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdevice_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_epintenset_reg_t
+hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_usbdevice_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = mask;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_usbhost_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const            hw,
+                                                                       hri_usbdevice_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = data;
+	((Usb *)hw)->DEVICE.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = mask;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const          hw,
+                                                                   hri_usbhost_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTENSET.reg;
+}
+
+static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = data;
+	((Usb *)hw)->HOST.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.SYNCBUSY.reg;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const          hw,
+                                                                           hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const          hw,
+                                                                               hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const          hw,
+                                                                      hri_usbdevice_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.STATUS.reg;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const       hw,
+                                                                        hri_usb_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FSMSTATUS.reg;
+}
+
+static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const        hw,
+                                                                       hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const        hw,
+                                                                      hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FNUM.reg;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const          hw,
+                                                                              hri_usbhost_flenhigh_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const          hw,
+                                                                      hri_usbhost_flenhigh_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FLENHIGH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FLENHIGH.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const             hw,
+                                                                            hri_usbdevice_epintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const          hw,
+                                                                      hri_usbhost_pintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PINTSMRY.reg;
+}
+
+static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg = data;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw)
+{
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	return ((Usb *)hw)->HOST.CTRLA.reg;
+}
+
+static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.QOSCTRL.reg;
+}
+
+static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_DETACH;
+	tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_UPRSM;
+	tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_NREPLY;
+	tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTJ;
+	tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTK;
+	tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_OPMODE2;
+	tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_GNAK;
+	tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk;
+	tmp |= USB_DEVICE_CTRLB_SPDCONF(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk;
+	tmp |= USB_DEVICE_CTRLB_LPMHDSK(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLB.reg;
+}
+
+static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_RESUME;
+	tmp |= value << USB_HOST_CTRLB_RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_AUTORESUME;
+	tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTJ;
+	tmp |= value << USB_HOST_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTK;
+	tmp |= value << USB_HOST_CTRLB_TSTK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SOFE;
+	tmp |= value << USB_HOST_CTRLB_SOFE_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_BUSRESET;
+	tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_VBUSOK;
+	tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_L1RESUME;
+	tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const       hw,
+                                                                       hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk;
+	tmp |= USB_HOST_CTRLB_SPDCONF(data);
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.CTRLB.reg;
+}
+
+static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_ADDEN;
+	tmp |= value << USB_DEVICE_DADD_ADDEN_Pos;
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const        hw,
+                                                                      hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_DADD_Msk;
+	tmp |= USB_DEVICE_DADD_DADD(data);
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DADD.reg;
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENCE;
+	tmp |= value << USB_HOST_HSOFC_FLENCE_Pos;
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENC_Msk;
+	tmp |= USB_HOST_HSOFC_FLENC(data);
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.HSOFC.reg;
+}
+
+static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_MFNUM_Msk;
+	tmp |= USB_HOST_FNUM_MFNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_FNUM_Msk;
+	tmp |= USB_HOST_FNUM_FNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FNUM.reg;
+}
+
+static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->HOST.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.DESCADD.reg;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PADCAL.reg;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const        hw,
+                                                                       hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const        hw,
+                                                                           hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.STATUS.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                                 hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const           hw,
+                                                                             hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                             hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                                hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                   hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const             hw,
+                                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const                hw,
+                                                             hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                         hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                      bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void
+hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR)
+	       >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_USB_E53_H_INCLUDED */
+#endif /* _SAME53_USB_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_wdt_e53.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_wdt_e53.h
new file mode 100644
index 000000000..a0bb36194
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/hri/hri_wdt_e53.h
@@ -0,0 +1,617 @@
+/**
+ * \file
+ *
+ * \brief SAM WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME53_WDT_COMPONENT_
+#ifndef _HRI_WDT_E53_H_INCLUDED_
+#define _HRI_WDT_E53_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
+#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define WDT_CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_wdt_syncbusy_reg_t;
+typedef uint8_t  hri_wdt_clear_reg_t;
+typedef uint8_t  hri_wdt_config_reg_t;
+typedef uint8_t  hri_wdt_ctrla_reg_t;
+typedef uint8_t  hri_wdt_ewctrl_reg_t;
+typedef uint8_t  hri_wdt_intenset_reg_t;
+typedef uint8_t  hri_wdt_intflag_reg_t;
+
+static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	((Wdt *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+}
+
+static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
+}
+
+static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+	} else {
+		((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+	}
+}
+
+static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+}
+
+static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTENSET.reg;
+}
+
+static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
+{
+	((Wdt *)hw)->INTENSET.reg = data;
+	((Wdt *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Wdt *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ENABLE;
+	tmp |= value << WDT_CTRLA_ENABLE_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_WEN;
+	tmp |= value << WDT_CTRLA_WEN_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ALWAYSON;
+	tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
+{
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	return ((Wdt *)hw)->CTRLA.reg;
+}
+
+static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_PER_Msk;
+	tmp |= WDT_CONFIG_PER(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_WINDOW_Msk;
+	tmp |= WDT_CONFIG_WINDOW(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CONFIG.reg;
+}
+
+static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
+	tmp |= WDT_EWCTRL_EWOFFSET(data);
+	((Wdt *)hw)->EWCTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->EWCTRL.reg;
+}
+
+static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CLEAR.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_WDT_E53_H_INCLUDED */
+#endif /* _SAME53_WDT_COMPONENT_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Arduino Reference.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Arduino Reference.doc
new file mode 100644
index 000000000..c3fcefe81
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Arduino Reference.doc	
@@ -0,0 +1,292 @@
+namespace ClearCore {
+/**
+\page ArduinoRef ClearCore Arduino API Reference
+<h1> Overview </h1>
+The ClearCore Arduino Wrapper Library, used in conjunction with the standard ClearCore Motion and I/O Library, allows for easy programming in the lightweight Arduino IDE. Using ClearCore with the Arduino IDE is suitable for all developers, from confident Arduino users to novice programmers or even experienced programmers who want to create a prototype as quickly as possible.
+
+This section serves as a reference guide for the ClearCore Arduino wrapper functions that can be used to control your ClearCore. Because this is a software wrapper, each of the functions within it interacts with the ClearCore Motion and I/O Library. As such, some of the functions you see here were modified from the original Arduino counterparts. Any differences from the standard Arduino functions are documented below as well.
+
+<table>
+<caption>ClearCore connector aliases</caption>
+<tr><th>Name<th>Arduino Alias
+<tr><td>#ConnectorIO0 <td><center>IO0</center>
+<tr><td>#ConnectorIO1 <td><center>IO1</center>
+<tr><td>#ConnectorIO2 <td><center>IO2</center>
+<tr><td>#ConnectorIO3 <td><center>IO3</center>
+<tr><td>#ConnectorIO4 <td><center>IO4</center>
+<tr><td>#ConnectorIO5 <td><center>IO5</center>
+<tr><td>#ConnectorDI6 <td><center>DI6</center>
+<tr><td>#ConnectorDI7 <td><center>DI7</center>
+<tr><td>#ConnectorDI8 <td><center>DI8</center>
+<tr><td>#ConnectorA9 <td><center>A9</center>
+<tr><td>#ConnectorA10 <td><center>A10</center>
+<tr><td>#ConnectorA11 <td><center>A11</center>
+<tr><td>#ConnectorA12 <td><center>A12</center>
+<tr><td>#ConnectorUsb <td><center>Serial</center>
+<tr><td>#ConnectorCOM0 <td><center>Serial0</center>
+<tr><td>#ConnectorCOM1 <td><center>Serial1</center>
+</table>
+<br>
+
+<table>
+<caption>ClearCore motor input aliases</caption>
+<tr><th>Name<th>Arduino Alias
+<tr><td>M-0 Input A <td><center>M0_INA</center>
+<tr><td>M-0 Input B <td><center>M0_INB</center>
+<tr><td>M-1 Input A <td><center>M1_INA</center>
+<tr><td>M-1 Input B <td><center>M1_INB</center>
+<tr><td>M-2 Input A <td><center>M2_INA</center>
+<tr><td>M-2 Input B <td><center>M2_INB</center>
+<tr><td>M-3 Input A <td><center>M3_INA</center>
+<tr><td>M-3 Input B <td><center>M3_INB</center>
+</table>
+<br>
+
+<h2> SDK Examples </h2>
+As part of the Arduino installation package a number of examples sketches are included. These sketches demonstrate how to utilize the various features of ClearCore using standard Arduino functions and classes. The examples may be found in the Arduino IDE under the Examples menu, as seen below:
+
+<img src="examples.png">
+
+
+<h2> Deviations from standard Arduino </h2>
+    - The pin mode INPUT_PULLUP has no functional difference from INPUT. The two may be used interchangeably.
+    - analogRead() has an extra optional parameter to specify the desired units of the 
+    analog reading returned:
+        - 'units' may be set to ADC_RAW (default) or MILLVOLTS.
+    - analogWrite() has two extra optional parameters relating to the output:
+        - 'mode' may be set to either PWM (default) or CURRENT.
+        - 'units' may be set to either DAC_RAW (default) or MICROAMPS.
+    - analogReference() is not a supported function. The ClearCore analog input reference voltage is not user-modifiable.
+    - The default analog read resolution is 12 bits, rather than 10 bits.
+    - analogWriteResolution() is not a supported function. The analog write resolution 
+    of the ClearCore is 12 bits and is not user-modifiable.
+    - Tones are sine waves rather than half-duty square waves like most Arduinos.
+    - Arduino-style periodic interrupts using Timer0 and Timer1 are not supported. The AVR registers used to configure these Timers
+    do not exist in the ClearCore hardware. Refer to the PeriodicInterrupt example in the Microchip_Examples directory for an alternative
+    way to achieve the same functionality as Timer0 and Timer1.
+    - The Serial keyword represents the USB serial port. Serial0 and Serial1 represent the COM-0 and COM-1 serial ports respectively.
+    - The Servo and Stepper Arduino libraries are not supported by ClearCore. For motor control, defer to the
+    underlying ClearCore I/O and Motion Control library. (See the \ref MotorDriverMain documentation for more information.)
+    - The pulseIn() and pulseInLong() functions do not require interrupts to be enabled.
+    - There is no functional difference between pulseIn() and pulseInLong().
+    
+    
+<h2> Global Types, Enumerators, and Objects </h2>
+
+<h3> Pin Mode </h3>
+    - Digital pins can be used as INPUT, INPUT_PULLUP, or OUTPUT. Changing a pin with pinMode() changes the electrical behavior of the pin.
+    - More information can be found <a href="https://www.arduino.cc/reference/en/language/variables/constants/constants/" >here</a>.
+
+<h3> Pin Status </h3>
+    - When reading or writing to a digital pin there are only two possible values a pin can take/be-set-to: HIGH and LOW.
+    - More information can be found <a href="https://www.arduino.cc/reference/en/language/variables/constants/constants/" >here</a>.
+
+<h3> Serial </h3>
+    - Used for communication between the Arduino board and a computer or other devices. All Arduino boards have at least one serial port (also known as a UART or USART), and some have several.
+        - ClearCore may use either Serial, Serial0, or Serial1.
+    - More information can be found <a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/" >here</a>.
+
+
+<h2> Basic I/O </h2>
+
+<h3> pinMode(pin, mode) </h3>
+    - Configures the specified pin to behave either as an input or an output.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/digital-io/pinmode/" >Arduino.cc Reference</a>
+    
+<h3> digitalRead(pin) </h3>
+    - Valid pins: All pins
+    - Reads the value from a specified digital pin, either HIGH or LOW.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/digital-io/digitalread/" >Arduino.cc Reference</a>
+    
+<h3> digitalWrite(pin, value) </h3>
+    - Valid pins: IO0, IO1, IO2, IO3, IO4, IO5, M0_INA, M0_INB, M1_INA, M1_INB, M2_INA, M2_INB, M3_INA, M3_INB
+    - Write a HIGH or a LOW value to a digital pin.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/digital-io/digitalwrite/" >Arduino.cc Reference</a>
+    
+<h3> analogRead(pin, units[optional]) </h3>
+    - Valid pins: A9, A10, A11, A12
+    - Reads the value from the specified analog pin. The analog-to-digital converter on
+    the ClearCore has a default resolution of 12 bits (not 10 bits like most Arduino boards).\n
+    The allowable range of analog input values is 0 to 10V. This function will map input 
+    voltages between 0 and 10V to integer values between 0 and 4095, unless the analog\n
+    read resolution is changed from its default value via a call to analogReadResolution().
+    - The <em>units</em> argument, if supplied, must be one of the following values:
+        - ADC_RAW - default, return the raw ADC value, with bit depth specified by analogReadResolution().
+        - MILLIVOLTS - the voltage level is returned, expressed in millivolts
+    - <a href="https://www.arduino.cc/reference/en/language/functions/analog-io/analogread/" >Arduino.cc Reference</a>
+    
+<h3> analogWrite(pin, value, mode[optional], units[optional]) </h3>
+    - Valid pins: IO0
+    - Writes an analog value (PWM wave) to a pin. Can be used to light a LED at varying brightnesses or drive a motor at various speeds. After a call to analogWrite(), \n
+    the pin will generate a steady rectangular wave of the specified duty cycle until the next call to analogWrite() (or a call to digitalRead() or digitalWrite()) on the same pin.
+    - The <em>mode</em> argument, if supplied, must be one of the following values: 
+        - PWM - default, digital PWM output
+        - CURRENT - analog current output, exclusive to the ClearCore
+    - The <em>units</em> argument, if supplied, must be one of the following values:
+        - DAC_RAW - default, the raw 12-bit DAC reading is returned 
+        - MICROAMPS - the voltage level is returned, expressed in microamps
+    - <a href="https://www.arduino.cc/reference/en/language/functions/analog-io/analogwrite/" >Arduino.cc Reference</a>
+    
+<h3> analogReadResolution(bits) </h3>
+    - Sets the size (in bits) of the value returned by analogRead().
+    - The analog read resolution of the ClearCore defaults to 12 bits (returns values 0-4095), 
+    rather than the Arduino standard resolution of 10 bits.
+    - The allowable bit resolutions are: 8, 10, and 12.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/zero-due-mkr-family/analogreadresolution/" >Arduino.cc Reference</a>
+    
+<h3> analogWriteResolution(bits) </h3>
+    - Not supported. The analog write resolution of the ClearCore is 12 bits and is not
+    user-modifiable.
+    
+<h3> analogReference(type) </h3>
+    - Not supported. The ClearCore analog input reference voltage is not user-modifiable.
+    
+
+<h2> Advanced I/O </h2>
+
+<h3> tone(pin, frequency, duration[optional]) </h3>
+    - Valid pins: IO4, IO5
+    - Generates an audible sine wave of the specified frequency on a pin. This is in contrast with standard
+    Arduino boards that produce a square wave tone with 50% duty cycle.\n
+    A duration can be specified, in milliseconds, otherwise the tone continues to sound until a call to noTone().
+    - <a href="https://www.arduino.cc/reference/en/language/functions/advanced-io/tone/" >Arduino.cc Reference</a>
+    
+<h3> noTone(pin) </h3>
+    - Stops the generation of an audible sine wave triggered by tone(). Has no effect if no tone is being generated on the specified pin.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/advanced-io/notone/" >Arduino.cc Reference</a>
+    
+<h3 id=pulseIn> pulseIn(pin, value, timeout[optional]) </h3>
+    - Reads a pulse (HIGH or LOW) on a pin, starts timing, then waits for the pin to change
+    state and stops timing. Returns the length of the pulse in microseconds,\n or zero if no
+    complete pulse was received within the timeout (specified in microseconds). If no timeout
+    argument is supplied, the timeout will default to\n 1,000,000 microseconds (1 second).
+    - <a href="https://www.arduino.cc/reference/en/language/functions/advanced-io/pulsein/" >Arduino.cc Reference</a>
+
+<h3> pulseInLong(pin, value, timeout[optional]) </h3>
+    - There is no functional difference between pulseIn() and pulseInLong() on the ClearCore board.
+    - See <a href="#pulseIn">pulseIn()</a>.
+
+
+<h2> Time </h2>
+    
+<h3> delay(ms) </h3>
+    - Pauses the program for the amount of time (in milliseconds) specified via parameter <em>ms</em>.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/time/delay/" >Arduino.cc Reference</a>
+
+<h3> delayMicroseconds(us) </h3>
+    - Pauses the program for the amount of time (in microseconds) specified via parameter <em>us</em>.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/time/delaymicroseconds/" >Arduino.cc Reference</a>
+    
+<h3> millis() </h3>
+    - Returns the number of milliseconds elapsed since the board began running the current program. This number will overflow (return to zero), after approximately 50 days.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/time/millis/" >Arduino.cc Reference</a>
+    
+<h3> micros() </h3>
+    - Returns the number of microseconds elapsed since the board began running the current program. This number will overflow (return to zero), after approximately 70 minutes.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/time/millis/" >Arduino.cc Reference</a>
+
+
+<h2> Interrupts </h2>
+
+ClearCore pins DI6 through A12 can be set up as digital interrupts.
+
+<h3> attachInterrupt(digitalPinToInterrupt(pin), ISR, mode) </h3>
+    - The first parameter to attachInterrupt() is an interrupt number. Use digitalPinToInterrupt(pin) to translate the actual digital pin to the specific interrupt number. For example,\n 
+    if you connect to pin 3 (DI-6), use digitalPinToInterrupt(DI6) as the first parameter to attachInterrupt().
+    - The ISR must be a pointer to a function that takes no parameters and returns void. This is
+    the function that will get called when the condition specified by <em>mode</em> is detected
+    on the pin.
+    - The ClearCore supports interrupts on the following state conditions: LOW, CHANGE, RISING, FALLING, and HIGH (specified by <em>mode</em>).
+    - <a href="https://www.arduino.cc/reference/en/language/functions/external-interrupts/attachinterrupt/" >Arduino.cc Reference</a>
+    
+<h3> detachInterrupt(pin) </h3>
+    - Turns off the interrupt registered on the specified pin.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/external-interrupts/detachinterrupt/" >Arduino.cc Reference</a>
+    
+<h3> interrupts() </h3>
+    - Re-enables interrupts after they’ve been disabled by nointerrupts().
+    - <a href="https://www.arduino.cc/reference/en/language/functions/interrupts/interrupts/" >Arduino.cc Reference</a>
+    
+<h3> noInterrupts() </h3>
+    - Disables interrupts on any pins that have had interrupts attached.
+    For any pin that had an attached interrupt, if the condition specified by <em>mode</em> in the corresponding attachInterrupt()\n call occurs while the interrupt is detached,
+    it will still be detected and the ISR will fire upon re-enabling interrupts with interrupts().
+    To completely disable interrupt functionality on the pin,\n use detachInterrupt() instead.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/interrupts/nointerrupts/" >Arduino.cc Reference</a>
+
+
+<h2> Serial </h2>
+<a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/" >Arduino.cc Reference</a>
+
+<h3> begin(speed, config[optional]) </h3>
+    - Sets the data rate in bits per second (baud) for serial data transmission. An optional second argument configures the data, parity, and stop bits. These default to 8 data bits, no parity, and one\n stop bit.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/begin/" >Arduino.cc Reference</a>
+    
+<h3> write(val) </h3>
+    - Writes binary data to the serial port.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/write/" >Arduino.cc Reference</a>
+    
+<h3> print(val, format[optional]) </h3>
+    - Prints data to the serial port as human-readable ASCII text. An optional second parameter specifies the base (format) to use; permitted values are BIN (binary, or base 2), OCT (octal, or base 8),\n  DEC (decimal, or base 10), HEX (hexadecimal, or base 16). For floating point numbers, this second parameter specifies the number of decimal places to use.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/print/" >Arduino.cc Reference</a>
+    
+<h3> println(val, format[optional]) </h3>
+    - Prints data to the serial port as human-readable ASCII text followed by a carriage return character (ASCII 13, or '\\r') and a newline character (ASCII 10, or '\\n').\n This command takes the same formats as Serial.print().
+    - <a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/println/" >Arduino.cc Reference</a>
+    
+<h3> read() </h3>
+    - Reads incoming serial data.
+    - <a href="https://www.arduino.cc/reference/en/language/functions/communication/serial/read/" >Arduino.cc Reference</a>
+    
+<h3> ttl(bool isTtl) </h3>
+    - Sets whether the serial COM port is wired as TTL or not.
+    - This is a ClearCore-specific addition to the Arduino standard library.
+ 
+
+<h2> SPI </h2>
+<a href="https://www.arduino.cc/en/reference/SPI" >Arduino.cc Reference</a>
+
+<h3> SPISettings(speedMaximum, dataOrder, dataMode) </h3>
+    - The SPISettings object is used to configure the SPI port for your SPI device. All 3 parameters are combined in a single SPISettings object, which is passed to SPI.beginTransaction().
+    - <a href="https://www.arduino.cc/en/Reference/SPISettings" >Arduino.cc Reference</a>
+    
+<h3> begin() </h3>
+    - Initializes the SPI bus by setting SCK, MOSI, and SS to outputs, pulling SCK and MOSI low, and SS high.
+    - <a href="https://www.arduino.cc/en/Reference/SPIBegin" >Arduino.cc Reference</a>
+    
+<h3> beginTransaction(mySettings) </h3>
+    - Initializes the SPI bus using the defined SPISettings.
+    - <a href="https://www.arduino.cc/en/Reference/SPIbeginTransaction" >Arduino.cc Reference</a>
+    
+<h3> transfer(val) </h3>
+    - Performs the SPI transfer by sending the passed-in <em>val</em> and returning the received data.
+    - <a href="https://www.arduino.cc/en/Reference/SPITransfer" >Arduino.cc Reference</a>
+    
+<h3> endTransaction() </h3>
+    - Stop using the SPI bus. Normally this is called after de-asserting the chip select to allow other libraries to use the SPI bus.
+    - <a href="https://www.arduino.cc/en/Reference/SPIendTransaction" >Arduino.cc Reference</a>
+
+    
+<h2> Ethernet </h2>
+<a href="https://www.arduino.cc/en/Reference/Ethernet" >Arduino.cc Reference</a>
+
+<h3> IPAddress() </h3>
+    - Defines an IP address. It can be used to declare both local and remote addresses.
+    - <a href="https://www.arduino.cc/en/Reference/EthernetIPAddress" >Arduino.cc Reference</a>
+    
+<h3> begin(mac) </h3>
+    - Initializes the ethernet library and network settings. Any value supplied for the MAC address (<em>mac</em>) parameter will be ignored. The ClearCore's MAC address is stored in \n
+    non-volatile memory and should not be altered.
+    - <a href="https://www.arduino.cc/en/Reference/EthernetBegin" >Arduino.cc Reference</a>
+    
+<h3> linkStatus() </h3>
+    - Tells you whether the link is active. LinkOFF could indicate the Ethernet cable is unplugged or defective. 
+    - <a href="https://www.arduino.cc/en/Reference/EthernetLinkStatus" >Arduino.cc Reference</a>
+    
+    
+<h2> External Reference </h2>
+See official Arduino documentation at https://www.arduino.cc/reference/en.
+
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/CCIO.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/CCIO.doc
new file mode 100644
index 000000000..d4efef869
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/CCIO.doc
@@ -0,0 +1,78 @@
+namespace ClearCore {
+/**
+\page CCIOMain ClearCore I/O Expansion Board
+<h1> Overview </h1>
+    For applications that require additional digital I/O pins, ClearCore may be linked with up to 8 ClearCore I/O Expansion Board (CCIO-8) modules. The ClearCore software package provides a \n
+    CcioBoardManager that interfaces with and controls the CCIO-8 link. Each CCIO-8 module has 8 CcioPin connectors that may be individually configured as a digital input or output, providing up to 64 \n
+    additional digital I/O connectors.
+
+    The CcioBoardManager uses SPI to communicate to the CCIO-8 modules. The CCIO-8 modules are chained together and attached to either the COM-0 or COM-1 connectors. When a COM port is opened in CCIO \n
+    mode, ClearCore automatically detects how many CCIO-8 modules are in the chain. The CcioBoardManager will then periodically refresh the input and output CcioPin connectors as part of the ClearCore \n
+    system's background processing.
+    
+<h2> Wiring and Initialization</h2>
+    - Connect 24V power to the PWR terminal block on each CCIO-8 module (next to CCIO-8 pin 3). 24V power may be supplied three ways: from a source independent of the ClearCore, by connecting to any \n
+    of the main ClearCore board's I/O connectors, or by connecting to an I/O connector of a CCIO-8 earlier in the chain.
+    - Check that the Power OK LED (next to CCIO-8 pin 4) on each CCIO-8 module is on.
+    - Connect either the COM-0 or COM-1 port from the ClearCore to the COM_IN port on the CCIO-8 module with an RJ45 cable.
+        - If multiple CCIO-8 modules are needed, create a chain by connecting the COM_OUT port of CCIO-8 module <em>(N - 1)</em> to the COM_IN port of CCIO-8 module <em>N</em>. Repeat until all of the \n
+        modules (up to 8) are linked together.
+    - Check that the LED in each connected COM_IN and COM_OUT port is on.
+        - The LED in the COM_OUT port on the final CCIO-8 module in the chain should be off.
+    - Put the ClearCore COM connector in CCIO mode using SerialDriver's \ref SerialDriver#Mode() function then open the port. Calling \ref SerialDriver#PortOpen() "PortOpen()" in CCIO mode will call \n
+    the \ref CcioBoardManager#CcioDiscover() "CcioDiscover()" function automatically in the background.
+        \code{.cpp}
+        // Set COM-1's mode to be the port controlling a CCIO-8 link
+        ConnectorCOM1.Mode(Connector::CCIO);
+        ConnectorCOM1.PortOpen();
+        \endcode
+    - Verify that the number of discovered CCIO-8 modules matches the number of modules that were wired.
+        \code{.cpp}
+        // Are the CCIO-8 modules properly wired and communicating?
+        if (CcioMgr.CcioCount() != myExpectedModules) {
+            // The link size is wrong, do something
+        }
+        \endcode
+    - The CCIO-8 modules in a link are represented by the letters A-H. The CCIO-8 module that is connected directly to the COM port is addressed using ClearCorePins CLEARCORE_PIN_CCIOA0 through \n
+    CLEARCORE_PIN_CCIOA7. The next CCIO-8 module in the chain uses ClearCorePins CLEARCORE_PIN_CCIOB0 through CLEARCORE_PIN_CCIOB7, and so on.
+
+<h2> Configuring CCIO-8 Pins </h2>
+    - Each pin on the CCIO-8 modules can be independently configured as either a digital output or digital input. 
+        \code{.cpp}
+        // Set CCIO-8 board A, pin 0 to output mode and assert the output.
+        CcioPin *ccioA0 = CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0);
+        if (ccioA0 != nullptr) {
+            ccioA0->Mode(Connector::OUTPUT_DIGITAL);
+            ccioA0->State(1);
+        }
+        // Set CCIO-8 board B, pin 1 to input mode and read the current value.
+        bool value = false;
+        CcioPin *ccioB1 = CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOB1);
+        if (ccioB1 != nullptr) {
+            ccioB1->Mode(Connector::INPUT_DIGITAL);
+            value = ccioB1->State();
+        }
+        \endcode
+
+<h2> Operation </h2>
+    - The CcioBoardManager periodically refreshes the CcioPin values as part of its background processing. The refresh rate varies depending on the length of the CCIO-8 chain.
+        - 1-2 CCIO-8 modules: Refresh at \ref SampleRateHz
+        - 3-4 CCIO-8 modules: Refresh at \ref SampleRateHz / 2
+        - 5-6 CCIO-8 modules: Refresh at \ref SampleRateHz / 3
+        - 7-8 CCIO-8 modules: Refresh at \ref SampleRateHz / 4
+    - CcioBoardManager refresh cycle processing operations:
+        - Ensure that the previous SPI transfer is complete.
+        - Toggle the SPI Slave Select line to activate the outputs that were sent in the previous refresh cycle and latch a snapshot of the inputs.
+        - Check the integrity of the previous input data transfer.
+        - Perform input pin filtering.
+        - Prepare the current output data to transfer.
+        - Initiate a background SPI data transfer.
+        
+    - The CcioBoardManager monitors the status of the CCIO-8 communications to ensure that the link is maintained. 
+        - If all or some of the CCIO-8 link goes offline the StatusManager#StatusRegister#CcioLinkBroken bit will be raised.
+        - The CcioBoardManager automatically attempts to re-establish a broken CCIO-8 link through the Rediscover feature. The CCIO-8 Rediscover feature is enabled by default, but it may be disabled \n
+        if link-breaks and rediscovers need to be manually controlled. \see CcioBoardManager::CcioRediscoverEnable
+    
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/ClearCoreOverview.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/ClearCoreOverview.doc
new file mode 100644
index 000000000..6811420c1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/ClearCoreOverview.doc
@@ -0,0 +1,275 @@
+#include "ClearCore.h";
+namespace ClearCore {
+/**
+
+\mainpage 
+# Introduction
+    ClearCore is an industrial motion and I/O controller featuring flexible, software-configurable I/O with a rich C++ Motion and I/O library. This document serves as a reference guide for the library and the variety of functions used to interface with and control your ClearCore in a motion control application.
+    
+    For ClearCore hardware documentation, including device specifications and I/O wiring examples, see the <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf">ClearCore System Diagram</a>.
+    
+    To get started, follow the ClearCore \ref InstallationInstructions.
+    SDK example projects and a Project Template can be found in the PC program
+    files after installing for Microchip Studio. <br>
+    C:\\Program Files (x86)\\Teknic\\ClearCore-Library x.x [where x.x is the version number]
+    
+# Informational Pages
+    - \ref InstallationInstructions
    - \ref ConnectorMain
+    - \ref MotorDriverMain
+        - \ref MoveGen
+    - \ref UsbMain
+    - \ref SerialDriverMain
+    - \ref CCIOMain
+    - \ref EthernetMain
+    - \ref SdkExamples
+
+# Connectors
+    - 1x DigitalInOutAnalogOut
+        - #ConnectorIO0
+    - 3x DigitalInOut
+        - #ConnectorIO1, #ConnectorIO2, #ConnectorIO3
+    - 2x DigitalInOutHBridge
+        - #ConnectorIO4, #ConnectorIO5
+    - 3x DigitalIn
+        - #ConnectorDI6, #ConnectorDI7, #ConnectorDI8
+    - 4x DigitalInAnalogIn
+        - #ConnectorA9, #ConnectorA10, #ConnectorA11, #ConnectorA12
+    - 1x LedDriver
+        - #ConnectorLed
+    - 4x MotorDriver
+        - #ConnectorM0, #ConnectorM1, #ConnectorM2, #ConnectorM3
+    - 1x SerialUsb
+        - #ConnectorUsb
+    - 2x SerialDriver
+        - #ConnectorCOM0, #ConnectorCOM1
+    - 1x EthernetManager
+        - #EthernetMgr
+    - 1x SerialBase socket to connect an XBee module
+        - #XBee
+    - 1x CcioBoardManager (\ref CCIOMain) providing up to 64x CcioPin connectors 
+        - #CcioMgr
+
+# Connector functionality checklist
+    - \subpage ConnectorFunctionality
+        - A table view of the different functionalities supported by each ClearCore I/O connector.
+
+# Status
+    - \subpage StatusIndicators
+        - \subpage BlinkCodes
+
+# Behavior on Powerup / Resetting
+    - When the ClearCore first powers up, the last-uploaded code will start
+    executing immediately. If no code has been uploaded yet, or if the chip
+    was erased, the ClearCore will start up in bootloader mode. See 
+    \ref InitializationBlinks and \ref BootloaderBlinks for more information.
+    - Pressing the reset button once will restart execution of user code. Quickly
+    double-pressing the reset button will reset the ClearCore into bootloader
+    mode.
+    
+# Arduino Reference
+    - \ref ArduinoRef
+
+# Hardware Reference
+    - Refer to the <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf">ClearCore System Diagram</a>.
+        - Jump to:
+            - <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf#page=1">Overview</a>
+            - <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf#page=2">Connector Wiring</a>
+            - <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf#page=6">Installing Debugger and XBee Modules</a>
+            - <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf#page=7">Block Diagram: I/O and Communication</a>
+            - <a href="https://www.teknic.com/files/downloads/clearcore_system_diagram.pdf#page=8">Block Diagram: Motor I/O and Configuration Shift Register</a>
+
+**/
+//********************************************************************************************
+/**
+\page StatusIndicators Status Indicators
+<h1> Status Indicators </h1>
+    ClearCore has several LEDs that reflect the status of the ClearCore hardware.
+
+    - \subpage IoLed
+    - \subpage ComLed
+    - \subpage UnderGlowLed
+        - \subpage BlinkCodes
+    - \subpage EthernetLed
+    - XBee LED Indicator
+        - Refer to the Associate LED settings of your XBee device.
+    - \subpage CcioLed
+    - \subpage BootloaderBlinks
+    - \subpage InitializationBlinks
+
+**/
+//********************************************************************************************
+/**
+\page IoLed I/O LED Indicators
+<h1> I/O LED Indicators </h1>
+    Near each of the 13 3-pin I/O terminal blocks there is an LED that will indicate the state of that connector.
+    
+<h2> I/O LED States </h2>
+    - Off: Connector is in the logic FALSE state.
+    - On: Connector is in the logic TRUE state.
+    - PWM Modulated: The LED is dimmed to reflect the analog or PWM value on the connector.
+    - Strobed: There is an overload condition.
+**/
+//********************************************************************************************
+/**
+\page ComLed COM Port LED Indicators
+<h1> COM Port LED Indicators </h1>
+    Within each of the COM port connectors, there is an LED that will indicate the state of communications for that connector.
+    
+<h2> COM Port LED States </h2>
+    - Off: The port has not been opened for data communications.
+    - On: The port has been opened and is ready to transmit and receive data.
+    - Breathing: The port has been configured to communicate with one or more ClearCore I/O Expansion (CCIO-8) Boards and the link established between the ClearCore and the CCIO-8 boards is healthy.
+    - Strobing: The port has been configured to communicate with one or more ClearCore I/O Expansion (CCIO-8) Boards and there is an overload condition on one of the CCIO-8 connectors.
+**/
+//********************************************************************************************
+/**
+\page UnderGlowLed Under Glow LED Indicator
+<h1> Under Glow LED Indicator </h1>
+    There are LEDs on the bottom side of the ClearCore board that are used to show the running state of the hardware.
+    
+<h2> Under Glow LED States </h2>
+    - Off: ClearCore is not powered properly.
+    - Breathing: Normal running state. LEDs slowly fade in and out.  
+    - On: Processor has crashed. To recover, double-click the reset button to put the processor into bootloader mode, then upload safe code.
+    - Error Code: A series of stobes and solid blinks indicate an error code that has occurred since the last time the processor was reset.
+        - See \subpage BlinkCodes
+**/
+//********************************************************************************************
+/**
+\page EthernetLed Ethernet LED Indicator
+<h1> Ethernet LED Indicator </h1>
+    The LED within the Ethernet connector indicates the state of the link and network activity on the link.
+    
+<h2> Ethernet LED States </h2>
+    - Off: No link established (link down).
+    - On: Link established but no network activity detected (link up).
+    - Blinking: Network activity detected on the link.
+**/
+//********************************************************************************************
+/**
+\page CcioLed ClearCore I/O Expansion Board (CCIO-8) LED Indicators
+<h1> ClearCore I/O Expansion Board (CCIO-8) LED Indicators </h1>
+    Each ClearCore I/O Expansion Board provides 8 I/O connectors that may be individually configured for digital input or digital output modes.
+    Near each of the 8 3-pin I/O terminal blocks, there is an LED that will indicate the state of that connector.
+    
+<h2> CCIO-8 I/O LED States </h2>
+    - Off: Connector is in the logic FALSE state.
+    - On: Connector is in the logic TRUE state.
+    - Strobing: There is an overload condition.
+**/
+//********************************************************************************************
+/**
+\page BootloaderBlinks Bootloader Mode
+<h1> Bootloader Mode </h1>
+    Bootloader mode is indicated by a continually repeating series of pulses on the bottom row of I/O LEDs. Double-clicking the reset button puts the ClearCore into bootloader mode.
+    - USB connected: The I/O LEDs IO-5 through IO-0 flash from right to left and the UnderGlow LED is breathing. 
+    - No USB connected: The I/O LEDs IO-0 through IO-5 flash from left to right and the UnderGlow LED is off.
+**/
+//********************************************************************************************
+/**
+\page InitializationBlinks Program Initialization
+<h1> Program Initialization </h1>
+    The start of program execution is indicated by the illumination of all the software-controllable board LEDs: the blue UnderGlow LED, the red user-controllable LED, and both blue COM port LEDs turn \n
+    on while the top and bottom rows of I/O LEDs (connnectors A-12 through DI-6 and IO-0 through IO-5, respectively) flash once from left to right (when viewing the board so that the connector labels \n
+    are facing upright).
+**/
+//********************************************************************************************
+/**
+\page BlinkCodes ClearCore Status Blink Codes
+<h1> Blink Code Sequencing </h1>
+    The ClearCore can provide multiple status codes using the \ref UnderGlowLed.  These codes use a pattern of strobes and blink pulses indicating error code groups and values.
+    
+<h2> Reading the Status </h2>
+    - Long Strobe: The status LED will strobe for 2.3 seconds, indicating the start of the status code sequence.
+    - Code(s): Each status code that has occurred since the last time that the processor has reset will be output.
+        - Strobes: The status LED will indicate the Code Group with a series of strobe pulses, 0.5 seconds strobing at 20Hz and 0.5 seconds off. The Code Group is the count of strobe groups.
+        - Blinks: The status LED then indicates the Code Value with a series of blinks, 0.5 seconds on and 0.5 seconds off. The Code Value is the count of blink pulses.
+        - If there are multiple codes, each strobe / blink pair will be displayed with brief pauses between them.
+    
+<h2> Decoding the Status </h2>
+<h3> Code Group 1: An output connector was overloaded </h3>
+    - Value N: Connector (N-1) was overloaded
+
+<br>
+
+<h2>Example</h2>
+4 pulses means IO-3 was overloaded
+<img src="blink_code_timing_diagram_1_4.png">
+\see \ref OutputOverload
+    
+<hr>
+
+<h3> Code Group 2: Power Supply Error </h3>
+    - Value 1: Vsupply voltage was low
+    - Value 2: Vsupply voltage was high
+    - Value 3: Offboard 5V supply was overloaded
+    
+<hr>
+
+<h3> Code Group 3: Device Error </h3>
+    - Value 1: H-Bridge error
+    - Value 2: SD card error
+    - Value 3: Ethernet error
+    - Value 4: CCIO-8 error
+    - Value 5: XBee error
+
+<br>
+    
+<h2>Example</h2>
+2 pulses indicate an SD card error
+<img src="blink_code_timing_diagram_3_2.png">
+
+<hr>
+
+<h3> Code Group 4: CCIO-8 output was overloaded </h3>
+    - Value N: Connector(s) on the Nth CCIO-8 board in the chain were overloaded
+
+**/
+//********************************************************************************************
+/**
+\page OutputOverload I/O Output Overload
+<h1> I/O Output Overload </h1>
+    Each ClearCore digital output can drive resistive or inductive loads up to 9 watts (0.375 A). If the load exceeds the output capacity, the connector detects that the output voltage is not at the \n
+    proper level and signals an overload condition.
+    
+    When an overload is detected, the connector's \ref IoLed is strobed at 10Hz while the overload condition persists. An error code will be shown on the \ref UnderGlowLed indicating that an overload \n
+    occurred on the given connector and persist until the ClearCore is reset.
+    
+\see \ref BlinkCodes
+**/
+//********************************************************************************************
+/**
+\page ConnectorFunctionality Connector functionality at a glance
+This table is a quick way to tell which connectors support which functionalities.
+
+<table>
+<caption>Connector functionality checklist</caption>
+<tr><td><th>Digital Input<th>Digital Output<sup>1</sup><th>0-10V Analog Input<th>4-20 mA Output<sup>2</sup><th>Servos or Steppers<th>Speaker Tones<th>DC Motor Drive
+<tr><td>#ConnectorIO0 <td><center>yes</center><td><center>yes</center><td><td><center>yes</center><td><td><td>
+<tr><td>#ConnectorIO1 <td><center>yes</center><td><center>yes</center><td><td><td><td><td>
+<tr><td>#ConnectorIO2 <td><center>yes</center><td><center>yes</center><td><td><td><td><td>
+<tr><td>#ConnectorIO3 <td><center>yes</center><td><center>yes</center><td><td><td><td><td>
+<tr><td>#ConnectorIO4 <td><center>yes</center><td><center>yes</center><td><td><td><td><center>yes</center><td><center>yes</center>
+<tr><td>#ConnectorIO5 <td><center>yes</center><td><center>yes</center><td><td><td><td><center>yes</center><td><center>yes</center>
+<tr><td>#ConnectorDI6 <td><center>yes</center><td><td><td><td><td><td>
+<tr><td>#ConnectorDI7 <td><center>yes</center><td><td><td><td><td><td>
+<tr><td>#ConnectorDI8 <td><center>yes</center><td><td><td><td><td><td>
+<tr><td>#ConnectorA9 <td><center>yes</center><td><td><center>yes</center><td><td><td><td>
+<tr><td>#ConnectorA10 <td><center>yes</center><td><td><center>yes</center><td><td><td><td>
+<tr><td>#ConnectorA11 <td><center>yes</center><td><td><center>yes</center><td><td><td><td>
+<tr><td>#ConnectorA12 <td><center>yes</center><td><td><center>yes</center><td><td><td><td>
+<tr><td>#ConnectorM0 <td><td><td><td><td><center>yes<sup>3</sup></center><td><td>
+<tr><td>#ConnectorM1 <td><td><td><td><td><center>yes<sup>3</sup></center><td><td>
+<tr><td>#ConnectorM2 <td><td><td><td><td><center>yes<sup>3</sup></center><td><td>
+<tr><td>#ConnectorM3 <td><td><td><td><td><center>yes<sup>3</sup></center><td><td>
+<tr><td>CCIO-8<sup>4</sup><td><center>yes</center><td><center>yes</center><td><td><td><td><td>
+</table>
+<ul>
+    <li> Note 1: All digital outputs are PWM capable (except for those on the CCIO-8 expansion board).
+    <li> Note 2: This output can also provide 0-20mA, which is less commonly used.
+    <li> Note 3: Each motor connector has 3 digital outputs (step, dir., enable) and 1 digital input.
+    <li> Note 4: There are 8 of these I/O points on the CCIO-8 expansion module.
+</ul>
+**/
+//********************************************************************************************
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/ConnectorSystem.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/ConnectorSystem.doc
new file mode 100644
index 000000000..8761e2739
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/ConnectorSystem.doc
@@ -0,0 +1,61 @@
+namespace ClearCore {
+/**
+\page ConnectorMain ClearCore Connector System
+<h1> Overview </h1>
+    The ClearCore board has several different kinds of hardware connectors that range from simple digital inputs to complex ClearPath motor connectors. To facilitate easier coding the ClearCore \n
+    library implements a Connector interface that is common to all connectors on the board. All classes representing a ClearCore hardware connector are derived, or inherit, from the common Connector \n
+    class.
+
+<h2> Inheritance and Child Classes </h2>
+    In C++ class inheritance, there is always a parent class and a child class. For the connector interface the parent class is Connector whereas all other classes, such as DigitalIn or MotorDriver, \n
+    are the children. A child class must implement the functionality of its parents, but it may also modify and extend that functionality.
+
+<h3> Shared Functionality </h3>
+    Because each child class implements the functionality of its parent all child classes have the same base set of functions and members. These functions typically perform the same actions as each \n
+    other for similar hardware connectors, but some may have different behavior. These shared functions make using groups of connectors much simpler, such as looping through an array of connectors to \n
+    call a common function.
+
+<h3> Extended Functionality </h3>
+    While all child classes share function definitions, the child implementations of those functions may not be the same. The common functions may be changed, or overriden, by child classes when extra \n
+    operations need to be performed. For instance, DigitalIn's Mode() function will slightly differ from DigitalInOut's because DigitalIn only has one valid operational mode.
+    
+    Child classes may also contain additional functions and members that other child classes do not. These functions and members perform specific actions that would not be useful in the other child \n
+    classes, such as MotorDriver's EnableRequest() function for enabling attached motors.
+
+<h2> Common Members </h2>
+    The functions and types shared between the Connector child classes provide a good base for operating hardware connectors as groups.
+
+<h3> Mode </h3>
+    - The ConnectorModes enumeration provides a set of operational modes a connector class may potentially be put in.
+    - The Mode() function may be used to read and set the current operational mode of a connector class.
+        - Attempting to set an invalid mode on a connector (like setting a DigitalIn to OUTPUT_ANALOG mode) will fail and the function will return false.
+   
+<h3> Type </h3>
+    - The ConnectorTypes enumeration provides a set of hardware connector types. These are specific to each child class and cannot be changed.
+    - The Type() function will return the type of the child class. This is useful when dealing with an array of connectors that are stored in a generic way.
+
+<h3> IsWritable </h3>
+    - This function will show whether a connector class is an input or an output.
+    - For hardware connectors that may be either an input or an output, the return of IsWritable() changes depending on which mode the connector is in.
+
+<h3> Re-initialize </h3>
+    - This function resets the connector to its state at program start-up. No settings, such as a change to the operational mode, will persist after the re-initialization.
+
+<h3> ConnectorIndex </h3>
+    - This returns the index of the connector in the ClearCore system's connector array.
+    - ConnectorIndex() is useful when accessing connectors through SysManager's ConnectorByIndex() function.
+
+<h3> State </h3>
+    - The State() functions are used to read and write to a hardware connector.
+        - For connectors that are only inputs attempting to write using State() will do nothing and the function will return false.
+    - Classes such as MotorDriver implement the State() functions but they don't do anything, thus they are hidden from most documentation.
+
+<h3> IsInHwFault </h3>
+    - This is a simple boolean return representing whether the connector is in a fault state or not.
+
+<h3> InputRegMask </h3>
+    - This function provides a bit mask of the current connector. It is useful for interacting with the InputManager when only the specific connector is needed to be looked at.
+
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Ethernet.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Ethernet.doc
new file mode 100644
index 000000000..45f51e5b0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Ethernet.doc
@@ -0,0 +1,168 @@
+namespace ClearCore {
+/**
+\page EthernetMain ClearCore Ethernet
+<h1> Overview </h1>
+    ClearCore provides fully-featured Ethernet functionality at 10 Mbps and 100 Mbps with a 10Base-T/100Base-TX Ethernet port. The ClearCore package implements LwIP's TCP/IP protocol suite and \n
+    provides a user-friendly API for TCP and UDP capabilities.
+
+<h2> Wiring and Initialization </h2>
+    - Connect the ClearCore to a router/switch using a standard ethernet RJ45 cable, or directly to another ClearCore or PC using an ethernet cross-over cable. Use the dedicated ClearCore ETHERNET \n
+    port.
+    - Make sure the router/switch or connected device is on.
+    - Verify that the Ethernet connector's LED turns on. This is a status indicator for link activity. The Ethernet LED can only indicate one of two states, off or blinking, to indicate the absence \n
+    or prescence of network activity, respectively.
+        - If the LED does not come on after connecting an RJ45 cable connected to the network the ClearCore won't be able to communicate on the network.
+    - Set up Ethernet functionality through the ClearCore EthernetManager.
+        - To configure with a static IP address, if manual configuration is required or DHCP is unavailable:
+        \code{.cpp}
+        // Specify the desired network values:
+        // ClearCore IP address
+        IpAddress ip = IpAddress(192, 168, 1, 8);
+        // Router/switch IP address
+        IpAddress gateway = IpAddress(192, 168, 1, 1);
+        // Mask to separate network vs. host addresses (required for TCP)
+        IpAddress netmask = IpAddress(255, 255, 255, 0);
+
+        // Set the network values through the EthernetManager.
+        EthernetMgr.Setup();
+        EthernetMgr.LocalIp(ip);
+        EthernetMgr.GatewayIp(gateway);
+        EthernetMgr.NetmaskIp(netmask);
+        \endcode
+        - To configure with an IP address assigned via DHCP:
+        \code{.cpp}
+        EthernetMgr.Setup();
+        bool dhcpSuccess = EthernetMgr.DhcpBegin();
+        if (dhcpSuccess) {
+            // DHCP successfully assigned an IP address.
+        }
+        \endcode
+    - To confirm that everything is working properly, once an IP address has been assigned, you should be able to communicate to the ClearCore using the Windows ping command from a PC on the same \n
+    network.
+        - Make sure that the sketch running on the ClearCore calls EthernetMgr.Refresh() in a timely manner in the loop() function so that incoming and outgoing packets will get processed. In \n
+        practical applications, this refreshing will be taken care of by the functions that send and receive packets.
+        - Connect a PC to the router/switch that the ClearCore is connected to.
+        - On that PC, open a Windows cmd shell, type "ping <ClearCore_IP_address>", and hit Enter. You should see four lines that begin with "Reply from <ClearCore_IP_address>: bytes=32", indicating \n
+        that the ClearCore is online.
+        - If instead you see "Reply from <ClearCore_IP_address>: Destination host unreachable", or if the ping otherwise fails, make sure the router/switch is on, the correct IP address was supplied \n
+        to ping, and that the ClearCore is running a sketch that called EthernetMgr.Setup(), successfully configured an IP address, and calls EthernetMgr.Refresh() at a reasonable rate.
+        
+
+<h2> Ethernet TCP </h2>
+    The TCP functionality of the ClearCore provides a Client-Server interface, allowing the ClearCore to act as either a client or a server. TCP is connection-oriented and provides built-in error \n
+    checking, guaranteed packet delivery, and delivery of packets in order. TCP is best suited for an application where reliability is more valuable than speed.
+    
+    <h3> TCP Client </h3>
+        From the Client-Server perspective, the client of a TCP connection is the device who initiates the connection.
+        - To initialize the ClearCore as a client connecting to a remote server:
+        \code{.cpp}
+        EthernetTcpClient client;
+        IpAddress serverIp = IpAddress(192, 168, 1, 78);
+        // Start a TCP connection with the server on port 8888.
+        if (client.Connect(serverIp, 8888)) {
+            // Successfully connected to the server.
+        }
+        \endcode
+        \note Ethernet functionality must be initialized before initializing TCP communications.
+        - To communicate with the connected server:
+            - Incoming TCP packets from the server are automatically buffered within the client. To process received data, the client's buffer can be read-from directly at any time by calling \n
+            EthernetTcpClient::Read().
+            - Outgoing TCP packets are automatically created and sent when using the EthernetTcpClient::Send() API. The TCP protocol of acknowledging received packets and resending lost packets is \n
+            handled automatically.
+        
+    <h3> TCP Server </h3>
+        From the Client-Server perspective, the server of a TCP connection is the device that listens for and accepts incoming connection requests. The EthernetTcpServer interface provides two distinct options for managing connected clients. Choose one or the other, but do not mix usage of EthernetTcpServer::Available() and EthernetTcpServer::Accept().
+
+<h3>Automatic Client Management (recommended)</h3>
+
+        - To obtain a reference to a connected client while leaving management of that client up to the server, use EthernetTcpServer::Available()
+	  - Each client reference is an EthernetTcpClient object. 
+	  	- Incoming TCP packets from an individual client are automatically buffered within the client. To process received data, the client's buffer can be read-from directly at any time by
+calling EthernetTcpClient::Read().
+	  	- Outgoing TCP packets to an individual client are automatically created and sent when using the EthernetTcpClient::Send() API. The TCP protocol of acknowledging received packets and
+resending lost packets is handled automatically.
+	  	- Outgoing TCP packets may be sent through the server to all currently connected clients using EthernetTcpServer::Send(). (applicable only when using the server’s automatic Client management).
+
+        \code{.cpp}
+	  // Initialize the ClearCore as a server listening for incoming client connections
+        EthernetTcpServer server = EthernetTcpServer(8888);
+        // Start listening for TCP connections on port 8888.
+        server.Begin();
+        \endcode
+
+	  \code{.cpp}
+// Obtain a reference to a connected client with incoming data                              available.
+        EthernetTcpClient client = server.Available();
+        if (client.Connected()) {
+// The server has returned a connected client with incoming data available.
+           while (client.BytesAvailable() > 0) {
+    // Send the data received from the client over a serial port.
+               ConnectorCOM0.Send(client.Read());
+           }
+        }
+        \endcode
+
+<h3>Manual Client Management</h3>
+        - To obtain a reference to a connected client and stop it from being managed by the server, use EthernetTcpServer::Accept().
+            - Each client reference is an EthernetTcpClient object.
+                - Incoming TCP packets from an individual client are automatically buffered within the client. To process received data, the client's buffer can be read-from directly at any time by \n
+                calling EthernetTcpClient::Read().
+                - Outgoing TCP packets to an individual client are automatically created and sent when using the EthernetTcpClient::Send() API.  The TCP protocol of acknowledging received packets and \n
+                resending lost packets is handled automatically.
+		    \code{.cpp}
+	  // Initialize the ClearCore as a server listening for incoming client connections
+        EthernetTcpServer server = EthernetTcpServer(8888);
+        // Start listening for TCP connections on port 8888.
+        server.Begin();
+        \endcode
+
+                \code{.cpp}
+                // The server will no longer keep track of connected clients returned by Accept().
+                EthernetTcpClient clients[4];
+                clients[0] = server.Accept();
+                if (clients[0].Connected()) {
+                    // Send a TCP packet to the client with a payload containing the string.
+                    clients[0].Send("Hello World");
+                }
+                \endcode                
+
+
+<h2> Ethernet UDP </h2>
+    UDP communications are connectionless and do not provide error checking or guaranteed delivery. The EthernetUdp interface manages a local UDP session and provides methods for sending and receiving \n
+    UDP datagrams. UDP is best suited for an application that performs its own error checking and appropriately handles packet loss or an application that requires efficiency and speed.
+
+    - UDP Initialization
+        - To initialize a local UDP session:
+        \code{.cpp}
+        // Start a local UDP session on port 23.
+        EthernetUdp Udp;
+        Udp.Begin(23);
+        \endcode
+        \note Ethernet functionality must be initialized before initializing UDP.
+        \note An EthernetUdp instance is bound to a local port upon initialization. Providing a local port number of 0 will bind to a random local port.
+    - UDP Communication
+        - To send a UDP datagram to a remote destination:
+        \code{.cpp}
+        // Form a new packet addressed to a specified remote IP address and port.
+        IpAddress remoteIp = IpAddress(192, 168, 1, 78);
+        uint16_t remotePort = 8888;
+        // Set up to send a packet to a remote IP/port.
+        Udp.Connect(remoteIp, remotePort);
+        // Write data into the payload of the outgoing packet.
+        Udp.PacketWrite("Hello World.");
+        // Send the packet to the remote destination.
+        Udp.PacketSend();
+        \endcode
+        - To process a received UDP datagram.
+        \code{.cpp}
+        // Save the newest UDP packet to be read from.
+        uint16_t packetSize = Udp.PacketParse();
+        // Read the contents of the received packet into our own variable.
+        char[packetSize] packetContents;
+        Udp.PacketRead(packetContents, packetSize);
+        \endcode
+
+**/
+//********************************************************************************************
+}
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Examples.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Examples.doc
new file mode 100644
index 000000000..747dc7581
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/Examples.doc
@@ -0,0 +1,262 @@
+namespace ClearCore {
+/**
+\page SdkExamples SDK Examples for Microchip Studio
+<h1> Overview </h1>
+These examples and a helpful Project Template will be located in your program files after installing for Microchip Studio. <br>
+C:\\Program Files (x86)\\Teknic\\ClearCore-Library x.x [where x.x is the version number]
+    
+<h2>Analog I/O Examples</h2>
+    - [Read Analog Input](@ref AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cpp)
+    - [Write Analog Current Output](@ref AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cpp)
+    
+<h2>Digital I/O Examples</h2>
+    - [Read Digital Input](@ref DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cpp)
+    - [Read Digital Input Rise/Fall](@ref DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cpp)
+    - [Write Digital Output](@ref DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cpp)
+    - [Write H-Bridge Output](@ref DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cpp)
+    - [Write PWM Output](@ref DigitalIOExamples/WritePwmOutput/WritePwmOutput.cpp)
+    - [Input Interrupts](@ref DigitalIOExamples/InputInterrupts/InputInterrupts.cpp)
+    - [Periodic Interrupt](@ref DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cpp)
+    - [Play Tone](@ref DigitalIOExamples/PlayTone/PlayTone.cpp)
+
+<h2>CCIO-8 Examples</h2>
+    - [ClearCore I/O Expansion Board](@ref CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cpp)
+    - [Read CCIO-8 Digital Input](@ref CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cpp)
+    - [Write CCIO-8 Digital Output](@ref CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cpp)
+    - [Write CCIO-8 Digital Output Pulses](@ref CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cpp)
+
+<h2>ClearCore Board Status Example</h2>
+    - [ClearCore Status Register](@ref ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cpp)
+    
+<h2>ClearPath Mode Examples</h2>
+    <h3>ClearPath-MC Series</h3>
+        - Absolute Positioning:
+            - [2 Positions Home to Switch](@ref ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cpp)
+            - [4 Positions Home to HardStop](@ref ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cpp)
+            - [16 Positions Home to HardStop](@ref ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cpp)
+            
+        - Incremental Positioning:
+            - [2 Increments Home to Switch](@ref ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cpp) 
+            - [4 Increments Home to HardStop](@ref ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cpp)
+            
+        - [Pulse Burst Positioning](@ref ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cpp)
+        - [Follow Digital Position Command, Unipolar PWM Command](@ref ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cpp)
+        - [Follow Digital Torque Command, Unipolar PWM Command](@ref ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cpp)
+        - [Follow Digital Velocity Command, Unipolar PWM Command](@ref ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cpp)
+        - [Follow Digital Velocity Command, Bipolar PWM Command w/ Variable Torque](@ref ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cpp)
+        - [Manual Velocity Control](@ref ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cpp)
+        - [Ramp Up/Down To Selected Velocity](@ref ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cpp)
+    
+    <h3>ClearPath-SD Series</h3>
+        - [SingleAxis, MovePositionAbsolute](@ref ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cpp)
+        - [SingleAxis, MovePositionRelative](@ref ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cpp)
+        - [SingleAxis, MoveVelocity](@ref ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cpp)
+        - [Dual Axis, Synchronized Motion](@ref ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cpp)
+        - [Homing, User Seeks Home](@ref ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cpp)
+        - [Motor Status Register](@ref ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cpp)
+        
+    <h3>High-Level Feedback (HLFB)</h3>
+        - [ASG With Measured Torque](@ref ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cpp)
+        - [Speed Output](@ref ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cpp)
+
+<h2>Encoder Input Example</h2>
+    - [Follow Encoder](@ref EncoderInputExamples/FollowEncoder/FollowEncoder.cpp)
+
+<h2>Ethernet Example</h2>
+    - [UDP Hello World](@ref EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cpp)
+    
+<h2>Serial Communication Examples</h2>
+    - [Serial Print](@ref SerialCommExamples/SerialPrint/SerialPrint.cpp)
+    - [Read Serial Input](@ref SerialCommExamples/ReadSerialInput/ReadSerialInput.cpp)
+    - [SPI COM-Port Initialization](@ref SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cpp)
+    - [SPI Serial Display](@ref SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cpp)
+    - [TTL Serial Display](@ref SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cpp)
+    
+<h2>Step And Direction Example (non-ClearPath)</h2>
+    - [Step And Direction](@ref StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirection.cpp)
+**/
+
+/**
+    \example AnalogIOExamples/ReadAnalogInput/ReadAnalogInput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example AnalogIOExamples/WriteAnalogCurrentOutput/WriteAnalogCurrentOutput.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example DigitalIOExamples/ReadDigitalInput/ReadDigitalInput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/ReadDigitalInputRiseFall/ReadDigitalInputRiseFall.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/WriteDigitalOutput/WriteDigitalOutput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/WriteHBridgeOutput/WriteHBridgeOutput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/WritePwmOutput/WritePwmOutput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/InputInterrupts/InputInterrupts.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/PeriodicInterrupt/PeriodicInterrupt.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example DigitalIOExamples/PlayTone/PlayTone.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example CCIO8Examples/ClearCoreIOExpansionBoard/ClearCoreIOExpansionBoard.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example CCIO8Examples/ReadCCIODigitalInput/ReadCCIODigitalInput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example CCIO8Examples/WriteCCIODigitalOutput/WriteCCIODigitalOutput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example CCIO8Examples/WriteCCIODigitalOutputPulses/WriteCCIODigitalOutputPulses.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example ClearCoreBoardStatus/ClearCoreStatusRegister/ClearCoreStatusRegister.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/Abs2PositionsHomeToSwitch/Abs2PositionsHomeToSwitch.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/Abs4PositionsHomeToHardStop/Abs4PositionsHomeToHardStop.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/Abs16PositionsHomeToHardStop/Abs16PositionsHomeToHardStop.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/Move2IncrementsHomeToSwitch/Move2IncrementsHomeToSwitch.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/Move4IncrementsHomeToHardStop/Move4IncrementsHomeToHardStop.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalPosition/FollowDigitalPosition.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalTorque/FollowDigitalTorque.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocity/FollowDigitalVelocity.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/FollowDigitalVelocityWithVariableTorque/FollowDigitalVelocityWithVariableTorque.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/ManualVelocity/ManualVelocity.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/PulseBurstPositioning/PulseBurstPositioning.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-MC_Series/RampUpDownToSelectedVelocity/RampUpDownToSelectedVelocity.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example ClearPathModeExamples/ClearPath-SD_Series/MovePositionAbsolute/MovePositionAbsolute.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-SD_Series/MovePositionRelative/MovePositionRelative.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-SD_Series/MoveVelocity/MoveVelocity.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-SD_Series/DualAxisSynchronized/DualAxisSynchronized.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-SD_Series/UserSeeksHome/UserSeeksHome.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/ClearPath-SD_Series/MotorStatusRegister/MotorStatusRegister.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example ClearPathModeExamples/High-Level_Feedback_HLFB/AsgWithMeasuredTorque/AsgWithMeasuredTorque.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example ClearPathModeExamples/High-Level_Feedback_HLFB/SpeedOutput/SpeedOutput.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example EncoderInputExamples/FollowEncoder/FollowEncoder.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example EthernetExamples/EthernetUdpHelloWorld/EthernetUdpHelloWorld.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example SerialCommExamples/SerialPrint/SerialPrint.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example SerialCommExamples/ReadSerialInput/ReadSerialInput.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example SerialCommExamples/SpiComPortInitialization/SpiComPortInitialization.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example SerialCommExamples/SpiSerialDisplay/SpiSerialDisplay.cpp
+    Return to \ref SdkExamples
+**/
+/**
+    \example SerialCommExamples/TtlSerialDisplay/TtlSerialDisplay.cpp
+    Return to \ref SdkExamples
+**/
+
+/**
+    \example StepAndDirectionExamplesNonClearPath/StepAndDirectionNonClearPath/StepAndDirection.cpp
+    Return to \ref SdkExamples
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/InstallationInstructions.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/InstallationInstructions.doc
new file mode 100644
index 000000000..7773b20e4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/InstallationInstructions.doc
@@ -0,0 +1,67 @@
+namespace ClearCore {
+/**
+\page InstallationInstructions Installation and Update Instructions
+<h1> Automatic Install </h1>
+    Download and run the appropriate installer for your development environment below to automatically install all ClearCore libraries:
+    <ul>
+        <li> Microchip/Atmel Studio<br>
+        https://www.teknic.com/files/downloads/ClearCore_Atmel_Installer.zip
+
+        <li> Arduino<br>
+        https://www.teknic.com/files/downloads/ClearCore_Arduino_Wrapper_Installer.zip
+    </ul>
+  
+<h1> Manual Install </h1>
+    If the installers above cannot be run, or if a manual installation is preferred, follow the appropriate instructions below for your development environment:
+    <ul>
+        <li> Microchip/Atmel Studio<br>
+        https://www.teknic.com/files/downloads/manual_install_instructions_atmel.pdf
+
+        <li> Arduino<br>
+        https://www.teknic.com/files/downloads/manual_install_instructions_arduino.pdf
+    </ul>
+<h1> Updating Libraries </h1>
+    To check which release of the ClearCore software library is being used, and/or to update to a different release follow the instructions below:
+    
+<h2> Microchip/Atmel Studio </h2>
+    <i>Checking your current version number</i>
+    <ol>
+        <li> The library version can be found by checking this folder name:<br>
+        C:\\Program Files (x86)\\Teknic\\ClearCore-Library <b>x.x</b>
+        where "x.x" is the version number.
+    </ol>
+    
+    <i>Updating the version</i>
+    <ol start="2">
+        <li> The latest released version can be found on Teknic's ClearCore GitHub repository:<br>
+        https://github.com/Teknic-Inc/ClearCore-library/releases
+        
+        <li> Under the most recent release, download the Source Code .zip file.<br>
+        <img src="assets.jpg">
+        
+        <li> Extract this .zip file to this location:<br>
+        C:\\Program Files (x86)\\Teknic
+        
+        <li> The newer version will now be included in your program files. Note: any older version is not removed by this process.<br>
+        <img src="installed_versions.jpg">
+    </ol>
+    
+<h2> Arduino </h2>
+    <i>Checking your current version number</i>
+    <ol>
+        <li> Open the Arudino IDE and navigate to Tools > Board > Boards Manager...
+        <li> In the Boards Manager search bar, search for "ClearCore". The library version number will be listed here.<br>
+        <img src="boards_manager_installed.png">
+    </ol>
+    <i>Updating the version</i>
+     <ol start="3">
+        <li> If newer versions are available, the "Update" button will be visible. Click "Update".<br>
+        <img src="boards_manager_update.png"><br>
+        
+        When the most recent library version is installed, older versions of the library may be selectable. It is only recommended to use older versions<br>
+        if your ClearCore application code was originally developed using an older version. Some newer features may not be usable with earlier versions.<br>
+        <img src="boards_manager_select_version.png"><br>
+    </ol>
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/MotorDriver.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/MotorDriver.doc
new file mode 100644
index 000000000..f44aa5eed
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/MotorDriver.doc
@@ -0,0 +1,104 @@
+namespace ClearCore {
+/**
+\page MotorDriverMain Motor Control System
+<h1> Overview </h1>
+    For applications that require the operation of a motor, ClearCore offers a suite of options to control up to four motors simultaneously. The MotorManager class handles the configuration of the \n
+    physical motor connectors (M-0 through M-3) on the ClearCore board. In code, these motor connectors are represented and controlled by instances of the MotorDriver class (#ConnectorM0 through \n
+    #ConnectorM3).
+    
+    The MotorDriver class is designed to facilitate and fully exercise all the features of a Teknic ClearPath motor, however generic stepper motor drives may be used as well. For simplicity's sake \n
+    this document will assume a ClearPath motor is being used when describing the features of the MotorDriver class.
+    
+<h2> Wiring and Initialization </h2>
+    - Before beginning to use the ClearCore, set up and connect a ClearPath motor to a host PC. Then, using Teknic's MSP software, configure and tune the ClearPath to the desired specifications. For \n
+    more information on these steps refer to the manual for your ClearPath motor found <a href="https://www.teknic.com/downloads/" >here</a>.
+    - Connect the ClearPath to one of the ClearCore's motor connectors (M-0, M-1, M-2, or M-3) with an 8-pin Molex Mini-fit control cable.
+        - Any of the four connectors may be used in any order. For example, M-2 may be used without occupying M-0 and M-1.
+    - Note the operational mode and the HLFB mode of the ClearPath in MSP.
+
+<h2> Motor Manager </h2>
+    The MotorManager class controls the configuration of the actual motor connectors, not the MotorDriver objects associated with the connectors. The manager has APIs for setting the controller mode of\n
+    the connectors as well as the clock rate of the connectors.
+
+<h3> Motor Input Clocking </h3>
+    - The MotorManager sets the input clock rate for all motor connectors on the ClearCore; connectors' clock rates may not be set individually.
+        \code{.cpp}
+        // Set the input clocking rate on all motor connectors
+        MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_NORMAL);
+        \endcode
+    - The clock rates may be set to \ref MotorManager#CLOCK_RATE_LOW "LOW", \ref MotorManager#CLOCK_RATE_NORMAL "NORMAL", or \ref MotorManager#CLOCK_RATE_HIGH "HIGH":
+        - LOW is 100 kHz
+        - NORMAL is 500 kHz
+        - HIGH is 2 MHz
+            - Note that a HIGH clock rate may induce errors with a ClearPath motor.
+
+<h3> Connector Modes </h3>
+    - The MotorManager class sets the motor controller mode in pairs. The controller mode may be set on M-0 and M-1, M-2 and M-3, or all 4 connectors at once. Modes may not be set on individual connectors.
+        \code{.cpp}
+        // Set the M-2 and M-3 motor connectors into step and direction mode.
+        MotorMgr.MotorModeSet(MotorManager::MOTOR_M2M3, Connector::CPM_MODE_STEP_AND_DIR);
+        \endcode
+    - There are four controller modes that correspond to various ClearPath operating modes:
+        - \ref Connector#CPM_MODE_STEP_AND_DIR "CPM_MODE_STEP_AND_DIR" - For generic stepper motor drives or a ClearPath in Step & Direction mode
+        - \ref Connector#CPM_MODE_A_DIRECT_B_DIRECT "CPM_MODE_A_DIRECT_B_DIRECT" - Compatible with ClearPath modes that require direct control of the A and B motor input signals (e.g., Incremental \n
+        Distance).
+        - \ref Connector#CPM_MODE_A_DIRECT_B_PWM "CPM_MODE_A_DIRECT_B_PWM" - Compatible with operational modes where motor input A is controlled by the user directly and motor input B is controlled \n
+        with a PWM signal (e.g., Follow Digital Torque).
+        - \ref Connector#CPM_MODE_A_PWM_B_PWM "CPM_MODE_A_PWM_B_PWM" - Compatible with Follow Digital Velocity: Bipolar PWM Command with Variable Torque operational mode where both motor inputs A and \n
+        B are controlled with PWM signals.
+
+<h2> Motor Driver </h2>
+    The MotorDriver class contains interfaces for controlling and communicating with a motor attached to a ClearCore motor connector. There are APIs provided to manipulate all the input lines of a \n
+    ClearPath as well as functions to interact with HLFB. The MotorDriver class also contains functions for motion generation by inheriting from the StepGenerator class. More information on the \n
+    MotorDriver's motion generation features may be found on the \ref MoveGen page.
+
+<h3> Motor Inputs </h3>
+    - The MotorDriver class provides interfaces for all of ClearPath's motor inputs: A, B, and Enable.
+    - The status of the motor's enable line may be checked and set by the \ref MotorDriver#EnableRequest() "EnableRequest" function.
+        \code{.cpp}
+        if (ConnectorM0.EnableRequest()) {
+            // If the motor is currently enabled, disable it.
+            ConnectorM0.EnableRequest(false);
+        }
+        \endcode
+    - For ClearPath modes that require a short off-on pulse of the enable line, such as to trigger a move, use the \ref MotorDriver#EnableTriggerPulse "EnableTriggerPulse" function.
+        \code{.cpp}
+        // Begin a train of five 100ms pulses on M-0's enable that block further 
+        // code execution until the pulse train is finished.
+        ConnectorM0.EnableTriggerPulse(100, true, 5);
+        \endcode
+    - ClearPath inputs A and B may be controlled as boolean values using the \ref MotorDriver#MotorInAState() "MotorInAState" and \ref MotorDriver#MotorInBState() "MotorInBState" functions. The \n
+    ClearPath motor inputs may also have a PWM wave sent to them by the ClearCore using the \ref MotorDriver#MotorInADuty() "MotorInADuty" and \ref MotorDriver#MotorInBDuty() "MotorInBDuty" functions\n
+    (when in the correct connector modes).
+        \code{.cpp}
+        // Set the motor connectors to use a PWM signal on A and B.
+        MotorMgr.MotorModeSet(MotorManager::MOTOR_M2M3, Connector::CPM_MODE_A_PWM_B_PWM);
+        // Begin a 50% duty cycle on M-2's Input B
+        ConnectorM2.MotorInBDuty(50);
+        \endcode
+    - For generic stepper motor drives that may be controlled by inverted signals all of the MotorDriver's motor input signals may be inverted. 
+        \code{.cpp}
+        // Invert M-2's enable signal
+        ConnectorM2.PolarityInvertSDEnable(true);
+        \endcode
+   
+<h3> HLFB </h3>
+    A key feature of ClearPath is the High-Level Feedback (HLFB) that can be output by the ClearPath to report on various motor statuses. For more information on HLFB you may reference the ClearPath \n
+    manual for your motor. The manuals may be found <a href="https://www.teknic.com/files/downloads/clearpath_user_manual.pdf">here</a> and <a href="https://www.teknic.com/files/downloads/ac_clearpath-mc-sd_manual.pdf">here</a> for DC- and AC-input ClearPaths, respectively.
+    - The MotorDriver class contains several functions and configuration options so HLFB can be fully utilized in motor control applications.
+    - \ref MotorDriver#HlfbState() "HlfbState" may return as \ref MotorDriver#HLFB_ASSERTED "ASSERTED", \ref MotorDriver#HLFB_DEASSERTED "DEASSERTED", or that a PWM signal has been measured. \n
+    \ref MotorDriver#HLFB_HAS_MEASUREMENT "HLFB_HAS_MEASUREMENT" will only be returned when there is an active PWM signal or there has been a PWM since the last read of \ref MotorDriver#HlfbState() "HlfbState".
+        \code{.cpp}
+        if (ConnectorM0.HlfbState() == MotorDriver::HLFB_HAS_MEASUREMENT) {
+            // If there is a PWM value for the HLFB, read and save the value.
+            float hlfbDuty = ConnectorM0.HlfbDuty();
+        }
+        \endcode
+    - The MotorDriver's HLFB interface can be set to three different modes that correspond to various HLFB modes on your ClearPath motor:
+        - \ref MotorDriver#HLFB_MODE_STATIC "HLFB_MODE_STATIC" - For use with ClearPath HLFB modes that only read as asserted or deasserted, such as ServoOn.
+        - \ref MotorDriver#HLFB_MODE_HAS_PWM "HLFB_MODE_HAS_PWM" - For modes where the HLFB signal may have a 0-100% PWM component, such as Speed Output.
+        - \ref MotorDriver#HLFB_MODE_HAS_BIPOLAR_PWM "HLFB_MODE_HAS_BIPOLAR_PWM" - For modes where the HLFB signal may have a -100 to 100% PWM component, such as ASG-Position with Measured Torque.
+
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/MoveGen.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/MoveGen.doc
new file mode 100644
index 000000000..ae7b6f3f1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/MoveGen.doc
@@ -0,0 +1,85 @@
+namespace ClearCore {
+/**
+\page MoveGen Step and Direction Control
+<h1> Overview </h1>
+    For applications that require motion control of a connected motor ClearCore provides a motion generation class called StepGenerator. StepGenerator is one of the parent classes of MotorDriver. \n
+    This allows all motor configuration functions and motion generation functions to be accessed by the same MotorDriver object.
+    
+    The StepGenerator class is designed to facilitate features of a Teknic ClearPath motor, however generic stepper motor drives may be used as well. For simplicity's sake this document will assume a \n
+    ClearPath motor is being used when describing the features of the StepGenerator class.
+    
+<h2> Wiring and Initialization </h2>
+    - Before beginning to use the ClearCore, set up and connect a ClearPath motor to a host PC. Then, using Teknic's MSP software, configure and tune the ClearPath to the desired specifications. For \n
+    more information on these steps refer to the manual for your ClearPath motor found <a href="https://www.teknic.com/downloads/" >here</a>.
+    - Using MSP, set the ClearPath's mode to Step and Direction. The StepGenerator will not function correctly if the ClearPath is in another operational mode.
+    - Attach the ClearPath to a motor connector, M-0, M-1, M-2, or M-3, on the ClearCore using the blue 8-pin data cable (Teknic P/N CPM-CABLE-CTRL-MM660).
+        - Any of the four connectors may be used in any order. For example, M-2 may be used without occupying M-0 and M-1. 
+    - Using the ClearCore's MotorManager, set the motor connector into Connector#CPM_MODE_STEP_AND_DIR mode using the MotorManager#MotorModeSet() function. The StepGenerator will not function if the \n
+    connector is in another mode.
+        - The MotorModeSet() function sets a pair of motor connectors into the specified mode. Choose the pair that includes the connector you'd like to use. The pairs are M-0/M-1 and M-2/M-3.
+
+<h2> Motion Parameters </h2>
+    The StepGenerator generates a move profile using pre-defined motion parameters set by the user. These parameters may be changed "on the fly"; newly commanded moves will immediately \n interrupt any currently active move.
+    An easy way to check the move's state, provided by StepGenerator, is by polling the StepGenerator#StepsComplete() function. This \n
+    will return a boolean value representing whether the StepGenerator is outputting steps. Note that depending on your mechanics the motor shaft may still be moving even if the value is false.
+
+<h3> Position Reference </h3>
+    - The StepGenerator's position reference may be read or set directly through code. 
+        \code{.cpp}
+        if (ConnectorM0.PositionRefCommanded() > 50000) {
+            // If the motor's position is high enough, reset the position to 0
+            ConnectorM0.PositionRefSet(0);
+        }
+        \endcode
+    - The position reference resets to zero at the beginning of code execution. It WILL NOT save between board resets.
+    - The position reference is entirely internal to the ClearCore. The StepGenerator's position reference will not reflect a ClearPath's own shaft position as displayed in the MSP software.
+
+<h3> Velocity and Acceleration </h3>
+    - Maximum velocity and acceleration values may be set to give the desired motion profile (in units of step pulses per second and step pulses per second<sup>2</sup>, respectively).
+        \code{.cpp}
+        ConnectorM0.VelMax(500);
+        ConnectorM0.AccelMax(5000);
+        \endcode
+    - Setting a velocity limit using StepGenerator#VelMax() will not limit the allowable velocities when commanding a velocity move using StepGenerator#MoveVelocity().
+
+<h2> Motion Commands </h2>
+    The StepGenerator class provides movement functions which can have various behaviors depending on the pre-defined motion parameters and the parameters passed into the functions. 
+    
+    Regardless of which move command is issued, they may both be stopped by calling the StepGenerator#MoveStopAbrupt() function.
+
+<h3> Positional Move </h3>
+    - Generates a triangle movement profile that obeys the set maximum velocity and acceleration limits.
+    - The function returns the movement success as a boolean value. The move will be rejected if the commanded position reference would result \n
+    in no motion or if an alert is present in the motor's Alert Register.
+    - The StepGenerator#Move() function by default commands a relative move.
+        \code{.cpp}
+        // Move 500 step pulses in the positive direction from the current position reference (ie 1250 -> 1750)
+        ConnectorM0.Move(500);
+        \endcode
+    - Setting the <em>moveTarget</em> parameter to <code>MOVE_TARGET_ABSOLUTE</code> will command a move to the (passed-in) absolute position reference.
+        \code{.cpp}
+        // Move the motor from its current position reference to -2500 (ie 850 -> -2500)
+        ConnectorM0.Move(-2500, StepGenerator::MOVE_TARGET_ABSOLUTE);
+        \endcode
+   
+<h3> Velocity Move </h3>
+    - Begins a continuous move at the specified velocity using the pre-defined max acceleration.
+    - Calling StepGenerator#MoveVelocity() will overwrite any currently active positional move.
+    - The function returns the movement success as a boolean value. The move will be rejected if the commanded position reference would result \n
+    in no motion or if an alert is present in the motor's Alert Register.
+        \code{.cpp}
+        // Move the motor 50000 step pulses
+        ConnectorM0.Move(50000);
+        // This will be rejected
+        ConnectorM0.MoveVelocity(10000);
+        \endcode
+    - Commanding a velocity move during another velocity move will cause the first move to smoothly accelerate/decelerate to the new velocity.
+        \code{.cpp}
+        // Move the motor at 10000 step pulses/second
+        ConnectorM0.MoveVelocity(10000);
+        // This will ramp up the speed to 15000 step pulses/second.
+        ConnectorM0.MoveVelocity(15000);
+        \endcode
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/SerialDriver.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/SerialDriver.doc
new file mode 100644
index 000000000..606bda54e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/SerialDriver.doc
@@ -0,0 +1,116 @@
+namespace ClearCore {
+/**
+\page SerialDriverMain SerialDriver COM Ports
+<h1> Overview </h1>
+    For applications that require sending or receiving data over a serial port ClearCore provides two COM ports (COM-0 and COM-1). The COM ports may be interfaced-with using the SerialDriver class.\n 
+    In code, these connectors are represented by ConnectorCOM0 and ConnectorCOM1.
+    
+    For UART communications the SerialDrivers may have their operational mode configured to facilitate either TTL or RS-232 wiring schemes. For SPI communications there is an SPI mode. The SerialDriver\n 
+    connectors also have an auxiliary mode called CCIO. This mode is used to connect to the ClearCore I/O Expansion Board (CCIO-8) which provides eight additional digital I/O points.
+    
+<h2> Wiring and Initialization </h2>
+    - See the <a href="www.teknic.com/files/downloads/clearcore_system_diagram.pdf#page=4">ClearCore System Diagram</a> for details on wiring COM-0 or COM-1 to a UART device, SPI device, or RS-232 DCE/Modem or DTE/Host.
+    - Initialize the serial port into the correct mode by calling the \ref SerialDriver#Mode() function. See below for examples on setting specific modes.
+    
+<h2> RS-232/TTL Modes </h2>
+    RS-232 and TTL (UART) modes use one wire (Rx) for receiving and another wire (Tx) for transmitting serial data asynchronously at a pre-determined baud rate. These modes are identical except that\n 
+    the signals used are inverted. Data frames are signaled by the use of start and stop bits of opposite polarity. The number of stop bits in a data frame is 1 by default, but may be set to 2. \n
+    Transmission parity may also be configured, but is turned off by default. For each mode, flow control may optionally be enabled to make use of the RTS and CTS lines.
+    
+    \code{.cpp}
+    // Configure COM-1 for TTL mode.
+    ConnectorCOM1.Mode(Connector::TTL);
+    // Set the data baud rate.
+    ConnectorCOM1.Speed(9600);
+    // Open the serial port to enable data transmission.
+    ConnectorCOM1.PortOpen();
+    \endcode
+    
+    \code{.cpp}
+    // Configure COM-0 for RS-232 mode.
+    ConnectorCOM0.Mode(Connector::RS232);
+    // Set the data baud rate.
+    ConnectorCOM0.Speed(115200);
+    // (Optional) Set the data frame parity.
+    ConnectorCOM0.Parity(SerialBase::PARITY_O);
+    // (Optional) Set each data frame to use 2 stop bits.
+    ConnectorCOM0.StopBits(2);
+    // (Optional) Enable flow control.
+    ConnectorCOM0.FlowControl(true);
+    // Open the serial port to enable data transmission.
+    ConnectorCOM0.PortOpen();
+    \endcode
+    
+    Once the port is open use Send() to output characters or numeric data to the serial port. Use SendLine() to send data appended with carriage return and newline characters.
+    
+    \code{.cpp}
+    // Output some data to COM-0.
+    ConnectorCOM0.Send("Hello, ");
+    ConnectorCOM0.SendLine("world!");
+    \endcode
+    
+    To halt serial communications close the port using the \ref SerialDriver#PortClose() function. Once the port is closed data will no longer be received by or transmitted from the serial port. \n
+    The port will only start receiving input again when it is re-opened.
+    
+    \code{.cpp}
+    // Close COM-0 to end serial communications.
+    ConnectorCOM0.PortClose();
+    \endcode
+
+<h2> SPI Mode </h2>
+    SPI (Serial Peripheral Interface) is a synchronous data transfer protocol; besides lines for transmitting and receiving data there is also a dedicated clock (SCK) to synchronize transfers. With \n
+    the ClearCore acting as an SPI master device the MOSI (Master Out, Slave In) line is analogous to the Tx signal, while the MISO (Master In, Slave Out) line is analogous to the Rx signal in \n
+    RS-232/TTL modes. As in RS-232/TTL modes, the speed of data transfers is set by the Speed() function. The difference is that in SPI there are no start or stop bits since data transfer is \n
+    synchronized using the clock signal. The polarity of the SPI clock can be configured to be idle low (default) or idle high. The SPI clock's phase may be configured so that data is sampled on a \n
+    falling edge and shifted out on a rising edge (default) or vice versa.
+    
+    \code{.cpp}
+    // Configure COM-0 for SPI mode.
+    ConnectorCOM0.Mode(Connector::SPI);
+    // Set the clock frequency / data transfer rate.
+    ConnectorCOM0.Speed(9600);
+    // Set the SPI clock polarity and phase to match the target device.
+    ConnectorCOM0.SpiClock(SerialDriver::SCK_HIGH, SerialDriver::LEAD_SAMPLE);
+    // Open the serial port to enable data transmission.
+    ConnectorCOM0.PortOpen();
+    \endcode
+    
+    Toggle the Slave Select line to send to or receive data from the connected SPI device.
+    \code{.cpp}
+    // Assert the Slave Select line to begin data transfer.
+    ConnectorCOM0.SpiSsMode(SerialDriver::LINE_ON);
+    // Receive up to 100 bytes of data from the connected SPI device.
+    uint8_t received[100] = {0};
+    ConnectorCOM0.SpiTransferData(nullptr, received, 100);
+    // De-assert the Slave Select line to end data transfer.
+    ConnectorCOM0.SpiSsMode(SerialDriver::LINE_OFF);
+    \endcode
+    
+    To halt serial communications close the port using the \ref SerialDriver#PortClose() function. Once the port is closed, data will no longer be received by or transmitted from the serial port. \n
+    The port will only start receiving input again when it is re-opened.
+
+    \code{.cpp}
+    // Close COM-0 to end serial communications.
+    ConnectorCOM0.PortClose();
+    \endcode
+   
+<h2> CCIO-8 Mode </h2>
+    Both SerialDriver ports may be configured for communications with up to eight ClearCore I/O Expansion Boards (CCIO-8). The operations of the attached CCIO-8 boards will be controlled by \n
+    ClearCore's CcioBoardManager, but the initial port setup is controlled by the SerialDriver functions.
+    
+    \code{.cpp}
+    // Set the mode of COM-0 to control the attached CCIO-8 boards.
+    ConnectorCOM0.Mode(Connector::CCIO);
+    // Open the serial port in CCIO-8 mode.
+    ConnectorCOM0.PortOpen();
+    \endcode
+    
+    The CcioBoardManager controls closing down of the CCIO-8 link and its associated serial port.
+    \code{.cpp}
+    // Close down the CCIO-8 link when we're done.
+    CcioMgr.LinkClose();
+    \endcode
+
+**/
+//********************************************************************************************
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/UsbDriver.doc b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/UsbDriver.doc
new file mode 100644
index 000000000..365f8b5b4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/UsbDriver.doc
@@ -0,0 +1,94 @@
+#include "ClearCore.h";
+namespace ClearCore {
+
+//********************************************************************************************
+/**
+\page UsbMain ClearCore USB Port
+<h1> Overview </h1>
+    The USB port on the ClearCore interfaces directly with the USB native support of the ATSAMEN19A processor. 
+    
+    This configuration removes the need for a seperate USB serial port chip and provides versatility in how the device is presented to the USB host computer. It also means that since the main processor is providing the USB support, the USB device will go away and come back as the ClearCore is powered down or reset. Since the port goes away during resets, applications that interface with the USB port should watch for port removals to avoid holding open a stale instance of the COM port.
+
+<h2> Windows Drivers </h2>
+    Windows drivers for the ClearCore USB port are downloadable from http://www.teknic.com/downloads. Windows 10 users are not required to install the driver, but it is helpful so that the ClearCore USB device appears as "Teknic ClearCore (COMxx)" instead of "USB Serial Device (COMxx)" in Device Manager.
+    
+<h2> Application Operation </h2>
+    During application operation, the USB port is presented as a serial device. Windows users will find the device listed in the Ports (COM & LPT) section of Device Manager. 
+    
+    From the ClearCore application, use the \ref ConnectorUsb object to interact with the USB port serial device.
+    
+     \code{.cpp}
+     // Open the USB serial port on the device side
+     ConnectorUsb.PortOpen();
+     // Wait for the host to open the USB serial port
+     while (!ConnectorUsb) {
+         continue;
+     }
+     ConnectorUsb.SendLine("Serial is now connected and host is listening.");
+     \endcode
+    
+<h2> Bootloader Operation </h2>
+    ClearCore ships with a UF2 bootloader installed. During bootloader operation, the USB port is presented as a serial device, HID device and a Mass Storage device. This allows the device to be reprogrammed in a variety of methods that only require a USB cable.
+    
+    \note The Application and Bootloader USB devices enumerate as different product IDs, and thus will show up as different COM ports. This allows the operation mode to be clearly identified and use different capabilities based on the mode.
+    \note As the ClearCore switches between the application COM port and the bootloader COM port, make sure you have the proper port selected.
+    
+    See \ref BootloaderMain for more details on the bootloader operation and flashing firmware.
+    
+
+**/
+//********************************************************************************************
+/**
+\page BootloaderMain UF2 Bootloader
+<h1> Overview </h1>
+    A bootloader is a small piece of code that allows users to reprogram the application code within that device. ClearCore ships with a UF2 bootloader programmed on the processor. This bootloader allows programming over the USB Serial Port, as well as UF2 format firmware images to/from a USB mass storage drive. The bootloader resides at memory locations 0x0000-0x4000 and is protected from being cleared or overwritten during device programming operations. When compiling and loading your application, the user application should begin at address 0x4000.
+    
+<h2> Entering the Bootloader </h2>
+    The bootloader can be entered several ways.
+    - Double click the reset button on the ClearCore
+    - Open and close the USB Serial Port at 1200 baud
+    - Call SysManager::ResetBoard with the SysManager::RESET_TO_BOOTLOADER argument
+    
+    Upon entering bootloader mode the LEDs for I/O-0 through I/O-5 will begin blinking in increasing order.
+    Once the USB cable is plugged into a host device, the LEDs for I/O-0 through I/O-5 will change to blinking in descending order and the underglow LEDs will start slowly fading in and out.
+    As a program is loaded by the bootloader, the underglow LEDs will toggle on and off as the flash operation progresses.
+    
+    The bootloader can be exited by hitting the reset button on the ClearCore.
+    
+    \note If there is not a valid program loaded in memory starting at address 0x4000, the ClearCore will stay in bootloader mode.
+    
+<h2> Loading a program </h2>
+    <h3> Using BOSSA </h3>
+    BOSSA is a flash programming utility for the processor family used in the ClearCore. BOSSA provides both UI and command line based interfaces which perform the flash operation and verify the contents of program memory over the USB Serial Port.
+    
+    To program the ClearCore using the UI based BOSSA.exe:
+    - Select the COM port for the ClearCore device while the booloader is running.
+    - Select the compiled *.bin file that you would like to load
+    - Select "Erase all" in the "Write Options" section
+    - Enter 0x4000 as the "Flash Offset"
+    - Click the "Write" button to program the ClearCore
+    - Hit the reset button or power cycle the ClearCore to run your application
+    
+    BOSSA can also extract a binary file with the current contents of program memory or compary the memory against a given binary file.
+    
+    See http://www.shumatech.com/web/products/bossa for more information and to download.
+    
+    <h3> Using the Mass Storage Device </h3>
+    When the ClearCore is running in the bootloader, you should see a USB disk drive labeled CLEAR_BOOT on your host computer.
+    In that drive should be three files:
+    - CURRENT.UF2 - the current contents of program memory
+    - INDEX.HTM - A link to the teknic webpage to learn more about ClearCore
+    - INFO_UF2.TXT - UF2 bootloader version information
+    
+    Note that the format of the program memory image is in the UF2 format. UF2 is a file format developed by Microsoft for flashing microcontrollers. Included in the ClearCore tools is a Windows program (uf2-builder.exe) that will create a *.UF2 file from the compiled *.bin file that is generated when you compile your application.
+    
+    To program the ClearCore using the Mass Storage Device:
+    - Generate a UF2 file of the image you want to load
+    - Copy that UF2 file into the CLEAR_BOOT drive
+    
+    The ClearCore will automatically reset after the flash operation completes and begin executing the newly loaded program.
+    
+    See https://github.com/Microsoft/uf2 for more information on the UF2 format and UF2 utilities.
+**/
+//********************************************************************************************
+}
\ No newline at end of file
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new file mode 100644
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diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/timing_diagram_wavedrom_code.txt b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/timing_diagram_wavedrom_code.txt
new file mode 100644
index 000000000..9b9d36100
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc-doc/timing_diagram_wavedrom_code.txt
@@ -0,0 +1,51 @@
+/* Source WaveDrom code for ClearCore blink code timing diagrams */
+
+/* Blink code 3-2: SD card error */
+
+{signal: [
+  {name:'Blink code region', 
+   wave: 'x.3...x4.....x5...x.3...x4.....x5...x', 
+   data: 'start group code start group code ' },
+  
+  {name:'Underglow state',
+   wave: '0.6...0606060.6060..6...0606060.6060.', 
+   data: [['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on'],
+          ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on']]},
+  
+  {name:'Duration (s)',     
+   wave: '2.2...22.....22...2.2...22.....22...2', 
+   data: '1 2.3 0.5 3 0.5 2 1 2.3 0.5 3 0.5 2 ' }
+],
+ head:{
+   text:'Blink code timing diagram',
+ },
+ foot:{
+   text:'Blink code 3-2: SD card error'
+ }
+}
+
+
+/* Blink code 1-4: I0-3 was overloaded */
+
+{signal: [
+  {name:'Blink code region', 
+   wave: 'x.3...x4.x5.......x.3...x4.x5.......x', 
+   data: 'start group code start group code ' },
+  
+  {name:'Underglow state',
+   wave: '0.6...060.60606060..6...060.60606060.', 
+   data: [['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on'],
+          ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'strobing'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on'], ['tspan', {class:'h6'}, 'on']] },
+
+  {name:'Duration (s)',     
+   wave: '2.2...22.22.......2.2...22.22.......2', 
+   data: '1 2.3 0.5 1 0.5 4 1 2.3 0.5 1 0.5 4 ' }
+],
+ head:{
+   text:'Blink code timing diagram',
+ },
+ foot:{
+   text:'Blink code 1-4: IO-3 was overloaded'
+ }
+}
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/AdcManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/AdcManager.h
new file mode 100644
index 000000000..708ed0923
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/AdcManager.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file AdcManager.h
+    \brief ADC Peripheral Manager for the ClearCore Board
+
+    This class manages the ADC conversions on the Teknic ClearCore.
+**/
+
+#ifndef __ADCMANAGER_H__
+#define __ADCMANAGER_H__
+
+#include <stdint.h>
+#include "IirFilter.h"
+
+namespace ClearCore {
+
+/**
+    \brief ADC Peripheral Manager for the ClearCore Board
+
+    This class manages the ADC peripheral on the Teknic ClearCore.
+
+    Utilizes DMA sequence to configure channels, trigger conversion, and
+    read results.
+
+    Uses DMAC Channels: 0,1
+**/
+class AdcManager {
+public:
+    /**
+        \enum AdcChannels
+
+        ADC conversion channels.
+
+        \note These are currently assumed to be unsigned values.
+    **/
+    typedef enum {
+        ADC_VSUPPLY_MON = 0, ///< Supply voltage monitor
+        ADC_AIN12,           ///< Analog input A-12
+        ADC_5VOB_MON,        ///< 5V off-board monitor
+        ADC_AIN11,           ///< Analog input A-11
+        ADC_AIN10,           ///< Analog input A-10
+        ADC_AIN09,           ///< Analog input A-9
+        ADC_SDRVR3_IMON,     ///< Screwdriver M-3 current monitor
+        ADC_SDRVR2_IMON,     ///< Screwdriver M-2 current monitor
+        ADC_CHANNEL_COUNT // Keep at end
+    } AdcChannels;
+
+    /**
+        \enum FilterUnits
+        \brief Units for the filter time constant.
+
+        \note One sample time is 200 microseconds, so 1 ms = 5 sample times.
+    **/
+    typedef enum {
+        /** Raw units. **/
+        FILTER_UNIT_RAW,
+        /** Milliseconds. **/
+        FILTER_UNIT_MS,
+        /** Sample times. **/
+        FILTER_UNIT_SAMPLES,
+    } FilterUnits;
+
+    /**
+        The default resolution of the ADC, in bits.
+    **/
+    static const uint8_t ADC_RESOLUTION_DEFAULT = 12;
+    /**
+        The default timeout for waiting on an ADC conversion, in samples.
+    **/
+    static const uint8_t ADC_TIMEOUT_DEFAULT = 3;
+    /**
+        The default ADC filter time constant, in milliseconds.
+    **/
+    static const uint32_t ADC_IIR_FILTER_TC_MS = 2;
+
+#ifndef HIDE_FROM_DOXYGEN
+    // Max voltage that a channel can read.
+    // This will probably need a scale rework once populated
+    // Calculated by multiplying the ratio by the ADC supply which is
+    // 3.3v
+    static constexpr float ADC_CHANNEL_MAX_FLOAT[ADC_CHANNEL_COUNT] = {
+        80.85,      // ADC_VSUPPLY_MON
+        10.0,       // ADC_AIN12
+        6.6,        // ADC_5VOB_MON
+        10.0,       // ADC_AIN11
+        10.0,       // ADC_AIN10
+        10.0,       // ADC_AIN09
+        10.0,       // ADC_SDRVR3_IMON
+        10.0        // ADC_SDRVR2_IMON
+    };
+
+    /**
+        \brief One-time initialization of the ADC.
+
+        Enables Peripheral clock, configures multiplexers,
+        configures DMAC (Direct Memory Access Controller),
+        and configures ADC module.
+    **/
+    void Initialize();
+
+    /**
+        \brief Updates the ADC Manager.
+
+        If a conversion has been performed, restarts the DMA sequence.
+        DMA sequence performs all of the actual work to setup channels,
+        trigger conversions, and read results.
+
+        \note: Should be called at the ClearCore sample rate.
+    **/
+    void Update();
+#endif
+
+    /**
+        \brief Configure the ADC conversion resolution.
+
+        ADC naturally supports 12-bit operation. Lower resolution is used
+        to decrease sample time.
+
+        Passing an unsupported resolution yields no change and returns false.
+
+        Acceptable Inputs:
+        - 8-bit
+        - 10-bit
+        - 12-bit
+
+        \note The default resolution is 12-bit.
+
+        \code{.cpp}
+        // Set the ADC resolution to 10-bit
+        AdcMgr.AdcResolution(10);
+        \endcode
+
+        \param resolution Bit resolution. Acceptable values: 8, 10, and 12.
+
+        \return Success
+    **/
+    bool AdcResolution(uint8_t resolution);
+
+    /**
+        \brief Returns the resolution of the ADC.
+
+        Possible values are: 8, 10, and 12.
+
+        \code{.cpp}
+        // Save the ADC resolution
+        uint8_t currentResolution = AdcMgr.AdcResolution();
+        \endcode
+    **/
+    volatile const uint8_t &AdcResolution() {
+        return m_AdcResolution;
+    }
+
+    /**
+        \brief Returns the filtered ADC result of a specific channel.
+
+        \code{.cpp}
+        // Save the filtered ADC reading of analog input A-10.
+        uint16_t result = AdcMgr.FilteredResult(AdcManager::ADC_AIN10);
+        \endcode
+
+        \param[in] adcChannel ADC channel to get the filtered results of.
+        \return Filtered result.
+
+        \note For performance reasons, does not perform any bounds checking.
+    **/
+    volatile const uint16_t &FilteredResult(AdcChannels adcChannel) {
+        return m_AdcResultsConvertedFiltered[adcChannel];
+    }
+
+    /**
+        \brief Returns the converted ADC result of a specific channel.
+
+        \code{.cpp}
+        // Save the converted ADC reading of analog input A-10.
+        uint16_t result = AdcMgr.ConvertedResult(AdcManager::ADC_AIN10);
+        \endcode
+
+        \param[in] adcChannel ADC channel to get the results of.
+        \return Converted result.
+
+        \note For performance reasons, does not perform any bounds checking.
+    **/
+    volatile const uint16_t &ConvertedResult(AdcChannels adcChannel) {
+        return m_AdcResultsConverted[adcChannel];
+    }
+
+    /**
+        \brief Sets the IIR filter time constant for an ADC channel.
+
+        \code{.cpp}
+        // Set the filter time constant of A-10 to 15ms and save its success
+        // status.
+        bool succeeded = AdcMgr.FilterTc(AdcManager::ADC_AIN10, 15,
+                                            AdcManager::FILTER_UNIT_MS);
+        \endcode
+
+        \param[in] adcChannel ADC channel to set filter constant for
+        \param[in] tc The new filter time constant (99% step change time)
+        \param[in] theUnits The units of the time constant \a tc.
+        See #FilterUnits.
+        \return Success.
+    **/
+    bool FilterTc(AdcChannels adcChannel, uint16_t tc, FilterUnits theUnits);
+
+    /**
+        \brief Gets the IIR filter time constant of an ADC channel.
+
+        \code{.cpp}
+        // Save the time constant in ms for A-10.
+        uint16_t tc = AdcMgr.FilterTc(AdcManager::ADC_AIN10,
+                                        AdcManager::FILTER_UNIT_MS);
+        \endcode
+
+        \param[in] adcChannel ADC channel to get filter constant for.
+        \param[in] theUnits The units of the returned time constant.
+        See #FilterUnits.
+
+        \return Time constant value in the specified units, or 0 if the
+        ADC channel is invalid.
+    **/
+    uint16_t FilterTc(AdcChannels adcChannel, FilterUnits theUnits);
+
+    /**
+        \brief Resets the filter for an ADC Channel.
+
+        \code{.cpp}
+        // Resets the filter for A-10 and saves the success status.
+        bool success = AdcMgr.FilterReset(AdcManager::ADC_AIN10, 10);
+        \endcode
+
+        \param[in] adcChannel ADC Channel filter to reset.
+        \param[in] newSetting The initial filter value.
+        \return Success.
+    **/
+    bool FilterReset(AdcChannels adcChannel, uint16_t newSetting) {
+        if (adcChannel >= ADC_CHANNEL_COUNT) {
+            return false;
+        }
+        m_analogFilter[adcChannel].Reset(newSetting);
+        m_AdcResultsConvertedFiltered[adcChannel] =
+            m_analogFilter[adcChannel].LastOutput();
+        return true;
+    }
+
+    /**
+        \brief Configure the ADC conversion timeout.
+
+        The ADC will post an error to the StatusReg if it is unable to
+        complete a conversion within the number of samples specified by the
+        input of this function.
+
+        \code{.cpp}
+        // Sets the timeout to 10 samples
+        AdcMgr.AdcTimeoutLimit(10);
+        \endcode
+
+        \param[in] timeout The length of the timeout in samples.
+    **/
+    void AdcTimeoutLimit(uint8_t timeout) {
+        m_AdcTimeoutLimit = timeout;
+    }
+
+    /**
+        \brief Determine whether the ADC has timed out.
+
+        \code{.cpp}
+        if (AdcMgr.AdcTimeout()) {
+            // The ADC has timed out
+        }
+        \endcode
+
+        \return true if the ADC has time out, false otherwise.
+    **/
+    volatile const bool &AdcTimeout() {
+        return m_AdcTimeout;
+    }
+
+    /**
+        \brief Returns the filtered ADC result of a specific channel in volts.
+
+        \code{.cpp}
+        // Save the filtered voltage reading on A-10.
+        float a10Volts = AdcMgr.AnalogVoltage(AdcManager::ADC_AIN10);
+        \endcode
+
+        \param[in] adcChannel ADC channel to get the voltage reading of.
+        \return Voltage on the given ADC channel.
+
+        \note For performance reasons, does not perform any bounds checking.
+    **/
+    float AnalogVoltage(AdcChannels adcChannel) {
+        uint16_t maxReading = INT16_MAX & ~(INT16_MAX >> m_AdcResolution);
+        float voltage = ADC_CHANNEL_MAX_FLOAT[adcChannel] *
+                        m_AdcResultsConvertedFiltered[adcChannel] / maxReading;
+        return voltage;
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for the AdcManager singleton instance.
+    **/
+    static AdcManager &Instance();
+
+    /**
+        \brief Get a copy of the shift register state last written to the SPI
+        data register.
+
+        \return The last-written shift register state.
+    **/
+    volatile const uint32_t &ShiftRegSnapshot() {
+        return m_shiftRegSnapshot;
+    }
+#endif
+private:
+
+    /**
+        Used to populate filters with initial values. Float to make human
+        readable. Conversion to ADC counts only happens once during init so
+        performance loss is minimal for the readability.
+    **/
+    static constexpr float ADC_INITIAL_FILTER_VALUE_V[ADC_CHANNEL_COUNT] = {
+        24.0, // ADC_VSUPPLY_MON
+        0.0,  // ADC_AIN12
+        5.0,  // ADC_5VOB_MON
+        0.0,  // ADC_AIN11
+        0.0,  // ADC_AIN10
+        0.0,  // ADC_AIN09
+        0.0,  // ADC_SDRVR3_IMON
+        0.0,  // ADC_SDRVR2_IMON
+    };
+
+    // ADC state holders in Q15. ADC logic has already been performed
+    volatile uint16_t m_AdcResultsConverted[ADC_CHANNEL_COUNT] = {0};
+    volatile uint16_t m_AdcResultsConvertedFiltered[ADC_CHANNEL_COUNT] = {0};
+    Iir16 m_analogFilter[ADC_CHANNEL_COUNT];
+
+    bool m_initialized;
+
+    bool m_AdcTimeout;
+    uint32_t m_shiftRegSnapshot;
+    uint32_t m_shiftRegPending;
+
+    /** Resolution of the ADC interface **/
+    uint8_t m_AdcResolution;
+    uint8_t m_AdcResPending;
+
+    /** ADC Conversion timeout. Timeout will trip if conversion is not done in
+        this number of samples.  **/
+    uint8_t m_AdcTimeoutLimit;
+
+    /** Count of samples since last ADC conversion. **/
+    uint32_t m_AdcBusyCount;
+
+    /**
+        \brief Constructor for AdcManager.
+
+        Initializes member variables, doesn't do any work.
+
+        \note Should not be called by anything other than SysManager.
+    **/
+    AdcManager();
+
+    void DmaInit();
+    void DmaUpdate();
+
+    /**
+        \brief Apply the ADC conversion resolution change.
+
+        Called from within the main interrupt to apply pending
+        resolution changes when the ADC conversion is idle.
+
+        \return Success
+    **/
+    bool AdcResChange();
+
+}; // AdcManager
+
+} // ClearCore namespace
+
+#endif // __ADCMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/BlinkCodeDriver.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/BlinkCodeDriver.h
new file mode 100644
index 000000000..4cdafc7f0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/BlinkCodeDriver.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file BlinkCodeDriver.h
+    \brief Status blink code driver
+
+    This class provides a state machine that manages displaying multiple status
+    codes via a group / code blink pattern.
+**/
+
+
+#ifndef BLINKCODEDRIVER_H_
+#define BLINKCODEDRIVER_H_
+
+#include <stdint.h>
+
+#ifndef HIDE_FROM_DOXYGEN
+namespace ClearCore {
+
+
+/**
+    Driver for outputting blink codes that consist of a count of strobe
+    blinks representing a code group, and solid blinks representing a
+    value within that group. There can be multiple values active within
+    the same group, and the group code will be output before each value.
+**/
+class BlinkCodeDriver {
+    friend class StatusManager;
+public:
+    typedef enum {
+        BLINK_GROUP_IO_OVERLOAD,
+        BLINK_GROUP_SUPPLY_ERROR,
+        BLINK_GROUP_DEVICE_ERROR,
+        BLINK_GROUP_CCIO_OVERLOAD,
+        BLINK_GROUP_APPLICATION,
+        BLINK_GROUP_MAX,
+    } BlinkCodeGroups;
+
+    typedef enum {
+        SUPPLY_ERROR_NONE = 0x00,
+        SUPPLY_ERROR_VSUPPLY_LOW = 0x01,
+        SUPPLY_ERROR_VSUPPLY_HIGH = 0x02,
+        SUPPLY_ERROR_5VOB_OVERLOAD = 0x04,
+    } SupplyErrorCodes;
+
+    typedef enum {
+        DEVICE_ERROR_NONE = 0x00,
+        DEVICE_ERROR_HBRIDGE = 0x01,
+        DEVICE_ERROR_SD_CARD = 0x02,
+        DEVICE_ERROR_ETHERNET = 0x04,
+        DEVICE_ERROR_CCIO = 0x08,
+        DEVICE_ERROR_XBEE = 0x10,
+    } DeviceErrors;
+
+    typedef enum {
+        CCIO_OVERLOAD_NONE = 0x00,
+        CCIO_OVERLOAD_BOARD0 = 0x01,
+        CCIO_OVERLOAD_BOARD1 = 0x02,
+        CCIO_OVERLOAD_BOARD2 = 0x04,
+        CCIO_OVERLOAD_BOARD3 = 0x08,
+        CCIO_OVERLOAD_BOARD4 = 0x10,
+        CCIO_OVERLOAD_BOARD5 = 0x20,
+        CCIO_OVERLOAD_BOARD6 = 0x40,
+        CCIO_OVERLOAD_BOARD7 = 0x80,
+    } CcioOverload;
+
+    /**
+        Check if there is an active blink pattern.
+    **/
+    bool CodePresent() {
+        return m_blinkState != IDLE;
+    }
+
+    /**
+        Current state of the blink pattern.
+    **/
+    volatile const bool &LedState() {
+        return m_ledOn;
+    }
+
+    /**
+        Deactivate the given blink code.
+    **/
+    void BlinkCodeClear(uint8_t group, uint8_t code);
+
+private:
+    enum BlinkState {
+        IDLE,
+        PRE_START_DELAY,
+        START_OUTPUT,
+        PRE_GROUP_DELAY,
+        GROUP_OUTPUT,
+        GROUP_DELAY,
+        PRE_CODE_DELAY,
+        CODE_OUTPUT,
+        CODE_DELAY,
+    };
+    // What are the codes that need displaying
+    uint8_t m_codes[BLINK_GROUP_MAX];
+    // Where are we in the code output sequence
+    BlinkState m_blinkState;
+    uint8_t m_currentCode;
+    uint8_t m_currentGroup;
+    uint16_t m_timer;
+    uint16_t m_strobeCnt;
+    uint16_t m_blinkCnt;
+    bool m_ledOn;
+    bool m_patternWrap;
+
+    // What is the timing of the blink pattern
+    uint16_t m_strobeOnOffTicks;
+    uint16_t m_blinkTicks;
+    uint16_t m_prestartTicks;
+    uint16_t m_startTicks;
+    uint16_t m_pregroupTicks;
+    uint16_t m_precodeTicks;
+
+    BlinkCodeDriver()
+        : m_codes{0},
+          m_blinkState(IDLE),
+          m_currentCode(0),
+          m_currentGroup(0),
+          m_timer(0),
+          m_strobeCnt(0),
+          m_blinkCnt(0),
+          m_ledOn(false),
+          m_patternWrap(false),
+          m_strobeOnOffTicks(250),
+          m_blinkTicks(2500),
+          m_prestartTicks(5000),
+          m_startTicks(11500),
+          m_pregroupTicks(5000),
+          m_precodeTicks(2500) {}
+
+    /**
+        Activate the given blink code.
+    **/
+    void CodeGroupAdd(uint8_t group, uint8_t codes) {
+        m_codes[group] |= codes;
+    }
+
+    /**
+        Update the blink codes.
+    **/
+    void Update();
+
+    /**
+        \brief Current state of the blink pattern.
+        \param[in] group The group that the blink pattern belongs to.
+        \param[in] code The error code to display.
+    **/
+    bool NextCode(uint8_t group, uint8_t code);
+};
+
+}
+#endif /* HIDE_FROM_DOXYGEN */
+#endif /* BLINKCODEDRIVER_H_ */
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/CcioBoardManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/CcioBoardManager.h
new file mode 100644
index 000000000..47873fce6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/CcioBoardManager.h
@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file CcioBoardManager.h
+
+    This class manages control of the ClearCore I/O (CCIO-8) Expansion Boards
+    connected to a serial port on the ClearCore.
+
+    Provides support for CCIO-8 discovery and non-PWM digital I/O on CCIO-8
+    board pins.
+**/
+
+#ifndef __CCIOBOARDMANAGER_H__
+#define __CCIOBOARDMANAGER_H__
+
+#include <stddef.h>
+#include <stdint.h>
+#include "CcioPin.h"
+#include "SerialDriver.h"
+#include "SysConnectors.h"
+#include "SysTiming.h"
+
+namespace ClearCore {
+
+/** The number of I/O pins on one CCIO-8 Expansion Board. **/
+#define CCIO_PINS_PER_BOARD  8
+#ifndef MAX_CCIO_DEVICES
+/** The maximum number CCIO-8 Expansion Boards that can be chained to the
+    ClearCore at any given time. **/
+#define MAX_CCIO_DEVICES 8
+/**
+    The maximum number of CCIO-8 pins that can be addressed at any given time.
+**/
+#define CCIO_PIN_CNT (CCIO_PINS_PER_BOARD * MAX_CCIO_DEVICES)
+#endif
+
+/** The maximum number of times to attempt to flush data through the chain of
+    connected  CCIO-8 boards during the discover process before bailing out. **/
+#ifndef MAX_FLUSH_ATTEMPTS
+#define MAX_FLUSH_ATTEMPTS 4
+#endif
+
+/** The maximum number of allowable data glitches to handle during the discover
+    process before bailing out. **/
+#ifndef MAX_GLITCH_LIM
+#define MAX_GLITCH_LIM 4
+#endif
+
+/** The number of consecutive samples having the output asserted with the input
+    deasserted before the output is flagged as being overloaded. **/
+#ifndef CCIO_OVERLOAD_TRIP_TICKS
+#define CCIO_OVERLOAD_TRIP_TICKS ((uint8_t)(2.4 * MS_TO_SAMPLES))
+#endif
+/** The number of samples to force the output to be deasserted when an
+    overload condition occurs on that output. **/
+#ifndef CCIO_OVERLOAD_FOLDBACK_TICKS
+#define CCIO_OVERLOAD_FOLDBACK_TICKS (100 * MS_TO_SAMPLES)
+#endif
+/**
+    \brief ClearCore I/O Expansion Board Manager Class
+
+    This is the manager class for all the CCIO-8 pin connectors. The CCIO-8 link
+    state is established and queried through this class, as well as the filter
+    setting for all of the CCIO-8 connectors. Each CCIO-8 connector can be
+    accessed through this class, in addition to the individual access available
+    through the CcioPin class.
+
+    For more detailed information on the CCIO-8 system, check out the \ref
+    CCIOMain informational page.
+**/
+class CcioBoardManager {
+    friend class SysManager;
+    friend class CcioPin;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for singleton instance
+    **/
+    static CcioBoardManager &Instance();
+#endif
+
+    /**
+        \brief Read the digital state of the specified CCIO-8 pin.
+
+        \code{.cpp}
+        if (CcioMgr.PinState(CLEARCORE_PIN_CCIOA0)) {
+            // The state of connector 0 on the first CCIO-8 board is high.
+        }
+        \endcode
+
+        \param[in] pinNum The CCIO-8 pin number
+
+        \return Returns true if the pin state is TRUE, and false if the pin
+                state is FALSE, or if the specified CCIO-8 pin does not exist, or
+                if the CcioBoardManager is not yet initialized.
+    **/
+    bool PinState(ClearCorePins pinNum);
+
+    /**
+        \brief Write the digital state to the specified CCIO-8 pin.
+
+        \code{.cpp}
+        // Set the first CCIO-8 board's connector 0 output FALSE.
+        CcioMgr.PinState(CLEARCORE_PIN_CCIOA0, false);
+        \endcode
+
+        \param[in] pinNum The CCIO-8 pin number
+        \param[in] newState The digital value to be written to the connector.
+    **/
+    void PinState(ClearCorePins pinNum, bool newState);
+
+    /**
+        \brief Start an output pulse.
+
+        This allows you to start a pulse on a CCIO-8 connector that is on for
+        \a onTime milliseconds and off for \a offTime milliseconds and will stop
+        after \a pulseCount cycles.
+        A \a pulseCount of 0 will cause the pulse to run endlessly.
+
+        If a pulse is already running, calling this will allow you to override
+        the previous pulse (after the next change in state).
+
+        \code{.cpp}
+        // Begin a 100ms on/200ms off pulse on the first CCIO-8 board's
+        // connector 0 output that will complete 20 cycles and prevent further
+        // code execution until the cycles are complete.
+        CcioMgr.OutputPulsesStart(CLEARCORE_PIN_CCIOA0, 100, 200, 20, true);
+        \endcode
+
+        \param[in] pinNum The CCIO-8 pin number.
+        \param[in] onTime The amount of time the input will be held on [ms].
+        \param[in] offTime The amount of time the input will be held off [ms].
+        \param[in] pulseCount (optional) The amount of cycles the pulse will
+        run for. Default: 0 (pulse runs endlessly).
+        \param[in] blockUntilDone (optional) If true, the function doesn't
+        return until the pulses have been sent. Default: false.
+    **/
+    void OutputPulsesStart(ClearCorePins pinNum, uint32_t onTime,
+                           uint32_t offTime, uint16_t pulseCount = 0,
+                           bool blockUntilDone = false);
+    /**
+        \brief Stop an output pulse.
+
+        This allows you to stop the currently running pulse on a CCIO-8 output.
+        The output will always be set to FALSE after canceling a pulse.
+
+        \code{.cpp}
+        // Stop the active output pulse on the first CCIO-8 board's connector 0.
+        CcioMgr.OutputPulsesStop(CLEARCORE_PIN_CCIOA0);
+        \endcode
+
+        \param[in] pinNum The CCIO-8 pin number
+        \param[in] stopImmediately (optional) If true, the output pulses will
+        be stopped immediately; if false, any active pulse will be completed
+        first. Default: true.
+    **/
+    void OutputPulsesStop(ClearCorePins pinNum, bool stopImmediately = true);
+
+    /**
+        \brief Check the output pulse state.
+
+        This allows you to see which CCIO-8 pins have active output pulses
+        being sent.
+
+        \code{.cpp}
+        if (CcioMgr.OutputPulsesActive()) {
+            // If there's an output pulse active on any output, do something
+        }
+        \endcode
+
+        \return A bitmask representing which pins are sending output pulses.
+    **/
+    volatile const uint64_t &OutputPulsesActive() {
+        return m_pulseActive;
+    }
+
+    /**
+        \brief Polls for and discovers all CCIO-8 boards connected to the
+        ClearCore.
+
+        \code{.cpp}
+        // Discover and create a CCIO-8 link on COM-1
+        CcioMgr.CcioDiscover(&ConnectorCOM1);
+        \endcode
+
+        \note Typically this function will not need to be called. Opening a
+        SerialDriver port in CCIO mode will automatically discover all CCIO
+        connections on that port. This function is only necessary when the Auto-
+        Rediscover feature is disabled and a broken CCIO link needs to be
+        rebuilt.
+
+        \param[in] comInstance A pointer to the SerialDriver that controls the
+                               serial port that the CCIO-8 is plugged into
+        \return Number of CCIO-8 devices connected.
+    **/
+    uint8_t CcioDiscover(SerialDriver *comInstance);
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Cleanly closes the CCIO-8 connection.
+
+        \code{.cpp}
+        // Kill the CCIO-8 link
+        CcioMgr.LinkClose();
+        \endcode
+    **/
+    void LinkClose();
+#endif
+
+    /**
+        \brief Accessor for the number of CCIO-8 boards connected to the
+        ClearCore.
+
+        \code{.cpp}
+        // Save how many CCIO-8 boards are in the link
+        uint8_t boardCount = CcioMgr.CcioCount();
+        \endcode
+
+        \note If the CCIO link is broken CcioCount will return the number of
+        CCIO-8 boards in the previously working link. CcioCount will only update
+        when a new, healthy CCIO link network is detected.
+
+        \return Number of CCIO-8 devices connected.
+    **/
+    volatile const uint8_t &CcioCount() {
+        return m_ccioCnt;
+    }
+
+    /**
+        \brief Accessor for the CCIO-8 link status.
+
+        \code{.cpp}
+        if (CcioMgr.LinkBroken()) {
+            // The link is down, handle it somehow
+        }
+        \endcode
+
+        \return True if the CCIO-8 link is broken.
+    **/
+    volatile const bool &LinkBroken() {
+        return m_ccioLinkBroken;
+    }
+
+    /**
+        \brief Accessor for all the CCIO-8 pins' overloaded states.
+
+        \code{.cpp}
+        if (CcioMgr.IoOverloadRT()) {
+            // There is an overload I/O point, handle it
+        }
+        \endcode
+
+        \return A bitmask indicating which CCIO-8 pins have asserted
+        outputs but the subsequent read of the input is FALSE.
+    **/
+    volatile const uint64_t &IoOverloadRT() {
+        return m_ccioOverloaded;
+    }
+
+    /**
+        \brief Accessor for all the CCIO-8 pins' accumulated overload states.
+
+        \code{.cpp}
+        // Save the I/O points that have overloaded since the previous read
+        uint64_t accumOverloads = CcioMgr.IoOverloadAccum();
+        \endcode
+
+        \return A bitmask indicating which CCIO-8 pins have been overloaded
+        since the last time IoOverloadAccum() was called.
+    **/
+    uint64_t IoOverloadAccum();
+
+    /**
+        \brief Accessor for all the CCIO-8 pins' accumulated overload states.
+
+        \code{.cpp}
+        // Save the I/O points that have overloaded since program startup
+        uint64_t accumOverloads = CcioMgr.IoOverloadSinceStartupAccum();
+        \endcode
+
+        \return A bitmask indicating which CCIO-8 pins have been overloaded
+        since the ClearCore has been restarted.
+    **/
+    volatile const uint64_t &IoOverloadSinceStartupAccum() {
+        return m_overloadSinceStartupAccum;
+    }
+
+    /**
+        \brief Clear on read accessor for rising input edges.
+
+        \code{.cpp}
+        if (CcioMgr.InputsRisen()) {
+            // An input on a CCIO-8 has risen, react to it.
+        }
+        \endcode
+
+        \param [in] mask (optional) The CCIO-8 bits to check for rising edges.
+
+        \return CCIO-8 bits that have risen since last poll.
+    **/
+    uint64_t InputsRisen(uint64_t mask = UINT64_MAX);
+
+    /**
+        \brief Clear on read accessor for falling input edges.
+
+        \code{.cpp}
+        if (CcioMgr.InputsFallen()) {
+            // An input on a CCIO-8 has fallen, react to it.
+        }
+        \endcode
+
+        \param [in] mask (optional) The CCIO-8 bits to check for falling edges.
+
+        \return CCIO-8 bits that have fallen since last poll.
+    **/
+    uint64_t InputsFallen(uint64_t mask = UINT64_MAX);
+
+    /**
+        \brief Accessor for all the CCIO-8 pins' filtered input states.
+
+        \code{.cpp}
+        // Save a reference to the state of all CCIO-8 input points.
+        uint64_t iState = CcioMgr.InputState();
+        \endcode
+
+        \return A bitmask indicating which CCIO-8 inputs are asserted.
+    **/
+    volatile const uint64_t &InputState() {
+        return m_filteredInputs;
+    }
+
+    /**
+        \brief Accessor for all the CCIO-8 pins' output states.
+
+        \code{.cpp}
+        // Save a reference to the state of all CCIO-8 output points.
+        uint64_t oState = CcioMgr.OutputState();
+        \endcode
+
+        \return A bitmask indicating which CCIO-8 outputs are asserted.
+    **/
+    volatile const uint64_t &OutputState() {
+        return m_lastOutputs;
+    }
+
+    /**
+        \brief Enable or Disable the automatic rediscover function
+
+        If the CCIO-8 link is broken the CcioBoardManager can attempt to rebuild
+        the link.
+
+        \code{.cpp}
+        // Turn off the CCIO-8 rediscover feature
+        CcioMgr.CcioRediscoverEnable(false);
+        \endcode
+
+        \note This feature is enabled by default.
+
+        \param[in] enable Whether to enable or disable rediscover.
+    **/
+    void CcioRediscoverEnable(bool enable);
+
+    /**
+        \brief Accessor for the individual CCIO-8 pin connectors.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->State()) {
+            // The first CCIO-8 board's connector 0 input is high.
+        }
+        \endcode
+
+        \param[in] connectorIndex The index of the CCIO-8 pin being requested
+        \return A pointer to the corresponding CcioPin Connector object
+    **/
+    CcioPin *PinByIndex(ClearCorePins connectorIndex);
+
+    /**
+        \brief Accessor for the CCIO-8 link refresh rate
+
+        Calculates and returns the refresh rate based on the number
+        of CCIO-8 boards currently connected.
+    **/
+    uint8_t RefreshRate() {
+        uint8_t cnt = CcioCount();
+        return (cnt > 1) ? (cnt >> 1) : 1;
+    }
+
+private:
+    union CcioBuf {
+        struct __attribute__((packed)) {
+            uint8_t writeMarker;
+            uint64_t inputs;
+            uint64_t outputsSwapped;
+            uint8_t readMarker;
+        } buf64;
+        uint8_t buf8[2 * MAX_CCIO_DEVICES + 2];
+        CcioBuf() {
+            Clear();
+        }
+        void Clear() {
+            buf64.writeMarker = 0;
+            buf64.inputs = 0;
+            buf64.outputsSwapped = 0;
+            buf64.readMarker = 0;
+        };
+    };
+
+    typedef enum {
+        CCIO_SEARCH,
+        CCIO_TEST,
+        CCIO_FOUND
+    } CcioDiscoverState;
+
+    CcioBuf m_writeBuf;
+    CcioBuf m_readBuf;
+
+    // Reference for the discovery state of the CCIO-8 link network
+    CcioDiscoverState m_discoverState;
+
+    // Reference to serial port
+    SerialDriver *m_serPort;
+    // CCIO-8 Device Count
+    uint8_t m_ccioCnt;
+    // Refresh rate
+    uint8_t m_ccioRefreshRate;
+    // Refresh delay
+    uint8_t m_ccioRefreshDelay;
+    // Currently overloaded outputs
+    uint64_t m_throttledOutputs;
+
+    // Storage for inputs/outputs (max 64 pins to a serial port)
+    // LSB corresponds to 1st pin on 1st CCIO-8 in the chain
+    uint64_t m_currentInputs;
+    uint64_t m_filteredInputs;
+    uint64_t m_currentOutputs;
+    uint64_t m_outputMask;
+    uint64_t m_lastOutputsSwapped;
+    // copy of last outputs sent, prior to any swapping or throttling
+    uint64_t m_lastOutputs;
+    uint64_t m_outputsWithThrottling;
+    uint64_t m_ccioMask;    // mask for active CCIOs
+
+    // Pulse out control variables
+    uint64_t m_pulseActive;
+    uint64_t m_pulseValue;
+    uint64_t m_pulseStopPending;
+
+    uint16_t m_consGlitchCnt;   // count of consecutive glitches detected
+    bool m_ccioLinkBroken;
+    uint64_t m_ccioOverloaded;
+    uint64_t m_ccioOverloadAccum;
+    uint64_t m_overloadSinceStartupAccum;
+    uint64_t m_inputRegRisen;
+    uint64_t m_inputRegFallen;
+    uint32_t m_faultLed;
+    bool m_autoRediscover;
+    uint32_t m_lastDiscoverTime;
+
+    CcioPin m_ccioPins[CCIO_PIN_CNT];
+
+    /**
+        Constructor
+    **/
+    CcioBoardManager();
+
+    /**
+        Initializes the CCIO-8 manager and the CcioPin objects.
+    **/
+    void Initialize();
+
+    /**
+        Updates filtered internal state.
+    **/
+    void Refresh();
+
+    /**
+        Slow rate refresh that controls the rediscover.
+    **/
+    void RefreshSlow();
+
+    /**
+        Set the current output overload bits
+    **/
+    void IoOverloadRT(uint64_t overloadState);
+
+    /*
+        Fill a buffer with len bytes of the given val
+    */
+    static void FillBuffer(uint8_t *buf, uint8_t len, uint8_t val) {
+        uint8_t i;
+        for (i = 0; i < len; i++) {
+            *buf++ = val;
+        }
+    }
+
+    /*
+        Return true if all entries are equal to val
+    */
+    static bool AllEntriesEqual(const uint8_t *buf, uint8_t len, uint8_t val) {
+        uint8_t i;
+        for (i = 0; i < len; i++) {
+            if (buf[i] != val) {
+                return false;
+            }
+        }
+        return true;
+    }
+
+}; // CcioBoardManager
+
+} // ClearCore namespace
+
+#endif // __CCIOBOARDMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/CcioPin.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/CcioPin.h
new file mode 100644
index 000000000..addf24fdb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/CcioPin.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file CcioPin.h
+    \brief Connector class for an individual CCIO-8 pin.
+
+    This manages the digital input and output for the CCIO-8 pins.
+**/
+
+#ifndef __CCIOPIN_H__
+#define __CCIOPIN_H__
+
+#include <sam.h>
+#include <stdint.h>
+
+#include "Connector.h"
+#include "SysConnectors.h"
+
+namespace ClearCore {
+
+/**
+    \class CcioPin
+    \brief Connector class for an individual CCIO-8 pin.
+
+    Manages individual CCIO-8 pins.
+
+    For more detailed information on the CCIO-8 system, check out the \ref
+    CCIOMain informational page.
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class CcioPin : public Connector {
+    friend class CcioBoardManager;
+
+public:
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->Mode() ==
+                                Connector::INPUT_DIGITAL) {
+            // Connector 0 on the first CCIO-8 board is currently configured
+            // as a digital input.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        Configure the connector to operate in a new I/O mode.
+
+        \code{.cpp}
+        // Configure the first CCIO-8 board's connector 0 as a digital output.
+        CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->Mode(Connector::OUTPUT_DIGITAL);
+        \endcode
+
+        \param[in] newMode The new mode to be set.
+        The valid modes for this connector type are:
+        - #INPUT_DIGITAL
+        - #OUTPUT_DIGITAL.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    virtual bool Mode(ConnectorModes newMode) override;
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias->Type() == CCIO_DIGITAL_IN_OUT_TYPE) {
+            // This generic connector variable is a CCIO-8 pin.
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::CCIO_DIGITAL_IN_OUT_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->IsWritable()) {
+            // The first CCIO-8 board's connector 0 is currently set as an
+            // output.
+        }
+        \endcode
+
+        \return True if in #OUTPUT_DIGITAL mode, false otherwise
+    **/
+    bool IsWritable() override {
+        return m_mode == OUTPUT_DIGITAL;
+    }
+
+    /**
+        \brief In input mode, get the connector's last filtered
+        sampled value. In output mode, get the connector's output state.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->State()) {
+            // The first CCIO-8 board's connector 0 input is high.
+        }
+        \endcode
+
+        \return The latest filtered value on this connector when in input mode;
+        the output state when in output mode.
+    **/
+    int16_t State() override;
+    /**
+        \brief Set the output state of the connector.
+
+        This allows you to change the output value of the connector item.
+
+        \code{.cpp}
+        // Set the first CCIO-8 board's connector 0 output to high.
+        CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->State(1);
+        \endcode
+
+        \param[in] newState The value to be output.
+    **/
+    bool State(int16_t newState) override;
+
+    /**
+        \brief Set the connector's digital filter length in samples. The default
+        is 3 samples.
+
+        This will set the length of the filter equal to
+        (\a samples * CCIO-8 refresh rate) for this connector.
+
+        Restarts any filtering in progress.
+
+        \code{.cpp}
+        // Sets the filter to 10 samples (2ms)
+        CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->FilterLength(10);
+        \endcode
+
+        \param[in] samples The number of samples to filter.
+
+        \note One sample time is 200 microseconds.
+    **/
+    void FilterLength(uint16_t samples) {
+        m_filterLength = samples;
+        m_filterTicksLeft = samples;
+    }
+
+    /**
+        \brief Set the connector's digital filter length in ms.
+
+        Restarts any filtering in progress.
+
+        \code{.cpp}
+        // Sets the filter to 10ms
+        CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->Filter_ms(10);
+        \endcode
+
+        \param[in] len The length of the filter in ms.
+
+        \note The maximum filter time is 13000 milliseconds.
+    **/
+    void Filter_ms(uint16_t len);
+
+    /**
+        \brief Check whether the connector is in a hardware fault state.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->IsInHwFault()) {
+            // The first CCIO-8 board's connector 0 is in a fault state.
+        }
+        \endcode
+
+        \return Connector is in fault
+    **/
+    bool IsInHwFault() override;
+
+    /**
+        \brief Clear on read accessor for this connector's rising input state.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->InputRisen()) {
+            // The first CCIO-8 board's connector 0 input has transitioned from
+            // FALSE to TRUE since the last read.
+        }
+        \endcode
+
+        \return true if the input has risen since the last call
+    **/
+    bool InputRisen();
+
+    /**
+        \brief Clear on read accessor for this connector's falling input state.
+
+        \code{.cpp}
+        if (CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->InputFallen()) {
+            // The first CCIO-8 board's connector 0 input has transitioned from
+            // TRUE to FALSE since the last read.
+        }
+        \endcode
+
+        \return true if the input has fallen since the last call
+    **/
+    bool InputFallen();
+
+    /**
+        \brief Start an output pulse.
+
+        This allows you to start a pulse on the output that is on for \a onTime
+        milliseconds and off for \a offTime milliseconds and will stop after
+        \a pulseCount cycles.
+        A \a pulseCount of 0 will cause the pulse to run endlessly. If a pulse
+        is already running, calling this will allow you to override the previous
+        pulse (after the next change in state).
+
+        \code{.cpp}
+        // Begin a 100ms on/200ms off pulse on the first CCIO-8 board's
+        // connector 0 output that will complete 20 cycles and prevent further
+        // code execution until the cycles are complete.
+        CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->OutputPulsesStart(100, 200,
+                                                                    20, true);
+        \endcode
+
+        \param[in] onTime The amount of time the input will be held on [ms].
+        \param[in] offTime The amount of time the input will be held off [ms].
+        \param[in] pulseCount (optional) The amount of cycles the pulse will run
+        for. Default: 0 (pulse runs endlessly).
+        \param[in] blockUntilDone (optional) If true, the function doesn't
+        return until the pulses have been sent. Default: false.
+    **/
+    void OutputPulsesStart(uint32_t onTime, uint32_t offTime,
+                           uint16_t pulseCount = 0, bool blockUntilDone = false);
+
+    /**
+        \brief Stop an output pulse.
+
+        This allows you to stop the currently running pulse on this output. The
+        output will always be set to FALSE after canceling a pulse.
+
+        \code{.cpp}
+        // Stop the active output pulse on the first CCIO-8's connector 0
+        CcioMgr.PinByIndex(CLEARCORE_PIN_CCIOA0)->OutputPulsesStop();
+        \endcode
+
+        \param[in] stopImmediately (optional) If true, the output pulses will
+        be stopped immediately; if false, any active pulse will be completed
+        first. Default: true.
+    **/
+    void OutputPulsesStop(bool stopImmediately = true);
+
+protected:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct the CCIO-8 pin.
+    **/
+    CcioPin();
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins ccioPin) override;
+
+    /**
+        \brief Update connector's state.
+
+        Poll the underlying connector for new state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    void Refresh() override {}
+#endif
+
+private:
+    // Port access
+    uint64_t m_dataBit;
+
+    // Stability filter
+    uint16_t m_filterLength;
+    // Set to filter length on input change
+    uint16_t m_filterTicksLeft;
+    // Consecutive sample filter for tripping overload conditions
+    uint16_t m_overloadTripCnt;
+    // Overload condition output throttling
+    uint16_t m_overloadFoldbackCnt;
+
+    uint32_t m_pulseOnTicks;
+    uint32_t m_pulseOffTicks;
+    uint32_t m_pulseTicksRemaining;
+    uint16_t m_pulseStopCount;
+    uint16_t m_pulseCounter;
+};
+
+} // ClearCore namespace
+
+#endif // __CCIOPIN_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ClearCore.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ClearCore.h
new file mode 100644
index 000000000..b62f22520
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ClearCore.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+ 
+#ifndef __CLEARCORE_H__
+#define __CLEARCORE_H__
+
+// Header files from the ClearCore hardware that define connectors available
+#include "AdcManager.h"
+#include "CcioBoardManager.h"
+#include "DigitalIn.h"
+#include "DigitalInAnalogIn.h"
+#include "DigitalInOut.h"
+#include "DigitalInOutAnalogOut.h"
+#include "DigitalInOutHBridge.h"
+#include "EthernetManager.h"
+#include "InputManager.h"
+#include "LedDriver.h"
+#include "EncoderInput.h"
+#include "MotorDriver.h"
+#include "MotorManager.h"
+#include "SdCardDriver.h"
+#include "SerialDriver.h"
+#include "SerialUsb.h"
+#include "StatusManager.h"
+#include "SysManager.h"
+#include "SysTiming.h"
+#include "XBeeDriver.h"
+
+
+namespace ClearCore {
+
+extern LedDriver ConnectorLed;              ///< User-driven LED instance
+
+// IO connectors
+extern DigitalInOutAnalogOut ConnectorIO0;  ///< IO-0 connector instance
+extern DigitalInOut ConnectorIO1;           ///< IO-1 connector instance
+extern DigitalInOut ConnectorIO2;           ///< IO-2 connector instance
+extern DigitalInOut ConnectorIO3;           ///< IO-3 connector instance
+
+// H-Bridge type connectors
+extern DigitalInOutHBridge ConnectorIO4;    ///< IO-4 connector instance
+extern DigitalInOutHBridge ConnectorIO5;    ///< IO-5 connector instance
+
+// Digital input only connectors
+extern DigitalIn ConnectorDI6;              ///< DI-6 connector instance
+extern DigitalIn ConnectorDI7;              ///< DI-7 connector instance
+extern DigitalIn ConnectorDI8;              ///< DI-8 connector instance
+
+// Analog/Digital Inputs
+extern DigitalInAnalogIn ConnectorA9;       ///< A-9 connector instance
+extern DigitalInAnalogIn ConnectorA10;      ///< A-10 connector instance
+extern DigitalInAnalogIn ConnectorA11;      ///< A-11 connector instance
+extern DigitalInAnalogIn ConnectorA12;      ///< A-12 connector instance
+
+// Motor Connectors
+extern MotorDriver ConnectorM0;             ///< M-0 connector instance
+extern MotorDriver ConnectorM1;             ///< M-1 connector instance
+extern MotorDriver ConnectorM2;             ///< M-2 connector instance
+extern MotorDriver ConnectorM3;             ///< M-3 connector instance
+
+// Serial Port connectors
+extern SerialUsb    ConnectorUsb;           ///< USB connector instance
+extern SerialDriver ConnectorCOM0;          ///< COM-0 connector instance
+extern SerialDriver ConnectorCOM1;          ///< COM-1 connector instance
+
+/// Ethernet manager
+extern EthernetManager &EthernetMgr;
+
+/// CCIO-8 manager
+extern CcioBoardManager &CcioMgr;
+
+/// Motor connector manager
+extern MotorManager &MotorMgr;
+
+/// ADC module manager
+extern AdcManager &AdcMgr;
+
+/// Input manager
+extern InputManager &InputMgr;
+
+/// Xbee wireless
+extern XBeeDriver XBee;
+
+/// Position Decoder
+extern EncoderInput EncoderIn;
+
+/// Status manager
+extern StatusManager &StatusMgr;
+
+/// Timing manager
+extern SysTiming &TimingMgr;
+
+/// SD card
+extern SdCardDriver SdCard;
+
+/// System manager
+extern SysManager SysMgr;
+}
+
+using namespace ClearCore;
+
+#endif // __CLEARCORE_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/Connector.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/Connector.h
new file mode 100644
index 000000000..d250e1b13
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/Connector.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file Connector.h
+    \brief Base class for all connector classes.
+
+    This is the base class for interacting with a ClearCore connector.
+
+    It provides a generic interface that all connectors have. This includes
+    - Connector Type
+    - Generic integer "value"
+    - A Refresh function to force the reading of the underlying information
+    and perform ancillary work such as scheduling and LED display update.
+**/
+
+#ifndef __CONNECTOR_H__
+#define __CONNECTOR_H__
+
+#include "SysConnectors.h"
+#include <stdint.h>
+
+
+#ifdef __cplusplus
+namespace ClearCore {
+
+/**
+    \class Connector
+    \brief Base class for interacting with all ClearCore connector objects.
+
+    This virtual class defines the common functionality for a connector object.
+
+    It provides a generic interface that all connectors have. This includes
+    - Connector Type
+    - Generic integer "state"
+    - A Refresh function to force the reading of the underlying information
+    and perform ancillary work such as scheduling and LED display update.
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+
+class Connector {
+    friend class SysManager;
+
+public:
+    /**
+        \enum ConnectorModes
+
+        \brief All possible operational modes for a connector.
+
+        \note Each type of connector supports only a limited subset of these
+        modes.
+    **/
+    typedef enum {
+        /**
+            [0] An invalid default mode.
+        **/
+        INVALID_NONE,
+        /**
+            [1] Analog input mode.
+                \note This is the default mode setting for connectors A-9
+                through A-12.
+        **/
+        INPUT_ANALOG,
+        /**
+            [2] Digital input mode.
+            \note This is the default mode setting for connectors IO-0 through
+            DI-8, and all pins on attached CCIO-8 expansion boards.
+        **/
+        INPUT_DIGITAL,
+        /**
+            [3] Analog current source output mode.
+        **/
+        OUTPUT_ANALOG,
+        /**
+            [4] Digital output mode.
+        **/
+        OUTPUT_DIGITAL,
+        /**
+            [5] H-Bridge mode, using differential PWM output.
+        **/
+        OUTPUT_H_BRIDGE,
+        /**
+            [6] Periodic digital output mode, using pulse-width modulation (PWM)
+        **/
+        OUTPUT_PWM,
+        /**
+            [7] Tone generation mode, using H-Bridge's differential PWM output
+            with tone generation features enabled.
+        **/
+        OUTPUT_TONE,
+        /**
+            [8] Audio generation mode, playing a wave file from a flash drive.
+        **/
+        OUTPUT_WAVE,
+        /**
+            [9] ClearPath&trade; motor controller mode, compatible with
+            operational modes that require user's direct control of the A and B
+            input signals.
+        **/
+        CPM_MODE_A_DIRECT_B_DIRECT,
+        /**
+            [10] ClearPath&trade; motor controller mode, compatible with Step
+            and Direction operational modes.
+        **/
+        CPM_MODE_STEP_AND_DIR,
+        /**
+            [11] ClearPath&trade; motor controller mode, compatible with
+            operational modes where A is controlled by the user directly and B
+            is controlled with a PWM signal (e.g., the Follow Digital Torque,
+            Velocity, and/or Position commands).
+        **/
+        CPM_MODE_A_DIRECT_B_PWM,
+        /**
+            [12] ClearPath&trade; motor controller mode, compatible with Follow
+            Digital Velocity: Bipolar PWM Command with Variable Torque
+            operational mode where both inputs A and B are controlled with PWM
+            signals.
+        **/
+        CPM_MODE_A_PWM_B_PWM,
+        /**
+            [13] Serial port mode, using standard TTL levels compatible with
+            USB Serial Bridges.
+        **/
+        TTL,
+        /**
+            [14] Serial port mode, using inverted TTL levels to allow direct
+            RS232 connections for ports tolerant of the lack of negative
+            voltages.
+        **/
+        RS232,
+        /**
+            [15] Serial port mode, using the port in SPI mode for connections
+            to serial devices using this format.
+        **/
+        SPI,
+        /**
+            [16] Serial port mode for CCIO-8 connections.
+        **/
+        CCIO,
+        /**
+            [17] Serial port mode for USB.
+        **/
+        USB_CDC
+    } ConnectorModes;
+
+    /**
+        \enum ConnectorTypes
+
+        \brief The different types of ClearCore connectors.
+    **/
+    typedef enum {
+        /**
+            [0] Digital input connector.
+
+            This connector has the following features:
+            - Optional majority filtering
+            - TTL or 24V input compatibility
+
+            Connectors of this type:
+            - ConnectorDI6
+            - ConnectorDI7
+            - ConnectorDI8
+        **/
+        DIGITAL_IN_TYPE,
+        /**
+            [1] Digital input/output connector.
+
+            This connector has the following features:
+            - Optional majority input filtering
+            - TTL or 24V input compatibility
+            - High power digital output
+
+            Connectors of this type:
+            - ConnectorIO1
+            - ConnectorIO2
+            - ConnectorIO3
+        **/
+        DIGITAL_IN_OUT_TYPE,
+        /**
+            [2] Virtual connector to access LED and configuration shift register
+        **/
+        SHIFT_REG_TYPE,
+        /**
+            [3] Analog and digital input connector.
+
+            This connector supports the following features:
+            - Optional majority input filtering
+            - TTL or 24V input compatibility
+            - 0-10V analog input measurements
+
+            Connectors of this type:
+            - ConnectorA9
+            - ConnectorA10
+            - ConnectorA11
+            - ConnectorA12
+        **/
+        ANALOG_IN_DIGITAL_IN_TYPE,
+        /**
+            [4] Digital input/output and analog output connector.
+
+            This connector supports the following features:
+            - Optional majority input filtering
+            - TTL or 24V input compatibility
+            - High power digital output
+            - 0-20mA analog current output
+
+            Connectors of this type:
+            - ConnectorIO0
+        **/
+        ANALOG_OUT_DIGITAL_IN_OUT_TYPE,
+        /**
+            [5] H-Bridge connector.
+
+            Utilizing V+ and IO pin as a pair these connectors can be setup
+            to:
+            - Drive a motor
+            - Create tones to drive a speaker
+            - Create bi-directional output via PWM
+
+            Connectors of this type:
+            - ConnectorIO4
+            - ConnectorIO5
+
+            \see DIGITAL_IN_OUT_TYPE
+        **/
+        H_BRIDGE_TYPE,
+        /**
+            [6] ClearPath&trade; motor connector.
+
+            This connector can control a ClearPath&trade; motor. Some of the
+            control abilities available include:
+            - Motor Enable
+            - Step+Direction Move Generation
+            - Control of the A and B inputs for use with the MC models.
+            - Reading of the HLFB from ClearPath motors.
+
+            Connectors of this type:
+            - ConnectorM0
+            - ConnectorM1
+            - ConnectorM2
+            - ConnectorM3
+        **/
+        CPM_TYPE,
+        /**
+            [7] Serial port connector.
+
+            These connectors can:
+            - be used as asynchronous serial ports with selectable baud rate and
+              data formats.
+            - be used as SPI master ports.
+
+            Connectors of this type:
+            - ConnectorCOM0
+            - ConnectorCOM1
+        **/
+        SERIAL_TYPE,
+        /**
+            [8] Serial USB connector.
+
+            These connectors can:
+            - be used as asynchronous serial ports.
+
+            Connectors of this type:
+            - ConnectorUsb
+        **/
+        SERIAL_USB_TYPE,
+        /**
+            [9] ClearCore I/O Expansion Board digital I/O connector.
+
+            This connector has the following features:
+            - Optional majority input filtering
+            - TTL or 24V input compatibility
+        **/
+        CCIO_DIGITAL_IN_OUT_TYPE,
+    } ConnectorTypes;
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorIO0.Mode() == Connector::OUTPUT_ANALOG) {
+            // IO-0 is currently an analog output.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() {
+        return m_mode;
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \code{.cpp}
+        // Set IO-0's mode to be an analog output
+        ConnectorIO0.Mode(Connector::OUTPUT_ANALOG);
+        \endcode
+
+        \param[in] newMode The new mode to be set.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    virtual bool Mode(ConnectorModes newMode) = 0;
+
+    /**
+        \brief Get the connector type.
+
+        \code{.cpp}
+        if (ConnectorIO1.Type() == DIGITAL_IN_OUT_TYPE) {
+            // IO-1 is a DigitalInOut
+        }
+        \endcode
+
+        \return Return the connector type for generic handling of connectors.
+    **/
+    virtual ConnectorTypes Type() = 0;
+
+    /**
+        \brief Determine whether values can be written to this connector.
+
+        \code{.cpp}
+        if (!ConnectorIO1.IsWritable()) {
+            // IO-1 is not currently set as an output
+        }
+        \endcode
+
+        \return true if this connector is writable, false if this connector is
+        read-only.
+    **/
+    virtual bool IsWritable() = 0;
+
+    /**
+        \brief Reinitialize this connector to the power-up state.
+
+        \code{.cpp}
+        // IO-1 needs to be re-initialized
+        ConnectorIO1.Reinitialize();
+        \endcode
+
+        \note Connectors IO-0 through DI-8 and all CCIO-8 connectors will be
+        set into #INPUT_DIGITAL mode, while connectors A-9 through A-12 will be
+        set into #INPUT_ANALOG mode, the default modes for these connectors.
+    **/
+    void Reinitialize() {
+        Initialize(m_clearCorePin);
+    }
+
+    /**
+        \brief Accessor for the bit index of this connector in the input
+        register.
+
+        \code{.cpp}
+        // Save IO-1's index for future use
+        int32_t io1Index = ConnectorIO1.ConnectorIndex();
+        \endcode
+
+        \return The connector bit index in the input register
+    **/
+    int32_t ConnectorIndex() {
+        return m_clearCorePin;
+    }
+
+    /**
+        \brief Get the connector's last sampled value.
+
+        Return the current "value" for this connector. For connectors with
+        more than one input or output the value returned here would depend
+        on the specific connector. Access to this information would need
+        to be provided by the implementation object.
+
+        For boolean items, this will return the values of C++ true and false.
+        For analog items, this could be the RAW or processed ADC value, etc.
+
+        \code{.cpp}
+        if (ConnectorIO0.State()) {
+            // IO-0's input is currently high
+        }
+        \endcode
+
+        \return The latest sample.
+    **/
+    virtual int16_t State() = 0;
+
+    /**
+        \brief Set the state of a R/W connector.
+
+        For read-write objects, this allows you to change the state of the
+        connector item.
+
+        \code{.cpp}
+        // Set IO-0's output to high
+        ConnectorIO0.State(1);
+        \endcode
+
+        \param[in] newState For mutable items, update the output.
+    **/
+    virtual bool State(int16_t newState) = 0;
+
+    /**
+        \brief Get whether the connector is in a hardware fault state.
+
+        \code{.cpp}
+        if (ConnectorIO1.IsInHwFault()) {
+            // IO-1 is in a fault state
+        }
+        \endcode
+
+        \return True if the connector is in fault; false otherwise.
+    **/
+    virtual bool IsInHwFault() = 0;
+
+    /**
+        \brief Get a bit mask representing this connector.
+
+        \code{.cpp}
+        // Create a SysConnectorState mask to check IO-1
+        SysConnectorState stateMask(ConnectorIO1.InputRegMask());
+
+        // Save whether IO-1 has risen
+        SysConnectorState risenInputs = InputMgr.InputsRisen(stateMask);
+        \endcode
+
+        \return A 32-bit mask of 0's, with a single 1 at the bit position of
+        this connector's index. (See #ClearCorePins to determine connector
+        indices.)
+    **/
+    uint32_t InputRegMask() {
+        return (m_clearCorePin < 0) ? 0 : (1 << m_clearCorePin);
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief This connector's external interrupt line index.
+
+        \note A value of -1 denotes that the connector has no external
+        interrupt available.
+    **/
+    virtual int8_t ExternalInterrupt() {
+        return -1;
+    }
+#endif
+
+protected:
+    /**
+        Pin for referencing ClearCore pin.
+
+        Set in Initialize().
+
+        Used to communicate with SysManager when the
+        Connector's index is required.
+    **/
+    ClearCorePins m_clearCorePin;
+
+    /**
+        Current mode for the connector.
+    **/
+    ConnectorModes m_mode;
+
+    /// Construct a connector
+    Connector();
+
+    /**
+        \brief Update the connector's state.
+
+        Poll the underlying connector for new state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    virtual void Refresh() = 0;
+
+    /**
+        \brief Initialize this connector to a "safe" and inert state.
+
+        \param[in] clearCorePin The connector bit index in the input register.
+    **/
+    virtual void Initialize(ClearCorePins clearCorePin) = 0;
+
+}; // Connector
+
+} // ClearCore namespace
+#endif // __cplusplus
+
+#endif // __CONNECTOR_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalIn.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalIn.h
new file mode 100644
index 000000000..cf082652a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalIn.h
@@ -0,0 +1,418 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file DigitalIn.h
+
+    \brief ClearCore Digital Input Connector class.
+**/
+
+#ifndef __DIGITALIN_H__
+#define __DIGITALIN_H__
+
+#include <stdint.h>
+#include "Connector.h"
+#include "InputManager.h"
+#include "PeripheralRoute.h"
+#include "ShiftRegister.h"
+
+namespace ClearCore {
+
+/**
+    Pointer to a function that takes no parameters and returns nothing.
+**/
+typedef void (*voidFuncPtr)(void);
+
+/**
+    \class DigitalIn
+
+    \brief ClearCore digital input connector class.
+
+    This manages a digital input connector on the ClearCore board.
+
+    The following connector instances support digital input functionality:
+    - #ConnectorIO0
+    - #ConnectorIO1
+    - #ConnectorIO2
+    - #ConnectorIO3
+    - #ConnectorIO4
+    - #ConnectorIO5
+    - #ConnectorDI6
+    - #ConnectorDI7
+    - #ConnectorDI8
+    - #ConnectorA9
+    - #ConnectorA10
+    - #ConnectorA11
+    - #ConnectorA12
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class DigitalIn : public Connector {
+    friend class SysManager;
+    friend class TestIO;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Default constructor so this connector can be a global and constructed
+        by SysManager
+
+        \note Should not be called by anything other than SysManager
+    **/
+    DigitalIn() {};
+#endif
+
+    /**
+        \enum FilterUnits
+        \brief Units for the digital filter length.
+
+        \note One sample time is 200 microseconds, so 1 ms = 5 sample times.
+    **/
+    typedef enum {
+        /** Milliseconds. **/
+        FILTER_UNIT_MS,
+        /** Sample times. **/
+        FILTER_UNIT_SAMPLES,
+    } FilterUnits;
+
+    /**
+        \brief Set the connector's digital transition filter length.
+        The default digital filter length for digital input connectors is 3
+        samples.
+
+        This will set the length, in samples (default) or milliseconds, of the
+        connector's transition filter and restarts any filtering in progress.
+
+        \code{.cpp}
+        // Sets DI-6's filter to 20 samples (4ms)
+        ConnectorDI6.FilterLength(20);
+        \endcode
+
+        \code{.cpp}
+        // Sets DI-6's filter to 10ms (50 samples)
+        ConnectorDI6.FilterLength(10, DigitalIn::FILTER_UNIT_MS);
+        \endcode
+
+        \note One sample time is 200 microseconds.
+
+        \param[in] length The length of the filter.
+        \param[in] units The units of the specified filter length: samples
+        (default) or milliseconds.
+    **/
+    void FilterLength(uint16_t length,
+                      FilterUnits units = FILTER_UNIT_SAMPLES) {
+        // 1 ms = 1000 us = 5 * (200 us) = 5 sample times
+        uint16_t samples = (units == FILTER_UNIT_MS) ? 5 * length : length;
+        m_filterLength = samples;
+        m_filterTicksLeft = samples;
+    }
+
+    /**
+        \brief Get the connector's digital filter length in samples. The default
+        is 3 samples.
+
+        This will get the length, in samples, of the connector's filter.
+
+        \code{.cpp}
+        if (ConnectorDI6.FilterLength() > 5) {
+            // DI6's filter length is greater than 5 samples (1ms), do something
+        }
+        \endcode
+
+        \note One sample time is 200 microseconds.
+
+        \return The length of the digital input filter in samples.
+    **/
+    uint16_t FilterLength() {
+        return m_filterLength;
+    }
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorDI6.Mode() == Connector::INPUT_DIGITAL) {
+            // DI-6 is currently a digital input.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \param[in] newMode The new mode to be set.
+        The only valid mode for this connector type is: #INPUT_DIGITAL.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    virtual bool Mode(ConnectorModes newMode) override {
+        if (newMode == ConnectorModes::INPUT_DIGITAL) {
+            m_mode = newMode;
+            return true;
+        }
+        else {
+            return false;
+        }
+    }
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() == Connector::DIGITAL_IN_TYPE) {
+            // This generic connector variable is a DigitalIn connector
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::DIGITAL_IN_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (!ConnectorAlias.IsWritable()) {
+            // This generic connector is not an output
+        }
+        \endcode
+
+        \return False because the connector is read-only.
+    **/
+    bool IsWritable() override {
+        return false;
+    }
+
+    /**
+        \brief Get the connector's last majority-filtered sampled value.
+
+        \code{.cpp}
+        if (ConnectorDI6.State()) {
+            // DI-6's input is currently high
+        }
+        \endcode
+
+        \return The latest filtered value on this connector.
+
+        \note If the filter length is set to 0, this will return the real-time
+        value from the hardware register instead (see
+        #FilterLength(uint16_t samples)).
+    **/
+    int16_t State() override;
+
+#ifndef HIDE_FROM_DOXYGEN
+
+    /**
+        \brief Get the connector's real time input value.
+
+        \return The current value on this connector.
+    **/
+    int16_t StateRT();
+
+    /**
+        \brief Set the state of a R/W connector.
+
+        For read-write objects, this allows you to change the state of the
+        connector item.
+
+        \param[in] newState For mutable items, update the output.
+
+        \note Does nothing since digital input connectors have no output
+        capability.
+    **/
+    bool State(int16_t newState) override {
+        (void)newState;
+        return false;
+    }
+#endif
+
+    /**
+        \brief Clear on read accessor for this connector's rising input state.
+
+        \code{.cpp}
+        if (ConnectorDI7.InputRisen()) {
+            // DI-7 rising edge detected since the last call
+        }
+        \endcode
+
+        \return true if the input has risen since the last call
+    **/
+    bool InputRisen();
+
+    /**
+        \brief Clear on read accessor for this connector's falling input state.
+
+        \code{.cpp}
+        if (ConnectorDI7.InputFallen()) {
+            // DI-7 falling edge detected since the last call
+        }
+        \endcode
+
+        \return true if the input has fallen since the last call
+    **/
+    bool InputFallen();
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \copydoc Connector::IsInHwFault()
+        \note Since this connector can only be configured as an input,
+        a fault state is not possible and so this function will always
+        return false.
+    **/
+    bool IsInHwFault() override {
+        return false;
+    }
+
+    /**
+        \brief This connector's external interrupt line index.
+
+        \note A value of -1 denotes that the connector has no external
+        interrupt available.
+    **/
+    int8_t ExternalInterrupt() override {
+        return m_extInt;
+    }
+#endif
+
+    /**
+        \brief Register the interrupt service routine to be triggered when the
+        given input state condition is met on this connector.
+
+        \code{.cpp}
+        // Signature for interrupt service routine (ISR)
+        void myCallback();
+
+        void setup() {
+            // Set an interrupt service routine (ISR) to be called when the
+            // state of the interrupt connector goes from TRUE to FALSE.
+            InterruptConnector.InterruptHandlerSet(&myCallback,
+                                                   InputManager::FALLING);
+
+            // Enable digital interrupts.
+            InputMgr.InterruptsEnabled(true);
+        }
+
+        // The function to be triggered on an interrupt.
+        // This function blinks the user-controlled LED once.
+        void myCallback() {
+            ConnectorLed.State(true);
+            Delay_ms(100);
+            ConnectorLed.State(false);
+            Delay_ms(100);
+        }
+        \endcode
+
+        \param[in] callback The ISR to be called when the interrupt is triggered
+        \param[in] trigger The input state condition on which to trigger the
+        interrupt.
+        \param[in] enable Whether this interrupt should be immediately enabled.
+        \return true if the ISR was registered successfully, false otherwise.
+
+        \note Only connectors DI-6 through A-12 can trigger interrupts.
+    **/
+    bool InterruptHandlerSet(voidFuncPtr callback = nullptr,
+                             InputManager::InterruptTrigger trigger =
+                                 InputManager::InterruptTrigger::RISING,
+                             bool enable = true);
+
+    /**
+        \brief Enable or disable the interrupt on this connector.
+
+        \code{.cpp}
+        // Enable interrupts on DI-6
+        ConnectorDI6.InterruptEnable(true);
+        \endcode
+
+        \param[in] enable If true, enable the interrupt. If false, disable the
+        interrupt.
+
+        \note Only connectors DI-6 through A-12 can trigger interrupts.
+        \note InputManager has a global version of this function that enables
+        or disables the interrupts for all connectors.
+    **/
+    void InterruptEnable(bool enable);
+
+protected:
+    // LED associated with input
+    ShiftRegister::Masks m_ledMask;
+
+    // Register that contains the digital input
+    uint32_t m_inputPort;
+    uint32_t m_inputDataBit;
+    uint32_t m_inputDataMask;
+
+    // External interrupts
+    uint8_t m_extInt;        // External interrupt line index
+    bool m_interruptAvail;   // An external interrupt is available on this input
+
+    uint32_t *m_changeRegPtr;
+    uint32_t *m_inRegPtr;
+    uint32_t *m_inputRegRTPtr;
+
+    // Boolean state holders
+    bool m_stateFiltered;
+
+    // Stability filter
+    uint16_t m_filterLength;
+    // Set to filter length on input state change
+    uint16_t m_filterTicksLeft;
+
+    /**
+        Construct, wire in pads and LED shift register object.
+    **/
+    DigitalIn(enum ShiftRegister::Masks ledMask,
+              const PeripheralRoute *inputInfo);
+
+    /**
+        \brief Update the connector's state.
+
+        Poll the underlying connector for a state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+
+        \return Updated filtered internal state.
+    **/
+    void Refresh() override;
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+
+    /**
+        Set the filtered pin value to the current input register state.
+    **/
+    void UpdateFilterState();
+
+}; // DigitalIn
+
+} // ClearCore namespace
+
+#endif // __DIGITALIN_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInAnalogIn.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInAnalogIn.h
new file mode 100644
index 000000000..62414aff3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInAnalogIn.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file DigitalInAnalogIn.h
+    \brief Connector class for analog and digital inputs.
+**/
+#ifndef __DIGITALINANALOGIN_H__
+#define __DIGITALINANALOGIN_H__
+
+#include <stdint.h>
+#include <sam.h>
+#include "AdcManager.h"
+#include "Connector.h"
+#include "DigitalIn.h"
+#include "IirFilter.h"
+#include "PeripheralRoute.h"
+#include "ShiftRegister.h"
+
+namespace ClearCore {
+
+/**
+    \class DigitalInAnalogIn
+
+    \brief ClearCore analog input connector class.
+
+    This manages an analog input connector on the ClearCore board. This
+    connector can also be configured as a digital input.
+
+    The following connector instances support analog input functionality:
+    - #ConnectorA9
+    - #ConnectorA10
+    - #ConnectorA11
+    - #ConnectorA12
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class DigitalInAnalogIn : public DigitalIn {
+    friend class SysManager;
+
+public:
+    /**
+        Default value for the analog input filter time constant:
+        2 milliseconds.
+    **/
+    static const uint16_t ANALOG_INPUT_FILTER_TC_MS_DEFAULT = 2;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Default constructor so this connector can be a global and constructed
+        by SysManager
+
+        \note Should not be called by anything other than SysManager
+    **/
+    DigitalInAnalogIn() {};
+#endif
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorA9.Mode() == Connector::INPUT_ANALOG) {
+            // A-9 is currently an analog input.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        Set the connector up in the given mode by setting the control bits
+        appropriately; also reset the analog filter to the current value if
+        setting up for analog mode.
+
+        \code{.cpp}
+        // Set A-9's mode to be an analog input
+        ConnectorA9.Mode(Connector::INPUT_ANALOG);
+        \endcode
+
+        \param[in] newMode The new mode to be set.
+        The valid modes for this connector type are:
+        - #INPUT_DIGITAL
+        - #INPUT_ANALOG.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    bool Mode(ConnectorModes newMode) override;
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() == Connector::ANALOG_IN_DIGITAL_IN_TYPE) {
+            // This generic connector variable is a DigitalInAnalogIn connector
+        }
+        \endcode
+
+        \return The type of this connector (Analog Input)
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::ANALOG_IN_DIGITAL_IN_TYPE;
+    }
+
+    /**
+        \brief Is this connector able to be written to?
+
+        \code{.cpp}
+        if (!ConnectorAlias.IsWritable()) {
+            // This generic connector is not an output
+        }
+        \endcode
+
+        \return False since this is a read-only connector.
+    **/
+    bool IsWritable() override {
+        return false;
+    }
+
+    /**
+        \brief Set the time constant for the analog input filter.
+
+        Set the time constant of the analog filter to the given value.
+
+        \code{.cpp}
+        // Set A-9's filter time constant to be 10ms
+        ConnectorA9.FilterTc(10, AdcManager::FilterUnits::FILTER_UNIT_MS);
+        \endcode
+
+        \param[in] tc The time constant to use for the analog filter.
+        \param[in] theUnits The units of the time constant \a tc.
+        See AdcManager#FilterUnits.
+
+        \return success
+    **/
+    bool FilterTc(uint16_t tc, AdcManager::FilterUnits theUnits);
+
+    /**
+        \brief Get the connector's last majority-filtered sampled value.
+
+        In digital input mode, return the last filtered digital input state.
+        When in analog input mode, return the last filtered input value.
+
+        \code{.cpp}
+        // Saves A-9's current sampled analog (or digital) input reading
+        int16_t analogReading = ConnectorA9.State();
+        \endcode
+
+        \return The latest filtered value.
+    **/
+    int16_t State() override;
+
+    /**
+        \brief Returns the analog voltage of the connector in volts.
+
+        \code{.cpp}
+        // Saves A-9's current sampled analog input reading in volts
+        float analogReadingV = ConnectorA9.AnalogVoltage();
+        \endcode
+
+        \return The filtered analog input voltage in volts
+    **/
+    float AnalogVoltage() {
+        // If there is not a valid reading available, return zero.
+        if (!m_analogValid) {
+            return 0;
+        }
+        return AdcManager::Instance().AnalogVoltage(m_adcChannel);
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Set the state of a R/W connector.
+
+        Since this is a read-only connector, setting the State has no effect.
+
+        \param[in] newState Does nothing.
+
+        \return failure
+    **/
+    bool State(int16_t newState) override {
+        // ignore attempts to write state
+        (void)newState;
+        return false;
+    }
+#endif
+private:
+    // Control bit for the analog input circuit
+    ShiftRegister::Masks m_modeControlBitMask;
+
+    AdcManager::AdcChannels m_adcChannel;
+
+    volatile const uint16_t *m_adcResultConvertedPtr;
+    volatile const uint16_t *m_adcResultConvertedFilteredPtr;
+    volatile bool m_analogValid;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct, wire in pads and LED Shift register object
+    **/
+    DigitalInAnalogIn(enum ShiftRegister::Masks ledMask,
+                      enum ShiftRegister::Masks modeControlMask,
+                      const PeripheralRoute *inputInfo,
+                      AdcManager::AdcChannels adcChannel);
+#endif
+
+    /**
+        \brief Update connector's state.
+
+        Poll the underlying connector for new state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    void Refresh() override;
+
+    /**
+        Reset the analog values, set up the digital input, and
+        default to digital input mode.
+
+        \param[in] clearCorePin The pin to initialize the connector on.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+
+}; // DigitalInAnalogIn
+
+} // ClearCore namespace
+
+#endif // __ANALOGINDIGITALIN_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOut.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOut.h
new file mode 100644
index 000000000..dd1ad65d8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOut.h
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file DigitalInOut.h
+
+    \brief ClearCore Digital Output Connector class
+**/
+
+#ifndef __DIGITALINOUT_H__
+#define __DIGITALINOUT_H__
+
+#include <stdint.h>
+#include <sam.h>
+#include "Connector.h"
+#include "DigitalIn.h"
+#include "ShiftRegister.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+/**
+    \class DigitalInOut
+
+    \brief ClearCore digital output connector class.
+
+    This manages a digital output connector on the ClearCore board. This
+    connector can also be configured as a digital input.
+
+    The following connector instances support digital output functionality:
+    - #ConnectorIO0
+    - #ConnectorIO1
+    - #ConnectorIO2
+    - #ConnectorIO3
+    - #ConnectorIO4
+    - #ConnectorIO5
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class DigitalInOut : public DigitalIn {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Default constructor so this connector can be a global and constructed
+        by SysManager
+
+        \note Should not be called by anything other than SysManager
+    **/
+    DigitalInOut() {};
+#endif
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorIO1.Mode() == Connector::OUTPUT_DIGITAL) {
+            // IO-1 is currently a digital output.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \code{.cpp}
+        // Set IO-1's mode to be an output configured to produce PWM signals
+        ConnectorIO1.Mode(Connector::OUTPUT_PWM);
+        \endcode
+
+        \param[in] newMode The new mode to be set.
+        The valid modes for this connector type are:
+        - #INPUT_DIGITAL
+        - #OUTPUT_DIGITAL
+        - #OUTPUT_PWM.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    virtual bool Mode(ConnectorModes newMode) override;
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() == Connector::DIGITAL_IN_OUT_TYPE) {
+            // This generic connector variable is a DigitalInOut connector
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::DIGITAL_IN_OUT_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (ConnectorIO1.IsWritable()) {
+            // IO-1 is in an output mode
+        }
+        \endcode
+
+        \return True if in #OUTPUT_DIGITAL or #OUTPUT_PWM mode, false otherwise.
+    **/
+    bool IsWritable() override {
+        return m_mode == OUTPUT_DIGITAL || m_mode == OUTPUT_PWM;
+    }
+
+    /**
+        \brief Get the connector's last majority-filtered sampled value.
+
+        \code{.cpp}
+        // In this example, IO-1 has been configured for digital input
+        if (ConnectorIO1.State()) {
+            // IO-1's input is currently high
+        }
+        \endcode
+
+        \code{.cpp}
+        // In this example, IO-1 has been configured for PWM output
+        if (ConnectorIO1.State() > UINT8_MAX / 2) {
+            // IO-1 is outputting PWM at a duty cycle greater than 50%
+        }
+        \endcode
+
+        \return The latest filtered value on this connector.
+
+        \note If the filter length is set to 0, this will return the real-time
+        value from the hardware register instead (see
+        #FilterLength(uint16_t samples)).
+    **/
+    int16_t State() override;
+
+    /**
+        \brief Set the output state of the connector.
+
+        This allows you to change the output value of the connector item.
+
+        \code{.cpp}
+        // Configure IO-1 for digital output mode
+        ConnectorIO1.Mode(Connector::OUTPUT_DIGITAL);
+        // Set IO-1's output to high
+        ConnectorIO1.State(1);
+        \endcode
+
+        \code{.cpp}
+        // Configure IO-1 for PWM output mode
+        ConnectorIO1.Mode(Connector::OUTPUT_PWM);
+        // Set IO-1 to output a PWM wave with 25% duty cycle
+        ConnectorIO1.State(UINT8_MAX / 4);
+        \endcode
+
+        \param[in] newState The value to be output.
+    **/
+    bool State(int16_t newState) override;
+
+    /**
+        \copydoc Connector::IsInHwFault()
+    **/
+    bool IsInHwFault() override {
+        return (volatile bool &)m_isInFault;
+    }
+
+    /**
+        \brief Start an output pulse.
+
+        This allows you to start a pulse on the output that is on for \a onTime
+        milliseconds and off for \a offTime milliseconds and will stop after
+        \a pulseCount cycles. A \a pulseCount of 0 will cause the pulse to run
+        endlessly. If a pulse is already running, calling this will allow you
+        to override the previous pulse (after the next change in state).
+
+        \code{.cpp}
+        // Begin a 100ms on/200ms off pulse on IO-1's output that will complete
+        // 20 cycles and prevent further code execution until the cycles are
+        // complete
+        ConnectorIO1.OutputPulsesStart(100, 200, 20, true);
+        \endcode
+
+        \param[in] onTime The amount of time the input will be held on [ms].
+        \param[in] offTime The amount of time the input will be held off [ms].
+        \param[in] pulseCount (optional) The amount of cycles the pulse will
+        run for. Default: 0 (pulse runs endlessly).
+        \param[in] blockUntilDone (optional) If true, the function call will
+        wait until \a pulseCount pulses have been sent before returning.
+        Default: false.
+    **/
+    void OutputPulsesStart(uint32_t onTime, uint32_t offTime,
+                           uint16_t pulseCount = 0,
+                           bool blockUntilDone = false);
+
+    /**
+        \brief Stop an output pulse.
+
+        This allows you to stop the currently running pulse on this output. The
+        output will always be set to FALSE after canceling a pulse.
+
+        \code{.cpp}
+        // Stop the active output pulse on IO-1
+        ConnectorIO1.OutputPulsesStop();
+        \endcode
+
+        \param[in] stopImmediately (optional) If true, the output pulses will
+        be stopped immediately; if false, any active pulse will be completed
+        first. Default: true.
+    **/
+    void OutputPulsesStop(bool stopImmediately = true);
+
+    /**
+        \brief Check the output pulse state.
+
+        This allows you to see if there is a currently running pulse on this
+        output.
+
+        \code{.cpp}
+        if (ConnectorIO1.OutputPulsesActive()) {
+            // IO-1 is outputting pulses
+        }
+        \endcode
+
+        \return True if output pulses are currently active.
+    **/
+    volatile const bool &OutputPulsesActive() {
+        return m_pulseActive;
+    }
+
+    /**
+        \brief Set the PWM duty on the I/O pin.
+
+        The pin must be in #OUTPUT_PWM mode, or else nothing will happen and
+        this function will return false.
+
+        \code{.cpp}
+        // Configure IO-1 for PWM output
+        ConnectorIO1.Mode(Connector::OUTPUT_PWM);
+        // Set the PWM output signal on IO-1 to be asserted 25% of the time
+        ConnectorIO1.PwmDuty(UINT8_MAX / 4);
+        \endcode
+
+        \param[in] newDuty The PWM duty cycle for the pin, from 0 to
+        255 (UINT8_MAX).
+
+        \return Successfully set the PWM duty value.
+    **/
+    bool PwmDuty(uint8_t newDuty);
+
+protected:
+    // Port access
+    uint32_t m_outputPort;
+    uint32_t m_outputDataBit;
+    uint32_t m_outputDataMask;
+    bool m_logicInversion;
+
+    bool m_isInFault;
+
+    Tc *m_tc;
+    uint8_t m_tcPadNum;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct and wire in the Input/Output pair.
+    **/
+    DigitalInOut(enum ShiftRegister::Masks ledMask,
+                 const PeripheralRoute *inputInfo,
+                 const PeripheralRoute *outputInfo,
+                 bool logicInversion);
+
+    /**
+        \brief Update connector's state.
+
+        Poll the underlying connector for new state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    void Refresh() override;
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+#endif
+private:
+    bool m_outState;
+    // Pulse control variables
+    uint32_t m_pulseOnTicks;
+    uint32_t m_pulseOffTicks;
+    uint32_t m_pulseStart;
+    uint16_t m_pulseStopCount;
+    uint16_t m_pulseCounter;
+    uint8_t m_overloadTripCnt;
+    bool m_pulseActive;
+    bool m_pulseValue;
+    bool m_pulseStopPending;
+    uint16_t m_overloadFoldbackCnt;
+
+    void OutputPin(bool val) {
+        DATA_OUTPUT_STATE(m_outputPort, m_outputDataMask,
+                          val != m_logicInversion);
+    }
+
+    /**
+        \brief Sets whether the connector is in a hardware fault state.
+
+        \param[in] inFault Fault state to set
+    **/
+    void IsInHwFault(bool inFault);
+};
+
+} // ClearCore namespace
+
+#endif // __DIGITALINOUT_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOutAnalogOut.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOutAnalogOut.h
new file mode 100644
index 000000000..c4ff6cff3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOutAnalogOut.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file DigitalInOutAnalogOut.h
+
+    \brief ClearCore Analog Output Connector class
+**/
+
+#ifndef __DIGITALINOUTANALOGOUT_H__
+#define __DIGITALINOUTANALOGOUT_H__
+
+#include <stdint.h>
+#include "Connector.h"
+#include "DigitalInOut.h"
+#include "PeripheralRoute.h"
+#include "ShiftRegister.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore digital input/output with analog current output
+    Connector class.
+
+    This manages an analog output connector on the ClearCore board. This
+    connector can also be configured as a digital output or digital input.
+
+    The following connector instances support analog output functionality:
+    - #ConnectorIO0
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class DigitalInOutAnalogOut : public DigitalInOut {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager
+
+        \note Should not be called by anything other than SysManager
+    **/
+    DigitalInOutAnalogOut() {};
+#endif
+
+    /**
+        \copydoc Connector::Mode
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set connector's operational mode.
+
+        \code{.cpp}
+        // Set IO-0's mode to be an analog output
+        ConnectorIO0.Mode(Connector::OUTPUT_ANALOG);
+        \endcode
+
+        \param[in] newMode The new operational mode to be set.
+        The valid modes for this connector type are:
+        - #INPUT_DIGITAL
+        - #OUTPUT_DIGITAL
+        - #OUTPUT_PWM
+        - #OUTPUT_ANALOG.
+        \return True if the mode change was successful.
+    **/
+    bool Mode(ConnectorModes newMode) override;
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() ==
+                Connector::ANALOG_OUT_DIGITAL_IN_OUT_TYPE) {
+            // This generic connector variable is a DigitalInOutAnalogOut
+            // connector
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::ANALOG_OUT_DIGITAL_IN_OUT_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (ConnectorIO0.IsWritable()) {
+            // IO-0 is in output mode
+        }
+        \endcode
+
+        \return False if the connector is read-only.
+    **/
+    bool IsWritable() override;
+
+    /**
+        \brief Get connector's last sampled digital value.
+
+        In digital modes, return the current digital state; in analog
+        output mode, returns 0.
+
+        \code{.cpp}
+        if (ConnectorIO0.State()) {
+            // IO-0's input is currently high
+        }
+        \endcode
+
+        \return 0 when in analog output mode; the current digital state
+                otherwise
+    **/
+    int16_t State() override;
+
+    /**
+        \brief Set the output value of the connector.
+
+        When in digital modes, set the digital output value via DigitalInOut
+        class. When in analog output mode, write the analog value out. Valid
+        analog values are unsigned 11-bit integers, where 0 corresponds to 0 mA
+        (minimum current output) and 2047 corresponds to 20 mA (maximum current
+        output).
+
+        \code{.cpp}
+        // Configure IO-0 for analog output
+        ConnectorIO0.Mode(Connector::OUTPUT_ANALOG);
+        // Write a (scaled) analog value to IO-0's output
+        ConnectorIO0.State(50);
+        \endcode
+
+        \param[in] newState The value to be output
+    **/
+    bool State(int16_t newState) override;
+
+    /**
+        \brief Command the DAC to output a (calibrated) value.
+
+        A value of 2047 corresponds to maximum (20 mA) current output, and
+        a value of 0 corresponds to minimum (0 mA) current output.
+
+        \code{.cpp}
+        // Configure IO-0 for analog output
+        ConnectorIO0.Mode(Connector::OUTPUT_ANALOG);
+        // Output the maximum analog voltage to IO-0
+        ConnectorIO0.AnalogWrite(2047);
+        \endcode
+
+        \param[in] value The raw 11-bit DAC value to command analog current.
+    **/
+    void AnalogWrite(uint16_t value);
+
+    /**
+        \brief Command the DAC to output the given number of microamps (uA).
+
+        \code{.cpp}
+        // Configure IO-0 for analog output
+        ConnectorIO0.Mode(Connector::OUTPUT_ANALOG);
+        // Output 5000 uA (5 mA) to IO-0's analog output
+        ConnectorIO0.OutputCurrent(5000);
+        \endcode
+
+        \param[in] currentuA Output current command in microamps (uA).
+    **/
+    void OutputCurrent(uint16_t currentuA);
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief This function should only be used for calibration purposes.
+
+        Command the DAC to output a raw uncalibrated value between 0
+        and 2047. 0 corresponds to the hardware's minimum current output (0 mA),
+        and 2047 corresponds to the hardware's maximum current output (20 mA).
+
+        \param[in] value The raw 11-bit DAC value to command analog current.
+    **/
+    void AnalogWriteUncalibrated(uint16_t value);
+
+    /**
+        \brief Persist the DAC's calibration setting in NVM.
+
+        Warning: Calling this function WILL overwrite any existing ClearCore
+        factory configuration. Improper use of this function will result in
+        poorly calibrated DAC output.
+
+        The \a zero parameter sets the minimum output value, corresponding to
+        minimum current output.
+        The \a span parameter sets the range of valid output values.
+        In essence, the DAC's output is scaled between \a zero  and
+        (\a zero + \a span).
+
+        \param[in] zero The 11-bit zero value (will be clipped if the value
+        exceeds 2047)
+        \param[in] span The 11-bit span value (clipped)
+        \return True if the calibration data is written successfully;
+        false otherwise.
+    **/
+    bool DacStoreCalibration(uint16_t zero, uint16_t span);
+#endif // HIDE_FROM_DOXYGEN
+
+private:
+    uint32_t m_analogPort;
+    uint32_t m_analogDataBit;
+    uint16_t m_dacZero;
+    uint16_t m_dacSpan;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct and wire in the Input/Output pair.
+    **/
+    DigitalInOutAnalogOut(enum ShiftRegister::Masks ledMask,
+                          const PeripheralRoute *inputInfo,
+                          const PeripheralRoute *outputInfo,
+                          const PeripheralRoute *outputAnalogInfo,
+                          bool digitalLogicInversion);
+#endif
+    /**
+        \brief Update connector's state.
+
+        For this connector, the Refresh does nothing when in analog output
+        mode; otherwise, the work is handled by the parent #DigitalInOut class.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    void Refresh() override;
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+
+    /**
+        One-time set up required to use the DAC on #ConnectorIO0.
+        This should be run before #DacEnable() or #DacDisable().
+    **/
+    void DacInitialize();
+
+    /**
+        Command the DAC to start outputting voltage. If the DAC is
+        enabled, other I/O functions on the pin may not behave properly.
+    **/
+    void DacEnable();
+
+    /**
+        Command the DAC to stop outputting voltage. Do this before using
+        other I/O functions on the pin.
+    **/
+    void DacDisable();
+
+    /**
+        Load DAC calibration values (zero, span) from NVM.
+    **/
+    void DacLoadCalibration();
+
+    /**
+        \brief Write a value to the DAC's DATA register.
+
+        Warning: No operations are performed on the input value so use at your
+        own risk, and be sure that \a value does not exceed 2047.
+
+        \param[in] value The 11-bit command to send
+    **/
+    void DacRegisterWrite(uint16_t value);
+
+}; // DigitalInOutAnalogOut class
+
+} // ClearCore namespace
+
+#endif // __ANALOGOUTDIGITALINOUT_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOutHBridge.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOutHBridge.h
new file mode 100644
index 000000000..504362d79
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DigitalInOutHBridge.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file DigitalInOutHBridge.h
+
+    \brief DigitalInOutHBridge Connector class for IO4 and IO5.
+
+    Uses different hardware than the other IO connectors.
+    Utilizes DigitalInOut for Input, Output, Output_PWM.
+    Adds HBridge functionality, such as tone generation.
+    The enable pin on the HBridge chip is treated the same as the output pin
+    for the other connectors.
+**/
+
+#ifndef __DIGITALINOUTHBRIDGE_H__
+#define __DIGITALINOUTHBRIDGE_H__
+
+#include <stdint.h>
+#include "Connector.h"
+#include "DigitalInOut.h"
+#include "PeripheralRoute.h"
+#include "ShiftRegister.h"
+#include "StatusManager.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore H-Bridge digital output connector class.
+
+    This manages a connector on the ClearCore board that supports H-Bridge
+    digital output functionality, including sine tone generation. This connector
+    can also be configured as a digital input or digital output.
+
+    The following connector instances support H-Bridge digital output
+    functionality:
+    - #ConnectorIO4
+    - #ConnectorIO5
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+
+    \note If overloaded, these connectors will need to be reset using the
+    StatusManager::HBridgeReset function. This applies when running in H-bridge
+    mode or digital input/output modes.
+**/
+class DigitalInOutHBridge : public DigitalInOut {
+    friend class StatusManager;
+    friend class SysManager;
+
+public:
+    /**
+       \enum ToneState
+
+       \brief Possible states of the tone generator.
+       \note IO-4 and IO-5 each have their own tone generators, and are the
+       only connectors capable of tone generation on the ClearCore.
+    **/
+    typedef enum {
+        /**
+            No tone is currently active.
+        **/
+        TONE_OFF = 0,
+        /**
+            A tone is playing indefinitely.
+        **/
+        TONE_CONTINUOUS,
+        /**
+            A tone is playing that will end after a specified duration.
+        **/
+        TONE_TIMED,
+        /**
+            A periodic tone is playing and the tone is currently sounding (in
+            the "on" phase of the tone output cycle).
+        **/
+        TONE_PERIODIC_ON,
+        /**
+            A periodic tone is playing and the tone is currently silent (in the
+            "off" phase of the tone output cycle).
+        **/
+        TONE_PERIODIC_OFF,
+    } ToneState;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager.
+
+        \note Should not be called by anything other than SysManager
+    **/
+    DigitalInOutHBridge() {};
+#endif
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorIO4.Mode() == Connector::OUTPUT_PWM) {
+            // IO-4 is currently a PWM output.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \code{.cpp}
+        // Configure IO-4 for tone output
+        ConnectorIO4.Mode(Connector::OUTPUT_TONE);
+        \endcode
+
+        \param[in] newMode The new mode to be set.
+        The valid modes for this connector type are:
+        - #INPUT_DIGITAL
+        - #OUTPUT_DIGITAL
+        - #OUTPUT_PWM
+        - #OUTPUT_H_BRIDGE
+        - #OUTPUT_TONE
+        - #OUTPUT_WAVE.
+        \return Returns false if the mode is invalid or setup fails.
+
+        \note If connector is in fault, attempts to set the mode will return
+        false, but the mode that was commanded will be applied once the
+        connector is no longer in a fault mode. Useful for getting out of a bad
+        mode.
+    **/
+    bool Mode(ConnectorModes newMode) override;
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() == Connector::H_BRIDGE_TYPE) {
+            // This generic connector variable is a DigitalInOutHBridge
+            // connector
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::H_BRIDGE_TYPE;
+    }
+
+    /**
+        \brief Set the amplitude of a PWM output for tone generation.
+
+        \code{.cpp}
+        // Set IO-4's amplitude to 1/10 of the max
+        ConnectorIO4.ToneAmplitude(INT16_MAX / 10);
+        \endcode
+
+        \param[in] amplitude The amplitude of the tone (0 to INT16_MAX)
+    **/
+    void ToneAmplitude(int16_t amplitude);
+
+    /**
+        \brief Output a continuous tone from the H-Bridge.
+
+        \code{.cpp}
+        // Start a continuous 100Hz tone on IO-4
+        ConnectorIO4.ToneContinuous(100);
+        \endcode
+
+        \param[in] frequency The frequency of the tone (Hz)
+    **/
+    void ToneContinuous(uint16_t frequency);
+
+    /**
+        \brief Output a tone from the H-Bridge for the specified duration.
+
+        \code{.cpp}
+        // Start a 50Hz, 500ms tone on IO-4 that does not block further code
+        // execution
+        ConnectorIO4.ToneTimed(50, 500);
+        \endcode
+
+        \param[in] frequency The frequency of the tone (Hz)
+        \param[in] duration How long to play the tone (ms). Specifying a
+        \a duration of 0 will result in a continuous tone (equivalent to
+        calling #ToneContinuous(uint16_t frequency) with the supplied
+        \a frequency).
+        \param[in] blocking (optional) Sets whether the function will block all
+        other operations until the tone has finished playing. Default: false.
+        \param[in] forceDuration (optional) If true, the tone will be made to
+        sound for the full \a duration specified, regardless of any subsequent
+        tone function calls made before the \a duration has elapsed.
+        Default: false.
+
+        \note Duration is only accurate to the SysTickRate.
+        \note The blocking and forceDuration parameters do not apply when
+        duration = 0.
+    **/
+    void ToneTimed(uint16_t frequency, uint32_t duration,
+                   bool blocking = false, bool forceDuration = false);
+
+    /**
+        \brief Output a periodic tone from the H-Bridge.
+
+        \code{.cpp}
+        // Start a 50Hz, 150ms on/25ms off tone on IO-4 that continues until
+        // stopped by a call to ToneStop().
+        ConnectorIO4.ToneTimed(50, 150, 25);
+        \endcode
+
+        \param[in] frequency The frequency of the tone (Hz)
+        \param[in] timeOn Periodic on time (ms)
+        \param[in] timeOff Periodic off time (ms)
+    **/
+    void TonePeriodic(uint16_t frequency, uint32_t timeOn, uint32_t timeOff);
+
+    /**
+        Stop the tone output.
+
+        \code{.cpp}
+        // Stop a tone playing on IO-4
+        ConnectorIO4.ToneStop();
+        \endcode
+    **/
+    void ToneStop();
+
+    /**
+        \brief Accessor for the state of the tone currently active on the
+        H-Bridge
+
+        \code{.cpp}
+        if (ConnectorIO5.ToneActiveState() ==
+            DigitalInOutHBridge::TONE_CONTINUOUS) {
+            // An endless tone is currently playing on IO-5
+        }
+        \endcode
+
+        \return The type of tone currently playing
+    **/
+    volatile const ToneState &ToneActiveState() {
+        return m_toneState;
+    }
+
+    /**
+        \brief Get connector's last sampled value.
+
+        \code{.cpp}
+        // In this example, IO-4 has been configured for digital input
+        if (ConnectorIO4.State()) {
+            // IO-4's input is currently high
+        }
+        \endcode
+
+        \code{.cpp}
+        // In this example, IO-4 has been configured for PWM output
+        if (ConnectorIO4.State() < UINT8_MAX / 4) {
+            // IO-4 is outputting PWM at a duty cycle less than 25%
+        }
+        \endcode
+
+        \code{.cpp}
+        // In this example, IO-4 has been configured for H-Bridge output
+        if (ConnectorIO4.State() < INT16_MIN / 2) {
+            // IO-4 is outputting differential PWM in the negative direction
+            // at a duty cycle greater than 50% (between -50% and -100%)
+        }
+        \endcode
+        \return The latest sample
+    **/
+    int16_t State() override;
+
+    /**
+        \brief Set the state of the Connector
+
+        \code{.cpp}
+        if (ConnectorIO5.Mode() == Connector::OUTPUT_DIGITAL) {
+            // Assert IO-5's digital output
+            ConnectorIO5.State(true);
+        }
+        if (ConnectorIO5.Mode() == Connector::OUTPUT_PWM) {
+            // Set IO-5's digital PWM output to 50% duty
+            // Valid range is 0 to UINT8_MAX
+            ConnectorIO5.State(UINT8_MAX / 2);
+        }
+        if (ConnectorIO5.Mode() == Connector::OUTPUT_H_BRIDGE) {
+            // Set IO-5's H-Bridge output to -25% duty
+            // Valid range is -INT16_MAX to INT16_MAX
+            ConnectorIO5.State(-INT16_MAX / 4);
+        }
+        \endcode
+
+        \param[in] newState New state to set for the connector.
+
+        \return success.
+    **/
+    bool State(int16_t newState) override;
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (ConnectorIO4.IsWritable()) {
+            // IO-4 is in an output mode
+        }
+        \endcode
+
+        \return True if in #OUTPUT_DIGITAL, #OUTPUT_PWM, #OUTPUT_H_BRIDGE,
+        #OUTPUT_TONE, or #OUTPUT_WAVE mode, false otherwise.
+    **/
+    bool IsWritable() override;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Update the tone sine wave output value
+    **/
+    void ToneUpdate();
+#endif
+
+private:
+    // Tone values
+    int16_t m_amplitude;
+    int16_t m_sinStep;
+    int16_t m_angle;
+    uint32_t m_toneStartTick;
+    uint32_t m_toneOnTicks;
+    uint32_t m_toneOffTicks;
+    ToneState m_toneState;
+
+    //Port, Pin, and Timer/Counter values
+    const PeripheralRoute *m_pwmAInfo;
+    const PeripheralRoute *m_pwmBInfo;
+
+    Tcc *m_tcc;
+    IRQn_Type m_tccIrq;
+
+    bool m_inFault;
+    bool m_forceToneDuration;
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+
+    /**
+        \brief Update connector's state.
+
+        Poll the underlying connector for new state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    void Refresh() override;
+
+    /**
+        \brief Set the frequency for a PWM output.
+
+        \param[in] frequency the frequency of the tone (Hz)
+    **/
+    inline void ToneFrequency(uint16_t frequency);
+
+    /**
+        \brief Sets the fault flag and disables the H-Bridge output when faulted
+
+        During fault, the HBridge I/O pin will be disabled.
+    **/
+    void FaultState(bool isFaulted);
+
+    /**
+        Construct and wire in LED bit number
+    **/
+    DigitalInOutHBridge(ShiftRegister::Masks ledMask,
+                        const PeripheralRoute *inputInfo,
+                        const PeripheralRoute *outputInfo,
+                        const PeripheralRoute *pwmAInfo,
+                        const PeripheralRoute *pwmBInfo,
+                        IRQn_Type tccIrq,
+                        bool invertDigitalLogic);
+}; // DigitalInOutHBridge
+
+} // ClearCore namespace
+
+#endif // __HBRIDGE_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DmaManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DmaManager.h
new file mode 100644
index 000000000..3587b37b3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/DmaManager.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file DmaManager.h
+    \brief DMA Peripheral Manager for the ClearCore Board
+
+    This class manages the DMA transfers on the Teknic ClearCore.
+**/
+
+#ifndef __DMAMANAGER_H__
+#define __DMAMANAGER_H__
+
+#include <stdint.h>
+#include <sam.h>
+
+#ifndef HIDE_FROM_DOXYGEN
+namespace ClearCore {
+
+/* DMA channels */
+typedef enum {
+    DMA_ADC_RESULTS,    ///< ADC result data
+    DMA_ADC_SEQUENCE,   ///< ADC conversion info
+    DMA_SERCOM0_SPI_RX, ///< COM1 SPI streaming input
+    DMA_SERCOM0_SPI_TX, ///< COM1 SPI streaming output
+    DMA_SERCOM7_SPI_RX, ///< COM0 SPI streaming input
+    DMA_SERCOM7_SPI_TX, ///< COM0 SPI streaming output
+    DMA_CHANNEL_COUNT,  // Keep at end
+    DMA_INVALID_CHANNEL // Placeholder for unset values
+} DmaChannels;
+
+/**
+    \brief DMA Peripheral Manager for the ClearCore Board
+
+    This class manages the DMA transfers on the Teknic ClearCore.
+**/
+class DmaManager {
+    friend class SysManager;
+
+public:
+    static DmacChannel *Channel(DmaChannels index);
+    static DmacDescriptor *BaseDescriptor(DmaChannels index);
+
+    /**
+        Public accessor for singleton instance
+    **/
+    static DmaManager &Instance();
+private:
+
+    static DmacDescriptor writeBackDescriptor[DMA_CHANNEL_COUNT] __attribute__((
+                aligned(16)));
+    static DmacDescriptor descriptorBase[DMA_CHANNEL_COUNT] __attribute__((aligned(
+                16)));
+
+    /**
+        \brief Constructor for DmaManager
+
+        Initializes member variables, doesn't do any work.
+
+        \note Should not be called by anything other than SysManager
+    **/
+    DmaManager() {};
+
+    /**
+        \brief One-time initialization of the DMAC
+
+        Enables Peripheral clock and configures DMAC (Direct Memory Access
+        Controller).
+    **/
+    static void Initialize();
+}; // DmaManager
+
+} // ClearCore namespace
+
+#endif // HIDE_FROM_DOXYGEN
+#endif // __DMAMANAGER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EncoderInput.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EncoderInput.h
new file mode 100644
index 000000000..1db5b0f90
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EncoderInput.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file EncoderInput.h
+    \brief ClearCore encoder input object.
+
+    Provides position information from quadrature and index signals.
+**/
+
+
+#ifndef __ENCODER_INPUT_H__
+#define __ENCODER_INPUT_H__
+
+#include "PeripheralRoute.h"
+
+/// Number of encoder samples to use for velocity calculation
+#define VEL_EST_SAMPLES 50
+
+namespace ClearCore {
+
+typedef void (*voidFuncPtr)(void);
+
+/**
+    \brief ClearCore Position Sensor Decoder.
+
+    Provides position and velocity information from external quadrature and
+    index signals. Use the Encoder Input Adapter Board (PN: CL-ENCDR-DFIN) to
+    wire an external encoder to ClearCore.
+
+    \note When using the Encoder Input Adapter Board, ClearCore's DI-6/DI-7/DI-8
+    inputs will be unavailable. Refer to the ClearCore User Manual for specs
+    and wiring information.
+**/
+class EncoderInput {
+    friend class SysManager;
+public:
+
+#ifndef HIDE_FROM_DOXYGEN
+
+    /**
+        Construct
+    **/
+    EncoderInput();
+
+    /**
+        \brief Debug function to monitor the PDEC peripheral
+
+        \code{.cpp}
+        if (EncoderIn.HwPosition() > 1000) {
+            // Position passed 1000, do something.
+        }
+        \endcode
+
+        \return The position count of the PDEC peripheral.
+    **/
+    volatile const int16_t& HwPosition() {
+        return m_hwPosn;
+    }
+
+    /**
+        \brief Index interrupt helper function.
+
+        Store the location of the index to be processed in the next update.
+    **/
+    void IndexDetected(int16_t posn) {
+        m_hwIndex = posn;
+        m_processIndex = true;
+    }
+#endif
+
+    /**
+        \brief Read the current position of the encoder
+
+        \code{.cpp}
+        if (EncoderIn.Position() > 1000) {
+            // Position passed 1000, do something.
+        }
+        \endcode
+
+        \return The position count of the Encoder Input module.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    int32_t Position();
+
+    /**
+        \brief Set the current position of the encoder
+
+        \code{.cpp}
+        // Zero the encoder position
+        EncoderIn.Position(0);
+        \endcode
+
+        \return The number of counts that the encoder position was shifted.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    int32_t Position(int32_t newPosn);
+
+    /**
+        \brief Adjust the current position of the encoder
+
+        \code{.cpp}
+        // Shift the encoder numberspace upwards by 500 counts
+        EncoderIn.AddToPosition(500);
+        \endcode
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    void AddToPosition(int32_t posnAdjust);
+
+    /**
+        \brief Read the last index position of the encoder
+
+        \code{.cpp}
+        static int32_t lastIndex = 0;
+        if (EncoderIn.IndexPosition() != lastIndex) {
+            // A new index pulse was seen, do something.
+
+            // Update the position of the last index pulse seen
+            lastIndex = EncoderIn.IndexPosition();
+        }
+        \endcode
+
+        \return The position count of the last Encoder index pulse.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    int32_t IndexPosition();
+
+    /**
+        \brief Set whether the encoder input should be active or not.
+
+        \code{.cpp}
+        // Before using the Encoder Input, it has to be enabled.
+        EncoderIn.Enable(true);
+        \endcode
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    void Enable(bool isEnabled);
+
+    /**
+        \brief Swap the sense of positive and negative encoder directions.
+
+        \code{.cpp}
+        // Set the encoder counting direction to match the wiring and code.
+        EncoderIn.SwapDirection(true);
+        \endcode
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    void SwapDirection(bool isSwapped);
+
+    /**
+        \brief Read the velocity of the encoder input (counts per second)
+
+        \code{.cpp}
+        // Read the current encoder velocity
+        int32_t encoderSpeed = EncoderIn.Velocity();
+        \endcode
+
+        \return The encoder input velocity in counts per second.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    volatile const int32_t& Velocity() {
+        return m_velocity;
+    }
+
+    /**
+        \brief Check if there was an index pulse in the last sample time.
+
+        \code{.cpp}
+        // Check for an index pulse
+        bool hadIndex = EncoderIn.IndexDetected();
+        \endcode
+
+        \return True if the index transitioned from deasserted to asserted
+        in the last sample time.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    volatile const bool& IndexDetected() {
+        return m_indexDetected;
+    }
+
+    /**
+        \brief Invert the edge that the index detection triggers on.
+
+        The index nominally triggers when the digital input value rises.
+        This setting allows the index to trigger on the falling edge.
+
+        \code{.cpp}
+        // Set the index pulse to trigger on the falling input edge.
+        bool hadIndex = EncoderIn.IndexInverted(true);
+        \endcode
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    void IndexInverted(bool invert);
+
+    /**
+        \brief Query for a quadrature error
+
+        \code{.cpp}
+        // Check for a quadrature error
+        bool quadratureError = EncoderIn.QuadratureError();
+        \endcode
+
+        \return The current state of the quadrature error flag in the position
+        decoder module.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool QuadratureError();
+
+    /**
+        \brief Clear a quadrature error
+
+        \code{.cpp}
+        // Clear a quadrature error if there is one
+        if (EncoderIn.QuadratureError()) {
+            EncoderIn.ClearQuadratureError();
+        }
+        \endcode
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    void ClearQuadratureError();
+
+    /**
+        \brief Get the number of encoder steps received in the last sample time.
+
+        \code{.cpp}
+        if (EncoderIn.StepsLastSample() == 0) {
+            // Do something in the case that we haven't received steps
+        }
+        \endcode
+
+        \return The number of steps received in the last sample time.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    volatile const int16_t& StepsLastSample() {
+        return m_stepsLast;
+    }
+
+private:
+    const PeripheralRoute *m_aInfo;
+    const PeripheralRoute *m_bInfo;
+    const PeripheralRoute *m_indexInfo;
+    int32_t m_curPosn;
+    int32_t m_offsetAdjustment;
+    int32_t m_velocity;
+    int16_t m_hwPosn;
+    int32_t m_posnHistory[VEL_EST_SAMPLES];
+    uint8_t m_posnHistoryIndex;
+    bool m_enabled;
+    bool m_processIndex;
+    int16_t m_hwIndex;
+    int32_t m_indexPosn;
+    bool m_indexDetected;
+    bool m_indexInverted;
+    int16_t m_stepsLast;
+
+    void Initialize();
+
+    void Update();
+
+}; // EncoderInput
+
+} // ClearCore namespace
+
+#endif /* __ENCODER_INPUT_H__ */
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetApi.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetApi.h
new file mode 100644
index 000000000..29f51e357
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetApi.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef HIDE_FROM_DOXYGEN
+/**
+    \file EthernetApi.h
+
+    This file contains standard definitions for the receive (RX) and transmit
+    (TX) descriptors as defined by the datasheet.
+    This file contains a definition for a local interface struct to be
+    used in conjunction with LwIP.
+**/
+
+#ifndef __ETHERNETAPI_H__
+#define __ETHERNETAPI_H__
+
+#include <stdint.h>
+
+#ifndef TX_BUFF_CNT
+#define TX_BUFF_CNT (8)
+#endif
+
+#ifndef RX_BUFF_CNT
+#define RX_BUFF_CNT (16)
+#endif
+
+#ifndef TX_BUFFER_SIZE
+#define TX_BUFFER_SIZE (520)
+#endif
+
+#ifndef RX_BUFFER_SIZE
+#define RX_BUFFER_SIZE (128)
+#endif
+
+/**
+    \brief Ethernet receive buffer descriptor.
+
+    A receive buffer descriptor list entry as described by the data sheet.
+**/
+typedef union {
+    struct {
+uint32_t OWN :
+        1;     /*!< bit:  0       Ownership of this buffer.                 */
+uint32_t WRAP :
+        1;    /*!< bit:  1       Last descriptor in receive buffer list    */
+uint32_t ADDR :
+        30;   /*!< bit:  2..31   Address of beginning of buffer            */
+uint32_t LEN :
+        13;    /*!< bit:  0..12   Length of the received frame              */
+uint32_t FCS :
+        1;     /*!< bit:  13      Meaning depending on jumbo frames and ignore FCS */
+uint32_t SF :
+        1;      /*!< bit:  14      Start of Frame                           */
+        uint32_t EF : 1;      /*!< bit:  15      End of Frame   */
+        uint32_t CFI : 1;     /*!< bit:  16      Canonical Format Indicator   */
+        uint32_t VLAN : 3;    /*!< bit:  17..19  VLAN priority  */
+        uint32_t PTAG : 1;    /*!< bit:  20      Priority Tag detected */
+        uint32_t VTAG : 1;    /*!< bit:  21      VLAN Tag detected */
+uint32_t CSM :
+        2;     /*!< bit:  22..23  Meaning depends on whether RX checksum offloading enabled */
+uint32_t SNAP :
+        1;    /*!< bit   24      Meaning depends on whether RX checksum offloading enabled */
+uint32_t SPAMI :
+        2;   /*!< bit   25..26  Specific Address Register Match -- which address */
+uint32_t SPAM :
+        1;    /*!< bit   27      Specific Address Register Match found */
+        uint32_t: 1;          /*!< bit   28      Reserved */
+        uint32_t UHM : 1;     /*!< bit   29      Unicast Hash Match */
+        uint32_t MHM : 1;     /*!< bit   30      Multicast Hash Match */
+        uint32_t GAO : 1;     /*!< bit   31      Global All Ones Broadcast Address */
+    } bit;
+    uint32_t reg[2];
+} GMAC_RX_DESC;
+
+/**
+   \brief Ethernet transmit buffer descriptor.
+
+   A transmit buffer descriptor list entry as described by the data sheet.
+**/
+typedef union {
+    struct {
+        uint32_t ADDR : 32;   /*!< bit   0..31   Byte Address of Buffer */
+        uint32_t LEN : 14;    /*!< bit   0..13   Length of buffer */
+        uint32_t: 1;          /*!< bit   14      Reserved */
+        uint32_t LB : 1;      /*!< bit   15      Last Buffer of the current frame */
+uint32_t CRC :
+        1;     /*!< bit   16      Data in buffer already contains a valid CRC */
+        uint32_t: 3;          /*!< bit   17..19  Reserved */
+uint32_t CSER :
+        3;    /*!< bit   20..22  Transmit IP/TCP/UDP checksum generation offload errors */
+        uint32_t: 3;          /*!< bit   23..25  Reserved */
+uint32_t LCERR :
+        1;   /*!< bit   26      Late collision, transmit error detected */
+uint32_t FCERR :
+        1;   /*!< bit   27      Transmit frame corruption due to AHB error */
+        uint32_t: 1;          /*!< bit   28      Reserved */
+uint32_t RLERR :
+        1;   /*!< bit   29      Retry limit exceeded, transmit error detected */
+uint32_t WRAP :
+        1;    /*!< bit   30      Marks last descriptor in transmit buffer descriptor list */
+        uint32_t OWN : 1;     /*!< bit   31      Ownership of this buffer */
+    } bit;
+    uint32_t reg[2];
+} GMAC_TX_DESC;
+
+/**
+    \brief The internal Ethernet interface.
+
+    The ClearCore's internal interface structure, passed around as 'state'
+    by the network interface for LwIP.
+**/
+typedef struct {
+    GMAC_RX_DESC *rxDesc;       /* Receive buffer descriptor address */
+    GMAC_TX_DESC *txDesc;       /* Transmit buffer descriptor address */
+    uint8_t *rxBuffIndex;       /* Receive buffer index */
+    uint16_t *txBuffIndex;      /* Transmit buffer index */
+    uint8_t mac[6];             /* MAC address */
+} ethInt;
+
+typedef struct netif netInt;
+typedef struct pbuf packetBuf;
+
+#endif // !__ETHERNETAPI_H__
+#endif // !HIDE_FROM_DOXYGEN
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetManager.h
new file mode 100644
index 000000000..5f48bb89b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetManager.h
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file EthernetManager.h
+    This class controls access to the Ethernet Port device.
+
+    It will allow you to set up:
+        - Ethernet connections
+**/
+
+#ifndef __ETHERNETMANAGER_H__
+#define __ETHERNETMANAGER_H__
+
+#include <cstring>
+#include <sam.h>
+#include "EthernetApi.h"
+#include "HardwareMapping.h"
+#include "IpAddress.h"
+#include "Phy.h"
+#include "SysUtils.h"
+#include "lwip/dhcp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore Ethernet configuration manager
+
+    This class manages setup and access to the Ethernet PHY chip and Ethernet
+    Media Access Controller (GMAC) peripheral.
+
+    For more detailed information on the ClearCore Ethernet system, check out
+    the \ref EthernetMain informational page.
+**/
+class EthernetManager {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for singleton instance
+    **/
+    static EthernetManager &Instance();
+
+    /**
+        \brief Initialize the EthernetManager.
+
+        Configures the GMAC pins and settings. Including addressing GMAC
+        registers to point to descriptor buffers and selecting interrupts
+        to activate.
+
+        \note Disables transmit and receive.
+    **/
+    void Initialize();
+
+    /**
+        \brief Initialize the PHY.
+
+        Performs a software reset of the PHY and configures the default
+        settings. Can be used to re-initialize when PHY initialization fails.
+
+        \code{.cpp}
+        if (EthernetMgr.PhyInitFailed()) {
+            // PHY initialization failed, re-initialize.
+            EthernetMgr.PhyInitialize();
+        }
+        \endcode
+    **/
+    void PhyInitialize();
+
+    /**
+        \brief Read or write to a PHY register.
+
+        Initiates and completes a shift operation to the PHY via the GMAC's
+        management port.
+
+        \param[in] phyOp    The PHY operation (read or write).
+        \param[in] phyReg   The PHY register to read the contents of.
+        \param[in] contents The desired contents for a write operation,
+                            ignored for read.
+
+        \return Returns the contents of the PHY register after the read or write
+    **/
+    uint32_t PhyShift(uint32_t phyOp, uint32_t phyReg, uint32_t contents);
+
+    /**
+        \brief Read and return the contents of a PHY register.
+
+        \param[in] phyReg   The PHY register to read the contents of.
+
+        \return Returns the contents of the specified PHY register.
+    **/
+    uint32_t PhyRead(uint32_t phyReg);
+
+    /**
+        \brief Write to a PHY register.
+
+        \param[in] phyReg   The PHY register that will be written.
+        \param[in] contents The value to write into the PHY register.
+
+        \return Returns the contents of the PHY register after the write.
+    **/
+    uint32_t PhyWrite(uint32_t phyReg, uint32_t contents);
+#endif
+
+    /**
+        \brief Check the link status from the PHY.
+
+        \return Returns true if the PHY has indicated link up.
+        Returns false if the PHY has indicated link down.
+
+        \note The PHY link should be confirmed before activating transmit and
+        receive of frames through the GMAC.
+    **/
+    volatile const bool &PhyLinkActive() {
+        return m_phyLinkUp;
+    }
+
+    /**
+        \brief Check the remote fault status from the PHY.
+
+        \return Returns true if the PHY indicates a remote fault.
+    **/
+    volatile const bool &PhyRemoteFault() {
+        return m_phyRemoteFault;
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Check the initialization failure status of the PHY.
+
+        \return Returns true if the PHY failed to initialize.
+    **/
+    volatile const bool &PhyInitFailed() {
+        return m_phyInitFailed;
+    }
+
+    /**
+        \brief Enable transmit and receive of frames.
+
+        \param[in] enable True enables transmit and receive of frames.
+    **/
+    void Enable(bool enable);
+
+    /**
+        \brief Clear on read check if a frame was received.
+
+        \return Returns true if a frame was received.
+    **/
+    bool ReceivedFrameFlag();
+
+    /**
+        Interrupt handler for Ethernet PHY.
+    **/
+    void IrqHandlerPhy();
+
+    /**
+        \brief Interrupt handler for Ethernet GMAC.
+
+        \note The interrupt register and bits are cleared on read.
+    **/
+    void IrqHandlerGmac();
+#endif
+
+    /**
+        \brief Get the MAC address.
+
+        \return Returns the MAC address as uint8_t pointer type.
+    **/
+    uint8_t *MacAddress();
+
+    /**
+        \brief Get the local IP address.
+
+        \return Returns the local IP address.
+    **/
+    IpAddress LocalIp();
+
+    /**
+        \brief Set the local IP address.
+
+        \note The local IP must be provided when using a static local IP. In
+        this case, be sure to specify a valid IP address on the same network
+        as your router/switch. This is probably an address of the form
+        "192.168.x.y". For example, if your router's address is 192.168.0.1,
+        you should use an address of the form 192.168.0.y as long as there
+        isn't a device on the network already that was assigned the same IP
+        address.
+        \note Doesn't have any effect when using DHCP.
+    **/
+    void LocalIp(IpAddress ipaddr);
+
+    /**
+        \brief Get the netmask IP.
+
+        \return Returns the netmask IP as uint32_t type.
+    **/
+    IpAddress NetmaskIp();
+
+    /**
+        \brief Set the netmask IP.
+        \note Doesn't have any effect when using DHCP.
+
+        \note The netmask IP must be provided when using a static local IP.
+    **/
+    void NetmaskIp(IpAddress address);
+
+    /**
+        \brief Get the gateway IP address.
+
+        \return Returns the gateway IP address.
+    **/
+    IpAddress GatewayIp();
+
+    /**
+        \brief Set the gateway IP address.
+        \note The gateway IP must be provided when using a static local IP.
+        \note Doesn't have any effect when using DHCP.
+    **/
+    void GatewayIp(IpAddress address);
+
+    /**
+        \brief Get the DNS IP address used for address resolution.
+
+        \return Returns the current default DNS IP address.
+    **/
+    IpAddress DnsIp();
+
+    /**
+        \brief Set the DNS IP address used for address resolution.
+
+        \param[in] dns The DNS IP address.
+
+        \note Doesn't have any effect when called prior to calling Setup().
+    **/
+    void DnsIp(IpAddress dns);
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Get a pointer to the network interface struct.
+
+        \return Returns a pointer to the network interface struct used by LwIP.
+    **/
+    netif *MacInterface() {
+        return &m_macInterface;
+    }
+#endif
+
+    /**
+        \brief Get the retransmission timeout.
+
+        \return Returns the retransmission timeout in milliseconds.
+    **/
+    volatile const uint16_t &RetransmissionTimeout() {
+        return m_retransmissionTimeout;
+    }
+
+    /**
+        \brief Set the retransmission timeout.
+
+        \param[in] timeout The retransmission timeout interval to be set,
+        in milliseconds.
+    **/
+    void RetransmissionTimeout(uint8_t timeout) {
+        m_retransmissionTimeout = timeout;
+    }
+
+    /**
+        \brief Get the retransmission count.
+
+        \return The number of times to attempt transmitting before giving up.
+    **/
+    volatile const uint8_t &RetransmissionCount() {
+        return m_retransmissionCount;
+    }
+
+    /**
+        \brief Set the retransmission count.
+
+        \param[in] count The retransmission count to be set.
+
+        \note This is really the total transmission count, so you should never
+              set this to a value less than 1.
+    **/
+    void RetransmissionCount(uint8_t count) {
+        m_retransmissionCount = count;
+    }
+
+    /**
+        \brief Set up DHCP connection to retrieve local IP.
+
+        Attempts to perform DHCP negotiation to be supplied an IP address.
+
+        \return Returns true if DHCP supplied an IP address.
+    **/
+    bool DhcpBegin();
+
+    /**
+        \brief Setup LwIP with the local network interface.
+        \note Should only be called once.
+    **/
+    void Setup();
+
+    /**
+        \brief Perform any necessary periodic Ethernet and LwIP updates.
+
+        Sends all incoming, buffered packets to the LwIP interface. Calls
+        sys_check_timeouts() to perform any necessary LwIP related tasks.
+
+        \note Must be called regularly when actively using Ethernet.
+        \note Must NOT be called from an interrupt context.
+    **/
+    void Refresh();
+
+    /**
+        \brief A flag to indicate whether Ethernet setup has been invoked.
+
+        \return true if Ethernet has been set up, false otherwise.
+    **/
+    volatile const bool &EthernetActive() {
+        return m_ethernetActive;
+    }
+
+private:
+    // GMAC port/pin combinations
+    uint32_t m_portPhyTxen;
+    uint32_t m_pinPhyTxen;
+    uint32_t m_portPhyTxd0;
+    uint32_t m_pinPhyTxd0;
+    uint32_t m_portPhyTxd1;
+    uint32_t m_pinPhyTxd1;
+    uint32_t m_portPhyRxd0;
+    uint32_t m_pinPhyRxd0;
+    uint32_t m_portPhyRxd1;
+    uint32_t m_pinPhyRxd1;
+    uint32_t m_portPhyRxer;
+    uint32_t m_pinPhyRxer;
+    uint32_t m_portPhyRxdv;
+    uint32_t m_pinPhyRxdv;
+    uint32_t m_portPhyMdio;
+    uint32_t m_pinPhyMdio;
+    uint32_t m_portPhyMdc;
+    uint32_t m_pinPhyMdc;
+    uint32_t m_portPhyTxclk;
+    uint32_t m_pinPhyTxclk;
+    uint32_t m_portPhyInt;
+    uint32_t m_pinPhyInt;
+
+    uint32_t m_phyExtInt;
+    // PHY link up bit - updated via PHY interrupt
+    bool m_phyLinkUp;
+    // PHY remote fault bit -- updated via PHY interrupt
+    bool m_phyRemoteFault;
+    // PHY initialization failed status
+    bool m_phyInitFailed;
+
+    // received a frame flag
+    bool m_recv;
+    // DHCP flag
+    bool m_dhcp;
+    // Ethernet setup complete flag
+    bool m_ethernetActive;
+
+    // Receive Buffer Current Index
+    uint8_t m_rxBuffIndex;
+    // Transmit Buffer Current Index
+    uint16_t m_txBuffIndex;
+    // Receive Buffer Descriptor List
+    GMAC_RX_DESC m_rxDesc[RX_BUFF_CNT];
+    // Transmit Buffer Descriptor List
+    GMAC_TX_DESC m_txDesc[TX_BUFF_CNT];
+    // Receive Buffers
+    uint8_t m_rxBuffer[RX_BUFF_CNT][RX_BUFFER_SIZE];
+    // Transmit Buffers
+    uint8_t m_txBuffer[TX_BUFF_CNT][TX_BUFFER_SIZE];
+
+    // Blocking retransmission timeout in milliseconds
+    uint16_t m_retransmissionTimeout;
+    // Number of transmission attempts before giving up
+    uint8_t m_retransmissionCount;
+
+    // internal network interface
+    ethInt m_ethernetInterface;
+
+    /* Built-in lwIP types.
+     */
+    // lwIP's network interface
+    struct netif m_macInterface;
+    // DHCP configuration
+    struct dhcp *m_dhcpData;
+
+    /**
+        \brief Network interface initialization for LwIP.
+        \note Should only be called once.
+    **/
+    void NetifInit();
+
+    /**
+        \brief Setup a single GMAC GPIO.
+
+        Sets a GPIO pin to enabled and assigns the correct PMUX
+        (odd or even) to PER_GMAC to be controlled by the GMAC.
+
+        \param[in] port The port.
+        \param[in] pin  The pin.
+    **/
+    void ConfigureGpioPerGmac(uint32_t port, uint32_t pin);
+
+    /**
+        Construct
+    **/
+    EthernetManager();
+
+}; // EthernetManager
+
+} // ClearCore namespace
+
+#endif // !__ETHERNETMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcp.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcp.h
new file mode 100644
index 000000000..d04e88b8f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcp.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file EthernetTcp.h
+**/
+
+#ifndef __ETHERNETTCP_H__
+#define __ETHERNETTCP_H__
+
+#include "lwip/tcp.h"
+#include <string.h>
+#ifndef HIDE_FROM_DOXYGEN
+namespace ClearCore {
+
+/** The maximum number of allowable client connections at any given time. **/
+#define CLIENT_MAX 8
+/** The size of the buffer to hold incoming TCP data, in bytes. **/
+#define TCP_DATA_BUFFER_SIZE 600
+
+/**
+    \brief A base class for an Ethernet TCP connection.
+
+    This class is a basic interface for a TCP connection.
+
+    For more detailed information on the ClearCore Ethernet system, check out
+    the \ref EthernetMain informational page.
+**/
+class EthernetTcp {
+
+public:
+    /**
+        ClearCore TCP connection state.
+    **/
+    typedef struct {
+        struct tcp_pcb *pcb;    /*!< The LwIP PCB for the TCP connection. */
+        uint16_t dataHead;      /*!< The head of the incoming data buffer. */
+        uint16_t dataTail;      /*!< The tail of the incoming data buffer. */
+        tcp_state state;        /*!< The state of this tcp_data. */
+        uint8_t data[TCP_DATA_BUFFER_SIZE]; /*!< The incoming data buffer for
+                                                        this TCP connection. */
+    } TcpData;
+
+    /**
+        Construct a TCP connection with no existing TCP state information.
+    **/
+    EthernetTcp() : m_tcpData(nullptr) {};
+
+    /**
+        Construct a TCP connection with existing TCP state information.
+    **/
+    EthernetTcp(TcpData *tcpData);
+
+    /**
+        \brief Send a TCP packet.
+
+        Send a TCP packet to the remote with a single character as the payload.
+
+        \param[in] charToSend A character to send to the remote.
+
+        \return The number of bytes written.
+    **/
+    uint32_t Send(uint8_t charToSend);
+
+    /**
+        \brief Send a TCP packet.
+
+        Send a TCP packet to the remote with a string of characters as the
+        payload.
+
+        \param[in] nullTermStr A string to send to the remote.
+
+        \return The number of bytes written.
+    **/
+    uint32_t Send(const char *nullTermStr) {
+        return Send((const uint8_t *)nullTermStr, strlen(nullTermStr));
+    }
+
+    /**
+        \brief Send a TCP packet.
+
+        Send a TCP packet to the remote with a sequence of characters as the
+        payload.
+
+        \param[in] buff The data to send.
+        \param[in] size The number of characters to send.
+
+        \return The number of bytes written.
+    **/
+    virtual uint32_t Send(const uint8_t *buff, uint32_t size) = 0;
+
+    /**
+        \brief Get the local port number.
+
+        \return Returns the local port number.
+    **/
+    uint16_t LocalPort();
+
+    /**
+        \brief Get the local port number.
+
+        \return Returns the local port number.
+    **/
+    volatile const TcpData *ConnectionState() {
+        return m_tcpData;
+    }
+
+protected:
+    // The TCP state.
+    TcpData *m_tcpData;
+
+};  // EthernetTcp
+
+#ifndef HIDE_FROM_DOXYGEN
+/**
+    \brief The TCP connection accepted callback.
+    Allows a TCP server to accept clients.
+**/
+err_t TcpAccept(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+/**
+    The TCP connection callback.
+**/
+err_t TcpConnect(void *arg, struct tcp_pcb *tpcb, err_t err);
+
+/**
+    The TCP connection error callback.
+**/
+void TcpError(void *arg, err_t err);
+
+/**
+    \brief Handles a packet received from a TCP connection.
+
+    A TCP Receive callback function will be passed a NULL pbuf if the
+    remote host has closed the connection. If we return ERR_OK or ERR_ABRT
+    from this callback function we must have freed the pbuf, otherwise we
+    must NOT have freed it.
+ **/
+err_t TcpReceive(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
+                 err_t err);
+
+/**
+    The TCP send complete callback.
+**/
+err_t TcpSend(void *arg, struct tcp_pcb *tpcb, u16_t len);
+
+/**
+    Closes a TCP connection.
+**/
+void TcpClose(struct tcp_pcb *pcb, EthernetTcp::TcpData *data);
+#endif // !HIDE_FROM_DOXYGEN
+
+} // ClearCore namespace
+#endif // !HIDE_FROM_DOXYGEN
+#endif // !__ETHERNETTCP_H__
+
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcpClient.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcpClient.h
new file mode 100644
index 000000000..ae6fe94ac
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcpClient.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file EthernetTcpClient.h
+**/
+
+#ifndef __ETHERNETTCPCLIENT_H__
+#define __ETHERNETTCPCLIENT_H__
+
+#include <stdint.h>
+#include "EthernetTcp.h"
+#include "IpAddress.h"
+
+namespace ClearCore {
+
+/** The minimum TCP connection timeout value, in milliseconds. Attempts to set a
+    TCP connection timeout less than this value will fail, and this value will
+    be used instead. **/
+#define TCP_CONNECTION_TIMEOUT_MIN 100
+/** The maximum TCP connection timeout value, in milliseconds. Attempts to set a
+    TCP connection timeout greater than this value will fail, and this value
+    will be used instead. **/
+#define TCP_CONNECTION_TIMEOUT_MAX 15000
+
+/**
+    \brief ClearCore TCP client class.
+
+    This class manages interactions with a single Ethernet TCP client
+    connection.
+
+    For more detailed information on the ClearCore Ethernet system, check out
+    the \ref EthernetMain informational page.
+**/
+class EthernetTcpClient : public EthernetTcp {
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct an empty TCP client with no existing connection information.
+    **/
+    EthernetTcpClient();
+
+    /**
+        Construct a TCP client with existing connection information.
+    **/
+    explicit EthernetTcpClient(TcpData *tcpData);
+#endif // !HIDE_FROM_DOXYGEN
+
+    /**
+        \brief Connects the client to a specified remote IP address and port.
+
+        \return True if the connection was successful.
+    **/
+    bool Connect(IpAddress ip, uint16_t port);
+
+    /**
+        \brief Determines if the client is actively connected to a server.
+
+        \return True if the client's connection is active. False if there is no
+        connection or the existing connection is closed or closing.
+    **/
+    bool Connected();
+
+    /**
+        \brief Returns the number of bytes available to read.
+
+        \return The number of bytes available to read.
+    **/
+    int16_t BytesAvailable();
+
+    /**
+        \brief Attempt to read the next available character.
+
+        Attempts to get the next available character from the client's
+        incoming data buffer.
+
+        \return The character first character available, or -1 if no data is
+        available.
+    **/
+    int16_t Read();
+
+    /**
+        \brief Reads data received from the server.
+
+        \param[out] dataPtr A pointer to a buffer to hold the received data.
+        \param[in] length The maximum number of bytes to read.
+
+        \return The number of bytes read.
+    **/
+    int16_t Read(uint8_t *dataPtr, uint32_t length);
+
+    /**
+        \brief Attempt to get the next available character.
+
+        Attempts to get the next available character without pulling the
+        character out of the buffer.
+
+        \return The first character in the buffer, or -1 if no data is
+        available.
+    **/
+    int16_t Peek();
+
+    /**
+        \brief Wait until all outgoing data to the server has been sent.
+
+        While the server is connected, blocks until the server has ACK'd all
+        outgoing packets.
+    **/
+    void Flush();
+
+    /**
+        \brief Flush the received data.
+    **/
+    void FlushInput();
+
+    /**
+        \brief Close the client's connection to the server.
+    **/
+    void Close();
+
+    /**
+        \brief Send the buffer contents to the server.
+
+        \param[in] buff A pointer to the beginning of the data to send.
+        \param[in] size The maximum number of bytes to send.
+        \return The number of bytes sent to the server.
+
+        \note The contents of the supplied buffer represents the payload in an
+        outgoing TCP packet.
+    **/
+    uint32_t Send(const uint8_t *buff, uint32_t size) override;
+
+    /**
+        \brief Send a TCP packet.
+
+        Send a TCP packet to the remote with a single character as the payload.
+
+        \param[in] charToSend A character to send to the remote.
+
+        \return The number of bytes written.
+    **/
+    uint32_t Send(uint8_t charToSend) {
+        return EthernetTcp::Send(charToSend);
+    }
+
+    /**
+        \brief Send a TCP packet.
+
+        Send a TCP packet to the remote with a string of characters as the
+        payload.
+
+        \param[in] nullTermStr A string to send to the remote.
+
+        \return The number of bytes written.
+    **/
+    uint32_t Send(const char *nullTermStr) {
+        return EthernetTcp::Send(nullTermStr);
+    }
+
+    /**
+        \brief Returns the remote port of the server this client is connected to
+
+        \return The server's remote port.
+    **/
+    uint16_t RemotePort();
+
+    using EthernetTcp::LocalPort;
+
+    /**
+        \brief Returns the remote IP address of the server this client is
+        connected to.
+
+        \return The server's remote IP address.
+    **/
+    IpAddress RemoteIp();
+
+    /**
+        \brief Returns the connection timeout.
+
+        \return The connection timeout, in milliseconds.
+    **/
+    uint16_t ConnectionTimeout() {
+        return m_connectionTimeout;
+    }
+
+    /**
+        \brief Set the connection timeout. This is the maximum amount of time
+        to wait for a server to accept this client after establishing initial
+        communication with the server.
+
+        \param[in] timeout The new connection timeout value, in milliseconds.
+
+        \note Constrained between #TCP_CONNECTION_TIMEOUT_MIN and
+        #TCP_CONNECTION_TIMEOUT_MAX in milliseconds.
+    **/
+    void ConnectionTimeout(uint16_t timeout);
+
+#ifndef HIDE_FROM_DOXYGEN
+    virtual bool operator == (const EthernetTcpClient);
+#endif // !HIDE_FROM_DOXYGEN
+
+private:
+    uint16_t m_connectionTimeout;
+    bool m_dnsInitialized;
+
+}; // EthernetTcpClient
+
+} // ClearCore namespace
+
+#endif // !__ETHERNETTCPCLIENT_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcpServer.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcpServer.h
new file mode 100644
index 000000000..1987643f0
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetTcpServer.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file EthernetTcpServer.h
+**/
+
+#ifndef __ETHERNETTCPSERVER_H__
+#define __ETHERNETTCPSERVER_H__
+
+#include "EthernetTcp.h"
+#include "EthernetManager.h"
+#include "EthernetTcpClient.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore TCP server class.
+
+    This class manages an instance of a TCP server and manages interactions
+    with multiple Ethernet TCP client connections.
+
+    For more detailed information on the ClearCore Ethernet system, check out
+    the \ref EthernetMain informational page.
+**/
+class EthernetTcpServer : public EthernetTcp {
+
+public:
+    /**
+        \brief Construct a TCP server.
+
+        \param[in] port The local port to listen for incoming TCP connections
+        on.
+    **/
+    explicit EthernetTcpServer(uint16_t port);
+
+    /**
+        \brief Set up the server to begin listening for incoming TCP connections
+    **/
+    void Begin();
+
+    /**
+        \brief Return a reference to a client that has incoming data.
+
+        Returns a reference to a client that has incoming data available to
+        read. The server will continue to manage the client.
+
+        \return Returns a TCP client that has incoming data available to read.
+
+        \note The server will continue to track the client's reference.
+    **/
+    EthernetTcpClient Available();
+
+    /**
+        \brief Return a client with an active connection.
+
+        Returns a client with an active connection. The server will only return
+        an active client once, and then the server will no longer manage the
+        client's connection.
+
+        \return Returns a TCP client with an active connection.
+
+        \note The server will no longer track the client's reference.
+    **/
+    EthernetTcpClient Accept();
+
+    /**
+        \brief Send data to all clients managed by the server.
+
+        Send a TCP packet to each client managed by the server with the
+        contents of the provided buffer as the packet's payload.
+
+        \param[in] buff A pointer to the beginning of the data to send.
+        \param[in] size The maximum number of bytes to send.
+
+        \return The number of bytes written to each client.
+        \note The contents of the supplied buffer represents the payload in an
+        outgoing TCP packet.
+    **/
+    uint32_t Send(const uint8_t *buff, uint32_t size) override;
+
+    /**
+        \brief Send data to all clients managed by the server.
+
+        Send a TCP packet to each client managed by the server with a
+        character as the payload.
+
+        \param[in] charToSend A character to send to the clients.
+
+        \return The number of bytes written to each client.
+    **/
+    uint32_t Send(uint8_t charToSend) {
+        return EthernetTcp::Send(charToSend);
+    }
+
+    /**
+        \brief Send data to all clients managed by the server.
+
+        Send a TCP packet to each client managed by the server with a
+        string of characters as the payload.
+
+        \param[in] nullTermStr A string to send to the clients.
+
+        \return The number of bytes written to each client.
+    **/
+    uint32_t Send(const char *nullTermStr) {
+        return EthernetTcp::Send(nullTermStr);
+    }
+
+    using EthernetTcp::LocalPort;
+
+    /**
+        \brief Is the server ready to accept a client?
+
+        \return Return true if the server is ready to accept clients.
+    **/
+    bool Ready();
+
+private:
+    bool m_initialized;
+
+    // The server's listening port.
+    uint16_t m_serverPort;
+
+    // TCP state for connected clients.
+    TcpData *m_tcpDataClient[CLIENT_MAX];
+
+}; // EthernetTcpServer
+
+} // ClearCore namespace
+
+#endif // !__ETHERNETTCPSERVER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetUdp.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetUdp.h
new file mode 100644
index 000000000..0eba7452e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetUdp.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+    \file EthernetUdp.h
+**/
+
+#ifndef __ETHERNETUDP_H__
+#define __ETHERNETUDP_H__
+
+#include "IpAddress.h"
+#include "lwip/udp.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore UDP session class.
+
+    This class manages a single local UDP session.
+
+    For more detailed information on the ClearCore Ethernet system, check out
+    the \ref EthernetMain informational page.
+**/
+class EthernetUdp {
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        ClearCore UDP connection state.
+    **/
+    typedef struct {
+        struct udp_pcb *pcb; /*!< The LwIP PCB for the UDP connection. */
+        struct pbuf *packet; /*!< The incoming data buffer. */
+        uint16_t available;  /*!< The number of available incoming bytes. */
+        ip_addr_t remoteIp;  /*!< The remote IP address of the incoming data. */
+        u16_t remotePort;    /*!< The remote port of the incoming data. */
+    } UdpData;
+#endif // !HIDE_FROM_DOXYGEN
+
+    /**
+        Construct an Ethernet UDP session.
+    **/
+    EthernetUdp();
+
+    /**
+        \brief  Initialize the UDP session and begin listening on the specified
+        local port.
+
+        \param[in] localPort The local port for the UDP session.
+
+        \return success
+    **/
+    bool Begin(uint16_t localPort);
+
+    /**
+        \brief Disable the UDP session.
+    **/
+    void End();
+
+    /**
+        \brief Setup to send a UDP packet to a specified remote.
+
+        \param[in] remoteIp The remote IP address.
+        \param[in] remotePort The remote port.
+
+        \return success
+    **/
+    bool Connect(IpAddress remoteIp, uint16_t remotePort);
+
+    /**
+        \brief Send the UDP packet set up with Connect().
+
+        \return success
+    **/
+    bool PacketSend();
+
+    /**
+        \brief Write data into the outgoing UDP packet.
+
+        Write data into the outgoing UDP packet set up with Connect().
+
+        \param[in] c Character to write.
+
+        \return The number of bytes written into the outgoing UDP packet.
+    **/
+    uint32_t PacketWrite(uint8_t c);
+
+    /**
+        \brief Write data into the outgoing UDP packet.
+
+        Write a string of characters to the UDP packet set up with Connect().
+
+        \param[in] nullTermStr The string to be sent.
+
+        \return The number of bytes written into the outgoing UDP packet.
+    **/
+    uint32_t PacketWrite(const char *nullTermStr);
+
+    /**
+        \brief PacketWrite data into the outgoing UDP packet.
+
+        Write data into the outgoing UDP packet set up with Connect().
+
+        \param[in] buffer A pointer to the beginning of the data to write.
+        \param[in] size The maximum number of bytes to write.
+
+        \return The number of bytes written into the outgoing UDP packet.
+    **/
+    uint32_t PacketWrite(const uint8_t *buffer, uint32_t size);
+
+    /**
+        \brief Check for the newest incoming UDP packet.
+
+        Checks for the newest incoming UDP packet received by the listening
+        UDP session. Moves the packet to be read from by following calls to
+        PacketRead().
+
+        \return The size of the incoming packet in bytes.
+    **/
+    uint16_t PacketParse();
+
+    /**
+        \brief Number of bytes available to read from the current packet.
+
+        \note PacketParse() must be called first to read an incoming packet.
+    **/
+    uint16_t BytesAvailable();
+
+    /**
+        \brief Reads the current packet received from the UDP session.
+
+        \param[out] dataPtr Where to write the data to.
+        \param[in] len Maximum number of bytes to write into dataPtr.
+
+        \return The number of bytes read.
+
+        \note PacketParse() must be called first to read an incoming packet.
+    **/
+    int32_t PacketRead(unsigned char *dataPtr, uint16_t len);
+
+    /**
+        \brief Attempts to get the next available character.
+
+        Attempts to get the next available character without pulling the
+        character out of the incoming packet.
+
+        \return The first character in the incoming packet, or -1 if no data is
+        available.
+
+        \note PacketParse() must be called first to read an incoming packet.
+    **/
+    int16_t Peek();
+
+    /**
+        \brief Flush the current packet.
+    **/
+    void PacketFlush();
+
+    /**
+        \brief Returns the remote IP address for the current packet.
+
+        \return The remote IP address.
+    **/
+    IpAddress RemoteIp();
+
+    /**
+        \brief Returns the remote port for the current packet.
+
+        \return The remote port.
+    **/
+    uint16_t RemotePort();
+
+private:
+    UdpData m_udpData;
+    uint16_t m_udpLocalPort;
+
+    struct pbuf *m_outgoingPacket;
+
+    struct pbuf *m_incomingPacket;
+    uint16_t m_udpBytesAvailable;
+    IpAddress m_udpRemoteIpReceived;
+    uint16_t m_udpRemotePortReceived;
+    IpAddress m_udpRemoteIpDestination;
+    uint16_t m_udpRemotePortDestination;
+
+    // Begin() was called.
+    bool m_initialized;
+    // Connect() was called and we can write to a packet.
+    bool m_packetBegun;
+    // PacketWrite() was called and we can send a packet.
+    bool m_packetReadyToSend;
+    // PacketParse() was called and we can read a packet.
+    bool m_packetParsed;
+
+    uint16_t UdpPacketRead(pbuf *packet, uint16_t *available,
+                           unsigned char *buffer, uint16_t size);
+}; // EthernetUdp
+
+#ifndef HIDE_FROM_DOXYGEN
+
+void UdpReceive(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+                const ip_addr_t *addr, u16_t port);
+
+#endif // !HIDE_FROM_DOXYGEN
+} // ClearCore namespace
+#endif // !__ETHERNETUDP_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetUtils.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetUtils.h
new file mode 100644
index 000000000..6932d94ff
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/EthernetUtils.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+    \file EthernetUtils.h
+**/
+
+#ifndef __ETHERNETUTILS_H__
+#define __ETHERNETUTILS_H__
+
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+
+namespace ClearCore {
+
+#ifndef HIDE_FROM_DOXYGEN
+/**
+    \brief A callback function to be provided to LwIP's DNS lookup functions.
+
+    A queued DNS request will call the callback function once the request has
+    been completed. A DNS request is only queued if the hostname is not already
+    cached in LwIP's DNS table.
+
+    \param hostname The hostname that was queried.
+    \param ip       The result IP address of the hostname, possibly NULL.
+    \param arg      The argument provided to be given to the callback, should
+                    always be an ip_addr_t *.
+**/
+void DnsFound(const char *hostname, const ip_addr_t *ip, void *arg);
+
+/**
+    \brief Attempt to resolve a hostname to an IP Address.
+
+    \param hostname     The hostname to look up.
+    \param remoteIp     The resultant IP Address for the host.
+
+    \return Returns ERR_OK on success, otherwise an error indication.
+**/
+err_t DnsGetHostByName(const char *hostname, ip_addr_t *remoteIp);
+
+#endif // HIDE_FROM_DOXYGEN
+
+} // ClearCore namespace
+
+#endif // !__ETHERNETUTILS_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/HardwareMapping.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/HardwareMapping.h
new file mode 100644
index 000000000..a4297b30b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/HardwareMapping.h
@@ -0,0 +1,1458 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file HardwareMapping.h
+    Maps hardware pins and ports to enums
+**/
+
+#ifndef __HARDWAREMAPPING_H__
+#define __HARDWAREMAPPING_H__
+
+#include <sam.h>
+#include "PeripheralRoute.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+namespace ClearCore {
+
+// g++, please don't spit out pedantic warnings in this file
+// BK: structs and their initializers were generated by a script, so there's
+// no need to complain about missing initializers. We chose to represent the
+// peripheral routing structs to make it clear which fields have which values,
+// as opposed to a class with a constructor, and potentially ambiguous
+// numbers and letters strewn about.
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+
+#ifndef HIDE_FROM_DOXYGEN
+const PeripheralRoute _5VOB_MON = {
+    .pin_raw = 9,
+    .gpioPort = PORTB,
+    .gpioPin = 4,
+    .extInt = 4,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 6,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute Com0_CTS_MISO = {
+    .pin_raw = 67,
+    .gpioPort = PORTB,
+    .gpioPin = 19,
+    .extInt = 3,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 3,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 1,
+    .tccPadNum = 1,
+    .gclkNum = 5,
+};
+const PeripheralRoute Com0_RTS_SS = {
+    .pin_raw = 66,
+    .gpioPort = PORTB,
+    .gpioPin = 18,
+    .extInt = 2,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 2,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 1,
+    .tccPadNum = 0,
+    .gclkNum = 4,
+};
+const PeripheralRoute Com0_RX_SCK = {
+    .pin_raw = 68,
+    .gpioPort = PORTB,
+    .gpioPin = 20,
+    .extInt = 4,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 1,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 1,
+    .tccPadNum = 2,
+    .gclkNum = 6,
+};
+const PeripheralRoute Com0_TX_MOSI = {
+    .pin_raw = 69,
+    .gpioPort = PORTB,
+    .gpioPin = 21,
+    .extInt = 5,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 0,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 1,
+    .tccPadNum = 3,
+    .gclkNum = 7,
+};
+const PeripheralRoute Com1_CTS_MISO = {
+    .pin_raw = 29,
+    .gpioPort = PORTA,
+    .gpioPin = 11,
+    .extInt = 11,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 0,
+    .sercomPadNum = 3,
+    .tcNum = 1,
+    .tcPadNum = 1,
+    .tccNum = 0,
+    .tccPadNum = 3,
+    .gclkNum = 5,
+};
+const PeripheralRoute Com1_RTS_SS = {
+    .pin_raw = 28,
+    .gpioPort = PORTA,
+    .gpioPin = 10,
+    .extInt = 10,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 0,
+    .sercomPadNum = 2,
+    .tcNum = 1,
+    .tcPadNum = 0,
+    .tccNum = 0,
+    .tccPadNum = 2,
+    .gclkNum = 4,
+};
+const PeripheralRoute Com1_RX_SCK = {
+    .pin_raw = 27,
+    .gpioPort = PORTA,
+    .gpioPin = 9,
+    .extInt = 9,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 3,
+    .dacChannel = 255,
+    .sercomNum = 0,
+    .sercomPadNum = 1,
+    .tcNum = 0,
+    .tcPadNum = 1,
+    .tccNum = 0,
+    .tccPadNum = 1,
+    .gclkNum = 255,
+};
+const PeripheralRoute Com1_TX_MOSI = {
+    .pin_raw = 26,
+    .gpioPort = PORTA,
+    .gpioPin = 8,
+    .extInt = 255,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 2,
+    .dacChannel = 255,
+    .sercomNum = 0,
+    .sercomPadNum = 0,
+    .tcNum = 0,
+    .tcPadNum = 0,
+    .tccNum = 0,
+    .tccPadNum = 0,
+    .gclkNum = 255,
+};
+const PeripheralRoute Aout00 = {
+    .pin_raw = 7,
+    .gpioPort = PORTA,
+    .gpioPin = 2,
+    .extInt = 2,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 1,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 0,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN00n_Aout00n = {
+    .pin_raw = 18,
+    .gpioPort = PORTA,
+    .gpioPin = 5,
+    .extInt = 5,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 1,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 0,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN01n = {
+    .pin_raw = 7,
+    .gpioPort = PORTB,
+    .gpioPin = 17,
+    .extInt = 2,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 0,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN02n = {
+    .pin_raw = 8,
+    .gpioPort = PORTA,
+    .gpioPin = 3,
+    .extInt = 3,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN03n = {
+    .pin_raw = 17,
+    .gpioPort = PORTC,
+    .gpioPin = 21,
+    .extInt = 4,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 0,
+    .tcPadNum = 0,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN04n = {
+    .pin_raw = 85,
+    .gpioPort = PORTC,
+    .gpioPin = 27,
+    .extInt = 11,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 0,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN05n = {
+    .pin_raw = 59,
+    .gpioPort = PORTC,
+    .gpioPin = 19,
+    .extInt = 3,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 3,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 3,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN06n_QuadA = {
+    .pin_raw = 56,
+    .gpioPort = PORTC,
+    .gpioPin = 16,
+    .extInt = 0,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 0,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 0,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN07n_QuadB = {
+    .pin_raw = 57,
+    .gpioPort = PORTC,
+    .gpioPin = 17,
+    .extInt = 1,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 1,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 1,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN08n_QuadI = {
+    .pin_raw = 58,
+    .gpioPort = PORTC,
+    .gpioPin = 18,
+    .extInt = 2,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 2,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 2,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN09n_AIN09 = {
+    .pin_raw = 14,
+    .gpioPort = PORTB,
+    .gpioPin = 7,
+    .extInt = 7,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 9,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN10n_AIN10 = {
+    .pin_raw = 13,
+    .gpioPort = PORTB,
+    .gpioPin = 6,
+    .extInt = 6,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 8,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN11n_AIN11 = {
+    .pin_raw = 10,
+    .gpioPort = PORTB,
+    .gpioPin = 5,
+    .extInt = 5,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 7,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute IN12n_AIN12 = {
+    .pin_raw = 6,
+    .gpioPort = PORTC,
+    .gpioPin = 3,
+    .extInt = 3,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 5,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute MicroSD_MISO = {
+    .pin_raw = 32,
+    .gpioPort = PORTB,
+    .gpioPin = 10,
+    .extInt = 10,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 2,
+    .tcNum = 5,
+    .tcPadNum = 0,
+    .tccNum = 0,
+    .tccPadNum = 4,
+    .gclkNum = 4,
+};
+const PeripheralRoute MicroSD_MOSI = {
+    .pin_raw = 15,
+    .gpioPort = PORTB,
+    .gpioPin = 8,
+    .extInt = 8,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 0,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 0,
+    .tcNum = 4,
+    .tcPadNum = 0,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute MicroSD_SCK = {
+    .pin_raw = 16,
+    .gpioPort = PORTB,
+    .gpioPin = 9,
+    .extInt = 9,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 1,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 1,
+    .tcNum = 4,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute MicroSD_SS = {
+    .pin_raw = 61,
+    .gpioPort = PORTA,
+    .gpioPin = 4,
+    .extInt = 5,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 5,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr_CLK_01 = {
+    .pin_raw = 87,
+    .gpioPort = PORTA,
+    .gpioPin = 27,
+    .extInt = 11,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 1,
+};
+const PeripheralRoute Mtr_CLK_23 = {
+    .pin_raw = 79,
+    .gpioPort = PORTB,
+    .gpioPin = 23,
+    .extInt = 7,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 3,
+    .tcNum = 7,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 1,
+};
+const PeripheralRoute Mtr0_An_SCTx = {
+    .pin_raw = 73,
+    .gpioPort = PORTA,
+    .gpioPin = 23,
+    .extInt = 7,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 5,
+    .sercomPadNum = 0,
+    .tcNum = 4,
+    .tcPadNum = 1,
+    .tccNum = 1,
+    .tccPadNum = 7,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr0_B = {
+    .pin_raw = 44,
+    .gpioPort = PORTC,
+    .gpioPin = 14,
+    .extInt = 14,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 2,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 4,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr0_HLFB_SCRx = {
+    .pin_raw = 70,
+    .gpioPort = PORTA,
+    .gpioPin = 20,
+    .extInt = 4,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 5,
+    .sercomPadNum = 2,
+    .tcNum = 7,
+    .tcPadNum = 0,
+    .tccNum = 1,
+    .tccPadNum = 4,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr1_An = {
+    .pin_raw = 71,
+    .gpioPort = PORTA,
+    .gpioPin = 21,
+    .extInt = 5,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 5,
+    .sercomPadNum = 3,
+    .tcNum = 7,
+    .tcPadNum = 1,
+    .tccNum = 1,
+    .tccPadNum = 5,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr1_B = {
+    .pin_raw = 45,
+    .gpioPort = PORTC,
+    .gpioPin = 15,
+    .extInt = 15,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 3,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 5,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr1_HLFB = {
+    .pin_raw = 33,
+    .gpioPort = PORTB,
+    .gpioPin = 11,
+    .extInt = 11,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 5,
+    .tcPadNum = 1,
+    .tccNum = 0,
+    .tccPadNum = 5,
+    .gclkNum = 5,
+};
+const PeripheralRoute Mtr2_An_Sdrvr2_PWMA = {
+    .pin_raw = 72,
+    .gpioPort = PORTA,
+    .gpioPin = 22,
+    .extInt = 6,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 3,
+    .sercomPadNum = 0,
+    .tcNum = 4,
+    .tcPadNum = 0,
+    .tccNum = 1,
+    .tccPadNum = 6,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr2_B_Sdrvr2_PWMB = {
+    .pin_raw = 43,
+    .gpioPort = PORTC,
+    .gpioPin = 13,
+    .extInt = 13,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 1,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 3,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr2_HLFB_Sdrvr2_Trig = {
+    .pin_raw = 84,
+    .gpioPort = PORTC,
+    .gpioPin = 26,
+    .extInt = 10,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr3_An_Sdrvr3_PWMA = {
+    .pin_raw = 52,
+    .gpioPort = PORTA,
+    .gpioPin = 16,
+    .extInt = 0,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 0,
+    .tcNum = 2,
+    .tcPadNum = 0,
+    .tccNum = 1,
+    .tccPadNum = 0,
+    .gclkNum = 2,
+};
+const PeripheralRoute Mtr3_B_Sdrvr3_PWMB = {
+    .pin_raw = 40,
+    .gpioPort = PORTC,
+    .gpioPin = 10,
+    .extInt = 10,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 2,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 0,
+    .gclkNum = 255,
+};
+const PeripheralRoute Mtr3_HLFB_Sdrvr3_Trig = {
+    .pin_raw = 96,
+    .gpioPort = PORTB,
+    .gpioPin = 31,
+    .extInt = 15,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 0,
+    .tcPadNum = 1,
+    .tccNum = 4,
+    .tccPadNum = 1,
+    .gclkNum = 255,
+};
+const PeripheralRoute OUT00 = {
+    .pin_raw = 1,
+    .gpioPort = PORTA,
+    .gpioPin = 0,
+    .extInt = 0,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 2,
+    .tcPadNum = 0,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute OUT01 = {
+    .pin_raw = 2,
+    .gpioPort = PORTA,
+    .gpioPin = 1,
+    .extInt = 1,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 2,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute OUT02 = {
+    .pin_raw = 19,
+    .gpioPort = PORTA,
+    .gpioPin = 6,
+    .extInt = 6,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 1,
+    .tcPadNum = 0,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute OUT03 = {
+    .pin_raw = 20,
+    .gpioPort = PORTA,
+    .gpioPin = 7,
+    .extInt = 7,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 1,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute OUT04_ENABLE04 = {
+    .pin_raw = 64,
+    .gpioPort = PORTB,
+    .gpioPin = 16,
+    .extInt = 0,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 5,
+    .sercomPadNum = 0,
+    .tcNum = 6,
+    .tcPadNum = 0,
+    .tccNum = 3,
+    .tccPadNum = 0,
+    .gclkNum = 2,
+};
+const PeripheralRoute OUT05_ENABLE05 = {
+    .pin_raw = 100,
+    .gpioPort = PORTB,
+    .gpioPin = 3,
+    .extInt = 3,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 6,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute OutFault_04or05 = {
+    .pin_raw = 97,
+    .gpioPort = PORTB,
+    .gpioPin = 0,
+    .extInt = 0,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 7,
+    .tcPadNum = 0,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_INT = {
+    .pin_raw = 86,
+    .gpioPort = PORTC,
+    .gpioPin = 28,
+    .extInt = 12,
+    .extIntAvail = true,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 1,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_MDC = {
+    .pin_raw = 41,
+    .gpioPort = PORTC,
+    .gpioPin = 11,
+    .extInt = 11,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 3,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 1,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_MDIO = {
+    .pin_raw = 42,
+    .gpioPort = PORTC,
+    .gpioPin = 12,
+    .extInt = 12,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 7,
+    .sercomPadNum = 0,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 2,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_RXD0 = {
+    .pin_raw = 47,
+    .gpioPort = PORTA,
+    .gpioPin = 13,
+    .extInt = 13,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 1,
+    .tcNum = 2,
+    .tcPadNum = 1,
+    .tccNum = 0,
+    .tccPadNum = 7,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_RXD1 = {
+    .pin_raw = 46,
+    .gpioPort = PORTA,
+    .gpioPin = 12,
+    .extInt = 12,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 0,
+    .tcNum = 2,
+    .tcPadNum = 0,
+    .tccNum = 0,
+    .tccPadNum = 6,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_RXDV = {
+    .pin_raw = 60,
+    .gpioPort = PORTC,
+    .gpioPin = 20,
+    .extInt = 4,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 0,
+    .tccPadNum = 4,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_RXER = {
+    .pin_raw = 49,
+    .gpioPort = PORTA,
+    .gpioPin = 15,
+    .extInt = 15,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 3,
+    .tcNum = 3,
+    .tcPadNum = 1,
+    .tccNum = 2,
+    .tccPadNum = 1,
+    .gclkNum = 1,
+};
+const PeripheralRoute PHY_TXCLK = {
+    .pin_raw = 48,
+    .gpioPort = PORTA,
+    .gpioPin = 14,
+    .extInt = 14,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 2,
+    .tcNum = 3,
+    .tcPadNum = 0,
+    .tccNum = 2,
+    .tccPadNum = 0,
+    .gclkNum = 0,
+};
+const PeripheralRoute PHY_TXD0 = {
+    .pin_raw = 54,
+    .gpioPort = PORTA,
+    .gpioPin = 18,
+    .extInt = 2,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 2,
+    .tcNum = 3,
+    .tcPadNum = 0,
+    .tccNum = 1,
+    .tccPadNum = 2,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_TXD1 = {
+    .pin_raw = 55,
+    .gpioPort = PORTA,
+    .gpioPin = 19,
+    .extInt = 3,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 3,
+    .tcNum = 3,
+    .tcPadNum = 1,
+    .tccNum = 1,
+    .tccPadNum = 3,
+    .gclkNum = 255,
+};
+const PeripheralRoute PHY_TXEN = {
+    .pin_raw = 53,
+    .gpioPort = PORTA,
+    .gpioPin = 17,
+    .extInt = 1,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 1,
+    .tcNum = 2,
+    .tcPadNum = 1,
+    .tccNum = 1,
+    .tccPadNum = 1,
+    .gclkNum = 3,
+};
+const PeripheralRoute Polarity04_PWM04A = {
+    .pin_raw = 36,
+    .gpioPort = PORTB,
+    .gpioPin = 14,
+    .extInt = 14,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 2,
+    .tcNum = 5,
+    .tcPadNum = 0,
+    .tccNum = 4,
+    .tccPadNum = 0,
+    .gclkNum = 0,
+};
+const PeripheralRoute Polarity04S_PWM04B = {
+    .pin_raw = 37,
+    .gpioPort = PORTB,
+    .gpioPin = 15,
+    .extInt = 15,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 3,
+    .tcNum = 5,
+    .tcPadNum = 1,
+    .tccNum = 4,
+    .tccPadNum = 1,
+    .gclkNum = 1,
+};
+const PeripheralRoute Polarity05_PWM05A = {
+    .pin_raw = 34,
+    .gpioPort = PORTB,
+    .gpioPin = 12,
+    .extInt = 12,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 0,
+    .tcNum = 4,
+    .tcPadNum = 0,
+    .tccNum = 3,
+    .tccPadNum = 0,
+    .gclkNum = 6,
+};
+const PeripheralRoute Polarity05S_PWM05B = {
+    .pin_raw = 35,
+    .gpioPort = PORTB,
+    .gpioPin = 13,
+    .extInt = 13,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 4,
+    .sercomPadNum = 1,
+    .tcNum = 4,
+    .tcPadNum = 1,
+    .tccNum = 3,
+    .tccPadNum = 1,
+    .gclkNum = 7,
+};
+const PeripheralRoute RESETn = {
+    .pin_raw = 88,
+    .gpioPort = NOT_A_PORT,
+    .gpioPin = 0,
+    .extInt = 255,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute Sdrvr2_iMon = {
+    .pin_raw = 4,
+    .gpioPort = PORTC,
+    .gpioPin = 1,
+    .extInt = 1,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 11,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute Sdrvr3_iMon = {
+    .pin_raw = 3,
+    .gpioPort = PORTC,
+    .gpioPin = 0,
+    .extInt = 0,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 10,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute SR_CLK = {
+    .pin_raw = 21,
+    .gpioPort = PORTC,
+    .gpioPin = 5,
+    .extInt = 5,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 1,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute SR_DATA = {
+    .pin_raw = 23,
+    .gpioPort = PORTC,
+    .gpioPin = 7,
+    .extInt = 9,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 3,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute SR_DATA_RET = {
+    .pin_raw = 22,
+    .gpioPort = PORTC,
+    .gpioPin = 6,
+    .extInt = 6,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 6,
+    .sercomPadNum = 2,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute SR_ENn = {
+    .pin_raw = 98,
+    .gpioPort = PORTB,
+    .gpioPin = 1,
+    .extInt = 1,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 7,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute SR_LOAD = {
+    .pin_raw = 99,
+    .gpioPort = PORTB,
+    .gpioPin = 2,
+    .extInt = 2,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 6,
+    .tcPadNum = 0,
+    .tccNum = 2,
+    .tccPadNum = 2,
+    .gclkNum = 255,
+};
+const PeripheralRoute SWCLK = {
+    .pin_raw = 93,
+    .gpioPort = PORTA,
+    .gpioPin = 30,
+    .extInt = 14,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 2,
+    .tcNum = 6,
+    .tcPadNum = 0,
+    .tccNum = 2,
+    .tccPadNum = 0,
+    .gclkNum = 0,
+};
+const PeripheralRoute SWDIO = {
+    .pin_raw = 94,
+    .gpioPort = PORTA,
+    .gpioPin = 31,
+    .extInt = 15,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 3,
+    .tcNum = 6,
+    .tcPadNum = 1,
+    .tccNum = 2,
+    .tccPadNum = 1,
+    .gclkNum = 255,
+};
+const PeripheralRoute SWO = {
+    .pin_raw = 95,
+    .gpioPort = PORTB,
+    .gpioPin = 30,
+    .extInt = 14,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 5,
+    .sercomPadNum = 1,
+    .tcNum = 0,
+    .tcPadNum = 0,
+    .tccNum = 4,
+    .tccPadNum = 0,
+    .gclkNum = 255,
+};
+const PeripheralRoute SYS_CLK = {
+    .pin_raw = 78,
+    .gpioPort = PORTB,
+    .gpioPin = 22,
+    .extInt = 6,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 1,
+    .sercomPadNum = 2,
+    .tcNum = 7,
+    .tcPadNum = 0,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 0,
+};
+const PeripheralRoute USB_DM = {
+    .pin_raw = 74,
+    .gpioPort = PORTA,
+    .gpioPin = 24,
+    .extInt = 8,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 3,
+    .sercomPadNum = 2,
+    .tcNum = 5,
+    .tcPadNum = 0,
+    .tccNum = 2,
+    .tccPadNum = 2,
+    .gclkNum = 255,
+};
+const PeripheralRoute USB_DP = {
+    .pin_raw = 75,
+    .gpioPort = PORTA,
+    .gpioPin = 25,
+    .extInt = 9,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 3,
+    .sercomPadNum = 3,
+    .tcNum = 5,
+    .tcPadNum = 1,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute Vsupply_MON_IO_4and5_RST = {
+    .pin_raw = 5,
+    .gpioPort = PORTC,
+    .gpioPin = 2,
+    .extInt = 2,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 4,
+    .dacChannel = 255,
+    .sercomNum = 255,
+    .sercomPadNum = 255,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute XBee_CTS_IN = {
+    .pin_raw = 83,
+    .gpioPort = PORTC,
+    .gpioPin = 25,
+    .extInt = 9,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 3,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute XBee_RTS_OUT = {
+    .pin_raw = 82,
+    .gpioPort = PORTC,
+    .gpioPin = 24,
+    .extInt = 8,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 2,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute XBee_Rx_IN = {
+    .pin_raw = 80,
+    .gpioPort = PORTB,
+    .gpioPin = 24,
+    .extInt = 8,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 1,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+const PeripheralRoute XBee_Tx_OUT = {
+    .pin_raw = 81,
+    .gpioPort = PORTB,
+    .gpioPin = 25,
+    .extInt = 9,
+    .extIntAvail = false,
+    .adc0Channel = 255,
+    .adc1Channel = 255,
+    .dacChannel = 255,
+    .sercomNum = 2,
+    .sercomPadNum = 0,
+    .tcNum = 255,
+    .tcPadNum = 255,
+    .tccNum = 255,
+    .tccPadNum = 255,
+    .gclkNum = 255,
+};
+#endif // HIDE_FROM_DOXYGEN
+
+// start complaining about -Wpedantic and -Wmissing-field-initializers again
+#pragma GCC diagnostic pop
+
+} // ClearCore namespace
+
+#ifdef __cplusplus
+#include "Connector.h"
+}
+#endif
+
+#endif // __HARDWAREMAPPING_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ISerial.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ISerial.h
new file mode 100644
index 000000000..4b7b8d3e3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ISerial.h
@@ -0,0 +1,552 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+ *    \file ISerial.h
+ *    \brief A standardized ClearCore Serial interface.
+ *
+ *    Provides a Serial API for USB coms to match standard coms.
+ **/
+
+
+#ifndef ISERIAL_H_
+#define ISERIAL_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+namespace ClearCore {
+/**
+    \class ISerial
+    \brief Base class for interacting with all ClearCore serial.
+
+    This virtual class defines the common functionality for a serial object.
+
+    It provides a generic interface that all serial objects have. This includes
+    - Port Opening/Closing
+    - Communication configuration
+**/
+class ISerial {
+public:
+
+    /**
+        Different types of transmission formats
+    **/
+    typedef enum _Parities {
+        /// Even Parity
+        PARITY_E = 0,
+        /// Odd Parity
+        PARITY_O,
+        /// No Parity
+        PARITY_N,
+    } Parities;
+
+    /**
+        Flush the serial port's transmit buffer
+
+        \code{.cpp}
+        // Flush COM-0's transmit buffer
+        ConnectorCOM0.Flush();
+        \endcode
+    **/
+    virtual void Flush() = 0;
+    /**
+        Flush the serial port's receive buffer
+
+        \code{.cpp}
+        // Flush COM-0's receive buffer
+        ConnectorCOM0.FlushInput();
+        \endcode
+    **/
+    virtual void FlushInput() = 0;
+
+    /**
+        Set up the port to allow operations
+
+        \code{.cpp}
+        // Open COM-0's serial port
+        ConnectorCOM0.PortOpen();
+        \endcode
+    **/
+    virtual void PortOpen() = 0;
+
+    /**
+        Shut down the port
+
+        \code{.cpp}
+        // Close COM-0's serial port
+        ConnectorCOM0.PortClose();
+        \endcode
+    **/
+    virtual void PortClose() = 0;
+
+    /**
+        \brief Change the baud rate for the port.
+
+        \code{.cpp}
+        if (ConnectorCOM0.Speed(9600)) {
+            // Setting COM-0's baud to 9600 bps was successful
+        }
+        \endcode
+
+        \param[in] bitsPerSecond The new speed setting
+        \return Returns true if port accepted the speed request.
+    **/
+    virtual bool Speed(uint32_t bitsPerSecond) = 0;
+
+    /**
+        \brief Gets the baud rate of the port.
+
+        \code{.cpp}
+        // Saves COM-0's current speed setting
+        uint32_t serialSpeed = ConnectorCOM1.Speed();
+        \endcode
+
+        \return Returns port speed in bits per second.
+    **/
+    virtual uint32_t Speed() = 0;
+
+    /**
+        \brief Attempt to read the next character from serial channel.
+
+        \return Returns the first character in the serial buffer, or
+        SerialBase#EOB if no data are available. If a character is found, it
+        will be consumed and removed from the serial buffer.
+    **/
+    virtual int16_t CharGet() = 0;
+
+    /**
+        \brief Attempt to get the next character from the serial channel without
+        pulling the character out of the buffer.
+
+        \return Returns the first character in the serial buffer, or
+        SerialBase#EOB if no data are available. If a character is found, it
+        will not be consumed, and will remain in the serial buffer for reading.
+    **/
+    virtual int16_t CharPeek() = 0;
+
+    /**
+        \brief Send an ascii character on the serial channel.
+
+        \param[in] charToSend The character to be sent
+        \return success
+    **/
+    virtual bool SendChar(uint8_t charToSend) = 0;
+
+    /**
+        \brief Send carriage return and newline characters.
+
+        \return success
+    **/
+    bool SendLine() {
+        return SendChar('\r') && SendChar('\n');
+    }
+
+    /**
+        \brief Send the array of characters out the port.
+
+        \param[in] buffer The array of characters to be sent
+        \param[in] bufferSize The number of characters to be sent
+        \return success
+    **/
+    bool Send(const char *buffer, size_t bufferSize) {
+        for (size_t iChar = 0; iChar < bufferSize; iChar++) {
+            if (!SendChar(buffer[iChar])) {
+                return false;
+            }
+        }
+        return true;
+    }
+
+    /**
+        \brief Send the array of characters out the port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] buffer The array of characters to be sent
+        \param[in] bufferSize The number of characters to be sent
+        \return success
+    **/
+    bool SendLine(const char *buffer, size_t bufferSize) {
+        return Send(buffer, bufferSize) && SendLine();
+    }
+
+    /**
+        \brief Send a string of characters out the port.
+
+        \param[in] nullTermStr The string to be sent
+        \return success
+    **/
+    bool Send(const char *nullTermStr) {
+        return Send(nullTermStr, strlen(nullTermStr));
+    }
+
+    /**
+        \brief Send a string of characters out the port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] nullTermStr The string to be sent
+        \return success
+    **/
+    bool SendLine(const char *nullTermStr) {
+        return Send(nullTermStr) && SendLine();
+    }
+
+    /**
+        \brief Send a character to be printed to the serial port.
+
+        \param[in] theChar The ascii character to be printed.
+        \return success
+    **/
+    bool Send(char theChar) {
+        return SendChar(theChar);
+    }
+
+    /**
+        \brief Send a character to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] theChar The ascii character to be printed.
+        \return success
+    **/
+    bool SendLine(char theChar) {
+        return Send(theChar) && SendLine();
+    }
+
+    /**
+        \brief Send a floating point number to the serial port.
+
+        \param[in] number The double precision float value to be printed.
+        \param[in] precision (optional) The number of digits to print after the
+        decimal point. Default: 2.
+        \note The string representation is capped at 20 characters.
+        \return success
+    **/
+    bool Send(double number, uint8_t precision = 2) {
+        char buffer[20];
+        snprintf(buffer, sizeof(buffer), "%.*f", precision, number);
+        return Send(buffer);
+    }
+
+    /**
+        \brief Send a floating point number to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The double precision float value to be printed.
+        \param[in] precision (optional) The number of digits to print after the
+        decimal point. Default: 2.
+        \note The string representation is capped at 20 characters.
+        \return success
+    **/
+    bool SendLine(double number, uint8_t precision = 2) {
+        return Send(number, precision) && SendLine();
+    }
+
+    /**
+        \brief Send an 8-bit signed number to be printed to the serial port.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(int8_t number, uint8_t radix = 10) {
+        return Send(static_cast<int32_t>(number), radix);
+    }
+
+    /**
+        \brief Send an 8-bit signed number to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(int8_t number, uint8_t radix = 10) {
+        return SendLine(static_cast<int32_t>(number), radix);
+    }
+
+    /**
+        \brief Send an 8-bit unsigned number to be printed to the serial port.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(uint8_t number, uint8_t radix = 10) {
+        return Send(static_cast<uint32_t>(number), radix);
+    }
+
+    /**
+        \brief Send an 8-bit unsigned number to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(uint8_t number, uint8_t radix = 10) {
+        return SendLine(static_cast<uint32_t>(number), radix);
+    }
+
+    /**
+        \brief Send a 16-bit signed number to be printed to the serial port.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(int16_t number, uint8_t radix = 10) {
+        return Send(static_cast<int32_t>(number), radix);
+    }
+
+    /**
+        \brief Send a 16-bit signed number to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(int16_t number, uint8_t radix = 10) {
+        return SendLine(static_cast<int32_t>(number), radix);
+    }
+
+    /**
+        \brief Send a 16-bit unsigned number to be printed to the serial port.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(uint16_t number, uint8_t radix = 10) {
+        return Send(static_cast<uint32_t>(number), radix);
+    }
+
+    /**
+        \brief Send a 16-bit unsigned number to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(uint16_t number, uint8_t radix = 10) {
+        return SendLine(static_cast<uint32_t>(number), radix);
+    }
+
+    /**
+        \brief Send a 32-bit signed number to be printed to the serial port.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(int32_t number, uint8_t radix = 10) {
+        if (radix < 2 || radix > 16) {
+            // Only support bases 2 through 16.
+            return false;
+        }
+        char strRep[2 + 8 * sizeof(number)];
+        itoa(number, strRep, radix);
+        Send((const char *)strRep);
+        return true;
+    }
+
+    /**
+        \brief Send a 32-bit signed number to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(int32_t number, uint8_t radix = 10) {
+        return Send(number, radix) && SendLine();
+    }
+
+    /**
+        \brief Send a 32-bit unsigned number to be printed to the serial port.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(uint32_t number, uint8_t radix = 10) {
+        if (radix < 2 || radix > 16) {
+            // Only support bases 2 through 16.
+            return false;
+        }
+        char strRep[1 + 8 * sizeof(number)];
+        utoa(number, strRep, radix);
+        Send((const char *)strRep);
+        return true;
+    }
+
+    /**
+        \brief Send a 32-bit unsigned number to be printed to the serial port.
+        Terminate the line with carriage return and newline characters.
+
+        \param[in] number The value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(uint32_t number, uint8_t radix = 10) {
+        return Send(number, radix) && SendLine();
+    }
+
+    /**
+        \brief Send an integer to be printed to the serial port.
+
+        \param[in] number The integer value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool Send(int number, uint8_t radix = 10) {
+        return Send(static_cast<int32_t>(number), radix);
+    }
+
+    /**
+        \brief Send an integer to be printed to the serial port.
+
+        \param[in] number The integer value to be printed.
+        \param[in] radix (optional) The base in which to display the character
+        representation of \a number. Default: 10.
+        \return success
+    **/
+    bool SendLine(int number, uint8_t radix = 10) {
+        return SendLine(static_cast<int32_t>(number), radix);
+    }
+
+    /**
+        Returns number of characters waiting in the receive buffer.
+    **/
+    virtual int32_t AvailableForRead() = 0;
+
+    /**
+        \brief Determines the number of characters available in the transmit
+        buffer.
+
+        \code{.cpp}
+        if (ConnectorCOM0.AvailableForWrite() < 10) {
+            // There are less than 10 free characters in COM-0's transmit buffer
+        }
+        \endcode
+
+        \return Returns number of free characters in transmit buffer
+    **/
+    virtual int32_t AvailableForWrite() = 0;
+
+    /**
+        Wait for transmission idle.
+    **/
+    virtual void WaitForTransmitIdle() = 0;
+
+    /**
+        \brief Return whether or not the port is open
+
+        \code{.cpp}
+        if (ConnectorCOM0.PortIsOpen()) {
+            // COM-0's port is currently open
+        }
+        \endcode
+
+        \return True if the port is open, and false otherwise.
+    **/
+    virtual bool PortIsOpen() = 0;
+
+    /**
+        Returns whether the serial port is open and the other end is connected.
+    **/
+    virtual operator bool() = 0;
+
+    /**
+        \brief Set UART transmission parity format.
+
+        \code{.cpp}
+        if (ConnectorCOM0.Parity(SerialBase::PARITY_O)) {
+            // Setting COM-0's parity format to odd was successful
+        }
+        \endcode
+
+        \param[in] newParity The new parity to be set
+        \return Returns true if port accepted the format change request.
+    **/
+    virtual bool Parity(Parities newParity) = 0;
+
+    /**
+        \brief Return current port UART transmission format.
+
+        \code{.cpp}
+        if (ConnectorCOM0.Parity() == SerialBase::PARITY_O) {
+            // COM-0's parity format is set to odd
+        }
+        \endcode
+
+        \return Returns transmission format enumeration.
+    **/
+    virtual Parities Parity() = 0;
+
+    /**
+        Change the number of stop bits used in UART communication.
+
+        \code{.cpp}
+        if (ConnectorCOM0.StopBits(2)) {
+            // Setting COM-0's stop bits was successful
+        }
+        \endcode
+    **/
+    virtual bool StopBits(uint8_t bits) = 0;
+
+    /**
+        \brief Change the number of bits in a character.
+
+        \code{.cpp}
+        if (ConnectorCOM0.CharSize(9)) {
+            // Setting COM-0's character size was successful
+        }
+        \endcode
+
+        \param[in] size The new character size to be set
+        \note For UART mode valid settings are: 5,6,7,8,9.
+        For SPI mode valid settings are: 8, 9.
+    **/
+    virtual bool CharSize(uint8_t size) = 0;
+
+};
+
+} // ClearCore namespace
+
+#endif /* ISERIAL_H_ */
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/IirFilter.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/IirFilter.h
new file mode 100644
index 000000000..fc40b467f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/IirFilter.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __IIRFILTER_H__
+#define __IIRFILTER_H__
+
+#include <math.h>
+#include "SysTiming.h"
+
+#ifndef HIDE_FROM_DOXYGEN
+namespace ClearCore {
+
+//*****************************************************************************
+// NAME                                                                       *
+//  Iir16 class
+//
+// DESCRIPTION
+///     \brief An IIR filter that filters a 16-bit input and provides a 16-bit
+///     output.
+///
+///     The classic form is:
+///     output = (1-K)*input + K*output
+///
+///     The DSP efficient form is:
+///            = input - K*input + K*output
+//
+class Iir16 {
+public:
+    Iir16(void) : m_tc(0), m_z(0) {};
+
+    /**
+        Update the output with this input and return new output.
+    **/
+    void Update(uint16_t input) {
+        m_z = ((static_cast<int64_t>(m_z) * m_tc) >> 15) -
+              ((static_cast<int32_t>(input) * m_tc) << 1) +
+              (static_cast<int32_t>(input) << 16);
+    }
+    /**
+        \return Return the last output
+    **/
+    uint16_t LastOutput() {
+        return (m_z >> 16);
+    };
+
+    /**
+        Set TC
+    **/
+    void Tc(uint16_t newTc) {
+        m_tc = newTc;
+    };
+
+    /**
+        Get TC
+    **/
+    uint16_t Tc() {
+        return m_tc;
+    };
+
+    void TcSamples(uint16_t riseSamples99pct) {
+        float tcTemp = powf(.01, 1. / riseSamples99pct) * 32768 + 0.5;
+        m_tc = (tcTemp < INT16_MAX) ? tcTemp : INT16_MAX;
+    }
+
+    uint16_t TcSamples() {
+        return logf(0.01) / logf(m_tc / 32768.);
+    }
+
+    uint16_t Tc_ms() {
+        return TcSamples() / MS_TO_SAMPLES;
+    }
+
+    void Tc_ms(uint16_t riseMs99pct) {
+        TcSamples(riseMs99pct * MS_TO_SAMPLES);
+    }
+
+    // Reset the filter to this level
+    void Reset(uint16_t newSetting) {
+        m_z = (newSetting << 16);
+    }
+
+private:
+    uint16_t m_tc; // Filter time constant (positive)
+    int32_t m_z;  // "Z" output/accumulator
+};
+
+} // ClearCore namespace
+#endif // HIDE_FROM_DOXYGEN
+#endif // #ifndef __IIRFILTER_H__
+//                                                                            *
+//*****************************************************************************
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/InputManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/InputManager.h
new file mode 100644
index 000000000..5e6463080
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/InputManager.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file InputManager.h
+    \brief ClearCore input state access.
+
+    Provides consolidated access to the input state of all of the ClearCore
+    connectors.
+**/
+
+
+#ifndef __INPUTMANAGER_H__
+#define __INPUTMANAGER_H__
+
+#include "PeripheralRoute.h"
+#include "SysConnectors.h"
+
+namespace ClearCore {
+
+typedef void (*voidFuncPtr)(void);
+
+/**
+    \brief ClearCore input state access.
+
+    Provides consolidated access to the input state of all of the ClearCore
+    connectors.
+**/
+class InputManager {
+    friend class DigitalIn;
+    friend class SerialBase;
+    friend class TestIO;
+public:
+    /**
+        \enum InterruptTrigger
+
+        \brief The possible input state conditions to trigger an interrupt on.
+    **/
+    typedef enum {
+        NONE = -1,
+        LOW = 0,
+        HIGH = 1,
+        CHANGE = 2,
+        FALLING = 3,
+        RISING = 4,
+    } InterruptTrigger;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for singleton instance.
+    **/
+    static InputManager &Instance();
+#endif
+
+    /**
+        \brief Clear on read accessor for inputs that have risen (transitioned
+        from deasserted to asserted) sometime since the previous invocation of
+        this function.
+        \param [in] mask (optional) A SysConnectorState whose asserted bits
+        indicate which of the ClearCore inputs to check for rising edges.
+        If one of the \a bit members of this mask are deasserted, that bit will
+        be ignored when checking for rising edges. If no \a mask is provided,
+        it's equivalent to passing a SysConnectorState with all bits asserted,
+        in which case this function would report rising edges on any of the
+        ClearCore inputs.
+
+        \code{.cpp}
+        // Utilize the full InputMgr Register to view rising edges.
+        uint32_t inputRisenReg = InputMgr.InputsRisen().reg;
+        if (inputRisenReg) {
+            // The state of one or more inputs has risen since the
+            // last time InputsRisen() was called.
+        }
+        \endcode
+
+        \return StatusRegister whose asserted bits indicate which ClearCore
+        inputs have risen since the last poll.
+    **/
+    SysConnectorState InputsRisen(SysConnectorState mask = UINT32_MAX);
+
+    /**
+        \brief Clear on read accessor for inputs that have fallen (transitioned
+        from asserted to deasserted) sometime since the previous invocation of
+        this function.
+        \param [in] mask (optional) A SysConnectorState whose asserted bits
+        indicate which of the ClearCore inputs to check for falling edges.
+        If one of the \a bit members of this mask are deasserted, that bit will
+        be ignored when checking for falling edges. If no \a mask is provided,
+        it's equivalent to passing a SysConnectorState with all bits asserted,
+        in which case this function would report falling edges on any of the
+        ClearCore inputs.
+
+        \code{.cpp}
+        // Generate a mask to filter only the falling edges we care to see.
+        SysConnectorState mask;
+        mask.bit.CLEARCORE_PIN_IO0 = 1;
+        mask.bit.CLEARCORE_PIN_IO1 = 1;
+        uint32_t inputFallenReg = InputMgr.InputsFallen(mask).reg;
+        if (inputFallenReg) {
+            // The state of either IO-0 or IO-1 has fallen since the
+            // last time InputsFallen() was called.
+        }
+        \endcode
+
+        \return StatusRegister whose asserted bits indicate which ClearCore
+        inputs have fallen since the last poll.
+    **/
+    SysConnectorState InputsFallen(SysConnectorState mask = UINT32_MAX);
+
+    /**
+        \brief Current state of the on-board ClearCore inputs.
+        \param [in] mask (optional) A SysConnectorState whose asserted bits
+        indicate which of the ClearCore inputs to check for falling edges.
+        If one of the \a bit members of this mask are deasserted, that bit will
+        be ignored when checking for falling edges. If no \a mask is provided,
+        it's equivalent to passing a SysConnectorState with all bits asserted,
+        in which case this function would report falling edges on any of the
+        ClearCore inputs.
+
+        \code{.cpp}
+        // Save the current state of all inputs for future use
+        SysConnectorState currState = InputMgr.InputsRT();
+        \endcode
+
+        \return SysConnectorState whose asserted bits indicate ClearCore inputs
+        that are currently asserted.
+    **/
+    SysConnectorState InputsRT(SysConnectorState mask = UINT32_MAX);
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Enable or disable the interrupt on a digital input connector with
+        the supplied external interrupt number.
+
+        \param[in] extInt The external interrupt line number associated with a
+        digital input connector that can trigger interrupts.
+        \param[in] enable If true, enable the interrupt. If false, disable the
+        interrupt.
+
+        \note Only connectors DI-6 through A-12 can trigger interrupts.
+    **/
+    void InterruptEnable(int8_t extInt, bool enable, bool clearPending = false);
+#endif
+
+    /**
+        \brief Enable or disable digital interrupts board-wide.
+
+        \code{.cpp}
+        // Set up an interrupt callback for 2 connectors
+        ConnectorDI7.InterruptHandlerSet(&myCallback, InputManager::RISING);
+        ConnectorDI8.InterruptHandlerSet(&myCallback, InputManager::RISING);
+        // Enable both interrupts at once
+        InputMgr.InterruptsEnabled(true);
+        \endcode
+
+        \note Only connectors DI-6 through A-12 can trigger interrupts.
+        \note DigitalIn has a connector-specific version of this function as a
+        class member.
+    **/
+    void InterruptsEnabled(bool enable);
+
+    /**
+        \brief Current enable state of digital interrupts.
+
+        \code{.cpp}
+        if (InputMgr.InterruptsEnabled()) {
+            // Input interrupts are globally enabled, do something (like disable
+            // them).
+        }
+        \endcode
+
+        \return true if interrupts are enabled board-wide, false if not.
+
+        \note Only connectors DI-6 through A-12 can trigger interrupts.
+    **/
+    bool InterruptsEnabled() {
+        return m_interruptsEnabled;
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Register the interrupt service routine to be triggered when the
+        given input state condition is met on the connector with the supplied
+        external interrupt number.
+
+        \param[in] extInt The external interrupt line number associated with a
+        digital input connector that can trigger interrupts.
+        \param[in] callback (optional) The ISR to be called when the interrupt
+        is triggered. Default: nullptr.
+        \param[in] trigger (optional) The input state condition on which to
+        trigger the interrupt. Default: RISING.
+        \param[in] enable (optional) Whether this interrupt should be
+        immediately enabled. Default: true.
+        \return true if the ISR was registered successfully, false otherwise.
+    **/
+    bool InterruptHandlerSet(int8_t extInt,
+                             voidFuncPtr callback = nullptr,
+                             InterruptTrigger trigger = RISING,
+                             bool enable = true,
+                             bool oneTime = false);
+
+    /**
+        Initialize the InputManager.
+    **/
+    void Initialize();
+
+    /**
+        Refresh the input register snapshots and see
+        which bits have changed since the last update.
+    **/
+    void UpdateBegin();
+
+    /**
+        At the end of the sample time, update Rise/Fall registers.
+    **/
+    void UpdateEnd();
+
+    /**
+        Main external interrupt handler.
+    **/
+    void EIC_Handler(uint8_t index);
+#endif
+private:
+    // State of the unfiltered input port registers from the DSP.
+    volatile uint32_t *m_inputPtrs[CLEARCORE_PORT_MAX];
+    uint32_t m_inputsUnfiltered[CLEARCORE_PORT_MAX];
+    uint32_t m_inputsUnfilteredChanges[CLEARCORE_PORT_MAX];
+
+    // Filtered input registers
+    // Real Time register for FILTERED values
+    SysConnectorState m_inputRegRT;
+    // Last sample time register for FILTERED values
+    SysConnectorState m_inputRegLast;
+    // Rising Edge register for FILTERED values
+    SysConnectorState m_inputRegRisen;
+    // Falling Edge register for FILTERED values
+    SysConnectorState m_inputRegFallen;
+    // End input registers
+
+    // A mask representing all connectors with registered ISRs.
+    uint32_t m_interruptsMask;
+    // Are interrupts enabled across the board?
+    bool m_interruptsEnabled;
+    // Registered interrupt service routines
+    voidFuncPtr m_interruptServiceRoutines[EIC_NUMBER_OF_INTERRUPTS];
+    // Bitmask indicating which interrupt handlers disable after triggerring
+    uint16_t m_oneTimeFlags;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct
+    **/
+    InputManager();
+
+    // Configure the addresses to read the inputs from
+    void SetInputRegisters(volatile uint32_t *a,
+                           volatile uint32_t *b,
+                           volatile uint32_t *c);
+
+    /**
+        Translates the \a trigger to the EIC config sense setting.
+    **/
+    uint32_t EicSense(InterruptTrigger trigger);
+
+#endif // !HIDE_FROM_DOXYGEN
+}; // InputManager
+
+} // ClearCore namespace
+
+#endif /* __INPUTMANAGER_H__ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/IpAddress.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/IpAddress.h
new file mode 100644
index 000000000..da8291751
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/IpAddress.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file IpAddress.h
+
+    A wrapper class for an IPv4 IP Address.
+**/
+
+
+#ifndef __IPADDR_H__
+#define __IPADDR_H__
+
+#include "lwip/ip_addr.h"
+
+namespace ClearCore {
+
+/**
+    \class IpAddress
+    \brief An IP Address class.
+**/
+class IpAddress {
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Construct a default IP Address.
+
+        \code{.cpp}
+        IpAddress ip = IpAddress();
+        \endcode
+    **/
+    IpAddress() : m_ipAddress(IPADDR4_INIT(0)) {}
+#endif
+
+    /**
+        \brief Construct an IP Address from four octet values.
+
+        \code{.cpp}
+        IpAddress ip = IpAddress(192, 168, 1, 8);
+        \endcode
+    **/
+    IpAddress(uint8_t firstOctet, uint8_t secondOctet,
+              uint8_t thirdOctet, uint8_t fourthOctet) :
+        m_ipAddress(IPADDR4_INIT_BYTES(firstOctet, secondOctet,
+                                       thirdOctet, fourthOctet)) {}
+
+    /**
+        \brief Construct an IP Address from an unsigned integer.
+
+        \code{.cpp}
+        IpAddress ip = IpAddress(3232235784);
+        \endcode
+    **/
+    IpAddress(uint32_t ipAddress) :  m_ipAddress(IPADDR4_INIT(ipAddress)) {}
+
+    /**
+        \brief Construct an IP Address from a character array.
+
+        \code{.cpp}
+        IpAddress ip = IpAddress("192.168.1.8");
+        \endcode
+    **/
+    explicit IpAddress(const char *ipAddress) {
+        ipaddr_aton(ipAddress, &m_ipAddress);
+    }
+
+    /**
+        \brief Returns a string representation of the IP Address.
+
+        \code{.cpp}
+        ConnectorCOM0.Send(ip.StringValue());
+        \endcode
+
+        \return Returns a string representation of the IP Address.
+    **/
+    char *StringValue() {
+        return ipaddr_ntoa(&m_ipAddress);
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+    // Overload cast operators
+    operator uint32_t() const {
+        return m_ipAddress.addr;
+    }
+#endif // !HIDE_FROM_DOXYGEN
+private:
+    ip_addr_t m_ipAddress;
+
+}; // IpAddress
+
+} // ClearCore namespace
+#endif // !__IPADDR_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/LedDriver.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/LedDriver.h
new file mode 100644
index 000000000..8270afaa8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/LedDriver.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file LedDriver.h
+    \brief Connector LED shift register access.
+
+    This class implements the Connector interface to conveniently drive the on-
+    board LED located next to the USB port.
+**/
+
+#ifndef __LEDDRIVER_H__
+#define __LEDDRIVER_H__
+
+#include <stdint.h>
+#include "Connector.h"
+#include "ShiftRegister.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore LED control class
+
+    This class manages access to the LED shift register so LEDs may be
+    controlled at the connector level.
+**/
+class LedDriver : public Connector {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager.
+
+        \note Should not be called by anything other than SysManager.
+    **/
+    LedDriver() {};
+
+    /**
+        \brief Get the connector's operational mode.
+        \note The only valid operational mode for this connector
+        type is #OUTPUT_DIGITAL.
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \param[in] newMode The new mode to be set.
+        The only valid mode for this connector type is: #OUTPUT_DIGITAL.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    bool Mode(ConnectorModes newMode) override {
+        return newMode == ConnectorModes::OUTPUT_DIGITAL;
+    }
+#endif
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() == Connector::SHIFT_REG_TYPE) {
+            // This generic connector variable is the LedDriver
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::SHIFT_REG_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (ConnectorAlias.IsWritable()) {
+            // This generic connector variable is writable
+        }
+        \endcode
+
+        \return True because this connector is always writable.
+    **/
+    bool IsWritable() override {
+        return true;
+    }
+
+    /**
+        \brief Get LED's last sampled state.
+
+        \code{.cpp}
+        if (ConnectorLed.State()) {
+            // The built-in LED is on
+        }
+        \endcode
+
+        \return The latest LED state.
+    **/
+    int16_t State() override;
+
+    /**
+        \brief Set the state of the LED.
+
+        \code{.cpp}
+        // Turn on the built-in LED
+        ConnectorLed.State(1);
+        \endcode
+
+        \param[in] newState New state to set for the LED.
+    **/
+    bool State(int16_t newState) override;
+
+#ifndef HIDE_FROM_DOXYGEN
+    bool IsInHwFault() override {
+        return false;
+    }
+#endif
+
+private:
+    ShiftRegister::Masks m_ledMask;
+    /**
+        \brief Update connector's state.
+
+        Poll the underlying connector for new state update.
+
+        This is typically called from a timer or main loop to update the
+        underlying value.
+    **/
+    void Refresh() override {}
+
+    /**
+        Initialize hardware and/or internal state.
+
+        \note This class requires no initialization, but requires an
+        implementation of Initialize() to be a concrete class.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override {
+        m_clearCorePin = clearCorePin;
+        m_mode = OUTPUT_DIGITAL;
+    }
+
+    /**
+        Construct and wire in LED bit number.
+    **/
+    explicit LedDriver(ShiftRegister::Masks ledMask);
+}; // LedDriver
+
+} // ClearCore namespace
+
+#endif // __LEDDRIVER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/MotorDriver.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/MotorDriver.h
new file mode 100644
index 000000000..aec68439e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/MotorDriver.h
@@ -0,0 +1,1667 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file MotorDriver.h
+    ClearCore stepper/servo motor Connector class
+**/
+#ifndef __MOTORDRIVER_H__
+#define __MOTORDRIVER_H__
+
+#include <stdint.h>
+#include "Connector.h"
+#include "DigitalIn.h"
+#include "PeripheralRoute.h"
+#include "ShiftRegister.h"
+#include "StatusManager.h"
+#include "StepGenerator.h"
+#include "SysUtils.h"
+#include "SysManager.h"
+
+#define HLFB_CARRIER_LOSS_ERROR_LIMIT (0)
+#define HLFB_CARRIER_LOSS_STATE_CHANGE_MS_45_HZ (25)
+#define HLFB_CARRIER_LOSS_STATE_CHANGE_MS_482_HZ (4)
+
+namespace ClearCore {
+
+/** The amount of HLFB captures to hold onto.
+    This should remain 2, as we only care about 1 capture back due to clipping
+    of the last PWM to assert move done/shutdown. **/
+#define CPM_HLFB_CAP_HISTORY 2
+
+/**
+    Delay before the motor is considered to be enabled after an enable request.
+**/
+#define CPM_ENABLE_DELAY 1250
+
+/** Default enable trigger pulse width, in milliseconds. **/
+#define DEFAULT_TRIGGER_PULSE_WIDTH_MS  25
+
+extern SysManager SysMgr;
+
+/**
+    \brief ClearCore motor connector class.
+
+    This class manages a motor connector on the ClearCore board.
+
+    The following connector instances support motor functionality:
+    - #ConnectorM0
+    - #ConnectorM1
+    - #ConnectorM2
+    - #ConnectorM3
+
+    For more detailed information on the ClearCore Motor Control and Motion
+    Generation systems, check out the \ref MotorDriverMain and \ref MoveGen
+    informational pages.
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class MotorDriver : public DigitalIn, public StepGenerator {
+    friend class MotorManager;
+    friend class StatusManager;
+    friend class SysManager;
+
+public:
+    /**
+        \union PolarityInversionsSD
+
+        \brief A small register with bit and field views. This allows easy
+        configuration for steppers that use an inverted signal on one of the
+        main input signals. See #PolarityInvertSDEnable(bool invert),
+        #PolarityInvertSDDirection(bool invert), and
+        #PolarityInvertSDHlfb(bool invert).
+    **/
+    union PolarityInversionsSD {
+        /**
+            Broad access to the whole register
+        **/
+        int16_t reg;
+
+        /**
+            Field access to the motor polarity inversions.
+        **/
+        struct {
+            /**
+                Invert the sense of the motor's enable input.
+            **/
+            uint32_t enableInverted : 1;
+            /**
+                Invert the sense of the motor's direction.
+            **/
+            uint32_t directionInverted : 1;
+            /**
+                Invert the sense of the motor's HLFB output.
+            **/
+            uint32_t hlfbInverted : 1;
+        } bit;
+
+        /**
+            PolarityInversionsSD default constructor
+        **/
+        PolarityInversionsSD() {
+            reg = 0;
+        }
+
+        /**
+            PolarityInversionsSD constructor with initial value
+        **/
+        PolarityInversionsSD(int16_t val) {
+            reg = val;
+        }
+    };
+
+    /**
+        Constant returned when HLFB duty cannot be determined.
+    **/
+    static const int16_t HLFB_DUTY_UNKNOWN = -9999;
+
+    /**
+        \brief Return state when HLFB state is requested.
+
+        \see HlfbMode for setting operational mode of HLFB to accommodate
+        PWM measurement modes versus static state modes.
+    **/
+    typedef enum {
+        /**
+            HLFB is de-asserted.
+        **/
+        HLFB_DEASSERTED,
+        /**
+            HLFB is asserted.
+        **/
+        HLFB_ASSERTED,
+        /**
+            For HLFB with PWM modes, this would signal that the #HlfbPercent
+            function has a new update.
+        **/
+        HLFB_HAS_MEASUREMENT,
+        /**
+            Unknown state
+        **/
+        HLFB_UNKNOWN
+    } HlfbStates;
+
+    /**
+        \brief Setup the HLFB query to match the ClearPath&trade; Motor's HLFB
+        signaling format.
+    **/
+    typedef enum {
+        /**
+            Use the current digital state of the HLFB input.
+
+            \note Applicable ClearPath HLFB modes:
+            - Servo On
+            - In Range
+            - All Systems Go (ASG)
+            - ASG - Latched
+        **/
+        HLFB_MODE_STATIC,
+        /**
+            The HLFB signal may have a 0-100% PWM component. If
+            #HLFB_HAS_MEASUREMENT occurred since the last query,
+            invoke the #HlfbPercent() function to get the last period measured.
+
+            \note If there is no more PWM signaling the #HlfbState() function
+            will return the digital state until another PWM is signaled.
+
+            \note Applicable ClearPath HLFB modes:
+            - Speed Output
+        **/
+        HLFB_MODE_HAS_PWM,
+        /**
+            The HLFB signal may have a -100% to +100% PWM component. If
+            #HLFB_HAS_MEASUREMENT occurred since the last query,
+            invoke the #HlfbPercent() function to get the last period measured.
+
+            \note If there is no more PWM signaling the #HlfbState() function
+            will return the digital state until another PWM is signaled.
+
+            \note Applicable ClearPath HLFB modes:
+            - Measured Torque
+            - ASG - w/Measured Torque
+            - ASG - Latched - w/Measured Torque
+        **/
+        HLFB_MODE_HAS_BIPOLAR_PWM
+    } HlfbModes;
+
+    /**
+        \brief High-Level Feedback (HLFB) carrier frequency: 45 Hz or 482 Hz
+    **/
+    typedef enum {
+        HLFB_CARRIER_45_HZ,
+        HLFB_CARRIER_482_HZ
+    } HlfbCarrierFrequency;
+
+    /**
+        \enum MotorReadyStates
+
+        \brief Motor readiness states.
+
+        \note This is a field in the StatusRegMotor.
+    **/
+    typedef enum {
+        /**
+            The motor is not enabled.
+        **/
+        MOTOR_DISABLED = 0,
+        /**
+            The motor is in the process of enabling.
+        **/
+        MOTOR_ENABLING,
+        /**
+            The motor is enabled and not moving, but HLFB is not asserted.
+        **/
+        MOTOR_FAULTED,
+        /**
+            The motor is enabled and HLFB is asserted.
+        **/
+        MOTOR_READY,
+        /**
+            The motor is enabled and moving.
+        **/
+        MOTOR_MOVING
+    } MotorReadyStates;
+
+    /**
+        \union StatusRegMotor
+
+        \brief Register access for information about the motor's operating
+        status. Intended for use in Step and Direction mode.
+    **/
+    union StatusRegMotor {
+        /**
+            Broad access to the whole register
+        **/
+        uint32_t reg;
+
+        /**
+            Field access to the motor status register
+        **/
+        struct {
+            /**
+                TRUE if the commanded position equals the target position and
+                the HLFB is asserted
+            **/
+            uint32_t AtTargetPosition : 1;
+            /**
+                TRUE if the commanded velocity is nonzero
+            **/
+            uint32_t StepsActive : 1;
+            /**
+                TRUE if the commanded velocity equals the target velocity
+            **/
+            uint32_t AtTargetVelocity : 1;
+            /**
+                Direction of the most recent move
+                TRUE if the last motion was in the positive direction
+                Latches until start of new move
+            **/
+            uint32_t MoveDirection : 1;
+            /**
+                TRUE if the HLFB is deasserted AND the enable output is asserted
+                When set, any currently executing motion will get canceled
+            **/
+            uint32_t MotorInFault : 1;
+            /**
+                TRUE if the motor's enable output is asserted AND the HLFB
+                is NOT deasserted.
+            **/
+            uint32_t Enabled : 1;
+            /**
+                TRUE if the last commanded move was a positional move.
+            **/
+            uint32_t PositionalMove : 1;
+            /**
+                Reflects the state of the HLFB.
+            **/
+            uint32_t HlfbState : 2;
+            /**
+                Alerts Present.
+            **/
+            uint32_t AlertsPresent : 1;
+            /**
+                Motor ready state
+            **/
+            MotorReadyStates ReadyState : 3;
+            /**
+                TRUE if enable trigger pulses are being sent
+            **/
+            uint32_t Triggering : 1;
+            /**
+                Reflects the state of the associated positive limit connector.
+            **/
+            uint32_t InPositiveLimit : 1;
+            /**
+                Reflects the state of the associated negative limit connector.
+            **/
+            uint32_t InNegativeLimit : 1;
+            /**
+                Reflects the state of the associated E-stop sensor connector.
+            **/
+            uint32_t InEStopSensor : 1;
+        } bit;
+
+        /**
+            StatusRegMotor default constructor
+        **/
+        StatusRegMotor() {
+            reg = 0;
+        }
+
+        /**
+            StatusRegMotor constructor with initial value
+        **/
+        StatusRegMotor(uint32_t val) {
+            reg = val;
+        }
+    };
+
+    /**
+        \union AlertRegMotor
+
+        \brief Accumulating register of alerts that have occurred on this motor.
+         Intended for use in Step and Direction mode.
+    **/
+    union AlertRegMotor {
+        /**
+            Broad access to the whole register
+        **/
+        uint32_t reg;
+
+        /**
+            Field access to the motor alert register
+        **/
+        struct {
+            /**
+                TRUE whenever a command is rejected due to an existing alert
+                register bit being asserted.
+            **/
+            uint16_t MotionCanceledInAlert : 1;
+            /**
+                TRUE whenever executing motion is canceled due to a positive
+                limit switch being asserted or whenever a command is rejected
+                while in the limit.
+            **/
+            uint16_t MotionCanceledPositiveLimit : 1;
+            /**
+                TRUE whenever executing motion is canceled due to a negative
+                limit switch being asserted or whenever a command is rejected
+                while in the limit.
+            **/
+            uint16_t MotionCanceledNegativeLimit : 1;
+            /**
+                TRUE whenever executing motion is canceled due to an E-Stop
+                triggered by the specified E-Stop sensor or whenever a command
+                is rejected while the E-Stop is asserted.
+            **/
+            uint16_t MotionCanceledSensorEStop : 1;
+            /**
+                TRUE whenever executing motion is canceled due to the enable
+                output deasserting or whenever a command is rejected while the
+                enable output is deasserted.
+            **/
+            uint16_t MotionCanceledMotorDisabled : 1;
+            /**
+                TRUE whenever the MotorInFault status is set in the motor status
+                register.
+            **/
+            uint16_t MotorFaulted : 1;
+        } bit;
+
+        /**
+            AlertRegMotor default constructor
+        **/
+        AlertRegMotor() {
+            reg = 0;
+        }
+
+        /**
+            AlertRegMotor constructor with initial value
+        **/
+        AlertRegMotor(uint32_t val) {
+            reg = val;
+        }
+    };
+
+    /**
+        Verify that the motor is in a good state before sending a move command.
+
+        \return True if the motor is ready for a move command; false if there
+        is a configuration setting or error that would (or should) prevent
+        motion.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool ValidateMove(bool negDirection);
+
+    /**
+        \copydoc StepGenerator::Move()
+    **/
+    virtual bool Move(int32_t dist,
+                      MoveTarget moveTarget = MOVE_TARGET_REL_END_POSN) override;
+
+    /**
+        \copydoc StepGenerator::MoveVelocity()
+    **/
+    virtual bool MoveVelocity(int32_t velocity) override;
+
+    /**
+        \brief Sets the filter length in samples. The default is 3 samples.
+
+        Restarts any in progress filtering.
+
+        \code{.cpp}
+        // Set M-0's HLFB filter to 5 samples (1ms)
+        ConnectorM0.HlfbFilterLength(5);
+        \endcode
+
+        \note One sample time is 200 microseconds.
+
+        \param[in] samples The length of the filter to set in samples
+    **/
+    void HlfbFilterLength(uint16_t samples) {
+        DigitalIn::FilterLength(samples);
+    }
+
+    /**
+        \brief Get connector type.
+
+        \code{.cpp}
+        if (ConnectorAlias.Type() == Connector::CPM_TYPE) {
+            // This generic connector variable is a MotorDriver connector
+        }
+        \endcode
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::CPM_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \code{.cpp}
+        if (ConnectorAlias.IsWritable()) {
+            // This generic connector variable is writable
+        }
+        \endcode
+
+        \return True because the connector is always writable
+    **/
+    bool IsWritable() override {
+        return true;
+    }
+
+    /**
+        \brief Accessor for the state of the motor's Input A
+
+        \code{.cpp}
+        if (ConnectorM0.MotorInAState()) {
+            // M-0's ClearPath motor has its input A raised
+        }
+        \endcode
+
+        \return The current state of Input A
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInAState();
+
+    /**
+        \brief Function to set the state of the motor's Input A
+
+        \code{.cpp}
+        // Turn off M-0's ClearPath motor's input A
+        ConnectorM0.MotorInAState(false);
+        \endcode
+
+        \param[in] value The boolean state to be passed to the input
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInAState(bool value);
+
+    /**
+        \brief Accessor for the state of the motor's Input B
+
+        \code{.cpp}
+        if (ConnectorM0.MotorInBState()) {
+            // M-0's ClearPath motor has its input B raised
+        }
+        \endcode
+
+        \return The current state of Input B
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInBState();
+
+    /**
+        \brief Function to set the value of the motor's Input B
+
+        \code{.cpp}
+        // Turn off M-0's ClearPath motor's input B
+        ConnectorM0.MotorInBState(false);
+        \endcode
+
+        \param[in] value The boolean state to be passed to the input
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInBState(bool value);
+
+    /**
+        \brief Accessor for the enable request state of the motor
+
+        \code{.cpp}
+        // Save the state of M-0's enable line
+        bool enableState = ConnectorM0.EnableRequest();
+        \endcode
+
+        \return The current state of the motor's Enable input
+    **/
+    bool EnableRequest() {
+        return m_enableRequestedState;
+    }
+
+    /**
+        \brief Function to request the motor to enable or disable
+
+        \code{.cpp}
+        // Send an enable request to M-0's ClearPath motor
+        ConnectorM0.EnableRequest(true);
+        \endcode
+
+        \note Any active step and direction moves on this MotorDriver
+        connector will be terminated if \a value is false.
+        \param[in] value The boolean state to be passed to the motor's Enable
+        input
+    **/
+    void EnableRequest(bool value);
+
+    /**
+        \brief Function to set the duty cycle of a PWM signal being sent to the
+        motor's Input A
+
+        \code{.cpp}
+        // Send a max duty cycle on M-0's input A line
+        ConnectorM0.MotorInADuty(255);
+        \endcode
+
+        \param[in] duty The PWM duty cycle
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInADuty(uint8_t duty);
+
+    /**
+        \brief Function to set the duty cycle of a PWM signal being sent to the
+        motor's Input B
+
+        \code{.cpp}
+        // Send a max duty cycle on M-0's input B line
+        ConnectorM0.MotorInBDuty(255);
+        \endcode
+
+        \param[in] duty The PWM duty cycle
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInBDuty(uint8_t duty);
+
+    /**
+        \brief Sends trigger pulse(s) to a connected ClearPath&trade; motor by
+        de-asserting the enable signal for \a time_ms milliseconds.
+
+        The pulse duration (\a time_ms) must be within the Trigger Pulse range
+        set in the MSP software. The default trigger pulse will not suffice if
+        not changed within MSP. If the pulse duration is too short, the pulse
+        will be ignored. If the pulse duration is too long, the motor will
+        momentarily disable.
+
+        This function can be used with the following ClearPath&trade; operating
+        modes:
+        - Move Incremental Distance
+        - Pulse Burst Positioning
+        - Multiple Sensor Positioning
+
+        \code{.cpp}
+        // Send a single trigger pulse of 25ms on M-0's enable that blocks
+        // further code execution until the pulse is finished.
+        ConnectorM0.EnableTriggerPulse(1, 25, true);
+        \endcode
+
+        \note The time specified by \a time_ms is checked at the SysTick rate.
+        \note If the motor EnableRequest is false when this function is called,
+        the function will return without doing anything.
+        \note \a time_ms specifies both the asserted and de-asserted pulse
+        widths.
+        The total time for sending the pulses is 2 * \a pulseCount * \a time_ms.
+
+        \param[in] pulseCount (optional) The number of times to pulse the enable
+        signal. Default: 1.
+        \param[in] time_ms (optional) The amount of time to pull the enable
+        signal low, in milliseconds. Default: #DEFAULT_TRIGGER_PULSE_WIDTH_MS.
+        \param[in] blockUntilDone (optional) If true, block further code
+        execution until the pulses have finished being sent. Default: false.
+    **/
+    void EnableTriggerPulse(uint16_t pulseCount = 1,
+                            uint32_t time_ms = DEFAULT_TRIGGER_PULSE_WIDTH_MS,
+                            bool blockUntilDone = false);
+
+    /**
+        \brief Check to see if enable trigger pulses are actively being sent.
+
+        When using the non-blocking option of EnableTriggerPulse, this function
+        allows you to check if the trigger pulse sequence is still being sent.
+
+        \code{.cpp}
+        // Begin a train of five pulses on M-0's enable that do not block
+        // further code execution until the pulse train is finished.
+        ConnectorM0.EnableTriggerPulse(5);
+        // Perform other processing here that does not have to wait for the
+        // trigger pulses to be sent...
+
+        while (ConnectorM0.EnableTriggerPulseActive()) {
+            continue;   // Wait for the trigger pulses to be sent
+        }
+        // Trigger pulses have all been sent.
+        // Now it is safe to change inputs, etc.
+        \endcode
+    **/
+    volatile const bool &EnableTriggerPulseActive() {
+        return m_enableTriggerActive;
+    }
+
+    /**
+        \brief Return the latest HLFB state information.
+
+        \code{.cpp}
+        if (ConnectorM0.HlfbState() == MotorDriver::HLFB_ASSERTED) {
+            // M-0's HLFB is fully asserted
+        }
+        \endcode
+
+        \return When configured in #HLFB_MODE_STATIC mode, this returns the
+        current HLFB state.
+
+        \return For #HLFB_MODE_HAS_PWM, the #HLFB_ASSERTED or #HLFB_DEASSERTED
+        state is returned if no PWM has been detected for 2 milliseconds.
+    **/
+    volatile const HlfbStates &HlfbState() {
+        return m_hlfbState;
+    }
+
+    /**
+        \brief Returns the percent of Peak Torque/Max Speed based on the current
+        HLFB PWM duty cycle
+
+        \code{.cpp}
+        // Save the current duty cycle of M-0's HLFB
+        float currentDuty = ConnectorM0.HlfbPercent();
+        \endcode
+
+        \note This function is only applicable when the #HlfbMode is set to
+        #HLFB_MODE_HAS_PWM or #HLFB_MODE_HAS_BIPOLAR_PWM.
+
+        \return Returns #HLFB_DUTY_UNKNOWN number if no update has been
+        detected.
+
+        \note The correct HLFB carrier frequency must be set using
+        #HlfbCarrier().
+    **/
+    volatile const float &HlfbPercent() {
+        return m_hlfbDuty;
+    }
+
+    /**
+        \brief Sets operational mode of the HLFB to match up with the HLFB
+        configuration of a ClearPath&trade; motor.
+
+        \code{.cpp}
+        // Set M-0's HLFB mode to bipolar PWM
+        ConnectorM0.HlfbMode(MotorDriver::HLFB_MODE_HAS_BIPOLAR_PWM);
+        \endcode
+
+        \param[in] newMode HLFB mode to switch to
+    **/
+    void HlfbMode(HlfbModes newMode) {
+        if (m_hlfbMode == newMode) {
+            return;
+        }
+        m_hlfbMode = newMode;
+        m_hlfbCarrierLost = true;
+        m_hlfbDuty = HLFB_DUTY_UNKNOWN;
+    }
+
+    /**
+        \brief Accessor for current HLFB operational mode
+
+        \code{.cpp}
+        if (ConnectorM0.HlfbMode() == MotorDriver::HLFB_MODE_STATIC) {
+            // M-0's HLFB mode is set to static
+        }
+        \endcode
+
+        \return Current HLFB mode
+    **/
+    HlfbModes HlfbMode() {
+        return m_hlfbMode;
+    }
+
+    /**
+        \brief Clear on read accessor for HLFB rising edge detection.
+
+        \code{.cpp}
+        if (ConnectorM0.HlfbHasRisen()) {
+            // M-0 HLFB rising edge detected
+        }
+        \endcode
+
+        \return True if the HLFB input state has risen since last poll
+    **/
+    bool HlfbHasRisen() {
+        return DigitalIn::InputRisen();
+    }
+
+    /**
+        \brief Clear on read accessor for HLFB falling edge detection.
+
+        \code{.cpp}
+        if (ConnectorM0.HlfbHasFallen()) {
+            // M-0 HLFB falling edge detected
+        }
+        \endcode
+
+        \return True if the HLFB input state has fallen since last poll
+    **/
+    bool HlfbHasFallen() {
+        return DigitalIn::InputFallen();
+    }
+
+    /**
+        \brief Set the HLFB carrier frequency signal.
+
+        \code{.cpp}
+        // Set motor M-0 to use the higher HFLB carrier frequency (482 Hz)
+        ConnectorM0.HlfbCarrier(MotorDriver::HLFB_CARRIER_482_HZ);
+        \endcode
+
+        \return True if the HLFB carrier frequency was correctly set
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool HlfbCarrier(HlfbCarrierFrequency freq) {
+        switch (freq) {
+            case HLFB_CARRIER_45_HZ:
+                m_hlfbCarrierLossStateChange_ms =
+                    HLFB_CARRIER_LOSS_STATE_CHANGE_MS_45_HZ;
+                break;
+            case HLFB_CARRIER_482_HZ:
+                m_hlfbCarrierLossStateChange_ms =
+                    HLFB_CARRIER_LOSS_STATE_CHANGE_MS_482_HZ;
+                break;
+            default:
+                return false;
+        }
+        m_hlfbCarrierFrequency = freq;
+        return true;
+    }
+
+    /**
+        \brief This motor's HLFB carrier frequency.
+
+        \code{.cpp}
+        // Do work that depends on the current HLFB carrier frequency
+        switch (ConnectorM0.HlfbCarrier()) {
+            case MotorDriver::HLFB_CARRIER_45_HZ:
+                // Slow HLFB carrier. Do something.
+                break;
+            case MotorDriver::HLFB_CARRIER_482_HZ:
+            default:
+                // Fast HLFB carrier. Do something else.
+                break;
+        }
+        \endcode
+
+        \return The HLFB carrier frequency.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    HlfbCarrierFrequency HlfbCarrier() {
+        return m_hlfbCarrierFrequency;
+    }
+
+    /**
+        \brief Check whether the connector is in a hardware fault state.
+
+        \code{.cpp}
+        if (ConnectorM0.IsInHwFault()) {
+            // M-0 is in a fault state
+        }
+        \endcode
+
+        \return Connector is in fault
+    **/
+    bool IsInHwFault() override {
+        return (volatile bool &)m_inFault;
+    }
+    /**
+        \brief Accessor for the current Motor Status Register
+
+        \code{.cpp}
+        if (ConnectorM0.StatusReg().bit.StepsActive) {
+            // M-0 is currently in motion
+        }
+        \endcode
+    **/
+    volatile const StatusRegMotor &StatusReg() {
+        return m_statusRegMotor;
+    }
+
+    /**
+        \brief Clear on read accessor for Motor Status Register rising edge
+        detection.
+
+        \code{.cpp}
+        if (ConnectorM0.StatusRegRisen().bit.Enabled) {
+            // M-0's requested enable state went from "off" to "on" since
+            // the last status poll.
+        }
+        \endcode
+    **/
+    StatusRegMotor StatusRegRisen();
+
+    /**
+        \brief Clear on read accessor for Motor Status Register falling edge
+        detection.
+
+        \code{.cpp}
+        if (ConnectorM0.StatusRegFallen().bit.Enabled) {
+            // M-0's requested enable state went from "on" to "off" since
+            // the last status poll.
+        }
+        \endcode
+    **/
+    StatusRegMotor StatusRegFallen();
+
+    /**
+        \brief Accessor for the current Motor Alert Register
+
+        \code{.cpp}
+        if (ConnectorM0.AlertReg().bit.MotionCanceledMotorDisabled) {
+            // Motion on M-0 was canceled because the motor was disabled
+        }
+        \endcode
+    **/
+    volatile const AlertRegMotor &AlertReg() {
+        return m_alertRegMotor;
+    }
+
+    /**
+        \brief Clear the Motor Alert Register. Motion will be prevented if any
+        Alert Register bits are set.
+
+        \code{.cpp}
+        // Clear any alerts that have accumulated for M-0.
+        ConnectorM0.ClearAlerts();
+        \endcode
+    **/
+    void ClearAlerts(uint32_t mask = UINT32_MAX) {
+        atomic_and_fetch(&m_alertRegMotor.reg, ~mask);
+    }
+
+    /**
+        \brief Function to invert the default polarity of the enable signal of
+        this motor.
+
+        \code{.cpp}
+        if (ConnectorM0.PolarityInvertSDEnable(true)) {
+            // M-0's enable signal was successfully inverted
+        }
+        \endcode
+
+        \note This inversion function is only usable in Step & Direction mode.
+
+        \param[in] invert If true, signal inversion will be turned on
+    **/
+    bool PolarityInvertSDEnable(bool invert);
+    /**
+        \brief Function to invert the default polarity of the direction signal
+        of this motor.
+
+        \code{.cpp}
+        if (ConnectorM0.PolarityInvertSDDirection(true)) {
+            // M-0's direction signal was successfully inverted
+        }
+        \endcode
+
+        \note This inversion function is only usable in Step & Direction mode.
+
+        \param[in] invert If true, signal inversion will be turned on
+    **/
+    bool PolarityInvertSDDirection(bool invert);
+    /**
+        \brief Function to invert the default polarity of the HLFB signal of
+        this motor.
+
+        \code{.cpp}
+        if (ConnectorM0.PolarityInvertSDHlfb(true)) {
+            // M-0's HLFB signal was successfully inverted
+        }
+        \endcode
+
+        \note This inversion function is only usable in Step & Direction mode.
+
+        \param[in] invert If true, signal inversion will be turned on
+    **/
+    bool PolarityInvertSDHlfb(bool invert);
+
+    /**
+        \brief Set the associated brake output connector.
+
+        Brake output mode uses HLFB readings from a connected ClearPath motor
+        to energize or de-energize a connected brake. HLFB must be configured
+        for either "ASG with Measured Torque" or "Servo On" for the automatic
+        brake to function correctly. The motor connectors M-0 through M-3
+        can be mapped to any of the ClearCore outputs IO-0 through IO-5, or to
+        any attached CCIO-8 output pin.
+
+        \code{.cpp}
+        if (ConnectorM0.BrakeOutput(CLEARCORE_PIN_IO2)) {
+            // M-0's brake output is now set to IO-2 and enabled.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (ConnectorM0.BrakeOutput(CLEARCORE_PIN_INVALID)) {
+            // M-0's brake output is now disabled.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the connector to use as the brake
+        output for this motor. If CLEARCORE_PIN_INVALID is supplied, brake
+        output is disabled.
+
+        \return True if the brake output was successfully set and enabled, or
+        successfully disabled; false if a pin other than CLEARCORE_PIN_INVALID
+        was supplied that isn't a valid digital output pin.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool BrakeOutput(ClearCorePins pin);
+
+    /**
+        \brief Get the associated brake output connector.
+
+        Brake output mode uses HLFB readings from a connected ClearPath motor
+        to energize or de-energize a connected brake. HLFB must be configured
+        for either "ASG with Measured Torque" or "Servo On" for the automatic
+        brake to function correctly. The motor connectors M-0 through M-3
+        can be mapped to any of the ClearCore outputs IO-0 through IO-5, or to
+        any attached CCIO-8 output pin.
+
+        \code{.cpp}
+        if (ConnectorM0.BrakeOutput() == CLEARCORE_PIN_IO2) {
+            // M-0's brake output is currently set to IO-2 and enabled.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (ConnectorM0.BrakeOutput() == CLEARCORE_PIN_INVALID) {
+            // M-0's brake output is currently disabled.
+        }
+        \endcode
+
+        \return The pin representing the digital output connector configured to
+        be this motor's brake output, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins BrakeOutput() {
+        return m_brakeOutputPin;
+    }
+
+    /**
+        \brief Set the associated positive limit switch connector.
+
+        When the input is deasserted (LED off) on the connector associated with
+        this limit, all motion in the positive direction will be stopped (i.e.
+        use a Normally Closed (NC) switch on this connector).
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchPos(CLEARCORE_PIN_IO2)) {
+            // M-0's positive limit switch is now set to IO-2 and enabled.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchPos(CLEARCORE_PIN_INVALID)) {
+            // M-0's positive limit switch is now disabled.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the connector to use as the
+        positive limit switch for this motor. If CLEARCORE_PIN_INVALID
+        is supplied, the positive limit is disabled.
+
+        \return True if the positive limit switch was successfully set and
+        enabled, or  successfully disabled; false if a pin other than
+        CLEARCORE_PIN_INVALID was supplied that isn't a valid digital
+        input pin.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool LimitSwitchPos(ClearCorePins pin);
+
+    /**
+        \brief Get the associated positive limit switch output connector.
+
+        When the input is deasserted (LED off) on the connector associated with
+        this limit, all motion in the positive direction will be stopped (i.e.
+        use a Normally Closed (NC) switch on this connector).
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchPos() == CLEARCORE_PIN_IO2) {
+            // M-0's positive limit switch is currently set to IO-2 and enabled.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchPos() == CLEARCORE_PIN_INVALID) {
+            // M-0's positive limit switch is currently disabled.
+        }
+        \endcode
+
+        \return The pin representing the digital output connector configured to
+        be this motor's positive limit, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins LimitSwitchPos() {
+        return m_limitSwitchPos;
+    }
+
+    /**
+        \brief Set the associated negative limit switch connector.
+
+        When the input is deasserted (LED off) on the connector associated with
+        this limit, all motion in the negative direction will be stopped (i.e.
+        use a Normally Closed (NC) switch on this connector).
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchNeg(CLEARCORE_PIN_IO2)) {
+            // M-0's negative limit switch is now set to IO-2 and enabled.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchNeg(CLEARCORE_PIN_INVALID)) {
+            // M-0's negative limit switch is now disabled.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the connector to use as the
+        negative limit switch for this motor. If CLEARCORE_PIN_INVALID
+        is supplied, the negative limit is disabled.
+
+        \return True if the negative limit switch was successfully set and
+        enabled, or  successfully disabled; false if a pin other than
+        CLEARCORE_PIN_INVALID was supplied that isn't a valid digital
+        input pin.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool LimitSwitchNeg(ClearCorePins pin);
+
+    /**
+        \brief Get the associated negative limit switch output connector.
+
+        When the input is deasserted (LED off) on the connector associated with
+        this limit, all motion in the negative direction will be stopped (i.e.
+        use a Normally Closed (NC) switch on this connector).
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchNeg() == CLEARCORE_PIN_IO2) {
+            // M-0's negative limit switch is currently set to IO-2 and enabled.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (ConnectorM0.LimitSwitchNeg() == CLEARCORE_PIN_INVALID) {
+            // M-0's negative limit switch is currently disabled.
+        }
+        \endcode
+
+        \return The pin representing the digital output connector configured to
+        be this motor's negative limit, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins LimitSwitchNeg() {
+        return m_limitSwitchNeg;
+    }
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorM0.Mode() == Connector::CPM_MODE_A_DIRECT_B_PWM) {
+            // M-0 is in A-Direct, B-PWM mode
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        Set the digital input connector used to control the state of the enable
+        signal.
+
+        \code{.cpp}
+        if (ConnectorM0.EnableConnector(CLEARCORE_PIN_DI6)) {
+            // Connector DI-6 was successfully configured to control the enable
+            // signal for motor M-0.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the digital input connector that
+        will control the state of this motor's enable signal.
+
+        \return True if the enable connector was configured successfully.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool EnableConnector(ClearCorePins pin);
+
+    /**
+        Get the digital input connector used to control the state of the enable
+        signal.
+
+        \code{.cpp}
+        if (ConnectorM0.EnableConnector() == CLEARCORE_PIN_DI8) {
+            // Connector DI-8 is currently configured to control the enable
+            // signal for motor M-0.
+        }
+        \endcode
+
+        \return The pin representing the digital input connector configured to
+        control this motor's enable signal, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins EnableConnector() {
+        return m_enableConnector;
+    }
+
+    /**
+        Set the digital input connector used to control the state of the Input A
+        signal.
+
+        \code{.cpp}
+        if (ConnectorM0.InputAConnector(CLEARCORE_PIN_DI6)) {
+            // Connector DI-6 was successfully configured to control the Input A
+            // signal for motor M-0.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the digital input connector that
+        will control the state of this motor's Input A signal.
+
+        \return True if the Input A connector was configured successfully.
+
+        \note For use with ClearPath-MC.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool InputAConnector(ClearCorePins pin);
+
+    /**
+        Get the digital input connector used to control the state of the Input A
+        signal.
+
+        \code{.cpp}
+        if (ConnectorM0.InputAConnector() == CLEARCORE_PIN_DI8) {
+            // Connector DI-8 is currently configured to control the Input A
+            // signal for motor M-0.
+        }
+        \endcode
+
+        \return The pin representing the digital input connector configured to
+        control this motor's Input A signal, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note For use with ClearPath-MC.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins InputAConnector() {
+        return m_inputAConnector;
+    }
+
+    /**
+        Set the digital input connector used to control the state of the Input B
+        signal.
+
+        \code{.cpp}
+        if (ConnectorM0.InputBConnector(CLEARCORE_PIN_DI6)) {
+            // Connector DI-6 was successfully configured to control the Input B
+            // signal for motor M-0.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the digital input connector that
+        will control the state of this motor's Input B signal.
+
+        \return True if the Input B connector was configured successfully.
+
+        \note For use with ClearPath-MC.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool InputBConnector(ClearCorePins pin);
+
+    /**
+        Get the digital input connector used to control the state of the Input B
+        signal.
+
+        \code{.cpp}
+        if (ConnectorM0.InputBConnector() == CLEARCORE_PIN_DI8) {
+            // Connector DI-8 is currently configured to control the Input B
+            // signal for motor M-0.
+        }
+        \endcode
+
+        \return The pin representing the digital input connector configured to
+        control this motor's Input B signal, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note For use with ClearPath-MC.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins InputBConnector() {
+        return m_inputBConnector;
+    }
+
+    /**
+        Set the digital input connector used as an E-Stop signal.
+
+        \code {.cppp}
+        if (ConnectorM0.EStopConnector(CLEARCORE_PIN_DI6)) {
+            // Connector DI-6 was successfully configured to act as an E-Stop
+            // input signal for motor M-0.
+        }
+        \endcode
+
+        \param[in] pin The pin representing the digital input connector that
+        will act as an E-Stop signal for this motor.
+
+        \return True if the E-Stop connector was configured successfully.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    bool EStopConnector(ClearCorePins pin);
+
+    /**
+        Get the digital input connector used to control the E-Stop input for
+        this motor.
+
+        \code{.cpp}
+        if (ConnectorM0.EStopConnector() == CLEARCORE_PIN_DI6) {
+            // Connector DI-6 is currently configured as an E-Stop input for
+            // motor M-0.
+        }
+        \endcode
+
+        \return The Pin representing the digital input connector configured as
+        an E-Stop input for this motor, or CLEARCORE_PIN_INVALID if no such
+        connector has been configured.
+
+        \note For use with Step and Direction mode.
+
+        \note Available with software version 1.1 or greater. See
+        \ref InstallationInstructions for information on updating library
+        versions.
+    **/
+    ClearCorePins EStopConnector() {
+        return m_eStopConnector;
+    }
+
+    /**
+        Get the HLFB input status.
+
+        \return True if the HLFB state is currently asserted or is actively
+        detecting a PWM signal.
+    **/
+    bool HlfbInputStatus() {
+        return m_hlfbState == HLFB_ASSERTED ||
+               m_hlfbState == HLFB_HAS_MEASUREMENT;
+    }
+
+    /**
+        Set the active level for the Enable signal. The default is active low.
+
+        \param[in] activeLevel True for active high; false for active low.
+    **/
+    void EnableActiveLevel(bool activeLevel) {
+        m_polarityInversions.bit.enableInverted = activeLevel;
+    }
+
+    /**
+        Get the active level for the Enable signal. The default is active low.
+
+        \return True if the enable signal is configured to be active high;
+        false if configured to be active low.
+    **/
+    bool EnableActiveLevel() {
+        return m_polarityInversions.bit.enableInverted;
+    }
+
+    /**
+        Set the active level for the HLFB signal. The default is active high.
+
+        \param[in] activeLevel True for active high; false for active low.
+    **/
+    void HlfbActiveLevel(bool activeLevel) {
+        m_polarityInversions.bit.hlfbInverted = !activeLevel;
+    }
+
+    /**
+        Get the active level for the HLFB signal. The default is active high.
+
+        \return True if the HLFB signal is configured to be active high;
+        false if configured to be active low.
+    **/
+    bool HlfbActiveLevel() {
+        return !m_polarityInversions.bit.hlfbInverted;
+    }
+
+#ifndef HIDE_FROM_DOXYGEN
+
+    virtual void OutputDirection() override {
+        if (m_mode == Connector::CPM_MODE_STEP_AND_DIR &&
+                m_polarityInversions.bit.directionInverted) {
+            DATA_OUTPUT_STATE(m_aInfo->gpioPort, m_aDataMask, Direction());
+        }
+        else {
+            DATA_OUTPUT_STATE(m_aInfo->gpioPort, m_aDataMask, !Direction());
+        }
+    }
+
+    void ClearFaults(uint32_t disableTime_ms, uint32_t waitForHlfbTime_ms = 0) {
+        EnableTriggerPulse(1, disableTime_ms);
+        m_clearFaultHlfbTimer = waitForHlfbTime_ms;
+        m_clearFaultState = CLEAR_FAULT_PULSE_ENABLE;
+    }
+
+    bool ClearFaultsActive() {
+        return m_clearFaultState != CLEAR_FAULT_IDLE;
+    }
+
+    /**
+        A helper function to determine whether the pin supplied is a valid
+        digital input connector.
+
+        \param[in] pin The pin to validate as a digital input.
+
+        \return True if the pin is a digital input connector; false otherwise.
+    **/
+    static bool IsValidInputPin(ClearCorePins pin);
+
+    /**
+        A helper function to determine whether the pin supplied is a valid
+        digital output connector.
+
+        \param[in] pin The pin to validate as a digital output.
+
+        \return True if the pin is a digital output connector; false otherwise.
+    **/
+    static bool IsValidOutputPin(ClearCorePins pin);
+
+    /**
+        \brief Function to set the on time of a PWM signal being sent to the
+        motor's Input A
+
+        \param[in] count The PWM on time
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInACount(uint16_t count);
+
+    /**
+        \brief Function to set the on time of a PWM signal being sent to the
+        motor's Input B
+
+        \param[in] count The PWM on time
+
+        \note For use with ClearPath-MC.
+    **/
+    bool MotorInBCount(uint16_t count);
+
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager.
+    **/
+    MotorDriver() {};
+#endif
+protected:
+    // Enable bit associated with this CPM
+    ShiftRegister::Masks m_enableMask;
+
+    // Mapping to all the pin information
+    const PeripheralRoute *m_aInfo;
+    const PeripheralRoute *m_bInfo;
+    const PeripheralRoute *m_hlfbInfo;
+
+    // Keep some commonly-used bits from the Info structures
+    uint32_t m_aDataMask;
+    volatile uint32_t *m_aTccBuffer;
+    uint32_t m_bDataMask;
+    volatile uint32_t *m_bTccBuffer;
+    uint32_t m_aTccSyncMask;
+    volatile uint32_t *m_aTccSyncReg;
+    uint32_t m_bTccSyncMask;
+    volatile uint32_t *m_bTccSyncReg;
+
+    // Enable, InA, InB connector pairing
+    ClearCorePins m_enableConnector;
+    ClearCorePins m_inputAConnector;
+    ClearCorePins m_inputBConnector;
+
+    // - - - - - - - - - - - - - - - - - - - - - - - - - - -
+    // HLFB State
+    // - - - - - - - - - - - - - - - - - - - - - - - - - - -
+    // Timer/Counter index associated with HLFB input
+    uint8_t m_hlfbTcNum;
+    // Assigned channel in EVSYS
+    uint8_t m_hlfbEvt;
+    // HLFB measurement mode
+    HlfbModes m_hlfbMode;
+    // HLFB width, period raw measurements
+    uint16_t m_hlfbWidth[CPM_HLFB_CAP_HISTORY];
+    uint16_t m_hlfbPeriod[CPM_HLFB_CAP_HISTORY];
+    // HLFB measurement count, used to show lack of PWM
+    uint16_t m_hlfbNoPwmSampleCount;
+    HlfbCarrierFrequency m_hlfbCarrierFrequency;
+    uint32_t m_hlfbCarrierLossStateChange_ms;
+    // The last board time (in milliseconds) when PWM carrier was detected
+    uint32_t m_hlfbLastCarrierDetectTime;
+    // HLFB last duty cycle
+    float m_hlfbDuty;
+    // HLFB state return
+    HlfbStates m_hlfbState;
+    bool m_lastHlfbInputValue;
+    bool m_hlfbPwmReadingPending;
+    uint16_t m_hlfbStateChangeCounter;
+
+    // Inversion mask of actual enable, direction, and HLFB state
+    PolarityInversionsSD m_polarityInversions;
+
+    bool m_enableRequestedState;
+    bool m_enableTriggerActive;
+    uint32_t m_enableTriggerPulseStartMs;
+    uint32_t m_enableTriggerPulseCount;
+    uint32_t m_enableTriggerPulseLenMs;
+
+    uint16_t m_aDutyCnt;
+    uint16_t m_bDutyCnt;
+
+    bool m_inFault;
+
+    StatusRegMotor m_statusRegMotor;
+    StatusRegMotor m_statusRegMotorRisen;
+    StatusRegMotor m_statusRegMotorFallen;
+    StatusRegMotor m_statusRegMotorLast;
+
+    AlertRegMotor m_alertRegMotor;
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+
+    /**
+        Function to toggle the enable state of the motor.
+
+        Used internally to generate trigger pulses on the enable line.
+    **/
+    void ToggleEnable();
+
+private:
+
+    enum ClearFaultState {
+        CLEAR_FAULT_IDLE,
+        CLEAR_FAULT_PULSE_ENABLE,
+        CLEAR_FAULT_WAIT_FOR_HLFB
+    };
+
+    bool m_initialized;
+
+    // Internal fields used for the IsReady field of the motor status reg
+    bool m_isEnabling;
+    bool m_isEnabled;
+    bool m_hlfbCarrierLost;
+    int32_t m_enableCounter;
+
+    // Brake Output Feature
+    ClearCorePins m_brakeOutputPin;
+
+    // Limit Switch Feature
+    ClearCorePins m_limitSwitchNeg;
+    ClearCorePins m_limitSwitchPos;
+
+    // Hardware E-Stop Sensor Feature
+    ClearCorePins m_eStopConnector;
+    bool m_motionCancellingEStop;
+
+    bool m_shiftRegEnableReq;
+    ClearFaultState m_clearFaultState;
+    uint32_t m_clearFaultHlfbTimer;
+
+    /**
+        Construct, wire in pads and LED Shift register object
+    **/
+    MotorDriver(enum ShiftRegister::Masks enableMask,
+                const PeripheralRoute *aInfo,
+                const PeripheralRoute *bInfo,
+                const PeripheralRoute *hlfbInfo,
+                uint16_t hlfbTc,
+                uint16_t hlfbEvt);
+
+    void UpdateADuty();
+    void UpdateBDuty();
+
+    /**
+          Refresh the Motor on the SysTick time.
+    **/
+    void RefreshSlow();
+
+    // Poll electrical connector state and update the internal state.
+    void Refresh() override;
+
+    /**
+        \brief Sets/Clears the fault flag and halts/restores the motor.
+
+        During fault, the HBridge will be disabled, any output will be halted.
+        Any attempt to change state will be applied after fault clears.
+        Clearing the fault flag will restore the connector to pre-fault state.
+
+        \param[in] isFaulted The desired value for the fault flag.
+    **/
+    void FaultState(bool isFaulted);
+
+    /**
+        \brief Set the motor's operational mode.
+
+        \param[in] newMode The new operational mode to be set.
+        The valid modes for this connector type are:
+        - Connector#CPM_MODE_STEP_AND_DIR
+        - Connector#CPM_MODE_A_DIRECT_B_DIRECT
+        - Connector#CPM_MODE_A_DIRECT_B_PWM
+        - Connector#CPM_MODE_A_PWM_B_PWM.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    bool Mode(Connector::ConnectorModes newMode) override;
+
+    /**
+        A helper function to wire in one of the connectors to control a motor
+        digital input or reflect the state of a motor digital output.
+
+        \param[in] pin The pin value requested to be assigned to the
+        \a memberPin member variable.
+        \param[in] memberPin A reference to the member variable that is to be
+        set to the value of \a pin.
+        \param[in] input True if the \a memberPin requires a digital input pin
+        (default) or false if it requires a digital output pin. Used to validate
+        the \a pin value supplied.
+
+        \return True if the pin supplied is valid and successfully configured;
+        false if the pin supplied was invalid.
+    **/
+    bool SetConnector(ClearCorePins pin, ClearCorePins &memberPin,
+                      bool input = true);
+
+    /**
+        A helper function to check if the E-Stop sensor is valid and/or
+        currently active (low).
+    **/
+    bool CheckEStopSensor();
+
+}; // MotorDriver
+
+} // ClearCore namespace
+
+#endif // __MOTORDRIVER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/MotorManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/MotorManager.h
new file mode 100644
index 000000000..e02bfa3ac
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/MotorManager.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file MotorManager.h
+    ClearCore motor-connector manager class
+**/
+#ifndef __MOTORMANAGER_H__
+#define __MOTORMANAGER_H__
+
+#include <stdint.h>
+#include "HardwareMapping.h"
+#include "MotorDriver.h"
+
+namespace ClearCore {
+
+/**
+    \class MotorManager
+    \brief ClearCore motor-connector manager.
+
+    This class manages shared settings for the MotorDriver connectors.
+
+    For more detailed information on the ClearCore Motor Control and Motion
+    Generation systems, check out the \ref MotorDriverMain and \ref MoveGen
+    informational pages.
+**/
+class MotorManager {
+public:
+    /**
+        Output step rates to be sent to motors.
+    **/
+    typedef enum {
+        /**
+            Select the slow speed step input rate (100 kHz, 5uS pulse width)
+        **/
+        CLOCK_RATE_LOW,
+        /**
+            Select the medium speed step input rate (500 kHz, 1uS pulse width)
+        **/
+        CLOCK_RATE_NORMAL,
+        /**
+            Select the fast speed step input rate (2 MHz, 250nS pulse width)
+        **/
+        CLOCK_RATE_HIGH
+    } MotorClockRates;
+
+    /**
+        Indicates a pair of MotorDriver Connectors.
+    **/
+    typedef enum {
+        /**
+            MotorDriver Connectors M-0 and M-1.
+        **/
+        MOTOR_M0M1 = 0,
+        /**
+            MotorDriver Connectors M-2 and M-3.
+        **/
+        MOTOR_M2M3 = 1,
+        /**
+            The total number of pairs of MotorDriver Connectors.
+        **/
+        NUM_MOTOR_PAIRS = 2,
+        /**
+            All MotorDriver Connectors.
+        **/
+        MOTOR_ALL = NUM_MOTOR_PAIRS,
+    } MotorPair;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for singleton instance.
+    **/
+    static MotorManager &Instance();
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize();
+#endif
+
+    /**
+        \brief Sets the output step rate for the motor step generators.
+
+        Sets the step rate for the MotorDriver connectors as a group.
+        They cannot be individually set.
+
+        \note Setting a HIGH clock rate when using a ClearPath motor may cause
+        errors. NORMAL clock rate is recommended for ClearPath motors.
+
+        \code{.cpp}
+        // Set all MotorDrivers' input clock rate to the high rate
+        MotorMgr.MotorInputClocking(MotorManager::CLOCK_RATE_HIGH);
+        \endcode
+
+        \param[in] newRate Step rate to be set
+
+        \return Success
+    **/
+    bool MotorInputClocking(MotorClockRates newRate);
+
+    /**
+        \brief Sets the operational mode for the specified MotorDriver
+        connectors.
+
+        Sets the mode for the specified MotorDriver connectors in tandem.
+        They cannot be individually set.
+
+        \code{.cpp}
+        // Set M-2 and M-3's mode to step and direction
+        MotorMgr.MotorModeSet(MotorManager::MOTOR_M2M3,
+                                Connector::CPM_MODE_STEP_AND_DIR);
+        \endcode
+
+        \param[in] motorPair Connectors to be set to specified mode.
+        \param[in] newMode Connector modes to be set.
+        The valid modes for the MotorDriver connectors are:
+        - Connector#CPM_MODE_STEP_AND_DIR
+        - Connector#CPM_MODE_A_DIRECT_B_DIRECT
+        - Connector#CPM_MODE_A_DIRECT_B_PWM
+        - Connector#CPM_MODE_A_PWM_B_PWM.
+
+        \return Success
+    **/
+    bool MotorModeSet(MotorPair motorPair, Connector::ConnectorModes newMode);
+
+protected:
+    uint8_t m_gclkIndex;
+    MotorClockRates m_clockRate;
+    ClearCorePorts m_stepPorts[NUM_MOTOR_PAIRS];
+    uint32_t m_stepDataBits[NUM_MOTOR_PAIRS];
+    Connector::ConnectorModes m_motorModes[NUM_MOTOR_PAIRS];
+
+private:
+#define CPM_CLOCK_RATE_LOW_HZ \
+    (100000 / _CLEARCORE_SAMPLE_RATE_HZ * _CLEARCORE_SAMPLE_RATE_HZ)
+#define CPM_CLOCK_RATE_NORMAL_HZ \
+    (500000 / _CLEARCORE_SAMPLE_RATE_HZ * _CLEARCORE_SAMPLE_RATE_HZ)
+#define CPM_CLOCK_RATE_HIGH_HZ \
+    (2000000 / _CLEARCORE_SAMPLE_RATE_HZ * _CLEARCORE_SAMPLE_RATE_HZ)
+
+    bool m_initialized;
+
+    /**
+        Construct, wire in the Gclk and the mode control pins
+    **/
+    MotorManager();
+
+    void PinMuxSet();
+};
+
+} // ClearCore namespace
+
+#endif  // __MOTORMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/NvmManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/NvmManager.h
new file mode 100644
index 000000000..dccda89bb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/NvmManager.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file NvmManager.h
+    Non-Volatile Memory Interface for the ClearCore Board
+**/
+
+#ifndef __NVMMANAGER_H__
+#define __NVMMANAGER_H__
+
+#include <stdint.h>
+#include <sam.h>
+
+#ifndef HIDE_FROM_DOXYGEN
+namespace ClearCore {
+
+/**
+    \brief ClearCore Board Non-Volatile Memory Interface
+
+    This class manages the non-volatile memory of the Teknic ClearCore board.
+
+    Data is stored in the USER section of memory.
+    the User section is protected from Chip Erase, making it ideal for
+    persistent info like MAC Address, Serial Config, etc.
+    The User section is erasable by page, and writable by quad word.
+    We keep a page cached so that we know what to write back once we clear the
+    page.
+    The writes will write the cache back to memory quad word at a time.
+
+    \note Writing to NVM does not immediately update what will be read from
+    that memory, this is why we read from cache.
+
+    \note Access will fail if the UF2 boot loader has not been run
+**/
+class NvmManager {
+public:
+
+    /**
+        Define byte-offsets for user-accessible NVM space
+    **/
+    typedef enum {
+        NVM_LOC_USER_START      = 0, // First user-accessible byte after
+        // Microchip's reserved 32 bytes (Section
+        // 9.4 NVM User Page Mapping in the
+        // datasheet)
+
+        NVM_LOC_RESERVED_TEKNIC = 416, // Reserved 64 bytes of data for
+        // Teknic use
+
+        NVM_LOC_USER_MAX = NVMCTRL_PAGE_SIZE - 32,   // 480
+
+        NVM_LOC_HW_REVISION = NVM_LOC_USER_MAX - 18,   // 462
+        NVM_LOC_SERIAL_NUMBER = NVM_LOC_USER_MAX - 16, // 464
+
+        NVM_LOC_MAC_FIRST  = NVM_LOC_USER_MAX - 12,    // 468
+        NVM_LOC_MAC_SECOND = NVM_LOC_USER_MAX - 8,     // 472
+
+        NVM_LOC_DAC_ZERO = NVM_LOC_USER_MAX - 4,       // 476
+        NVM_LOC_DAC_SPAN = NVM_LOC_USER_MAX - 2,       // 478
+
+    } NvmLocations;
+
+    /**
+        Public accessor for singleton instance
+    **/
+    static NvmManager &Instance();
+
+    /**
+        \brief Read octet from NVM
+
+        \param[in] nvmLocation location to read from
+    **/
+    int8_t Byte(NvmLocations nvmLocation);
+    /**
+        \brief Write octet to NVM
+
+        \param[in] nvmLocation location to write to
+        \param[in] newValue value to write
+
+        \return True if the write was submitted, false otherwise
+    **/
+    bool Byte(NvmLocations nvmLocation, int8_t newValue);
+
+
+    /**
+        \brief Read 16-bit integer from NVM
+
+        \param[in] nvmLocation location to read from
+
+        \note nvmLocation is the byte address into NVM
+    **/
+    int16_t Int16(NvmLocations nvmLocation);
+    /**
+        \brief Write 16-bit integer to NVM
+
+        \param[in] nvmLocation location to write to
+        \param[in] newValue value to write
+
+        \note nvmLocation is the byte address into NVM
+        \return True if the write was submitted, false otherwise
+    **/
+    bool Int16(NvmLocations nvmLocation, int16_t newValue);
+
+
+    /**
+        \brief Read 32-bit integer from NVM
+
+        \param[in] nvmLocation location to read from
+
+        \note nvmLocation is the byte address into NVM
+    **/
+    int32_t Int32(NvmLocations nvmLocation);
+    /**
+        \brief Write 32-bit integer to NVM
+
+        \param[in] nvmLocation location to write to
+        \param[in] newValue value to write
+
+        \note nvmLocation is the byte address into NVM
+        \return True if the write was submitted, false otherwise
+    **/
+    bool Int32(NvmLocations nvmLocation, int32_t newValue);
+
+    /**
+        \brief Read 64-bit integer from NVM
+
+        Reads the location at nvmLocationStart and nvmLocatinStart+1
+        and appends to two together
+
+        \param[in] nvmLocationStart location to start read
+    **/
+    int64_t Int64(NvmLocations nvmLocationStart);
+    /**
+        \brief Write 64-bit integer to NVM
+
+        \param[in] nvmLocationStart location to start write
+        \param[in] newValue value to write
+
+        \note nvmLocation is the byte address into NVM
+        \return True if the write was submitted, false otherwise
+    **/
+    bool Int64(NvmLocations nvmLocationStart, int64_t newValue);
+
+    /**
+        \brief Read a block of bytes from NVM
+
+        \param[in] nvmLocationStart location to start read
+        \param[in] lengthInBytes number of bytes to read
+        \param[in] p_data pointer to store read data
+    **/
+    void BlockRead(NvmLocations nvmLocationStart, int lengthInBytes, uint8_t * const p_data);
+
+    /**
+        \brief Write a block of bytes to NVM
+
+        \param[in] nvmLocationStart location to start write
+        \param[in] lengthInBytes number of bytes to write
+        \param[in] p_data pointer to store read data
+
+        \return True if the write was submitted, false otherwise
+    **/
+    bool BlockWrite(NvmLocations nvmLocationStart, int lengthInBytes, uint8_t const * const p_data);
+
+
+    /**
+        \brief Get the MAC address of the ClearCore.
+
+        \param[out] macAddress An unsigned byte pointer to store the MAC address
+        of this device.
+        \note Make sure to have allocated six bytes to store the full address!
+        This function will always write six bytes starting at macAddress[0].
+    **/
+    void MacAddress(uint8_t *macAddress);
+
+    /**
+        \brief Get the serial number of the ClearCore as an unsigned 32-bit
+        integer value.
+
+        \return An unsigned 32-bit integer representation of the ClearCore's
+        serial number.
+    **/
+    uint32_t SerialNumber();
+
+    bool FinishNvmWrite() {
+        while (m_pageModified || m_writeState != IDLE) {
+            if (WriteCacheToNvmProc()) {
+                continue;
+            }
+            else {
+                return false;
+            }
+        }
+        return true;
+    }
+
+    bool Synchonized() const {
+        return !m_pageModified;
+    }
+
+private:
+
+    typedef enum {
+        IDLE,
+        CLEAR_PAGE_BUFFER,
+        ERASE_PAGE,
+        WRITE_DATA,
+    } WriteCacheState;
+
+    // Page cache is a byte array.
+    int8_t m_nvmPageCache[NVMCTRL_PAGE_SIZE];
+    // The page cache gets written to NVM as 32-bit pieces
+    int32_t *m_nvmPageCache32;
+    WriteCacheState m_writeState;
+    uint8_t m_quadWordIndex;
+    bool m_pageModified;
+
+    /**
+        \brief Constructor
+
+        Will initialize the page cache if not already done
+    **/
+    NvmManager();
+
+    /**
+        \brief Populates the nvmPageCache from NVM
+
+        \note Will try to lock the mutex, make sure the calling function has
+        released the lock.
+    **/
+    void PopulateCache();
+
+    /**
+        \brief Write the cache to NVM.
+
+        \return Success
+
+        \note Will try to lock the mutex, make sure the calling function has
+        released the lock.
+    **/
+    bool WriteCacheToNvm();
+
+    /**
+        \brief State machine to write cache to NVM
+
+        \return Cache was successfully written
+
+        \note Using the state machine time splices writing, making it take longer
+    **/
+    bool WriteCacheToNvmProc();
+
+    bool BlockWrite();
+}; //NvmManager
+
+} // ClearCore namespace
+#endif // HIDE_FROM_DOXYGEN
+#endif // __NVMMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/PeripheralRoute.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/PeripheralRoute.h
new file mode 100644
index 000000000..02ded7191
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/PeripheralRoute.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+  \file PeripheralRoute.h
+  \brief Defines the Peripheral Route structure, used in HardwareMapping
+**/
+
+#ifndef __PERIPHERAL_ROUTE_H__
+#define __PERIPHERAL_ROUTE_H__
+
+#include <sam.h>
+
+/** ClearCore I/O pin groups **/
+typedef enum {
+    NOT_A_PORT = -1,
+    PORTA = 0,
+    PORTB,
+    PORTC,
+    CLEARCORE_PORT_MAX // Keep as last item
+} ClearCorePorts;
+
+#ifndef HIDE_FROM_DOXYGEN
+struct PeripheralRoute {
+    uint8_t pin_raw;
+    ClearCorePorts gpioPort;
+    uint8_t gpioPin;
+    uint8_t extInt;
+    bool extIntAvail;
+    uint8_t adc0Channel;
+    uint8_t adc1Channel;
+    uint8_t dacChannel;
+    uint8_t sercomNum;
+    uint8_t sercomPadNum;
+    uint8_t tcNum;
+    uint8_t tcPadNum;
+    uint8_t tccNum;
+    uint8_t tccPadNum;
+    uint8_t gclkNum;
+};
+#endif
+
+#endif // __PERIPHERAL_ROUTE_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/Phy.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/Phy.h
new file mode 100644
index 000000000..9d85f6400
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/Phy.h
@@ -0,0 +1,160 @@
+/*
+* Copyright (c) 2020 Teknic, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*/
+
+/**
+    \file Phy.h
+    An incomplete interface to the KSZ8081 Ethernet PHY chip.
+**/
+/************************ PHY ****************************/
+#ifndef __PHY_H__
+#define __PHY_H__
+
+#ifndef HIDE_FROM_DOXYGEN
+// Ethernet PHY Operations
+#define PHY_READ_OP         2
+#define PHY_WRITE_OP        1
+
+// Ethernet PHY Auto-Negotiated Modes
+#define PHY_CTRL_AN_MSK 0x0007
+#define BASE_10_HDX     0x1
+#define BASE_10_FDX     0x5
+#define BASE_100_HDX    0x2
+#define BASE_100_FDX    0x6
+
+#define PHY_CTRL_AN_SPD_MSK 0x2
+#define PHY_CTRL_AN_FD_MSK  0x4
+
+// Ethernet PHY Registers
+#define PHY_B_CTRL      0x00
+#define PHY_B_STATUS    0x01
+#define PHY_ID_1        0x02
+#define PHY_ID_2        0x03
+#define PHY_ANA         0x04
+#define PHY_ANLP        0x05
+#define PHY_ANE         0x06
+#define PHY_ANNP        0x07
+#define PHY_LPNP        0x08
+// reserved
+#define PHY_DRC         0x10
+#define PHY_AFE_CTRL    0x11
+// reserved
+#define PHY_RXER_COUNT  0x15
+#define PHY_ICS         0x1B
+#define PHY_LMD         0x1D
+#define PHY_CTRL_1      0x1E
+#define PHY_CTRL_2      0x1F
+
+// PHY_B_CTRL: Ethernet PHY Register 0h - Basic Control
+#define PHY_B_CTRL_COLEN_Pos 7   /**< \brief (PHY_B_CTRL) Enable Collision Test */
+#define PHY_B_CTRL_COLEN     (_U_(0x1) << PHY_B_CTRL_COLEN_Pos)
+#define PHY_B_CTRL_DPLX_Pos  8   /**< \brief (PHY_B_CTRL) Duplex Mode */
+#define PHY_B_CTRL_DPLX      (_U_(0x1) << PHY_B_CTRL_DPLX_Pos)
+#define PHY_B_CTRL_RAN_Pos   9   /**< \brief (PHY_B_CTRL) Restart Auto-Negotiation */
+#define PHY_B_CTRL_RAN       (_U_(0x1) << PHY_B_CTRL_RAN_Pos)
+#define PHY_B_CTRL_ISO_Pos   10  /**< \brief (PHY_B_CTRL) Electrical Isolation of PHY */
+#define PHY_B_CTRL_ISO       (_U_(0x1) << PHY_B_CTRL_ISO_Pos)
+#define PHY_B_CTRL_PD_Pos    11  /**< \brief (PHY_B_CTRL) Power-Down */
+#define PHY_B_CTRL_PD        (_U_(0x1) << PHY_B_CTRL_PD_Pos)
+#define PHY_B_CTRL_ANEN_Pos  12  /**< \brief (PHY_B_CTRL) Auto-Negotiation Enable */
+#define PHY_B_CTRL_ANEN      (_U_(0x1) << PHY_B_CTRL_ANEN_Pos)
+#define PHY_B_CTRL_SPD_Pos   13  /**< \brief (PHY_B_CTRL) Speed Select */
+#define PHY_B_CTRL_SPD       (_U_(0x1) << PHY_B_CTRL_SPD_Pos)
+#define PHY_B_CTRL_LB_Pos    14  /**< \brief (PHY_B_CTRL) Loopback Mode */
+#define PHY_B_CTRL_LB        (_U_(0x1) << PHY_B_CTRL_LB_Pos)
+#define PHY_B_CTRL_RES_Pos   15  /**< \brief (PHY_B_CTRL) Software Reset */
+#define PHY_B_CTRL_RES       (_U_(0x1) << PHY_B_CTRL_RES_Pos)
+
+// PHY_B_STATUS: Ethernet PHY Register 1h - Basic Status
+#define PHY_B_STATUS_EC_Pos     0   /**< \brief (PHY_B_STATUS) Extended Capability */
+#define PHY_B_STATUS_EC         (_U_(0x1) << PHY_B_STATUS_EC_Pos)
+#define PHY_B_STATUS_JAB_Pos    1   /**< \brief (PHY_B_STATUS) Jabber Detect */
+#define PHY_B_STATUS_JAB        (_U_(0x1) << PHY_B_STATUS_JAB_Pos)
+#define PHY_B_STATUS_LU_Pos     2   /**< \brief (PHY_B_STATUS) Link Status */
+#define PHY_B_STATUS_LU         (_U_(0x1) << PHY_B_STATUS_LU_Pos)
+#define PHY_B_STATUS_AN_Pos     3   /**< \brief (PHY_B_STATUS) Auto-Negotiation Ability */
+#define PHY_B_STATUS_AN         (_U_(0x1) << PHY_B_STATUS_AN_Pos)
+#define PHY_B_STATUS_REMF_Pos   4   /**< \brief (PHY_B_STATUS) Remote Fault */
+#define PHY_B_STATUS_REMF       (_U_(0x1) << PHY_B_STATUS_REMF_Pos)
+#define PHY_B_STATUS_ANC_Pos    5   /**< \brief (PHY_B_STATUS) Auto-Negotiation Complete */
+#define PHY_B_STATUS_ANC        (_U_(0x1) << PHY_B_STATUS_ANC_Pos)
+#define PHY_B_STATUS_NPRE_Pos   6   /**< \brief (PHY_B_STATUS) No Preamble */
+#define PHY_B_STATUS_NPRE       (_U_(0x1) << PHY_B_STATUS_NPRE_Pos)
+#define PHY_B_STATUS_TBTHD_Pos  11  /**< \brief (PHY_B_STATUS) 10BASE-T Half-Duplex Capable */
+#define PHY_B_STATUS_TBTHD      (_U_(0x1) << PHY_B_STATUS_TBTHD_Pos)
+#define PHY_B_STATUS_TBTFD_Pos  12  /**< \brief (PHY_B_STATUS) 10BASE-T Full-Duplex Capable */
+#define PHY_B_STATUS_TBTFD      (_U_(0x1) << PHY_B_STATUS_TBTFD_Pos)
+#define PHY_B_STATUS_HBTHD_Pos  13  /**< \brief (PHY_B_STATUS) 100BASE-T Half-Duplex Capable */
+#define PHY_B_STATUS_HBTHD      (_U_(0x1) << PHY_B_STATUS_HBTHD_Pos)
+#define PHY_B_STATUS_HBTFD_Pos  14  /**< \brief (PHY_B_STATUS) 100BASE-T Full-Duplex Capable */
+#define PHY_B_STATUS_HBTFD      (_U_(0x1) << PHY_B_STATUS_HBTFD_Pos)
+#define PHY_B_STATUS_TFOUR_Pos  15  /**< \brief (PHY_B_STATUS) 100BASE-T4 Capable */
+#define PHY_B_STATUS_TFOUR      (_U_(0x1) << PHY_B_STATUS_TFOUR_Pos)
+
+// PHY_ICS : Ethernet PHY Register 1Bh - Interrupt Control/Status
+#define PHY_ICS_LU_Pos      0   /**< \brief (PHY_ICS) Link-Up Interrupt */
+#define PHY_ICS_LU          (_U_(0x1) << PHY_ICS_LU_Pos)
+#define PHY_ICS_RF_Pos      1   /**< \brief (PHY_ICS) Remote Fault Interrupt */
+#define PHY_ICS_RF          (_U_(0x1) << PHY_ICS_RF_Pos)
+#define PHY_ICS_LD_Pos      2   /**< \brief (PHY_ICS) Link-Down Interrupt */
+#define PHY_ICS_LD          (_U_(0x1) << PHY_ICS_LD_Pos)
+#define PHY_ICS_LPA_Pos     3   /**< \brief (PHY_ICS) Link Partner Acknowledge Interrupt */
+#define PHY_ICS_LPA         (_U_(0x1) << PHY_ICS_LPAEN_Pos)
+#define PHY_ICS_PDF_Pos     4   /**< \brief (PHY_ICS) Parallel Detect Fault Interrupt */
+#define PHY_ICS_PDF         (_U_(0x1) << PHY_ICS_PDF_Pos)
+#define PHY_ICS_PRX_Pos     5   /**< \brief (PHY_ICS) Page Receive Interrupt */
+#define PHY_ICS_PRX         (_U_(0x1) << PHY_ICS_PRX_Pos)
+#define PHY_ICS_RXER_Pos    6   /**< \brief (PHY_ICS) Receive Error Interrupt */
+#define PHY_ICS_RXER        (_U_(0x1) << PHY_ICS_RXER_Pos)
+#define PHY_ICS_JAB_Pos     7   /**< \brief (PHY_ICS) Jabber Interrupt */
+#define PHY_ICS_JAB         (_U_(0x1) << PHY_ICS_JAB_Pos)
+#define PHY_ICS_LUEN_Pos    8   /**< \brief (PHY_ICS) Link-Up Interrupt Enable */
+#define PHY_ICS_LUEN        (_U_(0x1) << PHY_ICS_LUEN_Pos)
+#define PHY_ICS_RFEN_Pos    9   /**< \brief (PHY_ICS) Remote Fault Interrupt Enable */
+#define PHY_ICS_RFEN        (_U_(0x1) << PHY_ICS_RFEN_Pos)
+#define PHY_ICS_LDEN_Pos    10  /**< \brief (PHY_ICS) Link-Down Interrupt Enable */
+#define PHY_ICS_LDEN        (_U_(0x1) << PHY_ICS_LDEN_Pos)
+#define PHY_ICS_LPAEN_Pos   11  /**< \brief (PHY_ICS) Link Partner Acknowledge Interrupt Enable */
+#define PHY_ICS_LPAEN       (_U_(0x1) << PHY_ICS_LPAEN_Pos)
+#define PHY_ICS_PDFEN_Pos   12  /**< \brief (PHY_ICS) Parallel Detect Fault Interrupt Enable */
+#define PHY_ICS_PDFEN       (_U_(0x1) << PHY_ICS_PDFEN_Pos)
+#define PHY_ICS_PRXEN_Pos   13  /**< \brief (PHY_ICS) Page Receive Interrupt Enable */
+#define PHY_ICS_PRXEN       (_U_(0x1) << PHY_ICS_PRXEN_Pos)
+#define PHY_ICS_RXEREN_Pos  14  /**< \brief (PHY_ICS) Receive Error Interrupt Enable */
+#define PHY_ICS_RXEREN      (_U_(0x1) << PHY_ICS_RXEREN_Pos)
+#define PHY_ICS_JABEN_Pos   15  /**< \brief (PHY_ICS) Jabber interrupt enable */
+#define PHY_ICS_JABEN       (_U_(0x1) << PHY_ICS_JABEN_Pos)
+
+// PHY_LMD : Ethernet Phy Register 1Dh - LinkMD Control/Status
+#define PHY_LMD_FC_Pos      0   /**< \brief (PHY_LMD) Cable Fault Counter */
+#define PHY_LMD_FC_Msk      (_U_(0x1FF) << PHY_LMD_FC_Pos)
+#define PHY_LMD_FC(value)   (PHY_LMD_FC_Msk & ((value) << PHY_LMD_FC_Pos))
+#define PHY_LMD_SCI_Pos     12  /**< \brief (PHY_LMD) Short Cable Indicator */
+#define PHY_LMD_SCI         (_U_(0x1) << PHY_LMD_SCI_Pos)
+#define PHY_LMD_CDTR_Pos    13  /**< \brief (PHY_LMD) Cable Diagnostic Test Result */
+#define PHY_LMD_CDTR_Msk    (_U_(0x3) << PHY_LMD_CDTR_Pos)
+#define PHY_LMD_CDTR(value) (PHY_LMD_CDTR_Msk & ((value) << PHY_LMD_CDTR_Pos))
+#define PHY_LMD_CDEN_Pos    15  /**< \brief (PHY_LMD) Cable Diagnostic Test Enable */
+#define PHY_LMD_CDEN        (_U_(0x1) << PHY_LMD_CDEN_Pos)
+
+#endif // !HIDE_FROM_DOXYGEN
+
+#endif // !__PHY_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SdCardDriver.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SdCardDriver.h
new file mode 100644
index 000000000..323ef76c6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SdCardDriver.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SdCardDriver.h
+    This class controls access to the micro SD Card reader.
+
+    The class will provide SD card support for data logging, configuration
+    files, and disk emulation.
+**/
+
+#ifndef __SDCARDDRIVER_H__
+#define __SDCARDDRIVER_H__
+
+#include <stdint.h>
+#include "PeripheralRoute.h"
+#include "SerialBase.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore SD card interface
+
+    This class manages access to the micro SD Card reader.
+**/
+class SdCardDriver : public SerialBase {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager
+    **/
+    SdCardDriver() {};
+
+    /**
+        \brief Signal an error in the SD card
+
+        \param[in] errorCode An error code; constants are defined in SD.h
+    **/
+    void SetErrorCode(uint8_t errorCode) {
+        m_errorCode = errorCode;
+    }
+
+    /**
+        \brief Check if the SD card is in a fault state
+
+        \return True if an error code is present
+    **/
+    bool IsInFault() {
+        return (m_errorCode != 0);
+    }
+#endif // HIDE_FROM_DOXYGEN
+
+private:
+    uint8_t m_errorCode;
+
+    /**
+        Construction, wires in pins and non-volatile info.
+    **/
+    SdCardDriver(const PeripheralRoute *misoPin,
+                 const PeripheralRoute *ssPin,
+                 const PeripheralRoute *sckPin,
+                 const PeripheralRoute *mosiPin,
+                 uint8_t peripheral);
+};
+
+} // ClearCore namespace
+
+#endif // __SDCARDDRIVER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialBase.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialBase.h
new file mode 100644
index 000000000..860d5cf92
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialBase.h
@@ -0,0 +1,673 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SerialBase.h
+    This class controls access to the Serial Port device in the ARM processor.
+
+    It will allow you to set up:
+        - Asynchronous Serial transfers
+        - SPI transfers
+**/
+
+#ifndef __SERIALBASE_H__
+#define __SERIALBASE_H__
+
+#include <stdint.h>
+#include <sam.h>
+#include "DmaManager.h"
+#include "ISerial.h"
+#include "PeripheralRoute.h"
+
+namespace ClearCore {
+
+/** Size of the serial send and receive buffers, in bytes (64). **/
+#ifndef SERIAL_BUFFER_SIZE
+#define SERIAL_BUFFER_SIZE 64
+#endif
+
+/** Serial receive interrupt priority level. **/
+#ifndef SERCOM_NVIC_RX_PRIORITY
+#define SERCOM_NVIC_RX_PRIORITY (static_cast<IRQn_Type>(1))
+#endif
+/** Serial transmit interrupt priority level. **/
+#ifndef SERCOM_NVIC_TX_PRIORITY
+#define SERCOM_NVIC_TX_PRIORITY (static_cast<IRQn_Type>(1))
+#endif
+/** Serial error interrupt priority level. **/
+#ifndef SERCOM_NVIC_ERR_PRIORITY
+#define SERCOM_NVIC_ERR_PRIORITY (static_cast<IRQn_Type>(7))
+#endif
+
+/**
+    \brief ClearCore ARM Serial Port base class
+
+    This class is used to create a buffered serial port.
+**/
+class SerialBase : public ISerial {
+    friend class TestIO;
+
+public:
+    /**
+        Break detected 'character' placed in the character stream when
+        the break condition has been detected.
+    **/
+    static const int16_t BREAK_DETECTED = int16_t(0xBDBD);
+
+    /**
+        No character available indicator.
+    **/
+    static const int16_t EOB = -1;
+
+    /**
+        \union SerialErrorStatusRegister
+
+        A register to report errors detected on the serial port.
+    **/
+    union SerialErrorStatusRegister {
+        /**
+            Broad access to the whole register
+        **/
+        uint32_t reg;
+
+        /**
+            Field access to the register
+        **/
+        struct {
+            /**
+                A frame error has been detected on the serial port.
+            **/
+            uint32_t SerialFrameError      : 1;
+            /**
+                A parity error has been detected on the serial port.
+            **/
+            uint32_t SerialParityError     : 1;
+            /**
+                An overflow error has been detected on the serial port.
+            **/
+            uint32_t SerialOverflowError   : 1;
+        } bit;
+
+        /**
+            Serial error register default constructor
+        **/
+        SerialErrorStatusRegister() {
+            reg = 0;
+        }
+
+        /**
+            Serial error register constructor with initial value
+        **/
+        SerialErrorStatusRegister(uint32_t val) {
+            reg = val;
+        }
+
+        /**
+             Interpret the serial error register as a boolean by reporting
+             whether any bits are set.
+         **/
+        operator bool() const {
+            return reg > 0;
+        }
+    };
+
+    /**
+        MSB-first or LSB-first data order.
+    **/
+    typedef enum {
+        /// Most significant bit first
+        COM_MSB_FIRST = 0,
+        /// Least significant bit first
+        COM_LSB_FIRST = 1
+    } DataOrders;
+
+    /**
+        Sets the serial port into Asynchronous vs SPI mode.
+    **/
+    typedef enum {
+        /// Universal Asynchronous Receiver-Transmitter (UART) mode
+        UART,
+        /// Serial Peripheral Interface (SPI) mode
+        SPI
+    } PortModes;
+
+    /**
+        The different polarities for the SPI clock.
+    **/
+    typedef enum {
+        /// SCK is low when idle
+        SCK_LOW = 0,
+        /// SCK is high when idle
+        SCK_HIGH
+    } SpiClockPolarities;
+
+    /**
+        The SPI clock phase settings.
+    **/
+    typedef enum {
+        /// Leading edge samples, trailing edge changes
+        LEAD_SAMPLE = 0,
+        /// Leading edge changes, trailing edge samples
+        LEAD_CHANGE
+    } SpiClockPhases;
+
+    /**
+        Modes for the serial port control lines.
+    **/
+    typedef enum {
+        /// Control line is in the OFF state
+        LINE_OFF,
+        /// Control line is in the ON state
+        LINE_ON,
+        /// Control line is controlled by hardware
+        LINE_HW,
+    } CtrlLineModes;
+
+    // ======================= MODE INDEPENDENT API ============================
+    /**
+        \brief Setup the port mode.
+
+        Puts the port into SPI or UART mode for subsequent transfers.
+
+        \code{.cpp}
+        if (ConnectorCOM1.PortMode(SerialBase::UART)) {
+            // Setting COM-1's mode to UART was successful
+        }
+        \endcode
+
+        \param[in] newMode The requested serial mode.
+        \return Returns true if the mode is successfully set.
+    **/
+    bool PortMode(PortModes newMode);
+
+    // ========================== ISerial  API =================================
+    /**
+        \copydoc ISerial::Flush()
+    **/
+    void Flush() override;
+    /**
+        \copydoc ISerial::FlushInput()
+    **/
+    void FlushInput() override;
+
+    /**
+       \copydoc ISerial::PortOpen()
+    **/
+    virtual void PortOpen() override;
+
+    /**
+        \copydoc ISerial::PortClose()
+    **/
+    virtual void PortClose() override;
+
+    /**
+        \copydoc ISerial::Speed(uint32_t bitsPerSecond)
+        Will return false if the baud rate gets clipped for SPI mode.
+    **/
+    virtual bool Speed(uint32_t bitsPerSecond) override;
+
+    /**
+        \copydoc ISerial::Speed()
+    **/
+    virtual uint32_t Speed() override {
+        return m_baudRate;
+    }
+
+    /**
+        \copydoc ISerial::CharGet()
+    **/
+    int16_t CharGet() override;
+
+    /**
+        \copydoc ISerial::CharPeek()
+    **/
+    int16_t CharPeek() override;
+
+    /**
+        \copydoc ISerial::SendChar(uint8_t charToSend)
+    **/
+    bool SendChar(uint8_t charToSend) override;
+
+    /**
+        \copydoc ISerial::AvailableForRead()
+    **/
+    int32_t AvailableForRead() override;
+
+    /**
+         \copydoc ISerial::AvailableForWrite()
+    **/
+    int32_t AvailableForWrite() override;
+
+    /**
+        \copydoc ISerial::WaitForTransmitIdle()
+    **/
+    void WaitForTransmitIdle() override;
+
+    /**
+        \copydoc ISerial::PortIsOpen()
+    **/
+    bool PortIsOpen() override;
+
+    /**
+        \brief Set UART CTS/RTS flow control.
+
+        \code{.cpp}
+        ConnectorCOM0.FlowControl(true);
+        \endcode
+
+        \param[in] useFlowControl The new flow control setting.
+        \note Flow control is off by default. Some XBee devices have flow
+        control enabled by default. If using an XBee device, the ClearCore flow
+        control setting should match the XBee device setting.
+    **/
+    void FlowControl(bool useFlowControl);
+
+    /**
+        \brief Return whether UART CTS/RTS flow control is enabled.
+
+        \code{.cpp}
+        if (ConnectorCOM0.FlowControl()) {
+            // COM-0's flow control is enabled
+        }
+        \endcode
+
+        \return Returns true if port flow control setting is enabled.
+    **/
+    bool FlowControl() {
+        return m_flowControl;
+    };
+
+    /**
+        \brief Change the serial RTS mode
+
+        \code{.cpp}
+        if (ConnectorCOM0.RtsMode(SerialBase::LINE_ON)) {
+            // COM-0's RTS line has asserted successfully
+        }
+        \endcode
+
+        \param[in] mode The desired RTS pin mode.
+        \return Returns true if the mode was set.
+        \note Using #LINE_HW with #FlowControl enabled will
+        assert RTS when the Serial Port is ready to receive data.
+    **/
+    bool RtsMode(CtrlLineModes mode);
+
+    /**
+        \brief Read the serial CTS state.
+
+        \code{.cpp}
+        if (ConnectorCOM0.CtsState()) {
+            // COM-0's CTS pin is logical LINE_ON.
+        }
+        \endcode
+
+        \return Returns true if the CTS pin is #LINE_ON.
+    **/
+    bool CtsState();
+
+    /**
+        \brief Initiate a Serial Break
+
+        \code{.cpp}
+        // Enables a serial break on COM-0
+        ConnectorCOM1.SerialBreak(true);
+        \endcode
+
+        \param[in] enable true enables a serial break, false disables a serial
+        break
+    **/
+    void SerialBreak(bool enable);
+
+    /**
+        \brief Set UART transmission parity format.
+
+        \code{.cpp}
+        if (ConnectorCOM1.Parity(SerialBase::PARITY_O)) {
+            // Setting COM-1's parity format to odd was successful
+        }
+        \endcode
+
+        \return Returns true if port accepted the format change request.
+    **/
+    bool Parity(Parities newParity) override;
+
+    /**
+        \brief Return current port UART transmission format.
+
+        \code{.cpp}
+        if (ConnectorCOM0.Parity() == SerialBase::PARITY_O) {
+            // COM-0's parity format is set to odd
+        }
+        \endcode
+
+        \return Returns transmission format enumeration.
+    **/
+    Parities Parity() override {
+        return m_parity;
+    }
+
+    /**
+        Change the number of stop bits used in UART communication.
+
+        \code{.cpp}
+        // Sets COM-0 to require two stop bits
+        ConnectorCOM1.StopBits(2);
+        \endcode
+    **/
+    bool StopBits(uint8_t bits) override;
+
+    /**
+        \brief Change the number of bits in a character.
+
+        For UART mode valid settings are: 5, 6, 7, 8, or 9.
+        For SPI mode valid settings are: 8 or 9.
+
+        \code{.cpp}
+        // Sets COM-0 to have a 9-bit character size
+        ConnectorCOM1.CharSize(9);
+        \endcode
+    **/
+    bool CharSize(uint8_t size) override;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        bool operator for compatibility with ISerial
+    **/
+    operator bool() override {
+        return true;
+    }
+#endif
+
+    // =============================== SPI API =================================
+
+    /**
+        \brief Change the polarity and phase for the SPI clock
+
+        \code{.cpp}
+        // Set up COM-0's SPI clock
+        ConnectorCOM0.SpiClock(SerialBase::SCK_HIGH, SerialBase::LEAD_SAMPLE);
+        \endcode
+    **/
+    void SpiClock(SpiClockPolarities polarity, SpiClockPhases phase);
+
+    /**
+        \brief Change the SPI Slave Select mode
+
+        \code{.cpp}
+        if (ConnectorCOM0.SpiSsMode(SerialBase::LINE_HIGH)) {
+            // COM-0's SPI slave select mode set to high successfully
+        }
+        \endcode
+
+        \param[in] mode The desired SS pin mode.
+        \return Returns true if the mode was set.
+    **/
+    bool SpiSsMode(CtrlLineModes mode);
+
+    /**
+        SPI's transmit and receive function
+    **/
+    uint8_t SpiTransferData(uint8_t data);
+
+    /**
+        \brief SPI's multi-byte transmit and receive function
+
+        This can be used to send/receive a buffer's worth of data. The
+        SPI channel will be commanded to transfer a byte at a time for
+        the given \a len of bytes. The data transferred out will come from
+        the \a writeBuf or a dummy value, and the data received in will be
+        written to the \a readBuf or a dummy value.
+
+        \param[in] writeBuf A pointer to the beginning of the data to write
+        \param[in] readBuf A pointer to the beginning of a read destination
+        for the data in the serial port
+        \param[in] len The maximum number of bytes to read and write
+        \return The number of bytes written or read.
+    **/
+    int32_t SpiTransferData(
+        uint8_t const *writeBuf, uint8_t *readBuf, int32_t len);
+
+    /**
+        \brief SPI's asynchronous multi-byte transmit and receive function
+
+        This can be used to send/receive a buffer's worth of data. The
+        SPI channel will be commanded to transfer \a len of bytes asynchronously
+        via the Direct Memory Access Controller. The data transferred out will
+        come from the \a writeBuf or a dummy value, and the data received in
+        will be written to the \a readBuf or a dummy value.
+
+        \param[in] writeBuf A pointer to the beginning of the data to write
+        \param[in] readBuf A pointer to the beginning of a read destination
+        for the data in the serial port
+        \param[in] len The maximum number of bytes to read and write
+        \return True if transfer completed successfully, false otherwise.
+    **/
+    bool SpiTransferDataAsync(
+        uint8_t const *writeBuf, uint8_t *readBuf, int32_t len);
+
+    /**
+        \brief Block until asynchronous transfers are completed.
+        \return True when all asynchronous transfers are completed.
+        Does not return false.
+    **/
+    bool SpiAsyncWaitComplete();
+
+    // ============================= SETUP API =================================
+
+    /**
+        \brief Change the data order for the port.
+
+        For UART, this should most likely be set to #COM_LSB_FIRST.
+    **/
+    void DataOrder(DataOrders newOrder);
+
+    // ========================= ERROR HANDLING API ============================
+    /**
+        Handles frame errors by clearing the error flag and raising an
+        internal warning flag.
+    **/
+    void HandleFrameError();
+
+    /**
+        Handles parity errors by clearing the error flag and raising an
+        internal warning flag.
+    **/
+    void HandleParityError();
+
+    /**
+        Handles overflow errors by clearing the error flag and raising an
+        internal warning flag.
+    **/
+    void HandleOverflow();
+
+    /**
+        \brief Accumulating clear on read accessor for any error status bits
+        that were asserted sometime since the previous invocation of this
+        function.
+
+        \code{.cpp}
+        // See if an overflow error has occurred on COM-0 since the last poll.
+        bool serialOverflowError =
+            ConnectorCOM0.ErrorStatusAccum().bit.SerialOverflowError;
+        if (serialOverflowError) {
+            // Deal with the overflow.
+        }
+        \endcode
+
+        \param[in] mask (optional) A SerialErrorStatusRegister whose asserted
+        bits indicate which of the error status bits to check for an asserted
+        state. If one of the \a bit members of this mask are deasserted, that
+        bit will be ignored when checking for asserted status bits. If no
+        \a mask is provided, it's equivalent to passing a
+        SerialErrorStatusRegister with all bits asserted, in which case this
+        function would report any accumulated asserted error status bits.
+
+        \return SerialErrorStatusRegister whose asserted bits indicate which
+        serial error status bits have been asserted since the last poll.
+    **/
+    SerialErrorStatusRegister ErrorStatusAccum(SerialErrorStatusRegister mask =
+                UINT32_MAX);
+
+#ifndef HIDE_FROM_DOXYGEN
+    //========================= INTERRUPT HANDLERS =============================
+
+    /**
+        \brief Should be called by SERCOMx_0 Interrupt Vector.
+
+        This is typically associated with the transmit (TX) data service.
+    **/
+    void IrqHandlerTx();
+    /**
+        Should be called by SERCOMx_1 Interrupt Vector.
+    **/
+    void IrqHandler1();
+    /**
+        \brief Should be called by SERCOMx_2 Interrupt Vector.
+
+        This is typically associated with RX data service.
+    **/
+    void IrqHandlerRx();
+    /**
+        \brief Should be called by SERCOMx_3 Interrupt Vector.
+
+        This is typically called on port exceptions.
+    **/
+    void IrqHandlerException();
+#endif
+
+protected:
+    // Current format
+    Parities m_parity;
+    uint8_t m_stopBits;
+    uint8_t m_charSize;
+    PortModes m_portMode;
+    SpiClockPolarities m_polarity;
+    SpiClockPhases m_phase;
+    CtrlLineModes m_ssMode;
+    CtrlLineModes m_rtsMode;
+    bool m_flowControl;
+
+    // SERCOM instance
+    Sercom *m_serPort;
+
+    // Pin information
+    const PeripheralRoute *m_ctsMisoInfo;
+    const PeripheralRoute *m_rtsSsInfo;
+    const PeripheralRoute *m_rxSckInfo;
+    const PeripheralRoute *m_txMosiInfo;
+
+    uint32_t m_baudRate;
+    uint8_t m_peripheral;
+    // Port open/close state
+    bool m_portOpen;
+    // Serial Break state
+    bool m_serialBreak;
+    // SERCOM DRE interrupt number
+    IRQn_Type m_dreIrqN;
+    // SPI dma channels
+    DmaChannels m_dmaRxChannel;
+    DmaChannels m_dmaTxChannel;
+
+    /**
+        Construct and wire this serial port into the PADs.
+    **/
+    SerialBase(const PeripheralRoute *ctsMisoInfo,
+               const PeripheralRoute *rtsSsInfo,
+               const PeripheralRoute *rxSckInfo,
+               const PeripheralRoute *txMosiInfo,
+               uint8_t peripheral);
+
+    /**
+        Default constructor so this connector can be a global and constructed
+        by SysManager
+    **/
+    SerialBase() {};
+
+    /**
+        Delay function to let the line state settle out.
+    **/
+    void WaitOneCharTime();
+
+    // =========================== INTERRUPT API ===============================
+    /**
+        Enable the Data Register Empty UART interrupt.
+    **/
+    void EnableDreInterruptUart();
+    /**
+        Disable the Data Register Empty UART interrupt.
+    **/
+    void DisableDreInterruptUart();
+    /**
+        Enable the Receive Complete UART interrupt.
+    **/
+    void EnableRxcInterruptUart();
+    /**
+        Disable the Receive Complete UART interrupt.
+    **/
+    void DisableRxcInterruptUart();
+
+private:
+    // Serial Buffers
+    int16_t m_bufferIn[SERIAL_BUFFER_SIZE];
+    int16_t m_bufferOut[SERIAL_BUFFER_SIZE];
+    // Indices for head and tails of the ring buffers
+
+    volatile uint32_t m_inHead, m_inTail;
+    volatile uint32_t m_outHead, m_outTail;
+
+    // Clear-on-read accumulating error register.
+    SerialErrorStatusRegister m_errorRegAccum;
+
+    /**
+        Enables and disables the SPI connector and waits for the enable
+        status to sync properly.
+    **/
+    void PortEnable(bool initializing = false);
+    void PortDisable();
+
+    /**
+        Helper function to get next index in a buffer.
+    **/
+    uint32_t NextIndex(uint32_t currentIndex) {
+        return ((currentIndex + 1) & (SERIAL_BUFFER_SIZE - 1));
+    }
+
+    /**
+        Receives characters from the DATA register and places them in the
+        receiving buffer.
+    **/
+    void RxProc();
+
+    /**
+        Transmit any data waiting in the transmit buffer.
+    **/
+    void TxPump();
+
+    /**
+        Helper function for setting RTS/SS pin modes
+    **/
+    bool RtsSsPinState(CtrlLineModes mode);
+};
+
+} // ClearCore namespace
+#endif // __SERIALBASE_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialDriver.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialDriver.h
new file mode 100644
index 000000000..d4774b3cc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialDriver.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SerialDriver.h
+    This class controls access to the Serial Port Connector.
+
+    It will allow you to set up:
+        - RS232 direct connections for ports that tolerate no negative voltages
+          by inverting the serial signals.
+        - TTL direct connections to USB bridge parts
+        - SPI transfers
+**/
+
+#ifndef __SERIALDRIVER_H__
+#define __SERIALDRIVER_H__
+
+#include <stdint.h>
+#include "Connector.h"
+#include "SerialBase.h"
+#include "ShiftRegister.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore Serial UART/SPI Connector class
+
+    This class controls access to the COM-0 and COM-1 connectors.
+
+    For more detailed information on each configurable mode, see the
+    \ref SerialDriverMain informational page.
+
+    For more detailed information on the ClearCore Connector interface in
+    general, check out the \ref ConnectorMain informational page.
+**/
+class SerialDriver : public SerialBase, public Connector {
+    friend class SysManager;
+    friend class CcioBoardManager;
+    friend class TestIO;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager.
+    **/
+    SerialDriver() {};
+#endif
+
+    /**
+        \brief Get the connector's operational mode.
+
+        \code{.cpp}
+        if (ConnectorCOM0.Mode() == Connector::TTL) {
+            // COM-0 is currently in TTL mode.
+        }
+        \endcode
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \code{.cpp}
+        // Set COM-1's mode to be the port controlling a CCIO-8 link
+        ConnectorCOM1.Mode(Connector::CCIO);
+        \endcode
+
+        \param[in] newMode The new mode to be set.
+        The valid modes for this connector type are:
+        - Connector#RS232
+        - Connector#SPI
+        - Connector#TTL
+        - Connector#CCIO
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    bool Mode(ConnectorModes newMode) override;
+
+    /**
+        \brief Get connector type.
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::SERIAL_TYPE;
+    };
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \return True if the port is open.
+    **/
+    bool IsWritable() override {
+        return PortIsOpen();
+    };
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Alias to ISerial::PortIsOpen().
+
+        \return True if the port is open, and false otherwise.
+    **/
+    int16_t State() override {
+        return PortIsOpen();
+    }
+
+    /**
+        \brief Alternative method to open or close the serial port.
+
+        \param[in] newState Zero to close the port, non-zero to open the port.
+
+        \return Success
+    **/
+    bool State(int16_t newState) override {
+        if (newState) {
+            PortOpen();
+        }
+        else {
+            PortClose();
+        }
+        return true;
+    }
+
+    bool IsInHwFault() override {
+        return false;
+    }
+#endif
+
+    /**
+        \brief Change the baud rate for the port.
+
+        \param[in] bitsPerSecond The new speed to set.
+        \return Returns true if port accepted the speed request. Will return
+        false if the baud rate gets clipped for SPI mode.
+    **/
+    bool Speed(uint32_t bitsPerSecond) override {
+        bool retVal = SerialBase::Speed(bitsPerSecond);
+        // Delay to allow the port polarity to be written to the shift
+        // register and settle for a full character time before sending data
+        if (m_portOpen) {
+            WaitOneCharTime();
+        }
+        return retVal;
+    }
+
+    /**
+        Set up the port to allow operations/communications.
+    **/
+    void PortOpen() override;
+
+    /**
+        Shut down the port and discontinue operations/communications.
+    **/
+    void PortClose() override;
+
+private:
+    // Index of this instance
+    uint8_t m_index;
+    // Feedback LED
+    ShiftRegister::Masks m_ledMask;
+    // Control bit in shift register
+    ShiftRegister::Masks m_controlMask;
+    // Inverter bit in shift register
+    ShiftRegister::Masks m_polarityMask;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Construct and wire in LED bit number
+    **/
+    SerialDriver(uint16_t index,
+                 ShiftRegister::Masks feedBackLedMask,
+                 ShiftRegister::Masks controlMask,
+                 ShiftRegister::Masks polarityMask,
+                 const PeripheralRoute *ctsMisoInfo,
+                 const PeripheralRoute *rtsSsInfo,
+                 const PeripheralRoute *rxSckInfo,
+                 const PeripheralRoute *txMosiInfo,
+                 uint8_t peripheral);
+#endif
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override;
+
+    /**
+        Update connector's state.
+    **/
+    void Refresh() override {};
+}; // SerialDriver
+
+} // ClearCore namespace
+
+#endif // __SERIALDRIVER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialUsb.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialUsb.h
new file mode 100644
index 000000000..2e51a98a1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SerialUsb.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SerialUsb.h
+    This class controls access to the USB Serial Port Connector.
+
+    Implements ISerial API to be interchangeable with SerialDriver connectors.
+**/
+
+#ifndef __SERIALUSB_H__
+#define __SERIALUSB_H__
+
+#include <inttypes.h>
+#include "Connector.h"
+#include "ISerial.h"
+
+/** Decimal (base 10). **/
+#ifdef DEC
+#undef DEC
+#endif
+#define DEC 10
+
+/** Hexadecimal (base 16). **/
+#ifdef HEX
+#undef HEX
+#endif
+#define HEX 16
+
+/** Octal (base 8). **/
+#ifdef OCT
+#undef OCT
+#endif
+#define OCT 8
+
+/** Binary (base 2). **/
+#ifdef BIN
+#undef BIN
+#endif
+#define BIN 2
+
+/** Serial USB timeout, in milliseconds (5000ms). **/
+#define USB_SERIAL_TIMEOUT 5000 // milliseconds
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore Serial USB Connector class
+
+    This class provides support for emulated serial communications on the
+    ClearCore's USB port.
+
+    For more detailed information on the ClearCore Connector interface, check
+    out the \ref ConnectorMain informational page.
+**/
+class SerialUsb : public ISerial, public Connector {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Default constructor so this connector can be a global and
+        constructed by SysManager
+    **/
+    SerialUsb() {};
+#endif
+
+    ///////////////////////////////// ISerial API //////////////////////////////
+
+    /**
+        \copydoc ISerial::Flush()
+
+        Blocks until data in the write buffer is sent.
+    **/
+    void Flush() override;
+
+    /**
+        \copydoc ISerial::FlushInput()
+    **/
+    void FlushInput() override;
+
+    /**
+        \copydoc ISerial::PortOpen()
+    **/
+    void PortOpen() override;
+
+    /**
+        \copydoc ISerial::PortClose()
+    **/
+    void PortClose() override;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \copydoc ISerial::Speed(uint32_t bitsPerSecond)
+    **/
+    bool Speed(uint32_t bitsPerSecond) override;
+
+    /**
+        \copydoc ISerial::Speed()
+    **/
+    uint32_t Speed() override;
+#endif
+
+    /**
+        \copydoc ISerial::CharGet()
+    **/
+    int16_t CharGet() override;
+
+    /**
+        \copydoc ISerial::CharPeek()
+    **/
+    int16_t CharPeek() override;
+
+    /**
+        \copydoc ISerial::SendChar(uint8_t charToSend)
+
+        \note No characters will be sent if DTR is not asserted.
+    **/
+    bool SendChar(uint8_t charToSend) override;
+
+    /**
+        \copydoc ISerial::AvailableForRead()
+    **/
+    int32_t AvailableForRead() override;
+
+    /**
+        \copydoc ISerial::AvailableForWrite()
+
+        Currently hard-coded to one packet size. While more data can be sent,
+        this is the maximum amount of data that will be buffered. Writing
+        anything larger will require the data pointer to remain valid during
+        the writing.
+
+    **/
+    int32_t AvailableForWrite() override;
+
+    /**
+        \copydoc ISerial::WaitForTransmitIdle()
+    **/
+    void WaitForTransmitIdle() override;
+
+    /**
+        \copydoc ISerial::PortIsOpen()
+    **/
+    bool PortIsOpen() override;
+
+    /**
+        \brief Set UART transmission parity format.
+
+        \return Returns true if port accepted the format change request.
+    **/
+    bool Parity(Parities newParity) override {
+        return newParity == Parities::PARITY_N;
+    }
+
+    /**
+        \brief Return current port UART transmission parity.
+
+        \return Returns transmission parity enumeration.
+    **/
+    Parities Parity() override {
+        return Parities::PARITY_N;
+    }
+
+    /**
+        \brief Change the number of stop bits used in UART communication.
+
+        For USB Serial ports, only 1 stop bit is supported.
+    **/
+    bool StopBits(uint8_t bits) override {
+        return bits == 1;
+    }
+
+    /**
+        \brief Change the number of bits in a character.
+
+        For USB Serial ports, only 8-bit characters are supported.
+    **/
+    bool CharSize(uint8_t size) override {
+        return size == 8;
+    }
+
+    ////////////////////////////// Connector API ///////////////////////////////
+
+    /**
+        \brief Get the connector's operational mode.
+        \note The only valid mode for this connector is #USB_CDC.
+
+        \return The connector's current operational mode.
+    **/
+    virtual ConnectorModes Mode() override {
+        return Connector::Mode();
+    }
+
+    /**
+        \brief Set the connector's operational mode.
+
+        \param[in] newMode The new mode to be set.
+        The only valid mode is #USB_CDC.
+        \return Returns false if the mode is invalid or setup fails.
+    **/
+    bool Mode(ConnectorModes newMode) override {
+        return (m_mode == newMode);
+    }
+
+    /**
+        \brief Get connector type.
+
+        \return The type of the current connector.
+    **/
+    Connector::ConnectorTypes Type() override {
+        return Connector::SERIAL_USB_TYPE;
+    }
+
+    /**
+        \brief Get R/W status of the connector.
+
+        \return True if the port is open.
+    **/
+    bool IsWritable() override {
+        return PortIsOpen();
+    }
+
+    /**
+        \brief Returns whether the serial port is open and the other end is
+        connected.
+
+        ClearCore uses the virtual serial port DTR flag to recognize that the
+        USB host is connected and listening. If DTR is not asserted, no
+        characters will be sent by the SerialUsb Send functions.
+
+         \code{.cpp}
+         ConnectorUsb.PortOpen();
+         while (!ConnectorUsb) {
+             continue;
+         }
+         ConnectorUsb.Send("USB Serial is now connected and host is listening.");
+         \endcode
+
+         \return Returns true if the port is open and DTR is asserted.
+    **/
+    operator bool() override;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Alias to ISerial::PortIsOpen().
+
+        \return True if the port is open, and false otherwise.
+    **/
+    int16_t State() override {
+        return PortIsOpen();
+    }
+
+    /**
+        \brief Alternative method to open or close the serial port.
+
+        \param[in] newState Zero to close the port, non-zero to open the port.
+
+        \return Success
+    **/
+    bool State(int16_t newState) override {
+        if (newState) {
+            PortOpen();
+        }
+        else {
+            PortClose();
+        }
+        return true;
+    }
+
+    bool IsInHwFault() override {
+        return false;
+    }
+#endif
+
+private:
+    // Index of this instance
+    uint16_t m_index;
+
+#ifndef HIDE_FROM_DOXYGEN
+    explicit SerialUsb(uint16_t index);
+
+    /**
+        Initialize hardware and/or internal state.
+    **/
+    void Initialize(ClearCorePins clearCorePin) override {
+        m_index = clearCorePin;
+        m_mode = USB_CDC;
+    }
+
+    /**
+        \brief Update connector's state.
+
+        \return Update the internal state.
+    **/
+    void Refresh() override {};
+#endif
+}; // SerialUsb
+
+} // ClearCore namespace
+
+#endif // __SERIALDRIVER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ShiftRegister.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ShiftRegister.h
new file mode 100644
index 000000000..a0d840d37
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/ShiftRegister.h
@@ -0,0 +1,606 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file ShiftRegister.h
+    \brief LED shift register access class
+
+    This class provides control and access to the LED shift register while not
+    in a connector context.
+**/
+
+#ifndef __SHIFTREGISTER_H__
+#define __SHIFTREGISTER_H__
+
+#include <stdint.h>
+#include "atomic_utils.h"
+#include "BlinkCodeDriver.h"
+
+namespace ClearCore {
+
+#ifndef HIDE_FROM_DOXYGEN
+/**
+    \class ShiftRegister
+    \brief LED control and connector configuration class
+
+    This class manages access to the LED/Configuration shift register so LEDs
+    and the shift register may be controlled directly.
+**/
+class ShiftRegister {
+    friend class AdcManager;
+    friend class DigitalInAnalogIn;
+    friend class DigitalInOutAnalogOut;
+    friend class DigitalIn;
+    friend class DigitalInOut;
+    friend class DigitalInOutHBridge;
+    friend class CcioBoardManager;
+    friend class LedDriver;
+    friend class MotorDriver;
+    friend class MotorManager;
+    friend class SerialDriver;
+    friend class StatusManager;
+    friend class SysManager;
+    friend class TestIO;
+
+public:
+
+    /**
+        \union ShiftChain
+        \brief Shift register access type.
+
+        Public Access Type to shift register items. The low level code takes
+        care of any inversions. True implies LED or feature enabled.
+    **/
+    union ShiftChain {
+        /**
+            Parallel view of the shift register.
+        **/
+        uint32_t reg;
+
+        /**
+            Bit-wise view of the shift register.
+        **/
+        struct _bit {
+            uint32_t A_CTRL_3 : 1;            // 0
+            uint32_t A_CTRL_2 : 1;            // 1
+            uint32_t LED_IO_5 : 1;            // 2
+            uint32_t LED_IO_4 : 1;            // 3
+            uint32_t LED_IO_3 : 1;            // 4
+            uint32_t LED_IO_2 : 1;            // 5
+            uint32_t LED_IO_1 : 1;            // 6
+            uint32_t LED_IO_0 : 1;            // 7
+            uint32_t EN_OUT_3 : 1;            // 8
+            uint32_t EN_OUT_2 : 1;            // 9
+            uint32_t EN_OUT_1 : 1;            // 10
+            uint32_t EN_OUT_0 : 1;            // 11
+            uint32_t UART_TTL_1 : 1;          // 12
+            uint32_t UART_TTL_0 : 1;          // 13
+            uint32_t UNDERGLOW : 1;           // 14
+            uint32_t LED_USB : 1;             // 15
+            uint32_t UART_SPI_SEL_1 : 1;      // 16
+            uint32_t UART_SPI_SEL_0 : 1;      // 17
+            uint32_t LED_COM_0 : 1;           // 18
+            uint32_t LED_COM_1 : 1;           // 19
+            uint32_t CFG00_AOUT : 1;          // 20
+            uint32_t LED_DI_6 : 1;            // 21
+            uint32_t LED_DI_7 : 1;            // 22
+            uint32_t LED_DI_8 : 1;            // 23
+            uint32_t LED_ADI_12 : 1;          // 24
+            uint32_t LED_ADI_11 : 1;          // 25
+            uint32_t LED_ADI_10 : 1;          // 26
+            uint32_t LED_ADI_09 : 1;          // 27
+            uint32_t ANAIN_DIGITAL_12 : 1;    // 28
+            uint32_t ANAIN_DIGITAL_11 : 1;    // 29
+            uint32_t ANAIN_DIGITAL_10 : 1;    // 30
+            uint32_t ANAIN_DIGITAL_09 : 1;    // 31
+        } bit;
+
+        // Construct
+        ShiftChain() {
+            reg = 0;
+        }
+
+        // Construct
+        ShiftChain(uint32_t val) {
+            reg = val;
+        }
+    }; // ShiftChain
+
+    /**
+        \enum Masks
+
+        \brief Location of shift register outputs as a bit mask.
+    **/
+    enum Masks {
+        SR_NO_FEEDBACK_MASK = 0,
+        SR_A_CTRL_3_MASK = 1U << 0,
+        SR_A_CTRL_2_MASK = 1U << 1,
+        SR_LED_IO_5_MASK = 1U << 2,
+        SR_LED_IO_4_MASK = 1U << 3,
+        SR_LED_IO_3_MASK = 1U << 4,
+        SR_LED_IO_2_MASK = 1U << 5,
+        SR_LED_IO_1_MASK = 1U << 6,
+        SR_LED_IO_0_MASK = 1U << 7,
+        SR_EN_OUT_3_MASK = 1U << 8,
+        SR_EN_OUT_2_MASK = 1U << 9,
+        SR_EN_OUT_1_MASK = 1U << 10,
+        SR_EN_OUT_0_MASK = 1U << 11,
+        SR_UART_TTL_1_MASK = 1U << 12,
+        SR_UART_TTL_0_MASK = 1U << 13,
+        SR_UNDERGLOW_MASK = 1U << 14,
+        SR_LED_USB_MASK = 1U << 15,
+        SR_UART_SPI_SEL_1_MASK = 1U << 16,
+        SR_UART_SPI_SEL_0_MASK = 1U << 17,
+        SR_LED_COM_0_MASK = 1U << 18,
+        SR_LED_COM_1_MASK = 1U << 19,
+        SR_CFG00_AOUT_MASK = 1U << 20,
+        SR_LED_DI_6_MASK = 1U << 21,
+        SR_LED_DI_7_MASK = 1U << 22,
+        SR_LED_DI_8_MASK = 1U << 23,
+        SR_LED_ADI_12_MASK = 1U << 24,
+        SR_LED_ADI_11_MASK = 1U << 25,
+        SR_LED_ADI_10_MASK = 1U << 26,
+        SR_LED_ADI_09_MASK = 1U << 27,
+        SR_ANAIN_DIGITAL_12_MASK = 1U << 28,
+        SR_ANAIN_DIGITAL_11_MASK = 1U << 29,
+        SR_ANAIN_DIGITAL_10_MASK = 1U << 30,
+        SR_ANAIN_DIGITAL_09_MASK = 1U << 31
+    };
+
+    /**
+        \enum LED_BLINK_CODE
+
+        \brief LED blink codes for use with errors or normal operations.
+        The enum should be ordered by increasing priority.
+    **/
+    enum LED_BLINK_CODE {
+        // LED Patterns
+        LED_BLINK_IO_SET = 0, // lowest priority
+        LED_BLINK_FADE,
+        LED_BLINK_BREATHING,
+        LED_BLINK_FAST_STROBE, // highest priority
+        // Max value for bounds checking
+        LED_BLINK_CODE_MAX,
+        LED_BLINK_PWM = LED_BLINK_FADE,
+        // Mapped Error Codes to Patterns
+        LED_BLINK_OVERLOAD = LED_BLINK_FAST_STROBE,
+        LED_BLINK_CCIO_COMM_ERR = LED_BLINK_FADE,
+        LED_BLINK_CCIO_ONLINE = LED_BLINK_BREATHING
+    };
+
+    /**
+        Construct and prepare shift register for initialization.
+    **/
+    ShiftRegister();
+
+private:
+    /**
+        Initializes the shift register and begins the timer tick.
+    **/
+    void Initialize();
+
+    /**
+        \return Returns true if any non-underglow output is overloaded.
+    **/
+    volatile const uint32_t &OverloadActive() {
+        return m_patternMasks[LED_BLINK_OVERLOAD];
+    }
+
+    /**
+        \return Return True if the shift register is ready for operations.
+    **/
+    volatile const bool &Ready() {
+        return m_initialized;
+    }
+
+    /**
+        \brief Public accessor to shift register state.
+
+        \return Current shift register state.
+    **/
+    ShiftChain ShifterState() {
+        return atomic_load_n(&m_patternOutputs[LED_BLINK_IO_SET]);
+    }
+
+    /**
+        \brief Public accessor to shift register state.
+
+        \return Current shift register state.
+    **/
+    bool ShifterState(Masks bitToGet) {
+        return atomic_load_n(&m_patternOutputs[LED_BLINK_IO_SET]) & bitToGet;
+    }
+
+    /**
+        \brief The last state written to the SPI data register.
+
+        \return The shift register state last written to the SPI data register.
+    **/
+    volatile const uint32_t &LastOutput() {
+        return m_lastOutput;
+    }
+
+    /**
+        \brief Atomic set/clear of shift register state fields.
+
+        \param[in] setFlds True to set fields, false to clear.
+        \param[in] fldsToChange Union of fields in the shift register to be set
+        or cleared.
+    **/
+    void ShifterState(bool setFlds, const ShiftChain &fldsToChange) {
+        setFlds ? ShifterStateSet(fldsToChange)
+        : ShifterStateClear(fldsToChange);
+    }
+
+    /**
+        \brief Atomic set/clear of shift register state fields.
+
+        \param[in] setFlds True to set fields, false to clear.
+        \param[in] bitsToChange LED bit in the shift register to be set
+        or cleared.
+    **/
+    void ShifterState(bool setFlds, Masks bitsToChange) {
+        setFlds ? ShifterStateSet(bitsToChange)
+        : ShifterStateClear(bitsToChange);
+    }
+
+    /**
+        \brief Atomic toggle of shift register state fields.
+
+        \param[in] fldsToToggle Union of fields in the shift register to
+                   be toggled.
+    **/
+    void ShifterStateToggle(ShiftChain fldsToToggle) {
+        atomic_xor_fetch(&m_patternOutputs[LED_BLINK_IO_SET], fldsToToggle.reg);
+    }
+
+    /**
+        \brief Replaces the shift register state fields with value.
+
+        \param[in] value What to set the shift register state to.
+    **/
+    void ShifterStateReplace(uint32_t value) {
+        atomic_exchange_n(&m_patternOutputs[LED_BLINK_IO_SET], value);
+    }
+    /**
+        \brief Set or clear an LED's active fault state display.
+
+        \param[in] ledMask A mask to indicate which LED should have a fault
+        state display set or cleared.
+        \param[in] state True if the fault state display should be set, false if
+        the fault state display should be cleared.
+    **/
+    void LedInFault(uint32_t ledMask, bool state) {
+        if (state) {
+            m_patternMasks[LED_BLINK_OVERLOAD] |= ledMask;
+        }
+        else {
+            m_patternMasks[LED_BLINK_OVERLOAD] &= ~ledMask;
+        }
+    }
+
+    /**
+        \brief Set or clear an LED's active PWM state display.
+
+        \param[in] ledMask A mask to indicate which LED should have a PWM state
+        display set or cleared.
+        \param[in] state True if the PWM state display should be set, false if
+        the PWM state display should be cleared.
+        \param[in] index Index into the analog value array
+    **/
+    void LedInPwm(Masks ledMask, bool state, uint8_t index) {
+        index &= 0xf;   // guard against index out of bounds
+        m_fadeCounter.m_analogMasks[index] = ledMask;
+        state ? m_fadeCounter.m_activeMask |= 1 << index
+                                              : m_fadeCounter.m_activeMask &= ~(1 << index);
+        LedPattern(ledMask, LED_BLINK_FADE, state);
+    }
+
+    /**
+        \brief Set an LED's PWM state value.
+
+        \param[in] value The duty cycle of the specified LED.
+        \param[in] index Index into the analog value array
+    **/
+    void LedPwmValue(uint8_t index, uint32_t value) {
+        index &= 0xf;   // guard against index out of bounds
+        m_fadeCounter.m_valuesBuf[index] = value;
+    }
+
+
+    /**
+        \brief Activates or deactivates the pattern on an LED.
+
+        \param[in] ledMask LED to affect.
+        \param[in] pattern Which pattern to set for the LED.
+        \param[in] state If true, set the pattern. If false, clear the pattern.
+    **/
+    void LedPattern(uint32_t ledMask, LED_BLINK_CODE pattern,
+                    bool state) {
+        state ? m_patternMasks[pattern] |= ledMask
+                                           : m_patternMasks[pattern] &= ~ledMask;
+    }
+
+    /**
+        Simple counter to mimic a TC. Instead of returning 0 or 1, it returns
+        0x00000000 or 0xffffffff. This allows easy ANDing of the results to
+        create a mask.
+
+        Update() does all of the magic, performing all logic, and returns the
+        high or low output.
+
+    **/
+    struct TickCounter {
+        uint32_t period;
+        uint32_t cc;
+
+    private:
+        uint32_t count;
+
+    public:
+        TickCounter()
+            : period(5000),
+              cc(2500),
+              count(0) {}
+
+        TickCounter(uint32_t period, uint32_t cc)
+            : period(period),
+              cc(cc),
+              count(0) {}
+
+        const uint32_t returnTable[2] = {0x00000000, 0xffffffff};
+
+        uint32_t Update() {
+            if (!count--) {
+                count = period;
+            }
+            return returnTable[count < cc];
+        }
+    };
+
+    /**
+        Counter that fades in. Works by modifying the duty cycle of a PWM
+        signal.
+
+        Period specifies how long the fade will last.
+    **/
+    class AnalogLedDriver {
+    public:
+        uint16_t m_activeMask;
+        uint32_t m_lastOutput;
+        uint8_t m_count;
+        uint8_t m_values[16];
+        uint8_t m_valuesBuf[16];
+        Masks m_analogMasks[16];
+
+        AnalogLedDriver()
+            : m_activeMask(0),
+              m_lastOutput(0),
+              m_count(UINT8_MAX - 1),
+              m_values{0},
+              m_valuesBuf{0},
+              m_analogMasks{SR_NO_FEEDBACK_MASK} {}
+
+        uint32_t Update() {
+            uint32_t retVal = m_lastOutput;
+            if (!m_activeMask) {
+                m_count = UINT8_MAX - 1;
+                return 0;
+            }
+
+            if (++m_count > UINT8_MAX >> 2) {
+                retVal = 0;
+                m_count = 0;
+                for (uint8_t i = 0; i < 16; i++) {
+                    if (m_activeMask & (1 << i) && m_valuesBuf[i]) {
+                        m_values[i] = m_valuesBuf[i];
+                        retVal |= m_analogMasks[i];
+                    }
+                }
+            }
+            else {
+                uint8_t compare = m_count << 2;
+                for (uint8_t i = 0; i < 16; i++) {
+                    if ((retVal & m_analogMasks[i]) &&
+                            (m_values[i] < compare)) {
+                        retVal &= ~m_analogMasks[i];
+                    }
+                }
+            }
+            return m_lastOutput = retVal;
+        }
+    };
+
+    /**
+        Counter that fades in and out. Works by modifying the duty cycle of a
+        PWM signal.
+
+        Periods specify how long the fades will last in their respective
+        directions.
+    **/
+    struct FadeInOutCounter {
+        uint8_t m_maxValue;
+        uint8_t m_minValue;
+
+    private:
+        uint8_t m_count;
+        uint8_t m_compare;
+        bool fadingIn;
+        const uint32_t returnTable[2] = {0x00000000, 0xffffffff};
+
+    public:
+        FadeInOutCounter(uint8_t maxValue = UINT8_MAX >> 1,
+                         uint8_t minValue = 0x08)
+            : m_maxValue(maxValue),
+              m_minValue(minValue),
+              m_count(0),
+              m_compare(0),
+              fadingIn(true) {}
+
+        uint32_t Update() {
+            if (++m_count >= UINT8_MAX >> 2) {
+                m_count = 0;
+                if (fadingIn) {
+                    if (++m_compare >= m_maxValue) {
+                        fadingIn = false;
+                    }
+                }
+                else {
+                    if (--m_compare <= m_minValue) {
+                        fadingIn = true;
+                    }
+                }
+            }
+            return returnTable[m_count << 2 < m_compare];
+        }
+    };
+
+    // the "close" LEDs
+    static const uint8_t LED_BANK_0_LEN = 6;
+    const Masks LED_BANK_0[LED_BANK_0_LEN] = {SR_LED_IO_0_MASK,
+                                              SR_LED_IO_1_MASK, SR_LED_IO_2_MASK, SR_LED_IO_3_MASK, SR_LED_IO_4_MASK,
+                                              SR_LED_IO_5_MASK
+                                             };
+
+    // the "far" LEDs
+    static const uint8_t LED_BANK_1_LEN = 7;
+    const Masks LED_BANK_1[LED_BANK_1_LEN] = {SR_LED_ADI_12_MASK,
+                                              SR_LED_ADI_11_MASK, SR_LED_ADI_10_MASK, SR_LED_ADI_09_MASK,
+                                              SR_LED_DI_8_MASK, SR_LED_DI_7_MASK, SR_LED_DI_6_MASK
+                                             };
+
+    // the "misc" LEDs
+    static const uint8_t LED_BANK_2_LEN = 4;
+    const Masks LED_BANK_2[LED_BANK_2_LEN] = {SR_UNDERGLOW_MASK,
+                                              SR_LED_USB_MASK, SR_LED_COM_0_MASK, SR_LED_COM_1_MASK
+                                             };
+
+    static const uint16_t DELAY_TIME = 25; // milliseconds
+
+    // A mask that prevents sketches from changing Shift Register values that
+    // aren't LEDs.
+    const uint32_t SAFE_LED_MASK = SR_LED_IO_0_MASK | SR_LED_IO_1_MASK |
+                                   SR_LED_IO_2_MASK | SR_LED_IO_3_MASK | SR_LED_IO_4_MASK |
+                                   SR_LED_IO_5_MASK | SR_LED_DI_6_MASK | SR_LED_DI_7_MASK |
+                                   SR_LED_DI_8_MASK | SR_LED_ADI_09_MASK | SR_LED_ADI_10_MASK |
+                                   SR_LED_ADI_11_MASK | SR_LED_ADI_12_MASK | SR_LED_USB_MASK;
+
+    /**
+        The below constants/data members are grouped for ease of use - the
+        constants directly affect the associated counters and their physical
+        output.
+    **/
+    const uint32_t FAST_COUNTER_PERIOD = 500;
+    const uint32_t FAST_COUNTER_CC = 200;
+    TickCounter m_fastCounter;
+    FadeInOutCounter m_breathingCounter;
+    AnalogLedDriver m_fadeCounter;
+    /** -------------------- END OF GROUPED SECTION-----------------------**/
+
+    // Inversion mask of actual shift register state
+    ShiftChain m_shiftInversions;
+
+    uint32_t m_patternMasks[LED_BLINK_CODE_MAX];
+    uint32_t m_patternOutputs[LED_BLINK_CODE_MAX];
+    uint32_t m_altOutput;
+
+    // Set after initialization
+    bool m_initialized;
+    bool m_blinkCodeActive;
+    bool m_blinkCodeState;
+    bool m_useAltOutput;
+
+    // The values about to be written to the SPI data register.
+    uint32_t m_pendingOutput;
+    // The last values written to the SPI data register.
+    uint32_t m_lastOutput;
+    // The last values read from the SPI data register.
+    uint32_t m_latchedOutput;
+
+    /**
+        Update the shift chain and strobe.
+    **/
+    void Send();
+
+    /**
+        Update from timer tick.
+    **/
+    void Update();
+
+    /**
+        \brief Atomic set of shift register state fields.
+
+        \param[in] fldsToSet Union of fields in the shift register to be set.
+    **/
+    void ShifterStateSet(ShiftChain fldsToSet) {
+        atomic_or_fetch(&m_patternOutputs[LED_BLINK_IO_SET], fldsToSet.reg);
+    }
+
+    /**
+        \brief Atomic set of shift register state fields.
+
+        \param[in] bitsToSet LED bit in the shift register to be set.
+    **/
+    void ShifterStateSet(Masks bitsToSet) {
+        atomic_or_fetch(&m_patternOutputs[LED_BLINK_IO_SET], bitsToSet);
+    }
+
+    /**
+        \brief Atomic clear of shift register state fields.
+
+        \param[in] fldsToClr Union of fields in the shift register to be
+    cleared.
+    **/
+    void ShifterStateClear(ShiftChain fldsToClr) {
+        atomic_and_fetch(&m_patternOutputs[LED_BLINK_IO_SET], ~fldsToClr.reg);
+    }
+
+    /**
+        \brief Atomic clear of shift register state fields.
+
+        \param[in] bitsToClr LED bit in the shift register to be cleared.
+    **/
+    void ShifterStateClear(Masks bitsToClr) {
+        atomic_and_fetch(&m_patternOutputs[LED_BLINK_IO_SET], ~bitsToClr);
+    }
+
+    /**
+        \brief Turn all of the ClearCore's LEDs on. The user should be able to
+        easily tell if there are any that don't work anymore.
+
+        This function will block until the sequence is complete. It takes about
+        a second to complete, and will turn the LEDs back off, except for the
+        underglow.
+    **/
+    void DiagnosticLedSweep();
+
+    void BlinkCode(bool blinkCodeActive, bool blinkCodeState) {
+        m_blinkCodeActive = blinkCodeActive;
+        m_blinkCodeState = blinkCodeState;
+    }
+
+}; // ShiftRegister
+#endif
+
+} // ClearCore namespace
+
+#endif // __SHIFTREGISTER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/StatusManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/StatusManager.h
new file mode 100644
index 000000000..e9ef35e08
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/StatusManager.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __STATUSMANAGER_H__
+#define __STATUSMANAGER_H__
+
+#include "ShiftRegister.h"
+#include "BlinkCodeDriver.h"
+#include "SysConnectors.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore Status Register Manager class
+
+    This class manages access to ClearCore status information.
+**/
+class StatusManager {
+    friend class CcioBoardManager;
+    friend class DigitalInOut;
+
+public:
+    /**
+        \union StatusRegister
+
+        The ClearCore status register.
+    **/
+    union StatusRegister {
+        /**
+            Broad access to the whole register
+        **/
+        uint32_t reg;
+
+        /**
+            Field access to the status register
+        **/
+        struct {
+            /**
+                Supply voltage has exceeded 29V, outside of the range of
+                normal operating conditions (nominally 24 V).
+            **/
+            uint32_t VSupplyOverVoltage    : 1;
+            /**
+                Supply voltage has gone below 10V, outside of the range of
+                normal operating conditions (nominally 24V).
+            **/
+            uint32_t VSupplyUnderVoltage   : 1;
+            /**
+                The H-Bridge chip on connectors IO-4 and IO-5 has experienced
+                an overload condition.
+            **/
+            uint32_t HBridgeOverloaded     : 1;
+            /**
+                The H-Bridge chip on connectors IO-4 and IO-5 is currently
+                undergoing a hardware reset.
+            **/
+            uint32_t HBridgeReset          : 1;
+            /**
+                The 5V off-board supply has gone below 4V, outside of the range
+                of normal operating conditions (nominally 5V).
+            **/
+            uint32_t Overloaded5V          : 1;
+            /**
+                An output is currently overloaded on the ClearCore board
+                (driven TRUE but being pulled FALSE).
+            **/
+            uint32_t OutputOverloaded      : 1;
+            /**
+                An output is currently overloaded on an attached CCIO-8 board
+                (driven TRUE but being pulled FALSE).
+            **/
+            uint32_t CcioOverloaded        : 1;
+            /**
+                An established CCIO-8 link has gone offline.
+            **/
+            uint32_t CcioLinkBroken        : 1;
+            /**
+                A conversion in the analog-to-digital converter has timed out.
+            **/
+            uint32_t AdcTimeout            : 1;
+            /**
+                The Ethernet cable is unplugged.
+            **/
+            uint32_t EthernetDisconnect    : 1;
+            /**
+                A remote Ethernet error has occurred.
+            **/
+            uint32_t EthernetRemoteFault   : 1;
+            /**
+                Ethernet initialization was attempted but failed.
+            **/
+            uint32_t EthernetPhyInitFailed : 1;
+            /**
+                The SD card is currently in a hardware fault state.
+            **/
+            uint32_t SdCardError           : 1;
+            /**
+                The last NVM write has not yet synchronized or was unable to
+                synchronize.
+            **/
+            uint32_t NvmDesync      : 1;
+        } bit;
+
+        /**
+            Status Register default constructor
+        **/
+        StatusRegister() {
+            reg = 0;
+        }
+
+        /**
+            Status Register constructor with initial value
+        **/
+        StatusRegister(uint32_t val) {
+            reg = val;
+        }
+
+        /**
+            Interpret the StatusRegister as a boolean by reporting whether any
+            bits are set.
+        **/
+        operator bool() const {
+            return reg > 0;
+        }
+    };
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for singleton instance
+    **/
+    static StatusManager &Instance();
+#endif
+
+    /**
+        \brief The real time status register.
+
+        The bits that are asserted in the status register that's returned
+        indicate events that are occurring now.
+
+        \note This register shows a real-time view of the ClearCore's status.
+        Some of the status bits contained within are of a transient nature and
+        will not persist for multiple samples. This means that your polling of
+        this register may miss certain status events. To catch these events poll
+        the StatusRisen and StatusFallen registers.
+
+        \code{.cpp}
+        // Save the current ADC timeout status as a bool.
+        bool adcTimedOut = StatusMgr.StatusRT().bit.AdcTimeout;
+        if (adcTimedOut) {
+            // The ADC has timed out.
+        }
+        \endcode
+
+        \param [in] mask (optional) A StatusRegister whose asserted bits
+        indicate which of the ClearCore status bits to check for an asserted
+        state. If one of the \a bit members of this mask are deasserted, that
+        bit will be ignored when checking for asserted status bits. If no
+        \a mask is provided, it's equivalent to passing a StatusRegister with
+        all bits asserted, in which case this function would report any status
+        bits that are currently asserted.
+
+        \return StatusRegister whose asserted bits indicate currently active
+        ClearCore status events.
+    **/
+    StatusRegister StatusRT(StatusRegister mask = UINT32_MAX);
+
+    /**
+        \brief Clear on read accessor for status bits that have risen
+        (transitioned from deasserted to asserted) sometime since the previous
+        invocation of this function.
+
+        \code{.cpp}
+        // Check if any power supply problems have occurred since the last call
+        StatusManager::StatusRegister mask;
+        mask.bit.VSupplyOverVoltage = 1;
+        mask.bit.VSupplyUnderVoltage = 1;
+        StatusManager::StatusRegister risen = StatusMgr.StatusRisen(mask);
+        if (risen.reg) {
+            // Power supply problems have occurred since last call.
+        }
+        \endcode
+
+        \param [in] mask (optional) A StatusRegister whose asserted bits
+        indicate which of the ClearCore status bits to check for rising edges.
+        If one of the \a bit members of this mask are deasserted, that bit will
+        be ignored when checking for rising edges. If no \a mask is provided,
+        it's equivalent to passing a StatusRegister with all bits asserted, in
+        which case this function would report rising edges on any of the status
+        bits.
+
+        \return StatusRegister whose asserted bits indicate which ClearCore
+        status bits have risen since the last poll.
+    **/
+    StatusRegister StatusRisen(StatusRegister mask = UINT32_MAX);
+
+    /**
+        \brief Clear on read accessor for status bits that have fallen
+        (transitioned from asserted to deasserted) sometime since the previous
+        invocation of this function.
+
+        \code{.cpp}
+        // Check if any power supply problems have gone away since the last call
+        StatusManager::StatusRegister mask;
+        mask.bit.VSupplyOverVoltage = 1;
+        mask.bit.VSupplyUnderVoltage = 1;
+        StatusManager::StatusRegister fallen = StatusMgr.StatusFallen(mask);
+        if (fallen.reg) {
+            // Power supply problems have gone away since last call
+        }
+        \endcode
+
+        \param [in] mask (optional) A StatusRegister whose asserted bits
+        indicate which of the ClearCore status bits to check for falling edges.
+        If one of the \a bit members of this mask are deasserted, that bit will
+        be ignored when checking for falling edges. If no \a mask is provided,
+        it's equivalent to passing a StatusRegister with all bits asserted, in
+        which case this function would report falling edges on any of the status
+        bits.
+
+        \return StatusRegister whose asserted bits indicate which ClearCore
+        status bits have fallen since the last poll.
+    **/
+    StatusRegister StatusFallen(StatusRegister mask = UINT32_MAX);
+
+    /**
+        \brief Accumulating Clear on read accessor for any status bits that were
+        asserted sometime since the previous invocation of this function.
+
+        \note This is similar to #StatusRisen() except that it tracks asserted
+        status bits rather than status bits that have transitioned from
+        deasserted to asserted.
+        Therefore in the case that the supply voltage has been low since
+        startup, i.e. its status bit has been set since startup, calling this
+        function repeatedly will show that bit asserted each time, while calling
+        #StatusRisen() repeatedly will only show the bit asserted on the first
+        call, since it transitioned from deasserted to asserted only once at
+        startup.
+
+        \code{.cpp}
+        // See if any CCIO-8 link errors have occurred since the last call
+        bool ccioConnectionProb = StatusMgr.StatusAccum().bit.CcioLinkBroken;
+        if (ccioConnectionProb) {
+            // The CCIO-8 link is broken; do something about it here.
+        }
+        \endcode
+
+        \param [in] mask (optional) A StatusRegister whose asserted bits
+        indicate which of the ClearCore status bits to check for an asserted
+        state. If one of the \a bit members of this mask are deasserted, that
+        bit will be ignored when checking for asserted status bits. If no
+        \a mask is provided, it's equivalent to passing a StatusRegister with
+        all bits asserted, in which case this function would report any
+        accumulated asserted status bits.
+
+        \return StatusRegister whose asserted bits indicate which ClearCore
+        status bits have been asserted since the last poll.
+    **/
+    StatusRegister StatusAccum(StatusRegister mask = UINT32_MAX);
+
+    /**
+        \brief Access to all accumulated status bits that have asserted since
+        board startup (or since the last board reset).
+
+        \note This is not a clear on read operation, so reading this register
+        does not automatically clear out the bits that have been raised,
+        unlike #StatusRisen() and #StatusFallen().
+
+        \code{.cpp}
+        // See if any CCIO-8 link errors have occurred since startup.
+        bool ccioConnectionProb =
+            StatusMgr.SinceStartupAccum().bit.CcioLinkBroken;
+        if (ccioConnectionProb) {
+            // The CCIO-8 link is broken; do something about it here.
+        }
+        \endcode
+
+        \param [in] mask (optional) A StatusRegister whose asserted bits
+        indicate which of the ClearCore status bits to check for an asserted
+        state. If one of the \a bit members of this mask are deasserted, that
+        bit will be ignored when checking for asserted status bits. If no
+        \a mask is provided, it's equivalent to passing a StatusRegister with
+        all bits asserted, in which case this function would report any
+        accumulated asserted status bits.
+
+        \return StatusRegister whose asserted bits indicate which ClearCore
+        status bits have risen since startup.
+    **/
+    StatusRegister SinceStartupAccum(StatusRegister mask = UINT32_MAX);
+
+    /**
+        Deactivate a blink code.
+
+        Clear out a currently active blink code. This is useful for when an
+        error can be fixed on the fly, while the board is still operating,
+        to avoid being continually alerted to the error even after it was
+        resolved.
+
+        \param[in] group The group number the blink code belongs to.
+        \param[in] code The blink code number to clear.
+
+        \code{.cpp}
+        // Check for an historical overload on connector IO-0.
+        if (StatusMgr.IoOverloadAccum().bit.CLEARCORE_PIN_IO0) {
+            // Clear out the reporting of the overload (blink code 1-1)
+            StatusMgr.BlinkCodeClear(1, 1);
+        }
+        \endcode
+
+        See \ref BlinkCodes for group and code numbers.
+    **/
+    void BlinkCodeClear(uint8_t group, uint8_t code) {
+        m_blinkMgr.BlinkCodeClear(group, code);
+    }
+
+    /**
+        \brief Starts a reset pulse to the DigitalInOutHBridge connectors.
+
+        Resetting the HBridge will temporarily disable the DigitalInOutHBridge
+        and MotorDriver connectors.
+
+        \code{.cpp}
+        // Reset the HBridge connectors.
+        StatusMgr.HBridgeReset();
+        \endcode
+
+        \note Any active step and direction moves on the MotorDriver
+        connectors will be terminated.
+    **/
+    void HBridgeReset();
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Initializes the StatusManager.
+    **/
+    bool Initialize(ShiftRegister::Masks faultLed);
+
+    /**
+        Refreshes the StatusManager.
+    **/
+    void Refresh();
+
+    /**
+        \brief Helper to set the state of the DigitalInOutHBridge connectors
+        during reset.
+    **/
+    void HBridgeState(bool reset);
+#endif
+
+    /**
+        \brief Read accessor for whether the ADC has timed out while attempting
+        a conversion.
+
+        \code{.cpp}
+        if (StatusMgr.AdcIsInTimeout()) {
+            // ADC has timed out.
+        }
+        \endcode
+
+        \return True if the ADC is currently timed out, false otherwise.
+    **/
+    bool AdcIsInTimeout();
+
+    /**
+        \brief Accessor for the real time overload status of the I/O connectors.
+
+        \code{.cpp}
+        if (StatusMgr.IoOverloadRT().bit.CLEARCORE_PIN_IO3) {
+            // IO-3 is currently overloaded.
+        }
+        \endcode
+
+        \param [in] mask (optional) A SysConnectorState whose asserted bits
+        indicate which of the ClearCore connector overload status bits to
+        check for an asserted state. If one of the \a bit members of this mask
+        are deasserted, that bit will be ignored when checking for connector
+        overloads. If no \a mask is provided, it's equivalent to passing a
+        SysConnectorState with all bits asserted, in which case this function
+        would report any connectors currently in an overloaded state.
+
+        \return SysConnectorState register whose asserted bits indicate which
+        connectors are currently overloaded.
+    **/
+    SysConnectorState IoOverloadRT(SysConnectorState mask = UINT32_MAX);
+
+    /**
+        \brief Clear on read accessor for connector overload status since the
+        last invocation of this function.
+
+        \code{.cpp}
+        if (StatusMgr.IoOverloadAccum().reg) {
+            // There has been a connector overload since the last call to
+            // IoOverloadAccum().
+        }
+        \endcode
+
+        \param [in] mask (optional) A SysConnectorState whose asserted bits
+        indicate which of the ClearCore connector overload status bits to check
+        for an asserted state. If one of the \a bit members of this mask are
+        deasserted, that bit will be ignored when checking for connector
+        overloads. If no \a mask is provided, it's equivalent to passing a
+        SysConnectorState with all bits asserted, in which case this function
+        would report any connectors in an overload state since the last
+        invocation of this function.
+
+        \return SysConnectorState register whose asserted bits indicate which
+        connectors have been overloaded since the last poll.
+    **/
+    SysConnectorState IoOverloadAccum(SysConnectorState mask = UINT32_MAX);
+
+    /**
+        \brief Accessor for connector overload status since startup (or board
+        reset).
+
+        \code{.cpp}
+        if (StatusMgr.IoOverloadSinceStartupAccum().bit.CLEARCORE_PIN_IO3) {
+            // Connector IO-3 has overloaded since startup.
+        }
+        \endcode
+
+        \code{.cpp}
+        if (StatusMgr.IoOverloadSinceStartupAccum().bit.CLEARCORE_PIN_IO2) {
+            // Connector IO-2 was overloaded since startup.
+        }
+        \endcode
+
+        \param [in] mask (optional) A SysConnectorState whose asserted bits
+        indicate which of the ClearCore connector overload status bits to check
+        for an asserted state. If one of the \a bit members of this mask are
+        deasserted, that bit will be ignored when checking for connector
+        overloads. If no \a mask is provided, it's equivalent to passing a
+        SysConnectorState with all bits asserted, in which case this function
+        would report any connectors that have been in an overload state since
+        board startup.
+
+        \return SysConnectorState register whose asserted bits indicate which
+        connectors have been overloaded since startup.
+    **/
+    SysConnectorState IoOverloadSinceStartupAccum(SysConnectorState mask =
+                UINT32_MAX);
+
+    /**
+        Activate an application driven blink code.
+
+        This function allows the application code to display a blink code
+        in the #BLINK_GROUP_APPLICATION code group.
+
+        \code{.cpp}
+        // If an error code is present, display the corresponding blink code.
+        uint8_t errorCode = 3;
+        if (errorCode) {
+            StatusMgr.UserBlinkCode(1 << (errorCode-1));
+        }
+        \endcode
+
+        \param[in] mask A mask representing an aggregate of blink codes to
+        display.
+    **/
+    void UserBlinkCode(uint8_t mask) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_APPLICATION, mask);
+    }
+
+private:
+    StatusRegister m_statusRegSinceStartup;
+    StatusRegister m_statusRegRT;
+    StatusRegister m_statusRegAccum;
+    StatusRegister m_statusRegRisen;
+    StatusRegister m_statusRegFallen;
+
+    SysConnectorState m_overloadSinceStartup;
+    SysConnectorState m_overloadAccum;
+    SysConnectorState m_overloadRT;
+
+    ShiftRegister::Masks m_faultLed;
+    BlinkCodeDriver m_blinkMgr;
+
+    bool m_disableMotors;
+    volatile bool m_hbridgeResetting;
+
+    StatusManager()
+        : m_statusRegSinceStartup(),
+          m_statusRegRT(),
+          m_statusRegAccum(),
+          m_statusRegRisen(),
+          m_statusRegFallen(),
+          m_faultLed(ShiftRegister::SR_NO_FEEDBACK_MASK),
+          m_disableMotors(false),
+          m_hbridgeResetting(false) {}
+
+    /**
+        Activate a blink code.
+
+        \param[in] group The group the blink code belongs to.
+        See BlinkCodeDriver#BlinkCodeGroups.
+        \param[in] mask A mask representing an aggregate of blink codes to
+        display. See BlinkCodeDriver#SupplyErrorCodes,
+        BlinkCodeDriver#DeviceErrors, and BlinkCodeDriver#CcioOverload.
+    **/
+    void BlinkCode(BlinkCodeDriver::BlinkCodeGroups group, uint8_t mask);
+
+    /**
+        Update the board's blink codes with the supplied status
+        information.
+
+        \param[in] status A status register with error status information
+        to determine which blink codes to display.
+    **/
+    void UpdateBlinkCodes(StatusRegister status);
+
+    /**
+        Set or clear a connector's overload state.
+    **/
+    void OverloadUpdate(uint32_t mask, bool inFault);
+
+}; // StatusManager
+
+} // ClearCore namespace
+#endif // __STATUSMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/StepGenerator.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/StepGenerator.h
new file mode 100644
index 000000000..bc0c07636
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/StepGenerator.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file
+    ClearCore Step & Direction motion profile generator
+
+    A StepGenerator is activated by creating an instance of the StepGenerator
+    class. There can be several instances of StepGenerator, however, each must
+    be attached to different connectors.
+**/
+
+#ifndef __STEPGENERATOR_H__
+#define __STEPGENERATOR_H__
+
+#include <stdint.h>
+
+namespace ClearCore {
+
+/** All of the motor position, velocity, and acceleration parameters are signed
+    and in Q format, with all arithmetic performed in fixed point.
+    This defines the Q value - the number of bits that are treated as
+    fractional values (15). **/
+#define FRACT_BITS 15
+
+/**
+    \class StepGenerator
+    \brief ClearCore Step and Direction generator class
+
+    This class manages the generation and communication of movement profiles for
+    the MotorDriver connectors.
+
+    For more detailed information on the ClearCore Motor Control and Motion
+    Generation systems, check out the \ref MotorDriverMain and \ref MoveGen
+    informational pages.
+**/
+class StepGenerator {
+    friend class MotorManager;
+    friend class TestIO;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    StepGenerator();
+#endif
+
+    typedef enum {
+        MOVE_TARGET_ABSOLUTE,
+        MOVE_TARGET_REL_END_POSN,
+    } MoveTarget;
+
+    /**
+        \brief Issues a positional move for the specified distance.
+
+        \note When making absolute moves, ClearCore tracks the current position
+        based on the zero position at program-start. If there is a move in
+        progress when a new move is issued, the target position will be adjusted
+        according to the \a moveTarget parameter, the new acceleration and velocity
+        limits will be applied, and the new move is merged seamlessly with the
+        previous motion. If you want to make sure that the previous move fully
+        completes without being merged with a new command, wait for
+        #StepsComplete() to return true.
+
+        \code{.cpp}
+        // Interrupt any on-going move and move to the absolute position 5000
+        ConnectorM0.Move(5000, StepGenerator::MOVE_TARGET_ABSOLUTE);
+        \endcode
+
+        \param[in] dist The distance of the move in step pulses
+        \param[in] moveTarget (optional) Specify the type of movement that
+        should be done. Absolute or relative to the end position of the current
+        move. Invalid will result in move relative to the end position.
+        Default: MOVE_TARGET_REL_END_POSN
+
+        \note For use with Step and Direction mode.
+    **/
+    virtual bool Move(int32_t dist,
+                      MoveTarget moveTarget = MOVE_TARGET_REL_END_POSN);
+
+    /**
+        \brief Issues a velocity move at the specified velocity.
+
+        \code{.cpp}
+        // Perform a velocity move
+        ConnectorM0.MoveVelocity(500);
+        \endcode
+
+        \note Any existing move will be immediately overwritten with the new
+        velocity.
+
+        \param[in] velocity The velocity of the move in step pulses/second.
+
+        \note For use with Step and Direction mode.
+    **/
+    virtual bool MoveVelocity(int32_t velocity);
+
+    /**
+        Interrupts the current move; the motor may stop abruptly.
+
+        \code{.cpp}
+        // Command an abrupt stop
+        ConnectorM0.MoveStopAbrupt();
+        \endcode
+
+        \note For use with Step and Direction mode.
+    **/
+    void MoveStopAbrupt();
+
+    /**
+        Interrupts any current move and commands the motor to stop. The stopping
+        acceleration used will be the higher of either
+        - 1) the move's current acceleration rate, or
+        - 2) the value of #EStopDecelMax.
+
+        This function's \a decelMax parameter can be used to update the
+        #EStopDecelMax value used for stopping.
+
+        \code{.cpp}
+        // Ramp to a stop at a decel rate of 100000 pulses/sec^2
+        ConnectorM0.MoveStopDecel(100000);
+        \endcode
+
+        \param[in] decelMax The new EStop deceleration rate to set instead 
+        of the value that was set prior to issuing the move. Passing 0 
+        maintains the EStopDecelMax that was previously set.
+
+        \note For use with Step and Direction mode.
+    **/
+    void MoveStopDecel(uint32_t decelMax = 0);
+
+    /**
+        \brief Sets the absolute commanded position to the given value.
+
+        \code{.cpp}
+        // Set the StepGenerator's position reference to -5000
+        ConnectorM0.PositionRefSet(-5000);
+        \endcode
+
+        \param[in] posn The new position to be set.
+
+        \note For use with Step and Direction mode.
+    **/
+    void PositionRefSet(int32_t posn) {
+        m_posnAbsolute = posn;
+    }
+
+    /**
+        \brief Accessor for the StepGenerator's position reference
+
+        \code{.cpp}
+        if (ConnectorM0.PositionRefCommanded() > 5000) {
+            // M-0's position reference is above 5000
+        }
+        \endcode
+
+        \return Returns the absolute commanded position.
+
+        \note For use with Step and Direction mode.
+    **/
+    volatile const int32_t &PositionRefCommanded() {
+        return m_posnAbsolute;
+    }
+
+    /**
+        \brief Accessor for the StepGenerator's momentary velocity
+
+        \code{.cpp}
+        if (ConnectorM0.VelocityRefCommanded() > 1000) {
+            // M-0's current velocity is above 1000
+        }
+        \endcode
+
+        \return Returns the momentary commanded velocity.
+
+        \note For use with Step and Direction mode.
+    **/
+    int32_t VelocityRefCommanded();
+
+    /**
+        \brief Sets the maximum velocity for position moves, in step pulses per
+        second.
+
+        \code{.cpp}
+        // Set the StepGenerator's maximum velocity to 1200 step pulses/sec
+        ConnectorM0.VelMax(1200);
+        \endcode
+
+        \param[in] velMax The new velocity limit
+
+        \note For use with Step and Direction mode.
+    **/
+    void VelMax(uint32_t velMax);
+
+    /**
+        \brief Sets the maximum acceleration in step pulses per second^2.
+
+        Value will be clipped if out of bounds
+
+        \code{.cpp}
+        // Set the StepGenerator's maximum velocity to 15000 step pulses/sec^2
+        ConnectorM0.AccelMax(15000);
+        \endcode
+
+        \param[in] accelMax The new acceleration limit
+
+        \note For use with Step and Direction mode.
+    **/
+    void AccelMax(uint32_t accelMax);
+
+
+    /**
+        \brief Sets the maximum deceleration for E-stop Deceleration in
+        step pulses per second^2. This is only for MoveStopDecel.
+
+        Value will be clipped if out of bounds
+
+        \code{.cpp}
+        // Set the StepGenerator's maximum E-stop deceleration to 15000 step pulses/sec^2
+        ConnectorM0.EStopDecelMax(15000);
+        \endcode
+
+        \param[in] decelMax The new e-stop deceleration limit
+
+        \note For use with Step and Direction mode.
+    **/
+    void EStopDecelMax(uint32_t decelMax);
+
+    /**
+        \brief Function to check if no steps are currently being commanded to
+        the motor.
+
+        \code{.cpp}
+        if (ConnectorM0.StepsComplete()) {
+            // No more steps are being commanded
+        }
+        \endcode
+
+        \return Returns true if there is no valid current command.
+        \note The motor may still be moving after steps are done being sent.
+
+        \note For use with Step and Direction mode.
+    **/
+    bool StepsComplete() {
+        return MoveStateGet() == MS_IDLE;
+    }
+
+    /**
+        \brief Function to check if the commanded move is at the cruising
+        velocity - Acceleration portion of movement has finished.
+
+        \code{.cpp}
+        if (ConnectorM0.CruiseVelocityReached) {
+            // The commanded move is at the cruising velocity
+        }
+        \endcode
+
+        \return Returns true if there the move is in the cruise state
+        \note The motor will still need to decelerate after cruising
+
+        \note For use with Step and Direction mode.
+    **/
+    bool CruiseVelocityReached() {
+        return MoveStateGet() == MS_CRUISE;
+    }
+
+protected:
+    struct LimitStatus {
+        uint32_t LimitRampPos       : 1;    // True if we are ramping into the positive limit
+        uint32_t LimitRampNeg       : 1;    // True if we are ramping into the negative limit
+        uint32_t EnterHWLimit       : 1;    // True when entering HW limits
+        uint32_t InPosHWLimit       : 1;    // True if we are in the positive HW limit
+        uint32_t InNegHWLimit       : 1;    // True if we are in the negative HW limit
+        uint32_t InPosHWLimitLast   : 1;
+        uint32_t InNegHWLimitLast   : 1;
+
+        public:
+        LimitStatus()
+            : LimitRampPos(0),
+              LimitRampNeg(0),
+              EnterHWLimit(0),
+              InPosHWLimit(0),
+              InNegHWLimit(0),
+              InPosHWLimitLast(0),
+              InNegHWLimitLast(0) {}
+    };
+
+    typedef enum {
+        MS_IDLE,
+        MS_START,
+        MS_ACCEL,
+        MS_CRUISE,
+        MS_DECEL,
+        MS_DECEL_VEL,
+        MS_END,
+        MS_CHANGE_DIR,
+    } MoveStates;
+
+    uint32_t m_stepsPrevious;
+    uint32_t m_stepsPerSampleMax;
+    MoveStates m_moveState;
+    bool m_direction;
+    // True if the last move commanded was a positional move (latched)
+    bool m_lastMoveWasPositional;
+
+    LimitStatus m_limitInfo;
+
+    int32_t m_posnAbsolute;
+
+    volatile const bool &Direction() {
+        return m_direction;
+    }
+
+    volatile const MoveStates &MoveStateGet() {
+        return m_moveState;
+    }
+
+    void StepsCalculated();
+
+    uint32_t StepsPrevious() {
+        return m_stepsPrevious;
+    }
+
+    bool CheckTravelLimits();
+
+    void PosLimitActive(bool isActive) {
+        m_limitInfo.InPosHWLimit = isActive;
+    }
+
+    void NegLimitActive(bool isActive) {
+        m_limitInfo.InNegHWLimit = isActive;
+    }
+
+private:
+
+    int32_t m_stepsCommanded;
+    int32_t m_stepsSent;      // Accumulated integer position
+
+    bool m_velocityMove;      // A Velocity move is active
+    bool m_moveDirChange;     // The move is changing direction
+    bool m_dirCommanded;      // The direction of the commanded move
+
+
+    // All of the position, velocity and acceleration parameters are signed and
+    // in Q format, with all arithmetic performed in fixed point.
+    // FRACT_BITS defines the Q value - the number of bits that are treated as
+    // fractional values.
+
+    int32_t m_velLimitQx;     // Velocity limit
+    int32_t m_altVelLimitQx;  // Velocity move Velocity limit
+    int32_t m_accelLimitQx;   // Acceleration limit
+    int32_t m_altDecelLimitQx;// E-Stop Deceleration limit
+    int64_t m_posnCurrentQx;  // Current position
+    int32_t m_velCurrentQx;   // Current velocity
+    int32_t m_accelCurrentQx; // Current acceleration
+    int64_t m_posnTargetQx;   // Move length
+    int32_t m_velTargetQx;    // Adjusted velocity limit
+    int64_t m_posnDecelQx;    // Position to start decelerating
+
+    // Pending velocity and acceleration parameters that shouldn't be applied
+    // until a Move function is called again
+    int32_t m_velLimitPendingQx;     // Velocity limit
+    int32_t m_altVelLimitPendingQx;  // Velocity move Velocity limit
+    int32_t m_accelLimitPendingQx;   // Acceleration limit
+    int32_t m_altDecelLimitPendingQx;// E-Stop Deceleration limit
+
+    virtual void OutputDirection() = 0;
+    void StepsPerSampleMaxSet(uint32_t maxSteps);
+
+    void AltVelMax(int32_t velMax);
+
+    /**
+        \brief Private helper function for Move functions to call that
+        updates the internal vel/accel limits to those set by the user.
+
+        Used to latch limits so a move followed immediate by a limit change
+        is not used until the next move
+    **/
+    void UpdatePendingMoveLimits() {
+        m_velLimitQx = m_velLimitPendingQx;
+        m_altVelLimitQx = m_altVelLimitPendingQx;
+        m_accelLimitQx = m_accelLimitPendingQx;
+        m_altDecelLimitQx = m_altDecelLimitPendingQx;
+    }
+};
+
+} // ClearCore namespace
+
+#endif // __STEPGENERATOR_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysConnectors.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysConnectors.h
new file mode 100644
index 000000000..d708b385e
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysConnectors.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SysConnectors.h
+
+    Defines tools related to the entire ClearCore system and its connectors
+    (constants, enums, unions, structs).
+**/
+
+
+#ifndef __SYSCONNECTORS_H__
+#define __SYSCONNECTORS_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** The total number of H-Bridge capable connectors on the ClearCore (2). **/
+#define HBRIDGE_CON_CNT  (2)
+/** The total number of motor connectors on the ClearCore (4). **/
+#define MOTOR_CON_CNT (4)
+
+/**
+    \enum ClearCorePins
+
+    \brief ClearCore PIN definitions.
+
+    \note These do not strictly map to "pins" on the CPU. They map to the
+    internal connector objects that simulate or mediate access to the actual
+    processor resources.
+
+**/
+typedef enum {
+    CLEARCORE_PIN_INVALID = -1, ///< Invalid connector index
+    CLEARCORE_PIN_IO0,  ///< [00] IO-0 ClearCore::DigitalInOutAnalogOut Connector
+    CLEARCORE_PIN_IO1,  ///< [01] IO-1 ClearCore::DigitalInOut Connector
+    CLEARCORE_PIN_IO2,  ///< [02] IO-2 ClearCore::DigitalInOut Connector
+    CLEARCORE_PIN_IO3,  ///< [03] IO-3 ClearCore::DigitalInOut Connector
+    CLEARCORE_PIN_IO4,  ///< [04] IO-4 ClearCore::DigitalInOutHBridge Connector
+    CLEARCORE_PIN_IO5,  ///< [05] IO-5 ClearCore::DigitalInOutHBridge Connector
+    CLEARCORE_PIN_DI6,  ///< [06] DI-6 ClearCore::DigitalIn Connector
+    CLEARCORE_PIN_DI7,  ///< [07] DI-7 ClearCore::DigitalIn Connector
+    CLEARCORE_PIN_DI8,  ///< [08] DI-8 ClearCore::DigitalIn Connector
+    CLEARCORE_PIN_A9,   ///< [09] A-9 ClearCore::DigitalInAnalogIn Connector
+    CLEARCORE_PIN_A10,  ///< [10] A-10 ClearCore::DigitalInAnalogIn Connector
+    CLEARCORE_PIN_A11,  ///< [11] A-11 ClearCore::DigitalInAnalogIn Connector
+    CLEARCORE_PIN_A12,  ///< [12] A-12 ClearCore::DigitalInAnalogIn Connector
+    CLEARCORE_PIN_LED,  ///< [13] User LED ClearCore::LedDriver Connector
+    CLEARCORE_PIN_M0,   ///< [14] M-0 ClearCore::MotorDriver Connector
+    CLEARCORE_PIN_M1,   ///< [15] M-1 ClearCore::MotorDriver Connector
+    CLEARCORE_PIN_M2,   ///< [16] M-2 ClearCore::MotorDriver Connector
+    CLEARCORE_PIN_M3,   ///< [17] M-3 ClearCore::MotorDriver Connector
+    CLEARCORE_PIN_COM0, ///< [18] COM-0 ClearCore::SerialDriver Connector
+    CLEARCORE_PIN_COM1, ///< [19] COM-1 ClearCore::SerialDriver Connector
+    CLEARCORE_PIN_USB,  ///< [20] USB ClearCore::SerialUsb Connector
+    CLEARCORE_PIN_MAX,  ///< [21] Count of Connectors on the ClearCore board
+    // Motor inputs
+    CLEARCORE_PIN_M0_INA,   ///< [22] M-0 ClearCore::MotorDriver InA
+    CLEARCORE_PIN_M1_INA,   ///< [23] M-1 ClearCore::MotorDriver InA
+    CLEARCORE_PIN_M2_INA,   ///< [24] M-2 ClearCore::MotorDriver InA
+    CLEARCORE_PIN_M3_INA,   ///< [25] M-3 ClearCore::MotorDriver InA
+    CLEARCORE_PIN_M0_INB,   ///< [26] M-0 ClearCore::MotorDriver InB
+    CLEARCORE_PIN_M1_INB,   ///< [27] M-1 ClearCore::MotorDriver InB
+    CLEARCORE_PIN_M2_INB,   ///< [28] M-2 ClearCore::MotorDriver InB
+    CLEARCORE_PIN_M3_INB,   ///< [29] M-3 ClearCore::MotorDriver InB
+    // CCIO-8 Pins
+    CLEARCORE_PIN_CCIO_BASE = 64,///< [64] Base index of CCIO-8 connectors
+    CLEARCORE_PIN_CCIOA0 = CLEARCORE_PIN_CCIO_BASE, ///< CCIO-8 board 1, connector 0
+    CLEARCORE_PIN_CCIOA1,   ///< CCIO-8 board 1, connector 1
+    CLEARCORE_PIN_CCIOA2,   ///< CCIO-8 board 1, connector 2
+    CLEARCORE_PIN_CCIOA3,   ///< CCIO-8 board 1, connector 3
+    CLEARCORE_PIN_CCIOA4,   ///< CCIO-8 board 1, connector 4
+    CLEARCORE_PIN_CCIOA5,   ///< CCIO-8 board 1, connector 5
+    CLEARCORE_PIN_CCIOA6,   ///< CCIO-8 board 1, connector 6
+    CLEARCORE_PIN_CCIOA7,   ///< CCIO-8 board 1, connector 7
+    CLEARCORE_PIN_CCIOB0,   ///< CCIO-8 board 2, connector 0
+    CLEARCORE_PIN_CCIOB1,   ///< CCIO-8 board 2, connector 1
+    CLEARCORE_PIN_CCIOB2,   ///< CCIO-8 board 2, connector 2
+    CLEARCORE_PIN_CCIOB3,   ///< CCIO-8 board 2, connector 3
+    CLEARCORE_PIN_CCIOB4,   ///< CCIO-8 board 2, connector 4
+    CLEARCORE_PIN_CCIOB5,   ///< CCIO-8 board 2, connector 5
+    CLEARCORE_PIN_CCIOB6,   ///< CCIO-8 board 2, connector 6
+    CLEARCORE_PIN_CCIOB7,   ///< CCIO-8 board 2, connector 7
+    CLEARCORE_PIN_CCIOC0,   ///< CCIO-8 board 3, connector 0
+    CLEARCORE_PIN_CCIOC1,   ///< CCIO-8 board 3, connector 1
+    CLEARCORE_PIN_CCIOC2,   ///< CCIO-8 board 3, connector 2
+    CLEARCORE_PIN_CCIOC3,   ///< CCIO-8 board 3, connector 3
+    CLEARCORE_PIN_CCIOC4,   ///< CCIO-8 board 3, connector 4
+    CLEARCORE_PIN_CCIOC5,   ///< CCIO-8 board 3, connector 5
+    CLEARCORE_PIN_CCIOC6,   ///< CCIO-8 board 3, connector 6
+    CLEARCORE_PIN_CCIOC7,   ///< CCIO-8 board 3, connector 7
+    CLEARCORE_PIN_CCIOD0,   ///< CCIO-8 board 4, connector 0
+    CLEARCORE_PIN_CCIOD1,   ///< CCIO-8 board 4, connector 1
+    CLEARCORE_PIN_CCIOD2,   ///< CCIO-8 board 4, connector 2
+    CLEARCORE_PIN_CCIOD3,   ///< CCIO-8 board 4, connector 3
+    CLEARCORE_PIN_CCIOD4,   ///< CCIO-8 board 4, connector 4
+    CLEARCORE_PIN_CCIOD5,   ///< CCIO-8 board 4, connector 5
+    CLEARCORE_PIN_CCIOD6,   ///< CCIO-8 board 4, connector 6
+    CLEARCORE_PIN_CCIOD7,   ///< CCIO-8 board 4, connector 7
+    CLEARCORE_PIN_CCIOE0,   ///< CCIO-8 board 5, connector 0
+    CLEARCORE_PIN_CCIOE1,   ///< CCIO-8 board 5, connector 1
+    CLEARCORE_PIN_CCIOE2,   ///< CCIO-8 board 5, connector 2
+    CLEARCORE_PIN_CCIOE3,   ///< CCIO-8 board 5, connector 3
+    CLEARCORE_PIN_CCIOE4,   ///< CCIO-8 board 5, connector 4
+    CLEARCORE_PIN_CCIOE5,   ///< CCIO-8 board 5, connector 5
+    CLEARCORE_PIN_CCIOE6,   ///< CCIO-8 board 5, connector 6
+    CLEARCORE_PIN_CCIOE7,   ///< CCIO-8 board 5, connector 7
+    CLEARCORE_PIN_CCIOF0,   ///< CCIO-8 board 6, connector 0
+    CLEARCORE_PIN_CCIOF1,   ///< CCIO-8 board 6, connector 1
+    CLEARCORE_PIN_CCIOF2,   ///< CCIO-8 board 6, connector 2
+    CLEARCORE_PIN_CCIOF3,   ///< CCIO-8 board 6, connector 3
+    CLEARCORE_PIN_CCIOF4,   ///< CCIO-8 board 6, connector 4
+    CLEARCORE_PIN_CCIOF5,   ///< CCIO-8 board 6, connector 5
+    CLEARCORE_PIN_CCIOF6,   ///< CCIO-8 board 6, connector 6
+    CLEARCORE_PIN_CCIOF7,   ///< CCIO-8 board 6, connector 7
+    CLEARCORE_PIN_CCIOG0,   ///< CCIO-8 board 7, connector 0
+    CLEARCORE_PIN_CCIOG1,   ///< CCIO-8 board 7, connector 1
+    CLEARCORE_PIN_CCIOG2,   ///< CCIO-8 board 7, connector 2
+    CLEARCORE_PIN_CCIOG3,   ///< CCIO-8 board 7, connector 3
+    CLEARCORE_PIN_CCIOG4,   ///< CCIO-8 board 7, connector 4
+    CLEARCORE_PIN_CCIOG5,   ///< CCIO-8 board 7, connector 5
+    CLEARCORE_PIN_CCIOG6,   ///< CCIO-8 board 7, connector 6
+    CLEARCORE_PIN_CCIOG7,   ///< CCIO-8 board 7, connector 7
+    CLEARCORE_PIN_CCIOH0,   ///< CCIO-8 board 8, connector 0
+    CLEARCORE_PIN_CCIOH1,   ///< CCIO-8 board 8, connector 1
+    CLEARCORE_PIN_CCIOH2,   ///< CCIO-8 board 8, connector 2
+    CLEARCORE_PIN_CCIOH3,   ///< CCIO-8 board 8, connector 3
+    CLEARCORE_PIN_CCIOH4,   ///< CCIO-8 board 8, connector 4
+    CLEARCORE_PIN_CCIOH5,   ///< CCIO-8 board 8, connector 5
+    CLEARCORE_PIN_CCIOH6,   ///< CCIO-8 board 8, connector 6
+    CLEARCORE_PIN_CCIOH7,   ///< CCIO-8 board 8, connector 7
+    CLEARCORE_PIN_CCIO_MAX,
+} ClearCorePins;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#ifdef __cplusplus
+
+namespace ClearCore {
+
+/**
+    SysConnectorState union allocating 1 bit per connector.
+
+    This union is used to hold a bitmask of state information at a
+    system level instead of having to query each connector individually.
+
+    \note Names in the bitfield match the #ClearCorePins enum.
+    \note This interface does not include any attached CCIO-8 pins. To read all
+    CCIO-8 pins see CcioBoardManager::OutputState().
+**/
+union SysConnectorState {
+    /**
+        Constructor to allow initialization lists.
+    **/
+    SysConnectorState(uint32_t initialBits) : reg(initialBits) {}
+    /**
+        Default Constructor
+    **/
+    SysConnectorState() : reg(0) {}
+
+    /**
+        Broad access to the whole register
+    **/
+    uint32_t reg;
+    /**
+        Field access to the system connector state register
+    **/
+    struct {
+        // Matched to ClearCorePins enum.
+        uint32_t CLEARCORE_PIN_IO0 : 1;
+        uint32_t CLEARCORE_PIN_IO1 : 1;
+        uint32_t CLEARCORE_PIN_IO2 : 1;
+        uint32_t CLEARCORE_PIN_IO3 : 1;
+        uint32_t CLEARCORE_PIN_IO4 : 1;
+        uint32_t CLEARCORE_PIN_IO5 : 1;
+        uint32_t CLEARCORE_PIN_DI6 : 1;
+        uint32_t CLEARCORE_PIN_DI7 : 1;
+        uint32_t CLEARCORE_PIN_DI8 : 1;
+        uint32_t CLEARCORE_PIN_A9 : 1;
+        uint32_t CLEARCORE_PIN_A10 : 1;
+        uint32_t CLEARCORE_PIN_A11 : 1;
+        uint32_t CLEARCORE_PIN_A12 : 1;
+        uint32_t CLEARCORE_PIN_LED : 1;
+        uint32_t CLEARCORE_PIN_M0 : 1;
+        uint32_t CLEARCORE_PIN_M1 : 1;
+        uint32_t CLEARCORE_PIN_M2 : 1;
+        uint32_t CLEARCORE_PIN_M3 : 1;
+        uint32_t CLEARCORE_PIN_COM0 : 1;
+        uint32_t CLEARCORE_PIN_COM1 : 1;
+        uint32_t CLEARCORE_PIN_USB : 1;
+    } bit;
+};
+
+} // ClearCore namespace
+#endif // defined(__cplusplus)
+
+#endif // !__SYSCONNECTORS_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysManager.h
new file mode 100644
index 000000000..6b35d4170
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysManager.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SysManager.h
+    Supervisory System Manager for the ClearCore Board
+
+    This class implements the high level access to the Teknic ClearCore
+    features.
+**/
+
+#ifndef __SYSMANAGER_H__
+#define __SYSMANAGER_H__
+
+#include <stddef.h>
+#include <stdint.h>
+#include "Connector.h"
+#include "PeripheralRoute.h"
+#include "SysConnectors.h"
+
+#ifdef __cplusplus
+
+/**
+    \namespace ClearCore
+
+    \brief Namespace to encompass the ClearCore board API
+**/
+namespace ClearCore {
+
+#ifndef HIDE_FROM_DOXYGEN
+typedef void (*voidFuncPtr)(void);
+#endif
+
+/**
+    \brief ClearCore Board Supervisory System Manager
+
+    This class manages the features of the Teknic ClearCore board.
+**/
+class SysManager {
+
+public:
+    /**
+        \enum ResetModes
+        \brief Reset modes for the ClearCore board.
+    **/
+    typedef enum {
+        /**
+            Reset and restart normal program execution.
+        **/
+        RESET_NORMAL,
+        /**
+            Reset and start up in the bootloader.
+        **/
+        RESET_TO_BOOTLOADER,
+    } ResetModes;
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Constructor
+    **/
+    SysManager();
+
+    /**
+        Initialize the board to power-up state
+    **/
+    void Initialize();
+
+    /**
+        \brief Accessor for SysManager's readiness
+
+        \return True if the board is initialized and ready for
+        operations.
+    **/
+    bool Ready() {
+        return m_readyForOperations;
+    }
+#endif
+
+    /**
+        \brief Pin-determined accessor for ClearCore Connector objects.
+
+        \code{.cpp}
+        // Save and cast a pointer to the IO-3 connector object.
+        // Be sure to cast the base Connector pointer to the correct type!
+        DigitalInOut *io3 =
+            static_cast<DigitalInOut*>(SysMgr.ConnectorByIndex(CLEARCORE_PIN_IO3));
+        \endcode
+
+        \param[in] connectorIndex The index in the connector array
+        \return A pointer to a connector. If the connector is out of
+        range, a NULL pointer is returned.
+    **/
+    Connector *ConnectorByIndex(ClearCorePins connectorIndex);
+
+    /**
+        \brief Resets the ClearCore.
+
+        \code{.cpp}
+        // Reset the ClearCore and restart the application from the beginning.
+        SysMgr.ResetBoard();
+        \endcode
+        \param[in] mode The reset mode. Valid reset modes are:
+        - #RESET_NORMAL
+        - #RESET_TO_BOOTLOADER.
+    **/
+    void ResetBoard(ResetModes mode = RESET_NORMAL);
+
+#ifndef HIDE_FROM_DOXYGEN
+    // Ideally these would be private, but they need to be called from C
+    // interrupt handler functions that can't be friends without putting them
+    // in a namespace.
+    void SysTickUpdate();
+    void FastUpdate();
+#endif
+
+private:
+    /// Flag to defer operations until initialized.
+    bool m_readyForOperations;
+
+    /**
+        Initialize the clock rates and interrupts.
+    **/
+    void InitClocks();
+
+    /**
+        Update systems at #SampleRateHz.
+    **/
+    void UpdateFastImpl();
+
+    /**
+        Update systems at SysTick rate.
+    **/
+    void UpdateSlowImpl();
+
+};     // SysManager
+
+} // ClearCore namespace
+
+#endif // defined(__cplusplus)
+#endif // __SYSMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysTiming.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysTiming.h
new file mode 100644
index 000000000..471ba91d5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysTiming.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SysTiming.h
+    \brief ClearCore timing profiling utility functions
+**/
+
+// include guard
+#ifndef __SYSTIMING_H__
+#define __SYSTIMING_H__
+
+#include <stdint.h>
+
+/** Number of CPU cycles, in Hz. (120MHz) **/
+#ifndef CPU_CLK
+#define CPU_CLK 120000000
+#endif // CPU_CLK
+
+/**
+    ClearCore sample rate for main interrupt processing (5 kHz).
+**/
+#ifndef _CLEARCORE_SAMPLE_RATE_HZ
+#define _CLEARCORE_SAMPLE_RATE_HZ (5000)
+#endif
+
+/**
+    ClearCore sample rate, expressed in sample times (5).
+**/
+#define MS_TO_SAMPLES (_CLEARCORE_SAMPLE_RATE_HZ / 1000)
+/**
+    Number of CPU cycles per interrupt time (24,000).
+**/
+#define CYCLES_PER_INTERRUPT   (CPU_CLK / _CLEARCORE_SAMPLE_RATE_HZ)
+/**
+    ClearCore sample time, expressed in microseconds (200us).
+**/
+#define SAMPLE_PERIOD_MICROSECONDS (1000000UL / _CLEARCORE_SAMPLE_RATE_HZ)
+/**
+    Number of CPU cycles per microsecond (120).
+**/
+#define CYCLES_PER_MICROSECOND (CPU_CLK / 1000000)
+/**
+    Number of CPU cycles per millisecond (120,000).
+**/
+#define CYCLES_PER_MILLISECOND (CPU_CLK / 1000)
+/**
+    Number of CPU cycles per second (120,000,000).
+**/
+#define CYCLES_PER_SECOND      (CPU_CLK)
+
+
+
+namespace ClearCore {
+
+/** Refresh rate of ClearCore background processing.
+    \note The refresh rate is 5 kHz, so the refresh occurs once every 200
+    microseconds.
+ **/
+const uint16_t SampleRateHz = _CLEARCORE_SAMPLE_RATE_HZ;
+
+/**
+    \class SysTiming
+    \brief ClearCore system timing class
+
+    This class provides an interface for various timing-related operations.
+**/
+class SysTiming {
+    friend class SysManager;
+
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Return the minimum and maximum fast interrupt duration cycles
+
+        Returns the minimum and maximum isr duration cycles since the last call
+        to GetIsrLoading. The minimum and maximum values then reset to the
+        number of cycles in the last interrupt.
+
+        \param[out] minSlot The minimum slot loading cycles since the last call
+        \param[out] maxSlot The maximum slot loading cycles since the last call
+    **/
+    void GetIsrLoading(uint32_t &minSlot, uint32_t &maxSlot);
+
+    /**
+        Public accessor for singleton instance
+    **/
+    static SysTiming &Instance();
+#endif
+
+    /**
+        \brief Number of microseconds elapsed since the ClearCore was
+        initialized.
+
+        Uses the processor's cycle counter register to calculate the
+        number of microseconds elapsed.
+
+        \code{.cpp}
+        // Implement a timeout of 750 microseconds.
+        uint32_t timeout = 750;
+        uint32_t start = Microseconds();
+        while (Microseconds() - start < timeout) {
+            // wait for timeout...
+        }
+        \endcode
+
+        \returns Number of microseconds since board initialization.
+
+        \note Rolls over every ~71.5 minutes (at UINT32_MAX microseconds)
+    **/
+    uint32_t Microseconds();
+
+    /**
+        Resets the microsecond timer.
+
+        \code{.cpp}
+        // Implement a timeout of 750 microseconds.
+        uint32_t timeout = 750;
+        ResetMicroseconds();
+        while (Microseconds() < timeout) {
+            // wait for timeout...
+        }
+        \endcode
+    **/
+    void ResetMicroseconds();
+
+    /**
+        \brief Number of milliseconds elapsed since the ClearCore was
+        initialized.
+
+        Uses the fast update interrupt counter to retrieve the number of
+        milliseconds elapsed.
+
+        \code{.cpp}
+        // Implement a timeout of 2000 milliseconds.
+        uint32_t timeout = 2000;
+        uint32_t start = Milliseconds();
+        while (Milliseconds() - start < timeout) {
+            // wait for timeout...
+        }
+        \endcode
+
+        \return Number of milliseconds since board initialization.
+
+        \note Rolls over every ~49.7 days (at UINT32_MAX milliseconds)
+    **/
+    volatile const uint32_t &Milliseconds() {
+        return m_msTickCnt;
+    }
+
+    /**
+        Resets the millisecond timer.
+
+        \code{.cpp}
+        // Implement a timeout of 2000 milliseconds.
+        uint32_t timeout = 2000;
+        ResetMilliseconds();
+        while (Milliseconds() < timeout) {
+            // wait for timeout...
+        }
+        \endcode
+    **/
+    void ResetMilliseconds();
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        \brief Sets the SysTick period
+
+        Sets the SysTick period, also resets SysTickCnt.
+        Default 1000uS
+
+        Setting the SysTick faster than the ClearCore Sample Rate will cause the
+        UpdateSlow to be updated at the ClearCore Sample Rate.
+
+        \param[in] microseconds (optional) SysTick period
+
+        \return success
+    **/
+    bool SysTickPeriodMicroSec(uint32_t microseconds = 1000);
+#endif
+
+private:
+    uint32_t m_isrStartCycle;
+    uint32_t m_isrMinCycles;
+    uint32_t m_isrMaxCycles;
+    uint32_t m_isrLastCycles;
+    uint32_t m_msTickCnt;
+    uint8_t m_fractMsTick;
+    uint32_t m_lastIsrStartCnt;
+    uint32_t m_microAdj;
+    uint32_t m_microAdjHigh;
+    uint32_t m_microAdjLow;
+    uint32_t m_microAdjHighRemainder;
+    uint32_t m_microAdjLowRemainder;
+
+
+    /**
+        Constructor
+    **/
+    SysTiming();
+
+    /**
+        \brief Signal the start of the main interrupt service routine
+
+        Captures the CPU clock cycle counter at the start of the ISR
+    **/
+    void IsrStart();
+    /**
+        \brief Signal the end of the main interrupt service routine
+
+        Captures the CPU clock cycle counter at the end of the ISR.
+        Updates the minimum and maximum ISR duration values.
+    **/
+    void IsrEnd();
+    /**
+        \brief Update at the sample rate
+
+        Updates the millisecond tick counter. Keeps track of CPU
+        cycle counter overflows so that the microseconds calculations
+        can properly wrap at UINT32_MAX
+    **/
+    void Update();
+
+};
+
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+/**
+    \brief Number of milliseconds since the ClearCore was initialized
+
+    Uses the fast update interrupt counter to retrieve the number of
+    milliseconds elapsed.
+
+    \return milliseconds
+
+    \note Rolls over every ~49.7 days (at UINT32_MAX milliseconds)
+**/
+uint32_t Milliseconds(void);
+
+/**
+    \brief Number of microseconds since the ClearCore was initialized
+
+    Uses the processor's cycle counter register to calculate the
+    number of microseconds elapsed.
+
+    \returns Microseconds
+
+    \note Rolls over every ~71.5 minutes (at UINT32_MAX microseconds)
+**/
+uint32_t Microseconds(void);
+
+/**
+    \brief Blocks for operations cycles CPU cycles
+
+    \param[in] cycles Time in CPU cycles to delay
+**/
+void Delay_cycles(uint64_t cycles);
+
+/**
+    \brief Blocks operations for ms milliseconds
+
+    \param[in] ms Time in milliseconds to delay
+**/
+inline void Delay_ms(uint32_t ms)  {
+    return Delay_cycles(static_cast<uint64_t>(ms) * CYCLES_PER_MILLISECOND);
+}
+
+/**
+    \brief Blocks for operations usec microseconds
+
+    \param[in] usec Time in microseconds to delay
+**/
+inline void Delay_us(uint32_t usec) {
+    return Delay_cycles(static_cast<uint64_t>(usec) * CYCLES_PER_MICROSECOND);
+}
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+// end of include guard
+#endif // __SYSTIMING_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysUtils.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysUtils.h
new file mode 100644
index 000000000..8915c6ea2
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/SysUtils.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file SysUtils.h
+    \brief ClearCore common utility functions
+**/
+
+#ifndef __SYSUTILS_H__
+#define __SYSUTILS_H__
+
+#include <stdint.h>
+
+// A    EIC
+// B    REF
+//      ADC
+//      AC
+//      DAC
+//      PTC
+// C    SERCOM
+// D    SERCOM_ALT
+// E    TC
+// F    TCC
+// G    TCC/PDEC
+// H    USB
+// I    SDHC
+// J    I2S
+// K    PCC
+// L    GMAC
+// M    GCLK/AC
+// N    CCL
+
+/** Peripheral type **/
+typedef enum {
+    /* The pin is controlled by the assoc. signal of peripheral... */
+    PER_EXTINT = 0, /* A. */
+    PER_ANALOG,     /* B. */
+    PER_SERCOM,     /* C. */
+    PER_SERCOM_ALT, /* D. */
+    PER_TIMER,      /* E. */
+    PER_TIMER_ALT,  /* F. */
+    PER_TIMER_PDEC, /* G. */
+    PER_USB,        /* H. */
+    PER_SDHC,       /* I. */
+    PER_I2S,        /* J. */
+    PER_PCC,        /* K. */
+    PER_GMAC,       /* L. */
+    PER_GCLK_AC,    /* M. */
+    PER_CCL,        /* N. */
+} PerType;
+
+/**
+    Set the correct peripheral multiplexer for the specified pin in the
+    specified port.
+ **/
+#define PMUX_SELECTION(GPIO_PORT, GPIO_PIN, PER_TYPE)                          \
+if ((GPIO_PIN) & 1) {                                                          \
+    PORT->Group[(GPIO_PORT)].PMUX[(GPIO_PIN) >> 1].bit.PMUXO = (PER_TYPE);     \
+}                                                                              \
+else {                                                                         \
+    PORT->Group[(GPIO_PORT)].PMUX[(GPIO_PIN) >> 1].bit.PMUXE = (PER_TYPE);     \
+}
+
+/**
+    Write the data mask to the Data Output Value register on the specified port.
+**/
+#define DATA_OUTPUT_STATE(GPIO_PORT, DATA_MASK, STATE)                         \
+if ((STATE)) {                                                                 \
+    PORT->Group[(GPIO_PORT)].OUTSET.reg = (DATA_MASK);                         \
+}                                                                              \
+else {                                                                         \
+    PORT->Group[(GPIO_PORT)].OUTCLR.reg = (DATA_MASK);                         \
+}
+
+/**
+    Enable the peripheral multiplexer on the specified pin on the specified port.
+**/
+#define PMUX_ENABLE(GPIO_PORT, GPIO_PIN)                                       \
+PORT->Group[(GPIO_PORT)].PINCFG[(GPIO_PIN)].bit.PMUXEN = 1
+
+/**
+    Disable the peripheral multiplexer on the specified pin on the specified port.
+**/
+#define PMUX_DISABLE(GPIO_PORT, GPIO_PIN)                                      \
+PORT->Group[(GPIO_PORT)].PINCFG[(GPIO_PIN)].bit.PMUXEN = 0
+
+/**
+    Set the pin configuration for the specified pin on the specified port.
+**/
+#define PIN_CONFIGURATION(GPIO_PORT, GPIO_PIN, CONFIG)                         \
+PORT->Group[(GPIO_PORT)].PINCFG[(GPIO_PIN)].reg = (CONFIG)
+
+/**
+    Configure the port data direction as output.
+**/
+#define DATA_DIRECTION_OUTPUT(GPIO_PORT, DATA_MASK)                            \
+PORT->Group[(GPIO_PORT)].DIRSET.reg = (DATA_MASK)
+
+/**
+    Configure the port data direction as input.
+**/
+#define DATA_DIRECTION_INPUT(GPIO_PORT, DATA_MASK)                             \
+PORT->Group[(GPIO_PORT)].DIRCLR.reg = (DATA_MASK)
+
+/**
+    Wait for the synchronization bits (BITMASK) of the peripheral (PER).
+**/
+#define SYNCBUSY_WAIT(PER, BITMASK)                                            \
+while ((PER)->SYNCBUSY.reg & (BITMASK)) {                                      \
+    continue;                                                                  \
+}
+
+/**
+    Enable the clock specified by the bit on the given Advanced Peripheral Bus.
+**/
+#define CLOCK_ENABLE(BUS, BIT)                                                 \
+MCLK->BUS.bit.BIT = 1
+
+/**
+    Set the peripheral's clock source.
+
+    - PER_GLCK_ID is the GCLK ID of a peripheral (e.g. DAC_GCLK_ID).
+    - GCLK_INDEX is the numeric index of the GCLK source (i.e. 0-11).
+
+    This will work because GCLK_PCHCTRL_GEN_GCLKx_Val == x for x in [0, 11]
+    (see gclk.h).
+    Therefore GCLK_PCHCTRL_GEN(x) ==
+                GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLKx_Val)
+    and so the correct value will be set in the GEN register of the GCLK.
+
+    The procedure for setting a peripheral's clock source follows from
+    section 14.6.3.3 Selecting the Clock Source for a Peripheral (p. 155)
+    of the SAMD5xE5x datasheet:
+        1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN=0
+        2. Assert that PCHCTRLm.CHEN reads '0'
+        3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN
+        4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN=1
+
+    ...and from section 14.6.3.1 Enabling a Peripheral Clock (p. 155):
+
+    The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain.
+    PCHCTRLm.CHEN will continue to read as its previous state until the
+    synchronization is complete.
+
+    This necessary synchronization is the reason for the final while-loop.
+**/
+#define SET_CLOCK_SOURCE(PER_GCLK_ID, GCLK_INDEX)                              \
+GCLK->PCHCTRL[(PER_GCLK_ID)].bit.CHEN = 0;                                     \
+while (GCLK->PCHCTRL[(PER_GCLK_ID)].bit.CHEN) {                                \
+    continue;                                                                  \
+}                                                                              \
+GCLK->PCHCTRL[(PER_GCLK_ID)].bit.GEN = GCLK_PCHCTRL_GEN((GCLK_INDEX));         \
+GCLK->PCHCTRL[(PER_GCLK_ID)].bit.CHEN = 1;                                     \
+while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL((GCLK_INDEX))) {             \
+    continue;                                                                  \
+}
+/**
+    Return the maximum value of a and b.
+**/
+#ifndef max
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+/**
+    Return the minimum value of a and b.
+**/
+#ifndef min
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+    \brief Update GCLK frequency
+
+    Updates the divisor on the specified GCLK to generate the requested
+    frequency.
+
+    \param[in] gclkIndex The GCLK index.
+    \param[in] freqReq The requested frequency, in Hz.
+**/
+void GClkFreqUpdate(uint8_t gclkIndex, uint32_t freqReq);
+
+#ifdef __cplusplus
+}
+#endif
+#endif // __SYSUTILS_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/UsbManager.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/UsbManager.h
new file mode 100644
index 000000000..475349fba
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/UsbManager.h
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file UsbManager.h
+
+    USB manager class to handle USB 2.1 communication as a device.
+
+    General Operation:
+        The USB peripheral has a built in DMA separate from the main DMA. It
+        uses this DMA to transfer data to RAM for software to read.
+
+    Abbreviations:
+        EP -> Endpoint
+        DIR -> Direction
+        PCK -> Packet
+        CDC -> Communication Device Class
+        ACM -> Abstract Control Model
+**/
+
+#ifndef __USBMANAGER_H__
+#define __USBMANAGER_H__
+
+#include <stdint.h>
+#include <stdio.h>
+#include <sam.h>
+
+// extern "C" {
+//     #include "cdcdf_acm.h"
+// }
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "hpl_usb.h"
+#include "cdcdf_acm.h"
+#include "cdcdf_acm_desc.h"
+#include "hal_usb_device.h"
+#include "hri_mclk_e53.h"
+#include "hri_gclk_e53.h"
+#include "hal_gpio.h"
+#include "hri_port_e53.h"
+#ifdef __cplusplus
+}
+#endif
+namespace ClearCore {
+
+/** USB serial buffer size, in bytes. (64) **/
+#ifndef USB_SERIAL_BUFFER_SIZE
+#define USB_SERIAL_BUFFER_SIZE 64
+#endif
+
+// List of all UsbStatusReg items. Will be used to generate bitfield, enums, and
+// masks. Ensures that the three are kept up to date with each other.
+#define USB_STATUS_REG_LIST(Func)                                      \
+    Func(UnhandledSetupReq)                                            \
+    Func(UnhandledDescReq)                                             \
+    Func(UnhandledStringReq)                                           \
+    Func(UnhandledFeatureReq)                                          \
+    Func(FailedStandardSetup)                                          \
+    Func(FailedClassSetup)                                             \
+    Func(FailedDescriptor)                                             \
+    Func(FailedTransferIn)                                             \
+    Func(FailedTransferOut)                                            \
+    Func(TimeoutRead)                                                  \
+    Func(TimeoutWrite)                                                 \
+    Func(TimeoutSync)                                                  \
+    Func(RamAccessError)                                               \
+    Func(FrameNumberCrcError)                                          \
+    Func(ReadBufferOverflow)                                           \
+
+
+// Used to populate the bit fields in a union
+#ifdef STRUCTIFY
+#undef STRUCTIFY
+#endif
+#define STRUCTIFY(item) \
+uint32_t item  : 1;
+
+// Used to populate the items in a macro
+#ifdef ENUMIFY
+#undef ENUMIFY
+#endif
+#define ENUMIFY(item) \
+    item,
+
+// Used to generate masks from a previously defined enum.
+#ifdef MASKIFY
+#undef MASKIFY
+#endif
+#define MASKIFY(item) \
+    const uint32_t   item##Mask = 1UL << item ;
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+
+#ifndef HIDE_FROM_DOXYGEN
+/**
+    Status Register
+**/
+union UsbStatusRegister {
+    /**
+        Broad access to the whole register
+    **/
+    uint32_t reg;
+    /**
+        Field access to the status register
+    **/
+    struct {
+        USB_STATUS_REG_LIST(STRUCTIFY)
+    } bit;
+};
+#endif
+
+#ifndef HIDE_FROM_DOXYGEN
+/**
+    \brief USB Status register fields enum
+
+    Provides index into Status Register Fields with names matching those in
+    USB_STATUS_REG_LIST.
+**/
+typedef enum {
+    USB_STATUS_REG_LIST(ENUMIFY)
+    USB_STATUS_REG_FIELD_LAST_ITEM
+} UsbStatusRegFields;
+
+#define UNUSED(expr) (void)(expr)
+
+#endif
+/**
+    Generates a mask for all of the items in the USB_STATUS_REG_LIST. Appends
+    the text "Mask" to the item in the list.
+
+    e.g. The mask for TimeoutRead is TimeoutReadMask
+**/
+USB_STATUS_REG_LIST(MASKIFY)
+
+
+/**
+    \brief USB manager Class
+
+    Implements a CDC (Communications Device Class) USB device. The CDC uses
+    an abstract control model (ACM) to emulate a serial port.
+
+    Reading:
+        Upon receiving data (interrupt based), the data is copied into a
+        circular buffer. When the buffer is full, the receipt of data is
+        acknowledged, but not copied into the buffer. Data is drained from the
+        buffer via the Read function. To Query the number of available bytes
+        call Available().
+
+    Writing:
+        Small transfers (less than a packet size) are copied into a buffer
+        and sent in the background. Larger transfers are still sent in the
+        background, but are not buffered. This means that the pointer to the
+        data must remain valid during the sending procedure.
+
+**/
+class UsbManager {
+    friend class SysManager;
+public:
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Public accessor for singleton instance
+    **/
+    static UsbManager &Instance();
+#endif
+
+    /**
+        \brief Change the baud rate for the port.
+
+        \param[in] bitsPerSecond The new speed setting
+        \return Returns true if port accepted the speed request.
+    **/
+    bool Speed(uint32_t bitsPerSecond);
+
+    /**
+        \brief Get current port speed.
+
+        \return Returns port speed in bits per second.
+    **/
+    uint32_t Speed();
+
+    /**
+    \brief Return whether or not the USB port is open
+
+    \return True if the port is open, and false otherwise.
+    **/
+    bool PortIsOpen();
+
+    void PortOpen();
+    void PortClose();
+
+    void FlushInput();
+
+    void WaitForWriteFinish();
+
+    /**
+       \copydoc ISerial::AvailableForRead()
+    **/
+    int32_t AvailableForRead();
+
+    /**
+         \copydoc ISerial::AvailableForWrite()
+    **/
+    int32_t AvailableForWrite();
+
+    /**
+        \copydoc ISerial::CharGet()
+    **/
+    int16_t CharGet();
+
+    /**
+        \copydoc ISerial::CharPeek()
+    **/
+    int16_t CharPeek();
+
+    /**
+        \copydoc ISerial::SendChar(uint8_t charToSend)
+    **/
+    bool SendChar(uint8_t charToSend);
+
+    /**
+        \brief Returns whether USB is connected and operational.
+    **/
+    operator bool();
+
+    const volatile usb_cdc_control_signal_t &LineState() {
+        return m_lineState;
+    }
+
+    UsbManager();
+
+private:
+
+    void Refresh();
+
+    /**
+        Receives characters from the DATA register and places them in the
+        receiving buffer.
+    **/
+    void RxProc();
+
+    /**
+        Transmit any data waiting in the transmit buffer.
+    **/
+    void TxPump();
+    static bool CBLineStateChanged(usb_cdc_control_signal_t state);
+    static bool TxComplete(const uint8_t ep,
+                           const enum usb_xfer_code rc,
+                           const uint32_t count);
+    static bool RxComplete(const uint8_t ep,
+                           const enum usb_xfer_code rc,
+                           const uint32_t count);
+
+    void cdc_device_acm_init(void);
+
+
+    // Serial Buffers
+    __attribute__((__aligned__(4))) uint8_t m_bufferIn[USB_SERIAL_BUFFER_SIZE];
+    __attribute__((__aligned__(4))) uint8_t m_bufferOut[USB_SERIAL_BUFFER_SIZE];
+
+    __attribute__((__aligned__(4))) uint8_t m_usbReadBuf[USB_SERIAL_BUFFER_SIZE];
+    __attribute__((__aligned__(4))) uint8_t m_usbWriteBuf[USB_SERIAL_BUFFER_SIZE];
+    // Indices for head and tails of the ring buffers
+    volatile uint32_t m_inHead, m_inTail;
+    volatile uint32_t m_outHead, m_outTail;
+
+    volatile bool m_sendActive;
+    volatile bool m_readActive;
+    usb_cdc_control_signal_t m_lineState;
+    uint8_t *m_readBufPtr;
+    uint32_t m_readBufAvail;
+
+    bool m_portOpen;
+
+    /**
+        Initializes the UsbManager.
+    **/
+    bool Initialize();
+    /**
+        Software resets the USB peripheral. Initialization will have to
+        be re-performed.
+    **/
+    void Reset();
+    void RxCopyToRingBuf();
+    /**
+        \brief Returns whether USB is connected.
+    **/
+    bool Connected();
+
+}; // UsbManager
+
+} // ClearCore namespace
+#endif //__USBMANAGER_H__
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/VersionInfo.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/VersionInfo.h
new file mode 100644
index 000000000..716cea87d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/VersionInfo.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+ 
+#ifndef __VERSIONINFO_H__
+#define __VERSIONINFO_H__
+
+#define CLEARCORE_VERSION "1.0.101"
+ 
+#endif // __VERSIONINFO_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/XBeeDriver.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/XBeeDriver.h
new file mode 100644
index 000000000..5737cf11d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/XBeeDriver.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    \file XBeeDriver.h
+    This class controls access to the XBee wireless controller.
+
+    It will allow you to setup:
+        - Achieve a wireless serial port to a remote location
+**/
+
+#ifndef __XBEEDRIVER_H__
+#define __XBEEDRIVER_H__
+
+#include <stdint.h>
+#include "PeripheralRoute.h"
+#include "SerialDriver.h"
+
+namespace ClearCore {
+
+/**
+    \brief ClearCore XBee Interface
+
+    This class manages access to the XBee module on the ClearCore board.
+**/
+class XBeeDriver : public SerialBase {
+    friend class SysManager;
+
+public:
+
+#ifndef HIDE_FROM_DOXYGEN
+    /**
+        Default constructor so this connector can be a global and constructed
+        by SysManager.
+    **/
+    XBeeDriver() {};
+#endif
+
+private:
+    /**
+        Constructor, wires in pins and non-volatile info.
+    **/
+    XBeeDriver(const PeripheralRoute *ctsInfo, const PeripheralRoute *rtsInfo,
+               const PeripheralRoute *rxInfo, const PeripheralRoute *txInfo,
+               uint8_t peripheral);
+
+};
+
+} // ClearCore namespace
+#endif // __XBEEDRIVER_H__
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/atomic_utils.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/atomic_utils.h
new file mode 100644
index 000000000..20c27de30
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/inc/atomic_utils.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * atomic_utils.h
+ *
+ * Defines macros to aid in atomic gcc operations
+ */
+
+#ifndef __ATOMIC_UTILS_H_
+#define __ATOMIC_UTILS_H_
+
+#define atomic_store_n(ptr, val) __atomic_store_n(ptr, val, __ATOMIC_RELEASE)
+
+#define atomic_or_fetch(ptr, val)                                              \
+    __atomic_or_fetch(ptr, val, __ATOMIC_ACQ_REL)
+#define atomic_fetch_or(ptr, val)                                              \
+    __atomic_fetch_or(ptr, val, __ATOMIC_ACQ_REL)
+
+#define atomic_xor_fetch(ptr, val)                                             \
+    __atomic_xor_fetch(ptr, val, __ATOMIC_ACQ_REL)
+
+#define atomic_fetch_and(ptr, val)                                             \
+ __atomic_fetch_and(ptr, val, __ATOMIC_ACQ_REL)
+#define atomic_and_fetch(ptr, val)                                             \
+    __atomic_and_fetch(ptr, val, __ATOMIC_ACQ_REL)
+
+#define atomic_fetch_add(ptr, val)                                             \
+ __atomic_fetch_add(ptr, val, __ATOMIC_ACQ_REL)
+#define atomic_add_fetch(ptr, val)                                             \
+    __atomic_add_fetch(ptr, val, __ATOMIC_ACQ_REL)
+
+#define atomic_load(ptr, ret)                                                  \
+    __atomic_load(ptr, ret, __ATOMIC_CONSUME)
+
+#define atomic_load_n(ptr) __atomic_load_n(ptr, __ATOMIC_CONSUME)
+#define atomic_load_n_relaxed(ptr) __atomic_load_n(ptr, __ATOMIC_RELAXED)
+
+#define atomic_exchange(ptr, val, ret)                                         \
+    __atomic_exchange(ptr, val, ret, __ATOMIC_ACQ_REL)
+#define atomic_exchange_n(ptr, val)                                            \
+    __atomic_exchange_n(ptr, val, __ATOMIC_ACQ_REL)
+
+#define atomic_test_and_set(ptr) __atomic_test_and_set(ptr, __ATOMIC_ACQUIRE)
+
+#define atomic_clear(ptr) __atomic_clear(ptr, __ATOMIC_RELEASE)
+
+#define atomic_test_and_set_acqrel(ptr) __atomic_test_and_set(ptr, __ATOMIC_ACQ_REL)
+
+#define atomic_clear_seqcst(ptr) __atomic_clear(ptr, __ATOMIC_SEQ_CST)
+
+#endif /* __ATOMICGCC_H_ */
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/license.txt b/vendor/teknic/clear-core/ClearCore-library/libClearCore/license.txt
new file mode 100644
index 000000000..7aac97618
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/license.txt
@@ -0,0 +1,19 @@
+Copyright (c) 2019 Teknic, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/AdcManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/AdcManager.cpp
new file mode 100644
index 000000000..70046709b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/AdcManager.cpp
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ADC Peripheral Manager for the ClearCore Board
+
+    This class manages the ADC peripheral on the Teknic ClearCore.
+**/
+
+#include "AdcManager.h"
+#include <cstring>
+#include <stdio.h>
+#include <sam.h>
+#include "DmaManager.h"
+#include "HardwareMapping.h"
+#include "ShiftRegister.h"
+#include "StatusManager.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+extern ShiftRegister ShiftReg;
+extern StatusManager &StatusMgr;
+AdcManager &AdcMgr = AdcManager::Instance();
+
+constexpr float AdcManager::ADC_INITIAL_FILTER_VALUE_V[ADC_CHANNEL_COUNT];
+constexpr float AdcManager::ADC_CHANNEL_MAX_FLOAT[ADC_CHANNEL_COUNT];
+
+// Uncomment to generate an interrupt when the ADC result DMA transfer completes
+//#define DEBUG_ADC_RESULT_TIMING
+
+/**
+    ADC conversion results DMA data destination
+**/
+volatile uint16_t AdcResultsRaw[AdcManager::ADC_CHANNEL_COUNT] = {0};
+
+/**
+    ADC channel selection DMA data source structure
+**/
+union adcDSeqCfg {
+    struct {
+        ADC_INPUTCTRL_Type INPUTCTRL; ///< Offset: 0x04 (R/W 16) Input Control
+        ADC_CTRLB_Type CTRLB;         ///< Offset: 0x06 (R/W 16) Control B
+    } bit;
+    uint32_t reg;
+#ifdef __cplusplus
+    adcDSeqCfg() {
+        reg = 0;
+    }
+    adcDSeqCfg(uint16_t inputCtrl, uint16_t ctrlb) {
+        bit.INPUTCTRL.reg = inputCtrl;
+        bit.CTRLB.reg = ctrlb;
+    }
+#endif
+};
+
+// ADC channel selection DMA data source
+// The first argument is the full INPUTCTRL register value that will be loaded
+// into the ADC
+// Note: The last position also has the Sequence stop bit enabled
+//       to alert the ADC that the sequence is finished
+// Note: index matched to AdcChannels
+static const adcDSeqCfg adcSequence[AdcManager::ADC_CHANNEL_COUNT] = {
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN4, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN5, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN6, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN7, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN8, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN9, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN10, 0),
+    adcDSeqCfg(ADC_INPUTCTRL_MUXPOS_AIN11 | ADC_INPUTCTRL_DSEQSTOP, 0),
+};
+
+static inline void WaitAdc() {
+    while (ADC1->STATUS.bit.ADCBUSY) {
+        continue;
+    }
+}
+
+AdcManager &AdcManager::Instance() {
+    static AdcManager *instance = new AdcManager();
+    return *instance;
+}
+
+/**
+    Constructor
+**/
+AdcManager::AdcManager()
+    : m_initialized(false),
+      m_AdcTimeout(false),
+      m_shiftRegSnapshot(UINT32_MAX),
+      m_shiftRegPending(UINT32_MAX),
+      m_AdcResolution(ADC_RESOLUTION_DEFAULT),
+      m_AdcResPending(ADC_RESOLUTION_DEFAULT),
+      m_AdcTimeoutLimit(ADC_TIMEOUT_DEFAULT),
+      m_AdcBusyCount(0) {}
+
+/**
+    Initialize the ADC to power-up state.
+**/
+void AdcManager::Initialize() {
+    m_initialized = false;
+    m_AdcTimeout = false;
+    m_shiftRegSnapshot = UINT32_MAX;
+    m_shiftRegPending = UINT32_MAX;
+    m_AdcResolution = ADC_RESOLUTION_DEFAULT;
+    m_AdcResPending = ADC_RESOLUTION_DEFAULT;
+    m_AdcTimeoutLimit = ADC_TIMEOUT_DEFAULT;
+    m_AdcBusyCount = 0;
+
+    // Set default filter constants
+    for (uint8_t i = 0; i < ADC_CHANNEL_COUNT; i++) {
+        m_analogFilter[i].Tc_ms(ADC_IIR_FILTER_TC_MS);
+    }
+
+    // Configure internal analog inputs: Sdrvr2, Sdrvr3, VBus, 5V Ob monitor
+    const uint8_t INTERNAL_ADC_INPUTS = 4;
+    const PeripheralRoute *adcsToSetup[INTERNAL_ADC_INPUTS] = {
+        &_5VOB_MON, &Vsupply_MON_IO_4and5_RST,
+        &Sdrvr2_iMon, &Sdrvr3_iMon
+    };
+
+    for (uint8_t i = 0; i < INTERNAL_ADC_INPUTS; i++) {
+        const PeripheralRoute *prPtr = adcsToSetup[i];
+
+        ClearCorePorts adcGpioPort = prPtr->gpioPort;
+        uint8_t adcGpioPin = prPtr->gpioPin;
+
+        PMUX_SELECTION(adcGpioPort, adcGpioPin, PER_ANALOG);
+        PMUX_ENABLE(adcGpioPort, adcGpioPin);
+    }
+
+    // Set up ADC
+
+    // Set the clock source for ADC1 to GCLK4 (48 MHz) and enable
+    // the peripheral channel
+    SET_CLOCK_SOURCE(ADC1_GCLK_ID, 4);
+
+    // Enables the peripheral clock to ADC1
+    CLOCK_ENABLE(APBDMASK, ADC1_);
+
+    // Reset the ADC1 module
+    ADC1->CTRLA.bit.SWRST = 1;
+    SYNCBUSY_WAIT(ADC1, ADC_SYNCBUSY_SWRST);
+
+    // Configure the ADC read resolution
+    AdcResChange();
+
+    // Set clock pre-scaler to 4 to result in a clock signal of 48/4 = 12 MHz
+    // Note: ADC can pre-scale the clock a minimum of 2.
+    ADC1->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV4_Val;
+
+    // Set input to channel AIN4 and pause the DMA input sequencing
+    ADC1->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS_AIN4 | ADC_INPUTCTRL_DSEQSTOP;
+    SYNCBUSY_WAIT(ADC1, ADC_SYNCBUSY_INPUTCTRL);
+
+    // Setup the DMA input/result transfers
+    DmaInit();
+
+    // Update INPUTCTRL from the DMA engine
+    ADC1->DSEQCTRL.bit.INPUTCTRL = 1;
+    SYNCBUSY_WAIT(ADC1, ADC_SYNCBUSY_INPUTCTRL);
+    ADC1->DSEQCTRL.bit.AUTOSTART = 1;
+
+    // Enable reference buffer compensation and set the reference to VDDANA
+    ADC1->REFCTRL.reg |= ADC_REFCTRL_REFCOMP | ADC_REFCTRL_REFSEL_INTVCC1;
+    SYNCBUSY_WAIT(ADC1, ADC_SYNCBUSY_REFCTRL);
+
+    // Enable sampling period offset compensation
+    // Note: setting sample length fairly long since the ADC readings will be
+    // performed in the background, which results in more reliable readings.
+    // Setting the sample length to 31 uses approximately 20% of the available
+    // time when doing 8 12-bit readings per 5 kHz interrupt slot.
+    ADC1->SAMPCTRL.reg = ADC_SAMPCTRL_SAMPLEN(31);
+    SYNCBUSY_WAIT(ADC1, ADC_SYNCBUSY_SAMPCTRL);
+
+    ADC1->DBGCTRL.bit.DBGRUN = 1;
+
+    // Kick off the first ADC conversion
+    DmaUpdate();
+
+    // Enable ADC
+    ADC1->CTRLA.bit.ENABLE = 0x01;
+    SYNCBUSY_WAIT(ADC1, ADC_SYNCBUSY_ENABLE);
+
+    // Wait for the first conversion to complete
+    while (DmaManager::Channel(DMA_ADC_RESULTS)->CHCTRLA.bit.ENABLE) {
+        continue;
+    }
+    while (DmaManager::Channel(DMA_ADC_SEQUENCE)->CHCTRLA.bit.ENABLE) {
+        continue;
+    }
+
+    WaitAdc();
+
+    // Populate initial values
+    for (uint32_t i = 0; i < ADC_CHANNEL_COUNT; i++) {
+        uint16_t val = ADC_INITIAL_FILTER_VALUE_V[i] * (1 << 15) /
+                       ADC_CHANNEL_MAX_FLOAT[i];
+        m_AdcResultsConverted[i] = val;
+        m_AdcResultsConvertedFiltered[i] = val;
+        m_analogFilter[i].Reset(val);
+    }
+
+    m_initialized = true;
+}
+
+/**
+    Update systems at the sample rate
+**/
+void AdcManager::Update() {
+    if (!m_initialized) {
+        return;
+    }
+
+    // If the previous conversion isn't complete or there are more conversions
+    // still to be performed, increment the timeout counter
+    if (ADC1->STATUS.bit.ADCBUSY ||
+            DmaManager::Channel(DMA_ADC_RESULTS)->CHCTRLA.bit.ENABLE) {
+        // If the counter is greater than the timeout, throw an error
+        if (++m_AdcBusyCount >= m_AdcTimeoutLimit) {
+            m_AdcTimeout = true;
+        }
+    }
+    else {
+        // Clear the error and reset the counter
+        m_AdcBusyCount = 0;
+        m_AdcTimeout = false;
+
+        // Copy the finished results into m_AdcResultsConverted and convert to
+        // Q15
+        for (uint8_t i = 0; i < ADC_CHANNEL_COUNT; i++) {
+            // If HBridgeReset is set, do not update the VSupply value
+            if (i == ADC_VSUPPLY_MON && StatusMgr.StatusRT().bit.HBridgeReset) {
+                continue;
+            }
+            // Normalize the ADC results to a Q15 value
+            m_AdcResultsConverted[i] =
+                AdcResultsRaw[i] << (15 - m_AdcResolution);
+        }
+
+        // Kick off next conversion sequence
+        if (m_AdcResolution != m_AdcResPending) {
+            AdcResChange();
+        }
+        m_shiftRegSnapshot = m_shiftRegPending;
+        m_shiftRegPending = ShiftReg.LastOutput();
+        DmaUpdate();
+    }
+
+    // Apply IIR filtering even if the ADC values have not been updated
+    for (uint8_t i = 0; i < ADC_CHANNEL_COUNT; i++) {
+        m_analogFilter[i].Update(m_AdcResultsConverted[i]);
+        m_AdcResultsConvertedFiltered[i] = m_analogFilter[i].LastOutput();
+    }
+}
+
+/**
+    Initialize the DMA engine to stream ADC conversions and results.
+**/
+void AdcManager::DmaInit() {
+    // DMAC channel 0 is used to retrieve results from the ADC.
+    // Channel 0 is triggered by the ADC result ready flag.
+    // When triggered, the DMAC CH 0 should move the ADC result
+    // to the program-created AdcResultsRaw array. The DMAC needs to
+    // move 16-bits(one HWORD) of data(max output from the ADC).
+
+    /***************************************************************
+     * DMA_ADC_RESULTS Channel
+     * Read each ADC result and store it into the AdcResult array.
+     ***************************************************************/
+    DmacChannel *channel;
+    DmacDescriptor *baseDesc;
+    channel = DmaManager::Channel(DMA_ADC_RESULTS);
+    baseDesc = DmaManager::BaseDescriptor(DMA_ADC_RESULTS);
+    // Configure DMA channel 0 to stream results from the ADC
+    // Disable the channel so it can be written to
+    channel->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+
+    channel->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+    // Wait for the reset to finish
+    while (channel->CHCTRLA.reg == DMAC_CHCTRLA_SWRST) {
+        continue;
+    }
+
+    channel->CHCTRLA.reg = DMAC_CHCTRLA_TRIGSRC(ADC1_DMAC_ID_RESRDY) |
+                           DMAC_CHCTRLA_TRIGACT_BURST |
+                           DMAC_CHCTRLA_BURSTLEN_SINGLE;
+
+#ifdef DEBUG_ADC_RESULT_TIMING
+    // Enable channel completion interrupts
+    channel->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+    NVIC_EnableIRQ(static_cast<IRQn_Type>(DMAC_0_IRQn + DMA_ADC_RESULTS));
+#endif
+
+    // Descriptors can work like linked lists. Since this is the only
+    // transfer descriptor for the channel, point to 0 to stop transactions
+    baseDesc->DESCADDR.reg = static_cast<uint32_t>(0);
+    baseDesc->SRCADDR.reg = (uint32_t)&ADC1->RESULT.reg;
+    baseDesc->BTCNT.reg = ADC_CHANNEL_COUNT;
+
+    // End address
+    baseDesc->DSTADDR.reg = (uint32_t)(AdcResultsRaw + ADC_CHANNEL_COUNT);
+    baseDesc->BTCTRL.reg =
+        DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_VALID;
+
+    /***************************************************************
+     * DMA_ADC_SEQUENCE Channel
+     * This tells the ADC what channel to read
+     ***************************************************************/
+    channel = DmaManager::Channel(DMA_ADC_SEQUENCE);
+    // Disable and reset the channel so it is clean to setup
+    channel->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+    channel->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+    // Wait for the reset to finish
+    while (channel->CHCTRLA.reg == DMAC_CHCTRLA_SWRST) {
+        continue;
+    }
+
+    // Configure the channel to be triggered from the ADC1 DMAC sequence start
+    // Trigger will cause a single burst(one transfer)
+    channel->CHCTRLA.reg = DMAC_CHCTRLA_TRIGSRC(ADC1_DMAC_ID_SEQ) |
+                           DMAC_CHCTRLA_TRIGACT_BURST |
+                           DMAC_CHCTRLA_BURSTLEN_SINGLE;
+
+    baseDesc = DmaManager::BaseDescriptor(DMA_ADC_SEQUENCE);
+    // Descriptors can work like linked lists. Since this is the only
+    // transfer descriptor for the channel, point to 0 to stop transactions
+    baseDesc->DESCADDR.reg = static_cast<uint32_t>(0);
+    // Point the src to the end of the adcSequence. The transfer will copy the
+    // data before the src addr.
+    baseDesc->SRCADDR.reg =
+        (reinterpret_cast<uint32_t>(&adcSequence)) + sizeof(adcSequence);
+    baseDesc->BTCNT.reg = ADC_CHANNEL_COUNT;
+    // The Destination is the ADC register for sequence data.
+    // The sequence data is what will be moved into the ADC.
+    baseDesc->DSTADDR.reg =
+        reinterpret_cast<uint32_t>(&REG_ADC1_DSEQDATA); // end address
+    baseDesc->BTCTRL.reg = DMAC_BTCTRL_BEATSIZE_WORD | DMAC_BTCTRL_STEPSEL_SRC |
+                           DMAC_BTCTRL_VALID | DMAC_BTCTRL_SRCINC;
+}
+
+/**
+    Initialize the DMA engine to stream ADC conversions and results.
+**/
+void AdcManager::DmaUpdate() {
+    // Start channel
+    DmaManager::Channel(DMA_ADC_RESULTS)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+    DmaManager::Channel(DMA_ADC_SEQUENCE)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+    // Restart the DMA sequence to the ADC
+    ADC1->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP;
+}
+
+bool AdcManager::AdcResolution(uint8_t resolution) {
+    switch (resolution) {
+        case 8:
+        case 10:
+        case 12:
+            m_AdcResPending = resolution;
+            break;
+        // 16 bit is not supported
+        default:
+            // Invalid value
+            return false;
+    }
+    // Wait for the change to be applied in the interrupt
+    while (m_AdcResPending != AdcResolution()) {
+        continue;
+    }
+    return true;
+}
+
+bool AdcManager::AdcResChange() {
+    switch (m_AdcResPending) {
+        case 8:
+            ADC1->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_8BIT_Val;
+            break;
+        case 10:
+            ADC1->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_10BIT_Val;
+            break;
+        case 12:
+            ADC1->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_12BIT_Val;
+            break;
+        // 16 bit is not supported
+        default:
+            // Invalid value
+            return false;
+    }
+
+    m_AdcResolution = m_AdcResPending;
+
+    return true;
+}
+
+bool AdcManager::FilterTc(AdcChannels adcChannel,
+                          uint16_t tc,
+                          FilterUnits theUnits) {
+    if (adcChannel >= ADC_CHANNEL_COUNT) {
+        return false;
+    }
+
+    switch (theUnits) {
+        case AdcManager::FilterUnits::FILTER_UNIT_RAW:
+            m_analogFilter[adcChannel].Tc(tc);
+            return true;
+        case AdcManager::FilterUnits::FILTER_UNIT_MS:
+            m_analogFilter[adcChannel].Tc_ms(tc);
+            return true;
+        case AdcManager::FilterUnits::FILTER_UNIT_SAMPLES:
+            m_analogFilter[adcChannel].TcSamples(tc);
+            return true;
+        default:
+            // Error
+            return false;
+    }
+}
+
+uint16_t AdcManager::FilterTc(AdcChannels adcChannel,
+                              FilterUnits theUnits) {
+    if (adcChannel >= ADC_CHANNEL_COUNT) {
+        return false;
+    }
+
+    switch (theUnits) {
+        case AdcManager::FilterUnits::FILTER_UNIT_RAW:
+            return m_analogFilter[adcChannel].Tc();
+        case AdcManager::FilterUnits::FILTER_UNIT_MS:
+            return m_analogFilter[adcChannel].Tc_ms();
+        case AdcManager::FilterUnits::FILTER_UNIT_SAMPLES:
+            return m_analogFilter[adcChannel].TcSamples();
+        default:
+            // Error
+            return 0;
+    }
+}
+
+#ifdef DEBUG_ADC_RESULT_TIMING
+
+extern "C" void DMAC_0_Handler() {
+    // DMAC interrupts TERR TCMPL SUSP
+    DmaManager::Channel(DMA_ADC_RESULTS)->CHINTFLAG.reg =
+        DMAC_CHINTENCLR_TCMPL; // clear interrupt
+}
+#endif
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/BlinkCodeDriver.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/BlinkCodeDriver.cpp
new file mode 100644
index 000000000..8d9cd32e3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/BlinkCodeDriver.cpp
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Status blink code driver implementation
+
+    This class provides a state machine that manages displaying multiple status
+    codes via a group / code blink pattern.
+**/
+
+#include "BlinkCodeDriver.h"
+
+namespace ClearCore {
+
+void BlinkCodeDriver::Update() {
+    switch (m_blinkState) {
+        case IDLE:
+            // Check if there is an active blink group that needs to be started
+            if (!NextCode(0, 0)) {
+                break;
+            }
+            m_timer = m_prestartTicks;
+            m_ledOn = false;
+            m_blinkState = PRE_START_DELAY;
+            break;
+
+        case PRE_START_DELAY:
+            if (--m_timer) {
+                // Still waiting
+                break;
+            }
+            m_patternWrap = false;
+            m_strobeCnt = m_startTicks / m_strobeOnOffTicks;
+            m_timer = m_strobeOnOffTicks;
+            m_ledOn = true;
+            m_blinkState = START_OUTPUT;
+            break;
+
+        case START_OUTPUT:
+            if (--m_timer) {
+                // Strobe value is still active
+                break;
+            }
+            m_ledOn = !m_ledOn;
+            if (--m_strobeCnt) {
+                m_timer = m_strobeOnOffTicks;
+                // More strobe pulses to send
+                break;
+            }
+            m_timer = m_pregroupTicks;
+            m_ledOn = false;
+            m_blinkState = PRE_GROUP_DELAY;
+            break;
+
+        case PRE_GROUP_DELAY:
+            if (--m_timer) {
+                // Still waiting
+                break;
+            }
+            m_blinkCnt = m_currentGroup + 1;
+            m_strobeCnt = m_blinkTicks / m_strobeOnOffTicks;
+            m_timer = m_strobeOnOffTicks;
+            m_ledOn = true;
+            m_blinkState = GROUP_OUTPUT;
+            break;
+
+        case GROUP_OUTPUT:
+            if (--m_timer) {
+                // Strobe value is still active
+                break;
+            }
+            m_ledOn = !m_ledOn;
+            if (--m_strobeCnt) {
+                m_timer = m_strobeOnOffTicks;
+                // More strobe pulses to send
+                break;
+            }
+            m_timer = m_blinkTicks;
+            m_ledOn = false;
+            m_blinkState = GROUP_DELAY;
+            break;
+
+        case GROUP_DELAY:
+            if (--m_timer) {
+                // Still waiting
+                break;
+            }
+            if (--m_blinkCnt) {
+                // Output the next strobe blink for the group
+                m_strobeCnt = m_blinkTicks / m_strobeOnOffTicks;
+                m_timer = m_strobeOnOffTicks;
+                m_ledOn = true;
+                m_blinkState = GROUP_OUTPUT;
+                break;
+            }
+            m_timer = m_precodeTicks;
+            m_ledOn = false;
+            m_blinkState = PRE_CODE_DELAY;
+            break;
+
+        case PRE_CODE_DELAY:
+            if (--m_timer) {
+                // Still waiting
+                break;
+            }
+            m_blinkCnt = m_currentCode + 1;
+            m_timer = m_blinkTicks;
+            m_ledOn = true;
+            m_blinkState = CODE_OUTPUT;
+            break;
+
+        case CODE_OUTPUT:
+            if (--m_timer) {
+                // Code value is still active
+                break;
+            }
+            m_timer = m_blinkTicks;
+            m_ledOn = false;
+            m_blinkState = CODE_DELAY;
+            break;
+
+        case CODE_DELAY:
+            if (--m_timer) {
+                // Still waiting
+                break;
+            }
+            if (--m_blinkCnt) {
+                // Output the next strobe blink for the group
+                m_timer = m_blinkTicks;
+                m_ledOn = true;
+                m_blinkState = CODE_OUTPUT;
+                break;
+            }
+            if (!NextCode(m_currentGroup, m_currentCode + 1)) {
+                m_ledOn = false;
+                m_blinkState = IDLE;
+            }
+            else if (m_patternWrap) {
+                m_timer = m_prestartTicks;
+                m_ledOn = false;
+                m_blinkState = PRE_START_DELAY;
+            }
+            else {
+                m_timer = m_pregroupTicks;
+                m_ledOn = false;
+                m_blinkState = PRE_GROUP_DELAY;
+            }
+            break;
+    }
+}
+
+bool BlinkCodeDriver::NextCode(uint8_t group, uint8_t code) {
+    // Bounds check the parameters and adjust accordingly
+    if (code > 7) {
+        code = 0;
+        group++;
+    }
+    if (group >= BLINK_GROUP_MAX) {
+        group = 0;
+        m_patternWrap = true;
+    }
+    if (!(m_codes[group] >> code)) {
+        // There is not an active code within the current group
+        // Search for the next group with an active code
+        code = 0;
+        uint8_t iGroup;
+        // Search from the next index up to the maximum group index
+        for (iGroup = group + 1; iGroup < BLINK_GROUP_MAX; iGroup++) {
+            if (m_codes[iGroup]) {
+                // Found an active group
+                break;
+            }
+        }
+        if (iGroup >= BLINK_GROUP_MAX) {
+            // Now search the groups from 0 up to the current index
+            for (iGroup = 0; iGroup <= group; iGroup++) {
+                if (m_codes[iGroup]) {
+                    // Found an active group
+                    break;
+                }
+            }
+            if (iGroup > group) {
+                // No active group codes found
+                return false;
+            }
+            m_patternWrap = true;
+        }
+        // Set the index of the next active group found
+        group = iGroup;
+    }
+    // There is an active code within group, find out the code value
+    // Set the first group/code pair to output
+    for (; !(m_codes[group] & (1 << code)); code++) {
+        continue;
+    }
+    m_currentGroup = group;
+    m_currentCode = code;
+    return true;
+}
+
+void BlinkCodeDriver::BlinkCodeClear(uint8_t group, uint8_t code) {
+    if (code == 0 || code > 8) {
+        return; // Not a valid code.
+    }
+    if (group == 0 || group > BLINK_GROUP_MAX) {
+        return; // Not a valid group.
+    }
+
+    m_codes[group - 1] &= ~(1UL << (code - 1));
+}
+
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/CcioBoardManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/CcioBoardManager.cpp
new file mode 100644
index 000000000..037270628
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/CcioBoardManager.cpp
@@ -0,0 +1,691 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ClearCore CCIO-8 manager class implementation.
+**/
+
+#include "CcioBoardManager.h"
+#include <stddef.h>
+#include "SerialBase.h"
+#include "SerialDriver.h"
+#include "ShiftRegister.h"
+#include "SysConnectors.h"
+#include "StatusManager.h"
+#include "SysTiming.h"
+
+namespace ClearCore {
+
+extern ShiftRegister ShiftReg;
+extern StatusManager &StatusMgr;
+extern volatile uint32_t tickCnt;
+CcioBoardManager &CcioMgr = CcioBoardManager::Instance();
+
+#define MARKER_BYTE (0xCC)
+#define CCIO_REDISCOVER_TIME_TICKS (1000 * MS_TO_SAMPLES)
+
+#if MAX_CCIO_DEVICES != 8
+#error "MAX_CCIO_DEVICES has changed. CcioIoBuf setup needs updating."
+#endif
+
+/**
+    Modifies a specific bit in originalNumber at position to be
+    the value specified by finalBitValue.
+    \note position = 0 modifies LSB
+
+    \param[in] originalNumber Number to be modified
+    \param[in] position Index of the bit to be modified
+    \param[in] finalBitValue New value of the bit at the given position
+    \return Modified number
+**/
+inline uint64_t modifyBit(uint64_t originalNumber, uint8_t position,
+                          bool finalBitValue) {
+    uint64_t mask = 1ULL << position;
+    // First clear the bit at position, then OR it with the desired value.
+    return (originalNumber & ~mask) |
+           (static_cast<uint64_t>(finalBitValue) << position);
+}
+
+/**
+    Reverses the bytes of the given 32-bit value
+
+    \param[in] value Number to be swapped
+    \return Swapped value
+**/
+inline uint32_t reverseBytes(uint32_t value) {
+    uint32_t res = 0;
+    __asm("REV %[result], %[input]" : [result] "=r"(res) : [input] "r"(value));
+    return res;
+}
+
+CcioBoardManager &CcioBoardManager::Instance() {
+    static CcioBoardManager *instance = new CcioBoardManager();
+    return *instance;
+}
+
+#ifndef HIDE_FROM_DOXYGEN
+CcioBoardManager::CcioBoardManager()
+    : m_writeBuf(),
+      m_readBuf(),
+      m_discoverState(CCIO_SEARCH),
+      m_serPort(NULL),
+      m_ccioCnt(0),
+      m_ccioRefreshRate(1),
+      m_ccioRefreshDelay(0),
+      m_throttledOutputs(0),
+      m_currentInputs(0),
+      m_filteredInputs(0),
+      m_currentOutputs(0),
+      m_outputMask(0),
+      m_lastOutputsSwapped(~0),
+      m_lastOutputs(0),
+      m_outputsWithThrottling(0),
+      m_ccioMask(0),
+      m_pulseActive(0),
+      m_pulseValue(0),
+      m_pulseStopPending(0),
+      m_consGlitchCnt(0),
+      m_ccioLinkBroken(false),
+      m_ccioOverloaded(0),
+      m_ccioOverloadAccum(0),
+      m_overloadSinceStartupAccum(0),
+      m_inputRegRisen(0),
+      m_inputRegFallen(0),
+      m_faultLed(ShiftRegister::SR_NO_FEEDBACK_MASK),
+      m_autoRediscover(true),
+      m_lastDiscoverTime(0) {
+}
+#endif
+
+void CcioBoardManager::Initialize() {
+    for (uint8_t i = 0; i < CCIO_PIN_CNT; i++) {
+        m_ccioPins[i].Initialize((ClearCorePins)(i + CLEARCORE_PIN_CCIO_BASE));
+    }
+    CcioDiscover(NULL);
+
+    m_ccioCnt = 0;
+    m_ccioMask = 0;
+    m_ccioRefreshRate = 1;
+    m_ccioRefreshDelay = 0;
+    m_throttledOutputs = 0;
+    m_currentInputs = 0;
+    m_filteredInputs = 0;
+    m_currentOutputs = 0;
+    m_outputMask = 0;
+    m_lastOutputsSwapped = ~0ULL;
+    m_lastOutputs = 0;
+    m_outputsWithThrottling = 0;
+    m_ccioMask = 0;
+    m_pulseActive = 0;
+    m_pulseValue = 0;
+    m_pulseStopPending = 0;
+    m_consGlitchCnt = 0;
+    m_ccioLinkBroken = false;
+    m_ccioOverloaded = 0;
+    m_ccioOverloadAccum = 0;
+    m_inputRegRisen = 0;
+    m_inputRegFallen = 0;
+    m_autoRediscover = true;
+}
+
+bool CcioBoardManager::PinState(ClearCorePins pinNum) {
+    if (pinNum < CLEARCORE_PIN_CCIO_BASE || pinNum >= CLEARCORE_PIN_CCIO_MAX) {
+        return false;
+    }
+
+    // Reposition the pin reference to map it into a shift amount
+    int8_t bitIndex = pinNum - CLEARCORE_PIN_CCIO_BASE;
+    return ((m_filteredInputs >> bitIndex) & 1);
+}
+
+uint64_t CcioBoardManager::InputsRisen(uint64_t mask) {
+    uint64_t retVal;
+    // Block the interrupt while performing the clear on read masking
+    __disable_irq();
+    retVal = m_inputRegRisen & mask;
+    m_inputRegRisen &= ~mask;
+    __enable_irq();
+    return retVal;
+}
+
+uint64_t CcioBoardManager::InputsFallen(uint64_t mask) {
+    uint64_t retVal;
+    // Block the interrupt while performing the clear on read masking
+    __disable_irq();
+    retVal = m_inputRegFallen & mask;
+    m_inputRegFallen &= ~mask;
+    __enable_irq();
+    return retVal;
+}
+
+uint64_t CcioBoardManager::IoOverloadAccum() {
+    uint64_t retVal;
+    // Block the interrupt while performing the clear on read masking
+    __disable_irq();
+    retVal = m_ccioOverloadAccum;
+    m_ccioOverloadAccum = m_ccioOverloaded;
+    __enable_irq();
+    return retVal;
+}
+
+void CcioBoardManager::Refresh() {
+    // Don't refresh until CcioDiscover is called
+    if (!m_serPort || !m_ccioCnt || m_ccioLinkBroken) {
+        return;
+    }
+
+    uint64_t mask = 1;
+
+    // Refresh pulse counts when pulses are active
+    if (m_pulseActive) {
+        uint64_t pulsesEnded = 0;
+        uint64_t pulseRise = 0;
+        uint64_t pulseFall = 0;
+
+        for (uint8_t i = 0; i < CCIO_PINS_PER_BOARD * m_ccioCnt; i++) {
+            // Pulse out update
+            if (m_pulseActive & mask) {
+                CcioPin &currentPin = m_ccioPins[i];
+                if (!--currentPin.m_pulseTicksRemaining) {
+                    if (m_pulseValue & mask) {
+                        // Turn off the pulse
+                        pulseFall |= mask;
+                        currentPin.m_pulseTicksRemaining =
+                            currentPin.m_pulseOffTicks;
+                        // Increment the counter after a complete cycle
+                        if (++currentPin.m_pulseCounter >=
+                                currentPin.m_pulseStopCount &&
+                                currentPin.m_pulseStopCount) {
+                            pulsesEnded |= mask;
+                        }
+                        // If a stop is pending, handle it now that a cycle has
+                        // completed
+                        if (m_pulseStopPending & mask) {
+                            pulsesEnded |= mask;
+                            m_pulseStopPending &= ~mask;
+                        }
+                    }
+                    else {
+                        // If a stop is pending, stop any upcoming pulses
+                        if (m_pulseStopPending & mask) {
+                            pulsesEnded |= mask;
+                            m_pulseStopPending &= ~mask;
+                        }
+                        else {
+                            // Turn on the pulse
+                            pulseRise |= mask;
+                            currentPin.m_pulseTicksRemaining =
+                                currentPin.m_pulseOnTicks;
+                        }
+                    }
+                }
+            }
+            mask <<= 1;
+        }
+
+        // Update the pulse info with the bits that changed
+        m_pulseActive &= ~pulsesEnded;
+        m_pulseValue = (m_pulseValue | pulseRise) & ~pulseFall;
+        // currentOutputs are inverted from display
+        m_currentOutputs = (m_currentOutputs | pulseRise) & ~pulseFall;
+    }
+
+    // Bail out unless the refresh delay has timed out
+    if (--m_ccioRefreshDelay) {
+        return;
+    }
+    else {
+        // Reset delay
+        m_ccioRefreshDelay = m_ccioRefreshRate;
+    }
+
+    // Wait for the previous SPI transfer to complete
+    m_serPort->SpiAsyncWaitComplete();
+    m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_OFF);
+
+    // Save the current inputs and the last inputs
+    uint64_t lastInputs = m_currentInputs;
+
+    bool markerError =
+        m_readBuf.buf8[MAX_CCIO_DEVICES + m_ccioCnt + 1] != MARKER_BYTE;
+    m_readBuf.buf8[MAX_CCIO_DEVICES + m_ccioCnt + 1] = 0;
+    // Verify that the data read back matches what we had sent
+    if (markerError || m_lastOutputsSwapped ^ m_readBuf.buf64.outputsSwapped) {
+        if ((m_consGlitchCnt++ >= MAX_GLITCH_LIM) && (MAX_GLITCH_LIM > 0)) {
+            // Announce link broken
+            m_ccioLinkBroken = true;
+            m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_ON);
+            m_ccioOverloaded = 0;
+            StatusMgr.BlinkCode(
+                BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+                BlinkCodeDriver::DEVICE_ERROR_CCIO);
+            ShiftReg.LedInFault(m_faultLed, false);
+            ShiftReg.LedPattern(m_faultLed,
+                                ShiftRegister::LED_BLINK_CCIO_ONLINE,
+                                false);
+            // We're offline now, bail out
+            return;
+        }
+    }
+    else {
+        m_consGlitchCnt = 0;
+        m_currentInputs =
+            (~m_readBuf.buf64.inputs) >> ((MAX_CCIO_DEVICES - m_ccioCnt)
+                                          * CCIO_PINS_PER_BOARD);
+    }
+
+    mask = 1;
+    uint64_t settledChanges = 0;
+    uint64_t changedInputs = lastInputs ^ m_currentInputs;
+    uint64_t overloadedOutputSample = m_outputsWithThrottling & ~lastInputs;
+    uint64_t overloadedOutputRT = m_ccioOverloaded;
+    for (uint8_t i = 0; i < CCIO_PINS_PER_BOARD * m_ccioCnt; i++) {
+        CcioPin &currentPin = m_ccioPins[i];
+        if (m_throttledOutputs & mask) {
+            if (!(--currentPin.m_overloadFoldbackCnt)) {
+                // Coming out of foldback, reset the overload
+                // delay timer and restore the pin state
+                m_throttledOutputs &= ~mask;
+                currentPin.m_overloadTripCnt = CCIO_OVERLOAD_TRIP_TICKS;
+            }
+        }
+        // Read filtering update
+        else if (overloadedOutputSample & mask) {
+            // When the overload counter hits zero, signal the overload
+            if (currentPin.m_overloadTripCnt &&
+                    !--currentPin.m_overloadTripCnt) {
+                m_throttledOutputs |= mask;
+                currentPin.m_overloadFoldbackCnt = CCIO_OVERLOAD_FOLDBACK_TICKS;
+                overloadedOutputRT |= mask;
+            }
+        }
+        else {
+            // Not overloaded, reset the overload delay timer
+            currentPin.m_overloadTripCnt = CCIO_OVERLOAD_TRIP_TICKS;
+            overloadedOutputRT &= ~mask;
+        }
+
+        if (changedInputs & mask) {
+            currentPin.m_filterTicksLeft = currentPin.m_filterLength;
+            if (!currentPin.m_filterLength) {
+                settledChanges |= mask;
+            }
+        }
+        else if (currentPin.m_filterTicksLeft &&
+                 !(--currentPin.m_filterTicksLeft)) {
+            // When we decrement to zero, set the filtered state
+            settledChanges |= mask;
+        }
+        mask <<= 1;
+    }
+
+    // Update the filtered input value with the bits that changed
+    lastInputs = m_filteredInputs;
+    // If filtering, update the values that settled this sample
+    m_filteredInputs = (m_filteredInputs & ~settledChanges) |
+                       (m_currentInputs & settledChanges);
+    // Find the rise/fall
+    m_inputRegRisen |= (m_filteredInputs & ~lastInputs);
+    m_inputRegFallen |= (~m_filteredInputs & lastInputs);
+
+    // Output overloaded check if there wasn't a glitch
+    if (m_consGlitchCnt == 0) {
+        // There is an overload if the output was "asserted" and
+        // the input was "deasserted", or the output is throttling
+        // due to a previous overload condition.
+        IoOverloadRT(overloadedOutputRT & m_ccioMask);
+    }
+
+    // Store the last outputs that had been sent for glitch comparison
+    m_lastOutputsSwapped = m_writeBuf.buf64.outputsSwapped;
+    m_lastOutputs = m_currentOutputs;
+
+    // Put the current outputs in the write buffer
+    // Do not assert any bits that are inputs or throttled outputs
+    m_outputsWithThrottling =
+        m_currentOutputs & ~m_throttledOutputs & m_outputMask;
+    // Outputs are written in reverse byte order so the last byte written
+    // corresponds to the first CCIO-8 in the chain
+    uint64_t outputSwapped =
+        ~((static_cast<uint64_t>(reverseBytes(
+                                     static_cast<uint32_t>(m_outputsWithThrottling))) << 32) |
+          reverseBytes(static_cast<uint32_t>(m_outputsWithThrottling >> 32)));
+    m_writeBuf.buf64.outputsSwapped =
+        outputSwapped >> ((MAX_CCIO_DEVICES - m_ccioCnt) * CCIO_PINS_PER_BOARD);
+    m_writeBuf.buf8[(MAX_CCIO_DEVICES - m_ccioCnt)] = MARKER_BYTE;
+    // Start the SPI transfer
+    m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_ON);
+    m_serPort->SpiTransferDataAsync(
+        m_writeBuf.buf8 + (MAX_CCIO_DEVICES - m_ccioCnt),
+        m_readBuf.buf8 + (MAX_CCIO_DEVICES - m_ccioCnt) + 1, 2 * m_ccioCnt + 1);
+}
+
+void CcioBoardManager::RefreshSlow() {
+    if (m_serPort && LinkBroken() && m_autoRediscover &&
+            tickCnt - m_lastDiscoverTime > CCIO_REDISCOVER_TIME_TICKS) {
+        // Reset the discover state and try to remake the broken link network
+        m_discoverState = CCIO_SEARCH;
+        CcioDiscover(m_serPort);
+    }
+}
+
+void CcioBoardManager::IoOverloadRT(uint64_t overloadState) {
+    // OR the current overload state into the accum
+    m_ccioOverloadAccum |= overloadState;
+
+    // No change, just return
+    if (m_ccioOverloaded == overloadState) {
+        return;
+    }
+    m_ccioOverloaded = overloadState;
+    ShiftReg.LedInFault(m_faultLed, overloadState);
+
+    // If there are overload bits set that have not previously been flagged
+    // update the since startup overload register and the blink codes
+    if (overloadState & ~m_overloadSinceStartupAccum) {
+        m_overloadSinceStartupAccum |= overloadState;
+        // Any bits in the accum have the appropriate blink already running
+        // We just need to add the blinks for the new overloads
+        uint8_t *charPtr = (uint8_t *)&overloadState;
+        for (uint8_t i = 0; i < m_ccioCnt; i++) {
+            if (charPtr[i]) {
+                StatusMgr.BlinkCode(
+                    BlinkCodeDriver::BLINK_GROUP_CCIO_OVERLOAD, 1 << i);
+            }
+        }
+    }
+}
+
+void CcioBoardManager::PinState(ClearCorePins pinNum, bool newState) {
+    if (pinNum < CLEARCORE_PIN_CCIO_BASE || pinNum >= CLEARCORE_PIN_CCIO_MAX) {
+        return;
+    }
+
+    // Reposition the pin reference to work correctly with masking
+    uint32_t bitNum = static_cast<uint32_t>(pinNum - CLEARCORE_PIN_CCIO_BASE);
+
+    // Toggle the bit here and flush change in Refresh
+    m_currentOutputs = modifyBit(m_currentOutputs, bitNum, newState);
+}
+
+void CcioBoardManager::OutputPulsesStart(ClearCorePins pinNum, uint32_t onTime,
+        uint32_t offTime, uint16_t pulseCount,
+        bool blockUntilDone) {
+    if (pinNum < CLEARCORE_PIN_CCIO_BASE || pinNum >= CLEARCORE_PIN_CCIO_MAX) {
+        return;
+    }
+    if (onTime == 0 || offTime == 0) {
+        return;
+    }
+    // Reposition the pin reference to work correctly with masking
+    pinNum = static_cast<ClearCorePins>(pinNum - CLEARCORE_PIN_CCIO_BASE);
+    uint64_t pinMask = 1ULL << pinNum;
+    // Do not start output pulses if we are in input mode
+    if (!(pinMask & m_outputMask)) {
+        return;
+    }
+    CcioPin &currentPin = m_ccioPins[pinNum];
+    currentPin.m_pulseCounter = 0;
+    currentPin.m_pulseStopCount = pulseCount;
+    currentPin.m_pulseOnTicks = onTime * MS_TO_SAMPLES;
+    currentPin.m_pulseOffTicks = offTime * MS_TO_SAMPLES;
+
+    if (!(m_pulseActive & pinMask)) {
+        currentPin.m_pulseTicksRemaining = currentPin.m_pulseOnTicks;
+        m_pulseActive |= pinMask;
+        m_pulseValue |= pinMask;
+        // If a previous stop was pending, cancel it
+        m_pulseStopPending &= ~pinMask;
+        // Turn on the output directly
+        m_currentOutputs |= pinMask;
+    }
+
+    if (blockUntilDone && pulseCount != 0) {
+        while (OutputPulsesActive() & pinMask) {
+            continue;
+        }
+    }
+}
+
+void CcioBoardManager::LinkClose() {
+    m_discoverState = CCIO_SEARCH;
+    ShiftReg.LedPattern(m_faultLed, ShiftRegister::LED_BLINK_CCIO_COMM_ERR,
+                        false);
+    ShiftReg.LedInFault(m_faultLed, m_ccioOverloaded);
+    Initialize();
+}
+
+void CcioBoardManager::OutputPulsesStop(ClearCorePins pinNum,
+                                        bool stopImmediately) {
+    ClearCorePins ccioPinNum;
+    if (pinNum < CLEARCORE_PIN_CCIO_BASE || pinNum >= CLEARCORE_PIN_CCIO_MAX) {
+        return;
+    }
+    // Reposition the pin reference to work correctly with masking
+    ccioPinNum = static_cast<ClearCorePins>(pinNum - CLEARCORE_PIN_CCIO_BASE);
+
+    uint64_t pinMask = 1ULL << ccioPinNum;
+    if (stopImmediately) {
+        m_pulseActive &= ~pinMask;
+        // Turn off the output directly
+        m_currentOutputs &= ~pinMask;
+    }
+    else {
+        m_pulseStopPending |= pinMask;
+    }
+}
+
+uint8_t CcioBoardManager::CcioDiscover(SerialDriver *comInstance) {
+    // Ignore calls to this function if the link has been built and is healthy
+    if (m_discoverState == CCIO_FOUND || (LinkBroken() && !m_autoRediscover)) {
+        return m_ccioCnt;
+    }
+
+    uint8_t numFound = 0;
+    uint8_t flushCnt = 0;
+    bool sendData = true;
+    bool flush0Success = false;
+
+    m_serPort = comInstance;
+    if (!m_serPort) {
+        m_faultLed = ShiftRegister::Masks::SR_NO_FEEDBACK_MASK;
+        m_lastDiscoverTime = tickCnt;
+        return 0;
+    }
+
+    m_faultLed = m_serPort->m_ledMask;
+
+    m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_ON);
+    while (m_discoverState != CCIO_FOUND) {
+        // Fail after too many attempts
+        if (flushCnt >= MAX_FLUSH_ATTEMPTS) {
+            m_ccioLinkBroken = true;
+            StatusMgr.BlinkCode(
+                BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+                BlinkCodeDriver::DEVICE_ERROR_CCIO);
+            ShiftReg.LedPattern(m_faultLed,
+                                ShiftRegister::LED_BLINK_CCIO_ONLINE,
+                                false);
+            m_lastDiscoverTime = tickCnt;
+            return 0;
+        }
+
+        switch (m_discoverState) {
+            case CCIO_SEARCH:
+                if (sendData) {
+                    // Flush with 1's
+                    FillBuffer(m_writeBuf.buf8, 2 * MAX_CCIO_DEVICES, 0xff);
+                    m_serPort->SpiTransferData(m_writeBuf.buf8, m_readBuf.buf8,
+                                               2 * MAX_CCIO_DEVICES);
+                    sendData = false;
+                }
+                else {
+                    // Check if any 1's got through, otherwise resend 1s
+                    if (!AllEntriesEqual(m_readBuf.buf8,
+                                         2 * MAX_CCIO_DEVICES, 0)) {
+                        m_discoverState = CCIO_TEST;
+                        flushCnt = 0;
+                        flush0Success = false;
+                    }
+                    flushCnt++;
+                    sendData = true;
+                }
+                break;
+            case CCIO_TEST:
+                if (sendData) {
+                    if (!flush0Success) {
+                        // Attempt to flush with 0's
+                        FillBuffer(m_writeBuf.buf8, 2 * MAX_CCIO_DEVICES, 0);
+                        m_serPort->SpiTransferData(m_writeBuf.buf8,
+                                                   m_readBuf.buf8,
+                                                   2 * MAX_CCIO_DEVICES);
+                    }
+                    else {
+                        // Flush with a's, send extra byte to check for too many
+                        // CCIOs
+                        FillBuffer(m_writeBuf.buf8,
+                                   2 * MAX_CCIO_DEVICES + 1, 0xaa);
+                        m_serPort->SpiTransferData(m_writeBuf.buf8,
+                                                   m_readBuf.buf8,
+                                                   2 * MAX_CCIO_DEVICES + 1);
+                    }
+                    sendData = false;
+                }
+                else {
+                    if (!flush0Success) {
+                        // If 0's got through, try again with a's; otherwise
+                        // resend 0's.
+                        if (!AllEntriesEqual(m_readBuf.buf8,
+                                             2 * MAX_CCIO_DEVICES, 0xff)) {
+                            flush0Success = true;
+                        }
+                        flushCnt++;
+                    }
+                    else {
+                        uint8_t i;
+                        bool foundAA = false;
+                        // Count until we see a's
+                        for (i = 0; i < 2 * MAX_CCIO_DEVICES && !foundAA; i++) {
+                            if (m_readBuf.buf8[i] == 0xaa) {
+                                foundAA = true;
+                            }
+                            else {
+                                numFound++;
+                            }
+                        }
+                        if (!foundAA &&
+                                m_readBuf.buf8[2 * MAX_CCIO_DEVICES] != 0xaa) {
+                            // Error state - too many CCIOs
+                            m_ccioCnt = 0;
+                            m_ccioMask = 0;
+                            m_ccioRefreshRate = RefreshRate();
+                            m_ccioLinkBroken = true;
+                            StatusMgr.BlinkCode(
+                                BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+                                BlinkCodeDriver::DEVICE_ERROR_CCIO);
+                            ShiftReg.LedPattern(m_faultLed,
+                                                ShiftRegister::LED_BLINK_CCIO_ONLINE,
+                                                false);
+                            m_lastDiscoverTime = tickCnt;
+                            return 0;
+                        }
+                        // Break from loop
+                        m_discoverState = CCIO_FOUND;
+                        m_readBuf.Clear();
+                    }
+                    sendData = true;
+                }
+                break;
+            default:
+                break;
+        }
+    }
+
+    // numFound is the number of input and output regs found
+    // so divide by 2 to get CCIO-8 count
+    numFound >>= 1;
+    m_ccioCnt = numFound;
+    m_ccioMask = (1 << (m_ccioCnt * CCIO_PINS_PER_BOARD)) - 1;
+    m_ccioRefreshRate = RefreshRate();
+
+    if (numFound != 0) {
+        // Store the last outputs that had been sent for glitch comparison
+        m_lastOutputsSwapped =
+            UINT64_MAX >> ((MAX_CCIO_DEVICES - m_ccioCnt) *
+                           CCIO_PINS_PER_BOARD);
+
+        // Clear the outputs so that the CCIOs initialize cleanly
+        m_writeBuf.Clear();
+        m_writeBuf.buf64.outputsSwapped =
+            UINT64_MAX >> ((MAX_CCIO_DEVICES - m_ccioCnt) *
+                           CCIO_PINS_PER_BOARD);
+        m_writeBuf.buf8[MAX_CCIO_DEVICES] = MARKER_BYTE;
+
+        // Start the SPI transfer
+        m_serPort->SpiTransferData(m_writeBuf.buf8 +
+                                   (MAX_CCIO_DEVICES - m_ccioCnt),
+                                   m_readBuf.buf8 +
+                                   (MAX_CCIO_DEVICES - m_ccioCnt) + 1,
+                                   2 * m_ccioCnt + 1);
+        m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_OFF);
+        m_writeBuf.buf8[(MAX_CCIO_DEVICES - m_ccioCnt)] = MARKER_BYTE;
+        m_writeBuf.buf8[MAX_CCIO_DEVICES] = 0;
+        m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_ON);
+        m_serPort->SpiTransferData(m_writeBuf.buf8 +
+                                   (MAX_CCIO_DEVICES - m_ccioCnt),
+                                   m_readBuf.buf8 +
+                                   (MAX_CCIO_DEVICES - m_ccioCnt) + 1,
+                                   2 * m_ccioCnt + 1);
+        m_serPort->SpiSsMode(SerialBase::CtrlLineModes::LINE_OFF);
+
+        // We are now online and initialized
+        m_ccioRefreshDelay = m_ccioRefreshRate;
+        m_consGlitchCnt = 0;
+        m_ccioOverloaded = 0;
+        m_ccioLinkBroken = false;
+        ShiftReg.LedInFault(m_faultLed, m_ccioOverloaded);
+    }
+
+    ShiftReg.LedPattern(m_faultLed,
+                        ShiftRegister::LED_BLINK_CCIO_ONLINE,
+                        !m_ccioLinkBroken && !m_ccioOverloaded &&
+                        (numFound > 0));
+
+    m_lastDiscoverTime = tickCnt;
+    return numFound;
+}
+
+void CcioBoardManager::CcioRediscoverEnable(bool enable) {
+    m_autoRediscover = enable;
+}
+
+CcioPin *CcioBoardManager::PinByIndex(ClearCorePins connectorIndex) {
+    if (connectorIndex >= ClearCorePins::CLEARCORE_PIN_CCIO_BASE &&
+            connectorIndex < ClearCorePins::CLEARCORE_PIN_CCIO_MAX) {
+        return &m_ccioPins[connectorIndex - CLEARCORE_PIN_CCIO_BASE];
+    }
+    else {
+        return NULL;
+    }
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/CcioPin.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/CcioPin.cpp
new file mode 100644
index 000000000..8636e11ea
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/CcioPin.cpp
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Connector class for controlling a CCIO-8 pin
+
+    This manages a CCIO-8 input/output connector on the ClearCore board.
+**/
+
+#include "CcioPin.h"
+#include <sam.h>
+#include "CcioBoardManager.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+extern CcioBoardManager &CcioMgr;
+
+CcioPin::CcioPin()
+    : Connector(),
+      m_dataBit(0),
+      m_filterLength(3),
+      m_filterTicksLeft(1),
+      m_overloadTripCnt(CCIO_OVERLOAD_TRIP_TICKS),
+      m_overloadFoldbackCnt(0),
+      m_pulseOnTicks(0),
+      m_pulseOffTicks(0),
+      m_pulseTicksRemaining(0),
+      m_pulseStopCount(0),
+      m_pulseCounter(0) {}
+
+
+void CcioPin::Initialize(ClearCorePins ccioPin) {
+    m_clearCorePin = ccioPin;
+    m_dataBit = 1ULL << (ccioPin - CLEARCORE_PIN_CCIO_BASE);
+    m_mode = ConnectorModes::INPUT_DIGITAL;
+    m_filterLength = 3;
+    m_filterTicksLeft = 1;
+    m_overloadTripCnt = CCIO_OVERLOAD_TRIP_TICKS;
+    m_overloadFoldbackCnt = 0;
+    m_pulseOnTicks = 0;
+    m_pulseOffTicks = 0;
+    m_pulseTicksRemaining = 0;
+    m_pulseStopCount = 0;
+    m_pulseCounter = 0;
+}
+
+bool CcioPin::Mode(ConnectorModes newMode) {
+    // Bail out if we are already in the requested mode
+    if (newMode == m_mode) {
+        return true;
+    }
+
+    switch (newMode) {
+        // Set up as output
+        case OUTPUT_DIGITAL:
+            CcioMgr.m_outputMask |= m_dataBit;
+            m_mode = newMode;
+            break;
+        // Set up as input
+        case INPUT_DIGITAL:
+            CcioMgr.m_outputMask &= ~m_dataBit;
+            CcioMgr.m_pulseActive &= ~m_dataBit;
+            m_mode = newMode;
+            break;
+        // Unsupported mode, don't change anything
+        default:
+            break;
+    }
+    return m_mode == newMode;
+}
+
+int16_t CcioPin::State() {
+    bool state = false;
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+            state = CcioMgr.m_currentOutputs & m_dataBit;
+            break;
+        case INPUT_DIGITAL:
+            state = CcioMgr.m_filteredInputs & m_dataBit;
+            break;
+        default:
+            break;
+    }
+
+    return state;
+}
+
+bool CcioPin::State(int16_t newState) {
+    bool success = false;
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+            if (newState) {
+                CcioMgr.m_currentOutputs |= m_dataBit;
+            }
+            else {
+                CcioMgr.m_currentOutputs &= ~m_dataBit;
+            }
+            success = true;
+            break;
+        case INPUT_DIGITAL:
+        default:
+            break;
+    }
+
+    return success;
+}
+
+void CcioPin::Filter_ms(uint16_t len) {
+    uint32_t samples =
+        static_cast<uint32_t>(len) * MS_TO_SAMPLES / CcioMgr.m_ccioRefreshRate;
+    if (samples > UINT16_MAX) {
+        samples = UINT16_MAX;
+    }
+    FilterLength(samples);
+}
+
+bool CcioPin::InputRisen() {
+    return CcioMgr.InputsRisen(m_dataBit);
+}
+
+bool CcioPin::InputFallen() {
+    return CcioMgr.InputsFallen(m_dataBit);
+}
+
+bool CcioPin::IsInHwFault() {
+    return (volatile uint64_t &)(CcioMgr.m_ccioOverloaded) & m_dataBit;
+}
+
+void CcioPin::OutputPulsesStart(uint32_t onTime, uint32_t offTime,
+                                uint16_t pulseCount, bool blockUntilDone) {
+    CcioMgr.OutputPulsesStart(m_clearCorePin, onTime, offTime, pulseCount,
+                              blockUntilDone);
+}
+
+void CcioPin::OutputPulsesStop(bool stopImmediately) {
+    CcioMgr.OutputPulsesStop(m_clearCorePin, stopImmediately);
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalIn.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalIn.cpp
new file mode 100644
index 000000000..f792fb9b9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalIn.cpp
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    DigitalIn implementation
+
+    ClearCore Base Digital Input connector class implementation
+**/
+
+#include "DigitalIn.h"
+#include <sam.h>
+#include "atomic_utils.h"
+#include "InputManager.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+extern ShiftRegister ShiftReg;
+extern InputManager &InputMgr;
+
+#define OVERLOAD_CHECK_HOLDOFF 3
+
+// Stubbed connector base; purposefully set up in an invalid state
+Connector::Connector()
+    : m_clearCorePin(CLEARCORE_PIN_INVALID),
+      m_mode(INVALID_NONE) {}
+
+/**
+    Construct and wire in our input bit
+**/
+DigitalIn::DigitalIn(
+    ShiftRegister::Masks ledMask,
+    const PeripheralRoute *inputInfo)
+    : Connector(),
+      m_ledMask(ledMask),
+      m_inputPort(inputInfo->gpioPort),
+      m_inputDataBit(inputInfo->gpioPin),
+      m_inputDataMask(1UL << inputInfo->gpioPin),
+      m_extInt(inputInfo->extInt),
+      m_interruptAvail(inputInfo->extIntAvail),
+      m_changeRegPtr(nullptr),
+      m_inRegPtr(nullptr),
+      m_inputRegRTPtr(nullptr),
+      m_stateFiltered(false),
+      m_filterLength(3),
+      m_filterTicksLeft(1) {}
+
+/**
+    Set connector's internal state and update filtering if required.
+**/
+void DigitalIn::Refresh() {
+    if (*m_changeRegPtr & m_inputDataMask) {
+        m_filterTicksLeft = m_filterLength;
+
+        if (!m_filterLength) {
+            // If the filter length is zero, set the filtered state
+            UpdateFilterState();
+        }
+    }
+    else if (m_filterTicksLeft && !--m_filterTicksLeft) {
+        // When we decrement to zero, set the filtered state
+        UpdateFilterState();
+    }
+}
+
+/**
+    Initialize a digital input connector
+**/
+void DigitalIn::Initialize(ClearCorePins clearCorePin) {
+    // Clean up any state that Reinitialize may require
+    m_mode = INVALID_NONE;
+    m_stateFiltered = false;
+    m_filterLength = 3;
+    m_filterTicksLeft = 1;
+
+    // Enabling peripheral mux for interrupts
+    PMUX_SELECTION(m_inputPort, m_inputDataBit, PER_EXTINT);
+
+    // For EIC handling on connectors that share interrupt pins.
+    if (m_interruptAvail) {
+        PIN_CONFIGURATION(m_inputPort, m_inputDataBit,
+                          PORT_PINCFG_PMUXEN | PORT_PINCFG_INEN);
+    }
+    else {
+        // Disable interrupts on all other connectors
+        PIN_CONFIGURATION(m_inputPort, m_inputDataBit, PORT_PINCFG_INEN);
+    }
+
+    m_changeRegPtr = &InputMgr.m_inputsUnfilteredChanges[m_inputPort];
+    m_inRegPtr = &InputMgr.m_inputsUnfiltered[m_inputPort];
+    m_inputRegRTPtr = &InputMgr.m_inputRegRT.reg;
+
+    ShiftReg.ShifterState(m_stateFiltered, m_ledMask);
+
+    m_clearCorePin = clearCorePin;
+    Mode(INPUT_DIGITAL);
+}
+
+int16_t DigitalIn::State() {
+    if (m_filterLength == 0) {
+        // Pull an unfiltered, real time input value.
+        return StateRT();
+    }
+    return m_stateFiltered;
+}
+
+int16_t DigitalIn::StateRT() {
+    // Pull an unfiltered, real time input value.
+    return !(*InputMgr.m_inputPtrs[m_inputPort] & m_inputDataMask);
+}
+
+bool DigitalIn::InputRisen() {
+    return InputMgr.InputsRisen(1UL << m_clearCorePin).reg;
+}
+
+bool DigitalIn::InputFallen() {
+    return InputMgr.InputsFallen(1UL << m_clearCorePin).reg;
+}
+
+bool DigitalIn::InterruptHandlerSet(voidFuncPtr callback,
+                                    InputManager::InterruptTrigger trigger,
+                                    bool enable) {
+    if (!m_interruptAvail) {
+        return false;
+    }
+
+    return InputMgr.InterruptHandlerSet(m_extInt, callback, trigger, enable);
+}
+
+void DigitalIn::InterruptEnable(bool enable) {
+    InputMgr.InterruptEnable(m_extInt, enable);
+}
+
+// Write the current filtered pin status back to the member variables
+void DigitalIn::UpdateFilterState() {
+    m_stateFiltered = !(*m_inRegPtr & m_inputDataMask);
+    ShiftReg.ShifterState(m_stateFiltered, m_ledMask);
+
+    // Update the SysManager Register
+    if (m_stateFiltered) {
+        atomic_or_fetch(m_inputRegRTPtr, 1UL << m_clearCorePin);
+    }
+    else {
+        atomic_and_fetch(m_inputRegRTPtr, ~(1UL << m_clearCorePin));
+    }
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInAnalogIn.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInAnalogIn.cpp
new file mode 100644
index 000000000..da18012da
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInAnalogIn.cpp
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Connector class for analog and digital inputs.
+
+    This connector class supports reading digital or analog inputs, depending
+    on the mode. Connectors of this type include A9 through A12.
+**/
+
+#include "DigitalInAnalogIn.h"
+#include "AdcManager.h"
+#include "StatusManager.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+extern ShiftRegister ShiftReg;
+extern AdcManager &AdcMgr;
+extern StatusManager &StatusMgr;
+
+DigitalInAnalogIn::DigitalInAnalogIn(ShiftRegister::Masks ledMask,
+                                     ShiftRegister::Masks modeControlMask,
+                                     const PeripheralRoute *inputInfo,
+                                     AdcManager::AdcChannels adcChannel)
+    : DigitalIn(ledMask, inputInfo),
+      m_modeControlBitMask(modeControlMask),
+      m_adcChannel(adcChannel),
+      m_adcResultConvertedPtr(nullptr),
+      m_adcResultConvertedFilteredPtr(nullptr),
+      m_analogValid(false) {}
+
+/**
+    In digital mode, read the input.
+    In analog mode, read the raw value and update the filtered value.
+**/
+void DigitalInAnalogIn::Refresh() {
+    switch (m_mode) {
+        case INPUT_ANALOG:
+            // If the ShiftRegister was not set up for the analog input
+            // when this ADC reading was captured then it is not valid
+            if (!(AdcMgr.ShiftRegSnapshot() & m_modeControlBitMask)) {
+                // If this is the first valid reading, reset the IIR filter
+                if (!m_analogValid) {
+                    AdcMgr.FilterReset(m_adcChannel, *m_adcResultConvertedPtr);
+                    m_analogValid = true;
+                }
+
+                // Set the LED PWM representation of this connector's value
+                uint8_t value = (*m_adcResultConvertedPtr) >> 7;
+                // Set a lower threshold of when to show any duty on the LED
+                if (value < 0x03) {
+                    value = 0;
+                }
+                ShiftReg.LedPwmValue(m_clearCorePin, value);
+            }
+            break;
+        case INPUT_DIGITAL:
+            DigitalIn::Refresh();
+            break;
+        default:
+            break;
+    }
+}
+
+/**
+    Reset the analog values, setup the digital input, and
+    set the mode to be digital input.
+**/
+void DigitalInAnalogIn::Initialize(ClearCorePins clearCorePin) {
+    // Set the filter time
+    AdcMgr.FilterTc(m_adcChannel,
+                    ANALOG_INPUT_FILTER_TC_MS_DEFAULT,
+                    AdcManager::FILTER_UNIT_MS);
+
+    // Retrieve the pointers to AdcMgr results.
+    m_adcResultConvertedPtr = &AdcMgr.ConvertedResult(m_adcChannel);
+    m_adcResultConvertedFilteredPtr = &AdcMgr.FilteredResult(m_adcChannel);
+
+    DigitalIn::Initialize(clearCorePin);
+    // Mode is now set to INPUT_DIGITAL, reset state is INPUT_ANALOG, switch now
+    Mode(INPUT_ANALOG);
+}
+
+int16_t DigitalInAnalogIn::State() {
+    int16_t state;
+
+    switch (m_mode) {
+        case INPUT_ANALOG:
+            if (StatusMgr.AdcIsInTimeout()) {
+                state = -1;
+            }
+            else {
+                state = *m_adcResultConvertedFilteredPtr >>
+                        (15 - AdcMgr.AdcResolution());
+            }
+            break;
+        case INPUT_DIGITAL:
+            state = DigitalIn::State();
+            break;
+        default:
+            state = 0;
+            break;
+    }
+    return state;
+}
+
+bool DigitalInAnalogIn::FilterTc(uint16_t tc,
+                                 AdcManager::FilterUnits theUnits) {
+    return AdcMgr.FilterTc(m_adcChannel, tc, theUnits);
+}
+
+bool DigitalInAnalogIn::Mode(ConnectorModes newMode) {
+    // Bail out if we are already in the requested mode
+    if (newMode == m_mode) {
+        return true;
+    }
+
+    switch (newMode) {
+        case INPUT_DIGITAL:
+            ShiftReg.ShifterState(true, m_modeControlBitMask);
+            // If the system has already been initialized, wait until the
+            // digital reading is valid then reset the filtered state
+            if (ShiftReg.Ready()) {
+                while (!(AdcMgr.ShiftRegSnapshot() & m_modeControlBitMask)) {
+                    continue;
+                }
+                UpdateFilterState();
+            }
+            ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+            m_mode = newMode;
+            m_analogValid = false;
+            break;
+        case INPUT_ANALOG:
+            ShiftReg.ShifterState(false, m_modeControlBitMask);
+            m_mode = newMode;
+            // If the system has already been initialized, wait until the analog
+            // reading is valid to avoid invalid readings after switching modes
+            if (ShiftReg.Ready()) {
+                while (!m_analogValid) {
+                    continue;
+                }
+            }
+            ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+            break;
+        default:
+            break;
+    }
+
+    return (m_mode == newMode);
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOut.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOut.cpp
new file mode 100644
index 000000000..f9a93acc3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOut.cpp
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ClearCore Connector Digital Input/Output Class
+
+    This manages an input/output connector on the ClearCore board.
+
+    This class enhances an input point to include an output capability.
+**/
+
+#include "DigitalInOut.h"
+#include <sam.h>
+#include "StatusManager.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+
+#define OVERLOAD_TRIP_TICKS ((uint8_t)(2.4 * MS_TO_SAMPLES))
+#define OVERLOAD_FOLDBACK_TICKS (100 * MS_TO_SAMPLES)
+
+namespace ClearCore {
+
+extern StatusManager &StatusMgr;
+extern ShiftRegister ShiftReg;
+extern volatile uint32_t tickCnt;
+
+/**
+    Construct and wire in the Input/Output pair.
+**/
+DigitalInOut::DigitalInOut(ShiftRegister::Masks ledMask,
+                           const PeripheralRoute *inputInfo,
+                           const PeripheralRoute *outputInfo,
+                           bool logicInversion)
+    : DigitalIn(ledMask, inputInfo),
+      m_outputPort(outputInfo->gpioPort),
+      m_outputDataBit(outputInfo->gpioPin),
+      m_outputDataMask(1UL << outputInfo->gpioPin),
+      m_logicInversion(logicInversion),
+      m_isInFault(false),
+      m_tcPadNum(outputInfo->tcPadNum),
+      m_outState(false),
+      m_pulseOnTicks(0),
+      m_pulseOffTicks(0),
+      m_pulseStart(0),
+      m_pulseStopCount(0),
+      m_pulseCounter(0),
+      m_overloadTripCnt(OVERLOAD_TRIP_TICKS),
+      m_pulseActive(false),
+      m_pulseValue(false),
+      m_pulseStopPending(false),
+      m_overloadFoldbackCnt(0) {
+    static Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+    m_tc = tc_modules[outputInfo->tcNum];
+}
+
+bool DigitalInOut::Mode(ConnectorModes newMode) {
+    // Bail out if we are already in the requested mode
+    if (newMode == m_mode) {
+        return true;
+    }
+
+    switch (newMode) {
+        // Set up as output
+        case OUTPUT_DIGITAL:
+            m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+            m_overloadFoldbackCnt = 0;
+            m_mode = newMode;
+            State(m_outState);
+            ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+            PMUX_DISABLE(m_outputPort, m_outputDataBit);
+            break;
+        // Set up as input
+        case INPUT_DIGITAL:
+            m_mode = newMode;
+            // Force set output to avoid fault condition
+            m_pulseActive = false;
+            m_pulseStopPending = false;
+            OutputPin(false);
+            ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+            PMUX_DISABLE(m_outputPort, m_outputDataBit);
+            // Fault state only applies in output digital mode
+            IsInHwFault(false);
+            break;
+        case OUTPUT_PWM:
+            m_mode = newMode;
+            State(0);
+            ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+            PMUX_ENABLE(m_outputPort, m_outputDataBit);
+            // Fault state only applies in output digital mode
+            IsInHwFault(false);
+            break;
+        // Unsupported mode, don't change anything
+        default:
+            break;
+    }
+
+    return (m_mode == newMode);
+}
+
+/**
+    Update connector's state.
+**/
+void DigitalInOut::Refresh() {
+    DigitalIn::Refresh();
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+            if (m_overloadFoldbackCnt) {
+                if (!(--m_overloadFoldbackCnt)) {
+                    // Coming out of foldback, reset the overload
+                    // delay timer and restore the pin state
+                    OutputPin(m_outState);
+                    m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+                }
+            }
+            // If output is true and input is false, the pin is overloaded
+            else if (m_outState && !StateRT()) {
+                // When the overload counter hits zero, signal the overload
+                if (m_overloadTripCnt && !--m_overloadTripCnt) {
+                    IsInHwFault(true);
+                    OutputPin(false);
+                    m_overloadFoldbackCnt = OVERLOAD_FOLDBACK_TICKS;
+                }
+            }
+            else {
+                // Not overloaded, reset the overload delay timer
+                m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+                IsInHwFault(false);
+            }
+            if (!m_pulseActive) {
+                break;
+            }
+
+            if (m_pulseStopCount == 0 || m_pulseCounter < m_pulseStopCount) {
+                if (m_pulseValue) {
+                    if (tickCnt - m_pulseStart >= m_pulseOnTicks) {
+                        // Turn off the pulse
+                        m_pulseValue = false;
+                        m_pulseStart = tickCnt;
+                        // Reset the filter when the output changes (to
+                        // prevent an overload condition being falsely reported)
+                        m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+                        OutputPin(false);
+                        m_outState = false;
+                        // Increment the counter after a complete cycle
+                        ++m_pulseCounter;
+                        // If a stop is pending, handle it now that the cycle
+                        // has completed
+                        if (m_pulseStopPending) {
+                            m_pulseActive = false;
+                            m_pulseStopPending = false;
+                        }
+                    }
+                }
+                else {
+                    // If a stop is pending, handle it right away while the
+                    // pulseValue is low
+                    if (m_pulseStopPending) {
+                        m_pulseActive = false;
+                        m_pulseStopPending = false;
+                    }
+                    else if (tickCnt - m_pulseStart >= m_pulseOffTicks) {
+                        // Turn on the pulse
+                        m_pulseValue = true;
+                        m_pulseStart = tickCnt;
+                        // Reset the filter when the output changes (to
+                        // prevent an overload condition being falsely reported)
+                        m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+                        // Assert the output pin if we are not in overload
+                        // foldback
+                        OutputPin(!m_overloadFoldbackCnt);
+                        m_outState = true;
+                    }
+                }
+            }
+            else if (m_pulseCounter == m_pulseStopCount) {
+                m_pulseActive = false;
+                m_pulseStopPending = false;
+            }
+            break;
+        case OUTPUT_PWM:
+        case INPUT_DIGITAL:
+        default:
+            break;
+    }
+}
+
+int16_t DigitalInOut::State() {
+    int16_t state = -1;
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+            state = m_outState;
+            break;
+        case INPUT_DIGITAL:
+            // Return internal state, preventing re-read
+            state = DigitalIn::State();
+            break;
+        case OUTPUT_PWM:
+            if (!m_tc) {
+                break;
+            }
+
+            if (m_logicInversion) {
+                state = m_tc->COUNT8.CCBUF[m_tcPadNum].reg;
+            }
+            else {
+                state = 255 - m_tc->COUNT8.CCBUF[m_tcPadNum].reg;
+            }
+            break;
+        default:
+            state = 0;
+    }
+
+    return state;
+}
+
+bool DigitalInOut::State(int16_t newState) {
+    bool success = false;
+    m_pulseActive = false;
+    m_pulseStopPending = false;
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+            if (m_outState != static_cast<bool>(newState)) {
+                m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+                m_outState = static_cast<bool>(newState);
+            }
+            OutputPin(newState && !m_overloadFoldbackCnt);
+            success = true;
+            break;
+        case INPUT_DIGITAL:
+            // Not writable in input mode
+            success = false;
+            break;
+        case OUTPUT_PWM:
+            // Cap the input at max PWM (255)
+            if (static_cast<uint16_t>(newState) > UINT8_MAX) {
+                newState = UINT8_MAX;
+            }
+            // Start the PWM output
+            success = PwmDuty(newState);
+            break;
+        default:
+            break;
+    }
+
+    return success;
+}
+
+/**
+    Initialize a digital input/output connector. Set to input mode.
+**/
+void DigitalInOut::Initialize(ClearCorePins clearCorePin) {
+    // Clean up any state that Reinitialize may require
+    m_outState = false;
+    m_isInFault = false;
+    m_pulseActive = false;
+    m_pulseStopPending = false;
+
+    // Set up to multiplex with TC for periodic user output functions
+    PMUX_SELECTION(m_outputPort, m_outputDataBit, PER_TIMER);
+
+    // Perform any input initializing
+    DigitalIn::Initialize(clearCorePin);
+    // Mode is now set to INPUT_DIGITAL
+
+    // Set up output pin as output now that the connector is initialized
+    DATA_DIRECTION_OUTPUT(m_outputPort, m_outputDataMask);
+}
+
+void DigitalInOut::OutputPulsesStart(uint32_t onTime, uint32_t offTime,
+                                     uint16_t pulseCount, bool blockUntilDone) {
+    // Do not start output pulses if we are in input mode
+    if (!IsWritable()) {
+        return;
+    }
+    // Ignore pulses that never turn on or off
+    if (onTime == 0 || offTime == 0) {
+        return;
+    }
+
+    Mode(OUTPUT_DIGITAL);
+    m_pulseOnTicks = onTime * MS_TO_SAMPLES;
+    m_pulseOffTicks = offTime * MS_TO_SAMPLES;
+
+    m_pulseStopPending = false;
+    m_pulseCounter = 0;
+    m_pulseStopCount = pulseCount;
+
+    if (!OutputPulsesActive()) {
+        m_pulseStart = tickCnt;
+        m_pulseActive = true;
+        m_pulseValue = true;
+        // Turn on output directly (calling State() will stop the pulse)
+        m_overloadTripCnt = OVERLOAD_TRIP_TICKS;
+        OutputPin(!m_overloadFoldbackCnt);
+        m_outState = true;
+    }
+
+    if (blockUntilDone && pulseCount != 0) {
+        while (OutputPulsesActive()) {
+            continue;
+        }
+    }
+}
+
+void DigitalInOut::OutputPulsesStop(bool stopImmediately) {
+    // Always set output to low after clearing a pulse
+    if (stopImmediately) {
+        // State will automatically clear m_pulseActive
+        State(false);
+    }
+    else {
+        m_pulseStopPending = true;
+    }
+}
+
+bool DigitalInOut::PwmDuty(uint8_t newDuty) {
+    // Bail out if not in PWM output mode
+    if (m_mode != OUTPUT_PWM) {
+        return false;
+    }
+
+    // Wait for the TC CC value to be ready to be written
+    uint8_t ccBufVal = (m_logicInversion) ? newDuty : 255 - newDuty;
+    if (m_tc->COUNT8.CCBUF[m_tcPadNum].reg != ccBufVal) {
+        uint32_t syncMask = m_tcPadNum ? TC_SYNCBUSY_CC1 : TC_SYNCBUSY_CC0;
+        SYNCBUSY_WAIT(&m_tc->COUNT8, syncMask);
+        m_tc->COUNT8.CCBUF[m_tcPadNum].reg = ccBufVal;
+    }
+    ShiftReg.LedPwmValue(m_clearCorePin, newDuty);
+    return true;
+}
+
+void DigitalInOut::IsInHwFault(bool inFault) {
+    if (inFault != m_isInFault) {
+        m_isInFault = inFault;
+        ShiftReg.LedInFault(m_ledMask, m_isInFault);
+        StatusMgr.OverloadUpdate(1UL << m_clearCorePin, m_isInFault);
+        if (inFault) {
+            StatusMgr.BlinkCode(
+                BlinkCodeDriver::BLINK_GROUP_IO_OVERLOAD,
+                1UL << m_clearCorePin);
+        }
+    }
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOutAnalogOut.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOutAnalogOut.cpp
new file mode 100644
index 000000000..f992c5b87
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOutAnalogOut.cpp
@@ -0,0 +1,359 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ClearCore Connector Digital Input/Output with Analog Output Class
+
+    This manages an input/output connector on the ClearCore board.
+
+    This class enhances an input point to include an output capability.
+**/
+
+#include "DigitalInOutAnalogOut.h"
+#include <sam.h>
+#include "NvmManager.h"
+#include "SysUtils.h"
+
+#define DAC_BITS    11
+#define DAC_MAX_VALUE   (UINT16_MAX >> (16 - DAC_BITS))
+#define DAC_MAX_OUTPUT_UA   20000
+#define DAC_DEFAULT_SPAN    1700
+
+namespace ClearCore {
+
+extern ShiftRegister ShiftReg;
+extern NvmManager &NvmMgr;
+
+/**
+    Construct, wire in the Input/Output pair, and set pad to input mode.
+**/
+DigitalInOutAnalogOut::DigitalInOutAnalogOut(
+    ShiftRegister::Masks ledMask,
+    const PeripheralRoute *inputInfo,
+    const PeripheralRoute *outputInfo,
+    const PeripheralRoute *outputAnalogInfo,
+    bool digitalLogicInversion)
+    : DigitalInOut(ledMask, inputInfo, outputInfo, digitalLogicInversion),
+      m_analogPort(outputAnalogInfo->gpioPort),
+      m_analogDataBit(outputAnalogInfo->gpioPin),
+      m_dacZero(0),
+      m_dacSpan(DAC_DEFAULT_SPAN) {}
+
+/**
+    Do nothing if in analog output mode; otherwise call DigitalInOut's Refresh
+**/
+void DigitalInOutAnalogOut::Refresh() {
+    switch (m_mode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+            // Leave the work to the base class
+            DigitalInOut::Refresh();
+            break;
+        case OUTPUT_ANALOG:
+        // Do nothing here
+        default:
+            break;
+    }
+}
+
+bool DigitalInOutAnalogOut::Mode(ConnectorModes newMode) {
+    if (m_mode == newMode) {
+        return true;
+    }
+
+    switch (newMode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+            // The DAC isn't needed in these modes
+            DacDisable();
+            // Leave the work to the base class
+            DigitalInOut::Mode(newMode);
+            break;
+        case OUTPUT_ANALOG:
+            // Analog output requires the output pin to be turned off
+            // similar to when we are in digital input mode
+            DigitalInOut::Mode(INPUT_DIGITAL);
+            // Need the DAC for this mode
+            DacEnable();
+            m_mode = newMode;
+            break;
+        default:
+            break;
+    }
+
+    return (m_mode == newMode);
+}
+
+bool DigitalInOutAnalogOut::IsWritable() {
+    return m_mode == OUTPUT_DIGITAL || m_mode == OUTPUT_ANALOG ||
+           m_mode == OUTPUT_PWM;
+}
+
+int16_t DigitalInOutAnalogOut::State() {
+    int16_t state;
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+        case INPUT_DIGITAL:
+        case OUTPUT_PWM:
+            // Return internal state, preventing re-read
+            state = DigitalInOut::State();
+            break;
+        default:
+            state = 0;
+            break;
+    }
+
+    return state;
+}
+
+bool DigitalInOutAnalogOut::State(int16_t newState) {
+    bool success = false;
+
+    switch (m_mode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+            success = DigitalInOut::State(newState);
+            break;
+        case OUTPUT_ANALOG:
+            // AnalogWrite takes a uint16_t, so avoid interpreting
+            // negative values as large positive values
+            newState = max(newState, 0);
+            AnalogWrite(newState);
+            success = true;
+            break;
+        default:
+            break;
+    }
+
+    return success;
+}
+
+/**
+    Get the DAC and the DigitalInOut ready to go, and get into digital
+    input mode.
+**/
+void DigitalInOutAnalogOut::Initialize(ClearCorePins clearCorePin) {
+    // Perform any digital input/output initializing
+    DacInitialize();
+    DigitalInOut::Initialize(clearCorePin);
+    // Mode is now set to INPUT_DIGITAL
+
+    // Initialize the PMUX for analog output, but don't enable the MUX
+    PMUX_SELECTION(m_inputPort, m_inputDataBit, PER_ANALOG);   // (-) DAC output
+    PMUX_SELECTION(m_analogPort, m_analogDataBit, PER_ANALOG); // (+) DAC output
+}
+
+/**
+    One-time DAC Configuration
+**/
+void DigitalInOutAnalogOut::DacInitialize() {
+    // Give the DAC a clock
+    // The DAC will misbehave if clocked at more than 100 MHz
+    SET_CLOCK_SOURCE(DAC_GCLK_ID, 4);
+
+    // Set the supply controller's internal bandgap reference
+    SUPC->VREF.bit.SEL = SUPC_VREF_SEL_2V5_Val;
+
+    // Enables the peripheral clock to the DAC
+    CLOCK_ENABLE(APBDMASK, DAC_);
+
+    // Reset the DAC module
+    DAC->CTRLA.bit.SWRST = 1;
+    SYNCBUSY_WAIT(DAC, DAC_SYNCBUSY_SWRST);
+
+    // Use differential mode
+    DAC->CTRLB.bit.DIFF = 1;
+
+    // Set to internal bandgap reference
+    DAC->CTRLB.bit.REFSEL = DAC_CTRLB_REFSEL_INTREF_Val;
+
+    // Enable the DAC
+    DAC->DACCTRL[0].bit.ENABLE = 1;
+    // Set refresh rate to (5 x 30) = 150 us
+    DAC->DACCTRL[0].bit.REFRESH = 0x5;
+    // Current control: CC12M (6 MHz < GCLK_DAC <= 12 MHz)
+    DAC->DACCTRL[0].bit.CCTRL = DAC_DACCTRL_CCTRL_CC12M_Val;
+
+    // Write the lowest possible output current so we don't accidentally
+    // damage something connected to the pin during setup
+    DacRegisterWrite(0);
+
+    DacLoadCalibration();
+}
+
+/**
+    Turn on the DAC (and possibly cause other I/O functions to misbehave on IO-0)
+**/
+void DigitalInOutAnalogOut::DacEnable() {
+    // Make sure that a valid command has been written to the DAC
+    DacRegisterWrite(m_dacZero);
+
+    // Set up the INPUT pin as DAC output
+    PMUX_ENABLE(m_inputPort, m_inputDataBit);   // (-) DAC output
+    PMUX_ENABLE(m_analogPort, m_analogDataBit); // (+) DAC output
+
+    SYNCBUSY_WAIT(DAC, DAC_SYNCBUSY_ENABLE);
+    if (!DAC->CTRLA.bit.ENABLE) {
+        DAC->CTRLA.bit.ENABLE = 1;
+        SYNCBUSY_WAIT(DAC, DAC_SYNCBUSY_ENABLE);
+    }
+
+    while (!DAC->STATUS.vec.READY) {
+        continue;
+    }
+
+    // Update the LED pattern
+    ShiftReg.LedPwmValue(m_clearCorePin, 0);
+    ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+
+    // Set the Cfg00_CFG00_AOUT_BIT to HIGH for use as an Analog Output
+    ShiftReg.ShifterStateSet(ShiftRegister::SR_CFG00_AOUT_MASK);
+}
+
+/**
+    Turn off the DAC
+**/
+void DigitalInOutAnalogOut::DacDisable() {
+    // Set the CFG00_AOUT control point to LOW for use in Digital IO modes
+    ShiftReg.ShifterStateClear(ShiftRegister::SR_CFG00_AOUT_MASK);
+
+    // Update the LED pattern
+    ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+
+    // Disable the pin mux
+    PMUX_DISABLE(m_inputPort, m_inputDataBit);   // (-) DAC output
+    PMUX_DISABLE(m_analogPort, m_analogDataBit); // (+) DAC output
+
+    // Prevent the DAC from operating until re-enabled
+    SYNCBUSY_WAIT(DAC, DAC_SYNCBUSY_ENABLE);
+    if (DAC->CTRLA.bit.ENABLE) {
+        DAC->CTRLA.bit.ENABLE = 0;
+        SYNCBUSY_WAIT(DAC, DAC_SYNCBUSY_ENABLE);
+    }
+}
+
+/**
+    Command the DAC to output the given number of microamps
+**/
+void DigitalInOutAnalogOut::OutputCurrent(uint16_t currentuA) {
+    uint16_t dacValue =
+        static_cast<uint32_t>(currentuA) * DAC_MAX_VALUE / DAC_MAX_OUTPUT_UA;
+    AnalogWrite(dacValue);
+}
+
+/**
+    Command the DAC to output a raw 12-bit value
+**/
+void DigitalInOutAnalogOut::AnalogWrite(uint16_t value) {
+    if (m_mode != OUTPUT_ANALOG) {
+        return;
+    }
+
+    value = min(value, DAC_MAX_VALUE);
+
+    // Set the LED blink value
+    ShiftReg.LedPwmValue(m_clearCorePin, value * UINT8_MAX / DAC_MAX_VALUE);
+
+    // Factor in calibration
+    uint16_t command = ((static_cast<uint32_t>(value) * m_dacSpan)
+                        / DAC_MAX_VALUE) + m_dacZero;
+
+    command = min(command, DAC_MAX_VALUE);
+
+    DacRegisterWrite(command);
+}
+
+/**
+    Load DAC calibration from NVM
+**/
+void DigitalInOutAnalogOut::DacLoadCalibration() {
+    m_dacZero = NvmMgr.Int16(NvmManager::NVM_LOC_DAC_ZERO);
+    m_dacSpan = NvmMgr.Int16(NvmManager::NVM_LOC_DAC_SPAN);
+
+    if (m_dacZero > DAC_MAX_VALUE) {
+        // Something's wrong with zero, the calibration sketch should be run
+        m_dacZero = 0;
+    }
+
+    if (m_dacZero + m_dacSpan > DAC_MAX_VALUE) {
+        // Something's wrong with the range
+        m_dacSpan = DAC_DEFAULT_SPAN - m_dacZero;
+    }
+}
+
+/**
+    write DAC calibration to NVM
+**/
+bool DigitalInOutAnalogOut::DacStoreCalibration(uint16_t zero, uint16_t span) {
+    bool validRange = true;
+
+    if (zero > DAC_MAX_VALUE) {
+        validRange = false;
+    }
+
+    if (zero + span > DAC_MAX_VALUE) {
+        validRange = false;
+    }
+
+    if (validRange) {
+        // Only write good calibration info
+        m_dacZero = zero;
+        m_dacSpan = span;
+
+        NvmMgr.Int16(NvmManager::NVM_LOC_DAC_ZERO, m_dacZero);
+        NvmMgr.Int16(NvmManager::NVM_LOC_DAC_SPAN, m_dacSpan);
+    }
+
+    return validRange;
+}
+
+/**
+    Write a value to the DAC DATA register.
+**/
+void DigitalInOutAnalogOut::DacRegisterWrite(uint16_t value) {
+    if (DAC->DATA[0].reg != value) {
+        SYNCBUSY_WAIT(DAC, DAC_SYNCBUSY_DATA0);
+        DAC->DATA[0].reg = value;
+    }
+}
+
+/**
+    Write a value without performing calibration on it.
+**/
+void DigitalInOutAnalogOut::AnalogWriteUncalibrated(uint16_t value) {
+    if (m_mode != OUTPUT_ANALOG) {
+        return;
+    }
+
+    value = min(value, DAC_MAX_VALUE);
+
+    // Set the LED blink value
+    ShiftReg.LedPwmValue(m_clearCorePin, value * UINT8_MAX / DAC_MAX_VALUE);
+
+    DacRegisterWrite(value);
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOutHBridge.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOutHBridge.cpp
new file mode 100644
index 000000000..feaa79312
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DigitalInOutHBridge.cpp
@@ -0,0 +1,433 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    DigitalInOutHBridge implementation
+
+    Implements an H-Bridge, PWM output, and/or a digital input.
+**/
+
+#include "DigitalInOutHBridge.h"
+#include <arm_math.h>
+#include <sam.h>
+#include <stdlib.h>
+#include "DigitalInOut.h"
+#include "StatusManager.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+
+extern uint32_t SystemCoreClock;
+
+namespace ClearCore {
+
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+
+// PWM related constants
+#define TONE_RATE_HZ (22050)
+#define TONE_MAXIMUM_FREQ_HZ (TONE_RATE_HZ / 4)
+
+extern ShiftRegister ShiftReg;
+extern volatile uint32_t tickCnt;
+
+DigitalInOutHBridge::DigitalInOutHBridge(ShiftRegister::Masks ledMask,
+        const PeripheralRoute *inputInfo,
+        const PeripheralRoute *outputInfo,
+        const PeripheralRoute *pwmAInfo,
+        const PeripheralRoute *pwmBInfo,
+        IRQn_Type tccIrq,
+        bool invertDigitalLogic)
+    : DigitalInOut(ledMask,
+                   inputInfo,
+                   outputInfo,
+                   invertDigitalLogic),
+      m_amplitude(INT16_MAX / 10),
+      m_sinStep(0),
+      m_angle(0),
+      m_toneStartTick(0),
+      m_toneOnTicks(0),
+      m_toneOffTicks(0),
+      m_toneState(TONE_OFF),
+      m_pwmAInfo(pwmAInfo),
+      m_pwmBInfo(pwmBInfo),
+      m_tccIrq(tccIrq),
+      m_inFault(false),
+      m_forceToneDuration(false) {
+    static Tcc *const tcc_modules[TCC_INST_NUM] = TCC_INSTS;
+    m_tcc = tcc_modules[pwmAInfo->tccNum];
+}
+
+bool DigitalInOutHBridge::IsWritable() {
+    bool isWritable;
+
+    switch (m_mode) {
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+        case OUTPUT_H_BRIDGE:
+        case OUTPUT_TONE:
+        case OUTPUT_WAVE:
+            isWritable = true;
+            break;
+        case INPUT_DIGITAL:
+        default:
+            isWritable = false;
+            break;
+    }
+    return isWritable;
+}
+
+int16_t DigitalInOutHBridge::State() {
+    int16_t state;
+
+    switch (m_mode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+            // Let the DigitalInOut handle it.
+            state = DigitalInOut::State();
+            break;
+        case OUTPUT_H_BRIDGE:
+        case OUTPUT_TONE:
+            // Undo the state math to return the current state value
+            state =
+                static_cast<int16_t>((static_cast<int32_t>(m_tcc->CC[0].reg) -
+                                      (m_tcc->PER.reg >> 1)) * INT16_MAX / m_tcc->PER.reg >> 1);
+            break;
+        default:
+            state = 0;
+            break;
+    }
+    return state;
+}
+
+bool DigitalInOutHBridge::State(int16_t newState) {
+    bool success = false;
+
+    uint16_t halfDuty = m_tcc->PER.reg >> 1; // 50% duty cycle
+
+    switch (m_mode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+            // Let the DigitalInOut handle it.
+            success = DigitalInOut::State(newState);
+            break;
+        case OUTPUT_H_BRIDGE:
+            if (newState == INT16_MIN) {
+                ShiftReg.LedPwmValue(m_clearCorePin, UINT8_MAX);
+            }
+            else {
+                ShiftReg.LedPwmValue(m_clearCorePin, labs(newState) >> 7);
+            }
+        // Fall through
+        case OUTPUT_TONE:
+            // Create a PWM differential where state 0 is 50/50 duty cycles
+            m_tcc->CCBUF[0].reg = halfDuty + halfDuty * newState / INT16_MAX;
+            m_tcc->CCBUF[1].reg = halfDuty - halfDuty * newState / INT16_MAX;
+            success = true;
+            break;
+        default:
+            break;
+    }
+
+    return success;
+}
+
+void DigitalInOutHBridge::Refresh() {
+    switch (m_mode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        case OUTPUT_PWM:
+            // Let the DigitalInOut handle it.
+            DigitalInOut::Refresh();
+            break;
+        case OUTPUT_WAVE:
+            break;
+        case OUTPUT_H_BRIDGE:
+            break;
+        case OUTPUT_TONE:
+            switch (m_toneState) {
+                case TONE_CONTINUOUS:
+                    break;
+                case TONE_TIMED:
+                    if (tickCnt - m_toneStartTick > m_toneOnTicks) {
+                        m_toneState = TONE_OFF;
+                        m_forceToneDuration = false;
+                        ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+                    }
+                    break;
+                case TONE_PERIODIC_ON:
+                    if (tickCnt - m_toneStartTick > m_toneOnTicks) {
+                        m_toneStartTick = tickCnt;
+                        m_toneState = TONE_PERIODIC_OFF;
+                        ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+                    }
+                    break;
+                case TONE_PERIODIC_OFF:
+                    if (tickCnt - m_toneStartTick > m_toneOffTicks) {
+                        m_toneState = TONE_PERIODIC_ON;
+                        // Interrupt every period
+                        m_tcc->INTENSET.bit.OVF = 1;
+                        m_toneStartTick = tickCnt;
+                        ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+                    }
+                    break;
+                case TONE_OFF:
+                default:
+                    break;
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+void DigitalInOutHBridge::ToneUpdate() {
+    int32_t nextAngle = static_cast<int32_t>(m_angle) + m_sinStep;
+    // When a tone is active, or a tone is ending and we haven't yet reached
+    // the end of the final sine wave, find the next value to output
+    if ((ToneActiveState() && (ToneActiveState() != TONE_PERIODIC_OFF)) ||
+            (m_mode == OUTPUT_TONE && nextAngle < INT16_MAX)) {
+        // Increment the current angle and clip to q15 [0 +1)
+        m_angle = nextAngle & INT16_MAX;
+        State(static_cast<int16_t>((static_cast<int32_t>(arm_sin_q15(m_angle)) *
+                                    m_amplitude) >> 15));
+    }
+    else {
+        // End the tone output and disable the interrupt
+        m_tcc->INTENCLR.bit.OVF = 1;
+        m_angle = 0;
+        State(0);
+    }
+}
+
+void DigitalInOutHBridge::Initialize(ClearCorePins clearCorePin) {
+    DigitalInOut::Initialize(clearCorePin);
+    // Mode is now INPUT_DIGITAL
+    m_inFault = false;
+
+    // Set up the TCC used by this IO for PWM generation
+    // Disable TCC (must be disabled to write enable-protected registers)
+    m_tcc->CTRLA.bit.SWRST = 1;
+    SYNCBUSY_WAIT(m_tcc, TCC_SYNCBUSY_SWRST);
+
+    m_tcc->COUNT.reg = 0;
+    // Allow the PWM to continue when breakpoints are hit
+    m_tcc->DBGCTRL.reg = TCC_DBGCTRL_DBGRUN;
+    // Enable double buffering
+    m_tcc->CTRLBCLR.bit.LUPD = 1;
+    // TCC using dual-slope bottom PWM
+    m_tcc->WAVE.reg |= TCC_WAVE_WAVEGEN_DSBOTTOM;
+    // Interrupt every period when in TONE_OUTPUT, off for now
+    m_tcc->INTENCLR.bit.OVF = 1;
+    // Set the period for the TCC
+    m_tcc->PER.reg = SystemCoreClock / (TONE_RATE_HZ << 1) - 1;
+
+    // For default value drive both channels low
+    for (int8_t iChannel = 0; iChannel < 2; iChannel++) {
+        m_tcc->CC[iChannel].reg = m_tcc->PER.reg;
+    }
+
+    // All of the non-input pins can be configured for output
+    // The PMUX will just disconnect the CPU pin when the line is connected
+    // to the TCC.
+    DATA_OUTPUT_STATE(m_pwmAInfo->gpioPort, 1UL << m_pwmAInfo->gpioPin, false);
+    DATA_OUTPUT_STATE(m_pwmBInfo->gpioPort, 1UL << m_pwmBInfo->gpioPin, true);
+    DATA_DIRECTION_OUTPUT(m_pwmAInfo->gpioPort, 1UL << m_pwmAInfo->gpioPin);
+    DATA_DIRECTION_OUTPUT(m_pwmBInfo->gpioPort, 1UL << m_pwmBInfo->gpioPin);
+
+    // Configure the polarity pins to be driven by PWM
+    // The Port PMUX has it's multiplexing divided into odd and even bits
+    PMUX_SELECTION(m_pwmAInfo->gpioPort, m_pwmAInfo->gpioPin, PER_TIMER_ALT);
+    PMUX_SELECTION(m_pwmBInfo->gpioPort, m_pwmBInfo->gpioPin, PER_TIMER_ALT);
+}
+
+void DigitalInOutHBridge::ToneFrequency(uint16_t frequency) {
+    // Enforce a maximum frequency to stay under the Nyquist frequency
+    if (frequency > TONE_MAXIMUM_FREQ_HZ) {
+        frequency = TONE_MAXIMUM_FREQ_HZ;
+    }
+    m_sinStep = static_cast<int32_t>(INT16_MAX) * frequency / TONE_RATE_HZ;
+}
+
+void DigitalInOutHBridge::ToneAmplitude(int16_t amplitude) {
+    m_amplitude = max(amplitude, 0);
+    if (m_mode == OUTPUT_TONE) {
+        ShiftReg.LedPwmValue(m_clearCorePin, m_amplitude >> 7);
+    }
+}
+
+void DigitalInOutHBridge::ToneContinuous(uint16_t frequency) {
+    if (m_mode != OUTPUT_TONE || m_forceToneDuration) {
+        // A non-blocking timed tone is currently playing that must finish first
+        return;
+    }
+    ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+    ToneFrequency(frequency);
+    m_toneState = TONE_CONTINUOUS;
+    // Interrupt every period
+    m_tcc->INTENSET.bit.OVF = 1;
+}
+
+void DigitalInOutHBridge::ToneTimed(uint16_t frequency, uint32_t duration,
+                                    bool blocking, bool forceDuration) {
+    if (m_mode != OUTPUT_TONE) {
+        return;
+    }
+
+    if (m_toneState == TONE_TIMED && m_forceToneDuration) {
+        // There is already a timed tone with strict duration playing that
+        // hasn't sounded for the full duration. Wait for it to finish
+        // before generating a new tone.
+        return;
+    }
+
+    ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+    ToneFrequency(frequency);
+    m_toneStartTick = tickCnt;
+    m_toneOnTicks = duration * MS_TO_SAMPLES;
+    m_tcc->INTENSET.bit.OVF = 1; // Interrupt every period
+    if (duration == 0) {
+        m_toneState = TONE_CONTINUOUS;
+    }
+    else {
+        m_toneState = TONE_TIMED;
+        m_forceToneDuration = forceDuration;
+
+        if (blocking) {
+            while (ToneActiveState()) {
+                continue;
+            }
+        }
+    }
+}
+
+void DigitalInOutHBridge::TonePeriodic(uint16_t frequency, uint32_t timeOn,
+                                       uint32_t timeOff) {
+    if (m_mode != OUTPUT_TONE || m_forceToneDuration) {
+        // A non-blocking timed tone is currently playing that must finish first
+        return;
+    }
+    ShiftReg.LedInPwm(m_ledMask, true, m_clearCorePin);
+    ToneFrequency(frequency);
+    m_toneStartTick = tickCnt;
+    m_toneOnTicks = timeOn * MS_TO_SAMPLES;
+    m_toneOffTicks = timeOff * MS_TO_SAMPLES;
+    m_toneState = TONE_PERIODIC_ON;
+    // Interrupt every period
+    m_tcc->INTENSET.bit.OVF = 1;
+}
+
+void DigitalInOutHBridge::ToneStop() {
+    if (m_mode != OUTPUT_TONE) {
+        // Wrong mode
+        return;
+    }
+    if (!m_forceToneDuration) {
+        m_toneState = TONE_OFF;
+        ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+    }
+}
+
+bool DigitalInOutHBridge::Mode(ConnectorModes newMode) {
+    bool modeChangeSuccess = false;
+
+    if (m_mode == newMode) {
+        return true;
+    }
+
+    // Unless in H-Bridge, pwmA should be low and pwmB should be high
+    // This makes the connector look like the other IO connectors.
+    // In HBridge mode, these will be driven by the TCC
+    // Note: having the TCC control a pin will disconnect the CPU pins.
+    bool tccControlPwm = false;
+
+    switch (newMode) {
+        case INPUT_DIGITAL:
+        case OUTPUT_DIGITAL:
+        // Fall through. INPUT_DIGITAL, OUTPUT_DIGITAL, and OUTPUT_PWM
+        // all are run by the DigitalInOut class
+        case OUTPUT_PWM:
+            // Update the LED pattern
+            ShiftReg.LedInPwm(m_ledMask, false, m_clearCorePin);
+            modeChangeSuccess = DigitalInOut::Mode(newMode);
+            break;
+        case OUTPUT_TONE:
+            ShiftReg.LedPwmValue(m_clearCorePin, m_amplitude >> 7);
+        // H-BRIDGE, TONE, and WAVE have the same hardware
+        // fall through
+        case OUTPUT_H_BRIDGE:
+        case OUTPUT_WAVE:
+            DATA_OUTPUT_STATE(m_outputPort, m_outputDataMask, !m_inFault);
+            PMUX_DISABLE(m_outputPort, m_outputDataBit);
+            tccControlPwm = true;
+            modeChangeSuccess = true;
+
+            // Update the LED pattern
+            ShiftReg.LedInPwm(m_ledMask,
+                              newMode == OUTPUT_H_BRIDGE,
+                              m_clearCorePin);
+            break;
+        default:
+            break;
+    }
+
+    if (!modeChangeSuccess) {
+        return false;
+    }
+
+    // Configure PMUX for what needs to be controlled by the TCC.
+    if (tccControlPwm) {
+        PMUX_ENABLE(m_pwmAInfo->gpioPort, m_pwmAInfo->gpioPin);
+        PMUX_ENABLE(m_pwmBInfo->gpioPort, m_pwmBInfo->gpioPin);
+    }
+    else {
+        PMUX_DISABLE(m_pwmAInfo->gpioPort, m_pwmAInfo->gpioPin);
+        PMUX_DISABLE(m_pwmBInfo->gpioPort, m_pwmBInfo->gpioPin);
+    }
+
+    // Only enable the TCC if it is being used to control something
+    if (m_tcc->CTRLA.bit.ENABLE != tccControlPwm) {
+        m_tcc->CTRLA.bit.ENABLE = tccControlPwm;
+        SYNCBUSY_WAIT(m_tcc, TCC_SYNCBUSY_ENABLE);
+    }
+
+    m_mode = newMode;
+
+    return modeChangeSuccess;
+}
+
+void DigitalInOutHBridge::FaultState(bool isFaulted) {
+    m_inFault = isFaulted;
+    // Disable H-bridge driver when in an overload state
+    switch (Mode()) {
+        case OUTPUT_H_BRIDGE:
+        case OUTPUT_WAVE:
+        case OUTPUT_TONE:
+            DATA_OUTPUT_STATE(m_outputPort, m_outputDataMask, !isFaulted);
+            break;
+        default:
+            break;
+    }
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DmaManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DmaManager.cpp
new file mode 100644
index 000000000..78ba039f5
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/DmaManager.cpp
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    DMA Peripheral Manager for the ClearCore Board
+
+    This class manages the DMA transfers on the Teknic ClearCore.
+**/
+
+#include "DmaManager.h"
+#include <stddef.h>
+#include <sam.h>
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+// Interrupt priority 0(High) - 7(Low)
+#define DMA_COMPLETE_PRIORITY 2
+
+#if (DMA_CHANNEL_COUNT > DMAC_CH_NUM)
+#error "Attempting to use more DMA channels than available on the device"
+#endif
+
+#ifndef HIDE_FROM_DOXYGEN
+/* Active DMA descriptors */
+DmacDescriptor DmaManager::writeBackDescriptor[DMA_CHANNEL_COUNT]
+__attribute__((aligned(16)));
+/* Starting DMA descriptors */
+DmacDescriptor DmaManager::descriptorBase[DMA_CHANNEL_COUNT] __attribute__((
+            aligned(16)));
+#endif
+
+DmaManager &DmaMgr = DmaManager::Instance();
+
+DmaManager &DmaManager::Instance() {
+    static DmaManager *instance = new DmaManager();
+    return *instance;
+}
+
+void DmaManager::Initialize() {
+    /***********************************************************
+     * DMA peripheral initialization
+     ***********************************************************/
+    // Enables the peripheral clock to the DMAC
+    CLOCK_ENABLE(AHBMASK, DMAC_);
+
+    // Reset the DMAC to start fresh
+    DMAC->CTRL.reg = DMAC_CTRL_SWRST;
+    // Wait for the reset to finish
+    while (DMAC->CTRL.reg == DMAC_CHCTRLA_SWRST) {
+        continue;
+    }
+
+    /* Disable GPDMA interrupt */
+    NVIC_DisableIRQ(DMAC_0_IRQn);
+    /* Initialize DMA interrupt priority  */
+    NVIC_SetPriority(DMAC_0_IRQn, DMA_COMPLETE_PRIORITY);
+
+    // Tell the DMAC where the descriptors are (must be located in SRAM)
+    DMAC->BASEADDR.reg = (uint32_t)descriptorBase;
+    DMAC->WRBADDR.reg = (uint32_t)writeBackDescriptor;
+
+    // Enable the DMAC and set the priority
+    DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
+
+    DMAC->DBGCTRL.bit.DBGRUN = 1;
+
+    NVIC_EnableIRQ(DMAC_0_IRQn);
+
+    /***************************************************************
+     * DMA channels that will be automatically triggered
+     ***************************************************************/
+    DMAC->SWTRIGCTRL.reg &=
+        ~((1UL << DMA_ADC_SEQUENCE) | (1UL << DMA_ADC_RESULTS) |
+          (1UL << DMA_SERCOM0_SPI_TX) | (1UL << DMA_SERCOM0_SPI_RX) |
+          (1UL << DMA_SERCOM7_SPI_TX) | (1UL << DMA_SERCOM7_SPI_RX));
+}
+
+DmacChannel *DmaManager::Channel(DmaChannels index) {
+    if (index >= DMA_CHANNEL_COUNT) {
+        return NULL;
+    }
+    return &DMAC->Channel[index];
+}
+
+DmacDescriptor *DmaManager::BaseDescriptor(DmaChannels index) {
+    if (index >= DMA_CHANNEL_COUNT) {
+        return NULL;
+    }
+    return &descriptorBase[index];
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EncoderInput.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EncoderInput.cpp
new file mode 100644
index 000000000..edd66e136
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EncoderInput.cpp
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ClearCore position decoder object.
+
+    Provides position information from quadrature and index signals.
+**/
+
+#include "EncoderInput.h"
+#include "HardwareMapping.h"
+#include "InputManager.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+#include "atomic_utils.h"
+#include <stdlib.h>
+
+#define EIC_INDEX_INTERRUPT_PRIORITY 1
+#define EIC_INTERRUPT_PRIORITY 7
+
+namespace ClearCore {
+extern InputManager &InputMgr;
+extern EncoderInput EncoderIn;
+
+void IndexCallback() {
+    PDEC->CTRLBSET.reg = PDEC_CTRLBSET_CMD_READSYNC;
+    SYNCBUSY_WAIT(PDEC, PDEC_SYNCBUSY_COUNT);
+    EncoderIn.IndexDetected(PDEC->COUNT.reg);
+}
+
+int32_t EncoderInput::Position() {
+    return atomic_load_n(&m_curPosn) + atomic_load_n(&m_offsetAdjustment);
+}
+
+int32_t EncoderInput::IndexPosition() {
+    return m_indexPosn + atomic_load_n(&m_offsetAdjustment);
+}
+
+int32_t EncoderInput::Position(int32_t newPosn) {
+    int32_t newOffset = newPosn - atomic_load_n(&m_curPosn);
+    int32_t oldOffset = atomic_exchange_n(&m_offsetAdjustment, newOffset);
+    return newOffset - oldOffset;
+}
+
+void EncoderInput::AddToPosition(int32_t posnAdjust) {
+    atomic_add_fetch(&m_offsetAdjustment, posnAdjust);
+}
+
+void EncoderInput::Enable(bool isEnabled) {
+    while (PDEC->SYNCBUSY.reg);
+    if (isEnabled) {
+        PDEC->CTRLA.bit.ENABLE = 1;
+        PDEC->CTRLBSET.reg = PDEC_CTRLBSET_CMD_START;
+
+        // Enabling peripheral mux for position decoder
+        PMUX_SELECTION(m_aInfo->gpioPort, m_aInfo->gpioPin, PER_TIMER_PDEC);
+        PMUX_SELECTION(m_bInfo->gpioPort, m_bInfo->gpioPin, PER_TIMER_PDEC);
+        PMUX_SELECTION(m_indexInfo->gpioPort, m_indexInfo->gpioPin, PER_EXTINT);
+
+        SYNCBUSY_WAIT(PDEC, PDEC_SYNCBUSY_CTRLB);
+
+        // Block the interrupt while clearing the position history
+        __disable_irq();
+        PDEC->CTRLBSET.reg = PDEC_CTRLBSET_CMD_READSYNC;
+        SYNCBUSY_WAIT(PDEC, PDEC_SYNCBUSY_COUNT);
+        int16_t currentHwPosn = PDEC->COUNT.reg;
+        m_hwPosn = currentHwPosn;
+        m_velocity = 0;
+        for(uint16_t i = 0; i < VEL_EST_SAMPLES; i++) {
+            m_posnHistory[i] = currentHwPosn;
+        }
+        m_posnHistoryIndex = 0;
+        m_enabled = true;
+        __enable_irq();
+
+        NVIC_SetPriority((IRQn_Type)(EIC_0_IRQn + m_indexInfo->extInt),
+                         EIC_INDEX_INTERRUPT_PRIORITY);
+
+        // Set an ISR to be called when the index pulse is seen.
+        // Set the interrupt up as a one-time event and re-enable at sample time.
+        InputMgr.InterruptHandlerSet(m_indexInfo->extInt, IndexCallback,
+                                     m_indexInverted ? InputManager::FALLING : InputManager::RISING,
+                                     m_enabled, true);
+    }
+    else {
+        InputMgr.InterruptEnable(m_indexInfo->extInt, false);
+        m_enabled = false;
+        m_indexDetected = false;
+        m_processIndex = false;
+        m_velocity = 0;
+        PDEC->CTRLA.bit.ENABLE = 0;
+        PDEC->CTRLBSET.reg = PDEC_CTRLBSET_CMD_STOP;
+        // Enabling peripheral mux for interrupts
+        PMUX_SELECTION(m_aInfo->gpioPort, m_aInfo->gpioPin, PER_EXTINT);
+        PMUX_SELECTION(m_bInfo->gpioPort, m_bInfo->gpioPin, PER_EXTINT);
+        PMUX_SELECTION(m_indexInfo->gpioPort, m_indexInfo->gpioPin, PER_EXTINT);
+        NVIC_SetPriority((IRQn_Type)(EIC_0_IRQn + m_indexInfo->extInt),
+                         EIC_INTERRUPT_PRIORITY);
+    }
+}
+
+void EncoderInput::IndexInverted(bool invert) {
+    m_indexInverted = invert;
+    InputMgr.InterruptHandlerSet(m_indexInfo->extInt, IndexCallback,
+                                 m_indexInverted ? InputManager::FALLING : InputManager::RISING,
+                                 m_enabled, true);
+}
+
+void EncoderInput::SwapDirection(bool isSwapped) {
+    if (PDEC->CTRLA.bit.SWAP != isSwapped) {
+        bool wasEnabled = PDEC->CTRLA.bit.ENABLE;
+        if (wasEnabled) {
+            PDEC->CTRLA.bit.ENABLE = 0;
+            SYNCBUSY_WAIT(PDEC, PDEC_SYNCBUSY_ENABLE);
+            PDEC->CTRLA.bit.SWAP = isSwapped;
+            PDEC->CTRLA.bit.ENABLE = wasEnabled;
+            SYNCBUSY_WAIT(PDEC, PDEC_SYNCBUSY_ENABLE);
+            PDEC->CTRLBSET.reg = PDEC_CTRLBSET_CMD_START;
+        }
+        else {
+            PDEC->CTRLA.bit.SWAP = isSwapped;
+        }
+    }
+}
+
+/*
+    Construct and wire in our IO pins
+*/
+EncoderInput::EncoderInput()
+    : m_aInfo(&IN06n_QuadA),
+      m_bInfo(&IN07n_QuadB),
+      m_indexInfo(&IN08n_QuadI),
+      m_curPosn(0),
+      m_offsetAdjustment(0),
+      m_velocity(0),
+      m_hwPosn(0),
+      m_posnHistory{0},
+      m_posnHistoryIndex(0),
+      m_enabled(false),
+      m_processIndex(false),
+      m_hwIndex(0),
+      m_indexPosn(0),
+      m_indexDetected(false),
+      m_indexInverted(false),
+      m_stepsLast(0) {
+}
+
+
+void EncoderInput::Initialize() {
+
+    // Set up PDEC
+
+    // Set the clock source for PDEC to GCLK0 (120 MHz) and enable
+    // the peripheral channel
+    SET_CLOCK_SOURCE(PDEC_GCLK_ID, 0);
+
+    // Enables the peripheral clock to PDEC
+    CLOCK_ENABLE(APBCMASK, PDEC_);
+
+    PDEC->CTRLA.reg = PDEC_CTRLA_MODE_QDEC | PDEC_CTRLA_CONF_X4 |
+                      PDEC_CTRLA_PINEN0 | PDEC_CTRLA_PINEN1 |
+                      PDEC_CTRLA_ANGULAR_Msk;
+
+}
+
+void EncoderInput::Update() {
+    //If the encoder is disabled, just return
+    if (!m_enabled) {
+        return;
+    }
+    // Refresh the COUNT reading
+    PDEC->CTRLBSET.reg = PDEC_CTRLBSET_CMD_READSYNC;
+    SYNCBUSY_WAIT(PDEC, PDEC_SYNCBUSY_COUNT);
+    int16_t currentHwPosn = PDEC->COUNT.reg;
+    m_stepsLast = currentHwPosn - m_hwPosn;
+    
+    m_indexDetected = m_processIndex;
+    if (m_processIndex) {
+        m_indexPosn = atomic_load_n(&m_curPosn) + m_hwIndex - m_hwPosn;
+        m_processIndex = false;
+        // Re-enable the index capture interrupt
+        InputMgr.InterruptEnable(m_indexInfo->extInt, true, false);
+    }
+    m_hwPosn = currentHwPosn;
+    // Adjust the measured position
+    int32_t posnNow = atomic_add_fetch(&m_curPosn, (int32_t)m_stepsLast);
+    // Calculate the velocity based on the position change in the 
+    // last VEL_EST_SAMPLES sample times and convert to cnts/sec
+    int32_t posnDelta = posnNow - m_posnHistory[m_posnHistoryIndex];
+    m_velocity = posnDelta * (_CLEARCORE_SAMPLE_RATE_HZ / VEL_EST_SAMPLES);
+    m_posnHistory[m_posnHistoryIndex] = posnNow;
+    m_posnHistoryIndex = (m_posnHistoryIndex + 1) % VEL_EST_SAMPLES;
+}
+
+bool EncoderInput::QuadratureError() {
+    return PDEC->STATUS.bit.QERR;
+}
+
+void EncoderInput::ClearQuadratureError() {
+    // Clear the quadrature error status
+    PDEC->STATUS.reg = PDEC_STATUS_QERR;
+}
+
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetManager.cpp
new file mode 100644
index 000000000..3935c32c9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetManager.cpp
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    EthernetManager implementation
+
+    Implements an Ethernet port.
+**/
+
+#include "EthernetManager.h"
+#include "ethernetif.c"
+#include "lwip/init.h"
+#include "lwip/dhcp.h"
+#include "lwip/dns.h"
+#include "lwip/timeouts.h"
+#include "NvmManager.h"
+#include "SysTiming.h"
+
+namespace ClearCore {
+
+extern NvmManager &NvmMgr;
+
+EthernetManager &EthernetMgr = EthernetManager::Instance();
+
+EthernetManager &EthernetManager::Instance() {
+    static EthernetManager *instance = new EthernetManager();
+    return *instance;
+}
+
+EthernetManager::EthernetManager()
+    : m_portPhyTxen(PHY_TXEN.gpioPort), m_pinPhyTxen(PHY_TXEN.gpioPin),
+      m_portPhyTxd0(PHY_TXD0.gpioPort), m_pinPhyTxd0(PHY_TXD0.gpioPin),
+      m_portPhyTxd1(PHY_TXD1.gpioPort), m_pinPhyTxd1(PHY_TXD1.gpioPin),
+      m_portPhyRxd0(PHY_RXD0.gpioPort), m_pinPhyRxd0(PHY_RXD0.gpioPin),
+      m_portPhyRxd1(PHY_RXD1.gpioPort), m_pinPhyRxd1(PHY_RXD1.gpioPin),
+      m_portPhyRxer(PHY_RXER.gpioPort), m_pinPhyRxer(PHY_RXER.gpioPin),
+      m_portPhyRxdv(PHY_RXDV.gpioPort), m_pinPhyRxdv(PHY_RXDV.gpioPin),
+      m_portPhyMdio(PHY_MDIO.gpioPort), m_pinPhyMdio(PHY_MDIO.gpioPin),
+      m_portPhyMdc(PHY_MDC.gpioPort), m_pinPhyMdc(PHY_MDC.gpioPin),
+      m_portPhyTxclk(PHY_TXCLK.gpioPort), m_pinPhyTxclk(PHY_TXCLK.gpioPin),
+      m_portPhyInt(PHY_INT.gpioPort), m_pinPhyInt(PHY_INT.gpioPin),
+      m_phyExtInt(PHY_INT.extInt), m_phyLinkUp(false), m_phyRemoteFault(false),
+      m_phyInitFailed(false), m_recv(false), m_dhcp(false), m_ethernetActive(false),
+      m_rxBuffIndex(0), m_txBuffIndex(0), m_rxBuffer{0}, m_txBuffer{0},
+      m_retransmissionTimeout(200), m_retransmissionCount(8),
+      m_ethernetInterface({}), m_macInterface({}), m_dhcpData(nullptr) { }
+
+/**
+    Initialize the EthernetManager.
+**/
+void EthernetManager::Initialize() {
+    // Disable transmit and receive circuits
+    // Must be done prior to configuring GMAC settings
+    Enable(false);
+
+    // Write GMAC settings
+    GMAC->NCR.bit.MPE = 1;          // Management port enabled
+    GMAC->NCFGR.bit.SPD = 1;        // 100 Mbps
+    GMAC->NCFGR.bit.FD = 1;         // Full duplex mode
+    GMAC->NCFGR.bit.MAXFS = 1;      // Increase max frame size
+    GMAC->NCFGR.bit.CLK = 0x04;     // MCK divided by 64
+    GMAC->UR.bit.MII = 0;           // RMII mode
+    GMAC->DCFGR.bit.FBLDO = 0x04;   // Use INCR4 AHB bursts
+    GMAC->DCFGR.bit.RXBMS = 0x03;   // 4 Kbytes receiver packet buffer mem size
+    GMAC->DCFGR.bit.TXPBMS = 0x01;  // 4 Kb transmitter packet buffer mem size
+    GMAC->DCFGR.bit.DRBS = 0x02;    // 128 bytes receiver buffer in AHB
+    GMAC->WOL.reg = 0;
+    GMAC->IPGS.reg = GMAC_IPGS_FL((0x1 << 8) | 0x1);
+
+    // Initialize Receive Descriptor List
+    for (uint8_t buff = 0; buff < RX_BUFF_CNT; buff++) {
+        // Write an appropriate address
+        m_rxDesc[buff].reg[0] = (uint32_t) &m_rxBuffer[buff][0];
+        // Clear out status
+        m_rxDesc[buff].reg[1] = 0;
+    }
+    // Mark the last descriptor in the queue to wrap
+    m_rxDesc[RX_BUFF_CNT - 1].bit.WRAP = 1;
+    m_rxBuffIndex = 0;
+
+    // Initialize Transmit Descriptor List
+    for (uint8_t buff = 0; buff < TX_BUFF_CNT; buff++) {
+        // Write an appropriate address
+        m_txDesc[buff].reg[0] = (uint32_t) &m_txBuffer[buff][0];
+        // Clear out status
+        m_txDesc[buff].reg[1] = 0;
+        // Mark the entries as used
+        m_txDesc[buff].bit.OWN = 1;
+        // Mark the entries as individual.
+        m_txDesc[buff].bit.LB = 1;
+    }
+    // Mark the last descriptor in the queue to wrap
+    m_txDesc[TX_BUFF_CNT - 1].bit.WRAP = 1;
+    m_txBuffIndex = 0;
+
+    // Write address of transmit buffer descriptor list to register
+    // transmit buffer queue pointer.
+    // *Must be done while transmit is disabled.
+    GMAC->TBQB.reg = (uint32_t) &m_txDesc;
+    // Write address of receive buffer descriptor list to register receive
+    // buffer queue pointer.
+    // *Must be done while receive is disabled.
+    GMAC->RBQB.reg = (uint32_t) &m_rxDesc;
+
+    // Reset interrupts
+    NVIC_DisableIRQ(GMAC_IRQn);
+    NVIC_ClearPendingIRQ(GMAC_IRQn);
+    NVIC_EnableIRQ(GMAC_IRQn);
+
+    // Configure the GPIO pins
+    ConfigureGpioPerGmac(m_portPhyTxen, m_pinPhyTxen);
+    ConfigureGpioPerGmac(m_portPhyTxd0, m_pinPhyTxd0);
+    ConfigureGpioPerGmac(m_portPhyTxd1, m_pinPhyTxd1);
+    ConfigureGpioPerGmac(m_portPhyRxd0, m_pinPhyRxd0);
+    ConfigureGpioPerGmac(m_portPhyRxd1, m_pinPhyRxd1);
+    ConfigureGpioPerGmac(m_portPhyRxer, m_pinPhyRxer);
+    ConfigureGpioPerGmac(m_portPhyRxdv, m_pinPhyRxdv);
+    ConfigureGpioPerGmac(m_portPhyMdio, m_pinPhyMdio);
+    ConfigureGpioPerGmac(m_portPhyMdc, m_pinPhyMdc);
+    ConfigureGpioPerGmac(m_portPhyTxclk, m_pinPhyTxclk);
+
+    // Configure PHY interrupt in.
+    PIN_CONFIGURATION(m_portPhyInt, m_pinPhyInt, PORT_PINCFG_INEN);
+
+    // Connect PAD to External Interrupt device
+    PMUX_SELECTION(m_portPhyInt, m_pinPhyInt, PER_EXTINT);
+
+    PMUX_ENABLE(m_portPhyInt, m_pinPhyInt);
+    PORT->Group[m_portPhyInt].PINCFG[m_pinPhyInt].bit.INEN = 1;
+
+    // Enable appropriate GMAC interrupts.
+    GMAC->IER.bit.TCOMP = 1;    // Transmit complete
+    GMAC->IER.bit.RCOMP = 1;    // Receive complete
+
+    // Set up EIC for PHY interrupts
+    EIC->CTRLA.bit.ENABLE = 0;
+    SYNCBUSY_WAIT(EIC, EIC_SYNCBUSY_ENABLE);
+
+    uint32_t shiftAmt = 4 * (m_phyExtInt % 8);
+    // Interrupt 3 (from peripheral routing)
+    EIC->INTENSET.reg = (1UL << m_phyExtInt);
+    // Set interrupt mode (CONFIG reg)
+    EIC->CONFIG[m_phyExtInt / 8].reg &= (uint32_t) ~(0xf << shiftAmt);
+    EIC->CONFIG[m_phyExtInt / 8].reg |=
+        (EIC_CONFIG_SENSE0_LOW_Val << shiftAmt);
+
+    EIC->CTRLA.bit.ENABLE = 1;
+    SYNCBUSY_WAIT(EIC, EIC_SYNCBUSY_ENABLE);
+
+    // Initialize the PHY
+    PhyInitialize();
+
+    // Set up fields in our internal interface
+    m_ethernetInterface.rxDesc = &m_rxDesc[0];
+    m_ethernetInterface.txDesc = &m_txDesc[0];
+    m_ethernetInterface.rxBuffIndex = &m_rxBuffIndex;
+    m_ethernetInterface.txBuffIndex = &m_txBuffIndex;
+
+    // Retrieve the MAC address from NVM and write it to the interface
+    NvmMgr.MacAddress(m_ethernetInterface.mac);
+}
+
+void EthernetManager::PhyInitialize() {
+    // Reset PHY status values.
+    m_phyLinkUp = false;
+    m_phyInitFailed = false;
+    m_phyRemoteFault = false;
+    // Verify that the PHY is online.
+    if (PhyRead(PHY_B_CTRL) == 0xFFFF) {
+        m_phyInitFailed = true;
+        return;
+    }
+    // Software reset the PHY.
+    PhyWrite(PHY_B_CTRL, PHY_B_CTRL_RES);
+    if (PhyRead(PHY_ICS) != 0) {
+        m_phyInitFailed = true;
+        return;
+    }
+    // Enable PHY interrupts for Link-Down, Link-Up, and Remote Fault.
+    uint32_t phyIntMask = (PHY_ICS_LDEN | PHY_ICS_LUEN | PHY_ICS_RFEN);
+    uint32_t phyIntValue = PhyWrite(PHY_ICS, phyIntMask);
+    // Verify the interrupts were set correctly. Ignore the 8 LSB.
+    if ((phyIntMask >> 8) != (phyIntValue >> 8)) {
+        m_phyInitFailed = true;
+        return;
+    }
+    m_phyInitFailed = false;
+}
+
+uint32_t EthernetManager::PhyShift(uint32_t phyOp, uint32_t phyReg,
+                                   uint32_t contents) {
+    // Enable the GMAC management port and initiate a shift operation to the
+    // PHY. The PHY's status register is returned into the GMAC's MAN register.
+    GMAC->NCR.bit.MPE = 1;
+    GMAC->MAN.reg = GMAC_MAN_CLTTO |   // Clause 22 or 45 operation (1 is 22)
+                    GMAC_MAN_OP(phyOp) |        // Read or write operation
+                    GMAC_MAN_PHYA(0) |          // PHY address (default is 0)
+                    GMAC_MAN_REGA(phyReg) |     // Register in the PHY to access
+                    GMAC_MAN_WTN(0x2) |         // Must be written to '1' '0'
+                    GMAC_MAN_DATA(contents);
+
+    while (!((GMAC->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos)) {
+        // Wait for the PHY write to finish
+        continue;
+    }
+    GMAC->NCR.bit.MPE = 0;
+
+    return GMAC_MAN_DATA(GMAC->MAN.reg);
+}
+
+uint32_t EthernetManager::PhyRead(uint32_t phyReg) {
+    return PhyShift(PHY_READ_OP, phyReg, 0);
+}
+
+uint32_t EthernetManager::PhyWrite(uint32_t phyReg, uint32_t contents) {
+    PhyShift(PHY_WRITE_OP, phyReg, contents);
+    return PhyShift(PHY_READ_OP, phyReg, 0);
+}
+
+/**
+    Initialization for LwIP's network interface.
+**/
+void EthernetManager::NetifInit() {
+    struct netif *netif = &m_macInterface;
+    ip_addr_t dummyIp = IPADDR4_INIT(0);
+
+    netif_add(netif, &dummyIp, &dummyIp, &dummyIp,
+              &m_ethernetInterface, ethernetif_init, ethernet_input);
+
+    netif_set_default(netif);
+
+    netif_set_link_up(netif);
+
+    netif_set_up(netif);
+
+    Enable(true);
+}
+
+/**
+    Enable transmit and receive of frames.
+**/
+void EthernetManager::Enable(bool enable) {
+    bool enabled = (GMAC->NCR.bit.TXEN && GMAC->NCR.bit.RXEN);
+
+    if (enable == enabled) {
+        // Nothing to do.
+        return;
+    }
+
+    GMAC->NCR.bit.TXEN = enable ? 1 : 0;
+    GMAC->NCR.bit.RXEN = enable ? 1 : 0;
+
+    if (!enable) {
+        // Writing TXEN to 0 on the GMAC resets the GMAC's transmit queue
+        // pointer to the address of m_txBuffer[0].
+        // Reset the TX descriptors to init state
+        for (uint8_t i = 0; i < TX_BUFF_CNT; i++) {
+            m_txDesc[i].bit.OWN = 1;
+            m_txDesc[i].bit.LB = 1;
+        }
+        m_txBuffIndex = 0;
+    }
+}
+
+/**
+    Clear on read check if a frame was received.
+**/
+bool EthernetManager::ReceivedFrameFlag() {
+    bool recv = m_recv;
+    m_recv = false;
+    return recv;
+}
+
+/**
+    The PHY interrupt handler.
+**/
+void EthernetManager::IrqHandlerPhy() {
+    // Read the PHY interrupt status register to get the correct bits
+    // (checking just LinkUp here?)
+    EIC->INTFLAG.reg = 1UL << m_phyExtInt;
+    uint32_t phyRegData = PhyRead(PHY_ICS);
+    // PHY Link-Up
+    if (phyRegData & PHY_ICS_LU) {
+        m_phyLinkUp = true;
+        // Disable must be done before writing GMAC settings.
+        bool enabled = (GMAC->NCR.bit.TXEN == 1);
+        Enable(false);
+
+        // Set the GMAC settings to match the PHY's negotiated settings.
+        uint16_t phyMode = PhyRead(PHY_CTRL_1) & PHY_CTRL_AN_MSK;
+
+        GMAC->NCFGR.bit.SPD = (phyMode & PHY_CTRL_AN_SPD_MSK) ? 1 : 0;
+        GMAC->NCFGR.bit.FD = (phyMode & PHY_CTRL_AN_FD_MSK) ? 1 : 0;
+
+        Enable(enabled);
+    }
+
+    // PHY Link-Down
+    if (phyRegData & PHY_ICS_LD) {
+        m_phyLinkUp = false;
+    }
+    // PHY Remote Fault
+    if (phyRegData & PHY_ICS_RF) {
+        m_phyRemoteFault = true;
+        Enable(false);  // disable
+    }
+}
+
+
+/**
+    The GMAC interrupt handler.
+
+    This should be called by GMAC Interrupt Vector.
+    *Note: the register & bits are cleared on read
+**/
+void EthernetManager::IrqHandlerGmac() {
+    // Transmit status reg
+    volatile uint32_t tsr;
+    // Receive status reg
+    volatile uint32_t rsr;
+
+    tsr = GMAC->TSR.reg;    // Transmit status register
+    rsr = GMAC->RSR.reg;    // Receive  status register
+    // Need to clear the ISR (clear on read)
+    GMAC->ISR.reg;
+
+    // Frame transmitted
+    if (tsr & GMAC_TSR_TXCOMP) {
+        // Clear the TSR reg
+        GMAC->TSR.reg = tsr;
+    }
+
+    // Frame received, add a packet to packet buffer.
+    if (rsr & GMAC_RSR_REC) {
+        m_recv = true;
+    }
+    // Clear the RSR reg
+    GMAC->RSR.reg = rsr;
+}
+
+uint8_t *EthernetManager::MacAddress() {
+    return m_ethernetInterface.mac;
+}
+
+IpAddress EthernetManager::LocalIp() {
+    return IpAddress(m_macInterface.ip_addr.addr);
+}
+
+void EthernetManager::LocalIp(IpAddress ipaddr) {
+    if (!m_dhcp) {
+        m_macInterface.ip_addr.addr = uint32_t(ipaddr);
+    }
+}
+
+IpAddress EthernetManager::NetmaskIp() {
+    return IpAddress(m_macInterface.netmask.addr);
+}
+
+void EthernetManager::NetmaskIp(IpAddress address) {
+    if (!m_dhcp) {
+        m_macInterface.netmask.addr = uint32_t(address);
+    }
+}
+
+IpAddress EthernetManager::GatewayIp() {
+    return IpAddress(m_macInterface.gw.addr);
+}
+
+void EthernetManager::GatewayIp(IpAddress address) {
+    if (!m_dhcp) {
+        m_macInterface.gw.addr = uint32_t(address);
+    }
+}
+
+IpAddress EthernetManager::DnsIp() {
+    if (!m_ethernetActive) {
+        return IpAddress();
+    }
+    return IpAddress(dns_getserver(0)->addr);
+}
+
+void EthernetManager::DnsIp(IpAddress dns) {
+    if (m_ethernetActive) {
+        ip_addr_t dnsIp = IPADDR4_INIT(uint32_t(dns));
+        dns_setserver(0, &dnsIp);
+    }
+}
+
+/**
+    Setup a single GMAC GPIO.
+**/
+void EthernetManager::ConfigureGpioPerGmac(uint32_t port, uint32_t pin) {
+    PMUX_ENABLE(port, pin);
+    PMUX_SELECTION(port, pin, PER_GMAC);
+}
+
+bool EthernetManager::DhcpBegin() {
+    struct netif *netif = &m_macInterface;
+    uint32_t DHCP_TIMEOUT_MS = 1500;
+
+    bool dhcpSuccess = false;
+    for (uint8_t i = 0; i < 5 && !dhcpSuccess; i++) {
+        // Try to get our config info from a DHCP server
+        err_t err = dhcp_start(netif);
+
+        if (err == ERR_OK) {
+            uint32_t startMs = Milliseconds();
+
+            while (dhcp_supplied_address(netif) == 0) {
+                if (Milliseconds() - startMs > DHCP_TIMEOUT_MS) {
+                    // Timed out, stop the dhcp process.
+                    dhcp_release_and_stop(netif);
+                    break;
+                }
+                Refresh();
+            }
+            dhcpSuccess = (dhcp_supplied_address(netif) != 0);
+        }
+    }
+    if (dhcpSuccess) {
+        // Set up info from DHCP configuration
+        m_dhcpData = netif_dhcp_data(netif);
+    }
+    m_dhcp = dhcpSuccess;
+    return dhcpSuccess;
+}
+
+void EthernetManager::Setup() {
+    // Setup can only occur once.
+    if (m_ethernetActive) {
+        return;
+    }
+    lwip_init();
+    dns_init();
+    NetifInit();
+    m_ethernetActive = true;
+}
+
+void EthernetManager::Refresh() {
+    while (true) {
+        // Check for an available packet.
+        struct pbuf *packet = low_level_input(&m_macInterface);
+        if (packet == NULL) {
+            break;
+        }
+        // Send the packet as input to LwIP.
+        ethernetif_input(&m_macInterface, packet);
+    }
+    sys_check_timeouts();
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcp.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcp.cpp
new file mode 100644
index 000000000..8245a91fc
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcp.cpp
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "EthernetTcp.h"
+#include "lwip/tcp.h"
+#include <stdlib.h>
+
+namespace ClearCore {
+
+EthernetTcp::EthernetTcp(TcpData *tcpData)
+    : m_tcpData(tcpData) {}
+
+uint32_t EthernetTcp::Send(uint8_t charToSend) {
+    return Send(&charToSend, 1);
+}
+
+uint16_t EthernetTcp::LocalPort() {
+    if (m_tcpData == nullptr || m_tcpData->pcb == nullptr) {
+        return 0;
+    }
+    return m_tcpData->pcb->local_port;
+}
+
+/**
+    The TCP connection accepted callback.
+    Allows a TCP server to accept clients.
+**/
+err_t TcpAccept(void *arg, struct tcp_pcb *newpcb, err_t err) {
+    EthernetTcp::TcpData **tcpClientData = (EthernetTcp::TcpData **)arg;
+
+    // Set the priority for the new TCP connection. Make this higher than min?
+    tcp_setprio(newpcb, TCP_PRIO_MIN);
+
+    if ((tcpClientData == nullptr) || (err != ERR_OK)) {
+        // Either the client PCBs could not be allocated or there was another
+        // error that occurred during TCP connection setup.
+        tcp_close(newpcb);
+        return ERR_ARG;
+    }
+
+    EthernetTcp::TcpData *clientData =
+        (EthernetTcp::TcpData *)calloc(1, sizeof(EthernetTcp::TcpData));
+    if (clientData == nullptr) {
+        TcpClose(newpcb, clientData);
+        return ERR_MEM;
+    }
+
+    clientData->pcb = newpcb;
+    clientData->state = ESTABLISHED;
+
+    bool accepted = false;
+
+    // Look for an open 'socket' to allow the client to connect to the server.
+    for (uint8_t iClient = 0; iClient < CLIENT_MAX; iClient++) {
+        if (tcpClientData[iClient] == nullptr) {
+            tcpClientData[iClient] = clientData;
+            accepted = true;
+            break;
+        }
+    }
+
+    if (!accepted) {
+        TcpClose(newpcb, clientData);
+        free(clientData);
+        return ERR_MEM;
+    }
+    tcp_nagle_disable(newpcb);
+
+    tcp_arg(newpcb, clientData);
+    tcp_recv(newpcb, TcpReceive);
+    tcp_err(newpcb, TcpError);
+    tcp_sent(newpcb, TcpSend);
+
+    return ERR_OK;
+}
+
+/**
+    The TCP connection callback.
+**/
+err_t TcpConnect(void *arg, struct tcp_pcb *tpcb, err_t err) {
+    EthernetTcp::TcpData *data = (EthernetTcp::TcpData *)arg;
+
+    if (data == nullptr) {
+        return ERR_ARG;
+    }
+    if (err != ERR_OK) {
+        TcpClose(tpcb, data);
+        return err;
+    }
+    if (data->pcb == nullptr || data->pcb != tpcb) {
+        TcpClose(tpcb, data);
+        return ERR_ARG;
+    }
+
+    data->state = ESTABLISHED;
+
+    tcp_recv(tpcb, TcpReceive);
+    tcp_sent(tpcb, TcpSend);
+    tcp_err(tpcb, TcpError);
+
+    return ERR_OK;
+}
+
+/**
+    The TCP connection error callback.
+**/
+void TcpError(void *arg, err_t err) {
+    EthernetTcp::TcpData *data = (EthernetTcp::TcpData *)arg;
+
+    if ((data == nullptr) || (err == ERR_OK)) {
+        return;
+    }
+
+    // At this point the TCP PCB is already free'd.
+    data->pcb = nullptr;
+    data->state = CLOSING;
+}
+
+/**
+    Handles a packet received from a TCP connection.
+
+    A TCP Receive callback function will be passed a NULL pbuf if the
+    remote host has closed the connection. If we return ERR_OK or ERR_ABRT
+    from this callback function we must have freed the pbuf, otherwise we
+    must NOT have freed it.
+**/
+err_t TcpReceive(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) {
+    EthernetTcp::TcpData *tcpClientData =
+        static_cast<EthernetTcp::TcpData *>(arg);
+    if (tcpClientData == nullptr) {
+        return ERR_ARG;
+    }
+    // A NULL pbuf indicates that the remote host closed the connection.
+    if (p == NULL) {
+        TcpClose(tpcb, tcpClientData);
+        return ERR_OK;
+    }
+    // If return anything other than ERR_OK or ERR_ABRT, must NOT free pbuf.
+    if (err != ERR_OK) {
+        return err;
+    }
+    if (tcpClientData->state == ESTABLISHED) {
+        // Only copy the packet's payload if we have enough empty space to copy
+        // every byte.
+        int32_t availableToRead =
+            tcpClientData->dataTail - tcpClientData->dataHead;
+        if (availableToRead  < 0) {
+            availableToRead += TCP_DATA_BUFFER_SIZE;
+        }
+        if (TCP_DATA_BUFFER_SIZE - availableToRead < p->tot_len) {
+            return ERR_BUF;
+        }
+        // Put received packet into the buffer.
+        uint16_t bytesReceived = p->tot_len;
+        for (uint16_t i = 0; i < bytesReceived; i++) {
+            uint16_t nextIndex = (tcpClientData->dataTail + 1) %
+                                 TCP_DATA_BUFFER_SIZE;
+            // If the buffer is full drop the rest
+            if (nextIndex == tcpClientData->dataHead) {
+                bytesReceived = i;
+                break;
+            }
+            // If the buffer is not full, save the value
+            tcpClientData->data[tcpClientData->dataTail] = pbuf_get_at(p, i);
+            tcpClientData->dataTail = nextIndex;
+        }
+        // Acknowledge the data was received.
+        tcp_recved(tcpClientData->pcb, bytesReceived);
+        // Must free the pbuf
+        pbuf_free(p);
+        return ERR_OK;
+    }
+    // If we got this far, we've received a non-empty frame without error,
+    // but there's no established TCP connection.
+    tcp_recved(tcpClientData->pcb, p->tot_len);
+    pbuf_free(p);
+    return ERR_OK;
+}
+
+/**
+    The TCP send complete callback.
+**/
+err_t TcpSend(void *arg, struct tcp_pcb *tpcb, u16_t len) {
+    (void)len;
+    EthernetTcp::TcpData *data = (EthernetTcp::TcpData *)arg;
+
+    // Either the TCP PCB couldn't be allocated or the PCB target is wrong.
+    if (data == nullptr || data->pcb != tpcb) {
+        return ERR_ARG;
+    }
+    return ERR_OK;
+}
+
+/**
+    Closes a TCP connection.
+**/
+void TcpClose(struct tcp_pcb *pcb, EthernetTcp::TcpData *data) {
+    // Remove all the callbacks.
+    tcp_accept(pcb, nullptr);
+    tcp_err(pcb, nullptr);
+    tcp_poll(pcb, nullptr, 0);
+    tcp_recv(pcb, nullptr);
+    tcp_sent(pcb, nullptr);
+
+    // Close the TCP connection and free the PCB.
+    tcp_close(pcb);
+
+    // Clean up the TCP data.
+    if (data != nullptr) {
+        data->pcb = nullptr;
+        data->state = CLOSING;
+    }
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcpClient.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcpClient.cpp
new file mode 100644
index 000000000..ba088b6d6
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcpClient.cpp
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "EthernetTcpClient.h"
+
+#include "EthernetManager.h"
+#include "EthernetTcp.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+#include <stdlib.h>
+
+namespace ClearCore {
+
+extern EthernetManager &EthernetMgr;
+
+EthernetTcpClient::EthernetTcpClient()
+    : EthernetTcp(),
+      m_connectionTimeout(2000),
+      m_dnsInitialized(false) {}
+
+EthernetTcpClient::EthernetTcpClient(TcpData *tcpData)
+    : EthernetTcp(tcpData),
+      m_connectionTimeout(2000),
+      m_dnsInitialized(false) {}
+
+bool EthernetTcpClient::Connect(IpAddress ip, uint16_t port) {
+    if (m_tcpData != nullptr && Connected()) {
+        // Already connected.
+        return false;
+    }
+    if (m_tcpData == nullptr) {
+        m_tcpData = static_cast<TcpData *>(calloc(1, sizeof(TcpData)));
+        if (m_tcpData == nullptr) {
+            // Couldn't allocate TCP state.
+            return false;
+        }
+    }
+
+    m_tcpData->pcb = tcp_new();
+    if (m_tcpData->pcb == nullptr) {
+        free(m_tcpData);
+        // Couldn't allocate TCP PCB.
+        return false;
+    }
+    tcp_nagle_disable(m_tcpData->pcb);
+
+    // Pass the TCP state to TCP callbacks.
+    tcp_arg(m_tcpData->pcb, m_tcpData);
+
+    m_tcpData->state = CLOSED;
+
+    ip_addr_t ipaddr = IPADDR4_INIT(uint32_t(ip));
+    err_t err = tcp_connect(m_tcpData->pcb, &ipaddr, port, TcpConnect);
+    if (err != ERR_OK) {
+        Close();
+        return false;
+    }
+
+    uint32_t start = Milliseconds();
+    while (m_tcpData->state == CLOSED) {
+        EthernetMgr.Refresh();
+        uint32_t elapsed = Milliseconds() - start;
+        // Timeout for connection established.
+        if ((elapsed > m_connectionTimeout) || (m_tcpData->state == CLOSING)) {
+            Close();
+            free(m_tcpData);
+            m_tcpData = nullptr;
+            return false;
+        }
+    }
+    return true;
+}
+
+bool EthernetTcpClient::Connected() {
+    if (m_tcpData == nullptr || m_tcpData->pcb == nullptr) {
+        return false;
+    }
+    tcp_state tcpState = m_tcpData->pcb->state;
+    return (tcpState != CLOSING && tcpState != CLOSE_WAIT &&
+            tcpState != CLOSED);
+}
+
+int16_t EthernetTcpClient::BytesAvailable() {
+    EthernetMgr.Refresh();
+    if (m_tcpData == nullptr) {
+        return 0;
+    }
+    // Calculate the available data in the buffer
+    int32_t difference = m_tcpData->dataTail - m_tcpData->dataHead;
+
+    return (difference < 0) ? TCP_DATA_BUFFER_SIZE + difference : difference;
+}
+
+int16_t EthernetTcpClient::Read() {
+    uint8_t buff;
+    int16_t bytesRead = Read(&buff, 1);
+    return bytesRead == 1 ? buff : -1;
+}
+
+int16_t EthernetTcpClient::Read(uint8_t *dataPtr, uint32_t length) {
+    if (m_tcpData == nullptr) {
+        // Not initialized.
+        return -1;
+    }
+    uint16_t bytesRead = 0;
+    // Read from the TCP's incoming data buffer.
+    while (m_tcpData->dataTail != m_tcpData->dataHead && bytesRead < length) {
+        uint16_t nextIndex = (m_tcpData->dataHead + 1) % TCP_DATA_BUFFER_SIZE;
+        dataPtr[bytesRead++] = m_tcpData->data[m_tcpData->dataHead];
+        m_tcpData->dataHead = nextIndex;
+    }
+    return bytesRead;
+}
+
+int16_t EthernetTcpClient::Peek() {
+    if (m_tcpData == nullptr || m_tcpData->dataTail == m_tcpData->dataHead) {
+        // Not initialized or no data to read.
+        return -1;
+    }
+    int16_t peekChar = m_tcpData->data[m_tcpData->dataHead];
+    return peekChar;
+}
+
+void EthernetTcpClient::Flush() {
+    if (m_tcpData == nullptr || m_tcpData->pcb == nullptr) {
+        // Not initialized or no connection.
+        return;
+    }
+    while (Connected()) {
+        // All outgoing data has been sent when there is nothing unsent and
+        // nothing unacked.
+        if (m_tcpData->pcb->unsent == nullptr &&
+                m_tcpData->pcb->unacked == nullptr) {
+            break;
+        }
+        EthernetMgr.Refresh();
+    }
+}
+
+void EthernetTcpClient::FlushInput() {
+    if (m_tcpData == nullptr) {
+        return;
+    }
+    m_tcpData->dataHead = 0;
+    m_tcpData->dataTail = 0;
+}
+
+void EthernetTcpClient::Close() {
+    if (m_tcpData == nullptr) {
+        // No connection, nothing to do.
+        return;
+    }
+    // Close the TCP connection with FIN.
+    if (m_tcpData->state != CLOSING) {
+        TcpClose(m_tcpData->pcb, m_tcpData);
+    }
+    free(m_tcpData);
+    m_tcpData = nullptr;
+}
+
+uint32_t EthernetTcpClient::Send(const uint8_t *buffer, uint32_t size) {
+    if (m_tcpData == nullptr || m_tcpData->pcb == nullptr ||
+            size == 0 || buffer == nullptr) {
+        // State hasn't been initialized or requested zero bytes.
+        return 0;
+    }
+
+    if (m_tcpData->state != ESTABLISHED) {
+        // The connection has not yet been established.
+        return 0;
+    }
+
+    // Check the # of bytes available in the TCP send buffer.
+    uint32_t bufferAvailable = tcp_sndbuf(m_tcpData->pcb);
+    uint32_t bytesToWrite = min(bufferAvailable, size);
+    err_t err = tcp_write(m_tcpData->pcb, buffer, bytesToWrite,
+                          TCP_WRITE_FLAG_COPY);
+
+    if (err != ERR_OK) {
+        return 0;
+    }
+    // Initiate output immediately.
+    err = tcp_output(m_tcpData->pcb);
+    if (err != ERR_OK) {
+        return 0;
+    }
+    // Avoid filling the send queue.
+    uint32_t TCP_SEND_TIMEOUT_MS = 5;
+    uint32_t startMs = Milliseconds();
+    while (m_tcpData->pcb->snd_queuelen >= TCP_SND_QUEUELEN >> 1) {
+        if (Milliseconds() - startMs >= TCP_SEND_TIMEOUT_MS) {
+            break;
+        }
+        EthernetMgr.Refresh();
+    }
+    return bytesToWrite;
+}
+
+uint16_t EthernetTcpClient::RemotePort() {
+    if (m_tcpData == nullptr || m_tcpData->pcb == nullptr) {
+        return 0;
+    }
+    return m_tcpData->pcb->remote_port;
+}
+
+IpAddress EthernetTcpClient::RemoteIp() {
+    if (m_tcpData == nullptr || m_tcpData->pcb == nullptr) {
+        return IpAddress();
+    }
+    return IpAddress(m_tcpData->pcb->remote_ip.addr);
+}
+
+void EthernetTcpClient::ConnectionTimeout(uint16_t timeout) {
+    if (timeout <= TCP_CONNECTION_TIMEOUT_MIN) {
+        m_connectionTimeout = TCP_CONNECTION_TIMEOUT_MIN;
+    }
+    else if (timeout >= TCP_CONNECTION_TIMEOUT_MAX) {
+        m_connectionTimeout = TCP_CONNECTION_TIMEOUT_MAX;
+    }
+    else {
+        m_connectionTimeout = timeout;
+    }
+}
+
+bool EthernetTcpClient::operator ==(const EthernetTcpClient tcpClient) {
+    return (m_tcpData != nullptr) && (m_tcpData == tcpClient.m_tcpData) &&
+           (m_tcpData->pcb == tcpClient.m_tcpData->pcb);
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcpServer.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcpServer.cpp
new file mode 100644
index 000000000..b326170f1
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetTcpServer.cpp
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "EthernetTcpServer.h"
+#include <stdlib.h>
+
+namespace ClearCore {
+
+extern EthernetManager &EthernetMgr;
+
+EthernetTcpServer::EthernetTcpServer(uint16_t port)
+    : EthernetTcp(), m_initialized(false), m_serverPort(port) {
+    for (uint8_t i = 0; i < CLIENT_MAX; i++) {
+        m_tcpDataClient[i] = nullptr;
+    }
+}
+
+void EthernetTcpServer::Begin() {
+    if (m_tcpData == nullptr) {
+        // Allocate
+        m_tcpData = static_cast<TcpData *>(calloc(1, sizeof(TcpData)));
+    }
+    if (m_tcpData->pcb != nullptr) {
+        // Need to call stop() first. Server already in session.
+        return;
+    }
+
+    m_tcpData->pcb = tcp_new();
+    if (m_tcpData->pcb == nullptr) {
+        // Couldn't allocate TCP PCB for server.
+        return;
+    }
+    tcp_nagle_disable((m_tcpData->pcb));
+
+    // Pass the server's TCP clients array to server TCP callbacks.
+    tcp_arg(m_tcpData->pcb, &m_tcpDataClient);
+
+    // Bind the PCB to the local IP address and port.
+    ip_addr_t ip = IPADDR4_INIT(uint32_t(EthernetMgr.LocalIp()));
+
+    err_t err = tcp_bind(m_tcpData->pcb, &ip, m_serverPort);
+    if (err != ERR_OK) {
+        // Could not bind TCP PCB to the port.
+        TcpClose(m_tcpData->pcb, m_tcpData);
+        return;
+    }
+
+    // Set the server's TCP connection state to LISTEN.
+    m_tcpData->pcb = tcp_listen(m_tcpData->pcb);
+    m_tcpData->state = LISTEN;
+
+    // Register TCP connection accept callback.
+    tcp_accept(m_tcpData->pcb, TcpAccept);
+
+    m_initialized = true;
+}
+
+// EthernetServer manages the clients. A client is only identified and returned
+// when data has been received from the client and is available for reading.
+EthernetTcpClient EthernetTcpServer::Available() {
+    EthernetMgr.Refresh();
+    EthernetTcpClient client;
+
+    for (uint8_t iClient = 0; iClient < CLIENT_MAX; iClient++) {
+        TcpData *clientData = m_tcpDataClient[iClient];
+        if (clientData == nullptr) {
+            continue;
+        }
+
+        client = EthernetTcpClient(clientData);
+
+        // Clean out stale/old/'disconnected' references.
+        if (!client.Connected() && client.BytesAvailable() == 0) {
+            free(clientData);
+            m_tcpDataClient[iClient] = nullptr;
+            continue;
+        }
+
+        // Return a client with available incoming data.
+        if (client.BytesAvailable()) {
+            return client;
+        }
+    }
+
+    // No clients available. Return a default client with no TCP state.
+    client = EthernetTcpClient();
+    return client;
+}
+
+// EthernetServer gives a client only once, regardless of it it has sent data.
+// Then, the user is responsible for keeping track of connected clients.
+EthernetTcpClient EthernetTcpServer::Accept() {
+    EthernetMgr.Refresh();
+    EthernetTcpClient client;
+
+    for (uint8_t iClient = 0; iClient < CLIENT_MAX; iClient++) {
+        TcpData *clientData = m_tcpDataClient[iClient];
+        // Skip null or empty references.
+        if (clientData == nullptr) {
+            continue;
+        }
+
+        client = EthernetTcpClient(clientData);
+
+        // Clean out stale/old/'disconnected' references.
+        if (!client.Connected()) {
+            free(clientData);
+            m_tcpDataClient[iClient] = nullptr;
+            continue;
+        }
+
+        // Return any valid client.
+        m_tcpDataClient[iClient] = nullptr;
+        return client;
+    }
+
+    client = EthernetTcpClient();
+    return client;
+}
+
+uint32_t EthernetTcpServer::Send(const uint8_t *buff, uint32_t size) {
+    EthernetMgr.Refresh();
+
+    for (uint8_t iClient = 0; iClient < CLIENT_MAX; iClient++) {
+        TcpData *clientData = m_tcpDataClient[iClient];
+        EthernetTcpClient client = EthernetTcpClient(clientData);
+        // Don't send data to empty or closed connections.
+        if (!client.Connected()) {
+            continue;
+        }
+        if (clientData->state == ESTABLISHED) {
+            client.Send(buff, size);
+        }
+    }
+    return size;
+}
+
+bool EthernetTcpServer::Ready() {
+    bool full = true;
+    for (uint8_t iClient = 0; iClient < CLIENT_MAX; iClient++) {
+        if (m_tcpDataClient[iClient] == nullptr) {
+            full = false;
+            break;
+        }
+    }
+    return (m_initialized && !full);
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetUdp.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetUdp.cpp
new file mode 100644
index 000000000..a6b229498
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetUdp.cpp
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "EthernetUdp.h"
+#include "EthernetManager.h"
+
+namespace ClearCore {
+
+extern EthernetManager &EthernetMgr;
+
+EthernetUdp::EthernetUdp():
+    m_udpData({}),
+          m_udpLocalPort(0),
+          m_outgoingPacket(nullptr),
+          m_incomingPacket(nullptr),
+          m_udpBytesAvailable(0),
+          m_udpRemoteIpReceived(),
+          m_udpRemotePortReceived(0),
+          m_udpRemoteIpDestination(),
+          m_udpRemotePortDestination(0),
+          m_initialized(false),
+          m_packetBegun(false),
+          m_packetReadyToSend(false),
+m_packetParsed(false) { }
+
+bool EthernetUdp::Begin(uint16_t localPort) {
+    if (m_initialized) {
+        // Already initialized, nothing to do.
+        return false;
+    }
+
+    m_udpLocalPort = localPort;
+
+    // Set up the UDP state to pass to lwIP callbacks.
+    m_udpData.pcb = udp_new();
+    m_udpData.available = 0;
+    m_udpBytesAvailable = 0;
+
+    ip_addr_t ip = IPADDR4_INIT(uint32_t(EthernetMgr.LocalIp()));
+
+    // Bind the UDP PCB to the local IP and port.
+    err_t err = udp_bind(m_udpData.pcb, &ip, m_udpLocalPort);
+    if (err != ERR_OK) {
+        return false;
+    }
+
+    // Register the callback function upon receiving a UDP packet.
+    udp_recv(m_udpData.pcb, UdpReceive, &m_udpData);
+
+    m_packetBegun = false;
+    m_packetReadyToSend = false;
+    m_packetParsed = false;
+    m_initialized = true;
+
+    return m_initialized;
+}
+
+void EthernetUdp::End() {
+    if (!m_initialized) {
+        // Nothing to do.
+        return;
+    }
+
+    if (m_udpData.pcb != nullptr) {
+        // Remove the remote end of the PCB.
+        udp_disconnect(m_udpData.pcb);
+        // Remove PCB from the list of UDP PCBs and free the PCB.
+        udp_remove(m_udpData.pcb);
+        m_udpData.pcb = nullptr;
+    }
+
+    if (m_udpData.packet != nullptr) {
+        // Free the packet. Since there may be several packets chained together,
+        pbuf_free(m_udpData.packet);
+    }
+
+    m_udpData = {};
+
+    if (m_incomingPacket != nullptr) {
+        pbuf_free(m_incomingPacket);
+        m_incomingPacket = nullptr;
+    }
+
+    if (m_outgoingPacket != nullptr) {
+        pbuf_free(m_outgoingPacket);
+        m_outgoingPacket = nullptr;
+    }
+
+    m_udpLocalPort = 0;
+    m_udpRemoteIpReceived = IpAddress();
+    m_udpRemotePortReceived = 0;
+    m_udpBytesAvailable = 0;
+
+    m_packetParsed = false;
+    m_packetReadyToSend = false;
+    m_packetBegun = false;
+    m_initialized = false;
+}
+
+bool EthernetUdp::Connect(IpAddress ip, uint16_t port) {
+    if (!m_initialized) {
+        // Not initialized.
+        return false;
+    }
+    EthernetMgr.Refresh();
+    // Save the specified destination IP and port.
+    m_udpRemoteIpDestination = ip;
+    m_udpRemotePortDestination = port;
+
+    m_packetBegun = true;
+    m_packetReadyToSend = false;
+
+    return m_packetBegun;
+}
+
+bool EthernetUdp::PacketSend() {
+    if (!m_initialized || !m_packetBegun || !m_packetReadyToSend) {
+        return false;
+    }
+    // Try to send the outgoing data.
+    ip_addr_t destinationIp = IPADDR4_INIT(uint32_t(m_udpRemoteIpDestination));
+    err_t err = udp_sendto(m_udpData.pcb, m_outgoingPacket,
+                           &destinationIp, m_udpRemotePortDestination);
+
+    // Free the outgoing packet buffer chain.
+    pbuf_free(m_outgoingPacket);
+    m_outgoingPacket = nullptr;
+    m_udpRemoteIpDestination = IpAddress();
+    m_udpRemotePortDestination = 0;
+    m_packetBegun = false;
+    m_packetReadyToSend = false;
+
+    EthernetMgr.Refresh();
+
+    // Report whether data was sent successfully.
+    return err == ERR_OK;
+}
+
+uint32_t EthernetUdp::PacketWrite(uint8_t c) {
+    return PacketWrite(&c, 1);
+}
+
+uint32_t EthernetUdp::PacketWrite(const char *nullTermStr) {
+    uint32_t count = 0;
+    while (*nullTermStr) {
+        if (!PacketWrite(static_cast<uint8_t>(*nullTermStr++))) {
+            break;
+        }
+        count++;
+    }
+    return count;
+}
+
+uint32_t EthernetUdp::PacketWrite(const uint8_t *buffer, uint32_t size) {
+    err_t err;
+
+    if (!m_initialized || !m_packetBegun) {
+        // Not yet initialized or haven't called beginPacket() yet.
+        return 0;
+    }
+
+    EthernetMgr.Refresh();
+
+    if (m_outgoingPacket == nullptr) {
+        // Allocate a new pbuf to hold the outgoing data.
+        m_outgoingPacket = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+
+        if (m_outgoingPacket == nullptr) {
+            // Couldn't allocate an outgoing pbuf to hold data.
+            return 0;
+        }
+
+        // Copy data from the supplied buffer into the outgoing pbuf data.
+        err = pbuf_take(m_outgoingPacket, buffer, size);
+        if (err != ERR_OK) {
+            pbuf_free(m_outgoingPacket);
+            // Couldn't copy data from buffer into outgoing pbuf.
+            return 0;
+        }
+    }
+    else {
+        // The outgoing packet buffer already has some data in it that hasn't
+        // been sent yet. Allocate a new pbuf with enough size to hold the old
+        // data and the new data. After all the data is copied into the new pbuf
+        // re-assign the outgoing pbuf to this one.
+        struct pbuf *outgoing = pbuf_alloc(PBUF_TRANSPORT,
+                                           size + m_outgoingPacket->tot_len,
+                                           PBUF_RAM);
+        if (outgoing == nullptr) {
+            // Couldn't allocate a pbuf to hold all the data to write.
+            return 0;
+        }
+
+        err = pbuf_copy(outgoing, m_outgoingPacket);
+        if (err != ERR_OK) {
+            pbuf_free(outgoing);
+            // Couldn't copy the existing data into the outgoing pbuf.
+            return 0;
+        }
+
+        err = pbuf_take_at(outgoing, buffer, size, m_outgoingPacket->tot_len);
+        if (err != ERR_OK) {
+            pbuf_free(outgoing);
+            // Couldn't copy the new data into the outgoing pbuf.
+            return 0;
+        }
+
+        // Replace the outgoing packet with the newly built packet.
+        pbuf_free(m_outgoingPacket);
+        m_outgoingPacket = outgoing;
+    }
+
+    m_packetReadyToSend = true;
+
+    return m_outgoingPacket == nullptr ? 0 : size;
+}
+
+uint16_t EthernetUdp::PacketParse() {
+    EthernetMgr.Refresh();
+    if (!m_initialized || m_udpData.available == 0) {
+        return 0;
+    }
+
+    // Save the state of the received packet.
+    m_udpRemoteIpReceived = IpAddress(m_udpData.remoteIp.addr);
+    m_udpRemotePortReceived = m_udpData.remotePort;
+    m_udpBytesAvailable = m_udpData.available;
+
+    // Make this packet available to read by storing a copy as a class member.
+    // This prevents the received packet from being clobbered by subsequent
+    // received packets while attempting to do a chain of read()s on the
+    // original packet.
+    if (m_incomingPacket != nullptr) {
+        pbuf_free(m_incomingPacket);
+        m_incomingPacket = nullptr;
+    }
+
+    m_incomingPacket = pbuf_alloc(PBUF_TRANSPORT, m_udpData.packet->tot_len,
+                                  PBUF_RAM);
+    if (m_incomingPacket == nullptr) {
+        // Couldn't allocate a pbuf to copy the received packet into.
+        return 0;
+    }
+
+    err_t err = pbuf_copy(m_incomingPacket, m_udpData.packet);
+    if (err != ERR_OK) {
+        // Copy failed.
+        return 0;
+    }
+
+    // Free the received packet so we can receive another packet while reading
+    // the one we copied.
+    pbuf_free(m_udpData.packet);
+    m_udpData.packet = nullptr;
+    m_udpData.available = 0;
+
+    m_packetParsed = true;
+
+    return m_udpBytesAvailable;
+}
+
+uint16_t EthernetUdp::BytesAvailable() {
+    EthernetMgr.Refresh();
+    return m_udpBytesAvailable;
+}
+
+int32_t EthernetUdp::PacketRead(unsigned char *dataPtr, uint16_t length) {
+    if (!m_initialized) {
+        return -1;
+    }
+
+    if (!m_packetParsed || m_udpBytesAvailable == 0 || length == 0) {
+        // No valid data packet received or request to read nothing.
+        return -1;
+    }
+
+    // Limit read to what we have available.
+    if (m_udpBytesAvailable < length) {
+        length = m_udpBytesAvailable;
+    }
+
+    uint16_t bytesRead = UdpPacketRead(m_incomingPacket, &m_udpBytesAvailable,
+                                       dataPtr, length);
+
+    if (m_udpBytesAvailable == 0) {
+        // We've read all the bytes of the received packet so free it.
+        // Must call parsePacket() again before reading the next packet.
+        pbuf_free(m_incomingPacket);
+        m_incomingPacket = nullptr;
+        m_packetParsed = false;
+    }
+
+    return bytesRead == 0 ? -1 : bytesRead;
+}
+
+int16_t EthernetUdp::Peek() {
+    if (!m_initialized) {
+        return -1;
+    }
+
+    if (!m_packetParsed || m_udpBytesAvailable == 0) {
+        // No valid data packet received or request to read nothing.
+        return -1;
+    }
+
+    return pbuf_get_at(m_incomingPacket, 0);
+}
+
+void EthernetUdp::PacketFlush() {
+    if (!m_initialized || !m_packetParsed) {
+        return;
+    }
+
+    pbuf_free(m_incomingPacket);
+    m_incomingPacket = nullptr;
+}
+
+IpAddress EthernetUdp::RemoteIp() {
+    return m_udpRemoteIpReceived;
+}
+
+uint16_t EthernetUdp::RemotePort() {
+    return m_udpRemotePortReceived;
+}
+
+uint16_t EthernetUdp::UdpPacketRead(pbuf *packet, uint16_t *available,
+                                    unsigned char *buffer, uint16_t size) {
+    uint16_t bytesRead = 0;
+
+    // Read from incoming packet data as long as we have a packet to read with
+    // unread data available and there are requested bytes remaining to be read.
+    while (packet != nullptr && *available > 0 && bytesRead < size) {
+        // Calculate the location in the received packet to read from.
+        uint16_t offset = packet->tot_len - *available;
+
+        // Read byte by byte until there's nothing left to read:
+        // either we've read all available bytes, read all bytes requested,
+        // or we've exhausted the bytes available in the current pbuf and
+        // need to move on to the next pbuf in the chain to continue reading.
+        while ((*available > 0) && (bytesRead < size) &&
+                (offset < packet->len)) {
+            buffer[bytesRead++] = pbuf_get_at(packet, offset++);
+            (*available)--;
+        }
+        // If we haven't read all the bytes requested, check if we can move
+        // on to the next pbuf in the chain. If so, free the pbuf that had
+        // all of its data read.
+        if (bytesRead < size) {
+            pbuf *pbufToFree = packet;
+            packet = packet->next;
+
+            if (packet != nullptr) {
+                // Increase the ref count.
+                pbuf_ref(packet);
+            }
+            // Free the removed packet
+            pbuf_free(pbufToFree);
+        }
+    }
+    return bytesRead;
+}
+
+/**
+    lwIP UDP datagram received callback.
+**/
+void UdpReceive(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+                const ip_addr_t *addr, u16_t port) {
+    EthernetUdp::UdpData *data = (EthernetUdp::UdpData *)arg;
+
+    // Bail out if the udp_pcb received could not be allocated
+    // or if we received to an unregistered udp_pcb.
+    if (data == nullptr || data->pcb != pcb) {
+        pbuf_free(p);
+        return;
+    }
+
+    // Drop the last packet received.
+    if (data->packet != nullptr) {
+        pbuf_free(data->packet);
+    }
+
+    // Copy the remote IP, port, packet contents and number of bytes received
+    // into the UDP state.
+    ip_addr_copy(data->remoteIp, *addr);
+    data->remotePort = port;
+    data->packet = p;
+    data->available = p->tot_len;
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetUtils.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetUtils.cpp
new file mode 100644
index 000000000..3420d804c
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/EthernetUtils.cpp
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "EthernetUtils.h"
+#include "EthernetManager.h"
+#include "SysTiming.h"
+#include "lwip/dns.h"
+#include "lwip/ip_addr.h"
+
+namespace ClearCore {
+
+extern EthernetManager &EthernetMgr;
+
+void DnsFound(const char *hostname, const ip_addr_t *ip, void *arg) {
+    // Suppress unused param warning
+    (void)hostname;
+    uint32_t *hostIp = static_cast<uint32_t *>(arg);
+    if (hostIp == nullptr || ip == NULL) {
+        return;
+    }
+    // Move the resulting IP to the provided location in memory.
+    *(hostIp) = ip->addr;
+}
+
+err_t DnsGetHostByName(const char *hostname, ip_addr_t *remoteIp) {
+    // Allow a hostname to be a string of an IP Address.
+    if (ipaddr_aton(hostname, remoteIp) == 1) {
+        return ERR_OK;
+    }
+
+    // A location for the callback function to put the resulting IP.
+    uint32_t responseIp = 0;
+    // Check the local DNS table.
+    err_t err = dns_gethostbyname(hostname, remoteIp, DnsFound, &responseIp);
+
+    const uint16_t DNS_TIMEOUT = 2000;
+    // Timeout to wait for the queued DNS request response.
+    if (err == ERR_INPROGRESS) {
+        uint32_t startMs = Milliseconds();
+
+        while (responseIp == 0) {
+            EthernetMgr.Refresh();
+            if (Milliseconds() - startMs >= DNS_TIMEOUT) {
+                break; // Timed out.
+            }
+        }
+        // DNS request finished before the timeout.
+        if (responseIp != 0) {
+            remoteIp->addr = responseIp;
+            err = ERR_OK;
+        }
+    }
+    return err;
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/InputManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/InputManager.cpp
new file mode 100644
index 000000000..6b6706081
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/InputManager.cpp
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+    Implements the Input Manager class.
+
+    Provides consolidated access to the input states of all the ClearCore
+    connectors.
+ */
+
+#include "InputManager.h"
+#include <stddef.h>
+#include "atomic_utils.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+InputManager &InputMgr = InputManager::Instance();
+
+InputManager &InputManager::Instance() {
+    static InputManager *instance = new InputManager();
+    return *instance;
+}
+
+/**
+    Constructor
+**/
+InputManager::InputManager()
+    : m_inputPtrs(),
+      m_inputsUnfiltered { },
+      m_inputsUnfilteredChanges { },
+      m_inputRegRT(0),
+      m_inputRegRisen(0),
+      m_inputRegFallen(0),
+      m_interruptsMask(0),
+      m_interruptsEnabled(true),
+      m_interruptServiceRoutines(),
+      m_oneTimeFlags(0) {}
+
+/**
+    Initialize the InputManager.
+**/
+void InputManager::Initialize() {
+    SetInputRegisters(NULL, NULL, NULL);
+}
+
+void InputManager::SetInputRegisters(volatile uint32_t *a, volatile uint32_t *b,
+                                     volatile uint32_t *c) {
+    m_inputPtrs[PORTA] = a ? a : &PORT->Group[PORTA].IN.reg;
+    m_inputPtrs[PORTB] = b ? b : &PORT->Group[PORTB].IN.reg;
+    m_inputPtrs[PORTC] = c ? c : &PORT->Group[PORTC].IN.reg;
+}
+
+uint32_t InputManager::EicSense(InterruptTrigger trigger) {
+    // Logic on input pins is inverted: LOW <-> HIGH, RISING <-> FALLING
+    switch (trigger) {
+        case RISING:
+            return EIC_CONFIG_SENSE0_FALL;
+        case FALLING:
+            return EIC_CONFIG_SENSE0_RISE;
+        case CHANGE:
+            return EIC_CONFIG_SENSE0_BOTH;
+        case HIGH:
+            return EIC_CONFIG_SENSE0_LOW;
+        case LOW:
+            return EIC_CONFIG_SENSE0_HIGH;
+        default:
+            return EIC_CONFIG_SENSE0_NONE;
+    }
+}
+
+bool InputManager::InterruptHandlerSet(int8_t extInt, voidFuncPtr callback,
+                                       InterruptTrigger trigger, bool enable,
+                                       bool oneTime) {
+    if (extInt < 0 || extInt >= EIC_NUMBER_OF_INTERRUPTS) {
+        return false; // Invalid external interrupt number
+    }
+
+    EIC->CTRLA.bit.ENABLE = 0;
+    SYNCBUSY_WAIT(EIC, EIC_SYNCBUSY_ENABLE);
+
+    // Clear any existing interrupt flag
+    EIC->INTFLAG.reg = (1UL << extInt);
+
+    if (callback != nullptr) {
+        // Clear the existing interrupt trigger condition
+        uint8_t shiftAmt = 4 * (extInt % 8);
+        EIC->CONFIG[extInt / 8].reg &= ~(0xf << shiftAmt);
+
+        // Set the interrupt trigger condition
+        EIC->CONFIG[extInt / 8].reg |=
+            static_cast<uint32_t>(EicSense(trigger) << shiftAmt);
+    }
+    else {
+        enable = false;
+    }
+
+    m_interruptServiceRoutines[extInt] = callback;
+
+    if (oneTime) {
+        m_oneTimeFlags |= (1UL << extInt);
+    }
+    else  {
+        m_oneTimeFlags &= ~(1UL << extInt);
+    }
+
+    // Enable the interrupt if requested.
+    InterruptEnable(extInt, enable);
+
+    EIC->CTRLA.bit.ENABLE = 1;
+    SYNCBUSY_WAIT(EIC, EIC_SYNCBUSY_ENABLE);
+
+    return true;
+}
+
+void InputManager::InterruptEnable(int8_t extInt, bool enable,
+                                   bool clearPending) {
+    if (extInt < 0 || extInt >= EIC_NUMBER_OF_INTERRUPTS) {
+        return; // Invalid external interrupt number
+    }
+
+    if (enable) {
+        if (clearPending) {
+            // Clear any existing interrupt flag
+            EIC->INTFLAG.reg = (1UL << extInt);
+        }
+        atomic_or_fetch(&m_interruptsMask, (1UL << extInt));
+        if (m_interruptsEnabled) {
+            EIC->INTENSET.reg = (1UL << extInt);
+        }
+    }
+    else {
+        atomic_and_fetch(&m_interruptsMask, ~(1UL << extInt));
+        if (m_interruptsEnabled) {
+            EIC->INTENCLR.reg = (1UL << extInt);
+        }
+    }
+}
+
+void InputManager::InterruptsEnabled(bool enable) {
+    m_interruptsEnabled = enable;
+    if (enable) {
+        EIC->INTENSET.reg = atomic_load_n(&m_interruptsMask);
+    }
+    else {
+        EIC->INTENCLR.reg = atomic_load_n(&m_interruptsMask);
+    }
+}
+
+void InputManager::EIC_Handler(uint8_t index) {
+    if (index < EIC_NUMBER_OF_INTERRUPTS) {
+        // If this is a one time interrupt, disable the interrupt.
+        if (m_oneTimeFlags & (1UL << index)) {
+            atomic_and_fetch(&m_interruptsMask, ~(1UL << index));
+            EIC->INTENCLR.reg = (1UL << index);
+        }
+        // Ack the interrupt early so that we don't miss subsequent events
+        EIC->INTFLAG.reg = 1UL << index;
+        voidFuncPtr callback = m_interruptServiceRoutines[index];
+        if (callback != nullptr) {
+            callback();
+        }
+    }
+}
+
+void InputManager::UpdateBegin() {
+    for (int8_t iPort = 0; iPort < CLEARCORE_PORT_MAX; iPort++) {
+        uint32_t last = m_inputsUnfiltered[iPort];
+        m_inputsUnfiltered[iPort] = *m_inputPtrs[iPort];
+        m_inputsUnfilteredChanges[iPort] = m_inputsUnfiltered[iPort] ^ last;
+    }
+}
+
+void InputManager::UpdateEnd() {
+    atomic_fetch_or(&m_inputRegRisen.reg,
+                    m_inputRegRT.reg & (~m_inputRegLast.reg));
+    atomic_fetch_or(&m_inputRegFallen.reg,
+                    (~m_inputRegRT.reg) & m_inputRegLast.reg);
+    m_inputRegLast.reg = m_inputRegRT.reg;
+}
+
+SysConnectorState InputManager::InputsRisen(SysConnectorState mask) {
+    SysConnectorState retVal;
+    retVal.reg = atomic_fetch_and(&m_inputRegRisen.reg, ~mask.reg) & mask.reg;
+    return retVal;
+}
+
+SysConnectorState InputManager::InputsFallen(SysConnectorState mask) {
+    SysConnectorState retVal;
+    retVal.reg = atomic_fetch_and(&m_inputRegFallen.reg, ~mask.reg) & mask.reg;
+    return retVal;
+}
+
+SysConnectorState InputManager::InputsRT(SysConnectorState mask) {
+    SysConnectorState retVal;
+    retVal.reg = atomic_load_n(&m_inputRegRT.reg) & mask.reg;
+    return retVal;
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/LedDriver.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/LedDriver.cpp
new file mode 100644
index 000000000..4e77d4d3b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/LedDriver.cpp
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    LedDriver implementation
+
+    ClearCore LED shift register connector-level class implementation.
+**/
+
+#include "LedDriver.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+extern ShiftRegister ShiftReg;
+
+LedDriver::LedDriver(ShiftRegister::Masks ledMask)
+    : Connector(),
+      m_ledMask(ledMask) {}
+
+int16_t LedDriver::State() {
+    return static_cast<bool>(ShiftReg.ShifterState().reg & m_ledMask);
+}
+
+bool LedDriver::State(int16_t newState) {
+    ShiftReg.ShifterState(newState, m_ledMask);
+    return true;
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/MotorDriver.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/MotorDriver.cpp
new file mode 100644
index 000000000..9aa9f76fb
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/MotorDriver.cpp
@@ -0,0 +1,1042 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Implementation of ClearCore ClearPath motor connector
+**/
+
+#include "MotorDriver.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <sam.h>
+#include "atomic_utils.h"
+#include "CcioBoardManager.h"
+#include "Connector.h"
+#include "InputManager.h"
+#include "MotorManager.h"
+#include "StatusManager.h"
+#include "SysManager.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+
+#define HLFB_CARRIER_LOSS_ERROR_LIMIT (0)
+#define HLFB_CARRIER_LOSS_STATE_CHANGE_MS (4)
+#define HLFB_CARRIER_LOSS_STATE_CHANGE_SAMPLES (MS_TO_SAMPLES * HLFB_CARRIER_LOSS_STATE_CHANGE_MS)
+
+// TODO - name police, this is the amount of time we allow a move to execute
+// without expecting an HLFB reading to be back yet
+#define HARD_STOP_MOVE_MS (25)
+#define HARD_STOP_MOVE_SAMPLES (MS_TO_SAMPLES * HARD_STOP_MOVE_MS)
+
+namespace ClearCore {
+
+extern MotorManager &MotorMgr;
+extern SysManager SysMgr;
+extern SysTiming &TimingMgr;
+extern CcioBoardManager &CcioMgr;
+extern ShiftRegister ShiftReg;
+extern volatile uint32_t tickCnt;
+
+static Tcc *const tcc_modules[TCC_INST_NUM] = TCC_INSTS;
+
+// Needed to calculate the correct index into the CCBUF register
+// for a given TCC when constructing motor connectors.
+uint8_t TccCcNum(uint8_t tccNum) {
+    uint8_t tccCcNum;
+    switch (tccNum) {
+        case 0:
+            tccCcNum = TCC0_CC_NUM;
+            break;
+        case 1:
+            tccCcNum = TCC1_CC_NUM;
+            break;
+        case 2:
+            tccCcNum = TCC2_CC_NUM;
+            break;
+        case 3:
+            tccCcNum = TCC3_CC_NUM;
+            break;
+        case 4:
+            tccCcNum = TCC4_CC_NUM;
+            break;
+        default:
+            tccCcNum = 0;
+            break;
+    }
+    return tccCcNum;
+}
+
+/*
+    Construct and wire in our IO pins
+*/
+MotorDriver::MotorDriver(ShiftRegister::Masks enableMask,
+                         const PeripheralRoute *aInfo,
+                         const PeripheralRoute *bInfo,
+                         const PeripheralRoute *hlfbInfo,
+                         uint16_t hlfbTc,
+                         uint16_t hlfbEvt)
+    : DigitalIn(ShiftRegister::Masks::SR_NO_FEEDBACK_MASK, hlfbInfo),
+      m_enableMask(enableMask),
+      m_aInfo(aInfo),
+      m_bInfo(bInfo),
+      m_hlfbInfo(hlfbInfo),
+      m_aDataMask(1UL << aInfo->gpioPin),
+      m_bDataMask(1UL << bInfo->gpioPin),
+      m_enableConnector(CLEARCORE_PIN_INVALID),
+      m_inputAConnector(CLEARCORE_PIN_INVALID),
+      m_inputBConnector(CLEARCORE_PIN_INVALID),
+      m_hlfbTcNum(hlfbTc),
+      m_hlfbEvt(hlfbEvt),
+      m_hlfbMode(HLFB_MODE_STATIC),
+      m_hlfbWidth{0, 0},
+      m_hlfbPeriod{0, 0},
+      m_hlfbNoPwmSampleCount(2),
+      m_hlfbCarrierFrequency(HLFB_CARRIER_45_HZ),
+      m_hlfbCarrierLossStateChange_ms(HLFB_CARRIER_LOSS_STATE_CHANGE_MS_45_HZ),
+      m_hlfbLastCarrierDetectTime(UINT32_MAX),
+      m_hlfbDuty(HLFB_DUTY_UNKNOWN),
+      m_hlfbState(HLFB_UNKNOWN),
+      m_lastHlfbInputValue(false),
+      m_hlfbPwmReadingPending(false),
+      m_hlfbStateChangeCounter(MS_TO_SAMPLES * HLFB_CARRIER_LOSS_STATE_CHANGE_MS_45_HZ),
+      m_polarityInversions(0),
+      m_enableRequestedState(false),
+      m_enableTriggerActive(false),
+      m_enableTriggerPulseStartMs(0),
+      m_enableTriggerPulseCount(0),
+      m_enableTriggerPulseLenMs(25),
+      m_aDutyCnt(0),
+      m_bDutyCnt(0),
+      m_inFault(false),
+      m_statusRegMotor(0),
+      m_statusRegMotorRisen(0),
+      m_statusRegMotorFallen(0),
+      m_statusRegMotorLast(0),
+      m_alertRegMotor(0),
+      m_initialized(false),
+      m_isEnabling(false),
+      m_isEnabled(false),
+      m_hlfbCarrierLost(false),
+      m_enableCounter(0),
+      m_brakeOutputPin(CLEARCORE_PIN_INVALID),
+      m_limitSwitchNeg(CLEARCORE_PIN_INVALID),
+      m_limitSwitchPos(CLEARCORE_PIN_INVALID),
+      m_eStopConnector(CLEARCORE_PIN_INVALID),
+      m_motionCancellingEStop(false),
+      m_shiftRegEnableReq(false),
+      m_clearFaultState(CLEAR_FAULT_IDLE),
+      m_clearFaultHlfbTimer(0) {
+
+    m_interruptAvail = true;
+
+    Tcc *theTcc = (tcc_modules[m_aInfo->tccNum]);
+    uint8_t ccIndex = m_aInfo->tccPadNum % TccCcNum(m_aInfo->tccNum);
+    m_aTccBuffer = &theTcc->CCBUF[ccIndex].reg;
+    m_aTccSyncMask = TCC_SYNCBUSY_CC(1UL << ccIndex);
+    m_aTccSyncReg = &theTcc->SYNCBUSY.reg;
+
+    theTcc = (tcc_modules[m_bInfo->tccNum]);
+    ccIndex = m_bInfo->tccPadNum % TccCcNum(m_bInfo->tccNum);
+    m_bTccBuffer = &theTcc->CCBUF[ccIndex].reg;
+    m_bTccSyncMask = TCC_SYNCBUSY_CC(1UL << ccIndex);
+    m_bTccSyncReg = &theTcc->SYNCBUSY.reg;
+}
+
+
+/*
+    Update the HLFB state
+*/
+void MotorDriver::Refresh() {
+    if (!m_initialized) {
+        return;
+    }
+
+    // Process the HLFB input as static levels/filtering
+    DigitalIn::Refresh();
+
+    // Pointer to our TC
+    static Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+    TcCount16 *tcCount = &tc_modules[m_hlfbTcNum]->COUNT16;
+    uint8_t intFlagReg = tcCount->INTFLAG.reg;
+
+    bool invert = (m_mode == CPM_MODE_STEP_AND_DIR) &&
+                  m_polarityInversions.bit.hlfbInverted;
+
+    // Process the HLFB information
+    switch (m_hlfbMode) {
+        case HLFB_MODE_HAS_PWM:
+        case HLFB_MODE_HAS_BIPOLAR_PWM:
+            // Check for overflow or error conditions
+            if ((intFlagReg & (TC_INTFLAG_OVF | TC_INTFLAG_ERR)) ||
+                (Milliseconds() - m_hlfbLastCarrierDetectTime
+                    >= HLFB_CARRIER_LOSS_STATE_CHANGE_MS)) {
+                tcCount->INTFLAG.reg = TC_INTFLAG_OVF | TC_INTFLAG_MC0 |
+                                       TC_INTFLAG_ERR | TC_INTFLAG_MC1;
+                // Saturating increment
+                m_hlfbNoPwmSampleCount = __QADD16(m_hlfbNoPwmSampleCount, 1U);
+                m_hlfbCarrierLost =
+                    m_hlfbNoPwmSampleCount > HLFB_CARRIER_LOSS_ERROR_LIMIT;
+            }
+            // Did we capture a period?
+            if (intFlagReg & TC_INTFLAG_MC0) {
+                m_hlfbLastCarrierDetectTime = Milliseconds();
+
+                if (m_hlfbNoPwmSampleCount) {
+                    // When coming out of overflow/error conditions do not use
+                    // the next measurement because the pulse may be clipped
+                    tcCount->INTFLAG.reg = TC_INTFLAG_MC0 | TC_INTFLAG_MC1;
+                    m_hlfbPwmReadingPending = false;
+                    m_hlfbNoPwmSampleCount = 0;
+                }
+                else if (intFlagReg & TC_INTFLAG_MC1) {
+                    // Save history and use only the (n-1)st item to return as the
+                    // last PWM captured might be clipped in a move done case.
+                    m_hlfbWidth[0] = m_hlfbWidth[CPM_HLFB_CAP_HISTORY - 1];
+                    m_hlfbPeriod[0] = m_hlfbPeriod[CPM_HLFB_CAP_HISTORY - 1];
+                    m_hlfbWidth[CPM_HLFB_CAP_HISTORY - 1] = tcCount->CC[1].reg;
+                    m_hlfbPeriod[CPM_HLFB_CAP_HISTORY - 1] = tcCount->CC[0].reg;
+
+                    // Both period and pulse width have been captured
+                    // If this is the first valid pulse, wait until a second
+                    // pulse is seen before announcing that a measurement is
+                    // present. This ensures that the pulse isn't being clipped
+                    // by having the signal go away.
+                    if (m_hlfbPwmReadingPending) {
+                        m_hlfbCarrierLost = false;
+                        float dutyCycle = static_cast<float>(m_hlfbWidth[0]) /
+                                          static_cast<float>(m_hlfbPeriod[0]);
+                        // Convert to floating and inflate 5-95% to 0-100%
+                        m_hlfbDuty = (dutyCycle - 0.05) * (10000. / 90.);
+
+                        if (invert) {
+                            m_hlfbDuty = 100 - m_hlfbDuty;
+                        }
+
+                        // Convert unipolar to bipolar?
+                        if (m_hlfbMode == HLFB_MODE_HAS_BIPOLAR_PWM) {
+                            m_hlfbDuty = 2.0 * (m_hlfbDuty - 50.);
+                        }
+                        m_hlfbState = HLFB_HAS_MEASUREMENT;
+                    }
+                    m_hlfbPwmReadingPending = true;
+                }
+            }
+
+            if (!m_hlfbCarrierLost) {
+                m_hlfbStateChangeCounter = (MS_TO_SAMPLES * m_hlfbCarrierLossStateChange_ms);
+                break;
+            }
+            else {
+                // check for an HLFB state change
+                bool readHlfbState = (DigitalIn::m_stateFiltered ^ invert);
+                if (readHlfbState != m_lastHlfbInputValue) {
+                    m_hlfbStateChangeCounter = (MS_TO_SAMPLES * m_hlfbCarrierLossStateChange_ms);
+                    m_lastHlfbInputValue = readHlfbState;
+                    break;
+                }
+                else if (m_hlfbStateChangeCounter && m_hlfbStateChangeCounter--) {
+                    break;
+                }
+            }
+
+        // Fall through to process as a static signal if the carrier is lost
+        case HLFB_MODE_STATIC:
+        default:
+            m_hlfbDuty = HLFB_DUTY_UNKNOWN;
+            m_hlfbState = (DigitalIn::m_stateFiltered ^ invert) ?
+                          HLFB_ASSERTED : HLFB_DEASSERTED;
+            break;
+    }
+
+    // Read associated input connectors and write associated output connectors.
+    if (m_enableConnector != CLEARCORE_PIN_INVALID) {
+        // Update the Enable state with the value on the Enable connector.
+        Connector *input= SysMgr.ConnectorByIndex(m_enableConnector);
+        if (input->Type() == ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE) {
+            EnableRequest(CcioMgr.PinState(m_enableConnector));
+        }
+        else {
+            DigitalIn *enableIn = static_cast<DigitalIn *>(input);
+            EnableRequest(enableIn->DigitalIn::State());
+        }
+    }
+    if (m_inputAConnector != CLEARCORE_PIN_INVALID && m_mode != CPM_MODE_STEP_AND_DIR) {
+        // Update the Input A state with the value on the Input A connector.
+        Connector *input= SysMgr.ConnectorByIndex(m_inputAConnector);
+        if (input->Type() == ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE) {
+            MotorInAState(CcioMgr.PinState(m_inputAConnector));
+        }
+        else {
+            DigitalIn *inputA = static_cast<DigitalIn *>(input);
+            MotorInAState(inputA->DigitalIn::State());
+        }
+    }
+    if (m_inputBConnector != CLEARCORE_PIN_INVALID && m_mode != CPM_MODE_STEP_AND_DIR) {
+        // Update the Input B state with the value on the Input B connector.
+        Connector *input= SysMgr.ConnectorByIndex(m_inputBConnector);
+        if (input->Type() == ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE) {
+            MotorInBState(CcioMgr.PinState(m_inputBConnector));
+        }
+        else {
+            DigitalIn *inputB = static_cast<DigitalIn *>(input);
+            MotorInBState(inputB->DigitalIn::State());
+        }
+    }
+    if (m_brakeOutputPin != CLEARCORE_PIN_INVALID) {
+        Connector *brakeOutput = SysMgr.ConnectorByIndex(m_brakeOutputPin);
+        if (brakeOutput->Type() == CCIO_DIGITAL_IN_OUT_TYPE ||
+        brakeOutput->Mode() == ConnectorModes::OUTPUT_DIGITAL) {
+            // Using HLFB_MODE_STATIC assumes the motor is in Servo On HLFB mode
+            if (m_hlfbMode == HLFB_MODE_STATIC) {
+                brakeOutput->State(static_cast<int16_t>(m_hlfbState == HLFB_ASSERTED));
+            }
+            else {
+                brakeOutput->State(static_cast<int16_t>(m_hlfbState != HLFB_DEASSERTED));
+            }
+        }
+    }
+    if (m_limitSwitchPos != CLEARCORE_PIN_INVALID) {
+        // Update the positive limit state with the value on the connector.
+        Connector *input = SysMgr.ConnectorByIndex(m_limitSwitchPos);
+        if (input->Type() == CCIO_DIGITAL_IN_OUT_TYPE) {
+            PosLimitActive(!input->State());
+        }
+        else {
+            DigitalIn *inputB = static_cast<DigitalIn *>(input);
+            PosLimitActive(!inputB->DigitalIn::State());
+        }
+    }
+    if (m_limitSwitchNeg != CLEARCORE_PIN_INVALID) {
+        // Update the negative limit state with the value on the connector.
+        Connector *input = SysMgr.ConnectorByIndex(m_limitSwitchNeg);
+        if (input->Type() == CCIO_DIGITAL_IN_OUT_TYPE) {
+            NegLimitActive(!input->State());
+        }
+        else {
+            DigitalIn *inputB = static_cast<DigitalIn *>(input);
+            NegLimitActive(!inputB->DigitalIn::State());
+        }
+    }
+
+
+    // Update the Motor Status and Alert Registers
+    StatusRegMotor statusRegPending = m_statusRegMotor;
+    AlertRegMotor alertRegPending = m_alertRegMotor;
+
+    // Check E-stop
+    bool eStopInput = CheckEStopSensor();
+    if (m_moveState == MS_IDLE) {
+        m_motionCancellingEStop = false;
+    }
+    else if (eStopInput && !m_motionCancellingEStop) {
+        MoveStopDecel();
+        m_motionCancellingEStop = true;
+        alertRegPending.bit.MotionCanceledSensorEStop = 1;
+    }
+    statusRegPending.bit.InEStopSensor = (eStopInput || m_motionCancellingEStop);
+
+    // Check limits
+    if (!m_lastMoveWasPositional && m_statusRegMotor.bit.StepsActive) {
+        if (m_direction && m_limitInfo.InNegHWLimit) {
+            alertRegPending.bit.MotionCanceledNegativeLimit = 1;
+        }
+        else if (!m_direction && m_limitInfo.InPosHWLimit) {
+            alertRegPending.bit.MotionCanceledPositiveLimit = 1;
+        }
+    }
+
+    statusRegPending.bit.InPositiveLimit = m_limitInfo.InPosHWLimit;
+    statusRegPending.bit.InNegativeLimit = m_limitInfo.InNegHWLimit;
+
+    statusRegPending.bit.Triggering = m_enableTriggerActive;
+    statusRegPending.bit.MoveDirection = StepGenerator::m_direction;
+    statusRegPending.bit.StepsActive =
+        (StepGenerator::m_moveState != StepGenerator::MoveStates::MS_IDLE &&
+            StepGenerator::m_moveState != StepGenerator::MoveStates::MS_END);
+    statusRegPending.bit.AtTargetPosition = m_isEnabled && 
+        m_lastMoveWasPositional && !statusRegPending.bit.StepsActive &&
+        m_hlfbState == HLFB_ASSERTED;
+    statusRegPending.bit.AtTargetVelocity = m_isEnabled &&
+        (StepGenerator::m_moveState == StepGenerator::MoveStates::MS_CRUISE ||
+        (!statusRegPending.bit.StepsActive && !m_lastMoveWasPositional)) &&
+        m_hlfbState != HLFB_DEASSERTED;
+    statusRegPending.bit.PositionalMove = m_lastMoveWasPositional;
+
+    statusRegPending.bit.HlfbState = m_hlfbState;
+
+    if (m_isEnabling) {
+        if (m_enableCounter > 0) {
+            m_enableCounter--;
+        }
+        else {
+            m_isEnabled = true;
+            m_isEnabling = false;
+        }
+    }
+    statusRegPending.bit.Enabled = m_isEnabled;
+
+    if (!(m_isEnabled || m_isEnabling)) {
+        statusRegPending.bit.ReadyState = MotorReadyStates::MOTOR_DISABLED;
+        if (statusRegPending.bit.StepsActive) {
+            alertRegPending.bit.MotionCanceledMotorDisabled = 1;
+        }
+    }
+    else if (m_isEnabling) {
+        statusRegPending.bit.ReadyState = MotorReadyStates::MOTOR_ENABLING;
+    }
+    else {
+        if (m_hlfbMode != HLFB_MODE_STATIC &&
+            m_hlfbState == HlfbStates::HLFB_DEASSERTED) {
+            statusRegPending.bit.ReadyState = MotorReadyStates::MOTOR_FAULTED;
+            statusRegPending.bit.MotorInFault = 1;
+            alertRegPending.bit.MotorFaulted = 1;
+            MoveStopAbrupt();
+
+        }
+        else if ((m_hlfbMode == HLFB_MODE_STATIC &&
+                  m_hlfbState == MotorDriver::HlfbStates::HLFB_DEASSERTED) ||
+                 statusRegPending.bit.StepsActive) {
+            statusRegPending.bit.ReadyState = MotorReadyStates::MOTOR_MOVING;
+        }
+        else {
+            statusRegPending.bit.ReadyState = MotorReadyStates::MOTOR_READY;
+            statusRegPending.bit.MotorInFault = 0;
+        }
+    }
+
+    if (statusRegPending.bit.StepsActive) {
+        if (alertRegPending.bit.MotorFaulted) {
+            alertRegPending.bit.MotionCanceledInAlert = 1;
+        }
+    }
+
+    statusRegPending.bit.AlertsPresent = (bool)alertRegPending.reg;
+    m_statusRegMotor = statusRegPending;
+    m_alertRegMotor = alertRegPending;
+
+    atomic_or_fetch(&m_statusRegMotorRisen.reg,
+                    ~m_statusRegMotorLast.reg & statusRegPending.reg);
+    atomic_or_fetch(&m_statusRegMotorFallen.reg,
+                    m_statusRegMotorLast.reg & ~statusRegPending.reg);
+
+    m_statusRegMotorLast.reg = m_statusRegMotor.reg;
+
+    // Calculate the next S&D output step count
+    if (Connector::m_mode == Connector::CPM_MODE_STEP_AND_DIR) {
+        // Calculate the number of steps to send in the next sample time
+        StepGenerator::StepsCalculated();
+        // Check the status of the limits
+        StepGenerator::CheckTravelLimits();
+
+        m_bDutyCnt = StepGenerator::m_stepsPrevious;
+        // Queue up the steps by writing the B duty value
+        UpdateBDuty();
+    }
+}
+
+bool MotorDriver::ValidateMove(bool negDirection) {
+    bool valid = true;
+    if (m_alertRegMotor.reg) {
+        m_alertRegMotor.bit.MotionCanceledInAlert = 1;
+        valid = false;
+    }
+    if (!EnableRequest()) {
+        m_alertRegMotor.bit.MotionCanceledMotorDisabled = 1;
+        valid = false;
+    }
+    if (CheckEStopSensor()) {
+        m_alertRegMotor.bit.MotionCanceledSensorEStop = 1;
+        valid = false;
+    }
+    // Check +/- hardware limits
+    if (negDirection && m_limitInfo.InNegHWLimit) {
+        m_alertRegMotor.bit.MotionCanceledNegativeLimit = 1;
+        valid = false;
+    }
+    else if (!negDirection && m_limitInfo.InPosHWLimit) {
+        m_alertRegMotor.bit.MotionCanceledPositiveLimit = 1;
+        valid = false;
+    }
+    return valid;
+}
+
+bool MotorDriver::Move(int32_t dist, MoveTarget moveTarget) {
+    bool negDir;
+
+    if (moveTarget == MOVE_TARGET_ABSOLUTE) {
+        negDir = dist - m_posnAbsolute < 0;
+    }
+    else {
+        negDir = dist < 0;
+    }
+
+    if (!ValidateMove(negDir)) {
+        if (m_statusRegMotor.bit.StepsActive ) {
+            MoveStopDecel();
+        }
+        return false;
+    }
+
+    m_lastMoveWasPositional = true;
+    return StepGenerator::Move(dist, moveTarget);
+}
+
+bool MotorDriver::MoveVelocity(int32_t velocity) {
+    if (!ValidateMove(velocity < 0)) {
+        if (m_statusRegMotor.bit.StepsActive ) {
+            MoveStopDecel();
+        }
+        return false;
+    }
+    m_lastMoveWasPositional = false;
+    return StepGenerator::MoveVelocity(velocity);
+}
+
+MotorDriver::StatusRegMotor MotorDriver::StatusRegRisen() {
+    return StatusRegMotor(atomic_exchange_n(&m_statusRegMotorRisen.reg, 0));
+}
+
+MotorDriver::StatusRegMotor MotorDriver::StatusRegFallen() {
+    return StatusRegMotor(atomic_exchange_n(&m_statusRegMotorFallen.reg, 0));
+}
+
+bool MotorDriver::MotorInAState() {
+    bool retVal = !(PORT->Group[m_aInfo->gpioPort].OUT.reg & m_aDataMask);
+    if (Connector::m_mode == Connector::CPM_MODE_STEP_AND_DIR &&
+            m_polarityInversions.bit.directionInverted) {
+        retVal = !retVal;
+    }
+
+    return retVal;
+}
+
+bool MotorDriver::MotorInBState() {
+    return !(PORT->Group[m_bInfo->gpioPort].OUT.reg & m_bDataMask);
+}
+
+bool MotorDriver::MotorInAState(bool value) {
+    switch (m_mode) {
+        case Connector::CPM_MODE_A_DIRECT_B_DIRECT:
+        case Connector::CPM_MODE_A_DIRECT_B_PWM:
+            DATA_OUTPUT_STATE(m_aInfo->gpioPort, m_aDataMask, !value);
+            return true;
+        case Connector::CPM_MODE_A_PWM_B_PWM:
+            //MotorInACount(value ? m_stepsPerSampleMax : 0);
+            //return true;
+        case Connector::CPM_MODE_STEP_AND_DIR:
+        default:
+            return false;
+    }
+}
+
+bool MotorDriver::MotorInBState(bool value) {
+    switch (m_mode) {
+        case Connector::CPM_MODE_A_DIRECT_B_DIRECT:
+            DATA_OUTPUT_STATE(m_bInfo->gpioPort, m_bDataMask, !value);
+            return true;
+        case Connector::CPM_MODE_A_DIRECT_B_PWM:
+        case Connector::CPM_MODE_A_PWM_B_PWM:
+            //MotorInBCount(value ? m_stepsPerSampleMax : 0);
+            //return true;
+        case Connector::CPM_MODE_STEP_AND_DIR:
+        default:
+            return false;
+    }
+}
+
+bool MotorDriver::MotorInADuty(uint8_t duty) {
+    if (Connector::m_mode == Connector::CPM_MODE_A_PWM_B_PWM) {
+        m_aDutyCnt = (static_cast<uint32_t>(duty) * m_stepsPerSampleMax +
+                      (UINT8_MAX / 2)) / UINT8_MAX;
+        UpdateADuty();
+        return true;
+    }
+    return false;
+}
+
+bool MotorDriver::MotorInBDuty(uint8_t duty) {
+    if (Connector::m_mode == Connector::CPM_MODE_A_DIRECT_B_PWM ||
+            Connector::m_mode == Connector::CPM_MODE_A_PWM_B_PWM) {
+        m_bDutyCnt = (static_cast<uint32_t>(duty) * m_stepsPerSampleMax +
+                      (UINT8_MAX / 2)) / UINT8_MAX;
+        UpdateBDuty();
+        return true;
+    }
+    return false;
+}
+
+bool MotorDriver::MotorInACount(uint16_t count) {
+    if (Connector::m_mode == Connector::CPM_MODE_A_PWM_B_PWM) {
+        m_aDutyCnt = count;
+        UpdateADuty();
+        return true;
+    }
+    return false;
+}
+
+bool MotorDriver::MotorInBCount(uint16_t count) {
+    if (Connector::m_mode == Connector::CPM_MODE_A_DIRECT_B_PWM ||
+    Connector::m_mode == Connector::CPM_MODE_A_PWM_B_PWM) {
+        m_bDutyCnt = count;
+        UpdateBDuty();
+        return true;
+    }
+    return false;
+}
+
+void MotorDriver::EnableTriggerPulse(uint16_t pulseCount, uint32_t time_ms,
+                                     bool blockUntilDone) {
+    // If not enabled, just return without doing anything.
+    if (!EnableRequest() || m_inFault) {
+        return;
+    }
+
+    __disable_irq();
+    if (m_enableTriggerActive) {
+        m_enableTriggerPulseCount += (pulseCount * 2);
+    }
+    else if (pulseCount) {
+        m_enableTriggerPulseStartMs = TimingMgr.Milliseconds();
+        m_enableTriggerPulseCount = (pulseCount * 2);
+        m_enableTriggerActive = true;
+        ToggleEnable();
+    }
+    m_enableTriggerPulseLenMs = time_ms;
+    __enable_irq();
+
+    if (blockUntilDone) {
+        while (EnableTriggerPulseActive()) {
+            continue;
+        }
+    }
+}
+
+void MotorDriver::EnableRequest(bool value) {
+    bool wasDisabled = !(m_isEnabled || m_isEnabling);
+    bool wasPulsing = m_enableTriggerActive;
+
+    if (value != m_enableRequestedState || m_inFault) {
+        m_enableTriggerActive = false;
+        m_enableTriggerPulseCount = 0;
+    }
+
+    m_enableRequestedState = value;
+    // Make sure to disable if we're in a fault state.
+    // Otherwise, faithfully handle the request.
+    value = !m_inFault && value;
+
+    __disable_irq();
+
+    if (wasDisabled && value) {
+        // If we're enabling, set the enable delay.
+        m_enableCounter = CPM_ENABLE_DELAY;
+        // Set the enabling state based on the enable request.
+        m_isEnabling = true;
+    }
+    else if (!value) {
+        m_isEnabled = false;
+    }
+    __enable_irq();
+
+    // Invert the logic if necessary.
+    if (m_mode == Connector::CPM_MODE_STEP_AND_DIR) {
+        if (!value && m_statusRegMotor.bit.StepsActive) {
+            m_alertRegMotor.bit.MotionCanceledMotorDisabled = 1;
+            MoveStopAbrupt();
+        }
+        if (m_polarityInversions.bit.enableInverted) {
+            value = !value;
+        }
+    }
+
+    if (value != m_shiftRegEnableReq || (wasPulsing && !m_enableTriggerActive)) {
+        // Update the shift register.
+        ShiftReg.ShifterState(value, m_enableMask);
+    }
+     m_shiftRegEnableReq = value;
+}
+
+void MotorDriver::ToggleEnable() {
+    // Update the shift register.
+    ShiftReg.ShifterStateToggle(m_enableMask);
+}
+
+bool MotorDriver::PolarityInvertSDEnable(bool invert) {
+    if (m_mode == Connector::CPM_MODE_STEP_AND_DIR) {
+        m_polarityInversions.bit.enableInverted = invert ? 1 : 0;
+        EnableRequest(m_enableRequestedState);
+        return true;
+    }
+    else {
+        return false;
+    }
+}
+
+bool MotorDriver::PolarityInvertSDDirection(bool invert) {
+    if (m_mode == Connector::CPM_MODE_STEP_AND_DIR) {
+        m_polarityInversions.bit.directionInverted = invert ? 1 : 0;
+        return true;
+    }
+    else {
+        return false;
+    }
+}
+
+bool MotorDriver::PolarityInvertSDHlfb(bool invert) {
+    if (m_mode == Connector::CPM_MODE_STEP_AND_DIR) {
+        m_polarityInversions.bit.hlfbInverted = invert ? 1 : 0;
+        // Force the HLFB filtering to re-evaluate by setting TicksLeft
+        m_filterTicksLeft = 1;
+        return true;
+    }
+    else {
+        return false;
+    }
+}
+
+bool MotorDriver::BrakeOutput(ClearCorePins pin) {
+    if (pin != m_brakeOutputPin && m_brakeOutputPin != CLEARCORE_PIN_INVALID) {
+        // Reset the state of the previously-set brake output connector
+        SysMgr.ConnectorByIndex(m_brakeOutputPin)->State(false);
+    }
+
+    return SetConnector(pin, m_brakeOutputPin, false);
+}
+
+bool MotorDriver::LimitSwitchPos(ClearCorePins pin) {
+    bool retVal = SetConnector(pin, m_limitSwitchPos);
+    if (m_limitSwitchPos == CLEARCORE_PIN_INVALID) {
+        PosLimitActive(false);
+    }
+    return retVal;
+}
+
+bool MotorDriver::LimitSwitchNeg(ClearCorePins pin) {
+    bool retVal = SetConnector(pin, m_limitSwitchNeg);
+    if (m_limitSwitchNeg == CLEARCORE_PIN_INVALID) {
+        NegLimitActive(false);
+    }
+    return retVal;
+}
+
+bool MotorDriver::EnableConnector(ClearCorePins pin) {
+    return SetConnector(pin, m_enableConnector);
+}
+
+bool MotorDriver::InputAConnector(ClearCorePins pin) {
+    return SetConnector(pin, m_inputAConnector);
+}
+
+bool MotorDriver::InputBConnector(ClearCorePins pin) {
+    return SetConnector(pin, m_inputBConnector);
+}
+
+bool MotorDriver::EStopConnector(ClearCorePins pin) {
+    return SetConnector(pin, m_eStopConnector);
+}
+
+void MotorDriver::Initialize(ClearCorePins clearCorePin) {
+    // Initialize the output values
+    DATA_OUTPUT_STATE(m_aInfo->gpioPort, m_aDataMask, true);
+    DATA_OUTPUT_STATE(m_bInfo->gpioPort, m_bDataMask, true);
+    EnableRequest(false);
+
+    // Initialize the HLFB
+    DigitalIn::Initialize(clearCorePin);
+
+    // Disable mux
+    PIN_CONFIGURATION(m_aInfo->gpioPort, m_aInfo->gpioPin,  0);
+    PIN_CONFIGURATION(m_bInfo->gpioPort, m_bInfo->gpioPin,  0);
+
+    // Setup a and b as output
+    DATA_DIRECTION_OUTPUT(m_aInfo->gpioPort, m_aDataMask);
+    DATA_DIRECTION_OUTPUT(m_bInfo->gpioPort, m_bDataMask);
+
+    // Configure the MotorInAState MUX for TCC, but don't enable it unless we go
+    // into that mode
+    PMUX_SELECTION(m_aInfo->gpioPort, m_aInfo->gpioPin, PER_TIMER_ALT);
+
+    // Configure the MotorInBState MUX for TCC, but don't enable it unless we go
+    // into that mode
+    PMUX_SELECTION(m_bInfo->gpioPort, m_bInfo->gpioPin, PER_TIMER_ALT);
+
+    Mode(CPM_MODE_A_DIRECT_B_DIRECT);
+
+    // Connect PAD to External Interrupt device
+    PMUX_SELECTION(m_inputPort, m_inputDataBit, PER_EXTINT);
+    PMUX_ENABLE(m_inputPort, m_inputDataBit);
+
+    // Pointer to our TC
+    static Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+    TcCount16 *tcCount = &tc_modules[m_hlfbTcNum]->COUNT16;
+    // Turn off TC to allow setup
+    tcCount->CTRLA.bit.ENABLE = 0;
+    // Sync clocks
+    SYNCBUSY_WAIT(tcCount, TC_SYNCBUSY_ENABLE);
+
+    tcCount->CTRLA.bit.SWRST = 1;
+    SYNCBUSY_WAIT(tcCount, TC_SYNCBUSY_SWRST);
+
+    tcCount->CTRLA.bit.PRESCSYNC = TC_CTRLA_PRESCSYNC_GCLK_Val;
+    // Capture operation on channel 1 and 2 triggered from Event System
+    tcCount->CTRLA.bit.COPEN0 = 0;
+    tcCount->CTRLA.bit.COPEN1 = 0;
+    // Enables capture on channel 1 and 2 (vs compare)
+    tcCount->CTRLA.bit.CAPTEN0 = 1;
+    tcCount->CTRLA.bit.CAPTEN1 = 1;
+    // The LUPD bit is not affected on overflow/underflow and re-trigger event
+    tcCount->CTRLA.bit.ALOCK = 0;
+    // Prescaler: GCLK_TC
+    tcCount->CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV1_Val;
+    // Clock On Demand, TC will not request the clock when stopped
+    tcCount->CTRLA.bit.ONDEMAND = 1;
+    // Run in Standby, the TC continues to run in standby
+    tcCount->CTRLA.bit.RUNSTDBY = 1;
+    // Set the counter to 16 bit mode
+    tcCount->CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT16_Val;
+
+    // Select the count event action
+    tcCount->EVCTRL.bit.EVACT = TC_EVCTRL_EVACT_PPW_Val;
+    // Enable async input events to the TC
+    tcCount->EVCTRL.bit.TCEI = 1;
+    // Disable match/capture event
+    tcCount->EVCTRL.bit.MCEO0 = 0;
+    tcCount->EVCTRL.bit.MCEO1 = 0;
+    // Disable overflow/underflow event
+    tcCount->EVCTRL.bit.OVFEO = 0;
+    tcCount->EVCTRL.bit.TCINV = 1;
+
+    // Setup External Interrupt resource
+    EIC->CTRLA.bit.ENABLE = 0;
+    // Enable the corresponding output events
+    EIC->EVCTRL.reg |= 1 << m_hlfbInfo->extInt;
+    // Enable asynchronous edge detection operation
+    EIC->ASYNCH.reg |= 1 << m_hlfbInfo->extInt;
+    // See 28.8.10 in data sheet to see CONFIG register structure. 3-bit field
+    // every 4 bits.
+    EIC->CONFIG[m_hlfbInfo->extInt / 8].reg |=
+        (EIC_CONFIG_SENSE0_HIGH_Val << ((m_hlfbInfo->extInt & 7) * 4));
+    EIC->INTENCLR.bit.EXTINT = 1 << m_hlfbInfo->extInt;
+
+    EIC->CTRLA.bit.ENABLE = 1;
+    SYNCBUSY_WAIT(EIC, EIC_SYNCBUSY_ENABLE);
+
+    // Clock the channel
+    SET_CLOCK_SOURCE(EVSYS_GCLK_ID_0 + m_hlfbEvt, 6);
+
+    EvsysChannel *theEvCh = &EVSYS->Channel[m_hlfbEvt];
+    // Configure the event user mux to connect the channel to the event
+    EVSYS->USER[EVSYS_ID_USER_TC0_EVU + m_hlfbTcNum].reg = m_hlfbEvt + 1;
+    theEvCh->CHINTFLAG.bit.EVD = 1;
+    while (theEvCh->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) {
+        continue;
+    }
+    // Configure the event channel to use the ExtInt event, async
+    theEvCh->CHANNEL.reg =
+        EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_EIC_EXTINT_0 + m_hlfbInfo->extInt) |
+        EVSYS_CHANNEL_PATH_ASYNCHRONOUS;
+    while (theEvCh->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) {
+        continue;
+    }
+    // Turn on timer
+    tcCount->CTRLA.bit.ENABLE = 1;
+    // Sync clocks
+    SYNCBUSY_WAIT(tcCount, TC_SYNCBUSY_ENABLE);
+
+    // Initialize the Motor Status Registers
+    m_statusRegMotor.reg = 0;
+    m_statusRegMotorRisen.reg = 0;
+    m_statusRegMotorFallen.reg = 0;
+
+    m_initialized = true;
+}
+
+bool MotorDriver::Mode(ConnectorModes newMode) {
+    // Bail out if we are already in the requested mode
+    if (newMode == m_mode) {
+        return true;
+    }
+
+    switch (newMode) {
+        case CPM_MODE_A_PWM_B_PWM:
+            // Stop any active S&D command
+            MoveStopAbrupt();
+            // Block the interrupt and make sure that the PWM values are cleared
+            __disable_irq();
+            m_aDutyCnt = 0;
+            UpdateADuty();
+            m_bDutyCnt = 0;
+            UpdateBDuty();
+            // Enable peripheral on port/pin A and B to use PWM on both
+            PMUX_ENABLE(m_aInfo->gpioPort, m_aInfo->gpioPin);
+            PMUX_ENABLE(m_bInfo->gpioPort, m_bInfo->gpioPin);
+            m_mode = newMode;
+            __enable_irq();
+            break;
+        case CPM_MODE_A_DIRECT_B_PWM:
+        case CPM_MODE_STEP_AND_DIR:
+            // Stop any active S&D command
+            MoveStopAbrupt();
+            // Block the interrupt and make sure that the PWM/step value is
+            // cleared
+            __disable_irq();
+            m_bDutyCnt = 0;
+            UpdateBDuty();
+            // Enable peripheral on port/pin B to use PWM on B only
+            PMUX_DISABLE(m_aInfo->gpioPort, m_aInfo->gpioPin);
+            PMUX_ENABLE(m_bInfo->gpioPort, m_bInfo->gpioPin);
+            m_mode = newMode;
+            __enable_irq();
+            break;
+        case CPM_MODE_A_DIRECT_B_DIRECT:
+            // Stop any active S&D command
+            MoveStopAbrupt();
+            // Disable peripheral on both port/pin A and B
+            PMUX_DISABLE(m_aInfo->gpioPort, m_aInfo->gpioPin);
+            PMUX_DISABLE(m_bInfo->gpioPort, m_bInfo->gpioPin);
+            m_mode = CPM_MODE_A_DIRECT_B_DIRECT;
+            break;
+        default:
+            return false;
+    }
+
+    return true;
+}
+
+void MotorDriver::UpdateADuty() {
+    if (*m_aTccBuffer == m_aDutyCnt) {
+        return;
+    }
+    while (*m_aTccSyncReg & m_aTccSyncMask) {
+        continue;
+    }
+    *m_aTccBuffer = m_aDutyCnt;
+}
+
+void MotorDriver::UpdateBDuty() {
+    if (*m_bTccBuffer == m_bDutyCnt) {
+        return;
+    }
+    while (*m_bTccSyncReg & m_bTccSyncMask) {
+        continue;
+    }
+    *m_bTccBuffer = m_bDutyCnt;
+}
+
+void MotorDriver::RefreshSlow() {
+    if (!m_initialized) {
+        return;
+    }
+
+    uint32_t currentTimeMs = TimingMgr.Milliseconds();
+    if (m_enableTriggerActive &&
+            (currentTimeMs - m_enableTriggerPulseStartMs >=
+             m_enableTriggerPulseLenMs)) {
+        m_enableTriggerPulseStartMs = currentTimeMs;
+        if (!--m_enableTriggerPulseCount) {
+            m_enableTriggerActive = false;
+        }
+        else {
+            ToggleEnable();
+        }
+    }
+
+    switch (m_clearFaultState) {
+        case CLEAR_FAULT_PULSE_ENABLE:
+            if (m_enableTriggerActive) {
+                break;
+            }
+            m_clearFaultState = CLEAR_FAULT_WAIT_FOR_HLFB;
+            // Fall through
+        case CLEAR_FAULT_WAIT_FOR_HLFB:
+            if (m_hlfbState != HLFB_DEASSERTED) {
+                AlertRegMotor mask;
+                mask.bit.MotorFaulted = 1;
+                ClearAlerts(mask.reg);
+                m_clearFaultState = CLEAR_FAULT_IDLE;
+            }
+            else if (!(m_clearFaultHlfbTimer && m_clearFaultHlfbTimer--)) {
+                m_clearFaultState = CLEAR_FAULT_IDLE;
+            }
+            break;
+        case CLEAR_FAULT_IDLE:
+        default:
+            break;
+    }
+}
+
+void MotorDriver::FaultState(bool isFaulted) {
+    m_inFault = isFaulted;
+    // Let EnableRequest handle the fault condition logic
+    EnableRequest(m_enableRequestedState);
+}
+
+bool MotorDriver::SetConnector(ClearCorePins pin, ClearCorePins &memberPin,
+                               bool input) {
+    if (pin == memberPin) {
+        // Nothing to do; already assigned.
+        return true;
+    }
+
+    // Validate the pin type. If it checks out, write the pin value into the
+    // memberPin member variable. Allow setting an "invalid" pin value to
+    // disable the associated feature.
+    if ((pin == CLEARCORE_PIN_INVALID) || 
+        (input && IsValidInputPin(pin)) ||
+        (!input && IsValidOutputPin(pin))) {
+        memberPin = pin;
+        return true;
+    }
+
+    return false; // Pin supplied was invalid.
+}
+
+bool MotorDriver::IsValidOutputPin(ClearCorePins pin) {
+    // Pins IO-0 through IO-5 and all CCIO-8 connectors are the only
+    // valid digital output pins available.
+    return (pin >= CLEARCORE_PIN_IO0 && pin <= CLEARCORE_PIN_IO5) ||
+           (pin >= CLEARCORE_PIN_CCIOA0 && pin <= CLEARCORE_PIN_CCIOH7);
+}
+
+bool MotorDriver::IsValidInputPin(ClearCorePins pin) {
+    // Pins IO-0 through A-12 and all CCIO-8 connectors are the only
+    // valid digital input pins available.
+    return (pin >= CLEARCORE_PIN_IO0 && pin <= CLEARCORE_PIN_A12) ||
+           (pin >= CLEARCORE_PIN_CCIOA0 && pin <= CLEARCORE_PIN_CCIOH7);
+}
+
+bool MotorDriver::CheckEStopSensor() {
+    bool eStop = false;
+    if (m_eStopConnector != CLEARCORE_PIN_INVALID) {
+        Connector *input = SysMgr.ConnectorByIndex(m_eStopConnector);
+        if (input->Type() == ClearCore::Connector::CCIO_DIGITAL_IN_OUT_TYPE) {
+            eStop = !(input->State());
+        }
+        else {
+            DigitalIn *inputB = static_cast<DigitalIn *>(input);
+            eStop = !(inputB->DigitalIn::State());
+        }
+    }
+    return eStop;
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/MotorManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/MotorManager.cpp
new file mode 100644
index 000000000..06c6fc311
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/MotorManager.cpp
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Implementation of ClearCore step mode connector
+**/
+
+#include "MotorManager.h"
+#include <sam.h>
+#include "AdcManager.h"
+#include "MotorDriver.h"
+#include "ShiftRegister.h"
+#include "SysConnectors.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+#define MAIN_INTERRUPT_GCLK_ID    1
+
+extern MotorDriver *const MotorConnectors[MOTOR_CON_CNT];
+extern ShiftRegister ShiftReg;
+
+MotorManager &MotorMgr = MotorManager::Instance();
+
+MotorManager &MotorManager::Instance() {
+    static MotorManager *instance = new MotorManager();
+    return *instance;
+}
+
+/**
+    Construct and wire in our output pins
+**/
+MotorManager::MotorManager()
+    : m_gclkIndex(MAIN_INTERRUPT_GCLK_ID),
+      m_clockRate(CLOCK_RATE_NORMAL),
+      m_initialized(false) {
+    m_stepPorts[MOTOR_M0M1] =  Mtr_CLK_01.gpioPort;
+    m_stepPorts[MOTOR_M2M3] = Mtr_CLK_23.gpioPort;
+    m_stepDataBits[MOTOR_M0M1] = Mtr_CLK_01.gpioPin;
+    m_stepDataBits[MOTOR_M2M3] = Mtr_CLK_23.gpioPin;
+    m_motorModes[MOTOR_M0M1] = Connector::CPM_MODE_A_DIRECT_B_DIRECT;
+    m_motorModes[MOTOR_M2M3] = Connector::CPM_MODE_A_DIRECT_B_DIRECT;
+}
+
+/**
+    Set the motor pulse rate.
+
+    Returns true if successfully set.
+**/
+bool MotorManager::MotorInputClocking(MotorClockRates newRate) {
+    if (m_clockRate == newRate && m_initialized) {
+        // Same rate as before, nothing to change
+        return false;
+    }
+
+    uint32_t clkReq;
+    bool modeValid = true;
+
+    switch (newRate) {
+        case CLOCK_RATE_LOW:
+            clkReq = CPM_CLOCK_RATE_LOW_HZ;
+            break;
+        case CLOCK_RATE_NORMAL:
+            clkReq = CPM_CLOCK_RATE_NORMAL_HZ;
+            break;
+        case CLOCK_RATE_HIGH:
+            clkReq = CPM_CLOCK_RATE_HIGH_HZ;
+            break;
+        default:
+            modeValid = false;
+            break;
+    }
+
+    if (!modeValid) {
+        return false;
+    }
+
+    // Mode change successful; update the step rate.
+    m_clockRate = newRate;
+
+    // Configure TCC0 for the step step carrier signal
+    TCC0->CTRLA.bit.ENABLE = 0; // Disable TCC0
+    TCC1->CTRLA.bit.ENABLE = 0; // Disable TCC1
+
+    SYNCBUSY_WAIT(TCC0, TCC_SYNCBUSY_ENABLE);
+    SYNCBUSY_WAIT(TCC1, TCC_SYNCBUSY_ENABLE);
+
+    GClkFreqUpdate(m_gclkIndex, clkReq);
+    int32_t newPeriod = clkReq / _CLEARCORE_SAMPLE_RATE_HZ;
+
+    TCC0->COUNT.reg = 0;
+    TCC1->COUNT.reg = 0;
+
+    // Clear out any pending command
+    for (int8_t iChannel = 0; iChannel < TCC0_CC_NUM; iChannel++) {
+        TCC0->CC[iChannel].reg = 0;
+        TCC0->CCBUF[iChannel].reg = 0;
+    }
+
+    for (int8_t iChannel = 0; iChannel < TCC1_CC_NUM; iChannel++) {
+        TCC1->CC[iChannel].reg = 0;
+        TCC1->CCBUF[iChannel].reg = 0;
+    }
+
+    TCC0->PER.reg = newPeriod - 1;
+    TCC1->PER.reg = newPeriod - 1;
+
+    // Notify the StepGenerators of the new maximum rate
+    for (uint8_t iMotor = 0; iMotor < MOTOR_CON_CNT; iMotor++) {
+        MotorConnectors[iMotor]->StepsPerSampleMaxSet(newPeriod);
+    }
+
+    TCC0->CTRLA.bit.ENABLE = 1; // Enable TCC0
+    TCC1->CTRLA.bit.ENABLE = 1; // Enable TCC1
+
+    SYNCBUSY_WAIT(TCC0, TCC_SYNCBUSY_ENABLE);
+    SYNCBUSY_WAIT(TCC1, TCC_SYNCBUSY_ENABLE);
+
+    return true;
+}
+
+bool MotorManager::MotorModeSet(MotorPair motorPair,
+                                Connector::ConnectorModes newMode) {
+    if (motorPair == MOTOR_ALL) {
+        return MotorModeSet(MOTOR_M0M1, newMode) &&
+               MotorModeSet(MOTOR_M2M3, newMode);
+    }
+
+    switch (newMode) {
+        case Connector::CPM_MODE_A_DIRECT_B_DIRECT:
+        case Connector::CPM_MODE_STEP_AND_DIR:
+        case Connector::CPM_MODE_A_DIRECT_B_PWM:
+        case Connector::CPM_MODE_A_PWM_B_PWM:
+            m_motorModes[motorPair] = newMode;
+            MotorConnectors[motorPair * 2]->Mode(newMode);
+            MotorConnectors[motorPair * 2 + 1]->Mode(newMode);
+
+            if (newMode == Connector::CPM_MODE_STEP_AND_DIR) {
+                PMUX_ENABLE(m_stepPorts[motorPair],
+                            m_stepDataBits[motorPair]);
+            }
+            else {
+                PMUX_DISABLE(m_stepPorts[motorPair],
+                             m_stepDataBits[motorPair]);
+            }
+            break;
+        default:
+            break;
+    }
+    return (m_motorModes[motorPair] == newMode);
+}
+
+void MotorManager::Initialize() {
+    m_motorModes[MOTOR_M0M1] = Connector::CPM_MODE_A_DIRECT_B_DIRECT;
+    m_motorModes[MOTOR_M2M3] = Connector::CPM_MODE_A_DIRECT_B_DIRECT;
+    MotorInputClocking(CLOCK_RATE_NORMAL); // This will set m_clockRate
+
+    for (uint8_t i = 0; i < NUM_MOTOR_PAIRS; i++) {
+        // Configure the GClk output pin that will be used as the CPM step
+        // output carrier signal
+        PIN_CONFIGURATION(m_stepPorts[i], m_stepDataBits[i],  0);
+        DATA_OUTPUT_STATE(m_stepPorts[i], 1UL << m_stepDataBits[i], false);
+        PMUX_SELECTION(m_stepPorts[i], m_stepDataBits[i], PER_GCLK_AC);
+        DATA_DIRECTION_OUTPUT(m_stepPorts[i], 1UL << m_stepDataBits[i]);
+    }
+
+    PinMuxSet();
+
+    m_initialized = true;
+}
+
+/**
+    Helper function to control if the step rate signal is active
+**/
+void MotorManager::PinMuxSet() {
+    // Configure the motor connectors to be in the specified mode
+    for (uint8_t iMotor = 0; iMotor < MOTOR_CON_CNT; iMotor++) {
+        MotorConnectors[iMotor]->Mode(m_motorModes[iMotor / 2]);
+    }
+
+    // Turn on the carrier signals for S&D if needed
+    for (uint8_t iMotorPair = 0; iMotorPair < NUM_MOTOR_PAIRS; iMotorPair++) {
+        if (m_motorModes[iMotorPair] == Connector::CPM_MODE_STEP_AND_DIR) {
+            PMUX_ENABLE(m_stepPorts[iMotorPair], m_stepDataBits[iMotorPair]);
+        }
+        else {
+            PMUX_DISABLE(m_stepPorts[iMotorPair], m_stepDataBits[iMotorPair]);
+        }
+    }
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/NvmManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/NvmManager.cpp
new file mode 100644
index 000000000..6aea651b4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/NvmManager.cpp
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    NVM Peripheral Manager for the ClearCore Board
+
+    This class manages the the non-volatile EEPROM peripheral on the
+    Teknic ClearCore.
+**/
+
+#include "NvmManager.h"
+#include "AdcManager.h"
+#include "StatusManager.h"
+#include "atomic_utils.h"
+#include <cstring>
+#include <sam.h>
+
+#define NVM_BLOCK_WRITE_V (20)
+#define UNDER_VOLTAGE_TRIP_CNT ((uint16_t)(NVM_BLOCK_WRITE_V * (1 << 15) / \
+    AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_VSUPPLY_MON]))
+
+namespace ClearCore {
+
+
+// Execute a command.
+// Wait until the NVM controller is ready to accept a new command.
+// The given cmd must be OR'd with NVMCTRL_CTRLB_CMDEX_KEY into the CTRLB
+// register for the cmd to be executed.
+#define EXEC_CMD(cmd)                                                          \
+    while (NVMCTRL->STATUS.bit.READY == 0);                                    \
+    NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | (cmd);
+
+// According to Section 9.4 NVM User Page Mapping in the datasheet, the first
+// 32 bytes of the User Page contain calibration data that are automatically
+// read at device power-on. Those bytes will get read to and written from the
+// page cache, but we won't allow anyone to access them; anytime someone
+// accesses the NVM, we'll adjust the given address to account for these
+// reserved bytes.
+#define NVM_LOCATION_TO_INDEX(loc) ((loc) + 32)
+#define DEFAULT_MAC_ADDRESS 0x241510b00000
+
+NvmManager &NvmMgr = NvmManager::Instance();
+uint32_t NvmMgrUnlock;
+
+NvmManager &NvmManager::Instance() {
+    static NvmManager *instance = new NvmManager();
+    return *instance;
+}
+
+NvmManager::NvmManager()
+    : m_nvmPageCache32(reinterpret_cast<int32_t *>(m_nvmPageCache)),
+      m_writeState(IDLE),
+      m_quadWordIndex(0),
+      m_pageModified(false) {
+
+    PopulateCache();
+}
+
+/**
+    Read octet from NVM.
+**/
+int8_t NvmManager::Byte(NvmLocations nvmLocation) {
+
+    // Check bounds - upper
+    if (nvmLocation >= NvmLocations::NVM_LOC_USER_MAX) {
+        return -1;
+    }
+
+    int8_t returnValue = m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocation)];
+    return returnValue;
+}
+/**
+    Write octet to NVM.
+**/
+bool NvmManager::Byte(NvmLocations nvmLocation, int8_t newValue) {
+
+    // Check bounds - upper
+    if (nvmLocation >= NvmLocations::NVM_LOC_USER_MAX) {
+        return false;
+    }
+
+    // Check bounds - if trying to write to Teknic reserved space, make
+    // sure the unlock code is set first
+    if (nvmLocation >= NvmLocations::NVM_LOC_RESERVED_TEKNIC) {
+        // If trying to write into the Teknic reserved space, return if the
+        // unlock code is not set
+        if (NvmMgrUnlock != 0x3fadeb) {
+            return false;
+        }
+    }
+
+    // Check if an update is actually needed.
+    if (Byte(nvmLocation) == newValue) {
+        return true;
+    }
+
+    // Put the new desired value into the page cache.
+    m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocation)] = newValue;
+
+    return WriteCacheToNvm();
+}
+
+/**
+    Read 16-bit integer from NVM.
+**/
+int16_t NvmManager::Int16(NvmLocations nvmLocation) {
+
+    // Check bounds - upper
+    if (nvmLocation >=
+            (NvmLocations::NVM_LOC_USER_MAX - sizeof(uint16_t) + 1)) {
+        return -1;
+    }
+
+    int16_t returnValue;
+    // Get a pointer to the value to be read
+    int8_t *byteAddress =
+        &(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocation)]);
+    // Access it as a 16-bit array
+    int16_t *address = reinterpret_cast<int16_t *>(byteAddress);
+    returnValue = address[0];
+
+    return returnValue;
+}
+/**
+    Write 16-bit integer to NVM.
+**/
+bool NvmManager::Int16(NvmLocations nvmLocation, int16_t newValue) {
+
+    // Check bounds - upper
+    if (nvmLocation >=
+            (NvmLocations::NVM_LOC_USER_MAX - sizeof(uint16_t) + 1)) {
+        return false;
+    }
+
+    // Check bounds - if trying to write to Teknic reserved space, make
+    // sure the unlock code is set first
+    if (nvmLocation >=
+            (NvmLocations::NVM_LOC_RESERVED_TEKNIC - sizeof(uint16_t) + 1)) {
+        // If trying to write into the Teknic reserved space, return if the
+        // unlock code is not set
+        if (NvmMgrUnlock != 0x3fadeb) {
+            return false;
+        }
+    }
+
+    // Check if an update is actually needed.
+    if (Int16(nvmLocation) == newValue) {
+        return true;
+    }
+
+    // Get a pointer to the value to be written
+    int8_t *byteAddress =
+        &(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocation)]);
+    // Access it as a 16-bit array
+    int16_t *address = reinterpret_cast<int16_t *>(byteAddress);
+
+    // Put the new desired value into the page cache.
+    address[0] = newValue;
+
+    return WriteCacheToNvm();
+}
+
+/**
+    Read 32-bit integer from NVM.
+**/
+int32_t NvmManager::Int32(NvmLocations nvmLocation) {
+
+    // Check bounds - upper
+    if (nvmLocation >=
+            (NvmLocations::NVM_LOC_USER_MAX - sizeof(uint32_t) + 1)) {
+        return -1;
+    }
+
+    int32_t returnValue;
+    // Get a pointer to the value to be read
+    int8_t *byteAddress =
+        &(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocation)]);
+    // Access it as a 32-bit array
+    int32_t *address = reinterpret_cast<int32_t *>(byteAddress);
+    returnValue = address[0];
+
+    return returnValue;
+}
+
+/**
+    Write 32-bit integer to NVM.
+**/
+bool NvmManager::Int32(NvmLocations nvmLocation, int32_t newValue) {
+
+    // Check bounds - upper
+    if (nvmLocation >=
+            (NvmLocations::NVM_LOC_USER_MAX - sizeof(uint32_t) + 1)) {
+        return false;
+    }
+
+    // Check bounds - if trying to write to Teknic reserved space, make
+    // sure the unlock code is set first
+    if (nvmLocation >=
+            (NvmLocations::NVM_LOC_RESERVED_TEKNIC - sizeof(uint32_t) + 1)) {
+        // If trying to write into the Teknic reserved space, return if the
+        // unlock code is not set
+        if (NvmMgrUnlock != 0x3fadeb) {
+            return false;
+        }
+    }
+
+    // Check if an update is actually needed.
+    if (Int32(nvmLocation) == newValue) {
+        return true;
+    }
+
+    // Get a pointer to the value to be written
+    int8_t *byteAddress =
+        &(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocation)]);
+    // Access it as a 32-bit array
+    int32_t *address = reinterpret_cast<int32_t *>(byteAddress);
+
+    // Put the new desired value into the page cache.
+    address[0] = newValue;
+
+    return WriteCacheToNvm();
+}
+
+/**
+    Read 64-bit integer from NVM.
+**/
+int64_t NvmManager::Int64(NvmLocations nvmLocationStart) {
+
+    // Check bounds - upper
+    if (nvmLocationStart >=
+            (NvmLocations::NVM_LOC_USER_MAX - sizeof(uint64_t) + 1)) {
+        return -1;
+    }
+
+    // 64-bit reads don't work if they aren't aligned; read it as 2 32-bit
+    // values instead
+    uint32_t val1 = Int32(nvmLocationStart);
+    uint32_t val2 =
+        Int32(static_cast<NvmLocations>(nvmLocationStart + sizeof(int32_t)));
+    uint64_t returnValue = val1;
+    returnValue = (returnValue << 32) | val2;
+    return returnValue;
+}
+
+/**
+    Write 64-bit integer to NVM.
+**/
+bool NvmManager::Int64(NvmLocations nvmLocationStart, int64_t newValue) {
+
+    // Check bounds - upper
+    if (nvmLocationStart >=
+            (NvmLocations::NVM_LOC_USER_MAX - sizeof(uint64_t) + 1)) {
+        return false;
+    }
+
+    // Check bounds - if trying to write to Teknic reserved space, make
+    // sure the unlock code is set first
+    if (nvmLocationStart >=
+            (NvmLocations::NVM_LOC_RESERVED_TEKNIC - sizeof(uint64_t) + 1)) {
+        // If trying to write into the Teknic reserved space, return if the
+        // unlock code is not set
+        if (NvmMgrUnlock != 0x3fadeb) {
+            return false;
+        }
+    }
+
+    // Check if an update is actually needed.
+    if (Int64(nvmLocationStart) == newValue) {
+        return true;
+    }
+
+    int32_t upper = newValue >> 32;
+    int32_t lower = newValue;
+
+    // Get a pointer to the value to be written
+    int8_t *byteAddress =
+        &(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocationStart)]);
+    // Access it as a 32-bit array
+    int32_t *address = reinterpret_cast<int32_t *>(byteAddress);
+
+    // Put the new desired value into the page cache.
+    address[0] = upper;
+    address[1] = lower;
+
+    return WriteCacheToNvm();
+}
+
+/**
+    BlockRead from NVM.
+**/
+void NvmManager::BlockRead(NvmLocations nvmLocationStart, int lengthInBytes, uint8_t * const p_data)
+{
+    // Check bounds - upper
+    if (nvmLocationStart >=
+    (NvmLocations::NVM_LOC_USER_MAX - lengthInBytes + 1)) {
+        return;
+    }
+
+    memcpy(p_data, &(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocationStart)]), lengthInBytes);
+}
+
+/**
+    BlockWrite to NVM.
+**/
+bool NvmManager::BlockWrite(NvmLocations nvmLocationStart, int lengthInBytes, uint8_t const * const p_data)
+{
+    // Check bounds - upper
+    if (nvmLocationStart >=
+    (NvmLocations::NVM_LOC_USER_MAX - lengthInBytes + 1)) {
+        return false;
+    }
+
+    // Check bounds - if trying to write to Teknic reserved space, make
+    // sure the unlock code is set first
+    if (nvmLocationStart >=
+    (NvmLocations::NVM_LOC_RESERVED_TEKNIC - lengthInBytes + 1)) {
+        // If trying to write into the Teknic reserved space, return if the
+        // unlock code is not set
+        if (NvmMgrUnlock != 0x3fadeb) {
+            return false;
+        }
+    }
+
+    if(memcmp(&(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocationStart)]), p_data, lengthInBytes) == 0)
+        return false;
+
+    memcpy(&(m_nvmPageCache[NVM_LOCATION_TO_INDEX(nvmLocationStart)]), p_data, lengthInBytes);
+
+    return WriteCacheToNvm();
+}
+
+/**
+    Queue the page cache to be written to NVM.
+**/
+bool NvmManager::WriteCacheToNvm() {
+    m_pageModified = true;
+    return FinishNvmWrite();
+}
+
+/**
+    State machine to write the page cache to NVM.
+**/
+extern uint16_t AdcResultsRaw[AdcManager::ADC_CHANNEL_COUNT];
+bool NvmManager::WriteCacheToNvmProc() {
+    static int32_t *addressInNvmToWrite = reinterpret_cast<int32_t *>(NVMCTRL_USER);
+
+    // Reading from the NVM immediately after writing to it sometimes returns
+    // outdated data so we use a cache in RAM to store a copy of the data
+    // that's currently written into non-volatile memory. To be safe, we only
+    // read from the NVM once at start-up to initialize the cache and defer all
+    // writes to the NVM until the cache is initialized.
+    switch (m_writeState) {
+    case IDLE:
+        if (!m_pageModified) {
+            break;
+        }
+        // The page cache was modified, start the write process
+        m_writeState = CLEAR_PAGE_BUFFER;
+        // Fall through
+
+    // Check if the page buffer is dirty, clean if necessary
+    case CLEAR_PAGE_BUFFER:
+        if (NVMCTRL->STATUS.bit.LOAD) {
+            // Is the NVM ready for a command
+            if (!NVMCTRL->STATUS.bit.READY) {
+                break;
+            }
+            NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_PBC;
+        }
+
+        // Clear the DONE Flag
+        NVMCTRL->INTFLAG.bit.DONE = 1;
+        m_writeState = ERASE_PAGE;
+        // Fall through
+
+    // Erase the user page; note that NVM must be erased prior to writing to
+    // it (datasheet pg. 648, "Procedure for Manual Page Writes" section), and
+    // the User Page only support Page Erase (not Block Erase)
+    // Note: This will kill device critical information if not properly
+    // restored (the device-critical information is stored in the first 32
+    // bytes of the page cache, so it will be written back with the rest of the
+    // cache)
+    case ERASE_PAGE:
+        // Is the NVM ready for a command
+        if (!NVMCTRL->STATUS.bit.READY) {
+            break;
+        }
+
+        // Do as much as possible before checking voltage & subsequently erasing 
+        // the page
+        // Set write mode to manual. It may be faster to use automatic
+        NVMCTRL->CTRLA.bit.WMODE = NVMCTRL_CTRLA_WMODE_MAN;
+        // Set the addr to the page that we want to address
+        NVMCTRL->ADDR.reg = static_cast<uint32_t>(NVMCTRL_USER);
+        // Reset our index
+        m_quadWordIndex = 0;
+
+        // Check the voltage and if good, erase page
+        if (BlockWrite()) {
+            m_writeState = IDLE;
+            return false;
+        }
+        // It is now a race against capacitive drain to write as fast as possible
+        // in order to not loose data
+        NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_EP;
+        m_writeState = WRITE_DATA;
+        // Fall through
+
+    // Copy the contents of the page cache into the page buffer in 128-bit
+    // chunks, then write each chunk into NVM
+#define CHUNK_SIZE 16 //bytes per chunk (128 bits per chunk)
+#define num32sInPb      (NVMCTRL_PAGE_SIZE / sizeof(uint32_t))
+#define num32sIn128     (CHUNK_SIZE / sizeof(uint32_t))
+    case WRITE_DATA:
+        
+        // While data cannot be written while the page erase is happening, 
+        // the write can be prepared
+
+        // Tell the NVM the location of the 128-bit value to be written
+        NVMCTRL->ADDR.reg =
+            reinterpret_cast<uint32_t>(&addressInNvmToWrite[m_quadWordIndex]);
+        // Copy each of 4 the 32-bit values into the page buffer
+        memcpy( &addressInNvmToWrite[m_quadWordIndex], &m_nvmPageCache32[m_quadWordIndex], CHUNK_SIZE);
+        m_quadWordIndex+=num32sIn128;
+
+        // The Page Buffer cannot be written while a write command 
+        // is executing in the NVM. Wait for the status ready flag.
+        if (!NVMCTRL->STATUS.bit.READY) {
+            break;
+        }
+
+        // Tell the NVM controller to write the 128-bit value
+        NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_WQW;
+        if (m_quadWordIndex >= num32sInPb) {
+            m_writeState = IDLE;
+            m_pageModified = false;
+        }
+        break;
+
+    default:
+        m_writeState = IDLE;
+        break;
+    }
+    return true;
+}
+
+/**
+    Populate the page cache from NVM.
+**/
+void NvmManager::PopulateCache() {
+    // BK 9/9/20: Not sure why this was done, but it may slow down performance 
+    // if the cache is disabled. 
+    //NVMCTRL->CTRLA.bit.CACHEDIS0 = 1;
+    //NVMCTRL->CTRLA.bit.CACHEDIS1 = 1;
+    // Copy the contents of memory into a buffer
+    memcpy(m_nvmPageCache, reinterpret_cast<const void *>(NVMCTRL_USER),
+           NVMCTRL_PAGE_SIZE);
+}
+
+void NvmManager::MacAddress(uint8_t *macAddress) {
+    uint64_t macNvm = Int64(NVM_LOC_MAC_FIRST);
+    // If an invalid MAC address is detected, revert to 
+    // the default MAC address to be able to come online.
+    if (macNvm == UINT64_MAX || (macNvm >> 48)) {
+        macNvm = DEFAULT_MAC_ADDRESS;
+    }
+    for (int8_t shift = 5; shift >= 0; shift--) {
+        macAddress[5 - shift] = (macNvm >> shift * 8) & 0xFF;
+    }
+}
+
+uint32_t NvmManager::SerialNumber() {
+    return static_cast<uint32_t>(Int32(NVM_LOC_SERIAL_NUMBER));
+}
+
+bool NvmManager::BlockWrite() {
+    //return StatusManager::Instance().StatusRT().bit.VSupplyUnderVoltage;
+    return AdcManager::Instance().ConvertedResult(AdcManager::ADC_VSUPPLY_MON) 
+           < UNDER_VOLTAGE_TRIP_CNT;
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SdCardDriver.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SdCardDriver.cpp
new file mode 100644
index 000000000..e9478c22f
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SdCardDriver.cpp
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    SD card interface implementation
+
+    This class manages the optional micro SD card reader attached to the Teknic
+    ClearCore.
+**/
+
+#include "SdCardDriver.h"
+#include <sam.h>
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+/**
+    Construct and wire into the board.
+**/
+SdCardDriver::SdCardDriver(const PeripheralRoute *misoInfo,
+                           const PeripheralRoute *ssInfo,
+                           const PeripheralRoute *sckInfo,
+                           const PeripheralRoute *mosiInfo,
+                           uint8_t peripheral)
+    : SerialBase(misoInfo, ssInfo, sckInfo, mosiInfo, peripheral),
+      m_errorCode(0) {
+    PortMode(SerialBase::SPI);
+    SpiClock(SCK_LOW, LEAD_SAMPLE);
+    PortOpen();
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialBase.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialBase.cpp
new file mode 100644
index 000000000..67644b991
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialBase.cpp
@@ -0,0 +1,1108 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Serial implementation
+
+    ClearCore Serial Connector Base Class.
+**/
+
+#include "SerialBase.h"
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <sam.h>
+#include "atomic_utils.h"
+#include "InputManager.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+#define __SERCOM_USART_CLOCK_INDEX 0
+#define __SERCOM_SPI_CLOCK_INDEX 7
+#define __SERCOM_USART_CLOCK (SystemCoreClock)
+#define __SERCOM_SPI_CLOCK (10000000) // __CLEARCORE_GCLK7_HZ
+
+// Dummy location to read/write SPI data that is unused
+static uint32_t spiDummy;
+
+extern volatile uint32_t tickCnt;
+extern InputManager &InputMgr;
+
+/**
+    Construct this instance and remember all the pads and bit locations.
+**/
+SerialBase::SerialBase(const PeripheralRoute *ctsMisoInfo,
+                       const PeripheralRoute *rtsSsInfo,
+                       const PeripheralRoute *rxSckInfo,
+                       const PeripheralRoute *txMosiInfo,
+                       uint8_t peripheral)
+    : m_parity(PARITY_N),
+      m_stopBits(1),
+      m_charSize(8),
+      m_portMode(PortModes::UART),
+      m_polarity(SCK_LOW),
+      m_phase(LEAD_CHANGE),
+      m_ssMode(LINE_OFF),
+      m_rtsMode(LINE_HW),
+      m_flowControl(false),
+      m_ctsMisoInfo(ctsMisoInfo),
+      m_rtsSsInfo(rtsSsInfo),
+      m_rxSckInfo(rxSckInfo),
+      m_txMosiInfo(txMosiInfo),
+      m_baudRate(9600),
+      m_peripheral(peripheral),
+      m_portOpen(false),
+      m_serialBreak(false),
+      m_dreIrqN(static_cast<IRQn_Type>(INT32_MAX)),
+      m_dmaRxChannel(DMA_INVALID_CHANNEL),
+      m_dmaTxChannel(DMA_INVALID_CHANNEL),
+      m_bufferIn{0}, m_bufferOut{0},
+      m_inHead(0), m_inTail(0),
+      m_outHead(0), m_outTail(0) {
+    static Sercom *const sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+    m_serPort = sercom_instances[ctsMisoInfo->sercomNum];
+}
+
+/**
+    Enable/Disable the port.
+
+    ENABLE is the same for all modes of the port SPI/USART/I2C
+**/
+void SerialBase::PortEnable(bool initializing) {
+    // Enable port and wait for the sync.
+    m_serPort->USART.CTRLA.bit.ENABLE = 1;
+    SercomUsart *usart = &m_serPort->USART;
+    SYNCBUSY_WAIT(usart, SERCOM_USART_SYNCBUSY_ENABLE);
+
+    if (!initializing) {
+        PMUX_ENABLE(m_txMosiInfo->gpioPort, m_txMosiInfo->gpioPin);
+    }
+}
+
+void SerialBase::PortDisable() {
+    // Disable port and wait for the sync.
+    PMUX_DISABLE(m_txMosiInfo->gpioPort, m_txMosiInfo->gpioPin);
+    if (m_serPort->USART.CTRLA.bit.ENABLE) {
+        m_serPort->USART.CTRLA.bit.ENABLE = 0;
+    }
+
+    SercomUsart *usart = &m_serPort->USART;
+    SYNCBUSY_WAIT(usart, SERCOM_USART_SYNCBUSY_ENABLE);
+
+    Flush();
+    FlushInput();
+}
+
+/**
+    Disable the port and close it.
+**/
+void SerialBase::PortClose() {
+    if (m_portOpen) {
+        // Flush the transmit buffer before closing
+        WaitForTransmitIdle();
+
+        DATA_DIRECTION_INPUT(m_rtsSsInfo->gpioPort, 1L << m_rtsSsInfo->gpioPin);
+        PortDisable();
+        m_portOpen = false;
+    }
+}
+
+void SerialBase::WaitOneCharTime() {
+    uint32_t tickVal = tickCnt;
+    uint32_t ticksNeeded =
+        max(2, (SampleRateHz * 10 + m_baudRate - 1) / m_baudRate);
+    while (tickCnt - tickVal < ticksNeeded) {
+        continue;
+    }
+}
+
+void SerialBase::FlowControl(bool useFlowControl) {
+    m_flowControl = useFlowControl;
+    if (m_portMode == UART && m_portOpen) {
+        // Defines the Transmit Data Pin Out
+        // 0x0 for TxD pin PAD 0, RTS pin N/A, CTS pin N/A
+        // 0x2 for TxD pin PAD 0, RTS pin PAD 2, CTS pin PAD 3
+        bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+        PortDisable();
+        m_serPort->USART.CTRLA.bit.TXPO = m_flowControl ? 2 : 0;
+        if (sercomEnabled) {
+            PortEnable();
+        }
+    }
+}
+
+bool SerialBase::RtsMode(CtrlLineModes mode) {
+    m_rtsMode = mode;
+    return RtsSsPinState(mode);
+}
+
+bool SerialBase::CtsState() {
+    return !(*InputMgr.m_inputPtrs[m_ctsMisoInfo->gpioPort] &
+             (1UL << m_ctsMisoInfo->gpioPin));
+}
+
+bool SerialBase::RtsSsPinState(CtrlLineModes mode) {
+    bool success = true;
+
+    switch (mode) {
+        case LINE_HW:
+            PMUX_ENABLE(m_rtsSsInfo->gpioPort, m_rtsSsInfo->gpioPin);
+            break;
+        case LINE_OFF:
+        // Fall through
+        case LINE_ON:
+            DATA_OUTPUT_STATE(m_rtsSsInfo->gpioPort,
+                              1L << m_rtsSsInfo->gpioPin,
+                              mode == LINE_OFF); // ON is low voltage due to
+            // inversions
+            PMUX_DISABLE(m_rtsSsInfo->gpioPort, m_rtsSsInfo->gpioPin);
+            break;
+        default:
+            // Should not happen
+            success = false;
+            break;
+    }
+
+    return success;
+}
+
+/**
+    Initiate a serial break
+**/
+void SerialBase::SerialBreak(bool enable) {
+    if (enable) {
+        // Disable pmux on tx out
+        PMUX_DISABLE(m_txMosiInfo->gpioPort, m_txMosiInfo->gpioPin);
+        DATA_OUTPUT_STATE(m_txMosiInfo->gpioPort,
+                          1L << m_txMosiInfo->gpioPin, false);   // break
+        WaitOneCharTime();
+    }
+    else {
+        // Enable pmux on tx out
+        PMUX_ENABLE(m_txMosiInfo->gpioPort, m_txMosiInfo->gpioPin);
+        DATA_OUTPUT_STATE(m_txMosiInfo->gpioPort,
+                          1L << m_txMosiInfo->gpioPin, true);    // idle
+    }
+    m_serialBreak = enable;
+    // Make sure the line state is held steady long enough so that
+    // the enter/exit of break is not interpreted as a character
+    WaitOneCharTime();
+}
+
+/**
+    Open the port and set up the mode
+**/
+void SerialBase::PortOpen() {
+    if (!m_portOpen) {
+        m_portOpen = true;
+        PortMode(m_portMode);
+    }
+}
+
+/**
+    Return if the port is open or not.
+**/
+bool SerialBase::PortIsOpen() {
+    return m_portOpen;
+}
+
+/**
+    Set the SERCOM up for the supported operational mode.
+
+    This includes port setup, pad setup and clocks.
+**/
+bool SerialBase::PortMode(PortModes newMode) {
+    if (newMode != SPI && newMode != UART) {
+        return false;
+    }
+    m_portMode = newMode;
+    // If port is not open just return
+    if (!m_portOpen) {
+        return true;
+    }
+
+    SercomUsart *usart = &m_serPort->USART;
+    // Reset port to power-on state and force port to "disable"
+    usart->CTRLA.bit.SWRST = 1;
+    SYNCBUSY_WAIT(usart, SERCOM_USART_SYNCBUSY_SWRST);
+
+    Flush();
+    FlushInput();
+
+    // Dummy init to intercept potential error later
+    IRQn_Type IdNvic = PendSV_IRQn;
+    uint8_t clockId;
+    uint8_t dmaRxTrigger = DMAC_CHCTRLA_TRIGSRC_DISABLE_Val;
+    uint8_t dmaTxTrigger = DMAC_CHCTRLA_TRIGSRC_DISABLE_Val;
+
+    // Map clock and interrupt
+    if (m_serPort == SERCOM0) {
+        m_dmaRxChannel = DMA_SERCOM0_SPI_RX;
+        m_dmaTxChannel = DMA_SERCOM0_SPI_TX;
+        dmaRxTrigger = SERCOM0_DMAC_ID_RX;
+        dmaTxTrigger = SERCOM0_DMAC_ID_TX;
+        clockId = SERCOM0_GCLK_ID_CORE;
+        IdNvic = SERCOM0_0_IRQn;
+    }
+    else if (m_serPort == SERCOM2) {
+        m_dmaRxChannel = DMA_INVALID_CHANNEL;
+        m_dmaTxChannel = DMA_INVALID_CHANNEL;
+        clockId = SERCOM2_GCLK_ID_CORE;
+        IdNvic = SERCOM2_0_IRQn;
+    }
+    else if (m_serPort == SERCOM3) {
+        m_dmaRxChannel = DMA_INVALID_CHANNEL;
+        m_dmaTxChannel = DMA_INVALID_CHANNEL;
+        clockId = SERCOM3_GCLK_ID_CORE;
+        IdNvic = SERCOM3_0_IRQn;
+    }
+    else if (m_serPort == SERCOM4) {
+        m_dmaRxChannel = DMA_INVALID_CHANNEL;
+        m_dmaTxChannel = DMA_INVALID_CHANNEL;
+        clockId = SERCOM4_GCLK_ID_CORE;
+        IdNvic = SERCOM4_0_IRQn;
+    }
+    else if (m_serPort == SERCOM5) {
+        m_dmaRxChannel = DMA_INVALID_CHANNEL;
+        m_dmaTxChannel = DMA_INVALID_CHANNEL;
+        clockId = SERCOM5_GCLK_ID_CORE;
+        IdNvic = SERCOM5_0_IRQn;
+    }
+    else if (m_serPort == SERCOM7) {
+        m_dmaRxChannel = DMA_SERCOM7_SPI_RX;
+        m_dmaTxChannel = DMA_SERCOM7_SPI_TX;
+        dmaRxTrigger = SERCOM7_DMAC_ID_RX;
+        dmaTxTrigger = SERCOM7_DMAC_ID_TX;
+        clockId = SERCOM7_GCLK_ID_CORE;
+        IdNvic = SERCOM7_0_IRQn;
+    }
+    else {
+        return false;
+    }
+
+    if (IdNvic == PendSV_IRQn) {
+        // If we've reached this point there's a problem.
+        return false;
+    }
+
+    // Setup TX Out to high to hold the idle state or low for SerialBreak.
+    DATA_OUTPUT_STATE(m_txMosiInfo->gpioPort,
+                      1L << m_txMosiInfo->gpioPin, true); // idle
+    DATA_DIRECTION_OUTPUT(m_txMosiInfo->gpioPort, 1L << m_txMosiInfo->gpioPin);
+
+    // Set up SERCOM registers based on the desired mode.
+    switch (m_portMode) {
+        case SPI:
+            /* Data Register Empty Interrupt */
+            NVIC_DisableIRQ((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_DRE_Pos));
+            /* Receive Complete Interrupt */
+            NVIC_DisableIRQ((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_RXC_Pos));
+            /* Receive Start Interrupt and errors */
+            NVIC_DisableIRQ((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_RXS_Pos));
+
+            // Setting Generic Clock Generator 0 as the default source
+            SET_CLOCK_SOURCE(clockId, __SERCOM_SPI_CLOCK_INDEX);
+            // SPI master mode
+            m_serPort->SPI.CTRLA.bit.MODE = 0x3;
+            // Clock polarity, leading edge is rising edge
+            m_serPort->SPI.CTRLA.bit.CPOL = m_polarity;
+            // Clock phase, determines SPI transfer mode
+            m_serPort->SPI.CTRLA.bit.CPHA = m_phase;
+            // Frame format supported by SPI in slave mode
+            m_serPort->SPI.CTRLA.bit.FORM = 0;
+            // In master operation, DIPO is MISO
+            m_serPort->SPI.CTRLA.bit.DIPO = m_ctsMisoInfo->sercomPadNum;
+            // In master operation, DOPO is MOSI
+            // Data out can be either Pad 0: DOPO = 0 or Pad 3: DOPO = 2
+            m_serPort->SPI.CTRLA.bit.DOPO = m_txMosiInfo->sercomPadNum ? 2 : 0;
+            // 8 bit char size
+            m_serPort->SPI.CTRLB.bit.CHSIZE = m_charSize &
+                                              SERCOM_SPI_CTRLB_CHSIZE_Msk;
+            // MSB is transferred first
+            m_serPort->SPI.CTRLA.bit.DORD = 0;
+            // Set buffer overflow immediately
+            m_serPort->SPI.CTRLA.bit.IBON = 1;
+            // Hardware controlled SS if m_ssMode = LINE_HW
+            m_serPort->SPI.CTRLB.bit.MSSEN = 1;
+            // Receiver enable
+            m_serPort->SPI.CTRLB.bit.RXEN = 1;
+
+            // Configure the Slave Select pin
+            PMUX_SELECTION(m_rtsSsInfo->gpioPort, m_rtsSsInfo->gpioPin,
+                           m_peripheral);
+            SpiSsMode(m_ssMode);
+
+            // Setup the DMA descriptors to perform asynchronous SPI transfers
+            if (m_dmaRxChannel != DMA_INVALID_CHANNEL &&
+                    m_dmaTxChannel != DMA_INVALID_CHANNEL) {
+                DmacChannel *channel;
+                DmacDescriptor *baseDesc;
+                // Rx channel setup
+                channel = DmaManager::Channel(m_dmaRxChannel);
+                // Disable and reset the channel so it is clean to setup
+                channel->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+                channel->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+                // Wait for the reset to finish
+                while (channel->CHCTRLA.reg == DMAC_CHCTRLA_SWRST) {
+                    continue;
+                }
+
+                channel->CHCTRLA.reg = DMAC_CHCTRLA_TRIGSRC(dmaRxTrigger) |
+                                       DMAC_CHCTRLA_TRIGACT_BURST |
+                                       DMAC_CHCTRLA_BURSTLEN_SINGLE;
+
+                // Set up the Rx source descriptor since that will not change
+                baseDesc = DmaManager::BaseDescriptor(m_dmaRxChannel);
+                baseDesc->DESCADDR.reg = static_cast<uint32_t>(0);
+                baseDesc->SRCADDR.reg = (uint32_t)&m_serPort->SPI.DATA.reg;
+
+                // Tx channel setup
+                channel = DmaManager::Channel(m_dmaTxChannel);
+                // Disable and reset the channel so it is clean to setup
+                channel->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+                channel->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+                // Wait for the reset to finish
+                while (channel->CHCTRLA.reg == DMAC_CHCTRLA_SWRST) {
+                    continue;
+                }
+
+                channel->CHCTRLA.reg = DMAC_CHCTRLA_TRIGSRC(dmaTxTrigger) |
+                                       DMAC_CHCTRLA_TRIGACT_BURST |
+                                       DMAC_CHCTRLA_BURSTLEN_SINGLE;
+
+                // Set up the Tx dest descriptor since that will not change
+                baseDesc = DmaManager::BaseDescriptor(m_dmaTxChannel);
+                baseDesc->DESCADDR.reg = static_cast<uint32_t>(0);
+                baseDesc->DSTADDR.reg = (uint32_t)&m_serPort->SPI.DATA.reg;
+            }
+            break;
+
+        case UART:
+        default:
+            // 0x1 selects USART with internal clock
+            usart->CTRLA.bit.MODE = 1;
+            // 0x0 for 16x oversampling using arithmetic baud rate generation
+            usart->CTRLA.bit.SAMPR = 0;
+            // 0x0 for asynchronous communication
+            usart->CTRLA.bit.CMODE = 0;
+
+            // Defines the Receive Data Pin Out
+            // 0x1 for SERCOM PAD 1
+            usart->CTRLA.bit.RXPO = 1;
+
+            FlowControl(m_flowControl);
+
+            // 0x0 for 8-bit character size
+            usart->CTRLB.bit.CHSIZE =
+                m_charSize & SERCOM_USART_CTRLB_CHSIZE_Msk;
+            // 0x1 for specifying LSB first data order
+            usart->CTRLA.bit.DORD = 1;
+
+            // Check what parity should be used (if any)
+            if (m_parity != PARITY_N) {
+                // 0x1 for USART frame format with parity
+                usart->CTRLA.bit.FORM = 1;
+                // Set the parity mode
+                usart->CTRLB.bit.PMODE = m_parity;
+            }
+            else {
+                // 0x0 for USART frame without parity
+                usart->CTRLA.bit.FORM = 0;
+            }
+
+            // 0x0 sets one stop bit
+            usart->CTRLB.bit.SBMODE = m_stopBits - 1;
+            // 0x1 enables the USART receiver
+            usart->CTRLB.bit.RXEN = 1;
+            // 0x1 enables the USART transmitter
+            usart->CTRLB.bit.TXEN = 1;
+            // 0x0 Disables start of frame detection
+            usart->CTRLB.bit.SFDE = 0;
+
+            // Enable Error (ERROR) and Receive complete (RXC) interrupts
+            usart->INTENSET.reg =
+                SERCOM_USART_INTENSET_RXC |  SERCOM_USART_INTENSET_ERROR;
+
+            // Sync CTRLB
+            SYNCBUSY_WAIT(usart, SERCOM_USART_SYNCBUSY_CTRLB);
+
+            // Setting NVIC
+
+            /* Data Register Empty Interrupt */
+            m_dreIrqN = (IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_DRE_Pos);
+            NVIC_EnableIRQ((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_DRE_Pos));
+            NVIC_SetPriority((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_DRE_Pos),
+                             SERCOM_NVIC_TX_PRIORITY);
+
+            /* Receive Complete Interrupt */
+            NVIC_EnableIRQ((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_RXC_Pos));
+            NVIC_SetPriority((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_RXC_Pos),
+                             SERCOM_NVIC_RX_PRIORITY);
+
+            /* Receive Start Interrupt, CTS, and errors */
+            NVIC_EnableIRQ((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_RXS_Pos));
+            NVIC_SetPriority((IRQn_Type)(IdNvic + SERCOM_USART_INTFLAG_RXS_Pos),
+                             SERCOM_NVIC_ERR_PRIORITY);
+
+            PMUX_SELECTION(m_rtsSsInfo->gpioPort, m_rtsSsInfo->gpioPin,
+                           m_peripheral);
+            RtsMode(m_rtsMode);
+
+            // Setting Generic Clock Generator 0 as the default source
+            SET_CLOCK_SOURCE(clockId, __SERCOM_USART_CLOCK_INDEX);
+            break;
+    }
+
+    // Calculating BAUD according to figure 33-2 in datasheet
+    Speed(m_baudRate);
+
+    // Enable the MUX on each of the pins
+    DATA_DIRECTION_OUTPUT(m_rtsSsInfo->gpioPort, 1L << m_rtsSsInfo->gpioPin);
+
+    PMUX_SELECTION(m_ctsMisoInfo->gpioPort, m_ctsMisoInfo->gpioPin,
+                   m_peripheral);
+    PIN_CONFIGURATION(m_ctsMisoInfo->gpioPort, m_ctsMisoInfo->gpioPin,
+                      PORT_PINCFG_PMUXEN | PORT_PINCFG_INEN);
+    DATA_DIRECTION_INPUT(m_ctsMisoInfo->gpioPort, 1L << m_ctsMisoInfo->gpioPin);
+
+    PMUX_SELECTION(m_rxSckInfo->gpioPort, m_rxSckInfo->gpioPin,
+                   m_peripheral);
+    PIN_CONFIGURATION(m_rxSckInfo->gpioPort, m_rxSckInfo->gpioPin,
+                      PORT_PINCFG_PMUXEN);
+
+    PMUX_SELECTION(m_txMosiInfo->gpioPort, m_txMosiInfo->gpioPin,
+                   m_peripheral);
+    PIN_CONFIGURATION(m_txMosiInfo->gpioPort, m_txMosiInfo->gpioPin,
+                      PORT_PINCFG_PMUXEN);
+
+    // Enable SERCOM and wait for the sync
+    PortEnable(true);
+
+    return true;
+}
+
+/**
+    Change the baud rate for the port.
+**/
+bool SerialBase::Speed(uint32_t bitsPerSecond) {
+    bool success = true;
+    m_baudRate = bitsPerSecond;
+    bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+    PortDisable();
+
+    uint32_t baudVal;
+
+    switch (m_portMode) {
+        case SPI:
+            // Calculate the maximum baud rate that is <= the target rate
+            baudVal = ((__SERCOM_SPI_CLOCK / 2 + (bitsPerSecond - 1)) /
+                       bitsPerSecond) - 1;
+            // Limit the value to UINT8_MAX, even if it gives a rate faster
+            // than our target
+            if (baudVal > UINT8_MAX) {
+                baudVal = UINT8_MAX;
+                // If baudVal is greater than 255, a lower input clock rate is
+                // needed to achieve the requested baud rate
+                // We'll clip to the highest rate possible and let the user
+                // know that their setting didn't take
+                success = false;
+            }
+            m_serPort->SPI.BAUD.bit.BAUD = static_cast<uint8_t>(baudVal);
+            break;
+
+        case UART:
+        default:
+            float baudFloat =
+                65536 * (1 - (16.0 * bitsPerSecond / __SERCOM_USART_CLOCK));
+            m_serPort->USART.BAUD.bit.BAUD = (uint16_t)(baudFloat + 0.5);
+            break;
+    }
+
+    if (sercomEnabled) {
+        PortEnable();
+    }
+    return success;
+}
+
+/**
+    Set UART transmission parity format.
+**/
+bool SerialBase::Parity(Parities newParity) {
+    m_parity = newParity;
+
+    switch (m_portMode) {
+        case SPI:
+            return false;
+        case UART:
+        default: {
+            bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+            PortDisable();
+            if (m_parity != PARITY_N) {
+                // 0x1 to set a USART frame with parity
+                m_serPort->USART.CTRLA.bit.FORM = 1;
+                // Set the parity
+                m_serPort->USART.CTRLB.bit.PMODE = m_parity;
+            }
+            else {
+                // 0x0 to set a USART frame without parity
+                m_serPort->USART.CTRLA.bit.FORM = 0;
+            }
+            if (sercomEnabled) {
+                PortEnable();
+            }
+            return true;
+        }
+    }
+}
+
+/**
+    Change the number of bits in a character.
+**/
+bool SerialBase::CharSize(uint8_t size) {
+    // Note: Supports 5,6,7,8,9 bits.
+    if (size < 5 || size > 9) {
+        return false;
+    }
+    else if (m_portMode == SPI && (size < 8 || size > 9)) {
+        // Note: SPI only supports 8 or 9 bit characters
+        return false;
+    }
+    m_charSize = size;
+    bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+    PortDisable();
+
+
+    switch (m_portMode) {
+        case SPI:
+            // Register size clips 8 and 9 to 0 and 1 to match register
+            // definition.
+            m_serPort->SPI.CTRLB.bit.CHSIZE = size &
+                                              SERCOM_SPI_CTRLB_CHSIZE_Msk;
+            break;
+        case UART:
+        default:
+            // Register size clips 8 and 9 to 0 and 1 to match register
+            // definition.
+            m_serPort->USART.CTRLB.bit.CHSIZE = size &
+                                                SERCOM_USART_CTRLB_CHSIZE_Msk;
+            break;
+    }
+    if (sercomEnabled) {
+        PortEnable();
+    }
+    return true;
+}
+
+/**
+    Change the number of stop bits used in UART communication.
+**/
+bool SerialBase::StopBits(uint8_t bits) {
+    if (bits < 1 || bits > 2) {
+        return false;
+    }
+    m_stopBits = bits;
+    // Don't apply the change yet if we are not in UART mode
+    if (m_portMode != PortModes::UART) {
+        return true;
+    }
+    bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+    PortDisable();
+    m_serPort->USART.CTRLB.bit.SBMODE = bits - 1;
+    if (sercomEnabled) {
+        PortEnable();
+    }
+    return true;
+}
+
+/**
+    Change the data order for the port.
+**/
+void SerialBase::DataOrder(DataOrders newOrder) {
+    bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+    PortDisable();
+    // SPI/USART use the same bit.
+    m_serPort->USART.CTRLA.bit.DORD = newOrder;
+    if (sercomEnabled) {
+        PortEnable();
+    }
+}
+
+/**
+    Flush transmit buffers.
+**/
+void SerialBase::Flush() {
+    // Flush buffers
+    m_bufferOut[0] = 0;
+    m_outTail = 0;
+    m_outHead = 0;
+}
+
+/**
+    Flush receive buffers.
+**/
+void SerialBase::FlushInput() {
+    // Flush buffers
+    m_bufferIn[0] = 0;
+    m_inTail = 0;
+    m_inHead = 0;
+    EnableRxcInterruptUart();
+}
+
+/**
+    Enable the Data Register Empty USART interrupt.
+**/
+void SerialBase::EnableDreInterruptUart() {
+    m_serPort->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+/**
+    Disable the Data Register Empty USART interrupt.
+**/
+void SerialBase::DisableDreInterruptUart() {
+    m_serPort->USART.INTENCLR.reg = SERCOM_USART_INTENCLR_DRE;
+}
+
+/**
+    Enable the Receive Complete USART interrupt.
+**/
+void SerialBase::EnableRxcInterruptUart() {
+    m_serPort->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+/**
+    Disable the Receive Complete USART interrupt.
+**/
+void SerialBase::DisableRxcInterruptUart() {
+    m_serPort->USART.INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
+}
+
+/**
+    Set/Clear the slave select mode.
+**/
+bool SerialBase::SpiSsMode(CtrlLineModes mode) {
+    m_ssMode = mode;
+    return RtsSsPinState(mode);
+}
+
+/**
+    Change the polarity and phase for the SPI clock.
+**/
+void SerialBase::SpiClock(
+    SpiClockPolarities polarity, SpiClockPhases phase) {
+    m_polarity = polarity;
+    m_phase = phase;
+
+    // If we are not currently in SPI mode, don't apply the change yet.
+    if (m_portMode != PortModes::SPI) {
+        return;
+    }
+    bool sercomEnabled = m_serPort->USART.CTRLA.bit.ENABLE;
+    PortDisable();
+    m_serPort->SPI.CTRLA.bit.CPOL = m_polarity;
+    m_serPort->SPI.CTRLA.bit.CPHA = m_phase;
+    if (sercomEnabled) {
+        PortEnable();
+    }
+}
+
+/**
+    Attempt to get next character from serial channel.
+**/
+int16_t SerialBase::CharGet() {
+    // Return if nothing is waiting.
+    if (m_inTail == m_inHead) {
+        return SerialBase::EOB;
+    }
+
+    // Get head of buffer, wrapped.
+    int32_t nextIndex = NextIndex(m_inHead);
+    // Get head character.
+    int16_t returnChar = m_bufferIn[m_inHead];
+    // Save new head ptr.
+    m_inHead = nextIndex;
+    EnableRxcInterruptUart();
+
+    return returnChar;
+}
+
+/**
+    Attempt to get next character from serial channel without pulling it
+    out of the buffer.
+**/
+int16_t SerialBase::CharPeek() {
+    // Return if nothing is waiting
+    if (m_inTail == m_inHead) {
+        return SerialBase::EOB;
+    }
+
+    // Get head character
+    int16_t peekChar = m_bufferIn[m_inHead];
+    return (peekChar);
+}
+
+/**
+    Attempt to send a character on serial channel
+**/
+bool SerialBase::SendChar(uint8_t charToSend) {
+    // Guard against sending to a closed port or an incorrect mode.
+    if (!m_portOpen || m_portMode == PortModes::SPI) {
+        return false;
+    }
+    // Calculate next location with wrap
+    uint32_t nextIndex = NextIndex(m_outTail);
+
+    // If the buffer is full, elevate the priority of the interrupt to drain
+    // the buffer and wait for some space to open up
+    while (nextIndex == m_outHead) {
+        if (!m_portOpen) {
+            return false;
+        }
+    }
+
+    // Queue this character on tail
+    m_bufferOut[m_outTail] = charToSend;
+    m_outTail = nextIndex;
+
+    EnableDreInterruptUart();
+    return true;
+}
+
+/**
+    SPI's TX and RX function
+**/
+uint8_t SerialBase::SpiTransferData(uint8_t data) {
+    if (!m_portOpen || m_portMode != PortModes::SPI) {
+        return 0;
+    }
+    // Write data into Data register
+    m_serPort->SPI.DATA.bit.DATA = data;
+
+    while (!m_serPort->SPI.INTFLAG.bit.RXC ||
+            !m_serPort->SPI.INTFLAG.bit.TXC) {
+        // If the port is not open, bail out
+        if (!m_portOpen) {
+            return 0;
+        }
+        // Wait for it to complete
+        continue;
+    }
+    return m_serPort->SPI.DATA.bit.DATA;
+}
+
+/**
+    SPI's multi-byte TX and RX function
+**/
+int32_t SerialBase::SpiTransferData(
+    uint8_t const *writeBuf, uint8_t *readBuf, int32_t len) {
+    if (!m_portOpen || m_portMode != SPI) {
+        return 0;
+    }
+
+    int32_t iChar;
+    for (iChar = 0; iChar < len; iChar++) {
+        // Write data into Data register
+        m_serPort->SPI.DATA.bit.DATA = writeBuf ? *writeBuf++ : 0;
+
+        while (!m_serPort->SPI.INTFLAG.bit.RXC ||
+                !m_serPort->SPI.INTFLAG.bit.TXC) {
+            // If the port is not open, bail out
+            if (!m_portOpen) {
+                return iChar;
+            }
+            // Wait for it to complete
+            continue;
+        }
+
+        if (readBuf) {
+            *readBuf++ = m_serPort->SPI.DATA.bit.DATA;
+        }
+        else {
+            // Read from the register (value unused).
+            (void)m_serPort->SPI.DATA.bit.DATA;
+        }
+    }
+
+    return iChar;
+}
+
+/**
+    SPI's asynchronous multi-byte TX and RX function
+**/
+bool SerialBase::SpiTransferDataAsync(
+    uint8_t const *writeBuf, uint8_t *readBuf, int32_t len) {
+    if (!m_portOpen || m_portMode != SPI) {
+        return false;
+    }
+    // Setup the DMA descriptors to perform asynchronous transfers
+    if (m_dmaRxChannel == DMA_INVALID_CHANNEL ||
+            m_dmaTxChannel == DMA_INVALID_CHANNEL) {
+        return false;
+    }
+    DmacDescriptor *baseDesc;
+
+    // Set up the Rx dest descriptor
+    baseDesc = DmaManager::BaseDescriptor(m_dmaRxChannel);
+    if (readBuf) {
+        baseDesc->DSTADDR.reg = (uint32_t)(readBuf + len);
+        baseDesc->BTCTRL.reg =
+            DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_VALID;
+    }
+    else {
+        baseDesc->DSTADDR.reg = (uint32_t)&spiDummy;
+        baseDesc->BTCTRL.reg = DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID;
+    }
+    baseDesc->BTCNT.reg = len;
+    DmaManager::Channel(m_dmaRxChannel)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+    // Set up the Tx source descriptor
+    baseDesc = DmaManager::BaseDescriptor(m_dmaTxChannel);
+    if (writeBuf) {
+        baseDesc->SRCADDR.reg = (uint32_t)(writeBuf + len);
+        baseDesc->BTCTRL.reg =
+            DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_VALID;
+    }
+    else {
+        baseDesc->SRCADDR.reg = (uint32_t)&spiDummy;
+        baseDesc->BTCTRL.reg = DMAC_BTCTRL_BEATSIZE_BYTE | DMAC_BTCTRL_VALID;
+    }
+    baseDesc->BTCNT.reg = len;
+    DmaManager::Channel(m_dmaTxChannel)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+
+    return true;
+}
+
+bool SerialBase::SpiAsyncWaitComplete() {
+    // If this channel is not set up to do DMA transfers, it is already done
+    if (m_dmaRxChannel == DMA_INVALID_CHANNEL ||
+            m_dmaTxChannel == DMA_INVALID_CHANNEL) {
+        return true;
+    }
+    // The transfer is done when all of the Rx data has been read and the
+    // channel disables
+    while (m_portOpen && m_portMode == SPI &&
+            DmaManager::Channel(m_dmaRxChannel)->CHCTRLA.bit.ENABLE) {
+        continue;
+    }
+    return true;
+}
+
+void SerialBase::HandleFrameError() {
+    // If there's a framing error raise a warning and clear the flag
+    if (m_serPort->USART.STATUS.bit.FERR) {
+        // Clear the hardware error flag
+        m_serPort->USART.STATUS.bit.FERR = 1;
+        // Set the error status bit
+        m_errorRegAccum.bit.SerialFrameError = 1;
+    }
+}
+
+void SerialBase::HandleParityError() {
+    // If there's a parity error raise a warning and clear the flag
+    if (m_serPort->USART.STATUS.bit.PERR) {
+        // Clear the hardware error flag
+        m_serPort->USART.STATUS.bit.PERR = 1;
+        // Set the error status bit
+        m_errorRegAccum.bit.SerialParityError = 1;
+    }
+}
+
+void SerialBase::HandleOverflow() {
+    // If there's an overflow error raise a warning and clear the flag
+    if (m_serPort->USART.STATUS.bit.BUFOVF) {
+        // Clear the hardware error flag
+        m_serPort->USART.STATUS.bit.BUFOVF = 1;
+        // Set the error status bit
+        m_errorRegAccum.bit.SerialOverflowError = 1;
+    }
+}
+
+SerialBase::SerialErrorStatusRegister SerialBase::ErrorStatusAccum(
+    SerialErrorStatusRegister mask) {
+    SerialErrorStatusRegister statusReg;
+    statusReg.reg = atomic_fetch_and(&m_errorRegAccum.reg, ~mask.reg) & mask.reg;
+    return statusReg;
+}
+
+/**
+    Wait for the output to be idle
+**/
+void SerialBase::WaitForTransmitIdle() {
+    if (m_portMode == UART) {
+        // Wait until the out buffer has emptied
+        while (m_outHead != m_outTail) {
+            continue;
+        }
+
+        if (m_serPort->USART.INTFLAG.bit.DRE) {
+            // Data register is already empty, no need to wait anymore
+            return;
+        }
+
+        // Wait for transmission to complete
+        while (!m_serPort->USART.INTFLAG.bit.TXC) {
+            continue;
+        }
+    }
+    else if (m_portMode == SPI) {
+        SpiAsyncWaitComplete();
+    }
+}
+
+/**
+    Return the number of free characters in the receive buffer
+**/
+int32_t SerialBase::AvailableForRead() {
+    int32_t difference = m_inTail - m_inHead;
+
+    if (difference < 0) {
+        return SERIAL_BUFFER_SIZE + difference;
+    }
+    else {
+        return difference;
+    }
+}
+
+/**
+    Returns the number of available characters in the transmit buffer
+**/
+int32_t SerialBase::AvailableForWrite() {
+    int32_t difference = m_outHead - m_outTail - 1;
+
+    if (difference < 0) {
+        difference += SERIAL_BUFFER_SIZE;
+    }
+
+    return difference;
+}
+
+// =========================== INTERRUPT API ===============================
+
+/**
+    Pulls characters from the DATA register and puts them in the rx buffer
+**/
+void SerialBase::RxProc() {
+    // Must reinitialize to clear ort problems
+    if (m_serPort->USART.RXERRCNT.reg != 0) {
+        // On break detected, flush inBuf and insert flag character
+        m_inTail = 0;
+        m_inHead = 0;
+        m_bufferIn[m_inTail++] = SerialBase::BREAK_DETECTED;
+
+        // Clear error to allow more interrupts
+        m_serPort->USART.INTFLAG.bit.ERROR = 1;
+    }
+
+    // Generate wrapped next location
+    uint32_t nextIndex = NextIndex(m_inTail);
+    while (m_serPort->USART.INTFLAG.bit.RXC && nextIndex != m_inHead) {
+        m_bufferIn[m_inTail] = m_serPort->USART.DATA.bit.DATA;
+        m_inTail = nextIndex;
+        nextIndex = NextIndex(m_inTail);
+    }
+    if (nextIndex == m_inHead) {
+        DisableRxcInterruptUart();
+    }
+}
+
+/**
+    Transmit any data waiting in the tx buffer
+**/
+void SerialBase::TxPump() {
+    while (m_outHead != m_outTail) {
+        if (!m_serPort->USART.INTFLAG.bit.DRE) {
+            // Data register is full; can't send anything more right now
+            return;
+        }
+        int32_t nextIndex = NextIndex(m_outHead);
+        m_serPort->USART.DATA.bit.DATA = m_bufferOut[m_outHead];
+        m_outHead = nextIndex;
+    }
+
+    DisableDreInterruptUart();
+}
+
+/**
+    The TX data service interrupt handler.
+
+    This should be called by SERCOMx_0 Interrupt Vector.
+**/
+void SerialBase::IrqHandlerTx() {
+    switch (m_portMode) {
+        case SPI:
+            break;
+        case UART:
+        default:
+            TxPump();
+            break;
+    }
+}
+
+/**
+    Should be called by SERCOMx_1 Interrupt Vector.
+**/
+void SerialBase::IrqHandler1() {
+    // Does nothing
+}
+
+/**
+    Interrupt handler for the RX data service.
+
+    This should be called by SERCOMx_2 Interrupt Vector.
+**/
+void SerialBase::IrqHandlerRx() {
+    switch (m_portMode) {
+        case SPI:
+            break;
+        case UART:
+        default:
+            RxProc();
+            break;
+    }
+}
+
+/**
+    Interrupt handler for any serial port exceptions.
+
+    Should be called by SERCOMx_3 Interrupt Vector.
+**/
+void SerialBase::IrqHandlerException() {
+    switch (m_portMode) {
+        case SPI:
+            // This should not occur, but clear the interrupt flags to be safe.
+            m_serPort->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+            break;
+        case UART:
+        default:
+            if (m_serPort->USART.INTFLAG.bit.ERROR) {
+                // Clear the interrupt flag
+                m_serPort->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+                HandleFrameError();
+                HandleParityError();
+                HandleOverflow();
+            }
+            break;
+    }
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialDriver.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialDriver.cpp
new file mode 100644
index 000000000..6b1076db8
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialDriver.cpp
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    SerialDriver implementation
+
+    ClearCore Serial Connector Implementation.
+**/
+#include "SerialDriver.h"
+#include <stdio.h>
+#include "CcioBoardManager.h"
+#include "SerialBase.h"
+#include "SysUtils.h"
+
+#define CCIO_DEFAULT_BAUD_RATE    500000
+
+namespace ClearCore {
+
+// LED feedback and option shift register
+extern ShiftRegister ShiftReg;
+// CCIO-8 management
+extern CcioBoardManager &CcioMgr;
+
+SerialDriver::SerialDriver(uint16_t index,
+                           ShiftRegister::Masks feedBackLedMask,
+                           ShiftRegister::Masks controlMask,
+                           ShiftRegister::Masks polarityMask,
+                           const PeripheralRoute *ctsMisoInfo,
+                           const PeripheralRoute *rtsSsInfo,
+                           const PeripheralRoute *rxSckInfo,
+                           const PeripheralRoute *txMosiInfo,
+                           uint8_t peripheral)
+    : SerialBase(ctsMisoInfo, rtsSsInfo, rxSckInfo, txMosiInfo,
+                 peripheral),
+      m_index(index),
+      m_ledMask(feedBackLedMask),
+      m_controlMask(controlMask),
+      m_polarityMask(polarityMask) {}
+
+void SerialDriver::Initialize(ClearCorePins clearCorePin) {
+    m_clearCorePin = clearCorePin;
+    PortClose();
+    // Default to TTL mode
+    Mode(ConnectorModes::TTL);
+}
+
+bool SerialDriver::Mode(ConnectorModes newMode) {
+    SerialBase::PortModes portMode;
+
+    if (m_mode == newMode) {
+        // No change needed
+        return true;
+    }
+
+    if (m_mode == Connector::CCIO) {
+        CcioMgr.LinkClose();
+    }
+
+    switch (newMode) {
+        case Connector::CCIO:
+            SpiClock(SerialDriver::SCK_LOW, SerialDriver::LEAD_CHANGE);
+            SpiSsMode(SerialBase::CtrlLineModes::LINE_ON);
+            Speed(CCIO_DEFAULT_BAUD_RATE);
+        // Fall through
+        case Connector::SPI:
+            portMode = SerialBase::SPI;
+            ShiftReg.ShifterStateClear(m_polarityMask);
+            ShiftReg.ShifterStateSet(m_controlMask);
+            break;
+        case Connector::RS232:
+            // Clear the polarity bit to make compatible with RS232 levels
+            portMode = SerialBase::UART;
+            ShiftReg.ShifterStateSet(m_polarityMask);
+            ShiftReg.ShifterStateClear(m_controlMask);
+            break;
+        case Connector::TTL:
+            portMode = SerialBase::UART;
+            // Set polarity to make signaling TTL standard levels
+            ShiftReg.ShifterStateClear(m_polarityMask);
+            ShiftReg.ShifterStateClear(m_controlMask);
+            break;
+        default:
+            // Invalid mode
+            return false;
+    }
+
+    m_mode = newMode;
+
+    // Set up base class to use this mode
+    PortMode(portMode);
+
+    // Delay to allow the port polarity to be written to the shift
+    // register and settle for a full character time before sending data
+    if (m_portOpen) {
+        WaitOneCharTime();
+    }
+    return true;
+}
+
+void SerialDriver::PortOpen() {
+    if (!SerialBase::PortIsOpen()) {
+        SerialBase::PortOpen();
+        // Delay to allow the port polarity to be written to the shift
+        // register and settle for a full character time before sending data
+        WaitOneCharTime();
+        // LED under connector on
+        ShiftReg.ShifterStateSet(m_ledMask);
+
+        // Initialize the CCIO manager
+        if (m_mode == Connector::CCIO) {
+            CcioMgr.CcioDiscover(this);
+        }
+    }
+}
+
+void SerialDriver::PortClose() {
+    if (SerialBase::PortIsOpen()) {
+        if (m_mode == Connector::CCIO) {
+            CcioMgr.LinkClose();
+        }
+        SerialBase::PortClose();
+        // LED under connector off
+        ShiftReg.ShifterStateClear(m_ledMask);
+    }
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialUsb.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialUsb.cpp
new file mode 100644
index 000000000..2102bdbec
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SerialUsb.cpp
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ClearCore USB Serial Connector Implementation.
+**/
+#include "SerialUsb.h"
+#include "UsbManager.h"
+
+namespace ClearCore {
+
+extern UsbManager &UsbMgr;
+
+SerialUsb::SerialUsb(uint16_t index) :
+    m_index(index) {}
+
+void SerialUsb::FlushInput() {
+    UsbMgr.FlushInput();
+}
+
+void SerialUsb::Flush() {
+    UsbMgr.WaitForWriteFinish();
+}
+
+bool SerialUsb::PortIsOpen() {
+    return static_cast<bool>(UsbMgr);
+}
+
+void SerialUsb::PortOpen() {
+    UsbMgr.PortOpen();
+}
+
+void SerialUsb::PortClose() {
+    UsbMgr.PortClose();
+}
+
+bool SerialUsb::Speed(uint32_t bitsPerSecond) {
+    return UsbMgr.Speed(bitsPerSecond);
+}
+
+uint32_t SerialUsb::Speed() {
+    return UsbMgr.Speed();
+}
+
+int16_t SerialUsb::CharGet() {
+    return UsbMgr.CharGet();
+}
+
+int16_t SerialUsb::CharPeek() {
+    return UsbMgr.CharPeek();
+}
+
+bool SerialUsb::SendChar(uint8_t charToSend) {
+    return UsbMgr.SendChar(charToSend);
+}
+
+int32_t SerialUsb::AvailableForRead() {
+    return UsbMgr.AvailableForRead();
+}
+
+int32_t SerialUsb::AvailableForWrite() {
+    return UsbMgr.AvailableForWrite();
+}
+
+void SerialUsb::WaitForTransmitIdle() {
+    UsbMgr.WaitForWriteFinish();
+}
+
+SerialUsb::operator bool() {
+    return static_cast<bool>(UsbMgr);
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/ShiftRegister.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/ShiftRegister.cpp
new file mode 100644
index 000000000..5739c1d67
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/ShiftRegister.cpp
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    LED shift register chain implementation
+
+    Implementation of ClearCore shift register chain for LED displays and
+    connector setups.
+**/
+
+#include "ShiftRegister.h"
+#include <sam.h>
+#include "atomic_utils.h"
+#include "HardwareMapping.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+
+namespace ClearCore {
+
+/**
+    Constructs and adjusts inversions for hardware constraints
+**/
+ShiftRegister::ShiftRegister() :
+    m_fastCounter(FAST_COUNTER_PERIOD, FAST_COUNTER_CC),
+    m_breathingCounter(),
+    m_fadeCounter(),
+    m_patternMasks{UINT32_MAX},
+    m_patternOutputs{SR_UNDERGLOW_MASK},
+    m_altOutput(0),
+    m_initialized(false),
+    m_blinkCodeActive(false),
+    m_blinkCodeState(false),
+    m_useAltOutput(false),
+    m_pendingOutput(0),
+    m_lastOutput(0) {
+    m_shiftInversions.reg = 0xffffffff;
+    m_shiftInversions.bit.LED_USB = 0;
+    m_shiftInversions.bit.LED_IO_4 = 0;
+    m_shiftInversions.bit.LED_IO_5 = 0;
+    m_shiftInversions.bit.LED_COM_0 = 0;
+    m_shiftInversions.bit.LED_COM_1 = 0;
+    m_shiftInversions.bit.UNDERGLOW = 0;
+    m_shiftInversions.bit.EN_OUT_0 = 0;
+    m_shiftInversions.bit.EN_OUT_1 = 0;
+    m_shiftInversions.bit.EN_OUT_2 = 0;
+    m_shiftInversions.bit.EN_OUT_3 = 0;
+    m_shiftInversions.bit.UART_TTL_0 = 0;
+    m_shiftInversions.bit.UART_TTL_1 = 0;
+}
+
+/**
+    Turn on the shifter and setup the mode for SPI
+**/
+void ShiftRegister::Initialize() {
+    SET_CLOCK_SOURCE(SERCOM6_GCLK_ID_CORE, 5);
+    CLOCK_ENABLE(APBDMASK, SERCOM6_);
+
+    // Set up pins for SERCOM6 in SPI master mode and enable it to control them
+    PMUX_SELECTION(SR_CLK.gpioPort, SR_CLK.gpioPin, PER_SERCOM);
+    PMUX_ENABLE(SR_CLK.gpioPort, SR_CLK.gpioPin);
+
+    PMUX_SELECTION(SR_DATA.gpioPort, SR_DATA.gpioPin, PER_SERCOM);
+    PMUX_ENABLE(SR_DATA.gpioPort, SR_DATA.gpioPin);
+
+    PMUX_SELECTION(SR_DATA_RET.gpioPort, SR_DATA_RET.gpioPin, PER_SERCOM);
+    PMUX_ENABLE(SR_DATA_RET.gpioPort, SR_DATA_RET.gpioPin);
+
+    // Set up Load/Enable pins as outputs
+    DATA_OUTPUT_STATE(SR_ENn.gpioPort, 1UL << SR_ENn.gpioPin, true);
+    DATA_OUTPUT_STATE(SR_LOAD.gpioPort, 1UL << SR_LOAD.gpioPin, false);
+    DATA_DIRECTION_OUTPUT(SR_ENn.gpioPort, (1UL << SR_ENn.gpioPin));
+    DATA_DIRECTION_OUTPUT(SR_LOAD.gpioPort, (1UL << SR_LOAD.gpioPin));
+
+    // A pointer to the SPI register to make things easier.
+    SercomSpi *sercomSpi = &SERCOM6->SPI;
+
+    // Disable SERCOM6 to switch its role
+    sercomSpi->CTRLA.bit.ENABLE = 0;
+    SYNCBUSY_WAIT(sercomSpi, SERCOM_SPI_SYNCBUSY_ENABLE);
+
+    // Sets SERCOM6 to SPI Master mode
+    sercomSpi->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3);
+    // Sets PAD[3] to DO, PAD[2] to DI, and sets LSB-first transmission
+    sercomSpi->CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(0x2) |
+                            SERCOM_SPI_CTRLA_DIPO(0x2) |
+                            SERCOM_SPI_CTRLA_DORD;
+
+    // Enables the data receiver
+    sercomSpi->CTRLB.bit.RXEN = 1;
+
+    // Enables 32-bit DATA register transactions
+    sercomSpi->CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B;
+
+    // Sets the baud rate to GCLK1 frequency
+    sercomSpi->BAUD.reg = 0;
+
+    // Enables SERCOM6 and wait for core sync
+    sercomSpi->CTRLA.bit.ENABLE = 1;
+    SYNCBUSY_WAIT(sercomSpi, SERCOM_SPI_SYNCBUSY_ENABLE);
+
+    // Send the initial values to the chain
+    sercomSpi->DATA.reg = atomic_load_n(&m_patternOutputs[LED_BLINK_IO_SET])
+                          ^ m_shiftInversions.reg;
+
+    // Generate strobe and update
+    Send();
+
+    // Enable the chain, clear and set SR_EN_N
+    DATA_OUTPUT_STATE(SR_ENn.gpioPort, 1UL << SR_ENn.gpioPin, false);
+
+    // Allow timer tick to update
+    m_initialized = true;
+}
+
+void ShiftRegister::Update() {
+    if (!m_initialized) {
+        return;
+    }
+
+    // Update Counter Outputs
+    m_patternOutputs[LED_BLINK_FAST_STROBE]  = m_fastCounter.Update();
+    m_patternOutputs[LED_BLINK_BREATHING]    = m_breathingCounter.Update();
+    m_patternOutputs[LED_BLINK_FADE]         = m_fadeCounter.Update();
+
+    Send();
+}
+
+void ShiftRegister::Send() {
+    // Wait for TX-complete interrupt flag in case we get here too quickly
+    while (!(SERCOM6->SPI.INTFLAG.bit.TXC)) {
+        continue;
+    }
+    uint32_t output;
+
+    // Strobe the output with minimum pulse width to display last transfer
+    DATA_OUTPUT_STATE(SR_LOAD.gpioPort, 1UL << SR_LOAD.gpioPin, true);
+    DATA_OUTPUT_STATE(SR_LOAD.gpioPort, 1UL << SR_LOAD.gpioPin, false);
+    while (!(SERCOM6->SPI.INTFLAG.bit.RXC)) {
+        continue;
+    }
+    m_latchedOutput = SERCOM6->SPI.DATA.reg ^ m_shiftInversions.reg;
+    m_lastOutput = m_pendingOutput;
+
+    if (m_useAltOutput) {
+        output = m_altOutput;
+    }
+    else {
+        // Start the output with the low priority mask
+        output = m_patternOutputs[LED_BLINK_IO_SET];
+        // Start at 1 to skip the user LEDs
+        for (uint32_t i = LED_BLINK_IO_SET + 1; i < LED_BLINK_CODE_MAX; i++) {
+            // AND in the inverse of the mask to clear out the lower priority
+            // patterns.
+            output &= ~m_patternMasks[i];
+            // Set the output bits to the output of the pattern output.
+            output |= m_patternOutputs[i] & m_patternMasks[i];
+        }
+
+        if (m_blinkCodeActive) {
+            output &= ~SR_UNDERGLOW_MASK;
+            if (m_blinkCodeState) {
+                output |= SR_UNDERGLOW_MASK;
+            }
+        }
+    }
+    m_pendingOutput = output;
+
+    // Apply inversion
+    output ^= m_shiftInversions.reg;
+
+    SERCOM6->SPI.DATA.reg = output;
+}
+
+/**
+    Turn all of the LEDs on briefly so the user can see that they all work.
+**/
+void ShiftRegister::DiagnosticLedSweep() {
+    m_altOutput = 0;
+    m_useAltOutput = true;
+    // Illuminate bank 2
+    for (uint8_t i = 0; i < LED_BANK_2_LEN; i++) {
+        m_altOutput |= LED_BANK_2[i];
+        Delay_ms(DELAY_TIME);
+    }
+
+    // Illuminate bank 0 and 1 simultaneously
+    uint8_t largerBankLen = (LED_BANK_1_LEN > LED_BANK_0_LEN) ? LED_BANK_1_LEN
+                            : LED_BANK_0_LEN;
+    for (uint8_t i = 0; i < largerBankLen; i++) {
+        if (i < LED_BANK_0_LEN) {
+            m_altOutput |= LED_BANK_0[i];
+        }
+        if (i < LED_BANK_1_LEN) {
+            m_altOutput |= LED_BANK_1[i];
+        }
+
+        Delay_ms(DELAY_TIME);
+    }
+
+    Delay_ms(50);
+
+    // Turn them off the same way they were turned on
+    for (uint8_t i = 0; i < LED_BANK_2_LEN; i++) {
+        m_altOutput &= ~LED_BANK_2[i];
+        Delay_ms(DELAY_TIME);
+    }
+
+    ShifterStateSet(SR_UNDERGLOW_MASK);
+
+    for (uint8_t i = 0; i < largerBankLen; i++) {
+        if (i < LED_BANK_0_LEN) {
+            m_altOutput &= ~LED_BANK_0[i];
+        }
+        if (i < LED_BANK_1_LEN) {
+            m_altOutput &= ~LED_BANK_1[i];
+        }
+
+        Delay_ms(DELAY_TIME);
+    }
+    m_useAltOutput = false;
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/StatusManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/StatusManager.cpp
new file mode 100644
index 000000000..3164fc135
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/StatusManager.cpp
@@ -0,0 +1,349 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "StatusManager.h"
+#include <stddef.h>
+#include <stdio.h>
+#include "atomic_utils.h"
+#include "AdcManager.h"
+#include "CcioBoardManager.h"
+#include "DigitalInOutHBridge.h"
+#include "EthernetManager.h"
+#include "HardwareMapping.h"
+#include "MotorDriver.h"
+#include "NvmManager.h"
+#include "SdCardDriver.h"
+#include "SysConnectors.h"
+#include "SysTiming.h"
+
+namespace ClearCore {
+
+extern volatile uint32_t tickCnt;
+extern DigitalInOutHBridge *const hBridgeCon[];
+extern MotorDriver *const MotorConnectors[];
+extern AdcManager &AdcMgr;
+extern CcioBoardManager &CcioMgr;
+extern EthernetManager &EthernetMgr;
+extern NvmManager &NvmMgr;
+extern ShiftRegister ShiftReg;
+extern SdCardDriver SdCard;
+StatusManager &StatusMgr = StatusManager::Instance();
+
+#define OFFBOARD_5V_TRIP_V 4.0
+#define OVER_VOLTAGE_TRIP_V 32.0
+#define UNDER_VOLTAGE_TRIP_V 10.0
+#define OFFBOARD_5V_EXIT_V 4.5
+#define OVER_VOLTAGE_EXIT_V 28.0
+#define UNDER_VOLTAGE_EXIT_V 11.0
+
+// calc: TripInVolts * (1 << 15) / MaxReadoutInVolts
+#define OFFBOARD_5V_TRIP_CNT ((uint16_t)(OFFBOARD_5V_TRIP_V * (1 << 15) / \
+   AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_5VOB_MON]))
+#define OVER_VOLTAGE_TRIP_CNT ((uint16_t)(OVER_VOLTAGE_TRIP_V * (1 << 15) / \
+   AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_VSUPPLY_MON]))
+#define UNDER_VOLTAGE_TRIP_CNT ((uint16_t)(UNDER_VOLTAGE_TRIP_V * (1 << 15) / \
+   AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_VSUPPLY_MON]))
+#define OFFBOARD_5V_EXIT_CNT ((uint16_t)(OFFBOARD_5V_EXIT_V * (1 << 15) / \
+   AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_5VOB_MON]))
+#define OVER_VOLTAGE_EXIT_CNT ((uint16_t)(OVER_VOLTAGE_EXIT_V * (1 << 15) / \
+   AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_VSUPPLY_MON]))
+#define UNDER_VOLTAGE_EXIT_CNT ((uint16_t)(UNDER_VOLTAGE_EXIT_V * (1 << 15) / \
+   AdcManager::ADC_CHANNEL_MAX_FLOAT[AdcManager::ADC_VSUPPLY_MON]))
+
+
+// Ensures that only one instance of StatusManager is ever created.
+StatusManager &StatusManager::Instance() {
+    static StatusManager *instance = new StatusManager;
+    return *instance;
+}
+
+StatusManager::StatusRegister StatusManager::StatusRT(StatusRegister mask) {
+    StatusRegister statusReg;
+    statusReg.reg = atomic_load_n(&m_statusRegRT.reg) & mask.reg;
+    return statusReg;
+}
+
+StatusManager::StatusRegister StatusManager::StatusRisen(StatusRegister mask) {
+    StatusRegister statusReg;
+    statusReg.reg =
+        atomic_fetch_and(&m_statusRegRisen.reg, ~mask.reg) & mask.reg;
+    return statusReg;
+}
+
+StatusManager::StatusRegister StatusManager::StatusFallen(StatusRegister mask) {
+    StatusRegister statusReg;
+    statusReg.reg =
+        atomic_fetch_and(&m_statusRegFallen.reg, ~mask.reg) & mask.reg;
+    return statusReg;
+}
+
+StatusManager::StatusRegister StatusManager::StatusAccum(StatusRegister mask) {
+    StatusRegister statusReg;
+    statusReg.reg =
+        atomic_fetch_and(&m_statusRegAccum.reg, ~mask.reg) & mask.reg;
+    atomic_exchange_n(&m_statusRegAccum.reg, atomic_load_n(&m_statusRegRT.reg));
+    return statusReg;
+}
+
+StatusManager::StatusRegister StatusManager::SinceStartupAccum(
+    StatusRegister mask) {
+    StatusRegister statusReg;
+    statusReg.reg = atomic_load_n(&m_statusRegSinceStartup.reg) & mask.reg;
+    return statusReg;
+}
+
+bool StatusManager::AdcIsInTimeout() {
+    StatusRegister statusReg = StatusRT();
+    return statusReg.bit.AdcTimeout;
+}
+
+SysConnectorState StatusManager::IoOverloadRT(SysConnectorState mask) {
+    SysConnectorState overloadReg;
+    overloadReg.reg = atomic_load_n(&m_overloadRT.reg) & mask.reg;
+    return overloadReg;
+}
+
+SysConnectorState StatusManager::IoOverloadAccum(SysConnectorState mask) {
+    SysConnectorState overloadReg;
+    overloadReg.reg =
+        atomic_fetch_and(&m_overloadAccum.reg, ~mask.reg) & mask.reg;
+    m_overloadAccum.reg = m_overloadRT.reg;
+    return overloadReg;
+}
+
+SysConnectorState StatusManager::IoOverloadSinceStartupAccum(
+    SysConnectorState mask) {
+    SysConnectorState overloadReg;
+    overloadReg.reg = atomic_load_n(&m_overloadSinceStartup.reg) & mask.reg;
+    return overloadReg;
+}
+
+inline bool Offboard5VCheck(bool currentStatus) {
+    return (currentStatus &&
+            AdcMgr.FilteredResult(AdcManager::ADC_5VOB_MON) <
+            OFFBOARD_5V_EXIT_CNT) || (!currentStatus &&
+                                      AdcMgr.FilteredResult(AdcManager::ADC_5VOB_MON) <
+                                      OFFBOARD_5V_TRIP_CNT);
+}
+
+inline bool VSupplyOverVoltageCheck(bool currentStatus) {
+    return (currentStatus &&
+            AdcMgr.FilteredResult(AdcManager::ADC_VSUPPLY_MON) >=
+            OVER_VOLTAGE_EXIT_CNT) || (!currentStatus &&
+                                       AdcMgr.FilteredResult(AdcManager::ADC_VSUPPLY_MON) >=
+                                       OVER_VOLTAGE_TRIP_CNT);
+}
+
+inline bool VSupplyUnderVoltageCheck(bool currentStatus) {
+    return (currentStatus &&
+            AdcMgr.FilteredResult(AdcManager::ADC_VSUPPLY_MON) <
+            UNDER_VOLTAGE_EXIT_CNT) || (!currentStatus &&
+                                        AdcMgr.FilteredResult(AdcManager::ADC_VSUPPLY_MON) <
+                                        UNDER_VOLTAGE_TRIP_CNT);
+}
+
+inline bool HBridgeFaultCheck() {
+    return (!static_cast<bool>(PORT->Group[OutFault_04or05.gpioPort].IN.reg &
+                               (1UL << OutFault_04or05.gpioPin)));
+}
+
+bool StatusManager::Initialize(ShiftRegister::Masks faultLed) {
+    m_faultLed = faultLed;
+    m_disableMotors = false;
+    m_statusRegSinceStartup = 0;
+    ShiftReg.DiagnosticLedSweep();
+
+    return true;
+}
+
+void StatusManager::Refresh() {
+    // Temporary holder for status fields while being populated.
+    // Write all values to temp then do one atomic exchange
+    StatusRegister statusPrev;
+    StatusRegister statusPending;
+
+    // Load contents of the real-time status register into statusPrev
+    atomic_load(&m_statusRegRT.reg, &statusPrev.reg);
+
+    // Load the contents of statusPending with current status information
+    statusPending.bit.VSupplyOverVoltage =
+        VSupplyOverVoltageCheck(statusPrev.bit.VSupplyOverVoltage);
+    statusPending.bit.VSupplyUnderVoltage =
+        VSupplyUnderVoltageCheck(statusPrev.bit.VSupplyUnderVoltage);
+    statusPending.bit.Overloaded5V =
+        Offboard5VCheck(statusPrev.bit.Overloaded5V);
+    statusPending.bit.HBridgeOverloaded = HBridgeFaultCheck();
+    statusPending.bit.HBridgeReset = m_hbridgeResetting;
+    statusPending.bit.AdcTimeout = AdcMgr.AdcTimeout();
+    statusPending.bit.OutputOverloaded =
+        static_cast<bool>(ShiftReg.OverloadActive());
+    statusPending.bit.CcioLinkBroken = CcioMgr.LinkBroken();
+    statusPending.bit.CcioOverloaded = CcioMgr.IoOverloadRT();
+    statusPending.bit.EthernetDisconnect = !EthernetMgr.PhyLinkActive();
+    statusPending.bit.EthernetRemoteFault = EthernetMgr.PhyRemoteFault();
+    statusPending.bit.EthernetPhyInitFailed = EthernetMgr.PhyInitFailed();
+    statusPending.bit.SdCardError = SdCard.IsInFault();
+    statusPending.bit.NvmDesync = !NvmMgr.Synchonized();
+
+    UpdateBlinkCodes(statusPending);
+
+    if (hBridgeCon[0]->Mode() != Connector::OUTPUT_DIGITAL) {
+        ShiftReg.LedInFault(ShiftRegister::SR_LED_IO_4_MASK,
+                            statusPending.bit.HBridgeOverloaded);
+    }
+    if (hBridgeCon[1]->Mode() != Connector::OUTPUT_DIGITAL) {
+        ShiftReg.LedInFault(ShiftRegister::SR_LED_IO_5_MASK,
+                            statusPending.bit.HBridgeOverloaded);
+    }
+
+    // Write the updates in statusPending to the real-time register
+    atomic_load(&statusPending.reg, &m_statusRegRT.reg);
+
+    // Update the edge detection registers
+    atomic_or_fetch(&m_statusRegFallen.reg,
+                    statusPrev.reg & ~statusPending.reg);
+    atomic_or_fetch(&m_statusRegRisen.reg,
+                    ~statusPrev.reg & statusPending.reg);
+
+    // Update the accumulating registers
+    atomic_or_fetch(&m_statusRegAccum.reg, statusPending.reg);
+    atomic_or_fetch(&m_statusRegSinceStartup.reg, statusPending.reg);
+
+    bool disableMotorsPrev = m_disableMotors;
+
+    // Disable the MotorDrivers when the Vbus is overloaded, or the HBridge is
+    // resetting. When HBridge is resetting, the reading for Vbus is cut off
+    // and cannot be read. To prevent an undetected overvoltage, disable motors.
+    m_disableMotors = m_statusRegRT.bit.VSupplyOverVoltage |
+                      m_statusRegRT.bit.HBridgeReset;
+
+    // Set the motor disableMotors transition
+    if (disableMotorsPrev != m_disableMotors) {
+        for (uint8_t i = 0; i < MOTOR_CON_CNT; i++) {
+            MotorConnectors[i]->FaultState(m_disableMotors);
+        }
+        for (uint8_t i = 0; i < HBRIDGE_CON_CNT; i++) {
+            hBridgeCon[i]->FaultState(m_disableMotors);
+        }
+    }
+}
+
+void StatusManager::HBridgeReset() {
+    HBridgeState(true);
+
+    // Wait 2 System Ticks for the Refresh function to come through
+    // and force all motor outputs to disable
+    uint32_t tickStart = tickCnt;
+    while (tickCnt - tickStart < 2) {
+        continue;
+    }
+
+    HBridgeState(false);
+}
+
+void StatusManager::HBridgeState(bool reset) {
+    ClearCorePorts port = Vsupply_MON_IO_4and5_RST.gpioPort;
+    uint32_t pin = Vsupply_MON_IO_4and5_RST.gpioPin;
+    StatusRegister resetBit;
+    resetBit.bit.HBridgeReset = 1;
+    m_hbridgeResetting = reset;
+
+    if (reset) {
+        atomic_or_fetch(&m_statusRegRT.reg, resetBit.reg);
+        atomic_or_fetch(&m_statusRegRisen.reg, resetBit.reg);
+        // Configure the pin for I/O
+        PIN_CONFIGURATION(port, pin, PORT_PINCFG_INEN);
+        // Set the pin to output HIGH
+        DATA_OUTPUT_STATE(port, 1UL << pin, true);
+        // Set the pin as an output
+        DATA_DIRECTION_OUTPUT(port, 1UL << pin);
+    }
+    else {
+        // Set the pin as an input
+        DATA_DIRECTION_INPUT(port, 1UL << pin);
+        // Enable the Peripheral Multiplexer
+        PMUX_ENABLE(port, pin);
+    }
+}
+
+void StatusManager::BlinkCode(BlinkCodeDriver::BlinkCodeGroups group,
+                              uint8_t mask) {
+    m_blinkMgr.CodeGroupAdd(group, mask);
+}
+
+void StatusManager::UpdateBlinkCodes(StatusRegister status) {
+    if (status.bit.VSupplyOverVoltage) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_SUPPLY_ERROR,
+            BlinkCodeDriver::SUPPLY_ERROR_VSUPPLY_HIGH);
+    }
+    if (status.bit.VSupplyUnderVoltage) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_SUPPLY_ERROR,
+            BlinkCodeDriver::SUPPLY_ERROR_VSUPPLY_LOW);
+    }
+    if (status.bit.HBridgeOverloaded) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+            BlinkCodeDriver::DEVICE_ERROR_HBRIDGE);
+    }
+    if (status.bit.Overloaded5V) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_SUPPLY_ERROR,
+            BlinkCodeDriver::SUPPLY_ERROR_5VOB_OVERLOAD);
+    }
+    if (status.bit.SdCardError) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+            BlinkCodeDriver::DEVICE_ERROR_SD_CARD);
+    }
+    // Only report Ethernet problems if we called EthernetManager::Setup()
+    // and expect Ethernet to be functional.
+    if (EthernetMgr.EthernetActive() &&
+            (status.bit.EthernetRemoteFault ||
+             status.bit.EthernetPhyInitFailed)) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+            BlinkCodeDriver::DEVICE_ERROR_ETHERNET);
+    }
+    if (status.bit.CcioLinkBroken) {
+        m_blinkMgr.CodeGroupAdd(
+            BlinkCodeDriver::BLINK_GROUP_DEVICE_ERROR,
+            BlinkCodeDriver::DEVICE_ERROR_CCIO);
+    }
+
+    m_blinkMgr.Update();
+    ShiftReg.BlinkCode(m_blinkMgr.CodePresent(), m_blinkMgr.LedState());
+}
+
+void StatusManager::OverloadUpdate(uint32_t mask, bool inFault) {
+    if (inFault) {
+        m_overloadRT.reg |= mask;
+    }
+    else {
+        m_overloadRT.reg &= ~mask;
+    }
+    m_overloadSinceStartup.reg |= m_overloadRT.reg;
+    m_overloadAccum.reg |= m_overloadRT.reg;
+}
+
+}
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/StepGenerator.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/StepGenerator.cpp
new file mode 100644
index 000000000..4db5e16d3
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/StepGenerator.cpp
@@ -0,0 +1,619 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "StepGenerator.h"
+#include <math.h>
+#include <sam.h>
+#include "SysTiming.h"
+
+namespace ClearCore {
+
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+
+/*
+    This is an internal function to calculate how many pulses to send to each
+    motor. It tracks the current command, as well as how many steps have been
+    sent, and calculates how many steps to send in the next ISR.
+*/
+
+void StepGenerator::StepsCalculated() {
+
+    // Perform setup for a newly issued move.
+    // This is handled separately from the main state machine to determine
+    // determine the proper entry state and begin executing without delaying
+    // until the next sample.
+    if (m_moveState == MS_START) {
+        // Compute move parameters
+        m_accelCurrentQx = m_accelLimitQx;
+        m_posnTargetQx = static_cast<int64_t>(m_stepsCommanded)
+                         << FRACT_BITS;
+
+        if (m_velocityMove) {
+            if (m_altVelLimitQx && m_velCurrentQx && m_direction != m_dirCommanded) {
+                m_velTargetQx = 0;
+                m_moveDirChange = true;
+            }
+            else {
+                m_velTargetQx = m_altVelLimitQx;
+                m_moveDirChange = false;
+            }
+            if (m_velTargetQx) {
+                // Notify the system of the direction of the issued move
+                // if moving to a non-zero velocity
+                m_direction = m_dirCommanded;
+                OutputDirection();
+            }
+
+            if (m_velCurrentQx == m_velTargetQx) {
+                // Already at the correct velocity
+                m_moveState = MS_CRUISE;
+            }
+            else if (m_velCurrentQx > m_velTargetQx) {
+                // Decelerate to reach the target velocity
+                m_moveState = MS_DECEL_VEL;
+            }
+            else {
+                // Accelerate to reach the target velocity
+                m_moveState = MS_ACCEL;
+            }
+        }
+        else {
+            if (m_velCurrentQx) {
+                // Currently moving, check for a change in direction
+                if (m_direction == m_dirCommanded) {
+                    // A direction change is also needed if we overshoot our target position
+                    int64_t distToStopQx = (static_cast<int64_t>(m_velCurrentQx) * m_velCurrentQx /
+                                          m_accelCurrentQx) >> 1;
+                    // The distance to stop is how many steps it will take to slow to 0 velocity
+                    // If the number of commanded steps is less than that, we cannot stop in
+                    // time and must overshoot and come back.
+                    m_moveDirChange = m_posnTargetQx - m_posnCurrentQx < distToStopQx;
+                }
+                else {
+                    m_moveDirChange = true;
+                }
+                
+            }
+            else {
+                m_moveDirChange = false;
+                m_direction = m_dirCommanded;
+                if (m_posnTargetQx != m_posnCurrentQx) {
+                    // Notify the system of the direction of the issued move
+                    OutputDirection();
+                }
+            }
+            
+            if (m_moveDirChange) {
+                m_moveState = MS_DECEL_VEL;
+                m_velTargetQx = 0;
+            }
+
+            else {
+                // If the move profile is a triangle (i.e. doesn't reach
+                // VelLimit), set the velocity limit to peak velocity so that
+                // trapezoid logic can be used.
+                // The maximum triangle move distance =
+                //     VelLimit * (AccelSamples + DecelSamples) / 2 = V*V/A
+                // Account for the steps that would have been used to accelerate
+                // to the current velocity.
+                int64_t accelStepsQx = (static_cast<int64_t>(m_velCurrentQx) *
+                                        m_velCurrentQx / 2) / m_accelLimitQx;
+                if (static_cast<int64_t>(m_velLimitQx) * m_velLimitQx /
+                        m_accelLimitQx - accelStepsQx > m_posnTargetQx) {
+                    // Multiplication by 2^FRACT_BITS to preserve Q-format
+                    int64_t vel64 =
+                        static_cast<int64_t>(sqrtf((float)(
+                                                       ((static_cast<int64_t>(m_stepsCommanded) << FRACT_BITS)
+                                                        + accelStepsQx) * m_accelLimitQx)));
+
+                    m_velTargetQx = static_cast<int32_t>(min(vel64, INT32_MAX));
+                }
+                else {
+                    m_velTargetQx = m_velLimitQx;
+                }
+                if (m_velCurrentQx > m_velTargetQx) {
+                    // Decelerate to reach the target velocity
+                    m_moveState = MS_DECEL_VEL;
+                }
+                else {
+                    // Accelerate to reach the target velocity
+                    m_moveState = MS_ACCEL;
+                }
+            }
+        }
+    }
+
+    // Process the current move state.
+    switch (m_moveState) {
+        case MS_IDLE: // Idle state, waiting for a command.
+            return;
+        case MS_START: // Start state, this case was handled above
+            break;
+
+        case MS_ACCEL: // Ramp up to target speed
+            // Execute move
+            m_posnCurrentQx += m_velCurrentQx + (m_accelCurrentQx >> 1);
+            m_velCurrentQx += m_accelCurrentQx;
+
+            // Check if we reached target velocity or velocity overflow
+            if (m_velCurrentQx >= m_velTargetQx || m_velCurrentQx <= 0) {
+                // If maximum velocity reached, compute the distance overshoot
+                // from exceeding the velocity limit.
+                // Dist Over = % of sample time past when the vel was reached
+                //             * vel overshoot / 2
+                uint32_t overshootQx = m_velCurrentQx - m_velTargetQx;
+                uint32_t pctSampleOverQ32 =
+                    ((static_cast<uint64_t>(overshootQx)) << 32) /
+                    m_accelCurrentQx;
+                // Build in the divide by 2
+                uint32_t posnAdjQx =
+                    (static_cast<uint64_t>(pctSampleOverQ32) * overshootQx) >>
+                    33;
+
+                m_velCurrentQx = m_velTargetQx;
+                // Adjust position for overshoot.
+                // Also subtract off the distance moved in one sample time at
+                // target velocity to allow cruise state logic to determine
+                // whether we should start decelerating.
+                m_posnCurrentQx -= (posnAdjQx + m_velCurrentQx);
+                // Calculate the decel point
+                uint64_t decelDistQx = (static_cast<uint64_t>(m_velCurrentQx) *
+                                        m_velCurrentQx / m_accelCurrentQx) >> 1;
+                m_posnDecelQx = m_posnTargetQx - decelDistQx;
+                m_moveState = MS_CRUISE;
+                // Allow to fall through into cruise in case the decel
+                // needs to start immediately
+            }
+            else {
+                break;
+            }
+        // Fall through
+
+        case MS_CRUISE: // Continue at the current velocity
+            m_posnCurrentQx += m_velCurrentQx;
+
+            // Velocity moves don't need to decelerate in the typical way,
+            // just stay cruising
+            if (m_velocityMove) {
+                // If cruising at zero velocity, the move has ended
+                if (!m_velCurrentQx) {
+                    m_moveState = MS_END;
+                }
+                break;
+            }
+            // Check if we reached target decel position or position overflow
+            if (m_posnCurrentQx >= m_posnDecelQx || m_posnCurrentQx <= 0) {
+                // If the decel position is reached, compute the distance
+                // overshoot from where we needed to start ramping.
+                // Dist Over = % of sample time past when to decel
+                //             * vel change during that time / 2
+                uint64_t overshootQx = m_posnCurrentQx - m_posnDecelQx;
+                uint32_t pctSampleOverQ32 =
+                    (overshootQx << 32) / m_velCurrentQx;
+                uint32_t velAdjQx = (static_cast<uint64_t>(pctSampleOverQ32) *
+                                     m_accelCurrentQx) >> 32;
+                // Build in the divide by 2
+                uint32_t posnAdjQx =
+                    (static_cast<uint64_t>(pctSampleOverQ32) * velAdjQx) >> 33;
+
+                m_posnCurrentQx -= posnAdjQx;
+                m_velCurrentQx -= velAdjQx;
+                // Check for done condition: if we overshot target position or
+                // decel overshot zero velocity or position overflow
+                if ((m_posnCurrentQx >= m_posnTargetQx) ||
+                        (m_velCurrentQx <= 0) || (m_posnCurrentQx <= 0)) {
+                    // If done, enforce final position.
+                    m_accelCurrentQx = 0;
+                    m_velCurrentQx = 0;
+                    m_posnCurrentQx = m_posnTargetQx;
+                    m_moveState = MS_END;
+                }
+                else {
+                    m_moveState = MS_DECEL;
+                }
+            }
+            break;
+
+        case MS_DECEL: // Ramp down to stopped
+            // Execute move
+            m_posnCurrentQx += m_velCurrentQx - (m_accelCurrentQx >> 1);
+            m_velCurrentQx -= m_accelCurrentQx;
+
+            // Check for done condition: if we overshot target position or
+            // decel overshot zero velocity or position overflow
+            if ((m_posnCurrentQx >= m_posnTargetQx) || (m_velCurrentQx <= 0) ||
+                    (m_posnCurrentQx <= 0)) {
+                // If done, enforce final position.
+                m_accelCurrentQx = 0;
+                m_velCurrentQx = 0;
+                m_posnCurrentQx = m_posnTargetQx;
+                m_moveState = MS_END;
+            }
+            break;
+
+        case MS_DECEL_VEL: // Velocity move deceleration state
+            // When decreasing velocity, target a new velocity, not a position
+            // During decel, we still need to accumulate the steps that we are
+            // taking.
+            m_posnCurrentQx += m_velCurrentQx - (m_accelCurrentQx >> 1);
+            m_velCurrentQx -= m_accelCurrentQx;
+
+            // Check if we reached target velocity
+            if (m_velCurrentQx <= m_velTargetQx) {
+                // If target velocity reached, compute the distance overshoot
+                // from exceeding the velocity limit.
+                // Dist Over = % of sample time past when the vel was reached
+                //             * vel overshoot / 2
+                uint32_t overshootQx = m_velTargetQx - m_velCurrentQx;
+                uint32_t pctSampleOverQ32 =
+                    ((static_cast<uint64_t>(overshootQx)) << 32) /
+                    m_accelCurrentQx;
+                // Build in the divide by 2
+                uint32_t posnAdjQx =
+                    (static_cast<uint64_t>(pctSampleOverQ32) * overshootQx) >>
+                    33;
+
+                // Velocity may be slightly off of the target velocity due to
+                // discrete sampling. Force velocity to snap to the target
+                m_velCurrentQx = m_velTargetQx;
+                // Adjust position for overshoot.
+                m_posnCurrentQx += posnAdjQx;
+                // If there's no sign change between moves, head to cruise.
+                // Otherwise return to start to begin the new move in the opposite
+                // direction of the first move.
+                if (m_moveDirChange) {
+                    m_moveState = MS_CHANGE_DIR;
+                }
+                else {
+                    // Calculate the decel point
+                    uint64_t decelDistQx = (static_cast<uint64_t>(m_velCurrentQx) *
+                                            m_velCurrentQx / m_accelCurrentQx) >> 1;
+                    m_posnDecelQx = m_posnTargetQx - decelDistQx;
+
+                    m_moveState = MS_CRUISE;
+                }
+            }
+            break;
+        case MS_CHANGE_DIR:
+            // When a direction change occurs, the goal is to slow down
+            // as quickly as possible (accel limit). During this slow
+            // down period, we are moving in the direction that we were
+            // previously and steps are accumulating in that direction.
+            // In order to still meet the position target, we need to
+            // add these (wrong direction) steps to the  user entered
+            // commanded steps.
+
+            // We went past where the command was issued, we have to
+            // now go the original distance plus how far we went slowing
+            if (m_direction == m_dirCommanded) {
+                m_stepsCommanded = m_stepsSent - m_stepsCommanded;
+            }
+            else {
+                m_stepsCommanded += m_stepsSent;
+            }
+            // We are stopped and need to flop directions, so do so.
+            m_dirCommanded = !m_direction;
+            // Zero previous move
+            m_stepsSent = 0;
+            m_posnCurrentQx = m_posnCurrentQx & ~(UINT64_MAX << FRACT_BITS);
+
+            m_moveState = MS_START;
+            m_moveDirChange = false;
+            break;
+
+        case MS_END: // Clean up after the move completes
+        default:
+            m_posnCurrentQx = 0;
+            m_velCurrentQx = 0;
+            m_stepsSent = 0;
+            m_stepsPrevious = 0;
+            m_stepsCommanded = 0;
+            m_moveState = MS_IDLE;
+            m_velocityMove = false;
+            m_limitInfo.LimitRampPos = false;
+            m_limitInfo.LimitRampNeg = false;
+            return;
+    }
+
+    // Compute burst value
+    m_stepsPrevious = (m_posnCurrentQx >> FRACT_BITS) - m_stepsSent;
+
+    // Update accumulated integer position
+    m_stepsSent += m_stepsPrevious;
+
+    // Check move direction and increment absolute position
+    m_posnAbsolute += m_direction ? -m_stepsPrevious : m_stepsPrevious;
+}
+
+/*
+    Default constructor
+*/
+StepGenerator::StepGenerator()
+    : m_stepsPrevious(0),
+      m_stepsPerSampleMax(0),
+      m_moveState(MS_IDLE),
+      m_direction(false),
+      m_lastMoveWasPositional(true),
+	  m_limitInfo(),
+      m_posnAbsolute(0),
+      m_stepsCommanded(0),
+      m_stepsSent(0),
+      m_velocityMove(false),
+      m_moveDirChange(false),
+      m_dirCommanded(false),
+      m_velLimitQx(1),
+      m_altVelLimitQx(0),
+      m_accelLimitQx(2),
+      m_altDecelLimitQx(2),
+      m_posnCurrentQx(0),
+      m_velCurrentQx(0),
+      m_accelCurrentQx(0),
+      m_posnTargetQx(0),
+      m_velTargetQx(0),
+      m_posnDecelQx(0),
+      m_velLimitPendingQx(1),
+      m_altVelLimitPendingQx(0),
+      m_accelLimitPendingQx(2),
+      m_altDecelLimitPendingQx(2) {}
+
+/*
+    This function clears the current move and puts the motor in a
+    move idle state without disabling it or clearing the position.
+
+    This may cause an abrupt stop.
+*/
+void StepGenerator::MoveStopAbrupt() {
+    // Block the interrupt while changing the command
+    __disable_irq();
+    m_posnCurrentQx = 0;
+    m_velCurrentQx = 0;
+    m_stepsSent = 0;
+    m_moveState = MS_IDLE;
+    m_velocityMove = false;
+    m_stepsCommanded = 0;
+    m_stepsPrevious = 0;
+    UpdatePendingMoveLimits();
+    __enable_irq();
+}
+
+/*
+    This function commands a directional move.
+
+    The function will return true if the move was accepted.
+*/
+bool StepGenerator::Move(int32_t dist, MoveTarget moveTarget) {
+
+    // Block the interrupt while changing the command
+    __disable_irq();
+    // Make relative moves be based off of current position during a velocity
+    // move
+    if (m_velocityMove) {
+        m_stepsCommanded = 0;
+        m_stepsSent = 0;
+    }
+    switch (moveTarget) {
+        case MOVE_TARGET_ABSOLUTE:
+            m_stepsCommanded = dist - m_posnAbsolute;
+            break;
+        case MOVE_TARGET_REL_END_POSN:
+        default:
+            // relative end posn
+            // m_stepsCommanded += (newDir ? -dist : dist);
+            // Since the steps scale is relative to start of move to prevent
+            // overflow, the scale shifts by the number of steps taken
+            // So account for this, the current steps should be taken off of the
+            // previous commanded amount, then the new command should be added
+            // The steps send are in the direction of the commanded steps, subtract
+            // that first. Steps taken is always less than commanded, result (+)
+            m_stepsCommanded -= m_stepsSent;
+            // Convert magnitude + direction format to signed int
+            m_stepsCommanded = m_direction ? -m_stepsCommanded : m_stepsCommanded ;
+            // Now stepsCommanded and distance are signed and in the global
+            // direction. Add them
+            m_stepsCommanded += dist;
+            // Steps commanded and dir will be calculated later.
+            break;
+    }
+
+    // Zero out the steps and integer portion of current position to
+    // reduce chance of overflow
+    m_stepsSent = 0;
+
+    // Zero the integer portion of the current position. We want to keep
+    // partial steps so movement is smooth.
+    m_posnCurrentQx = m_posnCurrentQx & ~(UINT64_MAX << FRACT_BITS);
+
+    // Determine the direction of the movements.
+    m_dirCommanded = m_stepsCommanded < 0;
+
+    // Steps commanded now needs to be a positive value.
+    m_stepsCommanded = abs(m_stepsCommanded);
+
+    m_velocityMove = false;
+    UpdatePendingMoveLimits();
+    m_moveState = MS_START;
+
+    __enable_irq();
+    return true;
+}
+
+/*
+    This function commands a velocity move.
+    If there is a current move, it will be overwritten.
+*/
+bool StepGenerator::MoveVelocity(int32_t velocity) {
+    // Block the interrupt while changing the command
+    __disable_irq();
+    m_dirCommanded = (velocity < 0);
+
+    m_velocityMove = true;
+
+    int32_t velAbsolute = abs(velocity);
+    AltVelMax(velAbsolute);
+    UpdatePendingMoveLimits();
+    m_stepsCommanded = INT32_MAX;
+    m_posnCurrentQx &= ~(UINT64_MAX << FRACT_BITS);
+    m_stepsSent = 0;
+
+    m_moveState = MS_START;
+    __enable_irq();
+
+    return true;
+}
+
+void StepGenerator::MoveStopDecel(uint32_t decelMax) {
+    if (decelMax != 0) {
+        EStopDecelMax(decelMax);
+        m_altDecelLimitQx = m_altDecelLimitPendingQx;
+    }
+    __disable_irq();
+    m_accelLimitQx = max(m_altDecelLimitQx, m_accelLimitQx);
+    m_velocityMove = true;
+    m_altVelLimitQx = 0;
+    m_moveState = MS_START;
+    __enable_irq();
+}
+
+/*
+    This function takes the velocity in step pulses/sec
+    and sets VelLimitQx in step pulses/sample time.
+*/
+void StepGenerator::VelMax(uint32_t velMax) {
+    // Convert from step pulses/sec to step pulses/sample
+    int64_t velLim64 =
+        (static_cast<int64_t>(velMax) << FRACT_BITS) / SampleRateHz;
+    // Enforce the max steps per sample time
+    velLim64 =
+        min(velLim64, static_cast<int64_t>(m_stepsPerSampleMax) << FRACT_BITS);
+    // Ensure we didn't overflow 32-bit int
+    velLim64 = min(velLim64, INT32_MAX);
+    // Enforce minimum velocity of 1 step pulse/sample
+    m_velLimitPendingQx = max(velLim64, 1);
+}
+
+/*
+    This function takes the velocity in step pulses/sec
+    and sets AltVelLimitQx in step pulses/sample time.
+*/
+void StepGenerator::AltVelMax(int32_t velMax) {
+    // Convert from step pulses/sec to step pulses/sample
+    int64_t velLim64 =
+        (static_cast<int64_t>(velMax) << FRACT_BITS) / SampleRateHz;
+    // Enforce the max steps per sample time
+    velLim64 =
+        min(velLim64, static_cast<int64_t>(m_stepsPerSampleMax) << FRACT_BITS);
+    // Ensure we didn't overflow 32-bit int
+    m_altVelLimitPendingQx = min(velLim64, INT32_MAX);
+}
+
+int32_t StepGenerator::VelocityRefCommanded() {
+    // Reverse the calculation in AltVelMax to get the velocity in the same
+    // units that the user put in. Add half a decimal for rounding.
+    int32_t velTemp = ((static_cast<int64_t>(m_velCurrentQx) * SampleRateHz +
+                        (1 << (FRACT_BITS - 1))) >> FRACT_BITS);
+    return m_direction ? -velTemp : velTemp;
+}
+
+static int32_t ConvertAccel(uint32_t pulsesPerSecSq) {
+    // Convert from step pulses/sec/sec to step pulses/sample/sample
+    int64_t accelLim64 = ((static_cast<int64_t>(pulsesPerSecSq) << FRACT_BITS) /
+                          (SampleRateHz * SampleRateHz));
+    // Ensure we didn't overflow 32-bit int
+    int32_t accelLim32 = min(accelLim64, INT32_MAX);
+    // Since accel has to be divided by 2 when calculating position increments,
+    // make sure it is even
+    accelLim32 &= ~1L;
+    // Enforce minimum acceleration of 2 step pulses/sample^2
+    if (accelLim32 < 2) {
+        accelLim32 = 2;
+    }
+    return accelLim32;
+}
+
+/*
+    This function takes the acceleration in step pulses/sec^2
+    and sets AccLimitQx in step pulses/sample^2.
+*/
+void StepGenerator::AccelMax(uint32_t accelMax) {
+    // Convert from step pulses/sec/sec to step pulses/sample/sample
+    m_accelLimitPendingQx = ConvertAccel(accelMax);
+}
+
+/*
+    This function takes the acceleration in step pulses/sec^2
+    and sets m_accelLimitQx in step pulses/sample^2 to the higher
+    value of the current move's accel limit or the decelMax given.
+*/
+void StepGenerator::EStopDecelMax(uint32_t decelMax) {
+    // Convert from step pulses/sec/sec to step pulses/sample/sample
+    int32_t decelQx = ConvertAccel(decelMax);
+    m_altDecelLimitPendingQx = max(decelQx, m_accelLimitQx);
+}
+
+/*
+    This function limits the velocity to the maximum that the step output
+    can provide.
+*/
+void StepGenerator::StepsPerSampleMaxSet(uint32_t maxSteps) {
+    MoveStopAbrupt();
+    m_stepsPerSampleMax = maxSteps;
+    // Recalculate maximum velocity limit
+    int64_t velLim64 = static_cast<int64_t>(m_stepsPerSampleMax) << FRACT_BITS;
+    // Ensure we didn't overflow 32-bit int
+    velLim64 = min(velLim64, INT32_MAX);
+    // Enforce minimum velocity of 1 step pulse/sample
+    velLim64 = max(velLim64, 1);
+    // Clip velocity limit if higher than max velocity limit
+    m_velLimitPendingQx = min(velLim64, m_velLimitQx);
+}
+
+ bool StepGenerator::CheckTravelLimits() {
+    if (m_stepsPrevious == 0) {
+        return false;
+    }
+
+    // Determine if we are physically in the hardware limits
+    m_limitInfo.EnterHWLimit = (m_limitInfo.InPosHWLimit || m_limitInfo.InNegHWLimit)
+                            && ((m_limitInfo.InPosHWLimit != m_limitInfo.InPosHWLimitLast)
+                            ||  (m_limitInfo.InNegHWLimit != m_limitInfo.InNegHWLimitLast));
+    m_limitInfo.InPosHWLimitLast = m_limitInfo.InPosHWLimit;
+    m_limitInfo.InNegHWLimitLast = m_limitInfo.InNegHWLimit;
+
+    if (m_limitInfo.EnterHWLimit) {
+
+        if ((!m_direction && m_limitInfo.InPosHWLimit) ||
+            (m_direction && m_limitInfo.InNegHWLimit)) {
+            // Ramp to a stop
+            if (!m_direction) {
+                m_limitInfo.LimitRampPos = true;
+            }
+            else {
+                m_limitInfo.LimitRampNeg = true;
+            }
+            MoveStopDecel();
+        }
+    }
+    return false;
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SysManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SysManager.cpp
new file mode 100644
index 000000000..7247d296b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SysManager.cpp
@@ -0,0 +1,697 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    Supervisory Manager for the ClearCore Board
+
+    This class implements the high level access to the Teknic ClearCore
+    features.
+**/
+
+#include "SysManager.h"
+#include <stddef.h>
+#include <stdio.h>
+#include "AdcManager.h"
+#include "CcioBoardManager.h"
+#include "DigitalIn.h"
+#include "DigitalInAnalogIn.h"
+#include "DigitalInOut.h"
+#include "DigitalInOutAnalogOut.h"
+#include "DigitalInOutHBridge.h"
+#include "DmaManager.h"
+#include "EncoderInput.h"
+#include "EthernetManager.h"
+#include "HardwareMapping.h"
+#include "InputManager.h"
+#include "LedDriver.h"
+#include "MotorDriver.h"
+#include "MotorManager.h"
+#include "NvmManager.h"
+#include "SdCardDriver.h"
+#include "SerialDriver.h"
+#include "SerialUsb.h"
+#include "ShiftRegister.h"
+#include "StatusManager.h"
+#include "SysConnectors.h"
+#include "SysTiming.h"
+#include "SysUtils.h"
+#include "UsbManager.h"
+#include "XBeeDriver.h"
+
+// Variable from linker script
+extern uint32_t __text_start__;
+
+namespace ClearCore {
+
+bool FastSysTick = false;
+
+// Interrupt priority 0(High) - 7(Low)
+#define TONE_INTERRUPT_PRIORITY 2
+#define MAIN_INTERRUPT_PRIORITY 3
+#define SYSTICK_INTERRUPT_PRIORITY 6
+#define EIC_INTERRUPT_PRIORITY 7
+
+// These must match the bootloader!
+#define DOUBLE_TAP_MAGIC            0xf01669efUL
+#define BOOT_DOUBLE_TAP_ADDRESS     (HSRAM_ADDR + HSRAM_SIZE - 4)
+
+// EVSYS channel assignments
+enum _evSysCh {
+    // Motor HLFB event generators for period/pulse-width TC mode
+    EVSYS_M0,
+    EVSYS_M1,
+    EVSYS_M2,
+    EVSYS_M3
+};
+
+extern volatile uint32_t tickCnt;
+extern uint32_t NvmMgrUnlock;
+
+// Create our core system objects
+extern AdcManager &AdcMgr;
+extern DmaManager &DmaMgr;
+extern EthernetManager &EthernetMgr;
+extern CcioBoardManager &CcioMgr;
+EncoderInput EncoderIn;
+extern InputManager &InputMgr;
+extern MotorManager &MotorMgr;
+extern NvmManager &NvmMgr;
+extern StatusManager &StatusMgr;
+extern UsbManager &UsbMgr;
+extern SysTiming &TimingMgr;
+SdCardDriver SdCard;
+ShiftRegister ShiftReg;
+XBeeDriver XBee;
+
+// Special accessor to user-controlled LED
+LedDriver ConnectorLed;
+
+// I/O Connectors
+DigitalInOutAnalogOut ConnectorIO0;
+
+DigitalInOut ConnectorIO1;
+DigitalInOut ConnectorIO2;
+DigitalInOut ConnectorIO3;
+
+// H-Bridge type connectors
+DigitalInOutHBridge ConnectorIO4;
+DigitalInOutHBridge ConnectorIO5;
+
+extern DigitalInOutHBridge *const hBridgeCon[HBRIDGE_CON_CNT] = {
+    &ConnectorIO4, &ConnectorIO5
+};
+
+// Digital input only connectors
+DigitalIn ConnectorDI6;
+DigitalIn ConnectorDI7;
+DigitalIn ConnectorDI8;
+
+DigitalInAnalogIn ConnectorA9;
+DigitalInAnalogIn ConnectorA10;
+DigitalInAnalogIn ConnectorA11;
+DigitalInAnalogIn ConnectorA12;
+
+// ClearPath Motor Connectors
+MotorDriver ConnectorM0;
+MotorDriver ConnectorM1;
+MotorDriver ConnectorM2;
+MotorDriver ConnectorM3;
+
+extern MotorDriver *const MotorConnectors[MOTOR_CON_CNT] = {
+    &ConnectorM0, &ConnectorM1, &ConnectorM2, &ConnectorM3
+};
+
+SerialUsb    ConnectorUsb;
+SerialDriver ConnectorCOM0;
+SerialDriver ConnectorCOM1;
+
+SysManager SysMgr;
+
+// Create an array of "pin" handlers for each of the ClearCore connectors.
+Connector *const Connectors[CLEARCORE_PIN_MAX] = {
+    &ConnectorIO0, &ConnectorIO1, &ConnectorIO2, &ConnectorIO3,
+    &ConnectorIO4, &ConnectorIO5,
+    &ConnectorDI6, &ConnectorDI7, &ConnectorDI8,
+    &ConnectorA9, &ConnectorA10, &ConnectorA11, &ConnectorA12,
+    &ConnectorLed,
+    &ConnectorM0, &ConnectorM1, &ConnectorM2, &ConnectorM3,
+    &ConnectorCOM0, &ConnectorCOM1,
+    &ConnectorUsb
+};
+
+/**
+    Constructor
+**/
+SysManager::SysManager() : m_readyForOperations(false) {
+    XBee = XBeeDriver(&XBee_CTS_IN, &XBee_RTS_OUT, &XBee_Rx_IN, &XBee_Tx_OUT,
+                      PER_SERCOM_ALT);
+    SdCard = SdCardDriver(&MicroSD_MISO, &MicroSD_SS, &MicroSD_SCK,
+                          &MicroSD_MOSI, PER_SERCOM_ALT);
+    ConnectorLed = LedDriver(ShiftRegister::SR_LED_USB_MASK);
+
+    ConnectorIO0 = DigitalInOutAnalogOut(ShiftRegister::SR_LED_IO_0_MASK,
+                                         &IN00n_Aout00n, &OUT00, &Aout00, true);
+    ConnectorIO1 = DigitalInOut(ShiftRegister::SR_LED_IO_1_MASK, &IN01n,
+                                &OUT01, true);
+    ConnectorIO2 = DigitalInOut(ShiftRegister::SR_LED_IO_2_MASK, &IN02n,
+                                &OUT02, true);
+    ConnectorIO3 = DigitalInOut(ShiftRegister::SR_LED_IO_3_MASK, &IN03n,
+                                &OUT03, true);
+
+    ConnectorIO4 = DigitalInOutHBridge(ShiftRegister::SR_LED_IO_4_MASK, &IN04n,
+                                       &OUT04_ENABLE04, &Polarity04_PWM04A,
+                                       &Polarity04S_PWM04B, TCC4_0_IRQn, false);
+    ConnectorIO5 = DigitalInOutHBridge(ShiftRegister::SR_LED_IO_5_MASK, &IN05n,
+                                       &OUT05_ENABLE05, &Polarity05_PWM05A,
+                                       &Polarity05S_PWM05B, TCC3_0_IRQn, false);
+
+    ConnectorDI6 = DigitalIn(ShiftRegister::SR_LED_DI_6_MASK, &IN06n_QuadA);
+    ConnectorDI7 = DigitalIn(ShiftRegister::SR_LED_DI_7_MASK, &IN07n_QuadB);
+    ConnectorDI8 = DigitalIn(ShiftRegister::SR_LED_DI_8_MASK, &IN08n_QuadI);
+
+    ConnectorA9 = DigitalInAnalogIn(ShiftRegister::SR_LED_ADI_09_MASK,
+                                    ShiftRegister::SR_ANAIN_DIGITAL_09_MASK,
+                                    &IN09n_AIN09, AdcManager::ADC_AIN09);
+    ConnectorA10 = DigitalInAnalogIn(ShiftRegister::SR_LED_ADI_10_MASK,
+                                     ShiftRegister::SR_ANAIN_DIGITAL_10_MASK,
+                                     &IN10n_AIN10, AdcManager::ADC_AIN10);
+    ConnectorA11 = DigitalInAnalogIn(ShiftRegister::SR_LED_ADI_11_MASK,
+                                     ShiftRegister::SR_ANAIN_DIGITAL_11_MASK,
+                                     &IN11n_AIN11, AdcManager::ADC_AIN11);
+    ConnectorA12 = DigitalInAnalogIn(ShiftRegister::SR_LED_ADI_12_MASK,
+                                     ShiftRegister::SR_ANAIN_DIGITAL_12_MASK,
+                                     &IN12n_AIN12, AdcManager::ADC_AIN12);
+
+    ConnectorM0 = MotorDriver(ShiftRegister::SR_EN_OUT_0_MASK, &Mtr0_An_SCTx,
+                              &Mtr0_B, &Mtr0_HLFB_SCRx, 4, EVSYS_M0);
+    ConnectorM1 = MotorDriver(ShiftRegister::SR_EN_OUT_1_MASK, &Mtr1_An,
+                              &Mtr1_B, &Mtr1_HLFB, 5, EVSYS_M1);
+    ConnectorM2 = MotorDriver(ShiftRegister::SR_EN_OUT_2_MASK,
+                              &Mtr2_An_Sdrvr2_PWMA, &Mtr2_B_Sdrvr2_PWMB,
+                              &Mtr2_HLFB_Sdrvr2_Trig, 3, EVSYS_M2);
+    ConnectorM3 = MotorDriver(ShiftRegister::SR_EN_OUT_3_MASK,
+                              &Mtr3_An_Sdrvr3_PWMA, &Mtr3_B_Sdrvr3_PWMB,
+                              &Mtr3_HLFB_Sdrvr3_Trig, 0, EVSYS_M3);
+
+    ConnectorCOM0 = SerialDriver(0, ShiftRegister::SR_LED_COM_0_MASK,
+                                 ShiftRegister::SR_UART_SPI_SEL_0_MASK,
+                                 ShiftRegister::SR_UART_TTL_0_MASK,
+                                 &Com0_CTS_MISO, &Com0_RTS_SS, &Com0_RX_SCK,
+                                 &Com0_TX_MOSI, PER_SERCOM_ALT);
+    ConnectorCOM1 = SerialDriver(1, ShiftRegister::SR_LED_COM_1_MASK,
+                                 ShiftRegister::SR_UART_SPI_SEL_1_MASK,
+                                 ShiftRegister::SR_UART_TTL_1_MASK,
+                                 &Com1_CTS_MISO, &Com1_RTS_SS, &Com1_RX_SCK,
+                                 &Com1_TX_MOSI, PER_SERCOM);
+}
+
+/**
+    Initialize the board to power-up state.
+**/
+void SysManager::Initialize() {
+    // Clear and enable the cycle counter
+    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    DWT->CYCCNT = 0;
+    DWT->CTRL = DWT_CTRL_CYCCNTENA_Msk;
+
+    InitClocks();
+
+    // Enable brownout detection on the 3.3V rail. The default fuse value is 1.7
+    // Set brownout detection to ~2.5V. Default from factory is 1.7V,
+    // It appears that NVM can work to as low as 1.7V
+    SUPC->BOD33.bit.ENABLE = 0;
+    SUPC->BOD33.bit.LEVEL = 167;  // Brown out voltage = 1.5V + LEVEL * 6mV.
+    // Reset
+    // If desired, an interrupt can be triggered instead of reset. Useful if
+    // sensitive actions need to be completed at the last moment.
+    SUPC->BOD33.bit.ACTION = SUPC_BOD33_ACTION_RESET_Val;//SUPC_BOD33_ACTION_NONE_Val;
+    // Hysteresis voltage (4 bits). HYST*6mV
+    SUPC->BOD33.bit.HYST = 0x7;
+    SUPC->BOD33.bit.ENABLE = 1; // enable brown-out detection
+
+    // Reset and initialize the HBridge
+    StatusMgr.HBridgeState(true);
+    Delay_ms(1);
+    StatusMgr.HBridgeState(false);
+
+    // Set the output direction for the OutFault_04or05
+    DATA_DIRECTION_INPUT(OutFault_04or05.gpioPort,
+                         1UL << OutFault_04or05.gpioPin);
+
+    PIN_CONFIGURATION(OutFault_04or05.gpioPort, OutFault_04or05.gpioPin,
+                      PORT_PINCFG_INEN);
+
+    InputMgr.Initialize();
+
+    for (int32_t i = 0; i < CLEARCORE_PIN_MAX; i++) {
+        Connectors[i]->Initialize(static_cast<ClearCorePins>(i));
+    }
+
+    DmaMgr.Initialize();
+    MotorMgr.Initialize();
+    ShiftReg.Initialize();
+    AdcMgr.Initialize();
+    CcioMgr.Initialize();
+    UsbMgr.Initialize();
+    EncoderIn.Initialize();
+
+    // Configure external interrupt controller
+    SET_CLOCK_SOURCE(EIC_GCLK_ID, 0);
+
+    ShiftReg.LedPattern(ShiftRegister::SR_UNDERGLOW_MASK,
+                        ShiftRegister::LED_BLINK_BREATHING, true);
+
+    // Enable clock EIC for I/O interrupts
+    CLOCK_ENABLE(APBAMASK, EIC_);
+
+    // Enable External Interrupt Controllers 0-15
+    // EIC_0_IRQn = 12, ..., EIC_15_IRQn = 27
+    for (IRQn_Type irq = EIC_0_IRQn; irq <= EIC_15_IRQn;
+            irq = static_cast<IRQn_Type>(static_cast<uint8_t>(irq) + 1)) {
+        NVIC_EnableIRQ(irq);
+        NVIC_SetPriority(irq, EIC_INTERRUPT_PRIORITY);
+    }
+
+    NVIC_EnableIRQ(TCC0_0_IRQn); // Enable sample rate interrupt
+    NVIC_SetPriority(TCC0_0_IRQn, MAIN_INTERRUPT_PRIORITY); // Set priority
+
+    NVIC_EnableIRQ(GMAC_IRQn);
+    NVIC_SetPriority(GMAC_IRQn, MAIN_INTERRUPT_PRIORITY);
+
+    NVIC_EnableIRQ(TCC4_0_IRQn); // Enable IO4 tone interrupt
+    NVIC_EnableIRQ(TCC3_0_IRQn); // Enable IO5 tone interrupt
+    NVIC_SetPriority(TCC4_0_IRQn, TONE_INTERRUPT_PRIORITY); // Set priority
+    NVIC_SetPriority(TCC3_0_IRQn, TONE_INTERRUPT_PRIORITY); // Set priority
+
+    // Set SysTick to 1ms interval
+    if (TimingMgr.SysTickPeriodMicroSec(1000)) {
+        // Capture error
+        while (1) {
+            continue;
+        }
+    }
+    // Set priority for SysTick interrupt (2nd lowest).
+    NVIC_SetPriority(SysTick_IRQn, SYSTICK_INTERRUPT_PRIORITY);
+
+    // Run power-on tests and detect faults if any.
+    StatusMgr.Initialize(ShiftRegister::SR_UNDERGLOW_MASK);
+
+    // Ethernet PHY requires 300us + 10ms minimum for a cold startup.
+    while (Microseconds() < 10300) {
+        continue;
+    }
+
+    EthernetMgr.Initialize();
+
+    m_readyForOperations = true;
+}
+
+/**
+    Update systems at the sample rate
+**/
+void SysManager::UpdateFastImpl() {
+    CcioMgr.Refresh();
+    AdcMgr.Update();
+    StatusMgr.Refresh();
+    UsbMgr.Refresh();
+    InputMgr.UpdateBegin();
+
+    if (SysMgr.Ready()) {
+        for (uint8_t i = 0; i < CLEARCORE_PIN_MAX; i++) {
+            Connectors[i]->Refresh();
+        }
+    }
+
+    InputMgr.UpdateEnd();
+    EncoderIn.Update();
+
+    // Update subsystems in the background
+    ShiftReg.Update();
+    TimingMgr.Update();
+
+    tickCnt++;
+}
+
+/**
+    Update systems at SysTick rate.
+**/
+void SysManager::UpdateSlowImpl() {
+    if (!m_readyForOperations) {
+        return;
+    }
+
+    // CCIO-8 Auto-Rediscover
+    CcioMgr.RefreshSlow();
+
+    for (uint8_t iMotor = 0; iMotor < MOTOR_CON_CNT; iMotor++) {
+        MotorConnectors[iMotor]->RefreshSlow();
+    }
+}
+
+Connector *SysManager::ConnectorByIndex(ClearCorePins theConnector) {
+    if (theConnector < CLEARCORE_PIN_MAX) {
+        return Connectors[theConnector];
+    }
+    else {
+        return CcioMgr.PinByIndex(theConnector);
+    }
+}
+
+void SysManager::InitClocks() {
+    // Set up TCC0 which will be used to generate the sample time interrupt
+    // and by the motors in S&D/PWM mode to send bursts of steps or PWM duty.
+    SET_CLOCK_SOURCE(TCC0_GCLK_ID, 1);
+    CLOCK_ENABLE(APBBMASK, TCC0_);
+
+    // Disable TCC0
+    TCC0->CTRLA.bit.ENABLE = 0;
+    SYNCBUSY_WAIT(TCC0, TCC_SYNCBUSY_ENABLE);
+
+    // Initialize counter value to zero
+    TCC0->COUNT.reg = 0;
+
+    // Use double buffering
+    TCC0->CTRLBCLR.bit.LUPD = 1;
+
+    // Set TCC0 as normal PWM, invert the polarity of the outputs
+    TCC0->WAVE.reg |= TCC_WAVE_WAVEGEN_NPWM | TCC_WAVE_POL_Msk;
+    // Set the initial value
+    for (int8_t iChannel = 0; iChannel < 6; iChannel++) {
+        TCC0->CC[iChannel].reg = 0;
+    }
+    // Interrupt every period
+    TCC0->INTENSET.bit.OVF = 1;
+
+    // Setup TCC1 which will be used by motors using PWM input on InA
+    SET_CLOCK_SOURCE(TCC1_GCLK_ID, 1);
+    CLOCK_ENABLE(APBBMASK, TCC1_);
+
+    // Disable TCC1
+    TCC1->CTRLA.bit.ENABLE = 0;
+    SYNCBUSY_WAIT(TCC1, TCC_SYNCBUSY_ENABLE);
+
+    // Initialize counter value to zero
+    TCC1->COUNT.reg = 0;
+
+    // Use double buffering
+    TCC1->CTRLBCLR.bit.LUPD = 1;
+
+    // Set TCC1 as normal PWM, invert the polarity of the outputs
+    TCC1->WAVE.reg |= TCC_WAVE_WAVEGEN_NPWM | TCC_WAVE_POL_Msk;
+
+    // Set the initial value
+    for (int8_t iChannel = 0; iChannel < 6; iChannel++) {
+        TCC1->CC[iChannel].reg = 0;
+    }
+
+    // Initialize Timer/Counters
+    SET_CLOCK_SOURCE(TC1_GCLK_ID, 6);
+    CLOCK_ENABLE(APBAMASK, TC1_); // Enable TC1 bus clock
+
+    SET_CLOCK_SOURCE(TC2_GCLK_ID, 6);
+    CLOCK_ENABLE(APBBMASK, TC2_); // Enable TC2 bus clock
+
+    SET_CLOCK_SOURCE(TC5_GCLK_ID, 6);
+    CLOCK_ENABLE(APBCMASK, TC5_); // Enable TC5 bus clock
+
+    GCLK->PCHCTRL[TC6_GCLK_ID].reg =
+        GCLK_PCHCTRL_GEN_GCLK6 | GCLK_PCHCTRL_CHEN;
+    CLOCK_ENABLE(APBDMASK, TC6_); // Enable TC6 bus clock
+
+    // TCC3 used by IO5 for H-bridge PWM generation
+    SET_CLOCK_SOURCE(TCC3_GCLK_ID, 0);
+    CLOCK_ENABLE(APBCMASK, TCC3_);
+
+    // TCC4 used by IO4 for H-bridge PWM generation
+    SET_CLOCK_SOURCE(TCC4_GCLK_ID, 0);
+    CLOCK_ENABLE(APBDMASK, TCC4_);
+
+    Tc *TCs[] = {TC1, TC2, TC6};
+    for (int8_t tcIndex = 0; tcIndex < 3; tcIndex++) {
+        Tc *tc = TCs[tcIndex];
+        TcCount8 *tcCount = &tc->COUNT8;
+
+        // Disable TCx
+        tcCount->CTRLA.bit.ENABLE = 0;
+        SYNCBUSY_WAIT(tcCount, TC_SYNCBUSY_ENABLE);
+
+        tcCount->CTRLBCLR.bit.LUPD = 1; // Double buffering
+        tcCount->CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT8_Val;
+        // Make 500Hz carrier from GCLK
+        tcCount->CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV16_Val;
+        tcCount->WAVE.reg = TC_WAVE_WAVEGEN_NPWM;
+        tcCount->DRVCTRL.reg = TC_DRVCTRL_INVEN_Msk;
+
+        tcCount->PERBUF.reg = 254;
+        tcCount->CCBUF[0].reg = 0;
+        tcCount->CCBUF[1].reg = 0;
+
+        tcCount->COUNT.reg = 0;
+
+        // Enable TCx
+        tcCount->CTRLA.bit.ENABLE = 1;
+        SYNCBUSY_WAIT(tcCount, TC_SYNCBUSY_ENABLE);
+    }
+}
+
+void SysManager::ResetBoard(ResetModes mode) {
+    __disable_irq();
+
+    uint32_t *addr = (uint32_t *)BOOT_DOUBLE_TAP_ADDRESS;
+    if (mode == RESET_TO_BOOTLOADER) {
+        *addr = DOUBLE_TAP_MAGIC;
+    }
+    else {
+        *addr = 0;
+    }
+
+    // Reset the device
+    NVIC_SystemReset();
+
+    while (true) {
+        continue;
+    }
+}
+
+void SysManager::SysTickUpdate() {
+    if (!FastSysTick) {
+        SysMgr.UpdateSlowImpl();
+    }
+}
+
+#define ACK_FAST_UPDATE_INT TCC0->INTFLAG.reg = TCC_INTFLAG_MASK
+
+void SysManager::FastUpdate() {
+    ACK_FAST_UPDATE_INT;
+    TimingMgr.IsrStart();
+    SysMgr.UpdateFastImpl();
+    if (FastSysTick) {
+        SysMgr.UpdateSlowImpl();
+    }
+
+    TimingMgr.IsrEnd();
+}
+
+} // ClearCore namespace
+
+
+// =============================================================================
+// =========================== Connector ISR Handlers ==========================
+// =============================================================================
+
+extern "C" void GMAC_Handler(void) {
+    ClearCore::EthernetMgr.IrqHandlerGmac();
+}
+
+extern "C" void SERCOM0_0_Handler(void) {
+    ClearCore::ConnectorCOM1.IrqHandlerTx();
+}
+extern "C" void SERCOM0_2_Handler(void) {
+    ClearCore::ConnectorCOM1.IrqHandlerRx();
+}
+extern "C" void SERCOM0_3_Handler(void) {
+    ClearCore::ConnectorCOM1.IrqHandlerException();
+}
+
+extern "C" void SERCOM2_0_Handler(void) {
+    ClearCore::XBee.IrqHandlerTx();
+}
+extern "C" void SERCOM2_2_Handler(void) {
+    ClearCore::XBee.IrqHandlerRx();
+}
+extern "C" void SERCOM2_3_Handler(void) {
+    ClearCore::XBee.IrqHandlerException();
+}
+
+extern "C" void SERCOM7_0_Handler(void) {
+    ClearCore::ConnectorCOM0.IrqHandlerTx();
+}
+extern "C" void SERCOM7_2_Handler(void) {
+    ClearCore::ConnectorCOM0.IrqHandlerRx();
+}
+extern "C" void SERCOM7_3_Handler(void) {
+    ClearCore::ConnectorCOM0.IrqHandlerException();
+}
+
+extern "C" void EIC_0_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(0);
+}
+
+extern "C" void EIC_1_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(1);
+}
+
+extern "C" void EIC_2_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(2);
+}
+
+extern "C" void EIC_3_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(3);
+}
+
+extern "C" void EIC_4_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(4);
+}
+
+extern "C" void EIC_5_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(5);
+}
+
+extern "C" void EIC_6_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(6);
+}
+
+extern "C" void EIC_7_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(7);
+}
+
+extern "C" void EIC_8_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(8);
+}
+
+extern "C" void EIC_9_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(9);
+}
+
+extern "C" void EIC_10_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(10);
+}
+
+extern "C" void EIC_11_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(11);
+}
+
+extern "C" void EIC_12_Handler(void) {
+    ClearCore::EthernetMgr.IrqHandlerPhy();
+}
+
+extern "C" void EIC_13_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(13);
+}
+
+extern "C" void EIC_14_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(14);
+}
+
+extern "C" void EIC_15_Handler(void) {
+    ClearCore::InputMgr.EIC_Handler(15);
+}
+
+extern "C" void TCC3_0_Handler(void) {
+    TCC3->INTFLAG.reg = TCC_INTFLAG_MASK;
+    ClearCore::ConnectorIO5.ToneUpdate();
+}
+extern "C" void TCC4_0_Handler(void) {
+    TCC4->INTFLAG.reg = TCC_INTFLAG_MASK;
+    ClearCore::ConnectorIO4.ToneUpdate();
+}
+
+extern "C" void SysTick_Handler(void) {
+    ClearCore::SysMgr.SysTickUpdate();
+}
+/**
+    Interrupt to handle ClearCore background tasks
+**/
+extern "C" void TCC0_0_Handler(void) {
+    ClearCore::SysMgr.FastUpdate();
+}
+
+extern "C" void InitSysManager() {
+    // Start the ClearCore board manager
+    ClearCore::SysMgr.Initialize();
+}
+
+///////////////////////////////////////////////////////////////////
+//                    Startup Code                              //
+/////////////////////////////////////////////////////////////////
+
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+extern "C" void __libc_init_array(void);
+
+extern int main(void);
+
+/**
+    This is called on processor reset to initialize the device and call main().
+*/
+void Reset_Handler(void) {
+    uint32_t *pSrc, *pDest;
+
+    // Initialize the initialized data section
+    pSrc = &__etext;
+    pDest = &__data_start__;
+
+    if ((&__data_start__ != &__data_end__) && (pSrc != pDest)) {
+        for (; pDest < &__data_end__; pDest++, pSrc++) {
+            *pDest = *pSrc;
+        }
+    }
+
+    // Clear the zero section
+    if (&__bss_start__ != &__bss_end__) {
+        for (pDest = &__bss_start__; pDest < &__bss_end__; pDest++) {
+            *pDest = 0ul;
+        }
+    }
+
+    SystemInit();
+
+    /* Initialize the C library */
+    __libc_init_array();
+
+    ClearCore::SysMgr.Initialize();
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+    // ISO C++ forbids hijacking main(), but we can't avoid it
+    // in this application.
+    main();
+#pragma GCC diagnostic pop
+
+    while (1) {
+        continue;
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SysTiming.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SysTiming.cpp
new file mode 100644
index 000000000..024af9e35
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/SysTiming.cpp
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    ClearCore timing profiling utility functions
+**/
+
+#include "SysTiming.h"
+#include <sam.h>
+
+namespace ClearCore {
+
+// Make the interrupt rate visible to everyone
+extern const uint16_t SampleRateHz;
+extern bool FastSysTick;
+volatile uint32_t tickCnt = 0;
+
+SysTiming &TimingMgr = SysTiming::Instance();
+
+SysTiming::SysTiming() :
+    m_isrStartCycle(0),
+    m_isrMinCycles(UINT32_MAX),
+    m_isrMaxCycles(0),
+    m_isrLastCycles(0),
+    m_msTickCnt(0),
+    m_fractMsTick(MS_TO_SAMPLES),
+    m_lastIsrStartCnt(0),
+    m_microAdj(0),
+    m_microAdjHigh(0),
+    m_microAdjLow(0),
+    m_microAdjHighRemainder(0),
+    m_microAdjLowRemainder(0) {}
+
+
+SysTiming &SysTiming::Instance() {
+    static SysTiming *instance = new SysTiming();
+    return *instance;
+}
+
+void SysTiming::IsrStart() {
+    m_isrStartCycle = DWT->CYCCNT;
+}
+
+void SysTiming::IsrEnd() {
+    m_isrLastCycles = DWT->CYCCNT - m_isrStartCycle;
+    if (m_isrMinCycles > m_isrLastCycles) {
+        m_isrMinCycles = m_isrLastCycles;
+    }
+    if (m_isrMaxCycles < m_isrLastCycles) {
+        m_isrMaxCycles = m_isrLastCycles;
+    }
+}
+
+void SysTiming::GetIsrLoading(uint32_t &minSlot, uint32_t &maxSlot) {
+    minSlot = m_isrMinCycles;
+    m_isrMinCycles = m_isrLastCycles;
+    maxSlot = m_isrMaxCycles;
+    m_isrMaxCycles = m_isrLastCycles;
+}
+
+uint32_t SysTiming::Microseconds(void) {
+    // Microseconds = CPU cycles / CYCLES_PER_MICROSECOND
+    // Since the cycle counter wraps before Microseconds reaches UINT32_MAX
+    // keep track of when the cycle counter wraps and adjust accordingly
+    uint32_t cycleCounter = DWT->CYCCNT;
+    if (cycleCounter > UINT32_MAX / 2) {
+        return ((cycleCounter - m_microAdjHighRemainder) /
+                CYCLES_PER_MICROSECOND) + m_microAdjHigh;
+    }
+    else {
+        return ((cycleCounter + m_microAdjLowRemainder) /
+                CYCLES_PER_MICROSECOND) + m_microAdjLow;
+    }
+}
+
+void SysTiming::Update() {
+    // Detaching a debugger can clear CoreDebug_DEMCR_TRCENA_Msk
+    // so make sure it stays set to keep the cycle counter enabled
+    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+
+    // Update the millisecond tick counter
+    if (!--m_fractMsTick) {
+        m_msTickCnt++;
+        m_fractMsTick = MS_TO_SAMPLES;
+    }
+
+    // Since the cycleCounter wraps at 2^32 and we have to divide cycleCounter
+    // by CYCLES_PER_MICROSECOND to get microseconds, the microsecond
+    // calculation would wrap before we get to the desired 2^32 wrap point.
+    // To account for this we need to keep a counter of how many times we hit
+    // the wrap point to effectively extend the number of bits in the
+    // cycleCounter and control the wrap point properly.
+    // Precalculate adjustment values at UINT32_MAX/4 and UINT32_MAX*3/4
+    // by timing when the adjustments are calculated and used, we can safely
+    // modify the values when they are not in use (~9 sec margin).
+    if (((m_isrStartCycle ^ m_lastIsrStartCnt) & 0xc0000000) == 0x40000000) {
+        // At UINT32_MAX*3/4, prepare for the upcoming wrap point
+        if (m_isrStartCycle & 0x80000000) {
+            // Increment the wrap counter and set the adjustment to be used
+            // when the cycle counter is < UINT32_MAX/2
+            uint64_t cycCnt64 = (uint64_t)(++m_microAdj) << 32;
+            m_microAdjLow = cycCnt64 / CYCLES_PER_MICROSECOND;
+            // Are there any remainder bits to be added?
+            if (m_microAdjLow) {
+                m_microAdjLowRemainder =
+                    cycCnt64 - (m_microAdjLow * CYCLES_PER_MICROSECOND);
+            }
+            // If this adjustment value does not modify the microsecond count
+            // it is safe to reset the wrap counter and remainder to zero
+            else {
+                m_microAdj = 0;
+                m_microAdjLowRemainder = 0;
+            }
+        }
+        // At UINT32_MAX/4, set the adjustment to be used when the
+        // cycle counter is > UINT32_MAX/2
+        else {
+            m_microAdjHigh = m_microAdjLow + 1;
+            m_microAdjHighRemainder =
+                CYCLES_PER_MICROSECOND - m_microAdjLowRemainder;
+        }
+    }
+    m_lastIsrStartCnt = m_isrStartCycle;
+}
+
+void SysTiming::ResetMilliseconds() {
+    m_msTickCnt = 0;
+    m_fractMsTick = MS_TO_SAMPLES;
+}
+
+void SysTiming::ResetMicroseconds() {
+    m_microAdj = 0;
+    m_microAdjHigh = 0;
+    m_microAdjLow = 0;
+    m_microAdjHighRemainder = 0;
+    m_microAdjLowRemainder = 0;
+    m_lastIsrStartCnt -= DWT->CYCCNT;
+    DWT->CYCCNT = 0;
+}
+
+bool SysTiming::SysTickPeriodMicroSec(uint32_t microSeconds) {
+    // If the SysTick is faster than the sample rate set a
+    // flag to do the "slow update" within the sample interrupt
+    FastSysTick = microSeconds < SAMPLE_PERIOD_MICROSECONDS;
+    return SysTick_Config(microSeconds * CYCLES_PER_MICROSECOND);
+}
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint32_t Milliseconds(void) {
+    return ClearCore::TimingMgr.Milliseconds();
+}
+
+
+uint32_t Microseconds(void) {
+    return ClearCore::TimingMgr.Microseconds();
+}
+
+void Delay_cycles(uint64_t cycles) {
+    // Get a snapshot of the cycle counter as we enter the delay function
+    uint32_t cyclesLast = DWT->CYCCNT;
+
+    // If we do not need to delay, bail out
+    if (cycles == 0) {
+        return;
+    }
+
+    uint64_t cyclesRemaining = cycles;
+    uint32_t cyclesNow = DWT->CYCCNT;
+
+    while (cyclesRemaining > cyclesNow - cyclesLast) {
+        cyclesRemaining -= (cyclesNow - cyclesLast);
+        cyclesLast = cyclesNow;
+        cyclesNow = DWT->CYCCNT;
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/UsbManager.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/UsbManager.cpp
new file mode 100644
index 000000000..d17764742
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/UsbManager.cpp
@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "UsbManager.h"
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <sam.h>
+#include <component/usb.h>
+#include <component/mclk.h>
+#include "HardwareMapping.h"
+#include "ShiftRegister.h"
+#include "SysManager.h"
+#include "SysUtils.h"
+#include "SysTiming.h"
+#include "sam.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "cdcdf_acm.h"
+#include "cdcdf_acm_desc.h"
+#include "hal_usb_device.h"
+#ifdef __cplusplus
+}
+#endif
+
+#define USB_INTERRUPT_PRIORITY    4
+
+namespace ClearCore {
+
+#define PA24 GPIO(GPIO_PORTA, 24)
+#define PA25 GPIO(GPIO_PORTA, 25)
+
+extern SysManager SysMgr;
+UsbManager &UsbMgr = UsbManager::Instance();
+
+#if CONF_USBD_HS_SP
+static uint8_t single_desc_bytes[] = {
+    // Device descriptors and Configuration descriptors list.
+    CDCD_ACM_HS_DESCES_LS_FS
+};
+static uint8_t single_desc_bytes_hs[] = {
+    // Device descriptors and Configuration descriptors list.
+    CDCD_ACM_HS_DESCES_HS
+};
+#define CDCD_ECHO_BUF_SIZ CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ_HS
+#else
+static uint8_t single_desc_bytes[] = {
+    // Device descriptors and Configuration descriptors list.
+    CDCD_ACM_DESCES_LS_FS
+};
+#define CDCD_ECHO_BUF_SIZ CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ
+#endif
+
+static struct usbd_descriptors single_desc[]
+    = {{single_desc_bytes, single_desc_bytes + sizeof(single_desc_bytes)}
+#if CONF_USBD_HS_SP
+    ,
+    {
+        single_desc_bytes_hs,
+        single_desc_bytes_hs + sizeof(single_desc_bytes_hs)
+    }
+#endif
+};
+
+// Ctrl endpoint buffer
+static uint8_t ctrl_buffer[64];
+
+static void USB_DEVICE_INSTANCE_PORT_init(void);
+
+int writeNum(char *buf, uint32_t n, bool full) {
+    int i = 0;
+    int sh = 28;
+    while (sh >= 0) {
+        int d = (n >> sh) & 0xf;
+        if (full || d || sh == 0 || i) {
+            buf[i++] = d > 9 ? 'A' + d - 10 : '0' + d;
+        }
+        sh -= 4;
+    }
+    return i;
+}
+
+static void load_serial_number() {
+    // Overwrite the serial number descriptor in memory (16-bit unicode)
+    uint16_t *serNumDescPtr = (uint16_t *)usb_find_str_desc(single_desc_bytes,
+                              single_desc_bytes + sizeof(single_desc_bytes),
+                              CONF_USB_CDCD_ACM_ISERIALNUM);
+    if (!serNumDescPtr) {
+        // Descriptor does not exist, bail out
+        return;
+    }
+    // Serial numbers are derived from four 32-bit words.
+#define SERIAL_NUMBER_LENGTH (4 * 8)
+    // serial_number will be filled in when needed.
+    char serial_number[SERIAL_NUMBER_LENGTH];
+
+    // These are locations that taken together make up a unique serial number.
+    uint32_t *addresses[4] = {(uint32_t *) 0x008061FC, (uint32_t *) 0x00806010,
+                              (uint32_t *) 0x00806014, (uint32_t *) 0x00806018
+                             };
+    uint32_t serial_number_idx = 0;
+    for (int i = 0; i < 4; i++) {
+        serial_number_idx += writeNum(&(serial_number[serial_number_idx]),
+                                      *(addresses[i]), true);
+    }
+
+    // Skip over the length and type bytes
+    serNumDescPtr++;
+    for (int i = 0; i < SERIAL_NUMBER_LENGTH; i++) {
+        *serNumDescPtr++ = serial_number[i];
+    }
+}
+
+/**
+    CDC ACM Init
+**/
+void UsbManager::cdc_device_acm_init(void) {
+    // Usb stack init
+    usbdc_init(ctrl_buffer);
+
+    // usbdc_register_funcion inside
+    cdcdf_acm_init();
+
+    usbdc_start(single_desc);
+    usbdc_attach();
+}
+
+void USB_DEVICE_INSTANCE_PORT_init(void) {
+    gpio_set_pin_direction(PA24,
+                           // <y> Pin direction
+                           // <id> pad_direction
+                           // <GPIO_DIRECTION_OFF"> Off
+                           // <GPIO_DIRECTION_IN"> In
+                           // <GPIO_DIRECTION_OUT"> Out
+                           GPIO_DIRECTION_OUT);
+
+    gpio_set_pin_level(PA24,
+                       // <y> Initial level
+                       // <id> pad_initial_level
+                       // <false"> Low
+                       // <true"> High
+                       false);
+
+    gpio_set_pin_pull_mode(PA24,
+                           // <y> Pull configuration
+                           // <id> pad_pull_config
+                           // <GPIO_PULL_OFF"> Off
+                           // <GPIO_PULL_UP"> Pull-up
+                           // <GPIO_PULL_DOWN"> Pull-down
+                           GPIO_PULL_OFF);
+
+    gpio_set_pin_function(PA24,
+                          // <y> Pin function
+                          // <id> pad_function
+                          // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+                          // <PINMUX_PA24H_USB_DM"> Auto
+                          // <GPIO_PIN_FUNCTION_OFF"> Off
+                          // <GPIO_PIN_FUNCTION_A"> A
+                          // <GPIO_PIN_FUNCTION_B"> B
+                          // <GPIO_PIN_FUNCTION_C"> C
+                          // <GPIO_PIN_FUNCTION_D"> D
+                          // <GPIO_PIN_FUNCTION_E"> E
+                          // <GPIO_PIN_FUNCTION_F"> F
+                          // <GPIO_PIN_FUNCTION_G"> G
+                          // <GPIO_PIN_FUNCTION_H"> H
+                          // <GPIO_PIN_FUNCTION_I"> I
+                          // <GPIO_PIN_FUNCTION_J"> J
+                          // <GPIO_PIN_FUNCTION_K"> K
+                          // <GPIO_PIN_FUNCTION_L"> L
+                          // <GPIO_PIN_FUNCTION_M"> M
+                          // <GPIO_PIN_FUNCTION_N"> N
+                          PINMUX_PA24H_USB_DM);
+
+    gpio_set_pin_direction(PA25,
+                           // <y> Pin direction
+                           // <id> pad_direction
+                           // <GPIO_DIRECTION_OFF"> Off
+                           // <GPIO_DIRECTION_IN"> In
+                           // <GPIO_DIRECTION_OUT"> Out
+                           GPIO_DIRECTION_OUT);
+
+    gpio_set_pin_level(PA25,
+                       // <y> Initial level
+                       // <id> pad_initial_level
+                       // <false"> Low
+                       // <true"> High
+                       false);
+
+    gpio_set_pin_pull_mode(PA25,
+                           // <y> Pull configuration
+                           // <id> pad_pull_config
+                           // <GPIO_PULL_OFF"> Off
+                           // <GPIO_PULL_UP"> Pull-up
+                           // <GPIO_PULL_DOWN"> Pull-down
+                           GPIO_PULL_OFF);
+
+    gpio_set_pin_function(PA25,
+                          // <y> Pin function
+                          // <id> pad_function
+                          // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function
+                          // <PINMUX_PA25H_USB_DP"> Auto
+                          // <GPIO_PIN_FUNCTION_OFF"> Off
+                          // <GPIO_PIN_FUNCTION_A"> A
+                          // <GPIO_PIN_FUNCTION_B"> B
+                          // <GPIO_PIN_FUNCTION_C"> C
+                          // <GPIO_PIN_FUNCTION_D"> D
+                          // <GPIO_PIN_FUNCTION_E"> E
+                          // <GPIO_PIN_FUNCTION_F"> F
+                          // <GPIO_PIN_FUNCTION_G"> G
+                          // <GPIO_PIN_FUNCTION_H"> H
+                          // <GPIO_PIN_FUNCTION_I"> I
+                          // <GPIO_PIN_FUNCTION_J"> J
+                          // <GPIO_PIN_FUNCTION_K"> K
+                          // <GPIO_PIN_FUNCTION_L"> L
+                          // <GPIO_PIN_FUNCTION_M"> M
+                          // <GPIO_PIN_FUNCTION_N"> N
+                          PINMUX_PA25H_USB_DP);
+}
+
+UsbManager &UsbManager::Instance() {
+    static UsbManager *instance = new UsbManager();
+    return *instance;
+}
+
+UsbManager::UsbManager() :
+    m_inHead(0),
+    m_inTail(0),
+    m_outHead(0),
+    m_outTail(0),
+    m_sendActive(false),
+    m_readActive(false),
+    m_readBufPtr(m_usbReadBuf),
+    m_readBufAvail(0),
+    m_portOpen(false) {
+    m_lineState.value = 0;
+    cdcdf_acm_register_callback(CDCDF_ACM_CB_STATE_C,
+                                (FUNC_PTR)CBLineStateChanged);
+}
+
+bool UsbManager::Initialize() {
+    // Enable 48MHz clock to USB module from GCLK4
+    SET_CLOCK_SOURCE(USB_GCLK_ID, 4);
+    CLOCK_ENABLE(AHBMASK, USB_);
+    CLOCK_ENABLE(APBBMASK, USB_);
+
+    load_serial_number();
+
+    NVIC_SetPriority(USB_0_IRQn, USB_INTERRUPT_PRIORITY);
+    NVIC_SetPriority(USB_1_IRQn, USB_INTERRUPT_PRIORITY);
+    NVIC_SetPriority(USB_2_IRQn, USB_INTERRUPT_PRIORITY);
+    NVIC_SetPriority(USB_3_IRQn, USB_INTERRUPT_PRIORITY);
+
+    USB_DEVICE_INSTANCE_PORT_init();
+
+    cdc_device_acm_init();
+
+    return true;
+}
+
+bool UsbManager::Speed(uint32_t bitsPerSecond) {
+    // Speed is not set via this API for USB serial ports
+    (void)bitsPerSecond;
+    return true;
+}
+
+uint32_t UsbManager::Speed() {
+    return cdcdf_acm_get_line_coding()->dwDTERate;
+}
+
+/**
+    Sets the line break bit in the line state, then notifies the Host.
+
+    Currently not used, but it provides an example of how to notify the Host
+    that something has happened. Most Hosts ignore most notifications, but
+    if needed, this should be the proper way to send a notification.
+**/
+
+/**
+    Callback invoked when Line State Change
+**/
+bool UsbManager::CBLineStateChanged(usb_cdc_control_signal_t state) {
+    UsbMgr.m_lineState = state;
+    if (state.rs232.DTR) {
+        // Callbacks must be registered after endpoint allocation
+        cdcdf_acm_register_callback(CDCDF_ACM_CB_READ, (FUNC_PTR)RxComplete);
+        cdcdf_acm_register_callback(CDCDF_ACM_CB_WRITE, (FUNC_PTR)TxComplete);
+        // Start Rx
+        cdcdf_acm_read(UsbMgr.m_usbReadBuf, sizeof(UsbMgr.m_usbReadBuf));
+    }
+    else {
+        // Callbacks must be registered after endpoint allocation
+        cdcdf_acm_register_callback(CDCDF_ACM_CB_READ, (FUNC_PTR)NULL);
+        cdcdf_acm_register_callback(CDCDF_ACM_CB_WRITE, (FUNC_PTR)NULL);
+        // Stop Rx/Tx
+        cdcdf_acm_stop_xfer();
+        if (cdcdf_acm_get_line_coding()->dwDTERate == 1200) {
+            SysMgr.ResetBoard(SysManager::RESET_TO_BOOTLOADER);
+        }
+    }
+
+    // No error
+    return false;
+}
+
+bool UsbManager::PortIsOpen() {
+    return (bool) * this && m_portOpen;
+}
+
+void UsbManager::PortOpen() {
+    if (m_portOpen) {
+        return;
+    }
+
+    m_portOpen = true;
+
+    // Callbacks must be registered after endpoint allocation
+    cdcdf_acm_register_callback(CDCDF_ACM_CB_READ, (FUNC_PTR)RxComplete);
+    cdcdf_acm_register_callback(CDCDF_ACM_CB_WRITE, (FUNC_PTR)TxComplete);
+    // Start Rx
+    cdcdf_acm_read(m_usbReadBuf, sizeof(m_usbReadBuf));
+}
+
+void UsbManager::PortClose() {
+    if (!m_portOpen) {
+        return;
+    }
+
+    // Flush the transmit buffer before closing
+    TxPump();
+    WaitForWriteFinish();
+
+    m_portOpen = false;
+
+    // Callbacks must be registered after endpoint allocation
+    cdcdf_acm_register_callback(CDCDF_ACM_CB_READ, (FUNC_PTR)NULL);
+    cdcdf_acm_register_callback(CDCDF_ACM_CB_WRITE, (FUNC_PTR)NULL);
+    // Stop Rx/Tx
+    cdcdf_acm_stop_xfer();
+
+    m_inHead = 0;
+    m_inTail = 0;
+    m_outHead = 0;
+    m_outTail = 0;
+    m_readBufAvail = 0;
+    m_sendActive = false;
+    m_readActive = false;
+}
+
+void UsbManager::FlushInput() {
+    m_inHead = 0;
+    m_inTail = 0;
+    m_readActive = false;
+    m_readBufAvail = 0;
+    cdcdf_acm_read(m_usbReadBuf, sizeof(m_usbReadBuf));
+}
+
+void UsbManager::WaitForWriteFinish() {
+    while (m_outHead != m_outTail && Connected()) {
+        continue;
+    }
+}
+
+bool UsbManager::Connected() {
+    return cdcdf_acm_is_enabled() && LineState().rs232.DTR &&
+           USB->DEVICE.FSMSTATUS.bit.FSMSTATE == USB_FSMSTATUS_FSMSTATE_ON;
+}
+
+UsbManager::operator bool() {
+    bool retVal = Connected();
+    Delay_ms(10);
+    return retVal;
+}
+
+int16_t UsbManager::CharGet() {
+    uint32_t head = m_inHead;
+    if (m_inTail == head) {
+        return -1;
+    }
+    uint8_t retVal = m_bufferIn[head];
+    m_inHead = (head + 1) & (sizeof(m_bufferIn) - 1);
+    RxCopyToRingBuf();
+    return retVal;
+}
+
+int16_t UsbManager::CharPeek() {
+    if (m_inTail == m_inHead) {
+        return -1;
+    }
+    return m_bufferIn[m_inHead];
+}
+
+bool UsbManager::SendChar(uint8_t charToSend) {
+    while (Connected() && m_portOpen) {
+        if (AvailableForWrite()) {
+            m_bufferOut[m_outTail] = charToSend;
+            m_outTail = (m_outTail + 1) & (sizeof(m_bufferOut) - 1);
+            return true;
+        }
+    }
+    return false;
+}
+
+/**
+    Return the number of free characters in the receive buffer
+**/
+int32_t UsbManager::AvailableForRead() {
+    int32_t difference = m_inTail - m_inHead;
+
+    if (difference < 0) {
+        return sizeof(m_bufferIn) + difference;
+    }
+    else {
+        return difference;
+    }
+}
+
+/**
+    Returns the number of available characters in the transmit buffer
+**/
+int32_t UsbManager::AvailableForWrite() {
+    int32_t difference = m_outHead - m_outTail - 1;
+
+    if (difference < 0) {
+        difference += sizeof(m_bufferOut);
+    }
+
+    return difference;
+}
+
+/**
+    Transmit any data waiting in the tx buffer
+**/
+void UsbManager::TxPump() {
+    if (atomic_test_and_set_acqrel(&m_sendActive)) {
+        // Already sending; can't send anything more right now
+        return;
+    }
+
+    uint32_t head = m_outHead;
+    uint32_t tail = m_outTail;
+    if (head == tail) {
+        // Nothing to send, bail out
+        atomic_clear_seqcst(&m_sendActive);
+        return;
+    }
+
+    // The data sent to cdcdf_acm_write needs to be 4-byte aligned,
+    // so copy the data into an aligned buffer before sending it out
+    uint32_t count = sizeof(m_usbWriteBuf);
+    uint8_t *inPtr = m_bufferOut + head, *outPtr = m_usbWriteBuf;
+    if (head < tail) {
+        count = min(count, tail - head);
+        for (uint32_t iChar = 0; iChar < count; iChar++) {
+            *outPtr++ = *inPtr++;
+        }
+    }
+    else {
+        uint32_t countTilWrap = sizeof(m_bufferOut) - head;
+        count = min(count, countTilWrap + tail);
+        uint32_t loopEnd = min(countTilWrap, count);
+        for (uint32_t iChar = 0; iChar < loopEnd; iChar++) {
+            *outPtr++ = *inPtr++;
+        }
+        inPtr = m_bufferOut;
+        loopEnd = count - loopEnd;
+        for (uint32_t iChar = 0; iChar < loopEnd; iChar++) {
+            *outPtr++ = *inPtr++;
+        }
+    }
+    if (cdcdf_acm_write(m_usbWriteBuf, count)) {
+        // cdcdf_acm_write failed, clear the send active flag
+        atomic_clear_seqcst(&m_sendActive);
+    }
+}
+
+bool UsbManager::TxComplete(const uint8_t ep,
+                            const enum usb_xfer_code rc,
+                            const uint32_t count) {
+    UNUSED(ep);
+
+    if (rc == USB_XFER_DONE) {
+        UsbMgr.m_outHead =
+            (UsbMgr.m_outHead + count) & (sizeof(m_bufferOut) - 1);
+    }
+    atomic_clear_seqcst(&UsbMgr.m_sendActive);
+    UsbMgr.TxPump();
+
+    return true;
+}
+
+bool UsbManager::RxComplete(const uint8_t ep,
+                            const enum usb_xfer_code rc,
+                            const uint32_t count) {
+    UNUSED(ep);
+    UNUSED(rc);
+
+    __disable_irq();
+    // Make the Rx data available to be copied into the Rx ring buffer
+    UsbMgr.m_readBufAvail = count;
+    UsbMgr.m_readBufPtr = UsbMgr.m_usbReadBuf;
+    __enable_irq();
+    UsbMgr.RxCopyToRingBuf();
+    return true;
+}
+void UsbManager::Refresh(void) {
+    if (!m_sendActive && m_outHead != m_outTail) {
+        TxPump();
+    }
+}
+
+void UsbManager::RxCopyToRingBuf() {
+    __disable_irq();
+    uint32_t space = sizeof(m_bufferIn) - 1 - AvailableForRead();
+    if (m_readBufAvail && space) {
+
+        uint32_t count = min(space, m_readBufAvail);
+        uint32_t tail = m_inTail;
+        uint8_t *inPtr = m_readBufPtr;
+        uint8_t *outPtr = &m_bufferIn[tail];
+        uint32_t countTilWrap = sizeof(m_bufferIn) - tail;
+        countTilWrap = min(countTilWrap, count);
+
+        // Copy the available data until we get to the
+        // end of input data or the ring buffer wrap point
+        for (uint32_t i = 0; i < countTilWrap; i++) {
+            *outPtr++ = *inPtr++;
+        }
+        count -= countTilWrap;
+        m_readBufPtr += countTilWrap;
+        m_readBufAvail -= countTilWrap;
+        if (count) {
+            // Account for the ring buffer wrap point
+            // and copy the remaining available data
+            outPtr = m_bufferIn;
+            for (uint32_t i = 0; i < count; i++) {
+                *outPtr++ = *inPtr++;
+            }
+            m_inTail = count;
+            m_readBufPtr += count;
+            m_readBufAvail -= count;
+        }
+        else {
+            m_inTail = (tail + countTilWrap) & (sizeof(m_bufferIn) - 1);
+        }
+
+        // If all of the available input data has been copied into the
+        // ring buffer, read more input data from the USB device
+        if (!m_readBufAvail) {
+            cdcdf_acm_read(m_usbReadBuf, sizeof(m_usbReadBuf));
+        }
+    }
+    __enable_irq();
+}
+
+} // ClearCore namespace
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/XBeeDriver.cpp b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/XBeeDriver.cpp
new file mode 100644
index 000000000..1e5a58de9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/XBeeDriver.cpp
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2020 Teknic, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/**
+    XBee wireless manager implementation
+
+    This class manages the optional XBee board attached to the Teknic ClearCore.
+**/
+
+#include "XBeeDriver.h"
+#include <sam.h>
+
+namespace ClearCore {
+
+/**
+    Construct and wire into the board.
+**/
+XBeeDriver::XBeeDriver(const PeripheralRoute *ctsInfo,
+                       const PeripheralRoute *rtsInfo,
+                       const PeripheralRoute *rxInfo,
+                       const PeripheralRoute *txInfo,
+                       uint8_t peripheral)
+    : SerialBase(ctsInfo, rtsInfo, rxInfo, txInfo, peripheral) {
+    PortMode(SerialBase::UART);
+}
+
+} // ClearCore namespace
\ No newline at end of file
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/system_same53.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/system_same53.c
new file mode 100644
index 000000000..fb1680ef4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/src/system_same53.c
@@ -0,0 +1,245 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2017 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <same53.h>
+#include "SysUtils.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ *  the source for the main clock at chip startup.
+ */
+// Final CPU speed & DPLL1 frequency
+#define __CLEARCORE_CLOCK_HZ    (120000000)             // 120 MHz
+#define __SYSTEM_CLOCK          (__CLEARCORE_CLOCK_HZ)
+// Oscillator output into XOSC1
+#define __CLEARCORE_OSC_HZ      (25000000)              // 25 MHz
+// GCLK0 FREQ
+#define __CLEARCORE_GCLK0_HZ    __CLEARCORE_CLOCK_HZ
+// GCLK1 FREQ
+#define __CLEARCORE_GCLK1_HZ    (500000)                // 500 kHz
+// GCLK4 FREQ
+#define __CLEARCORE_GCLK4_HZ    (48000000)              // 48 MHz
+// GCLK5 FREQ
+#define __CLEARCORE_GCLK5_HZ    (1000000)               // 1 MHz
+// GCLK6 FREQ - set for 500Hz PWM with / 16; HLFB / 31.25Hz max period
+#define __CLEARCORE_GCLK6_HZ    (128000*16)             // 2.048 MHz
+// GCLK7 FREQ
+#define __CLEARCORE_GCLK7_HZ    (10000000)              // 10 MHz
+// DPLL0 FREQ
+#define __CLEARCORE_DPLL0_HZ    (96000000)              // 96 MHz
+// DPLL1 FREQ
+#define __CLEARCORE_DPLL1_HZ    (120000000)             // 120 MHz
+
+/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;
+
+/**
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the system and update the SystemCoreClock variable.
+ */
+void SystemInit(void) {
+    // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+    // Start and setup the various oscillators
+    // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+    // Start the external 10MHz MEMS oscillator
+    OSCCTRL->XOSCCTRL[1].reg =
+        OSCCTRL_XOSCCTRL_IMULT(4) |
+        OSCCTRL_XOSCCTRL_IPTAT(3) |
+        OSCCTRL_XOSCCTRL_ENABLE;
+    // Wait for clock to run
+    while (!OSCCTRL->STATUS.bit.XOSCRDY1) {
+        continue;
+    }
+    // Create 1MHz clock on GCLK5 to act as source for DPLL0/1 and SERCOM6
+    GCLK->GENCTRL[5].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC1_Val) |
+                           GCLK_GENCTRL_GENEN |
+                           GCLK_GENCTRL_DIV(__CLEARCORE_OSC_HZ /
+                                            __CLEARCORE_GCLK5_HZ) |
+                           GCLK_GENCTRL_IDC;
+    SYNCBUSY_WAIT(GCLK, GCLK_SYNCBUSY_GENCTRL5);
+
+    // Make good 120MHz CPU clock using DPLL1 multiplying GCLK5 up
+    SET_CLOCK_SOURCE(OSCCTRL_GCLK_ID_FDPLL1, 5);
+    // Set the integer part of the frequency multiplier (loop divider ratio)
+    OSCCTRL->Dpll[1].DPLLRATIO.reg =
+    OSCCTRL_DPLLRATIO_LDR(__CLEARCORE_DPLL1_HZ / __CLEARCORE_GCLK5_HZ - 1);  
+    // Set GCLK as the DPLL clock reference, and set Wake Up Fast
+    OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK |
+                                     OSCCTRL_DPLLCTRLB_WUF;
+        
+    // Set the DPLL (digital phase-locked loop) to run in standby and sleep mode
+    // If ONDEMAND is not set, the signal will be generated constantly
+    // Finally, enable the DPLL
+    OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY |
+                                     OSCCTRL_DPLLCTRLA_ENABLE;
+
+    while (OSCCTRL->STATUS.bit.DPLL1LCKR) {
+        continue;
+    }
+    // Route DPLL1 @ 120MHz to CPU Clock before killing off 48MHz clock we
+    // started with.
+    GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL1_Val) |
+                           GCLK_GENCTRL_GENEN |
+                           GCLK_GENCTRL_DIV(0);
+    SYNCBUSY_WAIT(GCLK, GCLK_SYNCBUSY_GENCTRL0);
+    // Clocks running and locked, switch core clock to 120MHz
+    MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV_DIV1;
+
+    // Use 96MHz clock for USB with / 2 on GCLK4 for 48MHz
+    // using GCLK5 as reference.
+    SET_CLOCK_SOURCE(OSCCTRL_GCLK_ID_FDPLL0, 5);
+    // set the integer part of the frequency multiplier (loop divider ratio)
+    OSCCTRL->Dpll[0].DPLLRATIO.reg =
+        OSCCTRL_DPLLRATIO_LDR(__CLEARCORE_DPLL0_HZ / __CLEARCORE_GCLK5_HZ - 1);
+        
+    // Set the lock timeout value to Default (none, automatic lock)
+    // Set the dedicated GCLK reference
+    // Set Wake Up Fast
+    OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_LTIME_DEFAULT |
+                                     OSCCTRL_DPLLCTRLB_REFCLK_GCLK |
+                                     OSCCTRL_DPLLCTRLB_WUF;
+    // enable the DPLL
+    OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
+
+    // Disable DFLL48M since we are going to use DPLL to generate 48MHz.
+    GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.CHEN = 0;
+    while (GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.CHEN) {
+        continue;
+    }
+
+    OSCCTRL->DFLLCTRLA.reg = 0;
+    // Setup GCLK4 to output 48 MHz for USB
+    GCLK->GENCTRL[4].reg = GCLK_GENCTRL_GENEN |
+                           GCLK_GENCTRL_DIV(__CLEARCORE_DPLL0_HZ /
+                                            __CLEARCORE_GCLK4_HZ) |
+                           GCLK_GENCTRL_SRC_DPLL0;
+    // Wait for clock domain sync
+    SYNCBUSY_WAIT(GCLK, GCLK_SYNCBUSY_GENCTRL4);
+
+    // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+    // Setup clock sources from oscillators or other sources
+    // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+    // Create 500kHz clock from GCLK1 to act as source for S&D mask
+    GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC1_Val) |
+                           GCLK_GENCTRL_GENEN |
+                           GCLK_GENCTRL_DIV(__CLEARCORE_OSC_HZ /
+                                            __CLEARCORE_GCLK1_HZ) |
+                           GCLK_GENCTRL_IDC |
+                           GCLK_GENCTRL_OE;
+
+    // Make sure PORT module is powered up and clocked
+    // Should be on already: CLOCK_ENABLE(APBBMASK, PORT_);
+    // Make sure SERCOMS are powered up and clocked
+    CLOCK_ENABLE(APBAMASK, SERCOM0_);
+    CLOCK_ENABLE(APBBMASK, TC3_); // HLFB(2)
+    CLOCK_ENABLE(APBAMASK, EIC_);
+
+    CLOCK_ENABLE(APBBMASK, EVSYS_);
+    CLOCK_ENABLE(APBBMASK, SERCOM2_);          // XBee
+
+    CLOCK_ENABLE(APBCMASK, TC4_); // HLFB(0)
+
+    CLOCK_ENABLE(AHBMASK, GMAC_);
+    CLOCK_ENABLE(APBCMASK, GMAC_); // Ethernet
+
+    CLOCK_ENABLE(APBDMASK, SERCOM4_);          // SD
+    CLOCK_ENABLE(APBDMASK, SERCOM7_);
+    CLOCK_ENABLE(APBDMASK, ADC1_);
+    CLOCK_ENABLE(APBCMASK, TC5_); // HLFB(1)
+    CLOCK_ENABLE(APBAMASK, TC0_); // HLFB(3)
+
+    CLOCK_ENABLE(APBDMASK, TC6_); // HBridge PWM output
+
+    // Enable the cache controller
+    CMCC->CTRL.reg = CMCC_CTRL_CEN;
+    // Enable the FPU
+    SCB->CPACR = 0xFU << 20;
+
+    // set up GCLK6 for OUT TCx and HLFB TCx
+    GCLK->GENCTRL[6].reg = GCLK_GENCTRL_GENEN |
+                           GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL1_Val) |
+                           GCLK_GENCTRL_DIV(__CLEARCORE_DPLL1_HZ /
+                                            __CLEARCORE_GCLK6_HZ);
+    SYNCBUSY_WAIT(GCLK, GCLK_SYNCBUSY_GENCTRL6);
+
+    // set up GCLK7 for SPI sercom clocking
+    GCLK->GENCTRL[7].reg = GCLK_GENCTRL_GENEN |
+                           GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL1_Val) |
+                           GCLK_GENCTRL_DIV(__CLEARCORE_DPLL1_HZ /
+                                            __CLEARCORE_GCLK7_HZ);
+
+    // CPU Clock @ 120MHz on GCLK(0), GCLK(6)=2.048MHz
+    SET_CLOCK_SOURCE(EIC_GCLK_ID, 6);
+    // HLFB timers
+    SET_CLOCK_SOURCE(TC0_GCLK_ID, 6);
+    SET_CLOCK_SOURCE(TC4_GCLK_ID, 6);
+    SET_CLOCK_SOURCE(TC6_GCLK_ID, 6);
+    
+    // NOTE: TC7 and TC6 share same clock source
+    // SET_CLOCK_SOURCE(TC7_GCLK_ID, 6);
+
+    // ZL: Is this still needed?
+    while (GCLK->SYNCBUSY.reg) {
+        continue;
+    }
+    return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void) {
+    // Not implemented
+    return;
+}
+
+/**
+ * Update GClk frequency
+ *
+ * @brief  Updates the divisor on the specified GClk to
+ *         generate the requested frequency
+ */
+void GClkFreqUpdate(uint8_t gclkIndex, uint32_t freqReq) {
+    // This adjustment is only supported for GClks that use XOSC1 as the src
+    if (GCLK->GENCTRL[gclkIndex].bit.SRC != GCLK_GENCTRL_SRC_XOSC1_Val) {
+        return;
+    }
+
+    // Configure the clock divisor for the requested frequency
+    GCLK->GENCTRL[gclkIndex].bit.DIV = __CLEARCORE_OSC_HZ / freqReq;
+    while (GCLK->SYNCBUSY.vec.GENCTRL & (1 << gclkIndex)) {
+        continue;
+    }
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm.c
new file mode 100644
index 000000000..2691cc8fe
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm.c
@@ -0,0 +1,379 @@
+/**
+ * \file
+ *
+ * \brief USB Device Stack CDC ACM Function Implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "cdcdf_acm.h"
+
+#define CDCDF_ACM_VERSION 0x00000001u
+#define CDCDF_ACM_COMM_EP_INDEX 0
+#define CDCDF_ACM_DATA_EP_INDEX 1
+
+/** USB Device CDC ACM Fucntion Specific Data */
+struct cdcdf_acm_func_data {
+	/** CDC Device ACM Interface information */
+	uint8_t func_iface[2];
+	/** CDC Device ACM IN Endpoint */
+	uint8_t func_ep_in[2];
+	/** CDC Device ACM OUT Endpoint */
+	uint8_t func_ep_out;
+	/** CDC Device ACM Enable Flag */
+	bool enabled;
+};
+
+static struct usbdf_driver        _cdcdf_acm;
+static struct cdcdf_acm_func_data _cdcdf_acm_funcd;
+static struct usb_cdc_line_coding usbd_cdc_line_coding;
+
+static cdcdf_acm_notify_state_t    cdcdf_acm_notify_state    = NULL;
+static cdcdf_acm_set_line_coding_t cdcdf_acm_set_line_coding = NULL;
+
+/**
+ * \brief Enable CDC ACM Function
+ * \param[in] drv Pointer to USB device function driver
+ * \param[in] desc Pointer to USB interface descriptor
+ * \return Operation status.
+ */
+static int32_t cdcdf_acm_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc)
+{
+	struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data);
+
+	usb_ep_desc_t    ep_desc;
+	usb_iface_desc_t ifc_desc;
+	uint8_t *        ifc, *ep;
+	uint8_t          i;
+
+	ifc = desc->sod;
+	for (i = 0; i < 2; i++) {
+		if (NULL == ifc) {
+			return ERR_NOT_FOUND;
+		}
+
+		ifc_desc.bInterfaceNumber = ifc[2];
+		ifc_desc.bInterfaceClass  = ifc[5];
+
+		if ((CDC_CLASS_COMM == ifc_desc.bInterfaceClass) || (CDC_CLASS_DATA == ifc_desc.bInterfaceClass)) {
+			if (func_data->func_iface[i] == ifc_desc.bInterfaceNumber) { // Initialized
+				return ERR_ALREADY_INITIALIZED;
+			} else if (func_data->func_iface[i] != 0xFF) { // Occupied
+				return ERR_NO_RESOURCE;
+			} else {
+				func_data->func_iface[i] = ifc_desc.bInterfaceNumber;
+			}
+		} else { // Not supported by this function driver
+			return ERR_NOT_FOUND;
+		}
+
+		// Install endpoints
+		ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT);
+		while (NULL != ep) {
+			ep_desc.bEndpointAddress = ep[2];
+			ep_desc.bmAttributes     = ep[3];
+			ep_desc.wMaxPacketSize   = usb_get_u16(ep + 4);
+			if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) {
+				return ERR_NOT_INITIALIZED;
+			}
+			if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) {
+				func_data->func_ep_in[i] = ep_desc.bEndpointAddress;
+				usb_d_ep_enable(func_data->func_ep_in[i]);
+			} else {
+				func_data->func_ep_out = ep_desc.bEndpointAddress;
+				usb_d_ep_enable(func_data->func_ep_out);
+			}
+			desc->sod = ep;
+			ep        = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod);
+		}
+		ifc = usb_find_desc(usb_desc_next(desc->sod), desc->eod, USB_DT_INTERFACE);
+	}
+	// Installed
+	_cdcdf_acm_funcd.enabled = true;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable CDC ACM Function
+ * \param[in] drv Pointer to USB device function driver
+ * \param[in] desc Pointer to USB device descriptor
+ * \return Operation status.
+ */
+static int32_t cdcdf_acm_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc)
+{
+	struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data);
+
+	usb_iface_desc_t ifc_desc;
+	uint8_t          i;
+
+	if (desc) {
+		ifc_desc.bInterfaceClass = desc->sod[5];
+		// Check interface
+		if ((ifc_desc.bInterfaceClass != CDC_CLASS_COMM) && (ifc_desc.bInterfaceClass != CDC_CLASS_DATA)) {
+			return ERR_NOT_FOUND;
+		}
+	}
+
+	for (i = 0; i < 2; i++) {
+		if (func_data->func_iface[i] == 0xFF) {
+			continue;
+		} else {
+			func_data->func_iface[i] = 0xFF;
+			if (func_data->func_ep_in[i] != 0xFF) {
+				usb_d_ep_deinit(func_data->func_ep_in[i]);
+				func_data->func_ep_in[i] = 0xFF;
+			}
+		}
+	}
+
+	if (func_data->func_ep_out != 0xFF) {
+		usb_d_ep_deinit(func_data->func_ep_out);
+		func_data->func_ep_out = 0xFF;
+	}
+
+	_cdcdf_acm_funcd.enabled = false;
+	return ERR_NONE;
+}
+
+/**
+ * \brief CDC ACM Control Function
+ * \param[in] drv Pointer to USB device function driver
+ * \param[in] ctrl USB device general function control type
+ * \param[in] param Parameter pointer
+ * \return Operation status.
+ */
+static int32_t cdcdf_acm_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param)
+{
+	switch (ctrl) {
+	case USBDF_ENABLE:
+		return cdcdf_acm_enable(drv, (struct usbd_descriptors *)param);
+
+	case USBDF_DISABLE:
+		return cdcdf_acm_disable(drv, (struct usbd_descriptors *)param);
+
+	case USBDF_GET_IFACE:
+		return ERR_UNSUPPORTED_OP;
+
+	default:
+		return ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Process the CDC class set request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ */
+static int32_t cdcdf_acm_set_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage)
+{
+	struct usb_cdc_line_coding line_coding_tmp;
+	uint16_t                   len      = req->wLength;
+	uint8_t *                  ctrl_buf = usbdc_get_ctrl_buffer();
+
+	switch (req->bRequest) {
+	case USB_REQ_CDC_SET_LINE_CODING:
+		if (sizeof(struct usb_cdc_line_coding) != len) {
+			return ERR_INVALID_DATA;
+		}
+		if (USB_SETUP_STAGE == stage) {
+			return usbdc_xfer(ep, ctrl_buf, len, false);
+		} else {
+			memcpy(&line_coding_tmp, ctrl_buf, sizeof(struct usb_cdc_line_coding));
+			if ((NULL == cdcdf_acm_set_line_coding) || (true == cdcdf_acm_set_line_coding(&line_coding_tmp))) {
+				usbd_cdc_line_coding = line_coding_tmp;
+			}
+			return ERR_NONE;
+		}
+	case USB_REQ_CDC_SET_CONTROL_LINE_STATE:
+		usbdc_xfer(0, NULL, 0, 0);
+		if (NULL != cdcdf_acm_notify_state) {
+			cdcdf_acm_notify_state(req->wValue);
+		}
+		return ERR_NONE;
+	default:
+		return ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Process the CDC class get request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ */
+static int32_t cdcdf_acm_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage)
+{
+	uint16_t len = req->wLength;
+
+	if (USB_DATA_STAGE == stage) {
+		return ERR_NONE;
+	}
+
+	switch (req->bRequest) {
+	case USB_REQ_CDC_GET_LINE_CODING:
+		if (sizeof(struct usb_cdc_line_coding) != len) {
+			return ERR_INVALID_DATA;
+		}
+		return usbdc_xfer(ep, (uint8_t *)&usbd_cdc_line_coding, len, false);
+	default:
+		return ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Process the CDC class request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ */
+static int32_t cdcdf_acm_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage)
+{
+	if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request
+		return ERR_NOT_FOUND;
+	}
+	if ((req->wIndex == _cdcdf_acm_funcd.func_iface[0]) || (req->wIndex == _cdcdf_acm_funcd.func_iface[1])) {
+		if (req->bmRequestType & USB_EP_DIR_IN) {
+			return cdcdf_acm_get_req(ep, req, stage);
+		} else {
+			return cdcdf_acm_set_req(ep, req, stage);
+		}
+	} else {
+		return ERR_NOT_FOUND;
+	}
+}
+
+/** USB Device CDC ACM Handler Struct */
+static struct usbdc_handler cdcdf_acm_req_h = {NULL, (FUNC_PTR)cdcdf_acm_req};
+
+/**
+ * \brief Initialize the USB CDC ACM Function Driver
+ */
+int32_t cdcdf_acm_init(void)
+{
+	if (usbdc_get_state() > USBD_S_POWER) {
+		return ERR_DENIED;
+	}
+
+	_cdcdf_acm.ctrl      = cdcdf_acm_ctrl;
+	_cdcdf_acm.func_data = &_cdcdf_acm_funcd;
+
+	usbdc_register_function(&_cdcdf_acm);
+	usbdc_register_handler(USBDC_HDL_REQ, &cdcdf_acm_req_h);
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize the USB CDC ACM Function Driver
+ */
+void cdcdf_acm_deinit(void)
+{
+	usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_COMM_EP_INDEX]);
+	usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]);
+	usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_out);
+}
+
+/**
+ * \brief USB CDC ACM Function Read Data
+ */
+int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size)
+{
+	if (!cdcdf_acm_is_enabled()) {
+		return ERR_DENIED;
+	}
+	return usbdc_xfer(_cdcdf_acm_funcd.func_ep_out, buf, size, false);
+}
+
+/**
+ * \brief USB CDC ACM Function Write Data
+ */
+int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size)
+{
+	if (!cdcdf_acm_is_enabled()) {
+		return ERR_DENIED;
+	}
+	return usbdc_xfer(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], buf, size, true);
+}
+
+/**
+ * \brief USB CDC ACM Stop the data transfer
+ */
+void cdcdf_acm_stop_xfer(void)
+{
+	/* Stop transfer. */
+	usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]);
+	usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_out);
+}
+
+/**
+ * \brief USB CDC ACM Function Register Callback
+ */
+int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func)
+{
+	switch (cb_type) {
+	case CDCDF_ACM_CB_READ:
+		usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_out, USB_D_EP_CB_XFER, func);
+		break;
+	case CDCDF_ACM_CB_WRITE:
+		usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], USB_D_EP_CB_XFER, func);
+		break;
+	case CDCDF_ACM_CB_LINE_CODING_C:
+		cdcdf_acm_set_line_coding = (cdcdf_acm_set_line_coding_t)func;
+		break;
+	case CDCDF_ACM_CB_STATE_C:
+		cdcdf_acm_notify_state = (cdcdf_acm_notify_state_t)func;
+		break;
+	default:
+		return ERR_INVALID_ARG;
+	}
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check whether CDC ACM Function is enabled
+ */
+bool cdcdf_acm_is_enabled(void)
+{
+	return _cdcdf_acm_funcd.enabled;
+}
+
+/**
+ * \brief Return the CDC ACM line coding structure start address
+ */
+const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void)
+{
+	return (const struct usb_cdc_line_coding *)&usbd_cdc_line_coding;
+}
+
+/**
+ * \brief Return version
+ */
+uint32_t cdcdf_acm_get_version(void)
+{
+	return CDCDF_ACM_VERSION;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm.h
new file mode 100644
index 000000000..ad060bc50
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm.h
@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief USB Device Stack CDC ACM Function Definition.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef USBDF_CDC_ACM_SER_H_
+#define USBDF_CDC_ACM_SER_H_
+
+#include "usbdc.h"
+#include "usb_protocol_cdc.h"
+
+/** CDC ACM Class Callback Type */
+enum cdcdf_acm_cb_type { CDCDF_ACM_CB_READ, CDCDF_ACM_CB_WRITE, CDCDF_ACM_CB_LINE_CODING_C, CDCDF_ACM_CB_STATE_C };
+
+/** CDC ACM Notify Line State Callback. */
+typedef void (*cdcdf_acm_notify_state_t)(uint16_t);
+
+/** CDC ACM Set Line Coding Callback. */
+typedef bool (*cdcdf_acm_set_line_coding_t)(struct usb_cdc_line_coding *);
+
+/**
+ * \brief Initialize the USB CDC ACM Function Driver
+ * \return Operation status.
+ */
+int32_t cdcdf_acm_init(void);
+
+/**
+ * \brief Deinitialize the USB CDC ACM Function Driver
+ * \return Operation status.
+ */
+void cdcdf_acm_deinit(void);
+
+/**
+ * \brief USB CDC ACM Function Read Data
+ * \param[in] buf Pointer to the buffer which receives data
+ * \param[in] size the size of data to be received
+ * \return Operation status.
+ */
+int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size);
+
+/**
+ * \brief USB CDC ACM Function Write Data
+ * \param[in] buf Pointer to the buffer which stores data
+ * \param[in] size the size of data to be sent
+ * \return Operation status.
+ */
+int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size);
+
+/**
+ * \brief USB CDC ACM Stop the currnet data transfer
+ */
+void cdcdf_acm_stop_xfer(void);
+
+/**
+ * \brief USB CDC ACM Function Register Callback
+ * \param[in] cb_type Callback type of CDC ACM Function
+ * \param[in] func Pointer to callback function
+ * \return Operation status.
+ */
+int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func);
+
+/**
+ * \brief Check whether CDC ACM Function is enabled
+ * \return Operation status.
+ * \return true CDC ACM Function is enabled
+ * \return false CDC ACM Function is disabled
+ */
+bool cdcdf_acm_is_enabled(void);
+
+/**
+ * \brief Return the CDC ACM line coding structure start address
+ * \return Pointer to USB CDC ACM line coding data.
+ */
+const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void);
+
+/**
+ * \brief Return version
+ */
+uint32_t cdcdf_acm_get_version(void);
+
+#endif /* USBDF_CDC_ACM_SER_H_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm_desc.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm_desc.h
new file mode 100644
index 000000000..ca29d33a9
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/device/cdcdf_acm_desc.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief USB Device Stack CDC ACM Function Descriptor Setting.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef USBDF_CDC_ACM_DESC_H_
+#define USBDF_CDC_ACM_DESC_H_
+
+#include "usb_protocol.h"
+#include "usb_protocol_cdc.h"
+#include "usbd_config.h"
+
+#define CDCD_ACM_DEV_DESC                                                                                              \
+	USB_DEV_DESC_BYTES(CONF_USB_CDCD_ACM_BCDUSB,                                                                       \
+	                   0x02,                                                                                           \
+	                   0x00,                                                                                           \
+	                   0x00,                                                                                           \
+	                   CONF_USB_CDCD_ACM_BMAXPKSZ0,                                                                    \
+	                   CONF_USB_CDCD_ACM_IDVENDER,                                                                     \
+	                   CONF_USB_CDCD_ACM_IDPRODUCT,                                                                    \
+	                   CONF_USB_CDCD_ACM_BCDDEVICE,                                                                    \
+	                   CONF_USB_CDCD_ACM_IMANUFACT,                                                                    \
+	                   CONF_USB_CDCD_ACM_IPRODUCT,                                                                     \
+	                   CONF_USB_CDCD_ACM_ISERIALNUM,                                                                   \
+	                   CONF_USB_CDCD_ACM_BNUMCONFIG)
+
+#define CDCD_ACM_DEV_QUAL_DESC                                                                                         \
+	USB_DEV_QUAL_DESC_BYTES(                                                                                           \
+	    CONF_USB_CDCD_ACM_BCDUSB, 0x02, 0x00, 0x00, CONF_USB_CDCD_ACM_BMAXPKSZ0, CONF_USB_CDCD_ACM_BNUMCONFIG)
+
+#define CDCD_ACM_CFG_DESC                                                                                              \
+	USB_CONFIG_DESC_BYTES(67,                                                                                          \
+	                      2,                                                                                           \
+	                      CONF_USB_CDCD_ACM_BCONFIGVAL,                                                                \
+	                      CONF_USB_CDCD_ACM_ICONFIG,                                                                   \
+	                      CONF_USB_CDCD_ACM_BMATTRI,                                                                   \
+	                      CONF_USB_CDCD_ACM_BMAXPOWER)
+
+#define CDCD_ACM_OTH_SPD_CFG_DESC                                                                                      \
+	USB_OTH_SPD_CFG_DESC_BYTES(67,                                                                                     \
+	                           2,                                                                                      \
+	                           CONF_USB_CDCD_ACM_BCONFIGVAL,                                                           \
+	                           CONF_USB_CDCD_ACM_ICONFIG,                                                              \
+	                           CONF_USB_CDCD_ACM_BMATTRI,                                                              \
+	                           CONF_USB_CDCD_ACM_BMAXPOWER)
+
+#define CDCD_ACM_COMM_IFACE_DESCES                                                                                     \
+	USB_IFACE_DESC_BYTES(CONF_USB_CDCD_ACM_COMM_BIFCNUM,                                                               \
+	                     CONF_USB_CDCD_ACM_COMM_BALTSET,                                                               \
+	                     1,                                                                                            \
+	                     0x2,                                                                                          \
+	                     0x2,                                                                                          \
+	                     0x0,                                                                                          \
+	                     CONF_USB_CDCD_ACM_COMM_IIFC),                                                                 \
+	    USB_CDC_HDR_DESC_BYTES(0x1001), USB_CDC_CALL_MGMT_DESC_BYTES(0x01, 0x00), USB_CDC_ACM_DESC_BYTES(0x02),        \
+	    USB_CDC_UNION_DESC_BYTES(CONF_USB_CDCD_ACM_COMM_BIFCNUM, 0x01),                                                \
+	    USB_ENDP_DESC_BYTES(CONF_USB_CDCD_ACM_COMM_INT_EPADDR,                                                         \
+	                        3,                                                                                         \
+	                        CONF_USB_CDCD_ACM_COMM_INT_MAXPKSZ,                                                        \
+	                        CONF_USB_CDCD_ACM_COMM_INT_INTERVAL)
+
+#define CDCD_ACM_DATA_IFACE_DESCES                                                                                     \
+	USB_IFACE_DESC_BYTES(CONF_USB_CDCD_ACM_DATA_BIFCNUM,                                                               \
+	                     CONF_USB_CDCD_ACM_DATA_BALTSET,                                                               \
+	                     2,                                                                                            \
+	                     0x0A,                                                                                         \
+	                     0x0,                                                                                          \
+	                     0x0,                                                                                          \
+	                     CONF_USB_CDCD_ACM_DATA_IIFC),                                                                 \
+	    USB_ENDP_DESC_BYTES(CONF_USB_CDCD_ACM_DATA_BULKOUT_EPADDR, 2, CONF_USB_CDCD_ACM_DATA_BULKOUT_MAXPKSZ, 0),      \
+	    USB_ENDP_DESC_BYTES(CONF_USB_CDCD_ACM_DATA_BULKIN_EPADDR, 2, CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ, 0)
+
+#define CDCD_ACM_DATA_IFACE_DESCES_HS                                                                                  \
+	USB_IFACE_DESC_BYTES(CONF_USB_CDCD_ACM_DATA_BIFCNUM,                                                               \
+	                     CONF_USB_CDCD_ACM_DATA_BALTSET,                                                               \
+	                     2,                                                                                            \
+	                     0x0A,                                                                                         \
+	                     0x0,                                                                                          \
+	                     0x0,                                                                                          \
+	                     CONF_USB_CDCD_ACM_DATA_IIFC),                                                                 \
+	    USB_ENDP_DESC_BYTES(CONF_USB_CDCD_ACM_DATA_BULKOUT_EPADDR, 2, CONF_USB_CDCD_ACM_DATA_BULKOUT_MAXPKSZ_HS, 0),   \
+	    USB_ENDP_DESC_BYTES(CONF_USB_CDCD_ACM_DATA_BULKIN_EPADDR, 2, CONF_USB_CDCD_ACM_DATA_BULKIN_MAXPKSZ_HS, 0)
+
+#define CDCD_ACM_STR_DESCES                                                                                            \
+	CONF_USB_CDCD_ACM_LANGID_DESC                                                                                      \
+	CONF_USB_CDCD_ACM_IMANUFACT_STR_DESC                                                                               \
+	CONF_USB_CDCD_ACM_IPRODUCT_STR_DESC                                                                                \
+	CONF_USB_CDCD_ACM_ISERIALNUM_STR_DESC                                                                              \
+	CONF_USB_CDCD_ACM_ICONFIG_STR_DESC
+
+/** USB Device descriptors and configuration descriptors */
+#define CDCD_ACM_DESCES_LS_FS                                                                                          \
+	CDCD_ACM_DEV_DESC, CDCD_ACM_CFG_DESC, CDCD_ACM_COMM_IFACE_DESCES, CDCD_ACM_DATA_IFACE_DESCES, CDCD_ACM_STR_DESCES
+
+#define CDCD_ACM_HS_DESCES_LS_FS                                                                                       \
+	CDCD_ACM_DEV_DESC, CDCD_ACM_DEV_QUAL_DESC, CDCD_ACM_CFG_DESC, CDCD_ACM_COMM_IFACE_DESCES,                          \
+	    CDCD_ACM_DATA_IFACE_DESCES, CDCD_ACM_OTH_SPD_CFG_DESC, CDCD_ACM_COMM_IFACE_DESCES,                             \
+	    CDCD_ACM_DATA_IFACE_DESCES_HS, CDCD_ACM_STR_DESCES
+
+#define CDCD_ACM_HS_DESCES_HS                                                                                          \
+	CDCD_ACM_CFG_DESC, CDCD_ACM_COMM_IFACE_DESCES, CDCD_ACM_DATA_IFACE_DESCES_HS, CDCD_ACM_OTH_SPD_CFG_DESC,           \
+	    CDCD_ACM_COMM_IFACE_DESCES, CDCD_ACM_DATA_IFACE_DESCES
+
+#endif /* USBDF_CDC_ACM_DESC_H_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/usb_protocol_cdc.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/usb_protocol_cdc.h
new file mode 100644
index 000000000..29d882a5a
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/class/cdc/usb_protocol_cdc.h
@@ -0,0 +1,426 @@
+/**
+ * \file
+ *
+ * \brief USB Communication Device Class (CDC) protocol definitions
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef _USB_PROTOCOL_CDC_H_
+#define _USB_PROTOCOL_CDC_H_
+
+#include "usb_includes.h"
+
+/**
+ * \ingroup usb_protocol_group
+ * \defgroup cdc_protocol_group Communication Device Class Definitions
+ * @{
+ */
+
+/**
+ * \name Possible values of class
+ */
+//@{
+#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class
+#define CDC_CLASS_COMM 0x02   //!< CDC Communication Class Interface
+#define CDC_CLASS_DATA 0x0A   //!< CDC Data Class Interface
+//@}
+
+//! \name USB CDC Subclass IDs
+//@{
+#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model
+#define CDC_SUBCLASS_ACM 0x02  //!< Abstract Control Model
+#define CDC_SUBCLASS_TCM 0x03  //!< Telephone Control Model
+#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model
+#define CDC_SUBCLASS_CCM 0x05  //!< CAPI Control Model
+#define CDC_SUBCLASS_ETH 0x06  //!< Ethernet Networking Control Model
+#define CDC_SUBCLASS_ATM 0x07  //!< ATM Networking Control Model
+//@}
+
+//! \name USB CDC Communication Interface Protocol IDs
+//@{
+#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands
+//@}
+
+//! \name USB CDC Data Interface Protocol IDs
+//@{
+#define CDC_PROTOCOL_I430 0x30   //!< ISDN BRI
+#define CDC_PROTOCOL_HDLC 0x31   //!< HDLC
+#define CDC_PROTOCOL_TRANS 0x32  //!< Transparent
+#define CDC_PROTOCOL_Q921M 0x50  //!< Q.921 management protocol
+#define CDC_PROTOCOL_Q921 0x51   //!< Q.931 [sic] Data link protocol
+#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor
+#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures
+#define CDC_PROTOCOL_Q931 0x91   //!< Euro-ISDN protocol control
+#define CDC_PROTOCOL_V120 0x92   //!< V.24 rate adaption to ISDN
+#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands
+#define CDC_PROTOCOL_HOST 0xFD   //!< Host based driver
+/**
+ * \brief Describes the Protocol Unit Functional Descriptors [sic]
+ * on Communication Class Interface
+ */
+#define CDC_PROTOCOL_PUFD 0xFE
+//@}
+
+//! \name USB CDC Functional Descriptor Types
+//@{
+#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor
+#define CDC_CS_ENDPOINT 0x25  //!< Endpoint Functional Descriptor
+//@}
+
+//! \name USB CDC Functional Descriptor Subtypes
+//@{
+#define CDC_SCS_HEADER 0x00    //!< Header Functional Descriptor
+#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management
+#define CDC_SCS_ACM 0x02       //!< Abstract Control Management
+#define CDC_SCS_UNION 0x06     //!< Union Functional Descriptor
+//@}
+
+//! \name USB CDC Request IDs
+//@{
+#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00
+#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01
+#define USB_REQ_CDC_SET_COMM_FEATURE 0x02
+#define USB_REQ_CDC_GET_COMM_FEATURE 0x03
+#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04
+#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10
+#define USB_REQ_CDC_SET_HOOK_STATE 0x11
+#define USB_REQ_CDC_PULSE_SETUP 0x12
+#define USB_REQ_CDC_SEND_PULSE 0x13
+#define USB_REQ_CDC_SET_PULSE_TIME 0x14
+#define USB_REQ_CDC_RING_AUX_JACK 0x15
+#define USB_REQ_CDC_SET_LINE_CODING 0x20
+#define USB_REQ_CDC_GET_LINE_CODING 0x21
+#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22
+#define USB_REQ_CDC_SEND_BREAK 0x23
+#define USB_REQ_CDC_SET_RINGER_PARMS 0x30
+#define USB_REQ_CDC_GET_RINGER_PARMS 0x31
+#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32
+#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33
+#define USB_REQ_CDC_SET_LINE_PARMS 0x34
+#define USB_REQ_CDC_GET_LINE_PARMS 0x35
+#define USB_REQ_CDC_DIAL_DIGITS 0x36
+#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37
+#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38
+#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39
+#define USB_REQ_CDC_GET_PROFILE 0x3A
+#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
+#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41
+#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42
+#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43
+#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44
+#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50
+#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51
+#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52
+#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53
+// Added bNotification codes according cdc spec 1.1 chapter 6.3
+#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09
+#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20
+#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28
+#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29
+//@}
+
+/*
+ * Need to pack structures tightly, or the compiler might insert padding
+ * and violate the spec-mandated layout.
+ */
+COMPILER_PACK_SET(1)
+
+//! \name USB CDC Descriptors
+//@{
+
+//! CDC Header Functional Descriptor
+typedef struct usb_cdc_hdr_desc {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	le16_t  bcdCDC;
+} usb_cdc_hdr_desc_t;
+
+#define USB_CDC_HDR_DESC_LEN 5
+#define USB_CDC_HDR_DESC_BYTES(bcdCDC)                                                                                 \
+	USB_CDC_HDR_DESC_LEN,                  /* bFunctionLength */                                                       \
+	    CDC_CS_INTERFACE,                  /* bDescriptorType */                                                       \
+	    CDC_SCS_HEADER,                    /* bDescriptorSubtype */                                                    \
+	    LE_BYTE0(bcdCDC), LE_BYTE1(bcdCDC) /* bcdCDC */
+
+//! CDC Call Management Functional Descriptor
+typedef struct usb_cdc_call_mgmt_desc {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bmCapabilities;
+	uint8_t bDataInterface;
+} usb_cdc_call_mgmt_desc_t;
+
+#define USB_CDC_CALL_MGMT_DESC_LEN 5
+#define USB_CDC_CALL_MGMT_DESC_BYTES(bmCapabilities, bDataInterface)                                                   \
+	USB_CDC_CALL_MGMT_DESC_LEN, /* bFunctionLength */                                                                  \
+	    CDC_CS_INTERFACE,       /* bDescriptorType */                                                                  \
+	    CDC_SCS_CALL_MGMT,      /* bDescriptorSubtype */                                                               \
+	    bmCapabilities, bDataInterface
+
+//! CDC ACM Functional Descriptor
+typedef struct usb_cdc_acm_desc {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bmCapabilities;
+} usb_cdc_acm_desc_t;
+
+#define USB_CDC_ACM_DESC_LEN 4
+#define USB_CDC_ACM_DESC_BYTES(bmCapabilities)                                                                         \
+	USB_CDC_ACM_DESC_LEN, /* bFunctionLength */                                                                        \
+	    CDC_CS_INTERFACE, /* bDescriptorType */                                                                        \
+	    CDC_SCS_ACM,      /* bDescriptorSubType */                                                                     \
+	    bmCapabilities
+
+//! CDC Union Functional Descriptor
+typedef struct usb_cdc_union_desc {
+	uint8_t bFunctionLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bMasterInterface;
+	uint8_t bSlaveInterface0;
+} usb_cdc_union_desc_t;
+
+#define USB_CDC_UNION_DESC_LEN 5
+#define USB_CDC_UNION_DESC_BYTES(bMasterInterface, bSlaveInterface)                                                    \
+	USB_CDC_UNION_DESC_LEN, CDC_CS_INTERFACE, CDC_SCS_UNION, bMasterInterface, bSlaveInterface
+
+//! \name USB CDC Call Management Capabilities
+//@{
+//! Device handles call management itself
+#define CDC_CALL_MGMT_SUPPORTED (1 << 0)
+//! Device can send/receive call management info over a Data Class interface
+#define CDC_CALL_MGMT_OVER_DCI (1 << 1)
+//@}
+
+//! \name USB CDC ACM Capabilities
+//@{
+//! Device supports the request combination of
+//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
+#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0)
+//! Device supports the request combination of
+//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding,
+//! and the notification Serial_State.
+#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1)
+//! Device supports the request Send_Break
+#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2)
+//! Device supports the notification Network_Connection.
+#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3)
+//@}
+//@}
+
+//! \name USB CDC line control
+//@{
+
+//! \name USB CDC line coding
+//@{
+
+//! Line Coding structure
+typedef struct usb_cdc_line_coding {
+	le32_t  dwDTERate;   //!< Data rate, bits per second
+	uint8_t bCharFormat; //!< 0-1 Stop bit,1-1.5 Stop bits,2-2 Stop bits
+	uint8_t bParityType; //!< 0-None,1-Odd,2-Even,3-Mark,4-Space
+	uint8_t bDataBits;   //!< 5,6,7,8 or 16
+} usb_cdc_line_coding_t;
+
+//! Possible values of bCharFormat
+enum cdc_char_format {
+	CDC_STOP_BITS_1   = 0, //!< 1 stop bit
+	CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits
+	CDC_STOP_BITS_2   = 2  //!< 2 stop bits
+};
+
+//! Possible values of bParityType
+enum cdc_parity {
+	CDC_PAR_NONE  = 0, //!< No parity
+	CDC_PAR_ODD   = 1, //!< Odd parity
+	CDC_PAR_EVEN  = 2, //!< Even parity
+	CDC_PAR_MARK  = 3, //!< Parity forced to 1 (mark)
+	CDC_PAR_SPACE = 4  //!< Parity forced to 0 (space)
+};
+//@}
+
+//! \name USB CDC control signals
+//! spec 1.1 chapter 6.2.14
+//@{
+
+//! Control signal structure
+typedef struct usb_cdc_control_signal {
+	union {
+		le16_t value;
+		struct {
+			uint8_t dte_present;
+			uint8_t carrier_ctrl;
+		} modem;
+		struct {
+			uint8_t DTR : 1; //!< Data Terminal Ready
+			uint8_t RTS : 1; //!< Request To Send
+		} rs232;
+		struct {
+			uint8_t s108_2 : 1; //!< V.24 signal 108/2
+			uint8_t s105 : 1;   //!< V.24 signal 105
+		} v24;
+	};
+} usb_cdc_control_signal_t;
+
+//! \name Possible values in usb_cdc_control_signal_t
+//@{
+//! Carrier control for half duplex modems.
+//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS.
+//! The device ignores the value of this bit
+//! when operating in full duplex mode.
+#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1)
+//! Indicates to DCE if DTE is present or not.
+//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
+#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0)
+//@}
+//@}
+
+//! \name USB CDC notification message
+//@{
+
+typedef struct usb_cdc_notify_msg {
+	uint8_t bmRequestType;
+	uint8_t bNotification;
+	union {
+		le16_t wValue;
+		struct {
+			uint8_t low;
+			uint8_t high;
+		} wValueBytes;
+	};
+	union {
+		le16_t wIndex;
+		struct {
+			uint8_t low;
+			uint8_t high;
+		} wIndexBytes;
+	};
+	union {
+		le16_t wLength;
+		struct {
+			uint8_t low;
+			uint8_t high;
+		} wLengthBytes;
+	};
+} usb_cdc_notify_msg_t;
+
+//! \name USB CDC serial state
+//@{*
+
+//! UART State Bitmap (cdc spec 1.1 chapter 6.3.5)
+typedef union usb_cdc_uart_state {
+	le16_t value;
+	struct {
+		uint8_t bRxCarrier : 1;
+		uint8_t bTxCarrier : 1;
+		uint8_t bBreak : 1;
+		uint8_t bRingSignal : 1;
+		uint8_t bFraming : 1;
+		uint8_t bParity : 1;
+		uint8_t bOverRun;
+	} bitmap;
+	struct {
+		uint8_t bDCD : 1;
+		uint8_t bDSR : 1;
+		uint8_t bBreak : 1;
+		uint8_t bRingSignal : 1;
+		uint8_t bFraming : 1;
+		uint8_t bParity : 1;
+		uint8_t bOverRun;
+	} rs232;
+	struct {
+		uint8_t bS109 : 1; //!< V.24 signal 109
+		uint8_t bS106 : 1; //!< V.24 signal 106
+		uint8_t bBreak : 1;
+		uint8_t bRingSignal : 1;
+		uint8_t bFraming : 1;
+		uint8_t bParity : 1;
+		uint8_t bOverRun;
+	} v24;
+} usb_cdc_uart_state_t;
+
+//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5)
+typedef struct usb_cdc_notify_serial_state {
+	usb_cdc_notify_msg_t     header;
+	union usb_cdc_uart_state state;
+} usb_cdc_notify_serial_state_t;
+
+//! \name Possible values in usb_cdc_notify_serial_state_t
+//@{
+#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1 << 0))
+#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1 << 1))
+#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1 << 2))
+#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1 << 3))
+#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1 << 4))
+#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1 << 5))
+#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1 << 6))
+//@}
+//! @}
+
+//! @}
+
+COMPILER_PACK_RESET()
+
+//! @}
+
+/**
+ * \brief Fill a CDC SetLineCoding request
+ * \param[out] req   Pointer to the request to fill
+ * \param[in]  iface Interface Number
+ */
+static inline void usb_fill_SetLineCoding_req(struct usb_req *req, uint8_t iface)
+{
+	req->bmRequestType = 0x21;
+	req->bRequest      = USB_REQ_CDC_SET_LINE_CODING;
+	req->wValue        = 0;
+	req->wIndex        = iface;
+	req->wLength       = sizeof(usb_cdc_line_coding_t);
+}
+
+/**
+ * \brief Fill a CDC SetControlLineState request
+ * \param[out] req   Pointer to the request to fill
+ * \param[in]  iface Interface Number
+ * \param[in]  ctrl  Control Signal Bitmap
+ */
+static inline void usb_fill_SetControlLineState_req(struct usb_req *req, uint8_t iface, uint16_t ctrl)
+{
+	req->bmRequestType = 0x21;
+	req->bRequest      = USB_REQ_CDC_SET_CONTROL_LINE_STATE;
+	req->wValue        = ctrl;
+	req->wIndex        = iface;
+	req->wLength       = 0;
+}
+
+#endif // _USB_PROTOCOL_CDC_H_
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/device/usbdc.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/device/usbdc.c
new file mode 100644
index 000000000..3cfd7bcb4
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/device/usbdc.c
@@ -0,0 +1,1027 @@
+/**
+ * \file
+ *
+ * \brief USB Device Stack Core Layer Implementation.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "usbdc.h"
+
+#define USBDC_VERSION 0x00000001u
+
+/**
+ * \brief USB Device Core Sof Handler
+ */
+struct usbdc_sof_handler {
+	struct usbdc_sof_handler *next;
+	usbdc_sof_cb_t            cb;
+};
+
+/**
+ * \brief USB Device Core Request Handler
+ */
+struct usbdc_req_handler {
+	struct usbdc_req_handler *next;
+	usbdc_req_cb_t            cb;
+};
+
+/**
+ * \brief USB Device Core Change Handler
+ */
+struct usbdc_change_handler {
+	struct usbdc_change_handler *next;
+	usbdc_change_cb_t            cb;
+};
+
+/**
+ * \brief USB Device Core Handler
+ */
+struct usbdc_handlers {
+	struct list_descriptor sof_list;
+	struct list_descriptor req_list;
+	struct list_descriptor change_list;
+};
+
+/**
+ * \brief USB Device Core Driver Structure
+ */
+struct usbdc_driver {
+	/** Pointer to descriptions of descriptors. */
+	struct usbdc_descriptors desces;
+	/** Callback handlers. */
+	struct usbdc_handlers handlers;
+	/** list of function drivers. */
+	struct list_descriptor func_list;
+	/** Control buffer. */
+	uint8_t *ctrl_buf;
+	/** Device status. */
+	uint16_t status;
+	/** Device state. */
+	uint8_t state;
+	/** Configuration value. */
+	uint8_t cfg_value;
+	/** Control endpoint size. */
+	uint8_t ctrl_size;
+	/** Alternate interface used map */
+	uint8_t ifc_alt_map;
+};
+
+/**
+ * \brief USB Device Core Driver Instance
+ */
+static struct usbdc_driver usbdc;
+
+/**
+ * \brief Process the GetDeviceDescriptor request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_dev_desc(const uint8_t ep, struct usb_req *req)
+{
+	uint8_t *dev_desc = NULL;
+	uint16_t length   = req->wLength;
+	if (length > 0x12) {
+		length = 0x12;
+	}
+#if CONF_USBD_HS_SP
+	if (usb_d_get_speed() == USB_SPEED_HS && usbdc.desces.hs) {
+		dev_desc = usb_find_desc(usbdc.desces.hs->sod, usbdc.desces.hs->eod, USB_DT_DEVICE);
+	} else {
+		/* Obtain descriptor from FS descriptors */
+	}
+#endif
+	if (!dev_desc) {
+		dev_desc = usb_find_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, USB_DT_DEVICE);
+	}
+	if (!dev_desc) {
+		return false;
+	}
+	if (ERR_NONE != usbdc_xfer(ep, dev_desc, length, false)) {
+		return false;
+	}
+	return true;
+}
+
+/**
+ * \brief Process the GetConfigurationDescriptor request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_cfg_desc(const uint8_t ep, struct usb_req *req)
+{
+	uint8_t *cfg_desc = NULL;
+	uint16_t total_len;
+	uint16_t length   = req->wLength;
+	uint8_t  index    = req->wValue & 0x00FF;
+	bool     need_zlp = !(length & (usbdc.ctrl_size - 1));
+
+#if CONF_USBD_HS_SP
+	if (usb_d_get_speed() == USB_SPEED_HS && usbdc.desces.hs) {
+		cfg_desc = usb_find_cfg_desc(usbdc.desces.hs->sod, usbdc.desces.hs->eod, index + 1);
+	} else {
+		/* Obtain descriptor from FS descriptors */
+	}
+#endif
+	if (!cfg_desc) {
+		cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index + 1);
+	}
+	if (NULL == cfg_desc) {
+		return false;
+	}
+	total_len = usb_cfg_desc_total_len(cfg_desc);
+	if (length <= total_len) {
+		need_zlp = false;
+	} else {
+		length = total_len;
+	}
+	if (ERR_NONE != usbdc_xfer(ep, cfg_desc, length, need_zlp)) {
+		return false;
+	}
+	return true;
+}
+
+/**
+ * \brief Process the GetStringDescriptor request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_str_desc(const uint8_t ep, struct usb_req *req)
+{
+	uint8_t *str_desc;
+	uint16_t length   = req->wLength;
+	uint8_t  index    = req->wValue & 0x00FF;
+	bool     need_zlp = !(length & (usbdc.ctrl_size - 1));
+	/* All string are in default descriptors block: FS/LS */
+	str_desc = usb_find_str_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index);
+	if (NULL == str_desc) {
+		return false;
+	}
+	if (length <= str_desc[0]) {
+		need_zlp = false;
+	} else {
+		length = str_desc[0];
+	}
+	if (ERR_NONE != usbdc_xfer(ep, str_desc, length, need_zlp)) {
+		return false;
+	}
+	return true;
+}
+
+#if CONF_USBD_HS_SP
+/**
+ * \brief Process the GetDeviceQualifierDescriptor request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_devqual_desc(const uint8_t ep, struct usb_req *req)
+{
+	uint8_t *dev_desc = NULL;
+	uint16_t length   = req->wLength;
+	if (length > 0x12) {
+		length = 0x12;
+	}
+	if (usb_d_get_speed() == USB_SPEED_HS && usbdc.desces.hs) {
+		dev_desc = usb_find_desc(usbdc.desces.hs->sod, usbdc.desces.hs->eod, USB_DT_DEVICE_QUALIFIER);
+	}
+	if (!dev_desc) {
+		dev_desc = usb_find_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, USB_DT_DEVICE_QUALIFIER);
+	}
+	if (!dev_desc) {
+		return false;
+	}
+	if (ERR_NONE != usbdc_xfer(ep, dev_desc, length, false)) {
+		return false;
+	}
+	return true;
+}
+
+/**
+ * \brief Process the GetOtherSpeedConfigurationDescriptor request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_othspdcfg_desc(const uint8_t ep, struct usb_req *req)
+{
+	uint8_t *cfg_desc = NULL;
+	uint16_t total_len;
+	uint16_t length   = req->wLength;
+	uint8_t  index    = req->wValue & 0x00FF;
+	bool     need_zlp = !(length & (usbdc.ctrl_size - 1));
+
+	if (usb_d_get_speed() == USB_SPEED_HS && usbdc.desces.hs) {
+		cfg_desc = usb_find_othspdcfg_desc(usbdc.desces.hs->sod, usbdc.desces.hs->eod, index + 1);
+	} else {
+		/* Obtain descriptor from FS descriptors */
+	}
+	if (!cfg_desc) {
+		cfg_desc = usb_find_othspdcfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index + 1);
+	}
+	if (NULL == cfg_desc) {
+		return false;
+	}
+	total_len = usb_cfg_desc_total_len(cfg_desc);
+	if (length <= total_len) {
+		need_zlp = false;
+	} else {
+		length = total_len;
+	}
+	if (ERR_NONE != usbdc_xfer(ep, cfg_desc, length, need_zlp)) {
+		return false;
+	}
+	return true;
+}
+#endif
+
+/**
+ * \brief Process the GetDescriptor request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_desc_req(const uint8_t ep, struct usb_req *req)
+{
+	uint8_t type = (uint8_t)(req->wValue >> 8);
+	switch (type) {
+	case USB_DT_DEVICE:
+		return usbdc_get_dev_desc(ep, req);
+	case USB_DT_CONFIG:
+		return usbdc_get_cfg_desc(ep, req);
+#if CONF_USBD_HS_SP
+	case USB_DT_DEVICE_QUALIFIER:
+		return usbdc_get_devqual_desc(ep, req);
+	case USB_DT_OTHER_SPEED_CONFIG:
+		return usbdc_get_othspdcfg_desc(ep, req);
+#endif
+	case USB_DT_STRING:
+		return usbdc_get_str_desc(ep, req);
+	default:
+		break;
+	}
+	return false;
+}
+
+/**
+ * \brief Process the GetStatus request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_status_req(const uint8_t ep, const struct usb_req *req)
+{
+	int32_t st;
+	(void)ep;
+
+	switch (req->bmRequestType & USB_REQT_RECIP_MASK) {
+	case USB_REQT_RECIP_DEVICE:
+	case USB_REQT_RECIP_INTERFACE:
+		st = 0;
+		break;
+	case USB_REQT_RECIP_ENDPOINT:
+		st = usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_GET);
+		if (st < 0) {
+			return false;
+		}
+		st = st & 0x1;
+		break;
+	default:
+		return false;
+	}
+	memcpy(usbdc.ctrl_buf, &st, 2);
+	usbdc_xfer(ep, usbdc.ctrl_buf, 2, false);
+	return true;
+}
+
+/**
+ * \brief Process the standard Get Interface
+ * \param[in] req Point to usb request struct.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_interface(struct usb_req *req)
+{
+	struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head;
+	int32_t              rc;
+
+	if (!(usbdc.ifc_alt_map & (1 << req->wIndex))) {
+		/* Return 0 if alternate is not used */
+		usbdc.ctrl_buf[0] = 0;
+		usbdc_xfer(0, usbdc.ctrl_buf, 1, false);
+		return true;
+	}
+	/* Check function drivers only if alternate is used */
+	while (NULL != func) {
+		if (0 > (rc = func->ctrl(func, USBDF_GET_IFACE, req))) {
+			func = func->next;
+		} else {
+			usbdc.ctrl_buf[0] = (uint8_t)rc;
+			usbdc_xfer(0, usbdc.ctrl_buf, 1, false);
+			return true;
+		}
+	}
+	return false;
+}
+
+/**
+ * \brief Process the standard Get request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_get_req(const uint8_t ep, struct usb_req *req)
+{
+	switch (req->bRequest) {
+	case USB_REQ_GET_DESC:
+		return usbdc_get_desc_req(ep, req);
+	case USB_REQ_GET_CONFIG:
+		*(uint8_t *)usbdc.ctrl_buf = usbdc.cfg_value;
+		usbdc_xfer(ep, usbdc.ctrl_buf, 1, false);
+		return true;
+	case USB_REQ_GET_STATUS:
+		return usbdc_get_status_req(ep, req);
+	case USB_REQ_GET_INTERFACE:
+		return usbdc_get_interface(req);
+	default:
+		return false;
+	}
+}
+
+/**
+ * \brief Process the standard ClearFeature request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req)
+{
+	(void)ep;
+	switch (req->bmRequestType & USB_REQT_RECIP_MASK) {
+	case USB_REQT_RECIP_ENDPOINT:
+		if (req->wLength != 0) {
+			return false;
+		}
+		usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR);
+		usbdc_xfer(ep, NULL, 0, true);
+		return true;
+	default:
+		return false;
+	}
+}
+
+/**
+ * \brief Process the standard SetFeature request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req)
+{
+	(void)ep;
+	switch (req->bmRequestType & USB_REQT_RECIP_MASK) {
+	case USB_REQT_RECIP_ENDPOINT:
+		if (req->wLength != 0) {
+			return false;
+		}
+		usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET);
+		usbdc_xfer(ep, NULL, 0, true);
+		return true;
+	default:
+		return false;
+	}
+}
+
+/**
+ * \brief Unconfig, close all interfaces
+ */
+static void usbdc_unconfig(void)
+{
+	struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head;
+	while (NULL != func) {
+		func->ctrl(func, USBDF_DISABLE, NULL);
+		func = func->next;
+	}
+}
+
+/**
+ * \brief Apply Set Configuration Value
+ * \param[in] cfg_value Configuration Value
+ * \retval true Set configuration OK.
+ * \retval false Request error.
+ */
+static bool usbdc_set_config(uint8_t cfg_value)
+{
+	struct usbd_descriptors desc;
+	struct usbdf_driver *   func;
+	uint8_t *               cfg_desc = NULL;
+	uint16_t                total_len;
+	uint8_t                 last_iface = 0xFF;
+
+	if (cfg_value == 0) {
+		usbdc_unconfig();
+		return true;
+	}
+
+#if CONF_USBD_HS_SP
+	if (usb_d_get_speed() == USB_SPEED_HS && usbdc.desces.hs) {
+		cfg_desc = usb_find_cfg_desc(usbdc.desces.hs->sod, usbdc.desces.hs->eod, cfg_value);
+	} else {
+		/* Obtain descriptor from FS descriptors */
+	}
+#endif
+	if (!cfg_desc) {
+		cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, cfg_value);
+	}
+	if (NULL == cfg_desc) {
+		return false;
+	}
+
+	total_len = usb_cfg_desc_total_len(cfg_desc);
+	desc.eod  = cfg_desc + total_len;
+	desc.sod  = usb_find_desc(cfg_desc, desc.eod, USB_DT_INTERFACE);
+
+	while (NULL != desc.sod) {
+		/* Apply very first alternate setting (must be 0) of the interface */
+		if (last_iface != desc.sod[2] /* bInterfaceNumber */) {
+			last_iface = desc.sod[2];
+			func       = (struct usbdf_driver *)usbdc.func_list.head;
+			while (NULL != func) {
+				if (func->ctrl(func, USBDF_ENABLE, &desc)) {
+					func = func->next;
+				} else {
+					break;
+				}
+			}
+		}
+		desc.sod = usb_desc_next(desc.sod);
+		desc.sod = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE);
+	}
+	return true;
+}
+
+/**
+ * \brief Apply the USB device address
+ * \param[in] addr address to be set.
+ */
+static void usbdc_set_address(uint8_t addr)
+{
+	usb_d_set_address(addr);
+}
+
+/**
+ * \brief Process the standard Set Interface
+ * \param[in] alt_set Alternate Setting.
+ * \param[in] ifc_id Interface Index.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_set_interface(uint16_t alt_set, uint16_t ifc_id)
+{
+	struct usbd_descriptors desc;
+	struct usbdf_driver *   func;
+	uint8_t *               ifc = NULL;
+
+#if CONF_USBD_HS_SP
+	if (usb_d_get_speed() == USB_SPEED_HS && usbdc.desces.hs) {
+		ifc = usb_find_cfg_desc(usbdc.desces.hs->sod, usbdc.desces.hs->eod, usbdc.cfg_value);
+	} else {
+		/* Obtain descriptor from FS descriptors */
+	}
+#endif
+	if (!ifc) {
+		ifc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, usbdc.cfg_value);
+	}
+	if (NULL == ifc) {
+		return false;
+	}
+	desc.sod = ifc;
+	desc.eod = ifc + usb_cfg_desc_total_len(ifc);
+
+	if (NULL == (ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE))) {
+		return false;
+	}
+
+	while (ifc[2] != ifc_id || ifc[3] != alt_set) {
+		desc.sod = usb_desc_next(desc.sod);
+		ifc      = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE);
+		if (NULL == ifc) {
+			return false;
+		}
+	}
+
+	desc.sod = ifc;
+	func     = (struct usbdf_driver *)usbdc.func_list.head;
+
+	while (NULL != func) {
+		if (func->ctrl(func, USBDF_DISABLE, &desc)) {
+			func = func->next;
+		} else if (ERR_NONE == func->ctrl(func, USBDF_ENABLE, &desc)) {
+			if (alt_set) {
+				/* Alternate settings are used from now on */
+				usbdc.ifc_alt_map |= 1 << ifc_id;
+			}
+			usbdc_xfer(0, NULL, 0, 0);
+			return true;
+		} else {
+			return false;
+		}
+	}
+
+	return false;
+}
+
+/**
+ * \brief Process the standard Set request
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_set_req(const uint8_t ep, struct usb_req *req)
+{
+	switch (req->bRequest) {
+	case USB_REQ_SET_ADDRESS:
+		return (ERR_NONE == usbdc_xfer(ep, NULL, 0, true));
+	case USB_REQ_SET_CONFIG:
+		if (!usbdc_set_config(req->wValue)) {
+			return false;
+		}
+		return (ERR_NONE == usbdc_xfer(ep, NULL, 0, true));
+	case USB_REQ_CLEAR_FTR:
+		return usbdc_clear_ftr_req(ep, req);
+	case USB_REQ_SET_FTR:
+		return usbdc_set_ftr_req(ep, req);
+	case USB_REQ_SET_INTERFACE:
+		return usbdc_set_interface(req->wValue, req->wIndex);
+	default:
+		return false;
+	}
+}
+
+/** Invoke all registered SOF callbacks. */
+static void usbdc_sof_notify(void)
+{
+	struct usbdc_sof_handler *sof = (struct usbdc_sof_handler *)usbdc.handlers.sof_list.head;
+
+	while (sof != NULL) {
+		if (NULL != sof->cb) {
+			sof->cb();
+		}
+		sof = sof->next;
+	}
+}
+
+/** Invoke all registered Change notification callbacks. */
+static void usbdc_change_notify(enum usbdc_change_type change, uint32_t value)
+{
+	struct usbdc_change_handler *cg = (struct usbdc_change_handler *)usbdc.handlers.change_list.head;
+
+	while (cg != NULL) {
+		if (NULL != cg->cb) {
+			cg->cb(change, value);
+		}
+		cg = cg->next;
+	}
+}
+
+/** Invoke all registered request callbacks until request handled. */
+static int32_t usbdc_request_handler(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage)
+{
+	struct usbdc_req_handler *h = (struct usbdc_req_handler *)usbdc.handlers.req_list.head;
+	int32_t                   rc;
+
+	while (h != NULL) {
+		if (NULL != h->cb) {
+			rc = h->cb(ep, req, stage);
+			if (0 == rc) {
+				return true;
+			} else if (ERR_NOT_FOUND != rc) {
+				return -1;
+			}
+		}
+		h = h->next;
+	}
+	return false;
+}
+
+/**
+ * \brief Callback invoked on USB device SOF
+ */
+static void usbd_sof_cb(void)
+{
+	usbdc_sof_notify();
+}
+
+/**
+ * \brief Callback invoked when control request is received
+ * \param[in] ep Endpoint address.
+ * \param[in] req Pointer to the request.
+ * \return Operation status.
+ * \retval true Request is handled OK.
+ * \retval false Request not supported.
+ */
+static bool usbdc_cb_ctl_req(const uint8_t ep, struct usb_req *req)
+{
+	switch (usbdc_request_handler(ep, req, USB_SETUP_STAGE)) {
+	case true:
+		return true;
+	case -1:
+		return false;
+	default:
+		break;
+	}
+
+	// STD request handling
+	switch (req->bmRequestType & (USB_REQT_TYPE_MASK | USB_REQT_DIR_IN)) {
+	case USB_REQT_TYPE_STANDARD:
+		return usbdc_set_req(ep, req);
+	case (USB_REQT_TYPE_STANDARD | USB_REQT_DIR_IN):
+		return usbdc_get_req(ep, req);
+	default:
+		return false;
+	}
+}
+
+/**
+ * \brief When control status stage is end
+ * \param[in] req Pointer to the request.
+ */
+static void usbdc_ctrl_status_end(const struct usb_req *req)
+{
+	if (req->bmRequestType != USB_REQT_TYPE_STANDARD) {
+		return;
+	}
+	switch (req->bRequest) {
+	case USB_REQ_SET_CONFIG:
+		usbdc.cfg_value = req->wValue;
+		usbdc.state     = req->wValue ? USBD_S_CONFIG : USBD_S_ADDRESS;
+		usbdc_change_notify(USBDC_C_STATE, usbdc.state);
+		break;
+	case USB_REQ_SET_ADDRESS:
+		usbdc_set_address(req->wValue);
+		usbdc.state = req->wValue ? USBD_S_ADDRESS : USBD_S_DEFAULT;
+		usbdc_change_notify(USBDC_C_STATE, usbdc.state);
+		break;
+	default:
+		break;
+	}
+}
+
+/**
+ * \brief When control data stage is end
+ * \param[in] req Pointer to the request.
+ */
+static bool usbdc_ctrl_data_end(struct usb_req *req)
+{
+	usbdc_request_handler(0, req, USB_DATA_STAGE);
+	return false;
+}
+
+/**
+ * \brief Callback invoked when control data done or status done
+ * \param[in] ep Endpoint number with direction on bit 8.
+ * \param[in] code Status code.
+ * \param[in] req Pointer to the control setup request.
+ * \return Data has error or not.
+ * \retval true There is data error, protocol error.
+ * \retval false There is no data error.
+ */
+static bool usbdc_cb_ctl_done(const uint8_t ep, const enum usb_xfer_code code, struct usb_req *req)
+{
+	(void)ep;
+
+	switch (code) {
+	case USB_XFER_DONE:
+		usbdc_ctrl_status_end(req);
+		break;
+	case USB_XFER_DATA:
+		return usbdc_ctrl_data_end(req);
+	default:
+		break;
+	}
+	return false;
+}
+
+/**
+ * \brief USB Device Core Reset
+ */
+void usbdc_reset(void)
+{
+	usbdc_unconfig();
+
+	usbdc.state       = USBD_S_DEFAULT;
+	usbdc.cfg_value   = 0;
+	usbdc.ifc_alt_map = 0;
+
+	// Setup EP0
+	usb_d_ep_deinit(0);
+	usb_d_ep0_init(usbdc.ctrl_size);
+	usb_d_ep_register_callback(0, USB_D_EP_CB_SETUP, (FUNC_PTR)usbdc_cb_ctl_req);
+	usb_d_ep_register_callback(0, USB_D_EP_CB_XFER, (FUNC_PTR)usbdc_cb_ctl_done);
+	usb_d_ep_enable(0);
+}
+
+/**
+ * \brief Callback invoked on USB device events
+ * \param[in] ev Event code.
+ * \param[in] param Event parameter for event handling.
+ */
+static void usbd_event_cb(const enum usb_event ev, const uint32_t param)
+{
+	(void)param;
+
+	switch (ev) {
+	case USB_EV_VBUS:
+		usbdc_change_notify(USBDC_C_CONN, param);
+		break;
+
+	case USB_EV_RESET:
+		usbdc_reset();
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * \brief Issue USB device transfer
+ */
+int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp)
+{
+	struct usb_d_transfer xfer = {(uint8_t *)buf, size, ep, zlp};
+	return usb_d_ep_transfer(&xfer);
+}
+
+/**
+ * \brief Register the handler
+ */
+void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h)
+{
+	switch (type) {
+	case USBDC_HDL_SOF:
+		list_insert_at_end(&usbdc.handlers.sof_list, (void *)h);
+		break;
+	case USBDC_HDL_REQ:
+		list_insert_at_end(&usbdc.handlers.req_list, (void *)h);
+		break;
+	case USBDC_HDL_CHANGE:
+		list_insert_at_end(&usbdc.handlers.change_list, (void *)h);
+		break;
+	default:
+		break;
+	}
+}
+
+/**
+ * \brief Unregister the handler
+ */
+void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h)
+{
+	switch (type) {
+	case USBDC_HDL_SOF:
+		list_delete_element(&usbdc.handlers.sof_list, (void *)h);
+		break;
+	case USBDC_HDL_REQ:
+		list_delete_element(&usbdc.handlers.req_list, (void *)h);
+		break;
+	case USBDC_HDL_CHANGE:
+		list_delete_element(&usbdc.handlers.change_list, (void *)h);
+		break;
+	default:
+		break;
+	}
+}
+
+/**
+ * \brief Initialize the USB device core driver
+ */
+int32_t usbdc_init(uint8_t *ctrl_buf)
+{
+	ASSERT(ctrl_buf);
+
+	int32_t rc;
+
+	rc = usb_d_init();
+	if (rc < 0) {
+		return rc;
+	}
+
+	memset(&usbdc, 0, sizeof(usbdc));
+	usbdc.ctrl_buf = ctrl_buf;
+	usb_d_register_callback(USB_D_CB_SOF, (FUNC_PTR)usbd_sof_cb);
+	usb_d_register_callback(USB_D_CB_EVENT, (FUNC_PTR)usbd_event_cb);
+
+	return 0;
+}
+
+/**
+ * \brief De-initialize the USB device core driver
+ */
+int32_t usbdc_deinit(void)
+{
+	usb_d_deinit();
+	return 0;
+}
+
+/**
+ * \brief Register/unregister function support of a USB device function
+ *
+ * Must be invoked when USB device is stopped.
+ */
+void usbdc_register_function(struct usbdf_driver *func)
+{
+	list_insert_at_end(&usbdc.func_list, func);
+}
+
+/**
+ * \brief Unregister function support of a USB device function
+ *
+ * Must be invoked when USB device is stopped.
+ */
+void usbdc_unregister_function(struct usbdf_driver *func)
+{
+	list_delete_element(&usbdc.func_list, func);
+}
+
+/**
+ * \brief Validate the descriptor
+ */
+int32_t usbdc_validate_desces(struct usbd_descriptors *desces)
+{
+	uint8_t *sod, *eod;
+	if (desces == NULL) {
+		return ERR_NOT_FOUND;
+	}
+	sod = usb_find_desc(desces->sod, desces->eod, USB_DT_DEVICE);
+	if (sod == NULL) {
+		return ERR_BAD_DATA;
+	}
+	sod = usb_find_desc(desces->sod, desces->eod, USB_DT_CONFIG);
+	if (sod == NULL) {
+		return ERR_BAD_DATA;
+	}
+	eod = sod + usb_cfg_desc_total_len(sod);
+	if (eod > desces->eod) {
+		return ERR_BAD_DATA;
+	}
+	return 0;
+}
+
+/**
+ * \brief Validate the descriptor
+ */
+int32_t usbdc_check_desces(struct usbdc_descriptors *desces)
+{
+#if CONF_USBD_HS_SP
+	int32_t rc;
+	if (desces->hs == NULL && desces->ls_fs == NULL) {
+		return ERR_NOT_FOUND;
+	}
+	if (desces->hs) {
+		rc = usbdc_validate_desces(desces->hs);
+		if (rc < 0) {
+			return rc;
+		}
+	}
+#endif
+	return usbdc_validate_desces(desces->ls_fs);
+}
+
+/**
+ * \brief Start the USB device driver with specific descriptors set
+ */
+int32_t usbdc_start(struct usbd_descriptors *desces)
+{
+	if (usbdc.state >= USBD_S_POWER) {
+		return ERR_BUSY;
+	}
+
+	if (desces) {
+		usbdc.desces.ls_fs = desces;
+#if CONF_USBD_HS_SP
+		usbdc.desces.hs = &desces[1];
+#endif
+	} else {
+		return ERR_BAD_DATA;
+	}
+
+	usbdc.ctrl_size = desces->sod[7];
+	usbdc.state     = USBD_S_POWER;
+	usb_d_enable();
+	return ERR_NONE;
+}
+
+/**
+ * \brief Stop the USB device driver
+ */
+int32_t usbdc_stop(void)
+{
+	usb_d_disable();
+	usbdc.state = USBD_S_OFF;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Attach the USB device to host
+ */
+void usbdc_attach(void)
+{
+	usb_d_attach();
+}
+
+/**
+ * \brief Detach the USB device from host
+ */
+void usbdc_detach(void)
+{
+	usb_d_detach();
+}
+
+/**
+ * \brief Send remote wakeup to host
+ */
+void usbdc_remotewakeup(void)
+{
+	usb_d_send_remotewakeup();
+	usbdc.state = USBD_S_POWER;
+}
+
+/**
+ * \brief Return USB Device endpoint0 buffer
+ */
+uint8_t *usbdc_get_ctrl_buffer(void)
+{
+	return usbdc.ctrl_buf;
+}
+
+/**
+ * \brief Return current USB state
+ */
+uint8_t usbdc_get_state(void)
+{
+	if (usbdc.state & USBD_S_SUSPEND) {
+		return USBD_S_SUSPEND;
+	}
+	return usbdc.state;
+}
+
+/**
+ * \brief Return version
+ */
+uint32_t usbdc_get_version(void)
+{
+	return USBDC_VERSION;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/device/usbdc.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/device/usbdc.h
new file mode 100644
index 000000000..f7419392d
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/device/usbdc.h
@@ -0,0 +1,249 @@
+/**
+ * \file
+ *
+ * \brief USB Device Stack Core Layer Definition.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _USB_USBDC_H_
+#define _USB_USBDC_H_
+
+#include "usb_includes.h"
+#include "usb_protocol.h"
+#include "hal_usb_device.h"
+#include "usbd_config.h"
+
+/** USB device states. */
+enum usbd_state {
+	USBD_S_OFF     = 0,
+	USBD_S_POWER   = 1,
+	USBD_S_DEFAULT = 2,
+	USBD_S_ADDRESS = 3,
+	USBD_S_CONFIG  = 4,
+	USBD_S_SUSPEND = 0x10
+};
+
+/** USB device core handler type. */
+enum usbdc_handler_type { USBDC_HDL_SOF, USBDC_HDL_REQ, USBDC_HDL_CHANGE };
+
+/** USB device core change notification type. */
+enum usbdc_change_type {
+	/** Change of connection, detected by vbus. */
+	USBDC_C_CONN,
+	/** Change of state, by RESET, SetAddress(), SetConfig(). */
+	USBDC_C_STATE,
+	/** Change of power. */
+	USBDC_C_POWER,
+	/** Change of remote wakeup setting. */
+	USBDC_C_REMOTE_WAKEUP
+};
+
+/** Power change. */
+enum usbdc_power_type { USBDC_ACTIVE, USBDC_SLEEP, USBDC_SUSPEND };
+
+/** USB device general function control code. */
+enum usbdf_control {
+	/** Enable the function.
+	 *  int32_t ctrl(usbdf, USBDF_ENABLE, struct usbd_descriptors *desc);
+	 *  Parameter holds interface descriptor and
+	 *  configuration descriptor end position.
+	 */
+	USBDF_ENABLE,
+	/** Disable the function.
+	 *  int32_t ctrl(usbdf, USBDF_DISABLE, struct usbd_descriptors *desc);
+	 *  Parameter holds interface descriptor and
+	 *  configuration descriptor end position.
+	 *  Input NULL to force disable the function anyway.
+	 */
+	USBDF_DISABLE,
+	/** Get interface alternate setting.
+	 *  int32_t ctrl(usbdf, USBDF_GET_IFACE, struct usb_req *req);
+	 *  Parameter holds interface number who should return
+	 *  the alternate setting.
+	 */
+	USBDF_GET_IFACE
+};
+
+/** Describes a list of USB descriptors. */
+struct usbd_descriptors {
+	/** Pointer to Start of Descriptors. */
+	uint8_t *sod;
+	/** Pointer to End of Descriptors. */
+	uint8_t *eod;
+};
+
+/** Describes the USB device core descriptors. */
+struct usbdc_descriptors {
+	struct usbd_descriptors *ls_fs;
+#if CONF_USBD_HS_SP
+	struct usbd_descriptors *hs;
+#endif
+};
+
+/** Describes a list of core handler descriptor. */
+struct usbdc_handler {
+	/** Pointer to next handler. */
+	struct usbdc_handler *next;
+	/** Pointer to handler function. */
+	FUNC_PTR func;
+};
+
+/** Forward declaration for USB device function driver. */
+struct usbdf_driver;
+
+/** SOF handling function. */
+typedef void (*usbdc_sof_cb_t)(void);
+
+/** REQ handling function. */
+typedef int32_t (*usbdc_req_cb_t)(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage);
+
+/** Change notification callback function. */
+typedef void (*usbdc_change_cb_t)(enum usbdc_change_type change, uint32_t value);
+
+/** Control function for USB device general function driver. */
+typedef int32_t (*usbdf_control_cb_t)(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param);
+
+/** USB device general function driver descriptor. */
+struct usbdf_driver {
+	/** Pointer to next function.*/
+	struct usbdf_driver *next;
+	/** Pointer to control function.*/
+	usbdf_control_cb_t ctrl;
+	/** Pointer to function driver specific data. */
+	void *func_data;
+};
+
+/**
+ * \brief Register the handler
+ * \param[in] type USB device core handler type.
+ * \param[in] h Pointer to usb device core handler.
+ */
+void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h);
+
+/**
+ * \brief Unregister the handler
+ * \param[in] type USB device core handler type.
+ * \param[in] h Pointer to usb device core handler.
+ */
+void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h);
+
+/**
+ * \brief Initialize the USB device core driver
+ * \param[in] ctrl_buf Pointer to a buffer to be used by usb device ctrl endpoint
+ *  Note: the size of ctrl_buf should not be less than the size of EP0
+ * \return Operation status.
+ */
+int32_t usbdc_init(uint8_t *ctrl_buf);
+
+/**
+ * \brief Deinitialize the USB device core driver
+ * \return Operation status.
+ */
+int32_t usbdc_deinit(void);
+
+/**
+ * \brief Register function support of a USB device function
+ * \param[in] func Pointer to usb device function driver structure
+ */
+void usbdc_register_function(struct usbdf_driver *func);
+
+/**
+ * \brief Unregister function support of a USB device function
+ * \param[in] func Pointer to usb device function driver structure
+ */
+void usbdc_unregister_function(struct usbdf_driver *func);
+
+/**
+ * \brief Validate the descriptors
+ * \param[in] desces Pointer to usb device core descriptors
+ * \return Operation status.
+ */
+int32_t usbdc_validate_desces(struct usbd_descriptors *desces);
+
+/**
+ * \brief Issue USB device data transfer
+ * \param[in] ep endpointer address.
+ * \param[in] buf Pointer to data transfer buffer.
+ * \param[in] size the size of data transfer.
+ * \param[in] zlp flag to indicate zero length packet.
+ * \return Operation status.
+ */
+int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp);
+
+/**
+ * \brief Start the USB device driver with specific descriptors set
+ * \param[in] desces Pointer to usb device core descriptors (FS/LS),
+ *                   or pointer to array of core descriptors (HS), the
+ *                   very first one includes device descriptor, FS/LS
+ *                   configuration descriptor, string descriptor, and
+ *                   may include device qualifier and other speed
+ *                   configuration descriptor; the second one includes
+ *                   high speed used descriptors.
+ *                   Note that string descriptor should be included in
+ *                   first place.
+ * \return Operation status.
+ */
+int32_t usbdc_start(struct usbd_descriptors *desces);
+
+/**
+ * \brief Stop the USB device driver
+ * \return Operation status.
+ */
+int32_t usbdc_stop(void);
+
+/**
+ * \brief Attach the USB device to host
+ */
+void usbdc_attach(void);
+
+/**
+ * \brief Detach the USB device from host
+ */
+void usbdc_detach(void);
+
+/**
+ * \brief Send remote wakeup to host
+ */
+void usbdc_remotewakeup(void);
+
+/**
+ * \brief Return USB device ctrl end pointer buffer start address
+ */
+uint8_t *usbdc_get_ctrl_buffer(void);
+
+/**
+ * \brief Return current USB state
+ */
+uint8_t usbdc_get_state(void);
+
+/**
+ * \brief Return version
+ */
+uint32_t usbdc_get_version(void);
+
+#endif /* USBDC_H_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_atmel.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_atmel.h
new file mode 100644
index 000000000..d7bbe596b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_atmel.h
@@ -0,0 +1,179 @@
+/**
+ * \file
+ *
+ * \brief All USB VIDs and PIDs from Atmel USB applications
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _USB_ATMEL_H_
+#define _USB_ATMEL_H_
+
+/**
+ * \defgroup usb_group USB Stack
+ *
+ * This stack includes the USB Device Stack, USB Host Stack and common
+ * definitions.
+ * @{
+ */
+
+//! @}
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_atmel_ids_group Atmel USB Identifiers
+ *
+ * This module defines Atmel PID and VIDs constants.
+ *
+ * @{
+ */
+
+//! \name Vendor Identifier assigned by USB org to ATMEL
+#define USB_VID_ATMEL 0x03EB
+
+//! \name Product Identifier assigned by ATMEL to AVR applications
+//! @{
+
+//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others.
+//! @{
+#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013
+#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017
+#define USB_PID_ATMEL_MEGA_CDC 0x2018
+#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019
+#define USB_PID_ATMEL_MEGA_MS 0x201A
+#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B
+#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C
+#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D
+#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E
+#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022
+#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023
+#define USB_PID_ATMEL_MEGA_MS_2 0x2029
+#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A
+#define USB_PID_ATMEL_MEGA_MS_3 0x2032
+#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050
+//! @}
+
+//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools.
+//! @{
+#define USB_PID_ATMEL_XPLAINED 0x2122
+#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A
+#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B
+//! @}
+
+//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=>
+//! @{
+#define USB_PID_ATMEL_UC3_ENUM 0x2300
+#define USB_PID_ATMEL_UC3_MS 0x2301
+#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302
+#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303
+#define USB_PID_ATMEL_UC3_HID 0x2304
+#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305
+#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306
+#define USB_PID_ATMEL_UC3_CDC 0x2307
+#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308
+#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx
+#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311
+#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312
+//! @}
+
+//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications
+//! @{
+#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400
+#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401
+#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402
+#define USB_PID_ATMEL_ASF_MSC 0x2403
+#define USB_PID_ATMEL_ASF_CDC 0x2404
+#define USB_PID_ATMEL_ASF_PHDC 0x2405
+#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406
+#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420
+#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421
+#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422
+#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423
+#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424
+#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425
+#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426
+#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430
+#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431
+#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432
+#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433
+#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434
+//! @}
+
+//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders
+//! Note, !!!! don't use this range for demos or examples !!!!
+//! @{
+#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6
+#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7
+#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8
+#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9
+#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA
+#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB
+#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC
+#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD
+#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE
+
+#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF
+#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0
+#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1
+#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2
+#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3
+#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4
+#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5
+#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6
+#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7
+#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8
+#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9
+#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA
+#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB
+#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC
+#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED
+#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE
+#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF
+#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0
+#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1
+#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2
+#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3
+#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4
+#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5
+#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6
+#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7
+#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8
+#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9
+#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA
+#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB
+// 2FFCh to 2FFFh used by C51 family products
+//! @}
+
+//! @}
+
+//! @}
+
+#endif // _USB_ATMEL_H_
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_debug.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_debug.h
new file mode 100644
index 000000000..b20c3564b
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_debug.h
@@ -0,0 +1,41 @@
+/**
+ * \file
+ *
+ * \brief USB Debug Files.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _USB_DEBUG_H_
+#define _USB_DEBUG_H_
+
+#define udbg_print(...)
+
+#endif
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_includes.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_includes.h
new file mode 100644
index 000000000..bcf99f763
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_includes.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief USB Include Header Files.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _USB_INCLUDES_H_
+#define _USB_INCLUDES_H_
+
+#ifdef USB_USER_INCLUDES
+
+#include "usb_user_includes.h"
+
+#else
+/* Include START headers */
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <utils.h>
+#include <utils_list.h>
+#include <utils_assert.h>
+#include <hal_atomic.h>
+
+typedef uint16_t le16_t;
+typedef uint32_t le32_t;
+typedef uint16_t be16_t;
+typedef uint32_t be32_t;
+
+#if (defined __GNUC__) || (defined __CC_ARM)
+#define is_constant(exp) __builtin_constant_p(exp)
+#else
+#define is_constant(exp) (0)
+#endif
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#if (defined __GNUC__)
+#define swap_u32(u32)                                                                                                  \
+	(is_constant(u32)                                                                                                  \
+	     ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))     \
+	     : ((uint32_t)__builtin_bswap32((uint32_t)(u32))))
+#else
+#define swap_u32(u32)                                                                                                  \
+	((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16)))
+#endif
+
+/** Get a value from/to LE16 data */
+#define LE16(x) (x)
+/** Get a value from/to LE32 data */
+#define LE32(x) (x)
+/** Get a value from/to BE16 data */
+#define BE16(x) swap_u16(x)
+/** Get a value from/to BE32 data */
+#define BE32(x) swap_u32(x)
+
+/** Get byte 0 for BE 16-bit value */
+#define BE16B0(a) ((uint8_t)((a) >> 8))
+/** Get byte 1 for BE 16-bit value */
+#define BE16B1(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for BE 32-bit value */
+#define BE32B0(a) ((uint8_t)((a) >> 24))
+/** Get byte 1 for BE 32-bit value */
+#define BE32B1(a) ((uint8_t)((a) >> 16))
+/** Get byte 2 for BE 32-bit value */
+#define BE32B2(a) ((uint8_t)((a) >> 8))
+/** Get byte 3 for BE 32-bit value */
+#define BE32B3(a) ((uint8_t)((a) >> 0))
+
+/** Get byte 0 for LE 16-bit value */
+#define LE16B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 16-bit value */
+#define LE16B1(a) ((uint8_t)((a) >> 8))
+
+/** Get byte 0 for LE 32-bit value */
+#define LE32B0(a) ((uint8_t)((a) >> 0))
+/** Get byte 1 for LE 32-bit value */
+#define LE32B1(a) ((uint8_t)((a) >> 8))
+/** Get byte 2 for LE 32-bit value */
+#define LE32B2(a) ((uint8_t)((a) >> 16))
+/** Get byte 3 for LE 32-bit value */
+#define LE32B3(a) ((uint8_t)((a) >> 24))
+
+#endif /* USB_USER_INCLUDES */
+
+#endif /* _USB_INCLUDES_H_ */
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_protocol.c b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_protocol.c
new file mode 100644
index 000000000..9f6323e93
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_protocol.c
@@ -0,0 +1,161 @@
+/**
+ * \file
+ *
+ * \brief USB protocol implementation.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#define CONF_NO_ASSERT_CHECK
+
+#include "usb_protocol.h"
+
+#ifdef CONF_NO_ASSERT_CHECK
+#define _param_error_check(cond)
+#define _desc_len_check()                                                                                              \
+	if (usb_desc_len(desc) < 2) {                                                                                      \
+		/* Encounter an invalid descriptor. */                                                                         \
+		return NULL;                                                                                                   \
+	}
+#else
+#define _param_error_check(cond) ASSERT(cond)
+#define _desc_len_check() ASSERT(usb_desc_len(desc) >= 2)
+#endif
+
+uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type)
+{
+	_param_error_check(desc && eof && (desc < eof));
+
+	while (desc < eof) {
+		_desc_len_check();
+		if (type == usb_desc_type(desc)) {
+			return desc;
+		}
+		desc = usb_desc_next(desc);
+	}
+	return NULL;
+}
+
+uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n)
+{
+	_param_error_check(desc && eof && (desc < eof));
+
+	while (desc < eof) {
+		_desc_len_check();
+		if (USB_DT_INTERFACE == usb_desc_type(desc)) {
+			if (iface_n != desc[2]) {
+				return desc;
+			}
+		}
+		desc = usb_desc_next(desc);
+	}
+	return eof;
+}
+
+uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof)
+{
+	_param_error_check(desc && eof && (desc < eof));
+
+	while (desc < eof) {
+		_desc_len_check();
+		if (USB_DT_INTERFACE == usb_desc_type(desc)) {
+			break;
+		}
+		if (USB_DT_ENDPOINT == usb_desc_type(desc)) {
+			return desc;
+		}
+		desc = usb_desc_next(desc);
+	}
+	return NULL;
+}
+
+uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value)
+{
+	_param_error_check(desc && eof && (desc < eof));
+
+	desc = usb_find_desc(desc, eof, USB_DT_CONFIG);
+	if (!desc) {
+		return NULL;
+	}
+	while (desc < eof) {
+		_desc_len_check();
+		if (desc[1] != USB_DT_CONFIG) {
+			break;
+		}
+		if (desc[5] == cfg_value) {
+			return desc;
+		}
+		desc = usb_cfg_desc_next(desc);
+	}
+	return NULL;
+}
+
+uint8_t *usb_find_othspdcfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value)
+{
+	_param_error_check(desc && eof && (desc < eof));
+
+	desc = usb_find_desc(desc, eof, USB_DT_OTHER_SPEED_CONFIG);
+	if (!desc) {
+		return NULL;
+	}
+	while (desc < eof) {
+		_desc_len_check();
+		if (desc[1] != USB_DT_OTHER_SPEED_CONFIG) {
+			break;
+		}
+		if (desc[5] == cfg_value) {
+			return desc;
+		}
+		desc = usb_cfg_desc_next(desc);
+	}
+	return NULL;
+}
+
+uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index)
+{
+	uint8_t i;
+
+	_param_error_check(desc && eof && (desc < eof));
+
+	for (i = 0; desc < eof;) {
+		desc = usb_find_desc(desc, eof, USB_DT_STRING);
+		if (desc) {
+			_desc_len_check();
+			if (i == str_index) {
+				return desc;
+			}
+			i++;
+			desc = usb_desc_next(desc);
+		} else {
+			return NULL;
+		}
+	}
+	return NULL;
+}
diff --git a/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_protocol.h b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_protocol.h
new file mode 100644
index 000000000..35e283369
--- /dev/null
+++ b/vendor/teknic/clear-core/ClearCore-library/libClearCore/usb/usb_protocol.h
@@ -0,0 +1,782 @@
+/**
+ * \file
+ *
+ * \brief USB protocol definitions.
+ *
+ * This file contains the USB definitions and data structures provided by the
+ * USB 2.0 specification.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _USB_PROTOCOL_H_
+#define _USB_PROTOCOL_H_
+
+#include "usb_includes.h"
+
+/**
+ * \ingroup usb_group
+ * \defgroup usb_protocol_group USB Protocol Definitions
+ *
+ * This module defines constants and data structures provided by the USB
+ * 2.0 specification.
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __CC_ARM
+#pragma anon_unions
+#endif
+
+/*! Value for field bcdUSB */
+#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */
+#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */
+
+/*! \name Generic definitions (Class, subclass and protocol)
+ */
+/*! @{ */
+#define USB_CLASS_NO (0x00)
+#define USB_SUBCLASS_NO (0x00)
+#define USB_PROTOCOL_NO (0x00)
+/*! @} */
+
+/*! \name IAD (Interface Association Descriptor) constants */
+/*! @{ */
+#define USB_CLASS_IAD (0xEF)
+#define USB_SUBCLASS_IAD (0x02)
+#define USB_PROTOCOL_IAD (0x01)
+/*! @} */
+
+/**
+ * \brief USB request data transfer direction (bmRequestType)
+ */
+#define USB_REQT_DIR_OUT (0 << 7)  /*!< Host to device */
+#define USB_REQT_DIR_H2D (0 << 7)  /*!< Host to device */
+#define USB_REQT_DIR_IN (1 << 7)   /*!< Device to host */
+#define USB_REQT_DIR_D2H (1 << 7)  /*!< Device to host */
+#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */
+
+/**
+ * \brief USB request types (bmRequestType)
+ */
+#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */
+#define USB_REQT_TYPE_CLASS (1 << 5)    /*!< Class-specific request */
+#define USB_REQT_TYPE_VENDOR (2 << 5)   /*!< Vendor-specific request */
+#define USB_REQT_TYPE_MASK (3 << 5)     /*!< Mask */
+
+/**
+ * \brief USB recipient codes (bmRequestType)
+ */
+#define USB_REQT_RECIP_DEVICE (0 << 0)    /*!< Recipient device */
+#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */
+#define USB_REQT_RECIP_ENDPOINT (2 << 0)  /*!< Recipient endpoint */
+#define USB_REQT_RECIP_OTHER (3 << 0)     /*!< Recipient other */
+#define USB_REQT_RECIP_MASK (0x1F)        /*!< Mask */
+
+/**
+ * \brief Standard USB control transfer stages.
+ */
+enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 };
+
+/**
+ * \brief Standard USB requests (bRequest)
+ */
+enum usb_req_code {
+	USB_REQ_GET_STATUS    = 0,
+	USB_REQ_CLEAR_FTR     = 1,
+	USB_REQ_SET_FTR       = 3,
+	USB_REQ_SET_ADDRESS   = 5,
+	USB_REQ_GET_DESC      = 6,
+	USB_REQ_SET_DESC      = 7,
+	USB_REQ_GET_CONFIG    = 8,
+	USB_REQ_SET_CONFIG    = 9,
+	USB_REQ_GET_INTERFACE = 10,
+	USB_REQ_SET_INTERFACE = 11,
+	USB_REQ_SYNCH_FRAME   = 12,
+	USB_REQ_SET_SEL       = 48,
+	USB_REQ_ISOCH_DELAY   = 49
+};
+
+/**
+ * \brief Standard USB device status flags
+ *
+ */
+enum usb_dev_status {
+	USB_DEV_STAT_BUS_POWERED  = 0,
+	USB_DEV_STAT_SELF_POWERED = 1,
+	USB_DEV_STAT_REMOTEWAKEUP = 2,
+	USB_DEV_STAT_U1_ENABLE    = 4,
+	USB_DEV_STAT_U2_ENABLE    = 8,
+	USB_DEV_STAT_LTM_ENABLE   = 16
+};
+
+/**
+ * \brief Standard USB Interface status flags
+ *
+ */
+enum usb_interface_status {
+	USB_IFACE_STAT_RESERVED       = 0,
+	USB_IFACE_STAT_REMOTEWAKE_CAP = 1,
+	USB_IFACE_STAT_REMOTEWAKE     = 2
+};
+
+/**
+ * \brief Standard USB endpoint status flags
+ *
+ */
+enum usb_endpoint_status { USB_EP_STAT_HALT = 1 };
+
+/**
+ * \brief Standard USB device feature flags
+ *
+ * \note valid for SetFeature request.
+ */
+enum usb_device_feature {
+	USB_DEV_FTR_REMOTE_WAKEUP    = 1, /*!< Remote wakeup enabled */
+	USB_DEV_FTR_TEST_MODE        = 2, /*!< USB test mode */
+	USB_DEV_FTR_OTG_B_HNP_ENABLE = 3,
+	USB_DEV_FTR_OTG_A_HNP_SP     = 4,
+	USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5,
+	USB_DEV_FTR_U1_ENABLE        = 48,
+	USB_DEV_FTR_U2_ENABLE        = 49,
+	USB_DEV_FTR_LTM_ENABLE       = 50
+};
+
+/**
+ * \brief Test Mode possible on HS USB device
+ *
+ * \note valid for USB_DEV_FTR_TEST_MODE request.
+ */
+enum usb_device_hs_test_mode {
+	USB_DEV_TEST_MODE_J            = 1,
+	USB_DEV_TEST_MODE_K            = 2,
+	USB_DEV_TEST_MODE_SE0_NAK      = 3,
+	USB_DEV_TEST_MODE_PACKET       = 4,
+	USB_DEV_TEST_MODE_FORCE_ENABLE = 5
+};
+
+/**
+ * \brief Standard Feature Selectors for Interface
+ */
+enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 };
+
+/**
+ * \brief Standard USB endpoint feature/status flags
+ */
+enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 };
+
+/**
+ * \brief Standard USB Test Mode Selectors
+ */
+enum usb_test_mode_selector {
+	USB_TEST_J            = 0x01,
+	USB_TEST_K            = 0x02,
+	USB_TEST_SE0_NAK      = 0x03,
+	USB_TEST_PACKET       = 0x04,
+	USB_TEST_FORCE_ENABLE = 0x05
+};
+
+/**
+ * \brief Standard USB descriptor types
+ */
+enum usb_descriptor_type {
+	USB_DT_DEVICE             = 1,
+	USB_DT_CONFIG             = 2,
+	USB_DT_STRING             = 3,
+	USB_DT_INTERFACE          = 4,
+	USB_DT_ENDPOINT           = 5,
+	USB_DT_DEVICE_QUALIFIER   = 6,
+	USB_DT_OTHER_SPEED_CONFIG = 7,
+	USB_DT_INTERFACE_POWER    = 8,
+	USB_DT_OTG                = 9,
+	USB_DT_DEBUG              = 10,
+	USB_DT_IAD                = 11,
+	USB_DT_BOS                = 15,
+	USB_DT_DEV_CAP            = 16,
+	USB_DT_SS_EP_COMPANION    = 48
+};
+
+/**
+ * \brief Capability types
+ */
+enum usb_capability_type {
+	USB_CAPT_WIRELESS     = 1,
+	USB_CAPT_2_0_EXT      = 2,
+	USB_CAPT_SUPER_SPEED  = 3,
+	USB_CAPT_CONTAINER_ID = 4
+};
+
+/**
+ * \brief USB 2.0 Extension attributes
+ */
+enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 };
+
+/**
+ * \brief USB SuperSpeed Capability attributes
+ */
+enum usb_ss_cap_attr { USB_SS_LTM_SP };
+
+/**
+ * \brief USB Speed Supports
+ */
+enum usb_speed_sp {
+	USB_SPEED_LOW_SP   = 1,
+	USB_SPEED_LS_SP    = 1,
+	USB_SPEED_FULL_SP  = 2,
+	USB_SPEED_FS_SP    = 2,
+	USB_SPEED_HIGH_SP  = 4,
+	USB_SPEED_HS_SP    = 4,
+	USB_SPEED_SUPER_SP = 8,
+	USB_SPEED_SS_SP    = 8
+};
+
+/**
+ * \brief Standard USB endpoint transfer types
+ */
+enum usb_ep_type {
+	USB_EP_TYPE_CONTROL     = 0x00,
+	USB_EP_TYPE_ISOCHRONOUS = 0x01,
+	USB_EP_TYPE_BULK        = 0x02,
+	USB_EP_TYPE_INTERRUPT   = 0x03,
+	USB_EP_TYPE_MASK        = 0x03u
+};
+
+/**
+ * \brief USB endpoint interrupt types
+ */
+enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u };
+
+/**
+ * \brief Standard USB endpoint synchronization types
+ */
+enum usb_ep_sync_type {
+	USB_EP_SYNC_T_NO       = 0x00u,
+	USB_EP_SYNC_T_ASYNC    = 0x02u,
+	USB_EP_SYNC_T_ADAPTIVE = 0x02u,
+	USB_EP_SYNC_T_SYNC     = 0x03u,
+	USB_EP_SYNC_T_MASK     = 0x03u
+};
+
+/**
+ * \brief Standard USB endpoint usage types
+ */
+enum usb_ep_usage_type {
+	USB_EP_USAGE_T_DATA          = 0x00u,
+	USB_EP_USAGE_T_FEEDBACK      = 0x01u,
+	USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u,
+	USB_EP_USAGE_T_MASK          = 0x03u
+};
+
+/**
+ * \brief Standard USB language IDs for string descriptors
+ */
+enum usb_langid {
+	USB_LANGID_EN_US = 0x0409 /*!< English (United States) */
+};
+
+/**
+ * \brief Mask selecting the index part of an endpoint address
+ */
+#define USB_EP_ADDR_MASK 0x0f
+/**
+ * \brief Endpoint transfer direction is IN
+ */
+#define USB_EP_DIR_IN 0x80
+/**
+ * \brief Endpoint transfer direction is OUT
+ */
+#define USB_EP_DIR_OUT 0x00
+
+/**
+ * \brief Maximum length in bytes of a USB descriptor
+ *
+ * The maximum length of a USB descriptor is limited by the 8-bit
+ * bLength field.
+ */
+#define USB_DESC_LEN_MAX 255
+
+/*
+ * 2-byte alignment requested for all USB structures.
+ */
+COMPILER_PACK_SET(1)
+
+/**
+ * \brief A USB Device SETUP request
+ *
+ * The data payload of SETUP packets always follows this structure.
+ */
+typedef struct usb_req {
+	uint8_t bmRequestType;
+	uint8_t bRequest;
+	union {
+		le16_t wValue;
+		struct {
+			uint8_t l;
+			uint8_t h;
+		} wValueBytes;
+	};
+	union {
+		le16_t wIndex;
+		struct {
+			uint8_t l;
+			uint8_t h;
+		} wIndexBytes;
+	};
+	union {
+		le16_t wLength;
+		struct {
+			uint8_t l;
+			uint8_t h;
+		} wLengthBytes;
+	};
+} usb_req_t;
+
+/**
+ * \brief Standard USB device descriptor structure
+ */
+typedef struct usb_dev_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  bcdUSB;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	le16_t  idVendor;
+	le16_t  idProduct;
+	le16_t  bcdDevice;
+	uint8_t iManufacturer;
+	uint8_t iProduct;
+	uint8_t iSerialNumber;
+	uint8_t bNumConfigurations;
+} usb_dev_desc_t;
+
+/**
+ * \brief Binary device Object Store (BOS) descriptor structure
+ */
+typedef struct usb_bos_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  wTotalLength;
+	uint8_t bNumDeviceCaps;
+} usb_bos_desc_t;
+
+/**
+ * \brief Device Capability Descriptor structure
+ */
+typedef struct usb_cap_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t Vars[1];
+} usb_cap_desc_t;
+
+/**
+ * \brief USB 2.0 Extension Descriptor structure
+ */
+typedef struct usb_2_0_ext {
+	uint8_t  bLength;
+	uint8_t  bDescriptorType;
+	uint8_t  bDevCapabilityType;
+	uint32_t bmAttributes;
+} usb_2_0_ext_t;
+
+/**
+ * \brief LPM Device Capabilities descriptor structure
+ */
+typedef struct usb_2_0_ext usb_lpm_cap_desc_t;
+
+/**
+ * \brief SuperSpeed USB Device Capability structure
+ */
+typedef struct usb_ss_cap_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t bmAttributes;
+	le16_t  wSpeedsSupported;
+	uint8_t bFunctionalitySupport;
+	uint8_t bU1DevExitLat;
+	uint8_t bU2DevExitLat;
+} usb_ss_cap_desc_t;
+
+/**
+ * \brief USB Container ID Descriptor structure
+ */
+typedef struct usb_container_id_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDevCapabilityType;
+	uint8_t bReserved;
+	uint8_t ContainerID[16];
+} usb_container_id_desc_t;
+
+/**
+ * \brief Standard USB device qualifier descriptor structure
+ *
+ * This descriptor contains information about the device when running at
+ * the "other" speed (i.e. if the device is currently operating at high
+ * speed, this descriptor can be used to determine what would change if
+ * the device was operating at full speed.)
+ */
+typedef struct usb_dev_qual_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  bcdUSB;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	uint8_t bNumConfigurations;
+	uint8_t bReserved;
+} usb_dev_qual_desc_t;
+
+/**
+ * \brief Standard USB configuration descriptor structure
+ */
+typedef struct usb_config_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	le16_t  wTotalLength;
+	uint8_t bNumInterfaces;
+	uint8_t bConfigurationValue;
+	uint8_t iConfiguration;
+	uint8_t bmAttributes;
+	uint8_t bMaxPower;
+} usb_config_desc_t;
+
+#define USB_CONFIG_ATTR_MUST_SET (1 << 7)      /*!< Must always be set */
+#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6)   /*!< Bus-powered */
+#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6)  /*!< Self-powered */
+#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */
+
+#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */
+
+/**
+ * \brief Standard USB association descriptor structure
+ */
+typedef struct usb_iad_desc {
+	uint8_t bLength;           /*!< Size of this descriptor in bytes */
+	uint8_t bDescriptorType;   /*!< Interface descriptor type */
+	uint8_t bFirstInterface;   /*!< Number of interface */
+	uint8_t bInterfaceCount;   /*!< value to select alternate setting */
+	uint8_t bFunctionClass;    /*!< Class code assigned by the USB */
+	uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */
+	uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */
+	uint8_t iFunction;         /*!< Index of string descriptor */
+} usb_iad_desc_t;
+
+/**
+ * \brief Standard USB interface descriptor structure
+ */
+typedef struct usb_iface_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bInterfaceNumber;
+	uint8_t bAlternateSetting;
+	uint8_t bNumEndpoints;
+	uint8_t bInterfaceClass;
+	uint8_t bInterfaceSubClass;
+	uint8_t bInterfaceProtocol;
+	uint8_t iInterface;
+} usb_iface_desc_t;
+
+/**
+ * \brief Standard USB endpoint descriptor structure
+ */
+typedef struct usb_ep_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bEndpointAddress;
+	uint8_t bmAttributes;
+	le16_t  wMaxPacketSize;
+	uint8_t bInterval;
+} usb_ep_desc_t;
+
+/**
+ * \brief SuperSpeed Endpoint Companion descriptor structure
+ */
+typedef struct usb_ss_ep_comp_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bMaxBurst;
+	uint8_t bmAttributes;
+	le16_t  wBytesPerInterval;
+} usb_ss_ep_comp_desc_t;
+
+/**
+ * \brief LPM Token bmAttributes structure
+ */
+typedef struct usb_lpm_attributes {
+	uint8_t bLinkState : 4;
+	uint8_t HIRD : 4;
+	uint8_t bRemoteWake : 1;
+	uint8_t Reserved : 2;
+} usb_lpm_attributes_t;
+
+/**
+ * \brief A standard USB string descriptor structure
+ */
+typedef struct usb_str_desc {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+} usb_str_desc_t;
+
+typedef struct usb_str_langid_desc {
+	usb_str_desc_t desc;
+	le16_t         string[1];
+} usb_str_langid_desc_t;
+
+COMPILER_PACK_RESET()
+
+/** \name Macros to build USB standard descriptors */
+/*@{*/
+
+/** Build bytes for USB device descriptor. */
+#define USB_DEV_DESC_BYTES(bcdUSB,                                                                                     \
+                           bDeviceClass,                                                                               \
+                           bDeviceSubClass,                                                                            \
+                           bDeviceProtocol,                                                                            \
+                           bMaxPacketSize0,                                                                            \
+                           idVendor,                                                                                   \
+                           idProduct,                                                                                  \
+                           bcdDevice,                                                                                  \
+                           iManufacturer,                                                                              \
+                           iProduct,                                                                                   \
+                           iSerialNumber,                                                                              \
+                           bNumConfigurations)                                                                         \
+	18,       /* bLength */                                                                                            \
+	    0x01, /* bDescriptorType: DEVICE */                                                                            \
+	    LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0,           \
+	    LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice),         \
+	    LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations
+
+#define USB_DEV_QUAL_DESC_BYTES(                                                                                       \
+    bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0, bNumConfigurations)                       \
+	10,                          /* bLength */                                                                         \
+	    USB_DT_DEVICE_QUALIFIER, /* bDescriptorType: DEVICE_QUALIFIER */                                               \
+	    LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0,           \
+	    bNumConfigurations, 0
+
+#define USB_DEV_DESC_LEN 18
+
+/** Build bytes for USB configuration descriptor. */
+#define USB_CONFIG_DESC_BYTES(                                                                                         \
+    wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower)                        \
+	9,        /* bLength */                                                                                            \
+	    0x02, /* bDescriptorType: CONFIGURATION */                                                                     \
+	    LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration,           \
+	    bmAttributes, bMaxPower
+
+#define USB_OTH_SPD_CFG_DESC_BYTES(                                                                                    \
+    wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower)                        \
+	9,                             /* bLength */                                                                       \
+	    USB_DT_OTHER_SPEED_CONFIG, /* bDescriptorType: OTH_SPD_CONFIGURATION */                                        \
+	    LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration,           \
+	    bmAttributes, bMaxPower
+
+#define USB_CONFIG_DESC_LEN 9
+
+/** Build bytes for USB IAD descriptor. */
+#define USB_IAD_DESC_BYTES(                                                                                            \
+    bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction)                 \
+	8,              /* bLength */                                                                                      \
+	    USB_DT_IAD, /* bDescriptorType */                                                                              \
+	    bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction
+
+#define USB_IAD_DESC_LEN 8
+
+/** Build bytes for USB interface descriptor. */
+#define USB_IFACE_DESC_BYTES(bInterfaceNumber,                                                                         \
+                             bAlternateSetting,                                                                        \
+                             bNumEndpoints,                                                                            \
+                             bInterfaceClass,                                                                          \
+                             bInterfaceSubClass,                                                                       \
+                             bInterfaceProtocol,                                                                       \
+                             iInterface)                                                                               \
+	9,        /* bLength */                                                                                            \
+	    0x04, /* bDescriptorType: INTERFACE */                                                                         \
+	    bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol,   \
+	    iInterface
+
+#define USB_IFACE_DESC_LEN 9
+
+/** Build bytes for USB endpoint descriptor. */
+#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval)                                 \
+	7,        /* bLength */                                                                                            \
+	    0x05, /* bDescriptorType: ENDPOINT */                                                                          \
+	    bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval
+
+#define USB_ENDP_DESC_LEN 7
+
+/*@}*/
+
+/** \brief Get a word (calculate by little endian 16-bit data)
+ *  \param[in] ptr Byte pointer to the address to get data
+ *  \return a 16-bit word
+ */
+static inline uint16_t usb_get_u16(const uint8_t *ptr)
+{
+	return (ptr[0] + (ptr[1] << 8));
+}
+
+/** \brief Get a double word (calculate by little endian 32-bit data)
+ *  \param[in] ptr Byte pointer to the address to get data
+ *  \return a 32-bit word
+ */
+static inline uint32_t usb_get_u32(const uint8_t *ptr)
+{
+	return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24));
+}
+
+/** \brief Get descriptor length
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \return descriptor length
+ */
+static inline uint8_t usb_desc_len(const uint8_t *desc)
+{
+	return desc[0];
+}
+
+/** \brief Get descriptor type
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \return descriptor type
+ */
+static inline uint8_t usb_desc_type(const uint8_t *desc)
+{
+	return desc[1];
+}
+
+/** \brief Get next USB descriptor
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \return Byte pointer to the next descriptor
+ */
+static inline uint8_t *usb_desc_next(uint8_t *desc)
+{
+	return (desc + usb_desc_len(desc));
+}
+
+/** \brief Get idVendor of USB Device Descriptor
+ *  \param[in] dev_desc Byte pointer to the descriptor start address
+ *  \return 16-bit idVendor value
+ */
+static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc)
+{
+	return usb_get_u16(dev_desc + 8);
+}
+
+/** \brief Get idProduct of USB Device Descriptor
+ *  \param[in] dev_desc Byte pointer to the descriptor start address
+ *  \return 16-bit idProduct value
+ */
+static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc)
+{
+	return usb_get_u16(dev_desc + 10);
+}
+
+/** \brief Get wTotalLength of USB Configuration Descriptor
+ *  \param[in] cfg_desc Byte pointer to the descriptor start address
+ *  \return 16-bit total length of configuration list
+ */
+static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc)
+{
+	return usb_get_u16(cfg_desc + 2);
+}
+
+/** \brief Get Next USB Descriptor After the Configuration Descriptors list
+ *  \param[in] cfg_desc Byte pointer to the descriptor start address
+ *  \return Byte pointer to descriptor after configuration end
+ */
+static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc)
+{
+	return (cfg_desc + usb_cfg_desc_total_len(cfg_desc));
+}
+
+/** \brief Find specific USB Descriptor by its type
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] type The descriptor type expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type);
+
+/** Get interface descriptor next to the specified one (by interface number)
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] iface_n The interface number to check
+ *  \return Pointer to the descriptor
+ *  \retval >= eof if not found
+ */
+uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n);
+
+/** Find endpoint descriptor, breaks if interface descriptor detected
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof);
+
+/** Find configuration descriptor by its configuration number
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] cfg_value The configure value expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value);
+
+/** Find other speed configuration descriptor by its configuration number
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] cfg_value The configure value expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_othspdcfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value);
+
+/** Find string descriptor by its index
+ *  \param[in] desc Byte pointer to the descriptor start address
+ *  \param[in] eof  Byte pointer to the descriptor end address
+ *  \param[in] str_index The string index expected
+ *  \return Pointer to the descriptor
+ *  \retval NULL if not found
+ */
+uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @} */
+
+#endif /* _USB_PROTOCOL_H_ */
diff --git a/vendor/teknic/clear-core/clearcore_system_diagram.pdf b/vendor/teknic/clear-core/clearcore_system_diagram.pdf
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+size 348810
diff --git a/vendor/teknic/clear-core/manual_install_instructions_arduino.pdf b/vendor/teknic/clear-core/manual_install_instructions_arduino.pdf
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index 000000000..4e999da67
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diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic sFoundation License.pdf b/vendor/teknic/clearpath-motor/Linux_Software/Teknic sFoundation License.pdf
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index 000000000..4fc2fa28e
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic sFoundation License.pdf	
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:0c3e8fb1e131739691777aa5cc910843c59a16b645368dc234357e6e9e27e21f
+size 69765
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/Install_DRV_SCRIPT.sh b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/Install_DRV_SCRIPT.sh
new file mode 100644
index 000000000..2f98c7456
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/Install_DRV_SCRIPT.sh
@@ -0,0 +1,65 @@
+#!/bin/bash
+# script MUST be executed inside of root terminal run ($ sudo su) to get there
+# the script MUST be executed from the directory it resides in (ExarKernelDriver)
+# ie
+# uname@machinename:.../ExarKernelDriver$
+if [ "$($PWD | sed 's/^.*\///g')" = "ExarKernelDriver" ] ; then
+    echo "please navigate root terminal to the ExarKernelDriver directory and rerun code"
+    exit
+fi
+
+# unload the xr module if it is already loaded in the kernel
+# this allows us to use our modified module
+# if the module is already loaded this method doesn't affect anything
+modprobe -r xr_usb_serial_common
+
+# Run the driver makefile
+make
+
+# Copy Driver Module into Modules
+cp xr_usb_serial_common.ko /lib/modules/"$(uname -r)"/kernel/drivers/usb/serial
+
+# Refresh Modules
+depmod
+
+# make module load at boot time by adding "xr_usb_serial_common" on its own line to /etc/modules
+echo "xr_usb_serial_common" | tee -a /etc/modules
+
+# Load the module into Kernel
+insmod /lib/modules/"$(uname -r)"/kernel/drivers/usb/serial/xr_usb_serial_common.ko
+
+# Check if SC4 Device Connected
+BUS_ID=""
+if grep -q v2890p0213 /sys/bus/usb/devices/*/modalias; then
+	# If Device connected check what driver is bound to it
+    # this gets the driver numbers just choose 1
+
+    BUS_ID=$(grep v2890p0213 /sys/bus/usb/devices/*/modalias | head -1 | sed 's/\/sys\/bus\/usb\/devices\///g;s/\/.*//g')
+    if [ -d "/sys/bus/usb/drivers/cdc_acm/$BUS_ID" ] ; then
+        # need to unbind from acm
+        echo -n "$BUS_ID" > /sys/bus/usb/drivers/cdc_acm/unbind
+        
+    elif [ -d "/sys/bus/usb/drivers/cdc_xr_usb_serial/$BUS_ID" ]; then
+        echo SC4 already bound to XR no need to rebind
+    elif [ -d "/sys/bus/usb/devices/$BUS_ID/driver" ]; then
+        echo "$BUS_ID" Appears to be bound to another unrecognized driver
+        echo "please unbind from this driver then reattempt this process"
+    fi
+    
+else
+	# we not connected
+    read -n 1 -s -r -p "Please Insert the SC HUB if you haven't already and press any key to continue"
+fi
+
+if  [ ! -d "/sys/bus/usb/drivers/cdc_xr_usb_serial/$BUS_ID" ] ; then
+    # bind hub to the loaded xr driver
+    echo -n "$BUS_ID" > /sys/bus/usb/drivers/cdc_xr_usb_serial/bind
+fi
+
+cd ..
+if [ ! -d "/sys/bus/usb/drivers/cdc_xr_usb_serial/$BUS_ID" ]; then
+    # one last check
+    echo Something went wrong it does not appear as though the SC-HUB is bound to the XR Driver
+else
+    echo "Teknic Driver Install appears to have succeeded"
+fi
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/driver_readme.txt b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/driver_readme.txt
new file mode 100644
index 000000000..ad9d33406
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/driver_readme.txt
@@ -0,0 +1,62 @@
+
+
+                     Installing SC4-Hub USB Driver on Linux
+                                   2021-06-11
+
+
+                                       0
+                             Background Information
+Your system might have a built-in cdc_acm driver that will take control of the
+SC4-Hub. That driver is adequate for establishing communications with the board,
+but it is NOT fully compatible with sFoundation. For full support, install the
+Exar USB Serial driver packaged here.
+
+This exact procedure has been verified on the following distributions. The 
+general concepts should apply to nearly all Linux systems.
+ - Ubuntu 20.04 (x64)
+ - Fedora Workstation 33 (x64)
+ - Debian 10.9 (x64)
+ - Raspberry Pi OS (buster) (arm)
+ - Ubuntu 18.04 on BeagleBone Black (arm)
+ - elementary OS 5.1 (Hera)
+
+You will need root permission to follow this procedure.
+
+                                       1
+                               Install Procedure
+ 1. Make sure the kernel headers are installed on your system.
+    
+    Debian/Ubuntu/Raspberry Pi: 
+    Headers are typically stored in /usr/src/linux-headers-{kernelVersion}.
+    See if they exist using ls.
+    $ ls /usr/src/linux-headers-$(uname -r)
+
+    If they don't exist, install them using apt.
+    $ sudo apt install linux-headers-$(uname -r)
+
+    For Raspberry Pi, simply install the raspberrypi-kernel-headers
+    package.
+    $ sudo apt install raspberrypi-kernel-headers
+
+    Fedora:
+    Headers are typically stored in /usr/src/kernels/{kernelVersion}. See
+    if they exist using ls.
+    $ ls /usr/src/kernels/$(uname -r)
+
+    In Fedora, you can install the kernel-devel package with yum.
+    $ sudo yum install kernel-devel-$(uname -r)
+
+ 2. If you're reading this, you've probably already extracted the tarball. In 
+    case you didn't, extract it, then change to the ExarKernelDriver directory.
+    $ tar -xvf Teknic_SC4Hub_USB_Driver.tar
+    $ cd ExarKernelDriver
+
+ 3. Make sure Install_DRV_SCRIPT.sh is an executable
+    $ chmod +x Install_DRV_SCRIPT.sh
+
+ 4. Enter Root Terminal and Run the Driver Install script
+    $ sudo su
+    $ ./Install_DRV_SCRIPT.sh
+
+ > Note if the script fails or if you'd prefer, open up the script and read through it and execute the lines one by one
+ > the script is commented to explain the purpose of all the instructions
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_common.c b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_common.c
new file mode 100644
index 000000000..e22483a68
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_common.c
@@ -0,0 +1,1832 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+ 
+  /*
+ * Copyright (c) 2015 Exar Corporation, Inc.
+ *
+ * This driver will work with any USB UART function in these Exar devices:
+ *	XR21V1410/1412/1414
+ *	XR21B1411
+ *	XR21B1420/1422/1424
+ *	XR22801/802/804
+ *
+ * The driver has been tested on various kernel versions from 3.6.x to 3.17.x.  
+ * This driver may work on newer versions as well.  There is a different driver available 
+ * from www.exar.com that will work with kernel versions 2.6.18 to 3.4.x.
+ *
+ * ChangeLog:
+ *            Version 1B - Initial released version.
+ */
+
+#undef DEBUG
+#undef VERBOSE_DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/uaccess.h>
+#include <linux/usb.h>
+#include <linux/usb/cdc.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <linux/list.h>
+#include "linux/version.h"
+
+#include "xr_usb_serial_common.h"
+#include "xr_usb_serial_ioctl.h"
+
+
+#define DRIVER_AUTHOR "<uarttechsupport@exar.com>"
+#define DRIVER_DESC "Exar USB UART (serial port) driver"
+
+static struct usb_driver xr_usb_serial_driver;
+static struct tty_driver *xr_usb_serial_tty_driver;
+static struct xr_usb_serial *xr_usb_serial_table[XR_USB_SERIAL_TTY_MINORS];
+
+static DEFINE_MUTEX(xr_usb_serial_table_lock);
+
+/*
+ * xr_usb_serial_table accessors
+ */
+
+/*
+ * Look up an XR_USB_SERIAL structure by index. If found and not disconnected, increment
+ * its refcount and return it with its mutex held.
+ */
+static struct xr_usb_serial *xr_usb_serial_get_by_index(unsigned index)
+{
+	struct xr_usb_serial *xr_usb_serial;
+
+	mutex_lock(&xr_usb_serial_table_lock);
+	xr_usb_serial = xr_usb_serial_table[index];
+	if (xr_usb_serial) {
+		mutex_lock(&xr_usb_serial->mutex);
+		if (xr_usb_serial->disconnected) {
+			mutex_unlock(&xr_usb_serial->mutex);
+			xr_usb_serial = NULL;
+		} else {
+			tty_port_get(&xr_usb_serial->port);
+			mutex_unlock(&xr_usb_serial->mutex);
+		}
+	}
+	mutex_unlock(&xr_usb_serial_table_lock);
+	return xr_usb_serial;
+}
+
+/*
+ * Try to find an available minor number and if found, associate it with 'xr_usb_serial'.
+ */
+static int xr_usb_serial_alloc_minor(struct xr_usb_serial *xr_usb_serial)
+{
+	int minor;
+
+	mutex_lock(&xr_usb_serial_table_lock);
+	for (minor = 0; minor < XR_USB_SERIAL_TTY_MINORS; minor++) {
+		if (!xr_usb_serial_table[minor]) {
+			xr_usb_serial_table[minor] = xr_usb_serial;
+			break;
+		}
+	}
+	mutex_unlock(&xr_usb_serial_table_lock);
+
+	return minor;
+}
+
+/* Release the minor number associated with 'xr_usb_serial'.  */
+static void xr_usb_serial_release_minor(struct xr_usb_serial *xr_usb_serial)
+{
+	mutex_lock(&xr_usb_serial_table_lock);
+	xr_usb_serial_table[xr_usb_serial->minor] = NULL;
+	mutex_unlock(&xr_usb_serial_table_lock);
+}
+
+/*
+ * Functions for XR_USB_SERIAL control messages.
+ */
+
+static int xr_usb_serial_ctrl_msg(struct xr_usb_serial *xr_usb_serial, int request, int value,
+							void *buf, int len)
+{
+	int retval = usb_control_msg(xr_usb_serial->dev, usb_sndctrlpipe(xr_usb_serial->dev, 0),
+		request, USB_RT_XR_USB_SERIAL, value,
+		xr_usb_serial->control->altsetting[0].desc.bInterfaceNumber,
+		buf, len, 5000);
+	dev_dbg(&xr_usb_serial->control->dev,
+			"%s - rq 0x%02x, val %#x, len %#x, result %d\n",
+			__func__, request, value, len, retval);
+	return retval < 0 ? retval : 0;
+}
+
+#include "xr_usb_serial_hal.c"
+
+
+/*
+ * Write buffer management.
+ * All of these assume proper locks taken by the caller.
+ */
+
+static int xr_usb_serial_wb_alloc(struct xr_usb_serial *xr_usb_serial)
+{
+	int i, wbn;
+	struct xr_usb_serial_wb *wb;
+
+	wbn = 0;
+	i = 0;
+	for (;;) {
+		wb = &xr_usb_serial->wb[wbn];
+		if (!wb->use) {
+			wb->use = 1;
+			return wbn;
+		}
+		wbn = (wbn + 1) % XR_USB_SERIAL_NW;
+		if (++i >= XR_USB_SERIAL_NW)
+			return -1;
+	}
+}
+
+static int xr_usb_serial_wb_is_avail(struct xr_usb_serial *xr_usb_serial)
+{
+	int i, n;
+	unsigned long flags;
+
+	n = XR_USB_SERIAL_NW;
+	spin_lock_irqsave(&xr_usb_serial->write_lock, flags);
+	for (i = 0; i < XR_USB_SERIAL_NW; i++)
+		n -= xr_usb_serial->wb[i].use;
+	spin_unlock_irqrestore(&xr_usb_serial->write_lock, flags);
+	return n;
+}
+
+/*
+ * Finish write. Caller must hold xr_usb_serial->write_lock
+ */
+static void xr_usb_serial_write_done(struct xr_usb_serial *xr_usb_serial, struct xr_usb_serial_wb *wb)
+{
+	wb->use = 0;
+	xr_usb_serial->transmitting--;
+	usb_autopm_put_interface_async(xr_usb_serial->control);
+}
+
+/*
+ * Poke write.
+ *
+ * the caller is responsible for locking
+ */
+
+static int xr_usb_serial_start_wb(struct xr_usb_serial *xr_usb_serial, struct xr_usb_serial_wb *wb)
+{
+	int rc;
+
+	xr_usb_serial->transmitting++;
+
+	wb->urb->transfer_buffer = wb->buf;
+	wb->urb->transfer_dma = wb->dmah;
+	wb->urb->transfer_buffer_length = wb->len;
+	wb->urb->dev = xr_usb_serial->dev;
+
+	rc = usb_submit_urb(wb->urb, GFP_ATOMIC);
+	if (rc < 0) {
+		dev_err(&xr_usb_serial->data->dev,
+			"%s - usb_submit_urb(write bulk) failed: %d\n",
+			__func__, rc);
+		xr_usb_serial_write_done(xr_usb_serial, wb);
+	}
+	return rc;
+}
+
+/*
+ * attributes exported through sysfs
+ */
+static ssize_t show_caps
+(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct usb_interface *intf = to_usb_interface(dev);
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+
+	return sprintf(buf, "%d", xr_usb_serial->ctrl_caps);
+}
+static DEVICE_ATTR(bmCapabilities, S_IRUGO, show_caps, NULL);
+
+static ssize_t show_country_codes
+(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct usb_interface *intf = to_usb_interface(dev);
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+
+	memcpy(buf, xr_usb_serial->country_codes, xr_usb_serial->country_code_size);
+	return xr_usb_serial->country_code_size;
+}
+
+static DEVICE_ATTR(wCountryCodes, S_IRUGO, show_country_codes, NULL);
+
+static ssize_t show_country_rel_date
+(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct usb_interface *intf = to_usb_interface(dev);
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+
+	return sprintf(buf, "%d", xr_usb_serial->country_rel_date);
+}
+
+static DEVICE_ATTR(iCountryCodeRelDate, S_IRUGO, show_country_rel_date, NULL);
+/*
+ * Interrupt handlers for various XR_USB_SERIAL device responses
+ */
+
+/* control interface reports status changes with "interrupt" transfers */
+static void xr_usb_serial_ctrl_irq(struct urb *urb)
+{
+	struct xr_usb_serial *xr_usb_serial = urb->context;
+	struct usb_cdc_notification *dr = urb->transfer_buffer;
+	struct tty_struct *tty;
+	unsigned char *data;
+	int newctrl;
+	int retval;
+	int status = urb->status;
+	int i;
+	unsigned char *p;
+		
+	switch (status) {
+	case 0:
+		p = (unsigned char *)(urb->transfer_buffer);
+		for(i=0;i<urb->actual_length;i++)
+	    {
+          dev_dbg(&xr_usb_serial->control->dev,"0x%02x\n",p[i]);
+	    }
+		/* success */
+		break;
+	case -ECONNRESET:
+	case -ENOENT:
+	case -ESHUTDOWN:
+		/* this urb is terminated, clean up */
+		dev_dbg(&xr_usb_serial->control->dev,
+				"%s - urb shutting down with status: %d\n",
+				__func__, status);
+		return;
+	default:
+		dev_dbg(&xr_usb_serial->control->dev,
+				"%s - nonzero urb status received: %d\n",
+				__func__, status);
+		goto exit;
+	}
+
+	usb_mark_last_busy(xr_usb_serial->dev);
+
+	data = (unsigned char *)(dr + 1);
+	switch (dr->bNotificationType) {
+	case USB_CDC_NOTIFY_NETWORK_CONNECTION:
+		dev_dbg(&xr_usb_serial->control->dev, "%s - network connection: %d\n",
+							__func__, dr->wValue);
+		break;
+
+	case USB_CDC_NOTIFY_SERIAL_STATE:
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 9, 0)		
+		newctrl = get_unaligned_le16(data);
+    	if (!xr_usb_serial->clocal && (xr_usb_serial->ctrlin & ~newctrl & XR_USB_SERIAL_CTRL_DCD)) {
+			dev_dbg(&xr_usb_serial->control->dev, "%s - calling hangup\n",
+					__func__);
+			tty_port_tty_hangup(&xr_usb_serial->port, false);
+		}
+#else		
+		tty = tty_port_tty_get(&xr_usb_serial->port);
+        newctrl = get_unaligned_le16(data);
+		if (tty)
+		{
+			if (!xr_usb_serial->clocal &&
+				(xr_usb_serial->ctrlin & ~newctrl & XR_USB_SERIAL_CTRL_DCD)) {
+				dev_dbg(&xr_usb_serial->control->dev,
+					"%s - calling hangup\n", __func__);
+				tty_hangup(tty);
+			}
+			tty_kref_put(tty);
+		}
+#endif
+		xr_usb_serial->ctrlin = newctrl;
+
+		dev_dbg(&xr_usb_serial->control->dev,
+			"%s - input control lines: dcd%c dsr%c break%c "
+			"ring%c framing%c parity%c overrun%c\n",
+			__func__,
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_DCD ? '+' : '-',
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_DSR ? '+' : '-',
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_BRK ? '+' : '-',
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_RI  ? '+' : '-',
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_FRAMING ? '+' : '-',
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_PARITY ? '+' : '-',
+			xr_usb_serial->ctrlin & XR_USB_SERIAL_CTRL_OVERRUN ? '+' : '-');
+			break;
+
+	default:
+		dev_dbg(&xr_usb_serial->control->dev,
+			"%s - unknown notification %d received: index %d "
+			"len %d data0 %d data1 %d\n",
+			__func__,
+			dr->bNotificationType, dr->wIndex,
+			dr->wLength, data[0], data[1]);
+		break;
+	}
+exit:
+	retval = usb_submit_urb(urb, GFP_ATOMIC);
+	if (retval)
+		dev_err(&xr_usb_serial->control->dev, "%s - usb_submit_urb failed: %d\n",
+							__func__, retval);
+}
+
+static int xr_usb_serial_submit_read_urb(struct xr_usb_serial *xr_usb_serial, int index, gfp_t mem_flags)
+{
+	int res;
+
+	if (!test_and_clear_bit(index, &xr_usb_serial->read_urbs_free))
+		return 0;
+
+	dev_vdbg(&xr_usb_serial->data->dev, "%s - urb %d\n", __func__, index);
+
+	res = usb_submit_urb(xr_usb_serial->read_urbs[index], mem_flags);
+	if (res) {
+		if (res != -EPERM) {
+			dev_err(&xr_usb_serial->data->dev,
+					"%s - usb_submit_urb failed: %d\n",
+					__func__, res);
+		}
+		set_bit(index, &xr_usb_serial->read_urbs_free);
+		return res;
+	}
+
+	return 0;
+}
+
+static int xr_usb_serial_submit_read_urbs(struct xr_usb_serial *xr_usb_serial, gfp_t mem_flags)
+{
+	int res;
+	int i;
+
+	for (i = 0; i < xr_usb_serial->rx_buflimit; ++i) {
+		res = xr_usb_serial_submit_read_urb(xr_usb_serial, i, mem_flags);
+		if (res)
+			return res;
+	}
+
+	return 0;
+}
+static void xr_usb_serial_process_read_urb(struct xr_usb_serial *xr_usb_serial, struct urb *urb)
+{
+    struct tty_struct *tty;
+	if (!urb->actual_length)
+		return;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
+	tty_insert_flip_string(&xr_usb_serial->port, urb->transfer_buffer,
+			urb->actual_length);
+	tty_flip_buffer_push(&xr_usb_serial->port);
+#else
+    tty = tty_port_tty_get(&xr_usb_serial->port);
+	if (!tty)
+		return;
+	tty_insert_flip_string(tty, urb->transfer_buffer, urb->actual_length);
+	tty_flip_buffer_push(tty);
+
+	tty_kref_put(tty);
+#endif
+}
+
+static void xr_usb_serial_read_bulk_callback(struct urb *urb)
+{
+	struct xr_usb_serial_rb *rb = urb->context;
+	struct xr_usb_serial *xr_usb_serial = rb->instance;
+	unsigned long flags;
+
+	dev_vdbg(&xr_usb_serial->data->dev, "%s - urb %d, len %d\n", __func__,
+					rb->index, urb->actual_length);
+	set_bit(rb->index, &xr_usb_serial->read_urbs_free);
+
+	if (!xr_usb_serial->dev) {
+		dev_dbg(&xr_usb_serial->data->dev, "%s - disconnected\n", __func__);
+		return;
+	}
+	usb_mark_last_busy(xr_usb_serial->dev);
+
+	if (urb->status) {
+		dev_dbg(&xr_usb_serial->data->dev, "%s - non-zero urb status: %d\n",
+							__func__, urb->status);
+		return;
+	}
+	xr_usb_serial_process_read_urb(xr_usb_serial, urb);
+
+	/* throttle device if requested by tty */
+	spin_lock_irqsave(&xr_usb_serial->read_lock, flags);
+	xr_usb_serial->throttled = xr_usb_serial->throttle_req;
+	if (!xr_usb_serial->throttled && !xr_usb_serial->susp_count) {
+		spin_unlock_irqrestore(&xr_usb_serial->read_lock, flags);
+		xr_usb_serial_submit_read_urb(xr_usb_serial, rb->index, GFP_ATOMIC);
+	} else {
+		spin_unlock_irqrestore(&xr_usb_serial->read_lock, flags);
+	}
+}
+
+/* data interface wrote those outgoing bytes */
+static void xr_usb_serial_write_bulk(struct urb *urb)
+{
+	struct xr_usb_serial_wb *wb = urb->context;
+	struct xr_usb_serial *xr_usb_serial = wb->instance;
+	unsigned long flags;
+
+	if (urb->status	|| (urb->actual_length != urb->transfer_buffer_length))
+		dev_vdbg(&xr_usb_serial->data->dev, "%s - len %d/%d, status %d\n",
+			__func__,
+			urb->actual_length,
+			urb->transfer_buffer_length,
+			urb->status);
+
+	spin_lock_irqsave(&xr_usb_serial->write_lock, flags);
+	xr_usb_serial_write_done(xr_usb_serial, wb);
+	spin_unlock_irqrestore(&xr_usb_serial->write_lock, flags);
+	schedule_work(&xr_usb_serial->work);
+}
+
+static void xr_usb_serial_softint(struct work_struct *work)
+{
+	struct xr_usb_serial *xr_usb_serial = container_of(work, struct xr_usb_serial, work);
+    struct tty_struct *tty;
+	
+	dev_vdbg(&xr_usb_serial->data->dev, "%s\n", __func__);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 9, 0)
+	tty_port_tty_wakeup(&xr_usb_serial->port);
+#else	
+	tty = tty_port_tty_get(&xr_usb_serial->port);
+	if (!tty)
+		return;
+	tty_wakeup(tty);
+	tty_kref_put(tty);
+#endif	
+}
+
+/*
+ * TTY handlers
+ */
+
+static int xr_usb_serial_tty_install(struct tty_driver *driver, struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial;
+	int retval;
+
+	dev_dbg(tty->dev, "%s\n", __func__);
+
+	xr_usb_serial = xr_usb_serial_get_by_index(tty->index);
+	if (!xr_usb_serial)
+		return -ENODEV;
+
+	retval = tty_standard_install(driver, tty);
+	if (retval)
+		goto error_init_termios;
+
+	tty->driver_data = xr_usb_serial;
+
+	return 0;
+
+error_init_termios:
+	tty_port_put(&xr_usb_serial->port);
+	return retval;
+}
+
+static int xr_usb_serial_tty_open(struct tty_struct *tty, struct file *filp)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	int result;
+    result = xr_usb_serial_fifo_reset(xr_usb_serial);
+	dev_dbg(tty->dev, "%s\n", __func__);
+    
+	return tty_port_open(&xr_usb_serial->port, tty, filp);
+}
+
+static int xr_usb_serial_port_activate(struct tty_port *port, struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = container_of(port, struct xr_usb_serial, port);
+	int retval = -ENODEV;
+
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+
+	mutex_lock(&xr_usb_serial->mutex);
+	if (xr_usb_serial->disconnected)
+		goto disconnected;
+
+	retval = usb_autopm_get_interface(xr_usb_serial->control);
+	if (retval)
+		goto error_get_interface;
+
+	/*
+	 * FIXME: Why do we need this? Allocating 64K of physically contiguous
+	 * memory is really nasty...
+	 */
+	set_bit(TTY_NO_WRITE_SPLIT, &tty->flags);
+	xr_usb_serial->control->needs_remote_wakeup = 1;
+
+	xr_usb_serial->ctrlurb->dev = xr_usb_serial->dev;
+	if (usb_submit_urb(xr_usb_serial->ctrlurb, GFP_KERNEL)) {
+		dev_err(&xr_usb_serial->control->dev,
+			"%s - usb_submit_urb(ctrl irq) failed\n", __func__);
+		goto error_submit_urb;
+	}
+
+	xr_usb_serial->ctrlout = XR_USB_SERIAL_CTRL_DTR | XR_USB_SERIAL_CTRL_RTS;
+	if (xr_usb_serial_set_control(xr_usb_serial, xr_usb_serial->ctrlout) < 0 &&
+	    (xr_usb_serial->ctrl_caps & USB_CDC_CAP_LINE))
+		goto error_set_control;
+
+	usb_autopm_put_interface(xr_usb_serial->control);
+
+	/*
+	 * Unthrottle device in case the TTY was closed while throttled.
+	 */
+	spin_lock_irq(&xr_usb_serial->read_lock);
+	xr_usb_serial->throttled = 0;
+	xr_usb_serial->throttle_req = 0;
+	spin_unlock_irq(&xr_usb_serial->read_lock);
+
+	if (xr_usb_serial_submit_read_urbs(xr_usb_serial, GFP_KERNEL))
+		goto error_submit_read_urbs;
+
+	mutex_unlock(&xr_usb_serial->mutex);
+
+	return 0;
+
+error_submit_read_urbs:
+	xr_usb_serial->ctrlout = 0;
+	xr_usb_serial_set_control(xr_usb_serial, xr_usb_serial->ctrlout);
+error_set_control:
+	usb_kill_urb(xr_usb_serial->ctrlurb);
+error_submit_urb:
+	usb_autopm_put_interface(xr_usb_serial->control);
+error_get_interface:
+disconnected:
+	mutex_unlock(&xr_usb_serial->mutex);
+	return retval;
+}
+
+static void xr_usb_serial_port_destruct(struct tty_port *port)
+{
+	struct xr_usb_serial *xr_usb_serial = container_of(port, struct xr_usb_serial, port);
+
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+    #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0)
+	tty_unregister_device(xr_usb_serial_tty_driver, xr_usb_serial->minor);
+	#endif
+	xr_usb_serial_release_minor(xr_usb_serial);
+	usb_put_intf(xr_usb_serial->control);
+	kfree(xr_usb_serial->country_codes);
+	kfree(xr_usb_serial);
+}
+
+static void xr_usb_serial_port_shutdown(struct tty_port *port)
+{
+	struct xr_usb_serial *xr_usb_serial = container_of(port, struct xr_usb_serial, port);
+	int i;
+
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+
+	mutex_lock(&xr_usb_serial->mutex);
+	if (!xr_usb_serial->disconnected) {
+		usb_autopm_get_interface(xr_usb_serial->control);
+		xr_usb_serial_set_control(xr_usb_serial, xr_usb_serial->ctrlout = 0);
+		usb_kill_urb(xr_usb_serial->ctrlurb);
+		for (i = 0; i < XR_USB_SERIAL_NW; i++)
+			usb_kill_urb(xr_usb_serial->wb[i].urb);
+		for (i = 0; i < xr_usb_serial->rx_buflimit; i++)
+			usb_kill_urb(xr_usb_serial->read_urbs[i]);
+		xr_usb_serial->control->needs_remote_wakeup = 0;
+		usb_autopm_put_interface(xr_usb_serial->control);
+	}
+	mutex_unlock(&xr_usb_serial->mutex);
+}
+
+static void xr_usb_serial_tty_cleanup(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+	tty_port_put(&xr_usb_serial->port);
+}
+
+static void xr_usb_serial_tty_hangup(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+	tty_port_hangup(&xr_usb_serial->port);
+}
+
+static void xr_usb_serial_tty_close(struct tty_struct *tty, struct file *filp)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+	tty_port_close(&xr_usb_serial->port, tty, filp);
+}
+
+static int xr_usb_serial_tty_write(struct tty_struct *tty,
+					const unsigned char *buf, int count)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	int stat;
+	unsigned long flags;
+	int wbn;
+	struct xr_usb_serial_wb *wb;
+
+	if (!count)
+		return 0;
+
+	dev_vdbg(&xr_usb_serial->data->dev, "%s - count %d\n", __func__, count);
+
+	spin_lock_irqsave(&xr_usb_serial->write_lock, flags);
+	wbn = xr_usb_serial_wb_alloc(xr_usb_serial);
+	if (wbn < 0) {
+		spin_unlock_irqrestore(&xr_usb_serial->write_lock, flags);
+		return 0;
+	}
+	wb = &xr_usb_serial->wb[wbn];
+
+	if (!xr_usb_serial->dev) {
+		wb->use = 0;
+		spin_unlock_irqrestore(&xr_usb_serial->write_lock, flags);
+		return -ENODEV;
+	}
+
+	count = (count > xr_usb_serial->writesize) ? xr_usb_serial->writesize : count;
+	dev_vdbg(&xr_usb_serial->data->dev, "%s - write %d\n", __func__, count);
+	memcpy(wb->buf, buf, count);
+	wb->len = count;
+
+	usb_autopm_get_interface_async(xr_usb_serial->control);
+	if (xr_usb_serial->susp_count) {
+		if (!xr_usb_serial->delayed_wb)
+			xr_usb_serial->delayed_wb = wb;
+		else
+			usb_autopm_put_interface_async(xr_usb_serial->control);
+		spin_unlock_irqrestore(&xr_usb_serial->write_lock, flags);
+		return count;	/* A white lie */
+	}
+	usb_mark_last_busy(xr_usb_serial->dev);
+
+	stat = xr_usb_serial_start_wb(xr_usb_serial, wb);
+	spin_unlock_irqrestore(&xr_usb_serial->write_lock, flags);
+
+	if (stat < 0)
+		return stat;
+	return count;
+}
+
+static int xr_usb_serial_tty_write_room(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	/*
+	 * Do not let the line discipline to know that we have a reserve,
+	 * or it might get too enthusiastic.
+	 */
+	return xr_usb_serial_wb_is_avail(xr_usb_serial) ? xr_usb_serial->writesize : 0;
+}
+
+static int xr_usb_serial_tty_chars_in_buffer(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	/*
+	 * if the device was unplugged then any remaining characters fell out
+	 * of the connector ;)
+	 */
+	if (xr_usb_serial->disconnected)
+		return 0;
+	/*
+	 * This is inaccurate (overcounts), but it works.
+	 */
+	return (XR_USB_SERIAL_NW - xr_usb_serial_wb_is_avail(xr_usb_serial)) * xr_usb_serial->writesize;
+}
+
+static void xr_usb_serial_tty_throttle(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+
+	spin_lock_irq(&xr_usb_serial->read_lock);
+	xr_usb_serial->throttle_req = 1;
+	spin_unlock_irq(&xr_usb_serial->read_lock);
+}
+
+static void xr_usb_serial_tty_unthrottle(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	unsigned int was_throttled;
+
+	spin_lock_irq(&xr_usb_serial->read_lock);
+	was_throttled = xr_usb_serial->throttled;
+	xr_usb_serial->throttled = 0;
+	xr_usb_serial->throttle_req = 0;
+	spin_unlock_irq(&xr_usb_serial->read_lock);
+
+	if (was_throttled)
+		xr_usb_serial_submit_read_urbs(xr_usb_serial, GFP_KERNEL);
+}
+
+static int xr_usb_serial_tty_break_ctl(struct tty_struct *tty, int state)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	int retval;
+
+	retval = xr_usb_serial_send_break(xr_usb_serial, state ? 0xffff : 0);
+	if (retval < 0)
+		dev_dbg(&xr_usb_serial->control->dev, "%s - send break failed\n",
+								__func__);
+	return retval;
+}
+
+static int xr_usb_serial_tty_tiocmget(struct tty_struct *tty)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_tty_tiocmget\n");
+    return xr_usb_serial_tiocmget(xr_usb_serial);
+
+}
+
+static int xr_usb_serial_tty_tiocmset(struct tty_struct *tty,
+			    unsigned int set, unsigned int clear)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_tty_tiocmset set=0x%x clear=0x%x\n",set,clear);
+    return xr_usb_serial_tiocmset(xr_usb_serial,set,clear);
+
+}
+
+static int get_serial_info(struct xr_usb_serial *xr_usb_serial, struct serial_struct __user *info)
+{
+	struct serial_struct tmp;
+
+	if (!info)
+		return -EINVAL;
+
+	memset(&tmp, 0, sizeof(tmp));
+	tmp.flags = ASYNC_LOW_LATENCY;
+	tmp.xmit_fifo_size = xr_usb_serial->writesize;
+	tmp.baud_base = le32_to_cpu(xr_usb_serial->line.dwDTERate);
+	tmp.close_delay	= xr_usb_serial->port.close_delay / 10;
+	tmp.closing_wait = xr_usb_serial->port.closing_wait == ASYNC_CLOSING_WAIT_NONE ?
+				ASYNC_CLOSING_WAIT_NONE :
+				xr_usb_serial->port.closing_wait / 10;
+
+	if (copy_to_user(info, &tmp, sizeof(tmp)))
+		return -EFAULT;
+	else
+		return 0;
+}
+
+static int set_serial_info(struct xr_usb_serial *xr_usb_serial,
+				struct serial_struct __user *newinfo)
+{
+	struct serial_struct new_serial;
+	unsigned int closing_wait, close_delay;
+	int retval = 0;
+
+	if (copy_from_user(&new_serial, newinfo, sizeof(new_serial)))
+		return -EFAULT;
+
+	close_delay = new_serial.close_delay * 10;
+	closing_wait = new_serial.closing_wait == ASYNC_CLOSING_WAIT_NONE ?
+			ASYNC_CLOSING_WAIT_NONE : new_serial.closing_wait * 10;
+
+	mutex_lock(&xr_usb_serial->port.mutex);
+
+	if (!capable(CAP_SYS_ADMIN)) {
+		if ((close_delay != xr_usb_serial->port.close_delay) ||
+		    (closing_wait != xr_usb_serial->port.closing_wait))
+			retval = -EPERM;
+		else
+			retval = -EOPNOTSUPP;
+	} else {
+		xr_usb_serial->port.close_delay  = close_delay;
+		xr_usb_serial->port.closing_wait = closing_wait;
+	}
+
+	mutex_unlock(&xr_usb_serial->port.mutex);
+	return retval;
+}
+
+static int xr_usb_serial_tty_ioctl(struct tty_struct *tty,
+					unsigned int cmd, unsigned long arg)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+	int rv = -ENOIOCTLCMD;
+    unsigned int  channel, reg, val;
+    int           baud_rate = 0;
+	struct usb_cdc_line_coding newline;
+    short	*data;
+	switch (cmd) {
+	case TIOCGSERIAL: /* gets serial port data */
+		rv = get_serial_info(xr_usb_serial, (struct serial_struct __user *) arg);
+		break;
+	case TIOCSSERIAL:
+		rv = set_serial_info(xr_usb_serial, (struct serial_struct __user *) arg);
+		break;
+    case XR_USB_SERIAL_GET_REG:
+                if (get_user(channel, (int __user *)arg))
+                        return -EFAULT;
+                if (get_user(reg, (int __user *)(arg + sizeof(int))))
+                        return -EFAULT;
+
+                data = kmalloc(2, GFP_KERNEL);
+                if (data == NULL) {
+                        dev_err(&xr_usb_serial->control->dev, "%s - Cannot allocate USB buffer.\n", __func__);
+                        return -ENOMEM;
+		}
+        			
+		        if (channel == -1)
+		        {
+		          rv = xr_usb_serial_get_reg(xr_usb_serial,reg, data);
+		        }
+				else
+				{
+			  	  rv = xr_usb_serial_get_reg_ext(xr_usb_serial,channel,reg, data);
+				}
+                if (rv < 0)
+                {
+                        dev_err(&xr_usb_serial->control->dev, "Cannot get register (%d)\n", rv);
+                        kfree(data);
+                        return -EFAULT;
+                }
+				if (put_user(le16_to_cpu(*data), (int __user *)(arg + 2 * sizeof(int))))
+              	{
+                   dev_err(&xr_usb_serial->control->dev, "Cannot put user result\n");
+                   kfree(data);
+                   return -EFAULT;
+                }
+                rv = 0;
+                kfree(data);
+                break;
+
+      case XR_USB_SERIAL_SET_REG:
+                if (get_user(channel, (int __user *)arg))
+                        return -EFAULT;
+                if (get_user(reg, (int __user *)(arg + sizeof(int))))
+                        return -EFAULT;
+                if (get_user(val, (int __user *)(arg + 2 * sizeof(int))))
+                        return -EFAULT;
+
+			if (channel == -1)
+			{
+				rv = xr_usb_serial_set_reg(xr_usb_serial,reg, val);
+			}
+			else
+			{
+			 	rv = xr_usb_serial_set_reg_ext(xr_usb_serial,channel,reg, val);
+				
+			}
+		    if (rv < 0)
+               return -EFAULT;  
+			rv = 0;
+            break;
+	case XR_USB_SERIAL_LOOPBACK:
+		     if (get_user(channel, (int __user *)arg))
+                        return -EFAULT;
+		     if (channel == -1)
+			   channel = xr_usb_serial->channel;
+			 rv = xr_usb_serial_set_loopback(xr_usb_serial,channel);
+			 if (rv < 0)
+               return -EFAULT;
+			 rv = 0;
+		     break;
+	 case XR_USB_SERIAL_SET_GPIO_MODE_REG:
+		xr_usb_serial_disable(xr_usb_serial);
+		if (get_user(channel, (int __user *)arg))
+		    return -EFAULT;
+		if (get_user(val, (int __user *)(arg + sizeof(int))))
+		    return -EFAULT;
+	   	if (channel == -1)
+		{
+			//block = portdata->block;
+		    rv = xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_mode_addr, val);
+		}
+		else
+		{
+		    rv = xr_usb_serial_set_reg_ext(xr_usb_serial,channel,xr_usb_serial->reg_map.uart_gpio_mode_addr, val);
+		}
+		
+		dev_dbg(&xr_usb_serial->control->dev, "XR_USB_SERIAL_SET_GPIO_MODE_REG 0x%x val:0x%x \n", xr_usb_serial->reg_map.uart_gpio_mode_addr,val);
+		xr_usb_serial_enable(xr_usb_serial);
+		if (rv < 0)
+		        return -EFAULT;
+		break;
+	case XR_USB_SERIAL_GET_GPIO_MODE_REG:
+		xr_usb_serial_disable(xr_usb_serial);
+		if (get_user(channel, (int __user *)arg))
+                        return -EFAULT;
+       
+        data = kmalloc(2, GFP_KERNEL);
+        if (data == NULL) {
+                dev_err(&xr_usb_serial->control->dev, "%s - Cannot allocate USB buffer.\n", __func__);
+                return -ENOMEM;
+		}
+
+		if (channel == -1)
+		{
+		     rv = xr_usb_serial_get_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_mode_addr, data);
+		}
+		else
+		{
+		    rv = xr_usb_serial_get_reg_ext(xr_usb_serial,channel,xr_usb_serial->reg_map.uart_gpio_mode_addr,data);
+		}
+		
+		xr_usb_serial_enable(xr_usb_serial);
+		
+		dev_dbg(&xr_usb_serial->control->dev, "XR_USB_SERIAL_GET_GPIO_MODE_REG 0x%x val:0x%x \n", xr_usb_serial->reg_map.uart_gpio_mode_addr,*data);
+		
+        if (rv < 0 ) {
+                dev_err(&xr_usb_serial->control->dev, "Cannot get register (%d) channel=%d \n", rv,channel);
+                kfree(data);
+                return -EFAULT;
+        }
+				
+        if (put_user(data[0], (int __user *)(arg + sizeof(int)))) {
+                dev_err(&xr_usb_serial->control->dev, "Cannot put user result\n");
+                kfree(data);
+                return -EFAULT;
+        }
+
+        kfree(data);
+		break;
+	case XRIOC_SET_ANY_BAUD_RATE:
+		
+		 if (get_user(baud_rate, (int __user *)arg)) {
+		 	   dev_dbg(&xr_usb_serial->control->dev, "get_user errot \n");
+               return -EFAULT;
+		 }
+		 xr_usb_serial->line.dwDTERate = baud_rate; 
+		 memcpy(&newline,&(xr_usb_serial->line),sizeof(struct usb_cdc_line_coding));
+		 xr_usb_serial_disable(xr_usb_serial);
+		 rv = xr_usb_serial_set_line(xr_usb_serial,&newline);
+		 xr_usb_serial_enable(xr_usb_serial);
+		 dev_dbg(&xr_usb_serial->control->dev, "XRIOC_SET_ANY_BAUD_RATE set baud_rate:%d ret=%d\n", baud_rate,rv);
+		 break;	
+		 
+		
+	}
+
+	return rv;
+}
+
+static void xr_usb_serial_tty_set_termios(struct tty_struct *tty,
+						struct ktermios *termios_old)
+{
+	struct xr_usb_serial *xr_usb_serial = tty->driver_data;
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0)	
+	struct ktermios *termios = tty->termios;
+#else
+    struct ktermios *termios = &tty->termios;
+#endif
+	unsigned int   cflag = termios->c_cflag;
+	struct usb_cdc_line_coding newline;
+	int newctrl = xr_usb_serial->ctrlout;
+    xr_usb_serial_disable(xr_usb_serial);
+	newline.dwDTERate = cpu_to_le32(tty_get_baud_rate(tty));
+	newline.bCharFormat = termios->c_cflag & CSTOPB ? 1 : 0;
+	newline.bParityType = termios->c_cflag & PARENB ?
+				(termios->c_cflag & PARODD ? 1 : 2) +
+				(termios->c_cflag & CMSPAR ? 2 : 0) : 0;
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:/*using CS5 replace of the 9 bit data mode*/
+		newline.bDataBits = 9;
+		break;
+	case CS6:
+		newline.bDataBits = 6;
+		break;
+	case CS7:
+		newline.bDataBits = 7;
+		break;
+	case CS8:
+	default:
+		newline.bDataBits = 8;
+		break;
+	}
+	/* FIXME: Needs to clear unsupported bits in the termios */
+	xr_usb_serial->clocal = ((termios->c_cflag & CLOCAL) != 0);
+
+	if (!newline.dwDTERate) {
+		newline.dwDTERate = xr_usb_serial->line.dwDTERate;
+		newctrl &= ~XR_USB_SERIAL_CTRL_DTR;
+	} else
+		newctrl |=  XR_USB_SERIAL_CTRL_DTR;
+
+	if (newctrl != xr_usb_serial->ctrlout)
+		xr_usb_serial_set_control(xr_usb_serial, xr_usb_serial->ctrlout = newctrl);
+	
+    xr_usb_serial_set_flow_mode(xr_usb_serial,tty,cflag);/*set the serial flow mode*/
+	 	
+	if (memcmp(&xr_usb_serial->line, &newline, sizeof newline))
+	{
+		memcpy(&xr_usb_serial->line, &newline, sizeof newline);
+		dev_dbg(&xr_usb_serial->control->dev, "%s - set line: %d %d %d %d\n",
+			__func__,
+			le32_to_cpu(newline.dwDTERate),
+			newline.bCharFormat, newline.bParityType,
+			newline.bDataBits);
+		xr_usb_serial_set_line(xr_usb_serial, &xr_usb_serial->line);
+	}
+	xr_usb_serial_enable(xr_usb_serial);
+}
+
+static const struct tty_port_operations xr_usb_serial_port_ops = {
+	.shutdown = xr_usb_serial_port_shutdown,
+	.activate = xr_usb_serial_port_activate,
+	.destruct = xr_usb_serial_port_destruct,
+};
+
+/*
+ * USB probe and disconnect routines.
+ */
+
+/* Little helpers: write/read buffers free */
+static void xr_usb_serial_write_buffers_free(struct xr_usb_serial *xr_usb_serial)
+{
+	int i;
+	struct xr_usb_serial_wb *wb;
+	struct usb_device *usb_dev = interface_to_usbdev(xr_usb_serial->control);
+
+	for (wb = &xr_usb_serial->wb[0], i = 0; i < XR_USB_SERIAL_NW; i++, wb++)
+		usb_free_coherent(usb_dev, xr_usb_serial->writesize, wb->buf, wb->dmah);
+}
+
+static void xr_usb_serial_read_buffers_free(struct xr_usb_serial *xr_usb_serial)
+{
+	struct usb_device *usb_dev = interface_to_usbdev(xr_usb_serial->control);
+	int i;
+
+	for (i = 0; i < xr_usb_serial->rx_buflimit; i++)
+		usb_free_coherent(usb_dev, xr_usb_serial->readsize,
+			  xr_usb_serial->read_buffers[i].base, xr_usb_serial->read_buffers[i].dma);
+}
+
+/* Little helper: write buffers allocate */
+static int xr_usb_serial_write_buffers_alloc(struct xr_usb_serial *xr_usb_serial)
+{
+	int i;
+	struct xr_usb_serial_wb *wb;
+
+	for (wb = &xr_usb_serial->wb[0], i = 0; i < XR_USB_SERIAL_NW; i++, wb++) {
+		wb->buf = usb_alloc_coherent(xr_usb_serial->dev, xr_usb_serial->writesize, GFP_KERNEL,
+		    &wb->dmah);
+		if (!wb->buf) {
+			while (i != 0) {
+				--i;
+				--wb;
+				usb_free_coherent(xr_usb_serial->dev, xr_usb_serial->writesize,
+				    wb->buf, wb->dmah);
+			}
+			return -ENOMEM;
+		}
+	}
+	return 0;
+}
+
+static int xr_usb_serial_probe(struct usb_interface *intf,
+		     const struct usb_device_id *id)
+{
+	struct usb_cdc_union_desc *union_header = NULL;
+	struct usb_cdc_country_functional_desc *cfd = NULL;
+	unsigned char *buffer = intf->altsetting->extra;
+	int buflen = intf->altsetting->extralen;
+	struct usb_interface *control_interface;
+	struct usb_interface *data_interface;
+	struct usb_endpoint_descriptor *epctrl = NULL;
+	struct usb_endpoint_descriptor *epread = NULL;
+	struct usb_endpoint_descriptor *epwrite = NULL;
+	struct usb_device *usb_dev = interface_to_usbdev(intf);
+	struct xr_usb_serial *xr_usb_serial;
+	int minor;
+	int ctrlsize, readsize;
+	u8 *buf;
+	u8 ac_management_function = 0;
+	u8 call_management_function = 0;
+	int call_interface_num = -1;
+	int data_interface_num = -1;
+	unsigned long quirks;
+	int num_rx_buf;
+	int i;
+	int combined_interfaces = 0;
+	struct device *tty_dev;
+	int rv = -ENOMEM;
+
+	/* normal quirks */
+	quirks = (unsigned long)id->driver_info;
+
+	if (quirks == IGNORE_DEVICE)
+		return -ENODEV;
+
+	num_rx_buf = (quirks == SINGLE_RX_URB) ? 1 : XR_USB_SERIAL_NR;
+	
+    dev_dbg(&intf->dev, "USB_device_id idVendor:%04x, idProduct %04x\n",id->idVendor,id->idProduct);
+	
+	/* handle quirks deadly to normal probing*/
+	if (quirks == NO_UNION_NORMAL) {
+		data_interface = usb_ifnum_to_if(usb_dev, 1);
+		control_interface = usb_ifnum_to_if(usb_dev, 0);
+		goto skip_normal_probe;
+	}
+
+	/* normal probing*/
+	if (!buffer) {
+		dev_err(&intf->dev, "Weird descriptor references\n");
+		return -EINVAL;
+	}
+
+	if (!buflen) {
+		if (intf->cur_altsetting->endpoint &&
+				intf->cur_altsetting->endpoint->extralen &&
+				intf->cur_altsetting->endpoint->extra) {
+			dev_dbg(&intf->dev,
+				"Seeking extra descriptors on endpoint\n");
+			buflen = intf->cur_altsetting->endpoint->extralen;
+			buffer = intf->cur_altsetting->endpoint->extra;
+		} else {
+			dev_err(&intf->dev,
+				"Zero length descriptor references\n");
+			return -EINVAL;
+		}
+	}
+
+	while (buflen > 0) {
+		if (buffer[1] != USB_DT_CS_INTERFACE) {
+			dev_err(&intf->dev, "skipping garbage\n");
+			goto next_desc;
+		}
+
+		switch (buffer[2]) {
+		case USB_CDC_UNION_TYPE: /* we've found it */
+			if (union_header) {
+				dev_err(&intf->dev, "More than one "
+					"union descriptor, skipping ...\n");
+				goto next_desc;
+			}
+			union_header = (struct usb_cdc_union_desc *)buffer;
+			break;
+		case USB_CDC_COUNTRY_TYPE: /* export through sysfs*/
+			cfd = (struct usb_cdc_country_functional_desc *)buffer;
+			break;
+		case USB_CDC_HEADER_TYPE: /* maybe check version */
+			break; /* for now we ignore it */
+		case USB_CDC_ACM_TYPE:
+			ac_management_function = buffer[3];
+			break;
+		case USB_CDC_CALL_MANAGEMENT_TYPE:
+			call_management_function = buffer[3];
+			call_interface_num = buffer[4];
+			if ((quirks & NOT_A_MODEM) == 0 && (call_management_function & 3) != 3)
+				dev_err(&intf->dev, "This device cannot do calls on its own. It is not a modem.\n");
+			break;
+		default:
+			/* there are LOTS more CDC descriptors that
+			 * could legitimately be found here.
+			 */
+			dev_dbg(&intf->dev, "Ignoring descriptor: "
+					"type %02x, length %d\n",
+					buffer[2], buffer[0]);
+			break;
+		}
+next_desc:
+		buflen -= buffer[0];
+		buffer += buffer[0];
+	}
+
+	if (!union_header) {
+		if (call_interface_num > 0) {
+			dev_dbg(&intf->dev, "No union descriptor, using call management descriptor\n");
+			/* quirks for Droids MuIn LCD */
+			if (quirks & NO_DATA_INTERFACE)
+				data_interface = usb_ifnum_to_if(usb_dev, 0);
+			else
+				data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = call_interface_num));
+			control_interface = intf;
+		} else {
+			if (intf->cur_altsetting->desc.bNumEndpoints != 3) {
+				dev_dbg(&intf->dev,"No union descriptor, giving up\n");
+				return -ENODEV;
+			} else {
+				dev_warn(&intf->dev,"No union descriptor, testing for castrated device\n");
+				combined_interfaces = 1;
+				control_interface = data_interface = intf;
+				goto look_for_collapsed_interface;
+			}
+		}
+	} else {
+		control_interface = usb_ifnum_to_if(usb_dev, union_header->bMasterInterface0);
+		data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = union_header->bSlaveInterface0));
+		if (!control_interface || !data_interface) {
+			dev_dbg(&intf->dev, "no interfaces\n");
+			return -ENODEV;
+		}
+	}
+
+	if (data_interface_num != call_interface_num)
+		dev_dbg(&intf->dev, "Separate call control interface. That is not fully supported.\n");
+
+	if (control_interface == data_interface) {
+		/* some broken devices designed for windows work this way */
+		dev_warn(&intf->dev,"Control and data interfaces are not separated!\n");
+		combined_interfaces = 1;
+		/* a popular other OS doesn't use it */
+		quirks |= NO_CAP_LINE;
+		if (data_interface->cur_altsetting->desc.bNumEndpoints != 3) {
+			dev_err(&intf->dev, "This needs exactly 3 endpoints\n");
+			return -EINVAL;
+		}
+look_for_collapsed_interface:
+		for (i = 0; i < 3; i++) {
+			struct usb_endpoint_descriptor *ep;
+			ep = &data_interface->cur_altsetting->endpoint[i].desc;
+
+			if (usb_endpoint_is_int_in(ep))
+				epctrl = ep;
+			else if (usb_endpoint_is_bulk_out(ep))
+				epwrite = ep;
+			else if (usb_endpoint_is_bulk_in(ep))
+				epread = ep;
+			else
+				return -EINVAL;
+		}
+		if (!epctrl || !epread || !epwrite)
+			return -ENODEV;
+		else
+			goto made_compressed_probe;
+	}
+
+skip_normal_probe:
+
+	/*workaround for switched interfaces */
+	if (data_interface->cur_altsetting->desc.bInterfaceClass
+						!= CDC_DATA_INTERFACE_TYPE) {
+		if (control_interface->cur_altsetting->desc.bInterfaceClass
+						== CDC_DATA_INTERFACE_TYPE) {
+			struct usb_interface *t;
+			dev_dbg(&intf->dev,
+				"Your device has switched interfaces.\n");
+			t = control_interface;
+			control_interface = data_interface;
+			data_interface = t;
+		} else {
+			return -EINVAL;
+		}
+	}
+
+	/* Accept probe requests only for the control interface */
+	if (!combined_interfaces && intf != control_interface)
+		return -ENODEV;
+
+	if (!combined_interfaces && usb_interface_claimed(data_interface)) {
+		/* valid in this context */
+		dev_dbg(&intf->dev, "The data interface isn't available\n");
+		return -EBUSY;
+	}
+
+
+	if (data_interface->cur_altsetting->desc.bNumEndpoints < 2 ||
+	    control_interface->cur_altsetting->desc.bNumEndpoints == 0)
+		return -EINVAL;
+
+	epctrl = &control_interface->cur_altsetting->endpoint[0].desc;
+	epread = &data_interface->cur_altsetting->endpoint[0].desc;
+	epwrite = &data_interface->cur_altsetting->endpoint[1].desc;
+
+
+	/* workaround for switched endpoints */
+	if (!usb_endpoint_dir_in(epread)) {
+		/* descriptors are swapped */
+		struct usb_endpoint_descriptor *t;
+		dev_dbg(&intf->dev,
+			"The data interface has switched endpoints\n");
+		t = epread;
+		epread = epwrite;
+		epwrite = t;
+	}
+made_compressed_probe:
+	dev_dbg(&intf->dev, "interfaces are valid\n");
+
+	xr_usb_serial = kzalloc(sizeof(struct xr_usb_serial), GFP_KERNEL);
+	if (xr_usb_serial == NULL) {
+		dev_err(&intf->dev, "out of memory (xr_usb_serial kzalloc)\n");
+		goto alloc_fail;
+	}
+
+	minor = xr_usb_serial_alloc_minor(xr_usb_serial);
+	if (minor == XR_USB_SERIAL_TTY_MINORS) {
+		dev_err(&intf->dev, "no more free xr_usb_serial devices\n");
+		kfree(xr_usb_serial);
+		return -ENODEV;
+	}
+
+	ctrlsize = usb_endpoint_maxp(epctrl);
+	readsize = usb_endpoint_maxp(epread) *
+				(quirks == SINGLE_RX_URB ? 1 : 2);
+	xr_usb_serial->combined_interfaces = combined_interfaces;
+	xr_usb_serial->writesize = usb_endpoint_maxp(epwrite) * 20;
+	xr_usb_serial->control = control_interface;
+	xr_usb_serial->data = data_interface;
+	xr_usb_serial->minor = minor;
+	xr_usb_serial->dev = usb_dev;
+	xr_usb_serial->ctrl_caps = ac_management_function;
+	if (quirks & NO_CAP_LINE)
+		xr_usb_serial->ctrl_caps &= ~USB_CDC_CAP_LINE;
+	xr_usb_serial->ctrlsize = ctrlsize;
+	xr_usb_serial->readsize = readsize;
+	xr_usb_serial->rx_buflimit = num_rx_buf;
+	INIT_WORK(&xr_usb_serial->work, xr_usb_serial_softint);
+	spin_lock_init(&xr_usb_serial->write_lock);
+	spin_lock_init(&xr_usb_serial->read_lock);
+	mutex_init(&xr_usb_serial->mutex);
+	xr_usb_serial->rx_endpoint = usb_rcvbulkpipe(usb_dev, epread->bEndpointAddress);
+	xr_usb_serial->is_int_ep = usb_endpoint_xfer_int(epread);
+	if (xr_usb_serial->is_int_ep)
+		xr_usb_serial->bInterval = epread->bInterval;
+	tty_port_init(&xr_usb_serial->port);
+	xr_usb_serial->port.ops = &xr_usb_serial_port_ops;
+	xr_usb_serial->DeviceVendor = id->idVendor;
+	xr_usb_serial->DeviceProduct = id->idProduct;
+	#if 0
+	if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1410)
+	{//map the serial port A B C D to blocknum 0 1 2 3 for the xr21v141x device
+	    xr_usb_serial->channel = epwrite->bEndpointAddress - 1;
+	}
+	else if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1420)
+	{//map the serial port A B C D to blocknum 0 2 4 6 for the xr21B142x device
+	    xr_usb_serial->channel = (epwrite->bEndpointAddress - 4)*2;
+	}
+	else
+	{
+	   xr_usb_serial->channel = epwrite->bEndpointAddress;
+	}
+	#else
+	xr_usb_serial->channel = epwrite->bEndpointAddress;
+	dev_dbg(&intf->dev, "epwrite->bEndpointAddress =%d\n",epwrite->bEndpointAddress);
+	#endif
+	buf = usb_alloc_coherent(usb_dev, ctrlsize, GFP_KERNEL, &xr_usb_serial->ctrl_dma);
+	if (!buf) {
+		dev_err(&intf->dev, "out of memory (ctrl buffer alloc)\n");
+		goto alloc_fail2;
+	}
+	xr_usb_serial->ctrl_buffer = buf;
+
+	if (xr_usb_serial_write_buffers_alloc(xr_usb_serial) < 0) {
+		dev_err(&intf->dev, "out of memory (write buffer alloc)\n");
+		goto alloc_fail4;
+	}
+
+	xr_usb_serial->ctrlurb = usb_alloc_urb(0, GFP_KERNEL);
+	if (!xr_usb_serial->ctrlurb) {
+		dev_err(&intf->dev, "out of memory (ctrlurb kmalloc)\n");
+		goto alloc_fail5;
+	}
+	for (i = 0; i < num_rx_buf; i++) {
+		struct xr_usb_serial_rb *rb = &(xr_usb_serial->read_buffers[i]);
+		struct urb *urb;
+
+		rb->base = usb_alloc_coherent(xr_usb_serial->dev, readsize, GFP_KERNEL,
+								&rb->dma);
+		if (!rb->base) {
+			dev_err(&intf->dev, "out of memory "
+					"(read bufs usb_alloc_coherent)\n");
+			goto alloc_fail6;
+		}
+		rb->index = i;
+		rb->instance = xr_usb_serial;
+
+		urb = usb_alloc_urb(0, GFP_KERNEL);
+		if (!urb) {
+			dev_err(&intf->dev,
+				"out of memory (read urbs usb_alloc_urb)\n");
+			goto alloc_fail6;
+		}
+		urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+		urb->transfer_dma = rb->dma;
+		if (xr_usb_serial->is_int_ep) {
+			usb_fill_int_urb(urb, xr_usb_serial->dev,
+					 xr_usb_serial->rx_endpoint,
+					 rb->base,
+					 xr_usb_serial->readsize,
+					 xr_usb_serial_read_bulk_callback, rb,
+					 xr_usb_serial->bInterval);
+		} else {
+			usb_fill_bulk_urb(urb, xr_usb_serial->dev,
+					  xr_usb_serial->rx_endpoint,
+					  rb->base,
+					  xr_usb_serial->readsize,
+					  xr_usb_serial_read_bulk_callback, rb);
+		}
+
+		xr_usb_serial->read_urbs[i] = urb;
+		__set_bit(i, &xr_usb_serial->read_urbs_free);
+	}
+	for (i = 0; i < XR_USB_SERIAL_NW; i++) {
+		struct xr_usb_serial_wb *snd = &(xr_usb_serial->wb[i]);
+
+		snd->urb = usb_alloc_urb(0, GFP_KERNEL);
+		if (snd->urb == NULL) {
+			dev_err(&intf->dev,
+				"out of memory (write urbs usb_alloc_urb)\n");
+			goto alloc_fail7;
+		}
+
+		if (usb_endpoint_xfer_int(epwrite))
+			usb_fill_int_urb(snd->urb, usb_dev,
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0)			
+				usb_sndbulkpipe(usb_dev, epwrite->bEndpointAddress),
+#else
+                usb_sndintpipe(usb_dev, epwrite->bEndpointAddress),
+#endif
+				NULL, xr_usb_serial->writesize, xr_usb_serial_write_bulk, snd, epwrite->bInterval);
+		else
+			usb_fill_bulk_urb(snd->urb, usb_dev,
+				usb_sndbulkpipe(usb_dev, epwrite->bEndpointAddress),
+				NULL, xr_usb_serial->writesize, xr_usb_serial_write_bulk, snd);
+		snd->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+		snd->instance = xr_usb_serial;
+	}
+
+	usb_set_intfdata(intf, xr_usb_serial);
+
+	i = device_create_file(&intf->dev, &dev_attr_bmCapabilities);
+	if (i < 0)
+		goto alloc_fail7;
+
+	if (cfd) { /* export the country data */
+		xr_usb_serial->country_codes = kmalloc(cfd->bLength - 4, GFP_KERNEL);
+		if (!xr_usb_serial->country_codes)
+			goto skip_countries;
+		xr_usb_serial->country_code_size = cfd->bLength - 4;
+		memcpy(xr_usb_serial->country_codes, (u8 *)&cfd->wCountyCode0,
+							cfd->bLength - 4);
+		xr_usb_serial->country_rel_date = cfd->iCountryCodeRelDate;
+
+		i = device_create_file(&intf->dev, &dev_attr_wCountryCodes);
+		if (i < 0) {
+			kfree(xr_usb_serial->country_codes);
+			xr_usb_serial->country_codes = NULL;
+			xr_usb_serial->country_code_size = 0;
+			goto skip_countries;
+		}
+
+		i = device_create_file(&intf->dev,
+						&dev_attr_iCountryCodeRelDate);
+		if (i < 0) {
+			device_remove_file(&intf->dev, &dev_attr_wCountryCodes);
+			kfree(xr_usb_serial->country_codes);
+			xr_usb_serial->country_codes = NULL;
+			xr_usb_serial->country_code_size = 0;
+			goto skip_countries;
+		}
+	}
+
+skip_countries:
+	usb_fill_int_urb(xr_usb_serial->ctrlurb, usb_dev,
+			 usb_rcvintpipe(usb_dev, epctrl->bEndpointAddress),
+			 xr_usb_serial->ctrl_buffer, ctrlsize, xr_usb_serial_ctrl_irq, xr_usb_serial,
+			 /* works around buggy devices */
+			 epctrl->bInterval ? epctrl->bInterval : 0xff);
+	xr_usb_serial->ctrlurb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+	xr_usb_serial->ctrlurb->transfer_dma = xr_usb_serial->ctrl_dma;
+
+	dev_info(&intf->dev, "ttyXR_USB_SERIAL%d: USB XR_USB_SERIAL device\n", minor);
+	
+    xr_usb_serial_pre_setup(xr_usb_serial);
+	
+	xr_usb_serial_set_control(xr_usb_serial, xr_usb_serial->ctrlout);
+
+	xr_usb_serial->line.dwDTERate = cpu_to_le32(9600);
+	xr_usb_serial->line.bDataBits = 8;
+	xr_usb_serial_set_line(xr_usb_serial, &xr_usb_serial->line);
+    
+	usb_driver_claim_interface(&xr_usb_serial_driver, data_interface, xr_usb_serial);
+	usb_set_intfdata(data_interface, xr_usb_serial);
+
+	usb_get_intf(control_interface);
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0)
+    tty_register_device(xr_usb_serial_tty_driver, minor, &control_interface->dev);
+#else
+	tty_dev = tty_port_register_device(&xr_usb_serial->port, xr_usb_serial_tty_driver, minor,
+			&control_interface->dev);
+	if (IS_ERR(tty_dev)) {
+		rv = PTR_ERR(tty_dev);
+		goto alloc_fail8;
+	}
+#endif	
+
+	return 0;
+alloc_fail8:
+	if (xr_usb_serial->country_codes) {
+		device_remove_file(&xr_usb_serial->control->dev,
+				&dev_attr_wCountryCodes);
+		device_remove_file(&xr_usb_serial->control->dev,
+				&dev_attr_iCountryCodeRelDate);
+	}
+	device_remove_file(&xr_usb_serial->control->dev, &dev_attr_bmCapabilities);
+alloc_fail7:
+	usb_set_intfdata(intf, NULL);
+	for (i = 0; i < XR_USB_SERIAL_NW; i++)
+		usb_free_urb(xr_usb_serial->wb[i].urb);
+alloc_fail6:
+	for (i = 0; i < num_rx_buf; i++)
+		usb_free_urb(xr_usb_serial->read_urbs[i]);
+	xr_usb_serial_read_buffers_free(xr_usb_serial);
+	usb_free_urb(xr_usb_serial->ctrlurb);
+alloc_fail5:
+	xr_usb_serial_write_buffers_free(xr_usb_serial);
+alloc_fail4:
+	usb_free_coherent(usb_dev, ctrlsize, xr_usb_serial->ctrl_buffer, xr_usb_serial->ctrl_dma);
+alloc_fail2:
+	xr_usb_serial_release_minor(xr_usb_serial);
+	kfree(xr_usb_serial);
+alloc_fail:
+	return rv;
+}
+
+static void stop_data_traffic(struct xr_usb_serial *xr_usb_serial)
+{
+	int i;
+
+	dev_dbg(&xr_usb_serial->control->dev, "%s\n", __func__);
+
+	usb_kill_urb(xr_usb_serial->ctrlurb);
+	for (i = 0; i < XR_USB_SERIAL_NW; i++)
+		usb_kill_urb(xr_usb_serial->wb[i].urb);
+	for (i = 0; i < xr_usb_serial->rx_buflimit; i++)
+		usb_kill_urb(xr_usb_serial->read_urbs[i]);
+
+	cancel_work_sync(&xr_usb_serial->work);
+}
+
+static void xr_usb_serial_disconnect(struct usb_interface *intf)
+{
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+	struct usb_device *usb_dev = interface_to_usbdev(intf);
+	struct tty_struct *tty;
+	int i;
+
+	dev_dbg(&intf->dev, "%s\n", __func__);
+
+	/* sibling interface is already cleaning up */
+	if (!xr_usb_serial)
+		return;
+
+	mutex_lock(&xr_usb_serial->mutex);
+	xr_usb_serial->disconnected = true;
+	if (xr_usb_serial->country_codes) {
+		device_remove_file(&xr_usb_serial->control->dev,
+				&dev_attr_wCountryCodes);
+		device_remove_file(&xr_usb_serial->control->dev,
+				&dev_attr_iCountryCodeRelDate);
+	}
+	device_remove_file(&xr_usb_serial->control->dev, &dev_attr_bmCapabilities);
+	usb_set_intfdata(xr_usb_serial->control, NULL);
+	usb_set_intfdata(xr_usb_serial->data, NULL);
+	mutex_unlock(&xr_usb_serial->mutex);
+
+	tty = tty_port_tty_get(&xr_usb_serial->port);
+	if (tty) {
+		tty_vhangup(tty);
+		tty_kref_put(tty);
+	}
+	stop_data_traffic(xr_usb_serial);
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 7, 0)
+	tty_unregister_device(xr_usb_serial_tty_driver, xr_usb_serial->minor);
+#endif
+
+	usb_free_urb(xr_usb_serial->ctrlurb);
+	for (i = 0; i < XR_USB_SERIAL_NW; i++)
+		usb_free_urb(xr_usb_serial->wb[i].urb);
+	for (i = 0; i < xr_usb_serial->rx_buflimit; i++)
+		usb_free_urb(xr_usb_serial->read_urbs[i]);
+	xr_usb_serial_write_buffers_free(xr_usb_serial);
+	usb_free_coherent(usb_dev, xr_usb_serial->ctrlsize, xr_usb_serial->ctrl_buffer, xr_usb_serial->ctrl_dma);
+	xr_usb_serial_read_buffers_free(xr_usb_serial);
+
+	if (!xr_usb_serial->combined_interfaces)
+		usb_driver_release_interface(&xr_usb_serial_driver, intf == xr_usb_serial->control ?
+					xr_usb_serial->data : xr_usb_serial->control);
+
+	tty_port_put(&xr_usb_serial->port);
+}
+
+#ifdef CONFIG_PM
+static int xr_usb_serial_suspend(struct usb_interface *intf, pm_message_t message)
+{
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+	int cnt;
+
+	if (PMSG_IS_AUTO(message)) {
+		int b;
+
+		spin_lock_irq(&xr_usb_serial->write_lock);
+		b = xr_usb_serial->transmitting;
+		spin_unlock_irq(&xr_usb_serial->write_lock);
+		if (b)
+			return -EBUSY;
+	}
+
+	spin_lock_irq(&xr_usb_serial->read_lock);
+	spin_lock(&xr_usb_serial->write_lock);
+	cnt = xr_usb_serial->susp_count++;
+	spin_unlock(&xr_usb_serial->write_lock);
+	spin_unlock_irq(&xr_usb_serial->read_lock);
+
+	if (cnt)
+		return 0;
+
+	if (test_bit(ASYNCB_INITIALIZED, &xr_usb_serial->port.flags))
+		stop_data_traffic(xr_usb_serial);
+
+	return 0;
+}
+
+static int xr_usb_serial_resume(struct usb_interface *intf)
+{
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+	struct xr_usb_serial_wb *wb;
+	int rv = 0;
+	int cnt;
+
+	spin_lock_irq(&xr_usb_serial->read_lock);
+	xr_usb_serial->susp_count -= 1;
+	cnt = xr_usb_serial->susp_count;
+	spin_unlock_irq(&xr_usb_serial->read_lock);
+
+	if (cnt)
+		return 0;
+
+	if (test_bit(ASYNCB_INITIALIZED, &xr_usb_serial->port.flags)) {
+		rv = usb_submit_urb(xr_usb_serial->ctrlurb, GFP_NOIO);
+
+		spin_lock_irq(&xr_usb_serial->write_lock);
+		if (xr_usb_serial->delayed_wb) {
+			wb = xr_usb_serial->delayed_wb;
+			xr_usb_serial->delayed_wb = NULL;
+			spin_unlock_irq(&xr_usb_serial->write_lock);
+			xr_usb_serial_start_wb(xr_usb_serial, wb);
+		} else {
+			spin_unlock_irq(&xr_usb_serial->write_lock);
+		}
+
+		/*
+		 * delayed error checking because we must
+		 * do the write path at all cost
+		 */
+		if (rv < 0)
+			goto err_out;
+
+		rv = xr_usb_serial_submit_read_urbs(xr_usb_serial, GFP_NOIO);
+	}
+
+err_out:
+	return rv;
+}
+
+static int xr_usb_serial_reset_resume(struct usb_interface *intf)
+{
+	struct xr_usb_serial *xr_usb_serial = usb_get_intfdata(intf);
+    struct tty_struct *tty;
+	if (test_bit(ASYNCB_INITIALIZED, &xr_usb_serial->port.flags)){
+#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 9, 0)	
+	tty_port_tty_hangup(&xr_usb_serial->port, false);
+#else
+ 	tty = tty_port_tty_get(&xr_usb_serial->port);
+	if (tty) {
+		tty_hangup(tty);
+		tty_kref_put(tty);
+	}
+#endif
+	}
+	return xr_usb_serial_resume(intf);
+}
+
+#endif /* CONFIG_PM */
+
+/*
+ * USB driver structure.
+ */
+static const struct usb_device_id xr_usb_serial_ids[] = {
+	{ USB_DEVICE(0x04e2, 0x1410)},
+    { USB_DEVICE(0x04e2, 0x1411)},
+	{ USB_DEVICE(0x04e2, 0x1412)},
+	{ USB_DEVICE(0x04e2, 0x1414)},
+	{ USB_DEVICE(0x04e2, 0x1420)},
+    { USB_DEVICE(0x04e2, 0x1421)},
+	{ USB_DEVICE(0x04e2, 0x1422)},
+	{ USB_DEVICE(0x04e2, 0x1424)},
+	{ USB_DEVICE(0x04e2, 0x1400)},
+    { USB_DEVICE(0x04e2, 0x1401)},
+    { USB_DEVICE(0x04e2, 0x1402)},
+    { USB_DEVICE(0x04e2, 0x1403)},
+    // Teknic COM4-HUB
+    { USB_DEVICE(0x2890, 0x0213)},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(usb, xr_usb_serial_ids);
+
+static struct usb_driver xr_usb_serial_driver = {
+	.name =		"cdc_xr_usb_serial",
+	.probe =	xr_usb_serial_probe,
+	.disconnect =	xr_usb_serial_disconnect,
+#ifdef CONFIG_PM
+	.suspend =	xr_usb_serial_suspend,
+	.resume =	xr_usb_serial_resume,
+	.reset_resume =	xr_usb_serial_reset_resume,
+#endif
+	.id_table =	xr_usb_serial_ids,
+#ifdef CONFIG_PM
+	.supports_autosuspend = 1,
+#endif
+	.disable_hub_initiated_lpm = 1,
+};
+
+/*
+ * TTY driver structures.
+ */
+
+static const struct tty_operations xr_usb_serial_ops = {
+	.install =		xr_usb_serial_tty_install,
+	.open =			xr_usb_serial_tty_open,
+	.close =		xr_usb_serial_tty_close,
+	.cleanup =		xr_usb_serial_tty_cleanup,
+	.hangup =		xr_usb_serial_tty_hangup,
+	.write =		xr_usb_serial_tty_write,
+	.write_room =		xr_usb_serial_tty_write_room,
+	.ioctl =		xr_usb_serial_tty_ioctl,
+	.throttle =		xr_usb_serial_tty_throttle,
+	.unthrottle =		xr_usb_serial_tty_unthrottle,
+	.chars_in_buffer =	xr_usb_serial_tty_chars_in_buffer,
+	.break_ctl =		xr_usb_serial_tty_break_ctl,
+	.set_termios =		xr_usb_serial_tty_set_termios,
+	.tiocmget =		xr_usb_serial_tty_tiocmget,
+	.tiocmset =		xr_usb_serial_tty_tiocmset,
+};
+
+/*
+ * Init / exit.
+ */
+
+static int __init xr_usb_serial_init(void)
+{
+	int retval;
+	xr_usb_serial_tty_driver = alloc_tty_driver(XR_USB_SERIAL_TTY_MINORS);
+	if (!xr_usb_serial_tty_driver)
+		return -ENOMEM;
+	xr_usb_serial_tty_driver->driver_name = "xr_usb_serial",
+	xr_usb_serial_tty_driver->name = "ttyXRUSB",
+	xr_usb_serial_tty_driver->major = XR_USB_SERIAL_TTY_MAJOR,
+	xr_usb_serial_tty_driver->minor_start = 0,
+	xr_usb_serial_tty_driver->type = TTY_DRIVER_TYPE_SERIAL,
+	xr_usb_serial_tty_driver->subtype = SERIAL_TYPE_NORMAL,
+	xr_usb_serial_tty_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
+	xr_usb_serial_tty_driver->init_termios = tty_std_termios;
+	xr_usb_serial_tty_driver->init_termios.c_cflag = B9600 | CS8 | CREAD |
+								HUPCL | CLOCAL;
+	tty_set_operations(xr_usb_serial_tty_driver, &xr_usb_serial_ops);
+
+	retval = tty_register_driver(xr_usb_serial_tty_driver);
+	if (retval) {
+		put_tty_driver(xr_usb_serial_tty_driver);
+		return retval;
+	}
+
+	retval = usb_register(&xr_usb_serial_driver);
+	if (retval) {
+		tty_unregister_driver(xr_usb_serial_tty_driver);
+		put_tty_driver(xr_usb_serial_tty_driver);
+		return retval;
+	}
+
+	printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_DESC "\n");
+
+	return 0;
+}
+
+static void __exit xr_usb_serial_exit(void)
+{
+	usb_deregister(&xr_usb_serial_driver);
+	tty_unregister_driver(xr_usb_serial_tty_driver);
+	put_tty_driver(xr_usb_serial_tty_driver);
+}
+
+module_init(xr_usb_serial_init);
+module_exit(xr_usb_serial_exit);
+
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_CHARDEV_MAJOR(XR_USB_SERIAL_TTY_MAJOR);
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_common.h b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_common.h
new file mode 100644
index 000000000..26e8d311c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_common.h
@@ -0,0 +1,191 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * CMSPAR, some architectures can't have space and mark parity.
+ */
+
+#ifndef CMSPAR
+#define CMSPAR			0
+#endif
+
+/*
+ * Major and minor numbers.
+ */
+
+#define XR_USB_SERIAL_TTY_MAJOR		    266
+#define XR_USB_SERIAL_TTY_MINORS		32
+
+/*
+ * Requests.
+ */
+
+#define USB_RT_XR_USB_SERIAL		(USB_TYPE_CLASS | USB_RECIP_INTERFACE)
+
+/*
+ * Output control lines.
+ */
+
+#define XR_USB_SERIAL_CTRL_DTR		0x01
+#define XR_USB_SERIAL_CTRL_RTS		0x02
+
+/*
+ * Input control lines and line errors.
+ */
+
+#define XR_USB_SERIAL_CTRL_DCD		0x01
+#define XR_USB_SERIAL_CTRL_DSR		0x02
+#define XR_USB_SERIAL_CTRL_BRK		0x04
+#define XR_USB_SERIAL_CTRL_RI		0x08
+
+#define XR_USB_SERIAL_CTRL_FRAMING	0x10
+#define XR_USB_SERIAL_CTRL_PARITY		0x20
+#define XR_USB_SERIAL_CTRL_OVERRUN	0x40
+
+// Teknic additions
+#define TEKNIC_VID 					0x2890
+#define TEKNIC_COM4_HUB_PID 		0x0213
+
+
+/*
+ * Internal driver structures.
+ */
+
+/*
+ * The only reason to have several buffers is to accommodate assumptions
+ * in line disciplines. They ask for empty space amount, receive our URB size,
+ * and proceed to issue several 1-character writes, assuming they will fit.
+ * The very first write takes a complete URB. Fortunately, this only happens
+ * when processing onlcr, so we only need 2 buffers. These values must be
+ * powers of 2.
+ */
+#define XR_USB_SERIAL_NW  16
+#define XR_USB_SERIAL_NR  16
+
+struct xr_usb_serial_wb {
+	unsigned char *buf;
+	dma_addr_t dmah;
+	int len;
+	int use;
+	struct urb		*urb;
+	struct xr_usb_serial		*instance;
+};
+
+struct xr_usb_serial_rb {
+	int			size;
+	unsigned char		*base;
+	dma_addr_t		dma;
+	int			index;
+	struct xr_usb_serial		*instance;
+};
+
+struct reg_addr_map {
+	unsigned int    uart_enable_addr;
+	unsigned int    uart_format_addr;
+	unsigned int    uart_flow_addr;
+	unsigned int    uart_loopback_addr;
+    unsigned int    uart_xon_char_addr;
+	unsigned int    uart_xoff_char_addr;
+	unsigned int    uart_gpio_mode_addr;
+	unsigned int    uart_gpio_dir_addr;
+	unsigned int    uart_gpio_set_addr;
+	unsigned int    uart_gpio_clr_addr;
+	unsigned int    uart_gpio_status_addr;
+	unsigned int    tx_break_addr;
+	unsigned int    uart_custom_driver;
+	unsigned int    uart_low_latency;
+};
+
+struct xr_usb_serial {
+	struct usb_device *dev;				/* the corresponding usb device */
+	struct usb_interface *control;			/* control interface */
+	struct usb_interface *data;			/* data interface */
+	struct tty_port port;			 	/* our tty port data */
+	struct urb *ctrlurb;				/* urbs */
+	u8 *ctrl_buffer;				/* buffers of urbs */
+	dma_addr_t ctrl_dma;				/* dma handles of buffers */
+	u8 *country_codes;				/* country codes from device */
+	unsigned int country_code_size;			/* size of this buffer */
+	unsigned int country_rel_date;			/* release date of version */
+	struct xr_usb_serial_wb wb[XR_USB_SERIAL_NW];
+	unsigned long read_urbs_free;
+	struct urb *read_urbs[XR_USB_SERIAL_NR];
+	struct xr_usb_serial_rb read_buffers[XR_USB_SERIAL_NR];
+	int rx_buflimit;
+	int rx_endpoint;
+	spinlock_t read_lock;
+	int write_used;					/* number of non-empty write buffers */
+	int transmitting;
+	spinlock_t write_lock;
+	struct mutex mutex;
+	bool disconnected;
+	struct usb_cdc_line_coding line;		/* bits, stop, parity */
+	struct work_struct work;			/* work queue entry for line discipline waking up */
+	unsigned int ctrlin;				/* input control lines (DCD, DSR, RI, break, overruns) */
+	unsigned int ctrlout;				/* output control lines (DTR, RTS) */
+	unsigned int writesize;				/* max packet size for the output bulk endpoint */
+	unsigned int readsize,ctrlsize;			/* buffer sizes for freeing */
+	unsigned int minor;				/* xr_usb_serial minor number */
+	unsigned char clocal;				/* termios CLOCAL */
+	unsigned int ctrl_caps;				/* control capabilities from the class specific header */
+	unsigned int susp_count;			/* number of suspended interfaces */
+	unsigned int combined_interfaces:1;		/* control and data collapsed */
+	unsigned int is_int_ep:1;			/* interrupt endpoints contrary to spec used */
+	unsigned int throttled:1;			/* actually throttled */
+	unsigned int throttle_req:1;			/* throttle requested */
+	u8 bInterval;
+	struct xr_usb_serial_wb *delayed_wb;			/* write queued for a device about to be woken */
+	unsigned int channel;
+	unsigned short DeviceVendor;
+	unsigned short DeviceProduct;
+	struct reg_addr_map reg_map;
+};
+
+#define CDC_DATA_INTERFACE_TYPE	0x0a
+
+/* constants describing various quirks and errors */
+#define NO_UNION_NORMAL			1
+#define SINGLE_RX_URB			2
+#define NO_CAP_LINE			4
+#define NOT_A_MODEM			8
+#define NO_DATA_INTERFACE		16
+#define IGNORE_DEVICE			32
+
+
+#define UART_ENABLE_TX                     1
+#define UART_ENABLE_RX                     2
+
+#define UART_GPIO_CLR_DTR                0x8
+#define UART_GPIO_SET_DTR                0x8
+#define UART_GPIO_CLR_RTS                0x20         
+#define UART_GPIO_SET_RTS                0x20
+
+#define LOOPBACK_ENABLE_TX_RX             1
+#define LOOPBACK_ENABLE_RTS_CTS           2
+#define LOOPBACK_ENABLE_DTR_DSR           4
+
+#define UART_FLOW_MODE_NONE              0x0
+#define UART_FLOW_MODE_HW                0x1
+#define UART_FLOW_MODE_SW                0x2
+
+#define UART_GPIO_MODE_SEL_GPIO          0x0
+#define UART_GPIO_MODE_SEL_RTS_CTS       0x1
+
+#define XR2280x_FUNC_MGR_OFFSET           0x40
+
+
+
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_hal.c b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_hal.c
new file mode 100644
index 000000000..d2708e8ca
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_hal.c
@@ -0,0 +1,747 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+ 
+#define XR_SET_MAP_XR2280X              5
+#define XR_GET_MAP_XR2280X              5
+
+#define XR_SET_MAP_XR21B142X             0
+#define XR_GET_MAP_XR21B142X             0
+
+#define XR_SET_MAP_XR21V141X             0
+#define XR_GET_MAP_XR21V141X             1
+
+#define XR_SET_MAP_XR21B1411             0
+#define XR_GET_MAP_XR21B1411             1
+
+
+int xr_usb_serial_set_reg(struct xr_usb_serial *xr_usb_serial,int regnum, int value)
+{
+	int result;
+	int channel = 0;
+	dev_dbg(&xr_usb_serial->control->dev, "%s Channel:%d 0x%02x = 0x%02x\n", __func__,channel,regnum, value);
+	if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1400)
+	{
+	    int XR2280xaddr = XR2280x_FUNC_MGR_OFFSET + regnum; 
+		result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+	                             usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+	                             XR_SET_MAP_XR2280X,                      /* request */
+	                             USB_DIR_OUT | USB_TYPE_VENDOR,   /* request_type */
+	                             value,                           /* request value */
+	                             XR2280xaddr,           /* index */
+	                             NULL,                            /* data */
+	                             0,                               /* size */
+	                             5000);                           /* timeout */
+
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1410) ||
+		    (xr_usb_serial->DeviceProduct == 0x1412) ||
+		    (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+
+		if(xr_usb_serial->channel)
+			channel = xr_usb_serial->channel - 1;
+ 		result = usb_control_msg(xr_usb_serial->dev,					  /* usb device */
+										usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+										XR_SET_MAP_XR21V141X, 					 /* request */
+										USB_DIR_OUT | USB_TYPE_VENDOR,	 /* request_type */
+										value,							 /* request value */
+										regnum | (channel << 8),			 /* index */
+										NULL,							 /* data */
+										0,								 /* size */
+										5000);							 /* timeout */
+	}
+	else if(xr_usb_serial->DeviceProduct == 0x1411 || xr_usb_serial->DeviceVendor == TEKNIC_VID)
+	{
+	    result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_SET_MAP_XR21B1411,                   /* request */
+                                 USB_DIR_OUT | USB_TYPE_VENDOR ,        /* request_type */
+                                 value,                           /* request value */
+                                 regnum ,                         /* index */
+                                 NULL,                            /* data */
+                                 0,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1420)||
+		   (xr_usb_serial->DeviceProduct == 0x1422)||
+		   (xr_usb_serial->DeviceProduct == 0x1424))
+		
+	{
+	   
+		channel = (xr_usb_serial->channel - 4)*2;
+        result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_SET_MAP_XR21B142X,                   /* request */
+                                 USB_DIR_OUT | USB_TYPE_VENDOR | 1,   /* request_type */
+                                 value,                           /* request value */
+                                 regnum | (channel << 8),           /* index */
+                                 NULL,                            /* data */
+                                 0,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else
+	{
+	    result = -1;
+	}
+	if(result < 0)
+		dev_dbg(&xr_usb_serial->control->dev, "%s Error:%d\n", __func__,result);
+    return result;
+	
+       
+}
+int xr_usb_serial_set_reg_ext(struct xr_usb_serial *xr_usb_serial,int channel,int regnum, int value)
+{
+	int result;
+	int XR2280xaddr = XR2280x_FUNC_MGR_OFFSET + regnum; 
+	dev_dbg(&xr_usb_serial->control->dev, "%s channel:%d 0x%02x = 0x%02x\n", __func__,channel,regnum, value);
+	if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1400)
+	{
+		result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+	                             usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+	                             XR_SET_MAP_XR2280X,                      /* request */
+	                             USB_DIR_OUT | USB_TYPE_VENDOR,   /* request_type */
+	                             value,                           /* request value */
+	                             XR2280xaddr,           /* index */
+	                             NULL,                            /* data */
+	                             0,                               /* size */
+	                             5000);                           /* timeout */
+
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1410) ||
+		    (xr_usb_serial->DeviceProduct == 0x1412) ||
+		    (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+       	result = usb_control_msg(xr_usb_serial->dev,					  /* usb device */
+										usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+										XR_SET_MAP_XR21V141X, 					 /* request */
+										USB_DIR_OUT | USB_TYPE_VENDOR,	 /* request_type */
+										value,							 /* request value */
+										regnum | (channel << 8),			 /* index */
+										NULL,							 /* data */
+										0,								 /* size */
+										5000);							 /* timeout */
+	}
+	else if(xr_usb_serial->DeviceProduct == 0x1411 || xr_usb_serial->DeviceVendor == TEKNIC_VID)
+	{
+	    result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_SET_MAP_XR21B1411,                   /* request */
+                                 USB_DIR_OUT | USB_TYPE_VENDOR ,        /* request_type */
+                                 value,                           /* request value */
+                                 regnum ,                         /* index */
+                                 NULL,                            /* data */
+                                 0,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1420)||
+		    (xr_usb_serial->DeviceProduct == 0x1422)||
+		     (xr_usb_serial->DeviceProduct == 0x1424))
+	{
+	    result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_SET_MAP_XR21B142X,                   /* request */
+                                 USB_DIR_OUT | USB_TYPE_VENDOR | 1,   /* request_type */
+                                 value,                           /* request value */
+                                 regnum | (channel << 8),           /* index */
+                                 NULL,                            /* data */
+                                 0,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else
+	{
+	    result = -1;
+	}
+	if(result < 0)
+		dev_dbg(&xr_usb_serial->control->dev, "%s Error:%d\n", __func__,result);
+    return result;
+	
+       
+}
+
+int xr_usb_serial_get_reg(struct xr_usb_serial *xr_usb_serial,int regnum, short *value)
+{
+	int result;
+	int channel = 0;
+	
+	if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1400)
+	{
+		int XR2280xaddr = XR2280x_FUNC_MGR_OFFSET + regnum; 
+    	result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR2280X,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR ,    /* request_type */
+                                 0,                               /* request value */
+                                 XR2280xaddr,                    /* index */
+                                 value,                           /* data */
+                                 2,                               /* size */
+                                 5000);                           /* timeout */
+		
+				
+		
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1410) ||
+		    (xr_usb_serial->DeviceProduct == 0x1412) ||
+		    (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+	   if(xr_usb_serial->channel)
+	   channel = xr_usb_serial->channel -1;
+       result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR21V141X,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR,    /* request_type */
+                                 0,                               /* request value */
+                                 regnum | (channel << 8),              /* index */
+                                 value,                           /* data */
+                                 1,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else if(xr_usb_serial->DeviceProduct == 0x1411 || xr_usb_serial->DeviceVendor == TEKNIC_VID)
+	{
+	     result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR21B1411,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR,    /* request_type */
+                                 0,                               /* request value */
+                                 regnum,                          /* index */
+                                 value,                           /* data */
+                                 2,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1420)||
+		    (xr_usb_serial->DeviceProduct == 0x1422)||
+		    (xr_usb_serial->DeviceProduct == 0x1424))
+		   
+	{
+	  channel = (xr_usb_serial->channel -4)*2;
+      result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR21B142X,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR | 1,    /* request_type */
+                                 0,                               /* request value */
+                                 regnum | (channel << 8),              /* index */
+                                 value,                           /* data */
+                                 2,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else
+	{
+	    result = -1;
+	}
+	
+	if(result < 0)
+		dev_dbg(&xr_usb_serial->control->dev, "%s channel:%d Reg 0x%x Error:%d\n", __func__,channel,regnum,result);
+	else
+	    dev_dbg(&xr_usb_serial->control->dev, "%s channel:%d 0x%x = 0x%04x\n", __func__,channel,regnum, *value);
+	
+	return result;
+
+}
+
+
+int xr_usb_serial_get_reg_ext(struct xr_usb_serial *xr_usb_serial,int channel,int regnum, short *value)
+{
+	int result;
+	int XR2280xaddr = XR2280x_FUNC_MGR_OFFSET + regnum; 
+	if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1400)
+	{
+		
+    	result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR2280X,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR ,    /* request_type */
+                                 0,                               /* request value */
+                                 XR2280xaddr,                    /* index */
+                                 value,                           /* data */
+                                 2,                               /* size */
+                                 5000);                           /* timeout */
+		
+				
+		
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1410) ||
+		    (xr_usb_serial->DeviceProduct == 0x1412) ||
+		    (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+	   unsigned char reg_value = 0;
+	   result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR21V141X,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR,    /* request_type */
+                                 0,                               /* request value */
+                                 regnum | (channel << 8),              /* index */
+                                 &reg_value,                           /* data */
+                                 1,                               /* size */
+                                 5000);                           /* timeout */
+	   dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_get_reg_ext reg:%x\n",reg_value);
+	   *value = reg_value; 
+	}
+	else if(xr_usb_serial->DeviceProduct == 0x1411 || xr_usb_serial->DeviceVendor == TEKNIC_VID)
+	{
+	     result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR21B1411,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR ,       /* request_type */
+                                 0,                               /* request value */
+                                 regnum | (channel << 8),              /* index */
+                                 value,                           /* data */
+                                 2,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1420)||
+		    (xr_usb_serial->DeviceProduct == 0x1422)||
+		    (xr_usb_serial->DeviceProduct == 0x1424))
+	{
+	   result = usb_control_msg(xr_usb_serial->dev,                     /* usb device */
+                                 usb_rcvctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */
+                                 XR_GET_MAP_XR21B142X,                     /* request */
+                                 USB_DIR_IN | USB_TYPE_VENDOR | 1,    /* request_type */
+                                 0,                               /* request value */
+                                 regnum | (channel << 8),              /* index */
+                                 value,                           /* data */
+                                 2,                               /* size */
+                                 5000);                           /* timeout */
+	}
+	else
+	{
+	    result = -1;
+	}
+	
+	if(result < 0)
+		dev_dbg(&xr_usb_serial->control->dev, "%s Error:%d\n", __func__,result);
+	else
+	    dev_dbg(&xr_usb_serial->control->dev, "%s channel:%d 0x%x = 0x%04x\n", __func__,channel,regnum, *value);
+	
+	return result;
+
+}
+
+struct xr21v141x_baud_rate
+{
+	unsigned int tx;
+	unsigned int rx0;
+	unsigned int rx1;
+};
+
+static struct xr21v141x_baud_rate xr21v141x_baud_rates[] = {
+	{ 0x000, 0x000, 0x000 },
+	{ 0x000, 0x000, 0x000 },
+	{ 0x100, 0x000, 0x100 },
+	{ 0x020, 0x400, 0x020 },
+	{ 0x010, 0x100, 0x010 },
+	{ 0x208, 0x040, 0x208 },
+	{ 0x104, 0x820, 0x108 },
+	{ 0x844, 0x210, 0x884 },
+	{ 0x444, 0x110, 0x444 },
+	{ 0x122, 0x888, 0x224 },
+	{ 0x912, 0x448, 0x924 },
+	{ 0x492, 0x248, 0x492 },
+	{ 0x252, 0x928, 0x292 },
+	{ 0X94A, 0X4A4, 0XA52 },
+	{ 0X52A, 0XAA4, 0X54A },
+	{ 0XAAA, 0x954, 0X4AA },
+	{ 0XAAA, 0x554, 0XAAA },
+	{ 0x555, 0XAD4, 0X5AA },
+	{ 0XB55, 0XAB4, 0X55A },
+	{ 0X6B5, 0X5AC, 0XB56 },
+	{ 0X5B5, 0XD6C, 0X6D6 },
+	{ 0XB6D, 0XB6A, 0XDB6 },
+	{ 0X76D, 0X6DA, 0XBB6 },
+	{ 0XEDD, 0XDDA, 0X76E },
+	{ 0XDDD, 0XBBA, 0XEEE },
+	{ 0X7BB, 0XF7A, 0XDDE },
+	{ 0XF7B, 0XEF6, 0X7DE },
+	{ 0XDF7, 0XBF6, 0XF7E },
+	{ 0X7F7, 0XFEE, 0XEFE },
+	{ 0XFDF, 0XFBE, 0X7FE },
+	{ 0XF7F, 0XEFE, 0XFFE },
+	{ 0XFFF, 0XFFE, 0XFFD },
+};
+#define UART_CLOCK_DIVISOR_0                               0x004
+#define UART_CLOCK_DIVISOR_1                               0x005
+#define UART_CLOCK_DIVISOR_2                               0x006
+#define UART_TX_CLOCK_MASK_0                               0x007
+#define UART_TX_CLOCK_MASK_1                               0x008
+#define UART_RX_CLOCK_MASK_0                               0x009
+#define UART_RX_CLOCK_MASK_1                               0x00a
+
+static int xr21v141x_set_baud_rate(struct xr_usb_serial *xr_usb_serial, unsigned int rate)
+{
+	unsigned int 	divisor = 48000000 / rate;
+	unsigned int 	i 	= ((32 * 48000000) / rate) & 0x1f;
+	unsigned int 	tx_mask = xr21v141x_baud_rates[i].tx;
+	unsigned int 	rx_mask = (divisor & 1) ? xr21v141x_baud_rates[i].rx1 : xr21v141x_baud_rates[i].rx0;
+
+	dev_dbg(&xr_usb_serial->control->dev, "Setting baud rate to %d: i=%u div=%u tx=%03x rx=%03x\n", rate, i, divisor, tx_mask, rx_mask);
+
+	xr_usb_serial_set_reg(xr_usb_serial,UART_CLOCK_DIVISOR_0, (divisor >>  0) & 0xff);
+	xr_usb_serial_set_reg(xr_usb_serial,UART_CLOCK_DIVISOR_1, (divisor >>  8) & 0xff);
+	xr_usb_serial_set_reg(xr_usb_serial,UART_CLOCK_DIVISOR_2, (divisor >> 16) & 0xff);
+	xr_usb_serial_set_reg(xr_usb_serial,UART_TX_CLOCK_MASK_0, (tx_mask >>  0) & 0xff);
+	xr_usb_serial_set_reg(xr_usb_serial,UART_TX_CLOCK_MASK_1, (tx_mask >>  8) & 0xff);
+	xr_usb_serial_set_reg(xr_usb_serial,UART_RX_CLOCK_MASK_0, (rx_mask >>  0) & 0xff);
+	xr_usb_serial_set_reg(xr_usb_serial,UART_RX_CLOCK_MASK_1, (rx_mask >>  8) & 0xff);
+	
+	return 0;
+}
+/* devices aren't required to support these requests.
+ * the cdc xr_usb_serial descriptor tells whether they do...
+ */
+int xr_usb_serial_set_control(struct xr_usb_serial *xr_usb_serial, unsigned int control)
+{
+    int ret = 0;
+    
+	if((xr_usb_serial->DeviceProduct == 0x1410) ||
+		   (xr_usb_serial->DeviceProduct == 0x1412) || 
+		   (xr_usb_serial->DeviceProduct == 0x1414)) 
+	{
+		if (control & XR_USB_SERIAL_CTRL_DTR) 
+		   xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_clr_addr, 0x08);
+		else
+		   xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_set_addr, 0x08);
+
+		if (control & XR_USB_SERIAL_CTRL_RTS) 
+		   xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_clr_addr, 0x20);
+		else
+		   xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_set_addr, 0x20);
+	}
+	else 
+	{
+	   ret = xr_usb_serial_ctrl_msg(xr_usb_serial, USB_CDC_REQ_SET_CONTROL_LINE_STATE, control, NULL, 0);
+	}
+	
+	return ret;
+}
+
+int xr_usb_serial_set_line(struct xr_usb_serial *xr_usb_serial, struct usb_cdc_line_coding* line)
+ {
+	 int ret = 0;
+	 unsigned int format_size;
+	 unsigned int format_parity;
+	 unsigned int format_stop;
+	 if((xr_usb_serial->DeviceProduct == 0x1410) ||
+		(xr_usb_serial->DeviceProduct == 0x1412) || 
+		(xr_usb_serial->DeviceProduct == 0x1414)) 
+	 {
+		xr21v141x_set_baud_rate(xr_usb_serial,line->dwDTERate);
+		format_size = line->bDataBits;
+		format_parity = line->bParityType;
+		format_stop = line->bCharFormat;
+		xr_usb_serial_set_reg(xr_usb_serial,
+			                  xr_usb_serial->reg_map.uart_format_addr,
+			                  (format_size << 0) | (format_parity << 4) | (format_stop << 7) );
+		
+	 }
+	 else 
+	 {
+	   ret = xr_usb_serial_ctrl_msg(xr_usb_serial, USB_CDC_REQ_SET_LINE_CODING, 0, line, sizeof *(line));
+	 }
+	 return ret;
+ }
+ int xr_usb_serial_set_flow_mode(struct xr_usb_serial *xr_usb_serial, 
+ 	                                     struct tty_struct *tty, unsigned int cflag)
+ {
+	unsigned int flow;
+	unsigned int gpio_mode;
+	
+	if (cflag & CRTSCTS)
+	{
+	    dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_set_flow_mode:hardware\n");
+	    flow      = UART_FLOW_MODE_HW;
+	    gpio_mode = UART_GPIO_MODE_SEL_RTS_CTS;
+	} 
+	else if (I_IXOFF(tty) || I_IXON(tty))
+	{
+	    unsigned char   start_char = START_CHAR(tty);
+	    unsigned char   stop_char  = STOP_CHAR(tty);
+        dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_set_flow_mode:software\n");
+	    flow      = UART_FLOW_MODE_SW;
+	    gpio_mode = UART_GPIO_MODE_SEL_GPIO;
+
+	    xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_xon_char_addr, start_char);
+	    xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_xoff_char_addr, stop_char);
+	}
+	else
+	{
+	    dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_set_flow_mode:none\n");
+	    flow      = UART_FLOW_MODE_NONE;
+	    gpio_mode = UART_GPIO_MODE_SEL_GPIO;
+	}
+	
+    if((xr_usb_serial->DeviceProduct == 0x1420)||
+	   (xr_usb_serial->DeviceProduct == 0x1422)||
+	   (xr_usb_serial->DeviceProduct == 0x1424))
+    {//Add support for the TXT and RXT function for 0x1420, 0x1422, 0x1424, by setting GPIO_MODE [9:8] = '11'
+        gpio_mode |= 0x300;
+    }
+		
+    xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_flow_addr, flow);
+    xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_mode_addr, gpio_mode);
+	return 0;
+	 
+
+ }
+ 
+int xr_usb_serial_send_break(struct xr_usb_serial *xr_usb_serial, int state)
+{
+	int ret = 0;
+	if((xr_usb_serial->DeviceProduct == 0x1410)||
+	   (xr_usb_serial->DeviceProduct == 0x1412)||
+	   (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+	  if(state)
+	     ret = xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.tx_break_addr,0xffff);
+	  else
+	  	 ret = xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.tx_break_addr,0);
+	}
+	else 
+	{
+	  ret = xr_usb_serial_ctrl_msg(xr_usb_serial, USB_CDC_REQ_SEND_BREAK, state, NULL, 0);
+	}
+	return ret;
+}
+
+#define URM_REG_BLOCK           4
+#define URM_ENABLE_BASE        0x010
+#define URM_ENABLE_0_TX        0x001
+#define URM_ENABLE_0_RX        0x002
+#define URM_RESET_RX_FIFO_BASE        0x018
+#define URM_RESET_TX_FIFO_BASE        0x01C
+
+
+
+int xr_usb_serial_enable(struct xr_usb_serial *xr_usb_serial)
+{
+	int ret = 0;
+	int channel = xr_usb_serial->channel;
+	if((xr_usb_serial->DeviceProduct == 0x1410)||
+	   (xr_usb_serial->DeviceProduct == 0x1412)||
+	   (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+	  ret = xr_usb_serial_set_reg_ext(xr_usb_serial,URM_REG_BLOCK,URM_ENABLE_BASE + channel,URM_ENABLE_0_TX);
+	  ret = xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_enable_addr,UART_ENABLE_TX | UART_ENABLE_RX);
+	  ret = xr_usb_serial_set_reg_ext(xr_usb_serial,URM_REG_BLOCK,URM_ENABLE_BASE + channel,URM_ENABLE_0_TX | URM_ENABLE_0_RX);
+	}
+	else 
+	{
+	  ret = xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_enable_addr,UART_ENABLE_TX | UART_ENABLE_RX);
+	}
+	
+	return ret;
+}
+int xr_usb_serial_fifo_reset(struct xr_usb_serial *xr_usb_serial)
+{
+	    int ret = 0;
+		int channel = xr_usb_serial->channel;
+		if(channel) channel--;
+		if((xr_usb_serial->DeviceProduct == 0x1410)||
+		   (xr_usb_serial->DeviceProduct == 0x1412)||
+		   (xr_usb_serial->DeviceProduct == 0x1414))
+		{
+		   
+		  ret = xr_usb_serial_set_reg_ext(xr_usb_serial,URM_REG_BLOCK,URM_RESET_RX_FIFO_BASE + channel,0xff);
+		  ret |= xr_usb_serial_set_reg_ext(xr_usb_serial,URM_REG_BLOCK,URM_RESET_TX_FIFO_BASE + channel,0xff);
+		   
+		}
+		return ret;
+}
+
+
+int xr_usb_serial_disable(struct xr_usb_serial *xr_usb_serial)
+{
+	int ret = 0;
+	int channel = xr_usb_serial->channel;
+	ret = xr_usb_serial_set_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_enable_addr,0);
+	if((xr_usb_serial->DeviceProduct == 0x1410)||
+	   (xr_usb_serial->DeviceProduct == 0x1412)||
+	   (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+	  ret = xr_usb_serial_set_reg_ext(xr_usb_serial,URM_REG_BLOCK,URM_ENABLE_BASE + channel,URM_ENABLE_0_TX);
+	}
+		
+	return ret;
+}
+int xr_usb_serial_set_loopback(struct xr_usb_serial *xr_usb_serial, int channel)
+{
+	int ret = 0;
+	xr_usb_serial_disable(xr_usb_serial);
+	ret = xr_usb_serial_set_reg_ext(xr_usb_serial,channel,
+		                            xr_usb_serial->reg_map.uart_loopback_addr,0x07);
+	xr_usb_serial_enable(xr_usb_serial);
+	return ret;
+}
+
+
+static int xr_usb_serial_tiocmget(struct xr_usb_serial *xr_usb_serial)
+
+{
+        short data;
+		int result;
+		result = xr_usb_serial_get_reg(xr_usb_serial,xr_usb_serial->reg_map.uart_gpio_status_addr, &data);
+		dev_dbg(&xr_usb_serial->control->dev, "xr_usb_serial_tiocmget uart_gpio_status_addr:0x%04x\n",data);
+		if (result)
+			return ((data & 0x8) ? 0: TIOCM_DTR) | ((data & 0x20) ? 0:TIOCM_RTS ) | ((data & 0x4) ? 0:TIOCM_DSR) | ((data & 0x1) ? 0 : TIOCM_RI) | ((data & 0x2) ? 0:TIOCM_CD) | ((data & 0x10) ? 0 : TIOCM_CTS); 
+		else
+			return -EFAULT;
+}
+static int xr_usb_serial_tiocmset(struct xr_usb_serial *xr_usb_serial,
+
+                            unsigned int set, unsigned int clear)
+
+{
+        unsigned int newctrl = 0;
+        newctrl = xr_usb_serial->ctrlout; 
+		
+        set = (set & TIOCM_DTR ? XR_USB_SERIAL_CTRL_DTR : 0) | (set & TIOCM_RTS ? XR_USB_SERIAL_CTRL_RTS : 0);
+		
+        clear = (clear & TIOCM_DTR ? XR_USB_SERIAL_CTRL_DTR : 0) | (clear & TIOCM_RTS ? XR_USB_SERIAL_CTRL_RTS : 0);
+       
+	    newctrl = (newctrl & ~clear) | set;
+		
+		if (xr_usb_serial->ctrlout == newctrl)
+                return 0;
+		
+		xr_usb_serial->ctrlout = newctrl;
+		
+		if (newctrl & XR_USB_SERIAL_CTRL_DTR) 
+			xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_clr_addr, 0x08);
+		else
+			xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_set_addr, 0x08);
+
+		if (newctrl & XR_USB_SERIAL_CTRL_RTS) 
+			xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_clr_addr, 0x20);
+		else
+			xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_set_addr, 0x20);
+
+        return 0;
+}
+
+
+static struct reg_addr_map xr21b140x_reg_map;
+static struct reg_addr_map xr21b1411_reg_map;
+static struct reg_addr_map xr21v141x_reg_map;
+static struct reg_addr_map xr21b142x_reg_map;
+
+static void init_xr21b140x_reg_map(void)
+{
+	xr21b140x_reg_map.uart_enable_addr = 0x00;
+	xr21b140x_reg_map.uart_format_addr = 0x05;
+	xr21b140x_reg_map.uart_flow_addr = 0x06;
+	xr21b140x_reg_map.uart_loopback_addr = 0x16;
+	xr21b140x_reg_map.uart_xon_char_addr = 0x07;
+	xr21b140x_reg_map.uart_xoff_char_addr = 0x08;
+	xr21b140x_reg_map.uart_gpio_mode_addr = 0x0c;
+	xr21b140x_reg_map.uart_gpio_dir_addr = 0x0d;
+	xr21b140x_reg_map.uart_gpio_set_addr = 0x0e;
+	xr21b140x_reg_map.uart_gpio_clr_addr = 0x0f;
+	xr21b140x_reg_map.uart_gpio_status_addr = 0x10;
+	xr21b140x_reg_map.tx_break_addr = 0x0a;
+	xr21b140x_reg_map.uart_custom_driver = 0x41;
+}
+
+static void init_xr21b1411_reg_map(void)
+{
+	xr21b1411_reg_map.uart_enable_addr = 0xc00;
+	xr21b1411_reg_map.uart_flow_addr = 0xc06;
+	xr21b1411_reg_map.uart_loopback_addr = 0xc16;
+	xr21b1411_reg_map.uart_xon_char_addr = 0xc07;
+	xr21b1411_reg_map.uart_xoff_char_addr = 0xc08;
+	xr21b1411_reg_map.uart_gpio_mode_addr = 0xc0c;
+	xr21b1411_reg_map.uart_gpio_dir_addr = 0xc0d;
+	xr21b1411_reg_map.uart_gpio_set_addr = 0xc0e;
+	xr21b1411_reg_map.uart_gpio_clr_addr = 0xc0f;
+	xr21b1411_reg_map.uart_gpio_status_addr = 0xc10;
+	xr21b1411_reg_map.tx_break_addr = 0xc0a;
+	xr21b1411_reg_map.uart_custom_driver = 0x20d;
+}
+
+static void init_xr21v141x_reg_map(void)
+{
+	xr21v141x_reg_map.uart_enable_addr = 0x03;
+	xr21v141x_reg_map.uart_format_addr = 0x0b;
+	xr21v141x_reg_map.uart_flow_addr = 0x0c;
+	xr21v141x_reg_map.uart_loopback_addr = 0x12;
+	xr21v141x_reg_map.uart_xon_char_addr = 0x10;
+	xr21v141x_reg_map.uart_xoff_char_addr = 0x11;
+	xr21v141x_reg_map.uart_gpio_mode_addr = 0x1a;
+	xr21v141x_reg_map.uart_gpio_dir_addr = 0x1b;
+	xr21v141x_reg_map.uart_gpio_set_addr = 0x1d;
+	xr21v141x_reg_map.uart_gpio_clr_addr = 0x1e;
+	xr21v141x_reg_map.uart_gpio_status_addr = 0x1f;
+	xr21v141x_reg_map.tx_break_addr = 0x14;
+}
+static void init_xr21b142x_reg_map(void)
+{
+	xr21b142x_reg_map.uart_enable_addr = 0x00;
+	xr21b142x_reg_map.uart_flow_addr = 0x06;
+	xr21b142x_reg_map.uart_loopback_addr = 0x16;
+	xr21b142x_reg_map.uart_xon_char_addr = 0x07;
+	xr21b142x_reg_map.uart_xoff_char_addr = 0x08;
+	xr21b142x_reg_map.uart_gpio_mode_addr = 0x0c;
+	xr21b142x_reg_map.uart_gpio_dir_addr = 0x0d;
+	xr21b142x_reg_map.uart_gpio_set_addr = 0x0e;
+	xr21b142x_reg_map.uart_gpio_clr_addr = 0x0f;
+	xr21b142x_reg_map.uart_gpio_status_addr = 0x10;
+    xr21b140x_reg_map.tx_break_addr = 0x0a;
+	xr21b140x_reg_map.uart_custom_driver = 0x60;
+	xr21b140x_reg_map.uart_low_latency = 0x46;
+}
+
+int xr_usb_serial_pre_setup(struct xr_usb_serial *xr_usb_serial)
+{
+	int ret = 0;
+	
+	init_xr21b140x_reg_map();
+	init_xr21b1411_reg_map();
+	init_xr21v141x_reg_map();
+	init_xr21b142x_reg_map();
+	if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1400)
+	{
+	  memcpy(&(xr_usb_serial->reg_map),&xr21b140x_reg_map,sizeof(struct reg_addr_map));
+	 
+	}
+	else if(xr_usb_serial->DeviceProduct == 0x1411 || xr_usb_serial->DeviceVendor == TEKNIC_VID)
+	{
+	  memcpy(&(xr_usb_serial->reg_map),&xr21b1411_reg_map,sizeof(struct reg_addr_map));
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1410)||
+		    (xr_usb_serial->DeviceProduct == 0x1412)||
+		    (xr_usb_serial->DeviceProduct == 0x1414))
+	{
+	  memcpy(&(xr_usb_serial->reg_map),&xr21v141x_reg_map,sizeof(struct reg_addr_map));
+	}
+	else if((xr_usb_serial->DeviceProduct == 0x1420)||
+		    (xr_usb_serial->DeviceProduct == 0x1422)||
+		    (xr_usb_serial->DeviceProduct == 0x1424))
+	{
+	  memcpy(&(xr_usb_serial->reg_map),&xr21b142x_reg_map,sizeof(struct reg_addr_map));
+	}
+	else
+	{
+	  ret = -1;
+	}
+	if(xr_usb_serial->reg_map.uart_custom_driver)
+	   xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_custom_driver, 1);
+
+	xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_mode_addr, 0);  
+	xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_dir_addr, 0x28);  
+    xr_usb_serial_set_reg(xr_usb_serial, xr_usb_serial->reg_map.uart_gpio_set_addr, UART_GPIO_SET_DTR | UART_GPIO_SET_RTS); 
+	
+    return ret;
+   
+}
+
+	
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_ioctl.h b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_ioctl.h
new file mode 100644
index 000000000..c0285dc08
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/Teknic_SC4Hub_USB_Driver/ExarKernelDriver/xr_usb_serial_ioctl.h
@@ -0,0 +1,36 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/ioctl.h>
+
+#define XR_USB_SERIAL_IOC_MAGIC       	'v'
+
+#define XR_USB_SERIAL_GET_REG           	_IOWR(XR_USB_SERIAL_IOC_MAGIC, 1, int)
+#define XR_USB_SERIAL_SET_REG           	_IOWR(XR_USB_SERIAL_IOC_MAGIC, 2, int)
+#define XR_USB_SERIAL_SET_ADDRESS_MATCH 	_IO(XR_USB_SERIAL_IOC_MAGIC, 3)
+#define XR_USB_SERIAL_SET_PRECISE_FLAGS     	_IO(XR_USB_SERIAL_IOC_MAGIC, 4)
+#define XR_USB_SERIAL_TEST_MODE         	_IO(XR_USB_SERIAL_IOC_MAGIC, 5)
+#define XR_USB_SERIAL_LOOPBACK          	_IO(XR_USB_SERIAL_IOC_MAGIC, 6)
+#define XR_USB_SERIAL_SET_GPIO_MODE_REG    _IO(XR_USB_SERIAL_IOC_MAGIC, 9) 
+#define	XR_USB_SERIAL_GET_GPIO_MODE_REG    _IO(XR_USB_SERIAL_IOC_MAGIC, 10) 
+#define  XRIOC_SET_ANY_BAUD_RATE           _IO(XR_USB_SERIAL_IOC_MAGIC, 11)
+
+
+
+#define VZ_ADDRESS_UNICAST_S        	0
+#define VZ_ADDRESS_BROADCAST_S      	8
+#define VZ_ADDRESS_MATCH(U, B)          (0x8000000 | ((B) << VZ_ADDRESS_BROADCAST_S) | ((U) << VZ_ADDRESS_UNICAST_S))
+#define VZ_ADDRESS_MATCH_DISABLE    	0
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/doc/S-FoundationRef.chm b/vendor/teknic/clearpath-motor/Linux_Software/doc/S-FoundationRef.chm
new file mode 100644
index 000000000..de6a319fb
Binary files /dev/null and b/vendor/teknic/clearpath-motor/Linux_Software/doc/S-FoundationRef.chm differ
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/doc/readme.txt b/vendor/teknic/clearpath-motor/Linux_Software/doc/readme.txt
new file mode 100644
index 000000000..a08f157a6
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/doc/readme.txt
@@ -0,0 +1,39 @@
+----------------------------------------
+ClearPath-SC Linux Documentation Notes
+----------------------------------------
+Revision: $Date: 05/29/2018$
+
+-----------------
+WHAT'S PROVIDED
+-----------------
+The documentation file provided is a CHM of the sFoundation documentation.
+
+----------------
+REQUIRED SETUP
+----------------
+A CHM viewer is required in order to open and view the sFoundation-Ref.chm
+file. 
+
+The recommended CHM viewer is kchmviewer. Kchmviewer is a free, open-source 
+viewer. More information regarding the viewer itself can be found at
+http://www.kchmviewer.net. 
+
+To install kchmviewer on Ubuntu run the command:
+sudo apt-get install kchmviewer
+
+A file can be launched from the command line using the command:
+kchmviewer filename
+
+Any other CHM viewers may be used but are not generally recommended. Other
+options include:
+
+- xchm
+To install xchm on Ubuntu run the command:
+sudo apt-get install xchm
+
+- Okular
+To install Okular it is recommended to use your software distribution center.
+In Ubuntu this would be the 'Ubuntu Software Center'. An add-on is required to
+support viewing CHM documents in Okular which can be installed directly from
+Okular's install page.
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/readme.txt b/vendor/teknic/clearpath-motor/Linux_Software/readme.txt
new file mode 100644
index 000000000..d2129146a
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/readme.txt
@@ -0,0 +1,206 @@
+
+
+                          Teknic sFoundation for Linux
+                                   2021-04-12
+
+
+                                 Setup Overview
+To start using sFoundation, you'll have to complete the following steps:
+ 1. Configure permissions for interacting with serial ports
+ 2. Build the sFoundation shared library
+ 3. Install the sFoundation shared library
+
+This document will also cover how to...
+ 4. Install the SC4-Hub driver if you plan on connecting it via USB
+ 5. Build and run the example projects
+ 6. Compile your own application
+ 7. Compile sFoundation for Single Board Computers
+
+
+                                       0
+                              Before You Start...
+Make sure you have the required software:
+ - tar (to extract package contents)
+    tested: 1.32, 1.3
+ - make (to build sFoundation)
+    tested: 4.3, 4.2.1
+ - g++ (to build sFoundation; must support C++ 11)
+    tested: 10.2.1, 9.3.0, 8.3.0
+ - ldconfig (for installing sFoundation)
+    tested: 2.32, 2.31, 2.28
+
+Make sure you have permission:
+ - To install sFoundation shared library for system use, you will need write
+   access to /usr/local/lib
+ - To install the SC4-Hub USB driver, you will need root access
+
+These instructions have been verified to work exactly as written in
+ - Ubuntu 20.04 (x64)
+ - Fedora Workstation 33 (x64)
+ - Debian 10.9 (x64)
+ - Raspberry Pi OS (buster) (arm)
+ - Ubuntu 18.04 on BeagleBone Black (arm) (linux 4.19.94-ti-r36)
+
+ > Note: Don't lose hope if your distribution isn't listed; there's a good
+   chance you will be able to get everything working with minimal tinkering
+
+
+                                       1
+                            Serial Port Permissions
+In most distributions, this will suffice:
+ 1. Add your user to the dialout group
+    $ sudo usermod -aG dialout <your_username>
+ 2. Reboot or log out and back in for your new permissions to take effect
+ 3. Make sure your user is now in the dialout group
+    $ groups
+    yourUsername adm dialout sudo cdrom ...
+                     ^^^^^^^
+
+
+                                       2
+                        Build sFoundation Shared Library
+ 1. Extract the sFoundation source bundled in this package. This will inflate
+    into multiple directories
+    $ tar -xvf sFoundation.tar
+ 2. Navigate to the sFoudnation directory
+    $ cd sFoundation
+ 3. Run make. This will build libsFoundation20.so in the current directory
+    $ make
+
+    > Note: By default, the g++ -w flag is used to suppress warnings. If you
+      want to see them, remove that flag from the CXXFLAGS variable in the
+      makefile. Either way, sFoundation should build without error.
+
+
+                                       3
+                       Install sFoundation Shared Library
+The sFoundation library can be installed for systemwide use by all users, or on
+a single-user basis. You can pick one or the other, depending on your use-case
+and permissions. You DO NOT need to do both.
+
+Systemwide Install:
+You will need permission to write to system directories (specifically,
+/usr/local/lib). If you lack the required permissions, you may need to contact
+your administrator, or consider using the library locally.
+ 1. Copy MNuserDriver.xml and libsFoundation20.so to /usr/local/lib
+    $ sudo cp {MNuserDriver20.xml,libsFoundation20.so} /usr/local/lib
+ 2. Run ldconfig to set up the proper symbolic links and add the sFoundation
+    library to the linker search path
+    $ sudo ldconfig
+ 3. For sanity, verify that the system detected the new shared library
+    $ ldconfig -p | grep "sFoundation"
+
+    The expected output would be something like this:
+    libsFoundation20.so.1 (libc6,x86-64) => /usr/local/lib/libsFoundation20.so.1
+
+    > Note: ldconfig is typically in /usr/sbin/ldconfig. On some distributions,
+      including Debian, /usr/sbin/ is not in the default search path for
+      standard users. You might need to specify the full path.
+      $ /usr/sbin/ldconfig -p | grep "sFoundation"
+
+    > Note: If the above command has no output, ldconfig might not be configured
+      to search /usr/local/lib by default. This seemed to be the case in Fedora
+      33.
+            1. Make sure /usr/local/lib is indeed absent from the ld search 
+               path. You should get no output.
+               $ grep -re "/usr/local/lib" /etc/ld.so.c*
+
+               > Note: If you did get output, make sure the appropriate files
+                 are included in /etc/ld.so.conf
+            2. Make sure /usr/local/lib is explicitly listed or included in 
+               /etc/ld.so.conf. You could create a new file in an included 
+               directory under /etc/ld.so.conf.d/, or simply append to 
+               /etc/ld.so.conf.
+               $ echo "/usr/local/lib" | sudo tee -a /etc/ld.so.conf
+            3. Try running sudo ldconfig again, then ldconfig -p. You should get
+               output this time.
+
+Single-User Install:
+You can point the linker and loader to your libsFoundation20.so wherever it was
+built. This has the advantage that you don't need super user access, but comes
+with the drawback that users may need to compile your application for
+themselves, depending on where libsFoundation20.so is located.
+ 1. Now would be a good time to copy MNuserDriver.xml and libsFoundation20.so
+    to wherever you want them to live. Keep in mind that moving the .so files
+    will require you to recompile dependent executables. They can remain where
+    they were built if you prefer.
+    $ cp {MNuserDriver20.xml,libsFoundation20.so} /home/user/teknic/
+ 2. Create the necessary symbolic links to the sFoundation library (the soname).
+    $ ldconfig -n /home/user/teknic/
+
+    > Note: Replace the path with the directory you copied libsFoundation20.so
+      to in step 1.
+    > Note: ldconfig is typically in /usr/sbin/ldconfig. On some distributions,
+      including Debian, /usr/sbin/ is not in the default search path for
+      standard users. You might need to specify the full path.
+      $ /usr/sbin/ldconfig -n /home/user/teknic/
+ 3. Make sure you compile your application with rpath. Section 6 contains 
+    specifics about this.
+
+Further Reading:
+The Linux Documentation Project has a good explanation of how shared libraries
+work, if you are having trouble getting things set up:
+https://tldp.org/HOWTO/Program-Library-HOWTO/shared-libraries.html
+
+
+                                       4
+                               SC4-Hub USB Driver
+This section can be skipped if you won't be connecting the SC4-Hub to your PC
+via USB. 
+ 1. Navigate back to the root directory of this package, if needed. If you're
+    coming from Section 2/3:
+    $ cd ..
+ 2. Extract the driver package. This will create a directory called
+    ExarKernelDriver.
+    $ tar -xvf Teknic_SC4Hub_USB_Driver.tar
+ 3. View the installation instructions in
+    ExarKernelDriver/driver_readme.txt in a text editor.
+
+
+
+                                       5
+                                Example Projects
+There are several examples that demonstrate how to interact with the sFoundation
+library. To build them, simply change to the example directory and run make.
+For example, to run HelloWorld:
+ 1. cd SDK_Examples/HelloWorld
+ 2. make
+ 3. ./HelloWorld
+
+ > Note: If sFoundation is installed in a non-standard location (outside
+   /usr/local/lib, or /usr/lib), point g++ to it, and embed the path of
+   the shared library into the executable using the rpath linker option. The
+   Makefiles allow you to do this by defining RPATH on the command line. For
+   example, if libsFoundation20.so is located in /home/user/stuff, your make
+   command (step 2 above) would look like this:
+ $ make RPATH=/home/user/stuff
+
+
+                                       6
+                         Compiling Your Own Application
+The example makefiles may be helpful as a reference to help you set up your
+target build system. Here is a summary of how the library can be used in a
+custom application:
+ 1. Add sFoundation headers, located at inc/inc-pub, to the compiler's include
+    path (-I in g++).
+ 2. Tell the linker to link against the sFoundation20 and pthread libraries
+    (-lsFoundation20 and -lpthread respectively in g++)
+
+If you did not install libsFoundation20 to a directory in the linker path (i.e.
+outside /usr/local/lib, /usr/lib, etc.), you will need to pass additional flags
+to g++. For reference, see the Example project Makefiles, which allow you to
+link to a nonstandard location using RPATH (Section 5).
+ 3. Specify the -L<dir> option. For example, if libsFoundation20.so is in 
+	/home/user/sf, simply add -L/home/user/sf to your build command.
+ 4. Pass the rpath option to the linker so that the shared library
+    loader knows which directory to load sFoundation from at runtime. Include
+	-Wl,-rpath=/home/user/sf in your build command if libsFoundation20.so is
+	located in /home/user/sf.
+
+
+                                       7
+                     sFoundation on Single Board Computers
+TODO DCB Talk about how this used to work in eclipse...
+All of the information in this document should apply to compiling natively on
+BeagleBone and Raspberry Pi. Cross-compilation for ARM on x86 is no longer
+officially supported.
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/inc/dictionary.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/inc/dictionary.h
new file mode 100644
index 000000000..67a4019c5
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/inc/dictionary.h
@@ -0,0 +1,191 @@
+
+/*-------------------------------------------------------------------------*/
+/**
+	@file    dictionary.h
+	@author  N. Devillard
+	@brief   Implements a dictionary for string variables.
+
+	This module implements a simple dictionary object, i.e. a list
+	of string/string associations. This object is useful to store e.g.
+	informations retrieved from a configuration file (ini files).
+
+	MIT License
+	
+	Permission is hereby granted, free of charge, to any person
+	obtaining a copy of this software and associated documentation
+	files (the "Software"), to deal in the Software without
+	restriction, including without limitation the rights to use,
+	copy, modify, merge, publish, distribute, sublicense, and/or sell
+	copies of the Software, and to permit persons to whom the
+	Software is furnished to do so, subject to the following
+	conditions:
+	
+	The above copyright notice and this permission notice shall be
+	included in all copies or substantial portions of the Software.
+	
+	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+	OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+	NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+	HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+	WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+	FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+	OTHER DEALINGS IN THE SOFTWARE.
+*/
+/*--------------------------------------------------------------------------*/
+
+#ifndef _DICTIONARY_H_
+#define _DICTIONARY_H_
+
+/*---------------------------------------------------------------------------
+                                Includes
+ ---------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#if !(defined(_WIN32)||defined(_WIN64))
+#include <unistd.h>
+#endif
+
+/*---------------------------------------------------------------------------
+                                New types
+ ---------------------------------------------------------------------------*/
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Dictionary object
+
+  This object contains a list of string/string associations. Each
+  association is identified by a unique string key. Looking up values
+  in the dictionary is speeded up by the use of a (hopefully collision-free)
+  hash function.
+ */
+/*-------------------------------------------------------------------------*/
+typedef struct _dictionary_ {
+    int             n ;     /** Number of entries in dictionary */
+    int             size ;  /** Storage size */
+    char        **  val ;   /** List of string values */
+    char        **  key ;   /** List of string keys */
+    unsigned     *  hash ;  /** List of hash values for keys */
+} dictionary ;
+
+
+/*---------------------------------------------------------------------------
+                            Function prototypes
+ ---------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Compute the hash key for a string.
+  @param    key     Character string to use for key.
+  @return   1 unsigned int on at least 32 bits.
+
+  This hash function has been taken from an Article in Dr Dobbs Journal.
+  This is normally a collision-free function, distributing keys evenly.
+  The key is stored anyway in the struct so that collision can be avoided
+  by comparing the key itself in last resort.
+ */
+/*--------------------------------------------------------------------------*/
+int32_t dictionary_hash(const char * key);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Create a new dictionary object.
+  @param    size    Optional initial size of the dictionary.
+  @return   1 newly allocated dictionary objet.
+
+  This function allocates a new dictionary object of given size and returns
+  it. If you do not know in advance (roughly) the number of entries in the
+  dictionary, give size=0.
+ */
+/*--------------------------------------------------------------------------*/
+dictionary * dictionary_new(int size);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Delete a dictionary object
+  @param    d   dictionary object to deallocate.
+  @return   void
+
+  Deallocate a dictionary object and all memory associated to it.
+ */
+/*--------------------------------------------------------------------------*/
+void dictionary_del(dictionary * vd);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get a value from a dictionary.
+  @param    d       dictionary object to search.
+  @param    key     Key to look for in the dictionary.
+  @param    def     Default value to return if key not found.
+  @return   1 pointer to internally allocated character string.
+
+  This function locates a key in a dictionary and returns a pointer to its
+  value, or the passed 'def' pointer if no such key can be found in
+  dictionary. The returned character pointer points to data internal to the
+  dictionary object, you should not try to free it or modify it.
+ */
+/*--------------------------------------------------------------------------*/
+const char * dictionary_get(dictionary * d, const char * key, const char * def);
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Set a value in a dictionary.
+  @param    d       dictionary object to modify.
+  @param    key     Key to modify or add.
+  @param    val     Value to add.
+  @return   int     0 if Ok, anything else otherwise
+
+  If the given key is found in the dictionary, the associated value is
+  replaced by the provided one. If the key cannot be found in the
+  dictionary, it is added to it.
+
+  It is Ok to provide a NULL value for val, but NULL values for the dictionary
+  or the key are considered as errors: the function will return immediately
+  in such a case.
+
+  Notice that if you dictionary_set a variable to NULL, a call to
+  dictionary_get will return a NULL value: the variable will be found, and
+  its value (NULL) is returned. In other words, setting the variable
+  content to NULL is equivalent to deleting the variable from the
+  dictionary. It is not possible (in this implementation) to have a key in
+  the dictionary without value.
+
+  This function throws an error string in case of failure.
+ */
+/*--------------------------------------------------------------------------*/
+int dictionary_set(dictionary * vd, const char * key, const char * val);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Delete a key in a dictionary
+  @param    d       dictionary object to modify.
+  @param    key     Key to remove.
+  @return   void
+
+  This function deletes a key in a dictionary. Nothing is done if the
+  key cannot be found.
+ */
+/*--------------------------------------------------------------------------*/
+void dictionary_unset(dictionary * d, const char * key);
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Dump a dictionary to an opened file pointer.
+  @param    d   Dictionary to dump
+  @param    f   Opened file pointer.
+  @return   void
+
+  Dumps a dictionary onto an opened file pointer. Key pairs are printed out
+  as @c [Key]=[Value], one per line. It is Ok to provide stdout or stderr as
+  output file pointers.
+ */
+/*--------------------------------------------------------------------------*/
+void dictionary_dump(dictionary * d, FILE * out);
+
+#endif
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/inc/iniparser.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/inc/iniparser.h
new file mode 100644
index 000000000..9a2382a6a
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/inc/iniparser.h
@@ -0,0 +1,280 @@
+
+/*-------------------------------------------------------------------------*/
+/**
+   @file    iniparser.h
+   @author  N. Devillard
+   @date    Sep 2007
+   @version 3.0
+   @brief   Parser for ini files.
+*/
+/*--------------------------------------------------------------------------*/
+
+/*
+	$Id: iniparser.h,v 1.24 2007-11-23 21:38:19 ndevilla Exp $
+	$Revision: 4 $
+*/
+
+#ifndef _INIPARSER_H_
+#define _INIPARSER_H_
+
+/*---------------------------------------------------------------------------
+   								Includes
+ ---------------------------------------------------------------------------*/
+
+//#include <stdio.h>
+//#include <stdlib.h>
+#include <string>
+
+/*
+ * The following #include is necessary on many Unixes but not Linux.
+ * It is not needed for Windows platforms.
+ * Uncomment it if needed.
+ */
+/* #include <unistd.h> */
+
+#include "dictionary.h"
+
+/*---------------------------------------------------------------------------
+   								Macros
+ ---------------------------------------------------------------------------*/
+/** For backwards compatibility only */
+#define iniparser_getstr(d, k)  iniparser_getstring(d, k, NULL)
+#define iniparser_setstr        iniparser_setstring
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get number of sections in a dictionary
+  @param    d   Dictionary to examine
+  @return   int Number of sections found in dictionary
+
+  This function returns the number of sections found in a dictionary.
+  The test to recognize sections is done on the string stored in the
+  dictionary: a section name is given as "section" whereas a key is
+  stored as "section:key", thus the test looks for entries that do not
+  contain a colon.
+
+  This clearly fails in the case a section name contains a colon, but
+  this should simply be avoided.
+
+  This function returns -1 in case of error.
+ */
+/*--------------------------------------------------------------------------*/
+
+int iniparser_getnsec(dictionary * d);
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get name for section n in a dictionary.
+  @param    d   Dictionary to examine
+  @param    n   Section number (from 0 to nsec-1).
+  @return   Pointer to char string
+
+  This function locates the n-th section in a dictionary and returns
+  its name as a pointer to a string statically allocated inside the
+  dictionary. Do not free or modify the returned string!
+
+  This function returns NULL in case of error.
+ */
+/*--------------------------------------------------------------------------*/
+
+char * iniparser_getsecname(dictionary * d, int n);
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Save a dictionary to a loadable ini file
+  @param    d   Dictionary to dump
+  @param    f   Opened file pointer to dump to
+  @return   void
+
+  This function dumps a given dictionary into a loadable ini file.
+  It is Ok to specify @c stderr or @c stdout as output files.
+ */
+/*--------------------------------------------------------------------------*/
+
+void iniparser_dump_ini(dictionary * d, FILE * f);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Dump a dictionary to an opened file pointer.
+  @param    d   Dictionary to dump.
+  @param    f   Opened file pointer to dump to.
+  @return   void
+
+  This function prints out the contents of a dictionary, one element by
+  line, onto the provided file pointer. It is OK to specify @c stderr
+  or @c stdout as output files. This function is meant for debugging
+  purposes mostly.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_dump(dictionary * d, FILE * f);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key
+  @param    d       Dictionary to search
+  @param    key     Key string to look for
+  @param    def     Default value to return if key not found.
+  @return   pointer to statically allocated character string
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the pointer passed as 'def' is returned.
+  The returned char pointer is pointing to a string allocated in
+  the dictionary, do not free or modify it.
+ */
+/*--------------------------------------------------------------------------*/
+const char * iniparser_getstring(dictionary * d, const char * key, const char * def);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key, convert to an int
+  @param    d Dictionary to search
+  @param    key Key string to look for
+  @param    notfound Value to return in case of error
+  @return   integer
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the notfound value is returned.
+
+  Supported values for integers include the usual C notation
+  so decimal, octal (starting with 0) and hexadecimal (starting with 0x)
+  are supported. Examples:
+
+  - "42"      ->  42
+  - "042"     ->  34 (octal -> decimal)
+  - "0x42"    ->  66 (hexa  -> decimal)
+
+  Warning: the conversion may overflow in various ways. Conversion is
+  totally outsourced to strtol(), see the associated man page for overflow
+  handling.
+
+  Credits: Thanks to A. Becker for suggesting strtol()
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_getint(dictionary * d, const char * key, int notfound);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key, convert to a double
+  @param    d Dictionary to search
+  @param    key Key string to look for
+  @param    notfound Value to return in case of error
+  @return   double
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the notfound value is returned.
+ */
+/*--------------------------------------------------------------------------*/
+double iniparser_getdouble(dictionary * d, char * key, double notfound);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key, convert to a boolean
+  @param    d Dictionary to search
+  @param    key Key string to look for
+  @param    notfound Value to return in case of error
+  @return   integer
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the notfound value is returned.
+
+  A true boolean is found if one of the following is matched:
+
+  - A string starting with 'y'
+  - A string starting with 'Y'
+  - A string starting with 't'
+  - A string starting with 'T'
+  - A string starting with '1'
+
+  A false boolean is found if one of the following is matched:
+
+  - A string starting with 'n'
+  - A string starting with 'N'
+  - A string starting with 'f'
+  - A string starting with 'F'
+  - A string starting with '0'
+
+  The notfound value returned if no boolean is identified, does not
+  necessarily have to be 0 or 1.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_getboolean(dictionary * d, const char * key, int notfound);
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Set an entry in a dictionary.
+  @param    ini     Dictionary to modify.
+  @param    entry   Entry to modify (entry name)
+  @param    val     New value to associate to the entry.
+  @return   int 0 if Ok, -1 otherwise.
+
+  If the given entry can be found in the dictionary, it is modified to
+  contain the provided value. If it cannot be found, -1 is returned.
+  It is Ok to set val to NULL.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_setstring(dictionary * ini, const char * entry, const char * val);
+
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Delete an entry in a dictionary
+  @param    ini     Dictionary to modify
+  @param    entry   Entry to delete (entry name)
+  @return   void
+
+  If the given entry can be found, it is deleted from the dictionary.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_unset(dictionary * ini, char * entry);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Finds out if a given entry exists in a dictionary
+  @param    ini     Dictionary to search
+  @param    entry   Name of the entry to look for
+  @return   integer 1 if entry exists, 0 otherwise
+
+  Finds out if a given entry exists in the dictionary. Since sections
+  are stored as keys with NULL associated values, this is the only way
+  of querying for the presence of sections in a dictionary.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_find_entry(dictionary * ini, char * entry) ;
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Parse an ini file and return an allocated dictionary object
+  @param    ininame Name of the ini file to read.
+  @return   Pointer to newly allocated dictionary
+
+  This is the parser for ini files. This function is called, providing
+  the name of the file to be read. It returns a dictionary object that
+  should not be accessed directly, but through accessor functions
+  instead.
+
+  The returned dictionary must be freed using iniparser_freedict().
+ */
+/*--------------------------------------------------------------------------*/
+dictionary * iniparser_load(const char * ininame);
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Free all memory associated to an ini dictionary
+  @param    d Dictionary to free
+  @return   void
+
+  Free all memory associated to an ini dictionary.
+  It is mandatory to call this function before the dictionary object
+  gets out of the current context.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_freedict(dictionary * d);
+
+#endif
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/src/dictionary.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/src/dictionary.cpp
new file mode 100644
index 000000000..3d28ffdd2
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/src/dictionary.cpp
@@ -0,0 +1,409 @@
+/*-------------------------------------------------------------------------*/
+/**
+   @file	dictionary.c
+   @author	N. Devillard
+   @date	Sep 2007
+   @version	$Revision: 4 $
+   @brief	Implements a dictionary for string variables.
+
+   This module implements a simple dictionary object, i.e. a list
+   of string/string associations. This object is useful to store e.g.
+   informations retrieved from a configuration file (ini files).
+*/
+/*--------------------------------------------------------------------------*/
+
+/*
+	$Id: dictionary.c,v 1.27 2007-11-23 21:39:18 ndevilla Exp $
+	$Revision: 4 $
+*/
+/*---------------------------------------------------------------------------
+   								Includes
+ ---------------------------------------------------------------------------*/
+#if defined(_WIN32)||defined(_WIN64)
+#define _CRT_SECURE_NO_WARNINGS 1
+#endif
+#include "dictionary.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+
+/** Maximum value size for integers and doubles. */
+#define MAXVALSZ	1024
+
+/** Minimal allocated number of entries in a dictionary */
+#define DICTMINSZ	128
+
+/** Invalid key token */
+#define DICT_INVALID_KEY    ((char*)-1)
+
+/*---------------------------------------------------------------------------
+  							Private functions
+ ---------------------------------------------------------------------------*/
+
+/* Doubles the allocated size associated to a pointer */
+/* 'size' is the current allocated size. */
+static void * mem_double(void * ptr, int size)
+{
+    void * newptr ;
+ 
+    newptr = calloc(2*size, 1);
+    if (newptr==NULL) {
+        return NULL ;
+    }
+    memcpy(newptr, ptr, size);
+    free(ptr);
+    return newptr ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Duplicate a string
+  @param    s String to duplicate
+  @return   Pointer to a newly allocated string, to be freed with free()
+
+  This is a replacement for strdup(). This implementation is provided
+  for systems that do not have it.
+ */
+/*--------------------------------------------------------------------------*/
+static char *xstrdup(const char *s)
+{
+    char * t ;
+    if (!s)
+        return NULL ;
+	size_t l = strlen(s)+1;
+    t = (char*)malloc(l) ;
+    if (t) {
+        strncpy(t,s,l);
+    }
+    return t ;
+}
+
+/*---------------------------------------------------------------------------
+  							Function codes
+ ---------------------------------------------------------------------------*/
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Compute the hash key for a string.
+  @param	key		Character string to use for key.
+  @return	1 unsigned int on at least 32 bits.
+
+  This hash function has been taken from an Article in Dr Dobbs Journal.
+  This is normally a collision-free function, distributing keys evenly.
+  The key is stored anyway in the struct so that collision can be avoided
+  by comparing the key itself in last resort.
+ */
+/*--------------------------------------------------------------------------*/
+int32_t dictionary_hash(const char *key)
+{
+	size_t		len ;
+	unsigned	hash ;
+	size_t			i ;
+
+	len = strlen(key);
+	for (hash=0, i=0 ; i<len ; i++) {
+		hash += (unsigned)key[i] ;
+		hash += (hash<<10);
+		hash ^= (hash>>6) ;
+	}
+	hash += (hash <<3);
+	hash ^= (hash >>11);
+	hash += (hash <<15);
+	return hash ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Create a new dictionary object.
+  @param	size	Optional initial size of the dictionary.
+  @return	1 newly allocated dictionary objet.
+
+  This function allocates a new dictionary object of given size and returns
+  it. If you do not know in advance (roughly) the number of entries in the
+  dictionary, give size=0.
+ */
+/*--------------------------------------------------------------------------*/
+dictionary * dictionary_new(int size)
+{
+	dictionary	*	d ;
+
+	/* If no size was specified, allocate space for DICTMINSZ */
+	if (size<DICTMINSZ) size=DICTMINSZ ;
+
+	if (!(d = (dictionary *)calloc(1, sizeof(dictionary)))) {
+		return NULL;
+	}
+	d->size = size ;
+	d->val  = (char **)calloc(size, sizeof(char*));
+	d->key  = (char **)calloc(size, sizeof(char*));
+	d->hash = (unsigned int *)calloc(size, sizeof(unsigned));
+	return d ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Delete a dictionary object
+  @param	d	dictionary object to deallocate.
+  @return	void
+
+  Deallocate a dictionary object and all memory associated to it.
+ */
+/*--------------------------------------------------------------------------*/
+void dictionary_del(dictionary * d)
+{
+	int		i ;
+
+	if (d==NULL) return ;
+	for (i=0 ; i<d->size ; i++) {
+		if (d->key[i]!=NULL)
+			free(d->key[i]);
+		if (d->val[i]!=NULL)
+			free(d->val[i]);
+	}
+	free(d->val);
+	free(d->key);
+	free(d->hash);
+	free(d);
+	return ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Get a value from a dictionary.
+  @param	d		dictionary object to search.
+  @param	key		Key to look for in the dictionary.
+  @param    def     Default value to return if key not found.
+  @return	1 pointer to internally allocated character string.
+
+  This function locates a key in a dictionary and returns a pointer to its
+  value, or the passed 'def' pointer if no such key can be found in
+  dictionary. The returned character pointer points to data internal to the
+  dictionary object, you should not try to free it or modify it.
+ */
+/*--------------------------------------------------------------------------*/
+const char *  dictionary_get(dictionary * d, const char *key, const char * def)
+{
+	int32_t	hash ;
+	size_t	i ;
+
+	hash = dictionary_hash(key);
+	for (i=0 ; i<(size_t)d->size ; i++) {
+        if (d->key[i]==NULL)
+            continue ;
+        /* Compare hash */
+		if (hash==(int32_t)d->hash[i]) {
+            /* Compare string, to avoid hash collisions */
+            if (!strcmp(key, d->key[i])) {
+				return d->val[i] ;
+			}
+		}
+	}
+	return def ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Set a value in a dictionary.
+  @param    d       dictionary object to modify.
+  @param    key     Key to modify or add.
+  @param    val     Value to add.
+  @return   int     0 if Ok, anything else otherwise
+
+  If the given key is found in the dictionary, the associated value is
+  replaced by the provided one. If the key cannot be found in the
+  dictionary, it is added to it.
+
+  It is Ok to provide a NULL value for val, but NULL values for the dictionary
+  or the key are considered as errors: the function will return immediately
+  in such a case.
+
+  Notice that if you dictionary_set a variable to NULL, a call to
+  dictionary_get will return a NULL value: the variable will be found, and
+  its value (NULL) is returned. In other words, setting the variable
+  content to NULL is equivalent to deleting the variable from the
+  dictionary. It is not possible (in this implementation) to have a key in
+  the dictionary without value.
+
+  This function returns non-zero in case of failure.
+ */
+/*--------------------------------------------------------------------------*/
+int dictionary_set(dictionary * d, const char *key, const char *val)
+{
+	int			i ;
+	unsigned	hash ;
+
+	if (d==NULL || key==NULL) return -1 ;
+	
+	/* Compute hash for this key */
+	hash = dictionary_hash(key) ;
+	/* Find if value is already in dictionary */
+	if (d->n>0) {
+		for (i=0 ; i<d->size ; i++) {
+            if (d->key[i]==NULL)
+                continue ;
+			if (hash==d->hash[i]) { /* Same hash value */
+				if (!strcmp(key, d->key[i])) {	 /* Same key */
+					/* Found a value: modify and return */
+					if (d->val[i]!=NULL)
+						free(d->val[i]);
+                    d->val[i] = val ? xstrdup(val) : NULL ;
+                    /* Value has been modified: return */
+					return 0 ;
+				}
+			}
+		}
+	}
+	/* Add a new value */
+	/* See if dictionary needs to grow */
+	if (d->n==d->size) {
+
+		/* Reached maximum size: reallocate dictionary */
+		d->val  = (char **)mem_double(d->val,  d->size * sizeof(char*)) ;
+		d->key  = (char **)mem_double(d->key,  d->size * sizeof(char*)) ;
+		d->hash = (unsigned int *)mem_double(d->hash, d->size * sizeof(unsigned)) ;
+        if ((d->val==NULL) || (d->key==NULL) || (d->hash==NULL)) {
+            /* Cannot grow dictionary */
+            return -1 ;
+        }
+		/* Double size */
+		d->size *= 2 ;
+	}
+
+    /* Insert key in the first empty slot */
+    for (i=0 ; i<d->size ; i++) {
+        if (d->key[i]==NULL) {
+            /* Add key here */
+            break ;
+        }
+    }
+	/* Copy key */
+	d->key[i]  = xstrdup(key);
+    d->val[i]  = val ? xstrdup(val) : NULL ;
+	d->hash[i] = hash;
+	d->n ++ ;
+	return 0 ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Delete a key in a dictionary
+  @param	d		dictionary object to modify.
+  @param	key		Key to remove.
+  @return   void
+
+  This function deletes a key in a dictionary. Nothing is done if the
+  key cannot be found.
+ */
+/*--------------------------------------------------------------------------*/
+void dictionary_unset(dictionary * d, const char *key)
+{
+	unsigned	hash ;
+	int			i ;
+
+	if (key == NULL) {
+		return;
+	}
+
+	hash = dictionary_hash(key);
+	for (i=0 ; i<d->size ; i++) {
+        if (d->key[i]==NULL)
+            continue ;
+        /* Compare hash */
+		if (hash==d->hash[i]) {
+            /* Compare string, to avoid hash collisions */
+            if (!strcmp(key, d->key[i])) {
+                /* Found key */
+                break ;
+			}
+		}
+	}
+    if (i>=d->size)
+        /* Key not found */
+        return ;
+
+    free(d->key[i]);
+    d->key[i] = NULL ;
+    if (d->val[i]!=NULL) {
+        free(d->val[i]);
+        d->val[i] = NULL ;
+    }
+    d->hash[i] = 0 ;
+    d->n -- ;
+    return ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Dump a dictionary to an opened file pointer.
+  @param	d	Dictionary to dump
+  @param	f	Opened file pointer.
+  @return	void
+
+  Dumps a dictionary onto an opened file pointer. Key pairs are printed out
+  as @c [Key]=[Value], one per line. It is Ok to provide stdout or stderr as
+  output file pointers.
+ */
+/*--------------------------------------------------------------------------*/
+void dictionary_dump(dictionary * d, FILE * out)
+{
+	int		i ;
+
+	if (d==NULL || out==NULL) return ;
+	if (d->n<1) {
+		fprintf(out, "empty dictionary\n");
+		return ;
+	}
+	for (i=0 ; i<d->size ; i++) {
+        if (d->key[i]) {
+            fprintf(out, "%20s\t[%s]\n",
+                    d->key[i],
+                    d->val[i] ? d->val[i] : "UNDEF");
+        }
+	}
+	return ;
+}
+
+
+/* Test code */
+#ifdef TESTDIC
+#define NVALS 20000
+int main(int argc, char *argv[])
+{
+	dictionary	*	d ;
+	char	*	val ;
+	int			i ;
+	char		cval[90] ;
+
+	/* Allocate dictionary */
+	printf("allocating...\n");
+	d = dictionary_new(0);
+	
+	/* Set values in dictionary */
+	printf("setting %d values...\n", NVALS);
+	for (i=0 ; i<NVALS ; i++) {
+		sprintf(cval, "%04d", i);
+		dictionary_set(d, cval, "salut");
+	}
+	printf("getting %d values...\n", NVALS);
+	for (i=0 ; i<NVALS ; i++) {
+		sprintf(cval, "%04d", i);
+		val = dictionary_get(d, cval, DICT_INVALID_KEY);
+		if (val==DICT_INVALID_KEY) {
+			printf("cannot get value for key [%s]\n", cval);
+		}
+	}
+    printf("unsetting %d values...\n", NVALS);
+	for (i=0 ; i<NVALS ; i++) {
+		sprintf(cval, "%04d", i);
+		dictionary_unset(d, cval);
+	}
+    if (d->n != 0) {
+        printf("error deleting values\n");
+    }
+	printf("deallocating...\n");
+	dictionary_del(d);
+	return 0 ;
+}
+#endif
+/* vim: set ts=4 et sw=4 tw=75 */
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/src/iniparser.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/src/iniparser.cpp
new file mode 100644
index 000000000..2a61d0256
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibINI/src/iniparser.cpp
@@ -0,0 +1,684 @@
+
+/*-------------------------------------------------------------------------*/
+/**
+   @file    iniparser.c
+   @author  N. Devillard
+   @date    Sep 2007
+   @version 3.0
+   @brief   Parser for ini files.
+
+	iniparser is a free stand-alone ini file parsing library.
+	It is written in portable ANSI C and should compile anywhere.
+	iniparser is distributed under an MIT license.
+	
+	From: http://ndevilla.free.fr/iniparser/
+	
+	Copyright (c) 2000-2012 by Nicolas Devillard.
+   
+	MIT License
+	
+	Permission is hereby granted, free of charge, to any person
+	obtaining a copy of this software and associated documentation
+	files (the "Software"), to deal in the Software without
+	restriction, including without limitation the rights to use,
+	copy, modify, merge, publish, distribute, sublicense, and/or sell
+	copies of the Software, and to permit persons to whom the
+	Software is furnished to do so, subject to the following
+	conditions:
+	
+	The above copyright notice and this permission notice shall be
+	included in all copies or substantial portions of the Software.
+	
+	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+	OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+	NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+	HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+	WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+	FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+	OTHER DEALINGS IN THE SOFTWARE.
+*/
+/*--------------------------------------------------------------------------*/
+/*
+    $Id: iniparser.c,v 2.18 2008-01-03 18:35:39 ndevilla Exp $
+    $Revision: 4 $
+    $Date: 01/23/2017 15:30 $
+*/
+/*---------------------------- Includes ------------------------------------*/
+#if defined(_WIN32)||defined(_WIN64)
+#define _CRT_SECURE_NO_WARNINGS 1
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "iniparser.h"
+
+/*---------------------------- Defines -------------------------------------*/
+#define ASCIILINESZ         (1024)
+#define INI_INVALID_KEY     ((char*)-1)
+
+/*---------------------------------------------------------------------------
+                        Private to this module
+ ---------------------------------------------------------------------------*/
+/**
+ * This enum stores the status for each parsed line (internal use only).
+ */
+typedef enum _line_status_ {
+    LINE_UNPROCESSED,
+    LINE_ERROR,
+    LINE_EMPTY,
+    LINE_COMMENT,
+    LINE_SECTION,
+    LINE_VALUE
+} line_status ;
+
+///*-------------------------------------------------------------------------*/
+///**
+//  @brief	Convert a string to lowercase.
+//  @param	s	String to convert.
+//  @return	ptr to statically allocated string.
+//
+//  This function returns a pointer to a statically allocated string
+//  containing a lowercased version of the input string. Do not free
+//  or modify the returned string! Since the returned string is statically
+//  allocated, it will be modified at each function call (not re-entrant).
+// */
+///*--------------------------------------------------------------------------*/
+//static char * strlwc(const char * s)
+//{
+//    static char l[ASCIILINESZ+1];
+//    int i ;
+//
+//    if (s==NULL) return NULL ;
+//    memset(l, 0, ASCIILINESZ+1);
+//    i=0 ;
+//    while (s[i] && i<ASCIILINESZ) {
+//        l[i] = (char)tolower((int)s[i]);
+//        i++ ;
+//    }
+//    l[ASCIILINESZ]=(char)0;
+//    return l ;
+//}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Remove blanks at the beginning and the end of a string.
+  @param	s	String to parse.
+  @return	ptr to statically allocated string.
+
+  This function returns a pointer to a statically allocated string,
+  which is identical to the input string, except that all blank
+  characters at the end and the beg. of the string have been removed.
+  Do not free or modify the returned string! Since the returned string
+  is statically allocated, it will be modified at each function call
+  (not re-entrant).
+ */
+/*--------------------------------------------------------------------------*/
+static char * strstrip(char * s)
+{
+    static char l[ASCIILINESZ+1];
+	char * last ;
+	
+    if (s==NULL) return NULL ;
+    
+	while (isspace((int)*s) && *s) s++;
+	memset(l, 0, ASCIILINESZ+1);
+	strncpy(l, s, ASCIILINESZ+1);
+	last = l + strlen(l);
+	while (last > l) {
+		if (!isspace((int)*(last-1)))
+				break ;
+		last -- ;
+	}
+	*last = (char)0;
+	return (char*)l ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get number of sections in a dictionary
+  @param    d   Dictionary to examine
+  @return   int Number of sections found in dictionary
+
+  This function returns the number of sections found in a dictionary.
+  The test to recognize sections is done on the string stored in the
+  dictionary: a section name is given as "section" whereas a key is
+  stored as "section:key", thus the test looks for entries that do not
+  contain a colon.
+
+  This clearly fails in the case a section name contains a colon, but
+  this should simply be avoided.
+
+  This function returns -1 in case of error.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_getnsec(dictionary * d)
+{
+    int i ;
+    int nsec ;
+
+    if (d==NULL) return -1 ;
+    nsec=0 ;
+    for (i=0 ; i<d->size ; i++) {
+        if (d->key[i]==NULL)
+            continue ;
+        if (strchr(d->key[i], ':')==NULL) {
+            nsec ++ ;
+        }
+    }
+    return nsec ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get name for section n in a dictionary.
+  @param    d   Dictionary to examine
+  @param    n   Section number (from 0 to nsec-1).
+  @return   Pointer to char string
+
+  This function locates the n-th section in a dictionary and returns
+  its name as a pointer to a string statically allocated inside the
+  dictionary. Do not free or modify the returned string!
+
+  This function returns NULL in case of error.
+ */
+/*--------------------------------------------------------------------------*/
+char * iniparser_getsecname(dictionary * d, int n)
+{
+    int i ;
+    int foundsec ;
+
+    if (d==NULL || n<0) return NULL ;
+    foundsec=0 ;
+    for (i=0 ; i<d->size ; i++) {
+        if (d->key[i]==NULL)
+            continue ;
+        if (strchr(d->key[i], ':')==NULL) {
+            foundsec++ ;
+            if (foundsec>n)
+                break ;
+        }
+    }
+    if (foundsec<=n) {
+        return NULL ;
+    }
+    return d->key[i] ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Dump a dictionary to an opened file pointer.
+  @param    d   Dictionary to dump.
+  @param    f   Opened file pointer to dump to.
+  @return   void
+
+  This function prints out the contents of a dictionary, one element by
+  line, onto the provided file pointer. It is OK to specify @c stderr
+  or @c stdout as output files. This function is meant for debugging
+  purposes mostly.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_dump(dictionary * d, FILE * f)
+{
+    int     i ;
+
+    if (d==NULL || f==NULL) return ;
+    for (i=0 ; i<d->size ; i++) {
+        if (d->key[i]==NULL)
+            continue ;
+        if (d->val[i]!=NULL) {
+            fprintf(f, "[%s]=[%s]\n", d->key[i], d->val[i]);
+        } else {
+            fprintf(f, "[%s]=UNDEF\n", d->key[i]);
+        }
+    }
+    return ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Save a dictionary to a loadable ini file
+  @param    d   Dictionary to dump
+  @param    f   Opened file pointer to dump to
+  @return   void
+
+  This function dumps a given dictionary into a loadable ini file.
+  It is Ok to specify @c stderr or @c stdout as output files.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_dump_ini(dictionary * d, FILE * f)
+{
+    int     i, j ;
+    char    keym[ASCIILINESZ+1];
+    int     nsec ;
+    char *  secname ;
+    int     seclen ;
+
+    if (d==NULL || f==NULL) return ;
+
+    nsec = iniparser_getnsec(d);
+    if (nsec<1) {
+        /* No section in file: dump all keys as they are */
+        for (i=0 ; i<d->size ; i++) {
+            if (d->key[i]==NULL)
+                continue ;
+            fprintf(f, "%s = %s\n", d->key[i], d->val[i]);
+        }
+        return ;
+    }
+    for (i=0 ; i<nsec ; i++) {
+        secname = iniparser_getsecname(d, i) ;
+        seclen  = (int)strlen(secname);
+        fprintf(f, "\n[%s]\n", secname);
+        snprintf(keym, sizeof(keym), "%s:", secname);
+        for (j=0 ; j<d->size ; j++) {
+            if (d->key[j]==NULL)
+                continue ;
+            if (!strncmp(d->key[j], keym, seclen+1)) {
+                fprintf(f,
+                        "%-30s = %s\n",
+                        d->key[j]+seclen+1,
+                        d->val[j] ? d->val[j] : "");
+            }
+        }
+    }
+    fprintf(f, "\n");
+    return ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key
+  @param    d       Dictionary to search
+  @param    key     Key string to look for
+  @param    def     Default value to return if key not found.
+  @return   pointer to statically allocated character string
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the pointer passed as 'def' is returned.
+  The returned char pointer is pointing to a string allocated in
+  the dictionary, do not free or modify it.
+ */
+/*--------------------------------------------------------------------------*/
+const char * iniparser_getstring(dictionary * d, const char * key, const char * def)
+{
+    const char * sval ;
+
+    if (d==NULL || key==NULL)
+        return def ;
+
+    //lc_key = strlwc(key);
+    sval = dictionary_get(d, key, def);
+    return sval ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key, convert to an int
+  @param    d Dictionary to search
+  @param    key Key string to look for
+  @param    notfound Value to return in case of error
+  @return   integer
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the notfound value is returned.
+
+  Supported values for integers include the usual C notation
+  so decimal, octal (starting with 0) and hexadecimal (starting with 0x)
+  are supported. Examples:
+
+  "42"      ->  42
+  "042"     ->  34 (octal -> decimal)
+  "0x42"    ->  66 (hexa  -> decimal)
+
+  Warning: the conversion may overflow in various ways. Conversion is
+  totally outsourced to strtol(), see the associated man page for overflow
+  handling.
+
+  Credits: Thanks to A. Becker for suggesting strtol()
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_getint(dictionary * d, const char * key, int notfound)
+{
+    const char    *   str ;
+
+    str = iniparser_getstring(d, key, INI_INVALID_KEY);
+    if (str==INI_INVALID_KEY) return notfound ;
+    return (int)strtol(str, NULL, 0);
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key, convert to a double
+  @param    d Dictionary to search
+  @param    key Key string to look for
+  @param    notfound Value to return in case of error
+  @return   double
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the notfound value is returned.
+ */
+/*--------------------------------------------------------------------------*/
+double iniparser_getdouble(dictionary * d, char * key, double notfound)
+{
+    const char    *   str ;
+
+    str = iniparser_getstring(d, key, INI_INVALID_KEY);
+    if (str==INI_INVALID_KEY) return notfound ;
+    return atof(str);
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Get the string associated to a key, convert to a boolean
+  @param    d Dictionary to search
+  @param    key Key string to look for
+  @param    notfound Value to return in case of error
+  @return   integer
+
+  This function queries a dictionary for a key. A key as read from an
+  ini file is given as "section:key". If the key cannot be found,
+  the notfound value is returned.
+
+  A true boolean is found if one of the following is matched:
+
+  - A string starting with 'y'
+  - A string starting with 'Y'
+  - A string starting with 't'
+  - A string starting with 'T'
+  - A string starting with '1'
+
+  A false boolean is found if one of the following is matched:
+
+  - A string starting with 'n'
+  - A string starting with 'N'
+  - A string starting with 'f'
+  - A string starting with 'F'
+  - A string starting with '0'
+
+  The notfound value returned if no boolean is identified, does not
+  necessarily have to be 0 or 1.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_getboolean(dictionary * d, const char * key, int notfound)
+{
+    const char    *   c ;
+    int         ret ;
+
+    c = iniparser_getstring(d, key, INI_INVALID_KEY);
+    if (c==INI_INVALID_KEY) return notfound ;
+    if (c[0]=='y' || c[0]=='Y' || c[0]=='1' || c[0]=='t' || c[0]=='T') {
+        ret = 1 ;
+    } else if (c[0]=='n' || c[0]=='N' || c[0]=='0' || c[0]=='f' || c[0]=='F') {
+        ret = 0 ;
+    } else {
+        ret = notfound ;
+    }
+    return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Finds out if a given entry exists in a dictionary
+  @param    ini     Dictionary to search
+  @param    entry   Name of the entry to look for
+  @return   integer 1 if entry exists, 0 otherwise
+
+  Finds out if a given entry exists in the dictionary. Since sections
+  are stored as keys with NULL associated values, this is the only way
+  of querying for the presence of sections in a dictionary.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_find_entry(
+    dictionary  *   ini,
+    char        *   entry
+)
+{
+    int found=0 ;
+    if (iniparser_getstring(ini, entry, INI_INVALID_KEY)!=INI_INVALID_KEY) {
+        found = 1 ;
+    }
+    return found ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Set an entry in a dictionary.
+  @param    ini     Dictionary to modify.
+  @param    entry   Entry to modify (entry name)
+  @param    val     New value to associate to the entry.
+  @return   int 0 if Ok, -1 otherwise.
+
+  If the given entry can be found in the dictionary, it is modified to
+  contain the provided value. If it cannot be found, -1 is returned.
+  It is Ok to set val to NULL.
+ */
+/*--------------------------------------------------------------------------*/
+int iniparser_setstring(dictionary * ini, const char * entry, const char * val)
+{
+    return dictionary_set(ini, entry, val) ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Delete an entry in a dictionary
+  @param    ini     Dictionary to modify
+  @param    entry   Entry to delete (entry name)
+  @return   void
+
+  If the given entry can be found, it is deleted from the dictionary.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_unset(dictionary * ini, char * entry)
+{
+    dictionary_unset(ini, entry);
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief	Load a single line from an INI file
+  @param    input_line  Input line, may be concatenated multi-line input
+  @param    section     Output space to store section
+  @param    key         Output space to store key
+  @param    value       Output space to store value
+  @return   line_status value
+ */
+/*--------------------------------------------------------------------------*/
+static line_status iniparser_line(
+    char * input_line,
+    char * section,
+    char * key,
+    char * value)
+{   
+    line_status sta ;
+    char        line[ASCIILINESZ+1];
+    int         len ;
+
+    strncpy(line, strstrip(input_line), sizeof(line));
+    len = (int)strlen(line);
+
+    sta = LINE_UNPROCESSED ;
+    if (len<1) {
+        /* Empty line */
+        sta = LINE_EMPTY ;
+    } else if (line[0]=='#') {
+        /* Comment line */
+        sta = LINE_COMMENT ; 
+    } else if (line[0]==';') {
+        /* Comment line */
+        sta = LINE_COMMENT ; 
+    } else if (line[0]=='[' && line[len-1]==']') {
+        /* Section name */
+        sscanf(line, "[%[^]]", section);
+        strcpy(section, strstrip(section));
+        sta = LINE_SECTION ;
+    } else if (sscanf (line, "%[^=] = \"%[^\"]\"", key, value) == 2
+           ||  sscanf (line, "%[^=] = '%[^\']'",   key, value) == 2
+           ||  sscanf (line, "%[^=] = %[^;#]",     key, value) == 2) {
+        /* Usual key=value, with or without comments */
+        strcpy(key, strstrip(key));
+        strcpy(value, strstrip(value));
+        /*
+         * sscanf cannot handle '' or "" as empty values
+         * this is done here
+         */
+        if (!strcmp(value, "\"\"") || (!strcmp(value, "''"))) {
+            value[0]=0 ;
+        }
+        sta = LINE_VALUE ;
+    } else if (sscanf(line, "%[^=] = %[;#]", key, value)==2
+           ||  sscanf(line, "%[^=] %[=]", key, value) == 2) {
+        /*
+         * Special cases:
+         * key=
+         * key=;
+         * key=#
+         */
+        strcpy(key, strstrip(key));
+        //strcpy(key, strlwc(key));
+        value[0]=0 ;
+        sta = LINE_VALUE ;
+    } else {
+        /* Generate syntax error */
+        sta = LINE_ERROR ;
+    }
+    return sta ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Parse an ini file and return an allocated dictionary object
+  @param    ininame Name of the ini file to read.
+  @return   Pointer to newly allocated dictionary
+
+  This is the parser for ini files. This function is called, providing
+  the name of the file to be read. It returns a dictionary object that
+  should not be accessed directly, but through accessor functions
+  instead.
+
+  The returned dictionary must be freed using iniparser_freedict().
+ */
+/*--------------------------------------------------------------------------*/
+dictionary * iniparser_load(const char * ininame)
+{
+    FILE * in ;
+
+    char line    [ASCIILINESZ+1] ;
+    char section [ASCIILINESZ+1] ;
+    char key     [ASCIILINESZ+1] ;
+    char tmp     [ASCIILINESZ+1] ;
+    char val     [ASCIILINESZ+1] ;
+
+    int  last=0 ;
+    int  len ;
+    int  lineno=0 ;
+    int  errs=0;
+
+    dictionary * dict ;
+
+    if ((in=fopen(ininame, "r"))==NULL) {
+        fprintf(stderr, "iniparser: cannot open %s\n", ininame);
+        return NULL ;
+    }
+
+    dict = dictionary_new(0) ;
+    if (!dict) {
+        fclose(in);
+        return NULL ;
+    }
+
+    memset(line,    0, ASCIILINESZ);
+    memset(section, 0, ASCIILINESZ);
+    memset(key,     0, ASCIILINESZ);
+    memset(val,     0, ASCIILINESZ);
+    last=0 ;
+
+    while (fgets(line+last, ASCIILINESZ-last, in)!=NULL) {
+        lineno++ ;
+        len = (int)strlen(line)-1;
+        /* Safety check against buffer overflows */
+        if (line[len]!='\n') {
+            fprintf(stderr,
+                    "iniparser: input line too long in %s (%d)\n",
+                    ininame,
+                    lineno);
+            dictionary_del(dict);
+            fclose(in);
+            return NULL ;
+        }
+        /* Get rid of \n and spaces at end of line */
+        while ((len>=0) &&
+                ((line[len]=='\n') || (isspace(line[len])))) {
+            line[len]=0 ;
+            len-- ;
+        }
+        /* Detect multi-line */
+        if (line[len]=='\\') {
+            /* Multi-line value */
+            last=len ;
+            continue ;
+        } else {
+            last=0 ;
+        }
+        switch (iniparser_line(line, section, key, val)) {
+            case LINE_EMPTY:
+            case LINE_COMMENT:
+            break ;
+
+            case LINE_SECTION:
+            errs = dictionary_set(dict, section, NULL);
+            break ;
+
+            case LINE_VALUE:
+            sprintf(tmp, "%s:%s", section, key);
+            errs = dictionary_set(dict, tmp, val) ;
+            break ;
+
+            case LINE_ERROR:
+            fprintf(stderr, "iniparser: syntax error in %s (%d):\n",
+                    ininame,
+                    lineno);
+            fprintf(stderr, "-> %s\n", line);
+            errs++ ;
+            break;
+
+            default:
+            break ;
+        }
+        memset(line, 0, ASCIILINESZ);
+        last=0;
+        if (errs<0) {
+            fprintf(stderr, "iniparser: memory allocation failure\n");
+            break ;
+        }
+    }
+    if (errs) {
+        dictionary_del(dict);
+        dict = NULL ;
+    }
+    fclose(in);
+    return dict ;
+}
+
+/*-------------------------------------------------------------------------*/
+/**
+  @brief    Free all memory associated to an ini dictionary
+  @param    d Dictionary to free
+  @return   void
+
+  Free all memory associated to an ini dictionary.
+  It is mandatory to call this function before the dictionary object
+  gets out of the current context.
+ */
+/*--------------------------------------------------------------------------*/
+void iniparser_freedict(dictionary * d)
+{
+    dictionary_del(d);
+}
+
+/* vim: set ts=4 et sw=4 tw=75 */
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/inc/tekEventsLinux.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/inc/tekEventsLinux.h
new file mode 100644
index 000000000..123ecfb06
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/inc/tekEventsLinux.h
@@ -0,0 +1,461 @@
+//*****************************************************************************
+// $Workfile: tekEventsLinux.h $
+// $Archive:: /ClearPath SC/LinuxPrjEclipse/sFoundation20/linux/inc/tekEvents $
+// $Revision: 12 $ $Date: 12/22/16 12:42 $
+//
+// DESCRIPTION:
+//		Thin layer to create synchronization objects for Linux.
+//
+// CREATION DATE:
+//		05/14/2004 13:03:56
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2004-2012  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			   *
+//******************************************************************************
+#ifndef __TEKEVENTS_H__
+#define	__TEKEVENTS_H__
+
+
+
+//******************************************************************************
+// NAME																           *
+// 	tekEvents.h headers
+//
+	#include <errno.h>
+	#include <pthread.h>
+	#include <semaphore.h>
+	#include <stdio.h>
+	#include <string>
+    #include <sys/time.h>
+
+	#include <assert.h>
+	#include "tekTypes.h"
+	using namespace std;
+	#define EOK 0
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																           *
+// 	tekEvents.h constants
+//
+//
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define SYNC_INFINITE  0xFFFFFFFFU
+#define INFINITE  DWORD(0xFFFFFFFF)
+#define LPSECURITY_ATTRIBUTES void *
+typedef void * HANDLE;
+
+
+//*****************************************************************************
+//   NAME
+//           CCaddAbsTime
+//
+//   CREATION DATE:
+//           03/29/2012 13:33
+//
+//   DESCRIPTION:
+/**
+          Add the required milliseconds from now and update
+          \a abs_time.
+
+          \param[in] incrMilliseconds time increment
+          \param[out] abs_time resulting time from now
+ **/
+//   SYNOPSIS:
+inline void CCaddAbsTime(timespec &abs_time, double incrMilliseconds)
+{
+	// Try better clock, if not fallback on common
+	//if(clock_gettime( CLOCK_MONOTONIC, &abs_time )) {
+		assert(clock_gettime( CLOCK_REALTIME, &abs_time ) == 0);
+	//}
+	nodeulong secs = nodeulong(incrMilliseconds/1000);
+	abs_time.tv_sec += secs;
+	// Prevent overflow on longer time-outs
+	abs_time.tv_nsec += (incrMilliseconds-secs*1000) * 1000000L;
+	if ( abs_time.tv_nsec > 1000000000L) {
+		abs_time.tv_nsec -= 1000000000L;
+		abs_time.tv_sec += 1;
+	}
+}
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//   NAME
+//           class CCSemaphore
+//
+//   CREATION DATE:
+//           02/08/2010 11:37:08
+//
+//   DESCRIPTION:
+///          The classic resource counting mutual exclusion device.  A request
+///          to Lock is blocked via the scheduler until some other thread
+///          Unlocks the resource. Optionally multiple "counts" can be made
+///          available if required.
+//
+//   SYNOPSIS:
+class CCSemaphore
+{
+public:
+	CCSemaphore (long lInitialCount = 0,
+			  long lMaxCount = 1,
+			  int lpsaAttributes = 0)
+	{
+		assert(sem_init( &sem, lpsaAttributes, unsigned(lMaxCount) )==EOK);
+	}
+	virtual ~CCSemaphore() {
+	    assert(sem_destroy(&sem)==EOK);
+	}
+
+	// Return TRUE if we own resource
+	virtual bool Lock (Uint32 timeoutMsec = SYNC_INFINITE)
+	{
+		int r = -1;
+		if ( timeoutMsec == SYNC_INFINITE ) {
+			r = sem_wait( &sem );
+		} else {
+			struct timespec abs_time;
+			CCaddAbsTime(abs_time, timeoutMsec);
+			r = sem_timedwait( &sem, &abs_time );
+		}
+	  	return r == -1 ? false : true;
+	}
+
+	// Release one item, return TRUE if succeeded
+	virtual int Unlock ()
+	{
+		return sem_post( &sem ) == 0 ? 1 : 0;
+	}
+
+	// Release multiple items and return the count that was left.
+	virtual bool Unlock (long lCount, long *lPrevCount = NULL)
+	{
+		for ( int ix = 0; ix < lCount; ++ix )
+			sem_post( &sem );
+		if ( lPrevCount != NULL )
+			sem_getvalue( &sem, (int *) lPrevCount );
+		return 1;
+	}
+
+protected:
+	sem_t sem;
+};
+//
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME
+//		class CCEvent
+//
+//  CREATION DATE:
+//		02/08/2010 11:37:08
+//
+//	DESCRIPTION:
+/**
+	A scheduler based blocking event. Multiple threads can wait for the
+	underlying event to "signal" via SetEvent to restart
+	their execution. There is an optional time-out for the wait.
+
+ 	Detailed description.
+**/
+//	SYNOPSIS:
+class CCEvent
+{
+private:
+	pthread_mutex_t mutex;
+	pthread_cond_t cond;
+	int manual_reset;
+	bool m_set;
+public:
+	CCEvent (bool bInitiallyOwn = false,
+			bool bManualReset = true,
+			LPSECURITY_ATTRIBUTES lpsaAttribute = NULL) :
+			manual_reset( bManualReset ),
+			m_set( bInitiallyOwn ) {
+		assert(pthread_mutex_init( &mutex, NULL )==EOK);
+		assert(pthread_cond_init( &cond, NULL )==EOK);
+ 	}
+	~CCEvent() {
+		int theErr;
+		assert((theErr=pthread_mutex_destroy(&mutex))==EOK);
+		assert((theErr=pthread_cond_destroy(&cond))==EOK);
+	}
+
+	// in Linux the semaphore always exists
+	bool isOK ()
+	{
+		return true;
+	}
+
+	// Signal and leave signaled our event
+	bool SetEvent ( bool do_mutex = true )
+	{
+//		_RPT1(_CRT_WARN, "Evt Set 0x%lx\n", this);
+		int r = EOK;
+		if ( do_mutex ) assert(pthread_mutex_lock( &mutex )==EOK);
+
+		if (!m_set) {
+			m_set = true;
+			r = pthread_cond_broadcast( &cond );
+		}
+		if ( do_mutex ) assert(pthread_mutex_unlock( &mutex )==EOK);
+	  	return r==EOK;
+	}
+
+	// Un-signal and block waiters
+	bool ResetEvent ()
+	{
+//		_RPT1(_CRT_WARN, "Evt Reset 0x%lx\n", this);
+		m_set = false;
+	  	return true;
+	}
+
+
+	// Cause the calling thread to block until "signaled" or TimeOut
+	// occurs. Returns TRUE if wait was signaled normally.
+	bool WaitFor ( unsigned timeoutMsec=SYNC_INFINITE )
+	{
+		assert(pthread_mutex_lock( &mutex )==EOK);
+		int r=EOK;
+		// Return if already signaled
+		if ( ! m_set ) {
+			if ( timeoutMsec == SYNC_INFINITE ) {
+				// Prevent spurious wakeup
+				do {
+					r = pthread_cond_wait( &cond, &mutex );
+				} while (r!=EOK && !m_set);
+			}
+			else {
+				// Create our time-out
+				struct timespec abs_time;
+				CCaddAbsTime(abs_time, timeoutMsec);
+				do {
+					r = pthread_cond_timedwait( &cond, &mutex, &abs_time );
+				} while (r!=EOK && r!=ETIMEDOUT && !m_set);
+			}
+		}
+		assert(pthread_mutex_unlock( &mutex )==EOK);
+	  	return (r == EOK);
+	}
+
+	HANDLE GetHandle() {
+		return(&cond);
+	}
+
+};
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME
+//		class CCCriticalSection
+//
+//  CREATION DATE:
+//		02/08/2010 11:37:08
+//
+//	DESCRIPTION:
+///		Create a critical section lockout.
+//
+//	SYNOPSIS:
+class CCCriticalSection
+{
+protected:
+	 pthread_mutex_t mutex;
+public:
+  	CCCriticalSection ()
+	{
+  		//pthread_mutexattr_t psharedm;
+  		//(void) pthread_mutexattr_init(&psharedm);
+  		//(void) pthread_mutexattr_settype(&psharedm, PTHREAD_MUTEX_RECURSIVE);
+  		//assert(pthread_mutex_init( &mutex, &psharedm )==EOK);
+  		assert(pthread_mutex_init( &mutex, NULL )==EOK);
+ 		// might need to set PTHREAD_PROCESS_SHARED
+	}
+
+  	~CCCriticalSection ()
+	{
+		pthread_mutex_destroy( &mutex );
+	}
+
+	HANDLE GetHandle ()
+	{
+	  return &mutex;
+	}
+	// Return TRUE if we released critical section
+	bool Unlock ()
+	{
+		return(pthread_mutex_unlock( &mutex )==EOK);
+	}
+
+	// Return TRUE if we own critical section
+	bool Lock ( Uint32 timeoutMsec=SYNC_INFINITE )
+	{
+		int r = 0;
+		if ( timeoutMsec == SYNC_INFINITE ) {
+			r = pthread_mutex_lock( &mutex );
+		} else {
+			struct timespec abs_time;
+			CCaddAbsTime(abs_time, timeoutMsec);
+			r = pthread_mutex_timedlock( &mutex, &abs_time );
+		}
+		//if ( r ) throw ;
+	  	return r==EOK;
+	}
+};
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME
+//		class CCMutex
+//
+//  CREATION DATE:
+//		02/08/2010 11:37:08
+//
+//	DESCRIPTION:
+///		Create a critical section lockout.
+//
+//	SYNOPSIS:
+class CCMutex
+{
+protected:
+	 pthread_mutex_t mutex;
+public:
+	 CCMutex ()
+	{
+  		//pthread_mutexattr_t psharedm;
+  		//(void) pthread_mutexattr_init(&psharedm);
+  		//(void) pthread_mutexattr_settype(&psharedm, PTHREAD_MUTEX_RECURSIVE);
+  		//assert(pthread_mutex_init( &mutex, &psharedm )==EOK);
+  		assert(pthread_mutex_init( &mutex, NULL )==EOK);
+ 		// might need to set PTHREAD_PROCESS_SHARED
+	}
+
+  	~CCMutex ()
+	{
+		pthread_mutex_destroy( &mutex );
+	}
+
+	HANDLE GetHandle ()
+	{
+	  return &mutex;
+	}
+	// Return TRUE if we released critical section
+	bool Unlock ()
+	{
+		return(pthread_mutex_unlock( &mutex )==EOK);
+	}
+
+	// Return TRUE if we own critical section
+	bool Lock ( Uint32 timeoutMsec=SYNC_INFINITE )
+	{
+		int r = 0;
+		if ( timeoutMsec == SYNC_INFINITE ) {
+			r = pthread_mutex_lock( &mutex );
+		} else {
+			struct timespec abs_time;
+			CCaddAbsTime(abs_time, timeoutMsec);
+			r = pthread_mutex_timedlock( &mutex, &abs_time );
+		}
+		//if ( r ) throw ;
+	  	return r==EOK;
+	}
+};
+//
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CCMTMultiLock Class
+//
+//  CREATION DATE:
+//		2012-03-27 13:40:33
+//
+//	DESCRIPTION:
+/**
+		Wait for one or all events to signal.
+
+**/
+class CCMTMultiLock
+{
+protected:
+	Uint32            m_dwUnlockCount;
+	Uint32            m_dwCount;
+	CCEvent           *m_hPreallocated[8];
+	bool              m_bPreallocated[8];
+	CCEvent * const *
+	                 m_ppObjectArray;
+	CCEvent         ** m_pHandleArray;
+	bool           * m_bLockedArray;
+
+public:
+	CCMTMultiLock(CCEvent *pObjects[], Uint32 dwCount,
+		          Uint32 UnlockCount=1, bool bWaitForAll=true,
+				  Uint32 dwTimeout=SYNC_INFINITE, Uint32 dwWakeMask=0);
+
+	~CCMTMultiLock();
+
+public:
+	Uint32 Lock(Uint32 dwTimeOut=SYNC_INFINITE,
+		     bool bWaitForAll=true,Uint32 dwWakeMask=0);
+
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		class CCatomicUpdate
+//
+//	DESCRIPTION:
+/**
+	Atomic increment and decrement / test object.
+**/
+//	SYNOPSIS:
+class CCatomicUpdate
+{
+private:
+	LONG m_value;
+public:
+	CCatomicUpdate() {
+		m_value = 0;
+	}
+
+	LONG Incr() {
+		return __sync_add_and_fetch(&m_value,1);
+	}
+
+	LONG Decr() {
+		return __sync_sub_and_fetch(&m_value,1);
+	}
+};
+//																			  *
+//*****************************************************************************
+
+
+#endif
+//=============================================================================
+//	END OF FILE tekEvents.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/tekEventsLinux.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/tekEventsLinux.cpp
new file mode 100644
index 000000000..f76076a9a
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/tekEventsLinux.cpp
@@ -0,0 +1,207 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/LinuxPrjEclipse/sFoundation20/linux/src/tekEventsLinux.cpp $
+// $Revision: 4 $ $Date: 9/19/16 12:11 $
+// $Workfile: tekEventsLinux.cpp $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief  Implementation module for a portable event based library for
+	the Linux platform.
+**/
+// PRINCIPLE AUTHORS:
+//		Dave Sewhuk
+//
+// CREATION DATE:
+//		2012-03-27 13:38:27
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2012  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	tekEventsLinux.cpp headers
+//
+	#include "tekEventsLinux.h"
+	#include <assert.h>
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	tekEventsLinux.cpp function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	tekEventsLinux.cpp constants
+//
+//
+const size_t MAXIMUM_WAIT_OBJECTS = 64;
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	tekEventsLinux.cpp static variables
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CCMTMultiLock::CCMTMultiLock
+//
+//	AUTHOR:
+//		Dave Sewhuk - created on 2012-03-27 13:42:31
+//
+//	DESCRIPTION:
+/**
+	Wait until all the events in the list signal when unlocking.
+
+	This version can only work with CCEvents and provides a subset
+	of the Windows functionality of the WaitForMultipleObjects
+	API function.
+
+ 	\param[in,out] xxx description
+	\return description
+
+**/
+//	SYNOPSIS:
+CCMTMultiLock::CCMTMultiLock(CCEvent *pObjects[],Uint32 dwCount,
+		          Uint32 UnlockCount, bool bWaitForAll,
+				  Uint32 dwTimeout, Uint32 dwWakeMask)
+{
+	//dwWakeMask=dwWakeMask;	// Suppress compiler warning
+	//dwTimeout=dwTimeout;	// Suppress compiler warning
+
+	m_dwUnlockCount = UnlockCount;
+	assert(dwCount > 0 && dwCount <= MAXIMUM_WAIT_OBJECTS);
+	assert(pObjects != NULL);
+	// Linux can't really do this
+	assert(bWaitForAll);
+
+	m_ppObjectArray = pObjects;
+	m_dwCount = dwCount;
+
+	// as an optimization, skip allocating array if
+	// we can use a small, pre-eallocated bunch of handles
+	if (m_dwCount > (sizeof(m_hPreallocated)/sizeof(m_hPreallocated[0]))) {
+		m_pHandleArray = new CCEvent *[m_dwCount];
+		m_bLockedArray = new bool[m_dwCount];
+	}
+	else {
+		m_pHandleArray = m_hPreallocated;
+		m_bLockedArray = m_bPreallocated;
+	}
+
+	// get list of handles from array of objects passed
+	for (Uint32 i = 0; i <m_dwCount; i++) {
+		assert(pObjects[i]);
+
+		m_pHandleArray[i] = pObjects[i];
+		m_bLockedArray[i] = false;
+	}
+	////Lock(dwTimeout,bWaitForAll,dwWakeMask);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CCMTMultiLock::~CCMTMultiLock
+//
+//	AUTHOR:
+//		Dave Sewhuk - created on 2012-03-27 13:43:39
+//
+//	DESCRIPTION:
+/**
+
+
+ 	\param[in,out] xxx description
+	\return description
+
+**/
+//	SYNOPSIS:
+CCMTMultiLock::~CCMTMultiLock()
+{
+	for (Uint32 i=0; i < m_dwCount; i++)
+	if (m_bLockedArray[i])
+	  	m_ppObjectArray[i]->SetEvent();
+
+	if (m_pHandleArray != m_hPreallocated) {
+		delete[] m_bLockedArray;
+		delete[] m_pHandleArray;
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CCMTMultiLock::Lock
+//
+//	AUTHOR:
+//		Dave Sewhuk - created on 2012-03-27 13:47:05
+//
+//	DESCRIPTION:
+/**
+
+
+ 	\param[in,out] xxx description
+	\return description
+
+**/
+//	SYNOPSIS:
+Uint32 CCMTMultiLock::Lock(Uint32 dwTimeOut,
+		     bool bWaitForAll,Uint32 dwWakeMask)
+{
+	Uint32 dwResult = 0;
+	//dwWakeMask=dwWakeMask;	// Suppress Compiler Warnings
+	if (bWaitForAll){
+		// Wait for all of our events to signal
+		for (Uint32 i = 0; i < m_dwCount; i++) {
+			m_bLockedArray[i] = m_pHandleArray[i]->WaitFor(dwTimeOut);
+			dwResult |= m_bLockedArray[i]<<i;
+		}
+	}
+	else {
+		assert(0);
+	}
+	return dwResult;
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+//=============================================================================
+//	END OF FILE tekEventsLinux.cpp
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/tekThreadsLinux.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/tekThreadsLinux.cpp
new file mode 100644
index 000000000..dcf30f573
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/tekThreadsLinux.cpp
@@ -0,0 +1,514 @@
+//*****************************************************************************
+// $Workfile: tekThreadsLinux.cpp $
+// $Archive: /ClearPath SC-1.0.123/User Driver/linux/src/tekThreadsLinux.cpp $
+// $Revision: 10 $ $Date: 12/09/16 4:45p $
+//
+// DESCRIPTION:
+/**
+	\file
+	\defgroup PortGrp Porting Abstraction Functions
+	\brief Linux Threading Implementation
+
+	This module implements the CThread virtual class for the Linux platform.
+**/
+//
+// CREATION DATE:
+//		01/18/2011 14:24:32
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2012  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	tekThreadsLinux.cpp headers
+//
+	#include <stdio.h>
+	#include <cassert>
+	#include <iostream>
+	#include <unistd.h>
+	#include <pthread.h>
+	#include <stdlib.h>
+	#include "tekThreads.h"
+	#include <assert.h>
+	#include <sys/types.h>
+    #include <sys/syscall.h>
+    #include <errno.h>
+    #include <asm-generic/errno-base.h>
+	using namespace std;
+
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	tekThreadsLinux.cpp function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	tekThreadsLinux.cpp constants
+//
+//
+	#pragma GCC diagnostic ignored "-Wunused-parameter"
+	// - - - - - - - - - - - - - - - - - - -
+	// DEBUG TRACING
+	// - - - - - - - - - - - - - - - - - - -
+#if !defined(TRACE_THREAD0)
+	#if defined( _DEBUG)
+	#define TRACE_THREAD0 0
+	#else
+	#define TRACE_THREAD0 0
+	#endif
+#endif
+	#define RPT_OUT _CRT_WARN
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	tekThreadsLinux.cpp static variables
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+//*****************************************************************************
+// NAME	  																	  *
+//		CThread::CThread
+//
+// DESCRIPTION:
+//		Construction/Destruction
+//
+// SYNOPSIS:
+CThread::CThread()
+{
+#if TRACE_THREAD0
+	_RPT0(RPT_OUT, "CThread::constructing\n");
+#endif
+	m_uiID = m_idThread = m_idThreadSaved = 0;
+	m_pTermFlag = new nodebool;
+	// We are not done yet
+	*m_pTermFlag = false;
+	m_lclOwnTerm = true;
+	m_context = NULL;
+	m_hThread = pthread_t(NULL);
+	m_running = false;
+}
+
+CThread::~CThread( )
+{
+	if (m_lclOwnTerm)
+		*m_pTermFlag = true;
+	if (m_hThread)	{
+		try {
+			TerminateAndWait();
+			#if TRACE_THREAD0
+				_RPT1(_CRT_WARN, "CThread destructor handle closed thrd=%d\n",
+						UIthreadID() );
+			#endif
+		}
+		catch(...) {
+			_RPT0(_CRT_WARN, "CThread destructor failed\n");
+		}
+	}
+	if (m_lclOwnTerm)
+		delete m_pTermFlag;
+
+	m_hThread = pthread_t(NULL);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		ThreadEntry
+//
+//	DESCRIPTION:
+/**
+	This is the static function the operating system will call on the
+	newly created thread. It is passed the object's \e this pointer to
+	allow access to the instance's state and member functions. This
+	method is a friend of CThread.
+
+ 	\param[in,out] arg Pointer to our class's this pointer to get access
+					   to the member functions and state.
+	\return it's argument
+
+**/
+//	SYNOPSIS:
+void *CThread::ThreadEntry( void * arg )
+{
+	CThread * t = static_cast< CThread * > ( arg );
+
+	t->m_idThreadSaved = nodeulong(t->m_idThread = pthread_self());
+	t->m_uiID = nodeulong(syscall(SYS_gettid));
+	// Setup random number generator
+	srand(1);				// reset random # gen
+	srand(t->m_seed);		// set the seed
+#if TRACE_THREAD0
+	_RPT1(RPT_OUT, "CThread::ThreadEntry, id=%d\n",
+			t->UIthreadID());
+#endif
+	t->Run( t->m_context );
+	// Signal completion event
+	if (t->m_lclOwnTerm)
+		*t->m_pTermFlag = true;
+	t->m_TermEvent.SetEvent();
+ 	//pthread_exit(arg);
+#if TRACE_THREAD0
+	_RPT1(_CRT_WARN,"CThread::Thread %d signaled and is exiting\n",
+				 t->UIthreadID());
+#endif
+	return (HANDLE)arg;
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::LaunchThread
+//
+//	DESCRIPTION:
+/**
+	Call this to start the thread,
+
+ 	\param[in,out] context Some \i context the
+	\return description
+
+**/
+//	SYNOPSIS:
+HANDLE CThread::LaunchThread( void *context, int priority )
+{
+	// This needs to get set right away so that nothing else thinks it's
+	// available.
+	int theErr;
+	m_context = context;
+	m_exitSection.Lock();
+#if TRACE_THREAD0
+	_RPT0(RPT_OUT, "CThread::LaunchThread\n");
+#endif
+
+    pthread_attr_t threadAttr;
+    struct sched_param  param;             // for setting priority
+    int32_t policy;
+
+    assert((theErr = pthread_getschedparam( pthread_self(), &policy, &param))==EOK);
+ 	assert((theErr = pthread_attr_init(&threadAttr))==EOK);
+ 	// Assign lighter weight stack
+ 	const int STACK_SIZE = 250000;
+ 	assert((theErr = pthread_attr_setstacksize(&threadAttr, STACK_SIZE))==EOK);
+#if 0
+    // TODO: Work out priority adjuster
+	assert((theErr = pthread_attr_setschedpolicy (&threadAttr, SCHED_RR))==EOK);
+    if (priority!=0) {
+    	_RPT1(RPT_OUT, "CThread::LaunchThread, prio adj=%d\n", priority);
+    	// TODO: changing this leads to dead-lock in netStateInfo construction
+		//theErr = pthread_attr_setinheritsched (&threadAttr, PTHREAD_EXPLICIT_SCHED);
+		assert((theErr = pthread_attr_setinheritsched (&threadAttr, PTHREAD_INHERIT_SCHED))==EOK);
+		// Adjust thread base priority
+		param.sched_priority += priority;
+		assert((theErr = pthread_attr_setschedparam (&threadAttr, &param))==EOK);
+		//theErr = pthread_attr_setschedpolicy (&threadAttr, SCHED_OTHER);
+    }
+#endif
+    theErr= pthread_create(&m_hThread, &threadAttr,
+                                ThreadEntry, this);
+ //   theErr= pthread_create(&m_hThread, NULL,
+ //                               ThreadEntry, this);
+    if (theErr != EOK) {
+        _RPT1(_CRT_WARN, "CThread::LaunchThread create err=%d\n", theErr);
+        assert(theErr==EOK);
+    }
+//assert((theErr = pthread_create(&m_hThread, &threadAttr,
+//							ThreadEntry, this))==EOK);
+    pthread_attr_destroy(&threadAttr);
+    m_exitSection.Unlock();
+
+	return (HANDLE)m_hThread;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::Sleep
+//
+//	DESCRIPTION:
+/**
+	Suspend the current thread for \e milliseconds.
+
+ 	\param[in] milliseconds Suspension time.
+	\return description
+
+**/
+//	SYNOPSIS:
+void CThread::Sleep(Uint32 milliseconds)
+{
+	// Convert to microseconds
+	usleep(milliseconds*1000);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::WaitForTerm
+//
+//	DESCRIPTION:
+/**
+	This function will wait for the thread function to return, signalling
+	the end of the the thread's Run function execution. The classes's
+	Run function dispatcher will still be running after this returns and
+	all the application's thread activities are guaranteed to be complete
+	when this returns TRUE.
+
+**/
+//	SYNOPSIS:
+nodebool CThread::WaitForTerm()
+{
+	nodebool exitState = FALSE;
+	// Lock state from thread
+	m_exitSection.Lock();
+	// Thread already dead!
+	if (!m_running) {
+		#if TRACE_THREAD0
+			_RPT1(RPT_OUT, "CThread::WaitForTerm already died %d\n",
+								UIthreadID());
+		#endif
+		exitState = TRUE;
+	}
+	// The thread is still "running", wait for it to signal the
+	// end of its control function.
+	else {
+		#if TRACE_THREAD0
+			_RPT1(RPT_OUT, "CThread::WaitForTerm waiting for thread %d\n",
+							 UIthreadID());
+		#endif
+		// Wait for it to terminate on its own
+		exitState = m_TermEvent.WaitFor(30000);
+		if (!exitState) {
+			// Failed to timely die, force kill it.
+			//TODO_LINUX pthread_cancel(m_hThread);
+			_RPT2(RPT_OUT, "CThread::WaitForTerm failed Run terminate, id=%d, exitState=%d\n",
+						m_idThreadSaved, exitState);
+		}
+		#if TRACE_THREAD0
+			_RPT2(RPT_OUT, "CThread::WaitForTerm terminated, id=%d, exitState=%d\n",
+						UIthreadID(), exitState);
+		#endif
+        // We are really gone, now, set state to reflect this
+		m_idThread = 0;
+		m_running = false;
+	}
+	// Unlock state from thread
+	m_exitSection.Unlock();
+	return(exitState);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::Terminate
+//
+//	DESCRIPTION:
+/**
+	Call this function to terminate the thread.
+
+	\return handle/ptr to thread
+**/
+//	SYNOPSIS:
+void *CThread::Terminate()
+{
+#if TRACE_THREAD0
+	_RPT1(RPT_OUT, "CThread::Terminate terminating thread %d\n",
+					 UIthreadID());
+#endif
+	// Thread still OK?
+	if (m_hThread) {
+		if (m_pTermFlag) {
+			// Own m_running to prevent exit race
+			m_exitSection.Lock();
+			*m_pTermFlag = true;
+			// Insure we break through the parking event
+			m_ThreadParkedEvent.SetEvent();
+			#ifdef THREAD_SLOTS
+				ShuttingDown.emit();
+			#endif
+			// Join with the thread until it terminates.
+			if (m_hThread) {
+				m_lastErr = pthread_join( m_hThread, &m_status );
+				if (m_lastErr)
+					_RPT2(RPT_OUT, "CThread::Terminate join failed id=%d, join ret'd=%d\n",
+													 m_idThreadSaved, m_lastErr);
+#if TRACE_THREAD0
+				_RPT2(RPT_OUT, "CThread::Terminate id=%d, join ret'd=%d\n",
+								 UIthreadID(), m_lastErr);
+#endif
+			}
+            // Return TLS and internal junk, else leak
+            if (m_hThread) {
+                // Note this usually returns ESRCH, but the leak is gone
+                /*int theDetachErr = */pthread_detach(m_hThread);
+               // if (theDetachErr)
+                //    _RPT1(_CRT_WARN, "CThread::Terminate detach err=%d\n", theDetachErr);
+                //assert(theDetachErr!=EOK);
+            }
+			// One join per terminate!
+			m_hThread = pthread_t(NULL);
+			m_running = false;
+			m_idThread = 0;
+			// Release m_running lock
+			m_exitSection.Unlock();
+		}
+		else {
+			// Insure we break through the parking event
+			m_ThreadParkedEvent.SetEvent();
+		}
+	}
+	return((void *)m_hThread);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::TerminateAndWait
+//
+//	DESCRIPTION:
+/**
+	Signal the thread function to terminate and wait for it to occur.
+**/
+//	SYNOPSIS:
+void CThread::TerminateAndWait()
+{
+#if TRACE_THREAD0
+	_RPT1(_CRT_WARN, "CThread::TerminateAndWait thrd=%d\n",
+			UIthreadID() );
+#endif
+	Terminate();
+	WaitForTerm();
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::SetTerminateFlag
+//
+//	DESCRIPTION:
+/**
+	This function is useful for tying many thread instances together to a
+	common termination flag.
+
+ 	\param[in] flag Pointer to the shared termination flag.
+**/
+//	SYNOPSIS:
+void CThread::SetTerminateFlag(nodebool *pFlag)
+{
+	// If we own our terminate flag, release and let owner
+	// control it.
+
+	// Own m_running to prevent exit race
+//    printf("CThread::SetTerminateFlag Start\n");
+	m_exitSection.Lock();
+	if (m_lclOwnTerm) {
+		delete m_pTermFlag;
+		m_lclOwnTerm = false;
+	}
+	m_pTermFlag = pFlag;
+	m_exitSection.Unlock();
+//    printf("CThread::SetTerminateFlag Stop\n");
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::CurrentThreadID
+//
+//	DESCRIPTION:
+/**
+	Utility function to return this instance's thread ID. This
+	may or may not match the internal OS identifier depending
+	on the platform.
+
+	\see UIthreadID
+
+	\return OS specific thread ID for current thread
+
+**/
+//	SYNOPSIS:
+nodeulong CThread::CurrentThreadID()
+{
+	return(nodeulong(pthread_self()));
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CThread::UIthreadID
+//
+//	DESCRIPTION:
+/**
+	Utility function to return this instance's thread ID. It is useful for
+	debugging and various low level reports as it should match
+	the debugger's identifiers.
+
+	\return OS specific thread ID for current thread
+
+**/
+//	SYNOPSIS:
+nodeulong CThread::UIthreadID()
+{
+    return(m_uiID);
+}
+//																			  *
+//*****************************************************************************
+
+
+//=============================================================================
+//	END OF FILE tekThreadsLinux.cpp
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/version.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/version.cpp
new file mode 100644
index 000000000..2ba6e0a69
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibLinuxOS/src/version.cpp
@@ -0,0 +1,114 @@
+/*
+ * version.cpp
+ *
+ *  Created on: Jun 23, 2016
+ *      Author: dave
+ *
+ *  Extract version information about a file. This is mostly a Windows thing for now.
+ */
+
+
+#include "version.h"
+
+CVersionInfo::CVersionInfo(void)
+{
+	m_bValidPath = false;
+	m_bVersionInfoExists = false;
+	m_nLanguage = 0;
+	m_nLangCount = 0;
+}
+
+
+CVersionInfo::~CVersionInfo(void)
+{
+
+}
+
+
+bool CVersionInfo::SetFilePath(string szPath)
+{
+	return false;
+}
+
+
+bool CVersionInfo::SetLanguage(int nLanguage)
+{
+	return false;
+}
+
+
+int CVersionInfo::GetLanguageCount(void)
+{
+	return 0;
+}
+
+
+string CVersionInfo::GetComments(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetCompanyName(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetFileDescription(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetFileVersion(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetInternalName(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetLegalCopyright(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetLegalTrademarks(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetOriginalFilename(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetProductName(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetProductVersion(void)
+{
+	return "N/A";
+}
+
+
+string CVersionInfo::GetPrivateBuild(void)
+{
+	return "N/A";
+}
+string CVersionInfo::GetSpecialBuild(void)
+{
+	return "N/A";
+}
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/ErrCodeStr.hpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/ErrCodeStr.hpp
new file mode 100644
index 000000000..e677a96f9
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/ErrCodeStr.hpp
@@ -0,0 +1,16 @@
+#pragma once
+#include "pugixml.hpp"
+
+class ErrCodeStr
+{
+private:
+	pugi::xml_document def_document;
+	pugi::xml_node definitions;
+
+
+public:
+	void load(char* filename);
+	char* lookup(char errCode[]);
+	// Create an unloaded instance
+	ErrCodeStr();
+};
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/pugiconfig.hpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/pugiconfig.hpp
new file mode 100644
index 000000000..2d1e6aa8b
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/pugiconfig.hpp
@@ -0,0 +1,74 @@
+/**
+ * pugixml parser - version 1.8
+ * --------------------------------------------------------
+ * Copyright (C) 2006-2016, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com)
+ * Report bugs and download new versions at http://pugixml.org/
+ *
+ * This library is distributed under the MIT License. See notice at the end
+ * of this file.
+ *
+ * This work is based on the pugxml parser, which is:
+ * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net)
+ */
+
+#ifndef HEADER_PUGICONFIG_HPP
+#define HEADER_PUGICONFIG_HPP
+
+// Uncomment this to enable wchar_t mode
+// #define PUGIXML_WCHAR_MODE
+
+// Uncomment this to enable compact mode
+// #define PUGIXML_COMPACT
+
+// Uncomment this to disable XPath
+// #define PUGIXML_NO_XPATH
+
+// Uncomment this to disable STL
+// #define PUGIXML_NO_STL
+
+// Uncomment this to disable exceptions
+// #define PUGIXML_NO_EXCEPTIONS
+
+// Set this to control attributes for public classes/functions, i.e.:
+// #define PUGIXML_API __declspec(dllexport) // to export all public symbols from DLL
+// #define PUGIXML_CLASS __declspec(dllimport) // to import all classes from DLL
+// #define PUGIXML_FUNCTION __fastcall // to set calling conventions to all public functions to fastcall
+// In absence of PUGIXML_CLASS/PUGIXML_FUNCTION definitions PUGIXML_API is used instead
+
+// Tune these constants to adjust memory-related behavior
+// #define PUGIXML_MEMORY_PAGE_SIZE 32768
+// #define PUGIXML_MEMORY_OUTPUT_STACK 10240
+// #define PUGIXML_MEMORY_XPATH_PAGE_SIZE 4096
+
+// Uncomment this to switch to header-only version
+// #define PUGIXML_HEADER_ONLY
+
+// Uncomment this to enable long long support
+// #define PUGIXML_HAS_LONG_LONG
+
+#endif
+
+/**
+ * Copyright (c) 2006-2016 Arseny Kapoulkine
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/pugixml.hpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/pugixml.hpp
new file mode 100644
index 000000000..6288d4bd9
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/inc/pugixml.hpp
@@ -0,0 +1,1434 @@
+/**
+ * pugixml parser - version 1.8
+ * --------------------------------------------------------
+ * Copyright (C) 2006-2016, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com)
+ * Report bugs and download new versions at http://pugixml.org/
+ *
+ * This library is distributed under the MIT License. See notice at the end
+ * of this file.
+ *
+ * This work is based on the pugxml parser, which is:
+ * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net)
+ */
+
+#ifndef PUGIXML_VERSION
+// Define version macro; evaluates to major * 100 + minor so that it's safe to use in less-than comparisons
+#	define PUGIXML_VERSION 180
+#endif
+
+// Include user configuration file (this can define various configuration macros)
+#include "pugiconfig.hpp"
+
+#ifndef HEADER_PUGIXML_HPP
+#define HEADER_PUGIXML_HPP
+
+// Include stddef.h for size_t and ptrdiff_t
+#include <stddef.h>
+
+// Include exception header for XPath
+#if !defined(PUGIXML_NO_XPATH) && !defined(PUGIXML_NO_EXCEPTIONS)
+#	include <exception>
+#endif
+
+// Include STL headers
+#ifndef PUGIXML_NO_STL
+#	include <iterator>
+#	include <iosfwd>
+#	include <string>
+#endif
+
+// Macro for deprecated features
+#ifndef PUGIXML_DEPRECATED
+#	if defined(__GNUC__)
+#		define PUGIXML_DEPRECATED __attribute__((deprecated))
+#	elif defined(_MSC_VER) && _MSC_VER >= 1300
+#		define PUGIXML_DEPRECATED __declspec(deprecated)
+#	else
+#		define PUGIXML_DEPRECATED
+#	endif
+#endif
+
+// If no API is defined, assume default
+#ifndef PUGIXML_API
+#	define PUGIXML_API
+#endif
+
+// If no API for classes is defined, assume default
+#ifndef PUGIXML_CLASS
+#	define PUGIXML_CLASS PUGIXML_API
+#endif
+
+// If no API for functions is defined, assume default
+#ifndef PUGIXML_FUNCTION
+#	define PUGIXML_FUNCTION PUGIXML_API
+#endif
+
+// If the platform is known to have long long support, enable long long functions
+#ifndef PUGIXML_HAS_LONG_LONG
+#	if __cplusplus >= 201103
+#		define PUGIXML_HAS_LONG_LONG
+#	elif defined(_MSC_VER) && _MSC_VER >= 1400
+#		define PUGIXML_HAS_LONG_LONG
+#	endif
+#endif
+
+// If the platform is known to have move semantics support, compile move ctor/operator implementation
+#ifndef PUGIXML_HAS_MOVE
+#	if __cplusplus >= 201103
+#		define PUGIXML_HAS_MOVE
+#	elif defined(_MSC_VER) && _MSC_VER >= 1600
+#		define PUGIXML_HAS_MOVE
+#	endif
+#endif
+
+// If C++ is 2011 or higher, add 'override' qualifiers
+#ifndef PUGIXML_OVERRIDE
+#	if __cplusplus >= 201103
+#		define PUGIXML_OVERRIDE override
+#	else
+#		define PUGIXML_OVERRIDE
+#	endif
+#endif
+
+// Character interface macros
+#ifdef PUGIXML_WCHAR_MODE
+#	define PUGIXML_TEXT(t) L ## t
+#	define PUGIXML_CHAR wchar_t
+#else
+#	define PUGIXML_TEXT(t) t
+#	define PUGIXML_CHAR char
+#endif
+
+namespace pugi
+{
+	// Character type used for all internal storage and operations; depends on PUGIXML_WCHAR_MODE
+	typedef PUGIXML_CHAR char_t;
+
+#ifndef PUGIXML_NO_STL
+	// String type used for operations that work with STL string; depends on PUGIXML_WCHAR_MODE
+	typedef std::basic_string<PUGIXML_CHAR, std::char_traits<PUGIXML_CHAR>, std::allocator<PUGIXML_CHAR> > string_t;
+#endif
+}
+
+// The PugiXML namespace
+namespace pugi
+{
+	// Tree node types
+	enum xml_node_type
+	{
+		node_null,			// Empty (null) node handle
+		node_document,		// A document tree's absolute root
+		node_element,		// Element tag, i.e. '<node/>'
+		node_pcdata,		// Plain character data, i.e. 'text'
+		node_cdata,			// Character data, i.e. '<![CDATA[text]]>'
+		node_comment,		// Comment tag, i.e. '<!-- text -->'
+		node_pi,			// Processing instruction, i.e. '<?name?>'
+		node_declaration,	// Document declaration, i.e. '<?xml version="1.0"?>'
+		node_doctype		// Document type declaration, i.e. '<!DOCTYPE doc>'
+	};
+
+	// Parsing options
+
+	// Minimal parsing mode (equivalent to turning all other flags off).
+	// Only elements and PCDATA sections are added to the DOM tree, no text conversions are performed.
+	const unsigned int parse_minimal = 0x0000;
+
+	// This flag determines if processing instructions (node_pi) are added to the DOM tree. This flag is off by default.
+	const unsigned int parse_pi = 0x0001;
+
+	// This flag determines if comments (node_comment) are added to the DOM tree. This flag is off by default.
+	const unsigned int parse_comments = 0x0002;
+
+	// This flag determines if CDATA sections (node_cdata) are added to the DOM tree. This flag is on by default.
+	const unsigned int parse_cdata = 0x0004;
+
+	// This flag determines if plain character data (node_pcdata) that consist only of whitespace are added to the DOM tree.
+	// This flag is off by default; turning it on usually results in slower parsing and more memory consumption.
+	const unsigned int parse_ws_pcdata = 0x0008;
+
+	// This flag determines if character and entity references are expanded during parsing. This flag is on by default.
+	const unsigned int parse_escapes = 0x0010;
+
+	// This flag determines if EOL characters are normalized (converted to #xA) during parsing. This flag is on by default.
+	const unsigned int parse_eol = 0x0020;
+
+	// This flag determines if attribute values are normalized using CDATA normalization rules during parsing. This flag is on by default.
+	const unsigned int parse_wconv_attribute = 0x0040;
+
+	// This flag determines if attribute values are normalized using NMTOKENS normalization rules during parsing. This flag is off by default.
+	const unsigned int parse_wnorm_attribute = 0x0080;
+
+	// This flag determines if document declaration (node_declaration) is added to the DOM tree. This flag is off by default.
+	const unsigned int parse_declaration = 0x0100;
+
+	// This flag determines if document type declaration (node_doctype) is added to the DOM tree. This flag is off by default.
+	const unsigned int parse_doctype = 0x0200;
+
+	// This flag determines if plain character data (node_pcdata) that is the only child of the parent node and that consists only
+	// of whitespace is added to the DOM tree.
+	// This flag is off by default; turning it on may result in slower parsing and more memory consumption.
+	const unsigned int parse_ws_pcdata_single = 0x0400;
+
+	// This flag determines if leading and trailing whitespace is to be removed from plain character data. This flag is off by default.
+	const unsigned int parse_trim_pcdata = 0x0800;
+
+	// This flag determines if plain character data that does not have a parent node is added to the DOM tree, and if an empty document
+	// is a valid document. This flag is off by default.
+	const unsigned int parse_fragment = 0x1000;
+
+	// This flag determines if plain character data is be stored in the parent element's value. This significantly changes the structure of
+	// the document; this flag is only recommended for parsing documents with many PCDATA nodes in memory-constrained environments.
+	// This flag is off by default.
+	const unsigned int parse_embed_pcdata = 0x2000;
+
+	// The default parsing mode.
+	// Elements, PCDATA and CDATA sections are added to the DOM tree, character/reference entities are expanded,
+	// End-of-Line characters are normalized, attribute values are normalized using CDATA normalization rules.
+	const unsigned int parse_default = parse_cdata | parse_escapes | parse_wconv_attribute | parse_eol;
+
+	// The full parsing mode.
+	// Nodes of all types are added to the DOM tree, character/reference entities are expanded,
+	// End-of-Line characters are normalized, attribute values are normalized using CDATA normalization rules.
+	const unsigned int parse_full = parse_default | parse_pi | parse_comments | parse_declaration | parse_doctype;
+
+	// These flags determine the encoding of input data for XML document
+	enum xml_encoding
+	{
+		encoding_auto,		// Auto-detect input encoding using BOM or < / <? detection; use UTF8 if BOM is not found
+		encoding_utf8,		// UTF8 encoding
+		encoding_utf16_le,	// Little-endian UTF16
+		encoding_utf16_be,	// Big-endian UTF16
+		encoding_utf16,		// UTF16 with native endianness
+		encoding_utf32_le,	// Little-endian UTF32
+		encoding_utf32_be,	// Big-endian UTF32
+		encoding_utf32,		// UTF32 with native endianness
+		encoding_wchar,		// The same encoding wchar_t has (either UTF16 or UTF32)
+		encoding_latin1
+	};
+
+	// Formatting flags
+
+	// Indent the nodes that are written to output stream with as many indentation strings as deep the node is in DOM tree. This flag is on by default.
+	const unsigned int format_indent = 0x01;
+
+	// Write encoding-specific BOM to the output stream. This flag is off by default.
+	const unsigned int format_write_bom = 0x02;
+
+	// Use raw output mode (no indentation and no line breaks are written). This flag is off by default.
+	const unsigned int format_raw = 0x04;
+
+	// Omit default XML declaration even if there is no declaration in the document. This flag is off by default.
+	const unsigned int format_no_declaration = 0x08;
+
+	// Don't escape attribute values and PCDATA contents. This flag is off by default.
+	const unsigned int format_no_escapes = 0x10;
+
+	// Open file using text mode in xml_document::save_file. This enables special character (i.e. new-line) conversions on some systems. This flag is off by default.
+	const unsigned int format_save_file_text = 0x20;
+
+	// Write every attribute on a new line with appropriate indentation. This flag is off by default.
+	const unsigned int format_indent_attributes = 0x40;
+
+	// Don't output empty element tags, instead writing an explicit start and end tag even if there are no children. This flag is off by default.
+	const unsigned int format_no_empty_element_tags = 0x80;
+
+	// The default set of formatting flags.
+	// Nodes are indented depending on their depth in DOM tree, a default declaration is output if document has none.
+	const unsigned int format_default = format_indent;
+
+	// Forward declarations
+	struct xml_attribute_struct;
+	struct xml_node_struct;
+
+	class xml_node_iterator;
+	class xml_attribute_iterator;
+	class xml_named_node_iterator;
+
+	class xml_tree_walker;
+
+	struct xml_parse_result;
+
+	class xml_node;
+
+	class xml_text;
+
+	#ifndef PUGIXML_NO_XPATH
+	class xpath_node;
+	class xpath_node_set;
+	class xpath_query;
+	class xpath_variable_set;
+	#endif
+
+	// Range-based for loop support
+	template <typename It> class xml_object_range
+	{
+	public:
+		typedef It const_iterator;
+		typedef It iterator;
+
+		xml_object_range(It b, It e): _begin(b), _end(e)
+		{
+		}
+
+		It begin() const { return _begin; }
+		It end() const { return _end; }
+
+	private:
+		It _begin, _end;
+	};
+
+	// Writer interface for node printing (see xml_node::print)
+	class PUGIXML_CLASS xml_writer
+	{
+	public:
+		virtual ~xml_writer() {}
+
+		// Write memory chunk into stream/file/whatever
+		virtual void write(const void* data, size_t size) = 0;
+	};
+
+	// xml_writer implementation for FILE*
+	class PUGIXML_CLASS xml_writer_file: public xml_writer
+	{
+	public:
+		// Construct writer from a FILE* object; void* is used to avoid header dependencies on stdio
+		xml_writer_file(void* file);
+
+		virtual void write(const void* data, size_t size) PUGIXML_OVERRIDE;
+
+	private:
+		void* file;
+	};
+
+	#ifndef PUGIXML_NO_STL
+	// xml_writer implementation for streams
+	class PUGIXML_CLASS xml_writer_stream: public xml_writer
+	{
+	public:
+		// Construct writer from an output stream object
+		xml_writer_stream(std::basic_ostream<char, std::char_traits<char> >& stream);
+		xml_writer_stream(std::basic_ostream<wchar_t, std::char_traits<wchar_t> >& stream);
+
+		virtual void write(const void* data, size_t size) PUGIXML_OVERRIDE;
+
+	private:
+		std::basic_ostream<char, std::char_traits<char> >* narrow_stream;
+		std::basic_ostream<wchar_t, std::char_traits<wchar_t> >* wide_stream;
+	};
+	#endif
+
+	// A light-weight handle for manipulating attributes in DOM tree
+	class PUGIXML_CLASS xml_attribute
+	{
+		friend class xml_attribute_iterator;
+		friend class xml_node;
+
+	private:
+		xml_attribute_struct* _attr;
+
+		typedef void (*unspecified_bool_type)(xml_attribute***);
+
+	public:
+		// Default constructor. Constructs an empty attribute.
+		xml_attribute();
+
+		// Constructs attribute from internal pointer
+		explicit xml_attribute(xml_attribute_struct* attr);
+
+		// Safe bool conversion operator
+		operator unspecified_bool_type() const;
+
+		// Borland C++ workaround
+		bool operator!() const;
+
+		// Comparison operators (compares wrapped attribute pointers)
+		bool operator==(const xml_attribute& r) const;
+		bool operator!=(const xml_attribute& r) const;
+		bool operator<(const xml_attribute& r) const;
+		bool operator>(const xml_attribute& r) const;
+		bool operator<=(const xml_attribute& r) const;
+		bool operator>=(const xml_attribute& r) const;
+
+		// Check if attribute is empty
+		bool empty() const;
+
+		// Get attribute name/value, or "" if attribute is empty
+		const char_t* name() const;
+		const char_t* value() const;
+
+		// Get attribute value, or the default value if attribute is empty
+		const char_t* as_string(const char_t* def = PUGIXML_TEXT("")) const;
+
+		// Get attribute value as a number, or the default value if conversion did not succeed or attribute is empty
+		int as_int(int def = 0) const;
+		unsigned int as_uint(unsigned int def = 0) const;
+		double as_double(double def = 0) const;
+		float as_float(float def = 0) const;
+
+	#ifdef PUGIXML_HAS_LONG_LONG
+		long long as_llong(long long def = 0) const;
+		unsigned long long as_ullong(unsigned long long def = 0) const;
+	#endif
+
+		// Get attribute value as bool (returns true if first character is in '1tTyY' set), or the default value if attribute is empty
+		bool as_bool(bool def = false) const;
+
+		// Set attribute name/value (returns false if attribute is empty or there is not enough memory)
+		bool set_name(const char_t* rhs);
+		bool set_value(const char_t* rhs);
+
+		// Set attribute value with type conversion (numbers are converted to strings, boolean is converted to "true"/"false")
+		bool set_value(int rhs);
+		bool set_value(unsigned int rhs);
+		bool set_value(long rhs);
+		bool set_value(unsigned long rhs);
+		bool set_value(double rhs);
+		bool set_value(float rhs);
+		bool set_value(bool rhs);
+
+	#ifdef PUGIXML_HAS_LONG_LONG
+		bool set_value(long long rhs);
+		bool set_value(unsigned long long rhs);
+	#endif
+
+		// Set attribute value (equivalent to set_value without error checking)
+		xml_attribute& operator=(const char_t* rhs);
+		xml_attribute& operator=(int rhs);
+		xml_attribute& operator=(unsigned int rhs);
+		xml_attribute& operator=(long rhs);
+		xml_attribute& operator=(unsigned long rhs);
+		xml_attribute& operator=(double rhs);
+		xml_attribute& operator=(float rhs);
+		xml_attribute& operator=(bool rhs);
+
+	#ifdef PUGIXML_HAS_LONG_LONG
+		xml_attribute& operator=(long long rhs);
+		xml_attribute& operator=(unsigned long long rhs);
+	#endif
+
+		// Get next/previous attribute in the attribute list of the parent node
+		xml_attribute next_attribute() const;
+		xml_attribute previous_attribute() const;
+
+		// Get hash value (unique for handles to the same object)
+		size_t hash_value() const;
+
+		// Get internal pointer
+		xml_attribute_struct* internal_object() const;
+	};
+
+#ifdef __BORLANDC__
+	// Borland C++ workaround
+	bool PUGIXML_FUNCTION operator&&(const xml_attribute& lhs, bool rhs);
+	bool PUGIXML_FUNCTION operator||(const xml_attribute& lhs, bool rhs);
+#endif
+
+	// A light-weight handle for manipulating nodes in DOM tree
+	class PUGIXML_CLASS xml_node
+	{
+		friend class xml_attribute_iterator;
+		friend class xml_node_iterator;
+		friend class xml_named_node_iterator;
+
+	protected:
+		xml_node_struct* _root;
+
+		typedef void (*unspecified_bool_type)(xml_node***);
+
+	public:
+		// Default constructor. Constructs an empty node.
+		xml_node();
+
+		// Constructs node from internal pointer
+		explicit xml_node(xml_node_struct* p);
+
+		// Safe bool conversion operator
+		operator unspecified_bool_type() const;
+
+		// Borland C++ workaround
+		bool operator!() const;
+
+		// Comparison operators (compares wrapped node pointers)
+		bool operator==(const xml_node& r) const;
+		bool operator!=(const xml_node& r) const;
+		bool operator<(const xml_node& r) const;
+		bool operator>(const xml_node& r) const;
+		bool operator<=(const xml_node& r) const;
+		bool operator>=(const xml_node& r) const;
+
+		// Check if node is empty.
+		bool empty() const;
+
+		// Get node type
+		xml_node_type type() const;
+
+		// Get node name, or "" if node is empty or it has no name
+		const char_t* name() const;
+
+		// Get node value, or "" if node is empty or it has no value
+		// Note: For <node>text</node> node.value() does not return "text"! Use child_value() or text() methods to access text inside nodes.
+		const char_t* value() const;
+
+		// Get attribute list
+		xml_attribute first_attribute() const;
+		xml_attribute last_attribute() const;
+
+		// Get children list
+		xml_node first_child() const;
+		xml_node last_child() const;
+
+		// Get next/previous sibling in the children list of the parent node
+		xml_node next_sibling() const;
+		xml_node previous_sibling() const;
+
+		// Get parent node
+		xml_node parent() const;
+
+		// Get root of DOM tree this node belongs to
+		xml_node root() const;
+
+		// Get text object for the current node
+		xml_text text() const;
+
+		// Get child, attribute or next/previous sibling with the specified name
+		xml_node child(const char_t* name) const;
+		xml_attribute attribute(const char_t* name) const;
+		xml_node next_sibling(const char_t* name) const;
+		xml_node previous_sibling(const char_t* name) const;
+
+		// Get attribute, starting the search from a hint (and updating hint so that searching for a sequence of attributes is fast)
+		xml_attribute attribute(const char_t* name, xml_attribute& hint) const;
+
+		// Get child value of current node; that is, value of the first child node of type PCDATA/CDATA
+		const char_t* child_value() const;
+
+		// Get child value of child with specified name. Equivalent to child(name).child_value().
+		const char_t* child_value(const char_t* name) const;
+
+		// Set node name/value (returns false if node is empty, there is not enough memory, or node can not have name/value)
+		bool set_name(const char_t* rhs);
+		bool set_value(const char_t* rhs);
+
+		// Add attribute with specified name. Returns added attribute, or empty attribute on errors.
+		xml_attribute append_attribute(const char_t* name);
+		xml_attribute prepend_attribute(const char_t* name);
+		xml_attribute insert_attribute_after(const char_t* name, const xml_attribute& attr);
+		xml_attribute insert_attribute_before(const char_t* name, const xml_attribute& attr);
+
+		// Add a copy of the specified attribute. Returns added attribute, or empty attribute on errors.
+		xml_attribute append_copy(const xml_attribute& proto);
+		xml_attribute prepend_copy(const xml_attribute& proto);
+		xml_attribute insert_copy_after(const xml_attribute& proto, const xml_attribute& attr);
+		xml_attribute insert_copy_before(const xml_attribute& proto, const xml_attribute& attr);
+
+		// Add child node with specified type. Returns added node, or empty node on errors.
+		xml_node append_child(xml_node_type type = node_element);
+		xml_node prepend_child(xml_node_type type = node_element);
+		xml_node insert_child_after(xml_node_type type, const xml_node& node);
+		xml_node insert_child_before(xml_node_type type, const xml_node& node);
+
+		// Add child element with specified name. Returns added node, or empty node on errors.
+		xml_node append_child(const char_t* name);
+		xml_node prepend_child(const char_t* name);
+		xml_node insert_child_after(const char_t* name, const xml_node& node);
+		xml_node insert_child_before(const char_t* name, const xml_node& node);
+
+		// Add a copy of the specified node as a child. Returns added node, or empty node on errors.
+		xml_node append_copy(const xml_node& proto);
+		xml_node prepend_copy(const xml_node& proto);
+		xml_node insert_copy_after(const xml_node& proto, const xml_node& node);
+		xml_node insert_copy_before(const xml_node& proto, const xml_node& node);
+
+		// Move the specified node to become a child of this node. Returns moved node, or empty node on errors.
+		xml_node append_move(const xml_node& moved);
+		xml_node prepend_move(const xml_node& moved);
+		xml_node insert_move_after(const xml_node& moved, const xml_node& node);
+		xml_node insert_move_before(const xml_node& moved, const xml_node& node);
+
+		// Remove specified attribute
+		bool remove_attribute(const xml_attribute& a);
+		bool remove_attribute(const char_t* name);
+
+		// Remove specified child
+		bool remove_child(const xml_node& n);
+		bool remove_child(const char_t* name);
+
+		// Parses buffer as an XML document fragment and appends all nodes as children of the current node.
+		// Copies/converts the buffer, so it may be deleted or changed after the function returns.
+		// Note: append_buffer allocates memory that has the lifetime of the owning document; removing the appended nodes does not immediately reclaim that memory.
+		xml_parse_result append_buffer(const void* contents, size_t size, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+
+		// Find attribute using predicate. Returns first attribute for which predicate returned true.
+		template <typename Predicate> xml_attribute find_attribute(Predicate pred) const
+		{
+			if (!_root) return xml_attribute();
+
+			for (xml_attribute attrib = first_attribute(); attrib; attrib = attrib.next_attribute())
+				if (pred(attrib))
+					return attrib;
+
+			return xml_attribute();
+		}
+
+		// Find child node using predicate. Returns first child for which predicate returned true.
+		template <typename Predicate> xml_node find_child(Predicate pred) const
+		{
+			if (!_root) return xml_node();
+
+			for (xml_node node = first_child(); node; node = node.next_sibling())
+				if (pred(node))
+					return node;
+
+			return xml_node();
+		}
+
+		// Find node from subtree using predicate. Returns first node from subtree (depth-first), for which predicate returned true.
+		template <typename Predicate> xml_node find_node(Predicate pred) const
+		{
+			if (!_root) return xml_node();
+
+			xml_node cur = first_child();
+
+			while (cur._root && cur._root != _root)
+			{
+				if (pred(cur)) return cur;
+
+				if (cur.first_child()) cur = cur.first_child();
+				else if (cur.next_sibling()) cur = cur.next_sibling();
+				else
+				{
+					while (!cur.next_sibling() && cur._root != _root) cur = cur.parent();
+
+					if (cur._root != _root) cur = cur.next_sibling();
+				}
+			}
+
+			return xml_node();
+		}
+
+		// Find child node by attribute name/value
+		xml_node find_child_by_attribute(const char_t* name, const char_t* attr_name, const char_t* attr_value) const;
+		xml_node find_child_by_attribute(const char_t* attr_name, const char_t* attr_value) const;
+
+	#ifndef PUGIXML_NO_STL
+		// Get the absolute node path from root as a text string.
+		string_t path(char_t delimiter = '/') const;
+	#endif
+
+		// Search for a node by path consisting of node names and . or .. elements.
+		xml_node first_element_by_path(const char_t* path, char_t delimiter = '/') const;
+
+		// Recursively traverse subtree with xml_tree_walker
+		bool traverse(xml_tree_walker& walker);
+
+	#ifndef PUGIXML_NO_XPATH
+		// Select single node by evaluating XPath query. Returns first node from the resulting node set.
+		xpath_node select_node(const char_t* query, xpath_variable_set* variables = 0) const;
+		xpath_node select_node(const xpath_query& query) const;
+
+		// Select node set by evaluating XPath query
+		xpath_node_set select_nodes(const char_t* query, xpath_variable_set* variables = 0) const;
+		xpath_node_set select_nodes(const xpath_query& query) const;
+
+		// (deprecated: use select_node instead) Select single node by evaluating XPath query.
+		xpath_node select_single_node(const char_t* query, xpath_variable_set* variables = 0) const;
+		xpath_node select_single_node(const xpath_query& query) const;
+
+	#endif
+
+		// Print subtree using a writer object
+		void print(xml_writer& writer, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, xml_encoding encoding = encoding_auto, unsigned int depth = 0) const;
+
+	#ifndef PUGIXML_NO_STL
+		// Print subtree to stream
+		void print(std::basic_ostream<char, std::char_traits<char> >& os, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, xml_encoding encoding = encoding_auto, unsigned int depth = 0) const;
+		void print(std::basic_ostream<wchar_t, std::char_traits<wchar_t> >& os, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, unsigned int depth = 0) const;
+	#endif
+
+		// Child nodes iterators
+		typedef xml_node_iterator iterator;
+
+		iterator begin() const;
+		iterator end() const;
+
+		// Attribute iterators
+		typedef xml_attribute_iterator attribute_iterator;
+
+		attribute_iterator attributes_begin() const;
+		attribute_iterator attributes_end() const;
+
+		// Range-based for support
+		xml_object_range<xml_node_iterator> children() const;
+		xml_object_range<xml_named_node_iterator> children(const char_t* name) const;
+		xml_object_range<xml_attribute_iterator> attributes() const;
+
+		// Get node offset in parsed file/string (in char_t units) for debugging purposes
+		ptrdiff_t offset_debug() const;
+
+		// Get hash value (unique for handles to the same object)
+		size_t hash_value() const;
+
+		// Get internal pointer
+		xml_node_struct* internal_object() const;
+	};
+
+#ifdef __BORLANDC__
+	// Borland C++ workaround
+	bool PUGIXML_FUNCTION operator&&(const xml_node& lhs, bool rhs);
+	bool PUGIXML_FUNCTION operator||(const xml_node& lhs, bool rhs);
+#endif
+
+	// A helper for working with text inside PCDATA nodes
+	class PUGIXML_CLASS xml_text
+	{
+		friend class xml_node;
+
+		xml_node_struct* _root;
+
+		typedef void (*unspecified_bool_type)(xml_text***);
+
+		explicit xml_text(xml_node_struct* root);
+
+		xml_node_struct* _data_new();
+		xml_node_struct* _data() const;
+
+	public:
+		// Default constructor. Constructs an empty object.
+		xml_text();
+
+		// Safe bool conversion operator
+		operator unspecified_bool_type() const;
+
+		// Borland C++ workaround
+		bool operator!() const;
+
+		// Check if text object is empty
+		bool empty() const;
+
+		// Get text, or "" if object is empty
+		const char_t* get() const;
+
+		// Get text, or the default value if object is empty
+		const char_t* as_string(const char_t* def = PUGIXML_TEXT("")) const;
+
+		// Get text as a number, or the default value if conversion did not succeed or object is empty
+		int as_int(int def = 0) const;
+		unsigned int as_uint(unsigned int def = 0) const;
+		double as_double(double def = 0) const;
+		float as_float(float def = 0) const;
+
+	#ifdef PUGIXML_HAS_LONG_LONG
+		long long as_llong(long long def = 0) const;
+		unsigned long long as_ullong(unsigned long long def = 0) const;
+	#endif
+
+		// Get text as bool (returns true if first character is in '1tTyY' set), or the default value if object is empty
+		bool as_bool(bool def = false) const;
+
+		// Set text (returns false if object is empty or there is not enough memory)
+		bool set(const char_t* rhs);
+
+		// Set text with type conversion (numbers are converted to strings, boolean is converted to "true"/"false")
+		bool set(int rhs);
+		bool set(unsigned int rhs);
+		bool set(long rhs);
+		bool set(unsigned long rhs);
+		bool set(double rhs);
+		bool set(float rhs);
+		bool set(bool rhs);
+
+	#ifdef PUGIXML_HAS_LONG_LONG
+		bool set(long long rhs);
+		bool set(unsigned long long rhs);
+	#endif
+
+		// Set text (equivalent to set without error checking)
+		xml_text& operator=(const char_t* rhs);
+		xml_text& operator=(int rhs);
+		xml_text& operator=(unsigned int rhs);
+		xml_text& operator=(long rhs);
+		xml_text& operator=(unsigned long rhs);
+		xml_text& operator=(double rhs);
+		xml_text& operator=(float rhs);
+		xml_text& operator=(bool rhs);
+
+	#ifdef PUGIXML_HAS_LONG_LONG
+		xml_text& operator=(long long rhs);
+		xml_text& operator=(unsigned long long rhs);
+	#endif
+
+		// Get the data node (node_pcdata or node_cdata) for this object
+		xml_node data() const;
+	};
+
+#ifdef __BORLANDC__
+	// Borland C++ workaround
+	bool PUGIXML_FUNCTION operator&&(const xml_text& lhs, bool rhs);
+	bool PUGIXML_FUNCTION operator||(const xml_text& lhs, bool rhs);
+#endif
+
+	// Child node iterator (a bidirectional iterator over a collection of xml_node)
+	class PUGIXML_CLASS xml_node_iterator
+	{
+		friend class xml_node;
+
+	private:
+		mutable xml_node _wrap;
+		xml_node _parent;
+
+		xml_node_iterator(xml_node_struct* ref, xml_node_struct* parent);
+
+	public:
+		// Iterator traits
+		typedef ptrdiff_t difference_type;
+		typedef xml_node value_type;
+		typedef xml_node* pointer;
+		typedef xml_node& reference;
+
+	#ifndef PUGIXML_NO_STL
+		typedef std::bidirectional_iterator_tag iterator_category;
+	#endif
+
+		// Default constructor
+		xml_node_iterator();
+
+		// Construct an iterator which points to the specified node
+		xml_node_iterator(const xml_node& node);
+
+		// Iterator operators
+		bool operator==(const xml_node_iterator& rhs) const;
+		bool operator!=(const xml_node_iterator& rhs) const;
+
+		xml_node& operator*() const;
+		xml_node* operator->() const;
+
+		const xml_node_iterator& operator++();
+		xml_node_iterator operator++(int);
+
+		const xml_node_iterator& operator--();
+		xml_node_iterator operator--(int);
+	};
+
+	// Attribute iterator (a bidirectional iterator over a collection of xml_attribute)
+	class PUGIXML_CLASS xml_attribute_iterator
+	{
+		friend class xml_node;
+
+	private:
+		mutable xml_attribute _wrap;
+		xml_node _parent;
+
+		xml_attribute_iterator(xml_attribute_struct* ref, xml_node_struct* parent);
+
+	public:
+		// Iterator traits
+		typedef ptrdiff_t difference_type;
+		typedef xml_attribute value_type;
+		typedef xml_attribute* pointer;
+		typedef xml_attribute& reference;
+
+	#ifndef PUGIXML_NO_STL
+		typedef std::bidirectional_iterator_tag iterator_category;
+	#endif
+
+		// Default constructor
+		xml_attribute_iterator();
+
+		// Construct an iterator which points to the specified attribute
+		xml_attribute_iterator(const xml_attribute& attr, const xml_node& parent);
+
+		// Iterator operators
+		bool operator==(const xml_attribute_iterator& rhs) const;
+		bool operator!=(const xml_attribute_iterator& rhs) const;
+
+		xml_attribute& operator*() const;
+		xml_attribute* operator->() const;
+
+		const xml_attribute_iterator& operator++();
+		xml_attribute_iterator operator++(int);
+
+		const xml_attribute_iterator& operator--();
+		xml_attribute_iterator operator--(int);
+	};
+
+	// Named node range helper
+	class PUGIXML_CLASS xml_named_node_iterator
+	{
+		friend class xml_node;
+
+	public:
+		// Iterator traits
+		typedef ptrdiff_t difference_type;
+		typedef xml_node value_type;
+		typedef xml_node* pointer;
+		typedef xml_node& reference;
+
+	#ifndef PUGIXML_NO_STL
+		typedef std::bidirectional_iterator_tag iterator_category;
+	#endif
+
+		// Default constructor
+		xml_named_node_iterator();
+
+		// Construct an iterator which points to the specified node
+		xml_named_node_iterator(const xml_node& node, const char_t* name);
+
+		// Iterator operators
+		bool operator==(const xml_named_node_iterator& rhs) const;
+		bool operator!=(const xml_named_node_iterator& rhs) const;
+
+		xml_node& operator*() const;
+		xml_node* operator->() const;
+
+		const xml_named_node_iterator& operator++();
+		xml_named_node_iterator operator++(int);
+
+		const xml_named_node_iterator& operator--();
+		xml_named_node_iterator operator--(int);
+
+	private:
+		mutable xml_node _wrap;
+		xml_node _parent;
+		const char_t* _name;
+
+		xml_named_node_iterator(xml_node_struct* ref, xml_node_struct* parent, const char_t* name);
+	};
+
+	// Abstract tree walker class (see xml_node::traverse)
+	class PUGIXML_CLASS xml_tree_walker
+	{
+		friend class xml_node;
+
+	private:
+		int _depth;
+
+	protected:
+		// Get current traversal depth
+		int depth() const;
+
+	public:
+		xml_tree_walker();
+		virtual ~xml_tree_walker();
+
+		// Callback that is called when traversal begins
+		virtual bool begin(xml_node& node);
+
+		// Callback that is called for each node traversed
+		virtual bool for_each(xml_node& node) = 0;
+
+		// Callback that is called when traversal ends
+		virtual bool end(xml_node& node);
+	};
+
+	// Parsing status, returned as part of xml_parse_result object
+	enum xml_parse_status
+	{
+		status_ok = 0,				// No error
+
+		status_file_not_found,		// File was not found during load_file()
+		status_io_error,			// Error reading from file/stream
+		status_out_of_memory,		// Could not allocate memory
+		status_internal_error,		// Internal error occurred
+
+		status_unrecognized_tag,	// Parser could not determine tag type
+
+		status_bad_pi,				// Parsing error occurred while parsing document declaration/processing instruction
+		status_bad_comment,			// Parsing error occurred while parsing comment
+		status_bad_cdata,			// Parsing error occurred while parsing CDATA section
+		status_bad_doctype,			// Parsing error occurred while parsing document type declaration
+		status_bad_pcdata,			// Parsing error occurred while parsing PCDATA section
+		status_bad_start_element,	// Parsing error occurred while parsing start element tag
+		status_bad_attribute,		// Parsing error occurred while parsing element attribute
+		status_bad_end_element,		// Parsing error occurred while parsing end element tag
+		status_end_element_mismatch,// There was a mismatch of start-end tags (closing tag had incorrect name, some tag was not closed or there was an excessive closing tag)
+
+		status_append_invalid_root,	// Unable to append nodes since root type is not node_element or node_document (exclusive to xml_node::append_buffer)
+
+		status_no_document_element	// Parsing resulted in a document without element nodes
+	};
+
+	// Parsing result
+	struct PUGIXML_CLASS xml_parse_result
+	{
+		// Parsing status (see xml_parse_status)
+		xml_parse_status status;
+
+		// Last parsed offset (in char_t units from start of input data)
+		ptrdiff_t offset;
+
+		// Source document encoding
+		xml_encoding encoding;
+
+		// Default constructor, initializes object to failed state
+		xml_parse_result();
+
+		// Cast to bool operator
+		operator bool() const;
+
+		// Get error description
+		const char* description() const;
+	};
+
+	// Document class (DOM tree root)
+	class PUGIXML_CLASS xml_document: public xml_node
+	{
+	private:
+		char_t* _buffer;
+
+		char _memory[192];
+
+		// Non-copyable semantics
+		xml_document(const xml_document&);
+		xml_document& operator=(const xml_document&);
+
+		void _create();
+		void _destroy();
+
+	public:
+		// Default constructor, makes empty document
+		xml_document();
+
+		// Destructor, invalidates all node/attribute handles to this document
+		~xml_document();
+
+		// Removes all nodes, leaving the empty document
+		void reset();
+
+		// Removes all nodes, then copies the entire contents of the specified document
+		void reset(const xml_document& proto);
+
+	#ifndef PUGIXML_NO_STL
+		// Load document from stream.
+		xml_parse_result load(std::basic_istream<char, std::char_traits<char> >& stream, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+		xml_parse_result load(std::basic_istream<wchar_t, std::char_traits<wchar_t> >& stream, unsigned int options = parse_default);
+	#endif
+
+		// (deprecated: use load_string instead) Load document from zero-terminated string. No encoding conversions are applied.
+		xml_parse_result load(const char_t* contents, unsigned int options = parse_default);
+
+		// Load document from zero-terminated string. No encoding conversions are applied.
+		xml_parse_result load_string(const char_t* contents, unsigned int options = parse_default);
+
+		// Load document from file
+		xml_parse_result load_file(const char* path, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+		xml_parse_result load_file(const wchar_t* path, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+
+		// Load document from buffer. Copies/converts the buffer, so it may be deleted or changed after the function returns.
+		xml_parse_result load_buffer(const void* contents, size_t size, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+
+		// Load document from buffer, using the buffer for in-place parsing (the buffer is modified and used for storage of document data).
+		// You should ensure that buffer data will persist throughout the document's lifetime, and free the buffer memory manually once document is destroyed.
+		xml_parse_result load_buffer_inplace(void* contents, size_t size, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+
+		// Load document from buffer, using the buffer for in-place parsing (the buffer is modified and used for storage of document data).
+		// You should allocate the buffer with pugixml allocation function; document will free the buffer when it is no longer needed (you can't use it anymore).
+		xml_parse_result load_buffer_inplace_own(void* contents, size_t size, unsigned int options = parse_default, xml_encoding encoding = encoding_auto);
+
+		// Save XML document to writer (semantics is slightly different from xml_node::print, see documentation for details).
+		void save(xml_writer& writer, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, xml_encoding encoding = encoding_auto) const;
+
+	#ifndef PUGIXML_NO_STL
+		// Save XML document to stream (semantics is slightly different from xml_node::print, see documentation for details).
+		void save(std::basic_ostream<char, std::char_traits<char> >& stream, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, xml_encoding encoding = encoding_auto) const;
+		void save(std::basic_ostream<wchar_t, std::char_traits<wchar_t> >& stream, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default) const;
+	#endif
+
+		// Save XML to file
+		bool save_file(const char* path, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, xml_encoding encoding = encoding_auto) const;
+		bool save_file(const wchar_t* path, const char_t* indent = PUGIXML_TEXT("\t"), unsigned int flags = format_default, xml_encoding encoding = encoding_auto) const;
+
+		// Get document element
+		xml_node document_element() const;
+	};
+
+#ifndef PUGIXML_NO_XPATH
+	// XPath query return type
+	enum xpath_value_type
+	{
+		xpath_type_none,	  // Unknown type (query failed to compile)
+		xpath_type_node_set,  // Node set (xpath_node_set)
+		xpath_type_number,	  // Number
+		xpath_type_string,	  // String
+		xpath_type_boolean	  // Boolean
+	};
+
+	// XPath parsing result
+	struct PUGIXML_CLASS xpath_parse_result
+	{
+		// Error message (0 if no error)
+		const char* error;
+
+		// Last parsed offset (in char_t units from string start)
+		ptrdiff_t offset;
+
+		// Default constructor, initializes object to failed state
+		xpath_parse_result();
+
+		// Cast to bool operator
+		operator bool() const;
+
+		// Get error description
+		const char* description() const;
+	};
+
+	// A single XPath variable
+	class PUGIXML_CLASS xpath_variable
+	{
+		friend class xpath_variable_set;
+
+	protected:
+		xpath_value_type _type;
+		xpath_variable* _next;
+
+		xpath_variable(xpath_value_type type);
+
+		// Non-copyable semantics
+		xpath_variable(const xpath_variable&);
+		xpath_variable& operator=(const xpath_variable&);
+
+	public:
+		// Get variable name
+		const char_t* name() const;
+
+		// Get variable type
+		xpath_value_type type() const;
+
+		// Get variable value; no type conversion is performed, default value (false, NaN, empty string, empty node set) is returned on type mismatch error
+		bool get_boolean() const;
+		double get_number() const;
+		const char_t* get_string() const;
+		const xpath_node_set& get_node_set() const;
+
+		// Set variable value; no type conversion is performed, false is returned on type mismatch error
+		bool set(bool value);
+		bool set(double value);
+		bool set(const char_t* value);
+		bool set(const xpath_node_set& value);
+	};
+
+	// A set of XPath variables
+	class PUGIXML_CLASS xpath_variable_set
+	{
+	private:
+		xpath_variable* _data[64];
+
+		void _assign(const xpath_variable_set& rhs);
+		void _swap(xpath_variable_set& rhs);
+
+		xpath_variable* _find(const char_t* name) const;
+
+		static bool _clone(xpath_variable* var, xpath_variable** out_result);
+		static void _destroy(xpath_variable* var);
+
+	public:
+		// Default constructor/destructor
+		xpath_variable_set();
+		~xpath_variable_set();
+
+		// Copy constructor/assignment operator
+		xpath_variable_set(const xpath_variable_set& rhs);
+		xpath_variable_set& operator=(const xpath_variable_set& rhs);
+
+	#ifdef PUGIXML_HAS_MOVE
+		// Move semantics support
+		xpath_variable_set(xpath_variable_set&& rhs);
+		xpath_variable_set& operator=(xpath_variable_set&& rhs);
+	#endif
+
+		// Add a new variable or get the existing one, if the types match
+		xpath_variable* add(const char_t* name, xpath_value_type type);
+
+		// Set value of an existing variable; no type conversion is performed, false is returned if there is no such variable or if types mismatch
+		bool set(const char_t* name, bool value);
+		bool set(const char_t* name, double value);
+		bool set(const char_t* name, const char_t* value);
+		bool set(const char_t* name, const xpath_node_set& value);
+
+		// Get existing variable by name
+		xpath_variable* get(const char_t* name);
+		const xpath_variable* get(const char_t* name) const;
+	};
+
+	// A compiled XPath query object
+	class PUGIXML_CLASS xpath_query
+	{
+	private:
+		void* _impl;
+		xpath_parse_result _result;
+
+		typedef void (*unspecified_bool_type)(xpath_query***);
+
+		// Non-copyable semantics
+		xpath_query(const xpath_query&);
+		xpath_query& operator=(const xpath_query&);
+
+	public:
+		// Construct a compiled object from XPath expression.
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on compilation errors.
+		explicit xpath_query(const char_t* query, xpath_variable_set* variables = 0);
+
+		// Constructor
+		xpath_query();
+
+		// Destructor
+		~xpath_query();
+
+	#ifdef PUGIXML_HAS_MOVE
+		// Move semantics support
+		xpath_query(xpath_query&& rhs);
+		xpath_query& operator=(xpath_query&& rhs);
+	#endif
+
+		// Get query expression return type
+		xpath_value_type return_type() const;
+
+		// Evaluate expression as boolean value in the specified context; performs type conversion if necessary.
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws std::bad_alloc on out of memory errors.
+		bool evaluate_boolean(const xpath_node& n) const;
+
+		// Evaluate expression as double value in the specified context; performs type conversion if necessary.
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws std::bad_alloc on out of memory errors.
+		double evaluate_number(const xpath_node& n) const;
+
+	#ifndef PUGIXML_NO_STL
+		// Evaluate expression as string value in the specified context; performs type conversion if necessary.
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws std::bad_alloc on out of memory errors.
+		string_t evaluate_string(const xpath_node& n) const;
+	#endif
+
+		// Evaluate expression as string value in the specified context; performs type conversion if necessary.
+		// At most capacity characters are written to the destination buffer, full result size is returned (includes terminating zero).
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws std::bad_alloc on out of memory errors.
+		// If PUGIXML_NO_EXCEPTIONS is defined, returns empty  set instead.
+		size_t evaluate_string(char_t* buffer, size_t capacity, const xpath_node& n) const;
+
+		// Evaluate expression as node set in the specified context.
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on type mismatch and std::bad_alloc on out of memory errors.
+		// If PUGIXML_NO_EXCEPTIONS is defined, returns empty node set instead.
+		xpath_node_set evaluate_node_set(const xpath_node& n) const;
+
+		// Evaluate expression as node set in the specified context.
+		// Return first node in document order, or empty node if node set is empty.
+		// If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on type mismatch and std::bad_alloc on out of memory errors.
+		// If PUGIXML_NO_EXCEPTIONS is defined, returns empty node instead.
+		xpath_node evaluate_node(const xpath_node& n) const;
+
+		// Get parsing result (used to get compilation errors in PUGIXML_NO_EXCEPTIONS mode)
+		const xpath_parse_result& result() const;
+
+		// Safe bool conversion operator
+		operator unspecified_bool_type() const;
+
+		// Borland C++ workaround
+		bool operator!() const;
+	};
+
+	#ifndef PUGIXML_NO_EXCEPTIONS
+	// XPath exception class
+	class PUGIXML_CLASS xpath_exception: public std::exception
+	{
+	private:
+		xpath_parse_result _result;
+
+	public:
+		// Construct exception from parse result
+		explicit xpath_exception(const xpath_parse_result& result);
+
+		// Get error message
+		virtual const char* what() const throw() PUGIXML_OVERRIDE;
+
+		// Get parse result
+		const xpath_parse_result& result() const;
+	};
+	#endif
+
+	// XPath node class (either xml_node or xml_attribute)
+	class PUGIXML_CLASS xpath_node
+	{
+	private:
+		xml_node _node;
+		xml_attribute _attribute;
+
+		typedef void (*unspecified_bool_type)(xpath_node***);
+
+	public:
+		// Default constructor; constructs empty XPath node
+		xpath_node();
+
+		// Construct XPath node from XML node/attribute
+		xpath_node(const xml_node& node);
+		xpath_node(const xml_attribute& attribute, const xml_node& parent);
+
+		// Get node/attribute, if any
+		xml_node node() const;
+		xml_attribute attribute() const;
+
+		// Get parent of contained node/attribute
+		xml_node parent() const;
+
+		// Safe bool conversion operator
+		operator unspecified_bool_type() const;
+
+		// Borland C++ workaround
+		bool operator!() const;
+
+		// Comparison operators
+		bool operator==(const xpath_node& n) const;
+		bool operator!=(const xpath_node& n) const;
+	};
+
+#ifdef __BORLANDC__
+	// Borland C++ workaround
+	bool PUGIXML_FUNCTION operator&&(const xpath_node& lhs, bool rhs);
+	bool PUGIXML_FUNCTION operator||(const xpath_node& lhs, bool rhs);
+#endif
+
+	// A fixed-size collection of XPath nodes
+	class PUGIXML_CLASS xpath_node_set
+	{
+	public:
+		// Collection type
+		enum type_t
+		{
+			type_unsorted,			// Not ordered
+			type_sorted,			// Sorted by document order (ascending)
+			type_sorted_reverse		// Sorted by document order (descending)
+		};
+
+		// Constant iterator type
+		typedef const xpath_node* const_iterator;
+
+		// We define non-constant iterator to be the same as constant iterator so that various generic algorithms (i.e. boost foreach) work
+		typedef const xpath_node* iterator;
+
+		// Default constructor. Constructs empty set.
+		xpath_node_set();
+
+		// Constructs a set from iterator range; data is not checked for duplicates and is not sorted according to provided type, so be careful
+		xpath_node_set(const_iterator begin, const_iterator end, type_t type = type_unsorted);
+
+		// Destructor
+		~xpath_node_set();
+
+		// Copy constructor/assignment operator
+		xpath_node_set(const xpath_node_set& ns);
+		xpath_node_set& operator=(const xpath_node_set& ns);
+
+	#ifdef PUGIXML_HAS_MOVE
+		// Move semantics support
+		xpath_node_set(xpath_node_set&& rhs);
+		xpath_node_set& operator=(xpath_node_set&& rhs);
+	#endif
+
+		// Get collection type
+		type_t type() const;
+
+		// Get collection size
+		size_t size() const;
+
+		// Indexing operator
+		const xpath_node& operator[](size_t index) const;
+
+		// Collection iterators
+		const_iterator begin() const;
+		const_iterator end() const;
+
+		// Sort the collection in ascending/descending order by document order
+		void sort(bool reverse = false);
+
+		// Get first node in the collection by document order
+		xpath_node first() const;
+
+		// Check if collection is empty
+		bool empty() const;
+
+	private:
+		type_t _type;
+
+		xpath_node _storage;
+
+		xpath_node* _begin;
+		xpath_node* _end;
+
+		void _assign(const_iterator begin, const_iterator end, type_t type);
+		void _move(xpath_node_set& rhs);
+	};
+#endif
+
+#ifndef PUGIXML_NO_STL
+	// Convert wide string to UTF8
+	std::basic_string<char, std::char_traits<char>, std::allocator<char> > PUGIXML_FUNCTION as_utf8(const wchar_t* str);
+	std::basic_string<char, std::char_traits<char>, std::allocator<char> > PUGIXML_FUNCTION as_utf8(const std::basic_string<wchar_t, std::char_traits<wchar_t>, std::allocator<wchar_t> >& str);
+
+	// Convert UTF8 to wide string
+	std::basic_string<wchar_t, std::char_traits<wchar_t>, std::allocator<wchar_t> > PUGIXML_FUNCTION as_wide(const char* str);
+	std::basic_string<wchar_t, std::char_traits<wchar_t>, std::allocator<wchar_t> > PUGIXML_FUNCTION as_wide(const std::basic_string<char, std::char_traits<char>, std::allocator<char> >& str);
+#endif
+
+	// Memory allocation function interface; returns pointer to allocated memory or NULL on failure
+	typedef void* (*allocation_function)(size_t size);
+
+	// Memory deallocation function interface
+	typedef void (*deallocation_function)(void* ptr);
+
+	// Override default memory management functions. All subsequent allocations/deallocations will be performed via supplied functions.
+	void PUGIXML_FUNCTION set_memory_management_functions(allocation_function allocate, deallocation_function deallocate);
+
+	// Get current memory management functions
+	allocation_function PUGIXML_FUNCTION get_memory_allocation_function();
+	deallocation_function PUGIXML_FUNCTION get_memory_deallocation_function();
+}
+
+#if !defined(PUGIXML_NO_STL) && (defined(_MSC_VER) || defined(__ICC))
+namespace std
+{
+	// Workarounds for (non-standard) iterator category detection for older versions (MSVC7/IC8 and earlier)
+	std::bidirectional_iterator_tag PUGIXML_FUNCTION _Iter_cat(const pugi::xml_node_iterator&);
+	std::bidirectional_iterator_tag PUGIXML_FUNCTION _Iter_cat(const pugi::xml_attribute_iterator&);
+	std::bidirectional_iterator_tag PUGIXML_FUNCTION _Iter_cat(const pugi::xml_named_node_iterator&);
+}
+#endif
+
+#if !defined(PUGIXML_NO_STL) && defined(__SUNPRO_CC)
+namespace std
+{
+	// Workarounds for (non-standard) iterator category detection
+	std::bidirectional_iterator_tag PUGIXML_FUNCTION __iterator_category(const pugi::xml_node_iterator&);
+	std::bidirectional_iterator_tag PUGIXML_FUNCTION __iterator_category(const pugi::xml_attribute_iterator&);
+	std::bidirectional_iterator_tag PUGIXML_FUNCTION __iterator_category(const pugi::xml_named_node_iterator&);
+}
+#endif
+
+#endif
+
+// Make sure implementation is included in header-only mode
+// Use macro expansion in #include to work around QMake (QTBUG-11923)
+#if defined(PUGIXML_HEADER_ONLY) && !defined(PUGIXML_SOURCE)
+#	define PUGIXML_SOURCE "pugixml.cpp"
+#	include PUGIXML_SOURCE
+#endif
+
+/**
+ * Copyright (c) 2006-2016 Arseny Kapoulkine
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/src/ErrCodeStr.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/src/ErrCodeStr.cpp
new file mode 100644
index 000000000..207114d13
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/src/ErrCodeStr.cpp
@@ -0,0 +1,13 @@
+#include "pugixml.hpp"
+#include "ErrCodeStr.hpp"
+
+
+void ErrCodeStr::load(char* filename) {
+	def_document.load_file(filename);
+	definitions = def_document.child("definitions");
+}
+
+char* ErrCodeStr::lookup(char errCode[]) {
+	pugi::xml_node definition = definitions.find_child_by_attribute("key", errCode);
+	return (char*)definition.child_value();
+}
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/src/pugixml.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/src/pugixml.cpp
new file mode 100644
index 000000000..cac51a534
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/LibXML/src/pugixml.cpp
@@ -0,0 +1,12622 @@
+/**
+ * pugixml parser - version 1.8
+ * --------------------------------------------------------
+ * Copyright (C) 2006-2016, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com)
+ * Report bugs and download new versions at http://pugixml.org/
+ *
+ * This library is distributed under the MIT License. See notice at the end
+ * of this file.
+ *
+ * This work is based on the pugxml parser, which is:
+ * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net)
+ */
+
+#ifndef SOURCE_PUGIXML_CPP
+#define SOURCE_PUGIXML_CPP
+
+#include "pugixml.hpp"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <limits.h>
+
+#ifdef PUGIXML_WCHAR_MODE
+#	include <wchar.h>
+#endif
+
+#ifndef PUGIXML_NO_XPATH
+#	include <math.h>
+#	include <float.h>
+#	ifdef PUGIXML_NO_EXCEPTIONS
+#		include <setjmp.h>
+#	endif
+#endif
+
+#ifndef PUGIXML_NO_STL
+#	include <istream>
+#	include <ostream>
+#	include <string>
+#endif
+
+// For placement new
+#include <new>
+
+#ifdef _MSC_VER
+#	pragma warning(push)
+#	pragma warning(disable: 4127) // conditional expression is constant
+#	pragma warning(disable: 4324) // structure was padded due to __declspec(align())
+#	pragma warning(disable: 4611) // interaction between '_setjmp' and C++ object destruction is non-portable
+#	pragma warning(disable: 4702) // unreachable code
+#	pragma warning(disable: 4996) // this function or variable may be unsafe
+#	pragma warning(disable: 4793) // function compiled as native: presence of '_setjmp' makes a function unmanaged
+#endif
+
+#ifdef __INTEL_COMPILER
+#	pragma warning(disable: 177) // function was declared but never referenced
+#	pragma warning(disable: 279) // controlling expression is constant
+#	pragma warning(disable: 1478 1786) // function was declared "deprecated"
+#	pragma warning(disable: 1684) // conversion from pointer to same-sized integral type
+#endif
+
+#if defined(__BORLANDC__) && defined(PUGIXML_HEADER_ONLY)
+#	pragma warn -8080 // symbol is declared but never used; disabling this inside push/pop bracket does not make the warning go away
+#endif
+
+#ifdef __BORLANDC__
+#	pragma option push
+#	pragma warn -8008 // condition is always false
+#	pragma warn -8066 // unreachable code
+#endif
+
+#ifdef __SNC__
+// Using diag_push/diag_pop does not disable the warnings inside templates due to a compiler bug
+#	pragma diag_suppress=178 // function was declared but never referenced
+#	pragma diag_suppress=237 // controlling expression is constant
+#endif
+
+// Inlining controls
+#if defined(_MSC_VER) && _MSC_VER >= 1300
+#	define PUGI__NO_INLINE __declspec(noinline)
+#elif defined(__GNUC__)
+#	define PUGI__NO_INLINE __attribute__((noinline))
+#else
+#	define PUGI__NO_INLINE
+#endif
+
+// Branch weight controls
+#if defined(__GNUC__)
+#	define PUGI__UNLIKELY(cond) __builtin_expect(cond, 0)
+#else
+#	define PUGI__UNLIKELY(cond) (cond)
+#endif
+
+// Simple static assertion
+#define PUGI__STATIC_ASSERT(cond) { static const char condition_failed[(cond) ? 1 : -1] = {0}; (void)condition_failed[0]; }
+
+// Digital Mars C++ bug workaround for passing char loaded from memory via stack
+#ifdef __DMC__
+#	define PUGI__DMC_VOLATILE volatile
+#else
+#	define PUGI__DMC_VOLATILE
+#endif
+
+// Borland C++ bug workaround for not defining ::memcpy depending on header include order (can't always use std::memcpy because some compilers don't have it at all)
+#if defined(__BORLANDC__) && !defined(__MEM_H_USING_LIST)
+using std::memcpy;
+using std::memmove;
+using std::memset;
+#endif
+
+// Some MinGW versions have headers that erroneously omit LLONG_MIN/LLONG_MAX/ULLONG_MAX definitions in strict ANSI mode
+#if defined(PUGIXML_HAS_LONG_LONG) && defined(__MINGW32__) && defined(__STRICT_ANSI__) && !defined(LLONG_MAX) && !defined(LLONG_MIN) && !defined(ULLONG_MAX)
+#	define LLONG_MAX 9223372036854775807LL
+#	define LLONG_MIN (-LLONG_MAX-1)
+#	define ULLONG_MAX (2ULL*LLONG_MAX+1)
+#endif
+
+// In some environments MSVC is a compiler but the CRT lacks certain MSVC-specific features
+#if defined(_MSC_VER) && !defined(__S3E__)
+#	define PUGI__MSVC_CRT_VERSION _MSC_VER
+#endif
+
+#ifdef PUGIXML_HEADER_ONLY
+#	define PUGI__NS_BEGIN namespace pugi { namespace impl {
+#	define PUGI__NS_END } }
+#	define PUGI__FN inline
+#	define PUGI__FN_NO_INLINE inline
+#else
+#	if defined(_MSC_VER) && _MSC_VER < 1300 // MSVC6 seems to have an amusing bug with anonymous namespaces inside namespaces
+#		define PUGI__NS_BEGIN namespace pugi { namespace impl {
+#		define PUGI__NS_END } }
+#	else
+#		define PUGI__NS_BEGIN namespace pugi { namespace impl { namespace {
+#		define PUGI__NS_END } } }
+#	endif
+#	define PUGI__FN
+#	define PUGI__FN_NO_INLINE PUGI__NO_INLINE
+#endif
+
+// uintptr_t
+#if (defined(_MSC_VER) && _MSC_VER < 1600) || (defined(__BORLANDC__) && __BORLANDC__ < 0x561)
+namespace pugi
+{
+#	ifndef _UINTPTR_T_DEFINED
+	typedef size_t uintptr_t;
+#	endif
+
+	typedef unsigned __int8 uint8_t;
+	typedef unsigned __int16 uint16_t;
+	typedef unsigned __int32 uint32_t;
+}
+#else
+#	include <stdint.h>
+#endif
+
+// Memory allocation
+PUGI__NS_BEGIN
+	PUGI__FN void* default_allocate(size_t size)
+	{
+		return malloc(size);
+	}
+
+	PUGI__FN void default_deallocate(void* ptr)
+	{
+		free(ptr);
+	}
+
+	template <typename T>
+	struct xml_memory_management_function_storage
+	{
+		static allocation_function allocate;
+		static deallocation_function deallocate;
+	};
+
+	// Global allocation functions are stored in class statics so that in header mode linker deduplicates them
+	// Without a template<> we'll get multiple definitions of the same static
+	template <typename T> allocation_function xml_memory_management_function_storage<T>::allocate = default_allocate;
+	template <typename T> deallocation_function xml_memory_management_function_storage<T>::deallocate = default_deallocate;
+
+	typedef xml_memory_management_function_storage<int> xml_memory;
+PUGI__NS_END
+
+// String utilities
+PUGI__NS_BEGIN
+	// Get string length
+	PUGI__FN size_t strlength(const char_t* s)
+	{
+		assert(s);
+
+	#ifdef PUGIXML_WCHAR_MODE
+		return wcslen(s);
+	#else
+		return strlen(s);
+	#endif
+	}
+
+	// Compare two strings
+	PUGI__FN bool strequal(const char_t* src, const char_t* dst)
+	{
+		assert(src && dst);
+
+	#ifdef PUGIXML_WCHAR_MODE
+		return wcscmp(src, dst) == 0;
+	#else
+		return strcmp(src, dst) == 0;
+	#endif
+	}
+
+	// Compare lhs with [rhs_begin, rhs_end)
+	PUGI__FN bool strequalrange(const char_t* lhs, const char_t* rhs, size_t count)
+	{
+		for (size_t i = 0; i < count; ++i)
+			if (lhs[i] != rhs[i])
+				return false;
+
+		return lhs[count] == 0;
+	}
+
+	// Get length of wide string, even if CRT lacks wide character support
+	PUGI__FN size_t strlength_wide(const wchar_t* s)
+	{
+		assert(s);
+
+	#ifdef PUGIXML_WCHAR_MODE
+		return wcslen(s);
+	#else
+		const wchar_t* end = s;
+		while (*end) end++;
+		return static_cast<size_t>(end - s);
+	#endif
+	}
+PUGI__NS_END
+
+// auto_ptr-like object for exception recovery
+PUGI__NS_BEGIN
+	template <typename T> struct auto_deleter
+	{
+		typedef void (*D)(T*);
+
+		T* data;
+		D deleter;
+
+		auto_deleter(T* data_, D deleter_): data(data_), deleter(deleter_)
+		{
+		}
+
+		~auto_deleter()
+		{
+			if (data) deleter(data);
+		}
+
+		T* release()
+		{
+			T* result = data;
+			data = 0;
+			return result;
+		}
+	};
+PUGI__NS_END
+
+#ifdef PUGIXML_COMPACT
+PUGI__NS_BEGIN
+	class compact_hash_table
+	{
+	public:
+		compact_hash_table(): _items(0), _capacity(0), _count(0)
+		{
+		}
+
+		void clear()
+		{
+			if (_items)
+			{
+				xml_memory::deallocate(_items);
+				_items = 0;
+				_capacity = 0;
+				_count = 0;
+			}
+		}
+
+		void** find(const void* key)
+		{
+			assert(key);
+
+			if (_capacity == 0) return 0;
+
+			size_t hashmod = _capacity - 1;
+			size_t bucket = hash(key) & hashmod;
+
+			for (size_t probe = 0; probe <= hashmod; ++probe)
+			{
+				item_t& probe_item = _items[bucket];
+
+				if (probe_item.key == key)
+					return &probe_item.value;
+
+				if (probe_item.key == 0)
+					return 0;
+
+				// hash collision, quadratic probing
+				bucket = (bucket + probe + 1) & hashmod;
+			}
+
+			assert(false && "Hash table is full");
+			return 0;
+		}
+
+		void** insert(const void* key)
+		{
+			assert(key);
+			assert(_capacity != 0 && _count < _capacity - _capacity / 4);
+
+			size_t hashmod = _capacity - 1;
+			size_t bucket = hash(key) & hashmod;
+
+			for (size_t probe = 0; probe <= hashmod; ++probe)
+			{
+				item_t& probe_item = _items[bucket];
+
+				if (probe_item.key == 0)
+				{
+					probe_item.key = key;
+					_count++;
+					return &probe_item.value;
+				}
+
+				if (probe_item.key == key)
+					return &probe_item.value;
+
+				// hash collision, quadratic probing
+				bucket = (bucket + probe + 1) & hashmod;
+			}
+
+			assert(false && "Hash table is full");
+			return 0;
+		}
+
+		bool reserve()
+		{
+			if (_count + 16 >= _capacity - _capacity / 4)
+				return rehash();
+
+			return true;
+		}
+
+	private:
+		struct item_t
+		{
+			const void* key;
+			void* value;
+		};
+
+		item_t* _items;
+		size_t _capacity;
+
+		size_t _count;
+
+		bool rehash();
+
+		static unsigned int hash(const void* key)
+		{
+			unsigned int h = static_cast<unsigned int>(reinterpret_cast<uintptr_t>(key));
+
+			// MurmurHash3 32-bit finalizer
+			h ^= h >> 16;
+			h *= 0x85ebca6bu;
+			h ^= h >> 13;
+			h *= 0xc2b2ae35u;
+			h ^= h >> 16;
+
+			return h;
+		}
+	};
+
+	PUGI__FN_NO_INLINE bool compact_hash_table::rehash()
+	{
+		compact_hash_table rt;
+		rt._capacity = (_capacity == 0) ? 32 : _capacity * 2;
+		rt._items = static_cast<item_t*>(xml_memory::allocate(sizeof(item_t) * rt._capacity));
+
+		if (!rt._items)
+			return false;
+
+		memset(rt._items, 0, sizeof(item_t) * rt._capacity);
+
+		for (size_t i = 0; i < _capacity; ++i)
+			if (_items[i].key)
+				*rt.insert(_items[i].key) = _items[i].value;
+
+		if (_items)
+			xml_memory::deallocate(_items);
+
+		_capacity = rt._capacity;
+		_items = rt._items;
+
+		assert(_count == rt._count);
+
+		return true;
+	}
+
+PUGI__NS_END
+#endif
+
+PUGI__NS_BEGIN
+#ifdef PUGIXML_COMPACT
+	static const uintptr_t xml_memory_block_alignment = 4;
+#else
+	static const uintptr_t xml_memory_block_alignment = sizeof(void*);
+#endif
+
+	// extra metadata bits
+	static const uintptr_t xml_memory_page_contents_shared_mask = 64;
+	static const uintptr_t xml_memory_page_name_allocated_mask = 32;
+	static const uintptr_t xml_memory_page_value_allocated_mask = 16;
+	static const uintptr_t xml_memory_page_type_mask = 15;
+
+	// combined masks for string uniqueness
+	static const uintptr_t xml_memory_page_name_allocated_or_shared_mask = xml_memory_page_name_allocated_mask | xml_memory_page_contents_shared_mask;
+	static const uintptr_t xml_memory_page_value_allocated_or_shared_mask = xml_memory_page_value_allocated_mask | xml_memory_page_contents_shared_mask;
+
+#ifdef PUGIXML_COMPACT
+	#define PUGI__GETHEADER_IMPL(object, page, flags) // unused
+	#define PUGI__GETPAGE_IMPL(header) (header).get_page()
+#else
+	#define PUGI__GETHEADER_IMPL(object, page, flags) (((reinterpret_cast<char*>(object) - reinterpret_cast<char*>(page)) << 8) | (flags))
+	// this macro casts pointers through void* to avoid 'cast increases required alignment of target type' warnings
+	#define PUGI__GETPAGE_IMPL(header) static_cast<impl::xml_memory_page*>(const_cast<void*>(static_cast<const void*>(reinterpret_cast<const char*>(&header) - (header >> 8))))
+#endif
+
+	#define PUGI__GETPAGE(n) PUGI__GETPAGE_IMPL((n)->header)
+	#define PUGI__NODETYPE(n) static_cast<xml_node_type>((n)->header & impl::xml_memory_page_type_mask)
+
+	struct xml_allocator;
+
+	struct xml_memory_page
+	{
+		static xml_memory_page* construct(void* memory)
+		{
+			xml_memory_page* result = static_cast<xml_memory_page*>(memory);
+
+			result->allocator = 0;
+			result->prev = 0;
+			result->next = 0;
+			result->busy_size = 0;
+			result->freed_size = 0;
+
+		#ifdef PUGIXML_COMPACT
+			result->compact_string_base = 0;
+			result->compact_shared_parent = 0;
+			result->compact_page_marker = 0;
+		#endif
+
+			return result;
+		}
+
+		xml_allocator* allocator;
+
+		xml_memory_page* prev;
+		xml_memory_page* next;
+
+		size_t busy_size;
+		size_t freed_size;
+
+	#ifdef PUGIXML_COMPACT
+		char_t* compact_string_base;
+		void* compact_shared_parent;
+		uint32_t* compact_page_marker;
+	#endif
+	};
+
+	static const size_t xml_memory_page_size =
+	#ifdef PUGIXML_MEMORY_PAGE_SIZE
+		(PUGIXML_MEMORY_PAGE_SIZE)
+	#else
+		32768
+	#endif
+		- sizeof(xml_memory_page);
+
+	struct xml_memory_string_header
+	{
+		uint16_t page_offset; // offset from page->data
+		uint16_t full_size; // 0 if string occupies whole page
+	};
+
+	struct xml_allocator
+	{
+		xml_allocator(xml_memory_page* root): _root(root), _busy_size(root->busy_size)
+		{
+		#ifdef PUGIXML_COMPACT
+			_hash = 0;
+		#endif
+		}
+
+		xml_memory_page* allocate_page(size_t data_size)
+		{
+			size_t size = sizeof(xml_memory_page) + data_size;
+
+			// allocate block with some alignment, leaving memory for worst-case padding
+			void* memory = xml_memory::allocate(size);
+			if (!memory) return 0;
+
+			// prepare page structure
+			xml_memory_page* page = xml_memory_page::construct(memory);
+			assert(page);
+
+			page->allocator = _root->allocator;
+
+			return page;
+		}
+
+		static void deallocate_page(xml_memory_page* page)
+		{
+			xml_memory::deallocate(page);
+		}
+
+		void* allocate_memory_oob(size_t size, xml_memory_page*& out_page);
+
+		void* allocate_memory(size_t size, xml_memory_page*& out_page)
+		{
+			if (PUGI__UNLIKELY(_busy_size + size > xml_memory_page_size))
+				return allocate_memory_oob(size, out_page);
+
+			void* buf = reinterpret_cast<char*>(_root) + sizeof(xml_memory_page) + _busy_size;
+
+			_busy_size += size;
+
+			out_page = _root;
+
+			return buf;
+		}
+
+	#ifdef PUGIXML_COMPACT
+		void* allocate_object(size_t size, xml_memory_page*& out_page)
+		{
+			void* result = allocate_memory(size + sizeof(uint32_t), out_page);
+			if (!result) return 0;
+
+			// adjust for marker
+			ptrdiff_t offset = static_cast<char*>(result) - reinterpret_cast<char*>(out_page->compact_page_marker);
+
+			if (PUGI__UNLIKELY(static_cast<uintptr_t>(offset) >= 256 * xml_memory_block_alignment))
+			{
+				// insert new marker
+				uint32_t* marker = static_cast<uint32_t*>(result);
+
+				*marker = static_cast<uint32_t>(reinterpret_cast<char*>(marker) - reinterpret_cast<char*>(out_page));
+				out_page->compact_page_marker = marker;
+
+				// since we don't reuse the page space until we reallocate it, we can just pretend that we freed the marker block
+				// this will make sure deallocate_memory correctly tracks the size
+				out_page->freed_size += sizeof(uint32_t);
+
+				return marker + 1;
+			}
+			else
+			{
+				// roll back uint32_t part
+				_busy_size -= sizeof(uint32_t);
+
+				return result;
+			}
+		}
+	#else
+		void* allocate_object(size_t size, xml_memory_page*& out_page)
+		{
+			return allocate_memory(size, out_page);
+		}
+	#endif
+
+		void deallocate_memory(void* ptr, size_t size, xml_memory_page* page)
+		{
+			if (page == _root) page->busy_size = _busy_size;
+
+			assert(ptr >= reinterpret_cast<char*>(page) + sizeof(xml_memory_page) && ptr < reinterpret_cast<char*>(page) + sizeof(xml_memory_page) + page->busy_size);
+			(void)!ptr;
+
+			page->freed_size += size;
+			assert(page->freed_size <= page->busy_size);
+
+			if (page->freed_size == page->busy_size)
+			{
+				if (page->next == 0)
+				{
+					assert(_root == page);
+
+					// top page freed, just reset sizes
+					page->busy_size = 0;
+					page->freed_size = 0;
+
+				#ifdef PUGIXML_COMPACT
+					// reset compact state to maximize efficiency
+					page->compact_string_base = 0;
+					page->compact_shared_parent = 0;
+					page->compact_page_marker = 0;
+				#endif
+
+					_busy_size = 0;
+				}
+				else
+				{
+					assert(_root != page);
+					assert(page->prev);
+
+					// remove from the list
+					page->prev->next = page->next;
+					page->next->prev = page->prev;
+
+					// deallocate
+					deallocate_page(page);
+				}
+			}
+		}
+
+		char_t* allocate_string(size_t length)
+		{
+			static const size_t max_encoded_offset = (1 << 16) * xml_memory_block_alignment;
+
+			PUGI__STATIC_ASSERT(xml_memory_page_size <= max_encoded_offset);
+
+			// allocate memory for string and header block
+			size_t size = sizeof(xml_memory_string_header) + length * sizeof(char_t);
+
+			// round size up to block alignment boundary
+			size_t full_size = (size + (xml_memory_block_alignment - 1)) & ~(xml_memory_block_alignment - 1);
+
+			xml_memory_page* page;
+			xml_memory_string_header* header = static_cast<xml_memory_string_header*>(allocate_memory(full_size, page));
+
+			if (!header) return 0;
+
+			// setup header
+			ptrdiff_t page_offset = reinterpret_cast<char*>(header) - reinterpret_cast<char*>(page) - sizeof(xml_memory_page);
+
+			assert(page_offset % xml_memory_block_alignment == 0);
+			assert(page_offset >= 0 && static_cast<size_t>(page_offset) < max_encoded_offset);
+			header->page_offset = static_cast<uint16_t>(static_cast<size_t>(page_offset) / xml_memory_block_alignment);
+
+			// full_size == 0 for large strings that occupy the whole page
+			assert(full_size % xml_memory_block_alignment == 0);
+			assert(full_size < max_encoded_offset || (page->busy_size == full_size && page_offset == 0));
+			header->full_size = static_cast<uint16_t>(full_size < max_encoded_offset ? full_size / xml_memory_block_alignment : 0);
+
+			// round-trip through void* to avoid 'cast increases required alignment of target type' warning
+			// header is guaranteed a pointer-sized alignment, which should be enough for char_t
+			return static_cast<char_t*>(static_cast<void*>(header + 1));
+		}
+
+		void deallocate_string(char_t* string)
+		{
+			// this function casts pointers through void* to avoid 'cast increases required alignment of target type' warnings
+			// we're guaranteed the proper (pointer-sized) alignment on the input string if it was allocated via allocate_string
+
+			// get header
+			xml_memory_string_header* header = static_cast<xml_memory_string_header*>(static_cast<void*>(string)) - 1;
+			assert(header);
+
+			// deallocate
+			size_t page_offset = sizeof(xml_memory_page) + header->page_offset * xml_memory_block_alignment;
+			xml_memory_page* page = reinterpret_cast<xml_memory_page*>(static_cast<void*>(reinterpret_cast<char*>(header) - page_offset));
+
+			// if full_size == 0 then this string occupies the whole page
+			size_t full_size = header->full_size == 0 ? page->busy_size : header->full_size * xml_memory_block_alignment;
+
+			deallocate_memory(header, full_size, page);
+		}
+
+		bool reserve()
+		{
+		#ifdef PUGIXML_COMPACT
+			return _hash->reserve();
+		#else
+			return true;
+		#endif
+		}
+
+		xml_memory_page* _root;
+		size_t _busy_size;
+
+	#ifdef PUGIXML_COMPACT
+		compact_hash_table* _hash;
+	#endif
+	};
+
+	PUGI__FN_NO_INLINE void* xml_allocator::allocate_memory_oob(size_t size, xml_memory_page*& out_page)
+	{
+		const size_t large_allocation_threshold = xml_memory_page_size / 4;
+
+		xml_memory_page* page = allocate_page(size <= large_allocation_threshold ? xml_memory_page_size : size);
+		out_page = page;
+
+		if (!page) return 0;
+
+		if (size <= large_allocation_threshold)
+		{
+			_root->busy_size = _busy_size;
+
+			// insert page at the end of linked list
+			page->prev = _root;
+			_root->next = page;
+			_root = page;
+
+			_busy_size = size;
+		}
+		else
+		{
+			// insert page before the end of linked list, so that it is deleted as soon as possible
+			// the last page is not deleted even if it's empty (see deallocate_memory)
+			assert(_root->prev);
+
+			page->prev = _root->prev;
+			page->next = _root;
+
+			_root->prev->next = page;
+			_root->prev = page;
+
+			page->busy_size = size;
+		}
+
+		return reinterpret_cast<char*>(page) + sizeof(xml_memory_page);
+	}
+PUGI__NS_END
+
+#ifdef PUGIXML_COMPACT
+PUGI__NS_BEGIN
+	static const uintptr_t compact_alignment_log2 = 2;
+	static const uintptr_t compact_alignment = 1 << compact_alignment_log2;
+
+	class compact_header
+	{
+	public:
+		compact_header(xml_memory_page* page, unsigned int flags)
+		{
+			PUGI__STATIC_ASSERT(xml_memory_block_alignment == compact_alignment);
+
+			ptrdiff_t offset = (reinterpret_cast<char*>(this) - reinterpret_cast<char*>(page->compact_page_marker));
+			assert(offset % compact_alignment == 0 && static_cast<uintptr_t>(offset) < 256 * compact_alignment);
+
+			_page = static_cast<unsigned char>(offset >> compact_alignment_log2);
+			_flags = static_cast<unsigned char>(flags);
+		}
+
+		void operator&=(uintptr_t mod)
+		{
+			_flags &= static_cast<unsigned char>(mod);
+		}
+
+		void operator|=(uintptr_t mod)
+		{
+			_flags |= static_cast<unsigned char>(mod);
+		}
+
+		uintptr_t operator&(uintptr_t mod) const
+		{
+			return _flags & mod;
+		}
+
+		xml_memory_page* get_page() const
+		{
+			// round-trip through void* to silence 'cast increases required alignment of target type' warnings
+			const char* page_marker = reinterpret_cast<const char*>(this) - (_page << compact_alignment_log2);
+			const char* page = page_marker - *reinterpret_cast<const uint32_t*>(static_cast<const void*>(page_marker));
+
+			return const_cast<xml_memory_page*>(reinterpret_cast<const xml_memory_page*>(static_cast<const void*>(page)));
+		}
+
+	private:
+		unsigned char _page;
+		unsigned char _flags;
+	};
+
+	PUGI__FN xml_memory_page* compact_get_page(const void* object, int header_offset)
+	{
+		const compact_header* header = reinterpret_cast<const compact_header*>(static_cast<const char*>(object) - header_offset);
+
+		return header->get_page();
+	}
+
+	template <int header_offset, typename T> PUGI__FN_NO_INLINE T* compact_get_value(const void* object)
+	{
+		return static_cast<T*>(*compact_get_page(object, header_offset)->allocator->_hash->find(object));
+	}
+
+	template <int header_offset, typename T> PUGI__FN_NO_INLINE void compact_set_value(const void* object, T* value)
+	{
+		*compact_get_page(object, header_offset)->allocator->_hash->insert(object) = value;
+	}
+
+	template <typename T, int header_offset, int start = -126> class compact_pointer
+	{
+	public:
+		compact_pointer(): _data(0)
+		{
+		}
+
+		void operator=(const compact_pointer& rhs)
+		{
+			*this = rhs + 0;
+		}
+
+		void operator=(T* value)
+		{
+			if (value)
+			{
+				// value is guaranteed to be compact-aligned; 'this' is not
+				// our decoding is based on 'this' aligned to compact alignment downwards (see operator T*)
+				// so for negative offsets (e.g. -3) we need to adjust the diff by compact_alignment - 1 to
+				// compensate for arithmetic shift rounding for negative values
+				ptrdiff_t diff = reinterpret_cast<char*>(value) - reinterpret_cast<char*>(this);
+				ptrdiff_t offset = ((diff + int(compact_alignment - 1)) >> compact_alignment_log2) - start;
+
+				if (static_cast<uintptr_t>(offset) <= 253)
+					_data = static_cast<unsigned char>(offset + 1);
+				else
+				{
+					compact_set_value<header_offset>(this, value);
+
+					_data = 255;
+				}
+			}
+			else
+				_data = 0;
+		}
+
+		operator T*() const
+		{
+			if (_data)
+			{
+				if (_data < 255)
+				{
+					uintptr_t base = reinterpret_cast<uintptr_t>(this) & ~(compact_alignment - 1);
+
+					return reinterpret_cast<T*>(base + ((_data - 1 + start) << compact_alignment_log2));
+				}
+				else
+					return compact_get_value<header_offset, T>(this);
+			}
+			else
+				return 0;
+		}
+
+		T* operator->() const
+		{
+			return *this;
+		}
+
+	private:
+		unsigned char _data;
+	};
+
+	template <typename T, int header_offset> class compact_pointer_parent
+	{
+	public:
+		compact_pointer_parent(): _data(0)
+		{
+		}
+
+		void operator=(const compact_pointer_parent& rhs)
+		{
+			*this = rhs + 0;
+		}
+
+		void operator=(T* value)
+		{
+			if (value)
+			{
+				// value is guaranteed to be compact-aligned; 'this' is not
+				// our decoding is based on 'this' aligned to compact alignment downwards (see operator T*)
+				// so for negative offsets (e.g. -3) we need to adjust the diff by compact_alignment - 1 to
+				// compensate for arithmetic shift behavior for negative values
+				ptrdiff_t diff = reinterpret_cast<char*>(value) - reinterpret_cast<char*>(this);
+				ptrdiff_t offset = ((diff + int(compact_alignment - 1)) >> compact_alignment_log2) + 65533;
+
+				if (static_cast<uintptr_t>(offset) <= 65533)
+				{
+					_data = static_cast<unsigned short>(offset + 1);
+				}
+				else
+				{
+					xml_memory_page* page = compact_get_page(this, header_offset);
+
+					if (PUGI__UNLIKELY(page->compact_shared_parent == 0))
+						page->compact_shared_parent = value;
+
+					if (page->compact_shared_parent == value)
+					{
+						_data = 65534;
+					}
+					else
+					{
+						compact_set_value<header_offset>(this, value);
+
+						_data = 65535;
+					}
+				}
+			}
+			else
+			{
+				_data = 0;
+			}
+		}
+
+		operator T*() const
+		{
+			if (_data)
+			{
+				if (_data < 65534)
+				{
+					uintptr_t base = reinterpret_cast<uintptr_t>(this) & ~(compact_alignment - 1);
+
+					return reinterpret_cast<T*>(base + ((_data - 1 - 65533) << compact_alignment_log2));
+				}
+				else if (_data == 65534)
+					return static_cast<T*>(compact_get_page(this, header_offset)->compact_shared_parent);
+				else
+					return compact_get_value<header_offset, T>(this);
+			}
+			else
+				return 0;
+		}
+
+		T* operator->() const
+		{
+			return *this;
+		}
+
+	private:
+		uint16_t _data;
+	};
+
+	template <int header_offset, int base_offset> class compact_string
+	{
+	public:
+		compact_string(): _data(0)
+		{
+		}
+
+		void operator=(const compact_string& rhs)
+		{
+			*this = rhs + 0;
+		}
+
+		void operator=(char_t* value)
+		{
+			if (value)
+			{
+				xml_memory_page* page = compact_get_page(this, header_offset);
+
+				if (PUGI__UNLIKELY(page->compact_string_base == 0))
+					page->compact_string_base = value;
+
+				ptrdiff_t offset = value - page->compact_string_base;
+
+				if (static_cast<uintptr_t>(offset) < (65535 << 7))
+				{
+					// round-trip through void* to silence 'cast increases required alignment of target type' warnings
+					uint16_t* base = reinterpret_cast<uint16_t*>(static_cast<void*>(reinterpret_cast<char*>(this) - base_offset));
+
+					if (*base == 0)
+					{
+						*base = static_cast<uint16_t>((offset >> 7) + 1);
+						_data = static_cast<unsigned char>((offset & 127) + 1);
+					}
+					else
+					{
+						ptrdiff_t remainder = offset - ((*base - 1) << 7);
+
+						if (static_cast<uintptr_t>(remainder) <= 253)
+						{
+							_data = static_cast<unsigned char>(remainder + 1);
+						}
+						else
+						{
+							compact_set_value<header_offset>(this, value);
+
+							_data = 255;
+						}
+					}
+				}
+				else
+				{
+					compact_set_value<header_offset>(this, value);
+
+					_data = 255;
+				}
+			}
+			else
+			{
+				_data = 0;
+			}
+		}
+
+		operator char_t*() const
+		{
+			if (_data)
+			{
+				if (_data < 255)
+				{
+					xml_memory_page* page = compact_get_page(this, header_offset);
+
+					// round-trip through void* to silence 'cast increases required alignment of target type' warnings
+					const uint16_t* base = reinterpret_cast<const uint16_t*>(static_cast<const void*>(reinterpret_cast<const char*>(this) - base_offset));
+					assert(*base);
+
+					ptrdiff_t offset = ((*base - 1) << 7) + (_data - 1);
+
+					return page->compact_string_base + offset;
+				}
+				else
+				{
+					return compact_get_value<header_offset, char_t>(this);
+				}
+			}
+			else
+				return 0;
+		}
+
+	private:
+		unsigned char _data;
+	};
+PUGI__NS_END
+#endif
+
+#ifdef PUGIXML_COMPACT
+namespace pugi
+{
+	struct xml_attribute_struct
+	{
+		xml_attribute_struct(impl::xml_memory_page* page): header(page, 0), namevalue_base(0)
+		{
+			PUGI__STATIC_ASSERT(sizeof(xml_attribute_struct) == 8);
+		}
+
+		impl::compact_header header;
+
+		uint16_t namevalue_base;
+
+		impl::compact_string<4, 2> name;
+		impl::compact_string<5, 3> value;
+
+		impl::compact_pointer<xml_attribute_struct, 6> prev_attribute_c;
+		impl::compact_pointer<xml_attribute_struct, 7, 0> next_attribute;
+	};
+
+	struct xml_node_struct
+	{
+		xml_node_struct(impl::xml_memory_page* page, xml_node_type type): header(page, type), namevalue_base(0)
+		{
+			PUGI__STATIC_ASSERT(sizeof(xml_node_struct) == 12);
+		}
+
+		impl::compact_header header;
+
+		uint16_t namevalue_base;
+
+		impl::compact_string<4, 2> name;
+		impl::compact_string<5, 3> value;
+
+		impl::compact_pointer_parent<xml_node_struct, 6> parent;
+
+		impl::compact_pointer<xml_node_struct, 8, 0> first_child;
+
+		impl::compact_pointer<xml_node_struct,  9>    prev_sibling_c;
+		impl::compact_pointer<xml_node_struct, 10, 0> next_sibling;
+
+		impl::compact_pointer<xml_attribute_struct, 11, 0> first_attribute;
+	};
+}
+#else
+namespace pugi
+{
+	struct xml_attribute_struct
+	{
+		xml_attribute_struct(impl::xml_memory_page* page): name(0), value(0), prev_attribute_c(0), next_attribute(0)
+		{
+			header = PUGI__GETHEADER_IMPL(this, page, 0);
+		}
+
+		uintptr_t header;
+
+		char_t*	name;
+		char_t*	value;
+
+		xml_attribute_struct* prev_attribute_c;
+		xml_attribute_struct* next_attribute;
+	};
+
+	struct xml_node_struct
+	{
+		xml_node_struct(impl::xml_memory_page* page, xml_node_type type): name(0), value(0), parent(0), first_child(0), prev_sibling_c(0), next_sibling(0), first_attribute(0)
+		{
+			header = PUGI__GETHEADER_IMPL(this, page, type);
+		}
+
+		uintptr_t header;
+
+		char_t* name;
+		char_t* value;
+
+		xml_node_struct* parent;
+
+		xml_node_struct* first_child;
+
+		xml_node_struct* prev_sibling_c;
+		xml_node_struct* next_sibling;
+
+		xml_attribute_struct* first_attribute;
+	};
+}
+#endif
+
+PUGI__NS_BEGIN
+	struct xml_extra_buffer
+	{
+		char_t* buffer;
+		xml_extra_buffer* next;
+	};
+
+	struct xml_document_struct: public xml_node_struct, public xml_allocator
+	{
+		xml_document_struct(xml_memory_page* page): xml_node_struct(page, node_document), xml_allocator(page), buffer(0), extra_buffers(0)
+		{
+		}
+
+		const char_t* buffer;
+
+		xml_extra_buffer* extra_buffers;
+
+	#ifdef PUGIXML_COMPACT
+		compact_hash_table hash;
+	#endif
+	};
+
+	template <typename Object> inline xml_allocator& get_allocator(const Object* object)
+	{
+		assert(object);
+
+		return *PUGI__GETPAGE(object)->allocator;
+	}
+
+	template <typename Object> inline xml_document_struct& get_document(const Object* object)
+	{
+		assert(object);
+
+		return *static_cast<xml_document_struct*>(PUGI__GETPAGE(object)->allocator);
+	}
+PUGI__NS_END
+
+// Low-level DOM operations
+PUGI__NS_BEGIN
+	inline xml_attribute_struct* allocate_attribute(xml_allocator& alloc)
+	{
+		xml_memory_page* page;
+		void* memory = alloc.allocate_object(sizeof(xml_attribute_struct), page);
+		if (!memory) return 0;
+
+		return new (memory) xml_attribute_struct(page);
+	}
+
+	inline xml_node_struct* allocate_node(xml_allocator& alloc, xml_node_type type)
+	{
+		xml_memory_page* page;
+		void* memory = alloc.allocate_object(sizeof(xml_node_struct), page);
+		if (!memory) return 0;
+
+		return new (memory) xml_node_struct(page, type);
+	}
+
+	inline void destroy_attribute(xml_attribute_struct* a, xml_allocator& alloc)
+	{
+		if (a->header & impl::xml_memory_page_name_allocated_mask)
+			alloc.deallocate_string(a->name);
+
+		if (a->header & impl::xml_memory_page_value_allocated_mask)
+			alloc.deallocate_string(a->value);
+
+		alloc.deallocate_memory(a, sizeof(xml_attribute_struct), PUGI__GETPAGE(a));
+	}
+
+	inline void destroy_node(xml_node_struct* n, xml_allocator& alloc)
+	{
+		if (n->header & impl::xml_memory_page_name_allocated_mask)
+			alloc.deallocate_string(n->name);
+
+		if (n->header & impl::xml_memory_page_value_allocated_mask)
+			alloc.deallocate_string(n->value);
+
+		for (xml_attribute_struct* attr = n->first_attribute; attr; )
+		{
+			xml_attribute_struct* next = attr->next_attribute;
+
+			destroy_attribute(attr, alloc);
+
+			attr = next;
+		}
+
+		for (xml_node_struct* child = n->first_child; child; )
+		{
+			xml_node_struct* next = child->next_sibling;
+
+			destroy_node(child, alloc);
+
+			child = next;
+		}
+
+		alloc.deallocate_memory(n, sizeof(xml_node_struct), PUGI__GETPAGE(n));
+	}
+
+	inline void append_node(xml_node_struct* child, xml_node_struct* node)
+	{
+		child->parent = node;
+
+		xml_node_struct* head = node->first_child;
+
+		if (head)
+		{
+			xml_node_struct* tail = head->prev_sibling_c;
+
+			tail->next_sibling = child;
+			child->prev_sibling_c = tail;
+			head->prev_sibling_c = child;
+		}
+		else
+		{
+			node->first_child = child;
+			child->prev_sibling_c = child;
+		}
+	}
+
+	inline void prepend_node(xml_node_struct* child, xml_node_struct* node)
+	{
+		child->parent = node;
+
+		xml_node_struct* head = node->first_child;
+
+		if (head)
+		{
+			child->prev_sibling_c = head->prev_sibling_c;
+			head->prev_sibling_c = child;
+		}
+		else
+			child->prev_sibling_c = child;
+
+		child->next_sibling = head;
+		node->first_child = child;
+	}
+
+	inline void insert_node_after(xml_node_struct* child, xml_node_struct* node)
+	{
+		xml_node_struct* parent = node->parent;
+
+		child->parent = parent;
+
+		if (node->next_sibling)
+			node->next_sibling->prev_sibling_c = child;
+		else
+			parent->first_child->prev_sibling_c = child;
+
+		child->next_sibling = node->next_sibling;
+		child->prev_sibling_c = node;
+
+		node->next_sibling = child;
+	}
+
+	inline void insert_node_before(xml_node_struct* child, xml_node_struct* node)
+	{
+		xml_node_struct* parent = node->parent;
+
+		child->parent = parent;
+
+		if (node->prev_sibling_c->next_sibling)
+			node->prev_sibling_c->next_sibling = child;
+		else
+			parent->first_child = child;
+
+		child->prev_sibling_c = node->prev_sibling_c;
+		child->next_sibling = node;
+
+		node->prev_sibling_c = child;
+	}
+
+	inline void remove_node(xml_node_struct* node)
+	{
+		xml_node_struct* parent = node->parent;
+
+		if (node->next_sibling)
+			node->next_sibling->prev_sibling_c = node->prev_sibling_c;
+		else
+			parent->first_child->prev_sibling_c = node->prev_sibling_c;
+
+		if (node->prev_sibling_c->next_sibling)
+			node->prev_sibling_c->next_sibling = node->next_sibling;
+		else
+			parent->first_child = node->next_sibling;
+
+		node->parent = 0;
+		node->prev_sibling_c = 0;
+		node->next_sibling = 0;
+	}
+
+	inline void append_attribute(xml_attribute_struct* attr, xml_node_struct* node)
+	{
+		xml_attribute_struct* head = node->first_attribute;
+
+		if (head)
+		{
+			xml_attribute_struct* tail = head->prev_attribute_c;
+
+			tail->next_attribute = attr;
+			attr->prev_attribute_c = tail;
+			head->prev_attribute_c = attr;
+		}
+		else
+		{
+			node->first_attribute = attr;
+			attr->prev_attribute_c = attr;
+		}
+	}
+
+	inline void prepend_attribute(xml_attribute_struct* attr, xml_node_struct* node)
+	{
+		xml_attribute_struct* head = node->first_attribute;
+
+		if (head)
+		{
+			attr->prev_attribute_c = head->prev_attribute_c;
+			head->prev_attribute_c = attr;
+		}
+		else
+			attr->prev_attribute_c = attr;
+
+		attr->next_attribute = head;
+		node->first_attribute = attr;
+	}
+
+	inline void insert_attribute_after(xml_attribute_struct* attr, xml_attribute_struct* place, xml_node_struct* node)
+	{
+		if (place->next_attribute)
+			place->next_attribute->prev_attribute_c = attr;
+		else
+			node->first_attribute->prev_attribute_c = attr;
+
+		attr->next_attribute = place->next_attribute;
+		attr->prev_attribute_c = place;
+		place->next_attribute = attr;
+	}
+
+	inline void insert_attribute_before(xml_attribute_struct* attr, xml_attribute_struct* place, xml_node_struct* node)
+	{
+		if (place->prev_attribute_c->next_attribute)
+			place->prev_attribute_c->next_attribute = attr;
+		else
+			node->first_attribute = attr;
+
+		attr->prev_attribute_c = place->prev_attribute_c;
+		attr->next_attribute = place;
+		place->prev_attribute_c = attr;
+	}
+
+	inline void remove_attribute(xml_attribute_struct* attr, xml_node_struct* node)
+	{
+		if (attr->next_attribute)
+			attr->next_attribute->prev_attribute_c = attr->prev_attribute_c;
+		else
+			node->first_attribute->prev_attribute_c = attr->prev_attribute_c;
+
+		if (attr->prev_attribute_c->next_attribute)
+			attr->prev_attribute_c->next_attribute = attr->next_attribute;
+		else
+			node->first_attribute = attr->next_attribute;
+
+		attr->prev_attribute_c = 0;
+		attr->next_attribute = 0;
+	}
+
+	PUGI__FN_NO_INLINE xml_node_struct* append_new_node(xml_node_struct* node, xml_allocator& alloc, xml_node_type type = node_element)
+	{
+		if (!alloc.reserve()) return 0;
+
+		xml_node_struct* child = allocate_node(alloc, type);
+		if (!child) return 0;
+
+		append_node(child, node);
+
+		return child;
+	}
+
+	PUGI__FN_NO_INLINE xml_attribute_struct* append_new_attribute(xml_node_struct* node, xml_allocator& alloc)
+	{
+		if (!alloc.reserve()) return 0;
+
+		xml_attribute_struct* attr = allocate_attribute(alloc);
+		if (!attr) return 0;
+
+		append_attribute(attr, node);
+
+		return attr;
+	}
+PUGI__NS_END
+
+// Helper classes for code generation
+PUGI__NS_BEGIN
+	struct opt_false
+	{
+		enum { value = 0 };
+	};
+
+	struct opt_true
+	{
+		enum { value = 1 };
+	};
+PUGI__NS_END
+
+// Unicode utilities
+PUGI__NS_BEGIN
+	inline uint16_t endian_swap(uint16_t value)
+	{
+		return static_cast<uint16_t>(((value & 0xff) << 8) | (value >> 8));
+	}
+
+	inline uint32_t endian_swap(uint32_t value)
+	{
+		return ((value & 0xff) << 24) | ((value & 0xff00) << 8) | ((value & 0xff0000) >> 8) | (value >> 24);
+	}
+
+	struct utf8_counter
+	{
+		typedef size_t value_type;
+
+		static value_type low(value_type result, uint32_t ch)
+		{
+			// U+0000..U+007F
+			if (ch < 0x80) return result + 1;
+			// U+0080..U+07FF
+			else if (ch < 0x800) return result + 2;
+			// U+0800..U+FFFF
+			else return result + 3;
+		}
+
+		static value_type high(value_type result, uint32_t)
+		{
+			// U+10000..U+10FFFF
+			return result + 4;
+		}
+	};
+
+	struct utf8_writer
+	{
+		typedef uint8_t* value_type;
+
+		static value_type low(value_type result, uint32_t ch)
+		{
+			// U+0000..U+007F
+			if (ch < 0x80)
+			{
+				*result = static_cast<uint8_t>(ch);
+				return result + 1;
+			}
+			// U+0080..U+07FF
+			else if (ch < 0x800)
+			{
+				result[0] = static_cast<uint8_t>(0xC0 | (ch >> 6));
+				result[1] = static_cast<uint8_t>(0x80 | (ch & 0x3F));
+				return result + 2;
+			}
+			// U+0800..U+FFFF
+			else
+			{
+				result[0] = static_cast<uint8_t>(0xE0 | (ch >> 12));
+				result[1] = static_cast<uint8_t>(0x80 | ((ch >> 6) & 0x3F));
+				result[2] = static_cast<uint8_t>(0x80 | (ch & 0x3F));
+				return result + 3;
+			}
+		}
+
+		static value_type high(value_type result, uint32_t ch)
+		{
+			// U+10000..U+10FFFF
+			result[0] = static_cast<uint8_t>(0xF0 | (ch >> 18));
+			result[1] = static_cast<uint8_t>(0x80 | ((ch >> 12) & 0x3F));
+			result[2] = static_cast<uint8_t>(0x80 | ((ch >> 6) & 0x3F));
+			result[3] = static_cast<uint8_t>(0x80 | (ch & 0x3F));
+			return result + 4;
+		}
+
+		static value_type any(value_type result, uint32_t ch)
+		{
+			return (ch < 0x10000) ? low(result, ch) : high(result, ch);
+		}
+	};
+
+	struct utf16_counter
+	{
+		typedef size_t value_type;
+
+		static value_type low(value_type result, uint32_t)
+		{
+			return result + 1;
+		}
+
+		static value_type high(value_type result, uint32_t)
+		{
+			return result + 2;
+		}
+	};
+
+	struct utf16_writer
+	{
+		typedef uint16_t* value_type;
+
+		static value_type low(value_type result, uint32_t ch)
+		{
+			*result = static_cast<uint16_t>(ch);
+
+			return result + 1;
+		}
+
+		static value_type high(value_type result, uint32_t ch)
+		{
+			uint32_t msh = static_cast<uint32_t>(ch - 0x10000) >> 10;
+			uint32_t lsh = static_cast<uint32_t>(ch - 0x10000) & 0x3ff;
+
+			result[0] = static_cast<uint16_t>(0xD800 + msh);
+			result[1] = static_cast<uint16_t>(0xDC00 + lsh);
+
+			return result + 2;
+		}
+
+		static value_type any(value_type result, uint32_t ch)
+		{
+			return (ch < 0x10000) ? low(result, ch) : high(result, ch);
+		}
+	};
+
+	struct utf32_counter
+	{
+		typedef size_t value_type;
+
+		static value_type low(value_type result, uint32_t)
+		{
+			return result + 1;
+		}
+
+		static value_type high(value_type result, uint32_t)
+		{
+			return result + 1;
+		}
+	};
+
+	struct utf32_writer
+	{
+		typedef uint32_t* value_type;
+
+		static value_type low(value_type result, uint32_t ch)
+		{
+			*result = ch;
+
+			return result + 1;
+		}
+
+		static value_type high(value_type result, uint32_t ch)
+		{
+			*result = ch;
+
+			return result + 1;
+		}
+
+		static value_type any(value_type result, uint32_t ch)
+		{
+			*result = ch;
+
+			return result + 1;
+		}
+	};
+
+	struct latin1_writer
+	{
+		typedef uint8_t* value_type;
+
+		static value_type low(value_type result, uint32_t ch)
+		{
+			*result = static_cast<uint8_t>(ch > 255 ? '?' : ch);
+
+			return result + 1;
+		}
+
+		static value_type high(value_type result, uint32_t ch)
+		{
+			(void)ch;
+
+			*result = '?';
+
+			return result + 1;
+		}
+	};
+
+	struct utf8_decoder
+	{
+		typedef uint8_t type;
+
+		template <typename Traits> static inline typename Traits::value_type process(const uint8_t* data, size_t size, typename Traits::value_type result, Traits)
+		{
+			const uint8_t utf8_byte_mask = 0x3f;
+
+			while (size)
+			{
+				uint8_t lead = *data;
+
+				// 0xxxxxxx -> U+0000..U+007F
+				if (lead < 0x80)
+				{
+					result = Traits::low(result, lead);
+					data += 1;
+					size -= 1;
+
+					// process aligned single-byte (ascii) blocks
+					if ((reinterpret_cast<uintptr_t>(data) & 3) == 0)
+					{
+						// round-trip through void* to silence 'cast increases required alignment of target type' warnings
+						while (size >= 4 && (*static_cast<const uint32_t*>(static_cast<const void*>(data)) & 0x80808080) == 0)
+						{
+							result = Traits::low(result, data[0]);
+							result = Traits::low(result, data[1]);
+							result = Traits::low(result, data[2]);
+							result = Traits::low(result, data[3]);
+							data += 4;
+							size -= 4;
+						}
+					}
+				}
+				// 110xxxxx -> U+0080..U+07FF
+				else if (static_cast<unsigned int>(lead - 0xC0) < 0x20 && size >= 2 && (data[1] & 0xc0) == 0x80)
+				{
+					result = Traits::low(result, ((lead & ~0xC0) << 6) | (data[1] & utf8_byte_mask));
+					data += 2;
+					size -= 2;
+				}
+				// 1110xxxx -> U+0800-U+FFFF
+				else if (static_cast<unsigned int>(lead - 0xE0) < 0x10 && size >= 3 && (data[1] & 0xc0) == 0x80 && (data[2] & 0xc0) == 0x80)
+				{
+					result = Traits::low(result, ((lead & ~0xE0) << 12) | ((data[1] & utf8_byte_mask) << 6) | (data[2] & utf8_byte_mask));
+					data += 3;
+					size -= 3;
+				}
+				// 11110xxx -> U+10000..U+10FFFF
+				else if (static_cast<unsigned int>(lead - 0xF0) < 0x08 && size >= 4 && (data[1] & 0xc0) == 0x80 && (data[2] & 0xc0) == 0x80 && (data[3] & 0xc0) == 0x80)
+				{
+					result = Traits::high(result, ((lead & ~0xF0) << 18) | ((data[1] & utf8_byte_mask) << 12) | ((data[2] & utf8_byte_mask) << 6) | (data[3] & utf8_byte_mask));
+					data += 4;
+					size -= 4;
+				}
+				// 10xxxxxx or 11111xxx -> invalid
+				else
+				{
+					data += 1;
+					size -= 1;
+				}
+			}
+
+			return result;
+		}
+	};
+
+	template <typename opt_swap> struct utf16_decoder
+	{
+		typedef uint16_t type;
+
+		template <typename Traits> static inline typename Traits::value_type process(const uint16_t* data, size_t size, typename Traits::value_type result, Traits)
+		{
+			while (size)
+			{
+				uint16_t lead = opt_swap::value ? endian_swap(*data) : *data;
+
+				// U+0000..U+D7FF
+				if (lead < 0xD800)
+				{
+					result = Traits::low(result, lead);
+					data += 1;
+					size -= 1;
+				}
+				// U+E000..U+FFFF
+				else if (static_cast<unsigned int>(lead - 0xE000) < 0x2000)
+				{
+					result = Traits::low(result, lead);
+					data += 1;
+					size -= 1;
+				}
+				// surrogate pair lead
+				else if (static_cast<unsigned int>(lead - 0xD800) < 0x400 && size >= 2)
+				{
+					uint16_t next = opt_swap::value ? endian_swap(data[1]) : data[1];
+
+					if (static_cast<unsigned int>(next - 0xDC00) < 0x400)
+					{
+						result = Traits::high(result, 0x10000 + ((lead & 0x3ff) << 10) + (next & 0x3ff));
+						data += 2;
+						size -= 2;
+					}
+					else
+					{
+						data += 1;
+						size -= 1;
+					}
+				}
+				else
+				{
+					data += 1;
+					size -= 1;
+				}
+			}
+
+			return result;
+		}
+	};
+
+	template <typename opt_swap> struct utf32_decoder
+	{
+		typedef uint32_t type;
+
+		template <typename Traits> static inline typename Traits::value_type process(const uint32_t* data, size_t size, typename Traits::value_type result, Traits)
+		{
+			while (size)
+			{
+				uint32_t lead = opt_swap::value ? endian_swap(*data) : *data;
+
+				// U+0000..U+FFFF
+				if (lead < 0x10000)
+				{
+					result = Traits::low(result, lead);
+					data += 1;
+					size -= 1;
+				}
+				// U+10000..U+10FFFF
+				else
+				{
+					result = Traits::high(result, lead);
+					data += 1;
+					size -= 1;
+				}
+			}
+
+			return result;
+		}
+	};
+
+	struct latin1_decoder
+	{
+		typedef uint8_t type;
+
+		template <typename Traits> static inline typename Traits::value_type process(const uint8_t* data, size_t size, typename Traits::value_type result, Traits)
+		{
+			while (size)
+			{
+				result = Traits::low(result, *data);
+				data += 1;
+				size -= 1;
+			}
+
+			return result;
+		}
+	};
+
+	template <size_t size> struct wchar_selector;
+
+	template <> struct wchar_selector<2>
+	{
+		typedef uint16_t type;
+		typedef utf16_counter counter;
+		typedef utf16_writer writer;
+		typedef utf16_decoder<opt_false> decoder;
+	};
+
+	template <> struct wchar_selector<4>
+	{
+		typedef uint32_t type;
+		typedef utf32_counter counter;
+		typedef utf32_writer writer;
+		typedef utf32_decoder<opt_false> decoder;
+	};
+
+	typedef wchar_selector<sizeof(wchar_t)>::counter wchar_counter;
+	typedef wchar_selector<sizeof(wchar_t)>::writer wchar_writer;
+
+	struct wchar_decoder
+	{
+		typedef wchar_t type;
+
+		template <typename Traits> static inline typename Traits::value_type process(const wchar_t* data, size_t size, typename Traits::value_type result, Traits traits)
+		{
+			typedef wchar_selector<sizeof(wchar_t)>::decoder decoder;
+
+			return decoder::process(reinterpret_cast<const typename decoder::type*>(data), size, result, traits);
+		}
+	};
+
+#ifdef PUGIXML_WCHAR_MODE
+	PUGI__FN void convert_wchar_endian_swap(wchar_t* result, const wchar_t* data, size_t length)
+	{
+		for (size_t i = 0; i < length; ++i)
+			result[i] = static_cast<wchar_t>(endian_swap(static_cast<wchar_selector<sizeof(wchar_t)>::type>(data[i])));
+	}
+#endif
+PUGI__NS_END
+
+PUGI__NS_BEGIN
+	enum chartype_t
+	{
+		ct_parse_pcdata = 1,	// \0, &, \r, <
+		ct_parse_attr = 2,		// \0, &, \r, ', "
+		ct_parse_attr_ws = 4,	// \0, &, \r, ', ", \n, tab
+		ct_space = 8,			// \r, \n, space, tab
+		ct_parse_cdata = 16,	// \0, ], >, \r
+		ct_parse_comment = 32,	// \0, -, >, \r
+		ct_symbol = 64,			// Any symbol > 127, a-z, A-Z, 0-9, _, :, -, .
+		ct_start_symbol = 128	// Any symbol > 127, a-z, A-Z, _, :
+	};
+
+	static const unsigned char chartype_table[256] =
+	{
+		55,  0,   0,   0,   0,   0,   0,   0,      0,   12,  12,  0,   0,   63,  0,   0,   // 0-15
+		0,   0,   0,   0,   0,   0,   0,   0,      0,   0,   0,   0,   0,   0,   0,   0,   // 16-31
+		8,   0,   6,   0,   0,   0,   7,   6,      0,   0,   0,   0,   0,   96,  64,  0,   // 32-47
+		64,  64,  64,  64,  64,  64,  64,  64,     64,  64,  192, 0,   1,   0,   48,  0,   // 48-63
+		0,   192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192, // 64-79
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 0,   0,   16,  0,   192, // 80-95
+		0,   192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192, // 96-111
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 0, 0, 0, 0, 0,           // 112-127
+
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192, // 128+
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192,
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192,
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192,
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192,
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192,
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192,
+		192, 192, 192, 192, 192, 192, 192, 192,    192, 192, 192, 192, 192, 192, 192, 192
+	};
+
+	enum chartypex_t
+	{
+		ctx_special_pcdata = 1,   // Any symbol >= 0 and < 32 (except \t, \r, \n), &, <, >
+		ctx_special_attr = 2,     // Any symbol >= 0 and < 32 (except \t), &, <, >, "
+		ctx_start_symbol = 4,	  // Any symbol > 127, a-z, A-Z, _
+		ctx_digit = 8,			  // 0-9
+		ctx_symbol = 16			  // Any symbol > 127, a-z, A-Z, 0-9, _, -, .
+	};
+
+	static const unsigned char chartypex_table[256] =
+	{
+		3,  3,  3,  3,  3,  3,  3,  3,     3,  0,  2,  3,  3,  2,  3,  3,     // 0-15
+		3,  3,  3,  3,  3,  3,  3,  3,     3,  3,  3,  3,  3,  3,  3,  3,     // 16-31
+		0,  0,  2,  0,  0,  0,  3,  0,     0,  0,  0,  0,  0, 16, 16,  0,     // 32-47
+		24, 24, 24, 24, 24, 24, 24, 24,    24, 24, 0,  0,  3,  0,  3,  0,     // 48-63
+
+		0,  20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,    // 64-79
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 0,  0,  0,  0,  20,    // 80-95
+		0,  20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,    // 96-111
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 0,  0,  0,  0,  0,     // 112-127
+
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,    // 128+
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20,
+		20, 20, 20, 20, 20, 20, 20, 20,    20, 20, 20, 20, 20, 20, 20, 20
+	};
+
+#ifdef PUGIXML_WCHAR_MODE
+	#define PUGI__IS_CHARTYPE_IMPL(c, ct, table) ((static_cast<unsigned int>(c) < 128 ? table[static_cast<unsigned int>(c)] : table[128]) & (ct))
+#else
+	#define PUGI__IS_CHARTYPE_IMPL(c, ct, table) (table[static_cast<unsigned char>(c)] & (ct))
+#endif
+
+	#define PUGI__IS_CHARTYPE(c, ct) PUGI__IS_CHARTYPE_IMPL(c, ct, chartype_table)
+	#define PUGI__IS_CHARTYPEX(c, ct) PUGI__IS_CHARTYPE_IMPL(c, ct, chartypex_table)
+
+	PUGI__FN bool is_little_endian()
+	{
+		unsigned int ui = 1;
+
+		return *reinterpret_cast<unsigned char*>(&ui) == 1;
+	}
+
+	PUGI__FN xml_encoding get_wchar_encoding()
+	{
+		PUGI__STATIC_ASSERT(sizeof(wchar_t) == 2 || sizeof(wchar_t) == 4);
+
+		if (sizeof(wchar_t) == 2)
+			return is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+		else
+			return is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+	}
+
+	PUGI__FN bool parse_declaration_encoding(const uint8_t* data, size_t size, const uint8_t*& out_encoding, size_t& out_length)
+	{
+	#define PUGI__SCANCHAR(ch) { if (offset >= size || data[offset] != ch) return false; offset++; }
+	#define PUGI__SCANCHARTYPE(ct) { while (offset < size && PUGI__IS_CHARTYPE(data[offset], ct)) offset++; }
+
+		// check if we have a non-empty XML declaration
+		if (size < 6 || !((data[0] == '<') & (data[1] == '?') & (data[2] == 'x') & (data[3] == 'm') & (data[4] == 'l') && PUGI__IS_CHARTYPE(data[5], ct_space)))
+			return false;
+
+		// scan XML declaration until the encoding field
+		for (size_t i = 6; i + 1 < size; ++i)
+		{
+			// declaration can not contain ? in quoted values
+			if (data[i] == '?')
+				return false;
+
+			if (data[i] == 'e' && data[i + 1] == 'n')
+			{
+				size_t offset = i;
+
+				// encoding follows the version field which can't contain 'en' so this has to be the encoding if XML is well formed
+				PUGI__SCANCHAR('e'); PUGI__SCANCHAR('n'); PUGI__SCANCHAR('c'); PUGI__SCANCHAR('o');
+				PUGI__SCANCHAR('d'); PUGI__SCANCHAR('i'); PUGI__SCANCHAR('n'); PUGI__SCANCHAR('g');
+
+				// S? = S?
+				PUGI__SCANCHARTYPE(ct_space);
+				PUGI__SCANCHAR('=');
+				PUGI__SCANCHARTYPE(ct_space);
+
+				// the only two valid delimiters are ' and "
+				uint8_t delimiter = (offset < size && data[offset] == '"') ? '"' : '\'';
+
+				PUGI__SCANCHAR(delimiter);
+
+				size_t start = offset;
+
+				out_encoding = data + offset;
+
+				PUGI__SCANCHARTYPE(ct_symbol);
+
+				out_length = offset - start;
+
+				PUGI__SCANCHAR(delimiter);
+
+				return true;
+			}
+		}
+
+		return false;
+
+	#undef PUGI__SCANCHAR
+	#undef PUGI__SCANCHARTYPE
+	}
+
+	PUGI__FN xml_encoding guess_buffer_encoding(const uint8_t* data, size_t size)
+	{
+		// skip encoding autodetection if input buffer is too small
+		if (size < 4) return encoding_utf8;
+
+		uint8_t d0 = data[0], d1 = data[1], d2 = data[2], d3 = data[3];
+
+		// look for BOM in first few bytes
+		if (d0 == 0 && d1 == 0 && d2 == 0xfe && d3 == 0xff) return encoding_utf32_be;
+		if (d0 == 0xff && d1 == 0xfe && d2 == 0 && d3 == 0) return encoding_utf32_le;
+		if (d0 == 0xfe && d1 == 0xff) return encoding_utf16_be;
+		if (d0 == 0xff && d1 == 0xfe) return encoding_utf16_le;
+		if (d0 == 0xef && d1 == 0xbb && d2 == 0xbf) return encoding_utf8;
+
+		// look for <, <? or <?xm in various encodings
+		if (d0 == 0 && d1 == 0 && d2 == 0 && d3 == 0x3c) return encoding_utf32_be;
+		if (d0 == 0x3c && d1 == 0 && d2 == 0 && d3 == 0) return encoding_utf32_le;
+		if (d0 == 0 && d1 == 0x3c && d2 == 0 && d3 == 0x3f) return encoding_utf16_be;
+		if (d0 == 0x3c && d1 == 0 && d2 == 0x3f && d3 == 0) return encoding_utf16_le;
+
+		// look for utf16 < followed by node name (this may fail, but is better than utf8 since it's zero terminated so early)
+		if (d0 == 0 && d1 == 0x3c) return encoding_utf16_be;
+		if (d0 == 0x3c && d1 == 0) return encoding_utf16_le;
+
+		// no known BOM detected; parse declaration
+		const uint8_t* enc = 0;
+		size_t enc_length = 0;
+
+		if (d0 == 0x3c && d1 == 0x3f && d2 == 0x78 && d3 == 0x6d && parse_declaration_encoding(data, size, enc, enc_length))
+		{
+			// iso-8859-1 (case-insensitive)
+			if (enc_length == 10
+				&& (enc[0] | ' ') == 'i' && (enc[1] | ' ') == 's' && (enc[2] | ' ') == 'o'
+				&& enc[3] == '-' && enc[4] == '8' && enc[5] == '8' && enc[6] == '5' && enc[7] == '9'
+				&& enc[8] == '-' && enc[9] == '1')
+				return encoding_latin1;
+
+			// latin1 (case-insensitive)
+			if (enc_length == 6
+				&& (enc[0] | ' ') == 'l' && (enc[1] | ' ') == 'a' && (enc[2] | ' ') == 't'
+				&& (enc[3] | ' ') == 'i' && (enc[4] | ' ') == 'n'
+				&& enc[5] == '1')
+				return encoding_latin1;
+		}
+
+		return encoding_utf8;
+	}
+
+	PUGI__FN xml_encoding get_buffer_encoding(xml_encoding encoding, const void* contents, size_t size)
+	{
+		// replace wchar encoding with utf implementation
+		if (encoding == encoding_wchar) return get_wchar_encoding();
+
+		// replace utf16 encoding with utf16 with specific endianness
+		if (encoding == encoding_utf16) return is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+
+		// replace utf32 encoding with utf32 with specific endianness
+		if (encoding == encoding_utf32) return is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+
+		// only do autodetection if no explicit encoding is requested
+		if (encoding != encoding_auto) return encoding;
+
+		// try to guess encoding (based on XML specification, Appendix F.1)
+		const uint8_t* data = static_cast<const uint8_t*>(contents);
+
+		return guess_buffer_encoding(data, size);
+	}
+
+	PUGI__FN bool get_mutable_buffer(char_t*& out_buffer, size_t& out_length, const void* contents, size_t size, bool is_mutable)
+	{
+		size_t length = size / sizeof(char_t);
+
+		if (is_mutable)
+		{
+			out_buffer = static_cast<char_t*>(const_cast<void*>(contents));
+			out_length = length;
+		}
+		else
+		{
+			char_t* buffer = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+			if (!buffer) return false;
+
+			if (contents)
+				memcpy(buffer, contents, length * sizeof(char_t));
+			else
+				assert(length == 0);
+
+			buffer[length] = 0;
+
+			out_buffer = buffer;
+			out_length = length + 1;
+		}
+
+		return true;
+	}
+
+#ifdef PUGIXML_WCHAR_MODE
+	PUGI__FN bool need_endian_swap_utf(xml_encoding le, xml_encoding re)
+	{
+		return (le == encoding_utf16_be && re == encoding_utf16_le) || (le == encoding_utf16_le && re == encoding_utf16_be) ||
+			   (le == encoding_utf32_be && re == encoding_utf32_le) || (le == encoding_utf32_le && re == encoding_utf32_be);
+	}
+
+	PUGI__FN bool convert_buffer_endian_swap(char_t*& out_buffer, size_t& out_length, const void* contents, size_t size, bool is_mutable)
+	{
+		const char_t* data = static_cast<const char_t*>(contents);
+		size_t length = size / sizeof(char_t);
+
+		if (is_mutable)
+		{
+			char_t* buffer = const_cast<char_t*>(data);
+
+			convert_wchar_endian_swap(buffer, data, length);
+
+			out_buffer = buffer;
+			out_length = length;
+		}
+		else
+		{
+			char_t* buffer = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+			if (!buffer) return false;
+
+			convert_wchar_endian_swap(buffer, data, length);
+			buffer[length] = 0;
+
+			out_buffer = buffer;
+			out_length = length + 1;
+		}
+
+		return true;
+	}
+
+	template <typename D> PUGI__FN bool convert_buffer_generic(char_t*& out_buffer, size_t& out_length, const void* contents, size_t size, D)
+	{
+		const typename D::type* data = static_cast<const typename D::type*>(contents);
+		size_t data_length = size / sizeof(typename D::type);
+
+		// first pass: get length in wchar_t units
+		size_t length = D::process(data, data_length, 0, wchar_counter());
+
+		// allocate buffer of suitable length
+		char_t* buffer = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+		if (!buffer) return false;
+
+		// second pass: convert utf16 input to wchar_t
+		wchar_writer::value_type obegin = reinterpret_cast<wchar_writer::value_type>(buffer);
+		wchar_writer::value_type oend = D::process(data, data_length, obegin, wchar_writer());
+
+		assert(oend == obegin + length);
+		*oend = 0;
+
+		out_buffer = buffer;
+		out_length = length + 1;
+
+		return true;
+	}
+
+	PUGI__FN bool convert_buffer(char_t*& out_buffer, size_t& out_length, xml_encoding encoding, const void* contents, size_t size, bool is_mutable)
+	{
+		// get native encoding
+		xml_encoding wchar_encoding = get_wchar_encoding();
+
+		// fast path: no conversion required
+		if (encoding == wchar_encoding)
+			return get_mutable_buffer(out_buffer, out_length, contents, size, is_mutable);
+
+		// only endian-swapping is required
+		if (need_endian_swap_utf(encoding, wchar_encoding))
+			return convert_buffer_endian_swap(out_buffer, out_length, contents, size, is_mutable);
+
+		// source encoding is utf8
+		if (encoding == encoding_utf8)
+			return convert_buffer_generic(out_buffer, out_length, contents, size, utf8_decoder());
+
+		// source encoding is utf16
+		if (encoding == encoding_utf16_be || encoding == encoding_utf16_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+
+			return (native_encoding == encoding) ?
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf16_decoder<opt_false>()) :
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf16_decoder<opt_true>());
+		}
+
+		// source encoding is utf32
+		if (encoding == encoding_utf32_be || encoding == encoding_utf32_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+
+			return (native_encoding == encoding) ?
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf32_decoder<opt_false>()) :
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf32_decoder<opt_true>());
+		}
+
+		// source encoding is latin1
+		if (encoding == encoding_latin1)
+			return convert_buffer_generic(out_buffer, out_length, contents, size, latin1_decoder());
+
+		assert(false && "Invalid encoding");
+		return false;
+	}
+#else
+	template <typename D> PUGI__FN bool convert_buffer_generic(char_t*& out_buffer, size_t& out_length, const void* contents, size_t size, D)
+	{
+		const typename D::type* data = static_cast<const typename D::type*>(contents);
+		size_t data_length = size / sizeof(typename D::type);
+
+		// first pass: get length in utf8 units
+		size_t length = D::process(data, data_length, 0, utf8_counter());
+
+		// allocate buffer of suitable length
+		char_t* buffer = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+		if (!buffer) return false;
+
+		// second pass: convert utf16 input to utf8
+		uint8_t* obegin = reinterpret_cast<uint8_t*>(buffer);
+		uint8_t* oend = D::process(data, data_length, obegin, utf8_writer());
+
+		assert(oend == obegin + length);
+		*oend = 0;
+
+		out_buffer = buffer;
+		out_length = length + 1;
+
+		return true;
+	}
+
+	PUGI__FN size_t get_latin1_7bit_prefix_length(const uint8_t* data, size_t size)
+	{
+		for (size_t i = 0; i < size; ++i)
+			if (data[i] > 127)
+				return i;
+
+		return size;
+	}
+
+	PUGI__FN bool convert_buffer_latin1(char_t*& out_buffer, size_t& out_length, const void* contents, size_t size, bool is_mutable)
+	{
+		const uint8_t* data = static_cast<const uint8_t*>(contents);
+		size_t data_length = size;
+
+		// get size of prefix that does not need utf8 conversion
+		size_t prefix_length = get_latin1_7bit_prefix_length(data, data_length);
+		assert(prefix_length <= data_length);
+
+		const uint8_t* postfix = data + prefix_length;
+		size_t postfix_length = data_length - prefix_length;
+
+		// if no conversion is needed, just return the original buffer
+		if (postfix_length == 0) return get_mutable_buffer(out_buffer, out_length, contents, size, is_mutable);
+
+		// first pass: get length in utf8 units
+		size_t length = prefix_length + latin1_decoder::process(postfix, postfix_length, 0, utf8_counter());
+
+		// allocate buffer of suitable length
+		char_t* buffer = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+		if (!buffer) return false;
+
+		// second pass: convert latin1 input to utf8
+		memcpy(buffer, data, prefix_length);
+
+		uint8_t* obegin = reinterpret_cast<uint8_t*>(buffer);
+		uint8_t* oend = latin1_decoder::process(postfix, postfix_length, obegin + prefix_length, utf8_writer());
+
+		assert(oend == obegin + length);
+		*oend = 0;
+
+		out_buffer = buffer;
+		out_length = length + 1;
+
+		return true;
+	}
+
+	PUGI__FN bool convert_buffer(char_t*& out_buffer, size_t& out_length, xml_encoding encoding, const void* contents, size_t size, bool is_mutable)
+	{
+		// fast path: no conversion required
+		if (encoding == encoding_utf8)
+			return get_mutable_buffer(out_buffer, out_length, contents, size, is_mutable);
+
+		// source encoding is utf16
+		if (encoding == encoding_utf16_be || encoding == encoding_utf16_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+
+			return (native_encoding == encoding) ?
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf16_decoder<opt_false>()) :
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf16_decoder<opt_true>());
+		}
+
+		// source encoding is utf32
+		if (encoding == encoding_utf32_be || encoding == encoding_utf32_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+
+			return (native_encoding == encoding) ?
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf32_decoder<opt_false>()) :
+				convert_buffer_generic(out_buffer, out_length, contents, size, utf32_decoder<opt_true>());
+		}
+
+		// source encoding is latin1
+		if (encoding == encoding_latin1)
+			return convert_buffer_latin1(out_buffer, out_length, contents, size, is_mutable);
+
+		assert(false && "Invalid encoding");
+		return false;
+	}
+#endif
+
+	PUGI__FN size_t as_utf8_begin(const wchar_t* str, size_t length)
+	{
+		// get length in utf8 characters
+		return wchar_decoder::process(str, length, 0, utf8_counter());
+	}
+
+	PUGI__FN void as_utf8_end(char* buffer, size_t size, const wchar_t* str, size_t length)
+	{
+		// convert to utf8
+		uint8_t* begin = reinterpret_cast<uint8_t*>(buffer);
+		uint8_t* end = wchar_decoder::process(str, length, begin, utf8_writer());
+
+		assert(begin + size == end);
+		(void)!end;
+		(void)!size;
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN std::string as_utf8_impl(const wchar_t* str, size_t length)
+	{
+		// first pass: get length in utf8 characters
+		size_t size = as_utf8_begin(str, length);
+
+		// allocate resulting string
+		std::string result;
+		result.resize(size);
+
+		// second pass: convert to utf8
+		if (size > 0) as_utf8_end(&result[0], size, str, length);
+
+		return result;
+	}
+
+	PUGI__FN std::basic_string<wchar_t> as_wide_impl(const char* str, size_t size)
+	{
+		const uint8_t* data = reinterpret_cast<const uint8_t*>(str);
+
+		// first pass: get length in wchar_t units
+		size_t length = utf8_decoder::process(data, size, 0, wchar_counter());
+
+		// allocate resulting string
+		std::basic_string<wchar_t> result;
+		result.resize(length);
+
+		// second pass: convert to wchar_t
+		if (length > 0)
+		{
+			wchar_writer::value_type begin = reinterpret_cast<wchar_writer::value_type>(&result[0]);
+			wchar_writer::value_type end = utf8_decoder::process(data, size, begin, wchar_writer());
+
+			assert(begin + length == end);
+			(void)!end;
+		}
+
+		return result;
+	}
+#endif
+
+	template <typename Header>
+	inline bool strcpy_insitu_allow(size_t length, const Header& header, uintptr_t header_mask, char_t* target)
+	{
+		// never reuse shared memory
+		if (header & xml_memory_page_contents_shared_mask) return false;
+
+		size_t target_length = strlength(target);
+
+		// always reuse document buffer memory if possible
+		if ((header & header_mask) == 0) return target_length >= length;
+
+		// reuse heap memory if waste is not too great
+		const size_t reuse_threshold = 32;
+
+		return target_length >= length && (target_length < reuse_threshold || target_length - length < target_length / 2);
+	}
+
+	template <typename String, typename Header>
+	PUGI__FN bool strcpy_insitu(String& dest, Header& header, uintptr_t header_mask, const char_t* source, size_t source_length)
+	{
+		if (source_length == 0)
+		{
+			// empty string and null pointer are equivalent, so just deallocate old memory
+			xml_allocator* alloc = PUGI__GETPAGE_IMPL(header)->allocator;
+
+			if (header & header_mask) alloc->deallocate_string(dest);
+
+			// mark the string as not allocated
+			dest = 0;
+			header &= ~header_mask;
+
+			return true;
+		}
+		else if (dest && strcpy_insitu_allow(source_length, header, header_mask, dest))
+		{
+			// we can reuse old buffer, so just copy the new data (including zero terminator)
+			memcpy(dest, source, source_length * sizeof(char_t));
+			dest[source_length] = 0;
+
+			return true;
+		}
+		else
+		{
+			xml_allocator* alloc = PUGI__GETPAGE_IMPL(header)->allocator;
+
+			if (!alloc->reserve()) return false;
+
+			// allocate new buffer
+			char_t* buf = alloc->allocate_string(source_length + 1);
+			if (!buf) return false;
+
+			// copy the string (including zero terminator)
+			memcpy(buf, source, source_length * sizeof(char_t));
+			buf[source_length] = 0;
+
+			// deallocate old buffer (*after* the above to protect against overlapping memory and/or allocation failures)
+			if (header & header_mask) alloc->deallocate_string(dest);
+
+			// the string is now allocated, so set the flag
+			dest = buf;
+			header |= header_mask;
+
+			return true;
+		}
+	}
+
+	struct gap
+	{
+		char_t* end;
+		size_t size;
+
+		gap(): end(0), size(0)
+		{
+		}
+
+		// Push new gap, move s count bytes further (skipping the gap).
+		// Collapse previous gap.
+		void push(char_t*& s, size_t count)
+		{
+			if (end) // there was a gap already; collapse it
+			{
+				// Move [old_gap_end, new_gap_start) to [old_gap_start, ...)
+				assert(s >= end);
+				memmove(end - size, end, reinterpret_cast<char*>(s) - reinterpret_cast<char*>(end));
+			}
+
+			s += count; // end of current gap
+
+			// "merge" two gaps
+			end = s;
+			size += count;
+		}
+
+		// Collapse all gaps, return past-the-end pointer
+		char_t* flush(char_t* s)
+		{
+			if (end)
+			{
+				// Move [old_gap_end, current_pos) to [old_gap_start, ...)
+				assert(s >= end);
+				memmove(end - size, end, reinterpret_cast<char*>(s) - reinterpret_cast<char*>(end));
+
+				return s - size;
+			}
+			else return s;
+		}
+	};
+
+	PUGI__FN char_t* strconv_escape(char_t* s, gap& g)
+	{
+		char_t* stre = s + 1;
+
+		switch (*stre)
+		{
+			case '#':	// &#...
+			{
+				unsigned int ucsc = 0;
+
+				if (stre[1] == 'x') // &#x... (hex code)
+				{
+					stre += 2;
+
+					char_t ch = *stre;
+
+					if (ch == ';') return stre;
+
+					for (;;)
+					{
+						if (static_cast<unsigned int>(ch - '0') <= 9)
+							ucsc = 16 * ucsc + (ch - '0');
+						else if (static_cast<unsigned int>((ch | ' ') - 'a') <= 5)
+							ucsc = 16 * ucsc + ((ch | ' ') - 'a' + 10);
+						else if (ch == ';')
+							break;
+						else // cancel
+							return stre;
+
+						ch = *++stre;
+					}
+
+					++stre;
+				}
+				else	// &#... (dec code)
+				{
+					char_t ch = *++stre;
+
+					if (ch == ';') return stre;
+
+					for (;;)
+					{
+						if (static_cast<unsigned int>(static_cast<unsigned int>(ch) - '0') <= 9)
+							ucsc = 10 * ucsc + (ch - '0');
+						else if (ch == ';')
+							break;
+						else // cancel
+							return stre;
+
+						ch = *++stre;
+					}
+
+					++stre;
+				}
+
+			#ifdef PUGIXML_WCHAR_MODE
+				s = reinterpret_cast<char_t*>(wchar_writer::any(reinterpret_cast<wchar_writer::value_type>(s), ucsc));
+			#else
+				s = reinterpret_cast<char_t*>(utf8_writer::any(reinterpret_cast<uint8_t*>(s), ucsc));
+			#endif
+
+				g.push(s, stre - s);
+				return stre;
+			}
+
+			case 'a':	// &a
+			{
+				++stre;
+
+				if (*stre == 'm') // &am
+				{
+					if (*++stre == 'p' && *++stre == ';') // &amp;
+					{
+						*s++ = '&';
+						++stre;
+
+						g.push(s, stre - s);
+						return stre;
+					}
+				}
+				else if (*stre == 'p') // &ap
+				{
+					if (*++stre == 'o' && *++stre == 's' && *++stre == ';') // &apos;
+					{
+						*s++ = '\'';
+						++stre;
+
+						g.push(s, stre - s);
+						return stre;
+					}
+				}
+				break;
+			}
+
+			case 'g': // &g
+			{
+				if (*++stre == 't' && *++stre == ';') // &gt;
+				{
+					*s++ = '>';
+					++stre;
+
+					g.push(s, stre - s);
+					return stre;
+				}
+				break;
+			}
+
+			case 'l': // &l
+			{
+				if (*++stre == 't' && *++stre == ';') // &lt;
+				{
+					*s++ = '<';
+					++stre;
+
+					g.push(s, stre - s);
+					return stre;
+				}
+				break;
+			}
+
+			case 'q': // &q
+			{
+				if (*++stre == 'u' && *++stre == 'o' && *++stre == 't' && *++stre == ';') // &quot;
+				{
+					*s++ = '"';
+					++stre;
+
+					g.push(s, stre - s);
+					return stre;
+				}
+				break;
+			}
+
+			default:
+				break;
+		}
+
+		return stre;
+	}
+
+	// Parser utilities
+	#define PUGI__ENDSWITH(c, e)        ((c) == (e) || ((c) == 0 && endch == (e)))
+	#define PUGI__SKIPWS()              { while (PUGI__IS_CHARTYPE(*s, ct_space)) ++s; }
+	#define PUGI__OPTSET(OPT)           ( optmsk & (OPT) )
+	#define PUGI__PUSHNODE(TYPE)        { cursor = append_new_node(cursor, *alloc, TYPE); if (!cursor) PUGI__THROW_ERROR(status_out_of_memory, s); }
+	#define PUGI__POPNODE()             { cursor = cursor->parent; }
+	#define PUGI__SCANFOR(X)            { while (*s != 0 && !(X)) ++s; }
+	#define PUGI__SCANWHILE(X)          { while (X) ++s; }
+	#define PUGI__SCANWHILE_UNROLL(X)   { for (;;) { char_t ss = s[0]; if (PUGI__UNLIKELY(!(X))) { break; } ss = s[1]; if (PUGI__UNLIKELY(!(X))) { s += 1; break; } ss = s[2]; if (PUGI__UNLIKELY(!(X))) { s += 2; break; } ss = s[3]; if (PUGI__UNLIKELY(!(X))) { s += 3; break; } s += 4; } }
+	#define PUGI__ENDSEG()              { ch = *s; *s = 0; ++s; }
+	#define PUGI__THROW_ERROR(err, m)   return error_offset = m, error_status = err, static_cast<char_t*>(0)
+	#define PUGI__CHECK_ERROR(err, m)   { if (*s == 0) PUGI__THROW_ERROR(err, m); }
+
+	PUGI__FN char_t* strconv_comment(char_t* s, char_t endch)
+	{
+		gap g;
+
+		while (true)
+		{
+			PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_comment));
+
+			if (*s == '\r') // Either a single 0x0d or 0x0d 0x0a pair
+			{
+				*s++ = '\n'; // replace first one with 0x0a
+
+				if (*s == '\n') g.push(s, 1);
+			}
+			else if (s[0] == '-' && s[1] == '-' && PUGI__ENDSWITH(s[2], '>')) // comment ends here
+			{
+				*g.flush(s) = 0;
+
+				return s + (s[2] == '>' ? 3 : 2);
+			}
+			else if (*s == 0)
+			{
+				return 0;
+			}
+			else ++s;
+		}
+	}
+
+	PUGI__FN char_t* strconv_cdata(char_t* s, char_t endch)
+	{
+		gap g;
+
+		while (true)
+		{
+			PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_cdata));
+
+			if (*s == '\r') // Either a single 0x0d or 0x0d 0x0a pair
+			{
+				*s++ = '\n'; // replace first one with 0x0a
+
+				if (*s == '\n') g.push(s, 1);
+			}
+			else if (s[0] == ']' && s[1] == ']' && PUGI__ENDSWITH(s[2], '>')) // CDATA ends here
+			{
+				*g.flush(s) = 0;
+
+				return s + 1;
+			}
+			else if (*s == 0)
+			{
+				return 0;
+			}
+			else ++s;
+		}
+	}
+
+	typedef char_t* (*strconv_pcdata_t)(char_t*);
+
+	template <typename opt_trim, typename opt_eol, typename opt_escape> struct strconv_pcdata_impl
+	{
+		static char_t* parse(char_t* s)
+		{
+			gap g;
+
+			char_t* begin = s;
+
+			while (true)
+			{
+				PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_pcdata));
+
+				if (*s == '<') // PCDATA ends here
+				{
+					char_t* end = g.flush(s);
+
+					if (opt_trim::value)
+						while (end > begin && PUGI__IS_CHARTYPE(end[-1], ct_space))
+							--end;
+
+					*end = 0;
+
+					return s + 1;
+				}
+				else if (opt_eol::value && *s == '\r') // Either a single 0x0d or 0x0d 0x0a pair
+				{
+					*s++ = '\n'; // replace first one with 0x0a
+
+					if (*s == '\n') g.push(s, 1);
+				}
+				else if (opt_escape::value && *s == '&')
+				{
+					s = strconv_escape(s, g);
+				}
+				else if (*s == 0)
+				{
+					char_t* end = g.flush(s);
+
+					if (opt_trim::value)
+						while (end > begin && PUGI__IS_CHARTYPE(end[-1], ct_space))
+							--end;
+
+					*end = 0;
+
+					return s;
+				}
+				else ++s;
+			}
+		}
+	};
+
+	PUGI__FN strconv_pcdata_t get_strconv_pcdata(unsigned int optmask)
+	{
+		PUGI__STATIC_ASSERT(parse_escapes == 0x10 && parse_eol == 0x20 && parse_trim_pcdata == 0x0800);
+
+		switch (((optmask >> 4) & 3) | ((optmask >> 9) & 4)) // get bitmask for flags (eol escapes trim)
+		{
+		case 0: return strconv_pcdata_impl<opt_false, opt_false, opt_false>::parse;
+		case 1: return strconv_pcdata_impl<opt_false, opt_false, opt_true>::parse;
+		case 2: return strconv_pcdata_impl<opt_false, opt_true, opt_false>::parse;
+		case 3: return strconv_pcdata_impl<opt_false, opt_true, opt_true>::parse;
+		case 4: return strconv_pcdata_impl<opt_true, opt_false, opt_false>::parse;
+		case 5: return strconv_pcdata_impl<opt_true, opt_false, opt_true>::parse;
+		case 6: return strconv_pcdata_impl<opt_true, opt_true, opt_false>::parse;
+		case 7: return strconv_pcdata_impl<opt_true, opt_true, opt_true>::parse;
+		default: assert(false); return 0; // should not get here
+		}
+	}
+
+	typedef char_t* (*strconv_attribute_t)(char_t*, char_t);
+
+	template <typename opt_escape> struct strconv_attribute_impl
+	{
+		static char_t* parse_wnorm(char_t* s, char_t end_quote)
+		{
+			gap g;
+
+			// trim leading whitespaces
+			if (PUGI__IS_CHARTYPE(*s, ct_space))
+			{
+				char_t* str = s;
+
+				do ++str;
+				while (PUGI__IS_CHARTYPE(*str, ct_space));
+
+				g.push(s, str - s);
+			}
+
+			while (true)
+			{
+				PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr_ws | ct_space));
+
+				if (*s == end_quote)
+				{
+					char_t* str = g.flush(s);
+
+					do *str-- = 0;
+					while (PUGI__IS_CHARTYPE(*str, ct_space));
+
+					return s + 1;
+				}
+				else if (PUGI__IS_CHARTYPE(*s, ct_space))
+				{
+					*s++ = ' ';
+
+					if (PUGI__IS_CHARTYPE(*s, ct_space))
+					{
+						char_t* str = s + 1;
+						while (PUGI__IS_CHARTYPE(*str, ct_space)) ++str;
+
+						g.push(s, str - s);
+					}
+				}
+				else if (opt_escape::value && *s == '&')
+				{
+					s = strconv_escape(s, g);
+				}
+				else if (!*s)
+				{
+					return 0;
+				}
+				else ++s;
+			}
+		}
+
+		static char_t* parse_wconv(char_t* s, char_t end_quote)
+		{
+			gap g;
+
+			while (true)
+			{
+				PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr_ws));
+
+				if (*s == end_quote)
+				{
+					*g.flush(s) = 0;
+
+					return s + 1;
+				}
+				else if (PUGI__IS_CHARTYPE(*s, ct_space))
+				{
+					if (*s == '\r')
+					{
+						*s++ = ' ';
+
+						if (*s == '\n') g.push(s, 1);
+					}
+					else *s++ = ' ';
+				}
+				else if (opt_escape::value && *s == '&')
+				{
+					s = strconv_escape(s, g);
+				}
+				else if (!*s)
+				{
+					return 0;
+				}
+				else ++s;
+			}
+		}
+
+		static char_t* parse_eol(char_t* s, char_t end_quote)
+		{
+			gap g;
+
+			while (true)
+			{
+				PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr));
+
+				if (*s == end_quote)
+				{
+					*g.flush(s) = 0;
+
+					return s + 1;
+				}
+				else if (*s == '\r')
+				{
+					*s++ = '\n';
+
+					if (*s == '\n') g.push(s, 1);
+				}
+				else if (opt_escape::value && *s == '&')
+				{
+					s = strconv_escape(s, g);
+				}
+				else if (!*s)
+				{
+					return 0;
+				}
+				else ++s;
+			}
+		}
+
+		static char_t* parse_simple(char_t* s, char_t end_quote)
+		{
+			gap g;
+
+			while (true)
+			{
+				PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr));
+
+				if (*s == end_quote)
+				{
+					*g.flush(s) = 0;
+
+					return s + 1;
+				}
+				else if (opt_escape::value && *s == '&')
+				{
+					s = strconv_escape(s, g);
+				}
+				else if (!*s)
+				{
+					return 0;
+				}
+				else ++s;
+			}
+		}
+	};
+
+	PUGI__FN strconv_attribute_t get_strconv_attribute(unsigned int optmask)
+	{
+		PUGI__STATIC_ASSERT(parse_escapes == 0x10 && parse_eol == 0x20 && parse_wconv_attribute == 0x40 && parse_wnorm_attribute == 0x80);
+
+		switch ((optmask >> 4) & 15) // get bitmask for flags (wconv wnorm eol escapes)
+		{
+		case 0:  return strconv_attribute_impl<opt_false>::parse_simple;
+		case 1:  return strconv_attribute_impl<opt_true>::parse_simple;
+		case 2:  return strconv_attribute_impl<opt_false>::parse_eol;
+		case 3:  return strconv_attribute_impl<opt_true>::parse_eol;
+		case 4:  return strconv_attribute_impl<opt_false>::parse_wconv;
+		case 5:  return strconv_attribute_impl<opt_true>::parse_wconv;
+		case 6:  return strconv_attribute_impl<opt_false>::parse_wconv;
+		case 7:  return strconv_attribute_impl<opt_true>::parse_wconv;
+		case 8:  return strconv_attribute_impl<opt_false>::parse_wnorm;
+		case 9:  return strconv_attribute_impl<opt_true>::parse_wnorm;
+		case 10: return strconv_attribute_impl<opt_false>::parse_wnorm;
+		case 11: return strconv_attribute_impl<opt_true>::parse_wnorm;
+		case 12: return strconv_attribute_impl<opt_false>::parse_wnorm;
+		case 13: return strconv_attribute_impl<opt_true>::parse_wnorm;
+		case 14: return strconv_attribute_impl<opt_false>::parse_wnorm;
+		case 15: return strconv_attribute_impl<opt_true>::parse_wnorm;
+		default: assert(false); return 0; // should not get here
+		}
+	}
+
+	inline xml_parse_result make_parse_result(xml_parse_status status, ptrdiff_t offset = 0)
+	{
+		xml_parse_result result;
+		result.status = status;
+		result.offset = offset;
+
+		return result;
+	}
+
+	struct xml_parser
+	{
+		xml_allocator* alloc;
+		char_t* error_offset;
+		xml_parse_status error_status;
+
+		xml_parser(xml_allocator* alloc_): alloc(alloc_), error_offset(0), error_status(status_ok)
+		{
+		}
+
+		// DOCTYPE consists of nested sections of the following possible types:
+		// <!-- ... -->, <? ... ?>, "...", '...'
+		// <![...]]>
+		// <!...>
+		// First group can not contain nested groups
+		// Second group can contain nested groups of the same type
+		// Third group can contain all other groups
+		char_t* parse_doctype_primitive(char_t* s)
+		{
+			if (*s == '"' || *s == '\'')
+			{
+				// quoted string
+				char_t ch = *s++;
+				PUGI__SCANFOR(*s == ch);
+				if (!*s) PUGI__THROW_ERROR(status_bad_doctype, s);
+
+				s++;
+			}
+			else if (s[0] == '<' && s[1] == '?')
+			{
+				// <? ... ?>
+				s += 2;
+				PUGI__SCANFOR(s[0] == '?' && s[1] == '>'); // no need for ENDSWITH because ?> can't terminate proper doctype
+				if (!*s) PUGI__THROW_ERROR(status_bad_doctype, s);
+
+				s += 2;
+			}
+			else if (s[0] == '<' && s[1] == '!' && s[2] == '-' && s[3] == '-')
+			{
+				s += 4;
+				PUGI__SCANFOR(s[0] == '-' && s[1] == '-' && s[2] == '>'); // no need for ENDSWITH because --> can't terminate proper doctype
+				if (!*s) PUGI__THROW_ERROR(status_bad_doctype, s);
+
+				s += 3;
+			}
+			else PUGI__THROW_ERROR(status_bad_doctype, s);
+
+			return s;
+		}
+
+		char_t* parse_doctype_ignore(char_t* s)
+		{
+			size_t depth = 0;
+
+			assert(s[0] == '<' && s[1] == '!' && s[2] == '[');
+			s += 3;
+
+			while (*s)
+			{
+				if (s[0] == '<' && s[1] == '!' && s[2] == '[')
+				{
+					// nested ignore section
+					s += 3;
+					depth++;
+				}
+				else if (s[0] == ']' && s[1] == ']' && s[2] == '>')
+				{
+					// ignore section end
+					s += 3;
+
+					if (depth == 0)
+						return s;
+
+					depth--;
+				}
+				else s++;
+			}
+
+			PUGI__THROW_ERROR(status_bad_doctype, s);
+		}
+
+		char_t* parse_doctype_group(char_t* s, char_t endch)
+		{
+			size_t depth = 0;
+
+			assert((s[0] == '<' || s[0] == 0) && s[1] == '!');
+			s += 2;
+
+			while (*s)
+			{
+				if (s[0] == '<' && s[1] == '!' && s[2] != '-')
+				{
+					if (s[2] == '[')
+					{
+						// ignore
+						s = parse_doctype_ignore(s);
+						if (!s) return s;
+					}
+					else
+					{
+						// some control group
+						s += 2;
+						depth++;
+					}
+				}
+				else if (s[0] == '<' || s[0] == '"' || s[0] == '\'')
+				{
+					// unknown tag (forbidden), or some primitive group
+					s = parse_doctype_primitive(s);
+					if (!s) return s;
+				}
+				else if (*s == '>')
+				{
+					if (depth == 0)
+						return s;
+
+					depth--;
+					s++;
+				}
+				else s++;
+			}
+
+			if (depth != 0 || endch != '>') PUGI__THROW_ERROR(status_bad_doctype, s);
+
+			return s;
+		}
+
+		char_t* parse_exclamation(char_t* s, xml_node_struct* cursor, unsigned int optmsk, char_t endch)
+		{
+			// parse node contents, starting with exclamation mark
+			++s;
+
+			if (*s == '-') // '<!-...'
+			{
+				++s;
+
+				if (*s == '-') // '<!--...'
+				{
+					++s;
+
+					if (PUGI__OPTSET(parse_comments))
+					{
+						PUGI__PUSHNODE(node_comment); // Append a new node on the tree.
+						cursor->value = s; // Save the offset.
+					}
+
+					if (PUGI__OPTSET(parse_eol) && PUGI__OPTSET(parse_comments))
+					{
+						s = strconv_comment(s, endch);
+
+						if (!s) PUGI__THROW_ERROR(status_bad_comment, cursor->value);
+					}
+					else
+					{
+						// Scan for terminating '-->'.
+						PUGI__SCANFOR(s[0] == '-' && s[1] == '-' && PUGI__ENDSWITH(s[2], '>'));
+						PUGI__CHECK_ERROR(status_bad_comment, s);
+
+						if (PUGI__OPTSET(parse_comments))
+							*s = 0; // Zero-terminate this segment at the first terminating '-'.
+
+						s += (s[2] == '>' ? 3 : 2); // Step over the '\0->'.
+					}
+				}
+				else PUGI__THROW_ERROR(status_bad_comment, s);
+			}
+			else if (*s == '[')
+			{
+				// '<![CDATA[...'
+				if (*++s=='C' && *++s=='D' && *++s=='A' && *++s=='T' && *++s=='A' && *++s == '[')
+				{
+					++s;
+
+					if (PUGI__OPTSET(parse_cdata))
+					{
+						PUGI__PUSHNODE(node_cdata); // Append a new node on the tree.
+						cursor->value = s; // Save the offset.
+
+						if (PUGI__OPTSET(parse_eol))
+						{
+							s = strconv_cdata(s, endch);
+
+							if (!s) PUGI__THROW_ERROR(status_bad_cdata, cursor->value);
+						}
+						else
+						{
+							// Scan for terminating ']]>'.
+							PUGI__SCANFOR(s[0] == ']' && s[1] == ']' && PUGI__ENDSWITH(s[2], '>'));
+							PUGI__CHECK_ERROR(status_bad_cdata, s);
+
+							*s++ = 0; // Zero-terminate this segment.
+						}
+					}
+					else // Flagged for discard, but we still have to scan for the terminator.
+					{
+						// Scan for terminating ']]>'.
+						PUGI__SCANFOR(s[0] == ']' && s[1] == ']' && PUGI__ENDSWITH(s[2], '>'));
+						PUGI__CHECK_ERROR(status_bad_cdata, s);
+
+						++s;
+					}
+
+					s += (s[1] == '>' ? 2 : 1); // Step over the last ']>'.
+				}
+				else PUGI__THROW_ERROR(status_bad_cdata, s);
+			}
+			else if (s[0] == 'D' && s[1] == 'O' && s[2] == 'C' && s[3] == 'T' && s[4] == 'Y' && s[5] == 'P' && PUGI__ENDSWITH(s[6], 'E'))
+			{
+				s -= 2;
+
+				if (cursor->parent) PUGI__THROW_ERROR(status_bad_doctype, s);
+
+				char_t* mark = s + 9;
+
+				s = parse_doctype_group(s, endch);
+				if (!s) return s;
+
+				assert((*s == 0 && endch == '>') || *s == '>');
+				if (*s) *s++ = 0;
+
+				if (PUGI__OPTSET(parse_doctype))
+				{
+					while (PUGI__IS_CHARTYPE(*mark, ct_space)) ++mark;
+
+					PUGI__PUSHNODE(node_doctype);
+
+					cursor->value = mark;
+				}
+			}
+			else if (*s == 0 && endch == '-') PUGI__THROW_ERROR(status_bad_comment, s);
+			else if (*s == 0 && endch == '[') PUGI__THROW_ERROR(status_bad_cdata, s);
+			else PUGI__THROW_ERROR(status_unrecognized_tag, s);
+
+			return s;
+		}
+
+		char_t* parse_question(char_t* s, xml_node_struct*& ref_cursor, unsigned int optmsk, char_t endch)
+		{
+			// load into registers
+			xml_node_struct* cursor = ref_cursor;
+			char_t ch = 0;
+
+			// parse node contents, starting with question mark
+			++s;
+
+			// read PI target
+			char_t* target = s;
+
+			if (!PUGI__IS_CHARTYPE(*s, ct_start_symbol)) PUGI__THROW_ERROR(status_bad_pi, s);
+
+			PUGI__SCANWHILE(PUGI__IS_CHARTYPE(*s, ct_symbol));
+			PUGI__CHECK_ERROR(status_bad_pi, s);
+
+			// determine node type; stricmp / strcasecmp is not portable
+			bool declaration = (target[0] | ' ') == 'x' && (target[1] | ' ') == 'm' && (target[2] | ' ') == 'l' && target + 3 == s;
+
+			if (declaration ? PUGI__OPTSET(parse_declaration) : PUGI__OPTSET(parse_pi))
+			{
+				if (declaration)
+				{
+					// disallow non top-level declarations
+					if (cursor->parent) PUGI__THROW_ERROR(status_bad_pi, s);
+
+					PUGI__PUSHNODE(node_declaration);
+				}
+				else
+				{
+					PUGI__PUSHNODE(node_pi);
+				}
+
+				cursor->name = target;
+
+				PUGI__ENDSEG();
+
+				// parse value/attributes
+				if (ch == '?')
+				{
+					// empty node
+					if (!PUGI__ENDSWITH(*s, '>')) PUGI__THROW_ERROR(status_bad_pi, s);
+					s += (*s == '>');
+
+					PUGI__POPNODE();
+				}
+				else if (PUGI__IS_CHARTYPE(ch, ct_space))
+				{
+					PUGI__SKIPWS();
+
+					// scan for tag end
+					char_t* value = s;
+
+					PUGI__SCANFOR(s[0] == '?' && PUGI__ENDSWITH(s[1], '>'));
+					PUGI__CHECK_ERROR(status_bad_pi, s);
+
+					if (declaration)
+					{
+						// replace ending ? with / so that 'element' terminates properly
+						*s = '/';
+
+						// we exit from this function with cursor at node_declaration, which is a signal to parse() to go to LOC_ATTRIBUTES
+						s = value;
+					}
+					else
+					{
+						// store value and step over >
+						cursor->value = value;
+
+						PUGI__POPNODE();
+
+						PUGI__ENDSEG();
+
+						s += (*s == '>');
+					}
+				}
+				else PUGI__THROW_ERROR(status_bad_pi, s);
+			}
+			else
+			{
+				// scan for tag end
+				PUGI__SCANFOR(s[0] == '?' && PUGI__ENDSWITH(s[1], '>'));
+				PUGI__CHECK_ERROR(status_bad_pi, s);
+
+				s += (s[1] == '>' ? 2 : 1);
+			}
+
+			// store from registers
+			ref_cursor = cursor;
+
+			return s;
+		}
+
+		char_t* parse_tree(char_t* s, xml_node_struct* root, unsigned int optmsk, char_t endch)
+		{
+			strconv_attribute_t strconv_attribute = get_strconv_attribute(optmsk);
+			strconv_pcdata_t strconv_pcdata = get_strconv_pcdata(optmsk);
+
+			char_t ch = 0;
+			xml_node_struct* cursor = root;
+			char_t* mark = s;
+
+			while (*s != 0)
+			{
+				if (*s == '<')
+				{
+					++s;
+
+				LOC_TAG:
+					if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) // '<#...'
+					{
+						PUGI__PUSHNODE(node_element); // Append a new node to the tree.
+
+						cursor->name = s;
+
+						PUGI__SCANWHILE_UNROLL(PUGI__IS_CHARTYPE(ss, ct_symbol)); // Scan for a terminator.
+						PUGI__ENDSEG(); // Save char in 'ch', terminate & step over.
+
+						if (ch == '>')
+						{
+							// end of tag
+						}
+						else if (PUGI__IS_CHARTYPE(ch, ct_space))
+						{
+						LOC_ATTRIBUTES:
+							while (true)
+							{
+								PUGI__SKIPWS(); // Eat any whitespace.
+
+								if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) // <... #...
+								{
+									xml_attribute_struct* a = append_new_attribute(cursor, *alloc); // Make space for this attribute.
+									if (!a) PUGI__THROW_ERROR(status_out_of_memory, s);
+
+									a->name = s; // Save the offset.
+
+									PUGI__SCANWHILE_UNROLL(PUGI__IS_CHARTYPE(ss, ct_symbol)); // Scan for a terminator.
+									PUGI__ENDSEG(); // Save char in 'ch', terminate & step over.
+
+									if (PUGI__IS_CHARTYPE(ch, ct_space))
+									{
+										PUGI__SKIPWS(); // Eat any whitespace.
+
+										ch = *s;
+										++s;
+									}
+
+									if (ch == '=') // '<... #=...'
+									{
+										PUGI__SKIPWS(); // Eat any whitespace.
+
+										if (*s == '"' || *s == '\'') // '<... #="...'
+										{
+											ch = *s; // Save quote char to avoid breaking on "''" -or- '""'.
+											++s; // Step over the quote.
+											a->value = s; // Save the offset.
+
+											s = strconv_attribute(s, ch);
+
+											if (!s) PUGI__THROW_ERROR(status_bad_attribute, a->value);
+
+											// After this line the loop continues from the start;
+											// Whitespaces, / and > are ok, symbols and EOF are wrong,
+											// everything else will be detected
+											if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) PUGI__THROW_ERROR(status_bad_attribute, s);
+										}
+										else PUGI__THROW_ERROR(status_bad_attribute, s);
+									}
+									else PUGI__THROW_ERROR(status_bad_attribute, s);
+								}
+								else if (*s == '/')
+								{
+									++s;
+
+									if (*s == '>')
+									{
+										PUGI__POPNODE();
+										s++;
+										break;
+									}
+									else if (*s == 0 && endch == '>')
+									{
+										PUGI__POPNODE();
+										break;
+									}
+									else PUGI__THROW_ERROR(status_bad_start_element, s);
+								}
+								else if (*s == '>')
+								{
+									++s;
+
+									break;
+								}
+								else if (*s == 0 && endch == '>')
+								{
+									break;
+								}
+								else PUGI__THROW_ERROR(status_bad_start_element, s);
+							}
+
+							// !!!
+						}
+						else if (ch == '/') // '<#.../'
+						{
+							if (!PUGI__ENDSWITH(*s, '>')) PUGI__THROW_ERROR(status_bad_start_element, s);
+
+							PUGI__POPNODE(); // Pop.
+
+							s += (*s == '>');
+						}
+						else if (ch == 0)
+						{
+							// we stepped over null terminator, backtrack & handle closing tag
+							--s;
+
+							if (endch != '>') PUGI__THROW_ERROR(status_bad_start_element, s);
+						}
+						else PUGI__THROW_ERROR(status_bad_start_element, s);
+					}
+					else if (*s == '/')
+					{
+						++s;
+
+						mark = s;
+
+						char_t* name = cursor->name;
+						if (!name) PUGI__THROW_ERROR(status_end_element_mismatch, mark);
+
+						while (PUGI__IS_CHARTYPE(*s, ct_symbol))
+						{
+							if (*s++ != *name++) PUGI__THROW_ERROR(status_end_element_mismatch, mark);
+						}
+
+						if (*name)
+						{
+							if (*s == 0 && name[0] == endch && name[1] == 0) PUGI__THROW_ERROR(status_bad_end_element, s);
+							else PUGI__THROW_ERROR(status_end_element_mismatch, mark);
+						}
+
+						PUGI__POPNODE(); // Pop.
+
+						PUGI__SKIPWS();
+
+						if (*s == 0)
+						{
+							if (endch != '>') PUGI__THROW_ERROR(status_bad_end_element, s);
+						}
+						else
+						{
+							if (*s != '>') PUGI__THROW_ERROR(status_bad_end_element, s);
+							++s;
+						}
+					}
+					else if (*s == '?') // '<?...'
+					{
+						s = parse_question(s, cursor, optmsk, endch);
+						if (!s) return s;
+
+						assert(cursor);
+						if (PUGI__NODETYPE(cursor) == node_declaration) goto LOC_ATTRIBUTES;
+					}
+					else if (*s == '!') // '<!...'
+					{
+						s = parse_exclamation(s, cursor, optmsk, endch);
+						if (!s) return s;
+					}
+					else if (*s == 0 && endch == '?') PUGI__THROW_ERROR(status_bad_pi, s);
+					else PUGI__THROW_ERROR(status_unrecognized_tag, s);
+				}
+				else
+				{
+					mark = s; // Save this offset while searching for a terminator.
+
+					PUGI__SKIPWS(); // Eat whitespace if no genuine PCDATA here.
+
+					if (*s == '<' || !*s)
+					{
+						// We skipped some whitespace characters because otherwise we would take the tag branch instead of PCDATA one
+						assert(mark != s);
+
+						if (!PUGI__OPTSET(parse_ws_pcdata | parse_ws_pcdata_single) || PUGI__OPTSET(parse_trim_pcdata))
+						{
+							continue;
+						}
+						else if (PUGI__OPTSET(parse_ws_pcdata_single))
+						{
+							if (s[0] != '<' || s[1] != '/' || cursor->first_child) continue;
+						}
+					}
+
+					if (!PUGI__OPTSET(parse_trim_pcdata))
+						s = mark;
+
+					if (cursor->parent || PUGI__OPTSET(parse_fragment))
+					{
+						if (PUGI__OPTSET(parse_embed_pcdata) && cursor->parent && !cursor->first_child && !cursor->value)
+						{
+							cursor->value = s; // Save the offset.
+						}
+						else
+						{
+							PUGI__PUSHNODE(node_pcdata); // Append a new node on the tree.
+
+							cursor->value = s; // Save the offset.
+
+							PUGI__POPNODE(); // Pop since this is a standalone.
+						}
+
+						s = strconv_pcdata(s);
+
+						if (!*s) break;
+					}
+					else
+					{
+						PUGI__SCANFOR(*s == '<'); // '...<'
+						if (!*s) break;
+
+						++s;
+					}
+
+					// We're after '<'
+					goto LOC_TAG;
+				}
+			}
+
+			// check that last tag is closed
+			if (cursor != root) PUGI__THROW_ERROR(status_end_element_mismatch, s);
+
+			return s;
+		}
+
+	#ifdef PUGIXML_WCHAR_MODE
+		static char_t* parse_skip_bom(char_t* s)
+		{
+			unsigned int bom = 0xfeff;
+			return (s[0] == static_cast<wchar_t>(bom)) ? s + 1 : s;
+		}
+	#else
+		static char_t* parse_skip_bom(char_t* s)
+		{
+			return (s[0] == '\xef' && s[1] == '\xbb' && s[2] == '\xbf') ? s + 3 : s;
+		}
+	#endif
+
+		static bool has_element_node_siblings(xml_node_struct* node)
+		{
+			while (node)
+			{
+				if (PUGI__NODETYPE(node) == node_element) return true;
+
+				node = node->next_sibling;
+			}
+
+			return false;
+		}
+
+		static xml_parse_result parse(char_t* buffer, size_t length, xml_document_struct* xmldoc, xml_node_struct* root, unsigned int optmsk)
+		{
+			// early-out for empty documents
+			if (length == 0)
+				return make_parse_result(PUGI__OPTSET(parse_fragment) ? status_ok : status_no_document_element);
+
+			// get last child of the root before parsing
+			xml_node_struct* last_root_child = root->first_child ? root->first_child->prev_sibling_c + 0 : 0;
+
+			// create parser on stack
+			xml_parser parser(static_cast<xml_allocator*>(xmldoc));
+
+			// save last character and make buffer zero-terminated (speeds up parsing)
+			char_t endch = buffer[length - 1];
+			buffer[length - 1] = 0;
+
+			// skip BOM to make sure it does not end up as part of parse output
+			char_t* buffer_data = parse_skip_bom(buffer);
+
+			// perform actual parsing
+			parser.parse_tree(buffer_data, root, optmsk, endch);
+
+			xml_parse_result result = make_parse_result(parser.error_status, parser.error_offset ? parser.error_offset - buffer : 0);
+			assert(result.offset >= 0 && static_cast<size_t>(result.offset) <= length);
+
+			if (result)
+			{
+				// since we removed last character, we have to handle the only possible false positive (stray <)
+				if (endch == '<')
+					return make_parse_result(status_unrecognized_tag, length - 1);
+
+				// check if there are any element nodes parsed
+				xml_node_struct* first_root_child_parsed = last_root_child ? last_root_child->next_sibling + 0 : root->first_child+ 0;
+
+				if (!PUGI__OPTSET(parse_fragment) && !has_element_node_siblings(first_root_child_parsed))
+					return make_parse_result(status_no_document_element, length - 1);
+			}
+			else
+			{
+				// roll back offset if it occurs on a null terminator in the source buffer
+				if (result.offset > 0 && static_cast<size_t>(result.offset) == length - 1 && endch == 0)
+					result.offset--;
+			}
+
+			return result;
+		}
+	};
+
+	// Output facilities
+	PUGI__FN xml_encoding get_write_native_encoding()
+	{
+	#ifdef PUGIXML_WCHAR_MODE
+		return get_wchar_encoding();
+	#else
+		return encoding_utf8;
+	#endif
+	}
+
+	PUGI__FN xml_encoding get_write_encoding(xml_encoding encoding)
+	{
+		// replace wchar encoding with utf implementation
+		if (encoding == encoding_wchar) return get_wchar_encoding();
+
+		// replace utf16 encoding with utf16 with specific endianness
+		if (encoding == encoding_utf16) return is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+
+		// replace utf32 encoding with utf32 with specific endianness
+		if (encoding == encoding_utf32) return is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+
+		// only do autodetection if no explicit encoding is requested
+		if (encoding != encoding_auto) return encoding;
+
+		// assume utf8 encoding
+		return encoding_utf8;
+	}
+
+	template <typename D, typename T> PUGI__FN size_t convert_buffer_output_generic(typename T::value_type dest, const char_t* data, size_t length, D, T)
+	{
+		PUGI__STATIC_ASSERT(sizeof(char_t) == sizeof(typename D::type));
+
+		typename T::value_type end = D::process(reinterpret_cast<const typename D::type*>(data), length, dest, T());
+
+		return static_cast<size_t>(end - dest) * sizeof(*dest);
+	}
+
+	template <typename D, typename T> PUGI__FN size_t convert_buffer_output_generic(typename T::value_type dest, const char_t* data, size_t length, D, T, bool opt_swap)
+	{
+		PUGI__STATIC_ASSERT(sizeof(char_t) == sizeof(typename D::type));
+
+		typename T::value_type end = D::process(reinterpret_cast<const typename D::type*>(data), length, dest, T());
+
+		if (opt_swap)
+		{
+			for (typename T::value_type i = dest; i != end; ++i)
+				*i = endian_swap(*i);
+		}
+
+		return static_cast<size_t>(end - dest) * sizeof(*dest);
+	}
+
+#ifdef PUGIXML_WCHAR_MODE
+	PUGI__FN size_t get_valid_length(const char_t* data, size_t length)
+	{
+		if (length < 1) return 0;
+
+		// discard last character if it's the lead of a surrogate pair
+		return (sizeof(wchar_t) == 2 && static_cast<unsigned int>(static_cast<uint16_t>(data[length - 1]) - 0xD800) < 0x400) ? length - 1 : length;
+	}
+
+	PUGI__FN size_t convert_buffer_output(char_t* r_char, uint8_t* r_u8, uint16_t* r_u16, uint32_t* r_u32, const char_t* data, size_t length, xml_encoding encoding)
+	{
+		// only endian-swapping is required
+		if (need_endian_swap_utf(encoding, get_wchar_encoding()))
+		{
+			convert_wchar_endian_swap(r_char, data, length);
+
+			return length * sizeof(char_t);
+		}
+
+		// convert to utf8
+		if (encoding == encoding_utf8)
+			return convert_buffer_output_generic(r_u8, data, length, wchar_decoder(), utf8_writer());
+
+		// convert to utf16
+		if (encoding == encoding_utf16_be || encoding == encoding_utf16_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+
+			return convert_buffer_output_generic(r_u16, data, length, wchar_decoder(), utf16_writer(), native_encoding != encoding);
+		}
+
+		// convert to utf32
+		if (encoding == encoding_utf32_be || encoding == encoding_utf32_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+
+			return convert_buffer_output_generic(r_u32, data, length, wchar_decoder(), utf32_writer(), native_encoding != encoding);
+		}
+
+		// convert to latin1
+		if (encoding == encoding_latin1)
+			return convert_buffer_output_generic(r_u8, data, length, wchar_decoder(), latin1_writer());
+
+		assert(false && "Invalid encoding");
+		return 0;
+	}
+#else
+	PUGI__FN size_t get_valid_length(const char_t* data, size_t length)
+	{
+		if (length < 5) return 0;
+
+		for (size_t i = 1; i <= 4; ++i)
+		{
+			uint8_t ch = static_cast<uint8_t>(data[length - i]);
+
+			// either a standalone character or a leading one
+			if ((ch & 0xc0) != 0x80) return length - i;
+		}
+
+		// there are four non-leading characters at the end, sequence tail is broken so might as well process the whole chunk
+		return length;
+	}
+
+	PUGI__FN size_t convert_buffer_output(char_t* /* r_char */, uint8_t* r_u8, uint16_t* r_u16, uint32_t* r_u32, const char_t* data, size_t length, xml_encoding encoding)
+	{
+		if (encoding == encoding_utf16_be || encoding == encoding_utf16_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf16_le : encoding_utf16_be;
+
+			return convert_buffer_output_generic(r_u16, data, length, utf8_decoder(), utf16_writer(), native_encoding != encoding);
+		}
+
+		if (encoding == encoding_utf32_be || encoding == encoding_utf32_le)
+		{
+			xml_encoding native_encoding = is_little_endian() ? encoding_utf32_le : encoding_utf32_be;
+
+			return convert_buffer_output_generic(r_u32, data, length, utf8_decoder(), utf32_writer(), native_encoding != encoding);
+		}
+
+		if (encoding == encoding_latin1)
+			return convert_buffer_output_generic(r_u8, data, length, utf8_decoder(), latin1_writer());
+
+		assert(false && "Invalid encoding");
+		return 0;
+	}
+#endif
+
+	class xml_buffered_writer
+	{
+		xml_buffered_writer(const xml_buffered_writer&);
+		xml_buffered_writer& operator=(const xml_buffered_writer&);
+
+	public:
+		xml_buffered_writer(xml_writer& writer_, xml_encoding user_encoding): writer(writer_), bufsize(0), encoding(get_write_encoding(user_encoding))
+		{
+			PUGI__STATIC_ASSERT(bufcapacity >= 8);
+		}
+
+		size_t flush()
+		{
+			flush(buffer, bufsize);
+			bufsize = 0;
+			return 0;
+		}
+
+		void flush(const char_t* data, size_t size)
+		{
+			if (size == 0) return;
+
+			// fast path, just write data
+			if (encoding == get_write_native_encoding())
+				writer.write(data, size * sizeof(char_t));
+			else
+			{
+				// convert chunk
+				size_t result = convert_buffer_output(scratch.data_char, scratch.data_u8, scratch.data_u16, scratch.data_u32, data, size, encoding);
+				assert(result <= sizeof(scratch));
+
+				// write data
+				writer.write(scratch.data_u8, result);
+			}
+		}
+
+		void write_direct(const char_t* data, size_t length)
+		{
+			// flush the remaining buffer contents
+			flush();
+
+			// handle large chunks
+			if (length > bufcapacity)
+			{
+				if (encoding == get_write_native_encoding())
+				{
+					// fast path, can just write data chunk
+					writer.write(data, length * sizeof(char_t));
+					return;
+				}
+
+				// need to convert in suitable chunks
+				while (length > bufcapacity)
+				{
+					// get chunk size by selecting such number of characters that are guaranteed to fit into scratch buffer
+					// and form a complete codepoint sequence (i.e. discard start of last codepoint if necessary)
+					size_t chunk_size = get_valid_length(data, bufcapacity);
+					assert(chunk_size);
+
+					// convert chunk and write
+					flush(data, chunk_size);
+
+					// iterate
+					data += chunk_size;
+					length -= chunk_size;
+				}
+
+				// small tail is copied below
+				bufsize = 0;
+			}
+
+			memcpy(buffer + bufsize, data, length * sizeof(char_t));
+			bufsize += length;
+		}
+
+		void write_buffer(const char_t* data, size_t length)
+		{
+			size_t offset = bufsize;
+
+			if (offset + length <= bufcapacity)
+			{
+				memcpy(buffer + offset, data, length * sizeof(char_t));
+				bufsize = offset + length;
+			}
+			else
+			{
+				write_direct(data, length);
+			}
+		}
+
+		void write_string(const char_t* data)
+		{
+			// write the part of the string that fits in the buffer
+			size_t offset = bufsize;
+
+			while (*data && offset < bufcapacity)
+				buffer[offset++] = *data++;
+
+			// write the rest
+			if (offset < bufcapacity)
+			{
+				bufsize = offset;
+			}
+			else
+			{
+				// backtrack a bit if we have split the codepoint
+				size_t length = offset - bufsize;
+				size_t extra = length - get_valid_length(data - length, length);
+
+				bufsize = offset - extra;
+
+				write_direct(data - extra, strlength(data) + extra);
+			}
+		}
+
+		void write(char_t d0)
+		{
+			size_t offset = bufsize;
+			if (offset > bufcapacity - 1) offset = flush();
+
+			buffer[offset + 0] = d0;
+			bufsize = offset + 1;
+		}
+
+		void write(char_t d0, char_t d1)
+		{
+			size_t offset = bufsize;
+			if (offset > bufcapacity - 2) offset = flush();
+
+			buffer[offset + 0] = d0;
+			buffer[offset + 1] = d1;
+			bufsize = offset + 2;
+		}
+
+		void write(char_t d0, char_t d1, char_t d2)
+		{
+			size_t offset = bufsize;
+			if (offset > bufcapacity - 3) offset = flush();
+
+			buffer[offset + 0] = d0;
+			buffer[offset + 1] = d1;
+			buffer[offset + 2] = d2;
+			bufsize = offset + 3;
+		}
+
+		void write(char_t d0, char_t d1, char_t d2, char_t d3)
+		{
+			size_t offset = bufsize;
+			if (offset > bufcapacity - 4) offset = flush();
+
+			buffer[offset + 0] = d0;
+			buffer[offset + 1] = d1;
+			buffer[offset + 2] = d2;
+			buffer[offset + 3] = d3;
+			bufsize = offset + 4;
+		}
+
+		void write(char_t d0, char_t d1, char_t d2, char_t d3, char_t d4)
+		{
+			size_t offset = bufsize;
+			if (offset > bufcapacity - 5) offset = flush();
+
+			buffer[offset + 0] = d0;
+			buffer[offset + 1] = d1;
+			buffer[offset + 2] = d2;
+			buffer[offset + 3] = d3;
+			buffer[offset + 4] = d4;
+			bufsize = offset + 5;
+		}
+
+		void write(char_t d0, char_t d1, char_t d2, char_t d3, char_t d4, char_t d5)
+		{
+			size_t offset = bufsize;
+			if (offset > bufcapacity - 6) offset = flush();
+
+			buffer[offset + 0] = d0;
+			buffer[offset + 1] = d1;
+			buffer[offset + 2] = d2;
+			buffer[offset + 3] = d3;
+			buffer[offset + 4] = d4;
+			buffer[offset + 5] = d5;
+			bufsize = offset + 6;
+		}
+
+		// utf8 maximum expansion: x4 (-> utf32)
+		// utf16 maximum expansion: x2 (-> utf32)
+		// utf32 maximum expansion: x1
+		enum
+		{
+			bufcapacitybytes =
+			#ifdef PUGIXML_MEMORY_OUTPUT_STACK
+				PUGIXML_MEMORY_OUTPUT_STACK
+			#else
+				10240
+			#endif
+			,
+			bufcapacity = bufcapacitybytes / (sizeof(char_t) + 4)
+		};
+
+		char_t buffer[bufcapacity];
+
+		union
+		{
+			uint8_t data_u8[4 * bufcapacity];
+			uint16_t data_u16[2 * bufcapacity];
+			uint32_t data_u32[bufcapacity];
+			char_t data_char[bufcapacity];
+		} scratch;
+
+		xml_writer& writer;
+		size_t bufsize;
+		xml_encoding encoding;
+	};
+
+	PUGI__FN void text_output_escaped(xml_buffered_writer& writer, const char_t* s, chartypex_t type)
+	{
+		while (*s)
+		{
+			const char_t* prev = s;
+
+			// While *s is a usual symbol
+			PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPEX(ss, type));
+
+			writer.write_buffer(prev, static_cast<size_t>(s - prev));
+
+			switch (*s)
+			{
+				case 0: break;
+				case '&':
+					writer.write('&', 'a', 'm', 'p', ';');
+					++s;
+					break;
+				case '<':
+					writer.write('&', 'l', 't', ';');
+					++s;
+					break;
+				case '>':
+					writer.write('&', 'g', 't', ';');
+					++s;
+					break;
+				case '"':
+					writer.write('&', 'q', 'u', 'o', 't', ';');
+					++s;
+					break;
+				default: // s is not a usual symbol
+				{
+					unsigned int ch = static_cast<unsigned int>(*s++);
+					assert(ch < 32);
+
+					writer.write('&', '#', static_cast<char_t>((ch / 10) + '0'), static_cast<char_t>((ch % 10) + '0'), ';');
+				}
+			}
+		}
+	}
+
+	PUGI__FN void text_output(xml_buffered_writer& writer, const char_t* s, chartypex_t type, unsigned int flags)
+	{
+		if (flags & format_no_escapes)
+			writer.write_string(s);
+		else
+			text_output_escaped(writer, s, type);
+	}
+
+	PUGI__FN void text_output_cdata(xml_buffered_writer& writer, const char_t* s)
+	{
+		do
+		{
+			writer.write('<', '!', '[', 'C', 'D');
+			writer.write('A', 'T', 'A', '[');
+
+			const char_t* prev = s;
+
+			// look for ]]> sequence - we can't output it as is since it terminates CDATA
+			while (*s && !(s[0] == ']' && s[1] == ']' && s[2] == '>')) ++s;
+
+			// skip ]] if we stopped at ]]>, > will go to the next CDATA section
+			if (*s) s += 2;
+
+			writer.write_buffer(prev, static_cast<size_t>(s - prev));
+
+			writer.write(']', ']', '>');
+		}
+		while (*s);
+	}
+
+	PUGI__FN void text_output_indent(xml_buffered_writer& writer, const char_t* indent, size_t indent_length, unsigned int depth)
+	{
+		switch (indent_length)
+		{
+		case 1:
+		{
+			for (unsigned int i = 0; i < depth; ++i)
+				writer.write(indent[0]);
+			break;
+		}
+
+		case 2:
+		{
+			for (unsigned int i = 0; i < depth; ++i)
+				writer.write(indent[0], indent[1]);
+			break;
+		}
+
+		case 3:
+		{
+			for (unsigned int i = 0; i < depth; ++i)
+				writer.write(indent[0], indent[1], indent[2]);
+			break;
+		}
+
+		case 4:
+		{
+			for (unsigned int i = 0; i < depth; ++i)
+				writer.write(indent[0], indent[1], indent[2], indent[3]);
+			break;
+		}
+
+		default:
+		{
+			for (unsigned int i = 0; i < depth; ++i)
+				writer.write_buffer(indent, indent_length);
+		}
+		}
+	}
+
+	PUGI__FN void node_output_comment(xml_buffered_writer& writer, const char_t* s)
+	{
+		writer.write('<', '!', '-', '-');
+
+		while (*s)
+		{
+			const char_t* prev = s;
+
+			// look for -\0 or -- sequence - we can't output it since -- is illegal in comment body
+			while (*s && !(s[0] == '-' && (s[1] == '-' || s[1] == 0))) ++s;
+
+			writer.write_buffer(prev, static_cast<size_t>(s - prev));
+
+			if (*s)
+			{
+				assert(*s == '-');
+
+				writer.write('-', ' ');
+				++s;
+			}
+		}
+
+		writer.write('-', '-', '>');
+	}
+
+	PUGI__FN void node_output_pi_value(xml_buffered_writer& writer, const char_t* s)
+	{
+		while (*s)
+		{
+			const char_t* prev = s;
+
+			// look for ?> sequence - we can't output it since ?> terminates PI
+			while (*s && !(s[0] == '?' && s[1] == '>')) ++s;
+
+			writer.write_buffer(prev, static_cast<size_t>(s - prev));
+
+			if (*s)
+			{
+				assert(s[0] == '?' && s[1] == '>');
+
+				writer.write('?', ' ', '>');
+				s += 2;
+			}
+		}
+	}
+
+	PUGI__FN void node_output_attributes(xml_buffered_writer& writer, xml_node_struct* node, const char_t* indent, size_t indent_length, unsigned int flags, unsigned int depth)
+	{
+		const char_t* default_name = PUGIXML_TEXT(":anonymous");
+
+		for (xml_attribute_struct* a = node->first_attribute; a; a = a->next_attribute)
+		{
+			if ((flags & (format_indent_attributes | format_raw)) == format_indent_attributes)
+			{
+				writer.write('\n');
+
+				text_output_indent(writer, indent, indent_length, depth + 1);
+			}
+			else
+			{
+				writer.write(' ');
+			}
+
+			writer.write_string(a->name ? a->name + 0 : default_name);
+			writer.write('=', '"');
+
+			if (a->value)
+				text_output(writer, a->value, ctx_special_attr, flags);
+
+			writer.write('"');
+		}
+	}
+
+	PUGI__FN bool node_output_start(xml_buffered_writer& writer, xml_node_struct* node, const char_t* indent, size_t indent_length, unsigned int flags, unsigned int depth)
+	{
+		const char_t* default_name = PUGIXML_TEXT(":anonymous");
+		const char_t* name = node->name ? node->name + 0 : default_name;
+
+		writer.write('<');
+		writer.write_string(name);
+
+		if (node->first_attribute)
+			node_output_attributes(writer, node, indent, indent_length, flags, depth);
+
+		// element nodes can have value if parse_embed_pcdata was used
+		if (!node->value)
+		{
+			if (!node->first_child)
+			{
+				if (flags & format_no_empty_element_tags)
+				{
+					writer.write('>', '<', '/');
+					writer.write_string(name);
+					writer.write('>');
+
+					return false;
+				}
+				else
+				{
+					if ((flags & format_raw) == 0)
+						writer.write(' ');
+
+					writer.write('/', '>');
+
+					return false;
+				}
+			}
+			else
+			{
+				writer.write('>');
+
+				return true;
+			}
+		}
+		else
+		{
+			writer.write('>');
+
+			text_output(writer, node->value, ctx_special_pcdata, flags);
+
+			if (!node->first_child)
+			{
+				writer.write('<', '/');
+				writer.write_string(name);
+				writer.write('>');
+
+				return false;
+			}
+			else
+			{
+				return true;
+			}
+		}
+	}
+
+	PUGI__FN void node_output_end(xml_buffered_writer& writer, xml_node_struct* node)
+	{
+		const char_t* default_name = PUGIXML_TEXT(":anonymous");
+		const char_t* name = node->name ? node->name + 0 : default_name;
+
+		writer.write('<', '/');
+		writer.write_string(name);
+		writer.write('>');
+	}
+
+	PUGI__FN void node_output_simple(xml_buffered_writer& writer, xml_node_struct* node, unsigned int flags)
+	{
+		const char_t* default_name = PUGIXML_TEXT(":anonymous");
+
+		switch (PUGI__NODETYPE(node))
+		{
+			case node_pcdata:
+				text_output(writer, node->value ? node->value + 0 : PUGIXML_TEXT(""), ctx_special_pcdata, flags);
+				break;
+
+			case node_cdata:
+				text_output_cdata(writer, node->value ? node->value + 0 : PUGIXML_TEXT(""));
+				break;
+
+			case node_comment:
+				node_output_comment(writer, node->value ? node->value + 0 : PUGIXML_TEXT(""));
+				break;
+
+			case node_pi:
+				writer.write('<', '?');
+				writer.write_string(node->name ? node->name + 0 : default_name);
+
+				if (node->value)
+				{
+					writer.write(' ');
+					node_output_pi_value(writer, node->value);
+				}
+
+				writer.write('?', '>');
+				break;
+
+			case node_declaration:
+				writer.write('<', '?');
+				writer.write_string(node->name ? node->name + 0 : default_name);
+				node_output_attributes(writer, node, PUGIXML_TEXT(""), 0, flags | format_raw, 0);
+				writer.write('?', '>');
+				break;
+
+			case node_doctype:
+				writer.write('<', '!', 'D', 'O', 'C');
+				writer.write('T', 'Y', 'P', 'E');
+
+				if (node->value)
+				{
+					writer.write(' ');
+					writer.write_string(node->value);
+				}
+
+				writer.write('>');
+				break;
+
+			default:
+				assert(false && "Invalid node type");
+		}
+	}
+
+	enum indent_flags_t
+	{
+		indent_newline = 1,
+		indent_indent = 2
+	};
+
+	PUGI__FN void node_output(xml_buffered_writer& writer, xml_node_struct* root, const char_t* indent, unsigned int flags, unsigned int depth)
+	{
+		size_t indent_length = ((flags & (format_indent | format_indent_attributes)) && (flags & format_raw) == 0) ? strlength(indent) : 0;
+		unsigned int indent_flags = indent_indent;
+
+		xml_node_struct* node = root;
+
+		do
+		{
+			assert(node);
+
+			// begin writing current node
+			if (PUGI__NODETYPE(node) == node_pcdata || PUGI__NODETYPE(node) == node_cdata)
+			{
+				node_output_simple(writer, node, flags);
+
+				indent_flags = 0;
+			}
+			else
+			{
+				if ((indent_flags & indent_newline) && (flags & format_raw) == 0)
+					writer.write('\n');
+
+				if ((indent_flags & indent_indent) && indent_length)
+					text_output_indent(writer, indent, indent_length, depth);
+
+				if (PUGI__NODETYPE(node) == node_element)
+				{
+					indent_flags = indent_newline | indent_indent;
+
+					if (node_output_start(writer, node, indent, indent_length, flags, depth))
+					{
+						// element nodes can have value if parse_embed_pcdata was used
+						if (node->value)
+							indent_flags = 0;
+
+						node = node->first_child;
+						depth++;
+						continue;
+					}
+				}
+				else if (PUGI__NODETYPE(node) == node_document)
+				{
+					indent_flags = indent_indent;
+
+					if (node->first_child)
+					{
+						node = node->first_child;
+						continue;
+					}
+				}
+				else
+				{
+					node_output_simple(writer, node, flags);
+
+					indent_flags = indent_newline | indent_indent;
+				}
+			}
+
+			// continue to the next node
+			while (node != root)
+			{
+				if (node->next_sibling)
+				{
+					node = node->next_sibling;
+					break;
+				}
+
+				node = node->parent;
+
+				// write closing node
+				if (PUGI__NODETYPE(node) == node_element)
+				{
+					depth--;
+
+					if ((indent_flags & indent_newline) && (flags & format_raw) == 0)
+						writer.write('\n');
+
+					if ((indent_flags & indent_indent) && indent_length)
+						text_output_indent(writer, indent, indent_length, depth);
+
+					node_output_end(writer, node);
+
+					indent_flags = indent_newline | indent_indent;
+				}
+			}
+		}
+		while (node != root);
+
+		if ((indent_flags & indent_newline) && (flags & format_raw) == 0)
+			writer.write('\n');
+	}
+
+	PUGI__FN bool has_declaration(xml_node_struct* node)
+	{
+		for (xml_node_struct* child = node->first_child; child; child = child->next_sibling)
+		{
+			xml_node_type type = PUGI__NODETYPE(child);
+
+			if (type == node_declaration) return true;
+			if (type == node_element) return false;
+		}
+
+		return false;
+	}
+
+	PUGI__FN bool is_attribute_of(xml_attribute_struct* attr, xml_node_struct* node)
+	{
+		for (xml_attribute_struct* a = node->first_attribute; a; a = a->next_attribute)
+			if (a == attr)
+				return true;
+
+		return false;
+	}
+
+	PUGI__FN bool allow_insert_attribute(xml_node_type parent)
+	{
+		return parent == node_element || parent == node_declaration;
+	}
+
+	PUGI__FN bool allow_insert_child(xml_node_type parent, xml_node_type child)
+	{
+		if (parent != node_document && parent != node_element) return false;
+		if (child == node_document || child == node_null) return false;
+		if (parent != node_document && (child == node_declaration || child == node_doctype)) return false;
+
+		return true;
+	}
+
+	PUGI__FN bool allow_move(xml_node parent, xml_node child)
+	{
+		// check that child can be a child of parent
+		if (!allow_insert_child(parent.type(), child.type()))
+			return false;
+
+		// check that node is not moved between documents
+		if (parent.root() != child.root())
+			return false;
+
+		// check that new parent is not in the child subtree
+		xml_node cur = parent;
+
+		while (cur)
+		{
+			if (cur == child)
+				return false;
+
+			cur = cur.parent();
+		}
+
+		return true;
+	}
+
+	template <typename String, typename Header>
+	PUGI__FN void node_copy_string(String& dest, Header& header, uintptr_t header_mask, char_t* source, Header& source_header, xml_allocator* alloc)
+	{
+		assert(!dest && (header & header_mask) == 0);
+
+		if (source)
+		{
+			if (alloc && (source_header & header_mask) == 0)
+			{
+				dest = source;
+
+				// since strcpy_insitu can reuse document buffer memory we need to mark both source and dest as shared
+				header |= xml_memory_page_contents_shared_mask;
+				source_header |= xml_memory_page_contents_shared_mask;
+			}
+			else
+				strcpy_insitu(dest, header, header_mask, source, strlength(source));
+		}
+	}
+
+	PUGI__FN void node_copy_contents(xml_node_struct* dn, xml_node_struct* sn, xml_allocator* shared_alloc)
+	{
+		node_copy_string(dn->name, dn->header, xml_memory_page_name_allocated_mask, sn->name, sn->header, shared_alloc);
+		node_copy_string(dn->value, dn->header, xml_memory_page_value_allocated_mask, sn->value, sn->header, shared_alloc);
+
+		for (xml_attribute_struct* sa = sn->first_attribute; sa; sa = sa->next_attribute)
+		{
+			xml_attribute_struct* da = append_new_attribute(dn, get_allocator(dn));
+
+			if (da)
+			{
+				node_copy_string(da->name, da->header, xml_memory_page_name_allocated_mask, sa->name, sa->header, shared_alloc);
+				node_copy_string(da->value, da->header, xml_memory_page_value_allocated_mask, sa->value, sa->header, shared_alloc);
+			}
+		}
+	}
+
+	PUGI__FN void node_copy_tree(xml_node_struct* dn, xml_node_struct* sn)
+	{
+		xml_allocator& alloc = get_allocator(dn);
+		xml_allocator* shared_alloc = (&alloc == &get_allocator(sn)) ? &alloc : 0;
+
+		node_copy_contents(dn, sn, shared_alloc);
+
+		xml_node_struct* dit = dn;
+		xml_node_struct* sit = sn->first_child;
+
+		while (sit && sit != sn)
+		{
+			if (sit != dn)
+			{
+				xml_node_struct* copy = append_new_node(dit, alloc, PUGI__NODETYPE(sit));
+
+				if (copy)
+				{
+					node_copy_contents(copy, sit, shared_alloc);
+
+					if (sit->first_child)
+					{
+						dit = copy;
+						sit = sit->first_child;
+						continue;
+					}
+				}
+			}
+
+			// continue to the next node
+			do
+			{
+				if (sit->next_sibling)
+				{
+					sit = sit->next_sibling;
+					break;
+				}
+
+				sit = sit->parent;
+				dit = dit->parent;
+			}
+			while (sit != sn);
+		}
+	}
+
+	PUGI__FN void node_copy_attribute(xml_attribute_struct* da, xml_attribute_struct* sa)
+	{
+		xml_allocator& alloc = get_allocator(da);
+		xml_allocator* shared_alloc = (&alloc == &get_allocator(sa)) ? &alloc : 0;
+
+		node_copy_string(da->name, da->header, xml_memory_page_name_allocated_mask, sa->name, sa->header, shared_alloc);
+		node_copy_string(da->value, da->header, xml_memory_page_value_allocated_mask, sa->value, sa->header, shared_alloc);
+	}
+
+	inline bool is_text_node(xml_node_struct* node)
+	{
+		xml_node_type type = PUGI__NODETYPE(node);
+
+		return type == node_pcdata || type == node_cdata;
+	}
+
+	// get value with conversion functions
+	template <typename U> U string_to_integer(const char_t* value, U minneg, U maxpos)
+	{
+		U result = 0;
+		const char_t* s = value;
+
+		while (PUGI__IS_CHARTYPE(*s, ct_space))
+			s++;
+
+		bool negative = (*s == '-');
+
+		s += (*s == '+' || *s == '-');
+
+		bool overflow = false;
+
+		if (s[0] == '0' && (s[1] | ' ') == 'x')
+		{
+			s += 2;
+
+			// since overflow detection relies on length of the sequence skip leading zeros
+			while (*s == '0')
+				s++;
+
+			const char_t* start = s;
+
+			for (;;)
+			{
+				if (static_cast<unsigned>(*s - '0') < 10)
+					result = result * 16 + (*s - '0');
+				else if (static_cast<unsigned>((*s | ' ') - 'a') < 6)
+					result = result * 16 + ((*s | ' ') - 'a' + 10);
+				else
+					break;
+
+				s++;
+			}
+
+			size_t digits = static_cast<size_t>(s - start);
+
+			overflow = digits > sizeof(U) * 2;
+		}
+		else
+		{
+			// since overflow detection relies on length of the sequence skip leading zeros
+			while (*s == '0')
+				s++;
+
+			const char_t* start = s;
+
+			for (;;)
+			{
+				if (static_cast<unsigned>(*s - '0') < 10)
+					result = result * 10 + (*s - '0');
+				else
+					break;
+
+				s++;
+			}
+
+			size_t digits = static_cast<size_t>(s - start);
+
+			PUGI__STATIC_ASSERT(sizeof(U) == 8 || sizeof(U) == 4 || sizeof(U) == 2);
+
+			const size_t max_digits10 = sizeof(U) == 8 ? 20 : sizeof(U) == 4 ? 10 : 5;
+			const char_t max_lead = sizeof(U) == 8 ? '1' : sizeof(U) == 4 ? '4' : '6';
+			const size_t high_bit = sizeof(U) * 8 - 1;
+
+			overflow = digits >= max_digits10 && !(digits == max_digits10 && (*start < max_lead || (*start == max_lead && result >> high_bit)));
+		}
+
+		if (negative)
+			return (overflow || result > minneg) ? 0 - minneg : 0 - result;
+		else
+			return (overflow || result > maxpos) ? maxpos : result;
+	}
+
+	PUGI__FN int get_value_int(const char_t* value)
+	{
+		return string_to_integer<unsigned int>(value, 0 - static_cast<unsigned int>(INT_MIN), INT_MAX);
+	}
+
+	PUGI__FN unsigned int get_value_uint(const char_t* value)
+	{
+		return string_to_integer<unsigned int>(value, 0, UINT_MAX);
+	}
+
+	PUGI__FN double get_value_double(const char_t* value)
+	{
+	#ifdef PUGIXML_WCHAR_MODE
+		return wcstod(value, 0);
+	#else
+		return strtod(value, 0);
+	#endif
+	}
+
+	PUGI__FN float get_value_float(const char_t* value)
+	{
+	#ifdef PUGIXML_WCHAR_MODE
+		return static_cast<float>(wcstod(value, 0));
+	#else
+		return static_cast<float>(strtod(value, 0));
+	#endif
+	}
+
+	PUGI__FN bool get_value_bool(const char_t* value)
+	{
+		// only look at first char
+		char_t first = *value;
+
+		// 1*, t* (true), T* (True), y* (yes), Y* (YES)
+		return (first == '1' || first == 't' || first == 'T' || first == 'y' || first == 'Y');
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN long long get_value_llong(const char_t* value)
+	{
+		return string_to_integer<unsigned long long>(value, 0 - static_cast<unsigned long long>(LLONG_MIN), LLONG_MAX);
+	}
+
+	PUGI__FN unsigned long long get_value_ullong(const char_t* value)
+	{
+		return string_to_integer<unsigned long long>(value, 0, ULLONG_MAX);
+	}
+#endif
+
+	template <typename U> PUGI__FN char_t* integer_to_string(char_t* begin, char_t* end, U value, bool negative)
+	{
+		char_t* result = end - 1;
+		U rest = negative ? 0 - value : value;
+
+		do
+		{
+			*result-- = static_cast<char_t>('0' + (rest % 10));
+			rest /= 10;
+		}
+		while (rest);
+
+		assert(result >= begin);
+		(void)begin;
+
+		*result = '-';
+
+		return result + !negative;
+	}
+
+	// set value with conversion functions
+	template <typename String, typename Header>
+	PUGI__FN bool set_value_ascii(String& dest, Header& header, uintptr_t header_mask, char* buf)
+	{
+	#ifdef PUGIXML_WCHAR_MODE
+		char_t wbuf[128];
+		assert(strlen(buf) < sizeof(wbuf) / sizeof(wbuf[0]));
+
+		size_t offset = 0;
+		for (; buf[offset]; ++offset) wbuf[offset] = buf[offset];
+
+		return strcpy_insitu(dest, header, header_mask, wbuf, offset);
+	#else
+		return strcpy_insitu(dest, header, header_mask, buf, strlen(buf));
+	#endif
+	}
+
+	template <typename U, typename String, typename Header>
+	PUGI__FN bool set_value_integer(String& dest, Header& header, uintptr_t header_mask, U value, bool negative)
+	{
+		char_t buf[64];
+		char_t* end = buf + sizeof(buf) / sizeof(buf[0]);
+		char_t* begin = integer_to_string(buf, end, value, negative);
+
+		return strcpy_insitu(dest, header, header_mask, begin, end - begin);
+	}
+
+	template <typename String, typename Header>
+	PUGI__FN bool set_value_convert(String& dest, Header& header, uintptr_t header_mask, float value)
+	{
+		char buf[128];
+		sprintf(buf, "%.9g", value);
+
+		return set_value_ascii(dest, header, header_mask, buf);
+	}
+
+	template <typename String, typename Header>
+	PUGI__FN bool set_value_convert(String& dest, Header& header, uintptr_t header_mask, double value)
+	{
+		char buf[128];
+		sprintf(buf, "%.17g", value);
+
+		return set_value_ascii(dest, header, header_mask, buf);
+	}
+
+	template <typename String, typename Header>
+	PUGI__FN bool set_value_bool(String& dest, Header& header, uintptr_t header_mask, bool value)
+	{
+		return strcpy_insitu(dest, header, header_mask, value ? PUGIXML_TEXT("true") : PUGIXML_TEXT("false"), value ? 4 : 5);
+	}
+
+	PUGI__FN xml_parse_result load_buffer_impl(xml_document_struct* doc, xml_node_struct* root, void* contents, size_t size, unsigned int options, xml_encoding encoding, bool is_mutable, bool own, char_t** out_buffer)
+	{
+		// check input buffer
+		if (!contents && size) return make_parse_result(status_io_error);
+
+		// get actual encoding
+		xml_encoding buffer_encoding = impl::get_buffer_encoding(encoding, contents, size);
+
+		// get private buffer
+		char_t* buffer = 0;
+		size_t length = 0;
+
+		if (!impl::convert_buffer(buffer, length, buffer_encoding, contents, size, is_mutable)) return impl::make_parse_result(status_out_of_memory);
+
+		// delete original buffer if we performed a conversion
+		if (own && buffer != contents && contents) impl::xml_memory::deallocate(contents);
+
+		// grab onto buffer if it's our buffer, user is responsible for deallocating contents himself
+		if (own || buffer != contents) *out_buffer = buffer;
+
+		// store buffer for offset_debug
+		doc->buffer = buffer;
+
+		// parse
+		xml_parse_result res = impl::xml_parser::parse(buffer, length, doc, root, options);
+
+		// remember encoding
+		res.encoding = buffer_encoding;
+
+		return res;
+	}
+
+	// we need to get length of entire file to load it in memory; the only (relatively) sane way to do it is via seek/tell trick
+	PUGI__FN xml_parse_status get_file_size(FILE* file, size_t& out_result)
+	{
+	#if defined(PUGI__MSVC_CRT_VERSION) && PUGI__MSVC_CRT_VERSION >= 1400 && !defined(_WIN32_WCE)
+		// there are 64-bit versions of fseek/ftell, let's use them
+		typedef __int64 length_type;
+
+		_fseeki64(file, 0, SEEK_END);
+		length_type length = _ftelli64(file);
+		_fseeki64(file, 0, SEEK_SET);
+	#elif defined(__MINGW32__) && !defined(__NO_MINGW_LFS) && (!defined(__STRICT_ANSI__) || defined(__MINGW64_VERSION_MAJOR))
+		// there are 64-bit versions of fseek/ftell, let's use them
+		typedef off64_t length_type;
+
+		fseeko64(file, 0, SEEK_END);
+		length_type length = ftello64(file);
+		fseeko64(file, 0, SEEK_SET);
+	#else
+		// if this is a 32-bit OS, long is enough; if this is a unix system, long is 64-bit, which is enough; otherwise we can't do anything anyway.
+		typedef long length_type;
+
+		fseek(file, 0, SEEK_END);
+		length_type length = ftell(file);
+		fseek(file, 0, SEEK_SET);
+	#endif
+
+		// check for I/O errors
+		if (length < 0) return status_io_error;
+
+		// check for overflow
+		size_t result = static_cast<size_t>(length);
+
+		if (static_cast<length_type>(result) != length) return status_out_of_memory;
+
+		// finalize
+		out_result = result;
+
+		return status_ok;
+	}
+
+	// This function assumes that buffer has extra sizeof(char_t) writable bytes after size
+	PUGI__FN size_t zero_terminate_buffer(void* buffer, size_t size, xml_encoding encoding)
+	{
+		// We only need to zero-terminate if encoding conversion does not do it for us
+	#ifdef PUGIXML_WCHAR_MODE
+		xml_encoding wchar_encoding = get_wchar_encoding();
+
+		if (encoding == wchar_encoding || need_endian_swap_utf(encoding, wchar_encoding))
+		{
+			size_t length = size / sizeof(char_t);
+
+			static_cast<char_t*>(buffer)[length] = 0;
+			return (length + 1) * sizeof(char_t);
+		}
+	#else
+		if (encoding == encoding_utf8)
+		{
+			static_cast<char*>(buffer)[size] = 0;
+			return size + 1;
+		}
+	#endif
+
+		return size;
+	}
+
+	PUGI__FN xml_parse_result load_file_impl(xml_document_struct* doc, FILE* file, unsigned int options, xml_encoding encoding, char_t** out_buffer)
+	{
+		if (!file) return make_parse_result(status_file_not_found);
+
+		// get file size (can result in I/O errors)
+		size_t size = 0;
+		xml_parse_status size_status = get_file_size(file, size);
+		if (size_status != status_ok) return make_parse_result(size_status);
+
+		size_t max_suffix_size = sizeof(char_t);
+
+		// allocate buffer for the whole file
+		char* contents = static_cast<char*>(xml_memory::allocate(size + max_suffix_size));
+		if (!contents) return make_parse_result(status_out_of_memory);
+
+		// read file in memory
+		size_t read_size = fread(contents, 1, size, file);
+
+		if (read_size != size)
+		{
+			xml_memory::deallocate(contents);
+			return make_parse_result(status_io_error);
+		}
+
+		xml_encoding real_encoding = get_buffer_encoding(encoding, contents, size);
+
+		return load_buffer_impl(doc, doc, contents, zero_terminate_buffer(contents, size, real_encoding), options, real_encoding, true, true, out_buffer);
+	}
+
+	PUGI__FN void close_file(FILE* file)
+	{
+		fclose(file);
+	}
+
+#ifndef PUGIXML_NO_STL
+	template <typename T> struct xml_stream_chunk
+	{
+		static xml_stream_chunk* create()
+		{
+			void* memory = xml_memory::allocate(sizeof(xml_stream_chunk));
+			if (!memory) return 0;
+
+			return new (memory) xml_stream_chunk();
+		}
+
+		static void destroy(xml_stream_chunk* chunk)
+		{
+			// free chunk chain
+			while (chunk)
+			{
+				xml_stream_chunk* next_ = chunk->next;
+
+				xml_memory::deallocate(chunk);
+
+				chunk = next_;
+			}
+		}
+
+		xml_stream_chunk(): next(0), size(0)
+		{
+		}
+
+		xml_stream_chunk* next;
+		size_t size;
+
+		T data[xml_memory_page_size / sizeof(T)];
+	};
+
+	template <typename T> PUGI__FN xml_parse_status load_stream_data_noseek(std::basic_istream<T>& stream, void** out_buffer, size_t* out_size)
+	{
+		auto_deleter<xml_stream_chunk<T> > chunks(0, xml_stream_chunk<T>::destroy);
+
+		// read file to a chunk list
+		size_t total = 0;
+		xml_stream_chunk<T>* last = 0;
+
+		while (!stream.eof())
+		{
+			// allocate new chunk
+			xml_stream_chunk<T>* chunk = xml_stream_chunk<T>::create();
+			if (!chunk) return status_out_of_memory;
+
+			// append chunk to list
+			if (last) last = last->next = chunk;
+			else chunks.data = last = chunk;
+
+			// read data to chunk
+			stream.read(chunk->data, static_cast<std::streamsize>(sizeof(chunk->data) / sizeof(T)));
+			chunk->size = static_cast<size_t>(stream.gcount()) * sizeof(T);
+
+			// read may set failbit | eofbit in case gcount() is less than read length, so check for other I/O errors
+			if (stream.bad() || (!stream.eof() && stream.fail())) return status_io_error;
+
+			// guard against huge files (chunk size is small enough to make this overflow check work)
+			if (total + chunk->size < total) return status_out_of_memory;
+			total += chunk->size;
+		}
+
+		size_t max_suffix_size = sizeof(char_t);
+
+		// copy chunk list to a contiguous buffer
+		char* buffer = static_cast<char*>(xml_memory::allocate(total + max_suffix_size));
+		if (!buffer) return status_out_of_memory;
+
+		char* write = buffer;
+
+		for (xml_stream_chunk<T>* chunk = chunks.data; chunk; chunk = chunk->next)
+		{
+			assert(write + chunk->size <= buffer + total);
+			memcpy(write, chunk->data, chunk->size);
+			write += chunk->size;
+		}
+
+		assert(write == buffer + total);
+
+		// return buffer
+		*out_buffer = buffer;
+		*out_size = total;
+
+		return status_ok;
+	}
+
+	template <typename T> PUGI__FN xml_parse_status load_stream_data_seek(std::basic_istream<T>& stream, void** out_buffer, size_t* out_size)
+	{
+		// get length of remaining data in stream
+		typename std::basic_istream<T>::pos_type pos = stream.tellg();
+		stream.seekg(0, std::ios::end);
+		std::streamoff length = stream.tellg() - pos;
+		stream.seekg(pos);
+
+		if (stream.fail() || pos < 0) return status_io_error;
+
+		// guard against huge files
+		size_t read_length = static_cast<size_t>(length);
+
+		if (static_cast<std::streamsize>(read_length) != length || length < 0) return status_out_of_memory;
+
+		size_t max_suffix_size = sizeof(char_t);
+
+		// read stream data into memory (guard against stream exceptions with buffer holder)
+		auto_deleter<void> buffer(xml_memory::allocate(read_length * sizeof(T) + max_suffix_size), xml_memory::deallocate);
+		if (!buffer.data) return status_out_of_memory;
+
+		stream.read(static_cast<T*>(buffer.data), static_cast<std::streamsize>(read_length));
+
+		// read may set failbit | eofbit in case gcount() is less than read_length (i.e. line ending conversion), so check for other I/O errors
+		if (stream.bad() || (!stream.eof() && stream.fail())) return status_io_error;
+
+		// return buffer
+		size_t actual_length = static_cast<size_t>(stream.gcount());
+		assert(actual_length <= read_length);
+
+		*out_buffer = buffer.release();
+		*out_size = actual_length * sizeof(T);
+
+		return status_ok;
+	}
+
+	template <typename T> PUGI__FN xml_parse_result load_stream_impl(xml_document_struct* doc, std::basic_istream<T>& stream, unsigned int options, xml_encoding encoding, char_t** out_buffer)
+	{
+		void* buffer = 0;
+		size_t size = 0;
+		xml_parse_status status = status_ok;
+
+		// if stream has an error bit set, bail out (otherwise tellg() can fail and we'll clear error bits)
+		if (stream.fail()) return make_parse_result(status_io_error);
+
+		// load stream to memory (using seek-based implementation if possible, since it's faster and takes less memory)
+		if (stream.tellg() < 0)
+		{
+			stream.clear(); // clear error flags that could be set by a failing tellg
+			status = load_stream_data_noseek(stream, &buffer, &size);
+		}
+		else
+			status = load_stream_data_seek(stream, &buffer, &size);
+
+		if (status != status_ok) return make_parse_result(status);
+
+		xml_encoding real_encoding = get_buffer_encoding(encoding, buffer, size);
+
+		return load_buffer_impl(doc, doc, buffer, zero_terminate_buffer(buffer, size, real_encoding), options, real_encoding, true, true, out_buffer);
+	}
+#endif
+
+#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) || (defined(__MINGW32__) && (!defined(__STRICT_ANSI__) || defined(__MINGW64_VERSION_MAJOR)))
+	PUGI__FN FILE* open_file_wide(const wchar_t* path, const wchar_t* mode)
+	{
+		return _wfopen(path, mode);
+	}
+#else
+	PUGI__FN char* convert_path_heap(const wchar_t* str)
+	{
+		assert(str);
+
+		// first pass: get length in utf8 characters
+		size_t length = strlength_wide(str);
+		size_t size = as_utf8_begin(str, length);
+
+		// allocate resulting string
+		char* result = static_cast<char*>(xml_memory::allocate(size + 1));
+		if (!result) return 0;
+
+		// second pass: convert to utf8
+		as_utf8_end(result, size, str, length);
+
+		// zero-terminate
+		result[size] = 0;
+
+		return result;
+	}
+
+	PUGI__FN FILE* open_file_wide(const wchar_t* path, const wchar_t* mode)
+	{
+		// there is no standard function to open wide paths, so our best bet is to try utf8 path
+		char* path_utf8 = convert_path_heap(path);
+		if (!path_utf8) return 0;
+
+		// convert mode to ASCII (we mirror _wfopen interface)
+		char mode_ascii[4] = {0};
+		for (size_t i = 0; mode[i]; ++i) mode_ascii[i] = static_cast<char>(mode[i]);
+
+		// try to open the utf8 path
+		FILE* result = fopen(path_utf8, mode_ascii);
+
+		// free dummy buffer
+		xml_memory::deallocate(path_utf8);
+
+		return result;
+	}
+#endif
+
+	PUGI__FN bool save_file_impl(const xml_document& doc, FILE* file, const char_t* indent, unsigned int flags, xml_encoding encoding)
+	{
+		if (!file) return false;
+
+		xml_writer_file writer(file);
+		doc.save(writer, indent, flags, encoding);
+
+		return ferror(file) == 0;
+	}
+
+	struct name_null_sentry
+	{
+		xml_node_struct* node;
+		char_t* name;
+
+		name_null_sentry(xml_node_struct* node_): node(node_), name(node_->name)
+		{
+			node->name = 0;
+		}
+
+		~name_null_sentry()
+		{
+			node->name = name;
+		}
+	};
+PUGI__NS_END
+
+namespace pugi
+{
+	PUGI__FN xml_writer_file::xml_writer_file(void* file_): file(file_)
+	{
+	}
+
+	PUGI__FN void xml_writer_file::write(const void* data, size_t size)
+	{
+		size_t result = fwrite(data, 1, size, static_cast<FILE*>(file));
+		(void)!result; // unfortunately we can't do proper error handling here
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN xml_writer_stream::xml_writer_stream(std::basic_ostream<char, std::char_traits<char> >& stream): narrow_stream(&stream), wide_stream(0)
+	{
+	}
+
+	PUGI__FN xml_writer_stream::xml_writer_stream(std::basic_ostream<wchar_t, std::char_traits<wchar_t> >& stream): narrow_stream(0), wide_stream(&stream)
+	{
+	}
+
+	PUGI__FN void xml_writer_stream::write(const void* data, size_t size)
+	{
+		if (narrow_stream)
+		{
+			assert(!wide_stream);
+			narrow_stream->write(reinterpret_cast<const char*>(data), static_cast<std::streamsize>(size));
+		}
+		else
+		{
+			assert(wide_stream);
+			assert(size % sizeof(wchar_t) == 0);
+
+			wide_stream->write(reinterpret_cast<const wchar_t*>(data), static_cast<std::streamsize>(size / sizeof(wchar_t)));
+		}
+	}
+#endif
+
+	PUGI__FN xml_tree_walker::xml_tree_walker(): _depth(0)
+	{
+	}
+
+	PUGI__FN xml_tree_walker::~xml_tree_walker()
+	{
+	}
+
+	PUGI__FN int xml_tree_walker::depth() const
+	{
+		return _depth;
+	}
+
+	PUGI__FN bool xml_tree_walker::begin(xml_node&)
+	{
+		return true;
+	}
+
+	PUGI__FN bool xml_tree_walker::end(xml_node&)
+	{
+		return true;
+	}
+
+	PUGI__FN xml_attribute::xml_attribute(): _attr(0)
+	{
+	}
+
+	PUGI__FN xml_attribute::xml_attribute(xml_attribute_struct* attr): _attr(attr)
+	{
+	}
+
+	PUGI__FN static void unspecified_bool_xml_attribute(xml_attribute***)
+	{
+	}
+
+	PUGI__FN xml_attribute::operator xml_attribute::unspecified_bool_type() const
+	{
+		return _attr ? unspecified_bool_xml_attribute : 0;
+	}
+
+	PUGI__FN bool xml_attribute::operator!() const
+	{
+		return !_attr;
+	}
+
+	PUGI__FN bool xml_attribute::operator==(const xml_attribute& r) const
+	{
+		return (_attr == r._attr);
+	}
+
+	PUGI__FN bool xml_attribute::operator!=(const xml_attribute& r) const
+	{
+		return (_attr != r._attr);
+	}
+
+	PUGI__FN bool xml_attribute::operator<(const xml_attribute& r) const
+	{
+		return (_attr < r._attr);
+	}
+
+	PUGI__FN bool xml_attribute::operator>(const xml_attribute& r) const
+	{
+		return (_attr > r._attr);
+	}
+
+	PUGI__FN bool xml_attribute::operator<=(const xml_attribute& r) const
+	{
+		return (_attr <= r._attr);
+	}
+
+	PUGI__FN bool xml_attribute::operator>=(const xml_attribute& r) const
+	{
+		return (_attr >= r._attr);
+	}
+
+	PUGI__FN xml_attribute xml_attribute::next_attribute() const
+	{
+		return _attr ? xml_attribute(_attr->next_attribute) : xml_attribute();
+	}
+
+	PUGI__FN xml_attribute xml_attribute::previous_attribute() const
+	{
+		return _attr && _attr->prev_attribute_c->next_attribute ? xml_attribute(_attr->prev_attribute_c) : xml_attribute();
+	}
+
+	PUGI__FN const char_t* xml_attribute::as_string(const char_t* def) const
+	{
+		return (_attr && _attr->value) ? _attr->value + 0 : def;
+	}
+
+	PUGI__FN int xml_attribute::as_int(int def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_int(_attr->value) : def;
+	}
+
+	PUGI__FN unsigned int xml_attribute::as_uint(unsigned int def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_uint(_attr->value) : def;
+	}
+
+	PUGI__FN double xml_attribute::as_double(double def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_double(_attr->value) : def;
+	}
+
+	PUGI__FN float xml_attribute::as_float(float def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_float(_attr->value) : def;
+	}
+
+	PUGI__FN bool xml_attribute::as_bool(bool def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_bool(_attr->value) : def;
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN long long xml_attribute::as_llong(long long def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_llong(_attr->value) : def;
+	}
+
+	PUGI__FN unsigned long long xml_attribute::as_ullong(unsigned long long def) const
+	{
+		return (_attr && _attr->value) ? impl::get_value_ullong(_attr->value) : def;
+	}
+#endif
+
+	PUGI__FN bool xml_attribute::empty() const
+	{
+		return !_attr;
+	}
+
+	PUGI__FN const char_t* xml_attribute::name() const
+	{
+		return (_attr && _attr->name) ? _attr->name + 0 : PUGIXML_TEXT("");
+	}
+
+	PUGI__FN const char_t* xml_attribute::value() const
+	{
+		return (_attr && _attr->value) ? _attr->value + 0 : PUGIXML_TEXT("");
+	}
+
+	PUGI__FN size_t xml_attribute::hash_value() const
+	{
+		return static_cast<size_t>(reinterpret_cast<uintptr_t>(_attr) / sizeof(xml_attribute_struct));
+	}
+
+	PUGI__FN xml_attribute_struct* xml_attribute::internal_object() const
+	{
+		return _attr;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(const char_t* rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(int rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(unsigned int rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(long rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(unsigned long rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(double rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(float rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(bool rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN xml_attribute& xml_attribute::operator=(long long rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute::operator=(unsigned long long rhs)
+	{
+		set_value(rhs);
+		return *this;
+	}
+#endif
+
+	PUGI__FN bool xml_attribute::set_name(const char_t* rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::strcpy_insitu(_attr->name, _attr->header, impl::xml_memory_page_name_allocated_mask, rhs, impl::strlength(rhs));
+	}
+
+	PUGI__FN bool xml_attribute::set_value(const char_t* rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::strcpy_insitu(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, impl::strlength(rhs));
+	}
+
+	PUGI__FN bool xml_attribute::set_value(int rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_integer<unsigned int>(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, rhs < 0);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(unsigned int rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_integer<unsigned int>(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, false);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(long rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_integer<unsigned long>(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, rhs < 0);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(unsigned long rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_integer<unsigned long>(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, false);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(double rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_convert(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(float rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_convert(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(bool rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_bool(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs);
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN bool xml_attribute::set_value(long long rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_integer<unsigned long long>(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, rhs < 0);
+	}
+
+	PUGI__FN bool xml_attribute::set_value(unsigned long long rhs)
+	{
+		if (!_attr) return false;
+
+		return impl::set_value_integer<unsigned long long>(_attr->value, _attr->header, impl::xml_memory_page_value_allocated_mask, rhs, false);
+	}
+#endif
+
+#ifdef __BORLANDC__
+	PUGI__FN bool operator&&(const xml_attribute& lhs, bool rhs)
+	{
+		return (bool)lhs && rhs;
+	}
+
+	PUGI__FN bool operator||(const xml_attribute& lhs, bool rhs)
+	{
+		return (bool)lhs || rhs;
+	}
+#endif
+
+	PUGI__FN xml_node::xml_node(): _root(0)
+	{
+	}
+
+	PUGI__FN xml_node::xml_node(xml_node_struct* p): _root(p)
+	{
+	}
+
+	PUGI__FN static void unspecified_bool_xml_node(xml_node***)
+	{
+	}
+
+	PUGI__FN xml_node::operator xml_node::unspecified_bool_type() const
+	{
+		return _root ? unspecified_bool_xml_node : 0;
+	}
+
+	PUGI__FN bool xml_node::operator!() const
+	{
+		return !_root;
+	}
+
+	PUGI__FN xml_node::iterator xml_node::begin() const
+	{
+		return iterator(_root ? _root->first_child + 0 : 0, _root);
+	}
+
+	PUGI__FN xml_node::iterator xml_node::end() const
+	{
+		return iterator(0, _root);
+	}
+
+	PUGI__FN xml_node::attribute_iterator xml_node::attributes_begin() const
+	{
+		return attribute_iterator(_root ? _root->first_attribute + 0 : 0, _root);
+	}
+
+	PUGI__FN xml_node::attribute_iterator xml_node::attributes_end() const
+	{
+		return attribute_iterator(0, _root);
+	}
+
+	PUGI__FN xml_object_range<xml_node_iterator> xml_node::children() const
+	{
+		return xml_object_range<xml_node_iterator>(begin(), end());
+	}
+
+	PUGI__FN xml_object_range<xml_named_node_iterator> xml_node::children(const char_t* name_) const
+	{
+		return xml_object_range<xml_named_node_iterator>(xml_named_node_iterator(child(name_)._root, _root, name_), xml_named_node_iterator(0, _root, name_));
+	}
+
+	PUGI__FN xml_object_range<xml_attribute_iterator> xml_node::attributes() const
+	{
+		return xml_object_range<xml_attribute_iterator>(attributes_begin(), attributes_end());
+	}
+
+	PUGI__FN bool xml_node::operator==(const xml_node& r) const
+	{
+		return (_root == r._root);
+	}
+
+	PUGI__FN bool xml_node::operator!=(const xml_node& r) const
+	{
+		return (_root != r._root);
+	}
+
+	PUGI__FN bool xml_node::operator<(const xml_node& r) const
+	{
+		return (_root < r._root);
+	}
+
+	PUGI__FN bool xml_node::operator>(const xml_node& r) const
+	{
+		return (_root > r._root);
+	}
+
+	PUGI__FN bool xml_node::operator<=(const xml_node& r) const
+	{
+		return (_root <= r._root);
+	}
+
+	PUGI__FN bool xml_node::operator>=(const xml_node& r) const
+	{
+		return (_root >= r._root);
+	}
+
+	PUGI__FN bool xml_node::empty() const
+	{
+		return !_root;
+	}
+
+	PUGI__FN const char_t* xml_node::name() const
+	{
+		return (_root && _root->name) ? _root->name + 0 : PUGIXML_TEXT("");
+	}
+
+	PUGI__FN xml_node_type xml_node::type() const
+	{
+		return _root ? PUGI__NODETYPE(_root) : node_null;
+	}
+
+	PUGI__FN const char_t* xml_node::value() const
+	{
+		return (_root && _root->value) ? _root->value + 0 : PUGIXML_TEXT("");
+	}
+
+	PUGI__FN xml_node xml_node::child(const char_t* name_) const
+	{
+		if (!_root) return xml_node();
+
+		for (xml_node_struct* i = _root->first_child; i; i = i->next_sibling)
+			if (i->name && impl::strequal(name_, i->name)) return xml_node(i);
+
+		return xml_node();
+	}
+
+	PUGI__FN xml_attribute xml_node::attribute(const char_t* name_) const
+	{
+		if (!_root) return xml_attribute();
+
+		for (xml_attribute_struct* i = _root->first_attribute; i; i = i->next_attribute)
+			if (i->name && impl::strequal(name_, i->name))
+				return xml_attribute(i);
+
+		return xml_attribute();
+	}
+
+	PUGI__FN xml_node xml_node::next_sibling(const char_t* name_) const
+	{
+		if (!_root) return xml_node();
+
+		for (xml_node_struct* i = _root->next_sibling; i; i = i->next_sibling)
+			if (i->name && impl::strequal(name_, i->name)) return xml_node(i);
+
+		return xml_node();
+	}
+
+	PUGI__FN xml_node xml_node::next_sibling() const
+	{
+		return _root ? xml_node(_root->next_sibling) : xml_node();
+	}
+
+	PUGI__FN xml_node xml_node::previous_sibling(const char_t* name_) const
+	{
+		if (!_root) return xml_node();
+
+		for (xml_node_struct* i = _root->prev_sibling_c; i->next_sibling; i = i->prev_sibling_c)
+			if (i->name && impl::strequal(name_, i->name)) return xml_node(i);
+
+		return xml_node();
+	}
+
+	PUGI__FN xml_attribute xml_node::attribute(const char_t* name_, xml_attribute& hint_) const
+	{
+		xml_attribute_struct* hint = hint_._attr;
+
+		// if hint is not an attribute of node, behavior is not defined
+		assert(!hint || (_root && impl::is_attribute_of(hint, _root)));
+
+		if (!_root) return xml_attribute();
+
+		// optimistically search from hint up until the end
+		for (xml_attribute_struct* i = hint; i; i = i->next_attribute)
+			if (i->name && impl::strequal(name_, i->name))
+			{
+				// update hint to maximize efficiency of searching for consecutive attributes
+				hint_._attr = i->next_attribute;
+
+				return xml_attribute(i);
+			}
+
+		// wrap around and search from the first attribute until the hint
+		// 'j' null pointer check is technically redundant, but it prevents a crash in case the assertion above fails
+		for (xml_attribute_struct* j = _root->first_attribute; j && j != hint; j = j->next_attribute)
+			if (j->name && impl::strequal(name_, j->name))
+			{
+				// update hint to maximize efficiency of searching for consecutive attributes
+				hint_._attr = j->next_attribute;
+
+				return xml_attribute(j);
+			}
+
+		return xml_attribute();
+	}
+
+	PUGI__FN xml_node xml_node::previous_sibling() const
+	{
+		if (!_root) return xml_node();
+
+		if (_root->prev_sibling_c->next_sibling) return xml_node(_root->prev_sibling_c);
+		else return xml_node();
+	}
+
+	PUGI__FN xml_node xml_node::parent() const
+	{
+		return _root ? xml_node(_root->parent) : xml_node();
+	}
+
+	PUGI__FN xml_node xml_node::root() const
+	{
+		return _root ? xml_node(&impl::get_document(_root)) : xml_node();
+	}
+
+	PUGI__FN xml_text xml_node::text() const
+	{
+		return xml_text(_root);
+	}
+
+	PUGI__FN const char_t* xml_node::child_value() const
+	{
+		if (!_root) return PUGIXML_TEXT("");
+
+		// element nodes can have value if parse_embed_pcdata was used
+		if (PUGI__NODETYPE(_root) == node_element && _root->value)
+			return _root->value;
+
+		for (xml_node_struct* i = _root->first_child; i; i = i->next_sibling)
+			if (impl::is_text_node(i) && i->value)
+				return i->value;
+
+		return PUGIXML_TEXT("");
+	}
+
+	PUGI__FN const char_t* xml_node::child_value(const char_t* name_) const
+	{
+		return child(name_).child_value();
+	}
+
+	PUGI__FN xml_attribute xml_node::first_attribute() const
+	{
+		return _root ? xml_attribute(_root->first_attribute) : xml_attribute();
+	}
+
+	PUGI__FN xml_attribute xml_node::last_attribute() const
+	{
+		return _root && _root->first_attribute ? xml_attribute(_root->first_attribute->prev_attribute_c) : xml_attribute();
+	}
+
+	PUGI__FN xml_node xml_node::first_child() const
+	{
+		return _root ? xml_node(_root->first_child) : xml_node();
+	}
+
+	PUGI__FN xml_node xml_node::last_child() const
+	{
+		return _root && _root->first_child ? xml_node(_root->first_child->prev_sibling_c) : xml_node();
+	}
+
+	PUGI__FN bool xml_node::set_name(const char_t* rhs)
+	{
+		xml_node_type type_ = _root ? PUGI__NODETYPE(_root) : node_null;
+
+		if (type_ != node_element && type_ != node_pi && type_ != node_declaration)
+			return false;
+
+		return impl::strcpy_insitu(_root->name, _root->header, impl::xml_memory_page_name_allocated_mask, rhs, impl::strlength(rhs));
+	}
+
+	PUGI__FN bool xml_node::set_value(const char_t* rhs)
+	{
+		xml_node_type type_ = _root ? PUGI__NODETYPE(_root) : node_null;
+
+		if (type_ != node_pcdata && type_ != node_cdata && type_ != node_comment && type_ != node_pi && type_ != node_doctype)
+			return false;
+
+		return impl::strcpy_insitu(_root->value, _root->header, impl::xml_memory_page_value_allocated_mask, rhs, impl::strlength(rhs));
+	}
+
+	PUGI__FN xml_attribute xml_node::append_attribute(const char_t* name_)
+	{
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::append_attribute(a._attr, _root);
+
+		a.set_name(name_);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::prepend_attribute(const char_t* name_)
+	{
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::prepend_attribute(a._attr, _root);
+
+		a.set_name(name_);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::insert_attribute_after(const char_t* name_, const xml_attribute& attr)
+	{
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+		if (!attr || !impl::is_attribute_of(attr._attr, _root)) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::insert_attribute_after(a._attr, attr._attr, _root);
+
+		a.set_name(name_);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::insert_attribute_before(const char_t* name_, const xml_attribute& attr)
+	{
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+		if (!attr || !impl::is_attribute_of(attr._attr, _root)) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::insert_attribute_before(a._attr, attr._attr, _root);
+
+		a.set_name(name_);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::append_copy(const xml_attribute& proto)
+	{
+		if (!proto) return xml_attribute();
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::append_attribute(a._attr, _root);
+		impl::node_copy_attribute(a._attr, proto._attr);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::prepend_copy(const xml_attribute& proto)
+	{
+		if (!proto) return xml_attribute();
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::prepend_attribute(a._attr, _root);
+		impl::node_copy_attribute(a._attr, proto._attr);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::insert_copy_after(const xml_attribute& proto, const xml_attribute& attr)
+	{
+		if (!proto) return xml_attribute();
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+		if (!attr || !impl::is_attribute_of(attr._attr, _root)) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::insert_attribute_after(a._attr, attr._attr, _root);
+		impl::node_copy_attribute(a._attr, proto._attr);
+
+		return a;
+	}
+
+	PUGI__FN xml_attribute xml_node::insert_copy_before(const xml_attribute& proto, const xml_attribute& attr)
+	{
+		if (!proto) return xml_attribute();
+		if (!impl::allow_insert_attribute(type())) return xml_attribute();
+		if (!attr || !impl::is_attribute_of(attr._attr, _root)) return xml_attribute();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_attribute();
+
+		xml_attribute a(impl::allocate_attribute(alloc));
+		if (!a) return xml_attribute();
+
+		impl::insert_attribute_before(a._attr, attr._attr, _root);
+		impl::node_copy_attribute(a._attr, proto._attr);
+
+		return a;
+	}
+
+	PUGI__FN xml_node xml_node::append_child(xml_node_type type_)
+	{
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::append_node(n._root, _root);
+
+		if (type_ == node_declaration) n.set_name(PUGIXML_TEXT("xml"));
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::prepend_child(xml_node_type type_)
+	{
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::prepend_node(n._root, _root);
+
+		if (type_ == node_declaration) n.set_name(PUGIXML_TEXT("xml"));
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::insert_child_before(xml_node_type type_, const xml_node& node)
+	{
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+		if (!node._root || node._root->parent != _root) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::insert_node_before(n._root, node._root);
+
+		if (type_ == node_declaration) n.set_name(PUGIXML_TEXT("xml"));
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::insert_child_after(xml_node_type type_, const xml_node& node)
+	{
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+		if (!node._root || node._root->parent != _root) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::insert_node_after(n._root, node._root);
+
+		if (type_ == node_declaration) n.set_name(PUGIXML_TEXT("xml"));
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::append_child(const char_t* name_)
+	{
+		xml_node result = append_child(node_element);
+
+		result.set_name(name_);
+
+		return result;
+	}
+
+	PUGI__FN xml_node xml_node::prepend_child(const char_t* name_)
+	{
+		xml_node result = prepend_child(node_element);
+
+		result.set_name(name_);
+
+		return result;
+	}
+
+	PUGI__FN xml_node xml_node::insert_child_after(const char_t* name_, const xml_node& node)
+	{
+		xml_node result = insert_child_after(node_element, node);
+
+		result.set_name(name_);
+
+		return result;
+	}
+
+	PUGI__FN xml_node xml_node::insert_child_before(const char_t* name_, const xml_node& node)
+	{
+		xml_node result = insert_child_before(node_element, node);
+
+		result.set_name(name_);
+
+		return result;
+	}
+
+	PUGI__FN xml_node xml_node::append_copy(const xml_node& proto)
+	{
+		xml_node_type type_ = proto.type();
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::append_node(n._root, _root);
+		impl::node_copy_tree(n._root, proto._root);
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::prepend_copy(const xml_node& proto)
+	{
+		xml_node_type type_ = proto.type();
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::prepend_node(n._root, _root);
+		impl::node_copy_tree(n._root, proto._root);
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::insert_copy_after(const xml_node& proto, const xml_node& node)
+	{
+		xml_node_type type_ = proto.type();
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+		if (!node._root || node._root->parent != _root) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::insert_node_after(n._root, node._root);
+		impl::node_copy_tree(n._root, proto._root);
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::insert_copy_before(const xml_node& proto, const xml_node& node)
+	{
+		xml_node_type type_ = proto.type();
+		if (!impl::allow_insert_child(type(), type_)) return xml_node();
+		if (!node._root || node._root->parent != _root) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		xml_node n(impl::allocate_node(alloc, type_));
+		if (!n) return xml_node();
+
+		impl::insert_node_before(n._root, node._root);
+		impl::node_copy_tree(n._root, proto._root);
+
+		return n;
+	}
+
+	PUGI__FN xml_node xml_node::append_move(const xml_node& moved)
+	{
+		if (!impl::allow_move(*this, moved)) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		// disable document_buffer_order optimization since moving nodes around changes document order without changing buffer pointers
+		impl::get_document(_root).header |= impl::xml_memory_page_contents_shared_mask;
+
+		impl::remove_node(moved._root);
+		impl::append_node(moved._root, _root);
+
+		return moved;
+	}
+
+	PUGI__FN xml_node xml_node::prepend_move(const xml_node& moved)
+	{
+		if (!impl::allow_move(*this, moved)) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		// disable document_buffer_order optimization since moving nodes around changes document order without changing buffer pointers
+		impl::get_document(_root).header |= impl::xml_memory_page_contents_shared_mask;
+
+		impl::remove_node(moved._root);
+		impl::prepend_node(moved._root, _root);
+
+		return moved;
+	}
+
+	PUGI__FN xml_node xml_node::insert_move_after(const xml_node& moved, const xml_node& node)
+	{
+		if (!impl::allow_move(*this, moved)) return xml_node();
+		if (!node._root || node._root->parent != _root) return xml_node();
+		if (moved._root == node._root) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		// disable document_buffer_order optimization since moving nodes around changes document order without changing buffer pointers
+		impl::get_document(_root).header |= impl::xml_memory_page_contents_shared_mask;
+
+		impl::remove_node(moved._root);
+		impl::insert_node_after(moved._root, node._root);
+
+		return moved;
+	}
+
+	PUGI__FN xml_node xml_node::insert_move_before(const xml_node& moved, const xml_node& node)
+	{
+		if (!impl::allow_move(*this, moved)) return xml_node();
+		if (!node._root || node._root->parent != _root) return xml_node();
+		if (moved._root == node._root) return xml_node();
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return xml_node();
+
+		// disable document_buffer_order optimization since moving nodes around changes document order without changing buffer pointers
+		impl::get_document(_root).header |= impl::xml_memory_page_contents_shared_mask;
+
+		impl::remove_node(moved._root);
+		impl::insert_node_before(moved._root, node._root);
+
+		return moved;
+	}
+
+	PUGI__FN bool xml_node::remove_attribute(const char_t* name_)
+	{
+		return remove_attribute(attribute(name_));
+	}
+
+	PUGI__FN bool xml_node::remove_attribute(const xml_attribute& a)
+	{
+		if (!_root || !a._attr) return false;
+		if (!impl::is_attribute_of(a._attr, _root)) return false;
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return false;
+
+		impl::remove_attribute(a._attr, _root);
+		impl::destroy_attribute(a._attr, alloc);
+
+		return true;
+	}
+
+	PUGI__FN bool xml_node::remove_child(const char_t* name_)
+	{
+		return remove_child(child(name_));
+	}
+
+	PUGI__FN bool xml_node::remove_child(const xml_node& n)
+	{
+		if (!_root || !n._root || n._root->parent != _root) return false;
+
+		impl::xml_allocator& alloc = impl::get_allocator(_root);
+		if (!alloc.reserve()) return false;
+
+		impl::remove_node(n._root);
+		impl::destroy_node(n._root, alloc);
+
+		return true;
+	}
+
+	PUGI__FN xml_parse_result xml_node::append_buffer(const void* contents, size_t size, unsigned int options, xml_encoding encoding)
+	{
+		// append_buffer is only valid for elements/documents
+		if (!impl::allow_insert_child(type(), node_element)) return impl::make_parse_result(status_append_invalid_root);
+
+		// get document node
+		impl::xml_document_struct* doc = &impl::get_document(_root);
+
+		// disable document_buffer_order optimization since in a document with multiple buffers comparing buffer pointers does not make sense
+		doc->header |= impl::xml_memory_page_contents_shared_mask;
+
+		// get extra buffer element (we'll store the document fragment buffer there so that we can deallocate it later)
+		impl::xml_memory_page* page = 0;
+		impl::xml_extra_buffer* extra = static_cast<impl::xml_extra_buffer*>(doc->allocate_memory(sizeof(impl::xml_extra_buffer), page));
+		(void)page;
+
+		if (!extra) return impl::make_parse_result(status_out_of_memory);
+
+		// add extra buffer to the list
+		extra->buffer = 0;
+		extra->next = doc->extra_buffers;
+		doc->extra_buffers = extra;
+
+		// name of the root has to be NULL before parsing - otherwise closing node mismatches will not be detected at the top level
+		impl::name_null_sentry sentry(_root);
+
+		return impl::load_buffer_impl(doc, _root, const_cast<void*>(contents), size, options, encoding, false, false, &extra->buffer);
+	}
+
+	PUGI__FN xml_node xml_node::find_child_by_attribute(const char_t* name_, const char_t* attr_name, const char_t* attr_value) const
+	{
+		if (!_root) return xml_node();
+
+		for (xml_node_struct* i = _root->first_child; i; i = i->next_sibling)
+			if (i->name && impl::strequal(name_, i->name))
+			{
+				for (xml_attribute_struct* a = i->first_attribute; a; a = a->next_attribute)
+					if (a->name && impl::strequal(attr_name, a->name) && impl::strequal(attr_value, a->value ? a->value + 0 : PUGIXML_TEXT("")))
+						return xml_node(i);
+			}
+
+		return xml_node();
+	}
+
+	PUGI__FN xml_node xml_node::find_child_by_attribute(const char_t* attr_name, const char_t* attr_value) const
+	{
+		if (!_root) return xml_node();
+
+		for (xml_node_struct* i = _root->first_child; i; i = i->next_sibling)
+			for (xml_attribute_struct* a = i->first_attribute; a; a = a->next_attribute)
+				if (a->name && impl::strequal(attr_name, a->name) && impl::strequal(attr_value, a->value ? a->value + 0 : PUGIXML_TEXT("")))
+					return xml_node(i);
+
+		return xml_node();
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN string_t xml_node::path(char_t delimiter) const
+	{
+		if (!_root) return string_t();
+
+		size_t offset = 0;
+
+		for (xml_node_struct* i = _root; i; i = i->parent)
+		{
+			offset += (i != _root);
+			offset += i->name ? impl::strlength(i->name) : 0;
+		}
+
+		string_t result;
+		result.resize(offset);
+
+		for (xml_node_struct* j = _root; j; j = j->parent)
+		{
+			if (j != _root)
+				result[--offset] = delimiter;
+
+			if (j->name && *j->name)
+			{
+				size_t length = impl::strlength(j->name);
+
+				offset -= length;
+				memcpy(&result[offset], j->name, length * sizeof(char_t));
+			}
+		}
+
+		assert(offset == 0);
+
+		return result;
+	}
+#endif
+
+	PUGI__FN xml_node xml_node::first_element_by_path(const char_t* path_, char_t delimiter) const
+	{
+		xml_node found = *this; // Current search context.
+
+		if (!_root || !path_ || !path_[0]) return found;
+
+		if (path_[0] == delimiter)
+		{
+			// Absolute path; e.g. '/foo/bar'
+			found = found.root();
+			++path_;
+		}
+
+		const char_t* path_segment = path_;
+
+		while (*path_segment == delimiter) ++path_segment;
+
+		const char_t* path_segment_end = path_segment;
+
+		while (*path_segment_end && *path_segment_end != delimiter) ++path_segment_end;
+
+		if (path_segment == path_segment_end) return found;
+
+		const char_t* next_segment = path_segment_end;
+
+		while (*next_segment == delimiter) ++next_segment;
+
+		if (*path_segment == '.' && path_segment + 1 == path_segment_end)
+			return found.first_element_by_path(next_segment, delimiter);
+		else if (*path_segment == '.' && *(path_segment+1) == '.' && path_segment + 2 == path_segment_end)
+			return found.parent().first_element_by_path(next_segment, delimiter);
+		else
+		{
+			for (xml_node_struct* j = found._root->first_child; j; j = j->next_sibling)
+			{
+				if (j->name && impl::strequalrange(j->name, path_segment, static_cast<size_t>(path_segment_end - path_segment)))
+				{
+					xml_node subsearch = xml_node(j).first_element_by_path(next_segment, delimiter);
+
+					if (subsearch) return subsearch;
+				}
+			}
+
+			return xml_node();
+		}
+	}
+
+	PUGI__FN bool xml_node::traverse(xml_tree_walker& walker)
+	{
+		walker._depth = -1;
+
+		xml_node arg_begin = *this;
+		if (!walker.begin(arg_begin)) return false;
+
+		xml_node cur = first_child();
+
+		if (cur)
+		{
+			++walker._depth;
+
+			do
+			{
+				xml_node arg_for_each = cur;
+				if (!walker.for_each(arg_for_each))
+					return false;
+
+				if (cur.first_child())
+				{
+					++walker._depth;
+					cur = cur.first_child();
+				}
+				else if (cur.next_sibling())
+					cur = cur.next_sibling();
+				else
+				{
+					// Borland C++ workaround
+					while (!cur.next_sibling() && cur != *this && !cur.parent().empty())
+					{
+						--walker._depth;
+						cur = cur.parent();
+					}
+
+					if (cur != *this)
+						cur = cur.next_sibling();
+				}
+			}
+			while (cur && cur != *this);
+		}
+
+		assert(walker._depth == -1);
+
+		xml_node arg_end = *this;
+		return walker.end(arg_end);
+	}
+
+	PUGI__FN size_t xml_node::hash_value() const
+	{
+		return static_cast<size_t>(reinterpret_cast<uintptr_t>(_root) / sizeof(xml_node_struct));
+	}
+
+	PUGI__FN xml_node_struct* xml_node::internal_object() const
+	{
+		return _root;
+	}
+
+	PUGI__FN void xml_node::print(xml_writer& writer, const char_t* indent, unsigned int flags, xml_encoding encoding, unsigned int depth) const
+	{
+		if (!_root) return;
+
+		impl::xml_buffered_writer buffered_writer(writer, encoding);
+
+		impl::node_output(buffered_writer, _root, indent, flags, depth);
+
+		buffered_writer.flush();
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN void xml_node::print(std::basic_ostream<char, std::char_traits<char> >& stream, const char_t* indent, unsigned int flags, xml_encoding encoding, unsigned int depth) const
+	{
+		xml_writer_stream writer(stream);
+
+		print(writer, indent, flags, encoding, depth);
+	}
+
+	PUGI__FN void xml_node::print(std::basic_ostream<wchar_t, std::char_traits<wchar_t> >& stream, const char_t* indent, unsigned int flags, unsigned int depth) const
+	{
+		xml_writer_stream writer(stream);
+
+		print(writer, indent, flags, encoding_wchar, depth);
+	}
+#endif
+
+	PUGI__FN ptrdiff_t xml_node::offset_debug() const
+	{
+		if (!_root) return -1;
+
+		impl::xml_document_struct& doc = impl::get_document(_root);
+
+		// we can determine the offset reliably only if there is exactly once parse buffer
+		if (!doc.buffer || doc.extra_buffers) return -1;
+
+		switch (type())
+		{
+		case node_document:
+			return 0;
+
+		case node_element:
+		case node_declaration:
+		case node_pi:
+			return _root->name && (_root->header & impl::xml_memory_page_name_allocated_or_shared_mask) == 0 ? _root->name - doc.buffer : -1;
+
+		case node_pcdata:
+		case node_cdata:
+		case node_comment:
+		case node_doctype:
+			return _root->value && (_root->header & impl::xml_memory_page_value_allocated_or_shared_mask) == 0 ? _root->value - doc.buffer : -1;
+
+		default:
+			return -1;
+		}
+	}
+
+#ifdef __BORLANDC__
+	PUGI__FN bool operator&&(const xml_node& lhs, bool rhs)
+	{
+		return (bool)lhs && rhs;
+	}
+
+	PUGI__FN bool operator||(const xml_node& lhs, bool rhs)
+	{
+		return (bool)lhs || rhs;
+	}
+#endif
+
+	PUGI__FN xml_text::xml_text(xml_node_struct* root): _root(root)
+	{
+	}
+
+	PUGI__FN xml_node_struct* xml_text::_data() const
+	{
+		if (!_root || impl::is_text_node(_root)) return _root;
+
+		// element nodes can have value if parse_embed_pcdata was used
+		if (PUGI__NODETYPE(_root) == node_element && _root->value)
+			return _root;
+
+		for (xml_node_struct* node = _root->first_child; node; node = node->next_sibling)
+			if (impl::is_text_node(node))
+				return node;
+
+		return 0;
+	}
+
+	PUGI__FN xml_node_struct* xml_text::_data_new()
+	{
+		xml_node_struct* d = _data();
+		if (d) return d;
+
+		return xml_node(_root).append_child(node_pcdata).internal_object();
+	}
+
+	PUGI__FN xml_text::xml_text(): _root(0)
+	{
+	}
+
+	PUGI__FN static void unspecified_bool_xml_text(xml_text***)
+	{
+	}
+
+	PUGI__FN xml_text::operator xml_text::unspecified_bool_type() const
+	{
+		return _data() ? unspecified_bool_xml_text : 0;
+	}
+
+	PUGI__FN bool xml_text::operator!() const
+	{
+		return !_data();
+	}
+
+	PUGI__FN bool xml_text::empty() const
+	{
+		return _data() == 0;
+	}
+
+	PUGI__FN const char_t* xml_text::get() const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? d->value + 0 : PUGIXML_TEXT("");
+	}
+
+	PUGI__FN const char_t* xml_text::as_string(const char_t* def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? d->value + 0 : def;
+	}
+
+	PUGI__FN int xml_text::as_int(int def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_int(d->value) : def;
+	}
+
+	PUGI__FN unsigned int xml_text::as_uint(unsigned int def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_uint(d->value) : def;
+	}
+
+	PUGI__FN double xml_text::as_double(double def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_double(d->value) : def;
+	}
+
+	PUGI__FN float xml_text::as_float(float def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_float(d->value) : def;
+	}
+
+	PUGI__FN bool xml_text::as_bool(bool def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_bool(d->value) : def;
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN long long xml_text::as_llong(long long def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_llong(d->value) : def;
+	}
+
+	PUGI__FN unsigned long long xml_text::as_ullong(unsigned long long def) const
+	{
+		xml_node_struct* d = _data();
+
+		return (d && d->value) ? impl::get_value_ullong(d->value) : def;
+	}
+#endif
+
+	PUGI__FN bool xml_text::set(const char_t* rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::strcpy_insitu(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, impl::strlength(rhs)) : false;
+	}
+
+	PUGI__FN bool xml_text::set(int rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_integer<unsigned int>(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, rhs < 0) : false;
+	}
+
+	PUGI__FN bool xml_text::set(unsigned int rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_integer<unsigned int>(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, false) : false;
+	}
+
+	PUGI__FN bool xml_text::set(long rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_integer<unsigned long>(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, rhs < 0) : false;
+	}
+
+	PUGI__FN bool xml_text::set(unsigned long rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_integer<unsigned long>(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, false) : false;
+	}
+
+	PUGI__FN bool xml_text::set(float rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_convert(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs) : false;
+	}
+
+	PUGI__FN bool xml_text::set(double rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_convert(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs) : false;
+	}
+
+	PUGI__FN bool xml_text::set(bool rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_bool(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs) : false;
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN bool xml_text::set(long long rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_integer<unsigned long long>(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, rhs < 0) : false;
+	}
+
+	PUGI__FN bool xml_text::set(unsigned long long rhs)
+	{
+		xml_node_struct* dn = _data_new();
+
+		return dn ? impl::set_value_integer<unsigned long long>(dn->value, dn->header, impl::xml_memory_page_value_allocated_mask, rhs, false) : false;
+	}
+#endif
+
+	PUGI__FN xml_text& xml_text::operator=(const char_t* rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(int rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(unsigned int rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(long rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(unsigned long rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(double rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(float rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(bool rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+#ifdef PUGIXML_HAS_LONG_LONG
+	PUGI__FN xml_text& xml_text::operator=(long long rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+
+	PUGI__FN xml_text& xml_text::operator=(unsigned long long rhs)
+	{
+		set(rhs);
+		return *this;
+	}
+#endif
+
+	PUGI__FN xml_node xml_text::data() const
+	{
+		return xml_node(_data());
+	}
+
+#ifdef __BORLANDC__
+	PUGI__FN bool operator&&(const xml_text& lhs, bool rhs)
+	{
+		return (bool)lhs && rhs;
+	}
+
+	PUGI__FN bool operator||(const xml_text& lhs, bool rhs)
+	{
+		return (bool)lhs || rhs;
+	}
+#endif
+
+	PUGI__FN xml_node_iterator::xml_node_iterator()
+	{
+	}
+
+	PUGI__FN xml_node_iterator::xml_node_iterator(const xml_node& node): _wrap(node), _parent(node.parent())
+	{
+	}
+
+	PUGI__FN xml_node_iterator::xml_node_iterator(xml_node_struct* ref, xml_node_struct* parent): _wrap(ref), _parent(parent)
+	{
+	}
+
+	PUGI__FN bool xml_node_iterator::operator==(const xml_node_iterator& rhs) const
+	{
+		return _wrap._root == rhs._wrap._root && _parent._root == rhs._parent._root;
+	}
+
+	PUGI__FN bool xml_node_iterator::operator!=(const xml_node_iterator& rhs) const
+	{
+		return _wrap._root != rhs._wrap._root || _parent._root != rhs._parent._root;
+	}
+
+	PUGI__FN xml_node& xml_node_iterator::operator*() const
+	{
+		assert(_wrap._root);
+		return _wrap;
+	}
+
+	PUGI__FN xml_node* xml_node_iterator::operator->() const
+	{
+		assert(_wrap._root);
+		return const_cast<xml_node*>(&_wrap); // BCC5 workaround
+	}
+
+	PUGI__FN const xml_node_iterator& xml_node_iterator::operator++()
+	{
+		assert(_wrap._root);
+		_wrap._root = _wrap._root->next_sibling;
+		return *this;
+	}
+
+	PUGI__FN xml_node_iterator xml_node_iterator::operator++(int)
+	{
+		xml_node_iterator temp = *this;
+		++*this;
+		return temp;
+	}
+
+	PUGI__FN const xml_node_iterator& xml_node_iterator::operator--()
+	{
+		_wrap = _wrap._root ? _wrap.previous_sibling() : _parent.last_child();
+		return *this;
+	}
+
+	PUGI__FN xml_node_iterator xml_node_iterator::operator--(int)
+	{
+		xml_node_iterator temp = *this;
+		--*this;
+		return temp;
+	}
+
+	PUGI__FN xml_attribute_iterator::xml_attribute_iterator()
+	{
+	}
+
+	PUGI__FN xml_attribute_iterator::xml_attribute_iterator(const xml_attribute& attr, const xml_node& parent): _wrap(attr), _parent(parent)
+	{
+	}
+
+	PUGI__FN xml_attribute_iterator::xml_attribute_iterator(xml_attribute_struct* ref, xml_node_struct* parent): _wrap(ref), _parent(parent)
+	{
+	}
+
+	PUGI__FN bool xml_attribute_iterator::operator==(const xml_attribute_iterator& rhs) const
+	{
+		return _wrap._attr == rhs._wrap._attr && _parent._root == rhs._parent._root;
+	}
+
+	PUGI__FN bool xml_attribute_iterator::operator!=(const xml_attribute_iterator& rhs) const
+	{
+		return _wrap._attr != rhs._wrap._attr || _parent._root != rhs._parent._root;
+	}
+
+	PUGI__FN xml_attribute& xml_attribute_iterator::operator*() const
+	{
+		assert(_wrap._attr);
+		return _wrap;
+	}
+
+	PUGI__FN xml_attribute* xml_attribute_iterator::operator->() const
+	{
+		assert(_wrap._attr);
+		return const_cast<xml_attribute*>(&_wrap); // BCC5 workaround
+	}
+
+	PUGI__FN const xml_attribute_iterator& xml_attribute_iterator::operator++()
+	{
+		assert(_wrap._attr);
+		_wrap._attr = _wrap._attr->next_attribute;
+		return *this;
+	}
+
+	PUGI__FN xml_attribute_iterator xml_attribute_iterator::operator++(int)
+	{
+		xml_attribute_iterator temp = *this;
+		++*this;
+		return temp;
+	}
+
+	PUGI__FN const xml_attribute_iterator& xml_attribute_iterator::operator--()
+	{
+		_wrap = _wrap._attr ? _wrap.previous_attribute() : _parent.last_attribute();
+		return *this;
+	}
+
+	PUGI__FN xml_attribute_iterator xml_attribute_iterator::operator--(int)
+	{
+		xml_attribute_iterator temp = *this;
+		--*this;
+		return temp;
+	}
+
+	PUGI__FN xml_named_node_iterator::xml_named_node_iterator(): _name(0)
+	{
+	}
+
+	PUGI__FN xml_named_node_iterator::xml_named_node_iterator(const xml_node& node, const char_t* name): _wrap(node), _parent(node.parent()), _name(name)
+	{
+	}
+
+	PUGI__FN xml_named_node_iterator::xml_named_node_iterator(xml_node_struct* ref, xml_node_struct* parent, const char_t* name): _wrap(ref), _parent(parent), _name(name)
+	{
+	}
+
+	PUGI__FN bool xml_named_node_iterator::operator==(const xml_named_node_iterator& rhs) const
+	{
+		return _wrap._root == rhs._wrap._root && _parent._root == rhs._parent._root;
+	}
+
+	PUGI__FN bool xml_named_node_iterator::operator!=(const xml_named_node_iterator& rhs) const
+	{
+		return _wrap._root != rhs._wrap._root || _parent._root != rhs._parent._root;
+	}
+
+	PUGI__FN xml_node& xml_named_node_iterator::operator*() const
+	{
+		assert(_wrap._root);
+		return _wrap;
+	}
+
+	PUGI__FN xml_node* xml_named_node_iterator::operator->() const
+	{
+		assert(_wrap._root);
+		return const_cast<xml_node*>(&_wrap); // BCC5 workaround
+	}
+
+	PUGI__FN const xml_named_node_iterator& xml_named_node_iterator::operator++()
+	{
+		assert(_wrap._root);
+		_wrap = _wrap.next_sibling(_name);
+		return *this;
+	}
+
+	PUGI__FN xml_named_node_iterator xml_named_node_iterator::operator++(int)
+	{
+		xml_named_node_iterator temp = *this;
+		++*this;
+		return temp;
+	}
+
+	PUGI__FN const xml_named_node_iterator& xml_named_node_iterator::operator--()
+	{
+		if (_wrap._root)
+			_wrap = _wrap.previous_sibling(_name);
+		else
+		{
+			_wrap = _parent.last_child();
+
+			if (!impl::strequal(_wrap.name(), _name))
+				_wrap = _wrap.previous_sibling(_name);
+		}
+
+		return *this;
+	}
+
+	PUGI__FN xml_named_node_iterator xml_named_node_iterator::operator--(int)
+	{
+		xml_named_node_iterator temp = *this;
+		--*this;
+		return temp;
+	}
+
+	PUGI__FN xml_parse_result::xml_parse_result(): status(status_internal_error), offset(0), encoding(encoding_auto)
+	{
+	}
+
+	PUGI__FN xml_parse_result::operator bool() const
+	{
+		return status == status_ok;
+	}
+
+	PUGI__FN const char* xml_parse_result::description() const
+	{
+		switch (status)
+		{
+		case status_ok: return "No error";
+
+		case status_file_not_found: return "File was not found";
+		case status_io_error: return "Error reading from file/stream";
+		case status_out_of_memory: return "Could not allocate memory";
+		case status_internal_error: return "Internal error occurred";
+
+		case status_unrecognized_tag: return "Could not determine tag type";
+
+		case status_bad_pi: return "Error parsing document declaration/processing instruction";
+		case status_bad_comment: return "Error parsing comment";
+		case status_bad_cdata: return "Error parsing CDATA section";
+		case status_bad_doctype: return "Error parsing document type declaration";
+		case status_bad_pcdata: return "Error parsing PCDATA section";
+		case status_bad_start_element: return "Error parsing start element tag";
+		case status_bad_attribute: return "Error parsing element attribute";
+		case status_bad_end_element: return "Error parsing end element tag";
+		case status_end_element_mismatch: return "Start-end tags mismatch";
+
+		case status_append_invalid_root: return "Unable to append nodes: root is not an element or document";
+
+		case status_no_document_element: return "No document element found";
+
+		default: return "Unknown error";
+		}
+	}
+
+	PUGI__FN xml_document::xml_document(): _buffer(0)
+	{
+		_create();
+	}
+
+	PUGI__FN xml_document::~xml_document()
+	{
+		_destroy();
+	}
+
+	PUGI__FN void xml_document::reset()
+	{
+		_destroy();
+		_create();
+	}
+
+	PUGI__FN void xml_document::reset(const xml_document& proto)
+	{
+		reset();
+
+		for (xml_node cur = proto.first_child(); cur; cur = cur.next_sibling())
+			append_copy(cur);
+	}
+
+	PUGI__FN void xml_document::_create()
+	{
+		assert(!_root);
+
+	#ifdef PUGIXML_COMPACT
+		const size_t page_offset = sizeof(uint32_t);
+	#else
+		const size_t page_offset = 0;
+	#endif
+
+		// initialize sentinel page
+		PUGI__STATIC_ASSERT(sizeof(impl::xml_memory_page) + sizeof(impl::xml_document_struct) + page_offset <= sizeof(_memory));
+
+		// prepare page structure
+		impl::xml_memory_page* page = impl::xml_memory_page::construct(_memory);
+		assert(page);
+
+		page->busy_size = impl::xml_memory_page_size;
+
+		// setup first page marker
+	#ifdef PUGIXML_COMPACT
+		// round-trip through void* to avoid 'cast increases required alignment of target type' warning
+		page->compact_page_marker = reinterpret_cast<uint32_t*>(static_cast<void*>(reinterpret_cast<char*>(page) + sizeof(impl::xml_memory_page)));
+		*page->compact_page_marker = sizeof(impl::xml_memory_page);
+	#endif
+
+		// allocate new root
+		_root = new (reinterpret_cast<char*>(page) + sizeof(impl::xml_memory_page) + page_offset) impl::xml_document_struct(page);
+		_root->prev_sibling_c = _root;
+
+		// setup sentinel page
+		page->allocator = static_cast<impl::xml_document_struct*>(_root);
+
+		// setup hash table pointer in allocator
+	#ifdef PUGIXML_COMPACT
+		page->allocator->_hash = &static_cast<impl::xml_document_struct*>(_root)->hash;
+	#endif
+
+		// verify the document allocation
+		assert(reinterpret_cast<char*>(_root) + sizeof(impl::xml_document_struct) <= _memory + sizeof(_memory));
+	}
+
+	PUGI__FN void xml_document::_destroy()
+	{
+		assert(_root);
+
+		// destroy static storage
+		if (_buffer)
+		{
+			impl::xml_memory::deallocate(_buffer);
+			_buffer = 0;
+		}
+
+		// destroy extra buffers (note: no need to destroy linked list nodes, they're allocated using document allocator)
+		for (impl::xml_extra_buffer* extra = static_cast<impl::xml_document_struct*>(_root)->extra_buffers; extra; extra = extra->next)
+		{
+			if (extra->buffer) impl::xml_memory::deallocate(extra->buffer);
+		}
+
+		// destroy dynamic storage, leave sentinel page (it's in static memory)
+		impl::xml_memory_page* root_page = PUGI__GETPAGE(_root);
+		assert(root_page && !root_page->prev);
+		assert(reinterpret_cast<char*>(root_page) >= _memory && reinterpret_cast<char*>(root_page) < _memory + sizeof(_memory));
+
+		for (impl::xml_memory_page* page = root_page->next; page; )
+		{
+			impl::xml_memory_page* next = page->next;
+
+			impl::xml_allocator::deallocate_page(page);
+
+			page = next;
+		}
+
+	#ifdef PUGIXML_COMPACT
+		// destroy hash table
+		static_cast<impl::xml_document_struct*>(_root)->hash.clear();
+	#endif
+
+		_root = 0;
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN xml_parse_result xml_document::load(std::basic_istream<char, std::char_traits<char> >& stream, unsigned int options, xml_encoding encoding)
+	{
+		reset();
+
+		return impl::load_stream_impl(static_cast<impl::xml_document_struct*>(_root), stream, options, encoding, &_buffer);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load(std::basic_istream<wchar_t, std::char_traits<wchar_t> >& stream, unsigned int options)
+	{
+		reset();
+
+		return impl::load_stream_impl(static_cast<impl::xml_document_struct*>(_root), stream, options, encoding_wchar, &_buffer);
+	}
+#endif
+
+	PUGI__FN xml_parse_result xml_document::load_string(const char_t* contents, unsigned int options)
+	{
+		// Force native encoding (skip autodetection)
+	#ifdef PUGIXML_WCHAR_MODE
+		xml_encoding encoding = encoding_wchar;
+	#else
+		xml_encoding encoding = encoding_utf8;
+	#endif
+
+		return load_buffer(contents, impl::strlength(contents) * sizeof(char_t), options, encoding);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load(const char_t* contents, unsigned int options)
+	{
+		return load_string(contents, options);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load_file(const char* path_, unsigned int options, xml_encoding encoding)
+	{
+		reset();
+
+		using impl::auto_deleter; // MSVC7 workaround
+		auto_deleter<FILE> file(fopen(path_, "rb"), impl::close_file);
+
+		return impl::load_file_impl(static_cast<impl::xml_document_struct*>(_root), file.data, options, encoding, &_buffer);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load_file(const wchar_t* path_, unsigned int options, xml_encoding encoding)
+	{
+		reset();
+
+		using impl::auto_deleter; // MSVC7 workaround
+		auto_deleter<FILE> file(impl::open_file_wide(path_, L"rb"), impl::close_file);
+
+		return impl::load_file_impl(static_cast<impl::xml_document_struct*>(_root), file.data, options, encoding, &_buffer);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load_buffer(const void* contents, size_t size, unsigned int options, xml_encoding encoding)
+	{
+		reset();
+
+		return impl::load_buffer_impl(static_cast<impl::xml_document_struct*>(_root), _root, const_cast<void*>(contents), size, options, encoding, false, false, &_buffer);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load_buffer_inplace(void* contents, size_t size, unsigned int options, xml_encoding encoding)
+	{
+		reset();
+
+		return impl::load_buffer_impl(static_cast<impl::xml_document_struct*>(_root), _root, contents, size, options, encoding, true, false, &_buffer);
+	}
+
+	PUGI__FN xml_parse_result xml_document::load_buffer_inplace_own(void* contents, size_t size, unsigned int options, xml_encoding encoding)
+	{
+		reset();
+
+		return impl::load_buffer_impl(static_cast<impl::xml_document_struct*>(_root), _root, contents, size, options, encoding, true, true, &_buffer);
+	}
+
+	PUGI__FN void xml_document::save(xml_writer& writer, const char_t* indent, unsigned int flags, xml_encoding encoding) const
+	{
+		impl::xml_buffered_writer buffered_writer(writer, encoding);
+
+		if ((flags & format_write_bom) && encoding != encoding_latin1)
+		{
+			// BOM always represents the codepoint U+FEFF, so just write it in native encoding
+		#ifdef PUGIXML_WCHAR_MODE
+			unsigned int bom = 0xfeff;
+			buffered_writer.write(static_cast<wchar_t>(bom));
+		#else
+			buffered_writer.write('\xef', '\xbb', '\xbf');
+		#endif
+		}
+
+		if (!(flags & format_no_declaration) && !impl::has_declaration(_root))
+		{
+			buffered_writer.write_string(PUGIXML_TEXT("<?xml version=\"1.0\""));
+			if (encoding == encoding_latin1) buffered_writer.write_string(PUGIXML_TEXT(" encoding=\"ISO-8859-1\""));
+			buffered_writer.write('?', '>');
+			if (!(flags & format_raw)) buffered_writer.write('\n');
+		}
+
+		impl::node_output(buffered_writer, _root, indent, flags, 0);
+
+		buffered_writer.flush();
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN void xml_document::save(std::basic_ostream<char, std::char_traits<char> >& stream, const char_t* indent, unsigned int flags, xml_encoding encoding) const
+	{
+		xml_writer_stream writer(stream);
+
+		save(writer, indent, flags, encoding);
+	}
+
+	PUGI__FN void xml_document::save(std::basic_ostream<wchar_t, std::char_traits<wchar_t> >& stream, const char_t* indent, unsigned int flags) const
+	{
+		xml_writer_stream writer(stream);
+
+		save(writer, indent, flags, encoding_wchar);
+	}
+#endif
+
+	PUGI__FN bool xml_document::save_file(const char* path_, const char_t* indent, unsigned int flags, xml_encoding encoding) const
+	{
+		using impl::auto_deleter; // MSVC7 workaround
+		auto_deleter<FILE> file(fopen(path_, (flags & format_save_file_text) ? "w" : "wb"), impl::close_file);
+
+		return impl::save_file_impl(*this, file.data, indent, flags, encoding);
+	}
+
+	PUGI__FN bool xml_document::save_file(const wchar_t* path_, const char_t* indent, unsigned int flags, xml_encoding encoding) const
+	{
+		using impl::auto_deleter; // MSVC7 workaround
+		auto_deleter<FILE> file(impl::open_file_wide(path_, (flags & format_save_file_text) ? L"w" : L"wb"), impl::close_file);
+
+		return impl::save_file_impl(*this, file.data, indent, flags, encoding);
+	}
+
+	PUGI__FN xml_node xml_document::document_element() const
+	{
+		assert(_root);
+
+		for (xml_node_struct* i = _root->first_child; i; i = i->next_sibling)
+			if (PUGI__NODETYPE(i) == node_element)
+				return xml_node(i);
+
+		return xml_node();
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN std::string PUGIXML_FUNCTION as_utf8(const wchar_t* str)
+	{
+		assert(str);
+
+		return impl::as_utf8_impl(str, impl::strlength_wide(str));
+	}
+
+	PUGI__FN std::string PUGIXML_FUNCTION as_utf8(const std::basic_string<wchar_t>& str)
+	{
+		return impl::as_utf8_impl(str.c_str(), str.size());
+	}
+
+	PUGI__FN std::basic_string<wchar_t> PUGIXML_FUNCTION as_wide(const char* str)
+	{
+		assert(str);
+
+		return impl::as_wide_impl(str, strlen(str));
+	}
+
+	PUGI__FN std::basic_string<wchar_t> PUGIXML_FUNCTION as_wide(const std::string& str)
+	{
+		return impl::as_wide_impl(str.c_str(), str.size());
+	}
+#endif
+
+	PUGI__FN void PUGIXML_FUNCTION set_memory_management_functions(allocation_function allocate, deallocation_function deallocate)
+	{
+		impl::xml_memory::allocate = allocate;
+		impl::xml_memory::deallocate = deallocate;
+	}
+
+	PUGI__FN allocation_function PUGIXML_FUNCTION get_memory_allocation_function()
+	{
+		return impl::xml_memory::allocate;
+	}
+
+	PUGI__FN deallocation_function PUGIXML_FUNCTION get_memory_deallocation_function()
+	{
+		return impl::xml_memory::deallocate;
+	}
+}
+
+#if !defined(PUGIXML_NO_STL) && (defined(_MSC_VER) || defined(__ICC))
+namespace std
+{
+	// Workarounds for (non-standard) iterator category detection for older versions (MSVC7/IC8 and earlier)
+	PUGI__FN std::bidirectional_iterator_tag _Iter_cat(const pugi::xml_node_iterator&)
+	{
+		return std::bidirectional_iterator_tag();
+	}
+
+	PUGI__FN std::bidirectional_iterator_tag _Iter_cat(const pugi::xml_attribute_iterator&)
+	{
+		return std::bidirectional_iterator_tag();
+	}
+
+	PUGI__FN std::bidirectional_iterator_tag _Iter_cat(const pugi::xml_named_node_iterator&)
+	{
+		return std::bidirectional_iterator_tag();
+	}
+}
+#endif
+
+#if !defined(PUGIXML_NO_STL) && defined(__SUNPRO_CC)
+namespace std
+{
+	// Workarounds for (non-standard) iterator category detection
+	PUGI__FN std::bidirectional_iterator_tag __iterator_category(const pugi::xml_node_iterator&)
+	{
+		return std::bidirectional_iterator_tag();
+	}
+
+	PUGI__FN std::bidirectional_iterator_tag __iterator_category(const pugi::xml_attribute_iterator&)
+	{
+		return std::bidirectional_iterator_tag();
+	}
+
+	PUGI__FN std::bidirectional_iterator_tag __iterator_category(const pugi::xml_named_node_iterator&)
+	{
+		return std::bidirectional_iterator_tag();
+	}
+}
+#endif
+
+#ifndef PUGIXML_NO_XPATH
+// STL replacements
+PUGI__NS_BEGIN
+	struct equal_to
+	{
+		template <typename T> bool operator()(const T& lhs, const T& rhs) const
+		{
+			return lhs == rhs;
+		}
+	};
+
+	struct not_equal_to
+	{
+		template <typename T> bool operator()(const T& lhs, const T& rhs) const
+		{
+			return lhs != rhs;
+		}
+	};
+
+	struct less
+	{
+		template <typename T> bool operator()(const T& lhs, const T& rhs) const
+		{
+			return lhs < rhs;
+		}
+	};
+
+	struct less_equal
+	{
+		template <typename T> bool operator()(const T& lhs, const T& rhs) const
+		{
+			return lhs <= rhs;
+		}
+	};
+
+	template <typename T> void swap(T& lhs, T& rhs)
+	{
+		T temp = lhs;
+		lhs = rhs;
+		rhs = temp;
+	}
+
+	template <typename I, typename Pred> I min_element(I begin, I end, const Pred& pred)
+	{
+		I result = begin;
+
+		for (I it = begin + 1; it != end; ++it)
+			if (pred(*it, *result))
+				result = it;
+
+		return result;
+	}
+
+	template <typename I> void reverse(I begin, I end)
+	{
+		while (end - begin > 1) swap(*begin++, *--end);
+	}
+
+	template <typename I> I unique(I begin, I end)
+	{
+		// fast skip head
+		while (end - begin > 1 && *begin != *(begin + 1)) begin++;
+
+		if (begin == end) return begin;
+
+		// last written element
+		I write = begin++;
+
+		// merge unique elements
+		while (begin != end)
+		{
+			if (*begin != *write)
+				*++write = *begin++;
+			else
+				begin++;
+		}
+
+		// past-the-end (write points to live element)
+		return write + 1;
+	}
+
+	template <typename I> void copy_backwards(I begin, I end, I target)
+	{
+		while (begin != end) *--target = *--end;
+	}
+
+	template <typename I, typename Pred, typename T> void insertion_sort(I begin, I end, const Pred& pred, T*)
+	{
+		assert(begin != end);
+
+		for (I it = begin + 1; it != end; ++it)
+		{
+			T val = *it;
+
+			if (pred(val, *begin))
+			{
+				// move to front
+				copy_backwards(begin, it, it + 1);
+				*begin = val;
+			}
+			else
+			{
+				I hole = it;
+
+				// move hole backwards
+				while (pred(val, *(hole - 1)))
+				{
+					*hole = *(hole - 1);
+					hole--;
+				}
+
+				// fill hole with element
+				*hole = val;
+			}
+		}
+	}
+
+	// std variant for elements with ==
+	template <typename I, typename Pred> void partition(I begin, I middle, I end, const Pred& pred, I* out_eqbeg, I* out_eqend)
+	{
+		I eqbeg = middle, eqend = middle + 1;
+
+		// expand equal range
+		while (eqbeg != begin && *(eqbeg - 1) == *eqbeg) --eqbeg;
+		while (eqend != end && *eqend == *eqbeg) ++eqend;
+
+		// process outer elements
+		I ltend = eqbeg, gtbeg = eqend;
+
+		for (;;)
+		{
+			// find the element from the right side that belongs to the left one
+			for (; gtbeg != end; ++gtbeg)
+				if (!pred(*eqbeg, *gtbeg))
+				{
+					if (*gtbeg == *eqbeg) swap(*gtbeg, *eqend++);
+					else break;
+				}
+
+			// find the element from the left side that belongs to the right one
+			for (; ltend != begin; --ltend)
+				if (!pred(*(ltend - 1), *eqbeg))
+				{
+					if (*eqbeg == *(ltend - 1)) swap(*(ltend - 1), *--eqbeg);
+					else break;
+				}
+
+			// scanned all elements
+			if (gtbeg == end && ltend == begin)
+			{
+				*out_eqbeg = eqbeg;
+				*out_eqend = eqend;
+				return;
+			}
+
+			// make room for elements by moving equal area
+			if (gtbeg == end)
+			{
+				if (--ltend != --eqbeg) swap(*ltend, *eqbeg);
+				swap(*eqbeg, *--eqend);
+			}
+			else if (ltend == begin)
+			{
+				if (eqend != gtbeg) swap(*eqbeg, *eqend);
+				++eqend;
+				swap(*gtbeg++, *eqbeg++);
+			}
+			else swap(*gtbeg++, *--ltend);
+		}
+	}
+
+	template <typename I, typename Pred> void median3(I first, I middle, I last, const Pred& pred)
+	{
+		if (pred(*middle, *first)) swap(*middle, *first);
+		if (pred(*last, *middle)) swap(*last, *middle);
+		if (pred(*middle, *first)) swap(*middle, *first);
+	}
+
+	template <typename I, typename Pred> void median(I first, I middle, I last, const Pred& pred)
+	{
+		if (last - first <= 40)
+		{
+			// median of three for small chunks
+			median3(first, middle, last, pred);
+		}
+		else
+		{
+			// median of nine
+			size_t step = (last - first + 1) / 8;
+
+			median3(first, first + step, first + 2 * step, pred);
+			median3(middle - step, middle, middle + step, pred);
+			median3(last - 2 * step, last - step, last, pred);
+			median3(first + step, middle, last - step, pred);
+		}
+	}
+
+	template <typename I, typename Pred> void sort(I begin, I end, const Pred& pred)
+	{
+		// sort large chunks
+		while (end - begin > 32)
+		{
+			// find median element
+			I middle = begin + (end - begin) / 2;
+			median(begin, middle, end - 1, pred);
+
+			// partition in three chunks (< = >)
+			I eqbeg, eqend;
+			partition(begin, middle, end, pred, &eqbeg, &eqend);
+
+			// loop on larger half
+			if (eqbeg - begin > end - eqend)
+			{
+				sort(eqend, end, pred);
+				end = eqbeg;
+			}
+			else
+			{
+				sort(begin, eqbeg, pred);
+				begin = eqend;
+			}
+		}
+
+		// insertion sort small chunk
+		if (begin != end) insertion_sort(begin, end, pred, &*begin);
+	}
+PUGI__NS_END
+
+// Allocator used for AST and evaluation stacks
+PUGI__NS_BEGIN
+	static const size_t xpath_memory_page_size =
+	#ifdef PUGIXML_MEMORY_XPATH_PAGE_SIZE
+		PUGIXML_MEMORY_XPATH_PAGE_SIZE
+	#else
+		4096
+	#endif
+		;
+
+	static const uintptr_t xpath_memory_block_alignment = sizeof(double) > sizeof(void*) ? sizeof(double) : sizeof(void*);
+
+	struct xpath_memory_block
+	{
+		xpath_memory_block* next;
+		size_t capacity;
+
+		union
+		{
+			char data[xpath_memory_page_size];
+			double alignment;
+		};
+	};
+
+	class xpath_allocator
+	{
+		xpath_memory_block* _root;
+		size_t _root_size;
+
+	public:
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		jmp_buf* error_handler;
+	#endif
+
+		xpath_allocator(xpath_memory_block* root, size_t root_size = 0): _root(root), _root_size(root_size)
+		{
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			error_handler = 0;
+		#endif
+		}
+
+		void* allocate_nothrow(size_t size)
+		{
+			// round size up to block alignment boundary
+			size = (size + xpath_memory_block_alignment - 1) & ~(xpath_memory_block_alignment - 1);
+
+			if (_root_size + size <= _root->capacity)
+			{
+				void* buf = &_root->data[0] + _root_size;
+				_root_size += size;
+				return buf;
+			}
+			else
+			{
+				// make sure we have at least 1/4th of the page free after allocation to satisfy subsequent allocation requests
+				size_t block_capacity_base = sizeof(_root->data);
+				size_t block_capacity_req = size + block_capacity_base / 4;
+				size_t block_capacity = (block_capacity_base > block_capacity_req) ? block_capacity_base : block_capacity_req;
+
+				size_t block_size = block_capacity + offsetof(xpath_memory_block, data);
+
+				xpath_memory_block* block = static_cast<xpath_memory_block*>(xml_memory::allocate(block_size));
+				if (!block) return 0;
+
+				block->next = _root;
+				block->capacity = block_capacity;
+
+				_root = block;
+				_root_size = size;
+
+				return block->data;
+			}
+		}
+
+		void* allocate(size_t size)
+		{
+			void* result = allocate_nothrow(size);
+
+			if (!result)
+			{
+			#ifdef PUGIXML_NO_EXCEPTIONS
+				assert(error_handler);
+				longjmp(*error_handler, 1);
+			#else
+				throw std::bad_alloc();
+			#endif
+			}
+
+			return result;
+		}
+
+		void* reallocate(void* ptr, size_t old_size, size_t new_size)
+		{
+			// round size up to block alignment boundary
+			old_size = (old_size + xpath_memory_block_alignment - 1) & ~(xpath_memory_block_alignment - 1);
+			new_size = (new_size + xpath_memory_block_alignment - 1) & ~(xpath_memory_block_alignment - 1);
+
+			// we can only reallocate the last object
+			assert(ptr == 0 || static_cast<char*>(ptr) + old_size == &_root->data[0] + _root_size);
+
+			// adjust root size so that we have not allocated the object at all
+			bool only_object = (_root_size == old_size);
+
+			if (ptr) _root_size -= old_size;
+
+			// allocate a new version (this will obviously reuse the memory if possible)
+			void* result = allocate(new_size);
+			assert(result);
+
+			// we have a new block
+			if (result != ptr && ptr)
+			{
+				// copy old data
+				assert(new_size >= old_size);
+				memcpy(result, ptr, old_size);
+
+				// free the previous page if it had no other objects
+				if (only_object)
+				{
+					assert(_root->data == result);
+					assert(_root->next);
+
+					xpath_memory_block* next = _root->next->next;
+
+					if (next)
+					{
+						// deallocate the whole page, unless it was the first one
+						xml_memory::deallocate(_root->next);
+						_root->next = next;
+					}
+				}
+			}
+
+			return result;
+		}
+
+		void revert(const xpath_allocator& state)
+		{
+			// free all new pages
+			xpath_memory_block* cur = _root;
+
+			while (cur != state._root)
+			{
+				xpath_memory_block* next = cur->next;
+
+				xml_memory::deallocate(cur);
+
+				cur = next;
+			}
+
+			// restore state
+			_root = state._root;
+			_root_size = state._root_size;
+		}
+
+		void release()
+		{
+			xpath_memory_block* cur = _root;
+			assert(cur);
+
+			while (cur->next)
+			{
+				xpath_memory_block* next = cur->next;
+
+				xml_memory::deallocate(cur);
+
+				cur = next;
+			}
+		}
+	};
+
+	struct xpath_allocator_capture
+	{
+		xpath_allocator_capture(xpath_allocator* alloc): _target(alloc), _state(*alloc)
+		{
+		}
+
+		~xpath_allocator_capture()
+		{
+			_target->revert(_state);
+		}
+
+		xpath_allocator* _target;
+		xpath_allocator _state;
+	};
+
+	struct xpath_stack
+	{
+		xpath_allocator* result;
+		xpath_allocator* temp;
+	};
+
+	struct xpath_stack_data
+	{
+		xpath_memory_block blocks[2];
+		xpath_allocator result;
+		xpath_allocator temp;
+		xpath_stack stack;
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		jmp_buf error_handler;
+	#endif
+
+		xpath_stack_data(): result(blocks + 0), temp(blocks + 1)
+		{
+			blocks[0].next = blocks[1].next = 0;
+			blocks[0].capacity = blocks[1].capacity = sizeof(blocks[0].data);
+
+			stack.result = &result;
+			stack.temp = &temp;
+
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			result.error_handler = temp.error_handler = &error_handler;
+		#endif
+		}
+
+		~xpath_stack_data()
+		{
+			result.release();
+			temp.release();
+		}
+	};
+PUGI__NS_END
+
+// String class
+PUGI__NS_BEGIN
+	class xpath_string
+	{
+		const char_t* _buffer;
+		bool _uses_heap;
+		size_t _length_heap;
+
+		static char_t* duplicate_string(const char_t* string, size_t length, xpath_allocator* alloc)
+		{
+			char_t* result = static_cast<char_t*>(alloc->allocate((length + 1) * sizeof(char_t)));
+			assert(result);
+
+			memcpy(result, string, length * sizeof(char_t));
+			result[length] = 0;
+
+			return result;
+		}
+
+		xpath_string(const char_t* buffer, bool uses_heap_, size_t length_heap): _buffer(buffer), _uses_heap(uses_heap_), _length_heap(length_heap)
+		{
+		}
+
+	public:
+		static xpath_string from_const(const char_t* str)
+		{
+			return xpath_string(str, false, 0);
+		}
+
+		static xpath_string from_heap_preallocated(const char_t* begin, const char_t* end)
+		{
+			assert(begin <= end && *end == 0);
+
+			return xpath_string(begin, true, static_cast<size_t>(end - begin));
+		}
+
+		static xpath_string from_heap(const char_t* begin, const char_t* end, xpath_allocator* alloc)
+		{
+			assert(begin <= end);
+
+			size_t length = static_cast<size_t>(end - begin);
+
+			return length == 0 ? xpath_string() : xpath_string(duplicate_string(begin, length, alloc), true, length);
+		}
+
+		xpath_string(): _buffer(PUGIXML_TEXT("")), _uses_heap(false), _length_heap(0)
+		{
+		}
+
+		void append(const xpath_string& o, xpath_allocator* alloc)
+		{
+			// skip empty sources
+			if (!*o._buffer) return;
+
+			// fast append for constant empty target and constant source
+			if (!*_buffer && !_uses_heap && !o._uses_heap)
+			{
+				_buffer = o._buffer;
+			}
+			else
+			{
+				// need to make heap copy
+				size_t target_length = length();
+				size_t source_length = o.length();
+				size_t result_length = target_length + source_length;
+
+				// allocate new buffer
+				char_t* result = static_cast<char_t*>(alloc->reallocate(_uses_heap ? const_cast<char_t*>(_buffer) : 0, (target_length + 1) * sizeof(char_t), (result_length + 1) * sizeof(char_t)));
+				assert(result);
+
+				// append first string to the new buffer in case there was no reallocation
+				if (!_uses_heap) memcpy(result, _buffer, target_length * sizeof(char_t));
+
+				// append second string to the new buffer
+				memcpy(result + target_length, o._buffer, source_length * sizeof(char_t));
+				result[result_length] = 0;
+
+				// finalize
+				_buffer = result;
+				_uses_heap = true;
+				_length_heap = result_length;
+			}
+		}
+
+		const char_t* c_str() const
+		{
+			return _buffer;
+		}
+
+		size_t length() const
+		{
+			return _uses_heap ? _length_heap : strlength(_buffer);
+		}
+
+		char_t* data(xpath_allocator* alloc)
+		{
+			// make private heap copy
+			if (!_uses_heap)
+			{
+				size_t length_ = strlength(_buffer);
+
+				_buffer = duplicate_string(_buffer, length_, alloc);
+				_uses_heap = true;
+				_length_heap = length_;
+			}
+
+			return const_cast<char_t*>(_buffer);
+		}
+
+		bool empty() const
+		{
+			return *_buffer == 0;
+		}
+
+		bool operator==(const xpath_string& o) const
+		{
+			return strequal(_buffer, o._buffer);
+		}
+
+		bool operator!=(const xpath_string& o) const
+		{
+			return !strequal(_buffer, o._buffer);
+		}
+
+		bool uses_heap() const
+		{
+			return _uses_heap;
+		}
+	};
+PUGI__NS_END
+
+PUGI__NS_BEGIN
+	PUGI__FN bool starts_with(const char_t* string, const char_t* pattern)
+	{
+		while (*pattern && *string == *pattern)
+		{
+			string++;
+			pattern++;
+		}
+
+		return *pattern == 0;
+	}
+
+	PUGI__FN const char_t* find_char(const char_t* s, char_t c)
+	{
+	#ifdef PUGIXML_WCHAR_MODE
+		return wcschr(s, c);
+	#else
+		return strchr(s, c);
+	#endif
+	}
+
+	PUGI__FN const char_t* find_substring(const char_t* s, const char_t* p)
+	{
+	#ifdef PUGIXML_WCHAR_MODE
+		// MSVC6 wcsstr bug workaround (if s is empty it always returns 0)
+		return (*p == 0) ? s : wcsstr(s, p);
+	#else
+		return strstr(s, p);
+	#endif
+	}
+
+	// Converts symbol to lower case, if it is an ASCII one
+	PUGI__FN char_t tolower_ascii(char_t ch)
+	{
+		return static_cast<unsigned int>(ch - 'A') < 26 ? static_cast<char_t>(ch | ' ') : ch;
+	}
+
+	PUGI__FN xpath_string string_value(const xpath_node& na, xpath_allocator* alloc)
+	{
+		if (na.attribute())
+			return xpath_string::from_const(na.attribute().value());
+		else
+		{
+			xml_node n = na.node();
+
+			switch (n.type())
+			{
+			case node_pcdata:
+			case node_cdata:
+			case node_comment:
+			case node_pi:
+				return xpath_string::from_const(n.value());
+
+			case node_document:
+			case node_element:
+			{
+				xpath_string result;
+
+				// element nodes can have value if parse_embed_pcdata was used
+				if (n.value()[0])
+					result.append(xpath_string::from_const(n.value()), alloc);
+
+				xml_node cur = n.first_child();
+
+				while (cur && cur != n)
+				{
+					if (cur.type() == node_pcdata || cur.type() == node_cdata)
+						result.append(xpath_string::from_const(cur.value()), alloc);
+
+					if (cur.first_child())
+						cur = cur.first_child();
+					else if (cur.next_sibling())
+						cur = cur.next_sibling();
+					else
+					{
+						while (!cur.next_sibling() && cur != n)
+							cur = cur.parent();
+
+						if (cur != n) cur = cur.next_sibling();
+					}
+				}
+
+				return result;
+			}
+
+			default:
+				return xpath_string();
+			}
+		}
+	}
+
+	PUGI__FN bool node_is_before_sibling(xml_node_struct* ln, xml_node_struct* rn)
+	{
+		assert(ln->parent == rn->parent);
+
+		// there is no common ancestor (the shared parent is null), nodes are from different documents
+		if (!ln->parent) return ln < rn;
+
+		// determine sibling order
+		xml_node_struct* ls = ln;
+		xml_node_struct* rs = rn;
+
+		while (ls && rs)
+		{
+			if (ls == rn) return true;
+			if (rs == ln) return false;
+
+			ls = ls->next_sibling;
+			rs = rs->next_sibling;
+		}
+
+		// if rn sibling chain ended ln must be before rn
+		return !rs;
+	}
+
+	PUGI__FN bool node_is_before(xml_node_struct* ln, xml_node_struct* rn)
+	{
+		// find common ancestor at the same depth, if any
+		xml_node_struct* lp = ln;
+		xml_node_struct* rp = rn;
+
+		while (lp && rp && lp->parent != rp->parent)
+		{
+			lp = lp->parent;
+			rp = rp->parent;
+		}
+
+		// parents are the same!
+		if (lp && rp) return node_is_before_sibling(lp, rp);
+
+		// nodes are at different depths, need to normalize heights
+		bool left_higher = !lp;
+
+		while (lp)
+		{
+			lp = lp->parent;
+			ln = ln->parent;
+		}
+
+		while (rp)
+		{
+			rp = rp->parent;
+			rn = rn->parent;
+		}
+
+		// one node is the ancestor of the other
+		if (ln == rn) return left_higher;
+
+		// find common ancestor... again
+		while (ln->parent != rn->parent)
+		{
+			ln = ln->parent;
+			rn = rn->parent;
+		}
+
+		return node_is_before_sibling(ln, rn);
+	}
+
+	PUGI__FN bool node_is_ancestor(xml_node_struct* parent, xml_node_struct* node)
+	{
+		while (node && node != parent) node = node->parent;
+
+		return parent && node == parent;
+	}
+
+	PUGI__FN const void* document_buffer_order(const xpath_node& xnode)
+	{
+		xml_node_struct* node = xnode.node().internal_object();
+
+		if (node)
+		{
+			if ((get_document(node).header & xml_memory_page_contents_shared_mask) == 0)
+			{
+				if (node->name && (node->header & impl::xml_memory_page_name_allocated_or_shared_mask) == 0) return node->name;
+				if (node->value && (node->header & impl::xml_memory_page_value_allocated_or_shared_mask) == 0) return node->value;
+			}
+
+			return 0;
+		}
+
+		xml_attribute_struct* attr = xnode.attribute().internal_object();
+
+		if (attr)
+		{
+			if ((get_document(attr).header & xml_memory_page_contents_shared_mask) == 0)
+			{
+				if ((attr->header & impl::xml_memory_page_name_allocated_or_shared_mask) == 0) return attr->name;
+				if ((attr->header & impl::xml_memory_page_value_allocated_or_shared_mask) == 0) return attr->value;
+			}
+
+			return 0;
+		}
+
+		return 0;
+	}
+
+	struct document_order_comparator
+	{
+		bool operator()(const xpath_node& lhs, const xpath_node& rhs) const
+		{
+			// optimized document order based check
+			const void* lo = document_buffer_order(lhs);
+			const void* ro = document_buffer_order(rhs);
+
+			if (lo && ro) return lo < ro;
+
+			// slow comparison
+			xml_node ln = lhs.node(), rn = rhs.node();
+
+			// compare attributes
+			if (lhs.attribute() && rhs.attribute())
+			{
+				// shared parent
+				if (lhs.parent() == rhs.parent())
+				{
+					// determine sibling order
+					for (xml_attribute a = lhs.attribute(); a; a = a.next_attribute())
+						if (a == rhs.attribute())
+							return true;
+
+					return false;
+				}
+
+				// compare attribute parents
+				ln = lhs.parent();
+				rn = rhs.parent();
+			}
+			else if (lhs.attribute())
+			{
+				// attributes go after the parent element
+				if (lhs.parent() == rhs.node()) return false;
+
+				ln = lhs.parent();
+			}
+			else if (rhs.attribute())
+			{
+				// attributes go after the parent element
+				if (rhs.parent() == lhs.node()) return true;
+
+				rn = rhs.parent();
+			}
+
+			if (ln == rn) return false;
+
+			if (!ln || !rn) return ln < rn;
+
+			return node_is_before(ln.internal_object(), rn.internal_object());
+		}
+	};
+
+	struct duplicate_comparator
+	{
+		bool operator()(const xpath_node& lhs, const xpath_node& rhs) const
+		{
+			if (lhs.attribute()) return rhs.attribute() ? lhs.attribute() < rhs.attribute() : true;
+			else return rhs.attribute() ? false : lhs.node() < rhs.node();
+		}
+	};
+
+	PUGI__FN double gen_nan()
+	{
+	#if defined(__STDC_IEC_559__) || ((FLT_RADIX - 0 == 2) && (FLT_MAX_EXP - 0 == 128) && (FLT_MANT_DIG - 0 == 24))
+		PUGI__STATIC_ASSERT(sizeof(float) == sizeof(uint32_t));
+		typedef uint32_t UI; // BCC5 workaround
+		union { float f; UI i; } u;
+		u.i = 0x7fc00000;
+		return u.f;
+	#else
+		// fallback
+		const volatile double zero = 0.0;
+		return zero / zero;
+	#endif
+	}
+
+	PUGI__FN bool is_nan(double value)
+	{
+	#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__)
+		return !!_isnan(value);
+	#elif defined(fpclassify) && defined(FP_NAN)
+		return fpclassify(value) == FP_NAN;
+	#else
+		// fallback
+		const volatile double v = value;
+		return v != v;
+	#endif
+	}
+
+	PUGI__FN const char_t* convert_number_to_string_special(double value)
+	{
+	#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__)
+		if (_finite(value)) return (value == 0) ? PUGIXML_TEXT("0") : 0;
+		if (_isnan(value)) return PUGIXML_TEXT("NaN");
+		return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity");
+	#elif defined(fpclassify) && defined(FP_NAN) && defined(FP_INFINITE) && defined(FP_ZERO)
+		switch (fpclassify(value))
+		{
+		case FP_NAN:
+			return PUGIXML_TEXT("NaN");
+
+		case FP_INFINITE:
+			return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity");
+
+		case FP_ZERO:
+			return PUGIXML_TEXT("0");
+
+		default:
+			return 0;
+		}
+	#else
+		// fallback
+		const volatile double v = value;
+
+		if (v == 0) return PUGIXML_TEXT("0");
+		if (v != v) return PUGIXML_TEXT("NaN");
+		if (v * 2 == v) return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity");
+		return 0;
+	#endif
+	}
+
+	PUGI__FN bool convert_number_to_boolean(double value)
+	{
+		return (value != 0 && !is_nan(value));
+	}
+
+	PUGI__FN void truncate_zeros(char* begin, char* end)
+	{
+		while (begin != end && end[-1] == '0') end--;
+
+		*end = 0;
+	}
+
+	// gets mantissa digits in the form of 0.xxxxx with 0. implied and the exponent
+#if defined(PUGI__MSVC_CRT_VERSION) && PUGI__MSVC_CRT_VERSION >= 1400 && !defined(_WIN32_WCE)
+	PUGI__FN void convert_number_to_mantissa_exponent(double value, char* buffer, size_t buffer_size, char** out_mantissa, int* out_exponent)
+	{
+		// get base values
+		int sign, exponent;
+		_ecvt_s(buffer, buffer_size, value, DBL_DIG + 1, &exponent, &sign);
+
+		// truncate redundant zeros
+		truncate_zeros(buffer, buffer + strlen(buffer));
+
+		// fill results
+		*out_mantissa = buffer;
+		*out_exponent = exponent;
+	}
+#else
+	PUGI__FN void convert_number_to_mantissa_exponent(double value, char* buffer, size_t buffer_size, char** out_mantissa, int* out_exponent)
+	{
+		// get a scientific notation value with IEEE DBL_DIG decimals
+		sprintf(buffer, "%.*e", DBL_DIG, value);
+		assert(strlen(buffer) < buffer_size);
+		(void)!buffer_size;
+
+		// get the exponent (possibly negative)
+		char* exponent_string = strchr(buffer, 'e');
+		assert(exponent_string);
+
+		int exponent = atoi(exponent_string + 1);
+
+		// extract mantissa string: skip sign
+		char* mantissa = buffer[0] == '-' ? buffer + 1 : buffer;
+		assert(mantissa[0] != '0' && mantissa[1] == '.');
+
+		// divide mantissa by 10 to eliminate integer part
+		mantissa[1] = mantissa[0];
+		mantissa++;
+		exponent++;
+
+		// remove extra mantissa digits and zero-terminate mantissa
+		truncate_zeros(mantissa, exponent_string);
+
+		// fill results
+		*out_mantissa = mantissa;
+		*out_exponent = exponent;
+	}
+#endif
+
+	PUGI__FN xpath_string convert_number_to_string(double value, xpath_allocator* alloc)
+	{
+		// try special number conversion
+		const char_t* special = convert_number_to_string_special(value);
+		if (special) return xpath_string::from_const(special);
+
+		// get mantissa + exponent form
+		char mantissa_buffer[32];
+
+		char* mantissa;
+		int exponent;
+		convert_number_to_mantissa_exponent(value, mantissa_buffer, sizeof(mantissa_buffer), &mantissa, &exponent);
+
+		// allocate a buffer of suitable length for the number
+		size_t result_size = strlen(mantissa_buffer) + (exponent > 0 ? exponent : -exponent) + 4;
+		char_t* result = static_cast<char_t*>(alloc->allocate(sizeof(char_t) * result_size));
+		assert(result);
+
+		// make the number!
+		char_t* s = result;
+
+		// sign
+		if (value < 0) *s++ = '-';
+
+		// integer part
+		if (exponent <= 0)
+		{
+			*s++ = '0';
+		}
+		else
+		{
+			while (exponent > 0)
+			{
+				assert(*mantissa == 0 || static_cast<unsigned int>(static_cast<unsigned int>(*mantissa) - '0') <= 9);
+				*s++ = *mantissa ? *mantissa++ : '0';
+				exponent--;
+			}
+		}
+
+		// fractional part
+		if (*mantissa)
+		{
+			// decimal point
+			*s++ = '.';
+
+			// extra zeroes from negative exponent
+			while (exponent < 0)
+			{
+				*s++ = '0';
+				exponent++;
+			}
+
+			// extra mantissa digits
+			while (*mantissa)
+			{
+				assert(static_cast<unsigned int>(*mantissa - '0') <= 9);
+				*s++ = *mantissa++;
+			}
+		}
+
+		// zero-terminate
+		assert(s < result + result_size);
+		*s = 0;
+
+		return xpath_string::from_heap_preallocated(result, s);
+	}
+
+	PUGI__FN bool check_string_to_number_format(const char_t* string)
+	{
+		// parse leading whitespace
+		while (PUGI__IS_CHARTYPE(*string, ct_space)) ++string;
+
+		// parse sign
+		if (*string == '-') ++string;
+
+		if (!*string) return false;
+
+		// if there is no integer part, there should be a decimal part with at least one digit
+		if (!PUGI__IS_CHARTYPEX(string[0], ctx_digit) && (string[0] != '.' || !PUGI__IS_CHARTYPEX(string[1], ctx_digit))) return false;
+
+		// parse integer part
+		while (PUGI__IS_CHARTYPEX(*string, ctx_digit)) ++string;
+
+		// parse decimal part
+		if (*string == '.')
+		{
+			++string;
+
+			while (PUGI__IS_CHARTYPEX(*string, ctx_digit)) ++string;
+		}
+
+		// parse trailing whitespace
+		while (PUGI__IS_CHARTYPE(*string, ct_space)) ++string;
+
+		return *string == 0;
+	}
+
+	PUGI__FN double convert_string_to_number(const char_t* string)
+	{
+		// check string format
+		if (!check_string_to_number_format(string)) return gen_nan();
+
+		// parse string
+	#ifdef PUGIXML_WCHAR_MODE
+		return wcstod(string, 0);
+	#else
+		return strtod(string, 0);
+	#endif
+	}
+
+	PUGI__FN bool convert_string_to_number_scratch(char_t (&buffer)[32], const char_t* begin, const char_t* end, double* out_result)
+	{
+		size_t length = static_cast<size_t>(end - begin);
+		char_t* scratch = buffer;
+
+		if (length >= sizeof(buffer) / sizeof(buffer[0]))
+		{
+			// need to make dummy on-heap copy
+			scratch = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+			if (!scratch) return false;
+		}
+
+		// copy string to zero-terminated buffer and perform conversion
+		memcpy(scratch, begin, length * sizeof(char_t));
+		scratch[length] = 0;
+
+		*out_result = convert_string_to_number(scratch);
+
+		// free dummy buffer
+		if (scratch != buffer) xml_memory::deallocate(scratch);
+
+		return true;
+	}
+
+	PUGI__FN double round_nearest(double value)
+	{
+		return floor(value + 0.5);
+	}
+
+	PUGI__FN double round_nearest_nzero(double value)
+	{
+		// same as round_nearest, but returns -0 for [-0.5, -0]
+		// ceil is used to differentiate between +0 and -0 (we return -0 for [-0.5, -0] and +0 for +0)
+		return (value >= -0.5 && value <= 0) ? ceil(value) : floor(value + 0.5);
+	}
+
+	PUGI__FN const char_t* qualified_name(const xpath_node& node)
+	{
+		return node.attribute() ? node.attribute().name() : node.node().name();
+	}
+
+	PUGI__FN const char_t* local_name(const xpath_node& node)
+	{
+		const char_t* name = qualified_name(node);
+		const char_t* p = find_char(name, ':');
+
+		return p ? p + 1 : name;
+	}
+
+	struct namespace_uri_predicate
+	{
+		const char_t* prefix;
+		size_t prefix_length;
+
+		namespace_uri_predicate(const char_t* name)
+		{
+			const char_t* pos = find_char(name, ':');
+
+			prefix = pos ? name : 0;
+			prefix_length = pos ? static_cast<size_t>(pos - name) : 0;
+		}
+
+		bool operator()(xml_attribute a) const
+		{
+			const char_t* name = a.name();
+
+			if (!starts_with(name, PUGIXML_TEXT("xmlns"))) return false;
+
+			return prefix ? name[5] == ':' && strequalrange(name + 6, prefix, prefix_length) : name[5] == 0;
+		}
+	};
+
+	PUGI__FN const char_t* namespace_uri(xml_node node)
+	{
+		namespace_uri_predicate pred = node.name();
+
+		xml_node p = node;
+
+		while (p)
+		{
+			xml_attribute a = p.find_attribute(pred);
+
+			if (a) return a.value();
+
+			p = p.parent();
+		}
+
+		return PUGIXML_TEXT("");
+	}
+
+	PUGI__FN const char_t* namespace_uri(xml_attribute attr, xml_node parent)
+	{
+		namespace_uri_predicate pred = attr.name();
+
+		// Default namespace does not apply to attributes
+		if (!pred.prefix) return PUGIXML_TEXT("");
+
+		xml_node p = parent;
+
+		while (p)
+		{
+			xml_attribute a = p.find_attribute(pred);
+
+			if (a) return a.value();
+
+			p = p.parent();
+		}
+
+		return PUGIXML_TEXT("");
+	}
+
+	PUGI__FN const char_t* namespace_uri(const xpath_node& node)
+	{
+		return node.attribute() ? namespace_uri(node.attribute(), node.parent()) : namespace_uri(node.node());
+	}
+
+	PUGI__FN char_t* normalize_space(char_t* buffer)
+	{
+		char_t* write = buffer;
+
+		for (char_t* it = buffer; *it; )
+		{
+			char_t ch = *it++;
+
+			if (PUGI__IS_CHARTYPE(ch, ct_space))
+			{
+				// replace whitespace sequence with single space
+				while (PUGI__IS_CHARTYPE(*it, ct_space)) it++;
+
+				// avoid leading spaces
+				if (write != buffer) *write++ = ' ';
+			}
+			else *write++ = ch;
+		}
+
+		// remove trailing space
+		if (write != buffer && PUGI__IS_CHARTYPE(write[-1], ct_space)) write--;
+
+		// zero-terminate
+		*write = 0;
+
+		return write;
+	}
+
+	PUGI__FN char_t* translate(char_t* buffer, const char_t* from, const char_t* to, size_t to_length)
+	{
+		char_t* write = buffer;
+
+		while (*buffer)
+		{
+			PUGI__DMC_VOLATILE char_t ch = *buffer++;
+
+			const char_t* pos = find_char(from, ch);
+
+			if (!pos)
+				*write++ = ch; // do not process
+			else if (static_cast<size_t>(pos - from) < to_length)
+				*write++ = to[pos - from]; // replace
+		}
+
+		// zero-terminate
+		*write = 0;
+
+		return write;
+	}
+
+	PUGI__FN unsigned char* translate_table_generate(xpath_allocator* alloc, const char_t* from, const char_t* to)
+	{
+		unsigned char table[128] = {0};
+
+		while (*from)
+		{
+			unsigned int fc = static_cast<unsigned int>(*from);
+			unsigned int tc = static_cast<unsigned int>(*to);
+
+			if (fc >= 128 || tc >= 128)
+				return 0;
+
+			// code=128 means "skip character"
+			if (!table[fc])
+				table[fc] = static_cast<unsigned char>(tc ? tc : 128);
+
+			from++;
+			if (tc) to++;
+		}
+
+		for (int i = 0; i < 128; ++i)
+			if (!table[i])
+				table[i] = static_cast<unsigned char>(i);
+
+		void* result = alloc->allocate_nothrow(sizeof(table));
+
+		if (result)
+		{
+			memcpy(result, table, sizeof(table));
+		}
+
+		return static_cast<unsigned char*>(result);
+	}
+
+	PUGI__FN char_t* translate_table(char_t* buffer, const unsigned char* table)
+	{
+		char_t* write = buffer;
+
+		while (*buffer)
+		{
+			char_t ch = *buffer++;
+			unsigned int index = static_cast<unsigned int>(ch);
+
+			if (index < 128)
+			{
+				unsigned char code = table[index];
+
+				// code=128 means "skip character" (table size is 128 so 128 can be a special value)
+				// this code skips these characters without extra branches
+				*write = static_cast<char_t>(code);
+				write += 1 - (code >> 7);
+			}
+			else
+			{
+				*write++ = ch;
+			}
+		}
+
+		// zero-terminate
+		*write = 0;
+
+		return write;
+	}
+
+	inline bool is_xpath_attribute(const char_t* name)
+	{
+		return !(starts_with(name, PUGIXML_TEXT("xmlns")) && (name[5] == 0 || name[5] == ':'));
+	}
+
+	struct xpath_variable_boolean: xpath_variable
+	{
+		xpath_variable_boolean(): xpath_variable(xpath_type_boolean), value(false)
+		{
+		}
+
+		bool value;
+		char_t name[1];
+	};
+
+	struct xpath_variable_number: xpath_variable
+	{
+		xpath_variable_number(): xpath_variable(xpath_type_number), value(0)
+		{
+		}
+
+		double value;
+		char_t name[1];
+	};
+
+	struct xpath_variable_string: xpath_variable
+	{
+		xpath_variable_string(): xpath_variable(xpath_type_string), value(0)
+		{
+		}
+
+		~xpath_variable_string()
+		{
+			if (value) xml_memory::deallocate(value);
+		}
+
+		char_t* value;
+		char_t name[1];
+	};
+
+	struct xpath_variable_node_set: xpath_variable
+	{
+		xpath_variable_node_set(): xpath_variable(xpath_type_node_set)
+		{
+		}
+
+		xpath_node_set value;
+		char_t name[1];
+	};
+
+	static const xpath_node_set dummy_node_set;
+
+	PUGI__FN unsigned int hash_string(const char_t* str)
+	{
+		// Jenkins one-at-a-time hash (http://en.wikipedia.org/wiki/Jenkins_hash_function#one-at-a-time)
+		unsigned int result = 0;
+
+		while (*str)
+		{
+			result += static_cast<unsigned int>(*str++);
+			result += result << 10;
+			result ^= result >> 6;
+		}
+
+		result += result << 3;
+		result ^= result >> 11;
+		result += result << 15;
+
+		return result;
+	}
+
+	template <typename T> PUGI__FN T* new_xpath_variable(const char_t* name)
+	{
+		size_t length = strlength(name);
+		if (length == 0) return 0; // empty variable names are invalid
+
+		// $$ we can't use offsetof(T, name) because T is non-POD, so we just allocate additional length characters
+		void* memory = xml_memory::allocate(sizeof(T) + length * sizeof(char_t));
+		if (!memory) return 0;
+
+		T* result = new (memory) T();
+
+		memcpy(result->name, name, (length + 1) * sizeof(char_t));
+
+		return result;
+	}
+
+	PUGI__FN xpath_variable* new_xpath_variable(xpath_value_type type, const char_t* name)
+	{
+		switch (type)
+		{
+		case xpath_type_node_set:
+			return new_xpath_variable<xpath_variable_node_set>(name);
+
+		case xpath_type_number:
+			return new_xpath_variable<xpath_variable_number>(name);
+
+		case xpath_type_string:
+			return new_xpath_variable<xpath_variable_string>(name);
+
+		case xpath_type_boolean:
+			return new_xpath_variable<xpath_variable_boolean>(name);
+
+		default:
+			return 0;
+		}
+	}
+
+	template <typename T> PUGI__FN void delete_xpath_variable(T* var)
+	{
+		var->~T();
+		xml_memory::deallocate(var);
+	}
+
+	PUGI__FN void delete_xpath_variable(xpath_value_type type, xpath_variable* var)
+	{
+		switch (type)
+		{
+		case xpath_type_node_set:
+			delete_xpath_variable(static_cast<xpath_variable_node_set*>(var));
+			break;
+
+		case xpath_type_number:
+			delete_xpath_variable(static_cast<xpath_variable_number*>(var));
+			break;
+
+		case xpath_type_string:
+			delete_xpath_variable(static_cast<xpath_variable_string*>(var));
+			break;
+
+		case xpath_type_boolean:
+			delete_xpath_variable(static_cast<xpath_variable_boolean*>(var));
+			break;
+
+		default:
+			assert(false && "Invalid variable type");
+		}
+	}
+
+	PUGI__FN bool copy_xpath_variable(xpath_variable* lhs, const xpath_variable* rhs)
+	{
+		switch (rhs->type())
+		{
+		case xpath_type_node_set:
+			return lhs->set(static_cast<const xpath_variable_node_set*>(rhs)->value);
+
+		case xpath_type_number:
+			return lhs->set(static_cast<const xpath_variable_number*>(rhs)->value);
+
+		case xpath_type_string:
+			return lhs->set(static_cast<const xpath_variable_string*>(rhs)->value);
+
+		case xpath_type_boolean:
+			return lhs->set(static_cast<const xpath_variable_boolean*>(rhs)->value);
+
+		default:
+			assert(false && "Invalid variable type");
+			return false;
+		}
+	}
+
+	PUGI__FN bool get_variable_scratch(char_t (&buffer)[32], xpath_variable_set* set, const char_t* begin, const char_t* end, xpath_variable** out_result)
+	{
+		size_t length = static_cast<size_t>(end - begin);
+		char_t* scratch = buffer;
+
+		if (length >= sizeof(buffer) / sizeof(buffer[0]))
+		{
+			// need to make dummy on-heap copy
+			scratch = static_cast<char_t*>(xml_memory::allocate((length + 1) * sizeof(char_t)));
+			if (!scratch) return false;
+		}
+
+		// copy string to zero-terminated buffer and perform lookup
+		memcpy(scratch, begin, length * sizeof(char_t));
+		scratch[length] = 0;
+
+		*out_result = set->get(scratch);
+
+		// free dummy buffer
+		if (scratch != buffer) xml_memory::deallocate(scratch);
+
+		return true;
+	}
+PUGI__NS_END
+
+// Internal node set class
+PUGI__NS_BEGIN
+	PUGI__FN xpath_node_set::type_t xpath_get_order(const xpath_node* begin, const xpath_node* end)
+	{
+		if (end - begin < 2)
+			return xpath_node_set::type_sorted;
+
+		document_order_comparator cmp;
+
+		bool first = cmp(begin[0], begin[1]);
+
+		for (const xpath_node* it = begin + 1; it + 1 < end; ++it)
+			if (cmp(it[0], it[1]) != first)
+				return xpath_node_set::type_unsorted;
+
+		return first ? xpath_node_set::type_sorted : xpath_node_set::type_sorted_reverse;
+	}
+
+	PUGI__FN xpath_node_set::type_t xpath_sort(xpath_node* begin, xpath_node* end, xpath_node_set::type_t type, bool rev)
+	{
+		xpath_node_set::type_t order = rev ? xpath_node_set::type_sorted_reverse : xpath_node_set::type_sorted;
+
+		if (type == xpath_node_set::type_unsorted)
+		{
+			xpath_node_set::type_t sorted = xpath_get_order(begin, end);
+
+			if (sorted == xpath_node_set::type_unsorted)
+			{
+				sort(begin, end, document_order_comparator());
+
+				type = xpath_node_set::type_sorted;
+			}
+			else
+				type = sorted;
+		}
+
+		if (type != order) reverse(begin, end);
+
+		return order;
+	}
+
+	PUGI__FN xpath_node xpath_first(const xpath_node* begin, const xpath_node* end, xpath_node_set::type_t type)
+	{
+		if (begin == end) return xpath_node();
+
+		switch (type)
+		{
+		case xpath_node_set::type_sorted:
+			return *begin;
+
+		case xpath_node_set::type_sorted_reverse:
+			return *(end - 1);
+
+		case xpath_node_set::type_unsorted:
+			return *min_element(begin, end, document_order_comparator());
+
+		default:
+			assert(false && "Invalid node set type");
+			return xpath_node();
+		}
+	}
+
+	class xpath_node_set_raw
+	{
+		xpath_node_set::type_t _type;
+
+		xpath_node* _begin;
+		xpath_node* _end;
+		xpath_node* _eos;
+
+	public:
+		xpath_node_set_raw(): _type(xpath_node_set::type_unsorted), _begin(0), _end(0), _eos(0)
+		{
+		}
+
+		xpath_node* begin() const
+		{
+			return _begin;
+		}
+
+		xpath_node* end() const
+		{
+			return _end;
+		}
+
+		bool empty() const
+		{
+			return _begin == _end;
+		}
+
+		size_t size() const
+		{
+			return static_cast<size_t>(_end - _begin);
+		}
+
+		xpath_node first() const
+		{
+			return xpath_first(_begin, _end, _type);
+		}
+
+		void push_back_grow(const xpath_node& node, xpath_allocator* alloc);
+
+		void push_back(const xpath_node& node, xpath_allocator* alloc)
+		{
+			if (_end != _eos)
+				*_end++ = node;
+			else
+				push_back_grow(node, alloc);
+		}
+
+		void append(const xpath_node* begin_, const xpath_node* end_, xpath_allocator* alloc)
+		{
+			if (begin_ == end_) return;
+
+			size_t size_ = static_cast<size_t>(_end - _begin);
+			size_t capacity = static_cast<size_t>(_eos - _begin);
+			size_t count = static_cast<size_t>(end_ - begin_);
+
+			if (size_ + count > capacity)
+			{
+				// reallocate the old array or allocate a new one
+				xpath_node* data = static_cast<xpath_node*>(alloc->reallocate(_begin, capacity * sizeof(xpath_node), (size_ + count) * sizeof(xpath_node)));
+				assert(data);
+
+				// finalize
+				_begin = data;
+				_end = data + size_;
+				_eos = data + size_ + count;
+			}
+
+			memcpy(_end, begin_, count * sizeof(xpath_node));
+			_end += count;
+		}
+
+		void sort_do()
+		{
+			_type = xpath_sort(_begin, _end, _type, false);
+		}
+
+		void truncate(xpath_node* pos)
+		{
+			assert(_begin <= pos && pos <= _end);
+
+			_end = pos;
+		}
+
+		void remove_duplicates()
+		{
+			if (_type == xpath_node_set::type_unsorted)
+				sort(_begin, _end, duplicate_comparator());
+
+			_end = unique(_begin, _end);
+		}
+
+		xpath_node_set::type_t type() const
+		{
+			return _type;
+		}
+
+		void set_type(xpath_node_set::type_t value)
+		{
+			_type = value;
+		}
+	};
+
+	PUGI__FN_NO_INLINE void xpath_node_set_raw::push_back_grow(const xpath_node& node, xpath_allocator* alloc)
+	{
+		size_t capacity = static_cast<size_t>(_eos - _begin);
+
+		// get new capacity (1.5x rule)
+		size_t new_capacity = capacity + capacity / 2 + 1;
+
+		// reallocate the old array or allocate a new one
+		xpath_node* data = static_cast<xpath_node*>(alloc->reallocate(_begin, capacity * sizeof(xpath_node), new_capacity * sizeof(xpath_node)));
+		assert(data);
+
+		// finalize
+		_begin = data;
+		_end = data + capacity;
+		_eos = data + new_capacity;
+
+		// push
+		*_end++ = node;
+	}
+PUGI__NS_END
+
+PUGI__NS_BEGIN
+	struct xpath_context
+	{
+		xpath_node n;
+		size_t position, size;
+
+		xpath_context(const xpath_node& n_, size_t position_, size_t size_): n(n_), position(position_), size(size_)
+		{
+		}
+	};
+
+	enum lexeme_t
+	{
+		lex_none = 0,
+		lex_equal,
+		lex_not_equal,
+		lex_less,
+		lex_greater,
+		lex_less_or_equal,
+		lex_greater_or_equal,
+		lex_plus,
+		lex_minus,
+		lex_multiply,
+		lex_union,
+		lex_var_ref,
+		lex_open_brace,
+		lex_close_brace,
+		lex_quoted_string,
+		lex_number,
+		lex_slash,
+		lex_double_slash,
+		lex_open_square_brace,
+		lex_close_square_brace,
+		lex_string,
+		lex_comma,
+		lex_axis_attribute,
+		lex_dot,
+		lex_double_dot,
+		lex_double_colon,
+		lex_eof
+	};
+
+	struct xpath_lexer_string
+	{
+		const char_t* begin;
+		const char_t* end;
+
+		xpath_lexer_string(): begin(0), end(0)
+		{
+		}
+
+		bool operator==(const char_t* other) const
+		{
+			size_t length = static_cast<size_t>(end - begin);
+
+			return strequalrange(other, begin, length);
+		}
+	};
+
+	class xpath_lexer
+	{
+		const char_t* _cur;
+		const char_t* _cur_lexeme_pos;
+		xpath_lexer_string _cur_lexeme_contents;
+
+		lexeme_t _cur_lexeme;
+
+	public:
+		explicit xpath_lexer(const char_t* query): _cur(query)
+		{
+			next();
+		}
+
+		const char_t* state() const
+		{
+			return _cur;
+		}
+
+		void next()
+		{
+			const char_t* cur = _cur;
+
+			while (PUGI__IS_CHARTYPE(*cur, ct_space)) ++cur;
+
+			// save lexeme position for error reporting
+			_cur_lexeme_pos = cur;
+
+			switch (*cur)
+			{
+			case 0:
+				_cur_lexeme = lex_eof;
+				break;
+
+			case '>':
+				if (*(cur+1) == '=')
+				{
+					cur += 2;
+					_cur_lexeme = lex_greater_or_equal;
+				}
+				else
+				{
+					cur += 1;
+					_cur_lexeme = lex_greater;
+				}
+				break;
+
+			case '<':
+				if (*(cur+1) == '=')
+				{
+					cur += 2;
+					_cur_lexeme = lex_less_or_equal;
+				}
+				else
+				{
+					cur += 1;
+					_cur_lexeme = lex_less;
+				}
+				break;
+
+			case '!':
+				if (*(cur+1) == '=')
+				{
+					cur += 2;
+					_cur_lexeme = lex_not_equal;
+				}
+				else
+				{
+					_cur_lexeme = lex_none;
+				}
+				break;
+
+			case '=':
+				cur += 1;
+				_cur_lexeme = lex_equal;
+
+				break;
+
+			case '+':
+				cur += 1;
+				_cur_lexeme = lex_plus;
+
+				break;
+
+			case '-':
+				cur += 1;
+				_cur_lexeme = lex_minus;
+
+				break;
+
+			case '*':
+				cur += 1;
+				_cur_lexeme = lex_multiply;
+
+				break;
+
+			case '|':
+				cur += 1;
+				_cur_lexeme = lex_union;
+
+				break;
+
+			case '$':
+				cur += 1;
+
+				if (PUGI__IS_CHARTYPEX(*cur, ctx_start_symbol))
+				{
+					_cur_lexeme_contents.begin = cur;
+
+					while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) cur++;
+
+					if (cur[0] == ':' && PUGI__IS_CHARTYPEX(cur[1], ctx_symbol)) // qname
+					{
+						cur++; // :
+
+						while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) cur++;
+					}
+
+					_cur_lexeme_contents.end = cur;
+
+					_cur_lexeme = lex_var_ref;
+				}
+				else
+				{
+					_cur_lexeme = lex_none;
+				}
+
+				break;
+
+			case '(':
+				cur += 1;
+				_cur_lexeme = lex_open_brace;
+
+				break;
+
+			case ')':
+				cur += 1;
+				_cur_lexeme = lex_close_brace;
+
+				break;
+
+			case '[':
+				cur += 1;
+				_cur_lexeme = lex_open_square_brace;
+
+				break;
+
+			case ']':
+				cur += 1;
+				_cur_lexeme = lex_close_square_brace;
+
+				break;
+
+			case ',':
+				cur += 1;
+				_cur_lexeme = lex_comma;
+
+				break;
+
+			case '/':
+				if (*(cur+1) == '/')
+				{
+					cur += 2;
+					_cur_lexeme = lex_double_slash;
+				}
+				else
+				{
+					cur += 1;
+					_cur_lexeme = lex_slash;
+				}
+				break;
+
+			case '.':
+				if (*(cur+1) == '.')
+				{
+					cur += 2;
+					_cur_lexeme = lex_double_dot;
+				}
+				else if (PUGI__IS_CHARTYPEX(*(cur+1), ctx_digit))
+				{
+					_cur_lexeme_contents.begin = cur; // .
+
+					++cur;
+
+					while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) cur++;
+
+					_cur_lexeme_contents.end = cur;
+
+					_cur_lexeme = lex_number;
+				}
+				else
+				{
+					cur += 1;
+					_cur_lexeme = lex_dot;
+				}
+				break;
+
+			case '@':
+				cur += 1;
+				_cur_lexeme = lex_axis_attribute;
+
+				break;
+
+			case '"':
+			case '\'':
+			{
+				char_t terminator = *cur;
+
+				++cur;
+
+				_cur_lexeme_contents.begin = cur;
+				while (*cur && *cur != terminator) cur++;
+				_cur_lexeme_contents.end = cur;
+
+				if (!*cur)
+					_cur_lexeme = lex_none;
+				else
+				{
+					cur += 1;
+					_cur_lexeme = lex_quoted_string;
+				}
+
+				break;
+			}
+
+			case ':':
+				if (*(cur+1) == ':')
+				{
+					cur += 2;
+					_cur_lexeme = lex_double_colon;
+				}
+				else
+				{
+					_cur_lexeme = lex_none;
+				}
+				break;
+
+			default:
+				if (PUGI__IS_CHARTYPEX(*cur, ctx_digit))
+				{
+					_cur_lexeme_contents.begin = cur;
+
+					while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) cur++;
+
+					if (*cur == '.')
+					{
+						cur++;
+
+						while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) cur++;
+					}
+
+					_cur_lexeme_contents.end = cur;
+
+					_cur_lexeme = lex_number;
+				}
+				else if (PUGI__IS_CHARTYPEX(*cur, ctx_start_symbol))
+				{
+					_cur_lexeme_contents.begin = cur;
+
+					while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) cur++;
+
+					if (cur[0] == ':')
+					{
+						if (cur[1] == '*') // namespace test ncname:*
+						{
+							cur += 2; // :*
+						}
+						else if (PUGI__IS_CHARTYPEX(cur[1], ctx_symbol)) // namespace test qname
+						{
+							cur++; // :
+
+							while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) cur++;
+						}
+					}
+
+					_cur_lexeme_contents.end = cur;
+
+					_cur_lexeme = lex_string;
+				}
+				else
+				{
+					_cur_lexeme = lex_none;
+				}
+			}
+
+			_cur = cur;
+		}
+
+		lexeme_t current() const
+		{
+			return _cur_lexeme;
+		}
+
+		const char_t* current_pos() const
+		{
+			return _cur_lexeme_pos;
+		}
+
+		const xpath_lexer_string& contents() const
+		{
+			assert(_cur_lexeme == lex_var_ref || _cur_lexeme == lex_number || _cur_lexeme == lex_string || _cur_lexeme == lex_quoted_string);
+
+			return _cur_lexeme_contents;
+		}
+	};
+
+	enum ast_type_t
+	{
+		ast_unknown,
+		ast_op_or,						// left or right
+		ast_op_and,						// left and right
+		ast_op_equal,					// left = right
+		ast_op_not_equal,				// left != right
+		ast_op_less,					// left < right
+		ast_op_greater,					// left > right
+		ast_op_less_or_equal,			// left <= right
+		ast_op_greater_or_equal,		// left >= right
+		ast_op_add,						// left + right
+		ast_op_subtract,				// left - right
+		ast_op_multiply,				// left * right
+		ast_op_divide,					// left / right
+		ast_op_mod,						// left % right
+		ast_op_negate,					// left - right
+		ast_op_union,					// left | right
+		ast_predicate,					// apply predicate to set; next points to next predicate
+		ast_filter,						// select * from left where right
+		ast_string_constant,			// string constant
+		ast_number_constant,			// number constant
+		ast_variable,					// variable
+		ast_func_last,					// last()
+		ast_func_position,				// position()
+		ast_func_count,					// count(left)
+		ast_func_id,					// id(left)
+		ast_func_local_name_0,			// local-name()
+		ast_func_local_name_1,			// local-name(left)
+		ast_func_namespace_uri_0,		// namespace-uri()
+		ast_func_namespace_uri_1,		// namespace-uri(left)
+		ast_func_name_0,				// name()
+		ast_func_name_1,				// name(left)
+		ast_func_string_0,				// string()
+		ast_func_string_1,				// string(left)
+		ast_func_concat,				// concat(left, right, siblings)
+		ast_func_starts_with,			// starts_with(left, right)
+		ast_func_contains,				// contains(left, right)
+		ast_func_substring_before,		// substring-before(left, right)
+		ast_func_substring_after,		// substring-after(left, right)
+		ast_func_substring_2,			// substring(left, right)
+		ast_func_substring_3,			// substring(left, right, third)
+		ast_func_string_length_0,		// string-length()
+		ast_func_string_length_1,		// string-length(left)
+		ast_func_normalize_space_0,		// normalize-space()
+		ast_func_normalize_space_1,		// normalize-space(left)
+		ast_func_translate,				// translate(left, right, third)
+		ast_func_boolean,				// boolean(left)
+		ast_func_not,					// not(left)
+		ast_func_true,					// true()
+		ast_func_false,					// false()
+		ast_func_lang,					// lang(left)
+		ast_func_number_0,				// number()
+		ast_func_number_1,				// number(left)
+		ast_func_sum,					// sum(left)
+		ast_func_floor,					// floor(left)
+		ast_func_ceiling,				// ceiling(left)
+		ast_func_round,					// round(left)
+		ast_step,						// process set left with step
+		ast_step_root,					// select root node
+
+		ast_opt_translate_table,		// translate(left, right, third) where right/third are constants
+		ast_opt_compare_attribute		// @name = 'string'
+	};
+
+	enum axis_t
+	{
+		axis_ancestor,
+		axis_ancestor_or_self,
+		axis_attribute,
+		axis_child,
+		axis_descendant,
+		axis_descendant_or_self,
+		axis_following,
+		axis_following_sibling,
+		axis_namespace,
+		axis_parent,
+		axis_preceding,
+		axis_preceding_sibling,
+		axis_self
+	};
+
+	enum nodetest_t
+	{
+		nodetest_none,
+		nodetest_name,
+		nodetest_type_node,
+		nodetest_type_comment,
+		nodetest_type_pi,
+		nodetest_type_text,
+		nodetest_pi,
+		nodetest_all,
+		nodetest_all_in_namespace
+	};
+
+	enum predicate_t
+	{
+		predicate_default,
+		predicate_posinv,
+		predicate_constant,
+		predicate_constant_one
+	};
+
+	enum nodeset_eval_t
+	{
+		nodeset_eval_all,
+		nodeset_eval_any,
+		nodeset_eval_first
+	};
+
+	template <axis_t N> struct axis_to_type
+	{
+		static const axis_t axis;
+	};
+
+	template <axis_t N> const axis_t axis_to_type<N>::axis = N;
+
+	class xpath_ast_node
+	{
+	private:
+		// node type
+		char _type;
+		char _rettype;
+
+		// for ast_step
+		char _axis;
+
+		// for ast_step/ast_predicate/ast_filter
+		char _test;
+
+		// tree node structure
+		xpath_ast_node* _left;
+		xpath_ast_node* _right;
+		xpath_ast_node* _next;
+
+		union
+		{
+			// value for ast_string_constant
+			const char_t* string;
+			// value for ast_number_constant
+			double number;
+			// variable for ast_variable
+			xpath_variable* variable;
+			// node test for ast_step (node name/namespace/node type/pi target)
+			const char_t* nodetest;
+			// table for ast_opt_translate_table
+			const unsigned char* table;
+		} _data;
+
+		xpath_ast_node(const xpath_ast_node&);
+		xpath_ast_node& operator=(const xpath_ast_node&);
+
+		template <class Comp> static bool compare_eq(xpath_ast_node* lhs, xpath_ast_node* rhs, const xpath_context& c, const xpath_stack& stack, const Comp& comp)
+		{
+			xpath_value_type lt = lhs->rettype(), rt = rhs->rettype();
+
+			if (lt != xpath_type_node_set && rt != xpath_type_node_set)
+			{
+				if (lt == xpath_type_boolean || rt == xpath_type_boolean)
+					return comp(lhs->eval_boolean(c, stack), rhs->eval_boolean(c, stack));
+				else if (lt == xpath_type_number || rt == xpath_type_number)
+					return comp(lhs->eval_number(c, stack), rhs->eval_number(c, stack));
+				else if (lt == xpath_type_string || rt == xpath_type_string)
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					xpath_string ls = lhs->eval_string(c, stack);
+					xpath_string rs = rhs->eval_string(c, stack);
+
+					return comp(ls, rs);
+				}
+			}
+			else if (lt == xpath_type_node_set && rt == xpath_type_node_set)
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all);
+				xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all);
+
+				for (const xpath_node* li = ls.begin(); li != ls.end(); ++li)
+					for (const xpath_node* ri = rs.begin(); ri != rs.end(); ++ri)
+					{
+						xpath_allocator_capture cri(stack.result);
+
+						if (comp(string_value(*li, stack.result), string_value(*ri, stack.result)))
+							return true;
+					}
+
+				return false;
+			}
+			else
+			{
+				if (lt == xpath_type_node_set)
+				{
+					swap(lhs, rhs);
+					swap(lt, rt);
+				}
+
+				if (lt == xpath_type_boolean)
+					return comp(lhs->eval_boolean(c, stack), rhs->eval_boolean(c, stack));
+				else if (lt == xpath_type_number)
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					double l = lhs->eval_number(c, stack);
+					xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all);
+
+					for (const xpath_node* ri = rs.begin(); ri != rs.end(); ++ri)
+					{
+						xpath_allocator_capture cri(stack.result);
+
+						if (comp(l, convert_string_to_number(string_value(*ri, stack.result).c_str())))
+							return true;
+					}
+
+					return false;
+				}
+				else if (lt == xpath_type_string)
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					xpath_string l = lhs->eval_string(c, stack);
+					xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all);
+
+					for (const xpath_node* ri = rs.begin(); ri != rs.end(); ++ri)
+					{
+						xpath_allocator_capture cri(stack.result);
+
+						if (comp(l, string_value(*ri, stack.result)))
+							return true;
+					}
+
+					return false;
+				}
+			}
+
+			assert(false && "Wrong types");
+			return false;
+		}
+
+		static bool eval_once(xpath_node_set::type_t type, nodeset_eval_t eval)
+		{
+			return type == xpath_node_set::type_sorted ? eval != nodeset_eval_all : eval == nodeset_eval_any;
+		}
+
+		template <class Comp> static bool compare_rel(xpath_ast_node* lhs, xpath_ast_node* rhs, const xpath_context& c, const xpath_stack& stack, const Comp& comp)
+		{
+			xpath_value_type lt = lhs->rettype(), rt = rhs->rettype();
+
+			if (lt != xpath_type_node_set && rt != xpath_type_node_set)
+				return comp(lhs->eval_number(c, stack), rhs->eval_number(c, stack));
+			else if (lt == xpath_type_node_set && rt == xpath_type_node_set)
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all);
+				xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all);
+
+				for (const xpath_node* li = ls.begin(); li != ls.end(); ++li)
+				{
+					xpath_allocator_capture cri(stack.result);
+
+					double l = convert_string_to_number(string_value(*li, stack.result).c_str());
+
+					for (const xpath_node* ri = rs.begin(); ri != rs.end(); ++ri)
+					{
+						xpath_allocator_capture crii(stack.result);
+
+						if (comp(l, convert_string_to_number(string_value(*ri, stack.result).c_str())))
+							return true;
+					}
+				}
+
+				return false;
+			}
+			else if (lt != xpath_type_node_set && rt == xpath_type_node_set)
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				double l = lhs->eval_number(c, stack);
+				xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all);
+
+				for (const xpath_node* ri = rs.begin(); ri != rs.end(); ++ri)
+				{
+					xpath_allocator_capture cri(stack.result);
+
+					if (comp(l, convert_string_to_number(string_value(*ri, stack.result).c_str())))
+						return true;
+				}
+
+				return false;
+			}
+			else if (lt == xpath_type_node_set && rt != xpath_type_node_set)
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all);
+				double r = rhs->eval_number(c, stack);
+
+				for (const xpath_node* li = ls.begin(); li != ls.end(); ++li)
+				{
+					xpath_allocator_capture cri(stack.result);
+
+					if (comp(convert_string_to_number(string_value(*li, stack.result).c_str()), r))
+						return true;
+				}
+
+				return false;
+			}
+			else
+			{
+				assert(false && "Wrong types");
+				return false;
+			}
+		}
+
+		static void apply_predicate_boolean(xpath_node_set_raw& ns, size_t first, xpath_ast_node* expr, const xpath_stack& stack, bool once)
+		{
+			assert(ns.size() >= first);
+			assert(expr->rettype() != xpath_type_number);
+
+			size_t i = 1;
+			size_t size = ns.size() - first;
+
+			xpath_node* last = ns.begin() + first;
+
+			// remove_if... or well, sort of
+			for (xpath_node* it = last; it != ns.end(); ++it, ++i)
+			{
+				xpath_context c(*it, i, size);
+
+				if (expr->eval_boolean(c, stack))
+				{
+					*last++ = *it;
+
+					if (once) break;
+				}
+			}
+
+			ns.truncate(last);
+		}
+
+		static void apply_predicate_number(xpath_node_set_raw& ns, size_t first, xpath_ast_node* expr, const xpath_stack& stack, bool once)
+		{
+			assert(ns.size() >= first);
+			assert(expr->rettype() == xpath_type_number);
+
+			size_t i = 1;
+			size_t size = ns.size() - first;
+
+			xpath_node* last = ns.begin() + first;
+
+			// remove_if... or well, sort of
+			for (xpath_node* it = last; it != ns.end(); ++it, ++i)
+			{
+				xpath_context c(*it, i, size);
+
+				if (expr->eval_number(c, stack) == i)
+				{
+					*last++ = *it;
+
+					if (once) break;
+				}
+			}
+
+			ns.truncate(last);
+		}
+
+		static void apply_predicate_number_const(xpath_node_set_raw& ns, size_t first, xpath_ast_node* expr, const xpath_stack& stack)
+		{
+			assert(ns.size() >= first);
+			assert(expr->rettype() == xpath_type_number);
+
+			size_t size = ns.size() - first;
+
+			xpath_node* last = ns.begin() + first;
+
+			xpath_context c(xpath_node(), 1, size);
+
+			double er = expr->eval_number(c, stack);
+
+			if (er >= 1.0 && er <= size)
+			{
+				size_t eri = static_cast<size_t>(er);
+
+				if (er == eri)
+				{
+					xpath_node r = last[eri - 1];
+
+					*last++ = r;
+				}
+			}
+
+			ns.truncate(last);
+		}
+
+		void apply_predicate(xpath_node_set_raw& ns, size_t first, const xpath_stack& stack, bool once)
+		{
+			if (ns.size() == first) return;
+
+			assert(_type == ast_filter || _type == ast_predicate);
+
+			if (_test == predicate_constant || _test == predicate_constant_one)
+				apply_predicate_number_const(ns, first, _right, stack);
+			else if (_right->rettype() == xpath_type_number)
+				apply_predicate_number(ns, first, _right, stack, once);
+			else
+				apply_predicate_boolean(ns, first, _right, stack, once);
+		}
+
+		void apply_predicates(xpath_node_set_raw& ns, size_t first, const xpath_stack& stack, nodeset_eval_t eval)
+		{
+			if (ns.size() == first) return;
+
+			bool last_once = eval_once(ns.type(), eval);
+
+			for (xpath_ast_node* pred = _right; pred; pred = pred->_next)
+				pred->apply_predicate(ns, first, stack, !pred->_next && last_once);
+		}
+
+		bool step_push(xpath_node_set_raw& ns, xml_attribute_struct* a, xml_node_struct* parent, xpath_allocator* alloc)
+		{
+			assert(a);
+
+			const char_t* name = a->name ? a->name + 0 : PUGIXML_TEXT("");
+
+			switch (_test)
+			{
+			case nodetest_name:
+				if (strequal(name, _data.nodetest) && is_xpath_attribute(name))
+				{
+					ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_type_node:
+			case nodetest_all:
+				if (is_xpath_attribute(name))
+				{
+					ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_all_in_namespace:
+				if (starts_with(name, _data.nodetest) && is_xpath_attribute(name))
+				{
+					ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc);
+					return true;
+				}
+				break;
+
+			default:
+				;
+			}
+
+			return false;
+		}
+
+		bool step_push(xpath_node_set_raw& ns, xml_node_struct* n, xpath_allocator* alloc)
+		{
+			assert(n);
+
+			xml_node_type type = PUGI__NODETYPE(n);
+
+			switch (_test)
+			{
+			case nodetest_name:
+				if (type == node_element && n->name && strequal(n->name, _data.nodetest))
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_type_node:
+				ns.push_back(xml_node(n), alloc);
+				return true;
+
+			case nodetest_type_comment:
+				if (type == node_comment)
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_type_text:
+				if (type == node_pcdata || type == node_cdata)
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_type_pi:
+				if (type == node_pi)
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_pi:
+				if (type == node_pi && n->name && strequal(n->name, _data.nodetest))
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_all:
+				if (type == node_element)
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			case nodetest_all_in_namespace:
+				if (type == node_element && n->name && starts_with(n->name, _data.nodetest))
+				{
+					ns.push_back(xml_node(n), alloc);
+					return true;
+				}
+				break;
+
+			default:
+				assert(false && "Unknown axis");
+			}
+
+			return false;
+		}
+
+		template <class T> void step_fill(xpath_node_set_raw& ns, xml_node_struct* n, xpath_allocator* alloc, bool once, T)
+		{
+			const axis_t axis = T::axis;
+
+			switch (axis)
+			{
+			case axis_attribute:
+			{
+				for (xml_attribute_struct* a = n->first_attribute; a; a = a->next_attribute)
+					if (step_push(ns, a, n, alloc) & once)
+						return;
+
+				break;
+			}
+
+			case axis_child:
+			{
+				for (xml_node_struct* c = n->first_child; c; c = c->next_sibling)
+					if (step_push(ns, c, alloc) & once)
+						return;
+
+				break;
+			}
+
+			case axis_descendant:
+			case axis_descendant_or_self:
+			{
+				if (axis == axis_descendant_or_self)
+					if (step_push(ns, n, alloc) & once)
+						return;
+
+				xml_node_struct* cur = n->first_child;
+
+				while (cur)
+				{
+					if (step_push(ns, cur, alloc) & once)
+						return;
+
+					if (cur->first_child)
+						cur = cur->first_child;
+					else
+					{
+						while (!cur->next_sibling)
+						{
+							cur = cur->parent;
+
+							if (cur == n) return;
+						}
+
+						cur = cur->next_sibling;
+					}
+				}
+
+				break;
+			}
+
+			case axis_following_sibling:
+			{
+				for (xml_node_struct* c = n->next_sibling; c; c = c->next_sibling)
+					if (step_push(ns, c, alloc) & once)
+						return;
+
+				break;
+			}
+
+			case axis_preceding_sibling:
+			{
+				for (xml_node_struct* c = n->prev_sibling_c; c->next_sibling; c = c->prev_sibling_c)
+					if (step_push(ns, c, alloc) & once)
+						return;
+
+				break;
+			}
+
+			case axis_following:
+			{
+				xml_node_struct* cur = n;
+
+				// exit from this node so that we don't include descendants
+				while (!cur->next_sibling)
+				{
+					cur = cur->parent;
+
+					if (!cur) return;
+				}
+
+				cur = cur->next_sibling;
+
+				while (cur)
+				{
+					if (step_push(ns, cur, alloc) & once)
+						return;
+
+					if (cur->first_child)
+						cur = cur->first_child;
+					else
+					{
+						while (!cur->next_sibling)
+						{
+							cur = cur->parent;
+
+							if (!cur) return;
+						}
+
+						cur = cur->next_sibling;
+					}
+				}
+
+				break;
+			}
+
+			case axis_preceding:
+			{
+				xml_node_struct* cur = n;
+
+				// exit from this node so that we don't include descendants
+				while (!cur->prev_sibling_c->next_sibling)
+				{
+					cur = cur->parent;
+
+					if (!cur) return;
+				}
+
+				cur = cur->prev_sibling_c;
+
+				while (cur)
+				{
+					if (cur->first_child)
+						cur = cur->first_child->prev_sibling_c;
+					else
+					{
+						// leaf node, can't be ancestor
+						if (step_push(ns, cur, alloc) & once)
+							return;
+
+						while (!cur->prev_sibling_c->next_sibling)
+						{
+							cur = cur->parent;
+
+							if (!cur) return;
+
+							if (!node_is_ancestor(cur, n))
+								if (step_push(ns, cur, alloc) & once)
+									return;
+						}
+
+						cur = cur->prev_sibling_c;
+					}
+				}
+
+				break;
+			}
+
+			case axis_ancestor:
+			case axis_ancestor_or_self:
+			{
+				if (axis == axis_ancestor_or_self)
+					if (step_push(ns, n, alloc) & once)
+						return;
+
+				xml_node_struct* cur = n->parent;
+
+				while (cur)
+				{
+					if (step_push(ns, cur, alloc) & once)
+						return;
+
+					cur = cur->parent;
+				}
+
+				break;
+			}
+
+			case axis_self:
+			{
+				step_push(ns, n, alloc);
+
+				break;
+			}
+
+			case axis_parent:
+			{
+				if (n->parent)
+					step_push(ns, n->parent, alloc);
+
+				break;
+			}
+
+			default:
+				assert(false && "Unimplemented axis");
+			}
+		}
+
+		template <class T> void step_fill(xpath_node_set_raw& ns, xml_attribute_struct* a, xml_node_struct* p, xpath_allocator* alloc, bool once, T v)
+		{
+			const axis_t axis = T::axis;
+
+			switch (axis)
+			{
+			case axis_ancestor:
+			case axis_ancestor_or_self:
+			{
+				if (axis == axis_ancestor_or_self && _test == nodetest_type_node) // reject attributes based on principal node type test
+					if (step_push(ns, a, p, alloc) & once)
+						return;
+
+				xml_node_struct* cur = p;
+
+				while (cur)
+				{
+					if (step_push(ns, cur, alloc) & once)
+						return;
+
+					cur = cur->parent;
+				}
+
+				break;
+			}
+
+			case axis_descendant_or_self:
+			case axis_self:
+			{
+				if (_test == nodetest_type_node) // reject attributes based on principal node type test
+					step_push(ns, a, p, alloc);
+
+				break;
+			}
+
+			case axis_following:
+			{
+				xml_node_struct* cur = p;
+
+				while (cur)
+				{
+					if (cur->first_child)
+						cur = cur->first_child;
+					else
+					{
+						while (!cur->next_sibling)
+						{
+							cur = cur->parent;
+
+							if (!cur) return;
+						}
+
+						cur = cur->next_sibling;
+					}
+
+					if (step_push(ns, cur, alloc) & once)
+						return;
+				}
+
+				break;
+			}
+
+			case axis_parent:
+			{
+				step_push(ns, p, alloc);
+
+				break;
+			}
+
+			case axis_preceding:
+			{
+				// preceding:: axis does not include attribute nodes and attribute ancestors (they are the same as parent's ancestors), so we can reuse node preceding
+				step_fill(ns, p, alloc, once, v);
+				break;
+			}
+
+			default:
+				assert(false && "Unimplemented axis");
+			}
+		}
+
+		template <class T> void step_fill(xpath_node_set_raw& ns, const xpath_node& xn, xpath_allocator* alloc, bool once, T v)
+		{
+			const axis_t axis = T::axis;
+			const bool axis_has_attributes = (axis == axis_ancestor || axis == axis_ancestor_or_self || axis == axis_descendant_or_self || axis == axis_following || axis == axis_parent || axis == axis_preceding || axis == axis_self);
+
+			if (xn.node())
+				step_fill(ns, xn.node().internal_object(), alloc, once, v);
+			else if (axis_has_attributes && xn.attribute() && xn.parent())
+				step_fill(ns, xn.attribute().internal_object(), xn.parent().internal_object(), alloc, once, v);
+		}
+
+		template <class T> xpath_node_set_raw step_do(const xpath_context& c, const xpath_stack& stack, nodeset_eval_t eval, T v)
+		{
+			const axis_t axis = T::axis;
+			const bool axis_reverse = (axis == axis_ancestor || axis == axis_ancestor_or_self || axis == axis_preceding || axis == axis_preceding_sibling);
+			const xpath_node_set::type_t axis_type = axis_reverse ? xpath_node_set::type_sorted_reverse : xpath_node_set::type_sorted;
+
+			bool once =
+				(axis == axis_attribute && _test == nodetest_name) ||
+				(!_right && eval_once(axis_type, eval)) ||
+				(_right && !_right->_next && _right->_test == predicate_constant_one);
+
+			xpath_node_set_raw ns;
+			ns.set_type(axis_type);
+
+			if (_left)
+			{
+				xpath_node_set_raw s = _left->eval_node_set(c, stack, nodeset_eval_all);
+
+				// self axis preserves the original order
+				if (axis == axis_self) ns.set_type(s.type());
+
+				for (const xpath_node* it = s.begin(); it != s.end(); ++it)
+				{
+					size_t size = ns.size();
+
+					// in general, all axes generate elements in a particular order, but there is no order guarantee if axis is applied to two nodes
+					if (axis != axis_self && size != 0) ns.set_type(xpath_node_set::type_unsorted);
+
+					step_fill(ns, *it, stack.result, once, v);
+					if (_right) apply_predicates(ns, size, stack, eval);
+				}
+			}
+			else
+			{
+				step_fill(ns, c.n, stack.result, once, v);
+				if (_right) apply_predicates(ns, 0, stack, eval);
+			}
+
+			// child, attribute and self axes always generate unique set of nodes
+			// for other axis, if the set stayed sorted, it stayed unique because the traversal algorithms do not visit the same node twice
+			if (axis != axis_child && axis != axis_attribute && axis != axis_self && ns.type() == xpath_node_set::type_unsorted)
+				ns.remove_duplicates();
+
+			return ns;
+		}
+
+	public:
+		xpath_ast_node(ast_type_t type, xpath_value_type rettype_, const char_t* value):
+			_type(static_cast<char>(type)), _rettype(static_cast<char>(rettype_)), _axis(0), _test(0), _left(0), _right(0), _next(0)
+		{
+			assert(type == ast_string_constant);
+			_data.string = value;
+		}
+
+		xpath_ast_node(ast_type_t type, xpath_value_type rettype_, double value):
+			_type(static_cast<char>(type)), _rettype(static_cast<char>(rettype_)), _axis(0), _test(0), _left(0), _right(0), _next(0)
+		{
+			assert(type == ast_number_constant);
+			_data.number = value;
+		}
+
+		xpath_ast_node(ast_type_t type, xpath_value_type rettype_, xpath_variable* value):
+			_type(static_cast<char>(type)), _rettype(static_cast<char>(rettype_)), _axis(0), _test(0), _left(0), _right(0), _next(0)
+		{
+			assert(type == ast_variable);
+			_data.variable = value;
+		}
+
+		xpath_ast_node(ast_type_t type, xpath_value_type rettype_, xpath_ast_node* left = 0, xpath_ast_node* right = 0):
+			_type(static_cast<char>(type)), _rettype(static_cast<char>(rettype_)), _axis(0), _test(0), _left(left), _right(right), _next(0)
+		{
+		}
+
+		xpath_ast_node(ast_type_t type, xpath_ast_node* left, axis_t axis, nodetest_t test, const char_t* contents):
+			_type(static_cast<char>(type)), _rettype(xpath_type_node_set), _axis(static_cast<char>(axis)), _test(static_cast<char>(test)), _left(left), _right(0), _next(0)
+		{
+			assert(type == ast_step);
+			_data.nodetest = contents;
+		}
+
+		xpath_ast_node(ast_type_t type, xpath_ast_node* left, xpath_ast_node* right, predicate_t test):
+			_type(static_cast<char>(type)), _rettype(xpath_type_node_set), _axis(0), _test(static_cast<char>(test)), _left(left), _right(right), _next(0)
+		{
+			assert(type == ast_filter || type == ast_predicate);
+		}
+
+		void set_next(xpath_ast_node* value)
+		{
+			_next = value;
+		}
+
+		void set_right(xpath_ast_node* value)
+		{
+			_right = value;
+		}
+
+		bool eval_boolean(const xpath_context& c, const xpath_stack& stack)
+		{
+			switch (_type)
+			{
+			case ast_op_or:
+				return _left->eval_boolean(c, stack) || _right->eval_boolean(c, stack);
+
+			case ast_op_and:
+				return _left->eval_boolean(c, stack) && _right->eval_boolean(c, stack);
+
+			case ast_op_equal:
+				return compare_eq(_left, _right, c, stack, equal_to());
+
+			case ast_op_not_equal:
+				return compare_eq(_left, _right, c, stack, not_equal_to());
+
+			case ast_op_less:
+				return compare_rel(_left, _right, c, stack, less());
+
+			case ast_op_greater:
+				return compare_rel(_right, _left, c, stack, less());
+
+			case ast_op_less_or_equal:
+				return compare_rel(_left, _right, c, stack, less_equal());
+
+			case ast_op_greater_or_equal:
+				return compare_rel(_right, _left, c, stack, less_equal());
+
+			case ast_func_starts_with:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_string lr = _left->eval_string(c, stack);
+				xpath_string rr = _right->eval_string(c, stack);
+
+				return starts_with(lr.c_str(), rr.c_str());
+			}
+
+			case ast_func_contains:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_string lr = _left->eval_string(c, stack);
+				xpath_string rr = _right->eval_string(c, stack);
+
+				return find_substring(lr.c_str(), rr.c_str()) != 0;
+			}
+
+			case ast_func_boolean:
+				return _left->eval_boolean(c, stack);
+
+			case ast_func_not:
+				return !_left->eval_boolean(c, stack);
+
+			case ast_func_true:
+				return true;
+
+			case ast_func_false:
+				return false;
+
+			case ast_func_lang:
+			{
+				if (c.n.attribute()) return false;
+
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_string lang = _left->eval_string(c, stack);
+
+				for (xml_node n = c.n.node(); n; n = n.parent())
+				{
+					xml_attribute a = n.attribute(PUGIXML_TEXT("xml:lang"));
+
+					if (a)
+					{
+						const char_t* value = a.value();
+
+						// strnicmp / strncasecmp is not portable
+						for (const char_t* lit = lang.c_str(); *lit; ++lit)
+						{
+							if (tolower_ascii(*lit) != tolower_ascii(*value)) return false;
+							++value;
+						}
+
+						return *value == 0 || *value == '-';
+					}
+				}
+
+				return false;
+			}
+
+			case ast_opt_compare_attribute:
+			{
+				const char_t* value = (_right->_type == ast_string_constant) ? _right->_data.string : _right->_data.variable->get_string();
+
+				xml_attribute attr = c.n.node().attribute(_left->_data.nodetest);
+
+				return attr && strequal(attr.value(), value) && is_xpath_attribute(attr.name());
+			}
+
+			case ast_variable:
+			{
+				assert(_rettype == _data.variable->type());
+
+				if (_rettype == xpath_type_boolean)
+					return _data.variable->get_boolean();
+
+				// fallthrough to type conversion
+			}
+
+			default:
+			{
+				switch (_rettype)
+				{
+				case xpath_type_number:
+					return convert_number_to_boolean(eval_number(c, stack));
+
+				case xpath_type_string:
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					return !eval_string(c, stack).empty();
+				}
+
+				case xpath_type_node_set:
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					return !eval_node_set(c, stack, nodeset_eval_any).empty();
+				}
+
+				default:
+					assert(false && "Wrong expression for return type boolean");
+					return false;
+				}
+			}
+			}
+		}
+
+		double eval_number(const xpath_context& c, const xpath_stack& stack)
+		{
+			switch (_type)
+			{
+			case ast_op_add:
+				return _left->eval_number(c, stack) + _right->eval_number(c, stack);
+
+			case ast_op_subtract:
+				return _left->eval_number(c, stack) - _right->eval_number(c, stack);
+
+			case ast_op_multiply:
+				return _left->eval_number(c, stack) * _right->eval_number(c, stack);
+
+			case ast_op_divide:
+				return _left->eval_number(c, stack) / _right->eval_number(c, stack);
+
+			case ast_op_mod:
+				return fmod(_left->eval_number(c, stack), _right->eval_number(c, stack));
+
+			case ast_op_negate:
+				return -_left->eval_number(c, stack);
+
+			case ast_number_constant:
+				return _data.number;
+
+			case ast_func_last:
+				return static_cast<double>(c.size);
+
+			case ast_func_position:
+				return static_cast<double>(c.position);
+
+			case ast_func_count:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				return static_cast<double>(_left->eval_node_set(c, stack, nodeset_eval_all).size());
+			}
+
+			case ast_func_string_length_0:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				return static_cast<double>(string_value(c.n, stack.result).length());
+			}
+
+			case ast_func_string_length_1:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				return static_cast<double>(_left->eval_string(c, stack).length());
+			}
+
+			case ast_func_number_0:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				return convert_string_to_number(string_value(c.n, stack.result).c_str());
+			}
+
+			case ast_func_number_1:
+				return _left->eval_number(c, stack);
+
+			case ast_func_sum:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				double r = 0;
+
+				xpath_node_set_raw ns = _left->eval_node_set(c, stack, nodeset_eval_all);
+
+				for (const xpath_node* it = ns.begin(); it != ns.end(); ++it)
+				{
+					xpath_allocator_capture cri(stack.result);
+
+					r += convert_string_to_number(string_value(*it, stack.result).c_str());
+				}
+
+				return r;
+			}
+
+			case ast_func_floor:
+			{
+				double r = _left->eval_number(c, stack);
+
+				return r == r ? floor(r) : r;
+			}
+
+			case ast_func_ceiling:
+			{
+				double r = _left->eval_number(c, stack);
+
+				return r == r ? ceil(r) : r;
+			}
+
+			case ast_func_round:
+				return round_nearest_nzero(_left->eval_number(c, stack));
+
+			case ast_variable:
+			{
+				assert(_rettype == _data.variable->type());
+
+				if (_rettype == xpath_type_number)
+					return _data.variable->get_number();
+
+				// fallthrough to type conversion
+			}
+
+			default:
+			{
+				switch (_rettype)
+				{
+				case xpath_type_boolean:
+					return eval_boolean(c, stack) ? 1 : 0;
+
+				case xpath_type_string:
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					return convert_string_to_number(eval_string(c, stack).c_str());
+				}
+
+				case xpath_type_node_set:
+				{
+					xpath_allocator_capture cr(stack.result);
+
+					return convert_string_to_number(eval_string(c, stack).c_str());
+				}
+
+				default:
+					assert(false && "Wrong expression for return type number");
+					return 0;
+				}
+
+			}
+			}
+		}
+
+		xpath_string eval_string_concat(const xpath_context& c, const xpath_stack& stack)
+		{
+			assert(_type == ast_func_concat);
+
+			xpath_allocator_capture ct(stack.temp);
+
+			// count the string number
+			size_t count = 1;
+			for (xpath_ast_node* nc = _right; nc; nc = nc->_next) count++;
+
+			// gather all strings
+			xpath_string static_buffer[4];
+			xpath_string* buffer = static_buffer;
+
+			// allocate on-heap for large concats
+			if (count > sizeof(static_buffer) / sizeof(static_buffer[0]))
+			{
+				buffer = static_cast<xpath_string*>(stack.temp->allocate(count * sizeof(xpath_string)));
+				assert(buffer);
+			}
+
+			// evaluate all strings to temporary stack
+			xpath_stack swapped_stack = {stack.temp, stack.result};
+
+			buffer[0] = _left->eval_string(c, swapped_stack);
+
+			size_t pos = 1;
+			for (xpath_ast_node* n = _right; n; n = n->_next, ++pos) buffer[pos] = n->eval_string(c, swapped_stack);
+			assert(pos == count);
+
+			// get total length
+			size_t length = 0;
+			for (size_t i = 0; i < count; ++i) length += buffer[i].length();
+
+			// create final string
+			char_t* result = static_cast<char_t*>(stack.result->allocate((length + 1) * sizeof(char_t)));
+			assert(result);
+
+			char_t* ri = result;
+
+			for (size_t j = 0; j < count; ++j)
+				for (const char_t* bi = buffer[j].c_str(); *bi; ++bi)
+					*ri++ = *bi;
+
+			*ri = 0;
+
+			return xpath_string::from_heap_preallocated(result, ri);
+		}
+
+		xpath_string eval_string(const xpath_context& c, const xpath_stack& stack)
+		{
+			switch (_type)
+			{
+			case ast_string_constant:
+				return xpath_string::from_const(_data.string);
+
+			case ast_func_local_name_0:
+			{
+				xpath_node na = c.n;
+
+				return xpath_string::from_const(local_name(na));
+			}
+
+			case ast_func_local_name_1:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_node_set_raw ns = _left->eval_node_set(c, stack, nodeset_eval_first);
+				xpath_node na = ns.first();
+
+				return xpath_string::from_const(local_name(na));
+			}
+
+			case ast_func_name_0:
+			{
+				xpath_node na = c.n;
+
+				return xpath_string::from_const(qualified_name(na));
+			}
+
+			case ast_func_name_1:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_node_set_raw ns = _left->eval_node_set(c, stack, nodeset_eval_first);
+				xpath_node na = ns.first();
+
+				return xpath_string::from_const(qualified_name(na));
+			}
+
+			case ast_func_namespace_uri_0:
+			{
+				xpath_node na = c.n;
+
+				return xpath_string::from_const(namespace_uri(na));
+			}
+
+			case ast_func_namespace_uri_1:
+			{
+				xpath_allocator_capture cr(stack.result);
+
+				xpath_node_set_raw ns = _left->eval_node_set(c, stack, nodeset_eval_first);
+				xpath_node na = ns.first();
+
+				return xpath_string::from_const(namespace_uri(na));
+			}
+
+			case ast_func_string_0:
+				return string_value(c.n, stack.result);
+
+			case ast_func_string_1:
+				return _left->eval_string(c, stack);
+
+			case ast_func_concat:
+				return eval_string_concat(c, stack);
+
+			case ast_func_substring_before:
+			{
+				xpath_allocator_capture cr(stack.temp);
+
+				xpath_stack swapped_stack = {stack.temp, stack.result};
+
+				xpath_string s = _left->eval_string(c, swapped_stack);
+				xpath_string p = _right->eval_string(c, swapped_stack);
+
+				const char_t* pos = find_substring(s.c_str(), p.c_str());
+
+				return pos ? xpath_string::from_heap(s.c_str(), pos, stack.result) : xpath_string();
+			}
+
+			case ast_func_substring_after:
+			{
+				xpath_allocator_capture cr(stack.temp);
+
+				xpath_stack swapped_stack = {stack.temp, stack.result};
+
+				xpath_string s = _left->eval_string(c, swapped_stack);
+				xpath_string p = _right->eval_string(c, swapped_stack);
+
+				const char_t* pos = find_substring(s.c_str(), p.c_str());
+				if (!pos) return xpath_string();
+
+				const char_t* rbegin = pos + p.length();
+				const char_t* rend = s.c_str() + s.length();
+
+				return s.uses_heap() ? xpath_string::from_heap(rbegin, rend, stack.result) : xpath_string::from_const(rbegin);
+			}
+
+			case ast_func_substring_2:
+			{
+				xpath_allocator_capture cr(stack.temp);
+
+				xpath_stack swapped_stack = {stack.temp, stack.result};
+
+				xpath_string s = _left->eval_string(c, swapped_stack);
+				size_t s_length = s.length();
+
+				double first = round_nearest(_right->eval_number(c, stack));
+
+				if (is_nan(first)) return xpath_string(); // NaN
+				else if (first >= s_length + 1) return xpath_string();
+
+				size_t pos = first < 1 ? 1 : static_cast<size_t>(first);
+				assert(1 <= pos && pos <= s_length + 1);
+
+				const char_t* rbegin = s.c_str() + (pos - 1);
+				const char_t* rend = s.c_str() + s.length();
+
+				return s.uses_heap() ? xpath_string::from_heap(rbegin, rend, stack.result) : xpath_string::from_const(rbegin);
+			}
+
+			case ast_func_substring_3:
+			{
+				xpath_allocator_capture cr(stack.temp);
+
+				xpath_stack swapped_stack = {stack.temp, stack.result};
+
+				xpath_string s = _left->eval_string(c, swapped_stack);
+				size_t s_length = s.length();
+
+				double first = round_nearest(_right->eval_number(c, stack));
+				double last = first + round_nearest(_right->_next->eval_number(c, stack));
+
+				if (is_nan(first) || is_nan(last)) return xpath_string();
+				else if (first >= s_length + 1) return xpath_string();
+				else if (first >= last) return xpath_string();
+				else if (last < 1) return xpath_string();
+
+				size_t pos = first < 1 ? 1 : static_cast<size_t>(first);
+				size_t end = last >= s_length + 1 ? s_length + 1 : static_cast<size_t>(last);
+
+				assert(1 <= pos && pos <= end && end <= s_length + 1);
+				const char_t* rbegin = s.c_str() + (pos - 1);
+				const char_t* rend = s.c_str() + (end - 1);
+
+				return (end == s_length + 1 && !s.uses_heap()) ? xpath_string::from_const(rbegin) : xpath_string::from_heap(rbegin, rend, stack.result);
+			}
+
+			case ast_func_normalize_space_0:
+			{
+				xpath_string s = string_value(c.n, stack.result);
+
+				char_t* begin = s.data(stack.result);
+				char_t* end = normalize_space(begin);
+
+				return xpath_string::from_heap_preallocated(begin, end);
+			}
+
+			case ast_func_normalize_space_1:
+			{
+				xpath_string s = _left->eval_string(c, stack);
+
+				char_t* begin = s.data(stack.result);
+				char_t* end = normalize_space(begin);
+
+				return xpath_string::from_heap_preallocated(begin, end);
+			}
+
+			case ast_func_translate:
+			{
+				xpath_allocator_capture cr(stack.temp);
+
+				xpath_stack swapped_stack = {stack.temp, stack.result};
+
+				xpath_string s = _left->eval_string(c, stack);
+				xpath_string from = _right->eval_string(c, swapped_stack);
+				xpath_string to = _right->_next->eval_string(c, swapped_stack);
+
+				char_t* begin = s.data(stack.result);
+				char_t* end = translate(begin, from.c_str(), to.c_str(), to.length());
+
+				return xpath_string::from_heap_preallocated(begin, end);
+			}
+
+			case ast_opt_translate_table:
+			{
+				xpath_string s = _left->eval_string(c, stack);
+
+				char_t* begin = s.data(stack.result);
+				char_t* end = translate_table(begin, _data.table);
+
+				return xpath_string::from_heap_preallocated(begin, end);
+			}
+
+			case ast_variable:
+			{
+				assert(_rettype == _data.variable->type());
+
+				if (_rettype == xpath_type_string)
+					return xpath_string::from_const(_data.variable->get_string());
+
+				// fallthrough to type conversion
+			}
+
+			default:
+			{
+				switch (_rettype)
+				{
+				case xpath_type_boolean:
+					return xpath_string::from_const(eval_boolean(c, stack) ? PUGIXML_TEXT("true") : PUGIXML_TEXT("false"));
+
+				case xpath_type_number:
+					return convert_number_to_string(eval_number(c, stack), stack.result);
+
+				case xpath_type_node_set:
+				{
+					xpath_allocator_capture cr(stack.temp);
+
+					xpath_stack swapped_stack = {stack.temp, stack.result};
+
+					xpath_node_set_raw ns = eval_node_set(c, swapped_stack, nodeset_eval_first);
+					return ns.empty() ? xpath_string() : string_value(ns.first(), stack.result);
+				}
+
+				default:
+					assert(false && "Wrong expression for return type string");
+					return xpath_string();
+				}
+			}
+			}
+		}
+
+		xpath_node_set_raw eval_node_set(const xpath_context& c, const xpath_stack& stack, nodeset_eval_t eval)
+		{
+			switch (_type)
+			{
+			case ast_op_union:
+			{
+				xpath_allocator_capture cr(stack.temp);
+
+				xpath_stack swapped_stack = {stack.temp, stack.result};
+
+				xpath_node_set_raw ls = _left->eval_node_set(c, swapped_stack, eval);
+				xpath_node_set_raw rs = _right->eval_node_set(c, stack, eval);
+
+				// we can optimize merging two sorted sets, but this is a very rare operation, so don't bother
+				rs.set_type(xpath_node_set::type_unsorted);
+
+				rs.append(ls.begin(), ls.end(), stack.result);
+				rs.remove_duplicates();
+
+				return rs;
+			}
+
+			case ast_filter:
+			{
+				xpath_node_set_raw set = _left->eval_node_set(c, stack, _test == predicate_constant_one ? nodeset_eval_first : nodeset_eval_all);
+
+				// either expression is a number or it contains position() call; sort by document order
+				if (_test != predicate_posinv) set.sort_do();
+
+				bool once = eval_once(set.type(), eval);
+
+				apply_predicate(set, 0, stack, once);
+
+				return set;
+			}
+
+			case ast_func_id:
+				return xpath_node_set_raw();
+
+			case ast_step:
+			{
+				switch (_axis)
+				{
+				case axis_ancestor:
+					return step_do(c, stack, eval, axis_to_type<axis_ancestor>());
+
+				case axis_ancestor_or_self:
+					return step_do(c, stack, eval, axis_to_type<axis_ancestor_or_self>());
+
+				case axis_attribute:
+					return step_do(c, stack, eval, axis_to_type<axis_attribute>());
+
+				case axis_child:
+					return step_do(c, stack, eval, axis_to_type<axis_child>());
+
+				case axis_descendant:
+					return step_do(c, stack, eval, axis_to_type<axis_descendant>());
+
+				case axis_descendant_or_self:
+					return step_do(c, stack, eval, axis_to_type<axis_descendant_or_self>());
+
+				case axis_following:
+					return step_do(c, stack, eval, axis_to_type<axis_following>());
+
+				case axis_following_sibling:
+					return step_do(c, stack, eval, axis_to_type<axis_following_sibling>());
+
+				case axis_namespace:
+					// namespaced axis is not supported
+					return xpath_node_set_raw();
+
+				case axis_parent:
+					return step_do(c, stack, eval, axis_to_type<axis_parent>());
+
+				case axis_preceding:
+					return step_do(c, stack, eval, axis_to_type<axis_preceding>());
+
+				case axis_preceding_sibling:
+					return step_do(c, stack, eval, axis_to_type<axis_preceding_sibling>());
+
+				case axis_self:
+					return step_do(c, stack, eval, axis_to_type<axis_self>());
+
+				default:
+					assert(false && "Unknown axis");
+					return xpath_node_set_raw();
+				}
+			}
+
+			case ast_step_root:
+			{
+				assert(!_right); // root step can't have any predicates
+
+				xpath_node_set_raw ns;
+
+				ns.set_type(xpath_node_set::type_sorted);
+
+				if (c.n.node()) ns.push_back(c.n.node().root(), stack.result);
+				else if (c.n.attribute()) ns.push_back(c.n.parent().root(), stack.result);
+
+				return ns;
+			}
+
+			case ast_variable:
+			{
+				assert(_rettype == _data.variable->type());
+
+				if (_rettype == xpath_type_node_set)
+				{
+					const xpath_node_set& s = _data.variable->get_node_set();
+
+					xpath_node_set_raw ns;
+
+					ns.set_type(s.type());
+					ns.append(s.begin(), s.end(), stack.result);
+
+					return ns;
+				}
+
+				// fallthrough to type conversion
+			}
+
+			default:
+				assert(false && "Wrong expression for return type node set");
+				return xpath_node_set_raw();
+			}
+		}
+
+		void optimize(xpath_allocator* alloc)
+		{
+			if (_left)
+				_left->optimize(alloc);
+
+			if (_right)
+				_right->optimize(alloc);
+
+			if (_next)
+				_next->optimize(alloc);
+
+			optimize_self(alloc);
+		}
+
+		void optimize_self(xpath_allocator* alloc)
+		{
+			// Rewrite [position()=expr] with [expr]
+			// Note that this step has to go before classification to recognize [position()=1]
+			if ((_type == ast_filter || _type == ast_predicate) &&
+				_right->_type == ast_op_equal && _right->_left->_type == ast_func_position && _right->_right->_rettype == xpath_type_number)
+			{
+				_right = _right->_right;
+			}
+
+			// Classify filter/predicate ops to perform various optimizations during evaluation
+			if (_type == ast_filter || _type == ast_predicate)
+			{
+				assert(_test == predicate_default);
+
+				if (_right->_type == ast_number_constant && _right->_data.number == 1.0)
+					_test = predicate_constant_one;
+				else if (_right->_rettype == xpath_type_number && (_right->_type == ast_number_constant || _right->_type == ast_variable || _right->_type == ast_func_last))
+					_test = predicate_constant;
+				else if (_right->_rettype != xpath_type_number && _right->is_posinv_expr())
+					_test = predicate_posinv;
+			}
+
+			// Rewrite descendant-or-self::node()/child::foo with descendant::foo
+			// The former is a full form of //foo, the latter is much faster since it executes the node test immediately
+			// Do a similar kind of rewrite for self/descendant/descendant-or-self axes
+			// Note that we only rewrite positionally invariant steps (//foo[1] != /descendant::foo[1])
+			if (_type == ast_step && (_axis == axis_child || _axis == axis_self || _axis == axis_descendant || _axis == axis_descendant_or_self) && _left &&
+				_left->_type == ast_step && _left->_axis == axis_descendant_or_self && _left->_test == nodetest_type_node && !_left->_right &&
+				is_posinv_step())
+			{
+				if (_axis == axis_child || _axis == axis_descendant)
+					_axis = axis_descendant;
+				else
+					_axis = axis_descendant_or_self;
+
+				_left = _left->_left;
+			}
+
+			// Use optimized lookup table implementation for translate() with constant arguments
+			if (_type == ast_func_translate && _right->_type == ast_string_constant && _right->_next->_type == ast_string_constant)
+			{
+				unsigned char* table = translate_table_generate(alloc, _right->_data.string, _right->_next->_data.string);
+
+				if (table)
+				{
+					_type = ast_opt_translate_table;
+					_data.table = table;
+				}
+			}
+
+			// Use optimized path for @attr = 'value' or @attr = $value
+			if (_type == ast_op_equal &&
+				_left->_type == ast_step && _left->_axis == axis_attribute && _left->_test == nodetest_name && !_left->_left && !_left->_right &&
+				(_right->_type == ast_string_constant || (_right->_type == ast_variable && _right->_rettype == xpath_type_string)))
+			{
+				_type = ast_opt_compare_attribute;
+			}
+		}
+
+		bool is_posinv_expr() const
+		{
+			switch (_type)
+			{
+			case ast_func_position:
+			case ast_func_last:
+				return false;
+
+			case ast_string_constant:
+			case ast_number_constant:
+			case ast_variable:
+				return true;
+
+			case ast_step:
+			case ast_step_root:
+				return true;
+
+			case ast_predicate:
+			case ast_filter:
+				return true;
+
+			default:
+				if (_left && !_left->is_posinv_expr()) return false;
+
+				for (xpath_ast_node* n = _right; n; n = n->_next)
+					if (!n->is_posinv_expr()) return false;
+
+				return true;
+			}
+		}
+
+		bool is_posinv_step() const
+		{
+			assert(_type == ast_step);
+
+			for (xpath_ast_node* n = _right; n; n = n->_next)
+			{
+				assert(n->_type == ast_predicate);
+
+				if (n->_test != predicate_posinv)
+					return false;
+			}
+
+			return true;
+		}
+
+		xpath_value_type rettype() const
+		{
+			return static_cast<xpath_value_type>(_rettype);
+		}
+	};
+
+	struct xpath_parser
+	{
+		xpath_allocator* _alloc;
+		xpath_lexer _lexer;
+
+		const char_t* _query;
+		xpath_variable_set* _variables;
+
+		xpath_parse_result* _result;
+
+		char_t _scratch[32];
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		jmp_buf _error_handler;
+	#endif
+
+		void throw_error(const char* message)
+		{
+			_result->error = message;
+			_result->offset = _lexer.current_pos() - _query;
+
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			longjmp(_error_handler, 1);
+		#else
+			throw xpath_exception(*_result);
+		#endif
+		}
+
+		void throw_error_oom()
+		{
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			throw_error("Out of memory");
+		#else
+			throw std::bad_alloc();
+		#endif
+		}
+
+		void* alloc_node()
+		{
+			void* result = _alloc->allocate_nothrow(sizeof(xpath_ast_node));
+
+			if (!result) throw_error_oom();
+
+			return result;
+		}
+
+		const char_t* alloc_string(const xpath_lexer_string& value)
+		{
+			if (value.begin)
+			{
+				size_t length = static_cast<size_t>(value.end - value.begin);
+
+				char_t* c = static_cast<char_t*>(_alloc->allocate_nothrow((length + 1) * sizeof(char_t)));
+				if (!c) throw_error_oom();
+				assert(c); // workaround for clang static analysis
+
+				memcpy(c, value.begin, length * sizeof(char_t));
+				c[length] = 0;
+
+				return c;
+			}
+			else return 0;
+		}
+
+		xpath_ast_node* parse_function_helper(ast_type_t type0, ast_type_t type1, size_t argc, xpath_ast_node* args[2])
+		{
+			assert(argc <= 1);
+
+			if (argc == 1 && args[0]->rettype() != xpath_type_node_set)
+				throw_error("Function has to be applied to node set");
+
+			return new (alloc_node()) xpath_ast_node(argc == 0 ? type0 : type1, xpath_type_string, args[0]);
+		}
+
+		xpath_ast_node* parse_function(const xpath_lexer_string& name, size_t argc, xpath_ast_node* args[2])
+		{
+			switch (name.begin[0])
+			{
+			case 'b':
+				if (name == PUGIXML_TEXT("boolean") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_boolean, xpath_type_boolean, args[0]);
+
+				break;
+
+			case 'c':
+				if (name == PUGIXML_TEXT("count") && argc == 1)
+				{
+					if (args[0]->rettype() != xpath_type_node_set)
+						throw_error("Function has to be applied to node set");
+
+					return new (alloc_node()) xpath_ast_node(ast_func_count, xpath_type_number, args[0]);
+				}
+				else if (name == PUGIXML_TEXT("contains") && argc == 2)
+					return new (alloc_node()) xpath_ast_node(ast_func_contains, xpath_type_boolean, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("concat") && argc >= 2)
+					return new (alloc_node()) xpath_ast_node(ast_func_concat, xpath_type_string, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("ceiling") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_ceiling, xpath_type_number, args[0]);
+
+				break;
+
+			case 'f':
+				if (name == PUGIXML_TEXT("false") && argc == 0)
+					return new (alloc_node()) xpath_ast_node(ast_func_false, xpath_type_boolean);
+				else if (name == PUGIXML_TEXT("floor") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_floor, xpath_type_number, args[0]);
+
+				break;
+
+			case 'i':
+				if (name == PUGIXML_TEXT("id") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_id, xpath_type_node_set, args[0]);
+
+				break;
+
+			case 'l':
+				if (name == PUGIXML_TEXT("last") && argc == 0)
+					return new (alloc_node()) xpath_ast_node(ast_func_last, xpath_type_number);
+				else if (name == PUGIXML_TEXT("lang") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_lang, xpath_type_boolean, args[0]);
+				else if (name == PUGIXML_TEXT("local-name") && argc <= 1)
+					return parse_function_helper(ast_func_local_name_0, ast_func_local_name_1, argc, args);
+
+				break;
+
+			case 'n':
+				if (name == PUGIXML_TEXT("name") && argc <= 1)
+					return parse_function_helper(ast_func_name_0, ast_func_name_1, argc, args);
+				else if (name == PUGIXML_TEXT("namespace-uri") && argc <= 1)
+					return parse_function_helper(ast_func_namespace_uri_0, ast_func_namespace_uri_1, argc, args);
+				else if (name == PUGIXML_TEXT("normalize-space") && argc <= 1)
+					return new (alloc_node()) xpath_ast_node(argc == 0 ? ast_func_normalize_space_0 : ast_func_normalize_space_1, xpath_type_string, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("not") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_not, xpath_type_boolean, args[0]);
+				else if (name == PUGIXML_TEXT("number") && argc <= 1)
+					return new (alloc_node()) xpath_ast_node(argc == 0 ? ast_func_number_0 : ast_func_number_1, xpath_type_number, args[0]);
+
+				break;
+
+			case 'p':
+				if (name == PUGIXML_TEXT("position") && argc == 0)
+					return new (alloc_node()) xpath_ast_node(ast_func_position, xpath_type_number);
+
+				break;
+
+			case 'r':
+				if (name == PUGIXML_TEXT("round") && argc == 1)
+					return new (alloc_node()) xpath_ast_node(ast_func_round, xpath_type_number, args[0]);
+
+				break;
+
+			case 's':
+				if (name == PUGIXML_TEXT("string") && argc <= 1)
+					return new (alloc_node()) xpath_ast_node(argc == 0 ? ast_func_string_0 : ast_func_string_1, xpath_type_string, args[0]);
+				else if (name == PUGIXML_TEXT("string-length") && argc <= 1)
+					return new (alloc_node()) xpath_ast_node(argc == 0 ? ast_func_string_length_0 : ast_func_string_length_1, xpath_type_number, args[0]);
+				else if (name == PUGIXML_TEXT("starts-with") && argc == 2)
+					return new (alloc_node()) xpath_ast_node(ast_func_starts_with, xpath_type_boolean, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("substring-before") && argc == 2)
+					return new (alloc_node()) xpath_ast_node(ast_func_substring_before, xpath_type_string, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("substring-after") && argc == 2)
+					return new (alloc_node()) xpath_ast_node(ast_func_substring_after, xpath_type_string, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("substring") && (argc == 2 || argc == 3))
+					return new (alloc_node()) xpath_ast_node(argc == 2 ? ast_func_substring_2 : ast_func_substring_3, xpath_type_string, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("sum") && argc == 1)
+				{
+					if (args[0]->rettype() != xpath_type_node_set) throw_error("Function has to be applied to node set");
+					return new (alloc_node()) xpath_ast_node(ast_func_sum, xpath_type_number, args[0]);
+				}
+
+				break;
+
+			case 't':
+				if (name == PUGIXML_TEXT("translate") && argc == 3)
+					return new (alloc_node()) xpath_ast_node(ast_func_translate, xpath_type_string, args[0], args[1]);
+				else if (name == PUGIXML_TEXT("true") && argc == 0)
+					return new (alloc_node()) xpath_ast_node(ast_func_true, xpath_type_boolean);
+
+				break;
+
+			default:
+				break;
+			}
+
+			throw_error("Unrecognized function or wrong parameter count");
+
+			return 0;
+		}
+
+		axis_t parse_axis_name(const xpath_lexer_string& name, bool& specified)
+		{
+			specified = true;
+
+			switch (name.begin[0])
+			{
+			case 'a':
+				if (name == PUGIXML_TEXT("ancestor"))
+					return axis_ancestor;
+				else if (name == PUGIXML_TEXT("ancestor-or-self"))
+					return axis_ancestor_or_self;
+				else if (name == PUGIXML_TEXT("attribute"))
+					return axis_attribute;
+
+				break;
+
+			case 'c':
+				if (name == PUGIXML_TEXT("child"))
+					return axis_child;
+
+				break;
+
+			case 'd':
+				if (name == PUGIXML_TEXT("descendant"))
+					return axis_descendant;
+				else if (name == PUGIXML_TEXT("descendant-or-self"))
+					return axis_descendant_or_self;
+
+				break;
+
+			case 'f':
+				if (name == PUGIXML_TEXT("following"))
+					return axis_following;
+				else if (name == PUGIXML_TEXT("following-sibling"))
+					return axis_following_sibling;
+
+				break;
+
+			case 'n':
+				if (name == PUGIXML_TEXT("namespace"))
+					return axis_namespace;
+
+				break;
+
+			case 'p':
+				if (name == PUGIXML_TEXT("parent"))
+					return axis_parent;
+				else if (name == PUGIXML_TEXT("preceding"))
+					return axis_preceding;
+				else if (name == PUGIXML_TEXT("preceding-sibling"))
+					return axis_preceding_sibling;
+
+				break;
+
+			case 's':
+				if (name == PUGIXML_TEXT("self"))
+					return axis_self;
+
+				break;
+
+			default:
+				break;
+			}
+
+			specified = false;
+			return axis_child;
+		}
+
+		nodetest_t parse_node_test_type(const xpath_lexer_string& name)
+		{
+			switch (name.begin[0])
+			{
+			case 'c':
+				if (name == PUGIXML_TEXT("comment"))
+					return nodetest_type_comment;
+
+				break;
+
+			case 'n':
+				if (name == PUGIXML_TEXT("node"))
+					return nodetest_type_node;
+
+				break;
+
+			case 'p':
+				if (name == PUGIXML_TEXT("processing-instruction"))
+					return nodetest_type_pi;
+
+				break;
+
+			case 't':
+				if (name == PUGIXML_TEXT("text"))
+					return nodetest_type_text;
+
+				break;
+
+			default:
+				break;
+			}
+
+			return nodetest_none;
+		}
+
+		// PrimaryExpr ::= VariableReference | '(' Expr ')' | Literal | Number | FunctionCall
+		xpath_ast_node* parse_primary_expression()
+		{
+			switch (_lexer.current())
+			{
+			case lex_var_ref:
+			{
+				xpath_lexer_string name = _lexer.contents();
+
+				if (!_variables)
+					throw_error("Unknown variable: variable set is not provided");
+
+				xpath_variable* var = 0;
+				if (!get_variable_scratch(_scratch, _variables, name.begin, name.end, &var))
+					throw_error_oom();
+
+				if (!var)
+					throw_error("Unknown variable: variable set does not contain the given name");
+
+				_lexer.next();
+
+				return new (alloc_node()) xpath_ast_node(ast_variable, var->type(), var);
+			}
+
+			case lex_open_brace:
+			{
+				_lexer.next();
+
+				xpath_ast_node* n = parse_expression();
+
+				if (_lexer.current() != lex_close_brace)
+					throw_error("Unmatched braces");
+
+				_lexer.next();
+
+				return n;
+			}
+
+			case lex_quoted_string:
+			{
+				const char_t* value = alloc_string(_lexer.contents());
+
+				xpath_ast_node* n = new (alloc_node()) xpath_ast_node(ast_string_constant, xpath_type_string, value);
+				_lexer.next();
+
+				return n;
+			}
+
+			case lex_number:
+			{
+				double value = 0;
+
+				if (!convert_string_to_number_scratch(_scratch, _lexer.contents().begin, _lexer.contents().end, &value))
+					throw_error_oom();
+
+				xpath_ast_node* n = new (alloc_node()) xpath_ast_node(ast_number_constant, xpath_type_number, value);
+				_lexer.next();
+
+				return n;
+			}
+
+			case lex_string:
+			{
+				xpath_ast_node* args[2] = {0};
+				size_t argc = 0;
+
+				xpath_lexer_string function = _lexer.contents();
+				_lexer.next();
+
+				xpath_ast_node* last_arg = 0;
+
+				if (_lexer.current() != lex_open_brace)
+					throw_error("Unrecognized function call");
+				_lexer.next();
+
+				if (_lexer.current() != lex_close_brace)
+					args[argc++] = parse_expression();
+
+				while (_lexer.current() != lex_close_brace)
+				{
+					if (_lexer.current() != lex_comma)
+						throw_error("No comma between function arguments");
+					_lexer.next();
+
+					xpath_ast_node* n = parse_expression();
+
+					if (argc < 2) args[argc] = n;
+					else last_arg->set_next(n);
+
+					argc++;
+					last_arg = n;
+				}
+
+				_lexer.next();
+
+				return parse_function(function, argc, args);
+			}
+
+			default:
+				throw_error("Unrecognizable primary expression");
+
+				return 0;
+			}
+		}
+
+		// FilterExpr ::= PrimaryExpr | FilterExpr Predicate
+		// Predicate ::= '[' PredicateExpr ']'
+		// PredicateExpr ::= Expr
+		xpath_ast_node* parse_filter_expression()
+		{
+			xpath_ast_node* n = parse_primary_expression();
+
+			while (_lexer.current() == lex_open_square_brace)
+			{
+				_lexer.next();
+
+				xpath_ast_node* expr = parse_expression();
+
+				if (n->rettype() != xpath_type_node_set)
+					throw_error("Predicate has to be applied to node set");
+
+				n = new (alloc_node()) xpath_ast_node(ast_filter, n, expr, predicate_default);
+
+				if (_lexer.current() != lex_close_square_brace)
+					throw_error("Unmatched square brace");
+
+				_lexer.next();
+			}
+
+			return n;
+		}
+
+		// Step ::= AxisSpecifier NodeTest Predicate* | AbbreviatedStep
+		// AxisSpecifier ::= AxisName '::' | '@'?
+		// NodeTest ::= NameTest | NodeType '(' ')' | 'processing-instruction' '(' Literal ')'
+		// NameTest ::= '*' | NCName ':' '*' | QName
+		// AbbreviatedStep ::= '.' | '..'
+		xpath_ast_node* parse_step(xpath_ast_node* set)
+		{
+			if (set && set->rettype() != xpath_type_node_set)
+				throw_error("Step has to be applied to node set");
+
+			bool axis_specified = false;
+			axis_t axis = axis_child; // implied child axis
+
+			if (_lexer.current() == lex_axis_attribute)
+			{
+				axis = axis_attribute;
+				axis_specified = true;
+
+				_lexer.next();
+			}
+			else if (_lexer.current() == lex_dot)
+			{
+				_lexer.next();
+
+				return new (alloc_node()) xpath_ast_node(ast_step, set, axis_self, nodetest_type_node, 0);
+			}
+			else if (_lexer.current() == lex_double_dot)
+			{
+				_lexer.next();
+
+				return new (alloc_node()) xpath_ast_node(ast_step, set, axis_parent, nodetest_type_node, 0);
+			}
+
+			nodetest_t nt_type = nodetest_none;
+			xpath_lexer_string nt_name;
+
+			if (_lexer.current() == lex_string)
+			{
+				// node name test
+				nt_name = _lexer.contents();
+				_lexer.next();
+
+				// was it an axis name?
+				if (_lexer.current() == lex_double_colon)
+				{
+					// parse axis name
+					if (axis_specified)
+						throw_error("Two axis specifiers in one step");
+
+					axis = parse_axis_name(nt_name, axis_specified);
+
+					if (!axis_specified)
+						throw_error("Unknown axis");
+
+					// read actual node test
+					_lexer.next();
+
+					if (_lexer.current() == lex_multiply)
+					{
+						nt_type = nodetest_all;
+						nt_name = xpath_lexer_string();
+						_lexer.next();
+					}
+					else if (_lexer.current() == lex_string)
+					{
+						nt_name = _lexer.contents();
+						_lexer.next();
+					}
+					else throw_error("Unrecognized node test");
+				}
+
+				if (nt_type == nodetest_none)
+				{
+					// node type test or processing-instruction
+					if (_lexer.current() == lex_open_brace)
+					{
+						_lexer.next();
+
+						if (_lexer.current() == lex_close_brace)
+						{
+							_lexer.next();
+
+							nt_type = parse_node_test_type(nt_name);
+
+							if (nt_type == nodetest_none)
+								throw_error("Unrecognized node type");
+
+							nt_name = xpath_lexer_string();
+						}
+						else if (nt_name == PUGIXML_TEXT("processing-instruction"))
+						{
+							if (_lexer.current() != lex_quoted_string)
+								throw_error("Only literals are allowed as arguments to processing-instruction()");
+
+							nt_type = nodetest_pi;
+							nt_name = _lexer.contents();
+							_lexer.next();
+
+							if (_lexer.current() != lex_close_brace)
+								throw_error("Unmatched brace near processing-instruction()");
+							_lexer.next();
+						}
+						else
+						{
+							throw_error("Unmatched brace near node type test");
+						}
+					}
+					// QName or NCName:*
+					else
+					{
+						if (nt_name.end - nt_name.begin > 2 && nt_name.end[-2] == ':' && nt_name.end[-1] == '*') // NCName:*
+						{
+							nt_name.end--; // erase *
+
+							nt_type = nodetest_all_in_namespace;
+						}
+						else
+						{
+							nt_type = nodetest_name;
+						}
+					}
+				}
+			}
+			else if (_lexer.current() == lex_multiply)
+			{
+				nt_type = nodetest_all;
+				_lexer.next();
+			}
+			else
+			{
+				throw_error("Unrecognized node test");
+			}
+
+			const char_t* nt_name_copy = alloc_string(nt_name);
+			xpath_ast_node* n = new (alloc_node()) xpath_ast_node(ast_step, set, axis, nt_type, nt_name_copy);
+
+			xpath_ast_node* last = 0;
+
+			while (_lexer.current() == lex_open_square_brace)
+			{
+				_lexer.next();
+
+				xpath_ast_node* expr = parse_expression();
+
+				xpath_ast_node* pred = new (alloc_node()) xpath_ast_node(ast_predicate, 0, expr, predicate_default);
+
+				if (_lexer.current() != lex_close_square_brace)
+					throw_error("Unmatched square brace");
+				_lexer.next();
+
+				if (last) last->set_next(pred);
+				else n->set_right(pred);
+
+				last = pred;
+			}
+
+			return n;
+		}
+
+		// RelativeLocationPath ::= Step | RelativeLocationPath '/' Step | RelativeLocationPath '//' Step
+		xpath_ast_node* parse_relative_location_path(xpath_ast_node* set)
+		{
+			xpath_ast_node* n = parse_step(set);
+
+			while (_lexer.current() == lex_slash || _lexer.current() == lex_double_slash)
+			{
+				lexeme_t l = _lexer.current();
+				_lexer.next();
+
+				if (l == lex_double_slash)
+					n = new (alloc_node()) xpath_ast_node(ast_step, n, axis_descendant_or_self, nodetest_type_node, 0);
+
+				n = parse_step(n);
+			}
+
+			return n;
+		}
+
+		// LocationPath ::= RelativeLocationPath | AbsoluteLocationPath
+		// AbsoluteLocationPath ::= '/' RelativeLocationPath? | '//' RelativeLocationPath
+		xpath_ast_node* parse_location_path()
+		{
+			if (_lexer.current() == lex_slash)
+			{
+				_lexer.next();
+
+				xpath_ast_node* n = new (alloc_node()) xpath_ast_node(ast_step_root, xpath_type_node_set);
+
+				// relative location path can start from axis_attribute, dot, double_dot, multiply and string lexemes; any other lexeme means standalone root path
+				lexeme_t l = _lexer.current();
+
+				if (l == lex_string || l == lex_axis_attribute || l == lex_dot || l == lex_double_dot || l == lex_multiply)
+					return parse_relative_location_path(n);
+				else
+					return n;
+			}
+			else if (_lexer.current() == lex_double_slash)
+			{
+				_lexer.next();
+
+				xpath_ast_node* n = new (alloc_node()) xpath_ast_node(ast_step_root, xpath_type_node_set);
+				n = new (alloc_node()) xpath_ast_node(ast_step, n, axis_descendant_or_self, nodetest_type_node, 0);
+
+				return parse_relative_location_path(n);
+			}
+
+			// else clause moved outside of if because of bogus warning 'control may reach end of non-void function being inlined' in gcc 4.0.1
+			return parse_relative_location_path(0);
+		}
+
+		// PathExpr ::= LocationPath
+		//				| FilterExpr
+		//				| FilterExpr '/' RelativeLocationPath
+		//				| FilterExpr '//' RelativeLocationPath
+		// UnionExpr ::= PathExpr | UnionExpr '|' PathExpr
+		// UnaryExpr ::= UnionExpr | '-' UnaryExpr
+		xpath_ast_node* parse_path_or_unary_expression()
+		{
+			// Clarification.
+			// PathExpr begins with either LocationPath or FilterExpr.
+			// FilterExpr begins with PrimaryExpr
+			// PrimaryExpr begins with '$' in case of it being a variable reference,
+			// '(' in case of it being an expression, string literal, number constant or
+			// function call.
+
+			if (_lexer.current() == lex_var_ref || _lexer.current() == lex_open_brace ||
+				_lexer.current() == lex_quoted_string || _lexer.current() == lex_number ||
+				_lexer.current() == lex_string)
+			{
+				if (_lexer.current() == lex_string)
+				{
+					// This is either a function call, or not - if not, we shall proceed with location path
+					const char_t* state = _lexer.state();
+
+					while (PUGI__IS_CHARTYPE(*state, ct_space)) ++state;
+
+					if (*state != '(') return parse_location_path();
+
+					// This looks like a function call; however this still can be a node-test. Check it.
+					if (parse_node_test_type(_lexer.contents()) != nodetest_none)
+						return parse_location_path();
+				}
+
+				xpath_ast_node* n = parse_filter_expression();
+
+				if (_lexer.current() == lex_slash || _lexer.current() == lex_double_slash)
+				{
+					lexeme_t l = _lexer.current();
+					_lexer.next();
+
+					if (l == lex_double_slash)
+					{
+						if (n->rettype() != xpath_type_node_set)
+							throw_error("Step has to be applied to node set");
+
+						n = new (alloc_node()) xpath_ast_node(ast_step, n, axis_descendant_or_self, nodetest_type_node, 0);
+					}
+
+					// select from location path
+					return parse_relative_location_path(n);
+				}
+
+				return n;
+			}
+			else if (_lexer.current() == lex_minus)
+			{
+				_lexer.next();
+
+				// precedence 7+ - only parses union expressions
+				xpath_ast_node* expr = parse_expression_rec(parse_path_or_unary_expression(), 7);
+
+				return new (alloc_node()) xpath_ast_node(ast_op_negate, xpath_type_number, expr);
+			}
+			else
+			{
+				return parse_location_path();
+			}
+		}
+
+		struct binary_op_t
+		{
+			ast_type_t asttype;
+			xpath_value_type rettype;
+			int precedence;
+
+			binary_op_t(): asttype(ast_unknown), rettype(xpath_type_none), precedence(0)
+			{
+			}
+
+			binary_op_t(ast_type_t asttype_, xpath_value_type rettype_, int precedence_): asttype(asttype_), rettype(rettype_), precedence(precedence_)
+			{
+			}
+
+			static binary_op_t parse(xpath_lexer& lexer)
+			{
+				switch (lexer.current())
+				{
+				case lex_string:
+					if (lexer.contents() == PUGIXML_TEXT("or"))
+						return binary_op_t(ast_op_or, xpath_type_boolean, 1);
+					else if (lexer.contents() == PUGIXML_TEXT("and"))
+						return binary_op_t(ast_op_and, xpath_type_boolean, 2);
+					else if (lexer.contents() == PUGIXML_TEXT("div"))
+						return binary_op_t(ast_op_divide, xpath_type_number, 6);
+					else if (lexer.contents() == PUGIXML_TEXT("mod"))
+						return binary_op_t(ast_op_mod, xpath_type_number, 6);
+					else
+						return binary_op_t();
+
+				case lex_equal:
+					return binary_op_t(ast_op_equal, xpath_type_boolean, 3);
+
+				case lex_not_equal:
+					return binary_op_t(ast_op_not_equal, xpath_type_boolean, 3);
+
+				case lex_less:
+					return binary_op_t(ast_op_less, xpath_type_boolean, 4);
+
+				case lex_greater:
+					return binary_op_t(ast_op_greater, xpath_type_boolean, 4);
+
+				case lex_less_or_equal:
+					return binary_op_t(ast_op_less_or_equal, xpath_type_boolean, 4);
+
+				case lex_greater_or_equal:
+					return binary_op_t(ast_op_greater_or_equal, xpath_type_boolean, 4);
+
+				case lex_plus:
+					return binary_op_t(ast_op_add, xpath_type_number, 5);
+
+				case lex_minus:
+					return binary_op_t(ast_op_subtract, xpath_type_number, 5);
+
+				case lex_multiply:
+					return binary_op_t(ast_op_multiply, xpath_type_number, 6);
+
+				case lex_union:
+					return binary_op_t(ast_op_union, xpath_type_node_set, 7);
+
+				default:
+					return binary_op_t();
+				}
+			}
+		};
+
+		xpath_ast_node* parse_expression_rec(xpath_ast_node* lhs, int limit)
+		{
+			binary_op_t op = binary_op_t::parse(_lexer);
+
+			while (op.asttype != ast_unknown && op.precedence >= limit)
+			{
+				_lexer.next();
+
+				xpath_ast_node* rhs = parse_path_or_unary_expression();
+
+				binary_op_t nextop = binary_op_t::parse(_lexer);
+
+				while (nextop.asttype != ast_unknown && nextop.precedence > op.precedence)
+				{
+					rhs = parse_expression_rec(rhs, nextop.precedence);
+
+					nextop = binary_op_t::parse(_lexer);
+				}
+
+				if (op.asttype == ast_op_union && (lhs->rettype() != xpath_type_node_set || rhs->rettype() != xpath_type_node_set))
+					throw_error("Union operator has to be applied to node sets");
+
+				lhs = new (alloc_node()) xpath_ast_node(op.asttype, op.rettype, lhs, rhs);
+
+				op = binary_op_t::parse(_lexer);
+			}
+
+			return lhs;
+		}
+
+		// Expr ::= OrExpr
+		// OrExpr ::= AndExpr | OrExpr 'or' AndExpr
+		// AndExpr ::= EqualityExpr | AndExpr 'and' EqualityExpr
+		// EqualityExpr ::= RelationalExpr
+		//					| EqualityExpr '=' RelationalExpr
+		//					| EqualityExpr '!=' RelationalExpr
+		// RelationalExpr ::= AdditiveExpr
+		//					  | RelationalExpr '<' AdditiveExpr
+		//					  | RelationalExpr '>' AdditiveExpr
+		//					  | RelationalExpr '<=' AdditiveExpr
+		//					  | RelationalExpr '>=' AdditiveExpr
+		// AdditiveExpr ::= MultiplicativeExpr
+		//					| AdditiveExpr '+' MultiplicativeExpr
+		//					| AdditiveExpr '-' MultiplicativeExpr
+		// MultiplicativeExpr ::= UnaryExpr
+		//						  | MultiplicativeExpr '*' UnaryExpr
+		//						  | MultiplicativeExpr 'div' UnaryExpr
+		//						  | MultiplicativeExpr 'mod' UnaryExpr
+		xpath_ast_node* parse_expression()
+		{
+			return parse_expression_rec(parse_path_or_unary_expression(), 0);
+		}
+
+		xpath_parser(const char_t* query, xpath_variable_set* variables, xpath_allocator* alloc, xpath_parse_result* result): _alloc(alloc), _lexer(query), _query(query), _variables(variables), _result(result)
+		{
+		}
+
+		xpath_ast_node* parse()
+		{
+			xpath_ast_node* result = parse_expression();
+
+			// check if there are unparsed tokens left
+			if (_lexer.current() != lex_eof)
+				throw_error("Incorrect query");
+
+			return result;
+		}
+
+		static xpath_ast_node* parse(const char_t* query, xpath_variable_set* variables, xpath_allocator* alloc, xpath_parse_result* result)
+		{
+			xpath_parser parser(query, variables, alloc, result);
+
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			int error = setjmp(parser._error_handler);
+
+			return (error == 0) ? parser.parse() : 0;
+		#else
+			return parser.parse();
+		#endif
+		}
+	};
+
+	struct xpath_query_impl
+	{
+		static xpath_query_impl* create()
+		{
+			void* memory = xml_memory::allocate(sizeof(xpath_query_impl));
+			if (!memory) return 0;
+
+			return new (memory) xpath_query_impl();
+		}
+
+		static void destroy(xpath_query_impl* impl)
+		{
+			// free all allocated pages
+			impl->alloc.release();
+
+			// free allocator memory (with the first page)
+			xml_memory::deallocate(impl);
+		}
+
+		xpath_query_impl(): root(0), alloc(&block)
+		{
+			block.next = 0;
+			block.capacity = sizeof(block.data);
+		}
+
+		xpath_ast_node* root;
+		xpath_allocator alloc;
+		xpath_memory_block block;
+	};
+
+	PUGI__FN xpath_string evaluate_string_impl(xpath_query_impl* impl, const xpath_node& n, xpath_stack_data& sd)
+	{
+		if (!impl) return xpath_string();
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		if (setjmp(sd.error_handler)) return xpath_string();
+	#endif
+
+		xpath_context c(n, 1, 1);
+
+		return impl->root->eval_string(c, sd.stack);
+	}
+
+	PUGI__FN impl::xpath_ast_node* evaluate_node_set_prepare(xpath_query_impl* impl)
+	{
+		if (!impl) return 0;
+
+		if (impl->root->rettype() != xpath_type_node_set)
+		{
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			return 0;
+		#else
+			xpath_parse_result res;
+			res.error = "Expression does not evaluate to node set";
+
+			throw xpath_exception(res);
+		#endif
+		}
+
+		return impl->root;
+	}
+PUGI__NS_END
+
+namespace pugi
+{
+#ifndef PUGIXML_NO_EXCEPTIONS
+	PUGI__FN xpath_exception::xpath_exception(const xpath_parse_result& result_): _result(result_)
+	{
+		assert(_result.error);
+	}
+
+	PUGI__FN const char* xpath_exception::what() const throw()
+	{
+		return _result.error;
+	}
+
+	PUGI__FN const xpath_parse_result& xpath_exception::result() const
+	{
+		return _result;
+	}
+#endif
+
+	PUGI__FN xpath_node::xpath_node()
+	{
+	}
+
+	PUGI__FN xpath_node::xpath_node(const xml_node& node_): _node(node_)
+	{
+	}
+
+	PUGI__FN xpath_node::xpath_node(const xml_attribute& attribute_, const xml_node& parent_): _node(attribute_ ? parent_ : xml_node()), _attribute(attribute_)
+	{
+	}
+
+	PUGI__FN xml_node xpath_node::node() const
+	{
+		return _attribute ? xml_node() : _node;
+	}
+
+	PUGI__FN xml_attribute xpath_node::attribute() const
+	{
+		return _attribute;
+	}
+
+	PUGI__FN xml_node xpath_node::parent() const
+	{
+		return _attribute ? _node : _node.parent();
+	}
+
+	PUGI__FN static void unspecified_bool_xpath_node(xpath_node***)
+	{
+	}
+
+	PUGI__FN xpath_node::operator xpath_node::unspecified_bool_type() const
+	{
+		return (_node || _attribute) ? unspecified_bool_xpath_node : 0;
+	}
+
+	PUGI__FN bool xpath_node::operator!() const
+	{
+		return !(_node || _attribute);
+	}
+
+	PUGI__FN bool xpath_node::operator==(const xpath_node& n) const
+	{
+		return _node == n._node && _attribute == n._attribute;
+	}
+
+	PUGI__FN bool xpath_node::operator!=(const xpath_node& n) const
+	{
+		return _node != n._node || _attribute != n._attribute;
+	}
+
+#ifdef __BORLANDC__
+	PUGI__FN bool operator&&(const xpath_node& lhs, bool rhs)
+	{
+		return (bool)lhs && rhs;
+	}
+
+	PUGI__FN bool operator||(const xpath_node& lhs, bool rhs)
+	{
+		return (bool)lhs || rhs;
+	}
+#endif
+
+	PUGI__FN void xpath_node_set::_assign(const_iterator begin_, const_iterator end_, type_t type_)
+	{
+		assert(begin_ <= end_);
+
+		size_t size_ = static_cast<size_t>(end_ - begin_);
+
+		if (size_ <= 1)
+		{
+			// deallocate old buffer
+			if (_begin != &_storage) impl::xml_memory::deallocate(_begin);
+
+			// use internal buffer
+			if (begin_ != end_) _storage = *begin_;
+
+			_begin = &_storage;
+			_end = &_storage + size_;
+			_type = type_;
+		}
+		else
+		{
+			// make heap copy
+			xpath_node* storage = static_cast<xpath_node*>(impl::xml_memory::allocate(size_ * sizeof(xpath_node)));
+
+			if (!storage)
+			{
+			#ifdef PUGIXML_NO_EXCEPTIONS
+				return;
+			#else
+				throw std::bad_alloc();
+			#endif
+			}
+
+			memcpy(storage, begin_, size_ * sizeof(xpath_node));
+
+			// deallocate old buffer
+			if (_begin != &_storage) impl::xml_memory::deallocate(_begin);
+
+			// finalize
+			_begin = storage;
+			_end = storage + size_;
+			_type = type_;
+		}
+	}
+
+#ifdef PUGIXML_HAS_MOVE
+	PUGI__FN void xpath_node_set::_move(xpath_node_set& rhs)
+	{
+		_type = rhs._type;
+		_storage = rhs._storage;
+		_begin = (rhs._begin == &rhs._storage) ? &_storage : rhs._begin;
+		_end = _begin + (rhs._end - rhs._begin);
+
+		rhs._type = type_unsorted;
+		rhs._begin = &rhs._storage;
+		rhs._end = rhs._begin;
+	}
+#endif
+
+	PUGI__FN xpath_node_set::xpath_node_set(): _type(type_unsorted), _begin(&_storage), _end(&_storage)
+	{
+	}
+
+	PUGI__FN xpath_node_set::xpath_node_set(const_iterator begin_, const_iterator end_, type_t type_): _type(type_unsorted), _begin(&_storage), _end(&_storage)
+	{
+		_assign(begin_, end_, type_);
+	}
+
+	PUGI__FN xpath_node_set::~xpath_node_set()
+	{
+		if (_begin != &_storage)
+			impl::xml_memory::deallocate(_begin);
+	}
+
+	PUGI__FN xpath_node_set::xpath_node_set(const xpath_node_set& ns): _type(type_unsorted), _begin(&_storage), _end(&_storage)
+	{
+		_assign(ns._begin, ns._end, ns._type);
+	}
+
+	PUGI__FN xpath_node_set& xpath_node_set::operator=(const xpath_node_set& ns)
+	{
+		if (this == &ns) return *this;
+
+		_assign(ns._begin, ns._end, ns._type);
+
+		return *this;
+	}
+
+#ifdef PUGIXML_HAS_MOVE
+	PUGI__FN xpath_node_set::xpath_node_set(xpath_node_set&& rhs): _type(type_unsorted), _begin(&_storage), _end(&_storage)
+	{
+		_move(rhs);
+	}
+
+	PUGI__FN xpath_node_set& xpath_node_set::operator=(xpath_node_set&& rhs)
+	{
+		if (this == &rhs) return *this;
+
+		if (_begin != &_storage)
+			impl::xml_memory::deallocate(_begin);
+
+		_move(rhs);
+
+		return *this;
+	}
+#endif
+
+	PUGI__FN xpath_node_set::type_t xpath_node_set::type() const
+	{
+		return _type;
+	}
+
+	PUGI__FN size_t xpath_node_set::size() const
+	{
+		return _end - _begin;
+	}
+
+	PUGI__FN bool xpath_node_set::empty() const
+	{
+		return _begin == _end;
+	}
+
+	PUGI__FN const xpath_node& xpath_node_set::operator[](size_t index) const
+	{
+		assert(index < size());
+		return _begin[index];
+	}
+
+	PUGI__FN xpath_node_set::const_iterator xpath_node_set::begin() const
+	{
+		return _begin;
+	}
+
+	PUGI__FN xpath_node_set::const_iterator xpath_node_set::end() const
+	{
+		return _end;
+	}
+
+	PUGI__FN void xpath_node_set::sort(bool reverse)
+	{
+		_type = impl::xpath_sort(_begin, _end, _type, reverse);
+	}
+
+	PUGI__FN xpath_node xpath_node_set::first() const
+	{
+		return impl::xpath_first(_begin, _end, _type);
+	}
+
+	PUGI__FN xpath_parse_result::xpath_parse_result(): error("Internal error"), offset(0)
+	{
+	}
+
+	PUGI__FN xpath_parse_result::operator bool() const
+	{
+		return error == 0;
+	}
+
+	PUGI__FN const char* xpath_parse_result::description() const
+	{
+		return error ? error : "No error";
+	}
+
+	PUGI__FN xpath_variable::xpath_variable(xpath_value_type type_): _type(type_), _next(0)
+	{
+	}
+
+	PUGI__FN const char_t* xpath_variable::name() const
+	{
+		switch (_type)
+		{
+		case xpath_type_node_set:
+			return static_cast<const impl::xpath_variable_node_set*>(this)->name;
+
+		case xpath_type_number:
+			return static_cast<const impl::xpath_variable_number*>(this)->name;
+
+		case xpath_type_string:
+			return static_cast<const impl::xpath_variable_string*>(this)->name;
+
+		case xpath_type_boolean:
+			return static_cast<const impl::xpath_variable_boolean*>(this)->name;
+
+		default:
+			assert(false && "Invalid variable type");
+			return 0;
+		}
+	}
+
+	PUGI__FN xpath_value_type xpath_variable::type() const
+	{
+		return _type;
+	}
+
+	PUGI__FN bool xpath_variable::get_boolean() const
+	{
+		return (_type == xpath_type_boolean) ? static_cast<const impl::xpath_variable_boolean*>(this)->value : false;
+	}
+
+	PUGI__FN double xpath_variable::get_number() const
+	{
+		return (_type == xpath_type_number) ? static_cast<const impl::xpath_variable_number*>(this)->value : impl::gen_nan();
+	}
+
+	PUGI__FN const char_t* xpath_variable::get_string() const
+	{
+		const char_t* value = (_type == xpath_type_string) ? static_cast<const impl::xpath_variable_string*>(this)->value : 0;
+		return value ? value : PUGIXML_TEXT("");
+	}
+
+	PUGI__FN const xpath_node_set& xpath_variable::get_node_set() const
+	{
+		return (_type == xpath_type_node_set) ? static_cast<const impl::xpath_variable_node_set*>(this)->value : impl::dummy_node_set;
+	}
+
+	PUGI__FN bool xpath_variable::set(bool value)
+	{
+		if (_type != xpath_type_boolean) return false;
+
+		static_cast<impl::xpath_variable_boolean*>(this)->value = value;
+		return true;
+	}
+
+	PUGI__FN bool xpath_variable::set(double value)
+	{
+		if (_type != xpath_type_number) return false;
+
+		static_cast<impl::xpath_variable_number*>(this)->value = value;
+		return true;
+	}
+
+	PUGI__FN bool xpath_variable::set(const char_t* value)
+	{
+		if (_type != xpath_type_string) return false;
+
+		impl::xpath_variable_string* var = static_cast<impl::xpath_variable_string*>(this);
+
+		// duplicate string
+		size_t size = (impl::strlength(value) + 1) * sizeof(char_t);
+
+		char_t* copy = static_cast<char_t*>(impl::xml_memory::allocate(size));
+		if (!copy) return false;
+
+		memcpy(copy, value, size);
+
+		// replace old string
+		if (var->value) impl::xml_memory::deallocate(var->value);
+		var->value = copy;
+
+		return true;
+	}
+
+	PUGI__FN bool xpath_variable::set(const xpath_node_set& value)
+	{
+		if (_type != xpath_type_node_set) return false;
+
+		static_cast<impl::xpath_variable_node_set*>(this)->value = value;
+		return true;
+	}
+
+	PUGI__FN xpath_variable_set::xpath_variable_set()
+	{
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+			_data[i] = 0;
+	}
+
+	PUGI__FN xpath_variable_set::~xpath_variable_set()
+	{
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+			_destroy(_data[i]);
+	}
+
+	PUGI__FN xpath_variable_set::xpath_variable_set(const xpath_variable_set& rhs)
+	{
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+			_data[i] = 0;
+
+		_assign(rhs);
+	}
+
+	PUGI__FN xpath_variable_set& xpath_variable_set::operator=(const xpath_variable_set& rhs)
+	{
+		if (this == &rhs) return *this;
+
+		_assign(rhs);
+
+		return *this;
+	}
+
+#ifdef PUGIXML_HAS_MOVE
+	PUGI__FN xpath_variable_set::xpath_variable_set(xpath_variable_set&& rhs)
+	{
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+		{
+			_data[i] = rhs._data[i];
+			rhs._data[i] = 0;
+		}
+	}
+
+	PUGI__FN xpath_variable_set& xpath_variable_set::operator=(xpath_variable_set&& rhs)
+	{
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+		{
+			_destroy(_data[i]);
+
+			_data[i] = rhs._data[i];
+			rhs._data[i] = 0;
+		}
+
+		return *this;
+	}
+#endif
+
+	PUGI__FN void xpath_variable_set::_assign(const xpath_variable_set& rhs)
+	{
+		xpath_variable_set temp;
+
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+			if (rhs._data[i] && !_clone(rhs._data[i], &temp._data[i]))
+				return;
+
+		_swap(temp);
+	}
+
+	PUGI__FN void xpath_variable_set::_swap(xpath_variable_set& rhs)
+	{
+		for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i)
+		{
+			xpath_variable* chain = _data[i];
+
+			_data[i] = rhs._data[i];
+			rhs._data[i] = chain;
+		}
+	}
+
+	PUGI__FN xpath_variable* xpath_variable_set::_find(const char_t* name) const
+	{
+		const size_t hash_size = sizeof(_data) / sizeof(_data[0]);
+		size_t hash = impl::hash_string(name) % hash_size;
+
+		// look for existing variable
+		for (xpath_variable* var = _data[hash]; var; var = var->_next)
+			if (impl::strequal(var->name(), name))
+				return var;
+
+		return 0;
+	}
+
+	PUGI__FN bool xpath_variable_set::_clone(xpath_variable* var, xpath_variable** out_result)
+	{
+		xpath_variable* last = 0;
+
+		while (var)
+		{
+			// allocate storage for new variable
+			xpath_variable* nvar = impl::new_xpath_variable(var->_type, var->name());
+			if (!nvar) return false;
+
+			// link the variable to the result immediately to handle failures gracefully
+			if (last)
+				last->_next = nvar;
+			else
+				*out_result = nvar;
+
+			last = nvar;
+
+			// copy the value; this can fail due to out-of-memory conditions
+			if (!impl::copy_xpath_variable(nvar, var)) return false;
+
+			var = var->_next;
+		}
+
+		return true;
+	}
+
+	PUGI__FN void xpath_variable_set::_destroy(xpath_variable* var)
+	{
+		while (var)
+		{
+			xpath_variable* next = var->_next;
+
+			impl::delete_xpath_variable(var->_type, var);
+
+			var = next;
+		}
+	}
+
+	PUGI__FN xpath_variable* xpath_variable_set::add(const char_t* name, xpath_value_type type)
+	{
+		const size_t hash_size = sizeof(_data) / sizeof(_data[0]);
+		size_t hash = impl::hash_string(name) % hash_size;
+
+		// look for existing variable
+		for (xpath_variable* var = _data[hash]; var; var = var->_next)
+			if (impl::strequal(var->name(), name))
+				return var->type() == type ? var : 0;
+
+		// add new variable
+		xpath_variable* result = impl::new_xpath_variable(type, name);
+
+		if (result)
+		{
+			result->_next = _data[hash];
+
+			_data[hash] = result;
+		}
+
+		return result;
+	}
+
+	PUGI__FN bool xpath_variable_set::set(const char_t* name, bool value)
+	{
+		xpath_variable* var = add(name, xpath_type_boolean);
+		return var ? var->set(value) : false;
+	}
+
+	PUGI__FN bool xpath_variable_set::set(const char_t* name, double value)
+	{
+		xpath_variable* var = add(name, xpath_type_number);
+		return var ? var->set(value) : false;
+	}
+
+	PUGI__FN bool xpath_variable_set::set(const char_t* name, const char_t* value)
+	{
+		xpath_variable* var = add(name, xpath_type_string);
+		return var ? var->set(value) : false;
+	}
+
+	PUGI__FN bool xpath_variable_set::set(const char_t* name, const xpath_node_set& value)
+	{
+		xpath_variable* var = add(name, xpath_type_node_set);
+		return var ? var->set(value) : false;
+	}
+
+	PUGI__FN xpath_variable* xpath_variable_set::get(const char_t* name)
+	{
+		return _find(name);
+	}
+
+	PUGI__FN const xpath_variable* xpath_variable_set::get(const char_t* name) const
+	{
+		return _find(name);
+	}
+
+	PUGI__FN xpath_query::xpath_query(const char_t* query, xpath_variable_set* variables): _impl(0)
+	{
+		impl::xpath_query_impl* qimpl = impl::xpath_query_impl::create();
+
+		if (!qimpl)
+		{
+		#ifdef PUGIXML_NO_EXCEPTIONS
+			_result.error = "Out of memory";
+		#else
+			throw std::bad_alloc();
+		#endif
+		}
+		else
+		{
+			using impl::auto_deleter; // MSVC7 workaround
+			auto_deleter<impl::xpath_query_impl> impl(qimpl, impl::xpath_query_impl::destroy);
+
+			qimpl->root = impl::xpath_parser::parse(query, variables, &qimpl->alloc, &_result);
+
+			if (qimpl->root)
+			{
+				qimpl->root->optimize(&qimpl->alloc);
+
+				_impl = impl.release();
+				_result.error = 0;
+			}
+		}
+	}
+
+	PUGI__FN xpath_query::xpath_query(): _impl(0)
+	{
+	}
+
+	PUGI__FN xpath_query::~xpath_query()
+	{
+		if (_impl)
+			impl::xpath_query_impl::destroy(static_cast<impl::xpath_query_impl*>(_impl));
+	}
+
+#ifdef PUGIXML_HAS_MOVE
+	PUGI__FN xpath_query::xpath_query(xpath_query&& rhs)
+	{
+		_impl = rhs._impl;
+		_result = rhs._result;
+		rhs._impl = 0;
+		rhs._result = xpath_parse_result();
+	}
+
+	PUGI__FN xpath_query& xpath_query::operator=(xpath_query&& rhs)
+	{
+		if (this == &rhs) return *this;
+
+		if (_impl)
+			impl::xpath_query_impl::destroy(static_cast<impl::xpath_query_impl*>(_impl));
+
+		_impl = rhs._impl;
+		_result = rhs._result;
+		rhs._impl = 0;
+		rhs._result = xpath_parse_result();
+
+		return *this;
+	}
+#endif
+
+	PUGI__FN xpath_value_type xpath_query::return_type() const
+	{
+		if (!_impl) return xpath_type_none;
+
+		return static_cast<impl::xpath_query_impl*>(_impl)->root->rettype();
+	}
+
+	PUGI__FN bool xpath_query::evaluate_boolean(const xpath_node& n) const
+	{
+		if (!_impl) return false;
+
+		impl::xpath_context c(n, 1, 1);
+		impl::xpath_stack_data sd;
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		if (setjmp(sd.error_handler)) return false;
+	#endif
+
+		return static_cast<impl::xpath_query_impl*>(_impl)->root->eval_boolean(c, sd.stack);
+	}
+
+	PUGI__FN double xpath_query::evaluate_number(const xpath_node& n) const
+	{
+		if (!_impl) return impl::gen_nan();
+
+		impl::xpath_context c(n, 1, 1);
+		impl::xpath_stack_data sd;
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		if (setjmp(sd.error_handler)) return impl::gen_nan();
+	#endif
+
+		return static_cast<impl::xpath_query_impl*>(_impl)->root->eval_number(c, sd.stack);
+	}
+
+#ifndef PUGIXML_NO_STL
+	PUGI__FN string_t xpath_query::evaluate_string(const xpath_node& n) const
+	{
+		impl::xpath_stack_data sd;
+
+		impl::xpath_string r = impl::evaluate_string_impl(static_cast<impl::xpath_query_impl*>(_impl), n, sd);
+
+		return string_t(r.c_str(), r.length());
+	}
+#endif
+
+	PUGI__FN size_t xpath_query::evaluate_string(char_t* buffer, size_t capacity, const xpath_node& n) const
+	{
+		impl::xpath_stack_data sd;
+
+		impl::xpath_string r = impl::evaluate_string_impl(static_cast<impl::xpath_query_impl*>(_impl), n, sd);
+
+		size_t full_size = r.length() + 1;
+
+		if (capacity > 0)
+		{
+			size_t size = (full_size < capacity) ? full_size : capacity;
+			assert(size > 0);
+
+			memcpy(buffer, r.c_str(), (size - 1) * sizeof(char_t));
+			buffer[size - 1] = 0;
+		}
+
+		return full_size;
+	}
+
+	PUGI__FN xpath_node_set xpath_query::evaluate_node_set(const xpath_node& n) const
+	{
+		impl::xpath_ast_node* root = impl::evaluate_node_set_prepare(static_cast<impl::xpath_query_impl*>(_impl));
+		if (!root) return xpath_node_set();
+
+		impl::xpath_context c(n, 1, 1);
+		impl::xpath_stack_data sd;
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		if (setjmp(sd.error_handler)) return xpath_node_set();
+	#endif
+
+		impl::xpath_node_set_raw r = root->eval_node_set(c, sd.stack, impl::nodeset_eval_all);
+
+		return xpath_node_set(r.begin(), r.end(), r.type());
+	}
+
+	PUGI__FN xpath_node xpath_query::evaluate_node(const xpath_node& n) const
+	{
+		impl::xpath_ast_node* root = impl::evaluate_node_set_prepare(static_cast<impl::xpath_query_impl*>(_impl));
+		if (!root) return xpath_node();
+
+		impl::xpath_context c(n, 1, 1);
+		impl::xpath_stack_data sd;
+
+	#ifdef PUGIXML_NO_EXCEPTIONS
+		if (setjmp(sd.error_handler)) return xpath_node();
+	#endif
+
+		impl::xpath_node_set_raw r = root->eval_node_set(c, sd.stack, impl::nodeset_eval_first);
+
+		return r.first();
+	}
+
+	PUGI__FN const xpath_parse_result& xpath_query::result() const
+	{
+		return _result;
+	}
+
+	PUGI__FN static void unspecified_bool_xpath_query(xpath_query***)
+	{
+	}
+
+	PUGI__FN xpath_query::operator xpath_query::unspecified_bool_type() const
+	{
+		return _impl ? unspecified_bool_xpath_query : 0;
+	}
+
+	PUGI__FN bool xpath_query::operator!() const
+	{
+		return !_impl;
+	}
+
+	PUGI__FN xpath_node xml_node::select_node(const char_t* query, xpath_variable_set* variables) const
+	{
+		xpath_query q(query, variables);
+		return select_node(q);
+	}
+
+	PUGI__FN xpath_node xml_node::select_node(const xpath_query& query) const
+	{
+		return query.evaluate_node(*this);
+	}
+
+	PUGI__FN xpath_node_set xml_node::select_nodes(const char_t* query, xpath_variable_set* variables) const
+	{
+		xpath_query q(query, variables);
+		return select_nodes(q);
+	}
+
+	PUGI__FN xpath_node_set xml_node::select_nodes(const xpath_query& query) const
+	{
+		return query.evaluate_node_set(*this);
+	}
+
+	PUGI__FN xpath_node xml_node::select_single_node(const char_t* query, xpath_variable_set* variables) const
+	{
+		xpath_query q(query, variables);
+		return select_single_node(q);
+	}
+
+	PUGI__FN xpath_node xml_node::select_single_node(const xpath_query& query) const
+	{
+		return query.evaluate_node(*this);
+	}
+}
+
+#endif
+
+#ifdef __BORLANDC__
+#	pragma option pop
+#endif
+
+// Intel C++ does not properly keep warning state for function templates,
+// so popping warning state at the end of translation unit leads to warnings in the middle.
+#if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
+#	pragma warning(pop)
+#endif
+
+// Undefine all local macros (makes sure we're not leaking macros in header-only mode)
+#undef PUGI__NO_INLINE
+#undef PUGI__UNLIKELY
+#undef PUGI__STATIC_ASSERT
+#undef PUGI__DMC_VOLATILE
+#undef PUGI__MSVC_CRT_VERSION
+#undef PUGI__NS_BEGIN
+#undef PUGI__NS_END
+#undef PUGI__FN
+#undef PUGI__FN_NO_INLINE
+#undef PUGI__GETHEADER_IMPL
+#undef PUGI__GETPAGE_IMPL
+#undef PUGI__GETPAGE
+#undef PUGI__NODETYPE
+#undef PUGI__IS_CHARTYPE_IMPL
+#undef PUGI__IS_CHARTYPE
+#undef PUGI__IS_CHARTYPEX
+#undef PUGI__ENDSWITH
+#undef PUGI__SKIPWS
+#undef PUGI__OPTSET
+#undef PUGI__PUSHNODE
+#undef PUGI__POPNODE
+#undef PUGI__SCANFOR
+#undef PUGI__SCANWHILE
+#undef PUGI__SCANWHILE_UNROLL
+#undef PUGI__ENDSEG
+#undef PUGI__THROW_ERROR
+#undef PUGI__CHECK_ERROR
+
+#endif
+
+/**
+ * Copyright (c) 2006-2016 Arseny Kapoulkine
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/Example-GPIO.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/Example-GPIO.cpp
new file mode 100644
index 000000000..2b0a69a60
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/Example-GPIO.cpp
@@ -0,0 +1,175 @@
+/******************************************************************************/
+/** 
+	Using Communications Hub for General Purpose Outputs, and Inputs
+
+	This example demonstrates setting the Brake Control mode to use a
+	communication hub Brake output for general purpose usages.  This example
+	also reads the local General purpose inputs at the Nodes.
+**/
+/******************************************************************************/
+
+#include <stdio.h>
+#include <string>
+#include <iostream>
+#include "pubSysCls.h"
+
+using namespace sFnd;
+using namespace std;
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+int main(int argc, char* argv[])
+{
+	msgUser("GPIO Example starting. Press Enter to continue.");
+	size_t portCount = 0;
+	std::vector<std::string> comHubPorts;
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{
+
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount > 0) {
+			//printf("\n I will now open port \t%i \n \n", portnum);
+			myMgr->PortsOpen(portCount);				//Open the port
+
+			for (size_t i = 0; i < portCount; i++) {
+				IPort &myPort = myMgr->Ports(i);
+
+				printf(" Port[%d]: state=%d, nodes=%d\n",
+					myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+			}
+		}
+		else {
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			return -1;  //This terminates the main program
+		}
+
+		//Once the code gets past this point, it can be assumed that the Port has been opened without issue
+		//Now we can get a reference to our port object which we will use to access the node objects
+
+		for (size_t iPort = 0; iPort < portCount; iPort++) {
+			// Get a reference to the port, to make accessing it easier
+			IPort &myPort = myMgr->Ports(iPort);
+
+
+
+			// Print out some information about the port
+			printf(" Port[%d]: state=%d, nodes=%d\n", myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+
+			// Set GPO to ON for the first brake control, 
+			myPort.BrakeControl.BrakeSetting(0, GPO_ON);
+			// Can set GPO to OFF for the second brake control using the method below
+			//myPort.BrakeControl.BrakeSetting(1, GPO_OFF);
+
+			for (size_t iBrake = 0; iBrake < 2; iBrake++) {
+				// Print out brake mode for the first brake
+				size_t controlMode = myPort.BrakeControl.BrakeSetting(iBrake);
+				printf("\nPort[%d] Brake %zi control mode: ", myPort.NetNumber(), iBrake);
+				switch (controlMode) {
+				case BRAKE_AUTOCONTROL:
+					printf("BRAKE_AUTOCONTROL");
+					break;
+				case BRAKE_PREVENT_MOTION:
+					printf("BRAKE_PREVENT_MOTION");
+					break;
+				case BRAKE_ALLOW_MOTION:
+					printf("BRAKE_ALLOW_MOTION");
+					break;
+				case GPO_ON:
+					printf("GPO_ON");
+					break;
+				case GPO_OFF:
+					printf("GPO_OFF");
+					break;
+				default:
+					printf("internal mode %zi", controlMode);
+				}
+
+				// keep the console output readable
+				printf("\n");
+			}
+
+			printf("\n");
+
+			for (unsigned iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+
+				INode &theNode = myPort.Nodes(iNode);
+
+				//Checking Inputs to each Node
+				if (theNode.Status.RT.Value().cpm.InA)
+				{
+					printf("Node %i Input A is asserted \n", iNode);
+				}
+				else
+				{
+					printf("Node %i Input A is not asserted \n", iNode);
+				}
+				if (theNode.Status.RT.Value().cpm.InB)
+				{
+					printf("Node %i Input B is asserted \n", iNode);
+				}
+				else
+				{
+					printf("Node %i Input B is not asserted\n", iNode);
+				}
+
+			}
+		}
+
+		printf("\nShutting down network\n");
+
+		// Close down the ports
+		myMgr->PortsClose();
+	
+
+	}
+	catch (mnErr& theErr) {
+		fprintf(stderr, "Caught error: addr=%d, err=0x%0x\nmsg=%s\n",
+				theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n",
+				theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+		// keep the console output readable
+		printf("\n");
+		return(2);
+	}
+	catch (...) {
+		fprintf(stderr, "Error generic caught\n");
+		printf("Generic error caught\n");
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+		// keep the console output readable
+		printf("\n");
+		return(3);
+	}
+
+	// Good-bye
+	msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+	// keep the console output readable
+	printf("\n");
+	return 0;
+}
+//																			   *
+//******************************************************************************
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/Example-GPIO.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/Example-GPIO.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/Example-GPIO.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/README.TXT
new file mode 100644
index 000000000..d2263d8c2
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-GPIO/README.TXT
@@ -0,0 +1,13 @@
+Example-GPIO
+======================
+
+This is an example for a network of ClearPath SC nodes connected to an SC-HUB. This program will assert the General purpose Brake output on the SC-HUB board, and discover all the nodes on the port. Finnally the program will record the current state of inputs A, and B on each node before shutting down.
+
+Requirements:
+
+-This program asserts the Brake output of the SC_HUB board, so an SC-HUB board is required.  Do not attempt to execute this program if using a custom communication hub.
+
+-Be aware that the Brake output 0 of the SC-HUB board will be temporarily asserted when this program is executed.
+
+
+Example-GPIO.cpp - This is the main function for the program. It holds a reference to the system manager of the network and Port objects. The main program then waits for the user to press a key in order to end the program.
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/Example-Homing.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/Example-Homing.cpp
new file mode 100644
index 000000000..5077161f4
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/Example-Homing.cpp
@@ -0,0 +1,174 @@
+//Required include files
+#include <stdio.h>	
+#include <string>
+#include <iostream>
+#include "pubSysCls.h"	
+
+using namespace sFnd;
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+//*********************************************************************************
+//This program will load configuration files onto each node connected to the port, then executes
+//sequential repeated moves on each axis.
+//*********************************************************************************
+
+#define CHANGE_NUMBER_SPACE	2000	//The change to the numberspace after homing (cnts)
+#define TIME_TILL_TIMEOUT	10000	//The timeout used for homing(ms)
+
+
+int main(int argc, char* argv[])
+{
+	msgUser("Homing Example starting. Press Enter to continue.");
+
+size_t portCount = 0;
+	std::vector<std::string> comHubPorts;
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{
+
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount > 0) {
+			//printf("\n I will now open port \t%i \n \n", portnum);
+			myMgr->PortsOpen(portCount);				//Open the port
+
+			for (size_t i = 0; i < portCount; i++) {
+				IPort &myPort = myMgr->Ports(i);
+
+				printf(" Port[%d]: state=%d, nodes=%d\n",
+					myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+			}
+		}
+		else {
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			return -1;  //This terminates the main program
+		}
+
+
+		//Once the code gets past this point, it can be assumed that the Port has been opened without issue
+		//Now we can get a reference to our port object which we will use to access the node 
+
+		for (size_t iPort = 0; iPort < portCount; iPort++) {
+			// Get a reference to the port, to make accessing it easier
+			IPort &myPort = myMgr->Ports(iPort);
+
+			for (unsigned iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+
+				//////////////////////////////////////////////////////////////////////////////////////////////////////////
+				//Here we identify the first Node, enable and home the node, then adjust the position reference
+				//////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+						// Create a shortcut reference for the first node
+				INode &theNode = myPort.Nodes(iNode);
+
+				//theNode.EnableReq(false);				//Ensure Node is disabled before starting
+
+				printf("   Node[%d]: type=%d\n", iNode, theNode.Info.NodeType());
+				printf("            userID: %s\n", theNode.Info.UserID.Value());
+				printf("        FW version: %s\n", theNode.Info.FirmwareVersion.Value());
+				printf("          Serial #: %d\n", theNode.Info.SerialNumber.Value());
+				printf("             Model: %s\n", theNode.Info.Model.Value());
+
+				//The following statements will attempt to enable the node.  First,
+				// any shutdowns or NodeStops are cleared, finally the node in enabled
+				theNode.Status.AlertsClear();					//Clear Alerts on node 
+				theNode.Motion.NodeStopClear();	//Clear Nodestops on Node  				
+				theNode.EnableReq(true);					//Enable node 
+
+				double timeout = myMgr->TimeStampMsec() + TIME_TILL_TIMEOUT;	//define a timeout in case the node is unable to enable
+																			//This will loop checking on the Real time values of the node's Ready status
+				while (!theNode.Motion.IsReady()) {
+					if (myMgr->TimeStampMsec() > timeout) {
+						printf("Error: Timed out waiting for Node %d to enable\n", iNode);
+						msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+						return -2;
+					}
+				}
+				//At this point the Node is enabled, and we will now check to see if the Node has been homed
+				//Check the Node to see if it has already been homed, 
+				if (theNode.Motion.Homing.HomingValid())
+				{
+					if (theNode.Motion.Homing.WasHomed())
+					{
+						printf("Node %d has already been homed, current position is: \t%8.0f \n", iNode, theNode.Motion.PosnMeasured.Value());
+						printf("Rehoming Node... \n");
+					}
+					else
+					{
+						printf("Node [%d] has not been homed.  Homing Node now...\n", iNode);
+					}
+					//Now we will home the Node
+						theNode.Motion.Homing.Initiate();
+
+						timeout = myMgr->TimeStampMsec() + TIME_TILL_TIMEOUT;	//define a timeout in case the node is unable to enable
+					   // Basic mode - Poll until disabled
+						while (!theNode.Motion.Homing.WasHomed()) {
+							if (myMgr->TimeStampMsec() > timeout) {
+								printf("Node did not complete homing:  \n\t -Ensure Homing settings have been defined through ClearView. \n\t -Check for alerts/Shutdowns \n\t -Ensure timeout is longer than the longest possible homing move.\n");
+								msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+								return -2;
+							}
+						}
+						theNode.Motion.PosnMeasured.Refresh();		//Refresh our current measured position
+						printf("Node completed homing, current position: \t%8.0f \n", theNode.Motion.PosnMeasured.Value());
+						printf("Soft limits now active\n");
+
+						printf("Adjusting Numberspace by %d\n", CHANGE_NUMBER_SPACE);
+
+						theNode.Motion.AddToPosition(CHANGE_NUMBER_SPACE);			//Now the node is no longer considered "homed, and soft limits are turned off
+
+						theNode.Motion.Homing.SignalComplete();		//reset the Node's "sense of home" soft limits (unchanged) are now active again
+
+						theNode.Motion.PosnMeasured.Refresh();		//Refresh our current measured position
+						printf("Numberspace changed, current position: \t%8.0f \n", theNode.Motion.PosnMeasured.Value());
+					}
+					else {
+						printf("Node[%d] has not had homing setup through ClearView.  The node will not be homed.\n", iNode);
+					}
+
+					printf("Disabling Node\n");
+					theNode.EnableReq(false);
+				}
+			}
+		}
+	catch (mnErr& theErr)
+	{
+		//This statement will print the address of the error, the error code (defined by the mnErr class), 
+		//as well as the corresponding error message.
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n", theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+		return 0;  //This terminates the main program
+	}
+		
+
+	// Close down the ports
+	myMgr->PortsClose();
+
+	msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+	return 0;			//End program
+}
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/Example-Homing.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/Example-Homing.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/Example-Homing.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/README.TXT
new file mode 100644
index 000000000..5faab1269
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Homing/README.TXT
@@ -0,0 +1,12 @@
+Example-Motion
+======================
+
+This is an example for a network of ClearPath SC nodes. This example will open all connected SC-Hub boards, and home each motor which has had homing defined through the ClearView setup software
+
+Requirements:
+
+-This program may execute motion on some or all nodes, nodes should be configured through the ClearView software.
+
+
+
+Example-Homing.cpp - This is the main function for the program. It holds a reference to the system manager of the network and Port and Node objects. 
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/Example-Motion.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/Example-Motion.cpp
new file mode 100644
index 000000000..0466e89c5
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/Example-Motion.cpp
@@ -0,0 +1,206 @@
+//Required include files
+#include <stdio.h>	
+#include <string>
+#include <iostream>
+#include "pubSysCls.h"	
+
+using namespace sFnd;
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+//*********************************************************************************
+//This program will load configuration files onto each node connected to the port, then executes
+//sequential repeated moves on each axis.
+//*********************************************************************************
+
+#define ACC_LIM_RPM_PER_SEC	100000
+#define VEL_LIM_RPM			700
+#define MOVE_DISTANCE_CNTS	10000	
+#define NUM_MOVES			5
+#define TIME_TILL_TIMEOUT	10000	//The timeout used for homing(ms)
+
+int main(int argc, char* argv[])
+{
+	msgUser("Motion Example starting. Press Enter to continue.");
+
+size_t portCount = 0;
+	std::vector<std::string> comHubPorts;
+
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{ 
+		
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+			
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount < 0) {
+			
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			return -1;  //This terminates the main program
+		}
+		//printf("\n I will now open port \t%i \n \n", portnum);
+		myMgr->PortsOpen(portCount);				//Open the port
+
+		for (size_t i = 0; i < portCount; i++) {
+			IPort &myPort = myMgr->Ports(i);
+
+			printf(" Port[%d]: state=%d, nodes=%d\n",
+				myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+
+
+
+			//Once the code gets past this point, it can be assumed that the Port has been opened without issue
+			//Now we can get a reference to our port object which we will use to access the node objects
+
+			for (size_t iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+				// Create a shortcut reference for a node
+				INode &theNode = myPort.Nodes(iNode);
+
+				theNode.EnableReq(false);				//Ensure Node is disabled before loading config file
+
+				myMgr->Delay(200);
+
+
+				//theNode.Setup.ConfigLoad("Config File path");
+
+
+				printf("   Node[%d]: type=%d\n", int(iNode), theNode.Info.NodeType());
+				printf("            userID: %s\n", theNode.Info.UserID.Value());
+				printf("        FW version: %s\n", theNode.Info.FirmwareVersion.Value());
+				printf("          Serial #: %d\n", theNode.Info.SerialNumber.Value());
+				printf("             Model: %s\n", theNode.Info.Model.Value());
+
+				//The following statements will attempt to enable the node.  First,
+				// any shutdowns or NodeStops are cleared, finally the node is enabled
+				theNode.Status.AlertsClear();					//Clear Alerts on node 
+				theNode.Motion.NodeStopClear();	//Clear Nodestops on Node  				
+				theNode.EnableReq(true);					//Enable node 
+				//At this point the node is enabled
+				printf("Node \t%zi enabled\n", iNode);
+				double timeout = myMgr->TimeStampMsec() + TIME_TILL_TIMEOUT;	//define a timeout in case the node is unable to enable
+																			//This will loop checking on the Real time values of the node's Ready status
+				while (!theNode.Motion.IsReady()) {
+					if (myMgr->TimeStampMsec() > timeout) {
+						printf("Error: Timed out waiting for Node %d to enable\n", iNode);
+						msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+						return -2;
+					}
+				}
+				//At this point the Node is enabled, and we will now check to see if the Node has been homed
+				//Check the Node to see if it has already been homed, 
+				if (theNode.Motion.Homing.HomingValid())
+				{
+					if (theNode.Motion.Homing.WasHomed())
+					{
+						printf("Node %d has already been homed, current position is: \t%8.0f \n", iNode, theNode.Motion.PosnMeasured.Value());
+						printf("Rehoming Node... \n");
+					}
+					else
+					{
+						printf("Node [%d] has not been homed.  Homing Node now...\n", iNode);
+					}
+					//Now we will home the Node
+					theNode.Motion.Homing.Initiate();
+
+					timeout = myMgr->TimeStampMsec() + TIME_TILL_TIMEOUT;	//define a timeout in case the node is unable to enable
+																			// Basic mode - Poll until disabled
+					while (!theNode.Motion.Homing.WasHomed()) {
+						if (myMgr->TimeStampMsec() > timeout) {
+							printf("Node did not complete homing:  \n\t -Ensure Homing settings have been defined through ClearView. \n\t -Check for alerts/Shutdowns \n\t -Ensure timeout is longer than the longest possible homing move.\n");
+							msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+							return -2;
+						}
+					}
+					printf("Node completed homing\n");
+				}
+				else {
+					printf("Node[%d] has not had homing setup through ClearView.  The node will not be homed.\n", iNode);
+				}
+				
+			}
+
+			///////////////////////////////////////////////////////////////////////////////////////
+			//At this point we will execute 10 rev moves sequentially on each axis
+			//////////////////////////////////////////////////////////////////////////////////////
+
+			for (size_t i = 0; i < NUM_MOVES; i++)
+			{
+				for (size_t iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+					// Create a shortcut reference for a node
+					INode &theNode = myPort.Nodes(iNode);
+
+					theNode.Motion.MoveWentDone();						//Clear the rising edge Move done register
+
+					theNode.AccUnit(INode::RPM_PER_SEC);				//Set the units for Acceleration to RPM/SEC
+					theNode.VelUnit(INode::RPM);						//Set the units for Velocity to RPM
+					theNode.Motion.AccLimit = ACC_LIM_RPM_PER_SEC;		//Set Acceleration Limit (RPM/Sec)
+					theNode.Motion.VelLimit = VEL_LIM_RPM;				//Set Velocity Limit (RPM)
+
+					printf("Moving Node \t%zi \n", iNode);
+					theNode.Motion.MovePosnStart(MOVE_DISTANCE_CNTS);			//Execute 10000 encoder count move 
+					printf("%f estimated time.\n", theNode.Motion.MovePosnDurationMsec(MOVE_DISTANCE_CNTS));
+					double timeout = myMgr->TimeStampMsec() + theNode.Motion.MovePosnDurationMsec(MOVE_DISTANCE_CNTS) + 100;			//define a timeout in case the node is unable to enable
+
+					while (!theNode.Motion.MoveIsDone()) {
+						if (myMgr->TimeStampMsec() > timeout) {
+							printf("Error: Timed out waiting for move to complete\n");
+							msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+							return -2;
+						}
+					}
+					printf("Node \t%zi Move Done\n", iNode);
+				} // for each node
+			} // for each move
+
+
+
+		//////////////////////////////////////////////////////////////////////////////////////////////
+		//After moves have completed Disable node, and close ports
+		//////////////////////////////////////////////////////////////////////////////////////////////
+			printf("Disabling nodes, and closing port\n");
+			//Disable Nodes
+
+			for (size_t iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+				// Create a shortcut reference for a node
+				myPort.Nodes(iNode).EnableReq(false);
+			}
+		}
+	}
+	catch (mnErr& theErr)
+	{
+		printf("Failed to disable Nodes n\n");
+		//This statement will print the address of the error, the error code (defined by the mnErr class), 
+		//as well as the corresponding error message.
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n", theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+		return 0;  //This terminates the main program
+	}
+
+	// Close down the ports
+	myMgr->PortsClose();
+
+	msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+	return 0;			//End program
+}
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/Example-Motion.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/Example-Motion.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/Example-Motion.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/README.TXT
new file mode 100644
index 000000000..d64444622
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-Motion/README.TXT
@@ -0,0 +1,14 @@
+Example-Motion
+======================
+
+This is an example for a network of ClearPath SC nodes. This example will discover all the nodes on each SC-hub port, and execute sequential moves on each Node.  The program will wait for each move to be finished before executing the next move on the next Node so only one node will be moving at a time. Node's which have been setup to home through the ClearView software will be homed before motion begins.
+
+Requirements:
+
+-This program executes motion, so all nodes should be unloaded with factory default settings, or should be autotuned on mechanics.
+
+-This program executes repeated motion in one direction, and is not reccommend to be used on axis with limited range of motion.
+
+
+
+Example-Motion.cpp - This is the main function for the program. It holds a reference to the system manager of the network and Port objects. The main program executes a series of moves, then waits for the user to press a key in order to end the program.
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Axis.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Axis.cpp
new file mode 100644
index 000000000..3546bb37c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Axis.cpp
@@ -0,0 +1,421 @@
+///*******************************************************************************
+//
+// NAME
+//		Axis
+//
+// DESCRIPTION:
+//		This class holds the state machine and handles communication
+//		directly with the ClearPath-SC node
+//
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+// 	Axis.cpp headers
+//
+#include <stdio.h>
+#include "Axis.h"
+#include "Supervisor.h"
+#if defined(_WIN32)||defined(_WIN64)
+#include <windows.h>
+#endif
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+// 	Axis.cpp defines
+//
+//																			   *
+//******************************************************************************
+#if defined(_MSC_VER) && _MSC_VER < 1900
+#define snprintf _snprintf
+#endif
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::Axis
+//
+//	DESCRIPTION:
+//		Constructor for the axis state
+//
+Axis::Axis(INode *node) : 
+	m_node(node), 
+	m_moveCount(0), 
+	m_quitting(false) {
+
+	// Save the config file before starting
+	// This would typically be performed right after tuning each axis.
+	// Chosing a file name that contains the address and serial number
+	// can ensure that the system does not get miswired.
+	// Using the UserID as a filename key can allow swapping motors with 
+	// minimal setup required. This requires that no invalid characters 
+	// are present in the UserID.
+	char tempPath[MAX_CONFIG_PATH_LENGTH];
+	#if defined(_WIN32)||defined(_WIN64)
+		GetTempPathA(MAX_CONFIG_PATH_LENGTH, tempPath);
+	#else
+		strncpy(tempPath, "/tmp", sizeof(tempPath));
+	#endif	
+	snprintf(m_configFile, sizeof(m_configFile), "%s/config-%02d-%d.mtr", tempPath, 
+		m_node->Info.Ex.Addr(), m_node->Info.SerialNumber.Value());
+	// sprintf(m_configFile, "%s\config-%s.mtr", tempPath, m_node->Info.UserID.Value());
+
+	if (m_node->Setup.AccessLevelIsFull())
+		m_node->Setup.ConfigSave(m_configFile);
+
+};
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::~Axis
+//
+//	DESCRIPTION:
+//		Destructor for the axis state
+//
+Axis::~Axis(){
+	// Print out the move statistics one last time
+	PrintStats();
+
+	// If we don't have full access, there's nothing to do here
+	if (!m_node->Setup.AccessLevelIsFull()){
+		return;
+	}
+
+	// Disable the node and restore the config file
+	attnReg attnReq;
+	attnReq.cpm.Disabled = 1;
+	m_node->Adv.Attn.ClearAttn(attnReq);
+	m_node->EnableReq(false);
+
+	m_node->Status.RT.Refresh();
+	if (m_node->Status.RT.Value().cpm.Enabled){
+		attnReg theAttn = m_node->Adv.Attn.WaitForAttn(attnReq, 3000);
+		if (theAttn.cpm.Enabled){
+			printf("Error: Timed out waiting for disable\n");
+			return;
+		}
+	}
+	// Restore the original config file
+	// This would typically be performed when setting up the machine.
+	m_node->Setup.ConfigLoad(m_configFile);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::Enable
+//
+//	DESCRIPTION:
+//		Clear alerts and get the node ready to roll
+//
+void Axis::Enable(){
+	if (m_node != NULL){
+		// Clear alerts and node stops
+		m_node->Status.AlertsClear();
+		m_node->Motion.NodeStop(STOP_TYPE_ABRUPT);
+		m_node->Motion.NodeStopClear();
+		
+		// Wait for node to be ready to take commands
+		attnReg attnReq;
+		attnReq.cpm.Ready = 1;
+		m_node->Adv.Attn.ClearAttn(attnReq);
+
+		m_node->EnableReq(true);
+
+		// If the node is not currently ready, wait for it to get there
+		if (!m_node->Status.IsReady()){
+			attnReg theAttn = m_node->Adv.Attn.WaitForAttn(attnReq, 3000);
+			if (!theAttn.cpm.Ready){
+				mnErr eInfo;
+				eInfo.ErrorCode = MN_ERR_TIMEOUT;
+				eInfo.TheAddr = m_node->Info.Ex.Addr();
+				snprintf(eInfo.ErrorMsg, sizeof(eInfo.ErrorMsg),
+					"Error: Timed out waiting for enable\n");
+				throw eInfo;
+			}
+		}
+		attnReq.cpm.Ready = 0;
+		attnReq.cpm.WasHomed = 1;
+
+		m_node->Adv.Attn.ClearAttn(attnReq);
+		//If node is set up to home, start homing
+		if (m_node->Motion.Homing.HomingValid()) {
+			m_node->Motion.Homing.Initiate();
+
+				attnReg theAttn = m_node->Adv.Attn.WaitForAttn(attnReq, 30000);
+				if (!theAttn.cpm.WasHomed) {
+					mnErr eInfo;
+					eInfo.ErrorCode = MN_ERR_TIMEOUT;
+					eInfo.TheAddr = m_node->Info.Ex.Addr();
+					snprintf(eInfo.ErrorMsg, sizeof(eInfo.ErrorMsg),
+						"Error: Timed out waiting for home\n");
+					throw eInfo;
+				}
+		}
+
+	}
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::InitMotionParams
+//
+//	DESCRIPTION:
+//		Initialize accLim, velLim, etc
+//
+void Axis::InitMotionParams(){
+	// Set the user units to RPM and RPM/s
+	m_node->VelUnit(INode::RPM);
+	m_node->AccUnit(INode::RPM_PER_SEC);
+	m_node->Motion.VelLimit = VEL_LIM_RPM;
+	m_node->Motion.AccLimit = ACC_LIM_RPM_PER_SEC;
+	m_node->Motion.JrkLimit = RAS_CODE;
+	m_node->Limits.PosnTrackingLimit.Value(TRACKING_LIM);
+	m_node->Limits.TrqGlobal.Value(TRQ_PCT);
+	// Set up the move itself
+	::int32_t moveDuration;
+#define USE_HEAD_TAIL_MOVES 1
+#if USE_HEAD_TAIL_MOVES
+	m_move.type = MG_MOVE_STYLE_HEADTAIL_TRIG;
+	// Create a reference to advanced motion object to save typing
+	IMotionAdv &motion = m_node->Motion.Adv;
+	motion.HeadDistance = m_move.value/4;
+	motion.TailDistance = m_move.value/4;
+	motion.HeadTailVelLimit = m_node->Motion.VelLimit.Value() / 8;
+	_mgPosnStyle theStyle(m_move.type);
+	moveDuration = (::int32_t)motion.MovePosnHeadTailDurationMsec(m_move.value,
+							theStyle.fld.relative == 0, 
+							motion.HeadDistance.Value() > 0,
+							motion.TailDistance.Value() > 0);
+#else
+	m_move.type = MG_MOVE_STYLE_NORM_TRIG;
+	_mgPosnStyle theStyle(m_move.type);
+	moveDuration = (::int32_t)m_node->Motion.Adv.MovePosnDurationMsec(m_move.value,
+							theStyle.fld.relative == 0);
+#endif
+	// Timeout for move: expected move duration + some time for synch between the nodes
+	m_moveTimeoutMs = moveDuration + 20;
+	//printf("  [%2d]: moveCounts=%d moveTimeout=%d\n", m_node->Info.Ex.Addr, m_move.value, m_moveTimeoutMs);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::Move
+//
+//	DESCRIPTION:
+//		Issue the move
+//
+void Axis::Move(){
+	// Clear out any lingering move done attentions
+	attnReg attnMask;
+	attnMask.cpm.MoveDone = 1;
+	attnMask.cpm.Disabled = 1;
+	attnMask.cpm.NotReady = 1;
+	m_node->Adv.Attn.ClearAttn(attnMask);
+
+	// Uncomment the following line to enable breakpoint debugging. The lock 
+	// allows the application to break without having timeout errors be thrown.
+	// WARNING: While stepping through, leaving the scope this lock is 
+	// declared in (ie this function) will disengage the lock,
+	// and may result in timeouts.
+	//SysManager::ThreadLock lock;
+
+	_mgPosnStyle theStyle(m_move.type);
+#if USE_HEAD_TAIL_MOVES
+	if (m_moveCount % 2 == 0){
+		// Make an absolute position move back to the zero location
+		m_node->Motion.Adv.MovePosnStart(0, true, theStyle.fld.wait);
+	} else {
+		m_node->Motion.Adv.MovePosnHeadTailStart(m_move.value,
+			!theStyle.fld.relative, theStyle.fld.wait,
+			m_node->Motion.Adv.HeadDistance.Value() > 0,
+			m_node->Motion.Adv.TailDistance.Value() > 0,
+			theStyle.fld.dwell);
+	}
+#else
+	m_node->Motion.Adv.MovePosnStart(m_move.value, 
+		!theStyle.fld.relative, theStyle.fld.wait, 
+		theStyle.fld.dwell);
+#endif
+	//printf("  Start move axis %d: %f\n", m_node->Info.Ex.Addr(), infcCoreTime());
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::WaitForMove
+//
+//	DESCRIPTION:
+//		Wait for attention that move has completed
+//
+bool Axis::WaitForMove(::int32_t timeoutMs){
+	if (m_node == NULL){
+		return false;
+	}
+	attnReg attnMask;
+	attnReg attnSeen;
+	attnMask.cpm.MoveDone = 1;
+	attnMask.cpm.Disabled = 1;
+	attnMask.cpm.NotReady = 1;
+	attnSeen = m_node->Adv.Attn.WaitForAttn(attnMask, timeoutMs, false);
+	//printf("  End move axis %d: %f\n", m_node->Info.Ex.Addr(), infcCoreTime());
+	if (attnSeen.cpm.Disabled){
+		printf("  ERROR: [%d] disabled during move\n", m_node->Info.Ex.Addr());
+		return false;
+	}
+	if (attnSeen.cpm.NotReady){
+		printf("  ERROR: [%d] went NotReady during move\n", m_node->Info.Ex.Addr());
+		return false;
+	}
+	return attnSeen.cpm.MoveDone;
+};
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::AxisMain
+//
+//	DESCRIPTION:
+//		The main work of the axis class - initialize the node and run
+//		the state machine
+//
+void Axis::AxisMain(Supervisor *theSuper){
+	bool moveDone;
+
+	m_super = theSuper;
+
+	// If we don't have nodes, exit
+	if (m_node == NULL) {
+		printf("Thread: No node, exiting\n");
+		return;
+	}
+
+	try {
+		attnReg attnMask;
+		attnMask.cpm.MoveDone = 1;
+		attnMask.cpm.Disabled = 1;
+		attnMask.cpm.Enabled = 1;
+		attnMask.cpm.Ready = 1;
+		attnMask.cpm.WasHomed = 1;
+		m_node->Adv.Attn.Mask = attnMask;
+
+		// Get the node ready to go
+		Enable();
+		// Initialize the motion values
+		InitMotionParams();
+	}
+	catch (mnErr &err) {
+		fprintf(stderr, "Thread Setup link error: %s\n", err.ErrorMsg);
+		m_super->Quit();
+	}
+	catch(...) {
+		fprintf(stderr, "Thread setup failed generically.\n");
+		m_super->Quit();
+	}
+
+	if (!m_quitting){
+		// Perform homing here??
+		
+		// Zero out the measured position
+		m_node->Motion.PosnMeasured.Refresh();
+		double posn = m_node->Motion.PosnMeasured.Value();
+		m_node->Motion.AddToPosition(-posn);
+		m_node->Motion.PosnMeasured.Refresh();
+		PrintStats(true);
+	}
+
+	m_state = STATE_IDLE;
+
+	m_super->SignalReady(m_node->Info.Ex.Addr());
+
+	// Start the machine cycling
+	while (!m_quitting)  {
+		try {
+
+			// Save last state for debugging purposes
+			m_lastState = m_state;
+			
+			switch (m_state) {
+				case STATE_IDLE:
+					// Update idle state
+					m_super->SignalIdle(m_node->Info.Ex.Addr());
+					// Quitting?
+					if (m_quitting) 
+						continue;
+					m_state = STATE_WAIT_FOR_KICK;
+					break;
+				case STATE_WAIT_FOR_KICK:
+					m_super->WaitForKick();
+					// Out of here?
+					if (m_quitting)
+						continue;
+					// Supervisor restarted us
+					m_state = STATE_SEND_MOVE;
+					break;
+				case STATE_SEND_MOVE:
+					// Initiate the motion
+					Move();
+					m_state = STATE_SIGNAL_MOVE_SENT;
+					break;
+				case STATE_SIGNAL_MOVE_SENT:
+					m_super->SignalMoveSent(m_node->Info.Ex.Addr());
+					m_state = STATE_WAIT_FOR_MOVE_DONE;
+					break;
+				case STATE_WAIT_FOR_MOVE_DONE:
+					moveDone = WaitForMove(m_moveTimeoutMs);
+					m_super->SignalMoveDone(m_node->Info.Ex.Addr());
+					if (!moveDone){
+						printf("ERROR: [%2d] timed out waiting for move done\n", m_node->Info.Ex.Addr());
+						m_super->Quit();
+						return;
+					}
+					else{
+						m_moveCount++;
+						m_state = STATE_IDLE;
+					}
+					if (m_quitting)
+						continue;
+					break;
+				default:
+					fprintf(stderr, "ThreadFunction: Illegal state");
+					return;
+			}
+		} // Try block
+		catch (mnErr &err) {
+			fprintf(stderr, "Thread link error: %s\n", err.ErrorMsg);
+			m_super->Quit();
+			// Send any signals that the supervisor might be waiting for
+			m_super->SignalMoveSent(m_node->Info.Ex.Addr());
+			m_super->SignalMoveDone(m_node->Info.Ex.Addr());
+			ResetToIdle();
+			continue;
+		}
+		catch(...) {
+			fprintf(stderr, "Thread failed generically.\n");
+			m_super->Quit();
+			// Send any signals that the supervisor might be waiting for
+			m_super->SignalMoveSent(m_node->Info.Ex.Addr());
+			m_super->SignalMoveDone(m_node->Info.Ex.Addr());
+			ResetToIdle();
+		}
+	} // while (!m_quitting) 
+
+	m_state = STATE_EXITED;
+	ResetToIdle();
+	m_super->SignalIdle(m_node->Info.Ex.Addr());
+	printf("[%s] Thread Exited...\n", m_node->Info.UserID.Value());
+	return;
+};
+//																			   *
+//******************************************************************************
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Axis.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Axis.h
new file mode 100644
index 000000000..95d327a9f
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Axis.h
@@ -0,0 +1,165 @@
+/****************************************************************************
+ * $Source: $
+ * $Revision: 7 $ $State: $ $Date: 6/02/16 5:32p $
+ *
+ * !NAME!
+ *		Axis
+ *
+ * DESCRIPTION:
+ *		This class provides an interface to the ClearPath SC node 
+ *		in our example program
+ *
+ * PRINCIPLE AUTHORS:
+ *		JS
+ *
+ * CREATION DATE:
+ *		03/30/2016
+ *
+ * !end!																    *
+ ****************************************************************************/
+
+#ifndef __AXIS_H__
+#define __AXIS_H__
+
+/****************************************************************************
+ * !NAME!																    *
+ * 	Axis.h headers
+ *																		!0! */
+#include <thread>
+#include <condition_variable>
+#include <mutex>
+#include "pubSysCls.h"
+using namespace sFnd;
+using namespace std;
+/* 																	   !end!*
+ ****************************************************************************/
+
+/****************************************************************************
+ * !NAME!																	*
+ * 	Axis.h constants
+ * 																		!0!	*/
+#define RAS_CODE			3 
+#define TRQ_PCT				100
+#define ACC_LIM_RPM_PER_SEC	8000
+#define VEL_LIM_RPM			2000
+#define TRACKING_LIM		(m_node->Info.PositioningResolution.Value() / 4)
+/* !end!																	*
+ ****************************************************************************/
+
+// This class needs to have a reference to its Supervisor
+class Supervisor;
+
+//******************************************************************************
+// NAME																		   *
+// 	Axis class
+//
+// DESCRIPTION
+//	This is the interface to the ClearPath SC. It includes a thread 
+//	which runs the state machine for the node.
+//
+class Axis {
+private:
+	Supervisor *m_super;		// The supervisor
+	INode *m_node;				// The ClearPath-SC for this axis
+	thread m_thread;			// Handle to this Axis's thread
+
+	// Filename for the config file stored at the start
+#define MAX_CONFIG_PATH_LENGTH 256
+#define MAX_CONFIG_FILENAME_LENGTH 384
+	char m_configFile[MAX_CONFIG_FILENAME_LENGTH];
+
+	// State machine information
+	enum StateEnum {
+		STATE_IDLE,
+		STATE_WAIT_FOR_KICK,
+		STATE_SEND_MOVE,
+		STATE_SIGNAL_MOVE_SENT,
+		STATE_WAIT_FOR_MOVE_DONE,
+		STATE_EXITED
+	};
+	StateEnum m_state;
+	StateEnum m_lastState;
+
+	// Move information
+	mgMoveProfiledInfo m_move;
+	::uint32_t m_moveCount;
+	::int32_t m_moveTimeoutMs;
+
+	bool m_quitting;			// Axis quitting
+
+	// Synchronization
+	condition_variable m_cond;
+	mutex m_mutex;
+
+	// Enable the node and get it ready to go
+	void Enable();
+
+	// Initialize accLim, velLim, etc
+	void InitMotionParams();
+
+	// Initiate a move
+	void Move();
+
+	// Wait for attention that move has completed
+	bool WaitForMove(::int32_t timeoutMs);
+	
+	// The state machine
+	void AxisMain(Supervisor *theSuper);
+
+public:
+	// Constructor/Destructor
+	Axis(INode *node);
+	~Axis();
+	
+	// Return a reference to our node
+	INode* MyNode() {
+		return(m_node);
+	};
+
+	// Print the current stats (number of moves performed and
+	// current measured position)
+	void PrintStats(bool onInit = false){
+		m_node->Motion.PosnMeasured.Refresh();
+		if (onInit){
+			printf("  [%2d]:\t\t**at startup**\t\t%8.0f\n", m_node->Info.Ex.Addr(),
+				m_node->Motion.PosnMeasured.Value());
+		}
+		else{
+			printf("  [%2d]:\t\t%8d\t\t%8.0f\n", m_node->Info.Ex.Addr(), m_moveCount,
+				m_node->Motion.PosnMeasured.Value());
+		}
+	}
+
+	// Set the move distance to the given number of revolutions
+	void SetMoveRevs(int numRevs){
+		m_move.value = (long)(m_node->Info.PositioningResolution.Value())*numRevs;
+		printf("[%s] m_move.value=%d\n", m_node->Info.UserID.Value(), m_move.value);
+		m_node->Motion.Adv.HeadDistance = m_move.value/4;
+		m_node->Motion.Adv.TailDistance = m_move.value/4;
+	}
+
+	// Create the thread and get it going
+	void CreateThread(Supervisor *theSuper){
+		m_thread = thread(&Axis::AxisMain, this, theSuper);
+	};
+
+	// Reset sequencer to "idle" state
+	void ResetToIdle(){
+		if (m_state != STATE_IDLE)
+			m_state = m_lastState = STATE_IDLE;
+	};
+
+	// Time to quit
+	void Quit(){
+		m_quitting = true;
+	}
+
+	// Park here to wait for the thread to exit
+	void Join(){
+		m_thread.join();
+	}
+};
+//																			   *
+//******************************************************************************
+
+#endif
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Example-MultiThreaded.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Example-MultiThreaded.cpp
new file mode 100644
index 000000000..d31dd133b
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Example-MultiThreaded.cpp
@@ -0,0 +1,222 @@
+///*******************************************************************************
+/**
+    Example-MultiThreaded
+
+	The main function for Multi-Threaded ClearPath-SC example. The only command
+	line argument is the port number where the network is attached. This
+	main function opens the port, prints some basic information about the
+	nodes that are found, checks that they are all in full-access mode,
+	then creates the Supervisor object (which has its own thread) to run
+	the show. This main thread then waits for the user to hit a key to
+	end the program.
+**/
+//******************************************************************************
+
+#include <stdio.h>
+#include <ctime>
+#include <chrono>
+#include <string>
+#include <iostream>
+#include "Axis.h"
+#include "Supervisor.h"
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+/*****************************************************************************
+*  Function Name: AttentionDetected
+*	 Description:	This is the port-level attention handler function.
+*					This handler simply prints out the attention information
+*					to the console window. 
+*	  Parameters:
+*          Input:	detected		- contains the attention information
+*         Return:		none
+*****************************************************************************/
+void MN_DECL AttentionDetected(const mnAttnReqReg &detected)
+{
+	// Make a local, non-const copy for printing purposes
+	mnAttnReqReg myAttns = detected;
+	// Create a buffer to hold the attentionReg information
+	char attnStringBuf[512];
+	// Load the buffer with the string representation of the attention information
+	myAttns.AttentionReg.StateStr(attnStringBuf, 512);
+	// Print it out to the console
+	printf("  --> ATTENTION: port %d, node=%d, attn=%s\n",
+		detected.MultiAddr >> 4, detected.MultiAddr, attnStringBuf);
+}
+
+
+#if _MSC_VER
+#pragma warning(disable:4996)
+#endif
+// A nice way of printing out the system time
+string CurrentTimeStr() {
+	time_t now = time(NULL);
+	return string(ctime(&now));
+}
+#define CURRENT_TIME_STR CurrentTimeStr().c_str()
+#if _MSC_VER
+#pragma warning(default:4996)
+#endif
+
+int main(int argc, char* argv[])
+{
+	msgUser("Multithreaded Example starting. Press Enter to continue.");
+
+	size_t portCount = 0;
+	std::vector<std::string> comHubPorts;
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{ 
+		
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+			
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount > 0) {
+			//printf("\n I will now open port \t%i \n \n", portnum);
+			myMgr->PortsOpen(portCount);				//Open the port
+
+			for (size_t i = 0; i < portCount; i++) {
+				IPort &myPort = myMgr->Ports(i);
+
+				printf(" Port[%d]: state=%d, nodes=%d\n",
+					myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+			}
+		}
+		else {
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			return -1;  //This terminates the main program
+		}
+
+		// Create a list of axes - one per node
+		vector<Axis*> listOfAxes;
+		// Assume that the nodes are of the right type and that this app has full control
+		bool nodeTypesGood = true, accessLvlsGood = true; 
+
+		for (size_t iPort = 0; iPort < portCount; iPort++){
+			// Get a reference to the port, to make accessing it easier
+			IPort &myPort = myMgr->Ports(iPort);
+
+			// Enable the attentions for this port
+			myPort.Adv.Attn.Enable(true);
+			// The attentions will be handled by the individual nodes, but register
+			// a handler at the port level, just for illustrative purposes.
+			myPort.Adv.Attn.AttnHandler(AttentionDetected);
+
+			for (unsigned iNode = 0; iNode < myPort.NodeCount(); iNode++){
+
+				// Get a reference to the node, to make accessing it easier
+				INode &theNode = myPort.Nodes(iNode);
+				theNode.Motion.AccLimit = 100000;
+
+				// Make sure we are talking to a ClearPath SC
+				if (theNode.Info.NodeType() != IInfo::CLEARPATH_SC_ADV) {
+					printf("---> ERROR: Uh-oh! Node %d is not a ClearPath-SC Advanced Motor\n", iNode);
+					nodeTypesGood = false;
+				}
+
+				if (nodeTypesGood) {
+					// Create an axis for this node
+					listOfAxes.push_back(new Axis(&theNode));
+
+					if (!theNode.Setup.AccessLevelIsFull()) {
+						printf("---> ERROR: Oh snap! Access level is not good for node %u\n", iNode);
+						accessLvlsGood = false;
+					}
+					else {
+						// Set the move distance based on where it is in the network
+						listOfAxes.at(iNode)->SetMoveRevs((iNode + 1) * 2);
+						// Set the trigger group indicator
+						theNode.Motion.Adv.TriggerGroup(1);
+					}
+				}
+
+			}
+
+#if 0
+			// Set the last node in the ring to a longer move
+			listOfAxes.at(listOfAxes.size()-1)->SetMoveRevs(listOfAxes.size()*10);
+#endif
+		}
+
+		// If we have full access to the nodes and they are all ClearPath-SC advanced nodes, 
+		// then continue with the example
+		if (nodeTypesGood && accessLvlsGood){
+
+			// Create the supervisor thread, giving it access to the list of axes
+			Supervisor theSuper(listOfAxes, *myMgr);
+			theSuper.CreateThread();
+
+			printf("\nMachine starting: %s\n", CURRENT_TIME_STR);
+
+			// Everything is running - wait for the user to press a key to end it
+			msgUser("Press any key to stop the machine."); //pause so the user can see the error message; waits for user to press a key
+			
+			printf("Machine stopping: %s\n", CURRENT_TIME_STR);
+
+			// Tell the supervisor to stop
+			theSuper.Quit();
+			theSuper.Terminate();
+
+			printf("\nFinalStats:\tnumMoves\t\tPosition\n");
+		}
+		else{
+			// If something is wrong with the nodes, tell the user about it and quit
+			if (!nodeTypesGood){
+				printf("\n\tFAILURE: Please attach only ClearPath-SC Advanced nodes.\n\n");
+			}
+			else if (!accessLvlsGood){
+				printf("\n\tFAILURE: Please get full access on all your nodes.\n\n");
+			}
+		}
+
+		// Delete the list of axes that were created
+		for (size_t iAxis = 0; iAxis < listOfAxes.size(); iAxis++){
+			delete listOfAxes.at(iAxis);
+		}
+
+		// Close down the ports
+		myMgr->PortsClose();
+
+	}
+	catch (mnErr& theErr) {
+		fprintf(stderr, "Caught error: addr=%d, err=0x%0x\nmsg=%s\n",
+				theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n",
+				theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+		return(2);
+	}
+	catch (...) {
+		fprintf(stderr, "Error generic caught\n");
+		printf("Generic error caught\n");
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+		return(3);
+	}
+
+	// Good-bye
+	msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+	return 0;
+}
+//																			   *
+//******************************************************************************
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Example-MultiThreaded.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Example-MultiThreaded.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Example-MultiThreaded.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/README.TXT
new file mode 100644
index 000000000..aeedef66e
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/README.TXT
@@ -0,0 +1,21 @@
+Example-MultiThreaded(Attentions)
+======================
+
+This is a multi-Threaded example for a network of ClearPath SC nodes. This program will discover all the nodes on each port and synchronize moves among those nodes. The synchronization is fairly simple - the moves are all started at the same time (using a trigger) and the new moves are not sent until all the moves have completed. Each node has a different length of move, so they all finish at different times. The Axis class handles the interaction with a node on the network. The Supervisor class interacts with the Axis objects, telling them when to send their moves to the node. After each node has sent its move, the Supervisor starts all the moves with a Trigger command. The Axis then waits for MoveDone, and reports back to the Supervisor. The Supervisor waits for all the moves to finish, and starts the cycle again.
+
+Requirements:
+
+-This program uses attentions, and triggered moves, so each Node on the port must be an advanced Clearpath Node.
+
+-This program executes motion, so all nodes should be unloaded with factory default settings, or should be autotuned on mechanics.
+
+-This program executes repeated motion in one direction, and is not reccommend to be used on axis with limited range of motion.
+
+
+
+Example-MultiThreaded.cpp - This is the main function for the program. It holds a reference to the system manager of the network and also creates the Supervisor object. The main program then waits for the user to press a key in order to end the program.
+
+Supervisor class - This class holds the references to all the nodes in the network, and synchronizes the moves among those nodes. This class runs its own thread to handle the synchronization without having to wait for the user input to end the program. The Supervisor thread is a state machine that waits for the Axes to be idle, kicks the Axes to tell them to send their move to their node, waits for all the moves to be sent, sends a Trigger to start the moves, waits for all the Axes to report MoveDone, then starts all over again.
+
+Axis class - This class talks to the nodes directly; there is one Axis object per node on the network. Each Axis runs in its own thread, and is synchronized with the other nodes through the Supervisor class. The Axis class basically waits for the Supervisor to tell it to send its move, then waits for MoveDone, reporting back to the Supervisor when it is received. It also reports to the Supervisor if an error was encountered with the node.
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Supervisor.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Supervisor.cpp
new file mode 100644
index 000000000..1e78ee4c1
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Supervisor.cpp
@@ -0,0 +1,215 @@
+///*******************************************************************************
+//
+// NAME
+//		Supervisor
+//
+// DESCRIPTION:
+//		This machine initializes all the nodes and runs the state machine
+//		that synchronizes the moves among the nodes; the synchronization
+//		is simply waiting for all nodes to send their moves to their nodes,
+//		triggering them all at the same time, then waiting for them all to
+//		finish before issuing any more moves
+//
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+// 	Supervisor.cpp headers
+//
+#include "Supervisor.h"
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::Supervisor
+//
+//	DESCRIPTION:
+//		Constructor for the supervisor state
+//
+Supervisor::Supervisor(vector<Axis*> theAxes, SysManager &myMgr) 
+	: m_sysMgr(myMgr)
+{
+	m_axes = theAxes;
+	m_state = SUPER_IDLE;
+	m_quitting = false;
+	// create list of flags to keep track of the nodes for
+	// various conditions
+	for (Uint16 iAxis = 0; iAxis < m_axes.size(); iAxis++){
+		m_axisIdle.push_back(false);
+		m_axisReady.push_back(false);
+		m_axisSentMove.push_back(false);
+		m_axisDone.push_back(false);
+	}
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::SignaleIdle
+//
+//	DESCRIPTION:
+//		Nodes signal to the supervisor when they are idle
+//
+void Supervisor::SignalIdle(Uint16 nodeNum){
+	SignalPerNode(m_axisIdle, m_nodesIdle, nodeNum);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::SignalReady
+//
+//	DESCRIPTION:
+//		Nodes signal to the supervisor when they are ready to go
+//
+void Supervisor::SignalReady(Uint16 nodeNum){
+	SignalPerNode(m_axisReady, m_nodesReady, nodeNum);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::WaitForKick
+//
+//	DESCRIPTION:
+//		Nodes will wait to be kicked
+//
+void Supervisor::WaitForKick(){
+	WaitForCondition(m_nodesKicked);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::SignalMoveSent
+//
+//	DESCRIPTION:
+//		Nodes signal that they have sent their moves
+//
+void Supervisor::SignalMoveSent(Uint16 nodeNum){
+	SignalPerNode(m_axisSentMove, m_nodesMoved, nodeNum);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::SignalMoveDone
+//
+//	DESCRIPTION:
+//		Nodes signal to the supervisor when their move is done
+//
+void Supervisor::SignalMoveDone(Uint16 nodeNum){
+	SignalPerNode(m_axisDone, m_nodesDone, nodeNum);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Supervisor::SuperMain
+//
+//	DESCRIPTION:
+//		The Supervisor's state machine thread; tells each Axis to create its
+//		own thread and initialize itself, then runs the state machine to
+//		tell the Axis objects when to send their moves, triggers the moves
+//		after they've all been sent, and waits for all the nodes to finish 
+//		their move before starting the process again.
+//
+void Supervisor::SuperMain(){
+	// Get all conditions to a known state
+	ResetCondition(m_axisIdle, m_nodesIdle);
+	ResetCondition(m_axisSentMove, m_nodesMoved);
+	ResetCondition(m_axisDone, m_nodesDone);
+	ResetCondition(m_nodesKicked);
+	ResetCondition(m_nodesReady);
+	try{
+		// Create threads for all the axes
+		for (Uint16 iAxis = 0; iAxis < m_axes.size(); iAxis++){
+			//printf(" axis[%d]: userID=%s\n", iAxis, theAxes.at(iAxis)->MyNode()->Info.UserID.Value());
+			m_axes.at(iAxis)->CreateThread(this);
+		}
+	}
+	catch(...){
+		printf("Supervisor failed initializing threads\n");
+		Quit();
+	}
+
+	// Get the state machine going
+	while (!m_quitting){
+		try {
+			// For debugging
+			m_lastState = m_state;
+			switch (m_state){
+				case SUPER_IDLE:
+					// Reset each node to idle
+					for (Uint16 iAxis = 0; iAxis < m_axes.size(); iAxis++)
+						m_axes.at(iAxis)->ResetToIdle();
+					m_state = SUPER_WAIT_FOR_IDLE;
+					break;
+				case SUPER_WAIT_FOR_IDLE:
+					if (m_quitting)
+						continue;
+					// Wait for the nodes to go idle
+					WaitForCondition(m_nodesIdle);
+					if (m_quitting)
+						continue;
+					ResetCondition(m_axisIdle, m_nodesIdle);
+					// Everyone is waiting; kick all the nodes
+					SetCondition(m_nodesKicked);
+					m_state = SUPER_WAIT_FOR_MOVES_SENT;
+					break;
+				case SUPER_WAIT_FOR_MOVES_SENT:
+					// Wait for them all to say their moves have been sent
+					WaitForCondition(m_nodesMoved);
+					if (m_quitting)
+						continue;
+					ResetCondition(m_nodesKicked);
+					ResetCondition(m_axisSentMove, m_nodesMoved);
+					m_axes.at(0)->MyNode()->Port.Adv.TriggerMovesInGroup(1);
+					m_state = SUPER_WAIT_FOR_MOVES_DONE;
+					break;
+				case SUPER_WAIT_FOR_MOVES_DONE:
+					WaitForCondition(m_nodesDone);
+					PrintStats();
+					// Take a break
+					m_sysMgr.Delay(200);
+					if (m_quitting)
+						continue;
+					ResetCondition(m_axisDone, m_nodesDone);
+					m_state = SUPER_WAIT_FOR_IDLE;
+					break;
+				default:
+					printf("Super: Undefined state %d\n", m_state);
+					return;
+			}
+		} // Try block
+		catch (mnErr &err) {
+			fprintf(stderr, "Supervisor thread failed: %s\n", err.ErrorMsg);
+			Quit();
+		}
+		catch(...) {
+			fprintf(stderr, "Supervisor thread failed.\n");
+			Quit();
+		}
+		m_sysMgr.Delay(0);
+	}
+
+	SetCondition(m_nodesKicked);
+	WaitForCondition(m_nodesIdle);
+
+	m_state = SUPER_EXITED;
+	// Wait for threads to end
+	for (Uint16 iAxis = 0; iAxis < m_axes.size(); iAxis++){
+		m_axes.at(iAxis)->Join();
+	}
+	return;
+}
+//																			   *
+//******************************************************************************
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Supervisor.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Supervisor.h
new file mode 100644
index 000000000..347c462e1
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-MultiThreaded/Supervisor.h
@@ -0,0 +1,150 @@
+/****************************************************************************
+ * $Source: $
+ * $Revision: 7 $ $State: $ $Date: 12/09/16 13:13 $
+ *
+ * !NAME!
+ *		Supervisor
+ *
+ * DESCRIPTION:
+ *		This class handles the synchronization between all the
+ *		nodes in the system
+ *
+ * !end!																    *
+ ****************************************************************************/
+
+/****************************************************************************
+ * !NAME!																    *
+ * 	Supervisor.h headers
+ *																		!0! */
+#include "Axis.h"
+#include "pubSysCls.h"
+/* 																	   !end!*
+ ****************************************************************************/
+
+//******************************************************************************
+// NAME																		   *
+// 	Supervisor class
+//
+// DESCRIPTION
+//	The supervisory thread that sets up and handles the synchronization
+//	between all the nodes.
+//
+class Supervisor {
+private:
+	thread m_thread;		// Supervisor's thread
+	SysManager &m_sysMgr;	// sFoundation manager
+
+	vector<Axis *> m_axes;		// the list of nodes
+
+	bool m_quitting;		// are we quitting?
+
+	// synchronization variables
+	mutex m_mutex;
+	condition_variable m_cond;
+	// Flags to indicate that all nodes have reported back 
+	// for various conditions
+	bool m_nodesIdle, m_nodesMoved, m_nodesDone, m_nodesKicked, m_nodesReady;
+	// Flags to keep track of which nodes have reported back
+	// for various conditions
+	vector<bool> m_axisReady;
+	vector<bool> m_axisIdle;
+	vector<bool> m_axisSentMove;
+	vector<bool> m_axisDone;
+
+	// State machine information
+	enum SuperStateEnum {
+		SUPER_IDLE,
+		SUPER_WAIT_FOR_IDLE,
+		SUPER_WAIT_FOR_MOVES_SENT,
+		SUPER_WAIT_FOR_MOVES_DONE,
+		SUPER_EXITED
+	};
+
+	SuperStateEnum m_state;
+	SuperStateEnum m_lastState;
+	
+public:
+	// Constructor
+	Supervisor(vector<Axis*> theAxes, SysManager &myMgr);
+
+	void CreateThread(){
+		m_thread = thread(&Supervisor::SuperMain, this);
+	}
+
+	// Print stats for all the nodes
+	void PrintStats(){
+		printf("\nStats:\t\tnumMoves\t\tPosition\n");
+		for (Uint16 iAxis = 0; iAxis < m_axes.size(); iAxis++){
+			m_axes.at(iAxis)->PrintStats();
+		}
+	}
+
+	// Signals and waits by the nodes
+	void SignalIdle(Uint16 nodeNum);		// Nodes tell the supervisor when they are idle
+	void WaitForKick();						// Nodes need to wait for the supervisor to kick them
+	void SignalMoveSent(Uint16 nodeNum);	// Nodes tell the supervisor when they've sent their move
+	void SignalMoveDone(Uint16 nodeNum);	// Nodes tell the supervisor whne their move is done
+	void SignalReady(Uint16 nodeNum);		// Nodes signal when they are initialized
+
+	void SuperMain();		// the work for this thread
+
+	// sFoundation supervisor for access to foundation support
+	SysManager &Mgr() { return m_sysMgr; }
+
+	// Quit and tell the nodes to quit, too
+	void Quit(){
+		printf("  Supervisor quitting\n");
+		m_quitting = true;
+		for (Uint16 iAxis = 0; iAxis < m_axes.size(); iAxis++)
+			m_axes.at(iAxis)->Quit();
+	}
+
+	// Wait for the thread to finish
+	void Terminate(){
+		m_thread.join();
+	}
+
+private:
+	// Mark that a particular node has signalled back for the given condition
+	void SignalPerNode(vector<bool> &nodeFlags, 
+					   bool &condition, 
+					   Uint16 nodeNum){
+		unique_lock<mutex> lock(m_mutex);
+		nodeFlags.at(nodeNum) = true;
+		bool gotAll = true;
+		for (Uint16 iAxis = 0; iAxis < nodeFlags.size(); iAxis++)
+			gotAll = gotAll && nodeFlags.at(iAxis);
+		if (gotAll){
+			condition = true;
+			m_cond.notify_all();
+		}
+	}
+
+	// Wait for a given condition
+	void WaitForCondition(bool &condition){
+		unique_lock<mutex> lock(m_mutex);
+		while (!condition && !m_quitting)
+			m_cond.wait(lock);
+	}
+
+	// Clear the indicators for a particular condition
+	void ResetCondition(vector<bool> &nodeFlags, bool &condition){
+		unique_lock<mutex> lock(m_mutex);
+		for (Uint16 iAxis = 0; iAxis < nodeFlags.size(); iAxis++)
+			nodeFlags.at(iAxis) = false;
+		condition = false;
+	}
+
+	// Set a condition that doesn't rely on all the nodes to do something
+	void SetCondition(bool &condition){
+		unique_lock<mutex> lock(m_mutex);
+		condition = true;
+		m_cond.notify_all();
+	}
+
+	// Clear a condition that doesn't relay on all the nodes
+	void ResetCondition(bool &condition){
+		unique_lock<mutex> lock(m_mutex);
+		condition = false;
+	}
+};
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Axis.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Axis.cpp
new file mode 100644
index 000000000..32bd89ae5
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Axis.cpp
@@ -0,0 +1,495 @@
+///*******************************************************************************
+//
+// NAME
+//		Axis
+//
+// DESCRIPTION:
+//		This class holds the state machine and handles communication
+//		directly with the ClearPath-SC node
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+// 	Axis.cpp headers
+//
+#include <stdio.h>
+#include "Axis.h"
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+// 	Axis.cpp defines
+//
+//																			   *
+//******************************************************************************
+#if defined(_MSC_VER) && _MSC_VER < 1900
+#define snprintf _snprintf
+#endif
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::Axis
+//
+//	DESCRIPTION:
+//		Constructor for the axis state
+//
+Axis::Axis(SysManager& SysMgr, INode *node) :
+	m_node(node),
+	m_moveCount(0),
+	m_positionWrapCount(0),
+	m_quitting(false),
+	m_sysMgr (SysMgr) {
+
+	// OPTIONAL - Save the config file before starting
+	// This would typically be performed right after tuning each axis.
+	// Chosing a file name that contains the address and serial number
+	// can ensure that the system does not get miswired.
+	// Using the UserID as a filename key can allow swapping motors with 
+	// minimal setup required. This requires that no invalid characters 
+	// are present in the UserID.
+#if defined(_WIN32) || defined(_WIN64)
+	char tempPath[MAX_CONFIG_PATH_LENGTH];
+	GetTempPathA(MAX_CONFIG_PATH_LENGTH, tempPath);
+	snprintf(m_configFile, sizeof(m_configFile), "%s\\config-%02d-%d.mtr", tempPath,
+		m_node->Info.Ex.Addr(), m_node->Info.SerialNumber.Value());
+#else
+	snprintf(m_configFile, sizeof(m_configFile), "/tmp/config-%02d-%d.mtr",
+			m_node->Info.Ex.Addr(), m_node->Info.SerialNumber.Value());
+#endif
+
+	if (m_node->Setup.AccessLevelIsFull())
+		m_node->Setup.ConfigSave(m_configFile);
+};
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::~Axis
+//
+//	DESCRIPTION:
+//		Destructor for the axis state; disable the node and restore the saved
+//		config file
+//
+Axis::~Axis() {
+	// Print out the move statistics one last time
+	PrintStats();
+
+	// If we don't have full access, there's nothing to do here
+	if (!m_node->Setup.AccessLevelIsFull()) {
+		return;
+	}
+
+	// Disable the node and wait for it to disable
+	m_node->EnableReq(false);
+
+	// Poll the status register to confirm the node's disable
+	time_t timeout;
+	timeout = time(NULL) + 3;
+	m_node->Status.RT.Refresh();
+	while (m_node->Status.RT.Value().cpm.Enabled) {
+		if (time(NULL) > timeout) {
+			printf("Error: Timed out waiting for disable\n");
+			return;
+		}
+		m_node->Status.RT.Refresh();
+	};
+
+	// Restore the original config file
+	m_node->Setup.ConfigLoad(m_configFile);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::Enable
+//
+//	DESCRIPTION:
+//		Clear alerts and get the node ready to roll
+//
+void Axis::Enable() {
+	if (m_node != NULL) {
+		// Clear alerts and node stops
+		m_node->Status.AlertsClear();
+		m_node->Motion.NodeStop(STOP_TYPE_ABRUPT);
+		m_node->Motion.NodeStop(STOP_TYPE_CLR_ALL);
+
+		// Enable the node
+		m_node->EnableReq(true);
+
+		// If the node is not currently ready, wait for it to get there
+		time_t timeout;
+		timeout = time(NULL) + 3;
+		// Basic mode - Poll until disabled
+		while (!m_node->Status.IsReady()) {
+			if (time(NULL) > timeout) {
+				printf("Error: Timed out waiting for enable\n");
+				return;
+			}
+		};
+
+		//If node is set up to home, start homing
+		if (m_node->Motion.Homing.HomingValid()) {
+			m_node->Motion.Homing.Initiate();
+			printf("Homing...");
+			time_t timeout;
+			timeout = time(NULL) + 10000;
+			// Basic mode - Poll until disabled
+			while (!m_node->Motion.Homing.WasHomed()) {
+				if (time(NULL) > timeout) {
+					printf("Error: Timed out waiting for homing\n");
+					return;
+				}
+			};
+			printf("Completed\n");
+		}
+	}
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::InitMotionParams
+//
+//	DESCRIPTION:
+//		Initialize accLim, velLim, etc
+//
+void Axis::InitMotionParams() {
+	// Set the user units to RPM and RPM/s
+	m_node->VelUnit(INode::RPM);
+	m_node->AccUnit(INode::RPM_PER_SEC);
+
+	// Set the motion's limits
+	m_node->Motion.VelLimit = VEL_LIM_RPM;
+	m_node->Motion.AccLimit = ACC_LIM_RPM_PER_SEC;
+	m_node->Motion.JrkLimit = RAS_CODE;
+	m_node->Limits.PosnTrackingLimit.Value(TRACKING_LIM);
+	m_node->Limits.TrqGlobal.Value(TRQ_PCT);
+
+	// Set the dwell used by the motor when applicable
+	m_node->Motion.DwellMs = 5;
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::ChangeMotionParams
+//
+//	DESCRIPTION:
+//		Modify velLimit, AccLimit, etc.
+//
+void Axis::ChangeMotionParams(double newVelLimit,
+	double newAccelLimit,
+	uint32_t newJrkLimit,
+	uint32_t newTrackingLimit,
+	int32_t newTrqGlobal) {
+	// Set the motion's limits
+	m_node->Motion.VelLimit = newVelLimit;
+	m_node->Motion.AccLimit = newAccelLimit;
+	m_node->Motion.JrkLimit = newJrkLimit;
+	m_node->Limits.PosnTrackingLimit.Value(newTrackingLimit);
+	m_node->Limits.TrqGlobal.Value(newTrqGlobal);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::PosnMove
+//
+//	DESCRIPTION:
+//		Issue a position move
+//
+void Axis::PosnMove(int32_t targetPosn, bool isAbsolute, bool addDwell) {
+	// Save the move's calculated time for timeout handling
+	m_moveTimeoutMs = (int32_t)m_node->Motion.MovePosnDurationMsec(targetPosn,
+		isAbsolute);
+	m_moveTimeoutMs += 20;
+
+	// Check for number-space wrapping. With successive moves, the position may
+	// pass the 32-bit number cap (+ or -). The check below looks for that and
+	// updates our counter to be used with GetPosition
+	if (!isAbsolute) {
+		if (GetPosition(false) + targetPosn > INT32_MAX) {
+			m_positionWrapCount++;
+		}
+		else if (GetPosition(false) + targetPosn < INT32_MIN) {
+			m_positionWrapCount--;
+		}
+	}
+
+	// Issue the move to the node
+	m_node->Motion.MovePosnStart(targetPosn, isAbsolute, addDwell);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::VelMove
+//
+//	DESCRIPTION:
+//		Issue a velocity move
+//
+void Axis::VelMove(double targetVel) {
+	// Issue the move to the node
+	m_node->Motion.MoveVelStart(targetVel);
+
+	// Move at the set velocity for half a second
+	m_sysMgr.Delay(500);
+
+	// Issue a node stop, forcing any movement (like a 
+	// velocity move) to stop. There are several 
+	// different types of node stops
+	m_node->Motion.NodeStop(STOP_TYPE_ABRUPT);
+	//m_node->Motion.NodeStop(STOP_TYPE_RAMP);
+
+	// Configure the timeout for the node stop to settle
+	m_moveTimeoutMs = 100;
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::WaitForMove
+//
+//	DESCRIPTION:
+//		Wait for attention that move has completed
+//
+bool Axis::WaitForMove(::int32_t timeoutMs, bool secondCall) {
+	if (m_node == NULL) {
+		return false;
+	}
+
+	// Wait for the proper calculated move time
+	time_t timeout;
+	timeout = time(NULL) + timeoutMs;
+
+	m_node->Status.RT.Refresh();
+	// Basic mode - Poll until move done
+	while (!m_node->Status.RT.Value().cpm.MoveDone) {
+		m_node->Status.RT.Refresh();
+		if (time(NULL) > timeout) {
+			printf("Error: Timed out during move\n");
+			return false;
+		}
+
+		// Catch specific errors that can occur during a move
+		if (m_node->Status.RT.Value().cpm.Disabled) {
+			printf("  ERROR: [%d] disabled during move\n",
+				m_node->Info.Ex.Addr());
+			return false;
+		}
+		if (m_node->Status.RT.Value().cpm.NotReady) {
+			printf("  ERROR: [%d] went NotReady during move\n",
+				m_node->Info.Ex.Addr());
+			return false;
+		}
+	}
+
+	return m_node->Status.RT.Value().cpm.MoveDone;
+};
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::AxisMain
+//
+//	DESCRIPTION:
+//		The main work of the axis class - initialize the node and run
+//		the state machine
+//
+void Axis::AxisMain() {
+	bool moveDone;
+
+	// If we don't have nodes, exit
+	if (m_node == NULL) {
+		printf("No node, exiting\n");
+		return;
+	}
+
+	try {
+		// Get the node ready to go
+		Enable();
+		// Initialize the motion values
+		InitMotionParams();
+	}
+	catch (mnErr &err) {
+		fprintf(stderr, "Setup error: %s\n", err.ErrorMsg);
+	}
+	catch (...) {
+		fprintf(stderr, "Setup failed generically.\n");
+	}
+
+	if (!m_quitting) {
+		// If your node has appropriate hardware (hardstop/home switch) 
+		// and is configured in ClearView, uncomment the line below to 
+		// initiate homing
+		//theNode.Motion.Homing.Initiate();
+
+		// Set the hardware brake to allow motion
+		m_node->Port.BrakeControl.BrakeSetting(0, BRAKE_ALLOW_MOTION);
+
+		// Zero out the commanded position
+		m_node->Motion.PosnCommanded.Refresh();
+		double posn = m_node->Motion.PosnCommanded.Value();
+		m_node->Motion.AddToPosition(-posn);
+		m_node->Motion.PosnCommanded.Refresh();
+		PrintStats(true);
+	}
+
+	m_state = STATE_IDLE;
+
+	// Start the machine cycling
+	while (!m_quitting) {
+		try {
+			// Save last state for debugging purposes
+			m_lastState = m_state;
+
+			// Check for alerts
+			CheckForAlerts();
+
+			switch (m_state) {
+			case STATE_IDLE:
+				// Update idle state
+				// Quitting?
+				if (m_quitting)
+					continue;
+				m_state = STATE_SEND_MOVE;
+				break;
+			case STATE_SEND_MOVE:
+				// Initiate the motion
+				if (m_moveCount % 2 == 0) {
+					PosnMove(5000);
+				}
+				else {
+					//Set new motion parameters before the next move
+					ChangeMotionParams(1500, 7500, 4,
+						m_node->Info.PositioningResolution.Value() / 4, 95);
+
+					VelMove(50);
+				}
+
+				// Reset our motion parameters.  The parameters for the 
+				// next move could be entered instead to get a head start
+				InitMotionParams();
+
+				m_state = STATE_WAIT_FOR_MOVE_DONE;
+				break;
+			case STATE_WAIT_FOR_MOVE_DONE:
+				//Check if the move is done yet
+				moveDone = WaitForMove(m_moveTimeoutMs);
+				if (!moveDone) {
+					printf("ERROR: [%2d] timed out waiting for move done\n",
+						m_node->Info.Ex.Addr());
+					return;
+				}
+				else {
+					m_moveCount++;
+					m_state = STATE_IDLE;
+				}
+				if (m_moveCount == 4) {
+					// Stop once we've properly demonstrated movement
+					Quit();
+				}
+				PrintStats();
+				if (m_quitting)
+					continue;
+				break;
+			default:
+				fprintf(stderr, "Illegal state");
+				return;
+			}
+		} // Try block
+		catch (mnErr &err) {
+			fprintf(stderr, "Link error: %s\n", err.ErrorMsg);
+			ResetToIdle();
+			continue;
+		}
+		catch (...) {
+			fprintf(stderr, "Node failed generically.\n");
+			ResetToIdle();
+		}
+	}
+
+	m_state = STATE_EXITED;
+	ResetToIdle();
+	printf("[%s] Quitting node...\n", m_node->Info.UserID.Value());
+	return;
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::CheckForAlerts
+//
+//	DESCRIPTION:
+//		Checks the status register if there are alerts present.
+//		If there are, print some information about them and quit.
+//
+void Axis::CheckForAlerts()
+{
+	// Refresh our relevant registers
+	m_node->Status.Alerts.Refresh();
+	m_node->Status.RT.Refresh();
+
+	//Check for alerts
+	if (m_node->Status.RT.Value().cpm.AlertPresent) {
+		char alertList[256];
+		m_node->Status.Alerts.Value().StateStr(alertList, 256);
+		printf("Node %d has alerts! Alert: %s",
+			m_node->Info.Ex.Addr(), alertList);
+		m_quitting = true;
+	}
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::SetBrakeControl
+//
+//	DESCRIPTION:
+//		Setup the hardware brake control on the node's port. Set's the indicated
+//		brake's mode to the passed-in value
+//
+void Axis::SetBrakeControl(size_t brakeNum, BrakeControls brakeMode)
+{
+	m_node->Port.BrakeControl.BrakeSetting(brakeNum, brakeMode);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		Axis::GetPosition
+//
+//	DESCRIPTION:
+//		Return the node's commanded position scaled properly to wraps of the
+//		number space.
+//
+int64_t Axis::GetPosition(bool includeWraps)
+{
+	// Create a variable to return and refresh the position
+	long long scaledPosn;
+	m_node->Motion.PosnCommanded.Refresh();
+
+	// If there have been no number wraps, just return the position
+	scaledPosn = int64_t(m_node->Motion.PosnCommanded.Value());
+
+	if (includeWraps) {
+		scaledPosn += int64_t(m_positionWrapCount) << 32;
+	}
+
+	return scaledPosn;
+}
+//																			   *
+//******************************************************************************
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Axis.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Axis.h
new file mode 100644
index 000000000..a24abc00c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Axis.h
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * NAME:
+ *		Axis
+ *
+ * DESCRIPTION:
+ *		This class provides an interface to the ClearPath SC node 
+ *		in our example program
+ *
+ ****************************************************************************/
+
+#ifndef __AXIS_H__
+#define __AXIS_H__
+
+ /****************************************************************************
+ * !NAME!																    *
+ * 	Axis.h headers
+ *																		!0! */
+#include <time.h>
+#include "pubSysCls.h"
+#if defined(_WIN32) || defined(_WIN64)
+#include "windows.h"
+#endif
+
+// Use the Teknic library's namespace
+using namespace sFnd;
+// Also use the standard namespace
+using namespace std;
+/* 																	   !end!*
+****************************************************************************/
+
+/****************************************************************************
+* !NAME!																	*
+* 	Axis.h constants
+* 																		!0!	*/
+#define RAS_CODE			3 
+#define TRQ_PCT				100
+#define ACC_LIM_RPM_PER_SEC	8000
+#define VEL_LIM_RPM			2000
+#define TRACKING_LIM		(m_node->Info.PositioningResolution.Value() / 4)
+/* !end!																	*
+****************************************************************************/
+
+//******************************************************************************
+// NAME																		   *
+// 	Axis class
+//
+// DESCRIPTION
+//	This is the interface to the ClearPath SC. 
+//
+class Axis {
+private:
+	INode *m_node;				// The ClearPath-SC for this axis
+	SysManager& m_sysMgr;
+
+// Filename for the stored config file
+#define MAX_CONFIG_PATH_LENGTH 256
+#define MAX_CONFIG_FILENAME_LENGTH 384
+	char m_configFile[MAX_CONFIG_FILENAME_LENGTH];
+
+	// State machine information
+	enum StateEnum {
+		STATE_IDLE,
+		STATE_SEND_MOVE,
+		STATE_WAIT_FOR_MOVE_DONE,
+		STATE_EXITED
+	};
+	StateEnum m_state;
+	StateEnum m_lastState;
+
+	// Move information
+	uint32_t m_moveCount;
+	int32_t m_positionWrapCount;
+	int32_t m_moveTimeoutMs;
+
+	bool m_quitting;			// Axis quitting
+
+	// Enable the node and get it ready to go
+	void Enable();
+
+	// Initialize accLim, velLim, etc
+	void InitMotionParams();
+
+	// Edit the current motion parameters
+	void ChangeMotionParams(double newVelLimit,
+		double newAccelLimit,
+		uint32_t newJrkLimit,
+		uint32_t newTrackingLimit,
+		int32_t newTrqGlobal);
+
+	// Initiate a move
+	void PosnMove(int32_t targetPosn,
+		bool isAbsolute = false,
+		bool addDwell = false);
+	void VelMove(double targetVel);
+
+	// Wait for attention that move has completed
+	bool WaitForMove(::int32_t timeoutMs, bool secondCall = false);
+
+	// Alert handlers
+	void CheckForAlerts();
+
+	// HW Brake Setup
+	void SetBrakeControl(size_t brakeNum, BrakeControls brakeMode);
+
+	// Return scaled position
+	int64_t GetPosition(bool includeWraps = true);
+
+public:
+	// Constructor/Destructor
+	Axis(SysManager&, INode *node);
+	~Axis();
+
+	// The state machine
+	void AxisMain();
+
+	// Return a reference to our node
+	INode* MyNode() {
+		return(m_node);
+	};
+
+	// Print the current stats (number of moves performed and
+	// current commanded position)
+	void PrintStats(bool onInit = false) {
+		// Refresh the measures position register
+		m_node->Motion.PosnCommanded.Refresh();
+		if (onInit) {
+			printf("  [%2d]:\t\t**at startup**\t\t%jd\n",
+				m_node->Info.Ex.Addr(),
+				(intmax_t) GetPosition());
+		}
+		else {
+			printf("  [%2d]:\t\t%8d\t\t%jd\n",
+				m_node->Info.Ex.Addr(), m_moveCount,
+				(intmax_t) GetPosition());
+		}
+	}
+
+	// Reset sequencer to "idle" state
+	void ResetToIdle() {
+		if (m_state != STATE_IDLE)
+			m_state = m_lastState = STATE_IDLE;
+	};
+
+	// Time to quit
+	void Quit() {
+		m_quitting = true;
+	}
+};
+//																			   *
+//******************************************************************************
+
+#endif
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Example-SingleThreaded.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Example-SingleThreaded.cpp
new file mode 100644
index 000000000..695580d8d
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Example-SingleThreaded.cpp
@@ -0,0 +1,160 @@
+///*******************************************************************************
+/**
+	Basic Operations Example
+
+	The main program for single threaded ClearPath-SC example. The only command
+	line argument is the port number where the network is attached. This
+	main function opens the port, prints some basic information about the
+	nodes that are found, checks that they are all in full-access mode,
+	then creates the Axis objects to run the nodes individually.
+**/
+//******************************************************************************
+
+#include <stdio.h>
+#include <ctime>
+#include <string>
+#include <iostream>
+#include "Axis.h"
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+/*****************************************************************************
+*  Function Name: main
+*	Description:	The main function for this single threaded example. 
+*					One command-line argument is expected, which is the COM
+*					port number for where the SC network is attached.
+*		Return:		0 if successful; non-zero if there was a problem
+*****************************************************************************/
+int main(int argc, char* argv[])
+{
+	msgUser("Single-threaded Example starting. Press Enter to continue.");
+
+	size_t portCount = 0;
+	size_t returnVal = 0;
+	std::vector<std::string> comHubPorts;
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{ 
+		
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+			
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount > 0) {
+			//printf("\n I will now open port \t%i \n \n", portnum);
+			myMgr->PortsOpen(portCount);				//Open the port
+
+			for (size_t i = 0; i < portCount; i++) {
+				IPort &myPort = myMgr->Ports(i);
+
+				printf(" Port[%d]: state=%d, nodes=%d\n",
+					myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+			}
+		}
+		else {
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			returnVal = -1;  //This terminates the main program
+		}
+
+		// Create a list of axes - there will be one Axis per node
+		vector<Axis*> listOfAxes;
+
+		// Assume that the nodes are of the right type and that this app has full control
+		bool nodeTypesGood = true, accessLvlsGood = true;
+
+		for (size_t iPort = 0; iPort < portCount; iPort++) {
+			// Get a reference to the port, to make accessing it easier
+			IPort &myPort = myMgr->Ports(iPort);
+
+			for (unsigned iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+				// Get a reference to the node, to make accessing it easier
+				INode &theNode = myPort.Nodes(iNode);
+
+				// Make sure we are talking to a ClearPath SC (advanced or basic model will work)
+				if (theNode.Info.NodeType() != IInfo::CLEARPATH_SC_ADV
+					&& theNode.Info.NodeType() != IInfo::CLEARPATH_SC) {
+					printf("---> ERROR: Uh-oh! Node %d is not a ClearPath-SC Motor\n", iNode);
+					nodeTypesGood = false;
+				}
+
+				if (nodeTypesGood) {
+					// Create an axis for this node
+					listOfAxes.push_back(new Axis(*myMgr, &theNode));
+
+					// Make sure we have full access
+					if (!theNode.Setup.AccessLevelIsFull()) {
+						printf("---> ERROR: Oh snap! Access level is not good for node %u\n", iNode);
+						accessLvlsGood = false;
+					}
+				}
+			}
+		}
+
+		// If we have full access to the nodes and they are all ClearPath-SC nodes, 
+		// then continue with the example
+		if (nodeTypesGood && accessLvlsGood) {
+			for (Uint16 iAxis = 0; iAxis < listOfAxes.size(); iAxis++) {
+				// Tell each axis to do its thing
+				listOfAxes.at(iAxis)->AxisMain();
+			}
+		}
+		else {
+			// If something is wrong with the nodes, tell the user about it
+			if (!nodeTypesGood) {
+				printf("\n\tFAILURE: Please attach only ClearPath-SC nodes.\n\n");
+				returnVal = -5;
+			}
+			else if (!accessLvlsGood) {
+				printf("\n\tFAILURE: Please get full access on all your nodes.\n\n");
+				returnVal = -6;
+			}
+		}
+
+		// Delete the list of axes that were created
+		for (size_t iAxis = 0; iAxis < listOfAxes.size(); iAxis++) {
+			delete listOfAxes.at(iAxis);
+		}
+
+		// Close down the ports
+		myMgr->PortsClose();
+
+	}
+	catch (mnErr& theErr) {
+		fprintf(stderr, "Caught error: addr=%d, err=0x%0x\nmsg=%s\n",
+			theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n",
+			theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		returnVal = -3;
+	}
+	catch (...) {
+		fprintf(stderr, "Error generic caught\n");
+		printf("Generic error caught\n");
+		returnVal = -4;
+	}
+
+	// Good-bye
+	msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+	return returnVal;
+}
+//																			   *
+//******************************************************************************
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Example-SingleThreaded.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Example-SingleThreaded.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/Example-SingleThreaded.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/README.TXT
new file mode 100644
index 000000000..3b9365c50
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-SingleThreaded/README.TXT
@@ -0,0 +1,17 @@
+Example-SingleThreaded(Polling) 
+======================
+
+This is an example for a network of ClearPath SC nodes. This program will discover all the nodes on each port and squentially perform a series of moves on each Node meant to exercise the basic features of a ClearPath SC.
+
+Requirements:
+
+-This program executes motion, so all nodes should be unloaded with factory default settings, or should be autotuned on mechanics.
+
+-This program executes repeated motion in one direction, and is not recommended to be used on axis with limited range of motion.
+
+ 
+
+Example-SingleThreaded.cpp - This is the main function for the program. It holds a reference to the system manager of the network and Axes objects. The main program then waits for the user to press a key in order to end the program.
+
+Axis class - This class talks to the nodes directly; there is one Axis object per node on the network. Each Axis runs in its own operations before calling the next Axis on the network. The Axis class basically starts up a node, issues a series of move and other operations, then closes down.
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/Example-StatusAlerts.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/Example-StatusAlerts.cpp
new file mode 100644
index 000000000..80c6ab122
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/Example-StatusAlerts.cpp
@@ -0,0 +1,174 @@
+///*******************************************************************************
+/**
+	Example-StatusAlerts
+
+	This example demonstrates checking Clearpath-SC node's status and Alert Registers.
+**/
+//******************************************************************************
+
+#include <stdio.h>
+#include <string>
+#include <iostream>
+#include "pubSysCls.h"
+
+using namespace sFnd;
+using namespace std;
+
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+
+int main(int argc, char* argv[])
+{
+	msgUser("Status Alerts Example starting. Press Enter to continue.");
+	size_t portCount = 0;
+	std::vector<std::string> comHubPorts;
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{ 
+		
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+			
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount > 0) {
+			//printf("\n I will now open port \t%i \n \n", portnum);
+			myMgr->PortsOpen(portCount);				//Open the port
+
+			for (size_t i = 0; i < portCount; i++) {
+				IPort &myPort = myMgr->Ports(i);
+
+				printf(" Port[%d]: state=%d, nodes=%d\n",
+					myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+			}
+		}
+		else {
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			return -1;  //This terminates the main program
+		}
+	
+
+		for (size_t iPort = 0; iPort < portCount; iPort++) {
+			// Get a reference to the port, to make accessing it easier
+			IPort &myPort = myMgr->Ports(iPort);
+
+			char alertList[256];
+
+			printf("Checking for Alerts: \n");
+
+			for (unsigned iNode = 0; iNode < myPort.NodeCount(); iNode++) {
+				// Get a reference to the node, to make accessing it easier
+				INode &theNode = myPort.Nodes(iNode);
+
+				// make sure our registers are up to date
+				theNode.Status.RT.Refresh();
+				theNode.Status.Alerts.Refresh();
+
+				printf("---------\n");
+				printf(" Checking node %i for Alerts:\n", iNode);
+
+				// Check the status register's "AlertPresent" bit
+				// The bit is set true if there are alerts in the alert register
+				if (!theNode.Status.RT.Value().cpm.AlertPresent) {
+					printf("   Node has no alerts!\n");
+				}
+				//Check to see if the node experienced torque saturation
+				if (theNode.Status.HadTorqueSaturation()) {
+					printf("      Node has experienced torque saturation since last checking\n");
+				}
+				// get an alert register reference, check the alert register directly for alerts
+				if (theNode.Status.Alerts.Value().isInAlert()) {
+					// get a copy of the alert register bits and a text description of all bits set
+					theNode.Status.Alerts.Value().StateStr(alertList, 256);
+					printf("   Node has alerts! Alerts:\n%s\n", alertList);
+
+					// can access specific alerts using the method below
+					if (theNode.Status.Alerts.Value().cpm.Common.EStopped) {
+						printf("      Node is e-stopped: Clearing E-Stop\n");
+						theNode.Motion.NodeStopClear();
+					}
+					if (theNode.Status.Alerts.Value().cpm.TrackingShutdown) {
+						printf("      Node exceeded Tracking error limit\n");
+					}
+
+					
+
+					// Check for more alerts and Clear Alerts
+					theNode.Status.Alerts.Refresh();
+					if (theNode.Status.Alerts.Value().isInAlert()) {
+						theNode.Status.Alerts.Value().StateStr(alertList, 256);
+						printf("      Node has non-estop alerts: %s\n", alertList);
+						printf("      Clearing non-serious alerts\n");
+						theNode.Status.AlertsClear();
+
+						// Are there still alerts?
+						theNode.Status.Alerts.Refresh();
+						if (theNode.Status.Alerts.Value().isInAlert()) {
+							theNode.Status.Alerts.Value().StateStr(alertList, 256);
+							printf("   Node has serious, non-clearing alerts: %s\n", alertList);
+						}
+						else {
+							printf("   Node %d: all alerts have been cleared\n", theNode.Info.Ex.Addr());
+						}
+					}
+					else {
+						printf("   Node %d: all alerts have been cleared\n", theNode.Info.Ex.Addr());
+					}
+
+				}
+				printf("=========\n");
+			}
+
+			printf("\nShutting down network\n");
+
+			// Close down the ports
+			myMgr->PortsClose();
+		}
+	}
+	catch (mnErr& theErr) {
+		fprintf(stderr, "Caught error: addr=%d, err=0x%0x\nmsg=%s\n",
+				theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n",
+				theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+		msgUser("Press any key to continue.");
+		// keep the console output readable
+		printf("\n");
+		return(2);
+	}
+	catch (...) {
+		fprintf(stderr, "Error generic caught\n");
+		printf("Generic error caught\n");
+		msgUser("Press any key to continue.");
+		// keep the console output readable
+		printf("\n");
+		return(3);
+	}
+
+	// Good-bye
+	msgUser("Press any key to continue.");
+	// keep the console output readable
+	printf("\n");
+	return 0;
+}
+//																			   *
+//******************************************************************************
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/Example-StatusAlerts.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/Example-StatusAlerts.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/Example-StatusAlerts.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/README.TXT
new file mode 100644
index 000000000..ca793c413
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/Example-StatusAlerts/README.TXT
@@ -0,0 +1,7 @@
+Example-StatusAlerts
+======================
+
+This is an example for a network of ClearPath SC nodes. This example will initiate communication with up to three ports.  The port number is automaticaly detected when using the USB connection on the SC4-Hub board. Every Node on each port is checked for alerts, and any found alerts are cleared if possible.
+
+
+Example-StatusAlerts.cpp - This is the main function for the program. It holds a reference to the system manager of the network and Port objects. The main program executes, then waits for the user to press a key in order to end the program.
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/HelloWorld.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/HelloWorld.cpp
new file mode 100644
index 000000000..af2333f77
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/HelloWorld.cpp
@@ -0,0 +1,87 @@
+//Required include files
+#include <stdio.h>		
+#include <iostream>
+#include "pubSysCls.h"	
+
+using namespace sFnd;	
+
+// Send message and wait for newline
+void msgUser(const char *msg) {
+	std::cout << msg;
+	getchar();
+}
+
+/*****************************************************************************
+*	Description:	This program is the bare minimum to open a port and identify the number of nodes
+*		on the port.
+*	
+*
+*		Return:		0 if the system was initialized properly.
+*					-1 if there was a problem accessing the port.
+*****************************************************************************/
+
+int main(int argc, char* argv[]){
+	size_t portCount = 0;
+	std::vector<std::string> comHubPorts;
+
+	msgUser("Hello World Example starting. Press Enter to continue.");
+
+	//Create the SysManager object. This object will coordinate actions among various ports
+	// and within nodes. In this example we use this object to setup and open our port.
+	SysManager* myMgr = SysManager::Instance();							//Create System Manager myMgr
+		
+	printf("Hello World, I am SysManager\n");	//Print to console
+
+	//This will try to open the port. If there is an error/exception during the port opening,
+	//the code will jump to the catch loop where detailed information regarding the error will be displayed;
+	//otherwise the catch loop is skipped over
+	try
+	{ 
+		
+		SysManager::FindComHubPorts(comHubPorts);
+		printf("Found %d SC Hubs\n", comHubPorts.size());
+
+		for (portCount = 0; portCount < comHubPorts.size() && portCount < NET_CONTROLLER_MAX; portCount++) {
+			
+			myMgr->ComHubPort(portCount, comHubPorts[portCount].c_str()); 	//define the first SC Hub port (port 0) to be associated 
+											// with COM portnum (as seen in device manager)
+		}
+
+		if (portCount > 0) {
+			//printf("\n I will now open port \t%i \n \n", portnum);
+			myMgr->PortsOpen(portCount);				//Open the port
+
+			for (size_t i = 0; i < portCount; i++) {
+				IPort &myPort = myMgr->Ports(i);
+
+				printf(" Port[%d]: state=%d, nodes=%d\n",
+					myPort.NetNumber(), myPort.OpenState(), myPort.NodeCount());
+			}
+			// Close down the ports
+			myMgr->PortsClose();
+		}
+		else {
+			printf("Unable to locate SC hub port\n");
+
+			msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+			return -1;  //This terminates the main program
+		}
+	}			
+	catch(mnErr& theErr)	//This catch statement will intercept any error from the Class library
+	{
+		printf("Port Failed to open, Check to ensure correct Port number and that ClearView is not using the Port\n");	
+		//This statement will print the address of the error, the error code (defined by the mnErr class), 
+		//as well as the corresponding error message.
+		printf("Caught error: addr=%d, err=0x%08x\nmsg=%s\n", theErr.TheAddr, theErr.ErrorCode, theErr.ErrorMsg);
+
+		msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+    
+		return -1;  //This terminates the main program
+	}
+
+	msgUser("Press any key to continue."); //pause so the user can see the error message; waits for user to press a key
+
+	return 0;			//End program
+}
+//
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/HelloWorld.vcxproj.user b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/HelloWorld.vcxproj.user
new file mode 100644
index 000000000..e18e04bce
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/HelloWorld.vcxproj.user
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
+    <LocalDebuggerCommandArguments>$(CLEARPATH_PORT)</LocalDebuggerCommandArguments>
+    <DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
+  </PropertyGroup>
+</Project>
\ No newline at end of file
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/README.TXT b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/README.TXT
new file mode 100644
index 000000000..507e0ac20
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/SDK_Examples/HelloWorld/README.TXT
@@ -0,0 +1,5 @@
+HelloWorld
+======================
+
+This example program will initiate communication with up to three ports.  The port number is automaticaly detected when using the USB connection on the SC4-Hub board.
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/linux/SerialLinux.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/linux/SerialLinux.h
new file mode 100644
index 000000000..cd3d37e1b
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/linux/SerialLinux.h
@@ -0,0 +1,402 @@
+//*****************************************************************************
+// $Workfile: SerialLinux.h $
+// $Archive: /ClearPath SC/User Driver/linux/inc/SerialLinux.h $
+// $Revision: 6 $ $Date: 8/29/16 3:14p $
+//
+//	SerialLinux - Definition of the CSerial class for Linux.
+//
+//	Copyright (C) 1999-2003 Ramon de Klein (Ramon.de.Klein@ict.nl)
+//	(C)Copyright 2012  Teknic, Inc.  All rights reserved.
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License, or (at your option) any later version.
+// 
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// Lesser General Public License for more details.
+// 
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+#ifndef __SERIALLINUX_H__
+#define __SERIALLINUX_H__
+
+#include "tekEvents.h"
+#include "tekTypes.h"
+#include <termios.h>
+
+/////////////////////////////////////////////////////////////////////
+// The SERIAL_DEFAULT_OVERLAPPED defines if the default open mode uses
+// overlapped I/O. When overlapped I/O is available (normal Win32
+// platforms) it uses overlapped I/O. Windows CE doesn't allow the use
+// of overlapped I/O, so it is disabled there by default.
+
+#ifndef SERIAL_DEFAULT_OVERLAPPED
+#ifdef __cplusplus
+
+#ifndef SERIAL_NO_OVERLAPPED
+#define SERIAL_DEFAULT_OVERLAPPED	true
+#else
+#define SERIAL_DEFAULT_OVERLAPPED	false
+#endif
+#endif
+#define BREAK_DURATION_MS	40			// # msec for break operation
+// Invalid handle return from "open" failures
+#define INVALID_HANDLE  -1
+
+// #define SERIAL_FULL_API				// Define for full API
+
+
+//////////////////////////////////////////////////////////////////////
+//
+// CSerial - Win32 wrapper for serial communications
+//
+// Serial communication often causes a lot of problems. This class
+// tries to supply an easy to use interface to deal with serial
+// devices.
+//
+// The class is actually pretty ease to use. You only need to open
+// the COM-port, where you need to specify the basic serial
+// communication parameters. You can also choose to setup handshaking
+// and read timeout behaviour.
+//
+// The following serial classes are available:
+//
+// CSerial      - Serial communication support.
+// CSerialEx    - Serial communication with listener thread for events
+// CSerialSync  - Serial communication with synchronized event handler
+// CSerialWnd   - Asynchronous serial support, which uses the Win32
+//                message queue for event notification.
+// CSerialMFC   - Preferred class to use in MFC-based GUI windows.
+// 
+//
+// Pros:
+// -----
+//	- Easy to use (hides a lot of nasty Win32 stuff)
+//	- Fully ANSI and Unicode aware
+//
+// Cons:
+// -----
+//  - Little less flexibility then native Win32 API, however you can
+//    use this API at the same time for features which are missing
+//    from this class.
+//  - Incompatible with Windows 95 or Windows NT v3.51 (or earlier),
+//    because CancelIo isn't support on these platforms. Define the
+//	  SERIAL_NO_CANCELIO macro for support of these platforms as
+//	  well. When this macro is defined, then only time-out values of
+//	  0 or INFINITE are valid.
+//
+//
+// Copyright (C) 1999-2003 Ramon de Klein
+//                         (Ramon.de.Klein@ict.nl)
+
+class CSerial
+{
+// Class enumerations
+public:
+	// These are return codes from serial API. They generally map
+	// into the host OS's error code list except for the items
+	// at the end of the list.
+	typedef enum
+	{
+		API_ERROR_SUCCESS = 0,
+		// Between here and API_ERROR_TIMEOUT are mapped
+		// to errno.
+		API_ERROR_TIMEOUT=0x40000000,
+		API_ERROR_PORT_SETUP,
+		API_ERROR_INVALID_HANDLE,
+		API_ERROR_INVALID_ARG,
+		API_ERROR_PORT_UNAVAILABLE
+	}
+	SERAPI_ERR;
+	
+	// Communication event. Bit encoded
+	typedef enum
+	{
+		EEventNone = 	0,
+		EEventBreak = 	1, 				// A break was detected on input
+		EEventError = 	2, 				// A line-status error occurred
+		EEventRecv = 	4, 				// Data is received on input
+		EEventCTS = 	8				// CTS change
+	} 
+	EEvent;
+
+	// Data bits (5-8)
+	typedef enum
+	{
+		EDataUnknown = -1,				// Unknown
+		EData5       =  CS5,			// 5 bits per byte
+		EData6       =  CS6,			// 6 bits per byte
+		EData7       =  CS7,			// 7 bits per byte
+		EData8       =  CS8				// 8 bits per byte (default)
+	}
+	EDataBits;
+
+	// Parity scheme
+	typedef enum
+	{
+		EParUnknown = -1,				// Unknown
+		EParNone    = 0,				// No parity (default)
+		EParOdd     = PARENB | PARODD,	// Odd parity
+		EParEven    = PARENB,			// Even parity
+//		EParMark    = PARENB | PARMRK,	// Mark parity
+//		EParSpace   = PARENB | CMSPAR	// Space parity
+	}
+	EParity;
+
+	// Stop bits
+	typedef enum
+	{
+		EStopUnknown = -1,				// Unknown
+		EStop1       = 0,				// 1 stopbit (default)
+		EStop2       = CSTOPB			// 2 stopbits
+	} 
+	EStopBits;
+
+	// return constant for unknown baud rate
+	static const nodeulong EBaudUnknown = 0;
+
+	// Handshaking
+	typedef enum
+	{
+		EHandshakeUnknown		= -1,			// Unknown
+		EHandshakeOff			=  0,			// No handshaking
+	} 
+	EHandshake;
+
+	// DTR
+	typedef enum
+	{
+		EDTRClear		= 0,	// Clear - (Volt DTR = -5)
+		EDTRSet			= true,	// Set - (Volt DTR = 5)
+	} 
+	EDTR;
+
+	// RTS
+	typedef enum
+	{
+		ERTSClear		= 0,	// Clear - (Volt RTS = -5)
+		ERTSSet			= true,	// Set - (Volt RTS = 5)
+	} 
+	ERTS;
+
+	// Timeout settings
+	typedef enum
+	{
+		EReadTimeoutUnknown		= -1,	// Unknown
+		EReadTimeoutNonblocking	=  0,	// Always return immediately
+		EReadTimeoutBlocking	=  1	// Block until everything is retrieved
+	}
+	EReadTimeout;
+
+	// Communication errors (bit encoded)
+	typedef enum
+	{
+		EErrorUnknown = 0,			// Unknown
+		EErrorFrame = 1,			// Framing error
+		EErrorRxOver = 2,			// Input buffer overflow, byte lost
+		EErrorMode = 4,
+		EErrorOverrun = 8,
+		EErrorBreak = 16
+	}
+	EError;
+
+	// Port availability
+	typedef enum
+	{
+		EPortUnknownError = -1,		// Unknown state
+		EPortAvailable    =  0,		// Port is available
+		EPortNotAvailable =  1,		// Port is not present
+		EPortInUse        =  2		// Port is in use
+	} 
+	EPort;
+	// Text if last failure
+	char m_lastErrMsg[500];
+
+// Construction
+public:
+	CSerial();
+	virtual ~CSerial();
+
+// Operations
+public:
+	// Open the serial communications for a particular COM port. You
+	// need to use the full devicename (i.e. "COM1") to open the port.
+	// It's possible to specify the size of the input/output queues.
+	virtual SERAPI_ERR Open ( const char * portName,
+						DWORD dwInQueue = 0,
+						DWORD dwOutQueue = 0,
+						bool fOverlapped = SERIAL_DEFAULT_OVERLAPPED);
+
+	// Close the serial port.
+	virtual SERAPI_ERR Close (void);
+
+	// Setup the communication settings such as baudrate, databits,
+	// parity and stopbits. The default settings are applied when the
+	// device has been opened. Call this function if these settings do
+	// not apply for your application. If you prefer to use integers
+	// instead of the enumerated types then just cast the integer to
+	// the required type. So the following two initializations are
+	// equivalent:
+	//
+	//   Setup(9600,EDataBits(8),EParity(NOPARITY),EStopBits(ONESTOPBIT))UD_RATE
+	//
+	// In the latter case, the types are not validated. So make sure
+	// that you specify the appropriate values.
+	virtual SERAPI_ERR Setup (nodeulong eBaudrate = 9600,
+						EDataBits eDataBits = EData8,
+						EParity   eParity   = EParNone,
+						EStopBits eStopBits = EStop1,
+						EDTR eDTRBit = EDTRClear,
+						ERTS eRTSBit = ERTSClear);
+
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Communications Event Interface. Provides signals upon various
+	// normal serial communications events such as break condition detect.
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+protected:
+	// Signaled when an unmasked event has occurred
+	CCEvent m_commEvent;
+	// Signaled when read data is available
+	CCEvent m_rdEvent;
+	// Comms Error(s) detected (bit field)
+	EError m_eError;
+public:
+	// Set the event mask, which indicates what events should be
+	// monitored. The WaitForCommEvent method can only monitor events that
+	// have been enabled. The default setting only monitors the
+	// error events and data events. An application may choose to
+	// monitor CTS. DSR, RLSD, etc as well.
+	virtual SERAPI_ERR SetEventMask (DWORD dwMask = EEventBreak|EEventError|EEventRecv|EEventCTS);
+	DWORD GetEventMask   (void) {return m_dwEventMask;}
+
+	// The WaitEvent method waits for one of the events that are
+	// enabled (see SetMask).
+	virtual SERAPI_ERR CommEventWaitInitiate();
+	// This is the communicatins notification event, must outlive the thread
+	bool WaitForCommEvent(unsigned int timeOutMS) {
+		return m_commEvent.WaitFor(timeOutMS);
+	}
+	void ForceCommEvent() {
+		m_commEvent.SetEvent();
+	}
+
+	// Determine what caused the event to trigger
+	EEvent GetEventType (void);
+	// Obtain the error and clear
+	EError GetError (void) {
+		EError errs = m_eError;
+		m_eError = EErrorUnknown;
+		return(errs);
+	}
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Basic Port Read/Write of data
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+	// Write ANSI data to the serial port.
+	virtual SERAPI_ERR Write (const void* pData,
+						size_t iLen,
+						DWORD* pdwWritten = 0,
+						DWORD dwTimeout = INFINITE);
+
+	// Read data from the serial port. 
+	virtual SERAPI_ERR Read (void* pData,
+					   size_t iLen,
+					   DWORD* pdwRead = 0,
+					   DWORD dwTimeout = INFINITE);
+
+	// Check if com-port is opened
+	bool IsOpen (void) const		{ return (m_hFile != INVALID_HANDLE); }
+
+	// Obtain last error status
+	SERAPI_ERR GetLastError (void) const	{ return m_lLastError; }
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Operational State and Control Line API
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+	// Send a break
+	virtual SERAPI_ERR Break (DWORD breakDurationMs);
+	// Data Terminal Ready output
+	bool GetDTR (void);
+	void SetDTR(bool EDTRBit);
+	// Request to Send output
+	bool GetRTS (void);
+	void SetRTS(bool ERTSBit);
+	// Data Set Ready input
+	bool GetDSR (void);
+	// Clear-to-send input
+	bool GetCTS (void);
+	
+	// Obtain communication settings
+	virtual nodeulong  GetBaudrate    (void);
+
+	
+	
+protected:
+
+// Attributes
+protected:
+	SERAPI_ERR	m_lLastError;		// Last serial error
+	int		m_hFile;			// File handle
+	EEvent	m_eEvent;			// Event type
+	DWORD	m_dwEventMask;		// Event mask
+	unsigned char readBuf [256];
+
+protected:
+	// CancelIo wrapper
+	SERAPI_ERR CancelCommIo (void);
+	// Purge all buffers
+	SERAPI_ERR Purge (void);
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	//						FULL API IMPLEMENTATION							  //
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	#ifdef SERIAL_FULL_API
+//	virtual BYTE       GetEventChar   (void);
+	// Setup the handshaking protocol. There are three forms of
+	// handshaking:
+	//
+	// 1) No handshaking, so data is always send even if the receiver
+	//    cannot handle the data anymore. This can lead to data loss,
+	//    when the sender is able to transmit data faster then the
+	//    receiver can handle.
+	// 2) Hardware handshaking, where the RTS/CTS lines are used to
+	//    indicate if data can be sent. This mode requires that both
+	//    ports and the cable support hardware handshaking. Hardware
+	//    handshaking is the most reliable and efficient form of
+	//    handshaking available, but is hardware dependant.
+	// 3) Software handshaking, where the XON/XOFF characters are used
+	//    to throttle the data. A major drawback of this method is that
+	//    these characters cannot be used for data anymore.
+//	virtual LONG SetupHandshaking (EHandshake eHandshake);
+	// Set/clear the event character. When this byte is being received
+	// on the serial port then the EEventRcvEv event is signalled,
+	// when the mask has been set appropriately. If the fAdjustMask flag
+	// has been set, then the event mask is automatically adjusted.
+//	virtual LONG SetEventChar (BYTE bEventChar, bool fAdjustMask = true);
+
+	// Obtain communication settings
+//	virtual EDataBits  GetDataBits    (void);
+//	virtual EParity    GetParity      (void);
+//	virtual EStopBits  GetStopBits    (void);
+//	virtual EHandshake GetHandshaking (void);
+	// Obtain CTS/DSR/RING/RLSD settings
+	bool GetCTS (void);
+	bool GetDSR (void);
+//	bool GetRing (void);
+//	bool GetRLSD (void);
+	#endif
+};
+#endif	// Cplusplus
+
+#endif	// __SERIAL_H
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/linux/tekEventsLinux.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/linux/tekEventsLinux.h
new file mode 100644
index 000000000..123ecfb06
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/linux/tekEventsLinux.h
@@ -0,0 +1,461 @@
+//*****************************************************************************
+// $Workfile: tekEventsLinux.h $
+// $Archive:: /ClearPath SC/LinuxPrjEclipse/sFoundation20/linux/inc/tekEvents $
+// $Revision: 12 $ $Date: 12/22/16 12:42 $
+//
+// DESCRIPTION:
+//		Thin layer to create synchronization objects for Linux.
+//
+// CREATION DATE:
+//		05/14/2004 13:03:56
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2004-2012  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			   *
+//******************************************************************************
+#ifndef __TEKEVENTS_H__
+#define	__TEKEVENTS_H__
+
+
+
+//******************************************************************************
+// NAME																           *
+// 	tekEvents.h headers
+//
+	#include <errno.h>
+	#include <pthread.h>
+	#include <semaphore.h>
+	#include <stdio.h>
+	#include <string>
+    #include <sys/time.h>
+
+	#include <assert.h>
+	#include "tekTypes.h"
+	using namespace std;
+	#define EOK 0
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																           *
+// 	tekEvents.h constants
+//
+//
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define SYNC_INFINITE  0xFFFFFFFFU
+#define INFINITE  DWORD(0xFFFFFFFF)
+#define LPSECURITY_ATTRIBUTES void *
+typedef void * HANDLE;
+
+
+//*****************************************************************************
+//   NAME
+//           CCaddAbsTime
+//
+//   CREATION DATE:
+//           03/29/2012 13:33
+//
+//   DESCRIPTION:
+/**
+          Add the required milliseconds from now and update
+          \a abs_time.
+
+          \param[in] incrMilliseconds time increment
+          \param[out] abs_time resulting time from now
+ **/
+//   SYNOPSIS:
+inline void CCaddAbsTime(timespec &abs_time, double incrMilliseconds)
+{
+	// Try better clock, if not fallback on common
+	//if(clock_gettime( CLOCK_MONOTONIC, &abs_time )) {
+		assert(clock_gettime( CLOCK_REALTIME, &abs_time ) == 0);
+	//}
+	nodeulong secs = nodeulong(incrMilliseconds/1000);
+	abs_time.tv_sec += secs;
+	// Prevent overflow on longer time-outs
+	abs_time.tv_nsec += (incrMilliseconds-secs*1000) * 1000000L;
+	if ( abs_time.tv_nsec > 1000000000L) {
+		abs_time.tv_nsec -= 1000000000L;
+		abs_time.tv_sec += 1;
+	}
+}
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//   NAME
+//           class CCSemaphore
+//
+//   CREATION DATE:
+//           02/08/2010 11:37:08
+//
+//   DESCRIPTION:
+///          The classic resource counting mutual exclusion device.  A request
+///          to Lock is blocked via the scheduler until some other thread
+///          Unlocks the resource. Optionally multiple "counts" can be made
+///          available if required.
+//
+//   SYNOPSIS:
+class CCSemaphore
+{
+public:
+	CCSemaphore (long lInitialCount = 0,
+			  long lMaxCount = 1,
+			  int lpsaAttributes = 0)
+	{
+		assert(sem_init( &sem, lpsaAttributes, unsigned(lMaxCount) )==EOK);
+	}
+	virtual ~CCSemaphore() {
+	    assert(sem_destroy(&sem)==EOK);
+	}
+
+	// Return TRUE if we own resource
+	virtual bool Lock (Uint32 timeoutMsec = SYNC_INFINITE)
+	{
+		int r = -1;
+		if ( timeoutMsec == SYNC_INFINITE ) {
+			r = sem_wait( &sem );
+		} else {
+			struct timespec abs_time;
+			CCaddAbsTime(abs_time, timeoutMsec);
+			r = sem_timedwait( &sem, &abs_time );
+		}
+	  	return r == -1 ? false : true;
+	}
+
+	// Release one item, return TRUE if succeeded
+	virtual int Unlock ()
+	{
+		return sem_post( &sem ) == 0 ? 1 : 0;
+	}
+
+	// Release multiple items and return the count that was left.
+	virtual bool Unlock (long lCount, long *lPrevCount = NULL)
+	{
+		for ( int ix = 0; ix < lCount; ++ix )
+			sem_post( &sem );
+		if ( lPrevCount != NULL )
+			sem_getvalue( &sem, (int *) lPrevCount );
+		return 1;
+	}
+
+protected:
+	sem_t sem;
+};
+//
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME
+//		class CCEvent
+//
+//  CREATION DATE:
+//		02/08/2010 11:37:08
+//
+//	DESCRIPTION:
+/**
+	A scheduler based blocking event. Multiple threads can wait for the
+	underlying event to "signal" via SetEvent to restart
+	their execution. There is an optional time-out for the wait.
+
+ 	Detailed description.
+**/
+//	SYNOPSIS:
+class CCEvent
+{
+private:
+	pthread_mutex_t mutex;
+	pthread_cond_t cond;
+	int manual_reset;
+	bool m_set;
+public:
+	CCEvent (bool bInitiallyOwn = false,
+			bool bManualReset = true,
+			LPSECURITY_ATTRIBUTES lpsaAttribute = NULL) :
+			manual_reset( bManualReset ),
+			m_set( bInitiallyOwn ) {
+		assert(pthread_mutex_init( &mutex, NULL )==EOK);
+		assert(pthread_cond_init( &cond, NULL )==EOK);
+ 	}
+	~CCEvent() {
+		int theErr;
+		assert((theErr=pthread_mutex_destroy(&mutex))==EOK);
+		assert((theErr=pthread_cond_destroy(&cond))==EOK);
+	}
+
+	// in Linux the semaphore always exists
+	bool isOK ()
+	{
+		return true;
+	}
+
+	// Signal and leave signaled our event
+	bool SetEvent ( bool do_mutex = true )
+	{
+//		_RPT1(_CRT_WARN, "Evt Set 0x%lx\n", this);
+		int r = EOK;
+		if ( do_mutex ) assert(pthread_mutex_lock( &mutex )==EOK);
+
+		if (!m_set) {
+			m_set = true;
+			r = pthread_cond_broadcast( &cond );
+		}
+		if ( do_mutex ) assert(pthread_mutex_unlock( &mutex )==EOK);
+	  	return r==EOK;
+	}
+
+	// Un-signal and block waiters
+	bool ResetEvent ()
+	{
+//		_RPT1(_CRT_WARN, "Evt Reset 0x%lx\n", this);
+		m_set = false;
+	  	return true;
+	}
+
+
+	// Cause the calling thread to block until "signaled" or TimeOut
+	// occurs. Returns TRUE if wait was signaled normally.
+	bool WaitFor ( unsigned timeoutMsec=SYNC_INFINITE )
+	{
+		assert(pthread_mutex_lock( &mutex )==EOK);
+		int r=EOK;
+		// Return if already signaled
+		if ( ! m_set ) {
+			if ( timeoutMsec == SYNC_INFINITE ) {
+				// Prevent spurious wakeup
+				do {
+					r = pthread_cond_wait( &cond, &mutex );
+				} while (r!=EOK && !m_set);
+			}
+			else {
+				// Create our time-out
+				struct timespec abs_time;
+				CCaddAbsTime(abs_time, timeoutMsec);
+				do {
+					r = pthread_cond_timedwait( &cond, &mutex, &abs_time );
+				} while (r!=EOK && r!=ETIMEDOUT && !m_set);
+			}
+		}
+		assert(pthread_mutex_unlock( &mutex )==EOK);
+	  	return (r == EOK);
+	}
+
+	HANDLE GetHandle() {
+		return(&cond);
+	}
+
+};
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME
+//		class CCCriticalSection
+//
+//  CREATION DATE:
+//		02/08/2010 11:37:08
+//
+//	DESCRIPTION:
+///		Create a critical section lockout.
+//
+//	SYNOPSIS:
+class CCCriticalSection
+{
+protected:
+	 pthread_mutex_t mutex;
+public:
+  	CCCriticalSection ()
+	{
+  		//pthread_mutexattr_t psharedm;
+  		//(void) pthread_mutexattr_init(&psharedm);
+  		//(void) pthread_mutexattr_settype(&psharedm, PTHREAD_MUTEX_RECURSIVE);
+  		//assert(pthread_mutex_init( &mutex, &psharedm )==EOK);
+  		assert(pthread_mutex_init( &mutex, NULL )==EOK);
+ 		// might need to set PTHREAD_PROCESS_SHARED
+	}
+
+  	~CCCriticalSection ()
+	{
+		pthread_mutex_destroy( &mutex );
+	}
+
+	HANDLE GetHandle ()
+	{
+	  return &mutex;
+	}
+	// Return TRUE if we released critical section
+	bool Unlock ()
+	{
+		return(pthread_mutex_unlock( &mutex )==EOK);
+	}
+
+	// Return TRUE if we own critical section
+	bool Lock ( Uint32 timeoutMsec=SYNC_INFINITE )
+	{
+		int r = 0;
+		if ( timeoutMsec == SYNC_INFINITE ) {
+			r = pthread_mutex_lock( &mutex );
+		} else {
+			struct timespec abs_time;
+			CCaddAbsTime(abs_time, timeoutMsec);
+			r = pthread_mutex_timedlock( &mutex, &abs_time );
+		}
+		//if ( r ) throw ;
+	  	return r==EOK;
+	}
+};
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME
+//		class CCMutex
+//
+//  CREATION DATE:
+//		02/08/2010 11:37:08
+//
+//	DESCRIPTION:
+///		Create a critical section lockout.
+//
+//	SYNOPSIS:
+class CCMutex
+{
+protected:
+	 pthread_mutex_t mutex;
+public:
+	 CCMutex ()
+	{
+  		//pthread_mutexattr_t psharedm;
+  		//(void) pthread_mutexattr_init(&psharedm);
+  		//(void) pthread_mutexattr_settype(&psharedm, PTHREAD_MUTEX_RECURSIVE);
+  		//assert(pthread_mutex_init( &mutex, &psharedm )==EOK);
+  		assert(pthread_mutex_init( &mutex, NULL )==EOK);
+ 		// might need to set PTHREAD_PROCESS_SHARED
+	}
+
+  	~CCMutex ()
+	{
+		pthread_mutex_destroy( &mutex );
+	}
+
+	HANDLE GetHandle ()
+	{
+	  return &mutex;
+	}
+	// Return TRUE if we released critical section
+	bool Unlock ()
+	{
+		return(pthread_mutex_unlock( &mutex )==EOK);
+	}
+
+	// Return TRUE if we own critical section
+	bool Lock ( Uint32 timeoutMsec=SYNC_INFINITE )
+	{
+		int r = 0;
+		if ( timeoutMsec == SYNC_INFINITE ) {
+			r = pthread_mutex_lock( &mutex );
+		} else {
+			struct timespec abs_time;
+			CCaddAbsTime(abs_time, timeoutMsec);
+			r = pthread_mutex_timedlock( &mutex, &abs_time );
+		}
+		//if ( r ) throw ;
+	  	return r==EOK;
+	}
+};
+//
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CCMTMultiLock Class
+//
+//  CREATION DATE:
+//		2012-03-27 13:40:33
+//
+//	DESCRIPTION:
+/**
+		Wait for one or all events to signal.
+
+**/
+class CCMTMultiLock
+{
+protected:
+	Uint32            m_dwUnlockCount;
+	Uint32            m_dwCount;
+	CCEvent           *m_hPreallocated[8];
+	bool              m_bPreallocated[8];
+	CCEvent * const *
+	                 m_ppObjectArray;
+	CCEvent         ** m_pHandleArray;
+	bool           * m_bLockedArray;
+
+public:
+	CCMTMultiLock(CCEvent *pObjects[], Uint32 dwCount,
+		          Uint32 UnlockCount=1, bool bWaitForAll=true,
+				  Uint32 dwTimeout=SYNC_INFINITE, Uint32 dwWakeMask=0);
+
+	~CCMTMultiLock();
+
+public:
+	Uint32 Lock(Uint32 dwTimeOut=SYNC_INFINITE,
+		     bool bWaitForAll=true,Uint32 dwWakeMask=0);
+
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		class CCatomicUpdate
+//
+//	DESCRIPTION:
+/**
+	Atomic increment and decrement / test object.
+**/
+//	SYNOPSIS:
+class CCatomicUpdate
+{
+private:
+	LONG m_value;
+public:
+	CCatomicUpdate() {
+		m_value = 0;
+	}
+
+	LONG Incr() {
+		return __sync_add_and_fetch(&m_value,1);
+	}
+
+	LONG Decr() {
+		return __sync_sub_and_fetch(&m_value,1);
+	}
+};
+//																			  *
+//*****************************************************************************
+
+
+#endif
+//=============================================================================
+//	END OF FILE tekEvents.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/SerialEx.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/SerialEx.h
new file mode 100644
index 000000000..44d4f3a43
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/SerialEx.h
@@ -0,0 +1,535 @@
+//*****************************************************************************
+// $Workfile: SerialEx.h $
+// $Archive: /ClearPath SC/Win Eclipse/MNuserDriver20/inc-private/SerialEx.h $
+// $Date: 01/19/2017 17:39 $
+//
+//	SerialEx.h - Definition of the CSerialEx class
+//
+//	Copyright (C) 1999-2003 Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+#ifndef __SERIAL_EX_H__
+#define __SERIAL_EX_H__
+
+
+//////////////////////////////////////////////////////////////////////
+// Include CSerial base class
+#if (defined(_WIN32)||defined(_WIN64))
+	#include "SerialWin32.h"
+#elif defined __QNX__
+	#include "SerialQNX.h"
+#else
+	#include "SerialLinux.h"
+#endif
+// Teknic Headers
+#include "pubMnNetDef.h"
+#include "tekThreads.h"
+#include "tekEvents.h"
+// StdLib inclusions
+#include <deque>
+
+// Maximum polling delay for break detector
+#define COMM_EVT_BRK_DLY_MS		100
+
+// Maximum number of characters to read from port at a time
+#define READ_BUF_LEN			4096
+
+// Set to 1 to record highest packet depth
+#define RECORD_PKT_DEPTH		1
+
+// Saturating incrementor
+#define ERRORCNT_MAX			1000000UL
+inline void INCREMENT_ERRORCNT(Uint32 &TheVariable)	{
+	TheVariable = (TheVariable<ERRORCNT_MAX) ? TheVariable+1
+											 : TheVariable;
+};
+
+//////////////////////////////////////////////////////////////////////
+//
+// CSerialEx - Win32 message-based wrapper for serial communications
+//
+// A lot of MS-Windows GUI based programs use a central message
+// loop, so the application cannot block to wait for objects. This
+// make serial communication difficult, because it isn't event
+// driven using a message queue. This class makes the CSerial based
+// classes suitable for use with such a message queue. Whenever
+// an event occurs on the serial port, a user-defined message will
+// be sent to a user-defined window. It can then use the standard
+// message dispatching to handle the event.
+//
+// Pros:
+// -----
+//	- Easy to use
+//	- Fully ANSI and Unicode aware
+//  - Integrates easily in GUI applications and is intuitive to
+//    use for GUI application programmers
+//
+// Cons:
+// -----
+//  - Uses a thread for each COM-port, which has been opened.
+//  - More overhead, due to thread switching and message queues.
+//  - Requires a window, but that's probably why you're using
+//    this class.
+//
+// Copyright (C) 1999-2003 Ramon de Klein
+//                         (Ramon.de.Klein@ict.nl)
+
+typedef enum _CserialMode
+{
+	SERIALMODE_SERIAL=0,
+	SERIALMODE_MERIDIAN_7BIT_PACKET
+}
+CSerialMode;
+
+//******************************************************************************
+// NAME																		   *
+// 	CSerialExErrReportInfo structure
+//
+// DESCRIPTION
+//  Serial Port status information.
+//
+//
+typedef struct  _CSerialExErrReportInfo {
+		Uint32 BREAKcnt;
+		Uint32 CTScnt;
+		Uint32 DSRcnt;
+		Uint32 ERR_FRAMEcnt;
+		Uint32 ERR_OVERRUNcnt;
+		Uint32 ERR_RXPARITYcnt;
+		Uint32 RINGcnt;
+		Uint32 RLSDcnt;
+		Uint32 RXCHARcnt;
+		Uint32 RXFLAGcnt;
+		Uint32 RX80FUllcnt;
+	// Reset value to zero
+	void clear() {
+		BREAKcnt=0;
+		CTScnt=0;
+		DSRcnt=0;
+		ERR_FRAMEcnt=0;
+		ERR_OVERRUNcnt=0;
+		ERR_RXPARITYcnt=0;
+		RINGcnt=0;
+		RLSDcnt=0;
+		RXCHARcnt=0;
+		RXFLAGcnt=0;
+		RX80FUllcnt=0;
+	};
+} CSerialExErrReportInfo;
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																		   *
+// 	rdBuf class
+//
+// DESCRIPTION
+//  A simple serial buffer with optional "ring buffer" debug buffer. It allows
+//	"bulk" updates via a block "read" function and sequential access to the
+//  items via a thread safe manner.
+//
+	#ifdef _DEBUG
+		#define DBG_RING_BUF 0			// Debug history buffer
+	#else
+		#define DBG_RING_BUF 0
+	#endif
+
+class rdBuf {
+public:
+	// Place to hold characters
+	CCCriticalSection m_lock;
+	char m_buffer[READ_BUF_LEN];
+	size_t m_head;			// Head of data index
+	size_t m_size;			// Size/tail of m_buffer contents
+	#if DBG_RING_BUF
+		int m_dbgPtr;
+		char m_ring[READ_BUF_LEN];
+	#endif
+	// State lock
+
+	// Kill the content
+	void flush() {
+		m_size = m_head = 0;
+		#ifdef _DEBUG
+			//memset(m_buffer, 0xff, READ_BUF_LEN);
+		#endif
+	};
+
+	// Set the buffer size to <newSize>
+	void makeAvailable(int newSize) {
+		#if DBG_RING_BUF
+		// Make debug copy
+		char *cp = &m_buffer[m_size];
+		for (int i=0; i<newSize; i++) {
+			m_ring[m_dbgPtr++] = *cp++;
+			m_dbgPtr &= (READ_BUF_LEN-1);
+		}
+		#endif
+		m_size += newSize;
+	};
+
+	// Return true if we have character(s)
+	bool hasChars() {
+		bool rVal;
+		rVal = m_head < m_size;
+		return(rVal);
+	};
+
+	// Return number of characters in the buffer
+	size_t charsInBuf() {
+		size_t rVal;
+		m_lock.Lock();
+		rVal = m_size-m_head;
+		m_lock.Unlock();
+		return(rVal);
+	};
+
+	// Return the number of characters we can put in the buffer
+	size_t charsLeft() {
+		size_t rVal;
+		rVal = READ_BUF_LEN - m_size;
+		return(rVal);
+	};
+
+	// Get pointer to end buffer
+	char *tailPtr() {
+		register char *pTheChar;
+		// Recycle buffer if we are empty
+		pTheChar = &m_buffer[m_size];
+		return(pTheChar);
+	};
+
+	// Get the next character
+	bool getChar(char &theChar) {
+		m_lock.Lock();
+		if (hasChars()) {
+			theChar = m_buffer[m_head++];
+			// Reset pointers when we got last group
+			if (!hasChars()) {
+				flush();
+			}
+			m_lock.Unlock();
+			return(true);
+		}
+		flush();
+		m_lock.Unlock();
+		return(false);
+	};
+
+	void lock() {
+		m_lock.Lock();
+	}
+
+	void unlock() {
+		m_lock.Unlock();
+	}
+
+	// Construct an empty buffer
+	rdBuf() {
+		flush();
+		#if DBG_RING_BUF
+		m_dbgPtr = 0;
+		#endif
+	};
+	#if _DEBUG
+	void dump() {
+		if (m_size>0) {
+			_RPT0(_CRT_WARN, "RdBuf: ");
+			for (size_t i = 0; i<m_size; i++) {
+				_RPT1(_CRT_WARN, "%02X_", m_buffer[i]);
+			}
+			_RPT0(_CRT_WARN, "\n");
+		}
+	}
+	#endif
+};
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+// 	CSerialEvt class
+//
+// DESCRIPTION
+//  This is a class that implements the serial port event dispatcher. The
+//	embedded thread will wait for the serial port to detect the arrival of
+//	data or the receive port break condition.
+//
+class CSerialEx;
+class CSerialEvt : protected CThread {
+private:
+	CSerialEx *pPort;						// Reference to our main port
+	bool m_paused;							// Set if paused
+	CCEvent m_parkAck;						// Signaled on initial park
+public:
+	CSerialEvt(CSerialEx *pOwner);
+	virtual ~CSerialEvt();
+	// Restart the event thread
+	void Restart() {
+		m_ThreadParkedEvent.SetEvent();
+	}
+	// Start/Stop API
+	void Start();
+	void Stop();
+	// Wait for loop to park.
+	void WaitForParked() {
+		m_parkAck.WaitFor();
+	}
+protected:
+	// Thread function
+	int Run(void *context);					// Thread Control function
+};
+
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+// 	CSerialEx class
+//
+// DESCRIPTION
+//  Provides a Meridian Packet Based interface to an asynchronous serial port.
+//
+// 	Each opened COM-port uses its own specific thread, which will
+// 	wait for one of the events to happen. When an event happens,
+// 	then the client window is send a message informing about the
+// 	event.
+//
+//
+class CSerialEx : public CSerial, protected CThread
+{
+// Construction
+public:
+	CSerialEx();
+	virtual ~CSerialEx();
+
+	typedef enum _ReadStates {
+		READ_STATE_IDLE=0,
+		READ_STATE_LP_PAYLOAD,
+		READ_STATE_HP_PAYLOAD,
+	} ReadStates;
+
+// Operations
+public:
+	// Open the numerically specified port for use
+	#if (defined(_WIN32)||defined(_WIN64))
+		virtual CSerial::SERAPI_ERR OpenComPort (long portNum);
+	#else
+		virtual CSerial::SERAPI_ERR OpenComPort (const char * portName);
+	#endif
+
+
+	// Close the serial port.
+	virtual CSerial::SERAPI_ERR Close (void);
+
+	// Connect the user's comm event to signal when packet is detected
+	void RegisterUserPktCommEvent(CCEvent *pUsersEvent);
+
+	// Operational mode: packets vs plain old serial
+	void SetMode(CSerialMode theNewMode);
+	CSerialMode GetMode(void);
+
+	// Packet Interface
+	bool GetPkt(packetbuf &buffer);
+	bool SendPkt(packetbuf &bufferLen);
+	bool IsPacketAvailable();
+
+	// Serial Port Interface
+	bool GetChar(char *theChar);
+	LONG GetCharsAvailable();
+	bool SendChars(char *theChars, unsigned int charsLen);
+	bool Send_Available();
+
+	// Port statistics
+	void ErrorReportClear();
+	void ErrorReportGet(CSerialExErrReportInfo *pErrorReport);
+private:
+	LONG m_nCharsRX;				// Receive character count
+	LONG m_nCharsTX;				// Transmit character count
+public:
+
+	// Get and clear receive character count
+	LONG ReceiveCount() {
+		LONG cnt = m_nCharsRX;
+		m_nCharsRX -= cnt;			// Atomic reset
+		return cnt;
+	}
+	// Get and clear transmit character count
+	LONG TransmitCount() {
+		LONG cnt = m_nCharsTX;
+		m_nCharsTX -= cnt;			// Atomic reset
+		return cnt;
+	}
+
+
+protected:
+	// Event handler
+	friend class CSerialEvt;
+	//virtual void OnEvent (EEvent eEvent, EError eError) = 0;
+	virtual __inline void cpymem(nodechar *src, nodechar *dest, nodeushort nchars);
+protected:
+	// The WaitEvent method is being used by this class internally
+	// and shouldn't be used by client applications. Client
+	// application should monior the messages.
+	using CSerial::CommEventWaitInitiate;
+
+	// The event-type is send in the WPARAM of the message and
+	// the GetEventType method returns the wrong data, so we'll
+	// hide this method for client applications to avoid problems.
+	using CSerial::GetEventType;
+	using CSerial::GetError;
+
+
+protected:
+	// - - - - - - - - - - - - - - - - - - - - - -
+	// Read Thread states and API
+	// - - - - - - - - - - - - - - - - - - - - - -
+	// Start the listener thread
+	virtual EPort StartListener (void);
+
+	// Stop the listener thread. Because the other thread might be
+	// busy processing data it might take a while, so you can specify
+	// a time-out.
+	virtual LONG StopListener (DWORD dwTimeout = INFINITE);
+
+	// Internal attributes
+	CCEvent *m_pUserCommInterrupt;
+	// Signalled when there is a packet received by the host.
+	// This application layer waits on this.
+	CCEvent m_responsePacketWaiting;
+
+	// Packets to send up to application layer
+	std::deque<packetbuf *> m_finishedPackets;
+
+	// Overlap structures for writing
+	CCEvent  m_evtWrOverlap;
+	// Size of last read event
+	#if _DEBUG
+		DWORD m_lastReadSize, m_maxReadSize;
+	#endif
+	#if RECORD_PKT_DEPTH
+		size_t m_maxDepth;
+	#endif
+	DWORD m_readSize;
+	#if RECORD_PKT_DEPTH
+public:
+	size_t MaxDepth() {
+		size_t maxD;
+		maxD = m_maxDepth;
+		m_maxDepth = 0;
+		return maxD;
+	}
+	#endif
+	// - - - - - - - - - - - - - - - - - - - - - -
+	// Virtual overrides of CSerial
+	// - - - - - - - - - - - - - - - - - - - - - -
+public:
+	CSerial::SERAPI_ERR Break (DWORD breakDurationMs)
+	{
+		m_breakSent = true;
+		return(CSerial::Break(breakDurationMs));
+	}
+
+	// - - - - - - - - - - - - - - - - - - - - - -
+	// Packet parser states
+	// - - - - - - - - - - - - - - - - - - - - - -
+private:
+	bool inHighPrioState() {
+		return(m_state == READ_STATE_HP_PAYLOAD);
+	}
+	// Low priority "next char" location
+	unsigned int m_lowPrioPktIndx;
+	// Accumulated checksum
+	unsigned int m_lowChecksum;
+	// High priority "next char" location
+	unsigned int m_hiPrioPktIndx;
+	// Accumulated checksum
+	unsigned int m_hiChecksum;
+	// Set when a break is sent, causes next Frame Error to be ignored
+	bool m_breakSent;
+	// WIP packets
+	packetbuf m_lowInProcPacket;
+	packetbuf m_hiInProcPacket;
+
+	unsigned m_strayCount;
+	bool m_AppPacketAvailable;
+
+	ReadStates m_state;
+	ReadStates m_pushedState;
+
+	// Reset the packet parser back to "idle" state.
+	void PacketParseReset() {
+		m_state = m_pushedState = READ_STATE_IDLE;
+		m_lowPrioPktIndx = m_hiPrioPktIndx = 0;
+		m_strayCount = 0;
+		ErrorReportClear();
+	}
+
+	// This function is used to process serial characters out of the
+	// m_rdBuffer and signal the upper packet loop we have something.
+	bool TestAndPushHiPacket(char nextChar);
+	void ProcessNextChar(char nextChar);
+public:
+	// Reset port items and work in progress
+	void Flush();
+
+	// - - - - - - - - - - - - - - - - - - - - - -
+	// Internal Packet based API and states
+	// - - - - - - - - - - - - - - - - - - - - - -
+	CCCriticalSection m_SendPacketToAppLock;
+
+	// Send a packet to the application
+	void SendPacketToApp(packetbuf &packet, BOOL convert7To8Bit);
+	// Create an error packet and send to the application
+	void SendErrToApp(mnNetErrs errorType, unsigned addr, unsigned data);
+	void convert7to8(packetbuf& inBuf, packetbuf& outBuf);
+	void convert8to7(packetbuf& inBuf, packetbuf& outBuf);
+
+//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// CThread implementation and state
+//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+private:
+	// This event is signalled when the thread is really running
+	CCEvent m_rdAck;
+	// Read Buffer filled by our thread
+	rdBuf m_rdBuffer;
+	// Set to have the thread ignore all data
+	bool m_rdAutoFlush;
+	// Things discovered during operations
+	CSerialExErrReportInfo m_ErrorReport;
+	// We are running in packet mode, else plain old serial mode
+	bool m_packetMode;
+	CSerialEvt *m_pSerialEvts;
+
+	// Thread Termination and cleanup
+	void TerminateAndWait();
+public:
+	// Tell read thread to ignore data when mode == true.
+	void AutoFlush(bool mode);
+	void ProcessEvent(EEvent what);
+
+protected:
+	int Run(void *context);					// Thread Control function
+};
+//																			   *
+//******************************************************************************
+
+#endif	// __SERIAL_EX_H
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/converterLib.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/converterLib.h
new file mode 100644
index 000000000..cd7f08cf4
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/converterLib.h
@@ -0,0 +1,126 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc-private/converterLib.h $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: converterLib.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	\brief Brief Module Description
+
+	
+**/
+// CREATION DATE:
+//		2012-03-14 14:27:44
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2012-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __CONVERTERLIB_H__
+#define __CONVERTERLIB_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	converterLib.h headers
+//
+	#include "tekTypes.h"
+	#include "pubMnNetDef.h"
+	#include "mnParamDefs.h"
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	converterLib.h function prototypes
+//
+//
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Common unit converters
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+double MN_DECL convertAcc(				// ticks/sample-time^2 <=> ticks/sec^2
+	nodebool valIsBits, 				// TRUE=>scaled, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData);
+
+double MN_DECL convertSquared(			// x^2 <=> x
+	nodebool valIsBits, 				// TRUE=>scaled, FALSE=>unscaled
+	multiaddr multiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData);
+
+double MN_DECL convertTimeMS(			// sample-times <=> milliseconds
+	nodebool valIsBits, 				// TRUE=>sample-times, FALSE=>ms
+	multiaddr multiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData);
+
+double MN_DECL convertVel(				// ticks/sample-time <=> ticks/sec
+	nodebool valIsBits, 				// TRUE=>ticks/sample-time, FALSE=>unscaled
+	multiaddr multiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData);
+
+// rounded for vel with no decimal places
+double MN_DECL convertVelRound(			// ticks/sample-time <=> ticks/sec 
+	nodebool valIsBits, 				// TRUE=>ticks/sample-time, FALSE=>unscaled
+	multiaddr multiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData);
+
+double MN_DECL limit2To27(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=> app bits
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// To/From value
+	byNodeDB *pNodeDB);
+
+// String utility functions
+void cleanForXML(char *pInputStr);
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	converterLib.h constants
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	converterLib.h static variables
+//
+// 
+
+//																			  *
+//*****************************************************************************
+
+
+
+#endif
+//============================================================================= 
+//	END OF FILE converterLib.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/cpmRegs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/cpmRegs.h
new file mode 100644
index 000000000..28f7fdbd8
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/cpmRegs.h
@@ -0,0 +1,289 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc-private/cpmRegs.h $
+// $Date: 01/24/2017 15:30 $
+// $Workfile: cpmRegs.h $
+//
+/// \file
+/// \brief C API: Private ClearPath-SC data structures
+//
+// NAME
+//		cpmRegs.h
+//
+// DESCRIPTION:
+///		This header file defines the private ClearPath_SC motor node registers.
+//
+// CREATION DATE:
+//		12/21/2011 
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2011-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			   *
+//******************************************************************************
+#ifndef __CPMREGS_H__
+#define	__CPMREGS_H__
+
+//******************************************************************************
+// NAME																		   *
+// 	cpmRegs.h constants
+
+//																			   *
+//******************************************************************************
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * MONITOR PORT SETTINGS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+#ifndef __TI_COMPILER_VERSION__             // Not needed on dsp
+
+// These are the same as Meridian ISC for now (TODO)
+typedef monTestPoints cpmMonVars;
+typedef iscTuneSyncs cpmTuneSyncs;
+
+// VB Friendly structure
+/**
+    \brief Monitor Port Settings structure.
+
+    This structure controls the selection of the diagnostic test points within
+    the drive.
+**/
+typedef struct _cpmMonState {
+    double          gain;       ///<  Gain setting
+    double          filterTC;   ///<  Output filter time constant (ms)
+    monTestPoints   var;        ///<  Test point to display
+    cpmTuneSyncs   tuneSync;   ///<  Is a bit field
+} cpmMonState;
+
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+typedef PACK_BYTES struct _cpmMonNodeState {
+    nodeushort      var;        // 16-bit variable selector
+    nodelong        gain;       // 32-bit gain
+    nodeshort       filter;     // 16-bit filter TC
+    nodeshort       tuneSync;   // 16-bit (should be bitfield)
+} cpmMonNodeState;
+#endif //not dsp
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * STIMULUS GENERATOR SETTINGS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+/// Stimulus mode types
+#if 0
+typedef enum _stimModes {
+    STIM_OFF    = 0,            ///<  Off
+    STIM_VEL    = 1,            ///<  Velocity toggle
+    STIM_TRQ    = 2,            ///<  Torque toggle
+    STIM_POSN   = 3,            ///<  Position toggle
+    STIM_CAL    = 4,            ///<  Calibrate/test value
+    STIM_MOVE_ONCE= 5,          ///<  Profiled single move
+    STIM_MOVE_RECP= 6,          ///<  Profiled reciprocating moves
+    STIM_MOVE_REPEAT= 7,        ///<  Repeated unidirection moves
+    STIM_REF_MAX
+} stimModes;
+#endif
+
+// Stimulus Request Packet Format used to create stimulus settings
+// and to extract stimulus state.
+
+typedef PACK_BYTES struct _cpmStimCmdPkt {
+    nodeshort       Mode;       // Operational mode
+    nodeshort       Period;     // Period in sample-times
+    nodelong        Amplitude;  // Amplitude in mode units
+    // - short form "classic" request end
+    nodeshort       Slew;       // Profiled slew sample-times
+    nodeshort       Dwell;      // Dwell sample-times
+    // - short form "profiled" request end
+    nodeshort       Status;     // Status bits (status request only)
+} cpmStimCmdPkt;
+#ifdef _MSC_VER
+#pragma pack(pop)
+#endif
+// Command sizes
+#define CP_STIM_CMD_PKT_PROF_SIZE (1+4*OCTET_SIZE(nodeshort)+OCTET_SIZE(nodelong))
+#define CP_STIM_CMD_PKT_SIZE (1+2*OCTET_SIZE(nodeshort)+OCTET_SIZE(nodelong))
+#define CP_STIM_CMD_STATUS_SIZE 1
+#define CP_STIM_RESP_STATUS_OCTETS 14
+
+// VB/C friendly stimulus request structure
+/**
+    \brief Stimulus Move Generator Settings structure.
+
+    This structure controls the internal tuning stimulus move generator.
+**/
+typedef struct _cpmStimState {
+    double          amplitude;  ///< Amplitude mode specific units
+    double          period;     ///< Stimulus period for "toggle" types
+    long            slew;
+    long            dwell;
+    long            bits;
+    stimModes       mode;       // Operational mode
+} cpmStimState;
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * DRIVE COMMAND NUMBERS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+typedef enum _cpmCmds {
+    SC_CMD_GET_PARAM = MN_CMD_GET_PARAM0,  // 0 Get parameter (bank 0)
+    SC_CMD_SET_PARAM = MN_CMD_SET_PARAM0,  // 1 Set parameter (bank 0)
+    SC_CMD_GET_PARAM1 = MN_CMD_GET_PARAM1, // 2 Get parameter (bank 1)
+    SC_CMD_SET_PARAM1 = MN_CMD_SET_PARAM1, // 3 Set parameter (bank 1)
+    SC_CMD_NODE_STOP  = MN_CMD_NODE_STOP,  // 4 E-stop (Node Stop, Stim Cancel)
+    SC_CMD_NET_ACCESS = MN_CMD_NET_ACCESS, // 5 Get net access level
+    SC_CMD_USER_ID = MN_CMD_USER_ID,       // 6 Get/Set the user ID
+    SC_CMD_CHK_BAUD_RATE = MN_CMD_CHK_BAUD_RATE, // 7 Get OK for proposed baud rate
+    SC_CMD_ALERT_CLR = MN_CMD_ALERT_CLR,   // 8 Clear non-serious Alert reg bits
+    SC_CMD_ALERT_LOG = MN_CMD_ALERT_LOG,   // 9 Read, clear, mark epoch of Alert log
+
+    // Start of node specific commands
+    SC_CMD_MOTOR_FILE=MN_CMD_COMMON_END,   // 16 Motor file name
+    SC_CMD_ADD_POSN=19,                    // 19 Adjust servo position
+    SC_CMD_ADD_POSN_LD,                    // 20 Adjust open loop load encoder
+    SC_CMD_SYNC_POSN,                      // 21 Synchronize position
+    SC_CMD_GET_SET_MONITOR,                // 22 Monitor port setting
+    SC_CMD_GET_SET_STIMULUS,               // 23 Stimulus settings
+    SC_CMD_RE_VECTOR,                      // 24 Reset the vector search
+    SC_CMD_DATA_ACQ,                       // 25 Data acquisition/scope feature
+    SC_CMD_TEST_GEN,                       // 26 Test Generator
+
+    // Short form position motion initiators
+    SC_CMD_MOVE_POSN_ABS=64+MG_MOVE_STYLE_NORM_ABS,// 64 Mv posn: abs
+    SC_CMD_MOVE_POSN_REL=64+MG_MOVE_STYLE_NORM,    // 65 Mv posn: relative
+    SC_CMD_MOVE_POSN_ABS_TRIG=64+MG_MOVE_STYLE_NORM_TRIG_ABS,// 66 Mv posn: abs
+    SC_CMD_MOVE_POSN_REL_TRIG=64+MG_MOVE_STYLE_NORM_TRIG,  // 67 Mv posn: relative
+    // Short form velocity motion initiator
+    SC_CMD_MOVE_VEL=68,                    // 68 Move velocity
+    SC_CMD_MOVE_VEL_TRIG,                  // 69 Move velocity
+
+    // Full feature motion initiator
+    SC_CMD_MOVE_POSN_EX,                   // 70 Move Posn: expanded
+    SC_CMD_MOVE_VEL_EX                     // 71 Move Velocity: expanded
+} cpmCmds;
+
+
+#ifndef __TI_COMPILER_VERSION__             // Skip DSP C problematic defs
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// POSITIONAL MOVE COMMANDS AND DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+// Expanded Profile move command format
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+typedef PACK_BYTES struct _cpmMoveProfiledExPacket {
+    int style                 : 8;  // Format of move (mgPosnStyle)
+    int value                 :32;  // Distance of the motion
+} cpmMovePosnExPacket;
+#ifdef _MSC_VER
+#pragma pack(pop)                   // Align to bytes boundaries
+#endif
+
+#endif // not dsp
+
+//                                                                            *
+//*****************************************************************************
+
+// Constants for RASgroup in option register
+#if 0 // TODO this model does not need this, causes compile issues
+enum RASOPT_LISTS {
+    RASOPT_AUTO = 0,                         // Automatically selected RAS
+    RASOPT_MANUAL_SK = 1,                   // Short Manual List
+    RASOPT_MANUAL_HP = 2,                    // Full Manual List
+    RASOPT_AUTO_FULL = 3                    // Auto RAS, but allow full list
+};
+
+// TODO: We will use isc list for here as these are the same DS 10/27/2015
+// RAS Constants for common settings
+enum CP_RAS_CODES {
+    CP_RAS_OFF = 0,                    // 0  OFF
+    CP_RAS_3MS,                        // 1  3 ms
+    CP_RAS_5MS,                        // 2  5 ms
+    CP_RAS_9MS,                        // 3  9 ms
+    CP_RAS_15MS,                       // 4  15 ms
+    CP_RAS_24MS,                       // 5  24 ms
+    CP_RAS_44MS                        // 6  44 ms
+};
+#endif
+
+//*****************************************************************************
+/**
+    \brief Encoder Quality Register.
+
+	This is the register used to quantify the encoder alignment quality when
+	the encoder is setup for the alignment mode and the motor is spun.
+**/
+typedef union _cpmEncQualReg {
+	Uint32	bits[6];						// Broad view
+	struct _Fld {
+		unsigned aEvents			: 4;	// A events
+		int							: 8;	//
+		int 	valid				: 1;	// Record is valid
+		int							: 3;
+		int		indexCount			: 4;	// Directional index count
+		unsigned iEvents			: 4;	// Indx Events
+		// Raw data (counts of CPU clocks)
+		int16	indexRise0;					// Rising index event from CAP1
+		int16	indexRise1;					// Rising index event from CAP3
+		int16	indexFall0;					// Falling index event from CAP2
+		int16	indexFall1;					// Falling index event from CAP4
+		int16	aRise0;						// Rising A event from CAP1
+		int16	aRise1;						// Rising A event from CAP3
+		int16	aFall0;						// Falling A event from CAP2
+		int16	aFall1;						// Falling A event from CAP4
+		int16   mechAngle;					// (mech angle) 2.14
+		int16	Pad;						// Extra padding
+	} Fld;
+	void reset() {
+		bits[0] &= ~0xFFFFL;
+	}
+} cpmEncQualReg;
+//                                                                            *
+//*****************************************************************************
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Number of bytes in each of these commands
+#define SC_CMD_MOVE_PROF_LEN       5
+#define SC_CMD_MOVE_SPLINE_LEN     10
+#define SC_CMD_MOVE_PROF_EX_LEN    5
+#define SC_CMD_MOVE_FLUSH_LEN      1
+#define SC_CMD_MOVE_VEL_EX_LEN     8
+#define SC_CMD_GET_PLA_LEN         2
+#define SC_CMD_SET_PLA_BASE_LEN        2       // + fuses
+#define SC_CMD_ADD_POSN_LEN            5
+#define SC_CMD_SYNC_POSN_LEN       1
+#define SC_CMD_GET_ACQUISITION_LEN 1
+#define SC_CMD_ACQUIRE_CONTROL_LEN 5
+
+// Velocity scaling factor
+#define SC_VEL_MOVE_SCALE (1LL<<MV_VEL_Q)  // Velocity scaling factor
+/// \endcond
+
+#ifndef __TI_COMPILER_VERSION__             // Not needed on dsp
+//******************************************************************************
+// NAME																		   *
+// 	cpmRegs.h function prototypes
+//
+// DESCRIPTION
+/**
+	\brief Internal prototypes.
+
+	Identifies the hardware configuration of the motor/drive.
+**/
+//
+// Initialize the parameter local copy of the parameter table
+cnErrCode cpmInitialize(
+			multiaddr theMultiAddr);
+
+cnErrCode cpmInitializeEx(
+			multiaddr theMultiAddr,
+			nodebool warmInitialize);
+//																			 *
+//****************************************************************************
+#endif //__TI_COMPILER_VERSION__
+#endif
+//============================================================================
+//	END OF FILE cpmRegs.h
+//============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/iscRegs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/iscRegs.h
new file mode 100644
index 000000000..3bd8d37e6
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/iscRegs.h
@@ -0,0 +1,125 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc-private/iscRegs.h $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: iscRegs.h $
+//
+/// \file
+/// \brief C API: Private Meridian data structures
+//
+// NAME
+//		iscRegs.h
+//
+// DESCRIPTION:
+///		This header file defines the private SST node registers.
+///		They handle all the drive and power supply products.
+//
+// CREATION DATE:
+//		12/23/2010 11:46:39
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2010-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			   *
+//******************************************************************************
+#ifndef __ISCREGS__H__
+#define	__ISCREGS__H__
+
+//******************************************************************************
+// NAME																		   *
+// 	iscRegs.h constants
+
+// Introduction of stepper, iex, enhanced RAS, PLA
+#define FW_MILESTONE_IEX 0x5200		
+// Had link voltage low counter
+#define FW_MILESTONE_LINK_LOW 0x5203
+// Had vector stepper
+#define FW_MILESTONE_VECTOR_STEEPER 0x5300
+// Had Software limits
+#define FW_MILESTONE_SOFT_LIMITS 0x5400
+// Had 32-bit RMS limit
+#define FW_MILESTONE_RMS_LIM_32 0x5403
+// Had skyline moves
+#define FW_MILESTONE_SKYLINE_MOVE 0x5500
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//  HwPlatform enum for the optionReg union
+//
+// DESCRIPTION
+/**
+	\brief Hardware platform enum for the option control register field.
+
+	Identifies the hardware configuration of the drive.
+**/
+//
+typedef enum _HwPlatform {
+	ISC9x_75V_DC,			//4xx and 5xx
+	ISC9x_300V_DC_Large,	//75x and 76x
+	ISC9x_300V_DC_Mid,		//60x, 62x, 72x, and 73x
+	ISC9x_75V_DC_Backplane	//2xx and 3xx
+} HwPlatform;
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+//  Structure for maintaining the monitor port's state.
+//
+// DESCRIPTION
+/**
+	\brief Hardware platform enum for the option control register field.
+
+	Identifies the hardware configuration of the drive.
+**/
+//
+typedef struct _monState {
+	bool		Set;					// Set if we have current data
+	iscMonVars	TestPoint;				// Current test point
+	double		FullScale;				// Full scale value for this TestPoint
+	_monState() {
+		Set=false;
+		TestPoint = MON_TRQ_CMD;
+		FullScale = 0;
+	}
+} monState;
+//																			   *
+//******************************************************************************
+
+// Place to put any by-node state in
+typedef struct _iscState {
+	monState	MonState;				// Monitor state information
+} iscState;
+
+
+//******************************************************************************
+// NAME																		   *
+// 	iscRegs.h function prototypes
+//
+// DESCRIPTION
+/**
+	\brief Internal prototypes.
+
+	Identifies the hardware configuration of the drive.
+**/
+//
+// Initialize the parameter local copy of the parameter table
+cnErrCode iscInitialize(
+			multiaddr theMultiAddr);
+
+cnErrCode iscInitializeEx(
+			multiaddr theMultiAddr,
+			nodebool warmInitialize);
+//																			 *
+//****************************************************************************
+
+#endif
+//============================================================================
+//	END OF FILE iscRegs.h
+//============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/lnkAccessAPI.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/lnkAccessAPI.h
new file mode 100644
index 000000000..e1a5a5f83
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/lnkAccessAPI.h
@@ -0,0 +1,570 @@
+//****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/lnkAccessAPI.h $
+// $Revision: 127 $ $Date: 12/09/16 1:46p $
+// $Workfile: lnkAccessAPI.h $
+//
+// DESCRIPTION:
+/**
+	\file 
+	\brief Definitions and function prototypes for the low
+	level setup functions used to set up Meridian links and serial port
+	access.
+
+	\ingroup SetupGrp
+	@{
+
+	This header file describes the public data types and API used
+	to access the link layer of the network.
+
+**/
+// 	The items in this file should also isolate platform specific 
+// 	implementations.
+//		
+//
+// CREATION DATE:
+//		2/11/1998 15:19:31 - was ioCore.h
+//		6/11/2008 10:11:00 - renamed lnkAccessAPI.h
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-1999, 2009-2018  Teknic, Inc.  All rights reserved.
+//		
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			 *
+//****************************************************************************
+
+#ifndef __LNKACCESSAPI_H__
+#define __LNKACCESSAPI_H__
+
+//***************************************************************************
+// NAME																		*
+// 	lnkAccessAPI.h headers
+//
+	#include "pubMnNetDef.h"
+	#include "mnErrors.h"
+	#include "mnDiags.h"
+
+	#include "pubCoreRegs.h"
+	#include "pubDataAcq.h"
+	#include "pubIscRegs.h"
+	#include "pubDataAcq.h"
+	#include "pubMotion.h"
+	#include "pubNetAPI.h"
+
+	#include <sys/types.h>
+	#include <sys/timeb.h>
+	#include "TeknicDevID.h"
+	#if defined(_WIN32)||defined(_WIN64)
+		#include <sys/types.h>
+		#ifndef MAX_PATH
+			 //#include "windows.h"
+		#endif
+ 	#else
+ 		#include <string.h>
+	#endif
+// 																	         *
+//****************************************************************************
+
+
+//***************************************************************************
+// NAME																		*
+// 	lnkAccessAPI.h constants
+//	
+//#define USE_ACTIVEX					// Define for ActiveX support
+/// \cond (INTERNAL_DOC||ISC_DOC)
+/// Extract the physical node address from multinet address selector
+#define NODE_ADDR(x) ((x)&(MN_API_MAX_NODES-1))
+/// Extracts the net number from the multinet address
+#define NET_NUM(multiAddr) (((multiAddr)/MN_API_MAX_NODES))
+/// Create a multinet address from a link number and physical address
+#define MULTI_ADDR(net, node) ((multiaddr)(((netaddr)(net))*MN_API_MAX_NODES)+(nodeaddr)(node))
+/// \endcond
+
+/// \cond INTERNAL_DOC
+// Unknown address marker
+const multiaddr MN_API_UNKNOWN_ADDR = (multiaddr)0xffffffff;
+
+// This list should match the TekNetLibX.NetAdapter list
+typedef enum NetworkChanges {
+    NODES_OFFLINE = 0,
+    NODES_ONLINE = 1,
+    NODES_RESETTING = 2,
+    NODES_SENDING = 3,
+    NODES_NO_NET_CONTROLLER = 4,
+    NODES_CHANGING_NET_CONTROLLER = 5,
+    NODES_NO_PORT = 6,
+    NODES_ONLINE_NO_TEST = 7,
+	NODES_FLASH_MODE = 8,
+	NODES_STOP_NET_CONFIG = 9,
+	NODES_BAUD_UNSUPPORTED = 10,
+	NODES_BAUD_CHANGING = 11,
+	NODES_DRIVER_ONLINE = 12
+} NetworkChanges;
+
+
+
+/// \endcond
+//																			  *
+//*****************************************************************************
+
+// 																	         *
+//****************************************************************************
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+//							   NODE/NET INFORMATION
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+/// \cond INTERNAL_DOC
+// This structure holds the serial port information.
+typedef struct _serPortInfo {
+	char mfg[64];
+	char adapter[64];
+} serPortInfo;
+/// \endcond
+
+#ifdef __cplusplus
+extern "C" {				// Use C linkage for wide flexibility of targets
+#endif
+
+/// \cond INTERNAL_DOC
+// Open the ports and setup for communications at standard speed
+MN_EXPORT cnErrCode MN_DECL infcStartController(
+		netaddr cNum);
+
+// Close down the communications port and release all resources
+MN_EXPORT cnErrCode MN_DECL infcStopController(
+		netaddr cNum);
+		
+// Reset the network speed to default rate		
+MN_EXPORT cnErrCode MN_DECL infcResetNetRate(
+		netaddr cNum);
+		
+// Set the network speed to given rate
+MN_EXPORT cnErrCode MN_DECL infcSetNetRate(
+		netaddr cNum,
+		netRates newRate);
+		
+// Main command/response execution API with logging.
+MN_EXPORT cnErrCode MN_DECL infcRunCommand(
+		netaddr cNum,						// Port index
+		packetbuf *theCommand,				// Ptr to buffered command
+		packetbuf *theResponse);			// Ptr to response area
+		
+// Microsecond level time stamp
+MN_EXPORT double MN_DECL infcCoreTime(void);
+
+// Millisecond level thread sleep function
+MN_EXPORT void MN_DECL infcSleep(Uint32 milliseconds);
+
+// Return TRUE if this network is online and able to communicate with nodes.
+MN_EXPORT nodebool MN_DECL infcOnline(
+		netaddr cNum);
+
+// Access standard error message strings for cnErrCodes.
+MN_EXPORT cnErrCode MN_DECL infcErrCodeStrA(
+	cnErrCode lookupCode,
+	Uint16 maxLen,
+	char resultStr[]);
+
+MN_EXPORT cnErrCode MN_DECL infcErrCodeStrW(
+	cnErrCode lookupCode,
+	Uint16 maxLen,
+	WCHAR resultStr[]);
+
+// Driver versioning information and location
+MN_EXPORT nodeulong MN_DECL infcVersion(void);
+MN_EXPORT void MN_DECL infcFileNameA(
+		char *fname, long len);
+		
+// Get port information about our controller
+MN_EXPORT cnErrCode MN_DECL infcGetPortInfo(
+		const char *portName, 
+		serPortInfo *portInfo);
+
+// Returns OS version string
+MN_EXPORT void MN_DECL infcOSversionW(
+		nodeulong strSize, 
+		nodeUNIstr pszOS);
+
+MN_EXPORT void MN_DECL infcOSversionA(
+		nodeulong strSize, 
+		char *pszOS);
+
+// Get the channel type for this controller
+MN_EXPORT mnNetSrcs MN_DECL infcGetNetSource(
+		netaddr cNum);
+
+// Get our thread ID
+MN_EXPORT Uint64 MN_DECL infcThreadID();
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// LOW LEVEL DRIVER ACCESS API
+//		These functions are generally used for diagnostics
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Flush all tracking and network data
+nodeulong MN_DECL infcFlush(
+		netaddr cNum);
+		
+// Low Level command transmission without tracking
+MN_EXPORT cnErrCode MN_DECL infcSendCommand(
+		netaddr cNum,					// Port Index
+		packetbuf *theCommand);			// Ptr to buffered command
+
+// Get Low Level logged response without tracking
+MN_EXPORT cnErrCode MN_DECL infcGetResponse(
+		netaddr cNum,					// Port Index
+		packetbuf *theResponse);		// Ptr to response area
+
+
+// Wait for all communications from this thread to stop
+void MN_DECL infcWaitForNetStop(netaddr cNum);
+
+// Get/Set Network Auto-Discovery mode
+MN_EXPORT cnErrCode MN_DECL infcSetAutoNetDiscovery(
+		netaddr cNum, 
+		nodebool AutoNetDiscovery);
+
+MN_EXPORT cnErrCode MN_DECL infcGetAutoNetDiscovery(
+		netaddr cNum, 
+		nodebool *AutoNetDiscovery);
+
+// Control the background polling thread
+MN_EXPORT cnErrCode MN_DECL infcBackgroundPollControl(
+		netaddr cNum,
+		nodebool start);
+
+// Set the cmd queue limit for the network
+MN_EXPORT cnErrCode MN_DECL infcSetCmdQueueLimit(
+		netaddr cNum,				// Network 
+		nodeulong nCmds);			// Number of commands allowed at once
+		
+MN_EXPORT cnErrCode MN_DECL infcGetOnlineState(
+		netaddr cNum,
+		nodebool *state);
+
+// Return expert online state
+MN_EXPORT cnErrCode MN_DECL infcGetOnlineStateEx(
+		netaddr cNum,
+		openStates *state);
+				
+// Low level packet formatter for the network set address command
+cnErrCode MN_DECL infcSetAddressFmt(
+		nodeulong startingAddr,		// Net address start here
+		packetbuf *theCmd);
+
+MN_EXPORT nodelong MN_DECL infcDbgDepth(netaddr cNum);
+
+// Get serial port stats
+MN_EXPORT cnErrCode MN_DECL infcSerialStats(
+		netaddr cNum, 
+		nodeulong &rxCnt, 
+		nodeulong &txCnt,
+		nodeulong &rxPktCnt,
+		nodeulong &txPktCnt);
+
+// NOTE: nc aka cNum and node address are long for ActiveX alignment and compatibility
+// reasons.
+typedef struct _packetbuf18 {
+	int32 bufferSize;
+	nodechar buffer[18];
+} packetbuf18;
+
+///\endcond
+/**
+	Error Callback information
+**/
+typedef struct _infcErrInfo { 
+	
+	Uint32 cNum;			///< Controller reporting error
+	Uint32 node;			///< Node on that network
+	cnErrCode errCode;		///< Error code reported
+	packetbuf18 response;	///< Command that caused error
+} infcErrInfo;
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// DIAGNOSTICS & CONTROL INTERFACES
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+///\cond INTERNAL_DOC
+// Command Trace Interface
+// Trace enable/disable
+MN_EXPORT void MN_DECL infcSetTraceEnable(
+		netaddr cNum, 
+		nodebool newState);
+///\endcond
+// Save information / UNICODE filename
+MN_EXPORT cnErrCode MN_DECL infcTraceDump(
+		netaddr cNum, 
+		const wchar_t *filePath);
+
+// Save information / ANSI filename
+MN_EXPORT cnErrCode MN_DECL infcTraceDumpA(
+		netaddr cNum, 
+		const char *filePath);
+
+// Get errors self-reported from nodes
+MN_EXPORT cnErrCode MN_DECL infcGetBackgroundErrs(
+	multiaddr theMultiAddr,
+	nodebool *pIsSet,
+	mnNetDiagStats *pResult);	
+
+// Get errors detected at host port		
+MN_EXPORT cnErrCode MN_DECL infcGetHostErrStats(
+	netaddr cNum,
+	nodebool *pIsSet,
+	mnNetDiagStats *pResult);
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// C EVENT CALLBACKS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+
+// Provides callbacks on the following events:
+//	* On network error detected 
+//	* After response from command detected
+//  * On a node's parameter being changed, signifing that the local cache
+//	  should be invalidated
+//	* Network Online/Offline state change
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Callback function definitions
+							  
+// ---------------------
+// On Parameter Change
+///\cond INTERNAL_DOC
+
+// Callback types for status and parameter value changes
+// Parameter change info block. NOTE: node and net are not necessarily the
+// same as internal types due to VB/C structure aligment issues.
+typedef struct _mnParamChg {
+	double newValue;				// New "numeric" value
+									// NOTE: VB/C aligment forces double first
+	nodeulong node;					// Node registering change (multiAddr)
+	nodeulong net;					// Net registering change
+	nodeparam paramNum;				// Parameter changing
+} mnParamChg;
+
+typedef void (nodeCallback *paramChangeFunc)
+				(const mnParamChg *chgItem);
+
+///\endcond
+// ---------------------
+/**
+	\typedef infcErrCallback
+	\brief Error Callback Function Type
+
+	The #infcSetErrorFunc registers a function of this type that will
+	be called whenever the S-Foundation detects an error.
+**/
+typedef void (nodeCallback *infcErrCallback)(
+						infcErrInfo *infcErrInfo);
+						
+MN_EXPORT infcErrCallback MN_DECL infcSetErrorFunc(
+	  		infcErrCallback newFunc);				// Ptr to callback function
+
+// ---------------------
+// Post-command execution
+
+///\cond INTERNAL_DOC
+// Information returned by the completion function. Provides central
+// statistics for QC and tuning purposes.
+typedef struct _mnCompletionInfo {
+	packetbuf cmd;					///< Original command if known, else NULL
+	packetbuf *pResp;				///< Response if known, else NULL
+	double execTime;				///< Execution time less pacing
+	double pacedTime;				///< Executoon time inclusive of pacing
+	double sendTime;				///< Time required to send command
+	double rxTime;					///< Time required to get response
+	nodeulong ringDepth;			///< Ring depth
+	long spare[4];					// Padding for future
+	#ifdef __cplusplus
+	// Construction initialization
+	_mnCompletionInfo() {
+		pacedTime = rxTime = execTime = sendTime = 0;
+		ringDepth = 0;
+		pResp = NULL;
+		spare[0] = spare[1] = spare[2] = spare[3] = 0;
+	};
+	#endif
+} mnCompletionInfo;
+
+typedef void (nodeCallback *infcCmdCompleteCallback)(
+						netaddr cNum,
+					    const mnCompletionInfo *pStats);
+					    
+MN_EXPORT infcCmdCompleteCallback MN_DECL infcSetCmdCompleteFunc(
+	  		infcCmdCompleteCallback newFunc);	// Ptr to callback function
+
+// ---------------------
+// Change of parameter; need to invalidate cache
+
+typedef void (nodeCallback *infcInvalCacheCallback)(
+						netaddr cNum,
+					    nodeaddr node);
+					    
+MN_EXPORT infcInvalCacheCallback MN_DECL infcSetInvalCacheFunc(
+	  		infcInvalCacheCallback newFunc);	// Ptr to callback function
+
+// ---------------------
+// Change of network state
+typedef void (nodeCallback *infcNetStateCallback)(
+						netaddr cNum,
+						nodebool online);
+						
+MN_EXPORT infcNetStateCallback MN_DECL infcSetNetStateFunc(
+	  		infcNetStateCallback newFunc);		// Ptr to callback function
+
+
+
+// ---------------------------------
+// BRAKE INTERFACE API
+// ---------------------------------
+
+// Direct user control of the indicated brake number
+// NOTE: If the brake mode is not set to BRAKE_AUTOCONTROL the
+//			auto-brake feature will not have control of the brake
+MN_EXPORT cnErrCode MN_DECL infcBrakeControlSet(
+		netaddr cNum,
+		size_t brakeNum,
+		BrakeControls brakeMode);
+
+MN_EXPORT cnErrCode MN_DECL infcBrakeControlGet(
+		netaddr cNum,
+		size_t brakeNum,
+		BrakeControls *pBrakeMode);
+
+MN_EXPORT cnErrCode MN_DECL infcGlobalStopGet(
+	netaddr cNum,
+	nodebool *pEngaged);
+
+// When theNode becomes disabled, engage the indicated brake number
+MN_EXPORT cnErrCode MN_DECL infcAutoBrakeSet(
+		netaddr cNum,
+		size_t brakeNum,
+		nodebool enabled,
+		multiaddr theMultiAddr);
+
+MN_EXPORT cnErrCode MN_DECL infcAutoBrakeGet(
+		netaddr cNum,
+		size_t brakeNum,
+		nodebool *pEnabled,
+		multiaddr *pTheMultiAddr);
+
+
+MN_EXPORT cnErrCode MN_DECL infcCommUnitPowered(
+		netaddr cNum,
+		nodebool *pIsPowered);
+
+
+
+// ---------------------------------
+// NODESTOP ON SHUTDOWN API
+// ---------------------------------
+// If any of the nodes in the group have a event included in the mask
+// send the specified nodestop type to each of the nodes in the group
+// setting the mask
+// NOTE: This feature waits for all shutdown conditions to clear to re-arm
+
+MN_EXPORT cnErrCode MN_DECL infcShutdownInfoSet(
+		multiaddr theAddr,
+		const ShutdownInfo *pTheInfo);
+
+MN_EXPORT cnErrCode MN_DECL infcShutdownInfoGet(
+		multiaddr theAddr,
+		ShutdownInfo *pTheInfo);
+
+MN_EXPORT cnErrCode MN_DECL infcShutdownInitiate(
+		netaddr cNum);
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// DATA ACQUISITION INTERFACE. 
+// Provide a polled data acquisition FIFO interface. This needs to be
+// VB friendly.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+		
+MN_EXPORT cnErrCode MN_DECL infcGetDataAcqPt(
+		multiaddr multiAddr, 
+		nodeulong ptsToRead, 
+		mnDataAcqPt pTheDataAcqPt[],
+		nodeulong *pPtsRead);
+		 
+MN_EXPORT cnErrCode MN_DECL infcGetDataAcqPtCount(
+		multiaddr multiAddr, 
+		nodeulong *pPointCount);
+		
+MN_EXPORT cnErrCode MN_DECL infcFlushDataAcq(
+		multiaddr multiAddr);
+/// \endcond
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// ATTENTION (NET INTERRUPT) INTERFACE. 
+// Provide a polled interface for getting the oldest attention request.
+// This needs to be VB friendly.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+
+// Detected Attention Packet Function
+MN_EXPORT cnErrCode MN_DECL infcNetGetAttnReq(
+		netaddr cNum,								// Channel number
+		mnAttnReqReg *pAttnReq);					// Ptr Oldest request copy
+
+// Flush all attentions detected so far
+MN_EXPORT cnErrCode MN_DECL infcNetAttnFlush(
+		netaddr cNum);								// Channel number
+		
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// VB POLLED INTERFACE. 
+// This is necessary to provide thread safe interface with this ActiveX 
+// client which want's to Apartment Marshall anything we want to do and 
+// can only serially processes Events and Function calls in a way that can
+// lead to dead-lock.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+/// \cond INTERNAL_DOC
+// Polled error interface
+MN_EXPORT nodebool MN_DECL infcGetNextError(
+			netaddr cNum, 
+			infcErrInfo *pErrInfo);
+// Polled net change interface
+MN_EXPORT nodebool MN_DECL infcGetNextNetChange(
+			netaddr cNum, 
+			NetworkChanges *pNetChange);
+// Polled param changed check interface
+MN_EXPORT nodebool MN_DECL infcParamsHaveChanged(
+			multiaddr multiAddr);
+
+// Polled autonomous error reporting interface
+MN_EXPORT cnErrCode MN_DECL infcGetNetErrorStats(
+	multiaddr theMultiAddr,			// Node to lookup
+	nodebool *pIsSet,				// Updated to TRUE if set
+	mnNetDiagStats *pResult);		// Result area				
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// DEBUGGING INTERFACE
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Check heap for corruption
+MN_EXPORT void MN_DECL infcHeapCheck(const char *msg);
+// Force unload of the library
+MN_EXPORT bool MN_DECL infcUnloadLib();
+/// \endcond
+#ifdef __cplusplus
+}
+#endif
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// NATIVE C++ INTERFACE
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+#ifdef __cplusplus
+#include <vector>
+#include <string>
+// Return a list of SC hubs currently connected
+MN_EXPORT cnErrCode MN_DECL infcGetHubPorts(
+		std::vector<std::string> &comHubPorts);
+#endif
+
+/// @}
+#endif //ifndef __LNKACCESSAPI_H__
+// 																			   *
+//******************************************************************************
+
+//============================================================================== 
+//	END OF FILE lnkAccessAPI.h
+//==============================================================================
+ 
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/lnkAccessCommon.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/lnkAccessCommon.h
new file mode 100644
index 000000000..e8940b3eb
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/lnkAccessCommon.h
@@ -0,0 +1,1088 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/inc-private/lnkAccessCommon.h $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: lnkAccessCommon.h $
+//
+// DESCRIPTION:
+///		\file
+///		This file contains the platform independent definitions and data for
+///		a Meridian node network.
+//
+// CREATION DATE:
+//		01/29/2010 16:05:21
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2010-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+/// \cond INTERNAL_DOC
+
+#ifndef __LNKACCESSCOMMON_H__
+#define __LNKACCESSCOMMON_H__
+//*****************************************************************************
+// !NAME!																      *
+// 	lnkAccessCommon.h headers included
+//
+	#ifndef DOXYGEN_SHOULD_SKIP_THIS
+		// StdLib inclusions
+		#include <queue>
+		// Our inclusions
+		#include "tekTypes.h"
+		#include "tekThreads.h"
+		#include "mnParamDefs.h"
+		#include "lnkAccessAPI.h"	
+		#include "pubSysCls.h"
+		#include "pubCpmCls.h"
+	#endif
+//																			  *
+//*****************************************************************************
+
+// Just need a pointer to this
+class CSerialEx;
+
+//*****************************************************************************
+// !NAME!																	  *
+// 	lnkAccessCommon.h constants
+//
+// Depth of the polled error event list
+#define ERR_CNT_MAX 			8
+// Depth of the polled network event list
+#define NET_EVENTS_MAX 			64
+// Trace Dump file "type" number in the header. Change if the header changes
+#define DUMP_TYPE_RANGE_STEP	100				// Groups of compatible files
+// V2 style, Meridian. Less than this are ControlPoint style files
+#define DUMP_TYPE_NUM_V2_BASE	200				// V2 style
+// V3 style/packed trace records
+#define DUMP_TYPE_NUM_V3_BASE	(DUMP_TYPE_NUM_V2_BASE+DUMP_TYPE_RANGE_STEP)
+// Current version number, change if file structure changes
+#define DUMP_TYPE_NUM			DUMP_TYPE_NUM_V3_BASE
+
+// Depth of the Trace Buffer for sent commands
+#define SEND_DEPTH				4096
+// Depth of the Trace Buffer for received responses
+#define RECV_DEPTH				SEND_DEPTH
+// Depth of the Attention Buffer. Add one more than this will yield overflow.
+#define ATTN_OVERFLOW_LVL		32
+// Depth of the Data Acquisition buffer at each node.
+#define DATAACQ_OVERFLOW_LVL	2000
+// Number of simultaneous command in ring default
+#define N_CMDS_IN_RING			3
+
+// XML based error text
+#define LNK_ACCESS_XML_ERR_TXT "/MNuserDriver20.xml"
+
+void DUMP_PKT(netaddr cNum, const char *msg, packetbuf *buf, bool backArrow=false);
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	mnClassInfo structure
+//
+// DESCRIPTION
+//	A node class information structure. It stores the counts the count of this
+//  type of node as well the addresses on this network where they exist.
+//
+// Holds the count and addresses on a network where these nodes live.
+EXTERN_C typedef struct _mnClassInfo {
+	nodeulong count;				// Count of nodes
+	multiaddr node[MN_API_MAX_NODES];// List of nodes found
+} mnClassInfo;
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	autoBrakeInfo structure
+//
+// DESCRIPTION
+//	This structure sets which node (if enabled is true) will control the
+//	.
+//
+typedef struct _autoBrakeInfo{
+	nodebool enabled;
+	multiaddr theNode;
+	BrakeControls brakeMode;
+}autoBrakeInfo;
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	txTraceBuf & rxTraceBuf tracing structures
+//
+// DESCRIPTION
+//	These structures hold the.
+//
+// Forward references
+typedef struct _respTrackInfo respTrackInfo;
+typedef struct _respNodeList  respNodeList;
+
+#if defined(_MSC_VER)||defined(__GNUC__)
+#pragma pack(push, 1)
+#endif
+// Transmission Traces (V3)
+typedef struct _txTraceBuf {
+	double timeStamp;			// Time command sent to NC
+	Uint32 order;				// Send serial number
+	Uint32 depth;				// Queue depth
+	packetbuf packet;			// Copy of the command sent
+	nodebool failed;			// Failed send
+	Uint16 pad;					// Pad to 60 bytes(dword)
+#ifdef __cplusplus
+	_txTraceBuf() {
+		timeStamp = 0;
+		order = 0;
+		depth = 0;
+		failed = 0;
+		pad = 0;
+	}
+#endif
+} txTraceBuf;
+
+// Reception Traces (V3)
+typedef struct _rxTraceBuf {
+	double timeStamp;			// Time response received
+	Uint32 sendCnt;				// By node count
+	Uint32 sendSer;				// Assumed sender serial number
+	Uint32 order;				// By network response count
+	packetbuf packet;			// Copy of the response received
+	Uint32  __pad;				// Unused (padding to preserve aligment)
+	cnErrCode error;			// Error code of result
+#ifdef __cplusplus
+	_rxTraceBuf() {
+		timeStamp = 0;
+		sendCnt = 0;
+		sendSer = 0;
+		order = 0;
+		__pad = 0;
+		error = MN_OK;
+	}
+#endif
+} rxTraceBuf;
+#if defined(_MSC_VER)||defined(__GNUC__)
+#pragma pack(pop)
+#endif
+// Version 2 "unpacked" buffers for trace dumps
+// Transmission Traces
+typedef struct _txTraceBuf200 {
+	double timeStamp;			// Time command sent to NC
+	Uint32 order;				// Send serial number
+	Uint32 depth;				// Queue depth
+	packetbuf packet;			// Copy of the command sent
+	nodebool failed;			// Failed send
+#ifdef __cplusplus
+	_txTraceBuf200() {
+		timeStamp = 0;
+		order = 0;
+		depth = 0;
+		failed = 0;
+	}
+#endif
+} txTraceBuf200;
+
+// Reception Traces
+typedef struct _rxTraceBuf200 {
+	double timeStamp;			// Time response received
+	Uint32 sendCnt;				// By node count
+	Uint32 sendSer;				// Assumed sender serial number
+	Uint32 order;				// By network response count
+	packetbuf packet;			// Copy of the response received
+	txTraceBuf *cmd;			// Matched command
+	cnErrCode error;			// Error code of result
+#ifdef __cplusplus
+	_rxTraceBuf200() {
+		timeStamp = 0;
+		sendCnt = 0;
+		sendSer = 0;
+		order = 0;
+		cmd = NULL;
+		error = MN_OK;
+	}
+#endif
+} rxTraceBuf200;
+//
+//	This structure defines the header of the trace dump file.
+//
+#if defined(_MSC_VER)||defined(__GNUC__)
+#pragma pack(push, 1)
+#endif
+#define TRACE_FILEPATH_LEN	260
+typedef struct _traceHeader {
+	Uint32 hdrLen;					// Header length
+	Uint32 type;					// Trace type
+	Uint32 numOfNodes;				// Number of nodes
+	Uint32 traceLen;				// Number of trace records
+	Uint32 nextRXrecord;			// Next trace record
+	devID_t nodeTypes[MN_API_MAX_NODES];	// Node types
+	Uint32 version;					// Driver version
+	Uint32 kernVersion;				// Kernel version
+	Uint32 pad32;
+	// Time trace was saved
+	#if (defined(_WIN32)||defined(_WIN64))
+		struct _timeb timestamp;
+	#else
+		// Time stamp compatible with Windows
+		struct _timeb {
+		        Uint64 time;
+		        Uint16 millitm;
+		        int16 timezone;
+		        int16 dstflag;
+				Uint16 pad;			// Align to Win32 version
+		} timestamp;
+	#endif
+	Uint32 nextTXrecord;			// Next TX trace item
+	Uint32 nTXrecords;				// Number of TX records
+	Uint32 nRXrecords;				// Number of RX records
+	mnNetDiagResults diags;			// Diagnostic results
+	char filename[TRACE_FILEPATH_LEN];	// DLL path used
+} traceHeader;
+#if defined(_MSC_VER)||defined(__GNUC__)
+#pragma pack(pop)
+#endif
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	mnNetInvRecords structure
+//
+// DESCRIPTION
+//	This structure holds the overview of a channel's inventory of nodes and the
+//	serial port specification.	There are one of these structures per serial 
+//	port.
+//
+class netStateInfo;			// Forward reference
+class mnNetInvRecords {
+public:
+	// This structure holds this network's locations and types of nodes
+	// detected upon enumeration. It is used to aid in locating nodes and 
+	// for determining if the configuration changed.
+	struct _netInfoByType {
+		bool isValid;
+		// Total # nodes on this port
+		nodeulong NumOfNodes;
+		// Number of Meridian Drives
+		mnClassInfo mnDrvInfo;
+		// ClearPath Motors
+		mnClassInfo mnClearPathInfo;
+		// ClearPath SC Motors
+		mnClassInfo mnCpScInfo;
+		// Last device ID set
+		devID_t LastIDs[MN_API_MAX_NODES];	
+		// Construction
+		_netInfoByType() {
+			isValid = false;
+		}
+	};
+
+	// ---------------------------------
+	// Tracing State
+	// ---------------------------------
+	nodebool TraceArmed;				// If set dump file will create on error
+	nodebool TraceActive;				// Tracing enabled
+	nodebool TraceActiveReq;			// Tracing enable request
+	Uint32 TraceCount;					// Count of automatic dumps attempted this session
+	Uint32 sendSerNum;					// Sending serial number
+	Uint32 respSerNum;					// Receive serial number
+	txTraceBuf *txTraces;				// Trace buffer SEND_DEPTH deep
+	size_t txTraceIndx;
+	rxTraceBuf *rxTraces;				// Trace buffer RECV_DEPTH deep
+	size_t rxTraceIndx;
+	CCCriticalSection TXlogLock;		// Transmit log critical section
+	CCCriticalSection RXlogLock;		// Receive log critical section
+	// Record in the log file what we sent and when
+	unsigned logSend(
+				packetbuf *cmd,
+				cnErrCode theErr,
+				double timeStamp);
+	// Record in the log file what we received and when
+	double logReceive(
+				packetbuf *readBuf,
+			    cnErrCode theErr,
+			    respTrackInfo *fillInfo,
+			    double timeStamp);
+
+	// - - - - - - - - - - - - - - - -//
+	// == Net Specific Information == //
+	// - - - - - - - - - - - - - - - -//
+	// Disposable state information
+	netStateInfo *pNCS;
+	// Current node information, value caches, construction/destruction
+	byNodeDB NodeInfo[MN_API_MAX_NODES];
+	// Set when something was discovered for diagStats
+	nodebool diagsAvailable[MN_API_MAX_NODES+1];
+	// Autonomously delivered stats
+	mnNetDiagStats diagStats[MN_API_MAX_NODES+1];
+	// The diagnostics are running; Prevent RunCommand from running if this is set
+	nodebool NetDiagBlock;				// Blocks diagnostics on this net
+	cnErrCode NetDiagLastResult;		// Last network diagnostic result
+	cnErrCode OfflineRootErr;			// Offline root error
+	nodeaddr OfflineErrNode;			// Node reporting root error
+	nodebool brake0Saved;				// Brake states at close time
+	nodebool brake1Saved;
+
+	// Port specifier: speed, number, etc.
+	portSpec PhysPortSpecifier;
+	// Number of simultaneous commands allowed in ring
+	nodeulong NumCmdsInRing;
+
+	// Initializing "stack"	counter. Maintained by infcSetInitializeMode.
+	// When this counter decrements back to zero, we signal we are "online",
+	// likewise when we increment from zero we go "offline". This accounting
+	// is necessary to allow internal and external usage of the diagnostic
+	// functions and prevents extraneous and premature "online" signalling.
+	int16 Initializing;
+	// Controls if auto discovery is allowed
+	nodebool AutoDiscoveryEnable;
+	// Controls if the "keep alive" poll is allowed
+	nodebool KeepAlivePollEnable;
+	// State to restore the "keep alive" poll to when we go online
+	nodebool KeepAlivePollRestoreState;
+
+	// - - - - - - - - - - - - - - - -//
+	// == By Node Type Information == //
+	// - - - - - - - - - - - - - - - -//
+	// Current information
+	struct _netInfoByType InventoryNow;
+	// Information saved when net went online
+	struct _netInfoByType InventoryLast;
+
+	// Current attention states
+	attnReg drvrAttnMask[MN_API_MAX_NODES];
+	attnReg attnMask[MN_API_MAX_NODES];
+	nodeulong attnCleanupMask[MN_API_MAX_NODES];
+	// Flag to suppress attentions during setups
+	int16 attnInitializing;
+
+	// - - - - - - - - - - - - - - - -//
+	// == State for class library  == //
+	// - - - - - - - - - - - - - - - -//
+	// Pointer to our shadow class library representation
+	sFnd::IPort *pPortCls;
+	// Serial port online state for class library
+	openStates OpenState;
+	openStates OpenStateLast;
+	// Set next open state
+	void OpenStateNext(openStates next);
+	// Connection Type and status
+	mnNetStatus AccessInfo[MN_API_MAX_NODES];
+	// Nodes class instances
+	sFnd::INode *pNodes[MN_API_MAX_NODES];
+
+	// - - - - - - - - - - - - - - - - - - - - //
+	// ==  User Driver Feature Information  == //
+	// - - - - - - - - - - - - - - - - - - - - //
+
+	// - - - - - - - - - - - - - - - - - - - - -
+	// Auto-brake feature state for ClearPath-SC
+	// - - - - - - - - - - - - - - - - - - - - -
+	// Maximum brakes for this controller
+	static const size_t MAX_BRAKES = 2;
+	// Information related to the auto-brake
+	typedef struct _autoBrakeInfo {
+		nodebool enabled;						// Brake is enabled to run
+		multiaddr relatedNode;					// Controlling node
+		BrakeControls brakeMode;				// Brake mode
+		// Construct a auto-controleld, unassigned brake
+		_autoBrakeInfo() {
+			enabled = true;
+			brakeMode = BRAKE_AUTOCONTROL;
+			relatedNode = MN_UNSET_ADDR;
+		}
+	} autoBrakeInfo;
+	// State recorded from API
+	autoBrakeInfo autoBrake[MAX_BRAKES];
+	// Setup the brake state to current node/net state.
+	void setupBrakes();
+
+	// - - - - - - - - - - - - - - - - - - - - -
+	// NodeStop on Status Event feature
+	// - - - - - - - - - - - - - - - - - - - - -
+	// When set, we will generate shutdown on next poll cycle
+	nodebool GroupShutdownRequest;
+	// State recorded from user API
+	ShutdownInfo GroupShutdownInfo[MN_API_MAX_NODES];
+	// This is the last sample of the CTS line whose rise
+	// edge causes can cause a group shutdown.
+	nodebool GroupLastExtRequest;
+
+	// Clear our counts and validity
+	void clearNodes(bool portIsClosed);
+	// Construct as cleared, dormant.
+	mnNetInvRecords();
+	~mnNetInvRecords();
+	// Returns true if serial port is open
+	bool PortIsOpen() 
+	{
+		return OpenState == FLASHING
+			|| OpenState == OPENED_SEARCHING
+			|| OpenState == OPENED_ONLINE;
+	}
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	profileStats structure
+//
+// DESCRIPTION
+//	This structure holds time profiling information used to evaluate efficiency.
+typedef struct _profileStats {
+	// Command Timing
+	double cmdSendTime;
+	double cmdSendTimeMax;
+	unsigned cmdsSent;
+	double cmdSendTimeSum;
+	// Response Timing
+	double respTime;
+	double respTimeMax;
+	unsigned responses;
+	double responseTimeSum;
+	// Read Thread Info
+	unsigned readIterations;
+	unsigned readsPerformed;
+	double readsPerfSum;
+	double readIterSum;
+	double readWaitSum;
+	double readTToLockSum;
+	double readTToStartSum;
+	unsigned readTToStartCount;
+	// Run Command Stats
+	double tToSend;
+	double tAfterSend;
+	double tToDeferExit;
+	double tToWaitExit;
+} profileStats;
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	dataAcqInfo structure
+//
+// DESCRIPTION
+//	This structure a node's data acquisition information.
+//
+typedef struct _dataAcqInfo {
+	// Interface Lock
+	CCCriticalSection AcqLock;
+	// Point not transferred to application
+	std::queue<mnDataAcqPt> Points;
+	// Sequence check
+	nodelong SeqCheck;
+	// Set when have lost samples in Points
+	nodebool Overflow;
+	// Samples since the start of acquisition
+	nodeulong SampleCount;
+	// The time between samples
+	double SampRateMilliSec;
+	// Construction initialization
+	_dataAcqInfo() {
+		SampRateMilliSec = 0;
+		SeqCheck = 0;
+		Overflow = FALSE;
+		SampleCount = 0;
+	}
+} dataAcqInfo;
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	respTrackInfo & respNodeList structure
+//
+// DESCRIPTION
+//	Command and Response tracking
+//
+//  This is a command response tracking database element. After a command is
+//	sent the information in this structure is used to copy the response to the
+//	waiting thread and signal its restart.
+typedef struct _respTrackInfo {
+	struct _respTrackInfo *next;		// Ptr to next response waiting thread
+	nodebool bufOK;						// TRUE if the buf has data
+	packetbuf *buf;						// User's response location
+	// This event blocks the commanding thread from running until
+	// the response is detected.
+	CCEvent evtRespWait;
+	Uint32 sendSerNum;					// Sending serial number
+	Uint32 nSentAtAddr;					// sendCnt for this node
+	double cmdStartAt;					// Time-stamp at start of infcSendCommand
+	double funcStartAt;					// Time-stamp at start of infcRunCommand
+	mnCompletionInfo stats;				// Command completion statistics
+	// Construct an empty tracking info record
+	_respTrackInfo() {
+		bufOK = false;
+		buf = NULL;
+		next = NULL;
+		sendSerNum = nSentAtAddr = 0;
+		cmdStartAt = 0;
+	}
+} respTrackInfo;
+
+// This is the main by-node tracking database element. It holds the list of
+// expected responses for a particular node as well as error information and
+// some by-node statistics.
+typedef struct _respNodeList {
+	respTrackInfo *head;				// Head (oldest) waiter on the net
+	respTrackInfo *tail;				// Tail (newest) waiter on the net
+	packetbuf errPkt;					// Error packet
+	Uint32 sendCnt;						// Sending count
+	Uint32 respCnt;						// Receive count
+	// Construct an empty by node tracker
+	_respNodeList() {
+		head = tail = NULL;
+		sendCnt = respCnt = -1;
+		errPkt.Byte.BufferSize = 0;
+	}
+} respNodeList;
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	autoDiscoverThread class
+//
+// DESCRIPTION
+//		This is a thread that attempts to detect nodes across the serial port 
+//		and bring them back online.
+//
+class netStateInfo;							// Forward reference
+class autoDiscoverThread : public CThread {
+private:
+	// This flag forces discover to park at halt state because we have found
+	// our network working again.
+	nodebool m_goneOnline;
+	// This flag reflects the parked status of the thread.
+	nodebool m_parked;
+	// This flag causes our discovery loop to exit
+	nodebool m_exitDiscovery;
+	// Our net context
+	netStateInfo *pNCS;
+	// The error that caused us to start
+	cnErrCode m_faultingErr;
+
+	// Internal operations sync event, used for starting and stopping
+	// the thread for diagnostics and other purposes.
+	CCEvent m_InternalSync;
+	// This is the interlocking event for cross thread handshaking
+	CCEvent m_InternalSyncAck;
+
+	// Run control interlocks
+	CCCriticalSection m_critSect;
+
+public:
+	autoDiscoverThread();
+	~autoDiscoverThread();
+
+	// Returns TRUE if Running
+	nodebool IsRunning() {
+		return(!m_parked && !Terminating());
+	}
+
+	// Force the autodiscover back to halted state
+	void Halt();
+
+	// Start node discovery process
+	void Start(cnErrCode theErr);
+
+	// Override terminate to allow proper exit
+	HANDLE Terminate();
+
+	// Override terminate and wait to insure proper exit
+	void TerminateAndWait();
+
+	// Wait for thread to park
+	void WaitUntilParked() {
+		if (m_parked)
+			return;
+		m_InternalSyncAck.WaitFor();
+	}
+
+	// Autodiscover loop running. We are allowed to keep
+	// waiting for network recovery if this is true.
+	bool WaitingForNet() ;
+
+
+protected:
+	int Run(void *context);					// Control function
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	readPktThread class
+//
+// DESCRIPTION
+//		This is a thread that waits for packets to arrive from the serial port
+//		and allows blocked threads waiting for responses to restart or
+//		other internal functions to start due to their arrival.
+//
+class netStateInfo;							// Forward reference
+class readPktThread : public CThread {
+public:
+	// Read thread states
+	typedef enum _readThreadStates {
+		READ_UNKNOWN,						// 0 Unknown state
+		READ_RUNNING,						// 1 Thread is running
+		READ_HALT_REQ,						// 2 Halt is requested/pending
+		READ_HALTED,						// 3 Thread is halted
+		READ_SHUTDOWN_REQ,					// 4 Shutdown requested/pending
+		READ_SHUTDOWN						// 5 Thread has exited
+	} readThreadStates;
+
+private:
+	readThreadStates m_state;				// Running state
+	readThreadStates m_lastState;			// Last state for debugging
+	// Internal operations sync event, used for starting and stopping
+	// the thread for diagnostics and other purposes.
+	CCEvent m_InternalSync;
+	// This is the interlocking event for cross thread handshaking
+	CCEvent m_InternalSyncAck;
+	CCCriticalSection ReadLock;				// Internal structure lock
+	CCCriticalSection StartStopLock;		// Internal structure lock
+	netStateInfo *pNCS;						// Our net context
+
+public:
+	// Construction/Destruction
+	readPktThread();
+	~readPktThread();
+
+	// Start/Stop API
+	void Start();
+	void Stop();
+	void ForceStop();
+
+	// Change read thread state
+	void NextState(readThreadStates nextState);
+
+	// State Info
+	nodebool IsRunning() {
+		return(m_state == READ_RUNNING);
+	}
+
+protected:
+	int Run(void *context);				// Control function
+
+private:
+	//void constructInit(netStateInfo *state);
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPollerThread	class
+//
+//  CREATION DATE:
+//		2014-05-21 11:29:40
+//
+//	DESCRIPTION:
+/**		
+	This class defines a class that periodically polls the device ID from 
+	node 0. This insures a net disconnect is timely reported and in the
+	case of VB apps, prevents the watchdog timer from prematuring expiring
+	during UI stalls.
+
+**/
+//	SYNOPSIS:
+class netStateInfo;
+class netPollerThread : public CThread 
+{
+private:
+	// This is the interlocking event for cross thread handshaking
+	CCEvent m_InternalSyncAck;
+	// If this is set, the polling can run
+	CCEvent m_RunControl;
+	CCCriticalSection m_critSection;		// Internal structure lock
+	netStateInfo *pNCS;						// Our net context
+	// Set when halted
+	bool m_halted;
+
+public:
+	// Construction/Description
+	netPollerThread(netStateInfo *pTheNetInfo);
+	~netPollerThread();
+
+	// CThread overrides for terminate
+	void *Terminate();
+
+	// Start/Stop API
+	void Start();
+	void Stop();
+	// Returns true if halted and parked
+	bool Halted() {
+		return m_halted;
+	}
+protected:
+	int Run(void *context);				// Control function
+
+private:
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	netStateInfo class
+//
+// DESCRIPTION
+//	By network specific state information. It contains the
+//	statistics as well as the response tracking databases. This remains a
+//	structure for compatibility with the C API.
+//
+class netStateInfo {
+public:
+	// Event switch managed by the cmdsIdleEvt class. 
+	CCEvent CmdsIdle;					// Signalled when cmds idle
+	CCatomicUpdate m_cmdsInPlay;
+	// RAII mechanism to prevent premature destruction of state by resetting
+	// the CmdsIdle event when commands are in play. It should be created
+	// in the infcRunCommand function to track the ports command activity.
+	class cmdsIdleEvt {
+	private:
+		netStateInfo &m_netState;
+		CCEvent &m_event;
+	public:
+		cmdsIdleEvt(netStateInfo &myNetState) :
+			m_netState(myNetState), m_event(myNetState.CmdsIdle)
+		{
+			m_netState.m_cmdsInPlay.Incr();
+			m_event.ResetEvent();
+		}
+		~cmdsIdleEvt() {
+			if (m_netState.m_cmdsInPlay.Decr()==0) {
+				m_event.SetEvent();
+			}
+		}
+	};
+	netaddr cNum;						// Port index number
+	// Serial Port Instance for this network
+	CSerialEx *pSerialPort;
+	// Read Thread to read all pending packets from the serial interface.
+	readPktThread ReadThread;
+	// Overall port and network state
+	mnNetSrcs OurNetConnector;			// Port this net is connected to
+	// Set this to cause all threads to terminate
+	nodebool SelfDestruct;				// Net wide self-destruct flag
+
+	nodeulong nRespOutstanding;			// Number of responses waiting
+	nodeulong nPktsSent;				// Number of packets sent
+	nodeulong nPktsRcvd;				// Number of packets received
+
+	size_t ErrListHeadPtr;				// Error head ptr
+	size_t ErrListTailPtr;				// Error tail ptr
+	infcErrInfo ErrList[ERR_CNT_MAX];	// Error circular list
+	int errorRecursePrevent;			// Set to prevent error callback recursion
+
+	// Net change circular list. This contains the last set of network changes 
+	// for use by polled systems.
+	size_t NetChgListHeadPtr;			// Net change list head ptr
+	size_t NetChgListTailPtr;			// Net change list tail ptr
+	NetworkChanges LastEvent;			// Last network change
+	NetworkChanges NetChgList[NET_EVENTS_MAX];
+	CCCriticalSection NetChgListLock;	// Network change lock
+
+	// This holds the "I've been changed" signal from the firmware until any 
+	// polled apps that would care (ie, APS) ask for it; this is
+	// basically a list of clear-on-read bits
+	nodebool paramsHaveChanged[MN_API_MAX_NODES];
+
+	nodeulong RingCmdsMax;				// Max # of simultaneous cmds in ring
+	CCSemaphore CmdPaceSemaphore;		// Command pacing semaphore
+#ifdef _DEBUG
+	long	SemaCount;
+#endif
+	CCCriticalSection cmdLock;			// Command/Response data Lock
+
+	// Interrupt events
+	CCEvent IrqEvent;					// IRQ event signaller
+	CCEvent ReadCommEvent;				// Read pacing signaller
+	CCEvent GroupShutdownEvent;			// Group Shutdown signaller
+
+	Uint32 ctsCount;
+
+	// ---------------------------------
+	// Diagnostics State
+	// ---------------------------------
+	CCEvent CmdGate;					// Spin-out gate for user cmds
+
+	// ---------------------------------
+	// Auto-Discovery State
+	// ---------------------------------
+	autoDiscoverThread *pAutoDiscover;	// Thread to support auto-discovery
+
+	// ---------------------------------
+	// Command Tracking State
+	// ---------------------------------
+	// These are the command tracking information records
+	// They contain house keepers, events and tracking info. They are assigned 
+	// via the pTrkTail pointer.  When the tracking is complete it is
+	// put back at the tail.
+	respTrackInfo **pTrkFixedList;		// Ptr to pTrkInfo ptrs
+	respTrackInfo **pTrkList;			// Ptr to pTrkInfo ptrs
+	respTrackInfo **pTrkTail;			// Ptr to available tracker
+	respNodeList respNodeState[MN_API_MAX_NODES];
+	respNodeList controlNodeState;
+
+
+	CCCriticalSection IOlock;			// ISC-TG I/O RMW lock
+	CCCriticalSection ErrListLock;		// Error lock
+
+
+	// ---------------------------------
+	// Attention Interface state
+	// ---------------------------------
+	CCCriticalSection AttnLock;			// Attention buffer lock
+	std::queue<mnAttnReqReg> AttnBuf;		// Buffer of attentions from the ring
+	nodebool AttnOverrun;				// Set on attention loss
+
+	// ---------------------------------
+	// Data Acquisition Interface
+	// ---------------------------------
+	dataAcqInfo DataAcq[MN_API_MAX_NODES];
+	// This flag causes the sequence checker to initialize on
+	// first packet.
+	nodebool DataAcqInit[MN_API_MAX_NODES];
+
+	// ---------------------------------
+	// Channel activity generator
+	// ---------------------------------
+	// Polling thread to insure network watchdog is refreshed when online
+	netPollerThread *pPollerThread;
+	Uint32 pollDelayTimeMS;
+
+	// ---------------------------------
+	// Construct or destroy our instance
+	// ---------------------------------
+	netStateInfo(nodeulong nRingCmdsMax, netaddr cNum);
+	~netStateInfo();
+
+	// ---------------------------------
+	// PUBLIC API
+	// ---------------------------------
+
+	// Command/Response Data Structure lock
+	void enterCmdLock();
+	void exitCmdLock();
+
+	// Inquire if current thread is a recovery or finding nodes thread.
+	nodebool isRecoveryThread();
+
+	// Inquire if current thread is the read thread.
+	nodebool isReadThread();
+
+	// Tracking data base maintainence
+	void removeThisDBitem(
+				respTrackInfo *pRespInfo,
+				respNodeList *pRespArea);
+
+	void removeHeadDBitem(
+				respNodeList *pRespArea);
+
+	// Waits for network traffic to complete without sending any data
+	void waitForIdle();
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	lnkAccessCommon.h function prototypes
+//		These are all C style interfaces
+//
+#ifdef __cplusplus
+extern "C" {
+#endif
+//
+	// ---------------------------------
+	// PACKET ORIENTED INTERFACES
+	// ---------------------------------
+	// Low Level logged command transmission without tracking
+	cnErrCode MN_DECL infcSendCommandLog(
+			nodeushort cNum,						// Port Index
+			packetbuf *theCommand);			    // Ptr to buffered command
+
+	// ---------------------------------
+	// CALLBACK INTERFACES
+	// ---------------------------------
+
+	// Internal function to fire off the error callback
+	void infcFireErrCallback(
+			infcErrInfo *errInfo,
+			bool forced = false);
+
+	// Internal function to fire off the network state callback
+	void infcFireParamCallback(
+			paramChangeFunc func,
+			const mnParamChg *chgItem);
+
+	// Internal function to fire off when the network state changes
+	void infcFireNetEvent(
+			netaddr cNum,
+			NetworkChanges newState);
+
+	// ---------------------------------
+	// SERIAL INTERFACE DIAGNOSTICS
+	// ---------------------------------
+
+	// Set/get the physical port number and speed related to this controller
+	cnErrCode MN_DECL infcSetPortSpecifier(
+			netaddr cNum,
+			const portSpec *pPortNumber	// Port Specification
+	);
+	cnErrCode MN_DECL infcGetPortSpecifier(
+			netaddr cNum,
+			portSpec *pPortNumber			// Port Specification
+	);
+
+	// Control and monitor snoop of other network
+	void infcSetOtherNetSnoop(
+			netaddr cNum,
+			nodebool TheDTRValue);
+	void infcGetOtherNetSnoop(
+			netaddr cNum,
+			nodebool *TheDTRValue);
+
+	// Run the network/flow break diagnostic
+	cnErrCode infcBrokenRingDiag(
+			netaddr cNum,
+			nodebool foundNodes,
+			unsigned nodeCount);
+
+	// Scan through the LastKnown network and search for offline nodes
+	// issuing error codes.
+	cnErrCode infcProbeForOffline(
+			netaddr cNum,
+			nodeulong *nNodes);
+
+	// Flush network via a set of NoOp packets and clear any responses out
+	Uint32 infcFlushProc(
+			netaddr cNum);
+
+
+	// ---------------------------------
+	// BRAKE INTERFACE API
+	// ---------------------------------
+	// Low level function for controlling the brake
+	cnErrCode infcBrakeSet(
+			netaddr cNum,
+			size_t brakeNum,
+			nodebool engaged,
+			nodebool forced=false);
+	cnErrCode infcBrakeGet(
+			netaddr cNum,
+			size_t brakeNum,
+			nodebool *pEngaged,
+			nodebool forced=false);
+
+
+	cnErrCode MN_DECL infcSetDiagBlock(
+			netaddr cNum,
+			nodebool state);
+
+	cnErrCode MN_DECL infcGetDiagBlock(
+			netaddr cNum,
+			nodebool *state);
+
+	// Start the auto network node discovery thread
+	void MN_DECL infcStartAutoNetDiscovery(
+			netaddr cNum,
+			cnErrCode initialError);
+
+	// Halt the auto network node discovery thread
+	void MN_DECL infcHaltAutoNetDiscovery(
+			netaddr cNum);
+
+	// Returns activity status of auto-discover process
+	nodebool infcAutoDiscoverRunning(netaddr cNum);
+
+	// ---------------------------------
+	// TRACE DUMP MANAGEMENT
+	// ---------------------------------
+	// Created next dump file
+	cnErrCode infcTraceDumpNext(
+			netaddr cNum);
+
+	// Returns a string terminated with directory delimiter for
+	// automatically generated dump files. For Windows
+	// this directory is "%TEMP%\Teknic\".
+	void infcGetDumpDir(
+			char *pStr,						// Ptr to string area
+			nodelong maxLen);				// Maximum size of string area
+
+
+	// ---------------------------------
+	// RECORD KEEPING & SETUP
+	// ---------------------------------
+	// Register <inventory> as the last inventory
+	cnErrCode infcUpdateInventory(
+			netaddr cNum,
+			mnNetInvRecords *inventory);
+	cnErrCode infcInitDataAcq(
+			multiaddr multiAddr,
+			double SampleRateMicroSec);
+	// Provides stacked online/offline support each
+	// initializing==true must be balanced with a
+	// initializing==false and the lastErr==some code. If
+	// stack unwind==0 and lastErr==MN_OK we go online.
+	cnErrCode MN_DECL infcSetInitializeMode(
+			netaddr cNum,
+			nodebool initializing,
+			cnErrCode lastErr);
+	cnErrCode MN_DECL infcGetInitializeMode(
+			netaddr cNum,
+			nodebool *initializing);
+
+	// Set the port connection to node's net
+	void infcSetNetSource(
+			netaddr cNum,
+			mnNetSrcs theConnector);
+
+	// ---------------------------------
+	// PARAMETER STATE LOCK INTERFACE
+	// ---------------------------------
+
+	// Register transaction locks
+	void infcGetIOlock(netaddr cNum);
+	void infcReleaseIOlock(netaddr cNum);
+
+#ifdef __cplusplus
+}
+#endif
+//																			  *
+//*****************************************************************************
+#endif
+/// \endcond
+
+//=============================================================================
+//	END OF FILE lnkAccessCommon.h
+// ============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/meridianHdrs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/meridianHdrs.h
new file mode 100644
index 000000000..b5ca86915
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/meridianHdrs.h
@@ -0,0 +1,124 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/meridianHdrs.h $
+// $Revision: 45 $ $Date: 12/09/16 1:47p $
+// $Workfile: meridianHdrs.h $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief Master C/C++ Header File for Meridian Projects.
+
+	This header file defines Meridian technology globally relevant
+	constants and functions. Include just this file in your project
+	using the Meridian library.
+**/
+//
+// CREATION DATE:
+//		10/29/1998 14:04:19
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//                                                                             *
+//******************************************************************************
+
+#ifndef __MERIDIANHDRS_H__
+#define __MERIDIANHDRS_H__
+
+//******************************************************************************
+// NAME                                                                        *
+// 	meridianHdrs.h headers
+//
+#include "tekTypes.h"
+#include "pubMnNetDef.h"
+#include "pubCoreRegs.h"
+#include "pubDataAcq.h"
+#include "pubMotion.h"
+
+#include "lnkAccessAPI.h"
+#include "netCmdAPI.h"
+#include "pubIscRegs.h"
+#include "pubIscAPI.h"
+#include "pubIex.h"
+#include "pubCpmAdvAPI.h"
+//                                                                             *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME                                                                        *
+// 	meridianHdrs.h function prototypes
+//
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//||||||||||||||||||||||||||||||||||||
+// MULTINET INITIALIZATION INTERFACE
+//||||||||||||||||||||||||||||||||||||
+
+// Main System initialization
+MN_EXPORT cnErrCode MN_DECL mnInitializeNets(
+			nodebool resetNodes,		// Set to reset nodes on init
+			nodeulong netCount,			// Number of nets to initialize (1..2)
+			const controllerSpec controllers[]); // Ptr to controller list
+
+// Return the node count of <device> type nodes on all initialized nets.
+MN_EXPORT cnErrCode MN_DECL mnSysInventoryCount(
+			nodeIDs deviceType,		// Which device type
+			nodeulong *pCount);		// Ptr to result
+
+// Return the node addresses of <device> type nodes on all initialized nets.
+MN_EXPORT cnErrCode MN_DECL mnSysInventoryRecord(
+			nodeIDs deviceType,		// Which device type
+			nodeulong maxDevices,	// Maximum number of devices in list
+			multiaddr devices[]);	// Ptr to result list
+
+// Return the count of all nodes on the system.
+MN_EXPORT cnErrCode MN_DECL mnSysNodeCount(
+			nodeulong *pCount);		// Ptr to result area
+
+// Return the node count of the specified <device> on the specified net.
+MN_EXPORT cnErrCode MN_DECL mnNetInventoryCount(
+			netaddr cNum,			// Network number
+			nodeIDs deviceType,		// Which device type
+			nodeulong *pCount);
+
+// Return the node addresses of <device> type nodes on the specified net.
+MN_EXPORT cnErrCode MN_DECL mnNetInventoryRecord(
+			netaddr cNum,			// Network number
+			nodeIDs deviceType,		// Which device type
+			nodeulong maxDevices,	// Maximum number of devices in list
+			multiaddr devices[]);	// Ptr to result list
+
+// Return the count of all nodes on the specified net.
+MN_EXPORT cnErrCode MN_DECL mnNetNodeCount(
+			netaddr cNum,			// Net to inquire about
+			nodeulong *pCount);		// Ptr to result area
+
+// Release all network ports and resources
+MN_EXPORT cnErrCode MN_DECL mnShutdown();
+
+// Attempt to restart the specified network
+MN_EXPORT cnErrCode MN_DECL mnRestartNet(
+	netaddr cNum, 					// Controller to restart
+	nodebool restartNodes = FALSE);
+
+// Attempt to restart the specified node
+MN_EXPORT cnErrCode MN_DECL mnRestartNode(
+	multiaddr addr);
+
+#ifdef __cplusplus
+}
+#endif
+//                                                                             *
+//******************************************************************************
+
+#endif
+//==============================================================================
+//	END OF FILE meridianHdrs.h
+//==============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/mnDiags.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/mnDiags.h
new file mode 100644
index 000000000..da8f5bef8
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/mnDiags.h
@@ -0,0 +1,149 @@
+//***************************************************************************
+// $Header:: /ClearPath SC-1.0.123/User Driver/inc/mnDiags.h 10    12/09/16  $
+//
+// NAME
+//		mnDiags.h
+//
+// DESCRIPTION:
+//		MachineNet diagnostic API elements
+//
+// CREATION DATE:
+//		12/10/2003 20:14:37
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2003-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+/***************************************************************************/
+
+#ifndef _MNDIAGS_H
+#define _MNDIAGS_H
+
+
+//***************************************************************************
+// NAME																        *
+// 	mnDiags.h headers
+//																			*/
+	#include "pubMnNetDef.h"
+	#include "pubNetAPI.h"
+	#include "mnErrors.h"
+/***************************************************************************/
+
+
+
+
+//***************************************************************************
+// NAME																	    *
+// 	mnDiags.h function prototypes
+//
+//
+
+/***************************************************************************/
+
+
+
+//***************************************************************************
+// NAME																	    *   
+// 	mnDiags.h constants
+//
+//
+
+/***************************************************************************/
+
+
+
+//***************************************************************************
+// NAME																	    *
+// 	mnDiags.h static variables
+//
+// 
+
+// Flow control diagnostic information
+//typedef struct _mnFlowStats {
+//	double maxFCin;					// Maximum time in flow control in
+//	double maxFCout;				// Maximum time flow control asserted
+//} mnFlowStats;
+
+/// Network error statistics for a single port on a single node
+typedef struct _mnNetErrStatsSinglePort {
+	nodeulong nFragPkts;			// Number of fragmented packets
+	nodeulong nChecksumBad;			// Number of badly checksumed packets
+	nodeulong nStrayChars;			// Number of stray data characters	
+	nodeulong nOverflows;			// Number of overflow events
+	void clear() {
+		nFragPkts = nChecksumBad = nStrayChars = nOverflows = 0;
+	}
+	_mnNetErrStatsSinglePort() {
+		clear();
+	}
+} mnNetErrStatsSinglePort;
+
+/// Network error statistics for a single network
+typedef struct _mnNetErrStats {
+	/// Errors detected on the application channel.
+	mnNetErrStatsSinglePort ApplicationPort;
+	/// Errors detected on the diagnostic channel.
+	mnNetErrStatsSinglePort DiagnosticPort;
+	/// Count of network brown-outs events detected.
+	nodeulong LowPowerEvents;		
+	/// Clear the statistics
+	void clear() {
+		ApplicationPort.clear();
+		DiagnosticPort.clear();
+		LowPowerEvents = 0;
+	}
+	/// Construct a cleared instance
+	_mnNetErrStats() {
+		clear();
+	}
+} mnNetErrStats;
+
+
+typedef enum _mnTestResult {
+	NET_TEST_UNTESTED,				// 0 Test not run (state unknown)
+	NET_TEST_PASSED,				// 1 Test passed
+	NET_TEST_FAILED					// 2 Test failed
+} mnTestResult;
+
+// Network Diagnostic Result information
+typedef struct _mnNetDiagResult {
+	// Raw Data Area
+	mnNetErrStats lastErrs;			// Last error report
+	cnErrCode collectCode;			// Error return of last collection cycle
+	// Accumulated Data
+	mnNetErrStats accumErrs;		// Last error report
+	// Results Area
+	mnTestResult netOK;				// Network test result
+#ifdef __cplusplus
+	_mnNetDiagResult() {
+		collectCode = MN_OK;
+		lastErrs.clear();
+		accumErrs.clear();
+		netOK = NET_TEST_UNTESTED;
+	}
+#endif
+} mnNetDiagResult;
+
+// Network Diagnostic Result information   (NOTE: This must match VB version)
+#pragma pack(push,1)
+typedef struct _mnNetDiagResults {
+	// Result area
+	mnNetDiagResult node[MN_API_MAX_NODES];
+	// Time Stamps
+	double startTime;				// Time @ last clear/initialization
+	double sampleTime;				// Time last sample occurred
+	nodeulong nSamples;				// Number of samples accumulated
+	// Network break diagnostic results
+	cnErrCode lastBreakDiag;		// Result of the last break diagnostic
+	cnErrCode breakDiag;			// Last non-MN_OK error
+} mnNetDiagResults;
+#pragma pack(pop)
+
+#endif
+//=========================================================================== 
+//	END OF FILE mnDiags.h
+//===========================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/mnParamDefs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/mnParamDefs.h
new file mode 100644
index 000000000..b0b382695
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/mnParamDefs.h
@@ -0,0 +1,819 @@
+//******************************************************************************
+// $Archive: /ClearPath SC/User Driver/inc/mnParamDefs.h $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: mnParamDefs.h $ 
+//
+// DESCRIPTION:
+/**
+	\file
+	\cond INTERNAL_DOC
+	\brief
+		Parameter managment API definitions. This includes common "unit" 
+		and parameter type definitions.
+
+	\ingroup ISCgrp
+	@{
+**/ 		
+//
+// CREATION DATE:
+//		02/13/1998 12:46:56 - as netCore.h
+//		06/11/2009 10:22:00 - renamed for Meridian family
+//																	  	 !-8!
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998, 2009-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+//																			   *
+////****************************************************************************
+
+#ifndef __MNPARAMDEFS_H__
+#define __MNPARAMDEFS_H__
+
+/**************************************************************************** 
+ * !NAME!																    *
+ * 	mnParamDefs.h headers
+ *																		!0! */
+#include "lnkAccessAPI.h"
+#include <assert.h>
+/* 																	   !end!*
+ ****************************************************************************/
+
+
+
+
+/****************************************************************************
+ * !NAME!																	*
+ * 	mnParamDefs.h types
+ * 																		    */
+/* Command Set Constants */
+#define RESP_STATUS_LEN 2			// Length of common response items (status)
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+	\brief Unit Type codes.
+
+	These code provide access to the desired units for a value.
+**/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef enum _unitTypes {
+	NO_UNIT,						// No intrinsic unit
+	BIT_FIELD,						// Value is a bit field
+	DX_TICK,						// Distance: the encoder tick
+	DX_INCH,						// Distance: inches
+	DX_MM,							// Distance: millimeters
+	DX_REV,							// Distance: revolution
+	VOLT,							// Voltage in volts
+	CURRENT,						// Current in amperes
+	TIME_S,							// Time in seconds
+	TIME_MSEC,						// Time in milliseconds
+	TIME_USEC,						// Time in microseconds
+	TIME_SAMPLE,					// Time in sample times
+	VEL_TICK_MSEC,					// Velocity is encoder counts / ms
+	VEL_TICK_MSEC2,					// Acceleration is encoder counts / ms^2
+	VEL_TICK_SAMPLE,				// Velocity is encoder counts / sample time
+	VEL_TICK_SAMPLE2,				// Acceleration is encoder counts / sample time^2
+	VEL_STEPS_S,					// Velocity is steps / second
+	VEL_STEPS_MS,					// Velocity is steps / millisecond
+	VEL_RPM,						// Velocity is revolutions per minute
+	VEL_RPS,						// Velocity is revolutions per second
+	VEL_IPS,						// Velocity is inches per second
+	VEL_MMPS,						// Velocity is mm per second
+	STRING8,						// String value	(fixed 8 bytes)
+	OSTRING,						// OLESTR
+	FW_VERS,						// Firmware version structure
+	HW_VERS,						// Hardware version structure	
+	DEV_ID,
+	IOC_HZ,							// IOC filter corner frequency
+	UNIT_HZ,						// Frequency in Hz
+	DEG_C,
+	VOLTS_PER_KRPM,
+	HOURS,
+	STRING,
+	DEGREES,
+	VEL_TICKS_S,					// Velocity in ticks/sec
+	VEL_TICKS_S2,					// Acceleration in ticks/sec^2
+	PERCENT_MAX,
+	TIME_MIN,						// Time in minutes
+	} unitTypes;
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+	\brief Parameter types codes
+
+	These codes describe the parameter type from the host's perspective.
+	The type is a bit oriented value made up of basic types. They tell
+	the driver and user how access to the parameter will be treated. For
+	example PT_RT will ignore the cached indicator and cause another
+	transfer from the node upon request. Non PT_RT will normal only read
+	the node's value once and return the cached copy.
+**/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef enum _paramTypes {
+	// Base type bits
+	PT_NONE,						///<  Parameter is not present
+	PT_RO=1,						///<  Read only parameter
+	PT_VOL=2,						///<  Volatile R/W parameter
+	PT_NV=4,						///<  Non-volatile R/W parameter
+	PT_RT=8,						///<  Real-time non-cached value
+	PT_CLR=16,						///<  Clear on read type
+	PT_RAM=32,						///<  RAM R/W type
+	PT_ADV=64,						///<  Exists in advanced models
+	PT_IN_NODE_CFG=128,				///<  In node section of cfg file
+	PT_IN_MTR_CFG=256,				///<  In motor section of cfg file
+	PT_IN_ALL_CFG=512,				///<  Extended config in drive section
+	PT_IN_FACT_CFG=1024,			///<  In Factory Settings
+	PT_RST_SHDN_RISK=2048,			///<  Could cause shutdown during factory reset
+	// Typical configurations
+	PT_VOL_RO=PT_RO|PT_VOL,			///<  Volatile R/O parameter
+	PT_RO_RT=PT_RO|PT_RT,			///<  Read only real-time parameter
+	PT_ROC_RT=PT_RO|PT_RT|PT_CLR,	///<  Read only real-time parameter/clear
+	PT_RW_RT=PT_RT,					///<  R/W real-time parameter
+	PT_RAM_RT=PT_RAM|PT_RT,			///<  R/W RAM real-time parameter
+	PT_NV_RW=PT_NV,					///<  Non-volatile R/W parameter
+	PT_NV_RWA=PT_NV|PT_ADV,			///<  Non-vol R/W parameter (advanced)
+	PT_NV_RW_RT=PT_RT|PT_NV,		///<  Non-volatile R/W real-time parameter
+	PT_CFG=PT_NV_RW|PT_IN_NODE_CFG,	///<  Non-vol R/W in config file item
+	PT_CFGA=PT_CFG|PT_ADV,			///<  Non-vol R/W in config file item (advanced)
+	PT_FCFG=PT_NV_RW|PT_IN_NODE_CFG|PT_IN_FACT_CFG,	// Factory setting in config file
+	PT_FCFG_RT = PT_NV_RW | PT_IN_NODE_CFG | PT_IN_FACT_CFG | PT_RT,	// Factory setting in config file (real-time)
+	PT_FAC=PT_NV_RW|PT_IN_FACT_CFG,	//	  Factory setting
+	PT_MTR=PT_NV_RW|PT_IN_MTR_CFG,	///<  Non-vol R/W in motor section
+	PT_MTR_R=PT_MTR|PT_RST_SHDN_RISK, //  Non-vol R/W in motor section; could cause shutdown during factory reset
+	PT_FMTR=PT_NV_RW|PT_IN_MTR_CFG|PT_IN_FACT_CFG,	///<  Factory motor items  in config file
+	PT_ALL=PT_NV_RW|PT_IN_ALL_CFG,	///<  Non-vol R/W extended config
+	PT_UNKNOWN=-1
+} paramTypes;
+
+typedef enum _signTypes  {			// Sign extension handling
+	ST_UNSIGNED,					// 0 - unsigned 0 ... 2^n
+	ST_SIGNED,						// 1 - signed -2^n-1 ... 2^n-1
+	ST_POS_ONLY						// 2 - signed 0 ... 2^n-1
+} signTypes;
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
+		 Format that the application layer uses to describe a parameter
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
+typedef union _appNodeParam {
+	unsigned bits;
+	struct {
+		unsigned param	: 7;		// Parameter base number
+		unsigned option : 1;		// Option bit
+		unsigned bank	: 2;		// Parameter bank
+	} fld;
+} appNodeParam;
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+	\brief Parameter value container. 
+
+	This container is used to access the bit-wise view of a non-numeric
+	parameter via the \a raw member. The \a BufferSize member will be
+	set to the length in the buffer received from the node. The \a
+	exists member will be set if the drive has a current value in its
+	cache. If the parameter has a numeric equivalent the \a value member
+	will be set to it.
+**/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+#pragma pack(push,1)				// Align to bytes boundaries
+
+typedef struct _paramValue {
+	double value;					///< Current numeric value (if exists)
+	nodebool exists;				///< Value present
+	nodebool isPolled;				// Value is polled (not used)
+	packetbuf raw;					///< The "raw" octet value
+#ifdef __cplusplus
+	_paramValue() {
+		value = 0;
+		exists = false;
+		isPolled = false;
+	}
+#endif
+} paramValue;
+#pragma pack(pop)
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
+							Parameter scaling holder
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
+typedef struct _paramscale {
+	nodeUNIstr unitName;			// Unit name ptr
+	unitTypes unitType;				// Unit type
+	double scaleFromBase;			// base unit * scale = new unit
+} paramscale;
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
+							 Parameter Information
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
+
+typedef enum _initType {
+	RAM,	// RAM only type
+	NV,		// EE only type
+	NVRV,	// EE w/ RAM virt shadow (write to RAM updates EE)
+	NVR,	// EE w/ RAM shadow (need to write to both)
+	RO		// Read-only
+} initType;
+
+typedef struct _factoryInitData  {
+	initType type;					// Parameter type
+	nodeulong paramNum;				// Parameter number
+	double value;					// Initialize value
+	nodelong minVersion;			// Minimum version (on ClearPath, a negative
+									// value indicate the version when the default
+									// param was removed from or made restrictive 
+									// on the FW)
+	nodeulong fwOption;				// Firmware option
+	nodeulong hwPlat;				// Setting for hardware platform
+} factoryInitData;
+
+// This is the enumeration from ValuesLib.dll that is used to translate 
+// node specific parameter numbers into the generic values used by the
+// PhysDriveObj node implementations.
+typedef enum _ParameterNumbers{
+    PARAM_NULL = 0,
+    PARAM_KV = 1,
+    PARAM_KI = 2,
+    PARAM_KP = 3,
+    PARAM_KFV = 4,
+    PARAM_KFA = 5,
+    PARAM_KFJ = 6,
+    PARAM_KIP = 7,
+    PARAM_KII = 8,
+    PARAM_KNP = 9,
+    PARAM_KNV = 10,
+    PARAM_KB = 11,
+    PARAM_KFF = 12,
+    PARAM_TRQ_LIM = 13,
+    PARAM_SAMP_RATE = 14,
+    PARAM_CONFIG_REG = 15,
+    PARAM_RO = 16,
+    PARAM_STEP_RES = 17,
+    PARAM_ENC_DENS = 18,
+    PARAM_ENC_RESOL = 19,
+    PARAM_POLES = 20,
+    PARAM_ROM_SUM = 21,
+    PARAM_ANA_IN_OFFS = 22,
+    PARAM_TRK_ERR_LIM = 23,
+    PARAM_RMS_LIM = 24,
+    PARAM_RMS_TC = 25,
+    PARAM_ERR_CODES = 26,
+    PARAM_TP_IR = 27,
+    PARAM_TP_IS = 28,
+    PARAM_MON_AMPL = 29,
+    PARAM_MON_VAR = 30,
+    PARAM_IN_RANGE_WIN = 31,
+    PARAM_TRQ_DIG = 32,
+    PARAM_MECH_ANGLE = 33,
+    PARAM_TP_ANALOG = 34,
+    PARAM_TP_IOP = 35,
+    PARAM_FUZZ_AP = 36,
+    PARAM_BUS_V = 37,
+    PARAM_MTR_OHMS = 38,
+    PARAM_MTR_ELECT_TC = 39,
+    PARAM_I_MAX = 40,
+    PARAM_MTR_KE = 41,
+    PARAM_SPEED_LIM = 42,
+    PARAM_MV_DN_TC = 43,
+    PARAM_COM_CAP = 44,
+    PARAM_RASCON = 45,
+    PARAM_TRQ_FLDBACK = 46,
+    PARAM_HS_THRESHOLD = 47,
+    PARAM_HS_TC = 48,
+    PARAM_TRQ_BIAS = 49,
+    PARAM_TRQ_REL_TC = 50,
+    PARAM_TRQ_FILT = 51,
+    PARAM_MON_FILT = 52,
+    PARAM_ANA_VEL_MAX = 53,
+    PARAM_EE_UPD_ACK = 54,
+    PARAM_SERVO_DELAY = 55,
+    PARAM_READY_DELAY = 56,
+    PARAM_LPB_WINDOW = 57,
+    PARAM_NV_MODIFIED = 58,
+    PARAM_SERIAL_NUMBER = 59,
+    PARAM_RMS_MAX = 60,
+    PARAM_RMS_MAX_TC = 61,
+    PARAM_OPTION_REG = 62,
+    PARAM_VECT_RATE = 63,
+    PARAM_HW_REV = 64,
+    PARAM_FUZZY_APERTURE = 65,
+    PARAM_ANTI_HUNT_HYSTERESIS = 66,
+    PARAM_POSN_CMD = 67,
+    PARAM_POSN_MEAS = 68,
+    PARAM_VEL_CMD = 69,
+    PARAM_VEL_MEAS = 70,
+    PARAM_RMS_LVL = 71,
+    PARAM_STATUS_REG = 72,
+    PARAM_ADC_MAX = 73,
+    PARAM_BUS_V_MEAS = 74,
+    PARAM_TRQ_MEAS = 75,
+    PARAM_TRQ_CMD = 76,
+    PARAM_TEMPERATURE = 77,
+    PARAM_TP16V = 78,
+    PARAM_TP5V = 79,
+    PARAM_TRQ_FLDBACK_NEG = 80,
+    PARAM_TRQ_FLDBACK_POS = 81,
+    PARAM_TRQ_FLDBACK_HS = 82,
+    PARAM_TRQ_FLDBACK_NEG_TC = 83,
+    PARAM_TRQ_FLDBACK_POS_TC = 84,
+    PARAM_TRQ_FLDBACK_HS_TC = 85,
+    PARAM_TRQ_FLDBACK_MVDN_TC = 86,
+    PARAM_TRQ_FLDBACK_MVDN = 87,
+    PARAM_STATUS_RT_REG = 88,
+    PARAM_OVER_V_TRIP = 89,
+    PARAM_LPB_THRESH = 90,
+    PARAM_HS_STOP_VEL = 91,
+    PARAM_NO_COMM_START_TRQ = 92,
+    PARAM_KNVAH = 93,
+    PARAM_TRQ_SCALE = 94,
+    PARAM_MIN_TRK_ERR = 95,
+    PARAM_MAX_TRK_ERR = 96,
+    PARAM_POSN_CAP_EN = 97,
+    PARAM_ANA_IN_CONFIG = 98,
+    PARAM_CONFIG1_REG = 99,
+    PARAM_COM_CONFIG = 100,
+    PARAM_GEAR_RES = 101,
+    PARAM_ESTOP_DECEL = 102,
+    PARAM_RMS_PEAK = 103,
+    PARAM_MTR_TEMP_LOCKOUT = 104,
+    PARAM_DRV_ENBL_LOCKOUT = 105,
+    PARAM_THERM_SHUTDOWN_DELAY = 106,
+    PARAM_VEL_FILTER = 107,
+    PARAM_NO_COM_TIME = 108,
+    PARAM_LOAD_MTR_RATIO = 109,
+    PARAM_COUPLING_ERR_LIM = 110,
+    PARAM_KPL = 111,
+    PARAM_POSN_MTR = 112,
+    PARAM_POSN_LOAD = 113,
+    PARAM_AHFUZZ2 = 114,
+    PARAM_GEAR_MAIN = 115,
+    PARAM_LD_SPEED_LIM = 116,
+    PARAM_RUNTIME_ERR = 117,
+    PARAM_AMBIENT_TEMP = 118,
+    PARAM_IR_CAL_FACTOR = 119,
+    PARAM_IS_CAL_FACTOR = 120,
+    PARAM_PARTID = 121,
+    PARAM_COMM_MASK = 122,
+    PARAM_COMM_FACTOR = 123,
+    PARAM_CAL_ANA = 124,
+    PARAM_CAL_ANA_OFFS = 125,
+    PARAM_FAN_ON_TEMP = 126,
+    PARAM_IB_TC = 127,
+    PARAM_IB_TRIP = 128,
+    PARAM_I_TRIP = 129,
+    PARAM_IB = 130,
+    PARAM_IB_PEAK = 131,
+    PARAM_I_TP_FILT = 132,
+    PARAM_BUS_V_OFFS = 133,
+    PARAM_BUS_V_CAL = 134,
+    PARAM_BUS_V_LOW = 135,
+    PARAM_REGEN_ON_V = 136,
+    PARAM_REGEN_OFF_V = 137,
+    PARAM_REGEN_PWR_LIM = 138,
+    PARAM_REGEN_PWR_TC = 139,
+    PARAM_REGEN_DMP_PWR_LIM = 140,
+    PARAM_IB_OFFS = 141,
+    PARAM_IB_CAL = 142,
+    PARAM_TEMP_WARN = 143,
+    PARAM_TEMP_LIM = 144,
+    PARAM_FAN_WARN_SPD = 145,
+    PARAM_FAN_FAULT_SPD = 146,
+    PARAM_IB_TRIP_RMS = 147,
+    PARAM_SHUTDOWN_DETAIL_REG = 148,
+    PARAM_OUTPUT_REG = 149,
+    PARAM_INPUT_REG = 150,
+    PARAM_FAN_SPD = 151,
+    PARAM_AC_FREQ = 152,
+    PARAM_RMS_LIM_3PH = 153,
+    PARAM_I_OFFS_INHIBIT = 154,
+    PARAM_AC_MON_FILT = 155,
+    PARAM_KM_FACT = 156,
+    PARAM_MTR_OHMS_MIN = 157,
+    PARAM_AH_HOLDOFF = 158,
+    PARAM_ACC_LIM = 159,
+    PARAM_DEC_LIM = 160,
+    PARAM_VEL_LIM = 161,
+    PARAM_HEAD_DX = 162,
+    PARAM_TAIL_DX = 163,
+    PARAM_HT_VEL_LIM = 164,
+    PARAM_POSN_MTR_INDX = 165,
+    PARAM_POSN_LD_INDX = 166,
+    PARAM_TSPD = 167,
+    PARAM_CFG_TUNE = 168,
+    PARAM_CFG_FEATURE = 169,
+    PARAM_CFG_HW = 170,
+    PARAM_CFG_APP = 171,
+    PARAM_PART_NUM = 172,
+    PARAM_EE_VER = 173,
+    PARAM_ROM_UPD_ACK = 174,
+    PARAM_ALERT_REG = 175,
+    PARAM_WARN_RT_REG = 176,
+    PARAM_WARN_MASK_REG = 177,
+    PARAM_WARN_ACCUM_REG = 178,
+    PARAM_STATUS1_SW_ACCUM = 179,
+    PARAM_STATUS1_ACCUM = 180,
+    PARAM_STATUS1_RT = 181,
+    PARAM_STATUS1_ATTN_MASK = 182,
+    PARAM_ON_TIME = 183,
+    PARAM_ALERT_MASK_REG = 184,
+    PARAM_STATUS1_ATTN_RISE = 185,
+    PARAM_STOP_TYPE = 186,
+    PARAM_WATCHDOG_TIME = 187,
+    PARAM_IEX_STATUS = 188,
+    PARAM_IEX_GLITCH_CNT = 189,
+    PARAM_IEX_GLITCH_PEAK = 190,
+    PARAM_IEX_INPUT_REG = 191,
+    PARAM_IEX_IN_RISE_REG = 192,
+    PARAM_IEX_IN_FALL_REG = 193,
+    PARAM_IEX_IN_REG_MASK = 194,
+    PARAM_IEX_IN_RISE_REG_MASK = 195,
+    PARAM_IEX_IN_FALL_REG_MASK = 196,
+    PARAM_IEX_GLITCH_LIM = 197,
+    PARAM_IEX_OUT_REG = 198,
+    PARAM_IEX_USER_OUT_REG = 199,
+    PARAM_IEX_STOP_OUT_REG = 200,
+    PARAM_STEP_RUN_TRQ = 201,
+    PARAM_STEP_IDLE_TRQ = 202,
+    PARAM_STEP_ACC_TRQ = 203,
+    PARAM_STEP_MICRO = 204,
+    PARAM_RAS_MAX_VEL = 205,
+    PARAM_TRQ_FLDBACK_STEP_TC = 206,
+    PARAM_CMD_TUNE_REG = 207,
+    PARAM_OUT_SRC = 208,
+    PARAM_CMD_TUNE_ATTACK = 209,
+    PARAM_CMD_TUNE_GSTOP = 210,
+    PARAM_CMD_TUNE_MODE = 211,
+    PARAM_CMD_TUNE_DELAY = 212,
+    PARAM_JOG_VEL_LIM = 213,
+    PARAM_JOG_ACC_LIM = 214,
+    PARAM_COUPLING_ERR = 215,
+    PARAM_TRK_ERR = 216,
+    PARAM_A_AFTER_DIST = 217,
+    PARAM_B_BEFORE_DIST = 218,
+    PARAM_AT_POSN_LOC = 219,
+    PARAM_COMM_ANGLE_LIM = 220,
+    PARAM_HLESS_RAMPUP_TIME = 221,
+    PARAM_HLESS_SWEEP_TIME = 222,
+    PARAM_HLESS_SETTLE_TIME = 223,
+    PARAM_SOFT_LIM_POSN_POS = 224,
+    PARAM_SOFT_LIM_POSN_NEG = 225,
+    PARAM_AH_GAIN = 226,
+    PARAM_MOVE_DWELL = 227,
+    PARAM_KZERO = 228,
+    PARAM_IZERO = 229,
+    PARAM_TGT_WIN = 230,
+    PARAM_STAB_WIN = 231,
+    PARAM_KP_UNDERDAMPED = 232,
+    PARAM_KP_CRITICAL = 233,
+    PARAM_KI_UNDERDAMPED = 234,
+    PARAM_KI_CRITICAL = 235,
+    PARAM_KOUT = 236,
+    PARAM_IOUT = 237,
+    PARAM_R2S_TRQ_LIM = 238,
+    PARAM_R2S_VEL0 = 239,
+    PARAM_R2S_VEL1 = 240,
+    PARAM_R2S_VEL2 = 241,
+    PARAM_R2S_VEL3 = 242,
+    PARAM_VELKNOB_MAX_CW_VEL = 243,
+    PARAM_VELKNOB_MAX_CCW_VEL = 244,
+    PARAM_VELKNOB_VEL_PER_CNT = 245,
+    PARAM_ABSPOSN_HOMING_VEL = 246,
+    PARAM_ABSPOSN_POSN0 = 247,
+    PARAM_ABSPOSN_POSN1 = 248,
+    PARAM_ABSPOSN_POSN2 = 249,
+    PARAM_ABSPOSN_POSN3 = 250,
+    PARAM_SPINONPWR_VEL = 251,
+    PARAM_M2S_DIST_TIL_SW = 252,
+    PARAM_STOP_QUAL_TC = 253,
+    PARAM_VELFLW_DEADBAND = 254,
+    PARAM_VELFLW_MAX_FREQ = 255,
+    PARAM_VELFLW_MIN_FREQ = 256,
+    PARAM_VELFLW_MAX_VEL = 257,
+    PARAM_HOMING_OFFSET = 258,
+    PARAM_TRQFLW_MAX_TRQ = 259,
+    PARAM_TRQFLW_OVERVEL_TC = 260,
+    PARAM_TRQFLW_TRQ_FILT_TC = 261,
+    PARAM_ENBL_TC = 262,
+    PARAM_ENBL_PULSE_TC = 263,
+    PARAM_IN1_IN2_TC = 264,
+    PARAM_INPUT_STIM = 265,
+    PARAM_VEL_MAX_HLFB = 266,
+    PARAM_STEP_RES_ACTIVE = 267,
+    PARAM_BASE_UNIT = 268,
+    PARAM_TP1_65V = 269,
+    PARAM_TP12V = 270,
+    PARAM_INCPOSN_DIST0 = 271,
+    PARAM_INCPOSN_DIST1 = 272,
+    PARAM_INCPOSN_DIST2 = 273,
+    PARAM_INCPOSN_DIST3 = 274,
+    PARAM_HLESS_RDG = 275,
+    PARAM_HLESS_SETUP = 276,
+    PARAM_HLESS_AMPS = 277,
+    PARAM_RMS_INIT = 278,
+    PARAM_BUS_V_MAX = 279,
+    PARAM_HLFB_DUTY = 280,
+    PARAM_IN_FREQ_OVR = 281,
+    PARAM_IN_DUTY_OVR = 282,
+    PARAM_PULSE_VEL_ADJ = 283,
+    PARAM_PULSE_INCR_ADJ = 284,
+    PARAM_SET_FLAGS = 285,
+    PARAM_RUNTIME_FLAGS = 286,
+    PARAM_CLAMP_TRQ = 287,
+    PARAM_CLAMP_TC = 288,
+    PARAM_AT_STROKE_MIN = 289,
+    PARAM_AT_STROKE_MAX = 290,
+    PARAM_AT_MAX_VEL = 291,
+    PARAM_AT_MAX_ACC = 292,
+    PARAM_AT_MAX_TRQ = 293,
+    PARAM_AT_MAX_VOLTS = 294,
+    PARAM_KP_ZERO = 295,
+    PARAM_KP_OUT = 296,
+    PARAM_KI_ZERO = 297,
+    PARAM_KI_OUT = 298,
+    PARAM_KT = 299,
+    PARAM_KV_BASE = 300,
+    PARAM_KII_0 = 301,
+    PARAM_KII_1 = 302,
+    PARAM_KII_2 = 303,
+    PARAM_KII_3 = 304,
+    PARAM_KII_4 = 305,
+    PARAM_KII_5 = 306,
+    PARAM_KII_6 = 307,
+    PARAM_KII_7 = 308,
+    PARAM_KII_8 = 309,
+    PARAM_KII_9 = 310,
+    PARAM_KIP_0 = 311,
+    PARAM_KIP_1 = 312,
+    PARAM_KIP_2 = 313,
+    PARAM_KIP_3 = 314,
+    PARAM_KIP_4 = 315,
+    PARAM_KIP_5 = 316,
+    PARAM_KIP_6 = 317,
+    PARAM_KIP_7 = 318,
+    PARAM_KIP_8 = 319,
+    PARAM_KIP_9 = 320,
+    PARAM_STOP_QUAL_VEL = 321,
+    PARAM_ALT_VEL_LIM = 322,
+    PARAM_HLESS_VOLTS = 323,
+    PARAM_PWM_CMD_PCT = 324,
+    PARAM_IN_FREQ = 325,
+    PARAM_IN_DUTY = 326,
+    PARAM_R_0 = 327,
+    PARAM_R_1 = 328,
+    PARAM_R_2 = 329,
+    PARAM_R_3 = 330,
+    PARAM_R_4 = 331,
+    PARAM_R_5 = 332,
+    PARAM_R_6 = 333,
+    PARAM_R_7 = 334,
+    PARAM_R_8 = 335,
+    PARAM_R_9 = 336,
+    PARAM_IN1_TC = 337,
+    PARAM_BNF_MAX_CW_VEL = 338,
+    PARAM_BNF_MAX_CCW_VEL = 339,
+    PARAM_MAX_STEP_RATE = 340,
+    PARAM_RMS_LIM_MSP = 341,
+    PARAM_RMS_TC_MSP = 342,
+    PARAM_MAX_TRAVEL_DIST = 343,
+    PARAM_HOMING_ACCEL = 344,
+    PARAM_HS_DELAY_TIME = 345,
+    PARAM_HOMING_DECEL = 346,
+    PARAM_DIST_INTO_SWITCH = 347,
+    PARAM_RAS_DELAY = 348,
+    PARAM_DRV_KP_FACTOR = 349,
+    PARAM_DRV_KPZ_FACTOR = 350,
+    PARAM_DRV_KI_FACTOR = 351,
+    PARAM_DRV_FINE_TUNE = 352,
+    PARAM_BURST_MIN_IN_FREQ = 353,
+    PARAM_KR = 354,
+    PARAM_VELKNOB_TARGET = 355,
+    PARAM_TRQFLW_MAX_SPEED = 356,
+    PARAM_AH_VOLT_FILT_TC = 357,
+    PARAM_DRV_MODES = 358,
+    PARAM_BUS_AT_ENBL = 359,
+    PARAM_KNOB_SPD_LIM = 360,
+    PARAM_AUTO_RAS_CODE = 361,
+    PARAM_ACC_ENH_AMPL = 362,
+    PARAM_ACC_ENH_PHASE = 363,
+    PARAM_MECH_POSN = 364,
+    PARAM_SPINONPWR_VEL_DRV = 365,
+    PARAM_HOMING_TRQ_LIM = 366,
+    PARAM_VEL_MEAS_FILT = 367,
+    PARAM_INDEX_COUNT = 368,
+    PARAM_INERTIA = 369,
+    PARAM_STATIC_FRICTION = 370,
+    PARAM_VISCOUS_FRICTION = 371,
+    PARAM_IN_RANGE_VEL = 372,
+    PARAM_KIP_ADJ = 373,
+    PARAM_KII_ADJ = 374,
+    PARAM_EFF_KPZERO = 375,
+    PARAM_EFF_KPOUT = 376,
+    PARAM_EFF_KIZERO = 377,
+    PARAM_EFF_KIOUT = 378,
+    PARAM_EFF_KIP = 379,
+    PARAM_EFF_KII = 380,
+    PARAM_VOLTSQ_CMD = 381,
+    PARAM_HLESS_ENTRY_MOTION = 382,
+    PARAM_HLESS_VERIFY_MAX_MOTION = 383,
+    PARAM_HLESS_VERIFY_MIN_MOTION = 384,
+    PARAM_HLESS_VERIFY_TRQ_TIME = 385,
+    PARAM_HLESS_VERIFY_RAMP_TIME = 386,
+    PARAM_POWERUP_HOLDOFF_TIME = 387,
+    PARAM_USER_DESC = 388,
+    PARAM_CFG_FLDBK=389,			// Foldback config register
+    PARAM_XPS_OUT_SRC_REG=390,		// Output bits sourced by CPS
+    PARAM_XPS_INVERT_INPUT=391,		// CPS invert inputs
+    PARAM_XPS_INVERT_OUTPUT=392,	// CPS invert outputs
+    PARAM_XPS_FEAT_ENABLE=393,		// CPS enable config
+	PARAM_XPS_FEAT_CAPTURE=394,		// CPS capture config
+    PARAM_XPS_FEAT_TRIGGER=395,		// CPS trigger config
+    PARAM_XPS_FEAT_NODE_STOP=396,	// CPS node stop config
+    PARAM_XPS_FEAT_RESET_TIMER=397, // CPS reset timer config
+    PARAM_XPS_FEAT_ATTN0=398,		// CPS attn-0 config
+    PARAM_XPS_FEAT_ATTN1=399,		// CPS attn-1 config
+    PARAM_XPS_FEAT_AT_HOME=400,		// CPS at home config
+    PARAM_XPS_FEAT_POS_TRQ_FLBK=401,// CPS positive trq foldback config
+    PARAM_XPS_FEAT_NEG_TRQ_FLBK=402,// CPS negative trq foldback config
+    PARAM_XPS_FEAT_IN_POS_LIM=403,	// CPS in positive limit config
+    PARAM_XPS_FEAT_IN_NEG_LIM=404,	// CPS in negative limit config
+	PARAM_XPS_IN_SRC_REG=405,       // Input bits sourced by CPS
+    PARAM_XPS_USER_IN_REG=406,      // User driven CPS Inputs
+    PARAM_XPS_USER_OUT_REG=407,     // User driven CPS Outputs
+	PARAM_XPS_ACTUAL_IN_REG=408,    // Drive driven CPS Inputs
+    PARAM_XPS_IN_REG=409,           // Input to the CPS
+	PARAM_DLY_TO_DISABLE,			// 410 Delay to disable for brakes
+	PARAM_ATTN_MASK_DRVR,			// 411 Driver's attention mask
+	PARAM_GRP_SHUTDOWN_MASK,		// 412 Group Shutdown items
+	PARAM_INPUT_ACTIONS,			// 413 Input A/B Actions (ClearView only)
+	PARAM_SOFT_LIM_POSN_1,			// 414 User defined soft limit
+	PARAM_SOFT_LIM_POSN_2,			// 415 User defined soft limit
+    PARAM_POSN_CAP_INA_HI_SPD,      // 416 Input A (high-speed) posn capture
+    PARAM_POSN_CAP_INB,             // 417 Input B posn capture
+	PARAM_COMM_LOW_V,				// 418 Minimum operating voltage
+	PARAM_TP_SUPPLY1_V,				// 419 Supply1 voltage
+	PARAM_REGEN_DUMP_RATE,			// 420 D-Cmd current to dump regen voltage
+	PARAM_REGEN_RAMP_TIME,			// 421 Time to ramp up to full regen dump current
+	PARAM_REGEN_TRIP_V,				// 422 Voltage to perform regen dump
+	PARAM_UNDER_TEMP_TRIP,			// 423
+	PARAM_ENCODER_TEMP,				// 424
+	PARAM_STATOR_TEMP,				// 425
+	PARAM_STATOR_TEMP_TRIP,			// 426
+	PARAM_STATOR_TEMP_WARN,			// 427
+	PARAM_PWR_STATUS,				// 428
+	PARAM_VECTOR_DRIFT_LIM,			// 429
+	PARAM_DRV_PB_SER_NUM,			// 430
+	PARAM_DRV_PB_REV,				// 431
+	PARAM_TP_PHASE_BOARD,			// 432
+	PARAM_DRV_TEMP,                 // 433 Drive Temperature
+	PARAM_ALERT_ACCUM_REG,			// 434 Accumulated alerts
+	PARAM_CFG_APP1 = 436,			// 436 App Config 1
+	PARAM_PWM_CMD_PCT_A,			// 437
+	PARAM_IN_FREQ_A,				// 438
+	PARAM_IN_DUTY_A,				// 439
+	PARAM_ALT_TRQ_LIM,				// 440
+	PARAM_ADV_TLIM_00,				// 441
+	PARAM_ADV_TLIM_01,				// 442
+	PARAM_ADV_TLIM_10,				// 443
+	PARAM_ADV_TLIM_11,				// 444
+	PARAM_ADV_TRQ_TC,				// 445
+	PARAM_APP_PWMC_MAX_VEL,			// 446
+	PARAM_RMS_SLOW_LIM,				// 447
+	PARAM_RMS_SLOW_TC,				// 448
+	PARAM_RMS_SLOW_LVL,				// 449
+	PARAM_BUSV_ADJ_RATE,			// 450
+	PARAM_SOFT_START_FREQ,			// 451
+	PARAM_INA_DUTY_OVR,				// 452
+	PARAM_PWMC_INA_DUTY,			// 453
+	PARAM_POSN_REC_VEL,				// 454
+	PARAM_POSN_REC_ACC,				// 455
+	PARAM_DRV_MIN_OPER_VOLTS,		// 456
+	PARAM_PWR_AC_LOSS_TC = 458,		// 458
+	PARAM_IB_TC_SLOW=460,			// 460
+	PARAM_TEMP_LIM_USER,			// 461
+	PARAM_EVENT_SHUTDOWN_MASK,		// 462
+	PARAM_PWR_AC_WIRING_ERROR_TC,	// 463
+	PARAM_IB_TRIP_USER,				// 464
+	PARAM_INDEX_DETECT_SPEED,		// 465
+	PARAM_RMS_STOPPED_FACTOR,		// 466
+	PARAM_RMS_STOPPED_SPEED,		// 467
+    PARAM_MOVE_OPTIONS              // 468 Move options for immediate moves 
+} configKeys;
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+	\brief Detailed parameter information.
+
+	This container provides more detailed internal information about the
+	type of a parameter.
+**/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef struct _paramInfo {
+	nodebool reciprical;			// Node value is reciprical of this value
+	nodeushort signextend;	   		// Value is signed	(signTypes)
+	paramTypes paramType;			///< Parameter type
+	unitTypes unitType;				///< Unit type
+	nodeulong paramSize;			// Number of octets expected in parameter
+	double scaleFromBase;			// <node octets>/scaleFromBase = value
+	configKeys keyID;				// Key index for configuration file	PARAM_*
+	nodeulong descID;				// Resource ID for description
+} paramInfo;
+
+typedef struct _paramInfoLcl paramInfoLcl;	// Forward reference structure def
+typedef struct _byNodeDB byNodeDB;
+
+typedef double (MN_DECL *unitConverter)(nodebool toUnit, 
+									    nodeaddr theNode,
+										appNodeParam parameter, 
+										double fromValue,
+										byNodeDB *nodeData);
+// If paramSize is negative, this represents a variable sized parameter with a 
+// maximum size equal to abs(paramSize).
+typedef struct _paramInfoLcl  {
+	paramInfo info;					// Node information
+	unitConverter converter;		// Optional unit converter
+} paramInfoLcl;
+
+// Database for class of device parameters
+typedef struct _byNodeClassDB {
+	paramChangeFunc paramChngFunc;	// Ptr to parameter change function
+} byNodeClassDB;
+	
+// Parameter bank holder - holds the parameter fixed information and the
+// current value.
+typedef struct _paramBank  {
+	nodeulong nParams;				// Number of parameters in bank
+	const paramInfoLcl *fixedInfoDB;// Fixed parameter info (static alloc)
+	paramValue *valueDB;			// Value database (dynamic alloc)
+} paramBank;
+
+typedef struct _byNodeDiagStats
+{
+										// Application Network
+										// -------------------
+	Uint16 appNetFragPktCtr;			// Fragment counter
+	Uint16 appNetBadChksumCtr;			// Checksum counter
+	Uint16 appNetStrayCtr;				// Stray data counter
+	Uint16 appNetOverrunCtr;			// Overrun counter
+										
+										// Diagnostic Network
+										// -------------------
+	Uint16 diagNetFragPktCtr;			// Fragment counter
+	Uint16 diagNetBadChksumCtr;			// Checksum counter
+	Uint16 diagNetStrayCtr;				// Stray data counter
+	Uint16 diagNetOverrunCtr;			// Overrun counter
+
+	Uint16 linkBusLow;					// Counter of link voltage low 
+	void clear() {
+		appNetFragPktCtr = 0;			// Fragment counter
+		appNetBadChksumCtr = 0;			// Checksum counter
+		appNetStrayCtr = 0;				// Stray data counter
+		appNetOverrunCtr = 0;			// Overrun counter
+							
+		diagNetFragPktCtr = 0;			// Fragment counter
+		diagNetBadChksumCtr = 0;		// Checksum counter
+		diagNetStrayCtr = 0;			// Stray data counter
+		diagNetOverrunCtr = 0;			// Overrun counter
+		linkBusLow = 0;				
+	}
+	_byNodeDiagStats() {
+		clear();
+	}
+} byNodeDiagStats;
+
+
+
+// iscClassSetup function will allocate and initialize this structure.
+
+typedef void (*deleteFunc)(multiaddr theMultiAddr);
+
+
+typedef struct _byNodeDB  {
+	devID_t theID;					// Device and Firmware type.
+	nodeulong rank;					// Rank within the node class
+	unsigned bankCount;				// Number of parameter banks
+	paramBank *paramBankList;		// Ptr to the parameter bank(s)
+	byNodeClassDB *pClassInfo;		// Class common information
+	deleteFunc delFunc;				// Cleanup and delete function
+	void *pNodeSpecific;			// Ptr to node specific 
+	_byNodeDB() {
+		paramBankList = NULL;
+		pNodeSpecific = NULL;
+		pClassInfo = NULL;
+		delFunc = NULL;
+		bankCount = 0;
+		rank = 0;
+	}
+} byNodeDB;
+
+
+
+ /* !end!																	*
+ ****************************************************************************/
+/// \endcond
+// end INTERNAL_DOC
+/// @}
+#endif
+
+/*========================================================================== 
+	END OF FILE mnParamDefs.h
+  ========================================================================== */
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/netCmdAPI.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/netCmdAPI.h
new file mode 100644
index 000000000..2eee77118
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/netCmdAPI.h
@@ -0,0 +1,345 @@
+//******************************************************************************
+// NAME
+//		netCmdAPI.h
+//
+// DESCRIPTION:
+//		This file decribes the network command level interface. It provides
+//		a common API for executing node commands and accessing network 
+//		facilities such as high-priority trigger commands and the like.
+//
+// CREATION DATE:
+//		09/22/2004 13:44:07 - was netCoreAPI.h
+//		06/11/2008 10:33:00 - renamed to avoid CP conflicts
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2004-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			   *
+//******************************************************************************
+#ifndef __NETCMDAPI_H__
+#define	__NETCMDAPI_H__
+
+
+//******************************************************************************
+// NAME																	       *   
+// 	netCmdAPI.h headers
+//
+	#include "pubMnNetDef.h"
+	#include "pubCoreRegs.h"
+	#include "mnErrors.h"
+	#include "TeknicDevID.h"
+	#include "mnDiags.h"
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																	       *   
+// 	netCmdAPI.h constants
+//
+//
+
+/**
+	This enumeration choses the format for the configuration file.
+**/
+typedef enum _configFmts {
+	CLASSIC,							///< Creates setup compatible file
+	ALL_NON_VOLATILE,					///< CLASSIC + all non-volatile items
+	CLASSIC_NO_RESET					///< Setup compatible file, no reset at end
+} configFmts;
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																	       *   
+// 	netCmdAPI.h function prototypes
+//
+// API functions
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//----------------------------------
+// NETWORK SETUP
+//----------------------------------
+// Issue the set address control packet
+MN_EXPORT cnErrCode MN_DECL netSetAddress(
+		netaddr cNum,
+		nodeulong *maxNode);
+
+// Issue the reverse set address control packet
+MN_EXPORT cnErrCode MN_DECL netReverseAddress(
+		netaddr cNum,
+		nodeaddr nodeCountLessOne);
+		
+// Scan the network and build up the inventory lists
+MN_EXPORT cnErrCode MN_DECL netEnumerate(
+		netaddr cNum);
+
+//----------------------------------
+// COMMAND INTERFACE
+//----------------------------------
+// Run a command and get the response on <cNum>
+MN_EXPORT cnErrCode MN_DECL netRunCommand(
+		netaddr cNum,				// Controller number
+		packetbuf *theCommand,		// pointer to filled in command
+		packetbuf *theResponse);	// pointer to response area
+					
+//----------------------------------
+// PARAMETER ACCESS AND MANIPULATION
+//----------------------------------
+// Get a parameter with various options
+MN_EXPORT cnErrCode MN_DECL netGetParameter(
+		multiaddr theMultiAddr, 		// device address
+		nodeparam theParam, 		// parameter index
+		packetbuf *paramInfo);		// ptr for returned param
+
+// Set a parameter via a number of methods
+MN_EXPORT cnErrCode MN_DECL netSetParameter(
+		multiaddr theMultiAddr, 		// node address
+		nodeparam theParamNum, 		// parameter index
+		packetbuf *pNewValue);		// ptr to new parameter data					
+
+MN_EXPORT cnErrCode MN_DECL netSetParameterEx(
+		multiaddr theMultiAddr, 		// node address
+		nodeparam theParamNum, 		// parameter index
+		packetbuf *pNewValue);		// ptr to new parameter data
+		
+// Force re-read of parameter on next request
+MN_EXPORT cnErrCode MN_DECL netClrParamCache(
+		multiaddr theMultiAddr,
+		mnParams parameter);
+
+// C++ Overloaded parameter accessors with multiaddr argument for numeric
+// parameters.
+MN_EXPORT cnErrCode MN_DECL netGetParameterDbl(
+		multiaddr theMultiAddr,
+		mnParams theParamNum,
+		double *pValue);
+MN_EXPORT cnErrCode MN_DECL netSetParameterDbl(
+		multiaddr theMultiAddr,
+		mnParams theParamNum,
+		double value);
+
+typedef struct _paramInfo paramInfo;
+typedef struct _paramValue paramValue;
+
+// Get info enhanced value
+MN_EXPORT cnErrCode MN_DECL netGetParameterInfo(
+		multiaddr multiAddr,		// Node address
+		nodeparam theParam,			// Parameter number
+		paramInfo *pRetValInfo,		// Ptr to returning value info or NULL
+		paramValue *pRetVal);		// Ptr to returning value or NULL
+	
+//----------------------------------
+// ALERT INTERFACE
+//----------------------------------
+// Time stamp epoch encoding starts here.
+#define MERIDIAN_EPOCH "2010-01-01T00:00:00Z"
+// Number of seconds since 1970-01-01T00:00:00Z to MERIDIAN_EPOCH
+#define MERIDIAN_EPOCH_CTIME 1262304000
+
+// Clear the selected node's alert log history
+MN_EXPORT cnErrCode MN_DECL netAlertLogClear(
+		multiaddr theMultiAddr);		// Node address
+
+// Read an alert log item. Set <restart> to TRUE get oldest, FALSE to get remaining.
+MN_EXPORT cnErrCode MN_DECL netAlertLogGet(
+		multiaddr theMultiAddr,		// Node address
+		nodebool restart,			// Restart the list from oldest
+		nodebool *pEntryExists,		// Updated with TRUE if <pEntry> OK
+		alertLogEntry *pEntry);		// Update user's buffer	
+		
+// Set Alert log epoch time
+MN_EXPORT cnErrCode MN_DECL netAlertLogEpoch(
+		multiaddr theMultiAddr);		// Node address
+
+// Clear and/or acknowledge non-serious Alerts
+MN_EXPORT cnErrCode MN_DECL netAlertClear(
+		multiaddr theMultiAddr);		// Node address
+
+// Get the current alert register
+MN_EXPORT cnErrCode MN_DECL netGetAlertReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pAlertReg);		// Current setting
+
+// Get and clear the current warning register
+MN_EXPORT cnErrCode MN_DECL netGetWarnReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pWarnReg);		// Current setting
+
+//----------------------------------
+// STATUS REGISTER INTERFACE
+//----------------------------------
+MN_EXPORT cnErrCode MN_DECL netGetAttnStatusRiseReg(
+			multiaddr theMultiAddr,			// Node address
+			mnStatusReg *pReg);				// Current setting
+
+MN_EXPORT cnErrCode MN_DECL netGetStatusRTReg(
+			multiaddr theMultiAddr,			// Node address
+			mnStatusReg *pReg);				// Current setting
+
+MN_EXPORT cnErrCode MN_DECL netGetStatusAccumReg(
+			multiaddr theMultiAddr,			// Node address
+			mnStatusReg *pReg);				// Current setting
+
+//----------------------------------
+// DATA ACQUISITION INTERFACE
+//----------------------------------
+// Start acquisition
+MN_EXPORT cnErrCode MN_DECL netEnterDataAcqMode(
+		multiaddr theMultiAddr,
+		double *startTime);
+	
+// Stop Acquisition
+MN_EXPORT cnErrCode MN_DECL netExitDataAcqMode(
+		multiaddr theMultiAddr);
+	
+//----------------------------------
+// NODE STOPS
+//----------------------------------
+// Stop command		
+MN_EXPORT cnErrCode MN_DECL netNodeStop(
+		multiaddr theMultiAddr, 	// node address
+		mgNodeStopReg stopType, 		// stop strategy
+		nodebool broadcast);		// hi prio broadcast
+
+
+//----------------------------------
+// TRIGGER INTERFACES
+//----------------------------------
+// Trigger a single or group of nodes
+MN_EXPORT cnErrCode MN_DECL netTrigger(
+		netaddr cNum,				// Net number
+		nodeaddr nodeOrGroupAddr,	// Node or Group Addr
+		nodebool usingGroup);		// Node(s) selection(s)
+
+//----------------------------------
+// PLA INTERFACES
+//----------------------------------
+// Clear PLA fuses
+MN_EXPORT cnErrCode MN_DECL netPLAclear(
+		multiaddr theMultiAddr); 	// node address
+
+// Get PLA fuses
+MN_EXPORT cnErrCode MN_DECL netPLAget(
+		multiaddr theMultiAddr, 	// node address
+		plaFuseBuffer *pFuses);		// Ptr to fuse buffer
+		
+// Set PLA fuses
+MN_EXPORT cnErrCode MN_DECL netPLAset(
+		multiaddr theMultiAddr, 	// node address
+		plaFuseBuffer *pFuses);		// Ptr to fuse buffer
+
+
+//----------------------------------
+// DIAGNOSTICS INTERFACE
+//----------------------------------
+MN_EXPORT cnErrCode MN_DECL netGetErrStats(
+		multiaddr theMultiAddr,
+		mnNetErrStats *pNetStats);
+	
+// Run a network diagnostic run
+MN_EXPORT cnErrCode MN_DECL netDiagsRun(
+		netaddr theNet,
+		mnNetDiagResults *stats);		// Net stats results
+
+// Return driver's diagnostic run results
+MN_EXPORT cnErrCode MN_DECL netDiagsGet(
+		netaddr theNet,
+		mnNetDiagResults *stats);		// Net stats results
+
+MN_EXPORT cnErrCode MN_DECL netDiagsClr(
+		netaddr theNet);
+
+// Motion Data Collected
+MN_EXPORT cnErrCode MN_DECL netGetDataCollected(
+		multiaddr theMultiAddr,			// Destination node
+		iscDataCollect *pReturnData);	// Returned data
+
+//----------------------------------
+// ACCESS LEVEL INTERFACE
+//----------------------------------
+MN_EXPORT cnErrCode MN_DECL netSetNetAccessLvl(
+		netaddr theNet,
+		mnNetStatus theAccessLevel);
+
+MN_EXPORT cnErrCode MN_DECL netGetNetAccessLvl(
+		netaddr theNet,
+		mnNetStatus *pAccessLevel);
+
+// Change and get the node's feature access level.
+MN_EXPORT cnErrCode MN_DECL netSetNodeAccessLvl(
+	multiaddr theMultiAddr,				// Destination node
+	mnNetStatus newAccessLevel);
+
+MN_EXPORT cnErrCode MN_DECL netGetNodeAccessLvl(
+	multiaddr theMultiAddr,				// Destination node
+	mnNetStatus *pAccessLevel);
+
+//--------------------------------------
+// NODE MANAGEMENT INTERFACE
+//--------------------------------------
+// Get the part number of the specified node into user's buffer
+MN_EXPORT cnErrCode MN_DECL netGetPartNumber(
+		multiaddr theMultiAddr,
+		char *partNumBuf,
+		Uint16 bufferSize);
+		
+// Get the type of device present at <theMultiAddr>
+MN_EXPORT nodeIDs MN_DECL netGetDevType(
+		multiaddr theMultiAddr);
+
+//--------------------------------------
+// USER ID MANAGEMENT INTERFACE
+//--------------------------------------
+MN_EXPORT cnErrCode MN_DECL netSetUserID(
+		multiaddr theMultiAddr,
+		const char *pNewID);
+
+MN_EXPORT cnErrCode MN_DECL netGetUserID(
+		multiaddr theMultiAddr,
+		char *pCurrentID,
+		Uint16 maxBufSize);
+
+//--------------------------------------
+// USER DESCRIPTION MANAGEMENT INTERFACE
+//--------------------------------------
+MN_EXPORT cnErrCode MN_DECL netSetUserDescription(
+		multiaddr theMultiAddr,
+		const char *pNewDescr);
+
+MN_EXPORT cnErrCode MN_DECL netGetUserDescription(
+		multiaddr theMultiAddr,
+		char *pUserDescrStr,
+		Uint16 maxBufSize);
+
+//--------------------------------------
+// CONFIGURATION FILE INTERFACE
+//--------------------------------------
+MN_EXPORT cnErrCode MN_DECL netConfigSave(
+		multiaddr theMultiAddr,
+		configFmts saveFmt,
+		const char *pFilePath);
+
+MN_EXPORT cnErrCode MN_DECL netConfigLoad(
+		multiaddr theMultiAddr,
+		configFmts loadFmt,
+		const char *pFilePath);
+#ifdef __cplusplus
+}
+#endif
+//																			   *
+//******************************************************************************
+#endif  // #ifndef __NETCMDAPI_H__
+
+//============================================================================== 
+//	END OF FILE netCmdAPI.h
+//==============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/netCmdPrivate.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/netCmdPrivate.h
new file mode 100644
index 000000000..61431c5b6
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/netCmdPrivate.h
@@ -0,0 +1,257 @@
+//*****************************************************************************
+// $Header:: /ClearPath SC-1.0.123/User Driver/inc-private/netCmdPrivate.h 4 $
+//
+// NAME
+//		netCmdPrivate.h
+//
+// DESCRIPTION:
+//		netCore.c private prototypes
+//
+// CREATION DATE:
+//		01/28/2004 16:51:59 - was netCorePrivate.h
+//		06/11/2009 10:47:00 - renamed to avoid CP conflicts
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2004-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+#ifndef _NETCMDPRIVATE_H
+#define _NETCMDPRIVATE_H
+
+//*****************************************************************************
+// NAME																          *
+// 	netCmdPrivate.h headers
+//
+	#include "pubMnNetDef.h"
+	#include "mnErrors.h"
+	#include "mnParamDefs.h"
+	#include "pubSysCls.h"
+	#if (defined(_WIN32)||defined(_WIN64))
+		#include "lnkAccessAPIwin32.h"
+	#endif
+	#include <stdarg.h>
+	
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	netCmdPrivate.h types
+//
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	netCmdPrivate.h constants
+//
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	netCmdPrivate.h function prototypes
+//
+//
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+/* 							Private functions 								  */
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Helper function to fill in an error object.
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+void fillInErrs(sFnd::mnErr &eInfo, 
+				cnErrCode theErr, std::string funcName,
+				const char *fmtStr, ...);
+
+void fillInErrs(sFnd::mnErr &eInfo, sFnd::INode *pNode, 
+				cnErrCode theErr, std::string funcName,
+				const char *fmtStr, ...);
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Helper functions to handle unexpected system errors.
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+void handleSystemError(sFnd::mnErr eInfo,
+	void(*callbackFunction)() = nullptr);
+
+void handleSystemError(const char *errStr,
+	void(*callbackFunction)() = nullptr);
+
+void throwSystemError(sFnd::mnErr eInfo);
+void throwSystemError(const char *errStr);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Error code classification functions
+nodebool IsNetClassErr(
+	cnErrCode theErr);
+
+nodebool IsNetBreakErr(
+	cnErrCode theErr);
+
+// Return the controller number to use
+netaddr coreController(multiaddr theMultiAddr);
+
+// Get an 16-bit integer value from the node
+cnErrCode coreBaseGetParameterInt(netaddr cNum, nodeaddr theNode, 
+								  nodeparam paramNum, Uint16 *pVal);
+// Set an 16-bit integer value to the node
+cnErrCode coreBaseSetParameterInt(netaddr cNum, nodeaddr theNode, 
+								  nodeparam paramNum, int pVal);
+
+// Update the value database
+cnErrCode coreUpdateParamInfo(
+		multiaddr multiAddr);		// Node to update		
+
+
+// Set info using enhanced value information
+cnErrCode netSetParameterInfo(
+		multiaddr multiAddr,		// Node address
+		nodeparam theParam,		   	// Parameter number
+		const double theValue,	   	// New value
+		nodebool verify);			// Verify write worked
+
+// Create basic error from the buffer contents
+cnErrCode coreGenErrCode(
+		netaddr cNum,				// Controller number
+		packetbuf *theResp,			// Response buffer
+		nodeaddr cmdNode);			// Expected node
+			
+// Reset the targetted node or network		
+cnErrCode MN_DECL netReset(
+		multiaddr multiAddr,
+		nodebool broadCast); 		// node address
+		
+		
+// Get parameter command		
+cnErrCode MN_DECL netGetParameterFmt(
+		packetbuf *frameBuf,		// ptr to the frame buffer to format
+		nodeaddr theNode, 			// node address
+		nodeparam theParamNum);		// parameter index
+cnErrCode MN_DECL netGetParameterExtract(
+		packetbuf *frameBuf,		// ptr to the frame buffer to format
+		packetbuf *paramInfo);		// ptr to return buffer
+// Set parameter command
+cnErrCode MN_DECL netSetParameterFmt(
+		packetbuf *frameBuf,		// ptr to the frame buffer to format
+		nodeaddr theNode, 			// node address
+		nodeparam theParamNum, 		// parameter index
+		packetbuf *newValue);		// ptr to new parameter data
+
+//MN_EXPORT cnErrCode MN_DECL netGetParameterDbl(
+//		netaddr cNum,				// NC number
+//		nodeaddr theNode, 			// device address
+//		mnParams theParam, 			// parameter index
+//		double *paramInfo);			// ptr for returned param
+//MN_EXPORT cnErrCode MN_DECL netSetParameterDbl(
+//		netaddr theNet,			// NC number
+//		nodeaddr theNode, 			// device address
+//		mnParams theParam, 			// parameter index
+//		double newValue);			// New setting
+
+
+// Internal Attention Feature for Auto-Brake and Group Shutdowns
+
+// Get the current driver attention mask
+cnErrCode MN_DECL netGetDrvrAttnMask(
+		multiaddr theMultiAddr,
+		attnReg *pAttnReg);
+
+// Set the current driver attention mask
+cnErrCode MN_DECL netSetDrvrAttnMask(
+		multiaddr theMultiAddr,
+		attnReg *pAttnReg);
+		
+// Get the current status event mask
+cnErrCode MN_DECL netGetStatusEventMask(
+		multiaddr theMultiAddr,
+		mnStatusReg *pAttnReg);
+
+// Set the current status event mask
+cnErrCode MN_DECL netSetStatusEventMask(
+		multiaddr theMultiAddr,
+		const mnStatusReg *pAttnReg);
+
+// Release all node parameter data for this net
+void coreFreeAllNodeInfo(netaddr cNUm);
+// Force flush of all cached values, next read is from the node
+void coreInvalidateValCache(netaddr cNum);
+void coreInvalidateValCacheByNode(netaddr cNum, nodeaddr nodeAddr);
+
+// Update the parameter database manually from a double
+cnErrCode coreSetParamFromBytes(multiaddr multiAddr, 
+								 nodeparam paramNum,
+								 nodeuchar *pVal,
+								 unsigned sizeInBytes);
+
+// Common initialize logic
+typedef cnErrCode (*coreParamSetupFuncPtr)(multiaddr theMultiAddr);
+cnErrCode MN_DECL coreInitializeEx(
+		multiaddr theMultiAddr,			// Ptr to return array
+		nodebool warmInitialize,
+		coreParamSetupFuncPtr classSetupFunc
+);
+
+// Special parameter callback functions	that require access to net inventory
+double MN_DECL spscWatchAttnMask(
+	nodebool valIsBits, 				// TRUE=>ADC Temp, FALSE=>C Temp
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB);
+#ifdef __cplusplus
+}
+#endif
+ 
+ 
+#ifndef NC_DRIVER
+//*****************************************************************************
+// NAME																          *
+//		cpymem
+//		
+//	DESCRIPTION:
+//		This function will copy nchars of memory from <src> to <dest>.
+//		
+//  CREATION DATE:
+//		February 13, 1998  13:24:34
+//
+//	RETURNS:
+//		cnErrCode error code
+//		
+//	SYNOPSIS:
+__inline void cpymem(nodeuchar *src, nodeuchar *dest, nodeushort nchars) {
+	while (nchars--)
+		*(dest++) = *(src++);
+}
+//																			  *
+//*****************************************************************************
+#endif
+
+
+//*****************************************************************************
+// NAME																          *
+// 	netCmdPrivate.h constants
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+#endif
+//============================================================================= 
+//	END OF FILE netCmdPrivate.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/sFoundResource.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/sFoundResource.h
new file mode 100644
index 000000000..8ba9bfd62
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/sFoundResource.h
@@ -0,0 +1,671 @@
+//{{NO_DEPENDENCIES}}
+// Microsoft Developer Studio generated include file.
+// Used by ntTrans.rc
+//
+#define STR_NULL						0			
+#define STR_UNKNOWN                    	8000
+#define STR_OUT_OF_RANGE				8001
+#define STR_PARAM_DEVID                	8002
+#define STR_PARAM_FWVERS               	8003
+#define STR_PARAM_HWVERS               	8004
+#define STR_PARAM_RESELLERID			8005
+#define STR_PARAM_SERIAL_NUM           	8006
+#define STR_PARAM_OPT_REG              	8007
+#define STR_PARAM_ROMSUM_ACK           	8008
+#define STR_PARAM_FWSUM                	8009
+#define STR_PARAM_SAMP_PER				8010
+#define STR_PARAM_ALERT_REG				8011
+#define STR_PARAM_STOPTYPE				8012
+#define STR_PARAM_WDTC					8013
+#define STR_PARAM_USERID				8014
+#define STR_PARAM_STATUS				8015
+#define STR_PARAM_STATUS_RT				8016
+#define STR_PARAM_STATUS_ATTN_RISE		8017
+#define STR_PARAM_ATTN_MASK				8018
+#define STR_PARAM_TIMESTAMP				8019
+#define STR_PARAM_TIMESTAMP16			8020
+#define STR_PARAM_CONFIG_REG			8021
+#define STR_PARAM_IN_REG				8022
+#define STR_PARAM_IN_RISE_REG			8023
+#define STR_PARAM_IN_FALL_REG			8024
+#define STR_PARAM_IN_TRANS_REG			8025
+#define STR_PARAM_IN_SRC_REG			8026
+#define STR_PARAM_USER_IN_REG			8027
+#define STR_PARAM_OUT_REG				8028
+#define STR_PARAM_OUT_RISE_REG			8029
+#define STR_PARAM_OUT_FALL_REG			8030
+#define STR_PARAM_OUT_TRANS_REG			8031
+#define STR_PARAM_IN_POLARITY			8032
+#define STR_PARAM_USER_OUT_REG			8033
+#define STR_PARAM_OUT_SRC_REG			8034
+#define STR_PARAM_GP_TIMER				8035
+#define STR_PARAM_PLA_OUT_REG		   	8036
+#define STR_PARAM_IN_POL_REG			8037
+#define STR_PARAM_MEAS_POSN				8038
+#define STR_PARAM_INDEX_POSN_CAP		8039
+#define STR_PARAM_GPI0_POSN_CAP			8040
+#define STR_PARAM_PLA_POSN_CAP		   	8041
+#define STR_PARAM_POLL_SET				8042
+#define STR_PARAM_POLL_TYPE_REG			8043
+#define STR_PARAM_VEL_LIMIT				8044
+#define STR_PARAM_ACC_LIMIT				8045
+#define STR_PARAM_TEST9					8046
+#define STR_PARAM_IMR					8047
+#define STR_PARAM_RAS_CON_REG		   	8048
+#define STR_PARAM_ATTN_REG				8049
+#define STR_PARAM_NODE_LIST				8050
+#define STR_PARAM_POSN_TRIG_PT			8051
+#define STR_PARAM_A_START				8052
+#define STR_PARAM_B_END					8053
+#define STR_PARAM_POS_TRK_RNG			8054
+#define STR_PARAM_CMD_POSN				8055
+#define STR_PARAM_POSN_TRK				8056
+#define STR_PARAM_PULSE_ENC_RATIO		8057
+#define STR_PARAM_STOPACC_LIM			8058
+#define STR_PARAM_I_MEAS_POSN			8059
+#define STR_PARAM_I_CMD_POSN			8060
+#define STR_PARAM_CMD_VEL				8061
+#define STR_PARAM_MEAS_VEL				8062
+#define STR_PARAM_DEC_LIMIT				8063
+#define STR_PARAM_HEAD_DX				8064
+#define STR_PARAM_TAIL_DX				8065
+#define STR_PARAM_HEADTAIL_VEL			8066
+#define STR_PARAM_VGLITCH				8067
+#define STR_PARAM_DGLITCH				8068
+#define STR_PARAM_MAXACC				8069
+#define STR_PARAM_N_GARBAGE				8070
+#define	STR_PARAM_RUN_ERROR				8071
+#define STR_PARAM_USERID1				8072
+#define	STR_DRV_ADC_MAX					8073
+#define STR_PARAM_FLOW_IN_TP			8074
+#define STR_PARAM_FLOW_OUT_TP			8075
+#define STR_DRV_TP_IR_FILT				8076
+#define STR_DRV_TP_IS_FILT				8077
+#define STR_WARN_RT						8078
+#define STR_USER_WARN_MASK_REG			8079
+#define STR_USER_ALERT_MASK_REG			8080
+#define STR_PARAM_STATUS_FALL			8081
+#define STR_PARAM_NETSTAT				8082
+#define STR_WARN_ACC					8083
+#define STR_PARAM_ACC_MAX				8084
+#define STR_PARAM_I_MEAS_POSN_MTR		8085
+#define STR_PARAM_CPL_ERR				8086
+#define STR_PARAM_SOFT_LIM_POS			8087
+#define STR_PARAM_SOFT_LIM_NEG			8088
+#define STR_PARAM_DWELL					8089
+#define STR_HOME_ACCEL					8090
+#define STR_RAS_DELAY					8091
+#define STR_HOME_TRAVEL					8092
+#define STR_HOME_DELAY					8093
+#define STR_PARAM_VEL_LIMIT_MAX			8094
+#define STR_PARAM_ACC_LIMIT_MAX			8095
+#define STR_PARAM_STOPACC_LIM_MAX		8096
+#define STR_MTR_INERTIA					8097
+#define STR_MTR_STAT_FRICTION			8098
+#define STR_MTR_VISC_FRICTION			8099
+
+#define STR_PARAM_POLL_PRIO				8100
+#define STR_PARAM_RING_POLL				8101
+#define STR_PARAM_RING_POLL_CNT			8102
+#define STR_PARAM_CHKS_ERR				8103
+#define STR_PARAM_FRAG_ERR				8104
+#define STR_PARAM_N_SENT				8105
+#define STR_PARAM_N_RCVD				8106
+#define STR_PARAM_N_SENT_SOF			8107
+#define STR_PARAM_N_RCVD_SOF			8108
+#define STR_PARAM_N_IRQ_SENT			8109
+#define STR_PARAM_N_ATTN_RCVD			8110
+#define STR_PARAM_PART_NUM				8111
+#define STR_PARAM_EE_ACK				8112
+#define STR_PARAM_EE_VER				8113
+
+#define STR_NETERR_APP_CHKSUM			8114
+#define STR_NETERR_APP_FRAG				8115
+#define STR_NETERR_APP_STRAY			8116
+#define STR_NETERR_APP_OVERRUN			8117
+#define STR_NETERR_DIAG_CHKSUM			8118
+#define STR_NETERR_DIAG_FRAG			8119
+#define STR_NETERR_DIAG_STRAY			8120
+#define STR_NETERR_DIAG_OVERRUN			8121
+
+#define STR_PARAM_POSN_CAP_INA_HI_SPD	8122
+#define STR_PARAM_POSN_CAP_INB			8123
+
+
+
+
+#define STR_PARAM_DATA_AQ_SET			8200
+#define STR_PARAM_THRES0				8201
+#define STR_PARAM_THRES1				8202
+#define STR_PARAM_THRES2				8203
+#define STR_PARAM_THRES3				8204
+#define STR_PARAM_THRES4				8205
+#define STR_PARAM_THRES5				8206
+#define STR_PARAM_THRES6				8207
+#define STR_PARAM_THRES7				8208
+#define STR_PARAM_THRES8				8209
+#define STR_PARAM_THRES9				8210
+#define STR_PARAM_THRES10				8211
+#define STR_PARAM_THRES11				8212
+
+#define STR_PARAM_ACOEF0				8213
+#define STR_PARAM_ACOEF1				8214
+#define STR_PARAM_ACOEF2				8215
+#define STR_PARAM_ACOEF3				8216
+#define STR_PARAM_ACOEF4				8217
+#define STR_PARAM_ACOEF5				8218
+#define STR_PARAM_ACOEF6				8219
+#define STR_PARAM_ACOEF7				8220
+#define STR_PARAM_ACOEF8				8221
+#define STR_PARAM_ACOEF9				8222
+#define STR_PARAM_ACOEF10				8223
+#define STR_PARAM_ACOEF11				8224
+
+#define STR_PARAM_ANALOGIN0				8225
+#define STR_PARAM_ANALOGIN1				8226
+#define STR_PARAM_ANALOGIN2				8227
+#define STR_PARAM_ANALOGIN3				8228
+#define STR_PARAM_ANALOGIN4				8229
+#define STR_PARAM_ANALOGIN5				8230
+#define STR_PARAM_ANALOGIN6				8231
+#define STR_PARAM_ANALOGIN7				8232
+#define STR_PARAM_ANALOGIN8				8233
+#define STR_PARAM_ANALOGIN9				8234
+#define STR_PARAM_ANALOGIN10			8235
+#define STR_PARAM_ANALOGIN11			8236
+
+#define STR_PARAM_OFFSET10				8237
+#define STR_PARAM_OFFSET11				8238
+#define STR_PARAM_TP_5V					8239
+#define STR_PARAM_TP_12V				8240
+#define STR_PARAM_MAXMIN_SEL			8241
+#define STR_PARAM_ANALOGMAX				8242
+#define STR_PARAM_ANALOGMIN				8243
+#define STR_PARAM_TEST_IN				8244
+#define STR_PARAM_TEST_OUT				8245
+#define STR_PARAM_NFRAGS				8246
+#define STR_PARAM_NBADCHKSUM			8247
+#define STR_PARAM_NSTRAYS				8248
+#define STR_PARAM_IEX_OUT				8249
+#define STR_PARAM_IEX_IN				8250
+#define STR_PARAM_IEX_DEF_OUT			8251
+#define STR_PARAM_IEX_IN_RISE			8252
+#define STR_PARAM_IEX_IN_FALL			8253
+#define STR_PARAM_IEX_USER_OUT			8254
+#define STR_PARAM_USER_EE0				8255
+#define STR_PARAM_USER_EE1				8256
+#define STR_PARAM_USER_EE2				8257  
+#define STR_PARAM_USER_EE3				8258  
+#define STR_PARAM_USER_RAM0				8259  
+#define STR_PARAM_ERR_HIST_INDX			8260  
+#define STR_PARAM_HIST_ELEMENT			8261  
+#define STR_PARAM_CFG_HW				8262
+#define STR_PARAM_CFG_FEAT				8263
+#define STR_PARAM_CFG_TUNE				8264
+#define STR_BUS_AT_ENBL					8265
+
+
+// ISC drive parameters
+#define STR_DRV_VECTOR_RATE      	 	8300 // Vector update rate (Hz)
+#define STR_DRV_ENC_DENS             	8301 // Encoder Dens. (/[turn/pole-pair])
+#define STR_DRV_POLES                	8302 // Motor Pole Count
+#define STR_DRV_MTR_KE               	8303 // Motor: Ke (V/KRPM)
+#define STR_DRV_MTR_OHMS             	8304 // Motor: Resistance (ohm)
+#define STR_DRV_MTR_ELEC_TC          	8305 // Motor: Elect Time Constant (ms)
+#define STR_DRV_RO                   	8306 // Commutation Reference Offset
+#define STR_DRV_RMS_LIM              	8307 // RMS shutdown limit (A)
+#define STR_DRV_RMS_TC               	8308 // RMS time constant (sec) @ 100% trq
+#define STR_DRV_SPEED_LIM            	8309 // Speed Limit (quads/ms)
+#define STR_DRV_COM_CAP              	8310 // Commutation Edge Capture
+#define STR_DRV_ANGLE                	8311 // Commutation Angle Reference (quads)
+#define STR_DRV_KIP                  	8312 // Vector Torque: Kip
+#define STR_DRV_KII                  	8313 // Vector Torque: Kii
+#define STR_DRV_KPL	                 	8314 // Compensator: Kpl
+#define STR_DRV_KV	                 	8315 // Compensator: Kv
+#define STR_DRV_KP                   	8316 // Compensator: Kp
+#define STR_DRV_KI                   	8317 // Compensator: Ki
+#define STR_DRV_KFV                  	8318 // Compensator: Kfv
+#define STR_DRV_KFA                  	8319 // Compensator: Kfa
+#define STR_DRV_KFJ                  	8320 // Compensator: Kfj (jerk ff)
+#define STR_DRV_KFF                  	8321 // Compensator: Kff (fric. ff)
+#define STR_DRV_KNV                  	8322 // Compensator: Knv
+#define STR_DRV_KR                 		8323 // Compensator: Kr
+#define STR_DRV_RASCON               	8324 // RAS setting
+#define STR_DRV_TRQ_BIAS             	8325 // Compensator: Torque Bias (A)
+#define STR_DRV_CMD_DENS				8326 // Cmd Dens. (/[turn/pole-pair])
+										 
+#define STR_DRV_MON0_AMPL        	 	8327 // Monitor Port 0: Scaling
+#define STR_DRV_MON0_VAR             	8328 // Monitor Port 0: Test Point
+#define STR_DRV_MON0_FILT            	8329 // Monitor Port 0: Filter Constant (ms)
+#define STR_DRV_MON1_AMPL        	 	8330 // Monitor Port 1: Scaling
+#define STR_DRV_MON1_VAR             	8331 // Monitor Port 1: Test Point
+#define STR_DRV_MON1_FILT            	8332 // Monitor Port 1: Filter Constant (ms)
+#define STR_DRV_AH_FILT_TC				8333 // Antihunt voltage filter TC (ms)
+
+#define STR_DRV_TRQ_LIM					8334 // Torque Limit  (A)
+#define STR_DRV_NEG_TRQ_LIM             8335 // Negative Torque Limit  (A)
+#define STR_DRV_TRK_ERR_LIM          	8336 // Tracking Error Limit (quad cnts)
+#define STR_DRV_MV_DN_TC             	8337 // Move Done: Time Constant (ms)
+#define STR_DRV_LPB_WINDOW           	8338 // Recovery window maximum
+#define STR_DRV_READY_DELAY          	8339 // Delay from Servo On to Ready
+#define STR_DRV_SERVO_DELAY          	8340 // Delay from LPB exit to servo
+#define STR_DRV_TRQ_FLDBACK          	8341 // Torque foldback value (A)
+#define STR_DRV_HS_TRQ_TRIP             8342 // Foldback Torque Trip Level (A)
+#define STR_DRV_HS_TC                	8343 // Hard Stop: entry delay (ms)
+#define STR_DRV_TRQ_REL_TC           	8344 // Torque Relax Time Constant (ms)
+#define STR_DRV_BUS_VOLTS            	8345 // Bus Voltage (V)
+#define STR_DRV_DRV_I_MAX            	8346 // Current Full Scale (A)
+#define STR_DRV_RMS_MAX              	8347 // Factory RMS limit
+#define STR_DRV_RMS_MAX_TC           	8348 // Factory upper limit for TC
+#define STR_DRV_TP_ANA_IN            	8349 // Analog Input Test Point (%)
+#define STR_DRV_TP_IOP               	8350 // I/O testpoint
+#define STR_DRV_TP_IR                	8351 // R Channel testpoint
+#define STR_DRV_TP_IS                	8352 // S Channel testpoint
+#define STR_DRV_ENC_RES              	8353 // Encoder step distance (microns/.01)
+#define STR_DRV_TEMPERATURE			 	8354 // Heatsink temperature
+#define STR_DRV_DIRTY					8355 // Drive parameters changed
+#define STR_DRV_CONFIG					8356 // Drive configuration
+#define STR_DRV_FUZZ_AP					8357 // Fuzzy aperature
+#define STR_DRV_FUZZ_HYST				8358 // Fuzzy hysterisis
+#define STR_DRV_RMS_LEVEL				8359 // RMS level (A)
+#define STR_DRV_TRQ_FLDBACK_NEG     	8360 // Trq foldback (neg)
+#define STR_DRV_HEATSINK				8361 // Heatsink temp (deg C)
+#define STR_DRV_STATUS					8362 // Drive Status
+#define STR_DRV_TRQ_FLDBACK_POS     	8363 // Trq foldback (pos)
+#define STR_DRV_POS_TRQ_LIM				8364 // Positive torque foldback
+#define STR_DRV_TP_5V					8365 // 5V testpoint
+#define STR_DRV_TP_16V					8366 // 16V testpoint
+#define STR_DRV_TP_IBUS					8367 // IBUS testpoint
+#define STR_EXT_CONFIG					8368 // Extended configuration
+#define	STR_DRV_IR_CAL					8369 // Ir calibration 
+#define	STR_DRV_IS_CAL					8370 // Is calibration
+#define STR_DRV_TP_VBUS					8371 // VBUS testpoint
+#define STR_DRV_TRQ_CMD					8372 // Trq/Frc Command
+#define STR_DRV_TRQ_MEAS				8373 // Trq/Frc Measured
+#define STR_DRV_TRQ_FB_POS_TC			8374
+#define STR_DRV_TRQ_FB_NEG_TC			8375
+#define STR_DRV_HS_FB_TC				8376
+#define STR_DRV_HS_FLDBACK				8377
+#define STR_DRV_MVDN_FB					8378
+#define STR_DRV_MVDN_FB_TC				8379
+#define STR_DRV_STATUS_RT				8380 // Drive Status
+#define STR_DRV_LD_SPEED_LIM			8381
+#define STR_DRV_RMS_INIT				8382
+#define STR_PARAM_SAFESTATUS			8383 // NCS Safety Status
+#define STR_PARAM_LASTSAFESTATUS		8384
+#define STR_OUT_REQ_REG					8385
+#define STR_PARAM_FAN_SPEED				8386	
+#define STR_PARAM_FAN_SPEED_MIN			8387 
+#define STR_DRV_HLESS_TRQ				8388
+#define STR_DRV_HS_QUAL_SPEED			8389
+#define AVAILABLE____6					8390
+#define AVAILABLE____7					8391
+#define STR_DRV_KNV_AH					8392
+#define STR_P_IEX_USER_OUT				8393
+#define STR_P_IEX_IN_RISE				8394
+#define STR_P_IEX_IN_FALL				8395
+#define STR_P_IEX_STOP_OUT				8396
+#define STR_P_IEX_OUT_REG				8397
+#define STR_P_IEX_IN_REG			8398
+#define STR_P_IEX_IN_ATTN_MASK			8399
+#define STR_P_IEX_GLITCH_TOLERANCE		8400
+//#define STR_P_IEX_STARTUP_DELAY			8401
+//#define STR_P_IEX_STARTUP_TRIES			8402
+#define STR_P_IEX_STATE_REG				8403
+#define STR_P_IEX_RISE_ATTN_MASK		8404
+#define STR_P_IEX_FALL_ATTN_MASK		8405
+#define STR_P_IEX_SUFFIX				8406 // Suffix to strip off if necesary
+#define STR_P_POSN1_CAP_INDEX			8407
+#define STR_P_POSN1_MEAS32				8408
+#define STR_P_TEMP_SIM					8409
+#define STR_P_DRV_PWR_LIM_EXP			8410
+#define STR_P_DRV_RES_MIN				8411
+#define STR_P_FAN_ON_TEMP				8412
+#define STR_P_DSP_INFO					8413
+#define STR_P_IB_FILT_TC				8414
+#define STR_P_IB_TRIP					8415
+#define STR_P_PHASE_TRIP				8416
+#define STR_P_IB_RT						8417
+#define STR_P_IB_RMS					8418
+#define STR_P_PWBA_TEMP					8419
+#define STR_P_IR_IS_TP_FILT_TC			8420
+#define STR_DRV_TRK_MAX					8421
+#define STR_DRV_TRK_MIN					8422
+#define STR_DRV_AH_HOLDOFF				8423
+#define STR_P_TSPD						8424
+#define STR_DRV_ANTIHUNT2				8425
+#define STR_ON_TIME						8426
+#define STR_CTL_STOP_OUT_REG			8427
+#define STR_DRV_STEPPER_TRQ				8428
+#define STR_DRV_STEP_IDLE_TRQ			8429
+#define STR_DRV_STEP_ACC_TRQ			8430
+#define STR_DRV_STEP_FB_TC				8431
+#define STR_DRV_CPL_ERR_LIM				8432
+#define STR_DRV_STEP_DENS				8433
+#define STR_DRV_COMM_CHK_ANGLE_LIM		8434
+#define STR_DRV_HLESS_RAMPUP_TIME		8435
+#define STR_DRV_HLESS_SWEEP_TIME		8436
+#define STR_DRV_HLESS_SETTLE_TIME		8437
+#define STR_DRV_TRQ_FILT_TC				8438
+#define STR_DRV_AH_GAIN					8439
+#define STR_NETERR_LOW_VOLTS			8440
+#define STR_P_BAD_TSPD_CNT				8441
+#define STR_P_BAD_SLOT_CNT				8442
+#define STR_P_LOAD_SLOT0	 			8443
+#define STR_P_LOAD_SLOT1	 			8444
+#define STR_P_LOAD_SLOT2	 			8445
+#define STR_P_LOAD_SLOT3	 			8446
+#define STR_P_AVG_LOAD	 				8447
+#define STR_PARAM_TP_REF				8448
+#define STR_DRV_KZERO					8449
+#define STR_DRV_IZERO					8450
+#define STR_DRV_TARGET_WIN				8451
+#define STR_DRV_STAB_WIN				8452
+#define STR_DISABLE_TC					8453		
+#define	STR_DISABLE_PULSE_TC				8454
+#define	STR_INPUT2_TC					8455
+#define	STR_INPUT_MASKS					8456
+#define STR_HOME_VEL					8457
+#define STR_HOME_OFFS					8458
+#define STR_ABS_POSN0					8459
+#define STR_ABS_POSN1					8460
+#define STR_ABS_POSN2					8461
+#define STR_ABS_POSN3					8462
+#define STR_PWM_DEADBAND				8463
+#define STR_PWM_MAX_FREQ				8464
+#define STR_PWM_MIN_FREQ				8465
+#define STR_VEL_FOLLOW_MAX_FRQ			8466
+#define STR_VEL_FOLLOW_MIN_FRQ			8467
+#define STR_VEL_FOLLOW_MAX_VEL			8468
+#define STR_KNOB_MAX_CW					8469
+#define STR_KNOB_MAX_CCW				8470
+#define STR_KNOB_VEL_INCR				8471
+#define STR_PWR_ON_VEL					8472
+#define STR_RAMP2SPD_TRQ_LIM			8473
+#define STR_RAMP2SPD_VEL0				8474
+#define STR_RAMP2SPD_VEL1				8475
+#define STR_RAMP2SPD_VEL2				8476
+#define STR_RAMP2SPD_VEL3				8477
+#define STR_TRQ_FOLLOW_MAX_FRQ			8478
+#define STR_TRQ_FOLLOW_FILTER			8479
+#define STR_TRQ_FOLLOW_OVER_VEL			8480
+#define STR_SWITCH_MV_DX				8481
+#define STR_STOP_QUAL					8482
+#define STR_DRV_HLESS_VOLTS				8483
+#define STR_DRV_HLESS_RDG_SAMPLES		8484
+#define STR_DRV_HLESS_SETUP_SAMPLES		8485
+#define STR_POSN_CMD_HIRES				8486
+#define STR_POSN_MEAS_HIRES				8487
+#define STR_OVER_VOLTS_TRIP				8488
+#define STR_INC_DIST0					8489
+#define STR_INC_DIST1					8490
+#define STR_INC_DIST2					8491
+#define STR_INC_DIST3					8492
+#define STR_DRV_VBUS_CAL				8493
+#define STR_PARAM_TP_REF_SIM			8494
+#define STR_DRV_BUS_VOLTS_SIM			8495
+#define STR_DRV_CLAMP_FB				8496
+#define STR_DRV_CLAMP_FB_TC				8497
+#define STR_ENC_QUAL					8498
+#define STR_SLESS_MIN_VOLTS				8499
+#define STR_SLESS_MIN_I					8500
+#define STR_SLESS_MAX_I					8501
+#define STR_SLESS_MIN_PH_I				8502
+#define STR_SLESS_MAX_I_DIFF			8503
+#define STR_P_IR_OFFSET					8504
+#define STR_P_IS_OFFSET					8505
+#define STR_P_OVER_TEMP					8506
+#define	STR_INPUT1_TC					8507
+#define STR_BNF_CW_VEL_LIMIT			8508
+#define STR_BNF_CCW_VEL_LIMIT			8509
+#define STR_USR_DESC0					8510		
+#define STR_USR_DESC1					8511			
+#define STR_USR_DESC2					8512			
+#define STR_USR_DESC3					8513			
+#define STR_USR_DESC4					8514			
+#define STR_TRQ_FOLLOW_MAX_SPD			8515
+#define STR_DRV_HS_TRQ_LIM				8516
+#define STR_PWRUP_HOLDOFF_TIME			8517
+#define STR_COMM_LOW_V					8518
+#define STR_XPS_OUTPUT_SRC_REG			8519
+#define STR_XPS_FEAT_00				    8520
+#define STR_XPS_FEAT_01				8521
+#define STR_XPS_FEAT_02				8522
+#define STR_XPS_FEAT_03				8523
+#define STR_XPS_FEAT_04				8524
+#define STR_XPS_FEAT_05				8525
+#define STR_XPS_FEAT_06				8526
+#define STR_XPS_FEAT_07				8527
+#define STR_XPS_FEAT_08				8528
+#define STR_XPS_FEAT_09				8529
+#define STR_XPS_FEAT_10				8530
+#define STR_XPS_FEAT_11				8531
+#define STR_XPS_FEAT_12				8532
+#define STR_XPS_FEAT_13				8533
+#define STR_XPS_FEAT_14				8534
+#define STR_XPS_FEAT_15				8535
+#define STR_XPS_INVERT_INPUT			8536
+#define STR_XPS_INVERT_OUTPUT			8537
+
+// Units strings
+#define STR_TICK						9000
+#define STR_US							9001
+#define STR_MS							9002
+#define STR_S							9003
+#define STR_TICK_MS						9004
+#define STR_TICK_US						9005
+#define STR_TICK_MS2					9006
+#define STR_TICK_MSAMP					9007
+#define STR_TICK_USAMP					9008
+#define STR_TICK_MSAMP2					9009
+#define STR_SAMPLE						9010
+#define STR_POSN						9011
+#define STR_VEL							9012
+#define STR_HZ							9013
+#define STR_MICRON						9014
+#define STR_OHMS						9015
+#define STR_DEG_ELECT					9016
+#define STR_VOLTS						9017
+#define	STR_AMPS						9018
+#define STR_PCT_MAX						9019
+#define	STR_DEG_C						9020
+#define STR_RPM							9021
+#define STR_HOURS						9022
+ 
+// Error base
+#define STR_ERR_BASE					20000
+#define STR_ERR_OK				    	20000	// OK
+#define STR_ERR_FAIL					20001	// Function failed.
+#define STR_ERR_TIMEOUT					20002	// Failed due to time-out
+#define STR_ERR_CHECKSUM				20003	// Packet checksum error.
+#define STR_ERR_DEV_ADDR				20004	// Device selected is out of range
+#define STR_ERR_TOO_MANY				20005	// There are too many nodes on the net.
+#define STR_ERR_RESP_FMT				20006	// Response is garbled.
+#define STR_ERR_RESP_ADDR				20007	// Response is from wrong node.
+#define STR_ERR_OFFLINE					20008	// Node is offline.
+#define STR_ERR_PARAM_RANGE				20009	// Parameter is out of range.
+#define STR_ERR_MEM_LOW					20010	// Memory is low.
+#define STR_ERR_OS						20011	// Operating System Error: %d.
+#define STR_ERR_CLOSED					20012	// Attempting to use a closed Network Controller.
+#define STR_ERR_VALUE					20013	// Value requested is invalid.
+#define STR_ERR_FRAME					20014	// Command packet error.
+#define STR_ERR_UNKN_DEVICE				20015	// Attempting to use an unknown node.
+#define STR_ERR_DEV_WAIT_TO				20016	// Time-out waiting for command access
+#define STR_ERR_PKT_ERR					20017	// Packet length != buffer length.
+#define STR_ERR_BUF_OVERFLOW			20018	// RX buffer overflow.
+#define STR_ERR_RX_ACCESS				20019	// RX buffer access/sync problem.
+#define STR_ERR_NOT_IMPL				20020	// Feature not implemented.
+#define STR_ERR_PORT_PROBLEM			20021
+#define STR_ERR_TX_BUSY					20022	// TX Buffer full
+#define STR_ERR_IN_SERIAL_PORT			20023	// Can't command in serial port mode.
+#define STR_ERR_PARAM_NOT_INIT			20024	// Parameter Database not initialized.
+#define STR_ERR_TEST_INCOMPLETE			20025	// Initialization tests incomplete due to old firmware.
+#define STR_ERR_IRQ_FAILED				20026	// Interrupt interface appears broken.
+#define STR_ERR_CMD_OFFLINE				20027	// Command attempt while net offline.
+#define STR_ERR_ADDR_LOCK				20028	// Address is locked
+#define STR_ERR_RESOURCE_BUSY			20029	// Resource is busy
+#define STR_ERR_ATTN_OVERRUN			20030	// Attention buffer has overflown
+#define STR_ERR_NO_TEST_INIT_ERR		20031	// No net test/further initialization errors
+#define STR_ERR_P2P_MOVE_TIMEOUT		20032	// Move segment timed out
+#define STR_ERR_P2P_DELAY_TIMEOUT		20033	// 0x2a Delay segment timed out
+#define STR_ERR_DEPRECATED				20034	// Deprecated API called
+#define STR_ERR_NET_ERRS				20035	// Net errors detected
+#define STR_ERR_NO_NODES				20036	// No nodes detected
+#define STR_ERR_DATAACQ_ERR				20037	// Invalid data point
+#define STR_ERR_DATAACQ_EMPTY			20038	// No Points found
+#define STR_ERR_BADARG					20039	// Bad command argument.
+#define STR_ERR_WRONG_NODE_TYPE			20040	// Interaction with wrong node type
+#define STR_ERR_BAUD_NOT_SUPPORTED		20041	// Unsupported baud rate
+#define STR_ERR_SEND_FAILED				20042	// Could send command. 
+#define STR_ERR_SEND_LOCKED				20043	// Could not acquire command interface. 
+#define STR_ERR_SEND_UNLOCK				20044	// Could not release command interface.
+#define STR_ERR_RESP_FAILED				20045	// Response failed to transfer.
+#define STR_ERR_RESP_TIMEOUT			20046	// NC response not found in time.
+#define STR_ERR_CMD_TIMEOUT				20047	// Command timeout.
+#define STR_ERR_CANCELED				20048	// Command canceled.
+#define STR_ERR_THREAD_CREATE			20049	// Thread create error.
+#define STR_ERR_UNSOLICITED				20050	// Unsolicted response detected.
+#define STR_ERR_DEF_RESP_TO				20051	// Deferred response time-out.
+#define STR_ERR_ADDR_RANGE				20052	// Response from out of range address.
+#define STR_ERR_WRONG_SRC				20053	// Response from wrong source.
+#define STR_ERR_FLUSH_MANY				20054	// Flush finding many characters.
+#define STR_ERR_PRIO_FAILED				20055	// Failed to set thread priority.
+#define STR_ERR_NET_DIAG_FAILED			20056	// Network diagnostic problems detected.
+#define STR_ERR_RD_COMM_IRQ				20057	// Could not start the read COMM IRQs.
+#define STR_ERR_NULL_RETURN				20058	// Read returned NULL buffer
+#define STR_ERR_RESET_FAILED			20059	// Reset command failed
+#define STR_ERR_LOG_CHANGED				20060	// Log extraction during change
+#define STR_ERR_DATAACQ_OVERRUN			20061	// Data acquisition overrun
+#define STR_ERR_HOST_APP_OVERRUN		20062	// Host's application port over-run
+#define STR_ERR_HOST_DIAG_OVERRUN		20063	// Host's diagnostic port over-run
+#define STR_ERR_FILE_WRITE				20064	// Configuration file failed to write
+#define STR_ERR_FILE_OPEN				20065	// Configuration file failed to open   
+#define STR_ERR_FILE_WRONG				20066	// Configuration file is for wrong node
+#define STR_ERR_FILE_BAD				20067	// Configuration file corrupt   
+#define STR_ERR_FILE_ENABLED			20068	// Configuration file load requires disabled node. 
+#define STR_ERR_CMD_IN_ATTN				20069	// Network comm attempt during attention processing
+#define STR_ERR_APP_NET_ONLY			20070	// Function only works on App Net
+#define STR_ERR_24V_OFF					20071	// Canceled due to lack of 24V supply
+
+
+// These are deprecated	from ControlPoint
+
+// MN_ERR_NET_ERR_BASE items
+#define STR_ERR_KERN_FRAG_PKT			20288	// Net Reject: Fragmented packet detected.
+#define STR_ERR_ND_CHKSUM				20289	// Net Reject: Detected bad checksum on network packet.
+#define STR_ERR_KERN_STRAY_DATA			20290	// Net Reject: Stray Data detected
+#define STR_ERR_PORT_OVERRUN			20291	// Net Reject: Port Overrun
+
+/* ----------- #define STR_ERR_BASE+MN_ERR_CMD_ERR_BASE ------------------------
+The result of a node rejecting a command
+*  ---------------------------------------------------------------------- */
+#define STR_ERR_NODE_INTERNAL			20256	// Node Reject: Generic Error
+#define STR_ERR_UNKNOWNCMD				20257	// Node Reject: Unknown command on this node.
+#define STR_ERR_NODE_BADARG				20258	// Node Reject: Bad command argument.
+#define STR_ERR_RO						20259	// Node Reject: Attempt to update Read-Only parameter.
+#define STR_ERR_EEHW					20260	// Node Reject: EE hardware fault.
+#define STR_ERR_ACCESS_LVL				20261	// Node Reject: Access level violation
+#define STR_ERR_MOVE_BUFFER_FULL		20262	// Node Reject: Move buffer is full move, move ignored.
+#define STR_ERR_MOVE_SPEC				20263	// Node Reject: Move spec issue
+#define STR_ERR_MOVE_NSTOP				20264	// Node Reject: Node-stop blocked move.
+#define STR_ERR_MOVE_RANGE				20265	// Node Reject: Move attempt is out of range
+#define STR_ERR_MOVE_SHUTDOWN			20266	// Node Reject: Move attempt in shutdown
+#define STR_ERR_IEX_ERROR				20267	// Node Reject: IEX interaction while stopped
+#define STR_ERR_MOVE_BLOCKED			20268	// Node Reject: Move attempt while blocking alert present
+#define STR_ERR_MOVE_HOMING				20269	// Node Reject: Move attempt while homing running
+#define STR_ERR_IN_MOTION				20272	// Node Reject: Command attempted while node in motion
+
+
+
+/* ----------- #define STR_ERR_BASE+MN_ERR_LOGIC_ERR ----------------------------
+   The result of a node rejecting a command
+*  ---------------------------------------------------------------------- */
+//#define STR_ERR_LOGIC_ERR 				20256	// Rejected by node: errCode[0..255]
+//#define STR_ERR_NC_CHKSUM				20257	// Node Reject: NC detected bad checksum on network packet.
+//#define STR_ERR_FORMAT					20262	// Node Reject: Command format error.
+//#define STR_ERR_UNKNOWNPARAM			20264	// Node Reject: Unknown parameter on this node.
+//#define STR_ERR_RX_TIMEOUT				20265	// Node Reject: Response did not arrive in time.
+//#define STR_ERR_MOVE					20267	// Node Reject: Move generation error.
+#define STR_ERR_INVALID_NODE			20270	// Node Reject: Invalid node.
+#define STR_ERR_IEEE_FRAGPKT_ERROR		20271	// Node Reject: Fragmented packet detected @ IEEE interface.
+#define STR_ERR_HW_MEM_ERROR			20272	// Node Reject: Command failure from hardware memory error.
+#define STR_ERR_RUNTIME_ERROR			20273	// Node Reject: Unknown run time error.
+#define STR_ERR_MV_ENC_SPD_LIM			20275	// Node Reject: Speed exceeds encoder limit
+#define STR_ERR_IEX_CONFIG				20276	// Node Reject: IEX configuration probl
+#define STR_ERR_SINE_ARGS				20277	// Node Reject: Sine argument problem
+#define STR_ERR_MOVE_UNSUPP				20278	// Node Reject: Move Not Supported
+#define STR_ERR_PARAM_UNSUPP			20279	// Node Reject: Parameter Not Supported
+/* -------- END OF #define STR_ERR_BASE+MN_ERR_LOGIC_ERR GROUP ------------------*/
+
+
+/* -------- END OF NETWORK ERROR GROUP ---------------------*/
+#define STR_ERR_NET_ERR_BASE			20768
+
+// Connectivity is not present on this net
+#define STR_ERR_BRK_DIAG_LOC_UNKNOWN 	(STR_ERR_NET_ERR_BASE+0xfc)
+#define STR_ERR_BRK_APP_LOC_UNKNOWN 	(STR_ERR_NET_ERR_BASE+0xfd)
+#define STR_ERR_BRK_LOC_UNKNOWN     	(STR_ERR_NET_ERR_BASE+0xfe)
+#define STR_ERR_NO_NET_CONNECTIVITY		(STR_ERR_NET_ERR_BASE+0xff)	
+
+// Node x was found offline
+#define STR_ERR_NODE_OFFLINE_0			(STR_ERR_NET_ERR_BASE+0xa0)	
+#define	STR_ERR_NODE_OFFLINE_31			STR_ERR_NODE_OFFLINE_0 + 31
+
+// xxxx060x errors
+#define STR_ERR_INIT_FAILED_BASE		21536	// Init error base messages (8 long)
+												// Spare 8 more
+// xxxx070x errors
+#define STR_ERR_PORT_FAILED_BASE		21792	// Port error base messages (8 long)
+												// Spare 8 more
+// xxxx080x errors
+#define STR_ERR_BAUD_FAILED_BASE		22048	// Baud error base messages (8 long)
+												// Spare 8 more
+
+// Next default values for new objects
+// 
+#ifdef APSTUDIO_INVOKED
+#ifndef APSTUDIO_READONLY_SYMBOLS
+#define _APS_NEXT_RESOURCE_VALUE        101
+#define _APS_NEXT_COMMAND_VALUE         40001
+#define _APS_NEXT_CONTROL_VALUE         1000
+#define _APS_NEXT_SYMED_VALUE           101
+#endif
+#endif
+
+// VERSIONING ITEMS
+#if _DEBUG
+#define VER_FILEDESCRIPTION_STR		"Meridian/ClearPath Network Driver (debug-not for release)"
+#else
+#define VER_FILEDESCRIPTION_STR     "Meridian/ClearPath Network Driver"
+#endif
+#ifdef _TEKNIC_DLL
+#define VER_INTERNALNAME_STR        "MNuserDriver20.dll"
+#else
+#define VER_INTERNALNAME_STR        "sFoundation20.dll"
+#endif
+#define VER_FILEFLAGSMASK			VS_FFI_FILEFLAGSMASK
+#define VER_FILEOS          		VOS_NT_WINDOWS32
+#define VER_FILEFLAGS				0
+#define VER_FILETYPE				VFT_DLL
+#define VER_FILESUBTYPE				VFT2_DRV_SYSTEM
+#define VER_ORIGINALFILENAME_STR	VER_INTERNALNAME_STR
+#define VER_COMPANYNAME_STR 		"Teknic, Inc."
+#if _WIN64
+#define VER_PRODUCTNAME_STR 		"Teknic Meridian™ & ClearPath Technology (x64)"
+#else
+#define VER_PRODUCTNAME_STR 		"Teknic Meridian™ & ClearPath Technology (x86)"
+#endif
+#define VER_LEGALCOPYRIGHT_YEARS    "1998-2017"
+#define VER_LEGALCOPYRIGHT_STR		"(C) Teknic, Inc." VER_LEGALCOPYRIGHT_YEARS
+#define VER_LEGALTRADEMARKS_STR     ""
+#define VER_FILE_MAJOR				2
+#define VER_FILE_MINOR				1
+#define VER_FILE_BUILDNUM			31
+#define VER_PROD_BUILDNUM			VER_FILE_BUILDNUM
+#define VER_FILEVERSION_DW          ((VER_FILE_MAJOR<<24) | (VER_FILE_MINOR<<16) | VER_FILE_BUILDNUM)
+#define VER_PRODUCTVERSION			VER_FILE_MAJOR,VER_FILE_MINOR,VER_FILE_BUILDNUM
+#define VER_PRODUCTVERSION_STR		VER_MK_STR(VER_FILE_MAJOR, VER_FILE_MINOR, VER_FILE_BUILDNUM)
+#define VER_STR(arg) #arg
+#define VER_MK_STR(major, minor, build)  VER_STR(major) "."  VER_STR(minor) "." VER_STR(build)
+#define VER_FILEVERSION				VER_PRODUCTVERSION
+#define VER_FILEVERSION_STR			VER_PRODUCTVERSION_STR
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/tekEvents.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/tekEvents.h
new file mode 100644
index 000000000..f8dfd20ef
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/tekEvents.h
@@ -0,0 +1,53 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc-private/tekEvents.h $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: tekEvents.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	\brief Brief Module Description
+
+	This file selects the proper platform specific events, mutexes, and other
+	primatives header file based on the project defined macros.
+	
+**/
+//
+// CREATION DATE:
+//		01/18/2011 13:54:56
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2011-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+#ifndef _tekEvents_h
+#define _tekEvents_h
+
+//*****************************************************************************
+// !NAME!																      *
+// 	tekEvents.h headers included
+//
+	#if (defined(_WIN32)||defined(_WIN64))	// MS Windows
+        #include "tekEventsWin32.h"
+	#elif defined __QNX__					// QNX
+        #include "tekEventsQNX.h"
+	#else									// Linux
+        #include "tekEventsLinux.h"
+	#endif
+//																			  *
+//*****************************************************************************
+
+
+#endif
+
+
+//============================================================================= 
+//	END OF FILE tekEvents.h
+// ============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/tekThreads.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/tekThreads.h
new file mode 100644
index 000000000..90d070afc
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/tekThreads.h
@@ -0,0 +1,218 @@
+//***************************************************************************
+// $Header:: /ClearPath SC-1.0.123/User Driver/inc-private/tekThreads.h 26   $
+//
+// NAME
+//		Thread.h
+//
+// DESCRIPTION:
+//		Thread virtual class template.
+//
+// CREATION DATE:
+//		03/10/2004 14:18:41
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2004-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+//																			  *
+//*****************************************************************************
+#ifndef _THREAD_H_
+#define _THREAD_H_
+
+//***************************************************************************
+// NAME																        *
+// 	Thread.h headers
+//																			*/
+	#include "tekEvents.h"
+	#ifdef THREAD_SLOTS
+		#include "sigslot.h"
+	#endif
+	#include <cstdlib>
+//																			  *
+//*****************************************************************************
+
+#if !(defined(_WIN32)||defined(_WIN64))
+        #define THREAD_PRIORITY_BELOW_NORMAL -1
+#endif
+
+//***************************************************************************
+// NAME																	    *
+// 	Thread.h function prototypes
+//
+//
+
+/***************************************************************************/
+
+
+
+//*****************************************************************************
+// NAME																		  *
+// 	Thread.h constants
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																		  *
+// 	CThread Class
+//
+// DESCRIPTION:
+///	This pure virtual class allows for the easy cross-platform construction
+/// and use of threads. The <Run> function will start and should continue to
+/// run until it's completion or the detection of the <*m_pTermFlag>. To
+/// prevent application deadlock the termination flag should be checked
+/// regularly and/or make sure to implement a destructor to cause the
+/// thread to terminate.
+///
+/// To create a thread:
+//		1) Derive a new class inheriting this class
+///		2) Implement the function int Run(void *context). The context
+///		   pointer will point to any data passed in on the <LaunchThread>
+///		   function.
+///		3) Optionally, setup a common termination flag via <SetTerminateFlag>.
+///		   A common flag in your application may then set this flag to
+///		   initiate a shutdown.
+///		4) For Windows based systems, an ActiveX apartment initialization
+///		   may be executed via the <UseWithCOM()>.
+///
+///		5) Once setup, call <LaunchThread()> to start the <Run> function
+///		   in a new thread.
+///
+///	You may call <TerminateAndWait()> to force a thread to terminate. This
+/// function returns when the thread has stopped.
+//
+class CThread
+{
+private:
+	#if (defined(_WIN32)||defined(_WIN64))
+		static unsigned __stdcall ThreadEntry(void* pArgs);
+		// TRUE if CoInitialize required
+		nodebool m_isCOM;
+		// Use DLL terminate ACK strategy
+		nodebool m_DLLterm;
+		// Thread handle
+		HANDLE m_hThread;
+	#else
+public:
+		// This is the control function run in the thread
+		static void *ThreadEntry(void *pArgs);
+		// Thread handle
+		pthread_t m_hThread;
+	#endif
+
+protected:
+
+#define THREAD_RET_TYPE
+	nodebool *m_pTermFlag;					// TRUE to terminate thread
+	nodebool m_lclOwnTerm;					// TRUE if we allocated m_pTermFlag
+	nodebool m_running;						// TRUE during thread function execution
+	// Function to run in the new thread
+	void constructInit(nodebool isCom=false);
+	CCCriticalSection m_exitSection;		// Critical section for access to isRunning
+	// Seed that was used to init random # generator
+	unsigned int m_seed;
+	// Status return of exiting thread control function
+	void *m_status;
+	// Last error code
+	nodeulong m_lastErr;
+
+public:
+	CCEvent m_TermEvent;					// Termination ACK event
+	// (optional) Event prior to running. Can be used to wait for thread
+	// function launch and initialization complete.
+	CCEvent m_ThreadParkedEvent;
+
+	void *m_context;						// Thread context pointer
+	virtual int Run(void *context)=0;
+	static void Sleep(Uint32 milliseconds);
+	// Create the thread
+	HANDLE LaunchThread(void *context = NULL, int priority = 0);
+#ifdef THREAD_SLOTS
+	signal0<> ShuttingDown;					// Signal at termination time
+	signal0<> Shutdown;						// Signal as terminating
+#endif
+	// NOTE: these unsigned int are required for WIN32/WIN64 
+	unsigned int m_idThread;				// Thread ID
+	unsigned int m_idThreadSaved;			// Saved m_idThread for debug
+	nodeulong m_uiID;						// Saved UI thread ID
+	// Wait for thread to terminate
+	nodebool WaitForTerm();
+	// Terminate the thread via term flag
+	virtual HANDLE Terminate();
+	// Terminate and wait for exit
+	virtual void TerminateAndWait();
+	// Detect if thread is terminating or has terminated
+	nodebool Terminating()
+	{
+		nodebool returnValue = (m_hThread == 0);
+		if (m_pTermFlag != NULL)
+		{
+			returnValue = (*m_pTermFlag || (m_hThread == 0));
+		}
+		return(returnValue);
+	}
+	// Setup a common terminate flag
+	void SetTerminateFlag(nodebool *flag);
+
+	// Returns the OS specific thread ID for this instance. This
+	// ID is useful when debugging to identify a thread using
+	// the operating system's debugger ability to show threads
+	// associated with the current process.
+	nodeulong ThreadID() {
+		return(nodeulong(m_idThreadSaved));
+	}
+
+	// Return the UI thread ID for the current thread
+	nodeulong UIthreadID();
+
+	// Returns the seed used for the random number generator
+	unsigned int Seed(){
+		return m_seed;
+	}
+
+	// Sets the seed to use for the random number generator
+	void SetSeed(unsigned int seed){
+		// Save the seed
+		m_seed = seed;
+		// Reinit the random # generator
+		srand(1);	// reset random # gen
+		srand(seed);	// set the seed
+	}
+
+	// Returns the operation system's current thread ID.
+	static nodeulong CurrentThreadID();
+
+	// Construction
+	CThread();
+	#if (defined(_WIN32)||defined(_WIN64))
+		CThread(nodebool isCOM);
+		CThread(void *context, int priority, nodebool isCOM = false);
+	// Set to perform ActiveX init/un-inits
+	void UseWithCOM() {
+		m_isCOM = TRUE;
+	}
+
+	// Set DLL terminate strategy, wait for event vs thread handle signal
+	// This is necessary as the handle cannot signal within the DLL coding.
+	void SetDLLterm(nodebool DLLterm) {
+		m_DLLterm = DLLterm;
+	}
+	#endif
+	virtual ~CThread();
+};
+//																			  *
+//*****************************************************************************
+
+#endif
+
+//=============================================================================
+//	END OF FILE Thread.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/valkeys.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/valkeys.h
new file mode 100644
index 000000000..f6185a018
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/sFound/valkeys.h
@@ -0,0 +1,473 @@
+// Do not edit this file, it is auto-created with ValuesLib resources
+const char *ConfigKeys[] = {
+" ",
+"Kv",
+"Ki",
+"Kp",
+"Kfv",
+"Kfa",
+"Kfj",
+"Kip",
+"Kii",
+"Knp",
+"Knv",
+"Kb",
+"Kff",
+"TrqLim",
+"SRate",
+"CfgReg",
+"RO",
+"StepsPerRev",
+"EncDens",
+"EncResol",
+"Poles",
+"ROMsum",
+"InOffset",
+"TrkErrLim",
+"RMSlim",
+"RMStime",
+"ErrCode",
+"Ir",
+"Is",
+"MonAmpl",
+"MonVar",
+"InRngWin",
+"DigTrqMax",
+"Angle",
+"TPana",
+"TPio",
+"FuzzAp",
+"Vbus",
+"MtrOhms",
+"MtrTC",
+"Imax",
+"Ke",
+"SpdLim",
+"MvDnTime",
+"HallCapAngl",
+"RAS",
+"TrqFldBck",
+"HrdStpTrip",
+"HrdStpTime",
+"TrqBias",
+"TrqFBTime",
+"TrqFltTC",
+"MonFltTC",
+"AnaVelMax",
+"EEupdAck",
+"LPBservoDly",
+"LPBreadyDly",
+"LPBwindow",
+"NVmod",
+"SN",
+"RMSmax",
+"RMSmaxTC",
+"Options",
+"VectRate",
+"HWrev",
+"AHfuzz",
+"AHhyst",
+"PosnCmd",
+"PosnMeas",
+"VelCmd",
+"VelMeas",
+"RMSlvl",
+"Status",
+"ADCmax",
+"VBusMeas",
+"TrqMeas",
+"TrqCmd",
+"Heatsink",
+"TP16v",
+"TP5v",
+"FldBckNeg",
+"FldBckPos",
+"FldBckHS",
+"FldBckNegTC",
+"FldBckPosTC",
+"FldBckHSTC",
+"FldBckMvDnTC",
+"FldBckMvDn",
+"StatusRT",
+"OverVTrip",
+"LPBthresh",
+"HrdStpVel",
+"NoCommTrq",
+"KnvAH",
+"TrqInScale",
+"MinTrkErr",
+"MaxTrkErr",
+"EnableCap",
+"AnaInCfg",
+"CfgReg1",
+"CommCfg",
+"GearRes",
+"EStopDec",
+"RMSpeak",
+"MtrTempLock",
+"EnblLock",
+"ThermDly",
+"VelFilt",
+"NoComTime",
+"LdMtrRatio",
+"CplErrLim",
+"Kpl",
+"PosnMtr",
+"PosnLoad",
+"AHfuzz2",
+"GearMain",
+"LdSpdLim",
+"RunErr",
+"PWBAtemp",
+"IrCal",
+"IsCal",
+"PartID",
+"CommMask",
+"CommFact",
+"CalAna",
+"CalOffs",
+"FanTemp",
+"IBtc",
+"IBlim",
+"IPhLim",
+"IB",
+"IBpeak",
+"TPIfilt",
+"VBusOffs",
+"VBusCal",
+"VBusLow",
+"RGenOn",
+"RGenOff",
+"RGenPMax",
+"RGenTC",
+"RGenDPMax",
+"IBoffs",
+"IBcal",
+"TempWarn",
+"OverTemp",
+"FanWarn",
+"FanFault",
+"IBlimRMS",
+"SDdetail",
+"OutReg",
+"InReg",
+"FanSpd",
+"AcFreq",
+"IBlim3PhRMS",
+"IoffsInh",
+"ACmonFilt",
+"KmFact",
+"MtrOhmsMin",
+"AHhold",
+"AccLim",
+"DecLim",
+"VelLim",
+"HeadDX",
+"TailDX",
+"HTvel",
+"MtrIndx",
+"LdIndx",
+"TSPD",
+"CfgTune",
+"CfgFeat",
+"CfgHW",
+"CfgApp",
+"PN",
+"EEver",
+"ROMupdAck",
+"Alert",
+"WarnRT",
+"WarnMask",
+"WarnAccum",
+"StatSW",
+"StatAcc",
+"StatRT",
+"StatAttn",
+"OnTime",
+"AlertMask",
+"StatRise",
+"StopType",
+"WDogTC",
+"IEXStatus",
+"IEXGlitchCount",
+"IEXGlitchPeak",
+"IEXInReg",
+"IEXInRiseReg",
+"IEXInFallReg",
+"IEXInRegMask",
+"IEXInRiseRgMsk",
+"IEXInFallRgMsk",
+"IEXGlitchLimit",
+"IEXOutReg",
+"IEXUserOutReg",
+"IEXStopOutReg",
+"StepRunAmps",
+"StepIdleAmps",
+"StepAccAmps",
+"StepMicro",
+"RASMaxVel",
+"StepTrqTC",
+"CmdTuneReg",
+"OutSrc",
+"CmdAttack",
+"CmdGStop",
+"CmdMode",
+"CmdDelay",
+"JogVel",
+"JogAccel",
+"CplErr",
+"TrkErr",
+"AAfterDist",
+"BBeforeDist",
+"AtPosnLoc",
+"CommAngleLim",
+"NoCommRamp",
+"NoCommSweep",
+"NoCommSettle",
+"SoftLimPos",
+"SoftLimNeg",
+"AHgain",
+"MvDwell",
+"Kzero",
+"Izero",
+"TgtWindow",
+"StabWindow",
+"KpNormal",
+"KpSoft",
+"KiNormal",
+"KiSoft",
+"Kout",
+"Iout",
+"Ramp2Spd TrqLim",
+"Ramp2Spd Vel0",
+"Ramp2Spd Vel1",
+"Ramp2Spd Vel2",
+"Ramp2Spd Vel3",
+"VelKnob MaxCWVel",
+"VelKnob MaxCCWVel",
+"VelKnob VelScale",
+"Homing Speed",
+"AbsPosn Posn0",
+"AbsPosn Posn1",
+"AbsPosn Posn2",
+"AbsPosn Posn3",
+"SpinOnPwr UI Vel",
+"Mv2Sw DistTilSw",
+"StopQualTime",
+"VelFollow PWM Deadband",
+"VelFollow MaxFreq",
+"VelFollow MinFreq",
+"VelFollow MaxSpeed",
+"Homing Offset",
+"TrqFollow MaxTrq",
+"TrqFollow OverSpd Time",
+"TrqFollow TrqFiltTC",
+"DisableFiltTC",
+"TrigMinPulseTime",
+"InBFiltTC",
+"InStim",
+"HLFB MaxVel",
+"Active CmdRes",
+"Base Unit",
+"TP 1.65V",
+"TP 12V",
+"IncPosn Dist0",
+"IncPosn Dist1",
+"IncPosn Dist2",
+"IncPosn Dist3",
+"InductRdg",
+"InductSetup",
+"InductAmps",
+"RMSinitLvl",
+"VBusMax",
+"HLFBDutyPct",
+"PWMInFreqOvr",
+"PWMInDutyOvr",
+"PulseVelAdj",
+"PulseIncrAdj",
+"SetFlags",
+"RuntimeFlags",
+"ClampTrq",
+"ClampTC",
+"ATstrokeMax",
+"ATstrokeMin",
+"ATmaxVel",
+"ATmaxAcc",
+"ATmaxTrq",
+"ATmaxVolts",
+"Kp-zero",
+"Kp-out",
+"Ki-zero",
+"Ki-out",
+"Kt",
+"KvBase",
+"Kii(0)",
+"Kii(1)",
+"Kii(2)",
+"Kii(3)",
+"Kii(4)",
+"Kii(5)",
+"Kii(6)",
+"Kii(7)",
+"Kii(8)",
+"Kii(9)",
+"Kip(0)",
+"Kip(1)",
+"Kip(2)",
+"Kip(3)",
+"Kip(4)",
+"Kip(5)",
+"Kip(6)",
+"Kip(7)",
+"Kip(8)",
+"Kip(9)",
+"StopQualVel",
+"AltSpdLim",
+"InductVolts",
+"PWMCmdPct",
+"PWMFreq",
+"PWMDutyPct",
+"R(0)",
+"R(1)",
+"R(2)",
+"R(3)",
+"R(4)",
+"R(5)",
+"R(6)",
+"R(7)",
+"R(8)",
+"R(9)",
+"InAFiltTC",
+"BnF CwVelLim",
+"BnF CcwVelLim",
+"MaxStepRate",
+"RMSlim",
+"RMStime",
+"MaxTravel",
+"Homing Accel",
+"HrdStpDelay",
+"Homing Decel",
+"Homing DistIntoSwitch",
+"DelayFromRAS",
+"KpFactor",
+"KpZFactor",
+"KiFactor",
+"FineTunePosn",
+"BurstMinInFreq",
+"Kr",
+"VelTarget",
+"TrqFollow MaxSpd",
+"AHFiltTC",
+"ValidOpModes",
+"VBusAtEnbl",
+"KnobSpdLim",
+"AutoRAS",
+"AccEnhAmpl",
+"AccEnhPhase",
+"MechPosn",
+"SpinOnPwr Vel",
+"HrdStpAltTrqLim",
+"VelMeasFiltered",
+"IndexCount",
+"Inertia",
+"Static Friction",
+"Viscous Friction",
+"InRngVelWin",
+"Kip Adj",
+"Kii Adj",
+"Eff KpZero",
+"Eff KpOut",
+"Eff KiZero",
+"Eff KiOut",
+"Eff Kip",
+"Eff Kii",
+"VoltsCmd",
+"Entry MaxMotion",
+"VerifyMaxMotion",
+"VerifyMinMotion",
+"VerifyTime",
+"VerifyRampTime",
+"PwrUpHoldoffTime",
+"UsrDesc",
+"CfgFldbk",
+"XPSOutSrcReg",
+"XPSInvertIn",
+"XPSInvertOut",
+"XPSFeatEnable",
+"XPSFeatCapture",
+"XPSFeatTrigger",
+"XPSFeatNodeStop",
+"XPSFeatResetTimer",
+"XPSFeatAttn0",
+"XPSFeatAttn1",
+"XPSFeatAtHome",
+"XPSFeatPosTrqFldbk",
+"XPSFeatNegTrqFldbk",
+"XPSFeatInPosLim",
+"XPSFeatInNegLim",
+"XPSInSrcReg",
+"XPSUserInReg",
+"XPSUserOutReg",
+"XPSStatusInReg",
+"XPSInReg",
+"DelayDisable",
+"AttnMaskDrvr",
+"GrpShutdownMask",
+"InputActions",
+"SoftLim1",
+"SoftLim2",
+"PosnCap InA-HiSpd",
+"PosnCap InB",
+"CommLowV",
+"TP Supply1",
+"VRSoff",
+"VRStc",
+"VRSon",
+"UnderTempTrip",
+"EncoderTemp",
+"StatorTemp",
+"OverTempTripStator",
+"OverTempWarnStator",
+"PwrReg",
+"VectorDriftLim",
+"PhaseBoardSN",
+"PhaseBoardRev",
+"TP PhaseBoard",
+"DriveTemp",
+"AlertAccum",
+"AccelAlertLim",
+"CfgApp1",
+"InA CmdPct",
+"InA Freq",
+"InA Duty",
+"AltTrqLim",
+"AsymTrqLim00",
+"AsymTrqLim01",
+"AsymTrqLim10",
+"AsymTrqLim11",
+"AltTrqTC",
+"PWMCMaxVel",
+"RMSSlowLim",
+"RMSSlowTC",
+"RMSSlowLvl",
+"VBusAdjRate",
+"SoftStartFreq",
+"InASwCmdPct",
+"PWMCInADutyOut",
+"PosnRecVel",
+"PosnRecAcc",
+"MinOperV",
+"PwrShutdownMask",
+"AC Loss TC",
+"PhaseLossTC",
+"IBtcSlow",
+"OverTempUser",
+"ShutdownMask",
+"ACWiringErrorTC",
+"IBLimUser",
+"IndexDetectSpeedLim",
+"RMSStoppedFactor",
+"RMSStoppedSpeed",
+"MoveOptions",
+""
+};
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/version.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/version.h
new file mode 100644
index 000000000..bcd48a3a4
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-private/version.h
@@ -0,0 +1,57 @@
+/*****************************************************************************
+* version.h file
+*
+* Written by Gary Webb
+* Copyright September 26, 2000
+*
+* Use CVersionInfo to obtain information from the version resource of your
+* application, or specify a valid path to another executable to obtain its
+* version information.
+*
+* The implementation file is version.cpp lives in LibLinuxOS and LibWinOS
+*****************************************************************************/
+#ifndef CVersionInfo_Class_File
+#define CVersionInfo_Class_File
+
+#ifdef _WIN32
+	#include <windows.h>
+#endif
+	#include <string>
+	#include <list>
+using namespace std;
+//---------------------------------------------------------------------------
+
+class CVersionInfo
+{
+public:
+    CVersionInfo(void);
+    ~CVersionInfo(void);
+    bool SetFilePath(string szPath);
+    bool SetLanguage(int nLanguage);
+    int GetLanguageCount(void);
+    string GetComments(void);
+    string GetCompanyName(void);
+    string GetFileDescription(void);
+    string GetFileVersion(void);
+    string GetInternalName(void);
+    string GetLegalCopyright(void);
+    string GetLegalTrademarks(void);
+    string GetOriginalFilename(void);
+    string GetProductName(void);
+    string GetProductVersion(void);
+    string GetPrivateBuild(void);
+    string GetSpecialBuild(void);
+	string GetFilePath() { return m_pszFilePath; };
+	string GetFileDir();
+private:
+    bool m_bValidPath;
+    bool m_bVersionInfoExists;
+    string m_pszFilePath;
+    int m_nLanguage;
+    int m_nLangCount;
+    list<string> m_lstLangCode;
+    bool GetLanguageCodes(void);
+    string GetData(string szData);
+};
+
+#endif
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/TeknicDevID.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/TeknicDevID.h
new file mode 100644
index 000000000..4027ec14d
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/TeknicDevID.h
@@ -0,0 +1,185 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/TeknicDevID.h $
+// $Revision: 37 $ $Date: 12/09/16 4:07p $
+// $Workfile: TeknicDevID.h $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief Node Type Identifiers and Node Type Container types.
+
+	This header defines the standard device ID container and constants.	 
+	
+	\note This file defines constants for all Teknic product families.
+	Not all node types are available within a product family.
+**/
+// CREATION DATE:
+//		9/13/2006 21:46:33
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2006-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+#ifndef __TEKNICDEVID_H__
+#define __TEKNICDEVID_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	TeknicDevId.h headers
+
+	#include "tekTypes.h"
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	TeknicDevId.h constants
+//
+/**
+	\brief Node class identifiers.	
+	\ingroup LinkGrp
+	@{
+
+	\note Not all devices are available within a product line.
+**/
+typedef enum _nodeIDs {
+	NODEID_UNK,						///< 0 Unknown
+#ifndef OMIT_LEGACY_PRODUCTS
+	NODEID_NC,						// 1 Network Controller
+	NODEID_TG,						// 2 Trajectory Generator
+	NODEID_SC,						// 3 ControlPoint Integrated Servo Controller
+	NODEID_IO,						// 4 IO Cluster
+	NODEID_DA,						// 5 SSt and Eclipse Drives
+	NODEID_NS,						// 6 eFoundation NC
+	NODEID_PS,						// 7 Amazon Power Supply
+#endif
+	NODEID_MD = 8,					///< 8 Meridian Integrated Servo Controller
+	NODEID_CP = 11,					//11 ClearPath Motor
+	NODEID_CS						///<12 ClearPath-SC Motor
+} nodeIDs;							///< Node Identifier Type
+/// @}
+
+/// \cond INTERNAL_DOC
+
+///  Processor Types
+typedef enum {
+	PROC_TARG_UNKNOWN,				//	0 Older type (F240, F2407)
+	PROC_TARG_F240,					//	1 F240
+	PROC_TARG_F2407,				//	2				; F2407
+	PROC_TARG_F2808,				//	3				; F2808
+	PROC_TARG_F2806,				//	4				; F2806
+	PROC_TARG_F28015,				//  5				; F28015
+	PROC_TARG_LM3S628,				//  6				; Stellaris
+	PROC_TARG_F28031,				//  7				; Piccolo
+	PROC_TARG_F28034,				//  8				; Piccolo
+	PROC_TARG_F28062,				//  9				; Piccolo
+	PROC_TARG_F28069,				//  10				; Piccolo
+	PROC_TARG_F28067				//  11				; Piccolo
+} processorTargets;
+
+// Magic number to qualify processor type
+#define ROMINFO_MAGIC 0xa5			 
+/// \endcond 
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	TeknicDevId.h types
+//
+// 
+/**
+	\brief Firmware Version container
+**/
+typedef union _versID {
+	/// Accessor to the bit-orient fields.
+	struct {
+		unsigned buildVers		: 8;	//!< Build version (x .y .\b z)
+		unsigned minorVers		: 4;	//!< Minor version (x. \b y .z)
+		unsigned majorVers		: 4;	//!< Major version (\b x .y .z)
+	} fld;								//!< Field access to version parts.
+	/// Version code as an integer.
+	Uint16 verCode;
+} versID_t;
+
+/**
+	\brief Device ID container
+**/
+typedef union _devID {
+	/// Accessor to the bit-oriented fields.
+	struct {
+		/// Model number.
+		unsigned devModel		: 8;
+		/// Device type from nodeID enumeration
+		nodeIDs devType			: 8;
+	} fld;								//!< Field access to identifier fields.
+	/// Device code as an integer.
+	Uint16 devCode;
+} devID_t;
+
+/**
+	\brief Hardware Version Number
+**/
+typedef union _hwVers {
+	struct {
+		unsigned char Minor;		//!< Minor version
+		unsigned char Major;		//!< Major version: 0=A. 1=B, etc
+	} fld;							//!< Field access to the hardware version.
+	Uint16 revCode;					//!< Bitwise access to the version code.
+} hwVers_t;
+
+/// \cond INTERNAL_DOC
+typedef union _procID {
+	struct {
+		unsigned procType		: 8;
+		unsigned magic			: 8;// Should be ROMINFO_MAGIC
+	} fld;
+	Uint16 procCode;
+} procID_t;
+// Logical device identifier
+typedef struct _TEKDEVID {
+	versID_t versID; 
+	devID_t devID; 
+	procID_t procID; 
+	int16 spare;
+	char copywright[60];
+} tekDevID;
+// Packed version of tekDevID
+typedef struct _TEKDEVIDACKED {
+	// WORD 0: Firmware Version
+	unsigned buildVers		: 8;	//!< Build version (x .y .\b z)
+	unsigned minorVers		: 4;	//!< Minor version (x. \b y .z)
+	unsigned majorVers		: 4;	//!< Major version (\b x .y .z)
+	// WORD 1: Model Version
+	unsigned devModel		: 8;	//!< Model Number
+	/// Device type from nodeID enumeration
+	nodeIDs devType			: 8;	// Device type: TG, NC, etc.
+	// WORD 2: Processor Target
+	unsigned procType		: 8;	// Processor type
+	unsigned magic			: 8;	// Should be ROMINFO_MAGIC
+	// WORD 3: Spare
+	unsigned				: 16;	// Padding/spare
+	// Copyright string
+	char copywright[60];
+} tekDevPacked;
+/// \endcond 
+
+//																			  *
+//*****************************************************************************
+
+#endif
+//============================================================================= 
+//	END OF FILE TeknicDevId.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/mnErrors.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/mnErrors.h
new file mode 100644
index 000000000..7451f55df
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/mnErrors.h
@@ -0,0 +1,575 @@
+//***************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/mnErrors.h $
+// $Revision: 55 $ $Date: 12/09/16 2:00p $
+// $Workfile: mnErrors.h $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief Error Code Definitions for sFoundation. 
+
+	This is the master list of driver error codes. The codes are grouped
+	by host detected, node elicited and initialization types.
+
+	Some codes are bit encoded with a base code and a network number
+	encoded into the code.
+**/
+//
+// CREATION DATE:
+//		12/10/2003 20:16:40
+// 
+// COPYRIGHT NOTICE:
+// 		(C)Copyright 2003-2018  Teknic, Inc.  All rights reserved.
+//
+// 		This copyright notice must be reproduced in any copy, modification, 
+// 		or portion thereof merged into another program. A copy of the 
+// 		copyright notice must be included in the object library of a user
+// 		program.
+//
+/***************************************************************************/
+
+#ifndef __MNERRORS_H__
+#define __MNERRORS_H__
+
+
+//***************************************************************************
+// NAME																	    *   
+// 	mnErrors.h constants
+//
+//
+/// \cond INTERNAL_DOC
+// Standard return codes
+#define MN_ERR_BASE					0x80040000L
+// Basic error ranges
+#define MN_ERR_CMD_ERR_BASE			0x80040100L
+#define MN_ERR_NET_ERR_BASE			0x80040120L
+#define MN_ERR_EXTEND_ERR_BASE		0x80040140L
+#define MN_ERR_NETBREAK_ERR_BASE	0x80040300L
+#define MN_ERR_NETBREAK_ERR_END		(MN_ERR_NETBREAK_ERR_BASE+0xff)
+/// \endcond
+   
+/**
+	\brief S-Foundation API error codes
+
+	These codes are returned by the S-Foundation functions. For the 
+	most part a return of MN_OK signals the requested operation executed
+	correctly.
+
+	Use the infcErrCodeStrA or infcErrCodeStrW functions to convert an 
+	error code into a more detailed message. 
+**/
+typedef enum _cnErrCode {
+	MN_OK,				    	///< 0x0:      	   function succeeded
+	MN_ERR_FAIL=MN_ERR_BASE+1,	///< 0x80040001:   function generically failed
+	MN_ERR_TIMEOUT,				///< 0x80040002:   failed due to time-out
+	MN_ERR_CHECKSUM,			///< 0x80040003:   failed due to checksum failure
+	MN_ERR_DEV_ADDR,			///< 0x80040004:   device addressing problems
+	MN_ERR_TOO_MANY,			///< 0x80040005:   there are too many nodes on the net
+	MN_ERR_RESP_FMT,			///< 0x80040006:   response is garbled
+	MN_ERR_RESP_ADDR,			///< 0x80040007:   response is from wrong address
+	MN_ERR_OFFLINE,				///< 0x80040008:   the node is offline
+	MN_ERR_PARAM_RANGE,			///< 0x80040009:   parameter is out of range
+	MN_ERR_MEM_LOW,				///< 0x8004000a:   memory is low
+	MN_ERR_OS,					///< 0x8004000b:   operating system error
+	MN_ERR_CLOSED,				///< 0x8004000c:   attempting to use a closed device
+	MN_ERR_VALUE,				///< 0x8004000d:   the value requested is invalid
+	MN_ERR_FRAME,				///< 0x8004000e:   command frame error
+	MN_ERR_UNKN_DEVICE,			///< 0x8004000f:   attempting to use unknown device
+	MN_ERR_DEV_WAIT_TO,			///< 0x80040010:   time-out waiting for command access
+	MN_ERR_PKT_ERR,				///< 0x80040011:   Packet length != buffer length err
+	MN_ERR_BUF_OVERFLOW,		///< 0x80040012:   RX buffer overflow
+	MN_ERR_RX_ACCESS,			///< 0x80040013:   RX buffer access/sync problem
+	MN_ERR_NOT_IMPL,			///< 0x80040014:   feature not implemented
+	MN_ERR_PORT_PROBLEM,		///< 0x80040015:   Serial port driver open failure
+	MN_ERR_TX_BUSY,				///< 0x80040016:   TX Buffer full
+	MN_ERR_IN_SERIAL_PORT,		///< 0x80040017:   In serial port mode
+	MN_ERR_PARAM_NOT_INIT,		///< 0x80040018:   Parameter Database not initialized
+	MN_ERR_TEST_INCOMPLETE,		///< 0x80040019:   Initialization tests incomplete due to old firmware
+	MN_ERR_IRQ_FAILED,			///< 0x8004001a:   Interrupt interface appears broken
+	MN_ERR_CMD_OFFLINE,			///< 0x8004001b:   Command attempt while net offline
+	MN_ERR_ADDR_LOCK,			///< 0x8004001c:   Address is locked
+	MN_ERR_RESOURCE_BUSY,		///< 0x8004001d:   A resource is busy, request canceled
+	MN_ERR_ATTN_OVERRUN,		///< 0x8004001e:   ATTN FIFO over-run
+	MN_ERR_NO_TEST_INIT_ERR,	///< 0x8004001f:   Old firmware/initialization failure
+	MN_ERR_P2P_MOVE_TIMEOUT,	///< 0x80040020:   Move segment time-out
+	MN_ERR_P2P_DELAY_TIMEOUT,	///< 0x80040021:   Delay segment time-out
+	MN_ERR_DEPRECATED,			///< 0x80040022:   Deprecated API element attempt
+	MN_ERR_NET_ERRS_DETECT,		///< 0x80040023:   Network errors detected
+	MN_ERR_NO_NODES_DETECTED,	///< 0x80040024:   No nodes are detected on both the diag and app net
+	MN_ERR_DATAACQ_INVALID,		///< 0x80040025:   There is an invalid dataAcq point detected; Reasons: Dropped packet, data overflow
+	MN_ERR_DATAACQ_EMPTY,		///< 0x80040026:   There is no data acq data point available
+	MN_ERR_BADARG,				///< 0x80040027:   API function passed bad argument
+	MN_ERR_WRONG_NODE_TYPE,		///< 0x80040028:   Interaction with wrong node type
+	MN_ERR_BAUD_NOT_SUPPORTED,	///< 0x80040029:   Port does not support request rate
+	MN_ERR_SEND_FAILED,			///< 0x8004002a:   Send failed
+	MN_ERR_SEND_LOCKED,			///< 0x8004002b:   Could not acquire NC command interface 
+	MN_ERR_SEND_UNLOCK,			///< 0x8004002c:   Could not release NC command interface
+	MN_ERR_RESP_FAILED,			///< 0x8004002d:   Response failed to transfer
+	MN_ERR_RESP_TIMEOUT,		///< 0x8004002e:   Response not found in time
+	MN_ERR_CMD_TIMEOUT,			///< 0x8004002f:   Command timeout
+	MN_ERR_CANCELED,			///< 0x80040030:   Command canceled
+	MN_ERR_THREAD_CREATE,		///< 0x80040031:   Thread create error
+	MN_ERR_UNSOLICITED,			///< 0x80040032:   Unsolicted response detected
+	MN_ERR_DEF_RESP_TO,			///< 0x80040033:   Deferred response time-out
+	MN_ERR_ADDR_RANGE,			///< 0x80040034:   Response from out of range address
+	MN_ERR_WRONG_SRC,			///< 0x80040035:   Response from wrong source
+	MN_ERR_FLUSH_MANY,			///< 0x80040036:   Flush finding many characters
+	MN_ERR_PRIO_FAILED,			///< 0x80040037:   Failed to set thread priority
+	MN_ERR_NET_DIAG_FAILED,     ///< 0x80040038:   Network diagnostic problems detected
+	MN_ERR_RD_COMM_IRQ,			///< 0x80040039:   Could not start the read COMM IRQs
+	MN_ERR_NULL_RETURN,		   	///< 0x8004003a:   Read returned NULL buffer
+	MN_ERR_RESET_FAILED,		///< 0x8004003b:   Reset command failed
+	MN_ERR_LOG_CHANGED,			///< 0x8004003c:   Error log changed during read
+	MN_ERR_DATAACQ_OVERRUN,		///< 0x8004003d:   Data acquisition over-run
+	MN_ERR_HOST_APP_OVERRUN,	///< 0x8004003e:   Host's application port over-run
+	MN_ERR_HOST_DIAG_OVERRUN,	///< 0x8004003f:   Host's diagnostic port over-run
+	MN_ERR_FILE_WRITE,			///< 0x80040040:   Configuration file failed to write
+	MN_ERR_FILE_OPEN,			///< 0x80040041:   Configuration file failed to open   
+	MN_ERR_FILE_WRONG,			///< 0x80040042:   Configuration file is for wrong node   
+	MN_ERR_FILE_BAD,			///< 0x80040043:   Configuration file corrupt   
+	MN_ERR_FILE_ENABLED,		///< 0x80040044:   Configuration file load requires node to be disabled.   
+	MN_ERR_CMD_IN_ATTN,			///< 0x80040045:   Command attempted from within an Attention Callback.
+	MN_ERR_APP_NET_ONLY,		///< 0x80040046:   Feature only available on App Net
+	MN_ERR_24V_OFF,				///< 0x80000047:   Canceled due to lack of 24V supply
+								// 0x48   
+								// 0x49   
+
+
+	/* ----------------------- MN_ERR_CMD ----------------------------*/
+	MN_ERR_CMD_INTERNAL=MN_ERR_CMD_ERR_BASE,			
+								// 0x100: Generic internal error
+	MN_ERR_CMD_CMD_UNK,			///< 0x80040101: Command unknown on this node
+	MN_ERR_CMD_ARGS,			///< 0x80040102: Illegal or missing command args
+	MN_ERR_CMD_WR_FAIL,			///< 0x80040103: Attempt to write read-only info
+	MN_ERR_CMD_EEHW,			///< 0x80040104: Non-Volatile memory failure
+	MN_ERR_CMD_ACCESS_LVL,		///< 0x80040105: Access level violation
+	MN_ERR_CMD_MV_FULL,			///< 0x80040106: Move Buffers full
+	MN_ERR_CMD_MV_SPEC,			///< 0x80040107: Move specification error
+	MN_ERR_CMD_MV_ESTOPPED,		///< 0x80040108: Motion attempt in E-Stopped state
+	MN_ERR_CMD_MV_RANGE,		///< 0x80040109: Motion attempt is out of range
+	MN_ERR_CMD_MV_SHUTDOWN,		///< 0x8004010a: Motion attempt / drive in shutdown
+	MN_ERR_CMD_IEX_ERROR,		///< 0x8004010b: IEX interaction while stopped
+	MN_ERR_CMD_MV_BLOCKED,		///< 0x8004010c: Motion blocked / non-disabling shutdown present
+								// 0x10d	Reserved for move errors
+								// 0x10e	Reserved for move errors
+								// 0x10f	Reserved for move errors
+	MN_ERR_NODE_IN_MOTION=MN_ERR_CMD_ERR_BASE+0x10,	///< 0x80040110:   Drive is in motion
+	
+	MN_ERR_CMD_ERR_END, // Used for class of error range
+	/* -------------------- END OF MN_ERR_CMD GROUP ------------------*/
+
+	/* ------------------------- MN_ERR_NET --------------------------------*/
+	MN_ERR_NET_FRAG=MN_ERR_NET_ERR_BASE,	
+								///< 0x80040120: Packet fragment detected
+	MN_ERR_NET_CHKSUM,			///< 0x80040121: Bad checksum detected
+	MN_ERR_NET_STRAY,			///< 0x80040122: Stray Data Found
+	MN_ERR_NET_PORT_OVERRUN,	///< 0x80040123: Serial Port overran receive
+
+	MN_ERR_NET_ERR_END,	// Used for class of error range
+	/* ---------------------- END OF MN_ERR_NET ----------------------------*/
+
+	/* -------------------- NODE BREAK ERROR GROUP ---------------------*/
+ 	/// Network Break detected on the other channel between node \e xx 
+	/// and the node \e yy.
+	MN_ERR_BRK_OTHER_00_01=MN_ERR_NETBREAK_ERR_BASE,
+                                // 0x80040300: Net Break OTHER: node 00-01	
+	MN_ERR_BRK_OTHER_01_02,     // 0x80040301: Net Break OTHER: node 01-02 
+	MN_ERR_BRK_OTHER_02_03,     // 0x80040302: Net Break OTHER: node 02-03 
+	MN_ERR_BRK_OTHER_03_04,     // 0x80040303: Net Break OTHER: node 03-04 
+	MN_ERR_BRK_OTHER_04_05,     // 0x80040304: Net Break OTHER: node 04-05 
+	MN_ERR_BRK_OTHER_05_06,     // 0x80040305: Net Break OTHER: node 05-06 
+	MN_ERR_BRK_OTHER_06_07,     // 0x80040306: Net Break OTHER: node 06-07 
+	MN_ERR_BRK_OTHER_07_08,     // 0x80040307: Net Break OTHER: node 07-08 
+	MN_ERR_BRK_OTHER_08_09,     // 0x80040308: Net Break OTHER: node 08-09 
+	MN_ERR_BRK_OTHER_09_10,     // 0x80040309: Net Break OTHER: node 09-10 
+	MN_ERR_BRK_OTHER_10_11,     // 0x8004030a: Net Break OTHER: node 10-11 
+	MN_ERR_BRK_OTHER_11_12,     // 0x8004030b: Net Break OTHER: node 11-12 
+	MN_ERR_BRK_OTHER_12_13,     // 0x8004030c: Net Break OTHER: node 12-13 
+	MN_ERR_BRK_OTHER_13_14,     // 0x8004030d: Net Break OTHER: node 13-14 
+	MN_ERR_BRK_OTHER_14_15,     // 0x8004030e: Net Break OTHER: node 14-15 
+	MN_ERR_BRK_OTHER_15_HOST, 	// 0x8004030f: Net Break OTHER: node 15-host
+								
+	/// Network Break detected on the application channel between node \e xx 
+	/// and the node \e yy.
+	MN_ERR_BRK_APP_00_01=MN_ERR_NETBREAK_ERR_BASE+0x10,		
+								// 0x80040310: Net Break APP: node 00-01
+	MN_ERR_BRK_APP_01_02,		// 0x80040311: Net Break APP: node 01-02 
+	MN_ERR_BRK_APP_02_03,		// 0x80040312: Net Break APP: node 02-03 
+	MN_ERR_BRK_APP_03_04,		// 0x80040313: Net Break APP: node 03-04 
+	MN_ERR_BRK_APP_04_05,		// 0x80040314: Net Break APP: node 04-05 
+	MN_ERR_BRK_APP_05_06,		// 0x80040315: Net Break APP: node 05-06 
+	MN_ERR_BRK_APP_06_07,		// 0x80040316: Net Break APP: node 06-07 
+	MN_ERR_BRK_APP_07_08,		// 0x80040317: Net Break APP: node 07-08 
+	MN_ERR_BRK_APP_08_09,		// 0x80040318: Net Break APP: node 08-09 
+	MN_ERR_BRK_APP_09_10,		// 0x80040319: Net Break APP: node 09-10 
+	MN_ERR_BRK_APP_10_11,		// 0x8004031a: Net Break APP: node 10-11 
+	MN_ERR_BRK_APP_11_12,		// 0x8004031b: Net Break APP: node 11-12 
+	MN_ERR_BRK_APP_12_13,		// 0x8004031c: Net Break APP: node 12-13 
+	MN_ERR_BRK_APP_13_14,		// 0x8004031d: Net Break APP: node 13-14 
+	MN_ERR_BRK_APP_14_15,		// 0x8004031e: Net Break APP: node 14-15 
+	MN_ERR_BRK_APP_15_TO_HOST,	// 0x8004031f: Net Break APP: node 15-host
+
+	/** 0x80040320: Network Break detected on the diagnostic channel between 
+	    node \e 0 and the node \e 1.
+	**/
+	MN_ERR_BRK_DIAG_00_01=MN_ERR_NETBREAK_ERR_BASE+0x20,		
+	/** 0x80040321: Network Break detected on the diagnostic channel between 
+	    node \e 1 and the node \e 2.
+	**/
+	MN_ERR_BRK_DIAG_01_02,		// 0x80040321: Net Break DIAG: node 01-02
+	/** 0x80040322: Network Break detected on the diagnostic channel between 
+	    node \e 2 and the node \e 3.
+	**/
+	MN_ERR_BRK_DIAG_02_03,		// 0x80040322: Net Break DIAG: node 02-03 
+	/** 0x80040323: Network Break detected on the diagnostic channel between 
+	    node \e 3 and the node \e 4.
+	**/
+	MN_ERR_BRK_DIAG_03_04,		// 0x80040323: Net Break DIAG: node 03-04 
+	/** 0x80040324: Network Break detected on the diagnostic channel between 
+	    node \e 4 and the node \e 5.
+	**/
+	MN_ERR_BRK_DIAG_04_05,		// 0x80040324: Net Break DIAG: node 04-05 
+	/** 0x80040325: Network Break detected on the diagnostic channel between 
+	    node \e 5 and the node \e 6.
+	**/
+	MN_ERR_BRK_DIAG_05_06,		// 0x80040325: Net Break DIAG: node 05-06 
+	/** 0x80040326: Network Break detected on the diagnostic channel between 
+	    node \e 6 and the node \e 7.
+	**/
+	MN_ERR_BRK_DIAG_06_07,		// 0x80040326: Net Break DIAG: node 06-07 
+	/** 0x80040327: Network Break detected on the diagnostic channel between 
+	    node \e 7 and the node \e 8.
+	**/
+	MN_ERR_BRK_DIAG_07_08,		// 0x80040327: Net Break DIAG: node 07-08 
+	/** 0x80040328: Network Break detected on the diagnostic channel between 
+	    node \e 8 and the node \e 9.
+	**/
+	MN_ERR_BRK_DIAG_08_09,		// 0x80040328: Net Break DIAG: node 08-09 
+	/** 0x80040329: Network Break detected on the diagnostic channel between 
+	    node \e 9 and the node \e 10.
+	**/
+	MN_ERR_BRK_DIAG_09_10,		// 0x80040329: Net Break DIAG: node 09-10 
+	/** 0x8004032a: Network Break detected on the diagnostic channel between 
+	    node \e 10 and the node \e 11.
+	**/
+	MN_ERR_BRK_DIAG_10_11,		// 0x8004032a: Net Break DIAG: node 10-11 
+	/** 0x8004032b: Network Break detected on the diagnostic channel between 
+	    node \e 11 and the node \e 12.
+	**/
+	MN_ERR_BRK_DIAG_11_12,		// 0x8004032b: Net Break DIAG: node 11-12 
+	/** 0x8004032c: Network Break detected on the diagnostic channel between 
+	    node \e 12 and the node \e 13.
+	**/
+	MN_ERR_BRK_DIAG_12_13,		// 0x8004032c: Net Break DIAG: node 12-13 
+	/** 0x8004032d: Network Break detected on the diagnostic channel between 
+	    node \e 13 and the node \e 14.
+	**/
+	MN_ERR_BRK_DIAG_13_14,		// 0x8004032d: Net Break DIAG: node 13-14 
+	/** 0x8004032e: Network Break detected on the diagnostic channel between 
+	    node \e 14 and the node \e 15.
+	**/
+	MN_ERR_BRK_DIAG_14_15,		// 0x8004032e: Net Break DIAG: node 14-15 
+	/** 0x8004032f: Network Break detected on the diagnostic channel between 
+	    node \e 15 and the host.
+	**/
+	MN_ERR_BRK_DIAG_15_TO_HOST,	// 0x8004032f: Net Break DIAG: node 15-host 
+
+	/// Network Break detected on the application channel between node \e xx 
+	/// and the host.
+	MN_ERR_BRK_APP_00_HOST=MN_ERR_NETBREAK_ERR_BASE+0x30,		
+	MN_ERR_BRK_APP_01_HOST,		// 0x330-0x33f Between node xx and host
+	MN_ERR_BRK_APP_02_HOST,
+	MN_ERR_BRK_APP_03_HOST,
+	MN_ERR_BRK_APP_04_HOST,
+	MN_ERR_BRK_APP_05_HOST,
+	MN_ERR_BRK_APP_06_HOST,
+	MN_ERR_BRK_APP_07_HOST,
+	MN_ERR_BRK_APP_08_HOST,
+	MN_ERR_BRK_APP_09_HOST,
+	MN_ERR_BRK_APP_10_HOST,
+	MN_ERR_BRK_APP_11_HOST,
+	MN_ERR_BRK_APP_12_HOST,
+	MN_ERR_BRK_APP_13_HOST,
+	MN_ERR_BRK_APP_14_HOST,
+	MN_ERR_BRK_APP_15_HOST,
+
+	/**
+	0x80040340 Network Break detected on the diagnostic channel between node
+	\e 0 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_00_HOST=MN_ERR_NETBREAK_ERR_BASE+0x40,
+	/**
+	0x80040341 Network Break detected on the diagnostic channel between node
+	\e 1 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_01_HOST, 
+	/**
+	0x80040342 Network Break detected on the diagnostic channel between node
+	\e 2 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_02_HOST,
+	/**
+	0x80040343 Network Break detected on the diagnostic channel between node
+	\e 3 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_03_HOST,
+	/**
+	0x80040344 Network Break detected on the diagnostic channel between node
+	\e 4 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_04_HOST,
+	/**
+	0x80040345 Network Break detected on the diagnostic channel between node
+	\e 5 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_05_HOST,
+	/**
+	0x80040346 Network Break detected on the diagnostic channel between node
+	\e 6 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_06_HOST,
+	/**
+	0x80040347 Network Break detected on the diagnostic channel between node
+	\e 7 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_07_HOST,
+	/**
+	0x80040348 Network Break detected on the diagnostic channel between node
+	\e 8 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_08_HOST,
+	/**
+	0x80040349 Network Break detected on the diagnostic channel between node
+	\e 9 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_09_HOST,
+	/**
+	0x8004034a Network Break detected on the diagnostic channel between node
+	\e 10 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_10_HOST,
+	/**
+	0x80040341 Network Break detected on the diagnostic channel between node
+	\e 11 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_11_HOST,
+	/**
+	0x8004034c Network Break detected on the diagnostic channel between node
+	\e 12 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_12_HOST,
+	/**
+	0x8004034d Network Break detected on the diagnostic channel between node
+	\e 13 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_13_HOST,
+	/**
+	0x8004034e Network Break detected on the diagnostic channel between node
+	\e 14 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_14_HOST,
+	/**
+	0x8004034f Network Break detected on the diagnostic channel between node
+	\e 15 and the host.
+	**/		
+	MN_ERR_BRK_DIAG_15_HOST,
+
+	/// Network Break detected between node \e xx and the host.
+	MN_ERR_BRK_00_HOST=MN_ERR_NETBREAK_ERR_BASE+0x50,		
+	MN_ERR_BRK_01_HOST,			// 0x340-0x34f Between node xx and host
+	MN_ERR_BRK_02_HOST,
+	MN_ERR_BRK_03_HOST,
+	MN_ERR_BRK_04_HOST,
+	MN_ERR_BRK_05_HOST,
+	MN_ERR_BRK_06_HOST,
+	MN_ERR_BRK_07_HOST,
+	MN_ERR_BRK_08_HOST,
+	MN_ERR_BRK_09_HOST,
+	MN_ERR_BRK_10_HOST,
+	MN_ERR_BRK_11_HOST,
+	MN_ERR_BRK_12_HOST,
+	MN_ERR_BRK_13_HOST,
+	MN_ERR_BRK_14_HOST,
+	MN_ERR_BRK_15_HOST,
+
+	// Detected offline nodes are reported with this group. These are
+	// usually caused by a node restarting via power or firmware error.
+	MN_ERR_OFFLINE_00=MN_ERR_NETBREAK_ERR_BASE+0xa0,
+							    // 0x800403a0: Node 0  detected offline
+	MN_ERR_OFFLINE_01,	    	// 0x800403a1: Node 1  detected offline
+	MN_ERR_OFFLINE_02,	    	// 0x800403a2: Node 2  detected offline
+	MN_ERR_OFFLINE_03,	    	// 0x800403a3: Node 3  detected offline
+	MN_ERR_OFFLINE_04,	    	// 0x800403a4: Node 4  detected offline
+	MN_ERR_OFFLINE_05,	    	// 0x800403a5: Node 5  detected offline
+	MN_ERR_OFFLINE_06,	    	// 0x800403a6: Node 6  detected offline
+	MN_ERR_OFFLINE_07,	    	// 0x800403a7: Node 7  detected offline
+	MN_ERR_OFFLINE_08,	    	// 0x800403a8: Node 8  detected offline
+	MN_ERR_OFFLINE_09,	    	// 0x800403a9: Node 9  detected offline
+	MN_ERR_OFFLINE_10,	    	// 0x800403aa: Node 10 detected offline
+	MN_ERR_OFFLINE_11,	    	// 0x800403ab: Node 11 detected offline
+	MN_ERR_OFFLINE_12,	    	// 0x800403ac: Node 12 detected offline
+	MN_ERR_OFFLINE_13,	    	// 0x800403ad: Node 13 detected offline
+	MN_ERR_OFFLINE_14,	    	// 0x800403ae: Node 14 detected offline
+	MN_ERR_OFFLINE_15,	    	// 0x800403af: Node 15 detected offline
+	
+	// Special Diagnostic Errors
+	MN_ERR_BRK_DIAG_LOC_UNKNOWN=MN_ERR_NETBREAK_ERR_BASE+0xFC,	
+								///< 0x800403fc: Net Break Diag: unknown location
+	MN_ERR_BRK_APP_LOC_UNKNOWN,	///< 0x800403fd: Net Break App: unknown location
+    MN_ERR_BRK_LOC_UNKNOWN,    	///< 0x800403fe: Net Break unknown
+	MN_ERR_NO_NET_CONNECTIVITY,	///< 0x800403ff: Cannot detect net connectivity
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Initialization bit oriented error codes
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+	/**
+		\brief Initialization Error(s)
+
+		The following codes describe the failing port initialization issue.
+		The 8 LSBs represent the problem ports with LSB = port 0.
+
+		0x80040600-0x80040607
+	**/
+	MN_ERR_INIT_FAILED_BASE=0x80040600,
+	/**
+	0x80040601: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 0.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_0,			// 0x80040601 Port 0 problem		
+	/**
+	0x80040602: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 1.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_1,			// 0x80040602: Port 1 problem
+	/**
+	0x80040603: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 0 & 1.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_1_0,		// 0x80040603: Port 0&1 problem
+	/**
+	0x80040604: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 2.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_2,			// 0x80040604: Port 2 problem
+	/**
+	0x80040605: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 2 & 0.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_2_0,		// 0x80040605: Port 2&0 problem
+	/**
+	0x80040606: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 2 & 1.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_2_1,		// 0x80040606: Port 2&1 problem
+	/**
+	0x80040607: Port opened OK but no nodes were found attached to the link.	
+ 	Problems detected at port index: 2 & 1 & 0.
+	**/
+	MN_ERR_INIT_FAILED_PORTS_2_1_0,		// 0x80040607: Port 2&1&0 problem
+
+	/**
+		\brief Port Open Error(s)
+
+		The following codes describe the failing port failed to open issue.
+		The 8 LSBs represent the problem ports with LSB = port 0.
+
+		0x80040700-0x80040707
+	**/
+	MN_ERR_PORT_FAILED_BASE = 0x80040700,
+	/**
+	0x80040701: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 0.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_0,			// 0x80040701: Port 0 problem		
+	/**
+	0x80040702: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 1.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_1,			// 0x80040702: Port 1 problem
+	/**
+	0x80040703: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 0 & 1.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_1_0,		// 0x80040703: Port 0&1 problem
+	/**
+	0x80040704: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 2.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_2,			// 0x80040704: Port 2 problem
+	/**
+	0x80040705: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 2 & 0.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_2_0,		// 0x80040705: Port 2&0 problem
+	/**
+	0x80040706: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 2 & 1.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_2_1,		// 0x80040706: Port 2&1 problem
+	/**
+	0x80040707: Port failed to open. Make sure you specify a working port or check
+	that the USB cable is properly inserted. 
+	Problems detected at port index: 2 & 1 & 0.
+	**/
+	MN_ERR_PORT_FAILED_PORTS_2_1_0,		// 0x80040707: Port 2&1&0 problem
+	/**
+		\brief Initialization Error	Due to Unsupported Port Rate
+
+		The following codes describe the failing port initialization issue.
+		The 8 LSBs represent the problem ports with LSB = port 0
+
+		0x80040800-0x80040807
+	**/
+	MN_ERR_BAUD_FAILED_BASE = 0x80040800,
+	/**
+	0x80040801: Port opened OK but doesn't support the requested baud rate. 
+	Problems detected at port index: 0.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_0,			// 0x80040801: Port 0 problem		
+	/**
+	0x80040802: Port opened OK but doesn't support the requested baud rate.
+	Problems detected at port index: 1.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_1,			// 0x80040802: Port 1 problem
+	/**
+	0x80040803: Port opened OK but doesn't support the requested baud rate.
+	Problems detected at port index: 0 & 1.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_1_0,		// 0x80040803: Port 0&1 problem
+	/**
+	0x80040804: Port opened OK but doesn't support the requested baud rate.
+	Problems detected at port index: 2.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_2,			// 0x80040804: Port 2 problem
+	/**
+	0x80040805: Port opened OK but doesn't support the requested baud rate.
+	Problems detected at port index: 2 & 0.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_2_0,		// 0x80040805: Port 2&0 problem
+	/**
+	0x80040806: Port opened OK but doesn't support the requested baud rate.
+	Problems detected at port index: 2 & 1.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_2_1,		// 0x80040806: Port 2&1 problem
+	/**
+	0x80040807: Port opened OK but doesn't support the requested baud rate.
+	Problems detected at port index: 2 & 1 & 0.
+	**/
+	MN_ERR_BAUD_FAILED_PORTS_2_1_0		// 0x80040807: Port 2&1&0 problem
+
+	/* --------------------- END OF NODE ERROR GROUP ----------------------*/
+
+} cnErrCode;
+/***************************************************************************/
+
+#endif
+//=========================================================================== 
+//	END OF FILE mnErrors.h
+//===========================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCoreRegs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCoreRegs.h
new file mode 100644
index 000000000..1ec2a599d
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCoreRegs.h
@@ -0,0 +1,1352 @@
+//***************************************************************************
+// DESCRIPTION:
+/**
+	\file
+	\brief Universal Register Definitions.
+
+	These registers are typically implemented as unions. The members of the
+	union include:
+	-a bit-wide interface named \a bits
+	-one or more node specific structs to access node specific fields. For
+	ClearPath-SC this member is named "cpm".
+	-The Meridian-ISC member is named either "isc" or "fld" depending on its
+	original legacy name.
+**/
+//
+// NAME
+//      pubCoreRegs.h
+//
+// CREATION DATE:
+//      06/19/2008 13:46:39
+//
+// COPYRIGHT NOTICE:
+//      (C)Copyright 2008-2018 Teknic, Inc.  All rights reserved.
+//
+//      This copyright notice must be reproduced in any copy, modification,
+//      or portion thereof merged into another program. A copy of the
+//      copyright notice must be included in the object library of a user
+//      program.
+//                                                                           *
+//****************************************************************************
+#ifndef __PUBCOREREGS__H__
+#define __PUBCOREREGS__H__
+
+
+//****************************************************************************
+// NAME                                                                      *
+//  pubCoreRegs.h headers
+//
+    #include "tekTypes.h"
+	#include "pubRegFldCommon.h"
+	#include "pubIscRegs.h"
+#if defined(IMPL_NODE_CP)
+	#include "pubClearPathRegs.h"
+#endif
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC) || defined(_CLEARPATH)
+	#include "pubCpmRegs.h"
+#endif
+//                                                                           *
+//****************************************************************************
+
+
+//****************************************************************************
+// NAME                                                                      *
+//  pubCoreRegs.h constants
+//
+													/** \cond INTERNAL_DOC **/
+#define ATTN_MASK_OCTETS 4
+													/** \endcond **/
+//                                                                           *
+//****************************************************************************
+
+
+//****************************************************************************
+// Insure structs are byte packed on target
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+//****************************************************************************
+
+
+
+//****************************************************************************
+// NAME                                                                      *
+//  optionReg union
+//
+// DESCRIPTION
+																/** \cond ExpertDoc **/
+/**
+    \brief Universal Factory setup and option control register.
+
+    This register describes the various model-specific information.
+**/
+//
+typedef union PACK_BYTES _optionReg {
+	/**
+	 *  Hardware Platforms
+	 */
+	enum _hwPlatforms {
+		HW_CLEARPATH,
+		HW_AC_GREEN
+	};
+	/**
+		Bit-wide access for options
+	**/
+    Uint32 bits; 
+    // - - - - - - - - - - - - - - - - - - - -
+    // COMMON PRODUCT OPTION DEFINITIONS
+    // - - - - - - - - - - - - - - - - - - - -
+	/**
+		\brief Universal Option Field Definitions.
+	**/
+    struct _optionsCommonFlds {
+        /*                   -----------  ----------------------------------- *
+         *                         bit #  description                         *
+         *                   -----------  ----------------------------------- */
+		/// Factory setup modes
+        int Setups          :4; // 0-3:   Factory setup modes
+		/// Product options installed
+        unsigned Product    :2; // 4-5:   Product options
+		/// Advanced feature supported
+		unsigned Advanced	:1; // 6 :	  Advanced features available
+														/// INTERNAL_DOC
+		unsigned VectorLock	:1; // 7 :    Lock Vector Mode
+														///
+		/// Option board(s) installed
+        unsigned OptionBrd  :2; // 8-9:   Installed option board configuration
+        unsigned IgnoreIndx :1; // 10:	  Prevent Ref Offset on index
+														/// INTERNAL_DOC
+        int					:1; // 11 :
+														///
+		/// Hardware platform code
+        unsigned HwPlatform :4; // 12-15: Hardware platform
+														/// INTERNAL_DOC
+        int					:9; // 16-24
+														///
+		/// Special debugging flags
+        unsigned Debug      :3; // 25-27: Debug flags
+    };
+    struct _drvCommonFlds {
+        /*                   -----------  ----------------------------------- *
+         *                         bit #  description                         *
+         *                   -----------  ----------------------------------- */
+        unsigned VoltMode		: 1; // 0:  Volt mode setup
+        unsigned RuntimeCal		: 1; // 1:  1=Enable run time calibration
+        unsigned ClockCal		: 1; // 2:  1=clock calibration
+        unsigned DirCwPositive	: 1; // 3:  1=CW direction is positive motion
+
+        unsigned Product		: 3; // 4:  3-bit product number
+									 // 5:  ""
+									 // 6:	""
+        /**
+    		\brief Vector Lock Diagnostic Enable
+
+            If the motor is vector oriented, such as a brushless motor
+            this will force the vector to freeze.
+        **/
+        unsigned VectorLock : 1; // 7   Lock Vector Mode
+
+        /**
+    		\brief Missing index tolerance
+
+    		When index checking is set, this field is the number of
+    		index pulses that can be missing before an error is flagged.
+    		0 = any missed index is an error
+        **/
+        unsigned IndexTolerance	: 2;    // 8-9
+        /**
+    		\brief Inhibit motor index processing for vector refinement.
+
+            If set, the encoder's index is ignored for vector processing. This
+    		is useful for development purposes as well as factory motor setup
+    		when combined with #CpHwConfigReg::SensorlessMode mode.
+        **/
+    	unsigned IgnoreIndx	 : 1;//  10 Prevent Ref Offset on index
+    	unsigned NoVectUpdate: 1;//  11 do not apply the angle from the enhanced sensorless algorithm
+		/// Hardware platform code
+    	unsigned HwPlatform :4; // 12-15: Hardware platform (enum _hwPlatforms)
+   };
+	/**
+		Access to common fields among nodes.
+	**/
+	struct _optionsCommonFlds Common;
+	/**
+		Access to common fields among drives.
+	**/
+	struct _drvCommonFlds DrvCommon;
+    // - - - - - - - - - - - - - - - - - - - -
+    // DRIVE PRODUCT OPTION DEFINITIONS
+    // - - - - - - - - - - - - - - - - - - - -
+														/// INTERNAL_DOC
+    /// Access to Meridian ISC option fields
+	iscOptionsFlds DrvFld;
+#if defined(IMPL_NODE_CP)
+    // - - - - - - - - - - - - - - - - - - - -
+    // CLEARPATH PRODUCT OPTION DEFINITIONS
+    // - - - - - - - - - - - - - - - - - - - -
+	/// Access to common fields among ClearPath motors
+    clearPathOptionsFlds ClrPathFld;            
+#endif
+														///
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC)
+	/// ClearPath-SC option register view
+	cpmOptionsFlds cpm;
+#endif
+	#ifdef __cplusplus
+														/// INTERNAL_DOC
+	/// Clear bits on construction
+    _optionReg() {                          
+        bits = 0;
+    }
+		#ifdef __TI_COMPILER_VERSION__
+		// Returns TRUE if the option register has us in debug mode
+		tBOOL InDebugMode() {
+			return((Common.Debug > 0) && (Common.Debug < 7));
+		}
+		#endif
+    #endif
+														///
+} optionReg;
+															/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																		  *
+//  alertReg union
+//
+// DESCRIPTION
+// Alert Register Size in octets: 96 bits = 3 32-bit entities = 12 octets
+#define ALERTREG_SIZEOCTETS 12
+/**
+    \brief Universal Alert and Warning Register Type
+
+    The alert register defines the shutdown state of the node. When a node enters a shutdown
+    or potentially non-operable condition, the node will set bits in this
+    register to tell the application what went wrong. Alerts range from serious to minor. 
+
+	- Hardware/Software failures during power on self testing and
+	internal consistency checks that occur during operation. These include items such as as:
+		- Sensor failures
+		- Component failures
+		- Sensors drifting out of their nominal ranges
+		- Non-volatile configuration errors
+	- Self preservation shutdowns where the node shuts down to protect itself from being damaged.
+		- Over motor bus voltage
+		- Shorted circuits
+		- Excessive power delivery to motor
+		- Jams
+	- Application errors such as:
+		- Parameters out-of-range for requested operations such as commanding a node past it's soft limits
+
+    Most shutdowns can be cleared via the sFnd::IStatus::AlertsClear function to allow
+    continued node operations, however fatal errors cannot be cleared by this
+    mechanism and require a power-cycle or node restart to clear them.
+
+	\note See the specific bit for potential recovery actions to allow node operations to continue.
+	If the Status Register's [HwFailure](@ref _cpmStatusRegFlds::HwFailure) bit is asserted, this is a
+	hardware failure and recovery is probably not possible.
+
+	
+	\see _cpmAlertFlds For the complete list of ClearPath-SC alert Fields.
+	\see sFnd::IStatus::Alerts for access to this register.
+ **/
+typedef union MN_EXPORT PACK_BYTES _alertReg {
+    /// "Parallel" view of register as three unsigned 32-bit integers.
+    Uint32 bits[3];
+													/** \cond ISC_DOC **/
+    /** 
+		\brief Common fields for all Meridian products. 
+		
+		Usually you would use the more specific items such as the drvFld
+		to look for specific shutdowns. This member is included within the 
+		device specific members.
+    **/
+    commonAlertFlds Common;
+													/** \endcond **/
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC)
+	/**
+		\brief Access to ClearPath-SC specific alert fields.
+
+	**/
+	cpmAlertFlds cpm;
+#endif
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+													/** \cond ISC_DOC **/
+    /**
+		\brief Field access to the Drive Specific items.
+	**/
+	iscAlertFlds DrvFld;
+													/** \endcond **/
+    // If we have C++, include these useful member functions.
+													/** \cond INTERNAL_DOC **/
+    #ifdef __cplusplus
+		/// Clear values back to zeroes
+		void clear() {
+			bits[0] = 0;
+			bits[1] = 0;
+			bits[2] = 0;
+		}
+													/** \endcond  **/
+		/// Test if all bits are non-zero
+		/**
+		Returns true if all fields in the register are zero.
+
+		\CODE_SAMPLE_HDR
+
+		// get an alertReg reference, and check directly for alerts
+		if (myNode.Status.Alerts.Value().isClear())
+		{
+		printf("Node has no alerts!");
+		}
+
+		\endcode
+		**/
+		bool isClear() {
+			return (bits[0] | bits[1] | bits[2]) == 0;
+		}
+		/// Test if any bits are non-zero
+		/**
+		Returns true if any fields in the register is asserted.
+
+		\CODE_SAMPLE_HDR
+
+		// get an alertReg reference, and check directly for alerts
+		if (myNode.Status.Alerts.Value().isInAlert())
+		{
+		printf("Node has alerts!");
+		}
+
+		\endcode
+		**/
+		bool isInAlert() {
+			return (bits[0] | bits[1] | bits[2]) != 0;
+		}
+#ifndef __TI_COMPILER_VERSION__
+		/**
+		\brief Update a string with the set fields in the Alert Register.
+
+		\param[in,out] buffer  Point to string buffer to update.
+		\param[in] size  The size of the buffer in characters including the null
+		character.
+		\return the parameter \a buffer.
+
+		\CODE_SAMPLE_HDR
+		char myBuffer[500];
+		cout << myNode.Status.Alert.Value.StateStr(myBuffer, sizeof(myBuffer));
+		\endcode
+		**/
+		char * StateStr(char *buffer, size_t size) {
+			return (cpm.StateStr(buffer, size));
+		}
+#endif
+													/** \cond INTERNAL_DOC **/
+		/// Number of Uint32 bits in structure
+		enum { N_BITS = 3};
+        #ifdef __TI_COMPILER_VERSION__
+            bool InShutdown();
+            bool InLockdown();
+            bool InPwrEvent();
+            bool InPwrEventShutdown();
+            bool InBlockMotionShutdown();
+            bool InBlockMotionSelfClearShutdown();
+            bool InNodeNeedsRepairShutdown();
+            bool InSeriousShutdown();
+            bool InKillOutputsShutdown();
+            bool InAlert();
+        #endif
+        // Constructor, create with bits cleared
+        _alertReg() {                   // Clear bits on construction
+            STATIC_ASSERT(ALERTREG_SIZEOCTETS==12);
+			clear();
+        }
+    #endif
+													/** \endcond **/
+} alertReg;
+
+													/** \cond INTERNAL_DOC **/
+// These bit numbers must match the locations in the alertReg union
+// They are used by coding that requires either a mask or a bit number.
+/*
+    Bit Number index for the Alert Register
+
+    These number can be used to construct masks.
+*/
+typedef enum _drvAlertBits {
+	DRV_ALERT_FW_BAD_ACQ_STATE_BIT              = 32,
+	DRV_ALERT_FW_MOVEGEN_MISC_BIT               = 33,
+	DRV_ALERT_FW_MOVEGEN_OFF_TARGET_BIT         = 34,
+	DRV_ALERT_FW_MOVEGEN_RANGE_BIT              = 35,
+	DRV_ALERT_FW_BAD_RAS_REQUEST_BIT            = 36,
+	DRV_ALERT_FW_MOVE_BUF_UNDERRUN_BIT          = 37,
+	DRV_ALERT_FW_BAD_RAS_VELOCITY_BIT           = 38,
+	DRV_ALERT_FW_MOVE_SPEC_ALTERED_BIT          = 39,
+	DRV_ALERT_HW_PHASE_SENSOR_BIT               = 40,   // HW Shdn
+	DRV_ALERT_FW_MOVEGEN_LIMSW_BIT              = 41,
+	DRV_ALERT_FW_MOVEGEN_SOFTLIM_BIT            = 42,
+	DRV_ALERT_FW_MOVE_BUF_OVERRUN_LOCKDN_BIT    = 43,
+	DRV_ALERT_IO_5V_SUPPLY_OVERLOAD_BIT         = 44,   // mtn Shdn
+	DRV_ALERT_IO_BRAKE_OVERLOAD_BIT             = 45,
+	DRV_ALERT_IO_GPO0_OVERLOAD_BIT              = 46,
+	DRV_ALERT_IO_GPO1_OVERLOAD_BIT              = 47,
+	DRV_ALERT_IO_GPO_DETECTOR_BIT               = 48,
+	DRV_ALERT_IO_GPO_OVERLOAD_BIT               = 49,
+	DRV_ALERT_IO_INVALID_BIT       		        = 50,
+	DRV_ALERT_IO_INVALID_LOCKDN_BIT     		= 51,
+	DRV_ALERT_AC_POWER_LOST_BIT					= 52,
+	DRV_ALERT_IEX_LINK_GLITCH_BIT               = 53,
+	DRV_ALERT_IEX_LINK_MULTI_GLITCH_BIT         = 54,
+	DRV_ALERT_MTR_UNDERTEMP_BIT			        = 55,
+	DRV_ALERT_MTR_COMM_BAD_SEQ_BIT              = 56,   // mtn Shdn
+	DRV_ALERT_MTR_COMM_BAD_STATE_BIT            = 57,   // mtn Shdn
+	DRV_ALERT_MTR_VECTOR_ERR_BIT                = 58,   // mtn Shdn
+	DRV_ALERT_MTR_VECTOR_CRIT_ERR_BIT           = 59,   // mtn Shdn
+	DRV_ALERT_MTR_ENC_GLITCH_BIT                = 60,   // mtn Shdn
+	DRV_ALERT_MTR_ENC_OVERSPEED_BIT             = 61,   // mtn Shdn
+	DRV_ALERT_LD_ENC_GLITCH_BIT                 = 62,   // mtn Shdn
+	DRV_ALERT_LD_ENC_OVERSPEED_BIT              = 63,   // mtn Shdn
+	DRV_ALERT_MTR_PHASE_OVERLOAD_BIT            = 64,   // mtn Shdn
+	DRV_ALERT_MTR_THERMAL_OVERLOAD_BIT          = 65,   // mtn Shdn
+	DRV_ALERT_MTR_BAD_SETUP_PARAMS_BIT          = 66,   // sw Shdn
+	DRV_ALERT_SVO_HARDSTOP_RELEASE_BIT          = 67,   // mtn Shdn
+	DRV_ALERT_SVO_TRACKING_BIT                  = 68,   // mtn Shdn
+	DRV_ALERT_SVO_TRACKING_CRIT_BIT             = 69,   // mtn Shdn
+	DRV_ALERT_SVO_RMS_OVERLOAD_BIT              = 70,   // mtn Shdn
+	DRV_ALERT_SVO_RMS_CRIT_OVERLOAD_BIT         = 71,   // mtn Shdn
+	DRV_ALERT_MTR_COUPLING_ERROR_BIT            = 72,   // mtn Shdn
+	DRV_ALERT_SVO_STEP_NOISE_BIT                = 73,   // mtn Shdn
+	DRV_ALERT_SVO_VOLT_SAT_BIT                  = 74,   // mtn Shdn
+	DRV_ALERT_SVO_TRQ_SAT_BIT                   = 75,   // mtn Shdn
+	DRV_ALERT_NOCOMM_DIST_ERROR_BIT             = 76,   // mtn Shdn
+	DRV_ALERT_NOCOMM_DIRECTION_ERROR_BIT        = 77,   // mtn Shdn
+	DRV_ALERT_NOCOMM_FAIL_BIT					= 78,	
+	DRV_ALERT_MTR_ENC_INDEX_MISSING_WARN_BIT	= 79,
+	DRV_ALERT_TEMP_AMBIENT_BIT                  = 80,   // mtn Shdn (drive hot)
+	DRV_ALERT_TEMP_HEATSINK_BIT                 = 81,   // mtn Shdn (stator hot)
+	DRV_ALERT_BUS_OVERCURRENT_BIT               = 82,   // mtn Shdn
+	DRV_ALERT_BUS_OVERVOLTAGE_BIT               = 83,   // mtn Shdn
+	DRV_ALERT_BUS_VOLTAGE_LOW_BIT               = 84,   // mtn Shdn
+	DRV_ALERT_BUS_RMS_OVERLOAD_BIT              = 85,   // mtn Shdn
+	DRV_ALERT_FAN_SPEED_LOW_BIT                 = 86,   // mtn Shdn
+	DRV_ALERT_MTR_ENC_INDEX_MISSING_BIT         = 87,
+	DRV_ALERT_NOCOMM_HW_FAULT_BIT				= 88,
+	DRV_ALERT_NOCOMM_BUS_LOW_BIT				= 89,
+	DRV_ALERT_NOCOMM_SW_FAULT_BIT				= 90,
+	DRV_ALERT_FW_MOVEGEN_LIMSW_LOCKDN_BIT       = 91,
+	DRV_ALERT_FW_MOVEGEN_SOFTLIM_LOCKDN_BIT     = 92,
+	DRV_ALERT_MTR_ENC_INDEX_MISPLACED_BIT		= 93,
+} drvAlertBits;
+
+// These bit numbers must match the locations in the alertReg union
+// They are used by coding that requires either a mask or a bit number.
+/*
+    Bit Number index for the Alert Register
+
+    These number can be used to construct masks.
+*/
+typedef enum _cpmAlertBits {
+    CPM_ALERT_FW_BAD_RAS_REQUEST_BIT            = DRV_ALERT_FW_BAD_RAS_REQUEST_BIT,     // 36
+    CPM_ALERT_FW_MOVE_BUF_UNDERRUN_BIT          = DRV_ALERT_FW_MOVE_BUF_UNDERRUN_BIT,   // 37
+    CPM_ALERT_FW_BAD_RAS_VELOCITY_BIT           = DRV_ALERT_FW_BAD_RAS_VELOCITY_BIT,    // 38
+    CPM_ALERT_FW_MOVE_SPEC_ALTERED_BIT          = DRV_ALERT_FW_MOVE_SPEC_ALTERED_BIT,   // 39
+    CPM_ALERT_HW_PHASE_SENSOR_BIT               = DRV_ALERT_HW_PHASE_SENSOR_BIT,        // 40 HW Shdn
+    CPM_ALERT_FW_MOVEGEN_LIMSW_BIT              = DRV_ALERT_FW_MOVEGEN_LIMSW_BIT,       // 41
+    CPM_ALERT_FW_MOVEGEN_SOFTLIM_BIT            = DRV_ALERT_FW_MOVEGEN_SOFTLIM_BIT,     // 42
+    CPM_ALERT_FW_MOVE_BUF_OVERRUN_LOCKDN_BIT    = DRV_ALERT_FW_MOVE_BUF_OVERRUN_LOCKDN_BIT,// 43
+    CPM_ALERT_IO_INVALID_BIT                    = DRV_ALERT_IO_INVALID_BIT,             // 50
+    CPM_ALERT_IO_INVALID_LOCKDN_BIT             = DRV_ALERT_IO_INVALID_LOCKDN_BIT,      // 51
+    CPM_ALERT_AC_POWER_LOST_BIT                 = DRV_ALERT_AC_POWER_LOST_BIT,          // 52
+    CPM_ALERT_AC_PHASE_WIRING_ERROR_BIT         = 53,                                   // 53
+    CPM_ALERT_MTR_UNDERTEMP_BIT                 = DRV_ALERT_MTR_UNDERTEMP_BIT,          // 55
+    CPM_ALERT_MTR_VECTOR_ERR_BIT                = DRV_ALERT_MTR_VECTOR_ERR_BIT,         // 58 mtn Shdn
+    CPM_ALERT_MTR_ENC_GLITCH_BIT                = DRV_ALERT_MTR_ENC_GLITCH_BIT,         // 60 mtn Shdn
+    CPM_ALERT_MTR_ENC_OVERSPEED_BIT             = DRV_ALERT_MTR_ENC_OVERSPEED_BIT,      // 61 mtn Shdn
+    CPM_ALERT_MTR_PHASE_OVERLOAD_BIT            = DRV_ALERT_MTR_PHASE_OVERLOAD_BIT,     // 64 mtn Shdn
+    CPM_ALERT_MTR_BAD_SETUP_PARAMS_BIT          = DRV_ALERT_MTR_BAD_SETUP_PARAMS_BIT,   // 66 sw Shdn
+    CPM_ALERT_SVO_HARDSTOP_RELEASE_BIT          = DRV_ALERT_SVO_HARDSTOP_RELEASE_BIT,   // 67 mtn Shdn
+    CPM_ALERT_SVO_TRACKING_CRIT_BIT             = DRV_ALERT_SVO_TRACKING_CRIT_BIT,      // 69 mtn Shdn
+    CPM_ALERT_SVO_RMS_OVERLOAD_BIT              = DRV_ALERT_SVO_RMS_OVERLOAD_BIT,       // 70 mtn Shdn
+    CPM_ALERT_SVO_RMS_CRIT_OVERLOAD_BIT         = DRV_ALERT_SVO_RMS_CRIT_OVERLOAD_BIT,  // 71 mtn Shdn
+    CPM_ALERT_SVO_STEP_NOISE_BIT                = DRV_ALERT_SVO_STEP_NOISE_BIT,         // 73 mtn Shdn
+    CPM_ALERT_SVO_VOLT_SAT_BIT                  = DRV_ALERT_SVO_VOLT_SAT_BIT,           // 74 mtn Shdn
+    CPM_ALERT_SVO_TRQ_SAT_BIT                   = DRV_ALERT_SVO_TRQ_SAT_BIT,            // 75 mtn Shdn
+    CPM_ALERT_NOCOMM_DIST_ERROR_BIT             = DRV_ALERT_NOCOMM_DIST_ERROR_BIT,      // 76 mtn Shdn
+    CPM_ALERT_NOCOMM_DIRECTION_ERROR_BIT        = DRV_ALERT_NOCOMM_DIRECTION_ERROR_BIT, // 77 mtn Shdn
+    CPM_ALERT_NOCOMM_FAIL_BIT                   = DRV_ALERT_NOCOMM_FAIL_BIT,            // 78
+    CPM_ALERT_MTR_ENC_INDEX_MISSING_WARN_BIT    = DRV_ALERT_MTR_ENC_INDEX_MISSING_WARN_BIT, // 79
+    CPM_ALERT_TEMP_DRIVE_BIT                    = DRV_ALERT_TEMP_AMBIENT_BIT,           // 80 mtn Shdn
+    CPM_ALERT_TEMP_STATOR_BIT                   = DRV_ALERT_TEMP_HEATSINK_BIT,          // 81 mtn Shdn
+    CPM_ALERT_BUS_OVERCURRENT_BIT               = DRV_ALERT_BUS_OVERCURRENT_BIT,        // 82 mtn Shdn
+    CPM_ALERT_BUS_OVERVOLTAGE_BIT               = DRV_ALERT_BUS_OVERVOLTAGE_BIT,        // 83 mtn Shdn
+    CPM_ALERT_BUS_VOLTAGE_LOW_BIT               = DRV_ALERT_BUS_VOLTAGE_LOW_BIT,        // 84 mtn Shdn
+    CPM_ALERT_BUS_RMS_OVERLOAD_BIT              = DRV_ALERT_BUS_RMS_OVERLOAD_BIT,       // 85 mtn Shdn
+    CPM_ALERT_BUS_PWR_MISMATCH_BIT              = 86,                                   // 86 Power issue (v1.6)
+    CPM_ALERT_MTR_ENC_INDEX_MISSING_BIT         = DRV_ALERT_MTR_ENC_INDEX_MISSING_BIT,  // 87
+    CPM_ALERT_BUS_VOLTAGE_UNDER_OPERATING_V_BIT = 88,                                   // 88 Power issue (v1.6)
+    CPM_ALERT_FW_MOVEGEN_LIMSW_LOCKDN_BIT       = DRV_ALERT_FW_MOVEGEN_LIMSW_LOCKDN_BIT,// 91
+    CPM_ALERT_FW_MOVEGEN_SOFTLIM_LOCKDN_BIT     = DRV_ALERT_FW_MOVEGEN_SOFTLIM_LOCKDN_BIT, // 92
+    CPM_ALERT_MTR_ENC_INDEX_MISPLACED_BIT       = DRV_ALERT_MTR_ENC_INDEX_MISPLACED_BIT,// 93
+    CPM_ALERT_STEPS_DURING_POSN_RECOVERY_BIT    = 94,                                   // 94
+} cpmAlertBits;
+
+//                                                                            *
+//*****************************************************************************
+													/** \endcond **/
+
+
+													/** \cond INTERNAL_DOC **/
+//*****************************************************************************
+//  NAME                                                                      *
+//      alertLogEntry structure and definitions
+//
+// CREATION DATE:
+//      02/11/2010 17:40:47
+//
+//  DESCRIPTION:
+/**
+    \brief Alert Log Entry Register.
+
+    The \e reason code will describe the format of the \e tstamp field.
+    The following table describes the formats.
+        ------------------------------------------------------------------
+        |     code            |  tstamp meaning                          |
+        ------------------------------------------------------------------
+        ALERT_LOG_EPOCH_CODE    seconds since 1/1/2010 00:00:00Z (UTC)
+        All others              tenths of seconds of unit up-time.
+
+    A log file processor will read the oldest entry and if an
+    ALERT_LOG_EPOCH_CODE is detected, the following timestamps may use
+    this entry to offset the timestamp to represent a time in the local
+    locale.
+**/
+typedef struct _alertLogEntry {
+    Uint32 Timestamp;               ///< Time stamp code
+	union _alertReasons {
+    	commonAlertBits common;
+		drvAlertBits isc;
+		cpmAlertBits cpm;
+		Uint32 bits;
+		// Common translators
+		void operator=(const commonAlertBits updVal) { common = updVal; }
+		void operator=(const drvAlertBits updVal) { isc = updVal; }
+		void operator=(const cpmAlertBits updVal) { cpm = updVal; }
+		bool operator==(const commonAlertBits lVal) { return common == lVal; }
+		bool operator!=(const commonAlertBits lVal) { return common != lVal; }
+		// Common constructors
+		_alertReasons(const commonAlertBits initVal) { common=initVal; }
+		_alertReasons(const drvAlertBits initVal) { isc=initVal; }
+		_alertReasons(const cpmAlertBits initVal) { cpm=initVal; }
+		_alertReasons() { bits = 0; }
+	} Reason;            ///< Reason and/or description
+} alertLogEntry;
+// - - - - - - - - - - - - - - - - -
+// Alert command arguments
+// - - - - - - - - - - - - - - - - -
+// Clear out all entries
+#define ALERT_ARG_CLEAR         ALERT_LOG_FREE_CODE
+// Update/create the wall clock time epoch value
+#define ALERT_ARG_GET_OLDEST    0
+//                                                                            *
+//*****************************************************************************
+													/** \endcond **/
+
+
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
+// STATUS REGISTER UNIONS AS "REGISTERS" WITH BIT-WISE AND FLD ACCESS
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
+
+ 													/** \cond ISC_DOC **/
+//*****************************************************************************
+// NAME                                                                       *
+//  lowAttnReg union
+//
+// DESCRIPTION
+/**
+    \brief <i>Lower Attentionable</i> portion of the <i>Status Register</i>.
+
+    This portion of the Status Register (#mnStatusReg) can be used to generate
+    attention packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef union PACK_BYTES _lowAttnReg {
+	/**
+		Bit-wise parallel access to the lower 16-bits of the status register.
+	**/
+	Uint16 bits;
+	/**
+		Common fields in the lower 16-bits of the status register
+	**/
+	lowAttnCommonFlds Common;
+	/**
+		Meridian ISC view of the lower 16-bits of the status register.
+	**/
+	iscLowAttnFlds DrvFld;
+} lowAttnReg;
+//                                                                            *
+//*****************************************************************************
+													/** \endcond **/
+
+
+ 													/** \cond ISC_DOC **/
+//*****************************************************************************
+// NAME                                                                       *
+//  nonAttnReg union
+//
+// DESCRIPTION
+
+/**
+    \brief Non-Attentional portion of the <i>Status Register</i>.
+
+    The most significant sixteen bit portion of the <i>Status Register</i>
+    (#mnStatusReg).
+    This portion of the register does not generate any attention packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef union PACK_BYTES _nonAttnReg {
+    /// Register view as an integer
+    Uint16 bits;
+    /**
+		Common non-attentionable fields
+	**/
+    nonAttnCommonFlds Common;
+	/**
+		Meridian ISC non-attentionable fields
+	**/
+    iscNonAttnFlds DrvFld;
+	// 12/21/2015 Delete me as this is handled by the new status register def
+	//ClearPathNonAttnReg ClrPathFld;
+} nonAttnReg;                       ///< Field access for the non-attention
+                                    ///< part of Status Register.
+//                                                                            *
+//*****************************************************************************
+													/** \endcond **/
+
+
+ 													/** \cond ISC_DOC **/
+//*****************************************************************************
+// NAME                                                                       *
+//  plaInReg union
+//
+// DESCRIPTION
+/**
+	\cond ISC_DOC
+    \brief <i>PLA Inputs</i> portion of the <i>Status Register</i>.
+
+    The middle portion of the Status Register (#mnStatusReg) that feeds the PLA
+    function. The lower eight bits can be used to generate attention
+    packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef union PACK_BYTES _plaInReg {
+    /// View of register as an integer
+    Uint16 bits;
+	/// Common fields across all devices in this register part
+	plaInCommonFlds Common;
+	/**
+		Meridian ISC view of the middle 16-bits of the status register. These
+		bits feed the PLA feature.
+	**/
+	iscPlaInFlds DrvFld;
+} plaInReg;
+//                                                                            *
+//*****************************************************************************
+													/** \endcond **/
+
+
+
+ 													/** \cond ISC_DOC **/
+//*****************************************************************************
+//  NAME                                                                      *
+//      plaOutReg union
+//
+// CREATION DATE:
+//      02/17/2010 16:08:32
+//
+//  DESCRIPTION:
+/**
+	\cond ISC_DOC
+    \brief PLA/Output Register Types.
+
+    This is a container that defines the outputs from the PLA structure
+    as well as the internal nexus to electrical outputs and internal
+    "feature" strobes.
+
+    The #iscGetUserOutputReg and #iscSetUserOutputReg functions are typically
+    used to control this register. Autonomous control of this register can be
+    done via the PLA Feature. 
+
+	\see \ref ISCplaPage
+
+    To check on the operations of the Output Register there are a number of
+    accumulating registers based on the sample-by-sample basis. These read-only
+    functions can access what happened to the output register since the last
+    request
+        - #iscGetOutputReg gets a copy of the current state
+        - #iscGetOutputRiseReg gets and clears the bits that have risen since
+        the last request.
+        - #iscGetOutputFallReg gets and clears the bits that have risen since
+        the last request.
+
+    \warning
+    For multi-threaded applications care must be taken to provide
+    serialization for the read-modify-write actions as well as accumulating
+    the Rise and Fall transition registers for use by your application.
+
+    The following diagram shows the layout of this register.
+        \image html "ISC_Out_Reg.png"
+        \image latex "ISC_Out_Reg.eps"
+**/
+typedef union PACK_BYTES _plaOutReg {
+    /// Integer view of the output register
+    Uint16 bits;
+    // Common outputs for all nodes
+    struct _plaOutCommonFlds {
+        int na0_4       : 5;
+        /**
+			\brief Generate node stop on asserting edge.
+
+            The asserting edge (0->1) of this bit will initiate the node stop
+            programmed in the Stop Type register (#ISC_P_STOP_TYPE).
+        **/
+        int NodeStop    : 1;    // Issue NodeStop
+    } Common;                   ///< Output fields common to all nodes.
+    /// Meridian ISC Specific Outputs
+	iscOutFlds DrvFld;
+#if defined(IMPL_NODE_CP)
+	/// ClearPath
+	clearPathOutFlds ClearPathFld;
+#endif
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC)
+	/// ClearPath-SC specific definitions
+	cpmOutFlds cpm;
+#endif
+	#ifdef __cplusplus
+    /// Zero out bits.
+    void clear() {
+        bits = 0;
+    };
+    #endif
+} plaOutReg;
+//                                                                            *
+//*****************************************************************************
+														/** \endcond **/
+
+
+														/** \cond ISC_DOC **/
+//*****************************************************************************
+//  NAME                                                                      *
+//      plaFuses structure
+//
+// CREATION DATE:
+//      10/12/2010 16:13
+//
+//  DESCRIPTION:
+/**
+    \brief PLA fuse buffer.
+
+    These bits are used to program a section of a node's PLA feature. All 
+	areas of the PLA are represented by this buffer.
+
+	\see \ref ISCplaPage
+	\see \ref plaFuseBuffer
+
+    Expected usage:
+    \code
+    plaFuseBuffer fuses;
+    // Select the OR area
+    fuses.FuseArea = plaFuseBuffer::PLA_OR;
+    // Select output # 7
+    fuses.FuseIndex.fld.Index = 7;
+    // Select AND term # 1
+    fuses.Fuses.orFuse.and01 = 1;
+    \endcode
+
+**/
+typedef union _plaFuses {
+    /// Integer view the fuses.
+    Uint16 bits;
+    /// The bits in this structure select the input bits or their complement
+    /// to be ANDed together.
+    plaInReg andFuse;
+    /// The bits in this structure select the AND outputs to be
+    /// ORed together to make an output bit.
+    struct  _orFuses {
+        unsigned and00        : 1;                ///< Select AND term 00
+        unsigned and01        : 1;                ///< Select AND term 01
+        unsigned and02        : 1;                ///< Select AND term 02
+        unsigned and03        : 1;                ///< Select AND term 03
+        unsigned and04        : 1;                ///< Select AND term 04
+        unsigned and05        : 1;                ///< Select AND term 05
+        unsigned and06        : 1;                ///< Select AND term 06
+        unsigned and07        : 1;                ///< Select AND term 07
+        unsigned and08        : 1;                ///< Select AND term 08
+        unsigned and09        : 1;                ///< Select AND term 09
+        unsigned and10        : 1;                ///< Select AND term 10
+        unsigned and11        : 1;                ///< Select AND term 11
+        unsigned and12        : 1;                ///< Select AND term 12
+        unsigned and13        : 1;                ///< Select AND term 13
+        unsigned and14        : 1;                ///< Select AND term 14
+        unsigned and15        : 1;                ///< Select AND term 15
+    } orFuse;                               ///< OR term selector type.
+    /// The bits in this structure select the output bits.
+    plaOutReg outFuse;
+    #ifdef __cplusplus
+    /// C++ Helper Constructor with no bits set.
+    _plaFuses() {
+        bits = 0;
+    };
+    /// C++ Helper Constructor with an integer setup.
+    _plaFuses(Uint16 initialBits) {
+        bits = initialBits;
+    };
+    #endif
+} plaFuses;
+//                                                                            *
+//*****************************************************************************
+														/** \endcond **/
+
+
+														/** \cond ISC_DOC **/
+//*****************************************************************************
+//  NAME                                                                      *
+//      plaFuseBuffer structure
+//
+// CREATION DATE:
+//      10/12/2010 16:13
+//
+//  DESCRIPTION:
+/**
+    \brief PLA term buffer.
+
+    The \a FuseArea and \a FuseIndex fields of this register select a section of
+    the PLA feature within a node. For the #netPLAget function this \a Fuses
+    (#plaFuses) area contains the fuses retrieved from the specified area of
+    the PLA. For the #netPLAset function the \a Fuses area contains the fuses
+    to program.
+
+	\section plaAreaSect Fuse Areas
+
+    The \a FuseArea field selects the specific fuse area in the PLA array.
+    
+    The PLA has the following areas:
+		- AND terms that AND the inputs to feed an OR term.
+		- NOT AND terms AND the inverted inputs to feed an OR term.
+		- OR terms are associated to an output bit to be controlled by
+		the values present on the input register.
+		- OPTION fuses allow access to internal features such as
+		the output inverter to convert AND terms into OR terms via
+		the DeMorgan process.
+		- The architectural area allows generic access to determine the
+		count of terms available in the PLA areas.
+		.
+
+	\section plaIndexSect Index
+
+	The PLA fuse buffer's \a FuseIndex field selects a specific set of fuses
+	within the selected area. These fuses are sixteen bit arrays that connect
+	the intersecting input to the specified function. In the AND area this is
+	the equivalent to a sixteen input AND gate. For the OR area this is a
+	sixteen bit OR gate  ORing the selected AND terms together.
+
+	The index for current devices runs from 0 to 15.
+
+	\see \ref ISCplaPage
+	\see \ref plaFuses
+
+    Expected use cases:
+        \code
+        plaFuseBuffer fuses;
+        // Copy GP Timer expire bit to AND(0)
+        // Select the AND area
+        fuses.FuseArea = plaFuseBuffer::PLA_AND;
+        // Assign to term # 0
+        fuses.FuseIndex.fld.Index = 0;
+        // Select the TimerExpired input bit
+        fuses.Fuses.andFuse.DrvFld.TimerExpired = 1;
+        \endcode
+
+        \code
+        // Setup for OR area for drive enable and clear fuses.
+        plaFuseBuffer fuses;
+        fuses.Setup(plaFuseBuffer::PLA_OR, ISC_PLAOUT_ENABLE_BIT, 0x0);
+        \endcode
+**/
+typedef struct _plaFuseBuffer {
+    /// PLA fuse area enumeration.
+    typedef enum _PLA_AREAS {
+        PLA_AND,                /* 0 */ ///< Inputs AND fuses area.
+        PLA_NAND,               /* 1 */ ///< Inverted inputs AND fuses area.
+        PLA_OR,                 /* 2 */ ///< OR of AND outputs.
+        PLA_OPTION,             /* 3 */ ///< Optional fuse area.
+        PLA_ARCH                /* 4 */ ///< Architectural information area.
+    } PLA_AREAS;
+    /// Fuse Area selector.
+    PLA_AREAS FuseArea;
+    /// PLA Fuse Index
+    typedef union _plaIndex {
+        Uint16   bits;                  ///< Bit-wise access
+        struct {
+            BFld Index      : 7;        ///< Zero based index number.
+            BFld EEalso     : 1;        ///< Access the non-volatile fuses.
+        } fld;                          ///< Field Access for the index.
+		/// Constructs PLA index of zero accessing the RAM item.
+        _plaIndex() {
+            bits = 0;
+        };
+    } plaIndex;                       	// PLA Index type.
+	/// Index and options selection.
+    plaIndex FuseIndex;               	
+    /// Fuse settings.
+    plaFuses Fuses;
+    /// Option Area Indices
+    typedef enum _PLA_OPT_INDICES {
+		/**
+			Output Inverters.
+
+			This set of fuses is useful for converting a series of OR
+			terms into one AND term using DeMorgan's theorem.
+		**/
+        OPTION_INVERTER                 /* 0 */ 
+    } PLA_OPT_INDICES;
+    /// Architectural Area Indices.
+    typedef enum _ARCH_INDICES {
+        AND_TERMS,                      /* 0 */ ///< Count of AND terms.
+        OR_TERMS,                       /* 1 */ ///< Count of OR terms.
+        OPTION_REGS                     /* 2 */ ///< Count of option registers.
+    } ARCH_INDICES;
+    #ifdef __cplusplus
+    /// C++ Helper Constructor (default).
+    _plaFuseBuffer() {
+        FuseArea = PLA_AND;
+        FuseIndex.bits = 0;
+        Fuses.bits = 0;
+    };
+    /// C++ Helper Constructor (initialized).
+    _plaFuseBuffer(PLA_AREAS area, Uint16 index, Uint16 fuses) {
+        FuseArea = area;
+        FuseIndex.bits = index;
+        Fuses.bits = fuses;
+    };
+    /// C++ Initializer for writing
+    void Setup(PLA_AREAS area, Uint16 index, Uint16 fuses) {
+        FuseArea = area;
+        FuseIndex.bits = index;
+        Fuses.bits = fuses;
+    };
+    /// C++ Initializer for reading
+    void Setup(PLA_AREAS area, Uint16 index) {
+        FuseArea = area;
+        FuseIndex.bits = index;
+        Fuses.bits = 0;
+    };
+    #endif
+} plaFuseBuffer;                                ///< PLA fuse buffer type.
+//																			  *
+//*****************************************************************************
+														/** \endcond **/
+
+														/** \cond CPM_ADV **/
+//*****************************************************************************
+//  NAME                                                                      *
+//      xpsFuseBuffer structure
+//
+// CREATION DATE:
+//      09/29/2015 16:13
+//
+//  DESCRIPTION:
+/**
+    \brief XPS term buffer.
+
+    The \a FuseArea and \a FuseIndex fields of this register select a section of
+    the XPS feature within a node. For the #netXPSget function this \a Fuses
+    (#xpsFuses) area contains the fuses retrieved from the specified area of
+    the XPS. For the #netXPSset function the \a Fuses area contains the fuses
+    to program.
+
+	\section xpsAreaSect Fuse Areas
+
+    The \a FuseArea field selects the specific fuse area in the XPS array.
+
+    The XPS has the following areas:
+    	- INPUT_OPTION fuses allow inversion of the inputs before entering
+    	the OR section
+		- OR terms are associated to an output bit to be controlled by
+		the values present on the input register.
+		- OPTION fuses allow access to internal features such as
+		the output inverter to convert AND terms into OR terms via
+		the DeMorgan process.
+		- The architectural area allows generic access to determine the
+		count of terms available in the XPS areas.
+
+	\section xpsIndexSect Index
+
+	The XPS fuse buffer's \a FuseIndex field selects a specific set of fuses
+	within the selected area. These fuses are sixteen bit arrays that connect
+	the intersecting input to the specified function. In the AND area this is
+	the equivalent to a sixteen input AND gate. For the OR area this is a
+	sixteen bit OR gate  ORing the selected AND terms together.
+
+	The index for current devices runs from 0 to 15.
+
+	\see \ref ISCplaPage
+	\see \ref plaFuses
+
+    Expected use cases:
+        \code
+        plaFuseBuffer fuses;
+        // Copy GP Timer expire bit to AND(0)
+        // Select the AND area
+        fuses.FuseArea = plaFuseBuffer::XPS_AND;
+        // Assign to term # 0
+        fuses.FuseIndex.fld.Index = 0;
+        // Select the TimerExpired input bit
+        fuses.Fuses.andFuse.DrvFld.TimerExpired = 1;
+        \endcode
+
+        \code
+        // Setup for OR area for drive enable and clear fuses.
+        plaFuseBuffer fuses;
+        fuses.Setup(plaFuseBuffer::XPS_OR, ISC_XPSOUT_ENABLE_BIT, 0x0);
+        \endcode
+**/
+typedef struct _xpsFuseBuffer {
+    /// XPS fuse area enumeration.
+    typedef enum _XPS_AREAS {
+    	XPS_IN_OPTION,          /* 0 */ ///< Optional Input fuse area.
+        XPS_OR,                 /* 1 */ ///< OR of AND outputs.
+        XPS_OPTION,             /* 2 */ ///< Optional fuse area.
+        XPS_ARCH                /* 3 */ ///< Architectural information area.
+    } XPS_AREAS;
+    /// Fuse Area selector.
+    XPS_AREAS FuseArea;
+    /// XPS Fuse Index
+    typedef union _xpsIndex {
+        Uint16   bits;                  ///< Bit-wise access
+        struct {
+            BFld Index      : 7;        ///< Zero based index number.
+            BFld EEalso     : 1;        ///< Access the non-volatile fuses.
+        } fld;                          ///< Field Access for the index.
+		/// Constructs XPS index of zero accessing the RAM item.
+        _xpsIndex() {
+            bits = 0;
+        };
+    } xpsIndex;                       	// XPS Index type.
+	/// Index and options selection.
+    xpsIndex FuseIndex;
+    /// Fuse settings.
+    plaFuses Fuses;
+    /// Option Area Indices
+    typedef enum _XPS_OPT_INDICES {
+		/**
+			Output Inverters.
+
+			This set of fuses is useful for converting a series of OR
+			terms into one AND term using DeMorgan's theorem.
+		**/
+        OPTION_INVERTER                 /* 0 */
+    } XPS_OPT_INDICES;
+    /// Architectural Area Indices.
+    typedef enum _ARCH_INDICES {
+        AND_TERMS,                      /* 0 */ ///< Count of AND terms.
+        OR_TERMS,                       /* 1 */ ///< Count of OR terms.
+        OPTION_REGS                     /* 2 */ ///< Count of option registers.
+    } ARCH_INDICES;
+    #ifdef __cplusplus
+    /// C++ Helper Constructor (default).
+    _xpsFuseBuffer() {
+        FuseArea = XPS_OR;
+        FuseIndex.bits = 0;
+        Fuses.bits = 0;
+    };
+    /// C++ Helper Constructor (initialized).
+    _xpsFuseBuffer(XPS_AREAS area, Uint16 index, Uint16 fuses) {
+        FuseArea = area;
+        FuseIndex.bits = index;
+        Fuses.bits = fuses;
+    };
+    /// C++ Initializer for writing
+    void Setup(XPS_AREAS area, Uint16 index, Uint16 fuses) {
+        FuseArea = area;
+        FuseIndex.bits = index;
+        Fuses.bits = fuses;
+    };
+    /// C++ Initializer for reading
+    void Setup(XPS_AREAS area, Uint16 index) {
+        FuseArea = area;
+        FuseIndex.bits = index;
+        Fuses.bits = 0;
+    };
+    #endif
+} xpsFuseBuffer;                                ///< XPS fuse buffer type.
+//																			  *
+//*****************************************************************************
+												/** \endcond **/
+
+
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      mnOutReg structure
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+						/** \cond INTERNAL_DOC **/
+/**
+    \brief Universal Output Register Type.
+
+	This object is used to represents the state of an <i>Output Register</i>
+	in a node. 
+
+	\todo add link to class
+**/
+typedef union MN_EXPORT PACK_BYTES _mnOutReg 
+{
+    /// Integer view of the output register
+    Uint16 bits;
+	// Meridian ISC outputs (TODO - Restore for ISC support)
+	//plaOutReg isc;
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC)
+	/// ClearPath-SC specific field access
+	cpmOutFlds cpm;
+#endif
+	//
+    #ifdef __cplusplus
+    /// Zero out all the fields.
+    void clear() {
+        bits = 0;
+    }
+	/**
+	Return true if all fields are clear
+	**/
+	bool isClear() {
+		return bits == 0;
+	}
+												
+	/// Construct with all zeros
+	_mnOutReg() 
+	{
+		clear();
+	}
+												
+    #endif
+} mnOutReg;
+									/** \endcond  **/
+//                                                                         *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  mnStatusReg union
+//
+// DESCRIPTION
+/**
+    \brief Universal Status Register Type
+
+    This Union defines the Universal Status Register for all types of Nodes.
+
+	The Status register is used to reflect the state of the Node.  Status events
+	occur when bits/fields of this register are set/cleared.    
+
+	The lower 32 bits of this register can be used to generate an asynchronous
+	attention packet to signal the host an event occurred.
+
+
+	\see sFnd::ValueStatus Class for accessing Status registers within the Node.
+	\see cpmStatusRegFlds For the Complete list of ClearPath-SC alert Fields.
+	\see \ref AttentionsPage for more information regarding Attentions.
+**/
+typedef union MN_EXPORT PACK_BYTES _mnStatusReg {
+    /// Integer view as three 16-bit integers.
+    Uint16 bits[3];
+	/// Long integer view that represents the attentional bits
+	Uint32 attnBits;
+													/** \cond ISC_DOC **/
+    /**
+        Access to common status field for all nodes.
+    **/
+    commonStatusFlds Common;
+													
+	/**
+		Access to the status for the Meridian ISC. This is the new
+		style flat accessor.
+	**/
+	iscStatusRegFlds isc;
+	/**
+		Access to the status register for the Meridian ISC compatible with
+		the sFoundation's first release.
+	**/
+	iscStatusRegOldFlds Fld;
+													/** \endcond **/
+	/**
+		\brief Access to the ClearPath-SC status fields
+	**/
+	cpmStatusRegFlds cpm;
+													/** \cond INTERNAL_DOC **/
+    #ifdef __cplusplus
+	/// Indices into bitwise register access by functional purpose
+	typedef enum _bitsTypes {
+		LOW_ATTN,		///< Lower 16-bits of the attentionable portion
+		IN_REG, 		///< Upper 16-bits of the attentionable portion
+		NON_ATTN		///< Non-attentionable portion
+	} bitsTypes;
+	/// The number of Uint16 items in the register.
+	enum {N_BITS = 3};
+													
+    /**
+		Clear the register bits in this instance.
+	**/
+    void clear() {
+        bits[LOW_ATTN] = bits[IN_REG] = bits[NON_ATTN] = 0;
+    }
+	/**
+		See if the register is all zeros.
+	**/
+	bool isClear() {
+		return (bits[LOW_ATTN] | bits[IN_REG] | bits[NON_ATTN]) == 0;
+	}
+																/** \endcond **/
+
+#ifndef __TI_COMPILER_VERSION__
+	/**
+		\brief Update a string with the set fields in the Status Register.
+
+		\param[in,out] buffer  Point to string buffer to update.
+		\param[in] size  The size of the buffer in characters including the null
+		character.
+		\return the parameter \a buffer.
+
+		\CODE_SAMPLE_HDR
+		char myBuffer[500];
+		cout << myNode.Status.RT.Value.StateStr(myBuffer, sizeof(myBuffer));
+		\endcode
+	**/
+	char * StateStr(char *buffer, size_t size) {
+		return (cpm.StateStr(buffer, size));
+	}
+#endif
+													/** \cond INTERNAL_DOC **/
+	// Construct a cleared register
+	_mnStatusReg() {
+		clear();
+	}
+    #endif
+													/** \endcond **/
+} mnStatusReg;
+/** \cond INTERNAL_DOC **/
+/// Alias to older usage
+typedef mnStatusReg attnReg;			// 1/5/16 Made equivalent
+// True size of the mnStatusReg
+#define MN_STATUS_REG_OCTETS	6
+/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  mnAuditData structure
+//
+// DESCRIPTION
+													/** \cond SC_EXPERT **/
+/**
+    \brief Motion Audit data type.
+
+    This structure is updated with the VB friendly results of the
+	motion audit collection command. This typically queried after the
+	reference move has occurred. 
+	
+	\note This feature appears on ISC firmware version 5.6 and later and
+	ClearPath-SC with the advanced feature set.
+**/
+typedef struct PACK_BYTES _mnAuditData {
+	double			LowPassRMS;		///< Low Pass RMS of monitor port value
+	double			LowPassMaxPos;	///< Maximum positive of monitor port value
+	double			LowPassMaxNeg;	///< Maximum negative of monitor port value
+	double			HighPassRMS;	///< High Pass RMS of monitor port value
+	double			DurationMS;		///< Duration (msec)
+	nodelong		MaxTrackingPos;	///< Maximum positive tracking
+	nodelong		MaxTrackingNeg;	///< Maximum negative tracking
+} mnAuditData;
+													/** \endcond  **/
+													/** \cond ISC_DOC **/
+/// Backwards compatible typename
+typedef struct _mnAuditData iscDataCollect;
+													/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME                                                                       *
+//  mnAppConfigReg union
+//
+// DESCRIPTION										/** \cond ExpertDoc **/
+/**
+\brief Universal Application Configuration Register Type
+
+This union defines a container for all types of nodes to control application
+settings.
+**/
+typedef union PACK_BYTES _mnAppConfigReg {
+	/// Bit-wise generic access
+	nodeulong		bits;
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC)
+	/// ClearPath-SC based register
+	cpmAppConfigFlds cpm;
+#endif
+	/// Meridian ISC based register
+	iscAppConfigFlds isc;
+} mnAppConfigReg;
+													/** \endcond  **/
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  mnHwConfigReg union
+//
+// DESCRIPTION
+												/** \cond ExpertDoc **/
+/**
+\brief Universal Hardware Configuration Register Type
+
+This union defines a container for all types of hardware configurations on 
+nodes.
+**/
+typedef union PACK_BYTES _mnHwConfigReg {
+	/// Bit-wise generic access
+	nodeulong		bits;
+#if !defined(__TI_COMPILER_VERSION__) || defined(_CPM_SC)
+	/// ClearPath-SC based register
+	cpmHwConfigFlds cpm;
+#endif
+	/// Meridian ISC based register
+	iscHwConfigFlds isc;
+} mnHwConfigReg;
+												/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// Restore packing rules
+#ifdef _MSC_VER
+#pragma pack(pop)
+#endif
+//*****************************************************************************
+
+#endif
+//=============================================================================
+//  END OF FILE pubCoreRegs.h
+//=============================================================================
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmAPI.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmAPI.h
new file mode 100644
index 000000000..6322153e4
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmAPI.h
@@ -0,0 +1,165 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubCpmAPI.h $
+// $Revision: 18 $ $Date: 12/09/16 2:43p $
+// $Workfile: pubCpmAPI.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	sFoundation definitions for programming the ClearPath-SC nodes.
+**/
+// CREATION DATE:
+//		2015-12-02 16:26:15
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __PUBCPM_API_H__
+#define __PUBCPM_API_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	pubCPM_API.h headers
+//
+	#include "tekTypes.h"
+	#include "pubNetAPI.h"
+	#include "pubCpmRegs.h"
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubCPM_API.h constants
+//
+typedef enum _cpmParams cpmParams;
+// 
+//																			  *
+//*****************************************************************************
+
+ 
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubCPM_API.h function prototypes
+//
+//
+//------------------------------------------
+// Parameter Group
+//------------------------------------------
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __TI_COMPILER_VERSION__
+
+MN_EXPORT cnErrCode MN_DECL cpmGetParameter(
+			multiaddr theMultiAddr,			// Node address
+			cpmParams theParam,			// Parameter index
+			double *pParamVal);				// Ptr to value area
+
+// Update the local parameter table and update node
+MN_EXPORT cnErrCode MN_DECL cpmSetParameter(
+			multiaddr theMultiAddr,	 		// Node address
+			cpmParams theParam,			// Parameter index
+			double paramVal);				// New value
+
+
+//------------------------------------------
+// Motion Group
+//------------------------------------------
+
+// Change axis to new velocity target / optional trigger
+MN_EXPORT cnErrCode MN_DECL cpmForkVelMove(
+			multiaddr theMultiAddr,			// Destination node
+			double velTargetStepsPerSec,	// Target velocity (steps/sec)
+			nodebool triggered,				// Start move with trigger
+			nodelong *pBuffersRemaining=NULL);	// Ptr to move buf remaining cnt		
+
+// Initiate positional move to target
+MN_EXPORT cnErrCode MN_DECL cpmForkPosnMove( 
+			multiaddr theMultiAddr,			// Destination node
+			nodelong posnTarget,			// Distance (steps)
+			mgPosnStyle moveType,			// Motion style
+			nodelong *pBuffersRemaining=NULL);	// Ptr to move buf remaining cnt		
+
+MN_EXPORT cnErrCode MN_DECL cpmForkProfiledMove(
+			multiaddr theMultiAddr,			// Destination node
+			mgMoveProfiledInfo *spec,		// Motion specification
+			nodelong *pBuffersRemaining);	// Ptr to move buf remaining cnt
+
+//------------------------------------------
+// Status Group
+//------------------------------------------
+MN_EXPORT cnErrCode MN_DECL cpmGetStatusAccumReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmStatusReg *pStatus);			// Current setting
+MN_EXPORT cnErrCode MN_DECL cpmGetAttnStatusRiseReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmStatusReg *pStatus);			// Current setting
+MN_EXPORT cnErrCode MN_DECL cpmGetStatusFallReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmStatusReg *pStatus);			// Current setting
+MN_EXPORT cnErrCode MN_DECL cpmGetStatusRTReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmStatusReg *pStatus);			// Current setting
+
+// Alert and Warning Register Access
+MN_EXPORT cnErrCode MN_DECL cpmGetAlertReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAlertReg *pAlertReg);		// Current setting
+MN_EXPORT cnErrCode MN_DECL cpmGetWarningReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAlertReg *pWarningReg);		// Current setting
+
+//------------------------------------------
+// Homing Group
+//------------------------------------------
+// Initiate the homing sequencer on the specified axis
+MN_EXPORT cnErrCode MN_DECL cpmSendHome(
+			multiaddr theMultiAddr);		// Destination node
+
+//------------------------------------------
+// Setup Group
+//------------------------------------------
+MN_EXPORT cnErrCode MN_DECL cpmSetUserOutputReg (
+			multiaddr theMultiAddr,			// Node address
+			cpmOutReg *pOutReg);		// New setting
+MN_EXPORT cnErrCode MN_DECL cpmGetUserOutputReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmOutReg *pOutReg);		// Current setting
+// Configuration Registers
+MN_EXPORT cnErrCode MN_DECL cpmSetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmHwConfigReg hwConfigReg);	// Current setting
+MN_EXPORT cnErrCode MN_DECL cpmGetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmHwConfigReg *pHwConfigReg);	// Current setting
+
+MN_EXPORT cnErrCode MN_DECL cpmSetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAppConfigReg appConfigReg);	// Current setting
+MN_EXPORT cnErrCode MN_DECL cpmGetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAppConfigReg *pAppConfigReg);	// Current setting
+//																			  *
+//*****************************************************************************
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+//============================================================================= 
+//	END OF FILE pubCPM_API.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmAdvAPI.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmAdvAPI.h
new file mode 100644
index 000000000..b09e28c17
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmAdvAPI.h
@@ -0,0 +1,197 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/inc/pubCpmAdvAPI.h $
+// $Revision: 12 $ $Date: 12/13/16 12:19p $
+// $Workfile: pubCpmAdvAPI.h $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief Function prototypes and constants related to the ClearPath-SC
+	motor API.
+
+	\ingroup CPMgrp
+	@{
+
+**/
+// CREATION DATE:
+//		8/2/2011 refactored from Meridian pubIscAPI.h
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//                                                                            *
+//*****************************************************************************
+
+#ifndef __PUB_CPM_ADV_API_H_
+#define __PUB_CPM_ADV_API_H_
+
+#include "mnParamDefs.h"
+#include "pubCpmRegs.h"
+#include "pubNetAPI.h"
+
+//////////////////////
+// PUBLIC FUNCTIONS	//
+//////////////////////
+
+/// Helper function to convert volatile parameter access reference into
+/// a non-volatile parameter access.
+inline cpmParams cpmNonVol(cpmParams volParam) {
+	return((cpmParams)(volParam|PARAM_OPT_MASK));
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Restore the parameters to factory default state
+MN_EXPORT cnErrCode MN_DECL cpmFactoryDefaults(
+			multiaddr theMultiAddr);	    // Destination node
+
+// Restore the parameters to factory default state
+MN_EXPORT cnErrCode MN_DECL cpmFactoryDefaultsEx(
+	multiaddr theMultiAddr,	    // Destination node
+	bool skipShutdownRisks);	// Skip some params which may cause shutdown
+
+
+MN_EXPORT cnErrCode MN_DECL cpmGetParameterEx(
+			multiaddr theMultiAddr,		// Node address
+			cpmParams theParam,			// Parameter index
+			paramValue *pParamVal,		// Ptr to value area
+			paramInfo *pParamInfo);		// Ptr to information area
+
+
+// Update the local parameter table and update node using a buffer
+MN_EXPORT cnErrCode MN_DECL cpmSetParameterEx(
+			multiaddr theMultiAddr,		// Node address
+			cpmParams theParam,			// Parameter index
+			packetbuf *pNewValue);		// New value
+
+// Adjust the position command
+MN_EXPORT cnErrCode MN_DECL cpmAddToPosition(
+			multiaddr theMultiAddr,		// Node address
+			double theOffset);			// Offset from current location
+
+// Register parameter change function
+MN_EXPORT paramChangeFunc MN_DECL cpmParamChangeFunc(
+	  		paramChangeFunc newFunc);	// Ptr to callback function
+
+//MN_EXPORT cnErrCode MN_DECL cpmGetOutputReg(
+//			multiaddr theMultiAddr,		// Node address
+//			plaOutReg *pGPOreg);		// Current setting
+//MN_EXPORT cnErrCode MN_DECL cpmGetOutputRiseReg(
+//			multiaddr theMultiAddr,		// Node address
+//			plaOutReg *pGPOreg);		// Current setting
+//MN_EXPORT cnErrCode MN_DECL cpmGetOutputFallReg(
+//			multiaddr theMultiAddr,		// Node address
+//			plaOutReg *pGPOreg);		// Current setting
+
+// Attention Generation Setup
+//MN_EXPORT cnErrCode MN_DECL cpmGetAttnMask(
+//			multiaddr theMultiAddr,		// Node address
+//			attnReg *pAttnMask);		// Current setting
+//MN_EXPORT cnErrCode MN_DECL cpmSetAttnMask(
+//			multiaddr theMultiAddr,		// Node address
+//			attnReg *pAttnMask);		// Current setting
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//								 MOTION API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+
+//-----------------
+// Velocity Group
+//-----------------
+// Low level command primitive
+MN_EXPORT cnErrCode MN_DECL cpmForkMoveVelEx(
+			multiaddr theMultiAddr,		// Node address
+			double velTargetStepPerSec,	// Velocity (steps/sec)
+			nodelong positionTarget,		// Target Position (optional)
+			mgVelStyle moveType);		// Motion style
+
+//MN_EXPORT cnErrCode MN_DECL cpmForkMoveVelQueued(
+//			multiaddr theMultiAddr,		// Node address
+//			double velTargetStepPerSec,	// Velocity (steps/sec)
+//			nodelong positionTarget,		// Target Position (optional)
+//			mgVelStyle moveType,		// Motion style
+//			nodelong *pBuffersRemaining);	// Ptr to move buf remaining cnt
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						  MONITOR PORT/DATA ACQUISITION API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Monitor port manipulations
+MN_EXPORT cnErrCode MN_DECL cpmGetMonitor(
+			multiaddr theMultiAddr,	// Target node addr
+			nodeushort channel,	// Target monitor port if supported
+			iscMonState *pState);
+
+MN_EXPORT cnErrCode MN_DECL cpmSetMonitor(
+			multiaddr theMultiAddr,	// Target node addr
+			nodeushort channel,	// Target monitor port if supported
+			iscMonState *pNewState);
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						     TUNING STIMULUS API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+MN_EXPORT cnErrCode MN_DECL cpmGetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pState);
+
+MN_EXPORT cnErrCode MN_DECL cpmSetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pNewState);
+
+// Reset the vector search flag
+MN_EXPORT cnErrCode MN_DECL cpmReVector(
+			multiaddr theMultiAddr);	// Target node addr
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						   NODE IDENTIFICATION API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Set/Get the user ID
+MN_EXPORT cnErrCode MN_DECL cpmSetUserID(
+			multiaddr theMultiAddr,
+			const char *pNewName);
+
+MN_EXPORT cnErrCode MN_DECL cpmGetUserID(
+			multiaddr theMultiAddr,
+			char *pUserIdStr,
+			Uint16 maxBufSize);
+
+// Set/Get Motor File Name
+MN_EXPORT cnErrCode MN_DECL cpmSetMotorFileName(
+			multiaddr theMultiAddr,
+			const char *pNewName);
+
+MN_EXPORT cnErrCode MN_DECL cpmGetMotorFileName(
+			multiaddr theMultiAddr,
+			char *pMotorFileNameStr,
+			Uint16 maxBufSize);
+
+// Set/Get User Description
+MN_EXPORT cnErrCode MN_DECL cpmSetUserDesc(
+			multiaddr theMultiAddr,
+			const char *pNewName);
+
+MN_EXPORT cnErrCode MN_DECL cpmGetUserDesc(
+			multiaddr theMultiAddr,
+			char *pMotorFileNameStr,
+			Uint16 maxBufSize);
+
+
+#ifdef __cplusplus
+}
+#endif
+/// @}
+
+#endif // __PUB_CPM_ADV_API_H_
+
+
+
+/*========================================================================== 
+	END OF FILE pubCpmAdvAPI.h
+  ==========================================================================*/
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmCls.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmCls.h
new file mode 100644
index 000000000..d6dd9f557
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmCls.h
@@ -0,0 +1,971 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubCpmCls.h $
+// $Revision: 50 $ $Date: 12/09/16 3:10p $
+// $Workfile: pubCpmCls.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	Concrete implementation of ClearPath-SC objects
+**/
+// CREATION DATE:	  
+//		2015-12-08 15:13:51
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __PUBCPMCLS_H__
+#define __PUBCPMCLS_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	pubCpmCls.h headers
+//
+#include "tekTypes.h"
+#include "pubSysCls.h"
+#include <vector>
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubCpmCls.h function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubCpmCls.h constants
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	CPMouts class
+//
+// 
+namespace sFnd
+{
+	// Forward declare for friends
+	class CPMnode;
+	class CPMnodeAdv;
+	class CPMinfo;
+	class CPMinfoAdv;
+	class CPMlimits;
+	class CPMmotion;
+	class CPMstatus;
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMstring class
+//
+// CREATION DATE:
+//      01/15/2016
+//
+//  DESCRIPTION:
+/**
+\brief Class to access and modify string items within a ClearPath-SC node.
+**/
+class MN_EXPORT CPMstring : public ValueString
+{
+friend class CPMnode;
+friend class CPMinfo;
+
+private:
+	void Refresh();
+	void Value(const char *newValue);
+	const char *Value();
+protected:
+	CPMstring(INode &theNode, nodeparam pNum, enum _srcs location);
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMattnNode class
+//
+// CREATION DATE:
+//      05/23/2016
+//
+//  DESCRIPTION:
+/**
+This class implements the ClearPath-SC attention feature.
+**/
+class MN_EXPORT CPMattnNode : public IAttnNode
+{
+friend class CPMnodeAdv;
+
+private:
+	bool AttnWait(size_t timeoutMs);
+	void AttnSignal();
+	void AttnRegister();
+	void AttnUnregister();
+	// Constructors
+protected:
+														/// \cond INTERNAL_DOC
+	CPMattnNode(INode &ourNode);
+														/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMlimitsAdv class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+This class implements the advanced ClearPath-SC limits feature.
+**/
+class MN_EXPORT CPMlimitsAdv : public ILimitsAdv
+{
+	friend class CPMlimits;
+	friend class CPMnode;
+private:
+	void StartPosFoldback(bool engage);
+	bool StartPosFoldback();
+
+	void StartNegFoldback(bool engage);
+	bool StartNegFoldback();
+
+	// Constructors
+protected:
+														/// \cond INTERNAL_DOC
+	CPMlimitsAdv(INode &ourNode);
+														/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMmotionAudit class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	\brief Motion audit feature access.
+
+	This class implements a ClearPath-SC advanced feature for collecting
+	data from moves.
+**/
+class MN_EXPORT CPMmotionAudit : public IMotionAudit
+{
+	friend class CPMnode;
+	friend class CPMnodeAdv;
+	friend class CPMinfoAdv;
+
+private:
+	void Refresh();
+	void SelectTestPoint(enum _testPoints testPoint,
+		double fullScale, double filterTCmsec);
+	// Constructors
+	/// \cond INTERNAL_DOC
+protected:
+	CPMmotionAudit(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+	
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMnodeAdv class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	\brief Advanced features access
+
+	This class implements a ClearPath-SC advanced features accessor.
+**/
+class MN_EXPORT CPMnodeAdv : public INodeAdv
+{
+	friend class CPMnode;
+protected:
+private:
+	CPMmotionAudit m_audit;
+	CPMattnNode m_attnNode;
+	/// \cond INTERNAL_DOC
+	void Supported(bool newState);
+	/// \endcond
+	// Constructors
+protected:
+	/// \cond INTERNAL_DOC
+	CPMnodeAdv(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMhoming class
+//
+// CREATION DATE:
+//      12/21/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements the homing feature of the ClearPath-SC.
+
+**/
+class MN_EXPORT CPMhoming : public IHoming
+{
+	friend class CPMmotion;
+private:
+	// Initiator
+	void Initiate();
+	// Test for execution
+	bool IsHoming();
+	// Test for homing complete
+	bool WasHomed();
+	// Signal homing complete
+	void SignalComplete();
+	// Signal home invalid
+	void SignalInvalid();
+	// Test homing settings
+	bool HomingValid();
+protected:
+	// Constructor
+	CPMhoming(INode &ourNode);
+};
+//																			  *
+//*****************************************************************************
+
+	
+	
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMinfoAdv class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	\brief Advanced information features access
+
+	This class implements a ClearPath-SC advanced information accessor.
+**/
+class MN_EXPORT CPMinfoAdv : public IInfoAdv
+{
+	friend class CPMinfo;
+protected:
+	// Constructors
+	/// \cond INTERNAL_DOC
+	CPMinfoAdv(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMinfoEx class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+\brief Expert information features access
+
+This class implements a ClearPath-SC advanced information accessor.
+**/
+class MN_EXPORT CPMinfoEx : public IInfoEx
+{
+	friend class CPMinfo;
+private:
+	// Parameter access
+	double Parameter(nodeparam index);
+	void Parameter(nodeparam index, double newValue);
+protected:
+	// Constructors
+	/// \cond INTERNAL_DOC
+	CPMinfoEx(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMinfo class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements the Info object for the INode virtual class.
+
+	This includes common information such as:
+	- Firmware version
+	- Node types
+	- Serial Number
+	- User ID
+
+	In addition to specific information, the configuration file can be
+	saved and loaded. This file is typically generated by the ClearView
+	setup application.
+**/
+class MN_EXPORT CPMinfo : public IInfo
+{
+	friend class CPMnode;
+protected:
+	nodeTypes m_nodeType;
+	void NodeType(nodeTypes);
+private:
+	// Access to node type
+	nodeTypes NodeType() { return m_nodeType; }
+	// User Data
+	void UserData(size_t bank, const uint8_t theData[MN_USER_NV_SIZE]);
+	std::vector<uint8_t> UserData(size_t bank);
+	// Construction
+	// Advanced info access
+	CPMinfoAdv m_advInfo;
+	// Expert info access
+	CPMinfoEx m_exInfo;
+	// Actual instances for string "parameters"
+	CPMstring m_userID;
+	CPMstring m_fwVersion;
+	CPMstring m_hwVersion;
+	CPMstring m_model;
+	/// \cond INTERNAL_DOC
+protected:
+	CPMinfo(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMlimits class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements a ClearPath-SC limits feature.
+**/
+class MN_EXPORT CPMlimits  : public ILimits
+{
+	friend class CPMnode;
+protected:
+	/**
+		\cond INTERNAL_DOC
+		ClearPath-SC implementation instance for advanced limits.
+	**/
+	CPMlimitsAdv m_adv;
+	/// \endcond
+private:
+
+public:
+
+	// Constructors
+	/// \cond INTERNAL_DOC
+protected:
+	CPMlimits(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMmotionAdv class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements the motion interface object for advanced optioned 
+	INode virtual class.
+
+	This interface can:
+	- query and setup kinematic limits for advanced motion 
+	- initiate advanced motion
+**/
+class MN_EXPORT CPMmotionAdv : public IMotionAdv
+{
+	friend class CPMmotion;
+public:
+	 
+	/**		
+		\copydoc IMotion::MovePosnHeadTailDurationMsec
+	**/
+	double MovePosnHeadTailDurationMsec(int32_t targetPosn,
+		bool targetIsAbsolute = false,
+		bool hasHead = true,
+		bool hasTail = true);
+	
+	/**		
+		\copydoc IMotion::MovePosnAsymDurationMsec
+	**/
+	double MovePosnAsymDurationMsec(int32_t targetPosn,
+		bool targetIsAbsolute = false);
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Motion Initiating Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	size_t MovePosnStart(int32_t target,
+						bool targetIsAbsolute,
+						bool isTriggered,
+						bool hasDwell);
+
+	size_t MovePosnHeadTailStart(int32_t target, 
+								bool targetIsAbsolute,
+								bool isTriggered,
+								bool hasHead, bool hasTail, 
+								bool hasDwell);
+	size_t MovePosnAsymStart(int32_t target, 
+						bool targetIsAbsolute,
+						bool isTriggered, bool hasDwell);
+	size_t MoveVelStart(double target,
+					   bool isTriggered);
+
+	// Triggering waiting moves
+	void TriggerMove();
+	void TriggerMovesInMyGroup();
+	void TriggerGroup(size_t groupNumber);
+	size_t TriggerGroup();
+
+	// Construction
+	/// \cond INTERNAL_DOC
+protected:
+	CPMmotionAdv(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMmotion class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements the motion interface object for the 
+	INode virtual class.
+
+	This interface can:
+	- query and setup kinematic limits for motion 
+	- initiate motion
+	- check for motion completion and status
+**/
+class MN_EXPORT CPMmotion : public IMotion
+{
+	friend class CPMnode;
+protected:
+	/**
+		\cond INTERNAL_DOC
+		ClearPath-SC implementation instance for advanced motion.
+	**/
+	CPMmotionAdv m_adv;
+	/**
+		ClearPath-SC implementation instance for homing.
+	**/
+	CPMhoming m_homing;
+	/// \endcond
+public:
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Kinematic Constraint Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**		
+		\copydoc IMotion::MovePosnDurationMsec
+	**/
+	double MovePosnDurationMsec(int32_t target, bool targetIsAbsolute);
+	/**		
+		\copydoc IMotion::MoveVelDurationMsec
+	**/
+	double MoveVelDurationMsec(double target);
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Motion Initiating Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	size_t MovePosnStart(int32_t target, 
+					     bool targetIsAbsolute,
+					     bool hasDwell);
+
+	size_t MoveVelStart(double target);
+	
+	/**
+		\copydoc IMotion::MoveWentDone
+	**/
+	virtual bool MoveWentDone();
+
+	/**
+		\copydoc IMotion::MoveIsDone
+	**/
+	virtual bool MoveIsDone();
+
+	/**
+		\copydoc IMotion::VelocityReachedTarget
+	**/
+	virtual bool VelocityReachedTarget();
+
+	/**
+		\copydoc IMotion::VelocityAtTarget
+	**/
+	virtual bool VelocityAtTarget();
+
+	/**
+		\copydoc IMotion::WentNotReady
+	**/
+	virtual bool WentNotReady();
+
+	/**
+		\copydoc IMotion::IsReady
+	**/
+	virtual bool IsReady();
+
+	void AddToPosition(double adjAmount);
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Motion Canceling Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	void NodeStop(nodeStopCodes howToStop);
+	void NodeStop(mgNodeStopReg &howToStop);
+	void GroupNodeStop(nodeStopCodes howToStop);
+	void NodeStopClear();
+	// Construction
+	/// \cond INTERNAL_DOC
+protected:
+	CPMmotion(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMouts class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements access to the outputs object.
+
+	This allow access to features controlled via the output register.
+**/
+class MN_EXPORT CPMouts : public IOuts
+{
+	friend class CPMnode;
+private:
+public:
+	// Easy access to enable request
+	void EnableReq(bool newState);
+	bool EnableReq();
+	// Constructor
+	/// \cond INTERNAL_DOC
+protected:
+	CPMouts(INode &ourNode);
+	~CPMouts();
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMsetup class
+//
+// CREATION DATE:
+//      12/21/2015
+//
+//  DESCRIPTION:
+/**
+This class implements access to the setup information and methods for
+a ClearPath-SC node.
+**/
+class MN_EXPORT CPMsetup : public ISetup
+{
+	friend class CPMnode;
+protected:
+	void ConfigLoad(const char *filePath, bool doReset = false);
+	void ConfigSave(const char *filePath);
+	bool AccessLevelIsFull();
+public:
+	// Construction
+	/// \cond INTERNAL_DOC
+protected:
+	CPMsetup(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMstatusAdv class
+//
+// CREATION DATE:
+//      12/21/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements access to the advanced status information for 
+	a ClearPath-SC node.
+**/
+class MN_EXPORT CPMstatusAdv  : public IStatusAdv
+{
+	friend class CPMstatus;
+protected:
+public:
+	// Construction
+	/// \cond INTERNAL_DOC
+protected:
+	CPMstatusAdv(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+	
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMstatus class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements access to status information for a ClearPath-SC
+	node.
+**/
+class MN_EXPORT CPMstatus  : public IStatus
+{
+	friend class CPMnode;
+protected:
+	/**
+		\cond INTERNAL_DOC
+		ClearPath-SC implementation instance for advanced motion.
+	**/
+	CPMstatusAdv m_adv;
+	/// \endcond
+public:
+	void AlertsClear();
+	bool IsReady() { return Node().Motion.IsReady(); }
+	bool HadTorqueSaturation();
+public:
+	// Construction
+	/// \cond INTERNAL_DOC
+protected:
+	CPMstatus(INode &ourNode);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMnodeEx class
+//
+// CREATION DATE:
+//      01/18/2016
+//
+//  DESCRIPTION:
+/**
+This class implements a ClearPath-SC node expert feature accessors.
+**/
+class MN_EXPORT CPMnodeEx : public INodeEx
+{
+	friend class CPMnode;
+protected:
+private:
+	void MutexTake();
+	void MutexRelease();
+	/// \cond INTERNAL_DOC	
+protected:
+	CPMnodeEx(INode &node);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      CPMnode class
+//
+// CREATION DATE:
+//      12/16/2015
+//
+//  DESCRIPTION:
+/**
+	This class implements a ClearPath-SC node accessors.
+**/
+class CPMnode : public INode
+{
+	friend class CPMmotion;
+	friend class CPMmotionAdv;
+private:
+	// Common node info access
+	CPMinfo m_info;
+	CPMmotion m_motion;
+    CPMstatus m_status;
+	CPMlimits m_limits;
+	CPMouts m_outs;
+	CPMsetup m_setup;
+	// Advanced features
+	CPMnodeAdv m_adv;
+	CPMnodeEx m_ex;
+	// Units interface
+	void VelUnit(enum _velUnits newUnits);
+	void TrqUnit(enum _trqUnits newUnits);
+	void AccUnit(enum _accUnits newUnits);
+
+	// Scaling 'constants'
+	double m_accScaleToUser;
+	// Scale factor to use for amps based on I_MAX
+	double m_trqScaleToUser;
+	// Scale factor to use for amps based on ADC_MAX
+	double m_adcTrqScaleToUser;
+	// Scale factor to use for amps to shutdown amps
+	double m_rmsTrqScaleToUser;
+	double m_velScaleToUser;
+protected:
+	double velScale() { return m_velScaleToUser;  }
+	// Handy lists of various values to allow quick unit changes.
+	std::vector<ValueDouble *> m_accValues;
+	std::vector<ValueDouble *> m_velValues;
+	std::vector<ValueDouble *> m_trqValues;
+	std::vector<ValueDouble *> m_adcTrqValues;
+	std::vector<ValueDouble *> m_rmsTrqValues;
+
+/// \cond INTERNAL_DOC	
+public:
+	CPMnode(IPort &port, multiaddr theAddr);
+	~CPMnode() {};
+	void Refresh();
+/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																	      *
+// 	SysCPMbrakeControl class 
+/**
+	\brief ClearPath COM Hub brake control feature implementation.
+
+	This is the brake control feature that either is driven by the enabled
+	state of the associated node or manually controlled by the user.
+**/
+class SysCPMbrakeControl : public IBrakeControl
+{
+	friend class SysCPMport;
+private:
+	void BrakeSetting(size_t brakeNum, BrakeControls brakeMode);
+	BrakeControls BrakeSetting(size_t brakeNum);
+	bool BrakeEngaged(size_t brakeNum);
+
+	/// \cond INTERNAL_DOC
+	/// Construct our ClearPath COM Hub brake implementation
+protected:
+	SysCPMbrakeControl(IPort &ourPort);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																	      *
+// 	SysCPMgrpShutdown class 
+/**
+	\brief ClearPath-SC Group Shutdown feature.
+
+	This is group shutdown feature for ClearPath-SC nodes.
+**/
+class SysCPMgrpShutdown : public IGrpShutdown
+{
+	friend class IGrpShutdown;
+	friend class SysCPMport;
+private:
+	void ShutdownWhen(size_t nodeIndex, const ShutdownInfo &theInfo);
+	void ShutdownWhenGet(size_t nodeIndex, ShutdownInfo &theInfo);
+	void ShutdownInitiate();
+	bool GetGlobalStop();
+	/// \cond INTERNAL_DOC
+	/// Construct our ClearPath COM Hub brake implementation
+protected:
+	SysCPMgrpShutdown(IPort &ourPort);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																	      *
+// 	SysCPMattnPort class 
+/**
+\brief ClearPath-SC Group Shutdown feature.
+
+This is group shutdown feature for ClearPath-SC nodes.
+**/
+class SysCPMattnPort : public IAttnPort
+{
+	friend class IPort;
+	friend class SysCPMportAdv;
+private:
+	void Enable(bool newState);
+	bool Enabled();
+	
+	IAttnPort::attnState WaitForAttn(mnAttnReqReg &attn);
+
+	/// \cond INTERNAL_DOC
+	/// Construct our ClearPath COM Hub brake implementation
+protected: 
+	SysCPMattnPort(IPort &ourPort);
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	SysCPMportAdv class
+/**
+\brief ClearPath COM Hub port implementation for advanced features.
+
+This is the IPortAdv implementation for the serial port attached to the
+ClearPath Communications hub.
+
+\note This is not exported to prevent end-user from creating
+instances in DLL.
+**/
+class SysCPMportAdv : public IPortAdv
+{
+	friend class IPort;
+	friend class SysCPMport;
+
+private:
+	SysCPMattnPort m_attnPort;
+	void TriggerMovesInGroup(size_t groupNumber);
+protected:
+	SysCPMportAdv(IPort &ourPort);
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	SysCPMport class 
+/**
+	\brief ClearPath COM Hub port implementation.
+
+	This is the IPort implementation for the serial port attached to the
+	ClearPath Communications hub.
+
+	\note This is not exported to prevent end-user from creating
+	instances in DLL.
+**/
+class SysCPMport : public IPort
+{
+private:
+	SysCPMbrakeControl m_brakeControl;
+	SysCPMgrpShutdown m_groupShutdown;
+	SysCPMportAdv m_advPort;
+	/**
+		\copydoc IPort::NodeCount
+	**/
+	Uint16 NodeCount();
+	/**
+		\copydoc IPort::OpenState
+	**/
+	openStates OpenState();
+	/**
+		\copydoc IPort::WaitForOnline
+	**/
+	bool WaitForOnline(int32_t timeoutMs = 15000);
+	/**
+		\copydoc IPort::RestartCold
+	**/
+	void RestartCold();
+	/**
+		\copydoc IPort::NodeStop
+	**/
+	void NodeStop(mgNodeStopReg stopType);
+	/**
+	\copydoc IPort::GetGlobalStop
+	**/
+	bool GetGlobalStop();
+	/**
+		\copydoc IPort::CommandTraceSave
+	**/
+	void CommandTraceSave(const char *filePath);
+	/// \cond INTERNAL_DOC
+	// Construction
+public: 
+	SysCPMport(netaddr index);
+	~SysCPMport();
+	/// \endcond
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+}  // namespace sFnd
+//*****************************************************************************
+
+#endif
+
+
+//============================================================================= 
+//	END OF FILE pubCpmCls.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmRegs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmRegs.h
new file mode 100644
index 000000000..958fa53ec
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubCpmRegs.h
@@ -0,0 +1,2346 @@
+//*****************************************************************************
+// DESCRIPTION:
+/**
+	\file
+	\brief S-Foundation register definitions for programming ClearPath-SC nodes.
+
+	This header defines the node specific registers of the ClearPath-SC node.
+	These include:
+	- Status Register
+	- Application Configuration
+	- Hardware Configurations
+	- Alert Register fields
+	- Output Register fields
+**/
+// PRINCIPLE AUTHORS:
+//		DWS
+//
+// CREATION DATE:
+//		2015-12-23 16:26:15
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __PUBCPM_REGS_H__
+#define __PUBCPM_REGS_H__
+
+//*****************************************************************************
+// NAME																          *
+// 	pubCPM_API.h headers
+//
+	#include "tekTypes.h"
+	#include "pubMotion.h"
+	#include "pubRegFldCommon.h"
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME                                                                       *
+//  pubCpmRegs.h constants
+//
+													/** \cond INTERNAL_DOC **/
+#define ALERTREG_SIZEOCTETS		12
+#define SC_USER_DESCR_SPAN		5		// Number parameters in
+#define SC_USER_DESCR_CHUNK 	25		// # chars per parameter
+// Max description size
+#define SC_USER_DESCR_SZ 		(CP_USER_DESCR_SPAN*CP_USER_DESCR_CHUNK)
+													/** \endcond **/
+
+													/** \cond INTERNAL_DOC **/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+    ClearPath-SC Parameter Numbers.
+    \public
+    This enumeration defines the set of ClearPath-SC registers accessible using 
+	the sFoundation #sFnd::IInfoEx class.
+**/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef enum _cpmParams {
+// Bank 0 - Core Parameters
+    CPM_P_NODEID,                        // 0  00 Device ID
+    CPM_P_FW_VERS,                       // 1  01 FW version
+    CPM_P_HW_VERS,                       // 2  02 HW version
+    CPM_P_RESELLER_ID,                   // 3  03 Reseller ID
+    CPM_P_SER_NUM,                       // 4  04 Unit serial number
+    CPM_P_OPTION_REG,                    // 5  05 Unit options
+    CPM_P_ROM_SUM_ACK,                   // 6  06 Firmware update ack
+    CPM_P_ROM_SUM,                       // 7  07 Firmware checksum
+    CPM_P_SAMPLE_PERIOD,                 // 8  08 Sample period (nsec)
+    CPM_P_ALERT_REG,                     // 9  09 Shutdown register
+    CPM_P_STOP_TYPE,                     // 10 0a Node Stop Type
+    CPM_P_WATCHDOG_TIME,                 // 11 0b Watchdog time constant
+
+	CPM_P_STATUS_ACCUM_REG=13,           // 13 0d Status accum register
+    CPM_P_STATUS_RISE_REG,               // 14 0e Status rise register
+    CPM_P_STATUS_RT_REG=16,              // 16 10 Status reg (realtime)
+    CPM_P_TIMESTAMP,                     // 17 11 8-bit timestamp
+    CPM_P_TIMESTAMP16,                   // 18 12 16-bit timestamp
+    CPM_P_PART_NUM,                      // 19 13 Part Number String
+    CPM_P_EE_UPD_ACK,                    // 20 14 EE Update Acknowlegde
+    CPM_P_EE_VER,                        // 21 15 EE Version Number
+    CPM_P_STATUS_FALL_REG,               // 22 16 Status fall register
+    CPM_P_HW_CONFIG_REG,                 // 23 17 Hardware config/setup reg
+    CPM_P_APP_CONFIG_REG,                // 24 18 Feature config/setup reg
+    CPM_P_WARN_REG,                      // 25 19 Warnings pending
+    CPM_P_WARN_RT_REG,                   // 26 1a Warnings (realtime)
+    CPM_P_WARN_MASK,                     // 27 1b Warnings for attention
+    CPM_P_ALERT_MASK,                    // 28 1c Alert selection
+    CPM_P_ON_TIME,                       // 29 1d Unit On Time
+	CPM_P_POSN_CAP_INA_HI_SPD,			 // 30 1e Captured position (Input A, high-speed capture)
+    CPM_P_USER_RAM0,                     // 31 1f User RAM parameter
+    CPM_P_USER_DATA_NV0,                 // 32 20 User NV (13-bytes)
+    CPM_P_USER_DATA_NV1,                 // 33 21 User NV (13-bytes)
+    CPM_P_USER_DATA_NV2,                 // 34 22 User NV (13-bytes)
+    CPM_P_USER_DATA_NV3,                 // 35 23 User NV (13-bytes)
+    CPM_P_NETERR_APP_CHKSUM,             // 36 24 Application Net Checksum counter
+    CPM_P_NETERR_APP_FRAG,               // 37 25 Application Net Fragment counter
+    CPM_P_NETERR_APP_STRAY,              // 38 26 Application Net Stray data counter
+    CPM_P_NETERR_APP_OVERRUN,            // 39 27 Application Net Overrun counter
+    CPM_P_NETERR_DIAG_CHKSUM,            // 40 28 Diagnostic Net Checksum counter
+    CPM_P_NETERR_DIAG_FRAG,              // 41 29 Diagnostic Net Fragment counter
+    CPM_P_NETERR_DIAG_STRAY,             // 42 2a Diagnostic Net Stray data counter
+    CPM_P_NETERR_DIAG_OVERRUN,           // 43 2b Diagnostic Net Overrun counter
+
+	CPM_P_ATTN_MASK=45,					 // 45 2d Attention mask register
+	CPM_P_GP_TIMER,						 // 46 2e General-purpose timer period
+	CPM_P_AT_POSN_LOC,					 // 47 2f At Position location
+	CPM_P_A_START,						 // 48 30 A after start location
+	CPM_P_B_END,						 // 49 31 B before end location
+	CPM_P_USER_OUT_REG,					 // 50 32 User output settings
+
+	CPM_P_OUT_REG = 52,					 // 52 34 Output register
+    CPM_P_DRV_MTR_SPEED_LIM,             // 53 35 Motor Speed Limit (quads/msec)
+
+	CPM_P_ATTN_DRVR_MASK=55,			 // 55 37 Driver's attention register
+	CPM_P_STATUS_EVENT_MASK,			 // 56 38 Status Event Mask
+// Motion Constraint Group
+	CPM_P_APP_RAS_DELAY,				 // 57 39 Stopping delay caused by RAS
+    CPM_P_RAS_MAX_VELOCITY=60,	 		 // 60 3c Maximum velocity for current RAS
+    CPM_P_VEL_LIM,                       // 61 3d Trapezoidal velocity limit
+    CPM_P_ACC_LIM,                       // 62 3e Trapezoidal acceleration limit
+    CPM_P_JERK_LIM,                      // 63 3f Jerk limit
+    CPM_P_DEC_LIM,                       // 64 40 Deceleration Limit
+    CPM_P_STOP_ACC_LIM,                  // 65 41 Stop acceleration limit
+	CPM_P_HEAD_DISTANCE, 				 // 66 42 Head distance
+	CPM_P_TAIL_DISTANCE,				 // 67 43 Tail distance
+	CPM_P_HEADTAIL_VEL,					 // 68 44 Head/Tail velocity
+	CPM_P_MOVE_DWELL,                    // 69 45 Post-move dwell time (sec)
+
+	CPM_P_DRV_STOP_QUALIFY_TC=72,		 // 72 48 Stopped qualification time (ms)
+
+	CPM_P_DRV_STOP_QUALIFY_VEL=74,		 // 74 4a Stopped qualify velocity
+// Motion Status Group
+    CPM_P_DRV_TRQ_CMD=80,                // 80 50 Commanded torque
+    CPM_P_DRV_TRQ_MEAS,                  // 81 51 Measured torque 
+    CPM_P_DRV_RMS_LVL,                   // 82 52 RMS level
+    CPM_P_POSN_MEAS,                     // 83 53 Measured position
+    CPM_P_POSN_CMD,                      // 84 54 Commanded position
+    CPM_P_VEL_MEAS,                      // 85 55 Measured velocity
+    CPM_P_VEL_CMD,                       // 86 56 Commanded velocity
+
+    CPM_P_DRV_RMS_SLOW_LVL=88,           // 88 58 RMS level (slow acting)
+
+    CPM_P_POSN_TRK=90,                   // 90 5a Position tracking error
+    CPM_P_POSN_TRK_RANGE,                // 91 5b Tracking in-range window
+    CPM_P_DRV_MV_DN_TC,                  // 92 5c Move Done: Time Constant (ms)
+
+	CPM_P_VEL_TRK_RANGE = 97,			 // 97 61 Vel tracking pct (1.15)
+
+    CPM_P_INA_TC = 99,					 // 99 Input A filter (ms)
+	CPM_P_INB_TC = 102,	                 // 102 Input B filter (ms)
+    
+    // BANK 1 items (Drive/Motor Configuration)
+// Factory Settings
+    CPM_P_DRV_ADC_MAX=256,               // 256 0  ADC full scale (A)
+    CPM_P_DRV_I_MAX,                     // 257 1  Current Full Scale (A)
+    CPM_P_DRV_RMS_MAX,                   // 258 2  Factory RMS limit
+    CPM_P_DRV_FACT_IR_CAL,               // 259 3  Ir Sensor Calibration
+    CPM_P_DRV_FACT_IS_CAL,               // 260 4  Is Sensor Calibration
+    CPM_P_DRV_FACT_KM_FACTOR,            // 261 5  Km Factor
+    CPM_P_DRV_FACT_MTR_MIN_RES,          // 262 6  Mtr Min Res
+    CPM_P_DRV_FACT_IB_TC,                // 263 7  IB time constant
+    CPM_P_DRV_FACT_IB_TRIP,              // 264 8  IB Trip Point (A)
+    CPM_P_DRV_FACT_PHASE_TRIP,           // 265 9  Phase Trip Point (A)
+    CPM_P_DRV_FACT_FS_BUSV,              // 266 A Full scale bus volts
+    CPM_P_FACT_OVER_V_TRIP=268,			 // 268 0c Over-voltage shutdown point
+    CPM_P_FACT_VBUS_CAL,				 // 269 0d Bus voltage calibration factor
+// Safety Items
+    CPM_P_DRV_RMS_LIM,					 // 270 0e RMS shutdown limit (A)
+    CPM_P_DRV_RMS_TC,                    // 271 0f RMS time constant (sec) @ 100% trq
+    CPM_P_POSN_TRK_ERR_LIM,              // 272 10 Position tracking rrror limit
+	CPM_P_DRV_RMS_INIT,					 // 273 11 RMS initial value on reset (%)
+	CPM_P_DRV_IB_PEAK,					 // 274 12 IB Level Peak
+    CPM_P_DRV_RMS_SLOW_LIM,				 // 275 13 RMS shutdown limit (A) (Slow acting)
+	CPM_P_TP_PHASE_BD = 276,			 // 276 14 Phase board test point
+
+	CPM_P_POSN_CAP_INB=277,				 // 277 15 Captured position (Input B)
+// Drive State Items   
+    CPM_P_DRV_BUS_VOLTS=280,             // 280 18 Real-time Bus Voltage (V)
+    CPM_P_DRV_CONFIG_CHANGED,            // 281 19 Configuration changed
+    CPM_P_DRIVE_TEMP=291,              	 // 291 23 Drive temperature (deg C)
+    CPM_P_DRV_IB_LVL=294,                // 294 26 IB Level
+
+	CPM_P_OVER_TEMP_TRIP=308,			 // 308 34 Over-Temp Trip Point
+// Motor Parameters                     
+    CPM_P_DRV_KIP_ADJ,		             // 309 35 Vector Torque: Kip Adjust
+    CPM_P_DRV_KIP=318,                   // 318 3e Vector Torque: Kip
+    CPM_P_DRV_KII,                       // 319 3f Vector Torque: Kii
+    CPM_P_DRV_STEP_DENS,                 // 320 40 Step+Dir Resolution (counts/rev)
+
+	CPM_P_CMD_CNTS_PER_REV=322,			 // 322 42 Command encoder density (counts/rev)
+    CPM_P_DRV_KR,                        // 323 43 Compensator: Kr
+    CPM_P_DRV_KII_ADJ,                   // 324 44 Vector Torque: Kii Adjust
+// Tuning parameters                    
+    CPM_P_DRV_TUNE_CONFIG_REG,		     // 325 45 Tuning Configuration Register
+    CPM_P_DRV_KV,                        // 326 46 Compensator: Kv
+    CPM_P_DRV_KP,                        // 327 47 Compensator: Kp
+    CPM_P_DRV_KI,                        // 328 48 Compensator: Ki
+    CPM_P_DRV_KFV,                       // 329 49 Compensator: Kfv
+    CPM_P_DRV_KFA,                       // 330 4a Compensator: Kfa
+    CPM_P_DRV_KFJ,                       // 331 4b Compensator: Kfj (jerk ff)
+
+    CPM_P_DRV_KNV=333,                   // 333 4d Compensator: Knv
+	CPM_P_DRV_AH_FILT_TC,				 // 334 4e Anti-hunt filter time constant
+    CPM_P_DRV_TRQ_BIAS,		             // 335 4f Compensator: Torque Bias (A)
+    CPM_P_DRV_FUZZY_APERTURE,            // 336 50 Fuzzy Aperture
+    CPM_P_DRV_FUZZY_HYST,                // 337 51 Fuzzy Hystersis
+    CPM_P_AH_HOLDOFF,                    // 338 52 Anti-hunt holdoff
+    CPM_P_DRV_KZERO,                     // 339 53 Compensator: Kzero
+    CPM_P_DRV_IZERO,                     // 340 54 Compensator: Izero
+    CPM_P_DRV_TARGET_WIN,                // 341 55 Compensator: Target Window
+    CPM_P_DRV_STAB_WIN,                  // 342 56 Compensator: Stability Window
+
+	CPM_P_DRV_KP_FACTOR=346,			 // 346 5a KpOut Factor
+	CPM_P_DRV_KPZ_FACTOR,				 // 347 5b KpZero Factor
+	CPM_P_DRV_KI_FACTOR,				 // 348 5c Ki Factor
+	CPM_P_DRV_FINE_TUNE,				 // 349 5d Fine Tuning
+// Foldback Settings                    
+    CPM_P_DRV_TRQ_LIM ,					 // 350 5e Torque Limit  (A)
+    CPM_P_DRV_POS_FLDBK_TRQ,             // 351 5f + Torque foldback limit (A)
+    CPM_P_DRV_POS_FLDBK_TRQ_TC,          // 352 60 + Torque foldback time const (ms)
+    CPM_P_DRV_NEG_FLDBK_TRQ,             // 353 61 - Torque foldback limit (A)
+    CPM_P_DRV_NEG_FLDBK_TRQ_TC,          // 354 62 - Torque foldback time const (ms)
+
+    CPM_P_DRV_HARDSTOP_FLDBK_TRQ=357,    // 357 65 Hardstop foldback limit (A)
+    CPM_P_DRV_HARDSTOP_FLDBK_TRQ_TC,     // 358 66 Hardstop foldback time const (ms)
+    CPM_P_DRV_HARDSTOP_ENTRY_SPD,        // 359 67 Hard-stop speed qualifier
+    CPM_P_DRV_HARDSTOP_ENTRY_TRQ,        // 360 68 Foldback Torque Trip Level (A)
+    CPM_P_DRV_HARDSTOP_ENTRY_TC,         // 361 69 Hard Stop: entry delay (ms)
+
+	CPM_P_DRV_HARDSTOP_TRQ_LIM=363,		 // 363 6b Alt Trq Lim for Hardstop homing (A)
+    CPM_P_DRV_RMS_SLOW_TC,               // 364 6c RMS time constant (sec) @ 100% trq (slow acting)
+		
+	CPM_P_DLY_TO_DISABLE=368,			 // 368 70 Delay to Disable for brakes (ms)
+	CPM_P_FACT_SOFT_START_FREQ,			 // 369 71 Soft start PWM carrier frequency (Hz)
+// VRS settings
+	CPM_P_DRV_VRS_TRQ_FILT=370,			 // 370 72 VRS Filtering (ms)
+	CPM_P_DRV_VRS_FULL_ON=371,			 // 371 73 VRS High Limit (V)
+	CPM_P_DRV_VRS_FULL_OFF=362,			 // 362 6a VRS Low Limit (V)
+	CPM_P_DRV_BUSV_ADJ_RATE=372,		 // 372 74 VBus runtime adjust rate (ms)
+
+// Drive Set Flags Register
+	CPM_P_DRV_SET_FLAGS=375,			 // 375 77 Drive SetFlags Register
+	CPM_P_FACT_UNDER_TEMP_TRIP=379,		 //	379 7b Under-Temp Trip (deg C 10.6)
+	CPM_P_DRV_ENCODER_TEMP,     		 // 380 7c Internal temp of encoder (deg C 10.6)
+	CPM_P_DRV_STATOR_TEMP,				 // 381 7d Internal temp of stator (deg C 10.6)
+	CPM_P_FACT_OVER_TEMP_TRIP_STATOR,	 // 382 7e Over-Temp Trip Stator (deg. C)
+	CPM_P_FACT_OVER_TEMP_WARN_STATOR,	 // 383 7f Over-Temp Warn Stator (deg. C)
+
+// Bank 2 Items - Application Specific Settings
+	// Homing Settings
+    CPM_P_APP_HOMING_VEL=512,    		 // 512 00 Homing Velocity
+    CPM_P_APP_HOMING_OFFSET,             // 513 01 Initial offset index after homing
+    CPM_P_APP_HOMING_ACCEL,				 // 514 02 Homing acceleration
+    CPM_P_APP_HOMING_DELAY=516,          // 516 04 Homing delay after hardstop
+	CPM_P_EVENT_SHUTDOWN_MASK,           // 517 05 Power event shutdown/warning selector (0=warning, 1=shutdown)
+
+	CPM_P_PWR_AC_LOSS_TC,				 // 518 06 AC Loss shutdown/warning time constant
+	CPM_P_PWR_AC_WIRING_ERROR_TC,		 // 519 07 AC Wiring Error shutdown/warning time constant
+
+	CPM_P_FACT_LPB_RESTORE_V = 520,		 // 520 08 Bus V restoration voltage
+	CPM_P_PWRUP_HOLDOFF_TIME = 521,		 // 521 09 Sensorless startup holdoff after powerup
+	CPM_P_FACT_LPB_ENTRY_V = 522,		 // 522 0a Bus V minimum operation voltage
+
+	CPM_P_XPS_OUT_SRC_REG = 545,		 // 545 21 XPS output register MUX
+	CPM_P_XPS_IN_SRC_REG,				 // 546 22 XPS input register MUX
+
+	CPM_P_XPS_USER_IN_REG=548,			 // 548 24 User driven input register
+	CPM_P_XPS_STATUS_IN_REG,			 // 549 25 Drive controlled input register
+	CPM_P_XPS_INVERT_INPUT,				 // 550 26 XPS bits driving pos limit feature
+	CPM_P_XPS_INVERT_OUTPUT,			 // 551 27 XPS bits driving pos limit feature
+	CPM_P_XPS_FEAT_ENABLE=554,			 // 554 2a XPS bits driving enable feature
+	CPM_P_XPS_FEAT_TRIGGER=556,			 // 556 2c XPS bits driving trigger feature
+	CPM_P_XPS_FEAT_NODE_STOP,			 // 557 2d XPS bits driving node stop feature
+	CPM_P_XPS_FEAT_RESET_TIMER,			 // 558 2e XPS bits driving timer reset feature
+	CPM_P_XPS_FEAT_ATTN0,				 // 559 2f XPS bits driving attn 0 feature
+	CPM_P_XPS_FEAT_ATTN1,				 // 560 30 XPS bits driving attn 1 feature
+	CPM_P_XPS_FEAT_AT_HOME=563,			 // 563 33 XPS bits driving homing feature
+	CPM_P_XPS_FEAT_POS_TRQ_FLDBK,		 // 564 34 XPS bits driving pos torque limit feature
+	CPM_P_XPS_FEAT_NEG_TRQ_FLDBK,		 // 565 35 XPS bits driving neg torque limit feature
+	CPM_P_XPS_FEAT_IN_POS_LIM,			 // 566 36 XPS bits driving pos limit feature
+	CPM_P_XPS_FEAT_IN_NEG_LIM,			 // 567 37 XPS bits driving neg limit feature
+
+	CPM_P_USER_SOFT_LIM_POSN_1 = 568,	 // 568 38 User defined software limit 1
+	CPM_P_USER_SOFT_LIM_POSN_2,			 // 569 39 User defined software limit 2
+	CPM_P_POWER_REG = 572,				 // 572 3c Power Status Register
+	CPM_P_FACT_PHASE_BD_SN = 574,		 // 574 3e Phase board serial num
+	CPM_P_FACT_PHASE_BD_REV,			 // 575 3f Phase board rev
+	CPM_P_DRV_MIN_OPER_VOLTS = 578,		 // 578 42 Minimum operating voltage
+	CPM_P_OVER_TEMP_TRIP_USER,			 // 579 43 User Over-Temp Trip
+	CPM_P_DRV_IB_TRIP_USER,				 // 580 44 User IB Trip
+} cpmParams;
+													/** \endcond **/
+
+//*****************************************************************************
+// Insure structs are byte packed on target
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+//*****************************************************************************
+
+
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	cpmHwConfigReg union and cpmHwConfigFlds
+												/** \cond ExpertDoc **/
+/**
+	\brief ClearPath-SC Hardware Configuration Field Definitions.
+
+	These field control the interactions of the node with the electrical
+	or other hardware based interfaces. 
+	
+	These include:
+	- homing setup
+	- A after start source
+	- B before end source
+	- various input polarity settings
+**/
+struct _cpmHwConfigFlds {
+	/// Homing styles for the HomingStyle field.
+	enum _homingStyles {
+		HOME_TO_SWITCH = 0,			///<  0 Homing to switch input
+		HOME_TO_HARDSTOP = 1		///<  1 Homing to a hardstop
+	};
+	/// Homing styles for the HomingStyle field.
+	typedef enum _homingStyles homingStyles;
+													/**  INTERNAL_DOC **/
+	BFld: 4;									//	0-3 
+													/**  **/
+	/**
+		\brief <i>A After Start</i> reference.
+		
+		Use measured position in determining A After Start, else use
+		commanded.
+	**/
+	BFld AAfterStartMeas : 1;					// 4
+	/**
+		\brief <i>B Before End</i> reference.
+
+		Use measured position in determining B Before End, else use
+		commanded.
+	**/
+	BFld BBeforeEndMeas : 1;					// 5
+	/**
+		\brief <i>At position</i> reference.
+		 
+		Use measured position in determining At Position, else use
+		commanded.
+	**/
+	BFld AtPositionMeas : 1;					// 6
+	/**
+		\brief Vector Regen Shunt Enable.
+
+		If set, allow excess bus voltage to be dissipated in the windings.
+	**/
+	BFld VRSEnable : 1;							// 7
+	/**
+		\brief Vector Validation.
+
+		If set, compare the sensorless start vector with the RO value.
+		If outside the acceptable range, cause a shutdown.
+	**/
+	BFld VectorValidation : 1;					// 8
+													/**  INTERNAL_DOC **/
+	BFld 	: 1;    							// 9
+													/**  **/
+													/** \endcond  **/
+	/**
+		\brief High-Speed Position Capture control
+
+		When should the position be captured by the high-speed input switch?
+		0 means to capture position when Input A turns off, 1 means to 
+		capture position when Input A turns on.
+	**/
+	BFld CapturePolarityHiSpd : 1;				// 10
+	/**
+		\brief Position Capture control.
+
+		When should the position be captured by the input switch?
+		0 means to capture position when Input B turns off, 1 means to 
+		capture position when Input B turns on.
+	**/
+	BFld CapturePolarity : 1;					// 11
+													/**  INTERNAL_DOC **/
+	/**
+		\brief Data acquisition over-sampling (for internal use).
+
+		Determines the rate that data acquisition points are sent
+		0 = every other sample
+		1 = every sample
+	**/
+	BFld DataAcqOversampling : 1;				// 12
+													/**  **/
+	/**
+		\brief Sensorless Start Mode
+
+		Determines when the initial vector is established.
+		0 = At Power-On
+		1 = At First Enable
+
+		First enable is the recommended method if multiple nodes share
+		a power supply. This minimizes a power supply overload condition
+		when a system is first powered up.
+
+		\note The power-on-delay parameter may be used to stagger the vector 
+		initialize for power-on mode.
+	**/
+	BFld SensorlessOnEnable : 1;				// 13
+	/**
+		\brief Homing style
+
+		What type of homing mode is being used? 0 is homing
+		to a switch input, 1 is homing to a hardstop
+	**/
+	BFld HomingStyle : 1;						// 14
+
+	/*!
+		\brief <i>Step & Direction Command Input Format</i>
+
+		If asserted, the input format will use the quadrature format. If
+		not asserted, the input format is step & direction.
+
+		\note This feature was introduced with firmware version 1.6
+
+		\note Used by ClearView
+	**/
+	BFld StepDirAsQuadrature: 1;				// 15
+
+    /**
+     * \brief Expected Power Source
+     *
+     *  On AC capable motors, this field sets the expected power connection.
+     *
+     *  Set to 0 for all DC powered motors and 1 for AC Powered.
+     *
+	 *	\note This feature was introduced with firmware version 1.6
+	 *
+	 *	\note Used by ClearView
+     **/
+    unsigned UsingAC : 1;						// 16 0=DC, 1=AC
+    /**
+     * \brief Expected AC Power Type
+     *
+     *  On AC capable motors, this field sets the expected AC power source.
+     *
+     *  Set to 0 for all 3phase powered motors and 1 for single phase.
+     *
+	 *	\note This feature was introduced with firmware version 1.6.10
+	 *
+	 *	\note Used by ClearView
+     **/
+    unsigned Using1PhAC : 1;					// 17 0=3ph, 1=1ph
+													/**  INTERNAL_DOC **/
+	BFld: 2;									// 18-19
+													/**  **/
+	/**
+		\brief Sensorless start algorithm(s) to use
+
+		When SensorlessMode is not set, this value determines the sensorless 
+		start method.
+	**/
+	BFld ValidStartMethods		 : 4;			// 20-23
+
+	BFld: 6;									// 24-29
+
+	unsigned UsingBlower : 1;					// 30
+};
+/// ClearPath-SC Hardware Configuration Field Definitions.
+typedef struct _cpmHwConfigFlds cpmHwConfigFlds;
+/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmHwConfigReg union
+//
+// DESCRIPTION
+															/** \cond ExpertDoc **/
+/**
+    \brief ClearPath-SC Hardware Configuration Register Type
+
+	This container type holds a copy of the <i>Hardware Configuration 
+	Register</i>. The contents can be accessed via \a bits field or via
+	the individual fields via the \a Fld field.
+
+	\copydetails _cpmHwConfigFlds
+
+	\see sFnd::ISetupEx::HW
+**/
+union PACK_BYTES _cpmHwConfigReg {
+    /// \brief Settings as an integer
+    Uint32 bits;
+	/// \brief Field access for hardware configuration.
+	cpmHwConfigFlds Fld;
+
+#ifdef __cplusplus
+#ifndef __TI_COMPILER_VERSION__
+
+	/// Clear bits on construction
+	_cpmHwConfigReg() {
+		bits = 0;
+	}
+
+#endif
+#endif
+};
+/// \copybrief _cpmHwConfigReg
+typedef union _cpmHwConfigReg  cpmHwConfigReg;
+
+																/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmAppConfigFlds union
+//
+// DESCRIPTION
+												/** \cond ExpertDoc **/
+/**
+	\brief ClearPath-SC Application Configuration Register Field Definitions.
+
+	The fields in this register control the various operational modes and 
+	specifications for the features in this node. 
+
+	It controls the following aspects of the node:
+	- Travel Limit processing
+	- Operational modes: Step+Direction vs Host Controlled
+	- Trigger Group assignment
+	- The reversal of the direction input for step+direction
+	- How homing is processed
+	- Control of disabling the node
+**/
+struct PACK_BYTES _cpmAppConfigFlds {
+	/**
+		\brief Limit Switch handling for the limit mode field.
+	**/
+	typedef enum _limitModes {
+		/*!
+		Ignores General Purpose inputs for travel limits.
+		**/
+		LIMIT_MODE_OFF,                     //  0: ignore limits
+		/*!
+		Inputs A and B can be travel limits depending on
+		the crosspoint switch settings.
+		**/
+		LIMIT_MODE_POSITION,                //  1: Limit position
+		/*!
+		Travel limits set using drive parameters.
+		**/
+		LIMIT_MODE_SOFT_POSN = 4,            //  4: Software position limit
+		/*!
+		Travel is limited by soft limits and hardware inputs based on
+		the crosspoint switch settings.
+		**/
+		LIMIT_MODE_SOFT_AND_INPS = 5
+	} limitModes; 
+
+	/**
+		\brief Operational Modes for the Mode field.
+	**/
+	typedef enum _operationalMode {
+		/*!
+		11: Step+Direction is followed
+		**/
+		MOVE_STEP_DIR = 11,
+		/*!
+		20: Idle mode that has no built in commands
+		**/
+		IDLE_MODE = 20
+	} operationalMode;
+
+	// Note: the numbers in the field descriptions denote their bit
+	// range in the register.
+	/*!
+		\brief Operational Mode
+
+		Which operational mode is the drive in
+
+		\note Used by ClearView
+		**/
+	BFld Mode : 6;							// 0-5 Operational Mode
+	/**
+		\brief Trigger Group
+		
+		For advanced models, this field defines the trigger group we will
+		respond to for initiating waiting moves. A zero value removes this
+		node from all groups.
+	**/
+	BFld TriggerGroup : 2;					// 6-7 
+	/*!
+		\brief <i>Limit Switch</i> Enable
+
+		Controls processing of limit switches \todo
+
+		- Ignore Mode (\ref LIMIT_MODE_OFF):
+	**/
+	BFld LimitMode : 3;						// 8-10 Limit switch mode
+	/*!
+		\brief <i>Limit Ramp Stop</i>
+
+		This field controls the type of stop that is used when
+		a limit is encountered. If asserted, a ramp-style stop
+		will be used; otherwise, an abrupt stop will be used
+		for stopping at a limit.
+
+		\note Used by ClearView
+	**/
+	BFld LimitRampStop : 1;					// 11 [TODO] Limit stop type
+													/**  INTERNAL_DOC **/
+	BFld: 2;								// 12-13 
+													/**  **/
+	/*!
+		\brief <i>Step & Direction Command Modes</i> reverses
+		the direction of motion.
+
+		\note Used by ClearView
+	**/
+	BFld DirInputReverse : 1;				// 14
+
+	/**  INTERNAL_DOC **/
+	BFld: 1;								// 15
+
+	/*!
+		\brief <i>Offset Move Performed in Homing Direction</i>
+
+		If asserted, this indicates that the post-homing offset move should be
+		in the same direction as the specified homing.
+
+		\note Used by ClearView
+	**/
+	BFld OffsetMoveInHomeDir : 1;			// 16
+													/**  INTERNAL_DOC **/
+	BFld: 1;								// 17 
+	BFld: 1;								// 18 
+												/**  **/
+	/*!
+		\brief <i>Homing Direction</i>
+
+		Sets the direction for rotation for the homing sequence (asserted
+		means reverse or CW)
+
+		\note Used by ClearView
+	**/
+	BFld HomingDirection : 1;				// 19
+
+	/**  **/
+	/*!
+		\brief <i>On Disable Action</i>
+
+		Sets the action the motor will take upon disabling and for AC
+		units upon loss of AC power.
+
+		\note Used by ClearView and introduced with firmware version 1.6.
+	**/
+	mnDisableActions DisableAction : 3;		// 20-22
+
+													/**  INTERNAL_DOC **/
+	BFld: 7;								// 23-29
+													/**  **/
+	/*!
+		\brief <i>Manual Homing</i>
+
+		Allows a user-driven hardstop homing to be performed in S&D modes
+
+		\note Used by ClearView
+	**/
+	BFld ManualHoming : 1;    				// 30 Manual Homing
+};
+/// \copybrief _cpmAppConfigFlds
+typedef struct  _cpmAppConfigFlds cpmAppConfigFlds;
+												/** \endcond  **/
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmAppConfigReg union
+//
+// DESCRIPTION
+														/** \cond ExpertDoc **/
+/**
+    \brief ClearPath-SC Application Configuration Register Type.
+
+	\copydetails _cpmAppConfigFlds
+
+	\note Care must be taken when changing these to not have them be
+	overridden by ClearView or a <i>Configuration File</i> load.
+
+	\see sFnd::ISetupEx::App For information on changing via the host.
+	\see _cpmAppConfigFlds For Specific field information.
+**/
+union PACK_BYTES _cpmAppConfigReg {
+			
+    /**
+		\brief Register state as an integer.
+
+		Register state as an integer.
+	**/
+    Uint32 bits;
+	/**
+		\brief ClearPath-SC Field view of the <i>Application 
+		Configuration Register</i> .
+	**/
+	cpmAppConfigFlds Fld;                                  
+    // For C++ non-firmware usage, include a constructor.
+    #ifdef __cplusplus
+        #ifndef __TI_COMPILER_VERSION__
+													/**  INTERNAL_DOC **/
+		/// Clear bits on construction
+		_cpmAppConfigReg() {                
+            bits = 0;
+        }
+													/**  **/
+        #endif
+    #endif
+};
+/// \brief ClearPath-SC Application Configuration Register Type.
+typedef union _cpmAppConfigReg cpmAppConfigReg;
+														/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//  NAME                                                                      *
+//      cpmOutFlds structure
+//
+//  DESCRIPTION:
+/**
+    \cond SC_EXPERT
+    \brief ClearPath-SC Output Field Definitions.
+
+    This is a container that defines the output register that is used
+	to control various features of the ClearPath-SC. The actual output
+	register can defined from a combination of the application requests or
+	from the Crosspoint Switch (XPS). The XPS feature allows the mapping
+	of internal state or electrical based inputs to control the state
+	of the operating output register.
+
+    To check on the operations of the Output Register there are a suite of
+    accumulating registers based on the sample-by-sample basis. These read-only
+    functions can access what happened to the output register since the last
+    request
+        - CPMOuts::OutReg
+        - \todo add rise/fall set
+
+    \warning
+    For multi-threaded applications care must be taken to provide
+    serialization for the read-modify-write actions as well as accumulating
+    the Rise and Fall transition registers for use by your application.
+
+    The following diagram shows the layout of this register.
+        \image html "SC_Out_Reg.png"
+        \image latex "SC_Out_Reg.eps"
+**/
+struct PACK_BYTES _cpmOutFlds {
+	/*                            ------
+	 *                             bit #
+	 *                            ------ */
+													
+	BFld		        : 2;		// 1
+													
+	/**
+		\brief Enable drive's power stage.
+
+		This field controls the enabling of the drive's power stage and
+		prepares the node to accept motion commands, which will be
+		accepted when the <i>Status Register's</i>
+		cpmStatusReg::NotReady bit has cleared.
+	**/
+	BFld EnableReq   : 1;			// 2
+	/**
+		
+		\brief Capture measured position on asserting edge.
+
+		The asserting edge (0->1) of This field will capture the measured
+		position to the PLA capture register.
+	**/
+	BFld PosnCapture  : 1;			// 3
+	/**
+		\brief Generate trigger event on asserting edge.
+
+		The asserting edge (0->1) of This field will generate a <i>Trigger
+		Event</i> which allows a waiting move  to begin.
+	**/
+	BFld Trigger     : 1;			// 4
+	/**
+		
+		\brief Generate node stop on asserting edge.
+
+		The asserting edge (0->1) of This field will initiate the node stop
+		programmed in the Stop Type register.
+	**/
+	BFld NodeStop    : 1;			// 5
+	/**
+		\brief Reset general purpose timer.
+
+		The asserting edge (0->1) of This field will reset the <i>General
+		Purpose Timer</i> with duration and
+		clear the timer expired bit in the <i>Status Register</i>.
+
+	**/
+	BFld ResetTimer  : 1;			// 6
+	/**
+		
+		\brief XPS Feedback output 0.
+
+		This output is fed back to a similarly named input in the
+		<i>Status Register</i>. It is used to make simple state machines
+		or to map inputs available to the XPS system to an Attentionable
+		location.
+	**/
+	BFld XPSattn0    : 1;			// 7
+	/**
+		\brief XPS Feedback output 1.
+
+		This output is fed back to a similarly named input in the
+		<i>Status Register</i>. It is used to make simple state machines or
+		to map inputs available to the XPS system to an Attentionable
+		location.
+		\todo Doc details?
+	**/
+	BFld XPSattn1    : 1;			// 8
+													
+	BFld             : 1;			// 9
+	BFld             : 1;			// 10
+													
+	/**
+		\brief Signal the end of homing move.
+
+		If homing move in progress, terminate it and start any offset
+		motion and mark this position as the zero point.
+	**/
+	BFld TerminateHomeMove	: 1;	// 11
+	/**
+		\brief Start Positive torque foldback
+
+		Setting This field can control the amount of positive torque
+		available. The Positive Foldback Torque (IFoldbacksAdv::PositiveTrq)
+		parameter controls the amount.
+
+		\todo ISCfoldbackPage
+	**/
+	BFld StartPosTrqFldBk : 1;		// 12
+	/**
+		\brief Start Negative torque foldback
+
+		Setting This field can control the amount of negative torque
+		available. The Negative Foldback Torque (IFoldbacksAdv::NegativeTrq)
+		parameter controls the amount.
+
+		\todo ISCfoldbackPage
+	**/
+	BFld StartNegTrqFldBk : 1;		// 13
+	/**
+		\brief Positive Limit detected.
+
+		This will cancel any positive motion and prevent additional
+		travel in the positive direction if the limit mode is set
+		appropriately.
+	**/
+
+	BFld PosLimitHit  : 1;			// 14 
+	/**
+		\brief Negative Limit detected.
+
+		This will cancel any negative motion and prevent additional
+		travel in the negative direction if the limit mode is set
+		appropriately.
+	**/
+	BFld NegLimitHit  : 1;			// 15 
+};
+/// ClearPath-SC Output Register Field Definitions
+typedef struct _cpmOutFlds cpmOutFlds;
+//              \endcond                                                              *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmOutReg union
+//
+// DESCRIPTION
+/**
+	 \cond INTERNAL_DOC
+	\brief ClearPath-SC Output Register Type.
+
+	This union is used to hold the contents of a ClearPath-SC output register.
+**/
+union PACK_BYTES _cpmOutReg
+{
+	/**
+		\brief Bit-wise access to the ClearPath-SC output register.
+	**/
+	Uint16 bits;
+	/**
+		\brief Field access to the ClearPath-SC output register.
+	**/
+	cpmOutFlds Fld;
+
+#ifdef __cplusplus
+#ifndef __TI_COMPILER_VERSION__
+
+	/// Clear bits on construction
+	_cpmOutReg() {
+		bits = 0;
+	}
+
+#endif
+#endif
+};
+
+/// ClearPath-SC Output Register Type
+typedef union _cpmOutReg cpmOutReg;
+//       \endcond                                                                     *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmStatusRegFlds structure
+//
+// DESCRIPTION
+
+/**
+	\brief ClearPath-SC Node Status Register Fields.
+
+	This page provides the detailed list of fields in the ClearPath SC status register.  
+	The lower 32-bits of this register are attentionable.
+
+
+	\see sFnd::ValueStatus for information on accessing different status registers within the Node.
+	\see \ref AttentionsPage for information regarding attentions.
+
+	\image html "SC_Status_Reg.png"  "Status Register Overview"
+	\image latex "SC_Status_Reg.eps" "Status Register Overview"	height=5in
+**/
+struct PACK_BYTES _cpmStatusRegFlds {
+	/**
+		\brief Motion Activity Indicator
+
+		This is a bit-mapped field definition that describes 
+		the current motion detected on the motor. The VEL_BOTH
+		state will occur with accumulating status when the motor
+		has moved in both directions since the last status query.
+	**/
+													/** \cond INTERNAL_DOC **/
+	typedef enum _velStates {
+		VEL_STOPPED,					//< 0: Stopped
+		VEL_POSITIVE,					//< 1: Positive velocity detected
+		VEL_NEGATIVE,					//< 2: Negative velocity detected
+		/** 3: For accumulating registers, this represents the detection of 
+			velocity in both directions **/
+		VEL_BOTH						
+	} velStates;
+	/**
+		\brief Shutdown States
+
+		This represents the current shutdown state. SHDN_STATE_IDLE means
+		the node is running with no current or pending shutdowns.
+	**/
+	typedef enum _shutdownStates {
+		SHDN_STATE_IDLE         = 0,    ///< All is well
+														
+		SHDN_STATE_DELAY        = 1,    ///< Shutdown is imminent
+		SHDN_STATE_RAMP         = 2,   ///< Axis is ramping down to zero speed
+														
+		SHDN_STATE_STOPPED      = 3    ///< Axis is shutdown
+	} shutdownStates;
+															/** \endcond  **/
+	/*  bits 00-15 - - - - - - - - - - - - - - - - - - - - - - ------ */
+	// Attentionable bits start here
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	//										Bit #
+											/** \cond INTERNAL_DOC **/
+	/**
+		\brief Warning is present.
+
+		This field is set when the bit-wise AND of the User Warning register
+		and the Warning Register is non-zero.
+
+		\see sFnd::IAttnNode::WarnMask
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+		**/
+	BFld Warning					: 1;	// 00 
+											/** \endcond  **/
+	/**
+		\brief User alert is present.
+
+		This field is set when the bit-wise AND of the [User Alert register](@ref sFnd::IAttnNode::AlertMask)
+		and the Alert Register is non-zero.
+
+		\see sFnd::IAttnNode::AlertMask
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+		**/
+	BFld UserAlert					: 1;    // 01
+	/**
+		\brief Node not ready for operation.
+
+		If this field is true, a Node is not ready to execute motion.  You must make sure to [clear shutdowns](@ref sFnd::IStatus::AlertsClear), ensure the
+		node is [Enabled](@ref sFnd::INode::EnableReq), and [clear any NodeStops.](@ref sFnd::IMotion::NodeStopClear)
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld NotReady					: 1;    // 02
+	/**
+		\brief Move buffer is available.
+
+		This field indicates the Node can receive additional move commands which will be stored in the Node's move buffer.
+		If this bit is deasserted, any move command sent to the Node will be ignored.
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld MoveBufAvail				: 1;	// 03
+	/**
+		\brief Node ready for operation.
+
+		This field is asserted when a Node is ready to receive motion commands.
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld Ready						: 1;    // 04
+
+	/**
+		\brief Power Event Occurred.
+
+		This field is asserted when a power event occurs. The power status
+		register can be used to determine the specifics.
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld PowerEvent					: 1;	// 05
+
+	/**
+		\brief Alert Present.
+
+		This field is set when the <i>Alert Register</i> is non-zero.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld AlertPresent				: 1;    // 06
+													/** \cond INTERNAL_DOC **/
+	BFld 							: 1;	// 07
+													/** \endcond **/
+	/**
+		\brief Positive limit asserted.
+
+		When This field is asserted, the Node is unable to execute moves in the positive direction.
+		The input configured through Clearview to limit motion in the positive direction is currently limiting motion.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld InPosLimit					: 1;    // 08 
+	/**
+		\brief Negative limit asserted.
+
+		When This field is asserted, the Node is unable to execute moves in the negative direction.
+		The input configured through Clearview to limit motion in the negative direction is currently limiting motion.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld InNegLimit					: 1;    // 09
+	/**
+		\brief Motion Blocked.
+
+		This field is asserted when motion is blocked by an E-Stop Nodestop Type.
+
+		\see CPMnodeStopPage
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld MotionBlocked				: 1;	// 10 
+	/**
+		\brief Was Homed
+
+		Indicates that a homing sequence has been
+		executed.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling. 
+	**/
+	BFld WasHomed					: 1;	// 11
+	///\endcond
+	/**
+		\brief In Homing Sequence
+
+		Indicates that a homing sequence is being
+		executed.	
+
+		\see [Homing Page](@ref HomingPage) for more information on homing
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling. 
+	**/
+	BFld Homing						: 1;	// 12
+	/**
+		\brief Going To Disable Soon
+
+		Indicates that the drive is about to go
+		disabled.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling. 
+	**/
+	BFld GoingDisabled				: 1;	// 13
+	/**
+		\brief Status Rise Event detected
+
+		This field is set when the bit-wise AND of the [Status Mask](@ref sFnd::IAttnNode::StatusMask)
+		and the Status Register is non-zero.
+
+		\see sFnd::IAttnNode::StatusMask
+
+		\remark
+		This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld StatusEvent				: 1;	// 14
+	/**
+		\brief Drive Enabled
+
+		This field is set when the drive is enabled. 
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld Enabled					: 1;	// 15
+	/*  bits 16-31 - - - - - - - - - - - - - - - - - - - - - - ------ */
+	/**
+		\brief Motion Canceled.
+
+		This condition will occur when a queued or executing move
+		is canceled en-route by a NodeStop.
+
+		\see CPMnodeStopPage
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld MoveCanceled		: 1;	// 16
+	/**
+		\brief Move completed and settled.
+
+		This field asserts when a Move is complete.
+
+		\see \ref CPMmoveDonePage
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+   **/
+	BFld MoveDone			: 1;    // 17
+	/**
+		\brief Tracking out of range.
+
+		This field indicates the Node is currently not tracking within the In-Range window.  This is especially common during moves.
+
+		\see \ref CPMmoveDonePage for more information regarding setting up the In-Range window in ClearView
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld OutOfRange			: 1;    // 18
+	/**
+		\brief <i>B Counts from End</i> of move.
+
+		This field asserts when the move is [B From End](@ref sFnd::IMotionAdv::BeforeEndDistance) of the move.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld BFromEnd			: 1;    // 19
+	/**
+		\brief Greater than position location.
+
+		This field asserts when the measured position is greater than
+		the  Absolute Position location specified in the torque limiting dialog window of ClearView.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld AbovePosn			: 1;    // 20
+	/**
+		\brief At Target Velocity.
+
+		This field asserts when velocity commands have reached their
+		target velocity.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld AtTargetVel		: 1;	// 21
+	/**
+		\brief Input-A state.
+
+		This field asserts when the Node's input A asserts.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld InA				: 1;    // 22
+	/**
+		\brief Input-B state.
+
+		This field asserts when the Node's input B asserts.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld InB				: 1;    // 23
+	/**
+		\brief Inverted Input-A state.
+
+		This field asserts when the Input-A is de-asserted.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld InvInA				: 1;    // 24
+	/**
+		\brief Inverted Input-B state.
+
+		This field asserts when the Input-B is de-asserted.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld InvInB				: 1;    // 25
+													/** \cond INTERNAL_DOC **/
+	BFld					: 2;    // 26-27
+													/** \endcond **/
+
+	/**
+		\brief <i>A From Start</i> of move.
+
+		This field asserts when the move is [A From Start](@ref sFnd::IMotionAdv::AfterStartDistance) of the move. 
+		
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld AFromStart			: 1;    // 28
+	/**
+		\brief Commanded move is negative.
+
+		This field asserts when the current command resulted in the
+		position changing in a negative direction. This field changes
+		at the start of a move and persists until the next move.
+		A zero step move is considered positive.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld MoveCmdNeg			: 1;    // 29
+	/**
+		\brief Drive is disabled.
+
+		This field asserts when the drive is disabled.
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld Disabled			: 1;	// 30
+												/** \cond INTERNAL_DOC **/
+	/**
+		\brief <i>General Purpose Timer</i> has expired.
+
+		This field asserts when the <i>General Purpose Timer</i>
+		timer has expired. This timer is reset by the
+		cpmOutReg::ResetTimer bit in the <i>Output
+		Register.</i> The duration of this timer is set by the
+		<i>General Purpose Timer Time Constant</i>
+		(CPM_P_GP_TIMER_PERIOD).
+
+		\remark This field can generate an attention request to the host for
+		autonomous handling.
+	**/
+	BFld TimerExpired		: 1;	// 31
+												/** \endcond  **/
+
+	/*  bits 32-47 - - - - - - - - - - - - - - - - - - - - - - ------ */
+	// ------------ Remaining fields are not attentionable ------------
+	/**
+		\brief Motion Indicator.
+
+		This field represents the load's velocity status. The
+		table describes the states:
+		- 0: Near zero speed
+		- 1: Moving in a positive direction
+		- 2: Moving in a negative direction
+		- 3: Moved in both directions since the last read (for Accumulating Registers)
+	**/
+	// Avoid VS compiler padding bug, don't use enum
+	BFld InMotion					: 2;	// 32-33 
+	/**
+		\brief The Output Register disable bit is set due to a NodeStop.
+
+		The Node Stop feature has forced the enable output to the
+		disabled state.  [Clear Nodestops](@ref sFnd::IMotion::NodeStopClear) to return the Node to it's previous enable state.
+
+		\see \ref CPMnodeStopPage
+	**/
+	BFld InDisableStop				: 1;	// 34
+											/** \cond INTERNAL_DOC **/
+	/**
+		\brief Controlled Stop in affect.
+	**/
+	BFld InCtrlStop      			: 1;	// 35 
+	/**
+		\brief Fan running.
+
+		For units with a fan, this field is asserted when the
+		fan is on. This is a warning that the drive
+		temperature is approaching the shutdown level.
+	**/
+	BFld FanOn           			: 1;	// 36 
+											/** \endcond  **/
+	/**
+		\brief Vector searching.
+
+		This field asserted when the vector has not been finalized.  
+		Typically, this happens on the first enable after power-up.
+		Once the vector is finalized normal operation can commence.
+	**/
+	BFld VectorSearch    			: 1;	// 37 
+	/**
+		\brief Motion command has completed.
+
+		This field is asserted after the motion command has been completed.
+		The move is considered totally complete when the [Move Done](@ref _cpmStatusRegFlds::MoveDone) has been asserted.
+	**/
+	BFld MoveCmdComplete			: 1;    // 38
+	/**
+		\brief In hard-stop mode.
+
+		This field asserts when the ClearPath-SC has entered the <i>
+		Hard Stopped</i> mode during homing and the node is applying clamping
+		torque. 
+
+		\see HomingPage
+	**/
+	BFld InHardStop     			: 1;    // 39 
+	/**
+		\brief Shutdown state.
+
+		These fields describes the shutdown condition of the node:
+		- 0: Idle: no shutdowns are present
+		- 1: Delay: A shutdown is imminent 
+		- 2: Ramp: Node is ramping down to zero speed
+		- 3: Stopped: Node is currently shutdown
+	**/
+	// Avoid VS compiler padding bug, don't use enum
+	BFld ShutdownState				: 2;	// 40-41
+
+	/**
+		\brief Hardware failure detected.
+
+		The unit's shutdown is caused by a hardware failure. This
+		unit should be replaced.
+	**/
+	BFld HwFailure      			: 1;	// 42
+	/**
+		\brief Move awaiting trigger event.
+
+		The node has a triggered move awaiting release.
+
+		\see \ref CPMtriggerPage
+	**/
+	BFld TriggerArmed   			: 1;	// 43
+	/**
+		\brief This field is set true when the step+direction inputs are
+		active.
+
+		This field is set true when the step and direction inputs are
+		active.
+	**/
+	BFld StepsActive     			: 1;	// 44
+											/** \cond INTERNAL_DOC **/
+	/**
+		\brief Index detected on motor encoder.
+
+		The node has detected an index pulse on the motor's encoder.
+	**/
+	BFld IndexMtr       			: 1;	// 45
+											/** \endcond **/
+											/** \cond INTERNAL_DOC **/
+    /**
+		\brief Software inputs are being used.
+
+        Indicates when inputs that have the ability to be controlled either
+        by software or hardware have been switched to software control.
+    **/
+    BFld SoftwareInputs  			: 1;    // 46	
+											/** \endcond  **/
+	// ------------------------------------------------------------------------
+																/** \cond INTERNAL_DOC **/
+	/** 
+		\brief Update a string with the set fields in the Status Register.
+
+		\param[in,out] buffer  Point to string buffer to update
+		\param[in] size  The size of the buffer in characters including the null
+		character.
+		\return the parameter \a buffer.
+		<b>Example Code</b>
+		\code
+			char myBuffer[500];
+			cout << myStatusRef.cpm.StateStr(myBuffer, sizeof(myBuffer));
+		\endcode
+	**/
+	MN_EXPORT char * MN_DECL StateStr(char *buffer, size_t size) const;
+																/** \endcond  **/
+};
+/// ClearPath-SC Status Register Field definitions
+typedef struct _cpmStatusRegFlds cpmStatusRegFlds;
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmStatusReg union
+//
+// DESCRIPTION
+													/** \cond INTERNAL_DOC **/
+/**
+	\brief ClearPath-SC Status Register Type.
+
+	The status register type defines the very large register which maintains 
+	the status and state of the node. The node maintains a suite of these
+	registers that have various behaviors. 
+
+	There are accumulating types that clear upon reading and one snap shot
+	of the current state.
+
+	Details of this register:
+	\copydetails _cpmStatusRegFlds
+
+	\see sFnd::IStatus::RT	Real-time snapshot.
+	\see sFnd::IStatus::Rise	Items that have asserted since last access.
+	\see sFnd::IStatus::Fall	Items that have deasserted since last access.
+	\see sFnd::IStatus::Accum Items that have asserted, and accumulate. This is 
+	is similar to the sFnd::IStatus:Rise, but currently asserted status is not
+	cleared upon reading.
+**/
+union PACK_BYTES _cpmStatusReg {
+	/**
+		\brief Bit-wise integer access to the status register.
+	**/
+	Uint16 bits[3];
+	/**
+		\brief Access to the fields of the ClearPath-SC <i>Status Register</i>.
+	**/
+	cpmStatusRegFlds Fld;
+
+#ifdef __cplusplus
+
+	// Constructor, create with bits cleared
+	_cpmStatusReg() {                   // Clear bits on construction
+		bits[0] = 0;
+		bits[1] = 0;
+		bits[2] = 0;
+	}
+#endif
+
+
+};
+/// ClearPath-SC Status Register Type
+typedef union _cpmStatusReg cpmStatusReg;
+														/** \endcond  **/
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmAlertFlds struct
+//
+// DESCRIPTION
+/**
+	\brief ClearPath-SC Alert and Warning Register Field Definitions.
+
+	This page provides the detailed list of the Clearpath SC alerts. These fields describe the reason a
+	shutdown has occurred, and potential solutions.
+
+	\see sFnd::ValueAlert For information on accessing alert registers within the Node
+
+	\image html "cpmAlertReg.png"
+
+**/
+struct PACK_BYTES _cpmAlertFlds {
+    /// \brief Common shutdown events. Least significant bits 0-31.
+	commonAlertFlds Common;
+    //                              ----------------------------------------
+    //                              |len|bit #|description                 |
+    //                              ----------------------------------------
+									/** \cond INTERNAL_DOC **/
+	BFld : 4; /* 32-35 */
+									 /** \endcond **/
+											   /** \cond INTERNAL_DOC **/
+	/**
+	\brief Jerk Limit Bad.
+
+	A move was started with bad Jerk Limit request. An illegal or
+	malformed <i>Jerk Limit</i> was specified for a move starting.
+	This move canceled.
+
+	Remedies:
+	- Check the Jerk Limit setting before issuing the move.
+	**/
+	BFld JrkLimRequestBad : 1; /* 36 */
+											   /** \endcond  **/
+											   /** \cond INTERNAL_DOC **/
+	/**
+	\brief Move Buffer Under-run.
+
+	Move Generator ran out of pending moves before the terminal move.
+	This would occur with move sequences where the host cannot keep
+	up with the moves required to follow a path.
+
+	Remedies:
+	- Create moves with longer time intervals.
+	- Use a more efficient mechanism to keep the move buffer busy.
+	Sometimes an attention-based mechanism will work.
+	**/
+	BFld MoveBufUnderrun : 1; /* 37 */
+													  /** \endcond  **/
+	/**
+	\brief Velocity limit too high for jerk limit.
+
+	The move was canceled due to the [Velocity Limit](@ref sFnd::IMotion::VelLimit) of the attempted move exceeding
+	the encoder's or RAS/G-Stop's maximum allowed speed.
+
+	Remedies:
+	- Reduce the [Velocity Limit](@ref sFnd::IMotion::VelLimit) of the move. 
+	- Decrease the RAS/G-Stop to one with less speed limiting(a lower time).
+	
+	**/
+	BFld JrkLimVelRequestBad : 1; /* 38 */
+								  /** \cond INTERNAL_DOC **/
+	/**
+	\brief Invalid move spec was altered.
+
+	The move could not meet both the distance and acceleration
+	parameters of the move with the given initial velocity.
+	The acceleration limit was increased to allow the
+	move to complete without overshooting.
+
+	Remedies:
+	- Allow a longer distance for the terminal move.
+	- Increase the [Acceleration Limit](@ref sFnd::IMotion::AccLimit).
+	- Reduce the velocity prior to the terminal move.
+	**/
+	BFld MoveSpecAltered : 1; /* 39 */
+									/** \endcond  **/
+	/**
+	\brief Phase sensor bad.
+
+	Phase sensor failed power-on self test.
+
+	Remedies:
+	- Replace motor.
+	**/
+	BFld PhaseSensorFailed : 1; /* 40 */
+	/**
+	\brief Limit switch activated.
+
+	Attempting to move in a direction in which the limit switch
+	is activated. Motion in the direction of the limit is prevented.  The current move, and any queued moves, are
+	canceled.
+
+	Remedies:
+	- Move away from the limit switch or clear the limit switch activation.
+	**/
+	BFld LimSwitchActivated : 1; /* 41 */
+	/**
+	\brief Soft limit prevents move.
+
+	A move attempted to exceed the bounds set by the software limits.
+	The current move, and any queued moves, are canceled.
+
+	Remedies:
+	- Decrease the distance of the commanded move such that it ends within the bounds of the current soft limit settings.
+	- Move away from the limit
+	- Adjust the soft limit settings.
+
+	**/
+	BFld SoftLimitExceeded : 1; /* 42 */
+								/** \cond INTERNAL_DOC **/
+								// Note: Must be separate around word boundary
+	BFld : 5; /* 43-47 */
+	BFld : 4; /* 48-51 */
+								/** \endcond **/
+	/**
+	\brief AC Power Lost
+
+	Motor was running with AC power and AC power has been removed.
+
+	Remedies:
+	- Check AC power wiring and power quality to attached modules.
+	**/
+	BFld ACPowerLost		    : 1; /* 52 */ // AC Power lost
+	/**
+	\brief AC Phase Lost
+
+	Motor was running with AC power and one or more of the AC phases have been removed.
+
+	Remedies:
+	- Check AC power wiring and power quality to attached modules.
+	**/
+	BFld ACPhaseLost		    : 1; /* 53 */ // AC Phase lost
+								/** \cond INTERNAL_DOC **/
+	BFld : 1; /* 54 */
+								/** \endcond **/
+	/**
+	\brief Low motor temperature.
+
+	The motor has detected an excessive operating
+	temperature. This condition is recoverable when the
+	temperature has been sufficiently reduced.
+
+	Remedies:
+	- Move the motor to a warmer environment.
+	**/
+	BFld MtrTempLow				: 1; /* 55 */
+								/** \cond INTERNAL_DOC **/
+	BFld : 2; /* 56-57 */
+								/** \endcond **/
+
+	/**
+	\brief Vector Problem.
+
+	The motor's commutation vector has drifted. This will lead to poor
+	performance. This is normally a warning indication.
+
+	Appears in: WarnReg
+
+	Remedies:
+	- Replace defective motor.
+	**/
+	BFld MtrVectorBad : 1; /* 58 */
+	/** \cond INTERNAL_DOC **/
+							
+	BFld : 1; /* 59 */
+							/** \endcond **/
+	/**
+	\brief Motor encoder glitch.
+
+	A glitch was detected on the motor encoder signals.
+
+	Remedies:
+	- Replace motor.
+	**/
+	BFld MtrEncGlitch : 1; /* 60 */
+						   /** \cond INTERNAL_DOC **/
+	/**
+	\brief Motor Encoder Overspeed.
+
+	The motor's encoder has exceeded the speed limit of the Motor.
+
+	Appears in: WarnReg
+
+	Remedies:
+	- Reduce commanded speed.
+	**/
+	BFld MtrEncOverspeed : 1; /* 61 */
+						
+	BFld : 2; /* 62-63 */
+							/** \endcond **/
+	/**
+	\brief Motor phase overload.
+
+	A motor phase has overloaded.
+
+	Remedies:
+	- Restore motor to factory defaults and reload a valid configuration
+	file.
+	- Check the mechanics for abnormally high friction/binding. Grease if necessary.
+	- If problem persists under no-load conditions, replace motor.
+	**/
+	BFld MtrPhaseOverload : 1; /* 64 */
+								/** \cond INTERNAL_DOC **/
+	BFld : 1; /* 65 */
+								/** \endcond **/
+	/**
+	\brief Bad motor parameters.
+
+	A motor-specific parameter has an illegal value.
+
+	Remedies:
+	- Restore motor to factory defaults and reload a valid configuration
+	file.
+	- If restoring to factory defaults doesn't clear the problem, replace
+	 motor.
+	**/
+	BFld MtrBadSetupParams : 1; /* 66 */
+	/**
+	\brief Hardstop broke free.
+
+	The hardstop moved when pressure was applied by the motor. Once the motor
+	has qualified for the hardstop condition, the mechanics must stay reasonably still while motor torque is applied at the foldback level.
+	If the coupling or hardstop should break free, the axis will move in the direction of the hardstop and this alert will be issued
+
+	Remedies:
+	- Checking homing parameters in ClearView
+	- Ensure that the hardstop for this axis is solid and unmovable.
+	- For High friction applications, or machines subject to binding issues, ensure that the hardstop entry torque defined through ClearView
+		is high enough that the motor will not qualify for the hardstop condition except when the axes is against the hardstop on the machine.
+	**/
+	BFld HardStopBrokeFree : 1; /* 67 */
+								/** \cond INTERNAL_DOC **/
+	BFld : 1; /* 68 */
+								/** \endcond **/
+	/**
+	\brief Tracking shutdown.
+
+	The position tracking error has exceeded the user specified critical tracking limit.
+	This is a resettable shutdown condition.
+
+	Remedies:
+	- Check the mechanics for abnormally high friction/binding. Grease if necessary.
+	- Reduce velocity, acceleration, and/or duty cycle.
+	- Check that the configuration file is appropriate for this motor.
+	- Increase tracking error limit to a higher value through the ClearView application.
+
+	**/
+	BFld TrackingShutdown : 1; /* 69 */
+							   /** \cond INTERNAL_DOC **/
+	/**
+	\brief RMS Overload Warning.
+
+	This warning occurs when the RMS load is approaching the critical limit.
+
+
+	Remedies:
+	- Check the mechanics for abnormally high friction/binding.
+	- Reduce feed rate.
+	- Improve tuning.
+	- Use a larger motor.
+	**/
+	BFld RMSOverload : 1; /* 70 */
+								/** \endcond  **/
+	/**
+	\brief RMS torque overload shutdown.
+
+	The RMS torque of the motor has exceeded the critical limit. This is a resettable shutdown
+	condition.
+
+	Remedies:
+	- Check the mechanics for abnormally high friction/binding.
+	- Reduce velocity, acceleration, and/or duty cycle.
+	- Check that the configuration file is appropriate for this motor.
+	- If the motor is actively cooled with a fan raise the continuous current limit of the motor appropriately
+	- Use a larger motor.
+	**/
+	BFld RMSOverloadShutdown : 1; /* 71 */
+								/** \cond INTERNAL_DOC **/
+	BFld : 2; /* 72-73 */
+	/**
+	\brief Bus Voltage Saturation.
+
+	This warning occurs when full bus voltage was required to
+	drive the motor.
+
+	Appears in: WarnReg
+
+	Remedies:
+	- Check power taps to bus supply.
+	- Check torque loop tunings.
+	- Check for mechanical issues such as binding.
+	- Check gearing and motor sizing for this application.
+	- See system configuration manual for more tips on this condition.
+	**/
+	BFld BusVoltSat : 1; /* 74 */
+	/**
+	\brief Torque Saturation.
+
+	This warning occurs when full torque was commanded to
+	drive the motor.
+
+	Appears in: WarnReg
+
+	Remedies:
+	- Check power taps to bus supply.
+	- Check torque loop tunings.
+	- Check for mechanical issues such as binding slides.
+	- Check gearing and motor sizing for this application.
+	- Check for the misapplication of any torque limiters such as
+	the Global Torque Limit.
+	- See system configuration manual for more tips on this condition.
+	**/
+	BFld TrqSat : 1; /* 75 */
+					 /** \endcond  **/
+	/**
+	\brief Insufficient sensorless sweep distance.
+
+	This shutdown occurs when a motor's sensorless start fails to
+	move the appropriate distance.
+
+	Remedies:
+	- Check the mechanics for abnormally high friction/binding. Grease if necessary.
+	- Check for excessive external forces acting on the axis.
+	- Verify that the configuration file is correct for the motor;
+	reload the configuration file.
+	- Check that the power supply has been correctly configured
+	for your AC voltage, and is producing the expected voltage level.
+	- Check for the misapplication of any torque limiters such as
+	the Global Torque Limit that might be limiting torque in the motor.
+	**/
+	BFld NoCommSweepFailed : 1; /* 76 */
+	/**
+	\brief Sensorless motion in wrong direction.
+
+	This shutdown occurs when a motor's sensorless start detects
+	the motor moving in the wrong direction.
+
+	Remedies:
+	- Verify that the configuration file is correct for the motor;
+	reload the configuration file.
+	- Check for excessive external forces acting on the axis.
+	- Check that the power supply has been correctly configured
+	for your AC voltage, and is producing the expected voltage level.
+	- Check the mechanics for abnormally high friction/binding.
+	**/
+	BFld NoCommSweepReversed : 1; /* 77 */
+	/**
+	\brief Sensorless startup failed.
+
+	This shutdown occurs when the sensorless startup failed
+	after too many retries.
+
+	Remedies:
+	- Verify that the configuration file is correct for the motor;
+	reload the configuration file.
+	- Check that the power supply has been correctly configured
+	for your AC voltage, and is producing the expected voltage level.
+	- Check the mechanics for abnormally high friction/binding.
+	- Check for excessive external forces acting on the axis.
+	**/
+	BFld NoCommFailed : 1; /* 78 */
+						   /** \cond INTERNAL_DOC **/
+	/**
+	\brief Index Count Zero Warning.
+
+	This warning occurs when no index pulses have been detected.
+
+	Remedies:
+	- Replace defective motor.
+	**/
+	BFld IndexCountZeroWarn : 1; /* 79 */
+								 /** \endcond  **/
+	/**
+	\brief High Drive temperature.
+
+	The motor has detected an excessive operating
+	temperature. This condition is recoverable when the
+	temperature has been sufficiently reduced.
+
+	Remedies:
+	- Provide more ventilation/fan cooling to motor.
+	**/
+	BFld DriveTempHigh : 1; 	/* 80 */
+
+	/**
+	\brief Stator temperature.
+
+	The motor has detected an excessive motor stator operating
+	temperature. This condition is recoverable when the
+	temperature has been sufficiently reduced.
+
+	Remedies:
+	- Provide more ventilation/fan cooling to motor.
+	**/
+	BFld StatorTempHigh	: 1; /* 81 */
+
+	/**
+	\brief Motor's bus power supply overloaded.
+
+	The motor's bus current has exceeded maximum thresholds.
+
+	Remedies:
+	- Increase the bus voltage.
+	- If condition still persists under non-stressful no-load conditions,
+	replace the damaged motor.
+	- Check the mechanics for abnormally high friction/binding. Grease if necessary.
+	**/
+	BFld BusOverCurrent : 1; /* 82 */
+	/**
+	\brief Motor's bus power supply voltage too high.
+
+	The motor's bus voltage has exceeded maximum thresholds.
+	This is recoverable when the bus voltage return to the operating range of the motor.
+
+	Remedies:
+	- Check that the power supply has been correctly configured
+	for your AC voltage and is producing the expected voltage level.
+	- Check and/or install regenerated bus voltage management system.
+	**/
+	BFld BusOverVoltage : 1; /* 83 */
+	/**
+	\brief Motor's bus power supply voltage too low.
+
+	The motor has detected a loss or brown-out of the motor's bus
+	voltage. This condition will automatically clear upon restoration
+	of the bus voltage without host intervention.
+
+	Remedies:
+	- Check that the power supply has been correctly configured
+	for your AC voltage and is producing the expected voltage level.
+	- Check the mechanics for abnormally high friction/binding. Grease if necessary.
+	**/
+	BFld BusVoltageLow : 1; /* 84 */
+	/**
+	\brief Motor's bus power supply overloaded.
+
+	The motor's bus current has exceeded maximum continuous thresholds.
+
+	Remedies:
+	- Check that the power supply has been correctly configured
+	for your AC voltage and is producing the expected voltage level.
+	- Check the mechanics for abnormally high friction/binding.
+	- Verify the configuration file in the motor is appropriate.
+	- Reduce motion duty cycle, acceleration, or load.
+	**/
+	BFld BusRMSOverload : 1; /* 85 */
+													/** \cond INTERNAL_DOC **/
+	BFld : 1; /* 86 */
+	/**
+	\brief MtrEncIndexMissing
+
+	The motor encoder index was not seen when it was expected.
+
+	Appears in: AlertReg, WarnReg
+
+	Remedies:
+	- Replace defective motor
+	**/
+	BFld MtrEncIndexMissing : 1; /* 87 */
+	
+	/**
+	 * \brief Bus Voltage under Minimum Operating Voltage
+	 *
+	 * The motor's bus voltage has drooped below the user-defined operating voltage.
+	 *
+	 * Remedies:
+	 *  - Check that the Minimum Operating Voltage parameter is set correctly
+	 * 	- Check that the power supply has been correctly configured
+	 *  for your voltage and is producing the expected voltage level.
+	 *  - Check the mechanics for abnormally high friction/binding. Grease if necessary.
+	 */
+	BFld BusVoltageUnderOperatingV : 1; /* 88 */
+
+	BFld : 1; /* 89 */
+													/** \endcond **/
+													/** \cond INTERNAL_DOC **/
+	BFld : 3; /* 90-92 */
+													/** \endcond **/
+	/**
+	\brief MtrEncIndexMisplaced
+
+	The motor encoder index was seen when it was not expected.
+
+	Appears in: AlertReg, WarnReg
+
+	Remedies:
+	- Replace defective motor
+	**/
+	BFld MtrEncIndexMisplaced : 1; /* 93 */
+	/**
+	\brief StepsDuringPosnRecovery
+
+	Step input commands were seen during the position recovery operation.
+
+	Appears in: AlertReg
+
+	Remedies:
+	- Check that power supply is producing the expected voltage level.
+	- Do not send steps until the motor is ready
+	**/
+	BFld StepsDuringPosnRecovery : 1; /* 94 */
+
+	/**
+	\brief Create a new line delimited string of the alerts set.
+
+	Create a new line delimited string of the alerts set
+
+	\param[in,out] buffer Pointer to a string buffer to replace with the
+	alert fields that are non-zero.
+	\param[in] size Count of characters in \a buffer.
+	\return The original pointer the buffer \a buffer. This allows this function
+	to be the argument of printing statement or other formatting function.
+	**/
+	MN_EXPORT char * MN_DECL StateStr(char *buffer, size_t size) const;
+													/** \endcond  **/
+};
+
+/// ClearPath-SC Alert and Warning Register Field Definitions
+typedef struct _cpmAlertFlds  cpmAlertFlds;
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  cpmAlertReg union
+//
+// DESCRIPTION
+// Alert Register Size in octets: 96 bits = 3 32-bit entities = 12 octets
+														/** \cond SC_EXPERT **/
+/**
+	\brief ClearPath-SC Alert and Warning Register Type.
+
+	The alert and its related warning registers define the shutdown and
+	transient operational state of the node. When a node enters a shutdown
+	or potentially non-operable condition, the node will set bits in this
+	register to tell the application what went wrong. The bits are classified
+	by the following criteria:
+	- \b Serious-fatal. This means the node has some condition that will
+	prevent its operation. This is usually due to some setup issue or a
+	hardware failure detected during the power-on self check. See the specific
+	bit for potential recovery actions to allow node operations to continue.
+	If the <i>Status Register's</i> [HwFailure](@ref _cpmStatusRegFlds::HwFailure) bit is asserted, this is a
+	hardware failure and recovery is probably not possible.
+	- \b Serious. This means some node self-preservation shutdown occurred.
+	This can occur for various reasons, such as an excessive amount of torque
+	was being utilized by the application.
+	- \b Warning. These bits are usually set in the Warning register first
+	to provide a "heads up" indication of looming troubles. Sometimes they
+	will propagate to the Alert register and cause a shutdown.
+
+	Many shutdowns can be cleared via the sFnd::IStatus::AlertsClear function to allow
+	continued node operations. Most fatal errors cannot be cleared by this
+	mechanism and require a power-cycle or node restart to clear them.
+
+	The following diagram illustrates big picture view of the register.
+
+	\image html "cpmAlertReg.png"
+**/
+union _cpmAlertReg {
+	/// \brief Bit-wide view of register as three unsigned 32-bit integers.
+	Uint32 bits[3];
+	/// \brief Field access to the ClearPath-SC status register
+	cpmAlertFlds Fld;
+	// If we have C++, include these useful member functions.
+																/// cond INTERNAL_DOC
+	#ifdef __cplusplus
+	#ifdef __TI_COMPILER_VERSION__
+	bool InShutdown();
+	bool InLockdown();
+	bool InBlockMotionShutdown();
+	bool InBlockMotionSelfClearShutdown();
+	bool InNodeNeedsRepairShutdown();
+	bool InSeriousShutdown();
+	bool InKillOutputsShutdown();
+	bool InAlert();
+	#endif
+	// Constructor, create with bits cleared
+	_cpmAlertReg() {                   // Clear bits on construction
+		STATIC_ASSERT(ALERTREG_SIZEOCTETS == 12);
+		bits[0] = 0;
+		bits[1] = 0;
+		bits[2] = 0;
+	}
+	#endif
+																	/// endcond
+};
+/// ClearPath-SC Alert and Warning Register Type.
+typedef union _cpmAlertReg cpmAlertReg;
+															/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+
+
+//****************************************************************************
+// NAME                                                                      *
+//  cpmTuneConfigReg union
+//
+// DESCRIPTION
+/**
+    \brief ClearPath-SC Tuning Configuration Register Type.
+
+    This register controls various servo performance settings. For example:
+    anti-hunt mode settings are here.
+
+	\note These should be set from ClearView and not programmatically 
+	changed unless directed by Teknic support staff.
+**/
+union PACK_BYTES _cpmTuneConfigReg {
+    /// \brief Antihunt selections
+    typedef enum _antihuntModes {
+        ANTIHUNT_OFF,                       ///<  0 Off
+        ANTIHUNT_STD                        ///<  1 Standard Mode
+    } antihuntModes;                        ///< Anti-hunt modes
+
+    /**
+		\brief Register value as an integer
+
+		Bit-wise representation of the <i>Tuning Configuration Register</i>.
+	**/
+    Uint32 bits;
+
+    // Note: the numbers in the field descriptions denote their bit
+    // range in the register.
+	/** \cond INTERNAL_DOC **/
+	/**
+		\brief ClearPath-SC Tuning Configuration Fields.
+
+		This register controls esoteric features of the various
+		compensators and is generally maintained by ClearView. Programmatic
+		changes should only be made under the advisement of Teknic 
+		support.
+	**/
+    struct _cpmTuneConfigFlds {
+        /**
+			\brief Anti-Hunt Mode selection.
+
+            Anti-Hunt mode select from the #antihuntModes enumeration.
+        **/
+        BFld AntiHunt			: 2;    // 0-1
+													
+        BFld					: 2;    // 2
+													
+        /**
+			\brief Motor's velocity estimator selection.
+
+            Motor's velocity estimator selection.
+        **/
+        BFld MtrVelocityEst     : 3;    // 4-6
+ 													
+        /**
+         	 \brief Don't ask if the load has changed
+
+         	 If not set, prompt the user to verify that the load connected to
+         	 this motor has not changed each time the motor is loaded into MSP
+ 
+			 \note Used by ClearView
+        **/
+        BFld DontAskAboutLoad	: 1;	// 7 
+        /**
+         	 \brief Optimizing is Active
+         	 Motor tuning gains are being modified by the auto-optimize process
+         	 If communication is lost during the process, reset the node.
+
+			 \note Used by ClearView
+         **/
+        BFld AutoTuning			: 1;	// 8
+													
+        /**
+         	 \brief Force Velocity Compensator for stimulus/movegen moves
+         	 Motor tuning gains are being modified by the auto-optimize process
+         	 If communication is lost during the process, reset the node
+         **/
+        BFld UseVelCompInStim	: 1;	// 9
+        /**
+			\brief Track Kp0, Ki0 Gains
+			As Kp-Out and Ki-Out are changed,
+			Kp0 and Ki0 should be changed to match
+
+			\note Used by ClearView
+       **/
+        BFld TrackGains			: 1;	// 10
+        /**
+        	\brief EnableFineTuning
+        	Apply fine tuning scale factors to Kp/Ki and set the target window size
+
+			\note Used by ClearView
+        **/
+        BFld EnableFineTuning	: 1;	// 11
+													
+		BFld 					: 1;	// 12
+													
+        /**
+         	\brief DisableNonLinearGains
+         	Turns off dynamically adjusted position gains based on tracking error
+
+			\note Used by ClearView
+         **/
+        BFld DisableNonLinearGains	: 1;// 13
+		/**
+			\brief Data Collection control
+
+			Clearing these bits will collect data during each move command.
+			This is the typical setting for this feature.
+
+			Setting This field will cause the <i>Data Collection</i>
+			feature to free-run the collection between command calls. This
+			is a special testing mode and generally not of much value
+			for applications.
+		**/
+		BFld DataCollectFreeRunApp	: 1;	// 14 Data collector free runs on App
+													
+		BFld DataCollectFreeRunDiag	: 1;	// 15 Data collector free runs on Diag
+
+		BFld VelocityCompensatorOverride : 1; // 16 Velocity Compensator Override
+													
+    };                               
+	/**
+		\brief ClearPath-SC Field Access for the Tuning Register
+	**/
+	struct _cpmTuneConfigFlds Fld;
+    // For C++ non-firmware usage, include a constructor.
+    #ifdef __cplusplus
+		#ifndef __TI_COMPILER_VERSION__
+													
+		/// Clear bits on construction
+		_cpmTuneConfigReg() {               
+            bits = 0;
+        }
+													
+        #endif
+    #endif
+};
+/// \copybrief _cpmTuneConfigReg
+typedef union _cpmTuneConfigReg cpmTuneConfigReg;
+
+//                                                                            *
+//*****************************************************************************
+
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
+//                      NOT DOCUMENTED ITEMS - BELOW
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
+
+													/** \cond INTERNAL_DOC **/
+
+
+
+//****************************************************************************
+// NAME                                                                      *
+//  cpmOptionRegFlds union
+//
+// DESCRIPTION
+/**
+	\brief ClearPath-SC Option Register Field Definitions.
+
+	This is a factory set register that is used for testing and commissioning
+	ClearPath-SC nodes.
+**/
+struct _cpmOptionRegFlds {
+	/*                   -----------  ----------------------------------- *
+	*                          bit #  description                         *
+	*                    -----------  ----------------------------------- */
+	BFld VoltMode : 1;			// 0:  Volt mode setup
+	BFld RuntimeCal : 1;		// 1:  1=Enable run time calibration
+	BFld ClockCal : 1;			// 2:  1=clock calibration
+	BFld DirCwPositive : 1;		// 3:  1=CW direction is positive motion
+
+	BFld Product : 2;			// 4:  2-bit product number
+								// 5:  ""
+	BFld Advanced : 1;			// 6:  Advanced features available
+	BFld VectorLock : 1;		// 7   Lock Vector Mode
+
+	BFld IndexTolerance : 2;	// 8-9
+	BFld IgnoreIndx : 1;		// 10 Prevent Ref Offset on index
+	BFld NoVectUpdate : 1;		// 11 do not apply the angle from the enhanced 
+								//    sensorless algorithm
+
+	BFld: 4;					// 12-15 <-DO NOT combine these BFld entries!
+	BFld: 3;					// 16-18 <-DO NOT combine these BFld entries!
+	BFld FWverMask : 1;			// 19: Inhibit display of minor FW version
+
+	BFld: 1;					// 20:
+	BFld Vendor : 4;			// 21: Vendor code (LSB)
+								// 22:  0=TEKNIC
+								// 23:
+								// 24: Vendor code (MSB)
+	BFld Debug : 3;				// 25: Debug Mode (LSB)
+								// 26:  0,7=off
+								// 27: Debug Mode (MSB)
+	BFld SensorlessDelaySeed : 3;//  28-30
+};
+/// ClearPath-SC Option Register Field Definitions
+typedef struct _cpmOptionRegFlds cpmOptionsFlds;
+//                                                                            *
+//*****************************************************************************
+
+
+typedef struct _cpmSetFlagsFlds {
+	BFld:1;
+	BFld HardStop : 1;					// 1  Simulate hitting a hard stop
+	BFld HomingReq : 1;					// 2  Request to initiate homing
+	BFld HomingComplete : 1;			// 3  Homing completed manually
+	BFld HomingInvalid : 1;				// 4  Force homing to be invalid
+} cpmSetFlagsFlds;
+
+typedef union _cpmSetFlagsReg {
+	Uint16 bits;
+	cpmSetFlagsFlds fld;
+
+	/// Clear bits on construction
+#ifdef __cplusplus
+#ifndef __TI_COMPILER_VERSION__
+
+	/// Clear bits on construction
+	_cpmSetFlagsReg() {
+		bits = 0;
+	}
+
+#endif
+#endif
+} cpmSetFlagsReg;
+
+												/** \endcond **/
+
+//*****************************************************************************
+// Restore byte packing
+#ifdef _MSC_VER
+#pragma pack(pop)
+#endif
+//*****************************************************************************
+#endif // __PUBCPM_REGS_H__
+//============================================================================= 
+//	END OF FILE pubCpmRegs.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubDataAcq.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubDataAcq.h
new file mode 100644
index 000000000..98d78575c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubDataAcq.h
@@ -0,0 +1,181 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubDataAcq.h $
+// $Revision: 21 $ $Date: 12/09/16 3:46p $
+// $Workfile: pubDataAcq.h $
+//
+/// \file
+/// \brief Link Data Acquisition Interface and types
+//
+// NAME
+//		pubDataAcq.h
+//
+// DESCRIPTION:
+///		
+//
+// CREATION DATE:
+//		9/3/2009 3:53:24 PM
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2009-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+//*****************************************************************************
+
+#ifndef __PUBDATAACQ_H__
+#define __PUBDATAACQ_H__
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubDataAcq.h headers
+	#include "tekTypes.h"
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubDataAcq.h constants
+//
+// scope mode definitions
+typedef enum {
+ 	SCP_OFF  = 0,				 // off
+ 	SCP_MXN  = 1,				 // max/min mode
+ 	SCP_PDR  = 2,				 // point/derivative mode
+ 	SCP_DRATE  = 3				 // double sample rate mode
+} scopemode;
+
+typedef enum _dacqSTATES {
+	DACQ_STATE_IDLE_DONE=0,
+	DACQ_STATE_NEG_IN	 =1,
+	DACQ_STATE_SETTLING =2,
+	DACQ_STATE_POS_IN	 =3,
+	DACQ_STATE_NEG_OUT	 =5,
+	DACQ_STATE_OUT_RANGE=6,
+	DACQ_STATE_POS_OUT	 =7
+} dacqSTATES;
+
+typedef enum _dacqEXCPS {
+	DACQ_EXCP_ENABLED		=	0,      // 00 Drive Enabled
+	DACQ_EXCP_VOLT_SAT		=	2,      // 02 Voltage Saturation
+	DACQ_EXCP_TRQ_SAT		=	3,      // 03 Torque Saturation
+	DACQ_EXCP_TRQ_VOLT_SAT	=	4,      // 04 Torque and Voltage Sat
+	DACQ_EXCP_OVER_SPEED	=	6,      // 06 Over-Speed
+	DACQ_EXCP_HARD_STOP		=	7,      // 07 Hard Stop asserted
+	DACQ_EXCP_POS_LIMIT		=	8,      // 08 Positive Limit asserted
+	DACQ_EXCP_NEG_LIMIT		=	9,      // 09 Negative Limit asserted
+	DACQ_EXCP_SHUTDOWN_ENBL	=	13,     // 13 Shutdown/enable asserted
+	DACQ_EXCP_DISABLE		=	14,     // 14 Disabled
+	DACQ_EXCP_LPB			=	15     	// 15 In LPB / Low Bus Voltage
+} dacqEXCPS;
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubDataAcq.h types 
+//
+// 4 octet return packet via the communications link
+#define P0_BITS		11			// # of bits in channel 0
+#define P1_BITS		11			// # of bits in channel 1
+#define P0LSB_BITS	6			// # of bits in channel 0 LSB field
+#define P1LSB_BITS	3			// # of bits in channel 1 LSB field
+#define INPUT_BITS	3			// # of bits of input
+
+typedef union _dacqPacket {
+	nodechar bits[6];				// Uses 6*8 bits of this buffer
+	struct {
+#ifdef __TI_COMPILER_VERSION__
+		unsigned Sequence	: 2;	// Sequence indicator
+		int		 T0p0LSBs	:P0LSB_BITS; // LSBs of Trace 0, point 0
+		int	nc0				: 8;	// Force word alignment
+
+		int		 T0p0MSBs	: 5;	// MSBs of Trace 0, point 0
+		int		 T0p1LSBs	:P1LSB_BITS; // LSBs of Trace 0, point 1
+		int	nc1				: 8;	// Force word alignment
+
+		int		 T0p1MSBs	: 8;	// MSBs of Trace 0, point 1
+		int	nc2				: 8;	// Force word alignment
+
+		unsigned MoveState0 : 3;	// Move state code
+		unsigned Trigger0	: 1;
+		unsigned Exception0	: 4;	// Exception code
+		int	nc4				: 8;		// Force word alignment
+
+		unsigned MoveState1 : 3;	// Move state code
+		unsigned Trigger1	: 1;
+		unsigned Exception1	: 4;	// Exception code
+		int	nc6				: 8;	// Force word alignment
+
+		unsigned Inputs0	: INPUT_BITS;	// Inputs - sample 0
+		unsigned Output0	: 1;	// Output - sample 0
+		unsigned Inputs1	: INPUT_BITS;	// Inputs - sample 1
+		unsigned Output1	: 1;	// Output - sample 1
+		int	nc8				: 8;	// Force word alignment
+#else
+		unsigned Sequence	: 2;	// Sequence indicator
+		int		 T0p0		:P0_BITS;	// Trace 0, point 0
+		int		 T0p1		:P1_BITS;	// Trace 0, point 1
+
+		unsigned MoveState0  : 3;	// Move state code
+		unsigned Trigger0	: 1;	// Trigger seen?
+		unsigned Exception0	: 4;	// Exception code
+
+		unsigned MoveState1 : 3;	// Move state code
+		unsigned Trigger1	: 1;	// Trigger seen?
+		unsigned Exception1	: 4;	// Exception code
+
+		unsigned Inputs0	: INPUT_BITS;	// Inputs - sample 0
+		unsigned Output0	: 1;	// Output - sample 0
+		unsigned Inputs1	: INPUT_BITS;	// Inputs - sample 1
+		unsigned Output1	: 1;	// Output - sample 1
+#endif
+
+//		unsigned nc			: 2;	// Move state code
+//		int		 T1p0		:DP0_BITS;	// Trace 1, point 0
+//		int		 T1p1		:DP1_BITS;	// Trace 1, point 1
+	} Fld;
+} dacqPacket;
+
+//																			  *
+//*****************************************************************************
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// User/sw driver accessible point structure
+//  NOTE: The ordering of the members must remain this way or the TekNetLib
+//        will cause crashes.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+typedef struct _mnDataAcqPt {
+    double TimeStamp;			// Time stamp (msec.)
+    float TraceValue[4];		// Normalized trace values (-1 .. 0.9999)
+    nodeulong MoveState;		// State information (dacqSTATES type)
+    nodeulong Exception;        // Exception state (dacqEXCPS type)
+	nodeushort Sequence;		// Sequencing check
+	nodebool Bool0;				// Spare
+    nodebool Bool1;				// Spare
+	nodebool Valid;				// Data gap
+    nodelong Spare[2];			// (unused) Future expansion/padding
+#ifdef __cplusplus
+    _mnDataAcqPt() {
+    	TimeStamp = 0;
+    	TraceValue[0] = TraceValue[1] = TraceValue[2] = TraceValue[3] = 0;
+    	MoveState = Exception = Sequence = 0;
+    	Bool0 = Bool1 = Valid = false;
+    	Spare[0] = Spare[1] = 0;
+    }
+#endif
+} mnDataAcqPt;
+
+#endif // __PUBDATAACQ_H__
+
+//=============================================================================
+//	END OF FILE mnDataAcq.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIQmath.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIQmath.h
new file mode 100644
index 000000000..2a4a7ced2
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIQmath.h
@@ -0,0 +1,86 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubIQmath.h $
+// $Revision: 3 $ $Date: 12/09/16 3:55p $
+// $Workfile: pubIQmath.h $
+//
+// DESCRIPTION:
+///		\file pubIQmath.h
+///		\brief C++ API: definitions for pubIQmathcpp
+///
+///		IQ Math Public definitions.
+//
+// CREATION DATE:
+//		06/10/2009 12:13:00
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2009-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+#ifndef __IQMATHLIB_H_INCLUDED__
+#ifndef _pubIQmath_h
+#define _pubIQmath_h
+
+//*****************************************************************************
+// !NAME!																      *
+// 	pubIQmath.h headers included
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// !NAME!																	  *
+// 	pubIQmath.h definitions
+//
+
+// Fixed point definitions
+typedef   long    _iq;
+typedef   long    _iq30;
+typedef   long    _iq29;
+typedef   long    _iq28;
+typedef   long    _iq27;
+typedef   long    _iq26;
+typedef   long    _iq25;
+typedef   long    _iq24;
+typedef   long    _iq23;
+typedef   long    _iq22;
+typedef   long    _iq21;
+typedef   long    _iq20;
+typedef   long    _iq19;
+typedef   long    _iq18;
+typedef   long    _iq17;
+typedef   long    _iq16;
+typedef   long    _iq15;
+typedef   long    _iq14;
+typedef   long    _iq13;
+typedef   long    _iq12;
+typedef   long    _iq11;
+typedef   long    _iq10;
+typedef   long    _iq9;
+typedef   long    _iq8;
+typedef   long    _iq7;
+typedef   long    _iq6;
+typedef   long    _iq5;
+typedef   long    _iq4;
+typedef   long    _iq3;
+typedef   long    _iq2;
+typedef   long    _iq1;
+//																			  *
+//*****************************************************************************
+
+
+#endif
+#endif
+
+//============================================================================= 
+//	END OF FILE pubIQmath.h
+// ============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIex.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIex.h
new file mode 100644
index 000000000..d0a5ee140
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIex.h
@@ -0,0 +1,145 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubIex.h $
+// $Revision: 16 $ $Date: 12/09/16 3:53p $
+// $Workfile: pubIex.h $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief IEX constants and data types.
+
+	The IEX programming interface consists of an <i>IEX Status Register</i>
+	and a number of enumerated constants. The status register allows
+	the user application to evaluate the status and reliability of the 
+	IEX modules and their wiring.
+**/
+// CREATION DATE:
+//		9/13/2010 08:16:15 AM
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2010-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+//*****************************************************************************
+#ifndef __PUBIEX_H__
+#define __PUBIEX_H__
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubIex.h headers
+//
+	#include "tekTypes.h"
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubIex.h function prototypes
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+/**
+	\brief IEX Link Operational State
+
+	The status register maintains the IEX subsystem's operational state
+	via these enumerated constants.
+**/
+typedef enum _iexLinkState {
+	/// Searching for IEX module(s)
+	IEX_LINK_SEARCH,				// 0	
+	/// Power stability wait
+	IEX_LINK_WAIT,					// 1 
+	/// Testing IEX modules
+	IEX_LINK_TEST,					// 2 
+	/// Modules online working
+	IEX_LINK_ONLINE,				// 3 
+	/// Module link broken
+	IEX_LINK_BROKEN,				// 4 
+	/// IEX modules stopped
+	IEX_LINK_STOPPED				// 5 
+} iexLinkState;	///< A typename for enum _iexLinkState
+
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+/**
+	\brief IEX Status Register. 
+
+	This information is returned by the device's IEX status parameter. It
+	contains the operational status and quality of the IEX subsytem. The
+	glitch registers will be non-zero when there is poor cabling or extreme
+	levels of electromagnetic interference on the IEX link.
+**/
+#ifdef DOXYGEN_SCAN
+typedef union _iexStatusReg {
+#else
+typedef PACK_BYTES union _iexStatusReg {
+#endif
+	/// This is the bit-wise interface
+	Uint16 bits[4];					
+	/// This is the field access to the status information
+	struct {
+		/** \brief Count of IEX devices found.
+
+		This field contains the number of detected IEX modules attached
+		to this node.
+		**/
+		unsigned deviceCnt			: 3;	// 0-2
+		/** \brief IEX not configured properly.
+		
+		The detected count of IEX modules does not match the expected count
+		or too many IEX modules were detected on the expansion link.
+		**/
+		unsigned configWarning		: 1;	// 3
+		/** \brief IEX Operational state.
+		
+		This field contains the operational state of the IEX system. 
+		Interactions when the link is not in the IEX_LINK_ONLINE state
+		will return an error.
+		**/
+		iexLinkState state			: 4;	// 4-7
+		// reserved
+		unsigned na8_15				: 8;	// 8-15
+		/** \brief Count of glitches detected.
+
+		This field will contain the count of link glitches detected since
+		the last read. It clears on read. Excessive errors will cause this
+		field to saturate at 32767.
+		**/
+		unsigned glitchCount		: 16;	// 16-31
+		/** \brief Maximum count of consecutive glitches.
+		
+		This field will contain the highest count of sequential link glitches
+		detected since the last read. It clears on read. Excessive errors will
+		cause this field to saturate at 32767.
+		**/
+		unsigned glitchPeak			: 16;	// 32-47
+		// reserved
+		Uint16	 spare;						// 48-63
+	} Fld;									///< Field access to IEX status register
+} iexStatusReg;								///< IEX Status Register Type
+//																			  *
+//*****************************************************************************
+
+#endif //__PUBIEX_H__
+// =============================================================================
+//	END OF FILE pubIex.h
+// =============================================================================
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIscAPI.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIscAPI.h
new file mode 100644
index 000000000..94ed31ce9
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIscAPI.h
@@ -0,0 +1,354 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubIscAPI.h $
+// $Revision: 26 $ $Date: 12/09/16 3:57p $
+// $Workfile: pubIscAPI.h $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief Function prototypes and constants related to the Meridian/ISC
+	emulation API.
+
+	\ingroup ISCgrp
+	@{
+
+**/
+// CREATION DATE:
+//		6/9/2009 refactored for Meridian
+//		2/10/2003 originally iscCmdsAPI.h
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//                                                                            *
+//*****************************************************************************
+
+#ifndef __PUBISCAPI_H
+#define __PUBISCAPI_H
+
+#include "pubIscRegs.h"
+#include "mnParamDefs.h"
+#include "pubCoreRegs.h"
+
+ //#include "mnParamDefs.h"
+ //#include "pubMotion.h"
+#include "pubIex.h"
+
+//////////////////////
+// PUBLIC FUNCTIONS	//
+//////////////////////
+
+/// Helper function to convert volatile parameter access reference into
+/// a non-volatile parameter access.
+inline iscParams iscNonVol(iscParams volParam) {
+	return((iscParams)(volParam|PARAM_OPT_MASK));
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Restore the parameters to factory default state
+MN_EXPORT cnErrCode MN_DECL iscFactoryDefaults(
+			multiaddr theMultiAddr);	    // Destination node
+
+// Get parameter value from the local parameter table or node
+MN_EXPORT cnErrCode MN_DECL iscGetParameter(
+			multiaddr theMultiAddr,		// Node address
+			iscParams theParam,			// Parameter index
+			double *pParamVal);			// Ptr to value area
+
+MN_EXPORT cnErrCode MN_DECL iscGetParameterEx(
+			multiaddr theMultiAddr,		// Node address
+			iscParams theParam,			// Parameter index
+			paramValue *pParamVal,		// Ptr to value area
+			paramInfo *pParamInfo);		// Ptr to information area
+
+// Update the local parameter table and update node
+MN_EXPORT cnErrCode MN_DECL iscSetParameter(
+			multiaddr theMultiAddr,	 	// Node address
+			iscParams theParam,			// Parameter index
+			double paramVal);			// New value
+
+// Update the local parameter table and update node using a buffer
+MN_EXPORT cnErrCode MN_DECL iscSetParameterEx(
+			multiaddr theMultiAddr,		// Node address
+			iscParams theParam,			// Parameter index
+			packetbuf *pNewValue);		// New value
+			
+
+// Add to position command
+MN_EXPORT cnErrCode MN_DECL iscAddToPosition(
+			multiaddr theMultiAddr,		// Node address
+			double theOffset);			// Offset from current location
+
+// Add to position command, load encoder
+MN_EXPORT cnErrCode MN_DECL iscAddToPositionLd(
+			multiaddr theMultiAddr,		// Node address
+			double theOffset);			// Offset from current location
+
+// Synchronize position
+MN_EXPORT cnErrCode MN_DECL iscSyncPosition(
+			multiaddr theMultiAddr);	// Node address
+
+// Register parameter change function
+MN_EXPORT paramChangeFunc MN_DECL iscParamChangeFunc(
+	  		paramChangeFunc newFunc);	// Ptr to callback function
+
+// Macro commands - these all block until completion
+
+MN_EXPORT cnErrCode MN_DECL iscSetUserOutputReg (
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg newState);		// New setting
+MN_EXPORT cnErrCode MN_DECL iscGetUserOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetOutputRiseReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetOutputFallReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg);		// Current setting
+
+// Status Register Access		
+MN_EXPORT cnErrCode MN_DECL iscGetStatusAccumReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetAttnStatusRiseReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetStatusFallReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetStatusRTReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus);		// Current setting
+
+// Attention Generation Setup
+MN_EXPORT cnErrCode MN_DECL iscGetAttnMask(
+			multiaddr theMultiAddr,		// Node address
+			attnReg *pAttnMask);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscSetAttnMask(
+			multiaddr theMultiAddr,		// Node address
+			attnReg *pAttnMask);		// Current setting
+
+// Alert and Warning Register Access with mask registers
+MN_EXPORT cnErrCode MN_DECL iscGetAlertReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pAlertReg);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetAlertMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pAlertMask);		// Get current setting
+MN_EXPORT cnErrCode MN_DECL iscSetAlertMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pAlertMask);		// New setting
+
+
+MN_EXPORT cnErrCode MN_DECL iscGetWarningReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pWarningReg);		// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetWarningMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pWarningMask);		// Get current setting
+MN_EXPORT cnErrCode MN_DECL iscSetWarningMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pWarningMask);		// New setting
+
+
+
+// Configuration Registers
+MN_EXPORT cnErrCode MN_DECL iscSetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscHwConfigReg hwConfigReg);	// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscHwConfigReg *pHwConfigReg);	// Current setting
+
+MN_EXPORT cnErrCode MN_DECL iscSetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscAppConfigReg appConfigReg);	// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscAppConfigReg *pAppConfigReg);	// Current setting
+
+MN_EXPORT cnErrCode MN_DECL iscSetTuneConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscTuneConfigReg tuneConfigReg);	// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetTuneConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscTuneConfigReg *pTuneConfigReg);	// Current setting
+
+MN_EXPORT cnErrCode MN_DECL iscSetLdMtrRatio(
+			multiaddr theMultiAddr,			// Node address
+			nodelong loadPart,
+			nodelong motorPart);			// Current setting
+MN_EXPORT cnErrCode MN_DECL iscGetLdMtrRatio(
+			multiaddr theMultiAddr,			// Node address
+			nodelong *pLoadPart,
+			nodelong *pMotorPart);			// Current setting
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//								 MOTION API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+
+// Constraint short cuts
+MN_EXPORT cnErrCode MN_DECL iscGetJerkTime(
+			multiaddr theMultiAddr,
+			double *pSettingValMS); 
+MN_EXPORT cnErrCode MN_DECL iscSetJerkTime(
+			multiaddr theMultiAddr,
+			double newValMS);
+
+
+//-----------------
+// Velocity Group
+//-----------------
+// Low level command primitive
+MN_EXPORT cnErrCode MN_DECL iscForkMoveVelEx(
+			multiaddr theMultiAddr,		// Node address
+			double velTargetStepPerSec,	// Velocity (steps/sec)
+			nodelong positionTarget,	// Target Position (optional)
+			mgVelStyle moveType);		// Motion style
+
+MN_EXPORT cnErrCode MN_DECL iscForkMoveVelQueued(
+			multiaddr theMultiAddr,		// Node address
+			double velTargetStepPerSec,	// Velocity (steps/sec)
+			nodelong positionTarget,	// Target Position (optional)
+			mgVelStyle moveType,		// Motion style
+			nodelong *pBuffersRemaining);	// Ptr to move buf remaining cnt
+
+// Change axis to new velocity target / optional trigger
+MN_EXPORT cnErrCode MN_DECL iscForkVelMove(
+			multiaddr theMultiAddr,		// Destination node
+			double velTargetStepPerSec,	// Target velocity (steps/sec)
+			nodebool triggered);		// Start move with trigger
+
+// Change axis to new velocity target with script buffer management
+MN_EXPORT cnErrCode MN_DECL iscForkVelMoveBuffered(
+			multiaddr theMultiAddr,		// Destination node
+			double velTargetStepPerSec,	// Target velocity (steps/sec)
+			nodelong positionTarget,	// Target Position (optional)
+			mgVelStyle moveType);		// Motion style
+
+MN_EXPORT cnErrCode MN_DECL iscForkSkylineMove(
+			multiaddr theMultiAddr,			// The node
+			double velTargetStepPerSec,		// Target velocity (steps/sec)
+			nodelong positionSpec,			// Position Target [optional]
+			mgVelStyle moveType,			// Enhanced style selection
+			nodelong *pBuffersRemaining);	// Ptr to move buf remaining cnt
+
+//-----------------
+// Positional Group
+//-----------------
+// Low level command primitive 
+MN_EXPORT cnErrCode MN_DECL iscForkMoveEx(
+			multiaddr theMultiAddr,		// Destination node
+			nodelong posnTarget,		// Distance (steps)
+			mgPosnStyle moveType);		// Motion style
+
+// Low level command primitive (>=v5.5 / buffer remaining)
+MN_EXPORT cnErrCode MN_DECL iscForkMoveQueued( 
+			multiaddr theMultiAddr,		// Destination node
+			nodelong posnTarget,		// Distance (steps)
+			mgPosnStyle moveType,		// Motion style
+			nodelong *pBuffersRemaining);	// Ptr to move buf remaining cnt		
+
+// Initiate positional motion with script buffer management.
+MN_EXPORT cnErrCode MN_DECL iscForkMoveExBuffered(
+			multiaddr theMultiAddr,		// Destination node
+			nodelong posnTarget,			// Distance (steps)
+			mgPosnStyle moveType);		// Motion style
+
+// Compatibility with ControlPoint 
+MN_EXPORT cnErrCode MN_DECL iscMoveProfiled(
+			multiaddr theMultiAddr,		// Destination node
+			mgMoveProfiledInfo *spec);	// Motion specification
+MN_EXPORT cnErrCode MN_DECL iscMoveProfiledQueued(
+			multiaddr theMultiAddr,		// Destination node
+			mgMoveProfiledInfo *spec,	// Motion specification
+			nodelong *pBuffersRemaining);	// Ptr to move buf remaining cnt
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						   NODE IDENTIFICATION API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Set/Get the user ID
+MN_EXPORT cnErrCode MN_DECL iscSetUserID(
+			multiaddr theMultiAddr,
+			const char *pNewName);
+
+MN_EXPORT cnErrCode MN_DECL iscGetUserID(
+			multiaddr theMultiAddr,
+			char *pUserIdStr,
+			Uint16 maxBufSize);
+// Set/Get Motor File Name
+MN_EXPORT cnErrCode MN_DECL iscSetMotorFileName(
+			multiaddr theMultiAddr,
+			const char *pNewName);
+
+MN_EXPORT cnErrCode MN_DECL iscGetMotorFileName(
+			multiaddr theMultiAddr,
+			char *pMotorFileNameStr,
+			Uint16 maxBufSize);
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						  MONITOR PORT/DATA ACQUISITION API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Monitor port manipulations
+MN_EXPORT cnErrCode MN_DECL iscGetMonitor(
+			multiaddr theMultiAddr,			// Target node addr
+			nodeushort channel,				// Target monitor port if supported
+			iscMonState *pState);
+
+MN_EXPORT cnErrCode MN_DECL iscSetMonitor(
+			multiaddr theMultiAddr,			// Target node addr
+			nodeushort channel,				// Target monitor port if supported
+			iscMonState *pNewState);
+
+MN_EXPORT cnErrCode MN_DECL iscGetDataCollected(
+			multiaddr theMultiAddr,			// Destination node
+			iscDataCollect *pReturnData);	// Returned data
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						  IEX API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+MN_EXPORT cnErrCode MN_DECL iscGetIEXStatus(
+			multiaddr theMultiAddr,
+			iexStatusReg *pIexStatus);
+
+MN_EXPORT cnErrCode MN_DECL iscRestartIEX(
+			multiaddr theMultiAddr);
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+//						     TUNING STIMULUS API
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+MN_EXPORT cnErrCode MN_DECL iscGetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pState);
+
+MN_EXPORT cnErrCode MN_DECL iscSetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pNewState);
+
+// Reset the vector search flag
+MN_EXPORT cnErrCode MN_DECL iscReVector(
+			multiaddr theMultiAddr);	// Target node addr
+
+#ifdef __cplusplus
+}
+#endif
+/// @}
+
+#endif // __ISCCMDSAPI_H
+
+
+
+/*========================================================================== 
+	END OF FILE iscCmdsAPI.h
+  ==========================================================================*/
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIscRegs.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIscRegs.h
new file mode 100644
index 000000000..726706680
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubIscRegs.h
@@ -0,0 +1,2937 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/inc/pubIscRegs.h $
+// $Revision: 104 $ $Date: 12/13/16 12:15p $
+// $Workfile: pubIscRegs.h $
+//
+// DESCRIPTION:
+//
+/**
+    \file
+    \brief Register definitions and constants related to the Meridian ISC.
+
+    This header file describes the register set and parameters used by the ISC.
+
+
+    \ingroup ISCgrp
+    @{
+**/
+//		The ISC registers are defined with an extra layer for backwards compatibility
+//		with the existing code base.
+//
+// CREATION DATE:
+//      03/13/1998 13:29:19
+//
+// COPYRIGHT NOTICE:
+//      (C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//      This copyright notice must be reproduced in any copy, modification,
+//      or portion thereof merged into another program. A copy of the
+//      copyright notice must be included in the object library of a user
+//      program.
+//                                                                            *
+//*****************************************************************************
+
+
+#ifndef _PUBISCREGS_H_
+#define _PUBISCREGS_H_
+
+//*****************************************************************************
+// NAME                                                                       *
+//  pubIscRegs.h headers
+//
+#include "tekTypes.h"
+#include "pubMnNetDef.h"
+#include "pubRegFldCommon.h"
+#ifndef __TI_COMPILER_VERSION__     // Not needed on dsp
+#include "pubMotion.h"
+
+#include "pubMonPort.h"
+#endif
+
+
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  pubIscRegs.h constants
+//
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+    \brief ISC Parameter Numbers.
+    \public
+
+    This enumeration defines the set of internal ISC registers accessible by
+    the #iscGetParameter and #iscSetParameter functions.
+**/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+enum _iscParams {
+    ISC_P_NODEID,                   // 0  00 Device ID
+    ISC_P_FW_VERSION,               // 1  01 FW version
+    ISC_P_HW_VERSION,               // 2  02 HW version
+    ISC_P_RESELLER_ID,              // 3  03 Reseller ID
+    ISC_P_SER_NUM,                  // 4  04 Unit serial number
+    ISC_P_OPTION_REG,               // 5  05 Unit options
+    ISC_P_ROM_SUM_ACK,              // 6  06 Firmware update ack
+    ISC_P_ROM_SUM,                  // 7  07 Firmware checksum
+    ISC_P_SAMPLE_PERIOD,            // 8  08 Sample period (nsec)
+    ISC_P_ALERT_REG,                // 9  09 Shutdown register
+    ISC_P_STOP_TYPE,                // 10 0a Node Stop Type
+    ISC_P_WATCHDOG_TIME,            // 11 0b Watchdog time constant
+    ISC_P_NET_STAT,                 // 12 0c Network Status
+    ISC_P_STATUS_ACCUM_REG,         // 13 0d Status accum register
+    ISC_P_STATUS_ATTN_RISE_REG,     // 14 0e Status attn/rise register
+    ISC_P_STATUS_ATTN_MASK,         // 15 0f Status mask register
+    ISC_P_STATUS_RT_REG,            // 16 10 Status reg (realtime)
+    ISC_P_TIMESTAMP,                // 17 11 8-bit timestamp
+    ISC_P_TIMESTAMP16,              // 18 12 16-bit timestamp
+    ISC_P_PART_NUM,                 // 19 13 Part Number String
+    ISC_P_EE_UPD_ACK,               // 20 14 EE Update Acknowlegde
+    ISC_P_EE_VER,                   // 21 15 EE Version Number
+    ISC_P_STATUS_FALL_REG,          // 22 16 Status fall register
+    ISC_P_HW_CONFIG_REG,            // 23 17 Hardware config/setup reg
+    ISC_P_APP_CONFIG_REG,           // 24 18 Feature config/setup reg
+                                    // 25 19
+                                    // 26 1a
+                                    // 27 1b
+                                    // 28 1c
+                                    // 29 1d
+    ISC_P_USER_IN_REG=30,           // 30 1e User input value
+    ISC_P_IN_SRC_REG,               // 31 1f Input source
+    ISC_P_OUT_REG,                  // 32 20 Output register
+    ISC_P_OUT_RISE_REG,             // 33 21 Output rise edge
+    ISC_P_OUT_FALL_REG,             // 34 22 Output fall edge
+    ISC_P_CTL_STOP_OUT_REG,         // 35 24 Controlled output register
+    ISC_P_USER_OUT_REG,             // 36 23 User output register
+    ISC_P_OUT_PLA_SRC_REG,          // 37 25 Output source definition
+    ISC_P_GP_TIMER_PERIOD,          // 38 26 Gen. purpose timer period
+    ISC_P_PLA_OUT_REG,              // 39 27 PLA output
+    ISC_P_IN_POLARITY_REG,          // 40 28 Input polarity register
+                                    // 41 29
+    ISC_P_POSN_CAP_INDEX=42,        // 42 2a Encoder index position
+    ISC_P_POSN_CAP_GPI1,            // 43 2b Encoder capture with GPI1
+    ISC_P_POSN_CAP_PLA,             // 44 2c Encoder capture with PLA
+    ISC_P_POSN_CAP_INDEX_LD,        // 45 2d Load Encoder index position
+    ISC_P_RAS_MAX_VELOCIY,          // 46 2e Maximum velocity for current RAS
+    ISC_P_VEL_LIM=47,               // 47 2f Trapezoidal velocity limit
+    ISC_P_ACC_LIM,                  // 48 30 Trapezoidal acceleration limit
+    ISC_P_JERK_LIM,                 // 49 31 Jerk limit
+    ISC_P_ACC_MAX,                  // 50 32 Test Point: Max Acc.
+    ISC_P_POSN_TRIG_PT,             // 51 33 At Position location
+    ISC_P_A_START,                  // 52 34 A after start point
+    ISC_P_B_END,                    // 53 35 B before end point
+    ISC_P_POSN_TRK_RANGE,           // 54 36 Tracking in range window
+                                    // 55 37
+    ISC_P_POSN_TRK=56,              // 56 38 Position tracking error
+                                    // 57 39
+                                    // 58 3a
+    ISC_P_STOP_ACC_LIM = 59,        // 59 3b Stop acceleration limit
+    ISC_P_POSN_MEAS_MTR,			// 60 3c Encoder 0 (motor) measured position
+    ISC_P_POSN_MEAS = 61,           // 61 3d Measured position
+    ISC_P_POSN_CMD,                 // 62 3e Commanded position
+    ISC_P_VEL_CMD,                  // 63 3f Commanded velocity
+    ISC_P_VEL_MEAS,                 // 64 40 Measured velocity
+    ISC_P_DEC_LIM,                  // 65 41 Deceleration Limit
+    ISC_P_HEAD_DISTANCE,            // 66 42 Head distance
+    ISC_P_TAIL_DISTANCE,            // 67 43 Tail distance
+    ISC_P_HEADTAIL_VEL,             // 68 44 Head/Tail velocity
+    ISC_P_POSN_MEAS_LD,             // 69 45 Encoder 1 measured position
+    ISC_P_WARN_REG,                 // 70 46 Warnings pending
+    ISC_P_WARN_MASK,                // 71 47 Warnings for attention
+    ISC_P_ALERT_MASK,               // 72 48 Alert selection
+									// 73 49
+	ISC_P_MOVE_DWELL = 74,			// 74 4a Post move dwell time (sec)
+
+    ISC_P_ON_TIME = 89,             // 89 59 Unit On Time
+    ISC_P_USER_RAM0,                // 90 5a User RAM parameter
+    ISC_P_USER_DATA_NV0,            // 91 5b User NV (13-bytes)
+    ISC_P_USER_DATA_NV1,            // 92 5c User NV (13-bytes)
+    ISC_P_USER_DATA_NV2,            // 93 5d User NV (13-bytes)
+    ISC_P_USER_DATA_NV3,            // 94 5e User NV (13-bytes)
+
+    ISC_P_NETERR_APP_CHKSUM=104,    // 104 68 Application Net Checksum counter
+    ISC_P_NETERR_APP_FRAG,          // 105 69 Application Net Fragment counter
+    ISC_P_NETERR_APP_STRAY,         // 106 6a Application Net Stray data counter
+    ISC_P_NETERR_APP_OVERRUN,       // 107 6b Application Net Overrun counter
+    ISC_P_NETERR_DIAG_CHKSUM,       // 108 6c Diagnostic Net Checksum counter
+    ISC_P_NETERR_DIAG_FRAG,         // 109 6d Diagnostic Net Fragment counter
+    ISC_P_NETERR_DIAG_STRAY,        // 110 6e Diagnostic Net Stray data counter
+    ISC_P_NETERR_DIAG_OVERRUN,      // 111 6f Diagnostic Net Overrun counter
+    ISC_P_NETERR_LOW_VOLTS=116,     // 116 74 Link Voltage Low Event counter
+
+    // BANK 1 items (Drive/Motor Configuration)
+                                    // 256 00
+    ISC_P_DRV_I_MAX=257,            // 257 01 Current Full Scale (A)
+    ISC_P_DRV_RMS_MAX,              // 258 02 Factory RMS limit
+    ISC_P_DRV_FACT_IR_CAL,          // 259 03 Ir Sensor Calibration
+    ISC_P_DRV_FACT_IS_CAL,          // 260 04 Is Sensor Calibration
+                                    // 261 05
+    ISC_P_DRV_ADC_MAX=262,          // 262 06 ADC full scale (A)
+    ISC_P_DRV_CONFIG_CHANGED,       // 263 07 Configuration changed
+    ISC_P_DRV_VECTOR_RATE,          // 264 08 Encoder Dens. (/[turn/pole-pair])
+    ISC_P_DRV_USTEPS_PER_REV,       // 265 09 Stepper uSteps (/[turn/pole-pair])
+    ISC_P_DRV_ENC_DENS,             // 266 0a Encoder Dens. (/[turn/pole-pair])
+    ISC_P_DRV_ENC_RES,              // 267 0b Encoder step distance (microns/.01)
+    ISC_P_DRV_MTR_POLES,            // 268 0c Motor Pole Count
+    ISC_P_DRV_MTR_KE,               // 269 0d Motor: Ke (V/KRPM)
+    ISC_P_DRV_MTR_OHMS,             // 270 0e Motor: Resistance (ohm)
+    ISC_P_DRV_MTR_ELEC_TC,          // 271 0f Motor: Elect Time Constant (ms)
+    ISC_P_DRV_COM_RO,               // 272 10 Commutation Reference Offset
+    ISC_P_DRV_RMS_LIM,              // 273 11 RMS shutdown limit (A)
+    ISC_P_DRV_RMS_TC,               // 274 12 RMS time constant (sec) @ 100% trq
+    ISC_P_DRV_MTR_SPEED_LIM,        // 275 13 Motor Speed Limit (quads/msec)
+    ISC_P_DRV_COM_CAP,              // 276 14 Commutation Edge Capture
+    ISC_P_DRV_COM_ANGLE,            // 277 15 Commutation Angle Reference (quads)
+    ISC_P_DRV_KIP,                  // 278 16 Vector Torque: Kip
+    ISC_P_DRV_KII,                  // 279 17 Vector Torque: Kii
+    ISC_P_DRV_LD_SPEED_LIM,         // 280 18 Load Speed Limit (quads/msec)
+    ISC_P_DRV_KPL,                  // 281 19 Compensator: Kpl
+    ISC_P_DRV_KV,                   // 282 1a Compensator: Kv
+    ISC_P_DRV_KP,                   // 283 1b Compensator: Kp
+    ISC_P_DRV_KI,                   // 284 1c Compensator: Ki
+    ISC_P_DRV_KFV,                  // 285 1d Compensator: Kfv
+    ISC_P_DRV_KFA,                  // 286 1e Compensator: Kfa
+    ISC_P_DRV_KFJ,                  // 287 1f Compensator: Kfj (jerk ff)
+    ISC_P_DRV_KFF,                  // 288 20 Compensator: Kff (fric. ff)
+    ISC_P_DRV_KNV,                  // 289 21 Compensator: Knv
+    ISC_P_DRV_AHFUZZ2,              // 290 22 Compensator: Antihunt 2
+    ISC_P_DRV_TRQ_BIAS,             // 291 23 Compensator: Torque Bias (A)
+    ISC_P_DRV_FUZZY_APERTURE,       // 292 24 Fuzzy Aperture
+    ISC_P_DRV_FUZZY_HYST,           // 293 25 Fuzzy Hystersis
+    ISC_P_DRV_FAN_SPEED,            // 294 26 Drive Fan Speed (RPM)
+    ISC_P_DRV_FAN_WARN_SPEED,       // 295 27 Drive Fan Warning Min Speed (RPM)
+    ISC_P_TRK_ERR_MAX=296,          // 296 28 Accumulated maximum error
+    ISC_P_TRK_ERR_MIN,              // 297 29 Accumulated minimum error
+    ISC_P_AH_HOLDOFF,               // 298 2A Anti-hunt holdoff
+    ISC_P_DRV_LD_MTR_RATIO,         // 299 2B Load to motor encoder ratio
+                                    // 300 2C
+    ISC_P_DRV_TUNE_CONFIG_REG=301,  // 301 2D
+    ISC_P_DRV_SENSORLESS_RAMPUP_TIME,//302 2E Sensorless start torque rampup time (ms)
+    ISC_P_DRV_SENSORLESS_SWEEP_TIME,// 303 2F Sensorless start angle sweep time (ms)
+    ISC_P_DRV_SENSORLESS_SETTLE_TIME,//304 30 Sensorless start settle time (ms)
+    ISC_P_DRV_SENSORLESS_TRQ,       // 305 31 Sensorless start torque
+    ISC_P_DRV_HARDSTOP_ENTRY_SPD,   // 306 32 Hard-stop speed qualifier
+    ISC_P_DRV_TRQ_LIM,              // 307 33 Torque Limit  (A)
+    ISC_P_DRV_POS_FLDBK_TRQ,        // 308 34 + Torque foldback limit (A)
+    ISC_P_DRV_POS_FLDBK_TRQ_TC,     // 309 35 + Torque foldback time const (ms)
+    ISC_P_DRV_NEG_FLDBK_TRQ,        // 310 36 - Torque foldback limit (A)
+    ISC_P_DRV_NEG_FLDBK_TRQ_TC,     // 311 37 - Torque foldback time const (ms)
+    ISC_P_DRV_HARDSTOP_FLDBK_TRQ,   // 312 38 Hardstop foldback limit (A)
+    ISC_P_DRV_HARDSTOP_FLDBK_TRQ_TC,// 313 39 Hardstop foldback time const (ms)
+    ISC_P_DRV_MOVEDONE_FLDBK_TRQ,   // 314 3a Move Done Foldback Limit (A)
+    ISC_P_DRV_MOVEDONE_FLDBK_TRQ_TC,// 315 3b Move Done Foldback time const (ms)
+    ISC_P_DRV_HARDSTOP_ENTRY_TRQ,   // 316 3c Foldback Torque Trip Level (A)
+    ISC_P_DRV_HARDSTOP_ENTRY_TC,    // 317 3d Hard Stop: entry delay (ms)
+    ISC_P_DRV_TRQ_CMD,              // 318 3e Torque/Force Commanded
+    ISC_P_DRV_TRQ_MEAS,             // 319 3f Torque/Force Measured
+    ISC_P_DRV_RMS_LVL,              // 320 40 RMS level
+    ISC_P_DRV_TRK_ERR_LIM,          // 321 41 Tracking Error Limit (quad cnts)
+    ISC_P_DRV_MV_DN_TC,             // 322 42 Move Done: Time Constant (ms)
+    ISC_P_DRV_STEPPER_TRQ,          // 323 43 Recovery window maximum
+    ISC_P_DRV_STEP_IDLE_TRQ,        // 324 44 Stepper idle torque (A)
+    ISC_P_DRV_STEP_ACC_TRQ,         // 325 45 Stepper accel torque (A)
+    ISC_P_DRV_STEP_FLDBK_TRQ_TC,    // 326 46 Stepper trq foldback time const (ms)
+    ISC_P_DRV_BUS_VOLTS,            // 327 47 Bus Voltage (V)
+    ISC_P_DRV_TP_IOP,               // 328 48 I/O testpoint
+    ISC_P_DRV_TP_IR,                // 329 49 R Channel testpoint
+    ISC_P_DRV_TP_IS,                // 330 4a S Channel testpoint
+    ISC_P_DRV_TP_IR_FILT,           // 331 4b R Channel testpoint/filter
+    ISC_P_DRV_TP_IS_FILT,           // 332 4c S Channel testpoint/filter
+    ISC_P_HEATSINK_TEMP,            // 333 4d Heatsink temperature
+    ISC_P_AMBIENT_TEMP,             // 334 4e Internal temperature
+    ISC_P_DRV_TP_5V,                // 335 4f 5V testpoint
+    ISC_P_DRV_TP_12V,               // 336 50 12V testpoint
+    ISC_P_DRV_TRQ_MEAS_FILT_TC,     // 337 51 Trq Measured Filter Time Const
+    ISC_P_DRV_TEMP_SIM,             // 338 52 Temp Simulator
+    ISC_P_DRV_FACT_KM_FACTOR,       // 339 53 Km Factor
+    ISC_P_DRV_FACT_MTR_MIN_RES,     // 340 54 Mtr Min Res
+    ISC_P_FACT_FAN_ON_TEMP,         // 341 55 Fan On Temp
+    ISC_P_DRV_PARTID,               // 342 56 Part ID
+    ISC_P_DRV_FACT_IB_TC,           // 343 57 IB TC
+    ISC_P_DRV_FACT_IB_TRIP,         // 344 58 IB Trip Point (A)
+    ISC_P_DRV_FACT_PHASE_TRIP,      // 345 59 Phase Trip Point (A)
+    ISC_P_DRV_IB_LVL,               // 346 5a IB Level
+    ISC_P_DRV_TSPD,                 // 347 5b Tspd phase delay
+    ISC_P_DRV_COMM_CHK_ANGLE_LIM = 349, // 349 5d Comm check angle limit
+    ISC_P_DRV_CPL_ERR_LIM = 350,    // 350 5e Coupling Error Limit (quad cnts)
+
+    ISC_P_IEX_STATUS=357,           // 357 6f Current IEX status info
+    ISC_P_IEX_USER_OUT_REG,         // 358 66 IEX output register
+    ISC_P_IEX_STOP_OUT_REG,         // 359 67 IEX output register when stopped
+    ISC_P_IEX_OUT_REG,              // 360 68 IEX last output register
+    ISC_P_IEX_IN_REG,               // 361 69 IEX input register
+    ISC_P_IEX_IN_RISE_REG,          // 362 6a IEX input rise register
+    ISC_P_IEX_IN_FALL_REG,          // 363 6b IEX input fall register
+    ISC_P_IEX_IN_REG_MASK,          // 364 6c IEX input register
+    ISC_P_IEX_IN_RISE_REG_MASK,     // 365 6d IEX input rise register
+    ISC_P_IEX_IN_FALL_REG_MASK,     // 366 6e IEX input fall register
+	ISC_P_IEX_GLITCH_LIM,           // 367 6f IEX glitch limit
+	ISC_P_DRV_SOFT_LIM_POSN_POS,    // 368 70 Software limit positive position
+	ISC_P_DRV_SOFT_LIM_POSN_NEG     // 369 71 Software limit negative position
+};
+
+/// Typedef for ISC parameter enum
+typedef enum _iscParams iscParams;
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * ISC PLA OR term indices for its outputs.
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+/**
+	\brief OR fuse indices for selecting PLA outputs.
+
+	These constants are used as the index of an OR term to select an
+	output.
+**/
+typedef enum _iscPLAoutIndex {
+	/**
+	Index for <i>General Purpose Output 0</i>.
+
+	\see \ref plaOutReg::Gpo0
+	**/
+    ISC_PLAOUT_GPO0_BIT,                  	// 0 Gen. purpose output 0
+	/**
+	Index for <i>General Purpose Output 1</i>.
+
+	\see \ref plaOutReg::Gpo1
+	**/
+    ISC_PLAOUT_GPO1_BIT,                  	// 1 Gen. purpose output 1
+	/**
+	Index for <i>Drive Enable Request</i>.
+
+	\see \ref plaOutReg::Enable
+	**/
+    ISC_PLAOUT_ENABLE_BIT,                	// 2 Drive enable request
+	/**
+	Index for <i>Position Capture</i>.
+
+	\see \ref plaOutReg::Capture
+	**/
+    ISC_PLAOUT_CAPTURE_BIT,               	// 3 Position capture trigger
+	/**
+	Index for <i>Move Trigger</i>.	
+
+	\see \ref plaOutReg::Trigger
+	**/
+    ISC_PLAOUT_TRIGGER_BIT,               	// 4 Move trigger
+	/**
+	Index for <i>Node Stop Initiator</i>.	
+
+	\see \ref plaOutReg::NodeStop
+	**/
+    ISC_PLAOUT_NODE_STOP_BIT,             	// 5 Trigger node stop
+	/**
+	Index for <i>Reset Timer</i>.	
+
+	\see \ref plaOutReg::ResetTimer
+	**/
+    ISC_PLAOUT_RESET_TIMER_BIT,				// 6 Reset the gen purpose timer
+	/**
+	Index for <i>PLA Feedback Term 0</i>.	
+
+	\see \ref plaOutReg::PLAattn0
+	**/
+    ISC_PLAOUT_PLA_ATTN0_BIT,             	// 7 PLA output 0
+	/**
+	Index for <i>PLA Feedback Term 1</i>.	
+
+	\see \ref plaOutReg::PLAattn1
+	**/
+    ISC_PLAOUT_PLA_ATTN1_BIT,             	// 8 PLA output 1
+											// 9
+											// 10
+											// 11
+
+	/**
+	Index for <i>Positive Torque/Force Foldback</i>.	
+
+	\see \ref plaOutReg::PosTrqFldBk
+	**/
+	ISC_PLAOUT_POS_TRQ_FLBK_BIT = 12,		// 12 Positive torque foldback
+	/**
+	Index for <i>Negative Torque/Force Foldback</i>.	
+
+	\see \ref plaOutReg::NegTrqFldBk
+	**/
+	ISC_PLAOUT_NEG_TRQ_FLBK_BIT				// 13 Negative torque foldback
+} iscPLAoutIndex;
+
+//****************************************************************************
+// Insure structs are byte packed on target
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+//****************************************************************************
+
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * ISC CONFIGURATION REGISTER DEFINITIONS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+/**
+	\brief Meridian-ISC hardware configuration register fields.
+**/
+typedef struct PACK_BYTES _iscHwConfigFlds
+{
+	/// Motor Type Selection
+	typedef enum _motorTypes {
+		MOTOR_BRUSHLESS_ROTARY,         ///<  0: Rotary, brushless
+		MOTOR_BRUSH_ROTARY,             ///<  1: Rotary, brush
+		MOTOR_BRUSHLESS_LINEAR,         ///<  2: Linear, brushless
+		MOTOR_UNKNOWN,                  ///<  3: Unknown motor
+		MOTOR_STEPPER = -4,             ///<  4/-4: Stepper motor
+		MOTOR_RESERVED5 = -3,           ///<  5/-3: Reserved
+		MOTOR_STEPPER_CLOSED_LOOP = -2  ///<  6/-2: Closed loop stepper
+	} motorTypes;                       ///< Motor Types
+
+										/// Commutation Sensor Mode Selection
+	typedef enum _commSensorModes {
+		CSM_STATE_SEQ_THERMAL,          ///<  0 Chk bad state & seq.,000=thermal fault
+		CSM_STATE_SEQ,                  ///<  1 Chk bad state & seq.,000!=thermal fault
+		CSM_STATE_THERMAL,              ///<  2 Chk bad state only, 000=thermal fault
+		CSM_STATE,                      ///<  3 Chk bad state only, 000!=thermal fault
+		CSM_NO_STATE_CHECK = 4,           ///<  4 Ignore the states
+		CSM_SENSORLESS_WITH_DAMPING = 6,  ///<  6 Sensorless start (no checks)
+		CSM_SENSORLESS_NO_DAMPING = 7,    ///<  7 Sensorless start, A-Style (DA4x)
+		CSM_SENSORLESS_DAMPING_DIST_CHK = -2, ///<  14 Sensorless start (distance check, damping)
+		CSM_SENSORLESS_NO_DAMP_DIST_CHK = -1  ///<  15 Sensorless start (distance check, A-Style)
+	} commSensorModes;                  ///< Commutation Sensor Handling
+
+										/// Servo Mode Selection.
+	typedef enum _servoModes {
+		/*!
+			\brief Single-Loop
+
+			Closed loop servo with feedback from the motor's encoder.
+		**/
+		SINGLE_LOOP,                    //  0: Single Loop from motor encoder
+		MODE_NA1,                       //  1: Illegal mode
+		SINGLE_LOAD,                    //  2: Single Loop/load encoder units, read 2nd enc.
+		/*!
+			\brief Dual-Loop
+
+			Dual loop servo. The measured position is from the load encoder and
+			the motor's encoder is used for inner velocity control.
+		**/
+		DUAL_LOOP,                      //  3: Dual Loop, read 2nd encoder
+		/*!
+			\brief Open-Loop
+
+			Open loop servo for stepper motors. The motor's position
+			is optionally allowed to be read but never acted on for position
+			control. When the motor's encoder is enabled, the position
+			tracking is calculated for display and safety shutdown purposes.
+		**/
+		OPEN_LOOP = -4                  //  4: Open loop
+	} servoModes;                       // Servo Modes
+
+	/**
+		\brief Motor type selection.
+
+		Attached motor type.
+	**/
+	motorTypes MotorType : 3;					//  0-3
+	/**
+		\brief Vector Lock Diagnostic Enable
+
+		If the motor is vector oriented, such as a brushless motor
+		this will force the vector to freeze.
+	**/
+	BFld VectorLock : 1;						//   3 
+	/**
+		\brief Commutation handling for vector type motors.
+
+		The commutation handling for vector type motors.
+	**/
+	commSensorModes CommMode : 4;				//  4-7
+	/**
+		\brief Commutation sensor inverter.
+
+		Invert the commutation sensors.
+	**/
+	BFld CommutationInvert : 1;					//   8 
+	/**
+		\brief Encoder sequence checking.
+
+		If set, the encoders will be tested for bad sequences. This will
+		generate warnings and/or shutdowns when encountered.
+	**/
+	BFld EncCheck : 1;							//   9 
+	/**
+		\brief Disable phase overload checking.
+
+		If set, this bit will disable the phase overload checking. This
+		test should be disabled only under extreme conditions as real
+		problems could lead to drive or motor destruction.
+	**/
+	BFld DisPhaseOver : 1;						//  10
+	/**
+		\cond FW_MILESTONE_5R4
+		\brief Dynamic Brake Disable (v5.4)
+
+		If not set, this bit will provide motor braking by connecting the
+		windings to the motor power bus's return. The drive will modulate
+		the braking to prevent damage to the power stage during this time.
+
+
+		When this feature is enabled, the brake effect is engaged with
+		any or all of these conditions:
+		- Motor power bus low conditions that assert the
+		#alertReg::BusVoltageLow bit.
+		- Disabling of the enable.
+		- Shutdown condition that disables the drive
+		\endcond
+
+		\note This feature requires ISC firmware version 5.4 and above.
+	**/
+	BFld DisDynamicBrake : 1;					//  11 
+	BFld: 4;									//  12-15
+	/**
+		\brief Expected IEX count/plug-and-play mode.
+
+		This field, if non-zero will cause the IEX module to check for
+		the presence of the specified IEX modules on the IEX link. This
+		provides a mechanism to insure the setup of each node is correctly
+		implemented. If there is a mismatch the IEX status register will
+		reflect this. This register is accessed via the #iscGetIEXStatus
+		function.
+	**/
+	BFld IEXcount : 3;							//  16-18
+	/**
+		\brief IEX system stop.
+
+		This field controls the IEX modules. Setting this bit to one
+		will stop the IEX subsystem and hold the outputs at the last
+		updated value. If the inputs are read or outputs attempting to
+		change will return an error.
+
+		When this bit is cleared, the IEX subsystem is restarted. If
+		the modules are connected and powered properly the subsystem
+		will go online and interaction with the IEX modules may be
+		performed.
+
+		Watch the #iscGetIEXStatus results to find out when you can
+		interact with the modules.
+	**/
+	BFld IEXstop : 1;							//  19 
+	/**
+		\brief Servo operation mode.
+
+		Change the servo loop mode. This can provide single-loop,
+		dual-loop or open-loop modes.
+
+		The single-loop uses the motor's encoder as the feedback device
+		for positioning.  The dual-loop mode uses the load encoder for
+		the position feedback device and the motor as as stablilizing
+		feedback device. In open-loop mode, the measured position is not
+		used.
+	**/
+	servoModes ServoMode : 3;					//  20-22
+	/**
+		\brief Ignore open-loop encoder.
+
+		Setting this field will cause the open-loop mode to ignore the
+		motor's encoder and cause the measured position to equal the
+		commanded position.
+	**/
+	BFld IgnoreEnc : 1;							//  23
+	/**
+		\brief Load encoder sequence check.
+
+		If set, the load encoder will be tested for bad sequences
+		when operating in single loop mode. This will
+		generate warnings and/or shutdowns when encountered.
+	**/
+	/**
+		 Detect ld encoder bad seqs in single loop mode
+	**/
+	BFld LdEncCheck : 1;						//  24
+} iscHwConfigFlds;
+
+
+/**
+    \brief Hardware Configuration Register.
+
+	\copydetails ISC_P_HW_CONFIG_REG
+
+	\see \ref iscGetHwConfigReg
+	\see \ref iscSetHwConfigReg
+**/
+typedef union _iscHwConfigReg {
+	/// Settings as an integer
+	Uint32 bits;
+	///< Field based access for <i>Hardware Configuration Register</i>.
+	iscHwConfigFlds Fld;
+    /// \cond INTERNAL_DOC
+    // Indicate commSensorMode state chk enabled
+    tBOOL UsingCommStateChk() {
+        // Non-state chk entries of commSensorModes should have MSb of 1.
+        STATIC_ASSERT((iscHwConfigFlds::CSM_NO_STATE_CHECK & iscHwConfigFlds::CSM_SENSORLESS_WITH_DAMPING
+                       & iscHwConfigFlds::CSM_SENSORLESS_NO_DAMPING & iscHwConfigFlds::CSM_SENSORLESS_DAMPING_DIST_CHK
+                       & iscHwConfigFlds::CSM_SENSORLESS_NO_DAMP_DIST_CHK & 0x4) != 0);
+        return ((Fld.CommMode & 0x4) == 0);
+    }
+
+    // Indicate commSensorMode 000 == thermal fault
+    tBOOL UsingCommThermalChk() {
+        // 000 == thermal fault entries of commSensorModes should have LSb of 0.
+        STATIC_ASSERT(((iscHwConfigFlds::CSM_STATE_SEQ_THERMAL | iscHwConfigFlds::CSM_STATE_THERMAL) & 0x1) == 0);
+        return (UsingCommStateChk() && (Fld.CommMode & 0x1) == 0);
+    }
+    //! \endcond
+
+} iscHwConfigReg;
+//                                                                            *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+/**																			  *
+\brief Meridian ISC Application Configuration Register fields.
+
+\copydetails ISC_P_APP_CONFIG_REG
+
+\see \ref iscGetAppConfigReg
+\see \ref iscSetAppConfigReg
+**/
+// Note: the numbers in the field descriptions denote their bit
+// range in the register.
+/// Field of the <i>Application Configuration Register</i>.
+typedef struct _iscAppConfigFlds {
+
+	/// General Purpose Input/Limit Switch handling
+	typedef enum _limitModes {
+		/*!
+			Ignores General Purpose inputs for travel limits.
+		**/
+		LIMIT_MODE_OFF,                     //  0: ignore limits
+		/*!
+			General Purpose Inputs 2 and 3 are travel limits.
+		**/
+		LIMIT_MODE_POSITION,                //  1: Limit position
+		/*!
+			Not implemented
+		**/
+		LIMIT_MODE_TORQUE,                  //  2: Limit torque
+		/*!
+			\cond FW_MILESTONE_5R4
+			Travel limits set using drive parameters.
+
+			\note Soft position limit mode is only available on firmware
+			version 5.4 and later.
+		**/
+		LIMIT_MODE_SOFT_POSN = -4			//  4: Software position limit
+	} limitModes;                           ///< GPI/Limit Switch Modes
+	/*!
+		\brief Trigger group.
+
+		Trigger group ID for the trigger command. The Trigger Group
+		of zero is always ignored.
+	**/
+	BFld TriggerGroup : 2;				//   0 ID for group trigger event
+	BFld na2 : 1;						//     2
+	/*!
+		\brief GPI-0 Global Node Stop Enable
+
+		If asserted the de-assertion of the GPI-0 causes this node
+		to enter its Node Stop defined by the Stop Type Parameter
+		(#ISC_P_STOP_TYPE). This node will also generate a node stop
+		to all of it's upstream nodes.
+	**/
+	BFld GPI0nodeStop : 1;				//   3 Gen Node Stop on GPI-0 Rise
+	/*!
+		\brief GPI-0 <i>A After Start</i> comparison source.
+
+		For the <i>A After Start</i> feature, this field will select if the
+		position is based on the commanded or the measured values.
+		<table class="doxtable">
+		<tr> <th>Code</th>  <th>Description             </th> </tr>
+		<tr> <td>0</td>     <td>Commanded Position      </td> </tr>
+		<tr> <td>1</td>     <td>Measured Position       </td> </tr>
+		</table>
+		Set the A After Start Parameter (#ISC_P_A_START) to setup
+		this feature.
+	**/
+	BFld AAfterStartMeas : 1;			//   4 0=Commanded,1=Measured
+	/*!
+		\brief GPI-0 <i>B Before End</i> comparison source.
+
+		For the <i>B Before End</i> feature, this field will select if the
+		position is based on the commanded or the measured values.
+		<table class="doxtable">
+		<tr> <th>Code</th>  <th>Description             </th> </tr>
+		<tr> <td>0</td>     <td>Commanded Position      </td> </tr>
+		<tr> <td>1</td>     <td>Measured Position       </td> </tr>
+		</table>
+		Set the B Before Start Parameter (#ISC_P_B_END) to setup
+		this feature.
+	**/
+	BFld BBeforeEndMeas : 1;			//   5 0=Commanded,1=Measured
+	/*!
+		\brief GPI-0 <i>At Position</i> comparison source.
+
+		For the <i>At Position</i> feature, this field will select if the
+		position is based on the commanded or the measured values.
+		<table class="doxtable">
+		<tr> <th>Code</th>  <th>Description             </th> </tr>
+		<tr> <td>0</td>     <td>Commanded Position      </td> </tr>
+		<tr> <td>1</td>     <td>Measured Position       </td> </tr>
+		</table>
+		When the #plaOutReg::Capture output is asserted the
+		specified position is captured to the PLA Capture register.
+		(#ISC_P_POSN_CAP_PLA)
+	**/
+	BFld AtPositionMeas : 1;			//   6 0=Commanded,1=Measured
+	BFld na7 : 1;						//     7
+	/*!
+		\brief <i>Hard Stop</i> Foldback Enable
+
+		This field enables the <i>Hard Stop</i> feature. This feature
+		will allow the application to utilize a rigid end stop
+		as a home position. This feature allows the deletion of
+		a home sensor from a design. Setting this bit enables
+		this feature.
+		The torque/force is
+		specified by the <i>Hard Stop Foldback</i> parameter
+		(#ISC_P_DRV_HARDSTOP_FLDBK_TRQ). If torque/force
+		relaxation is required from the initial torque/force to
+		the end torque/force use the <i>Hard Stop Relax
+		Time Constant</i> (#ISC_P_DRV_HARDSTOP_FLDBK_TRQ_TC).
+
+		/todo HardStop Feature
+	**/
+	BFld FoldbackHardStop : 1;			//   8 Foldback on hard stop
+	/*!
+		\brief <i>Move Done</i> Foldback Enable
+
+		This field enables the <i>Move Done Foldback</i> feature.
+		This feature will allow the application to utilize
+		a rigid end stop as a home position. This feature
+		allows the deletion of a home sensor from a design.
+
+		Asserting this bit will cause a torque/force foldback
+		to assert at the end of move. The torque/force is
+		specified by the <i>Move Done Foldback</i> parameter
+		(#ISC_P_DRV_MOVEDONE_FLDBK_TRQ). If torque/force
+		relaxation is required from the initial torque/force to
+		the end torque/force, use the <i>Move Done Relax
+		Time Constant</i> (#ISC_P_DRV_MOVEDONE_FLDBK_TRQ_TC).
+
+		\see \ref ISCmoveDonePage
+	**/
+	BFld FoldbackMoveDone : 1;			//   9 Foldback on move done
+	BFld na10_11 : 2;					//    10
+	/*!
+		\brief <i>Limit Switch/GPI</i> Enable
+
+		This field controls the processing of the GPI-2 and GPI-3
+		as well as the limit mode enabled. Three limit modes are
+		available:
+		- Ignore Mode (\ref LIMIT_MODE_OFF):
+		The GPI-2 and GPI-3 inputs are used as general purpose inputs.
+		- Position Mode (\ref LIMIT_MODE_POSITION):
+		GPI-2 and GPI-3 are treated as limit switches
+		and the node will cancel movement when one of these limits is
+		asserted.
+		- Soft Position Mode (\ref LIMIT_MODE_SOFT_POSN):
+		The GPI-2 and GPI-3 inputs are used
+		as general purpose inputs and the travel limits are set using
+		parameters to specify the upper and lower positional limits for travel.
+
+		\note The Soft Position Mode is only available on firmware
+		version 5.4 and later.
+	**/
+	limitModes LimitMode : 3;			//  12-14 Limit switch mode
+	/*!
+		\brief <i>Limit Ramp Stop</i>
+
+		This field controls the type of stop that is used when
+		a limit is encountered. If asserted, a ramp-style stop
+		will be used; otherwise, an abrupt stop will be used
+		for stopping at a limit.
+
+		\note A ramp-type stop is only
+		available on firmware version 5.4 and later.
+	**/
+	BFld LimitRampStop : 1;				//  15 Limit stop type
+} iscAppConfigFlds;
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+/**																			  *
+    \brief Application Configuration Register.
+
+    \copydetails ISC_P_APP_CONFIG_REG
+
+	\see \ref iscGetAppConfigReg
+	\see \ref iscSetAppConfigReg
+**/
+typedef union _iscAppConfigReg {
+    /// Register state as an integer.
+    Uint32 bits;
+	/**
+	Application Configuration field access
+	**/
+	iscAppConfigFlds Fld;                                 
+    // For C++ non-firmware usage, include a constructor.
+    #ifdef __cplusplus
+        #ifndef __TI_COMPILER_VERSION__
+        _iscAppConfigReg() {                // Clear bits on construction
+            bits = 0;
+        }
+        #endif
+    #endif
+} iscAppConfigReg;
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+/**																			  *
+    \brief Tuning Configuration Register.
+
+    This register controls various servo performance settings. For example:
+    anti-hunt mode settings are here.
+
+	\see \ref ISC_P_APP_CONFIG_REG
+	\see \ref iscGetAppConfigReg
+	\see \ref iscSetAppConfigReg
+**/
+typedef union _iscTuneConfigReg {
+    /// Antihunt selections
+    typedef enum _antihuntModes {
+        ANTIHUNT_OFF,                       ///<  0 Off
+        ANTIHUNT_STD                        ///<  1 Standard Mode
+    } antihuntModes;                        ///< Anti-hunt modes
+    /// Register value as an integer
+    Uint32 bits;
+    // Note: the numbers in the field descriptions denote their bit
+    // range in the register.
+    struct _iscTuneConfigFlds {
+        /**
+			\brief Anti-Hunt Mode selection.
+
+            Anti-Hunt mode select from the #antihuntModes enumeration.
+        **/
+        antihuntModes AntiHunt      : 2;    // 0-1 Anti-hunt modes
+		/// \cond INTERNAL_DOC
+        BFld na2_3              : 2;    // 2
+		/// \endcond
+        /**
+			\brief Motor's velocity estimator selection.
+
+            Motor's velocity estimator selection.
+        **/
+        BFld MtrVelocityEst     : 3;    // 4-6 Motor velocity estimator
+		/// \cond INTERNAL_DOC
+        BFld na7                : 1;    // 7
+		/// \endcond
+        /**
+			\brief Load's velocity estimator selection.
+
+            Load's velocity estimator selection.
+        **/
+        BFld LdVelocityEst      : 3;    // 8-10 Load velocity estimator
+		/// \cond INTERNAL_DOC
+		BFld na11				: 1;
+		/// \endcond
+		/**
+			\brief Data Collection control (v5.6)
+
+			Clearing these bits will collect data during each move command.
+			This is the typical setting for this feature. 
+
+			Setting this bit will cause the <i>Data Collection</i>
+			feature to free-run the collection between command calls. This
+			is a special testing mode and generally not of much value
+			for applications.
+
+			\note This feature appears on ISC firmware version 5.6 and later.
+		**/
+		BFld DataCollectFreeRunApp	: 1;	// 12 Data collector free runs on App
+		BFld DataCollectFreeRunDiag	: 1;	// 13 Data collector free runs on Diag
+    } Fld;                                  ///< Field Access to Tuning Register
+    // For C++ non-firmware usage, include a constructor.
+    #ifdef __cplusplus
+		#ifndef __TI_COMPILER_VERSION__
+        _iscTuneConfigReg() {               // Clear bits on construction
+            bits = 0;
+        }
+        #endif
+    #endif
+} iscTuneConfigReg;
+//																			  *
+//*****************************************************************************
+
+//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+//                          ISC NODE STATUS REGISTER
+//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+//      This register is made up of three 16-bit sections for a total length
+//      of 48 bits. The lower 24-bits can be used to generate spontaneous
+//      attention packets to the host as a form of interrupt to the host.
+//
+//      The three sections are:
+//          - Attentionable state information
+//          - PLA input register (first 8-bits attentional)
+//          - Non-attentionable state
+//
+//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  iscLowAttnFlds union
+//
+// DESCRIPTION
+/**
+ 	\cond ISC_DOC
+    \brief <i>Lower Attentionable</i> portion of the <i>Status Register</i>.
+
+    This portion of the Status Register (#mnStatusReg) can be used to generate
+    attention packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+
+// Use typedef for bitfields so that the size of the field, and apparently
+// therefore the size of the struct, will be the same on host and node.
+// Note that just "unsigned" causes a 32 vs 16-bit mismatch on host and node.
+
+
+/**
+	LSBs of the attentionable part of the status register.	
+**/
+typedef struct _iscLowAttnFlds {
+    //                              Bit #     Describe
+    /**
+		\brief Warning is present.
+
+		\copydetails attnReg::DrvFld
+
+    **/
+    BFld Warning        : 1;    // 0  00 Warning is present
+    /**
+		\brief User alert is present.
+
+		\copydetails attnReg::DrvFld
+
+    **/
+    BFld UserAlert      : 1;    // 1  01 User Alert is present
+    /**
+		\brief Node not ready for operation.
+
+		\copydetails attnReg::DrvFld
+
+    **/
+    BFld NotReady       : 1;    // 2  02 Not Rdy for Operation
+    /**
+		\brief Move buffer is available.
+
+		\copydetails attnReg::MoveBufAvail
+
+        \remark
+        This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld MoveBufAvail   : 1;    // 3  03 Move buffer is available
+    /**
+		\brief IEX input rise detected.
+
+		\copydetails attnReg::IEXrise
+
+        \remark
+        This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld IEXrise        : 1;    // 4  04 IEXrise & riseMask is nonzero
+    /**
+		\brief IEX input fall detected.
+
+		\copydetails attnReg::IEXfall
+
+        \remark
+        This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld IEXfall        : 1;    // 5  05 IEXfall & fallMask is nonzero
+    /**
+		\brief IEX status and statistics changed.
+
+		\copydetails attnReg::IEXstatus
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld IEXstatus      : 1;    // 6  06 IEX status reg changed
+    /**
+		\brief Motion will occur on enable
+
+		Most of this logic will be handled by the UI. However, there are
+		a few command controllers that have to supply some additional
+		information for this logic. Instead of creating separate bits for
+		each command controller, they can all use this one.
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling. (NOTE: This bit probably does not need to be
+        in the attentionable part of the status register. When/If we free
+        up more bits in the unattentionable part for clearPath, this could
+        be moved.)
+    **/
+    BFld MotionPending            : 1;    // 7
+    /**
+		\brief Positive limit asserted (FW v5.4).
+
+		\copydetails attnReg::InPosLimit
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld InPosLimit     : 1;    // 8 Positive limit asserted
+    /**
+		\brief Negative limit asserted (FW v5.4).
+
+		\copydetails attnReg::InNegLimit
+		
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld InNegLimit     : 1;    // 9 Negative limit asserted
+    /**
+		\brief Motion Blocked (FW v5.4).
+
+		\copydetails attnReg::MotionBlocked
+		
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld MotionBlocked     : 1; //10 Motion blocked
+	///\cond INTERNAL_DOC
+	/**
+     	\brief Trigger Pulse Detected
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld TriggerPulse		: 1; //11 Trigger pulse detected
+    /**
+     	\brief In Homing Sequence
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling. Indicates that a homing sequence is being
+        executed
+    **/
+    BFld Homing				: 1; //12 In Homing Sequence
+	///\endcond
+	/**
+		\brief Going To Disable Soon
+
+		\remark This bit can generate an attention request to the host for
+		autonomous handling. Indicates that the drive is about to go
+		disabled.
+	**/
+	BFld GoingDisabled		: 1; //13 Heads-up going to disable
+	/**
+		\brief Status Rise Event detected
+
+		\remark This bit is set when the StatusRT register ANDed 
+		with the Group Status Mask Register is non-zero.
+	**/
+	BFld StatusEvent		: 1; //14 Heads-up going to disable
+	/**
+		\brief Drive Enabled
+
+		\remark This bit is set when the drive is enabled. This
+		can be used to release a brake.
+	**/
+	BFld Enabled			: 1; //15 Drive is enabled
+} iscLowAttnFlds;
+/// \endcond                                                                  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  _iscPlaInFlds struct
+//
+// DESCRIPTION
+/**
+	\cond ISC_DOC
+    \brief <i>PLA Inputs</i> portion of the <i>Status Register</i>.
+
+    The middle portion of the Status Register (#mnStatusReg) that feeds the PLA
+    function. The lower eight bits can be used to generate attention
+    packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct _iscPlaInFlds {
+    // ---------------- These fields are attentionable ----------------
+    //                                    Status #
+    /**
+		\brief Node stopped.
+
+		\copydetails attnReg::DrvFld
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld NodeStopped    : 1;    // 0  16: node stop
+    /**
+		\brief Move completed and settled.
+
+		\copydetails attnReg::MoveDone
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+   **/
+    BFld MoveDone       : 1;    // 1  17: move done
+    /**
+		\brief Tracking out of range.
+
+		\copydetails attnReg::OutOfRange
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld OutOfRange     : 1;    // 2  18: not in range
+    /**
+		\brief <i>B Counts from End</i> of Move.
+
+		\copydetails attnReg::BFromEnd
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld BFromEnd       : 1;    // 3  19: n counts from end
+    /**
+		\brief PLA Feedback output 0.
+
+		\copydetails attnReg::PlaOut0
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld PlaOut0        : 1;    // 4  20: PLA output 0
+    /**
+		\brief PLA Feedback output 1.
+
+		\copydetails attnReg::PlaOut1
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld PlaOut1        : 1;    // 5  21: PLA output 1
+    /**
+		\brief General Purpose Input 0.
+
+		\copydetails attnReg::Gpi0
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld Gpi0           : 1;    // 6  22: general purpose input 0
+    /**
+		\brief General Purpose Input 1.
+
+		\copydetails attnReg::Gpi1
+
+        \remark This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld Gpi1           : 1;    // 7  23: general purpose input 1
+    // ------------ Remaining fields are not attentionable ------------
+    /**
+		\brief General Purpose Input 2 / Positive Limit.
+
+        This bit asserts when the General Purpose Input 2 is asserted
+        or, when in position limit mode, the node is in the positive limit
+        switch.
+
+        The operational mode is set by the
+        #iscAppConfigReg::LimitMode field.
+    **/
+    BFld Gpi2_posLim    : 1;    // 8  24: GPI2 / positive limit asserted
+    /**
+		\brief General Purpose Input 3 / Negative Limit.
+
+        This bit asserts when the General Purpose Input 3 is asserted
+        or, when in position limit mode, the node is in the negative limit
+        switch.
+
+        The operational mode is set by the
+        #iscAppConfigReg::LimitMode field.
+    **/
+    BFld Gpi3_negLim    : 1;    // 9  25: GPI3 / negative limit asserted
+    /**
+		\brief Crossed At Position location.
+
+        This bit asserts when the measured position crosses the
+        location specified in the <i>At Position Location</i> 
+        (#ISC_P_POSN_TRIG_PT).
+    **/
+    BFld AtPosition     : 1;    // 10 26: at position
+    /**
+		\brief Masked IEX active.
+
+        This bit asserts when the <i>IEX Input Register</i>
+        (#ISC_P_IEX_IN_REG), bitwise ANDed with the
+        <i>IEX Input Mask Register</i> (#ISC_P_IEX_IN_REG_MASK),
+        produces a non-zero result.
+    **/
+    BFld MaskedIEX      : 1;    // 11 27: IEX & IEX mask = nonzero
+    /**
+		\brief <i>A From Start</i> of move.
+
+        This bit asserts when the move is <i>A From Start</i>
+        (#ISC_P_A_START) of the move. The basis of the move is
+        selected by the
+        #iscAppConfigReg::AAfterStartMeas bit in
+        the <i>Application Configuration Register</i>
+        (#ISC_P_APP_CONFIG_REG).
+		\note Behavior is undefined for moves that cross a 32-bit
+		signed position boundary
+    **/
+    BFld AFromStart     : 1;    // 12 28: n counts from start
+    /**
+		\brief Commanded move is negative.
+
+        This bit asserts when the current command resulted in the
+        position changing in a negative direction. This bit changes
+        at the start of a move and persists until the next move.
+        A zero step move is considered positive.
+
+        This feature is useful for controlling foldback modes based
+        on the motion issued using the PLA feature.
+        \see \ref ISCplaPage
+		\see \ref ISCfoldbackPage
+    **/
+    BFld MoveCmdNeg     : 1;    // 13 29: move direction is negative
+    /**
+		\brief Drive is disabled.
+
+        This bit asserts when the ISC's power amplifier is
+        disabled.
+    **/
+    BFld Disabled       : 1;    // 14 30: Drive disabled
+    /**
+		\brief <i>General Purpose Timer</i> has expired.
+
+        This bit asserts when the <i>General Purpose Timer</i>
+        timer has expired. This timer is reset by the
+        #plaOutReg::ResetTimer bit in the <i>Output
+        Register.</i> The duration of this timer is set by the
+        <i>General Purpose Timer Time Constant</i>
+        (#ISC_P_GP_TIMER_PERIOD).
+
+		\see \ref ISCgpTimerPage
+    **/
+    BFld TimerExpired   : 1;    // 15 31: timer expired
+	
+} iscPlaInFlds;
+/// \endcond                                                                  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME                                                                       *
+//  iscOutFlds structure
+//
+// DESCRIPTION
+
+/**
+	\cond ISC_DOC
+    \brief Meridian ISC output register definition. It allows access to
+	actuation of various features within and external via electrical outputs
+	from the node.
+**/
+typedef struct PACK_BYTES _iscOutFlds
+{
+    /*                   -----------  --------------------------------- *
+     *                         bit #  description                       *
+     *                   -----------  --------------------------------- */
+    /**
+		\brief General purpose output 0 assert.
+
+        This bit controls the <i>General Purpose Output 0</i> 
+        pin on the node's I/O connector.
+
+		\see \ref ISCoutputsPage
+    **/
+    BFld Gpo0        : 1;    // 0 : general purpose output 0
+    /**
+		\brief General purpose output 1 assert.
+
+        This bit controls the <i>General Purpose Output 1</i> 
+        pin on the node's I/O connector.
+
+		\see \ref ISCoutputsPage
+    **/
+    BFld Gpo1        : 1;    /* 1 */ // general purpose output 1
+    /**
+		\brief Enable drive's power stage.
+
+        This bit controls the enabling of the drive's power stage and
+        prepares the node to accept motion commands, which will be
+        accepted when the <i>Status Register's</i> 
+        #lowAttnReg::NotReady bit has cleared.
+    **/
+    BFld Enable      : 1;    /* 2 */ // enable request
+    /**
+		\brief Capture measured position on asserting edge.
+
+        The asserting edge (0->1) of this bit will capture the measured
+        position to the PLA capture register (#ISC_P_POSN_CAP_PLA).
+    **/
+    BFld Capture     : 1;    /* 3 */ // capture
+    /**
+		\brief Generate trigger event on asserting edge.
+
+        The asserting edge (0->1) of this bit will generate a <i>Trigger
+        Event</i> which allows a waiting move  to begin.
+    **/
+    BFld Trigger     : 1;    /* 4 */ // a.k.a. go
+    /**
+		\brief Generate node stop on asserting edge.
+
+        The asserting edge (0->1) of this bit will initiate the node stop
+        programmed in the Stop Type register (#ISC_P_STOP_TYPE).
+    **/
+    BFld NodeStop    : 1;    /* 5 */ // enter node stop
+    /**
+		\brief Reset general purpose timer.
+
+        The asserting edge (0->1) of this bit will reset the <i>General
+        Purpose Timer</i> with duration (#ISC_P_GP_TIMER_PERIOD) and
+        clear the timer expired bit in the Status Register.
+
+		\see \ref ISCgpTimerPage
+    **/
+    BFld ResetTimer  : 1;    /* 6 */ // reset timer
+    /**
+		\brief PLA Feedback output 0.
+
+        This output is fed back to a similarly named input in the
+        <i>Status Register</i>. It is used to make simple state machines
+        or to map inputs available to the PLA system to an Attentionable
+        location.
+
+		\see \ref ISCplaPage
+		\see \ref ISCinputsPage
+    **/
+    BFld PLAattn0    : 1;    /* 7 */ // PLA output 0
+    /**
+		\brief PLA Feedback output 1.
+
+        This output is fed back to a similarly named input in the
+        <i>Status Register</i>. It is used to make simple state machines or
+        to map inputs available to the PLA system to an Attentionable
+        location.
+
+		\see \ref ISCplaPage
+		\see \ref ISCinputsPage
+    **/
+    BFld PLAattn1    : 1;    /* 8 */ // PLA output 1
+    BFld             : 1;    /* 9 */ // unused
+    BFld             : 1;    /* 10 */ // unused
+    BFld             : 1;    /* 11 */ // unused
+    /**
+		\brief Positive torque/force foldback enable.
+
+        Setting this bit can control the amount of positive torque/force
+        available. The Positive Foldback Torque (#ISC_P_DRV_POS_FLDBK_TRQ) 
+        parameter controls the amount.
+
+		\see \ref ISCfoldbackPage
+    **/
+    BFld PosTrqFldBk : 1;    /* 12 */ // positive torque foldback enable
+    /**
+		\brief Negative torque/force foldback enable.
+
+        Setting this bit can control the amount of negative torque/force
+        available. The Negative Foldback Torque (#ISC_P_DRV_NEG_FLDBK_TRQ) 
+        parameter controls the amount.
+
+		\see \ref ISCfoldbackPage
+    **/
+    BFld NegTrqFldBk : 1;    /* 13 */ // negative torque foldback enable
+    BFld             : 1;    /* 14 */ // unused
+    BFld             : 1;    /* 15 */ // unused
+} iscOutFlds;
+/// \endcond                                                                  *
+//*****************************************************************************
+
+/**
+	\cond INTERNAL_DOC
+    \brief Shutdown Field States
+    \public
+
+    These elements describe the state of the node shutdown system.
+**/
+typedef enum _shutdownStates {
+    SHDN_STATE_IDLE         = 0,    ///< All is well
+    SHDN_STATE_DELAY        = 1,    ///< Shutdown is imminent
+    SHDN_STATE_RAMP         = -2,   ///< Axis is ramping down to zero speed
+    SHDN_STATE_STOPPED      = -1    ///< Axis is shutdown
+} shutdownStates;
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  iscNonAttnFlds union
+//
+// DESCRIPTION
+
+/**
+	\cond ISC_DOC
+    \brief Non-Attentional portion of the ISC <i>Status Register</i>.
+
+    The most significant sixteen bit portion of the <i>Status Register</i>
+    (#mnStatusReg).
+    This portion of the register does not generate any attention packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct PACK_BYTES _drvNonAttnFlds
+{
+    //                                Status #
+    /**
+		\brief Motion Indicator.
+
+        This field represents the load's velocity status. The
+        table describes the states:
+		- 0: Near zero speed
+		- 1: Moving in a positive direction
+		- 2: Moving in a negative direction
+		- 3: Moved in both directions since the last read
+
+		\note This feature requires ISC firmware version 5.4 and above.
+    **/
+	BFld InMotion		: 2;	//0-1 32-33: Motion Signum
+    /**
+		\brief The Output Register bits are set using the
+		<i>Controlled Output Register</i> (#ISC_P_CTL_STOP_OUT_REG).
+
+        The Node Stop feature has forced the outputs to the
+        <i>Controlled</i> state. In this state the <i>Output
+        Register</i> is set to the state stored in the
+        <i>Controlled Output Register</i> (#ISC_P_CTL_STOP_OUT_REG).
+
+		\see \ref ISCnodeStopPage
+    **/
+	/**
+		\brief For drives with step+direction inputs and this feature.
+		This field is set true when the step+direction inputs are
+		active.
+	**/
+    BFld StepsActive    : 1;  // 0  34: True when step+dir active
+	/**
+		The Node Stop feature has forced the node into its 
+		<i>Controlled state</i>. The output register is now set to the
+		#ISC_P_CTL_STOP_OUT_REG register.
+
+	**/
+    BFld InCtrlStop     : 1;    // 3  35: Controlled Stop OutputReg
+    /**
+		\brief Fan running.
+
+        For units with a fan, this field is asserted when the
+        fan is on. This is a warning that the ambient or internal
+        temperature is approaching the shutdown level.
+    **/
+    BFld FanOn          : 1;    // 4  36: Fan is on
+    /**
+		\brief Vector searching.
+
+        For vector based motors, this bit asserted when the
+        vector has not been initialized.
+    **/
+    BFld VectorSearch   : 1;    // 5  37: Searching for commutation edges
+    /**
+		\brief Motion command has completed.
+
+        This bit is asserted after the motion command has been completed.
+        The move is considered totally complete when the <i>Move Done</i>
+        #plaInReg::MoveDone has been been asserted.
+    **/
+    BFld MoveCmdComplete: 1;    // 6  38: Move command completed
+    /**
+		\brief In hard-stop mode.
+
+        This bit asserts when the ISC has entered the <i>
+        Hard Stopped</i> mode and the node is applying clamping
+        torque/force. The feature is enabled with the
+        #iscAppConfigReg::FoldbackHardStop bit in the 
+		<i>Application Configuration Register</i> (#ISC_P_APP_CONFIG_REG).
+        \see \ref ISCfoldbackHardStop
+    **/
+    BFld InHardStop     : 1;    // 7  39: In hard-stop mode
+    /**
+		\brief Shutdown state.
+
+        This field describes the shutdown condition of the node.
+    **/
+#if defined(_WIN32)||defined(_WIN64)
+	// Avoid compiler padding bug
+    BFld ShutdownState	: 2;	// 8-9:40-41 Shutdown state
+#else
+    shutdownStates ShutdownState : 2;// 8-9:40-41 Shutdown state
+#endif
+    /**
+		\brief Hardware failure detected.
+
+        The unit's shutdown is caused by a hardware failure. This
+        unit should be replaced.
+    **/
+    BFld HwFailure      : 1;    // 10 42: Replace the node
+    /**
+		\brief Move awaiting trigger event.
+
+        The node has a triggered move awaiting release.
+
+		\see \ref ISCnodeStopPage
+    **/
+    BFld TriggerArmed   : 1;    // 11 43: Triggered move loaded on drive
+	/// \cond INTERNAL_DOC
+    BFld		        : 1;    // 12 44: Velocity Type
+	/// \endcond
+    /**
+		\brief Index detected on motor encoder.
+
+        The node has detected an index pulse on the motor's encoder. Read
+        the <i>Motor's Encoder Index</i> (#ISC_P_POSN_CAP_INDEX) parameter
+        to get its location.
+    **/
+    BFld IndexMtr       : 1;    // 13 45: Index detected on motor encoder
+    /**
+		\brief Index detected on load encoder.
+
+        The node has detected an index pulse on the load's encoder. Read
+        the <i>Load's Encoder Index</i> (#ISC_P_POSN_CAP_INDEX_LD) parameter
+        to get its location.
+    **/
+    BFld IndexLd        : 1;    // 14 46: Index detected on load encoder
+    /**
+		\brief Software inputs are being used.
+
+        Indicates when inputs that have the ability to be controlled either
+        by software or hardware have been switched to software control.
+    **/
+    BFld SoftwareInputs  : 1;    // 15 47: Using Software Inputs
+} iscNonAttnFlds;
+/// \endcond                                                                  *
+//*****************************************************************************
+
+//*****************************************************************************
+// Initial release of sFoundation compatible structs.
+/**
+	S-Foundation original release PLA input register fields for drives.
+**/
+typedef union _iscPlaInOldFlds {
+	plaInCommonFlds Common;
+	iscPlaInFlds DrvFld;
+} iscPlaInOldFlds;
+
+/**
+	S-Foundation original release low order attentionable fields for drives.
+**/
+typedef union _iscLowAttnOldFlds {
+	lowAttnCommonFlds Common;
+	iscLowAttnFlds DrvFld;
+} iscLowAttnOldFlds;
+
+/**
+	S-Foundation original release non-attentionable fields for drives.
+**/
+typedef union _iscNonAttnOldFlds {
+	nonAttnCommonFlds Common;
+	iscNonAttnFlds DrvFld;
+} iscNonAttnOldFlds;
+
+/**
+	\cond ISC_DOC
+    \brief <i>PLA Inputs</i> portion of the <i>Status Register</i>.
+
+    This is status register field definitions for the Meridian ISC.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct _iscStatusRegOldFlds {
+    iscLowAttnOldFlds  LowAttn; 	//!< Low part, all attentionable bits
+    iscPlaInOldFlds    PLAin;		//!< PLA input,  partially attentionable bits
+    iscNonAttnOldFlds  NonAttn;		//!< High part, non-attentionable
+} iscStatusRegOldFlds;
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  iscStatusRegFlds struct
+//
+// DESCRIPTION
+/**
+	\cond ISC_DOC
+    \brief <i>PLA Inputs</i> portion of the <i>Status Register</i>.
+
+    This is status register field definitions for the Meridian ISC.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct PACK_BYTES _iscStatusRegFlds {
+    iscLowAttnFlds  LowAttn; 	 //!< Low part, all attentionable bits
+    iscPlaInFlds    PLAin;		 //!< PLA input,  partially attentionable bits
+    iscNonAttnFlds  NonAttn;	 //!< High part, non-attentionable
+} iscStatusRegFlds; 
+//                                                                           *
+//****************************************************************************
+
+//******************************************************************************
+// NAME	
+//	iscStatusReg union
+/**
+	\cond ISC_DOC
+	\brief The Status Register definition for Meridian ISC.
+**/
+typedef union _iscStatusReg { 
+	/**
+		Bit-wise access to the status register contents.
+	**/
+	Uint16 bits[3];
+	iscStatusRegFlds Fld;
+} iscStatusReg;
+//                                                                           *
+//****************************************************************************
+
+
+//******************************************************************************
+// NAME	
+//	iscAttnFlds structure
+/**
+	\cond ISC_DOC
+	\brief Attention Register definition for Meridian Nodes.
+
+	ISC Drive Attention fields.  \b NOTE: the numbers in
+	description refer to the bit number in the register.
+**/
+typedef struct _iscAttnFlds {                // Attentionable 24-bits of status
+    /**
+		\brief Warning asserted.
+
+        This bit asserts when the <i>Warning Register</i> contents,
+        (#ISC_P_WARN_REG) ANDed with the user's <i>Warning Mask
+        Register</i> contents (#ISC_P_WARN_MASK), is non-zero.
+    **/
+    BFld Warning        : 1;    /* 0 */ // Warning asserted
+    /**
+		\brief 	User alert asserted.
+
+        This bit asserts when the <i>Alert Register</i> contents,
+        (#ISC_P_ALERT_REG) ANDed with the user's <i>Alert Mask
+        Register</i> contents (#ISC_P_ALERT_MASK), is non-zero.
+    **/
+    BFld UserAlert      : 1;    /* 1 */ // User alert asserted
+    /**
+		\brief Not ready for operation.
+
+        This bit asserts when the node is not ready. Consult the
+        <i>Status Register</i> (#mnStatusReg), as well as the other
+        bits in this register, for the reasons why the node is not
+        ready.
+
+        If the shutdown is clearable, the user application can try to 
+        clear the alerts with the IStatus::AlertsClear function. If the enable
+        request (#plaOutReg::Enable) for the drive is still asserted and
+        there are no other shutdown reasons, the node will
+        automatically become ready.
+		**/
+    BFld NotReady       : 1;    /* 2 */ // Not ready for operation
+    /**
+		\brief Move buffer is available.
+
+        This bit asserts when the move buffer is ready to
+        accept another move command. Moves sent while this
+        bit is de-asserted will be rejected by the node. Various
+        alert states may prevent the node from executing motion.
+
+        \see \ref ISCshutdownsPage
+		\see \ref MoveAnatomy 
+    **/
+    BFld MoveBufAvail   : 1;    /* 3 */ // Move buffer is available
+    /**
+		\brief IEX input rise detected.
+
+        This bit asserts when the <i>IEX Input Risen Register</i>
+        (#ISC_P_IEX_IN_RISE_REG), ANDed with the user's <i>IEX Risen
+        Mask Register</i> (#ISC_P_IEX_IN_RISE_REG_MASK), is non-zero.
+        To clear this bit, the application must read the <i>IEX Inputs
+        Risen Register</i> (#ISC_P_IEX_IN_RISE_REG).
+
+    **/
+    BFld IEXrise        : 1;    /* 4 */ // IEX input rise detected
+    /**
+		\brief IEX input fall detected.
+
+        This bit asserts when the <i>IEX Input Fallen Register</i>
+        (#ISC_P_IEX_IN_FALL_REG), ANDed with the user's <i>IEX Fallen
+        Mask Register</i> (#ISC_P_IEX_IN_FALL_REG_MASK), is non-zero.
+        To clear this bit, the application must read the <i>IEX
+        Inputs Fallen Register</i> (#ISC_P_IEX_IN_FALL_REG).
+    **/
+    BFld IEXfall        : 1;    /* 5 */ // IEX input fall detected
+    /**
+		\brief IEX status and statistics changed.
+
+        This bit asserts when the <i>IEX Status Register</i> (#ISC_P_IEX_STATUS) changes.
+        It can be used to detect problems with the IEX subsystem
+        due to IEX link issues or power problems with the IEX modules
+        themselves. Use the #iscGetIEXStatus function to read the
+        IEX system status.
+    **/
+    BFld IEXstatus      : 1;    /* 6 */ // IEX status and statistics
+	/// \cond INTERNAL_DOC
+    BFld na7            : 1;    // 7
+	/// \endcond
+    /**
+		\brief Positive limit asserted (FW v5.4).
+
+        This bit asserts when the positive position limit switch is
+        activated.  The conditions for when this bit is set depend on the
+        value of the #iscAppConfigReg::LimitMode setting in the
+        <i>Application Configuration Register</i> (#ISC_P_APP_CONFIG_REG).
+        Use the #iscSetAppConfigReg function to set up this mode.
+        Commands in the positive direction  will be flushed when this bit
+        is asserted.
+
+		\note This feature requires ISC firmware version 5.4 and above.
+		\see #plaInReg::Gpi2_posLim for this feature in older firmware.
+    **/
+    BFld InPosLimit     : 1;    /* 8 */ // Positive limit asserted
+    /**
+		\brief Negative limit asserted (FW v5.4).
+
+        This bit asserts when the negative position limit switch
+		is activated.  The conditions for when this bit is set depend
+		on the value of the #iscAppConfigReg::LimitMode setting
+        in the <i>Application Configuration Register</i>.
+        (#ISC_P_APP_CONFIG_REG) Use the #iscSetAppConfigReg function
+        to set up this mode.  Commands in the negative direction
+		will be flushed when this bit is asserted.
+
+		\note This feature requires ISC firmware version 5.4 and above.
+		\see #plaInReg::Gpi3_negLim for this feature in older firmware.
+	**/
+    BFld InNegLimit     : 1;    /* 9 */ // Negative limit asserted
+    /**
+		\brief Motion Blocked (FW v5.4).
+
+        This bit asserts when motion commands are blocked due 
+        a motion related condition. Some of these include:
+		- E-Stop
+		- Motion command under-run
+		- Repeated attempt to move into a position limit either
+		via the hardware limit switch or the soft limits.
+
+		\see #ISC_P_DRV_SOFT_LIM_POSN_POS
+		\see #ISC_P_DRV_SOFT_LIM_POSN_NEG
+		\see #iscAppConfigReg::LimitMode
+		\see #alertReg::FwMoveBufUnderrun
+		\see #alertReg::FwBadRASVelrequest
+		\see #alertReg::FwMoveGenRange
+		\see #alertReg::FwMoveGenHwLim
+
+		\note This feature requires ISC firmware version 5.4 and above.
+    **/
+    BFld MotionBlocked     : 1; /* 10 */ // Motion Blocked
+    /**
+     	\brief Trigger Pulse Detected
+
+		This bit indicates when a trigger pulse occurs. The action taken
+		by the drive when a trigger occurs is dependent on the
+		configuration and state of the drive at that time.
+    **/
+    BFld TriggerPulse		: 1; /* 11 */ // Trigger pulse detected
+	/// \cond INTERNAL_DOC
+    BFld na12_15	        : 4;    /* 12-15 */
+	/// \endcond
+    /**
+		\brief Node Stopped.
+
+        This bit represents the receipt of a node stop event. Depending
+        on the method the node stop was initiated with, the node may
+        or may not accept motion commands and may not allow changes to
+        the output register. If the node stop involved an E-Stop request,
+        this bit will remain on until the E-Stop state is cleared.
+
+        Node stops with the <i>Quiet</i> bit set will not assert
+        this bit.
+
+        \see \ref ISCnodeStopPage
+    **/
+    BFld NodeStopped    : 1;    /* 16 */ // node stopped
+    /**
+		\brief Move Done and Settled.
+
+        This bit is asserted at the end of every settled move command.
+        Once the  #nonAttnReg::MoveCmdComplete state has been reached the
+		node will check compliance with the <i>Move Done</i> criteria to
+		be met. Once this occurs this bit will be asserted and remain so
+		until the beginning of the next move command.
+
+        For velocity type moves, this bit will be set once the
+        node has attained the commanded velocity.
+
+        \see \ref ISCmoveDonePage
+    **/
+    BFld MoveDone       : 1;    /* 17 */ // move done and settled
+    /**
+		\brief Tracking out of range.
+
+        This bit asserts when the current <i>Tracking Error</i>
+        (#ISC_P_POSN_TRK) has exceeded the <i>Tracking Range</i>
+        (#ISC_P_POSN_TRK_RANGE) parameter.
+    **/
+    BFld OutOfRange     : 1;    /* 18 */ // not in range
+    /**
+		\brief <i>B Counts from End</i> of Move.
+
+        This bit asserts when the move is <i>B From End</i>
+        (#ISC_P_B_END) from the end of a positional move. 
+        The basis of the move is selected by the
+        #iscAppConfigReg::BBeforeEndMeas setting
+        in the <i>Application Configuration Register</i>
+        (#ISC_P_APP_CONFIG_REG). Use the #iscSetAppConfigReg function
+        to set up this mode.
+
+		\note Behavior is undefined for moves that cross a 32-bit
+		signed position boundary
+
+    **/
+    BFld BFromEnd       : 1;    /* 19 */ // B counts from end
+    /**
+		\brief PLA Feedback output 0.
+
+        This is a feedback term from the plaOutReg.
+
+        \see \ref ISCplaPage
+    **/
+    BFld PlaOut0        : 1;    /* 20 */ // PLA output 0
+    /**
+		\brief PLA Feedback output 1.
+
+        This is a feedback term from the plaOutReg.
+
+        \see \ref ISCplaPage
+    **/
+    BFld PlaOut1        : 1;    /* 21 */ // PLA output 1
+    /**
+		\brief General Purpose Input 0.
+
+        This bit asserts when the General Purpose Input 0 is asserted.
+    **/
+    BFld Gpi0           : 1;    /* 22 */ // general purpose input 0
+    /**
+		\brief General Purpose Input 1.
+
+        This bit asserts when the General Purpose Input 1 is asserted.
+    **/
+    BFld Gpi1           : 1;    /* 23 */ // general purpose input 1
+} iscAttnFlds; 
+/// \endcond																  *
+//*****************************************************************************
+
+
+//****************************************************************************
+// NAME                                                                      *
+//  iscAlertFlds struct
+//
+// DESCRIPTION
+/**
+	\cond ISC_DOC
+	\brief ISC Alert Register Fields
+	
+	This structure describes the ISC specific fields within the Alert 
+	Register.
+**/
+typedef struct PACK_BYTES _iscAlertFlds
+{
+	/// Common shutdown events. Least significant bits 0-31.
+	commonAlertFlds Common;
+	//                              ----------------------------------------
+	//                              |len|bit #|description                 |
+	//                              ----------------------------------------
+	/**
+		\brief Bad Data Acquisition State
+
+		The data acquisition system is in a bad state due to unsupported mode
+		or option(s).
+
+		Remedies:
+		- Stop and restart the data acquisition system.
+	**/
+	BFld FwBadDataAcqState      : 1; /* 32 */ // Bad Data Acquisiton State
+	/**
+		\brief Internal error in Move Generator
+
+		Move Generator Miscellaneous shutdown.
+
+		Remedies:
+		- Verify the move parameter ranges and options. There maybe
+		a conflicting request.
+	**/
+	BFld FwMoveGenMisc          : 1; /* 33 */ // Internal error in Move Gen
+	/**
+		\brief Move Generator Off Target
+
+		Move Generator was found off target. This is most likely a firmware
+		error detected by an internal inconsistency.
+
+		Remedies:
+		- Update firmware
+		- Try different acceleration and/or velocity limits.
+	**/
+	BFld FwMoveGenOffTarget     : 1; /* 34 */ // Move Gen off Target
+	/**
+		\brief Move > 8M Incremental
+
+		Attempting to move too far. Although the command and measurement
+		number space is 32 bits wide, this firmware has an internal limit
+		of motion of about 8 million steps (2^31-1).
+
+		Remedies:
+		- Break up move into smaller pieces.
+	**/
+	BFld FwMoveGenRange         : 1; /* 35 */ // Move > 8M incremental
+	/**
+		\brief Jerk Limit Bad
+
+		Move started with bad Jerk Limit request. An illegal or malformed
+		Jerk Limit was specified for a move starting. This move is
+		canceled.
+
+		Remedies:
+		- Check the Jerk Limit (#ISC_P_JERK_LIM) setting before
+		issuing the move.
+	**/
+	BFld FwBadRASrequest        : 1; /* 36 */ // Jerk Lim bad
+	/**
+		\brief Move Buffer Underran
+
+		Move Generator ran out of pending moves before terminal move.  This
+		would occur with spline type moves when the host cannot keep up
+		with the moves required to follow a path.
+
+		Remedies:
+		- Create moves with longer time intervals
+		- Use a more efficient mechanism to keep move buffer busy. Sometimes
+		an attention based mechanism will work.
+	**/
+	BFld FwMoveBufUnderrun      : 1; /* 37 */ // Move Buffer Underran
+	/**
+		\brief Velocity Limit Too High for Jerk Limit
+
+		The move was canceled due to velocity limit exceeding the encoder's
+		or Jerk Limit maximum allowed speed.
+
+		Remedies:
+		- Reduce the Velocity Limit (#ISC_P_VEL_LIM). Consult the
+		Jerk Limit Maximum Velocity parameter
+		(#ISC_P_RAS_MAX_VELOCIY) for the maximum allowable speed
+		at the current Jerk Limit setting.
+		- Change the Jerk Limit (#ISC_P_JERK_LIM) to one with
+		less speed limiting.
+	**/
+	BFld FwBadRASVelrequest     : 1; /* 38 */ // Vel. Limit too high for RAS
+	/**
+		\brief Invalid move spec was altered
+
+		The move could not meet both the distance and acceleration
+		parameters of the move with the given initial velocity.
+		The acceleration limit was increased to allow the
+		move to complete without overshooting.
+
+		Remedies:
+		- Allow a longer distance for the terminal move
+		- Increase the acceleration limit
+		- Limit the velocity prior to the terminal move
+	**/
+	BFld FwMoveSpecAltered      : 1; /* 39 */ // Move spec altered
+	/**
+		\brief Phase Sensor Bad
+
+		Phase Sensor failed Power-On Self Test.
+
+		Remedies:
+		- Replace drive.
+	**/
+	BFld HwPhaseSensor          : 1; /* 40 */ // Phase Sensor bad
+	/**
+		\brief Limit switch activated
+
+		Attempting to move in a direction in which the limit switch
+		is activated.
+
+		Remedies:
+		- Move away from the limit or clear the limit activation.
+	**/
+	BFld FwMoveGenHwLim         : 1; /* 41 */ // Limit switch activated
+	/**
+		\brief Soft Limit prevents move
+
+		Attempting to move outside the range specified by the software
+		limits.
+
+		Remedies:
+		- Move away from the limit or adjust the limit settings.
+	**/
+	BFld FwMoveGenSwLim         : 1; /* 42 */ // SoftLim range exceeded
+	/**
+		\brief Move Buffer Overrun
+
+		Attempting to buffer up more move than the move buffer can hold.
+
+		Remedies:
+		- Slow down rate at which moves are being sent to the ClearPath to
+		  allow moves to execute
+	**/
+	BFld FwMoveBufOverrunLockdown	: 1; /* 43 */ // Move Buffer Overrun
+	/**
+		\brief Courtesy 5V Overloaded
+
+		Courtesy 5 Volt Power Supply is overloaded.
+
+		Remedies:
+		- Check for shorts on Motor or Load Encoder.
+		- Check for shorts on General Purpose I/O connections.
+		- If this persists with nothing attached to the ISC, the unit is
+		defective and should be replaced.
+	**/
+	BFld Io5VSupplyOverload     : 1;  /* 44 */ // Courtesy 5V overloaded
+	/**
+		\brief Brake Overloaded
+
+		Brake output is overloaded (for models that include brake output).
+
+		Remedies:
+		- Check for shorts in wiring harnesses.
+		- Use a brake that requires less current.
+	**/
+	BFld IoBrakeOverload        : 1;  /* 45 */ // Brake output overloaded
+	/**
+		\brief GPO-0 Overloaded
+
+		General Purpose Output 0 is overloaded (for models that support
+		individual output overload detection).
+
+		Remedies:
+		- Check for shorts in wiring harnesses.
+		- Reduce load on output (i.e., use LED instead of
+		incandescent lights).
+	**/
+	BFld IoGPO0overload         : 1;  /* 46 */ // GPO-0 overloaded
+	/**
+		\brief GPO-1 Overloaded
+
+		General Purpose Output 1 is overloaded (for models that support
+		individual output overload detection).
+
+		Remedies:
+		- Check for shorts in wiring harnesses.
+		- Reduce load on output (i.e., use LED instead of
+		incandescent lights).
+	**/
+	BFld IoGPO1overload         : 1;  /* 47 */ // GPO-1 overloaded
+
+	/**
+		\brief GPO Overload Detector Bad
+
+		General Purpose Overload Detector defective.
+
+		Remedies:
+		- Replace drive.
+	**/
+	BFld IoGPOdetector          : 1; /* 48 */ // GPO overload detector bad
+	/**
+		\brief GPO Overloaded
+
+		A General Purpose Output is overloaded.
+
+		Remedies:
+		- Check for shorts in wiring harnesses.
+		- Reduce load on output (i.e., use LED instead of
+		incandescent lights).
+	**/
+	BFld IoGPOoverload          : 1; /* 49 */ // GPO overloaded
+	/**
+		\brief Invalid Inputs
+
+		Inputs are in an invalid combination; HW enable
+		occurred while ClearPath was in motion
+
+		Remedies:
+		- Check that HW inputs match the current SW inputs
+		when switching from SW to HW enabled
+	**/
+	BFld IoInvalidInputs        : 1; /* 50 */ // IO invalid
+	/**
+		\brief Invalid Inputs - Lockdown
+
+		Inputs are in an invalid combination; HW enable
+		occurred while ClearPath was stopped
+
+		Remedies:
+		- Check that HW inputs match the current SW inputs
+		when switching from SW to HW enabled
+	**/
+	BFld IoInvalidInputsLkdn    : 1; /* 51 */ // IO invalid
+	/**
+		\brief AC Power Lost
+
+		Motor was running with AC power and AC power has been removed.
+
+		Remedies:
+		- Check AC power wiring and power quality to attached modules.
+	**/
+	BFld ACPowerLost		    : 1; /* 52 */ // AC Power lost
+	/**
+		\brief IEX Glitch Event
+
+		IEX Module is detecting link communications troubles.
+
+		Remedies:
+		- Check wiring and power quality to attached modules.
+		- Use higher quality wiring and/or shielding on link cables.
+	**/
+	BFld IEXlinkGlitch          : 1; /* 53 */ // IEX glitched detected
+	/**
+		\brief IEX Multiple Glitch Events
+
+		IEX Module is detecting excessive link communications troubles
+		and went offline.
+
+		Remedies:
+		- Check wiring and power quality to attached modules.
+		- Use higher quality wiring and/or shielding on link cables.
+	**/
+	BFld IEXlinkMultiGlitch     : 1; /* 54 */ // IEX multiple glitch event
+	BFld na55                   : 1; // 55
+
+	/**
+		\brief Commutation Bad Sequence
+
+		A bad sequence was detected from the commutation sensors.
+
+		Remedies:
+		- Check wiring and cable shield to motor.
+		- Replace motor.
+		- Check for excessive electrical noise in system.
+	**/
+	BFld MtrCommBadSeq          : 1; /* 56 */ // Commutation Bad Sequence
+	/**
+		\brief Commutation Bad State Code
+
+		An illegal '111' or '000' commutation signal pattern was detected.
+		This may occur with Hudson-style motors that are over-temp and
+		the ISC is not set up to distinguish this operational mode.
+
+		Remedies:
+		- Check wiring and cable shield to motor.
+		- Replace motor.
+		- Check for excessive electrical noise in system.
+		- Check commutation handling settings for use with Hudson motors.
+	**/
+	BFld MtrCommBadState        : 1; /* 57 */ // Commutation Bad State code
+	/**
+		\brief Vector Problem
+
+		The motor's commutation vector has drifted. This will lead to poor
+		performance. This is normally a warning indication.
+
+		Remedies:
+		- Check wiring and shield to motor.
+		- Fix defective motor
+		- Check for excessive electrical noise in system.
+		- Prevent encoder from slipping with respect to motor rotor/forcer.
+	**/
+	BFld MtrVector              : 1; /* 58 */ // Vector Problem
+	/**
+		\brief Critical Vector Problem
+
+		The motor's commutation vector has drifted beyond tolerance. This will
+		lead to poor performance. This is the shutdown due to the
+		MtrCommBadState persisting or getting worse.
+
+		Remedies:
+		- Check wiring and shield to motor.
+		- Defective motor
+		- Check for excessive electrical noise in system.
+		- Encoder slipping with respect to motor rotor/forcer.
+	**/
+	BFld MtrVectorCrit          : 1; /* 59 */ // Critical Vector Problem
+	/**
+		\brief Motor Encoder Glitch
+
+		A glitch was detected on the motor encoder signals. This glitch occurs
+		when the normal two phase sequence has transitioned through an
+		illegal state.
+
+		Remedies:
+		- Check wiring and shield to motor.
+		- Check for excessive electrical noise in system.
+		- Defective motor.
+	**/
+	BFld MtrEncGlitch           : 1; /* 60 */ // Mtr Encoder glitch
+	/**
+		\brief Motor Encoder Overspeed
+
+		The motor's encoder has exceeded the speed limit set up by the
+		Motor Speed Limit (#ISC_P_DRV_MTR_SPEED_LIM) parameter.
+
+		Remedies:
+		- Reduce command speed.
+		- Check wiring and shield to motor.
+		- Check for excessive electrical noise in system.
+		- Replace the defective encoder.
+	**/
+	BFld MtrEncOverspeed        : 1; /* 61 */ // Mtr Encoder overspeed
+	/**
+		\brief Load Encoder Glitch
+
+		 A glitch was detected on the load encoder signals. This glitch occurs
+		when the normal two phase sequence has transitioned through an
+		illegal state.
+
+		Remedies:
+		- Check wiring and shield to motor.
+		- Check for excessive electrical noise in system.
+		- Defective encoder.
+	**/
+	BFld LdEncGlitch            : 1; /* 62 */ // Ld Encoder glitch
+	/**
+		\brief Load Encoder Overspeed
+
+		The load encoder has exceeded the speed limit set up by the
+		Load Speed Limit (#ISC_P_DRV_LD_SPEED_LIM) parameter.
+
+		Remedies:
+		- Reduce command speed.
+		- Check wiring and shield to motor.
+		- Check for excessive electrical noise in system.
+		- Replace the defective encoder.
+	**/
+	BFld LdEncOverspeed         : 1; /* 63 */ // Ld Encoder overspeed
+	/**
+		\brief Motor Phase Overload
+
+		A motor phase has overloaded.
+
+		Remedies:
+		- Check wiring for shorts.
+		- Check motor tuning files.
+		- Retune the motor torque parameters.
+		- Defective motor.
+	**/
+	BFld MtrPhaseOverload       : 1; /* 64 */ // Phase overload
+	/**
+		\brief Motor Hot
+
+		A motor too hot (for models that support a motor thermostat input).
+
+		Remedies:
+		- Reduce motion stress.
+		- Add external motor cooling.
+	**/
+	BFld MtrThermalOverload     : 1; /* 65 */ // Thermal overload
+	/**
+		\brief Onboard Parameters Badly Set up
+
+		A required parameter has an illegal value.
+
+		Remedies:
+		- Reset node to factory defaults and reload a valid configuration
+		file.
+	**/
+	BFld MtrBadSetupParams      : 1; /* 66 */ // Bad Setup Parameter(s)
+	/**
+		\brief Hard Stop Broke Free
+
+		The motor has broken free during hard stop clamping. Once the motor
+		has entered the hard stopped mode, it must stay reasonably
+		still. If the coupling or end stop should break free, the axis may
+		unexpectedly accelerate.
+
+		Remedies:
+		- If this is due to clamping drift, adjust the <i> Hard Stop
+		Entry Speed</i> (#ISC_P_DRV_HARDSTOP_ENTRY_SPD) parameter upwards.
+	**/
+	BFld SvoHardStopRelease     : 1; /* 67 */ // Hardstop released
+	/**
+		\brief Tracking Problem
+
+		The position tracking error is about to exceed the critical tracking limit.
+		This usually appears in the Warning Register first.
+
+		Remedies:
+		- Reduce feed rate.
+		- Improve drive tuning.
+	**/
+	BFld SvoTracking            : 1; /* 68 */ // Tracking Problem
+	/**
+		\brief Critical Tracking Problem
+
+		The position tracking error has exceeded the critical tracking limit.
+		This is a resettable shutdown condition.
+
+		Remedies:
+		- Reduce feed rate.
+		- Improve drive tuning.
+		- Increase <i>Tracking Limit</i> (#ISC_P_DRV_TRK_ERR_LIM) to a more
+		reasonable value.
+	**/
+	BFld SvoTrackingCrit        : 1; /* 69 */ // Critical Tracking Problem
+	/**
+		\brief RMS Overload
+
+		The RMS load is approaching the critical limit.  This usually
+		appears in the Warning Register first.
+
+		Remedies:
+		- Reduce feed rate.
+		- Improve drive tuning.
+		- Use a larger motor or drive.
+	**/
+	BFld SvoRMSoverload         : 1; /* 70 */ // RMS overload
+	/**
+		\brief Critical RMS Overload
+
+		The RMS load has exceeded the critical limit. This is a resettable shutdown
+		condition.
+
+		Remedies:
+		- Reduce feed rate.
+		- Improve drive tuning.
+		- Use a larger motor or drive.
+	**/
+	BFld SvoRMScritOverload     : 1; /* 71 */ // Critical Tracking Problem
+	/**
+		\brief Dual-Loop Coupling Error Exceeded
+
+		The dual-loop coupling error between the motor and the load has
+		exceeded the <i>Coupling Limit</i> (#ISC_P_DRV_CPL_ERR_LIM) parameter.
+		The most common reason for this would involve the transmission
+		between the motor and the load. A belt break or slip of the coupler
+		would be a common problem leading to this condition.
+
+		This is a resettable shutdown condition.
+
+		Remedies:
+		- Fix the broken or slipping coupling between the motor and the
+		load.
+		- Reduce feed rate.
+		- Improve drive tuning.
+		- Increase <i>Coupling Limit</i> (#ISC_P_DRV_CPL_ERR_LIM) to a more
+		reasonable value.
+	**/
+	BFld SvoCoupling            : 1; /* 72 */ // Dual-Loop Coupling Problem
+	/**
+		\brief Step+Direction Input Noise
+
+		For nodes that support the step and direction input, this warning
+		occurs when there are detected glitches on the step and direction
+		inputs.
+
+		This is a resettable shutdown condition.
+
+		Remedies:
+		- Check wiring and shield to node.
+		- Check for excessive electrical noise in system.
+		- Defective motion controller.
+	**/
+	BFld SvoStepNoise           : 1; /* 73 */ // Step+Dir Noise Problem
+	/**
+		\brief Bus Voltage Saturation
+
+		This warning occurs when the node required full bus voltage to
+		drive the motor.
+
+		Remedies:
+		- Check power taps to bus supply.
+		- Check torque/force loop tunings.
+		- Check for mechanical issues such as binding.
+		- Check gearing and motor sizing for this application.
+		- See system configuration manual for more tips on this condition.
+	**/
+	BFld SvoVoltSat             : 1; /* 74 */ // Output Voltage Saturation
+	/**
+		\brief Torque/Force Saturation
+
+		This warning occurs when the node commanded full torque/force to
+		drive the motor.
+
+		Remedies:
+		- Check power taps to bus supply.
+		- Check torque loop tunings.
+		- Check for mechanical issues such as binding slides.
+		- Check gearing and motor sizing for this application.
+		- Check for the misapplication of any Torque/Force limiters such as
+		the Global Torque/Force limit (#ISC_P_DRV_TRQ_LIM).
+		- See system configuration manual for more tips on this condition.
+	**/
+	BFld SvoTrqSat              : 1; /* 75 */ // Torque/Force Saturated
+	/**
+		\brief Insufficient Sensorless Sweep Distance
+
+		This shutdown occurs when a motor's sensorless start fails to
+		sweep the appropriate amount.
+
+		Remedies:
+		- Check for excessive friction on axis.
+		- Check for excessive external forces acting on the axis.
+		- Check that motor wiring is correct. Phase or encoder miswiring
+		can lead to this shutdown.
+		- Verify that the configuration file is correct for the drive;
+		reload the configuration file.
+		- Check torque loop tunings.
+		- Check for the misapplication of any Torque/Force limiters such as
+		the Global Torque/Force limit (#ISC_P_DRV_TRQ_LIM).
+	**/
+	BFld NoCommSweepFailed      : 1; /* 76 */ // Sensorless sweep distance problem
+	/**
+		\brief Sensorless Motion in Wrong Direction
+
+		This shutdown occurs when a motor's sensorless start detects
+		the motor moving in the wrong direction.
+
+		Remedies:
+		- Check that motor wiring is correct. Phase or encoder miswiring
+		can lead to this shutdown.
+		- Verify that the configuration file is correct for the drive;
+		reload the configuration file.
+		- Check for excessive external forces acting on the axis.
+	**/
+	BFld NoCommSweepReversed    : 1; /* 77 */ // Sensorless sweep direction problem
+	BFld NoCommFailed    		: 1; /* 78 */ // Sensorless failed after too many retries
+	/**
+		 \brief Index Count Zero Warning
+
+		 No index pulses have been detected
+
+		 Remedies:
+		 - Return to Teknic
+	 **/
+	BFld IndexCountZeroWarn		: 1; /* 79 */ // No index detected
+	/**
+		\brief High Ambient Temperature
+
+		The node has detected an excessive ambient operating
+		temperature.  This is condition is recoverable when the
+		temperature has been sufficiently reduced.
+
+		Remedies:
+		- Verify node mounting orientation is correct.
+		- Provide more ventilation to drive.
+		- See system configuration manual for more tips on this condition.
+	**/
+	BFld TempAmbient            : 1; /* 80 */ // High Ambient Temperature
+	/**
+		\brief Heatsink Hot
+
+		The node has detected an excessive heatsink temperature. This is
+		condition is recoverable when the temperature has been sufficiently
+		reduced.
+
+		Remedies:
+		- Check mounting for lack of heat transfer to system heatsink.
+		- Verify mounting orientation is correct.
+		- Provide more ventilation to drive.
+		- See system configuration manual for more tips on this condition.
+	**/
+	BFld TempHeatsink           : 1; /* 81 */ // High Heat Sink Temp.
+	/**
+		\brief Motor Supply Bus Short
+
+		The node's bus (motor) current has exceeded maximum thresholds.
+
+		Remedies:
+		- Check phase wiring for short circuits.
+		- Check for defective motor.
+	**/
+	BFld BusOverCurrent         : 1; /* 82 */ // Power Bus Short
+	/**
+		\brief Motor Supply Bus Voltage High
+
+	   The node's bus (motor) voltage has exceeded maximum thresholds.
+This is recoverable when the bus voltage has returned to a safe level.
+
+		Remedies:
+		- Check power supply taps for proper settings.
+		- Check and/or install bus regenerated voltage bleed system.
+	**/
+	BFld BusOverVoltage         : 1; /* 83 */ // Power Bus Over-voltage
+	/**
+		\brief Motor Supply Bus Voltage Low
+
+		The node has detected a loss or brown-out of the node's bus (motor)
+		voltage. This condition will automatically clear upon restoration
+		of the bus voltage without host intervention.
+
+		Remedies:
+		- Check that power supply taps have proper settings for locale.
+		- Check and/or install bus regeneration bleed system.
+	**/
+	BFld BusVoltageLow          : 1; /* 84 */ // Power Bus Low
+	/**
+		\brief Motor Supply Bus Overloaded
+
+		The node's bus (motor) current has exceeded maximum continuous thresholds.
+
+		Remedies:
+		- Check that power supply taps have proper settings for locale.
+		- Verify the configuration file is correct for this node.
+		- Reduce motion duty cycle and/or aggressiveness.
+		- Check phase wiring for short circuits.
+	**/
+	BFld BusRMSoverload         : 1; /* 85 */ // Power Bus Overload
+	/**
+		\brief Fan Speed Low
+
+		For models that include a fan, this warning condition occurs
+		when the fan appears jammed.
+
+		Remedies:
+		- Replace drive
+	**/
+	BFld FanSpeedLow            : 1; /* 86 */ // Fan on but not up to speed
+	/**
+		\brief MtrEncIndexMissing
+
+		The motor encoder index seen when it was not expected
+		or not seen when it was expected
+
+		Remedies:
+		- Replace drive
+	**/
+	BFld MtrEncIndexMissing     : 1; /* 87 */ // Mtr index is missing
+	BFld NoCommHwErr         	: 1; /* 88 */ // Hall-less failed due to HW problem
+	BFld NoCommBusLow         	: 1; /* 89 */ // Hall-less failed due low bus voltage
+	BFld NoCommSetupErr         : 1; /* 90 */ // Hall-less failed due incorrect settings
+	/**
+		\brief Home Limit Lockdown
+
+		Attempting to move past the home position
+	**/
+	BFld HomeLimLockdown         : 1; /* 91 */ // Home Limit
+	/**
+		\brief Travel Limit Lockdown
+
+		Attempting to move past the travel limits; clears on re-enable
+	**/
+	BFld TravelLimLockdown		: 1; /* 92 */ // Travel Limit
+	BFld MtrEncIndexMisplaced	: 1; /* 93 */ //  Mtr index seen at an incorrect location
+} iscAlertFlds;
+/// \endcond																  *
+//*****************************************************************************
+
+
+
+
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
+//                      NOT DOCUMENTED ITEMS - BELOW
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
+
+//****************************************************************************
+// NAME                                                                      *
+//  iscOptionsFlds struct
+//
+// DESCRIPTION
+/**
+	\cond INTERNAL_DOC
+	\brief ISC Option Register Fields
+	
+	This structure describes the ISC specific fields within the Option 
+	Register.
+**/
+typedef struct PACK_BYTES _iscOptionsFlds
+{
+    /*                   -----------  ----------------------------------- *
+     *                         bit #  description                         *
+     *                   -----------  ----------------------------------- */
+    BFld VoltMode        : 1; // 0:  Volt mode setup
+    BFld RuntimeCal      : 1; // 1:  1=Enable run time calibration
+    BFld nDualLoop       : 1; // 2:  1=does not support dual-loop
+    BFld nClosedStepper  : 1; // 3:	1=does not support closed-loop stepper
+
+    BFld Product    : 3; // 4:  3-bit product number, 0=U/R, 1=J/K, 2=T
+                             // 5:  ""
+                             // 6:	""
+    BFld LPB             : 1; // 7:  LPB mode, 0=disable, 1=enable
+
+    BFld OptionBrd  : 3; // 8:  Installed option board (LSB)
+                             // 9:  ""
+                             // 10: Installed option board (MSB)
+    BFld VoltTable  : 1; // 11 0=S,P volt table, 1=G
+
+    BFld HwPlatform : 4; // 12: 4-bit hardware platform code (LSB)
+    						 // 13: ""
+                             // 14: ""
+                             // 15: "" (MSB)
+
+    BFld CaseType   : 3; // 16: Case type (LSB)
+                             // 17:
+                             // 18: Case type (MSB)
+    BFld FWverMask       : 1; // 19: Inhibit display of minor FW version
+
+    BFld ExtWty     : 1; // 20: Extended Wty option
+    BFld Vendor     : 4; // 21: Vendor code (LSB)
+                             // 22:  0=TEKNIC
+                             // 23:
+
+                             // 24: Vendor code (MSB)
+    BFld Debug      : 3; // 25: Debug Mode (LSB)
+                             // 26:  0,7=off
+                             // 27: Debug Mode (MSB)
+    BFld na28_31	: 4; // 28-31
+} iscOptionsFlds;
+/// \endcond																  *
+//*****************************************************************************
+
+//****************************************************************************
+// Restore byte packing
+#ifdef _MSC_VER
+#pragma pack(pop)
+#endif
+//****************************************************************************
+
+/// \cond INTERNAL_DOC
+
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * MONITOR PORT SETTINGS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+#ifndef __TI_COMPILER_VERSION__             // Not needed on dsp
+
+typedef  monTestPoints iscMonVars;
+
+typedef enum _iscTuneSyncs {
+    ISC_MON_SYNC_OFF,           //  0: None
+    ISC_MON_SYNC_POS_START = 1, //  1: At Start of Positive Move
+    ISC_MON_SYNC_NEG_START = 2, //  2: At Start of Negative Move
+    ISC_MON_SYNC_POS_END = 4,   //  4: At End of Positive Move
+    ISC_MON_SYNC_NEG_END = 8,   //  8: At End of Negative Move
+    ISC_MON_SYNC_SHUTDOWN = 16  // 16: At Shutdown
+} iscTuneSyncs;
+
+// VB Friendly structure
+/**
+    \brief Monitor Port Settings structure.
+
+    This structure controls the selection of the diagnostic test points within
+    the drive.
+**/
+typedef struct _iscMonState {
+    double          gain;       ///<  Gain setting
+    double          filterTC;   ///<  Output filter time constant (ms)
+    monTestPoints   var;        ///<  Test point to display
+    iscTuneSyncs    tuneSync;   ///<  Is a bit field
+} iscMonState;
+
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+typedef PACK_BYTES struct _iscMonNodeState {
+    nodeushort      var;        // 16-bit variable selector
+    nodelong        gain;       // 32-bit gain
+    nodeshort       filter;     // 16-bit filter TC
+    nodeshort       tuneSync;   // 16-bit (should be bitfield)
+} iscMonNodeState;
+#endif // __TI_COMPILER_VERSION__
+/// \endcond
+///**
+//    \brief Data Collection Return structure (v5.6)
+//
+//    This structure is updated with the VB friendly results of the
+//	data collection command.
+//	
+//	\note This feature appears on ISC firmware version 5.6 and later.
+//**/
+//typedef PACK_BYTES struct _iscDataCollect {
+//	double			LowPassRMS;		///< Low Pass RMS of monitor port value
+//	double			LowPassMaxPos;	///< Maximum positive of monitor port value
+//	double			LowPassMaxNeg;	///< Maximum negative of monitor port value
+//	double			HighPassRMS;	///< High Pass RMS of monitor port value
+//	double			DurationMS;		///< Duration (msec)
+//	nodelong		MaxTrackingPos;	///< Maximum positive tracking
+//	nodelong		MaxTrackingNeg;	///< Maximum negative tracking
+//} iscDataCollect;
+/// \cond INTERNAL_DOC
+/**
+    \brief Data Collection Return Payload defintion (v5.6).
+
+    This structure overlays the data returned to extract data collection
+	information to return via iscDataCollect.
+
+	\note This feature appears on ISC firmware version 5.6 and later.
+**/
+#define ISC_CMD_DATA_COLLECT_RESP_LEN 17
+typedef PACK_BYTES union _iscDataCollectPayload {
+	Uint16 buffer[(ISC_CMD_DATA_COLLECT_RESP_LEN+1)/2];
+	struct   {	 
+		// Mean^2 filtered sums during motion generation
+		nodeushort	LPmeanSqLSBs;		///< Lower 16-bit sum
+		nodeushort	HPmeanSqLSBs;		///< Lower 16-bit sum
+		// Maximums detected of monitor port channel. Cleared on read or
+		// at start of move depending on tune register setting. 
+		_iq15_s		LPmeasMaxPos;		///< Maximum LP measured (positive)
+		_iq15_s		LPmeasMaxNeg;		///< Maximum LP measured (negative)
+		// Maximums of position tracking. Cleared on read or
+		// at start of move depending on tune register setting.
+		nodeshort	TrackingMaxPos;		///< Maximum tracking (positive)
+		nodeshort	TrackingMaxNeg;		///< Maximum tracking (negative)
+		// Remainder of mean^2 data with scaling factors. These are
+		// here to preserve memory alignment and packing considerations.
+		unsigned	LPmeanSqScale:5;	///< 2^n scaling factor for HP sum
+		signed		LPmeanSqMSBs:3;		///< Upper MSBs of LP mean^2 sum
+		unsigned	HPmeanSqScale:5;	///< 2^n scaling factor for HP sum
+		signed		HPmeanSqMSBs:3;		///< Upper MSBs of HP mean^2 sum
+		unsigned	SampleTimesLSB:16;	///< Sample-times of measurement
+		signed		SampleTimesMSB:5;	///< MSBs of sample-times
+	} data;
+} iscDataCollectPkt;
+
+const int32 MAX_DATA_COLLECT_SAMPLES = (1L<<20);
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * STIMULUS GENERATOR SETTINGS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+/// Stimulus mode types
+typedef enum _stimModes {
+    STIM_OFF    = 0,            ///<  Off
+    STIM_VEL    = 1,            ///<  Velocity toggle
+    STIM_TRQ    = 2,            ///<  Torque toggle
+    STIM_POSN   = 3,            ///<  Position toggle
+    STIM_CAL    = 4,            ///<  Calibrate/test value
+    STIM_MOVE_ONCE= 5,          ///<  Profiled single move
+    STIM_MOVE_RECP= 6,          ///<  Profiled reciprocating moves
+    STIM_MOVE_REPEAT= 7,        ///<  Repeated unidirection moves
+    STIM_REF_MAX
+} stimModes;
+
+typedef enum _iscStimStatus {
+    ISC_STIM_STATUS_SST,
+    ISC_STIM_STATUS_EXTENDED
+} iscStimStatus;
+
+// Stimulus Request Packet Format used to create stimulus settings
+// and to extract stimulus state.
+
+typedef PACK_BYTES struct _iscStimCmdPkt {
+    nodeshort       Mode;       // Operational mode
+    nodeshort       Period;     // Period in sample-times
+    nodelong        Amplitude;  // Amplitude in mode units
+    // - short form "classic" request end
+    nodeshort       Slew;       // Profiled slew sample-times
+    nodeshort       Dwell;      // Dwell sample-times
+    // - short form "profiled" request end
+    nodeshort       Status;     // Status bits (status request only)
+} iscStimCmdPkt;
+#ifdef _MSC_VER
+#pragma pack(pop)
+#endif
+// Command sizes
+#define ISC_STIM_CMD_PKT_PROF_SIZE (1+4*OCTET_SIZE(nodeshort)+OCTET_SIZE(nodelong))
+#define ISC_STIM_CMD_PKT_SIZE (1+2*OCTET_SIZE(nodeshort)+OCTET_SIZE(nodelong))
+#define ISC_STIM_CMD_STATUS_SIZE 1
+#define ISC_STIM_RESP_STATUS_OCTETS 14
+
+// VB/C friendly stimulus request structure
+/**
+    \brief Stimulus Move Generator Settings structure.
+
+    This structure controls the internal tuning stimulus move generator.
+**/
+typedef struct _iscStimState {
+    double          amplitude;  ///< Amplitude mode specific units
+    double          period;     ///< Stimulus period for "toggle" types
+    long            slew;
+    long            dwell;
+    long            bits;
+    stimModes       mode;       // Operational mode
+} iscStimState;
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * DRIVE COMMAND NUMBERS
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+typedef enum _iscCmds {
+    ISC_CMD_GET_PARAM = MN_CMD_GET_PARAM0,  // 0 Get parameter (bank 0)
+    ISC_CMD_SET_PARAM = MN_CMD_SET_PARAM0,  // 1 Set parameter (bank 0)
+    ISC_CMD_GET_PARAM1 = MN_CMD_GET_PARAM1, // 2 Get parameter (bank 1)
+    ISC_CMD_SET_PARAM1 = MN_CMD_SET_PARAM1, // 3 Set parameter (bank 1)
+    ISC_CMD_NODE_STOP  = MN_CMD_NODE_STOP,  // 4 E-stop (Node Stop, Stim Cancel)
+    ISC_CMD_NET_ACCESS = MN_CMD_NET_ACCESS, // 5 Set net access level
+    ISC_CMD_USER_ID = MN_CMD_USER_ID,       // 6 Get/Set the user ID
+    ISC_CMD_CHK_BAUD_RATE = MN_CMD_CHK_BAUD_RATE, // 7 Get OK for proposed baud rate
+    ISC_CMD_ALERT_CLR = MN_CMD_ALERT_CLR,   // 8 Clear non-serious Alert reg bits
+    ISC_CMD_ALERT_LOG = MN_CMD_ALERT_LOG,   // 9 Read, clear, mark epoch of Alert log
+
+    // Start of node specific commands
+    ISC_CMD_MOTOR_FILE=MN_CMD_COMMON_END,   // 16 Motor file name
+    ISC_CMD_ADD_POSN=19,                    // 19 Adjust servo position
+    ISC_CMD_ADD_POSN_LD,                    // 20 Adjust open loop load encoder
+    ISC_CMD_SYNC_POSN,                      // 21 Synchronize position
+    ISC_CMD_GET_SET_MONITOR,                // 22 Monitor port setting
+    ISC_CMD_GET_SET_STIMULUS,               // 23 Stimulus settings
+    ISC_CMD_RE_VECTOR,                      // 24 Reset the vector search
+    ISC_CMD_DATA_ACQ,                       // 25 Data acquisition/scope feature
+    ISC_CMD_TEST_GEN,                       // 26 Test Generator
+
+	ISC_CMD_DATA_COLLECT = 28,				// 28 Special data collection command (v5.6)
+
+    // Short form position motion initiators
+    ISC_CMD_MOVE_POSN_ABS=64,//+MG_MOVE_STYLE_NORM_ABS,	// 64 Mv posn: abs
+    ISC_CMD_MOVE_POSN_REL,//64+MG_MOVE_STYLE_NORM,		// 65 Mv posn: relative
+    ISC_CMD_MOVE_POSN_ABS_TRIG,//=64+MG_MOVE_STYLE_NORM_TRIG_ABS,// 66 Mv posn: abs
+    ISC_CMD_MOVE_POSN_REL_TRIG,//=64+MG_MOVE_STYLE_NORM_TRIG,	 // 67 Mv posn: relative
+    // Short form velocity motion initiator
+    ISC_CMD_MOVE_VEL=68,                    // 68 Move velocity
+    ISC_CMD_MOVE_VEL_TRIG,                  // 69 Move velocity
+
+    // Full feature motion initiator
+    ISC_CMD_MOVE_POSN_EX,                   // 70 Move Posn: expanded
+    ISC_CMD_MOVE_VEL_EX                     // 71 Move Velocity: expanded
+} iscCmds;
+
+
+#ifndef __TI_COMPILER_VERSION__             // Skip DSP C problematic defs
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// POSITIONAL MOVE COMMANDS AND DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+// Expanded Profile move command format
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+typedef PACK_BYTES struct _iscMoveProfiledExPacket {
+    int style                 : 8;  // Format of move (mgPosnStyle)
+    int value                 :32;  // Distance of the motion
+} iscMovePosnExPacket;
+#ifdef _MSC_VER
+#pragma pack(pop)                   // Align to bytes boundaries
+#endif
+
+#endif // __TI_COMPILER_VERSION__
+
+//                                                                            *
+//*****************************************************************************
+
+enum ISC_RAS_CODES {
+    ISC_RAS_OFF = 0,                    // 0  OFF
+    ISC_RAS_3MS,                        // 1  3 ms
+    ISC_RAS_5MS,                        // 2  5 ms
+    ISC_RAS_9MS,                        // 3  9 ms
+    ISC_RAS_15MS,                       // 4  15 ms
+    ISC_RAS_24MS,                       // 5  24 ms
+    ISC_RAS_44MS                        // 6  44 ms
+};
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// TEST POINT I/O REGISTER
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+//  I/O test point register compatible with all drives.
+
+// BIT NUMBERS and MASKS
+typedef enum _TPIObits {
+    TPIO_OVERV_BIT      =0,             // Over-voltage
+    TPIO_MTR_INDX_BIT   =1,             // Motor index bit logic level
+//                      =2,
+//                      =3,
+
+    TPIO_NOT_POS_LIM_BIT=4,             // +Limit switch hit
+    TPIO_NOT_NEG_LIM_BIT=5,             // -Limit switch hit
+    TPIO_READY_OUT_BIT  =6,             // Ready (not, out)
+    TPIO_COMM_1_BIT     =7,             // Hall effect feedback 1
+
+    TPIO_COMM_2_BIT     =8,             // Hall effect feedback 2
+    TPIO_COMM_3_BIT     =9,             // Hall effect feedback 3
+    TPIO_ENABLE_IN_BIT  =10,            // Enable drive in
+    TPIO_AMP_DIS_BIT    =11,            // Amplifier disable bit
+
+    TPIO_MTR_THERM_BIT  =12,            // Motor Over Temp
+    TPIO_NOT_OVERI_BIT=13,              // Hardware fault detected (not)
+    TPIO_TEMP_FAULT_BIT =14,            // Temperature fault detected
+    TPIO_MODE_IN_BIT    =15             // Enable torque drive
+} TPIObits;
+
+// MASKS
+typedef enum {
+    TPIO_NOT_POS_LIM=(1<<TPIO_NOT_POS_LIM_BIT), // +Limit switch hit
+    TPIO_NOT_NEG_LIM=(1<<TPIO_NOT_NEG_LIM_BIT), // -Limit switch hit
+    TPIO_READY_OUT  =(1<<TPIO_READY_OUT_BIT),   // Ready output (not)
+    TPIO_MTR_THERM  =(1<<TPIO_MTR_THERM_BIT),   // Motor Over Temperature
+    TPIO_COMM_1     =(1<<TPIO_COMM_1_BIT),      // Hall effect feedback 1
+    TPIO_COMM_2     =(1<<TPIO_COMM_2_BIT),      // Hall effect feedback 2
+    TPIO_COMM_3     =(1<<TPIO_COMM_3_BIT),      // Hall effect feedback 3
+    TPIO_ENABLE_IN  =(1<<TPIO_ENABLE_IN_BIT),   // Enable drive in
+    TPIO_AMP_DIS_OUT=(1<<TPIO_AMP_DIS_BIT),     // Amp Disabled (out)
+    TPIO_NOT_OVERI  =(1<<TPIO_NOT_OVERI_BIT),   // Fault in (not)
+    TPIO_TEMP_FAULT =(1<<TPIO_TEMP_FAULT_BIT),  // Temperature fault (not)
+    TPIO_MODE_IN    =(1<<TPIO_MODE_IN_BIT),     // Torque mode enable
+    TPIO_MTR_INDX   =(1<<TPIO_MTR_INDX_BIT)     // Motor Index logic level
+} TPIOmasks;
+
+typedef union _tpIOreg {
+#ifdef __cplusplus
+public:
+#endif
+    int16 bits;
+        /*                   -----------  ----------------------------------- *
+         *                         bit #  description                         *
+         *                   -----------  ----------------------------------- */
+    struct _tpIOfld {
+        BFld OverVoltage        : 1;    // 0  Over-Voltage detected
+        BFld MtrIndex           : 1;    // 1  Motor Index track logic level
+        BFld na23               : 2;    // 2-3
+        BFld PosLimit           : 1;    // 4  Positive limit
+        BFld NegLimit           : 1;    // 5  Negative limit
+        BFld nReadyOut          : 1;    // 6  Shutdown (not, out)
+        BFld Commutation        : 3;    // 7-9  Commutation TSR code
+        BFld EnableIn           : 1;    // 10 Enable request
+        BFld AmpDisable         : 1;    // 11 Amplifier stage disable (out)
+        BFld MtrOverTemp        : 1;    // 12 Motor Over Temperature
+        BFld nOverCurrent       : 1;    // 13 Overcurrent (not)
+        BFld Thermostat         : 1;    // 14 Thermostat input
+        BFld ModeIn             : 1;    // 15 Mode line
+    } Fld;
+    #ifdef __cplusplus
+    _tpIOreg() { bits = 0; };
+    _tpIOreg(int16 initial) { bits = initial; };
+    #endif
+} tpIOreg;
+//                                                                            *
+//*****************************************************************************
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Number of bytes in each of these commands
+#define ISC_CMD_MOVE_PROF_LEN       5
+#define ISC_CMD_MOVE_SPLINE_LEN     10
+#define ISC_CMD_MOVE_PROF_EX_LEN    5
+#define ISC_CMD_MOVE_FLUSH_LEN      1
+#define ISC_CMD_MOVE_VEL_EX_LEN     8
+#define ISC_CMD_GET_PLA_LEN         2
+#define ISC_CMD_SET_PLA_BASE_LEN        2       // + fuses
+#define ISC_CMD_ADD_POSN_LEN            5
+#define ISC_CMD_SYNC_POSN_LEN       1
+#define ISC_CMD_GET_ACQUISITION_LEN 1
+#define ISC_CMD_ACQUIRE_CONTROL_LEN 5
+
+// Velocity scaling factor
+#define ISC_VEL_MOVE_SCALE (1LL<<MV_VEL_Q)  // Velocity scaling factor
+/// \endcond
+
+/// @}
+
+#endif // _PUBISCREGS_H_
+//=============================================================================
+//  END OF FILE pubIscRegs.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMnNetDef.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMnNetDef.h
new file mode 100644
index 000000000..70b398595
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMnNetDef.h
@@ -0,0 +1,579 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubMnNetDef.h $
+// $Revision: 141 $ $Date: 12/09/16 4:01p $
+// $Workfile: pubMnNetDef.h $
+//
+// DESCRIPTION:
+///		\file
+///		\brief Meridian Network definitions and data types.
+///
+///		Meridian Networked Product definitions for link layer and user APIs.
+//
+// CREATION DATE:
+//		05/18/1998 12:44:53	  	- originally cnPub.h
+//		June 05, 2009  18:18:13 - Refactored and improvements for Meridian 
+//								  products
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+#ifndef __PUBMNNETDEF_H__
+#define __PUBMNNETDEF_H__
+
+//*****************************************************************************
+// !NAME!																      *
+// 	pubMnNetDef.h headers included
+//
+	#include "tekTypes.h"
+//
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// !NAME!																	  *
+// 	pubMnNetDef.h function prototypes
+//
+
+//
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// !NAME!																	  *
+// 	pubMnNetDef.h headers
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// NETWORK DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+/**
+	\brief Supported communication rates.
+	\public
+	\ingroup SetupGrp
+
+	Select one of these items to match the capabilities of the serial port
+	attached to your network.
+**/
+typedef enum _netRates {
+	MN_BAUD_1X  =9600,			///< 1x Net Speed
+	MN_BAUD_12X =115200,		///< 12x Net Speed
+	MN_BAUD_24X =230400,		///< 24x Net Speed
+	MN_BAUD_48X =460800,		///< 48x Net Speed
+	MN_BAUD_96X =921600,		///< 96x Net Speed
+	MN_BAUD_108X=1036800		///< 108x Net Speed
+} netRates;						///< Type for netRates
+
+/// \cond INTERNAL_DOC
+
+// Initial and Post Break Network Baud Rate
+#define MN_NET_BAUD_RATE		MN_BAUD_1X
+// Divider to convert to speed switch argument
+#define MN_NET_RATE_DIVIDER		9600
+// # msec for break operation
+#define MN_BREAK_DURATION_MS 	40U
+#define MN_BREAK_EXTEND_MS 		4U
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// PACKET DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/// Max # of nodes on a network
+#define MN_API_ADDR_MASK		(MN_API_MAX_NODES-1)
+// This macro is TRUE if the <x> character is a start of packet type
+#define MN_API_IS_START_PKT(x)  (x&0x80)
+// Max # of 8-bit bytes in user payload
+#define MN_HDR_LEN_MASK			0x1fU	// Note: 8<->7 conversion rounding
+// Max 8-bit chars in MN_HDR_LEN_MASK length 7-bit packet
+#define MN_API_PAYLOAD_MAX  	((MN_HDR_LEN_MASK*7)/8)
+// Header length characters
+#define MN_API_PACKET_HDR_LEN	2U
+// Post payload character count
+#define MN_API_PACKET_TAIL_LEN	1U
+// Total maximum 8-bit packet length (less checksum)
+#define MN_API_PACKET_MAX	(MN_API_PACKET_HDR_LEN+MN_API_PAYLOAD_MAX)
+// Total maximum 7-bit items in 8-bit buffers + checksum
+#define MN_NET_PACKET_MAX	(MN_API_PACKET_HDR_LEN+MN_HDR_LEN_MASK\
+					        +MN_API_PACKET_TAIL_LEN)
+
+#define FRAME_WRITE_TIMEOUT 1000U	// max # ms for a packet to send
+#define FRAME_READ_TIMEOUT  1000U	// max # ms for to wait for packet
+#define MN_MAX_RESET_TIME	1200U	// max # ms for node to reset
+
+// Internal 'character' sizes for various "string-like" items
+#define MN_USER_ID_SIZE		13U		// User ID maximum size
+#define MN_USER_ID_SIZE_V2	25U		// User ID maximum size	(Net Protocal V2 Nodes)
+#define MN_FILENAME_SIZE	25U		// Filename maximum size
+#define MN_PART_NUM_SIZE	(MN_API_PAYLOAD_MAX-2)	// Part # string 
+
+// Hinted reasonable buffer size. 
+#define MN_UI_STR_BUF_SIZE	64U
+
+// Fixed locations in <packetbuf>.Byte.Buffer
+#define ADDR_LOC			0U		// Address location
+#define LEN_LOC				1U		// Frame length location
+#define CMD_LOC				2U		// Command location
+#define EXTEND_CODE_LOC		2U		// Command location
+#define RESP_LOC			2U		// Start of the response area
+#define RESP_BUF_START		0U		// Location response data in buf->data
+
+// type: field definitions
+typedef enum _mnPktType {
+	// Frames of these types honor flow control
+	MN_PKT_TYPE_CMD,				// 0 Command 					ND_ERR_NET,			
+	MN_PKT_TYPE_RESP,				// 1 Command Response 			ND_ERR_CMDOK,		
+	MN_PKT_TYPE_ERROR,				// 2 Error Detected 			ND_ERR_LOGIC,		
+	MN_PKT_TYPE_EXTEND_LOW,			// 3 Extension, low priority	ND_ERR_FRAME,		
+	// Frames of these types do not honor flow control				
+	MN_PKT_TYPE_ATTN_IRQ=-4,		// 4 Attn Request				ND_CTL_ATTN_REQ,	
+	MN_PKT_TYPE_SET_ADDR=-3,		// 5 Set Address				ND_CTL_SET_ADDR,	
+	MN_PKT_TYPE_TRIGGER=-2,			// 6 Event Trigger (i.e. Go)	ND_CTL_GO,			
+	MN_PKT_TYPE_EXTEND_HIGH=-1		// 7 Extension, high priority	ND_CTL_EXT			
+} mnPktType;
+
+// Macro to determine high-priority packet type
+#define MN_PKT_IS_HIGH_PRIO(pktType)	((pktType&4)!=0)
+
+
+// src: field definitions
+typedef enum _mnSrc {
+	MN_SRC_HOST,					// 0 Host initiated packet
+	MN_SRC_NODE=1					// 1 Node initiated packet (1 bit, so use -1)
+} mnSrc;
+
+// User API all purpose transmission / reception buffer. The field <bufSize> contains
+//   the current length of <buffer> in 8-bit quantities. 
+#ifdef __cplusplus
+	#define MN_TYPE 	mnPktType
+	#define MN_SRC		mnSrc
+#else
+	#define MN_TYPE		int
+	#define MN_SRC		int
+#endif
+/// \endcond
+
+/// Packet field definitions for use as an overlay for parsing.
+typedef struct _packetFields {
+	/// Destination/source address
+	unsigned Addr		: 4;
+	/// Packet Type	
+	MN_TYPE PktType  	: 3;
+	/// Start of packet indicator	
+	unsigned StartOfPacket	: 1;
+	#ifdef __TI_COMPILER_VERSION__
+		/// unpacked high order bits, set to 0
+		int Padding		: 8;	
+	#endif
+	/// Number of items in \p buffer
+	unsigned PktLen     : 5;
+	/// pkt specific modifier, otherwise 0	
+	unsigned Mode	  	: 1;
+	/// Command source field	
+	unsigned Src		: 1;
+	/// Always 0	
+	int	Zero1			: 1;	
+	#ifndef __ASM_HEADER__
+		#ifdef __cplusplus
+		/// Setup base and unused fields in a packet.
+		void SetupHdr() {
+			Mode = Zero1 = 0;
+			StartOfPacket = 1;
+		};
+
+		/// Setup headers for a fully specified packet type
+		void SetupHdr(MN_TYPE thisType, unsigned thisAddr, MN_SRC thisSrc) {
+			SetupHdr();
+			PktType = thisType;
+			Addr = thisAddr;
+			Src = thisSrc;
+		};
+
+		/// Setup headers for a packet for a host packet.
+		void SetupHdr(MN_TYPE thisType, unsigned thisAddr) {
+			SetupHdr(thisType, thisAddr, MN_SRC_HOST);
+		};
+		#endif
+	#endif
+} packetFields;				///< Type for packet fields
+
+/// Packet buffer used for driver internal and external APIs.
+typedef union _packetbuf {
+	struct _pktBytes {
+		/// Buffer of octets to or from the link
+		nodechar Buffer[MN_NET_PACKET_MAX];
+		/// Count of characters in \p Buffer
+		nodeulong BufferSize;			// Buffer size now
+	} Byte;								///< Octet accessor.
+	/// Packet field access. 
+	packetFields Fld;
+	// bufferSize should be less than MN_NET_PACKET_MAX
+#ifdef __cplusplus
+	// C++ Construct with all zeros
+	_packetbuf() {
+		for (unsigned int i=0; i<MN_NET_PACKET_MAX; i++) {
+			Byte.Buffer[i] = 0;
+		}
+		Byte.BufferSize = 0;
+	}
+	_packetbuf(void*){
+	}
+#endif
+} packetbuf;
+
+/// Option bit to OR into a parameter number to allow access to special
+/// handling for the particular types of parameters. The most common use
+/// is for parameters that have a non-volatile shadow value. Setting
+/// this mask will access the non-volatile part of the parameter without
+/// affecting the run-time value.
+#define PARAM_OPT_MASK	0x80			// Definition of parameter # option bit
+
+///	@}
+
+
+/// \cond INTERNAL_DOC
+ 
+// MN_PKT_TYPE_EXTEND_HIGH sub types
+typedef enum _mnCtlExtHigh {
+	MN_CTL_EXT_NOP,					 // 0  Do Nothing
+	MN_CTL_EXT_RESET,				 // 1  Reset Node
+	MN_CTL_EXT_REV_ADDR,			 // 2  Reverse address node
+	MN_CTL_EXT_NODE_STOP,			 // 3  E-Stop nodes
+	MN_CTL_EXT_NET_DIAG_INFO,		 // 4  Network diagnostic result
+	MN_CTL_EXT_NET_CHECK,			 // 5  Cross-net integrety check
+	MN_CTL_EXT_CRASH_TEST,			 // 6  Uncontrolled reset of node
+	MN_CTL_EXT_WATCHDOG_TERMINATION, // 7  Elicit reset via watchdog timer
+	MN_CTL_EXT_ENTER_MULTI_BYPASS,	 // 8  Put all but one node in bypass mode
+	MN_CTL_EXT_BAUD_RATE			 // 9  Change network baud rate
+} mnCtlExtHigh;
+
+// MN_PKT_TYPE_EXTEND_LOW sub types
+typedef enum _mnCtlExtLow {
+	MN_CTL_EXT_LOW_NOP,				 // 0  Do Nothing
+	MN_CTL_EXT_DATA_ACQ,			 // 1  Data acquistion packet
+	MN_CTL_EXT_PARAM_CHANGED,		 // 2  Changed parameter(s) notification
+	MN_CTL_EXT_HOST_ALIVE			 // 3  Host "ping" packet
+} mnCtlExtLow;
+
+//  Packet field definitions for use as overlay to aid parsing
+typedef struct _extendedFields {
+	mnCtlExtHigh Code	: 7;	// Extended code
+	int unused			: 1;	// 0
+	#if !(defined(_WIN32)||defined(_WIN64))
+		int Padding		: 8;	// unpacked high order bits, set to 0
+	#endif
+	unsigned OptData	: 8;	// 
+} extendedFields;
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// ERROR PACKET DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef enum _mnErrClasses {
+	ND_ERRCLS_NET,				// 00: Network detected error
+	ND_ERRCLS_CMD,				// 01: Command processing error
+	ND_ERRCLS_EXTEND=3			// 03: Extended error classes
+} mnErrClasses;
+
+
+typedef enum _mnNetErrs {
+	ND_ERRNET_FRAG,				// 00: Packet fragment detected
+	ND_ERRNET_CHKSUM,			// 01: Bad checksum detected
+	ND_ERRNET_STRAY,			// 02: Stray Data Found
+	ND_ERRNET_PORT_OVERRUN,		// 03: Serial Port overran receive
+	ND_ERRNET_FRAME,			// 04: Serial Port detected a framing error
+	ND_ERRNET_RXPARITY,			// 05: Serial Port detected a parity error
+	ND_ERRNET_BABBLE			// 06: Net detected babble
+} mnNetErrs;
+
+typedef enum _mnCmdErrs {
+	ND_ERRCMD_INTERNAL,			// 00: Generic internal error
+	ND_ERRCMD_CMD_UNK,			// 01: Command unknown on this node
+	ND_ERRCMD_ARGS,				// 02: Illegal or missing command args
+	ND_ERRCMD_WR_FAIL,			// 03: Attempt to write read-only info
+	ND_ERRCMD_EEHW,				// 04: NVM broken
+	ND_ERRCMD_ACCESS_LVL,		// 05: Insufficient access level
+	// The following MV errors must match internal numbering (plus offset)	
+	ND_ERRCMD_MV_FULL,			// 06: Move Buffers full
+	ND_ERRCMD_MV_SPEC,			// 07: Move spec error
+	ND_ERRCMD_MV_ESTOPPED,		// 08: Motion attempt in E-Stopped state
+	ND_ERRCMD_MV_RANGE,			// 09: Move distance out of range
+	ND_ERRCMD_MV_SHUTDOWN,		// 10: Motion attempt in shutdown/disabled state
+	ND_ERRCMD_IEX_ERROR,		// 11: IEX interaction while stopped
+	ND_ERRCMD_MV_BLOCKED,		// 12: Motion attempt in non-disabling shutdown
+	ND_ERRCMD_MV_HOMING,		// 13: Motion attempt while homing
+					// NOTE: leave gap for additional MV errors
+	ND_ERRCMD_DRV_IN_MOTION=16	// 16: Command not accepted due to move in progress
+} mnCmdErrs;
+// Offset to add to internal MV errors to translate them into mnCmdErrs
+#define MV_ERR_BASE	(ND_ERRCMD_MV_FULL-1)
+
+// Overlay on data
+typedef union _netErrGeneric {
+	nodeushort bits;				// Broad 16-bit view
+	struct {
+		unsigned ErrCode	: 5;	// Basic error code
+		mnErrClasses ErrCls	: 2;	// Error Class
+		unsigned Optional	: 7;	// (Optional)
+	} Fld;
+} netErrGeneric;
+// Optional depends on the mnNetErrs code
+// For ND_ERRNET_STRAY, this will be filled in with the stray count
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// SET ADDRESS PACKET DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// MN_PKT_TYPE_SET_ADDR packet field definitions
+typedef union _setAddrPkt {
+	nodechar bytes[3];
+	struct {
+			unsigned addr		: 4;	// Destination/source address
+			MN_TYPE pktType  	: 3;	// Packet Type
+			int StartOfPacket	: 1;	// Start of packet indicator
+
+			unsigned PktLen     : 5;	// Number of items in \p buffer
+			unsigned Err    	: 1;	// Error in configuration flag
+			MN_SRC Src			: 1;	// Command source field
+			int	Zero1			: 1;	// Always 0
+	} Fld;
+} setAddrPkt;
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// CORE Command set. If implemented by the a node, these are their command
+// numbers.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef enum _mncmds {
+	MN_CMD_GET_PARAM0 		= 0,	// Get a parameter from bank 0  (0-255)
+	MN_CMD_SET_PARAM0 		= 1,	// Set a parameter from bank 0  (0-255)
+	MN_CMD_GET_PARAM1	    = 2,	// Get parameter from bank 1
+	MN_CMD_SET_PARAM1		= 3,	// Set parameter from bank 1 (256-511)
+	MN_CMD_NODE_STOP		= 4,	// Stop node motion (aka Stim Cancel)
+	MN_CMD_NET_ACCESS		= 5,	// Set net access level
+	MN_CMD_USER_ID			= 6,	// Get/Set the user ID
+	MN_CMD_CHK_BAUD_RATE	= 7,	// Get OK for proposed baud rate
+	MN_CMD_ALERT_CLR		= 8,	// Clear non-serious Alert reg bits
+	MN_CMD_ALERT_LOG		= 9,	// Read, clear & mark epoch of Alert log
+	MN_CMD_PLA				=10,	// PLA setup and inspection
+	MN_CMD_GET_PARAM2		=11,	// Get a parameter from bank 2 (512-639)
+	MN_CMD_SET_PARAM2		=12,	// Set a parameter from bank 2 (512-639)
+	MN_CMD_COMMON_END		=16,	// Node specific cmds can start here
+	ASUM_CMD				=80		// Run an ASUM command (send data to app proc)	
+} mncmds; 
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// CORE Parameter set. If implemented by the a node, these are their command
+// numbers.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// CORE parameters
+typedef enum _mnparams {
+	MN_P_NODEID,					// 0  00 Device ID
+	MN_P_FW_VERSION,				// 1  01 FW version
+	MN_P_HW_VERSION,				// 2  02 HW version
+	MN_P_RESELLER_ID,				// 3  03 Reseller ID
+	MN_P_SER_NUM,					// 4  04 Unit serial number
+	MN_P_OPTION_REG,				// 5  05 Unit options
+	MN_P_ROM_SUM_ACK,				// 6  06 Firmware update ack
+	MN_P_ROM_SUM,					// 7  07 Firmware checksum
+	MN_P_SAMPLE_PERIOD,				// 8  08 Sample period (nsec)
+	MN_P_ALERT_REG,					// 9  09 Shutdown register
+	MN_P_STOP_TYPE,					// 10 0a Node Stop Type
+	MN_P_WATCHDOG_TIME,				// 11 0b Watchdog time constant
+	MN_P_NET_STAT,					// 12 0c Network Status
+	MN_P_STATUS_ACCUM_REG,			// 13 0d Status accum register
+	MN_P_STATUS_ATTN_RISE_REG,		// 14 0e Status attn/rise register
+	MN_P_STATUS_ATTN_MASK,			// 15 0f Status mask register
+	MN_P_STATUS_RT_REG,				// 16 10 Status reg (realtime)
+	MN_P_TIMESTAMP,					// 17 11 8-bit timestamp
+	MN_P_TIMESTAMP16,				// 18 12 16-bit timestamp
+	MN_P_PART_NUM,					// 19 13 Part Number String
+	MN_P_EE_UPD_ACK,				// 20 14 EE Update Acknowlegde
+	MN_P_EE_VER,					// 21 15 EE Version Number
+	MN_P_STATUS_FALL_REG,			// 22 16 Status fall register
+	MN_P_HW_CONFIG_REG,				// 23 17 Hardware config/setup reg
+	MN_P_APP_CONFIG_REG,			// 24 18 Feature config/setup reg
+    MN_P_OUT_REG			= 32,   // 32 20 Output register
+    MN_P_OUT_RISE_REG,              // 33 21 Output rise edge
+    MN_P_OUT_FALL_REG,              // 34 22 Output fall edge
+    MN_P_CTL_STOP_OUT_REG,          // 35 24 Controlled output register
+	MN_P_USER_OUT_REG,				// 36 24 User output register
+	MN_P_WARN_REG			= 70,	// 70 46 Warning register
+	MN_P_WARN_MASK_REG		= 71,	// 71 47 Warning register mask
+	MN_P_ALERT_MASK_REG		= 72,	// 72 48 Alert register mask
+
+
+	MN_P_ON_TIME			= 89,	// 89 Unit powered on time
+	MN_P_USER_RAM0			= 90,	// 90 User RAM parameter
+	MN_P_USER_DATA_NV0,				// 91 User NV (13-bytes)
+	MN_P_USER_DATA_NV1,				// 92 User NV (13-bytes)
+	MN_P_USER_DATA_NV2,				// 93 User NV (13-bytes)
+	MN_P_USER_DATA_NV3,				// 94 User NV (13-bytes)
+
+	MN_P_NETERR_APP_CHKSUM=104,		// 104 68 Application Net Checksum counter
+	MN_P_NETERR_APP_FRAG,			// 105 69 Application Net Fragment counter
+	MN_P_NETERR_APP_STRAY,			// 106 6a Application Net Stray data counter
+	MN_P_NETERR_APP_OVERRUN,		// 107 6b Application Net Overrun counter
+
+	MN_P_NETERR_DIAG_CHKSUM=108,	// 108 6c Diagnostic Net Checksum counter
+	MN_P_NETERR_DIAG_FRAG,			// 109 6d Diagnostic Net Fragment counter
+	MN_P_NETERR_DIAG_STRAY,			// 110 6e Diagnostic Net Stray data counter	
+	MN_P_NETERR_DIAG_OVERRUN,		// 111 6f Diagnostic Net Overrun counter	
+	MN_P_NETERR_LOW_VOLTS=116		// 116 74 Diagnostic Net Brownout counter
+} mnParams;
+
+// Version 1 common parameter order
+typedef enum _mnParams1 {
+	MN_P1_NODEID,					// 0  00 Device ID
+	MN_P1_FW_VERSION,				// 1  01 FW version
+	MN_P1_HW_VERSION,				// 2  02 HW version
+	MN_P1_RESELLER_ID,				// 3  03 Reseller ID
+	MN_P1_SER_NUM,					// 4  04 Unit serial number
+	MN_P1_OPTION_REG,				// 5  05 Unit options
+	MN_P1_ROM_SUM_ACK,				// 6  06 Firmware update ack
+	MN_P1_ROM_SUM,					// 7  07 Firmware checksum
+	MN_P1_SAMPLE_PERIOD,			// 8  08 Sample period (nsec)
+	MN_P1_ALERT_REG,				// 9  09 Shutdown register
+	MN_P1_STOP_TYPE,				// 10 0a Node Stop Type
+	MN_P1_WATCHDOG_TIME,			// 11 0b Watchdog time constant
+	MN_P1_NET_STAT,					// 12 0c Network Status
+	MN_P1_STATUS_ACCUM_REG,			// 13 0d Status accum register
+	MN_P1_STATUS_ATTN_RISE_REG,		// 14 0e Status attn/rise register
+	MN_P1_STATUS_ATTN_MASK,			// 15 0f Status mask register
+	MN_P1_STATUS_RT_REG,			// 16 10 Status reg (realtime)
+	MN_P1_TIMESTAMP,				// 17 11 8-bit timestamp
+	MN_P1_TIMESTAMP16,				// 18 12 16-bit timestamp
+	MN_P1_PART_NUM,					// 19 13 Part Number String
+	MN_P1_EE_UPD_ACK,				// 20 14 EE Update Acknowlegde
+	MN_P1_EE_VER,					// 21 15 EE Version Number
+	MN_P1_STATUS_FALL_REG,			// 22 16 Status fall register
+	MN_P1_HW_CONFIG_REG,			// 23 17 Hardware config/setup reg
+	MN_P1_APP_CONFIG_REG,			// 24 18 Feature config/setup reg
+	MN_P1_WARN_REG,					// 25 19 Warnings accumulated register
+	MN_P1_WARN_RT_REG,				// 26 1a Warning real-time register
+	MN_P1_WARN_MASK_REG,			// 27 1b Warning Attn Mask register
+	MN_P1_ALERT_MASK_REG,			// 28 1c Alert Attn Mask register
+	MN_P1_ON_TIME,					// 29 1d Powered On Time
+
+	MN_P1_USER_RAM0			= 31,	// 31 1F User RAM parameter
+	MN_P1_USER_DATA_NV0,			// 32 20 User NV (13-bytes)
+	MN_P1_USER_DATA_NV1,			// 33 21 User NV (13-bytes)
+	MN_P1_USER_DATA_NV2,			// 34 22 User NV (13-bytes)
+	MN_P1_USER_DATA_NV3,			// 35 23 User NV (13-bytes)
+	MN_P1_NETERR_APP_CHKSUM,		// 36 24 Application Net Checksum counter
+	MN_P1_NETERR_APP_FRAG,			// 37 25 Application Net Fragment counter
+	MN_P1_NETERR_APP_STRAY,			// 38 26 Application Net Stray data counter
+	MN_P1_NETERR_APP_OVERRUN,		// 39 27 Application Net Overrun counter
+	MN_P1_NETERR_DIAG_CHKSUM,		// 40 28 Diagnostic Net Checksum counter
+	MN_P1_NETERR_DIAG_FRAG,			// 41 29 Diagnostic Net Fragment counter
+	MN_P1_NETERR_DIAG_STRAY,		// 42 2a Diagnostic Net Stray data counter	
+	MN_P1_NETERR_DIAG_OVERRUN,		// 43 2b Diagnostic Net Overrun counter	
+	MN_P1_NETERR_LOW_VOLTS,			// 44 2c Diagnostic Net Brownout counter
+
+	MN_P1_USER_OUT_REG,				// 50 32 User output register
+	MN_P1_CTLD_OUT_REG,				// 51 33 Controlled output register
+	MN_P1_OUT_REG,					// 52 34 Real-Time Output Register
+	MN_P1_OUT_RISE_REG,				// 53 35 Accumulated risen outputs
+	MN_P1_OUT_FALL_REG				// 54 36 Accumulated fallen outputs
+} mnParams1;
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Network Access Status and Identifier information overlay
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Sources types for execContext.source
+typedef enum _mnNetSrcs {
+	MN_SRC_APP_NET,
+	MN_SRC_DIAG_NET,
+	MN_SRC_UNKNOWN_NET=-1				// -1 Unknown source
+} mnNetSrcs;
+
+// Net access level constants for use with MN_CMD_NET_ACCESS command
+typedef enum _mnAccessLvls {
+	MN_ACCESS_LVL_READ_ONLY=0,			// Read-only access - current net
+	MN_ACCESS_LVL_TUNE=1,				// Allow tuning param access - current net
+	MN_ACCESS_LVL_FULL=2,				// All commands and modes work - current net
+	MN_ACCESS_LVL_FACTORY=3				// Factory access
+} mnAccessLvls;
+
+#ifdef _cplusplus
+	#define MN_NSRCS mnNetSrcs
+#else
+	#define MN_NSRCS unsigned
+#endif
+
+typedef union _mnNetStatus {
+	Uint16 bits;
+	struct {
+		mnNetSrcs NetSource		: 2;	// Network Source
+		unsigned NetAccessApp	: 2;	// Access level (app)
+		unsigned NetAccessDiag	: 2;	// Access level (diag)
+		unsigned NetParamVer	: 2;	// Base parameter version
+	} Fld;
+} mnNetStatus;
+#define NETDIAG_SPARE_WORDS				7
+/// \endcond
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+	\brief Network Diagnostic statistics.
+
+	This container hold the results of collected network diagnostics. It
+	has the statistics for the \e Application and \e Diagnostic nets.
+*/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+typedef struct _mnNetDiagStats {		// Application Network
+										// -------------------
+	Uint16 AppNetFragPktCtr;			///< Fragment counter for Application Channel
+	Uint16 AppNetBadChksumCtr;			///< Checksum counter for Application Channel
+	Uint16 AppNetStrayCtr;				///< Stray data counter for Application Channel
+	Uint16 AppNetOverrunCtr;			///< Overrun counter for Application Channel
+										
+										// Diagnostic Network
+										// -------------------
+	Uint16 DiagNetFragPktCtr;			///< Fragment counter for Application Channel
+	Uint16 DiagNetBadChksumCtr;			///< Checksum counter for Application Channel
+	Uint16 DiagNetStrayCtr;				///< Stray data counter for Application Channel
+	Uint16 DiagNetOverrunCtr;			///< Overrun counter for Application Channel
+	Uint16 NetVoltsLowCtr;				///< Network Power Low for the link
+	Uint16 Spare[NETDIAG_SPARE_WORDS];	///< Future expansion
+
+	#ifndef __ASM_HEADER__
+		#ifdef __cplusplus
+			void Clear() {
+				AppNetFragPktCtr
+				= AppNetBadChksumCtr
+				= AppNetStrayCtr
+				= AppNetOverrunCtr
+				= DiagNetFragPktCtr
+				= DiagNetBadChksumCtr
+				= DiagNetStrayCtr
+				= DiagNetOverrunCtr = 0;
+				NetVoltsLowCtr = 0;
+			};
+			
+			_mnNetDiagStats() {
+				Clear();
+			};
+		#endif
+	#endif
+} mnNetDiagStats;
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
+// 						  COMMON SCALING FACTORS
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
+/// \cond INTERNAL_DOC
+#define MN_POSN_Q	0
+/// \endcond 
+ 
+// 																			  *
+//*****************************************************************************
+#endif
+
+
+//============================================================================= 
+//	END OF FILE pubMnNetDef.h
+// ============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMonPort.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMonPort.h
new file mode 100644
index 000000000..42ac75b4c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMonPort.h
@@ -0,0 +1,107 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubMonPort.h $
+// $Revision: 12 $ $Date: 12/09/16 4:02p $
+// $Workfile: pubMonPort.h $
+//
+/// \file
+/// \brief Monitor Port types and constants
+//
+// NAME
+//		pubMonPort.h
+//
+// DESCRIPTION:
+///		Public monitor port definitions.
+//
+// CREATION DATE:
+//		10/08/2009 16:24:52
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2009-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+//*****************************************************************************
+#ifndef __PUBMONPORT_H__
+#define	__PUBMONPORT_H__
+
+
+//*****************************************************************************
+// NAME																	      *
+// 		pubMonPort.h channel definitions
+//
+// DESCRIPTION
+// 		Supported channel for data acquisition and the monitor port
+typedef enum _monTestPoints {
+    MON_INTERNAL0 = 0,              // 0 : internal mode
+    MON_INTERNAL1 = 1,              // 1 : internal mode
+    MON_VEL_MEAS,                   // 2 : Velocity, measured (steps/ms)
+    MON_VEL_CMD,                    // 3 : Velocity, commanded (steps/ms)
+    MON_VEL_STEP,                   // 4 : Velocity, input (steps/ms)
+    MON_VEL_TRK,                    // 5 : Velocity, tracking (steps/ms)
+    MON_POSN_TRK,                   // 6 : Position, tracking (quad counts)
+    MON_TRQ_MEAS,                   // 7 : Torque, measured (% of max)
+    MON_TRQ_CMD,                    // 8 : Torque, commanded (% of max)
+    MON_CALIBRATE,                  // 9 : Stimulus generator (% of max)
+    MON_ANALOG_IN,                  // 10: Analog input (% of max)
+    MON_SINE_R,                     // 11: Vector R sin (% of max)
+    MON_COS_R,                      // 12: Vector R cos (% of max)
+    MON_VOLT_D,                     // 13: Volts D (% of max)
+    MON_VOLT_Q,                     // 14: Volts Q (% of max)
+    MON_SGN_CMD_VEL,                // 15: SGN(cmd vel)
+    MON_SGN_CMD_STEP,               // 16: SGN(step vel)
+    MON_INTEGRATOR,                 // 17: Integrator
+    MON_POSN_MEAS,                  // 18: Position, measured (quad counts)
+    MON_VEL_TRK_SERVO,              // 19: Servo velocity tracking (steps/ms)
+    MON_JRK_CMD,                    // 20: Jerk, commanded (Mquads/sec^3)
+    MON_ACC_CMD,                    // 21: Acceleration, commanded (quads/sec^2)
+    MON_TRQ_D_MEAS,                 // 22: Torque, measured D (% of max)
+    MON_VOLTS_MAX,                  // 23: Maximum phase voltage (% of max)
+    MON_NOT_INRANGE,                // 24: Not In-Range
+    MON_NOT_MOVEDONE,               // 25: Not Move Done
+    MON_NOT_HLFB,                   // 26: Not HLFB
+    MON_POSN_DIR_TRK,				// 27: Directional Tracking, Load
+    MON_TRQ_TRK,                    // 28: Torque tracking
+    MON_COUPLING,   	            // 29: Motor-Load coupling
+    MON_POSN_DIR_TRK_MTR,			// 30: Directional Tracking, Motor
+    MON_POSN_TRK_MTR,				// 31: Tracking, Motor
+
+    MON_TRK_LD=33,					// 33: Tracking, Load
+    MON_TRQ_TRK_PEAK,				// 34: Peak Torque Tracking
+    MON_TRQ_MEAS_PEAK,				// 35: Peak Torque Measured
+    MON_BUS_VOLTS,					// 36: Bus Voltage
+    MON_SHOW_HIGH_PASS = 8192,		// Show high pass monitor port data
+	MON_SAVE_NV_MASK = 16384,		// OR with testpoint to save in Non-Volatile
+	MON_OPTION_MASKS = MON_SHOW_HIGH_PASS|MON_SAVE_NV_MASK
+} monTestPoints;
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 		pubMonPort.h tune sync sources
+//
+// DESCRIPTION
+// 		Supported channel for data acquisition and the monitor port
+typedef union _tuneSyncs {
+	unsigned bits;
+	struct {
+		int PosStart	: 1;				// Pulse at start of pos cmd
+		int NegStart	: 1;				// Pulse at start of neg cmd
+		int PosEnd		: 1;				// Pulse at end of pos cmd
+		int NegEnd		: 1;				// Pulse at end of neg cmd
+		int OnShutdown	: 1;				// Pulse at shutdown	
+	} Fld;
+} tuneSyncs;
+//																			  *
+//*****************************************************************************
+
+#endif
+//=============================================================================
+//	END OF FILE pubMonPort.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMotion.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMotion.h
new file mode 100644
index 000000000..0a7dab9f1
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubMotion.h
@@ -0,0 +1,763 @@
+
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubMotion.h $
+// $Revision: 70 $ $Date: 12/09/16 4:03p $
+// $Workfile: pubMotion.h $
+/**
+	\file pubMotion.h
+
+	Motion Related Definitions
+
+	This C/C++ header defines the data types related to the motion programming
+	interfaces.
+**/
+// NAME
+//      pubMotion.h
+//
+// DESCRIPTION
+//     Suite of motion related constants.
+//
+// CREATION DATE:
+//      06/26/2008 18:01:23
+//      09/24/2009 16:56:34 Refactored from iCmdController.h
+//
+// COPYRIGHT NOTICE:
+//      (C)Copyright 2008-2018 Teknic, Inc.  All rights reserved.
+//
+//      This copyright notice must be reproduced in any copy, modification,
+//      or portion thereof merged into another program. A copy of the
+//      copyright notice must be included in the object library of a user
+//      program.
+//                                                                            *
+//*****************************************************************************
+#ifndef __PUBMOTION_H__
+#define __PUBMOTION_H__
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  pubMotion.h headers
+//
+    #include "tekTypes.h"
+//                                                                            *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  pubMotion.h function prototypes
+//
+//                                                                            *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  pubMotion.h constants
+//
+
+															/** \cond INTERNAL_DOC **/
+#define MV_VEL_Q    17                  // Q factor for velocity
+															/** \endcond **/
+
+#if defined(_WIN32)||defined(_WIN64)
+#pragma pack(push,1)                // Align to bytes boundaries
+#endif
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+															/** \cond ISC_DOC **/
+/**
+    Positional Move "Shapes" and types as an integer code.
+
+    This enumerated list provides an easy-to-specify list of valid
+    motion type codes. Using the base level #mgPosnStyle structure provides
+    an easy-to-use translation from this enumerated list to the proper
+    set of bit fields. The generic field access should be avoided as
+    this structure allows for invalid combinations of motion styles and
+    options.
+
+	\ref ISCmovePositionalPage
+**/
+typedef enum _mgPosnStyles {
+// Absolute moves
+    MG_MOVE_STYLE_NORM_ABS,             ///< Move triangle / trapezoid abs target
+    MG_MOVE_STYLE_ASYM_ABS=0x08,        ///< Move / programmable Acc/Dec limit  abs target
+    MG_MOVE_STYLE_TAIL_ABS=0x10,        ///< Move / tail velocity segment  abs target
+    MG_MOVE_STYLE_HEAD_ABS=0x20,        ///< Move / head velocity segment  abs target
+    MG_MOVE_STYLE_HEADTAIL_ABS=0x30,    ///< Move / head-tail velocity segments  abs target
+// Relative moves
+    MG_MOVE_STYLE_NORM=0x01,            ///< Move triangle / trapezoid
+    MG_MOVE_STYLE_ASYM=0x09,            ///< Move / programmable Acc/Dec limit
+    MG_MOVE_STYLE_TAIL=0x11,            ///< Move / tail velocity segment
+    MG_MOVE_STYLE_HEAD=0x21,            ///< Move / head velocity segment
+    MG_MOVE_STYLE_HEADTAIL=0x31,        ///< Move / head-tail velocity segments
+// Absolute moves/trigger
+    MG_MOVE_STYLE_NORM_TRIG_ABS=0x02,   ///< Move triangle / trapezoid abs target/trigger
+    MG_MOVE_STYLE_ASYM_TRIG_ABS=0x0a,   ///< Move / programmable Acc/Dec limit  abs target abs target/trigger
+    MG_MOVE_STYLE_TAIL_TRIG_ABS=0x12,   ///< Move / tail velocity segment abs target/trigger
+    MG_MOVE_STYLE_HEAD_TRIG_ABS=0x22,   ///< Move / head velocity segment abs target/trigger
+    MG_MOVE_STYLE_HEADTAIL_TRIG_ABS=0x32,///< Move / head-tail velocity segments  abs target
+// Relative moves/trigger
+    MG_MOVE_STYLE_NORM_TRIG=0x03,       ///< Move triangle / trapezoid  / trigger
+    MG_MOVE_STYLE_ASYM_TRIG=0x0b,       ///< Move / programmable Acc/Dec limit /trigger
+    MG_MOVE_STYLE_TAIL_TRIG=0x13,       ///< Move / tail velocity segment / trigger
+    MG_MOVE_STYLE_HEAD_TRIG=0x23,       ///< Move / head velocity segment / trigger
+    MG_MOVE_STYLE_HEADTAIL_TRIG=0x33,   ///< Move / head-tail velocity segments / trigger
+// Modifier
+    MG_MOVE_STYLE_DWELL_OPTION = 0x04   ///< Create post move dwell (newer f/w)
+} mgPosnStyles;
+
+#define MG_REL_TRIG_MASK    0x3
+															/** \endcond **/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+															/** \cond ISC_DOC **/
+/**
+    Positional Move "Shapes" Data Structure.
+
+    For most applications it is simpler to pass in the #mgPosnStyles code
+    for any function to select a desired style.
+
+    For example:
+    \code
+    iscForkMoveEx(someNode, 1000, MG_MOVE_STYLE_HEADTAIL);
+    \endcode
+
+    \note Some combinations of style selectors are not valid.
+**/
+typedef union _mgPosnStyle {
+    /// Move Style as an integer code.
+    mgPosnStyles styleCode;         // Move style
+    /// Field oriented style selectors
+    struct {
+        unsigned	relative    :1;     ///< Relative moves
+		/**
+			Wait for Trigger
+
+			Cause this move to await a trigger event before starting. This
+			will cause the #nonAttnReg::TriggerArmed field to set until
+			a trigger event releases this move.
+
+			\see \ref netTrigger
+		**/
+        unsigned	wait        :1;
+        unsigned	dwell       :1;     ///< Create post move dwell
+        unsigned	asym        :1;     ///< Absolute moves
+        unsigned	tail        :1;     ///< Tail section
+        unsigned	head        :1;     ///< Head section
+		unsigned	repeat		:1;		///< Cause move to repeat/dwell
+		unsigned	reciprocate :1;		///< Reciprocating moves/repeat
+    } fld;                          ///< Field access to move styles.
+    #ifdef __cplusplus
+        /// Useful converter to convert integer code to style container.
+        _mgPosnStyle(mgPosnStyles how) {styleCode = how;}
+        _mgPosnStyle() {styleCode = MG_MOVE_STYLE_NORM;}
+        void operator=(const mgPosnStyles &how) {styleCode = how;}
+    #endif
+} mgPosnStyle;
+															/** \endcond **/
+															/** \cond INTERNAL_DOC **/
+// Structure based move API
+typedef struct _mgMoveProfiledInfo {
+    mgPosnStyles    type;           // Motion style: trap,head,tail, etc.
+    nodelong           value;       // Position Target (based on style)
+    #ifdef __cplusplus
+        _mgMoveProfiledInfo() {type = MG_MOVE_STYLE_NORM;}
+    #endif
+} mgMoveProfiledInfo;
+															/** \endcond **/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+															/** \cond ISC_DOC **/
+/**
+	Velocity Move Styles and types as an integer code.
+
+	This enumerated type describes the velocity move styles.  This allows
+	a simple conversion to the #mgVelStyle union.
+
+	There are two basic velocity style moves:
+		- Classic velocity mode
+		- Skyline velocity mode
+
+	\ref ISCmoveVelocityPage
+	\ref ISCmoveSkylinePage
+
+**/
+typedef enum _mgVelStyles {
+	/**
+	Change the commanded velocity immediately.
+	**/
+    MG_MOVE_VEL_STYLE,                  // Regular change to new velocity
+	/**
+	Change to new commanded velocity after trigger event.
+	**/
+    MG_MOVE_VEL_STYLE_TRIG = 0x2,       // Start motion on trigger event
+	/**
+	Change to new commanded velocity and travel the commanded distance.
+	**/
+    MG_MOVE_SKY_STYLE = 0x4,			// Regular move segment
+	/**
+	Change to new commanded velocity and travel to the commanded location.
+	**/
+    MG_MOVE_SKY_STYLE_ABS = 0x5,		// Absolute position move segment
+	/**
+	Change to new velocity and travel the commanded distance after trigger.
+	**/
+    MG_MOVE_SKY_STYLE_TRIG = 0x6,		// Regular move segment
+	/**
+	Change to new velocity and travel to the commanded location after trigger.
+	**/
+    MG_MOVE_SKY_STYLE_TRIG_ABS = 0x7,	// Absolute position move segment
+    /**
+     * Regular velocity with no positional tracking shutdown
+     */
+    MG_MOVE_VEL_STYLE_NO_TRK = 0x8
+} mgVelStyles;
+
+/**
+	This container holds the velocity move type specification.
+
+	\remark With C++ you can use a #mgVelStyles enumeration to initialize
+	this container using the constructor.
+**/
+typedef union _mgVelStyle {
+    mgVelStyles styleCode;      ///< Move style
+    struct {
+  		/**
+			Absolute Position.
+
+			If this field is cleared, the target position is the position
+			value relative to the start of move. If set, the position is the
+			absolute position at the end of the move.
+
+			\note This field is used only when \c skyline field is set.
+		**/
+        unsigned absolute	:1; 
+		/**
+			Trigger Move.
+
+			Cause this move to await a trigger event before starting. This
+			will cause the #nonAttnReg::TriggerArmed field to set until
+			a trigger event releases this move.
+
+			\see \ref netTrigger
+		**/
+        unsigned wait		:1;     // Wait for trigger
+		/**
+			Skyline Move.
+
+			This field specifies a move segment that will attempt a ramp to
+			the requested speed toward the target position using the current 
+			acceleration limit and continue at this speed until it reaches 
+			the target position.  When the position is reached this move is 
+			complete and the next segment will begin. If the motion 
+			specification is not achievable due to too short of distances or 
+			insufficient acceleration values, the move may end not achieving 
+			the desired velocity. If the terminating segment cannot achieve 
+			the desired position within the current acceleration constraint, 
+			the acceleration will be increased to hit the target without 
+			overshooting and the #alertReg::FwMoveSpecAltered condition is 
+			raised to signal the violation of the constraints. 
+
+		    \image html "Move_Skyline.png"
+		    \image latex "Move_Skyline.eps"
+			
+			\remark If the #mgVelStyle::absolute field is set this move
+			segment specifies the end position as an absolute position versus
+			relative to the start of the move.
+		**/
+        unsigned skyline		:1;     // Skyline move segment
+        /**
+         * 	Suppress Tracking Shutdown
+         *
+         * 	This field tells the drive to ignore positional tracking
+         * 	errors.
+         */
+        unsigned noTrackingShutdown	:1;
+
+    } styles;					///< Style type bit fields.
+														/** \endcond **/
+														/** \cond INTERNAL_DOC **/
+	#ifdef __cplusplus
+        _mgVelStyle(mgVelStyles how) {styleCode = how;}
+        _mgVelStyle() {styleCode = MG_MOVE_VEL_STYLE;}
+        void operator=(const mgVelStyles &how) {styleCode = how;}
+    #endif
+} mgVelStyle;
+														/** \endcond **/
+
+
+														/** \cond ISC_DOC **/
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Jerk Limiting Selections
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+//*****************************************************************************
+// NAME                                                                       *
+//  rasSelector union
+//
+// DESCRIPTION
+///     \brief gStop/RAS type and value specification
+
+typedef union _rasSelector {        // Output RAS value
+    Uint32 Bits;                    ///< gStop/RAS selection code number.
+} rasSelector;
+//                                                                            *
+//*****************************************************************************
+														/** \endcond **/
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+//					 NODE STOP FEATURE DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//      mgStopStyles enumeration
+//
+// DESCRIPTION
+/**
+	\brief Motion stop strategies.
+
+	This enumeration defines the action taken by the move generator when
+	a node stop is issued.
+**/
+typedef enum _mgStopStyles {
+	/**
+		Kill Motion Abruptly
+
+		This style terminates the motion immediately and flushes
+		any pending motion buffered up.
+	**/
+	MG_STOP_STYLE_ABRUPT,              // 0 Kill Motion Abruptly
+	/**
+		Kill Motion with Deceleration
+
+		This style ramps the speed down to zero using the EStopDecel rate.
+	**/
+	MG_STOP_STYLE_RAMP,                // 1 Kill Motion with the greater of the active and stop decel limits
+															/** \cond INTERNAL_DOC **/
+	MG_STOP_STYLE_AFTER_CYCLE,         // 2 After cycle completes
+															/** \endcond **/
+	/**
+		Ignore Node Stop
+
+		This style tells this node to ignore the default node
+		stop requests.
+	**/
+	MG_STOP_STYLE_IGNORE,              // 3 Node stop ignore
+	/**
+		Kill Motion with Deceleration at the active decel rate
+
+		This style ramps the speed down to zero using the deceleration rate
+		of the active move.
+	**/
+	MG_STOP_STYLE_RAMP_AT_DECEL        // 4 Kill Motion with active decel limit
+} mgStopStyles;
+//                                                                            *
+//*****************************************************************************
+
+
+															/** \cond ISC_DOC **/
+//*****************************************************************************
+// NAME                                                                       *
+//      iscStopFlds structure
+//
+// DESCRIPTION
+/**
+	\brief Meridian ISC stop type definition.
+
+	This bit encoded register is used to specify the actions a motor will take
+	when a default or explicit node stop action occurs.
+**/
+typedef struct _iscStopFlds {
+/**
+	Move Generator response
+
+	This is what the motion generator will do for all non-Clearing actions.
+**/
+	mgStopStyles MotionAction : 3;
+	// - - - - - - - - - - - -
+	// Stop type modifiers
+	// - - - - - - - - - - - -
+	/// Clear modifier(s)
+	unsigned Clear : 1;
+	/// Lockout subsequent motion and enter E-Stopped State
+	unsigned MotionLock : 1;
+	/// Force the <i>Output Register</i> to the <i>Controlled
+	/// Output Register</i>.
+	unsigned IOControl : 1;
+	/// Suppress update of <i>Status Register</i> making this
+	/// a stealth <i>Node Stop</i>.
+	unsigned Quiet : 1;
+} iscNodeStopFlds;
+//                                                                            *
+//*****************************************************************************
+															/** \endcond **/
+
+//*****************************************************************************
+// NAME                                                                       *
+//      cpmNodeStopFlds structure
+//
+// DESCRIPTION
+/**
+	\brief ClearPath-SC stop type definition.
+
+	This bit encoded register is used to specify the actions a motor will take
+	when a default or explicit node stop action occurs.
+**/
+struct _cpmNodeStopFlds {
+	/**
+		\brief Move Generator Action to Take
+
+		This is what the motion generator will do for all non-clearing actions.
+	**/
+	mgStopStyles MotionAction : 3;
+	// - - - - - - - - - - - -
+	// Stop type modifiers
+	// - - - - - - - - - - - -
+														/** \cond INTERNAL_DOC **/
+	/**
+		\brief Clear modifier(s)
+
+		This field is set in conjunction with the \a MotionLock or \a Disable
+		fields to clear the latching condition preventing normal operations
+		of these features.
+	**/
+	unsigned Clear : 1;
+														/** \endcond **/
+	/**
+		\brief Motion Lockout latch
+		
+		If this set, subsequent motion requests are rejected until this
+		condition is cleared with the \a Clear modifier.
+	**/
+	unsigned MotionLock : 1;
+														/** \cond INTERNAL_DOC **/
+	unsigned : 1;
+														/** \endcond **/
+	/**
+		\brief Suppress Node Stop Status
+		
+		The update of the <i>Status Register</i> is suppressed making this
+		a stealth <i>Node Stop</i>.
+	**/
+	unsigned Quiet : 1;
+	/**
+		\brief Force disable after Motion Action is complete
+		
+		The node will disable the servo after the motion action completes. This
+		can be used with the AutoBrake feature to engage the brake.
+
+		\see sFnd::IBrakeControl
+	**/
+	unsigned Disable : 1;
+};
+/// ClearPath-SC Node Stop Request Field Definitions
+typedef struct _cpmNodeStopFlds cpmNodeStopFlds;
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//      nodeStopCodes enumeration
+//
+// DESCRIPTION
+/**
+	\brief Commonly used <i>Node Stops</i> as a set of constants.
+
+    This enumeration provides a convenient mechanism for issuing common
+    <i>Node Stops</i>. The sFnd::IMotion::NodeStop function will
+    accept these constants instead of creating and initializing a
+	#_mgNodeStopReg object.
+
+    \code
+    // Stop the motion at node 'myNode' with ramp.
+    myNode.Motion.NodeStop(STOP_TYPE_RAMP);
+    \endcode
+**/
+enum _nodeStopCodes {
+    /*!
+        Stop the executing motion and flush any pending motion
+        commands immediately.
+    **/
+    STOP_TYPE_ABRUPT        =0x00,		// Kill Motion Abruptly
+    /*!
+        Flush any pending motion commands and ramp the node's speed to
+        zero using the <i>E-Stop Deceleration Rate.</i>
+    **/
+    STOP_TYPE_RAMP          =0x01,		// Kill Motion with decel limit
+												/** \cond ISC_DOC **/
+    /*!
+        Ignore any node stop requests.
+        \note This mode does not affect directed node stops via commands.
+    **/					
+    STOP_TYPE_IGNORE        =0x03,		// Node stop ignored
+												/** \endcond **/
+	/*!
+		Kill Motion with Deceleration at the active decel rate and flush 
+		any pending motion commands immediately.
+		
+	**/
+	STOP_TYPE_RAMP_AT_DECEL = 0x04,		// Kill Motion with active decel limit
+    /*!
+        Stop the executing motion and flush any pending motion commands
+        immediately.
+
+        Future motion is blocked until a directed [NodeStopClear](@ref sFnd::IMotion::NodeStopClear)
+		is sent.
+    **/
+    STOP_TYPE_ESTOP_ABRUPT  =0x10,		// E-Stop Abruptly
+    /*!
+        Flush any pending motion commands and ramp the node's speed to
+        zero using the <i>E-Stop Deceleration Rate.</i>
+
+        Future motion is blocked until a directed [NodeStopClear](@ref sFnd::IMotion::NodeStopClear)
+		is sent.
+    **/
+    STOP_TYPE_ESTOP_RAMP    =0x11,		// E-Stop Ramping to stop
+	/*!
+		Flush any pending motion commands and ramp the node's speed to
+		zero using the <i>active decel rate.</i>
+
+		Future motion is blocked until a directed [NodeStopClear](@ref sFnd::IMotion::NodeStopClear)
+		is sent.
+	**/
+	STOP_TYPE_ESTOP_RAMP_AT_DECEL = 0x14,		// E-Stop Abruptly
+	/*!
+		Stop the executing motion and flush any pending motion commands
+        immediately.
+
+		Once the node has stopped, the node will be disabled.
+	**/
+	STOP_TYPE_DISABLE_ABRUPT = 0x80,		// E-Stop Ramping to stop
+	/*!
+		Stop the executing motion and flush any pending motion commands
+		immediately.
+
+		Once the node has stopped, the node will be disabled.
+	**/
+	STOP_TYPE_DISABLE_RAMP = 0x81,		// E-Stop Ramping to stop
+	/*!
+		Stop the executing motion and flush any pending motion commands
+		immediately.
+
+		Once the node has stopped, the node will be disabled.
+	**/
+	STOP_TYPE_DISABLE_RAMP_AT_DECEL = 0x84,		// E-Stop Ramping to stop
+     /*!
+        This stop type will prevent future motion and set the <i>Output
+        Register</i> enable state to disabled.
+
+        This node stop can be canceled by a directed [NodeStopClear](@ref sFnd::IMotion::NodeStopClear)
+		command.
+    **/
+    STOP_TYPE_ESTOP_DISABLE_RAMP =0x91, // E-Stop/ramp to 0/node disables
+	// - - - - - - - - - - - - - - - - -
+    // Node Stop Modifier Clear Masks
+	// - - - - - - - - - - - - - - - - -				/** \cond ISC_DOC **/ 
+	/*!
+        This stop type clears the E-Stop condition, which blocks the motion
+        commands from running.
+    **/
+    STOP_TYPE_CLR_ESTOP     =0x18,		// Node stop clear (E-Stop)
+														
+    /*!
+        This stop type clears the Controlled Output condition.
+    **/
+    STOP_TYPE_CLR_CTRLD     =0x28,		// Restore output register state
+														
+    /*!
+        This stop type clears the Disabled Stop condition.
+    **/
+    STOP_TYPE_CLR_DISABLE   =0x88,		// Restore enable state
+    /*!
+        This stop type clears all latched condition such as the
+        <i>E-Stop</i> and the <i>Controlled Output</i> conditions.
+    **/
+    STOP_TYPE_CLR_ALL       =0xf8		// Clear all modifiers
+														/** \endcond **/
+};
+/// \copybrief _nodeStopCodes
+typedef enum _nodeStopCodes nodeStopCodes;
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//      mgNodeStopReg union
+//
+// DESCRIPTION
+/**
+    \brief Universal Node Stop Action Register Definition
+
+    This container type is used to describe the actions taken when a node
+	stop is issued. The node stop system can affect multiple features within
+	the node.
+	
+	The following items are affected by issuing a node stop.
+	- Motion
+	- Output or Drive Enable States
+	- Status
+
+	The motion portion of the node stop specified by the \a Style field
+	specifies the action to be taken by the move generator. These include:
+	- Immediate cancellation of the motion and any queued motion
+	- Ramp the current velocity to zero at a pre-specified deceleration rate
+	and cancel queued motion 
+	- Not to perform any action at all
+
+	The \a EStop field controls what happens with subsequent motion requests. If
+	non-zero, all motion requests will be rejected. This field is also referred
+	to as the \a MotionLock field and the terms are interchangeable.
+
+	For nodes that have a <i>General Purpose Output</i> feature, the 
+	\a Controlled field defines the action taken by the outputs. For
+	ClearPath-SC this does nothing.
+
+	The \a Disable field controls the node's servo state at the end of
+	motion. If non-zero, the motor will disable and enter the dynamic brake 
+	mode.
+
+	The \a Quiet field controls the posting of the Node Stop event to the 
+	status register. 
+
+	The \a EStop, \a Controlled and \a Disable states latch upon execution 
+	block their respective features from operating in the normal fashion. 
+	\a EStop in particular is a safety feature to prevent inadvertent motion
+	to occur in your application until the originating reason has been cleared.
+
+	To restore operations each of these features can be cleared by setting
+	the \a Clear field to non-zero and setting the respective other field to
+	non-zero and issuing a node stop. The STOP_TYPE_CLR_ALL enumeration
+	provides a convenient way to clear all blocking actions.
+
+	The commonly used node stops are available as enumerated constants 
+	defined in the #nodeStopCodes enumeration.
+**/
+union _mgNodeStopReg {
+
+																/** \cond ISC_DOC **/
+	/**
+		\brief Universal Node Stop Register Field Definitions.
+
+		\copydetails _mgNodeStopReg
+
+		\note Not all models support all options.
+	**/
+	struct _nodeStopFlds {
+		/**
+			\brief Move Generator Action Taken.
+
+			This is what the motion generator will do for all non-Clearing 
+			actions.
+		**/
+		mgStopStyles Style : 3;
+		// - - - - - - - - - - - -
+		// Stop type modifiers
+		// - - - - - - - - - - - -
+		/**
+			\brief Clear latched modifier(s).
+
+			This is used to restore operations after \a EStop, 
+			\a Controlled, or \a Disable node stop has been issued. Set this
+			field with along with the modifier you wish to clear. The \a
+			Style field is ignored when this is set.
+		**/
+		unsigned Clear : 1;
+		/**
+			\brief Lockout subsequent motion.
+			
+			Prevent subsequent motion after node stop issued until the latch
+			is cleared. This is sometimes called the E-Stop or MotionLock
+			state. Clear this condition by issuing a node stop with this field
+			set and the \a Clear field set.
+		**/
+		unsigned EStop : 1;
+		/**
+			\brief Force the <i>Output Register</i> to the <i>Controlled
+			Output Register</i> state.
+
+			Prevent subsequent output register changes until cleared. Clear 
+			this condition by issuing a node stop with this field
+			set and the \a Clear field set.
+
+			\note This is Meridian-ISC only feature
+		**/
+		unsigned Controlled : 1;
+		/**
+			\brief Suppress update of <i>Status Register</i>.
+			
+			This makes this node stop a stealth <i>Node Stop</i>.
+		**/
+		unsigned Quiet : 1;
+		/**
+			\brief Force drive to disable after the <i>Motion Action</i> completes.
+
+			Clear this condition by issuing a node stop with this field
+			set and the \a Clear field set.
+		**/
+		unsigned Disable : 1;
+	};													/** \endcond **/ 
+	/** 
+		\brief Bit-wide access to the Node Stop information.
+	**/
+	nodeStopCodes bits;
+														/** \cond INTERNAL_DOC **/
+	/**
+		\brief Universal field view of the stop types.
+	**/
+	struct _nodeStopFlds fld;
+														/** \endcond **/
+	/**
+		\brief ClearPath-SC field view of the stop types.
+	**/
+	cpmNodeStopFlds cpm;
+														/** \cond ISC_DOC **/
+	/**
+		\brief Meridian ISC field view of the stop types.
+	**/
+	iscNodeStopFlds isc;
+														/** \endcond **/
+	#ifdef __cplusplus
+														/** \cond INTERNAL_DOC **/
+		// Constructors
+		_mgNodeStopReg(int how) {
+			bits = static_cast<nodeStopCodes>(how);
+		};
+		// Convert convenience \e mgStopCodes code to \e mgStopType.
+		_mgNodeStopReg() {
+			bits = static_cast<nodeStopCodes>(MG_STOP_STYLE_ABRUPT);
+		};
+														/** \endcond **/
+		/**
+			Convert the convenience \e mgStopCodes code to \e mgStopType.
+
+			\param[in] how Enumerated value to setup node stop register.
+		**/
+		_mgNodeStopReg(nodeStopCodes how) {
+			bits = static_cast<nodeStopCodes>(how);
+		};
+	#endif
+};
+/// \copydetails _mgNodeStopReg
+typedef union _mgNodeStopReg  mgNodeStopReg;
+														/** \cond INTERNAL_DOC **/
+// Legacy alias
+#define nodeStopTypes mgNodeStopReg
+														/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+
+#ifdef _MSC_VER
+#pragma pack(pop)                   // Restore to byte alignment boundaries
+#endif
+
+#endif   // __PUBMOTION_H__
+//=============================================================================
+//  END OF FILE pubMotion.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubNetAPI.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubNetAPI.h
new file mode 100644
index 000000000..70e490d2b
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubNetAPI.h
@@ -0,0 +1,589 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/pubNetAPI.h $
+// $Revision: 30 $ $Date: 12/09/16 4:05p $
+// $Workfile: pubNetAPI.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\brief Network Constants and types for interacting with nodes.
+
+
+
+**/
+// CREATION DATE:
+//		2015-12-02 16:32:18
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __PUBNETAPI_H__
+#define __PUBNETAPI_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	pubNetAPI.h headers
+//
+	#include "tekTypes.h"
+
+#ifndef __TI_COMPILER_VERSION__
+	#include "pubCoreRegs.h"
+	#include "mnErrors.h"
+	#include "pubIscRegs.h"
+#endif
+	#include <string.h>
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubNetAPI.h constants
+//
+//
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// NETWORK DEFINITIONS
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+	The internally assigned unique address type for a node.
+
+	The system initialization assigns this address for it's internal purposes. 
+	It should only be used for error messages and the arguments of legacy
+	C-based API calls.
+**/
+typedef Uint16 multiaddr;		// Combined net and node address
+/**
+	The internally assigned index type of a node on a serial port.
+
+	Node are numbered from zero, starting from the transmit port of the host.
+**/
+typedef Uint16 nodeaddr;		// Node's address on its net
+/**
+	The serial port index type. 
+	
+	This corresponds to the index supplied during system initialization.
+**/
+typedef Uint16 netaddr;			// Net number (a.k.a. cNum)
+/// The numeric value for an unassigned multiaddr.  
+#define MN_UNSET_ADDR multiaddr(0xffffu)		// The illegal address value 
+													/** \cond INTERNAL_DOC **/
+/// Maximum # of serial ports we can specify.
+#define NET_CONTROLLER_MAX 3 
+/// Maximum # of nodes on a port
+#define MN_API_MAX_NODES		16U
+
+/// Maximum size of the user non-volatile data area
+#define MN_USER_NV_SIZE		13U
+													/** \endcond **/
+
+
+/**
+	\brief This enumeration describes the port open state. 
+	
+	Operations to nodes may be performed when the port is in the OPENED_ONLINE
+	state.
+**/
+typedef enum _openStates {
+	/**
+	We do not know the current state
+	**/
+	UNKNOWN,
+	/**
+	A previously opened port was shutdown.
+	**/
+	CLOSED,
+	/**
+	The port is opened in FLASH mode.
+	**/
+	FLASHING,
+	/**
+	The port requested does not exist or is currently owned by another
+	application.
+	**/
+	PORT_UNAVAILABLE,
+	/**
+	The port is opened and initial detection of nodes resulted
+	in no detected nodes.  Communications with nodes will result
+	in failures.
+	**/
+	OPENED_SEARCHING,
+	/**
+	The port is opened and we have detected nodes. Interactions with
+	nodes can occur normally.
+	**/
+	OPENED_ONLINE
+} openStates;
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+//							NODE/NET INFORMATION V2
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+
+#ifndef __TI_COMPILER_VERSION__
+//*****************************************************************************
+//																			  *
+/**
+	\brief The type of nodes attached to this port. 
+
+	This list defines the types of adapters attached directly to the serial
+	port. For ClearPath-SC systems this is usually the CPM_COMHUB.
+**/
+typedef enum _portTypes {
+	/**
+		Unspecified nodes
+	**/
+	UNKNOWN_NODES,				
+	/**
+		Meridian Family CON-MOD connection
+	**/
+	MERIDIAN_CONMOD,			
+	/**
+		ClearPath-SC Communications Hub connection
+	**/
+	CPM_COMHUB,	
+	/**
+		Node connected via generic serial connection
+	**/
+	GENERIC_SERIAL
+} portTypes;
+//																			  *
+//*****************************************************************************
+
+													/** \cond INTERNAL_DOC **/
+//*****************************************************************************
+//																			  *
+/**
+	\brief Container used to specify the communications port and operational 
+	speed.
+**/
+typedef struct _controllerSpec {
+	netRates PortRate;				///< Network Operational rate
+#if defined(_WIN32)||defined(_WIN64)
+	Uint16 PortNumber;              ///< Port number
+#else
+	char PortName[MAX_PATH];			///< Port device path
+#endif
+#ifdef __cplusplus
+	_controllerSpec() {
+		PortRate = MN_BAUD_108X;
+	}
+	#if defined(_WIN32)||defined(_WIN64)
+		/**
+			\brief Convenience Constructor
+			\param number COM port number for this channel.
+			\param rate Desired operational rate for this channel.
+		**/ 
+        _controllerSpec(Uint16 number, netRates rate = MN_BAUD_108X) {
+			PortNumber = number;
+			PortRate = rate;
+        }
+	#else
+		/**
+			\brief Convenience Constructor
+			\param name Ptr to serial port device.
+			\param rate Desired operational rate for this channel.
+		**/ 
+		_controllerSpec(const char * name, netRates rate = MN_BAUD_108X);
+	#endif
+#endif
+} controllerSpec;
+//																			  *
+//*****************************************************************************
+													/** \endcond **/
+
+//*****************************************************************************
+//																			  *
+														/** \cond INTERNAL_DOC **/
+/**
+	\brief Serial Port specification type
+	
+	This container is used to specify the communications port, operational 
+	speed and network type for a Meridian or ClearPath-SC network.
+**/
+struct MN_EXPORT _portSpec {
+#if defined(_WIN32)||defined(_WIN64)
+	netRates PortRate;				///< Network Operational rate
+	Uint16 PortNumber;              ///< Port number
+	portTypes PortType;				///< Type of port and nodes
+#else
+	netRates PortRate;				///< Network Operational rate
+	char PortName[MAX_PATH];		///< Port device path
+	portTypes PortType;				///< Type of port and nodes
+#endif // defined(_WIN32)||defined(_WIN64)
+#ifdef __cplusplus
+	#if defined(_WIN32)||defined(_WIN64)
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// WINDOWS CONSTRUCTION
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+													/** cond INTERNAL_DOC **/
+		/// Generic construction
+		_portSpec() {
+			PortRate = MN_BAUD_12X;
+			PortNumber = 0;
+			PortType = UNKNOWN_NODES;
+		}
+		/// Convert older buffer to new one
+		_portSpec operator=(const _controllerSpec &oldForm) {
+			PortRate = oldForm.PortRate;
+			PortNumber = oldForm.PortNumber;
+			PortType = MERIDIAN_CONMOD;
+			return(*this);
+		}
+													/** endcond **/
+		/**
+			\brief Convenience Constructor
+			\param[in] number COM port number for this channel.
+			\param[in] rate Desired operational rate for this channel.
+			\param[in] thePortType The type of adapter attached to this serial
+			port.
+		**/ 
+        _portSpec(Uint16 number, 
+				  portTypes thePortType,
+				  netRates rate = MN_BAUD_108X) {
+			PortNumber = number;
+			PortType = thePortType;
+        }
+	#else  
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// NON-WINDOWS CONSTRUCTION (QNX/Linux)
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+													/** cond INTERNAL_DOC **/
+		_portSpec() {
+			PortRate = MN_BAUD_12X;
+			PortName[0] = 0;
+			PortType = UNKNOWN_NODES;
+		}
+		/**
+			\brief Convenience Constructor
+			\param name Ptr to serial port device.
+			\param rate Desired operational rate for this channel.
+		**/ 
+        _portSpec(const char *name,  
+						portTypes theNodeTypes,
+						netRates rate = MN_BAUD_108X){
+			PortRate = rate;
+			PortType = theNodeTypes;
+			strncpy(PortName, name, MAX_PATH);
+		}
+		_portSpec operator=(const _controllerSpec &oldForm) {
+			PortRate = oldForm.PortRate;
+			PortType = MERIDIAN_CONMOD;
+			strncpy(PortName, oldForm.PortName, MAX_PATH);
+			return(*this);
+		}
+													/** endcond **/
+	#endif
+#endif	//__cplusplus
+};
+
+/// \copybrief _portSpec
+typedef struct _portSpec portSpec;
+#endif // __TI_COMPILER_VERSION__
+
+													/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+
+
+//*****************************************************************************
+// NAME	
+//	BrakeControl enum
+/**
+	\brief State for the brake control feature. 
+**/
+enum _BrakeControls
+{
+	/**
+		Brake activates automatically depending on the state of the node.  BrakeNum 0 will correspond to Brake 1 on the SC hub.  BrakeNum 1 will correspond to Brake 2 on the SC hub
+	**/
+	BRAKE_AUTOCONTROL,
+	/**
+		Engage the brake.
+	**/
+	BRAKE_PREVENT_MOTION,
+	/**
+		Disengage the brake
+	**/
+	BRAKE_ALLOW_MOTION,
+	/**
+		Use the brake output as a GPO that is asserted.
+	**/
+	GPO_ON,
+	/**
+		Use the brake output as a GPO that is deasserted.
+	**/
+	GPO_OFF
+};
+/// \copybrief _BrakeControls
+typedef enum _BrakeControls BrakeControls;
+//																			   *
+//******************************************************************************
+
+
+
+
+
+#ifndef __TI_COMPILER_VERSION__
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Standard Error Object
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/** 
+	Namespace for sFoundation class library.
+**/
+namespace sFnd {
+/**
+	\brief Error code and reason structure.
+	
+	Error code and reason structure.  When the sFoundation class library encounters an error, this item will be
+	thrown.  This item can be used to identify the error, the address reporting the error, and get a brief description of the error.
+
+
+	\CODE_SAMPLE_HDR
+	try	{
+		// Do some library function
+	}
+	// If there is a error print out details
+	catch (mnErr theErr) {
+		cout << theErr.TheAddr;
+		cout << theErr.ErrorCode;
+		cout << theErr.ErrMsg;
+	}
+	\endcode
+**/
+	typedef struct _mnErr {
+		/**
+			Address reporting the error.
+		**/
+		multiaddr TheAddr;
+		/**
+			The system Error Code number.
+		**/
+		cnErrCode ErrorCode;
+		/**
+			A printable error string that includes the ErrorCode.
+
+			<table class="tableizer-table">
+			<tr class="tableizer-firstrow"><th>cnErrCode</th><th>Value</th><th>Description</th></tr>
+			<tr><td>MN_ERR_TIMEOUT,</td><td> 0x80040002</td><td>Failed due to time-out while waiting for attention.</td></tr>
+			<tr><td>MN_ERR_DEV_ADDR,</td><td> 0x80040004</td><td> Device addressing problems.
+			- Check that you are not trying to send commands to a port that does not exist.
+			- Only address ports [0-2].</td></tr>
+			<tr><td>MN_ERR_TOO_MANY,</td><td> 0x80040005</td><td>There are too many nodes on the net(16 Max).</td></tr>
+			<tr><td>MN_ERR_RESP_FMT,</td><td> 0x80040006</td><td>Response is garbled. This indicates serious com issues.
+			- Ensure network power supply is stable.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_OFFLINE,</td><td> 0x80040008</td><td>The node went offline.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_PARAM_RANGE,</td><td> 0x80040009</td><td>Parameter is out of range.</td></tr>
+			<tr><td>MN_ERR_CLOSED,</td><td> 0x8004000c</td><td>Attempting to use a closed port/node.
+			- Ensure ports are opened before accessing.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_PKT_ERR,</td><td> 0x80040011</td><td>Packet length does not equal buffer length.
+			- Check for issues with the serial port.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_CMD_OFFLINE,</td><td> 0x8004001b</td><td>Command attempt while net offline.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_ATTN_OVERRUN,</td><td> 0x8004001e</td><td>Attention over-run error.  This indicates one or more attentions may have been lost due to incorrect attention aetup handling.
+			- Ensure attentions are enabled at the [IAttnPort](@ref sFnd::IAttnPort) level.</td></tr>
+			<tr><td>MN_ERR_BADARG,</td><td> 0x80040027</td><td>API function passed bad argument</td></tr>
+			<tr><td>MN_ERR_SEND_FAILED,</td><td> 0x8004002a</td><td>The host serial port rejected a command.
+			- Check that the host serial port is operating properly.</td></tr>
+			<tr><td>MN_ERR_RESP_TIMEOUT,</td><td> 0x8004002e</td><td>Response from Node not found in time.
+			- Ensure network power supply is stable.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_CANCELED,</td><td> 0x80040030</td><td>Command canceled during Node restart.</td></tr>
+			<tr><td>MN_ERR_ADDR_RANGE,</td><td> 0x80040034</td><td>Response from out of range address. A node likely went offline.
+			- Ensure network power supply is stable.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_RESET_FAILED,</td><td> 0x8004003b</td><td>Reset command failed, node isn't responding.
+			- Ensure network power supply is stable.
+			- Check conections, and wiring for intermittent connectivity issues.</td></tr>
+			<tr><td>MN_ERR_FILE_WRITE,</td><td> 0x80040040</td><td>Configuration file failed to write to file location.
+			- Check for correct directory.
+			- Check for appropriate write-access for specified directory.
+			- Check for adequate disk space.</td></tr>
+			<tr><td>MN_ERR_FILE_OPEN,</td><td> 0x80040041</td><td>Configuration file failed to open.
+			- Check for correct directory.
+			- Check for appropriate read/write-access for specified directory.</td></tr>
+			<tr><td>MN_ERR_FILE_WRONG,</td><td> 0x80040042</td><td>Configuration file is for wrong node.
+			- Ensure the configuration file specified is for the correct Node type.</td></tr>
+			<tr><td>MN_ERR_FILE_BAD,</td><td> 0x80040043</td><td>Configuration file corrupt   </td></tr>
+			<tr><td>MN_ERR_FILE_ENABLED,</td><td> 0x80040044</td><td>Configuration file load requires node to be disabled.
+			- Ensure node is disabled before attempting to load configuration file.</td></tr>
+			<tr><td>MN_ERR_CMD_IN_ATTN,</td><td> 0x80040045</td><td>Node command attempted from within an Attention Callback.
+			- Ensure your registered attention callback functions do not attempt to send commands to any node.</td></tr>
+			<tr><td>MN_ERR_APP_NET_ONLY,</td><td> 0x80040046</td><td>Feature only available on App Net</td></tr>
+			<tr><td>MN_ERR_24V_OFF,</td><td> 0x80000047</td><td>Canceled due to lack of 24V supply.
+			- Ensure communication power supply is stable, and turned on.</td></tr>
+			<tr><td>MN_ERR_CMD_ARGS,</td><td> 0x80040102</td><td> Illegal or missing command args</td></tr>
+			<tr><td>MN_ERR_CMD_WR_FAIL,</td><td> 0x80040103</td><td> Attempt to write to a read-only parameter.</td></tr>
+			<tr><td>MN_ERR_CMD_EEHW,</td><td> 0x80040104</td><td>Non-Volatile memory failure.
+			- Check conections, and wiring for intermittent connectivity issues.
+			- If problem persists, replace motor.</td></tr>
+			<tr><td>MN_ERR_CMD_ACCESS_LVL,</td><td> 0x80040105</td><td>Access level violation.
+			- Make sure that the diagnostic USB channel is in moniter mode through ClearView.</td></tr>
+			<tr><td>MN_ERR_CMD_MV_FULL,</td><td> 0x80040106</td><td> Move Buffers full.
+			- Allow moves in buffer to complete before adding additional moves.</td></tr>
+			<tr><td>MN_ERR_CMD_MV_SPEC,</td><td>0x80040107</td><td>Move specification error.
+			- Check that the commanded velocity is below the velocity limit for the node.
+			- Ensure that the move distance is within the soft limits of the motor, and does not exxceed the numberspace (~8,000,000).</td></tr>
+			<tr><td>MN_ERR_CMD_MV_ESTOPPED,</td><td>0x80040108</td><td>Motion attempt in E-Stopped state.
+			- Clear E-Stop state before commanding motion.</td></tr>
+			<tr><td>MN_ERR_CMD_MV_RANGE,</td><td>0x80040109</td><td>Motion attempt is out of range.
+			- Ensure that the move distance is within the soft limits of the motor, and does not exxceed the numberspace (~8,000,000).</td></tr>
+			<tr><td>MN_ERR_CMD_MV_SHUTDOWN,</td><td>0x8004010a</td><td> Motion attempt when drive is in shutdown.
+			- Appropriatly clear shutdown before commanding motion.</td></tr>
+			<tr><td>MN_ERR_CMD_MV_BLOCKED,</td><td>0x8004010c</td><td> Motion blocked non-disabling shutdown(ie: limit switches) present.
+			- Remove cause of non-disabling shutdown.
+			- Ensure commanded motion is in valid direction(ie: not attempting to move into an already asserted limit).</td></tr>
+			<tr><td>MN_ERR_NODE_IN_MOTION,</td><td>0x80040110</td><td>Drive is in motion. Some node commands cannot be called during motion(ie: Initiating homing). </td></tr>
+			<tr><td>MN_ERR_OFFLINE_XX,</td><td>0x800403a0-0x800403af</td><td> Node X detected offline Detected offline nodes are reported with this group. These are usually caused by a node restarting via communication power or firmware error.</td></tr>
+			<tr><td>MN_ERR_INIT_FAILED_PORTS_X,</td><td>0x80040600-0x80040607</td><td> Port X opened OK but no nodes were found attached to the link.</td></tr>
+			<tr><td>MN_ERR_PORT_FAILED_PORTS_X</td><td>0x80040700-0x80040707</td><td> Port  X failed to open.
+			- Make sure you specify a working port.
+			- Check that the USB/Serial cable is properly inserted.
+			- Ensure no other applications are activly using the port(ie: ClearView).</td></tr>
+			<tr><td>MN_ERR_BAUD_FAILED_PORTS_X</td><td> 0x80040800 - 0x80040807</td><td> Port X opened OK but doesn't support the requested baud rate.
+			- Check that the serial port supports your requested baud rate.
+			- If using the SC-Hub, use a baud rate of MN_BAUD_12X, or MN_BAUD_24X.</td></tr>
+			</table>
+		**/
+		char ErrorMsg[512];
+	} mnErr;
+}
+//																			  *
+//*****************************************************************************
+#endif
+
+
+
+#ifndef __TI_COMPILER_VERSION__
+//*****************************************************************************
+// NAME	
+//	ShutdownInfo struct
+/**
+	\brief Information to setup group shutdowns at a node.
+
+	This is the main struct for the <i>Auto-shutdown </i> feature.  The struct consists of three parts:
+	- Whether or not the node should respond to a Group Shutdown.
+	- The Node Stop type for this node.
+	- The [Status Register](@ref mnStatusReg) mask for this Node which will trigger a Group shutdown.
+
+	\CODE_SAMPLE_HDR
+
+	// The following lines of code show an example of how to create a Shutdown info object.
+
+	// First we create the status mask object consisting of which status events on the node will trigger a group shutdown.
+	// In this case we are using "AlertPresent", "Disabled", and "Input A"
+
+	mnStatusReg myShutdownStatusMask;						//Create Status mask
+	myShutdownStatusMask.cpm.AlertPresent = 1;				//Set desired fields
+	myShutdownStatusMask.cpm.Disabled = 1;
+	myShutdownStatusMask.cpm.InA = 1;
+
+	// Next we create the ShutdownInfo object we will use to configure the Node with
+	ShutdownInfo myShutdownInfo;							//Create ShutdownInfo Object
+	myShutdownInfo.enabled = true;							// This sets the node to respond to Group Shutdowns
+	myShutdownInfo.theStopType = STOP_TYPE_ABRUPT;			//Use an Abrupt Nodestop type for this node in response to a group shutdown
+	myShutdownInfo.statusMask = myShutdownStatusMask;		// Configure the node to issue a group shutdown automatically based on our status mask
+
+	//Finally we use configure the Port's first Node (Node 0) with our shutdown object
+	myport.GrpShutdown.ShutdownWhen(0,myShutdownInfo);
+
+	\endcode
+
+	\see \ref CPMnodeStopPage
+**/
+struct _ShutdownInfo {
+	/**
+		Enables checking at this node.  If this is set to false, the node will not shutdown during a group shutdown.
+	**/
+	nodebool enabled;
+	/**
+		The kind of stop to assert when this feature fires off.
+		\see \ref CPMnodeStopPage for a complete list of Node Stop types.
+	**/
+	mgNodeStopReg theStopType;
+	/**
+		Items to trigger a Group Shutdown stop when the Node's status register rises on the unmasked 
+		bits of the \a statusMask. Set the bits to non-zero to enable the
+		detection of this event.
+	**/
+	mnStatusReg statusMask; 
+#ifdef __cplusplus
+													/** \cond INTERNAL_DOC **/
+	/// Construct our ClearPath COM Hub brake implementation
+	_ShutdownInfo() {
+		enabled = false;
+	}
+													/** \endcond **/
+#endif
+};
+/// \copybrief _ShutdownInfo
+typedef struct _ShutdownInfo ShutdownInfo;
+//																			   *
+//******************************************************************************
+#endif // __TI_COMPILER_VERSION__
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Attention Request/Status Register
+// 
+// NOTE: arrays of this items will involve 32-bit spacings
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+													/** \cond SC_EXPERT **/
+/**
+	\brief <i>Attention Request</i> Register and Source Container.
+
+	This register is the representation of an <i>Attention Packet
+	</i>. 
+
+	An \e AttentionReg.lBits equal to zero occurs when the function
+	did not successfully get an attention.
+
+	\see sFnd::IAttnPort::WaitForAttn
+**/
+typedef struct _mnAttnReqReg {
+	multiaddr MultiAddr;				///< Node signaling change
+	attnReg AttentionReg;				///< Status signaled
+} mnAttnReqReg;
+													/** \endcond  **/
+
+#ifndef __TI_COMPILER_VERSION__
+													/** \cond INTERNAL_DOC **/
+//*****************************************************************************
+// NAME																	      *
+// 	pubNetAPI.h function prototypes
+//
+/**
+	\brief C Based initialization function
+	
+	This is the expanded initializing function for combination Meridian 
+	and ClearPath-SC systems.
+**/
+MN_EXPORT cnErrCode MN_DECL mnInitializeSystem(
+			nodebool resetNodes,			// Set to reset nodes at startup
+			nodeulong netCount,				// Number of nets to initialize (1..2)
+			const portSpec controllers[]);	// Ptr to controller list
+
+//																			  *
+//*****************************************************************************
+													/** \endcond **/
+#endif
+
+#endif // __PUBNETAPI_H__
+//============================================================================= 
+//	END OF FILE pubNetAPI.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubPwrReg.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubPwrReg.h
new file mode 100644
index 000000000..b1dba461b
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubPwrReg.h
@@ -0,0 +1,201 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/inc/pubPwrReg.h $
+// $Revision: 3 $ $Date: 12/06/16 19:09 $
+// $Workfile: pubPwrReg.h $
+//
+// DESCRIPTION:
+/**
+ * 	\file
+ * 	sFoundation definition of the power status register.
+**/
+// CREATION DATE:
+//		2016-11-28
+//
+// COPYRIGHT NOTICE:-
+//		(C)Copyright 2016-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//
+//*****************************************************************************
+#ifndef __PUBPWRREG_H__
+#define __PUBPWRREG_H__
+
+//*****************************************************************************
+// NAME																          *
+// 	pubCPM_API.h headers
+//
+	#include "tekTypes.h"
+//																			  *
+//*****************************************************************************
+
+// Set byte packing
+#ifdef _MSC_VER
+#pragma pack(push, 1)
+#endif
+
+//*****************************************************************************
+// NAME                                                                       *
+//  mnPowerFlds structure
+//
+// DESCRIPTION
+/** \cond ExpertDoc **/
+/**
+\brief Fields of the Power Status Register.
+
+This status defines a container used to access a node's power status.
+**/
+typedef struct PACK_BYTES _mnPowerFlds {
+
+	typedef enum _acConnectionTypes {
+		AC_PHASES_NONE = 0,
+		AC_PHASES_X = 1,
+		AC_PHASES_Y = 2,
+		AC_PHASES_Z = 4,
+		AC_PHASES_XY = AC_PHASES_X | AC_PHASES_Y,
+		AC_PHASES_XZ = AC_PHASES_X | AC_PHASES_Z,
+		AC_PHASES_YZ = AC_PHASES_Y | AC_PHASES_Z,
+		AC_PHASES_XYZ = AC_PHASES_X | AC_PHASES_Y | AC_PHASES_Z,
+	} acConnectionTypes;
+	/**
+		Active Phases
+
+		This field shows which AC phases have a signal present
+	**/
+	acConnectionTypes AcPhaseActive			: 3;	// 0-2
+
+	/**
+		AC Phase Direction
+
+		This field shows that AC is applied in a manner to imply the reverse direction.
+	**/
+	unsigned AcPhaseDir						: 1;	// 3
+
+	/**
+		Last Active Phases
+
+		This field shows which AC phases have a signal present
+	**/
+	acConnectionTypes AcPhaseActiveLast		: 3;	// 4-6
+
+	/**
+		Last AC Phase Direction
+
+		This field shows that AC is applied in a manner to imply the reverse direction.
+	**/
+	unsigned AcPhaseDirLast					: 1;	// 7
+	
+	/**
+		Active Phases Accumulating
+
+		This field shows which AC phases have had a signal present
+	**/
+	
+	unsigned AcPhaseActiveAccum				: 3;	// 8-10
+
+	/**
+		AC Phase Direction Accumulating
+
+		This field shows that AC had been applied in a manner to imply the reverse direction.
+	**/
+	unsigned AcPhaseDirAccum				: 1;	// 11
+
+	/**
+		Bus Power Loss is detected.
+
+		This field will be set when bus voltage source has been disconnected.
+		Motion will be canceled and new motion will be blocked when this
+		field is set.
+
+		\note If 24V Backup power is not present, communications will be
+		interrupted after a short duration. The duration depends on the
+		charge remaining in the motor's power supply.
+	**/
+	unsigned InBusLoss						: 1;	// 12
+
+	/**
+		AC wiring error is detected.
+
+		This error is detected when the configuration is set for 3phase
+		and an AC source other than 3phase is encountered, or when the
+		configuration is set for single phase and an AC source other
+		than single phase is encountered.
+
+	**/
+	unsigned InWiringError					: 1;	// 13
+
+	/**
+		24V Power Present.
+
+		This field will be set when 24 volt backup power is detected.
+	**/
+	unsigned LogicPwrSupply					: 1;	// 14
+
+	/**
+	 	 Under Operating Voltage
+
+	 	 This field will be set when the bus power is below the user-
+	 	 defined minimum operating voltage.
+	**/
+	unsigned InUnderOperV					: 1;	// 15
+
+} mnPowerFlds;
+
+/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME                                                                       *
+//  mnPowerReg union
+//
+// DESCRIPTION
+/** \cond ExpertDoc **/
+/**
+\brief Universal Power Status register.
+
+This union defines a container used to access a node's power status.
+**/
+typedef union MN_EXPORT PACK_BYTES _mnPowerReg {
+	/// Bit-wise generic access
+	uint32_t	bits;
+	/// Field access to the power information.
+	mnPowerFlds	fld;
+
+	/** \cond INTERNAL_DOC **/
+	// Construction
+	_mnPowerReg() {
+		bits = 0;
+	}
+	/**
+	\brief Update a string with the set fields in the Power Status Register.
+
+	\param[in,out] buffer  Point to string buffer to update.
+	\param[in] size  The size of the buffer in characters including the null
+	character.
+	\return the parameter \a buffer.
+
+	\CODE_SAMPLE_HDR
+	char myBuffer[500];
+	cout << myNode.Status.Power.Value.StateStr(myBuffer, sizeof(myBuffer));
+	\endcode
+	**/
+	char * StateStr(char *buffer, size_t size);
+	// Copy constructor
+	_mnPowerReg(const _mnPowerReg &src);
+	/** \endcond **/
+} mnPowerReg;
+/** \endcond **/
+//                                                                            *
+//*****************************************************************************
+// Restore byte packing
+#ifdef _MSC_VER
+#pragma pack(pop)
+#endif
+
+#endif
+//===========================================================================
+//	END OF FILE pubPwrReg.h
+//===========================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubRegFldCommon.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubRegFldCommon.h
new file mode 100644
index 000000000..3784eaec5
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubRegFldCommon.h
@@ -0,0 +1,696 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/Firmware/cp1x/inc_pub/pubRegFldCommon.h $
+// $Revision: 7 $ $Date: 7/08/16 3:00p $
+// $Workfile: pubRegFldCommon.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\brief Definitions of the common parts of various registers.
+
+	
+**/
+// CREATION DATE:
+//		2015-12-24 10:59:53
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2010-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __PUBREGFLDCOMMON_H__
+#define	__PUBREGFLDCOMMON_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	pubRegFldCommon.h headers
+//
+#include "tekTypes.h"
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubRegFldCommon.h function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubRegFldCommon.h constants
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubRegFldCommon.h static variables
+//
+// 
+
+//																			  *
+//*****************************************************************************
+
+//****************************************************************************
+// NAME                                                                      *
+//  commonAlertFlds struct
+//
+// DESCRIPTION
+/**
+    \brief Alert bits common to all nodes.
+
+    This union defines the common areas of the node's Alert Register. All
+    nodes will use these definitions.
+ **/
+typedef struct PACK_BYTES _commonAlertFlds {
+    //                              ------------------------------------------
+    //                              |len|bit #|description                   |
+    //                              ------------------------------------------
+    /**
+        \brief Node power-on self test has failed.
+		
+		Node power-on self test has failed.
+
+		Appears in:
+
+        Remedies:
+        - Replace node.
+    */
+    unsigned FwSelfTest             : 1; /* 0 */ // Firmware self-test failed
+    /**
+        \brief Network buffer overrun.
+
+        Network buffer overrun.
+
+		Appears in:
+
+        Remedies:
+        - Check command pacing.
+    */
+    unsigned FwNetBufferOverrun     : 1; /* 1 */ // Network buffer overrun
+    /**
+        \brief Internal Firmware Error 0.
+
+        Internal Firmware Error 0.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - Update firmware.
+    */
+    unsigned FwError0               : 1; /* 2 */ // Internal Error 0
+    /**
+        \brief Internal Firmware Error 0.
+
+        Internal Firmware Error 0.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - Update firmware.
+    */
+    unsigned FwError1               : 1; /* 3 */ // Internal Error 1
+    /**
+        \brief Internal Firmware Error due to stack issues.
+
+        Internal Firmware Error due to stack issues.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - Update firmware.
+    */
+    unsigned FwStackOverrun         : 1; /* 4 */ // Firmware Stack problem
+    /**
+        \brief The DSP watchdog timer has restarted the node.
+
+        The DSP watchdog timer has restarted the node.
+
+        Appears in:
+
+        Remedies:
+        - Check link power supply for brown-outs.
+        - Update firmware.
+    */
+    unsigned FwWatchdogRestarted    : 1; /* 5 */ // DSP Watchdog restarted node
+    /**
+        \brief Invalid setting detected.
+
+        An invalid setting is detected that prevents the drive from running
+
+        Appears in: AlertReg
+
+        Remedies:
+        - Clear to factory defaults and load a valid configuration file.
+        - Replace node
+    */
+    unsigned FwInvalidConfiguration : 1; /* 6 */ // DSP Watchdog restarted node
+	/** \cond INTERNAL_DOC **/
+    unsigned na7_10                 : 4; // 7-10
+	/** \endcond **/
+    /**
+		\brief Power Supply Problem.
+
+        Onboard power supply out of regulation or missing. This condition is 
+        stored in internal log for factory use.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - Replace node.
+    */
+    unsigned HwPowerProblem         : 1; /* 11 */ // Bad power supply
+    /**
+		\brief DSP clock problem.
+
+        The DSP clock did not initialize properly. Most likely you will
+        not be able to communicate with this node. This condition is stored in internal log
+        for factory use.
+
+        Appears in: AlertReg
+
+        Remedies:
+        - Replace node.
+    */
+    unsigned HwClockProblem         : 1; /* 12 */ // Clock Bad
+    /**
+        \brief The node's non-volatile memory is broken.
+
+        The node's non-volatile memory is broken.
+
+        Appears in: AlertReg
+
+        Remedies:
+        - Replace node.
+    */
+    unsigned HwEEPROMdead           : 1; /* 13 */ // EEPROM hw bad
+    /**
+		\brief Flash content drifting.
+
+        The run-time test of the firmware has determined the flash memory
+        is drifting.
+
+        Appears in: AlertReg
+
+        Remedies:
+        - Replace or reflash node.
+    */
+    unsigned HwFlashCorrupt         : 1; /* 14 */ // Runtime corruption test
+    /**
+		\brief Flash changed due to update.
+
+        This bit is asserted after the flash memory is updated with new firmware
+        or has drifted from the known image. Normally the Teknic supplied
+        flash updater will reset this when it clears the configuration out of
+        the node as the firmware is updated.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - If the firmware has not been recently updated, replace this node.
+        - Reload the node's configuration file using the APS application.
+        - Ensure the Flash Update Acknowledge parameter has been set to the
+        node's checksum.
+    */
+    unsigned HwFlashChanged         : 1; /* 15 */ // POR test, firmware updated
+    /**
+        \brief The power-on self test has determined the RAM is bad.
+
+        The power-on self test has determined the RAM is bad.
+
+        Appears in:
+
+        Remedies:
+        - Replace the node
+    */
+    unsigned HwRAM                  : 1; /* 16 */ // POR test, RAM problem
+    /**
+		\brief ADC failed self-test.
+		
+		The power-on self test has determined the Analog to Digital
+        converter or its related analog hardware is bad.
+
+		Appears in:
+
+		Remedies:
+        - Replace the node
+    */
+    unsigned HwADC                  : 1; /* 17 */ // POR test, ADC problem
+    /**
+		\brief ADC Saturated
+
+        ADC in saturation mode.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - Check for new firmware.
+        - Replace node.
+    */
+    unsigned HwADCsat				: 1; // 18 Unexpected ADC saturation
+	/** \cond INTERNAL_DOC **/
+    unsigned na19_23                : 5; // 19-23
+	/** \endcond **/
+    /**
+		\brief Link/Node power supply low.
+
+        The link and node's power supply is low. This could be due to an
+        overloaded supply or extremely long cables.
+
+		Appears in:
+
+        Remedies:
+        - Check link power supply
+    */
+    unsigned NetVoltageLow          : 1; /* 24 */ // Link voltage brown-out
+    /**
+		\brief Network activity watchdog node stop.
+
+        The node has entered a node stop state due to a lack of communications
+        from the host. If the node's Stop Type is set to
+        STOP_TYPE_IGNORE this feature is defeated.
+
+		Appears in: AlertReg, WarnReg
+
+        Remedies:
+        - Ensure the application requests some real-time parameter
+        or run a command within the watchdog time.
+        - Adjust or disable the network activity watchdog parameter.
+    */
+    unsigned NetWatchdog            : 1; /* 25 */ // Network watchdog shutdown
+													/** \cond INTERNAL_DOC **/
+    unsigned na26_27                : 2; // 26-27
+													/** \endcond **/
+    /**
+		\brief Node E-Stopped.
+
+        The node has entered an E-Stop state and will no longer accept motion
+        commands until this condition is cleared.  This code is not cleared
+        with the IStatus::AlertsClear function to prevent unintended motion.
+
+		Appears in: AlertReg
+
+        Remedies:
+		- Issue a IMotion::
+        - Issue a netNodeStop command with the STOP_TYPE_CLR_ESTOP argument
+        to allow motion to be re-issued.
+    */
+    unsigned EStopped               : 1; /* 28 */ // In E-Stopped State
+    /**
+		\brief Configuration file out of date for firmware.
+
+        The node's internal configuration file is out of date for the loaded
+        firmware.
+
+		Appears in: AlertReg
+
+        Remedies:
+        - Clear to factory defaults and load a valid configuration file.
+    */
+    unsigned ConfigOutOfDate        : 1; /* 29 */ // Non-Volatile mismatch / Firmware
+    /**
+		\brief Internal firmware error.
+
+        Internal firmware error.
+
+		Appears in:
+
+        Remedies:
+        - Update node firmware to newer release.
+    */
+    unsigned RunTimeErr             : 1; /* 30 */ // Generic runtime error
+	/** \cond INTERNAL_DOC **/
+    unsigned na31                   : 1; // 31
+	/** \endcond **/
+} commonAlertFlds;
+
+// These bit numbers must match the locations in the alertReg union
+// They are used by coding that requires either a mask or a bit number.
+/**
+    \brief Common Alert Bit numbers.
+
+    These numbers can be used to construct masks into the alert/warning
+    register.
+**/
+/** \cond INTERNAL_DOC **/
+typedef enum _commonAlertBits {
+    ALERT_FW_SELFTEST_BIT                       = 0,
+    ALERT_FW_NET_BUF_OVERRUN_BIT                = 1,
+    ALERT_FW_ERROR0_BIT                         = 2,
+    ALERT_FW_ERROR1_BIT                         = 3,
+    ALERT_FW_STACK_OVERRUN_BIT                  = 4,
+    ALERT_FW_WATCHDOG_RESTARTED_BIT             = 5,
+    ALERT_FW_INVALID_CONFIGURATION_BIT			= 6,
+	ALERT_HW_POWER_BIT							= 11,   // Hw Shdn
+    ALERT_HW_CLOCK_PROBLEM_BIT                  = 12,   // HW Shdn
+    ALERT_HW_EEPROM_DEAD_BIT                    = 13,   // HW Shdn
+    ALERT_HW_FLASH_CORRUPT_BIT                  = 14,   // sw Shdn
+    ALERT_HW_FLASH_CHANGED_BIT                  = 15,
+    ALERT_HW_RAM_BIT                            = 16,   // HW Shdn
+    ALERT_HW_ADC_BIT                            = 17,   // Hw Shdn
+    ALERT_HW_ADC_SATURATION						= 18,
+    ALERT_NET_VOLTAGE_LOW_BIT                   = 24,   // sw Shdn
+    ALERT_NET_WATCHDOG_BIT                      = 25,
+    ALERT_NET_ESTOPPED_BIT                      = 28,   // mtn Shdn
+    ALERT_NET_CONFIG_OUT_OF_DATE_BIT            = 29,   // sw Shdn
+    ALERT_RUN_TIME_ERR_BIT                      = 30,    // sw Shdn
+	ALERT_LOG_EPOCH_CODE                        = 0xFE,
+	ALERT_LOG_FREE_CODE                         = 0xFF
+} commonAlertBits;
+/** \endcond **/
+//                                                                           *
+//****************************************************************************
+
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
+// STATUS REGISTER COMMON FIELD DEFINITIONS
+//=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
+
+//*****************************************************************************
+// NAME                                                                       *
+//  lowAttnCommonFlds struct
+//
+// DESCRIPTION
+/**
+ 	\cond ISC_DOC
+    \brief <i>Lower Attentionable</i> portion of the <i>Status Register</i>.
+
+    This portion of the Status Register (#mnStatusReg) can be used to generate
+    attention packets and has common features across all models.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct PACK_BYTES _lowAttnCommonFlds {
+   /**
+		\brief Warning is present.
+
+        This bit asserts when the <i>Warning Register</i> contents,
+        ANDed with the user's <i>Warning Mask
+        Register</i> contents, is non-zero.
+
+        \remark
+        This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld Warning        : 1;    // 0  00 Warning is present
+    /**
+		\brief User alert is present.
+
+        This bit asserts when the <i>Alert Register</i> contents,
+        ANDed with the user's <i>Alert Mask
+        Register</i> contents,is non-zero.
+
+        \remark
+        This bit can generate an attention request to the host for
+        autonomous handling.
+    **/
+    BFld UserAlert      : 1;    // 1  01 User Alert is present
+    /**
+		\brief Not ready for operation.
+
+        This bit asserts when the node is not ready. Consult the
+        <i>Status Register</i> (#mnStatusReg) and if indicated
+		the <i>Alert Register</i> (#alertReg), for the reasons why the node is 
+		not ready.
+
+        If the shutdown is clearable, the user application can try to 
+        clear the alerts with the IStatus::AlertsClear function. If the 
+		<i>Enable Request</i> for the drive is still asserted and
+        there are no other shutdown reasons, the node will
+        automatically become ready.
+
+        \remark
+        This bit can generate an attention request to the host for
+        autonomous handling.
+	**/
+    BFld NotReady       : 1;    // 2  02 Not Rdy for Operation
+} lowAttnCommonFlds;
+//                                                                           *
+//****************************************************************************
+
+//*****************************************************************************
+// NAME                                                                       *
+//  plaInCommonFlds struct
+//
+// DESCRIPTION
+/**
+	\cond ISC_DOC
+    \brief <i>PLA Inputs</i> portion of the <i>Status Register</i>.
+
+    The middle portion of the Status Register (#mnStatusReg) that feeds the PLA
+    function. The lower eight bits can be used to generate attention
+    packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct PACK_BYTES _plaInCommonFlds {
+   /**
+        This bit represents the receipt of a node stop event. Depending
+        on the method the node stop was initiated with, the node may
+        or may not accept motion commands and may not allow changes to
+        the output register. If the node stop involved an E-Stop request
+        this bit will remain on until the E-Stop state is cleared.
+
+        Node stops with the <i>Quiet</i> bit set will not assert
+        this bit.
+
+        \see \ref ISCnodeStopPage
+    **/
+    BFld NodeStopped    : 1;    // 0  16: node stop
+	/** \cond INTERNAL_DOC **/
+    BFld na0_15         : 15;
+	/** \endcond **/
+} plaInCommonFlds;
+//                                                                           *
+//****************************************************************************
+
+//*****************************************************************************
+// NAME                                                                       *
+//  nonAttnCommonFlds struct
+//
+// DESCRIPTION
+
+/**
+    \brief Common Non-Attentional portion of the <i>Status Register</i>.
+
+    The most significant sixteen bit portion of the <i>Status Register</i>
+    (#mnStatusReg).
+    This portion of the register does not generate any attention packets.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct PACK_BYTES _nonAttnCommonFlds {
+	/** \cond INTERNAL_DOC **/
+    BFld				: 3;
+	/** \endcond **/
+    /**
+		\brief Node in <i>Controlled Stop</i>.
+
+        The Node Stop feature has forced the node into its <i>
+        Controlled</i> state.
+
+    **/
+    BFld InCtrlStop     : 1;    // 3  35: Output Register is controlled
+    /**
+		\brief Fan running.
+
+        For units with a fan, this field is asserted when the
+        fan is on.
+    **/
+    BFld FanOn          : 1;    // 4  36: Fan is running
+	/** \cond INTERNAL_DOC **/
+    BFld		        : 5;
+	/** \endcond **/
+    /**
+		\brief Hardware failure detected.
+
+        The unit's shutdown is caused by a hardware failure. This
+        unit should be replaced.
+    **/
+    BFld HwFailure      : 1;    // 10 42: Replace the node
+} nonAttnCommonFlds;
+//                                                                           *
+//****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  commonStatusFlds struct
+//
+// DESCRIPTION
+
+/**
+    \brief Common portions of the <i>Status Register</i>.
+
+	This is the structure defined for Meridian ISC's status register.
+
+	\see \ref mnStatusReg for details about accessing this type of register.
+**/
+typedef struct PACK_BYTES _commonStatusFlds {
+	/**
+		\brief Lower attentionable register.
+	**/
+	lowAttnCommonFlds LowAttn;
+	/**
+		\brief Input register with partial attentionable fields.
+	**/
+	plaInCommonFlds PlaIn;
+	/**
+		\brief Non-attentionable fields.
+	**/
+	nonAttnCommonFlds NonAttn;
+} commonStatusFlds;
+//                                                                           *
+//****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  sensorlessMethodsReg union
+//
+// DESCRIPTION
+/**
+\brief Sensorless start methods.
+
+This bit-mapped control register definitions.
+**/
+union sensorlessMethodsReg {
+	/// Numeric representation of sensorless start methods.
+	typedef enum _sensorlessMethods {
+		INDUCTANCE=1,					///<  1 Pulse voltages and measure current response
+		INDEX_SEARCH=2,					///<  2 Lock vector and move to an index
+		MAG_ALIGN_UNDAMPED=4,			///<  4 30 degree lock vector sweep/undamped
+		MAG_ALIGN_DAMPED=8
+	} sensorlessMethods;
+	/// Field access to sensorless start methods
+	struct _sensorlessFlds {
+		BFld Inductance : 1;
+		BFld IndexSearch : 1;
+		BFld MagAlignUndampled : 1;
+		BFld MagAlignDamped : 1;
+	} fld;
+	/// Bit-wise representation of methods
+	sensorlessMethods bits;
+};
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  Travel Limit Switch Handling enumeration
+//
+// DESCRIPTION
+/**
+	\brief Generic Travel Limit handling enumeration.
+**/
+/// General Purpose Input/Limit Switch handling
+typedef enum _mnLimitModes {
+	/*!
+		Ignores General Purpose inputs for travel limits.
+	**/
+	LIMIT_MODE_OFF,                     //  0: ignore limits
+	/*!
+		Travel Limits use General Purpose inputs.
+	**/
+	LIMIT_MODE_POSITION,                //  1: Limit position
+	/*!
+		Not implemented (Torque OFF)
+	**/
+	LIMIT_MODE_TORQUE,                  //  2
+	/*!
+		Travel limits set using node positional limit parameters
+		and General Purpose inputs.
+	**/
+	LIMIT_MODE_POSN_INS_AND_SOFT = -3,	// -3:
+	/*!
+		Travel limits set using node positional limit parameters.
+	**/
+	LIMIT_MODE_SOFT_POSN = -4			//  4: Software position limit
+} mnLimitModes;                           ///< GPI/Limit Switch Modes
+//                                                                            *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  High Level Feedback modes
+//
+// DESCRIPTION
+/**
+	\brief High Level Feedback modes.
+**/
+typedef enum _mnHLFBmodes {
+	HLFB_BRAKE_OFF,					///<  0 Brake off (Servo On), not shutdown
+	HLFB_ASG,						///<  1 All Systems Go
+	HLFB_SPEED,						///<  2 PWM output proportional to measured speed
+	HLFB_FORCE_OFF,					///<  3 Always off (test mode)
+	HLFB_FORCE_ON,					///<  4 Always on (test mode)
+	HLFB_INDEX,						///<  5 Output on when index occurs
+	HLFB_IN_RANGE,					///<  6 Position in-range
+	HLFB_TORQUE_ASG,				///<  7 Torque/ASG, 5%=-100, 95%=100
+	HLFB_TORQUE						///<  8 Torque out 5%=-100, 50%=0, 95%=100
+} mnHLFBmodes;
+//                                                                            *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME                                                                       *
+//  Disable Action enumerations
+//
+// DESCRIPTION
+/**
+ * Disable actions enumeration
+ *
+ * These values determine the drive's actions to take upon disable, LPB
+ * or AC Loss.
+ **/
+typedef enum _mnDisableActions {
+	/**
+	 * Use dynamic brake to stop
+	 *
+	 * This potentially is the most abrupt way to stop as it uses the
+	 * shorted motor windings to dissipate the kinetic energy of the
+	 * axis.
+	 **/
+	DYNAMIC_BRAKE,
+	/**
+	 * Controlled deceleration to a stop.
+	 *
+	 * Uses the motion constraints defined by the current move to
+	 * ramp to a stop then disable the drive.
+	 **/
+	DECEL_TO_STOP,
+	/**
+	 * Coast to a stop.
+	 *
+	 * Free wheel the axis until it stops from its own friction.
+	 **/
+	COAST
+} mnDisableActions;
+//                                                                            *
+//*****************************************************************************
+
+
+ #endif // __PUBREGFLDCOMMON_H__
+//============================================================================= 
+//	END OF FILE pubRegFldCommon.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubSysCls.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubSysCls.h
new file mode 100644
index 000000000..dad1d79cf
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/pubSysCls.h
@@ -0,0 +1,6292 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/inc/pubSysCls.h $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: pubSysCls.h $
+//
+// DESCRIPTION:
+/**
+	\file	
+	sFoundation 2.0 Software Framework Class Library.
+
+	sFoundation 2.0 software framework for host programming a system
+	of ClearPath-SC nodes. This framework implements a rich class library
+	for interacting with the nodes via C++.ZSFzsdfzdzd
+**/
+// PRINCIPLE AUTHORS:
+//		DWS
+//
+// CREATION DATE:
+//		2015-12-08 12:36:45
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __PUBSYSCLS_H__
+#define __PUBSYSCLS_H__
+
+
+//*****************************************************************************
+// NAME																          *
+// 	pubSysCls.h headers
+//
+#include "tekTypes.h"
+#include "pubCoreRegs.h"
+#include "pubPwrReg.h"
+#include "pubNetAPI.h"
+
+// Use C++ lib strings
+#include <string>
+#include <vector>
+
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubSysCls.h forward references
+													/** \cond INTERNAL_DOC **/	
+namespace sFnd 
+{
+	class INode;
+	class IPort;
+	class IAttnPort;
+	/**
+		Function template for the attention callback function.
+	**/
+	typedef void (nodeCallback *mnAttnCallback)(const mnAttnReqReg &detected);
+}
+//													/** \endcond **/
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	pubSysCls.h constants
+//
+//
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+
+/**
+	Teknic S-Foundation namespace.
+**/
+namespace sFnd 
+{
+#if defined(__GNUC__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wreorder"
+#endif
+
+//*****************************************************************************
+// NAME																	      *
+// 	IObj Class
+/**
+	\brief Feature Availability Interface. 
+
+	This is the base object for all feature objects. It provides the 
+	function for determining whether a "feature object" is supported.
+**/
+class MN_EXPORT IObj
+{
+													/** \cond INTERNAL_DOC **/	
+	friend class CPMinfo;
+	friend class CPMnode;
+													/** \endcond **/
+public:
+	/**
+		\brief Query if this feature is supported in this node.
+
+		\return Returns true if this object is supported by this node.
+		
+		A programmatic way of determining if this node supports this feature.
+		Some features are not available on certain types of nodes.
+	**/
+	virtual bool Supported();
+
+													/** \cond INTERNAL_DOC **/	
+private:
+	// Flag showing support
+	bool m_supported;
+
+protected:
+	IObj();
+	IObj(bool support);
+
+protected:
+	/// Sets the supported state for this object
+	void Supported(bool newState);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IObjWithNode Class
+/**
+	\brief Feature Availability And Root Node Access Interface. 
+
+	This is the base object for all Node Level feature Objects, and provides a
+	common function each feature to have a back link to the owner node. 
+**/
+class MN_EXPORT IObjWithNode : public IObj
+{
+public:
+	/**
+		\brief Reference to our node object.
+
+		\return Reference to our node object.
+
+		This member function is useful when you want to return the root of your
+		node when you are using a feature object. For example, your are 
+		interacting with a status object IStatus and you wish to disable the
+		node.
+
+		\CODE_SAMPLE_HDR
+		// Access another feature from another feature
+		myStatusObj.Node().EnableReq(false));
+		\endcode
+	**/
+	INode &Node() { return *m_pNode; }
+protected:
+													/** \cond INTERNAL_DOC **/
+	INode *m_pNode;
+	IObjWithNode(INode &ourNode); 
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IObjWithPort Class
+/**
+	\brief Feature Availability And Port Access Interface.
+
+	This is the base object for all Port Level feature Objects.
+**/
+class MN_EXPORT IObjWithPort : public IObj
+{
+protected:
+													/** \cond INTERNAL_DOC **/
+	/// Pointer to our IPort object
+	IPort *m_pPort;
+	/// Construction with tie-in to our port
+	IObjWithPort(IPort &ourPort);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueBase class
+/**
+
+\brief Node Parameter Container Base Class. 
+
+This class defines the base parameter access 
+object with functions to determine the existence, volatility, and refresh parameters from
+a node. 
+
+This object provides your application with:
+- A test for parameter existence for your node
+- A test for volatile type parameters
+- A Refresh control for volatile parameters such as position
+**/
+class MN_EXPORT ValueBase : public IObjWithNode
+{
+													/** \cond INTERNAL_DOC **/
+	friend class ValueString;
+	friend class ValueDouble;
+	friend class ValueSigned;
+	friend class ValueUnsigned;
+	friend class ValueAlert;
+	friend class ValueAppConfigReg;
+	friend class ValueHwConfigReg;
+	friend class ValuePowerReg;
+	friend class ValueOutReg;
+	friend class ValueStatus;
+	friend class CPMstring;
+	friend class CPMstatus;
+	friend class CPMstatusAdv;
+	friend class CPMouts;
+	friend class CPMmotion;
+private:
+	double m_scaleToUser;
+	nodeparam m_paramNum;
+	bool m_valid;
+	bool m_exists;
+	bool m_isVolatile;
+	bool m_refreshOnAccess;
+													/** \endcond **/
+public:
+	/**
+		\brief Update our local copy from the node
+
+		Use this function to update the local cached copy of the node's
+		parameter. For most static type parameters, there is little need to
+		call this member function as the first access will perform this
+		operation automatically.
+
+		For dynamic parameters, such as position, status and velocity, use
+		this function to obtain a fresh copy from the node.
+
+		\see AutoRefresh(bool) for changing the behavior to refresh on each
+		access.
+	**/
+	virtual void Refresh() = 0;
+
+	/**
+		\brief Determine the parameter's existence.
+
+		Determine the parameter's existence.
+
+		This is a helpful function when a mixture of node types may be in
+		a system an some models may not support certain parameters.
+
+		\return True if the underlying parameter exists for this node.
+
+		
+	**/
+	bool Exists() { return m_exists; }
+
+	/**
+		\brief Adjust the auto-refresh setting
+
+		Quite often a application needs to get a snapshot of a parameter for
+		use during a loop through the application logic. If you don't care about
+		"sample-time" consistency, you can save calling the \a Refresh
+		function before each access by setting this to true.
+
+		The default is false for this setting. This will cause one refresh
+		on the first access.
+
+		\note For performance reasons, don't set AutoRefresh on static
+		type parameters, such as Acceleration Limits. Setting this true will
+		cause network traffic on each inquiry to the value.
+
+		\param[in] newState Set true to force a refresh on each value access.
+		This should only be used for dynamic parameters such as position.
+	**/
+	void AutoRefresh(bool newState) { m_refreshOnAccess = newState; }
+
+	/**
+		\brief Return the auto-refresh state
+
+		This feature controls when queries from a node occur. If true is returned,
+		each inquiry via the Value or type conversion functions will
+		result in network traffic to query the value from the node.
+
+		If false is returned, only the first inquiry will transfer data from the
+		node.
+
+		\return Current auto-refresh state.
+
+		
+	**/
+	bool AutoRefresh() { return m_refreshOnAccess; }
+
+	/**
+	\brief Determine if this parameter is a dynamic parameter.
+
+	Determine if this parameter is a dynamic parameter, such as status.
+
+	\return True if the value of this parameter can change after refresh.
+	**/
+	bool IsVolatile() { return m_isVolatile; }
+													/** \cond INTERNAL_DOC **/
+protected:
+	/// Set Valid state
+	void Valid(bool newState);
+	/// Set/Get parameter number
+	void ParamNum(nodeparam newParamNum);
+	nodeparam ParamNum() { return m_paramNum; }
+	/// Set value scale constant
+	void Scale(double newScale);
+	/// Construction
+	ValueBase(INode &node, nodeparam pNum);
+	/// Existence flag setup
+	void Exists(bool newState);
+	/// Set the volatile state
+	void IsVolatile(bool newState) {m_isVolatile = newState;}
+public:
+	virtual ~ValueBase() {};
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueDouble class
+/**
+	\brief This class object implements access to floating point parameters from
+	a node. 
+	This class object implements access to floating point parameters within the node.
+
+	For most applications the following code sequence samples illustrate
+	the commonly used functions.
+
+	\CODE_SAMPLE_HDR
+	// Setting a value
+	myNode.someFeature.someParameter = 12345;
+
+	// Getting a value
+	double myVal = myNode.someFeature.someParameter;
+
+	// Using a parameter in a calculation
+	double myCalVal = myNode.someFeature.someParameter.Value() + 1000;
+
+	// Making a copy of a value. This copy will run independently of the
+	// node's reference. For example, myCopy.Refresh() will only
+	// update myCopy's internal value.
+	ValueDouble myCopy = myNode.someFeature.someParameter;
+
+	// Making a short-cut reference. This sometimes can reduce the typing
+	// requirements for using a parameter. In this example, myRef for
+	// all intents and purposes is the same as myNode.aFeature.aParameter.
+	ValueDouble &myRef = myNode.someFeature.someParameter;
+	myRef.Refresh();
+	// is the same as
+	myNode.someFeature.someParameter.Refresh();
+	\endcode
+
+	\see [Value Parameter Overview](@ref ValueSect) for more information on ValueXXXX Classes
+**/
+class MN_EXPORT ValueDouble : public ValueBase
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IInfo;
+	friend class IHoming;
+	friend class ILimits;
+	friend class ILimitsAdv;
+	friend class IMotion;
+	friend class IMotionAdv;
+	friend class IStatusAdv;
+	friend class CPMnode;
+	friend class IStatus;
+	friend class ISetup;
+	friend class ISetupEx;
+
+protected:
+	// Source of parameter value
+	enum _srcs {
+		VIA_PARAM
+	};
+	double m_lastValue;
+	double m_currentValue;
+	enum _srcs m_src;
+													/** \endcond **/
+public:
+	/*
+		\brief Query the node and obtain a new copy of the parameter.
+
+		Query the node and obtain a new copy of the parameter.
+
+
+		\CODE_SAMPLE_HDR
+		//Refresh a volatile parameter before reading
+		mynode.someFeature.someParameter.Refresh();
+		\endcode
+	**/
+	void Refresh();
+
+	/**
+		\brief Set new double value using the assignment operator.
+
+		Set new double value using the assignment operator.
+
+		\param[in] newValue New value to send to the node.
+
+		\CODE_SAMPLE_HDR
+		myNode.someFeature.someParameter = 1000;
+		\endcode
+
+		\see sFnd::ValueDouble::Value For explicit function way of setting
+		a parameter as well as it's power-on default value.
+	**/
+	double operator=(double newValue);
+
+	/**
+		\brief Get the current value and ensure it is represented as a double.
+
+		Get the current value and ensure it is represented as a double.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		double myDouble = myNode.someFeature.someParameter;
+		
+		// Explicit conversion
+		printf("%f", double(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator double();
+
+	/**
+		\brief Get the current value and ensure it is represented as a signed integer.
+
+		Get the current value and ensure it is represented as a signed integer.
+
+		\note If the parameter is larger then +/- 31-bits the value will be truncated.
+		
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		int32_t myInt = myNode.someFeature.someParameter;
+		
+		// Explicit conversion
+		printf("%d", int32_t(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator int32_t();
+
+	/**
+		\brief Get the current value and ensure it is an unsigned integer.
+
+		Get the current value and ensure it is an unsigned integer.
+
+		\note If the parameter is larger then 32-bits the value will be truncated.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		uint32_t myInt = myNode.someFeature.someParameter;
+		
+		// Explicit conversion
+		printf("%u", uint32_t(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator uint32_t();
+
+	/**
+		\brief Change our run-time parameter and optionally update the non-volatile
+		default power-up value.
+
+		Change our run-time parameter and optionally update the non-volatile
+		default power-up value.
+
+		\param[in] newValue New value to send to the node.
+		\param[in] makeNonVolatile [Optionally update the non-volatile power
+		on default as well]
+
+		\CODE_SAMPLE_HDR
+		// Set the run-time value only
+		myNode.someFeature.someParameter.Value(1000);
+		// Set the run-time value and non-volatile power-on default
+		myNode.someFeature.someParameter.Value(1000, true);
+		\endcode
+
+		\note Care should be taken to not excessively write the non-volatile
+		power-up default parameter as the memory has a write count limitation.
+
+		\see #sFnd::ValueDouble::operator= For a simpler syntax for setting
+		a parameter.
+	**/
+	void Value(int32_t newValue, bool makeNonVolatile = false);
+
+	/**
+		\brief Change our run-time parameter and optionally update the non-volatile
+		default power-up value.
+
+		Change our run-time parameter and optionally update the non-volatile
+		default power-up value.
+
+		\param[in] newValue New value to send to the node.
+		\param[in] makeNonVolatile [Optionally update the non-volatile power
+		on default as well]
+
+		\CODE_SAMPLE_HDR
+		// Set the run-time value only
+		myNode.someFeature.someParameter.Value(1000.5);
+		// Set the run-time value and non-volatile power-on default
+		myNode.someFeature.someParameter.Value(1000.5, true);
+		\endcode
+
+		\note Care should be taken to not excessively write the non-volatile
+		power-up default parameter as the memory has a write count limitation.
+
+		\see #sFnd::ValueDouble::operator= For simplified syntax to write
+		the run-time value.
+		**/
+	void Value(double newValue, bool makeNonVolatile=false);
+
+	/**
+		\brief Return the parameter's current value as a double.
+
+		Return the parameter's current value as a double.
+
+		\param[in] getNonVolatile If true, the power-on default non-volatile
+		value is returned.
+
+		\CODE_SAMPLE_HDR
+		// Get and print the run-time value
+		cout << myNode.someFeature.someParameter.Value() << endl;
+		// Get and print the power-on default non-volatile value
+		cout << myNode.someFeature.someParameter.Value(true) << endl;
+		\endcode
+	**/
+	double Value(bool getNonVolatile = false);
+
+	/** \cond INTERNAL_DOC **/
+	// - - - - - - - - - - - - - - - - - - -
+	// Common overrides for signed integers
+	// - - - - - - - - - - - - - - - - - - -
+	double operator|(int32_t arg) {
+		return(operator int32_t() | arg);
+	}
+	double operator&(int32_t arg) {
+		return(operator int32_t() & arg);
+	}
+	double operator^(int32_t arg) {
+		return(operator int32_t() ^ arg);
+	}
+	double operator+(int32_t arg) {
+		return(operator double() + arg);
+	}
+	double operator-(int32_t arg) {
+		return(operator double() - arg);
+	}
+	double operator*(int32_t arg) {
+		return(operator double() * arg);
+	}
+	double operator/(int32_t arg) {
+		return(operator double() / arg);
+	}
+	double operator|=(int32_t arg) {
+		return(operator=(operator|(arg)));
+	}
+	double operator&=(int32_t arg) {
+		return(operator=(operator&(arg)));
+	}
+	double operator^=(int32_t arg) {
+		return(operator=(operator^(arg)));
+	}
+	double operator+=(int32_t arg) {
+		return(operator=(operator+(arg)));
+	}
+	double operator-=(int32_t arg) {
+		return(operator=(operator-(arg)));
+	}
+	double operator*=(int32_t arg) {
+		return(operator=(operator*(arg)));
+	}
+	double operator/=(int32_t arg) {
+		return(operator=(operator/(arg)));
+	}
+	
+	// - - - - - - - - - - - - - - - - - - -
+	// Common overrides for unsigned integers
+	// - - - - - - - - - - - - - - - - - - -
+	double operator|(uint32_t arg) {
+		return(operator uint32_t() | arg);
+	}
+	double operator&(uint32_t arg) {
+		return(operator uint32_t() & arg);
+	}
+	double operator^(uint32_t arg) {
+		return(operator uint32_t() ^ arg);
+	}
+	double operator+(uint32_t arg) {
+		return(operator double() + arg);
+	}
+	double operator-(uint32_t arg) {
+		return(operator double() - arg);
+	}
+	double operator*(uint32_t arg) {
+		return(operator double() * arg);
+	}
+	double operator/(uint32_t arg) {
+		return(operator double() / arg);
+	}
+	double operator|=(uint32_t arg) {
+		return(operator=(operator|(arg)));
+	}
+	double operator&=(uint32_t arg) {
+		return(operator=(operator&(arg)));
+	}
+	double operator^=(uint32_t arg) {
+		return(operator=(operator^(arg)));
+	}
+	double operator+=(uint32_t arg) {
+		return(operator=(operator+(arg)));
+	}
+	double operator-=(uint32_t arg) {
+		return(operator=(operator-(arg)));
+	}
+	double operator*=(uint32_t arg) {
+		return(operator=(operator*(arg)));
+	}
+	double operator/=(uint32_t arg) {
+		return(operator=(operator/(arg)));
+	}
+
+	// Common overrides for doubles
+	double operator+(double arg) {
+		return(operator double() + arg);
+	}
+	double operator-(double arg) {
+		return(operator double() - arg);
+	}
+	double operator*(double arg) {
+		return(operator double() * arg);
+	}
+	double operator/(double arg) {
+		return(operator double() / arg);
+	}
+	double operator+=(double arg) {
+		return(operator=(operator+(arg)));
+	}
+	double operator-=(double arg) {
+		return(operator=(operator-(arg)));
+	}
+	double operator*=(double arg) {
+		return(operator=(operator*(arg)));
+	}
+	double operator/=(double arg) {
+		return(operator=(operator/(arg)));
+	}
+	/** \endcond **/
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValueDouble(INode &node, nodeparam pNum, enum _srcs src = VIA_PARAM);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueSigned class
+/**
+	\brief Signed 32-bit Integer Parameter Object.
+
+	This class object implements access to integer parameters within the node.
+
+	For most applications the following code sequence samples illustrate
+	the commonly used functions.
+
+	\CODE_SAMPLE_HDR
+	// Setting a value
+	myNode.someFeature.someParameter = 12345;
+
+	// Getting a value
+	int32_t myVal = myNode.someFeature.someParameter;
+
+	// Using a parameter in a calculation
+	int32_t myCalVal = myNode.someFeature.someParameter.Value() + 1000;
+
+	// Making a copy of a value. This copy will run independently of the
+	// node's reference. For example, myCopy.Refresh() will only
+	// update myCopy's internal value.
+	ValueSigned myCopy = myNode.someFeature.someParameter;
+
+	// Making a short-cut reference. This sometimes can reduce the typing
+	// requirements for using a parameter. In this example, aRef for
+	// all intents and purposes is the same as myNode.aFeature.aParameter.
+	ValueSigned &myRef = myNode.someFeature.someParameter;
+	myRef.Refresh();
+	// is the same as
+	myNode.someFeature.someParameter.Refresh();
+	\endcode
+
+	\see [Value Parameter Overview](@ref ValueSect) for more information on ValueXXXX classes.
+**/
+class MN_EXPORT ValueSigned : public ValueBase
+{
+	/** \cond INTERNAL_DOC **/
+	friend class IInfo;
+	friend class IHoming;
+	friend class ILimits;
+	friend class IMotion;
+	friend class IMotionAdv;
+	friend class IStatusAdv;
+
+private:
+	int32_t m_lastValue;
+	int32_t m_currentValue;
+	/** \endcond **/
+public:
+	/**
+		\brief Query the node and obtain a new copy of the parameter.
+
+		Query the node and obtain a new copy of the parameter.
+
+
+		\CODE_SAMPLE_HDR
+		//Refresh a volatile parameter before reading
+		mynode.someFeature.someParameter.Refresh();
+		\endcode
+	**/
+	void Refresh();
+
+	/**
+		\brief Set new signed value using the assignment operator.
+
+		Set new signed value using the assignment operator.
+
+		This is the most common way to change an integer based parameter.
+
+		\CODE_SAMPLE_HDR
+		myNode.someFeature.someParameter = 1000;
+		\endcode
+
+		\see sFnd::ValueSigned::Value For an explicit way of setting
+		a parameter as well as it's power-on default value.
+	**/
+	int32_t operator=(int32_t newValue);
+
+	/**
+		\brief Get the current value and ensure it is represented as a double.
+
+		Get the current parameter as double.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		double someDouble = myNode.someFeature.someParameter;
+		or
+		// Explicit conversion
+		printf("%f", double(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator double();
+	/**
+		\brief Get the current value and ensure it is represented as a signed 
+		integer.
+
+		Get the current parameter as a signed integer.
+
+		\note If the parameter is larger then +/- 31-bits the value will be 
+		truncated.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		int32_t someInt = myNode.someFeature.someParameter;
+		or
+		// Explicit conversion
+		printf("%d", int32_t(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator int32_t();
+	/**
+		\brief Get the current value and ensure it is an unsigned integer.
+
+		Get the current parameter as an unsigned integer.
+
+		\note If the parameter is larger then 32-bits the value will be 
+		truncated.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		uint32_t someInt = myNode.someFeature.someParameter;
+		or
+		// Explicit conversion
+		printf("%u", uint32_t(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator uint32_t();
+	/**
+		\brief Change our integer based parameter and optionally update the 
+		non-volatile default value.
+
+		\param[in] newValue New value to send to the node.
+		\param[in] makeNonVolatile [Optionally update the non-volatile power-on
+		default as well]
+
+		\CODE_SAMPLE_HDR
+		// Set Value and non-volatile power-on default
+		myNode.someFeature.someParameter.Value(-1000, true);
+		// Set Value only
+		myNode.someFeature.someParameter.Value(-1000);
+		\endcode
+
+		\note Care should be taken to not excessively write the non-volatile
+		parameter as the memory has a write count limitation.
+
+		\see sFnd::ValueSigned::operator= For simplified syntax to write
+		the run-time value.
+	**/
+	void Value(int32_t newValue, bool makeNonVolatile = false);
+	/**
+		\brief Get the current parameter value as an integer.
+
+		\param[in] getNonVolatile If set, the value returned will be the
+		power-on non-volatile value.
+
+		\CODE_SAMPLE_HDR
+		// Get and print the run-time value
+		cout << myNode.Limits.SoftLimit0.Value() << endl;
+		// Get and print the power-on default non-volatile value
+		cout << myNode.Limits.SoftLimit0.Value(true) << endl;
+		\endcode
+
+		\note Care should be taken to not excessively write the non-volatile
+		parameter as the memory has a write count limitation.
+	**/
+	int32_t Value(bool getNonVolatile=false);
+	/** \cond INTERNAL_DOC **/
+	// - - - - - - - - - - - - - - - - - - -
+	// Common overrides for signed integers
+	// - - - - - - - - - - - - - - - - - - -
+	int32_t operator|(int32_t arg) {
+		return(operator int32_t() | arg);
+	}
+	int32_t operator&(int32_t arg) {
+		return(operator int32_t() & arg);
+	}
+	int32_t operator^(int32_t arg) {
+		return(operator int32_t() ^ arg);
+	}
+	int32_t operator+(int32_t arg) {
+		return(operator int32_t() + arg);
+	}
+	int32_t operator-(int32_t arg) {
+		return(operator int32_t() - arg);
+	}
+	int32_t operator*(int32_t arg) {
+		return(operator int32_t() * arg);
+	}
+	int32_t operator/(int32_t arg) {
+		return(operator int32_t() / arg);
+	}
+	int32_t operator|=(int32_t arg) {
+		return operator=(operator|(arg));
+	}
+	int32_t operator&=(int32_t arg) {
+		return operator=(operator&(arg));
+	}
+	int32_t operator^=(int32_t arg) {
+		return operator=(operator^(arg));
+	}
+	int32_t operator+=(int32_t arg) {
+		return operator=(operator+(arg));
+	}
+	int32_t operator-=(int32_t arg) {
+		return operator=(operator-(arg));
+	}
+	int32_t operator*=(int32_t arg) {
+		return operator=(operator*(arg));
+	}
+	int32_t operator/=(int32_t arg) {
+		return operator=(operator/(arg));
+	}
+
+	// Common overrides for unsigned integers
+	
+	int32_t operator|(uint32_t arg) {
+		return(operator int32_t() | arg);
+	}
+	int32_t operator&(uint32_t arg) {
+		return(operator int32_t() & arg);
+	}
+	int32_t operator^(uint32_t arg) {
+		return(operator int32_t() ^ arg);
+	}
+	int32_t operator+(uint32_t arg) {
+		return(operator int32_t() + arg);
+	}
+	int32_t operator-(uint32_t arg) {
+		return(operator int32_t() - arg);
+	}
+	int32_t operator*(uint32_t arg) {
+		return(operator int32_t() * arg);
+	}
+	int32_t operator/(uint32_t arg) {
+		return(operator int32_t() / arg);
+	}
+	int32_t operator|=(uint32_t arg) {
+		return operator=(operator|(arg));
+	}
+	int32_t operator&=(uint32_t arg) {
+		return operator=(operator&(arg));
+	}
+	int32_t operator^=(uint32_t arg) {
+		return operator=(operator^(arg));
+	}
+	int32_t operator+=(uint32_t arg) {
+		return operator=(operator+(arg));
+	}
+	int32_t operator-=(uint32_t arg) {
+		return operator=(operator-(arg));
+	}
+	int32_t operator*=(uint32_t arg) {
+		return operator=(operator*(arg));
+	}
+	int32_t operator/=(uint32_t arg) {
+		return operator=(operator/(arg));
+	}
+
+	// Common overrides for doubles
+	double operator+(double arg) {
+		return(operator int32_t() + arg);
+	}
+	double operator-(double arg) {
+		return(operator int32_t() - arg);
+	}
+	double operator*(double arg) {
+		return(operator int32_t() * arg);
+	}
+	double operator/(double arg) {
+		return(operator int32_t() / arg);
+	}
+	int32_t operator+=(double arg) {
+		return operator=(static_cast<int32_t>(operator+(arg)));
+	}
+	int32_t operator-=(double arg) {
+		return operator=(static_cast<int32_t>(operator-(arg)));
+	}
+	int32_t operator*=(double arg) {
+		return operator=(static_cast<int32_t>(operator*(arg)));
+	}
+	int32_t operator/=(double arg) {
+		return operator=(static_cast<int32_t>(operator/(arg)));
+	}
+	/** \endcond **/
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValueSigned(INode &node, nodeparam pNum);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueUnsigned class
+/**
+	\brief Unsigned 32-bit Integer Parameter Object.
+
+	This class object implements access to unsigned integer parameters within
+	the node.
+
+	For most applications the following code sequence samples illustrate
+	the commonly used functions.
+
+	\CODE_SAMPLE_HDR
+	// Setting a value
+	myNode.someFeature.someParameter = 12345;
+
+	// Getting a value
+	uint32_t myVal = myNode.someFeature.someParameter;
+
+	// Using a parameter in a calculation
+	uint32_t myCalVal = myNode.someFeature.someParameter.Value() + 1000;
+
+	// Making a copy of a value. This copy will run independently of the
+	// node's reference. For example, myCopy.Refresh() will only
+	// update myCopy's internal value.
+	ValueUnsigned myCopy = myNode.someFeature.someParameter;
+
+	// Making a short-cut reference. This sometimes can reduce the typing
+	// requirements for using a parameter. In this example, aRef for
+	// all intents and purposes is the same as myNode.aFeature.aParameter.
+	ValueUnsigned &myRef = myNode.someFeature.someParameter;
+	myRef.Refresh();
+	// is the same as
+	myNode.someFeature.someParameter.Refresh();
+	\endcode
+
+	\see [Value Parameter Overview](@ref ValueSect) for more information on ValueXXXX classes.
+**/
+class MN_EXPORT ValueUnsigned : public ValueBase
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IInfo;
+	friend class IHoming;
+	friend class ILimits;
+	friend class IMotion;
+	friend class IMotionAdv;
+private:
+	uint32_t m_lastValue;
+	uint32_t m_currentValue;
+													/** \endcond **/
+public:
+	/**
+		\brief Query the node and obtain a new copy of the parameter.
+
+		Query the node and obtain a new copy of the parameter.
+
+
+		\CODE_SAMPLE_HDR
+		//Refresh a volatile parameter before reading
+		mynode.someFeature.someParameter.Refresh();
+		\endcode
+	**/
+	void Refresh();
+
+	/**
+		\brief Set a new unsigned value using the assignment operator.
+
+		This is the most common way to change an integer based parameter.
+
+		\CODE_SAMPLE_HDR
+		myNode.someFeature.someParameter = 1000;
+		\endcode
+
+		\see sFnd::ValueSigned::Value For an explicit way of setting
+		a parameter as well as it's power-on default value.
+		**/
+		uint32_t operator=(uint32_t newValue);
+
+	/**
+		\brief Get the current parameter and ensure it is represented as a 
+		double.
+
+		Get the current parameter and format it as a double.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		double someDouble = myNode.someFeature.someParameter;
+		or
+		// Explicit conversion
+		printf("%f", double(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator double();
+
+	/**
+		\brief Get the current value and ensure it is an integer.
+
+		Get the current value and ensure it is an integer.
+
+		\note If the parameter is larger then 31-bits the value will be 
+		truncated or undefined.
+
+		\CODE_SAMPLE_HDR
+		// Implicit conversion
+		uint32_t someInt = myNode.someFeature.someParameter;
+		or
+		// Explicit conversion
+		printf("%u", int32_t(myNode.someFeature.someParameter));
+		\endcode
+	**/
+	operator uint32_t();
+
+	/**
+		\brief Change our integer based parameter and optionally update the
+		non-volatile default value.
+
+		Change our integer based parameter and optionally update the
+		non-volatile default value.
+
+		\param[in] newValue New value to send to the node.
+		\param[in] makeNonVolatile [Optionally update the non-volatile power-on
+		default as well]
+
+		\CODE_SAMPLE_HDR
+		// Set Value and non-volatile power-on default
+		myNode.someFeature.someParameter.Value(2000, true);
+		// Set Value only
+		myNode.someFeature.someParameter.Value(2000);
+		\endcode
+
+		\note Care should be taken to not excessively write the non-volatile
+		parameter as the memory has a write count limitation.
+
+		\see sFnd::ValueSigned::operator= For simplified syntax to write
+		the run-time value.
+	**/
+	void Value(uint32_t newValue, bool makeNonVolatile = false);
+
+	/**
+		\brief Get the current parameter value as an integer.
+
+		Get the current parameter value as an integer.
+
+		\param[in] getNonVolatile If set, the value returned will be the
+		power-on non-volatile value.
+
+		\CODE_SAMPLE_HDR
+		// Get and print the run-time value
+		cout << myNode.Limits.SoftLimit0.Value() << endl;
+		// Get and print the power-on default non-volatile value
+		cout << myNode.Limits.SoftLimit0.Value(true) << endl;
+		\endcode
+
+		\note Care should be taken to not excessively write the non-volatile
+		parameter as the memory has a write count limitation.
+	**/
+	uint32_t Value(bool getNonVolatile = false);
+	/** \cond INTERNAL_DOC **/
+	// - - - - - - - - - - - - - - - - - - -
+	// Common overrides for signed integers
+	// - - - - - - - - - - - - - - - - - - -
+	uint32_t operator|(int32_t arg) {
+		return(operator uint32_t() | arg);
+	}
+	uint32_t operator&(int32_t arg) {
+		return(operator uint32_t() & arg);
+	}
+	uint32_t operator^(int32_t arg) {
+		return(operator uint32_t() ^ arg);
+	}
+	uint32_t operator+(int32_t arg) {
+		return(operator uint32_t() + arg);
+	}
+	uint32_t operator-(int32_t arg) {
+		return(operator uint32_t() - arg);
+	}
+	uint32_t operator*(int32_t arg) {
+		return(operator uint32_t() * arg);
+	}
+	uint32_t operator/(int32_t arg) {
+		return(operator uint32_t() / arg);
+	}
+	uint32_t operator|=(int32_t arg) {
+		return operator=(operator|(arg));
+	}
+	uint32_t operator&=(int32_t arg) {
+		return operator=(operator&(arg));
+	}
+	uint32_t operator^=(int32_t arg) {
+		return operator=(operator^(arg));
+	}
+	uint32_t operator+=(int32_t arg) {
+		return operator=(operator+(arg));
+	}
+	uint32_t operator-=(int32_t arg) {
+		return operator=(operator-(arg));
+	}
+	uint32_t operator*=(int32_t arg) {
+		return operator=(operator*(arg));
+	}
+	uint32_t operator/=(int32_t arg) {
+		return operator=(operator/(arg));
+	}
+
+	// Common overrides for unsigned integers
+	
+	uint32_t operator|(uint32_t arg) {
+		return(operator uint32_t() | arg);
+	}
+	uint32_t operator&(uint32_t arg) {
+		return(operator uint32_t() & arg);
+	}
+	uint32_t operator^(uint32_t arg) {
+		return(operator uint32_t() ^ arg);
+	}
+	uint32_t operator+(uint32_t arg) {
+		return(operator uint32_t() + arg);
+	}
+	uint32_t operator-(uint32_t arg) {
+		return(operator uint32_t() - arg);
+	}
+	uint32_t operator*(uint32_t arg) {
+		return(operator uint32_t() * arg);
+	}
+	uint32_t operator/(uint32_t arg) {
+		return(operator uint32_t() / arg);
+	}
+	uint32_t operator|=(uint32_t arg) {
+		return operator=(operator|(arg));
+	}
+	uint32_t operator&=(uint32_t arg) {
+		return operator=(operator&(arg));
+	}
+	uint32_t operator^=(uint32_t arg) {
+		return operator=(operator^(arg));
+	}
+	uint32_t operator+=(uint32_t arg) {
+		return operator=(operator+(arg));
+	}
+	uint32_t operator-=(uint32_t arg) {
+		return operator=(operator-(arg));
+	}
+	uint32_t operator*=(uint32_t arg) {
+		return operator=(operator*(arg));
+	}
+	uint32_t operator/=(uint32_t arg) {
+		return operator=(operator/(arg));
+	}
+
+	// Common overrides for doubles
+	double operator+(double arg) {
+		return(operator uint32_t() + arg);
+	}
+	double operator-(double arg) {
+		return(operator uint32_t() - arg);
+	}
+	double operator*(double arg) {
+		return(operator uint32_t() * arg);
+	}
+	double operator/(double arg) {
+		return(operator uint32_t() / arg);
+	}
+	uint32_t operator+=(double arg) {
+		return operator=(static_cast<uint32_t>(operator+(arg)));
+	}
+	uint32_t operator-=(double arg) {
+		return operator=(static_cast<uint32_t>(operator-(arg)));
+	}
+	uint32_t operator*=(double arg) {
+		return operator=(static_cast<uint32_t>(operator*(arg)));
+	}
+	uint32_t operator/=(double arg) {
+		return operator=(static_cast<uint32_t>(operator/(arg)));
+	}
+	/** \endcond **/
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValueUnsigned(INode &node, nodeparam pNum);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueString class
+/**
+	\brief String Parameter Object.
+
+	This class object implements access to various string oriented
+	parameters within the node.
+
+	For most applications the following code sequence samples illustrate
+	the commonly used functions.
+
+	\CODE_SAMPLE_HDR
+	// Setting a value
+	myNode.someFeature.someParameter = 12345;
+
+	// Getting a value
+	String myVal = myNode.someFeature.someParameter;
+
+	// Using a parameter in a calculation
+	String myCalVal = myNode.someFeature.someParameter.Value() + 1000;
+
+	// Making a copy of a value. This copy will run independently of the
+	// node's reference. For example, myCopy.Refresh() will only
+	// update myCopy's internal value.
+	ValueString myCopy = myNode.someFeature.someParameter;
+
+	// Making a short-cut reference. This sometimes can reduce the typing
+	// requirements for using a parameter. In this example, aRef for
+	// all intents and purposes is the same as myNode.aFeature.aParameter.
+	ValueString &myRef = myNode.someFeature.someParameter;
+	myRef.Refresh();
+	// is the same as
+	myNode.someFeature.someParameter.Refresh();
+	\endcode
+
+	\see [Value Parameter Overview](@ref ValueSect) for more information on ValueXXXX classes.
+**/
+class MN_EXPORT ValueString : public ValueBase
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IInfo;
+	friend class CPMinfo;
+protected:
+	enum _srcs {
+		/**
+			String is the user ID
+		**/
+		STR_USERID,
+		/**
+			String is located in the defined parameter.
+		**/
+		STR_PARAM,
+		/**
+			String is the config file name
+		**/
+		STR_CONFIG_NAME,
+		/**
+			Firmware Version String
+		**/
+		STR_FW_VERSION,
+		/**
+			Hardware Version String
+		**/
+		STR_HW_VERSION,
+		/**
+			Return the model string
+		**/
+		STR_MODEL_STR
+	};
+
+	// C++ hack to create a constant
+	enum _MAX_STR { MAX_STR = MN_UI_STR_BUF_SIZE };
+	// Where to find string
+	enum _srcs  m_location;
+
+	char m_lastValue[MAX_STR];
+	char m_currentValue[MAX_STR];
+													/** \endcond **/
+public:
+	/**
+		\brief Query the node and obtain a new copy of the parameter.
+
+		Query the node and obtain a new copy of the parameter.
+
+
+		\CODE_SAMPLE_HDR
+		//Refresh a volatile parameter before reading
+		mynode.someFeature.someParameter.Refresh();
+		\endcode
+	**/
+	virtual void Refresh() = 0;
+
+	/**
+		\brief Update the string parameter.
+
+		\param[in] newValue New C-String to use for update.
+
+		Update the string parameter with \a newValue.
+
+		\CODE_SAMPLE_HDR
+		myNode.Info.UserID.Value("My Node");
+		\endcode
+	**/
+	virtual void Value(const char *newValue) = 0;
+
+	/**
+		\brief Get the current string parameter.
+
+		\return The current string parameter.
+
+		Return a pointer to a read-only buffer that contains the current
+		value. 
+
+		\CODE_SAMPLE_HDR
+		cout << myNode.Info.UserID.Value() << endl;
+		\endcode
+	**/
+	virtual const char *Value() = 0;
+
+	/**
+		\brief Update the string value using the assignment operator.
+
+		\param[in] newValue Incoming string pointer.
+
+		This is the most common way to change a string based parameter.
+
+		\CODE_SAMPLE_HDR
+		myNode.Info.UserID = "My Node";
+		\endcode
+	**/
+	const char *operator=(const char *newValue);
+
+	/**
+		\brief Get a Pointer to the Current String Value.
+
+		Get a pointer to the read-only current string value.
+
+		\CODE_SAMPLE_HDR
+		const char *myParam = myNode.Info.UserID;
+		\endcode
+	**/
+	operator const char *();
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValueString(INode &node, nodeparam pNum, enum _srcs location);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueStatus class
+/**
+	\brief Status Type Register Node Parameter Access Object.
+
+	This class object implements access to the various types of status register/masks within the
+	node.
+
+	Different Types of Node status registers are useful for determining whether a particular
+	status field is currently asserted, has been asserted since the last read, or has been cleared
+	since the last read.  The different types of Status Registers are:
+
+	- [Real-Time](@ref sFnd::IStatus::RT) Which represents the current state of the Status Register.
+	- [Rising](@ref sFnd::IStatus::Rise) Which tracks rising edges of status fields. Fields in this 
+	register are set when the [Real-Time](@ref sFnd::IStatus::RT) fields transition from 0 to 1.
+	- [Falling](@ref sFnd::IStatus::Fall) Which tracks falling edges of status fields. Fields in this 
+	register are set when the [Real-Time](@ref sFnd::IStatus::RT) fields transition from 1 to 0.
+	- [Accumulating](@ref sFnd::IStatus::Accum) Which represents the Or accumulation of the 
+	[Real-Time](@ref sFnd::IStatus::RT) register.
+
+	These registers are internally clear-on-read within the Node.  This object provides a
+	caching mechanism allowing the application to control when the stored value of this register is 
+	cleared/refreshed.  This allows multiple threads which are competing for different Status event to 
+	coexist without interfering with each other.
+
+	This object also provides access to Status masks used to generate attentions.
+
+	\see sFnd::IStatus::RT
+	\see sFnd::IStatus::Rise
+	\see sFnd::IStatus::Fall
+	\see sFnd::IStatus::Accum
+	\see cpmStatusRegFlds for a complete list of ClearPath-SC Status Fields
+	\see \ref AttentionsPage
+**/
+class MN_EXPORT ValueStatus : public ValueBase
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IStatus;
+	friend class IAttnNode;
+private:
+	mnStatusReg m_lastValue;
+	mnStatusReg m_currentValue;
+	mnStatusReg m_testResult;
+	bool m_clearOnRead;
+													/** \endcond **/
+public:
+	/**
+		\brief Update our Status Register from the Node.
+
+		This function will atomically read and accumulate Rising, Falling, and Accumulating registers to prevent the loss of state information when accessed by 
+		multiple threads.  This means refreshing these registers will not clear any currently asserted bits. Use one of the [TestAndClear](@ref sFnd::ValueStatus::TestAndClear) 
+		functions to combine with testing to prevent possible information loss from clearing the entire register at once.
+
+		For the Real-Time register this function simply replaces the value of the stored register to the current status register within the Node.
+
+		\CODE_SAMPLE_HDR
+		//Refresh The Accumulating register
+		mynode.Status.Accum.Clear();		//Clear the accumulating register so we only capture accumulated events since the last read
+		mynode.Status.Accum.Refresh();		//Refresh the register
+
+		//Refresh the Register (No clear is needed since the Real Time register simply overwrites the REgister to be the current value)
+		mynode.Status.RT.Refresh();			
+
+		\endcode
+	**/
+	void Refresh();
+
+	/**
+		\brief Read, Test and Clear Accumulated <i>Status Register</i> state.
+
+		\param[in] mask fields to test for.
+		\param[out] result fields that were cleared.
+		\return true if one or more were true.
+	
+		This function is a thread safe way of updating and atomically testing 
+		and clearing fields from the accumulating <i>Status Registers</i> ()Rise, Fall, Accum). The 
+		\a result is updated with all the fields detected by the mask. This 
+		is useful when testing multiple fields.  This function is not needed with the Real-Time register.
+
+		\CODE_SAMPLE_HDR
+		//Create a Status register mask to test the Accumulating register
+		//Test for move done, A from start, and B from end.
+		mnStatusReg mymask;
+		mymask.cpm.MoveDone = 1;
+		mymask.cpm.BFromEnd = 1;
+		mymask.cpm.AFromStart = 1;
+
+		//Test and clear these three fields
+		mnStatusReg myResult;
+		if(mynode.Status.Accum(mymask,myResult))
+		{
+			if(myResult.cpm.MoveDone)
+			{ Move Done occured}
+			if(myResult.cpm.BFromEnd)
+			{ B from end occured}
+			if(myResult.cpm.AFromStart)
+			{ A from start occured}
+		}
+		//At this point the three fields are now clear in our stored copy of the Accum register Refresh to find more events 
+		\endcode
+	**/
+	bool TestAndClear(const mnStatusReg &mask, mnStatusReg &result);
+
+	/**
+		\brief Read and simple test and clear for single fields
+
+		\param[in] mask <i>Status Register</i> union with the desired field to 
+		test and clear.
+		\return True if the desired field was set.
+
+		This function is a thread safe way of updating and atomically testing
+		and clearing a field from the accumulating <i>Status Registers</i> ()Rise, Fall, Accum).
+		This function is not needed with the Real-Time register.
+
+		\note You should only use this function to test a single field. You cannot
+		determine which field was set if multiple fields are set in the mask.
+
+		\see sFnd::ValueStatus::TestAndClear(const mnStatusReg &, mnStatusReg &) for multiple
+		field test and clear.
+
+		\CODE_SAMPLE_HDR
+		//Create a Status register mask to test the Accumulating register
+		//Test for move done
+		mnStatusReg mymask;
+		mymask.cpm.MoveDone = 1;
+
+		//Test and clear the move done field
+		if(mynode.Status.Accum(mymask))
+		{Move Done occured}
+		
+		//At this point the three fields are now clear in our stored copy of the Accum register Refresh to find more events
+		\endcode
+	**/
+	bool TestAndClear(const mnStatusReg &mask);
+
+	/**
+		\brief Clear the accumulated state
+
+		This function is used to clear out accumulated status information
+		from the internal copy.   This function is not needed for the Real-Time register. 
+
+		\CODE_SAMPLE_HDR
+		//Clear, and refresh The Accumulating register
+		mynode.Status.Accum.Clear();
+		mynode.Status.Accum.Refresh();	
+
+		\endcode
+	**/
+	void Clear();
+
+	/**
+		\brief Assignment operator to update value with #mnStatusReg union value.
+
+		Assignment operator to update value with #mnStatusReg union value.
+		This function should only be used when setting up Status masks for attentions.
+		
+		\see sFnd::IAttnNode::Mask
+		\see sFnd::IAttnNode::StatusMask
+
+		\CODE_SAMPLE_HDR
+		//Create a Status register mask to set the Attentionable Status Mask to.
+		//Here we are setting up attentions for Move done, A from start, and B from end
+		// Only the lower 32 bits are attentionable.
+		mnStatusReg mymask;
+		mymask.cpm.MoveDone = 1;
+		mymask.cpm.BFromEnd = 1;
+		mymask.cpm.AFromStart = 1;
+
+		//Set the Node's Attentionable Status Mask to our mask.
+		mynode.Adv.Attn.Mask = mymask;
+
+		\endcode
+	**/
+	mnStatusReg &operator=(mnStatusReg &newValue);
+
+	/**
+		\brief Copy operator to return a copy of the current status type 
+		register.
+
+		Copy operator to return a copy of the current status type
+		register.
+	**/
+	operator mnStatusReg();
+
+	/**
+		\brief Return a copy of the last acquired Status Type Register.
+
+		Return a copy of the last acquired Status Type Register.
+	**/
+	mnStatusReg Value();
+
+	/**
+		\brief Set the <i>Status Register</i> type register with the new value.
+	
+		Update the internal register value within the Node with newValue.
+		This function should only be used when setting up Status masks for attentions.
+		
+		\see sFnd::IAttnNode::Mask
+		\see sFnd::IAttnNode::StatusMask
+
+		\CODE_SAMPLE_HDR
+		//Create a Status register mask to set the Attentionable Status Mask to.
+		//Here we are setting up attentions for Move done, A from start, and B from end
+		// Only the lower 32 bits are attentionable.
+		mnStatusReg mymask;
+		mymask.cpm.MoveDone = 1;
+		mymask.cpm.BFromEnd = 1;
+		mymask.cpm.AFromStart = 1;
+
+		//Set the Node's Attentionable Status Mask to our mask.
+		mynode.Adv.Attn.Mask.Value(mymask);
+
+		\endcode
+	**/
+	void Value(const mnStatusReg &newValue);
+
+	/**
+		\brief Return a copy of the last acquired value.
+
+		Return a copy of the last acquired value.
+
+		\return Copy of the last updated value.
+	**/
+	mnStatusReg Last();
+
+protected:
+												/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValueStatus(INode &node, nodeparam pNum, bool clearOnReadType);
+												/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueAlert class
+/**
+	\brief Alert Type Register Node Parameter Access Object.
+
+	This class object implements access to the alert register and the attentionable alert mask within the
+	node.
+
+	The motor's firmware and hardware contains many mechanisms to protect
+	the motor and the application from problems that may occur. When
+	an operation-blocking condition occurs, it is known as an <i>Alert</i>, or
+	sometimes called a <i>Shutdown</i>. The shutdown is logged in the
+	non-volatile memory with a time-stamp for review with the ClearView application.
+	These alerts are stored locally within the node in a ninety-six bit [alertReg](@ref alertReg) struct.
+	
+	The Attentionable alert mask is the mask which determines what alert bits will show in the User Alert field of the #mnStatusReg.
+
+	The following is an example
+
+	\see sFnd::IStatus::Alerts 
+	\see sFnd::IAttnNode::AlertMask
+	\see \ref AttentionsPage
+	\CODE_SAMPLE_HDR
+	
+	//This example code will check to see if a node has any current alerts and 
+	//print out the state string of any alerts found
+
+	//This creates an Empty String for us to put our Alert State String into
+	char alertList[256];
+
+	// get a reference to our ValueAlert Object
+	ValueAlert &myNodesAlert = myNode.Status.Alerts;
+
+	// Refresh the Real-Time Status, and Alert Register
+	theNode.Status.RT.Refresh();
+	myNodesAlert.Refresh();
+
+
+	// Check the Real-Time Status Register's "AlertPresent" bit
+	// The bit is set true if there are alerts in the alert register
+	if (theNode.Status.RT.Value().cpm.AlertPresent) 
+	{
+		printf("Node has alerts!\n");
+	}
+	else 
+	{
+		printf("Node has no alerts!\n");
+	}
+
+	// get an alertReg reference, and check directly for alerts
+	if (myNodesAlert.Value().isInAlert()) 
+	{
+		// Put a text description of all alert bits set into our empty string, then print the string
+		myNodesAlerts.Value().StateStr(alertList, 256);
+		printf("Node has alerts! Alerts: %s", alertList);
+
+	// Check for specific alerts by accessing the cpmAlertFlds within the alertReg Struct
+		if (myNodesAlert.Value().cpm.TrackingShutdown)
+		{
+			printf("Tracking Shutdown\n");
+		} 
+	}
+	
+	\endcode
+
+	\see _cpmAlertFlds for a complete list of Possible Alerts
+**/
+class MN_EXPORT ValueAlert : public ValueBase
+{
+												/** \cond INTERNAL_DOC **/
+	friend class IStatus;
+	friend class IAttnNode;
+private:
+	alertReg m_lastValue;
+	alertReg m_currentValue;
+	alertReg m_testResult;
+	bool m_clearOnRead;
+												/** \endcond **/
+public:
+	/**
+		\brief Query the node for a new copy of the underlying alert register.
+
+		This function will update the stored value to reflect current state 
+		of the node's Alert Register.
+	**/
+	void Refresh();
+													/** \cond INTERNAL_DOC **/
+	/**
+		\brief Read, Accumulate and Test and Clear Accumulated Alert Type 
+		Register state.
+
+		\param[in] mask Fields to test for
+		\param[out] result Fields that were cleared
+		\return true if one or more were true
+
+		This function is a thread safe way of atomically testing and clearing
+		fields from accumulating <i>Status Registers</i>. The /a result
+		union is updated with all the fields detected by the mask. This is useful
+		when testing multiple fields.
+		**/
+	bool TestAndClear(const alertReg &mask, alertReg &result);
+
+	/**
+		\brief Clear the accumulated state
+
+		This function is used to clear out the accumulated alert information from
+		the internal copy.
+	**/
+	void Clear();
+													/** \endcond  **/
+	/**
+		\brief Assignment operator to update value with #alertReg union value.
+
+		Assignment operator to update value with #alertReg union value.
+		This function should only be used when setting up the Attentionable Alert mask for attentions.
+
+		/see sFnd::IAttnNode::AlertMask
+
+		\CODE_SAMPLE_HDR
+		//Create a Alert register mask to set the Attentionable Alert Mask to.
+		//Here we are setting up attentions for a tracking error shutdown, a RMS Shutdown, 
+		// and a soft limit shutdown
+		alertReg mymask;
+		mymask.cpm.TrackingShutdown = 1;
+		mymask.cpm.RMSOverloadShutdown = 1;
+		mymask.cpm.SoftLimitsExceeded = 1;
+
+		//Set the Node's Attentionable Status Mask to our mask.
+		mynode.Adv.Attn.AlertMask = mymask;
+
+		\endcode
+	**/
+	alertReg &operator=(alertReg &newValue);
+
+	/**
+		\brief Copy operator to return a copy of the current alert type register.
+
+		Copy operator to return a copy of the current alert type register.
+	**/
+	operator alertReg();
+
+	/**
+		\brief Return a copy of the last acquired Alert Type Register.
+
+		Copy operator to return a copy of the current alert type register.
+	**/
+	alertReg Value();
+
+	/**
+		\brief Set the <i>Alert Register</i> type register with the new value.
+
+		\param[in] newValue The value to update.
+
+		Update the internal register value within the Node with newValue.
+		This function should only be used when setting up the Attentionable Alert mask for attentions.
+
+		/see sFnd::IAttnNode::AlertMask
+
+		\CODE_SAMPLE_HDR
+		//Create a Alert register mask to set the Attentionable Alert Mask to.
+		//Here we are setting up attentions for a tracking error shutdown, a RMS Shutdown,
+		// and a soft limit shutdown
+		alertReg mymask;
+		mymask.cpm.TrackingShutdown = 1;
+		mymask.cpm.RMSOverloadShutdown = 1;
+		mymask.cpm.SoftLimitsExceeded = 1;
+
+		//Set the Node's Attentionable Status Mask to our mask.
+		mynode.Adv.Attn.AlertMask = mymask;
+
+		\endcode
+	**/
+	void Value(const alertReg &newValue);
+
+	/**
+		\brief Return a copy of the prior acquired value.
+
+		Return a copy of the prior acquired value.
+	**/
+	alertReg Last() { return m_lastValue; }
+protected:
+												/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValueAlert(INode &node, nodeparam pNum, bool clearOnReadType);
+												/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValuePowerReg class
+/**
+\brief Power Status Register Node Parameter Access Object.
+
+This class object implements access to the power state register.
+
+The motor's firmware monitors the power connections continuously. This
+register shows the currently detected connections and any anomalies detected
+during operations. These include loose phase wiring and which terminals
+the power is attached to.
+
+The following is an example
+
+\todo see
+\CODE_SAMPLE_HDR
+
+//This example code will check and return the current power conditions and
+//print out the state string of any issues found.
+
+//This creates an Empty String for us to put our state string into
+char pwrInfo[256];
+
+// get a reference to our ValuePowerReg Object
+ValuePowerReg &myPower = myNode.Status.Power;
+
+// Refresh the Real-Time Status, and Alert Register
+theNode.Status.Power.Refresh();
+myPower.Refresh();
+
+
+// Check that there has been no disruptions in the AC supply.
+// The bit is set true if there are alerts in the alert register
+if (theNode.Status.Power.Value().fld.InBusLoss)
+{
+printf("Node's power bus has been removed!\n");
+}
+else
+{
+printf("Node has no bus supply problems!\n");
+}
+
+// Put a text description of all alert bits set into our empty string, then print the string
+myNodesAlerts.Value().StateStr(pwrInfo, 256);
+printf("Node power state: %s", pwrInfo);
+
+
+\endcode
+
+\see _mnPowerFlds for a complete list of Possible Alerts
+**/
+class MN_EXPORT ValuePowerReg : public ValueBase
+{
+	/** \cond INTERNAL_DOC **/
+	friend class IStatus;
+	friend class IAttnNode;
+private:
+	mnPowerReg m_lastValue;
+	mnPowerReg m_currentValue;
+	mnPowerReg m_testResult;
+	bool m_clearOnRead;
+	/** \endcond **/
+public:
+	/**
+	\brief Query the node for a new copy of the underlying alert register.
+
+	This function will update the stored value to reflect current state
+	of the node's Alert Register.
+	**/
+	void Refresh();
+	/** \cond INTERNAL_DOC **/
+	/**
+	\brief Read, Accumulate and Test and Clear Accumulated Power Type
+	Register state.
+
+	\param[in] mask Fields to test for
+	\param[out] result Fields that were cleared
+	\return true if one or more were true
+
+	This function is a thread safe way of atomically testing and clearing
+	fields from accumulating <i>Power Status Register</i>. The /a result
+	union is updated with all the fields detected by the mask. This is useful
+	when testing multiple fields.
+	**/
+	bool TestAndClear(const mnPowerReg &mask, mnPowerReg &result);
+
+	/**
+	\brief Clear the accumulated state
+
+	This function is used to clear out the accumulated status information from
+	the internal copy.
+	**/
+	void Clear();
+	/** \endcond  **/
+
+	/**
+	\brief Copy operator to return a copy of the current power type register.
+
+	Copy operator to return a copy of the current power type register.
+	**/
+	operator mnPowerReg();
+
+	/**
+	\brief Return a copy of the last acquired power Type Register.
+
+	Copy operator to return a copy of the current power type register.
+	**/
+	mnPowerReg Value();
+
+	/**
+	\brief Return a copy of the prior acquired value.
+
+	Return a copy of the prior acquired value.
+	**/
+	mnPowerReg Last() { return m_lastValue; }
+protected:
+	/** \cond INTERNAL_DOC **/
+	// Construction to wire to our node object
+	ValuePowerReg(INode &node, nodeparam pNum, bool clearOnReadType);
+	/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// ValueOutReg class
+/**
+	\cond SC_EXPERT
+	\brief Output Register Node Parameter Access Object.
+
+	This class object implements the access to a #mnOutReg type register.
+**/
+class MN_EXPORT ValueOutReg : public ValueBase
+{
+											
+	friend class IOuts;
+
+private:
+	mnOutReg m_lastValue;
+	mnOutReg m_currentValue;
+	mnOutReg m_testResult;
+	bool m_clearOnRead;
+	bool m_writeable;
+											
+public:
+	/**
+		\brief Query the node of a new copy of the underlying output register.
+
+		The update will atomically read and accumulate clear-on-read style registers
+		to prevent the loss of state information when accessed by multiple
+		threads. 
+	**/
+	void Refresh();
+	/**
+		\brief Clear fields from the output register state
+
+		Use this function to atomically update the output register from multiple
+		threads to avoid state corruption.
+	**/
+	void Clear(const mnOutReg &mask);
+	/**
+		\brief Set fields from the output register state
+
+		\param[in] mask Fields to set.
+
+		Use this function to atomically update the output register from multiple
+		threads to avoid state corruption.
+
+		\CODE_SAMPLE_HDR
+		mnOutReg bitsToSet;
+		bitsToSet.cpm.EnableReq = true;
+		bitsToSet.cpm.ResetTimer = true;
+		myNode.Outs.User.Set(bitsToSet);
+		\endcode
+	**/
+	void Set(const mnOutReg &mask);
+
+	/**
+		\brief Update the output register using an mnOutReg.
+
+		Update the output register using an mnOutReg.
+
+		\CODE_SAMPLE_HDR
+		const char *myParam = myNode.Info.UserID;
+		\endcode
+		**/
+	mnOutReg &operator=(mnOutReg &newValue);
+	/**
+		\brief Copy the current state of the <i>Output Register</i>
+		to another mnOutReg instance.
+
+		Copy the current state of the <i>Output Register</i>
+		to another mnOutReg instance.
+	**/
+	operator mnOutReg();
+	/**
+		\brief Copy the current state of the <i>Output Register</i> as a
+		bit-wide integer value.
+
+		Copy the current state of the <i>Output Register</i> as a
+		bit-wide integer value.
+	**/
+	operator double();
+	/** 
+		\brief Copy the current state of the <i>Output Register</i> as a
+		bit-wide integer value.
+
+		Copy the current state of the <i>Output Register</i> as a
+		bit-wide integer value.
+	**/
+	operator int32_t();
+	/**
+		\brief Copy the current state of the <i>Output Register</i> as a
+		bit-wide integer value.
+
+		Copy the current state of the <i>Output Register</i> as a
+		bit-wide integer value.
+	**/
+	operator uint32_t();
+
+	/**
+		\brief Update the <i>Output Register</i> to a new value from an 
+		mnOutReg union.
+	
+		\param[in] newValue Reference to a mnOutReg instance.
+
+		Update the <i>Output Register</i> to a new value from an
+		mnOutReg union.
+	**/ 
+	void Value(const mnOutReg &newValue);
+	
+	/**
+		\brief Return a copy of the current <i>Output Register</i> state.
+
+		Return a copy of the current <i>Output Register</i> state.
+	**/
+	mnOutReg Value();
+
+	/**
+		\brief Return a copy of the last updated <i>Output Register</i> state.
+
+		Return a copy of the last updated <i>Output Register</i> state.
+	**/
+	mnOutReg Last() { return m_lastValue; }
+
+protected:
+													
+	// Construction to wire to our node object
+	ValueOutReg(INode &node, nodeparam pNum,
+		bool clearOnReadType, bool writeable);
+													
+};
+							/**   \endcond **/
+//						  													  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueAppConfigReg class
+														/** \cond SC_EXPERT **/
+/**
+	\brief Application Configuration Parameter Object.
+
+	This class object implements the access to an mnAppConfigReg type register. 
+
+	\copydetails _mnAppConfigReg
+
+	\note Care should be taken accessing these registers as configuration file
+	loads may modify these settings.
+
+	\see _cpmAppConfigReg For details about the ClearPath-SC application
+	configuration.
+**/
+class MN_EXPORT ValueAppConfigReg : public ValueBase
+{
+													/**  INTERNAL_DOC **/
+	friend class ISetupEx;
+	friend class CPMmotionAdv;
+
+private:
+	mnAppConfigReg m_lastValue;
+	mnAppConfigReg m_currentValue;
+	mnAppConfigReg m_testResult;
+													/**  **/
+public:
+	/**
+		\brief Query the node of a new copy of the underlying <i>Application
+		Configuration</i> register.
+
+		Query the node of a new copy of the underlying <i>Application
+		Configuration</i> register.
+	**/
+	void Refresh();
+	/**
+		\brief Clear fields in this register in thread safe manner.
+
+		\param[in] mask Fields to clear out of the register
+
+		Clear fields in this register in thread safe manner.
+	**/
+	void Clear(const mnAppConfigReg &mask);
+	/**
+		\brief Set fields in this register in thread safe manner.
+
+		\param[in] mask Fields to set in the register
+
+		Set fields in this register in thread safe manner.
+	**/
+	void Set(const mnAppConfigReg &mask);
+
+	/**
+		\brief Copy an existing instance to our state via the 
+		assignment operator.
+
+		Copy an existing instance to our state via the
+		assignment operator.
+	**/
+	mnAppConfigReg &operator=(mnAppConfigReg &newValue);
+
+	/**
+		\brief Copy our instance to another instance.
+
+		Copy our instance to another instance.
+	**/
+	operator mnAppConfigReg();
+
+	/**
+		\brief Get our state as an integer represented in a double.
+
+		Get our state as an integer represented in a double.
+	**/
+	operator double();
+
+	/**
+		\brief Get our state as an integer.
+
+		Get our state as an integer.
+	**/
+	operator int32_t();
+
+	/**
+		\brief Get our state as an integer.
+
+		Get our state as an integer.
+	**/
+	operator uint32_t();
+
+	/**
+		\brief Update our internal state from another instance.
+
+		Update our internal state from another instance.
+	**/
+	void Value(const mnAppConfigReg &newValue);
+	/**
+		\brief Get a copy of our current state.
+
+		Get a copy of our current state.
+	**/
+	mnAppConfigReg Value();
+
+	/**
+		\brief Return the last prior state of this register.
+
+		Return the last prior state of this register.
+	**/
+	mnAppConfigReg Last() { return m_lastValue; }
+
+
+protected:
+													/**  INTERNAL_DOC **/
+	// Update the internal value to new state
+	void setNewVal(const mnAppConfigReg &newValue);
+	// Construction to wire to our node object
+	ValueAppConfigReg(INode &node, nodeparam pNum);
+													/**  **/
+};
+													/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ValueHwConfigReg class
+													/** \cond SC_EXPERT **/
+/**
+	\brief Hardware Configuration Parameter Object.
+
+	This class object implements the access to an mnHwConfigReg type register.
+
+	\copydetails _mnHwConfigReg
+
+	\note Care should be taken accessing these registers as configuration file
+	loads may modify these settings.
+
+	\see _cpmHwConfigReg For details about the ClearPath-SC hardware 
+	configuration register.
+**/
+class MN_EXPORT ValueHwConfigReg : public ValueBase
+{
+													/**  INTERNAL_DOC **/
+	friend class ISetupEx;
+
+private:
+	mnHwConfigReg m_lastValue;
+	mnHwConfigReg m_currentValue;
+	mnHwConfigReg m_testResult;
+													/**  **/
+public:
+	/**
+		\brief Query the node for a new copy of the underlying <i>Application
+		Configuration</i> register.
+
+		Query the node for a new copy of the underlying <i>Application
+		Configuration</i> register.
+	**/
+	void Refresh();
+
+	/**
+		\brief Clear fields in this register in thread safe manner.
+
+		\param[in] mask Fields to clear out of the register
+
+		Clear fields in this register in thread safe manner.
+	**/
+	void Clear(const mnHwConfigReg &mask);
+
+	/**
+		\brief Set fields in this register in thread safe manner.
+
+		\param[in] mask Fields to set in the register
+
+		Set fields in this register in thread safe manner.
+	**/
+	void Set(const mnHwConfigReg &mask);
+
+
+	/**
+		\brief Copy an existing instance to our state via the
+		assignment operator.
+
+		\param[in] newValue The incoming instance
+
+		Copy an existing instance to our state via the
+		assignment operator.
+	**/
+	mnHwConfigReg &operator=(mnHwConfigReg &newValue);
+
+	/**
+		\brief Copy our internal state to another instance.
+
+		Copy our internal state to another instance.
+	**/
+	operator mnHwConfigReg();
+
+	/**
+		\brief Get the numeric equivalent value of our register.
+
+		Get the numeric equivalent value of our register formatted as 
+		a double.
+	**/
+	operator double();
+
+
+	/**
+		\brief Get the numeric equivalent value of our register.
+
+		Get the numeric equivalent value of our register as integer.
+	**/
+	operator int32_t();
+
+	/**
+		\brief Get the numeric equivalent value of our register.
+
+		Get the numeric equivalent value of our register as an unsigned integer.
+	**/
+	operator uint32_t();
+
+	/**
+		\brief Get a copy of our current state.
+
+		Get a copy of our current state.
+	**/
+	mnHwConfigReg Value();
+
+	/**
+		\brief Set this register to a new value
+
+		\param[in] newValue New value to send to the node.
+
+		Set this register to a new value.
+	**/
+	void Value(const mnHwConfigReg &newValue);
+
+	/** 
+		\brief Get a copy of the previous value.
+
+		Get a copy of the previous value.
+	**/
+	mnHwConfigReg Last() { return m_lastValue; }
+
+protected:
+													/**  INTERNAL_DOC **/
+	/// Construction to wire to our node object
+	ValueHwConfigReg(INode &node, nodeparam pNume);
+													/**  **/
+};
+														/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IBrakeControl class
+/**
+	\brief Brake Control Feature Interface.
+	
+	This class implements access to the brake control outputs of a SC-Hub Board.  If multiple SC-Hub boards are chained together on a single port, 
+	only the first SC-Hub board's outputs will be controllable.
+
+	The Brake Control feature can be used to automatically control a brake whenever a node is disabled or shutdown, or they can be used as general purpose outputs.
+	This object also allows the application to override the brake to turn the brake off even when the node is disabled, allowing 
+	the axis to move freely.  This class provides functions to turn the outputs on and off, as well as to check the current state of the outputs.
+
+	Sometimes a brake can take time to engage so there is a Node Level [delay to disable](@ref sFnd::ISetup::DelayToDisableMsecs) parameter 
+	which can be set to give the brake time to activate before the motor disables.
+
+
+	\note When using #BRAKE_AUTOCONTROL mode, Brake_0 will activate and deactivate based on the state of the node connected to the CP0 connector on the SC-Hub Board.
+	Similarly, Brake_1 will correspond to CP1 on the SC-Hub Board.
+
+	\CODE_SAMPLE_HDR
+
+	// Configure the SC hub's Brake_0 to be in auto control mode (the brake will automatically activate, and deactivate based on the state of node 0)
+	myPort.BrakeControl.BrakeSetting(0,BRAKE_AUTOCONTROL);
+
+	//Determine if the current Brake Setting for the SC-Hub Board's Brake_0 is BRAKE_AUTOCONTROL
+	if(myPort.BrakeControl.BrakeSetting(0)==BRAKE_AUTOCONTROL)
+	{  In auto control}
+	else
+	{ Not in auto control (The brake could be overridden)}
+
+	//Determine if the Brake_0 output on the SC-Hub Board's is engaged
+	if(myPort.BrakeControl.BrakeEngaged(0))
+	{  Brake Engaged }
+	else
+	{  Brake Not Engaged}
+
+	// Turn on the SC hub's Brake_1 output as a general purpose Output.
+	myPort.BrakeControl.BrakeSetting(1,GPO_ON);
+	
+	\endcode
+
+	\see  #_BrakeControls for the complete list of brake modes
+
+**/
+class MN_EXPORT IBrakeControl : public IObjWithPort
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IPort;
+													/** \endcond **/
+public:
+	/**
+		\brief Setup how brake will function.
+
+		This function configures the configures the brake output.
+
+
+		\param[in] brakeNum Brake number to use [0..1] 0 corresponds to Brake_0 on a SC Hub, 1 corresponds to Brake_1.
+		\param[in] brakeMode Brake mode to use. 
+
+		\see  #_BrakeControls for the complete list of modes
+
+	**/
+	virtual void BrakeSetting(size_t brakeNum, BrakeControls brakeMode) = 0;
+	/**
+		\brief Get the brake control state.
+
+		Get the brake control state.
+
+		\param[in] brakeNum Brake number to use [0..1] 0 corresponds to Brake_0 on a SC Hub, 1 corresponds to Brake_1.
+		
+		\see  #_BrakeControls for the complete list of modes
+		
+	**/
+	virtual BrakeControls BrakeSetting(size_t brakeNum) = 0;
+
+	/**
+		\brief Return the current brake state.
+
+		Determine the curent state of the Brake.  A Brake is considered engaged when the brake is holding the axis.  This would correspond to zero current flow on a GPO.
+
+		
+		\param[in] brakeNum Brake number to use [0..1]; 0 corresponds to Brake_0 on a SC Hub, 1 corresponds to Brake_1.
+		\return true if the brake is engaged.
+
+	**/
+	virtual bool BrakeEngaged(size_t brakeNum) = 0;
+
+protected:
+	/** \cond INTERNAL_DOC **/
+	/* Construction */
+	IBrakeControl(IPort &port);
+public:
+	virtual ~IBrakeControl() {}
+	/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IGrpShutdown class
+/**
+	\brief Group Shutdown Feature Interface.
+
+	This class implements access to the group shutdown feature which
+	 allows an electrical connection or a change in a node's status to initiate a Group Shutdown Node Stop. 
+	 This Group Shutdown will automatically propagate and initiate a Node Stop on all nodes in the port.
+	 
+	This class can configure how each node on the port will react to a Group Shutdown Node Stop, as well as whether 
+	certain fields in the Node's mnStatusdReg will issue a group shutdown.  For instance, once a node goes [not ready](@ref cpmStatusRegFlds::NotReady)
+	, a group shutdown can be called.
+
+	Once a group shutdown is triggered the shutdown is sent to each node on the port. A group shutdown 
+	is also automatically triggered upon the loss of power (negative edge) of the global stop input on the SC-Hub board.
+
+	\CODE_SAMPLE_HDR
+
+	// The following lines of code show an example of how to create a Shutdown info object.
+	
+	// First we create the status mask object consisting of which status events on the node will trigger a group shutdown.
+	// In this case we are using "AlertPresent", "Disabled", and "Input A"
+
+	mnStatusReg myShutdownStatusMask;						//Create Status mask
+	myShutdownStatusMask.cpm.AlertPresent = 1;				//Set desired fields
+	myShutdownStatusMask.cpm.Disabled = 1;
+	myShutdownStatusMask.cpm.InA = 1;
+
+	// Next we create the ShutdownInfo object we will use to configure the Node with
+	ShutdownInfo myShutdownInfo;							//Create ShutdownInfo Object	
+	myShutdownInfo.enabled = true;							// This sets the node to respond to Group Shutdowns
+	myShutdownInfo.theStopType = STOP_TYPE_ABRUPT;			//Use an Abrupt Nodestop type for this node in response to a group shutdown
+	myShutdownInfo.statusMask = myShutdownStatusMask;		// Configure the node to issue a group shutdown automatically based on our status mask
+
+	//Finally we configure the Port's first Node (Node 0) with our shutdown object 
+	myport.GrpShutdown.ShutdownWhen(0,myShutdownInfo);
+
+	\endcode
+
+	\see \ref CPMnodeStopPage
+
+**/
+class MN_EXPORT IGrpShutdown : public IObjWithPort
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IPort;
+													/** \endcond **/
+public:
+	/**
+		\brief Setup the group shutdown for this node.
+
+		This function is used to setup how a node will react to a group shutdown, as well as
+		which items in the node's status register will trigger a group shutdown.  
+
+		\param[in] nodeIndex Node index. This corresponds to the location from
+		the host on the network.
+		\param[in] theInfo Settings to apply to this node.
+
+		\see _ShutdownInfo for information on how to specify the stoptype, status mask, and
+		whether the grpShutdown feature is enabled for this node
+
+	**/
+	virtual void ShutdownWhen(size_t nodeIndex, const ShutdownInfo &theInfo) = 0;
+	/**
+		\brief Get the group shutdown settings for this node.
+
+		Retrieve the current #_ShutdownInfo for this node, including the stop type, status mask, 
+		and whether the feature is enabled
+
+		\param[in] nodeIndex Node index. This corresponds to the location from
+		the host on the network.
+		\param[out] theInfo Settings to apply to this node.
+
+	**/
+	virtual void ShutdownWhenGet(size_t nodeIndex, ShutdownInfo &theInfo) = 0;
+	/**
+		\brief Initiate a group shutdown.
+
+		Trigger the Group Shutdown to occur via an API call.
+
+	**/
+	virtual void ShutdownInitiate() = 0;
+
+	/**
+	\brief Return the current global stop state.
+
+	Determine the current state of the Global Stop input.
+
+	\return true if the Global Stop is engaged.
+
+	**/
+	virtual bool GetGlobalStop() = 0;
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construct our group shutdown implementation
+	IGrpShutdown(IPort &port);
+public:
+	virtual ~IGrpShutdown() {}
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IPortAdv class
+/**
+	\brief Advanced Port Features Interface.
+
+	This implements the objects required to access any advanced features
+	at the port level.  Currently, this class provides a function to trigger groups of Nodes on this Port.
+**/
+class MN_EXPORT IPortAdv : public IObjWithPort
+{
+												/** \cond INTERNAL_DOC **/
+	friend class IPort;
+												/** \endcond **/
+public:
+												
+	/**
+		\brief Access the Attention Handling feature object
+
+		This object allows access to the advanced <i>Attention Request</i>
+		feature. This feature allows for non-polled asynchronous event
+		handling.
+	**/
+	IAttnPort &Attn;
+													
+	/**
+		\brief Trigger a group of nodes to initiate their moves.
+
+		\param[in] groupNumber Group to signal on the network attached to this
+		port.
+
+		If there are no waiting moves or nodes setup at this \a groupNumber,
+		this command will be ignored with no actions taken.
+
+		\see \ref CPMtriggerPage for more infomation on triggered moves
+		\see sFnd::IMotionAdv for configuring/loading triggered moves
+		\see sFnd::IMotionAdv::TriggerGroup to set/get a Node's trigger Group 
+
+		\CODE_SAMPLE_HDR
+		// This example will load some triggered moves onto a group of Nodes, then Trigger them at the Port Level
+
+		myNode1.Motion.Adv.MovePosnStart(1000,false,true);  /Load a 1000 cnt relative triggered move onto Node 1
+		myNode2.Motion.Adv.MovePosnStart(1000,false,true);  /Load a 1000 cnt relative triggered move onto Node 2
+		myNode3.Motion.Adv.MovePosnStart(1000,false,true);  /Load a 1000 cnt relative triggered move onto Node 3
+
+		//Set the Trigger group of Node's 1, 2, and 3
+		myNode1.Motion.Adv.TriggerGroup(1);
+		myNode2.Motion.Adv.TriggerGroup(1);
+		myNode3.Motion.Adv.TriggerGroup(2);
+
+		//Trigger the Loaded Moves
+		myPort.Adv.TriggerMovesInGroup(1);	//This will trigger Node 1 and 2 (Group 1)
+		myPort.Adv.TriggerMovesInGroup(2);	//This will only trigger Node 3 (Group 2)
+
+		\endcode
+
+	**/
+	virtual void TriggerMovesInGroup(size_t groupNumber) = 0;
+
+
+	bool Supported();
+													/** \cond INTERNAL_DOC **/
+	// Construction
+protected:
+	IPortAdv(IPort &ourPort, IAttnPort &attnPort);
+public:
+	virtual ~IPortAdv() {}
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																	      *
+// 	IPort class
+/**
+	\brief Serial Port Interface.
+
+	This class defines a "super" Port whose framework exposes the Port Level features
+	available for your application by a series of public attribute references.
+	There are common member functions for these feature objects to determine
+	if the node supports the feature.
+
+	This class also implements:
+	- References to Node object on the Port
+	- Functions to restart the Port, and determine if the Port is currently Open 
+	- A function to issue a Port wide Nodestop to every Node on this Port
+	- A function to record the command history of all communication on this Port
+
+	\CODE_SAMPLE_HDR
+	// Create instance of sFoundation
+	SysManager myMgr;
+	// Define a port SC4-HUB attached to
+	myMgr.ComHubPort(0, 13);
+	// Tell system to open this one port
+	myMgr.PortsOpen(1);
+	// Create useful reference to the first port object
+	IPort &myPort = myMgr.Ports(0);
+	// Test for presence of nodes
+	if (myPort.NodeCount() == 0) {
+	// Bail out, no nodes
+		return;
+	}
+	\endcode
+
+	\see sFnd::SysManager For the root object for interacting with
+	ClearPath-SC motors.
+	\see sFnd::SysManager::Ports To get references to the IPort objects created
+	when SysManager::PortsOpen has successfully opened.
+	**/
+class MN_EXPORT IPort
+{
+													/** \cond INTERNAL_DOC **/
+	friend class CPMportAdv;
+public:
+protected:
+	/// Port index number, zero based.
+	netaddr m_netNumber;
+public:
+													/** \endcond **/
+
+public:
+	/**
+		\brief Return a reference to the indexed node on this port
+
+		\param[in] index Get a reference for the node. This is the zero based
+		index, meaning zero is the first node. The first node is the node
+		closest to the host serial port in the ring.
+	**/
+	INode &Nodes(size_t index);
+
+	/**
+		\brief Return the count of nodes active on this port
+
+		\return Return the count of nodes present on this port.
+
+		Use this function to find out how many active nodes are attached to
+		this port. If the port if offline, this will be zero.
+
+		\CODE_SAMPLE_HDR
+		// Check to see if there are nodes on the Port.
+		if (myPort.NodeCount() == 0) {
+		// Bail out, no nodes
+		return;
+		}
+		\endcode
+	**/
+	virtual Uint16 NodeCount() = 0;
+
+	/**
+		\brief Restart this nodes to its powered on state and re-connect
+
+		This causes the nodes on this port to restart and re-establish 
+		contact with the detected node configuration.
+	**/
+	virtual void RestartCold() = 0;
+
+	/**
+		\brief Get port state
+
+		\return Current port operational state.
+
+		Use this function to ascertain the operation state of this port.
+
+		\note Ports operate independently from each other. In other words, a
+		failure on connections on one port should not affect another port.
+	**/
+	virtual openStates OpenState() = 0;
+
+	/**
+		\brief Wait for the port to go online
+
+		\param[in] timeoutMsec Time to wait for port to return or go online
+
+		\return True if the port came back online.
+
+		This function is useful after restarting the network after power is lost.
+	**/
+	virtual bool WaitForOnline(int32_t timeoutMsec = 15000) = 0;
+
+	/**
+		\brief Create command trace file.
+
+		This function creates a file which contains a detailed transaction log 
+		of the all the commands	send and data received by the host. It will 
+		remember the last 4096 commands and/or responses.
+
+		Teknic support staff may ask for the file created via this function
+		to determine where a programming error occurred.
+	**/
+	virtual void CommandTraceSave(const char *filePath) = 0;
+
+	/**
+		\brief Send a high-priority <i>Node Stop</i> command to all the nodes
+		attached to this serial port. If stopType is
+		STOP_TYPE_IGNORE, the nodes will use their default stop type instead 
+		of the specific type. 
+
+		\param [in] stopType Will force this stop type to all nodes on this port.
+
+		This is a fast acting command that can be used to stop all motion on a
+		port. If a modifier field is set, such as E-Stop, all motion will be 
+		blocked until this condition is cleared.
+
+		\see #sFnd::IMotion::NodeStop For initiating node stops at a single node.
+
+		\CODE_SAMPLE_HDR
+
+		myport.NodeStop(STOP_TYPE_ABRUPT);				//This issues an abrupt nodestop on all the nodes on this port
+		myport.NodeStop(STOP_TYPE_RAMP_WITH_DECEL);		//This issues a nodestop to ramp to zero velocity using the current decel parameter's on all the nodes on this port
+
+		\endcode
+	**/
+	virtual void NodeStop(mgNodeStopReg stopType = STOP_TYPE_IGNORE) = 0;
+
+	/**
+		\brief Group Shutdown Feature
+
+	**/
+	IGrpShutdown &GrpShutdown;
+
+	/**
+		\brief Brake Control Feature of SC-Hub
+	**/
+	IBrakeControl &BrakeControl;
+
+	/**
+		\brief Access to advanced features for the port.
+	**/
+	IPortAdv &Adv;
+
+													/**	\cond INTERNAL_DOC	**/
+	netaddr NetNumber() { return m_netNumber; }
+	void NetNumber(netaddr index) { m_netNumber = index; }
+													/** \endcond **/
+
+public:
+													/** \cond INTERNAL_DOC **/
+	// Construction
+	IPort(netaddr index, IBrakeControl &brake, IGrpShutdown &shtDwn,
+		IPortAdv &advPort);
+	virtual ~IPort();
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IMotionAudit class
+																/** \cond SC_EXPERT **/
+/**
+	\brief Motion Audit Feature Interface
+
+	This class object implements access to the motion audit feature. This
+	feature is used to watch a reference move and determine if the axis
+	has problems that may require service. 
+
+	\note This is only available with Advanced feature set.
+**/
+class MN_EXPORT IMotionAudit : public IObjWithNode
+{
+private:
+public:
+	/**
+		\brief Audit Monitoring Testpoints
+	**/
+	enum _testPoints {
+		/**
+		Watch Positional tracking errors.
+		**/
+		MON_POS_TRK = 6,
+		/**
+		Watch measured torque.
+		**/
+		MON_TRQ_MEAS = 7,
+		/**
+		Watch commanded torque.
+		**/
+		MON_TRQ_CMD = 8
+	};
+	/**
+		\brief Result from last Refresh.
+
+		After calling the \a Refresh function, the results are stored here.
+
+		\note This feature is only available on Advanced nodes.
+	**/
+	mnAuditData Results;
+
+	/**
+		\brief Update the results.
+
+		Calling this member function will retrieve the last collected audit
+		information updating by calling IMotionAutit::Results function..
+
+		\note This feature is only available on Advanced nodes.
+	**/
+	virtual void Refresh() = 0;
+
+	/**
+		\brief Setup monitoring test point
+
+		\param[in] testPoint The node test point to monitor and collect
+		statistics on.
+		\param[in] fullScale The gain to apply for the selected channel. This
+		should be carefully selected to match the expected values. If set too
+		small, the values could be clipped in amplitude and if too large,
+		quantization effects could affect the RMS and high frequency results.
+		\param[in] filterTCmsec Low-pass filtering time constant specified
+		in milliseconds.
+
+		This function sets up the monitoring system test point. This test
+		point collects high pass, low pass, maximum positive value, maximum
+		negative value and RMS values during the collection interval.
+	**/
+	virtual void SelectTestPoint(enum _testPoints testPoint,
+		double fullScale, double filterTCmsec) = 0;
+
+	// Construction
+	/** cond INTERNAL_DOC **/
+protected:
+	IMotionAudit(INode &ourNode);
+public:
+	virtual ~IMotionAudit() {}
+	/** endcond **/
+};
+														/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IAttnNode class
+/**
+	\brief <i>Node Attention</i> Feature Interface.
+
+	<i>Node Attention</i> Feature Interface.
+
+	A reference to this object allows your application to control which node
+	status events will generate a <i>Network Attention</i> packet. These packets
+	efficiently signal the host some noteworthy event, such as move done, has
+	occurred. Using Attentions eliminates the overhead and latency involved with
+	polling.
+
+	\note This feature is only available on nodes that have the Advanced
+	feature set.
+
+	\see \ref AttentionsPage
+	\see cpmStatusRegFlds for a complete list of Node status events
+
+	
+**/
+class MN_EXPORT IAttnNode : public IObjWithNode
+{
+													/** \cond INTERNAL_DOC **/
+	friend class INodeAdv;
+	friend class INode;
+													/** \endcond **/
+protected:
+public:
+	/**
+		\brief Attention Enabling Mask
+
+		Setup which fields of the <i>Status Attn/Rise Register</i> cause the
+		generation of an <i>Attention Packet</i> to the host. These packets are
+		similar to a microprocessor interrupt.
+
+		\see _cpmStatusRegFlds		For details about ClearPath-SC specific status
+		\see _mnStatusReg		For details about the <i>Universal Status Register</i>
+
+		\note This is an advanced feature.
+	**/
+	ValueStatus Mask;
+												/** \cond INTERNAL_DOC **/
+	/**
+		\brief Warnings to indicate in the <i>Status Register</i>
+
+		Setup which fields of the <i>Warning Register</i> will set the
+		cpmStatusRegFlds::Warning field in the <i>Status Register</i>.
+
+		This can be used to send attentions on drive events such as torque
+		saturations.
+
+		\see _cpmStatusRegFlds		For details about ClearPath-SC specific status
+		\see _mnStatusReg		For details about the <i>Universal Status Register</i>
+	**/
+	ValueAlert WarnMask;
+												/** \endcond  **/
+
+	/**
+		\brief Selection of Alerts to include in the <i>Status Register</i>
+		User Alert field.
+
+		Setup which fields of the <i>Alert Register</i> will set the
+		cpmStatusRegFlds::UserAlert field in the <i>Status Register</i>.
+
+		\see _cpmStatusReg		For details about ClearPath-SC specific status
+		\see _mnStatusReg		For details about the <i>Universal Status Register</i>
+	**/
+	ValueAlert AlertMask;
+
+	/**
+		\brief Selection of Status Events to include in the <i>Status Register</i> Status Event field.
+
+		Setup which fields of the <i>Status Register</i> will set the
+		cpmStatusRegFlds::StatusEvent field in the <i>Status Register</i>.
+
+		\note Do not include the \e StatusEvent field in this mask to avoid
+		latching this field in the status register.
+
+		\see _cpmStatusRegFlds		For details about ClearPath-SC specific status
+		\see _mnStatusReg		For details about the <i>Universal Status Register</i>
+	**/
+	ValueStatus StatusMask;
+
+	/**
+		\brief Wait for any of the indicated attention fields to assert.
+
+		\param[in] theAttn The set of attentions to wait on. \note Only the lower
+		32-bits of the status register generate attentions.
+		\param[in] timeoutMsec The maximum time to wait for these attentions.
+		\param[in] autoClear If set, the bits underlying last attention register
+		cooresponding to theAttn will be atomically cleared.
+		\return A copy of the attentions that released this function. If the
+		fields of this register is zero, the timeout occurred.
+
+		When called, this function blocks until the desired attention occurs.
+		The returned mnStatusReg is set with the fields of the last
+		matching attention. This is helpful when waiting on multiple attentions
+		to find out the actual attention signaled. The \a timeoutMS parameter
+		allows you limit the amount of waiting time until the return. This is
+		typically required to prevent your application from hanging up when
+		something fails to deliver the expected event(s).
+
+		\CODE_SAMPLE_HDR
+		//Enable attentions on the Port (typically this would be enabled once ate the beginning of the application)
+		myPort.Adv.Attn.Enable(true);
+
+		// Wait for node to be ready to take commands
+		attnReg attnReq;
+		attnReq.cpm.Ready = 1;
+		mynode.Adv.Attn.ClearAttn(attnReq);
+
+		mynode.EnableReq(true);
+
+		// If the node is not currently ready, wait for it to get there
+		mynode.Status.RT.Refresh();
+		if (!mynode.Status.RT.Value().cpm.Ready){
+		attnReg theAttn = mynode.Adv.Attn.WaitForAttn(attnReq, 3000);
+		if (!theAttn.cpm.Ready){
+		mnErr eInfo;
+		eInfo.ErrorCode = MN_ERR_TIMEOUT;
+		eInfo.TheAddr = mynode.Info.Ex.Addr;
+		snprintf(eInfo.ErrorMsg, sizeof(eInfo.ErrorMsg),
+		"Error: Timed out waiting for enable\n");
+		throw eInfo;
+		}
+		}
+		\endcode
+	**/
+	mnStatusReg WaitForAttn(mnStatusReg theAttn, int32_t timeoutMsec,
+						 bool autoClear = true);
+	/**
+		\brief Clear the indicated fields from the current attention state.
+
+		\param[in] attnClr Set fields you wish to clear from the accumulating
+		attentions.
+
+		This member function is used to clear unwanted past Attentions that
+		have been received by the host.
+	**/
+	void ClearAttn(mnStatusReg attnClr);
+
+													/** \cond INTERNAL_DOC **/
+	/**
+		\brief Signal that an <i>Attention Packet</i> has arrived with the
+		indicated attn fields set.
+
+		\param[in] theAttn Detected attention information
+	**/
+	void SignalAttn(mnStatusReg theAttn);
+	// Construction
+protected:
+	// Attention handling implementation.
+	/**
+		\brief Register that this thread will be looking for an attention.
+	**/
+	virtual void AttnRegister() = 0;
+	/**
+		\brief Unregister that this thread will no longer be looking for an 
+		attention.
+	**/
+	virtual void AttnUnregister() = 0;
+	/**
+		\brief Wait for an attention to occur
+
+		\param[in] timeoutMsec The maximum time to wait for an attention.
+		\return True if the event has signaled before the timeout.
+
+		\brief This member function wait up to \timeoutMsec for the attention to
+		occur.
+	**/
+	virtual bool AttnWait(size_t timeoutMsec) = 0;
+	/**
+		\brief Signal that an attention occurred.
+	**/
+	virtual void AttnSignal() = 0;
+
+	/**
+		\brief Current attention state.
+	**/
+	mnStatusReg m_attn;
+
+	IAttnNode(INode &ourNode,
+		nodeparam attnMaskPnum, nodeparam usrWarnMaskPnum,
+		nodeparam usrAlertMaskPnum, nodeparam usrStatMaskPnum);
+															/** \endcond **/
+public:
+	virtual ~IAttnNode() {};
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IAttnPort class
+													
+/**
+	\brief Serial Port Attention Feature Interface.
+
+	This implements the feature object required to setup attentions and register 
+	an Attention handler callback function on this port.
+
+	\see AttentionsPage
+
+**/
+class MN_EXPORT IAttnPort : public IObjWithPort
+{
+													/** \cond INTERNAL_DOC **/
+	friend class SysCPMattnPort;
+private:
+	bool AttnsEnabled;
+	mnAttnCallback AttnCallback;
+													/** \endcond **/
+public:
+													/** \cond SC_EXPERT **/
+	/**
+		\brief Return codes for IAttnPort::WaitForAttn.
+
+		Use these return codes to interpret how the IAttnPort::WaitForAttn
+		succeeded. Usually your application would perform some action
+		when HAS_ATTN is returned.
+	**/
+	typedef enum _attnState {
+		/**
+		An attention was received.
+		**/
+		HAS_ATTN,
+		/**
+		No attentions have been received for a while.
+		**/
+		TIMEOUT,
+		/**
+		The attentions are disabled.
+		**/
+		DISABLED,
+		/**
+		The system is shutting down and no more attentions are going
+		to be posted.
+		**/
+		TERMINATING
+	} attnState;
+													/** \endcond  **/
+	/**
+		\brief Control the posting of attentions 
+
+		\param[in] newState If set, sFoundation will process received
+		<i>Attention Requests</i>.
+
+		\note This does not turn off the generation of attentions by the node.
+		Turn off Attention generation by clearing the sFnd::IAttnNode::Mask for
+		each node on the Port.  If attention posting is disabled, but attentions
+		are still generated, an error will be generated.
+	**/
+	virtual void Enable(bool newState) = 0;
+
+	/**
+		\brief Return the global attention posting switch
+
+		\return True if attentions can be posted.
+
+	**/
+	virtual bool Enabled() = 0;
+													/** \cond SC_EXPERT **/
+	/**
+		\brief Wait for an attention to arrive. 
+	
+		This function will periodically
+		return TIMEOUT to allow the application to terminate when no attentions
+		have been detected.
+
+		\param[out] attnRecvd If the function returns IAttnPort::HAS_ATTN, this
+		buffer will be filled in with detected event.
+		\return attnState To determine processing of the attn buffer.
+	**/
+	virtual attnState WaitForAttn(mnAttnReqReg &attnRecvd) = 0;
+													/** \endcond  **/
+	/**
+		\brief Detect if handler is defined.
+
+		\return true if a handler is installed.
+
+		Use the IAttnPort::AttnHandler function to register a handler callback
+		function.
+	**/
+	bool HasAttnHandler();
+
+	/**
+		\brief Register an attention callback function.
+
+		Register an attention callback function.
+
+		\param[in] theNewHandler The address of a handler function of type
+		mnAttnCallback;
+
+		\note To prevent system performance issues, the implemented callback
+		function should not run for extended periods of time. The function is
+		also restricted from running any network based command. This includes
+		parameter accesses and node commands. This function should signal other threads to
+		restart themselves or other lightweight signaling mechanisms.
+
+		\CODE_SAMPLE_HDR
+		// Example showing a Attention Handler function
+		// Enable the attentions for this port
+		myPort.Adv.Attn.Enable(true);
+		// The attentions will be handled by the individual nodes, but register
+		// a handler at the port level, just for illustrative purposes.
+		myPort.Adv.Attn.AttnHandler(AttentionDetected);
+
+		void MN_DECL AttentionDetected(const mnAttnReqReg &detected)
+		{
+		// Make a local, non-const copy for printing purposes
+		mnAttnReqReg myAttns = detected;
+		// Create a buffer to hold the attentionReg information
+		char attnStringBuf[512];
+		// Load the buffer with the string representation of the attention information
+		myAttns.AttentionReg.StateStr(attnStringBuf, 512);
+		// Print it out to the console
+		printf("  --> ATTENTION: port %d, node=%d, attn=%s\n",
+		detected.MultiAddr >> 4, detected.MultiAddr, attnStringBuf);
+		}
+		\endcode
+	**/
+	void AttnHandler(mnAttnCallback theNewHandler);
+													/** \cond INTERNAL_DOC **/
+	/**
+		\brief Invoke the attention handler if defined.
+
+		\param[in]  detected attention
+
+		This is an internal function and should not be used.
+	**/
+	void InvokeAttnHandler(const mnAttnReqReg &detected);
+
+	// Construction
+protected:
+	IAttnPort(IPort &ourPort);
+	virtual ~IAttnPort();
+													/** \endcond **/
+};
+													
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ILimitsAdv Class
+													/** \cond SC_EXPERT **/
+/**
+	\brief Advanced Limit Feature Interface.
+
+	This class object implements the settings for directional torque limiting.
+**/
+class MN_EXPORT ILimitsAdv : public IObjWithNode
+{
+													/** cond INTERNAL_DOC **/
+	friend class CPMnode;
+													/** endcond **/
+public:
+	/**
+		\brief Access the node's positive torque limit object.
+
+		Access the node's positive torque limit parameter object using the current torque 
+		units. This parameter determines the positive torque limit used when positive torque limiting 
+		is started.
+
+		\see sFnd::INode::TrqUnit To determine the unit
+		\see sFnd::INode::TrqUnit(_trqUnits) To change the unit
+		\see sFnd::ValueDouble for manipulation examples
+	**/
+	ValueDouble PositiveTrq;
+
+	/**
+		\brief Access the node's positive torque limit time constant. 
+	
+		Access the node's positive torque limit time constant parameter object. The value is
+		specified in milliseconds.  This parameter controls how quickly the torque limit is changed
+		after positive torque limiting has started.  A longer time constant will produce a smoother 
+		change in torque, a shorter time constant will produce a more sudden change.
+
+		\see sFnd::ValueDouble for manipulation examples
+	**/
+	ValueDouble PositiveRelaxTCmsec;
+
+	/**
+		\brief Access the node's negative torque limit.
+
+		Access the node's negative torque limit parameter object in the current torque units.  
+		This parameter determines the negative torque limit used when negative torque limiting 
+		is started.
+
+		\see sFnd::INode::TrqUnit To determine the unit
+		\see sFnd::INode::TrqUnit(_trqUnits) To change the unit
+		\see sFnd::ValueDouble for manipulation examples
+	**/
+	ValueDouble NegativeTrq;
+
+	/**
+		\brief Access the node's negative torque limit time constant. 
+		
+		Access the node's negative torque limit time constant parameter object. The value is
+		specified in milliseconds.  This parameter controls how quickly the torque limit is changed
+		after negative torque limiting has started.  A longer time constant will produce a smoother 
+		change in torque, a shorter time constant will produce a more sudden change.
+
+		\see sFnd::ValueDouble for manipulation examples
+	**/
+	ValueDouble NegativeRelaxTCmsec;
+
+	/**
+		\brief Control the positive torque limit feature.
+
+		Control user initiate the positive torque limit feature when 
+		\a engage is true.  If \a engage is false positive torque limiting is
+		turned off.
+	
+		\note If the node has been configured through Clearview to start limiting positive torque based off
+		and input, or move done, etc. this request is ignored but remembered as the user's selection.
+	**/
+	virtual void StartPosFoldback(bool engage) = 0;
+
+	/**
+		\brief Get current state of the positive torque limit.
+
+		Return the status of the user initiated positive torque limiting.  True indicates the positive 
+		torque limit is active.  False indicates the positive torque limit is inactive. 
+
+		\note  If the node has been configured through Clearview to start limiting positive torque based off
+		and input, or move done, etc. this request returns the user's requested state, not the actual state.
+	**/
+	virtual bool StartPosFoldback() = 0;
+
+	/**
+		\brief Control the negative torque limit feature.
+
+		Control user initiate the negative torque limit feature when
+		\a engage is true.
+
+		\note If the node has been configured through Clearview to start limiting negative torque based off
+		and input, or move done, etc. this request is ignored but remembered as the user's selection.
+	**/
+	virtual void StartNegFoldback(bool engage) = 0;
+
+	/**
+		\brief Get current state of the negative torque limit.
+
+		Return the status of the user initiated negative torque limiting.  True indicates the negative 
+		torque limit is active.  False indicates the negative torque limit is inactive. 
+
+		\note If the node has been configured through Clearview to start limiting negative torque based off
+		and input, or move done, etc. this request returns the user's requested state, not the actual state.
+	**/
+	virtual bool StartNegFoldback() = 0;
+
+protected:
+													/** cond INTERNAL_DOC **/
+	// Construction 
+	ILimitsAdv(INode &ourNode,
+		nodeparam posFldkPnum, nodeparam posFldkTCpNum,
+		nodeparam negFldkPnum, nodeparam negFldkTCpNum);
+public:
+	virtual ~ILimitsAdv() {}
+													/** endcond **/
+};
+													/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	INodeAdv class
+/**
+	\brief Advanced Node Features Interface.
+
+	This implements the objects required to access any advanced features
+	of a node.
+
+	Provides access to the following advanced features:
+	- Attention Generation
+**/
+class MN_EXPORT INodeAdv : public IObjWithNode
+{
+public:
+	/**
+		\brief Attention Generation Feature Setup.
+
+		Access the node's <i>Attention Generation</i> feature.
+
+	**/
+	IAttnNode &Attn;
+											/** \cond SC_EXPERT **/
+	/**
+		\brief Motion Audit Feature Access
+
+		This feature can be used to monitor an axis' operational 
+		characteristics and monitor for changes.
+	**/
+	IMotionAudit &MotionAudit;
+											/** \endcond  **/
+													/** \cond INTERNAL_DOC **/
+	// Construction
+protected:
+	INodeAdv(INode &ourNode, IMotionAudit &audit, IAttnNode &attnNode);
+	virtual ~INodeAdv() {};
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	INodeEx class
+/** \cond SC_EXPERT **/
+/**
+	\brief Expert Node Features Interface.
+
+	This implements the objects required to access any expert features
+	of a node.
+**/
+class MN_EXPORT INodeEx : public IObjWithNode
+{
+													/** cond INTERNAL_DOC **/
+	friend class INode;
+													/** endcond **/
+													/** cond INTERNAL_DOC **/
+protected:
+	// Read-modify-write parameter mutex access via INode implementations
+	// using the INode::UseMutex class.
+	/**
+		\brief Initiate an update lock access to registers
+
+		If directly modifying a register for read-modify-write, you should
+		take this lock before performing read-modify-write operations. This
+		prevents value corruption by other threads trying to perform similar
+		operations.
+	**/
+	virtual void MutexTake() = 0;
+	/**
+		\brief Release the update access lock for read-modify-write
+		operation
+
+		After completing a read-modify-write operation you need to release
+		the lock to allow other threads to have access.
+
+		\note Failure to release the mutex will lead to system dead-lock. Insure
+		all error paths release this lock as well.
+	**/
+	virtual void MutexRelease() = 0;
+	// Construction
+													/** endcond **/
+protected:
+													/** cond INTERNAL_DOC **/
+	INodeEx(INode &ourNode);
+public:
+	virtual ~INodeEx() {}
+													/** endcond **/
+};		
+/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IHoming class
+/**
+	\brief Homing Feature Interface.
+
+	This class object implements access to Teknic's homing engine.  This object allows
+	a user to initiate homing and test whether homing was complete. This object
+	cannot configure homing parameters such as homing direction/speed.  Homing parameters
+	must be set using the ClearView software, and this object only provides the ability
+	to start homing and check whether the axis has homed.
+
+	Homing is required to use soft limits and
+	establish the node's number space for absolute type moves.
+**/
+class MN_EXPORT IHoming : public IObjWithNode
+{
+													/** \cond INTERNAL_DOC **/
+	friend class INode;
+													/** \endcond **/
+
+public:
+	/**
+		\brief Initiate the homing sequence.
+
+		This function is called to initiate a homing sequence. ClearView
+		should be used to setup how homing is performed. 
+
+		\CODE_SAMPLE_HDR
+		// Initiate Homing
+		mynode.Motion.Homing.Initiate();
+		\endcode
+	**/
+	virtual void Initiate() = 0;
+
+	/**
+		\brief Update status real-time and return the state of the homing active
+		flag.
+
+		Update [status real-time register](@ref sFnd::IStatus::RT) and return the state of the homing active
+		flag.
+
+		\return True if homing is occurring.
+
+		\CODE_SAMPLE_HDR
+		// Check to see if the Node is still homing
+		if(mynode.Motion.Homing.IsHoming())
+		{ StillHoming }
+		else
+		{ No Longer Homing  }
+
+		\endcode
+
+	**/
+	virtual bool IsHoming() = 0;
+
+	/**
+		\brief Update status real-time and return the state of the homing 
+		complete flag.
+
+		Update [status real-time register](@ref sFnd::IStatus::RT) and return the state of the homing
+		complete flag.  Homing complete will only assert after a successful homing sequence
+		or if the user calls the SignalComplete() function indicating a successful manual homing.
+
+		\return True if homing has completed.
+
+		\CODE_SAMPLE_HDR
+		// Check to see if the Node is still homing
+		if(mynode.Motion.Homing.WasHomed())
+		{ Homed Successfully }
+		else
+		{ Not Successfuly Homed  }
+
+		\endcode
+	**/
+	virtual bool WasHomed() = 0;
+
+	/**
+		\brief Signal the completion of manual homing.
+
+		This function is used to signal to the node that the homing sequence
+		has completed. Typically the homing process automatically 
+		proceeds until completion. If a hard-stop or input cannot
+		be used to terminate the homing sequence, this function can be
+		used to signal the completion of a homing sequence.
+
+		Calling this function will cause soft limits to activate.
+
+		\note This function is used when the  automatic homing
+		feature cannot be used to establish the absolute number space. For
+		example when camera processing is used to establish a position.
+
+		\see IHoming::SignalInvalid To disable soft limits and allow another
+		homing sequence to occur.
+		\see IMotion::AddToPosition to manually adjust the number space during manual homing
+
+		\CODE_SAMPLE_HDR
+
+		// Manually zero position, and declare the number space valid
+		mynode.Motion.AddToPosition(-mynode.Motion.MeasPosition);
+		mynode.Motion.Homing.SignalComplete();
+
+		\endcode
+
+	**/
+	virtual void SignalComplete() = 0;
+
+	/**
+		\brief Signal the node that our absolute position space is invalid. 
+		
+		Signal the node that our absolute position space is invalid.
+
+		This is	useful when using soft limits and manual homing procedure.
+
+		\note After calling this function the soft limit feature, if enabled,
+		is disabled.
+
+		\see IHoming::SignalComplete to reverse the affects of this function.
+
+		\see IMotion::AddToPosition to manually adjust the number space during manual homing
+	**/
+	virtual void SignalInvalid() = 0;
+
+	/**
+		\brief Check Homing settings to see if they are set-up properly
+
+		\return True if homing has been set-up
+	**/
+	virtual bool HomingValid() = 0;
+
+protected:
+	// Construction
+													/** \cond INTERNAL_DOC **/
+	IHoming(INode &ourNode, nodeparam accPnum, nodeparam velLimPnum,
+		nodeparam clampPnum, nodeparam offsPnum, nodeparam postMvDlyPnum);
+public:
+	virtual ~IHoming() {}
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IInfoAdv class
+
+													/** \cond SC_EXPERT **/
+/**
+	\brief Advanced Information Features Interface.
+
+	This class object implements access to the advanced node information.
+
+	There is currently no advanced information available.
+**/
+class MN_EXPORT IInfoAdv : public IObjWithNode
+{
+private:
+public:
+protected:
+													/** cond INTERNAL_DOC **/
+	// Constructor
+	IInfoAdv(INode &ourNode);
+													/** endcond **/
+};
+													/** \endcond  **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IInfoEx class
+													
+/**
+	\brief Expert Information Interface.
+
+	This class object implements access to expert node information.
+**/
+class MN_EXPORT IInfoEx : public IObjWithNode
+{
+													/** \cond INTERNAL_DOC **/
+private:
+	multiaddr m_addr;
+protected:
+	void Addr(multiaddr assignAddr);
+													/** \endcond **/
+public:
+	/**
+		\brief Get our internal network address.
+
+		\return The network address for this node.
+
+		This information allows the retrieval of the internal network address.
+	**/
+	multiaddr Addr();
+
+	/**
+		\brief Get this node's network location
+
+		\return The node index for this port.
+
+		This is the zero based index of the location of the node. The first
+		node from the host starts the count.
+	**/
+	nodeaddr NodeIndex();
+
+	/**
+		\brief Get a numeric parameter's current value
+
+		\param[in] index The parameter number for a numeric parameter.
+		\return Numeric value. The scaling and units depend on the requested
+		parameter.
+
+		\note This function should only be used under direction of Teknic support
+		staff.
+	**/
+
+	virtual double Parameter(nodeparam index) = 0;
+	/**
+		\brief Set a numeric parameter's new value
+
+		\param[in] index The parameter number for a numeric parameter.
+		\param[in] newValue The new value to write into this parameter.
+
+		\note This function should only be used under direction of support
+		staff.
+	**/
+	virtual void Parameter(nodeparam index, double newValue) = 0;
+													/** \cond INTERNAL_DOC **/
+protected:
+	IInfoEx(INode &ourNode);
+public:
+	virtual ~IInfoEx() {}
+													/** \endcond **/
+};
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IInfo class
+/**
+	\brief Node Information Interface.
+
+	This class object implements access to node information.
+
+	This includes node management items such as:
+	- Serial Number
+	- Node Type
+	- Firmware Version
+	- User ID management
+	- Configuration file loading and saving
+**/
+class MN_EXPORT IInfo : public IObjWithNode
+{
+private:
+public:
+	/// This enumeration describes the type of node this object represents.
+	typedef enum _nodeTypes {
+		/// The type cannot be determined
+		UNKNOWN,
+								/** \cond SC_EXPERT **/
+		/// The node is a Meridian ISC
+		MERIDIAN_ISC,
+								/** \endcond  **/
+		/// The node is a ClearPath-SC
+		CLEARPATH_SC,
+		/// The node is an Advanced ClearPath-SC
+		CLEARPATH_SC_ADV
+	} nodeTypes;
+
+	/**
+		\brief Get serial number of this node.
+
+		Access the node serial number via the Value function.
+
+		\CODE_SAMPLE_HDR
+		printf( "SN=%u\n", uint32_t(myNode.Info.SerialNumber));
+		\endcode
+	**/
+	ValueUnsigned SerialNumber;
+
+	/**
+		\brief Return a firmware version string.
+		
+		The string is in the format of "x.y.z checksum" for example, "1.0.2 E113".
+
+		\CODE_SAMPLE_HDR
+		printf( "FW Ver=%s\n", myNode.Info.FirmwareVersion.Value());
+		// prints: 1.0.2 E113
+		\endcode
+	**/
+	ValueString &FirmwareVersion;
+														/** \cond SC_EXPERT **/
+	/**
+		\brief Get the version number code.
+
+		This is an unique value where the magnitude increases as newer firmware
+		is released.
+
+		\CODE_SAMPLE_HDR
+		printf( "FW code=0x%x\n", uint32_t(myNode.Info.FirmwareVersionCode));
+		// prints: 0x1002 which represents 1.0.2
+		\endcode
+	**/
+	ValueUnsigned FirmwareVersionCode;
+
+	/**
+		\brief Get the hardware version code string.
+
+		This reference allows access to the node's hardware version string.
+
+		\CODE_SAMPLE_HDR
+		printf( "HW Ver=%s\n", myNode.Info.HardwareVersion.Value());
+		// prints: K1
+		\endcode
+	**/
+	ValueString &HardwareVersion;
+															/** \endcond  **/
+	/**
+		\brief Get the model string.
+
+		This reference allows access to the model string for this node
+
+		\CODE_SAMPLE_HDR
+		printf( "Model=%s\n", myNode.Info.Model.Value());
+		// prints: CPM-SCSK-3411P-ELSA-1-0-D
+		\endcode
+	**/
+	ValueString &Model;
+
+	/**
+		\brief Get the positioning resolution
+
+		This function allows access to the node's positioning resolution. 
+		The returned value is the number of position counts per revolution.
+
+		\CODE_SAMPLE_HDR
+		//Get the positioning resolution of the Node
+		uint32_t myPosnResolution = myNode.Info.PositioningResolution;
+		\endcode
+	**/
+	ValueUnsigned PositioningResolution;
+
+	/**
+		\brief Return the enumerated type of this node.
+
+		This function is used to determine the type and base capabilities 
+		of this node. 
+
+		\CODE_SAMPLE_HDR
+		if (myNode.Info.NodeType() == IInfo::CLEARPATH_SC) {
+			printf( "My Node is a ClearPath-SC\n");
+			return(2);
+		}
+		if(myNode.Info.NodeType() != IInfo::CLEARPATH_SC_ADV){
+			printf( "My Node is an Advanced ClearPath-SC\n");
+			return(2);
+		}
+		\endcode
+	**/
+	virtual nodeTypes NodeType() = 0;
+
+	/**
+		\brief Manage the UserID string for this node.
+
+		Manage the UserID string for this node.  
+
+		\note This parameter is saved to and overwritten by [loading configuration files](@ref configfileLoadPage), or resetting to factory defaults
+
+		\CODE_SAMPLE_HDR
+		// Set User ID via the Value function
+		myNode.Info.UserID.Value("My Node");
+		// Set User ID via the operator= override
+		myNode.Info.UserID = "My Node";
+		// Get User ID via the Value function
+		cout << myNode.Info.UserID.Value() << endl;
+		// Get User ID via operator const char*()
+		const char *myParam = myNode.Info.UserID;
+		\endcode
+	**/
+	ValueString &UserID;
+
+	/**
+		\brief Set the Current User Defined Non-volatile Data.
+
+		\param [in] bank which bank of data to write to [0-3].
+
+		\param [in] m_lastUserData The data to write into the Node.  MN_USER_NV_SIZE = 13 for ClearPath SC Nodes.
+
+
+		This feature allows the storage of calibration or other data at a node
+		location. This information will be retained without power and survives
+		node restarts, and configuration file changes.  Up to 4 banks of 13 bytes are available
+
+		\note Restoring the node to Factory Settings will clear this 
+		data.
+
+		\CODE_SAMPLE_HDR
+		// Data to write
+		uint8_t newNV[MN_USER_NV_SIZE] = {
+			0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88,
+			0x99, 0xaa, 0xbb, 0xcc, 0xdd
+		};
+		// Write new data to bank 0
+		myNode.Info.UserData(0, newNV);
+		\endcode
+	**/
+	virtual void UserData(size_t bank, 
+						  const uint8_t m_lastUserData[MN_USER_NV_SIZE]) = 0;
+
+	/**
+		\brief Get the Current User Defined Non-volatile Data.
+
+		\param [in] bank which bank of data to access [0-3].
+
+		This function allows access to the non-volatile storage areas.
+
+		\note Restoring the node to Factory Settings will clear this 
+		data.
+
+		\CODE_SAMPLE_HDR
+		// Get non-volatile data from node bank 0.
+		vector<uint8_t> myUserNV = myNode.Info.UserData(0); 
+		\endcode
+	**/
+	virtual std::vector<uint8_t> UserData(size_t bank) = 0;
+
+
+	/**
+		\brief Manage User Volatile Data.
+
+		This feature is useful for your application to stash information in
+		a node in case the host application crashes.
+
+		\note This value is set to zero up power-up or restarting.
+
+		\CODE_SAMPLE_HDR
+		// Set the volatile value
+		myNode.Info.UserRAM = 0x1234
+		// Get the volatile value
+		cout << myNode.Info.UserRAM.Value() << endl;
+		// Alternate access way
+		uint16_t myVolatile = myNode.Info.UserRAM;
+		\endcode
+	**/
+	ValueUnsigned UserRAM;
+													
+	/**
+		\brief Expert Information Access.
+
+		This object allow access to expert information.
+
+		These include:
+		- The network address
+		- The node index for this node
+		- Generic Parameter maintenance
+	**/
+	IInfoEx &Ex;
+													/** \cond SC_EXPERT **/
+	/**
+		\brief Advanced model information access.
+
+		This object will work with Advanced firmware nodes.
+
+		There is no feature currently implemented here yet.
+	**/
+	IInfoAdv &Adv;
+													/** \endcond  **/
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Constructor
+	IInfo(INode &ourNode, IInfoAdv &adv, IInfoEx &ex,
+		nodeparam snPnum, nodeparam fwPnum, nodeparam usrRamPnum,
+		ValueString &userID, ValueString &hwVer, ValueString &fwStr,
+		ValueString &model, nodeparam resPnum);
+public:
+	virtual ~IInfo() {}
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ILimits Class
+											
+/**
+	\brief Torque and Position Limits Feature Interface.
+
+	This class object implements the settings for torque limits and
+	positional limits.  
+**/
+class MN_EXPORT ILimits : public IObjWithNode
+{
+public:
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Torque Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Access the node's global torque limit.
+
+		Access the node's global torque limit in the current user [torque units.](@ref sFnd::INode::TrqUnit).  
+		Typically this value is set through the ClearView application and is not changed during the application.
+
+		\CODE_SAMPLE_HDR
+		// Set the torque Limit to 100%
+		myNode.TrqUnit(myNode.PCT_MAX);
+		myNode.Limits.TrqGlobal = 100;
+		// Print out the torque limit
+		cout << myNode.Limits.TrqGlobal.Value() << endl;
+		// Alternate access way
+		double myTrqLimit = myNode.Limits.TrqGlobal;
+		\endcode
+	**/
+	ValueDouble TrqGlobal;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Position Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+																	/** \cond SC_EXPERT **/
+	/**
+		\brief Access the software limits 1.
+
+		Access the software limits 1.  Typically these values are set through the ClearView application and are not changed during the application.
+
+		\note Soft limits are only enabled when the absolute number space has been established via [homing](@ref HomingPage)
+	**/
+	ValueSigned SoftLimit1;
+
+	/**
+		\brief Access the software limits 2.
+
+		Access the software limits 2. Typically these values are set through the ClearView application and are not changed during the application.
+
+		\note Soft limits are only enabled when the absolute number space has been established via [homing](@ref HomingPage)
+		**/
+	ValueSigned SoftLimit2;
+																	/** \endcond  **/
+	/**
+		\brief Access the tracking limit shutdown point.
+		
+		Access the tracking limit shutdown point. This parameter is a safety limit should not be changed by the application 
+		during operation except is rare application specific circumstances.
+		
+		[Tracking error](@ref sFnd::IMotion::PosnTracking) at or beyond this point will cause a safety shutdown to occur. 
+	**/
+	ValueUnsigned PosnTrackingLimit;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Velocity Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+																	/** \cond SC_EXPERT **/
+	/**
+		\brief Access the motor speed limit. 
+		
+		This value is returned in the current user velocity units.
+		\todo Would this ever need to be changed or can we hide this?
+	**/
+	ValueDouble MotorSpeedLimit;
+	/**
+		\brief Access the advanced limits object.
+
+		Access to the advanced limit features for Advanced ClearPath-SC Nodes.
+	**/
+	ILimitsAdv &Adv;
+																	/** \endcond  **/
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction 
+	ILimits(INode &ourNode, ILimitsAdv &adv, 
+		nodeparam globTrqPnum, nodeparam trkLimPnum,
+		nodeparam softLim1Pnum, nodeparam softLim2Pnum,
+		nodeparam mtrSpdLimPnum);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IMotionAdv Class
+/**
+	\brief Advanced Motion Control Interface.
+
+	This class object allows setup and initiation of advanced motion features only available
+	in advance models of Clearpath SC.  These features include:
+
+	- [Head, and Tail Moves](@ref HeadTailMoveSect)
+	- [Asymmetric moves](@ref AsymetricalMoveSect)
+	- [Triggered Moves](@ref	CPMtriggerPage)
+	- [A after start](@ref cpmStatusRegFlds::AFromStart)/ [B after end events](@ref cpmStatusRegFlds::BFromEnd)  
+
+	\see \ref CPMAdvancedMovePage for more information.
+
+
+**/
+class MN_EXPORT IMotionAdv : public IObjWithNode
+{
+public:
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Kinematic Constraint Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Access the deceleration limit for the next issued Asymmetric move. 
+		
+		Access the decceleration limit value for the next asymmetric move. The value
+		is specified using this node's user acceleration units. Changed values will
+		apply to the next move.  The default units are RPM/sec
+	
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Decceleration Limit
+		myNode.Motion.Adv.DecelLimit = 10000.;				// Sets
+		double accLim = myNode.Motion.Adv.DecelLimit;	// Gets
+		\endcode
+
+		\see INode::AccUnit(enum _accUnits newUnits) Changing Acceleration Units
+	**/
+	ValueDouble DecelLimit;
+
+	/**
+			\brief Access the velocity limit for the head-tail sections of the
+		next issued head-tail move. 
+	
+		Access the current head/tail velocity limit for the next head-tail move.
+		The value is specified in the current velocity
+		units. Changed values will apply to the next issued move.  The default units 
+		are RPM.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Head/Tail Velocity Limit
+		myNode.Motion.Adv.HeadTailVelLimit = 1000.;				// Sets
+		double velLim = myNode.Motion.Adv.HeadTailVelLimit;	// Gets
+		\endcode
+
+		\see INode::VelUnit(enum _velUnits newUnits)
+	**/
+	ValueDouble HeadTailVelLimit;
+
+	/**
+		\brief Access the head distance for the next issued head-tail move.
+
+		Access the head distance for the next issued head-tail move
+		in steps.
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "Regular" 6400cnts/rev for "Enhanced").
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Head Distance 
+		myNode.Motion.Adv.HeadDistance = 10000.;				// Sets
+		double headDist = myNode.Motion.Adv.HeadDistance;	// Gets
+		\endcode
+		
+	**/
+	ValueUnsigned HeadDistance;
+
+	/**
+		\brief Access the tail distance for the next issued head-tail move.
+
+		Access the tail distance for the next issued head-tail
+		move in steps.
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "Regular" 6400cnts/rev for "Enhanced").
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Tail Distance 
+		myNode.Motion.Adv.TailDistance = 10000.;				// Sets
+		double tailDist = myNode.Motion.AdvTaildDistance;	// Gets
+		\endcode
+	**/
+	ValueUnsigned TailDistance;
+
+	/**
+		\brief Access the <i>A after Start</i> event distance.
+
+		Access the <i>A after Start</i> event distance
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "Regular" 6400cnts/rev for "Enhanced").
+
+		\see cpmStatusRegFlds::AFromStart for the associated Status event
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the A after start distance
+		myNode.Motion.Adv.AfterStartDistance = 10000.;				// Sets
+		double Adist = myNode.Motion.Adv.AfterStartDistance;	// Gets
+		\endcode
+	**/
+	ValueUnsigned AfterStartDistance;
+	/**
+		\brief Access the <i>B before End</i> event distance.
+
+		Access the <i>B before End</i> event distance in steps.
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "Regular" 6400cnts/rev for "Enhanced").
+
+		\see cpmStatusRegFlds::BFromEnd for the associated Status event
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the B before end distance
+		myNode.Motion.Adv.BeforeEndDistance = 10000.;				// Sets
+		double Bdist = myNode.Motion.Adv.BeforeEndDistance;	// Gets
+		\endcode
+	**/
+	ValueUnsigned BeforeEndDistance;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Motion Duration Calculation Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Calculate the duration of a positional move.
+
+		\param [in] targetPosn Target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a targetIsAbsolute argument.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\return duration (milliseconds)
+
+		Using the currently specified kinematic constraints, return the
+		expected duration (in milliseconds) of the move from when it
+		starts to when the move command completes.
+
+		This function is useful for setting up timeouts or helping to schedule
+		other events in your application.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Using MovePosnDurationMsec to set up a reasonable timeout for a move to complete
+
+		//define a timeout in case the node is unable to complete the move
+		double timeout =  mynode.Motion.Adv.MoveDurationMsec(1000) + 100;  
+		double StartTime = myMgr.TimeStampMsec();
+
+		//This will loop checking to see if the node went Move done with the defined timeout
+		while (!mynode.Motion.MoveWentDone() && myMgr.TimeStampMsec() < StartTime+timeout) 
+		{//Wait for move to complete
+		}
+
+		\endcode
+
+	**/
+	double MovePosnDurationMsec(int32_t targetPosn,
+		bool targetIsAbsolute = false);
+
+	/**
+		\brief Returns the duration of a head-tail positional move.
+
+		\param [in] targetPosn Target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a theType argument. The triggered
+		type move will prevent execution of the motion until a
+		trigger event is detected at the node.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\param [in] hasHead Do not exceed the HeadTailVelLimit until
+		after HeadDistance steps have been sent.
+		\param [in] hasTail Do not exceed the HeadTailVelLimit during
+		the last TailDistance steps of the move.
+		\return motion duration (milliseconds)
+
+		Using the currently specified kinematic constraints, return the
+		expected duration (in milliseconds) of the move from when it
+		starts to when the move command completes.
+
+		This function is useful for setting up timeouts or helping to schedule
+		other events in your application.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Using MovePosnHeadTailDurationMsec to set up a reasonable timeout for a head-tail move to complete
+
+		//define a timeout in case the node is unable to complete the move
+		double timeout =  mynode.Motion.Adv.MovePosnHeadTailDurationMsec(1000) + 100;  
+		double StartTime = myMgr.TimeStampMsec();
+
+		//This will loop checking to see if the node went Move done with the defined timeout
+		while (!mynode.Motion.MoveWentDone() && myMgr.TimeStampMsec() < StartTime+timeout) 
+		{//Wait for move to complete
+		}
+
+		\endcode
+	**/
+	virtual double MovePosnHeadTailDurationMsec(int32_t targetPosn,
+		bool targetIsAbsolute = false,
+		bool hasHead = true,
+		bool hasTail = true);
+
+	/**
+		\brief Returns the duration of an asymmetric positional move.
+
+		\param [in] targetPosn Target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a theType argument. The triggered
+		type move will prevent execution of the motion until a
+		trigger event is detected at the node.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\return motion duration (milliseconds)
+
+		Using the currently specified kinematic constraints, return the
+		expected duration (in milliseconds) of the move from when it
+		starts to when the move command completes.
+
+		This function is useful for setting up timeouts or helping to schedule
+		other events in your application.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Using MovePosnAsymDurationMsec to set up a reasonable timeout for an asymmetric move to complete
+
+		//define a timeout in case the node is unable to complete the move
+		double timeout =  mynode.Motion.Adv.MovePosnAsymDurationMsec(1000) + 100;  
+		double StartTime = myMgr.TimeStampMsec();
+
+		//This will loop checking to see if the node went Move done with the defined timeout
+		while (!mynode.Motion.MoveWentDone() && myMgr.TimeStampMsec() < StartTime+timeout) 
+		{//Wait for move to complete
+		}
+
+		\endcode
+	**/
+	virtual double MovePosnAsymDurationMsec(int32_t targetPosn,
+		bool targetIsAbsolute = false);
+
+
+	/**
+		\brief Returns the duration of a velocity move.
+
+		\param [in] targetCountsPerSec Target velocity. (counts/sec)		
+		\return time to reach target velocity (milliseconds)
+
+		Using the currently specified kinematic constraints, return the
+		expected duration (in milliseconds) of the move's acceleration to the target velocity.
+
+		This function is useful for setting up timeouts or helping to schedule
+		other events in your application.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Using MoveVelDurationMsec to set up a reasonable timeout for a velocity move to complete
+
+		//define a timeout in case the node is unable to complete the move
+		double timeout = mynode.Motion.MoveVelDurationMsec() + 100;
+		double StartTime = myMgr.TimeStampMsec();
+
+		//This will loop checking to see if the node went Move done with the defined timeout
+		while (!mynode.Motion.VelocityReachedTarget() && myMgr.TimeStampMsec() < StartTime+timeout)
+		{//Wait for move to complete
+		}
+
+		\endcode
+	**/
+	double MoveVelDurationMsec(double targetCountsPerSec);
+
+
+	/**/
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Motion Initiating Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Initiate a trapezoid/triangle positional move.
+
+		\param [in] targetPosn Target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a theType argument. The triggered
+		type move will prevent execution of the motion until a
+		trigger event is detected at the node.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\param [in] isTriggered The move awaits a trigger event
+		to start the motion if true.
+		\param [in] hasDwell The move will wait the dwell parameter
+		amount of time before starting the next move.
+		\return Number of additional moves the node will accept.
+
+		The move is kinematically limited by the current
+		[acceleration](@ref sFnd::IMotion::AccLimit), and [velocity](@ref sFnd::IMotion::VelLimit) limits.
+
+		Move requests are buffered and requests initiated during an active move will execute
+		immediately after the active move completes.  Triggered moves will wait for a trigger event before executing.
+		The return value will tell you the number of additional moves that may be queued(up to 16) when
+		this request is processed.  You can also use the <i>Status
+		Register's</i> #_cpmStatusRegFlds::MoveBufAvail field, which will be
+		deasserted when the buffer is full.
+
+		\see sFnd::IPortAdv::TriggerMovesInGroup For starting these moves
+		\see sFnd::IMotionAdv::TriggerMove For starting these moves
+	**/
+	virtual size_t MovePosnStart(int32_t targetPosn,
+		bool targetIsAbsolute = false,
+		bool isTriggered = false,
+		bool hasDwell = false) = 0;
+
+	/**
+		\brief Initiate a head-tail positional move.
+
+		\param [in] targetPosn The target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a theType argument. The triggered
+		type move will prevent execution of the motion until a
+		trigger event is detected at the node.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\param [in] isTriggered The move awaits a trigger event
+		to start the motion if true.
+		\param [in] hasHead Do not exceed the HeadTailVelLimit until
+		after HeadDistance steps have been sent.
+		\param [in] hasTail Do not exceed the HeadTailVelLimit during
+		the last TailDistance steps of the move.
+		\param [in] hasDwell delay the next move being issued
+		by DwellMs after this move profile completes.
+		\return Number of additional moves the node will accept.
+
+		The move is kinematically limited by the current
+		[acceleration](@ref sFnd::IMotion::AccLimit), [velocity](@ref sFnd::IMotion::VelLimit), as well as [Head](@ref sFnd::IMotionAdv::HeadDistance) and [tail](@ref sFnd::IMotionAdv::TailDistance) distances.
+
+		Move requests are buffered and requests initiated during an active move will execute
+		immediately after the active move completes.  Triggered moves will wait for a trigger event before executing.
+		The return value will tell you the number of additional moves that may be queued(up to 16) when
+		this request is processed.  You can also use the <i>Status
+		Register's</i> #_cpmStatusRegFlds::MoveBufAvail field, which will be
+		deasserted when the buffer is full.
+
+		\see sFnd::IPortAdv::TriggerMovesInGroup For starting these moves
+		\see sFnd::IMotionAdv::TriggerMove For starting these moves
+	**/
+	virtual size_t MovePosnHeadTailStart(int32_t targetPosn,
+		bool targetIsAbsolute = false,
+		bool isTriggered = false,
+		bool hasHead = true,
+		bool hasTail = true,
+		bool hasDwell = false) = 0;
+
+	/**
+		\brief Initiate a asymmetric positional move.
+
+		\param [in] targetPosn Target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a theType argument. The triggered
+		type move will prevent execution of the motion until a
+		trigger event is detected at the node.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\param [in] isTriggered The move awaits a trigger event
+		to start the motion if true.
+		\param [in] hasDwell The move will wait the dwell parameter
+		amount of time before starting the next move.
+		\return Number of additional moves the node will accept.
+
+		The move is kinematically limited by the current
+		[acceleration](@ref sFnd::IMotion::AccLimit), [deceleration](@ref sFnd::IMotionAdv::DecelLimit), and [velocity](@ref sFnd::IMotion::VelLimit).
+
+		Move requests are buffered and requests initiated during an active move will execute
+		immediately after the active move completes.  Triggered moves will wait for a trigger event before executing.
+		The return value will tell you the number of additional moves that may be queued(up to 16) when
+		this request is processed.  You can also use the <i>Status
+		Register's</i> #_cpmStatusRegFlds::MoveBufAvail field, which will be
+		deasserted when the buffer is full.
+
+		\see sFnd::IPortAdv::TriggerMovesInGroup For starting these moves
+		\see sFnd::IMotionAdv::TriggerMove For starting these moves
+	**/
+	virtual size_t MovePosnAsymStart(int32_t targetPosn,
+		bool targetIsAbsolute = false,
+		bool isTriggered = false,
+		bool hasDwell = false) = 0;
+
+	/**
+		\brief Initiate a velocity move.
+
+		\param [in] targetPosn Target velocity. If the \a triggered
+		argument is true, this move will wait for a trigger event
+		to be detected at the node.
+		\param [in] isTriggered The move awaits a trigger event
+		to start the motion if true.
+		\return Number of additional moves the node will accept.
+
+		The move is kinematically limited by the current
+		[acceleration limit](@ref sFnd::IMotion::AccLimit).
+
+		Move requests are buffered and requests initiated during an active move will execute
+		immediately after the active move completes.  Triggered moves will wait for a trigger event before executing.
+		The return value will tell you the number of additional moves that may be queued(up to 16) when
+		this request is processed.  You can also use the <i>Status
+		Register's</i> #_cpmStatusRegFlds::MoveBufAvail field, which will be
+		deasserted when the buffer is full.
+
+	**/
+	virtual size_t MoveVelStart(double targetPosn,
+		bool isTriggered = false) = 0;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Triggering waiting moves
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	/**
+		\brief Trigger a waiting move
+
+		Call this function to release a waiting move.
+
+		\note If there are no waiting moves or if the Node is currently executing a move, this command will be ignored.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This loads a relative triggered move into the move buffer
+		mynode.Motion.Adv.MovePosnStart(1000,false,true);
+
+		//No motion has occurred yet...
+
+		mynode.Motion.Adv.TriggerMove();
+		//Motion now begins
+
+		\endcode
+	**/
+	virtual void TriggerMove() = 0;
+
+	/**
+		\brief Trigger a group of waiting moves
+
+		Call this function to release waiting moves in this trigger group.
+
+		\note If there are no waiting moves, or if the node is currently executing a move this command will be ignored on that node.
+
+		/see CPMtriggerPage
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This loads a relative triggered move into each node
+		mynode.Motion.Adv.MovePosnStart(1000,false,true);
+		myothernode.Motion.Adv.MovePosnStart(1000,false,true);
+
+		//No motion has occurred yet...
+
+		mynode.Motion.Adv.TriggerMovesInMyGroup();
+		//If both Nodes share a trigger group, then both node will start motion now
+		//If the nodes do not share a trigger group only mynode will begin motion
+
+		\endcode
+	**/
+	virtual void TriggerMovesInMyGroup() = 0;
+
+	/**
+		\brief Get our current trigger group setting. 
+
+		\return This node's current group number
+
+		If zero, there is no trigger group assigned and the group trigger
+		will be ignored.
+	**/
+	virtual size_t TriggerGroup() = 0;
+
+	/**
+		\brief Set our trigger group
+
+		\param[in] groupNumber Set to non-zero to assign this
+		node to a triggerable group. To remove from a group set to zero.
+
+		\remark The trigger group allows multiple nodes to start motion with low
+		latency. For example a machine with multiple XYZ axes could assign
+		\a groupNumber 1 to one set and 2 to another. Releasing one group with
+		a sFnd::IPortAdv::TriggerMovesInGroup(size_t) call, or by calling #TriggerMovesInMyGroup on one of the Nodes.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This will set two Nodes to have the same trigger group
+		mynode.Motion.Adv.TriggerGroup(1);
+		myothernode.Motion.Adv.TriggerGroup(1);
+
+		//set the last node to have a different trigger group
+		myThirdNode.Motion.Adv.TriggerGroup(2);
+
+		\endcode
+	**/
+	virtual void TriggerGroup(size_t groupNumber) = 0;
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction 
+	IMotionAdv(INode &ourNode,
+		nodeparam decLimPnum, nodeparam headTailVlimPnum, nodeparam headDxPnum,
+		nodeparam tailDxPnum, nodeparam aDxPnum, nodeparam bDxPnum);
+	// Destruction
+public:
+	virtual ~IMotionAdv() {};
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IMotion Class
+/**
+	\brief Motion Control Feature Interface.
+
+	This class object allows setup, initiation and cancellation of motion.
+**/
+class MN_EXPORT IMotion : public IObjWithNode
+{
+public:
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Kinematic Constraint Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Current Node Acceleration Limit
+
+		Access the acceleration limit value for the next issued move. The value
+		is specified using this node's user acceleration units. Changed values will
+		apply to the next move.  The default units are RPM/sec
+	
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Acceleration Limit
+		myNode.Motion.AccLimit = 10000.;				// Sets
+		double accLim = myNode.Motion.AccLimit;	// Gets
+		\endcode
+
+		\see INode::AccUnit(enum _accUnits newUnits) Changing Acceleration Units
+	**/
+	ValueDouble AccLimit;
+
+	/**
+		\brief Current Node Velocity Limit
+
+		Access the current velocity limit value specified in the current velocity
+		units. Changed values will apply to the next issued move.  The default units 
+		are RPM.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Velocity Limit
+		myNode.Motion.VelLimit = 1000.;				// Sets
+		double velLim = myNode.Motion.VelLimit;	// Gets
+		\endcode
+
+		\see INode::VelUnit(enum _velUnits newUnits)
+	**/
+	ValueDouble VelLimit;
+
+													/** \cond SC_EXPERT **/
+	/**
+		\brief Get the current jerk limit register.
+	**/
+	ValueUnsigned JrkLimit;
+
+	/**
+		\brief Get the current delay added by the jerk limit.
+	**/
+	ValueDouble JrkLimitDelay;
+													/** \endcond  **/
+	/**
+		\brief Post-motion dwell time in milliseconds.
+
+		Access to the post move dwell time used in positional moves with a after-move dwell.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the Post-motion dwell time.
+		myNode.Motion.DwellMs = 100.;				// Sets
+		double myDwell = myNode.Motion.DwellMs;	// Gets
+		\endcode
+
+		\see MovePosnStart() for more information on how to command a positional move with dwell
+
+	**/
+	ValueUnsigned DwellMs;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Motion Duration Calculation Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Calculate the duration of a positional move.
+
+		\param[in] target Target position. This is either the
+		absolute position or relative to the current position
+		depending on the \a targetIsAbsolute argument.
+		\param[in] targetIsAbsolute The target is an absolute
+		destination.
+
+		Using the currently specified kinematic constraints, return the
+		expected duration (in milliseconds) of the move from when it
+		starts to when the move command completes.
+
+		This function is useful for setting up timeouts or helping to schedule
+		other events in your application.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Using MovePosnDurationMsec to set up a reasonable timeout for a move to complete
+
+		//define a timeout in case the node is unable to complete the move
+		double timeout =  mynode.Motion.MoveDurationMsec(1000) + 100;  
+		double StartTime = myMgr.TimeStampMsec();
+
+		//This will loop checking to see if the node went Move done with the defined timeout
+		while (!mynode.Motion.MoveWentDone() && myMgr.TimeStampMsec() < StartTime+timeout) 
+		{//Wait for move to complete
+		}
+
+		\endcode
+
+	**/
+	virtual double MovePosnDurationMsec(int32_t target,
+		bool targetIsAbsolute = false);
+
+	/**
+		\brief Calculate the duration of a velocity move.
+
+		\param [in] target Target velocity.
+
+		Using the currently specified kinematic constraints, return the
+		expected duration (in milliseconds) of the move's acceleration to the target velocity.
+
+		This function is useful for setting up timeouts or helping to schedule
+		other events in your application.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Using MoveVelDurationMsec to set up a reasonable timeout for a velocity move to complete
+
+		//define a timeout in case the node is unable to complete the move
+		double timeout = mynode.Motion.MoveVelDurationMsec() + 100;
+		double StartTime = myMgr.TimeStampMsec();
+
+		//This will loop checking to see if the node went Move done with the defined timeout
+		while (!mynode.Motion.VelocityReachedTarget() && myMgr.TimeStampMsec() < StartTime+timeout)
+		{//Wait for move to complete
+		}
+
+		\endcode
+	**/
+	virtual double MoveVelDurationMsec(double target);
+
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Motion Initiating Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Initiate a positional move.
+
+		\param [in] target Target position. This is either the
+		absolute position of relative to the current position
+		depending on the \a targetIsAbsolute argument.
+		\param [in] targetIsAbsolute the target is an absolute
+		destination.
+		\param [in] addPostMoveDwell delay the next move being issued
+		by DwellMs after this move profile completes.
+		\return Number of additional moves the node will accept.
+
+		The move is kinematically limited by the current
+		[acceleration](@ref AccLimit), and [velocity](@ref VelLimit) limits.
+
+		Move requests are buffered and requests initiated during an active move will execute
+		immediately after the active move completes. The return value
+		will tell you the number of additional moves that may be queued(up to 16) when
+		this request is processed.  You can also use the <i>Status
+		Register's</i> #_cpmStatusRegFlds::MoveBufAvail field, which will be
+		deasserted when the buffer is full.
+	**/
+	virtual size_t MovePosnStart(int32_t target,
+		bool targetIsAbsolute = false,
+		bool addPostMoveDwell = false) = 0;
+
+	/**
+		\brief Initiate a velocity move.
+
+		\param [in] target Target velocity.
+		\return Number of additional moves the node will accept.
+
+		The move is kinematically limited by the current
+		[acceleration limit](@ref sFnd::IMotion::AccLimit).
+
+		Move requests are buffered and requests initiated during a active move will execute
+		immediately after the active move completes. The return value
+		will tell you the number of additional moves that may be queued(up to 16) when
+		this request is processed. You can also use the <i>Status
+		Register's</i> #_cpmStatusRegFlds::MoveBufAvail field, which will be
+		deasserted when the buffer is full.
+	**/
+	virtual size_t MoveVelStart(double target) = 0;
+
+	/**
+		\brief Update the status rise register and test and clear the move
+		done field.
+
+		Update the [status rise register](@ref sFnd::IStatus::Rise)  and test and clear the node
+		[Move Done](@ref cpmStatusRegFlds::MoveDone) field.
+
+		\return true if [Move Done](@ref cpmStatusRegFlds::MoveDone) went true since last call.
+
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This checks if the Node has reached move done since the last time the application checked.
+		if(mynode.Motion.VelocityReachedTarget())
+		{
+		printf("the Node reached move done");
+		}
+		else
+		{
+		printf("the Node has not reached move done");
+		}
+
+		\endcode
+
+		\note For performance reasons it may be superior to use the [Status reference](@ref sFnd::IStatus::Rise) 
+		and perform a Refresh in a periodic place in your
+		application and check the results via the [Status object](@ref sFnd::ValueStatus).
+	**/
+	virtual bool MoveWentDone() = 0;
+
+	/**
+		\brief Update the real-time status register and test for move done.
+
+		Refresh the [real-time status register](@ref sFnd::IStatus::RT) and test for [Move Done](@ref cpmStatusRegFlds::MoveDone). 
+		This allows for a simple script-like interface.
+
+
+		\return true if [Move Done](@ref cpmStatusRegFlds::MoveDone) is true.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This checks if the Node is move done.
+		if(mynode.Motion.MoveIsDone())
+		{
+		printf("the Node is move done");
+		}
+		else
+		{
+		printf("the Node is not move done");
+		}
+
+		\endcode
+
+		\note For performance reasons it may be superior to use the  [real-time status register](@ref sFnd::IStatus::RT) reference
+		and perform a Refresh in a periodic place in your application and check the results via the [Status object](@ref sFnd::ValueStatus).
+	**/
+	virtual bool MoveIsDone() = 0;
+
+	/**
+		\brief Update the status rise register and test and clear the 
+		At Target Velocity field.
+
+		Update the [status rise register](@ref sFnd::IStatus::Rise)  and test and clear the node
+		[At Target Velocity](@ref cpmStatusRegFlds::AtTargetVel) field.
+
+		\return true if <i>At Target Velocity</i> went true since last call.
+
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This checks if the Node has reached the target velocity since the last time the application checked.
+		if(mynode.Motion.VelocityReachedTarget())
+		{
+		printf("the Node reached target velocity");
+		}
+		else
+		{
+		printf("the Node has not reached the target velocity");
+		}
+
+		\endcode
+
+		\note For performance reasons it may be superior to use the [status rise register](@ref sFnd::IStatus::Rise) reference
+		and perform a Refresh in a periodic place in your
+		application and check the results via the [Status object](@ref sFnd::ValueStatus).
+
+
+	**/
+	virtual bool VelocityReachedTarget() = 0;
+
+	/**
+		\brief Update the real-time status register and test for At 
+		Target Velocity.
+
+		Refresh the [real-time status register](@ref sFnd::IStatus::RT) and test for [At Target Velocity](@ref cpmStatusRegFlds::AtTargetVel). 
+		This allows for a simple script-like interface.
+
+		\return true if [At Target Velocity](@ref cpmStatusRegFlds::AtTargetVel) is true.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This checks if the Node is at the commanded velocity
+		if(mynode.Motion.VelocityAtTarget())
+		{
+		printf("the Node is at velocity");
+		}
+		else
+		{
+		printf("the Node is not at velocity");
+		}
+
+		\endcode
+
+		\note For performance reasons it may be necessary to use the [Status reference](@ref sFnd::IStatus::RT) 
+		and manually perform a Refresh in a periodic place if your application and check the results.
+	**/
+	virtual bool VelocityAtTarget() = 0;
+
+	/**
+		\brief Update the status rise register and test and clear the node
+		not ready field.
+
+		Update the [status rise register](@ref sFnd::IStatus::Rise)  and test and clear the node
+		 [Not Ready](@ref cpmStatusRegFlds::NotReady) field.
+
+		 \CODE_SAMPLE_HDR
+		 // SAMPLE: This checks if the Node has gone not ready since the last time the application checked.
+		 if(mynode.Motion.WentNotReady())
+		 {
+		 printf("the Node went not ready");
+		 }
+		 else
+		 {
+		 printf("the Node has been and still is ready");
+		 }
+
+		 \endcode
+
+		 \note For performance reasons it may be superior to use the [status rise register](@ref sFnd::IStatus::Rise) 
+		 reference and perform a Refresh in a periodic place in your
+		 application and check the results via the [Status object](@ref sFnd::ValueStatus).
+	**/
+	virtual bool WentNotReady() = 0;
+
+	/**
+		\brief Update the real-time status register and test for Node ready.
+
+		Refresh the [real-time status register](@ref sFnd::IStatus::RT) and test for [Node Ready](@ref cpmStatusRegFlds::NotReady). 
+		This allows for a simple script-like interface.
+
+		\return true if the Node is [ready](@ref cpmStatusRegFlds::NotReady) for motion command.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This checks if the Node is ready for motion commands
+		if(mynode.Motion.IsReady())
+		{
+			printf("the Node is ready");
+		}
+		else
+		{
+			printf("the Node is not ready");
+		}
+
+		\endcode
+
+		\note For performance reasons it may be necessary to use the [Status reference](@ref sFnd::IStatus::RT)
+		and manually perform a Refresh in a periodic place if your application and check the results via the Status object.
+	**/
+	virtual bool IsReady() = 0;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Motion Cancel Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	/**
+		\brief Initiate a simple node stop at this node.
+
+		\param[in] howToStop One of the commonly used <i>Node Stop codes.</i>
+
+		This is the simplest way to command a nodestop.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: This issues an abrupt nodestop on this node
+		mynode.Motion.NodeStop(STOP_TYPE_ABRUPT);		
+
+		// SAMPLE: This issues a nodestop to ramp to zero velocity using the current decel parameter's on this node
+		mynode.Motion.NodeStop(STOP_TYPE_RAMP_WITH_DECEL);		
+
+		\endcode
+
+		\see [Node Stop Page](@ref CPMnodeStopPage) for a complete list of stop types
+		\see sFnd::IMotion::NodeStopClear To clear latching attributes
+
+	**/
+	virtual void NodeStop(nodeStopCodes howToStop) = 0;
+														/** \cond ISC_DOC **/
+	/**
+		\brief Initiate a node stop at this node
+
+		\param[in] howToStop Reference to a <i>Node Stop Register</i> object 
+		specifying how to stop this node.
+
+		This is the most flexible form of <i>Node Stop</i>. It is used to initiate
+		or clear latching modifiers, such as the E-Stop condition.
+
+		\see sFnd::IMotion::NodeStopClear To clear latching attributes
+
+	**/
+	virtual void NodeStop(mgNodeStopReg &howToStop) = 0;
+													/** \endcond **/
+
+	/**
+		\brief Initiate a node stop on all nodes on this port.
+
+		\param[in] howToStop One of the commonly used <i>Node Stop codes.</i>
+
+		This is the simplest way to broadcast a group node stop. This issues
+		a stop of the specified type to all nodes on the initiating node's port.
+
+		\see sFnd::IMotion::NodeStopClear To clear latching attributes
+
+	**/
+	virtual void GroupNodeStop(nodeStopCodes howToStop) = 0;
+
+	/**
+		\brief Clear all latching Node Stop modifiers.
+
+		This function will clear the MotionLock, E-Stop, Controlled, Disabled, 
+		etc. latching conditions from the node. This will allow
+		normal operations to continue, unless the motor is shutdown state.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Clear any Current NodeStops
+		myNode.Motion.NodeStopClear();
+		\endcode
+
+		\see sFnd::IMotion::NodeStop(nodeStopCodes) For initiating Node Stops
+	**/
+	virtual void NodeStopClear() = 0;
+														/** \cond SC_EXPERT **/
+	/**
+		\brief Access the stopping acceleration limits in step/sec^2.
+	**/
+	ValueDouble NodeStopDecelLim;
+														/** \endcond  **/
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Position Status Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Access the current measured position.
+
+		Access the current measured position.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current measured position.
+		double myPosn = myNode.Motion.PosnMeasured;
+		\endcode
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "Regular" 6400cnts/rev for "Enhanced").
+		This means that for step+direction modes the position may be scaled differently from the step and direction input  based on the ratio of the input 
+		resolution set up through ClearView, and the motor's native positioning resolution.  For example, if you are using a "Regular" ClearPath-SC motor
+		with a native positioning resolution of 800 cnts/rev, and you set the Input resolution to 200 steps/rev to drop in for a 200 cnt stepper motor, each
+		step sent will change the position 4 cnts.
+	**/
+	ValueDouble PosnMeasured;
+
+	/**
+		\brief Access the current commanded position.
+
+		Access the current commanded position.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current commanded position.
+		double myPosnCmd = myNode.Motion.PosnCommanded;
+		\endcode
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "R" 6400cnts/rev for "E").
+		This means that for step and direction modes, the position may be scaled differently from the step and direction input  based on the ratio of the input 
+		resolution set up through ClearView, and the motor's native positioning resolution.  For example, if you are using a "R" ClearPath-SC motor
+		with a native positioning resolution of 800 cnts/rev, and you set the Input resolution to 200 steps/rev to drop in for a 200 cnt stepper motor, each
+		step sent will change the position 4 cnts.
+	**/
+	ValueDouble PosnCommanded;
+
+	/**
+		\brief Access the current position tracking error.
+
+		Access the current position tracking error.  Tracking error is defined as commanded position - measured position.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current position tracking error.
+		double myPosnErr = myNode.Motion.PosnTracking;
+		\endcode
+
+		\note The resolution of this value will be the same as the positioning resolution of the motor (800cnts/rev for "Regular" 6400cnts/rev for "Enhanced").
+		This means that for step+direction modes the position may be scaled differently from the step and direction input  based on the ratio of the input 
+		resolution set up through ClearView, and the motor's native positioning resolution.  For example, if you are using a "Regular" ClearPath-SC motor
+		with a native positioning resolution of 800 cnts/rev, and you set the Input resolution to 200 steps/rev to drop in for a 200 cnt stepper motor, each
+		step sent will change the position 4 cnts.
+	**/
+	ValueDouble PosnTracking;
+
+	/**
+		\brief Adjust number space.
+
+		\param[in] adjAmount The amount to adjust the number space.
+
+		This function is used mostly with a manual homing process, or anytime an application need to adjust the number space. It allows
+		the [measured](@ref PosnMeasured)  and [commanded](@ref PosnCommanded) position to be shifted by the specified amount.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Zeroing the number space around the current Measured Position
+		myNode.Motion.AddToPosition(-myNode.Motion.PosnMeasured);
+		\endcode
+
+		\note If using Soft Position limits, this command will
+		reset the motor's ["Was Homed"](@ref  _cpmStatusRegFlds::WasHomed) status causing the soft
+		limit settings to be ignored.  To re-enable soft limits see the \ref IHoming::SignalComplete function.
+
+	**/
+	virtual void AddToPosition(double adjAmount) = 0;
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Velocity Status Group
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Access the current measured velocity.
+
+		Access the current measured velocity. The velocity is scaled to the
+		current node's velocity unit.  The default units are RPM.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current measured velocity.
+		double myVel = myNode.Motion.VelMeasured;
+		\endcode
+
+		\see INode::VelUnit(_velUnits) To set velocity units.
+	**/
+	ValueDouble VelMeasured;
+
+	/**
+		\brief Access the current commanded velocity.
+
+		Access the current commanded velocity. The velocity is scaled to the
+		current node's velocity unit. The default units are RPM.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current commanded velocity.
+		double myVelCmd = myNode.Motion.VelCommanded;
+		\endcode
+
+		\see INode::VelUnit(_velUnits) To set velocity units.
+	**/
+	ValueDouble VelCommanded;
+
+	/**
+		\brief Access the current measured torque.
+
+		Access the current measured torque. The torque is scaled to the 
+		current node's torque unit. The default units are percentage of maximum.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current measured torque.
+		double myTrq = myNode.Motion.TrqMeasured;
+		\endcode
+
+		\see INode::TrqUnit(_trqUnits)
+	**/
+	ValueDouble TrqMeasured;
+
+	/**
+		\brief Access the current commanded torque.
+
+		Access the current commanded torque. The torque is scaled to the 
+		current node's torque unit. The default units are percentage of maximum.
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Reading the current commanded Torque.
+		double myTrqCmd = myNode.Motion.TrqCommanded;
+		\endcode
+
+		\see INode::TrqUnit(_trqUnits)
+	**/
+	ValueDouble TrqCommanded;
+
+	/**
+		\brief Access advanced features if available on the node's model.
+	**/
+	IMotionAdv &Adv;
+
+	/**
+		\brief Access to the homing feature.
+	**/
+	IHoming &Homing;
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction 
+	IMotion(INode &ourNode, IMotionAdv &adv, IHoming &homing,
+		nodeparam accLimPnum, nodeparam velLimPnum, nodeparam stopDecLimPnum,
+		nodeparam posnMeasPnum, nodeparam posnCmdPnum, nodeparam posnTrkPnum,
+		nodeparam velMeasPnum, nodeparam velCmdPnum,
+		nodeparam trqMeasPnum, nodeparam trqCmdPnum, nodeparam jrkLimPnum,
+		nodeparam dwellPnum, nodeparam jrkDelayPnum);
+	// Destruction
+public:
+	virtual ~IMotion() {};
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																	      *
+// 	IOuts class
+/** \cond SC_EXPERT **/
+/**
+
+	\brief Output Register Interface.
+
+	This class manages the access to the output registers.
+
+	This includes:
+	- The <i>User Output Register</i>
+	- Access to the actual output register state
+
+	Functions are provided to allow thread safe modifications to the
+	<i>User Output Register</i>.
+**/
+class MN_EXPORT IOuts : public IObjWithNode
+{
+protected:
+public:
+	// Easy access to enable request
+	
+	/**
+	\copydoc INode::EnableReq(bool)
+	**/
+	virtual void EnableReq(bool newState) = 0;
+	/**
+	\copydoc INode::EnableReq(bool)
+	**/
+	virtual bool EnableReq() = 0;
+	// Access to whole output register
+	/**
+		\brief Access the <i>User Output Register</i>.
+
+		Access the <i>User Output Register</i> object. This is used to 
+		change application initiated actions. 
+
+		\note Use the Set and Clear functions to adjust this register when
+		multiple threads may be changing this register.
+	**/
+	ValueOutReg User;
+	/**
+		\brief Access the <i>Operational Output Register</i>.
+
+		This read-only reference will allow access to the current 
+		<i>Operational Output Register</i>. This register is the internal
+		register that engages the features attached to it.
+	**/
+	ValueOutReg Out;
+protected:
+													
+	// Construction
+	IOuts(INode &ourNode, nodeparam usrOutPnum, nodeparam outPnum);
+	virtual ~IOuts() {};
+													
+};
+			/** \endcond **/
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ISetupEx class
+/**
+	\brief Expert Setup Interface.
+
+	This class allows access to the more advanced setup options for this node. Items accessed in this class may be overridden by ClearView or 
+	configuration file loads.
+**/
+class MN_EXPORT ISetupEx : public IObjWithNode
+{
+													/** \cond INTERNAL_DOC **/
+	friend class ISetup;
+													/** \endcond **/
+public:
+	/**
+		\brief Network watchdog timer. 
+		
+		This allows the adjustment of a network watchdog timer that will
+		force a ramped Node Stop if the host stops communicating with
+		the node. This is a safety feature and should not be changed except in 
+		rare application specific circumstances.
+
+		The ramp stop acceleration is setup via the E-Stop deceleration rate in ClearView.
+		This is found in the details dropdown menu in ClearView.
+		
+		Set this to zero to disable. Units are milliseconds.
+
+		\note This setting can be [saved into a config file](@ref sFnd::ISetup::ConfigSave), and is overwritten when a [config file is loaded](@ref sFnd::ISetup::ConfigLoad).
+	**/
+	ValueDouble NetWatchdogMsec;
+													/** \cond SC_EXPERT **/
+	/**
+		\brief Access application setup register.
+
+		This register will not be changed for nearly all applications.
+		This register is configured within the motor configuration file, and will not typically change during operation.
+	**/
+	ValueAppConfigReg App;
+
+	/**
+		\brief Access the hardware setup register.
+
+		This register will not be changed for nearly all applications.
+		This register is configured within the motor configuration file, and will not typically change during operation.
+	**/
+	ValueHwConfigReg HW;
+														/** \endcond  **/
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction
+	ISetupEx(INode &ourNode,
+		nodeparam appPnum, nodeparam hwPnum, nodeparam netWdPnum);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	ISetup class
+/**
+	\brief Node Setup Features Interface.
+	
+This class accesses and manages node setup features. These include:
+	- Loading Configuration files from your application
+	- Saving Configuration files
+**/
+class MN_EXPORT ISetup : public IObjWithNode
+{
+public:
+	/**
+		\brief Manage the delay to actual disable. 
+	
+		This allows an electrical brake to engage
+		prior to the actual disable. The units are milliseconds.
+
+		\see sFnd::IBrakeControl for more information on configuring, and controlling brakes
+
+		\CODE_SAMPLE_HDR
+		// SAMPLE: Getting and setting the delay to disable time.
+		myNode.Setup.DelayToDisableMsecs = 100.;				// Sets
+		double myDwell = myNode.Setup.DelayToDisableMsecs;	// Gets
+		\endcode
+	**/
+	ValueDouble DelayToDisableMsecs;
+
+	// Configuration Load/Save
+
+	/**
+		\brief Load configuration File.
+
+		\param[in] filePath Pointer to C-String file path to the file
+		to load.
+		\param[in] doReset Set this to true to force the node to reset
+		at the end of load.
+		
+		Load the configuration file specified by \a filePath to
+		this node.
+
+		\CODE_SAMPLE_HDR
+		// This function will load the Config file. You will have to edit the file path for your application
+		char* myconfigFile = "...\MyConfigFolder\MyConfigFile.mtr";
+		mynode.Setup.ConfigLoad(myconfigFile);
+		\endcode
+	**/
+	virtual void ConfigLoad(const char *filePath, bool doReset = false) = 0;
+
+	/**
+		\brief Save the node's configuration.
+		
+		\param[in] filePath Pointer to C-String file path to save the
+		configuration at.
+
+		Save the node's configuration to the \a filePath specified.  This would typically be performed through ClearView right after tuning each axis. 
+
+		\CODE_SAMPLE_HDR
+		//Save the config file before starting to the windows Temp file path
+		char tempPath[256];
+		GetTempPathA(256, tempPath);
+		char myconfigFile[269];
+		sprintf(myconfigFile, "%s\myConfig.mtr", tempPath);
+		mynode.Setup.ConfigSave(myconfigFile);
+		\endcode
+	**/
+	virtual void ConfigSave(const char *filePath) = 0;
+
+	/**
+		\brief Returns true if the node is in full access mode on this network.
+
+		Returns true if the node is in full access mode on this network.  
+		The only time a node may not be in full access mode is if ClearView is connected through the USB hub on the motor
+		and the user has taken Full Access through the USB diagnostic port via ClearView.
+
+		\CODE_SAMPLE_HDR
+		// This example will check to see if the application has full access to the Node
+		if(myNode.Setup.AccessLevelIsFull())
+		{ ...we have full access. Normal operation can continue...}
+		else
+		{ ...we don't have full access. Set ClearView to Monitor Mode before continuing...}
+		\endcode
+	**/
+	virtual bool AccessLevelIsFull() = 0;
+	/**
+		\brief Expert setup features access.
+	**/
+	ISetupEx Ex;
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction
+	ISetup(INode &ourNode,
+		nodeparam appPnum, nodeparam hwPnum, nodeparam wdogPnum,
+		nodeparam delayPnum);
+public:
+	virtual ~ISetup() {}
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IStatusAdv class
+/**
+	\brief Advanced Status Features Interface.
+
+	This class accesses and manages the advanced node status information.
+	It provides	access to:
+	- Capture Registers
+
+	\see \ref PosnCaptPage for information on configuring inputs to capture position
+**/
+class MN_EXPORT IStatusAdv : public IObjWithNode
+{
+public:
+	/**
+	\brief Access the last captured high resolution position value.
+
+	Access the last captured high resolution position value.
+
+	\note This input corresponds to a change of state of the Node's input A
+	**/
+	ValueSigned CapturedHiResPosn;
+	/**
+	\brief Return the last at sample-rate position captured.
+
+	Return the last at sample-rate position captured.
+
+	\note This input corresponds to a change of state of the Node's input A
+	**/
+	ValueSigned CapturedPos;
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction
+	IStatusAdv(INode &ourNode, nodeparam hiResCapPnum, nodeparam capPnum);
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	IStatus class
+/**
+	\brief Node Status Features Interface.
+
+	This Node Level class accesses and manages the node status information.  Node Status information is divided into 
+	two types of registers:
+	- Status Registers
+	- Alert/Shutdown Registers
+
+	Status Registers contain current information about the node's dynamic state such as whether a node: is
+	in motion, has gone move done, etc. The main Realtime Status Register is maintained by the node
+	and is updated each sample-time to reflect the node's state.  To reduce latency and allow the capture of 
+	short transient events, the Realtime Status Register feeds a series of accumulating registers. 
+	These registers store transitional events until they are accessed by the application program. These are:
+
+	- The deassertions are captured by the Status Fallen Register. 
+	- The assertions are captured by the Status Risen & Attention Source Register. This register is the source of the autonomous Attention Packets when enabled on "Advanced" motors. 
+	- The Status Accumulated Register is a bitwise OR accumulation of the Realtime Status Register. This register is useful for determining if an assertion has occurred since the last access. 
+
+	
+	The Alert Register contains information regarding a shutdown the Node may have experienced during normal operation.
+	Depending on the type of alert, the application may be able to recover and/or indentify the root cause of the failure.
+
+	Access to these registers is provided through the [ValueAlert](@ref sFnd::ValueAlert) and [ValueStatus](@ref sFnd::ValueStatus) classes.
+
+	\CODE_SAMPLE_HDR
+
+	//This example code will check a node's status for any current alerts and
+	//print out the state string of any alerts found
+
+	//This creates an Empty String for us to put our Alert State String into
+	char alertList[256];
+
+	// Refresh the Real-Time Status, and Alert Register
+	theNode.Status.RT.Refresh();
+	myNode.Status.Alerts.Refresh();
+
+
+	// Check the Real-Time Status Register's "AlertPresent" bit
+	// The bit is set true if there are alerts in the alert register
+	if (theNode.Status.RT.Value().cpm.AlertPresent)
+	{
+	printf("Node has alerts!\n");
+	}
+	else
+	{
+	printf("Node has no alerts!\n");
+	}
+
+	// get an alertReg reference, and check directly for alerts
+	if (myNode.Status.Alerts.Value().isInAlert())
+	{
+	// Put a text description of all alert bits set into our empty string, then print the string
+	myNode.Status.Alerts.Value().StateStr(alertList, 256);
+	printf("Node has alerts! Alerts: %s", alertList);
+
+	// Check for specific alerts by accessing the cpmAlertFlds within the alertReg Struct
+	if (myNode.Status.Alerts.Value().cpm.TrackingShutdown)
+	{
+	printf("Tracking Shutdown\n");
+	}
+	}
+
+	\endcode
+
+	\see sFnd::ValueAlert for more information on accessing the Node's Alert Register
+	\see sFnd::ValueStatus for more information on accessing the Node's Status Register
+	\see cpmStatusRegFlds for a complete list of ClearPath-SC Status Fields
+	\see cpmAlertFlds for a complete list of ClearPath-SC Alerts
+**/
+class MN_EXPORT IStatus : public IObjWithNode
+{
+public:
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Status Register Instances
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	/**
+		\brief Real Time Status Register Reference.
+
+		The <i>Real Time Status Register</i> reference 
+	**/
+	ValueStatus RT;
+
+	/**
+		\brief Status Risen Register Reference.
+
+		The <i>Status Risen Register</i> reference.
+	**/
+	ValueStatus Rise;
+
+	/**
+		\brief Status Fallen Register Reference.
+
+		The <i>Status Fallen Register</i> reference.
+	**/
+	ValueStatus Fall;
+
+	/**
+		\brief Status Accumulated Register Reference.
+
+		 The <i>Status Accumulated Register</i> reference.
+	**/
+	ValueStatus Accum;
+											/** \cond INTERNAL_DOC **/
+	/**
+		\brief Warnings Accumulated Register Reference.
+
+		Update and manage <i>Warnings Accumulated Register</i>.
+	**/
+	ValueAlert Warnings;
+											/** \endcond  **/
+
+	/**
+		\brief Alerts/Shutdowns Registers Reference.
+
+		The <i>Alerts/Shutdowns Register</i> reference.
+	**/
+	ValueAlert Alerts;
+
+	/**
+		\brief RMS level Reference.
+
+		A reference to the Node's <i>RMS Level</i>.
+	**/
+	ValueDouble RMSlevel;
+	
+	/**
+	\brief RMS level Reference.
+
+	A reference to the Node's bus and backup power status.
+	**/
+	ValuePowerReg Power;
+	
+	/**
+		\brief Advanced status information.
+
+		Access to extra status information only available in advanced ClearPath-SC nodes.
+	**/
+	IStatusAdv &Adv;
+public:
+	/**
+		\brief Clear non-serious alerts.
+
+		Clear all non-serious alerts and allow node to enable if an
+		<i>Enable Request</i> is still pending.
+	**/
+	virtual void AlertsClear() = 0;
+
+	/**
+		\brief If true, the node is ready for motion.
+		\return True if the node is ready for motion.
+
+		This function is used to determine the availability of the move
+		generator to begin operations.
+	**/
+	virtual bool IsReady() = 0;
+
+	/**
+	\brief If true, the node is ready for motion.
+	\return True if the node is ready for motion.
+
+	This function is used to determine if a Torque saturation event has
+	occurred since the last query. 
+	
+	\note The <i>Warnings</i> register is queried when this function is called
+	**/
+	virtual bool HadTorqueSaturation() = 0;
+
+
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction
+	IStatus(INode &ourNode, IStatusAdv &adv,
+		nodeparam rtPnum, nodeparam risePnum, nodeparam fallPnum, nodeparam accumPnum,
+		nodeparam warnPnum, nodeparam alertPnum, nodeparam rmsLvlPnum,
+		nodeparam powerPnum);
+public:
+	virtual ~IStatus() {}
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	INode class
+/**
+	\brief Virtual Node Interface.
+
+	This class defines a "super" node whose framework exposes the Node Level features
+	available for your application by a series of public attribute references.
+	There are common member functions for these feature objects to determine
+	if the node supports the feature.
+
+	This class also implements:
+	- Velocity Units
+	- Acceleration Units
+	- Torque Units
+	- Enable Requests
+
+
+	\CODE_SAMPLE_HDR
+		// Create instance of sFoundation
+		SysManager myMgr;
+		// Define a port SC4-HUB attached to
+		myMgr.ComHubPort(0, 13);
+		// Tell system to open this one port
+		myMgr.PortsOpen(1);
+		// Create useful reference to the first port object
+		IPort &myPort = myMgr.Ports(0);
+		// Test for presence of nodes
+		if (myPort.NodeCount() == 0) {
+			// Bail out, no nodes
+			return;
+		}
+		// If there are nodes present, get a reference to the first one
+		INode &myNode =  myPort.Nodes(0);
+		// You can now interact with myNode
+		myNode.EnableReq(true);
+	\endcode
+
+	\see sFnd::SysManager For the root object for interacting with
+	ClearPath-SC motors.
+	\see sFnd::SysManager::Ports To get references to the IPort objects created
+	when SysManager::PortsOpen has successfully opened.
+	\see sFnd::IPort::Nodes To get references to INode objects detected on a
+	port.
+**/
+class MN_EXPORT INode
+{
+													/** \cond INTERNAL_DOC **/
+	friend class IInfoEx;
+													/** \endcond **/
+public:
+	/**
+		\brief A Simple and Safe Mutex mechanism
+		
+		This mechanism is used to create critical sections of code when multiple 
+		threads are accessing a node, in order to perform read-modify-write 
+		operations by one of the threads, for example. An instance of this 
+		simplifies error handling whether node mutex is utilized.
+
+		\note This instance should generally be created in a C++ code block
+		that requires the node mutex. It must go out of scope before the
+		code stream after the mutually exclusive tasks are complete. This
+		ensures the release of the mutex in the case of operational failures
+		that causes the called function to throw an error.
+	
+		\CODE_SAMPLE_HDR
+		// This function will lock out any other parallel attempts to 
+		// access the node until it returns.
+		void myFuncWithLock(INode &myNode) {
+			// Lock is taken automatically
+			INode::UseMutex myLock(myNode);			
+
+			// Perform read-modify-write action
+
+			// Exiting this function guarantees unlock occurs
+		}
+		\endcode
+
+		\note Care should be taken to hold this instance as short as possible
+		to avoid starving competing threads from executing.
+	**/
+	class MN_EXPORT UseMutex {
+	private:
+		/// Hold a reference to our node class's internal mutex.
+		INode &m_node;
+	public:
+		/**
+			\brief Create a safe and simple mutex
+
+			\param[in,out] ourNode This is passed a reference to the node
+			you wish to perform the mutual exclusion on.
+		**/
+		UseMutex(INode &ourNode);
+													/** \cond INTERNAL_DOC **/
+		~UseMutex();
+													/** \endcond **/
+	};
+													/** \cond INTERNAL_DOC **/
+	/**
+		Internal event handler
+	**/
+	class MN_EXPORT MyEvent {
+	private:
+		// Hold a reference to our node class's internal mutex.
+		INode &m_node;
+		int32_t m_eventCount;
+	public:
+		MyEvent(INode &ourNode);
+		bool Wait(size_t timeoutMs);
+		void Signal();
+		void Register();
+		void Unregister();
+		int32_t Count();
+		void Reset(int32_t count);
+	};
+													/** \endcond **/
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Address of this node
+	multiaddr m_addr;
+													/** \endcond **/
+
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Acceleration unit handling
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+public:
+	/**
+		\brief Units for Accelerations parameters and status.
+	**/
+	enum _accUnits {
+		RPM_PER_SEC,	///< Revolutions/Minute/Second 
+		COUNTS_PER_SEC2	///< Counts/Second^2
+	};
+protected:
+													/** \cond INTERNAL_DOC **/
+	/**
+	Current unit storage.
+	**/
+	enum _accUnits m_AccUnit;
+													/** \endcond **/
+public:
+	/**
+		\brief Change the acceleration units
+
+		\param[in] newUnits Change the acceleration units to \a newUnits.
+
+		\CODE_SAMPLE_HDR
+		// Change the Units of Acceleration to RPM/Sec
+		mynode.AccUnit(mynode.RPM_PER_SEC);
+
+		// Change the Units of Acceleration to Cnts/sec/sec
+		mynode.AccUnit(mynode.COUNTS_PER_SEC2);
+		\endcode
+
+	**/
+	virtual void AccUnit(enum _accUnits newUnits) = 0;
+	/**
+		\brief Get the current acceleration units
+
+		\return Current acceleration unit
+	**/
+	enum _accUnits AccUnit() { return m_AccUnit; }
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Velocity unit handling
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+public:
+	/**
+		\brief Units for velocity parameters and status.
+	**/
+	enum _velUnits {
+		RPM,			///< Revolutions/Minute 
+		COUNTS_PER_SEC	///< Counts/Second
+	};
+protected:
+													/** \cond INTERNAL_DOC **/
+	/**
+		\brief Current unit storage.
+	**/
+	enum _velUnits m_VelUnit;
+													/** \endcond **/
+public:
+	/**
+		\brief Change the velocity units
+
+		\param[in] newUnits Set new velocity unit
+
+		\CODE_SAMPLE_HDR
+		// Change the Units of Velocity to RPM
+		mynode.VelUnit(mynode.RPM);
+
+		// Change the Units of Velocity to Cnts/Sec
+		mynode.VelUnit(mynode.COUNTS_PER_SEC);
+		\endcode
+
+
+	**/
+	virtual void VelUnit(enum _velUnits newUnits) = 0;
+	/**
+		\brief Get the current velocity units
+
+		\return Current velocity unit
+	**/
+	enum _velUnits VelUnit() { return m_VelUnit; }
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Torque unit handling
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+public:
+	/**
+		\brief Units for torque parameters and status.
+	**/
+	enum _trqUnits {
+		PCT_MAX,		///< Percentage of drive maximum
+		AMPS			///< Drive delivery amps
+	};
+protected:
+													/** \cond INTERNAL_DOC **/
+	/**
+		\Current unit storage.
+	**/
+	enum _trqUnits m_TrqUnit;
+													/** \endcond **/
+public:
+	/**
+		\brief Change the torque units
+
+		\param[in] newUnits New torque unit
+
+		\CODE_SAMPLE_HDR
+		// Change the Units of torque to percent of max
+		mynode.AccUnit(mynode.PCT_MAX);
+
+		// Change the Units of torque to Amps
+		mynode.AccUnit(mynode.AMPS);
+		\endcode
+	**/
+	virtual void TrqUnit(enum _trqUnits newUnits) = 0;
+	/**
+		\brief Get the current torque units
+
+		\return Current torque unit
+	**/
+	enum _trqUnits TrqUnit() { return m_TrqUnit; }
+
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	// Feature Access
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+public:
+	/**
+		\brief Get a reference to the port object this node is attached to.
+	**/
+	IPort &Port;
+	/**
+		\brief This reference allows for access about generic information
+		about a node.
+	**/
+	IInfo &Info;
+	/**
+		\brief Get a reference to the motion feature interface object
+	**/
+	IMotion &Motion;
+	/**
+		\brief Get a reference to the status information object
+	**/
+	IStatus &Status;
+	/**
+		\brief Get a reference to the limits feature object
+	**/
+	ILimits &Limits;
+															/** \cond INTERNAL_DOC **/
+	/**
+		\brief Get a reference to the outputs object
+	**/
+	IOuts &Outs;
+															/** \endcond **/
+	/**
+		\brief Get a reference to our Setup object
+	**/
+	ISetup &Setup;
+															/** \cond SC_EXPERT **/
+	/**
+		\brief Get a reference to our expert features object
+	**/
+	INodeEx &Ex;
+															/** \endcond **/
+	/**
+		\brief Get a reference to the advanced features object
+	**/
+	INodeAdv &Adv;
+
+	// Easy access to enable request
+	/**
+	\brief Thread safe enable request
+	\param[in] newState Change the state of the <i>Enable Request</i>.
+
+	This function allows you to assert the user <i>Enable Request</i>.  If <i>Enable Request</i>
+	is asserted the drive will enable unless an overriding disable nodeStop condition or a shutdown persists.
+	If a [shutdown, or nodestop](@ref CPMnodeStopPage) prevents the Node from enabling, then as soon as the condition is removed by 
+	[clearing the Nodestop](@ref sFnd::IMotion::NodeStopClear) or [clearing the alert](@ref sFnd::IStatus::AlertsClear)
+	The Node will immediately enable(there is no need to re-send the enable request).
+
+	**/
+	void EnableReq(bool newState) {
+		Outs.EnableReq(newState);
+	}
+	/**
+	\brief Get the current <i>Enable Request</i> state.
+
+	This function will return the state of the user <i>Enable Request</i>.
+
+	\note The Node may not be Enabled even if this request is asserted.  A [NodeStop](@ref CPMnodeStopPage), or [Shutdown Alert](@ref sFnd::ValueAlert)
+	can prevent the enable request from executing.
+
+	**/
+	bool EnableReq(){
+		return Outs.EnableReq();
+	}
+protected:
+													/** \cond INTERNAL_DOC **/
+	// Construction
+	INode(IPort &port, multiaddr theAddr,
+		IInfo &info, IMotion &motion, IStatus &status,
+		ILimits &limits, IOuts &outs, INodeAdv &adv, ISetup &setup,
+		INodeEx &ex);
+
+public:
+	// Destruct
+	virtual ~INode() {};
+	virtual void Refresh() {};
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	SysManager class 
+/**
+	\brief sFoundation Top Level System Object.
+
+	This class defines the manager object whose framework implements system level functions including:
+	- Functions to open, close, and restart ports in the system
+	- A thread safe system dwell
+	- The system timestamp
+	- Direct access to ports and nodes within the system
+
+	Only one instance of this object can be used in any application.
+
+	\CODE_SAMPLE_HDR
+	// Create instance of sFoundation
+	SysManager myMgr = SysManager::Instance();
+	// Define a port SC4-HUB attached to
+	myMgr->ComHubPort(0, 13);
+	// Tell system to open this one port
+	myMgr->PortsOpen(1);
+	// Access Node objects through the port
+	myMgr->Ports(0).Nodes(0);
+	\endcode
+
+	\see \ref sFnd::IPort to reference port level features
+	\see \ref sFnd::INode to reference node level features
+	\see \ref ClassOverviewPage for a high level overview of how these libraries interact
+**/
+class MN_EXPORT SysManager
+{
+public:
+	/**
+		\brief A  safe thread locking mechanism
+
+		This mechanism is used to allow debugging in a multi-threaded 
+		application. It locks a gate to prevent commands from being issued, 
+		then waits for all outstanding commands to finish and receive their 
+		responses from the Nodes. It then locks the mutex to the current thread, preventing 
+		other threads from executing. Doing this prevents response timeouts from 
+		occurring while stepping through code.
+
+		\note This instance should generally be created in a C++ code block
+		prior to a placed breakpoint within the same scope. When stepping 
+		through code, leaving the scope of where the ThreadLock was taken will unlock the other threads; 
+		possibly resulting in a timeout.
+
+		\note It may also be advisable when debugging to turn off the [watchdog timers](@ref sFnd::ISetupEx) for each Node.
+
+		\CODE_SAMPLE_HDR
+		// This example shows how you can use ThreadLocks in
+		// conjuction with breakpoints to debug your application.
+		void myFunction() {
+
+		<<<<<<  function code Here <<<<<<<<<<<<<<
+
+		// Insert this just before the Break point to lock other threads to prevent response timeouts
+		SysManager::ThreadLock lock;
+
+		<<<<  insert breakpoint Here <<<<<<<<
+
+		<<<<<< more function code Here <<<<<<<<<<<<<<
+		}
+		//Once the scope of the function is left, the ThreadLock is released allowing other Threads to function normally.
+		\endcode
+	**/
+	class MN_EXPORT ThreadLock {
+	public:
+		/**
+			\brief Create a safe and simple locking mutex to block other
+					threads from execution.
+		**/
+		ThreadLock();	
+													/** \cond INTERNAL_DOC **/
+		~ThreadLock();
+													/** \endcond **/
+	};
+													/** \cond INTERNAL_DOC **/
+private:
+	/*
+	Port Specifications
+	*/
+	portSpec m_ports[NET_CONTROLLER_MAX];
+	// Count specified from last PortsOpen call
+	size_t m_portOpenCount;
+
+	// Constructor
+	SysManager();
+
+	//Singleton Instance
+	static SysManager* _instance;
+													/** \endcond **/
+public:
+
+	
+	/**
+		\brief Search for ClearPath-SC COM Hubs on this machine
+
+		\param[out] comHubPorts This will hold a vector of strings 
+		which can later be passed to ComHubPort to open the given port(s).
+	**/
+	static void FindComHubPorts(std::vector<std::string>& comHubPorts);
+
+	#if defined(_WIN32)||defined(_WIN64)
+	/**
+		\brief Simplified setup for ClearPath-SC COM Hub
+
+		\param[in] netNumber This is the index of the port to setup. The first
+		port is numbered zero. The range of the netNumbers is from 0 to 2.
+		\param[in] portNumber This is Windows oriented port number. i.e.
+		COM1 would set \a portNumber = 1.
+		\param[in] portRate This is set to the desired network rate to operate
+		at. If using a SC-HUB, you can specify the speed as MN_BAUD_24X, else
+		you should use MN_BAUD_12X for 115200 fields/second ports typically
+		found on a PC motherboard.
+
+		This function is used to define the relationship between the system's
+		serial port number and the index number(netNumber) in your system.
+		\CODE_SAMPLE_HDR
+		// This example configures the first port(netNumber=0) to refer to windows COM5, using the default baud rate of 115200
+		myMgr.ComHubPort(0,5);
+
+		// This example configures the 2nd port(netNumber=1) to refer to windows COM10, using the higher baud rate of 230400
+		myMgr.ComHubPort(1,10,MN_BAUD_24X);
+		\endcode
+	**/
+	void ComHubPort(size_t netNumber,
+		int portNumber,
+		netRates portRate = MN_BAUD_12X);
+	#endif
+													/** \cond INTERNAL_DOC **/
+	void ComHubPort(size_t netNumber,
+		const char *portPath,
+		netRates portRate = MN_BAUD_12X);
+													/** \endcond **/
+													/** \cond INTERNAL_DOC **/
+	/**
+		\brief Get a reference to port's setup
+
+		\param[in] netNumber The index into the port table. The first port is
+		numbered zero. The valid range is [0...NET_CONTROLLER_MAX-1].
+
+		Returns the current settings for the specified port.
+	**/
+	portSpec &PortSetup(size_t netNumber);
+													/** \endcond **/
+
+	/**
+		\brief Open ports to start operations.
+
+		\param[in] portCount Number of ports specified
+
+		Call this function to start network operations after the ports have
+		been specified.
+
+		\note Ports should be assigned from 0 without skipping
+		any.
+
+		\CODE_SAMPLE_HDR
+		// Create our system instance
+		SysManager myMgr;
+		// Set the first port = COM10
+		myMgr.ComHubPort(0, 10);
+		// Set the second port = COM12
+		myMgr.ComHubPort(1, 12);
+		// Start system with two ports.
+		myMgr.PortsOpen(2);
+		\endcode
+
+		\see IPort::OpenState For information about starting success.
+		\see IPort::WaitForOnline To synchronize waiting for online state.
+	**/
+	void PortsOpen(size_t portCount);
+
+	/**
+		\brief Open ports to start operations.
+
+		\copydetails PortsOpen(size_t)
+	*/
+	void PortsOpen(int portCount);
+
+	/**
+		\brief Close all operations down and close the ports.
+
+		This function will close the serial ports in the system and release
+		all resources related to them.
+		
+		\note Any references to Ports, Nodes, or ValueXXXX parameters will no longer be valid after this function is called
+	**/
+	void PortsClose();
+
+	/**
+		\brief Close and re-open ports with node restarts and perform system 
+		initialization.
+		
+		This function will send a reset node command to restart them
+		to their powered-up state. The serial ports are re-inventoried for 
+		nodes and the SysManager refreshed for a new startup.
+
+		\note Any references to Ports, Nodes, or ValueXXXX parameters will no longer be valid after this function is called
+
+		\see IPort::OpenState For information about starting success.
+		\see IPort::WaitForOnline To synchronize waiting for online state.
+		**/
+	void RestartCold();
+
+	/**
+		\brief Close and re-open ports and perform system initialization.
+
+		This function will close and re-open the serial ports are 
+		re-inventoried for nodes and the SysManager refreshed for a new startup.
+
+		\note Any references to Ports, Nodes, or ValueXXXX parameters will no longer be valid after this function is called
+
+		\see IPort::OpenState For information about starting success.
+		\see IPort::WaitForOnline To synchronize waiting for online state.
+		**/
+	void RestartWarm();
+
+	/**
+		\brief Get a time-stamp.
+
+		\return High precision time-stamp
+
+		This time-stamp will have at least millisecond resolution. For the
+		Windows platform this is actually microsecond resolution.
+
+		\note This time stamp correlates to the time stamp in the [Command Trace](@ref sFnd::IPort::CommandTraceSave)  file.
+
+		\CODE_SAMPLE_HDR
+		//This example show how you can use the TimeStampMsec function to establish a reasonable timout for a polling loop.
+
+		 double timeout;
+        timeout = myMgr.TimeStampMsec() + TimeToWait;         //define a timeout in case the node is unable to enable
+
+        //This will loop checking on some status, and will timeout if the status is not found
+        while (!mynode.SomeStatus()) {
+            mynode.SomeStatus.Refresh();
+            if (myMgr.TimeStampMsec() > timeout) {
+                printf("Error: Timed out waiting for some status\n");
+                return -2;
+            }
+        }
+		\endcode
+
+	**/
+	double TimeStampMsec();
+
+	/**
+		\brief Format a std:string with a time-stamp string.
+
+		Updates \a toUpdString with a time-stamp string that correlates to
+		the [Command Trace](@ref sFnd::IPort::CommandTraceSave) feature.
+
+		\param[in,out] toUpdString Reference to string to update
+		\returns \a toUpdString the incoming string reference
+
+		\CODE_SAMPLE_HDR
+		// Create our system instance
+		SysManager myMgr;
+		// String to store results
+		string myString;
+		// Print time stamp to cout
+		cout << myMgr.TimeStampMsecStr(myString) << endl;
+		cout << myString << endl;
+		printf("%s\n", myString.c_str());
+		\endcode
+		**/
+	std::string &TimeStampMsecStr(std::string &toUpdString);
+
+	/**
+		\brief Format a std:string with a time-stamp string.
+
+		Returns a time-stamp string that correlates to
+		the [Command Trace](@ref sFnd::IPort::CommandTraceSave) feature.
+
+		\CODE_SAMPLE_HDR
+		// Create our system instance
+		SysManager myMgr;
+		// Print time stamp to cout
+		cout << myMgr.TimeStampMsecStr() << endl;
+		printf("%s\n", myMgr.TimeStampMsecStr().c_str());
+		\endcode
+
+	**/
+	std::string TimeStampMsecStr();
+
+	/**
+		\brief Suspend thread execution.
+
+		\param [in] msec Delay in milliseconds.
+
+		This calls the underlying operating system's thread suspension 
+		function to delay execution for this thread.
+
+		\CODE_SAMPLE_HDR
+		// Create our system instance
+		SysManager myMgr;
+		// Wait 100 milliseconds
+		cout << myMgr.TimeStampMsecStr() << endl;
+		myMgr.Delay(100);
+		cout << myMgr.TimeStampMsecStr() << endl;
+		\endcode
+	**/
+	void Delay(uint32_t msec);
+
+	/**
+		\brief Get reference to our port object.
+
+		\param[in] index The port index used when initializing the system.
+
+		This function is used to get a reference to the IPort object associated
+		with serial port. This would be the same as argument used with the 
+		SysManager::ComHubPort function.
+
+		\see SysManager::ComHubPort For setting up a serial port,
+	**/
+	IPort &Ports(size_t index);
+
+	/**
+		\brief Convert multi-address to an INode reference. 
+
+		\param[in] theMultiAddr This a system's internal node address.
+
+		The returned node reference may exist on any defined ports. 
+		
+		\remark A \ref _mnErr object is thrown if the requested address does not
+		exist in your system or the port currently is offline.
+
+		\CODE_SAMPLE_HDR
+		// Get a reference to a node from a specific address
+		// 0-15 correspond to Nodes on port 0
+		// 16-31 correspond to Nodes on port 1
+		// 32-47 correspond to Nodes on port 2
+		INode &mynode = myMgr.NodeGet(3);	// Get the 4th node on port 0
+		INode &mynode2 = myMgr.NodeGet(18); // Get the 3rd node on port 1
+		\endcode
+	**/
+	INode &NodeGet(multiaddr theMultiAddr);
+													/** \cond INTERNAL_DOC **/
+	//Destructor
+	~SysManager();
+
+	//Singleton accessor function
+	static SysManager* Instance();
+													/** \endcond **/
+};
+//																			  *
+//*****************************************************************************
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif
+
+
+//*****************************************************************************
+}  // namespace sFnd
+//*****************************************************************************
+#endif
+//============================================================================= 
+//	END OF FILE pubSysCls.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/tekTypes.h b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/tekTypes.h
new file mode 100644
index 000000000..3587d0898
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/inc/inc-pub/tekTypes.h
@@ -0,0 +1,467 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/inc/tekTypes.h $
+// $Revision: 77 $ $Date: 12/09/16 4:08p $
+// $Workfile: tekTypes.h $
+//
+// NAME
+//		tekTypes.h
+//
+// DESCRIPTION:
+/** \file
+	\brief Standardized types for Windows, QNX, Linux and DSP applications to 
+	insure properly sized data items across platforms.
+
+**/
+// CREATION DATE:
+//		05/17/2007 15:13:46
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2007-2018 Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+#ifndef __TEKTYPES_H__
+#define	__TEKTYPES_H__
+
+// Standard lib definitions
+#include <limits.h>
+#include <stdint.h>
+
+
+#if defined(_WIN32)||defined(_WIN64)&&!defined(__ASM_HEADER__)
+	#include <tchar.h>
+#endif
+
+#if !defined(__ASM_HEADER__)
+#ifdef __TI_COMPILER_VERSION__
+	#include "IQmathLib.h"
+#endif
+
+#ifndef ASM_CONST
+typedef unsigned long asmConst;
+#define ASM_CONST(x) ((unsigned long)(&x))
+#endif
+
+#endif
+
+//||||||||||||||||||||||||||||||||||||
+// Linux helper defines 
+//||||||||||||||||||||||||||||||||||||
+
+
+#if !(defined(_WIN32)||defined(_WIN64))&&!defined(__ASM_HEADER__)
+	#ifndef _CRT_WARN
+	#include <stdio.h>
+	#endif
+	#ifdef _DEBUG
+			#define _RPT0(f,a0) fprintf(f,a0)
+			#define _RPT1(f,a0,a1) fprintf(f,a0,a1)
+			#define _RPT2(f,a0,a1,a2) fprintf(f,a0,a1,a2)
+			#define _RPT3(f,a0,a1,a2,a3) fprintf(f,a0,a1,a2,a3)
+			#define _RPT4(f,a0,a1,a2,a3,a4) fprintf(f,a0,a1,a2,a3,a4)
+			#define _RPT5(f,a0,a1,a2,a3,a4,a5) fprintf(f,a0,a1,a2,a3,a4,a5)
+			#define _RPTF0(f,a0) fprintf(f,a0)
+			#define _RPTF1(f,a0,a1)fprintf(f,a0,a1)
+			#define _RPTF2(f,a0,a1,a2) fprintf(f,a0,a1,a2)
+	#else
+			#define _RPT0(f,a0)
+			#define _RPT1(f,a0,a1)
+			#define _RPT2(f,a0,a1,a2)
+			#define _RPT3(f,a0,a1,a2,a3)
+			#define _RPT4(f,a0,a1,a2,a3,a4)
+			#define _RPT5(f,a0,a1,a2,a3,a4,a5)
+			#define _RPTF0(f,a0)
+			#define _RPTF1(f,a0,a1)
+			#define _RPTF2(f,a0,a1,a2)
+	#endif
+	// Allow project re-direct
+	#ifndef _CRT_WARN
+		#define _CRT_WARN stderr
+	#endif
+	#ifndef _CRT_ERROR
+		#define _CRT_ERROR stderr
+	#endif
+	#ifndef _CRT_ASSERT
+		#define _CRT_ASSERT stdout
+	#endif
+#endif
+
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// TI header types mapped to platform equivalents.
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// This header will implement TI header typedefs if not included
+#if !(defined(DSP28_DATA_TYPES) || defined(_TI_STD_TYPES))
+	typedef int16_t             int16;
+	typedef int32_t             int32;
+	typedef uint16_t            Uint16;
+	typedef uint32_t            Uint32;
+	typedef int					Int;
+	typedef unsigned			Uns;
+	typedef char            	*String;
+	typedef void           		*Ptr;
+	#if !defined(DSP28_DATA_TYPES)
+		#define DSP28_DATA_TYPES
+	#endif
+	#if !defined(_TI_STD_TYPES)
+		#define _TI_STD_TYPES
+	#endif
+#endif
+
+typedef int_least8_t		int8;
+typedef uint_least8_t		Uint8;
+typedef uint64_t            Uint64;
+typedef int64_t         	int64;
+typedef float           	float32;
+typedef long double     	float64;
+/// Bit Field Type
+typedef Uint16 BFld;
+
+
+#ifndef FAR
+	#define FAR
+#endif
+
+
+#ifndef INT16_MAX
+#define INT16_MAX 32767
+#endif
+
+#ifndef INT32_MAX
+#define INT32_MAX 0x7FFFFFFF
+#endif
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Backward compatible definitions to ControlPoint library
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+typedef Uint32 nodeparam;		// Node parameter
+
+typedef Uint16 nodebool;		// Node boolean (VB boolean is 16-bits)
+typedef Uint16 nodeushort;
+typedef int16 nodeshort;
+typedef Uint32 nodeulong;		// Unsigned 32-bit item
+typedef int32 nodelong;			// Signed 32-bit item
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// String and character definitions
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+#if defined(_WIN32)||defined(_WIN64)
+	typedef char nodechar;			// "char" type
+	typedef char nodeuchar;
+	typedef char *nodeANSIstr;
+	typedef wchar_t* nodeUNIstr;	// Unicode string
+#else
+// ANSI style 8-bit character. Maybe >8 bits if platform does not support
+// octet addressing.
+	#ifdef __TMS470__
+		typedef int16 nodechar;		// "char" type
+		typedef int16 nodeuchar;	// A character/extra attributes
+	#else
+#if defined(__linux__)
+		typedef char nodechar;		// "char" type
+		typedef char nodeuchar;		// A character
+#else
+		typedef int8 nodechar;		// "char" type
+		typedef int8 nodeuchar;		// A character
+#endif
+	#endif
+	typedef char *nodeANSIstr;
+	typedef nodechar* nodeUNIstr;   // Unicode string
+	// Define Windows normal macro
+	#ifndef MAX_PATH
+	#define MAX_PATH 260
+	#endif
+#endif
+typedef nodechar *nodestr;			// String of nodechars
+
+
+// Basic link character which includes out of band
+// values such as break detected.
+typedef Uint16 linkChar;	
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Serial Classes assume Windows standard sizes, assign to our generic typedefs
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+#if !(defined(_WIN32)||defined(_WIN64))
+	#if defined(__cplusplus) && !defined(BOOL)
+		typedef bool BOOL;
+	#else
+		typedef int16 BOOL;
+	#endif
+	typedef int32_t LONG;
+	typedef int16_t WORD;
+	typedef int32_t DWORD;
+	typedef int64_t LONGLONG;
+	typedef uint32_t ULONG;
+	typedef uint16_t UINT;
+	typedef const nodechar * LPCTSTR;
+
+	#define _T (char *) 
+#endif
+
+// Quad Word Container for grabbing values at various
+// 16-bit locations.
+/// \cond	INTERNAL_DOC
+#if defined(__TMS320C2000__) || defined(__PICCOLO)
+typedef union _qTainer {
+	int64	i64;
+	struct _i32 {
+		Uint32	lsb;
+		int32	msb;
+	} i32;
+	struct _i16 {
+		Uint16	lsb;
+		Uint16  msb;
+		Uint16	usb;
+		int16   vsb;
+	} i16;
+} qTainer, nodequad;
+// Long Word Container for grabbing values at various
+// 16-bit locations.
+typedef union _lTainer {
+	int32	i32;
+	struct {
+		Uint16	lsb;
+		int16   msb;
+	} i16;
+} lTainer;
+#endif
+/// \endcond
+
+#if !defined(__ASM_HEADER__)
+	#if defined(__TMS320C2000__) || defined(__PICCOLO)
+		// DSP architectures
+		#define OCTET_SIZE(x) (sizeof(x)*2)
+	#else
+		// Byte oriented architectures
+		#define OCTET_SIZE(x) sizeof(x)
+	#endif
+#endif
+typedef int16					tBOOL;
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// IQmath mappings
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+// Short signed fixed-point values
+typedef int16					_iq15_s;
+typedef int16					_iq14_s;
+typedef int16					_iq13_s;
+typedef int16					_iq12_s;
+typedef int16					_iq11_s;
+typedef int16					_iq10_s;
+typedef int16					_iq9_s;
+typedef int16					_iq8_s;
+typedef int16					_iq7_s;
+typedef int16					_iq6_s;
+typedef int16					_iq5_s;
+typedef int16					_iq4_s;
+typedef int16					_iq3_s;
+typedef int16					_iq2_s;
+typedef int16					_iq1_s;
+
+// Short unsigned fixed-point values
+typedef Uint16					_iq16_su;
+typedef Uint16					_iq15_su;
+typedef Uint16					_iq14_su;
+typedef Uint16					_iq13_su;
+typedef Uint16					_iq12_su;
+typedef Uint16					_iq11_su;
+typedef Uint16					_iq10_su;
+typedef Uint16					_iq9_su;
+typedef Uint16					_iq8_su;
+typedef Uint16					_iq7_su;
+typedef Uint16					_iq6_su;
+typedef Uint16					_iq5_su;
+typedef Uint16					_iq4_su;
+typedef Uint16					_iq3_su;
+typedef Uint16					_iq2_su;
+typedef Uint16					_iq1_su;
+
+typedef int32					_iq31;					// (1.31) fixed-point number
+// Long fixed-point values
+typedef int64				    _iq17_l;				// (47.17) variable [15.17 as LSBs]
+typedef int64					_iq27_l;
+typedef int64					_iq34_l;
+
+#if !defined(__ASM_HEADER__)
+// Create missing long Q constants
+#define	  _IQ31(A)		  (int32) ((A) * 2147483648.0L)
+
+// Create short Q constants
+#define   _IQ15_S(A)      (int16) ((A) * 32768.0L)
+#define   _IQ14_S(A)      (int16) ((A) * 16384.0L)
+#define   _IQ13_S(A)      (int16) ((A) * 8192.0L)
+#define   _IQ12_S(A)      (int16) ((A) * 4096.0L)
+#define   _IQ11_S(A)      (int16) ((A) * 2048.0L)
+#define   _IQ10_S(A)      (int16) ((A) * 1024.0L)
+#define   _IQ9_S(A)       (int16) ((A) * 512.0L)
+#define   _IQ8_S(A)       (int16) ((A) * 256.0L)
+#define   _IQ7_S(A)       (int16) ((A) * 128.0L)
+#define   _IQ6_S(A)       (int16) ((A) * 64.0L)
+#define   _IQ5_S(A)       (int16) ((A) * 32.0L)
+#define   _IQ4_S(A)       (int16) ((A) * 16.0L)
+#define   _IQ3_S(A)       (int16) ((A) * 8.0L)
+#define   _IQ2_S(A)       (int16) ((A) * 4.0L)
+#define   _IQ1_S(A)       (int16) ((A) * 2.0L)
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef VB_TRUE
+#define VB_TRUE ((nodebool)-1)
+#endif
+
+#ifndef VB_FALSE
+#define VB_FALSE ((nodebool)0)
+#endif
+
+#ifndef NULL 
+#define NULL 0
+#endif
+
+#ifndef NULL_FUNC 
+#define NULL_FUNC ((void (*)())0)
+#endif
+
+#ifndef __cplusplus
+typedef FAR void *romPtr;
+#else
+typedef void *romPtr;
+#endif
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Linkages and calling convention definitions
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+#if !(defined(_WIN32)||defined(_WIN64)) || defined(__ASM_HEADER__) || defined(__TI_COMPILER_VERSION__)
+	#ifndef EXTERN_C
+		#ifdef __cplusplus
+			#define EXTERN_C extern "C"
+		#else
+			#define EXTERN_C extern
+		#endif
+	#endif	// EXTERN_C
+	// Ignore on non-Windows platforms
+	#ifndef MN_EXPORT
+		#define MN_EXPORT
+	#endif
+	#ifndef MN_DECL
+		#define MN_DECL
+	#endif
+	#ifndef CALLBACK 
+		#define CALLBACK
+	#endif
+	typedef int16 WCHAR;
+#else
+	// Windows C DLL Linkage hack
+	#define	MN_DECL __stdcall
+	#ifdef _DLL
+		#define MN_EXPORT __declspec(dllexport)
+	#else
+		#define MN_EXPORT __declspec(dllimport)
+	#endif
+
+	#ifndef CALLBACK
+		#define CALLBACK __stdcall
+	#endif
+	typedef wchar_t WCHAR;
+#endif
+
+// prevent declaration type issues with shared files
+#if defined(__ASM_HEADER__)
+#undef EXTERN_C
+#define EXTERN_C
+#endif
+// Function signature macro defines
+#if defined(_MSC_VER)
+#define _TEK_FUNC_SIG_	__FUNCSIG__
+#elif defined(__GNUC__)
+#define _TEK_FUNC_SIG_	__PRETTY_FUNCTION__
+#endif
+// Useful for checking constant assertions
+#ifdef __TI_COMPILER_VERSION__
+	#define STATIC_ASSERT(e) { extern char assert_static__[(e) ? 1 : -1]; }
+#else
+	#define STATIC_ASSERT(e)
+#endif
+// Useful macros that generate good code
+#if !defined(_MIN) && !defined(__ASM_HEADER__)
+	#define _MIN(a,b) (a < b) ? a : b
+#endif
+
+#if !defined(_MAX) && !defined(__ASM_HEADER__)
+	#define _MAX(a,b) (a > b) ? a : b
+#endif
+
+// Packing control to force structure alignments to byte boundaries
+// Order of definitions is important for cases where multiple conditions may be true
+#ifdef PACK_BYTES
+#error "PACK_BYTES already defined"
+#endif
+
+#ifdef __DOXYGEN__
+#define PACK_BYTES
+#endif
+
+#if (defined(__TI_COMPILER_VERSION__) || defined(__ASM_HEADER__)) && !defined(PACK_BYTES)
+#define PACK_BYTES
+#endif
+
+#if defined(_MSC_VER) && !defined(PACK_BYTES)
+#ifdef __cplusplus_cli
+#define PACK_BYTES
+#else
+#define PACK_BYTES 
+#endif
+#endif
+
+#if defined(__GNUC__) && !defined(PACK_BYTES)
+#define PACK_BYTES __attribute__((aligned(1)))
+#endif
+
+#ifndef PACK_BYTES
+// Make sure PACK_BYTES has been explicitly defined
+#error "Please define PACK_BYTES for this platform"
+// Suppress additional errors for PACK_BYTES not being known by defining it to do nothing
+#define PACK_BYTES
+#endif
+
+//// Windows STL exports
+//#if defined(_MSC_VER)
+//#ifdef EXP_STL
+//#    define DECLSPECIFIER __declspec(dllexport)
+//#    define EXPIMP_TEMPLATE
+//#else
+//#    define DECLSPECIFIER __declspec(dllimport)
+//#    define EXPIMP_TEMPLATE extern
+//#endif
+//#else
+//	// Non-Windows
+//#    define DECLSPECIFIER
+//#    define EXPIMP_TEMPLATE
+//#endif
+
+// CALLBACK DEFINITION
+#if defined(_WIN32)||defined(_WIN64)
+#define nodeCallback __stdcall 
+#else
+#define nodeCallback
+#endif
+
+
+#endif	// __TEKTYPES_H__
+//=============================================================================
+//	END OF FILE tekTypes.h
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/MNuserDriver20.xml b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/MNuserDriver20.xml
new file mode 100644
index 000000000..366378176
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/MNuserDriver20.xml
@@ -0,0 +1,617 @@
+<?xml version="1.0"?>
+<definitions>
+	<def key="8000">&lt;unknown parameter&gt;</def>
+	<def key="8001">&lt;out of range&gt;</def>
+	<def key="8002">Device ID</def>
+	<def key="8003">Firmware Version</def>
+	<def key="8004">Hardware Version</def>
+	<def key="8005">Reseller ID</def>
+	<def key="8006">Serial Number</def>
+	<def key="8007">Options Register</def>
+	<def key="8008">Firmware Update Acknowledge</def>
+	<def key="8009">Firmware Checksum</def>
+	<def key="8010">Sample Period</def>
+	<def key="8011">Op. State Register</def>
+	<def key="8012">Node Stop Type</def>
+	<def key="8013">Watchdog Time Constant</def>
+	<def key="8014">User Identification</def>
+	<def key="8072">User Identification(ext)</def>
+	<def key="8015">Status Register</def>
+	<def key="8071">Run-Time Error Code</def>
+	<def key="8016">Status Register (realtime)</def>
+	<def key="8017">Status Rise/Attn Register</def>
+	<def key="8081">Status Fall Register</def>
+	<def key="8018">Attention Mask Register</def>
+	<def key="8019">Node Time</def>
+	<def key="8020">Node Time (long)</def>
+	<def key="8021">Configuration Options</def>
+	<def key="8022">Input Register</def>
+	<def key="8023">Input Rising Edge Latch</def>
+	<def key="8024">Input Falling Edge Latch</def>
+	<def key="8025">Input Transition Latch</def>
+	<def key="8026">Input Source Definition</def>
+	<def key="8027">User Input Register</def>
+	<def key="8028">Output Register</def>
+	<def key="8029">Output Rising Edge Latch</def>
+	<def key="8030">Output Falling Edge Latch</def>
+	<def key="8031">Output Transition Latch</def>
+	<def key="8032">Input Polarity Register</def>
+	<def key="8033">User Output Register</def>
+	<def key="8034">Output PLA Source</def>
+	<def key="8035">GP timer period</def>
+	<def key="8036">PLA Output Register</def>
+	<def key="8037">Input Polarity Register</def>
+	<def key="8038">Measured Position</def>
+	<def key="8039">Index Position Capture</def>
+	<def key="8040">GPI 00 Position Capture</def>
+	<def key="8041">PLA Position Capture</def>
+	<def key="8042">Set of Param. to Poll</def>
+	<def key="8043">Poll Parameter Register</def>
+	<def key="8044">Velocity Limit</def>
+	<def key="8045">Acceleration Limit</def>
+	<def key="8046">Test param #9</def>
+	<def key="8047">Interrupt Mask</def>
+	<def key="8407">Index Position Capture (load)</def>
+	<def key="8408">Measured Position (load)</def>
+	<def key="8048">RAS™ Jerk Limit</def>
+	<def key="8049">Attention Register</def>
+	<def key="8050">Polled Node List</def>
+	<def key="8051">Position Trigger Point</def>
+	<def key="8052">A after Start</def>
+	<def key="8053">B before End</def>
+	<def key="8054">Tracking Range</def>
+	<def key="8055">Commanded Position</def>
+	<def key="8056">Position Error</def>
+	<def key="8057">Pulse/Encoder Ratio</def>
+	<def key="8058">Stop Acceleration Limit</def>
+	<def key="8059">Measured Position (int)</def>
+	<def key="8060">Commanded Position (int)</def>
+	<def key="8061">Commanded Velocity</def>
+	<def key="8062">Measured Velocity</def>
+	<def key="8063">Deceleration Limit</def>
+	<def key="8085">Measured Motor Position (int)</def>
+	<def key="8086">Coupling Error</def>
+	<def key="8087">Software Limit Position Positive</def>
+	<def key="8088">Software Limit Position Negative</def>
+	<def key="8089">Repeating Move Dwell</def>
+	<def key="8090">Homing Acceleration</def>
+	<def key="8091">RAS Delay</def>
+	<def key="8092">Maximum travel from home</def>
+	<def key="8093">Hardstop delay time</def>
+	<def key="8094">Velocity Limit Max</def>
+	<def key="8095">Acceleration Limit Max</def>
+	<def key="8096">Stop Acceleration Limit Max</def>
+	<def key="8097">Motor Inertia</def>
+	<def key="8098">Motor Static Friction</def>
+	<def key="8099">Motor Viscous Friction</def>
+	<def key="8064">Head Distance</def>
+	<def key="8065">Tail Distance</def>
+	<def key="8066">Head/Tail Velocity Limit</def>
+	<def key="8067">Velocity Glitch</def>
+	<def key="8068">Position Glitch</def>
+	<def key="8069">Maximum Acceleration</def>
+	<def key="8070">Number of Stray Characters</def>
+	<def key="8100">Poll Priority List</def>
+	<def key="8101">Maximum Ring Poll</def>
+	<def key="8102">Current Ring Poll</def>
+	<def key="8103">Number of Packets/Bad Checksum </def>
+	<def key="8104">Number of Fragmented Packets</def>
+	<def key="8105">Number of Packets Sent</def>
+	<def key="8106">Number of Packets Received</def>
+	<def key="8107">Number of SOF Sent</def>
+	<def key="8108">Number of SOF Received</def>
+	<def key="8109">Number of Interrupts Received</def>
+	<def key="8110">Number of Attn. Req. Received</def>
+	<def key="8200">Acquisition Parameters</def>
+	<def key="8201">DigiLog Thresholds 0</def>
+	<def key="8202">DigiLog Thresholds 1</def>
+	<def key="8203">DigiLog Thresholds 2</def>
+	<def key="8204">DigiLog Thresholds 3</def>
+	<def key="8205">DigiLog Thresholds 4</def>
+	<def key="8206">DigiLog Thresholds 5</def>
+	<def key="8207">DigiLog Thresholds 6</def>
+	<def key="8208">DigiLog Thresholds 7</def>
+	<def key="8209">DigiLog Thresholds 8</def>
+	<def key="8210">DigiLog Thresholds 9</def>
+	<def key="8211">DigiLog Thresholds 10</def>
+	<def key="8212">DigiLog Thresholds 11</def>
+	<def key="8213">DigiLog Filter 0</def>
+	<def key="8214">DigiLog Filter 1</def>
+	<def key="8215">DigiLog Filter 2</def>
+	<def key="8216">DigiLog Filter 3</def>
+	<def key="8217">DigiLog Filter 4</def>
+	<def key="8218">DigiLog Filter 5</def>
+	<def key="8219">DigiLog Filter 6</def>
+	<def key="8220">DigiLog Filter 7</def>
+	<def key="8221">DigiLog Filter 8</def>
+	<def key="8222">DigiLog Filter 9</def>
+	<def key="8223">DigiLog Filter 10</def>
+	<def key="8224">DigiLog Filter 11</def>
+	<def key="8225">DigiLog Input 0</def>
+	<def key="8226">DigiLog Input 1</def>
+	<def key="8227">DigiLog Input 2</def>
+	<def key="8228">DigiLog Input 3</def>
+	<def key="8229">DigiLog Input 4</def>
+	<def key="8230">DigiLog Input 5</def>
+	<def key="8231">DigiLog Input 6</def>
+	<def key="8232">DigiLog Input 7</def>
+	<def key="8233">DigiLog Input 8</def>
+	<def key="8234">DigiLog Input 9</def>
+	<def key="8235">DigiLog Input 10</def>
+	<def key="8236">DigiLog Input 11</def>
+	<def key="8237">Bipolar Offset 10</def>
+	<def key="8238">Bipolar Offset 11</def>
+	<def key="8239">+5V Supply</def>
+	<def key="8240">+12V Supply</def>
+	<def key="8241">Analog Max/Min Select</def>
+	<def key="8242">Analog Max</def>
+	<def key="8243">Analog Min</def>
+	<def key="8244">Test Input</def>
+	<def key="8245">Test Output</def>
+	<def key="8246">Number of Fragmented Packets</def>
+	<def key="8247">Number of Badly Checksumed Packets</def>
+	<def key="8248">Number of Stray Characters</def>
+	<def key="8249">Output Register (IEX)</def>
+	<def key="8250">Input Register (IEX)</def>
+	<def key="8251">Default Output Register (IEX)</def>
+	<def key="8252">Input Rise Register (IEX)</def>
+	<def key="8253">Input Fall Register (IEX)</def>
+	<def key="8254">User Output Request (IEX)</def>
+	<def key="8255">User Non-Volatile 0</def>
+	<def key="8256">User Non-Volatile 1</def>
+	<def key="8257">User Non-Volatile 2</def>
+	<def key="8258">User Non-Volatile 3</def>
+	<def key="8259">User Volatile 0</def>
+	<def key="8260">Shutdown History Index</def>
+	<def key="8261">Shutdown History Item</def>
+	<def key="8262">Hardware Configuration Register</def>
+	<def key="8263">Application Configuration Register</def>
+	<def key="8264">Tuning Configuration Register</def>
+	<def key="8111">Part Number</def>
+	<def key="8112">Configuration Update Acknowledge</def>
+	<def key="8113">Configuration Version</def>
+	<def key="8082">Link Status</def>
+	<def key="8426">Powered On Time</def>
+	<def key="8427">Controlled Stop Output Register</def>
+	<def key="8114">App Channel Checksum Error Count</def>
+	<def key="8115">App Channel Fragment Error Count</def>
+	<def key="8116">App Channel Stray Error Count</def>
+	<def key="8117">App Channel Overrun Error Count</def>
+	<def key="8118">Diagnostic Channel Checksum Error Count</def>
+	<def key="8119">Diagnostic Channel Fragment Error Count</def>
+	<def key="8120">Diagnostic Channel Stray Error Count</def>
+	<def key="8121">Diagnostic Channel Overrun Error Count</def>
+	<def key="8440">Network Power Brown Out Count</def>
+	<def key="8441">Bad TSPD Event Count</def>
+	<def key="8442">Bad Slot Event Count</def>
+	<def key="8443">Slot 0 loading</def>
+	<def key="8444">Slot 1 loading</def>
+	<def key="8445">Slot 2 loading</def>
+	<def key="8446">Slot 3 loading</def>
+	<def key="8447">Average loading</def>
+	<def key="8448">Reference Supply</def>
+	<def key="8510">User Description (0)</def>
+	<def key="8511">User Description (1)</def>
+	<def key="8512">User Description (2)</def>
+	<def key="8513">User Description (2)</def>
+	<def key="8514">User Description (4)</def>
+	<def key="8122">Input A (high-speed) Position Capture</def>
+	<def key="8123">Input B Position Capture</def>
+	<def key="8300">Vector Update Rate</def>
+	<def key="8301">Encoder Density</def>
+	<def key="8302">Motor Poles</def>
+	<def key="8303">Motor Torque/Force Constant [Ke]</def>
+	<def key="8326">Command Unit Density</def>
+	<def key="8304">Motor Ph-Ph Resistance</def>
+	<def key="8305">Motor Electrical Time Constant</def>
+	<def key="8306">Reference Offset</def>
+	<def key="8307">Max. Continuous (RMS) Motor Current</def>
+	<def key="8308">Max. Time @ 100% Output</def>
+	<def key="8382">RMS initial level on reset</def>
+	<def key="8309">Mtr. Encoder Max. Freq.</def>
+	<def key="8310">Commutation Edge Capture</def>
+	<def key="8311">Commutation Angle</def>
+	<def key="8312">Kip</def>
+	<def key="8313">Kii</def>
+	<def key="8315">Kv</def>
+	<def key="8316">Kp</def>
+	<def key="8314">Kpl</def>
+	<def key="8317">Ki</def>
+	<def key="8318">Kfv</def>
+	<def key="8319">Kfa</def>
+	<def key="8320">Kfj</def>
+	<def key="8321">Kff</def>
+	<def key="8322">Knv</def>
+	<def key="8323">Kr</def>
+	<def key="8325">Torque/Force Bias</def>
+	<def key="8327">Monitor 0-Amplitude</def>
+	<def key="8328">Monitor 0-Variable</def>
+	<def key="8329">Monitor 0-Filter</def>
+	<def key="8330">Monitor 1-Amplitude</def>
+	<def key="8331">Monitor 1-Variable</def>
+	<def key="8332">Monitor 1-Filter</def>
+	<def key="8392">Knv(Anti-Hunt)</def>
+	<def key="8425">AntiHunt 2</def>
+	<def key="8334">Torque/Force Limit</def>
+	<def key="8335">Negative Torque Limit</def>
+	<def key="8336">Tracking Error Limit</def>
+	<def key="8432">Coupling Error Limit</def>
+	<def key="8337">Move Done Time Const.</def>
+	<def key="8338">Logic Power Backup Recovery Window</def>
+	<def key="8339">Delay-Power-up to Ready</def>
+	<def key="8340">Delay-Power-up to Servo</def>
+	<def key="8341">Torque/Force Foldback Level</def>
+	<def key="8342">Hard Stop - Threshold</def>
+	<def key="8343">Hard Stop - Qualify Time</def>
+	<def key="8344">Relax Time</def>
+	<def key="8345">Bus Voltage</def>
+	<def key="8346">Maximum Output Current</def>
+	<def key="8347">Maximum Drive RMS</def>
+	<def key="8348">Longest Drive RMS TC</def>
+	<def key="8349">Analog Input Test Point</def>
+	<def key="8350">I/O Testpoint</def>
+	<def key="8351">R Channel Testpoint</def>
+	<def key="8352">S Channel Testpoint</def>
+	<def key="8353">Encoder Resolution</def>
+	<def key="8354">Heatsink Temperature</def>
+	<def key="8355">Configuration Changes</def>
+	<def key="8356">Drive Configuration</def>
+	<def key="8357">Fuzzy Aperture</def>
+	<def key="8358">Fuzzy Hysteresis</def>
+	<def key="8359">RMS Level</def>
+	<def key="8360">Torque/Force Foldback Level (neg)</def>
+	<def key="8361">Heatsink Temperature</def>
+	<def key="8362">Drive Status (accum)</def>
+	<def key="8380">Drive Status (real-time)</def>
+	<def key="8363">Torque/Force Foldback Level (pos)</def>
+	<def key="8364">Positive Torque Limit</def>
+	<def key="8365">5V Testpoint</def>
+	<def key="8366">16V Testpoint</def>
+	<def key="8367">IBUS Testpoint</def>
+	<def key="8368">Extended Configuration</def>
+	<def key="8369">R Sensor calibration</def>
+	<def key="8370">S Sensor calibration</def>
+	<def key="8493">Bus voltage calibration</def>
+	<def key="8371">VBUS Testpoint</def>
+	<def key="8372">Torque/Force Commanded</def>
+	<def key="8373">Torque/Force Measured</def>
+	<def key="8374">Positive Torque/Force Foldback Release Time</def>
+	<def key="8375">Negative Torque/Force Foldback Release Time</def>
+	<def key="8376">Hard-stopped Torque/Force Foldback Release Time</def>
+	<def key="8377">Hard-stopped Torque/Force Foldback</def>
+	<def key="8378">Move Done Torque/Force Foldback</def>
+	<def key="8379">Move Done Torque/Force Foldback Release Time</def>
+	<def key="8496">Clamping Torque/Force Foldback</def>
+	<def key="8497">Clamping Torque/Force Foldback Release Time</def>
+	<def key="8073">ADC maximum scale</def>
+	<def key="8074">Flow Control In Test Point</def>
+	<def key="8075">Flow Control Out Test Point</def>
+	<def key="8388">Commutation Sensorless Startup Torque/Force</def>
+	<def key="8389">Hard-stop Qualify Velocity</def>
+	<def key="8390"></def>
+	<def key="8391"></def>
+	<def key="8076">R Sensor Reading(filtered)</def>
+	<def key="8077">S Sensor Reading(filtered)</def>
+	<def key="8078">Warning Register</def>
+	<def key="8079">Warning Mask Register</def>
+	<def key="8080">Alert Mask Register</def>
+	<def key="8083">Warning Register (accumulating)</def>
+	<def key="8084">Max. Accel Used</def>
+	<def key="8494">Ref. Supply (adjust)</def>
+	<def key="8495">Bus Supply (adjust)</def>
+	<def key="8498">Encoder Alignment Register</def>
+	<def key="8499">Min Sensor-less Bus V</def>
+	<def key="8500">Min Sensor-less I</def>
+	<def key="8501">Max Sensor-less I</def>
+	<def key="8502">Min Sensor-less phase I</def>
+	<def key="8503">Max non-dominant phase I diff</def>
+	<def key="8504">Ir Offset</def>
+	<def key="8505">Is Offset</def>
+	<def key="8265">Bus @ Enable</def>
+	<def key="8516">Maximum Torque/Force during Hardstop</def>
+	<def key="8518">Communications Only Mode voltage</def>
+	<def key="8383">Safety Status</def>
+	<def key="8384">Last Safety Status</def>
+	<def key="8385">Output Request Register</def>
+	<def key="8386">Fan Speed</def>
+	<def key="8387">Fan Speed (minimum)</def>
+	<def key="8409">Heatsink temp simulation</def>
+	<def key="8410">Km Factor</def>
+	<def key="8411">Km Min R</def>
+	<def key="8412">Fan On Temp</def>
+	<def key="8413">Part Identifier</def>
+	<def key="8414">Ibus RMS Time Constant</def>
+	<def key="8415">Ibus Shutdown Limit</def>
+	<def key="8416">Phase Over-Current Limit</def>
+	<def key="8417">Ibus (peak)</def>
+	<def key="8418">Ibus Level</def>
+	<def key="8419">PWBA temp</def>
+	<def key="8420">Ir/Is TP Filter</def>
+	<def key="8422">Maximum Tracking Error</def>
+	<def key="8421">Maximum Tracking Error</def>
+	<def key="8423">Anti-Hunt Holdoff</def>
+	<def key="8381">Ld. Encoder Max. Freq.</def>
+	<def key="8424">Servo TSPD</def>
+	<def key="8428">Stepper running torque</def>
+	<def key="8429">Stepper idle torque</def>
+	<def key="8430">Stepper accel torque</def>
+	<def key="8431">Stepper Torque/Force change time constant</def>
+	<def key="8433">Microsteps per turn</def>
+	<def key="8434">Comm Check Angle Limit</def>
+	<def key="8435">Sensorless Startup Torque/Force Rampup Time</def>
+	<def key="8436">Sensorless Startup Torque/Force Sweep Time</def>
+	<def key="8437">Sensorless Startup Torque/Force Settle Time</def>
+	<def key="8438">Torque/Force Request Filter Time Constant</def>
+	<def key="8439">Anti-Hunt gain</def>
+	<def key="8449">Kzero</def>
+	<def key="8450">Izero</def>
+	<def key="8451">Target Window</def>
+	<def key="8452">Stability Window</def>
+	<def key="8453">Enable Input Qualification</def>
+	<def key="8454">Enable Pulse Qualification</def>
+	<def key="8455">Input B Qualification</def>
+	<def key="8456">Input AND/OR Mask Register</def>
+	<def key="8507">Input A Qualification</def>
+	<def key="8406"> (IEX)</def>
+	<def key="8393">User Output Request (IEX)</def>
+	<def key="8394">Inputs Risen (IEX)</def>
+	<def key="8395">Inputs Fallen (IEX)</def>
+	<def key="8396">Node Stop Default (IEX)</def>
+	<def key="8400">Glitch Tolerance Limit (IEX)</def>
+	<def key="8403">Status Register (IEX)</def>
+	<def key="8404">Inputs Risen Attention Mask (IEX)</def>
+	<def key="8405">Inputs Fallen Attention Mask (IEX)</def>
+	<def key="8399">Inputs Attention Mask (IEX)</def>
+	<def key="8397">Output Reg. (IEX)</def>
+	<def key="8398">Input Reg. (IEX)</def>
+	<def key="9000">quad. count</def>
+	<def key="9001">us</def>
+	<def key="9002">ms</def>
+	<def key="9003">s</def>
+	<def key="9004">K ticks/s</def>
+	<def key="9005">M ticks/s</def>
+	<def key="9006">K ticks/s/s</def>
+	<def key="9007">K ticks/sample T</def>
+	<def key="9008">M ticks/sample T</def>
+	<def key="9009">K ticks/sample T^2</def>
+	<def key="9010">sample times</def>
+	<def key="9011">position units</def>
+	<def key="9012">velocity units</def>
+	<def key="9013">Hz</def>
+	<def key="9014">micron</def>
+	<def key="9015">Ohms</def>
+	<def key="9016">degrees (elect.)</def>
+	<def key="9017">Volts</def>
+	<def key="9018">Amperes</def>
+	<def key="9019">% of max</def>
+	<def key="9020">degrees(C)</def>
+	<def key="9021">RPM</def>
+	<def key="9022">hours</def>
+	<def key="20000">OK</def>
+	<def key="20001">Function failed.</def>
+	<def key="20002">Failed due to time-out</def>
+	<def key="20003">Packet checksum error.</def>
+	<def key="20004">Device selected is out of range</def>
+	<def key="20005">There are too many nodes on the link.</def>
+	<def key="20006">Response is garbled.</def>
+	<def key="20007">Response is from wrong node.</def>
+	<def key="20008">Node is offline.</def>
+	<def key="20009">Parameter is out of range.</def>
+	<def key="20010">Memory is low.</def>
+	<def key="20011">Operating System Error: %d.</def>
+	<def key="20012">Attempting to use a closed Link Controller.</def>
+	<def key="20013">Value requested is invalid.</def>
+	<def key="20014">Command packet error.</def>
+	<def key="20015">Attempting to use an unknown node.</def>
+	<def key="20016">Time-out waiting for command access</def>
+	<def key="20017">Packet length != buffer length.</def>
+	<def key="20018">RX buffer overflow.</def>
+	<def key="20019">RX buffer access/sync problem.</def>
+	<def key="20020">Feature not implemented.</def>
+	<def key="20021">Port(s) failed to open, already open, or non-existent.</def>
+	<def key="20022">TX Buffer full</def>
+	<def key="20023">Can't command in serial port mode.</def>
+	<def key="20024">Parameter Database not initialized.</def>
+	<def key="20025">Initialization tests incomplete due to lack of diagnostic firmware.</def>
+	<def key="20026">Interrupt interface appears broken.</def>
+	<def key="20027">Command attempt while link offline.</def>
+	<def key="20028">Address is locked</def>
+	<def key="20029">Resource to complete command is busy</def>
+	<def key="20030">Attention FIFO over-run</def>
+	<def key="20031">Initialization tests incomplete due to old firmware/further errors.</def>
+	<def key="20032">Repeat-Move Time Limit Exceeded:  Use a script for moves &gt;8 seconds</def>
+	<def key="20033">Repeat-Move Delay did not complete in time.</def>
+	<def key="20034">Attempt to use deprecated API function</def>
+	<def key="20035">Link errors detected</def>
+	<def key="20036">No Nodes Detected</def>
+	<def key="20037">Data acquisition gap in the stream due to invalid sequence.</def>
+	<def key="20038">There are no data points in the buffer.</def>
+	<def key="20039">Bad API call argument.</def>
+	<def key="20040">Interaction with wrong node type.</def>
+	<def key="20041">Serial Port does not support requested rate.</def>
+	<def key="20042">Command failed to transfer.</def>
+	<def key="20043">Could not acquire NC command interface.</def>
+	<def key="20044">Could not release NC command interface.</def>
+	<def key="20045">Response failed to transfer.</def>
+	<def key="20046">Response time-out.</def>
+	<def key="20047">Command timeout.</def>
+	<def key="20048">Command canceled.</def>
+	<def key="20049">Thread create error.</def>
+	<def key="20050">Unsolicited response detected.</def>
+	<def key="20051">Deferred command response time-out.</def>
+	<def key="20052">Response from beyond end of link.</def>
+	<def key="20053">Response from wrong source.</def>
+	<def key="20054">Flush finding many characters.</def>
+	<def key="20055">Failed to set thread priority.</def>
+	<def key="20056">Link diagnostic problems detected.</def>
+	<def key="20057">Could not start the read COMM IRQs.</def>
+	<def key="20058">Read thread returned a NULL buffer.</def>
+	<def key="20059">Reset command failed.</def>
+	<def key="20060">Log changed during read.</def>
+	<def key="20061">Data acquisition overrun.</def>
+	<def key="20062">Host's application serial port over-ran.</def>
+	<def key="20063">Host's diagnostic port over-ran.</def>
+	<def key="20064">Configuration file failed to open for write</def>
+	<def key="20065">Configuration file failed to open for reading, missing or security.</def>
+	<def key="20066">Configuration file is not for this node.</def>
+	<def key="20067">Configuration file has missing or corrupted item(s).</def>
+	<def key="20068">Configuration file load requires node to be disabled</def>
+	<def key="20069">Illegal command attempt from within an Attention Callback function.</def>
+	<def key="20070">Requested function only works on Application net.</def>
+	<def key="20071">Request canceled due to lack of 24V supply.</def>
+	<def key="21536">Initialization problem (internal error)!</def>
+	<def key="21537">Serial Port @ Net Number(s): 0. Initialization problem.</def>
+	<def key="21538">Serial Port @ Net Number(s): 1. Initialization problem.</def>
+	<def key="21539">Serial Port @ Net Number(s): 0 &amp; 1. Initialization problem.</def>
+	<def key="21540">Serial Port @ Net Number(s): 2. Initialization problem.</def>
+	<def key="21541">Serial Port @ Net Number(s): 2 &amp; 0. Initialization problem.</def>
+	<def key="21542">Serial Port @ Net Number(s): 2 &amp; 1. Initialization problem.</def>
+	<def key="21543">Serial Port @ Net Number(s): 2 &amp; 1 &amp; 0. Initialization problem.</def>
+	<def key="21792">Port open problem (internal error)!</def>
+	<def key="21793">Serial Port @ Net Number(s): 0. Failed to open error: busy or missing.</def>
+	<def key="21794">Serial Port @ Net Number(s): 1. Failed to open error: busy or missing.</def>
+	<def key="21795">Serial Port @ Net Number(s): 0 &amp; 1. Failed to open error: busy or missing.</def>
+	<def key="21796">Serial Port @ Net Number(s): 2. Failed to open error: busy or missing.</def>
+	<def key="21797">Serial Port @ Net Number(s): 2 &amp; 0. Failed to open error: busy or missing.</def>
+	<def key="21798">Serial Port @ Net Number(s): 2 &amp; 1. Failed to open error: busy or missing.</def>
+	<def key="21799">Serial Port @ Net Number(s): 2 &amp; 1 &amp; 0. Failed to open error: busy or missing.</def>
+	<def key="22048">Port baud problem (internal error)!</def>
+	<def key="22049">Serial Port @ Net Number(s): 0. Doesn't support baud rate.</def>
+	<def key="22050">Serial Port @ Net Number(s): 1. Doesn't support baud rate.</def>
+	<def key="22051">Serial Port @ Net Number(s): 0 &amp; 1. Doesn't support baud rate.</def>
+	<def key="22052">Serial Port @ Net Number(s): 2. Doesn't support baud rate.</def>
+	<def key="22053">Serial Port @ Net Number(s): 2 &amp; 0. Doesn't support baud rate.</def>
+	<def key="22054">Serial Port @ Net Number(s): 2 &amp; 1. Doesn't support baud rate.</def>
+	<def key="22055">Serial Port @ Net Number(s): 2 &amp; 1 &amp; 0. Doesn't support baud rate.</def>
+	<def key="20256">Generic reject by node.</def>
+	<def key="20257">Node Reject: Unknown command on this node.</def>
+	<def key="20258">Node Reject: Bad or missing command arguments.</def>
+	<def key="20259">Node Reject: Attempt to update Read-Only parameter.</def>
+	<def key="20260">Node Reject: EE hardware fault.</def>
+	<def key="20261">Node Reject: Access Level Violation</def>
+	<def key="20262">Node Reject: Move buffer is full, move ignored.</def>
+	<def key="20263">Node Reject: Move rejected, specification problem.</def>
+	<def key="20264">Node Reject: Node-stop blocked move.</def>
+	<def key="20265">Node Reject: Move distance attempt out of range.</def>
+	<def key="20266">Node Reject: Move blocked by drive shutdown/disable/limit.</def>
+	<def key="20267">Node Reject: IEX interaction when stopped.</def>
+	<def key="20268">Node Reject: Move blocked by alert condition.</def>
+	<def key="20272">Node Reject: Invalid operation while node is in motion.</def>
+	<def key="20269">Node Reject: Move blocked while homing runs.</def>
+	<def key="20768">Link break between node 0 and 1 on the other channel.</def>
+	<def key="20769">Link break between node 1 and 2 on the other channel.</def>
+	<def key="20770">Link break between node 2 and 3 on the other channel.</def>
+	<def key="20771">Link break between node 3 and 4 on the other channel.</def>
+	<def key="20772">Link break between node 4 and 5 on the other channel.</def>
+	<def key="20773">Link break between node 5 and 6 on the other channel.</def>
+	<def key="20774">Link break between node 6 and 7 on the other channel.</def>
+	<def key="20775">Link break between node 7 and 8 on the other channel.</def>
+	<def key="20776">Link break between node 8 and 9 on the other channel.</def>
+	<def key="20777">Link break between node 9 and 10 on the other channel.</def>
+	<def key="20778">Link break between node 10 and 11 on the other channel.</def>
+	<def key="20779">Link break between node 11 and 12 on the other channel.</def>
+	<def key="20780">Link break between node 12 and 13 on the other channel.</def>
+	<def key="20781">Link break between node 13 and 14 on the other channel.</def>
+	<def key="20782">Link break between node 14 and 15 on the other channel.</def>
+	<def key="20783">Link break between node 15 and the host on the other channel.</def>
+	<def key="20784">Link break between node 0 and 1 on app. channel</def>
+	<def key="20785">Link break between node 1 and 2 on app. channel</def>
+	<def key="20786">Link break between node 2 and 3 on app. channel</def>
+	<def key="20787">Link break between node 3 and 4 on app. channel</def>
+	<def key="20788">Link break between node 4 and 5 on app. channel</def>
+	<def key="20789">Link break between node 5 and 6 on app. channel</def>
+	<def key="20790">Link break between node 6 and 7 on app. channel</def>
+	<def key="20791">Link break between node 7 and 8 on app. channel</def>
+	<def key="20792">Link break between node 8 and 9 on app. channel</def>
+	<def key="20793">Link break between node 9 and 10 on app. channel</def>
+	<def key="20794">Link break between node 10 and 11 on app. channel</def>
+	<def key="20795">Link break between node 11 and 12 on app. channel</def>
+	<def key="20796">Link break between node 12 and 13 on app. channel</def>
+	<def key="20797">Link break between node 13 and 14 on app. channel</def>
+	<def key="20798">Link break between node 14 and 15 on app. channel</def>
+	<def key="20799">Link break between node 15 and the host on app. channel</def>
+	<def key="20800">Link break after 1 node from ConMod J1 (black) connector</def>
+	<def key="20801">Link break after 2 nodes from ConMod J1 (black) connector</def>
+	<def key="20802">Link break after 3 nodes from ConMod J1 (black) connector</def>
+	<def key="20803">Link break after 4 nodes from ConMod J1 (black) connector</def>
+	<def key="20804">Link break after 5 nodes from ConMod J1 (black) connector</def>
+	<def key="20805">Link break after 6 nodes from ConMod J1 (black) connector</def>
+	<def key="20806">Link break after 7 nodes from ConMod J1 (black) connector</def>
+	<def key="20807">Link break after 8 nodes from ConMod J1 (black) connector</def>
+	<def key="20808">Link break after 9 nodes from ConMod J1 (black) connector</def>
+	<def key="20809">Link break after 10 nodes from ConMod J1 (black) connector</def>
+	<def key="20810">Link break after 11 nodes from ConMod J1 (black) connector</def>
+	<def key="20811">Link break after 12 nodes from ConMod J1 (black) connector</def>
+	<def key="20812">Link break after 13 nodes from ConMod J1 (black) connector</def>
+	<def key="20813">Link break after 14 nodes from ConMod J1 (black) connector</def>
+	<def key="20814">Link break after 15 nodes from ConMod J1 (black) connector</def>
+	<def key="20815">Link break after 16 nodes from ConMod J1 (black) connector</def>
+	<def key="20816">Link break between node 0 and the host on app. channel</def>
+	<def key="20817">Link break between node 1 and the host on app. channel</def>
+	<def key="20818">Link break between node 2 and the host on app. channel</def>
+	<def key="20819">Link break between node 3 and the host on app. channel</def>
+	<def key="20820">Link break between node 4 and the host on app. channel</def>
+	<def key="20821">Link break between node 5 and the host on app. channel</def>
+	<def key="20822">Link break between node 6 and the host on app. channel</def>
+	<def key="20823">Link break between node 7 and the host on app. channel</def>
+	<def key="20824">Link break between node 8 and the host on app. channel</def>
+	<def key="20825">Link break between node 9 and the host on app. channel</def>
+	<def key="20826">Link break between node 10 and the host on app. channel</def>
+	<def key="20827">Link break between node 11 and the host on app. channel</def>
+	<def key="20828">Link break between node 12 and the host on app. channel</def>
+	<def key="20829">Link break between node 13 and the host on app. channel</def>
+	<def key="20830">Link break between node 14 and the host on app. channel</def>
+	<def key="20831">Link break between node 15 and the host on app. channel</def>
+	<def key="20832">Link break after 1 node from ConMod J1 (black) connector</def>
+	<def key="20833">Link break after 2 nodes from ConMod J1 (black) connector</def>
+	<def key="20834">Link break after 3 nodes from ConMod J1 (black) connector</def>
+	<def key="20835">Link break after 4 nodes from ConMod J1 (black) connector</def>
+	<def key="20836">Link break after 5 nodes from ConMod J1 (black) connector</def>
+	<def key="20837">Link break after 6 nodes from ConMod J1 (black) connector</def>
+	<def key="20838">Link break after 7 nodes from ConMod J1 (black) connector</def>
+	<def key="20839">Link break after 8 nodes from ConMod J1 (black) connector</def>
+	<def key="20840">Link break after 9 nodes from ConMod J1 (black) connector</def>
+	<def key="20841">Link break after 10 nodes from ConMod J1 (black) connector</def>
+	<def key="20842">Link break after 11 nodes from ConMod J1 (black) connector</def>
+	<def key="20843">Link break after 12 nodes from ConMod J1 (black) connector</def>
+	<def key="20844">Link break after 13 nodes from ConMod J1 (black) connector</def>
+	<def key="20845">Link break after 14 nodes from ConMod J1 (black) connector</def>
+	<def key="20846">Link break after 15 nodes from ConMod J1 (black) connector</def>
+	<def key="20847">Link break after 16 nodes from ConMod J1 (black) connector</def>
+	<def key="20848">Link break between node 0 and the host.</def>
+	<def key="20849">Link break between node 1 and the host.</def>
+	<def key="20850">Link break between node 2 and the host.</def>
+	<def key="20851">Link break between node 3 and the host.</def>
+	<def key="20852">Link break between node 4 and the host.</def>
+	<def key="20853">Link break between node 5 and the host.</def>
+	<def key="20854">Link break between node 6 and the host.</def>
+	<def key="20855">Link break between node 7 and the host.</def>
+	<def key="20856">Link break between node 8 and the host.</def>
+	<def key="20857">Link break between node 9 and the host.</def>
+	<def key="20858">Link break between node 10 and the host.</def>
+	<def key="20859">Link break between node 11 and the host.</def>
+	<def key="20860">Link break between node 12 and the host.</def>
+	<def key="20861">Link break between node 13 and the host.</def>
+	<def key="20862">Link break between node 14 and the host.</def>
+	<def key="20863">Link break between node 15 and the host.</def>
+	<def key="20928">Node 0 was unexpectedly found offline.</def>
+	<def key="20929">Node 1 was unexpectedly found offline.</def>
+	<def key="20930">Node 2 was unexpectedly found offline.</def>
+	<def key="20931">Node 3 was unexpectedly found offline.</def>
+	<def key="20932">Node 4 was unexpectedly found offline.</def>
+	<def key="20933">Node 5 was unexpectedly found offline.</def>
+	<def key="20934">Node 6 was unexpectedly found offline.</def>
+	<def key="20935">Node 7 was unexpectedly found offline.</def>
+	<def key="20936">Node 8 was unexpectedly found offline.</def>
+	<def key="20937">Node 9 was unexpectedly found offline.</def>
+	<def key="20938">Node 10 was unexpectedly found offline.</def>
+	<def key="20939">Node 11 was unexpectedly found offline.</def>
+	<def key="20940">Node 12 was unexpectedly found offline.</def>
+	<def key="20941">Node 13 was unexpectedly found offline.</def>
+	<def key="20942">Node 14 was unexpectedly found offline.</def>
+	<def key="20943">Node 15 was unexpectedly found offline.</def>
+	<def key="21020">Link break before first node from ConMod J1 (black) connector</def>
+	<def key="21021">Link break between host and node 0 on app. channel</def>
+	<def key="21022">Link break between host and node 0</def>
+	<def key="21023">Can't detect connectivity on this link.</def>
+</definitions>
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src-linux/SerialLinux.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src-linux/SerialLinux.cpp
new file mode 100644
index 000000000..00665a216
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src-linux/SerialLinux.cpp
@@ -0,0 +1,949 @@
+//*****************************************************************************
+// $Workfile: SerialLinux.cpp $
+// $Archive: /ClearPath SC-1.0.123/User Driver/linux/src/SerialLinux.cpp $
+// $Revision: 13 $ $Date: 12/09/16 4:43p $
+//
+//	SerialLinux.cpp - Implementation of the CSerial class for QNX.
+//
+//	Copyright (C) 1999-2003 Ramon de Klein (Ramon.de.Klein@ict.nl)
+//	(C)Copyright 2012  Teknic, Inc.  All rights reserved.
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+//////////////////////////////////////////////////////////////////////
+// Include module headerfile
+
+#include "SerialEx.h"
+#include "SerialLinux.h"
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <sys/select.h>
+#include <termios.h>
+#include <signal.h>
+
+#ifdef _DEBUG
+#define T_ON TRUE
+#else
+#define T_ON FALSE
+#endif
+#define T_OFF FALSE
+#if !defined(TRACE_THREAD)
+#define TRACE_THREAD		T_OFF	// Print thread create/exit IDs
+#endif
+#define TRACE_HIGH_LEVEL	T_OFF	// Print high level debug text
+#define TRACE_LOW_LEVEL		T_OFF	// Print low level debug test
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+
+// *************** Prototype *********
+// Returns the baud rate to set baud rate via OS function calls
+// Argument 1 is a long that specifies the bit/second (e.g. 9600)
+bool OSBaudRate(nodeulong eBaudrate, speed_t *theSpeed);
+
+// Time stamper
+extern "C" MN_EXPORT double MN_DECL infcCoreTime(void);
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::breakSigHandler
+//
+//	DESCRIPTION:
+/**
+ *	Register the detection of a serial line break condition.
+ *
+ *	\return TRUE on success
+**/
+//	SYNOPSIS:
+void sigHandler(int signo, siginfo_t *info, void *context) {
+	switch (signo) {
+	case SIGINT:
+		break;
+	default:
+		// We don't care about unprocessed signals
+		break;
+	}
+}
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::CancelCommIo
+//
+//	AUTHOR:
+//		Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Cancel pending serial I/O and flush all current data.
+ *
+ *	\return TRUE on success
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::CancelCommIo (void)
+{
+	SERAPI_ERR retErr;
+	// Cancel pending I/O
+	// ... TODO?
+	// Kill buffers
+	retErr = Purge();
+	return (retErr);
+}
+//
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::Purge
+//
+//	AUTHOR:
+//		Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Purge all of our hardware and operating system buffers.
+ *
+ *	\return TRUE on success
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Purge (void)
+{
+	if (tcflush(m_hFile, TCIOFLUSH))
+		return (CSerial::SERAPI_ERR(errno));
+	return(API_ERROR_SUCCESS);
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::CSerial
+//
+//	AUTHOR:
+//		Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Generic asynchronous threaded serial port access for use on various
+ *	operating systems.
+**/
+//	SYNOPSIS:
+CSerial::CSerial ()
+	: m_lLastError(API_ERROR_SUCCESS)
+	, m_hFile(INVALID_HANDLE)
+	, m_eEvent(EEventNone)
+	, m_dwEventMask(0)
+{
+	#if TRACE_THREAD
+		_RPTF0(_CRT_WARN,"CSerial::CSerial (created)\n");
+	#endif
+}
+
+CSerial::~CSerial ()
+{
+	// Close implicitly
+	if (m_hFile != INVALID_HANDLE)
+		Close();
+	#if TRACE_THREAD
+		_RPTF0(_CRT_WARN,"CSerial::~CSerial (destroyed)\n");
+	#endif
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::CSerial
+//
+//	AUTHOR:
+//		Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Generic asynchronous threaded serial port access for use on various
+ *	operating systems.
+ *
+ *	\param portName[in] Pointer to serial port path.
+ *	\param dwInQueue[in] Suggested input queue size
+ *	\param dwOutQueue[in] Suggested output queue size
+ *	\param fOverlapped[in] Performed overlapped I/O if possible
+ *	\return API_ERROR_SUCCESS(0) on success
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Open (
+	const char * portName,
+	DWORD dwInQueue,
+	DWORD dwOutQueue,
+	bool fOverlapped) {
+
+	struct termios tio;
+	speed_t theSpeed;
+	int theErr;
+#if TRACE_HIGH_LEVEL
+	_RPT1(_CRT_WARN, "CSerial::Open serial port %s\n", portName);
+#endif
+	// definition of signal action
+#if 0
+	struct sigaction saio;
+	saio.sa_sigaction = sigHandler;
+	saio.sa_flags = SA_SIGINFO;
+	// saio.sa_mask = 0;
+	saio.sa_flags = 0;
+//MD_TODO	saio.sa_restorer = NULL;
+//	sigaction(SIGINT, &saio, NULL);	  // 5/29/12 DS ?? TODO will this catch break if we can cancel action
+#endif
+
+	//set the user console port up
+	//m_hFile = open( portName, O_RDWR | O_NOCTTY | O_NONBLOCK | O_NDELAY);
+	m_hFile = open( portName, O_RDWR | O_NOCTTY | O_NONBLOCK );
+	if (m_hFile == INVALID_HANDLE) {
+		m_lLastError = (CSerial::SERAPI_ERR)errno;
+		snprintf(m_lastErrMsg, sizeof(m_lastErrMsg),
+				"open %s failed, errno=%d\n", portName, m_lLastError);
+		fputs(m_lastErrMsg, stderr);
+		return(API_ERROR_INVALID_HANDLE);
+	}
+	//_RPT1(_CRT_WARN, "opened m_hFile: %d\n", m_hFile);
+	// set new port settings for non-canonical input processing  //must be NOCTTY
+    tcgetattr(m_hFile, &tio);
+    cfmakeraw(&tio);
+//    // No RTS/CTS handshake, no hang-up on break, 8 bit, no parity
+//    tio.c_cflag &= ~(CRTSCTS);
+//    tio.c_cflag |= CS8 | CLOCAL | CREAD;
+//
+//    // No output processing
+//	tio.c_oflag = 0;
+//
+//	// Setup raw
+//	tio.c_lflag = 0;		//ICANON;
+//
+//	// Input options: flow control off, no parity check, ignore break
+//	tio.c_iflag &= ~(IXON | IXOFF | IXANY | BRKINT | INPCK);
+//	tio.c_iflag |= IGNBRK;
+
+    theErr=OSBaudRate(9600, &theSpeed);
+    if(!theErr) {                           // If invalid baud rate, return error
+        m_lLastError=API_ERROR_PORT_SETUP;
+        return API_ERROR_PORT_SETUP;
+    }
+	cfsetispeed(&tio, theSpeed);  // Input BAUD Rate = 9600
+	cfsetospeed(&tio, theSpeed);  // Output BAUD Rate = 9600
+	// Wait for one character minimally to wake up
+	tio.c_cc[VMIN]= 1;
+	// No delay until we see char
+	tio.c_cc[VTIME]= 0;
+
+	if (tcsetattr( m_hFile, TCSANOW, &tio ) == -1) {
+		_RPT0(_CRT_WARN, "serial port setup issue!\n" );
+		printf("tcsetattr failure, code %d\n",errno);
+		return(API_ERROR_PORT_SETUP);
+	}
+//    // Make sure flow control is defeated
+//    if(tcflow(m_hFile, TCOON | TCION)) {
+//    	fprintf(stderr, "Serial::Open flow control off failed, %d\n", errno);
+//    }
+	// Reset CON-MOD loopback
+	SetDTR( false );
+	SetRTS( false );
+	usleep( 100000 );
+	// Clear any character that leaked in before changes
+	Purge();
+	// OK, return
+	return(API_ERROR_SUCCESS);
+}
+//
+//****************************************************************************
+
+//****************************************************************************
+//	NAME																	 *
+//		CSerial::Close
+//
+//	AUTHOR:
+//		Refactored from Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+	Shutdown the serial port and release to the operating system.
+
+	\return API_ERROR_SUCCESS(0) on success
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Close (void) {
+
+	// Reset error state
+	m_lLastError = API_ERROR_SUCCESS;
+
+	// If the device is already closed,
+	// then we don't need to do anything.
+	if (m_hFile == INVALID_HANDLE)
+	{
+		// Display a warning
+		//_RPTF0(_CRT_WARN,"CSerial::Close - Method called when device is not open\n");
+		return API_ERROR_SUCCESS;
+	}
+	// Insure all open work has stopped
+	CancelCommIo();
+	// Yield quanta now to let it happen
+	usleep(10000);
+
+	// Close COM port
+//	#if TRACE_HIGH_LEVEL
+//		_RPTF1(_CRT_WARN, "CSerial::Close port = hndl=0x%x\n", m_hFile);
+//	#endif
+	close( m_hFile );
+	m_hFile = INVALID_HANDLE;
+
+	// Return successful
+	return API_ERROR_SUCCESS;
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::Setup
+//
+//	DESCRIPTION:
+/**
+ *	Setup the serial port's speed in bits/second (baud rate)
+ *
+ *	\param eBaudrate[in] Send/Receive speed in bits/second.
+ *
+ *	\return API_ERROR_SUCCESS(0) on success
+**/
+//	SYNOPSIS:
+bool OSBaudRate(nodeulong eBaudrate, speed_t *theSpeed) {
+
+    switch(eBaudrate){
+        case 9600:      // Common Rate
+            *theSpeed=B9600;
+            break;
+        case 19200:
+            *theSpeed=B19200;
+            break;
+        case 38400:
+            *theSpeed=B38400;
+            break;
+        case 57600:
+            *theSpeed=B57600;
+            break;
+        case 115200:
+            *theSpeed=B115200;    // Common
+            break;
+        case 230400:
+            *theSpeed=B230400;   // Common
+            break;
+        case 460800:
+            *theSpeed=B460800;
+            break;
+        case 921600:
+            *theSpeed=B921600;
+            break;
+        case 1152000:
+            *theSpeed=B1152000;
+            break;
+        default:
+            return false;
+            break;
+    }
+
+    // Speed was set successfully
+    return true;
+
+}
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::Setup
+//
+//	AUTHOR:
+//		Refactored from Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Setup the serial port's speed and other attributes.
+ *
+ *	\param eBaudrate[in] Send/Receive speed in bits/second.
+ *	\param eDataBits[in] Data size, usually EData8
+ *	\param eParity[in] Parity generation/checking, usually EParNone
+ *	\param eStopBits[in] Stop bits, usually EStop1
+ *	\param eDTRBit[in] DTR output assertion, usually EDTRSet
+ *
+ *	\return API_ERROR_SUCCESS(0) on success
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Setup (
+		nodeulong eBaudrate,
+		EDataBits eDataBits,
+		EParity eParity,
+		EStopBits eStopBits,
+		EDTR eDTRBit,
+		ERTS eRTSBit) {
+    speed_t theSpeed;
+    int theErr;
+
+	// Reset error state
+	m_lLastError = API_ERROR_SUCCESS;
+
+	// Check if the device is open
+	if (m_hFile == INVALID_HANDLE)
+	{
+		// Set the internal error code
+		m_lLastError = API_ERROR_INVALID_HANDLE;
+
+		// Issue an error and quit
+		_RPTF0(_CRT_WARN,"CSerial::Setup - Device is not opened\n");
+		return API_ERROR_INVALID_HANDLE;
+	}
+#if TRACE_HIGH_LEVEL
+	_RPT1(_CRT_WARN, "CSerial::Setup baud=%d\n", eBaudrate);
+#endif
+	struct termios my_termios;
+
+	m_lLastError = (CSerial::SERAPI_ERR)tcgetattr( m_hFile, &my_termios );
+	if (m_lLastError)
+		return API_ERROR_PORT_SETUP;
+	my_termios.c_cflag &= ~CSIZE;
+	my_termios.c_cflag |= eDataBits;
+	my_termios.c_cflag &= ~EParOdd;
+	my_termios.c_cflag |= eParity;
+	my_termios.c_cflag &= ~CSTOPB;
+	my_termios.c_cflag |= eStopBits;
+	my_termios.c_iflag |= BRKINT;
+
+    theErr=OSBaudRate(eBaudrate, &theSpeed);
+    if(!theErr) {                           // If invalid baud rate, return error
+        m_lLastError=API_ERROR_PORT_SETUP;
+        return API_ERROR_PORT_SETUP;
+    }
+
+    theErr=cfsetispeed(&my_termios, theSpeed);
+    if(theErr!=0){
+        m_lLastError=API_ERROR_PORT_SETUP;
+    }
+
+	theErr=cfsetospeed(&my_termios, theSpeed);
+    if(theErr!=0){
+        m_lLastError=API_ERROR_PORT_SETUP;
+    }
+
+	m_lLastError = (CSerial::SERAPI_ERR)tcsetattr( m_hFile, TCSANOW, &my_termios );
+	if (m_lLastError)
+		return API_ERROR_PORT_SETUP;
+	
+	// Make sure DTR is set properly
+	SetDTR(eDTRBit);
+	// Make sure DTR is set properly
+	SetRTS(eRTSBit);
+	// Return successful
+	return API_ERROR_SUCCESS;
+}
+//
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::SetEventMask
+//
+//	AUTHOR:
+//		Refactored from Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Setup the serial port's speed and other attributes.
+ *
+ *	\param dwEventMask[in] Bit mask of events to watch for.
+ *
+ *	\return API_ERROR_SUCCESS(0) on success
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::SetEventMask (DWORD dwEventMask) {
+
+	// Reset error state
+	m_lLastError = API_ERROR_SUCCESS;
+
+	// Check if the device is open
+	if (m_hFile == INVALID_HANDLE) {
+		// Set the internal error code
+		m_lLastError = API_ERROR_INVALID_HANDLE;
+
+		// Issue an error and quit
+		_RPTF0(_CRT_WARN,"CSerial::SetEventMask - Device is not opened\n");
+		return API_ERROR_INVALID_HANDLE;
+	}
+
+	// Set the new mask. Note that this will generate an EEventNone
+	// if there is an asynchronous WaitCommEvent pending.
+
+
+
+
+	// Save event mask and return successful
+	m_dwEventMask = dwEventMask;
+	return API_ERROR_SUCCESS;
+}
+//
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME
+//		CSerial::CommWaitEventInitiate
+//
+//	DESCRIPTION:
+/**
+	Initiate the wait for the specified serial communications event(s).
+
+	This could be implemented via polling or other operating system
+	event support for responsive reactions.
+
+	Note: For POSIX style platforms, only the break is detected (TODO)
+
+	\return API_ERROR_SUCCESS(0) of OK, else an error code.
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::CommEventWaitInitiate() {
+	// TODO: Find and post events in m_eEvent
+	usleep(100000);
+	return API_ERROR_SUCCESS;
+}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerial::GetEventType
+//
+//	AUTHOR:
+//		Refactored from Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+//	DESCRIPTION:
+/**
+ *	Return the events detected since last inquiry.
+ *
+  *	\return EEventNone if none, else a bit encoded result.
+**/
+CSerial::EEvent CSerial::GetEventType (void)
+{
+
+	// Obtain the event (mask unwanted events out)
+	EEvent eEvent = m_eEvent;
+
+	// Reset internal event type
+	m_eEvent = EEventNone;
+
+	// Return the current cause
+	return eEvent;
+}
+//
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME
+//		CSerial Write
+//
+//	DESCRIPTION:
+///		Write data to port.
+//
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Write (const void* pData, size_t iLen, DWORD* pdwWritten, DWORD dwTimeoutMS) {
+	// Reset error state
+	m_lLastError = API_ERROR_SUCCESS;
+
+	// Reset the number of bytes written
+	*pdwWritten = 0;
+
+	// Check if the device is open
+	if (m_hFile == INVALID_HANDLE) {
+		// Set the internal error code
+		m_lLastError = API_ERROR_INVALID_HANDLE;
+
+		// Issue an error and quit
+		_RPTF0(_CRT_WARN,"CSerial::Write - Device is not opened\n");
+		return API_ERROR_INVALID_HANDLE;
+	}
+	ssize_t ret = write( m_hFile, pData, iLen );
+	if ( ret < 0 ) {
+		// Set the internal error code
+	 	m_lLastError = (CSerial::SERAPI_ERR)errno;
+	 	snprintf(m_lastErrMsg, sizeof(m_lastErrMsg),
+		// Issue an error and quit
+	 			"CSerial::Write - Unable to write the data err=%d\n", (int)m_lLastError);
+	 	_RPTF1(_CRT_WARN, "%s", m_lastErrMsg);
+		return (CSerial::SERAPI_ERR)errno;
+	}
+	else {
+		*pdwWritten = ret;
+//		unsigned char * prt = (unsigned char *)pData;
+//		printf( "write: " );
+//		for ( int ix = 0; ix < iLen; ++ix ) printf( "%X ", prt[ix] );
+//		printf( "\n" );
+	}
+
+	// Return successfully
+	return API_ERROR_SUCCESS;
+}
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerialEx::Read
+//
+//	DESCRIPTION:
+/**
+	Read the current unprocessed characters from the serial port with
+	time-out.
+
+ 	\param pData[out] Buffer to write the octets received by the serial
+ 	port to.
+ 	\param iLen[in] Maximum number of characters to read this call.
+ 	\param pdwRead[out] The number of characters actually read into
+ 	\a pData.
+ 	\param dwTimeoutMS[in] Maximum time to wait for characters to
+ 	arrive.
+
+	\return API_ERROR_SUCCESS(0) if read was successful and \a pData was
+	filled with \a pdwRead characters.
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Read (
+	void* pData,
+	size_t iLen,
+	DWORD* pdwRead,
+	DWORD dwTimeoutMS)
+{
+	// Reset error state
+	m_lLastError = API_ERROR_SUCCESS;
+
+	// Reset the number of bytes read
+	*pdwRead = 0;
+
+	// Check if the device is open
+	if (m_hFile == INVALID_HANDLE) {
+		// Set the internal error code
+		m_lLastError = API_ERROR_INVALID_HANDLE;
+		// Issue an error and quit
+		_RPTF0(_CRT_WARN,"CSerial::Read - Device is not opened\n");
+		return API_ERROR_INVALID_HANDLE;
+	}
+
+//	printf("about to read serial port\n");
+    fd_set r_fds;
+	FD_ZERO(&r_fds);
+	FD_SET( m_hFile, &r_fds );
+	ssize_t ret = -1;
+	if ( dwTimeoutMS == INFINITE ) {
+		ret = select( m_hFile + 1, &r_fds, NULL, NULL, NULL );
+	} else {
+		struct timeval tv;
+		tv.tv_sec = 0;
+		tv.tv_usec = dwTimeoutMS * 1000;
+		ret = select( m_hFile + 1, &r_fds, NULL, NULL, &tv );
+	}
+
+	if ( ret && FD_ISSET( m_hFile, &r_fds ) ) {
+		ret = read( m_hFile, pData, iLen );
+		if ( ret == -1 ) {
+		 	m_lLastError = (CSerial::SERAPI_ERR)errno; 		// Set the internal error code
+//			_RPTF1(_CRT_WARN, "CSerial::Read - Unable to read the data err=%d\n", (int)m_lLastError);
+			return (CSerial::SERAPI_ERR)errno;
+		} else if ( ret >= 0 ) {
+			*pdwRead = ret;
+		}
+	} else if ( ret == 0 ) {
+		m_lLastError = API_ERROR_TIMEOUT;
+		return API_ERROR_TIMEOUT;
+		// Allow release of waiters
+		m_rdEvent.SetEvent();	//5/29/12 DS Do we really need this?
+	} else {
+	 	m_lLastError = (CSerial::SERAPI_ERR)errno; 		// Set the internal error code
+	 	snprintf(m_lastErrMsg, sizeof(m_lastErrMsg),
+	 			"CSerial::Read - Unable to read the data err=%d\n", (int)m_lLastError);
+		fputs(m_lastErrMsg, stderr);
+		return (CSerial::SERAPI_ERR)errno;
+	}
+	return API_ERROR_SUCCESS;
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::Break
+//
+//	DESCRIPTION:
+/**
+	Send the break condition for the specified time.
+
+	\param breakDurationMs[in] Duration in milliseconds.
+
+	\return API_ERROR_SUCCESS(0) if performed.
+**/
+//	SYNOPSIS:
+CSerial::SERAPI_ERR CSerial::Break ( DWORD breakDurationMs)
+{
+	// Reset error state
+	m_lLastError = API_ERROR_SUCCESS;
+
+	// Check if the device is open
+	if (m_hFile == INVALID_HANDLE)
+	{
+		// Set the internal error code
+		m_lLastError = API_ERROR_INVALID_HANDLE;
+
+		// Issue an error and quit
+		_RPTF0(_CRT_WARN,"CSerial::Break - Device is not opened\n");
+		return API_ERROR_INVALID_HANDLE;
+	}
+#if TRACE_HIGH_LEVEL
+	fprintf(stderr, "%.1f CSerial::Break about to send\n", infcCoreTime() );
+#endif
+	// Set the RS-232 port in break mode for a little while
+	if (tcsendbreak(m_hFile, breakDurationMs)) {
+		m_lLastError = (CSerial::SERAPI_ERR)errno;
+		fprintf(stderr, "%.1f CSerial::Break failed, err=%d\n",
+				infcCoreTime(), m_lLastError);
+		return (CSerial::SERAPI_ERR)m_lLastError;
+	}
+	// TODO: Assume we get our break back (no good POSIX way
+	// to detect in C++). The subsequent time-out will keep us
+	// offline. Uses serial event thread to signal back.
+	m_eEvent = EEvent(EEventBreak|EEventError);
+	m_eError = EErrorBreak;
+	//struct termios options;
+	//tcgetattr(m_hFile, &options);
+	//tcsetattr(m_hFile, TCSADRAIN, &options);
+#if TRACE_HIGH_LEVEL
+	fprintf(stderr, "%.1f CSerial::Break finished\n", infcCoreTime() );
+#endif
+	ForceCommEvent();
+
+	// Return successfully
+	return API_ERROR_SUCCESS;
+}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::GetDSR
+//
+//	DESCRIPTION:
+/**
+	Return the last known state of the DSR line.
+
+	\return true if asserted
+**/
+//	SYNOPSIS:
+bool CSerial::GetDSR(void)
+{
+	unsigned long int status;
+	if (ioctl(m_hFile, TIOCMGET, &status) == -1)
+		return false;
+	return (status & TIOCM_DSR) != 0;
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::GetDTR
+//
+//	DESCRIPTION:
+/**
+	Return the last known state of the DTR line.
+
+	\return true if asserted
+**/
+//	SYNOPSIS:
+bool CSerial::GetDTR(void)
+{
+	unsigned long int status;
+	if (ioctl(m_hFile, TIOCMGET, &status) == -1)
+		return false;
+	return (status & TIOCM_DTR) != 0;
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::SetDTR
+//
+//	DESCRIPTION:
+/**
+	Return the last known state of the DTR line.
+
+	\param EDTRBit state to assert.
+**/
+//	SYNOPSIS:
+void CSerial::SetDTR(bool EDTRBit)
+{
+	int iFlags;
+	if (ioctl (m_hFile, TIOCMGET, &iFlags) == -1)
+		return;
+	if(EDTRBit) {
+		iFlags |= TIOCM_DTR;
+	}
+	else {
+		iFlags &= ~TIOCM_DTR;
+	}
+	ioctl( m_hFile, TIOCMSET, &iFlags );
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::GetRTS
+//
+//	DESCRIPTION:
+/**
+	Return the last known state of the RTS line.
+
+	\return true if asserted
+**/
+//	SYNOPSIS:
+bool CSerial::GetRTS(void)
+{
+	int iFlags;
+	if (ioctl (m_hFile, TIOCMGET, &iFlags) == -1)
+		return false;
+
+	return (iFlags & TIOCM_RTS) != 0;
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::SetRTS
+//
+//	DESCRIPTION:
+/**
+	Return the last known state of the RTS line.
+
+	\param ERTSBit state to assert.
+**/
+//	SYNOPSIS:
+void CSerial::SetRTS(bool ERTSBit)
+{
+	int iFlags;
+	if (ioctl (m_hFile, TIOCMGET, &iFlags) == -1)
+		return;
+
+	if(ERTSBit) {
+		iFlags |= TIOCM_RTS;
+	}
+	else {
+		iFlags &= ~TIOCM_RTS;
+	}
+	ioctl( m_hFile, TIOCMSET, &iFlags );
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerial::GetCTS
+//
+//	DESCRIPTION:
+/**
+	Return the state of the CTS line.
+
+	\return true if asserted
+**/
+//	SYNOPSIS:
+bool CSerial::GetCTS(void)
+{
+	int iFlags;
+	if (ioctl (m_hFile, TIOCMGET, &iFlags) == -1)
+		return false;
+	
+	return (iFlags & TIOCM_CTS) != 0;
+}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		CSerialEx::GetBaudrate
+//
+//	DESCRIPTION:
+/**
+	Get the port's current baud rate in bits/seconds.
+
+	\return Port speed in bits/second. EBaudUnknown if unknown.
+**/
+//	SYNOPSIS:
+nodeulong  CSerial::GetBaudrate(void)
+{
+	struct termios my_termios;
+
+	if (tcgetattr( m_hFile, &my_termios )) {
+		m_lLastError = (CSerial::SERAPI_ERR)errno;
+		return(EBaudUnknown);
+	}
+	// Note: ispeed and ospeed are always identical in our driver
+	return(nodeulong(my_termios.c_ispeed));
+}
+//
+//****************************************************************************
+
+
+//*****************************************************************************
+//*****************************************************************************
+//                       Platform Dependent CSerialEx
+//*****************************************************************************
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::GetCharsAvailable
+//
+//	DESCRIPTION:
+///		Return the count of characters available for reading.
+///
+///		\return Number of unprocessed characters.
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+LONG CSerialEx::GetCharsAvailable(void)
+{
+	int bytes = 0;
+	if (m_hFile != INVALID_HANDLE)
+		ioctl(m_hFile, FIONREAD, &bytes);
+	return(LONG(bytes));
+}
+
+//																			  *
+//*****************************************************************************
+
+
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src-linux/lnkAccessLinux.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src-linux/lnkAccessLinux.cpp
new file mode 100644
index 000000000..8c297ae8c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src-linux/lnkAccessLinux.cpp
@@ -0,0 +1,461 @@
+//******************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/linux/src/lnkAccessLinux.cpp $
+// $Revision: 8 $ $Date: 12/09/16 5:00p $
+// $Workfile: lnkAccessLinux.cpp $
+//
+// DESCRIPTION:
+/**
+	\file
+	\defgroup ChanGrp Channel Access Functions
+	\brief Channel Access API for Linux
+
+	This implements the function library portion of the driver suite for
+	operating system dependent features.
+
+**/
+// CREATION DATE:
+//	02/11/1998 16:34:00
+//  06/09/2009 17:39 Refactored from ControlPoint implementation
+//
+// COPYRIGHT NOTICE:
+//	(C)Copyright 1998-2012  Teknic, Inc.  All rights reserved.
+//
+//	This copyright notice must be reproduced in any copy, modification,
+//	or portion thereof merged into another program. A copy of the
+//	copyright notice must be included in the object library of a user
+//	program.
+// 																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																		   *
+// 	lnkAccessLinux.cpp headers
+//
+	// Our driver headers
+	#include "lnkAccessCommon.h"
+	#include "mnErrors.h"
+	#include "sFoundResource.h"
+	#include "SerialEx.h"
+
+	#include <errno.h>
+	#include <stdio.h>
+	#include <string.h>
+	#include <unistd.h>
+	#include <sys/stat.h>
+	#include <sys/types.h>
+	#include <sys/syscall.h>
+	#include <time.h>
+	#include <inttypes.h>
+	#include <wchar.h>
+	#include "ErrCodeStr.hpp"
+
+	#ifndef _GNU_SOURCE
+	#define _GNU_SOURCE
+	#endif
+	#include <dlfcn.h>
+	#include <libgen.h>
+// 																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																		   *
+// 	lnkAccessLinux.cpp constants
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+// 	lnkAccessLinux.cpp imported information
+//
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+// 	lnkAccessLinux.cpp function prototypes
+//
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+// 	lnkAccessLinux.cpp static variables
+//
+ErrCodeStr ErrorLookups;
+// 																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcCoreTime
+//
+//	CREATION DATE:
+//		11/17/1998 21:13:16
+//
+//	DESCRIPTION:
+///		Return the high precision time value with at least tenth of millisecond
+///		resolution.	This is used to time stamp the log files and provide
+///		time-out facilities.
+///
+///		\return double count in milliseconds
+//
+//	SYNOPSIS:
+MN_EXPORT double MN_DECL infcCoreTime(void)
+{
+#if 1
+	static double initial = 0;
+	struct timespec now;
+	if (clock_gettime(CLOCK_REALTIME, &now) == -1)
+		return(0);
+	double tNow = double(now.tv_sec)*1000 + double(now.tv_nsec)*1e-6-initial;
+	if (!initial)
+		initial = tNow;
+
+	//clock_t now = clock();
+	//double tNow = double(now/(CLOCKS_PER_SEC*.001));
+	return(tNow);
+#else
+	static Uint64 initial = 0;
+	Uint64 tNow = ClockCycles()-initial;
+	// Reset time at first request
+	if (!initial)
+		initial = tNow;
+	return(1000*double(tNow)/ SYSPAGE_ENTRY(qtime)->cycles_per_sec);
+#endif
+}
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//		infcVersion
+//
+//	CREATION DATE:
+//		01/26/2001 10:38:58
+//
+//	DESCRIPTION:
+/**
+	Return the DLL driver revision code in 8.8.16 format.
+
+	\return	unsigned 8.8.16 format. \b major . \b minor . \b revision
+**/
+//	SYNOPSIS:
+MN_EXPORT nodeulong MN_DECL infcVersion(void)
+{
+	return(VER_FILEVERSION_DW);
+}
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//		infcGetDumpDir
+//
+//	CREATION DATE:
+//		03/10/2010 10:15:25
+//
+//	DESCRIPTION:
+/**
+	Return the directory where automatic dump files are created with
+	trailing directory delimitor.  This will be "%TEMP%\Teknic\" for Windows.
+
+ 	\param[out] pStr Ptr to string to be returned.
+	\param[in] maxLen Size of \e pStr area.
+**/
+//	SYNOPSIS:
+void infcGetDumpDir(
+	char *pStr,						// Ptr to string area
+	nodelong maxLen)
+{
+	// Create a dump file in the temp directory
+	if (mkdir("/tmp/Teknic", 0777) != 0){
+        if(errno != EEXIST)
+            fprintf(stderr, "ERROR %d: unable to mkdir; %s\n",
+                    errno, strerror(errno));
+	}
+	strncpy(pStr, "/tmp/Teknic/", maxLen);
+}
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//		infcErrCodeStrA
+//
+// 	CREATION DATE:
+//      01/15/2004 14:49:41
+//
+// 	DESCRIPTION:
+/**
+    Return the descriptive ANSI string for the selected cnErrCode.
+
+	\param[in] lookupCode Error code number to lookup.
+	\param[in] maxLen Maximum size of return string
+	\param[out] resultStr Ptr to the string result to return
+
+	\return MN_OK if succeed and \p resultStr updated.
+**/
+//      SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcErrCodeStrA(
+        cnErrCode lookupCode,
+        Uint16 maxLen,
+        char resultStr[])
+{
+	int nChars;
+	switch(lookupCode) {
+	case MN_OK:
+		strncpy(resultStr, "OK", maxLen);
+		// Insure null
+		resultStr[maxLen-1] = 0;
+		nChars = strlen(resultStr);
+		break;
+	case MN_ERR_OS:
+		break;
+	default:
+		if (lookupCode >= MN_ERR_BASE && lookupCode < MN_ERR_BASE+0xfff) {
+			char toStringBuf[10];
+			// Create "key"
+			snprintf(toStringBuf, sizeof(toStringBuf), "%ld",
+					lookupCode - MN_ERR_BASE + STR_ERR_BASE);
+			char *errString = ErrorLookups.lookup(toStringBuf);
+			// Safe copy to user
+			strncpy(resultStr, errString, maxLen);
+			nChars = strlen(resultStr);
+		}
+		else {
+			nChars = snprintf(resultStr, maxLen, "Error: 0x%x", lookupCode);
+		}
+		break;
+	}
+	// Warn if the buffer is too small
+	return(nChars<maxLen ? MN_OK : MN_ERR_BADARG);
+}
+// 																			   *
+//******************************************************************************
+
+//******************************************************************************
+// NAME																		   *
+//		infcHeapCheck
+//
+// 	CREATION DATE:
+//      03-26-2012
+//
+// 	DESCRIPTION:
+/**
+    Debugging aid for checking heap corruption at various points within
+    the driver.
+
+**/
+//      SYNOPSIS:
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+MN_EXPORT void infcHeapCheck(const char *msg)
+{
+	// TODO
+}
+// 																			   *
+//******************************************************************************
+
+
+//****************************************************************************
+//	NAME																	 *
+//		infcFilenameA
+//
+//	DESCRIPTION:
+//		Update the ANSI <fname> string up to <len> chars with the file name of
+//		this DLL.
+//
+//	CREATION DATE:
+//		09/23/2004 16:02:36
+//
+//	RETURNS:
+//		fname updated
+//
+//	SYNOPSIS:
+MN_EXPORT void MN_DECL infcFileNameA(char *fname, long len)
+{
+	Dl_info dl_info;
+    dladdr((void *)infcFileNameA, &dl_info);
+    strncpy(fname, dl_info.dli_fname, len);
+}
+//																			 *
+//****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGetHubPorts
+//
+//	DESCRIPTION:
+///		return the SC Hub USB port adapter name(s)
+///
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetHubPorts(std::vector<std::string> &comHubPorts)
+{
+
+	comHubPorts.clear();
+	FILE *pfd = popen( "ls /dev/ttyXRUSB*", "r" );
+
+    if ( pfd <= 0 )
+    {
+      throw std::runtime_error( "Command or process could not be executed." );
+    }
+
+    while ( !feof(pfd) )
+    {
+      char buf[ 1024 ] = {0};
+
+      if ( fgets(buf, sizeof(buf), pfd) > 0 )
+      {
+        std::string str(buf);
+        // TODO: check the VID/PID of the device using udevadm/libudev to
+        // verify that this is a Teknic SC4-Hub (vid=2890, pid=0213)
+        comHubPorts.push_back(str.substr(0, str.length()-1));
+      }
+    }
+    pclose( pfd );
+
+    return MN_OK;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGetPortInfo
+//
+//	CREATION DATE:
+//		2/8/2011 08:45:35
+//
+//	DESCRIPTION:
+///		return the port adapter name and manufacturer from the registry
+///
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetPortInfo(
+		const char *portName,
+		serPortInfo *portInfo)
+{
+	return(MN_ERR_NOT_IMPL);
+}
+//																			 *
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcDbgDepth
+//
+//	CREATION DATE:
+//		2/8/2011 08:45:35
+//
+//	DESCRIPTION:
+///		return the port adapter name and manufacturer from the registry
+///
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT nodelong MN_DECL infcDbgDepth(netaddr cNum) {
+	extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+	if (cNum > NET_CONTROLLER_MAX)
+		return(0);
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (pNCS)
+		return(pNCS->pSerialPort->MaxDepth());
+	return(0);
+}
+//																			 *
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcThreadID
+//
+//	CREATION DATE:
+//		6/23/2016 12:04
+//
+//	DESCRIPTION:
+///		Return the thread ID of the currently running thread.
+///
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT Uint64 MN_DECL infcThreadID() {
+	return (Uint64)syscall(SYS_gettid);
+}
+//																			 *
+//****************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//		_controllerSpec::_controllerSpec
+//
+// 	CREATION DATE:
+//      03-26-2012
+//
+// 	DESCRIPTION:
+/**
+    Create a controller specification record.
+
+    \param[in] Ptr to serial port device path.
+    \param[in] Speed to run port at.
+
+**/
+//      SYNOPSIS:
+_controllerSpec::_controllerSpec(const char * name, netRates rate) {
+	strncpy(PortName, name, MAX_PATH);
+	PortRate = rate;
+}
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//		ErrCodeStr::ErrCodeStr()
+//
+// 	CREATION DATE:
+//      01-25-2017
+//
+// 	DESCRIPTION:
+/**
+    Load the XML error code list at construction time. It will be
+    located were this shared object file is located.
+
+**/
+//      SYNOPSIS:
+ErrCodeStr::ErrCodeStr() {
+	char pathLoc[MAX_PATH];
+	infcFileNameA(pathLoc, sizeof(pathLoc));
+	dirname(pathLoc);
+	strncat(pathLoc, LNK_ACCESS_XML_ERR_TXT, sizeof(pathLoc));
+	//fprintf(stderr, "In ErrCodeStr constructor err XML=%s\n", pathLoc);
+	this->load(pathLoc);
+}
+// 																			   *
+//******************************************************************************
+
+
+//==============================================================================
+//	END OF FILE lnkAccessLinux.cpp
+//==============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/SerialEx.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/SerialEx.cpp
new file mode 100644
index 000000000..85504303c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/SerialEx.cpp
@@ -0,0 +1,1532 @@
+//*****************************************************************************
+// $Workfile: SerialEx.cpp $
+// $Archive: /ClearPath SC-1.0.123/User Driver/src/SerialEx.cpp $
+// $Date: 01/19/2017 17:39 $
+//
+//	SerialEx.cpp - Implementation of the CSerialEx class for QNX Real Time OS
+//
+//	Copyright (C) 1999-2003 Ramon de Klein (Ramon.de.Klein@ict.nl)
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2.1 of the License, or (at your option) any later version.
+// 
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+// Lesser General Public License for more details.
+// 
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+//////////////////////////////////////////////////////////////////////
+// Include the standard header files
+
+#define STRICT
+
+
+	#include "pubMnNetDef.h"
+	#include "lnkAccessCommon.h"
+	#if (defined(_WIN32)||defined(_WIN64))
+		#include <crtdbg.h>
+	#endif
+
+
+//////////////////////////////////////////////////////////////////////
+// Include module headerfile
+
+#include "SerialEx.h"
+
+//////////////////////////////////////////////////////////////////////
+// Disable warning C4127: conditional expression is constant, which
+// is generated when using the _RPTF and _ASSERTE macros.
+#if (defined(_MSC_VER))
+#pragma warning(disable: 4127)
+#endif
+#if defined (__GNUC__)
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#ifdef _DEBUG
+#define T_ON TRUE
+#else
+#define T_ON FALSE
+#endif
+#define T_OFF FALSE
+
+#if !defined(TRACE_THREAD)
+#define TRACE_THREAD		T_OFF	// Print thread create/exit IDs
+#endif
+#define TRACE_HIGH_LEVEL	T_OFF
+#define TRACE_LOW_LEVEL		T_OFF
+#define TRACE_ERR			T_OFF
+#define TRACE_READS			T_OFF
+#define TRACE_STRAY			T_OFF
+#define TRACE_DESTRUCT		T_OFF	// Print construction/destruction
+
+// Read request time-out. All reads will be protected by this time-out.
+// The time-out is a balance of timing between excessive read thread processing
+// and the ability to close down the port at the end of port use. This time
+// will most likely be added to the destruction time of this object.
+#define READ_TIME_OUT_MS  200
+
+// Print ID in platform normal way
+#ifdef __unix
+#define THREAD_RADIX "%d"
+#else
+#define THREAD_RADIX "0x%x"
+#endif
+
+//*****************************************************************************
+//	NAME																	  *
+//		DUMP_PKT
+//
+//	DESCRIPTION:							
+//		Write buffer as hex debug string.
+//
+//	SYNOPSIS:
+void DUMP_PKT(const char *msg, packetbuf *buf) {
+	unsigned i, bLen;
+	//DisplayLock.Lock();
+	_RPT1(_CRT_WARN,"%s", msg);
+	if (buf->Byte.BufferSize > 20)
+		bLen = 20;
+	else
+		bLen = buf->Byte.BufferSize;
+	for (i=0; i<bLen; i++) {
+		_RPT1(_CRT_WARN,"%02x ", 0xff&buf->Byte.Buffer[i]);
+	}
+	_RPT0(_CRT_WARN,"\n");
+	//DisplayLock.Unlock();
+}
+//																			 *
+//****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx Construction/Destruction 
+//
+//	DESCRIPTION:							
+//		Write buffer as hex debug string.
+//
+//	SYNOPSIS:
+CSerialEx::CSerialEx()
+{
+	#if TRACE_THREAD || TRACE_DESTRUCT
+		_RPT0(_CRT_WARN, "CSerialEx constructing\n");
+	#endif
+	m_AppPacketAvailable = false;
+	m_nCharsRX = m_nCharsTX = 0;
+
+	// Insure all buffers look empty
+	m_lowInProcPacket.Byte.BufferSize = 0;
+	m_hiInProcPacket.Byte.BufferSize = 0;
+	
+	// Start up a plain old serial port
+	m_packetMode = false;
+	
+	// Nothing read yet
+	#ifdef _DEBUG
+		m_maxReadSize = 0;
+	#endif
+	#if RECORD_PKT_DEPTH
+		m_maxDepth = 0;
+	#endif
+
+	PacketParseReset();
+	m_pUserCommInterrupt = NULL;
+
+	// Create our event engine
+	m_pSerialEvts = new CSerialEvt(this);
+	
+	// ------------------------
+	// CThread initializations
+	// ------------------------
+	
+	// This is used in a DLL to implement a special exit strategy as
+	// we cannot wait on the thread handle to sync to it's death.
+	#if (defined(_WIN32)||defined(_WIN64))
+		SetDLLterm(true);
+	#endif
+}
+
+CSerialEx::~CSerialEx()
+{
+	// Prevent packet waiters from restarting
+	m_packetMode = false;
+	// Note: this does not exit on non-Windows system
+	if (m_pSerialEvts) {
+		delete m_pSerialEvts;
+		m_pSerialEvts = NULL;
+	}
+	// Kill the character read thread
+	CThread::Terminate();
+	m_responsePacketWaiting.SetEvent();
+	// Cancel pending OS I/O 
+	CancelCommIo();
+	m_rdEvent.SetEvent();
+	// Wait for read thread to exit
+	CThread::WaitForTerm();
+	#if TRACE_THREAD || TRACE_DESTRUCT
+		_RPT2(_CRT_WARN,"%.1f CSerialEx (destruction started), id=" THREAD_RADIX "\n",
+			infcCoreTime(), ThreadID());
+	#endif
+	Close();
+	// Kill any packets we have outstanding
+	m_SendPacketToAppLock.Lock();	
+	for (size_t i=0; m_finishedPackets.size(); i++) {
+		packetbuf *buf = m_finishedPackets.front();
+		m_finishedPackets.pop_front();
+		delete buf;
+	}
+	m_SendPacketToAppLock.Unlock();	
+	#if TRACE_THREAD || TRACE_DESTRUCT
+		_RPT1(_CRT_WARN,"%.1f CSerialEx (destroyed)\n", infcCoreTime());
+	#endif
+}
+//																			 *
+//****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx Open/Close  
+//
+//	DESCRIPTION:							
+//		Open and close the serial port hardware.
+//
+//	SYNOPSIS:
+#if (defined(_WIN32)||defined(_WIN64))
+CSerial::SERAPI_ERR CSerialEx::OpenComPort (long portNum)
+#else
+CSerial::SERAPI_ERR CSerialEx::OpenComPort (const char * portName)
+#endif
+{
+	// Call the base class first/ overlap enabled
+	#if (defined(_WIN32)||defined(_WIN64))
+		CSerial::SERAPI_ERR lLastError = CSerial::Open(portNum, READ_BUF_LEN, 64, true);
+	#else
+		CSerial::SERAPI_ERR lLastError = CSerial::Open(portName, 0, 0, true);
+	#endif
+	
+	if (lLastError != API_ERROR_SUCCESS)
+		return lLastError;
+	// Reset OS flags and state
+	//6/6/13 Flush();
+	// Start the listener thread
+	CSerial::EPort pErr;
+	pErr = StartListener();
+	if (pErr != CSerial::EPortAvailable) {
+		// Close the serial port
+		Close();
+
+		// Return the error-code
+		m_lLastError = API_ERROR_PORT_UNAVAILABLE;
+		return API_ERROR_PORT_UNAVAILABLE;
+	}
+	// Return the error
+	m_lLastError = API_ERROR_SUCCESS;
+	return API_ERROR_SUCCESS;
+}
+
+//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *
+
+CSerial::SERAPI_ERR CSerialEx::Close (void)
+{
+	// Stop listener thread (wait until it ends)
+	StopListener();
+	// Reset all members
+	m_responsePacketWaiting.SetEvent();
+	// Call the base class
+	return CSerial::Close();
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::TerminateAndWait
+//
+//	DESCRIPTION:
+///		Override CThread termination logic
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::TerminateAndWait()
+{
+	// Set terminate flag and release all waiting objects 
+	CThread::Terminate();
+	// Cancel any pending I/O
+	CancelCommIo();
+	// Setup for our specific cleanup, allow any external waiters to go
+	m_commEvent.SetEvent();
+	// Cancel new I/O that may have leaked through
+	CancelCommIo();
+	// Do base class work now
+	CThread::TerminateAndWait();
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::StartListener
+//
+//	DESCRIPTION:
+///		Start the read listening thread.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+CSerial::EPort CSerialEx::StartListener (void)
+{
+	// Start our event engine
+    #if TRACE_THREAD
+        _RPT1(_CRT_WARN, "%.1f CSerialEx::StartListener...\n", infcCoreTime());
+    #endif
+    if (m_pSerialEvts)
+		m_pSerialEvts->Restart();
+    #if TRACE_THREAD
+        _RPT1(_CRT_WARN, "%.1f CSerialEx::StartListener evt restarted...\n", infcCoreTime());
+    #endif
+    // Launch with elevated priority to insure responsiveness
+	LaunchThread(this, 1);
+    #if TRACE_THREAD
+        _RPT1(_CRT_WARN, "%.1f CSerialEx::StartListener launched...\n", infcCoreTime());
+    #endif
+	// Wait until running
+	m_ThreadParkedEvent.ResetEvent();
+	m_rdAck.WaitFor();
+    #if TRACE_THREAD
+        _RPT1(_CRT_WARN, "%.1f CSerialEx::StartListener started\n", infcCoreTime());
+    #endif
+	return(Terminating() ? EPortNotAvailable : EPortAvailable);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::StopListener
+//
+//	DESCRIPTION:
+///		Stop the read listening thread.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+LONG CSerialEx::StopListener (
+		DWORD dwTimeout)
+{
+    #if TRACE_THREAD
+        _RPT1(_CRT_WARN, "%.1f CSerial::StopListener...\n", infcCoreTime());
+    #endif
+	CThread::Terminate();
+	// Insure we release external waiters
+	m_responsePacketWaiting.SetEvent();
+	m_commEvent.SetEvent();
+	// Kill our thread
+	TerminateAndWait();
+    #if TRACE_THREAD
+        _RPT1(_CRT_WARN, "%.1f CSerial::StopListener stopped\n", infcCoreTime());
+    #endif
+	// Insure we release external waiters
+	m_responsePacketWaiting.SetEvent();
+	m_lLastError = API_ERROR_SUCCESS;
+	return API_ERROR_SUCCESS;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::TestAndPushHiPacket
+//
+//	DESCRIPTION:
+///		This will test for embedded high packet in another packet. If we
+///		are going to push this this function returns true.
+///
+///		Typical usage:
+///		void someStateFunc(char myChar) {
+///			if (TestAndPushHiPacket(myChar))
+///				return;
+///			// Keep processing
+///
+/// 	\param xxx description
+///		\return true if we are still processing
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool CSerialEx::TestAndPushHiPacket(char nextChar) {
+	register packetFields *parser = (packetFields *)&nextChar;
+	
+	// Not start of packet, no problem!
+	if (!parser->StartOfPacket)
+		return(false);
+		
+	// We have some start of packet, therefore the first octet's fields
+	// are OK.
+	
+	// Fragmented high-priority packet or low priority start in non-idle
+	if (inHighPrioState()  // Any "restart" in high-prio is bad
+	|| (!MN_PKT_IS_HIGH_PRIO(parser->PktType) && m_state != READ_STATE_IDLE)) {
+		// Create a Fragmentation Error
+		SendErrToApp(ND_ERRNET_FRAG, 0,0);
+		PacketParseReset();
+		// Reset processing and reparse this "start of packet"
+		ProcessNextChar(nextChar);
+		// Break recursion
+		return(true);
+	}
+	
+	// Start of packet / high priority type in regular packet
+	if (MN_PKT_IS_HIGH_PRIO(parser->PktType)) {
+		// Initialize the high priority packet buffer
+		m_hiPrioPktIndx = 0;
+		m_hiInProcPacket.Byte.Buffer[m_hiPrioPktIndx++] = nextChar;
+		// Assign maximum length until we get the length octet
+		m_hiInProcPacket.Fld.PktLen = MN_HDR_LEN_MASK;
+		m_hiChecksum = nextChar;
+		// We interrupted current state
+		m_pushedState = m_state;
+		// We get length next
+		m_state = READ_STATE_HP_PAYLOAD;
+		return(true);
+	}
+	return(false);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::ProcessNextChar
+//
+//	DESCRIPTION:
+///		This FSM will grab sequential characters from the serial port and 
+///		extract	any detected packets and signal the application when there 
+///		are some available.
+///
+/// 	\param xxx description
+///		\return true if we are still processing
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+inline void CSerialEx::ProcessNextChar(char nextChar)
+{
+#if TRACE_LOW_LEVEL
+	_RPT2(_CRT_WARN, "ProcessNextChar(%d): char 0x%02x\n",
+							m_state, nextChar);
+#endif
+	// Parser view of this char
+	packetFields *parser = (packetFields *)&nextChar;
+	// Try and extract the next packet.
+	switch(m_state) {
+	// --------------------------------------------------
+	// WAIT FOR PACKET START (IDLE)
+	// --------------------------------------------------
+	case READ_STATE_IDLE:
+		//we want to fill char 0 first
+		m_hiPrioPktIndx = m_lowPrioPktIndx = 0;
+		// do we have a start of packet?
+		if (parser->StartOfPacket) {
+			// if the stray packet count is > 0, send a stray error packet and zero 
+			// packet count; the data is contained in location [3] of m_strayCount
+			if (m_strayCount>0) {
+				// Construct a error packet: Type=2 (stray), Data=StrayOctetCnt
+				// Stray Error
+				SendErrToApp(ND_ERRNET_STRAY, 0, m_strayCount);
+				m_strayCount=0;
+				m_pushedState = READ_STATE_IDLE;
+			}
+			// Push processing 
+			if (TestAndPushHiPacket(nextChar))
+				break;
+			// low priority - cannot interrupt each other
+			m_lowInProcPacket.Byte.Buffer[m_lowPrioPktIndx++] = nextChar;
+			// Assign maximum length until we get the length octet
+			m_lowInProcPacket.Fld.PktLen = MN_HDR_LEN_MASK;
+			m_lowChecksum = nextChar;
+			m_state = READ_STATE_LP_PAYLOAD;
+		} 
+		else {
+			// Stray octet has been detected!
+			// Increment stray count; max count of 127
+			if (m_strayCount < 127) {
+				#if TRACE_STRAY
+					_RPT1(_CRT_WARN, "READ_STATE_IDLE: stray 0x%x\n", 
+									 nextChar);
+				#endif
+				m_strayCount++;
+			}
+		}
+		// we are done with this character - either thrown out or processed
+		break;
+		
+	// --------------------------------------------------
+	// PROCESS THE LOW PRIORITY PACKET
+	// --------------------------------------------------
+	case READ_STATE_LP_PAYLOAD:
+		//check to see if we are the start of a high priority packet
+		if (TestAndPushHiPacket(nextChar))
+			break;
+		#define PKT_OVERHEAD_LEN (MN_API_PACKET_HDR_LEN+MN_API_PACKET_TAIL_LEN)
+		// Accumulate characters and calculate the checksum 
+		m_lowInProcPacket.Byte.Buffer[m_lowPrioPktIndx++] = nextChar;
+		m_lowChecksum += nextChar;
+		// Have we reached the checksum?
+		if (m_lowPrioPktIndx >= m_lowInProcPacket.Fld.PktLen+PKT_OVERHEAD_LEN) {
+			#if TRACE_LOW_LEVEL
+			//	printf("Checksum calc:%X Checksum received: %X\n", m_checkSumCalc, m_lowInProcPacket.Byte.Buffer[m_lowInProcPacket.Fld.PktLen+2]);
+			#endif			
+			// Non-zero means corruption					
+			if(m_lowChecksum & 0x7F) {	
+				// Checksum Error!
+				SendErrToApp(ND_ERRNET_CHKSUM, m_lowInProcPacket.Fld.Addr, 0);
+			} 
+			else {
+				// Setup the character length
+				m_lowInProcPacket.Byte.BufferSize=m_lowPrioPktIndx;
+				#if TRACE_LOW_LEVEL
+				DUMP_PKT("LO pkt", &m_lowInProcPacket);
+				#endif
+				// Send the packet to app and wait until it reads it
+				SendPacketToApp(m_lowInProcPacket,true);
+			}
+			// We are done, go idle
+			m_state = READ_STATE_IDLE;
+		}
+		break;
+	// --------------------------------------------------
+	// PROCESS THE HIGH PRIORITY PACKET
+	// --------------------------------------------------
+	case READ_STATE_HP_PAYLOAD:
+		if (TestAndPushHiPacket(nextChar))
+			break;
+		// Accumulate characters and calculate the checksum 
+		m_hiInProcPacket.Byte.Buffer[m_hiPrioPktIndx++] = nextChar;
+		m_hiChecksum += nextChar;
+		// Have we reached the checksum?
+		 if (m_hiPrioPktIndx >= m_hiInProcPacket.Fld.PktLen+PKT_OVERHEAD_LEN) {
+			// Non-zero means corruption					
+			if(m_hiChecksum & 0x7F) {
+				// Checksum Error!
+				SendErrToApp(ND_ERRNET_CHKSUM, m_hiInProcPacket.Fld.Addr,0 );
+			} 
+			else {
+				// Setup the character length
+				m_hiInProcPacket.Byte.BufferSize=m_hiPrioPktIndx;
+				#if TRACE_LOW_LEVEL
+				DUMP_PKT("HI pkt", &m_hiInProcPacket);
+				#endif
+				// Send the packet to app and wait until it reads it
+				SendPacketToApp(m_hiInProcPacket,true);
+			}
+			// Return to last processing state
+			m_state = m_pushedState;
+			m_pushedState = READ_STATE_IDLE;
+			m_hiPrioPktIndx = 0;
+		}
+		break;
+	default:
+		_RPT1(_CRT_ASSERT, "CSerialEx::ProcessNextChar unknown state %d\n", m_state);
+		PacketParseReset();
+		// Process the low priority packet
+		break;
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::Run
+//
+//	DESCRIPTION:
+///		Background thread to collect characters from the serial port and 
+///		packetize them for the upper packet processing thread.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+int CSerialEx::Run(void *context)
+{
+	// Packet parsing current character
+	char thisChar;
+	
+	// Port event statististics
+	#if TRACE_THREAD || TRACE_DESTRUCT
+		_RPT2(_CRT_WARN, "%.1f CSerialEx::Run thread id=" THREAD_RADIX " starting\n", 
+							infcCoreTime(), CurrentThreadID());
+	#endif
+	// Initiate the Wait Comm Event waiter on:
+	//		 break detect, errors and data reception
+	SetEventMask(EEventBreak|EEventError|EEventRecv|EEventCTS);
+	// Start the event engine if it exists
+	if (m_pSerialEvts) {
+		// First let it get to ::Run function
+		m_pSerialEvts->WaitForParked();
+		m_pSerialEvts->Restart();
+	}
+	// Signal we are running
+	m_rdAck.SetEvent();
+#if TRACE_THREAD || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f CSerialEx::Run thread id=" THREAD_RADIX " looping\n", 
+						infcCoreTime(), CurrentThreadID());
+#endif
+			
+	// Keep looping until big error or StopListener kills us
+	do {
+		// Park here until the event thread wakes us up
+#if (defined(_WIN32)||defined(_WIN64))
+		m_ThreadParkedEvent.WaitFor();
+		//_RPT0(_CRT_WARN,"w");
+		// Let event set us
+		m_ThreadParkedEvent.ResetEvent();
+#endif
+		// Stop processing if terminating
+		if (Terminating()) {
+			#if TRACE_DESTRUCT
+				_RPT1(_CRT_WARN, "%.1f CSerialEx::Run terminating post restart\n", infcCoreTime());
+			#endif
+			break;
+		}
+		// Read into our empty buffer
+		m_rdBuffer.lock();
+		#ifdef _DEBUG
+			// Save last bucket size for diagnostic purposes
+			m_lastReadSize = m_readSize;
+		#endif
+		while (Read(m_rdBuffer.tailPtr(), m_rdBuffer.charsLeft(),
+			&m_readSize, READ_TIME_OUT_MS)) {
+			if (Terminating()) {
+				m_rdBuffer.unlock();
+				goto exit_pt;
+			}
+		}
+
+		//_RPT1(_CRT_WARN,"r%d ", m_readSize);
+		// Store stuff if we had a successful read and not flushing
+		if (m_readSize) {
+			if (!m_rdAutoFlush) {
+				// Make them available in the buffer
+				m_rdBuffer.makeAvailable(m_readSize);
+				m_nCharsRX += m_readSize;
+			}
+			else
+				m_rdBuffer.flush();
+		}
+		m_rdBuffer.unlock();
+		#ifdef _DEBUG
+			// Save peak read size for diagnostic purposes
+			if (m_maxReadSize < m_readSize) 
+				m_maxReadSize = m_readSize;
+		#endif
+		// Process any buffer items based on operational mode
+		if (m_packetMode) {
+			// Process all the characters in our buffer
+			while(m_rdBuffer.getChar(thisChar) && !((m_pTermFlag != NULL) && (*m_pTermFlag)) && !m_rdAutoFlush) {
+				#ifdef _DEBUG
+					static bool dbg=false;
+					if (dbg)
+						_RPT1(_CRT_WARN, "chr=0x%02x\n", 0xff&thisChar);
+				#endif
+				ProcessNextChar(thisChar);
+			}
+			// Reset the buffer for next read
+			m_rdBuffer.flush();
+		}
+	} while (!Terminating());
+exit_pt:
+	// Kill any I/O pending to prevent issues as port closes
+	CancelCommIo();
+	// Wait for the cancel to occur
+	//m_commEvent.WaitFor();
+	#if TRACE_THREAD || TRACE_DESTRUCT
+		_RPT2(_CRT_WARN, "%.1f CSerialEx::Run thread id=" THREAD_RADIX
+						 " exiting\n",
+						infcCoreTime(), ThreadID());
+	#endif
+	return (API_ERROR_SUCCESS);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::ProcessEvent
+//
+//	DESCRIPTION:
+/**		
+	Process this event. This is normally fed from the event detection thread.
+
+ 	\param[in,out] xxx description
+	\return description
+ 
+**/
+//	SYNOPSIS:
+void CSerialEx::ProcessEvent(EEvent eEvent)
+{
+	//#ifdef _DEBUG
+	//if (eEvent & 0xfe)
+	//	_RPT2(_CRT_WARN, "%.1f CSerialEx::Run evt=" THREAD_RADIX "\n", infcCoreTime(), eEvent);
+	//#endif
+	// There was a COMM event, which needs handling. We'll call the
+	// appropriate event handler(s). 
+	if (eEvent) { 
+		// We have received some data, restart the read thread
+		if((eEvent & CSerial::EEventRecv)) {
+			//_RPT1(_CRT_WARN, "%.1f CSerialEx::incr rx char\n", infcCoreTime());
+			INCREMENT_ERRORCNT(m_ErrorReport.RXCHARcnt);
+			//_RPT0(_CRT_WARN,"*");
+			m_ThreadParkedEvent.SetEvent();
+		}
+		// We received a CTS changed event.
+		// We are only interested in the CTS falling edge events
+		if((eEvent & CSerial::EEventCTS) && !GetCTS()) {
+			//_RPT0(_CRT_WARN, "CSerialEx::Run got CTS fall\n");
+			INCREMENT_ERRORCNT(m_ErrorReport.CTScnt);
+			m_ThreadParkedEvent.SetEvent();
+		}
+		// We received the break condition, baud rate changed
+		// and note we received one.
+		if((eEvent & CSerial::EEventBreak)) {
+			//_RPT0(_CRT_WARN, "CSerialEx::Run got break\n");
+			INCREMENT_ERRORCNT(m_ErrorReport.BREAKcnt);
+		}
+		// Some port error was detected, log each one, if not break!
+		else if((eEvent & CSerial::EEventError)) {
+			// Obtain the error status during this event
+			CSerial::EError eError = GetError();
+			if (eError & (CSerial::EErrorRxOver | CSerial::EErrorOverrun)) {
+				// Port Overrun
+				INCREMENT_ERRORCNT(m_ErrorReport.ERR_OVERRUNcnt);
+				SendErrToApp(ND_ERRNET_PORT_OVERRUN,0,0);
+				_RPT1(_CRT_WARN, "%.1f CSerialEx::RX overrun\n", infcCoreTime());
+				Purge();
+				eError = (CSerial::EError)(eError & ~(CSerial::EErrorRxOver | CSerial::EErrorOverrun));
+			}
+			if (eError & (CSerial::EErrorBreak | CSerial::EErrorFrame)) {
+				// Ignoring this case as break sometimes appears as this
+				// condition
+				if (!m_breakSent && !m_rdAutoFlush) {
+					_RPT1(_CRT_WARN, "%.1f CSerialEx::Framing Error\n", infcCoreTime());
+					INCREMENT_ERRORCNT(m_ErrorReport.ERR_FRAMEcnt);
+					SendErrToApp(ND_ERRNET_FRAME, 0, 0);
+				}
+				#if _DEBUG
+				else _RPT1(_CRT_WARN, "%.1f CSerialEx::Framing Error(expected)\n", infcCoreTime());
+				#endif
+
+				// Reset filter
+				m_breakSent = false;
+				eError = (CSerial::EError)(eError & ~(CSerial::EErrorBreak | CSerial::EErrorFrame));
+			}
+			if (eError) {
+				// Skip the rest
+				_RPT2(_CRT_WARN, "%.1f CSerialEx::eError %d\n", infcCoreTime(), eError);
+			}
+		}
+	} // if (eEvent)
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+//*****************************************************************************
+//*****************************************************************************
+//                          PACKET ORIENTED API
+//*****************************************************************************
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::SendPacketToApp
+//
+//	DESCRIPTION:
+///		Send the <thePacket> to the application layer.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::SendPacketToApp(packetbuf &thePacket, BOOL Convert7To8Bit)
+{
+
+#if TRACE_READS
+	{
+		_RPT1(_CRT_WARN, "%.1f SendPacketToApp(Start): ", infcCoreTime());
+		for (unsigned i=0; i<thePacket.Byte.BufferSize; i++) {
+			_RPT1(_CRT_WARN, "%02X+", 0xff&thePacket.Byte.Buffer[i]);
+		}
+	}
+#endif
+	if (m_pUserCommInterrupt && !m_rdAutoFlush) {
+		// We are going to use this packet, stash it in heap
+		packetbuf *pkt = new packetbuf;
+		// Copy to internal buffer with proper conversion if required.
+		if (Convert7To8Bit) {
+			convert7to8(thePacket, *pkt);
+		}
+		else {
+			*pkt = thePacket;
+		}
+		// Lock GetPkt state until we finish setup
+		m_SendPacketToAppLock.Lock();	
+		// We want to actually send, queue to back
+		m_finishedPackets.push_back(pkt);
+		// Tell application layer we have something new
+		m_AppPacketAvailable = true;
+		m_responsePacketWaiting.SetEvent();
+		if (m_pUserCommInterrupt)
+			m_pUserCommInterrupt->SetEvent();
+		// Allow interactions with m_AppPacketAvailable & m_finishedPackets
+		m_SendPacketToAppLock.Unlock();
+	}
+	else {
+		// Flush everything we have
+		Flush();
+	}
+	//_RPT0(_CRT_WARN,"e");
+#if TRACE_READS
+	_RPT0(_CRT_WARN, "SendPacketToApp(End)\n");
+#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::SendErrToApp
+//
+//	DESCRIPTION:
+///		Create and queue an error packet back to application layer.
+///
+/// 	\param errorType type of error to return
+/// 	\param addr address to report error at
+/// 	\param data extra information to report
+///		\return true if we have data, else was a timeout and no data.
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::SendErrToApp(mnNetErrs errorType, unsigned addr, unsigned data)
+{
+	// Construct a error packet: Type=0 (frag)
+	packetbuf errpacket;
+	errpacket.Fld.Addr=addr;
+	errpacket.Fld.Mode=errpacket.Fld.Zero1=0;
+	// Host initiated error
+	errpacket.Fld.Src=MN_SRC_HOST;
+	errpacket.Fld.PktType = MN_PKT_TYPE_ERROR;
+	errpacket.Fld.PktLen = 2;				// Payload size
+	// Total packet size (includes header and length fields)
+	errpacket.Byte.BufferSize = errpacket.Fld.PktLen + MN_API_PACKET_HDR_LEN;		
+	errpacket.Byte.Buffer[RESP_LOC] = (nodechar)errorType;
+	errpacket.Byte.Buffer[RESP_LOC+1] = (nodechar)data;
+	SendPacketToApp(errpacket, false);
+	#if TRACE_ERR
+	_RPT3(_CRT_WARN,"CSerialEx::SendErrToApp: errorType = %d ; addr = %d ; data = %d\n",
+					 errorType,addr,data);
+	#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::GetPkt
+//
+//	DESCRIPTION:
+///		Wait for and get the oldest packet received.
+///
+/// 	\param buffer buffer to copy data into
+///		\return true if we have data, else was a timeout and no data.
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool CSerialEx::GetPkt(packetbuf &buffer)
+{
+#if TRACE_HIGH_LEVEL
+	_RPT1(_CRT_WARN, "%.1f CSerialEx::GetPkt...(start)\n", infcCoreTime());
+#endif
+	if (m_packetMode) {
+		// Wait for one to show up or time-out
+		if (m_responsePacketWaiting.WaitFor(FRAME_READ_TIMEOUT+500)) {
+			//_RPT1(_CRT_WARN, "%.1f CSerialEx::GetPkt...got!\n", infcCoreTime());
+			//_RPT0(_CRT_WARN, ".\n");
+			// Copy our buffer to the caller
+			m_SendPacketToAppLock.Lock();
+#if RECORD_PKT_DEPTH
+			if (m_finishedPackets.size() > m_maxDepth) {
+				m_maxDepth = m_finishedPackets.size();
+				//_RPT1(_CRT_WARN, "SerialEx max rx depth=%d pkts\n", m_maxDepth);
+			}
+#endif
+			if (m_finishedPackets.size()) {
+				packetbuf *pkt = m_finishedPackets.front();
+				#if TRACE_LOW_LEVEL
+					DUMP_PKT("SerialEx: <= ", pkt);
+				#endif
+				buffer = *pkt;
+				delete pkt;
+				m_finishedPackets.pop_front();
+				// Setup app layer for next read if we have them and not terminating
+				if ((m_finishedPackets.size()==0) || Terminating()) {
+					m_AppPacketAvailable = false;
+					m_responsePacketWaiting.ResetEvent();
+					if (m_pUserCommInterrupt) 
+						m_pUserCommInterrupt->ResetEvent();
+				}
+				m_SendPacketToAppLock.Unlock();	
+				#if TRACE_HIGH_LEVEL
+					_RPT1(_CRT_WARN, "%.1f CSerialEx::GetPkt...(OK)!\n", infcCoreTime());
+				#endif
+				return(true);
+			}
+			else {
+				m_SendPacketToAppLock.Unlock();
+			}
+		} 
+		else {
+			//_RPT1(_CRT_WARN, "%.1f CSerialEx::GetPkt...timeout!\n", infcCoreTime());
+			buffer.Byte.BufferSize = 0;
+			m_responsePacketWaiting.ResetEvent();
+			if (m_pUserCommInterrupt) 
+				m_pUserCommInterrupt->ResetEvent();
+		}
+	}
+#if TRACE_HIGH_LEVEL
+	_RPT1(_CRT_WARN, "%.1f CSerialEx::GetPkt...(fail)!\n", infcCoreTime());
+#endif
+	// If not processed we failed
+	return(false);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::SendPkt
+//
+//	DESCRIPTION:
+///		Send the packet to the serial ring channel in an atomic fashion.
+///
+/// 	\param xxx description
+///		\return TRUE on success
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool CSerialEx::SendPkt(packetbuf &buffer)
+{
+	CSerial::SERAPI_ERR result=API_ERROR_SUCCESS;
+	DWORD nWritten;
+	packetbuf sendBuf;							// Local thread safe copy
+	
+	// Clean start of packet
+	buffer.Byte.Buffer[0] |= 0x80;			// Set start of packet
+	buffer.Byte.Buffer[1] &= ~(0x80);			// Insure length field MSB clear
+
+	convert8to7(buffer, sendBuf);				// Convert to channel format
+
+	// Send link formatted command to the port
+	result = Write(sendBuf.Byte.Buffer, sendBuf.Byte.BufferSize,
+							&nWritten);
+	m_nCharsTX += nWritten;
+	if (result!=API_ERROR_SUCCESS) {
+		_RPTF1(_CRT_WARN,"CSerial::SendPkt - err 0x%x\n", (unsigned int)result);		
+		m_lLastError = result;			
+	} 
+	return(result==API_ERROR_SUCCESS);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::IsPacketAvailable
+//
+//	DESCRIPTION:
+///		Returns true if a packet is available.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool CSerialEx::IsPacketAvailable(void)
+{
+	bool avail;
+	//m_SendPacketToAppLock.Lock();
+	avail = m_AppPacketAvailable;
+	//m_SendPacketToAppLock.Unlock();	
+	return(avail && m_packetMode);
+}
+//																			  *
+//*****************************************************************************
+
+bool CSerialEx::Send_Available()
+{
+	return true;	// To be modified if we use threaded write
+}
+
+//*****************************************************************************
+//*****************************************************************************
+//                          PLAIN SERIAL PORT API
+//*****************************************************************************
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::GetChar
+//
+//	DESCRIPTION:
+///		Get the oldest buffered character. If we have a character, the function
+///		returns true.
+///
+/// 	\param xxx description
+///		\return true if we got our character
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool CSerialEx::GetChar(char *theChar)
+{
+	DWORD nRead;
+	LONG retErr;
+	// This API works only in serial port mode
+	if (!m_packetMode) {
+		//// getChar returns TRUE if we get char OK
+		//return m_rdBuffer.getChar(*theChar);
+		retErr = Read(theChar, 1, &nRead, 100);
+		m_nCharsRX += nRead;
+		return (retErr==0) && (nRead==1);
+	}
+	return false;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::SendChars
+//
+//	DESCRIPTION:
+///		Atomically send the characters.
+///
+/// 	\param xxx description
+///		\return true if sucessfully queued.
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool CSerialEx::SendChars(char *theChars, unsigned int charsLen)
+{
+	LONG result;
+	DWORD nWritten;
+	result = Write(theChars, charsLen, &nWritten);
+	m_nCharsTX += nWritten;
+	if (result != API_ERROR_SUCCESS || charsLen != (unsigned int)nWritten) {
+		_RPTF1(_CRT_WARN, "CSerialEx::SendChars failed %d\n", (int)result);
+		return(false);
+	}
+	return (true);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::Set/GetMode
+//
+//	DESCRIPTION:
+///		Set/Get the serial port operational mode: packets or plain old
+///		serial port.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::SetMode(CSerialMode theNewMode)
+{
+	switch (theNewMode) {
+	case SERIALMODE_MERIDIAN_7BIT_PACKET:
+		m_packetMode = true;
+		if (m_pSerialEvts)
+			m_pSerialEvts->Start();
+		break;
+	case SERIALMODE_SERIAL:
+		m_packetMode = false;
+		if (m_pSerialEvts)
+			m_pSerialEvts->Stop();
+		break;
+	default:
+		_RPTF1(_CRT_ASSERT, "CSerialEx::SetMode unsupported type %d\n", theNewMode);
+		break;
+	}
+}
+
+CSerialMode CSerialEx::GetMode()
+{
+	return m_packetMode ? SERIALMODE_MERIDIAN_7BIT_PACKET 
+						: SERIALMODE_SERIAL;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::AutoFlush
+//
+//	DESCRIPTION:
+///		Cancel all work in process and flush the characters waiting in the
+///		serial port hardware.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::AutoFlush(bool mode) {
+	m_rdAutoFlush = mode;
+	// If flushing, make sure packets waiting are released
+	//if (mode) {
+	//	
+	//}
+};
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::Flush
+//
+//	DESCRIPTION:
+///		Cancel all work in process and flush the characters waiting in the
+///		serial port hardware.
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::Flush()
+{
+#if TRACE_READS
+	_RPT0(_CRT_WARN,"CSerialEx::Flush()\n");
+#endif
+	bool autoIn = m_rdAutoFlush;
+	// Start ignoring the data
+	AutoFlush(true);
+
+	// Prevent packet waiters from restarting
+	m_responsePacketWaiting.ResetEvent();
+	// Let stuff pile up
+	CThread::Sleep(100);
+	// Make sure all the events are cleared
+	GetError();
+	// Kill serial traffic accumulated
+	m_SendPacketToAppLock.Lock();	
+	m_rdBuffer.flush();
+	for (size_t i=0; m_finishedPackets.size(); i++) {
+		packetbuf *buf = m_finishedPackets.front();
+		m_finishedPackets.pop_front();
+		delete buf;
+	}
+	m_responsePacketWaiting.ResetEvent();
+	// Restart the packet parser
+	PacketParseReset();
+	m_SendPacketToAppLock.Unlock();
+	// Clear OS queue
+	Purge();
+#if 0
+	// Clear pending events
+	SetEventMask(0);
+	// Start looking again for breaks
+	SetEventMask();
+#endif
+	// Allow our read thread to grab data
+	AutoFlush(autoIn);
+}
+//																			  *
+//*****************************************************************************
+
+
+void CSerialEx::ErrorReportClear()
+{
+	m_ErrorReport.clear();
+}
+//																			  *
+//*****************************************************************************
+
+void CSerialEx::ErrorReportGet(CSerialExErrReportInfo *pErrorReport)
+{
+	*pErrorReport = m_ErrorReport;
+}
+//																			  *
+//*****************************************************************************
+/*****************************************************************************
+ *	!NAME!
+ *		cpymem
+ *		
+ *	DESCRIPTION:
+ *		This function will copy nchars of memory from <src> to <dest>.
+ *
+ *	RETURNS:
+ *		cnErrCode error code
+ *		
+ *	SYNOPSIS: 															    */
+__inline void CSerialEx::cpymem(
+		nodechar *src, 
+		nodechar *dest, 
+		nodeushort nchars)
+{
+	while (nchars--)
+		*(dest++) = *(src++);
+}
+//																			  *
+//*****************************************************************************
+
+
+// This function should allow intentional misconduct by having the
+// buffer length not related to packet header length+overhead. If allowed
+// this function can be used to test buffer and network proceeing by
+// allowing fragmented packets to be transmitted as well as stray data.
+void CSerialEx::convert8to7(packetbuf& inBuf, packetbuf& outBuf)
+{
+	// we copy the first 2 bytes without translation
+	outBuf.Byte.Buffer[0] = inBuf.Byte.Buffer[0];
+	outBuf.Byte.Buffer[1] = inBuf.Byte.Buffer[1];
+
+	nodechar *s = &inBuf.Byte.Buffer[2];
+	nodechar *d = &outBuf.Byte.Buffer[2];
+	nodechar *origD = d;
+	unsigned long chksum = 0;
+
+	// Allow caller to lie about length to create frag or stray data
+	int num8 = inBuf.Fld.PktLen;
+	int consumeBytes;
+	int outBytes;
+
+	while(num8 > 0){
+		consumeBytes = num8 >= 7 ? 7 : num8;
+		outBytes = consumeBytes + 1;
+		switch(outBytes) {
+			case 8: d[7] = 0x7f &				 ((unsigned char)s[6] >> 1);
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 7: d[6] = 0x7f & ((s[6] << 6) | ((unsigned char)s[5] >> 2));
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 6: d[5] = 0x7f & ((s[5] << 5) | ((unsigned char)s[4] >> 3));
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 5: d[4] = 0x7f & ((s[4] << 4) | ((unsigned char)s[3] >> 4));
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 4: d[3] = 0x7f & ((s[3] << 3) | ((unsigned char)s[2] >> 5));
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 3: d[2] = 0x7f & ((s[2] << 2) | ((unsigned char)s[1] >> 6));
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 2: d[1] = 0x7f & ((s[1] << 1) | ((unsigned char)s[0] >> 7));
+			// no break OK (special line for Code Analyzer to suppress warning)
+			case 1: d[0] = 0x7f &   s[0];
+			// no break OK (special line for Code Analyzer to suppress warning)
+		}
+		d += outBytes;
+		s += consumeBytes;
+		num8 -= consumeBytes;
+	}
+	// Adjusts output header for expansion due to 8->7
+	outBuf.Fld.PktLen = (d - origD);
+	// Adjust packet buffer size for expansion due to 8->7 + checksum append
+	// 64-bit OK, buffer small always
+	outBuf.Byte.BufferSize = (nodeulong)(inBuf.Byte.BufferSize 
+		+ (d - origD)-inBuf.Fld.PktLen
+		+ MN_API_PACKET_TAIL_LEN);
+	for(unsigned i=0;i<(outBuf.Fld.PktLen+2U);i++) {
+		chksum+=outBuf.Byte.Buffer[i];
+	}
+	chksum = (-1*chksum)&0x7f;
+	outBuf.Byte.Buffer[outBuf.Fld.PktLen+2] = (nodechar) chksum;
+}
+//																			  *
+//*****************************************************************************
+
+void CSerialEx::convert7to8(packetbuf& inBuf, packetbuf& outBuf)
+{
+	// we copy the header without translation
+	outBuf.Byte.Buffer[0] = inBuf.Byte.Buffer[0];
+	outBuf.Byte.Buffer[1] = inBuf.Byte.Buffer[1];
+
+
+	int num7 = inBuf.Fld.PktLen;
+
+	nodechar *buf7 = &inBuf.Byte.Buffer[RESP_LOC];
+	nodechar *d = &outBuf.Byte.Buffer[RESP_LOC];
+	nodechar *origD = d;
+
+	int i, mod8;
+	for(i = 0; i < num7; ++i) {
+		mod8 = 0x07 & i;
+		*d |= 0xff & (buf7[i] << (8 - mod8));
+		d += mod8 != 0;			// inc. d 7 out of 8 times
+		*d = buf7[i] >> mod8;
+	}
+	
+	outBuf.Fld.PktLen = (num7==1) ? 1: d - origD;
+	outBuf.Byte.BufferSize=outBuf.Fld.PktLen+MN_API_PACKET_HDR_LEN;
+
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEx::RegisterUserPktCommEvent
+//
+//	DESCRIPTION:
+///		
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void CSerialEx::RegisterUserPktCommEvent(CCEvent *pUsersEvent)
+{
+	m_pUserCommInterrupt = pUsersEvent;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEvt::CSerialEvt
+//
+//	DESCRIPTION:
+/**		
+	This class polls for serial port events via a thread and wakes up any
+	appropriate threads to handle the event.
+
+ 	\param[in,out] xxx description
+	\return description
+ 
+**/
+//	SYNOPSIS:
+CSerialEvt::CSerialEvt(CSerialEx *pOwner)
+{
+#if TRACE_DESTRUCT
+	_RPT1(_CRT_WARN, "%.1f CSerialEvt constructing...\n", infcCoreTime());
+#endif
+	// Object we interact with for events.
+	pPort = pOwner;
+	m_paused = false;
+	// Pause at startup
+	m_ThreadParkedEvent.ResetEvent();
+	#if (defined(_WIN32)||defined(_WIN64))
+		SetDLLterm(true);
+	#endif
+	LaunchThread(this,1);
+}
+CSerialEvt::~CSerialEvt()
+{
+#if TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f CSerialEvt destroying...id=" THREAD_RADIX "\n",
+			infcCoreTime(), ThreadID());
+#endif
+	// Insure waiters are released
+	m_paused = false;
+	m_parkAck.SetEvent();
+	Terminate();
+	pPort->ForceCommEvent();
+	TerminateAndWait();
+	pPort = NULL;
+#if TRACE_DESTRUCT
+	_RPT1(_CRT_WARN, "%.1f CSerialEvt destroyed\n", infcCoreTime());
+#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEvt::Run
+//
+//	DESCRIPTION:
+/**		
+	This thread polls for events detected by the serial port.  When certain
+	ones are found the owner serial port is notified.
+
+ 	\param[in,out] xxx description
+	\return description
+ 
+**/
+//	SYNOPSIS:
+int CSerialEvt::Run(void *context)
+{
+	LONG lastError;
+	// Signal we are at park state
+	m_parkAck.SetEvent();
+#if TRACE_DESTRUCT||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f CSerialEvt::Run parked, id=" THREAD_RADIX "...\n",
+		infcCoreTime(), ThreadID());
+#endif
+	// Wait for a signal from read thread to start
+	m_ThreadParkedEvent.WaitFor();
+#if TRACE_DESTRUCT||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f CSerialEvt::Run restarted, id=" THREAD_RADIX "...\n",
+			infcCoreTime(), ThreadID());
+#endif
+	while (!Terminating()) {
+		// Start another wait for event
+		if ((lastError = pPort->CommEventWaitInitiate()) != 0) {
+#ifdef _DEBUG
+			if (pPort->IsOpen() && !Terminating())
+				_RPT1(_CRT_WARN, "CSerialEvt::Run CommEventWaitInitiate failed,err=%d\n", lastError);
+#endif
+			break;
+		}
+		// We don't care if this fails, causes a periodic poll
+		#if (defined(_WIN32)||defined(_WIN64))				// TODO 9/22/10 DS Why not Linux (Rvw? no-events?)!
+			/*bool waitOK = */pPort->WaitForCommEvent(INFINITE);
+		#endif
+		// Exiting?
+		if (Terminating())
+			break;
+		// Determine the event
+			CSerial::EEvent eEvent = pPort->GetEventType();
+		//_RPT2(_CRT_WARN,"%.1f SerEvt 0x%x\n", infcCoreTime(), eEvent);
+		if (!m_paused) 
+			pPort->ProcessEvent(eEvent);
+		else {
+			//_RPT1(_CRT_WARN, "%.1f CSerialEvt::Run paused\n",
+			//	 infcCoreTime());
+			// Signal we are at park state
+			m_parkAck.SetEvent();
+			m_ThreadParkedEvent.ResetEvent();
+		}
+		// Pause control
+		m_ThreadParkedEvent.WaitFor();
+	}
+#if TRACE_DESTRUCT||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f CSerialEvt::Run exiting, id=" THREAD_RADIX "...\n",
+			infcCoreTime(), ThreadID());
+#endif
+	return(0);
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CSerialEvt::Start/Stop
+//
+//	DESCRIPTION:
+/**		
+	Cause the event loop to pause or restart.
+
+ 	\param[in,out] xxx description
+	\return description
+ 
+**/
+//	SYNOPSIS:
+void CSerialEvt::Start() 
+{
+	m_paused = false;
+	m_ThreadParkedEvent.SetEvent();
+	//_RPT0(_CRT_WARN, "CSerialEvt::Start\n");
+}
+
+void CSerialEvt::Stop() 
+{
+	m_paused = true;
+	//_RPT0(_CRT_WARN, "CSerialEvt::Stop\n");
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+#if 0
+ Comm event handling from CSerialEx::Run we are not using
+				if((eEvent & CSerial::EEventCTS)) {
+					INCREMENT_ERRORCNT(m_ErrorReport.CTScnt);
+				};
+
+				if((eEvent & CSerial::EEventDSR)) {
+					INCREMENT_ERRORCNT(m_ErrorReport.DSRcnt);
+				};
+				if((eEvent & CSerial::EEventRing)) {
+					INCREMENT_ERRORCNT(m_ErrorReport.RINGcnt);
+				};
+
+				if((eEvent & CSerial::EEventRLSD)) {
+					INCREMENT_ERRORCNT(m_ErrorReport.RLSDcnt);
+				};
+
+				if((eEvent & CSerial::EEventRcvEv)) {
+					INCREMENT_ERRORCNT(m_ErrorReport.RXFLAGcnt);
+				};
+				// FIFO / buffer @ 80% full (TODO?)
+				if((eEvent & CSerial::EEventRx80Full)) {
+					INCREMENT_ERRORCNT(m_ErrorReport.RX80FUllcnt);
+				}
+#endif
+
+//============================================================================= 
+//	END OF FILE SerialEx.cpp
+//=============================================================================
+
+
+
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/converterLib.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/converterLib.cpp
new file mode 100644
index 000000000..747501ecf
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/converterLib.cpp
@@ -0,0 +1,352 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC-1.0.123/User Driver/src/converterLib.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: converterLib.cpp $
+/// \cond INTERNAL_DOC
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	\brief Useful functions to convert node's native units to standard
+	values and back.
+
+	These functions must utilize only common MN_P style parameters and
+	the incoming referenced parameter for their function. This allows
+	them to be used on any node class.
+**/
+//
+// CREATION DATE:
+//		2012-03-14 14:26:32
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2012-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	converterLib.cpp headers
+//
+	#include "converterLib.h"
+	#include "netCmdPrivate.h"
+	#include "netCmdAPI.h"
+	#include <math.h>
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	converterLib.cpp function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	converterLib.cpp constants
+//
+//
+#if defined (__GNUC__)
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	converterLib.cpp static variables
+//
+// 
+
+//																			  *
+//*****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		convertAcc
+//
+//	DESCRIPTION:
+//		This function converts to and from ticks/second and ticks/sample-time.
+//
+//	RETURNS:
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL convertAcc(				// ticks/sample-time <=> ticks/sec
+	nodebool valIsBits, 				// TRUE=>ticks/sample-time, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData)
+{
+	paramValue sampleTime;				
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_SAMPLE_PERIOD,
+							      NULL, &sampleTime);
+	// Avoid divide-by-0 problems and other errors
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(0);
+
+	if (valIsBits)  {
+		return(1e12 * convVal / (sampleTime.value * sampleTime.value));
+	}
+	else {
+		// convVal in ms => us / # us/sample-time
+		return(1e-12 * convVal * sampleTime.value * sampleTime.value);
+	}
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertSquared
+//
+//	DESCRIPTION:
+//		This function converts values represented as the square of their
+//		actual value to and from its normal state.
+//
+//	RETURNS:
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL convertSquared(			// sample-times <=> milliseconds
+	nodebool valIsBits, 				// TRUE=>sample-times, FALSE=>ms
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData)
+{
+	if (valIsBits)  {
+		if (convVal<0)
+			return(0);
+		// Return x^.5
+		return(sqrt(convVal));
+	}
+	else {
+		// Return x^2
+		return(convVal*convVal);
+	}
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertTimeMS
+//
+//	DESCRIPTION:
+//		This function converts sample-times to milliseconds based on the
+//		MN_SAMPLE_PERIOD parameter.
+//
+//	RETURNS:
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL convertTimeMS(			// sample-times <=> milliseconds
+	nodebool valIsBits, 				// TRUE=>sample-times, FALSE=>ms
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData)
+{
+	paramValue sampleTime;				
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_SAMPLE_PERIOD,
+							      NULL, &sampleTime);
+	// Avoid divide-by-0 problems and other errors
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(0);
+
+	if (valIsBits)  {
+		// Return sample-times in milliseconds
+		return(convVal * .001 * sampleTime.value);
+	}
+	else {
+		// convVal in ms => us / # us/sample-time
+		return((long)((1000 * convVal / sampleTime.value)+0.5));
+	}
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertVel
+//
+//	DESCRIPTION:
+//		This function converts to and from ticks/second and ticks/sample-time.
+//
+//	RETURNS:
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL convertVel(				// ticks/sample-time <=> ticks/sec
+	nodebool valIsBits, 				// TRUE=>ticks/sample-time, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData)
+{
+	paramValue sampleTime;				
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_SAMPLE_PERIOD,
+							      NULL, &sampleTime);
+	// Avoid divide-by-0 problems and other errors
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(0);
+
+	if (valIsBits)  {
+		return(1e6 * convVal / sampleTime.value);
+	}
+	else {
+		// convVal in ms => us / # us/sample-time
+		return(1e-6 * convVal * sampleTime.value);
+	}
+}
+/****************************************************************************/
+
+
+
+//****************************************************************************
+//	NAME
+//		convertVelRound
+//
+//	DESCRIPTION:
+//		This function converts to and from ticks/second and ticks/sample-time.
+//		Results are rounded with no decimals.
+//		This is needed for 16 bit velocity parameters that has no bits for decimals
+//
+//	RETURNS:
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL convertVelRound(				// ticks/sample-time <=> ticks/sec
+	nodebool valIsBits, 				// TRUE=>ticks/sample-time, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData)
+{
+	double ReturnDouble;
+
+	// Call the original convertVel function
+	ReturnDouble = convertVel(valIsBits,
+		theMultiAddr,
+		parameter,
+		convVal,
+		nodeData);
+	
+	// Round the value
+	if(ReturnDouble-floor(ReturnDouble)>=0.5)
+		ReturnDouble = ceil(ReturnDouble);
+	else
+		ReturnDouble=floor(ReturnDouble);
+
+	return ReturnDouble;
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convert2To27
+//
+//	DESCRIPTION:
+//		Convert Ke to properly scaled value when using a linear motor.
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL limit2To27(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=> app bits
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// To/From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	if (valIsBits) {
+		return(convVal);
+	}
+	else {
+		//  Limit to 2^26 range
+		if (convVal > ((1<<26)-1))
+			return ((1<<26)-1);
+		else if (convVal < (-1<<26))
+			return (-1<<26);
+	}
+	return(convVal);
+}
+/****************************************************************************/
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cleanForXML
+//
+//	DESCRIPTION:
+/**
+	This function will replace any troublesome XML characters with "_"
+	characters.
+
+	\param[in,out] Pointer to original string.
+**/
+void cleanForXML(char *pInputStr) {
+	char *pch;
+	pch = pInputStr;
+	// Kill control characters
+	while (*pch) {
+		if (*pch < ' ')	{
+			*pch = ' ';
+		}
+		else if(*pch >= 0x7f) {
+			*pch = '_';
+		}
+		else {
+			switch (*pch) {
+			case '<':
+			case '>':
+			case '&':
+			case '\'':
+			case '\"':
+				*pch = '_';
+				break;
+			default:
+				// Is OK as-is
+				break;
+			}
+		}
+		pch++;
+	}
+}
+//																			  *
+//*****************************************************************************
+
+/// \endcond INTERNAL_DOC
+
+//============================================================================= 
+//	END OF FILE converterLib.cpp
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/cpmAPI.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/cpmAPI.cpp
new file mode 100644
index 000000000..5df5df555
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/cpmAPI.cpp
@@ -0,0 +1,4333 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/cpmAPI.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: cpmAPI.cpp $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief ClearPath-SC Programming Interface Implementation.
+
+	\defgroup ClearPathgrp ClearPath Programming Interface
+	\brief Functions related to ClearPath functionality.
+
+	Provides:
+		- checking on the operation state of the node
+		- initiating and canceling motion
+		- accessing and changing I/O
+		- accessing and modifying the parameter table
+
+	\remark C and C++ Applications should include the master header file
+	\c meridianHdrs.h in the source code to insure the various function
+	prototypes and data types are available for your application.
+
+	@{
+**/		
+//
+// CREATION DATE:
+//		8/2/2011 DS refactored from Meridian iscAPI.cpp
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																          *
+// 	 cpscAPI.cpp headers
+//
+	//#include "meridianHdrs.h"
+	#include "mnDiags.h"
+	#include "pubNetAPI.h"
+	#include "netCmdAPI.h"
+	#include "pubCpmRegs.h"
+	#include "pubCpmAPI.h"
+	#include "pubIscAPI.h"
+	#include "sFoundResource.h"
+	#include "netCmdPrivate.h"
+	#include "converterLib.h"
+	#include "iscRegs.h"
+	#include "cpmRegs.h"
+	#include "pubCpmAdvAPI.h"
+/// \cond	INTERNAL_DOC
+	#include <math.h>
+ 	#include <stdlib.h>
+ 	#include <malloc.h>
+	#include "lnkAccessCommon.h"
+
+#if defined(_MSC_VER)
+	#pragma warning(disable:4996)
+	#if _MSC_VER<=1800
+	#define snprintf sprintf_s
+	#endif
+#endif
+#if (defined(_WIN32)||defined(_WIN64))
+	#include <crtdbg.h>
+#else
+	#include <string.h>
+#endif
+/// \endcond																  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	 cpscAPI.cpp function prototypes
+//
+/// \cond INTERNAL_DOC
+#define Sgn(x) (((x)>0) ? 1 : (((x)==0) ? 0 : -1))
+#define Q15_MAX (32767./32768.)
+#define Q11_MAX 2048
+// Module private functions
+// Add back enum that we hide
+#define CPM_P_FACT_DRV_ENC_EFF_DENS (cpmParams)322
+
+// Buffer management items
+// "Class" constructor
+cnErrCode cpmClassSetup(multiaddr theMultiAddr);
+// "Class" destructors
+void cpmClassDelete(multiaddr theMultiAddr);
+/// \endcond																  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	cpscAPI.cpp imports
+//
+/// \cond INTERNAL_DOC
+extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+/// \endcond																  *
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	cpscAPI.cpp constants
+//
+/// \cond INTERNAL_DOC
+const double CP_MON_SCALE = 1<<16; 			// Format of scale/ampl control
+const double CP_MON_MAX_VEL = 8192;   		// Vel. full-scale (quads/sample-time)
+const double CP_MON_MIN_VEL = 4;      		// Minimum velocity to display
+const double CP_MON_MAX_POS_LEGACY = 8192;	// Position error full-scale
+const double CP_MON_MAX_POS = 32768;		// Position error full-scale
+const double CP_MON_MAX_POS_MEAS = (1<<20);
+const double CP_MON_MAX_JRK = 0.000001;
+const double CP_MON_MAX_INTG = 1UL<<31;
+#define CP_ADC_SCALE (0.8*(double)(1<<13))	// ADC measure to torque values
+
+// RAS selector table						
+typedef struct _rasTarg {
+	double target;						// Optimal value
+	unsigned code;						// RAS code for this
+} rasTarg;
+
+#define ISC_MV_NEG_LIMIT  0x800000	// Largest negative move
+#define ISC_MV_POS_LIMIT  0x7FFFFF	// Largest positive move
+
+const double ISC_MON_SCALE = 1<<16; 	// Format of scale/ampl control
+const double ISC_MON_MAX_VEL = 8192;   	// Vel. full-scale (quads/sample-time)
+const double ISC_MON_MIN_VEL = 4;      	// Minimum velocity to display
+const double ISC_MON_MAX_POS_LEGACY = 8192;	// Position error full-scale
+const double ISC_MON_MAX_POS = 32768;		// Position error full-scale
+const double ISC_MON_MAX_POS_MEAS = (1<<20);
+const double ISC_MON_MAX_JRK = 0.000001;
+const double ISC_MON_MAX_INTG = 1UL<<31;
+
+// Firmware milestones
+#define FW_MILESTONE_ALL_VERS 0
+#define FW_MILESTONE_AC_GREEN 0x1600
+#define FW_MILESTONE_DUAL_RMS 0x1601
+#define FW_MILESTONE_VBUS_ADJ 0x1606
+#define FW_MILESTONE_MIN_VOLT 0x1607
+#define FW_MILESTONE_USER_TEMP 0x1608
+#define FW_MILESTONE_INDEX_IB 0x1701
+
+
+// Parameter locations that we don't want exposed publicly
+const int CPM_P_DRV_ENC_DENS = 310;
+const int CPM_P_DRV_MTR_POLES = 311;
+
+// Status register bit/field names
+const char *CPSCStatusBitStrs[] = {
+	"Warning", "UserAlert", "NotReady", "MoveBufAvail",
+	"Ready", "PowerEvent", "Alert Present", "#7",
+	"InPosLimit", "InNegLimit", "MotionBlocked", "WasHomed",
+	"Homing", "GoingDisabled", "StatusEvent", "Enabled",
+	"MoveCanceled", "MoveDone", "OutOfRange", "BFromEnd",
+	"AbovePosn", "AtTargetVel", "InA", "InB",
+	"InvInA", "InvInB", "#26", "#27",
+	"AFromStart", "MoveCmdNeg", "Disabled", "TimerExpired",
+	"InMotionPos", "InMotionNeg", "InDisableStop", "InCtrlStop",
+	"FanOn", "VectorSearch", "MoveCmdComplete", "InHardStop",
+	"ShutdownState", "ShutdownState1", "HwFailure", "TriggerArmed",
+	"StepsActive", "IndexMtr", "SoftwareInputs" };
+// Shutdown states (note integer offset for enum)
+const char *CPSCshutdowns[] = {
+	 "OK", "Shutdown Imminent", "Shutdown Ramping", "Shutdown"
+};
+// In motion states (note integer offset for enum)
+const char *CPSCinMotions[] = {
+	 "Stopped", "+", "-", "+/-"
+};
+
+// Alert/Warning Register field names
+const char *CPSCalertsBitStrs[] = {
+	"FwSelfTest", "FwNetBufferOverrun", "FwError0", "FwError1", 
+	"FwStackOverrun", "FwWatchdogRestarted", "FwInvalidConfiguration", 
+	"#7", "#8", "#9", "#10", 
+	"HwPowerProblem", "HwClockProblem", "HwEEPROMdead", "HwFlashCorrupt",
+	"HwFlashChanged", "HwRAM", "HwADC", "HwADCsat",
+	"#19", "#20", "#21", "#22", "#23", 
+	"NetVoltageLow", "NetWatchdog", 
+	"#26", "#27",
+	"EStopped", "ConfigOutOfDate", "RunTimeErr",
+	"#31", "#32", "#33", "#34",
+	"MoveGenRange", "JrkLimRequestBad", "MoveBufUnderrun", 
+	"JrkLimVelRequestBad", "MoveSpecAltered", "PhaseSensorFailed", 
+	"LimSwitchActivated", "SoftLimitExceeded", 
+	"#43", "#44", "#45", "#46", "#47", "#48", "#49", "#50", "#51", 
+	"AClost", 
+	"ACphaseLost", "#54", "LowTemp", "#56", "#57", 
+	"MtrVectorBad",
+	"#59", 
+	"MtrEncGlitch", "MtrEncOverspeed", 
+	"#62", "#63",
+	"MtrPhaseOverload",
+	"#65", "MtrBadSetupParams", "HardStopBrokeFree", "#68", 
+	"TrackingShutdown", "RMSOverload", "RMSOverloadShutdown",
+	"#72", "#73", 
+	"BusVoltSat", "TrqSat", "NoCommSweepFailed", "NoCommSweepReversed", 
+	"NoCommFailed", "IndexCountZeroWarn", "TempAmbientHigh", 
+	"StatorHot", 
+	"BusOverCurrent", "BusOverVoltage", "BusVoltageLow", "BusRMSOverload", 
+	"#86", 
+	"MtrEncIndexMissing", 
+	"BusVoltageUnderOperatingV",
+	"#89", "#90", "#91", "#92",
+	"MtrEncIndexMisplaced", "StepsDuringPosnRecovery", "#95"
+};
+
+/// \endcond																  *
+//*****************************************************************************
+
+//*****************************************************************************
+//*****************************************************************************
+//					 Value Converters for ClearPath-EC Motors
+//
+//			Group these together for Doxygen with INTERNAL_DOC tag
+//*****************************************************************************
+//*****************************************************************************
+
+/// \cond INTERNAL_DOC
+
+//*****************************************************************************
+//	NAME																	  *
+//		convertADCmax
+//
+//	DESCRIPTION:
+/**	
+	Conversion to and from ADC max parameter
+
+ 	\param xxx description
+	\return description
+ 
+ 	Detailed description.
+**/
+//	SYNOPSIS:
+static double MN_DECL convertADCmax(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=> app bits
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// To/From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	double iMax;
+	cnErrCode theErr;
+	theErr = cpmGetParameter(theMultiAddr, CPM_P_DRV_I_MAX, &iMax);
+	if (theErr==MN_OK) {
+		if (valIsBits) {
+			return(iMax/convVal);
+		}
+		else {
+			return(iMax/convVal);
+		}
+	}
+	return(0);
+}
+//																			  *
+//*****************************************************************************
+
+/******************************************************************************
+ *	!NAME!
+ *		convertAmperes
+ *
+ *	DESCRIPTION: */
+/**
+ *		Convert a 1.15 type number into a fraction of I_MAX.
+ *
+ *		\return double
+ **/
+//	SYNOPSIS:
+static double MN_DECL convertAmperes(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue iMax;					// Full scale
+	double newInt;						// Temp variables
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_I_MAX, NULL, &iMax);
+	// The basis value is OK?
+	if (theErr != MN_OK || iMax.value <= 0)
+		return(0);
+
+	if (valIsBits)   {
+		// Convert to Amperes from the fraction of full scale
+		return(convVal * iMax.value);
+	}
+	else {
+		newInt = (convVal / iMax.value);
+		if (newInt > Q15_MAX) newInt = Q15_MAX;
+		return(newInt);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertAmpsRMS
+ *
+ *	DESCRIPTION:
+ *		Convert RMS level from base units. This RMS level is returned
+ *		referenced to ADC max.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertAmpsRMS(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue adcMax;			// Basis information
+	double finalVal;
+	cnErrCode theErr;
+//                             %     Trq->A                 Q Factor
+//	const double CONST_FACT = 100 / (2^28) ^ 0.5
+	
+	// Maximum current
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK)
+		return(0);
+
+	if (valIsBits) {
+		// Prevent errors
+		if (convVal < 0) convVal = 0;
+		finalVal = (sqrt(convVal) * adcMax.value);
+	}
+	else {
+		finalVal = convVal / adcMax.value;
+		finalVal *= finalVal;
+	}
+	return(finalVal);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertMeasAmperes
+ *
+ *	DESCRIPTION:
+ *		Convert a 1.15 type number into a fraction of ADC_MAX.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertMeasAmperes(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,					// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue adcMax;					// Full scale
+	double newInt;						// Temp variables
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	// The basis value is OK?
+	if (theErr != MN_OK || adcMax.value <= 0)
+		return(0);
+
+	if (valIsBits)   {
+		// Convert to Amperes from the fraction of full scale
+		return(convVal * adcMax.value);
+	}
+	else {
+		newInt = (convVal / adcMax.value);
+		if (newInt > Q15_MAX) newInt = Q15_MAX;
+		return(newInt);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+///*****************************************************************************
+// *	!NAME!
+// *		convertTemp
+// *
+// *	DESCRIPTION:
+// *		Convert a Celsius temperature on the user side to an ADC-scaled
+// *		representation of that temperature on the drive side
+// *
+// *	\return
+// *		double
+// *
+// *	SYNOPSIS: 															    */
+//static double MN_DECL convertTemp(
+//	nodebool valIsBits, 				// TRUE=>ADC Temp, FALSE=>C Temp
+//	multiaddr theMultiAddr,				// Node address
+//	appNodeParam parameter,				// Target parameter
+//	double convVal,						// From value
+//	byNodeDB *pNodeDB)					// Parameter information
+//{
+//
+//#define DEG_C_PER_LSB		(0.18/8)
+//#define ADC_ZERO_C			(1750<<3)
+//	//Constans and calculations copied from hardware.h in ClearPath FW
+//
+//	if (valIsBits)   {
+//		return (convVal - ADC_ZERO_C) * DEG_C_PER_LSB;
+//	}
+//	else {
+//		//Conversion copied from hardware.h in ClearPath FW
+//		return convVal/DEG_C_PER_LSB + ADC_ZERO_C;
+//	}
+//}
+///*																 !end!		*/
+///****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertMeasVolts
+ *
+ *	DESCRIPTION:
+ *		Convert a 1.15 type number into a fraction of full scale range.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertMeasVolts(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,					// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue fsBusV;					// Full scale
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_FACT_FS_BUSV, NULL, &fsBusV);
+	// The basis value is OK?
+	if (theErr != MN_OK || fsBusV.value <= 0)
+		return(0);
+
+	if (valIsBits) {
+		// Convert to Volts from the fraction of full scale
+		return(convVal * fsBusV.value);
+	}
+	else {
+		return(convVal / fsBusV.value);
+	}
+
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertMonGain
+//
+//	DESCRIPTION:
+//		Convert the monitor port gain setting to/from a full-scale range
+//		value.
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+static double MN_DECL convertMonGain(
+	nodebool valIsBits, 				// TRUE=>scaled, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	iscMonVars theVar,					// The variable to adjust
+	double convVal)
+{
+	paramValue sampleTime, iMax, adcMax;
+	cnErrCode theErr;
+	double baseVal, fsVal;
+	paramValue cmdRes, encRes;
+	double resScale=1;
+	#define FG_RATE_MAX 100000
+
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr addr = NODE_ADDR(theMultiAddr);
+	iscState *pState;
+	if (!(pState = (iscState *)SysInventory[cNum].NodeInfo[addr].pNodeSpecific))
+		return(0);
+	monState &monNow = pState->MonState; 
+	monNow.TestPoint = theVar;
+	// Assume failure until we get to the end
+	monNow.Set = false;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_I_MAX, NULL, &iMax);
+	if (theErr != MN_OK)
+		return(0);
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK)
+		return(0);
+	if (iMax.value <=0 || adcMax.value <= 0)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_CMD_CNTS_PER_REV,
+							      NULL, &cmdRes);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ENC_DENS,
+								  NULL, &encRes);
+	if (theErr != MN_OK)
+		return(0);
+	// Scale the display by the encoder to cmd ratio
+	if (cmdRes.value > 0 && encRes.value > 0)
+		resScale = encRes.value / cmdRes.value;
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTime);
+	if (fabs(sampleTime.value) < 0.001) 
+		// Protect from divide-by-zero
+		return(0);
+
+	if (valIsBits)  {
+		// Convert from fixed point
+		convVal /= ISC_MON_SCALE;
+	}
+	// Protect from \ 0
+	if (fabs(convVal) < 0.0001)  {
+		// Show as "off"
+		return(0);
+	}
+//#if defined(__GNUC__)
+//#pragma GCC diagnostic push
+//#pragma GCC diagnostic ignored "-Wswitch"
+//#endif
+	// return the full scale value
+	switch (theVar) {
+		case MON_VEL_MEAS:
+		case MON_VEL_CMD:
+		case MON_VEL_TRK:
+		case MON_VEL_TRK_SERVO:
+		case 59:
+			// Return the monitor value in Hertz
+			baseVal = ((1e3*ISC_MON_MAX_VEL)
+			        / (sampleTime.value*convVal*resScale));
+			break;
+
+		case MON_VEL_STEP:
+			baseVal = (4e3*ISC_MON_MAX_VEL)
+			        / (sampleTime.value*convVal*resScale);
+			break;
+
+		case MON_JRK_CMD:
+			baseVal = (1e12*ISC_MON_MAX_VEL)
+					/ (pow(sampleTime.value,3) * convVal*resScale);
+			break;
+
+		case MON_ACC_CMD:
+			baseVal = (1e6*ISC_MON_MAX_VEL)
+					/ (sampleTime.value*sampleTime.value*convVal*resScale);
+			break;
+
+		case MON_POSN_TRK:
+		case MON_POSN_DIR_TRK:
+		case MON_TRK_LD:
+		case MON_POSN_DIR_TRK_MTR:
+		case MON_POSN_TRK_MTR:
+		case MON_COUPLING:
+			baseVal = (ISC_MON_MAX_POS/(convVal*resScale));
+			break;
+
+		case MON_SINE_R:		// (2.14 format)
+		case MON_COS_R:
+			baseVal = (200/convVal);
+			break;
+
+		case MON_TRQ_MEAS:		// (1.15 format) scaled to trq amps
+		case MON_TRQ_MEAS_PEAK:
+		case MON_TRQ_D_MEAS:
+		case MON_TRQ_TRK:
+		case MON_TRQ_TRK_PEAK:
+			baseVal = (100*adcMax.value/iMax.value)/convVal;
+			break;
+
+		case MON_POSN_MEAS:
+		case 76:				// Position Cmd
+			baseVal = (ISC_MON_MAX_POS_MEAS/(convVal*resScale));
+			break;
+
+		case (monTestPoints)77:	// FG rate
+			baseVal = FG_RATE_MAX / convVal;
+			break;
+
+		case MON_INTEGRATOR:
+			baseVal = (ISC_MON_MAX_INTG/convVal);
+			break;
+
+		case MON_SGN_CMD_VEL:
+		case MON_SGN_CMD_STEP:
+			baseVal = (100. / convVal);
+			break;
+
+		case MON_BUS_VOLTS:
+			theErr = netGetParameterDbl(theMultiAddr,
+										mnParams(CPM_P_DRV_FACT_FS_BUSV),
+										&fsVal);
+			if (theErr != MN_OK)
+				return theErr;
+			baseVal = fsVal / convVal;
+			break;
+
+
+		case MON_TRQ_CMD:		// (1.15 format)
+		case MON_CALIBRATE:
+		default:
+			baseVal = (100/convVal);
+			break;
+	}
+//#if defined(__GNUC__)
+//#pragma GCC diagnostic pop
+//#endif
+	if (!valIsBits)  {
+		baseVal *= 0x10000;				// Scale to (16.16)
+		// Put at maximum number
+		if (baseVal > 0x7fffffff) baseVal = 0x7fffffff;
+		if (baseVal < 1) baseVal = 1;
+		// Get rescaled value
+		monNow.FullScale = convertMonGain(true, theMultiAddr, theVar, baseVal); 
+		monNow.Set = true;
+	}
+	else {
+		monNow.FullScale = baseVal;
+		monNow.Set = true;
+	}
+	return(baseVal);
+}
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlevel
+ *
+ *	DESCRIPTION:
+ *		Convert RMS level from base units. This RMS level is a 
+ *		0 TO 100 value where 100 corresponds to the RMS shutdown point.	 This
+ *		converter does not need to convert to base units as it is a display
+ *		value only.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlevel(   
+	nodebool scaled, 					// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue rmsLimit, adcMax;			// Basis information
+	double finalVal;
+	cnErrCode theErr;
+//                             %     Trq->A                 Q Factor
+//	const double CONST_FACT = 100 / (2^28) ^ 0.5
+//	const double CONST_FACT = 0.006103515625;
+	
+	// Maximum current
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK || adcMax.value == 0)
+		return(0);
+
+	// RMS maximum amperes
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_RMS_LIM, NULL, &rmsLimit);
+	if (theErr != MN_OK || rmsLimit.value == 0)
+		return(0);
+
+	if (convVal < 0 || convVal > 0x7FFFFFFF) 
+		return(0);
+		
+	// Convert to integer with rounding
+	//										      ADCmax
+	finalVal = (nodelong)(((100 * sqrt(convVal/(1<<28)) * adcMax.value) 
+				/ rmsLimit.value) + 0.5);
+
+	// Insure the numbers don't exceed the range
+	if (finalVal > 100) finalVal = 100;
+	if (finalVal < 0) finalVal = 0;
+	
+	//_RPT2(_CRT_WARN, "%.3f  %08x\n", finalVal, lVal);
+
+	return(finalVal);
+}
+//																      		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlevelSlow
+ *
+ *	DESCRIPTION:
+ *		Convert RMS level from base units. This RMS level is a 
+ *		0 TO 100 value where 100 corresponds to the RMS shutdown point.	 This
+ *		converter does not need to convert to base units as it is a display
+ *		value only.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlevelSlow(   
+	nodebool scaled, 					// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue rmsLimit, adcMax;			// Basis information
+	double finalVal;
+	cnErrCode theErr;
+//                             %     Trq->A                 Q Factor
+//	const double CONST_FACT = 100 / (2^28) ^ 0.5
+//	const double CONST_FACT = 0.006103515625;
+	
+	// Maximum current
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK || adcMax.value == 0)
+		return(0);
+
+	// RMS maximum amperes
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_RMS_SLOW_LIM, NULL, &rmsLimit);
+	if (theErr != MN_OK || rmsLimit.value == 0)
+		return(0);
+
+	if (convVal < 0 || convVal > 0x7FFFFFFF) 
+		return(0);
+		
+	// Convert to integer with rounding
+	//										      ADCmax
+	finalVal = (nodelong)(((100 * sqrt(convVal/(1<<28)) * adcMax.value) 
+				/ rmsLimit.value) + 0.5);
+
+	// Insure the numbers don't exceed the range
+	if (finalVal > 100) finalVal = 100;
+	if (finalVal < 0) finalVal = 0;
+	
+	//_RPT2(_CRT_WARN, "%.3f  %08x\n", finalVal, lVal);
+
+	return(finalVal);
+}
+//																      		*/
+/****************************************************************************/
+
+/*****************************************************************************
+*	!NAME!
+*		checkPosnLimit
+*
+*	DESCRIPTION:
+*		This converter is used to limit tracking and in-position limits
+*		for new and older firmwares.
+*
+*	\return
+*		double
+*
+*	SYNOPSIS: 															    */
+static double MN_DECL checkPosnLimit(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	double fwVers;
+	cnErrCode theErr;
+
+	theErr = netGetParameterDbl(theMultiAddr, mnParams(CPM_P_FW_VERS), &fwVers);
+	if (theErr == MN_OK) {
+		// Get the maximum current 
+		if (!valIsBits) {
+			if (FW_MILESTONE_DUAL_RMS > fwVers && convVal > INT16_MAX) {
+				convVal = INT16_MAX;
+			}
+		}
+	}
+	return (convVal);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlimit
+ *
+ *	DESCRIPTION:
+ *		Unit conversion to convert the RMS limit settings to and from the 
+ *		unscaled values.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlimit(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue adcMax;
+	cnErrCode theErr;
+	int rVal;
+
+	const double CONST_FACT = 1<<12; //(4.12 basis value)
+	const double TRQ_MAX_PCT = 0.9999;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr == MN_OK) {
+		// Make sure the adcMax is reasonable
+		if (adcMax.value <= 0)
+			return(0);
+		// Make sure the value in is reasonable
+		if (convVal <= 0)		   
+			return(0);
+
+		// Get the maximum current 
+		if (valIsBits)
+			// Convert to RMS from unscaled
+			return(sqrt(convVal * adcMax.value * adcMax.value / CONST_FACT));
+		else {
+			// Convert RMS to unscaled value
+			if (convVal > adcMax.value)	
+				rVal = ((int)(CONST_FACT * 
+					  ((TRQ_MAX_PCT) * (TRQ_MAX_PCT))));
+			else
+				rVal = ((int)(CONST_FACT * 
+				           ((convVal / adcMax.value) * (convVal / adcMax.value))+0.5));
+			//_RPT2(_CRT_WARN, "ISC(%d) RMS LIM = 0x%x\n", theMultiAddr, rVal);
+			return(rVal);
+		}
+	}
+	return (0);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlimit32
+ *
+ *	DESCRIPTION:
+ *		Unit conversion to convert the RMS limit settings to and from the 
+ *		unscaled values.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlimit32(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue adcMax;
+	cnErrCode theErr;
+	int rVal;
+
+	const double CONST_FACT = 1<<28; //(4.28 basis value)
+	const double TRQ_MAX_PCT = 0.9999;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr == MN_OK) {
+		// Make sure the adcMax is reasonable
+		if (adcMax.value <= 0)
+			return(0);
+		// Make sure the value in is reasonable
+		if (convVal <= 0)		   
+			return(0);
+
+		// Get the maximum current 
+		if (valIsBits)
+			// Convert to RMS from unscaled
+			return(sqrt(convVal * adcMax.value * adcMax.value / CONST_FACT));
+		else {
+			// Convert RMS to unscaled value
+			if (convVal > adcMax.value)	
+				rVal = ((int)(CONST_FACT * 
+					  ((TRQ_MAX_PCT) * (TRQ_MAX_PCT))));
+			else
+				rVal = ((int)(CONST_FACT * 
+				           ((convVal / adcMax.value) * (convVal / adcMax.value))+0.5));
+			//_RPT2(_CRT_WARN, "ISC(%d) RMS LIM = 0x%x\n", theMultiAddr, rVal);
+			return(rVal);
+		}
+	}
+	return (0);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSFactor
+ *
+ *	DESCRIPTION:
+ *		Amount to scale RMS values by if the motor velocity is below the RMS
+ *	stopped speed
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSFactor(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+
+	// Make sure the value in is reasonable
+	if (convVal <= 0)		   
+		return(0);
+
+	// Get the maximum current 
+	if (valIsBits)
+		// Convert to scale factor from drive value
+		return(sqrt(convVal));
+	else {
+		// Convert scale factor to drive value value
+		return(convVal * convVal);
+	}
+	return (0);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMStc
+ *
+ *	DESCRIPTION:
+ *		Convert RMS time constants to and from seconds and base units.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMStc(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue sampleTimeV;
+	cnErrCode theErr;
+	double b;
+	double retVal;
+
+	// Winding Amperes to torque Amperes factor
+	const int SCALE_FACT_Q = 23;              // Parameter window scale 
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	NULL, &sampleTimeV);
+	if (theErr != MN_OK)
+		return(0);
+	sampleTimeV.value *=  1e-6;		// Convert to seconds
+
+	// Make sure the sampleTime is reasonable
+	if (sampleTimeV.value == 0)
+		return(0);
+
+	// Insure problems return zero
+	retVal = 0;
+
+	// Convert TC to and from base units 
+	if (valIsBits)	 {
+		// Convert base to seconds
+		b = (1. - (convVal/(1<<SCALE_FACT_Q)));
+		if (b>0 && b<1)  {
+			b = log(b)/sampleTimeV.value;
+			if (b != 0)
+				retVal = log(8./9.)/b;	
+		}
+		//_RPT2(_CRT_WARN, "ISC(%d) RMS TC = %.3f\n", theMultiAddr, retVal);
+	}
+	else {
+		// Convert seconds to base units
+
+		// Enforce minimal values
+		if (convVal < 0.01) convVal = 0.01;
+		b = 1 - pow(8./9., (sampleTimeV.value/convVal));
+		// Convert to integer / rounding
+		retVal = (nodelong)((b*(1<<SCALE_FACT_Q))+0.5);
+		// Prevent the value from turning "negative"
+		if (retVal > 32767) retVal = 32767;
+		// Prevent the value from going to zero
+		if (retVal < 1) retVal = 1;
+		//_RPT2(_CRT_WARN, "ISC(%d) RMS TC = 0x%x\n", theMultiAddr, retVal);
+	}
+	return (retVal);
+}
+//																      		*/
+/****************************************************************************/
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSSlowtc
+ *
+ *	DESCRIPTION:
+ *		Convert RMS time constants to and from minutes and base units.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSSlowtc(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue sampleTimeV;
+	cnErrCode theErr;
+	double b;
+	double retVal;
+
+	// Winding Amperes to torque Amperes factor
+	const int SCALE_FACT_Q = 23;              // Parameter window scale 
+	const int SLOW_RMS_Q = 8;              // Parameter window scale 
+	const int SECS_PER_MINUTE = 60;        // Scale to minutes 
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	NULL, &sampleTimeV);
+	if (theErr != MN_OK)
+		return(0);
+	sampleTimeV.value *=  1e-6;		// Convert to seconds
+
+	// Make sure the sampleTime is reasonable
+	if (sampleTimeV.value == 0)
+		return(0);
+
+	// Insure problems return zero
+	retVal = 0;
+
+	// Convert TC to and from base units 
+	if (valIsBits)	 {
+		// Convert base to minutes
+		b = (1. - (convVal/(1<<SCALE_FACT_Q)));
+		if (b>0 && b<1)  {
+			b = log(b)/sampleTimeV.value;
+			if (b != 0)
+				retVal = log(8./9.)/b;	
+		}
+		retVal = retVal * (1 << SLOW_RMS_Q) / SECS_PER_MINUTE;
+		//_RPT2(_CRT_WARN, "ISC(%d) RMS TC = %.3f\n", theMultiAddr, retVal);
+	}
+	else {
+		// Convert seconds to base units
+
+		// Enforce minimal values
+		convVal = convVal * SECS_PER_MINUTE / (1 << SLOW_RMS_Q);
+		if (convVal < 0.01) convVal = 0.01;
+		b = 1 - pow(8./9., (sampleTimeV.value/convVal));
+		// Convert to integer / rounding
+		retVal = (nodelong)((b*(1<<SCALE_FACT_Q))+0.5);
+		// Prevent the value from turning "negative"
+		if (retVal > 32767) retVal = 32767;
+		// Prevent the value from going to zero
+		if (retVal < 1) retVal = 1;
+		//_RPT2(_CRT_WARN, "ISC(%d) RMS TC = 0x%x\n", theMultiAddr, retVal);
+	}
+	return (retVal);
+}
+//																      		*/
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertAngle
+//
+//	DESCRIPTION:
+//		Convert to and from the commutation angle in encoder ticks to an
+//		angle in electrical degrees.
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+static double MN_DECL convertAngle(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=>mech degrees
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)
+{
+	paramValue poles, encDens;
+	cpmHwConfigReg hwConfig;
+	optionReg opts;
+
+	double ticksPerDegree, degreesPerTurn, rVal;
+	cnErrCode theErr;
+	
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_MTR_POLES, NULL, &poles);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ENC_DENS, NULL, &encDens);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = cpmGetHwConfigReg(theMultiAddr, &hwConfig);
+	if (theErr != MN_OK)
+		return(0);
+
+	double pVal;
+	theErr = cpmGetParameter(theMultiAddr, CPM_P_OPTION_REG, &pVal);
+	if (theErr != MN_OK)
+		return(0);
+	opts.bits = Uint32(pVal);
+
+	degreesPerTurn = poles.value * 180.;
+	if (poles.value != 0) {
+		ticksPerDegree = encDens.value / degreesPerTurn;
+	}
+	else {
+		return(0);
+	}
+
+	if (valIsBits)  {
+		// Convert convVal to electrical degrees
+		rVal = convVal/ticksPerDegree;
+		if (opts.cpm.VectorLock) {
+			rVal += 90;
+		}
+		// Keep result between 0 and degreesPerTurn
+		if (rVal >= degreesPerTurn)
+			rVal -= degreesPerTurn;
+		if (rVal < 0)
+			 rVal += degreesPerTurn;
+		// Return the value 
+		return(rVal);
+	}
+	else {
+		// Convert convVal to drive bits
+		rVal = convVal;
+		if (opts.cpm.VectorLock)
+			rVal -= 90;
+		// Scale back to ticks
+		rVal *= ticksPerDegree;
+		// Bounds test the results between 0 and ticksPerTurn-1
+		if (rVal < 0)
+			rVal += ticksPerDegree*degreesPerTurn;
+		if (rVal >= ticksPerDegree*degreesPerTurn)
+			rVal -= ticksPerDegree*degreesPerTurn;
+		// Return the final value
+		return(((nodelong)(rVal+0.5)));
+	}	
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertSpdLim
+//
+//	DESCRIPTION:
+//		This function converts to and from ticks/second and ticks/sample-time.
+//
+//	RETURNS:
+//		double
+//
+//	SYNOPSIS:
+double MN_DECL convertSpdLim(			// encoder ticks/sample-time <=> user ticks/sec
+	nodebool valIsBits, 				// TRUE=>ticks/sample-time, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *nodeData)
+{
+	paramValue sampleTime;				
+	cnErrCode theErr;
+	paramValue userDens, encDens;
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,
+							      NULL, &sampleTime);
+	// Avoid divide-by-0 problems and other errors
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_DRV_ENC_DENS, NULL, &encDens);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_CMD_CNTS_PER_REV, NULL, &userDens);
+	if (theErr != MN_OK)
+		return(0);
+
+	if (valIsBits)  {
+		return(1e6 * convVal * userDens.value / ( encDens.value * sampleTime.value));
+	}
+	else {
+		// convVal in ms => us / # us/sample-time
+		return(1e-6 * convVal * sampleTime.value * encDens.value / userDens.value);
+	}
+}
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertFilt99pctMilliseconds
+ *
+ *	DESCRIPTION:
+ *		Convert IIR time constants from milliseconds to and from the 99% 
+ *		trip points.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertFilt99pctMilliseconds(
+	nodebool scaled, 					// TRUE=>milliseconds, FALSE=>unscaled
+	multiaddr theMultiAddr,					// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue sampleTime;
+	cnErrCode theErr;
+	nodelong intVal; double x;
+
+	const double TripPoint = 1-0.99;	// Trip point
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTime);
+	// Was it OK?
+	if (theErr != MN_OK && sampleTime.value <=0)
+		return(0);
+
+	if (scaled)  {
+		// Convert to milliseconds from base units
+		if (convVal > 32767 || convVal <=0)	
+			return(0);
+		return(.001*sampleTime.value * log(TripPoint)/log(convVal/32768.));
+	}
+	else {
+		// Convert to base units from milliseconds	
+		if (convVal <= 0) return(0);
+		x = pow(TripPoint, .001*sampleTime.value/convVal);
+		intVal = (nodelong)((32768.*x)+0.5);
+		if (intVal > 32767) intVal = 32767;
+		return(intVal);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertFilt1TCMilliseconds
+ *
+ *	DESCRIPTION:
+ *		Convert IIR time constants from milliseconds to and from the 99% 
+ *		trip points.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertFilt1TCMilliseconds(
+	nodebool scaled, 					// TRUE=>milliseconds, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue sampleTime;
+	cnErrCode theErr;
+	nodelong intVal; double x;
+
+	const double TripPoint = 0.367879;	// Trip point 1/e
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTime);
+	// Was it OK?
+	if (theErr != MN_OK && sampleTime.value <=0)
+		return(0);
+
+	if (scaled)  {
+		// Convert to milliseconds from base units
+		if (convVal > 32767 || convVal <=0)	
+			return(0);
+		return(.001*sampleTime.value * log(TripPoint)/log(convVal/32768.));
+	}
+	else {
+		// Convert to base units from milliseconds	
+		if (convVal <= 0) return(0);
+		x = pow(TripPoint, .001*sampleTime.value/convVal);
+		intVal = (nodelong)((32768.*x)+0.5);
+		if (intVal > 32767) intVal = 32767;
+		return(intVal);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertIBRMStc
+ *
+ *	DESCRIPTION:
+ *		Convert IB RMS time constants to and from seconds and base units.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertIBRMStc(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue sampleTimeV;
+	cnErrCode theErr;
+	double b;
+	double retVal;
+
+	// Winding Amperes to torque Amperes factor
+	const int SCALE_FACT_Q = 23;              // Parameter window scale 
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	NULL, &sampleTimeV);
+	if (theErr != MN_OK)
+		return(0);
+	sampleTimeV.value *=  1e-6/4;		// Convert to seconds
+
+	// Make sure the sampleTime is reasonable
+	if (sampleTimeV.value == 0)
+		return(0);
+
+	// Insure problems return zero
+	retVal = 0;
+
+	// Convert TC to and from base units 
+	if (valIsBits)	 {
+		// Convert base to seconds
+		b = (1. - (convVal/(1<<SCALE_FACT_Q)));
+		if (b>0 && b<1)  {
+			b = log(b)/sampleTimeV.value;
+			if (b != 0)
+				retVal = log(8./9.)/b;	
+		}
+		if (retVal < 0.01) retVal = 0.01;
+		//_RPT2(_CRT_WARN, "CP(%d) IB RMS TC = %.3f\n", theMultiAddr, retVal);
+	}
+	else {
+		// Convert seconds to base units
+
+		// Enforce minimal values
+		if (convVal < 0.01) convVal = 0.01;
+		b = 1 - pow(8./9., (sampleTimeV.value/convVal));
+		retVal = (nodelong)(b*(1<<SCALE_FACT_Q));
+		// Prevent the value from turning "negative"
+		if (retVal > 32767) retVal = 32767;
+		//_RPT2(_CRT_WARN, "CP(%d) IB RMS TC = 0x%x\n", theMultiAddr, retVal);
+	}
+	return (retVal);
+}
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertIBRMSSlowtc
+ *
+ *	DESCRIPTION:
+ *		Convert IB RMS time constants to and from seconds and base units.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertIBRMSSlowtc(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue sampleTimeV;
+	cnErrCode theErr;
+	double b;
+	double retVal;
+
+	// Winding Amperes to torque Amperes factor
+	const int SCALE_FACT_Q = 23;              // Parameter window scale 
+	const int SLOW_RMS_Q = 7;	              // Parameter window scale 
+
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	NULL, &sampleTimeV);
+	if (theErr != MN_OK)
+		return(0);
+	sampleTimeV.value *=  1e-6/4;		// Convert to seconds
+
+	// Make sure the sampleTime is reasonable
+	if (sampleTimeV.value == 0)
+		return(0);
+
+	// Insure problems return zero
+	retVal = 0;
+
+	// Convert TC to and from base units 
+	if (valIsBits)	 {
+		// Convert base to seconds
+		b = (1. - (convVal/(1<<SCALE_FACT_Q)));
+		if (b>0 && b<1)  {
+			b = log(b)/sampleTimeV.value;
+			if (b != 0)
+				retVal = log(8./9.)/b * (1 << SLOW_RMS_Q);	
+		}
+		if (retVal < 0.01) retVal = 0.01;
+		//_RPT2(_CRT_WARN, "CP(%d) IB RMS TC = %.3f\n", theMultiAddr, retVal);
+	}
+	else {
+		// Convert seconds to base units
+
+		// Enforce minimal values
+		convVal = convVal / (1 << SLOW_RMS_Q);
+		if (convVal < 0.01) convVal = 0.01;
+		b = 1 - pow(8./9., (sampleTimeV.value/convVal));
+		retVal = (nodelong)(b*(1<<SCALE_FACT_Q));
+		// Prevent the value from turning "negative"
+		if (retVal > 32767) retVal = 32767;
+		//_RPT2(_CRT_WARN, "CP(%d) IB RMS TC = 0x%x\n", theMultiAddr, retVal);
+	}
+	return (retVal);
+}
+
+
+//****************************************************************************
+//	NAME
+//		convertJerk
+//
+//	DESCRIPTION:
+//		Convert jerk specified in units of milliseconds to the internal
+//		codes.  
+//
+//		TO_KILL: When we stop support of v5.0-v5.1 Meridian Firmare
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+static double MN_DECL convertJerk(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=>msecs
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// To/From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	optionReg optReg;
+	packetbuf resp;
+	cnErrCode theErr;
+	bool isKdrive = false, isEnhanced;
+	double KdrvMaxRas, fwVer, sampleTimeMicroSec;
+//	// Code boundaries
+//	static const int classicStart = 0;
+//	static const int shallowCodeStart = 16;
+//	static const int deepCodeStart = 48;
+//	static const int enhancedRASlen = 30;
+//	static const int rasFracLSD = 100;				// 0.01 is least significant digit
+	
+	#define SHALLOW_CODE 10
+	#define DEEP_CODE	 20
+	
+	// Get base information
+	theErr = cpmGetParameter(theMultiAddr, CPM_P_SAMPLE_PERIOD, &sampleTimeMicroSec);
+	if (theErr != MN_OK)
+		return(ISC_RAS_OFF);
+	theErr = cpmGetParameter(theMultiAddr, CPM_P_FW_VERS, &fwVer);
+	if (theErr != MN_OK)
+		return(ISC_RAS_OFF);
+	isEnhanced = TRUE;
+	
+	if (!isEnhanced){
+		//K-drive check only matters in legacy, pre-IEX FW
+		theErr = netGetParameter(theMultiAddr, CPM_P_OPTION_REG, &resp);
+		if (theErr != MN_OK)
+			return(ISC_RAS_OFF);
+		optReg = *((optionReg*)(&resp.Byte.Buffer[0]));
+		if(optReg.DrvFld.Product == 1){
+			isKdrive = true;
+		}
+	}
+
+	if (valIsBits) {
+		// conVal = drive bits convert to a UI code
+		//rasSelector codeParser;
+		//codeParser.Bits = (unsigned)convVal;
+		if (isEnhanced) {
+			return(convVal);			// Pass bits through
+		}
+		else {
+			KdrvMaxRas = ISC_RAS_9MS;
+			if( isKdrive && convVal > KdrvMaxRas )
+				convVal = KdrvMaxRas;
+			switch((int)convVal)  {
+				case ISC_RAS_OFF: 
+					return(0);
+				case ISC_RAS_3MS:
+					return(3);
+				case ISC_RAS_5MS:
+					return(5);
+				case ISC_RAS_9MS:
+					return(9);
+				case ISC_RAS_15MS:
+					return(15);
+				case ISC_RAS_24MS:
+					return(24);
+				case ISC_RAS_44MS:
+					return(44);
+			}
+		}
+		return(ISC_RAS_OFF);
+	}
+	else {
+		// Enhanced SST sub-system
+		if (isEnhanced) {
+			return(convVal);				// Return untouched
+		}
+		// Classic SST codes
+		else {
+			// conVal = time in milliseconds, create node selection bit pattern.
+			KdrvMaxRas = 9;
+			if( isKdrive && convVal > KdrvMaxRas )
+				convVal = KdrvMaxRas;
+			if (convVal < 1.5)
+				return(ISC_RAS_OFF);
+
+			if (convVal >= 1.5 && convVal < 4)
+				return(ISC_RAS_3MS);
+			else if (convVal >= 4 && convVal < 7)
+				return(ISC_RAS_5MS);
+			else if (convVal >= 7 && convVal < 12)
+				return(ISC_RAS_9MS);
+			else if (convVal >= 12 && convVal < 19.5)
+				return(ISC_RAS_15MS);
+			else if (convVal >= 19.5 && convVal < 34)
+				return(ISC_RAS_24MS);
+			else
+				return(ISC_RAS_44MS);
+		}
+	}
+	return(ISC_RAS_OFF);
+}
+/******************************************************************************/
+// END OF CONVERTERS
+//	cond INTERNAL_DOC
+/// \endcond
+/******************************************************************************/
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	cpscAPI.cpp static variables
+//
+///	\cond INTERNAL_DOC
+// Note: Setting length to negative means valid up to labs(size)
+//
+// The parameter handler table
+static const paramInfoLcl cpmInfoDB[] = {
+// 		 1/x, signed, type,  unit,    size, scale,		config key id,			description, 			[converter]
+//=======Core Node Parameters===============
+/* 0  */ { 0, 0, PT_RO,		DEV_ID,			2, 1<<8,	PARAM_NULL,				STR_PARAM_DEVID}, 	
+/* 1  */ { 0, 0, PT_RO,	 	FW_VERS,		2, 1<<12,	PARAM_NULL,				STR_PARAM_FWVERS}, 	
+/* 2  */ { 0, 0, PT_RO,	 	HW_VERS,		2, 1<<8,	PARAM_NULL,				STR_PARAM_HWVERS}, 	
+/* 3  */ { 0, 0, PT_RO,		NO_UNIT,		2, 1,		PARAM_NULL,				STR_PARAM_RESELLERID},
+/* 4  */ { 0, 0, PT_RO,	 	NO_UNIT, 		4, 1,		PARAM_SERIAL_NUMBER,	STR_PARAM_SERIAL_NUM}, 	
+/* 5  */ { 0, 0, PT_FCFG,	BIT_FIELD,		4, 1,		PARAM_OPTION_REG,		STR_PARAM_OPT_REG}, 	
+/* 6  */ { 0, 0, PT_NV_RW,	NO_UNIT, 		2, 1,		PARAM_ROM_UPD_ACK,		STR_PARAM_ROMSUM_ACK}, 	
+/* 7  */ { 0, 0, PT_RO,	 	NO_UNIT, 		2, 1,		PARAM_ROM_SUM,			STR_PARAM_FWSUM}, 	
+/* 8  */ { 0, 0, PT_RO,	 	TIME_USEC, 		4, 1000,	PARAM_SAMP_RATE,		STR_PARAM_SAMP_PER}, 	
+/* 9  */ { 0, 0, PT_RO_RT,	BIT_FIELD,	   12, 1,		PARAM_ALERT_REG,		STR_PARAM_ALERT_REG}, 	
+/* 10 */ { 0, 0, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_STOP_TYPE,		STR_PARAM_STOPTYPE}, 	
+/* 11 */ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_WATCHDOG_TIME,	STR_PARAM_WDTC,		    convertTimeMS}, 	
+/* 12 */ { 0, 0, PT_RO, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_PARAM_NETSTAT}, 	
+/* 13 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		6, 1,		PARAM_STATUS1_ACCUM,	STR_PARAM_STATUS}, 	
+/* 14 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		6, 1,		PARAM_STATUS1_ATTN_RISE,STR_PARAM_STATUS_ATTN_RISE}, 	
+/* 15 */ { 0, 0, PT_FCFG, 	BIT_FIELD,		4, 1,		PARAM_DRV_MODES,		STR_UNKNOWN}, 	
+/* 16 */ { 0, 0, PT_RO_RT, 	BIT_FIELD,		6, 1,		PARAM_STATUS1_RT,		STR_PARAM_STATUS_RT}, 	
+/* 17 */ { 0, 0, PT_RO_RT, 	TIME_MSEC,		1, 1,		PARAM_NULL,				STR_PARAM_TIMESTAMP,	convertTimeMS}, 
+/* 18 */ { 0, 0, PT_RO_RT, 	TIME_MSEC,		2, 1,		PARAM_NULL,				STR_PARAM_TIMESTAMP16,	convertTimeMS}, 
+/* 19 */ { 0, 0, PT_RO, 	STRING, MN_PART_NUM_SIZE,1,	PARAM_PART_NUM,			STR_PARAM_PART_NUM},
+/* 20 */ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_EE_UPD_ACK,		STR_PARAM_EE_ACK},
+/* 21 */ { 0, 0, PT_RO,		NO_UNIT,		2, 1,		PARAM_EE_VER,			STR_PARAM_EE_VER}, 	
+/* 22 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		6, 1,		PARAM_NULL,				STR_PARAM_STATUS_FALL}, 	
+/* 23 */ { 0, 0, PT_CFG, 	BIT_FIELD,		4, 1,		PARAM_CFG_HW,			STR_PARAM_CFG_HW}, 	
+/* 24 */ { 0, 0, PT_CFG, 	BIT_FIELD,		4, 1,		PARAM_CFG_APP,			STR_PARAM_CFG_FEAT}, 	
+/* 25 */ { 0, 0, PT_ROC_RT, BIT_FIELD,	   12, 1,		PARAM_WARN_ACCUM_REG,	STR_WARN_ACC}, 	
+/* 26 */ { 0, 0, PT_ROC_RT, NO_UNIT,	   12, 1,		PARAM_NULL,				STR_WARN_RT}, 	
+/* 27 */ { 0, 0, PT_VOL, 	NO_UNIT,	   12, 1,		PARAM_NULL,				STR_USER_WARN_MASK_REG}, 	
+/* 28 */ { 0, 0, PT_VOL, 	NO_UNIT,	   12, 1,		PARAM_NULL,				STR_USER_ALERT_MASK_REG}, 	
+/* 29 */ { 0, 0, PT_RO_RT, 	HOURS,		4, 10.*60.*60.,	PARAM_NULL,				STR_ON_TIME}, 	// .1 Sec -> Hours
+/* 30 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_POSN_CAP_INA_HI_SPD,	STR_PARAM_POSN_CAP_INA_HI_SPD}, 	
+/* 31 */ { 0, 0, PT_VOL, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_PARAM_USER_RAM0}, 	
+/* 32 */ { 0, 0, PT_NV_RW, 	NO_UNIT, MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE0}, 	
+/* 33 */ { 0, 0, PT_NV_RW, 	NO_UNIT, MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE1}, 	
+/* 34 */ { 0, 0, PT_NV_RW, 	NO_UNIT, MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE2}, 	
+/* 35 */ { 0, 0, PT_NV_RW, 	NO_UNIT, MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE3},
+/* 36 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_CHKSUM}, 	
+/* 37 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_FRAG}, 	
+/* 38 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_STRAY}, 	
+/* 39 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_OVERRUN}, 	
+/* 40 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_CHKSUM}, 	
+/* 41 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_FRAG}, 	
+/* 42 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_STRAY}, 	
+/* 43 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_OVERRUN}, 
+/* 44 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 45 */ { 0, 0, PT_VOL, 	BIT_FIELD,ATTN_MASK_OCTETS, 1,PARAM_NULL,			STR_PARAM_ATTN_MASK,	spscWatchAttnMask}, 	
+/* 46 */ { 0, 0, PT_NV_RW, 	TIME_MSEC,		2, 1,		PARAM_NULL,				STR_PARAM_GP_TIMER,		convertTimeMS}, 	
+/* 47 */ { 0, 1, PT_NV_RWA, DX_TICK,		4, 1,		PARAM_AT_POSN_LOC,		STR_PARAM_POSN_TRIG_PT},
+/* 48 */ { 0, 0, PT_NV_RWA, DX_TICK,		4, 1,		PARAM_A_AFTER_DIST,		STR_PARAM_A_START},
+/* 49 */ { 0, 0, PT_NV_RWA, DX_TICK,		4, 1,		PARAM_B_BEFORE_DIST,	STR_PARAM_B_END},
+/* 50 */ { 0, 0, PT_VOL, 	BIT_FIELD,		2, 1,		PARAM_XPS_USER_OUT_REG,	STR_PARAM_USER_OUT_REG}, 	
+/* 51 */ { 0, 0, PT_RO_RT,BIT_FIELD,		12, 1,		PARAM_ALERT_ACCUM_REG,	STR_UNKNOWN},
+/* 52 */ { 0, 0, PT_RO_RT, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_OUT_REG}, 	
+/* 53 */ { 0, 2, PT_FMTR, 	VEL_TICKS_S,	2, 1<<2,	PARAM_SPEED_LIM,		STR_DRV_SPEED_LIM,		convertSpdLim}, 	
+/* 54 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 55 */ { 0, 0, PT_VOL,	BIT_FIELD,ATTN_MASK_OCTETS,1,	PARAM_ATTN_MASK_DRVR,	STR_UNKNOWN,			spscWatchAttnMask}, 	
+/* 56 */ { 0, 0, PT_VOL,	BIT_FIELD,		6, 1,		PARAM_GRP_SHUTDOWN_MASK,STR_UNKNOWN}, 	
+//=======Motion Constraint group
+/* 57 */ { 0, 0, PT_RO_RT, 	TIME_MSEC,		2, 1,		PARAM_RAS_DELAY,		STR_RAS_DELAY,		    convertTimeMS}, 	
+/* 58 */ { 0, 2, PT_NV_RW, 	VEL_TICKS_S,	4, 1<<17,	PARAM_JOG_VEL_LIM,		STR_PARAM_VEL_LIMIT,	convertVel}, 	
+/* 59 */ { 0, 2, PT_NV_RW, 	VEL_TICKS_S2,	4,1<<17,	PARAM_JOG_ACC_LIM,		STR_PARAM_ACC_LIMIT,	convertAcc},
+/* 60 */ { 0, 1, PT_RO_RT, 	VEL_TICKS_S,	4, 1<<18,	PARAM_NULL,				STR_UNKNOWN,			convertVel},
+/* 61 */ { 0, 2, PT_NV_RW, 	VEL_TICKS_S,	4, 1<<17,	PARAM_VEL_LIM,			STR_PARAM_VEL_LIMIT,	convertVel}, 	
+/* 62 */ { 0, 2, PT_NV_RW, 	VEL_TICKS_S2,	4,1<<17,	PARAM_ACC_LIM,			STR_PARAM_ACC_LIMIT,	convertAcc},
+/* 63 */ { 0, 0, PT_CFG, 	BIT_FIELD,		4, 1,		PARAM_CMD_TUNE_REG,		STR_PARAM_RAS_CON_REG,	convertJerk}, 	
+/* 64 */ { 0, 2, PT_NV_RWA, VEL_TICKS_S2,	4,1<<17,	PARAM_DEC_LIM,			STR_PARAM_DEC_LIMIT,	convertAcc},
+/* 65 */ { 0, 0, PT_CFG, 	VEL_TICKS_S2,	4,1<<17,	PARAM_ESTOP_DECEL,		STR_PARAM_STOPACC_LIM,	convertAcc},
+/* 66 */ { 0, 0, PT_NV_RWA,	DX_TICK,		4, 1,		PARAM_HEAD_DX,			STR_PARAM_HEAD_DX},
+/* 67 */ { 0, 0, PT_NV_RWA,	DX_TICK,		4, 1,		PARAM_TAIL_DX,			STR_PARAM_TAIL_DX},
+/* 68 */ { 0, 0, PT_NV_RWA,	VEL_TICKS_S,	4, 1<<17,	PARAM_HT_VEL_LIM,		STR_PARAM_HEADTAIL_VEL,	convertVel},	
+/* 69 */ { 0, 0, PT_NV_RW, 	TIME_MSEC,		2, 1,		PARAM_MOVE_DWELL,		STR_PARAM_DWELL,		convertTimeMS}, 	
+/* 70 */ { 0, 0, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_SOFT_LIM_POSN_POS,STR_PARAM_SOFT_LIM_POS},
+/* 71 */ { 0, 0, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_SOFT_LIM_POSN_NEG,STR_PARAM_SOFT_LIM_NEG},
+/* 72 */ { 0, 2, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_STOP_QUAL_TC,		STR_UNKNOWN,			convertTimeMS}, 	
+/* 73 */ { 0, 1, PT_RAM, 	NO_UNIT,	2, (1<<15)/100.,PARAM_VOLTSQ_CMD,	STR_UNKNOWN}, 	
+/* 74 */ { 0, 2, PT_CFG, 	VEL_TICKS_S,	4, 1<<18,	PARAM_STOP_QUAL_VEL,	STR_UNKNOWN,			convertVel}, 
+/* 75 */ { 0, 0, PT_NV_RW, 	VEL_TICKS_S,	4, 1<<17,	PARAM_AT_MAX_VEL,		STR_PARAM_VEL_LIMIT_MAX,	convertVel}, /*CPM_P_DRV_VEL_LIM_MAX*/ 	
+/* 76 */ { 0, 0, PT_NV_RW, 	VEL_TICKS_S2,	4, 1<<17,	PARAM_AT_MAX_ACC,		STR_PARAM_ACC_LIMIT_MAX,	convertAcc}, /*CPM_P_DRV_ACC_LIM_MAX*/
+/* 77 */ { 0, 2, PT_NV_RW, 	VEL_TICKS_S2,	4, 1<<17,	PARAM_NULL/*AT_MAX_DECEL*/,	STR_PARAM_STOPACC_LIM_MAX,	convertAcc}, /*CPM_P_DRV_DEC_LIM_MAX*/
+/* 78 */ { 0, 2, PT_FAC, 	NO_UNIT,		4, 1<<17,	PARAM_RMS_STOPPED_FACTOR,STR_UNKNOWN,			convertRMSFactor}, 	
+//=======Motion Status Group
+/* 79 */ { 0, 2, PT_FMTR, 	VEL_TICKS_S,	2, 1<<2,	PARAM_RMS_STOPPED_SPEED,STR_UNKNOWN,			convertSpdLim}, 
+/* 80 */ { 0, 1, PT_RO_RT, 	CURRENT,		2, 1<<15,	PARAM_TRQ_CMD,			STR_DRV_TRQ_CMD,		convertAmperes},
+/* 81 */ { 0, 1, PT_RO_RT, 	CURRENT,		2, 1<<15, 	PARAM_TRQ_MEAS,			STR_DRV_TRQ_MEAS,		convertMeasAmperes},
+/* 82 */ { 0, 0, PT_RO_RT, 	CURRENT,		4, 1,		PARAM_RMS_LVL,			STR_DRV_RMS_LEVEL,		convertRMSlevel}, 
+/* 83 */ { 0, 1, PT_RO_RT, 	DX_TICK,		3, 1,		PARAM_NULL,				STR_PARAM_I_MEAS_POSN},
+/* 84 */ { 0, 1, PT_RO_RT, 	DX_TICK,		3, 1,		PARAM_NULL,				STR_PARAM_I_CMD_POSN},
+/* 85 */ { 0, 1, PT_RO_RT, 	VEL_TICKS_S,	4, 1<<18,	PARAM_VEL_MEAS,			STR_PARAM_MEAS_VEL,		convertVel},
+/* 86 */ { 0, 1, PT_RO_RT, 	VEL_TICKS_S,	4, 1<<18,	PARAM_VEL_CMD,			STR_PARAM_CMD_VEL,		convertVel},
+/* 87 */ { 0, 1, PT_RO_RT, 	DX_TICK,	    3, 1,		PARAM_NULL,				STR_PARAM_I_MEAS_POSN_MTR},
+/* 88 */ { 0, 0, PT_RO_RT, 	CURRENT,		4, 1,		PARAM_RMS_SLOW_LVL,		STR_DRV_RMS_LEVEL,		convertRMSlevelSlow}, 
+/* 89 */ { 0, 2, PT_RO_RT, 	VEL_TICKS_S2,	4,1<<18,	PARAM_NULL,				STR_PARAM_ACC_MAX,		convertAcc},
+/* 90 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_TRK_ERR,			STR_PARAM_POSN_TRK},
+/* 91 */ { 0, 1, PT_CFG, 	DX_TICK,		4, 1,		PARAM_IN_RANGE_WIN,		STR_PARAM_POS_TRK_RNG,  checkPosnLimit},
+/* 92 */ { 0, 2, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_MV_DN_TC,			STR_DRV_MV_DN_TC,		convertTimeMS}, 
+/* 93 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_INDEX_POSN_CAP}, 	
+/* 94 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, /*Hi-Res cmd posn*/	
+/* 95 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, /*Hi-Res meas posn*/
+/* 96 */ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, /*Steps accumulator*/
+/* 97 */ { 0, 2, PT_CFG, 	VEL_TICKS_S,2, (1<<15)/100,	PARAM_IN_RANGE_VEL,	STR_UNKNOWN}, 		
+/* 98 */ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_MOVE_OPTIONS,		STR_UNKNOWN},
+/* 99 */ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_IN1_TC,			STR_INPUT1_TC,			convertTimeMS},
+/* 100*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 101*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 102*/ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_IN1_IN2_TC,		STR_INPUT2_TC,			convertTimeMS},
+/* 103*/ { 0, 0, PT_NONE, 	DEGREES,		4, 1,		PARAM_VECTOR_DRIFT_LIM,	STR_UNKNOWN}, 
+//=======Sensorless Start Group
+/* 104*/ { 0, 0, PT_CFG,    DEGREES,	4, (1<<17)/360.,PARAM_COMM_ANGLE_LIM,	STR_DRV_COMM_CHK_ANGLE_LIM}, 	
+/* 105*/ { 0, 0, PT_CFG,	TIME_MSEC,		2, 1,		PARAM_HLESS_RAMPUP_TIME,STR_DRV_HLESS_RAMPUP_TIME,convertTimeMS}, 	
+/* 106*/ { 0, 0, PT_CFG,	TIME_MSEC,		2, 1,		PARAM_HLESS_SWEEP_TIME,	STR_DRV_HLESS_SWEEP_TIME,convertTimeMS}, 	
+/* 107*/ { 0, 0, PT_CFG,	TIME_MSEC,		2, 1,		PARAM_HLESS_SETTLE_TIME,STR_DRV_HLESS_SETTLE_TIME,convertTimeMS}, 	
+/* 108*/ { 0, 0, PT_FMTR,	VOLT,			2, 1<<5,	PARAM_HLESS_VOLTS,		STR_DRV_HLESS_VOLTS}, 	
+/* 109*/ { 0, 0, PT_FMTR,	NO_UNIT,		2, 1,		PARAM_HLESS_RDG,		STR_DRV_HLESS_RDG_SAMPLES}, 	
+/* 110*/ { 0, 0, PT_FMTR,	NO_UNIT,		2, 1,		PARAM_HLESS_SETUP,		STR_DRV_HLESS_SETUP_SAMPLES}, 	
+/* 111*/ { 0, 1, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_HLESS_VERIFY_TRQ_TIME,STR_UNKNOWN,		convertTimeMS},
+/* 112*/ { 0, 0, PT_RAM_RT,	NO_UNIT,		24, 1,		PARAM_NULL,				STR_ENC_QUAL},
+/* 113*/ { 0, 0, PT_CFG, 	DX_TICK,	2, (1<<15)/360.,PARAM_HLESS_VERIFY_MAX_MOTION,STR_UNKNOWN},
+/* 114*/ { 0, 0, PT_CFG, 	DX_TICK,	2, (1<<15)/360.,PARAM_HLESS_VERIFY_MIN_MOTION,STR_UNKNOWN},
+/* 115*/ { 0, 1, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_HLESS_VERIFY_RAMP_TIME,STR_UNKNOWN,		convertTimeMS},
+// 		 1/x, signed, type,  unit,    size, scale,		config key id,			description, 			[converter]
+};
+#define PARAM_BASE_COUNT (sizeof(cpmInfoDB)/sizeof(paramInfoLcl))
+// Node class database
+static byNodeClassDB cpmClassDB = {
+	NULL 					// Parameter change function
+};
+
+
+static const paramInfoLcl cpmDrvInfoDB[] = {
+// 		 1/x, signed, type,  unit,    size, scale,		config key id,			description, 			[converter]
+//=======Factory Settings===================
+/* 256*/ { 0, 1, PT_FCFG, 	CURRENT,		2, 1<<14,	PARAM_ADC_MAX,			STR_DRV_ADC_MAX,		convertADCmax}, 	
+/* 257*/ { 0, 1, PT_FCFG, 	CURRENT,		2, 1<<9,	PARAM_I_MAX,			STR_DRV_DRV_I_MAX}, 
+/* 258*/ { 0, 2, PT_FCFG, 	CURRENT,		2, 1,		PARAM_RMS_MAX,			STR_DRV_RMS_MAX,		convertRMSlimit}, 
+/* 259*/ { 0, 0, PT_FAC, 	NO_UNIT,		2, 1<<14,	PARAM_IR_CAL_FACTOR,	STR_DRV_IR_CAL},
+/* 260*/ { 0, 0, PT_FAC, 	NO_UNIT,		2, 1<<14,	PARAM_IS_CAL_FACTOR,	STR_DRV_IS_CAL},
+/* 261*/ { 0, 0, PT_FAC, 	NO_UNIT,		2, 1,		PARAM_KM_FACT,			STR_P_DRV_PWR_LIM_EXP}, 	
+/* 262*/ { 0, 0, PT_FAC, 	NO_UNIT,		2, 1<<9,	PARAM_MTR_OHMS_MIN,		STR_P_DRV_RES_MIN}, 	
+/* 263*/ { 0, 2, PT_FAC, 	TIME_MSEC,		2, 1,		PARAM_IB_TC,			STR_P_IB_FILT_TC,		convertIBRMStc}, 	
+/* 264*/ { 0, 1, PT_FAC, 	CURRENT,		2, 1U<<15,	PARAM_IB_TRIP_RMS,		STR_P_IB_TRIP,			convertAmpsRMS}, 	
+/* 265*/ { 0, 0, PT_FAC, 	CURRENT,		2, 1U<<15,	PARAM_I_TRIP,			STR_P_PHASE_TRIP,		convertMeasAmperes}, 	
+/* 266*/ { 0, 2, PT_FAC, 	VOLT,			2, 1<<5,	PARAM_BUS_V_MAX,		STR_DRV_BUS_VOLTS}, 	
+/* 267*/ { 0, 2, PT_CFG,	CURRENT,		2, 1<<15,	PARAM_NO_COMM_START_TRQ,STR_DRV_HLESS_TRQ,		convertAmperes},
+/* 268*/ { 0, 2, PT_FAC, 	VOLT,			2, 1<<5,	PARAM_OVER_V_TRIP,		STR_OVER_VOLTS_TRIP}, 	
+/* 269*/ { 0, 0, PT_FAC, 	NO_UNIT,		2, 1<<14,	PARAM_BUS_V_CAL,		STR_DRV_VBUS_CAL},
+//=======Safety Related  Parameters=========
+/* 270*/ { 0, 2, PT_MTR_R, 	NO_UNIT,		4, 1,		PARAM_RMS_LIM,			STR_DRV_RMS_LIM,		convertRMSlimit32}, 	
+/* 271*/ { 0, 2, PT_MTR, 	TIME_S,			2, 1,		PARAM_RMS_TC,			STR_DRV_RMS_TC,			convertRMStc}, 	
+/* 272*/ { 0, 4, PT_CFG, 	DX_TICK,		4, 1,		PARAM_TRK_ERR_LIM,		STR_DRV_TRK_ERR_LIM,	checkPosnLimit},
+/* 273*/ { 0, 1, PT_CFG, 	PERCENT_MAX,2, (1<<15)/100.,PARAM_RMS_INIT,			STR_DRV_RMS_INIT}, 	
+/* 274*/ { 0, 0, PT_RO_RT, 	CURRENT,		4, 1U<<31,	PARAM_IB_PEAK,			STR_P_IB_RT,			convertAmpsRMS}, 
+/* 275*/ { 0, 2, PT_MTR_R, 	NO_UNIT,		4, 1,		PARAM_RMS_SLOW_LIM,		STR_DRV_RMS_LIM,		convertRMSlimit32}, 	
+/* 276*/ { 0, 0, PT_RO_RT,	VOLT,			2, 32768./3.3,PARAM_NULL,			STR_UNKNOWN},     
+/* 277*/ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_POSN_CAP_INB,		STR_PARAM_POSN_CAP_INB}, 	
+//=======Status Related Parameters==========
+/* 278*/ { 0, 0, PT_RO_RT, 	VOLT,			2, 1U<<15,	PARAM_BUS_AT_ENBL,		STR_BUS_AT_ENBL,		convertMeasVolts}, 	
+/* 279*/ { 0, 0, PT_RO_RT, 	VOLT,		2, 32768./6.6,	PARAM_TP5V,				STR_PARAM_TP_5V},	
+/* 280*/ { 0, 2, PT_RO_RT, 	VOLT,			2, 1U<<15,	PARAM_BUS_V,			STR_DRV_BUS_VOLTS,		convertMeasVolts}, 
+/* 281*/ { 0, 0, PT_RW_RT, 	NO_UNIT,		2, 1,		PARAM_NV_MODIFIED,		STR_DRV_DIRTY}, 
+/* 282*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1,		PARAM_VECT_RATE,		STR_DRV_VECTOR_RATE}, 
+/* 283*/ { 0, 0, PT_RO_RT, 	NO_UNIT,	2, 32768./3.3,	PARAM_TP1_65V,			STR_PARAM_TP_REF},
+/* 284*/ { 0, 0, PT_RO_RT, 	NO_UNIT,	2, 32768./36.3,	PARAM_TP12V,			STR_PARAM_TP_12V},
+/* 285*/ { 0, 0, PT_RO_RT, 	BIT_FIELD,		4, 1,		PARAM_TP_IOP,			STR_DRV_TP_IOP}, 
+/* 286*/ { 0, 1, PT_RO_RT, 	CURRENT,		2, 1U<<15,	PARAM_TP_IR,			STR_DRV_TP_IR,			convertMeasAmperes}, 
+/* 287*/ { 0, 1, PT_RO_RT, 	CURRENT,		2, 1U<<15,	PARAM_TP_IS,			STR_DRV_TP_IS,			convertMeasAmperes}, 
+/* 288*/ { 0, 0, PT_FAC, 	TIME_MSEC,		2, 1,		PARAM_I_TP_FILT,		STR_P_IR_IS_TP_FILT_TC,	convertFilt1TCMilliseconds}, 
+/* 289*/ { 0, 1, PT_RO_RT,	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_DRV_TP_IR_FILT,		convertMeasAmperes}, 	
+/* 290*/ { 0, 1, PT_RO_RT, 	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_DRV_TP_IS_FILT,		convertMeasAmperes}, 	
+/* 291*/ { 0, 1, PT_RO_RT, 	DEG_C,			2, 1,		PARAM_DRV_TEMP,			STR_P_PWBA_TEMP}, 
+/* 292*/ { 0, 1, PT_VOL, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_TEMP_SIM}, 
+/* 293*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_DSP_INFO}, 	
+/* 294*/ { 0, 0, PT_RO_RT, 	CURRENT,		4, 1U<<31,	PARAM_IB,				STR_P_IB_RMS,			convertAmpsRMS}, 	
+/* 295*/ { 0, 0, PT_RO_RT, 	TIME_USEC,		4, 1000,	PARAM_TSPD,				STR_P_TSPD}, 	
+/* 296*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_BAD_TSPD_CNT},
+/* 297*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_BAD_SLOT_CNT},
+/* 298*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_LOAD_SLOT0}, 	
+/* 299*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_LOAD_SLOT1}, 	
+/* 300*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_LOAD_SLOT2}, 	
+/* 301*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_LOAD_SLOT3}, 	
+/* 302*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_AVG_LOAD}, 	
+/* 303*/ { 0, 1, PT_NONE, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 304*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 305*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 306*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IR_OFFSET}, 	
+/* 307*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IS_OFFSET}, 	
+/* 308*/ { 0, 0, PT_FAC, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_OVER_TEMP}, 	
+//=======Motor Related Params===============
+/* 309*/ { 0, 1, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_KIP_ADJ,			STR_DRV_KIP}, 	
+/* 310*/ { 0, 2, PT_FMTR, 	DX_TICK,		4, 1,		PARAM_ENC_DENS,			STR_DRV_ENC_DENS}, 	
+/* 311*/ { 0, 2, PT_FMTR, 	NO_UNIT,		2, 1,		PARAM_POLES,			STR_DRV_POLES}, 	
+/* 312*/ { 0, 2, PT_FMTR, 	VOLTS_PER_KRPM,	4, 1<<7,	PARAM_MTR_KE,			STR_DRV_MTR_KE}, 	
+/* 313*/ { 0, 2, PT_FMTR, 	NO_UNIT,		2, 1<<9,	PARAM_MTR_OHMS,			STR_DRV_MTR_OHMS}, 	
+/* 314*/ { 0, 2, PT_FMTR, 	NO_UNIT,		2, 1<<9,	PARAM_MTR_ELECT_TC,		STR_DRV_MTR_ELEC_TC}, 	
+/* 315*/ { 0, 1, PT_FMTR, 	DEGREES,		2,32768/360,PARAM_RO,				STR_DRV_RO}, 	
+/* 316*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_NULL},
+/* 317*/ { 0, 0, PT_RW_RT, 	DEGREES,		4, 1,		PARAM_MECH_ANGLE,		STR_DRV_ANGLE,			convertAngle}, 	
+/* 318*/ { 0, 2, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_KIP,				STR_DRV_KIP}, 
+/* 319*/ { 0, 2, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_KII,				STR_DRV_KII}, 
+/* 320*/ { 0, 0, PT_CFG, 	DX_TICK,		4, 1,		PARAM_STEP_RES,			STR_DRV_CMD_DENS}, 	// request step/rev
+/* 321*/ { 0, 1, PT_FMTR, 	VEL_TICKS_S,	2, 1<<2,	PARAM_INDEX_DETECT_SPEED,STR_DRV_SPEED_LIM,		convertSpdLim}, 
+/* 322*/ { 0, 0, PT_FMTR, 	NO_UNIT,		4, 1,		PARAM_STEP_RES_ACTIVE,	STR_UNKNOWN}, 	
+/* 323*/ { 0, 2, PT_CFG, 	NO_UNIT,		2, 1<<9,	PARAM_KR,				STR_DRV_KR}, 	
+/* 324*/ { 0, 1, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_KII_ADJ,			STR_DRV_KII}, 	
+//=======Tuning Related Params==============
+/* 325*/ { 0, 0, PT_CFG, 	BIT_FIELD,		4, 1,		PARAM_CFG_TUNE,			STR_PARAM_CFG_TUNE}, 	
+/* 326*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KV,				STR_DRV_KV}, 
+/* 327*/ { 0, 2, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KP_OUT,			STR_DRV_KP}, 
+/* 328*/ { 0, 2, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KI_OUT,			STR_DRV_KI}, 
+/* 329*/ { 0, 1, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KFV,				STR_DRV_KFV}, 
+/* 330*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KFA,				STR_DRV_KFA,			limit2To27}, 
+/* 331*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KFJ,				STR_DRV_KFJ,			limit2To27}, 
+/* 332*/ { 0, 0, PT_RO_RT, 	BIT_FIELD,		4, 1,		PARAM_NULL,				STR_UNKNOWN },
+/* 333*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KNV,				STR_DRV_KNV}, 
+/* 334*/ { 0, 0, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_AH_VOLT_FILT_TC,	STR_DRV_AH_FILT_TC,		convertFilt99pctMilliseconds}, 
+/* 335*/ { 0, 1, PT_CFG, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_BIAS,			STR_DRV_TRQ_BIAS,		convertAmperes}, 
+/* 336*/ { 0, 0, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_FUZZY_APERTURE,	STR_DRV_FUZZ_AP}, 
+/* 337*/ { 0, 0, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_ANTI_HUNT_HYSTERESIS,	STR_DRV_FUZZ_HYST}, 
+/* 338*/ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_AH_HOLDOFF,		STR_DRV_AH_HOLDOFF,		convertTimeMS}, 	
+/* 339*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KP_ZERO,			STR_DRV_KZERO}, 	
+/* 340*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1,		PARAM_KI_ZERO,			STR_DRV_IZERO}, 	
+/* 341*/ { 0, 0, PT_CFG, 	DX_TICK,		2, 1,		PARAM_TGT_WIN,			STR_DRV_TARGET_WIN}, 	
+/* 342*/ { 0, 0, PT_CFG, 	DX_TICK,		2, 1,		PARAM_STAB_WIN,			STR_DRV_STAB_WIN}, 	
+/* 343*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_INERTIA,			STR_MTR_INERTIA}, /*CPM_P_MTR_INERTIA*/ 	
+/* 344*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_STATIC_FRICTION,	STR_MTR_STAT_FRICTION}, /*CPM_P_MTR_STATIC_FRICTION*/	
+/* 345*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_VISCOUS_FRICTION,	STR_MTR_VISC_FRICTION}, /*CPM_P_MTR_VISCOUS_FRICTION*/	
+/* 346*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1<<16,	PARAM_DRV_KP_FACTOR,	STR_UNKNOWN}, 	
+/* 347*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1<<16,	PARAM_DRV_KPZ_FACTOR,	STR_UNKNOWN}, 	
+/* 348*/ { 0, 0, PT_CFG, 	NO_UNIT,		4, 1<<16,	PARAM_DRV_KI_FACTOR,	STR_UNKNOWN}, 	
+/* 349*/ { 0, 0, PT_CFG, 	NO_UNIT,		2, 1,		PARAM_DRV_FINE_TUNE,	STR_UNKNOWN}, 	
+//=======Foldback Related Parameters========
+/* 350*/ { 0, 2, PT_CFG, 	CURRENT,		2, 1<<15,	PARAM_TRQ_LIM,			STR_DRV_TRQ_LIM,		convertAmperes}, 
+/* 351*/ { 0, 2, PT_CFGA, 	CURRENT,		2, 1<<15,	PARAM_TRQ_FLDBACK_POS,	STR_DRV_TRQ_FLDBACK_POS,convertAmperes}, 
+/* 352*/ { 0, 2, PT_CFGA, 	TIME_MSEC,		2, 1,		PARAM_TRQ_FLDBACK_POS_TC,STR_DRV_TRQ_FB_POS_TC, convertFilt99pctMilliseconds}, 
+/* 353*/ { 0, 2, PT_CFGA, 	CURRENT,		2, 1<<15,	PARAM_TRQ_FLDBACK_NEG,	STR_DRV_TRQ_FLDBACK_NEG,convertAmperes}, 
+/* 354*/ { 0, 2, PT_CFGA, 	TIME_MSEC,		2, 1,		PARAM_TRQ_FLDBACK_NEG_TC,STR_DRV_TRQ_FB_NEG_TC, convertFilt99pctMilliseconds}, 
+/* 355*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 356*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 357*/ { 0, 2, PT_CFG, 	CURRENT,		2, 1<<15,	PARAM_TRQ_FLDBACK_HS,	STR_DRV_HS_FLDBACK, 	convertAmperes}, 
+/* 358*/ { 0, 2, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_TRQ_FLDBACK_HS_TC,STR_DRV_HS_FB_TC,   	convertFilt99pctMilliseconds}, 
+/* 359*/ { 0, 2, PT_CFG,	VEL_TICKS_S,	4, 1<<18,	PARAM_HS_STOP_VEL,		STR_DRV_HS_QUAL_SPEED,	convertVel}, 	
+/* 360*/ { 0, 2, PT_CFG,	CURRENT,	2,(1U<<15)/100.,PARAM_HS_THRESHOLD,	STR_DRV_HS_TRQ_TRIP}, 
+/* 361*/ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_HS_TC,			STR_DRV_HS_TC,			convertTimeMS},
+/* 362*/ { 0, 2, PT_CFG, 	VOLT,			2, 1<<5,	PARAM_REGEN_OFF_V,		STR_UNKNOWN}, 
+/* 363*/ { 0, 2, PT_CFG, 	CURRENT,		2, 1<<15,	PARAM_HOMING_TRQ_LIM,	STR_DRV_HS_TRQ_LIM,		convertAmperes}, 
+/* 364*/ { 0, 2, PT_MTR, 	TIME_MIN,		2, 1,		PARAM_RMS_SLOW_TC,		STR_DRV_RMS_TC,			convertRMSSlowtc}, 
+/* 365*/ { 0, 0, PT_FAC, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 366*/ { 0, 0, PT_FAC, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 367*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_MECH_POSN,		STR_UNKNOWN}, 	
+/* 368*/ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_DLY_TO_DISABLE,	STR_UNKNOWN,			convertTimeMS}, 	
+/* 369*/ { 0, 1, PT_FAC, 	UNIT_HZ,		4, 1,		PARAM_SOFT_START_FREQ,	STR_UNKNOWN}, 	
+/* 370*/ { 0, 2, PT_CFG,	TIME_MSEC,		2, 1,		PARAM_REGEN_RAMP_TIME,	STR_UNKNOWN,			convertFilt99pctMilliseconds}, 	
+/* 371*/ { 0, 2, PT_CFG,	VOLT,			2, 1<<5,	PARAM_REGEN_ON_V,		STR_UNKNOWN},
+/* 372*/ { 0, 2, PT_CFG,	TIME_MSEC,		2, 1,		PARAM_BUSV_ADJ_RATE,	STR_UNKNOWN}, 	
+/* 373*/ { 0, 0, PT_RAM_RT,	NO_UNIT,		4, 1<<16,	PARAM_PULSE_VEL_ADJ,	STR_UNKNOWN,			convertVel}, 	
+/* 374*/ { 0, 0, PT_RAM_RT, NO_UNIT,		2, 1,		PARAM_PULSE_INCR_ADJ,	STR_UNKNOWN}, 	
+/* 375*/ { 0, 0, PT_RAM_RT, NO_UNIT,		4, 1,		PARAM_SET_FLAGS,		STR_UNKNOWN}, 	
+/* 376*/ { 0, 0, PT_RAM, 	VOLT,		2, 32768./3.3,	PARAM_NULL,				STR_PARAM_TP_REF_SIM},
+/* 377*/ { 0, 0, PT_RAM, 	VOLT,			2, 1U<<15,	PARAM_NULL,				STR_DRV_BUS_VOLTS_SIM,	convertMeasVolts}, 
+/* 378*/ { 0, 0, PT_RAM,	NO_UNIT,		4, 1,		PARAM_RUNTIME_FLAGS,	STR_UNKNOWN}, 	
+/* 379*/ { 0, 1, PT_RO,		DEG_C,			2, 1U<<6,	PARAM_NULL,				STR_UNKNOWN}, 	
+/* 380*/ { 0, 1, PT_RO_RT,	DEG_C,			2, 1U<<6,	PARAM_ENCODER_TEMP,		STR_UNKNOWN},
+/* 381*/ { 0, 1, PT_RO_RT,	DEG_C,			2, 1U<<6,	PARAM_STATOR_TEMP,		STR_UNKNOWN},
+/* 382*/ { 0, 1, PT_RO,		DEG_C,			2, 1U<<6,	PARAM_NULL,				STR_UNKNOWN}, 	
+/* 383*/ { 0, 1, PT_RO,		DEG_C,			2, 1U<<6,	PARAM_NULL,				STR_UNKNOWN}, 	
+};
+
+#define PARAM_DRV_COUNT (sizeof(cpmDrvInfoDB)/sizeof(paramInfoLcl))
+
+
+
+// Application runtime 
+static const paramInfoLcl cpmAppInfoDB[] = {
+// 		 1/x, signed, type,  unit,    size, scale,		config key id,			description, 			[converter]
+// ======Homing parameters====
+/* 512*/ { 0, 1, PT_CFG,	VEL_TICKS_S,	4, 1<<17,	PARAM_ABSPOSN_HOMING_VEL,STR_HOME_VEL,			convertVel}, 	
+/* 513*/ { 0, 0, PT_CFG, 	DX_TICK,		4, 1,		PARAM_HOMING_OFFSET,	STR_HOME_OFFS},	//homing offset
+/* 514*/ { 0, 0, PT_CFG, 	VEL_TICKS_S2,	4,1<<17,	PARAM_HOMING_ACCEL,		STR_HOME_ACCEL,			convertAcc}, 	
+/* 515*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 516*/ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_HS_DELAY_TIME,	STR_HOME_DELAY,			convertTimeMS}, 
+/* 517*/ { 0, 0, PT_CFG, 	NO_UNIT,	   12, 1,		PARAM_EVENT_SHUTDOWN_MASK,	STR_UNKNOWN },
+/* 518*/ { 0, 2, PT_CFG, 	TIME_SAMPLE,	2, 1,		PARAM_PWR_AC_LOSS_TC,	STR_UNKNOWN,			convertTimeMS },
+/* 519*/ { 0, 2, PT_CFG, 	TIME_SAMPLE,	2, 1,		PARAM_PWR_AC_WIRING_ERROR_TC,STR_UNKNOWN,			convertTimeMS },
+/* 520*/ { 0, 2, PT_FAC, 	VOLT,			2, 1<<5,	PARAM_BUS_V_LOW,		STR_SLESS_MIN_VOLTS},
+/* 521*/ { 0, 0, PT_CFG, 	TIME_MSEC,		2, 1,		PARAM_POWERUP_HOLDOFF_TIME,STR_UNKNOWN,			convertTimeMS}, 
+/* 522*/ { 0, 0, PT_FAC, 	VOLT,			2, 1<<5,	PARAM_COMM_LOW_V,		STR_COMM_LOW_V },
+/* 523*/ { 0, 2, PT_FAC, 	TIME_MSEC,		2, 1,		PARAM_IB_TC_SLOW,		STR_P_IB_FILT_TC,		convertIBRMSSlowtc}, 
+/* 524*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 
+
+/* 525*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 526*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 527*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 528*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 529*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 530*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 531*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 532*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 533*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 534*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+
+/* 535*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 536*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 537*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 538*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 539*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+#define UDSZ SC_USER_DESCR_CHUNK
+/* 540*/ { 0, 0, PT_NV_RW, 	NO_UNIT,	 UDSZ, 1,		PARAM_NULL,				STR_USR_DESC0}, 
+/* 541*/ { 0, 0, PT_NV_RW,  NO_UNIT,	 UDSZ, 1,		PARAM_NULL,				STR_USR_DESC1}, 	
+/* 542*/ { 0, 0, PT_NV_RW,  NO_UNIT,	 UDSZ, 1,		PARAM_NULL,				STR_USR_DESC2}, 	
+/* 543*/ { 0, 0, PT_NV_RW,  NO_UNIT,	 UDSZ, 1,		PARAM_NULL,				STR_USR_DESC3}, 	
+/* 544*/ { 0, 0, PT_NV_RW,  NO_UNIT,	 UDSZ, 1,		PARAM_NULL,				STR_USR_DESC4}, 	
+// ======Cross-point switch====
+/* 545*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_OUT_SRC_REG,		STR_XPS_OUTPUT_SRC_REG}, 
+/* 546*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_IN_SRC_REG,		STR_UNKNOWN}, 
+/* 547*/ { 0, 0, PT_NONE, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_UNKNOWN}, 
+/* 548*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_USER_IN_REG,		STR_UNKNOWN}, 
+/* 549*/ { 0, 0, PT_RO_RT, 	BIT_FIELD,		2, 1,		PARAM_XPS_ACTUAL_IN_REG,	STR_UNKNOWN}, 
+/* 550*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_INVERT_INPUT,		STR_XPS_INVERT_INPUT}, 
+/* 551*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_INVERT_OUTPUT,	STR_XPS_INVERT_OUTPUT}, 
+/* 552*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_XPS_FEAT_00}, 
+/* 553*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_XPS_FEAT_01}, 
+/* 554*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_ENABLE,		STR_XPS_FEAT_02}, 
+/* 555*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_XPS_FEAT_03}, 
+/* 556*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_TRIGGER,		STR_XPS_FEAT_04}, 
+/* 557*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_NODE_STOP,	STR_XPS_FEAT_05}, 
+/* 558*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_RESET_TIMER,	STR_XPS_FEAT_06}, 
+/* 559*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_ATTN0,		STR_XPS_FEAT_07}, 
+/* 560*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_ATTN1,		STR_XPS_FEAT_08}, 
+/* 561*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_XPS_FEAT_09}, 
+/* 562*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_XPS_FEAT_10}, 
+/* 563*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_AT_HOME,		STR_XPS_FEAT_11}, 
+/* 564*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_POS_TRQ_FLBK,STR_XPS_FEAT_12}, 
+/* 565*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_NEG_TRQ_FLBK,STR_XPS_FEAT_13}, 
+/* 566*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_IN_POS_LIM,	STR_XPS_FEAT_14}, 
+/* 567*/ { 0, 0, PT_CFG, 	BIT_FIELD,		2, 1,		PARAM_XPS_FEAT_IN_NEG_LIM,	STR_XPS_FEAT_15},
+// ======User Soft Limits====
+/* 568*/ { 0, 0, PT_CFG, 	DX_TICK,		4, 1,		PARAM_SOFT_LIM_POSN_1,		STR_UNKNOWN},
+/* 569*/ { 0, 0, PT_CFG, 	DX_TICK,		4, 1,		PARAM_SOFT_LIM_POSN_2,		STR_UNKNOWN},
+/* 570*/ { 0, 0, PT_RAM_RT, NO_UNIT,		2, 1,		PARAM_NULL,					STR_UNKNOWN },
+/* 571*/ { 0, 0, PT_RAM_RT, NO_UNIT,		2, 1,		PARAM_NULL,					STR_UNKNOWN },
+/* 572*/ { 0, 0, PT_RO_RT,	NO_UNIT,		4, 1,		PARAM_PWR_STATUS,			STR_UNKNOWN },
+/* 573*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,					STR_UNKNOWN },
+/* 574*/ { 0, 0, PT_FAC,	NO_UNIT, 		4, 1,		PARAM_DRV_PB_SER_NUM,		STR_UNKNOWN },
+/* 575*/ { 0, 0, PT_FAC,	HW_VERS, 		2, 1,		PARAM_DRV_PB_REV,			STR_UNKNOWN },
+/* 576*/ { 0, 1, PT_VOL, 	NO_UNIT,		2, 1,		PARAM_NULL,					STR_P_TEMP_SIM },
+/* 577*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,					STR_UNKNOWN },
+/* 578*/ { 0, 2, PT_CFG,	VOLT,			2, 1 << 5,	PARAM_DRV_MIN_OPER_VOLTS,	STR_UNKNOWN },
+/* 579*/ { 0, 2, PT_CFG,	DEG_C,			2, 1,		PARAM_TEMP_LIM_USER,		STR_UNKNOWN },
+/* 580*/ { 0, 1, PT_NV_RW, 	NO_UNIT,		2, 1U << 15,PARAM_IB_TRIP_USER,			STR_P_IB_TRIP,			convertAmpsRMS },
+};
+#undef UDSZ
+#define PARAM_APP_COUNT (sizeof(cpmAppInfoDB)/sizeof(paramInfoLcl))
+
+#define DFLT_HS_FLDBK_TC	200
+
+// Hw Config Default:
+//   Sensorless @ First Enable, use inductive sensorless modes,
+//   A After Start, B Before End, At Posn Capture all use measured position,
+//   Input A/B position capture happens on assertion of input,
+//   Homing mode is to switch (not hardstop)
+#define DFLT_HW_CFG_REG		(0x00102c70)
+// AC units get VRS enabled, AC powered flag, and Vector Validation enabled by default
+#define DFLT_HW_CFG_REG_AC	(DFLT_HW_CFG_REG|0x80|0x10000|0x100)
+
+// Application configuration register
+// Tuning mode, trigGrp 0, No limits (HW or SW), Limit stop type is ramp,
+// Don't invert direction for S&D, Offset after home is in dir opp. homing,
+// Homing Direction is CW (-), Homing is done automatically (no manual homing)
+#define DFLT_APP_CFG_REG	(0x00080800 | \
+							 cpmAppConfigFlds::IDLE_MODE)  
+
+// TrackGains=1, MtrVelEst=2, AntiHunt on
+
+#define DFLT_TUNE_CFG_REG	(0x4A1 | \
+							 cpmTuneConfigReg::ANTIHUNT_STD)
+
+// This data is the list of end user and/or ship-out settings for nodes
+// of this type.
+static const factoryInitData initData[] =  { 
+//    Type, Parameter,					    VAL,			FW Version, fwOpt, hwPlat
+	{ NVR,	CPM_P_STOP_TYPE, 				STOP_TYPE_RAMP_AT_DECEL },
+	{ NVR,	CPM_P_HW_CONFIG_REG, 			DFLT_HW_CFG_REG,	FW_MILESTONE_ALL_VERS,		0, 1 },	//2-3"
+	{ NVR,	CPM_P_HW_CONFIG_REG, 			DFLT_HW_CFG_REG_AC,	FW_MILESTONE_ALL_VERS,		0, 2 },	//AC Green
+	{ NVR,	CPM_P_APP_CONFIG_REG, 			DFLT_APP_CFG_REG },
+	{ NV,	CPM_P_USER_DATA_NV0,			0 },
+	{ NV,	CPM_P_USER_DATA_NV1,			0 },
+	{ NV,	CPM_P_USER_DATA_NV2,			0 },
+	{ NV,	CPM_P_USER_DATA_NV3,			0 },
+
+	{ NVR,	CPM_P_JERK_LIM, 				ISC_RAS_3MS },
+	{ NVR,	CPM_P_HEAD_DISTANCE,			1000},
+	{ NVR,	CPM_P_TAIL_DISTANCE,			1000},
+	{ NVR,  CPM_P_MOVE_DWELL,				0 },
+	{ NVR,	CPM_P_DRV_STOP_QUALIFY_TC,		1000 },
+	{ NVR,	MN_P_WATCHDOG_TIME,				2000 },
+	{ NVR,	CPM_P_POSN_TRK_RANGE,			10 },
+	{ NVR,	CPM_P_VEL_TRK_RANGE,			3 },
+	{ NVR,	CPM_P_DRV_MV_DN_TC,    			10 },					// ms
+	// Input filters
+	{ NVR,	CPM_P_INA_TC,					20 },
+	{ NVR,	CPM_P_INB_TC,					20 },
+	// Sensorless defaults
+	{ NVR,	104,							20 },					//COMM_CHK_ANGLE_LIM
+	{ NVR,	105,							2000 },					//SENSORLESS_RAMPUP_TIME (ms)
+	{ NVR,	106,							1000 },					//SENSORLESS_SWEEP_TIME (ms)
+	{ NVR,	107,							500 },					//SENSORLESS_SETTLE_TIME (ms)
+	{ NVR,	113,							15 },					//SENSORLESS_MOTION_DEG (elec deg)
+	{ NVR,	114,							5 },					//SENSORLESS_MIN_MOTION_DEG (ele Deg)
+	{ NVR,	115,							100 },					//SENSORLESS_VERIFY_RAMP (ms)
+	{ NVR,	111,							300 },					//SENSORLESS_VERIFY_TIME (ms)
+	{ NVR,	CPM_P_PWRUP_HOLDOFF_TIME,		500 },					// ms
+	// Drive Parameters
+	{ NVR,	CPM_P_DRV_RMS_LIM,				3 },					// A
+	{ NVR,	CPM_P_POSN_TRK_ERR_LIM, 		1000 },
+	{ NVR,	CPM_P_DRV_RMS_INIT,				80 },					// % of RMS Max
+	// Tuning Parameters
+	{ NVR,	CPM_P_DRV_KIP,					0 },
+	{ NVR,	CPM_P_DRV_KII,					0 },
+	{ NVR,	CPM_P_DRV_KIP_ADJ,				0 },
+	{ NVR,	CPM_P_DRV_KII_ADJ,				0 },
+	{ NVRV,	CPM_P_DRV_STEP_DENS,			800,	FW_MILESTONE_ALL_VERS, 0, 1 },
+	{ NVRV,	CPM_P_DRV_STEP_DENS,			4000,	FW_MILESTONE_MIN_VOLT, 0, 2 },
+	{ NVR,	CPM_P_DRV_KR,					1 },
+	{ NVR,	CPM_P_DRV_TUNE_CONFIG_REG, 		DFLT_TUNE_CFG_REG },		
+	{ NVR,	CPM_P_DRV_KV,					0 },
+	{ NVR,	CPM_P_DRV_KP,      				0 },
+	{ NVR,	CPM_P_DRV_KI,      				0 },
+	{ NVR,	CPM_P_DRV_KFV,     				0 },
+	{ NVR,	CPM_P_DRV_KFA,     				0 },
+	{ NVR,	CPM_P_DRV_KFJ,     				0 },
+	{ NVR,	CPM_P_DRV_KNV,     				0 },
+	{ NVR,	CPM_P_DRV_TRQ_BIAS,				0 },
+	{ NVR,	CPM_P_DRV_FUZZY_APERTURE, 		1 },
+	{ NVR,	CPM_P_DRV_FUZZY_HYST, 			1 },
+	{ NVR,	CPM_P_AH_HOLDOFF,				50 },					// ms
+	{ NVR,	CPM_P_DRV_AH_FILT_TC,			50 },					// ms
+	{ NVR,  CPM_P_DRV_KZERO,				0 },
+	{ NVR,  CPM_P_DRV_IZERO,				0 },
+	{ NVR,  CPM_P_DRV_TARGET_WIN,			3 },
+	{ NVR,  CPM_P_DRV_STAB_WIN,				0 },
+/* Inertia, Static Friction, Viscous Friction - not implemented yet
+	// TO_DO: MTR_INERTIA,STATIC_FRICTION,VISC_FRICTION	(XML override?)
+	{ NVR,  CPM_P_MTR_INERTIA,				0 },
+	{ NVR,  CPM_P_MTR_STATIC_FRICTION,		0 },
+	{ NVR,  CPM_P_MTR_VISCOUS_FRICTION,		0 },
+	// TO_REVIEW: VEL/ACC/DEC_LIM_MAX
+*/
+	{ NVR,  CPM_P_DRV_KP_FACTOR,			1 },
+	{ NVR,  CPM_P_DRV_KPZ_FACTOR,			1 },
+	{ NVR,  CPM_P_DRV_KI_FACTOR,			1 },
+	{ NVR,  CPM_P_DRV_FINE_TUNE,			19 },
+
+	{ NVR,	CPM_P_DRV_POS_FLDBK_TRQ_TC,		200 },
+	{ NVR,	CPM_P_DRV_NEG_FLDBK_TRQ_TC,		200 },
+	{ NVR,	CPM_P_DRV_HARDSTOP_FLDBK_TRQ_TC, DFLT_HS_FLDBK_TC },
+	{ NVR,	CPM_P_DRV_HARDSTOP_ENTRY_TRQ,	80 },
+	{ NVR,	CPM_P_DRV_HARDSTOP_ENTRY_TC,	50 },					// ms
+
+	// Homing items (note out of order)
+	{ NVR,  CPM_P_APP_HOMING_OFFSET,		0 },
+	{ NVR,  CPM_P_APP_HOMING_DELAY,			0 },
+
+	{ RAM,	CPM_P_USER_OUT_REG,				0 },
+	{ NVR,	CPM_P_XPS_OUT_SRC_REG,			0 },
+	{ NVR,	CPM_P_XPS_IN_SRC_REG,			0 },
+	{ NVR,	CPM_P_XPS_USER_IN_REG,			0 },
+	{ NVR,	CPM_P_XPS_INVERT_INPUT,			0 },
+	{ NVR,	CPM_P_XPS_INVERT_OUTPUT,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_ENABLE-2,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_ENABLE-1,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_ENABLE,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_ENABLE+1,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_TRIGGER,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_NODE_STOP,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_RESET_TIMER,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_ATTN0,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_ATTN1,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_ATTN1+1,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_ATTN1+2,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_AT_HOME,			0 },
+	{ NVR,	CPM_P_XPS_FEAT_POS_TRQ_FLDBK,	0 },
+	{ NVR,	CPM_P_XPS_FEAT_NEG_TRQ_FLDBK,	0 },
+	{ NVR,	CPM_P_XPS_FEAT_IN_POS_LIM,		0 },
+	{ NVR,	CPM_P_XPS_FEAT_IN_NEG_LIM,		0 },
+
+	{ NVR,  CPM_P_DLY_TO_DISABLE,			200 },
+	{ NVR,	CPM_P_USER_SOFT_LIM_POSN_1,		0 },
+	{ NVR,  CPM_P_USER_SOFT_LIM_POSN_2,		0 },
+	{ NVR,  CPM_P_DRV_VRS_TRQ_FILT,			10,		FW_MILESTONE_AC_GREEN },
+	// 6th item is one greater than HW Platform version for HW specific items
+	// 2",3" Settings
+	{ NVR,	CPM_P_DRV_RMS_TC,				3,		FW_MILESTONE_ALL_VERS, 0, 1 }, // sec
+	{ NVR,  CPM_P_DRV_VRS_FULL_ON,			88,		FW_MILESTONE_AC_GREEN, 0, 1 },
+	{ NVR,  CPM_P_DRV_VRS_FULL_OFF,			86,		FW_MILESTONE_AC_GREEN, 0, 1 },
+	{ NVR,  CPM_P_DRV_RMS_SLOW_LIM,			3,		FW_MILESTONE_DUAL_RMS, 0, 1 },
+	{ NVR,  CPM_P_DRV_RMS_SLOW_TC,			5,		FW_MILESTONE_DUAL_RMS, 0, 1 },
+	{ NVR,  CPM_P_DRV_BUSV_ADJ_RATE,		-1,		FW_MILESTONE_VBUS_ADJ, 0, 1 },
+	{ NVR,	CPM_P_DRV_MIN_OPER_VOLTS,		0,		FW_MILESTONE_MIN_VOLT, 0, 1 },
+	{ NVR,  CPM_P_OVER_TEMP_TRIP_USER,		70,		FW_MILESTONE_USER_TEMP, 0, 1 },
+	{ NVR,  CPM_P_DRV_IB_TRIP_USER,			8,		FW_MILESTONE_INDEX_IB, 0, 1 },
+	// AC_GREEN Settings
+	{ NVR,	CPM_P_DRV_RMS_TC,				6,		FW_MILESTONE_ALL_VERS, 0, 2 }, // sec
+	{ NVR,  CPM_P_DRV_VRS_FULL_ON,			417,	FW_MILESTONE_AC_GREEN, 0, 2 },
+	{ NVR,  CPM_P_DRV_VRS_FULL_OFF,			400,	FW_MILESTONE_AC_GREEN, 0, 2 },
+	{ NVR,  CPM_P_DRV_RMS_SLOW_LIM,			15,		FW_MILESTONE_DUAL_RMS, 0, 2 },
+	{ NVR,  CPM_P_DRV_RMS_SLOW_TC,			3,		FW_MILESTONE_DUAL_RMS, 0, 2 },
+	{ NVR,  CPM_P_DRV_BUSV_ADJ_RATE,		5,		FW_MILESTONE_VBUS_ADJ, 0, 2 },
+	{ NVR,	CPM_P_DRV_MIN_OPER_VOLTS,		0,		FW_MILESTONE_MIN_VOLT, 0, 2 },
+	{ NVR,  CPM_P_PWR_AC_LOSS_TC,			150,	FW_MILESTONE_MIN_VOLT, 0, 2 },
+	{ NVR,  CPM_P_PWR_AC_WIRING_ERROR_TC,	50,		FW_MILESTONE_MIN_VOLT, 0, 2 },
+	{ NVR,  CPM_P_OVER_TEMP_TRIP_USER,		70,		FW_MILESTONE_USER_TEMP, 0, 2 },
+	{ NVR,  CPM_P_DRV_IB_TRIP_USER,			12.5,	FW_MILESTONE_INDEX_IB, 0, 2 },
+
+	{ NVR,  CPM_P_GP_TIMER,					0 },
+		//    Type, Parameter,					    VAL,	FW Version,        fwOpt, hwPlat
+};
+
+// Default settings
+#define DFLT_VEL_LIM		1000					// RPM
+#define DFLT_ACC_LIM		5000					// RPM/s
+#define DFLT_STOP_ACC_LIM	(DFLT_ACC_LIM*80.)		// 400,000 RPM/s (~10ms stop from max speed of 4000RPM)
+static const factoryInitData initSpdAccelData[] =  { 
+//    Type, Parameter,					    VAL,			FW Version
+	{ NVR,	58,				 				15 },						//JOG_VEL_LIM (RPM)
+	{ NVR,	59,				 				DFLT_ACC_LIM },				//JOG_ACC_LIM (RPM/s)
+	{ NVR,	CPM_P_VEL_LIM, 					DFLT_VEL_LIM  },			// RPM
+	{ NVR,	CPM_P_ACC_LIM, 					DFLT_ACC_LIM },				// RPM/s
+	{ NVR,	CPM_P_DEC_LIM, 					DFLT_ACC_LIM },				// RPM/s
+	{ NVR,	CPM_P_STOP_ACC_LIM, 			DFLT_STOP_ACC_LIM },		// RPM/s
+	{ NVR,	CPM_P_HEADTAIL_VEL,				200 },						// RPM
+	{ NVR,	CPM_P_DRV_STOP_QUALIFY_VEL,		0 },						// RPM
+	{ NVR,	CPM_P_DRV_HARDSTOP_ENTRY_SPD,	17.8 },						// RPM
+	{ NVR,	CPM_P_APP_HOMING_VEL,			DFLT_VEL_LIM/25 },			// RPM
+	{ NVR,  CPM_P_APP_HOMING_ACCEL,			DFLT_ACC_LIM/10},			// RPM/s
+
+	{ NVR,  CPM_P_AT_POSN_LOC,				0 },						// Revs
+	{ NVR,  CPM_P_A_START,					0 },						// Revs
+	{ NVR,  CPM_P_B_END,					0 },						// Revs
+    { NVR,  98,					            0 },
+};
+
+#define DFLT_FULL_TRQ		1.						// Current scale maximum
+#define DFLT_HS_TRIP		0.80					// Hardstop Trip Point (% of IMax)
+#define DFLT_FLD_BACK		0.05					// Foldback levels (% of IMax)
+#define DFLT_SENSORLESS_TRQ 0.05					// Sensorless startup trq (% of IMax)
+
+static const factoryInitData initTrqData[] =  { 
+	{ NVR,	267,							DFLT_SENSORLESS_TRQ },	// % of IMax
+
+	// Foldback settings
+	{ NVR,	CPM_P_DRV_TRQ_LIM,				DFLT_FULL_TRQ },
+ 	{ NVR,	CPM_P_DRV_POS_FLDBK_TRQ, 		DFLT_FLD_BACK },
+	{ NVR,	CPM_P_DRV_NEG_FLDBK_TRQ, 		DFLT_FLD_BACK },
+	{ NVR,	CPM_P_DRV_HARDSTOP_FLDBK_TRQ,	DFLT_FULL_TRQ },
+	{ NVR,  CPM_P_DRV_HARDSTOP_TRQ_LIM,		0.2 },
+};
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmClassDelete
+//
+//	DESCRIPTION:
+//		Delete any memory this node allocated.
+//
+//	\return MN_OK if successful
+//
+//	SYNOPSIS:
+void cpmClassDelete(multiaddr theMultiAddr) {
+	register byNodeDB *pNodeDB;
+	netaddr cNum = NET_NUM(theMultiAddr);
+//#define DEL_PRN
+#ifdef DEL_PRN
+	_RPT2(_CRT_WARN, "%.1f cpmClassDelete: node %d...\n", 
+				infcCoreTime(), theMultiAddr); 
+#endif
+	pNodeDB = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	// Delete if no one else has
+	if (pNodeDB->paramBankList) {
+		for (unsigned iBank = 0; iBank < pNodeDB->bankCount; iBank++){
+			free((void *)(pNodeDB->paramBankList[iBank]).valueDB);
+			(pNodeDB->paramBankList[iBank]).valueDB = NULL;
+		}
+		pNodeDB->bankCount = 0;
+		pNodeDB->theID.devCode = NODEID_UNK;
+		free((void *)pNodeDB->paramBankList);
+		pNodeDB->paramBankList = NULL;
+		if (pNodeDB->pNodeSpecific) {
+			delete (iscState *)pNodeDB->pNodeSpecific;
+			pNodeDB->pNodeSpecific = NULL;
+		}
+#ifdef DEL_PRN
+		_RPT2(_CRT_WARN, "%.1f cpmClassDelete: %d...done\n", 
+			infcCoreTime(), theMultiAddr); 
+#endif
+	}
+#ifdef DEL_PRN
+	#ifdef _DEBUG
+	else {
+		_RPT2(_CRT_WARN, "%.1f cpmClassDelete: %d already gone\n", 
+			infcCoreTime(), theMultiAddr); 
+	}
+	#endif
+#endif
+}
+//      																	  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmClassSetup
+//
+//	DESCRIPTION:
+//		Setup the parameter manager and node database for this node.
+//
+//	\return  MN_OK if successful
+//
+//	SYNOPSIS:
+cnErrCode cpmClassSetup(
+	multiaddr theMultiAddr)
+{
+	cnErrCode errRet;
+	packetbuf resp, fwVers, dummy;
+	register byNodeDB *pNodeDB;
+	netaddr cNum = NET_NUM(theMultiAddr);
+//	_RPT3(_CRT_WARN, "%.1f cpmClassSetup net=%d, node=%d\n", 
+//		infcCoreTime(), cNum, theMultiAddr);
+	
+	// Stop using old memory
+	cpmClassDelete(theMultiAddr);
+	// Make sure this is a Integrated Servo Controller
+	errRet = netGetParameter(theMultiAddr, MN_P_NODEID, &resp);
+	if (errRet == MN_OK)  {
+		errRet = netGetParameter(theMultiAddr, CPM_P_FW_VERS, &fwVers);
+		if (errRet == MN_OK)  {
+			// Shorthand to access the device ID field
+			#define DEVID ((devID_t *)(&resp.Byte.Buffer[0]))
+			#define FWVER ((versID_t *)(&fwVers.Byte.Buffer[0]))
+			// Fill in the database from the node if this is a ClearPath-SC
+			if (DEVID->fld.devType == NODEID_CS)	 {		
+				// Initialize the register/shortcut
+				pNodeDB = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+				// Wire in our destructor
+				pNodeDB->delFunc = cpmClassDelete;
+				// Initialize the per node database
+				pNodeDB->bankCount = 3;
+				// Update the ID area
+				pNodeDB->theID.fld.devType = DEVID->fld.devType;
+				pNodeDB->theID.fld.devModel = DEVID->fld.devModel;
+				// Create and initialize the parameter banks
+				pNodeDB->paramBankList = (paramBank *)calloc(pNodeDB->bankCount,
+															 sizeof(paramBank));
+				// Bank 0 information
+				(pNodeDB->paramBankList[0]).nParams = PARAM_BASE_COUNT;
+				(pNodeDB->paramBankList[0]).fixedInfoDB = &cpmInfoDB[0];
+				// Create the value storage area together
+				(pNodeDB->paramBankList[0]).valueDB 
+					= (paramValue *)calloc(PARAM_BASE_COUNT, sizeof(paramValue));
+				// Bank 1 information
+				(pNodeDB->paramBankList[1]).nParams = PARAM_DRV_COUNT;
+				(pNodeDB->paramBankList[1]).fixedInfoDB = &cpmDrvInfoDB[0];
+				// Create the value storage area together
+				(pNodeDB->paramBankList[1]).valueDB 
+					= (paramValue *)calloc(PARAM_DRV_COUNT, sizeof(paramValue));
+				// Bank 2 information
+				(pNodeDB->paramBankList[2]).nParams = PARAM_APP_COUNT;
+				(pNodeDB->paramBankList[2]).fixedInfoDB = &cpmAppInfoDB[0];
+				// Create the value storage area together
+				(pNodeDB->paramBankList[2]).valueDB 
+					= (paramValue *)calloc(PARAM_APP_COUNT, sizeof(paramValue));
+
+				// Create by node information
+				pNodeDB->pNodeSpecific = new iscState;
+
+				// Initialize the class specific items
+				pNodeDB->pClassInfo = &cpmClassDB; 
+
+				// Reset all node diagnostics by reading them (clear on read)
+				netGetParameter(theMultiAddr,CPM_P_NETERR_APP_CHKSUM,&dummy);
+				netGetParameter(theMultiAddr,CPM_P_NETERR_APP_FRAG,&dummy);
+				netGetParameter(theMultiAddr,CPM_P_NETERR_APP_STRAY,&dummy);
+				netGetParameter(theMultiAddr,CPM_P_NETERR_APP_OVERRUN,&dummy);
+
+				errRet = coreUpdateParamInfo(theMultiAddr);
+			}
+			else
+				errRet = MN_ERR_WRONG_NODE_TYPE;
+		}
+	}
+//	_RPT1(_CRT_WARN, "%.1f cpmClassSetup done\n", infcCoreTime()); 
+	return(errRet);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//******************************************************************************
+//	!NAME!
+//		cpmInitializeEx
+//
+//	DESCRIPTION:
+//		This function will configure the network and download the parameters 
+//		into a local copy of the parameters for the addressed node.
+//
+//	\return
+//		MN_OK if successful
+//
+//	SYNOPSIS:
+cnErrCode cpmInitializeEx(
+	multiaddr theMultiAddr,						// Ptr to return array
+	nodebool warmInitialize)
+{
+	return(coreInitializeEx(theMultiAddr, warmInitialize, cpmClassSetup));
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		cpmInitialize
+ *
+ *	DESCRIPTION:
+ *		This function will configure the network and download the parameters 
+ *		into a local copy of the parameters for the addressed node.
+ *
+ *	\return
+ *		MN_OK if successful
+ *
+ *	SYNOPSIS: 															     */
+cnErrCode cpmInitialize(
+	multiaddr theMultiAddr)						// Ptr to return array
+{
+	return(cpmInitializeEx(theMultiAddr, FALSE));
+}
+//																			  *
+/*****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		cpmParamChangeFunc
+ *
+ *	DESCRIPTION:
+ *		Set the parameter change callback function.
+ *
+ *	\return
+ *		Old handler
+ *
+ *	SYNOPSIS: 															    */
+MN_EXPORT paramChangeFunc MN_DECL cpmParamChangeFunc(
+	  	paramChangeFunc newFunc)		// Node number of changed
+{
+	paramChangeFunc oldFunc = cpmClassDB.paramChngFunc;
+	cpmClassDB.paramChngFunc = newFunc;
+	return(oldFunc);
+}
+//																			  *
+//==============================================================================
+/// \endcond
+// END OF PARAMETER ORIENTED INTERNAL_DOC
+//==============================================================================
+
+
+//==============================================================================
+// UNDOCUMENTED API FUNCTIONS GO BELOW THIS LINE
+/// \cond INTERNAL_DOC
+//==============================================================================
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetMotorFileName
+//
+//	DESCRIPTION:
+/**
+	Get the configuration file name for this node. This information is normally
+	maintained by the configuration file loading API.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pMotorFileNameStr Ptr to result area.
+	\param[in] maxBufSize Maximum size of the \a pMotorFileNameStr buffer.
+
+	\return  MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetMotorFileName(
+		multiaddr theMultiAddr,
+		char *pMotorFileNameStr,
+		Uint16 maxBufSize)
+{
+	packetbuf nameBuf, cmdBuf;
+	cnErrCode theErr;
+	unsigned i;
+	
+	cmdBuf.Byte.Buffer[CMD_LOC] = ISC_CMD_MOTOR_FILE;
+	for(i=CMD_LOC+1; i<(MN_FILENAME_SIZE+CMD_LOC+1); i++)
+		cmdBuf.Byte.Buffer[i] = 0;
+	cmdBuf.Fld.Addr = theMultiAddr;
+	cmdBuf.Fld.PktLen = 1;
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &cmdBuf, &nameBuf);
+	
+	if (theErr == MN_OK) {
+		// Limit return size to buffer size
+		i = (nameBuf.Fld.PktLen < maxBufSize) 
+			? nameBuf.Fld.PktLen : maxBufSize;
+		strncpy((char *)&pMotorFileNameStr[0], 
+				(const char *)&nameBuf.Byte.Buffer[CMD_LOC], i);
+		pMotorFileNameStr[i] = 0;				// Insure term'd
+	}
+	else {
+		pMotorFileNameStr[0] = 0;
+	}
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetMotorFileName
+//
+//	DESCRIPTION:
+/**
+	Set the configuration file name for this node. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pNewName Ptr null terminated ANSI string up to 25 characters in
+				length. 
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetMotorFileName(
+		multiaddr theMultiAddr,
+		const char *pNewName)
+{
+	packetbuf nameBuf, respBuf;
+	size_t i;
+	size_t nSize = strlen(pNewName);
+	cnErrCode theErr = MN_OK;
+	
+	if (pNewName == NULL) 
+		return(MN_ERR_BADARG);
+	
+	if (nSize > MN_FILENAME_SIZE) nSize = MN_FILENAME_SIZE;
+
+	// Clear out buffer with 0 padding
+	for(i=nSize; i<MN_FILENAME_SIZE; i++)
+		nameBuf.Byte.Buffer[i+CMD_LOC+1] = 0;
+
+	nameBuf.Byte.Buffer[CMD_LOC] = ISC_CMD_MOTOR_FILE;
+	// Cmd Byte + Motor File Octets
+	nameBuf.Fld.PktLen = 1+MN_FILENAME_SIZE;
+	nameBuf.Fld.Addr = NODE_ADDR(theMultiAddr);
+	strncpy((char *)&nameBuf.Byte.Buffer[CMD_LOC+1], 
+			(char *)&pNewName[0], nSize);
+	// Ensure that the buffer is null-terminated
+	nameBuf.Byte.Buffer[MN_NET_PACKET_MAX-1] = 0;
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &nameBuf, &respBuf); 
+
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetUserID
+//
+//	DESCRIPTION:
+/**
+	Get the User ID for this node. This is an identifier the application
+	may use for "plug-and-play" or diagnostic purpose. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pUserIdStr Return buffer area
+	\param[in] maxBufSize Size of \p pUserIdStr area
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetUserID(
+		multiaddr theMultiAddr,
+		char *pUserIdStr,
+		Uint16 maxBufSize)
+{
+	return netGetUserID(theMultiAddr, pUserIdStr, maxBufSize);
+}
+//																 			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetUserID
+//
+//	DESCRIPTION:
+/**
+	Set the User ID for this node. Any ANSI character string maybe used
+	up to 13 characters.
+	
+	This maybe used as an identifier for application "plug-and-play" or
+	diagnostic purposes. If set to NULL, the APS application will apply
+	a generic name "Axis \<addr\>" on its display.  A typical name could
+	be "X Axis".
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewName Ptr to NULL terminated ANSI string.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetUserID(
+		multiaddr theMultiAddr,
+		const char *pNewName)
+{
+	return netSetUserID(theMultiAddr, pNewName);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetStimulus
+//
+//	DESCRIPTION:
+/**
+	Get the current stimulus generator settings.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pState Ptr to the result area updated with current state 
+			information.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pState)
+{
+	packetbuf theCmd, theResp;
+	paramValue sampleTime;
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+	iscStimCmdPkt *pStimData = ((iscStimCmdPkt *)&theResp.Byte.Buffer[RESP_LOC]);
+
+	cNum = coreController(theMultiAddr);
+	
+	// Get sample rate conversion factor	
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD, NULL, &sampleTime);
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(MN_ERR_RESP_FMT);
+	sampleTime.value *= 0.001;			// Convert microseconds to milliseconds
+
+	// Fill in the command head parts
+	theCmd.Fld.Addr = theMultiAddr;
+	theCmd.Fld.PktLen = 1;
+	theCmd.Byte.Buffer[CMD_LOC] = SC_CMD_GET_SET_STIMULUS;
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	// DEBUG PRINT
+	//ISC_DUMP_PKT(theMultiAddr, "Get Stim", &theResp);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// Properly formatted response?
+	if (theResp.Fld.PktLen != CP_STIM_RESP_STATUS_OCTETS) 
+		return(MN_ERR_RESP_FMT);
+	// Crack the return buffer into standard units
+	pState->mode = (stimModes)pStimData->Mode;
+	pState->period = (nodelong)(0.5+(pStimData->Period * sampleTime.value));
+	pState->bits = pStimData->Status;
+	switch (pState->mode) {
+		case STIM_OFF:
+			pState->amplitude = 0;				
+			break;
+		case STIM_VEL:				// Velocity	(ticks/ms)
+			pState->amplitude = (CP_MON_MAX_VEL * pStimData->Amplitude 
+							   / sampleTime.value)
+		             		   / 32767;
+			break;
+		case STIM_CAL:				// Calibrate/test (100% FS)
+		case STIM_TRQ:				// Torque
+			pState->amplitude = pStimData->Amplitude / 327.67;
+			break;
+		case STIM_POSN:				// Position	(ticks)
+			pState->amplitude = pStimData->Amplitude;
+			break;
+		case STIM_MOVE_ONCE:
+		case STIM_MOVE_RECP:
+		case STIM_MOVE_REPEAT:
+			pState->amplitude = pStimData->Amplitude;
+			pState->slew = pStimData->Slew;
+			// Convert dwell back to milliseconds
+			if (sampleTime.value != 0) 
+				pState->dwell = static_cast<nodelong>(pStimData->Dwell 
+													 / sampleTime.value);
+			else
+				pState->dwell = 0;
+			break;
+		default:
+			return(MN_ERR_BADARG);
+	}
+	//_RPT3(_CRT_WARN, "iscGetStimulus: mode %d ampl=%f per=%f\n", pState->mode, 
+	//									pState->amplitude, pState->period);
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetStimulus
+//
+//	DESCRIPTION:
+/**
+	Change the stimulus generator setting.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewState Ptr to the new state desired.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pNewState)
+{
+	packetbuf theCmd, theResp;
+	paramValue sampleTime;
+	nodelong lVal, tVal;
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+
+	//_RPT3(_CRT_WARN, "cpmSetStimulus: mode %d ampl=%f per=%f\n", pNewState->mode, pNewState->amplitude, pNewState->period);
+	// Get sample rate conversion factor	
+	theErr = netGetParameterInfo(theMultiAddr, CPM_P_SAMPLE_PERIOD,	
+								NULL, &sampleTime);
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(MN_ERR_BADARG);
+	sampleTime.value *= 0.001;			// Convert microseconds to milliseconds
+
+	// Fill in the command head parts
+	theCmd.Fld.Addr = theMultiAddr;
+	switch(pNewState->mode){
+		case STIM_MOVE_ONCE:
+		case STIM_MOVE_RECP:
+		case STIM_MOVE_REPEAT:
+			theCmd.Fld.PktLen = CP_STIM_CMD_PKT_PROF_SIZE;
+			break;
+		default:
+			theCmd.Fld.PktLen = CP_STIM_CMD_PKT_SIZE;
+			break;
+	}
+	theCmd.Byte.Buffer[CMD_LOC] = SC_CMD_GET_SET_STIMULUS;
+	// Shortcut to the command buffer
+	iscStimCmdPkt *pSimCmd = ((iscStimCmdPkt *)&theCmd.Byte.Buffer[CMD_LOC+1]);
+
+	// Set the mode
+	pSimCmd->Mode = (nodechar)pNewState->mode;
+	// Saturate @ largest value
+	// Set the 0.5*period(ms) in sample-time(us) counts
+	lVal = (nodelong)(0.5+(pNewState->period/sampleTime.value));
+	// Saturate @ largest value
+	if (lVal > 32767) lVal = 32767;
+	pSimCmd->Period = (nodeshort)(lVal);
+	// Zero out potentially unused fields
+	pSimCmd->Dwell = 0;
+	pSimCmd->Status = 0;
+	pSimCmd->Slew = 0;
+
+	// Figure out the scaling for the amplitude based on the mode
+	switch(pNewState->mode)  {
+		case STIM_OFF:
+			lVal = 0;				
+			break;
+		case STIM_VEL:				// Velocity	(ticks/ms)
+			lVal = (nodelong)(32767. * pNewState->amplitude * sampleTime.value 
+			             / CP_MON_MAX_VEL + ((pNewState->amplitude<0)?(-.5):(.5)));
+			if (lVal > 32767) lVal = 32767;
+			break;
+		case STIM_CAL:				// Calibrate/test (100% FS)
+		case STIM_TRQ:				// Torque
+			lVal = (nodelong)(327.67*pNewState->amplitude);
+			if (lVal > 32767) lVal = 32767;
+			break;
+		case STIM_POSN:				// Position	(ticks)
+			if (pNewState->amplitude < 32767)
+				lVal = (nodelong)pNewState->amplitude;
+			else
+				lVal = 32767;
+			break;
+		case STIM_MOVE_ONCE:
+		case STIM_MOVE_RECP:
+		case STIM_MOVE_REPEAT:
+			pSimCmd->Period = static_cast<nodeshort>(pNewState->period);
+			lVal = (nodelong)pNewState->amplitude;
+			// Saturate @ largest value
+			if (pNewState->amplitude > LONG_MAX) lVal = (nodelong)LONG_MAX;
+			pSimCmd->Slew = (nodeshort)pNewState->slew;
+			// Convert request milliseconds to sample-counts
+			tVal = (nodelong)(0.5+(pNewState->dwell/sampleTime.value));
+			if (tVal > INT_MAX) tVal = INT_MAX;
+			pSimCmd->Dwell = (nodeshort)tVal;
+			break;
+		default:
+			return(MN_ERR_BADARG);
+	}
+	
+	pSimCmd->Amplitude = lVal;
+
+	// Make it so, wait for return
+	//ISC_DUMP_PKT(theMultiAddr, "Set Stim", &theCmd);
+
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	if (theErr == MN_OK && theResp.Fld.PktLen != 0)
+		return(MN_ERR_RESP_FMT);
+	// Test we get back our settings 
+	//{
+	//	 iscStimState x;
+	//	 theErr = cpmGetStimulus(theMultiAddr, &x); 
+	//}
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmForkMoveVelEx
+//
+//	DESCRIPTION:
+/**
+	Sends a move that ramps up or down in speed to Velocity (using the
+	previously set limits for acceleration and jerk [RAS]).
+
+	Program execution does not suspend.  Once Velocity is achieved, the
+	move stays at Velocity until explicitly changed. Velocity is specified
+	as steps/second.
+
+	\return	cnErrCode; MN_OK if successful
+**/
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmForkMoveVelEx(
+			multiaddr theMultiAddr,			// The node
+			double velTargetStepPerSec,		// Target velocity (steps/sec)
+			nodelong positionTarget,			// Position Target [optional]
+			mgVelStyle moveType)			// Enhanced style selection
+{
+	nodelong bufsLeft;
+	return cpmForkVelMove(theMultiAddr, velTargetStepPerSec, false, &bufsLeft);
+}
+//																			  *
+//*****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetMonitor
+//
+//	DESCRIPTION:
+/**
+	Get the monitor state for the selected node. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] channel Targets which monitor port channel. Set this to zero.
+	\param[out] pState Ptr to result area.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetMonitor(
+			multiaddr theMultiAddr,	// Target node addr
+			nodeushort channel,		// Target monitor port if supported
+			iscMonState *pState)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+	appNodeParam param;
+	netaddr cNum;
+
+	// Pointer to data overlay in packet
+	iscMonNodeState *MON_AREA_GET 
+		= ((iscMonNodeState *)&theResp.Byte.Buffer[RESP_LOC]);
+
+	cNum = coreController(theMultiAddr);
+
+	// We only support one channel
+	if (channel != 0)
+		return(MN_ERR_BADARG);
+
+	theCmd.Fld.Addr = theMultiAddr;
+	theCmd.Fld.PktLen = 1;
+	theCmd.Byte.Buffer[CMD_LOC] = SC_CMD_GET_SET_MONITOR;
+	// Get the raw data
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	//ISC_DUMP_PKT(theMultiAddr, "Get Mon", &theResp);
+	if (theErr!=MN_OK)
+		return(theErr);
+	// Properly formatted response?
+	if (theResp.Fld.PktLen < 9 || theResp.Fld.PktLen > 10) 
+		return(MN_ERR_RESP_FMT);
+	// Fill in the return buffer
+	if (pState)  {
+		// Convert buffer to VB friendly structure
+		pState->var = (iscMonVars)MON_AREA_GET->var;
+		pState->tuneSync = (iscTuneSyncs)MON_AREA_GET->tuneSync;
+
+		// Convert gain number to full scale equivalent
+		pState->gain = convertMonGain(TRUE, theMultiAddr, 
+											   pState->var, 
+											   MON_AREA_GET->gain);
+
+		// Convert filter TC bits to milliseconds
+		param.bits = 0;					// Not used by converter anyways
+		pState->filterTC = convertFilt1TCMilliseconds(TRUE, theMultiAddr, param, 
+									MON_AREA_GET->filter,
+									&SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)]);
+
+		// Copy tune syncs
+	}
+	return(theErr);	
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetMonitor
+//
+//	DESCRIPTION:
+/**
+	Set the monitor state for the selected node. This function will
+	also update the parameter values which mirror the individual states.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] channel Targets which monitor port channel. Set this to zero.
+	\param[out] pNewState Ptr to desired new state.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetMonitor(
+			multiaddr theMultiAddr,	// Target node addr
+			nodeushort channel,		// Target monitor port if supported
+			iscMonState *pNewState)
+{
+
+	cnErrCode theErr = MN_OK;
+	packetbuf theCmd, theResp;
+	nodelong paramLng;
+	appNodeParam param;
+	netaddr cNum;
+
+	// Shortcut to the command buffer
+	iscMonNodeState *MON_AREA_SET 
+		= ((iscMonNodeState *)&theCmd.Byte.Buffer[CMD_LOC+1]);
+
+	// We only support one channel
+	if (channel != 0) 
+		return(MN_ERR_BADARG);
+
+	// Get controller context
+	cNum = coreController(theMultiAddr);
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+
+	// Fill in the command head parts
+	theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);
+	theCmd.Fld.PktLen = 10;
+	theCmd.Byte.Buffer[CMD_LOC] = SC_CMD_GET_SET_MONITOR;
+
+	// Set the variable member
+	MON_AREA_SET->var = (nodeshort)pNewState->var;
+	
+	// Convert the full scale value to a gain number
+	paramLng = (nodelong)convertMonGain(FALSE, theMultiAddr, 
+						  (iscMonVars)(pNewState->var & ~(MON_SAVE_NV_MASK)), 
+						  pNewState->gain);
+	MON_AREA_SET->gain = paramLng;
+
+	// Convert the filter constant to the internal representation
+	param.bits = 0;					// This is not used by the converter
+	paramLng = (nodelong)convertFilt1TCMilliseconds(FALSE, theMultiAddr, param, 
+						  pNewState->filterTC, 
+						  &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)]);
+	MON_AREA_SET->filter = (nodeshort)paramLng;
+
+	// tuneSync
+	MON_AREA_SET->tuneSync = (nodeshort)pNewState->tuneSync;
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	//ISC_DUMP_PKT(theMultiAddr, "Set Mon", &theCmd);
+	if (theErr == MN_OK && theResp.Fld.PktLen != 0)
+		return(MN_ERR_RESP_FMT);
+	// Test that we get our setting
+	//iscMonState x;
+	//theErr = iscGetMonitor(theMultiAddr, 0, &x);
+
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+#
+
+
+
+//==============================================================================
+// END OF UNDOCUMENTED API FUNCTIONS TO THIS LINE
+/// \endcond
+//==============================================================================
+
+//==============================================================================
+// DOCUMENTED API FUNCTIONS GO BELOW THIS LINE
+//==============================================================================
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetParameter
+//
+//  DESCRIPTION:
+/**
+	Get parameter value with no extra information.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The ClearPath-SC parameter code
+	\param[out] pParamVal Ptr to result
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetParameter(
+			multiaddr theMultiAddr,		// Node address
+			cpmParams theParam,			// Parameter index
+			double *pParamVal)			// Ptr to value area
+{
+	paramValue pVal;
+	cnErrCode theErr;
+
+	theErr = cpmGetParameterEx(theMultiAddr, theParam, &pVal, NULL);
+//	if (theParam == (CPM_P_DRV_I_MAX)) {
+//		_RPT3(_CRT_WARN, "ding p#%d(%d)=>%f\n", theParam, theMultiAddr, pVal.value );
+//	}
+//	else {
+//		_RPT2(_CRT_WARN, "cpm param %d=%f\n", theParam, pVal.value);
+//	}
+	if (pParamVal != NULL) 
+		*pParamVal = pVal.value;
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetParameter
+//
+//  DESCRIPTION:
+/**
+	This function will update the local parameter value for the selected
+	node and then change the value at the node if possible. If the
+	parameter is inaccessible the appropriate error is returned.
+		
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The ClearPath-SC m parameter code
+	\param[out] paramVal New value to set at node
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetParameter(
+			multiaddr theMultiAddr,		// Node address
+			cpmParams theParam,			// Parameter index
+			double paramVal)			// New value
+{
+	cnErrCode theErr = MN_OK;
+	theErr = netSetParameterInfo(theMultiAddr,
+								  theParam,
+								  paramVal, FALSE);
+	#ifdef _DEBUG
+		if(theErr != MN_OK)
+			_RPT4(_CRT_WARN,"netSetParameterInfo(%d, %d, %f) failed, err=0x%x", 
+			theMultiAddr, theParam, paramVal, theErr);
+	#endif
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetParameterEx
+//
+//  DESCRIPTION:
+/**
+	This function will retreive the local parameter value for the
+	selected node and return its value and information pertaining to it.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The cpsc parameter code
+	\param[out] pTheValue Ptr to the parameter value / raw bits.
+	\param[out] pTheInfo Ptr to optional information if non-NULL
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetParameterEx(
+			multiaddr theMultiAddr, 		// Node address
+			cpmParams theParam,			// Parameter index
+			paramValue *pTheValue,		// Ptr to returning value area
+			paramInfo *pTheInfo) 		// Ptr to returning optional information
+{
+
+	cnErrCode theErr=MN_OK;
+	theErr = netGetParameterInfo(theMultiAddr,
+								  theParam, 
+								  pTheInfo, 
+								  pTheValue);
+	return(theErr);
+}
+
+//																               *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetParameterEx
+//
+//  DESCRIPTION:
+/**
+	Set the parameter using the bytes described in the \a paramVal
+	buffer.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The cpsc parameter code
+	\param[out] pNewValue Ptr to bit-oriented packet buffer. The buffer size
+				will determine the amount written to the node.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetParameterEx(
+			multiaddr theMultiAddr,		// Node address
+			cpmParams theParam,			// Parameter index
+			packetbuf *pNewValue)		// New value
+{
+	cnErrCode theErr = MN_OK;
+	// Set the raw value at the node
+	theErr = netSetParameterEx
+		(theMultiAddr, theParam, pNewValue);
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetHwConfigReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Hardware Configuration Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pHwConfigReg Ptr to the result.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmHwConfigReg *pHwConfigReg)	// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_HW_CONFIG_REG, 
+							&paramVal, NULL);
+	*pHwConfigReg = *((cpmHwConfigReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetHwConfigReg
+//		As of 01/11/10, this is a 32 bit register
+//
+//	DESCRIPTION:
+/**
+	Set the current state of the Hardware Configuration Register. This register
+	controls many the hardware related options and features.  For example 
+	the IEX control is setup here.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] hwConfigReg New state.
+
+	\return	MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmHwConfigReg hwConfigReg)		// New setting
+{
+	// Update the double value
+	return(cpmSetParameter(theMultiAddr, CPM_P_HW_CONFIG_REG, 
+			hwConfigReg.bits));
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetAppConfigReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Hardware Configuration Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAppConfigReg Ptr to the result.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAppConfigReg *pAppConfigReg)	// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_APP_CONFIG_REG, 
+							&paramVal, NULL);
+	*pAppConfigReg = *((cpmAppConfigReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetAppConfigReg
+//
+//	DESCRIPTION:
+/**
+	Set the current state of the Hardware Configuration Register. This register
+	controls many the hardware related options and features.  For example 
+	the IEX control is setup here.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] appConfigReg New state.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAppConfigReg appConfigReg)		// New setting
+{
+	// Update the double value
+	return(cpmSetParameter(theMultiAddr, CPM_P_APP_CONFIG_REG, 
+			appConfigReg.bits));
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetStatusAccumReg
+//
+//	DESCRIPTION:
+/**
+	Get and clear the current Status Accumulation Register value.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS: 
+MN_EXPORT cnErrCode MN_DECL cpmGetStatusAccumReg(
+			multiaddr theMultiAddr,		// Node address
+			cpmStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_STATUS_ACCUM_REG, 
+							   &paramVal, NULL);
+	// Use overlay master type
+	mnStatusReg *pmnStat = (mnStatusReg *)pStatus;
+	pmnStat->clear();
+	*pStatus = *((cpmStatusReg *)&(paramVal.raw.Byte.Buffer[0]));
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetAttnStatusRiseReg
+//
+//	DESCRIPTION:
+/**
+	Get and clear the current accumulation of rising status register states.
+
+	\note Any bits that are unmasked for Attention Generation always return
+	zero.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS: 
+MN_EXPORT cnErrCode MN_DECL cpmGetAttnStatusRiseReg(
+			multiaddr theMultiAddr,		// Node address
+			cpmStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_STATUS_RISE_REG, 
+							  &paramVal, NULL);
+	// Use overlay master type
+	mnStatusReg *pmnStat = (mnStatusReg *)pStatus;
+	pmnStat->clear();
+	*pStatus = *((cpmStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetStatusFallReg
+//
+//	DESCRIPTION:
+/**
+	Get and clear the current accumulation of the falling status register 
+	states.
+
+	\note Any bits that are unmasked for Attention Generation always return
+	zero.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return MN_OK if successful
+**/		
+//	SYNOPSIS: 
+MN_EXPORT cnErrCode MN_DECL cpmGetStatusFallReg(
+			multiaddr theMultiAddr,		// Node address
+			cpmStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_STATUS_FALL_REG, 
+							  &paramVal, NULL);
+	// Use overlay master type
+	mnStatusReg *pmnStat = (mnStatusReg *)pStatus;
+	pmnStat->clear();
+	*pStatus = *((cpmStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetStatusRTReg
+//
+//	DESCRIPTION:
+/**
+	Get a snapshot of the current status register states.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetStatusRTReg(
+			multiaddr theMultiAddr,		// Node address
+			cpmStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_STATUS_RT_REG, 
+							   &paramVal, NULL);
+	// Use overlay master type
+	mnStatusReg *pmnStat = (mnStatusReg *)pStatus;
+	pmnStat->clear();
+	*pStatus = *((cpmStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetAlertReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Alert Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAlertReg Ptr to result area.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetAlertReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAlertReg *pAlertReg)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_ALERT_REG, &paramVal, NULL);
+	*pAlertReg = *((cpmAlertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetWarningReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Warning Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pWarningReg Ptr to result area.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetWarningReg(
+			multiaddr theMultiAddr,			// Node address
+			cpmAlertReg *pWarningReg)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = cpmGetParameterEx(theMultiAddr, CPM_P_WARN_REG, &paramVal, NULL);
+	*pWarningReg = *((cpmAlertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmFactoryDefaults
+//
+//	DESCRIPTION:
+/**
+	Initialize the node to factory defaults. All tuning and features are
+	restored to factory ship out state.
+
+	\param[in] theMultiAddr The address code for this node.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmFactoryDefaults(
+	multiaddr theMultiAddr)			// Destination node
+{
+	return cpmFactoryDefaultsEx(theMultiAddr, false);
+}
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmFactoryDefaultsEx
+//
+//	DESCRIPTION:
+/**
+Initialize the node to factory defaults. All tuning and features are
+restored to factory ship out state.
+
+\param[in] theMultiAddr The address code for this node.
+\param[in] skipShutdownRisks Don't reset parameters which may cause false shutdowns
+
+\return MN_OK if successful
+**/
+MN_EXPORT cnErrCode MN_DECL cpmFactoryDefaultsEx(
+	multiaddr theMultiAddr,			// Destination node
+	bool skipShutdownRisks)
+{
+	double romSum, eeVer, cmdRes;
+	packetbuf buf;
+	cnErrCode theErr;
+	unsigned i, maxItems;
+	double nodeVers, pVal;
+	optionReg opts;
+	double iMax;
+
+	maxItems = sizeof(initData)/sizeof(factoryInitData);
+
+	// Dis-Acknowledge EE update
+	if ((theErr = cpmGetParameter(theMultiAddr, CPM_P_EE_VER, &eeVer)) != MN_OK)
+		return(theErr);
+	if ((theErr = cpmGetParameter(theMultiAddr, CPM_P_ROM_SUM, &romSum)) != MN_OK)
+		return(theErr);
+    if ((theErr = netSetParameterInfo(theMultiAddr, CPM_P_EE_UPD_ACK , 
+										  -eeVer, TRUE)) != MN_OK)
+		return(theErr);
+
+	if ((theErr = cpmGetParameter(theMultiAddr, CPM_P_FW_VERS, &nodeVers)) != MN_OK)
+		return(theErr);
+    
+	if ((theErr = cpmGetParameter(theMultiAddr, CPM_P_OPTION_REG, &pVal)) != MN_OK)
+		return(theErr);
+    opts.bits = (unsigned)pVal;
+
+	// Get the command resolution for velocity and acceleration conversions
+	if ((theErr = cpmGetParameter(theMultiAddr, CPM_P_CMD_CNTS_PER_REV, &cmdRes)) != MN_OK)
+		return(theErr);
+
+	if ((theErr = cpmGetParameter(theMultiAddr, CPM_P_DRV_I_MAX, &iMax)) != MN_OK)
+		return(theErr);
+
+	// Parameter info
+	paramInfo const *pTheParam;			// Current parameter fixed info
+ 	appNodeParam coreParam;				// Parameter cracker
+ 	// Extract out the node address parts, the netGetFirmwareID verified the
+	// multi-address is OK.
+	netaddr cNum;
+	nodeaddr theNode;
+	cNum = NET_NUM(theMultiAddr);
+	theNode = NODE_ADDR(theMultiAddr);
+	//cnErrCode lastLoadErr=MN_OK;		// Last non-OK error in load loop
+
+	for (i=0 ; i<maxItems ; i++) {
+		// Get parameter info to see if this would be OK to use
+		coreParam.bits = initData[i].paramNum;
+		pTheParam = &SysInventory[cNum].NodeInfo[theNode].paramBankList[coreParam.fld.bank].fixedInfoDB[coreParam.fld.param].info;
+		bool inThisVers = (initData[i].minVersion & 0x10000000) ? 
+			nodeVers < (int)(-1*initData[i].minVersion) : 
+			nodeVers >= initData[i].minVersion;
+
+		bool advChkOK = !(pTheParam->paramType & PT_ADV)		// All non-advanced OK
+				|| ((pTheParam->paramType & PT_ADV) && (opts.cpm.Advanced));
+		bool fwOptOK = (initData[i].fwOption==0)		// Cover invariant cases
+				|| (opts.Common.Product==3 && initData[i].fwOption==2);  // Cover K case(s)
+		// AC green 
+		bool thisHW = (nodeulong)(opts.DrvCommon.HwPlatform+1) == initData[i].hwPlat
+				|| initData[i].hwPlat == 0;
+		// Avoid shutdowns caused by the reset sequence
+		bool shdnOK = !(skipShutdownRisks && (pTheParam->paramType & PT_RST_SHDN_RISK));
+		if (inThisVers && advChkOK && fwOptOK && thisHW && shdnOK) {  
+			switch (initData[i].type) {
+				case RAM:
+					// There is no EE version; just set the RAM value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum, 
+						                     initData[i].value, TRUE);
+					break;
+				case NV:
+					// There is no RAM shadow; just set the EE value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum|PARAM_OPT_MASK, 
+						                     initData[i].value, TRUE);
+					break;
+				case NVRV:
+					// Set the RAM version and the EE version will be updated
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum, 
+						                     initData[i].value, TRUE);
+					break;
+				case NVR:
+					// Set non-volatile
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum|PARAM_OPT_MASK, 
+						                     initData[i].value, TRUE);
+					//If the EE write failed, don't bother trying the RAM value
+					if (theErr == MN_OK){
+						// Set RAM shadow
+						theErr = netSetParameterInfo(theMultiAddr, 
+												 initData[i].paramNum, 
+												 initData[i].value, TRUE);
+						//In this case, we don't really care if the RAM value took
+						theErr = MN_OK;
+					}
+					break;
+				case RO:
+					break;
+			}
+		}
+		else {
+#if _DEBUG
+			_RPT1(_CRT_WARN, "cpmFactoryDefaults: skipping param %d\n", initData[i].paramNum);
+#endif
+		}
+		if (theErr != MN_OK) {
+			_RPT2(_CRT_WARN, "cpm factory defaults: failed param#%d, err=0x%x\n",
+							 initData[i].paramNum, theErr);				
+			return(theErr);
+		}
+	}
+
+	/* Update velocity parameters */
+	maxItems = sizeof(initSpdAccelData)/sizeof(factoryInitData);
+	for (i=0 ; i<maxItems ; i++) {
+		// Get parameter info to see if this would be OK to use
+		coreParam.bits = initSpdAccelData[i].paramNum;
+		pTheParam = &SysInventory[cNum].NodeInfo[theNode].paramBankList[coreParam.fld.bank].fixedInfoDB[coreParam.fld.param].info;
+		bool inThisVers = ((initSpdAccelData[i].minVersion & 0x10000000)
+				&& nodeVers < (int)(-1*initSpdAccelData[i].minVersion)) 
+					|| nodeVers >= initSpdAccelData[i].minVersion;
+		bool advChkOK = !(pTheParam->paramType & PT_ADV)		// All non-advanced OK
+				|| ((pTheParam->paramType & PT_ADV) && (opts.cpm.Advanced));
+		bool fwOptOK = (initSpdAccelData[i].fwOption==0)		// Cover invariant cases
+				|| (opts.Common.Product==3 && initSpdAccelData[i].fwOption==2);  // Cover K case(s)
+		// AC green 
+		bool thisHW = (opts.DrvCommon.HwPlatform + 1U) == initSpdAccelData[i].hwPlat
+			|| initSpdAccelData[i].hwPlat == 0;
+		if (inThisVers && advChkOK && fwOptOK && thisHW) {  
+			double driveVal = initSpdAccelData[i].value * cmdRes / 60;
+			switch (initSpdAccelData[i].type) {
+				case RAM:
+					// There is no EE version; just set the RAM value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initSpdAccelData[i].paramNum, 
+						                     driveVal, TRUE);
+					break;
+				case NV:
+					// There is no RAM shadow; just set the EE value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initSpdAccelData[i].paramNum|PARAM_OPT_MASK, 
+						                     driveVal, TRUE);
+					break;
+				case NVRV:
+					// Set the RAM version and the EE version will be updated
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initSpdAccelData[i].paramNum, 
+						                     driveVal, TRUE);
+					break;
+				case NVR:
+					// Set non-volatile
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initSpdAccelData[i].paramNum|PARAM_OPT_MASK, 
+						                     driveVal, TRUE);
+					//If the EE write failed, don't bother trying the RAM value
+					if (theErr == MN_OK){
+						// Set RAM shadow
+						theErr = netSetParameterInfo(theMultiAddr, 
+												 initSpdAccelData[i].paramNum, 
+												 driveVal, TRUE);
+						//In this case, we don't really care if the RAM value took
+						theErr = MN_OK;
+					}
+					break;
+				case RO:
+					break;
+			}
+		}
+		else {
+#if _DEBUG
+			_RPT1(_CRT_WARN, "cpmFactoryDefaults spdAccelItems: skipping param %d\n", initSpdAccelData[i].paramNum);
+#endif
+		}
+		if (theErr != MN_OK) {
+			_RPT2(_CRT_WARN, "cpm factory defaults spdAccelItems: failed param#%d, err=0x%x\n",
+							 initSpdAccelData[i].paramNum, theErr);				
+			return(theErr);
+		}
+	}
+
+	/* Update torque parameters */
+	maxItems = sizeof(initTrqData)/sizeof(factoryInitData);
+	for (i=0 ; i<maxItems ; i++) {
+		// Get parameter info to see if this would be OK to use
+		coreParam.bits = initTrqData[i].paramNum;
+		pTheParam = &SysInventory[cNum].NodeInfo[theNode].paramBankList[coreParam.fld.bank].fixedInfoDB[coreParam.fld.param].info;
+		bool inThisVers = ((initTrqData[i].minVersion & 0x10000000)
+				&& nodeVers < (int)(-1*initTrqData[i].minVersion)) 
+					|| nodeVers >= initTrqData[i].minVersion;
+		bool advChkOK = !(pTheParam->paramType & PT_ADV)		// All non-advanced OK
+				|| ((pTheParam->paramType & PT_ADV) && (opts.cpm.Advanced));
+		bool fwOptOK = (initTrqData[i].fwOption==0)		// Cover invariant cases
+				|| (opts.Common.Product==3 && initTrqData[i].fwOption==2);  // Cover K case(s)
+		// AC green 
+		bool thisHW = (opts.DrvCommon.HwPlatform + 1U) == initTrqData[i].hwPlat
+			|| initTrqData[i].hwPlat == 0;
+		if (inThisVers && advChkOK && fwOptOK && thisHW) {  
+			double driveVal = initTrqData[i].value * iMax;
+			switch (initTrqData[i].type) {
+				case RAM:
+					// There is no EE version; just set the RAM value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initTrqData[i].paramNum, 
+						                     driveVal, TRUE);
+					break;
+				case NV:
+					// There is no RAM shadow; just set the EE value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initTrqData[i].paramNum|PARAM_OPT_MASK, 
+						                     driveVal, TRUE);
+					break;
+				case NVRV:
+					// Set the RAM version and the EE version will be updated
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initTrqData[i].paramNum, 
+						                     driveVal, TRUE);
+					break;
+				case NVR:
+					// Set non-volatile
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initTrqData[i].paramNum|PARAM_OPT_MASK, 
+						                     driveVal, TRUE);
+					//If the EE write failed, don't bother trying the RAM value
+					if (theErr == MN_OK){
+						// Set RAM shadow
+						theErr = netSetParameterInfo(theMultiAddr, 
+												 initTrqData[i].paramNum, 
+												 driveVal, TRUE);
+						//In this case, we don't really care if the RAM value took
+						theErr = MN_OK;
+					}
+					break;
+				case RO:
+					break;
+			}
+		}
+		if (theErr != MN_OK) {
+			_RPT2(_CRT_WARN, "ClearPath factory defaults trqItems: failed param#%d, err=0x%x\n",
+							 initTrqData[i].paramNum, theErr);				
+			return(theErr);
+		}
+	}
+
+	// Clear out the user ID
+	theErr = cpmSetUserID(theMultiAddr, "");
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+    
+    // Clear out the motor filename
+	theErr = cpmSetMotorFileName(theMultiAddr, "");
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+
+	// Clear out the user's description
+
+	theErr = cpmSetUserDesc(theMultiAddr, "");
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+	// Clear the user managed storage
+	buf.Byte.BufferSize = 13;
+	for (i=0; i<4; i++) {
+		if ((theErr = cpmSetParameterEx(theMultiAddr, 
+									   (cpmParams)(CPM_P_USER_DATA_NV0+i), 
+									   &buf)) != MN_OK)
+			return(theErr);
+	}
+	// Setup the monitor port
+	double ticksPerTurn;
+	theErr = cpmGetParameter(theMultiAddr, CPM_P_FACT_DRV_ENC_EFF_DENS, &ticksPerTurn);
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+	iscMonState theMonState;
+	theMonState.filterTC = 0;
+	theMonState.var = MON_VEL_CMD;
+	// Convert RPM to Kticks/sec
+	theMonState.gain = 4000. * ticksPerTurn/60000.;
+	theErr = cpmSetMonitor(theMultiAddr, 0, &theMonState);
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+
+	// Set factory defaults of parameters wider than nodelong
+	if (nodeVers >= FW_MILESTONE_MIN_VOLT) {
+		coreParam.bits = CPM_P_EVENT_SHUTDOWN_MASK;
+		pTheParam = &SysInventory[cNum].NodeInfo[theNode].paramBankList[coreParam.fld.bank].fixedInfoDB[coreParam.fld.param].info;
+		buf.Byte.BufferSize = pTheParam->paramSize;
+		memset(buf.Byte.Buffer, (nodechar)-1, buf.Byte.BufferSize);
+		theErr = cpmSetParameterEx(theMultiAddr,
+			CPM_P_EVENT_SHUTDOWN_MASK,
+			&buf);
+		if (theErr != MN_OK) {
+			return(theErr);
+		}
+		theErr = cpmSetParameterEx(theMultiAddr,
+			cpmNonVol(CPM_P_EVENT_SHUTDOWN_MASK),
+			&buf);
+		if (theErr != MN_OK) {
+			return(theErr);
+		}
+	}
+
+	// Acknowledge firmware & configuration update
+    if ((theErr = netSetParameterInfo(theMultiAddr, CPM_P_EE_UPD_ACK, 
+										  eeVer, TRUE)) != MN_OK)
+		return(theErr);
+    if ((theErr = netSetParameterInfo(theMultiAddr, CPM_P_ROM_SUM_ACK, 
+										  romSum, TRUE)) != MN_OK)
+		return(theErr);
+    
+	// Force node to reset and re-init parameter DB
+	{
+		double pVal;
+		cpmGetParameter(theMultiAddr, CPM_P_TIMESTAMP, &pVal);
+	}
+	// Indicate that the params need to be refreshed
+	SysInventory[cNum].pNCS->paramsHaveChanged[theNode] = TRUE;
+	// Got through here OK
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmForkMoveVel
+//
+//	DESCRIPTION:
+/**
+	Sends a move that ramps up or down in speed to \a velTargetStepsPerSec 
+	(using the previously set limits for acceleration and jerk [RAS]).
+
+	Program execution does not suspend.  Once target velocity is achieved, the
+	move stays there until explicitly changed. The velocity is specified
+	as steps/second.
+
+	Setting the \a triggered parameter true will cause the move to await
+	a trigger event before starting.
+
+	\todo see ref ISCtriggerRefPage Starting Triggered Moves
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] velTargetStepsPerSec Target velocity in encoder steps per second
+		units.
+	\param[in] triggered Set this parameter to download the move and await a 
+		trigger event.
+	\param[out] pBuffersRemaining If MN_OK, this is count of buffers available
+		more moves.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmForkVelMove(
+			multiaddr theMultiAddr,			// Destination node
+			double velTargetStepsPerSec,	// Target velocity (steps/sec)
+			nodebool triggered,				// Start move with trigger
+			nodelong *pBuffersRemaining)	// Ptr to move buf remaining cnt		
+{
+	mgVelStyle theStyle = triggered ? MG_MOVE_VEL_STYLE_TRIG : MG_MOVE_VEL_STYLE;
+	return iscForkMoveVelQueued(theMultiAddr, velTargetStepsPerSec,
+							    0, theStyle, pBuffersRemaining);
+}
+//*
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmReVector
+//
+//	DESCRIPTION:
+/**
+	Reset the vector search flag. This function is mostly diagnostic in nature.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmReVector(
+			multiaddr theMultiAddr)	// Target node addr
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+	// Fill in the command head parts
+	theCmd.Fld.Addr = theMultiAddr;
+	theCmd.Fld.PktLen = 1;
+	theCmd.Byte.Buffer[CMD_LOC] = SC_CMD_RE_VECTOR;
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmAddToPosition
+//
+//  DESCRIPTION:
+/**
+	Change the node's measured and commanded positions by the \p theOffset 
+	amount.	All position capture sources are adjusted to reflect the offset
+	in number space. The change is atomically applied to all values. 
+
+	This function will not cause any motion to occur and provides a mechanism
+	for aligning the application's number space with the node's.
+		
+	\remark Incoming capture sources properly reflect the offset in 
+	number space.
+	\remark Since this command changes the position of the number space,
+	Soft Limits are ignored after this command is performed until the next
+	homing sequence if performed.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theOffset Offset amount in encoder units.
+
+	\return MN_OK if successful
+
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmAddToPosition(
+			multiaddr theMultiAddr,		// Node address
+			double theOffset)			// Offset amount
+{
+	packetbuf theCmd, theResp;					// Input and output buffers
+	cnErrCode theErr;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+	// Format the command
+	theCmd.Fld.Addr = theMultiAddr;	
+	theCmd.Fld.PktLen = SC_CMD_ADD_POSN_LEN;
+	theCmd.Byte.Buffer[CMD_LOC] = SC_CMD_ADD_POSN;
+	*((nodelong *)&theCmd.Byte.Buffer[CMD_LOC+1]) 
+		= (nodelong)(theOffset);
+	// Run it and wait for response
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	return theErr;
+}
+//																               *
+//******************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmSetUserDesc
+//
+//	DESCRIPTION:
+/**		
+	Set the user description to the null-terminated ANSI string. If the
+	string is too long it will be truncated at the maximum point to 
+	allow for a null-terminated end.
+
+	\see SC_USER_DESCR_SZ Use this for the maximum allowed string.
+
+ 	\param[in] theMultiAddr Node Address
+ 	\param[in] pNewDescr Pointer to null-terminated replacement string.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetUserDesc(
+			multiaddr theMultiAddr,
+			const char *pNewDescr)
+{
+	return netSetUserDescription(theMultiAddr, pNewDescr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmGetUserDesc
+//
+//	DESCRIPTION:
+/**		
+	Get the user description string from the node. A null-terminated
+	string of up to \a maxBufSize is returned.
+
+	\see SC_USER_DESCR_SZ Use this for the maximum allowed string.
+
+ 	\param[in] theMultiAddr Node Address
+ 	\param[out] pDescription description
+ 	\param[in] maxBufSize description
+
+	\return  MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetUserDesc(
+			multiaddr theMultiAddr,
+			char *pDescription,
+			Uint16 maxBufSize)
+{
+	return netGetUserDescription(theMultiAddr, pDescription, maxBufSize);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmSendHome
+//
+//	DESCRIPTION:
+/**		
+	Tell the node to initiate the homing sequencer
+
+ 	\param[in] theMultiAddr Node Address
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSendHome(
+			multiaddr theMultiAddr)
+{
+	cnErrCode theErr = cpmSetParameter(
+		theMultiAddr, CPM_P_DRV_SET_FLAGS, 4);
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmSetUserOutputReg
+//
+//  DESCRIPTION:
+/**
+	Set the state of the User Output Register. When the output register is
+	controlled by bits in this register, changes here are reflected in the 
+	output register. This register typically is used to enable the drive and to 
+	set the General Purpose Outputs.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewOutReg New state for User Output Register.
+
+	\return	 MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmSetUserOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			cpmOutReg *pNewOutReg)			// New setting
+{
+	// Update the double value
+	plaOutReg *pOuts = (plaOutReg *)pNewOutReg;
+	return(cpmSetParameter(theMultiAddr, CPM_P_USER_OUT_REG, pOuts->bits));
+}
+
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		cpmGetUserOutputReg
+//
+//  DESCRIPTION:
+/**
+	Get the current setting of the User Output Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pOutReg Ptr to current state.
+
+	\return MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmGetUserOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			cpmOutReg *pOutReg)	// Current setting
+{
+	double pVal;
+	cnErrCode theErr;
+	
+	theErr = cpmGetParameter(theMultiAddr, CPM_P_USER_OUT_REG, &pVal);
+	// Update the raw buffer
+	plaOutReg *pOuts = (plaOutReg *)pOutReg;
+	pOuts->bits = (nodeushort)pVal;
+	return(theErr);
+}
+
+//																               *
+//******************************************************************************
+//
+//
+////******************************************************************************
+////	NAME																	   *
+////		cpmGetOutputReg
+////
+////  DESCRIPTION:
+///**
+//	Get the current setting of the Output Register.
+//
+//	\param[in] theMultiAddr The address code for this node.
+//	\param[out] pGPOreg Ptr to current state.
+//
+//	\return MN_OK if successful
+//**/
+////	SYNOPSIS:
+//MN_EXPORT cnErrCode MN_DECL cpmGetOutputReg(
+//			multiaddr theMultiAddr,		// Node address
+//			plaOutReg *pGPOreg)			// Current setting
+//{
+//	double pVal;
+//	cnErrCode theErr;
+//	
+//	theErr = cpmGetParameter(theMultiAddr, CPM_P_OUT_REG, &pVal);
+//	// Update the raw buffer
+//	pGPOreg->bits = (nodeushort)pVal;
+//	return(theErr);
+//}
+//
+////																               *
+////******************************************************************************
+//
+//
+////******************************************************************************
+////	NAME																	   *
+////		cpmGetOutputRiseReg
+////
+////  DESCRIPTION:
+///**
+//	Get the current setting of the Output Rise Register
+//
+//	\param[in] theMultiAddr The address code for this node.
+//	\param[out] pGPOreg Ptr to current state.
+//
+//	\return MN_OK if successful
+//**/
+////	SYNOPSIS:
+//MN_EXPORT cnErrCode MN_DECL cpmGetOutputRiseReg(
+//			multiaddr theMultiAddr,		// Node address
+//			plaOutReg *pGPOreg)			// Current setting
+//{
+//	double pVal;
+//	cnErrCode theErr;
+//	
+//	theErr = cpmGetParameter(theMultiAddr, CPM_P_OUT_RISE_REG, &pVal);
+//	// Update the raw buffer
+//	pGPOreg->bits = (nodeushort)pVal;
+//	return(theErr);
+//}
+////																               *
+////******************************************************************************
+//
+//
+////******************************************************************************
+////	NAME																	   *
+////		cpmGetOutputFallReg
+////
+////  DESCRIPTION:
+///**
+//	Get the current setting of the Output Fall Register
+//
+//	\param[in] theMultiAddr The address code for this node.
+//	\param[out] pGPOreg Ptr to current state.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//**/
+////	SYNOPSIS:
+//MN_EXPORT cnErrCode MN_DECL cpmGetOutputFallReg(
+//			multiaddr theMultiAddr,		// Node address
+//			plaOutReg *pGPOreg)			// Current setting
+//{
+//	double pVal;
+//	cnErrCode theErr;
+//	
+//	theErr = cpmGetParameter(theMultiAddr, CPM_P_OUT_FALL_REG, &pVal);
+//	// Update the raw buffer
+//	pGPOreg->bits = (nodeushort)pVal;
+//	return(theErr);
+//}
+////																               *
+////******************************************************************************
+//
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmForkPosnMove
+//
+//	DESCRIPTION:
+/**
+	This is the main function to initiate a positional moves and inquire
+	on how many more pending moves the node will accept. 
+
+	The motion is constrained to the settings of the acceleration, velocity
+	and jerk limits.  For the more complex head and tail moves the additional
+	constraints of head and tail distances as well as head/tail velocity
+	limits apply. Once this move has been accepted, any constraints values
+	changed will apply only to the next move segment.
+
+	The \a moveType field is most easily supplied a #mgPosnStyle enumeration
+	type. This #mgPosnStyle provides a copy constructor to allow direct
+	use of this enumeration.
+
+	A C example for issuing a head/tail absolute position move.
+	\code
+	theErr = cpmForkPosnMove(m_nodeAddr, target, MG_MOVE_STYLE_HEADTAIL_ABS, &nMovesLeft);
+	\endcode 
+
+	\remark If a triggered move is accepted in a "stream" of other non-triggered
+	moves, it will block upon its execution until a new trigger event
+	occurs.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] posnTarget Target position. If this is a relative type move 
+		then this is the increment from the initial position. If this is 
+		and absolute move, then this is the final location.
+	\param[in] moveType The move style. This is a bit oriented value that
+		specifies the profile, triggering event handling and the handling 
+		of the target.
+	\param[out] pBuffersRemaining Pointer to buffers remaining count.
+		Upon return the node will accept up to \a pBuffersRemaining more
+		calls to this function.
+
+	\return	 MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmForkPosnMove(
+			multiaddr theMultiAddr,			// Destination node
+			nodelong posnTarget,				// Target (steps)
+			mgPosnStyle moveType,			// Style code
+			nodelong *pBuffersRemaining)		// Ptr to move buf remaining cnt
+{
+	mgMoveProfiledInfo spec;
+	spec.value = posnTarget;
+	spec.type = moveType.styleCode;
+	return(iscMoveProfiledQueued(theMultiAddr, &spec, pBuffersRemaining));
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		cpmForkProfiledMove
+//
+//	DESCRIPTION:
+/**
+	This is the main function to initiate profiled moves and inquire
+	on how many more pending moves the node will accept. 
+
+	\param[in] theMultiAddr			The address code for this node.
+	\param[in] spec					The move specification
+	\param[out] pBuffersRemaining	Pointer to buffers remaining count.
+		Upon return the node will accept up to \a pBuffersRemaining more
+		calls to this function.
+
+	\return	 MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL cpmForkProfiledMove(
+			multiaddr theMultiAddr,			// Destination node
+			mgMoveProfiledInfo *spec,		// Move specification
+			nodelong *pBuffersRemaining)	// Ptr to move buf remaining cnt
+{
+	return(iscMoveProfiledQueued(theMultiAddr, spec, pBuffersRemaining));
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		_cpmStatusRegFlds::StateStr
+//
+//	DESCRIPTION:
+/**
+Return a buffer of newline-delimited field names of all bits that
+are set in the status register.
+
+\param[in]		buffer		A buffer to store the created string
+\param[in]		size		The size of the given buffer
+
+\return		A pointer to the filled-in buffer
+**/
+//	SYNOPSIS:
+char * MN_DECL _cpmStatusRegFlds::StateStr(char *buffer, size_t size) const
+{
+	// Value to return
+	std::string retVal, bitVals;
+	retVal.reserve(size);
+	// Convert to bits
+	Uint16 mask;
+	// Convert to our register view to get at bits
+	cpmStatusReg &bits = *(cpmStatusReg *)this;
+	size_t bitIndex = 47;
+
+	// Token to append
+	char token[50];
+	retVal = "0x";
+	int nInts = sizeof(bits) / sizeof(Uint16);
+	for (int intNum = nInts-1; intNum >= 0; intNum--) {
+		snprintf(token, sizeof(token), "%04X ", bits.bits[intNum]);
+		retVal += token;
+		for (size_t bitNum = 0; bitNum < 16; bitNum++) {
+			mask = 0x8000 >> bitNum;
+			switch (bitIndex) {
+			case 32:
+				snprintf(token, sizeof(token), "[%02d-%02d] InMotion: %s\n", 
+					int(bitIndex), int(bitIndex + 1),
+					CPSCinMotions[InMotion]);
+				bitVals += token;
+				break;
+			case 33:
+				// MSB of InMotion covered already
+				break;
+			case 40:
+				snprintf(token, sizeof(token), "[%02d-%02d] ShutdownState: %s\n", 
+					int(bitIndex), int(bitIndex + 1),
+					CPSCshutdowns[ShutdownState]);
+				bitVals += token;
+				break;
+			case 41:
+				// MSB of ShutdownState covered already
+				break;
+			default:
+				// Print only set bits
+				if (bits.bits[intNum] & mask) {
+					snprintf(token, sizeof(token), "[%02d] %s\n", int(bitIndex),
+						CPSCStatusBitStrs[bitIndex]);
+					bitVals += token;
+				}
+			}
+			bitIndex--;
+		}
+	}
+	retVal += "\n";
+	retVal += bitVals;
+	strncpy(buffer, retVal.c_str(), size);
+	// Ensure that the buffer is null-terminated
+	buffer[size-1] = 0;
+	return (buffer);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		_cpmAlertFlds::StateStr
+//
+//	DESCRIPTION:
+/**
+Return a buffer of newline-delimited field names of all bits that
+are set in the alert register.
+
+\param[in]		buffer		A buffer to store the created string
+\param[in]		size		The size of the given buffer
+
+\return		A pointer to the filled-in buffer
+**/
+//	SYNOPSIS:
+char * MN_DECL _cpmAlertFlds::StateStr(char *buffer, size_t size) const
+{
+	// Value to return
+	std::string retVal, bitVals;
+	retVal.reserve(size);
+	// Convert to bits
+	Uint32 mask;
+	// Convert to our register view to get at bits
+	cpmAlertReg &bits = *(cpmAlertReg *)this;
+	size_t bitIndex = 95;
+	// Token to append
+	char token[50];
+	int nInts = sizeof(bits) / sizeof(Uint32);
+
+	retVal = "0x";
+	for (int intNum = nInts-1; intNum>=0; intNum--) {
+		snprintf(token, sizeof(token), "%04X %04X ", 
+			bits.bits[intNum]>>16, bits.bits[intNum]&0xFFFF);
+		retVal += token;
+		for (size_t bitNum = 0; bitNum < 32; bitNum++) {
+			mask = 0x80000000 >> bitNum;
+			// Print only set bits
+			if (bits.bits[intNum] & mask) {
+				snprintf(token, sizeof(token), "[%02d] %s\n", int(bitIndex),
+					CPSCalertsBitStrs[bitIndex]);
+				bitVals += token;
+			}
+			bitIndex--;
+		}
+	}
+	retVal += "\n";
+	retVal += bitVals;
+	strncpy(buffer, retVal.c_str(), size);
+	// Ensure that the buffer is null-terminated
+	buffer[size-1] = 0;
+	return (buffer);
+}
+//																			  *
+//*****************************************************************************
+
+/// @}
+//==============================================================================
+//	END OF FILE cpscAPI.cpp
+//==============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/cpmClassImpl.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/cpmClassImpl.cpp
new file mode 100644
index 000000000..8c3e94b4b
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/cpmClassImpl.cpp
@@ -0,0 +1,1800 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/cpmClassImpl.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: cpmClassImpl.cpp $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	\brief Implementations of the ClearPath-SC node object and dependencies.
+
+	
+**/
+//
+// CREATION DATE:
+//		2015-12-08 18:22:51
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	cpmClassImpl.cpp headers
+//
+#include "pubCpmCls.h"
+#include "pubCpmAPI.h"
+#include "tekEvents.h"
+#include "lnkAccessAPI.h"
+#include "lnkAccessCommon.h"
+#include "meridianHdrs.h"
+#include "netCmdPrivate.h"
+
+// Disable windows warning about 'this' in constructor.
+#ifdef _MSC_VER
+#pragma warning(disable:4355)
+#pragma warning(disable:4715)
+#if _MSC_VER<=1800
+#define snprintf sprintf_s
+#endif
+#endif
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	cpmClassImpl.cpp function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	cpmClassImpl.cpp constants
+//
+//
+#define FW_MILESTONE_PWR 0x1504
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	cpmClassImpl.cpp static variables
+//
+// 
+	extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+	// Read-modify-write mutex for node parameters. This is declared
+	// here to avoid including events headers to make these opaque to 
+	// the user.
+	CCCriticalSection ParamLockMutex[NET_CONTROLLER_MAX][MN_API_MAX_NODES];
+	// Events objects to signal Attention packets received from the node
+	CCEvent AttnEvent[NET_CONTROLLER_MAX][MN_API_MAX_NODES];
+	// Read-modify-write mutex for node parameters. This is declared
+	// here to avoid including events headers to make these opaque to 
+	// the user.
+	CCCriticalSection AttnEvtMutex[NET_CONTROLLER_MAX][MN_API_MAX_NODES];
+	CCCriticalSection AttnCntMutex[NET_CONTROLLER_MAX][MN_API_MAX_NODES];
+	int32_t AttnListenerCnt[NET_CONTROLLER_MAX][MN_API_MAX_NODES];
+
+//																			  *
+//*****************************************************************************
+using namespace sFnd;
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Helper function to fill in an error object.
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMstring Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+CPMstring::CPMstring(INode &theNode, nodeparam pNum, enum _srcs location)
+	: ValueString(theNode, pNum, location)
+{
+
+}
+
+void CPMstring::Refresh()
+{
+	cnErrCode theErr = MN_ERR_FAIL;
+	mnErr eInfo;
+	char tempStr[MAX_STR];
+	double theDblVal;
+	paramInfo theInfo;
+	paramValue theVal;
+	uint16_t romSum;
+
+	switch (m_location) {
+	case STR_MODEL_STR:
+		theErr = netGetPartNumber(Node().Info.Ex.Addr(), tempStr, MAX_STR);
+		break;
+	case STR_USERID:
+		theErr = netGetUserID(Node().Info.Ex.Addr(),
+							  tempStr, MAX_STR);
+		break;
+	case STR_HW_VERSION:
+		theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+									MN_P_HW_VERSION, &theInfo, &theVal);
+		if (theErr == MN_OK) {
+			strncpy(tempStr, (char *)theVal.raw.Byte.Buffer, MAX_STR);
+		}
+		break;
+	case STR_FW_VERSION:
+		theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+			MN_P_FW_VERSION, &theInfo, &theVal);
+		if (theErr == MN_OK) {
+			theErr = netGetParameterDbl(Node().Info.Ex.Addr(), 
+									MN_P_ROM_SUM, &theDblVal);
+			if (theErr == MN_OK) {
+				romSum = uint16_t(theDblVal);
+				snprintf(tempStr, MAX_STR, "%s %04X",
+					(char *)theVal.raw.Byte.Buffer, romSum);
+			}
+		}
+		break;
+	default:
+		// Implement me
+		break;
+	}
+	// Ensure that the buffer is null-terminated
+	tempStr[MAX_STR-1] = 0;
+
+	// If OK tempStr has our string
+	if (theErr == MN_OK) {
+		memcpy(m_lastValue, m_currentValue, MAX_STR);
+		memcpy(m_currentValue, tempStr, MAX_STR);
+		Valid(true);
+		return;
+	}
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+
+void CPMstring::Value(const char *newValue)
+{
+	cnErrCode theErr=MN_ERR_FAIL;
+	mnErr eInfo;
+
+	switch (m_location) {
+	case STR_USERID:
+		theErr = netSetUserID(Node().Info.Ex.Addr(), newValue);
+		if (theErr == MN_OK) {
+			memcpy(m_lastValue, m_currentValue, MAX_STR);
+			memcpy(m_currentValue, newValue, MAX_STR);
+			Valid(true);
+			return;
+		}
+		break;
+		
+	// Read-only parameters, cause errors
+	case STR_MODEL_STR:
+	case STR_HW_VERSION:
+	case STR_FW_VERSION:
+		theErr = MN_ERR_CMD_WR_FAIL;
+		break;
+	default:
+		// We don't handle these yet
+		break;
+	}
+	// Show as busted
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+
+const char *CPMstring::Value()
+{
+	if (!m_valid) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMlimitsAdv Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+void CPMlimitsAdv::StartPosFoldback(bool engage)
+{
+	mnOutReg fld;
+	fld.cpm.StartPosTrqFldBk = true;
+	if (engage)
+		Node().Outs.User.Set(fld);
+	else
+		Node().Outs.User.Clear(fld);
+}
+
+
+bool CPMlimitsAdv::StartPosFoldback()
+{
+	return Node().Outs.User.Value().cpm.StartPosTrqFldBk;
+}
+
+void CPMlimitsAdv::StartNegFoldback(bool engage)
+{
+	mnOutReg fld;
+	fld.cpm.StartNegTrqFldBk = true;
+	if (engage)
+		Node().Outs.User.Set(fld);
+	else
+		Node().Outs.User.Clear(fld);
+}
+
+
+bool CPMlimitsAdv::StartNegFoldback()
+{
+	return Node().Outs.User.Value().cpm.StartNegTrqFldBk;
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMhoming Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+
+/**		
+	\copydoc IHoming::Initiate()
+**/
+void CPMhoming::Initiate()
+{
+	cpmSetFlagsReg flgs;
+	flgs.fld.HomingReq = 1;
+	// Initiate homing (see drvSetFlagsReg in ioHAL for this constant)
+	Node().Info.Ex.Parameter(CPM_P_DRV_SET_FLAGS, flgs.bits);
+}
+
+/**
+	\copydoc IHoming::IsComplete
+**/
+bool CPMhoming::IsHoming()
+{
+	Node().Status.RT.Refresh();
+	return Node().Status.RT.Value().cpm.Homing;
+}
+
+/**
+	\copydoc IHoming::WasHomed
+**/
+bool CPMhoming::WasHomed()
+{
+	Node().Status.RT.Refresh();
+	return Node().Status.RT.Value().cpm.WasHomed;
+}
+
+/**
+\copydoc IHoming::SignalComplete
+**/
+void CPMhoming::SignalComplete()
+{
+	cpmSetFlagsReg flgs;
+	flgs.fld.HomingComplete = 1;
+	// Complete homing (see drvSetFlagsReg in ioHAL for this constant)
+	Node().Info.Ex.Parameter(CPM_P_DRV_SET_FLAGS, flgs.bits);
+}
+
+/**
+\copydoc IHoming::SignalInvalid()
+**/
+void CPMhoming::SignalInvalid()
+{
+	cpmSetFlagsReg flgs;
+	flgs.fld.HomingInvalid = 1;
+	// Complete homing (see drvSetFlagsReg in ioHAL for this constant)
+	Node().Info.Ex.Parameter(CPM_P_DRV_SET_FLAGS, flgs.bits);
+}
+
+/**
+\copydoc IHoming::HomingValid()
+**/
+bool CPMhoming::HomingValid()
+{
+	bool isValid = true;
+	paramValue* val = new paramValue();
+	netGetParameterInfo(Node().Info.Ex.Addr(), CPM_P_XPS_FEAT_AT_HOME, NULL, val);
+	
+	if (Node().Setup.Ex.HW.Value().cpm.HomingStyle == _cpmHwConfigFlds::HOME_TO_SWITCH &&
+		val->value == 0) {
+		isValid = false;
+	}
+	return isValid;
+}
+//																			  *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMinfoEx Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMinfoEx::Parameter
+//
+//	DESCRIPTION:
+/**
+\copydoc IInfoEx::Parameter
+**/
+double CPMinfoEx::Parameter(nodeparam index)
+{
+	double paramVal;
+	cnErrCode theErr = netGetParameterDbl(Node().Info.Ex.Addr(), mnParams(index),
+										  &paramVal);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, 
+			"Parameter(%d) failed to read,", index);
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return paramVal;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMinfoEx::Parameter
+//
+//	DESCRIPTION:
+/**
+\copydoc IInfoEx::Parameter
+**/
+void CPMinfoEx::Parameter(nodeparam index, double newValue)
+{
+	cnErrCode theErr = netSetParameterDbl(Node().Info.Ex.Addr(), mnParams(index),
+										  newValue);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, 
+			"Parameter(%d) failed to write %f", index, newValue);
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMinfo Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+
+void CPMinfo::NodeType(nodeTypes newType) {
+	m_nodeType = newType;
+	bool isAdvanced = newType == IInfo::CLEARPATH_SC_ADV;
+	INode &theNode = Node();
+	//IPort &thePort = Node().Port;
+	theNode.Adv.Supported(isAdvanced);
+	theNode.Info.Adv.Supported(isAdvanced);
+	theNode.Limits.Adv.Supported(isAdvanced);
+	theNode.Motion.Adv.Supported(isAdvanced);
+	theNode.Status.Adv.Supported(isAdvanced);
+}
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMinfo::UserData
+//
+//	DESCRIPTION:
+/**		
+	\copydoc IInfo::UserData(size_t, nodeuchar[])
+**/
+void CPMinfo::UserData(size_t bank, const uint8_t theData[MN_USER_NV_SIZE])
+{
+	cnErrCode theErr;
+	packetbuf rBuf;
+	if (bank < 4) {
+		memcpy(rBuf.Byte.Buffer, theData, MN_USER_NV_SIZE);
+		rBuf.Byte.BufferSize = MN_USER_NV_SIZE;
+		theErr = netSetParameterEx(Node().Info.Ex.Addr(),
+									nodeparam(bank + CPM_P_USER_DATA_NV0),
+									&rBuf);
+		if (theErr != MN_OK) {
+			mnErr eInfo;
+			fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_, "");
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+	}
+	else {
+		mnErr eInfo;
+		fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_,
+			"Bank number must be less then 4.");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMinfo::UserData
+//
+//	DESCRIPTION:
+/**		
+	\copydoc IInfo::UserData(size_t)
+**/
+std::vector<uint8_t> CPMinfo::UserData(size_t bank)
+{
+	std::vector<uint8_t> rVal;
+	paramValue rBuf;
+	// Args OK
+	if (bank < 4) {
+		rVal.reserve(MN_USER_NV_SIZE);
+		cnErrCode theErr;
+		theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+			nodeparam(bank + CPM_P_USER_DATA_NV0), NULL, &rBuf);
+		if (theErr != MN_OK) {
+			mnErr eInfo;
+			fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_, "");
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+	}
+	else {
+		mnErr eInfo;
+		fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_, 
+			"Bank number must be less then 4.");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	// Update our vector with returned data
+	for (size_t i = 0; i < MN_USER_NV_SIZE; i++) {
+		rVal.push_back(uint8_t(rBuf.raw.Byte.Buffer[i]));
+	}
+	return rVal;
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//						CPMlimits class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//					  CPMlimitsAdv class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//					    CPMmotion Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Kinematic Constraint Group
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+/**		
+	\copydoc IMotion::MovePosnDurationMsec
+**/
+double CPMmotion::MovePosnDurationMsec(int32_t target, bool targetIsAbsolute)
+{
+	double retVal = IMotion::MovePosnDurationMsec(target, targetIsAbsolute);
+	retVal += Node().Info.Ex.Parameter(CPM_P_DRV_MV_DN_TC);
+	return retVal;
+}
+
+/**		
+	\copydoc IMotion::MoveVelDurationMsec
+**/
+double CPMmotion::MoveVelDurationMsec(double target)
+{
+	double retVal = IMotion::MoveVelDurationMsec(target);
+	retVal += Node().Info.Ex.Parameter(CPM_P_DRV_MV_DN_TC);
+	return retVal;
+}
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Motion Initiating Group
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+/**		
+	\copydoc IMotion::MovePosnStart
+**/
+size_t CPMmotion::MovePosnStart(int32_t target, 
+						   bool targetIsAbsolute,
+						   bool hasDwell)
+{
+	int32_t bufsLeft = 0;
+	mgPosnStyle theStyle;
+	theStyle.fld.wait = false;
+	theStyle.fld.head = false;
+	theStyle.fld.tail = false;
+	theStyle.fld.relative = !targetIsAbsolute;
+	theStyle.fld.dwell = hasDwell;
+	cnErrCode theErr = cpmForkPosnMove(Node().Info.Ex.Addr(), target,
+		theStyle, &bufsLeft);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return bufsLeft;
+}
+
+/**		
+	\copydoc IMotion::MoveVelStart(double)
+**/
+size_t CPMmotion::MoveVelStart(double target)
+{
+	int32_t bufsLeft = 0;
+
+	// This is safe as CPMmotion always back point to a CPMnode instance
+	CPMnode &myNode = static_cast<CPMnode &>(Node());
+	cnErrCode theErr = cpmForkVelMove(Node().Info.Ex.Addr(),
+		target/ myNode.velScale(),	false, &bufsLeft);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return bufsLeft;
+}
+
+
+bool CPMmotion::VelocityReachedTarget()
+{
+	mnStatusReg fld;
+	fld.cpm.AtTargetVel = true;
+	return Node().Status.Rise.TestAndClear(fld);
+}
+
+
+bool CPMmotion::VelocityAtTarget()
+{
+	Node().Status.RT.Refresh();
+	return Node().Status.RT.Value().cpm.AtTargetVel;
+}
+
+bool CPMmotion::MoveWentDone()
+{
+	mnStatusReg fld;
+	fld.cpm.MoveDone = true;
+	return Node().Status.Rise.TestAndClear(fld);
+}
+
+
+bool CPMmotion::MoveIsDone()
+{
+	Node().Status.RT.Refresh();
+	return Node().Status.RT.Value().cpm.MoveDone;
+}
+
+bool CPMmotion::WentNotReady()
+{
+	mnStatusReg fld, result;
+	fld.cpm.NotReady = true;
+
+	return Node().Status.Rise.TestAndClear(fld);
+}
+
+bool CPMmotion::IsReady()
+{
+	Node().Status.RT.Refresh();
+	return !Node().Status.RT.Value().cpm.NotReady;
+}
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Motion Canceling Group
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+/**
+\copydoc IMotion::NodeStop(nodeStopCodes)
+**/
+void CPMmotion::NodeStop(nodeStopCodes howToStop)
+{
+	cnErrCode theErr = netNodeStop(Node().Info.Ex.Addr(), howToStop, false);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**
+\copydoc IMotion::NodeStop(mgNodeStopReg)
+**/
+void CPMmotion::NodeStop(mgNodeStopReg &howToStop)
+{
+	cnErrCode theErr = netNodeStop(Node().Info.Ex.Addr(), howToStop.bits, false);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**
+\copydoc IMotion::GroupNodeStop(nodeStopCodes)
+**/
+void CPMmotion::GroupNodeStop(nodeStopCodes howToStop)
+{
+	for (Uint16 iNode = 0; iNode < m_pNode->Port.NodeCount(); iNode++) {
+		cnErrCode theErr = netNodeStop(m_pNode->Port.Nodes(iNode).Info.Ex.Addr(), howToStop, false);
+		if (theErr != MN_OK) {
+			mnErr eInfo;
+			fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+	}
+}
+
+/**
+\copydoc IMotion::NodeStopClearC
+**/
+void CPMmotion::NodeStopClear()
+{
+	cnErrCode theErr = netNodeStop(Node().Info.Ex.Addr(), 
+						STOP_TYPE_CLR_ALL, false);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**		
+	\copydoc IMotion::AddToPosition
+**/
+void CPMmotion::AddToPosition(double adjAmount)
+{
+	cnErrCode theErr = cpmAddToPosition(Node().Info.Ex.Addr(), adjAmount);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMmotionAdv Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+
+
+double CPMmotionAdv::MovePosnHeadTailDurationMsec(int32_t target,
+	bool targetIsAbsolute,
+	bool hasHead, bool hasTail)
+{
+	double retVal = IMotionAdv::MovePosnHeadTailDurationMsec(target, 
+		targetIsAbsolute, hasHead, hasTail);
+	retVal += Node().Info.Ex.Parameter(CPM_P_DRV_MV_DN_TC);
+	return retVal;
+}
+
+double CPMmotionAdv::MovePosnAsymDurationMsec(int32_t target,
+	bool targetIsAbsolute)
+{
+	double retVal = IMotionAdv::MovePosnAsymDurationMsec(target, 
+		targetIsAbsolute);
+	retVal += Node().Info.Ex.Parameter(CPM_P_DRV_MV_DN_TC);
+	return retVal;
+}
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+// Motion Initiating Group
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
+/**
+**/
+
+/**		
+	\copydoc IMotionAdv::MovePosnHeadTailStart
+**/
+size_t CPMmotionAdv::MovePosnStart(int32_t target,
+	bool targetIsAbsolute,
+	bool isTriggered, bool hasDwell)
+{
+	return MovePosnHeadTailStart(target, targetIsAbsolute, isTriggered, 
+							 false, false, hasDwell);
+}
+
+size_t CPMmotionAdv::MovePosnHeadTailStart(int32_t target, 
+							bool targetIsAbsolute,
+							bool isTriggered,
+						    bool hasHead, bool hasTail, bool hasDwell)
+{
+	int32_t bufsLeft = 0;
+	mgPosnStyle theStyle;
+	theStyle.fld.wait = isTriggered;
+	theStyle.fld.head = hasHead;
+	theStyle.fld.tail = hasTail;
+	theStyle.fld.relative = !targetIsAbsolute;
+	theStyle.fld.dwell = hasDwell;
+	cnErrCode theErr = cpmForkPosnMove(Node().Info.Ex.Addr(), target,
+									  theStyle, &bufsLeft);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return bufsLeft;
+}
+
+
+/**		
+	\copydoc IMotionAdv::MovePosnAsymStart
+**/
+size_t CPMmotionAdv::MovePosnAsymStart(int32_t target, 
+							bool targetIsAbsolute,
+							bool isTriggered,
+							bool hasDwell)
+{
+	int32_t bufsLeft = 0;
+	mgPosnStyle theStyle;
+	theStyle.fld.wait = isTriggered;
+	theStyle.fld.asym = true;
+	theStyle.fld.relative = !targetIsAbsolute;
+	theStyle.fld.dwell = hasDwell;
+	cnErrCode theErr = cpmForkPosnMove(Node().Info.Ex.Addr(), target,
+									   theStyle, &bufsLeft);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return bufsLeft;
+}
+
+/**		
+	\copydoc IMotionAdv::MoveVelStart
+**/
+size_t CPMmotionAdv::MoveVelStart(double target, 
+								 bool isTriggered)
+{
+	int32_t bufsLeft = 0;
+	// This is safe as CPMmotion always back point to a CPMnode instance
+	CPMnode &myNode = static_cast<CPMnode &>(Node());
+	cnErrCode theErr = cpmForkVelMove(Node().Info.Ex.Addr(),
+									  target/myNode.velScale(),
+									  isTriggered, &bufsLeft);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr,  _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return bufsLeft;
+}
+
+// Triggering waiting moves
+/**		
+	\copydoc IMotionAdv::TriggerMove
+**/
+void CPMmotionAdv::TriggerMove()
+{
+	cnErrCode theErr = netTrigger(Node().Port.NetNumber(),
+								  nodeaddr(NODE_ADDR(Node().Info.Ex.Addr())),
+								  false);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**		
+	\copydoc IMotionAdv::TriggerMovesInMyGroup
+**/
+void CPMmotionAdv::TriggerMovesInMyGroup()
+{
+	mnAppConfigReg app = Node().Setup.Ex.App.Value();
+	cnErrCode theErr = netTrigger(Node().Port.NetNumber(),
+								  nodeaddr(app.cpm.TriggerGroup),
+								  true);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**
+	\copydoc IMotionAdv::TriggerGroup(size_t)
+**/
+void CPMmotionAdv::TriggerGroup(size_t groupNumber)
+{
+	if (groupNumber <= 3) {
+		cnErrCode theErr;
+		INode::UseMutex myMutex(Node());
+		double theVal;
+		theErr = netGetParameterDbl(Node().Info.Ex.Addr(),
+									mnParams(CPM_P_APP_CONFIG_REG), &theVal);
+		if (theErr == MN_OK) {
+			mnAppConfigReg app;
+			app.bits = nodeulong(theVal);
+			app.cpm.TriggerGroup = groupNumber;
+			theErr = netSetParameterDbl(Node().Info.Ex.Addr(),
+									mnParams(CPM_P_APP_CONFIG_REG),
+									double(app.bits));
+			if (theErr == MN_OK) {
+				Node().Setup.Ex.App.setNewVal(app);
+			}
+		}
+		return;
+	}
+	// Argument out of range
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, MN_ERR_BADARG, _TEK_FUNC_SIG_, "", "");
+}
+
+/**
+\copydoc IMotionAdv::TriggerGroup()
+**/
+size_t CPMmotionAdv::TriggerGroup()
+{
+	mnAppConfigReg app = Node().Setup.Ex.App.Value();
+	return app.cpm.TriggerGroup;
+}
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMmotionAudit Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+/**		
+	\copydoc IMotionAudit::Refresh()
+**/
+void CPMmotionAudit::Refresh()
+{
+	cnErrCode theErr;
+	theErr = netGetDataCollected(Node().Info.Ex.Addr(), &Results);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+/**
+\copydoc IMotionAudit::SelectTestPoint()
+**/
+
+void CPMmotionAudit::SelectTestPoint(enum _testPoints testPoint,
+								     double fullScale, double filterTCmsec)
+{
+	iscMonState setup;
+	setup.filterTC = filterTCmsec;
+	setup.gain = fullScale;
+	// The motion audit class should map the indices to the monTestPoints.
+	setup.var = monTestPoints(testPoint);
+	cnErrCode theErr;
+	theErr = iscSetMonitor(Node().Info.Ex.Addr(), 0, &setup);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+
+}
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//						CPMnode Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+void CPMnode::VelUnit(enum _velUnits newUnits)
+{
+	if (Info.NodeType() != UNKNOWN) {
+		mnErr eInfo;
+		double effDens;
+
+		switch (newUnits) {
+		case INode::COUNTS_PER_SEC:
+			m_velScaleToUser = 1;
+			break;
+		case INode::RPM:
+			effDens = Info.Ex.Parameter(CPM_P_CMD_CNTS_PER_REV);
+			m_velScaleToUser = 60. / effDens;
+			break;
+		default:
+			fillInErrs(eInfo, this, MN_ERR_BADARG, _TEK_FUNC_SIG_,
+				"Unknown velocity unit %d", newUnits);
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+		// Adjust the list of know values
+		std::vector<ValueDouble *>::iterator i;
+		for (i = m_velValues.begin(); i < m_velValues.end(); ++i) {
+			ValueDouble &v = **i;
+			v.Scale(m_velScaleToUser);
+		}
+	}
+	m_VelUnit = newUnits;
+}
+
+void CPMnode::AccUnit(enum _accUnits newUnits)
+{
+	if (Info.NodeType() != UNKNOWN) {
+		mnErr eInfo;
+		double effDens;
+		switch (newUnits) {
+		case INode::COUNTS_PER_SEC2:
+			m_accScaleToUser = 1;
+			break;
+		case INode::RPM_PER_SEC:
+			effDens = Info.Ex.Parameter(CPM_P_CMD_CNTS_PER_REV);
+			m_accScaleToUser = 60. / effDens;
+			break;
+		default:
+			fillInErrs(eInfo, this, MN_ERR_BADARG, _TEK_FUNC_SIG_,
+				"Unknown acceleration unit %d", newUnits);
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+		// Adjust the list of know values
+		std::vector<ValueDouble *>::iterator i;
+		for (i = m_accValues.begin(); i < m_accValues.end(); ++i) {
+			ValueDouble &v = **i;
+			v.Scale(m_accScaleToUser);
+		}
+	}
+	m_AccUnit = newUnits;
+}
+
+
+void CPMnode::TrqUnit(enum _trqUnits newUnits)
+{
+	if (Info.NodeType() != UNKNOWN) {
+		mnErr eInfo;
+		double limDbl;
+		switch (newUnits) {
+		case AMPS:
+			m_trqScaleToUser = 1;
+			break;
+		case PCT_MAX:
+			// Get scale, if basis is bad zero out scale to force 
+			// bad values.
+			limDbl = Info.Ex.Parameter(CPM_P_DRV_I_MAX);
+			if (limDbl > 0)
+				m_trqScaleToUser = 100. / limDbl;
+			else
+				m_trqScaleToUser = 0;
+
+			limDbl = Info.Ex.Parameter(CPM_P_DRV_ADC_MAX);
+			if (limDbl > 0)
+				m_adcTrqScaleToUser = 100. / limDbl;
+			else
+				m_adcTrqScaleToUser = 0;
+
+			m_rmsTrqScaleToUser = 1;
+			break;
+		default:
+			fillInErrs(eInfo, this, MN_ERR_BADARG, _TEK_FUNC_SIG_,
+				"Unknown torque unit %d", newUnits);
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+		// Adjust the list of know values
+		std::vector<ValueDouble *>::iterator i;
+		for (i = m_trqValues.begin(); i < m_trqValues.end(); ++i) {
+			ValueDouble &v = **i;
+			v.Scale(m_trqScaleToUser);
+		}
+		for (i = m_adcTrqValues.begin(); i < m_adcTrqValues.end(); ++i) {
+			ValueDouble &v = **i;
+			v.Scale(m_adcTrqScaleToUser);
+		}
+		for (i = m_rmsTrqValues.begin(); i < m_rmsTrqValues.end(); ++i) {
+			ValueDouble &v = **i;
+			v.Scale(m_rmsTrqScaleToUser);
+		}
+	}
+	m_TrqUnit = newUnits;
+}
+
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//						CPMouts Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+// Easy access to enable request
+/**
+\copydoc IOuts::EnableReq(bool)
+**/
+void CPMouts::EnableReq(bool newState)
+{
+	mnOutReg enbl;
+	enbl.cpm.EnableReq = 1;
+	if (newState)
+		User.Set(enbl);
+	else
+		User.Clear(enbl);
+}
+/**
+\copydoc IOuts::EnableReq()
+**/
+bool CPMouts::EnableReq()
+{
+	bool enbl = User.Value().cpm.EnableReq;
+	return enbl;
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMsetup Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMsetup::ConfigLoad
+//
+//	DESCRIPTION:
+/**
+\copydoc ISetup::ConfigLoad
+**/
+void CPMsetup::ConfigLoad(const char *filePath,
+						  bool doReset)
+{
+	cnErrCode theErr;
+	configFmts cfgFmt;
+	cfgFmt = doReset ? CLASSIC : CLASSIC_NO_RESET;
+	theErr = netConfigLoad(Node().Info.Ex.Addr(),
+							cfgFmt, filePath);
+	if (theErr == MN_OK)
+		return;
+	mnErr eInfo;
+	fillInErrs(eInfo, &Node(), theErr, _TEK_FUNC_SIG_, "");
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMsetup::ConfigSave
+//
+//	DESCRIPTION:
+/**
+\copydoc ISetup::ConfigSave
+**/
+void CPMsetup::ConfigSave(const char *filePath)
+{
+	cnErrCode theErr;
+	theErr = netConfigSave(Node().Info.Ex.Addr(),
+							CLASSIC, filePath);
+	if (theErr == MN_OK) return;
+	mnErr eInfo;
+	fillInErrs(eInfo, &Node(), theErr, _TEK_FUNC_SIG_, "");
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		CPMsetup::AccessLevelIsFull
+//
+//	DESCRIPTION:
+/**
+\copydoc ISetup::AccessLevelIsFull
+**/
+bool CPMsetup::AccessLevelIsFull()
+{
+	mnNetStatus accessLvl = SysInventory->AccessInfo[Node().Info.Ex.Addr()];
+	if ( (accessLvl.Fld.NetSource == MN_SRC_APP_NET && 
+		  accessLvl.Fld.NetAccessApp == MN_ACCESS_LVL_FULL) ||
+	     (accessLvl.Fld.NetSource == MN_SRC_DIAG_NET && 
+		  accessLvl.Fld.NetAccessDiag == MN_ACCESS_LVL_FULL) ){
+		return true;
+	}
+	else
+		return false;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMstatusAdv Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// CPMstatus Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+
+
+/**		
+	\copydoc IStatus::AlertsClear
+**/
+void CPMstatus::AlertsClear()
+{
+	cnErrCode theErr = netAlertClear(Node().Info.Ex.Addr());
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**
+	\copydoc IStatus::HadTorqueSaturation
+**/
+bool CPMstatus::HadTorqueSaturation()
+{
+	Warnings.Refresh();
+	alertReg satFld, result;
+	satFld.cpm.TrqSat = 1;
+	return (Warnings.TestAndClear(satFld, result));
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Constructor Implementations
+/// \cond INTERNAL_DOC	
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+CPMattnNode::CPMattnNode(INode &ourNode)
+	: IAttnNode(ourNode,
+		   CPM_P_ATTN_MASK, CPM_P_WARN_MASK, CPM_P_ALERT_MASK, 
+		   CPM_P_STATUS_EVENT_MASK)
+{
+
+}
+
+CPMnodeAdv::CPMnodeAdv(INode &ourNode) 
+	: INodeAdv(ourNode, m_audit, m_attnNode),
+	  m_audit(ourNode), m_attnNode(ourNode)
+{
+	
+}
+
+void CPMnodeAdv::Supported(bool newState) 
+{
+	IObj::Supported(newState);
+	m_audit.Supported(newState);
+	m_attnNode.Supported(newState);
+}
+
+CPMhoming::CPMhoming(INode &ourNode)
+	: IHoming(ourNode, 
+		CPM_P_APP_HOMING_ACCEL, CPM_P_APP_HOMING_VEL,
+		CPM_P_DRV_HARDSTOP_TRQ_LIM, CPM_P_APP_HOMING_OFFSET, 
+		CPM_P_APP_HOMING_DELAY)
+{
+	Supported(true);
+}
+
+CPMinfo::CPMinfo(INode &ourNode) 
+	: IInfo(ourNode, m_advInfo, m_exInfo,
+		CPM_P_SER_NUM, CPM_P_FW_VERS, CPM_P_USER_RAM0,
+		m_userID, m_hwVersion, m_fwVersion, m_model, CPM_P_CMD_CNTS_PER_REV),
+	m_advInfo(ourNode), m_exInfo(ourNode),
+	m_userID(ourNode, 0, ValueString::STR_USERID),
+	m_fwVersion(ourNode, 0, ValueString::STR_FW_VERSION),
+	m_hwVersion(ourNode, 0, ValueString::STR_HW_VERSION),
+	m_model(ourNode, 0, ValueString::STR_MODEL_STR)
+{
+	m_nodeType = UNKNOWN;
+	Supported(true);
+}
+
+CPMinfoAdv::CPMinfoAdv(INode &ourNode) 
+	: IInfoAdv(ourNode)
+{
+	Supported(true);
+}
+
+CPMinfoEx::CPMinfoEx(INode &ourNode)
+	: IInfoEx(ourNode)
+{
+	Supported(true);
+}
+
+CPMlimits::CPMlimits(INode &ourNode)
+	: ILimits(ourNode, m_adv,
+		CPM_P_DRV_TRQ_LIM, CPM_P_POSN_TRK_ERR_LIM,
+		CPM_P_USER_SOFT_LIM_POSN_1, CPM_P_USER_SOFT_LIM_POSN_2,
+		CPM_P_DRV_MTR_SPEED_LIM),
+	m_adv(ourNode)
+{
+	Supported(true);
+}
+
+CPMlimitsAdv::CPMlimitsAdv(INode &ourNode)
+	: ILimitsAdv(ourNode,
+		CPM_P_DRV_POS_FLDBK_TRQ, CPM_P_DRV_POS_FLDBK_TRQ_TC,
+		CPM_P_DRV_NEG_FLDBK_TRQ, CPM_P_DRV_NEG_FLDBK_TRQ_TC)
+{
+	
+}
+
+CPMmotion::CPMmotion(INode &ourNode) 
+	: IMotion(ourNode, m_adv, m_homing,
+				CPM_P_ACC_LIM, CPM_P_VEL_LIM, CPM_P_STOP_ACC_LIM, 
+				CPM_P_POSN_MEAS, CPM_P_POSN_CMD, CPM_P_POSN_TRK,
+				CPM_P_VEL_MEAS, CPM_P_VEL_CMD, 
+				CPM_P_DRV_TRQ_MEAS, CPM_P_DRV_TRQ_CMD,
+				CPM_P_JERK_LIM, CPM_P_MOVE_DWELL, CPM_P_APP_RAS_DELAY),
+	m_adv(ourNode), 
+	m_homing(ourNode)
+{
+	Supported(true);
+	VelCommanded.IsVolatile(true);
+	VelMeasured.IsVolatile(true);
+	PosnCommanded.IsVolatile(true);
+	PosnMeasured.IsVolatile(true);
+	PosnTracking.IsVolatile(true);
+	TrqCommanded.IsVolatile(true);
+	TrqMeasured.IsVolatile(true);
+	JrkLimitDelay.IsVolatile(true);
+}
+
+CPMmotionAdv::CPMmotionAdv(INode &ourNode) 
+	: IMotionAdv(ourNode,
+		CPM_P_DEC_LIM, CPM_P_HEADTAIL_VEL, 
+		CPM_P_HEAD_DISTANCE, CPM_P_TAIL_DISTANCE, CPM_P_A_START,
+		CPM_P_B_END)
+{
+	
+}
+
+
+CPMmotionAudit::CPMmotionAudit(INode &ourNode) 
+	: IMotionAudit(ourNode)
+{
+	
+}
+
+
+CPMnodeEx::CPMnodeEx(INode &ourNode)
+	: INodeEx(ourNode)
+{
+
+}
+
+
+CPMouts::CPMouts(INode &ourNode) 
+	: IOuts(ourNode,
+		CPM_P_USER_OUT_REG, CPM_P_OUT_REG)
+{
+	Supported(true);
+	Out.IsVolatile(true);
+}
+
+CPMouts::~CPMouts()
+{
+}
+
+CPMsetup::CPMsetup(INode &ourNode)
+	: ISetup(ourNode, CPM_P_APP_CONFIG_REG, CPM_P_HW_CONFIG_REG, 
+			CPM_P_WATCHDOG_TIME, CPM_P_DLY_TO_DISABLE)
+{
+
+}
+
+CPMstatus::CPMstatus(INode &ourNode) 
+	: IStatus(ourNode, m_adv, 
+			  CPM_P_STATUS_RT_REG, CPM_P_STATUS_RISE_REG, 
+			  CPM_P_STATUS_FALL_REG, CPM_P_STATUS_ACCUM_REG,
+			  CPM_P_WARN_REG, CPM_P_ALERT_REG, CPM_P_DRV_RMS_LVL,
+			  CPM_P_POWER_REG), 
+	  m_adv(ourNode)
+{
+	Supported(true);
+	RT.IsVolatile(true);
+	Rise.IsVolatile(true);
+	Fall.IsVolatile(true);
+	Accum.IsVolatile(true);
+	Alerts.IsVolatile(true);
+	Warnings.IsVolatile(true);
+	RMSlevel.IsVolatile(true);
+	Power.IsVolatile(true);
+	Power.Supported(ourNode.Info.NodeType() != UNKNOWN && ourNode.Info.FirmwareVersionCode.Value() >= FW_MILESTONE_PWR);
+}
+
+CPMstatusAdv::CPMstatusAdv(INode &ourNode) 
+	: IStatusAdv(ourNode, CPM_P_POSN_CAP_INA_HI_SPD, CPM_P_POSN_CAP_INB)
+{
+	CapturedHiResPosn.IsVolatile(true);
+	CapturedPos.IsVolatile(true);
+}
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//						CPMnodeEx Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+/**
+\copydoc INodeEx::MutexTake
+**/
+void CPMnodeEx::MutexTake()
+{
+	ParamLockMutex[Node().Port.NetNumber()]
+				  [NODE_ADDR(Node().Info.Ex.Addr())].Lock();
+}
+
+/**
+\copydoc INodeEx::MutexRelease
+**/
+void CPMnodeEx::MutexRelease()
+{
+	ParamLockMutex[Node().Port.NetNumber()]
+				  [NODE_ADDR(Node().Info.Ex.Addr())].Unlock();
+}
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//						CPMattnNode Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+/**
+\copydoc IAttnNode::AttnRegister
+**/
+void CPMattnNode::AttnRegister()
+{
+	netaddr netNum = Node().Port.NetNumber();
+	int nodeNum = NODE_ADDR(Node().Info.Ex.Addr());
+
+	infcSleep(0);
+	AttnEvtMutex[netNum][nodeNum].Lock();
+
+}
+
+/**
+\copydoc IAttnNode::AttnUnregister
+**/
+void CPMattnNode::AttnUnregister()
+{
+	netaddr netNum = Node().Port.NetNumber();
+	int nodeNum = NODE_ADDR(Node().Info.Ex.Addr());
+
+	AttnEvtMutex[netNum][nodeNum].Unlock();
+}
+
+/**
+\copydoc IAttnNode::AttnWait
+**/
+bool CPMattnNode::AttnWait(size_t timeoutMs)
+{
+	bool retVal;
+	netaddr netNum = Node().Port.NetNumber();
+	int nodeNum = NODE_ADDR(Node().Info.Ex.Addr());
+	
+
+	AttnCntMutex[netNum][nodeNum].Lock();
+	AttnListenerCnt[netNum][nodeNum]++;
+	AttnCntMutex[netNum][nodeNum].Unlock();
+
+	AttnEvtMutex[netNum][nodeNum].Unlock();
+
+	retVal = AttnEvent[netNum][nodeNum].WaitFor(unsigned(timeoutMs));
+
+	AttnCntMutex[netNum][nodeNum].Lock();
+
+	AttnListenerCnt[netNum][nodeNum]--;
+	if (retVal && AttnListenerCnt[netNum][nodeNum] == 0){
+		AttnEvent[netNum][nodeNum].ResetEvent();
+	}
+	AttnCntMutex[netNum][nodeNum].Unlock();
+	infcSleep(0);
+	AttnEvtMutex[netNum][nodeNum].Lock();
+
+	return retVal;
+}
+
+/**
+\copydoc IAttnNode::AttnSignal
+**/
+void CPMattnNode::AttnSignal()
+{
+
+	netaddr netNum = Node().Port.NetNumber();
+	int nodeNum = NODE_ADDR(Node().Info.Ex.Addr());
+	
+	AttnCntMutex[netNum][nodeNum].Lock();
+
+	if (AttnListenerCnt[netNum][nodeNum]){
+		AttnEvent[netNum][nodeNum].SetEvent();
+	}
+	AttnCntMutex[netNum][nodeNum].Unlock();
+}
+
+
+// NODE 
+CPMnode::CPMnode(IPort &port, multiaddr theAddr)
+	: INode(port, theAddr, m_info, m_motion, m_status, m_limits, m_outs, m_adv, 
+			m_setup, m_ex),
+	m_motion(*this),
+	m_status(*this), 
+	m_limits(*this),
+	m_outs(*this),
+	m_setup(*this),
+	m_adv(*this),
+	m_ex(*this),
+	m_info(*this)
+{
+	// Setup advanced API items
+	Refresh();
+
+	AttnListenerCnt[port.NetNumber()][NODE_ADDR(theAddr)] = 0;
+
+	// Build up our list of acceleration items.
+	m_accValues.push_back(&m_motion.AccLimit);
+	m_accValues.push_back(&m_motion.NodeStopDecelLim);
+	m_accValues.push_back(&m_motion.Adv.DecelLimit);
+	
+	// Build up our list of velocity items.
+	m_velValues.push_back(&m_motion.VelLimit);
+	m_velValues.push_back(&m_motion.VelCommanded);
+	m_velValues.push_back(&m_motion.VelMeasured);
+	m_velValues.push_back(&m_motion.Adv.HeadTailVelLimit);
+	m_velValues.push_back(&m_limits.MotorSpeedLimit);
+
+	// Build up our list of torque items.
+	m_trqValues.push_back(&m_motion.TrqCommanded);
+	m_trqValues.push_back(&m_motion.TrqMeasured);
+	m_trqValues.push_back(&m_limits.TrqGlobal);
+	m_trqValues.push_back(&m_limits.Adv.NegativeTrq);
+	m_trqValues.push_back(&m_limits.Adv.PositiveTrq);
+
+	// RMS level / RMS limit setting
+	m_rmsTrqValues.push_back(&m_status.RMSlevel);
+
+
+	// Establish unit scalings
+	AccUnit(INode::RPM_PER_SEC);
+	VelUnit(INode::RPM);
+	TrqUnit(INode::PCT_MAX);
+}
+
+void CPMnode::Refresh() 
+{
+	if ((Port.OpenState() == OPENED_ONLINE || Port.OpenState() == OPENED_SEARCHING) 
+		&& Port.NodeCount() > nodeaddr(NODE_ADDR(Info.Ex.Addr()))) {
+		// Setup advanced API items
+		optionReg myOptions;
+		myOptions.bits = nodeulong(m_info.Ex.Parameter(MN_P_OPTION_REG));
+		if (myOptions.cpm.Advanced) {
+			m_info.NodeType(IInfo::CLEARPATH_SC_ADV);
+		}
+		else {
+			m_info.NodeType(IInfo::CLEARPATH_SC);
+		}
+
+		m_adv.Supported(myOptions.cpm.Advanced);
+		m_limits.Adv.Supported(myOptions.cpm.Advanced);
+		// Get the user ID for potential error messages later while node 
+		// appears to be online.
+		m_info.UserID.Refresh();
+		Status.Power.Supported(Info.FirmwareVersionCode.Value() >= FW_MILESTONE_PWR);
+		// Update unit scalings
+		AccUnit(m_AccUnit);
+		VelUnit(m_VelUnit);
+		TrqUnit(m_TrqUnit);
+	}
+	else {
+		m_info.NodeType(IInfo::UNKNOWN);
+	}
+}
+
+// END OF INTERNAL_DOC
+/// \endcond
+//																			  *
+//*****************************************************************************
+
+
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// SysCPMport Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+/**
+	\copydoc IPort::NodeCount
+**/
+Uint16 SysCPMport::NodeCount() 
+{
+	return SysInventory[m_netNumber].InventoryNow.NumOfNodes;
+}
+
+/**
+	\copydoc IPort::OpenState
+**/
+openStates SysCPMport::OpenState() 
+{
+	return SysInventory[m_netNumber].OpenState;
+}
+
+/**
+	\copydoc IPort::WaitForOnline
+**/
+bool SysCPMport::WaitForOnline(int32_t timeoutMs) 
+{
+	double endTime = infcCoreTime() + timeoutMs;
+	
+	while (infcCoreTime() < endTime) {
+		if (SysInventory[m_netNumber].OpenState == OPENED_ONLINE){
+			return true;
+		}
+		infcSleep(100);
+	}
+
+	return (SysInventory[m_netNumber].OpenState == OPENED_ONLINE);
+}
+
+/**
+	\copydoc IPort::RestartCold
+**/
+void SysCPMport::RestartCold() 
+{
+	cnErrCode theErr = mnRestartNet(NetNumber(), true);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+			"Failure to restart network %d", NetNumber());
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+
+/**
+	\copydoc IPort::NodeStop
+**/
+void SysCPMport::NodeStop(mgNodeStopReg stopType)
+{
+	// This is the network form of high-priority note stops, 
+	// create fake address to allow function to extract controller number.
+	cnErrCode theErr = netNodeStop(MULTI_ADDR(NetNumber(), 0), stopType, true);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+			"Failure to issue network %d node stop type 0x%x", 
+			NetNumber(), stopType.bits);
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+/**
+	\copydoc IPort::CommandTraceSave
+**/
+void SysCPMport::CommandTraceSave(const char *filePath)
+{
+	cnErrCode theErr = infcTraceDumpA(NetNumber(), filePath);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+			"Failure to create dump file %s for net %d", 
+			filePath, NetNumber());
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// SysCPMportAdv Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+/**
+\copydoc IPortAdv::TriggerMovesInGroup
+**/
+void SysCPMportAdv::TriggerMovesInGroup(size_t groupNumber)
+{
+	cnErrCode theErr = netTrigger(m_pPort->NetNumber(), 
+								  nodeaddr(groupNumber), true);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_, 
+			"Failure to trigger moves in group %d on network %d",
+			groupNumber, m_pPort->NetNumber());
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// SysCPMattnPort Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+void SysCPMattnPort::Enable(bool newState)
+{
+	AttnsEnabled = newState;
+}
+
+bool SysCPMattnPort::Enabled()
+{
+	return AttnsEnabled;
+}
+
+IAttnPort::attnState SysCPMattnPort::WaitForAttn(mnAttnReqReg &attnRecvd)
+{
+	cnErrCode theErr;
+	mnErr eInfo;
+
+	// They have disabled our processing of attentions
+	if (!AttnsEnabled) {
+		// Spin-out prevention as well as fielding any in route
+		// attentions. 
+		infcSleep(100);
+		// Keep killing buffer
+		theErr = infcNetAttnFlush(m_pPort->NetNumber());
+		if (theErr != MN_OK) {
+			fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+				"Attention flush critically failed");
+			//throw eInfo;
+			throwSystemError(eInfo);
+		}
+		return IAttnPort::DISABLED;
+	}
+
+	// Wait for next attention or time-out
+	theErr = infcNetGetAttnReq(m_pPort->NetNumber(), &attnRecvd);
+	switch (theErr) {
+	case MN_OK:
+		return IAttnPort::HAS_ATTN;
+	case MN_ERR_TIMEOUT:
+		return IAttnPort::TIMEOUT;
+	case MN_ERR_ATTN_OVERRUN:
+	default:
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+			"Wait for attention critically failing");
+		//throw eInfo;
+		throwSystemError(eInfo);
+		break;
+	};
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// SysCPMgrpShutdown Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+void SysCPMgrpShutdown::ShutdownWhen(size_t nodeIndex, const ShutdownInfo &theInfo)
+{
+	multiaddr theAddr = MULTI_ADDR(m_pPort->NetNumber(), nodeIndex);
+	cnErrCode theErr = infcShutdownInfoSet(theAddr, &theInfo);
+	if (theErr == MN_OK) return;
+	mnErr eInfo;
+	fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+		"Failed to setup group shutdown for node %d on port %d",
+		nodeIndex, m_pPort->NetNumber());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+void SysCPMgrpShutdown::ShutdownWhenGet(size_t nodeIndex, ShutdownInfo &theInfo)
+{
+	multiaddr theAddr = MULTI_ADDR(m_pPort->NetNumber(), nodeIndex);
+	cnErrCode theErr = infcShutdownInfoGet(theAddr, &theInfo);
+	if (theErr == MN_OK) return;
+	mnErr eInfo;
+	fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+		"Failed to get group shutdown information for node %d on port %d",
+		nodeIndex, m_pPort->NetNumber());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+void SysCPMgrpShutdown::ShutdownInitiate()
+{
+	cnErrCode theErr = infcShutdownInitiate(m_pPort->NetNumber());
+	if (theErr == MN_OK) return;
+	mnErr eInfo;
+	fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+		"Failed to initiate group shutdown on port %d",
+		m_pPort->NetNumber());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+bool SysCPMgrpShutdown::GetGlobalStop()
+{
+	nodebool nBool;
+	cnErrCode theErr = infcGlobalStopGet(
+		m_pPort->NetNumber(), &nBool);
+	return nBool != 0;
+}
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// SysCPMbrakeControl Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+/**
+	\copydoc IBrakeControl::BrakeSetting(size_t, BrakeControls)
+**/
+void SysCPMbrakeControl::BrakeSetting(size_t brakeNum, BrakeControls brakeMode)
+{
+	cnErrCode theErr = infcBrakeControlSet(
+			m_pPort->NetNumber(), brakeNum, brakeMode);
+	if (theErr == MN_OK) return;
+	mnErr eInfo;
+	fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+		"Failed override brake %d on port %d",
+		brakeNum, m_pPort->NetNumber());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+	\copydoc IBrakeControl::BrakeControl(size_t)
+**/
+BrakeControls SysCPMbrakeControl::BrakeSetting(size_t brakeNum)
+{
+	BrakeControls theState;
+	cnErrCode theErr = infcBrakeControlGet(
+			m_pPort->NetNumber(), brakeNum, &theState);
+	if (theErr == MN_OK) return theState;
+	mnErr eInfo;
+	fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_,
+		"Failed get override state for brake %d on port %d",
+		brakeNum, m_pPort->NetNumber());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+/**
+	\copydoc IBrakeControl::BrakeEngaged(size_t)
+**/
+bool SysCPMbrakeControl::BrakeEngaged(size_t brakeNum) 
+{
+	nodebool nBool;
+	/*cnErrCode theErr =*/ infcBrakeGet(
+		m_pPort->NetNumber(), brakeNum, &nBool);
+	return nBool != 0;
+}
+//============================================================================= 
+//	END OF FILE cpmClassImpl.cpp
+//=============================================================================
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/iscAPI.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/iscAPI.cpp
new file mode 100644
index 000000000..0ef5d5d7c
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/iscAPI.cpp
@@ -0,0 +1,4396 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/iscAPI.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: iscAPI.cpp $
+//
+// DESCRIPTION:
+/**
+	\file
+	\cond ISC_DOC
+	\brief ISC Programming Interface Implementation.
+
+	\defgroup ISCgrp ISC Programming Interface
+	\brief Functions related to Integrated Servo Controller (ISC) functionality.
+
+	Provides:
+		- checking on the operation state of the node
+		- initiating and canceling motion
+		- accessing and programming the Programmable Logic Array (PLA)
+		- accessing and changing I/O
+		- accessing and modifying the parameter table
+
+	\remark C and C++ Applications should include the master header file
+	\c meridianHdrs.h in the source code to insure the various function
+	prototypes and data types are available for your application.
+
+	@{
+**/		
+//
+// CREATION DATE:
+//		6/6/2009 refactored from ControlPoint iscCmds.c
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+// NAME																          *
+// 	 iscAPI.cpp headers
+//
+/// \cond	INTERNAL_DOC
+ 	#include <stdlib.h>
+ 	#include <malloc.h>
+	#include <assert.h>
+	#include <stdint.h>
+	#include <math.h>
+/// \endcond
+#if 1  // TO_KILL was used to test header file issues
+	#include "pubCoreRegs.h"
+	#include "pubNetAPI.h"
+	#include "netCmdPrivate.h"
+	#include "converterLib.h"
+	#include "netCmdAPI.h"
+	#include "sFoundResource.h"
+	#include "iscRegs.h"
+	#include "pubIscAPI.h"
+/// \cond	INTERNAL_DOC
+	#include "lnkAccessCommon.h"
+#if defined(_WIN32) || defined(_WIN64)
+	#include <crtdbg.h>
+#endif
+#if (defined(_MSC_VER))
+	#pragma warning(disable:4996)
+#else
+	#include <string.h>
+#endif
+#if defined (__GNUC__)
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+/// \endcond																  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	 iscAPI.cpp function prototypes
+//
+/// \cond INTERNAL_DOC
+#define Sgn(x) (((x)>0) ? 1 : (((x)==0) ? 0 : -1))
+#define Q15_MAX (32767./32768.)
+// Module private functions
+
+// Buffer management items
+static cnErrCode MN_DECL waitForMoveBuffer(
+			multiaddr theMultiAddr);			// Node to access
+// "Class" constructor
+cnErrCode iscClassSetup(multiaddr theMultiAddr);
+// "Class" destructors
+void iscClassDelete(multiaddr theMultiAddr);
+
+EXTERN_C paramscale VelScale;
+/// \endcond																  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	iscAPI.cpp imports
+//
+extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	iscAPI.cpp constants
+//
+/// \cond INTERNAL_DOC
+const double ISC_MON_SCALE = 1<<16; 	// Format of scale/ampl control
+const double ISC_MON_MAX_VEL = 8192;   	// Vel. full-scale (quads/sample-time)
+const double ISC_MON_MIN_VEL = 4;      	// Minimum velocity to display
+const double ISC_MON_MAX_POS_LEGACY = 8192;	// Position error full-scale
+const double ISC_MON_MAX_POS = 32768;		// Position error full-scale
+const double ISC_MON_MAX_POS_MEAS = (1<<20);
+const double ISC_MON_MAX_JRK = 0.000001;
+const double ISC_MON_MAX_INTG = 1UL<<31;
+#define ISC_ADC_SCALE (0.8*(double)(1<<13))	// ADC measure to torque values
+
+// RAS selector table						
+typedef struct _rasTarg {
+	double target;						// Optimal value
+	unsigned code;						// RAS code for this
+} rasTarg;
+
+#define ISC_MV_NEG_LIMIT  0x800000	// Largest negative move
+#define ISC_MV_POS_LIMIT  0x7FFFFF	// Largest positive move
+/// \endcond																  *
+//*****************************************************************************
+
+//==============================================================================
+/// \cond INTERNAL_DOC
+//	Internally documented functions from here to "END OF UNDOCUMENTED..."
+//==============================================================================
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Common unit converters
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+//*****************************************************************************
+//	NAME																	  *
+//		convertADCmax
+//
+//	DESCRIPTION:
+///		Conversion to and from ADC max parameter
+///
+/// 	\param xxx description
+///		\return description
+/// 
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+static double MN_DECL convertADCmax(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=> app bits
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// To/From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	double iMax;
+	cnErrCode theErr;
+	theErr = iscGetParameter(theMultiAddr, ISC_P_DRV_I_MAX, &iMax);
+	if (theErr==MN_OK) {
+		if (valIsBits) {
+			return(iMax/convVal);
+		}
+		else {
+			return(iMax/convVal);
+		}
+	}
+	return(0);
+}
+//																			  *
+//*****************************************************************************
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertAmperes
+ *
+ *	DESCRIPTION:
+ *		Convert a 1.15 type number into a fraction of I_MAX.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertAmperes(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue iMax;					// Full scale
+	double newInt;						// Temp variables
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_I_MAX, NULL, &iMax);
+	// The basis value is OK?
+	if (theErr != MN_OK || iMax.value <= 0)
+		return(0);
+
+	if (valIsBits)   {
+		// Convert to Amperes from the fraction of full scale
+		return(convVal * iMax.value);
+	}
+	else {
+		newInt = (convVal / iMax.value);
+		if (newInt > Q15_MAX) newInt = Q15_MAX;
+		return(newInt);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertMeasAmperes
+ *
+ *	DESCRIPTION:
+ *		Convert a 1.15 type number into a fraction of ADC_MAX.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertMeasAmperes(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,					// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue adcMax;					// Full scale
+	double newInt;						// Temp variables
+	cnErrCode theErr;
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ADC_MAX, NULL, &adcMax);
+	// The basis value is OK?
+	if (theErr != MN_OK || adcMax.value <= 0)
+		return(0);
+
+	if (valIsBits)   {
+		// Convert to Amperes from the fraction of full scale
+		return(convVal * adcMax.value);
+	}
+	else {
+		newInt = (convVal / adcMax.value);
+		if (newInt > Q15_MAX) newInt = Q15_MAX;
+		return(newInt);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertTripAmperes
+ *
+ *	DESCRIPTION:
+ *		Convert a 1.15 type number into a fraction of I_MAX.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+//static double MN_DECL convertTripAmperes(
+//	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+//	multiaddr theMultiAddr,				// Node address
+//	appNodeParam parameter,				// Target parameter
+//	double convVal,						// From value
+//	byNodeDB *pNodeDB)					// Parameter information
+//{
+//	paramValue globLim;					// Full scale
+//	double newVal;						// Temp variables
+//	cnErrCode theErr;
+//
+//	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_TRQ_LIM, NULL, &globLim);
+//	// The basis value is OK?
+//	if (theErr != MN_OK || globLim.value <= 0)
+//		return(0);
+//
+//	if (valIsBits)   {
+//		// Convert to Amperes from the fraction of full scale
+//		return(convVal * globLim.value);
+//	}
+//	else {
+//		newVal = (convVal / globLim.value);
+//		if (newVal > 1) newVal = 1;
+//		return(newVal);
+//	}
+//}
+///*																 !end!		*/
+///****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertFilt99pctMilliseconds
+ *
+ *	DESCRIPTION:
+ *		Convert IIR time constants from milliseconds to and from the 99% 
+ *		trip points.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertFilt99pctMilliseconds(
+	nodebool scaled, 					// TRUE=>milliseconds, FALSE=>unscaled
+	multiaddr theMultiAddr,					// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue sampleTime;
+	cnErrCode theErr;
+	nodelong intVal; double x;
+
+	const double TripPoint = 1-0.99;	// Trip point
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTime);
+	// Was it OK?
+	if (theErr != MN_OK && sampleTime.value <=0)
+		return(0);
+
+	if (scaled)  {
+		// Convert to milliseconds from base units
+		if (convVal > 32767 || convVal <=0)	
+			return(0);
+		return(.001*sampleTime.value * log(TripPoint)/log(convVal/32768.));
+	}
+	else {
+		// Convert to base units from milliseconds	
+		if (convVal <= 0) return(0);
+		x = pow(TripPoint, .001*sampleTime.value/convVal);
+		intVal = (nodelong)((32768.*x)+0.5);
+		if (intVal > 32767) intVal = 32767;
+		return(intVal);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertFilt1TCMilliseconds
+ *
+ *	DESCRIPTION:
+ *		Convert IIR time constants from milliseconds to and from the 99% 
+ *		trip points.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertFilt1TCMilliseconds(
+	nodebool scaled, 					// TRUE=>milliseconds, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue sampleTime;
+	cnErrCode theErr;
+	nodelong intVal; double x;
+
+	const double TripPoint = 0.367879;	// Trip point 1/e
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTime);
+	// Was it OK?
+	if (theErr != MN_OK && sampleTime.value <=0)
+		return(0);
+
+	if (scaled)  {
+		// Convert to milliseconds from base units
+		if (convVal > 32767 || convVal <=0)	
+			return(0);
+		return(.001*sampleTime.value * log(TripPoint)/log(convVal/32768.));
+	}
+	else {
+		// Convert to base units from milliseconds	
+		if (convVal <= 0) return(0);
+		x = pow(TripPoint, .001*sampleTime.value/convVal);
+		intVal = (nodelong)((32768.*x)+0.5);
+		if (intVal > 32767) intVal = 32767;
+		return(intVal);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+///*****************************************************************************
+// *	!NAME!
+// *		convertVectFilt99pctMilliseconds
+// *
+// *	DESCRIPTION:
+// *		Convert vector rate IIR time constants from milliseconds to and
+// *		from the 99% trip points.
+// *
+// *	\return
+// *		double
+// *
+// *	SYNOPSIS: 															    */
+//static double MN_DECL convertVectFilt99pctMilliseconds(
+//	nodebool scaled, 					// TRUE=>milliseconds, FALSE=>unscaled
+//	multiaddr theMultiAddr,					// Node address
+//	appNodeParam parameter,				// Target parameter
+//	double convVal,						// From value
+//	byNodeDB *pNodeDB)					// Parameter information
+//{
+//
+//	if (scaled)  {
+//		return convertFilt99pctMilliseconds(scaled, theMultiAddr, parameter, convVal, pNodeDB)/4;
+//	}
+//	else {
+//		return convertFilt99pctMilliseconds(scaled, theMultiAddr, parameter, convVal*4, pNodeDB);
+//	}
+//}
+///*																 !end!		*/
+///****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlevel
+ *
+ *	DESCRIPTION:
+ *		Convert RMS level from base units. This RMS level is a 
+ *		0 TO 100 value where 100 corresponds to the RMS shutdown point.	 This
+ *		converter does not need to convert to base units as it is a display
+ *		value only.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlevel(
+	nodebool scaled, 					// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue rmsLimit, adcMax;			// Basis information
+	double finalVal;
+	cnErrCode theErr;
+//                             %     Trq->A                 Q Factor
+//	const double CONST_FACT = 100 / (2^28) ^ 0.5
+//	const double CONST_FACT = 0.006103515625;
+	
+	// Maximum current
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK || adcMax.value == 0)
+		return(0);
+
+	// RMS maximum amperes
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_RMS_LIM, NULL, &rmsLimit);
+	if (theErr != MN_OK || rmsLimit.value == 0)
+		return(0);
+
+	if (convVal < 0 || convVal > 0x7FFFFFFF) 
+		return(0);
+		
+	// Convert to integer with rounding
+	//										      ADCmax
+	finalVal = (nodelong)(((100 * sqrt(convVal/(1<<28)) * adcMax.value) 
+				/ rmsLimit.value) + 0.5);
+
+	// Insure the numbers don't exceed the range
+	if (finalVal > 100) finalVal = 100;
+	if (finalVal < 0) finalVal = 0;
+	
+	//_RPT2(_CRT_WARN, "%.3f  %08x\n", finalVal, lVal);
+
+	return(finalVal);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertAmpsRMS
+ *
+ *	DESCRIPTION:
+ *		Convert RMS level from base units. This RMS level is returned
+ *		referenced to ADC max.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertAmpsRMS(
+	nodebool valIsBits, 				// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	paramValue adcMax;			// Basis information
+	double finalVal;
+	cnErrCode theErr;
+//                             %     Trq->A                 Q Factor
+//	const double CONST_FACT = 100 / (2^28) ^ 0.5
+	
+	// Maximum current
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK)
+		return(0);
+
+	if (valIsBits) {
+		// Prevent errors
+		if (convVal < 0) convVal = 0;
+		finalVal = (sqrt(convVal) * adcMax.value);
+	}
+	else {
+		finalVal = convVal / adcMax.value;
+		finalVal *= finalVal;
+	}
+	return(finalVal);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		convertMonGain
+//
+//	DESCRIPTION:
+//		Convert the monitor port gain setting to/from a full-scale range
+//		value.
+//
+//	\return
+//		double
+//
+//  SETUPS
+#if defined(__GNUC__)&&!defined(__QNX__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wswitch"
+#endif
+//
+//	SYNOPSIS:
+static double MN_DECL convertMonGain(
+	nodebool valIsBits, 				// TRUE=>scaled, FALSE=>unscaled
+	multiaddr theMultiAddr,				// Node address
+	iscMonVars theVar,					// The variable to adjust
+	double convVal)
+{
+	paramValue sampleTime, iMax, adcMax;
+	cnErrCode theErr;
+	double baseVal, fwVer;
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr addr = NODE_ADDR(theMultiAddr);
+	assert(SysInventory[cNum].NodeInfo[addr].pNodeSpecific != NULL);
+	iscState *pState = (iscState *)SysInventory[cNum].NodeInfo[addr].pNodeSpecific;
+	monState &monNow = pState->MonState; 
+	monNow.TestPoint = theVar;
+
+	// Assume failure until we get to the end
+	monNow.Set = false;
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_I_MAX, NULL, &iMax);
+	if (theErr != MN_OK)
+		return(0);
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr != MN_OK)
+		return(0);
+	if (iMax.value <=0 || adcMax.value <= 0)
+		return(0);
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTime);
+	if (fabs(sampleTime.value) < 0.001) 
+		// Protect from divide-by-zero
+		return(0);
+
+	if (valIsBits)  {
+		// Convert from fixed point
+		convVal /= ISC_MON_SCALE;
+	}
+	// Protect from \ 0
+	if (fabs(convVal) < 0.0001)  {
+		// Show as "off"
+		return(0);
+	}
+	// return the full scale value
+	switch (theVar) {
+		case MON_VEL_MEAS:
+		case MON_VEL_CMD:
+		case MON_VEL_TRK:
+		case MON_VEL_TRK_SERVO:
+		case 52:
+			// Return the monitor value in Hertz
+			baseVal = ((1e3*ISC_MON_MAX_VEL)
+			        / (sampleTime.value*convVal));
+			break;
+
+		case MON_VEL_STEP:
+			baseVal = (4e3*ISC_MON_MAX_VEL)
+			        / (sampleTime.value*convVal);
+			break;
+
+		case MON_JRK_CMD:
+			baseVal = (1e12*ISC_MON_MAX_VEL)
+					/ (pow(sampleTime.value,3) * convVal);
+			break;
+
+		case MON_ACC_CMD:
+			baseVal = (1e6*ISC_MON_MAX_VEL)
+					/ (sampleTime.value*sampleTime.value*convVal);
+			break;
+
+		case MON_POSN_TRK:
+		case MON_POSN_DIR_TRK:
+		case MON_TRK_LD:
+		case MON_POSN_DIR_TRK_MTR:
+		case MON_POSN_TRK_MTR:
+		case MON_COUPLING:
+			theErr = iscGetParameter(theMultiAddr, ISC_P_FW_VERSION, &fwVer);
+			if (theErr != MN_OK || fwVer < FW_MILESTONE_IEX)
+				baseVal = (ISC_MON_MAX_POS_LEGACY/convVal);
+			else
+				baseVal = (ISC_MON_MAX_POS/convVal);
+			break;
+
+		case MON_SINE_R:		// (2.14 format)
+		case MON_COS_R:
+			baseVal = (200/convVal);
+			break;
+
+		case MON_TRQ_MEAS:		// (1.15 format) scaled to trq amps
+		case MON_TRQ_MEAS_PEAK:
+		case MON_TRQ_D_MEAS:
+		case MON_TRQ_TRK:
+		case MON_TRQ_TRK_PEAK:
+			baseVal = (100*adcMax.value/iMax.value)/convVal;
+			break;
+
+		case MON_POSN_MEAS:
+		case 69:				// Position Cmd
+			baseVal = (ISC_MON_MAX_POS_MEAS/convVal);
+			break;
+
+		case MON_INTEGRATOR:
+			baseVal = (ISC_MON_MAX_INTG/convVal);
+			break;
+
+		case MON_SGN_CMD_VEL:
+		case MON_SGN_CMD_STEP:
+			baseVal = (100. / convVal);
+			break;
+
+		case MON_TRQ_CMD:		// (1.15 format)
+		case MON_CALIBRATE:
+		default:
+			baseVal = (100/convVal);
+			break;
+	}
+	if (!valIsBits) {
+		baseVal *= 0x10000;				// Scale to (16.16)
+		// Put at maximum number
+		if (baseVal > 0x7fffffff) baseVal = 0x7fffffff;
+		// Get rescaled value
+		monNow.FullScale = convertMonGain(true, theMultiAddr, theVar, baseVal); 
+		monNow.Set = true;
+	}
+	// Save our full scale value in user units
+	else {
+		monNow.FullScale = baseVal;
+		monNow.Set = true;
+	}
+	return(baseVal);
+}
+#if defined(__GNUC__)&&!defined(__QNX__)
+#pragma GCC diagnostic pop
+#endif
+/****************************************************************************/
+
+
+
+
+//****************************************************************************
+//	NAME
+//		convertAngle
+//
+//	DESCRIPTION:
+//		Convert to and from the commutation angle in encoder ticks to an
+//		angle in electrical degrees.
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+static double MN_DECL convertAngle(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=>mech degrees
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)
+{
+	paramValue poles, encDens, refOffs;
+	iscHwConfigReg hwConfig;
+
+	double ticksPerDegree, degreesPerTurn, rVal;
+	cnErrCode theErr;
+	
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_MTR_POLES, NULL, &poles);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ENC_DENS, NULL, &encDens);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_COM_RO, NULL, &refOffs);
+	if (theErr != MN_OK)
+		return(0);
+
+	theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+	if (theErr != MN_OK)
+		return(0);
+
+	degreesPerTurn = poles.value * 180.;
+	if (poles.value != 0) {
+		ticksPerDegree = encDens.value / degreesPerTurn;
+	}
+	else {
+		return(0);
+	}
+
+	if (valIsBits)  {
+		// Convert convVal to electrical degrees
+		rVal = convVal/ticksPerDegree-refOffs.value;
+		if (hwConfig.Fld.VectorLock) {
+			rVal += 90;
+		}
+		// Keep result between 0 and degreesPerTurn
+		if (rVal >= degreesPerTurn)
+			rVal -= degreesPerTurn;
+		if (rVal < 0)
+			 rVal += degreesPerTurn;
+		// Return the value 
+		return(rVal);
+	}
+	else {
+		// Convert convVal to drive bits
+		rVal = convVal + refOffs.value;
+		if (hwConfig.Fld.VectorLock)
+			rVal -= 90;
+		// Scale back to ticks
+		rVal *= ticksPerDegree;
+		// Bounds test the results between 0 and ticksPerTurn-1
+		if (rVal < 0)
+			rVal += ticksPerDegree*degreesPerTurn;
+		if (rVal >= ticksPerDegree*degreesPerTurn)
+			rVal -= ticksPerDegree*degreesPerTurn;
+		// Return the final value
+		return(((nodelong)(rVal+0.5)));
+	}	
+}
+/****************************************************************************/
+
+
+
+//****************************************************************************
+//	NAME
+//		convertKe
+//
+//	DESCRIPTION:
+//		Convert Ke to properly scaled value when using a linear motor.
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+static double MN_DECL convertKe(
+	nodebool valIsBits, 				// TRUE=>drive bits, FALSE=>msecs
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// To/From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	iscHwConfigReg hwConfig;
+	paramValue encRes, encDens;
+	cnErrCode theErr;
+	double cVal;
+
+	theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+	if (theErr != MN_OK)
+		return(0);
+
+	// The Encoder Density
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ENC_DENS, NULL, &encDens);
+	if (theErr != MN_OK)
+		return(0);
+	// The Encoder Resolution
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ENC_RES, NULL, &encRes);
+	if (theErr != MN_OK)
+		return(0);
+	cVal = ((1000.*encRes.value*encDens.value)/(60.*25400.));
+	// Make 
+	if (valIsBits) {
+		// conVal = drive bits (V/KRPM)
+		if (hwConfig.Fld.MotorType == iscHwConfigFlds::MOTOR_BRUSHLESS_LINEAR) {
+			// Convert V/Inches/sec => Rotational V/KRPM
+			if (cVal != 0)
+				return convVal/cVal;
+			else
+				return 0;
+		}
+		else {
+			return(convVal);
+		}
+	}
+	else {
+		// conVal = V/KRPM
+		if (hwConfig.Fld.MotorType == iscHwConfigFlds::MOTOR_BRUSHLESS_LINEAR) {
+			return convVal*cVal;
+		}
+		else {
+			return(convVal);
+		}
+	}
+}
+/****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlimit
+ *
+ *	DESCRIPTION:
+ *		Unit conversion to convert the RMS limit settings to and from the 
+ *		unscaled values.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlimit(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue adcMax;
+	cnErrCode theErr;
+	int rVal;
+
+	const double CONST_FACT = 1<<12; //(4.12 basis value)
+	const double TRQ_MAX_PCT = 0.9999;
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr == MN_OK) {
+		// Make sure the adcMax is reasonable
+		if (adcMax.value <= 0)
+			return(0);
+		// Make sure the value in is reasonable
+		if (convVal <= 0)		   
+			return(0);
+
+		// Get the maximum current 
+		if (valIsBits)
+			// Convert to RMS from unscaled
+			return(sqrt(convVal * adcMax.value * adcMax.value / CONST_FACT));
+		else {
+			// Convert RMS to unscaled value
+			if (convVal > adcMax.value)	
+				rVal = ((int)(CONST_FACT * 
+					  ((TRQ_MAX_PCT) * (TRQ_MAX_PCT))));
+			else
+				rVal = ((int)(CONST_FACT * 
+				           ((convVal / adcMax.value) * (convVal / adcMax.value))+0.5));
+			//_RPT2(_CRT_WARN, "ISC(%d) RMS LIM = 0x%x\n", theMultiAddr, rVal);
+			return(rVal);
+		}
+	}
+	return (0);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMSlimit
+ *
+ *	DESCRIPTION:
+ *		Unit conversion to convert the RMS limit settings to and from the 
+ *		unscaled values.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMSlimit32(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue adcMax;
+	cnErrCode theErr;
+	int rVal;
+	double nodeVers;
+
+	const double CONST_FACT = 1<<28; //(4.28 basis value)
+	const double TRQ_MAX_PCT = 0.9999;
+
+	theErr = iscGetParameter(theMultiAddr, ISC_P_FW_VERSION, &nodeVers);
+	if (theErr != MN_OK)
+		return(0);
+	// Prior to FW_MILESTONE_RMS_LIM_32, the RMS limit was 16 bits
+	if ( nodeVers < FW_MILESTONE_RMS_LIM_32 &&
+		(parameter.fld.bank == 1 && parameter.fld.param == (ISC_P_DRV_RMS_LIM&0x7f)) ) {
+		return convertRMSlimit(valIsBits, theMultiAddr, parameter, convVal, pNodeDB);
+	}
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_DRV_ADC_MAX, NULL, &adcMax);
+	if (theErr == MN_OK) {
+		// Make sure the adcMax is reasonable
+		if (adcMax.value <= 0)
+			return(0);
+		// Make sure the value in is reasonable
+		if (convVal <= 0)		   
+			return(0);
+
+		// Get the maximum current 
+		if (valIsBits)
+			// Convert to RMS from unscaled
+			return(sqrt(convVal * adcMax.value * adcMax.value / CONST_FACT));
+		else {
+			// Convert RMS to unscaled value
+			if (convVal > adcMax.value)	
+				rVal = ((int)(CONST_FACT * 
+					  ((TRQ_MAX_PCT) * (TRQ_MAX_PCT))));
+			else
+				rVal = ((int)(CONST_FACT * 
+				           ((convVal / adcMax.value) * (convVal / adcMax.value))+0.5));
+			//_RPT2(_CRT_WARN, "ISC(%d) RMS LIM = 0x%x\n", theMultiAddr, rVal);
+			return(rVal);
+		}
+	}
+	return (0);
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertRMStc
+ *
+ *	DESCRIPTION:
+ *		Convert RMS time constants to and from seconds and base units.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertRMStc(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue sampleTimeV;
+	cnErrCode theErr;
+	double b;
+	double retVal;
+
+	// Winding Amperes to torque Amperes factor
+	const int SCALE_FACT_Q = 23;              // Parameter window scale 
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD,	NULL, &sampleTimeV);
+	if (theErr != MN_OK)
+		return(0);
+	sampleTimeV.value *=  1e-6;		// Convert to seconds
+
+	// Make sure the sampleTime is reasonable
+	if (sampleTimeV.value == 0)
+		return(0);
+
+	// Insure problems return zero
+	retVal = 0;
+
+	// Convert TC to and from base units 
+	if (valIsBits)	 {
+		// Convert base to seconds
+		b = (1. - (convVal/(1<<SCALE_FACT_Q)));
+		if (b>0 && b<1)  {
+			b = log(b)/sampleTimeV.value;
+			if (b != 0)
+				retVal = log(8./9.)/b;	
+		}
+		//_RPT2(_CRT_WARN, "ISC(%d) RMS TC = %.3f\n", theMultiAddr, retVal);
+	}
+	else {
+		// Convert seconds to base units
+
+		// Enforce minimal values
+		if (convVal < 0.01) convVal = 0.01;
+		b = 1 - pow(8./9., (sampleTimeV.value/convVal));
+		retVal = (nodelong)((b*(1<<SCALE_FACT_Q)+.5));
+		// Prevent the value from turning "negative"
+		if (retVal > 32767) retVal = 32767;
+		//_RPT2(_CRT_WARN, "ISC(%d) RMS TC = 0x%x\n", theMultiAddr, retVal);
+	}
+	return (retVal);
+}
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		convertIBRMStc
+ *
+ *	DESCRIPTION:
+ *		Convert IB RMS time constants to and from seconds and base units.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+static double MN_DECL convertIBRMStc(
+	nodebool valIsBits, 			// TRUE=>RMS, FALSE=>unscaled
+	multiaddr theMultiAddr,			// Node address
+	appNodeParam parameter,			// Target parameter
+	double convVal,					// From value
+	byNodeDB *pNodeDB)				// Parameter information
+{
+	paramValue sampleTimeV;
+	cnErrCode theErr;
+	double b;
+	double retVal;
+
+	// Winding Amperes to torque Amperes factor
+	const int SCALE_FACT_Q = 23;              // Parameter window scale 
+
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD,	NULL, &sampleTimeV);
+	if (theErr != MN_OK)
+		return(0);
+	sampleTimeV.value *=  1e-6/4;		// Convert to seconds
+
+	// Make sure the sampleTime is reasonable
+	if (sampleTimeV.value == 0)
+		return(0);
+
+	// Insure problems return zero
+	retVal = 0;
+
+	// Convert TC to and from base units 
+	if (valIsBits)	 {
+		// Convert base to seconds
+		b = (1. - (convVal/(1<<SCALE_FACT_Q)));
+		if (b>0 && b<1)  {
+			b = log(b)/sampleTimeV.value;
+			if (b != 0)
+				retVal = log(8./9.)/b;	
+		}
+		if (retVal < 0.01) retVal = 0.01;
+		//_RPT2(_CRT_WARN, "ISC(%d) IB RMS TC = %.3f\n", theMultiAddr, retVal);
+	}
+	else {
+		// Convert seconds to base units
+
+		// Enforce minimal values
+		if (convVal < 0.01) convVal = 0.01;
+		b = 1 - pow(8./9., (sampleTimeV.value/convVal));
+		retVal = (nodelong)(b*(1<<SCALE_FACT_Q));
+		// Prevent the value from turning "negative"
+		if (retVal > 32767) retVal = 32767;
+		//_RPT2(_CRT_WARN, "ISC(%d) IB RMS TC = 0x%x\n", theMultiAddr, retVal);
+	}
+	return (retVal);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+// NAME																          *
+// 	iscAPI.cpp static variables
+//
+// The parameter handler table
+#if defined (__GNUC__)
+	#pragma GCC diagnostic ignored "-Wmissing-braces"
+	#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+#endif
+static const paramInfoLcl iscInfoDB[] = {
+// 		 1/x, signed, type,  unit,    size, scale,		config key id,			description, 			[converter]
+/* 0  */ { 0, 0, PT_RO,		DEV_ID,			2, 1<<8,	PARAM_NULL,				STR_PARAM_DEVID}, 	
+/* 1  */ { 0, 0, PT_RO,	 	FW_VERS,		2, 1<<12,	PARAM_NULL,				STR_PARAM_FWVERS}, 	
+/* 2  */ { 0, 0, PT_RO,	 	HW_VERS,		2, 1<<8,	PARAM_NULL,				STR_PARAM_HWVERS}, 	
+/* 3  */ { 0, 0, PT_RO,		BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_RESELLERID},
+/* 4  */ { 0, 0, PT_RO,	 	NO_UNIT, 		4, 1,		PARAM_SERIAL_NUMBER,	STR_PARAM_SERIAL_NUM}, 	
+/* 5  */ { 0, 1, PT_RO,	 	BIT_FIELD,		4, 1,		PARAM_OPTION_REG,		STR_PARAM_OPT_REG}, 	
+/* 6  */ { 0, 0, PT_NV_RW,	NO_UNIT, 		2, 1,		PARAM_ROM_UPD_ACK,		STR_PARAM_ROMSUM_ACK}, 	
+/* 7  */ { 0, 0, PT_RO,	 	NO_UNIT, 		2, 1,		PARAM_ROM_SUM,			STR_PARAM_FWSUM}, 	
+/* 8  */ { 0, 0, PT_RO,	 	TIME_USEC, 		4, 1000,	PARAM_SAMP_RATE,		STR_PARAM_SAMP_PER}, 	
+/* 9  */ { 0, 0, PT_RO_RT,	BIT_FIELD,	   12, 1,		PARAM_ALERT_REG,		STR_PARAM_ALERT_REG}, 	
+/* 10 */ { 0, 0, PT_NV_RW, 	NO_UNIT,		1, 1,		PARAM_STOP_TYPE,		STR_PARAM_STOPTYPE}, 	
+/* 11 */ { 0, 0, PT_VOL, 	TIME_SAMPLE,	2, 1,		PARAM_WATCHDOG_TIME,	STR_PARAM_WDTC,		    convertTimeMS}, 	
+/* 12 */ { 0, 0, PT_RO, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_PARAM_NETSTAT}, 	
+/* 13 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		6, 1,		PARAM_NULL,				STR_PARAM_STATUS}, 	
+/* 14 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		6, 1,		PARAM_NULL,				STR_PARAM_STATUS_ATTN_RISE}, 	
+/* 15 */ { 0, 0, PT_RAM, 	BIT_FIELD,ATTN_MASK_OCTETS, 1,PARAM_NULL,			STR_PARAM_ATTN_MASK}, 	
+/* 16 */ { 0, 0, PT_RO_RT, 	BIT_FIELD,		6, 1,		PARAM_NULL,				STR_PARAM_STATUS_RT}, 	
+/* 17 */ { 0, 0, PT_RO_RT, 	TIME_SAMPLE,	1, 1,		PARAM_NULL,				STR_PARAM_TIMESTAMP,	convertTimeMS}, 
+/* 18 */ { 0, 0, PT_RO_RT, 	TIME_SAMPLE,	2, 1,		PARAM_NULL,				STR_PARAM_TIMESTAMP16,	convertTimeMS}, 
+/* 19 */ { 0, 0, PT_RO, 	NO_UNIT,MN_PART_NUM_SIZE, 1,PARAM_PART_NUM,			STR_PARAM_PART_NUM},
+/* 20 */ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_EE_UPD_ACK,		STR_PARAM_EE_ACK},
+/* 21 */ { 0, 0, PT_RO,		NO_UNIT,		2, 1,		PARAM_EE_VER,			STR_PARAM_EE_VER}, 	
+/* 22 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		6, 1,		PARAM_NULL,				STR_PARAM_STATUS_FALL}, 	
+/* 23 */ { 0, 0, PT_NV_RW, 	BIT_FIELD,		4, 1,		PARAM_CFG_HW,			STR_PARAM_CFG_HW}, 	
+/* 24 */ { 0, 0, PT_NV_RW, 	BIT_FIELD,		4, 1,		PARAM_CFG_APP,			STR_PARAM_CFG_FEAT}, 	
+/* 25 */ { 0, 0, PT_NONE,	NO_UNIT,		2, 1,		PARAM_NULL,				STR_UNKNOWN},	
+/* 26 */ { 0, 0, PT_NONE,	NO_UNIT,		2, 1,		PARAM_NULL,				STR_UNKNOWN},	
+/* 27 */ { 0, 0, PT_NONE,	NO_UNIT,		2, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 28 */ { 0, 0, PT_NONE,	NO_UNIT,		2, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 29 */ { 0, 0, PT_NONE,	NO_UNIT,		2, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 30 */ { 0, 0, PT_VOL, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_USER_IN_REG}, 	
+/* 31 */ { 0, 0, PT_VOL, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_IN_SRC_REG}, 	
+/* 32 */ { 0, 0, PT_RO_RT, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_OUT_REG}, 	
+/* 33 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_OUT_RISE_REG}, 	
+/* 34 */ { 0, 0, PT_ROC_RT, BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_OUT_FALL_REG}, 	
+/* 35 */ { 0, 0, PT_NV_RW,  BIT_FIELD,		2, 1,		PARAM_NULL,				STR_CTL_STOP_OUT_REG}, 	
+/* 36 */ { 0, 0, PT_VOL, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_USER_OUT_REG}, 	
+/* 37 */ { 0, 0, PT_NV_RW, 	BIT_FIELD,		2, 1,		PARAM_OUT_SRC,			STR_PARAM_OUT_SRC_REG}, 	
+/* 38 */ { 0, 0, PT_RW_RT, 	TIME_SAMPLE,	2, 1,		PARAM_NULL,				STR_PARAM_GP_TIMER,		convertTimeMS}, 	
+/* 39 */ { 0, 0, PT_RO_RT, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_PLA_OUT_REG}, 	
+/* 40 */ { 0, 0, PT_NV_RW, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_PARAM_IN_POLARITY}, 	
+/* 41 */ { 0, 1, PT_NONE, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 42 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_INDEX_POSN_CAP}, 	
+/* 43 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_GPI0_POSN_CAP}, 	
+/* 44 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_PLA_POSN_CAP}, 	
+/* 45 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_P_POSN1_CAP_INDEX}, 	
+/* 46 */ { 0, 1, PT_RO_RT, 	VEL_TICK_SAMPLE,4, 1<<18,	PARAM_NULL,				STR_UNKNOWN,			convertVel},
+/* 47 */ { 0, 2, PT_NV_RW, 	VEL_TICK_SAMPLE,4, 1<<17,	PARAM_VEL_LIM,			STR_PARAM_VEL_LIMIT,	convertVel}, 	
+/* 48 */ { 0, 2, PT_NV_RW, 	VEL_TICK_SAMPLE2,4,1<<17,	PARAM_ACC_LIM,			STR_PARAM_ACC_LIMIT,	convertAcc},
+/* 49 */ { 0, 1, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_RASCON,			STR_PARAM_RAS_CON_REG},
+/* 50 */ { 0, 2, PT_RO_RT, 	VEL_TICK_SAMPLE2,4,1<<18,	PARAM_NULL,				STR_PARAM_ACC_MAX,		convertAcc},
+/* 51 */ { 0, 1, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_POSN_TRIG_PT},
+/* 52 */ { 0, 0, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_A_START},
+/* 53 */ { 0, 0, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_B_END},
+/* 54 */ { 0, 1, PT_NV_RW, 	DX_TICK,		2, 1,		PARAM_IN_RANGE_WIN,		STR_PARAM_POS_TRK_RNG},
+/* 55 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_CPL_ERR}, 	
+/* 56 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_PARAM_POSN_TRK},
+/* 57 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 58 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 59 */ { 0, 2, PT_NV_RW, 	VEL_TICK_SAMPLE2,4,1<<17,	PARAM_NULL,				STR_PARAM_STOPACC_LIM,	convertAcc},
+/* 60 */ { 0, 1, PT_RO_RT, 	DX_TICK,	    3, 1,		PARAM_NULL,				STR_PARAM_I_MEAS_POSN_MTR},
+/* 61 */ { 0, 1, PT_RO_RT, 	DX_TICK,		3, 1,		PARAM_NULL,				STR_PARAM_I_MEAS_POSN},
+/* 62 */ { 0, 1, PT_RO_RT, 	DX_TICK,		3, 1,		PARAM_NULL,				STR_PARAM_I_CMD_POSN},
+/* 63 */ { 0, 1, PT_RO_RT, 	VEL_TICK_SAMPLE,4, 1<<18,	PARAM_NULL,				STR_PARAM_CMD_VEL,		convertVel},
+/* 64 */ { 0, 1, PT_RO_RT, 	VEL_TICK_SAMPLE,4, 1<<18,	PARAM_NULL,				STR_PARAM_MEAS_VEL,		convertVel},
+/* 65 */ { 0, 0, PT_NV_RW, 	VEL_TICK_SAMPLE2,4,1<<17,	PARAM_DEC_LIM,			STR_PARAM_DEC_LIMIT,	convertAcc},
+/* 66 */ { 0, 0, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_HEAD_DX,			STR_PARAM_HEAD_DX},
+/* 67 */ { 0, 0, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_TAIL_DX,			STR_PARAM_TAIL_DX},
+/* 68 */ { 0, 0, PT_NV_RW, 	VEL_TICK_SAMPLE,4, 1<<17,	PARAM_HT_VEL_LIM,		STR_PARAM_HEADTAIL_VEL,	convertVel},	
+/* 69 */ { 0, 1, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_P_POSN1_MEAS32}, 	
+/* 70 */ { 0, 0, PT_ROC_RT, NO_UNIT,ALERTREG_SIZEOCTETS, 1,		PARAM_NULL,		STR_WARN_ACC}, 	
+/* 71 */ { 0, 0, PT_RAM, 	NO_UNIT,ALERTREG_SIZEOCTETS, 1,		PARAM_NULL,		STR_USER_WARN_MASK_REG}, 	
+/* 72 */ { 0, 0, PT_RAM, 	NO_UNIT,ALERTREG_SIZEOCTETS, 1,		PARAM_NULL,		STR_USER_ALERT_MASK_REG}, 	
+/* 73 */ { 0, 0, PT_ROC_RT, NO_UNIT,ALERTREG_SIZEOCTETS, 1,		PARAM_NULL,		STR_WARN_RT}, 	
+/* 74 */ { 0, 0, PT_RW_RT, 	TIME_SAMPLE,	2, 1,		PARAM_MOVE_DWELL,		STR_PARAM_DWELL,		convertTimeMS}, 	
+/* 75 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 76 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 77 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 78 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 79 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 80 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 81 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 82 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 83 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 84 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 85 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 86 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 87 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 88 */ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 89 */ { 0, 0, PT_RT, 	NO_UNIT,		4, 10.*60.*60.,	PARAM_NULL,			STR_ON_TIME}, 	// .1 Sec -> Hours
+/* 90 */ { 0, 1, PT_VOL, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_PARAM_USER_RAM0},
+/* 91 */ { 0, 0, PT_NV_RW, 	NO_UNIT,MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE0}, 	
+/* 92 */ { 0, 0, PT_NV_RW, 	NO_UNIT,MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE1}, 	
+/* 93 */ { 0, 0, PT_NV_RW, 	NO_UNIT,MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE2}, 	
+/* 94 */ { 0, 0, PT_NV_RW, 	NO_UNIT,MN_USER_NV_SIZE,1,	PARAM_NULL,				STR_PARAM_USER_EE3},
+/* 95 */ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 96 */ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 97 */ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 98 */ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 100*/ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 101*/ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 102*/ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 103*/ { 0, 0, PT_RT, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 104*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_CHKSUM}, 	
+/* 105*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_FRAG}, 	
+/* 106*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_STRAY}, 	
+/* 107*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_APP_OVERRUN}, 	
+/* 108*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_CHKSUM}, 	
+/* 109*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_FRAG}, 	
+/* 110*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_STRAY}, 	
+/* 111*/ { 0, 0, PT_RT, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_NETERR_DIAG_OVERRUN}
+};
+#if defined (__GNUC__)
+#pragma GCC diagnostic warning "-Wmissing-braces"
+#pragma GCC diagnostic warning "-Wmissing-field-initializers"
+#endif
+#define PARAM_MAX (sizeof(iscInfoDB)/sizeof(paramInfoLcl))
+// Node class database
+static byNodeClassDB iscClassDB = {
+	NULL 					// Parameter change function
+};
+
+#if defined (__GNUC__)
+	#pragma GCC diagnostic ignored "-Wmissing-braces"
+	#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+#endif
+static const paramInfoLcl iscDrvInfoDB[] = {
+// 		 1/x, signed, type,  unit,    size, scale,		config key index,		description, 			[converter]
+/* 256*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 257*/ { 0, 1, PT_RO, 	NO_UNIT,		2, 1<<9,	PARAM_I_MAX,			STR_DRV_DRV_I_MAX}, 
+/* 258*/ { 0, 2, PT_RO, 	NO_UNIT,		2, 1,		PARAM_RMS_MAX,			STR_DRV_RMS_MAX,		convertRMSlimit}, 
+/* 259*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1<<14,	PARAM_IR_CAL_FACTOR,	STR_DRV_IR_CAL},
+/* 260*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1<<14,	PARAM_IS_CAL_FACTOR,	STR_DRV_IS_CAL},
+/* 261*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},	
+/* 262*/ { 0, 1, PT_RO, 	NO_UNIT,		2, 1<<14,	PARAM_ADC_MAX,			STR_DRV_ADC_MAX,		convertADCmax}, 	
+/* 263*/ { 0, 0, PT_RW_RT, 	NO_UNIT,		2, 1,		PARAM_NV_MODIFIED,		STR_DRV_DIRTY}, 
+/* 264*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1,		PARAM_VECT_RATE,		STR_DRV_VECTOR_RATE}, 
+/* 265*/ { 0, 2, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_STEP_RES,			STR_DRV_STEP_DENS}, 	
+/* 266*/ { 0, 2, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_ENC_DENS,			STR_DRV_ENC_DENS}, 	
+/* 267*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 100,		PARAM_ENC_RESOL,		STR_DRV_ENC_RES}, 	
+/* 268*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_POLES,			STR_DRV_POLES}, 	
+/* 269*/ { 0, 2, PT_RW_RT, 	NO_UNIT,		4, 1<<7,	PARAM_MTR_KE,			STR_DRV_MTR_KE,			convertKe}, 	
+/* 270*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<9,	PARAM_MTR_OHMS,			STR_DRV_MTR_OHMS}, 	
+/* 271*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<9,	PARAM_MTR_ELECT_TC,		STR_DRV_MTR_ELEC_TC}, 	
+/* 272*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 32768/360,PARAM_RO,				STR_DRV_RO}, 	
+/* 273*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_RMS_LIM,			STR_DRV_RMS_LIM,		convertRMSlimit32}, 	
+/* 274*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_RMS_TC,			STR_DRV_RMS_TC,			convertRMStc}, 	
+/* 275*/ { 0, 2, PT_NV_RW, 	VEL_TICK_SAMPLE,2, 1<<2,	PARAM_SPEED_LIM,		STR_DRV_SPEED_LIM,		convertVelRound}, 	
+/* 276*/ { 0, 0, PT_RO_RT, 	DX_TICK,		4, 1,		PARAM_NULL,				STR_DRV_COM_CAP,		convertAngle}, 	
+/* 277*/ { 0, 0, PT_RW_RT, 	DX_TICK,		4, 1,		PARAM_MECH_ANGLE,		STR_DRV_ANGLE,			convertAngle}, 	
+/* 278*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_KIP,				STR_DRV_KIP}, 
+/* 279*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_KII,				STR_DRV_KII}, 
+/* 280*/ { 0, 2, PT_NV_RW, 	VEL_TICK_SAMPLE,2, 1<<2,	PARAM_LD_SPEED_LIM,		STR_DRV_LD_SPEED_LIM,	convertVelRound}, 	
+/* 281*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KPL,				STR_DRV_KPL}, 	
+/* 282*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KV,				STR_DRV_KV}, 
+/* 283*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KP,				STR_DRV_KP}, 
+/* 284*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KI,				STR_DRV_KI}, 
+/* 285*/ { 0, 1, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KFV,				STR_DRV_KFV}, 
+/* 286*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KFA,				STR_DRV_KFA,			limit2To27}, 
+/* 287*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KFJ,				STR_DRV_KFJ,			limit2To27}, 
+/* 288*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 327.68,	PARAM_KFF,				STR_DRV_KFF}, 
+/* 289*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_KNV,				STR_DRV_KNV}, 
+/* 290*/ { 0, 1, PT_NONE, 	NO_UNIT,		2, 1,		PARAM_AHFUZZ2,			STR_DRV_ANTIHUNT2}, 
+/* 291*/ { 0, 1, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_BIAS,			STR_DRV_TRQ_BIAS,		convertAmperes}, 
+/* 292*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_FUZZ_AP,			STR_DRV_FUZZ_AP}, 
+/* 293*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_ANTI_HUNT_HYSTERESIS,STR_DRV_FUZZ_HYST}, 
+/* 294*/ { 1, 0, PT_RO_RT, 	NO_UNIT,		2, 30,		PARAM_NULL,				STR_PARAM_FAN_SPEED}, 	
+/* 295*/ { 1, 0, PT_RO, 	NO_UNIT,		2, 30,		PARAM_FAN_FAULT_SPD,	STR_PARAM_FAN_SPEED_MIN}, 	
+/* 296*/ { 0, 0, PT_RO_RT, 	DX_TICK,		2, 1,		PARAM_NULL,				STR_DRV_TRK_MAX}, 	
+/* 297*/ { 0, 0, PT_RO_RT, 	DX_TICK,		0, 1,		PARAM_NULL,				STR_DRV_TRK_MIN}, 	
+/* 298*/ { 0, 0, PT_NV_RW, 	TIME_SAMPLE,	2, 1,		PARAM_AH_HOLDOFF,		STR_DRV_AH_HOLDOFF,		convertTimeMS}, 	
+/* 299*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		8, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 300*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN},
+/* 301*/ { 0, 0, PT_NV_RW, 	BIT_FIELD,		4, 1,		PARAM_CFG_TUNE,			STR_PARAM_CFG_TUNE}, 	
+/* 302*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_HLESS_RAMPUP_TIME,STR_DRV_HLESS_RAMPUP_TIME}, 	
+/* 303*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_HLESS_SWEEP_TIME,	STR_DRV_HLESS_SWEEP_TIME}, 	
+/* 304*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_HLESS_SETTLE_TIME,STR_DRV_HLESS_SETTLE_TIME}, 	
+/* 305*/ { 0, 2, PT_NV_RW,  NO_UNIT,		2, 1<<15,	PARAM_NO_COMM_START_TRQ,STR_DRV_HLESS_TRQ,		convertAmpsRMS},	
+/* 306*/ { 0, 2, PT_NV_RW,  NO_UNIT,		2, 1<<2,	PARAM_HLESS_ENTRY_MOTION,STR_DRV_HS_QUAL_SPEED,	convertVelRound}, 	
+/* 307*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_LIM,			STR_DRV_TRQ_LIM,		convertAmperes}, 
+/* 308*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_FLDBACK_POS,	STR_DRV_TRQ_FLDBACK_POS,convertAmperes}, 
+/* 309*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_TRQ_FLDBACK_POS_TC,STR_DRV_TRQ_FB_POS_TC, convertFilt99pctMilliseconds}, 
+/* 310*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_FLDBACK_NEG,	STR_DRV_TRQ_FLDBACK_NEG,convertAmperes}, 
+/* 311*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_TRQ_FLDBACK_NEG_TC,STR_DRV_TRQ_FB_NEG_TC, convertFilt99pctMilliseconds}, 
+/* 312*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_FLDBACK_HS,	STR_DRV_HS_FLDBACK, 	convertAmperes}, 
+/* 313*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_TRQ_FLDBACK_HS_TC,STR_DRV_HS_FB_TC,   	convertFilt99pctMilliseconds}, 
+/* 314*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_TRQ_FLDBACK_MVDN,	STR_DRV_MVDN_FB,		convertAmperes}, 
+/* 315*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_TRQ_FLDBACK_MVDN_TC,STR_DRV_MVDN_FB_TC,	convertFilt99pctMilliseconds}, 
+/* 316*/ { 0, 2, PT_NV_RW_RT,NO_UNIT,		2, (1U<<15)/100.,PARAM_HS_THRESHOLD,STR_DRV_HS_TRQ_TRIP}, 
+/* 317*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_HS_TC,			STR_DRV_HS_TC,			convertTimeMS},
+/* 318*/ { 0, 1, PT_RO_RT, 	NO_UNIT,		2, 1<<15,	PARAM_NULL,				STR_DRV_TRQ_CMD,		convertAmperes},
+/* 319*/ { 0, 1, PT_RO_RT, 	NO_UNIT,		2, 1<<13, 	PARAM_NULL,				STR_DRV_TRQ_MEAS,		convertMeasAmperes},
+/* 320*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_DRV_RMS_LEVEL,		convertRMSlevel}, 
+/* 321*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_TRK_ERR_LIM,		STR_DRV_TRK_ERR_LIM}, 
+/* 322*/ { 0, 2, PT_NV_RW, 	TIME_SAMPLE,	2, 1,		PARAM_MV_DN_TC,			STR_DRV_MV_DN_TC,		convertTimeMS}, 
+/* 323*/ { 0, 2, PT_NV_RW,  NO_UNIT,		2, 1<<15,	PARAM_STEP_RUN_TRQ,		STR_DRV_STEPPER_TRQ,	convertAmpsRMS},
+/* 324*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_STEP_IDLE_TRQ,	STR_DRV_STEP_IDLE_TRQ,	convertAmpsRMS}, 
+/* 325*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<15,	PARAM_STEP_ACC_TRQ,		STR_DRV_STEP_ACC_TRQ,	convertAmpsRMS}, 
+/* 326*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_TRQ_FLDBACK_STEP_TC,STR_DRV_STEP_FB_TC,   convertFilt99pctMilliseconds}, 
+/* 327*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1<<5,	PARAM_BUS_V,			STR_DRV_BUS_VOLTS}, 
+/* 328*/ { 0, 1, PT_RO_RT, 	BIT_FIELD,		2, 1,		PARAM_NULL,				STR_DRV_TP_IOP}, 
+/* 329*/ { 0, 1, PT_RO_RT, 	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_DRV_TP_IR,			convertMeasAmperes}, 
+/* 330*/ { 0, 1, PT_RO_RT, 	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_DRV_TP_IS,			convertMeasAmperes}, 
+/* 331*/ { 0, 1, PT_RO_RT,	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_DRV_TP_IR_FILT,		convertMeasAmperes}, 	
+/* 332*/ { 0, 1, PT_RO_RT, 	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_DRV_TP_IS_FILT,		convertMeasAmperes}, 	
+/* 333*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 65520./300.,	PARAM_NULL,			STR_DRV_HEATSINK}, 
+/* 334*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 65520./300.,	PARAM_NULL,			STR_P_PWBA_TEMP}, 
+/* 335*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 32768./6.,	PARAM_NULL,			STR_PARAM_TP_5V},
+/* 336*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		2, 32768./18,	PARAM_NULL,			STR_PARAM_TP_12V},
+/* 337*/ { 0, 0, PT_VOL, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_IR_IS_TP_FILT_TC,	convertFilt1TCMilliseconds}, 
+/* 338*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		2, 65520./300.,	PARAM_NULL,			STR_P_TEMP_SIM}, 
+/* 339*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1<<4,	PARAM_NULL,				STR_P_DRV_PWR_LIM_EXP}, 	
+/* 340*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1<<9,	PARAM_NULL,				STR_P_DRV_RES_MIN}, 	
+/* 341*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 65520./300,	PARAM_NULL,			STR_P_FAN_ON_TEMP}, 	
+/* 342*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_DSP_INFO}, 	
+/* 343*/ { 0, 2, PT_RO, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_IB_FILT_TC,		convertIBRMStc}, 	
+/* 344*/ { 0, 1, PT_RO, 	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_P_IB_TRIP,			convertAmpsRMS}, 	
+/* 345*/ { 0, 0, PT_RO, 	NO_UNIT,		2, 1U<<15,	PARAM_NULL,				STR_P_PHASE_TRIP,		convertMeasAmperes}, 	
+/* 346*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1U<<31,	PARAM_NULL,				STR_P_IB_RMS,			convertAmpsRMS}, 	
+/* 347*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1000,	PARAM_NULL,				STR_P_TSPD}, 	
+/* 348*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 349*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, (1<<17)/360., PARAM_NULL,		STR_DRV_COMM_CHK_ANGLE_LIM}, 	
+/* 350*/ { 0, 2, PT_NV_RW, 	NO_UNIT,		2, 1,		PARAM_COUPLING_ERR_LIM,	STR_DRV_CPL_ERR_LIM}, 	
+/* 351*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 352*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 353*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 354*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 355*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 356*/ { 0, 0, PT_NONE, 	NO_UNIT,		0, 1,		PARAM_NULL,				STR_UNKNOWN}, 	
+/* 357*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		6, 1,		PARAM_NULL,				STR_P_IEX_STATE_REG}, 	
+/* 358*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_IEX_USER_OUT_REG,	STR_P_IEX_USER_OUT}, 	
+/* 359*/ { 0, 0, PT_NV_RW, 	NO_UNIT,		4, 1,		PARAM_IEX_STOP_OUT_REG,	STR_P_IEX_STOP_OUT}, 	
+/* 360*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_OUT_REG}, 	
+/* 361*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_IN_REG}, 	
+/* 362*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_IN_RISE}, 	
+/* 363*/ { 0, 0, PT_RO_RT, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_IN_FALL}, 	
+/* 364*/ { 0, 0, PT_RAM, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_IN_ATTN_MASK}, 	
+/* 365*/ { 0, 0, PT_RAM, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_RISE_ATTN_MASK}, 	
+/* 366*/ { 0, 0, PT_RAM, 	NO_UNIT,		4, 1,		PARAM_NULL,				STR_P_IEX_FALL_ATTN_MASK}, 	
+/* 367*/ { 0, 0, PT_RAM, 	NO_UNIT,		2, 1,		PARAM_NULL,				STR_P_IEX_GLITCH_TOLERANCE}, 	
+/* 368*/ { 0, 0, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_SOFT_LIM_POSN_POS,STR_PARAM_SOFT_LIM_POS},
+/* 369*/ { 0, 0, PT_NV_RW, 	DX_TICK,		4, 1,		PARAM_SOFT_LIM_POSN_NEG,STR_PARAM_SOFT_LIM_NEG}
+};
+#if defined (__GNUC__)
+#pragma GCC diagnostic warning "-Wmissing-braces"
+#pragma GCC diagnostic warning "-Wmissing-field-initializers"
+#endif
+
+#define DRV_PARAM_MAX (sizeof(iscDrvInfoDB)/sizeof(paramInfoLcl))
+
+// Default settings
+#define DFLT_STOP_ACC_LIM	100000.
+#define DFLT_VEL_LIM		175000.
+#define DFLT_ACC_LIM		1000000.
+#define DFLT_IMAX			33.						// Current scale maximum
+#define DFLT_HS_TRIP		(DFLT_IMAX*0.80)		// Hardstop Trip Point (A)
+#define DFLT_FLD_BACK		(DFLT_IMAX*0.05)		// Foldback levels (A)
+#define DFLT_SENSORLESS_TRQ 1.						// Sensorless startup trq (A)
+
+
+#if defined (__GNUC__)
+#pragma GCC diagnostic ignored "-Wmissing-braces"
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+#endif
+static const factoryInitData initData[] =  { 
+	// Trajectory Generator Parameters  VAL,		"Not J"
+	{ NVR,	ISC_P_HW_CONFIG_REG, 		0x220 }, // comm sensors = state + thermal, encoder checking
+	{ NVR,	ISC_P_APP_CONFIG_REG, 		0 },
+	{ NVR,	ISC_P_DRV_TUNE_CONFIG_REG, 	0x220 }, // MtrVelocityEst=LdVelocityEst=2
+	{ NVR,	ISC_P_STOP_ACC_LIM, 		DFLT_STOP_ACC_LIM },
+	{ NVR,	ISC_P_ACC_LIM, 				DFLT_ACC_LIM },
+	{ NVR,	ISC_P_DEC_LIM, 				DFLT_ACC_LIM },
+	{ NVR,	ISC_P_VEL_LIM, 				DFLT_VEL_LIM },
+	{ NVR,	ISC_P_HEAD_DISTANCE,		1000 },
+	{ NVR,	ISC_P_TAIL_DISTANCE,		1000 },
+	{ NVR,	ISC_P_HEADTAIL_VEL,			100000 },
+	{ NVR,	ISC_P_JERK_LIM, 			3 }, //3 ms in 5.1.1 FW; 10 ms in 5.2.0+ FW
+	{ NVR,	ISC_P_JERK_LIM, 			0x00000090, FW_MILESTONE_IEX }, //Attack=1, gStop=2, normal in 5.2.2+ FW
+	{ NVR,	ISC_P_STOP_TYPE, 			STOP_TYPE_ABRUPT },
+	{ NVR,	ISC_P_CTL_STOP_OUT_REG, 	0 },
+	{ NVR,	ISC_P_USER_OUT_REG, 		0 },
+	{ NV,	ISC_P_IN_POLARITY_REG, 		0 },
+	{ NVR,	ISC_P_POSN_TRK_RANGE,		10 },
+	// Drive Parameters
+	{ NVR,	ISC_P_DRV_RMS_LIM,			1 },		// A
+	{ NVR,	ISC_P_DRV_RMS_TC,			1 },		// sec
+	{ NVR,	ISC_P_DRV_KIP,				0 },
+	{ NVR,	ISC_P_DRV_KII,				0 },
+	{ NVR,	ISC_P_DRV_KV,				0 },
+	{ NVR,	ISC_P_DRV_KP,      			0 },
+	{ NVR,	ISC_P_DRV_KI,      			0 },
+	{ NVR,	ISC_P_DRV_KFV,     			0 },
+	{ NVR,	ISC_P_DRV_KFA,     			0 },
+	{ NVR,	ISC_P_DRV_KFJ,     			0 },
+	{ NVR,	ISC_P_DRV_KFF,     			0 },
+	{ NVR,	ISC_P_DRV_KNV,     			0 },
+	{ NVR,	ISC_P_DRV_KPL,				0 },
+	{ NVR,	ISC_P_DRV_AHFUZZ2,     		-1 },
+	{ NVR,	ISC_P_DRV_TRQ_BIAS,			0 },
+	{ NVR,	ISC_P_DRV_FUZZY_APERTURE, 	0 },
+	{ NVR,	ISC_P_DRV_FUZZY_HYST, 		3 },
+	{ NVR,	ISC_P_AH_HOLDOFF,			50 },
+	{ NVR,	ISC_P_DRV_TRK_ERR_LIM, 		1000 },
+	{ NVR,	ISC_P_DRV_CPL_ERR_LIM,		1000,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_DRV_MV_DN_TC,    		10 },			// ms
+	{ NVR,	ISC_P_DRV_POS_FLDBK_TRQ, 	DFLT_FLD_BACK },
+	{ NVR,	ISC_P_DRV_POS_FLDBK_TRQ_TC, 200 },
+	{ NVR,	ISC_P_DRV_NEG_FLDBK_TRQ, 	DFLT_FLD_BACK },
+	{ NVR,	ISC_P_DRV_NEG_FLDBK_TRQ_TC, 200 },
+	{ NVR,	ISC_P_DRV_MOVEDONE_FLDBK_TRQ, DFLT_FLD_BACK },
+	{ NVR,	ISC_P_DRV_MOVEDONE_FLDBK_TRQ_TC, 200 },
+	{ NVR,	ISC_P_DRV_HARDSTOP_FLDBK_TRQ, DFLT_FLD_BACK },
+	{ NVR,	ISC_P_DRV_HARDSTOP_FLDBK_TRQ_TC, 200 },
+	{ NVR,	ISC_P_DRV_HARDSTOP_ENTRY_TRQ, 80 },
+	{ NVR,	ISC_P_DRV_HARDSTOP_ENTRY_TC, 50 },	// ms
+	{ NVR,	ISC_P_DRV_TRQ_LIM,			DFLT_IMAX },			// A
+	{ NVR,	ISC_P_DRV_SENSORLESS_TRQ,	DFLT_SENSORLESS_TRQ },	// A
+	{ NVR,	ISC_P_DRV_HARDSTOP_ENTRY_SPD, 7598.7 },	// encs/sec
+	{ NVRV,	ISC_P_DRV_BUS_VOLTS,		75 },
+	{ NVR,	ISC_P_DRV_TRQ_MEAS_FILT_TC,	50  },		// ms
+	// Motor items last, 'cause they fail more often
+	{ NVR,	ISC_P_DRV_MTR_SPEED_LIM,	200000 },	// encs/sec
+	{ NVR,	ISC_P_DRV_LD_SPEED_LIM,		200000 },	// encs/sec
+	{ NV,	ISC_P_DRV_ENC_RES,			1.0 },
+	{ NV,	ISC_P_USER_DATA_NV0,		0 },
+	{ NV,	ISC_P_USER_DATA_NV1,		0 },
+	{ NV,	ISC_P_USER_DATA_NV2,		0 },
+	{ NV,	ISC_P_USER_DATA_NV3,		0 },
+	{ NVRV,	ISC_P_DRV_MTR_POLES,		8 },
+	{ NVRV,	ISC_P_DRV_ENC_DENS,			4000 },
+	{ NVRV,	ISC_P_DRV_MTR_KE,			0 },
+	{ NVRV,	ISC_P_DRV_MTR_OHMS,			0 },
+	{ NVRV,	ISC_P_DRV_MTR_ELEC_TC,		0 },
+	{ NVRV,	ISC_P_DRV_COM_RO,			0 },
+	// New Meridian Params
+	{ NVRV,	ISC_P_USER_IN_REG,			0 },
+	{ NVRV,	ISC_P_IN_SRC_REG,			0 },
+	{ NVR,	ISC_P_OUT_PLA_SRC_REG,		0 },
+	{ NVR,	ISC_P_POSN_TRIG_PT,			0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_A_START,				0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_B_END,				0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_GP_TIMER_PERIOD,		0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_DRV_STEPPER_TRQ,		0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_DRV_STEP_IDLE_TRQ,	0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_DRV_STEP_ACC_TRQ,		0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_DRV_STEP_FLDBK_TRQ_TC, 0,	FW_MILESTONE_IEX },
+	{ NVRV,	ISC_P_DRV_USTEPS_PER_REV,	32000, FW_MILESTONE_IEX },
+	// IEX init only power-on default to avoid errors on nodes
+	// with not IEX modules attached or running.
+	{ NV,	ISC_P_IEX_USER_OUT_REG,		0,	FW_MILESTONE_IEX },
+	{ NV,	ISC_P_IEX_STOP_OUT_REG,		0,	FW_MILESTONE_IEX },
+	{ RAM,	ISC_P_STATUS_ATTN_MASK,		0 },
+	{ RAM,	ISC_P_WARN_MASK,			0 },
+	{ RAM,	ISC_P_ALERT_MASK,			0 },
+	{ RAM,	ISC_P_IEX_IN_REG_MASK,		0,	FW_MILESTONE_IEX },
+	{ RAM,	ISC_P_IEX_IN_RISE_REG_MASK,	0,	FW_MILESTONE_IEX },
+	{ RAM,	ISC_P_IEX_IN_FALL_REG_MASK,	0,	FW_MILESTONE_IEX },
+	{ NVR,	ISC_P_DRV_COMM_CHK_ANGLE_LIM,20,FW_MILESTONE_VECTOR_STEEPER },
+	{ NVR,	ISC_P_DRV_SENSORLESS_RAMPUP_TIME,2000,FW_MILESTONE_VECTOR_STEEPER },
+	{ NVR,	ISC_P_DRV_SENSORLESS_SWEEP_TIME,1000,FW_MILESTONE_VECTOR_STEEPER },
+	{ NVR,	ISC_P_DRV_SENSORLESS_SETTLE_TIME,500,FW_MILESTONE_VECTOR_STEEPER },
+	{ NVR,	ISC_P_DRV_SOFT_LIM_POSN_POS,0,	FW_MILESTONE_SOFT_LIMITS },
+	{ NVR,	ISC_P_DRV_SOFT_LIM_POSN_NEG,0,	FW_MILESTONE_SOFT_LIMITS },
+};
+#if defined (__GNUC__)
+#pragma GCC diagnostic warning "-Wmissing-braces"
+#pragma GCC diagnostic warning "-Wmissing-field-initializers"
+#endif
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		ISC_DUMP_PKT
+//
+//	DESCRIPTION:							
+//		Write buffer as hex debug string.
+//
+//	SYNOPSIS:
+void ISC_DUMP_PKT(multiaddr theMultiAddr, char *msg, packetbuf *buf) {
+#ifdef _DEBUG
+	size_t i;
+	_RPT2(_CRT_WARN, "%s: %.1f -> ", msg, infcCoreTime());
+	//buf->u.fld.startOfPacket = 1;
+	//buf->u.fld.zero1 = buf->u.fld.mode = 0;
+	//buf->u.fld.pktType = MN_PKT_TYPE_CMD;
+	for (i=0; i<buf->Fld.PktLen+MN_API_PACKET_HDR_LEN; i++) {
+		_RPT1(_CRT_WARN, "%02x ", 0xFF & buf->Byte.Buffer[i]);
+	}
+	_RPT0(_CRT_WARN, "\n");
+#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscClassDelete
+//
+//	DESCRIPTION:
+//		Delete any memory this node allocated.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+void iscClassDelete(multiaddr theMultiAddr) {
+	register byNodeDB *pNodeDB;
+	netaddr cNum = NET_NUM(theMultiAddr);
+	pNodeDB = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	// Delete if no one else has
+	if (pNodeDB->paramBankList) {
+		//_RPT1(_CRT_WARN, "iscClassDelete %d\n", theMultiAddr);
+		pNodeDB->bankCount = 0;
+		pNodeDB->theID.devCode = NODEID_UNK;
+		free((void *)(pNodeDB->paramBankList[0]).valueDB);
+		(pNodeDB->paramBankList[0]).valueDB = NULL;
+		free((void *)(pNodeDB->paramBankList[1]).valueDB);
+		(pNodeDB->paramBankList[1]).valueDB = NULL;
+		free((void *)pNodeDB->paramBankList);
+		pNodeDB->paramBankList = NULL;
+		if (pNodeDB->pNodeSpecific) {
+			delete (iscState *)pNodeDB->pNodeSpecific;
+			pNodeDB->pNodeSpecific = NULL;
+		}
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscClassSetup
+//
+//	DESCRIPTION:
+//		Setup the parameter manager and node database for this node.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+cnErrCode iscClassSetup(
+	multiaddr theMultiAddr)
+{
+	cnErrCode errRet;
+	packetbuf resp, fwVers, dummy;
+	register byNodeDB *pNodeDB;
+	netaddr cNum = NET_NUM(theMultiAddr);
+	//_RPT2(_CRT_WARN, "iscClassSetup net=%d, node=%d\n", cNum, theMultiAddr);
+	
+	// Stop using old memory
+	iscClassDelete(theMultiAddr);
+	// Make sure this is a Integrated Servo Controller
+	errRet = netGetParameter(theMultiAddr, MN_P_NODEID, &resp);
+	if (errRet == MN_OK)  {
+		errRet = netGetParameter(theMultiAddr, ISC_P_FW_VERSION, &fwVers);
+		if (errRet == MN_OK)  {
+			// Shorthand to access the device ID field
+			#define DEVID ((devID_t *)(&resp.Byte.Buffer[0]))
+			#define FWVER ((versID_t *)(&fwVers.Byte.Buffer[0]))
+			// Fill in the database from the node if this is a TG
+			if (DEVID->fld.devType	== NODEID_MD)	 {		
+				// Initialize the register/shortcut
+				pNodeDB = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+				// Wire in our destructor
+				pNodeDB->delFunc = iscClassDelete;
+				// Initialize the per node database
+				pNodeDB->bankCount = 2;
+				// Update the ID area
+				pNodeDB->theID.fld.devType = DEVID->fld.devType;
+				pNodeDB->theID.fld.devModel = DEVID->fld.devModel;
+				// Create and initialize the parameter banks
+				pNodeDB->paramBankList = (paramBank *)calloc(2, sizeof(paramBank));
+				// Bank 0 information
+				(pNodeDB->paramBankList[0]).nParams = PARAM_MAX;
+				(pNodeDB->paramBankList[0]).fixedInfoDB = &iscInfoDB[0];
+				// Create the value storage area together
+				(pNodeDB->paramBankList[0]).valueDB 
+					= (paramValue *)calloc(PARAM_MAX, sizeof(paramValue));
+				// Bank 1 information
+				(pNodeDB->paramBankList[1]).nParams = DRV_PARAM_MAX;
+				(pNodeDB->paramBankList[1]).fixedInfoDB = &iscDrvInfoDB[0];
+				// Create the value storage area together
+				(pNodeDB->paramBankList[1]).valueDB 
+					= (paramValue *)calloc(DRV_PARAM_MAX, sizeof(paramValue));
+				// Create by node information
+				pNodeDB->pNodeSpecific = new iscState;
+
+				// Initialize the class specific items
+				pNodeDB->pClassInfo = &iscClassDB; 
+
+				// Reset all node diagnostics by reading them (clear on read)
+				netGetParameter(theMultiAddr,ISC_P_NETERR_APP_CHKSUM,&dummy);
+				netGetParameter(theMultiAddr,ISC_P_NETERR_APP_FRAG,&dummy);
+				netGetParameter(theMultiAddr,ISC_P_NETERR_APP_STRAY,&dummy);
+				netGetParameter(theMultiAddr,ISC_P_NETERR_APP_OVERRUN,&dummy);
+
+				netGetParameter(theMultiAddr,ISC_P_NETERR_DIAG_CHKSUM,&dummy);
+				netGetParameter(theMultiAddr,ISC_P_NETERR_DIAG_FRAG,&dummy);
+				netGetParameter(theMultiAddr,ISC_P_NETERR_DIAG_STRAY,&dummy);
+				netGetParameter(theMultiAddr,ISC_P_NETERR_DIAG_OVERRUN,&dummy);
+				if (FWVER->verCode >= FW_MILESTONE_LINK_LOW) {
+					netGetParameter(theMultiAddr,ISC_P_NETERR_LOW_VOLTS,&dummy);
+				}
+
+				errRet = coreUpdateParamInfo(theMultiAddr);
+			}
+			else
+				errRet = MN_ERR_WRONG_NODE_TYPE;
+		}
+	}
+	return(errRet);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//******************************************************************************
+//	!NAME!
+//		iscInitializeEx
+//
+//	DESCRIPTION:
+//		This function will configure the network and download the parameters 
+//		into a local copy of the parameters for the addressed node.
+//
+//	\return
+//		MN_OK if successful
+//
+//	SYNOPSIS:
+cnErrCode iscInitializeEx(
+	multiaddr theMultiAddr,						// Ptr to return array
+	nodebool warmInitialize)
+{
+	return(coreInitializeEx(theMultiAddr, warmInitialize, iscClassSetup));
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		iscInitialize
+ *
+ *	DESCRIPTION:
+ *		This function will configure the network and download the parameters 
+ *		into a local copy of the parameters for the addressed node.
+ *
+ *	\return
+ *		MN_OK if successful
+ *
+ *	SYNOPSIS: 															    */
+cnErrCode iscInitialize(
+	multiaddr theMultiAddr)						// Ptr to return array
+{
+	return(iscInitializeEx(theMultiAddr, FALSE));
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetStimulus
+//
+//	DESCRIPTION:
+/**
+	Get the current stimulus generator settings.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pState Ptr to the result area updated with current state 
+			information.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pState)
+{
+	packetbuf theCmd, theResp;
+	paramValue sampleTime;
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+	iscStimCmdPkt *pStimData = ((iscStimCmdPkt *)&theResp.Byte.Buffer[RESP_LOC]);
+
+	cNum = coreController(theMultiAddr);
+	
+	// Get sample rate conversion factor	
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD, NULL, &sampleTime);
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(MN_ERR_RESP_FMT);
+	sampleTime.value *= 0.001;			// Convert microseconds to milliseconds
+
+	// Fill in the command head parts
+	theCmd.Fld.Addr = theMultiAddr;
+	theCmd.Fld.PktLen = 1;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_GET_SET_STIMULUS;
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	// DEBUG PRINT
+	//ISC_DUMP_PKT(theMultiAddr, "Get Stim", &theResp);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// Properly formatted response?
+	if (theResp.Fld.PktLen != ISC_STIM_RESP_STATUS_OCTETS) 
+		return(MN_ERR_RESP_FMT);
+	// Crack the return buffer into standard units
+	pState->mode = (stimModes)pStimData->Mode;
+	pState->period = (nodelong)(0.5+(pStimData->Period * sampleTime.value));
+	pState->bits = pStimData->Status;
+	switch (pState->mode) {
+		case STIM_OFF:
+			pState->amplitude = 0;				
+			break;
+		case STIM_VEL:				// Velocity	(ticks/ms)
+			pState->amplitude = (ISC_MON_MAX_VEL * pStimData->Amplitude 
+							   / sampleTime.value)
+		             		   / 32767;
+			break;
+		case STIM_CAL:				// Calibrate/test (100% FS)
+		case STIM_TRQ:				// Torque
+			pState->amplitude = pStimData->Amplitude / 327.67;
+			break;
+		case STIM_POSN:				// Position	(ticks)
+			pState->amplitude = pStimData->Amplitude;
+			break;
+		case STIM_MOVE_ONCE:
+		case STIM_MOVE_RECP:
+		case STIM_MOVE_REPEAT:
+			pState->amplitude = pStimData->Amplitude;
+			pState->slew = pStimData->Slew;
+			// Convert dwell back to milliseconds
+			if (sampleTime.value != 0) 
+				pState->dwell = static_cast<nodelong>(pStimData->Dwell 
+													 / sampleTime.value);
+			else
+				pState->dwell = 0;
+			break;
+		default:
+			return(MN_ERR_BADARG);
+	}
+	//_RPT3(_CRT_WARN, "iscGetStimulus: mode %d ampl=%f per=%f\n", pState->mode, 
+	//									pState->amplitude, pState->period);
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetStimulus
+//
+//	DESCRIPTION:
+/**
+	Change the stimulus generator setting.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewState Ptr to the new state desired.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetStimulus(
+			multiaddr theMultiAddr,	// Target node addr
+			iscStimState *pNewState)
+{
+	packetbuf theCmd, theResp;
+	paramValue sampleTime;
+	nodelong lVal, tVal;
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+
+	//_RPT3(_CRT_WARN, "iscSetStimulus: mode %d ampl=%f per=%f\n", pNewState->mode, pNewState->amplitude, pNewState->period);
+	// Get sample rate conversion factor	
+	theErr = netGetParameterInfo(theMultiAddr, ISC_P_SAMPLE_PERIOD,	
+								NULL, &sampleTime);
+	if (theErr != MN_OK || sampleTime.value == 0)
+		return(MN_ERR_BADARG);
+	sampleTime.value *= 0.001;			// Convert microseconds to milliseconds
+
+	// Fill in the command head parts
+	theCmd.Fld.Addr = theMultiAddr;
+	switch(pNewState->mode){
+		case STIM_MOVE_ONCE:
+		case STIM_MOVE_RECP:
+		case STIM_MOVE_REPEAT:
+			theCmd.Fld.PktLen = ISC_STIM_CMD_PKT_PROF_SIZE;
+			break;
+		default:
+			theCmd.Fld.PktLen = ISC_STIM_CMD_PKT_SIZE;
+			break;
+	}
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_GET_SET_STIMULUS;
+	// Shortcut to the command buffer
+	iscStimCmdPkt *pSimCmd = ((iscStimCmdPkt *)&theCmd.Byte.Buffer[CMD_LOC+1]);
+
+	// Set the mode
+	pSimCmd->Mode = (nodechar)pNewState->mode;
+	// Saturate @ largest value
+	// Set the 0.5*period(ms) in sample-time(us) counts
+	lVal = (nodelong)(0.5+(pNewState->period/sampleTime.value));
+	// Saturate @ largest value
+	if (lVal > 32767) lVal = 32767;
+	pSimCmd->Period = (nodeshort)(lVal);
+	// Zero out potentially unused fields
+	pSimCmd->Dwell = 0;
+	pSimCmd->Status = 0;
+	pSimCmd->Slew = 0;
+
+	// Figure out the scaling for the amplitude based on the mode
+	switch(pNewState->mode)  {
+		case STIM_OFF:
+			lVal = 0;				
+			break;
+		case STIM_VEL:				// Velocity	(ticks/ms)
+			lVal = (nodelong)(32767. * pNewState->amplitude * sampleTime.value 
+			             / ISC_MON_MAX_VEL + ((pNewState->amplitude<0)?(-.5):(.5)));
+			if (lVal > 32767) lVal = 32767;
+			break;
+		case STIM_CAL:				// Calibrate/test (100% FS)
+		case STIM_TRQ:				// Torque
+			lVal = (nodelong)(327.67*pNewState->amplitude);
+			if (lVal > 32767) lVal = 32767;
+			break;
+		case STIM_POSN:				// Position	(ticks)
+			if (pNewState->amplitude < 32767)
+				lVal = (nodelong)pNewState->amplitude;
+			else
+				lVal = 32767;
+			break;
+		case STIM_MOVE_ONCE:
+		case STIM_MOVE_RECP:
+		case STIM_MOVE_REPEAT:
+			pSimCmd->Period = static_cast<nodeshort>(pNewState->period);
+			lVal = (nodelong)pNewState->amplitude;
+			// Saturate @ largest value
+			if (pNewState->amplitude > INT32_MAX) lVal = INT32_MAX;
+			pSimCmd->Slew = (nodeshort)pNewState->slew;
+			// Convert request milliseconds to sample-counts
+			tVal = (nodelong)(0.5+(pNewState->dwell/sampleTime.value));
+			if (tVal > INT16_MAX) tVal = INT16_MAX;
+			pSimCmd->Dwell = (nodeshort)tVal;
+			break;
+		default:
+			return(MN_ERR_BADARG);
+	}
+	
+	pSimCmd->Amplitude = lVal;
+
+	// Make it so, wait for return
+	//ISC_DUMP_PKT(theMultiAddr, "Set Stim", &theCmd);
+
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	if (theErr == MN_OK && theResp.Fld.PktLen != 0)
+		return(MN_ERR_RESP_FMT);
+	// Test we get back our settings 
+	//{
+	//	 iscStimState x;
+	//	 theErr = iscGetStimulus(theMultiAddr, &x); 
+	//}
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetMonitor
+//
+//	DESCRIPTION:
+/**
+	Get the monitor state for the selected node. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] channel Targets which monitor port channel. Set this to zero.
+	\param[out] pState Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetMonitor(
+			multiaddr theMultiAddr,	// Target node addr
+			nodeushort channel,		// Target monitor port if supported
+			iscMonState *pState)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+	appNodeParam param;
+	netaddr cNum;
+
+	// Pointer to data overlay in packet
+	iscMonNodeState *MON_AREA_GET 
+		= ((iscMonNodeState *)&theResp.Byte.Buffer[RESP_LOC]);
+
+	cNum = coreController(theMultiAddr);
+
+	// We only support one channel
+	if (channel != 0)
+		return(MN_ERR_BADARG);
+
+	theCmd.Fld.Addr = theMultiAddr;
+	theCmd.Fld.PktLen = 1;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_GET_SET_MONITOR;
+	// Get the raw data
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	//ISC_DUMP_PKT(theMultiAddr, "Get Mon", &theResp);
+	if (theErr!=MN_OK)
+		return(theErr);
+	// Properly formatted response?
+	if (theResp.Fld.PktLen < 9 || theResp.Fld.PktLen > 10) 
+		return(MN_ERR_RESP_FMT);
+	// Fill in the return buffer
+	if (pState)  {
+		// Convert buffer to VB friendly structure
+		pState->var = (iscMonVars)MON_AREA_GET->var;
+		pState->tuneSync = (iscTuneSyncs)MON_AREA_GET->tuneSync;
+
+		// Convert gain number to full scale equivalent
+		pState->gain = convertMonGain(TRUE, theMultiAddr, 
+											   pState->var, 
+											   MON_AREA_GET->gain);
+
+		// Convert filter TC bits to milliseconds
+		param.bits = 0;					// Not used by converter anyways
+		pState->filterTC = convertFilt1TCMilliseconds(TRUE, theMultiAddr, param, 
+									MON_AREA_GET->filter,
+									&SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)]);
+
+		// Copy tune syncs
+	}
+	return(theErr);	
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetMonitor
+//
+//	DESCRIPTION:
+/**
+	Set the monitor state for the selected node. This function will
+	also update the parameter values which mirror the individual states.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] channel Targets which monitor port channel. Set this to zero.
+	\param[out] pNewState Ptr to desired new state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetMonitor(
+			multiaddr theMultiAddr,	// Target node addr
+			nodeushort channel,		// Target monitor port if supported
+			iscMonState *pNewState)
+{
+
+	cnErrCode theErr = MN_OK;
+	packetbuf theCmd, theResp;
+	nodelong paramLng;
+	appNodeParam param;
+	netaddr cNum;
+
+	// Shortcut to the command buffer
+	iscMonNodeState *MON_AREA_SET 
+		= ((iscMonNodeState *)&theCmd.Byte.Buffer[CMD_LOC+1]);
+
+	// We only support one channel
+	if (channel != 0) 
+		return(MN_ERR_BADARG);
+
+	// Get controller context
+	cNum = coreController(theMultiAddr);
+	if (cNum > NET_CONTROLLER_MAX)
+			return(MN_ERR_BADARG);
+
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+
+	// Fill in the command head parts
+	theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);
+	theCmd.Fld.PktLen = 10;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_GET_SET_MONITOR;
+
+	// Set the variable member
+	MON_AREA_SET->var = (nodeshort)pNewState->var;
+	
+	// Convert the full scale value to a gain number
+	paramLng = (nodelong)convertMonGain(FALSE, theMultiAddr, 
+						  (iscMonVars)(pNewState->var & ~(MON_OPTION_MASKS)), 
+						  pNewState->gain);
+	MON_AREA_SET->gain = paramLng;
+
+	// Convert the filter constant to the internal representation
+	param.bits = 0;					// This is not used by the converter
+	paramLng = (nodelong)convertFilt1TCMilliseconds(FALSE, theMultiAddr, param, 
+						  pNewState->filterTC, 
+						  &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)]);
+	MON_AREA_SET->filter = (nodeshort)paramLng;
+
+	// tuneSync
+	MON_AREA_SET->tuneSync = (nodeshort)pNewState->tuneSync;
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	//ISC_DUMP_PKT(theMultiAddr, "Set Mon", &theCmd);
+	if (theErr == MN_OK && theResp.Fld.PktLen != 0)
+		return(MN_ERR_RESP_FMT);
+	// Test that we get our setting
+	//iscMonState x;
+	//theErr = iscGetMonitor(theMultiAddr, 0, &x);
+
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+/*****************************************************************************
+ *	!NAME!
+ *		iscParamChangeFunc
+ *
+ *	DESCRIPTION:
+ *		Set the parameter change callback function.
+ *
+ *	\return
+ *		Old handler
+ *
+ *	SYNOPSIS: 															    */
+MN_EXPORT paramChangeFunc MN_DECL iscParamChangeFunc(
+	  	paramChangeFunc newFunc)		// Node number of changed
+{
+	paramChangeFunc oldFunc = iscClassDB.paramChngFunc;
+	iscClassDB.paramChngFunc = newFunc;
+	return(oldFunc);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+//==============================================================================
+// END OF UNDOCUMENTED API FUNCTIONS TO THIS LINE
+/// \endcond
+//==============================================================================
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		iscSyncPosition
+ *
+ *	DESCRIPTION:
+ *		Run the Synchronize Position command.
+ *
+ *	\return
+ *		#cnErrCode; MN_OK if successful
+ *
+ *	SYNOPSIS: 															    */
+MN_EXPORT cnErrCode MN_DECL iscSyncPosition(
+			multiaddr theMultiAddr)			// Node address
+{
+	packetbuf cmd, theResp;					// Input and output buffers
+	cnErrCode theErr;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+	cmd.Fld.Addr = theMultiAddr;	
+	cmd.Fld.PktLen = ISC_CMD_SYNC_POSN_LEN;
+	cmd.Byte.Buffer[CMD_LOC] = ISC_CMD_SYNC_POSN;
+	theErr = netRunCommand(cNum, &cmd, &theResp);
+	return theErr;
+}
+
+/*																 !end!		*/
+/****************************************************************************/
+
+
+
+
+
+
+
+
+////****************************************************************************
+////	NAME
+////		iscReEnable
+////
+////	DESCRIPTION:
+////		Reset the vector search flag
+////
+////	\return
+////		#cnErrCode; MN_OK if successful
+////
+////	SYNOPSIS:
+//MN_EXPORT cnErrCode MN_DECL iscReEnable(
+//			multiaddr theMultiAddr)	// Target node addr
+//{
+//	packetbuf theCmd;
+//	cnErrCode theErr = MN_OK;
+//	netaddr cNum;
+//
+//	cNum = coreController(theMultiAddr);
+//	// Fill in the command head parts
+//	theCmd.Fld.Addr = theMultiAddr;
+//	theCmd.Fld.PktLen = 1;
+//	theCmd.Byte.Buffer[CMD_LOC] = MD_CMD_RE_ENABLE;
+//	theErr = netRunCommand(cNum, &theCmd, NULL);
+//	return(theErr);
+//}
+///****************************************************************************/
+
+//******************************************************************************
+//	NAME																	   *
+//		iscReVector
+//
+//	DESCRIPTION:
+/**
+	Reset the vector search flag. This function is mostly diagnostic in nature.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscReVector(
+			multiaddr theMultiAddr)	// Target node addr
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+	// Fill in the command head parts
+	theCmd.Fld.Addr = theMultiAddr;
+	theCmd.Fld.PktLen = 1;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_RE_VECTOR;
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+//****************************************************************************
+//	NAME
+//		iscGet/SetJerkTime
+//
+//	DESCRIPTION:
+//		Manipulate jerk limit in terms of time. This is a TG porting function.
+//
+//	\return
+//		double
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetJerkTime(
+			multiaddr theMultiAddr,
+			double *settingValMS) 
+{
+	return(iscGetParameter(theMultiAddr, ISC_P_JERK_LIM, settingValMS));
+}
+
+MN_EXPORT cnErrCode MN_DECL iscSetJerkTime(
+			multiaddr theMultiAddr,
+			double newValMS)
+{
+	return(iscSetParameter(theMultiAddr, ISC_P_JERK_LIM, newValMS));
+}
+
+
+//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+//-----------------------------------------------------------------------------
+//			         MOTION INITIATION AND CONTROL API
+//-----------------------------------------------------------------------------
+//* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+
+
+////*****************************************************************************
+////	NAME																	  *
+////		waitForMoveIdle
+////
+////	DESCRIPTION:
+////      This function spin waits for the move subsystem to become idle.
+////		TODO: 01/6/09 DS Add timeout to protect scripts.
+////
+////	\return
+////		#cnErrCode; MN_OK if successful
+////
+////	SYNOPSIS:
+//static cnErrCode MN_DECL waitForMoveIdle(
+//			multiaddr theMultiAddr)				// Node to access
+//{
+//	mnStatusReg rtStatus;
+//	cnErrCode theErr;
+//
+//    do {
+//        theErr  = iscGetStatusRTReg(theMultiAddr, &rtStatus);
+//		infcSleep(0);
+//    } while (theErr == MN_OK
+//			 && (!rtStatus.Fld.PLAin.DrvFld.MoveDone
+//			  || !rtStatus.Fld.LowAttn.DrvFld.MoveBufAvail));
+//	return (theErr);
+//}
+////																			  *
+////*****************************************************************************
+
+
+/// \cond INTERNAL_DOC
+//*****************************************************************************
+//	NAME																	  *
+//		waitForMoveBuffer
+//
+//	DESCRIPTION:
+//		This function spin waits until the move buffer is available.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL waitForMoveBuffer(
+			multiaddr theMultiAddr)			// Node to access
+{
+	return(MN_OK);
+ //   mnStatusReg rtStatus;				// RVW? TODO...
+ //   cnErrCode theErr;
+	//double timeOut;
+ //   
+ //   // Wait for room in the buffer
+	//timeOut = infcCoreTime() + 10000;
+ //   do {
+ //   	theErr = iscGetStatusRTReg(theMultiAddr, &rtStatus);
+	//	infcSleep(0);
+	//	if (infcCoreTime() > timeOut)
+	//		return(MN_ERR_TIMEOUT);
+ //   } while (theErr == MN_OK 
+ //   		 && !rtStatus.bit.moveBufEmpty);
+	//return(theErr);
+}	
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkMoveVelQueued
+//
+//	DESCRIPTION:
+//      Sends a move that ramps up or down in speed to Velocity (using the
+//      previously set limits for acceleration and jerk [RAS]).
+//
+//      Program execution does not suspend.  Once Velocity is achieved, the
+//      move stays at Velocity until explicitly changed. Velocity is specified
+//      as steps/second.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkMoveVelQueued(
+			multiaddr theMultiAddr,		// Node address
+			double velTargetStepPerSec,	// Velocity (steps/sec)
+			nodelong positionTarget,	// Target Position (optional)
+			mgVelStyle moveType,		// Motion style
+			nodelong *pBuffersRemaining)	// Ptr to move buf remaining cnt
+{
+	packetbuf cmd, resp;					// Input and output buffers
+	netaddr cNum;
+	double velScale, velTarg;
+	nodelong iVelTarg;
+	cnErrCode theErr = MN_OK;
+
+	// Get sample rate as basis for ticks/sample
+    theErr = iscGetParameter(theMultiAddr, ISC_P_SAMPLE_PERIOD, &velScale);
+	if (theErr == MN_OK) {
+		cNum = NET_NUM(theMultiAddr);
+		cmd.Fld.Addr = NODE_ADDR(theMultiAddr);	
+		// Len=cmd byte, 4 bytes target vel, mode byte
+		cmd.Fld.PktLen = 1 + sizeof(iVelTarg) + 1;
+		cmd.Byte.Buffer[CMD_LOC] = ISC_CMD_MOVE_VEL_EX;
+		velTarg = (nodelong)(0.5 + (velTargetStepPerSec * ISC_VEL_MOVE_SCALE * velScale 
+									   / 1000000.));
+		// Saturate test
+		/// \cond INTERNAL_DOC
+		#define MAX_VEL_Q 31
+		/// \endcond
+		if (velTarg > (1LL<<MAX_VEL_Q)-1)
+			velTarg = (1LL<<MAX_VEL_Q)-1;
+		else if(velTarg < (-1LL<<MAX_VEL_Q))
+			velTarg  = -1LL<<MAX_VEL_Q;
+		// Save as long integer bits
+		iVelTarg = (nodelong)velTarg;
+		// copy the position target into the command buffer
+		memcpy(&cmd.Byte.Buffer[CMD_LOC+1], &iVelTarg, sizeof(iVelTarg));
+		// Copy move type over
+		cmd.Byte.Buffer[CMD_LOC+5] = (nodechar)moveType.styleCode;
+		// If positional involved
+		if (positionTarget) {
+			memcpy(&cmd.Byte.Buffer[CMD_LOC+6], &positionTarget, 
+											    sizeof(positionTarget));
+			cmd.Fld.PktLen += sizeof(positionTarget);
+		}
+		// Run the command and await the response
+		theErr = netRunCommand(cNum, &cmd, &resp);
+		if (pBuffersRemaining && theErr == MN_OK)
+			*pBuffersRemaining = resp.Byte.Buffer[RESP_LOC];
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+/// \endcond
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkMoveVelEx
+//
+//	DESCRIPTION:
+//      Sends a move that ramps up or down in speed to Velocity (using the
+//      previously set limits for acceleration and jerk [RAS]).
+//
+//      Program execution does not suspend.  Once Velocity is achieved, the
+//      move stays at Velocity until explicitly changed. Velocity is specified
+//      as steps/second.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkMoveVelEx(
+			multiaddr theMultiAddr,			// The node
+			double velTargetStepPerSec,		// Target velocity (steps/sec)
+			nodelong positionTarget,		// Position Target [optional]
+			mgVelStyle moveType)			// Enhanced style selection
+{
+	return iscForkMoveVelQueued(theMultiAddr, velTargetStepPerSec,
+							    positionTarget, moveType,
+								NULL);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkVelMoveBuffered
+//
+//	DESCRIPTION:
+//      Sends a move that ramps up or down in speed to Velocity (using the
+//      previously set limits for acceleration and jerk [RAS]).
+//
+//      Program execution does not suspend.  Once Velocity is achieved, the
+//      move stays at Velocity until explicitly changed. Velocity is specified
+//      as steps/second.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkVelMoveBuffered(
+			multiaddr theMultiAddr,			// The node
+			double velTargetStepPerSec,		// Target velocity (steps/sec)
+			nodelong positionTarget,			// Position Target [optional]
+			mgVelStyle moveType)			// Enhanced style selection
+{
+	// Wait for buffer to free up
+	cnErrCode theErr = waitForMoveBuffer(theMultiAddr);
+	// If OK, run the command, it shouldn't fail due to no buffer space.
+	if (theErr == MN_OK) {
+		theErr = iscForkMoveVelEx(theMultiAddr, velTargetStepPerSec, 
+								  positionTarget, moveType);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscMoveProfiled
+//
+//	DESCRIPTION:
+//		This function performs a move using an information buffer
+//		for motion specification.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscMoveProfiled(
+			multiaddr theMultiAddr,		// Destination node
+			mgMoveProfiledInfo *spec)	// Target (steps)
+{
+	packetbuf cmd, resp;					// Input and output buffers
+	netaddr cNum;
+	cnErrCode theErr = MN_OK;
+
+	//_RPT3(_CRT_WARN, "%.1f move(%d)=>%d\n", infcCoreTime(), theMultiAddr, spec->value);
+
+	// TODO convert to use most net efficient form of command
+	cNum = coreController(theMultiAddr);
+	cmd.Fld.Addr = theMultiAddr;	
+	cmd.Fld.PktLen = 1 + 1 + sizeof(spec->value);
+	cmd.Byte.Buffer[CMD_LOC] = ISC_CMD_MOVE_POSN_EX;
+	iscMovePosnExPacket *MOVE_DATAP = 
+		((iscMovePosnExPacket *)&cmd.Byte.Buffer[CMD_LOC+1]);
+	MOVE_DATAP->style = spec->type;
+	// copy the position target into the command buffer
+	memcpy(&cmd.Byte.Buffer[CMD_LOC+2], &spec->value, 
+										  sizeof(spec->value));
+	// Run the command and await the response
+	theErr = netRunCommand(cNum, &cmd, &resp);
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscMoveProfiledQueued
+//
+//	DESCRIPTION:
+//		This function performs a move using an information buffer
+//		for motion specification.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscMoveProfiledQueued(
+			multiaddr theMultiAddr,		// Destination node
+			mgMoveProfiledInfo *spec,	// Target (steps)
+			nodelong *pBuffersRemaining)
+{
+	packetbuf cmd, resp;					// Input and output buffers
+	netaddr cNum;
+	cnErrCode theErr = MN_OK;
+
+	//_RPT3(_CRT_WARN, "%.1f move(%d)=>%d\n", infcCoreTime(), theMultiAddr, spec->value);
+	// TODO convert to use most net efficient form of command
+	cNum = coreController(theMultiAddr);
+	cmd.Fld.Addr = theMultiAddr;	
+	cmd.Fld.PktLen = 1 + 1 + sizeof(spec->value);
+	cmd.Byte.Buffer[CMD_LOC] = ISC_CMD_MOVE_POSN_EX;
+	iscMovePosnExPacket *MOVE_DATAP = 
+		((iscMovePosnExPacket *)&cmd.Byte.Buffer[CMD_LOC+1]);
+	MOVE_DATAP->style = spec->type;
+	// copy the position target into the command buffer
+	memcpy(&cmd.Byte.Buffer[CMD_LOC+2], &spec->value, 
+										  sizeof(spec->value));
+	// Run the command and await the response
+	theErr = netRunCommand(cNum, &cmd, &resp);
+
+	// If run on older node, assume nothing left
+	if (pBuffersRemaining) {
+		*pBuffersRemaining = 0;
+		if (resp.Fld.PktLen)
+			*pBuffersRemaining = resp.Byte.Buffer[RESP_LOC];
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkMoveExBuffered
+//
+//	DESCRIPTION:
+//		This function performs initiates a move with buffer management.
+//
+//	\return
+//		#cnErrCode; MN_OK if successful
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkMoveExBuffered(
+			multiaddr theMultiAddr,		// Destination node
+			nodelong posnTarget,			// Target (steps)
+			mgPosnStyle moveType)
+{
+	// Wait for buffer to free up
+	cnErrCode theErr = waitForMoveBuffer(theMultiAddr);
+	// If OK, run the command, it shouldn't fail due to no buffer space.
+	if (theErr == MN_OK) {
+		theErr = iscForkMoveEx(theMultiAddr, posnTarget, moveType);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+#ifdef BONE_YARD
+//Boneyard: Some features haven't been implemented yet, but we want to save
+//the original functions and declarations for when they are.
+
+/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ * ISC Drive IO sample register
+ * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/
+typedef union _iscDrvIOsampleReg  {
+	nodeushort bits;
+	struct _iscDrvIOsampleRegBits  {
+		unsigned					: 4;	// 0-3
+		unsigned nPosLimit			: 1;	// 4  ~Positive limit (in)
+		unsigned nNegLimit			: 1;	// 5  ~Negative limit (in)
+		unsigned Shutdown			: 1;	// 6  Shutdown (out)
+		unsigned Commutation		: 3;	// 7-9  Commutation TSR code (in)
+		unsigned EnableIn			: 1;	// 10 Enable (in) emulated
+		unsigned AmpDisable			: 1;	// 11 Amplifier stage disable (out)
+		unsigned DriveLED			: 1;	// 12 Drive LED (out)
+		unsigned OverCurrent		: 1;	// 13 Overcurrent (in)
+		unsigned Thermostat			: 1;	// 14 Thermostat input
+		unsigned ModeIn				: 1;	// 15 Mode line (in) <unused>
+	} bit;
+} iscDrvIOsampleReg;
+
+/*																 !end!		*/
+/****************************************************************************/
+
+#endif	 // BONE_YARD
+/// \endcond
+
+//==============================================================================
+// DOCUMENTED API FUNCTIONS GO BELOW THIS LINE
+//==============================================================================
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetParameter
+//
+//  DESCRIPTION:
+/**
+	Get parameter value with no extra information.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The ISC parameter code
+	\param[out] pParamVal Ptr to result
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetParameter(
+			multiaddr theMultiAddr,		// Node address
+			iscParams theParam,			// Parameter index
+			double *pParamVal)			// Ptr to value area
+{
+	paramValue pVal;
+	cnErrCode theErr;
+
+	theErr = iscGetParameterEx(theMultiAddr, theParam, &pVal, NULL);
+//	if (theParam == (ISC_P_DRV_I_MAX)) {
+//		_RPT3(_CRT_WARN, "ding p#%d(%d)=>%f\n", theParam, theMultiAddr, pVal.value );
+//	}
+//	else {
+//		_RPT2(_CRT_WARN, "isc param %d=%f\n", theParam, pVal.value);
+//	}
+	if (pParamVal != NULL) 
+		*pParamVal = pVal.value;
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetParameter
+//
+//  DESCRIPTION:
+/**
+	This function will update the local parameter value for the selected
+	node and then change the value at the node if possible. If the
+	parameter is inaccessible the appropriate error is returned.
+		
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The ISC parameter code
+	\param[out] paramVal New value to set at node
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetParameter(
+			multiaddr theMultiAddr,		// Node address
+			iscParams theParam,			// Parameter index
+			double paramVal)			// New value
+{
+	cnErrCode theErr = MN_OK;
+	theErr = netSetParameterInfo(theMultiAddr,
+								  theParam,
+								  paramVal, FALSE);
+	#ifdef _DEBUG
+		if(theErr != MN_OK)
+			_RPT4(_CRT_WARN,"netSetParameterInfo(%d, %d, %f) failed, err=0x%x", 
+			theMultiAddr, theParam, paramVal, theErr);
+	#endif
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetParameterEx
+//
+//  DESCRIPTION:
+/**
+	This function will retreive the local parameter value for the
+	selected node and return its value and information pertaining to it.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The ISC parameter code
+	\param[out] pTheValue Ptr to the parameter value / raw bits.
+	\param[out] pTheInfo Ptr to optional information if non-NULL
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetParameterEx(
+			multiaddr theMultiAddr, 		// Node address
+			iscParams theParam,			// Parameter index
+			paramValue *pTheValue,		// Ptr to returning value area
+			paramInfo *pTheInfo) 		// Ptr to returning optional information
+{
+
+	cnErrCode theErr=MN_OK;
+	theErr = netGetParameterInfo(theMultiAddr,
+								  theParam, 
+								  pTheInfo, 
+								  pTheValue);
+	return(theErr);
+}
+
+//																               *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetParameterEx
+//
+//  DESCRIPTION:
+/**
+	Set the parameter using the bytes described in the \a paramVal
+	buffer.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParam The ISC parameter code
+	\param[out] pNewValue Ptr to bit-oriented packet buffer. The buffer size
+				will determine the amount written to the node.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetParameterEx(
+			multiaddr theMultiAddr,		// Node address
+			iscParams theParam,			// Parameter index
+			packetbuf *pNewValue)		// New value
+{
+	cnErrCode theErr = MN_OK;
+	// Set the raw value at the node
+	theErr = netSetParameterEx
+		(theMultiAddr, theParam, pNewValue);
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscAddToPosition
+//
+//  DESCRIPTION:
+/**
+	Change the node's measured and commanded positions by the \p theOffset 
+	amount.	All position capture sources are adjusted to reflect the offset
+	in number space. The change is atomically applied to all values. 
+
+	This function will not cause any motion to occur and provides a mechanism
+	for aligning the application's number space with the node's.
+		
+	\remark Incoming capture sources properly reflect the offset in 
+	number space.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theOffset Offset amount in encoder units.
+
+	\return
+		#cnErrCode; MN_OK if successful
+
+	\see ISC_P_POSN_CAP_GPI1
+	\see ISC_P_POSN_CAP_INDEX
+	\see ISC_P_POSN_CAP_INDEX_LD
+	\see ISC_P_POSN_CAP_PLA
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscAddToPosition(
+			multiaddr theMultiAddr,		// Node address
+			double theOffset)			// Offset amount
+{
+	packetbuf theCmd, theResp;					// Input and output buffers
+	cnErrCode theErr;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+	// Format the command
+	theCmd.Fld.Addr = theMultiAddr;	
+	theCmd.Fld.PktLen = ISC_CMD_ADD_POSN_LEN;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_ADD_POSN;
+	*((nodelong *)&theCmd.Byte.Buffer[CMD_LOC+1]) 
+		= (nodelong)(theOffset);
+	// Run it and wait for response
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	return theErr;
+}
+//																               *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscAddToPositionLd
+//
+//  DESCRIPTION:
+/**
+	Change the load's measured position by the \p theOffset 
+	amount.
+		
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theOffset Offset amount in encoder units.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscAddToPositionLd(
+			multiaddr theMultiAddr,		// Node address
+			double theOffset)			// Ptr to parameter list definitions
+{
+	packetbuf theCmd, theResp;					// Input and output buffers
+	cnErrCode theErr;
+	netaddr cNum;
+
+	theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);	
+	theCmd.Fld.PktLen = ISC_CMD_ADD_POSN_LEN;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_ADD_POSN_LD;
+    *((nodelong *)&theCmd.Byte.Buffer[CMD_LOC+1]) 
+		= (nodelong)((theOffset));
+
+	cNum = coreController(theMultiAddr);
+	theErr = netRunCommand(cNum, &theCmd, &theResp);
+	return theErr;
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetUserOutputReg
+//
+//  DESCRIPTION:
+/**
+	Set the state of the User Output Register. When the output register is
+	controlled by bits in this register, changes here are reflected in the 
+	output register. This register typically is used to enable the drive and to 
+	set the General Purpose Outputs.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] newState New state for User Output Register.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetUserOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg newState)			// New setting
+{
+	// Update the double value
+	return(iscSetParameter(theMultiAddr, ISC_P_USER_OUT_REG, newState.bits));
+}
+
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetUserOutputReg
+//
+//  DESCRIPTION:
+/**
+	Get the current setting of the User Output Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pGPOreg Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetUserOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg)			// Current setting
+{
+	double pVal;
+	cnErrCode theErr;
+	
+	theErr = iscGetParameter(theMultiAddr, ISC_P_USER_OUT_REG, &pVal);
+	// Update the raw buffer
+	pGPOreg->bits = (nodeushort)pVal;
+	return(theErr);
+}
+
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetOutputReg
+//
+//  DESCRIPTION:
+/**
+	Get the current setting of the Output Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pGPOreg Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetOutputReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg)			// Current setting
+{
+	double pVal;
+	cnErrCode theErr;
+	
+	theErr = iscGetParameter(theMultiAddr, ISC_P_OUT_REG, &pVal);
+	// Update the raw buffer
+	pGPOreg->bits = (nodeushort)pVal;
+	return(theErr);
+}
+
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetOutputRiseReg
+//
+//  DESCRIPTION:
+/**
+	Get the current setting of the Output Rise Register
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pGPOreg Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetOutputRiseReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg)			// Current setting
+{
+	double pVal;
+	cnErrCode theErr;
+	
+	theErr = iscGetParameter(theMultiAddr, ISC_P_OUT_RISE_REG, &pVal);
+	// Update the raw buffer
+	pGPOreg->bits = (nodeushort)pVal;
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetOutputFallReg
+//
+//  DESCRIPTION:
+/**
+	Get the current setting of the Output Fall Register
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pGPOreg Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetOutputFallReg(
+			multiaddr theMultiAddr,		// Node address
+			plaOutReg *pGPOreg)			// Current setting
+{
+	double pVal;
+	cnErrCode theErr;
+	
+	theErr = iscGetParameter(theMultiAddr, ISC_P_OUT_FALL_REG, &pVal);
+	// Update the raw buffer
+	pGPOreg->bits = (nodeushort)pVal;
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetStatusAccumReg
+//
+//	DESCRIPTION:
+/**
+	Get and clear the current Status Accumulation Register value.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS: 
+MN_EXPORT cnErrCode MN_DECL iscGetStatusAccumReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_STATUS_ACCUM_REG, 
+							   &paramVal, NULL);
+	pStatus->clear();					// Insure MSBs cleared
+	*pStatus = *((mnStatusReg *)&(paramVal.raw.Byte.Buffer[0]));
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetAttnStatusRiseReg
+//
+//	DESCRIPTION:
+/**
+	Get and clear the current accumulation of rising status register states.
+
+	\note Any bits that are unmasked for Attention Generation always return
+	zero.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+
+	\deprecated To future-proof for future devices use the generic
+	read function #netGetAttnStatusRiseReg.
+**/
+//	SYNOPSIS: 
+MN_EXPORT cnErrCode MN_DECL iscGetAttnStatusRiseReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_STATUS_ATTN_RISE_REG, 
+							  &paramVal, NULL);
+	pStatus->clear();					// Insure MSBs cleared
+	*pStatus = *((mnStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetStatusFallReg
+//
+//	DESCRIPTION:
+/**
+	Get and clear the current accumulation of the falling status register 
+	states.
+
+	\note Any bits that are unmasked for Attention Generation always return
+	zero.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/		
+//	SYNOPSIS: 
+MN_EXPORT cnErrCode MN_DECL iscGetStatusFallReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_STATUS_FALL_REG, 
+							  &paramVal, NULL);
+	pStatus->clear();					// Insure MSBs cleared
+	*pStatus = *((mnStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetStatusRTReg
+//
+//	DESCRIPTION:
+/**
+	Get a snapshot of the current status register states.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatus Ptr to current state.
+
+	\return
+		#cnErrCode; MN_OK if successful
+
+	\deprecated To future-proof for future devices use the generic
+	read function #netGetStatusRTReg.
+	\todo add other common register accesors for mask, etc.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetStatusRTReg(
+			multiaddr theMultiAddr,		// Node address
+			mnStatusReg *pStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_STATUS_RT_REG, 
+							   &paramVal, NULL);
+	pStatus->clear();					// Insure MSBs cleared
+	*pStatus = *((mnStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetAlertReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Alert Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAlertReg Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetAlertReg(
+			multiaddr theMultiAddr,			// Node address
+			alertReg *pAlertReg)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_ALERT_REG, &paramVal, NULL);
+	*pAlertReg = *((alertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetWarningReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Warning Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pWarningReg Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetWarningReg(
+			multiaddr theMultiAddr,			// Node address
+			alertReg *pWarningReg)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_WARN_REG, &paramVal, NULL);
+	*pWarningReg = *((alertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetAttnMask
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Attention Mask Register. Bits set in this
+	register will allow automatic generation of Attentions (Network Interrupts)
+	to the host.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAttnMask Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetAttnMask(
+			multiaddr theMultiAddr,		// Node address
+			attnReg *pAttnMask)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_STATUS_ATTN_MASK, 
+							   &paramVal, NULL);
+	*pAttnMask = *((attnReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetAttnMask
+//
+//	DESCRIPTION:
+/**
+	Set the Attention Mask Register. Bits set in this
+	register will allow automatic generation of Attentions (Network Interrupts)
+	to the host.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pAttnMask Ptr to new setting.
+
+	\return		
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetAttnMask(
+			multiaddr theMultiAddr,		// Node address
+			attnReg *pAttnMask)			// Current setting
+{
+	cnErrCode theErr;
+	packetbuf paramVal;
+	memcpy(paramVal.Byte.Buffer, pAttnMask, ATTN_MASK_OCTETS);
+	paramVal.Byte.BufferSize = ATTN_MASK_OCTETS;
+	theErr = iscSetParameterEx(theMultiAddr, ISC_P_STATUS_ATTN_MASK, &paramVal);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetAlertMaskReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the <i>Alert Mask Register</i> (#ISC_P_ALERT_MASK). 
+	Bits set in this register could allow the automatic generation of
+	Attentions (Network Interrupts) when specifically selected items become 
+	active. The #lowAttnReg::UserAlert bit is set in the Status Register when 
+	the Alert Register bit-wised ANDed with this register is non-zero.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAlertMask Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+
+	\see \ref iscSetAlertMaskReg
+	\see \ref mnStatusReg
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetAlertMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pAlertMask)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_ALERT_MASK, 
+							   &paramVal, NULL);
+	*pAlertMask = *((alertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetAlertMaskReg
+//
+//	DESCRIPTION:
+/**
+	Set the current state of the <i>Alert Mask Register</i> (#ISC_P_ALERT_MASK). 
+	Bits set in this register could allow the automatic generation of 
+	Attentions (Network Interrupts) when specifically selected items become 
+	active. The #lowAttnReg::UserAlert bit is set in the Status Register when 
+	the Alert Register bit-wised ANDed with this register is non-zero. 
+	The alert mask for #lowAttnReg::UserAlert, when set, will generate an 
+	automatic attention.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pAlertMask Ptr to new setting.
+
+	\return		
+		#cnErrCode; MN_OK if successful
+
+	\see \ref iscGetAlertMaskReg
+	\see \ref mnStatusReg
+	\see \ref iscSetAttnMask
+	\see \ref mnAttnsPage
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetAlertMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pAlertMask)		// Current setting
+{
+	cnErrCode theErr;
+	packetbuf paramVal;
+	memcpy(paramVal.Byte.Buffer, pAlertMask, ALERTREG_SIZEOCTETS);
+	paramVal.Byte.BufferSize = ALERTREG_SIZEOCTETS;
+	theErr = iscSetParameterEx(theMultiAddr, ISC_P_ALERT_MASK, &paramVal);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetWarningMaskReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the <i>Warning Mask Register</i> (#ISC_P_WARN_REG). 
+	Bits set in this register could allow the automatic generation of Attentions
+	(Network Interrupts) when specifically selected items become active. The 
+	#lowAttnReg::Warning bit is set in the Status Register when the
+	Warning Register bit-wised ANDed with this register is non-zero.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pWarnMask Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+
+	\see \ref iscSetWarningMaskReg
+	\see \ref mnStatusReg
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetWarningMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pWarnMask)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_WARN_MASK, 
+							   &paramVal, NULL);
+	*pWarnMask = *((alertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetWarningMaskReg
+//
+//	DESCRIPTION:
+/**
+	Set the current state of the <i>Warning Mask Register</i> (#ISC_P_WARN_REG). 
+	Bits set in this register could allow the automatic generation of Attentions
+	(Network Interrupts) when specifically selected items become active. The 
+	#lowAttnReg::Warning bit is set in the Status Register when the
+	Warning Register bit-wised ANDed with this register is non-zero.
+	The alert mask for #lowAttnReg::Warning, when set, will generate an 
+	automatic attention.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pWarnMask Ptr to new setting.
+
+	\return		
+		#cnErrCode; MN_OK if successful
+
+	\see \ref iscGetWarningMaskReg
+	\see \ref mnStatusReg
+	\see \ref iscSetAttnMask
+	\see \ref mnAttnsPage
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetWarningMaskReg(
+			multiaddr theMultiAddr,		// Node address
+			alertReg *pWarnMask)		// Current setting
+{
+	cnErrCode theErr;
+	packetbuf paramVal;
+	memcpy(paramVal.Byte.Buffer, pWarnMask, ALERTREG_SIZEOCTETS);
+	paramVal.Byte.BufferSize = ALERTREG_SIZEOCTETS;
+	theErr = iscSetParameterEx(theMultiAddr, ISC_P_WARN_MASK, &paramVal);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetHwConfigReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Hardware Configuration Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pHwConfigReg Ptr to the result.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscHwConfigReg *pHwConfigReg)	// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_HW_CONFIG_REG, 
+							&paramVal, NULL);
+	*pHwConfigReg = *((iscHwConfigReg *)&paramVal.raw.Byte.Buffer[0]);
+
+	pHwConfigReg->bits &= 0xffffffff;			// 32 bit register
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetHwConfigReg
+//		As of 01/11/10, this is a 32 bit register
+//
+//	DESCRIPTION:
+/**
+	Set the current state of the Hardware Configuration Register. This register
+	controls many the hardware related options and features.  For example 
+	the IEX control is setup here.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] hwConfigReg New state.
+
+	\return	
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetHwConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscHwConfigReg hwConfigReg)		// New setting
+{
+	hwConfigReg.bits &= 0xffffffff;
+	// Update the double value
+	return(iscSetParameter(theMultiAddr, ISC_P_HW_CONFIG_REG, hwConfigReg.bits));
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetAppConfigReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Application Configuration Register. This 
+	register controls application and drive specific features such as control
+	of the hard-stop feature.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAppConfigReg Ptr to the result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscAppConfigReg *pAppConfigReg)	// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_APP_CONFIG_REG, 
+							   &paramVal, NULL);
+	*pAppConfigReg = *((iscAppConfigReg *)&paramVal.raw.Byte.Buffer[0]);
+
+	pAppConfigReg->bits &= 0xffffffff;			// 32 bit register
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetAppConfigReg
+//		As of 01/11/10, this is a 32 bit register
+//
+//	DESCRIPTION:
+/**
+	Set the state of the Application Configuration Register. This 
+	register controls application and drive specific features such as control
+	of the hard-stop feature.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] appConfigReg New state for the register.
+
+	\return		
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetAppConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscAppConfigReg appConfigReg)	// New setting
+{
+	appConfigReg.bits &= 0xffffffff;
+	// Update the double value
+	return(iscSetParameter(theMultiAddr, ISC_P_APP_CONFIG_REG, 
+						   appConfigReg.bits));
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetTuneConfigReg
+//
+//	DESCRIPTION:
+/**
+	Get the state of the Tuning Configuration Register. This 
+	register controls items related to servo tuning.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pTuneConfigReg Ptr to the result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetTuneConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscTuneConfigReg *pTuneConfigReg)	// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_DRV_TUNE_CONFIG_REG, 
+							   &paramVal, NULL);
+	*pTuneConfigReg = *((iscTuneConfigReg *)&paramVal.raw.Byte.Buffer[0]);
+
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetTuneConfigReg
+//		As of 01/11/10, this is a 32 bit register
+//
+//	DESCRIPTION:
+/**
+	Set the state of the Tuning Configuration Register. This 
+	register controls tuning related features such as anti-hunt
+	and the velocity estimators.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] tuneConfigReg New state to set.
+
+	\return	
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetTuneConfigReg(
+			multiaddr theMultiAddr,			// Node address
+			iscTuneConfigReg tuneConfigReg)	// New setting
+{
+	// Update the double value
+	return(iscSetParameter(theMultiAddr, ISC_P_DRV_TUNE_CONFIG_REG, 
+							tuneConfigReg.bits));
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetLdMtrRatio
+//
+//	DESCRIPTION:
+/**
+	Get the load to motor encoder ratio. This setting specifies
+	the coupling that exists between the motor and load encoders.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pLoadPart Ptr to the load portion of the load/mtr ratio.
+	\param[out] pMotorPart Ptr to the motor portion of the load/mtr ratio.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetLdMtrRatio(
+			multiaddr theMultiAddr,			// Node address
+			nodelong *pLoadPart,
+			nodelong *pMotorPart)	// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_DRV_LD_MTR_RATIO, 
+							   &paramVal, NULL);
+	if (theErr == MN_OK){
+		*pLoadPart = *((nodelong *)&paramVal.raw.Byte.Buffer[0]);
+		*pMotorPart = *((nodelong *)&paramVal.raw.Byte.Buffer[4]);
+	}
+	return(theErr);
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetLdMtrRatio
+//
+//	DESCRIPTION:
+/**
+	Set the load to motor encoder ratio. This setting specifies
+	the coupling that exists between the motor and load encoders.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] loadPart The load portion of the load/mtr ratio to set.
+	\param[in] motorPart The motor portion of the load/mtr ratio to set.
+
+	\return		
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetLdMtrRatio(
+			multiaddr theMultiAddr,			// Node address
+			nodelong loadPart,
+			nodelong motorPart)	// New setting
+{
+	packetbuf buf;
+	// Set the Ld to Mtr ratio to loadPart:motorPart
+	buf.Byte.BufferSize = sizeof(nodelong)*2;
+	*(nodelong*)(&buf.Byte.Buffer[0]) = loadPart;
+	*(nodelong*)(&buf.Byte.Buffer[4]) = motorPart;
+	// Always write the ld/mtr ratio to EE
+	iscSetParameterEx(theMultiAddr, 
+							 (iscParams)(ISC_P_DRV_LD_MTR_RATIO+128), 
+							 &buf);
+	// Always write the ld/mtr ratio to EE
+	return(iscSetParameterEx(theMultiAddr, 
+							 (iscParams)(ISC_P_DRV_LD_MTR_RATIO), 
+							 &buf));
+}
+//																               *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscFactoryDefaults
+//
+//	DESCRIPTION:
+/**
+	Initialize the node to factory defaults. All tuning and features are
+	restored to factory ship out state.
+
+	\param[in] theMultiAddr The address code for this node.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscFactoryDefaults(
+			multiaddr theMultiAddr)			// Destination node
+{
+	double romSum, eeVer;
+	packetbuf buf;
+	cnErrCode theErr;
+	unsigned i, maxItems;
+	double nodeVers, pVal;
+	optionReg opts;
+
+	maxItems = sizeof(initData)/sizeof(factoryInitData);
+
+	// Dis-Acknowledge EE update
+	if ((theErr = iscGetParameter(theMultiAddr, ISC_P_EE_VER, &eeVer)) != MN_OK)
+		return(theErr);
+	if ((theErr = iscGetParameter(theMultiAddr, ISC_P_ROM_SUM, &romSum)) != MN_OK)
+		return(theErr);
+    if ((theErr = netSetParameterInfo(theMultiAddr, ISC_P_EE_UPD_ACK , 
+										  -eeVer, TRUE)) != MN_OK)
+		return(theErr);
+
+	if ((theErr = iscGetParameter(theMultiAddr, ISC_P_FW_VERSION, &nodeVers)) != MN_OK)
+		return(theErr);
+    
+	if ((theErr = iscGetParameter(theMultiAddr, ISC_P_OPTION_REG, &pVal)) != MN_OK)
+		return(theErr);
+    opts.bits = (unsigned)pVal;
+
+	for (i=0 ; i<maxItems ; i++) {
+		if ((nodeVers >= initData[i].minVersion) 
+		&& ((initData[i].fwOption==0)		// Cover invariant cases
+		|| (opts.Common.Product==3 && initData[i].fwOption==2)) ) {  // Cover K case(s)
+			switch (initData[i].type) {
+				case RAM:
+					// There is no EE version; just set the RAM value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum, 
+						                     initData[i].value, TRUE);
+					break;
+				case NV:
+					// There is no RAM shadow; just set the EE value
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum|PARAM_OPT_MASK, 
+						                     initData[i].value, TRUE);
+					break;
+				case NVRV:
+					// Set the RAM version and the EE version will be updated
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum, 
+						                     initData[i].value, TRUE);
+					break;
+				case NVR:
+					// Set non-volatile
+					theErr = netSetParameterInfo(theMultiAddr, 
+											 initData[i].paramNum|PARAM_OPT_MASK, 
+						                     initData[i].value, TRUE);
+					//If the EE write failed, don't bother trying the RAM value
+					if (theErr == MN_OK){
+						// Set RAM shadow
+						theErr = netSetParameterInfo(theMultiAddr, 
+												 initData[i].paramNum, 
+												 initData[i].value, TRUE);
+						//In this case, we don't really care if the RAM value took
+						theErr = MN_OK;
+					}
+					break;
+				default:
+					// We don't do anything with items not defined yet
+					_RPT1(_CRT_WARN, "Factory default item not processed: type %d\n",
+								initData[i].type);
+					break;
+			}
+#if 0
+			{
+				iscOpStateReg ops; cnErrCode e;
+				// TODO debug
+				e = iscGetAlertReg (theMultiAddr, &ops); 
+				if(e==MN_OK && ops.bit.runtimeErr)  {
+					double pVal;
+					e = iscGetParameter(theMultiAddr, ISC_P_LAST_RUNTIME_ERR, &pVal);
+					_RPT2(_CRT_WARN, "ISC factory defaults +> runtime error @ %d Code=%d\n",
+									 initData[i].paramNum|PARAM_OPT_MASK,(nodelong)pVal);				
+				}
+			}
+#endif
+		}
+		if (theErr != MN_OK && theErr != MN_ERR_CMD_ARGS) {
+			_RPT2(_CRT_WARN, "ISC factory defaults: failed param#%d, err=0x%x\n",
+							 initData[i].paramNum, theErr);				
+			return(theErr);
+		}
+	}
+
+	// Clear out the user ID
+	theErr = iscSetUserID(theMultiAddr, "");
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+    // Clear out the motor filename
+	theErr = iscSetMotorFileName(theMultiAddr, "");
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+    
+	// Clear the user managed storage
+	buf.Byte.BufferSize = 13;
+	for (i=0; i<4; i++) {
+		if ((theErr = iscSetParameterEx(theMultiAddr, 
+									   (iscParams)(ISC_P_USER_DATA_NV0+i), 
+									   &buf)) != MN_OK)
+			return(theErr);
+	}
+
+	// Setup the monitor port
+	iscMonState newMonState;
+	newMonState.var = static_cast<iscMonVars>(MON_TRQ_CMD | MON_SAVE_NV_MASK);
+	newMonState.gain = 100;
+	newMonState.filterTC = 0;
+	newMonState.tuneSync = ISC_MON_SYNC_POS_START;
+    if ((theErr = iscSetMonitor(theMultiAddr, 0, &newMonState)) != MN_OK)
+		return(theErr);
+		
+	// Clear the PLA if we have it
+	if (nodeVers >= FW_MILESTONE_IEX) {
+		if ((theErr = netPLAclear(theMultiAddr)) != MN_OK) {
+			return(theErr);
+		}
+		// Initialize Ld to Mtr ratio to 1:1
+		if ((theErr = iscSetLdMtrRatio(theMultiAddr, 1, 1)) != MN_OK){
+			return(theErr);
+		}
+	}
+
+	if (opts.DrvFld.HwPlatform == ISC9x_300V_DC_Large 
+		|| opts.DrvFld.HwPlatform == ISC9x_300V_DC_Mid) {
+		
+		if ((theErr = netSetParameterInfo(theMultiAddr, ISC_P_DRV_BUS_VOLTS, 
+										  300, TRUE)) != MN_OK)
+			return(theErr);
+	}
+	
+	// Acknowledge firmware & configuration update
+    if ((theErr = netSetParameterInfo(theMultiAddr, ISC_P_EE_UPD_ACK, 
+										  eeVer, TRUE)) != MN_OK)
+		return(theErr);
+    if ((theErr = netSetParameterInfo(theMultiAddr, ISC_P_ROM_SUM_ACK, 
+										  romSum, TRUE)) != MN_OK)
+		return(theErr);
+    
+	// Force node to reset and re-init parameter DB
+	{
+		double pVal2;
+		iscGetParameter(theMultiAddr, ISC_P_TIMESTAMP, &pVal2);
+	}
+	theErr=iscInitialize(theMultiAddr);
+	// Got through here OK
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetUserID
+//
+//	DESCRIPTION:
+/**
+	Get the User ID for this node. This is an identifier the application
+	may use for "plug-and-play" or diagnostic purpose. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pUserIdStr Return buffer area
+	\param[in] maxBufSize Size of \p pUserIdStr area
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetUserID(
+		multiaddr theMultiAddr,
+		char *pUserIdStr,
+		Uint16 maxBufSize)
+{
+	return netGetUserID(theMultiAddr, pUserIdStr, maxBufSize);
+}
+//																 			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscSetUserID
+//
+//	DESCRIPTION:
+/**
+	Set the User ID for this node. Any ANSI character string maybe used
+	up to 13 characters.
+	
+	This maybe used as an identifier for application "plug-and-play" or
+	diagnostic purposes. If set to NULL, the APS application will apply
+	a generic name "Axis \<addr\>" on its display.  A typical name could
+	be "X Axis".
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewName Ptr to NULL terminated ANSI string.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetUserID(
+		multiaddr theMultiAddr,
+		const char *pNewName)
+{
+	return netSetUserID(theMultiAddr, pNewName);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetMotorFileName
+//
+//	DESCRIPTION:
+/**
+	Get the motor file name for this node. This information is normally
+	maintained by the motor file loading API.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pMotorFileNameStr Ptr to result area.
+	\param[in] maxBufSize Maximum size of the \a pMotorFileNameStr buffer.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetMotorFileName(
+		multiaddr theMultiAddr,
+		char *pMotorFileNameStr,
+		Uint16 maxBufSize)
+{
+	packetbuf nameBuf, cmdBuf;
+	cnErrCode theErr;
+	size_t i;
+	
+	cmdBuf.Byte.Buffer[CMD_LOC] = ISC_CMD_MOTOR_FILE;
+	for(i=CMD_LOC+1; i<(MN_FILENAME_SIZE+CMD_LOC+1); i++)
+		cmdBuf.Byte.Buffer[i] = 0;
+	cmdBuf.Fld.Addr = theMultiAddr;
+	cmdBuf.Fld.PktLen = 1;
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &cmdBuf, &nameBuf);
+	
+	if (theErr == MN_OK) {
+		// Limit return size to buffer size
+		i = (nameBuf.Fld.PktLen < maxBufSize) 
+			? nameBuf.Fld.PktLen : maxBufSize;
+		strncpy((char *)&pMotorFileNameStr[0], 
+				(const char *)&nameBuf.Byte.Buffer[CMD_LOC], i);
+		pMotorFileNameStr[i] = 0;				// Insure term'd
+	}
+	else {
+		pMotorFileNameStr[0] = 0;
+	}
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+/// \cond INTERNAL_DOC
+//******************************************************************************
+//	NAME																	   *
+//		iscSetMotorFileName
+//
+//	DESCRIPTION:
+/**
+	Set the motor file name for this node. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pNewName Ptr null terminated ANSI string up to 25 characters in
+				length. 
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscSetMotorFileName(
+		multiaddr theMultiAddr,
+		const char *pNewName)
+{
+	packetbuf nameBuf, respBuf;
+	size_t i;
+	size_t nSize = strlen(pNewName);
+	cnErrCode theErr = MN_OK;
+	
+	if (pNewName == NULL) 
+		return(MN_ERR_BADARG);
+		
+	if (nSize > MN_FILENAME_SIZE) nSize = MN_FILENAME_SIZE;
+
+	// Clear out buffer with 0 padding
+	for(i=nSize; i<MN_FILENAME_SIZE; i++)
+		nameBuf.Byte.Buffer[i+CMD_LOC+1] = 0;
+
+	nameBuf.Byte.Buffer[CMD_LOC] = ISC_CMD_MOTOR_FILE;
+	// Cmd Byte + Motor File Octets
+	nameBuf.Fld.PktLen = 1+MN_FILENAME_SIZE;
+	nameBuf.Fld.Addr = theMultiAddr;
+	strncpy((char *)&nameBuf.Byte.Buffer[CMD_LOC+1], 
+			(char *)&pNewName[0], nSize);
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &nameBuf, &respBuf); 
+
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+/// \endcond
+
+
+//******************************************************************************
+//	NAME																	   *
+//		iscGetIEXStatus
+//
+//	DESCRIPTION:
+/**
+	Get the current IEX status info.  This includes its operation state as well
+	as diagnostic information on the health of the IEX link.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pIexStatus	Ptr to the returned status area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetIEXStatus(
+			multiaddr theMultiAddr,			// Node address
+			iexStatusReg *pIexStatus)		// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+
+	theErr = iscGetParameterEx(theMultiAddr, ISC_P_IEX_STATUS, &paramVal, NULL);
+	// Overlay buffer with struct
+	register iexStatusReg *pBuf 
+		= reinterpret_cast<iexStatusReg *>(&paramVal.raw.Byte.Buffer[0]);
+	*pIexStatus = *pBuf;
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscRestartIEX
+//
+/**
+	Restart the IEX feature. This typically required after an IEX link 
+	disruption.
+
+	\param[in] theMultiAddr The address code for this node.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+MN_EXPORT cnErrCode MN_DECL iscRestartIEX(
+			multiaddr theMultiAddr)	// Target node addr
+{
+	cnErrCode theErr = MN_OK;
+	iscHwConfigReg hwConfig;
+	int readCnt;
+
+	//Get the current HW Config Register
+	theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	//Tell the IEX to stop
+	hwConfig.Fld.IEXstop = 1;
+	theErr = iscSetHwConfigReg(theMultiAddr, hwConfig);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	//Make sure it took
+	readCnt = 0;
+	theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+	if (theErr != MN_OK)
+		return(theErr);
+	while (hwConfig.Fld.IEXstop == 0){
+		//only try for a few times
+		if (++readCnt > 3)
+			return MN_ERR_CMD_CMD_UNK;
+		theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+		if (theErr != MN_OK)
+			return(theErr);
+	}
+
+	//Tell the IEX to get going again
+	hwConfig.Fld.IEXstop = 0;
+
+	//Write the new config to the drive
+	theErr = iscSetHwConfigReg(theMultiAddr, hwConfig);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	//make sure it took
+	readCnt = 0;
+	theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+	if (theErr != MN_OK)
+		return(theErr);
+	while (hwConfig.Fld.IEXstop){
+		//only try for a few times
+		if (++readCnt > 3)
+			return MN_ERR_CMD_CMD_UNK;
+		theErr = iscGetHwConfigReg(theMultiAddr, &hwConfig);
+		if (theErr != MN_OK)
+			return(theErr);
+	}
+
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkVelMove
+//
+//	HISTORY
+//      Created 11/18/1998 10:17:56 AM
+//		adopted VB on 08/16/1999 14:04:40
+//
+//	DESCRIPTION:
+/**
+	Sends a move that ramps up or down in speed to \a velTargetStepPerSec 
+	(using the previously set limits for acceleration and jerk [RAS]).
+
+	Program execution does not suspend.  Once target velocity is achieved, the
+	move stays there until explicitly changed. The velocity is specified
+	as steps/second.
+
+	Setting the \a triggered parameter true will cause the move to await
+	a trigger event before starting.
+
+	\see \ref ISCtriggerRefPage Starting Triggered Moves
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] velTargetStepPerSec Target velocity in encoder steps per second
+		units.
+	\param[in] triggered Set this parameter to download the move and await a 
+		trigger event.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkVelMove(
+			multiaddr theMultiAddr,		// Destination node
+			double velTargetStepPerSec,	// Target velocity (steps/sec)
+			nodebool triggered)			// Start move with trigger
+{
+
+	return(iscForkMoveVelEx(theMultiAddr, velTargetStepPerSec, 0,
+					triggered ? MG_MOVE_VEL_STYLE_TRIG : MG_MOVE_VEL_STYLE));
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkSkylineMove
+//
+//	DESCRIPTION:
+/**
+	This function allows access to the skyline move command. This function
+	does not block host execution.
+
+    \copydetails ISCmoveSkylinePage
+
+	\see \ref ISCmoveDonePage
+	\see #mnStatusReg Node Status Register
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] velTargetStepPerSec Target velocity magnitude in encoder 
+		steps per second units.
+	\param[in] positionSpec End of the velocity segment position target. This
+		is either an offset from the current commanded position at the start 
+		of the move or an absolute position depending on the \a moveType.
+	\param[in] moveType This parameter selects the move style and optional
+		modes, such as triggering and positional value processing.
+	\param[out] pBuffersRemaining Pointer to location updated with the move
+		buffer count remaining.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkSkylineMove(
+			multiaddr theMultiAddr,			// The node
+			double velTargetStepPerSec,		// Target velocity (steps/sec)
+			nodelong positionSpec,				// Position Target
+			mgVelStyle moveType,			// Enhanced style selection
+			nodelong *pBuffersRemaining)		// Ptr to move buf remaining cnt
+{
+	packetbuf cmd, resp;			// Input and output buffers
+	netaddr cNum;
+	double velScale, velTarg;
+	nodelong iVelTarg;
+	cnErrCode theErr = MN_OK;
+
+	if (!pBuffersRemaining)
+		return(MN_ERR_BADARG);
+
+	// Get sample rate as basis for ticks/sample
+    theErr = iscGetParameter(theMultiAddr, ISC_P_SAMPLE_PERIOD, &velScale);
+	if (theErr == MN_OK) {
+		// TODO convert to use most net efficient form of command
+		cNum = coreController(theMultiAddr);
+		cmd.Fld.Addr = theMultiAddr;	
+		// Len=cmd byte, 4 bytes target vel, mode byte
+		cmd.Fld.PktLen = 1 + sizeof(iVelTarg) + 1;
+		cmd.Byte.Buffer[CMD_LOC] = ISC_CMD_MOVE_VEL_EX;
+		velTarg = (nodelong)(0.5 + (velTargetStepPerSec * ISC_VEL_MOVE_SCALE * velScale 
+									   / 1000000.));
+		// Saturate test
+		/// \cond INTERNAL_DOC
+		#define MAX_VEL_Q 31
+		/// \endcond
+		if (velTarg > (1LL<<MAX_VEL_Q)-1)
+			velTarg = (1LL<<MAX_VEL_Q)-1;
+		else if(velTarg < (-1LL<<MAX_VEL_Q))
+			velTarg  = -1LL<<MAX_VEL_Q;
+		// Save as long integer bits
+		iVelTarg = (nodelong)velTarg;
+		// copy the position target into the command buffer
+		memcpy(&cmd.Byte.Buffer[CMD_LOC+1], &iVelTarg, sizeof(iVelTarg));
+		// Copy move type over
+		cmd.Byte.Buffer[CMD_LOC+5] = (nodechar)moveType.styleCode;
+		// If positional involved
+		if (positionSpec) {
+			memcpy(&cmd.Byte.Buffer[CMD_LOC+6], &positionSpec, 
+											    sizeof(positionSpec));
+			cmd.Fld.PktLen += sizeof(positionSpec);
+		}
+		// Run the command and await the response
+		theErr = netRunCommand(cNum, &cmd, &resp);
+		// Extract off the remaining buffers
+		*pBuffersRemaining = resp.Byte.Buffer[RESP_LOC];
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkMoveEx
+//
+//	DESCRIPTION:
+/**
+	This is the main function to initiate a positional move with 
+	no buffer management. The motion is constrained to the settings of
+	the acceleration, velocity and jerk limits.  For the more
+	complex head and tail moves the additional constraints of head and
+	tail distances as well as head/tail velocity limits apply. Once this
+	move has been accepted, any constraints values changed will
+	apply only to the next move segment.
+
+	The \a moveType field is most easily supplied a #mgPosnStyles enumeration
+	type. This #mgPosnStyle provides a copy constructor to allow direct
+	use of this enumeration.
+
+	A C example for issuing a head/tail absolute position move.
+	\code
+	theErr = iscForkMoveEx(m_nodeAddr, target, MG_MOVE_STYLE_HEADTAIL_ABS);
+	\endcode 
+
+	\see \ref mgPosnStyles for information on the various profiles.
+	\see \ref ISCtriggerRefPage Starting Triggered Moves
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] posnTarget Target position. If this is a relative type move 
+		then this is the increment from the initial position. If this is 
+		and absolute move, then this is the final location.
+	\param[in] moveType The move style. This is a bit oriented value that
+		specifies the profile, triggering event handling and the handling 
+		of the target.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkMoveEx(	// Move with no buffer management
+			multiaddr theMultiAddr,			// Destination node
+			nodelong posnTarget,			// Target (steps)
+			mgPosnStyle moveType)
+{
+	mgMoveProfiledInfo spec;
+	spec.value = posnTarget;
+	spec.type = moveType.styleCode;
+	return(iscMoveProfiled(theMultiAddr, &spec));
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscForkMoveQueued
+//
+//	DESCRIPTION:
+/**
+	This is the main function to initiate a positional moves and inquire
+	on how many more pending moves the node will accept. 
+
+	The motion is constrained to the settings of the acceleration, velocity
+	and jerk limits.  For the more complex head and tail moves the additional
+	constraints of head and tail distances as well as head/tail velocity
+	limits apply. Once this move has been accepted, any constraints values
+	changed will apply only to the next move segment.
+
+	This function is similar to the #iscForkMoveEx function and only
+	differs from it in that the remaining buffer level is returned on
+	each call. This facilitates the queuing of additional moves.
+
+	The \a moveType field is most easily supplied a #mgPosnStyles enumeration
+	type. This #mgPosnStyle provides a copy constructor to allow direct
+	use of this enumeration.
+
+	A C example for issuing a head/tail absolute position move.
+	\code
+	theErr = iscForkMoveQueued(m_nodeAddr, target, MG_MOVE_STYLE_HEADTAIL_ABS, &nMovesLeft);
+	\endcode 
+
+	\see \ref mgPosnStyles for information on the various profiles.
+	\see \ref ISCtriggerRefPage Starting Triggered Moves
+
+	\remark If a triggered move is accepted in a "stream" of other non-triggered
+	moves, it will block upon its execution until a new trigger event
+	occurs.
+
+    \note This feature is only available on firmware version 5.5 and later.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] posnTarget Target position. If this is a relative type move 
+		then this is the increment from the initial position. If this is 
+		and absolute move, then this is the final location.
+	\param[in] moveType The move style. This is a bit oriented value that
+		specifies the profile, triggering event handling and the handling 
+		of the target.
+	\param[out] pBuffersRemaining Pointer to buffers remaining count.
+		Upon return the node will accept up to \a pBuffersRemaining more
+		calls to this function.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscForkMoveQueued(
+			multiaddr theMultiAddr,			// Destination node
+			nodelong posnTarget,				// Target (steps)
+			mgPosnStyle moveType,			// Style code
+			nodelong *pBuffersRemaining)		// Ptr to move buf remaining cnt
+{
+	mgMoveProfiledInfo spec;
+	spec.value = posnTarget;
+	spec.type = moveType.styleCode;
+	return(iscMoveProfiledQueued(theMultiAddr, &spec, pBuffersRemaining));
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		iscGetDataCollected
+//
+//	DESCRIPTION:
+/**		
+	Return consolidated motion quality data. 
+
+	This command will return a consolidated set of data related to 
+	the monitor port variable as well as motion tracking. The node collects
+	mean squared low and high pass data as well as the maximum low pass value 
+	encountered	since the last command request.	 The motion tracking collects
+	the maximum negative and positive tracking from the command.
+	
+	The tracking data is collected from the last query or only collected
+	during the last move depending on settings in the #iscTuneConfigReg register.
+
+	\remark In the "by-move" mode, the values returned are always from the 
+	last completed move. This will allow double-buffered collection for moves
+	who's durations are longer than the request delay.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pReturnData Pointer to a \a pReturnData structure to return
+		the collected data.
+
+	\return
+		#cnErrCode; MN_OK if successful and all data has been updated.
+		MN_ERR_PARAM_RANGE if motion was too long of there was overflow
+		detected on a parameter return. 
+
+	\see #iscTuneConfigReg for detailed field defintions.
+ 
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL iscGetDataCollected(
+			multiaddr theMultiAddr,			// Destination node
+			iscDataCollect *pReturnData)	// Returned data
+{
+	return (netGetDataCollected(theMultiAddr, pReturnData));
+}
+//																			  *
+//*****************************************************************************
+
+
+/// @}
+// if ISC_DOC
+/// \endcond
+//==============================================================================
+//	END OF FILE iscAPI.cpp
+//==============================================================================
+#endif
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/lnkAccessCommon.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/lnkAccessCommon.cpp
new file mode 100644
index 000000000..15369b01a
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/lnkAccessCommon.cpp
@@ -0,0 +1,8049 @@
+//******************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/lnkAccessCommon.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: lnkAccessCommon.cpp $
+//
+// DESCRIPTION:
+/**
+\file
+\cond INTERNAL_DOC
+\brief Low Level Link Function Programming Interface Implementation.
+
+Implements the programming interfaces related to link wide functionality.
+
+\addtogroup LinkGrp
+\brief Channel Access API
+- Include "meridianHdrs.h" in your project to use these functions.
+
+These functions are related to channel operation activities. They provide
+for creating a diagnostic dump file of the last 4096 commands and access
+to event driven Attention Packet receptions.
+
+
+Platform independent low level packet driver for Meridian Networks.
+All coding in this module uses generic C++ or platform virtualizing
+classes to interface to a target operating system.
+
+Each "controller" represents a network of Meridian Nodes connected via
+a asynchronous serial port. The controller number starts at zero and
+represents the first net. The actual port number is specified at
+startup time.
+
+The port is is assumed offline until and "initializing" event occurs.
+Usually this is initiated via the mnInitializeNets functions.
+The controller is "started" when the port and associated resources
+are created and opened.
+
+Threads are created to read responses, run diagnostics and a number of
+"housekeeping" threads for tracking responses.
+A number of event objects are created to allow the various parts of the
+driver to "sync" up with the actions of the application and the driver
+itself.
+
+Threaded commands that require a response are parked via an unsignaled
+event object until the read thread detects and matches it up with this
+command.
+
+Multiple command starts can be initiated at once and are paced via
+a semaphore. As responses are received, another command is allowed to
+start.
+
+When an error is detected, all application threads are blocked via
+an unsignalled event object and the error recovery thread is invoked
+to detect network restoration. Network diagnostics are performed and
+the results sent to the application via callback. If the disruption
+persists, the application will periodically be notified of the current
+diagnostic results.
+
+On network restoration, the configuration is checked for changes and
+if appears the same, the application is notified that network is online
+and the block on existing traffic is released.
+
+If the LPT port interrupts are available, they are used to pace the
+sending and receiving of packets. This allows a minimum of polling
+in the driver and prevents the high priority threads from "spinning"
+out on hardware or power-failures.
+
+MNCLASSEX EVENTS
+NODES_OFFLINE
+Initial state until initialization or the state that occurs
+when network errors have been detected.	 Network traffic attempts
+are failed with code MN_ERR_CMD_OFFLINE.
+NODES_ONLINE
+After initialization this state is signalled to allow the
+application to interact with the network.
+NODES_ONLINE_NO_TEST
+After initialization this state is signalled to allow the
+application to interact with the network when older firmware
+has been detected. Interaction is blocked unless the little
+publicized infcSetInitMode function is called to unlock
+the operation with older firmware. This feature is used by
+our diagnostic software as well as the RPE to allow interaction
+with older nets.
+NODES_RESETTING
+This event is fired at the start of an initializing or resetting
+operation.
+NODES_SENDING
+This event is sent during the resetting phase to signal
+the collection of node information has begun. A NODES_ONLINE
+event usually follows if this process completes without error.
+NODES_NO_PORT
+This event is sent if the initializing function cannot open
+the NT device driver for this port.
+NODES_NO_NET_CONTROLLER
+This event is sent if the initializing function cannot find
+a Network Controller.
+NODES_CHANGING_NET_CONTROLLER
+This event is sent to the current controller as well as the
+new controller the current controller is changed.
+**/
+// CREATION DATE:
+//		02/08/2010 13:20:40
+//
+// COPYRIGHT NOTICE:
+//		02/11/1998 16:34:00 Original ControlPoint implementation
+//		06/09/2009 17:39 Refactored from ControlPoint implementation
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+/// \endcond																   *
+//******************************************************************************
+
+/// \cond INTERNAL_DOC
+//******************************************************************************
+// NAME																	       *
+// 	lnkAccessCommon.cpp headers
+//
+#include "lnkAccessCommon.h"
+#include "netCmdPrivate.h"
+#include "SerialEx.h"
+#include "netCmdAPI.h"
+// Std Library
+#include <fstream>
+// System include files
+#include <assert.h>
+#if (defined(_WIN32)||defined(_WIN64))
+#include <direct.h>
+#include <crtdbg.h>
+#else
+#include <stdlib.h>
+#include <string.h>
+#include <sys/stat.h>
+#endif
+/// \endcond																   *
+//******************************************************************************
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+// NAME																	       *
+// 	lnkAccessCommon.cpp local function prototypes
+//
+//
+#ifndef _WIN32
+int GetLastError() {
+	return 1;
+}
+#endif
+
+void infcCopyPktToPkt18(
+	packetbuf18 *dest,
+	packetbuf *src);
+
+// Process a node initiate packet such as attentions and errors
+void processNodeInitiatedPkt(netaddr cNum, nodeaddr respAddr,
+	netStateInfo *pNCS, packetbuf &readBuf);
+
+// Process an attention packet
+void processAttention(mnAttnReqReg theAttn, netStateInfo *pNCS);
+
+// Start the node auto-discovery process
+void autoDiscoverStart(infcErrInfo *pErrInfo);
+void autoDiscoverStart(netaddr cNum, cnErrCode theErr);
+void attemptAutoDiscover(infcErrInfo *pErrInfo);
+
+cnErrCode MN_DECL infcChangeLinkSpeed(
+	netaddr cNum,
+	netRates newRate);
+
+/// \endcond																   *
+//******************************************************************************
+
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+// NAME																	       *
+// 	lnkAccessCommon.cpp constants
+//
+//
+#if defined (__GNUC__)
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+// Time between net re-discovery attempts
+const unsigned AUTODISCOVER_WAIT_MS = 500;
+// Wrap around value (%d) for dump files: "root%d.ext"
+#define DUMP_WRAP_NUM			10
+//- - - - - - - - - - - - - - - - - - - -
+// TRACING/DEBUG SETUP
+//- - - - - - - - - - - - - - - - - - - -
+#if defined(_MSC_VER)
+#define DBG_LOG(x) OutputDebugString(_T(x))
+#else
+#define DBG_LOG(x)
+#endif
+
+#ifdef _DEBUG
+#define T_ON TRUE
+#else
+#define T_ON FALSE
+#endif
+#define T_OFF FALSE
+
+#define TRACE_LOW_PRINT			T_OFF	// Print low level activities
+#ifndef TRACE_SEND_RESP
+#define TRACE_SEND_RESP			T_OFF	// Print commands/responses
+#endif
+#define TRACE_HIGH_LEVEL		T_OFF	// Print high level activities
+#define TRACE_RD_THRD			T_OFF	// Print high level read thread activities
+#define TRACE_POLL_THRD			T_OFF	// Print polling thread activities
+#define TRACE_START_STOP		T_OFF	// Print controller start/stop events
+#define TRACE_ERR_HNDL			T_OFF	// Print error handler actions
+#define TRACE_TICKLER			T_OFF	// Print tickler actions
+#define TRACE_LOCKS				T_OFF	// Trace cmd lock
+#define TRACE_CALLBACK			T_OFF	// Trace callback functions
+#define TRACE_HEAP				T_OFF	// Enable heap tracing
+#define TRACE_IRQ				T_OFF	// Trace interrupt / HIGH LEVEL
+#define TRACE_THREAD			T_OFF	// Thread create/exit IDs
+#define TRACE_HALT				T_OFF	// Force printing of just read thread actions
+#define TRACE_SERIAL			T_OFF	// Trace serial/flash API
+#define TRACE_ATTN				T_OFF	// Trace attentions recv'd
+#define TRACE_DESTRUCT			T_OFF	// Trace construction/destruction
+#define TRACE_DACQ_SEQ			T_OFF	// Trace data acq sequence issues
+#define TRACE_BAUD				T_OFF	// Trace baud rate changes
+#define TRACE_NET_ERR			T_ON	// Dump net error packets
+#define TRACE_SIZES				T_OFF	// Dump base type sizes
+#define TRACE_BRAKE				T_OFF	// Trace brake actions
+#define TRACE_BREAK				T_OFF	// Trace serial port breaks sent
+#define TRACE_NET_NATIVE		T_OFF	// Show link layer as raw bytes
+#define TRACE_FLUSH				T_OFF	// Show flush activities
+
+#ifndef COMM_EVT_MAX_MS
+#define COMM_EVT_BRK_DLY_MS 100
+#endif
+
+#if TRACE_LOCKS
+#define ENTER_LOCK(where) \
+	_RPT2(_CRT_WARN, "%.1f enterLock	%s\n", infcCoreTime(), where); pNCS->enterCmdLock();
+#define EXIT_LOCK(where) \
+	_RPT2(_CRT_WARN, "%.1f exitLock	%s\n", infcCoreTime(), where); pNCS->exitCmdLock();
+#else
+#define ENTER_LOCK(where) pNCS->enterCmdLock()
+#define EXIT_LOCK(where) pNCS->exitCmdLock()
+#endif
+
+#ifdef __linux
+#ifdef __LP64__
+	#define THREAD_RADIX "0x%x"
+	#define THREAD_RADIX_LONG "0x%lx"
+#else
+	#define THREAD_RADIX "%d"
+	#define THREAD_RADIX_LONG "%ld"
+#endif
+#else
+	#define THREAD_RADIX "0x%x"
+	#define THREAD_RADIX_LONG "0x%lx"
+#endif
+
+// Power Types
+#define PWR_CNT 8
+const char *pwrTypes[PWR_CNT] = {
+	"None", "X", "Y", "XY", "Z", "XZ", "YZ", "XYZ"
+};
+/// \endcond																   *
+//******************************************************************************
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+// NAME																	       *
+// 	lnkAccessCommon.cpp static variables
+//
+//
+///////////////////////
+// Callback pointers //
+///////////////////////
+
+// Error reporting function
+infcErrCallback userErrCallbackFunc = NULL;
+// Command completion function
+infcCmdCompleteCallback userCmdCompleteFunc = NULL;
+// Network State change callback
+infcNetStateCallback userNetStateFunc = NULL;
+// Invalidate cache function
+infcInvalCacheCallback userInvalCacheFunc = NULL;
+/// \endcond																   *
+//******************************************************************************
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+// NAME																	       *
+// 	lnkAccessCommon.cpp global variables
+//
+// Global access to network state instances
+//netStateInfo *pNet[NET_CONTROLLER_MAX] = {NULL};
+
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// These might be overwritten by OS specific persistance mechanism
+// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+// Create a trace dump on exit of library
+BOOL InfcDumpOnExit = TRUE;
+// Global time-out setting
+unsigned InfcRespTimeOut = FRAME_READ_TIMEOUT + FRAME_READ_TIMEOUT / 8;
+// Default read thread priority
+int InfcPrioBoostFactor = 0;
+// Last dump file number
+unsigned InfcLastDumpNumber = 0;
+// Inhibits running diagnostics
+BOOL InfcDiagnosticsOn = TRUE;
+// When non-zero, the system is initializing. This should always
+// equal the sum of the SysInventory[*].Initializing
+int InitializingGlobal = 0;
+/// \endcond																   *
+//******************************************************************************
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+// NAME																	       *
+// 	lnkAccessCommon.cpp imported variables
+//
+//
+// Count of specified ports
+extern unsigned SysPortCount;
+// Inventory records of where nodes are
+extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+
+// State that maybe restored via offline persistance
+extern BOOL InfcDiagnosticsOn;			// Inhibits running diagnostics
+extern unsigned InfcLastDumpNumber;		// Last Dump File number
+extern unsigned InfcRespTimeOut;		// Response time-out setting
+
+										// Global references
+extern mnNetDiagResults NetDiags[NET_CONTROLLER_MAX];
+
+// Variables for debug thread locking
+extern CCEvent debugGate;
+extern CCEvent debugThreadLockResponseGate;
+extern bool inDebugging;
+extern nodeulong lockedThreadID;
+
+/// \endcond																   *
+//******************************************************************************
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+//	NAME																	   *
+//		DUMP_PKT
+//
+//	DESCRIPTION:
+//		Write buffer as hex debug string.
+//
+//	SYNOPSIS:
+void DUMP_PKT(netaddr cNum, const char *msg, packetbuf *buf, bool backArrow)
+{
+	#ifdef _DEBUG
+	unsigned i, bLen;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS)
+		return;
+
+	_RPT5(_CRT_WARN, "%.1f %s(%d) %d: %s ", infcCoreTime(), msg, cNum,
+		(int)pNCS->nRespOutstanding, backArrow ? "<-" : "->");
+	if (buf->Byte.BufferSize > MN_API_PACKET_MAX)
+		bLen = MN_API_PACKET_MAX;
+	else
+		bLen = buf->Byte.BufferSize;
+	#if TRACE_NET_NATIVE
+	packetbuf nativeBuf;
+	unsigned char chksum = 0;
+	_RPT0(_CRT_WARN, "N[");
+	pNCS->pSerialPort->convert8to7(*buf, nativeBuf);
+	nativeBuf.Byte.BufferSize = nativeBuf.Fld.PktLen + MN_API_PACKET_HDR_LEN;
+	for (i = 0; i<nativeBuf.Byte.BufferSize; i++) {
+		chksum -= nativeBuf.Byte.Buffer[i];
+		_RPT1(_CRT_WARN, "%02X ", 0xFF & nativeBuf.Byte.Buffer[i]);
+	}
+	_RPT1(_CRT_WARN, "%02X] ", 0xFF & chksum);
+	#endif
+	for (i = 0; i<bLen; i++) {
+		_RPT1(_CRT_WARN, "%02x ", 0xFF & buf->Byte.Buffer[i]);
+	}
+	_RPT0(_CRT_WARN, "\n");
+	#endif
+}
+/// \endcond																   *
+//******************************************************************************
+
+
+///	\cond INTERNAL_DOC
+//******************************************************************************
+//******************************************************************************
+//						   netStateInfo IMPLEMENTATION
+//******************************************************************************
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::netStateInfo
+//
+//	DESCRIPTION:
+///		Construct the state for a single serial network.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+netStateInfo::netStateInfo(nodeulong ringCmdsMax,
+	netaddr controllerNum)
+	: CmdPaceSemaphore(ringCmdsMax, ringCmdsMax)
+{
+	extern int InfcPrioBoostFactor;					// Read thread prio boost
+	cNum = controllerNum;							// Our index
+	nodeaddr node;
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f netStateInfo(new)(%d) constructing...\n",
+		infcCoreTime(), cNum);
+	#endif
+	#ifdef USE_ACTIVEX
+	mnCookie = 0;
+	mnThreadID = 0;
+	ChangeRecurse = 0;
+	NetChangeMarshalled = TRUE;
+	#endif
+
+	pSerialPort = NULL;						// Insure pointer initialized
+	ctsCount = 0;
+	#ifdef _DEBUG
+	SemaCount = 0;
+	#endif
+	OurNetConnector = MN_SRC_UNKNOWN_NET;
+	ErrListHeadPtr = ErrListTailPtr = 0;
+	NetChgListHeadPtr = NetChgListTailPtr = 0;
+	AttnOverrun = FALSE;					// Nothing in error, yet
+	LastEvent = NODES_OFFLINE;				// We start from offline
+	pAutoDiscover = NULL;
+	// Offline tickler
+	SelfDestruct = false;					// No death yet
+
+	RingCmdsMax = ringCmdsMax;				// Save for destruction time
+											// Adjust select event objects
+	CmdGate.SetEvent();
+	// We start idle
+	CmdsIdle.SetEvent();
+
+	nPktsSent = nPktsRcvd = nRespOutstanding = 0;
+
+	for (node = 0; node<MN_API_MAX_NODES; node++) {
+		// Initialize the node response databases, assuming no waiters
+		respNodeState[node].head = NULL;
+		respNodeState[node].tail = NULL;
+		respNodeState[node].errPkt.Byte.BufferSize = 0;
+		respNodeState[node].sendCnt = 0;
+		respNodeState[node].respCnt = 0;
+
+		//while we're going through the nodes, mark that they haven't been changed
+		paramsHaveChanged[node] = FALSE;
+		// Force init on first data acquisition packet.
+		DataAcqInit[node] = TRUE;
+		// Nothing yet
+		SysInventory[cNum].diagsAvailable[node] = FALSE;
+		SysInventory[cNum].diagStats[node].Clear();
+	}
+	// Nothing yet
+	SysInventory[cNum].diagsAvailable[MN_API_MAX_NODES] = FALSE;
+	// Take care of the host's extra diags slot off the end
+	SysInventory[cNum].diagStats[MN_API_MAX_NODES].Clear();
+
+	controlNodeState.head = NULL;
+	controlNodeState.tail = NULL;
+	controlNodeState.errPkt.Byte.BufferSize = 0;
+	controlNodeState.sendCnt = 0;
+	controlNodeState.respCnt = 0;
+
+	// Create our port
+	pSerialPort = new CSerialEx;
+	#if TRACE_SIZES
+	_RPT2(_CRT_WARN, "CSerialEx size=%d(0x%x)\n",
+		sizeof(CSerialEx), sizeof(CSerialEx));
+	#endif
+	assert(pSerialPort);
+
+	// Create threads
+	ReadThread.SetTerminateFlag(&SelfDestruct);
+
+	// Create trackers for each possible command in progress on this net
+	pTrkFixedList = (respTrackInfo **)malloc(sizeof(respTrackInfo *)*ringCmdsMax);
+	pTrkList = (respTrackInfo **)malloc(sizeof(respTrackInfo *)*ringCmdsMax);
+	for (node = 0; node<ringCmdsMax; node++) {
+		pTrkFixedList[node] = new respTrackInfo;
+		pTrkList[node] = pTrkFixedList[node];
+	}
+	assert(pTrkList);
+	#if TRACE_SIZES
+	_RPT2(_CRT_WARN, "respTrackInfo size=%d(0x%x)\n",
+		sizeof(respTrackInfo)*ringCmdsMax,
+		sizeof(respTrackInfo)*ringCmdsMax);
+	_RPT1(_CRT_WARN, "sizeof(rxTraceBuf)=%d\n", sizeof(rxTraceBuf));
+	_RPT1(_CRT_WARN, "sizeof(txTraceBuf)=%d\n", sizeof(txTraceBuf));
+	_RPT1(_CRT_WARN, "sizeof(traceHeader)=%d\n", sizeof(traceHeader));
+	#endif
+
+	// Insure the tail is initialized
+	pTrkTail = &pTrkList[ringCmdsMax - 1];
+	// Create our discovery thread
+	pAutoDiscover = new autoDiscoverThread;
+	#if TRACE_SIZES
+	_RPT2(_CRT_WARN, "autoDiscover size=%d(0x%x)\n",
+		sizeof(autoDiscoverThread),
+		sizeof(autoDiscoverThread));
+	#endif
+	// Get it started until parking point
+	pAutoDiscover->LaunchThread(this);
+	pAutoDiscover->WaitUntilParked();
+	errorRecursePrevent = 0;
+
+
+	// Lastly, start our read thread now that our state has settled in
+	ReadThread.LaunchThread(this, InfcPrioBoostFactor);
+	// Wait for it to start up and enter "halted" state
+	ReadThread.ForceStop();
+
+	// Initialize the polling rate and start in halted state
+	pollDelayTimeMS = 250;
+	pPollerThread = new	netPollerThread(this);
+	pPollerThread->LaunchThread(this);
+
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f netStateInfo(new)(%d) finished...\n",
+		infcCoreTime(), cNum);
+	#endif
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::~netStateInfo
+//
+//	DESCRIPTION:
+///		Destruct the state for a single serial network.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+netStateInfo::~netStateInfo()
+{
+	//cnErrCode theErr = MN_OK;
+	unsigned i;
+
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	double sTime, eTime;						// Profiling time
+	#endif
+
+												// Bad news see DllMain MSDN definition of not allowing Sync Waits on
+												// threads created with DLL operations. One must set a proxy "exit" event
+												// set just before exit of thread control function to sync with end of
+												// thread activity.  After this event is signalled it will be assumed that
+												// no other activity is generated by the thread function.
+
+												// Prevent more activities on this port
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	sTime = infcCoreTime();
+	_RPT2(_CRT_WARN, "%.1f ~netStateInfo(%d) starting...\n",
+		sTime, cNum);
+	#endif
+	// Wait for commands to terminate
+	if (pSerialPort && pSerialPort->IsOpen())
+		CmdsIdle.WaitFor();
+	// Start all the threads exiting, avoid error on these commands
+	SelfDestruct = TRUE;
+	// Force reporter to start and terminate
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f ~netStateInfo(%d) deleting auto-discover...\n",
+		sTime, cNum);
+	#endif
+	//// Let pending work drain out
+	//if (!Offline) {
+	//	waitForIdle();
+	//}
+	// Allow no more "work"
+	///Offline = TRUE;
+	// Get rid of the auto-discovery to avoid starting new commands
+	if (pAutoDiscover) {
+		delete pAutoDiscover;
+		pAutoDiscover = NULL;
+	}
+
+	if (pPollerThread) {
+		delete pPollerThread;
+		pPollerThread = NULL;
+	}
+
+	// Restart the the waiting responses
+	for (i = 0; i<RingCmdsMax; i++) {
+		// Signal events waiting for responses
+		if (pTrkFixedList && pTrkFixedList[i])
+			pTrkFixedList[i]->evtRespWait.SetEvent();
+	}
+	// Make sure those waiting (re)start
+	IrqEvent.SetEvent();
+	ReadCommEvent.SetEvent();
+	CmdGate.SetEvent();
+	ReadThread.Start();
+
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f ~netStateInfo(%d) about to free node info\n",
+		infcCoreTime(), cNum);
+	#endif
+
+	// Wait for read thread to terminate to prevent access violations
+	ReadThread.WaitForTerm();
+
+	// Done with serial port now
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f ~netStateInfo(%d) deleting serial port\n",
+		infcCoreTime(), cNum);
+	#endif
+	if (pSerialPort) {
+		delete pSerialPort;
+		pSerialPort = NULL;
+	}
+
+	// Free all of our node class memory
+	coreFreeAllNodeInfo(cNum);
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f ~netStateInfo(%d) node info free\n",
+		infcCoreTime(), cNum);
+	#endif
+
+	pTrkTail = NULL;
+	if (pTrkList) {
+		// Return the tracking database memory
+		for (i = 0; i < RingCmdsMax; i++) {
+			pTrkList[i] = NULL;
+		}
+		free(pTrkList);
+		pTrkList = NULL;
+	}
+	if (pTrkFixedList) {
+		// Return the tracking database memory
+		for (i = 0; i < RingCmdsMax; i++) {
+			if (pTrkFixedList[i]) {
+				delete pTrkFixedList[i];
+				pTrkFixedList[i] = NULL;
+			}
+		}
+		free(pTrkFixedList);
+		pTrkFixedList = NULL;
+	}
+
+	// Relieve the Initialization stack in inventory
+	SysInventory[cNum].Initializing = 0;
+
+	// This controller is all deleted
+	#if TRACE_LOW_LEVEL || TRACE_DESTRUCT
+	eTime = infcCoreTime();
+	_RPT3(_CRT_WARN, "%.1f ~netStateInfo(%d) done, duration=%.1f\n",
+		eTime, cNum, eTime - sTime);
+	#endif
+	SysInventory[cNum].clearNodes(true);
+	// Let events propagate
+	infcSleep(0);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::enterCmdLock
+//
+//	DESCRIPTION:
+//		Enter command interface lock section
+//
+//	SYNOPSIS:
+void netStateInfo::enterCmdLock() {
+	if (!cmdLock.Lock()) {
+		_RPT1(_CRT_WARN, "enterCmdLock%d: time-out\n", cNum);
+	}
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::exitCmdLock
+//
+//	DESCRIPTION:
+//		Exit lock section
+//
+//	RETURNS:
+//		MN_OK if sucessfully updated
+//
+//	SYNOPSIS:
+void netStateInfo::exitCmdLock()
+{
+	if (!cmdLock.Unlock()) {
+		_RPT2(_CRT_WARN, "exitCmdLock: semaphore %d release err 0x%X\n",
+			cNum, GetLastError());
+	}
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::isRecoveryThread
+//
+//	DESCRIPTION:
+//		Return true if the current thread is one of the recovery threads.
+//
+//	RETURNS:
+//		bool
+//
+//	SYNOPSIS:
+nodebool netStateInfo::isRecoveryThread()
+{
+	nodeulong curThread = CThread::CurrentThreadID();
+
+	return ((pAutoDiscover && (pAutoDiscover->ThreadID() == curThread)));
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::isReadThread
+//
+//	DESCRIPTION:
+//		Return true if the current thread is the read thread.
+//
+//	RETURNS:
+//		bool
+//
+//	SYNOPSIS:
+nodebool netStateInfo::isReadThread()
+{
+	nodeulong curThread = CThread::CurrentThreadID();
+
+	return ((ReadThread.ThreadID() == curThread));
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::logSend
+//
+//	DESCRIPTION:
+//		Log the sent item and return the TX serial number.
+//
+//	RETURNS:
+//		this entry's serial number
+//
+//	SYNOPSIS:
+unsigned mnNetInvRecords::logSend(packetbuf *cmd, cnErrCode theErr, double timeStamp)
+{
+	unsigned nextSerNum = sendSerNum, indx;
+	if (!pNCS) return nextSerNum;
+	TXlogLock.Lock();
+	// Save and increment the serial number
+	nextSerNum = sendSerNum++;
+	// Wrap the log file index
+	indx = nextSerNum % SEND_DEPTH;
+	// Setup issues!
+	assert(txTraces);
+
+	if (TraceActive) {
+		txTraceBuf *pTxTrace;					// Pointer to tx traces
+												// Make shortcut to transmit trace log entry for the rest of command
+		pTxTrace = &txTraces[indx];
+		txTraceIndx = indx;
+		// Log the send number
+		pTxTrace->order = nextSerNum;
+		// Log when it left here
+		pTxTrace->timeStamp = timeStamp;
+		// Log the command itself
+		pTxTrace->packet = *cmd;
+		// Log command depth
+		pTxTrace->depth = pNCS->nRespOutstanding;
+		// Log as a failure
+		pTxTrace->failed = (unsigned short)theErr;
+	}
+	TXlogLock.Unlock();
+	#if defined(_DEBUG)
+	if (theErr != MN_OK) {
+		_RPT3(_CRT_WARN, "%.1f TX Error(%d): 0x%x\n", infcCoreTime(), pNCS->cNum, theErr);
+		DUMP_PKT(pNCS->cNum, "...", cmd);
+	}
+	#endif
+	return(nextSerNum);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::logReceive
+//
+//	DESCRIPTION:
+//		Log a receive packet.
+//
+//	RETURNS:
+//		elapsed command time if known, else 0
+//
+//	SYNOPSIS:
+double mnNetInvRecords::logReceive(
+	packetbuf *readBuf,
+	cnErrCode theErr,
+	respTrackInfo *fillInfo,
+	double timeStamp)
+{
+	size_t rxSerNum, rxTraceIndex;
+	rxTraceBuf *pRXtrc;
+	txTraceBuf *pTXtrc;
+	double eTime = 0;
+	if (!pNCS) return 0;
+	// Setup issues!
+	assert(rxTraces);
+	assert(txTraces);
+
+	RXlogLock.Lock();
+	rxSerNum = respSerNum++;
+	// Wrap the log item
+	rxTraceIndex = rxTraceIndx = rxSerNum % RECV_DEPTH;
+	// Setup "shortcuts"
+	pRXtrc = &rxTraces[rxTraceIndex];
+	// Do actual tracing work if turned on
+	if (TraceActive) {
+		// Log the serial number of received packet
+		pRXtrc->order = (Uint32)rxSerNum;
+		// Log the receipt time
+		pRXtrc->timeStamp = timeStamp;
+		// Log the packet
+		pRXtrc->packet = *readBuf;
+		if (fillInfo) {
+			// Expected a response here
+			pTXtrc = &txTraces[fillInfo->sendSerNum%SEND_DEPTH];
+			pRXtrc->sendCnt = fillInfo->nSentAtAddr;
+			pRXtrc->sendSer = fillInfo->sendSerNum;
+			eTime = pRXtrc->timeStamp - pTXtrc->timeStamp;
+		}
+		else {
+			// Unexpected response or error
+			pRXtrc->sendCnt = -1;
+			pRXtrc->sendSer = -1;
+		}
+	}
+	// Record the error code
+	pRXtrc->error = theErr;
+	RXlogLock.Unlock();
+	#if 1 //defined(_DEBUG)
+	//	if (theErr != MN_OK) {
+	if (theErr != MN_OK && pNCS->cNum == 1) {
+		_RPT4(_CRT_WARN, "%.1f RX Error(%d): 0x%x, thread=" THREAD_RADIX_LONG "\n",
+			infcCoreTime(), pNCS->cNum, theErr, infcThreadID());
+	}
+	#endif
+	return(eTime);
+}
+//																			   *
+//******************************************************************************
+
+
+//****************************************************************************
+//	NAME																	 *
+//		netStateInfo::removeHeadDBitem
+//
+//	DESCRIPTION:
+//		Remove the head item from the <respArea> nodelist and relieve the
+//		command pacing semaphore by one item.
+//
+// 		NOTE: The response database should be locked when this function is
+//		called.
+//
+//	SYNOPSIS:
+void netStateInfo::removeHeadDBitem(
+	respNodeList *pRespArea)
+{
+	respTrackInfo *pThisInfo, *pNextInfo;		// Parsers of response DB
+	BOOL dataOK;
+
+	// No node list
+	if ((pRespArea == NULL) || (pRespArea->head == NULL)) {
+		_RPT0(_CRT_WARN, "removeHeadDBitem: NULL response or head!\n");
+		return;
+	}
+
+	// Init parsers
+	pThisInfo = pRespArea->head;
+	pNextInfo = pThisInfo->next;
+	// Unlink the head and point at tail
+	pRespArea->head = pNextInfo;
+	if (pRespArea->head == NULL) {
+		// Clean up our tail if we are empty
+		pRespArea->tail = NULL;
+	}
+	// Signal we have something
+	//if (pThisInfo->evtRespWait.isOK()) {
+	//_RPT2(_CRT_WARN," removeHeadDB wait event set hndl=0x%0x, %.2f\n",
+	//	pThisInfo->hRespWait, infcCoreTime());
+	pThisInfo->evtRespWait.SetEvent();
+	// Synchronize with others waiting
+	pThisInfo->evtRespWait.WaitFor();
+	//}
+	// Return this tracker to pool
+	++pTrkTail;					// Create space at the end
+	*pTrkTail = pThisInfo;
+	// Release the command semaphore allowing one more
+	//_RPT1(_CRT_WARN, "returnHead @ 0x%x\n", pThisInfo);
+	//_RPT2(_CRT_WARN, "Release PACE(removeDBhead) cmd=%d rank=%d\n", pThisInfo->sendSerNum, nRespOutstanding);
+	// There is one less to expect now
+	#if defined(_DEBUG)
+	dataOK = CmdPaceSemaphore.Unlock(1, &SemaCount);
+	//if ((SysInventory[cNum].NumCmdsInRing-SemaCount)!=nRespOutstanding) {
+	//	_RPT3(_CRT_WARN,"%.1f removeHeadDBitem semaphore mismatch! @%d we think %d\n",
+	//			infcCoreTime(), (SysInventory[cNum].NumCmdsInRing-SemaCount),
+	//			nRespOutstanding);
+	//}
+	#else
+	dataOK = CmdPaceSemaphore.Unlock();
+	#endif
+	if (dataOK) {
+		// Make sure the read thread keeps running
+		if (nRespOutstanding > 0)
+			if (--nRespOutstanding > 0)
+				ReadThread.Start();
+	}
+	else {
+		infcErrInfo semaErr;
+		int semaErrCode = GetLastError();
+		semaErr.errCode = MN_ERR_SEND_UNLOCK;
+		semaErr.cNum = cNum;
+		semaErr.node = semaErrCode;
+		infcFireErrCallback(&semaErr);
+		_RPT1(_CRT_ERROR, "removeHeadDBitem: semaphore release err 0x%X\n",
+			semaErrCode);
+	}
+	//_RPT1(_CRT_WARN, "returnThis @ 0x%x\n", pThisInfo);
+}
+//																			 *
+//****************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::removeThisDBitem
+//
+//	DESCRIPTION:
+//		This is the function called to remove a database item from the running
+//		queue. The command pacing semaphore is relieved by one item.
+//
+// 		NOTE: The response database should be locked when this function is
+//		called.
+//
+//	SYNOPSIS:
+void netStateInfo::removeThisDBitem(
+	respTrackInfo *pRespInfo,
+	respNodeList *pRespArea)
+{
+	respTrackInfo *pThisInfo, *pLastInfo;		// Parsers of response DB
+	BOOL dataOK;
+
+	// No node list
+	if ((pRespArea == NULL) || (pRespInfo == NULL) || pRespArea->head == NULL)
+		return;
+
+	// Init parsers
+	pThisInfo = pLastInfo = pRespArea->head;
+	// Track down database links looking for us
+	while (pThisInfo != NULL) {
+		if (pThisInfo == pRespInfo) {
+			// It's us, remove our entry, are we head?
+			if (pThisInfo == pRespArea->head) {
+				// Yes, change head to next
+				pRespArea->head = pRespInfo->next;
+			}
+			else {
+				// Unlink us from the chain
+				pLastInfo->next = pThisInfo->next;
+			}
+			// Clean up the tail, if we are it
+			if (pRespInfo == pRespArea->tail) {
+				pRespArea->tail = NULL;
+			}
+			break;
+		}
+		// Look at the next item in the list
+		pLastInfo = pThisInfo;
+		pThisInfo = pThisInfo->next;
+	}
+	if (pThisInfo == NULL) {
+		// Item not found!
+		_RPT0(_CRT_WARN, "removeDB did not find our item!\n");
+		return;
+	}
+	// Signal we have something
+	if (pRespInfo->evtRespWait.isOK()) {
+		#if TRACE_LOW_PRINT
+		_RPT2(_CRT_WARN, "%.1f removeDB wait event set hndl=0x%0lx\n",
+			infcCoreTime(), reinterpret_cast<long>(pRespInfo->evtRespWait.GetHandle()));
+		#endif
+		pRespInfo->evtRespWait.SetEvent();
+		// Synchronize with others waiting
+		pRespInfo->evtRespWait.WaitFor();
+	}
+	// Return this tracker to the end of the pool
+	++pTrkTail;
+	*pTrkTail = pRespInfo;
+	//_RPT1(_CRT_WARN, "returnThis @ 0x%x\n", pRespInfo);
+	// Release the command semaphore allowing one more
+	//_RPT2(_CRT_WARN, "Release PACE(removeDB) cmd=%d rank=%d\n", pRespInfo->sendSerNum, nRespOutstanding);
+	// There is one less to expect now
+	#ifdef _DEBUG
+	dataOK = CmdPaceSemaphore.Unlock(1, &SemaCount);
+	#else
+	dataOK = CmdPaceSemaphore.Unlock();
+	#endif
+	if (dataOK) {
+		if (nRespOutstanding > 0)
+			if (--nRespOutstanding > 0)
+				ReadThread.Start();
+		//_RPT1(_CRT_WARN, "RemoveFromDB outstanding=%d\n",
+		//				(int)nRespOutstanding);
+	}
+	else {
+		infcErrInfo semaErr;
+		int semaErrCode = GetLastError();
+		semaErr.errCode = MN_ERR_SEND_UNLOCK;
+		semaErr.cNum = cNum;
+		semaErr.node = semaErrCode;
+		infcFireErrCallback(&semaErr);
+		_RPT1(_CRT_ERROR, "removeThisDBitem: semaphore release err 0x%X\n",
+			semaErrCode);
+	}
+
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netStateInfo::waitForIdle
+//
+//	DESCRIPTION:
+//		Wait for all the network history to time-out.
+//
+//	SYNOPSIS:
+void netStateInfo::waitForIdle()
+{
+	while (ReadThread.IsRunning() && !SelfDestruct && nRespOutstanding > 0) {
+		infcSleep(100);
+	}
+}
+/// \endcond																  *
+//*****************************************************************************
+
+
+//******************************************************************************
+//******************************************************************************
+//						readPktThread IMPLEMENTATION
+//******************************************************************************
+///	\cond INTERNAL_DOC
+//******************************************************************************
+//	NAME																	   *
+//		readPktThread construction/destruction
+//
+//	DESCRIPTION:
+///
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+readPktThread::readPktThread()
+{
+	#if TRACE_THREAD || TRACE_DESTRUCT
+	_RPT1(_CRT_WARN, "%.1f readPktThread constructing\n",
+		infcCoreTime());
+	#endif
+	#if (defined(_WIN32)||defined(_WIN64))
+	SetDLLterm(true);
+	#endif
+	// 4/29/11 DS Leads to issues with Win7 UseWithCOM();
+	pNCS = NULL;
+	// Insure we halt at HALTED state
+	m_InternalSync.ResetEvent();
+	m_state = m_lastState = READ_HALT_REQ;
+}
+
+
+readPktThread::~readPktThread() {
+	#if TRACE_THREAD || TRACE_DESTRUCT
+	double sTime = infcCoreTime();
+	#endif
+	//TerminateAndWait();
+	#if TRACE_THREAD || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f readPktThread destructed, elapsed=%.1f\n",
+		infcCoreTime(), infcCoreTime() - sTime);
+	#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		readPktThread::Run
+//
+//	DESCRIPTION:
+///
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+int readPktThread::Run(void *context)
+{
+	cnErrCode theErr;
+	nodeaddr respAddr;
+	packetbuf readBuf;
+	respTrackInfo *pFillInfo;
+	respNodeList *pNodeList;
+	double eTime = 0;	// Execution time
+	double rxTime;
+
+	// Initialize our netStateInfo pointer to allow interactions with
+	// the network.
+	pNCS = static_cast<netStateInfo *>(context);
+	mnNetInvRecords &theNet = SysInventory[pNCS->cNum];
+
+	#define RD_TIME_TRC 0
+	#if RD_TIME_TRC
+	double lTime, // Last time running start
+		iTime; // Time since last run
+	#endif
+	#if TRACE_CMD_PROFILE
+	double pTime = infcCoreTime();
+	#endif
+	infcErrInfo errInfo;				// Error reporting buffer
+	BOOL waitOK = false;
+	BOOL doTheRead, ctsEvent;
+
+	#if TRACE_RD_THRD||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f readPktThread(%d): id=" THREAD_RADIX " starting\n",
+		infcCoreTime(), pNCS->cNum, UIthreadID());
+	#endif
+
+	// Initializing
+	m_InternalSync.SetEvent();			// Insure we drop through
+	m_state = READ_HALT_REQ;
+
+	while (!((m_pTermFlag != NULL) && *m_pTermFlag) && m_state != READ_SHUTDOWN) {
+		//_RPT2(_CRT_WARN, "%.1f <1{%d}\n", infcCoreTime(), pNCS->nRespOutstanding);
+		#if TRACE_RD_THRD
+		if (m_state == READ_HALTED) {
+			_RPT2(_CRT_WARN, "%.1f readThread(%d) halted and waiting for restart\n",
+				infcCoreTime(), pNCS->cNum);
+		}
+		#endif
+		// Read Thread Operation Gate: if not-signalled, wait for a
+		// someone to restart us
+		waitOK = m_InternalSync.WaitFor(INFINITE);
+		if (!waitOK) {
+			_RPT1(_CRT_ERROR, "readThread(%d): InternalSync failed\n", pNCS->cNum);
+		}
+		#if RD_TIME_TRC
+		iTime = infcCoreTime() - lTime;
+		lTime = infcCoreTime();
+		#endif
+		// Run the proper state
+		//_RPT2(_CRT_WARN, "%.1f pre-Rlock>, state=%d\n", infcCoreTime(), m_state);
+		// Protect read thread state from start/stops until settled out
+		ReadLock.Lock();
+		//_RPT2(_CRT_WARN, "%.1f Rlocked, state=%d\n", infcCoreTime(), m_state);
+
+		switch (m_state) {
+		case READ_RUNNING:
+			// Allow state changes until end of cycle
+			//_RPT1(_CRT_WARN, "%.1f pre-Runlock>\n", infcCoreTime());
+			ReadLock.Unlock();
+			//_RPT1(_CRT_WARN, "%.1f Runlock>\n", infcCoreTime());
+
+			// Time to drop out and "poll"
+			#define RD_THREAD_PREMPTIVE_WAIT 100
+
+			if (theNet.PortIsOpen()) {
+				// Wait for the interrupt to occur or the timeout
+				waitOK = pNCS->ReadCommEvent.WaitFor(RD_THREAD_PREMPTIVE_WAIT);
+			}
+			else {
+				// The port is not open any more, so halt ourselves
+				ReadLock.Lock();
+				NextState(READ_HALT_REQ);
+				ReadLock.Unlock();
+				break;
+			}
+
+			CSerialExErrReportInfo errReport;
+			pNCS->pSerialPort->ErrorReportGet(&errReport);
+
+			ctsEvent = pNCS->ctsCount != errReport.CTScnt
+				&& m_state == READ_RUNNING
+				&& (theNet.OpenState != FLASHING);
+
+			if (ctsEvent && !((m_pTermFlag != NULL) && *m_pTermFlag)) {
+				// Issue node stops if CTS gets de-asserted
+				theNet.GroupShutdownRequest = true;
+				pNCS->GroupShutdownEvent.SetEvent();
+				pNCS->ctsCount = errReport.CTScnt;
+			}
+
+			//DEBUG
+			//_RPT1(_CRT_WARN, "%.1f *\n", infcCoreTime());
+			// Read should be OK if comm event signalled, we there is a packet,
+			// the read thread is running and we are not in serial mode.
+			doTheRead = waitOK
+				&& pNCS->pSerialPort->IsPacketAvailable()
+				&& m_state == READ_RUNNING
+				&& (theNet.OpenState != FLASHING);
+
+
+			if (doTheRead && !((m_pTermFlag != NULL) && *m_pTermFlag)) {
+				// Yes, read it now
+				readBuf.Byte.BufferSize = 0;					// Null in case of failure
+				eTime = infcCoreTime();					// Make sure time is reset
+				theErr = infcGetResponse(pNCS->cNum, &readBuf);
+				rxTime = infcCoreTime();
+				eTime = rxTime - eTime;
+
+				// Lock other command starts and housekeepers out here
+				ENTER_LOCK("readThreadProc");
+				// How did the read go?
+				if (theErr == MN_OK) {
+					#if TRACE_SEND_RESP
+					if (readBuf.Fld.Src == MN_SRC_HOST) {
+						netErrGeneric *pGenErr = (netErrGeneric *)&readBuf.Byte.Buffer[2];
+						//_RPT3(_CRT_WARN, "readThread    %.1f (%d) %d: <- ",
+						//								infcCoreTime(),	pNCS->cNum,
+						//								pNCS->nRespOutstanding);
+						DUMP_PKT(pNCS->cNum, "readThread    ", &readBuf, true);
+						//for (respAddr=0; respAddr<readBuf.Byte.BufferSize; respAddr++) {
+						//	_RPT1(_CRT_WARN, "%02x ", 0xFF & readBuf.Byte.Buffer[respAddr]);
+						//}
+						if (readBuf.Fld.PktType == MN_PKT_TYPE_ERROR) {
+							switch (pGenErr->Fld.ErrCls) {
+							case ND_ERRCLS_NET:
+								_RPT1(_CRT_WARN, " (net err %d)\n", pGenErr->Fld.ErrCode);
+								break;
+							case ND_ERRCLS_CMD:
+								_RPT1(_CRT_WARN, " (cmd err %d)\n", pGenErr->Fld.ErrCode);
+								break;
+							default:
+								_RPT2(_CRT_WARN, " (err cls %d, code=%d)\n", pGenErr->Fld.ErrCls,
+									pGenErr->Fld.ErrCode);
+								break;
+							}
+						}
+						else {
+							_RPT0(_CRT_WARN, "\n");
+						}
+					}
+					#endif
+					// Get address of the responder
+					if (readBuf.Byte.BufferSize == 0) {
+						theErr = MN_ERR_NULL_RETURN;
+						// Log the outcome
+						theNet.logReceive(&readBuf, theErr, NULL, rxTime);
+						// Release cmd lock on database
+						EXIT_LOCK("readThreadProc (nil buffer)");
+					}
+					else {
+						// Extract address once to "automatic"
+						respAddr = readBuf.Fld.Addr;
+						// Set nodeList to appropriate response database
+						if (MN_PKT_IS_HIGH_PRIO(readBuf.Fld.PktType)) {
+							// This is a control packet
+							pNodeList = &pNCS->controlNodeState;
+						}
+						else {
+							// This is a regular packet
+							pNodeList = &pNCS->respNodeState[respAddr];
+						}
+						// Update statistic
+						pNodeList->respCnt++;
+						// Get the head of our database item
+						pFillInfo = pNodeList->head;
+						// Source from the host?
+						if (readBuf.Fld.Src == MN_SRC_HOST) {
+							// This response originated from the host.
+
+							// Did we find the expected response record in command DB?
+							//  and not a network error
+							netErrGeneric *pErrPkt = (netErrGeneric *)&readBuf.Byte.Buffer[RESP_LOC];
+							bool isNetReject = ((unsigned)readBuf.Fld.PktType == MN_PKT_TYPE_ERROR)
+								&& (pErrPkt->Fld.ErrCls == ND_ERRCLS_NET);
+							if (isNetReject) {
+								EXIT_LOCK("readThreadProc (isNetReject)");
+								//In this case, the host noticed a net error while reading in
+								// a packet; increment the host diagStats to signal to those who
+								// might care
+
+								infcErrInfo errInfo;
+								nodeulong fakeAddr;
+								// This will always appear @ 1+End
+								fakeAddr = MN_API_MAX_NODES;
+
+								// Setup core error messages
+								errInfo.cNum = pNCS->cNum;
+								errInfo.node = fakeAddr;
+								// Let others know of the troubles
+								// .. this maybe overridden on a case by case basis.
+								errInfo.errCode = MN_ERR_NET_ERRS_DETECT;
+								infcCopyPktToPkt18(&errInfo.response, &readBuf);
+
+								mnNetDiagStats *pLog = &theNet.diagStats[fakeAddr];
+
+								#if defined(_DEBUG)&&0
+								if (!theNet.Initializing) {
+									_RPT2(_CRT_WARN, "Host net reject: cNum=%d, pkterr=%d\n",
+										pNCS->cNum, pErrPkt->Fld.ErrCode);
+								}
+								#endif
+
+								//Set the type of net error that was detected
+								if (pNCS->OurNetConnector == MN_SRC_APP_NET) {
+									switch (pErrPkt->Fld.ErrCode) {
+									case ND_ERRNET_FRAG:
+										pLog->AppNetFragPktCtr++;
+										break;
+									case ND_ERRNET_CHKSUM:
+										pLog->AppNetBadChksumCtr++;
+										break;
+									case ND_ERRNET_STRAY:
+										pLog->AppNetStrayCtr++;
+										break;
+									case ND_ERRNET_PORT_OVERRUN:
+										pLog->AppNetOverrunCtr++;
+										errInfo.errCode = MN_ERR_HOST_APP_OVERRUN;
+										// Show lead up issue
+										infcTraceDumpNext(errInfo.cNum);
+										break;
+									default:
+										_RPT1(_CRT_WARN, "Unknown host app net reject (%d)\n",
+											pErrPkt->Fld.ErrCode);
+									}
+								}
+								else {
+									switch (pErrPkt->Fld.ErrCode) {
+									case ND_ERRNET_FRAG:
+										pLog->DiagNetFragPktCtr = 1;
+										break;
+									case ND_ERRNET_CHKSUM:
+										pLog->DiagNetBadChksumCtr = 1;
+										break;
+									case ND_ERRNET_STRAY:
+										pLog->DiagNetStrayCtr = 1;
+										break;
+									case ND_ERRNET_PORT_OVERRUN:
+										pLog->DiagNetOverrunCtr = 1;
+										errInfo.errCode = MN_ERR_HOST_DIAG_OVERRUN;
+										// Show lead up issue
+										infcTraceDumpNext(errInfo.cNum);
+										break;
+									default:
+										_RPT1(_CRT_WARN, "Unknown host diag net reject (%d)\n",
+											pErrPkt->Fld.ErrCode);
+									}
+								}
+
+								theNet.diagsAvailable[fakeAddr] = TRUE;
+								#if TRACE_NET_ERR
+								_RPT2(_CRT_WARN, "%.1f readThread(%d) host detected err: \n", 
+									infcCoreTime(), pNCS->cNum);
+								//DUMP_PKT(cNum, (char *)"...", &readBuf);
+								_RPT2(_CRT_WARN, "Net Diag Counters:\tApp Net\t\t\t\t"
+									"Diag Net reporting node %d, net %d\n",
+									fakeAddr, pNCS->cNum);
+								_RPT0(_CRT_WARN, "\tfrags\tchks\tstray\tover\t\t"
+									"frags\tchks\tstray\tover\n");
+								_RPT4(_CRT_WARN, "%8d%8d%8d%8d",
+									pLog->AppNetFragPktCtr, pLog->AppNetBadChksumCtr,
+									pLog->AppNetStrayCtr, pLog->AppNetOverrunCtr);
+								_RPT4(_CRT_WARN, "\t%8d%8d%8d%8d\n",
+									pLog->DiagNetFragPktCtr, pLog->DiagNetBadChksumCtr,
+									pLog->DiagNetStrayCtr, pLog->DiagNetOverrunCtr);
+								#endif
+								infcFireErrCallback(&errInfo);
+							}
+							// Expecting response?
+							else if (pFillInfo != NULL) {
+								// Yes, get and remove from the DB
+								#if TRACE_LOW_PRINT&&TRACE_SEND_RESP
+								if (MN_PKT_IS_HIGH_PRIO(readBuf.Fld.PktType)) {
+									if (pFillInfo->nSentAtAddr == pNodeList->respCnt)
+										_RPT2(_CRT_WARN, "R%d<%d>", respAddr,
+											pNodeList->respCnt);
+									else
+										_RPT3(_CRT_WARN, "R%d<%d>->(%d)??",
+											respAddr,
+											pFillInfo->nSentAtAddr,
+											pNodeList->respCnt);
+								}
+								else {
+									if (pFillInfo->nSentAtAddr == pNodeList->respCnt)
+										_RPT2(_CRT_WARN, "R%d(%d)",
+											respAddr, pNodeList->respCnt);
+									else
+										_RPT3(_CRT_WARN, "R%d(%d)->(%d)??",
+											respAddr, pFillInfo->nSentAtAddr,
+											pNodeList->respCnt);
+								}
+								#endif
+								// Say we got something and copy to user buffer
+								pFillInfo->bufOK = TRUE;
+								if (pFillInfo->buf != NULL) {
+									*(pFillInfo->buf) = readBuf;
+									//_RPT1(_CRT_WARN, "readThread => buf 0x%x\n", pFillInfo->buf);
+								}
+								// Record time it took to read the response
+								pFillInfo->stats.rxTime = eTime;
+								pFillInfo->stats.pResp = pFillInfo->buf;
+								// Record receive time - send time + queue delay + overhead
+								pFillInfo->stats.pacedTime = infcCoreTime() - pFillInfo->funcStartAt;
+								// Record receive time - send time and packet received
+								pFillInfo->stats.execTime
+									= theNet.logReceive(&readBuf, theErr, pFillInfo, rxTime);
+								// Signal performance outcomes
+								if (userCmdCompleteFunc != NULL && theNet.TraceActive) {
+									(*userCmdCompleteFunc)(pNCS->cNum, &pFillInfo->stats);
+								}
+								// We are done using this response, return it back to free pool
+								pNCS->removeHeadDBitem(pNodeList);
+								// Log the outcome
+								EXIT_LOCK("readThreadProc (norm expect)");
+								#if TRACE_HIGH_LEVEL&0
+								_RPT2(_CRT_WARN, "cmd completed net %d in %.2f ms\n", pNCS->cNum, pFillInfo->stats.execTime);
+								#endif
+
+							} // IF (MN_SRC_HOST: expected response)
+							else { // (!rejected and unexpected)
+								   // MN_SRC_HOST: We are here because there is no record of a response expected.
+								   // Save in case this is serious
+								if (!pNCS->SelfDestruct) {
+									errInfo.node = respAddr;
+									infcCopyPktToPkt18(&errInfo.response, &readBuf);
+									switch (readBuf.Fld.PktType) {
+									case MN_PKT_TYPE_ERROR:
+										theErr = coreGenErrCode(pNCS->cNum, &readBuf, (nodeaddr)errInfo.node);
+										theNet.logReceive(&readBuf, theErr, NULL, rxTime);
+										// Release cmd lock on database
+										EXIT_LOCK("readThreadProc (unsol)");
+										// Create dump file to show context
+										_RPT2(_CRT_WARN, "readThread(%d) MN_PKT_TYPE_ERROR detected by node %d\n",
+											pNCS->cNum, readBuf.Fld.Addr);
+										// (TODO 11/18/2009 DS took out for experiment) infcTraceDumpNext(pNCS->cNum);
+										break;
+									default:
+										// Issue an error at this point
+										theErr = MN_ERR_UNSOLICITED;
+										if (respAddr >= theNet.InventoryNow.NumOfNodes)
+											theErr = MN_ERR_ADDR_RANGE;
+										else
+											theErr = MN_ERR_UNSOLICITED;
+										// Log the outcome
+										theNet.logReceive(&readBuf, theErr, NULL, rxTime);
+										// Release cmd lock on database
+										EXIT_LOCK("readThreadProc (unsol)");
+										// Tick the debug log with this information
+										_RPT2(_CRT_WARN, "readThread(%d): unsolicited packet response: node=%d\n",
+											pNCS->cNum, respAddr);
+										DUMP_PKT(pNCS->cNum, "...", &readBuf, true);
+										break;
+									}
+								}
+								else {
+									EXIT_LOCK("readThreadProc (unexpected)");
+								}
+							}
+						}  // src==MN_SRC_HOST
+						else {  // src==MN_SRC_NODE
+								// Packet claims it is from node and therefore not expected at
+								// the host. These packets are typically: error reports,
+								// attention notifications or data acquisition information.
+
+								// Log the reception
+							theNet.logReceive(&readBuf, theErr, NULL, rxTime);
+							// Prevent deadlock on any callbacks we no longer interact with cmd database
+							EXIT_LOCK("readThread: src=MN_SRC_NODE");
+							// Process the buffer and signal information
+							processNodeInitiatedPkt(pNCS->cNum, respAddr, pNCS, readBuf);
+						} // src=MN_SRC_MODE
+					} // if (bufferSize==0)
+				}
+				else { // theErr != MN_OK (infcGetResponse failed)
+					if (theNet.OpenState == FLASHING) {
+						EXIT_LOCK("readThread: inserial");
+						// Halt ourselves
+						ReadLock.Lock();
+						NextState(READ_HALT_REQ);
+						ReadLock.Unlock();
+						break;
+					}
+					else {
+						// Shutting down
+						if (((m_pTermFlag != NULL) && *m_pTermFlag)) {
+							EXIT_LOCK("readThread(read failure, shutting down)");
+							goto exit_thread;
+						}
+						// Read failed, create a "null" receive record in the trace
+						_RPT3(_CRT_WARN, "%.1f readThread(%d): read failed code=0x%x\n",
+							infcCoreTime(), pNCS->cNum, theErr);
+						EXIT_LOCK("readThread(read failure)");
+					}
+				} // (2) infcGetResponse
+			} // (1) if (doRead && !*m_pTermFlag)
+			break;
+		case READ_HALT_REQ:
+			#if TRACE_RD_THRD
+			_RPT2(_CRT_WARN, "%.1f readThread(%d), halt requested\n", infcCoreTime(), pNCS->cNum);
+			#endif
+			// Reset all acknowledgments
+			m_InternalSyncAck.ResetEvent();
+			NextState(READ_HALTED);
+			// Fall into halted state and let halt at InternalSync
+			// no break OK (special line for Code Analyzer to suppress warning)
+		case READ_HALTED:
+			#if TRACE_RD_THRD
+			_RPT2(_CRT_WARN, "%.1f readThread(%d), halted\n", infcCoreTime(), pNCS->cNum);
+			#endif
+			// Release function waiting for this stage of halt
+			m_InternalSyncAck.SetEvent();
+			// We park before the switch until woken up in potentially new state
+			m_InternalSync.ResetEvent();
+			// Allow read state changes
+			ReadLock.Unlock();
+			break;
+		case READ_SHUTDOWN_REQ:
+			#if TRACE_RD_THRD
+			_RPT2(_CRT_WARN, "%.1f readThread(%d), shutdown requested\n", infcCoreTime(), pNCS->cNum);
+			#endif
+			m_InternalSyncAck.ResetEvent();
+			NextState(READ_SHUTDOWN);
+			// Allow read state changes
+			ReadLock.Unlock();
+			break;
+		case READ_SHUTDOWN:
+			// Can't really get here as this is loop exit condition
+			#if TRACE_RD_THRD
+			_RPT1(_CRT_WARN, "readThread(%d), exit shutdown\n", pNCS->cNum);
+			#endif
+			// Honor the exit request
+			m_InternalSyncAck.SetEvent();
+			#if TRACE_RD_THRD||(TRACE_HIGH_LEVEL&&TRACE_THREAD)
+			_RPT3(_CRT_WARN, "%.1f readThread(%d), ID=" THREAD_RADIX
+				" exit via shutdown request!\n",
+				infcCoreTime(), pNCS->cNum, UIthreadID());
+			#endif
+			m_InternalSyncAck.SetEvent();
+			// Allow read state changes
+			ReadLock.Unlock();
+			return(300 + pNCS->cNum);
+		default:
+			_RPT2(_CRT_ERROR, "readThread(%d): Unknown state %d\n", pNCS->cNum,
+				m_state);
+			NextState(READ_SHUTDOWN);
+			m_InternalSyncAck.SetEvent();
+			// Allow read state changes
+			ReadLock.Unlock();
+			return(399);
+		};
+		// Yield while waiting for the response. This allows waiters
+		// to restart before processing another response.
+		infcSleep(0);
+	} // while (m_state != READ_SHUTDOWN)
+	m_InternalSyncAck.SetEvent();
+	ReadLock.Lock();
+	NextState(READ_SHUTDOWN);
+	ReadLock.Unlock();
+exit_thread:
+	#if TRACE_RD_THRD|TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f readPktThread(%d), ID=" THREAD_RADIX
+		" exit via loop termination!\n",
+		infcCoreTime(), pNCS->cNum, UIthreadID());
+	#endif
+	return(200 + pNCS->cNum);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		readPktThread::NextState
+//
+//	DESCRIPTION:
+///		Change the operational state of the read thread.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void readPktThread::NextState(readThreadStates nextState)
+{
+	#define TRC_NEXT TRACE_RD_THRD & 0
+	#if TRC_NEXT
+	static double sTime = 0, eTime = 0;
+	#endif
+
+	// Remember last state for diagnositic purposes
+	if (nextState != m_state)
+		m_lastState = m_state;
+
+	//_RPT1(_CRT_WARN, "NextReadState: %d\n", nextState);
+	switch (nextState) {
+	case READ_RUNNING:
+		// Insure ack event is reset on re-start
+		m_InternalSync.ResetEvent();
+		#if TRC_NEXT
+		_RPT1(_CRT_WARN, "NextReadState %d running\n", cNum);
+		sTime = infcCoreTime();
+		#endif
+		break;
+	case READ_HALTED:
+		#if TRC_NEXT
+		eTime = infcCoreTime();
+		_RPT2(_CRT_WARN, "NextReadState %d read thread ran for %.2f ms\n",
+			cNum, eTime - sTime);
+		#endif
+		break;
+	case READ_HALT_REQ:
+		// Reset the acknowledgment
+		m_InternalSync.ResetEvent();
+		break;
+	default:
+		// We don't care
+		break;
+	}
+	m_state = nextState;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		readPktThread::ForceStop
+//
+//	DESCRIPTION:
+///
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void readPktThread::ForceStop()
+{
+	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+	_RPT0(_CRT_WARN, "ReadThreadHalt Forced (no thread)...waiting on event");
+	#endif
+	// Wait for creation and park @ HALTED
+	m_InternalSync.SetEvent();
+	m_InternalSyncAck.WaitFor(INFINITE);
+	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+	_RPT0(_CRT_WARN, "ReadThreadHalt OK (no thread)..Halted\n");
+	#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		readPktThread::Stop
+//
+//	DESCRIPTION:
+///		Stop and park the read thread in an idle mode. This function returns
+///		when the read thread is parked, beware of deadlock!
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void readPktThread::Stop()
+{
+	StartStopLock.Lock();
+	// If not created, we are halted by definition. State will be setup
+	// after the thread reaches the halted state as denoted by the
+	// setting of the internal event object.
+	if (!pNCS) {
+		ForceStop();
+		StartStopLock.Unlock();
+		return;
+	}
+
+	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+	if (m_state != READ_HALTED)
+		_RPT2(_CRT_WARN, "%.1f ReadThreadHalt %d requested...",
+			infcCoreTime(), pNCS->cNum);
+	#endif
+
+	// Lock down the read state
+	ReadLock.Lock();
+
+	switch (m_state) {
+	case READ_SHUTDOWN_REQ:
+	case READ_SHUTDOWN:
+		#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+		_RPT0(_CRT_WARN, "shutting down\n");
+		#endif
+		// We are essentially halted, leave state alone
+		ReadLock.Unlock();
+		break;
+	case READ_HALTED:
+		#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+		//_RPT0(_CRT_WARN, "ReadThreadHalt: already halted\n");
+		#endif
+		pNCS->ReadCommEvent.ResetEvent();
+		// Already halted, do nothing.
+		ReadLock.Unlock();
+		break;
+	case READ_HALT_REQ:
+		// Waiting for halt already, keep waiting
+		#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+		_RPT0(_CRT_WARN, "waiting to park\n");
+		#endif
+		// Prevent new external commands
+		pNCS->CmdGate.ResetEvent();
+		// Force read thread to restart
+		pNCS->ReadCommEvent.SetEvent();
+		ReadLock.Unlock();
+		// Wait for it to park
+		m_InternalSyncAck.WaitFor(INFINITE);
+		#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+		_RPT1(_CRT_WARN, "%.1f ReadThreadHalt: parked\n",
+			infcCoreTime());
+		#endif
+		break;
+	case READ_RUNNING:
+		// We are still running, should we stop now?
+		//if (m_state == READ_RUNNING) {
+		// Next state is halt request
+		NextState(READ_HALT_REQ);
+		// Insure thread still running
+		m_InternalSync.SetEvent();
+		// Pretend data arrived
+		pNCS->ReadCommEvent.SetEvent();
+		// Allow thread to react
+		ReadLock.Unlock();
+		// Wait for it to stop
+		#ifdef _DEBUG
+		{
+			BOOL waitOK = m_InternalSyncAck.WaitFor(15000);
+			if (!waitOK) {
+				_RPT1(_CRT_WARN, "%.1f ReadThreadHalt wait failed\n",
+					infcCoreTime());
+			}
+		}
+		#else
+		m_InternalSyncAck.WaitFor(15000);
+		#endif
+		//}
+		//else {
+		//	// The new information take precendence
+		//	ReadLock.Unlock();
+		//	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+		//		_RPT1(_CRT_WARN, "%.1f ReadThreadHalt halt skipped\n",
+		//					infcCoreTime());
+		//	#endif
+		//	// Allow new external commands
+		//	pNCS->CmdGate.SetEvent();
+		//}
+		break;
+	default:
+		// Oops, pretend we are halted
+		NextState(READ_HALTED);
+		break;
+	}
+	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+	_RPT2(_CRT_WARN, "%.1f ReadThreadHalt(%d) halted\n",
+		infcCoreTime(), pNCS->cNum);
+	#endif
+	StartStopLock.Unlock();
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		readPktThread::Start
+//
+//	DESCRIPTION:
+///		(Re)Start the read thread to accept packets.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void readPktThread::Start()
+{
+	// Prevent access to internal structures
+	StartStopLock.Lock();
+	ReadLock.Lock();
+	// If no serial port, we don't need to start or we are running now
+	if (!pNCS || m_state == READ_RUNNING
+		|| !pNCS->pSerialPort || m_state == READ_SHUTDOWN) {
+		#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+		_RPT2(_CRT_WARN, "%.1f readThreadStart %d request ignored...\n",
+			infcCoreTime(), pNCS ? pNCS->cNum : 99);
+		#endif
+		ReadLock.Unlock();
+		StartStopLock.Unlock();
+		return;
+	}
+
+	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+	_RPT2(_CRT_WARN, "%.1f readThreadStart %d requested...\n",
+		infcCoreTime(), pNCS->cNum);
+	#endif
+
+	//SD 8/16/2017: Removed to prevent packets from being cleared if they come in during Start()
+	//pNCS->ReadCommEvent.ResetEvent();	
+
+	// Set state to running
+	NextState(READ_RUNNING);
+
+	// Make sure the thread restarts
+	switch (m_state) {
+	case READ_SHUTDOWN_REQ:
+	case READ_SHUTDOWN:
+		// Shutting down, don't allow start
+		ReadLock.Unlock();
+		break;
+	case READ_UNKNOWN:
+		// Should not get here, but assume same as halted
+		m_InternalSyncAck.ResetEvent();
+		NextState(READ_HALTED);
+		// Allow thread to run
+		m_InternalSync.SetEvent();
+		// Sync threads
+		m_InternalSync.WaitFor(INFINITE);
+		// Fall into the HALT request logic to wait for
+		// halt and then start thread
+		// no break OK (special line for Code Analyzer to suppress warning)
+	case READ_HALT_REQ:
+		#if TRACE_RD_THRD
+		_RPT2(_CRT_WARN, "%.1f readThreadStart(%d) from halt requested\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		// Allow read thread to run
+		ReadLock.Unlock();
+		// Wait until halted
+		m_InternalSyncAck.WaitFor(INFINITE);
+		ReadLock.Lock();
+		// Fall into the halted state, as that is where we are now
+		// to restart the thread
+		// no break OK (special line for Code Analyzer to suppress warning)
+	case READ_HALTED:
+		// Switch to the running state
+		NextState(READ_RUNNING);
+		// Allow thread to restart from wait prior to switch statement
+		m_InternalSync.SetEvent();
+		#if TRACE_RD_THRD || TRACE_HALT
+		_RPT2(_CRT_WARN, "%.1f readThreadStart(%d) restarting\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		ReadLock.Unlock();
+		break;
+	case READ_RUNNING:
+		#if TRACE_RD_THRD & 0
+		_RPT2(_CRT_WARN, "%.1f readThreadStart(%d) from running\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		ReadLock.Unlock();
+		// Allow read thread to run again
+		m_InternalSync.SetEvent();
+		break;
+	default:
+		#if TRACE_RD_THRD
+		_RPT2(_CRT_WARN, "%.1f readThreadStart(%d) (unlock#2b)\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		ReadLock.Unlock();
+		_RPT2(_CRT_ASSERT, "readThreadStart(%d) unknown read state handling %d\n",
+			pNCS->cNum, m_state);
+		break;
+	}
+	//////  READ CRITICAL SECTION RELEASED PAST HERE ////////
+	infcSleep(0);					// Release scheduling quanta
+	#if TRACE_HIGH_LEVEL & TRACE_START_STOP || TRACE_HALT
+	_RPT2(_CRT_WARN, "%.1f readThreadStart %d finished\n",
+		infcCoreTime(), pNCS->cNum);
+	#endif
+
+	StartStopLock.Unlock();
+}
+/// \endcond																  *
+//*****************************************************************************
+
+///	\cond INTERNAL_DOC
+//*****************************************************************************
+//	NAME																	  *
+//		infcHaltAutoNetDiscovery/Proc
+//
+//	DESCRIPTION:
+//		Kill the offline tickler and wait for exit.
+//
+//	SYNOPSIS:
+void MN_DECL infcHaltAutoNetDiscovery(netaddr cNum)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Insure our net is still there
+	if (!pNCS)
+		return;
+
+	if (pNCS->pAutoDiscover) {
+		_RPT2(_CRT_WARN, "%.1f infcHaltAutoNetDiscovery(%d): stopping\n",
+			infcCoreTime(), cNum);
+		pNCS->pAutoDiscover->Halt();
+		_RPT2(_CRT_WARN, "%.1f infcHaltAutoNetDiscovery(%d): stopped\n",
+			infcCoreTime(), cNum);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		attemptAutoDiscover
+//
+//	DESCRIPTION:
+//		This will attempt to start the auto-discovery thread if this feature
+//		is enabled and create dump file.
+//
+//	SYNOPSIS:
+
+void attemptAutoDiscover(infcErrInfo *pErrInfo) {
+	netaddr cNum = pErrInfo->cNum;
+	//	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (InfcDiagnosticsOn
+		&& SysInventory[cNum].AutoDiscoveryEnable
+		&& IsNetBreakErr(pErrInfo->errCode)) {
+		autoDiscoverStart(pErrInfo);
+	}
+}
+
+void attemptAutoDiscover(netaddr cNum, cnErrCode theErr) {
+	infcErrInfo errInfo;
+	errInfo.cNum = cNum;
+	errInfo.errCode = theErr;
+	errInfo.node = -1;
+	attemptAutoDiscover(&errInfo);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		autoDiscoverStart
+//
+//	DESCRIPTION:
+//		Start a thread that will attempt to detect attached nodes and restore
+//		the basic network connectivity. It will use the passed in error as
+//		basis for how to poll for active nodes.
+//
+//	SYNOPSIS:
+void autoDiscoverStart(netaddr cNum, cnErrCode theErr) {
+	infcErrInfo errInfo;
+	errInfo.cNum = cNum;
+	errInfo.errCode = theErr;
+	errInfo.node = -1;
+	autoDiscoverStart(&errInfo);
+}
+
+void autoDiscoverStart(infcErrInfo *pErrInfo)
+{
+	packetbuf zero;
+
+	netaddr cNum = pErrInfo->cNum;
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return;
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	netStateInfo *pNCS = theNet.pNCS;
+	// Don't bother to start auto-discovery if port in not open. The
+	// situation will not get better!
+
+	#if TRACE_TICKLER
+	_RPT2(_CRT_WARN, "%.1f autoDiscoverStart(%d): initiating\n",
+		infcCoreTime(), cNum);
+	#endif
+
+	if (!(theNet.AutoDiscoveryEnable || !InfcDiagnosticsOn)
+		|| !pNCS->pSerialPort->IsOpen()) {
+		_RPT2(_CRT_WARN, "%.1f autoDiscoverStart(%d): blocked from running\n",
+			infcCoreTime(), cNum);
+		return;
+	}
+
+	// Don't start during initializing or they don't want to run this
+	if (theNet.Initializing || InitializingGlobal) {
+		//	if (theNet.Initializing) {
+		_RPT3(_CRT_WARN, "%.1f autoDiscoverStart(%d) ignored: initializing, global=%d\n",
+			infcCoreTime(), cNum, InitializingGlobal);
+		return;
+	}
+	// Is there a auto-discover thread running now or we are shutting down?
+	if ((pNCS->pAutoDiscover && pNCS->pAutoDiscover->IsRunning())
+		|| pNCS->SelfDestruct) {
+		// Yes, let it keep running
+		_RPT2(_CRT_WARN, "%.1f autoDiscoverStart(%d): running or already shutdown\n",
+			infcCoreTime(), cNum);
+		return;
+	}
+	// No, prevent commands from running
+	pNCS->CmdGate.ResetEvent();
+
+	// Record this as the first reason we went offline
+	if (SysInventory[cNum].OpenState == OPENED_ONLINE) {
+		if (theNet.OfflineRootErr == MN_OK) {
+			theNet.OfflineRootErr = pErrInfo->errCode;
+			theNet.OfflineErrNode = pErrInfo->node;
+		}
+	}
+	// Mark that we are recovering
+	SysInventory[cNum].OpenStateNext(OPENED_SEARCHING);
+	// Get this started
+	pNCS->pAutoDiscover->Start(pErrInfo->errCode);
+	#if TRACE_HIGH_LEVEL||TRACE_TICKLER
+	_RPT2(_CRT_WARN, "%.1f autoDiscoverStart(%d)...\n",
+		infcCoreTime(), cNum);
+	#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcStartAutoNetDiscovery
+//
+//	DESCRIPTION:
+//		Start a thread that will attempt to detect attached nodes and restore
+//		the basic network connectivity. It will use the passed in error as
+//		basis for how to poll for active nodes. This used by the higher level
+//		initialization functions to start auto-discovery during startup
+//		time.
+//
+//	SYNOPSIS:
+void MN_DECL infcStartAutoNetDiscovery(
+	netaddr cNum,
+	cnErrCode initialError) {
+
+
+	infcErrInfo dummyErr;
+	dummyErr.cNum = cNum;
+	dummyErr.node = MULTI_ADDR(cNum, 0);
+	dummyErr.errCode = initialError;
+	if (initialError != MN_OK) {
+		autoDiscoverStart(&dummyErr);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		autoDiscoverThread construction/destruction
+//
+//	DESCRIPTION:
+///		Construct an offline tickler thread. This thread will periodically
+///		poll the serial port for the presence of nodes and bring the network
+///		back online. If the network was previously online, a test is made
+///		to locate "crashed" nodes.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+autoDiscoverThread::autoDiscoverThread()
+{
+	#if TRACE_THREAD || TRACE_DESTRUCT
+	_RPT1(_CRT_WARN, "%.1f autoDiscoverThread constructed\n",
+		infcCoreTime());
+	#endif
+	#if (defined(_WIN32)||defined(_WIN64))
+	// 4/29/11 DS Leads to issues with Win 7 UseWithCOM();
+	SetDLLterm(true);
+	#endif
+	m_goneOnline = false;
+	m_parked = true;
+	m_exitDiscovery = false;
+	pNCS = NULL;
+	m_faultingErr = MN_OK;
+}
+
+autoDiscoverThread::~autoDiscoverThread() {
+	#if TRACE_THREAD || TRACE_DESTRUCT
+	double sTime = infcCoreTime();
+	_RPT2(_CRT_WARN, "%.1f autoDiscoverThread destructing, id=" THREAD_RADIX "\n",
+		infcCoreTime(), UIthreadID());
+	#endif
+	// Kill our thread
+	TerminateAndWait();
+	#if TRACE_THREAD || TRACE_DESTRUCT
+	_RPT2(_CRT_WARN, "%.1f autoDiscoverThread destructed, elapsed=%.1f\n",
+		infcCoreTime(), infcCoreTime() - sTime);
+	#endif
+}
+
+void *autoDiscoverThread::Terminate() {
+	void *rVal;
+	// Force exit of discovery loop
+	m_exitDiscovery = true;
+	m_ThreadParkedEvent.SetEvent();
+	// Wait for it to park
+	//WaitUntilParked();
+	//WaitForTerm();
+	// Get things started
+	rVal = CThread::Terminate();
+	// Cause termination now, the error code is ignored due to termination
+	// flag priority.
+	#if TRACE_TICKLER && TRACE_LOW_PRINT
+	_RPT1(_CRT_WARN, "%.1f autoDiscoverThread::Terminate\n",
+		infcCoreTime());
+	#endif
+	return(rVal);
+}
+
+void autoDiscoverThread::TerminateAndWait() {
+	#if TRACE_TICKLER && TRACE_LOW_PRINT
+	_RPT1(_CRT_WARN, "%.1f autoDiscoverThread::TerminateAndWait\n",
+		infcCoreTime());
+	#endif
+	// Get loops to terminate and thread function to exit
+	Terminate();
+	// Wait for function to return
+	CThread::WaitForTerm();
+	//_RPT1(_CRT_WARN,"%.1f autoDiscoverThread::TerminateAndWait (terminated)\n",
+	//				infcCoreTime());
+}
+
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		autoDiscoverThread::WaitingForNet
+//
+//	DESCRIPTION:
+///		This function returns TRUE if we are still waiting for the network
+///		to come online.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+bool autoDiscoverThread::WaitingForNet() {
+	// no net context
+	if (pNCS == NULL)
+		return true;
+
+	bool retVal = (!m_goneOnline							// Still offline
+		&& !((m_pTermFlag != NULL) && *m_pTermFlag)		// Not terminating thread
+		&& !m_exitDiscovery								// Not exiting	
+														// We park if network closes or we enter serial port mode
+		// Not in "serial port" mode
+		&& SysInventory[pNCS->cNum].OpenState != FLASHING);
+	#if TRACE_TICKLER
+	_RPT3(_CRT_WARN, "%.1f autoDiscoverStart(%d): WaitingForNet=%d\n",
+		infcCoreTime(), pNCS->cNum, retVal);
+	#endif
+	return retVal;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		autoDiscoverThread::Run
+//
+//	DESCRIPTION:
+///		This is the thread control function. It does the polling and test
+///		sequencing.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+int autoDiscoverThread::Run(void *context)
+{
+	// Initialize our netStateInfo pointer to allow interactions with
+	// the network.
+	ULONG exitCode = 666;
+	pNCS = static_cast<netStateInfo *>(context);
+	if (!pNCS)
+		return(exitCode);
+	netaddr cNum = pNCS->cNum;
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	#if TRACE_TICKLER||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d): starting, id=" THREAD_RADIX "\n",
+		infcCoreTime(), cNum, UIthreadID());
+	#endif
+	cnErrCode theErr = MN_OK;
+	nodebool inventoryChanged = false;
+	nodebool hasConnectivity;
+	nodebool engagedCmdGate = false;
+	nodebool forcedOffline = false;
+
+	//DBG_LOG("Auto-discover starting\n");
+	// This loop runs until our owner terminates us. It parks at the
+	// m_ThreadParked Event until signalled. If thread termination is not
+	// in store, we will assume something bad happened, take our network
+	// offline, create a dump file to log the reason and then attempt
+	// to reconnect to our network by running a series of diagnostic
+	// processes. If the newly contacted network appears different the
+	// the network that went away the NODE_CHANGING_NETWORK_CONFIG event
+	// will we signalled and the system will re-enumerate.
+	while ((m_pTermFlag == NULL) || (!(*m_pTermFlag)))
+	{
+		#if TRACE_TICKLER
+		_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d): parking, id=" THREAD_RADIX "\n",
+			infcCoreTime(), cNum, UIthreadID());
+		#endif
+		// Signal we are parked now atomically
+		m_critSect.Lock();
+		m_parked = true;
+		m_ThreadParkedEvent.ResetEvent();
+		// Release autoDiscoverThread::Halt if this isn't initial start
+		m_InternalSyncAck.SetEvent();
+		// Allow commands again and release any waiters for our completion.
+		pNCS->CmdGate.SetEvent();
+		engagedCmdGate = false;
+		m_critSect.Unlock();
+		// Wait for supervision to restart us....
+		m_ThreadParkedEvent.WaitFor();
+
+		// If we have been asked to exit, do it now
+		if (m_pTermFlag && *m_pTermFlag) {
+			break;
+		}
+		// Someone started us, atomically change our state
+		m_critSect.Lock();
+		// Signal we are not parked now
+		m_parked = false;
+		// Reset our loop gater to prevent restart
+		m_ThreadParkedEvent.SetEvent();
+		m_InternalSyncAck.ResetEvent();
+		engagedCmdGate = true;
+		// Prevent RunCommand from running
+		pNCS->CmdGate.ResetEvent();
+		//m_critSect.Unlock();
+		exitCode = 600 + cNum;
+		// Reset diag counter
+		unsigned cnt = 0;
+		// Assume nothing changed yet
+		forcedOffline = m_goneOnline = inventoryChanged = false;
+		#if TRACE_TICKLER
+		_RPT4(_CRT_WARN, "%.1f autoDiscoverThread(%d): woke up, "
+			"exiting=%d, id=" THREAD_RADIX "\n",
+			infcCoreTime(), cNum,
+			m_exitDiscovery, UIthreadID());
+		#endif
+
+		// If we restarted due to errors, create our next dump file and
+		// send system offline.
+		if (!((m_pTermFlag != NULL) && *m_pTermFlag)
+			&& !m_exitDiscovery && SysInventory[cNum].PortIsOpen()) {
+			if (SysInventory[cNum].Initializing == 0) {
+				// Create a dump file if we can
+				infcTraceDumpNext(cNum);
+			}
+			// Send us offline and save inventory if we were previously online
+			forcedOffline = true;
+			infcSetInitializeMode(cNum, TRUE, m_faultingErr);
+			#if TRACE_TICKLER
+			_RPT2(_CRT_WARN, "%.1f autoDiscoverThread(%d): forcing offline\n",
+				infcCoreTime(), cNum);
+			#endif
+		}
+		m_critSect.Unlock();
+		// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+		// Start looking for the network to come online, then park
+		// waiting for another event unless we are shutting down.
+		// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+		// This inner loop exits when the network is restored
+	restartOnlineSearch:
+		while (((WaitingForNet() && !m_goneOnline) || forcedOffline) && !m_exitDiscovery) {
+			// Give things time to settle out.
+			infcSleep(AUTODISCOVER_WAIT_MS);
+			// Attempt to clear out issues
+			pNCS->pSerialPort->Flush();
+			cnt++;
+			#if TRACE_HIGH_LEVEL|TRACE_TICKLER
+			_RPT5(_CRT_WARN, "%.1f in autoDiscoverThread(%d) restarted #%d, forced=%d, "
+				"thread ID=" THREAD_RADIX "\n",
+				infcCoreTime(), cNum, cnt, forcedOffline, UIthreadID());
+			#endif
+			// Wants to stop after sleep?
+			if (!WaitingForNet()) {
+				#if TRACE_TICKLER
+				_RPT2(_CRT_WARN, "%.1f in autoDiscoverThread(%d) post-flush cancel\n",
+					infcCoreTime(), cNum);
+				#endif
+				break;
+			}
+			// Perform proper recovery strategy based on the initial error.
+			if (IsNetClassErr(theNet.OfflineRootErr)) {
+				#if TRACE_HIGH_LEVEL|TRACE_TICKLER
+				_RPT4(_CRT_WARN, "%.1f in autoDiscoverThread(%d) net class err 0x%x,"
+					"thread ID=" THREAD_RADIX "\n",
+					infcCoreTime(), cNum, theNet.OfflineRootErr, UIthreadID());
+				#endif
+				// Network based error was detected, such as time-out. Get
+				// original count of nodes.
+				nodeulong nNodes = SysInventory[cNum].InventoryNow.NumOfNodes;
+				#if TRACE_BREAK
+				_RPT3(_CRT_WARN, "%.1f in autoDiscoverThread(%d) calling infcResetNetRate,"
+					"thread ID=" THREAD_RADIX "\n",
+					infcCoreTime(), cNum, UIthreadID());
+				#endif
+				// Restore network back to default speed and test for
+				// connectivity using the serial "break" condition.
+				theErr = infcResetNetRate(cNum);
+				// Try and release port if port that is the issue
+				#if TRACE_HIGH_LEVEL|TRACE_TICKLER|TRACE_BREAK
+				_RPT4(_CRT_WARN, "%.1f in autoDiscoverThread(%d) infcResetNetRate err=0x%x,"
+					"thread ID=" THREAD_RADIX "\n",
+					infcCoreTime(), cNum, theErr, UIthreadID());
+				#endif
+				if (theErr != MN_OK) {
+					infcFireNetEvent(cNum, NODES_OFFLINE);
+					// Close the port an attempt to re-open again
+					#if TRACE_HIGH_LEVEL|TRACE_TICKLER|TRACE_BREAK
+					_RPT4(_CRT_WARN, "%.1f in autoDiscoverThread(%d) connectivity bad, err=0x%x,"
+						"thread ID=" THREAD_RADIX "\n",
+						infcCoreTime(), cNum, theErr, UIthreadID());
+					#endif
+					continue;
+				}
+				else {
+					m_goneOnline = true;
+					forcedOffline = false;
+				}
+				#ifdef __QNX__
+				// 2014/10/1 JS: Because the break detection is "faked" in QNX,
+				// just assume there is no connectivity before going into the
+				// broken ring diagnostics.
+				hasConnectivity = false; //(theErr == MN_OK);
+				#else
+				hasConnectivity = (theErr == MN_OK);
+				#endif
+
+				#if 0// TO_KILL
+				{
+					WCHAR foo[100];
+					if (hasConnectivity)
+						wsprintf(foo, _T("AD: brk OK\n"));
+					else
+						wsprintf(foo, _T("AD: brk failed 0x%x\n"), theErr);
+					OutputDebugStr(foo);
+				}
+				#endif
+				// If this fails, we do not have connectivity yet, or lopsided
+				// connectivity with other network.
+				if (WaitingForNet() && !hasConnectivity) {
+					// No connectivity, try and run the network break diagnostic
+					// via other channel on Meridian hardware nodes. We only do
+					// this for Meridian CON-MOD connected nodes.
+					if (SysInventory[cNum].PhysPortSpecifier.PortType == MERIDIAN_CONMOD) {
+						#if TRACE_HIGH_LEVEL||TRACE_TICKLER
+						_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d) "
+							"look for broken ring, err=0x%x\n",
+							infcCoreTime(), cNum, theErr);
+						#endif
+						theErr = infcBrokenRingDiag(cNum, hasConnectivity, nNodes);
+						if (theErr != MN_OK && theErr != MN_ERR_SEND_FAILED) {
+							// Signal back diagnostic results back to the app.
+							// This will usually be the bit encoded break location.
+							infcErrInfo errRep;
+							errRep.errCode = theErr;
+							errRep.cNum = cNum;
+							errRep.node = MN_API_UNKNOWN_ADDR;
+							errRep.response.bufferSize = 0;
+							// Force, call it if it exists
+							infcFireErrCallback(&errRep, true);
+							continue;
+						}
+					}
+				}
+				// Want's early quit?
+				if (!WaitingForNet())
+					break;
+				// We seem to be back online. Check for nodes that are talking but
+				// have spontaneously reset. This is determined by sending a simple
+				// get parameter command and if the node has reset we will receive
+				// our original command back instead of a response type packet.
+				theErr = infcProbeForOffline(cNum, &nNodes);
+				if (theErr != MN_OK) {
+					#if TRACE_HIGH_LEVEL||TRACE_TICKLER
+					_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d) probe for offline nodes err=%x\n",
+						infcCoreTime(), cNum, theErr);
+					#endif
+					infcErrInfo errRep;
+					errRep.errCode = theErr;
+					errRep.cNum = cNum;
+					errRep.node = MULTI_ADDR(cNum, theErr & MN_API_ADDR_MASK);
+					errRep.response.bufferSize = 0;
+					// Call it if it exists
+					infcFireErrCallback(&errRep);
+					continue;
+				}
+				// Restore original baud rate and check things out
+				theErr = infcChangeLinkSpeed(cNum, SysInventory[cNum].PhysPortSpecifier.PortRate);
+				if (theErr != MN_OK)
+					continue;
+				// Exit discovery loop and put network back online
+				exitCode = 800 + cNum;
+				m_goneOnline = true;
+			}
+			else {
+				// Unclassified error, assume this was a use error
+				#if TRACE_HIGH_LEVEL|TRACE_TICKLER
+				_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d) errors unhandled, "
+					"assumed use err type=0x%x\n",
+					infcCoreTime(), cNum, theNet.OfflineRootErr);
+				#endif
+				//if (!((m_pTermFlag != NULL) && *m_pTermFlag)) {
+				//	// Verify we still are OK
+				//	theErr = netEnumerate(cNum);
+				//	// Glitched out, try again
+				//	if (theErr != MN_OK)
+				//		continue;
+				//}
+				// Seems like the network came back, a non-error
+				exitCode = 700 + cNum;
+			} // unhandled auto-discover error
+		} // while (WaitingForNet() && !m_goneOnline)
+
+		  // We get here because was appear to be online
+		#if TRACE_TICKLER
+		_RPT5(_CRT_WARN, "%.1f autoDiscoverThread(%d) going online, initsema=%d"
+			", m_exitDiscovery=%d, m_goneOnline=%d\n",
+			infcCoreTime(), cNum,
+			SysInventory[cNum].Initializing, m_exitDiscovery, m_goneOnline);
+		#endif
+		// Reset the value cache in case the network went away due to power
+		// disruption.
+		coreInvalidateValCache(cNum);
+		// Go back online if we can
+		nodebool shouldTerm = Terminating() || m_exitDiscovery;
+		if (!shouldTerm) {
+			if (m_goneOnline) {
+				// Assume OK at start
+				inventoryChanged = false;
+				// Verify we still are OK and look for node count changes
+				theErr = netEnumerate(cNum);
+				// Glitched out, try again
+				if (theErr != MN_OK) {
+					_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d): "
+									 "failed netEnumerate, err=0x%x\n",
+									 infcCoreTime(), cNum, theErr);
+					m_goneOnline = false;
+					goto restartOnlineSearch;
+				}
+
+				// Check for net size change
+				if (SysInventory[cNum].InventoryLast.NumOfNodes
+					!= SysInventory[cNum].InventoryNow.NumOfNodes) {
+					#if TRACE_HIGH_LEVEL||TRACE_TICKLER
+					_RPT4(_CRT_WARN, "%.1f autoDiscoverThread(%d) node count change"
+						", now=%d, was=%d\n",
+						infcCoreTime(), cNum,
+						SysInventory[cNum].InventoryNow.NumOfNodes,
+						SysInventory[cNum].InventoryLast.NumOfNodes);
+					#endif
+					// Node count changed, rebuild internal net information to
+					// reflect changes.
+					inventoryChanged = true;
+					exitCode = 500 + cNum;
+				}
+				// Verify the nodes types are the same as last time
+				nodeaddr nAddr;
+				for (nAddr = 0; nAddr<SysInventory[cNum].InventoryNow.NumOfNodes; nAddr++) {
+					devID_t dID;
+					theErr = coreBaseGetParameterInt(cNum, nAddr,
+						MN_P_NODEID, &dID.devCode);
+					if (theErr == MN_OK
+						&&SysInventory[cNum].InventoryNow.LastIDs[nAddr].fld.devType != dID.fld.devType) {
+						_RPT2(_CRT_WARN, "%.1f autoDiscoverThread(%d): "
+							"Network nodes different!\n",
+							infcCoreTime(), cNum);
+						// Rebuild node info, node types changed
+						inventoryChanged = TRUE;
+						break;
+					}
+					// If we failed any test, keep offline, and try again
+					if (theErr != MN_OK)
+						break;
+				}
+				// If we failed any of the post-online checks, start from scratch
+				// to go online.
+				if (theErr != MN_OK)
+					continue;
+				// Signal change if we are still allowed to come online
+				if (inventoryChanged
+					&& !((m_pTermFlag != NULL) && *m_pTermFlag)) {
+					_RPT2(_CRT_WARN, "%.1f autoDiscoverThread(%d): "
+						"Network nodes different count!\n",
+						infcCoreTime(), cNum);
+					// NOTE: In VB this is NODES_CHANGING_NETWORK_CONFIG
+					infcFireNetEvent(cNum, NODES_CHANGING_NET_CONTROLLER);
+				}
+				// Wait for new kind of error to occur before we start again.
+				theNet.OfflineRootErr = MN_OK;
+				forcedOffline = false;
+				// Allow us to go online
+				theErr = infcSetInitializeMode(cNum, FALSE, theErr);
+				if (theErr != MN_OK) {
+					m_goneOnline = false;
+				}
+				// Allow next diagnostic to play
+				theNet.NetDiagLastResult = theErr;
+			}
+			// Release init mode if we have halt requested
+			else if (m_exitDiscovery) {
+				m_goneOnline = false;
+				// Relieve initializing count without events
+				if (SysInventory[cNum].Initializing>0) {
+					SysInventory[cNum].Initializing--;
+					if (InitializingGlobal) InitializingGlobal--;
+				}
+			}
+		}
+		#if TRACE_TICKLER
+		if (shouldTerm) {
+			_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d): terminating, id="
+				THREAD_RADIX "\n",
+				infcCoreTime(), cNum, UIthreadID());
+		}
+		else {
+			_RPT4(_CRT_WARN, "%.1f autoDiscoverThread(%d): going back online=%d, id="
+				THREAD_RADIX "\n",
+				infcCoreTime(), cNum, m_goneOnline, UIthreadID());
+			_RPT5(_CRT_WARN, "%.1f autoDiscoverThread(%d) initializing (non-term)=%d"
+				",forceOffline=%d,inventoryChanged=%d \n",
+				infcCoreTime(), cNum,
+				SysInventory[cNum].Initializing, forcedOffline,
+				inventoryChanged);
+		}
+		#endif
+	} // while waiting shutdown
+	  // Relieve our initialization state
+	if (forcedOffline)
+		infcSetInitializeMode(cNum, FALSE, m_faultingErr);
+
+	#if TRACE_TICKLER||TRACE_DESTRUCT
+	_RPT5(_CRT_WARN, "%.1f autoDiscoverThread(%d) thread ID=" THREAD_RADIX ","
+		" exiting code=%d, cnErr=%x\n",
+		infcCoreTime(), cNum, UIthreadID(), exitCode, theErr);
+	_RPT3(_CRT_WARN, "%.1f autoDiscoverThread(%d) exiting, initializing=%d\n",
+		infcCoreTime(), cNum,
+		SysInventory[cNum].Initializing);
+	#endif
+	// Make exit appear same as "parked"
+	m_critSect.Lock();
+	m_parked = true;
+	m_InternalSyncAck.SetEvent();
+	// Insure we don't leave gate closed if we closed it
+	if (engagedCmdGate)
+		pNCS->CmdGate.SetEvent();
+	
+	pNCS->CmdGate.WaitFor();
+	pNCS = NULL;
+
+	m_critSect.Unlock();
+	#if TRACE_HIGH_LEVEL
+	//DBG_LOG("Auto-discover exiting\n");
+	#endif
+	return(exitCode);
+
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		autoDiscoverThread::Halt
+//
+//	DESCRIPTION:
+/**
+Force the auto-discover thread to enter its halted and parked state.
+
+\param[in,out] xxx description
+\return description
+
+**/
+//	SYNOPSIS:
+void autoDiscoverThread::Halt()
+{
+	m_critSect.Lock();
+	#if TRACE_LOW_PRINT||TRACE_TICKLER
+	_RPT2(_CRT_WARN, "%.1f autoDiscoverThread::Halt: init cnt=%d\n",
+		infcCoreTime(), SysInventory[pNCS->cNum].Initializing);
+	#endif
+	// Already parked, ignore the request
+	if (m_parked) {
+		m_critSect.Unlock();
+		return;
+	}
+	if (!m_exitDiscovery) {
+		m_exitDiscovery = true;
+		// Wait for the thread to park
+		m_critSect.Unlock();
+		// Wait until it stops
+		m_InternalSyncAck.WaitFor();
+	}
+	else {
+		// Already exited
+		m_InternalSyncAck.SetEvent();
+		m_critSect.Unlock();
+	}
+	return;
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		autoDiscoverThread::Start
+//
+//	DESCRIPTION:
+/**
+Start the auto-discover process due to incoming reason.
+
+\param[in,out] xxx description
+\return description
+
+**/
+//	SYNOPSIS:
+void autoDiscoverThread::Start(cnErrCode theErr) {
+	// If serial port is closed, don't start discovery
+	// we can never go online.
+	if (!pNCS || !pNCS->pSerialPort || !pNCS->pSerialPort->IsOpen())
+		return;
+	m_critSect.Lock();
+	// Already parked?
+	if (m_parked) {
+		// Yes, restart thread
+		m_parked = false;
+		m_exitDiscovery = false;
+		m_faultingErr = theErr;
+		#if TRACE_LOW_PRINT||TRACE_TICKLER
+		_RPT2(_CRT_WARN, "%.1f autoDiscoverThread::Start from parked: init cnt=%d\n",
+			infcCoreTime(), SysInventory[pNCS->cNum].Initializing);
+		#endif
+		// Signal we can restart the thread
+		m_ThreadParkedEvent.SetEvent();
+		m_critSect.Unlock();
+	}
+	else {
+		// Not parked yet, wait for thread to park
+		// before restarting.
+		#if TRACE_LOW_PRINT||TRACE_TICKLER
+		_RPT2(_CRT_WARN, "%.1f autoDiscoverThread::Restarting: init cnt=%d\n",
+			infcCoreTime(), SysInventory[pNCS->cNum].Initializing);
+		#endif
+		m_critSect.Unlock();
+		m_InternalSyncAck.WaitFor();
+		// It will restart now from parked state.
+		Start(theErr);
+	}
+}
+/// \endcond																  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//*****************************************************************************
+//						   PUBLIC C STYLE INTERFACES
+//*****************************************************************************
+//*****************************************************************************
+
+/// \cond INFC_CLIB
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcSleep
+//
+//	DESCRIPTION:
+///		Efficiently waste time.
+///
+/// 	\param milliseconds Pauses the current thread for \a milliseconds.
+//
+//	SYNOPSIS:
+MN_EXPORT void MN_DECL infcSleep(
+	Uint32 milliseconds)
+{
+	CThread::Sleep(milliseconds);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcResetNetRate
+//
+//	DESCRIPTION:
+///		Restore the network back to it's power-on default rate.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcResetNetRate(
+	netaddr cNum)
+{
+	CSerial::SERAPI_ERR serErr;
+	cnErrCode theErr = MN_OK;
+	CSerialExErrReportInfo currentErrors;
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Port exists?
+	if (!pNCS || !pNCS->pSerialPort)
+		return(MN_ERR_PORT_PROBLEM);
+
+	// Prevent poller from running
+	if (pNCS->pPollerThread) pNCS->pPollerThread->Stop();
+
+	#if TRACE_BAUD
+	_RPT2(_CRT_WARN, "%.1f infcResetNetRate(%d) to 9600\n", infcCoreTime(), cNum);
+	#endif
+	// Setup/restore our port to initial settings
+	bool dtrState = pNCS->pSerialPort->GetDTR();
+	bool rtsState = pNCS->pSerialPort->GetRTS();
+
+	// Stop packet processing
+	pNCS->ReadThread.Stop();
+	// Start ignoring incoming data
+	pNCS->pSerialPort->AutoFlush(true);
+
+	serErr = pNCS->pSerialPort->Setup(MN_NET_BAUD_RATE,
+		CSerial::EData8,
+		CSerial::EParNone,
+		CSerial::EStop1,
+		dtrState ? CSerial::EDTRSet
+		: CSerial::EDTRClear,
+		rtsState ? CSerial::ERTSSet
+		: CSerial::ERTSClear);
+	// How did we do?
+	switch(serErr) {
+	case CSerial::API_ERROR_SUCCESS:
+		// All OK, continue
+		break;
+	case CSerial::API_ERROR_PORT_SETUP:
+		_RPT2(_CRT_WARN, "%.1f infcResetNetRate(%d) default net rate not supported!\n",
+			infcCoreTime(), cNum);
+		return(MN_ERR_BAUD_NOT_SUPPORTED);
+	default:
+		_RPT3(_CRT_WARN, "%.1f infcResetNetRate(%d) port unavailable! Err=0x%x\n",
+			infcCoreTime(), cNum, serErr);
+		return(MN_ERR_PORT_PROBLEM);
+	}
+
+	// Clear history of break and network errors
+	pNCS->pSerialPort->ErrorReportClear();
+
+	for (int i = 0; i<5; i++) {
+		// Send a break
+		#if TRACE_SERIAL || TRACE_BAUD
+		_RPT2(_CRT_WARN, "%.1f infcResetNetRate(%d) sending break\n",
+			infcCoreTime(), cNum);
+		#endif
+		serErr = pNCS->pSerialPort->Break(MN_BREAK_DURATION_MS);
+		if (serErr) {
+			#if 0
+			WCHAR foo[100];	   // TO_KILL
+			wsprintf(foo, _T("Break Failed 0x%x\n"), serErr);
+			OutputDebugStr(foo);
+			#endif
+			_RPT3(_CRT_WARN, "%.1f infcResetNetRate(%d) sending break failed, err=0x%x\n",
+				infcCoreTime(), cNum, serErr);
+			return(MN_ERR_PORT_PROBLEM);
+		}
+		// Wait for break to cycle around
+		infcSleep(Uint32(COMM_EVT_BRK_DLY_MS*1.2));
+		// Did we see one?
+		pNCS->pSerialPort->ErrorReportGet(&currentErrors);
+		// Basic connectivity if we saw break cycle around
+		if (currentErrors.BREAKcnt == 0) {
+			_RPT2(_CRT_WARN, "%.1f infcResetNetRate(%d) no BREAK was detected\n",
+				infcCoreTime(), cNum);
+			theErr = MN_ERR_NO_NET_CONNECTIVITY;
+			//03/23/2011 JS: Flush the port to get it moving again
+			infcFlush(cNum);
+			continue;
+		}
+		else {
+			theErr = MN_OK;
+		}
+
+		#if TRCE_LOW_PRINT|TRACE_BREAK
+		_RPT2(_CRT_WARN, "%.1f infcResetNetRate(%d) BREAK was detected\n",
+			infcCoreTime(), cNum);
+		#endif
+
+		break;
+	}
+	// Make sure we are in packet mode past here, we are running channel
+	// at "default" rate past here.
+	pNCS->pSerialPort->SetMode(SERIALMODE_MERIDIAN_7BIT_PACKET);
+
+	// Clear history of break and network errors
+	pNCS->pSerialPort->ErrorReportClear();
+
+	// Allow data to flow
+	pNCS->pSerialPort->AutoFlush(false);
+	#if TRACE_BAUD
+	_RPT3(_CRT_WARN, "%.1f infcResetNetRate(%d) exiting, err=%d\n",
+		infcCoreTime(), cNum, theErr);
+	#endif
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcChangeLinkSpeed
+//
+//	DESCRIPTION:
+/**
+	From the current port and net speed, send the command to change to 
+	the new speed. After successful speed change command on the link, the
+	port will be changed to match the new rate on the net.
+
+ 	\param cNum port index
+	\return Success code, MN_OK if executed OK
+
+ 	Detailed description.
+**/
+//	SYNOPSIS:
+cnErrCode MN_DECL infcChangeLinkSpeed(
+	netaddr cNum,
+	netRates newRate)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS)
+		return(MN_ERR_CLOSED);
+	// Port exists?
+	if (!pNCS->pSerialPort)
+		return(MN_ERR_PORT_PROBLEM);
+
+	// Bounds check request
+	if (newRate <= 0)
+		return(MN_ERR_BADARG);
+
+	#if TRACE_BAUD||TRACE_HIGH_LEVEL
+	_RPT3(_CRT_WARN, "%.1f infcChangeLinkSpeed(%d) rate=%d\n", infcCoreTime(), cNum, newRate);
+	#endif
+	// Create command to change to new rate.
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_EXTEND_HIGH, 0);
+	theCmd.Fld.PktLen = 2;
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CTL_EXT_BAUD_RATE;
+	theCmd.Byte.Buffer[CMD_LOC + 1] = newRate / MN_NET_RATE_DIVIDER;
+	// Make sure request works out perfectly
+	if ((theCmd.Byte.Buffer[CMD_LOC + 1] * MN_NET_RATE_DIVIDER) != newRate) {
+		theErr = MN_ERR_BADARG;
+		return(MN_ERR_BADARG);
+	}
+	theCmd.Byte.BufferSize = theCmd.Fld.PktLen + MN_API_PACKET_HDR_LEN;
+	theErr = infcRunCommand(cNum, &theCmd, &theResp);
+	if (theErr != MN_OK) {
+		// Attempt to restore default baud rate @ nodes, ignoring outcome.
+		infcResetNetRate(cNum);
+	}
+	else {
+		#if TRACE_BAUD
+		_RPT3(_CRT_WARN, "%.1f infcChangeLinkSpeed(%d) nodes now @ %d\n",
+			infcCoreTime(), cNum, newRate);
+		#endif
+		// Setup/restore our port to user's settings
+		bool dtrState = pNCS->pSerialPort->GetDTR();
+		bool rtsState = pNCS->pSerialPort->GetRTS();
+		// Setup port to new settings
+		CSerial::SERAPI_ERR winErr = pNCS->pSerialPort->Setup(newRate,
+										CSerial::EData8, CSerial::EParNone,
+										CSerial::EStop1,
+										dtrState ? CSerial::EDTRSet
+										: CSerial::EDTRClear,
+										rtsState ? CSerial::ERTSSet
+										: CSerial::ERTSClear);
+		// How did we do?
+		switch (winErr) {
+		case CSerial::API_ERROR_SUCCESS:
+			// This is OK
+			#if TRACE_BAUD
+			_RPT3(_CRT_WARN, "%.1f infcChangeLinkSpeed(%d) port now @ %d\n",
+				infcCoreTime(), cNum, newRate);
+			#endif
+			// Save the current rate
+			SysInventory[cNum].PhysPortSpecifier.PortRate = newRate;
+			// Clean up diagnostic cruft from speed change
+			netDiagsClr(cNum);
+			// We are all set
+			break;
+		case CSerial::API_ERROR_PORT_SETUP:
+			// Report we have issues with the request
+			theErr = MN_ERR_BAUD_NOT_SUPPORTED;
+			_RPT4(_CRT_WARN, "%.1f infcChangeLinkSpeed(%d) port doesn't support %d, "
+				"thread ID=" THREAD_RADIX_LONG "\n",
+				infcCoreTime(), cNum, newRate, infcThreadID());
+			break;
+		case CSerial::API_ERROR_PORT_UNAVAILABLE:
+		default:
+			// We failed recover due to some port problem: removed device,
+			// handle issue, etc.
+			theErr = MN_ERR_PORT_PROBLEM;
+			_RPT2(_CRT_WARN, "%.1f infcChangeLinkSpeed(%d), port unavailable\n",
+				infcCoreTime(), cNum);
+			break;
+		}
+	}
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcSetNetRate
+//
+//	DESCRIPTION:
+///		Set the network adapter rate to run at the new rate. The network
+///		rate command is transmitted and when returned back to the host
+///		the port will change to the new network communications rate.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL  infcSetNetRate(
+	netaddr cNum,
+	netRates newRate)
+{
+	cnErrCode theErr = MN_OK;
+
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS)
+		return(MN_ERR_CLOSED);
+	// Port exists?
+	if (!pNCS->pSerialPort)
+		return(MN_ERR_PORT_PROBLEM);
+
+	// Bounds check request
+	if (newRate <= 0)
+		return(MN_ERR_BADARG);
+	#if TRACE_BAUD||TRACE_HIGH_LEVEL
+	_RPT3(_CRT_WARN, "%.1f infcSetNetRate(%d) rate=%d\n", infcCoreTime(), cNum, newRate);
+	#endif
+	// Block recovery and error processing
+	SysInventory[cNum].Initializing++;
+
+	// Stop polling thread to prevent interference
+	infcBackgroundPollControl(cNum, false);
+
+	// Try it a few times if it doesn't work out (HACK)
+	for (int i = 0; i<3; i++) {
+		// Send break and restore baud back to default rate. This will kill
+		// any data acquisition that maybe running and about to interfere.
+		#if TRACE_BREAK
+		_RPT3(_CRT_WARN, "%.1f in infcSetNetRate(%d) calling infcResetNetRate,"
+			"thread ID=" THREAD_RADIX_LONG "\n",
+			infcCoreTime(), cNum, infcThreadID());
+		#endif
+		theErr = infcResetNetRate(cNum);
+		if (theErr != MN_OK)
+			continue;
+		// Run it and await its response
+		#if TRACE_BAUD
+		_RPT3(_CRT_WARN, "%.1f infcSetNetRate(%d) setting nodes to %d\n",
+			infcCoreTime(), cNum, newRate);
+		#endif
+		theErr = infcChangeLinkSpeed(cNum, newRate);
+		// Allow a few retries
+		if (theErr == MN_OK)
+			break;
+	}
+	// Signal error if this didn't work out
+	if (theErr != MN_OK) {
+		// Create errir
+		infcErrInfo errInfo;
+		errInfo.cNum = cNum;
+		errInfo.errCode = theErr;
+		errInfo.node = -1;			// HOST detected
+		infcFireErrCallback(&errInfo);
+	}
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Done and running at the new rate.
+	// - - - - - - - - - - - - - - - - - - - - - - - - - - 
+	// Unstack initialization/recovery and error processing
+	SysInventory[cNum].Initializing--;
+	// Restart the poller if we can and it was running at start.
+	if (SysInventory[cNum].Initializing == 0
+		&& SysInventory[cNum].OpenState == OPENED_ONLINE) {
+		// Turn on the polling, keeping existing error
+		cnErrCode pollErr
+			= infcBackgroundPollControl(cNum,
+				SysInventory[cNum].KeepAlivePollRestoreState);
+		theErr = (theErr == MN_OK) ? pollErr : theErr;
+	}
+	return(theErr);
+}
+//																			    *
+//*******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		infcRunCommand
+//
+//	DESCRIPTION:
+//		This function will send the buffer specified in <theCommand> and
+//		wait for the response and store it in <theResponse>. If no response
+//		is desired, a NULL pointer is passed to <theResponse> parameter. In
+//		this case, the function will always returns MN_OK.
+//
+//		Commands are run by:
+//			1) acquiring the command semaphore to limit the number of
+//			   simultaneous commands in the network
+//			2) the command lock semaphore is then acquired
+//			3) the command is sent
+//			4) the response database is created and updated with the desired
+//			   handling for this command
+//		    5) The command lock is released
+//			6) If no response is desired, this function returns MN_OK
+//			   else
+//			   We go to sleep waiting for the read thread to wake us up via
+//			   an APC being queued to this thread.
+//			7) If there is a valid response, this function returns MN_OK, else
+//			   it returns the appropriate code.
+//
+//	RETURNS:
+//		Standard return codes
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcRunCommand(
+	netaddr cNum,
+	packetbuf *theCommand,				// pointer to filled in command
+	packetbuf *theResponse)				// pointer to response area
+{
+	double funcStartAt = infcCoreTime();					// Time we started this function
+	cnErrCode theErr = MN_OK;
+	respNodeList *pRespArea;								// By node address & type data areas
+	respTrackInfo *pRespInfo;								// Thread / response info data
+	BOOL sleepOK;
+	BOOL dataOK, inRecovery;
+	mnCompletionInfo stats;									// Command completion statistics
+
+	register netStateInfo *pNCS;							// Quick access to net info
+
+															// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	// We must have defined buffers
+	if (!theResponse || !theCommand)
+		return MN_ERR_BADARG;
+
+	// Initialize fast pointer to our data
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	pNCS = theNet.pNCS;
+	// RAII Lock on pNCS until return
+	netStateInfo::cmdsIdleEvt idleChecker(*pNCS);
+
+	// Don't allow if the port is not open
+	if (!pNCS || !pNCS->pSerialPort || !pNCS->pSerialPort->IsOpen())
+		return(MN_ERR_CLOSED);
+
+	// Don't do in serial port mode
+	if (theNet.OpenState == FLASHING) {
+		return(MN_ERR_IN_SERIAL_PORT);
+	}
+
+	// Cannot run commands from the read thread
+	if (pNCS->isReadThread()) {
+		return(MN_ERR_CMD_IN_ATTN);
+	}
+
+
+	theCommand->Fld.StartOfPacket = 1;
+	theResponse->Byte.BufferSize = 0;
+	theResponse->Fld.PktLen = 0;
+	//#ifdef _DEBUG
+	//	theResponse->Byte.Buffer[0] = 0x00;
+	//	theResponse->Byte.Buffer[1] = 0x11;
+	//	theResponse->Byte.Buffer[10] = 0xaaU;
+	//	theResponse->Byte.Buffer[11] = 0xbbU;
+	//#endif
+
+	// Check for outstanding responses
+	if (pNCS->nRespOutstanding == 0 && inDebugging) {
+		if (SysPortCount > 1) {
+			// Check for outstanding responses on other ports
+		}
+		else {
+			// Release the debugging thread lock gate, allowing us to step 
+			// through code
+			debugThreadLockResponseGate.SetEvent();
+		}
+	}
+
+	// Check if the current thread should hit the gate
+	if (inDebugging) {
+		if (CThread::CurrentThreadID() != lockedThreadID) {
+			// Blocks new commands from being sent
+			debugGate.WaitFor(INFINITE);
+		}
+	}
+
+	// Are we in recovery thread?
+	inRecovery = pNCS->isRecoveryThread();
+
+	// If diagnostic is running we slowly cancel user's requests to
+	// prevent application spinout.
+	if (!inRecovery && !pNCS->CmdGate.WaitFor(FRAME_WRITE_TIMEOUT))
+		return MN_ERR_CANCELED;
+
+	// Block here if too many commands are attempted at once, the read
+	// thread will release each of these if the send is successful.
+	// If the transmission fails, we releave this semaphore.
+	sleepOK = pNCS->CmdPaceSemaphore.Lock(INFINITE);
+
+	// Too long to release, this should only occur if there is a deadlock
+	if (!sleepOK) {
+		//NOTE: Since the semaphore wait time is now infinite, we should never
+		// get in here!
+		infcErrInfo semaErr;
+		_RPT1(_CRT_WARN, "infcRunCommand(%d): pace semaphore release err, deadlocked?\n",
+			cNum);
+		semaErr.errCode = MN_ERR_SEND_LOCKED;
+		semaErr.cNum = cNum;
+		semaErr.node = -1;
+		infcCopyPktToPkt18(&semaErr.response, theCommand);
+		infcFireErrCallback(&semaErr);
+		// Log the problem
+		theNet.logSend(theCommand, MN_ERR_SEND_LOCKED, infcCoreTime());
+		// We are screwed, kill all pending work to flush
+		infcFlush(cNum);
+		return(MN_ERR_SEND_LOCKED);
+	}
+	// Attempt to send command while not initializing?
+	if (!inRecovery && SysInventory[cNum].OpenState != OPENED_ONLINE
+		&& !(SysInventory[cNum].Initializing)) {
+		// Log the send attempt and the error it caused
+		theNet.logSend(theCommand, MN_ERR_CMD_OFFLINE, infcCoreTime());
+		// Prevent leaking locks!
+		#ifdef _DEBUG
+		pNCS->CmdPaceSemaphore.Unlock(1, &pNCS->SemaCount);
+		#else
+		pNCS->CmdPaceSemaphore.Unlock();
+		#endif
+		return(MN_ERR_CMD_OFFLINE);
+	}
+
+	// Setup the response area for this command while sending/wait.
+	if (MN_PKT_IS_HIGH_PRIO(theCommand->Fld.PktType)) {
+		// Control packets are not node related, queue separately
+		pRespArea = &pNCS->controlNodeState;
+		#if TRACE_LOW_PRINT&&TRACE_SEND_RESP
+		_RPT2(_CRT_WARN, "\nS%d<%d>", theCommand->Fld.Addr, pRespArea->sendCnt + 1);
+		#endif
+	}
+	else {
+		// Regular packets queue at each node
+		pRespArea = &pNCS->respNodeState[theCommand->Fld.Addr];
+		#if TRACE_LOW_PRINT&&TRACE_SEND_RESP
+		_RPT2(_CRT_WARN, "\nS%d(%d)", theCommand->Fld.Addr, pRespArea->sendCnt + 1);
+		#endif
+	}
+	//
+	// Lock out the other threads until we have this sent out
+	// and the response database entries have been made.
+	// The rule for responses is that by node, responses are in order, but
+	// not nodes are allowed to return out of the transmit order.
+	// For example:
+	// - command #1 is issued to node 3
+	// - command #2 is issued to node 0 (NC)
+	// - command #3 is issued to node 3
+	//
+	// The responses could come back #2, #1, #3 or #1, #2, #3.  Responses
+	// from an individual node are always processed the order transmitted.
+	// If a node can finish ahead of another node in the ring, it may
+	// transmit its result ahead of the transmit order.
+	//
+	ENTER_LOCK("infcRunCommand (cmd init)");
+
+	// Assign a response tracking database element.
+	if (!pNCS->pTrkTail) {
+		EXIT_LOCK("infcRunCommand(going away)");
+		// Prevent leaking locks!
+		#ifdef _DEBUG
+		pNCS->CmdPaceSemaphore.Unlock(1, &pNCS->SemaCount);
+		#else
+		pNCS->CmdPaceSemaphore.Unlock();
+		#endif
+		return(MN_ERR_CMD_OFFLINE);
+	}
+	pRespInfo = *pNCS->pTrkTail;
+	*pNCS->pTrkTail-- = NULL;
+	//_RPT2(_CRT_WARN, "infcRunCommand: trk list %d @ 0x%x\n", pNCS->pTrkTail-pNCS->pTrkList, pRespInfo);
+	if (pNCS->pTrkTail < &pNCS->pTrkList[-1]) {
+		_RPT0(_CRT_ASSERT, "infcRunCommand: oops using illegal tracker\n");
+	}
+
+	// Initialize the response database tracking info
+	pRespInfo->stats.cmd = *theCommand;		// Save our command
+	pRespInfo->next = NULL;					// We are always a leaf
+	pRespInfo->buf = theResponse;			// Where to finally store resp
+	pRespInfo->bufOK = FALSE;				// Nothing here yet
+	pRespInfo->funcStartAt = funcStartAt;	// Record function start
+	pRespInfo->nSentAtAddr = ++pRespArea->sendCnt;
+
+	if (theErr == MN_OK) {
+		// Record time when command hits the net
+		pRespInfo->cmdStartAt = infcCoreTime();
+		++pNCS->nRespOutstanding;
+		theErr = infcSendCommand(cNum, theCommand);
+		if (theErr != MN_OK) {
+			--pNCS->nRespOutstanding;
+		}
+		pRespInfo->stats.sendTime = infcCoreTime() - pRespInfo->cmdStartAt;
+	}
+	// If we sent command, continue processing for the expected response.
+	if (theErr == MN_OK) {
+		// We expect one to return
+		pRespInfo->stats.ringDepth = pNCS->nRespOutstanding;
+
+		// Initialize database pointers if first time through here
+		if (pRespArea->head == NULL) {
+			pRespArea->head = pRespInfo;	// Head = first one
+			pRespArea->tail = NULL;		// Reset the tail
+		}
+		// Link previous item to this one if there was one
+		if (pRespArea->tail != NULL) {
+			pRespArea->tail->next = pRespInfo;
+		}
+		// Tail always points to latest sent item
+		pRespArea->tail = pRespInfo;		// DB tail ptr to the end
+											// Save our serial number
+		pRespInfo->sendSerNum = theNet.logSend(theCommand, theErr, pRespInfo->cmdStartAt);
+		// Make sure response wait event is unsignalled??
+		pRespInfo->evtRespWait.ResetEvent();
+
+		// Make sure the read thread starts running
+		pNCS->ReadThread.Start();
+
+		//_RPT1(_CRT_WARN, "ReadThreadState: %d\n", pNCS->readThreadState );
+		// Unlock previous lock now that the response database is updated
+		EXIT_LOCK("infcRunCommand (restart read)");
+		// This thread is waiting for the response, wait for event or timeout
+		#if TRACE_LOW_PRINT&&TRACE_SEND_RESP
+		_RPT0(_CRT_WARN, "W");
+		#endif
+		//_RPT1(_CRT_WARN, "%.1f start response wait\n", infcCoreTime());
+		BOOL waitOK = pRespInfo->evtRespWait.WaitFor(InfcRespTimeOut);
+		#if TRACE_LOW_PRINT&&TRACE_SEND_RESP
+		_RPT1(_CRT_WARN, ".<%d>", sleepOK);
+		#endif
+		if (!waitOK) {
+			// -------------------------------------------------- //
+			// We are restarted via time-out                      //
+			// -------------------------------------------------- //
+			theErr = MN_ERR_RESP_TIMEOUT;
+			//_RPT2(_CRT_WARN, "%.1f cmd timeout! hndl=0x%x\n",
+			//				 infcCoreTime(),pRespInfo->hRespWait);
+			DUMP_PKT(cNum, "**Timeout cmd ", &pRespInfo->stats.cmd);
+			ENTER_LOCK("infcRunCommand (timeout)");
+			// Add failure to the rx log file
+			if (SysInventory[cNum].TraceActive) {
+				packetbuf nullPkt;
+
+				// Create null packet buffer
+				nullPkt.Byte.BufferSize = 0;
+				nullPkt.Byte.Buffer[0] = nullPkt.Byte.Buffer[1] = 0;
+				// Assign a receive trace record
+				theNet.logReceive(&nullPkt, MN_ERR_RESP_TIMEOUT, pRespInfo, infcCoreTime());
+			}
+			if (SysInventory[cNum].OpenState == OPENED_ONLINE) {
+				// Send off the error callback, fill in the relevant
+				// error information
+				infcErrInfo errInfo;
+				errInfo.errCode = theErr;
+				errInfo.cNum = cNum;
+				infcCopyPktToPkt18(&errInfo.response, theCommand);
+				errInfo.node = theCommand->Fld.Addr;
+				// Notify the user
+				infcFireErrCallback(&errInfo);
+			}
+			// Remove this as an expected item
+			pNCS->removeThisDBitem(pRespInfo, pRespArea);
+			EXIT_LOCK("infcRunCommand (resp timeout)");
+		}
+		//else {
+		//	//_RPT1(_CRT_WARN, "infcRunCommand: response wait OK\n", sleepOK);
+		//}
+	}
+	else {
+		_RPT2(_CRT_WARN, "infcRunCommand: failed send 0x%0x @ %f\n", theErr, infcCoreTime());
+		// Return the tracking DB item
+		pNCS->pTrkTail++;
+		*pNCS->pTrkTail = pRespInfo;
+		// Release the command semaphore allowing one more (if even possible)
+		// - note we have the command lock when we get here, don't forget to
+		// release it.
+		#ifdef _DEBUG
+		dataOK = pNCS->CmdPaceSemaphore.Unlock(1, &pNCS->SemaCount);
+		#else
+		dataOK = pNCS->CmdPaceSemaphore.Unlock();
+		#endif
+		if (dataOK) {
+			// Make sure read thread keeps running
+			if (pNCS->nRespOutstanding > 0) {
+				if (--pNCS->nRespOutstanding > 0) {
+					pNCS->ReadThread.Start();
+				}
+			}
+		}
+		else {
+			infcErrInfo semaErr;
+			int semaErrCode = GetLastError();
+			_RPT1(_CRT_ERROR, "readThread: semaphore release err 0x%X\n",
+				semaErrCode);
+			semaErr.errCode = MN_ERR_SEND_UNLOCK;
+			semaErr.cNum = cNum;
+			semaErr.node = semaErrCode;
+			EXIT_LOCK("infcRunCommand: (sema rel err)");
+			infcFireErrCallback(&semaErr);
+			theErr = (cnErrCode)GetLastError();
+			_RPT1(_CRT_ERROR, "infcRunCommand: semaphore release err 0x%X\n",
+				theErr);
+			theNet.logSend(theCommand, MN_ERR_SEND_UNLOCK, infcCoreTime());
+			return(theErr);
+		}
+		// Release lock, started upon command attempt
+		EXIT_LOCK("infcRunCommand (send fail)");
+		// Command failed, make sure there is someone to clean up
+		// any remaining items.
+		pNCS->ReadThread.Start();
+		// Log transfer timeout to a special error
+		if (theErr == MN_ERR_TIMEOUT) {
+			theErr = MN_ERR_SEND_FAILED;
+		}
+		theNet.logSend(theCommand, theErr, infcCoreTime());
+		// Send off the callback if it exists
+		{
+			infcErrInfo errInfo;
+			// Fill in the relevant information
+			errInfo.errCode = theErr;
+			errInfo.cNum = cNum;
+			infcCopyPktToPkt18(&errInfo.response, theCommand);
+			errInfo.node = 0;
+			// Notify the user
+			infcFireErrCallback(&errInfo);
+		}
+	}
+	// Return the last error
+	return theErr;
+}
+//																			 *
+//******************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		infcOnline
+//
+//	DESCRIPTION:
+//		Returns TRUE if the port is open and ready to accept characters.
+//
+//	RETURNS:
+//		nodebool
+//
+//	SYNOPSIS:
+MN_EXPORT nodebool MN_DECL infcOnline(netaddr cNum)
+{
+	// In range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return(false);
+	return SysInventory[cNum].OpenState == OPENED_ONLINE;
+}
+/// \endcond																  *
+//****************************************************************************
+
+
+/// \cond INTERNAL_DOC
+//*****************************************************************************
+//	NAME																	  *
+//		infcStartController
+//
+//	DESCRIPTION:
+//		This function will open our NT device driver returning a handle to
+//		that device for future use. This handle should be passed to the
+//		NCstopController function when operations are complete or the
+//		application is terminating.
+//
+//		If a controller is currently open, this call will always close it
+//		down before re-opening.
+//
+//	RETURNS:
+//		MN_OK if device opened and port at the default rate.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcStartController(
+	netaddr cNum)					// cNum = the COM Port to be opened
+{
+	cnErrCode theErr = MN_OK;
+	netStateInfo *pNCS;
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	#if TRACE_START_STOP
+	_RPT2(_CRT_WARN, "%.1f infcStartController %d...", infcCoreTime(), cNum);
+	#endif
+	#ifdef _DEBUG
+	// Look for trouble every restart
+	infcHeapCheck("infcStartController: start");
+	#endif
+	// Hook to pointer based reference
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	pNCS = theNet.pNCS;
+
+	// Create logging on first open
+	if (!theNet.txTraces) theNet.txTraces = new txTraceBuf[SEND_DEPTH];
+	if (!theNet.rxTraces) theNet.rxTraces = new rxTraceBuf[RECV_DEPTH];
+
+	// Our port is active and/or exists?
+	if (pNCS) {
+		// Yes, kill us
+		theNet.TraceActive
+			= theNet.TraceActiveReq | InfcDumpOnExit;
+
+		pNCS->waitForIdle();
+
+		// Allow only one starter at a time
+		//pInitLock->Lock();
+		// Destroy the old environment
+		infcStopController(cNum);
+		// This is gone now
+		pNCS = NULL;
+	}
+	// We have no environment, make a new one now.
+	if (!pNCS) {
+		pNCS = SysInventory[cNum].pNCS = new netStateInfo(SysInventory[cNum].NumCmdsInRing, cNum);
+		#if TRACE_SIZES
+		_RPT2(_CRT_WARN, "infcStartController: netStateInfo size=%d(0x%x)\n",
+			sizeof(netStateInfo(SysInventory[cNum].NumCmdsInRing, cNum)),
+			sizeof(netStateInfo(SysInventory[cNum].NumCmdsInRing, cNum)));
+		#endif
+		// Did it work out?
+		if (!pNCS) {
+			return(MN_ERR_MEM_LOW);
+		}
+	}
+
+	/****** Open and Setup Serial Port  *******/
+	if (!pNCS->pSerialPort
+		#if (defined(_WIN32)||defined(_WIN64))
+		|| ((pNCS->pSerialPort)->OpenComPort(SysInventory[cNum].PhysPortSpecifier.PortNumber))
+		!= CSerial::API_ERROR_SUCCESS
+		#else
+		|| ((pNCS->pSerialPort)->OpenComPort(SysInventory[cNum].PhysPortSpecifier.PortName))
+		!= CSerial::API_ERROR_SUCCESS
+		#endif
+		) {
+		// No port is detected - notify application
+		infcFireNetEvent(cNum, NODES_NO_PORT);
+		// Unlock
+		//pInitLock->Unlock();
+		return(MN_ERR_PORT_PROBLEM);
+	}
+	// Say port is basically open
+	SysInventory[cNum].OpenStateNext(OPENED_SEARCHING);
+	// Setup our port, if all is OK
+	if (theErr == MN_OK) {
+		CSerial::SERAPI_ERR winErr;
+		// Setup basic port states / brakes on until proven otherwise
+		winErr = pNCS->pSerialPort->Setup(MN_NET_BAUD_RATE,
+			CSerial::EData8,
+			CSerial::EParNone,
+			CSerial::EStop1,
+			CSerial::EDTRClear,
+			CSerial::ERTSClear);
+		// Translate port error to a better error codes
+		switch (winErr) {
+		case CSerial::API_ERROR_SUCCESS:
+			// This is OK
+			break;
+		case CSerial::API_ERROR_PORT_SETUP:
+			return(MN_ERR_BAUD_NOT_SUPPORTED);
+		case CSerial::API_ERROR_PORT_UNAVAILABLE:
+		default:
+			return(MN_ERR_PORT_PROBLEM);
+		}
+		// Restore brake settings if restarting
+		theErr = infcBrakeSet(cNum, 0, SysInventory[cNum].brake0Saved, true);
+		if (theErr == MN_OK) 
+			theErr = infcBrakeSet(cNum, 1, SysInventory[cNum].brake1Saved, true);
+		if (theErr != MN_OK) 
+			return theErr;
+
+		// Prevent errors from reporting to user
+		SysInventory[cNum].Initializing++;
+
+		// Stop polling thread to prevent interference
+		infcBackgroundPollControl(cNum, false);
+
+		// Assume an NC for commands to run without MN_ERR_ADDR_RANGE error.
+		SysInventory[cNum].InventoryNow.NumOfNodes = 0;
+
+		// Connect our local pkt received event to the serial channel
+		pNCS->pSerialPort->RegisterUserPktCommEvent(&pNCS->ReadCommEvent);
+		if (SysInventory[cNum].OpenState != OPENED_ONLINE)
+			SysInventory[cNum].OpenStateNext(OPENED_SEARCHING);
+		SysInventory[cNum].Initializing--;
+
+		// Restart the poller if we can and it was running at start.
+		if (SysInventory[cNum].Initializing == 0) {
+			// Turn on the polling, keeping existing error
+			cnErrCode pollErr = infcBackgroundPollControl(cNum,
+				SysInventory[cNum].KeepAlivePollRestoreState);
+			theErr = (theErr == MN_OK) ? pollErr : theErr;
+		}
+
+	}
+	// If we get here, we are up and running
+	pNCS->ReadThread.Start();
+	// Setup the port for use on Meridian network at power-up baud rate
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+	#if TRACE_BREAK
+	_RPT3(_CRT_WARN, "%.1f in infcStartController(%d) calling infcResetNetRate,"
+		"thread ID=" THREAD_RADIX_LONG "\n",
+		infcCoreTime(), cNum, infcThreadID());
+	#endif
+	// Finalize with force net to initial rate and run connectivity test
+	theErr = infcResetNetRate(cNum);
+	//pInitLock->Unlock();							// Unlock
+	#ifdef _DEBUG
+	// Look for trouble created during init
+	infcHeapCheck("infcStartController: exiting");
+	#endif
+	#if TRACE_START_STOP
+	_RPT2(_CRT_WARN, "%.1f infcStartController %d done.\n", infcCoreTime(), cNum);
+	#endif
+	return theErr;
+
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcStopController
+//
+//	DESCRIPTION:
+//		Shutdown access to the previously started net controller
+//		device.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcStopController(
+	netaddr cNum)		// Index of controller desired
+
+{
+	netStateInfo *pNCS;
+	cnErrCode theErr = MN_OK;
+	#if TRACE_START_STOP
+	_RPT2(_CRT_WARN, "%.1f infcStopController %d...\n",
+		infcCoreTime(), cNum);
+	#endif
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	// Convert to pointer form
+	pNCS = SysInventory[cNum].pNCS;
+
+	// Already Offline, say OK
+	if (!pNCS)
+		return MN_OK;
+
+	// We are shutting down now	if currently open and running
+	if (pNCS->pSerialPort->IsOpen()) {
+		infcFireNetEvent(cNum, NODES_OFFLINE);
+		// Kill off any workers using the port
+		pNCS->pAutoDiscover->Terminate();
+		pNCS->pAutoDiscover->WaitForTerm();
+
+		pNCS->pPollerThread->Terminate();
+		pNCS->pPollerThread->WaitForTerm();
+
+		// Get current state, ignore errors that occurred
+		infcBrakeGet(cNum, 0, &SysInventory[cNum].brake0Saved, true);
+		infcBrakeGet(cNum, 1, &SysInventory[cNum].brake1Saved, true);
+		// Start ignoring incoming data
+		pNCS->pSerialPort->AutoFlush(true);
+		pNCS->pSerialPort->Flush();
+		pNCS->pSerialPort->Break(100);
+		SysInventory[cNum].OpenStateNext(CLOSED);
+		pNCS->ReadThread.Stop();
+		pNCS->pSerialPort->Close();
+		// Insure destruction can proceed
+		pNCS->CmdsIdle.SetEvent();
+	}
+	delete SysInventory[cNum].pNCS;
+	SysInventory[cNum].pNCS = NULL;
+
+	// Unhook ourselves from the system
+	SysInventory[cNum].clearNodes(true);
+	#if TRACE_START_STOP
+	_RPT3(_CRT_WARN, "%.1f infcStopController %d: stopped code=%x\n",
+		infcCoreTime(), cNum, theErr);
+	#endif
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*******************************************************************************
+//	NAME																	    *
+//		makeNopPacket
+//
+//	DESCRIPTION:
+//		Flush network received data and structures. It is assumed the data
+//		structures are locked out prior to calling this.
+//
+//	RETURNS:
+//		Number of characters flushed.
+//
+//	SYNOPSIS:
+void makeNopPacket(packetbuf *pBuf, bool isHighPrio) {
+	// Create a low level NOP to clear out any frags waiting
+	pBuf->Fld.Src = MN_SRC_HOST;
+	pBuf->Fld.PktType = isHighPrio ? MN_PKT_TYPE_EXTEND_HIGH
+		: MN_PKT_TYPE_EXTEND_LOW;
+	pBuf->Fld.Addr = 0;						// Assume first node
+	pBuf->Fld.PktLen = 1;
+	pBuf->Fld.Mode = pBuf->Fld.Zero1 = 0;	// Fill in unused with 0
+	pBuf->Byte.Buffer[2] = (isHighPrio ? (nodechar)MN_CTL_EXT_NOP
+		: (nodechar)MN_CTL_EXT_LOW_NOP);
+	pBuf->Byte.BufferSize = pBuf->Fld.PktLen + MN_API_PACKET_HDR_LEN;
+}
+//																			    *
+//*******************************************************************************
+
+//*******************************************************************************
+//	NAME																	    *
+//		infcFlushProc
+//
+//	DESCRIPTION:
+//		Flush network received data and structures. It is assumed the data
+//		structures are locked out prior to calling this.
+//
+//	RETURNS:
+//		Number of characters flushed.
+//
+//	SYNOPSIS:
+nodeulong infcFlushProc(netaddr cNum)
+{
+	nodeulong lostCount = 0;
+	nodeushort i;
+	respTrackInfo *nextWaiter, *head;
+	packetbuf theCmd;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	// Skip if device is not open
+	if (!pNCS->pSerialPort)
+		return(0);
+
+	#if TRACE_LOW_PRINT&&TRACE_FLUSH
+	_RPT1(_CRT_WARN, "%.1f infcFlushProc, starting...\n", infcCoreTime());
+	#endif
+	if (SysInventory[cNum].Initializing == 0) {
+		_RPT2(_CRT_WARN, "%.1f infcFlushProc(%d), online during flush...\n", infcCoreTime(), cNum);
+	}
+	// Prevent reading of these responses
+	pNCS->ReadThread.Stop();
+	// Ignore all data past here
+	pNCS->pSerialPort->AutoFlush(true);
+
+	// Create a low level NOP to clear out any frags waiting
+	makeNopPacket(&theCmd, false);
+	infcSendCommand(cNum, &theCmd);
+
+	// Create a high level NOP to clear out any frags waiting
+	makeNopPacket(&theCmd, true);
+	infcSendCommand(cNum, &theCmd);
+	// Let junk accumulate
+	infcSleep(50);
+	// flush all data out of the serial port
+	// Clean up threads waiting
+	for (i = 0; i<MN_API_MAX_NODES; i++) {
+		// Return all storage for threads waiting past head
+		head = pNCS->respNodeState[i].head;
+		while (head != NULL) {
+			nextWaiter = head->next;
+			pNCS->removeThisDBitem(head, &pNCS->respNodeState[i]);
+			head = nextWaiter;
+		}
+	}
+
+	// Clean up the control command buffers
+	head = pNCS->controlNodeState.head;
+	while (head != NULL) {
+		nextWaiter = head->next;
+		pNCS->removeThisDBitem(head, &pNCS->controlNodeState);
+		// Record the next head
+		head = nextWaiter;
+	}
+	// There are no responses left now
+	pNCS->nRespOutstanding = 0;	// This should have already been 0
+	infcSleep(0);					// Yield our quantum
+									// Get rid of any other detritus
+	if (pNCS->pSerialPort) {
+		(pNCS->pSerialPort)->Flush();
+		// Start getting data past here
+		pNCS->pSerialPort->AutoFlush(false);
+	}
+	// Restart the reader
+	pNCS->ReadThread.Start();
+	infcSleep(0);					// Yield our quantum
+	#if TRACE_LOW_PRINT&&TRACE_FLUSH
+	_RPT1(_CRT_WARN, "%.1f infcFlushProc, done...\n", infcCoreTime());
+	#endif
+	return(lostCount);
+}
+//																			    *
+//*******************************************************************************
+
+
+//*******************************************************************************
+//	NAME																	    *
+//		infcFlush
+//
+//	DESCRIPTION:
+//		Flush network received data while locking out structures.
+//
+//	RETURNS:
+//		Number of characters flushed.
+//
+//	SYNOPSIS:
+nodeulong MN_DECL infcFlush(
+	netaddr cNum)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	nodeulong lostCount;
+	// Lock out other activity
+	ENTER_LOCK("infcFlush");
+	// Flush NC data
+	lostCount = infcFlushProc(cNum);
+	EXIT_LOCK("infcFlush");
+	return(lostCount);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcGetResponse
+//
+//	DESCRIPTION:
+//		This function will retrieve the response for <theCmd> sent
+//		previously. The the current thread is suspended until the result
+//		is returned or on error due to lack of response. The results of this
+//		transfer are placed in the packetbuf pointed by <theResponse>.
+//
+//	RETURNS:
+//		#cnErrCode of send success
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetResponse(
+	netaddr cNum,
+	packetbuf *theResp)					// pointer to a command buffer area
+
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Interface gone?
+	if (!pNCS->pSerialPort)
+		return(MN_ERR_CLOSED);
+	// Wait and get a response
+	if (pNCS->pSerialPort->GetPkt(*theResp)) {
+		//_RPT2(_CRT_WARN, "%.1f infcGetResponse bufsize=%d\n",
+		//	infcCoreTime(), theResp->Byte.BufferSize);
+		pNCS->nPktsRcvd++;
+		return(MN_OK);
+	}
+	else
+		return(MN_ERR_RESP_TIMEOUT);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcSendCommand
+//
+//	DESCRIPTION:
+//		This function will send the command specified by the <theCommand>
+//		field to the current network controller.
+//
+//	RETURNS:
+//		#cnErrCode of send success
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcSendCommand(
+	netaddr cNum,
+	packetbuf *theCommand)			// pointer to a command buffer area
+
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Interface gone?
+	if (!pNCS->pSerialPort)
+		return(MN_ERR_CLOSED);
+
+	#if TRACE_SEND_RESP
+	theCommand->Fld.StartOfPacket = 1;
+	DUMP_PKT(cNum, "SendCommand   ", theCommand);
+	#endif
+
+	// Send atomically via the serial port
+	if (pNCS->pSerialPort->SendPkt(*theCommand)) {
+		pNCS->nPktsSent++;
+		return(MN_OK);
+	}
+
+	// Something went wrong!
+	return(MN_ERR_SEND_FAILED);
+}
+
+
+// Same as infcSendCommand, but log in send log, we are not expecting response.
+cnErrCode MN_DECL infcSendCommandLog(
+	nodeushort cNum,					// Port Index
+	packetbuf *theCommand)			    // Ptr to buffered command
+{
+	cnErrCode theErr;
+	double txStart = infcCoreTime();
+	theErr = infcSendCommand(cNum, theCommand);
+	// If all OK, log it
+	if (cNum < NET_CONTROLLER_MAX && SysInventory[cNum].pNCS)
+		SysInventory[cNum].logSend(theCommand, theErr, txStart);
+	return(theErr);
+}
+///																			   *
+//******************************************************************************
+
+
+
+
+/*****************************************************************************
+*	NAME
+*		infcSerialStats
+*
+*	DESCRIPTION:
+*		Get and reset the current character counts for the serial port.
+*
+*	RETURNS:
+*		TRUE if a character is can safely be sent
+*
+*	SYNOPSIS: 															    */
+MN_EXPORT cnErrCode MN_DECL infcSerialStats(
+	netaddr cNum,
+	nodeulong &rxCnt,
+	nodeulong &txCnt,
+	nodeulong &rxPktCnt,
+	nodeulong &txPktCnt)
+{
+	// Bounds check arguments
+	if (cNum > NET_CONTROLLER_MAX)
+		return MN_ERR_BADARG;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS)
+		return MN_ERR_FAIL;
+	if (!pNCS->pSerialPort)
+		return MN_ERR_FAIL;
+	rxCnt = pNCS->pSerialPort->ReceiveCount();
+	txCnt = pNCS->pSerialPort->TransmitCount();
+	rxPktCnt = pNCS->nPktsRcvd;
+	txPktCnt = pNCS->nPktsSent;
+	// Atomically reduce counts
+	pNCS->nPktsRcvd -= rxPktCnt;
+	pNCS->nPktsSent -= txPktCnt;
+	return MN_OK;
+}
+//																			 *
+//****************************************************************************
+
+
+
+
+//****************************************************************************
+//	NAME
+//		infcSetInitializeMode
+//
+//	DESCRIPTION:
+//		Adjust the initializing flag and fire the proper set of callbacks
+//		when we are completed with all the initializing items. This function
+//		is called in a "stacked" manner from all the initializing functions
+//		to allow low and high level initialization to produce a single set
+//		of "offline" and "online" events for each invokation of the
+//		initialization functions such as mnInitializeNet or tgInitialization.
+//		mnInitialization calls the low-level functions as a matter of its
+//		execution so scheduling of the events would be complicated if this
+//		function did not keep track of the "stack depth".
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcSetInitializeMode(
+	netaddr cNum,
+	nodebool initializing,
+	cnErrCode lastErr)
+{
+	enum NetworkChanges state = NODES_OFFLINE;
+	#define LCL_INIT_PR 0
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	//netStateInfo *pNCS = theNet.pNCS;
+	if (initializing) {
+		theNet.Initializing++;
+		if (theNet.Initializing == 1) {
+			// If first time, signal we are going offline
+			state = NODES_OFFLINE;
+			// Prevent polling
+			infcBackgroundPollControl(cNum, false);
+			infcFireNetEvent(cNum, NODES_OFFLINE);
+		}
+		#if (TRACE_CALLBACK&&TRACE_LOW_LEVEL) || LCL_INIT_PR
+		_RPT4(_CRT_WARN, "%.1f infcSetInitializeMode(%d): Initializing #%d, err=0x%x\n",
+			infcCoreTime(), cNum, theNet.Initializing, lastErr);
+		#endif
+	} // if (initializing)
+	else {
+		if (theNet.Initializing > 0) {
+			theNet.Initializing--;
+		}
+		else {
+			// 12/20/12 DS infcSetQueueLimit when online can cause this
+			//// Decrement when the init counter is zero - this shouldn't happen
+			//infcErrInfo theErrRec;
+			//theErrRec.cNum = cNum;
+			//theErrRec.node = MN_API_MAX_NODES;
+			//theErrRec.errCode = MN_ERR_RESET_FAILED;
+			//theErrRec.response.bufferSize = 0;
+			////infcFireErrCallback(&theErrRec);
+			//_RPT2(_CRT_WARN, "%.1f infcSetInitializeMode(%d): Init counter already zero\n",
+			//				infcCoreTime(), cNum);
+		}
+		// Last one out fires off the final net state event
+		if (theNet.Initializing == 0) {
+
+			//cnErrCode theErr = MN_OK;
+			#if (TRACE_CALLBACK&&TRACE_LOW_LEVEL) || LCL_INIT_PR
+			_RPT3(_CRT_WARN, "%.1f infcSetInitializeMode(%d): Initialization complete, err=0x%x\n",
+				infcCoreTime(), cNum, lastErr);
+			#endif
+			// Allow next diagnostic to play
+			theNet.NetDiagLastResult = MN_OK;
+			if (theNet.OpenState == OPENED_SEARCHING) {
+				// Save a copy of the inventory in case we go offline
+				theNet.InventoryLast = theNet.InventoryNow;
+			}
+			// Attempt to restore network speed when going back online
+			switch (lastErr) {
+			case MN_OK:
+			case MN_ERR_TEST_INCOMPLETE:
+				break;
+			default:
+				// Ignore other types
+				break;
+			}
+			// Always send some events based on our final operational
+			// state.
+			switch (lastErr) {
+			case MN_OK:
+				state = NODES_DRIVER_ONLINE;
+				break;
+			case MN_ERR_TEST_INCOMPLETE:
+				state = NODES_ONLINE_NO_TEST;
+				break;
+			case MN_ERR_PORT_PROBLEM:
+				state = NODES_NO_PORT;
+				break;
+			case MN_ERR_BAUD_NOT_SUPPORTED:
+				state = NODES_BAUD_UNSUPPORTED;
+				break;
+			default:
+				// Start looking for nodes if we could not
+				// get online at this time.
+				infcStartAutoNetDiscovery(cNum, lastErr);
+				state = NODES_OFFLINE;
+				break;
+			}
+			// Clear node error counts when going online, the
+			// initialization process leaves nodes with errors due
+			// to the break condition sent to set baud rates.
+			if (state == NODES_DRIVER_ONLINE) {
+				for (unsigned i = 0; i<theNet.InventoryNow.NumOfNodes; i++) {
+					mnNetErrStats myDiagResult;
+					cnErrCode theErr =
+						netGetErrStats(MULTI_ADDR(cNum, i), &myDiagResult);
+					// Rescind our ONLINE state!
+					if (theErr != MN_OK) {
+						_RPT3(_CRT_WARN, "%.1f infcSetInitializeMode(%d): failed to clear net stats, err=0x%x\n",
+							infcCoreTime(), cNum, theErr);
+						lastErr = theErr;
+						break;
+					}
+				}
+				// Rescind advance for port options if we have a non-advance node
+				if (theNet.PhysPortSpecifier.PortType == CPM_COMHUB 
+				&& (theNet.pNCS)->OurNetConnector == MN_SRC_APP_NET) {
+					// Make sure the brake addressing is OK
+					for (size_t i = 0; i < mnNetInvRecords::MAX_BRAKES; i++) {
+						nodeaddr theAddr = NODE_ADDR(theNet.autoBrake[i].relatedNode);
+						// If net smaller now, cancel old brakes
+						if (theAddr != MN_UNSET_ADDR
+							&& theAddr > theNet.InventoryNow.NumOfNodes) {
+							theNet.autoBrake[i].relatedNode = MN_UNSET_ADDR;
+						}
+						// If unset, make it match the node number
+						if (theNet.autoBrake[i].relatedNode == MN_UNSET_ADDR
+							&& i < theNet.InventoryNow.NumOfNodes) {
+							theNet.autoBrake[i].relatedNode = MULTI_ADDR(cNum, i);
+						}
+					}
+
+					// Restore the auto-brake state
+					theNet.setupBrakes();
+
+					// Restore group shutdowns
+					// Skip processing our attentions
+					theNet.attnInitializing++;
+					for (size_t i = 0; i < theNet.InventoryNow.mnCpScInfo.count; i++) {
+						multiaddr theAddr = theNet.InventoryNow.mnCpScInfo.node[i];
+						ShutdownInfo &sInfo = theNet.GroupShutdownInfo[NODE_ADDR(theAddr)];
+						infcShutdownInfoSet(theAddr, &sInfo);
+						// Restore the driver attention masks
+						netSetDrvrAttnMask(theAddr, &theNet.drvrAttnMask[NODE_ADDR(theAddr)]);
+					}
+					// Wait for attentions to propagate
+					infcSleep(50);
+					// Allow processing again
+					theNet.attnInitializing--;
+				}
+				// Restore the polling, keeping existing error
+				cnErrCode pollErr
+					= infcBackgroundPollControl(cNum,
+						theNet.KeepAlivePollRestoreState);
+				lastErr = (lastErr == MN_OK) ? pollErr : lastErr;
+			}
+			// Go online now so that stats clear can run from user's
+			// threads.
+			infcFireNetEvent(cNum, state);
+			} // if theNet.Initializing == 0 && InitializingGlobal == 0
+		else {
+			// Still not enough layers of initialization complete yet
+			#if (TRACE_CALLBACK&&TRACE_LOW_LEVEL) || LCL_INIT_PR
+			_RPT4(_CRT_WARN, "%.1f infcSetInitializeMode: heading online #%d offline=%d, err=0x%x\n",
+				infcCoreTime(), theNet.Initializing,
+				theNet.OpenState, lastErr);
+			#endif
+		} // theNet.Initializing != 0 || InitializingGlobal != 0
+		} // if !initializing
+	#if TRACE_LOW_LEVEL || LCL_INIT_PR
+	_RPT2(_CRT_WARN, "infcSetInitializeMode: count=%d, state=%d\n",
+		theNet.Initializing, theNet.OpenState);
+	#endif
+	return(lastErr);
+	}
+//																			 *
+//****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcGetInitializeMode
+//
+//	DESCRIPTION:
+//		Get the initializing flag.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcGetInitializeMode(
+	netaddr cNum,
+	nodebool *initializing)
+{
+	// Return TRUE if we are still initializing
+	*initializing = (SysInventory[cNum].Initializing > 0);
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcSetCmdQueueLimit
+//
+//	DESCRIPTION:
+//		Set the limit of simultaneous commands in the ring.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcSetCmdQueueLimit(
+	netaddr cNum,
+	nodeulong nCmds)
+{
+	cnErrCode theErr = MN_OK;
+	// Bounds check arguments
+	if (nCmds == 0 || nCmds > 14 || cNum > NET_CONTROLLER_MAX)
+		return(MN_ERR_BADARG);
+	// See if the network exists
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (pNCS) {
+		infcSetInitializeMode(cNum, TRUE, MN_OK);
+		// Stop using the network
+		theErr = infcStopController(cNum);
+		// Note: pNCS is invalid past here!
+		// Make the change in our static area
+		SysInventory[cNum].NumCmdsInRing = nCmds;
+		if (theErr == MN_OK) {
+			// Restart the controller to install new command limits if
+			// we were running before.
+			theErr = infcStartController(cNum);
+			if (theErr == MN_OK) {
+				theErr = netEnumerate(cNum);
+			}
+		}
+		infcSetInitializeMode(cNum, FALSE, theErr);
+	}
+	else {
+		// Make the change in our static area
+		SysInventory[cNum].NumCmdsInRing = nCmds;
+	}
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcSetTraceEnable
+//
+//	DESCRIPTION:
+//		Manipulate the capture of the trace information.
+//
+//	RETURNS:
+//		Nothing
+//
+//	SYNOPSIS:
+MN_EXPORT void MN_DECL infcSetTraceEnable(
+	netaddr cNum,
+	nodebool state)
+{
+	SysInventory[cNum].TraceActiveReq = SysInventory[cNum].TraceActive = state;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME
+//		infcUpdateInventory
+//
+//	DESCRIPTION:
+//		Update the last known inventory with this information.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode infcUpdateInventory(netaddr cNum,
+	mnNetInvRecords *inventory)
+{
+	unsigned i;
+
+	SysInventory[cNum].InventoryNow.isValid = false;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS || !pNCS->pSerialPort)
+		return(MN_ERR_CLOSED);
+	SysInventory[cNum].InventoryLast = inventory->InventoryNow;
+	for (i = 0; i<MN_API_MAX_NODES; i++) {
+		SysInventory[cNum].InventoryNow.LastIDs[i]
+			= SysInventory[cNum].NodeInfo[i].theID;
+	}
+	SysInventory[cNum].InventoryNow.isValid = true;
+	return(MN_OK);
+}
+//																			 *
+//****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcWaitForNetStop
+//
+//	DESCRIPTION:
+//		This function will wait for the current network commands to finish
+//		and their responses to return.
+//
+//	SYNOPSIS:
+void MN_DECL infcWaitForNetStop(netaddr cNum)
+{
+	cnErrCode theErr;
+	packetbuf theCmd, theResp;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS || !pNCS->pSerialPort)
+		return;
+	// If the channel is offline and can't work return immediatly
+	if (SysInventory[cNum].OpenState != OPENED_ONLINE)
+		return;
+	// If there were nodes at one time, send a probe command to sync up, else
+	// return immediately.
+	if (SysInventory[cNum].InventoryLast.NumOfNodes == 0)
+		return;
+	// Generate a command all nodes have: get node ID of first node.
+	theErr = netGetParameterFmt(&theCmd, 0, MN_P_NODEID);
+	if (theErr != MN_OK)
+		return;
+	// Run the command to sync this thread's view of the network
+	// It doesn't matter if this works or not
+	netRunCommand(cNum, &theCmd, &theResp);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcAutoDiscoverRunning
+//
+//	DESCRIPTION:
+//		This function will return true if the network is "offline" and
+//		the auto-discover thread is looking for nodes.
+//
+//	SYNOPSIS:
+nodebool infcAutoDiscoverRunning(netaddr cNum)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS || !pNCS->pSerialPort || !pNCS->pAutoDiscover)
+		return(false);
+	return(pNCS->pAutoDiscover->IsRunning());
+}
+//																			   *
+//******************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcCopyPktToPkt18
+//
+//	DESCRIPTION:
+///		Copy a full packet buffer to truncated one.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+//#if (defined(_WIN32)||defined(_WIN64))
+//static void infcCopyPktToPkt18(packetbuf18 *dest, packetbuf *src)
+//#else
+void infcCopyPktToPkt18(packetbuf18 *dest, packetbuf *src)
+//#endif
+{
+	dest->bufferSize = src->Byte.BufferSize < 18 ? src->Byte.BufferSize : 18;
+	memcpy(&dest->buffer[0], &src->Byte.Buffer[0],
+		dest->bufferSize);
+}
+//																			  *
+//*****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		IsNetClassErr
+//
+//	DESCRIPTION:
+//		Return TRUE if this is a potentially node H/W based error:
+//
+//	RETURNS:
+//		nodebool
+//
+//	SYNOPSIS:
+nodebool IsNetClassErr(
+	cnErrCode theErr)
+{
+	BOOL bErr = FALSE;
+	switch (theErr) {
+	case MN_ERR_FRAME:				/* 0xe:  command frame error */
+	case MN_ERR_OFFLINE:			/* 0x8:  the node is offline */
+	case MN_ERR_PKT_ERR:			/* 0x11: Pkt Error */
+	case MN_ERR_NET_ERRS_DETECT:	/* 0x2c: Network Errors */
+	case MN_ERR_RX_ACCESS:			/* 0x14: RX buffer access/sync problem */
+	case MN_ERR_NET_FRAG:			/* 0x104: Fragmented packet detected */
+	case MN_ERR_SEND_FAILED:		/* 0x200: Command failed to transfer from NC in time */
+	case MN_ERR_SEND_LOCKED:		/* 0x201: Could not acquire NC command interface */
+	case MN_ERR_SEND_UNLOCK:		/* 0x202: Could not release NC command interface */
+	case MN_ERR_RESP_FAILED:		/* 0x203: Response failed to transfer */
+	case MN_ERR_CMD_TIMEOUT:		/* 0x205: Command timeout */
+	case MN_ERR_DEF_RESP_TO:		/* 0x20A: Deferred response time-out */
+	case MN_ERR_ADDR_RANGE:			/* 0x20D: Response from out of range address */
+	case MN_ERR_RESP_TIMEOUT:		/* 0x204: NC response not found in time */
+
+		bErr = TRUE;
+		break;
+	default:
+		// Not sure yet, keep checking
+		break;
+	}
+
+	// Check for network breaks/offline - network breaks and offline are
+	// considered hardware errors
+	if (IsNetBreakErr(theErr))
+		bErr = TRUE;
+
+	return(bErr);
+}
+
+
+// Returns TRUE if this is a net connectivity type error.
+nodebool IsNetBreakErr(
+	cnErrCode theErr)
+{
+	nodebool bErr = (((theErr) >= MN_ERR_NETBREAK_ERR_BASE
+		&& (theErr) <= MN_ERR_NETBREAK_ERR_END)
+		|| ((theErr) == MN_ERR_RESP_TIMEOUT)
+		|| ((theErr) == MN_ERR_SEND_FAILED)
+		|| ((theErr) == MN_ERR_RESET_FAILED)
+		|| ((theErr) == MN_ERR_CMD_OFFLINE));
+	return(bErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		processNodeInitiatedPkt
+//
+//	DESCRIPTION:
+/**
+Process the node initiated data
+
+\param xxx description
+\return description
+**/
+//	SYNOPSIS:
+inline void processNodeInitiatedPkt(netaddr cNum, nodeaddr respAddr,
+	netStateInfo *pNCS, packetbuf &readBuf)
+{
+	infcErrInfo errInfo;		// Error reporting buffer
+	mnAttnReqReg attn;
+	dacqPacket *dataAcqPacket;
+	mnDataAcqPt dataAcqPt[2];
+	nodebool lastOverflow;
+
+	nodeaddr changedNode;
+	mnNetDiagStats *pStats = (mnNetDiagStats *)(&readBuf.Byte.Buffer[CMD_LOC + 1]);
+
+	// See if we do anything with these6
+	mnNetDiagStats *pLog = &SysInventory[cNum].diagStats[readBuf.Fld.Addr];
+	switch (readBuf.Fld.PktType) {
+	case MN_PKT_TYPE_EXTEND_HIGH:
+		switch (readBuf.Byte.Buffer[CMD_LOC]) {
+		case MN_CTL_EXT_NET_DIAG_INFO:
+			SysInventory[cNum].diagsAvailable[readBuf.Fld.Addr] = TRUE;
+			// Fix up new fields found when old firmware in use
+			if ((readBuf.Fld.PktLen - 1) / 2U
+				<= (unsigned)(&pStats->NetVoltsLowCtr - (Uint16 *)pStats)) {
+				pStats->NetVoltsLowCtr = 0;
+			}
+			// Copy to our state
+			*pLog = *pStats;
+			_RPT3(_CRT_WARN, "%.1f readThread(%d) node %d reported err: \n",
+				infcCoreTime(), cNum, readBuf.Fld.Addr);
+			DUMP_PKT(cNum, (char *)"...", &readBuf, true);
+			#ifdef _DEBUG
+			_RPT2(_CRT_WARN, "Net Diag Counters:\tApp Net\t\t\t\tDiag Net reporting node %d, net %d\n",
+				readBuf.Fld.Addr, cNum);
+			_RPT0(_CRT_WARN, "\tfrags\tchks\tstray\tover\t\tfrags\tchks\tstray\tover\tlow V\n");
+			_RPT4(_CRT_WARN, "%8d%8d%8d%8d",
+				pLog->AppNetFragPktCtr, pLog->AppNetBadChksumCtr,
+				pLog->AppNetStrayCtr, pLog->AppNetOverrunCtr);
+			_RPT5(_CRT_WARN, "\t%8d%8d%8d%8d%8d\n",
+				pLog->DiagNetFragPktCtr, pLog->DiagNetBadChksumCtr,
+				pLog->DiagNetStrayCtr, pLog->DiagNetOverrunCtr,
+				pLog->NetVoltsLowCtr);
+			#endif
+			// Let others know of the troubles
+			errInfo.cNum = cNum;
+			errInfo.node = respAddr;
+			errInfo.errCode = MN_ERR_NET_ERRS_DETECT;
+			infcCopyPktToPkt18(&errInfo.response, &readBuf);
+			infcFireErrCallback(&errInfo);
+			break;
+		case MN_CTL_EXT_NET_CHECK:
+			_RPT2(_CRT_WARN, "readThread(%d) detected net integrity check request from node %d\n",
+				cNum, readBuf.Fld.Addr);
+			break;
+		default:
+			_RPT2(_CRT_WARN, "readThread(%d) detected unhandled node generated extended high packet %d\n",
+				cNum, readBuf.Byte.Buffer[CMD_LOC]);
+			break;
+		}
+		break;
+		//case MN_PKT_TYPE_EXTEND_NORMAL:
+		//	break;
+		//case MN_PKT_TYPE_ERROR:
+		//	break;
+	case MN_PKT_TYPE_ATTN_IRQ:
+		attn.AttentionReg.attnBits = *((Uint32 *)&readBuf.Byte.Buffer[RESP_LOC]);
+		// Cleanup the attention bits as required by device
+		attn.AttentionReg.attnBits &= SysInventory[cNum].attnCleanupMask[readBuf.Fld.Addr];
+		attn.MultiAddr = MULTI_ADDR(cNum, readBuf.Fld.Addr);
+		processAttention(attn, pNCS);
+		break;
+	case MN_PKT_TYPE_EXTEND_LOW:
+		switch (readBuf.Byte.Buffer[CMD_LOC]) {
+		case MN_CTL_EXT_LOW_NOP:
+			break;
+		case MN_CTL_EXT_DATA_ACQ:	// Data return originated from the node and is a dataAcq point
+			#if 1
+									// Record DataAcq in Queue - each data point from the node contains 2 point
+			dataAcqPacket = (dacqPacket*)&(readBuf.Byte.Buffer[RESP_LOC + 1]);
+
+			// Replicate the common information
+			dataAcqPt[1].Sequence = dataAcqPt[0].Sequence
+				= dataAcqPacket->Fld.Sequence;
+
+			dataAcqPt[0].Bool0 = dataAcqPt[1].Bool0 = FALSE;
+			dataAcqPt[0].Bool1 = dataAcqPt[1].Bool1 = FALSE;
+
+			dataAcqPt[0].Exception = dataAcqPacket->Fld.Exception0;
+			dataAcqPt[1].Exception = dataAcqPacket->Fld.Exception1;
+
+			dataAcqPt[0].MoveState = dataAcqPacket->Fld.MoveState0;
+			dataAcqPt[1].MoveState = dataAcqPacket->Fld.MoveState1;
+			// Check for alignment issues
+			//dataAcqPt[0].Spare[1] = 0x0111;
+			//dataAcqPt[1].Spare[1] = 0x1111;
+			//dataAcqPt[0].TraceValue[3] = 0.0333;
+			//dataAcqPt[1].TraceValue[3] = 0.1333;
+
+
+			// Calculate fractional (+/-1) first point
+			dataAcqPt[0].TraceValue[0]
+				= (float)dataAcqPacket->Fld.T0p0
+				/ (1 << (P0_BITS - 1));
+
+			dataAcqPt[0].TimeStamp
+				= (double)(pNCS->DataAcq[respAddr].SampleCount)
+				* pNCS->DataAcq[respAddr].SampRateMilliSec;
+			dataAcqPt[1].TimeStamp
+				= dataAcqPt[0].TimeStamp
+				+ pNCS->DataAcq[respAddr].SampRateMilliSec;
+
+			// We have processed two samples
+			pNCS->DataAcq[respAddr].SampleCount += 2;
+
+			// Calculate fractional (+/-1) second point
+			dataAcqPt[1].TraceValue[0]
+				= (float)dataAcqPacket->Fld.T0p1
+				/ (1 << (P1_BITS - 1));
+
+			// If the I/O state was sent in this packet, copy the data to trace 1
+			if (readBuf.Byte.BufferSize == 9) {
+				dataAcqPt[0].TraceValue[1] = (float)((dataAcqPacket->Fld.Trigger0 << (INPUT_BITS + 1))
+					| (dataAcqPacket->Fld.Inputs0 << 1)
+					| dataAcqPacket->Fld.Output0);
+				dataAcqPt[1].TraceValue[1] = (float)((dataAcqPacket->Fld.Trigger1 << (INPUT_BITS + 1))
+					| (dataAcqPacket->Fld.Inputs1 << 1)
+					| dataAcqPacket->Fld.Output1);
+			}
+
+
+			// Check for dropped packet by checking sequence, we are OK if
+			// the init flag is set
+			if (pNCS->DataAcqInit[respAddr]
+				|| (dataAcqPt[0].Sequence
+					== pNCS->DataAcq[respAddr].SeqCheck + 1)
+				|| ((dataAcqPt[0].Sequence == 0)
+					&& (pNCS->DataAcq[respAddr].SeqCheck == 3))) {
+				// Once we get here, init no longer necessary
+				pNCS->DataAcqInit[respAddr] = FALSE;
+				// Sequence is valid (it is an increment from before or it wrapped from 3 to 0)
+				dataAcqPt[0].Valid = VB_TRUE;
+				dataAcqPt[1].Valid = VB_TRUE;
+			}
+			else {
+				// Sequence is invalid
+				dataAcqPt[0].Valid = VB_FALSE;
+				dataAcqPt[1].Valid = VB_FALSE;
+				// 11/4/09 DS Let Reader discover problem, this
+				// just leads to more errors if we callback.
+				// 11/6/10 DS Restoring for diagnostic purposes. Newer error
+				// processing should prevent last year issues
+
+				// Notify that there is an invalid point
+				errInfo.cNum = cNum;
+				errInfo.node = respAddr;
+				errInfo.errCode = MN_ERR_DATAACQ_INVALID;
+				_RPT4(_CRT_WARN, "%.1f data acq seq err@node %d: %d->%d\n", 
+					infcCoreTime(), respAddr, pNCS->DataAcq[respAddr].SeqCheck,
+					dataAcqPt[0].Sequence);
+				infcFireErrCallback(&errInfo);
+				#if TRACE_DACQ_SEQ
+				infcTraceDumpA(cNum, "MeridianSeqErr.dat");
+				#endif
+		}
+			// Save this sequence number in channel state to compare with next sample
+			pNCS->DataAcq[respAddr].SeqCheck = dataAcqPt[0].Sequence;
+			//_RPT1(_CRT_WARN, "%d", respAddr); // Show activity
+
+			// Write the points to the queue, locking out reader
+			pNCS->DataAcq[respAddr].AcqLock.Lock();
+
+			// On overflow deprecate the two oldest points to make room
+			// in buffer for 2 new points marking gap at front
+			lastOverflow = pNCS->DataAcq[respAddr].Overflow;
+			pNCS->DataAcq[respAddr].Overflow
+				= pNCS->DataAcq[respAddr].Points.size()
+				>= (DATAACQ_OVERFLOW_LVL - 2);
+			if (pNCS->DataAcq[respAddr].Overflow) {
+				pNCS->DataAcq[respAddr].Points.pop();
+				pNCS->DataAcq[respAddr].Points.pop();
+				pNCS->DataAcq[respAddr].Points.front().Valid = VB_FALSE;
+			}
+
+			// If an overflow occurred, signal back to app
+			if (pNCS->DataAcq[respAddr].Overflow && !lastOverflow) {
+				// Notify that there was an overflow event
+				errInfo.cNum = cNum;
+				errInfo.node = respAddr;
+				errInfo.errCode = MN_ERR_DATAACQ_INVALID;
+				infcCopyPktToPkt18(&errInfo.response, &readBuf);
+				//						infcFireErrCallback(&errInfo);
+				_RPT2(_CRT_WARN, "%.1f dacq overrun @%d\n",
+					infcCoreTime(), respAddr); // Show activity
+			}
+
+			// Add the two points on queue
+			pNCS->DataAcq[respAddr].Points.push(dataAcqPt[0]);
+			pNCS->DataAcq[respAddr].Points.push(dataAcqPt[1]);
+
+			// Allow reader now
+			pNCS->DataAcq[respAddr].AcqLock.Unlock();
+			#endif
+			break;
+		case MN_CTL_EXT_PARAM_CHANGED:	//A parameter on the node has changed
+										// grab the node id from the packet
+			changedNode = readBuf.Fld.Addr;
+
+			// invalidate the local cache so the data gets re-read from the node
+			coreInvalidateValCacheByNode(cNum, changedNode);
+
+			// call app's callback associated with this
+			if (userInvalCacheFunc != NULL) {
+				(*userInvalCacheFunc)(cNum, changedNode);
+			}
+
+			// also signal to any non-callback apps that would care
+			//   Yes, I'm talking to you, VB/APS!
+			pNCS->paramsHaveChanged[changedNode] = TRUE;
+
+			break;
+		default:
+			_RPT2(_CRT_WARN, "readThread(%d) detected unhandled MN_PKT_TYPE_EXTEND_LOW packet type=%d\n",
+				cNum, readBuf.Byte.Buffer[CMD_LOC]);
+			break;
+	}
+		break;
+	default:
+		_RPT2(_CRT_WARN, "readThread(%d) detected unhandled node generated packet type=%d\n",
+			cNum, readBuf.Fld.PktType);
+		break;
+}
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		processAttention
+//
+//	DESCRIPTION:
+/**
+Process the passed attention. This will release any waiters for the
+user any of the detected bits are unmasked.
+
+\note The reaction functions within and called by this function
+must not use any network functions as the read thread is locked
+until this function completes.
+
+\param theAttn A filled attention structure.
+\param pNCS Network state
+**/
+//	SYNOPSIS:
+inline void processAttention(
+	mnAttnReqReg theAttn,
+	netStateInfo *pNCS)
+{
+	// This is set if this attention should be sent to the user code.
+	bool postAttn;
+	bool disabling;
+	netaddr cNum = pNCS->cNum;
+	//cnErrCode theErr;
+	#if TRACE_ATTN
+	_RPT3(_CRT_WARN, "%.1f attn(%d)=>0x%lx\n", infcCoreTime(), theAttn.MultiAddr, theAttn.AttentionReg.attnBits);
+	#endif
+	// Prevent re-entry until we process all the items. 
+	pNCS->AttnLock.Lock();
+	mnNetInvRecords &theNet = SysInventory[pNCS->cNum];
+	nodeaddr theAddr = NODE_ADDR(theAttn.MultiAddr);
+	disabling = (theAttn.AttentionReg.cpm.Disabled
+		| theAttn.AttentionReg.cpm.GoingDisabled) != 0;
+
+	// Look for what happened and cause internal re-actions if required
+	// Are these the auto-brake related items
+	if ((theAttn.AttentionReg.cpm.Enabled | disabling) != 0
+		&& theNet.attnInitializing == 0) {
+		// Release any brakes?
+		#if TRACE_ATTN
+		_RPT5(_CRT_WARN, "%.1f attn(%d) going disabled=%d, disabled=%d, enabled=%d\n",
+			infcCoreTime(), theAttn.MultiAddr, theAttn.AttentionReg.cpm.GoingDisabled,
+			theAttn.AttentionReg.cpm.Disabled, theAttn.AttentionReg.cpm.Enabled);
+		#endif
+		for (Uint32 i = 0; i<mnNetInvRecords::MAX_BRAKES; i++) {
+			mnNetInvRecords::autoBrakeInfo &brk = theNet.autoBrake[i];
+			if (brk.enabled
+				&& theAttn.MultiAddr == brk.relatedNode
+				&& brk.brakeMode == BRAKE_AUTOCONTROL) {
+				#if TRACE_ATTN || TRACE_BRAKE
+				_RPT4(_CRT_WARN, "%.1f attn(%d) brake(%d) set=%d\n", infcCoreTime(), theAttn.MultiAddr, i,
+					theAttn.AttentionReg.cpm.Disabled);
+				#endif
+				// We engage the brake when we either about to disable or currently are
+				// disabled.
+				/*theErr = */infcBrakeSet(pNCS->cNum, i, disabling);
+		}
+}
+	}
+	// Was there a status event?
+	if (theAttn.AttentionReg.cpm.StatusEvent && theNet.attnInitializing == 0) {
+		#if TRACE_ATTN
+		_RPT2(_CRT_WARN, "%.1f attn(%d) status event\n", infcCoreTime(), theAttn.MultiAddr);
+		#endif
+		// See we are enabled to cause shutdowns
+		if (theNet.GroupShutdownInfo[theAddr].enabled) {
+			theNet.GroupShutdownRequest = true;
+			pNCS->GroupShutdownEvent.SetEvent();
+	}
+	}
+
+	// Apply the attention mask
+	theAttn.AttentionReg.attnBits &= theNet.attnMask[NODE_ADDR(theAttn.MultiAddr)].attnBits;
+	// Tell the user?
+	postAttn = theAttn.AttentionReg.attnBits != 0;
+	if (postAttn) {
+		// If using the class library methods, do not queue.
+		if (SysInventory[cNum].pPortCls->Adv.Attn.Enabled()) {
+			if (SysInventory[cNum].pPortCls->Adv.Attn.HasAttnHandler()) {
+				#if TRACE_ATTN
+				_RPT2(_CRT_WARN, "%.1f attn(%d) invoking user callback\n", infcCoreTime(), theAttn.MultiAddr);
+				#endif
+				SysInventory[cNum].pPortCls->Adv.Attn.InvokeAttnHandler(theAttn);
+			}
+			// Try using the by-node signaler
+			for (int iNode = 0; iNode < SysInventory[cNum].pPortCls->NodeCount(); iNode++) {
+				if (SysInventory[cNum].pPortCls->Nodes(iNode).Info.Ex.Addr() == theAttn.MultiAddr) {
+					SysInventory[cNum].pPortCls->Nodes(iNode).Adv.Attn.SignalAttn(theAttn.AttentionReg);
+				}
+			}
+			pNCS->AttnLock.Unlock();
+		}
+		// Queue and release the lock
+		else {
+			if (pNCS->AttnBuf.size() < ATTN_OVERFLOW_LVL) {
+				pNCS->AttnBuf.push(theAttn);
+				pNCS->AttnLock.Unlock();
+				pNCS->IrqEvent.SetEvent();
+			}
+			else {
+				infcErrInfo theErr;
+				// Post overrun as error
+				pNCS->AttnOverrun = TRUE;
+				pNCS->AttnLock.Unlock();
+				theErr.cNum = pNCS->cNum;
+				theErr.node = theAttn.MultiAddr;
+				theErr.errCode = MN_ERR_ATTN_OVERRUN;
+				theErr.response.bufferSize = 0;
+				infcFireErrCallback(&theErr);
+			}
+		}
+	}
+	else {
+		pNCS->AttnLock.Unlock();
+	}
+	#if TRACE_ATTN
+	_RPT2(_CRT_WARN, "%.1f attn(%d) complete\n", infcCoreTime(), theAttn.MultiAddr);
+	#endif
+}
+/// \endcond																  *
+//******************************************************************************
+
+/****************************************************************************/
+//						    CALLBACK INTERFACES
+/****************************************************************************/
+
+/// \cond INTERNAL_DOC
+/*****************************************************************************
+*	NAME
+*		postErrList
+*
+*	DESCRIPTION:
+*		Log error to the VB error list and .
+*
+*	SYNOPSIS: 															    */
+void postErrList(netStateInfo *pNCS, infcErrInfo *pErrInfo)
+{
+	pNCS->ErrListLock.Lock();
+	size_t nextTail;
+	// Too many there now?
+	if ((nextTail = ((pNCS->ErrListTailPtr + 1) % ERR_CNT_MAX))
+		== pNCS->ErrListHeadPtr) {
+		// Eat oldest item off head
+		pNCS->ErrListHeadPtr++;
+		pNCS->ErrListHeadPtr %= ERR_CNT_MAX;
+	}
+	// Add to tail
+	pNCS->ErrList[pNCS->ErrListTailPtr] = *pErrInfo;
+	pNCS->ErrListTailPtr = nextTail;
+	pNCS->ErrListLock.Unlock();
+
+}
+/// 																  *
+//******************************************************************************
+
+/*****************************************************************************
+*	NAME
+*		infcFireErrCallback
+*
+*	DESCRIPTION:
+*		Fire off the error callback if defined.
+*
+*	SYNOPSIS: 															    */
+void infcFireErrCallback(infcErrInfo *pErrInfo, bool forced)
+{
+	#define ERR_TRACE 1			// Set to force trace debugs
+	infcErrInfo cpyErr;
+	unsigned initCntIn;
+	BOOL isRecovery;
+	netaddr cNum = pErrInfo->cNum;
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	netStateInfo *pNCS = theNet.pNCS;
+	// Port gone
+	if (!pNCS)
+		return;
+	//if (pErrInfo->errCode == MN_ERR_BADARG)
+	//	_RPT0(_CRT_WARN, "Ding\n");
+
+	// Prevent recursion here
+	if (pNCS->errorRecursePrevent>0) {
+		_RPT4(_CRT_WARN, "%.1f infcFireErrCallback(recursion): "
+			"err=0x%x, node=%d, net=%d\n",
+			infcCoreTime(), pErrInfo->errCode,
+			(int)pErrInfo->node, (int)pErrInfo->cNum);
+		attemptAutoDiscover(pErrInfo);
+		return;
+	}
+
+	// we do not want to send an error during shutdown
+	if (pNCS && !pNCS->SelfDestruct) {
+		pNCS->errorRecursePrevent++;
+		// Save the incoming initialization state
+		initCntIn = SysInventory[cNum].Initializing;
+		// Get a copy of the original error
+		cpyErr = *pErrInfo;
+		isRecovery = pNCS->isRecoveryThread();
+		// Split out handling for specific errors
+		switch (cpyErr.errCode) {
+		case MN_ERR_CMD_OFFLINE:
+			break;
+		default:
+			// Real user error during online time or a break diagnostic error, skipping
+			// redundant items on forced situations.
+			if ((((initCntIn == 0) && InitializingGlobal == 0)
+				&& ((theNet.OpenState != FLASHING) && !isRecovery))
+				|| forced) {
+				// Skip if diagnostic same result
+				if (IsNetBreakErr(cpyErr.errCode)
+					&& (cpyErr.errCode == theNet.NetDiagLastResult)) {
+					#if TRACE_CALLBACK
+					_RPT4(_CRT_WARN, "%.1f infcFireErrCallback(%d) ignoring dup err: err=0x%x, node=%d\n",
+						infcCoreTime(), (int)cpyErr.cNum, cpyErr.errCode, (int)cpyErr.node);
+					#endif
+					break;
+				}
+				#if TRACE_CALLBACK
+				_RPT4(_CRT_WARN, "%.1f infcFireErrCallback(%d): err=0x%x, node=%d\n",
+					infcCoreTime(), (int)cpyErr.cNum, cpyErr.errCode, (int)cpyErr.node);
+				#endif
+				// Save the error into queue that is extracted from VB app.
+				// This will prevent a deadlock on error notification due to single
+				// marshalling channel in ActiveX. Are we shutdown now?
+				if (!pNCS->SelfDestruct) {
+					// No we are not shutdown, post the error in the list
+					postErrList(pNCS, &cpyErr);
+					// Node rejection errors are non-serious,
+					// we create a dump file to record issue.
+					if (cpyErr.errCode >= MN_ERR_CMD_ERR_BASE
+						&& cpyErr.errCode <= MN_ERR_CMD_ERR_END
+						&& SysInventory[cNum].AutoDiscoveryEnable) {
+						// Node reject class - just create a trace dump on our dime
+						infcTraceDumpNext(cpyErr.cNum);
+						// Allow another one here
+						theNet.TraceArmed = TRUE;
+						#if ERR_TRACE|TRACE_CALLBACK
+						_RPT4(_CRT_WARN, "%.1f infcFireErrCallback(net rejected type): err=0x%x, node=%d, net=%d\n",
+							infcCoreTime(), pErrInfo->errCode, (int)cpyErr.node, cpyErr.cNum);
+						#endif
+					}
+					else {
+						// More serious issue, start diagnostic and fire off recovery
+						// efforts using offline threads.
+						#if (TRACE_CALLBACK|ERR_TRACE) && defined(_DEBUG)
+						_RPT4(_CRT_WARN, "%.1f infcFireErrCallback(other type): err=0x%x, node=%d, net=%d\n",
+							infcCoreTime(), pErrInfo->errCode, (int)cpyErr.node, (int)cpyErr.cNum);
+						#endif
+						// Log lead-up if possible
+						infcTraceDumpNext(cpyErr.cNum);
+						// If we allow diagnostics and this is not a result of the diagnostics, run them
+						// and start auto-discover to watch for network returning to life.
+						if (IsNetBreakErr(cpyErr.errCode))
+							theNet.NetDiagLastResult = cpyErr.errCode;
+						// See if we need to go back online.
+						attemptAutoDiscover(&cpyErr);
+					}
+				}
+				// Only report external thread's problems and not
+				// initialization errors.
+
+				// Signal user of problem if they registered callback
+				if (userErrCallbackFunc != NULL && !pNCS->SelfDestruct
+					&& pNCS->pAutoDiscover->ThreadID() != infcThreadID()) {
+					(*userErrCallbackFunc)(pErrInfo);
+				}
+			} // ONLINE detected error
+			else {
+				if (isRecovery
+					&& (cpyErr.errCode >= MN_ERR_OFFLINE_00
+						&& cpyErr.errCode <= MN_ERR_OFFLINE_15)) {
+					postErrList(pNCS, &cpyErr);
+					if (userErrCallbackFunc != NULL && !pNCS->SelfDestruct) {
+						(*userErrCallbackFunc)(&cpyErr);
+					}
+				}
+				}
+			break;
+			}
+	}
+	#if TRACE_CALLBACK&0
+	_RPT0(_CRT_WARN, "infcFireErrCallback: complete\n");
+	#endif
+	pNCS->errorRecursePrevent--;
+}
+//																			 *
+//****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcFireNetEvent
+//
+//	DESCRIPTION:
+//		Fire the mnClassEx network event if there is a current reference
+//		to a mnClassEx object.
+//
+//	SYNOPSIS:
+void infcFireNetEvent(netaddr cNum, enum NetworkChanges state)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	#if TRACE_CALLBACK//||1
+	switch (state) {
+	case NODES_OFFLINE:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) OFFLINE\n", infcCoreTime(), cNum);
+		break;
+	case NODES_ONLINE:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) ONLINE\n", infcCoreTime(), cNum);
+		break;
+	case NODES_DRIVER_ONLINE:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) DRIVER ONLINE\n", infcCoreTime(), cNum);
+		break;
+	case NODES_SENDING:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) SENDING\n", infcCoreTime(), cNum);
+		break;
+	case NODES_STOP_NET_CONFIG:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) STOP_NET_CONFIG\n", infcCoreTime(), cNum);
+		break;
+	case NODES_CHANGING_NET_CONTROLLER:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) CHANGING_NET_CONFIG\n", infcCoreTime(), cNum);
+		break;
+	case NODES_RESETTING:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) RESETTING\n", infcCoreTime(), cNum);
+		break;
+	case NODES_BAUD_UNSUPPORTED:
+		_RPT2(_CRT_WARN, "%.1f infcFireNetEvent(%d) BAUD_UNSUPPORTED\n", infcCoreTime(), cNum);
+		break;
+	default:
+		_RPT3(_CRT_WARN, "%.1f infcFireNetEvent(%d)=>%d\n", infcCoreTime(), cNum, state);
+		break;
+		}
+	#endif
+	// Prevent crash on dead net
+	if (!pNCS)
+		return;
+	// Queue in the list if state is changing
+	if (state != pNCS->LastEvent) {
+		pNCS->NetChgListLock.Lock();
+		unsigned nextTail;
+		// Too many there now?
+		if ((nextTail = ((pNCS->NetChgListTailPtr + 1) % NET_EVENTS_MAX))
+			== pNCS->NetChgListHeadPtr) {
+			// Eat oldest item off head
+			pNCS->NetChgListHeadPtr++;
+			pNCS->NetChgListHeadPtr %= NET_EVENTS_MAX;
+		}
+		// Add to tail
+		pNCS->NetChgList[pNCS->NetChgListTailPtr] = state;
+		pNCS->NetChgListTailPtr = nextTail;
+		pNCS->NetChgListLock.Unlock();
+
+		// Implement old online/offline model
+		openStates currentState = SysInventory[cNum].OpenState;
+		switch (state) {
+		case NODES_OFFLINE:
+			if (currentState == OPENED_ONLINE) {
+				if (pNCS->pSerialPort->IsOpen())
+					SysInventory[cNum].OpenStateNext(OPENED_SEARCHING);
+				else
+					SysInventory[cNum].OpenStateNext(CLOSED);
+			}
+			break;
+		case NODES_DRIVER_ONLINE:
+			if (currentState != OPENED_ONLINE) {
+				SysInventory[cNum].OpenStateNext(OPENED_ONLINE);
+			}
+			// Insure auto-brake is reset to current node complement
+
+			break;
+		case NODES_FLASH_MODE:
+			SysInventory[cNum].OpenStateNext(FLASHING);
+			break;
+			// Ignore all others
+		default:
+			break;
+		}
+	}
+	// Signal external watcher our new state
+	if (userNetStateFunc != NULL && pNCS->LastEvent != state) {
+		(*userNetStateFunc)(cNum, SysInventory[cNum].OpenState == OPENED_ONLINE);
+	}
+	// Save our current state as the last state
+	pNCS->LastEvent = state;
+}
+//																			   *
+//******************************************************************************
+
+
+
+//****************************************************************************
+//	NAME
+//		infcFireParamCallback
+//
+//	DESCRIPTION:
+//		Fire the parameter change callback if it not part of the recovery
+//		process.
+//
+//	SYNOPSIS:
+void infcFireParamCallback(paramChangeFunc func, const mnParamChg *pChgItem)
+{
+	mnParamChg copyChg;
+	static unsigned pChgCnt = 0;
+	netStateInfo *pNCS = SysInventory[pChgItem->net].pNCS;
+	if (!pNCS)
+		return;
+	// Create working copy on stack
+	copyChg = *pChgItem;
+	#if 0
+	if (copyChg.paramNum == TG_P_POSN_MEAS && copyChg.node == 1) {
+		_RPT1(_CRT_WARN, "Reading meas32 %.0f\n", copyChg.newValue);
+	}
+	#endif
+	pChgCnt++;
+	if (!pNCS->isRecoveryThread() && !pNCS->SelfDestruct) {
+		if (func) {
+			(*func)(&copyChg);
+		}
+		#ifdef USE_ACTIVEX
+		// Is this using activex class style interface
+		if (mnRef[copyChg.net] != NULL) {
+			HRESULT hr;
+			// Marshall mnClass
+			double tStart = infcCoreTime();
+			#if TRACE_CALLBACK&0
+			//if (copyChg.node == 4) {
+			_RPT4(_CRT_WARN, "%u Fire Param change n=%d p(%d)=%.2f\n",
+				pChgCnt, copyChg.node, copyChg.paramNum, copyChg.newValue);
+			//}
+			#endif
+			mn1::_NetAdapterObj *pMN6 = NULL;
+			long inCurse = InterlockedIncrement(&ncs[copyChg.net].ChangeRecurse);
+			// Marshall the net
+			hr = m_pGIT->GetInterfaceFromGlobal(ncs[copyChg.net].mnCookie,
+				__uuidof(mn1::_NetAdapterObj),
+				(void **)&pMN6);
+			if (hr == 0) {
+				pMN6->FireParameterChanged((mn1::infcParamChg *)&copyChg);
+				pMN6->Release();
+			}
+			inCurse = InterlockedDecrement(&ncs[copyChg.net].ChangeRecurse);
+}
+		#endif
+	}
+}
+//																			 *
+//****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME
+//		infcGetNextError
+//
+//	DESCRIPTION:
+//		Get the next error from list if it exists.
+//
+//	RETURNS:
+//		nodebool TRUE if there was a new item
+//
+//	SYNOPSIS:
+MN_EXPORT nodebool MN_DECL infcGetNextError(
+	netaddr cNum,
+	infcErrInfo *pErrInfo)
+{
+	if (cNum > NET_CONTROLLER_MAX)
+		return(FALSE);
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Anything there?
+	if (!pNCS || pNCS->ErrListHeadPtr == pNCS->ErrListTailPtr)
+		return(FALSE);
+	pNCS->ErrListLock.Lock();
+	// Get copy of head and eat
+	*pErrInfo = pNCS->ErrList[pNCS->ErrListHeadPtr++];
+	// Insure head in bounds
+	pNCS->ErrListHeadPtr %= ERR_CNT_MAX;
+	pNCS->ErrListLock.Unlock();
+	return(TRUE);
+}
+//																			 *
+//****************************************************************************
+
+//****************************************************************************
+//	NAME
+//		infcGetNetErrorStats
+//
+//	DESCRIPTION:
+//		Grab all the net stats from the node.
+//
+//	RETURNS:
+//		
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetNetErrorStats(
+	multiaddr theMultiAddr,
+	nodebool *pIsSet,
+	mnNetDiagStats *pResult)
+{
+	Uint16 stat;
+	cnErrCode theErr = MN_OK, finalErr = MN_OK;
+
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr nodeAddr = NODE_ADDR(theMultiAddr);
+
+	if (pIsSet)
+		*pIsSet = FALSE;	//will get set to true if we make it through the whole function
+
+	if (cNum > NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS)
+		return(MN_ERR_DEV_ADDR);
+
+	switch (SysInventory[cNum].InventoryNow.LastIDs[nodeAddr].fld.devType) {
+	case NODEID_MD:
+	case NODEID_SC:
+	case NODEID_CS:
+		break;
+	default:
+		return(MN_ERR_UNKN_DEVICE);
+	}
+
+	if (!pResult)
+		return(MN_ERR_BADARG);
+
+	// Dump a trace file
+	theErr = infcTraceDumpNext(cNum);
+	if (theErr != MN_OK)
+		finalErr = theErr;
+
+	// Initialize all the stats
+	pResult->AppNetBadChksumCtr = pResult->AppNetFragPktCtr = pResult->AppNetOverrunCtr = pResult->AppNetStrayCtr = -1;
+	pResult->DiagNetBadChksumCtr = pResult->DiagNetFragPktCtr = pResult->DiagNetOverrunCtr = pResult->DiagNetStrayCtr = -1;
+	pResult->NetVoltsLowCtr = -1;
+	// Grab all the data from the node
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_APP_CHKSUM, &stat);
+	if (theErr == MN_OK)
+		pResult->AppNetBadChksumCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_APP_FRAG, &stat);
+	if (theErr == MN_OK)
+		pResult->AppNetFragPktCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_APP_OVERRUN, &stat);
+	if (theErr == MN_OK)
+		pResult->AppNetOverrunCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_APP_STRAY, &stat);
+	if (theErr == MN_OK)
+		pResult->AppNetStrayCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_DIAG_CHKSUM, &stat);
+	if (theErr == MN_OK)
+		pResult->DiagNetBadChksumCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_DIAG_FRAG, &stat);
+	if (theErr == MN_OK)
+		pResult->DiagNetFragPktCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_DIAG_OVERRUN, &stat);
+	if (theErr == MN_OK)
+		pResult->DiagNetOverrunCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_DIAG_STRAY, &stat);
+	if (theErr == MN_OK)
+		pResult->DiagNetStrayCtr = stat;
+	else
+		finalErr = theErr;
+	theErr = coreBaseGetParameterInt(cNum, nodeAddr, MN_P_NETERR_LOW_VOLTS, &stat);
+	if (theErr == MN_OK)
+		pResult->NetVoltsLowCtr = stat;
+	else
+		finalErr = theErr;
+
+	if (pIsSet)
+		*pIsSet = TRUE;
+	return(finalErr);
+}
+//																			 *
+//****************************************************************************
+
+//****************************************************************************
+//	NAME
+//		infcParamsHaveChanged
+//
+//	DESCRIPTION:
+//		Have any params on the given node changed? If so, clear the change bit
+//		and return that the node was changed
+//
+//	RETURNS:
+//		nodebool TRUE if there was a change
+//
+//	SYNOPSIS:
+MN_EXPORT nodebool MN_DECL infcParamsHaveChanged(
+	multiaddr multiAddr)
+{
+	netaddr cNum = NET_NUM(multiAddr);
+	nodeaddr nodeAddr = NODE_ADDR(multiAddr);
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (cNum >= NET_CONTROLLER_MAX || !pNCS)
+		return FALSE;
+
+	if (pNCS->paramsHaveChanged[nodeAddr]) {
+		pNCS->paramsHaveChanged[nodeAddr] = FALSE;
+		return TRUE;
+	}
+	else
+		return FALSE;
+
+}
+//																			 *
+//****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME
+//		infcGetDiagBlock
+//
+//	DESCRIPTION:
+//		Get the new diagnostic block state. When TRUE the network diagnostic
+//		is prevented from running.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcGetDiagBlock(
+	netaddr cNum,
+	nodebool *state)
+{
+	*state = SysInventory[cNum].NetDiagBlock;
+	return(MN_OK);
+}
+//																			 *
+//****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME
+//		infcSetDiagBlock
+//
+//	DESCRIPTION:
+//		Set the new diagnostic block state. When TRUE the network diagnostic
+//		is prevented from running.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcSetDiagBlock(
+	netaddr cNum,
+	nodebool state)
+{
+	_RPT2(_CRT_WARN, "infcSetDiagBlock(%d) <= %d\n", cNum, state);
+	SysInventory[cNum].NetDiagBlock = state;
+	return(MN_OK);
+}
+//																			 *
+//****************************************************************************
+
+//****************************************************************************
+//	NAME
+//		infcGetOnlineState
+//
+//	DESCRIPTION:
+//		Get the initializing flag.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetOnlineState(
+	netaddr cNum,
+	nodebool *state)
+{
+	if (cNum < NET_CONTROLLER_MAX) {
+		*state = SysInventory[cNum].OpenState == OPENED_ONLINE;
+		return(MN_OK);
+	}
+	else
+		return(MN_ERR_DEV_ADDR);
+}
+//																			 *
+//****************************************************************************
+
+//****************************************************************************
+//	NAME
+//		infcGetOnlineStateEx
+//
+//	DESCRIPTION:
+//		Get the initializing flag.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetOnlineStateEx(
+	netaddr cNum,
+	openStates *state)
+{
+	if (cNum < NET_CONTROLLER_MAX) {
+		*state = SysInventory[cNum].OpenState;
+		return(MN_OK);
+	}
+	else
+		return(MN_ERR_DEV_ADDR);
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		infcGetNextNetChange
+//
+//	DESCRIPTION:
+//		Retrieve the oldest net change from the net change queue.
+//
+//	RETURNS:
+//		TRUE if there is one
+//
+//	SYNOPSIS:
+MN_EXPORT nodebool MN_DECL infcGetNextNetChange(
+	netaddr cNum,
+	NetworkChanges *pNetChange)
+{
+	if (cNum<SysPortCount) {
+		netStateInfo *pNCS = SysInventory[cNum].pNCS;
+		// Anything there?
+		if (!pNCS || pNCS->NetChgListHeadPtr == pNCS->NetChgListTailPtr)
+			return(FALSE);
+		pNCS->NetChgListLock.Lock();
+		// Get copy of head and eat
+		*pNetChange = pNCS->NetChgList[pNCS->NetChgListHeadPtr++];
+		// Insure head in bounds
+		pNCS->NetChgListHeadPtr %= NET_EVENTS_MAX;
+		pNCS->NetChgListLock.Unlock();
+		return(TRUE);
+	}
+	return(FALSE);
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		infcGetIOlock
+//
+//	DESCRIPTION:
+//		Acquire the I/O critical section lock. Release with
+//		infcReleaseIOlock()
+//
+//	RETURNS:
+//		When Lock is acquired
+//
+//	SYNOPSIS:
+void infcGetIOlock(netaddr cNum)
+{
+	if (cNum > SysPortCount)
+		return;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (pNCS)
+		pNCS->IOlock.Lock();
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		infcReleaseIOlock
+//
+//	DESCRIPTION:
+//		Release the I/O critical section lock acquired by infcGetIOlock()
+//
+//	SYNOPSIS:
+void infcReleaseIOlock(netaddr cNum)
+{
+	if (cNum > SysPortCount)
+		return;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (pNCS)
+		pNCS->IOlock.Unlock();
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		infcProbeForOffline
+//
+//	DESCRIPTION:
+//		Probe the last known network and fire errors off for all the nodes
+//		found offline.
+//
+//	RETURNS:
+//		#cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode infcProbeForOffline(netaddr cNum, nodeulong *pNodesNow)
+{
+	cnErrCode theErr;
+	#if TRACE_LOW_PRINT
+	_RPT1(_CRT_WARN, "infcProbeForOffline(%d) starting\n", cNum);
+	#endif
+	// Assume same node count as last at start
+	*pNodesNow = SysInventory[cNum].InventoryLast.NumOfNodes;
+	// See if we have basic connectivity
+	#if TRACE_BREAK
+	_RPT3(_CRT_WARN, "%.1f in infcProbeForOffline(%d) calling infcResetNetRate,"
+		"thread ID=" THREAD_RADIX_LONG "\n",
+		infcCoreTime(), cNum, infcThreadID());
+	#endif
+	//theErr = infcResetNetRate(cNum);
+	//if (theErr == MN_OK) {
+		// Yes, probe for crashed nodes by asking for their node
+		// IDs. If node crashed it will echo this command and return
+		// MN_ERR_OFFLINE.
+		unsigned i;
+		for (i = 0; i<SysInventory[cNum].InventoryLast.NumOfNodes; i++) {
+			packetbuf theResp;
+			theErr = netGetParameter(MULTI_ADDR(cNum, i),
+				MN_P_NODEID,
+				&theResp);
+			// Find someone offline?
+			//	if (theErr == MN_ERR_OFFLINE)  {
+			//		netGetParameter will post errors as it goes
+			//	}
+		}
+		// Restore online state
+		*pNodesNow = 0;
+		// Restore addressing for next probe
+		theErr = netSetAddress(cNum, pNodesNow);
+	//}
+	//else {
+	//	*pNodesNow = 0;
+	//}
+	#if TRACE_LOW_PRINT
+	if (theErr != MN_OK) {
+		_RPT2(_CRT_WARN, "infcProbeForOffline(%d) returns 0x%x\n", cNum, theErr);
+	}
+	#endif
+	return(theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcSetPortSpecifier
+//
+//	DESCRIPTION:
+///		Store the physical port number for this controller in the by
+///		controller data base.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL  infcSetPortSpecifier(
+	netaddr cNum,					// Controller slot
+	const portSpec *portSpec	// x of COMx, LPTx, etc
+	)
+{
+	// Bound problem?
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	SysInventory[cNum].PhysPortSpecifier = *portSpec;
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGetPortSpecifier
+//
+//	DESCRIPTION:
+///		Get the physical port number for this controller in the by
+///		controller data base.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL  infcGetPortSpecifier(
+	netaddr cNum,					// Controller slot
+	portSpec *portSpec		// Controller specifier
+	)
+{
+	// Bound problem?
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	*portSpec = SysInventory[cNum].PhysPortSpecifier;
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcSetAutoNetDiscovery
+//
+//	DESCRIPTION:
+///		Control the auto-recovery state setting.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcSetAutoNetDiscovery(
+	netaddr cNum,
+	nodebool newState)
+{
+	// Bound problem?
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	// Persist across restarts
+	//_RPT3(_CRT_WARN, "%.1f infcSetAutoNetDiscovery(%d)=%d\n", 
+	//	infcCoreTime(), cNum, newState);
+	SysInventory[cNum].AutoDiscoveryEnable = newState;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (!pNCS)
+		return(MN_ERR_OFFLINE);
+
+	if (!newState)
+		infcHaltAutoNetDiscovery(cNum);
+	return(MN_OK);
+}
+
+MN_EXPORT cnErrCode MN_DECL infcGetAutoNetDiscovery(
+	netaddr cNum,
+	nodebool *currentState)
+{
+	// Bound problem?
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	*currentState = SysInventory[cNum].AutoDiscoveryEnable;
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcBackgroundPollControl
+//
+//	DESCRIPTION:
+///		Control the operations of the background poller. This polling thread
+///		keeps the watchdog timer from expiring when the driver is loaded.
+///
+///		This function returns when the thread has entered the desired state.
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcBackgroundPollControl(
+	netaddr cNum,
+	nodebool start)
+{
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f infcBackgroundPollControl(%d): start=%d\n",
+		infcCoreTime(), cNum, start);
+	#endif
+	// Bound problem?
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Persist the request
+	SysInventory[cNum].KeepAlivePollEnable = start;
+	// If we are currently online, use this as the restore state as well
+	if (!SysInventory[cNum].Initializing)
+		SysInventory[cNum].KeepAlivePollRestoreState = start;
+
+	if (pNCS) {
+		if (start) {
+			pNCS->pPollerThread->Start();
+		}
+		else {
+			pNCS->pPollerThread->Stop();
+		}
+	}
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f infcBackgroundPollControl(%d): exited\n",
+		infcCoreTime(), cNum);
+	#endif
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGet/SetOtherNetSnoop
+//
+//	DESCRIPTION:
+///		Control and get the DTR pin state on the serial port. This is used to
+///		snoop on traffic from the other net via our serial channel. This
+///		feature will disrupt the other channel's data and must be used with
+///		care to prevent system errors.
+//
+//	SYNOPSIS:
+void infcSetOtherNetSnoop(netaddr cNum,
+	nodebool TheDTRValue)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (pNCS->pSerialPort) {
+		if (TheDTRValue)
+			pNCS->pSerialPort->SetDTR(true);
+		else
+			pNCS->pSerialPort->SetDTR(false);
+	}
+}
+void infcGetOtherNetSnoop(netaddr cNum,
+	nodebool *pTheDTRValue)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (pTheDTRValue && pNCS->pSerialPort) {
+		*pTheDTRValue = (pNCS->pSerialPort->GetDTR());
+	}
+}
+
+//																			   *
+//******************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcFlushDataAcq
+//
+//	DESCRIPTION:
+///		Flush the currently stored data acquisition points.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcFlushDataAcq(multiaddr multiAddr)
+{
+	netaddr cNum = NET_NUM(multiAddr);
+	nodeaddr respAddr = NODE_ADDR(multiAddr);
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	//_RPT2(_CRT_WARN, "%.1f infcFlushDataAcq(%d)\n", infcCoreTime(), multiAddr);
+	if (cNum > SysPortCount || pNCS == NULL)
+		return(MN_ERR_BADARG);
+
+	pNCS->DataAcq[respAddr].AcqLock.Lock();
+
+	while (!(pNCS->DataAcq[respAddr].Points.empty())) {
+		pNCS->DataAcq[respAddr].Points.pop();
+	}
+
+	pNCS->DataAcq[respAddr].Overflow = FALSE;
+	pNCS->DataAcq[respAddr].SampleCount = 0;
+	pNCS->DataAcq[respAddr].AcqLock.Unlock();
+
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcInitDataAcq
+//
+//	DESCRIPTION:
+///		Record the sample rate for this node.
+//
+//	SYNOPSIS:
+cnErrCode infcInitDataAcq(
+	multiaddr multiAddr,
+	double SampleRateMicroSec)
+{
+	netaddr cNum = NET_NUM(multiAddr);
+	//_RPT2(_CRT_WARN, "%.1f infcInitDataAcq(%d)\n", infcCoreTime(), cNum);
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	pNCS->DataAcq[NODE_ADDR(multiAddr)].SampRateMilliSec
+		= SampleRateMicroSec * 2 / 1000;
+	// Restart the sequence number on next packet
+	pNCS->DataAcqInit[NODE_ADDR(multiAddr)] = TRUE;
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGetDataAcqPt
+//
+//	DESCRIPTION:
+///		Get up to \e ptsToRead samples in the user supplied \e pTheDataAcqPt
+///		buffer. The actual number of samples returned is stored in
+///		\e pPtsRead.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetDataAcqPt(
+	multiaddr multiAddr,
+	nodeulong ptsToRead,
+	mnDataAcqPt pTheDataAcqPt[],
+	nodeulong *pPtsRead)
+{
+	cnErrCode errRet = MN_OK;
+	netaddr cNum = NET_NUM(multiAddr);
+	nodeaddr theAddr = NODE_ADDR(multiAddr);
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	// Hint this is heavily used value
+	register netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	// Protect against bad arguments
+	if (pPtsRead == NULL)
+		return MN_ERR_BADARG;
+
+	// Lock out the writer until we are done copying
+	pNCS->DataAcq[theAddr].AcqLock.Lock();
+
+	// If empty avoid dequeue error on read
+	if (pNCS->DataAcq[theAddr].Points.empty()) {
+		pNCS->DataAcq[theAddr].AcqLock.Unlock();
+		return MN_ERR_DATAACQ_EMPTY;
+	}
+
+	*pPtsRead = 0;
+	//_RPT3(_CRT_WARN, "%.1f infcGetDataAcqPt(%d) len=%d\n", infcCoreTime(), multiAddr, ptsToRead);
+	// Copy up to the requester's defined buffer length
+	while (!(pNCS->DataAcq[theAddr].Points.empty())
+		&& *pPtsRead<ptsToRead) {
+		pTheDataAcqPt[*pPtsRead] = pNCS->DataAcq[theAddr].Points.front();
+		pNCS->DataAcq[theAddr].Points.pop();
+		(*pPtsRead)++;
+	}
+	pNCS->DataAcq[theAddr].Overflow = FALSE;
+	// Writer can now run
+	pNCS->DataAcq[theAddr].AcqLock.Unlock();
+
+	return errRet;
+}
+//																			   *
+//******************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGetDataAcqPt
+//
+//	DESCRIPTION:
+///		Return the number of data acquisition points available for this node.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetDataAcqPtCount(
+	multiaddr multiAddr,
+	nodeulong *pPointCount)
+{
+	netaddr cNum = NET_NUM(multiAddr);
+	netStateInfo *pNCS;
+	// Bounds and arg check
+	if ((multiAddr == MN_UNSET_ADDR) || cNum > SysPortCount
+		|| (pNCS = SysInventory[cNum].pNCS, pNCS == NULL)
+		|| pPointCount == NULL)
+		return MN_ERR_BADARG;
+	*pPointCount
+		= (nodeulong)pNCS->DataAcq[NODE_ADDR(multiAddr)].Points.size();
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+//*****************************************************************************
+//	NAME
+//		infcSetAddressFmt
+//
+//	DESCRIPTION:
+//		Create the re-address the network command using <startingAddr> as
+//		the first node.
+//
+//		NOTE:	The network is addressed starting from <startingAddr>.  For normal
+//				operation caller should initialize <startingAddr> with 0.
+//
+//	RETURNS:
+//		MN_OK, else the error condition
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcSetAddressFmt(
+	nodeulong startingAddr,		// Net address start here
+	packetbuf *theCmd)
+{
+	theCmd->Fld.PktLen = 0;
+	theCmd->Fld.Addr = startingAddr;
+	theCmd->Fld.PktType = MN_PKT_TYPE_SET_ADDR;
+	theCmd->Fld.Mode = theCmd->Fld.Zero1 = 0;	// Fill in unused with 0
+	theCmd->Fld.Src = MN_SRC_HOST;
+	theCmd->Byte.BufferSize = theCmd->Fld.PktLen + MN_API_PACKET_HDR_LEN;
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcBreakChkFmt
+//
+//	DESCRIPTION:
+//		Format the command buffer with the command that sends a packet
+//		around the Meridian ring for a bring-net detection
+//
+//		NOTE: this command must be sent via the low-level transmission
+//		function to preserve the cc_err field.
+//
+//	RETURNS:
+//		standard error return
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL infcBreakChkFmt(
+	packetbuf *theCmd)			// ptr to a command buffer
+{
+	theCmd->Fld.Src = MN_SRC_HOST;
+	theCmd->Fld.PktType = MN_PKT_TYPE_EXTEND_HIGH;
+	theCmd->Fld.Addr = 0;
+	theCmd->Fld.PktLen = 1;
+	theCmd->Fld.Zero1 = theCmd->Fld.Mode = 0;
+	theCmd->Byte.Buffer[CMD_LOC] = MN_CTL_EXT_NET_CHECK;
+	theCmd->Byte.BufferSize = theCmd->Fld.PktLen + MN_API_PACKET_HDR_LEN;
+	return(MN_OK);
+
+}
+//																   		      *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcBrokenRingDiag
+//
+//	DESCRIPTION:
+//		This diagnostic works for all newer nodes that supports the flow
+//		control diagnostic control packet. This diagnostic will disrupt
+//		traffic on the other network if ran.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode infcBrokenRingDiag(
+	netaddr cNum,
+	nodebool hasConnectivity,
+	unsigned knownNodeCount)
+{
+	packetbuf theCmd, theResp;
+	//nodebool ChkSuccessful[MN_API_MAX_NODES]={FALSE};
+	nodebool CurNetOK = FALSE;
+	nodebool CurNetGarbled = FALSE;
+	int netBreakLastAddrOK = -1;
+	unsigned AltNodeCounted;
+	cnErrCode errRet = MN_OK;
+	mnNetSrcs otherNet = MN_SRC_UNKNOWN_NET;
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	netStateInfo *pNCS = theNet.pNCS;
+	double startTimeMS, currentTimeMS;
+
+	// --------- Check continuity on the current net ---------
+	CurNetOK = FALSE;
+	CurNetGarbled = FALSE;
+
+	// Insure we leave with DTR clear
+	infcSetOtherNetSnoop(cNum, FALSE);
+
+	// Send probe command if we have connectivity. If not we will try
+	// a blind send later of this command and look for results.
+	if (hasConnectivity) {
+		// Run the probe command
+		infcBreakChkFmt(&theCmd);
+		errRet = infcRunCommand(cNum, &theCmd, &theResp);
+		// If we succeed, we are done. Care must be taken not disturb the
+		// other running net.
+		if ((CurNetOK = (errRet == MN_OK))) {
+			// A successful read happened, make sure the response is correct
+			// which is to say the same as what we sent.
+			if (theResp.Fld.PktType == theCmd.Fld.PktType					// Right type
+				&&  theResp.Fld.Src == theCmd.Fld.Src							// Node originated
+				&&  theResp.Byte.Buffer[CMD_LOC] == theCmd.Byte.Buffer[CMD_LOC]	// Same cmd
+				&& theResp.Byte.BufferSize == 3) {								// Size OK
+																				// OK done.
+				return(errRet);
+			}
+			// We got a response, but it was garbage
+			CurNetGarbled = TRUE;
+		}
+	}
+	// We either have no net or got garbage back if <CurNetGarbled> is TRUE.
+
+	// --------- END - Check continuity on the current net ---------
+
+	// Stop the read thread to allow special command cases
+	pNCS->ReadThread.Stop();
+	pNCS->pSerialPort->AutoFlush(false);
+	// Make sure we are in packet mode.
+	pNCS->pSerialPort->SetMode(SERIALMODE_MERIDIAN_7BIT_PACKET);
+
+	// Count the number of nodes seen on the alternate net
+	// by switching the net adapter to monitor the other ring and wait
+	// for responses to appear.
+
+	// Set alternate-net node counted to 0. This variable will be increased as nodes are found
+	AltNodeCounted = 0;
+
+	// Insure we have some addresses up to the break.
+	infcSetAddressFmt(0, &theCmd);
+	// Blind send an addressing packet to give nodes up to the break
+	// an address.
+	errRet = infcSendCommandLog(cNum, &theCmd);
+	if (errRet != MN_OK) {
+		goto coreBreakDiagnostic_Exit;
+	}
+
+	// Enable the DTR line to get data from other ring to our serial port
+	infcSetOtherNetSnoop(cNum, TRUE);
+
+	// Send network break check packet to force traffic onto other net
+	infcBreakChkFmt(&theCmd);
+	errRet = infcSendCommandLog(cNum, &theCmd);
+	if (errRet != MN_OK) {
+		// Put serial port back into pass-through
+		infcSetOtherNetSnoop(cNum, FALSE);
+		goto coreBreakDiagnostic_Exit;
+	}
+
+	// If the other net is online, activity on that net can be seen and
+	// keep the while loop going - use a timeout to prevent getting stuck
+	currentTimeMS = startTimeMS = infcCoreTime();
+
+	// Poll the other network via DTR switch to detect which nodes
+	// heard the packet.
+	// Add a timeout because the other net could be sending commands
+	while (((errRet = infcGetResponse(cNum, &theResp)) == MN_OK) &&
+		(currentTimeMS - startTimeMS < 100)) {
+		theNet.logReceive(&theResp, errRet, NULL, infcCoreTime());
+
+		// A successful read happened, make sure the response is correct
+		if (theResp.Fld.PktType == MN_PKT_TYPE_EXTEND_HIGH		// Right type
+			&&  theResp.Fld.Src == MN_SRC_NODE						// Node originated
+			&&  theResp.Byte.Buffer[CMD_LOC] == MN_CTL_EXT_NET_CHECK	// Same cmd
+			&&  theResp.Byte.BufferSize == 3) {								// Size OK
+																			// The other net is set in the mode field
+			otherNet = (mnNetSrcs)theResp.Fld.Mode;
+			// Update entry in the array
+			//ChkSuccessful[theResp.Fld.Addr]=TRUE;
+			// Record the highest responding address
+			if (netBreakLastAddrOK < (int)theResp.Fld.Addr)
+				netBreakLastAddrOK = theResp.Fld.Addr;
+			AltNodeCounted++;
+		}		// 	if ( correct packet type )
+
+		currentTimeMS = infcCoreTime();
+		theNet.logReceive(&theResp, errRet, NULL, infcCoreTime());
+	}	// while(infcGetResponse(cNum, &theResp)==MN_OK) {
+
+		// Put serial port back into pass-through
+	infcSetOtherNetSnoop(cNum, FALSE);
+
+	// --------- END - Count the number of nodes seen on the alternate net ---------
+
+	// ------ Interpret the values:
+	//	CurNetOK - whether the current net is fully connected
+	//	AltNodeCounted - How many nodes were counted on the alternate ring
+	//	CurNetGarbled - whether there is a garbled response from the current net
+	if (CurNetGarbled) {
+		errRet = MN_ERR_BRK_LOC_UNKNOWN;
+		goto coreBreakDiagnostic_Exit;
+	}
+
+	// If there are no nodes found, it could either by alternate ring broken,
+	// or the RX of the current ring is broken
+	if (netBreakLastAddrOK < 0) {
+		switch (pNCS->OurNetConnector) {
+		case MN_SRC_APP_NET:
+			errRet = MN_ERR_BRK_APP_LOC_UNKNOWN;
+			break;
+		case MN_SRC_DIAG_NET:
+			errRet = MN_ERR_BRK_DIAG_LOC_UNKNOWN;
+			break;
+		default:
+			errRet = MN_ERR_BRK_LOC_UNKNOWN;
+			break;
+		}
+	}
+	else {
+		// If we had no known nodes, see if alternate net detection
+		// got us some information.
+		if (knownNodeCount == 0) {
+			// We are starting from unknown start due to break somewhere.
+			if (AltNodeCounted > 0) {
+				// We did get hits from other net via DTR switch, therefore
+				// we know the net we are connected. Break is after
+				// the highest reported node on the other net. There
+				// maybe other nodes past this point, but we can't tell.
+				if (otherNet == MN_SRC_APP_NET)
+					// Problem somewhere after netBreakLastAddrOK
+					errRet = (cnErrCode)(MN_ERR_BRK_DIAG_00_HOST
+						+ (cnErrCode)(netBreakLastAddrOK));
+				else
+					errRet = (cnErrCode)(MN_ERR_BRK_APP_00_HOST
+						+ (cnErrCode)(netBreakLastAddrOK));
+			}
+			else
+				// We go no responses, therefore we know nothing new other
+				// than its broken,
+				errRet = MN_ERR_BRK_LOC_UNKNOWN;
+		}
+		else {
+			// There were nodes at one time, therefore we know location more
+			// accurately
+			if (netBreakLastAddrOK + 1 >= (int)knownNodeCount) {
+				switch (pNCS->OurNetConnector) {
+				case MN_SRC_APP_NET:
+					errRet = (cnErrCode)(MN_ERR_BRK_APP_00_HOST
+						+ (cnErrCode)(netBreakLastAddrOK));
+					break;
+				case MN_SRC_DIAG_NET:
+					errRet = (cnErrCode)(MN_ERR_BRK_DIAG_00_HOST
+						+ (cnErrCode)(netBreakLastAddrOK));
+					break;
+				default:
+					errRet = (cnErrCode)(MN_ERR_BRK_00_HOST
+						+ (cnErrCode)(netBreakLastAddrOK));
+					break;
+				}
+			}
+			else {
+				switch (pNCS->OurNetConnector) {
+				case MN_SRC_APP_NET:
+					errRet = (cnErrCode)(MN_ERR_BRK_APP_00_01
+						+ (cnErrCode)(netBreakLastAddrOK));
+					break;
+				case MN_SRC_DIAG_NET:
+					errRet = (cnErrCode)(MN_ERR_BRK_DIAG_00_01
+						+ (cnErrCode)(netBreakLastAddrOK));
+					break;
+				default:
+					errRet = (cnErrCode)(MN_ERR_BRK_OTHER_00_01
+						+ (cnErrCode)(netBreakLastAddrOK));
+					break;
+				}
+			}
+		}
+	}
+	// ------ END - Interpret the values ---------------------
+
+
+coreBreakDiagnostic_Exit:
+	// Restore read thread
+	pNCS->ReadThread.Start();
+	return errRet;
+}
+//																   		      *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcGetNetSource
+//
+//	DESCRIPTION:
+///		Tell drive what net the serial port is attached to.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT mnNetSrcs MN_DECL infcGetNetSource(netaddr cNum)
+{
+	// Bounds check
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_SRC_UNKNOWN_NET);
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (!pNCS)
+		return(MN_SRC_UNKNOWN_NET);
+
+	return(pNCS->OurNetConnector);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcSetNetSource
+//
+//	DESCRIPTION:
+///		Tell drive what net the serial port is attached to.
+///
+/// 	\param xxx description
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+void infcSetNetSource(netaddr cNum, mnNetSrcs theNet)
+{
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	pNCS->OurNetConnector = theNet;
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		infcTraceDumpNext
+//
+//	DESCRIPTION:
+//		If trace dump is armed, and we have not made too many of them since
+//		the session start, create dump directory in the user's temporary area
+//		and then write the next file in sequence there.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode infcTraceDumpNext(netaddr cNum)
+{
+	char fPath[MAX_PATH], winDir[MAX_PATH];
+	cnErrCode theErr = MN_OK;
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	netStateInfo *pNCS = theNet.pNCS;
+
+	// If pNCS is NULL, exit
+	if (!pNCS) {
+		_RPT1(_CRT_WARN, "infcTraceDumpNext %d skipped, pNCS = NULL.\n", cNum);
+		return(MN_OK);
+	}
+
+	// Only perform if armed
+	if (!theNet.TraceArmed) {
+		//_RPT1(_CRT_WARN, "infcTraceDumpNext %d skipped, not armed.\n", cNum);
+		return(MN_OK);
+	}
+	// Reset dumps until online again
+	theNet.TraceArmed = FALSE;
+	// Get our temporary location
+	infcGetDumpDir(winDir, MAX_PATH);
+	// Setup the next number
+	InfcLastDumpNumber++;
+	InfcLastDumpNumber %= DUMP_WRAP_NUM;				// Wrap to ten files
+	theNet.TraceCount++;
+	// Insure directory is created, we ignore errors the dump will create
+	// an appropriate error.
+	#if (defined(_WIN32)||defined(_WIN64))
+	mkdir(winDir);
+	#else
+	mkdir(winDir, 0755);
+	#endif
+	// Create full name
+	sprintf((char*)fPath, "%sMNuserDriver%d-%d.dat", winDir, cNum,
+		InfcLastDumpNumber);
+	if (theNet.TraceCount < DUMP_WRAP_NUM) {
+		//_RPT1(_CRT_WARN, "infcTraceDumpNext dumping %s\n", fPath);
+		theErr = infcTraceDumpA(cNum, (nodeANSIstr)fPath);
+	}
+	//else {
+	//	_RPT1(_CRT_WARN, "infcTraceDumpNext skipped, too many @ cnt %d\n",
+	//					  theNet.TraceCount);
+	//}
+	return(theErr);
+	}
+//																			  *
+//*****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME																	 *
+//		infcCmdCompleteCallback
+//
+//	DESCRIPTION:
+/**
+This function registers a callback function that is called after the a
+node responds to any commands from the host computer.
+
+The callback function template is declared as:
+\code
+infcCmdCompleteCallback priorHandler;
+void MN_DECL myCmdCompletionHandler(mnCompletionInfo *pCmdStats) {
+// Signal your application the stats for this command
+...
+// If prior handler exists, call it.
+if (priorHandler)
+(*priorHandler)(pCmdStats);
+}
+
+...
+
+// Register a callback
+priorHandler = infcCmdCompleteCallback(myCmdCompletionHandler);
+\endcode
+
+\param[in] newFunc Pointer to the call back function
+\return The pointer of the previous callback function that was assigned for this
+callback
+
+\see \ref mnCompletionInfo
+**/
+//	RETURNS:
+//		infcAboutRunCallback
+//
+//	SYNOPSIS:
+MN_EXPORT infcCmdCompleteCallback MN_DECL infcSetCmdCompleteFunc(
+	infcCmdCompleteCallback newFunc)
+{
+	infcCmdCompleteCallback oldFunc = userCmdCompleteFunc;
+	userCmdCompleteFunc = newFunc;
+	return(oldFunc);
+}
+//																			 *
+//****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME																	 *
+//		infcSetInvalCacheFunc
+//
+//	DESCRIPTION:
+//		This function registers a callback function that is called after
+//		a node indicates that a param has been changed and the param cache
+//		should be invalidated. The callback function template is declared as:
+//			void (*funcPtr)(netaddr net, nodeaddr node)
+//
+//	RETURNS:
+//		infcInvalCacheCallback
+//
+//	SYNOPSIS:
+MN_EXPORT infcInvalCacheCallback MN_DECL infcSetInvalCacheFunc(
+	infcInvalCacheCallback newFunc)
+{
+	infcInvalCacheCallback oldFunc = userInvalCacheFunc;
+	userInvalCacheFunc = newFunc;
+	return(oldFunc);
+}
+
+
+// End of INTERNAL_DOC
+/// \endcond
+
+
+
+
+//==============================================================================
+// DOCUMENTED API FUNCTIONS GO BELOW THIS LINE
+//==============================================================================
+/**
+\addtogroup LinkGrp
+@{
+**/
+/// \cond ISC_DOC
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcGetBackgroundErrs
+//
+//	DESCRIPTION:
+/**
+Get network error statistics detected by the nodes.
+The statistics are then cleared as part of the function call.
+
+\param[in] theMultiAddr The address code for this node.
+\param[out] pIsSet Ptr boolean result set non-zero if there was a
+a statistic item present.
+\param[out] pResult Ptr to statistic that was collected.
+\return #cnErrCode; MN_OK if \p pResult was updated and \p pIsSet is non-zero
+if there was a stored statistic.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetBackgroundErrs(
+	multiaddr theMultiAddr,
+	nodebool *pIsSet,
+	mnNetDiagStats *pResult)
+{
+	netaddr cNum = NET_NUM(theMultiAddr);
+	// Did they spec a location?
+	if (!pResult)
+		return(MN_ERR_BADARG);
+	if (!pIsSet)
+		return(MN_ERR_BADARG);
+	*pIsSet = false;
+	// Is the requested node in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+	netaddr nodeAddr = NODE_ADDR(theMultiAddr);
+	if (nodeAddr >= SysInventory[cNum].InventoryNow.NumOfNodes)
+		return(MN_ERR_PARAM_RANGE);
+
+	// Get our net's state
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Anything there?
+	if (pNCS && SysInventory[cNum].diagsAvailable[nodeAddr]) {
+		*pResult = SysInventory[cNum].diagStats[nodeAddr];
+		*pIsSet = VB_TRUE;
+		SysInventory[cNum].diagsAvailable[nodeAddr] = FALSE;
+		SysInventory[cNum].diagStats[nodeAddr].Clear();
+	}
+	else {
+		*pIsSet = VB_FALSE;
+		pResult->Clear();
+	}
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcGetHostErrStats
+//
+//	DESCRIPTION:
+/**
+Get network error statistics detected by the host computer.
+The statistics are then cleared as part of the function call.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[out] pIsSet Ptr boolean result set non-zero if there was a
+statistic item present.
+\param[out] pResult Ptr to statistic that was collected.
+\return #cnErrCode; MN_OK if \p pResult was updated and \p pIsSet is non-zero
+if there was a stored statistic.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcGetHostErrStats(
+	netaddr cNum,
+	nodebool *pIsSet,
+	mnNetDiagStats *pResult)
+{
+	// Is the requested node in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+	// Did they spec a location?
+	if (!pResult)
+		return(MN_ERR_BADARG);
+	if (!pIsSet)
+		return(MN_ERR_BADARG);
+
+	// Anything there?
+	*pResult = SysInventory[cNum].diagStats[MN_API_MAX_NODES];
+	*pIsSet = VB_TRUE;
+	SysInventory[cNum].diagsAvailable[MN_API_MAX_NODES] = FALSE;
+	SysInventory[cNum].diagStats[MN_API_MAX_NODES].Clear();
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+//		infcTraceDumpA
+//
+//	DESCRIPTION:
+/**
+Dump and reset the trace log with a ANSI string interface.
+
+\param[in] cNum Channel number to for node. The first channel is zero.
+\param[in] filePath The ANSI string of the dump file to create from this
+channel.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcTraceDumpA(
+	netaddr cNum,
+	const char *filePath)
+{
+	wchar_t uniStr[MAX_PATH];
+	mbstowcs(uniStr, filePath, MAX_PATH);
+	return(infcTraceDump(cNum, uniStr));
+}
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcTraceDump
+//
+//	DESCRIPTION:
+/**
+Dump and reset the trace log using the UNICODE interface.
+
+\param cNum Channel number. The first channel is zero.
+\param pFilePath A null terminated UNICODE string that represents the
+file to store into. The directory path must exist prior to calling this
+function.
+
+\return #cnErrCode; MN_OK if dump was succesfully created
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcTraceDump(
+	netaddr cNum,
+	const wchar_t *pFilePath)
+{
+	std::ofstream outStream;
+	Uint32 len;
+	txTraceBuf zero;
+	traceHeader theHeader;
+	cnErrCode theErr = MN_OK;
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	netStateInfo *pNCS = theNet.pNCS;
+
+	// Skip if we are gone!
+	if (!pNCS)
+		return(MN_ERR_CLOSED);
+	// Create the file
+	#if defined(__linux__)||defined(__GNUC__)
+	char utf8Path[MAX_PATH];
+	wcstombs(utf8Path, pFilePath, MAX_PATH);
+	outStream.open(utf8Path, ios::out | ios::binary);
+	#else
+	outStream.open(pFilePath, std::ios::out | std::ios::binary);
+	#endif
+	if (!outStream.is_open()) {
+		return(MN_ERR_OS);
+	}
+
+	// Send the header size
+	len = sizeof(theHeader);
+	if (!outStream.write((char *)&len, sizeof(len))) {
+		return(MN_ERR_OS);
+	}
+	// Lock out updates
+	theNet.RXlogLock.Lock();
+	theNet.TXlogLock.Lock();
+	// Send the header
+	theHeader.type = DUMP_TYPE_NUM;
+	//02-06-2012 DS Not sure why this is off by one?
+	theHeader.numOfNodes = SysInventory[cNum].InventoryLast.NumOfNodes - 1;
+	theHeader.nextRXrecord = (Uint32)theNet.rxTraceIndx;
+	theHeader.nextTXrecord = (Uint32)theNet.txTraceIndx;
+	theHeader.version = infcVersion();
+	theHeader.kernVersion = 0;
+	theHeader.traceLen = SEND_DEPTH;
+	theHeader.hdrLen = sizeof(theHeader);
+	infcFileNameA(theHeader.filename, TRACE_FILEPATH_LEN);
+	#if (defined(_WIN32)||defined(_WIN64))
+	_ftime(&theHeader.timestamp);
+	#else
+	// Convert to 64 bit time buffer
+	struct timeb lclTime;
+	ftime(&lclTime);
+	theHeader.timestamp.time = lclTime.time;
+	theHeader.timestamp.millitm = lclTime.millitm;
+	theHeader.timestamp.timezone = lclTime.timezone;
+	theHeader.timestamp.dstflag = lclTime.dstflag;
+	#endif
+	if (theNet.respSerNum < SEND_DEPTH) {
+		len = theNet.respSerNum;
+	}
+	else {
+		len = SEND_DEPTH;
+	}
+	theHeader.nRXrecords = len;
+	if (theNet.sendSerNum < SEND_DEPTH) {
+		len = theNet.sendSerNum;
+	}
+	else {
+		len = SEND_DEPTH;
+	}
+	theHeader.nTXrecords = len;
+	theHeader.diags = NetDiags[cNum];
+	//mnNetInvRecords *pInv = &SysInventory[cNum].InventoryLast;
+	for (len = 0; len<MN_API_MAX_NODES; len++) {
+		theHeader.nodeTypes[len] = SysInventory[cNum].InventoryNow.LastIDs[len];
+	}
+	if (!outStream.write((char *)&theHeader.type,
+		sizeof(theHeader) - sizeof(len))) {
+		theErr = MN_ERR_OS;
+	}
+	// Store the receive information
+	if (theErr == MN_OK && !outStream.write((char*)&theNet.rxTraces[0],
+		sizeof(rxTraceBuf)*theHeader.nRXrecords)) {
+		theErr = MN_ERR_OS;
+	}
+
+	// Store the transmit information
+	if (theErr == MN_OK && !outStream.write((char*)&theNet.txTraces[0],
+		sizeof(txTraceBuf)*theHeader.nTXrecords)) {
+		theErr = MN_ERR_OS;
+	}
+	// Release the lock on the trace updates
+	theNet.RXlogLock.Unlock();
+	theNet.TXlogLock.Unlock();
+	// Got the file open, write out the buffer
+	outStream.close();
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcNetAttnFlush
+//
+//	DESCRIPTION:
+/**
+Flush all detected attentions.
+
+\param[in] cNum Channel number. The first channel is zero.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have cleared all past attentions.
+- MN_ERR_DEV_ADDR cNum out of range
+*/
+MN_EXPORT cnErrCode MN_DECL infcNetAttnFlush(
+	netaddr cNum)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// No port no storage, we're done.
+	if (!pNCS)
+		return MN_OK;
+
+	pNCS->AttnLock.Lock();
+	// No overruns now
+	pNCS->AttnOverrun = false;
+	// Zap items
+	while (!pNCS->AttnBuf.empty()) {
+		pNCS->AttnBuf.pop();
+	}
+	pNCS->AttnLock.Unlock();
+	return (MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcNetGetAttnReq
+//
+//	DESCRIPTION:
+/**
+Wait for a new attention to arrive or retrieve the oldest attention
+request from the specified network.
+
+Attentions are high priority network packets that implement
+an interrupt-like event on detected node events. This feature
+reduces the need for host polling on certain events.
+
+Typically this function is called from a loop within a dedicated
+"interrupt" thread. When it returns MN_OK the attention is inspected
+and the user application will change state or notify some other part of
+its code that this event occured.
+
+Before attentions can be received, the desired nodes must unmask status
+bits on which notification is required.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[out] pRequest Ptr to result when function returns MN_OK.
+
+\return #cnErrCode; Typical Return Values
+- MN_OK A valid attention update exists in the \a pRequest buffer.
+- MN_ERR_ATTN_OVERRUN There has been a loss of attentions due to
+insufficient service rate or flood generated by a node.	No value is
+returned.
+- MN_ERR_TIMEOUT There have not been any attentions in the last second. No
+value is returned.
+.
+
+\see \ref mnAttnsPage
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL infcNetGetAttnReq(
+	netaddr cNum,
+	mnAttnReqReg *pRequest)
+{
+	BOOL waitOK;
+	ULONG waitPeriod = 1000;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	if (!pNCS)
+		return MN_ERR_CLOSED;
+
+	// Signal a loss occurred
+	if (pNCS->AttnOverrun) {
+		pNCS->AttnOverrun = FALSE;
+		return MN_ERR_ATTN_OVERRUN;
+	}
+
+	// If we have one, just return it, otherwise wait
+	if (pNCS->AttnBuf.empty()) {
+		// Wait for the interrupt to occur or the timeout
+		waitOK = pNCS->IrqEvent.WaitFor(waitPeriod);
+	}
+	else {
+		waitOK = TRUE;
+	}
+	// If this did not time-out get and reset the event
+	if (waitOK && !pNCS->AttnBuf.empty()) {
+		// Get flags and reset the interrupt event
+		#if TRACE_ATTN
+		_RPT1(_CRT_WARN, "%.1f ntInfc.WaitForIrq\n", infcCoreTime());
+		#endif
+		pNCS->AttnLock.Lock();
+		// get the attn from the queue
+		*pRequest = pNCS->AttnBuf.front();
+		// remove the item
+		pNCS->AttnBuf.pop();
+		// reset the event if there are no more to get
+		if (pNCS->AttnBuf.empty())
+			pNCS->IrqEvent.ResetEvent();
+
+		pNCS->AttnLock.Unlock();
+		return MN_OK;
+	}
+	return(MN_ERR_TIMEOUT);
+	}
+//																			  *
+//*****************************************************************************
+
+
+
+/****************************************************************************/
+//						 CALLBACK SETUP INTERFACES
+/****************************************************************************/
+
+//*****************************************************************************
+//	NAME
+//		infcNetStateFunc
+//
+//	DESCRIPTION:
+/**
+This function registers a callback function that is called when network
+changes state from online to offline or vice versa.
+
+\note There should be no attempt to call any of the S-Foundation library
+APIs as deadlock could occur.
+
+An example of a state change function and setup is below:
+\code
+infcNetStateCallback priorHandler;
+void MN_DECL myNetStateHandler(nodeshort cNum, nodebool online) {
+// Signal your application something happened
+...
+// If prior handler exists, call it.
+if (priorHandler)
+(*priorHandler)(cNum, online);
+}
+
+...
+
+// Register a callback
+priorHandler = infcNetStateCallback(myNetStateHandler);
+\endcode
+
+\param[in] newFunc Pointer to the call back function
+\return The pointer of the previous callback function that was
+assigned for this callback.	This allows for chained handlers.
+**/
+//
+//	RETURNS:
+//		infcNetStateCallback
+//
+//	SYNOPSIS:
+MN_EXPORT infcNetStateCallback MN_DECL infcSetNetStateFunc(
+	infcNetStateCallback newFunc)
+{
+	infcNetStateCallback oldFunc = userNetStateFunc;
+	userNetStateFunc = newFunc;
+	return(oldFunc);
+}
+//																			 *
+//****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcSetErrorFunc
+//
+//	DESCRIPTION:
+/**
+This function registers a callback function that is called when network
+communication errors occurs. When this function is called it
+is provided with the network address of the error as well as
+an #cnErrCode error number.
+
+\note The function is not called from the main thread and should
+not initiate any new network traffic or calls to the
+S-Foundation APIs. Deadlock could occur if this is done.
+
+The sample callback function template could be declared as:
+\code
+infcErrCallback priorHandler;
+void MN_DECL myNetworkErrorHandler(infcErrInfo *infcErrInfo) {
+// Signal your application something happened
+...
+// If prior handler exists, call it.
+if (priorHandler)
+(*priorHandler)(infcErrInfo);
+}
+
+...
+
+// Register a callback
+priorHandler = infcSetErrorFunc(myNetworkErrorHandler);
+\endcode
+
+\param[in] newFunc Pointer to the call back function
+\return The pointer of the previous callback function that was
+assigned for this callback.
+
+\see \ref infcErrInfo
+**/
+//
+//	RETURNS:
+//		Old handler
+//
+//	SYNOPSIS:
+MN_EXPORT infcErrCallback MN_DECL infcSetErrorFunc(
+	infcErrCallback newFunc)
+{
+	infcErrCallback oldFunc;
+	oldFunc = userErrCallbackFunc;
+	userErrCallbackFunc = newFunc;
+	return (oldFunc);
+}
+/// \endcond																  *
+//*****************************************************************************
+
+
+//******************************************************************************
+//******************************************************************************
+//						netPollerThread IMPLEMENTATION
+//******************************************************************************
+///	\cond INTERNAL_DOC
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPollerThread::netPollerThread construction and destruction
+//
+//	DESCRIPTION:
+/**
+
+
+\param[in,out] xxx description
+\return description
+
+**/
+//	SYNOPSIS:
+netPollerThread::netPollerThread(netStateInfo *pTheNetInfo)
+{
+	#if TRACE_THREAD || TRACE_DESTRUCT || TRACE_POLL_THRD
+	_RPT1(_CRT_WARN, "%.1f netPollerThread constructing\n",
+		infcCoreTime());
+	#endif
+	#if (defined(_WIN32)||defined(_WIN64))
+	SetDLLterm(true);
+	#endif
+	// Insure we halt at HALTED state
+	m_InternalSyncAck.ResetEvent();
+	m_halted = true;
+	pNCS = pTheNetInfo;
+	pNCS->GroupShutdownEvent.ResetEvent();
+}
+
+netPollerThread::~netPollerThread() {
+	#if TRACE_THREAD || TRACE_DESTRUCT || TRACE_POLL_THRD
+	double sTime = infcCoreTime();
+	#endif
+	// Insure we exit
+	Terminate();
+	WaitForTerm();
+	#if TRACE_THREAD || TRACE_DESTRUCT || TRACE_POLL_THRD
+	_RPT2(_CRT_WARN, "%.1f netPollerThread destructed, elapsed=%.1f\n",
+		infcCoreTime(), infcCoreTime() - sTime);
+	#endif
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPollerThread::Run
+//
+//	DESCRIPTION:
+/**
+This thread polls the first one on this network to maintain the watchdog
+timer. It is halted in offline and in serial port mode.
+
+\param[in,out] xxx description
+\return description
+
+**/
+//	SYNOPSIS:
+int netPollerThread::Run(void *context)
+{
+	// Create the address for node 0 on our net
+	int cntr = 0;
+
+	infcErrInfo errInfo;					// Error reporting buffer
+	cnErrCode theErr;
+	packetbuf outPkt;
+	packetbuf inPkt;
+	// Set instance net information
+	pNCS = (netStateInfo *)context;
+	netaddr cNum = pNCS->cNum;
+	multiaddr theNodeAddr = MULTI_ADDR(cNum, 0);
+	mnNetInvRecords &theNet = SysInventory[pNCS->cNum];
+
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f netPollerThread(%d): id=" THREAD_RADIX " starting\n",
+		infcCoreTime(), cNum, UIthreadID());
+	#endif
+	// Prevent initialize race
+	m_critSection.Lock();
+	m_halted = true;
+	// Ack we have halted
+	m_InternalSyncAck.SetEvent();
+	// Allow start
+	m_critSection.Unlock();
+	// Build the out packet
+	outPkt.Fld.SetupHdr(MN_PKT_TYPE_EXTEND_LOW, theNodeAddr);
+	outPkt.Fld.PktLen = 2;
+	outPkt.Byte.Buffer[CMD_LOC] = MN_CTL_EXT_HOST_ALIVE;
+	outPkt.Byte.Buffer[CMD_LOC + 1] = cntr;
+	outPkt.Byte.BufferSize = outPkt.Fld.PktLen + MN_API_PACKET_HDR_LEN;
+	// Loop to read the device ID of the first node.
+	while (!Terminating()) {
+		// Wait for something to wake us up
+		m_RunControl.WaitFor();
+		// Wait for start to begin our polling
+		#if TRACE_POLL_THRD||TRACE_THREAD
+		if (m_halted) {
+			_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): Halting!\n",
+				infcCoreTime(), cNum);
+		}
+		#endif
+		// Do they want our thread to exit?
+		if (Terminating()) {
+			#if TRACE_POLL_THRD||TRACE_THREAD
+			_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): Terminating!\n",
+				infcCoreTime(), cNum);
+			#endif
+			break;
+		}
+		// Start to halt
+		if (!m_halted) {
+			// Driver state allows operations?
+			if (SysInventory[cNum].OpenState == OPENED_ONLINE) {
+				// Issue node stops if we had detected the need or externally
+				// issued.
+				if (theNet.GroupShutdownRequest) {
+					_RPT1(_CRT_WARN, "%.1f Group Shutdown Request\n", infcCoreTime());
+					// Is there group node stop request?
+					// Process the ClearPath SC nodes
+					for (size_t i = 0; i < theNet.InventoryNow.mnCpScInfo.count; i++) {
+						multiaddr theAddr = theNet.InventoryNow.mnCpScInfo.node[i];
+						ShutdownInfo &sInfo = theNet.GroupShutdownInfo[NODE_ADDR(theAddr)];
+						if (sInfo.enabled) {
+							_RPT3(_CRT_WARN, "%.1f Group Shutdown(%d) type %0x\n",
+								infcCoreTime(), theAddr,
+								sInfo.theStopType.bits);
+							theErr = netNodeStop(theAddr, sInfo.theStopType, false);
+						}
+					}
+					// If other node types implement the GroupShutdown feature, process them here
+
+					// Wait for next request
+					theNet.GroupShutdownRequest = false;
+				}
+				else {
+					// Runnning. Send low-level get to insure no caching
+					theErr = infcRunCommand(cNum, &outPkt, &inPkt);
+
+					// Check that the contents of the return packet match the contents of the sent packet
+					bool pktMismatch = outPkt.Byte.BufferSize != inPkt.Byte.BufferSize;
+					for (nodeulong iByte = 0; iByte < outPkt.Byte.BufferSize && !pktMismatch; iByte++) {
+						pktMismatch = pktMismatch || outPkt.Byte.Buffer[iByte] != inPkt.Byte.Buffer[iByte];
+					}
+					// If the command failed, it is handled elsewhere
+					pktMismatch = pktMismatch && theErr == MN_OK;
+
+					cntr++;
+					outPkt.Byte.Buffer[CMD_LOC + 1] = cntr & 0xff;
+					#if TRACE_POLL_THRD||TRACE_THREAD
+					if ((cntr % 10) == 0) {
+						_RPT0(_CRT_WARN, "Polled 10 more\n");
+					}
+					#endif
+					// Ack we have started
+					m_InternalSyncAck.SetEvent();
+					if (theErr != MN_OK || pktMismatch) {
+						#if TRACE_POLL_THRD||TRACE_THREAD
+						_RPT3(_CRT_WARN, "%.1f netPollerThread(%d): probe cmd err=0x%x\n",
+							infcCoreTime(), cNum, theErr);
+						#endif
+						if (pktMismatch) {
+							// Fire off the error callback
+							errInfo.cNum = cNum;
+							errInfo.node = theNodeAddr;
+							errInfo.errCode = MN_ERR_CMD_OFFLINE;
+							infcFireErrCallback(&errInfo);
+							_RPT3(_CRT_WARN, "%.1f netPollerThread::Run(%d): response err 0x%x\n",
+								infcCoreTime(), cNum, errInfo.errCode);
+							// Create dump file on this error
+							infcTraceDumpNext(cNum);
+						}
+						// Stop this until recovery occurs
+						m_critSection.Lock();
+						m_halted = true;
+						// Don't allow loop to run again.
+						m_RunControl.ResetEvent();
+						m_critSection.Unlock();
+						#if TRACE_POLL_THRD||TRACE_THREAD
+						_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): Error Halted!\n",
+							infcCoreTime(), cNum);
+						#endif
+					}
+					#if 0
+					else {
+						// Probe was OK, perform additional polling
+						_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): probe OK\n",
+							infcCoreTime(), cNum);
+					}
+					#endif				
+				} // else not group shutdown
+			}
+			else {
+				// Say we started now, even offline
+				m_InternalSyncAck.SetEvent();
+			}
+			// Wait until we try again
+			//CThread::Sleep(pNCS->pollDelayTimeMS);
+			pNCS->GroupShutdownEvent.WaitFor(pNCS->pollDelayTimeMS);
+			pNCS->GroupShutdownEvent.ResetEvent();
+			#if TRACE_POLL_THRD||TRACE_THREAD
+			_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): Poll delay complete\n",
+				infcCoreTime(), cNum);
+			#endif
+		} // if (!m_halted)
+		// If halted, insure we stop
+		m_critSection.Lock();
+		if (m_halted && !Terminating()) {
+			m_RunControl.ResetEvent();
+			m_InternalSyncAck.SetEvent();
+		}
+		m_critSection.Unlock();
+		if (Terminating())
+			break;
+	}  // while(!Terminating())
+	// We are forced halted.
+	m_critSection.Lock();
+	m_halted = true;
+	m_InternalSyncAck.SetEvent();
+	m_critSection.Unlock();
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f netPollerThread(%d), ID=" THREAD_RADIX
+		" exit via loop termination!\n",
+		infcCoreTime(), cNum, UIthreadID());
+	#endif
+	return(777);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPollerThread::Start
+//
+//	DESCRIPTION:
+/**
+Start the polling thread and return when running.
+**/
+//	SYNOPSIS:
+void netPollerThread::Start()
+{
+	cnErrCode errRet;
+	packetbuf fwVers;
+	#define FWVER ((versID_t *)(&fwVers.Byte.Buffer[0]))
+	#define CP_P_FW_VERS 1
+	#define ISC_P_FW_VERSION 1
+	#define CP_MILESTONE_POLLER 0x1109
+	#define ISC_MILESTONE_POLLER 0x5600
+
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f netPollerThread(%d): starting poll...,term=%d\n",
+		infcCoreTime(), pNCS->cNum, Terminating());
+	#endif
+	// Lock down the read state
+	m_critSection.Lock();
+	// Already running?
+	if (!m_halted || Terminating()) {
+		#if TRACE_POLL_THRD||TRACE_THREAD
+		_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): already running\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		m_critSection.Unlock();
+		return;
+	}
+	// Make sure Node 0 supports the ping 
+	bool pollerSupported = false;
+	errRet = MN_OK;		// Assume good, until a real failure occurs
+	if (SysInventory[pNCS->cNum].NodeInfo[0].theID.fld.devType == NODEID_CP) {
+		errRet = netGetParameter(MULTI_ADDR(pNCS->cNum, 0), CP_P_FW_VERS, &fwVers);
+		if (errRet == MN_OK && FWVER->verCode >= CP_MILESTONE_POLLER) {
+			pollerSupported = true;
+		}
+	}
+	if (errRet == MN_OK && SysInventory[pNCS->cNum].NodeInfo[0].theID.fld.devType == NODEID_MD) {
+		errRet = netGetParameter(MULTI_ADDR(pNCS->cNum, 0), ISC_P_FW_VERSION, &fwVers);
+		if (errRet == MN_OK && FWVER->verCode >= ISC_MILESTONE_POLLER) {
+			pollerSupported = true;
+		}
+	}
+	if (errRet == MN_OK && SysInventory[pNCS->cNum].NodeInfo[0].theID.fld.devType == NODEID_CS) {
+		errRet = netGetParameter(MULTI_ADDR(pNCS->cNum, 0), MN_P_FW_VERSION, &fwVers);
+		if (errRet == MN_OK) {
+			pollerSupported = true;
+		}
+	}
+	// Not supported or lost contact?
+	if (!pollerSupported || errRet != MN_OK) {
+		#if TRACE_POLL_THRD||TRACE_THREAD
+		_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): not supported\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		m_critSection.Unlock();
+		return;
+	}
+
+	// Disarm ACK
+	m_InternalSyncAck.ResetEvent();
+	// Set state before restarting thread
+	m_halted = false;
+	m_RunControl.SetEvent();
+	m_critSection.Unlock();
+	m_InternalSyncAck.WaitFor();
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): poll running\n",
+		infcCoreTime(), pNCS->cNum);
+	#endif
+	}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPollerThread::Stop
+//
+//	DESCRIPTION:
+/**
+Stop the polling thread and return when stopped.
+**/
+//	SYNOPSIS:
+void netPollerThread::Stop()
+{
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT3(_CRT_WARN, "%.1f netPollerThread(%d): stopping poll...,term=%d\n",
+		infcCoreTime(), pNCS->cNum, Terminating());
+	#endif
+	// Lock down the read state
+	m_critSection.Lock();
+	// Already stopped?
+	if (m_halted) {
+		#if TRACE_POLL_THRD||TRACE_THREAD
+		_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): already stopped\n",
+			infcCoreTime(), pNCS->cNum);
+		#endif
+		// We are halted, leave state alone
+		m_critSection.Unlock();
+		return;
+	}
+	// We are running, get things to stop
+	m_halted = true;
+	m_RunControl.SetEvent();
+	if (!Terminating())
+		m_InternalSyncAck.ResetEvent();
+	else
+		m_InternalSyncAck.SetEvent();
+
+	// Allow thread to run
+	m_critSection.Unlock();
+	BOOL waitOK = m_InternalSyncAck.WaitFor();
+	if (!waitOK) {
+		_RPT2(_CRT_WARN, "%.1f netPollerThread(%d) wait failed\n",
+			infcCoreTime(), pNCS->cNum);
+	}
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): poll stopped\n",
+		infcCoreTime(), pNCS->cNum);
+	#endif
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPollerThread::Terminate
+//
+//	DESCRIPTION:
+/**
+Insure the thread exits in a timely manner.
+
+\param[in,out] xxx description
+\return description
+
+**/
+//	SYNOPSIS:
+void *netPollerThread::Terminate()
+{
+	#if TRACE_POLL_THRD||TRACE_THREAD
+	_RPT2(_CRT_WARN, "%.1f netPollerThread(%d): terminate set\n",
+		infcCoreTime(), pNCS->cNum);
+	#endif
+	*m_pTermFlag = true;
+	m_RunControl.SetEvent();
+	pNCS->GroupShutdownEvent.SetEvent();
+
+	// Set the terminate flag
+	void *rVal = CThread::Terminate();
+	return rVal;
+}
+//																			  *
+//*****************************************************************************
+/// \endcond 
+
+/// \cond CPM_CLIB
+
+//******************************************************************************
+//	NAME																	   *
+//		infcCommUnitPowered
+//
+//	DESCRIPTION:
+/**
+Query that Comm Unit is powered up.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[in] brakeNum Brake number. The first brake is zero.
+\param[in] engaged Operational state of the brake.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have set the brake override.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_PORT_PROBLEM port not available
+- MN_ERR_BADARG Target is not a Comm Unit
+*/
+MN_EXPORT cnErrCode MN_DECL infcCommUnitPowered(
+	netaddr cNum,
+	nodebool *pIsPowered)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB)
+		return MN_ERR_BADARG;
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (!pNCS || !pNCS->pSerialPort)
+		return MN_ERR_PORT_PROBLEM;
+	// Does the hub board have power?
+	*pIsPowered = pNCS->pSerialPort->GetDSR();
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcBrakeSet
+//
+//	DESCRIPTION:
+/**
+Set the specified brake override bit.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[in] brakeNum Brake number. The first brake is zero.
+\param[in] engaged Operational state of the brake.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have set the brake override.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_PORT_PROBLEM port not available or no power
+- MN_ERR_PARAM_RANGE brakeNum invalid
+- MN_ERR_BADARG Target is not a ClearPath-SC system
+*/
+cnErrCode infcBrakeSet(
+	netaddr cNum,
+	size_t brakeNum,
+	nodebool engaged,
+	nodebool forced)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	if (brakeNum >= mnNetInvRecords::MAX_BRAKES)
+		return MN_ERR_PARAM_RANGE;
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB && !forced)
+		return MN_ERR_BADARG;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (!pNCS || !pNCS->pSerialPort)
+		return MN_ERR_PORT_PROBLEM;
+
+	#if TRACE_BRAKE
+	_RPT3(_CRT_WARN, "%.1f brake %d, engaged=%d\n", infcCoreTime(), brakeNum, engaged);
+	#endif
+	switch (brakeNum) {
+	case 0:
+		pNCS->pSerialPort->SetDTR(!engaged);
+		break;
+	case 1:
+		pNCS->pSerialPort->SetRTS(!engaged);
+		break;
+	}
+
+	return MN_OK;
+
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		infcBrakeGet
+//
+//	DESCRIPTION:
+/**
+Get the specified brake bit.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[in] brakeNum Brake number. The first brake is zero.
+\param[out] pBrakeVal Operational state of the brake.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have returned the brake override.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_PORT_PROBLEM port not available or no power
+- MN_ERR_PARAM_RANGE brakeNum invalid
+- MN_ERR_BADARG pBrakeVal invalid or target network is not
+a ClearPath-SC
+*/
+cnErrCode infcBrakeGet(
+	netaddr cNum,
+	size_t brakeNum,
+	nodebool *pEngaged,
+	nodebool forced)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	if (brakeNum >= mnNetInvRecords::MAX_BRAKES)
+		return MN_ERR_PARAM_RANGE;
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB && !forced)
+		return MN_ERR_BADARG;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (!pNCS || !pNCS->pSerialPort)
+		return MN_ERR_PORT_PROBLEM;
+
+	if (!pEngaged)
+		return MN_ERR_BADARG;
+
+	switch (brakeNum) {
+	case 0:
+		*pEngaged = !pNCS->pSerialPort->GetDTR();
+		break;
+	case 1:
+		*pEngaged = !pNCS->pSerialPort->GetRTS();
+		break;
+	}
+
+	return MN_OK;
+
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		infcGlobalStopGet
+//
+//	DESCRIPTION:
+/**
+Get the specified global stop bit.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[out] pEngaged Operational state of the brake.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have returned the brake override.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_PORT_PROBLEM port not available or no power
+- MN_ERR_PARAM_RANGE brakeNum invalid
+- MN_ERR_BADARG pBrakeVal invalid or target network is not
+a ClearPath-SC
+*/
+MN_EXPORT cnErrCode MN_DECL infcGlobalStopGet(
+	netaddr cNum,
+	nodebool *pEngaged)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB)
+		return MN_ERR_BADARG;
+
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+
+	if (!pNCS || !pNCS->pSerialPort)
+		return MN_ERR_PORT_PROBLEM;
+
+	if (!pEngaged)
+		return MN_ERR_BADARG;
+
+	*pEngaged = !pNCS->pSerialPort->GetCTS();
+
+	return MN_OK;
+
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		infcBrakeControlSet
+//
+//	DESCRIPTION:
+/**
+Set the specified brake control mode.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[in] brakeNum Brake number. The first brake is zero.
+\param[in] brakeVal Operational state of the brake.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have set the brake override.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_PORT_PROBLEM port not available
+- MN_ERR_PARAM_RANGE brakeNum or brakeVal invalid
+*/
+MN_EXPORT cnErrCode MN_DECL infcBrakeControlSet(
+	netaddr cNum,
+	size_t brakeNum,
+	BrakeControls brakeVal)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	if (brakeNum >= mnNetInvRecords::MAX_BRAKES)
+		return MN_ERR_BADARG;
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB)
+		return MN_ERR_BADARG;
+
+	cnErrCode attnOffErr = MN_OK;
+	// If exiting autobrake mode, turn off the autobrake attentions
+	if (SysInventory[cNum].autoBrake[brakeNum].brakeMode == BRAKE_AUTOCONTROL
+		&& brakeVal != BRAKE_AUTOCONTROL
+		&& SysInventory[cNum].autoBrake[brakeNum].enabled
+		&& SysInventory[cNum].autoBrake[brakeNum].relatedNode != MN_UNSET_ADDR) {
+		// Save but ignore the error for now
+		attnOffErr = infcAutoBrakeSet(cNum, brakeNum, false,
+			SysInventory[cNum].autoBrake[brakeNum].relatedNode);
+	}
+	SysInventory[cNum].autoBrake[brakeNum].brakeMode = brakeVal;
+	nodebool engaged;
+
+	switch (brakeVal) {
+	case BRAKE_PREVENT_MOTION:
+	case GPO_OFF:
+		engaged = true;
+		break;
+	case BRAKE_ALLOW_MOTION:
+	case GPO_ON:
+		engaged = false;
+		break;
+	case BRAKE_AUTOCONTROL:
+		// Configure the autobrake
+		return infcAutoBrakeSet(cNum, brakeNum, true,
+			SysInventory[cNum].autoBrake[brakeNum].relatedNode);
+	default:
+		return MN_ERR_BADARG;
+	}
+	// Make sure the brake is set to final state if possible.
+	cnErrCode setErr = infcBrakeSet(cNum, brakeNum, engaged);
+	// Return error that we didn't clean-up OK.
+	if (attnOffErr != MN_OK) return attnOffErr;
+	return setErr;
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		infcBrakeControlGet
+//
+//	DESCRIPTION:
+/**
+Get the specified brake control configuration. This feature requires a
+ClearPath-SC system.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[in] brakeNum Brake number. The first brake is zero.
+\param[out] pBrakeVal Operational state of the brake.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have returned the brake override.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_BADARG brakeNum or pBrakeVal invalid
+*/
+MN_EXPORT cnErrCode MN_DECL infcBrakeControlGet(
+	netaddr cNum,
+	size_t brakeNum,
+	BrakeControls *pBrakeVal)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	if (brakeNum >= mnNetInvRecords::MAX_BRAKES || !pBrakeVal)
+		return MN_ERR_BADARG;
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB)
+		return MN_ERR_BADARG;
+
+	*pBrakeVal = SysInventory[cNum].autoBrake[brakeNum].brakeMode;
+
+	return MN_OK;
+
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcAutoBrakeSet
+//
+//	DESCRIPTION:
+/**
+Link the disable state of a node with a given brake.
+
+\param[in] cNum Channel number. The first channel is zero.
+\param[in] brakeNum Brake number. The first brake is zero.
+\param[in] brakeInfo The node to associate and if the feature is active.
+
+\return #cnErrCode; Various Possible Return Values
+- MN_OK We have set the auto brake.
+- MN_ERR_DEV_ADDR cNum out of range
+- MN_ERR_PARAM_RANGE brakeNum or pBrakeInfo invalid
+*/
+MN_EXPORT cnErrCode MN_DECL infcAutoBrakeSet(
+	netaddr cNum,
+	size_t brakeNum,
+	nodebool enabled,
+	multiaddr theMultiAddr)
+{
+	// Insure boolean is converted to C-type
+	enabled = enabled ? TRUE : FALSE;
+	cnErrCode theErr = MN_OK;
+	// The address was not set
+	if (theMultiAddr == MN_UNSET_ADDR)
+		return MN_ERR_BADARG;
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	if (brakeNum >= mnNetInvRecords::MAX_BRAKES)
+		return MN_ERR_PARAM_RANGE;
+
+	if (enabled && cNum != NET_NUM(theMultiAddr))
+		return MN_ERR_BADARG;
+
+	// This feature requires ClearPath-SC network
+	if (SysInventory[cNum].PhysPortSpecifier.PortType != CPM_COMHUB)
+		return MN_ERR_BADARG;
+	// This feature only works on APP channel
+	if (SysInventory[cNum].AccessInfo[0].Fld.NetSource != MN_SRC_APP_NET)
+		return MN_ERR_APP_NET_ONLY;
+
+
+	#if TRACE_BRAKE
+	_RPT4(_CRT_WARN, "infcAutoBrakeSet: cNum=%d, brake=%d, enable=%d, addr=%d\n",
+		cNum, brakeNum, enabled, theMultiAddr);
+	#endif
+	// Prevent premature setup from past disabled states
+	SysInventory[cNum].attnInitializing++;
+	nodeaddr theAddr = NODE_ADDR(theMultiAddr);
+	attnReg &newSettings = SysInventory[cNum].drvrAttnMask[theAddr];
+	newSettings.cpm.GoingDisabled = enabled;
+	newSettings.cpm.Disabled = enabled;
+	newSettings.cpm.Enabled = enabled;
+	theErr = netSetDrvrAttnMask(theMultiAddr, &newSettings);
+	if (theErr != MN_OK) {
+		SysInventory[cNum].attnInitializing--;
+		return(theErr);
+	}
+	// See if we need to assert brake now
+	if (enabled) {
+		mnStatusReg statusNow;
+		theErr = netGetStatusRTReg(theMultiAddr, &statusNow);
+		if (theErr != MN_OK) {
+			SysInventory[cNum].attnInitializing--;
+			return(theErr);
+		}
+		theErr = infcBrakeSet(cNum, brakeNum,
+			!statusNow.Fld.LowAttn.DrvFld.Enabled);
+
+	}
+	else {
+		// Leave the brake control in the current state to avoid flickering
+		//theErr = infcBrakeSet(cNum, brakeNum, false);
+	}
+	// Wait for transmission of attentions to propagate. Ignore errors
+	// here, the 24V supply maybe not ready yet so we assume all OK.
+	infcSleep(50);
+	SysInventory[cNum].autoBrake[brakeNum].enabled = enabled;
+	SysInventory[cNum].autoBrake[brakeNum].relatedNode = theMultiAddr;
+	SysInventory[cNum].attnInitializing--;
+#if TRACE_BRAKE
+	if (theErr)
+		_RPT2(_CRT_WARN, "%.1f infcAutoBrakeSet return=0x%x.\n",
+				infcCoreTime(), theErr);
+#endif
+	return theErr;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcAutoBrakeGet
+//
+//	DESCRIPTION:
+/**
+	Link the disable state of a node with a given brake.
+
+	\param[in] cNum Channel number. The first channel is zero. This is the index
+	into the original port selections for \ref mnInitializeSystem.
+	\param[in] brakeNum Brake number. The first brake is zero.
+	\param[out] pTheMultiAddr The node watched when the feature is active.
+
+	\return #cnErrCode; Various Possible Return Values
+	- MN_OK We have returned the brake override.
+	- MN_ERR_DEV_ADDR cNum out of range
+	- MN_ERR_PARAM_RANGE brakeNum invalid
+	- MN_ERR_BADARG pEnabled or pTheMultiAddr invalid
+*/
+MN_EXPORT cnErrCode MN_DECL infcAutoBrakeGet(
+			netaddr cNum,
+			size_t brakeNum,
+			nodebool *pEnabled,
+			multiaddr *pTheMultiAddr)
+{
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	if (brakeNum >= mnNetInvRecords::MAX_BRAKES)
+		return MN_ERR_PARAM_RANGE;
+	if (!pEnabled || !pTheMultiAddr)
+		return MN_ERR_BADARG;
+
+	*pEnabled = SysInventory[cNum].autoBrake[brakeNum].enabled;
+	*pTheMultiAddr = SysInventory[cNum].autoBrake[brakeNum].relatedNode;
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcShutdownInfoSet
+//
+//	DESCRIPTION:
+/**
+	Register the node at \a theMultiAddr to cause a group shutdown if the 
+	Status Event condition in the \a pTheInfo condition is detected and
+	the feature is enabled.
+
+	\param[in] theMultiAddr The node to include or exclude from the group
+			   shutdown feature.
+	\param[in] pTheInfo Pointer to #ShutdownInfo buffer that defines how
+			   this node is part of the group shutdown feature. This includes
+			   the inclusion in the group state and what condition on this
+			   node is considered a shutdown condition.
+
+	\return #cnErrCode; Various Possible Return Values
+	- MN_OK The feature is has been setup properly.
+	- MN_ERR_DEV_ADDR theMultiAddr is illegal or out of range
+*/
+MN_EXPORT cnErrCode MN_DECL infcShutdownInfoSet(
+			multiaddr theMultiAddr,
+			const ShutdownInfo *pTheInfo)
+{
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theAddr = NODE_ADDR(theMultiAddr);
+	cnErrCode theErr= MN_OK;
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	if (theAddr > MN_API_ADDR_MASK)
+		return MN_ERR_DEV_ADDR;
+
+	mnNetInvRecords &inv = SysInventory[cNum];
+	ShutdownInfo &info = inv.GroupShutdownInfo[theAddr];
+
+	// Clear GroupShutdownRequest to allow any failure to reissue the nodestop
+	inv.GroupShutdownRequest = false;
+
+	// Adjust the polling list as necessary, watch out for VB 
+	// booleans for compares.
+#if defined(_MSC_VER)
+#pragma warning(push)
+#pragma warning(disable:4800)
+#endif
+	// Disable attns to eat historic event that maybe pending
+	inv.attnInitializing++;
+	// Set up the status event mask
+	theErr = netSetStatusEventMask(theMultiAddr, &pTheInfo->statusMask);
+	if (theErr == MN_OK) {
+		inv.drvrAttnMask[theAddr].cpm.StatusEvent = pTheInfo->enabled;
+		theErr = netSetDrvrAttnMask(theMultiAddr, &inv.drvrAttnMask[theAddr]);
+		// Copy in the new shutdown info and enable if required
+		if (theErr == MN_OK) {
+			info = *pTheInfo;
+		}
+	}
+	// Wait for attentions to transit net
+	infcSleep(100);
+	// Allow attention processing
+	inv.attnInitializing--;
+	return theErr;
+#if defined(_MSC_VER)
+#pragma warning(pop)
+#endif
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcShutdownInfoGet
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Group Shutdown feature at this node.
+
+	\param[in] theMultiAddr The node to include or exclude from the group
+			   shutdown feature.
+	\param[in] pTheInfo Pointer to #ShutdownInfo buffer that is updated with
+			   this node's current Group Shutdown State.
+
+	\return #cnErrCode; Various Possible Return Values
+	- MN_OK The feature is has been setup properly.
+	- MN_ERR_DEV_ADDR theMultiAddr is illegal or out of range
+*/
+MN_EXPORT cnErrCode MN_DECL infcShutdownInfoGet(
+			multiaddr theMultiAddr,
+			ShutdownInfo *pTheInfo)
+{
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theAddr = NODE_ADDR(theMultiAddr);
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	if (theAddr > MN_API_ADDR_MASK)
+		return MN_ERR_DEV_ADDR;
+
+	mnNetInvRecords &inv = SysInventory[cNum];
+	*pTheInfo = inv.GroupShutdownInfo[theAddr];
+	return MN_OK;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcShutdownInitiate
+//
+//	DESCRIPTION:
+/**
+	Trigger a Group Shutdown to occur via API call on the given channel.
+
+	\param[in] cNum Channel number. The first channel is zero.
+
+	\return #cnErrCode; Various Possible Return Values
+	- MN_OK The shutdown event was triggered.
+	- MN_ERR_DEV_ADDR cNum is illegal or out of range
+*/
+MN_EXPORT cnErrCode MN_DECL infcShutdownInitiate(
+			netaddr cNum)
+{
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+	
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	
+	if (!pNCS)
+		return MN_ERR_DEV_ADDR;
+
+	SysInventory[cNum].GroupShutdownRequest = true;
+	pNCS->GroupShutdownEvent.SetEvent();
+
+	return MN_OK;
+}
+// cond CPM_CLIB
+/// \endcond																   *
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::mnNetInvRecords constructor
+/// \cond INTERNAL_DOC
+//
+//	DESCRIPTION:
+/**
+	Construct the network inventory records
+*/
+mnNetInvRecords::mnNetInvRecords() {
+	//_RPT1(_CRT_WARN, "%.1f creating mnNetInvRecords(SysInventory)\n", infcCoreTime());
+	for (size_t i=0; i<MN_API_MAX_NODES; i++) {
+		pNodes[i] = (sFnd::INode *)NULL;
+		AccessInfo[i].bits = 0;
+		attnCleanupMask[i] = 0xFFFFFF;
+	}
+	pNCS = NULL;
+	pPortCls = (sFnd::IPort *)NULL;
+	brake0Saved = brake1Saved = true;
+	// Initialize with serial port closed
+	clearNodes(false);
+	Initializing = 0;
+	NumCmdsInRing = N_CMDS_IN_RING;
+	AutoDiscoveryEnable = true;
+	KeepAlivePollEnable = true;
+	KeepAlivePollRestoreState = true;
+	GroupShutdownRequest = false;
+	attnInitializing = 0;
+	OpenState = UNKNOWN;
+
+	NetDiagLastResult = MN_OK;
+	TraceArmed = TRUE;						// Create dump on next error
+	NetDiagBlock = FALSE;
+	OfflineRootErr = MN_OK;
+	OfflineErrNode = MN_UNSET_ADDR;
+	TraceActive = TRUE;
+	TraceActiveReq = TRUE;
+	TraceCount = 0;							// No traces yet
+	sendSerNum = respSerNum = 0;			// Start counting from 0
+	txTraceIndx = rxTraceIndx = 0;
+	txTraces = NULL;
+	rxTraces = NULL;
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::mnNetInvRecords destructor
+//
+//	DESCRIPTION:
+/**
+	Construct the network inventory records
+*/
+mnNetInvRecords::~mnNetInvRecords() {
+	//_RPT1(_CRT_WARN, "%.1f deleting mnNetInvRecords\n", infcCoreTime());
+	if (txTraces) delete[] txTraces;
+	if (rxTraces) delete[] rxTraces;
+	txTraces = NULL;
+	rxTraces = NULL;
+	clearNodes(true);
+	delete pPortCls;
+	pPortCls = NULL;
+	delete pNCS;
+	pNCS = NULL;
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::setupBrakeState
+//
+//	DESCRIPTION:
+/**
+Set brake outputs based on net type and node states.
+*/
+void mnNetInvRecords::setupBrakes()
+{
+	// Return if we don't have brake or can't control one.
+	if (!pNCS || !pNCS->pSerialPort) return;
+	if (!pNCS->pSerialPort->IsOpen()) return;
+	if (AccessInfo[0].Fld.NetSource != MN_SRC_APP_NET) return;
+	for (size_t i = 0; i < MAX_BRAKES; i++) {
+		// Run ignoring success/failure
+		infcAutoBrakeSet(pNCS->cNum, i, autoBrake[i].enabled, autoBrake[i].relatedNode);
+	}
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::OpenStateNext
+//
+//	DESCRIPTION:
+/**
+	Change the ValidState and record prior state.
+*/
+void mnNetInvRecords::OpenStateNext(openStates next)
+{
+#if TRACE_CALLBACK
+	_RPT2(_CRT_WARN, "%.1f mnNetInvRecords.OpenStateNext=%d\n", infcCoreTime(), next);
+#endif
+	//if (next == ONLINE)
+	//	_RPT0(_CRT_WARN, "ding\n");
+	if (next != OpenState) {
+		OpenStateLast = OpenState;
+		OpenState = next;
+	}
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInvRecords::clearNodes
+//
+//	DESCRIPTION:
+/**
+	Clear node information from this channel.
+*/
+void mnNetInvRecords::clearNodes(bool portIsClosed) 
+{
+	InventoryNow.NumOfNodes = 0;
+	InventoryNow.mnDrvInfo.count = 0;
+	InventoryNow.mnClearPathInfo.count = 0;
+	InventoryNow.mnCpScInfo.count = 0;
+	// Notify the nodes that they have went away
+	for (size_t i = 0; i<MN_API_MAX_NODES; i++) {
+		if (pNodes[i])
+			pNodes[i]->Refresh();
+	}
+	if (portIsClosed) {
+		OpenStateNext(CLOSED);
+	}
+	else {
+		OpenStateNext(OPENED_SEARCHING);
+	}
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		_mnPowerReg::_mnPowerReg
+//
+//	AUTHOR:
+//		Dave Sewhuk - 12/06/2016 17:24
+//
+//	DESCRIPTION:
+/**
+	Power Status register for ClearPath/Meridian nodes.
+*/
+_mnPowerReg::_mnPowerReg(const _mnPowerReg &src)
+{
+	bits = src.bits;
+}
+
+char * _mnPowerReg::StateStr(char *buffer, size_t size)
+{
+	size_t nowIndx, lastIndx, accumIndex;
+	nowIndx = fld.AcPhaseActive >= PWR_CNT ? PWR_CNT-1 : fld.AcPhaseActive;
+	lastIndx = fld.AcPhaseActiveLast >= PWR_CNT ? PWR_CNT - 1 : fld.AcPhaseActiveLast;
+	accumIndex = fld.AcPhaseActiveAccum >= PWR_CNT ? PWR_CNT - 1 : fld.AcPhaseActiveAccum;
+
+	// Format up a nicely formatted string
+	snprintf(buffer, size, "AC Phases Now: %s%s, Last AC Phases: %s%s, AC Phases since reset: %s\n"
+						   "Bus loss: %s; Phase loss: %s\n"
+						   "Under Operating Voltage: %s; logic supply detected: %s\n",
+		pwrTypes[nowIndx], fld.AcPhaseDir ? "(reverse)" : "", pwrTypes[lastIndx], fld.AcPhaseDirLast ? "(reverse)" : "", 
+		pwrTypes[accumIndex], fld.InBusLoss ? "yes" : "no", fld.InWiringError ? "yes" : "no",
+		fld.InUnderOperV ? "yes" : "no", fld.LogicPwrSupply ? "yes" : "no");
+	// Insure buffer is terminated
+	buffer[size - 1] = 0;
+	return (buffer);
+}
+// cond INTERNAL_DOC
+/// \endcond																   *
+//******************************************************************************
+
+/**
+	@}
+**/
+// End of ChanGrp
+//==============================================================================
+//	END OF FILE lnkAccessCommon.cpp
+//==============================================================================
+
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/meridianNet.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/meridianNet.cpp
new file mode 100644
index 000000000..8418c5529
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/meridianNet.cpp
@@ -0,0 +1,998 @@
+//******************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/meridianNet.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: meridianNet.cpp $
+//
+// DESCRIPTION
+/**
+	\file
+	\cond ISC_DOC
+	\brief System Setup Programming Interface Implementation
+
+	This module implements the system startup/shutdown and node inventory
+	features.
+
+	\defgroup SetupGrp System Setup Programming Interface
+	\brief Meridian Link Setup, Shutdown and Node Discovery Functions.
+	- Include "meridianHdrs.h" in your project to use these functions.
+
+	This group of functions sets up a system of Meridian nodes that may
+	span multiple serial ports. Once a system is initialized an
+	application can query for the quantities and addresses of specific
+	types of node in the system.
+
+	There are two groups for functions noted by the inclusion of \e
+	"Sys" or \e "Net" in their names. The \e "Sys" group of functions
+	targets all serial ports atomically. The \e "Net" group targets a
+	specific serial port channel alone.
+
+	On larger systems, breaking functionality up by individual serial
+	ports can lead to improved performance or the ability to adapt to
+	new machine features in a modular fashion. 	i.e. an additional
+	elevator sub-system is added and its motion and I/O is provided by
+	its communication link on a separate port. Alternatively within the
+	node count limitations, this could be appended to an existing
+	sub-system and the presence of additional nodes an indication of
+	this potentially optional feature.
+@{
+**/
+//		Provides the following main functions:
+//			mnInitializeSystem
+//			mnInitializeNets
+//				System Initialization
+//
+//			mnShutdown
+//				Orderly shutdown fucntion
+//
+//			mnRestartNet
+//				Restart either cold or warm of specified network and nodes.
+//
+// CREATION DATE:
+//		10/30/1998 09:55:47
+//		06/11/2009 10:52:00 - Renamed and cleaned out irrelavent CP stuff
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+// 																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//  NAME																       *
+// 	meridianNet.c headers
+//
+	#include "meridianHdrs.h"
+	#ifndef DOXYGEN_SHOULD_SKIP_THIS
+		#include "lnkAccessCommon.h"
+		#include "netCmdPrivate.h"
+		#include "pubSysCls.h"
+		#if (defined(_WIN32)||defined(_WIN64))
+			#include <crtdbg.h>
+			#include <winbase.h>
+		#else
+			#include <stdio.h>
+			#include <string.h>
+		#endif
+	#endif
+// 																	           *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//  NAME																       *
+// 	meridianNet.c constants
+//
+#if (defined(_WIN32)||defined(_WIN64))
+#define DBG_LOG(x) OutputDebugString(_T(x))
+#else
+#define DBG_LOG(x) fprintf(stderr, x)
+#endif
+// 																	           *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//  NAME																       *
+// 	meridianNet.c static
+
+/// \cond	INTERNAL_DOC
+
+	// Number of specified ports on last mnInitializeNets
+	unsigned SysPortCount = 0;
+	// System inventory of nodes types and addresses
+	mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+
+	// Variables for debug thread locking
+	CCEvent debugGate;
+	CCEvent debugThreadLockResponseGate;
+	bool inDebugging;
+	nodeulong lockedThreadID;
+	CCMutex threadLockMutex;
+
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//  NAME																       *
+//		mnInitializeProc
+//
+//  CREATION DATE
+//		Modified on 01/12/2001 18:27:40
+//		Modified 08/05/09 2:37:45 - from ControlPoint implementation/new diags
+//
+//	DESCRIPTION
+/**
+	Initialize the internal databases for port specified by \a pPortSpec.
+
+	/return MN_OK on success
+**/
+//	SYNOPSIS:
+cnErrCode MN_DECL mnInitializeProc(
+		nodebool resetNodes,		// TRUE if a nodes are to reset
+		nodebool singleNode,		// TRUE if we want to reset single node
+		multiaddr addr,				// Net/Node to reset
+		const portSpec *pPortSpec,	// Port information
+		mnNetInvRecords *initInfo)	// Ptr to information return
+
+{
+	cnErrCode lastErr=MN_OK, initErr=MN_OK, startErr, netBreakErr = MN_OK;
+	cnErrCode resetErr=MN_OK;
+	netaddr cNum = NET_NUM(addr);	// Controller number
+	nodebool foundNetworkNodes;
+
+	nodebool diagsOff;
+
+	// Bounds check controller destination
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	// If controller is open and auto-discover running we return
+	// our normal "still looking" case.
+	if (infcOnline(cNum) && infcAutoDiscoverRunning(cNum) && !resetNodes)
+		return(MN_ERR_NO_NET_CONNECTIVITY);
+
+	//_RPT3(_CRT_WARN, "%.1f mnInitializeProc(%d) reset=%d\n",
+	//				 infcCoreTime(), cNum, resetNodes);
+	infcFireNetEvent(cNum, NODES_RESETTING);
+	infcSetInitializeMode(cNum, TRUE, MN_OK);
+
+	// Halt the offline recovery tickler if running
+	infcHaltAutoNetDiscovery(cNum);
+
+	// Reset the inventory count and invalidate the inventory records
+	mnNetInvRecords &theNet = SysInventory[cNum];
+	// Create our port class for the location if we can
+	switch (pPortSpec->PortType) {
+	case CPM_COMHUB:
+	case GENERIC_SERIAL:
+		if (theNet.pPortCls)
+			theNet.pPortCls->NetNumber(cNum);
+		break;
+	case MERIDIAN_CONMOD:
+		break;
+	default:
+		_RPT3(_CRT_WARN,"%.1f mnInitializeProc(%d) no port class for this type %d\n",
+						 infcCoreTime(), cNum, pPortSpec->PortType);
+	}
+	// Assume port is still open at this point, stop controller will 
+	// definitively set this.
+	theNet.clearNodes(false);
+	int16 stackIn = theNet.Initializing;
+	startErr = infcStopController(cNum);
+	if (startErr == MN_OK) {
+		startErr = infcStartController(cNum);
+	}
+	// We are always one away from here
+	theNet.Initializing = stackIn;
+		
+	// Reset the global stop setup to the default state
+	for (size_t i=0; i < MN_API_MAX_NODES; i++) {
+		ShutdownInfo &sInfo = theNet.GroupShutdownInfo[NODE_ADDR(i)];
+		sInfo.enabled = true;
+		sInfo.statusMask.clear();
+		//sInfo.theStopType.bits = 0;
+		sInfo.theStopType.cpm.MotionAction = MG_STOP_STYLE_RAMP;
+		sInfo.theStopType.cpm.Disable = true;
+		sInfo.theStopType.cpm.MotionLock = true;
+	}
+	// Serial Port startup OK?
+	if (startErr == MN_OK) {
+
+		// Reset all the nodes once	if desired
+		if (resetNodes && initErr == MN_OK) {
+			// Start error will reflect reset failure
+			resetErr = netReset(addr, singleNode ? FALSE : TRUE);
+			if (resetErr != MN_OK) {
+				infcErrInfo errInfo;
+				_RPT3(_CRT_WARN,"%.1f mnInitializeProc(%d) reset failed code 0x%X\n",
+								 infcCoreTime(), cNum, startErr);
+				// Convert code to a more specific one and send failure
+				// back to application.
+				resetErr = MN_ERR_RESET_FAILED;
+				errInfo.cNum = cNum;
+				errInfo.errCode = resetErr;
+				errInfo.node = MN_API_UNKNOWN_ADDR;
+				// Force a message back to UI or application
+				infcFireErrCallback(&errInfo, true);
+			}
+			// Insure failed reset gets net @ same rate
+			lastErr = infcResetNetRate(cNum);
+		}
+		// Let stuff settle out
+		infcSleep(100);
+		// Kill any data that trickled in
+		infcFlush(cNum);
+		// Fire up the nodes and note the inventory count
+		theNet.InventoryNow.NumOfNodes = 0;			// Start net @ 0
+		initErr = netSetAddress(cNum, &theNet.InventoryNow.NumOfNodes);
+		// Set boolean to reflect the basic presence of nodes
+		if (initErr == MN_OK) {
+			foundNetworkNodes = theNet.InventoryNow.NumOfNodes >= 1;
+			// Set the network rate to requested rate
+			initErr = infcSetNetRate(cNum, pPortSpec->PortRate);
+			if (initErr != MN_OK) {
+				// Unwind init stack and report error, too serious to run
+				infcErrInfo errInfo;
+				errInfo.cNum = cNum;
+				errInfo.errCode = initErr;
+				errInfo.node = MN_API_UNKNOWN_ADDR;
+				infcSetInitializeMode(cNum, FALSE, initErr);
+				// Force a message back to UI or application
+				infcFireErrCallback(&errInfo, true);
+				return(initErr);
+			}
+		}
+		else {
+			foundNetworkNodes = FALSE;
+		}
+
+		// Get system diagnostic blocker state
+		netBreakErr = infcGetDiagBlock(cNum, &diagsOff);
+		// If diagnostics are not blocked and we did not have
+		// a successful "set address" bid, run diagnostics to see if
+		// we can determine the problem.
+		if (!diagsOff && initErr != MN_OK)  {
+			// Run the network diagnostics to detect broken ring
+			initErr = netBreakErr
+				= infcBrokenRingDiag(cNum, foundNetworkNodes,
+										  theNet.InventoryNow.NumOfNodes);
+		}
+		else {
+			netBreakErr = MN_OK;		// Assume OK if not run
+		}
+
+		// If we failed the reset and there are net problems, return them
+		// and create a dump file
+		if (IsNetBreakErr(netBreakErr)) {
+			infcTraceDumpNext(cNum);
+			infcSetInitializeMode(cNum, FALSE, netBreakErr);
+			//infcFireNetEvent(cNum, NODES_ONLINE_NO_TEST);
+			return(netBreakErr);
+		}
+		// ---- END - Diagnostics: Run if node initialize not successful ----
+
+
+		// We got some nodes, enumerate them
+		if (initErr == MN_OK && foundNetworkNodes) {
+			startErr = netEnumerate(cNum);
+		}
+		else
+			lastErr = startErr = initErr;
+
+		// Convert node command type errors into nothing bad. The node exists
+		// and will talk.
+		if (startErr >= MN_ERR_CMD_INTERNAL && startErr <= MN_ERR_CMD_ERR_END)
+			startErr = MN_OK;
+
+		switch(startErr) {
+			case MN_OK:
+				// Net break issues drive return error code
+				lastErr = netBreakErr;
+				// If otherwise OK but reset failed, note it
+				if (lastErr == MN_OK && resetErr != MN_OK)
+					lastErr = resetErr;
+				infcFlushProc(cNum);
+				// If problems, start the search to wait for it repair
+				infcSetInitializeMode(cNum, FALSE, lastErr);
+				if (lastErr != MN_OK)
+					// Start looking for network to re-appear
+					infcStartAutoNetDiscovery(cNum, lastErr);
+				break;
+			case MN_ERR_NO_NET_CONNECTIVITY:
+			case MN_ERR_RESP_TIMEOUT:
+				// Could not detect anything, assume we don't know
+				theNet.OpenStateNext(OPENED_SEARCHING);
+				if (initInfo != NULL) {
+					*initInfo = SysInventory[cNum];
+				}
+				infcSetInitializeMode(cNum, FALSE, lastErr);
+				// Start looking for network to re-appear
+				infcStartAutoNetDiscovery(cNum, lastErr);
+				return(lastErr);
+			default:
+				_RPT1(_CRT_WARN,
+					"mnInitializeProc: netEnumerate failed code=0x%0X\n",
+					lastErr);
+				// Do final cleanup
+				infcSetInitializeMode(cNum, FALSE, lastErr);
+				break;
+		}
+	}
+
+	else {
+		lastErr = startErr;
+		// We are done initialization now, let auto-discover run
+		infcSetInitializeMode(cNum, FALSE, lastErr);
+	}
+	// NOTE: infcSetInitializeMode(FALSE) should all have been done
+
+	// Last error reflects the final initialization outcome
+	// Return whether this data is OK
+	if (!((lastErr == MN_OK) || (lastErr == MN_ERR_TEST_INCOMPLETE))) 
+		theNet.OpenStateNext(OPENED_SEARCHING);
+
+	if (theNet.OpenState == OPENED_ONLINE) {
+		infcUpdateInventory(cNum, &SysInventory[cNum]);
+	}
+	
+//#ifdef DUMP_INIT
+//	infcTraceDump(cNum, L"#mn_init.log");
+//#endif
+	// If they requested inventory copy, give them it
+	if (initInfo != NULL) {
+		*initInfo = SysInventory[cNum];
+	}
+	// Something wrong enroute, create dump
+	if (theNet.OpenState != OPENED_ONLINE) {
+		infcTraceDumpNext(cNum);
+	}
+
+	return(lastErr);
+}
+// 																	           *
+//******************************************************************************
+
+/// \endcond
+
+
+//||||||||||||||||||||||||||||||||||||
+// MULTINET INITIALIZATION INTERFACE
+//||||||||||||||||||||||||||||||||||||
+
+
+//******************************************************************************
+//  NAME																       *
+//		mnInitializeNets
+//
+//	DESCRIPTION:
+/**
+	This function initializes the Meridian system and is used to
+	start communications on the channel(s).
+
+	\deprecated	This function has been replaced with #mnInitializeSystem
+	to allow initialization of systems with a combination of Meridian 
+	and ClearPath-SC nodes.
+
+	\param[in] resetNodes
+		- True = Reset all individual nodes before establishing channel
+		- False = Just establish communication
+	\param[in] netCount
+		Number of communication channels to initialize (e.g. 1..2)
+	\param[in]	controllers[]
+		Ptr to controller array of \a netCount elements. Each item in the array
+		identifies the PortRate (speed) and the PortNumber (COM #) that
+		the function will try to initialize.
+
+	\return
+		#cnErrCode; MN_OK if all channels and nodes are ready for
+		interactions.  Some errors return bit-mapped fields to signal the
+		channels that are broken.
+
+	\see \ref SFinitPage
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnInitializeNets(
+		nodebool resetNodes,
+		nodeulong netCount,
+		const controllerSpec controllers[])
+{
+	portSpec converted[NET_CONTROLLER_MAX];
+	// Bounds check the table
+	if (netCount>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+	for (size_t cNum = 0; cNum < netCount; cNum++) {
+		converted[cNum] = controllers[cNum];
+	}
+	return (mnInitializeSystem(resetNodes, netCount, converted));
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//  NAME																       *
+//		mnInitializeSystem
+//
+//	DESCRIPTION:
+/**
+	This function initializes a system consisting of Meridian and ClearPath-SC 
+	nodes. The function arguments describe the serial ports to utilize, the
+	type of nodes attached and the desired communications speed.
+
+	\param[in] resetNodes
+		- True = Reset all individual nodes before establishing channel
+		- False = Just establish communication
+	\param[in] netCount
+		Number of communication channels to initialize (e.g. 1..2)
+	\param[in]	controllers[]
+		Ptr to controller array of \a netCount elements. Each item in the array
+		identifies the PortRate (speed), the PortNumber (COM #) and
+		the types of nodes to expect on that port. 
+
+	\return
+		#cnErrCode; MN_OK if all channels and nodes are ready for
+		interactions.  Some errors return bit-mapped fields to signal the
+		channels that are broken or the serial ports do not exist.
+
+	\see \ref SFinitPage
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnInitializeSystem(
+		nodebool resetNodes,
+		nodeulong netCount,
+		const portSpec controllers[])
+{
+	// Overall initializing state, 0==System ONLINE, else
+	// initialization still in progress.
+	extern int InitializingGlobal;
+	unsigned cNum, initFailures, portFailures, baudFailures;
+	cnErrCode initErr[NET_CONTROLLER_MAX], theErr;
+
+	//DBG_LOG("mnInitializeSystem\n");
+	// Bounds check the table
+	if (netCount>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	// Insure past failed initializations are cleared and all ports closed
+	for (cNum=0; cNum<NET_CONTROLLER_MAX; cNum++) {
+		theErr = infcStopController(cNum);
+		#ifdef _DEBUG
+			if (theErr != MN_OK) {
+				_RPT3(_CRT_WARN, "%.1f mnInitializeSystem stopping error @%d, code=0x%0X\n",
+					  infcCoreTime(), cNum, theErr);
+			}
+		#endif
+		SysInventory[cNum].clearNodes(true);
+		SysInventory[cNum].Initializing = 0;
+	}
+	// Block error callbacks
+	InitializingGlobal = 1;
+
+	// Start with no ports
+	SysPortCount = 0;
+	baudFailures = initFailures = portFailures = 0;
+	// Initialize them in turn
+	for (netaddr i=0 ; i<netCount ; i++ ) {
+		// Defer "online/offline/error" events until completed
+		infcSetInitializeMode(i, TRUE, MN_OK);
+		// Save our port and speed information for later
+		infcSetPortSpecifier(i, &controllers[i]);
+		// Perform net enumeration and node class initialization if possible
+		initErr[i] = mnInitializeProc(resetNodes, false, MULTI_ADDR(i, 0),
+									  &controllers[i], NULL);
+		// How did this initialization go?
+		switch (initErr[i]) {
+			case MN_OK:
+				// Great, allow us to go online immediately
+				SysInventory[i].OpenStateNext(OPENED_ONLINE);
+				break;
+			case MN_ERR_PORT_PROBLEM:
+				// Record as specific issue, serial port not found
+				portFailures |= (1<<i);
+				SysInventory[i].OpenStateNext(PORT_UNAVAILABLE);
+				break;
+			case MN_ERR_BAUD_NOT_SUPPORTED:
+				// Record as specific issue, serial port baud rate not supported
+				baudFailures |= (1<<i);
+				SysInventory[i].OpenStateNext(PORT_UNAVAILABLE);
+				break;
+			default:
+				// Record as generic sort of failure, port probably OK, nodes
+				// not detected yet.
+				initFailures |= (1<<i);
+				SysInventory[i].OpenStateNext(OPENED_SEARCHING);
+				break;
+
+		}
+		// Record our requested configuration count
+		SysPortCount++;
+	}
+	// Return bit oriented failure code based on initialization results
+	if (portFailures) {
+		// Return failure source(s)
+		theErr = (cnErrCode)(MN_ERR_PORT_FAILED_BASE + portFailures);
+	}
+	else if (baudFailures) {
+		// Return failure source(s)
+		theErr = (cnErrCode)(MN_ERR_BAUD_FAILED_BASE + baudFailures);
+	}
+	else if (initFailures) {
+		// Return failure source(s)
+		theErr = (cnErrCode)(MN_ERR_INIT_FAILED_BASE + initFailures);
+	}
+	else
+		theErr = MN_OK;
+
+	// Allow global operations to occur
+	InitializingGlobal = 0;
+
+	// Allow the online/offline/error events now
+	for (netaddr i=0 ; i<netCount ; i++ ) {
+		// Record the last error in case the port isn't online
+		SysInventory[i].OfflineRootErr = initErr[i];
+		// Allow successful ports to go online
+		infcSetInitializeMode(i, FALSE, initErr[i]);
+	}
+	// Make sure background poller (re)starts
+	if (theErr == MN_OK) {
+		//DBG_LOG("mnInitializeSystem OK\n");
+		for (netaddr i=0 ; i<netCount ; i++ ) {
+			// Start keep alive polling if enabled
+			if (SysInventory[i].KeepAlivePollEnable
+			&& SysInventory[i].OpenState == OPENED_ONLINE) {
+				infcBackgroundPollControl(i, TRUE);
+			}
+		}
+	}
+	#ifdef _DEBUG
+	else { 
+		// Start auto-discovery threads on the failed ports
+		for (netaddr i = 0; i < netCount; i++) {
+			if (SysInventory[i].OpenState == OPENED_SEARCHING)
+				infcStartAutoNetDiscovery(i, initErr[i]);
+		}
+		_RPT1(_CRT_WARN, "mnInitializeSystem err=0x%X\n", theErr);
+	}
+	infcHeapCheck("mnInitializeSystem");
+	#endif
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnRestartNet
+//
+//	DESCRIPTION:
+/**
+	Restart the previously-initialized network.
+
+	\param[in] cNum Channel number to restart. The first channel is zero.
+	\param[in] restartNodes
+	- True = Reset all individual nodes
+	- False = Just establish communication
+
+	\return
+		#cnErrCode; MN_OK if system restarted without problems.
+**/
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnRestartNet(
+	netaddr cNum,
+	nodebool restartNodes)
+{
+	cnErrCode theErr;
+	portSpec comPortSpec;
+
+	DBG_LOG("mnRestartNet\n");
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+	// Prevent interference
+	nodebool pollIn = SysInventory[cNum].KeepAlivePollEnable;
+	infcBackgroundPollControl(cNum, false);
+	// Signal online->offline transition
+	infcSetInitializeMode(cNum, TRUE, MN_OK);
+	// Rebuild the network
+	theErr = infcGetPortSpecifier(cNum, &comPortSpec);
+	if (theErr ==  MN_OK) {
+		theErr = mnInitializeProc(restartNodes, false, MULTI_ADDR(cNum, 0),
+								  &comPortSpec, NULL);
+	}
+	// Signal offline->online or error condition as a result of restart
+	infcSetInitializeMode(cNum, FALSE, theErr);
+	// Restore background keep alive polling.
+	SysInventory[cNum].KeepAlivePollEnable = pollIn;
+	if (theErr == MN_OK && SysInventory[cNum].KeepAlivePollEnable 
+	&& SysInventory[cNum].Initializing == 0) {
+		cnErrCode pollErr = infcBackgroundPollControl(cNum, true);
+		theErr = (theErr == MN_OK) ? pollErr : theErr; 
+	}
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnRestartNode
+//
+//	DESCRIPTION:
+/**
+	Restart the specified node.
+
+	\param[in] addr multi-net address of node to restart.
+
+	\return
+		#cnErrCode; MN_OK if node started without problems.
+
+	\see \ref MULTI_ADDR for macros to build specific node addresses
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnRestartNode(
+	multiaddr addr)
+{
+	cnErrCode theErr;
+	portSpec comPortSpec;
+	nodeaddr cNum = NET_NUM(addr);
+
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+	// Signal online->offline transition
+	infcSetInitializeMode(cNum, TRUE, MN_OK);
+	// Rebuild the network
+	theErr = infcGetPortSpecifier(cNum, &comPortSpec);
+	if (theErr ==  MN_OK) {
+		theErr = mnInitializeProc(true, true, addr,
+								  &comPortSpec, NULL);
+		// Signal offline->online or error condition as a result of restart
+		infcSetInitializeMode(cNum, FALSE, theErr);
+	}
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+/// \cond INTERNAL_DOC
+//******************************************************************************
+//	NAME																	   *
+//		mnGetClassItem
+//
+//	DESCRIPTION:
+/**
+	Return a pointer to the node class record for this channel.
+
+	\param[in] cNum Channel number to restart. The first channel is zero.
+	\param[in] deviceType device type
+
+	\return mnClassInfo Ptr to the class information record for
+			the specified node type.  NULL is returned if no devices of this
+			type can be present.
+**/
+//	SYNOPSIS:
+mnClassInfo *mnGetClassItem(
+	netaddr cNum,
+	nodeIDs deviceType)
+{
+	switch(deviceType)  {
+		case NODEID_MD:
+			return &SysInventory[cNum].InventoryNow.mnDrvInfo;
+		case NODEID_CP:
+			return &SysInventory[cNum].InventoryNow.mnClearPathInfo;
+		case NODEID_CS:
+			return &SysInventory[cNum].InventoryNow.mnCpScInfo;
+		default:
+			return(NULL);
+	}
+}
+//																			   *
+//******************************************************************************
+/// \endcond
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInventoryCount
+//
+//	DESCRIPTION:
+/**
+	Return the inventory count of the specified device type on the
+	specified channel.
+
+	\param[in] cNum Zero-based channel index.
+	\param[in] deviceType Device type to find.
+	\param[out] pCount When return is MN_OK, the user's \a pCount is
+			    updated with the count of these \a deviceTypes present on
+				this channel.
+	\return #cnErrCode; If MN_OK returned, \a pCount was updated with count of
+				\a deviceTypes found on this channel.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnNetInventoryCount(
+	netaddr cNum,
+	nodeIDs deviceType,
+	nodeulong *pCount)
+{
+	mnClassInfo *ip;
+
+	if (pCount == NULL)
+		return(MN_ERR_VALUE);
+	// Reset user's counter
+	*pCount = 0;
+	// Accumulate the counts
+	ip = mnGetClassItem(cNum, deviceType);
+	if (ip == NULL)
+		return(MN_ERR_VALUE);
+	*pCount = ip->count;
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnNetInventoryRecord
+//
+//	DESCRIPTION:
+/**
+	Get the address list for the specified node type on the specified channel.
+	The \a devices list is filled up to \a maxDevices.	This is useful for
+	identifying the locations of certain types of nodes on a specific channel.
+
+	Use \c mnNetInventoryCount to aid in memory allocation for the \a
+	devices argument.
+
+	\param[in] cNum Zero-based channel index.
+	\param[in] deviceType Device type to find.
+	\param[in] maxDevices Maximum number of devices in list.
+	\param[out] devices Ptr to result list, filled in on successful completion.
+
+	\return #cnErrCode; MN_OK if \a devices was updated with locations of \a
+	deviceTypes on this channel.
+
+	\see mnNetInventoryCount
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnNetInventoryRecord(
+	netaddr cNum,
+	nodeIDs deviceType,
+	nodeulong maxDevices,
+	multiaddr devices[])
+{
+	mnClassInfo *ip;
+	// Make sure we have a place to write!
+	if (devices == NULL)
+		return(MN_ERR_VALUE);
+	// Scan through the inventory records picking up items
+
+	ip = mnGetClassItem(cNum, deviceType);
+	if (ip == NULL)
+		return(MN_ERR_VALUE);
+	if (maxDevices<ip->count)
+		return(MN_ERR_VALUE);
+	// Copy addresses over
+	memcpy(devices, ip->node, ip->count*sizeof(multiaddr));
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																       	   *
+//		mnNetNodeCount
+//
+// DESCRIPTION:
+/**
+	Return the number of nodes on the network.
+
+	\param[in] cNum Zero-based channel index.
+	\param[out] pCount Pointer to the count location.
+
+	\return #cnErrCode; MN_OK if \a pCount was updated.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnNetNodeCount(
+	netaddr cNum,
+	nodeulong *pCount)
+{
+	if (pCount == NULL || cNum > SysPortCount)
+		return(MN_ERR_VALUE);
+	*pCount= SysInventory[cNum].InventoryNow.NumOfNodes;
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnSysInventoryCount
+//
+//	DESCRIPTION:
+/**
+	Return the system inventory count for this type of device.
+
+	\param[in] deviceType Device type to find.
+	\param[out] pCount Ptr to return count.
+
+	\return #cnErrCode; MN_OK if \a pCount was updated.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnSysInventoryCount(
+	nodeIDs deviceType,
+	nodeulong *pCount)		// Ptr to result
+{
+	unsigned i;
+	mnClassInfo *ip;
+
+	// Prevent crash
+	if (!pCount)
+		return(MN_ERR_VALUE);
+	// Reset user's count
+	*pCount = 0;
+	for (i=0; i<SysPortCount; i++) {
+		// Accumulate the counts
+		ip = mnGetClassItem(i, deviceType);
+		if (ip == NULL)
+			return(MN_ERR_VALUE);
+		*pCount += ip->count;
+	}
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnSysInventoryRecord
+//
+//	DESCRIPTION:
+/**
+	Get the address list for all the specified node types in the system. The
+	\a devices list is filled up to \a maxDevices.  This is useful for
+	identifying the locations of certain types of nodes in the system.
+
+	Use \c mnSysInventoryCount to aid in memory allocation for the \a
+	devices argument.
+
+	\param[in] deviceType Device type to find.
+	\param[in] maxDevices Maximum number of devices in list
+	\param[out] devices Ptr to user's list of addresses in the system of this
+		   type, filled in up to \a maxDevices.
+
+	\return #cnErrCode; MN_OK if \a devices was updated with locations
+	of \a deviceTypes.
+
+	\see mnSysInventoryCount
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnSysInventoryRecord(
+	nodeIDs deviceType,			// Which device type
+	nodeulong maxDevices,	// Maximum number of devices in list
+	multiaddr devices[])		// Ptr to result list
+{
+	unsigned i;
+	mnClassInfo *ip;
+	netaddr cNum;
+	// Make sure we have a place to write!
+	if (devices == NULL)
+		return(MN_ERR_VALUE);
+	// Scan through the inventory records picking up items
+
+	for (i=0; i<SysPortCount; i++) {
+		// Get this class record for this net
+		cNum = i;
+		ip = mnGetClassItem(cNum, deviceType);
+		if (ip == NULL)
+			return(MN_ERR_VALUE);
+		if (maxDevices<ip->count)
+			return(MN_ERR_VALUE);
+		// Copy addresses over
+		memcpy(devices, ip->node, ip->count*sizeof(multiaddr));
+		// Move pointer down
+		devices+=ip->count;
+	}
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//  NAME																       *
+//		mnSysNodeCount
+//
+//  DESCRIPTION:
+/**
+	Return the count of all nodes detected in the system.
+
+	\param[out] pCount Ptr to returned count area.
+
+	\return #cnErrCode; MN_OK if \a pCount was updated with total system
+				node count.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnSysNodeCount(
+			nodeulong *pCount)		// Ptr to result area
+{
+	unsigned i;
+	nodeulong thisNetCnt;
+	cnErrCode theErr;
+
+	// Prevent crash on stupid
+	if (!pCount)
+		return (MN_ERR_VALUE);
+	// Start with no nodes
+	*pCount = 0;
+	for (i=0; i<SysPortCount; i++) {
+		if ((theErr = mnNetNodeCount(i, &thisNetCnt)) == MN_OK) {
+			*pCount += thisNetCnt;
+		}
+		else
+			return(theErr);
+	}
+	return(MN_OK);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+//	NAME																	   *
+//		mnShutdown
+//
+//	DESCRIPTION:
+/**
+	Shutdown the networks and release any resources.
+
+	\return #cnErrCode; MN_OK if system is shutdown and ports are released.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL mnShutdown(void)
+{
+	cnErrCode theErr, compositeErr = MN_OK;
+
+	//_RPT1(_CRT_WARN, "%.1f mnShutdown started\n", infcCoreTime());
+	for (netaddr i=0; i<NET_CONTROLLER_MAX; i++) {
+		if (infcOnline(i))
+			// Tell everyone to stop using us
+			infcFireNetEvent(i, NODES_STOP_NET_CONFIG);
+		// Test for NCS and insure complete shutdown if not in special mode
+		theErr = infcStopController(i);
+		if (theErr != MN_OK && compositeErr == MN_OK)
+			compositeErr = theErr;
+	}
+	SysPortCount = 0;
+	//_RPT1(_CRT_WARN, "%.1f mnShutdown done\n", infcCoreTime());
+	return(compositeErr);
+}
+//																			   *
+//******************************************************************************
+
+
+// End of Group: SetupGrp
+/// @}
+// cond ISC_DOC
+/// \endcond
+
+//==============================================================================
+//	END OF FILE meridianNet.c
+//==============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/netCmdAPI.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/netCmdAPI.cpp
new file mode 100644
index 000000000..21db03f3d
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/netCmdAPI.cpp
@@ -0,0 +1,5148 @@
+//******************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/netCmdAPI.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: netCmdAPI.cpp $
+//
+// DESCRIPTION:
+/**
+	\file
+	\brief 	Link Function Programming Interface Implementation
+	This module implements functions that act on all nodes or generically
+	access common features among all node types.
+
+	\defgroup LinkGrp Link Function Programming Interface
+	@{
+	\brief Link oriented feature functions. These act upon all nodes or
+	target nodes generically. Link oriented features such as, Trigger
+	and Stop, are accessed by functionality in the group of functions.
+	- Include "meridianHdrs.h" in your project to use these functions.
+
+	This module defines the common link command set and utilities that all
+	network devices will utilize in the programming interface. It
+	provides the utilities that:
+		- retrieve the generic device information
+		- set and retrieve parameters from devices in a generic sense.
+	@}
+**/
+//	All I/O is handled by linking to the transport layer module. That
+//	module provides the core functions of opening/closing communications
+//	to the network controller, provides base transfer of command
+//	information and responses and provides a hook to field an
+//	asynchronous request for service by the network controller.
+//
+// CREATION DATE:
+//		02/13/1998 12:22:30
+//
+// COPYRIGHT NOTICE:
+//		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification,
+//		or portion thereof merged into another program. A copy of the
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			   *
+//******************************************************************************
+
+/// \cond	INTERNAL_DOC
+
+//******************************************************************************
+// NAME																		   *
+// 	netCore.c headers
+//
+	#include "meridianHdrs.h"
+	#include "mnParamDefs.h"
+	#include "sFoundResource.h"
+	#include "lnkAccessCommon.h"
+	#include "netCmdPrivate.h"
+	#include "pubIscAPI.h"
+	#include "pubCpmAPI.h"
+	#include "iscRegs.h"
+	#include "pubSysCls.h"
+	#include "pubCpmCls.h"
+	#include "iniparser.h"
+#if defined(IMPL_NODE_CP)
+	#include "clearPathRegs.h"
+	#include "pubClearPathAPI.h"
+#endif
+	#include "dictionary.h"
+	#include "iniparser.h"
+	#include "cpmRegs.h"
+	#include "converterLib.h"
+	#include "pubMonPort.h"
+	#include "SerialEx.h"
+	#include <math.h>
+	#include <assert.h>
+	#include <time.h>
+	#if !(defined(_WIN32)||defined(_WIN64))
+		#include <string.h>
+		#include <stdio.h>
+		#include <stdlib.h>
+	#else
+	    #include <CRTDBG.H>
+		#include <stdio.h>
+		#include <io.h>
+		#include <fcntl.h>
+		#include <sys/stat.h>
+	#endif
+	// Fix up windows naming for VS8
+	#if defined(_WIN32)||defined(_WIN64)
+		#define access _access
+		#if defined(_MSC_VER) && _MSC_VER<=1800
+			#define snprintf sprintf_s
+		#endif
+		#define open _open
+		#define W_OK 2
+		#define R_OK 4
+	#endif
+
+	#ifdef __linux
+	#ifdef __LP64__
+		#define THREAD_RADIX "0x%lx"
+	#else
+		#define THREAD_RADIX "%d"
+	#endif
+	#else
+		#define THREAD_RADIX "0x%x"
+	#endif
+
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+// NAME																		   *
+// 	netCore.c global variables
+//
+	// Reference to channel and node information
+	extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+	// This is the master configuration file key list as enumerated by
+	// the ParameterNumbers enumeration. This is used to locate or store
+	// configuration parameters in configuration files.	This file
+	// is maintained by the ValuesLib.dll make file.
+	#include "valkeys.h"
+	#ifdef __QNX__
+	#pragma GCC diagnostic ignored "-Wunused-parameter"
+	#endif
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																		   *
+// 	netCore.c local variables
+//
+#define IOC_HZ_MIN			1.0							// Minimum frequency
+// Maximum allowable time(ms) difference between FC Out on a given node and
+// FC IN on the neighboring(lower address number) node
+#define NET_CHECKSUMS_BAD 	1
+#define NET_FRAGS_BAD 		1
+#define NET_STRAYS_BAD 		1
+#define NET_OVERRUN_BAD 	1
+
+//- - - - - - - - - - - - - - - - - - - -
+// TRACING/DEBUG SETUP
+//- - - - - - - - - - - - - - - - - - - -
+#ifdef _DEBUG
+#define T_ON TRUE
+#else
+#define T_ON FALSE
+#endif
+#define T_OFF FALSE
+#define TRACE_HIGH_LEVEL	T_OFF
+#define TRACE_SERIAL		T_ON
+#define TRACE_HEAP			T_OFF
+
+// The base level by node information
+mnNetDiagResults NetDiags[NET_CONTROLLER_MAX];
+
+// Configuration File Strings
+const char *CNFG_VER_KEY = "Chip Version";
+const char *CNFG_DATE_KEY = "File Written";
+const char *CNFG_MOD_VER_KEY = "Writer";
+const char *CNFG_SYS_VCS_KEY = "SysWriter";
+const char *CNFG_LOAD_MTR_RATIO = "LoadMtrRatio";
+// Motor file key for user description
+const char *CNFG_USER_DESC = "UserDesc";
+const char *CNFG_USERID = "UserID0";
+const char *MOTOR_SECTION = "Motor Info";
+const char *CNFG_PN = "PN";
+
+// Parameter location for the user description; define here so 
+// it's not exposed publicly
+const int CPM_P_USER_DESCR_BASE = 540;
+
+// Cracker for long form version strings
+typedef union _lvers {
+	nodeulong	bits;
+	struct {
+		unsigned build	: 16;
+		unsigned minor	: 8;
+		unsigned major	: 8;
+	} fld;
+} longVers;
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																		   *
+// 	netCore.c function prototypes
+//
+// Local Function Prototype
+// Convert a buffer area to a double based on the parameter information
+//cnErrCode coreBufToValue(
+//		const paramInfoLcl *info,	// Parameter information
+//		paramValue *bufValue);		// Effective value
+
+// Convert a double to a buffer area based on the parameter information
+void coreDoubleToBuf(
+		const paramInfoLcl *info, 	// Parameter information
+		packetbuf *buffer,			// Ptr to start of buffer
+		double newValue);			// Value to set
+
+double coreBufToDouble(
+	const paramInfoLcl *info,		// Information about this param
+	paramValue *bufValue);			// Effective value
+
+// Convert value in user units to base node value
+void toBaseUnit(
+		multiaddr theMultiAddr,		// Node address
+		appNodeParam paramNum,		// the parameter number
+		byNodeDB *nodeInfo,			// the node information
+		paramInfoLcl const *pFixedInfoDB,	// the fixed parameter info
+		paramBank *pBankInfo,		// the parameter bank
+		paramValue *userVal);		// user value in their unit
+
+// Convert base node value to a value in user specified units
+void fromBaseUnit(
+		multiaddr theMultiAddr,		// Node address
+		appNodeParam paramNum,		// the parameter number
+		byNodeDB *nodeInfo,			// the node information
+		paramInfoLcl const *pFixedInfoDB,	// the fixed parameter info
+		paramBank *pBankInfo,		// the parameter bank
+		paramValue *pNodeVal);		// node's base value
+
+cnErrCode coreBaseGetParameterLong(netaddr cNum, nodeaddr theNode,
+								  nodeparam paramNum, int *pVal);
+
+
+// Returns the firmware ID for this node
+cnErrCode netGetFirmwareID(
+		multiaddr theMultiAddr,		// Node address
+		size_t bufSizeMax,			// sizeof theID buffer
+		char *theID);
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		hexToDec
+//
+//	DESCRIPTION:
+///		Parse the string for hex chars and convert to decimal.
+///
+/// 	\param pDest Destination area of compatibility 18 octet buffer
+///		\param pSrc  Source of the copy
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+nodelong hexToDec(char *theStr)
+{
+	size_t theLen = strlen(theStr);
+	unsigned char *p = (unsigned char *)theStr
+		+ theLen - 1;
+	nodelong lVal = 0;
+	for (size_t i=0; i<theLen; i++) {
+		*p = toupper(*p);
+		if (*p>='0' && *p<='9')
+			lVal = lVal | ((*p-- - '0')<<(4*i));
+		else if(*p>='A' && *p<='F')
+			lVal = lVal | ((*p-- - 'A' + 10)<<(4*i));
+		else  {
+			p--;
+			//throw "Bad character";			// Skip this bad char
+			throwSystemError("Bad character");
+		}
+	}
+	return lVal;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		infcCopyPktToPkt18
+//
+//	DESCRIPTION:
+///		Copy a full packet buffer to truncated one.
+///
+/// 	\param pDest Destination area of compatibility 18 octet buffer
+///		\param pSrc  Source of the copy
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+static void infcCopyPktToPkt18(packetbuf18 *pDest, packetbuf *pSrc)
+{
+	pDest->bufferSize = pSrc->Byte.BufferSize < 18 ? pSrc->Byte.BufferSize : 18;
+	memcpy(&pDest->buffer[0], &pSrc->Byte.Buffer[0],
+		   pDest->bufferSize);
+}
+//																			   *
+//******************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		coreController
+//
+//	DESCRIPTION:
+//		Return the controller based on the node address. If the node address
+//		is between [0..31] the current controller is returned else the new
+//		algorithm
+//
+//	RETURNS:
+//		netaddr (controller target)
+//
+//	SYNOPSIS:
+netaddr coreController(multiaddr theMultiAddr)
+{
+	// Make sure they are not using old "currentController" form
+	assert(NET_NUM(theMultiAddr)<NET_CONTROLLER_MAX);
+	return(NET_NUM(theMultiAddr));
+}
+/****************************************************************************/
+
+
+
+
+//****************************************************************************
+//	NAME
+//		netEnumerate
+//
+//	DESCRIPTION:
+//		Bring nodes online/re-address and enumerate the inventory list.
+//
+//		SysInventory[cNum] is updated with the results
+//
+//	RETURNS:
+//		#cnErrCode: MN_OK if there is at least an NC
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netEnumerate(
+	netaddr cNum)				// Controller number
+{
+	cnErrCode theErr = MN_OK, lastErr = MN_OK;
+	nodeulong i;
+	nodeulong maxNode;
+	packetbuf theResp;
+	mnClassInfo *pClassInfo;
+	mnNetInvRecords &netInv = SysInventory[cNum];
+
+	// Get current controller
+	infcSetInitializeMode(cNum, TRUE, MN_OK);
+	infcFireNetEvent(cNum, NODES_SENDING);
+	// Clear our initial set of counts until we rediscover
+	netInv.clearNodes(false);
+
+	maxNode=0;
+	lastErr = netSetAddress(cNum, &maxNode);
+
+	// Assign nodes their addresses
+	netInv.InventoryNow.NumOfNodes = maxNode;
+	// Collect array of basic devices, if NC OK
+	if (theErr == MN_OK && lastErr == MN_OK) {
+		// Reset to user's desired speed for this if not already there
+		if (netInv.PhysPortSpecifier.PortRate != netInv.pNCS->pSerialPort->GetBaudrate()) {
+			theErr = infcSetNetRate(cNum, netInv.PhysPortSpecifier.PortRate);
+			#if defined(_DEBUG) && ((TRACE_CALLBACK&&TRACE_LOW_LEVEL) || LCL_INIT_PR || TRACE_SERIAL)
+			_RPT4(_CRT_WARN, "%.1f netEnumerate(%d): restoring baud, rate=%d, err=0x%x\n",
+				infcCoreTime(), cNum, netInv.PhysPortSpecifier.PortRate, theErr);
+			#endif
+			if (theErr != MN_OK)
+				return theErr;
+		}
+		for (i=0; i<maxNode; i++) {
+			pClassInfo = NULL;
+			// Get the device type from the
+			theErr = netGetParameter(MULTI_ADDR(cNum, i),
+									  MN_P_NODEID, &theResp);
+			// Correct packet and size?
+			if (theErr == MN_OK && theResp.Byte.BufferSize==2) {
+				theErr = netGetNodeAccessLvl(MULTI_ADDR(cNum, i),
+											 &netInv.AccessInfo[i]);
+				if (theErr == MN_OK) {
+					// Setup data for coreGetDevType
+					netInv.NodeInfo[i].theID =
+						*((devID_t *)&theResp.Byte.Buffer[0]);
+					// Initialize the nodes and reverse ranking
+					switch(netInv.NodeInfo[i].theID.fld.devType) {
+						case NODEID_MD:
+							pClassInfo = &netInv.InventoryNow.mnDrvInfo;
+							lastErr = iscInitializeEx(MULTI_ADDR(cNum,i), TRUE);
+							// Adjust the cleanup masks
+							for (size_t j=0; j<MN_API_MAX_NODES; j++)
+								netInv.attnCleanupMask[j] = 0xffffff;
+							break;
+	#if defined(IMPL_NODE_CP)
+						case NODEID_CP:
+							pClassInfo = &netInv.InventoryNow.mnClearPathInfo;
+							lastErr = clearPathInitializeEx(MULTI_ADDR(cNum,i), TRUE);
+							// Adjust the cleanup masks
+							for (size_t j=0; j<MN_API_MAX_NODES; j++)
+								netInv.attnCleanupMask[j] = 0;
+							break;
+	#endif
+						case NODEID_CS:
+							pClassInfo = &netInv.InventoryNow.mnCpScInfo;
+							lastErr = cpmInitializeEx(MULTI_ADDR(cNum,i), TRUE);
+							// If we have a port, setup nodes
+							if (netInv.pPortCls) {
+								try {
+									// sync up the node
+									netInv.pNodes[i]->Refresh();
+								}
+								catch (sFnd::mnErr theErr) {
+									// Something failed
+									lastErr = theErr.ErrorCode;
+								}
+								catch (...) {
+									return MN_ERR_FAIL;
+								}
+							}
+							// Adjust the cleanup masks
+							for (size_t j=0; j<MN_API_MAX_NODES; j++)
+								netInv.attnCleanupMask[j] = 0xffffffff;
+							break;
+						default:
+							lastErr = MN_ERR_WRONG_NODE_TYPE;
+							break;
+					}
+				}
+				// Update the inventory records
+				if (pClassInfo != NULL) {
+					// Build up the reverse link from the address
+					netInv.NodeInfo[i].rank = pClassInfo->count;
+					// Add one to the bunch and mark the location
+					pClassInfo->node[pClassInfo->count++] = MULTI_ADDR(cNum,i);
+				}
+			}
+			else {
+				netInv.NodeInfo[i].theID.fld.devType = NODEID_UNK;
+				lastErr = theErr;
+			}
+		}
+	}
+	// Initialize the remaining nodes to 'unknown'
+	for (i=maxNode+1 ; i<MN_API_MAX_NODES; i++) {
+		netInv.NodeInfo[i].theID.fld.devType = NODEID_UNK;
+		netInv.NodeInfo[i].rank = 0;
+	}
+
+	// Force Initialize mode to determine if online
+	netInv.OpenStateNext(OPENED_ONLINE);
+
+	// No more commands to protect
+	infcSetInitializeMode(cNum, FALSE, lastErr);
+
+	return lastErr;
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		netGetUserDescription
+//
+//	DESCRIPTION:
+/**
+	Get the user description for this node. An error is returned if the
+	node does not support this feature.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pUserDescrStr Return buffer area
+	\param[in] maxBufSize Size of \p pUserIdStr area
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetUserDescription(
+		multiaddr theMultiAddr,
+		char *pUserDescrStr,
+		Uint16 maxBufSize)
+{
+	cnErrCode theErr = MN_ERR_CMD_INTERNAL;
+	nodeparam theBasePnum;
+	paramValue paramBytes;
+	//Uint16 nProcessed = 0;
+	char *bufEnd = pUserDescrStr+maxBufSize-1;
+	size_t len;
+
+	// Args make sense?
+	if (!pUserDescrStr || !maxBufSize)
+		return MN_ERR_BADARG;
+	netaddr cNum = NET_NUM(theMultiAddr);
+	if (cNum>NET_CONTROLLER_MAX)
+		return MN_ERR_BADARG;
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	if (SysInventory[cNum].InventoryNow.NumOfNodes < theNode) {
+		return MN_ERR_ADDR_RANGE;
+	}
+	// Does this node support this
+	switch(SysInventory[cNum].NodeInfo[theNode].theID.fld.devType ) {
+#if defined(IMPL_NODE_CP)
+	case NODEID_CP:
+		theBasePnum = CP_P_USER_DESCR_BASE;
+		break;
+#endif
+	case NODEID_CS:
+		theBasePnum = CPM_P_USER_DESCR_BASE;
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+	// Insure null-term inside buffer. Link pkt is smaller than buffer
+	// so there will always be one just off the end.
+	memset(paramBytes.raw.Byte.Buffer, 0, sizeof(paramBytes.raw.Byte.Buffer));
+	// Get and concatenate chunks
+	for (size_t i=0; i<SC_USER_DESCR_SPAN; i++) {
+		theErr = netGetParameterInfo(theMultiAddr, nodeparam(theBasePnum+i),
+									NULL, &paramBytes);
+		if (theErr != MN_OK)
+			break;
+
+		// Do we have the null-term block?
+		len = strlen((const char *)paramBytes.raw.Byte.Buffer);
+		if (len>=maxBufSize) {
+			memcpy(pUserDescrStr, paramBytes.raw.Byte.Buffer, maxBufSize);
+			pUserDescrStr += maxBufSize;
+			break;
+		}
+		else {
+			memcpy(pUserDescrStr, paramBytes.raw.Byte.Buffer, SC_USER_DESCR_CHUNK);
+			maxBufSize -= SC_USER_DESCR_CHUNK;
+			pUserDescrStr += SC_USER_DESCR_CHUNK;
+		}
+	}
+	// Insure null-terminated
+	*bufEnd = '\0';
+	return(theErr);
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		netSetUserDescription
+//
+//	DESCRIPTION:
+/**
+	Set the user description for this node. Any ANSI character string maybe used
+	up to 125 characters.
+	
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewDescr Ptr to NULL terminated ANSI string.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netSetUserDescription(
+		multiaddr theMultiAddr,
+		const char *pNewDescr)
+{
+	cnErrCode theErr = MN_ERR_CMD_INTERNAL;
+	packetbuf paramBytes;
+	size_t len;
+	if (!pNewDescr)
+		return MN_ERR_BADARG;
+	netaddr cNum = NET_NUM(theMultiAddr);
+	if (cNum>NET_CONTROLLER_MAX)
+		return MN_ERR_BADARG;
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	nodeparam theBasePnum;
+	if (SysInventory[cNum].InventoryNow.NumOfNodes < theNode) {
+		return MN_ERR_ADDR_RANGE;
+	}
+	// Does this node support this
+	switch(SysInventory[cNum].NodeInfo[theNode].theID.fld.devType) {
+#if defined(IMPL_NODE_CP)
+	case NODEID_CP:
+		theBasePnum = CP_P_USER_DESCR_BASE;
+		break;
+#endif
+	case NODEID_CS:
+		theBasePnum = CPM_P_USER_DESCR_BASE;
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+	// Setup parameter buffer for set operation
+	paramBytes.Byte.BufferSize = SC_USER_DESCR_CHUNK;
+	len = strlen(pNewDescr);
+	for (size_t i=0; i<SC_USER_DESCR_SPAN; i++) {
+		// Insure null terminate and end of string bytes
+		memset(paramBytes.Byte.Buffer, 0, SC_USER_DESCR_CHUNK);
+		if (len > 0) {
+			strncpy((char *)paramBytes.Byte.Buffer,
+					(const char *)pNewDescr, SC_USER_DESCR_CHUNK);
+			// Insure last char is always NUL
+			if (i==(SC_USER_DESCR_SPAN-1)) {
+				paramBytes.Byte.Buffer[SC_USER_DESCR_CHUNK-1] = '\0';
+			}
+			pNewDescr += SC_USER_DESCR_CHUNK;
+			len -= SC_USER_DESCR_CHUNK; 
+		}
+		// Send chunks to drive
+		theErr = netSetParameterEx(theMultiAddr, nodeparam(theBasePnum+i),
+									&paramBytes);
+		if (theErr != MN_OK)
+			break;
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+
+
+//****************************************************************************
+//	NAME
+//		netGetUserID
+//
+//	DESCRIPTION:
+/**
+	Get the User ID for this node. This is an identifier the application
+	may use for "plug-and-play" or diagnostic purpose. 
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pUserIdStr Return buffer area
+	\param[in] maxBufSize Size of \p pUserIdStr area
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetUserID(
+		multiaddr theMultiAddr,
+		char *pUserIdStr,
+		Uint16 maxBufSize)
+{
+	packetbuf nameBuf, cmdBuf;
+	cnErrCode theErr;
+	size_t i;
+	char *pNextChar = pUserIdStr;
+ 	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+
+	cmdBuf.Byte.Buffer[CMD_LOC] = MN_CMD_USER_ID;
+	
+	// Clear out buffer with 0 padding
+	for(i=CMD_LOC+1; i<sizeof(nameBuf.Byte.Buffer); i++)
+		nameBuf.Byte.Buffer[i] = 0;
+	cmdBuf.Fld.Addr = theNode;
+	cmdBuf.Fld.PktLen = 1;
+	theErr = netRunCommand(cNum, &cmdBuf, &nameBuf); 
+	if (theErr == MN_OK) {
+		// Limit return size to buffer size plus room for terminating null.
+		i = nameBuf.Fld.PktLen+RESP_LOC;		// End char loc
+		if (nameBuf.Fld.PktLen > size_t(maxBufSize-1)) 
+			i = size_t(maxBufSize-1);
+		for (size_t j=RESP_LOC; j<i; j++) {
+			if (nameBuf.Byte.Buffer[j] >= ' ' 
+			&& nameBuf.Byte.Buffer[j] < 127)
+				*pNextChar++ = nameBuf.Byte.Buffer[j];
+			else
+				*pNextChar++ = 0;
+		}
+		// Ensure buffer is null terminated
+		*pNextChar = 0;
+	}
+	else {
+		pUserIdStr[0] = 0;
+	}
+	// If the UserID is null, fill it with our default
+	if (!pUserIdStr[0]) {
+		char modelStr[MN_PART_NUM_SIZE+1];
+		theErr = netGetPartNumber(theMultiAddr, modelStr, sizeof(modelStr));
+		if (theErr != MN_OK)
+			return theErr;
+		snprintf(pUserIdStr, maxBufSize, "Unloaded <%s>",
+			modelStr);
+	}
+
+	return(theErr);
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		netSetUserID
+//
+//	DESCRIPTION:
+/**
+	Set the User ID for this node. Any ANSI character string maybe used
+	up to 13 characters.
+	
+	This maybe used as an identifier for application "plug-and-play" or
+	diagnostic purposes. If set to NULL, the APS application will apply
+	a generic name "Axis \<addr\>" on its display.  A typical name could
+	be "X Axis".
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pNewName Ptr to NULL terminated ANSI string.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netSetUserID(
+		multiaddr theMultiAddr,
+		const char *pNewName)
+{
+	packetbuf nameBuf, respBuf;
+	size_t i, nSize;
+	cnErrCode theErr = MN_OK;
+	char newName[MN_USER_ID_SIZE_V2] = "";
+	
+	if(pNewName == NULL)
+		return(MN_ERR_BADARG);
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	nameBuf.Byte.BufferSize = 0;
+	nameBuf.Byte.Buffer[CMD_LOC] = MN_CMD_USER_ID;
+	// Setup buffer based on model
+	switch (SysInventory[cNum].NodeInfo[theNode].theID.fld.devType) {
+	case NODEID_MD:
+		nameBuf.Fld.PktLen = MN_USER_ID_SIZE+1;
+		// 02/12/2016 JS: This section of code will have to be tested the next
+		//                time we test the Meridian codebase!
+		if (strncmp(pNewName, "Axis ", strlen("Axis ")) != 0) {
+			// If it doesn't look like the default name, copy it over
+			strncpy(newName, pNewName, MN_USER_ID_SIZE);
+		}
+		break;
+	case NODEID_CP:
+	case NODEID_CS:
+	default:
+		nameBuf.Fld.PktLen = MN_USER_ID_SIZE_V2+1;
+		if (strncmp(pNewName, "Unloaded ", strlen("Unloaded ")) != 0) {
+			// If it doesn't look like the default name, copy it over
+			strncpy(newName, pNewName, MN_USER_ID_SIZE_V2);
+		}
+		break;
+	}
+	
+	nSize = strlen(newName);
+	if (nSize > nameBuf.Fld.PktLen) nSize = nameBuf.Fld.PktLen;
+
+	// Clear out buffer with 0 padding
+	for(i=nSize; i<nameBuf.Fld.PktLen; i++)
+		nameBuf.Byte.Buffer[i+CMD_LOC+1] = 0;
+	
+	strncpy((char *)&nameBuf.Byte.Buffer[CMD_LOC+1], 
+			(char *)&newName[0], nSize);
+	cleanForXML((char *)&nameBuf.Byte.Buffer[CMD_LOC+1]);
+	nameBuf.Fld.Addr = theNode;
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &nameBuf, &respBuf); 
+
+	return(theErr);
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		netRunCommand
+//
+//	DESCRIPTION:
+//		This function will send the specified command on the <cNum>
+//		and wait for the response and stores its response in <pTheResp>.
+//
+//		If <pTheResp> is NULL, this command returns MN_OK if the network
+//		controller accepts the command.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netRunCommand(
+		netaddr cNum,				// Controller number
+		packetbuf *pTheCmd,		// pointer to filled in command
+		packetbuf *pTheResp)
+{
+#define RUN_CMD_ERR_DBG (_DEBUG&&1)			// Show err src
+	cnErrCode theErr = MN_OK;
+	infcErrInfo errInfo;					// Error reporting buffer
+
+	if (pTheResp==NULL)
+		return(MN_ERR_BADARG);
+
+	if (cNum>NET_CONTROLLER_MAX)
+		return(MN_ERR_DEV_ADDR);
+
+	// Adjust the frame length to match command length information
+	// Initialize the command invariant information
+	pTheCmd->Fld.PktType = MN_PKT_TYPE_CMD;
+	pTheCmd->Fld.Src = MN_SRC_HOST;
+	pTheCmd->Fld.Mode = 0;
+	pTheCmd->Fld.Zero1 = 0;
+	pTheCmd->Byte.BufferSize = pTheCmd->Fld.PktLen + MN_API_PACKET_HDR_LEN;
+
+	// Run the command and check the response for acceptance.
+	if ((theErr = infcRunCommand(cNum, pTheCmd, pTheResp)) == MN_OK)  {
+		// Make sure the packet is consistent with the length
+		if (pTheResp->Byte.BufferSize
+		&& (pTheResp->Fld.PktLen + MN_API_PACKET_HDR_LEN)
+		   != pTheResp->Byte.BufferSize) {
+			//_RPT4(_CRT_WARN, "%.1f netRunCommand(%d): pkt buf mismatch,"
+			//				 "buf size=%d, pkt size=%d\n",
+			//				infcCoreTime(), cNum,
+			//				pTheResp->Byte.BufferSize,
+			//				pTheResp->Fld.PktLen + MN_API_PACKET_HDR_LEN);
+			theErr = MN_ERR_PKT_ERR;
+		}
+		else {
+			// Check that the response was legit
+			theErr = coreGenErrCode(cNum, pTheResp, pTheCmd->Fld.Addr);
+			#ifdef RUN_CMD_ERR_DBG
+			if (theErr != MN_OK) {
+				_RPT3(_CRT_WARN, "%.1f netRunCommand(%d): parse error 0x%x\n",
+								infcCoreTime(), cNum, theErr);
+			}
+			#endif
+
+		}
+	}
+	#ifdef RUN_CMD_ERR_DBG
+	else {
+		_RPT4(_CRT_WARN, 
+			"%.1f netRunCommand(%d): exec error 0x%x, thread=" THREAD_RADIX "\n",
+			infcCoreTime(), cNum, theErr, infcThreadID());
+	}
+	#endif
+	// If we find this in the normal coarse of events, fire off the callbacks
+	if (theErr != MN_OK) {
+		// Fire off the error callback
+		errInfo.cNum = cNum;
+		errInfo.node = MULTI_ADDR(cNum, pTheCmd->Fld.Addr);
+		infcCopyPktToPkt18(&errInfo.response, pTheResp);
+		if (theErr == MN_ERR_OFFLINE)
+			errInfo.errCode = (cnErrCode)(MN_ERR_OFFLINE_00+pTheCmd->Fld.Addr);
+		else
+			errInfo.errCode = theErr;
+		infcFireErrCallback(&errInfo);
+		// Insure response buffer is cleared
+		pTheResp->Fld.PktLen = 0;
+		pTheResp->Byte.BufferSize = 0;
+		_RPT4(_CRT_WARN, "%.1f netRunCommand(%d): response err 0x%x, thread=" THREAD_RADIX "\n",
+						infcCoreTime(), cNum, errInfo.errCode, infcThreadID());
+		// Create dump file on this error
+		infcTraceDumpNext(cNum);
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	NAME
+ *		coreGenErrCode
+ *
+ *	DESCRIPTION:
+ *		Create the appropriate error code for this buffer
+ *
+ *	RETURNS:
+ *		cnErrCode
+ *
+ *	SYNOPSIS: 															    */
+cnErrCode coreGenErrCode(netaddr cNum, packetbuf *pTheResp, nodeaddr cmdNode)
+{
+	nodebool initMode;
+	netErrGeneric *pErrPkt;
+	//char msg[100];
+
+	// Is the response plausible?
+	if (pTheResp->Byte.BufferSize < MN_API_PACKET_HDR_LEN)  {
+		return(MN_ERR_RESP_FMT);
+	}
+	// Get initialization mode flag
+	infcGetInitializeMode(cNum, &initMode);
+	// Is the address plausable and we are not in initialization phase?
+	if (pTheResp->Fld.PktType != MN_PKT_TYPE_SET_ADDR
+	&& (pTheResp->Fld.Addr > SysInventory[cNum].InventoryNow.NumOfNodes)
+	&& !initMode)
+		return(MN_ERR_ADDR_RANGE);
+	// Is this response from a known source?
+	if (pTheResp->Fld.Src != MN_SRC_HOST)
+		return(MN_ERR_WRONG_SRC);
+	// Has it been processed and OK?
+	switch(pTheResp->Fld.PktType) {
+		case MN_PKT_TYPE_CMD:
+			// Make sure response from proper node
+			if(pTheResp->Fld.Addr != cmdNode)
+				return(MN_ERR_RESP_ADDR);
+//			if(!initMode)
+//				return(MN_ERR_OFFLINE);
+			// Let upper levels declare this un-executed
+			return(MN_ERR_OFFLINE);
+		case MN_PKT_TYPE_ERROR:
+			pErrPkt = (netErrGeneric *)&pTheResp->Byte.Buffer[RESP_LOC];
+			switch (pErrPkt->Fld.ErrCls) {
+				case ND_ERRCLS_CMD:
+					return((cnErrCode)(MN_ERR_CMD_ERR_BASE
+									   + pErrPkt->Fld.ErrCode));
+				case ND_ERRCLS_NET:
+					return((cnErrCode)(MN_ERR_NET_ERR_BASE
+									   + pErrPkt->Fld.ErrCode));
+				default:
+					return(MN_ERR_FRAME);
+			}
+			break;
+		case MN_PKT_TYPE_RESP:
+			// If basically OK, make sure it came from proper node
+			if (pTheResp->Fld.Addr != cmdNode)
+				return(MN_ERR_RESP_ADDR);
+			return(MN_OK);
+		// Assume other are OK
+		case MN_PKT_TYPE_ATTN_IRQ:				// Attn Request
+		case MN_PKT_TYPE_SET_ADDR:				// Set Address
+		case MN_PKT_TYPE_TRIGGER:				// Motion trigger
+		case MN_PKT_TYPE_EXTEND_HIGH:			// Extended control frames
+		case MN_PKT_TYPE_EXTEND_LOW:
+			return(MN_OK);
+		default:
+			_RPT2(_CRT_WARN, "coreGenErrcode(%d), type unknown %d\n",
+				pTheResp->Fld.Addr, pTheResp->Fld.PktType);
+	}
+	return(MN_ERR_FAIL);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetParameterDbl
+//
+//	DESCRIPTION:
+/**
+	This function will get the parameter specified by \a theParamNum on
+	device \a theNode. The parameter is returned in the buffer pointed to
+	by \a paramInfo. The actual length and information will be updated
+	when this function returns MN_OK.
+
+	\param[in] cNum Channel number to for node. The first channel is zero.
+	\param[in] theNode Node address on the channel.
+	\param[in] theParamNum The parameter code number for retrieval.
+	\param[out] pValue Response area update with the scaled double
+				parameter value.
+
+	\return MN_OK if succeed and \p pValue updated
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetParameterDbl(
+		multiaddr theMultiAddr,
+		mnParams theParamNum,
+		double *pValue)
+{
+	cnErrCode theErr;
+	paramValue theValue;
+	theErr = netGetParameterInfo(theMultiAddr, theParamNum,
+								  NULL, &theValue);
+	*pValue = theValue.value;
+	return theErr;
+}
+
+
+//cnErrCode MN_DECL netGetParameterDbl(
+//		netaddr cNum,				// network controller
+//		nodeaddr theNode, 			// device address
+//		mnParams theParamNum,		// parameter index
+//		double *pValue)				// ptr for returned param
+//
+//{
+//	cnErrCode theErr;
+//	paramValue theValue;
+//	theErr = netGetParameterInfo(MULTI_ADDR(cNum, theNode), theParamNum,
+//								  NULL, &theValue);
+//	*pValue = theValue.value;
+//	return theErr;
+//}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netSetParameterDbl
+//
+//  DESCRIPTION:
+/**
+	This function will get the parameter specified by \a theParamNum on
+	device \a theNode. The parameter is returned in the buffer pointed to
+	by \a paramInfo. The actual length and information will be updated
+	when this function returns MN_OK.
+
+	\param[in] cNum Channel number to for node. The first channel is zero.
+	\param[in] theNode Node address on the channel.
+	\param[in] theParamNum The parameter code number for retrieval.
+	\param[in] value New value to set at the node.
+
+	\return MN_OK if the node's parameter is updated
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netSetParameterDbl(
+		multiaddr theMultiAddr,
+		mnParams theParamNum,
+		double value)
+{
+	cnErrCode theErr;
+	theErr = netSetParameterInfo(theMultiAddr,
+								  theParamNum, value, FALSE);
+	return theErr;
+}
+
+//cnErrCode MN_DECL netSetParameterDbl(
+//		netaddr cNum,				// network controller
+//		nodeaddr theNode, 			// device address
+//		mnParams theParamNum,		// parameter index
+//		double value)				// ptr for returned param
+//
+//{
+//	cnErrCode theErr;
+//	theErr = netSetParameterInfo(MULTI_ADDR(cNum, theNode),
+//								  theParamNum, value, FALSE);
+//	return theErr;
+//}
+//																			 *
+//****************************************************************************
+
+
+//******************************************************************************
+//	NAME
+//		netSetParameterEx
+//
+//	DESCRIPTION:
+/**
+	This function will run the set parameter command for device \a
+	theMultiAddr at parameter index \a theParamNum. The parameter
+	database is updated and any change callbacks issued for this node.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParamNum The parameter code number for retrieval.
+	\param[in] pParamBuf Ptr to value area
+
+	\return MN_OK if node updated successfully
+**/
+//	SYNOPSIS:
+
+MN_EXPORT cnErrCode MN_DECL netSetParameterEx(
+		multiaddr theMultiAddr, 		// node address
+		nodeparam theParamNum, 		// parameter index
+		packetbuf *pNewValue)		// ptr to new parameter data
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+	byNodeDB *pNodeInfo;			// Node information
+	paramBank *pParamBank;			// Current parameter bank
+	paramInfoLcl const *pTheInfoDB;	// Current parameter fixed info
+	paramValue *pTheValDB;			// Current value DB
+	netaddr cNum;
+	mnParamChg paramChgObj;			// Parameter change object
+	appNodeParam appParam;			// Parameter info extractor instance
+
+	cNum = coreController(theMultiAddr);
+	// Get a pointer to this node's information
+	pNodeInfo = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	// Bail if port closed/offline
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS || !(pNCS->pSerialPort) || !pNCS->pSerialPort->IsOpen())
+		return(MN_ERR_CLOSED);
+
+	if (pNodeInfo->paramBankList == NULL)
+		return(MN_ERR_PARAM_NOT_INIT);
+
+	// Request makes sense?
+	appParam.bits = theParamNum;
+	if (appParam.fld.bank >= pNodeInfo->bankCount) {
+		return MN_ERR_PARAM_RANGE;
+	}
+
+	if ((theErr = netSetParameterFmt(&theCmd,
+								      theMultiAddr,
+								      theParamNum,
+								      pNewValue)) == MN_OK) {
+		// Can/should we update the value table
+		pParamBank = &(pNodeInfo->paramBankList)[appParam.fld.bank];
+		if (pParamBank->nParams > appParam.fld.param) {
+			pTheInfoDB = pParamBank->fixedInfoDB+appParam.fld.param;
+			pTheValDB =  pParamBank->valueDB+appParam.fld.param;
+		}
+		else {
+			pTheInfoDB = NULL;
+			pTheValDB =  NULL;
+		}
+
+
+		// Update the parameter database if necessary
+		if (theErr == MN_OK && pTheValDB) {
+			// If non-volatile, make sure the length match
+			if (appParam.fld.param < pParamBank->nParams) {
+				// Too big for parameter?
+				if ((unsigned)labs(pTheInfoDB->info.paramSize) < pNewValue->Byte.BufferSize)
+					return(MN_ERR_VALUE);
+				// If positive, it must match
+				if (pTheInfoDB->info.paramSize > 0
+				&& (pTheInfoDB->info.paramSize != pNewValue->Byte.BufferSize))
+					return(MN_ERR_VALUE);
+				// Only fail if Read-Only past here
+				if (!(pTheInfoDB->info.paramType & PT_RO)) {
+					pTheValDB->raw = *pNewValue;
+				}
+				// If VA, the double value is meaningless, make 0
+				if (pTheInfoDB->info.paramSize <= 0) {
+					pTheValDB->value = 0;
+				}
+				// Call the parameter handler if it exists
+				if (pTheInfoDB->converter) {
+					(*pTheInfoDB->converter)(false, theMultiAddr, appParam, 0, pNodeInfo);
+				}
+			}
+		}
+		// If buffer is still OK, run the command
+		if (theErr == MN_OK) {
+			//if (verify)
+				theErr = netRunCommand(cNum, &theCmd, &theResp);
+			//else
+			//	theErr = netRunCommand(cNum, &theCmd, NULL);
+			// Mark that we set the value
+			if (theErr == MN_OK) {
+				if (pTheValDB) {
+					pTheValDB->exists = TRUE;
+					paramChgObj.newValue = pTheValDB->value;
+					pTheValDB->value = coreBufToDouble(pTheInfoDB, pTheValDB);
+				}
+				else {
+					paramValue pv;
+					pv.raw = *pNewValue;
+					paramChgObj.newValue = coreBufToDouble(pTheInfoDB, &pv);
+				}
+
+				paramChgObj.net = cNum;
+				paramChgObj.node = theMultiAddr;
+				paramChgObj.paramNum = theParamNum;
+				// Call the callback
+				infcFireParamCallback(pNodeInfo->pClassInfo->paramChngFunc,
+									  &paramChgObj);
+			}
+		}
+		else {
+			_RPT1(_CRT_WARN, "netSetParameterEx error: %0X\n", theErr);
+		}
+	}
+	return (theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		netSetAddress
+//
+//	DESCRIPTION:
+//		Re-address the selected network and return the quantity of nodes
+//		detected.
+//
+//		NOTE:	The network is addressed starting from <maxNode>.  For normal
+//				operation caller should initialize <maxNode> to 0.
+//
+//	RETURNS:
+//		MN_OK and *maxNode set, else the error condition
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netSetAddress(
+		netaddr cNum,
+		nodeulong *maxNode)
+{
+	packetbuf theCmd, theResp;
+	unsigned i;
+	cnErrCode theErr = MN_ERR_FAIL;
+
+	theCmd.Byte.BufferSize = 2;						// This is always length 2
+
+	// Build set address packet
+	infcSetAddressFmt(*maxNode, &theCmd);
+
+	SysInventory[cNum].InventoryNow.NumOfNodes = *maxNode = 0;		// Assume no response
+	theErr = MN_ERR_FAIL;
+	// Run the set address control frame a few times
+	for (i=0; i<3 && theErr != MN_OK; i++) {
+		if ((theErr = infcRunCommand(cNum, &theCmd, &theResp)) == MN_OK)  {
+			// Make sure this is the correct response type
+			if ((theResp.Fld.PktType != MN_PKT_TYPE_SET_ADDR
+			|| theResp.Byte.BufferSize != theCmd.Byte.BufferSize)) {
+				theErr = MN_ERR_RESP_FMT;
+			}
+			// We did get a valid response
+			else if (((setAddrPkt *) &theResp)->Fld.Err != 0 && theResp.Fld.Addr > 0) {
+				theErr = MN_ERR_TOO_MANY;
+			}
+			else {
+				// Extract the address/# of nodes (0 means 16 nodes online)
+				*maxNode = theResp.Fld.Addr > 0 ? theResp.Fld.Addr :
+												// <err> will be set if there are 16
+												// else we got back what we sent
+												(theResp.Fld.Mode ? 16 : 0);
+				SysInventory[cNum].InventoryNow.NumOfNodes = *maxNode;
+				#if TRACE_HIGH_LEVEL
+				_RPT3(_CRT_WARN, "%.1f netSetAddress(%d): found %d\n",
+								infcCoreTime(), cNum, *maxNode);
+				#endif
+			}
+		}
+		#ifdef _DEBUG
+		else {
+		//	infcFlush();
+			_RPT3(_CRT_WARN, "%.1f netSetAddress(%d): failed %0X!\n",
+							  infcCoreTime(), cNum, theErr);
+		}
+		#endif
+	}
+	// Reverse the addresses if this is the diagnostic network to align
+	// numbering with the Application net.
+	if (theErr == MN_OK && *maxNode>0) {
+		// Ask the first node on our net to find out what net it is
+		// attached to.
+		mnNetStatus netState;
+		theErr = netGetNodeAccessLvl(MULTI_ADDR(cNum,0), &netState);
+		if (theErr == MN_OK) {
+			// Tell driver for diagnostics purposes
+			infcSetNetSource(cNum, (mnNetSrcs)netState.Fld.NetSource);
+			if (netState.Fld.NetSource != MN_SRC_APP_NET) {
+				_RPT2(_CRT_WARN, "%.1f netSetAddress(%d): reversing addresses of diag net\n",
+								  infcCoreTime(), cNum);
+				theErr = netReverseAddress(cNum, *maxNode-1);
+			}
+		}
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+
+//****************************************************************************
+//	NAME
+//		netReverseAddress
+//
+//	DESCRIPTION:
+//		Re-address the selected network by taking the node's current address
+//		and subtracting the <nodeCountLessOne> value from it. The affect is
+//		to reverse address the targeted network. This is done to allow a
+//		reverse wired diagnostic net to have the same addresses as the forward
+//		direction.
+//
+//	RETURNS:
+//		MN_OK if successfully executed
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netReverseAddress(
+		netaddr cNum,
+		nodeaddr nodeCountLessOne)
+{
+	packetbuf theCmd, theResp;
+	unsigned i;
+	cnErrCode theErr = MN_ERR_FAIL;
+
+	theCmd.Byte.BufferSize = 3;						// This is always length 3
+
+	// Build set address control frame
+	theCmd.Fld.PktLen = 1;
+	theCmd.Fld.Addr = nodeCountLessOne;
+	theCmd.Fld.PktType = MN_PKT_TYPE_EXTEND_HIGH;
+	theCmd.Fld.Mode = theCmd.Fld.Zero1 = 0;	// Fill in unused with 0
+	theCmd.Fld.Src = MN_SRC_HOST;
+	theCmd.Byte.Buffer[EXTEND_CODE_LOC] = MN_CTL_EXT_REV_ADDR;
+
+	theErr = MN_ERR_FAIL;
+	// Run the set address control frame a few times
+	for (i=0; i<3 && theErr != MN_OK; i++) {
+		if ((theErr = infcRunCommand(cNum, &theCmd, &theResp)) == MN_OK)  {
+			// Make sure this is the correct response type
+			if ((theResp.Fld.PktType != MN_PKT_TYPE_EXTEND_HIGH)) {
+				theErr = MN_ERR_RESP_FMT;
+			}
+			// We did get a valid response
+		}
+		else {
+		//	infcFlush();
+			_RPT1(_CRT_WARN, "netReverseAddress: failed %0X!\n", theErr);
+		}
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netReset
+//
+//	DESCRIPTION:
+//		Format and run the node reset command. This command will return with a
+//		time-out if the network is broken. The node waits for the completion
+//		of the re-transmission of this command before actually resetting.
+//
+//		<theMultiAddr> = 0 will reset all nodes on the network except the NC
+//		else the specific node is reset.
+//
+//		NOTE: DS 2/3/2010 deprecating this for public use as it requires
+//		scheduling of a baud rate change and restoration to prevent the node
+//		from being isolated at an incompatible baud rate.
+//
+//	RETURNS:
+//		ND_ERR_TIMEOUT normally
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL netReset(
+		multiaddr theMultiAddr,
+		nodebool broadCast) 				// node address
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+	int i;
+	netaddr cNum = coreController(theMultiAddr);
+
+	// Try reset a couple of times (this is a hack!)
+	for (i=0; i<3; i++) {
+
+		theCmd.Fld.SetupHdr(MN_PKT_TYPE_EXTEND_HIGH,
+							  NODE_ADDR(theMultiAddr),
+							  MN_SRC_HOST);
+		theCmd.Fld.PktLen = 1;
+		theCmd.Fld.Mode=broadCast;
+		theCmd.Byte.Buffer[CMD_LOC] = MN_CTL_EXT_RESET;
+		theCmd.Byte.BufferSize = theCmd.Fld.PktLen + MN_API_PACKET_HDR_LEN;
+		theErr = infcRunCommand(cNum, &theCmd, &theResp);
+		if (theErr == MN_OK)
+			break;
+	}
+
+	// Show reset state
+	infcFireNetEvent(cNum, NODES_RESETTING);
+	// Wait for nodes to reset
+	infcSleep(MN_MAX_RESET_TIME);
+	return (theErr);
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		netGetNodeAccessLvl
+//
+//	DESCRIPTION:
+//		Gets the the node access level of the specified node on the specified
+//		node.
+//
+//		Parameter
+//			theMultiAddr - the node on the network to get the access level
+//
+//			theAccessLevel - this is the new access level to be set at
+//				0 = MN_ACCESS_LVL_MONITOR
+//				1 = MN_ACCESS_LVL_TUNE
+//				2 = MN_ACCESS_LVL_FULL
+//
+//	RETURNS:
+//		MN_OK on success or cnErrCode reason.
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL netGetNodeAccessLvl(
+	multiaddr theMultiAddr,							// Destination node
+	mnNetStatus *pAccessLevel)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	// Build the command packet
+	theCmd.Fld.PktLen = 1;
+	theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);
+	theCmd.Fld.PktType = MN_PKT_TYPE_CMD;
+	theCmd.Fld.Mode = theCmd.Fld.Zero1 = 0;	// Fill in unused with 0
+	theCmd.Fld.Src = MN_SRC_HOST;
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_NET_ACCESS;
+	theCmd.Byte.BufferSize = theCmd.Fld.PktLen + MN_API_PACKET_HDR_LEN;
+
+	if ((theErr = infcRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp)) == MN_OK) {
+		// Make sure this is the correct response type
+		if ((theResp.Fld.PktType != MN_PKT_TYPE_RESP)) {
+			_RPT1(_CRT_WARN, "netSetNodeAccessLvl: failed %0X!\n", theErr);
+		}
+	}
+	pAccessLevel->bits = theResp.Byte.Buffer[RESP_LOC];
+	return(theErr);
+}
+//																		      *
+//*****************************************************************************
+
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+/*  PRIVATE DLL UTILITY FUNCTIONS 										   */
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+
+/*****************************************************************************
+ *	NAME
+ *		coreBufToDouble
+ *
+ *	DESCRIPTION:
+ *		Convert the buffer to a double precision floating point value.
+ *
+ *		NOTE: This code depends on little-endian architecture
+ *
+ *	RETURNS:
+ *		double precision value of buffer contents
+ *
+ *	SYNOPSIS: 															    */
+double coreBufToDouble(
+	const paramInfoLcl *info,			// Information about this param
+	paramValue *bufValue)				// Effective value
+{
+	hwVers_t hwVersInfo;
+	versID_t fwVersInfo;
+	devID_t theID;
+	const char *devIDstr;
+	char devIDunkn[5];
+	double val;
+	unsigned long lVal;
+
+	// Perform sign extended conversion right from buffer
+	switch (bufValue->raw.Byte.BufferSize)  {
+		case 1:
+			val = (nodechar)bufValue->raw.Byte.Buffer[0];
+			break;
+		case 2:
+			val = *((nodeshort *)&bufValue->raw.Byte.Buffer[0]);
+			break;
+		case 3:
+			// Sign extend and convert to long
+			if (bufValue->raw.Byte.Buffer[2] & 0x80)
+				bufValue->raw.Byte.Buffer[3] = (nodechar)0xff;
+			else
+				bufValue->raw.Byte.Buffer[3] = 0x0;
+			// no break OK (special line for Code Analyzer to suppress warning)
+		case 4:
+			val = *((nodelong *)&bufValue->raw.Byte.Buffer[0]);
+			break;
+		case 6:
+			// Sign extend and convert to long
+			if ((bufValue->raw.Byte.Buffer[5] & 0x80) &&
+				(info->info.signextend ==ST_SIGNED)) {
+				bufValue->raw.Byte.Buffer[6] = (nodechar)0xff;
+				bufValue->raw.Byte.Buffer[7] = (nodechar)0xff;
+			} else {
+				bufValue->raw.Byte.Buffer[6] = 0x00;
+				bufValue->raw.Byte.Buffer[7] = 0x00;
+			}
+			// no break OK (special line for Code Analyzer to suppress warning)
+		case 8:
+#if (defined(_MSC_VER))
+			#pragma warning(push)
+			#pragma warning(disable: 4244)
+#endif
+			val = *((long long *)&bufValue->raw.Byte.Buffer[0]);
+#if (defined(_MSC_VER))
+			#pragma warning(pop)
+#endif
+			break;
+		default:
+			bufValue->exists = FALSE;
+			val = 0;
+			break;
+	}
+	// This a generic buffer conversion?
+	if (info == NULL) {
+		return(val);
+	}
+	// Is this non-defined type conversion?
+	if (info->info.paramType == PT_NONE) {
+		// Return as plain signed integer
+		bufValue->exists = TRUE;
+		return(val);
+	}
+	bufValue->exists = TRUE;			// Assume good until the end
+
+	if (info->info.paramSize <= 0)
+		return (0);						// There is no double view
+
+	// Do we know anything about this parameter?
+	lVal = (long)val;
+	switch(info->info.unitType) {
+		// Note: These are special cases, where the buffer is transformed
+		// into an intermediate form.
+		case DEV_ID:
+			theID = *((devID_t *)(&lVal));
+			switch(theID.fld.devType) {
+				case NODEID_MD:
+					devIDstr = "MD";
+					break;
+				case NODEID_CP:
+					devIDstr = "CP";
+					break;
+				case NODEID_CS:
+					devIDstr = "CS";
+					break;
+				default:
+					devIDstr = &devIDunkn[0];
+					sprintf((char *)devIDstr, "%d.", theID.fld.devType);
+					break;
+			}
+			bufValue->raw.Byte.BufferSize
+			= sprintf((char *)bufValue->raw.Byte.Buffer,
+					"%s.%d",
+					devIDstr, theID.fld.devModel);
+			return val;
+		case FW_VERS:
+			fwVersInfo = *((versID_t *)(&lVal));
+			bufValue->raw.Byte.BufferSize
+			= sprintf((char *)bufValue->raw.Byte.Buffer,
+					"%d.%d.%d",
+					fwVersInfo.fld.majorVers, fwVersInfo.fld.minorVers, fwVersInfo.fld.buildVers);
+			return val;
+		case HW_VERS:
+			hwVersInfo = *((hwVers_t *)(&lVal));
+			if (hwVersInfo.fld.Major<26) {
+				bufValue->raw.Byte.BufferSize
+				= sprintf((char *)bufValue->raw.Byte.Buffer,
+						"%c%d",
+						hwVersInfo.fld.Major+'A', hwVersInfo.fld.Minor);
+			}
+			else {
+				bufValue->raw.Byte.BufferSize
+				= sprintf((char *)bufValue->raw.Byte.Buffer,
+						"%c%c%d",
+						hwVersInfo.fld.Major/26+'A', hwVersInfo.fld.Major%26+'A',
+						hwVersInfo.fld.Minor);
+			}
+			return val;
+		default:
+			// Convert buffer to signed integer
+			switch(info->info.signextend)  {
+				case ST_SIGNED:
+					// <val> was already converted this way
+					break;
+				case ST_UNSIGNED:
+				case ST_POS_ONLY:
+					// Unsigned
+					switch (bufValue->raw.Byte.BufferSize) {
+						case 1:
+							val = (nodechar)bufValue->raw.Byte.Buffer[0];
+							break;
+						case 2:
+							val = *((nodeushort *)&bufValue->raw.Byte.Buffer[0]);
+							break;
+						case 3:
+							bufValue->raw.Byte.Buffer[3] = 0x0;
+							// no break OK (special line for Code Analyzer to suppress warning)
+						case 4:
+							val = *((nodelong *)&bufValue->raw.Byte.Buffer[0]);
+							break;
+						case 6:
+						case 8:
+							break;
+						default:
+							bufValue->exists = FALSE;
+							return(0);
+					}
+					break;
+			}
+			//
+			// Scale the value by the appropriate amount and take reciprical flag
+			// into consideration.
+			//
+			if (!info->info.reciprical && info->info.scaleFromBase != 0) {
+				// Avoid divide by 0 by leaving value @ 0
+				if (val != 0)
+					val /= info->info.scaleFromBase;
+				else
+					val	= 0;
+			}
+			else {
+				val *= info->info.scaleFromBase;
+			}
+			return(val);
+	}
+	//// If we got here, the value was not OK
+	//bufValue->exists = FALSE;
+	//return(0);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+ 
+/*****************************************************************************
+ *	NAME
+ *		coreDoubleToBuf
+ *
+ *	DESCRIPTION:
+ *		This function will convert a double precision floating point value
+ *		<newValue> into a nodechar buffer area. If <info> is defined that
+ *		value is scaled appropriately into the proper fixed point value.
+ *
+ *		If <info> is NULL, the value is assumed to be an signed integer
+ *		value whose length is defined by <bufsize>.
+ *
+ *		NOTE: This code depends on little-endian architecture
+ *
+ *	RETURNS:
+ *		cnErrCode, MN_OK if successful
+ *
+ *	SYNOPSIS: 															    */
+void coreDoubleToBuf(
+	const paramInfoLcl *info, 			// Parameter information
+	packetbuf *buffer,					// Ptr to start of buffer
+	double newValue)					// Value to set
+{
+	int64 lValue;
+	Uint64 uMax;
+
+	if (info == NULL)  {
+		// Default value to at least a long
+		lValue = (int64)(newValue+0.5);			// Convert to a long
+	}
+	else {
+		double scaleFact = info->info.scaleFromBase;
+		// Round only scaled items
+		if (!info->info.reciprical)  {
+			lValue = (int64)(newValue * scaleFact 
+				+ (scaleFact > 1.0? 0.5 : 0));
+		}
+		else {
+			// Avoid the divide by 0 case
+			if (newValue != 0)
+				lValue = (int64)(newValue / scaleFact 
+				+ (scaleFact > 1.0? 0.5 : 0));
+			else
+				lValue = 0;
+		}
+		#define BIG1 (Uint64(1))
+		switch (info->info.signextend) {
+			case ST_SIGNED:
+				uMax = (BIG1<<(8*buffer->Byte.BufferSize-1))-1;
+				if (lValue > 0 && lValue > (int64)uMax) lValue = (Uint64)uMax;
+				if (lValue < 0 && lValue < -((int64)uMax))
+					lValue = -((int64)uMax+1);
+				break;
+			case ST_UNSIGNED:
+				uMax = (BIG1<<(8*buffer->Byte.BufferSize))-1;
+				lValue &= uMax;
+				break;
+			case ST_POS_ONLY:
+				uMax = (BIG1<<(8*buffer->Byte.BufferSize-1))-1;
+				if (lValue > (int64)uMax) lValue = uMax;
+				if (lValue < 0) lValue = 0;
+				break;
+		}
+	}
+	//
+	// Convert this nominal long into the buffer area
+	//
+	switch (labs(buffer->Byte.BufferSize)) {
+		case 1:
+			buffer->Byte.Buffer[0] = (nodechar)lValue;
+			break;
+		case 3:
+			buffer->Byte.Buffer[2] = *((nodechar *)(&lValue)+2);
+			// Set LSBs with int case
+			// no break OK (special line for Code Analyzer to suppress warning)
+		case 2:
+			*((int16 *)&buffer->Byte.Buffer[0])
+			= (int16)lValue;
+			break;
+		case 4:
+			*((int32 *)&buffer->Byte.Buffer[0])
+			= (int32)lValue;
+			break;
+		case 8:
+			*((int64 *)&buffer->Byte.Buffer[0])
+			= (int64)lValue;
+			break;
+		default:
+			// Leave the buffer along, we can't do this
+			_RPT2(_CRT_WARN, "coreDoubleToBuf: Unknown conversion size %d, desc ID=%d\n",
+								buffer->Byte.BufferSize, info->info.descID);
+			break;
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+ 
+/*****************************************************************************
+ *	NAME
+ *		coreUpdateParamInfo
+ *
+ *	DESCRIPTION:
+ *		This function initializes the parameter manager for a particular
+ *		node class.
+ *
+ *	RETURNS:
+ *		cnErrCode, MN_OK if successful
+ *
+ *	SYNOPSIS: 															    */
+cnErrCode coreUpdateParamInfo(
+	multiaddr theMultiAddr)			// Node address
+{
+	nodeparam pNum;					// Parameter loop counter
+	cnErrCode lastErr = MN_OK;
+	netaddr cNum;
+	//cnErrCode errRet;
+	byNodeDB *pNodeInfo;			// Node information
+	paramBank *pParamBank;			// Current parameter bank
+	paramInfoLcl const *pFixedInfoDB;	// Current parameter fixed info
+	paramValue *pValueDB;			// Current value DB
+	unsigned bank;
+	#ifdef PRE_CACHE
+	appNodeParam coreParam;
+	coreParam.bits = 0;
+	#endif
+
+
+	cNum = coreController(theMultiAddr);
+	// Get a pointer to this node's information
+	pNodeInfo = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	for(bank=0; bank<pNodeInfo->bankCount; bank++) {
+		// Get fixed and current parameter value information pointers
+		pParamBank = &(pNodeInfo->paramBankList)[bank];
+		// Now get the values from the node and update the value DB
+		for(pNum=0; pNum<pParamBank->nParams; pNum++) {
+            #ifdef PRE_CACHE
+                coreParam.fld.bank = bank;
+                coreParam.fld.param = pNum;
+            #endif
+			pFixedInfoDB = &pParamBank->fixedInfoDB[pNum];
+			pValueDB = &pParamBank->valueDB[pNum];
+			pValueDB->isPolled = FALSE;
+			pValueDB->exists = FALSE;			// Mark "un-read"
+			pValueDB->value = 0;
+			if (pFixedInfoDB->info.paramType != PT_NONE)  {
+#ifdef PRE_CACHE
+				errRet = netGetParameter(theMultiAddr, coreParam.bits,
+										  &pValueDB->raw);
+				// Convert this buffer to a double
+				if (errRet == MN_OK)  {
+					// Scale the base units to the user's units
+					fromBaseUnit(theMultiAddr, coreParam, pNodeInfo,
+						   	   pFixedInfoDB, pParamBank, pValueDB);
+				}
+				else {
+					_RPT2(_CRT_WARN,"coreUpdateParamInfo error %x on param %d\n",
+						  errRet, coreParam.bits);
+				}
+				// Mark the value as valid
+				pValueDB->exists = errRet == MN_OK;
+				// Mark the error
+				if (pValueDB->exists) {
+					// Force a callback if defined
+					paramChgObj.node = theMultiAddr;
+					paramChgObj.net = cNum;
+					paramChgObj.paramNum = coreParam.bits;
+					paramChgObj.newValue = pValueDB->value;
+					infcFireParamCallback(pNodeInfo->pClassInfo->paramChngFunc,
+									      &paramChgObj);
+				}
+#endif
+			}
+			else {
+				//lastErr = errRet;
+			}
+		} // for pNum
+	}
+	return(lastErr);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	NAME
+ *		netGetParameterInfo
+ *
+ *	DESCRIPTION:
+ *		This is a generic parameter read function that gets augmented
+ *		parameter information.
+ *
+ *	RETURNS:
+ *		cnErrCode, MN_OK if successful
+ *
+ *	SYNOPSIS: 															    */
+MN_EXPORT cnErrCode MN_DECL netGetParameterInfo(
+		multiaddr theMultiAddr,			// Node address
+		nodeparam theParam,			// Parameter number
+		paramInfo *pRetValInfo,		// Ptr to returning value info or NULL
+		paramValue *pRetVal)		// Ptr to returning value or NULL
+{
+	appNodeParam coreParam;			// The core parameter number
+	cnErrCode theErr=MN_OK;
+	double initialVal;				// Initial value for this parameter
+	mnParamChg paramChgObj;			// Parameter change object
+	byNodeDB *pNodeInfo;			// Node information
+	paramBank *pParamBank;			// Current parameter bank
+	paramInfoLcl const *pFixedInfoDB;	// Current parameter fixed info
+	paramInfoLcl dummyInfo;			// Dummy information
+	paramValue *pValueDB;			// Current value DB
+	netaddr cNum;					// Current network
+
+	cNum = coreController(theMultiAddr);
+
+#if 0
+	if (NODE_ADDR(theMultiAddr) == 4 && theParam == ISC_P_STATUSRT_REG) {
+		_RPT0(_CRT_WARN, "StatusRT\n");
+	}
+#endif
+	// Bail if port closed/offline
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS || !(pNCS->pSerialPort) || !pNCS->pSerialPort->IsOpen())
+		return(MN_ERR_CLOSED);
+	pNodeInfo = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	if (pNodeInfo->paramBankList == NULL)
+		return(MN_ERR_PARAM_NOT_INIT);
+
+	// Initialize the parameter cracker
+	coreParam.bits = theParam;
+	// Request makes sense?
+	if (coreParam.fld.bank >= pNodeInfo->bankCount) {
+		return MN_ERR_PARAM_RANGE;
+	}
+	// Create shortcut to the proper parameter bank
+	pParamBank = &(pNodeInfo->paramBankList)[coreParam.fld.bank];
+
+	if (coreParam.fld.param < pParamBank->nParams)  {
+		paramValue optVal;
+		// We are within our database, copy the basic information
+		// to the user if requested. First speed up the operations
+		// and clutter by initializing local values.
+
+		// Initialize shortcuts
+		pFixedInfoDB = pParamBank->fixedInfoDB + coreParam.fld.param;
+		if (coreParam.fld.option)
+			pValueDB = &optVal;
+		else
+			pValueDB = pParamBank->valueDB + coreParam.fld.param;
+		// Save initial value
+		initialVal = pValueDB->value;
+
+		// Are they requesting extra information?
+		if (pRetValInfo) {
+			*pRetValInfo = pFixedInfoDB->info;
+		} // if (pRetValInfo)
+
+		//
+		// If this is a real time parameter, never been read or the
+		// Option Bit is set update the value DB now. If option bit
+		// is set the acquired value is not cached.
+		//
+		if (((pFixedInfoDB->info.paramType & PT_RT) != 0)
+		  || coreParam.fld.option
+		  || !pValueDB->exists
+		  || (pFixedInfoDB->info.paramType == PT_NONE)) {
+
+			// Read from the node directly, real-time, EEPROM type or first time
+			theErr = netGetParameter(theMultiAddr, theParam, &pValueDB->raw);
+			// Kill the command execute bit for all opstates
+			//_RPT2(_CRT_WARN, "netCore: get param(RT) node=%d, param=%d\n", theMultiAddr, theParam);
+			// If we got value OK, convert to value
+			if (theErr == MN_OK)  {
+				// Update the database entry
+				fromBaseUnit(theMultiAddr, coreParam, pNodeInfo,
+						   pFixedInfoDB, pParamBank, pValueDB);
+			}
+		}
+
+		// This parameter converted OK
+		pValueDB->exists = (theErr == MN_OK);
+		// So far so good?
+		if (theErr != MN_OK)  {
+			// Nope, make sure value is marked as junk
+			if (pRetValInfo) {
+				pRetValInfo->unitType = NO_UNIT;
+				pRetValInfo->paramType  = PT_UNKNOWN;
+			}
+			return(theErr);
+		}
+
+		//
+		// We have a value in pValueDB, return it via pRetVal after
+		// performing possible scaling.
+		//
+
+		// Copy raw parts to user's buffer, assume no scaling
+		*pRetVal = *pValueDB;
+		// If this is a clear-on-read type, OR in with previous value(s)
+		// and kill the DB copy now
+		if ((pFixedInfoDB->info.paramType & PT_CLR) != 0)  {
+			pRetVal->value = (unsigned long)pRetVal->value
+								   | (unsigned long)initialVal;
+			pValueDB->value = 0;
+		}
+		// Signal parameter change if this occurred	using user unit values
+		if(initialVal != pRetVal->value) {
+			paramChgObj.net = cNum;
+			paramChgObj.node = theMultiAddr;
+			paramChgObj.paramNum = coreParam.bits;
+			paramChgObj.newValue = pRetVal->value;
+			// Call the callback
+			infcFireParamCallback(pNodeInfo->pClassInfo->paramChngFunc,
+								  &paramChgObj);
+			// If clear-on-read, kill the old value
+			if (pFixedInfoDB->info.paramType & PT_CLR)
+				pValueDB->value = 0;
+		}
+	}
+	else {
+		//
+		// Off the end of the table.
+		// Dummy up a parameter descriptor making this value an integer.
+		//
+		dummyInfo.info.reciprical = FALSE;
+		dummyInfo.info.signextend = FALSE;
+		dummyInfo.info.unitType = NO_UNIT;
+		dummyInfo.info.paramType = PT_UNKNOWN;
+		dummyInfo.info.scaleFromBase = 1;
+		dummyInfo.info.signextend = ST_SIGNED;
+		dummyInfo.info.descID = STR_UNKNOWN;
+		dummyInfo.converter = NULL;
+
+		// Get value in real-time from node into local area and return
+		theErr = netGetParameter(theMultiAddr, theParam, &pRetVal->raw);
+		if (theErr == MN_OK)  {
+			// Dummy up the size from the received data
+			dummyInfo.info.paramSize = pRetVal->raw.Byte.BufferSize;
+			pRetVal->value = coreBufToDouble(&dummyInfo, pRetVal);
+		}
+		if (pRetValInfo)
+			*pRetValInfo = dummyInfo.info;
+		// Fire the callback if it exists
+		paramChgObj.net = cNum;
+		paramChgObj.node = theMultiAddr;
+		paramChgObj.paramNum = coreParam.bits;
+		paramChgObj.newValue = pRetVal->value;
+		infcFireParamCallback(pNodeInfo->pClassInfo->paramChngFunc,
+								  &paramChgObj);
+	}
+#ifdef TRACE_PARAMS
+	_RPT3(_CRT_WARN, "netGetParameterInfo(0x%x,p=%d)=>%f\n", theMultiAddr, theParam, pRetVal->value);
+#endif
+	return(theErr);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+ 
+/*****************************************************************************
+ *	NAME
+ *		netSetParameterInfo
+ *
+ *	DESCRIPTION:
+ *		This function will take a VB friendly double precision floating point
+ *		value and convert it to the proper internal representation for the
+ *		node and update the node and if this succeeds the value database will
+ *		be updated to match this value.
+ *
+ *	RETURNS:
+ *		cnErrCode, MN_OK if successful
+ *
+ *	SYNOPSIS: 															    */
+cnErrCode netSetParameterInfo(
+		multiaddr theMultiAddr,		// Node address
+		nodeparam theParam,		   	// Parameter number
+		const double theValue,	   	// New value
+		nodebool verify)			// TRUE, verify write worked OK
+{
+	cnErrCode theErr;
+	paramValue newParamValue, *pVal;
+//	double oldValue;
+	mnParamChg paramChgObj;			// Parameter change
+	appNodeParam coreParam;			// Parameter cracker
+	byNodeDB *pNodeInfo;			// Node Data
+	paramBank *pParamBank;			// Current parameter bank
+	paramInfoLcl const *pFixedInfoDB;	// Current parameter fixed info
+	netaddr cNum;				// Current network
+	// Vars for manipulating unknown parameters
+	paramInfoLcl dummyInfo;			// Unknown parameter dummy info
+	packetbuf dummyBuf;				// Scratch buffer
+#ifdef TRACE_PARAMS
+	_RPT3(_CRT_WARN, "netSetParameterInfo(0x%x,p=%d)<=%f\n", theMultiAddr, theParam,theValue);
+#endif
+	// Get node base info
+	cNum = coreController(theMultiAddr);
+	coreParam.bits = theParam;		// Initialize the parameter cracker
+
+	pNodeInfo = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	if (coreParam.fld.bank >= pNodeInfo->bankCount) {
+		return(MN_ERR_BADARG);
+	}
+	// Create shortcut to the proper parameter bank
+	pParamBank = &(pNodeInfo->paramBankList)[coreParam.fld.bank];
+	//
+	// Find out if this is a known or unknown parameter
+	//
+
+	if (coreParam.fld.param >= pParamBank->nParams
+	|| pParamBank->fixedInfoDB[coreParam.fld.param].info.paramType==PT_NONE) {
+		//
+		// If parameter is out of range don't update the paramDB, get
+		// a value to establish parameter size and pretend that it is an
+		// integer.
+		theErr = netGetParameter(theMultiAddr, theParam, &dummyBuf);
+		if (theErr == MN_OK)  {
+			// Read OK, assign set size to equal read size
+			pVal = &newParamValue;
+			pVal->raw.Byte.BufferSize = dummyBuf.Byte.BufferSize;
+			// Dummy up an information record for this parameter
+			pFixedInfoDB = &dummyInfo;
+			dummyInfo.info.paramSize = dummyBuf.Byte.BufferSize;	// Size from get
+			dummyInfo.info.paramType = PT_UNKNOWN;	// Unknown type
+			dummyInfo.info.unitType = NO_UNIT;		// No units
+			dummyInfo.info.reciprical = FALSE;		// Standard value
+			dummyInfo.info.scaleFromBase = 1;		// No scaling
+			dummyInfo.info.signextend = TRUE;		// Sign-extended
+			dummyInfo.info.descID = STR_UNKNOWN;	// Description
+			dummyInfo.converter = NULL;				// No converter
+		}
+		else {
+			// Nothing returned is meaningful, just error out
+			return(theErr);
+		}
+	}
+	else {
+		// Point at our parameter information to convert to bits
+		pFixedInfoDB = pParamBank->fixedInfoDB+coreParam.fld.param;
+		// Using the option bit?
+		if (!coreParam.fld.option)  {
+			// No, use the value database as the basis
+			pVal = pParamBank->valueDB + coreParam.fld.param;
+			// Save the old value
+//			oldValue = pVal->value;
+		}
+		else {
+			// Yes, dummy up the database entry for proper conversions
+			pVal = &newParamValue;
+			// Produce the callback for non-zero
+//			oldValue = -theValue;
+		}
+	}
+	//
+	// We have parameter specifics, now convert to buffer format
+	//
+	pVal->raw.Byte.BufferSize = pFixedInfoDB->info.paramSize;
+	// Set the proposed value in the database
+	pVal->value = theValue;
+	// Convert value to base unit in the "raw" buffer.
+	toBaseUnit(theMultiAddr, coreParam, pNodeInfo, pFixedInfoDB, pParamBank, pVal);
+	// Convert the "raw" base value to the standard display value
+	fromBaseUnit(theMultiAddr, coreParam, pNodeInfo, pFixedInfoDB, pParamBank, pVal);
+	//
+	// The buffer is now loaded, send it off to the node.
+	//
+	theErr = netSetParameter(theMultiAddr, theParam, &pVal->raw);
+	// Is there a registered callback and a value change or
+	// this is off the end of the parameter table.
+	if (theErr == MN_OK	|| (coreParam.fld.param > pParamBank->nParams)) {
+		// Mark value OK if we sent OK
+		pVal->exists = (theErr == MN_OK);
+		// Make copy of the value
+		newParamValue = *pVal;
+		paramChgObj.net = cNum;
+		paramChgObj.node = theMultiAddr;
+		paramChgObj.paramNum = coreParam.bits;
+		paramChgObj.newValue = newParamValue.value;
+		// Call the callback
+		infcFireParamCallback(pNodeInfo->pClassInfo->paramChngFunc,
+							  &paramChgObj);
+	}
+	else {
+		pVal->exists = FALSE;
+	}
+	return(theErr);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+ 
+/*****************************************************************************
+ *	NAME
+ *		toBaseUnit
+ *
+ *	DESCRIPTION:
+ *		Convert the paramValue's value member to a properly scaled unit
+ *		in the raw member's buffer.
+ *
+ *	SYNOPSIS: 															    */
+void toBaseUnit(
+	multiaddr theMultiAddr,					// Node address
+	appNodeParam appParam,				// parameter number of interest
+	byNodeDB *pNodeDB,					// ptr to this node's param data
+	paramInfoLcl const *pFixedInfoDB,	// Current parameter fixed info
+	paramBank *pBankInfo,				// Current bank
+	paramValue *userVal)				// user value in their unit
+{
+	double convVal;
+
+	// Custom converter defined?
+	if (pFixedInfoDB->converter != NULL)  {
+		// Yes, run it to convert the value member to "bits"
+		convVal =
+			(pFixedInfoDB->converter)(FALSE, theMultiAddr, appParam,
+									  userVal->value, pNodeDB);
+	}
+	else {
+		// Value requires no special conversions
+		convVal = userVal->value;
+	}
+	// Convert the "base" number in the value field to the "raw" value
+	coreDoubleToBuf(pFixedInfoDB, &userVal->raw, convVal);
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	NAME
+ *		fromBaseUnit
+ *
+ *	DESCRIPTION:
+ *		Convert the node's base unit value to the user's unit.
+ *
+ *	SYNOPSIS: 															    */
+void fromBaseUnit(
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam appParam,				// parameter number of interest
+	byNodeDB *pNodeDB,					// ptr to this node's param data
+	paramInfoLcl const *pFixedInfoDB,	// ptr to fixed info
+	paramBank *pBankInfo,				// ptr to current parameter bank
+	paramValue *pNodeVal)				// ptr to node's base value
+{
+	double pVal;
+
+	// Using a custom converter?
+	if (pFixedInfoDB->converter != NULL)  {
+		// Do base level conversion
+		pVal = coreBufToDouble(pFixedInfoDB, pNodeVal);
+		// Convert using base level conversion of buffer
+		pNodeVal->value = (pFixedInfoDB->converter)(TRUE, theMultiAddr, appParam,
+									                pVal, pNodeDB);
+		return;
+	}
+	else {
+		// Do base level conversion
+		pNodeVal->value = coreBufToDouble(pFixedInfoDB, pNodeVal);
+	}
+}
+//																			 *
+//****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME																	 *
+//		netEnterDataAcqMode
+//
+//	DESCRIPTION:
+//		Start a node's data acquisition mode.
+//
+//	RETURNS:
+//		cnErrCode, <startTime> set to node's time stamp at start of
+//		acquisition.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netEnterDataAcqMode(multiaddr theMultiAddr,
+												double *startTime)
+{
+	packetbuf theCmd, aResp;
+	double theSampPeriod;
+	cnErrCode theErr;
+
+	if (startTime==NULL)
+		return(MN_ERR_BADARG);
+	//#if TRACE_HIGH_LEVEL
+	//	_RPT2(_CRT_WARN, "%.1f netEnterDataAcqMode(%d)\n",
+	//					  infcCoreTime(), theMultiAddr);
+	//#endif
+	netGetParameterDbl(theMultiAddr,
+						MN_P_SAMPLE_PERIOD, &theSampPeriod);
+	// Remember sample rate for return data
+	infcInitDataAcq(theMultiAddr, theSampPeriod);
+
+	// Kill old data
+	infcFlushDataAcq(theMultiAddr);
+
+	// Build command
+	theCmd.Fld.Src = MN_SRC_HOST;
+	theCmd.Fld.PktType = MN_PKT_TYPE_CMD;
+	theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);
+	theCmd.Fld.PktLen = 2;
+	theCmd.Fld.Zero1 = theCmd.Fld.Mode = 0;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_DATA_ACQ ;
+	theCmd.Byte.Buffer[CMD_LOC+1] = SCP_DRATE;
+
+	// Expect a response - it is a timestamp
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &aResp);
+	if (theErr == MN_OK) {
+		*startTime = theSampPeriod*(*(nodeushort *)&aResp.Byte.Buffer[RESP_LOC]);
+	}
+	return(theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME																	 *
+//		netExitDataAcqMode
+//
+//	DESCRIPTION:
+//		Stop a node's data acquisition mode.
+//
+//	RETURNS:
+//		cnErrCode, <startTime> set to node's time stamp at start of
+//		acquisition.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netExitDataAcqMode(multiaddr theMultiAddr)
+{
+	packetbuf theCmd, aResp;
+
+	//#if TRACE_HIGH_LEVEL
+	//	_RPT2(_CRT_WARN, "%.1f netExitDataAcqMode(%d)\n",
+	//					  infcCoreTime(), theMultiAddr);
+	//#endif
+	theCmd.Fld.Src = MN_SRC_HOST;
+	theCmd.Fld.PktType = MN_PKT_TYPE_EXTEND_HIGH;
+	theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);
+	theCmd.Fld.PktLen = 2;
+	theCmd.Fld.Zero1 = theCmd.Fld.Mode = 0;
+	theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_DATA_ACQ;
+	theCmd.Byte.Buffer[CMD_LOC+1] = SCP_OFF;
+	return(netRunCommand(NET_NUM(theMultiAddr), &theCmd, &aResp));
+}
+//																			 *
+//****************************************************************************
+
+
+//****************************************************************************
+//	NAME
+//		netGetErrStats
+//
+//	DESCRIPTION:
+//		Get the network statistics for the specified node. The node's values
+//		are cleared upon execution.
+//
+//	RETURNS:
+//		cnErrCode, <netStats> updated
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetErrStats(
+	multiaddr theMultiAddr,
+	mnNetErrStats *pNetStats)
+{
+	cnErrCode theErr = MN_OK;
+
+	double theDbl;
+	mnParams appChksParam, appFragParam, appStrayParam, appOverrunParam;
+	mnParams diagChksParam, diagFragParam, diagStrayParam, diagOverrunParam;
+	mnParams netUnderVoltParam;
+
+	mnNetStatus netState;
+	theErr = netGetNodeAccessLvl(theMultiAddr, &netState);
+	// Get each diagnostic element from the node
+	switch(netState.Fld.NetParamVer) {
+	case 0:
+		appChksParam = MN_P_NETERR_APP_CHKSUM;
+		appFragParam = MN_P_NETERR_APP_FRAG;
+		appStrayParam = MN_P_NETERR_APP_STRAY;
+		appOverrunParam = MN_P_NETERR_APP_OVERRUN;
+		diagChksParam = MN_P_NETERR_DIAG_CHKSUM;
+		diagFragParam = MN_P_NETERR_DIAG_FRAG;
+		diagStrayParam = MN_P_NETERR_DIAG_STRAY;
+		diagOverrunParam = MN_P_NETERR_DIAG_OVERRUN;
+		netUnderVoltParam = MN_P_NETERR_LOW_VOLTS;
+		break;
+	default:
+		// Newer compact base parameter map
+		appChksParam = (mnParams)MN_P1_NETERR_APP_CHKSUM;
+		appFragParam = (mnParams)MN_P1_NETERR_APP_FRAG;
+		appStrayParam = (mnParams)MN_P1_NETERR_APP_STRAY;
+		appOverrunParam = (mnParams)MN_P1_NETERR_APP_OVERRUN;
+		diagChksParam = (mnParams)MN_P1_NETERR_DIAG_CHKSUM;
+		diagFragParam = (mnParams)MN_P1_NETERR_DIAG_FRAG;
+		diagStrayParam = (mnParams)MN_P1_NETERR_DIAG_STRAY;
+		diagOverrunParam = (mnParams)MN_P1_NETERR_DIAG_OVERRUN;
+		netUnderVoltParam = (mnParams)MN_P1_NETERR_LOW_VOLTS;
+		break;
+	}
+	// Application Port
+	theErr = netGetParameterDbl(theMultiAddr,
+								appChksParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->ApplicationPort.nChecksumBad=(nodeulong)theDbl;
+
+	theErr = netGetParameterDbl(theMultiAddr,
+								appFragParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->ApplicationPort.nFragPkts=(nodeulong)theDbl;
+
+	theErr = netGetParameterDbl(theMultiAddr,
+								appStrayParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->ApplicationPort.nStrayChars=(nodeulong)theDbl;
+
+	theErr = netGetParameterDbl(theMultiAddr,
+								appOverrunParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->ApplicationPort.nOverflows=(nodeulong)theDbl;
+
+
+	// Diagnostic Port
+	theErr = netGetParameterDbl(theMultiAddr,
+								diagChksParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->DiagnosticPort.nChecksumBad=(nodeulong)theDbl;
+
+	theErr = netGetParameterDbl(theMultiAddr,
+								diagFragParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->DiagnosticPort.nFragPkts=(nodeulong)theDbl;
+
+	theErr = netGetParameterDbl(theMultiAddr,
+								diagStrayParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->DiagnosticPort.nStrayChars=(nodeulong)theDbl;
+
+	theErr = netGetParameterDbl(theMultiAddr,
+								diagOverrunParam,&theDbl);
+	if(theErr != MN_OK)
+		return theErr;
+	pNetStats->DiagnosticPort.nOverflows=(nodeulong)theDbl;
+
+	// New items to try
+	nodeIDs thisNodeType = netGetDevType(theMultiAddr);
+	bool hasNetLowFeature = false;
+	switch(thisNodeType) {
+		case NODEID_MD:
+			theErr = netGetParameterDbl(theMultiAddr,
+										MN_P_FW_VERSION, &theDbl);
+			hasNetLowFeature = (theErr == MN_OK
+				&& (theDbl >= FW_MILESTONE_LINK_LOW));
+			break;
+		default:
+			hasNetLowFeature = true;
+			break;
+	}
+	// Get the accumlated counts
+	if (hasNetLowFeature) {
+		theErr = netGetParameterDbl(theMultiAddr,
+									netUnderVoltParam,&theDbl);
+		if (theErr == MN_OK)
+			pNetStats->LowPowerEvents = (nodeulong)theDbl;
+	}
+	else {
+		pNetStats->LowPowerEvents = 0;		// Assume zero
+	}
+
+	return(theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+
+//****************************************************************************
+//	NAME
+//		netRunNetDiag
+//
+//	DESCRIPTION:
+//		Run the network diagnostic function and accumulate data updating
+//		the user's <stats> buffer.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netDiagsRun(
+	netaddr cNum,
+	mnNetDiagResults *stats)
+{
+	unsigned i;
+	nodeulong nodesNow;
+	cnErrCode theErr = MN_OK;
+	mnNetDiagResult zeroes;
+
+	//if (!SysInventory.valid)
+	//	return(MN_ERR_PARAM_NOT_INIT);
+
+	// Read the results
+	//infcSetInitializeMode(cNum, TRUE, MN_OK);
+
+	// Record the time we read this stuff
+	NetDiags[cNum].sampleTime = infcCoreTime();
+	NetDiags[cNum].nSamples++;
+
+	// See if there are currently any nodes and if communications OK
+	nodesNow = 0;
+	theErr = infcProbeForOffline(cNum, &nodesNow);
+
+	// Detect if network is not online - exit
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+
+	// Query the diagnostic data from each node and interpret it properly
+	for (i=0; i<SysInventory[cNum].InventoryNow.NumOfNodes; i++) {
+		// Invalidate the results until analyzed
+		theErr = netGetErrStats(MULTI_ADDR(cNum,i), &NetDiags[cNum].node[i].lastErrs);
+		NetDiags[cNum].node[i].netOK = NET_TEST_UNTESTED;
+		if(theErr != MN_OK)
+			return(theErr);
+
+	}
+
+	// Zero out "off the net items"
+	for(i=SysInventory[cNum].InventoryNow.NumOfNodes; i<MN_API_MAX_NODES; i++) {
+		NetDiags[cNum].node[i] = zeroes;
+	}
+
+	// Accumulate and analyze the results
+	for (i=0; i<SysInventory[cNum].InventoryNow.NumOfNodes && SysInventory[cNum].InventoryNow.NumOfNodes>1; i++) {
+		if (NetDiags[cNum].node[i].collectCode == MN_OK) {
+			mnNetDiagResult	*mErr;
+			mErr = &NetDiags[cNum].node[i];
+			// Update the network problem statistics
+			mErr->accumErrs.ApplicationPort.nChecksumBad
+			+= mErr->lastErrs.ApplicationPort.nChecksumBad;
+			mErr->accumErrs.ApplicationPort.nFragPkts
+			+= mErr->lastErrs.ApplicationPort.nFragPkts;
+			mErr->accumErrs.ApplicationPort.nStrayChars
+			+= mErr->lastErrs.ApplicationPort.nStrayChars;
+			mErr->accumErrs.ApplicationPort.nOverflows
+			+= mErr->lastErrs.ApplicationPort.nOverflows;
+
+			mErr->accumErrs.DiagnosticPort.nChecksumBad
+			+= mErr->lastErrs.DiagnosticPort.nChecksumBad;
+			mErr->accumErrs.DiagnosticPort.nFragPkts
+			+= mErr->lastErrs.DiagnosticPort.nFragPkts;
+			mErr->accumErrs.DiagnosticPort.nStrayChars
+			+= mErr->lastErrs.DiagnosticPort.nStrayChars;
+			mErr->accumErrs.DiagnosticPort.nOverflows
+			+= mErr->lastErrs.DiagnosticPort.nOverflows;
+			mErr->accumErrs.LowPowerEvents += mErr->lastErrs.LowPowerEvents;
+
+			// Mark as problem if we see too many frags or strays
+			if (mErr->accumErrs.ApplicationPort.nChecksumBad > NET_CHECKSUMS_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.ApplicationPort.nFragPkts > NET_FRAGS_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.ApplicationPort.nStrayChars > NET_STRAYS_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.ApplicationPort.nOverflows > NET_OVERRUN_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+
+			if (mErr->accumErrs.DiagnosticPort.nChecksumBad > NET_CHECKSUMS_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.DiagnosticPort.nFragPkts > NET_FRAGS_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.DiagnosticPort.nStrayChars > NET_STRAYS_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.DiagnosticPort.nOverflows > NET_OVERRUN_BAD)
+				mErr->netOK = NET_TEST_FAILED;
+			if (mErr->accumErrs.LowPowerEvents > 1)
+				mErr->netOK = NET_TEST_FAILED;
+
+			// If we didn't detect any problems set the node state to PASSED
+			if (mErr->netOK == NET_TEST_UNTESTED)
+				mErr->netOK = NET_TEST_PASSED;
+		}
+	}
+	// Return results if they want them
+	if (stats != NULL) {
+		*stats = NetDiags[cNum];
+	}
+
+	if (theErr != MN_OK) {
+		return(theErr);
+	}
+	//infcSetInitializeMode(cNum, FALSE, theErr);
+	return(theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+
+
+
+//****************************************************************************
+//	NAME
+//		netDiagsGet
+//
+//	DESCRIPTION:
+//		Return the driver's network diagnostics data.
+//
+//	RETURNS:
+//		cnErrCode, *stats updated with driver state
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netDiagsGet(netaddr cNum,
+    mnNetDiagResults *pStats)
+{
+	_RPT1(_CRT_WARN, "sizeof(mnNetDiagResults)=%ld\n", sizeof(mnNetDiagResults));
+	*pStats = NetDiags[cNum];
+	return(MN_OK);
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		netDiagsClr
+//
+//	DESCRIPTION:
+//		Clear the accumulated network diagnostic information.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netDiagsClr(
+	netaddr cNum)
+{
+	unsigned i;
+	mnNetDiagResult zeroes;
+
+	for (i=0; i<MN_API_MAX_NODES; i++) {
+		NetDiags[cNum].node[i] = zeroes;
+	}
+	NetDiags[cNum].startTime = infcCoreTime();
+	NetDiags[cNum].sampleTime = NetDiags[cNum].startTime;
+	NetDiags[cNum].nSamples = 0;
+	return(MN_OK);
+}
+/****************************************************************************/
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		coreFreeAllNodeInfo
+//
+//	DESCRIPTION:
+//		Return the entire node information DB for this net.
+//
+//	SYNOPSIS:
+void coreFreeAllNodeInfo(netaddr cNum)
+{
+	unsigned nodeAddr;
+
+#if TRACE_HEAP
+	infcHeapCheck("coreFreeAllNodeInfo start");
+#endif
+
+	for (nodeAddr=0 ; nodeAddr<MN_API_MAX_NODES ; nodeAddr++) {
+		//WCHAR foo[200];
+		byNodeDB *pNodeDB = &SysInventory[cNum].NodeInfo[nodeAddr];
+		if (pNodeDB->delFunc) {
+			//wsprintf(foo,L"coreFreeAllNodeInfo net %d node %d\n", cNum, nodeAddr);
+			//OutputDebugString(foo);
+			(*pNodeDB->delFunc)(MULTI_ADDR(cNum, nodeAddr));
+		}
+	}
+#if TRACE_HEAP
+	infcHeapCheck("coreFreeAllNodeInfo exit");
+#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+/*****************************************************************************
+ *	NAME
+ *		coreInvalidateValCache
+ *
+ *	DESCRIPTION:
+ *		Invalidate all the value cache items for this controller
+ *
+ *	SYNOPSIS: 															    */
+void coreInvalidateValCache(netaddr cNum)
+{
+	unsigned nodeAddr;
+
+	for (nodeAddr=0 ; nodeAddr<MN_API_MAX_NODES ; nodeAddr++) {
+            coreInvalidateValCacheByNode(cNum, nodeAddr);
+	}
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	NAME
+ *		coreInvalidateValCacheByNode
+ *
+ *	DESCRIPTION:
+ *		Invalidate all the value cache items for a particular node
+ *
+ *	SYNOPSIS: 															    */
+void coreInvalidateValCacheByNode(netaddr cNum, nodeaddr nodeAddr)
+{
+	unsigned bank, param;
+	paramBank *pBank;
+
+        for (bank=0; bank < SysInventory[cNum].NodeInfo[nodeAddr].bankCount; bank++) {
+            pBank = &SysInventory[cNum].NodeInfo[nodeAddr].paramBankList[bank];
+			for (param=0; pBank && param < pBank->nParams; param++) {
+				if (pBank && pBank->valueDB) {
+					pBank->valueDB[param].exists = FALSE;
+					pBank->valueDB[param].value = 0;
+				}
+            }
+        }
+}
+/*																 !end!		*/
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		netClrParamCache
+//
+//	DESCRIPTION:
+//		Invalidate the parameter cache for this node and parameter. This will
+//		cause the driver to re-read the value on the next get parameter
+//		 request.
+//
+//	RETURNS:
+//		#cnErrCode: MN_OK on success, otherwise a specific error
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netClrParamCache(
+	multiaddr theMultiAddr,
+	mnParams parameter)
+{
+	paramBank *pBank;
+	appNodeParam pCrack;
+
+	pCrack.bits = parameter;
+
+	netaddr cNum = coreController(theMultiAddr);
+	nodeaddr nodeAddr = NODE_ADDR(theMultiAddr);
+
+	// Is the address ok for this net
+	if (nodeAddr >= SysInventory[cNum].InventoryNow.NumOfNodes)
+		return(MN_ERR_PARAM_RANGE);
+
+	// Param out of range?
+	if (pCrack.fld.bank > SysInventory[cNum].NodeInfo[nodeAddr].bankCount)
+		return(MN_ERR_PARAM_RANGE);
+
+	// Get bank list for this parameter
+	pBank = &SysInventory[cNum].NodeInfo[nodeAddr].paramBankList[pCrack.fld.bank];
+
+	// Param out of range?
+	if (!pBank || pBank->nParams <= pCrack.fld.param)
+		return(MN_ERR_PARAM_RANGE);
+
+	// Kill the cached value and mark as unread
+	pBank->valueDB[pCrack.fld.param].exists = FALSE;
+	pBank->valueDB[pCrack.fld.param].value = 0;
+
+	return(MN_OK);
+}
+/****************************************************************************/
+
+
+
+//****************************************************************************
+//	NAME
+//		coreSetParamFromBytes
+//
+//	DESCRIPTION:
+//		Set the parameter database as though the SetParameter was run using
+//		the specified value byte string <pVal>.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode coreSetParamFromBytes(multiaddr theMultiAddr,
+								 nodeparam paramNum,
+								 nodeuchar *pVal,
+								 unsigned sizeInBytes)
+{
+	cnErrCode theErr = MN_OK;
+	netaddr cNum;
+	paramValue *pTheVal,uVal;			// Ptr to current value item
+	double oldValue;
+	mnParamChg paramChgObj;				// Parameter change object
+	appNodeParam coreParam;				// Parameter cracker
+	byNodeDB *pNodeInfo;				// Node Data
+	paramBank *pParamBank;				// Current parameter bank
+	paramInfoLcl const *pFixedInfoDB;	// Current parameter fixed info
+
+	// Get node number and current controller
+	cNum = coreController(theMultiAddr);
+	// Bail if port closed/offline
+	netStateInfo *pNCS = SysInventory[cNum].pNCS;
+	if (!pNCS || !(pNCS->pSerialPort) || !pNCS->pSerialPort->IsOpen())
+		return(MN_ERR_CLOSED);
+	pNodeInfo = &SysInventory[cNum].NodeInfo[NODE_ADDR(theMultiAddr)];
+	if (pNodeInfo == NULL || pNodeInfo->paramBankList == NULL)
+		return MN_ERR_PARAM_NOT_INIT;
+	coreParam.bits = paramNum;
+	if (pNodeInfo->bankCount <= coreParam.fld.bank)
+		return MN_ERR_PARAM_RANGE;
+	// Shortcut to the parameter bank
+	pParamBank = pNodeInfo->paramBankList + coreParam.fld.bank;
+	// Calc ptr to value area
+	pTheVal = &pParamBank->valueDB[coreParam.fld.param];
+	pFixedInfoDB = &pParamBank->fixedInfoDB[coreParam.fld.param];
+	oldValue = pTheVal->value;
+	// Update the raw information area
+	cpymem(pVal, (nodeuchar *)&pTheVal->raw.Byte.Buffer[0], sizeInBytes);
+	pTheVal->raw.Byte.BufferSize = sizeInBytes;
+	fromBaseUnit(theMultiAddr, coreParam, pNodeInfo,
+			   pFixedInfoDB, pParamBank, pTheVal);
+	// Register the change
+	if (oldValue != pTheVal->value
+	   || ((pFixedInfoDB->info.paramType & PT_CLR)
+		   && (pTheVal->value != 0))) {
+		uVal = *pTheVal;
+		// Call the user callback
+		paramChgObj.node = theMultiAddr;
+		paramChgObj.net = cNum;
+		paramChgObj.paramNum = paramNum;
+		paramChgObj.newValue = uVal.value;
+		infcFireParamCallback(pNodeInfo->pClassInfo->paramChngFunc,
+							  &paramChgObj);
+		// If clear-on-read, kill the old value
+		if (pFixedInfoDB->info.paramType & PT_CLR)
+			pTheVal->value = 0;
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+/*  C O M M O N    C O N V E R T E R S   								   */
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+
+//****************************************************************************
+//	NAME
+//		coreBaseGetParameterInt
+//
+//	DESCRIPTION:
+//		Get a 16-bit parameter using just base commands. This function only
+//		works when the read thread is not running.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode coreBaseGetParameterInt(netaddr cNum, nodeaddr theNode,
+								  nodeparam paramNum, Uint16 * pVal)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+
+	#if MN_PKT_TYPE_CMD!=0
+	#error "assumption on ADDR_LOC not true"
+	#endif
+
+	theCmd.Byte.BufferSize = 4;
+	theCmd.Byte.Buffer[ADDR_LOC] = 0;
+	theCmd.Byte.Buffer[LEN_LOC] = 0;
+	theCmd.Fld.Addr = theNode;
+	theCmd.Fld.PktLen = 2;
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_GET_PARAM0;
+	theCmd.Byte.Buffer[CMD_LOC+1] = (nodechar)paramNum;
+	//theErr = infcRunCommandRaw(cNum, &theCmd, &theResp);
+	theErr = infcRunCommand(cNum, &theCmd, &theResp);
+	if (theErr == MN_OK)  {
+		*pVal = *(nodeshort *)&theResp.Byte.Buffer[RESP_LOC] & 0xFFFF;
+	}
+	return(theErr);
+}
+cnErrCode coreBaseGetParameterLong(netaddr cNum, nodeaddr theNode,
+								  nodeparam paramNum, int *pVal)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+
+	#if MN_PKT_TYPE_CMD!=0
+	#error "assumption on ADDR_LOC not true"
+	#endif
+
+	theCmd.Byte.BufferSize = 4;
+	theCmd.Byte.Buffer[ADDR_LOC] = 0;
+	theCmd.Byte.Buffer[LEN_LOC] = 0;
+	theCmd.Fld.Addr = theNode;
+	theCmd.Fld.PktLen = 2;
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_GET_PARAM0;
+	theCmd.Byte.Buffer[CMD_LOC+1] = (nodechar)paramNum;
+//	theErr = infcRunCommandRaw(cNum, &theCmd, &theResp);
+	theErr = infcRunCommand(cNum, &theCmd, &theResp);
+	if (theErr == MN_OK)  {
+		*pVal = *(nodelong *)&theResp.Byte.Buffer[RESP_LOC] & 0xFFFFFFFF;
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+
+//****************************************************************************
+//	NAME
+//		coreBaseSetParameterInt
+//
+//	DESCRIPTION:
+//		Set a 16-bit parameter using just base commands. This function only
+//		works when the read thread is not running.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode coreBaseSetParameterInt(netaddr cNum, nodeaddr theNode,
+								  nodeparam paramNum, int pVal)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr = MN_OK;
+
+	#if MN_PKT_TYPE_CMD!=0
+	#error "assumption on ADDR_LOC not true"
+	#endif
+
+	theCmd.Byte.BufferSize = 6;
+	theCmd.Byte.Buffer[ADDR_LOC] = 0;
+	theCmd.Byte.Buffer[LEN_LOC] = 0;
+	theCmd.Fld.Addr = theNode;
+	theCmd.Fld.PktLen = 4;
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_SET_PARAM0;
+	theCmd.Byte.Buffer[CMD_LOC+1] = (nodechar)paramNum;
+	theCmd.Byte.Buffer[CMD_LOC+2] = pVal & 0xff;
+	theCmd.Byte.Buffer[CMD_LOC+3] = (pVal>>8) & 0xff;
+	//theErr = infcRunCommandRaw(cNum, &theCmd, &theResp);
+	theErr = infcRunCommand(cNum, &theCmd, &theResp);
+	if (theErr == MN_OK)  {
+		theErr = coreGenErrCode(cNum, &theResp, theResp.Fld.Addr);
+	}
+	return(theErr);
+}
+/****************************************************************************/
+
+
+//****************************************************************************
+//	NAME
+//		coreInitializeEx
+//
+//	DESCRIPTION:
+//		Perform common initializing functions for the specified node class.
+//
+//	RETURNS:
+//		cnErrCode
+//
+//	SYNOPSIS:
+cnErrCode MN_DECL coreInitializeEx(
+		multiaddr theMultiAddr,
+		nodebool warmInitialize,
+		coreParamSetupFuncPtr classSetupFunc)
+{
+	cnErrCode errRet = MN_OK;
+	netaddr cNum = NET_NUM(theMultiAddr);
+
+	#if TRACE_HIGH_LEVEL&0
+	_RPT2(_CRT_WARN, "%.1f coreInitializeEx(%d)\n",
+			infcCoreTime(), theMultiAddr);
+	#endif
+
+	//
+	// Wait for commands to sync in this thread, if we are talking on the net
+	//
+	infcWaitForNetStop(cNum);
+
+	// Signal we are initializing
+	infcSetInitializeMode(cNum, TRUE, MN_OK);
+
+	infcFireNetEvent(cNum, NODES_SENDING);
+
+	// Setup the node
+	errRet = (*classSetupFunc)(theMultiAddr);
+	// Relieve another init count / this error
+	infcSetInitializeMode(cNum, FALSE, errRet);
+	return(errRet);
+}
+/****************************************************************************/
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netAlertLogEpoch
+//
+//	DESCRIPTION:
+///		Setup the node's Alert epoch entry to the current system time.
+///
+/// 	\param[in] theMultiAddr The address code for this node.
+///		\return description
+///
+/// 	Detailed description.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netAlertLogEpoch(
+		multiaddr theMultiAddr)		// Node address
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+	time_t timeNowZ;				// Current time in UTC
+	time_t *pktTime
+		= reinterpret_cast<time_t *>(&theCmd.Byte.Buffer[CMD_LOC+1]);
+
+	time(&timeNowZ);
+
+	// Convert to Merdian epoch
+	timeNowZ = MERIDIAN_EPOCH_CTIME - timeNowZ;
+
+	// Start with basic command
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_CMD, NODE_ADDR(theMultiAddr), MN_SRC_HOST);
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_ALERT_LOG;
+	// Signal epoch adjust by sending 4 octets
+	theCmd.Fld.PktLen = 4;
+	// Copy our epoch adjustment
+	*pktTime = timeNowZ;
+	// Run it
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp);
+	// Send to node and wait for null response.
+	if (theErr == MN_OK) {
+		// Should return null packet
+		if (theResp.Fld.PktLen)
+			return(MN_ERR_RESP_FMT);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+/// \endcond
+
+// =============================================================================
+// DOCUMENTED FUNCTIONS BELOW HERE
+// =============================================================================
+
+/**
+	\addtogroup LinkGrp
+	@{
+**/
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetParameter
+//
+//	DESCRIPTION:
+/**
+	This function will get the bit-oriented parameter specified by \a
+	theParamNum on device \a theMultiAddr. The parameter is returned in the
+	buffer pointed to by \a paramInfo. The actual length and information
+	will be updated when this function returns MN_OK.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParamNum The parameter code number for retrieval.
+	\param[out] pParamBuf Ptr to result area
+
+	\return	MN_OK if the parameter was retrieved and the \p pParamBuf
+
+	\see mnSysInventoryRecord function
+	\see MULTI_ADDR macro
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetParameter(
+		multiaddr theMultiAddr, 			// device address
+		nodeparam theParamNum,		// parameter index
+		packetbuf *pParamBuf)		// ptr for returned param
+
+{
+	packetbuf cmd,resp;				// Input and output buffers
+	cnErrCode theErr;
+	netaddr cNum;
+
+	cNum = coreController(theMultiAddr);
+
+	if ((theErr = netGetParameterFmt(&cmd, NODE_ADDR(theMultiAddr), theParamNum)) == MN_OK)  {
+		if ((theErr = netRunCommand(cNum, &cmd, &resp)) == MN_OK)  {
+			theErr = netGetParameterExtract(&resp, pParamBuf);
+		}
+		else {
+			pParamBuf->Fld.PktLen = 0;
+			pParamBuf->Byte.BufferSize = 0;
+		}
+	}
+#if _DEBUG
+	if (theErr != MN_OK) {
+			_RPT3(_CRT_WARN,
+				"netGetParameter(multiaddr=%d,param=%d failed: 0x%X\n",
+				theMultiAddr, theParamNum, theErr);	
+			DUMP_PKT(cNum, "...the cmd", &cmd);
+	}
+#endif
+	return theErr;
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netSetParameter
+//
+//	DESCRIPTION:
+/**
+	This function will run the set parameter command for device \a theMultiAddr
+	at parameter index \a theParamNum. The parameter value is defined in the
+	\a paramInfo area and the \a paramSize field defines the actual size.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] theParamNum The parameter code number for retrieval.
+	\param[in] pNewValue Bit-oriented area that will be sent to node to update
+			   the parameter.
+
+	\return MN_OK if the value was successfully updated.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netSetParameter(
+		multiaddr theMultiAddr, 			// node address
+		nodeparam theParamNum, 		// parameter index
+		packetbuf *pNewValue)		// ptr to new parameter data
+{
+	packetbuf theCmd;
+	cnErrCode theErr;
+	netaddr cNum;
+	packetbuf theResp;
+	nodeaddr respAddr;
+	cNum = coreController(theMultiAddr);
+
+	if ((theErr = netSetParameterFmt(&theCmd,
+								     NODE_ADDR(theMultiAddr),
+								     theParamNum,
+								     pNewValue)) == MN_OK) {
+		theErr = netRunCommand(cNum, &theCmd, &theResp);
+		if(theErr == MN_OK) {	// Figure out if return is
+			respAddr = theResp.Fld.Addr;
+			theErr= coreGenErrCode(cNum, &theResp, respAddr);
+		}
+	}
+#if _DEBUG	
+	if (theErr != MN_OK) {
+		_RPT3(_CRT_WARN,
+			"netSetParameter(multiaddr=%d,param=%d) failed: 0x%X\n",
+			theMultiAddr, theParamNum, theErr);	
+		DUMP_PKT(cNum, "..the cmd: ", &theCmd);
+	}
+#endif
+	return (theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netGetPartNumber
+//
+//	DESCRIPTION:
+/**
+	This function will fill the user's buffer with the addressed node's
+	part number.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param partNumBuf Ptr to response are
+	\param maxBufSize size of the \p paramNumBuf
+
+	\return MN_OK if the \p paramNumBuf is updated from the node.
+**/
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetPartNumber(
+	multiaddr theMultiAddr,
+	char *partNumBuf,
+	Uint16 maxBufSize)
+{
+	cnErrCode theErr;
+	unsigned i, nChars;
+	int nVerChars;
+	paramValue versionCode, options, partNum;
+	const unsigned verStrMax = 15;
+	char verStr[verStrMax];
+	optionReg opts;
+
+	// Get version code
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_FW_VERSION, NULL, &versionCode);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// Get this device's option register
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_OPTION_REG, NULL, &options);
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// Get the part number information
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_PART_NUM, NULL, &partNum);
+
+	if (theErr == MN_OK) {
+		// Limit return size to buffer size
+		nChars = (partNum.raw.Byte.BufferSize < maxBufSize)
+			? partNum.raw.Byte.BufferSize : maxBufSize;
+		// Copy and test characters for sanity until end of string
+		for (i=0; i<nChars && partNum.raw.Byte.Buffer[i]; i++) {
+			// Make sure we are ANSI like
+			if (partNum.raw.Byte.Buffer[i] > 127
+			|| partNum.raw.Byte.Buffer[i] < ' ') {
+				strncpy(partNumBuf, "N/A", maxBufSize);
+				return(MN_OK);
+			}
+			partNumBuf[i] = partNum.raw.Byte.Buffer[i];
+		}
+		// Save as the exit location
+		nChars = i;
+		// Make <partNum>-
+		if (nChars<maxBufSize) {
+			partNumBuf[nChars++] = '-';
+		}
+		// Create version string
+		versID_t verCracker;
+		verCracker.verCode = (Uint16)versionCode.value;
+		opts.bits = (unsigned)options.value;
+		if(opts.DrvFld.FWverMask) {
+			nVerChars = sprintf(verStr, "%d-%d-D", verCracker.fld.majorVers,
+													verCracker.fld.minorVers)+1;
+		} else {
+			nVerChars = sprintf(verStr, "%d-%d-%d", verCracker.fld.majorVers,
+													verCracker.fld.minorVers,
+													verCracker.fld.buildVers)+1;
+		}
+		// Insure it will fit
+		if ((nVerChars+nChars)>maxBufSize)
+			nVerChars = maxBufSize-nChars;		// Rest of buffer
+		if (nVerChars > 0) {
+			// Append to base part
+			strncpy(&partNumBuf[nChars], verStr, nVerChars);
+		}
+		// Insure string terminated even if truncated
+		partNumBuf[maxBufSize-1] = 0;
+	}
+	else {
+		partNumBuf[0] = 0;
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netNodeStop
+//
+//	DESCRIPTION:
+/**
+	For broadcast style usage:
+	- the stopType is inspected and if not STOP_TYPE_IGNORE the
+	short form high priority packet is sent forcing the node to use
+	it's default stop type upon command reception. The network is
+	derived from the the \a theMultiAddr argument and the node address
+	is ignored. Therefore the address of any node on that
+	network can be used as the argument.
+	.
+
+	For addressed
+	- Run the specified \a stopType on the addressed node.
+	.
+
+	To clear an existing node stop condition such as E-Stop, the
+	clear type must be specified with the modifier bits set for
+	the condition you want to clear.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] stopType Stopping strategy
+	\param[in] broadcast Send to all nodes, the address is ignored in this mode.
+
+	\return MN_OK when the node stop has been received by all the nodes.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netNodeStop(
+		multiaddr theMultiAddr, 	// node address/net
+		mgNodeStopReg stopType,		// stop strategy
+		nodebool broadcast)			// Send as high prio-broadcast
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+	netaddr cNum;
+	cNum = coreController(theMultiAddr);
+	if (!broadcast) {
+		// Send via regular command
+		theCmd.Fld.Addr = NODE_ADDR(theMultiAddr);
+		theCmd.Fld.PktLen = 2;
+		theCmd.Byte.Buffer[CMD_LOC] = ISC_CMD_NODE_STOP;
+		theCmd.Byte.Buffer[CMD_LOC+1] = nodechar(stopType.bits);
+
+		theErr = netRunCommand(cNum, &theCmd, &theResp);
+	}
+	else {
+		// Send via a high-priority packet
+
+		// Setup hi-prio pkt and user 0 address for now
+		theCmd.Fld.SetupHdr(MN_PKT_TYPE_EXTEND_HIGH, 0);
+		// Signal this is broadcast
+		theCmd.Fld.Mode = 1;
+		theCmd.Byte.Buffer[CMD_LOC] = MN_CTL_EXT_NODE_STOP;
+		theCmd.Byte.Buffer[CMD_LOC+1] = nodechar(stopType.bits);
+		// If stop type is zero, force the default stop type
+		if (stopType.bits == STOP_TYPE_IGNORE) {
+			theCmd.Fld.PktLen = 1;
+		}
+		else {
+			theCmd.Fld.PktLen = 2;
+		}
+		// Setup for low level command
+		theCmd.Byte.BufferSize = theCmd.Fld.PktLen + MN_API_PACKET_HDR_LEN;
+		// Run via low level command interface to avoid changing to
+		// straight command.
+		theErr = infcRunCommand(cNum, &theCmd, &theResp);
+		// We should get back what we sent.
+		if (theErr != MN_OK ||
+		    (theResp.Byte.Buffer[0] != theCmd.Byte.Buffer[0])
+		||  (theResp.Byte.Buffer[1] != theCmd.Byte.Buffer[1])
+		||  (theResp.Byte.Buffer[2] != theCmd.Byte.Buffer[2])
+		||  (theCmd.Fld.PktLen == 2
+				&& theResp.Byte.Buffer[3] != theCmd.Byte.Buffer[3]))
+			return(MN_ERR_RESP_FMT);
+	}
+	return (theErr);
+}
+//																		      *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netTrigger
+//
+//	DESCRIPTION:
+/**
+	Send a <i>Trigger</i> control packet through the network.  If \a usingGroup is
+	false, only the node with a matching address will interpret
+	the <i>Trigger Event</i>.  Otherwise the address signifies a group trigger, and
+	in this case the address field is interpreted as the group ID.
+
+	The group ID of zero cannot be assigned to any node and therefore will not
+	cause a trigger.
+
+	\param cNum Channel number to restart. The first channel is zero.
+	\param nodeOrGroupAddr Depending on the \a usingGroup setting, this is
+				the group number of the node address on the channel.
+	\param usingGroup Specifies the meaning of the \a nodeOrGroupAddr field.
+
+	\return #cnErrCode; MN_OK when the network has finished triggering.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netTrigger(
+		netaddr cNum,				// Net number
+		nodeaddr nodeOrGroupAddr,	// Node or Group Addr
+		nodebool usingGroup)		// Node(s) selection(s)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	// Build the packet
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_TRIGGER, nodeOrGroupAddr);
+	theCmd.Fld.PktLen = 0;
+	theCmd.Byte.BufferSize = 2;
+	// Pkt mode indicates group trigger
+	theCmd.Fld.Mode = usingGroup;
+
+	// Send the packet and check for correct response
+	theErr = infcRunCommand(cNum, &theCmd, &theResp);
+	if (theErr == MN_OK && (theResp.Fld.PktType != MN_PKT_TYPE_TRIGGER))
+			return(MN_ERR_RESP_FMT);
+	return (theErr);
+}
+//																			 *
+//****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netAlertLogClear
+//
+//	DESCRIPTION:
+///		Clear the entries out of node's alert log.
+///
+/// 	\param[in] theMultiAddr The address code for this node.
+///		\return MN_OK if the value was successfully updated.
+//
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netAlertLogClear(
+		multiaddr theMultiAddr)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	// Start with basic command
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_CMD, NODE_ADDR(theMultiAddr), MN_SRC_HOST);
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_ALERT_LOG;
+	theCmd.Byte.Buffer[CMD_LOC+1] = (nodechar)ALERT_ARG_CLEAR;
+	theCmd.Fld.PktLen = 2;
+
+	// Run it
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp);
+	if (theErr == MN_OK) {
+		// Should return null packet
+		if (theResp.Fld.PktLen)
+			return(MN_ERR_RESP_FMT);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netAlertLogGet
+//
+//	DESCRIPTION:
+///		Get the next newest, or the oldest, if \p restart is true, Alert log
+///		entry.
+///
+/// 	\param theMultiAddr
+///				target net/node
+/// 	\param restart
+///				set true to get oldest item.
+/// 	\param pEntryExists
+///				set true if the entry has been update in pEntry.
+/// 	\param pEntry
+///				updated with first/next entry if pEntryExists was true.
+///
+///		\return MN_OK if the entry was successfully retrieved.
+///
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netAlertLogGet(
+		multiaddr theMultiAddr,					// Node address
+		nodebool restart,						// Restart the list from oldest
+		nodebool *pEntryExists,					// Updated with TRUE if <pEntry> OK
+		alertLogEntry *pEntry)					// Update user's buffer
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	// No crashes by us
+	if (!pEntryExists || !pEntry)
+		return(MN_ERR_BADARG);
+	// Assume failure until proven OK
+	*pEntryExists = FALSE;
+
+	// Start with basic command
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_CMD, NODE_ADDR(theMultiAddr), MN_SRC_HOST);
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_ALERT_LOG;
+	theCmd.Byte.Buffer[CMD_LOC+1] = ALERT_ARG_GET_OLDEST;
+	// If they want reset, send the "arg", else send "null" arg
+	theCmd.Fld.PktLen = restart ? 2 : 1;
+
+	// Run it
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp);
+	if (theErr == MN_OK) {
+		// Did the log change since last read?
+		if (theResp.Fld.PktLen == 1 && theResp.Byte.Buffer[RESP_LOC] == 0)
+			return(MN_ERR_LOG_CHANGED);
+
+		// If we have a response, it must be 5 octets long (time stamp + code)
+		*pEntryExists = theResp.Fld.PktLen == 5;
+		if (*pEntryExists) {
+			alertLogEntry *pAlert = reinterpret_cast<alertLogEntry *>
+										(&theResp.Byte.Buffer[RESP_LOC]);
+
+			// Clear MSBs to convert nodechar to enum
+			theResp.Byte.Buffer[RESP_LOC+5] = 0;
+			theResp.Byte.Buffer[RESP_LOC+6] = 0;
+			theResp.Byte.Buffer[RESP_LOC+7] = 0;
+
+			if (pAlert->Reason == ALERT_LOG_EPOCH_CODE){
+				//TODO: Need to check MSB of timestamp to determine what
+				//type it is; currently, only the restart-initiated epoch
+				//type has been implemented; we still need to handle the
+				//user-defined epoch type!!
+
+				// Adjust the timestamp to clear out the user-defined epoch
+				// type flag
+				pAlert->Timestamp *= 2;
+			}
+
+			// Copy to user's buffer and clean up
+			*pEntry = *pAlert;
+		}
+		// Or NULL response if we have read them all
+		else if(theResp.Fld.PktLen!=0) {
+			return(MN_ERR_RESP_FMT);
+		}
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netAlertClear
+//
+//	DESCRIPTION:
+///		Clear and/or acknowledge items from the Alert Register. Serious
+///		errors cannot be cleared via this mechanism.
+///
+///		\param[in] theMultiAddr The address code for this node.
+///
+///		\return MN_OK if the log was cleared.
+///
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netAlertClear(
+		multiaddr theMultiAddr)
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	// Start with basic command
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_CMD, NODE_ADDR(theMultiAddr), MN_SRC_HOST);
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_ALERT_CLR;
+	theCmd.Fld.PktLen = 1;
+
+	// Run it
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp);
+	if (theErr == MN_OK) {
+		// Should return null packet
+		if (theResp.Fld.PktLen)
+			return(MN_ERR_RESP_FMT);
+	}
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetAlertReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Alert Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAlertReg Ptr to result area.
+
+	\return
+		cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetAlertReg(
+			multiaddr theMultiAddr,			// Node address
+			alertReg *pAlertReg)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_ALERT_REG, NULL, &paramVal);
+	*pAlertReg = *((alertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetWarnReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the Warning Register.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pWarningReg Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetWarnReg(
+			multiaddr theMultiAddr,			// Node address
+			alertReg *pWarningReg)			// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+	// Check parameter location
+
+	nodeIDs theNodeType = netGetDevType(theMultiAddr);
+	if (theNodeType == NODEID_MD)
+		theErr = netGetParameterInfo(theMultiAddr, MN_P_WARN_REG,
+									NULL, &paramVal);
+	else
+		theErr = netGetParameterInfo(theMultiAddr, (mnParams)MN_P1_WARN_REG,
+									NULL, &paramVal);
+
+	*pWarningReg = *((alertReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetStatusRTReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the <i>Status Real-Time Register</i>.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pReg Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetStatusRTReg(
+			multiaddr theMultiAddr,			// Node address
+			mnStatusReg *pReg)				// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_STATUS_RT_REG,
+									NULL, &paramVal);
+	*pReg = *((mnStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetAttnStatusRiseReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the <i>Status Attn/Rise Register</i>.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pReg Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetAttnStatusRiseReg(
+			multiaddr theMultiAddr,			// Node address
+			mnStatusReg *pReg)				// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_STATUS_ATTN_RISE_REG,
+									NULL, &paramVal);
+	*pReg = *((mnStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetStatusAccumReg
+//
+//	DESCRIPTION:
+/**
+	Get the current state of the <i>Status Accumulating Register</i>.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pReg Ptr to result area.
+
+	\return
+		#cnErrCode; MN_OK if successful
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetStatusAccumReg(
+			multiaddr theMultiAddr,			// Node address
+			mnStatusReg *pReg)				// Current setting
+{
+	cnErrCode theErr;
+	paramValue paramVal;
+
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_STATUS_ACCUM_REG,
+									NULL, &paramVal);
+	*pReg = *((mnStatusReg *)&paramVal.raw.Byte.Buffer[0]);
+	return(theErr);
+}
+//																			   *
+//******************************************************************************
+
+
+
+//******************************************************************************
+// NAME																		   *
+//		netGetDevType
+//
+//	DESCRIPTION:
+/**
+	Return the device type of the specified node \a theMultiAddr.
+
+	\param[in] theMultiAddr The address code for this node.
+
+	\return
+		Specified device type
+**/
+//	SYNOPSIS:
+MN_EXPORT nodeIDs MN_DECL netGetDevType(
+		multiaddr theMultiAddr)
+{
+	netaddr cNum = NET_NUM(theMultiAddr);
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return NODEID_UNK;
+
+	return((nodeIDs)SysInventory[cNum].NodeInfo
+							[NODE_ADDR(theMultiAddr)].theID.fld.devType);
+}
+//																			   *
+//******************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		netGetDataCollected
+//
+//	DESCRIPTION:
+/**		
+	Return consolidated motion quality data. 
+
+	This command will return a consolidated set of data related to 
+	the monitor port variable as well as motion tracking. The node collects
+	mean squared low and high pass data as well as the maximum low pass value 
+	encountered	since the last command request.	 The motion tracking collects
+	the maximum negative and positive tracking from the command.
+	
+	The tracking data is collected from the last query or only collected
+	during the last move depending on settings in the #iscTuneConfigReg register.
+
+	\remark In the "by-move" mode, the values returned are always from the 
+	last completed move. This will allow double-buffered collection for moves
+	who's durations are longer than the request delay.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pReturnData Pointer to a \a pReturnData structure to return
+		the collected data.
+
+	\return
+		#cnErrCode; MN_OK if successful and all data has been updated.
+		MN_ERR_PARAM_RANGE if motion was too long of there was overflow
+		detected on a parameter return. 
+
+	\see #iscTuneConfigReg for detailed field defintions.
+ 
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netGetDataCollected(
+			multiaddr theMultiAddr,			// Destination node
+			iscDataCollect *pReturnData)	// Returned data
+{
+	packetbuf cmd, resp;			// Input and output buffers
+	netaddr cNum;
+	nodeaddr addr;
+	cnErrCode theErr = MN_OK;
+	paramValue sampleTimeMicroseconds;
+
+
+	if (!pReturnData)
+		return(MN_ERR_BADARG);
+
+	// Build the request command
+	cNum = NET_NUM(theMultiAddr);
+	addr = NODE_ADDR(theMultiAddr);
+
+	// Is the device in our range?
+	if (cNum >= NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	// Insure we support this feature
+	switch(SysInventory[cNum].NodeInfo[addr].theID.fld.devType ) {
+	case NODEID_CS:				// ClearPath-SC
+	case NODEID_MD:				// Meridian ISC FW 5.7 and beyond
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+
+	// Get the sample period
+	theErr = netGetParameterInfo(theMultiAddr, MN_P_SAMPLE_PERIOD,	
+								  NULL, &sampleTimeMicroseconds);
+	// Convert to sample-time in milliseconds
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// If there is no info, the node has disappeared.
+	monState *pMonNow;
+	if (!(pMonNow = (monState *)SysInventory[cNum].NodeInfo[addr].pNodeSpecific)) {
+		return MN_ERR_OFFLINE;
+	}
+
+	// Do we need monitor state?
+	if (!pMonNow->Set) {
+		// Get our monitor state
+		iscMonState monInfo;
+		theErr = iscGetMonitor(theMultiAddr, 0, &monInfo);
+		if (theErr != MN_OK) 
+			return(theErr);
+	}
+
+	cmd.Fld.Addr = theMultiAddr;	
+	cmd.Fld.PktLen = 1;						// No arguments
+	cmd.Byte.Buffer[CMD_LOC] = ISC_CMD_DATA_COLLECT;
+#define SIM_MODE 0
+	// Run the command and await the response
+#if !SIM_MODE
+	theErr = netRunCommand(cNum, &cmd, &resp);
+	if (theErr != MN_OK)
+		return (theErr);
+	// We have data, check for alignment/format problems
+	if (resp.Fld.PktLen != ISC_CMD_DATA_COLLECT_RESP_LEN) 
+		return (MN_ERR_RESP_FMT);
+#endif
+	// Copy response to parser to avoid alignment issues
+	iscDataCollectPkt parser;
+	memcpy(&parser, &resp.Byte.Buffer[RESP_LOC], sizeof(parser));
+#if SIM_MODE	// TEST CASE
+	pMonNow->FullScale = 1;
+
+	parser.data.LPmeanSqLSBs = 0x1e6e;
+	parser.data.LPmeanSqMSBs = 3;
+	parser.data.LPmeanSqScale = 5;
+
+	parser.data.HPmeanSqLSBs = 0x561b;
+	parser.data.HPmeanSqMSBs = 2;
+	parser.data.HPmeanSqScale = 12;
+
+	const size_t TIME_SAMPLE_LP = 55555;
+	parser.data.SampleTimesLSB = TIME_SAMPLE_LP&0xFFFF;
+	parser.data.SampleTimesMSB = TIME_SAMPLE_LP>>16;
+	parser.data.TrackingMaxNeg = -55;
+	parser.data.TrackingMaxPos = 66;
+	parser.data.LPmeasMaxNeg = -44;
+	parser.data.LPmeasMaxPos = 33;
+#endif
+
+	// Build the responses
+	pReturnData->MaxTrackingNeg = parser.data.TrackingMaxNeg;
+	pReturnData->MaxTrackingPos = parser.data.TrackingMaxPos;
+	pReturnData->LowPassMaxNeg = parser.data.LPmeasMaxNeg/32768. * pMonNow->FullScale;
+	pReturnData->LowPassMaxPos = parser.data.LPmeasMaxPos/32768. * pMonNow->FullScale;
+
+	// Check for saturation issues
+	const int16 MAX_DATA_POS = 32767;
+	const int16 MAX_DATA_NEG = -32768;
+
+	if (parser.data.TrackingMaxNeg==MAX_DATA_NEG ||
+		parser.data.TrackingMaxPos==MAX_DATA_POS ||
+		parser.data.LPmeasMaxNeg==MAX_DATA_NEG ||
+		parser.data.LPmeasMaxPos==MAX_DATA_POS) {
+		// Setup as failure, see if we can get more data returned first
+		theErr = MN_ERR_PARAM_RANGE; 
+	}
+	double rms;
+	int64 rmsMantissa;
+	// Restore 24-bit to 32-bit / sign extension
+	const size_t TIMER_BITS = 32-20;	// Padding bits
+	nodelong nSamples = ((parser.data.SampleTimesLSB << TIMER_BITS)
+					  | (parser.data.SampleTimesMSB << (16+TIMER_BITS)))>>TIMER_BITS;
+	// If negative or no samples, then move took to long or is too short
+	if (nSamples <= 0) { 
+		// Poison the bad return results
+		pReturnData->HighPassRMS = -1;
+		pReturnData->LowPassRMS = -1;
+		return(MN_ERR_PARAM_RANGE);
+	}
+	// Return the duration in milliseconds
+	pReturnData->DurationMS = nSamples * sampleTimeMicroseconds.value * .001;
+
+	const size_t MANTISSA_BITS = 19;	// Bits in the mantissa plus sign guard
+	const size_t INTEGER_BITS = 20;		// Number of integer bits
+	const size_t Q_TO_SUM = 12;			// Fixed pt to float scale factor
+
+	// Restore 19-bit mantissa (1.63) and align sign bit to machine sign-bit
+	rmsMantissa = ((int64)parser.data.LPmeanSqLSBs<<(64-MANTISSA_BITS))
+				| ((int64)parser.data.LPmeanSqMSBs<<(64-MANTISSA_BITS+16));
+	// Move fixed-point decimal back in place/ sign extension
+	rmsMantissa >>= (INTEGER_BITS+parser.data.LPmeanSqScale);
+	// Convert the fixed-point mean to floating point
+	rms = double(rmsMantissa)/double(1LL<<Q_TO_SUM);
+	// Get root mean squared and scale by the current monitor port full-scale
+	rms = sqrt(rms/double(nSamples));
+	pReturnData->LowPassRMS = rms*pMonNow->FullScale;
+
+	// Restore 19-bit mantissa (1.63) and align sign bit to machine sign-bit
+	rmsMantissa = ((int64)parser.data.HPmeanSqLSBs<<(64-MANTISSA_BITS))
+				| ((int64)parser.data.HPmeanSqMSBs<<(64-MANTISSA_BITS+16));
+	// Move fixed-point decimal back in place/ sign extension
+	rmsMantissa >>= (INTEGER_BITS+parser.data.HPmeanSqScale);
+	// Calculate the mean and convert to floating point
+	rms = double(rmsMantissa)/double(1LL<<Q_TO_SUM);
+	// Get root mean and scale by monitor port scale
+	rms = sqrt(rms/double(nSamples));
+	pReturnData->HighPassRMS = rms*pMonNow->FullScale;
+
+	return (theErr);
+}
+//																			  *
+//*****************************************************************************
+
+/// \cond INTERNAL_DOC
+
+//*****************************************************************************
+//	NAME																	  *
+//		netGetDrvrAttnMask
+//
+//	DESCRIPTION:
+/**
+	This function get the current special driver attention register for 
+	implementing Auto-Brake and Group Shutdowns via Attentions.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pAttnMask A pointer to an #attnReg structure to get the
+				current value of the driver's attention mask register.
+	\return MN_OK if successful.
+
+**/
+//	SYNOPSIS:
+cnErrCode MN_DECL netGetDrvrAttnMask(
+		multiaddr theMultiAddr,
+		attnReg *pAttnMask)
+{
+	cnErrCode theErr;
+	if (!pAttnMask)
+		return MN_ERR_BADARG;
+	if (theMultiAddr==MN_UNSET_ADDR)
+		return MN_ERR_BADARG;
+
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	// Does this node support this
+	nodeparam pNum;
+	switch(SysInventory[cNum].NodeInfo[theNode].theID.fld.devType) {
+	case NODEID_CS:
+		pNum = nodeparam(CPM_P_ATTN_DRVR_MASK);
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+	paramValue paramVal;
+	// Get the bits back
+	theErr = netGetParameterInfo(theMultiAddr, pNum, NULL, &paramVal);
+	if (theErr != MN_OK)
+		return theErr;
+	*pAttnMask = *((attnReg *)paramVal.raw.Byte.Buffer);
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netSetDrvrAttnMask
+//
+//	DESCRIPTION:
+/**
+	This function get the current special driver attention register for 
+	implementing Auto-Brake and Group Shutdowns via Attentions.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pAttnMask A pointer to an #attnReg structure to set the
+				driver's attention mask register at the requested node.
+	\return MN_OK if successful.
+
+**/
+//	SYNOPSIS:
+cnErrCode MN_DECL netSetDrvrAttnMask(
+		multiaddr theMultiAddr,
+		attnReg *pAttnMask)
+{
+	cnErrCode theErr;
+	if (!pAttnMask)
+		return MN_ERR_BADARG;
+	if (theMultiAddr==MN_UNSET_ADDR)
+		return MN_ERR_BADARG;
+
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	// Does this node support this
+	nodeparam pNum;
+	switch(SysInventory[cNum].NodeInfo[theNode].theID.fld.devType) {
+	case NODEID_CS:
+		pNum = nodeparam(CPM_P_ATTN_DRVR_MASK);
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+	theErr = netSetParameterInfo(theMultiAddr, pNum, pAttnMask->attnBits, true);
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netGetStatusEventMask
+//
+//	DESCRIPTION:
+/**
+	This function get the current special driver attention register for 
+	implementing Auto-Brake and Group Shutdowns via Attentions.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[out] pStatusEventMask A pointer to an #mnStatusReg structure to get the
+				current value of the driver's attention mask register.
+	\return MN_OK if successful.
+
+**/
+//	SYNOPSIS:
+cnErrCode MN_DECL netGetStatusEventMask(
+		multiaddr theMultiAddr,
+		mnStatusReg *pStatusEventMask)
+{
+	cnErrCode theErr;
+	if (!pStatusEventMask)
+		return MN_ERR_BADARG;
+	if (theMultiAddr==MN_UNSET_ADDR)
+		return MN_ERR_BADARG;
+
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	// Does this node support this
+	nodeparam pNum;
+	switch(SysInventory[cNum].NodeInfo[theNode].theID.fld.devType) {
+	case NODEID_CS:
+		pNum = nodeparam(CPM_P_STATUS_EVENT_MASK);
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+	paramValue paramVal;
+	// Get the bits back
+	theErr = netGetParameterInfo(theMultiAddr, pNum, NULL, &paramVal);
+	if (theErr != MN_OK)
+		return theErr;
+	*pStatusEventMask = *((mnStatusReg *)paramVal.raw.Byte.Buffer);
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netSetStatusEventMask
+//
+//	DESCRIPTION:
+/**
+	This function sets the current special driver attention register for 
+	implementing Auto-Brake and Group Shutdowns via Attentions.
+
+	\param[in] theMultiAddr The address code for this node.
+	\param[in] pStatusEventMask A pointer to an #mnStatusReg structure to set the
+				driver's attention mask register at the requested node.
+	\return MN_OK if successful.
+
+**/
+//	SYNOPSIS:
+cnErrCode MN_DECL netSetStatusEventMask(
+		multiaddr theMultiAddr,
+		const mnStatusReg *pStatusEventMask)
+{
+	cnErrCode theErr;
+	if (!pStatusEventMask)
+		return MN_ERR_BADARG;
+	if (theMultiAddr==MN_UNSET_ADDR)
+		return MN_ERR_BADARG;
+
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	// Does this node support this
+	nodeparam pNum;
+	switch(SysInventory[cNum].NodeInfo[theNode].theID.fld.devType) {
+	case NODEID_CS:
+		pNum = nodeparam(CPM_P_STATUS_EVENT_MASK);
+		break;
+	default:
+		return MN_ERR_NOT_IMPL;
+	}
+	packetbuf paramVal;
+	// Fill the buffer with the request
+	memcpy(paramVal.Byte.Buffer, pStatusEventMask, MN_STATUS_REG_OCTETS);
+	paramVal.Byte.BufferSize = MN_STATUS_REG_OCTETS;
+	// Send them out
+	theErr = netSetParameterEx(theMultiAddr, pNum, &paramVal);
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+/// \endcond
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPLAclear
+//
+//	DESCRIPTION:
+/**
+	This function will clear the active and non-volatile fuses for the PLA
+	feature.
+
+	\param[in] theMultiAddr The address code for this node.
+	\return MN_OK if successful.
+
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netPLAclear(
+		multiaddr theMultiAddr) 	// node address
+
+{
+	plaFuseBuffer fuses, wrFuses;
+	cnErrCode theErr;
+
+	// Get the AND term count
+	fuses.Setup(plaFuseBuffer::PLA_ARCH, plaFuseBuffer::AND_TERMS);
+	theErr = netPLAget(theMultiAddr, &fuses);
+	for (int i=0; i<fuses.Fuses.bits && theErr == MN_OK; i++) {
+		// Clear the AND area
+		wrFuses.Setup(plaFuseBuffer::PLA_AND, PARAM_OPT_MASK|i, 0);
+		theErr = netPLAset(theMultiAddr, &wrFuses);
+		if (theErr != MN_OK)
+			return(theErr);
+		// Clear the Not AND area
+		wrFuses.Setup(plaFuseBuffer::PLA_NAND, PARAM_OPT_MASK|i, 0);
+		theErr = netPLAset(theMultiAddr, &wrFuses);
+	}
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// Get the OR term count
+	fuses.Setup(plaFuseBuffer::PLA_ARCH, plaFuseBuffer::OR_TERMS);
+	theErr = netPLAget(theMultiAddr, &fuses);
+	for (int i=0; i<fuses.Fuses.bits && theErr == MN_OK; i++) {
+		// Clear the OR area
+		wrFuses.Setup(plaFuseBuffer::PLA_OR, PARAM_OPT_MASK|i, 0);
+		theErr = netPLAset(theMultiAddr, &wrFuses);
+	}
+	if (theErr != MN_OK)
+		return(theErr);
+
+	// Get the Option register count
+	fuses.Setup(plaFuseBuffer::PLA_ARCH, plaFuseBuffer::OPTION_REGS);
+	theErr = netPLAget(theMultiAddr, &fuses);
+	for (int i=0; i<fuses.Fuses.bits && theErr == MN_OK; i++) {
+		// Clear the OR area
+		wrFuses.Setup(plaFuseBuffer::PLA_OPTION, PARAM_OPT_MASK|i, 0);
+		theErr = netPLAset(theMultiAddr, &wrFuses);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPLAget
+//
+//	DESCRIPTION:
+/**
+	This function will get the fuse settings for the specified location within
+	the PLA device.
+
+	\param[in] theMultiAddr The address code for this node.
+ 	\param[in,out] pFuses Ptr to the fuse selection and result storage.
+	\return MN_OK if fuses successfully updated.
+
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netPLAget(
+		multiaddr theMultiAddr, 	// node address
+		plaFuseBuffer *pFuses)		// Ptr to fuse buffer
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_CMD, NODE_ADDR(theMultiAddr), MN_SRC_HOST);
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_PLA;
+	theCmd.Byte.Buffer[CMD_LOC+1] = (nodechar)pFuses->FuseArea;
+	theCmd.Byte.Buffer[CMD_LOC+2] = (nodechar)pFuses->FuseIndex.bits;
+	theCmd.Fld.PktLen = 3;
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp);
+	if (theErr == MN_OK) {
+		if (theResp.Fld.PktLen != 2)
+			return(MN_ERR_RESP_FMT);
+		pFuses->Fuses.bits = ((Uint16)theResp.Byte.Buffer[RESP_LOC] & 0xff)
+						   | ((Uint16)theResp.Byte.Buffer[RESP_LOC+1]<<8);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		netPLAset
+//
+//	DESCRIPTION:
+/**
+	This function will set the fuse settings for the specified location within
+	the PLA device.
+
+	\param[in] theMultiAddr The address code for this node.
+ 	\param[in,out] pFuses Ptr to the fuse selection and new settings storage.
+	\return MN_OK if fuses successfully updated.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netPLAset(
+		multiaddr theMultiAddr, 	// node address
+		plaFuseBuffer *pFuses)		// Ptr to fuse buffer
+{
+	packetbuf theCmd, theResp;
+	cnErrCode theErr;
+
+	theCmd.Fld.SetupHdr(MN_PKT_TYPE_CMD, NODE_ADDR(theMultiAddr), MN_SRC_HOST);
+	theCmd.Byte.Buffer[CMD_LOC] = MN_CMD_PLA;
+	theCmd.Byte.Buffer[CMD_LOC+1] = (nodechar)pFuses->FuseArea;
+	theCmd.Byte.Buffer[CMD_LOC+2] = (nodechar)pFuses->FuseIndex.bits;
+	theCmd.Byte.Buffer[CMD_LOC+3] = (nodechar)pFuses->Fuses.bits;
+	theCmd.Byte.Buffer[CMD_LOC+4] = (nodechar)(pFuses->Fuses.bits>>8);
+
+	theCmd.Fld.PktLen = 5;
+
+	theErr = netRunCommand(NET_NUM(theMultiAddr), &theCmd, &theResp);
+	if (theErr == MN_OK) {
+		if (theResp.Fld.PktLen != 0)
+			return(MN_ERR_RESP_FMT);
+	}
+	return(theErr);
+}
+//																			  *
+//*****************************************************************************
+
+
+/// \cond INTERNAL_DOC
+
+//*****************************************************************************
+//	NAME																	  *
+//		extractFileNameBase
+//
+//	DESCRIPTION:
+/**
+	This function extracts the basename from a Windows or Unix type file
+	path.
+
+	\param[in] pInputName full filename path.
+	\param[out] pBaseName Basename of the file path
+ 	\param[in] maxLen size of pBaseName array.
+**/
+const char *extractFileNameBase(const char *pInputName, char *pBaseName, size_t maxLen)
+{
+	char srcCopy[MAX_PATH];
+	strncpy(srcCopy, pInputName, sizeof(srcCopy));
+	// Extract last item from path
+	char *pLastToken[2] = {0};
+	pLastToken[0] = strtok(srcCopy, "\\/");
+	while (pLastToken[0]) {
+		pLastToken[1] = pLastToken[0];
+		pLastToken[0] = strtok(NULL, "\\/");
+	}
+	// Break apart the last item at the optional "."
+	pLastToken[1] = strtok(pLastToken[1], ".");
+	// Send to the output string area
+	strncpy(pBaseName, pLastToken[1], maxLen);
+	// Return convenience pointer
+	return(pBaseName);
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		setNodeNewConfig
+//
+//	DESCRIPTION:
+/**
+	These functions writes the base name of the file path and clears the
+	modified indicator at the node.
+
+	\param[in] theMultiPath The node to update.
+	\param[in] pFilePath File path in UNIX or WINDOWS format.
+**/
+cnErrCode setNodeNewConfig(
+	multiaddr theMultiAddr, 
+	const char *pFilePath)
+{
+	cnErrCode theErr = MN_ERR_NOT_IMPL;
+	char cfgFileName[MN_FILENAME_SIZE];
+	// Clear 'modified' counter	and store config file name at node.
+	nodeIDs theNodeType = netGetDevType(theMultiAddr);
+	switch(theNodeType) {
+#if 0 // Prevent usage for now
+	case NODEID_MD:
+		theErr = iscSetParameter(theMultiAddr, ISC_P_DRV_CONFIG_CHANGED, 0);
+		break;
+	case NODEID_CP:
+		theErr = clearPathSetParameter(theMultiAddr, CP_P_DRV_CONFIG_CHANGED, 0);
+		break;
+#endif
+	case NODEID_CS:
+		theErr = cpmSetMotorFileName(theMultiAddr, 
+									  extractFileNameBase(
+											pFilePath, 
+										    cfgFileName,
+											sizeof(cfgFileName)));
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN,"Failed to set motor filename, err %0X\n", theErr);
+			goto bailOut;
+		}
+		theErr = cpmSetParameter(theMultiAddr, CPM_P_DRV_CONFIG_CHANGED, 0);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN,"Failed to clear config changed indicator, err %0X\n", theErr);
+			goto bailOut;
+		}
+		break;
+	default:
+		theErr = MN_ERR_NOT_IMPL;
+		goto bailOut;
+	}
+//--------
+bailOut:
+//--------
+	return (theErr);
+}
+
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		setConfigItem
+//
+//	DESCRIPTION:
+/**
+	These functions sets items in the motor file dictionary for
+	subsequent writing as a file.
+
+	\param[in] d Point to the dictionary.
+	\param[in] theSection Section of file.
+ 	\param[in] theItem Key to store value at.
+	\param[in] theVal String to store at key.
+**/
+//	SYNOPSIS:
+cnErrCode setConfigItem(
+    dictionary *d,
+	const char *theSection, 
+	const char *theItem, 
+	const char *theVal)
+{
+	const size_t MAX_ITEM_CHARS = 100;
+	char itemKey[MAX_ITEM_CHARS];
+	snprintf(itemKey, sizeof(itemKey), "%s:%s", theSection, theItem);
+	iniparser_setstring(d, itemKey, theVal);
+	return MN_OK;
+}
+cnErrCode setConfigItem(
+    dictionary *d,
+	const char *theSection, 
+	const char *theItem, 
+	double theVal)
+{
+	const size_t MAX_ITEM_CHARS = 100;
+	char valStr[MAX_ITEM_CHARS];
+	snprintf(valStr, sizeof(valStr), "%lf", theVal);
+	return setConfigItem(d, theSection, theItem, valStr);
+}
+
+cnErrCode setConfigItem(
+	dictionary *d,
+	const char *theSection,
+	multiaddr theMultiAddr,
+	nodeparam theParam,
+	const paramInfo &info)
+{
+	const size_t MAX_ITEM_CHARS = 100;
+	char valStr[MAX_ITEM_CHARS];
+	const char *unitStr=NULL;
+	cnErrCode theErr;
+	paramValue paramVal;
+
+	// Get the value from the node in long form, in case non-numeric
+	theErr = netGetParameterInfo(theMultiAddr, theParam, NULL, &paramVal);
+	if (theErr != MN_OK) {
+		_RPT2(_CRT_WARN, "setConfig get param failed param=%d, err=%x\n",
+			theParam, theErr);
+		return theErr;
+	}
+	
+	if (info.unitType == BIT_FIELD) {
+		if (info.paramSize == 2)
+			snprintf(valStr, sizeof(valStr), "&H%04X", nodeulong(paramVal.value));
+		else
+			snprintf(valStr, sizeof(valStr), "&H%08X", nodeulong(paramVal.value));
+	}
+	else if (info.paramSize > 4) {
+		const size_t BYTE_REPR_WIDTH = 2;
+		char byteRepr[BYTE_REPR_WIDTH + 1];
+
+		memset(valStr, 0, sizeof(valStr));
+		strncpy(valStr, "&H", 2);
+		
+		for (int i = info.paramSize - 1; i >= 0; i--) {
+			snprintf(byteRepr, sizeof(byteRepr), "%02X", (unsigned char) paramVal.raw.Byte.Buffer[i]);
+			strncat(valStr, byteRepr, BYTE_REPR_WIDTH);
+		}
+	}
+	else {
+		switch (info.unitType) {
+		case TIME_USEC:
+			unitStr = "usec";
+			break;
+		case DX_TICK:
+			unitStr = "ticks";
+			break;
+		case VEL_TICKS_S:
+			unitStr = "ticks/sec";
+			break;
+		case VEL_TICKS_S2:
+			unitStr = "ticks/sec^2";
+			break;
+		case CURRENT:
+			unitStr = "A";
+			break;
+		case VOLT:
+			unitStr = "V";
+			break;
+		case TIME_MSEC:
+			unitStr = "msec";
+			break;
+		case VOLTS_PER_KRPM:
+			unitStr = "V/kRPM";
+			break;
+		case DEGREES:
+			unitStr = "degrees";
+			break;   
+		case PERCENT_MAX:
+			unitStr = "% of max.";
+			break;
+		case NO_UNIT:
+			break;
+		default:
+			break;
+		}
+		if (unitStr) 
+			snprintf(valStr, sizeof(valStr), "%lf\t;(%s)", paramVal.value, unitStr);
+		else
+			snprintf(valStr, sizeof(valStr), "%lf", paramVal.value);
+	}
+	// Check for issues
+	if ((size_t)info.keyID > sizeof(ConfigKeys)/sizeof(char *))
+		//throw "valkeys.h is too short";
+		throwSystemError("valkeys.h is too short");
+	if (info.keyID == PARAM_NULL)
+		//throw "param table not setup properly";
+		throwSystemError("param table not setup properly");
+
+	return setConfigItem(d, theSection, ConfigKeys[info.keyID], valStr);
+}
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		getAndSetConfigItem
+//
+//	DESCRIPTION:
+/**
+	This functions retrieves the value in the configuration file and storing
+	it in the drive as run-time and non-volatile locations.
+
+	\param[in] d Point to the dictionary.
+	\param[in] theSection Section of file.
+	\param[in] theMultiAddr The address of the node to update.
+ 	\param[in] theParam The parameter number in the drive.
+	\param[in] info Parameter information structure for this parameter.
+**/
+//	SYNOPSIS:
+cnErrCode getAndSetConfigItem(
+	dictionary *d,
+	const char *theSection,
+	multiaddr theMultiAddr,
+	nodeparam theParam,
+	const paramInfo &info)
+{
+	#define SCAN_MAX "100"
+	const size_t MAX_ITEM_CHARS = 150;
+	char valStr[MAX_ITEM_CHARS], keyStr[MAX_ITEM_CHARS];
+	const char* DEFAULT_VAL = "__XZYZY42__", *iniItem;
+	// Extract out the node address parts, the netGetFirmwareID verified the
+	// multi-address is OK.
+	//netaddr cNum = NET_NUM(theMultiAddr);
+	//nodeaddr theNode = NODE_ADDR(theMultiAddr);
+	cnErrCode theErr;
+	if ((size_t)info.keyID > sizeof(ConfigKeys) / sizeof(char *))
+		//throw "valkeys.h is too short";
+		throwSystemError("valkeys.h is too short");
+	// Build up value query
+	snprintf(keyStr, sizeof(keyStr), "%s:%s",
+		theSection, ConfigKeys[info.keyID]);
+	iniItem = iniparser_getstring(d, keyStr, DEFAULT_VAL);
+	// Missing item
+	if (strcmp(iniItem, DEFAULT_VAL)==0) {
+		_RPT1(_CRT_WARN, "Missing item %s\n", keyStr);
+		return MN_ERR_FILE_BAD;
+	}
+
+	// Strip out comment or EOLs
+	unsigned numMatches = sscanf(iniItem, "%" SCAN_MAX "s", valStr);
+	if (numMatches == 0) {
+		_RPT0(_CRT_WARN, "Missing item value is null\n");
+		return	MN_ERR_FILE_BAD;
+	}
+	size_t theLength = strlen(valStr);
+	if (info.paramSize > 4) {
+		// Parameter too wide to read as a nodelong; do byte-by-byte hex conversion
+		if (theLength % 2) {
+			// We always emit 0-padded even-length strings to make reading easy
+			_RPT0(_CRT_WARN, "Item length not even");
+			return MN_ERR_FILE_BAD;
+		}
+		if (theLength > 2 + info.paramSize * 2) {
+			// 2 chars for "&H" and 2 chars per byte
+			_RPT0(_CRT_WARN, "Item too long");
+			return MN_ERR_FILE_BAD;
+		}
+		if (theLength < 2) {
+			// "&H" is interpreted as 0, but anything shorter is invalid;
+			// we do not support decimal conversion for wide params
+			_RPT0(_CRT_WARN, "Item too short");
+			return MN_ERR_FILE_BAD;
+		}
+		// Start with a zeroed-out buffer in case the hex string is short
+		paramValue paramVal;
+		paramVal.raw.Byte.BufferSize = info.paramSize;
+		memset(paramVal.raw.Byte.Buffer, 0, sizeof(paramVal.raw.Byte.Buffer));
+		int scanSuccess; // equals 1 when hex conversion succeeds
+		unsigned byteIndex; // index into the buffer
+		// Endianness swap: start with the last two characters in the string
+		const char *hexStrPos = valStr + theLength - 2;
+
+		// Two chars per byte, minus the "&H"
+		for (byteIndex = 0; byteIndex < theLength / 2 - 1; byteIndex++) {
+			// read the characters and put the result directly into the buffer
+			scanSuccess = sscanf(hexStrPos, "%2hhx", &paramVal.raw.Byte.Buffer[byteIndex]);
+			if (scanSuccess < 1) {
+				_RPT2(_CRT_WARN, "Failed extended hex conversion of %s, parameter %d\n",
+					valStr, theParam);
+				return MN_ERR_FILE_BAD;
+			}
+			hexStrPos -= 2;
+		}
+		// Run the command and update our cache
+		theErr = netSetParameterEx(theMultiAddr, mnParams(theParam), &paramVal.raw);
+		if (theErr != MN_OK) {
+			_RPT2(_CRT_WARN, "Failed to save parameter %d in node. Err=0x%x\n",
+				theParam, theErr);
+			return theErr;
+		}
+		theErr = netSetParameterEx(theMultiAddr, mnParams(theParam + PARAM_OPT_MASK), &paramVal.raw);
+		if (theErr != MN_OK) {
+			_RPT2(_CRT_WARN, "Failed to save NV parameter %d in node. Err=0x%x\n",
+				theParam, theErr);
+			return theErr;
+		}
+		return theErr;
+	}
+	double paramVal;
+	switch (info.unitType) {
+	case BIT_FIELD:
+		// Change from VB hex to C hex
+		try {
+			paramVal = hexToDec(valStr+2);
+		}
+		catch (...) {
+			_RPT2(_CRT_WARN, "Failed hex conversion of %s, parameter %d\n", 
+				valStr, theParam);
+			return MN_ERR_FILE_BAD;
+		}
+		break;
+	default:
+		errno = 0;			// Zap old errors
+		paramVal = atof(valStr);
+		if (errno) {
+			_RPT2(_CRT_WARN, "Failed numeric conversion of %s, parameter %d\n", 
+				valStr, theParam);
+			return MN_ERR_FILE_BAD;
+		}
+		break;
+	}
+	theErr = netSetParameterDbl(theMultiAddr, mnParams(theParam), paramVal);
+	if (theErr != MN_OK) {
+		_RPT2(_CRT_WARN, "Failed to save parameter %d in node. Err=0x%x\n", 
+			theParam, theErr);
+		return theErr;
+	}
+	theErr = netSetParameterDbl(theMultiAddr, mnParams(theParam+PARAM_OPT_MASK), paramVal);
+	if (theErr != MN_OK) {
+		_RPT2(_CRT_WARN, "Failed to save NV parameter %d in node. Err=0x%x\n", 
+			theParam, theErr);
+		return theErr;
+	}
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+ /// \endcond
+
+
+//******************************************************************************
+//	NAME																	   *
+//		netConfigLoad
+//
+//	DESCRIPTION:
+/**
+	Query the node and build up the firmware ID used as the key for 
+	a configuration file. This is in the format:
+		TEK32{moniker}{model}-{amps}-{pwba}
+
+	\param[in] theMultiAddr The address code for this node.
+ 	\param[in] loadFmt Expected format of the data  
+	\param[in] pFilePath Pointer to configuration file.
+	
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netConfigLoad(
+		multiaddr theMultiAddr,
+		configFmts loadFmt,
+		const char *pFilePath)
+{
+	dictionary *d;
+	char firmwareID[20];
+	char keyStr[100];
+	cnErrCode theErr;
+	bool isAdvanced = false;
+	bool hasMtrPart = false;
+	bool hasNodePart = false;
+ 	// Extract out the node address parts, the netGetFirmwareID verified the
+	// multi-address is OK.
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theNode = NODE_ADDR(theMultiAddr);
+
+	// TODO: add other formats
+	if (loadFmt != CLASSIC && loadFmt != CLASSIC_NO_RESET)
+		return MN_ERR_NOT_IMPL;
+
+	// Make sure node is not enabled
+	mnStatusReg currentStatus;
+	theErr = netGetStatusRTReg(theMultiAddr, &currentStatus);
+	if (theErr != MN_OK)
+		return theErr;
+
+	// Don't allow load if enabled
+	if (currentStatus.cpm.Enabled) {
+		return MN_ERR_FILE_ENABLED;
+	}
+
+
+	// Get the section name for this file
+	theErr = netGetFirmwareID(theMultiAddr, sizeof(firmwareID), firmwareID);
+	if (theErr != MN_OK)
+		return theErr;
+
+	// Get firmware version
+	double versNum;
+	theErr = netGetParameterDbl(theMultiAddr, MN_P_FW_VERSION, &versNum);
+	if (theErr != MN_OK) {
+		_RPT1(_CRT_WARN,"Failed getting firmware version. Err=0x%X.\n", theErr);
+		return theErr;
+	}
+	//versID_t chipVers;
+	//chipVers.verCode = Uint16(versNum);
+
+	// Get options 
+	double optionsDbl;
+	optionReg options;
+	theErr = netGetParameterDbl(theMultiAddr, MN_P_OPTION_REG, &optionsDbl);
+	if (theErr != MN_OK) 
+		return theErr;
+	options.bits = nodeulong(optionsDbl);
+
+	// Clear out any old config first to insure common start
+	nodeIDs theNodeType = netGetDevType(theMultiAddr);
+	switch(theNodeType) {
+#if 0 // Prevent usage for now
+	case NODEID_MD:
+		theErr = iscFactoryDefaults(theMultiAddr);
+		break;
+	case NODEID_CP:
+		theErr = clearPathFactoryDefaults(theMultiAddr);
+		break;
+#endif
+	case NODEID_CS:
+		isAdvanced = options.Common.Advanced;
+		break;
+	default:
+		_RPT0(_CRT_WARN,"No config file support for this node.\n");
+		theErr = MN_ERR_NOT_IMPL;
+		goto bailOut;
+	}
+
+	// Load the file
+	d = iniparser_load(pFilePath);
+	if (d == NULL) {
+		_RPT1(_CRT_WARN, "Failed to parse config file '%s'.\n", pFilePath);
+		return MN_ERR_FILE_OPEN;
+	}
+
+	char *thisSect;
+	const char *theItem;
+	// Make sure this file matches the type of node specified.
+	for (int i=0; i<iniparser_getnsec(d); i++) {
+		thisSect = iniparser_getsecname(d, i);
+		if (thisSect == NULL)
+			return MN_ERR_CMD_INTERNAL;
+		hasNodePart |= strcmp(firmwareID, thisSect) == 0;
+		hasMtrPart |= strcmp(MOTOR_SECTION, thisSect) == 0;
+	}
+	// Missing required parts?
+	if (!(hasNodePart && hasMtrPart)) {
+		_RPT0(_CRT_WARN, "Missing section(s) in config file.\n");
+		theErr = MN_ERR_FILE_WRONG;
+		goto bailOut;
+	}
+	// Poison the configuration in case of failure
+	theErr = netSetParameterDbl(theMultiAddr, MN_P_EE_UPD_ACK, 0);
+	if (theErr != MN_OK) {
+		_RPT1(_CRT_WARN,"Failed config poisoning err %0X\n", theErr);
+		goto bailOut;
+	}
+	try {
+		// Load the motor parts first
+		for (size_t bank=0; bank < SysInventory[cNum].NodeInfo[theNode].bankCount; bank++) {
+			for (size_t pIndx=0; 
+				pIndx < SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].nParams ;
+				pIndx++) {
+					const paramInfo &p 
+						= SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].fixedInfoDB[pIndx].info;
+					if ((p.paramType & PT_IN_MTR_CFG) && !(p.paramType & PT_IN_FACT_CFG)) {
+						getAndSetConfigItem(d, MOTOR_SECTION, theMultiAddr, 
+											nodeparam(256*bank+pIndx), p);
+					}
+
+			}
+		}
+		// Load the rest of the configuration
+		for (size_t bank=0; bank < SysInventory[cNum].NodeInfo[theNode].bankCount; bank++) {
+			for (size_t pIndx=0; 
+				pIndx < SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].nParams ;
+				pIndx++) {
+					const paramInfo &p 
+						= SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].fixedInfoDB[pIndx].info;
+					// Load if a non factory config item and skip advanced 
+					// items when we are not advanced.
+					if ((p.paramType & PT_IN_NODE_CFG) && !(p.paramType & PT_IN_FACT_CFG)
+					&& (!(p.paramType & PT_ADV) || (isAdvanced && (p.paramType & PT_ADV)))) {
+						getAndSetConfigItem(d, firmwareID, theMultiAddr, 
+											nodeparam(256*bank+pIndx), p);
+					}
+
+			}
+		}
+		// Restore the user ID
+		snprintf(keyStr, sizeof(keyStr), "%s:%s", (const char *)firmwareID, CNFG_USERID);
+		theItem = iniparser_getstring(d, keyStr, "");
+		theErr = netSetUserID(theMultiAddr, theItem);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN, "Failed to set user ID, err=0x%x\n", theErr);
+			goto bailOut;
+		}
+		// Restore the user description
+		snprintf(keyStr, sizeof(keyStr), "%s:%s", (const char *)firmwareID, CNFG_USER_DESC);
+		theItem = iniparser_getstring(d, keyStr, "");
+		theErr = netSetUserDescription(theMultiAddr, theItem);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN, "Failed to set user description, err=0x%x\n", theErr);
+			goto bailOut;
+		}
+		double paramVal;
+		// We have succeeded, update EE and ROM Ack parameters to clear any
+		// errors.
+		theErr = netGetParameterDbl(theMultiAddr, MN_P_EE_VER, &paramVal);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN, "Failed to get EE Ver, err=0x%x\n", theErr);
+			goto bailOut;
+		}
+		theErr = netSetParameterDbl(theMultiAddr, MN_P_EE_UPD_ACK, paramVal);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN, "Failed to set EE Ver Ack, err=0x%x\n", theErr);
+			goto bailOut;
+		}
+		// Update ROMSUM Ack in case this load fixed firmware updated
+		theErr = netGetParameterDbl(theMultiAddr, MN_P_ROM_SUM, &paramVal);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN, "Failed to get ROM checksum, err=0x%x\n", theErr);
+			goto bailOut;
+		}
+		theErr = netSetParameterDbl(theMultiAddr, MN_P_ROM_SUM_ACK, paramVal);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN, "Failed to set ROM update Ack, err=0x%x\n", theErr);
+			goto bailOut;
+		}
+		// Reset modified indicator and update the filename
+		theErr = setNodeNewConfig(theMultiAddr, pFilePath);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN,"Failed config finalize err %0X\n", theErr);
+			goto bailOut;
+		}
+		if (loadFmt != CLASSIC_NO_RESET){
+			// All Done, Restart node to insure its using the new settings
+			theErr = mnRestartNode(theMultiAddr);
+			if (theErr != MN_OK) {
+				_RPT1(_CRT_WARN, "Failed to restart, err=0x%x\n", theErr);
+				goto bailOut;
+			}
+		}
+		else{
+			theErr = netAlertClear(theMultiAddr);
+			if (theErr != MN_OK) {
+				_RPT1(_CRT_WARN, "Failed to clear shutdowns, err=0x%x\n", theErr);
+				goto bailOut;
+			}
+			// Indicate that the params need to be refreshed
+			SysInventory[cNum].pNCS->paramsHaveChanged[theNode] = TRUE;
+		}
+	}
+	catch(...) {
+		theErr = MN_ERR_FAIL;
+	}
+// ----------
+bailOut:
+// ----------
+	iniparser_freedict(d);
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+//*****************************************************************************
+//	NAME																	  *
+//		netConfigSave
+//
+//	DESCRIPTION:
+/**
+	This function with save the motor and drive configuration of a drive which
+	can be loaded at a later time with #netConfigLoad function.
+
+	\param[in] theMultiAddr The address code for this node.
+ 	\param[in] saveFmt Format of the data, for future use.
+	\param[in] pFilePath Pointer to configuration file.
+**/
+//	SYNOPSIS:
+MN_EXPORT cnErrCode MN_DECL netConfigSave(
+		multiaddr theMultiAddr,
+		configFmts saveFmt,
+		const char *pFilePath)
+{
+	cnErrCode theErr = MN_OK;
+	const size_t MAX_ITEM_CHARS = 150;
+	// Values from the node
+	double versNum, optionsDbl;
+	optionReg options;
+	// Place to put string items in
+	char itemStr[MAX_ITEM_CHARS];
+	time_t now;
+	bool isAdvanced = false;
+
+	char sectName[20];
+	// TODO: add other formats
+	if (saveFmt != CLASSIC)
+		return MN_ERR_NOT_IMPL;
+
+	// Get the section name for this file
+	theErr = netGetFirmwareID(theMultiAddr, sizeof(sectName), sectName);
+	if (theErr != MN_OK)
+		return theErr;
+
+	// Extract out the node address parts, the netGetFirmwareID verified the
+	// multi-address is OK.
+	netaddr cNum;
+	nodeaddr theNode;
+	cNum = NET_NUM(theMultiAddr);
+	theNode = NODE_ADDR(theMultiAddr);
+
+	// Get common items for the start of file
+	theErr = netGetParameterDbl(theMultiAddr, MN_P_OPTION_REG, &optionsDbl);
+	if (theErr != MN_OK) 
+		return theErr;
+	options.bits = nodeulong(optionsDbl);
+	// Get firmware version
+	versID_t chipVers;
+	theErr = netGetParameterDbl(theMultiAddr, MN_P_FW_VERSION, &versNum);
+	if (theErr != MN_OK) 
+		return theErr;
+	chipVers.verCode = Uint16(versNum);
+	// Start building the file
+	dictionary *d;
+	d = dictionary_new(0);
+	if (!d) 
+		return MN_ERR_MEM_LOW;
+	// Create the section
+	try {
+
+		// Create the section entry
+		iniparser_setstring(d, sectName, "");
+		// Write out chip version info
+		snprintf(itemStr, sizeof(itemStr), "%d.%d.%d",
+			chipVers.fld.majorVers, chipVers.fld.minorVers, chipVers.fld.buildVers);
+		setConfigItem(d, sectName, CNFG_VER_KEY, itemStr);
+		// Write out the user id
+		theErr = netGetUserID(theMultiAddr, itemStr, sizeof(itemStr));
+		if (theErr != MN_OK)
+			goto bailOut;
+		if (strncmp(itemStr, "Unloaded ", strlen("Unloaded ")) != 0) {
+			// If it doesn't look like the default name, copy it over
+			setConfigItem(d, sectName, CNFG_USERID, itemStr);
+		}
+		else {
+			// Otherwise, save it as a blank value
+			setConfigItem(d, sectName, CNFG_USERID, "");
+		}
+		// Write out the current time/date
+		time(&now);
+		struct tm *timeInfo;
+		timeInfo = localtime(&now);
+		snprintf(itemStr, sizeof(itemStr), "%04d-%02d-%02d %02d:%02d:%02d",
+			1900+timeInfo->tm_year, timeInfo->tm_mon+1, timeInfo->tm_mday,
+			timeInfo->tm_hour, timeInfo->tm_min, timeInfo->tm_sec);
+		setConfigItem(d, sectName, CNFG_DATE_KEY, itemStr);
+		// Write out our write version
+		longVers libVers;
+		libVers.bits = infcVersion();
+		snprintf(itemStr, sizeof(itemStr), "sFoundation %d.%d.%d",
+			libVers.fld.major, libVers.fld.minor, libVers.fld.build);
+		setConfigItem(d, sectName, CNFG_MOD_VER_KEY, itemStr);
+		// Write out our part number
+		theErr = netGetPartNumber(theMultiAddr, itemStr, sizeof(itemStr));
+		if (theErr != MN_OK)
+			goto bailOut;
+		setConfigItem(d, sectName, CNFG_PN, itemStr);
+		// Write out the user description
+		theErr = netGetUserDescription(theMultiAddr, itemStr, sizeof(itemStr));
+		if (theErr != MN_OK)
+			goto bailOut;
+		setConfigItem(d, sectName, CNFG_USER_DESC, itemStr);
+
+		// Clear out any old config first to insure common start
+		nodeIDs theNodeType = netGetDevType(theMultiAddr);
+		switch(theNodeType) {
+#if 0 // Prevent usage for now
+		case NODEID_MD:
+			theErr = iscFactoryDefaults(theMultiAddr);
+			break;
+		case NODEID_CP:
+			theErr = clearPathFactoryDefaults(theMultiAddr);
+			break;
+#endif
+		case NODEID_CS:
+			isAdvanced = options.Common.Advanced;
+			break;
+		default:
+			_RPT0(_CRT_WARN,"No config file support for this node.\n");
+			theErr = MN_ERR_NOT_IMPL;
+			goto bailOut;
+		}
+		// Loop through our parameter banks for configuration parameters
+		for (size_t bank=0; bank < SysInventory[cNum].NodeInfo[theNode].bankCount; bank++) {
+			for (size_t pIndx=0; 
+				pIndx < SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].nParams ;
+				pIndx++) {
+					const paramInfo &p 
+						= SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].fixedInfoDB[pIndx].info;
+					// Grab items in our configuration and skip advanced items
+					// when our node is not that type.
+					bool inCfg = (p.paramType & PT_IN_NODE_CFG) != 0;
+					bool advChkOK = !(p.paramType & PT_ADV)		// All non-advanced OK
+							|| ((p.paramType & PT_ADV) && isAdvanced);
+					if (inCfg && advChkOK) {
+						setConfigItem(d, sectName, theMultiAddr, 
+									  nodeparam(256*bank+pIndx), p);
+					}
+
+			}
+		}
+
+		// Create the motor section entry
+		iniparser_setstring(d, MOTOR_SECTION, "");
+		// Loop through the motor parameter for configuration parameters
+		for (size_t bank=0; bank < SysInventory[cNum].NodeInfo[theNode].bankCount; bank++) {
+			for (size_t pIndx=0; 
+				pIndx < SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].nParams ;
+				pIndx++) {
+					const paramInfo &p 
+						= SysInventory[cNum].NodeInfo[theNode].paramBankList[bank].fixedInfoDB[pIndx].info;
+					bool inMtrCfg = (p.paramType & PT_IN_MTR_CFG) != 0;
+					bool advMtrChkOK = !(p.paramType & PT_ADV)		// All non-advanced OK
+							|| ((p.paramType & PT_ADV) && isAdvanced);
+					if (inMtrCfg && advMtrChkOK) {
+						setConfigItem(d, MOTOR_SECTION, theMultiAddr, 
+									  nodeparam(256*bank+pIndx), p);
+					}
+
+			}
+		}
+		// Reset modified indicator and update the filename
+		theErr = setNodeNewConfig(theMultiAddr, pFilePath);
+		if (theErr != MN_OK) {
+			_RPT1(_CRT_WARN,"No config file support for this node. Err=%x\n",
+				theErr);
+			goto bailOut;
+		}
+		// Write out our completed dictionary in INI format
+		FILE *fo;
+		fo = fopen(pFilePath, "w");
+		if (fo!=NULL) {
+			iniparser_dump_ini(d, fo);
+			fclose(fo);
+		} 
+		else { 
+			//throw("failed to create file");
+			throwSystemError("failed to create file");
+		}
+	}
+	catch(...) {
+		dictionary_del (d);
+		return MN_ERR_FAIL; 
+	}
+//------------
+bailOut:
+//------------
+	dictionary_del (d);
+	return theErr;
+}
+//																			  *
+//*****************************************************************************
+
+
+/// \cond	INTERNAL_DOC
+
+//******************************************************************************
+//	NAME																	   *
+//		netGetFirmwareID
+//
+//	DESCRIPTION:
+/**
+	Query the node and build up the firmware ID used as the key for 
+	a configuration file. This is in the format:
+		TEK32 {moniker}{model}-{amps}-{pwba}
+
+	\param[in] theMultiAddr The address code for this node.
+ 	\param[in] bufSizeMax Destination area of compatibility 18 octet buffer
+	\param[out] theID  Buffer for c string result.
+	
+**/
+//	SYNOPSIS:
+cnErrCode netGetFirmwareID (
+		multiaddr theMultiAddr,		// Node address
+		size_t bufSizeMax,			// sizeof theID buffer
+		char *theID)
+{
+	cnErrCode theErr;
+	double theParam, theAmps;
+	nodeulong pwbType;
+	const size_t FWID_SZ = 19;
+	const nodeulong PWB_TYPE_MASK = 0xc0;
+
+	// Parameter locations that we don't want exposed publicly
+	const cpmParams CPM_P_DRV_TP_IOP = (cpmParams)285;
+
+	// Is address OK?
+	netaddr cNum = NET_NUM(theMultiAddr);
+	//nodeaddr addr = NODE_ADDR(theMultiAddr);
+	if (cNum>NET_CONTROLLER_MAX)
+		return MN_ERR_DEV_ADDR;
+
+	// The output buffer is too small?
+	if (bufSizeMax<FWID_SZ) 
+		return MN_ERR_BADARG;
+
+	// Get our node ID
+	devID_t theNodeType;
+	theErr = netGetParameterDbl(theMultiAddr, MN_P_NODEID, &theParam); 
+	if (theErr != MN_OK)
+		return theErr;
+	// Convert to structure format
+	theNodeType.devCode = (Uint16)theParam;
+
+	// Get the option register
+	theErr = netGetParameterDbl(theMultiAddr, MN_P_OPTION_REG, &theParam);
+	if (theErr != MN_OK)
+		return theErr;
+
+	switch(theNodeType.fld.devType) {
+	case NODEID_MD:
+		// Get PWBA type from internal register
+		theErr = iscGetParameter(theMultiAddr, ISC_P_DRV_TP_IOP, &theParam);
+ 		if (theErr != MN_OK)
+			return theErr;
+		// Extract out of bits
+		pwbType = (PWB_TYPE_MASK & nodeulong(theParam)) >> 6;
+		theErr = iscGetParameter(theMultiAddr, ISC_P_DRV_I_MAX, &theAmps);
+ 		if (theErr != MN_OK)
+			return theErr;
+		if(snprintf(theID, bufSizeMax, "TEK32MD%02d-%d-%d", 
+					 theNodeType.fld.devModel, int(theAmps), 
+					 pwbType) < 0) {
+			return MN_ERR_BADARG;
+		}
+		break;
+#if defined(IMPL_NODE_CP)
+	case NODEID_CP:
+		// Get PWBA type from internal register (ClearPath)
+		theErr = clearPathGetParameter(theMultiAddr, CP_P_DRV_TP_IOP, &theParam);
+ 		if (theErr != MN_OK)
+			return theErr;
+		// Extract out of bits
+		pwbType = (PWB_TYPE_MASK & nodeulong(theParam)) >> 6;
+		theErr = clearPathGetParameter(theMultiAddr, CP_P_DRV_I_MAX, &theAmps);
+ 		if (theErr != MN_OK)
+			return theErr;
+		if(snprintf(theID, bufSizeMax, "TEK32CP%02d-%d-%d", 
+					 theNodeType.fld.devModel, int(theAmps), 
+					 pwbType) < 0) {
+			return MN_ERR_BADARG;
+		}
+		break;
+#endif
+	case NODEID_CS:
+		// Get PWBA type from internal register (ClearPath-SC)
+		theErr = cpmGetParameter(theMultiAddr, CPM_P_DRV_TP_IOP, &theParam);
+ 		if (theErr != MN_OK)
+			return theErr;
+		// Extract out of bits
+		pwbType = (PWB_TYPE_MASK & nodeulong(theParam)) >> 6;
+		theErr = cpmGetParameter(theMultiAddr, CPM_P_DRV_I_MAX, &theAmps);
+ 		if (theErr != MN_OK)
+			return theErr;
+		if(snprintf(theID, bufSizeMax, "TEK32CS%02d-%d-%d", 
+					 theNodeType.fld.devModel, int(theAmps), 
+					 pwbType) < 0) {
+			return MN_ERR_BADARG;
+		}
+		break;
+	default:
+		return MN_ERR_UNKN_DEVICE;
+	}
+	return(MN_OK);
+}
+//																			  *
+//*****************************************************************************
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		spscWatchAttnMask
+ *
+ *	DESCRIPTION:
+ *		Record the current attention mask for ClearPath-SC nodes. This is 
+ *		the parameter callback for each of these parameters.
+ *
+ *	\return
+ *		double
+ *
+ *	SYNOPSIS: 															    */
+double MN_DECL spscWatchAttnMask(
+	nodebool valIsBits, 				// TRUE=>ADC Temp, FALSE=>C Temp
+	multiaddr theMultiAddr,				// Node address
+	appNodeParam parameter,				// Target parameter
+	double convVal,						// From value
+	byNodeDB *pNodeDB)					// Parameter information
+{
+	netaddr cNum = NET_NUM(theMultiAddr);
+	nodeaddr theAddr = NODE_ADDR(theMultiAddr);
+	extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+	attnReg attnreg;
+	attnreg.attnBits = Uint32(convVal);
+	if (valIsBits)
+		return(convVal);
+
+	switch (parameter.bits) {
+	case CPM_P_ATTN_DRVR_MASK:
+		SysInventory[cNum].drvrAttnMask[theAddr] = attnreg; 
+		break;
+	case CPM_P_ATTN_MASK:
+		SysInventory[cNum].attnMask[theAddr] = attnreg; 
+		break;
+	default:
+		_RPT0(_CRT_ASSERT, "watchAttnMask non-attention called!\n");
+	}
+	return(convVal);
+}
+/*																 !end!		*/
+/****************************************************************************/
+/// \endcond
+
+// End of Group: LinkGrp
+/// @}
+
+//=============================================================================
+//	END OF FILE netCmdAPI.c
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/netCoreFmt.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/netCoreFmt.cpp
new file mode 100644
index 000000000..89fc042f8
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/netCoreFmt.cpp
@@ -0,0 +1,274 @@
+/****************************************************************************
+ * $Archive: /ClearPath SC/User Driver/src/netCoreFmt.cpp $
+ *  $Date: 01/19/2017 17:39 $
+ *
+ * !NAME!
+ *		netCoreFmt
+ *
+ * DESCRIPTION:
+ *		This module defines a set of utilities that allow the creation of
+ *		<packetbuf> objects for the core command set. These form the
+ *		basis of the Set and Get Parameter commands	utilized by all
+ *		node devices. 
+ *		
+ * CREATION DATE:
+ *		June 23, 1998  18:34:12 12:22:30
+ *																	  	 !-8!
+ * COPYRIGHT NOTICE:
+ *		(C)Copyright 1998-2018  Teknic, Inc.  All rights reserved.
+ *
+ *		This copyright notice must be reproduced in any copy, modification, 
+ *		or portion thereof merged into another program. A copy of the 
+ *		copyright notice must be included in the object library of a user
+ *		program.
+ *
+ * !end!																    *
+ ****************************************************************************/
+
+
+
+/****************************************************************************
+ * !NAME!																    *
+ * 	netCore.c headers
+ *		
+																!0! */
+	 #include "mnParamDefs.h"
+	 #include "meridianHdrs.h"
+	 #include "netCmdPrivate.h"
+	 #include "netCmdAPI.h"
+	 #include "sFoundResource.h"
+/* 																	   !end!*
+ ****************************************************************************/
+
+
+
+
+/****************************************************************************
+ * !NAME!																	*
+ * 	netCore.c constants
+ *
+ * !PATHS!
+ *		constants\all
+ *		constants\netCore
+ * !0!																		*/
+
+/* !end!																	*
+ ****************************************************************************/
+
+
+
+/****************************************************************************
+ * !NAME!																	*
+ * 	netCore.c static variables
+ *
+ * !PATHS!
+ *		statics\all
+ *		statics\netCore
+ * !0!																		*/
+/* !end!																	*
+ ****************************************************************************/
+
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		netGetParameterFmt
+ *		
+ *	DESCRIPTION:
+ *		This function will format the <frameBuf> with the get parameter
+ *		command for device <theAddr> at parameter index <theParam>.
+ *
+ *	RETURNS:
+ *		cnErrCode error code
+ *		
+ *	SYNOPSIS: 															    */
+cnErrCode MN_DECL netGetParameterFmt(
+		packetbuf *theCmd,			// ptr to the frame buffer to format
+		nodeaddr theNode, 			// device address
+		nodeparam theParamNum)		// parameter index
+		
+{
+	appNodeParam param;
+	param.bits = theParamNum;		// Init the field cracker
+
+	// Stuff the frame with this command
+	switch(param.fld.bank) {
+		case 0:
+			theCmd->Byte.Buffer[CMD_LOC] = MN_CMD_GET_PARAM0;
+			break;
+		case 1:
+			theCmd->Byte.Buffer[CMD_LOC] = MN_CMD_GET_PARAM1;
+			break;
+		case 2:
+			theCmd->Byte.Buffer[CMD_LOC] = MN_CMD_GET_PARAM2;
+			break;
+		default:
+			return (MN_ERR_PARAM_RANGE);
+	}
+	theCmd->Fld.Addr = theNode;
+	theCmd->Fld.PktLen = 2;
+	theCmd->Byte.Buffer[CMD_LOC+1] = (nodechar)(0xff & theParamNum);
+	return(MN_OK);
+}
+/* 																 !skip end! */
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		netGetParameterExtract
+ *		
+ *	DESCRIPTION:
+ *		This function will extract returned parameter from the <theResp>
+ *		into the raw area of the parameter database, stripping it of the
+ *		response header.
+ *
+ *	RETURNS:
+ *		cnErrCode error code
+ *		
+ *	SYNOPSIS: 															    */
+cnErrCode MN_DECL netGetParameterExtract(
+		packetbuf *theResp,			// ptr to the frame buffer to format
+		packetbuf *paramRaw)		// ptr to length and data itself
+		
+{
+	// Make copy of parameter to return
+	if (theResp->Byte.BufferSize > MN_API_PACKET_MAX)
+		return(MN_ERR_FRAME);
+	paramRaw->Byte.BufferSize = theResp->Byte.BufferSize - MN_API_PACKET_HDR_LEN;
+	cpymem((nodeuchar *)&theResp->Byte.Buffer[RESP_LOC],
+		   (nodeuchar *)&paramRaw->Byte.Buffer[0],
+		   paramRaw->Byte.BufferSize);
+	return MN_OK;
+}
+/* 																 !skip end! */
+/*																 !end!		*/
+/****************************************************************************/
+
+
+/*****************************************************************************
+ *	!NAME!
+ *		netSetParameterFmt
+ *		
+ *	DESCRIPTION:
+ *		This function will format the <theCmd> with the set parameter
+ *		command for device <theNode> at parameter index <theParam>. The
+ *		parameter value is defined in the <paramRaw> area and the <paramSize>
+ *		field defines the actual size.
+ *
+ *	RETURNS:
+ *		cnErrCode error code
+ *		
+ *	SYNOPSIS: 															    */
+cnErrCode MN_DECL netSetParameterFmt(
+		packetbuf *theCmd,			// ptr to the frame buffer to format
+		nodeaddr theNode, 			// node address
+		nodeparam theParamNum, 		// parameter index
+		packetbuf *paramRaw)		// ptr to new parameter data
+{
+	appNodeParam param;
+	// Stuff the frame with this command if room for cmd and parameter #
+	if (paramRaw->Byte.BufferSize > MN_API_PAYLOAD_MAX-2) {
+		return (MN_ERR_PARAM_RANGE);
+	}
+		
+	param.bits = theParamNum;		// Init the field cracker
+
+	// Stuff the frame with this command
+	switch(param.fld.bank) {
+		case 0:
+			theCmd->Byte.Buffer[CMD_LOC] = MN_CMD_SET_PARAM0;
+			break;
+		case 1:
+			theCmd->Byte.Buffer[CMD_LOC] = MN_CMD_SET_PARAM1;
+			break;
+		case 2:
+			theCmd->Byte.Buffer[CMD_LOC] = MN_CMD_SET_PARAM2;
+			break;
+		default:
+			return (MN_ERR_PARAM_RANGE);
+	}
+	theCmd->Fld.Addr = theNode;
+	theCmd->Fld.PktLen = 2+paramRaw->Byte.BufferSize;
+	theCmd->Byte.Buffer[CMD_LOC+1] = (nodechar)(0xff&theParamNum);
+	// Copy info into command frame
+	cpymem((nodeuchar *)&paramRaw->Byte.Buffer[0],
+		   (nodeuchar *)&theCmd->Byte.Buffer[CMD_LOC+2],
+		   paramRaw->Byte.BufferSize); 
+	return (MN_OK);
+}
+/* 																 !skip end! */
+/*																 !end!		*/
+/****************************************************************************/
+
+
+///*****************************************************************************
+// *	!NAME!
+// *		coreGoFmt
+// *
+// *	DESCRIPTION:
+// *		Format a Go control frame.
+// *		
+// *		NOTE: this command must be sent via the low-level transmission
+// *		function to preserve the cc_err field.
+// *
+// *	RETURNS:
+// *		standard error code
+// *
+// *	SYNOPSIS: 															    */
+//MN_EXPORT cnErrCode MN_DECL coreGoFmt(
+//		packetbuf *theCmd,			// ptr to a command buffer
+//		nodeaddr theNode) 			// node address
+//{
+//	theCmd->Fld.Src = MN_SRC_HOST;
+//	theCmd->Fld.PktType = MN_PKT_TYPE_TRIGGER;
+//	theCmd->Fld.Addr = theNode;
+//	theCmd->Fld.PktLen = 0;
+//	theCmd->Fld.Mode = 0;					// Fill in unused with 0
+//	theCmd->bufferSize = 2;						// This is always length 2
+//	return(MN_OK);
+//}
+///* 																 !skip end! */
+///*																 !end!		*/
+///****************************************************************************/
+//
+
+
+///*****************************************************************************
+// *	!NAME!
+// *		coreNetFlushFmt
+// *
+// *	DESCRIPTION:
+// *		Format the command buffer with the command that flushes all regular
+// *		
+// *
+// *		NOTE: this command must be sent via the low-level transmission
+// *		function to preserve the cc_err field.
+// *
+// *	RETURNS:
+// *		standard error return
+// *		
+// *	SYNOPSIS: 															    */
+//MN_EXPORT cnErrCode MN_DECL coreNetFlushFmt(
+//		packetbuf *theCmd,			// ptr to a command buffer
+//		nodeaddr theNode) 			// node address
+//{
+//	theCmd->Fld.Src = MN_SRC_HOST;
+//	theCmd->Fld.PktType = MN_PKT_TYPE_EXTEND_HIGH;
+//	theCmd->Fld.Addr = theNode;
+//	theCmd->Fld.PktLen = 1;
+//	theCmd->u.fld.unused1 = 0;					// Fill in unused with 0
+//	theCmd->Byte.Buffer[2] = ND_CTL_EXT_NET_FLUSH;
+//	theCmd->bufferSize = 3;						// This is always length 3
+//	return(MN_OK);
+//}
+///* 																 !skip end! */
+///*																 !end!		*/
+///****************************************************************************/
+
+
+
+/*========================================================================== 
+	END OF FILE netCoreFmt.c
+  ==========================================================================*/
diff --git a/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/sysClassImpl.cpp b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/sysClassImpl.cpp
new file mode 100644
index 000000000..37162cde0
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/Linux_Software/sFoundation/sFoundation/src/sysClassImpl.cpp
@@ -0,0 +1,2588 @@
+//*****************************************************************************
+// $Archive: /ClearPath SC/User Driver/src/sysClassImpl.cpp $
+// $Date: 01/19/2017 17:39 $
+// $Workfile: sysClassImpl.cpp $
+//
+// DESCRIPTION:
+/**
+	\file	
+	\defgroup grpCode grpDescription
+	\brief Implements the integration of the system and port classes into
+	the sFoundation function library.
+**/
+// PRINCIPLE AUTHORS:
+//		DWS
+//
+// CREATION DATE:
+//		2015-12-08 18:24:15
+// 
+// COPYRIGHT NOTICE:
+//		(C)Copyright 2015-2018  Teknic, Inc.  All rights reserved.
+//
+//		This copyright notice must be reproduced in any copy, modification, 
+//		or portion thereof merged into another program. A copy of the 
+//		copyright notice must be included in the object library of a user
+//		program.
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																          *
+// 	sysClassImpl.cpp headers
+//
+	#include "pubNetAPI.h"
+	#include "lnkAccessAPI.h"
+	#include "pubSysCls.h"
+	#include "pubCpmCls.h"
+	#include "lnkAccessCommon.h"
+	#include "meridianHdrs.h"
+	#include "netCmdPrivate.h"
+	#include "mnParamDefs.h"
+	#include <stdarg.h>
+	#include <stdio.h>
+	#include <math.h>
+
+// Disable windows warning about 'this' in constructor.
+#ifdef _MSC_VER
+#pragma warning(disable:4355)
+#pragma warning(disable:4715)
+#if _MSC_VER<=1800
+#define snprintf sprintf_s
+#endif
+#endif
+
+
+//																			  *
+//*****************************************************************************
+
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	sysClassImpl.cpp function prototypes
+//
+//
+
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	sysClassImpl.cpp constants
+//
+//
+#define LIB_ERR_MSG_SIZE 256
+// If CALLBACK_ERROR_HANDLER is defined, callback functions will be used 
+// on errors instead of throw and the resulting try/catch
+//#define CALLBACK_ERROR_HANDLER
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+// NAME																	      *
+// 	sysClassImpl.cpp static variables
+//
+// 
+	extern mnNetInvRecords SysInventory[NET_CONTROLLER_MAX];
+	extern unsigned SysPortCount;
+
+	// Variables for debug thread locking
+	extern bool inDebugging;
+	extern nodeulong lockedThreadID;
+	extern CCEvent debugThreadLockResponseGate;
+	extern CCEvent debugGate;
+	extern CCMutex threadLockMutex;
+
+	// Use our sFoundation namespace
+	using namespace sFnd;
+
+	// Static hack for attention handling by class lib
+	static CCCriticalSection AttnMutex;
+
+	class UseAttnMutex {
+	private:
+	public:
+		UseAttnMutex() {
+			AttnMutex.Lock();
+		}
+		~UseAttnMutex() {
+			AttnMutex.Unlock();
+		}
+	};
+//																		      *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Helper function to fill in an error object.
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		fillInErrs
+//
+//	AUTHOR:
+//		DWS - created on 2016-01-20
+//
+//	DESCRIPTION:
+/**
+Fill in an mnErr structure with standardized error information.
+
+\param [out] eInfo Buffer to fill in
+\param [in] pNode, if non-NULL a node reference to use
+\param [in] funcName, the function name to report as the source
+\param [in] fmtStr, if non-null a printf control string to add to message as
+			details.
+**/
+void vfillInErrs(mnErr &eInfo, INode *pNode,
+		cnErrCode theErr, std::string funcName,
+		const char *fmtStr, va_list vl)
+{
+	char sfndErrMsg[LIB_ERR_MSG_SIZE];
+	char lclMsg[LIB_ERR_MSG_SIZE];
+	char boilerPlate[256];
+	// Get our error message from C driver resources
+	infcErrCodeStrA(theErr, sizeof(sfndErrMsg), sfndErrMsg);
+	// Fill in address if a node defined.
+	if (pNode) {
+		// Format their message
+		snprintf(boilerPlate, sizeof(boilerPlate),
+			"Node @ %d error. Reported by function: %s.\n",
+			pNode->Info.Ex.Addr(), funcName.c_str());
+		eInfo.TheAddr = pNode->Info.Ex.Addr();
+	}
+	else {
+		snprintf(boilerPlate, sizeof(boilerPlate),
+			"Serial Port Problem. Reported by function: %s.\n",
+			funcName.c_str());
+		eInfo.TheAddr = MN_UNSET_ADDR;
+	}
+	eInfo.ErrorCode = theErr;
+	// They have a message to add?
+	if (fmtStr && *fmtStr) {
+		vsnprintf(lclMsg, sizeof(lclMsg), fmtStr, vl);
+		snprintf(eInfo.ErrorMsg, sizeof(eInfo.ErrorMsg),
+			"%s\nError: %s\nDetails: %s\n", boilerPlate, sfndErrMsg, lclMsg);
+	}
+	else {
+		snprintf(eInfo.ErrorMsg, sizeof(eInfo.ErrorMsg),
+			"%s\nError: %s\n", boilerPlate, sfndErrMsg);
+	}
+}
+
+
+void fillInErrs(mnErr &eInfo,
+				cnErrCode theErr, std::string funcName,
+			    const char *fmtStr, ...) 
+{
+	va_list vl;
+	va_start(vl, fmtStr);
+	vfillInErrs(eInfo, NULL, theErr, funcName, fmtStr, vl);
+	va_end(vl);
+}
+
+void fillInErrs(mnErr &eInfo, INode *pNode,
+				cnErrCode theErr, std::string funcName,
+				const char *fmtStr, ...)
+{
+	va_list vl;
+	va_start(vl, fmtStr);
+	vfillInErrs(eInfo, pNode, theErr, funcName,
+		fmtStr, vl);
+	va_end(vl);
+}
+//																			  *
+//*****************************************************************************
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Helper functions to handle unexpected system errors.
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+//*****************************************************************************
+//	NAME																	  *
+//		handleSystemError
+//
+//	AUTHOR:
+//		SD - created on 2017-10-25
+//
+//	DESCRIPTION:
+/**
+Print information on the unexpected system error or call a user-defined function
+
+\param [in] eInfo, Info on the error
+\param [out] callbackFunction, Defaults to a nullptr, if passed in this 
+			 function will be called
+**/
+void handleSystemError(sFnd::mnErr eInfo,
+					  void (*callbackFunction)()/* = nullptr */)
+{
+	if (callbackFunction) {
+		callbackFunction();
+	}
+	else {
+		printf("****The system has caught an unexpected error.****\n");
+		printf("Node Address: %d \nError Code: 0x%08x \nError Message: %s\n", eInfo.TheAddr, eInfo.ErrorCode, eInfo.ErrorMsg);
+	}
+}
+
+void handleSystemError(const char *errStr,
+					  void(*callbackFunction)()/* = nullptr */)
+{
+	if (callbackFunction) {
+		callbackFunction();
+	}
+	else {
+		printf("****The system has caught an unexpected error.****\n");
+		printf("Error Message: %s\n", errStr);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		throwSystemError
+//
+//	AUTHOR:
+//		SD - created on 2017-10-25
+//
+//	DESCRIPTION:
+/**
+Wrapper function for handleSystemError. This is meant for the user to define a
+callback function for handleSystemError to use.
+
+\param [in] eInfo, Info on the error
+**/
+void throwSystemError(sFnd::mnErr eInfo)
+{
+#ifdef CALLBACK_ERROR_HANDLER
+	handleSystemError(eInfo);	//Add your desired callback to the function call
+#else
+	throw eInfo;
+#endif
+}
+void throwSystemError(const char *errStr)
+{
+#ifdef CALLBACK_ERROR_HANDLER
+	handleSystemError(errStr);	//Add your desired callback to the function call
+#else
+	throw errStr;
+#endif
+}
+//																			  *
+//*****************************************************************************
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// SysManager implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Initialize Singleton instance to null
+SysManager* SysManager::_instance = nullptr;
+
+// Windows port opener
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::FindComHubPorts
+//
+//	AUTHOR:
+//		SM - created on 2017-07-21
+//
+//	DESCRIPTION:
+/**		
+	Get a reference to the port setup object.
+
+ 	\param[in] comHubPorts Vector of strings to be filled with port numbers
+**/
+//	SYNOPSIS:
+void SysManager::FindComHubPorts(std::vector<std::string>& comHubPorts)
+{
+	infcGetHubPorts(comHubPorts);
+}
+
+//																			  *
+//*****************************************************************************
+
+#if defined(_WIN32)||defined(_WIN64)
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::PortSetup
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-28
+//
+//	DESCRIPTION:
+/**		
+	Get a reference to the port setup object.
+
+ 	\param[in] index Port index to specify [0..NET_CONTROLLER_MAX-1]
+**/
+//	SYNOPSIS:
+void SysManager::ComHubPort(
+		size_t netNumber, 
+		int portNumber, 
+		netRates portRate)
+{
+	if (netNumber >= NET_CONTROLLER_MAX) {
+		mnErr eInfo;
+		fillInErrs(eInfo, MN_ERR_PARAM_RANGE, _TEK_FUNC_SIG_,
+			"Port Index %d should be less than %d", netNumber, NET_CONTROLLER_MAX);
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	m_ports[netNumber].PortNumber = portNumber;
+	m_ports[netNumber].PortType	= CPM_COMHUB;
+	m_ports[netNumber].PortRate = portRate;
+}
+#endif
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::PortSetup
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-28
+//
+//	DESCRIPTION:
+/**
+	Get a reference to the port setup object.
+
+ 	\param[in] index Port index to specify [0..NET_CONTROLLER_MAX-1]
+ 	\param[in] portPath Path to the serial port device.
+ 	\param[in] portRate Operational speed desired
+**/
+//	SYNOPSIS:
+void SysManager::ComHubPort(
+		size_t netNumber,
+		const char *portPath,
+		netRates portRate)
+{
+	if (netNumber >= NET_CONTROLLER_MAX) {
+		mnErr eInfo;
+		fillInErrs(eInfo, MN_ERR_PARAM_RANGE, _TEK_FUNC_SIG_,
+			"Port Index %d should be less than %d", netNumber, NET_CONTROLLER_MAX);
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+#if defined(_WIN32)||defined(_WIN64)
+
+	if (strstr(portPath, "COM") == portPath) {
+		int portNumber = strtol(portPath + 3, nullptr, 10);
+		m_ports[netNumber].PortNumber = portNumber;
+		m_ports[netNumber].PortType	= CPM_COMHUB;
+		m_ports[netNumber].PortRate = portRate;
+	}
+	else {
+		mnErr eInfo;
+		fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_,
+			"Port Path format should be \"COMXX\"");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+#else
+	strncpy(m_ports[netNumber].PortName, portPath, MAX_PATH);
+	m_ports[netNumber].PortType	= CPM_COMHUB;
+	m_ports[netNumber].PortRate = portRate;
+#endif
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::PortSetup
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Get a reference to the port setup object.
+
+ 	\param[in] netNumber Port index to specify [0..NET_CONTROLLER_MAX-1]
+**/
+//	SYNOPSIS:
+portSpec &SysManager::PortSetup(size_t netNumber)
+{
+	if (netNumber < NET_CONTROLLER_MAX) {
+		return(m_ports[netNumber]);
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, MN_ERR_PARAM_RANGE, _TEK_FUNC_SIG_,
+		"Port Index %d should be less than %d", netNumber, NET_CONTROLLER_MAX);
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::PortsOpen
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Open port(s) specified by the earlier setup SysManager::PortSetup 
+
+ 	\param[in] portCount Number of ports to open.
+**/
+//	SYNOPSIS:
+
+void SysManager::PortsOpen(size_t portCount)
+{
+	PortsOpen(int(portCount));
+}
+//																			  *
+//*****************************************************************************
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::PortsOpen
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**
+Open port(s) specified by the earlier setup SysManager::PortSetup
+
+\param[in] portCount Number of ports to open.
+**/
+//	SYNOPSIS:
+
+void SysManager::PortsOpen(int portCount)
+{
+	cnErrCode theErr = mnInitializeSystem(false, portCount, m_ports);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	// Save for restarts
+	m_portOpenCount = portCount;
+}
+//																			  *
+//*****************************************************************************
+
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::Ports
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Get reference to our port object.
+
+ 	\param[in] index Port index to specify [0..NET_CONTROLLER_MAX-1]
+	\return Reference to the port object for this system.
+**/
+IPort &SysManager::Ports(size_t netNumber)
+{ 
+	if (netNumber < NET_CONTROLLER_MAX) {
+		return *SysInventory[netNumber].pPortCls;
+	}
+	// Bad call
+	mnErr eInfo;
+	fillInErrs(eInfo, NULL, MN_ERR_PARAM_RANGE, _TEK_FUNC_SIG_, 
+		"Port Index %d should be less than %d", netNumber, NET_CONTROLLER_MAX);
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::Shutdown
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Close operations all the ports.
+**/
+void SysManager::PortsClose() 
+{
+	// If this thread has other threads locked out, 
+	// release the lock to allow others to clean up properly
+	if (inDebugging && CThread::CurrentThreadID() == lockedThreadID) {
+		// Release the mutex and debugging gate
+		inDebugging = false;
+		debugGate.SetEvent();
+		threadLockMutex.Unlock();
+	}
+	mnShutdown();
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::RestartCold
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Close and re-open port, restart nodes to powered-up	state and re-inventory 
+	for nodes.
+**/
+void SysManager::RestartCold() 
+{
+	cnErrCode theErr = mnInitializeSystem(true, nodeulong(m_portOpenCount), m_ports);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::TimeStampMs
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Get time stamp with millisecond resolution.
+**/
+double SysManager::TimeStampMsec()
+{
+	return infcCoreTime();
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::TimeStampMsecStr
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**
+Get time stamp with millisecond resolution.
+**/
+std::string &SysManager::TimeStampMsecStr(std::string &toUpdString)
+{
+	double tNow = infcCoreTime();
+	char buffer[40];
+	snprintf(buffer, sizeof(buffer), "%.1f", tNow);
+	toUpdString = buffer;
+	return toUpdString;
+}
+std::string SysManager::TimeStampMsecStr() 
+{
+	double tNow = infcCoreTime();
+	std::string rStr;
+	char buffer[40];
+	snprintf(buffer, sizeof(buffer), "%.1f", tNow);
+	rStr = buffer;
+	return rStr;
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::RestartWarm
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**
+Close and re-open all the ports then detect attached nodes.
+**/
+void SysManager::RestartWarm()
+{
+	cnErrCode theErr = mnInitializeSystem(false, nodeulong(m_portOpenCount), m_ports);
+	if (theErr != MN_OK) {
+		mnErr eInfo;
+		fillInErrs(eInfo, theErr, _TEK_FUNC_SIG_, "");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::Delay
+//
+//	AUTHOR:
+//		DWS - created on 2016-01-21
+//
+//	DESCRIPTION:
+/**
+Suspend thread for specified number of milliseconds.
+
+\param [in] msec Delay in milliseconds.
+**/
+void SysManager::Delay(uint32_t msec)
+{
+	infcSleep(msec);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::Delay
+//
+//	AUTHOR:
+//		DWS - created on 2016-03-16
+//
+//	DESCRIPTION:
+/**
+Return an INode object reference for the node at \a theMultiAddr.
+
+\param [in] theMultiAddr Address of the desired node.
+**/
+INode &SysManager::NodeGet(multiaddr theMultiAddr)
+{
+	mnErr eInfo;
+	if (theMultiAddr == MN_UNSET_ADDR) {
+		fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_, "Unset address");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	netaddr theNetAddr = NET_NUM(theMultiAddr);
+	nodeaddr theNodeAddr = NODE_ADDR(theMultiAddr);
+	// Is the request in range of port count
+	if (theNetAddr > SysPortCount || theNetAddr > NET_CONTROLLER_MAX) {
+		fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_, "Net Number out of range");
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	// Is there a node here?
+	if (theNodeAddr > SysInventory[theNetAddr].InventoryNow.NumOfNodes
+		|| !SysInventory[theNetAddr].pNodes[theNodeAddr]) {
+		fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_, 
+				"No nodes at multi-address %d", theMultiAddr);
+		//throw eInfo;
+		throwSystemError(eInfo);
+	}
+	return *SysInventory[theNetAddr].pNodes[theNodeAddr];
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//	NAME																	  *
+//		SysManager::SysManager
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Create the management object for interacting with ClearPath-SC nodes
+	attached to serial ports.
+**/
+SysManager::SysManager()
+{
+	m_portOpenCount = 0;
+	for (int iPort = 0; iPort < NET_CONTROLLER_MAX; iPort++) {
+		SysInventory[iPort].pPortCls = new sFnd::SysCPMport(iPort);
+		for (int iNode = 0; iNode < MN_API_MAX_NODES; iNode++) {
+			SysInventory[iPort].pNodes[iNode]
+				= new sFnd::CPMnode(*SysInventory[iPort].pPortCls,
+					MULTI_ADDR(iPort, iNode));
+		}
+	}
+}
+
+SysManager::~SysManager()
+{
+	PortsClose();
+	for (int iPort = 0; iPort < NET_CONTROLLER_MAX; iPort++) {
+		if (SysInventory[iPort].pPortCls)
+			delete SysInventory[iPort].pPortCls;
+		SysInventory[iPort].pPortCls = NULL;
+		for (int iNode = 0; iNode < MN_API_MAX_NODES; iNode++) {
+			if (SysInventory[iPort].pNodes[iNode])
+				delete SysInventory[iPort].pNodes[iNode];
+			SysInventory[iPort].pNodes[iNode] = NULL;
+		}
+	}
+	_instance = nullptr;
+}
+
+SysManager* SysManager::Instance()
+{
+	if (!_instance) {
+		_instance = new SysManager();
+	}
+	else {
+		return _instance;
+	}
+}
+//																			  *
+//*****************************************************************************
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IPort Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+//*****************************************************************************
+//	NAME																	  *
+//		IPort::Nodes
+//
+//	AUTHOR:
+//		DWS - created on 2015-12-16
+//
+//	DESCRIPTION:
+/**		
+	Return a reference to the indexed node on this port.
+
+ 	\param[in] index Node index to specify [0..(MN_API_MAX_NODES-1)]
+	/return INode reference
+**/
+INode &IPort::Nodes(size_t index)
+{
+	if (index < MN_API_MAX_NODES)
+		return(*SysInventory[m_netNumber].pNodes[index]);
+	mnErr eInfo;
+	fillInErrs(eInfo, MN_ERR_BADARG, _TEK_FUNC_SIG_, "");
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+//																			  *
+//*****************************************************************************
+
+
+//*****************************************************************************
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//			INTERNAL DOCUMENTED BELOW HERE
+//
+/// \cond INTERNAL_DOC
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+//*****************************************************************************
+IPort::IPort(netaddr index, IBrakeControl &brake, IGrpShutdown &shtDwn, 
+			 IPortAdv &adv)
+	: m_netNumber(index), GrpShutdown(shtDwn), BrakeControl(brake), Adv(adv)
+{
+}
+
+IPort::~IPort()
+{
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IObj Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+IObj::IObj() 
+{ 
+	m_supported = false; 
+}
+
+IObj::IObj(bool support) 
+{ 
+	m_supported = support; 
+}
+
+/// Returns true if this object is supported by this node
+bool IObj::Supported() 
+{ 
+	return m_supported; 
+}
+
+void IObj::Supported(bool newState) 
+{ 
+	m_supported = newState; 
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IObjWithNode/Port Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+IObjWithNode::IObjWithNode(INode &ourNode) 
+{
+	m_pNode = &ourNode;
+}
+
+IObjWithPort::IObjWithPort(IPort &ourPort) 
+{
+	m_pPort = &ourPort;
+}
+
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Base class constructors for our virtual classes with port references.
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+IBrakeControl::IBrakeControl(IPort &ourPort) 
+	: IObjWithPort(ourPort)
+{
+}
+
+IGrpShutdown::IGrpShutdown(IPort &ourPort) 
+	: IObjWithPort(ourPort)
+{
+}
+
+SysCPMbrakeControl::SysCPMbrakeControl(IPort &ourPort)
+	: IBrakeControl(ourPort) 
+{
+}
+
+SysCPMgrpShutdown::SysCPMgrpShutdown(IPort &ourPort)
+	: IGrpShutdown(ourPort) 
+{
+}
+
+SysCPMattnPort::SysCPMattnPort(IPort &ourPort)
+	: IAttnPort(ourPort)
+{
+}
+
+IAttnPort::IAttnPort(IPort &ourPort)
+	: IObjWithPort(ourPort),
+	AttnsEnabled(false),
+	AttnCallback(NULL)
+{
+}
+
+IAttnPort::~IAttnPort()
+{
+}
+
+IPortAdv::IPortAdv(IPort &ourPort, IAttnPort &attnPort)
+	: IObjWithPort(ourPort), Attn(attnPort)
+{
+
+}
+
+bool IPortAdv::Supported()
+{
+	bool isAdv = true;
+	// If any node is not advanced, port functions are not advanced
+	for (nodeaddr i=0; i<m_pPort->NodeCount(); i++) {
+		isAdv &= m_pPort->Nodes(i).Adv.Supported();
+	}
+	return(isAdv);
+}
+
+
+SysCPMportAdv::SysCPMportAdv(IPort &ourPort)
+	: IPortAdv(ourPort, m_attnPort), m_attnPort(ourPort)
+{
+
+}
+
+SysCPMport::SysCPMport(netaddr index)
+	: IPort(index, m_brakeControl, m_groupShutdown,  m_advPort),
+	m_brakeControl(*this), m_groupShutdown(*this), 
+	m_advPort(*this)
+{
+	bool isComHub = SysInventory[index].PhysPortSpecifier.PortType == CPM_COMHUB;
+	m_brakeControl.Supported(isComHub);
+	m_groupShutdown.Supported(isComHub);
+}
+
+SysCPMport::~SysCPMport()
+{
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// Base class constructors for our virtual classes with node references
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+IAttnNode::IAttnNode(INode &ourNode,
+	nodeparam attnMaskPnum, nodeparam warnMaskPnum,
+	nodeparam alertMaskPnum, nodeparam statusMaskPnum)
+	: IObjWithNode(ourNode),
+	Mask(ourNode, attnMaskPnum, false),
+	WarnMask(ourNode, warnMaskPnum, false),
+	AlertMask(ourNode, alertMaskPnum, false),
+	StatusMask(ourNode, statusMaskPnum, false)
+{
+
+}
+
+
+IHoming::IHoming(INode &ourNode, nodeparam accPnum, nodeparam velLimPnum,
+			     nodeparam clampPnum, nodeparam offsPnum, nodeparam postMvDlyPnum)
+	: IObjWithNode(ourNode)
+{
+}
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wreorder"
+#endif
+IInfo::IInfo(INode &ourNode,
+			 IInfoAdv &adv, IInfoEx &ex,
+			 nodeparam snPnum, nodeparam fwPnum, nodeparam usrRamPnum, 
+			 ValueString &userID, ValueString &hwVer, ValueString &fwStr,
+			 ValueString &model, nodeparam resPnum)
+	: IObjWithNode(ourNode),
+	SerialNumber(ourNode, snPnum),
+	FirmwareVersion(fwStr),
+	FirmwareVersionCode(ourNode, fwPnum),
+	HardwareVersion(hwVer),
+	Model(model),
+	UserID(userID),
+	UserRAM(ourNode, usrRamPnum),
+	PositioningResolution(ourNode, resPnum),
+	Ex(ex), Adv(adv)
+
+{
+}
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif
+
+IInfoAdv::IInfoAdv(INode &ourNode) 
+	: IObjWithNode(ourNode)
+{
+}
+
+IInfoEx::IInfoEx(INode &ourNode)
+	: IObjWithNode(ourNode), m_addr(ourNode.m_addr)
+{
+}
+
+multiaddr IInfoEx::Addr()
+{
+	return m_addr;
+}
+
+nodeaddr IInfoEx::NodeIndex()
+{
+	return NODE_ADDR(m_addr);
+}
+
+ILimits::ILimits(INode &ourNode, ILimitsAdv &adv, 
+				nodeparam globTrqPnum, nodeparam trkLimPnum,
+				nodeparam softLim1Pnum, nodeparam softLim2Pnum,
+				nodeparam mtrSpdLimPnum)
+	: IObjWithNode(ourNode),
+	TrqGlobal(ourNode, globTrqPnum), 
+	SoftLimit1(ourNode, softLim1Pnum),
+	SoftLimit2(ourNode, softLim2Pnum),
+	PosnTrackingLimit(ourNode, trkLimPnum),
+	MotorSpeedLimit(ourNode, mtrSpdLimPnum),
+	Adv(adv)
+{
+}
+
+ILimitsAdv::ILimitsAdv(INode &ourNode,
+	nodeparam posFldkPnum, nodeparam posFldkTCpNum,
+	nodeparam negFldkPnum, nodeparam negFldkTCpNum)
+	: IObjWithNode(ourNode),
+	PositiveTrq(ourNode, posFldkPnum),
+	PositiveRelaxTCmsec(ourNode, posFldkTCpNum),
+	NegativeTrq(ourNode, negFldkPnum),
+	NegativeRelaxTCmsec(ourNode, negFldkTCpNum)
+{
+}
+
+#if defined(__GNUC__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wreorder"
+#endif
+INodeAdv::INodeAdv(INode &ourNode, IMotionAudit &audit, IAttnNode &attnNode)
+	: IObjWithNode(ourNode), MotionAudit(audit), Attn(attnNode)
+{
+}
+#if defined(__GNUC__)
+#pragma GCC diagnostic pop
+#endif
+
+INodeEx::INodeEx(INode &ourNode)
+	: IObjWithNode(ourNode)
+{
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IAttnNode Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+void IAttnNode::SignalAttn(mnStatusReg theAttn)
+{
+	INode::MyEvent myEvent(Node());
+	m_attn.attnBits |= theAttn.attnBits;
+
+	myEvent.Signal();
+
+}
+
+void IAttnNode::ClearAttn(mnStatusReg attnClr)
+{
+	m_attn.attnBits &= ~attnClr.attnBits;
+}
+
+mnStatusReg IAttnNode::WaitForAttn(mnStatusReg theAttn, int32_t timeoutMs, bool autoClear)
+{
+	INode::MyEvent myEvent(Node());
+	mnStatusReg retVal;
+	double endTime = infcCoreTime() + timeoutMs;
+	double timeRemaining = timeoutMs;
+
+	myEvent.Register();
+
+	while (timeoutMs < 0 || timeRemaining > 0) {
+		retVal.attnBits = m_attn.attnBits & theAttn.attnBits;
+		if (retVal.attnBits){
+			break;
+		}
+		myEvent.Wait((DWORD)timeRemaining);
+
+		timeRemaining = endTime - infcCoreTime();
+	}
+
+	// Timed out, do one last refresh 
+	retVal.attnBits = m_attn.attnBits & theAttn.attnBits;
+	if (autoClear)
+		ClearAttn(retVal);
+	
+	myEvent.Unregister();
+
+	return retVal;
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IAttnPort Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+bool IAttnPort::HasAttnHandler()
+{
+	return AttnCallback != NULL;
+}
+
+void IAttnPort::InvokeAttnHandler(const mnAttnReqReg &detected)
+{
+	// Serialize the calls from each port to avoid re-entrancy
+	UseAttnMutex lock;
+	if (AttnCallback) {
+		(*AttnCallback)(detected);
+	}
+}
+
+void IAttnPort::AttnHandler(mnAttnCallback theNewHandler)
+{
+	AttnCallback = theNewHandler;
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IMotion Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+IMotion::IMotion(INode &ourNode, IMotionAdv &adv, IHoming &homing,
+	nodeparam accLimPnum, nodeparam velLimPnum, nodeparam stopDecLimPnum,
+	nodeparam posnMeasPnum, nodeparam posnCmdPnum, nodeparam posnTrkPnum,
+	nodeparam velMeasPnum, nodeparam velCmdPnum,
+	nodeparam trqMeasPnum, nodeparam trqCmdPnum, nodeparam jrkLimPnum, 
+	nodeparam dwellPnum, nodeparam jrkDelayPnum)
+	: IObjWithNode(ourNode),
+	AccLimit(ourNode, accLimPnum),
+	VelLimit(ourNode, velLimPnum),
+	JrkLimit(ourNode, jrkLimPnum),
+	JrkLimitDelay(ourNode, jrkDelayPnum),
+	DwellMs(ourNode, dwellPnum),
+	NodeStopDecelLim(ourNode, stopDecLimPnum),
+	PosnMeasured(ourNode, posnMeasPnum),
+	PosnCommanded(ourNode, posnCmdPnum),
+	PosnTracking(ourNode, posnTrkPnum),
+	VelMeasured(ourNode, velMeasPnum),
+	VelCommanded(ourNode, velCmdPnum),
+	TrqMeasured(ourNode, trqMeasPnum),
+	TrqCommanded(ourNode, trqCmdPnum), Adv(adv), Homing(homing)
+{
+}
+
+double IMotion::MovePosnDurationMsec(int32_t target, bool targetIsAbsolute)
+{
+	double retVal = 0;
+	int32_t relativeDist;
+	double accelTime, slewTime;
+	double accelDecelCnts, slewCnts;
+	double velLimCntPerSec;
+	double accLimCntPerSec2;
+
+
+	if (targetIsAbsolute){
+		PosnCommanded.Refresh();
+		relativeDist = abs(target - (int32_t)PosnCommanded.Value());
+	}
+	else {
+		relativeDist = abs(target);
+	}
+
+	switch (Node().VelUnit()){
+		case INode::RPM:
+			velLimCntPerSec = VelLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+			break;
+		case INode::COUNTS_PER_SEC:
+			velLimCntPerSec = VelLimit.Value();
+			break;
+	}
+
+	switch (Node().AccUnit()){
+		case INode::RPM_PER_SEC:
+			accLimCntPerSec2 = AccLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+			break;
+		case INode::COUNTS_PER_SEC2:
+			accLimCntPerSec2 = AccLimit.Value();
+			break;
+	}
+
+	// We are calculating the time for a symmetric move so accel info 
+	// will be used to calculate both accel and decel times and distances
+	accelTime = velLimCntPerSec / accLimCntPerSec2;
+	accelDecelCnts = accelTime * velLimCntPerSec;
+
+	//Check if the distance required to accelerate to full speed is greater than the move distance
+	if (accelDecelCnts >= relativeDist){
+		// The triangle move to peak velocity exceeds the move distance
+		// The actual move will be a smaller similar triangle
+		// Distance traveled scales at the square of the time, 
+		// so rescale the time by the sqrt of the distance ratio
+		accelTime = accelTime * sqrt(relativeDist / accelDecelCnts);
+		accelDecelCnts = relativeDist;
+		slewTime = slewCnts = 0;
+	}
+	else {
+		// Distance requested is greater than the triangle move distance
+		// Calculate the constant velocity time
+		slewCnts = relativeDist - accelDecelCnts;
+		slewTime = slewCnts / velLimCntPerSec;
+	}
+
+	// The move duration is the sum of the accel, slew, and decel times
+	retVal = accelTime * 2 + slewTime;
+
+	// Convert from sec to ms
+	retVal *= 1000;
+
+	// Account for the RAS time
+	retVal += JrkLimitDelay.Value();
+
+	return retVal;
+}
+
+double IMotion::MoveVelDurationMsec(double target)
+{
+	double retVal = 0;
+	double velChange;
+	double accLimCntPerSec2;
+
+	switch (Node().AccUnit()){
+		case INode::RPM_PER_SEC:
+			accLimCntPerSec2 = AccLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+			break;
+		case INode::COUNTS_PER_SEC2:
+			accLimCntPerSec2 = AccLimit.Value();
+			break;
+	}
+
+	// Refresh the current velocity so the difference can be calculated
+	VelCommanded.Refresh();
+	velChange = fabs(target - VelCommanded.Value());
+
+	// Translate to cnts/sec
+	if (Node().VelUnit() == INode::RPM) {
+		velChange = velChange / 60 * Node().Info.PositioningResolution.Value();
+	}
+
+	// Calculate the time to change velocity by the given amount
+	retVal = velChange / accLimCntPerSec2;
+
+	// Convert from sec to ms
+	retVal *= 1000;
+
+	// Account for the RAS time
+	retVal += JrkLimitDelay.Value();
+
+	return retVal;
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// IMotionAdv Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+IMotionAdv::IMotionAdv(INode &ourNode,
+	nodeparam decLimPnum, nodeparam headTailVlimPnum, nodeparam headDxPnum,
+	nodeparam tailDxPnum, nodeparam aDxPnum, nodeparam bDxPnum)
+	: IObjWithNode(ourNode),
+	DecelLimit(ourNode,decLimPnum),
+	HeadTailVelLimit(ourNode, headTailVlimPnum),
+	HeadDistance(ourNode, headDxPnum),
+	TailDistance(ourNode, tailDxPnum),
+	AfterStartDistance(ourNode, aDxPnum),
+	BeforeEndDistance(ourNode, bDxPnum)
+{
+}
+
+double IMotionAdv::MovePosnDurationMsec(int32_t target, 
+	bool targetIsAbsolute){
+	return Node().Motion.MovePosnDurationMsec(target, targetIsAbsolute);
+}
+
+double IMotionAdv::MoveVelDurationMsec(double target){
+	return Node().Motion.MoveVelDurationMsec(target);
+}
+
+double IMotionAdv::MovePosnHeadTailDurationMsec(int32_t target, 
+							bool targetIsAbsolute,
+							bool hasHead, bool hasTail)
+{
+	double retVal = 0;
+	int32_t relativeDist;
+	double htAccelTime, htSlewTime = 0;
+	double htAccelCnts, htSlewCnts = 0;
+	double htVelLimCntPerSec;
+	double accLimCntPerSec2;
+
+	if (targetIsAbsolute){
+		Node().Motion.PosnCommanded.Refresh();
+		relativeDist = abs(target - (int32_t)Node().Motion.PosnCommanded.Value());
+	}
+	else {
+		relativeDist = abs(target);
+	}
+
+	// If HTVelLim > VelLim treat this as a normal move
+	if (HeadTailVelLimit.Value() < Node().Motion.VelLimit.Value() ){
+
+		switch (Node().VelUnit()){
+			case INode::RPM:
+				htVelLimCntPerSec = HeadTailVelLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+				break;
+			case INode::COUNTS_PER_SEC:
+				htVelLimCntPerSec = HeadTailVelLimit.Value();
+				break;
+		}
+
+		switch (Node().AccUnit()){
+			case INode::RPM_PER_SEC:
+				accLimCntPerSec2 = Node().Motion.AccLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+				break;
+			case INode::COUNTS_PER_SEC2:
+				accLimCntPerSec2 = Node().Motion.AccLimit.Value();
+				break;
+		}
+
+		htAccelTime = htVelLimCntPerSec / accLimCntPerSec2;
+		htAccelCnts = htAccelTime * htVelLimCntPerSec / 2;
+		
+		htSlewCnts = 0;
+		if (hasHead){
+			htSlewCnts += max(0., HeadDistance.Value() - htAccelCnts);
+		}
+		if (hasTail){
+			htSlewCnts += max(0., TailDistance.Value() - htAccelCnts);
+		}
+
+		htSlewCnts = min(htSlewCnts, relativeDist - (2 * htAccelCnts));
+		htSlewCnts = max(htSlewCnts, 0.);
+		htSlewTime = htSlewCnts / htVelLimCntPerSec;
+	}
+
+	retVal = MovePosnDurationMsec(relativeDist - (int32_t)htSlewCnts) + (htSlewTime * 1000);
+
+	return retVal;
+}
+
+double IMotionAdv::MovePosnAsymDurationMsec(int32_t target, 
+							bool targetIsAbsolute)
+{
+	double retVal = 0;
+	int32_t relativeDist;
+	double accelTime, decelTime, slewTime;
+	double accelCnts, decelCnts, slewCnts;
+	double velLimCntPerSec;
+	double accLimCntPerSec2;
+	double decLimCntPerSec2;
+
+
+	if (targetIsAbsolute){
+		Node().Motion.PosnCommanded.Refresh();
+		relativeDist = abs(target - (int32_t)Node().Motion.PosnCommanded.Value());
+	}
+	else {
+		relativeDist = abs(target);
+	}
+
+	switch (Node().VelUnit()){
+		case INode::RPM:
+			velLimCntPerSec = Node().Motion.VelLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+			break;
+		case INode::COUNTS_PER_SEC:
+			velLimCntPerSec = Node().Motion.VelLimit.Value();
+			break;
+	}
+
+	switch (Node().AccUnit()){
+		case INode::RPM_PER_SEC:
+			accLimCntPerSec2 = Node().Motion.AccLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+			decLimCntPerSec2 = DecelLimit.Value() / 60 * Node().Info.PositioningResolution.Value();
+			break;
+		case INode::COUNTS_PER_SEC2:
+			accLimCntPerSec2 = Node().Motion.AccLimit.Value();
+			decLimCntPerSec2 = DecelLimit.Value();
+			break;
+	}
+
+	// Calculate accel and decel times and distances
+	accelTime = velLimCntPerSec / accLimCntPerSec2;
+	accelCnts = accelTime * velLimCntPerSec / 2;
+	decelTime = velLimCntPerSec / decLimCntPerSec2;
+	decelCnts = decelTime * velLimCntPerSec / 2;
+
+	//Check if the distance required to accelerate to full speed is greater than the move distance
+	if ((accelCnts + decelCnts) >= relativeDist){
+		// The triangle move to peak velocity exceeds the move distance
+		// The actual move will be a smaller similar triangle
+		// Distance traveled scales at the square of the time, 
+		// so rescale the time by the sqrt of the distance ratio
+		double scaleFactor = sqrt(relativeDist / (accelCnts + decelCnts));
+		accelTime *= scaleFactor;
+		decelTime *= scaleFactor;
+
+		scaleFactor = relativeDist / (accelCnts + decelCnts);
+		accelCnts *= scaleFactor;
+		decelCnts *= scaleFactor;
+		slewTime = slewCnts = 0;
+	}
+	else {
+		// Distance requested is greater than the triangle move distance
+		// Calculate the constant velocity time
+		slewCnts = relativeDist - (accelCnts + decelCnts);
+		slewTime = slewCnts / velLimCntPerSec;
+	}
+
+	// The move duration is the sum of the accel, slew, and decel times
+	retVal = accelTime + decelTime + slewTime;
+
+	// Convert from sec to ms
+	retVal *= 1000;
+
+	// Account for the RAS time
+	retVal += Node().Motion.JrkLimitDelay.Value();
+
+	return retVal;
+}
+
+
+IMotionAudit::IMotionAudit(INode &ourNode) 
+	: IObjWithNode(ourNode)
+{
+}
+
+IOuts::IOuts(INode &ourNode,
+			nodeparam usrOutPnum, nodeparam outPnum) 
+	: IObjWithNode(ourNode),
+	User(ourNode, usrOutPnum, false, true),
+	Out(ourNode, outPnum, false, false)
+{
+}
+
+
+ISetupEx::ISetupEx(INode &ourNode, 
+					nodeparam appPnum, nodeparam hwPnum, nodeparam netWdPnum)
+	: IObjWithNode(ourNode),
+	NetWatchdogMsec(ourNode, netWdPnum),
+	App(ourNode, appPnum), 
+	HW(ourNode, hwPnum)
+{
+
+}
+ISetup::ISetup(INode &ourNode, 
+				nodeparam appPnum, nodeparam hwPnum, nodeparam netWdPnum,
+				nodeparam delayPnum)
+	: IObjWithNode(ourNode),
+	DelayToDisableMsecs(ourNode, delayPnum),
+	Ex(ourNode, appPnum, hwPnum, netWdPnum)
+{
+
+}
+
+IStatus::IStatus(INode &ourNode, IStatusAdv &adv,
+	nodeparam rtPnum, nodeparam risePnum, nodeparam fallPnum, nodeparam accumPnum,
+	nodeparam warnPnum, nodeparam alertPnum, nodeparam rmsLvlPnum,
+	nodeparam powerPnum)
+	: IObjWithNode(ourNode),
+	RT(ourNode, rtPnum, false), Rise(ourNode, risePnum, true),
+	Fall(ourNode, fallPnum, true), Accum(ourNode, accumPnum, true),
+	Warnings(ourNode, warnPnum, true), Alerts(ourNode, alertPnum, false),
+	RMSlevel(ourNode, rmsLvlPnum), Power(ourNode, powerPnum, true), Adv(adv)
+{
+}
+
+IStatusAdv::IStatusAdv(INode &ourNode, nodeparam hiResCapPnum, nodeparam capPnum)
+	: IObjWithNode(ourNode),
+	CapturedHiResPosn(ourNode, hiResCapPnum),
+	CapturedPos(ourNode, capPnum)
+{
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// INode Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+INode::INode(IPort &port, multiaddr theAddr,
+			 IInfo &info, IMotion &motion, IStatus &status, 
+			 ILimits &limits, IOuts &outs, INodeAdv &adv, ISetup &setup,
+			 INodeEx &ex) 
+	: m_addr(theAddr), Port(port), Info(info), Motion(motion), Status(status),
+	  Limits(limits), Outs(outs), Setup(setup),
+	  Ex(ex), Adv(adv)
+
+{ 
+	m_AccUnit = INode::RPM_PER_SEC;
+	m_VelUnit = INode::RPM;
+	m_TrqUnit = INode::PCT_MAX;
+}
+/// END INTERNAL_DOC
+/// \endcond
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ValueBase Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueBase::ValueBase(INode &node, nodeparam pNum)
+: IObjWithNode(node), m_paramNum(pNum), m_valid(false)
+{
+	m_exists = true;
+	m_scaleToUser = 1.0;
+	m_refreshOnAccess = false;
+	m_isVolatile = false;
+}
+
+
+void ValueBase::Exists(bool newState)
+{
+	m_exists = newState;
+}
+
+void ValueBase::ParamNum(nodeparam newParamNum)
+{
+	m_valid = false;
+	m_paramNum = newParamNum;
+}
+
+void ValueBase::Scale(double newScale)
+{
+	m_scaleToUser = newScale;
+	m_valid = false;
+}
+
+void ValueBase::Valid(bool newState) 
+{
+	m_valid = false;
+}
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamDouble Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueDouble::ValueDouble(INode &node, nodeparam pNum, enum _srcs src)
+	:ValueBase(node, pNum), m_src(src)
+	
+{
+	m_currentValue = 0;
+	m_lastValue = 0;
+}
+
+void ValueDouble::Value(int32_t newValue, bool makeNonVolatile)
+{
+	Value(double(newValue), makeNonVolatile);
+}
+
+void ValueDouble::Value(double newValue, bool makeNonVolatile)
+{
+	// Write out new value
+	Node().Info.Ex.Parameter(ParamNum(), newValue/m_scaleToUser);
+	// Save new power-on default as well
+	if (makeNonVolatile)
+		Node().Info.Ex.Parameter(ParamNum()+PARAM_OPT_MASK, 
+								 newValue/m_scaleToUser);
+	// Save last value
+	m_lastValue = m_currentValue;
+	// Account for truncations
+	m_currentValue = Node().Info.Ex.Parameter(ParamNum())*m_scaleToUser;
+	m_valid = true;
+}
+
+double ValueDouble::Value(bool getNonVolatile)
+{
+	return getNonVolatile ? Node().Info.Ex.Parameter(ParamNum()+PARAM_OPT_MASK)
+						  : operator double();
+}
+
+double ValueDouble::operator=(double newValue) 
+{
+	Value(newValue);
+	return m_currentValue;
+}
+
+/**
+	Update a numeric parameter using a floating point value.
+**/
+ValueDouble::operator double() 
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(m_currentValue);
+}
+/**
+Update a numeric parameter using a 32-bit integer value.
+**/
+ValueDouble::operator int32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(int32_t(m_currentValue));
+}
+
+ValueDouble::operator uint32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(uint32_t(m_currentValue));
+}
+
+
+void ValueDouble::Refresh()
+{
+	double rdVal = Node().Info.Ex.Parameter(ParamNum());
+	m_lastValue = m_currentValue;
+	m_currentValue = rdVal*m_scaleToUser;
+	m_valid = true;
+}
+
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamSigned Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueSigned::ValueSigned(INode &node, nodeparam pNum)
+	:ValueBase(node, pNum)
+
+{
+	m_lastValue = 0;
+	m_currentValue = 0;
+}
+
+void ValueSigned::Value(int32_t newValue, bool makeNonVolatile)
+{
+	// Write out new value
+	Node().Info.Ex.Parameter(ParamNum(), newValue);
+	// Save new power-on default as well
+	if (makeNonVolatile)
+		Node().Info.Ex.Parameter(ParamNum() + PARAM_OPT_MASK, newValue);
+	// Save last value
+	m_lastValue = m_currentValue;
+	// Account for truncations
+	m_currentValue = int32_t(Node().Info.Ex.Parameter(ParamNum()));
+	m_valid = true;
+}
+
+int32_t ValueSigned::Value(bool getNonVolatile)
+{
+	return int32_t(
+		getNonVolatile ? Node().Info.Ex.Parameter(ParamNum() + PARAM_OPT_MASK)
+		: operator int32_t());
+}
+
+int32_t ValueSigned::operator=(int32_t newValue)
+{
+	Value(newValue);
+	return m_currentValue;
+}
+
+ValueSigned::operator double()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(double(m_currentValue));
+}
+ValueSigned::operator int32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(m_currentValue);
+}
+
+ValueSigned::operator uint32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(uint32_t(m_currentValue));
+}
+
+
+void ValueSigned::Refresh()
+{
+	int32_t rdVal = int32_t(Node().Info.Ex.Parameter(ParamNum()));
+	m_lastValue = m_currentValue;
+	m_currentValue = rdVal;
+	m_valid = true;
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamUnsigned Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueUnsigned::ValueUnsigned(INode &node, nodeparam pNum)
+	:ValueBase(node, pNum)
+
+{
+	m_lastValue = 0;
+	m_currentValue = 0;
+}
+
+void ValueUnsigned::Value(uint32_t newValue, bool makeNonVolatile)
+{
+	// Write out new value
+	Node().Info.Ex.Parameter(ParamNum(), newValue);
+	// Save new power-on default as well
+	if (makeNonVolatile)
+		Node().Info.Ex.Parameter(ParamNum() + PARAM_OPT_MASK, newValue);
+	// Save last value
+	m_lastValue = m_currentValue;
+	// Account for truncations
+	m_currentValue = uint32_t(Node().Info.Ex.Parameter(ParamNum()));
+	m_valid = true;
+}
+
+uint32_t ValueUnsigned::Value(bool getNonVolatile)
+{
+	return uint32_t(
+		getNonVolatile ? Node().Info.Ex.Parameter(ParamNum() + PARAM_OPT_MASK)
+		: operator uint32_t());
+}
+
+uint32_t ValueUnsigned::operator=(uint32_t newValue)
+{
+	Value(newValue);
+	return m_currentValue;
+}
+
+ValueUnsigned::operator double()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(double(m_currentValue));
+}
+
+ValueUnsigned::operator uint32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(m_currentValue);
+}
+
+
+void ValueUnsigned::Refresh()
+{
+	uint32_t rdVal = uint32_t(Node().Info.Ex.Parameter(ParamNum()));
+	m_lastValue = m_currentValue;
+	m_currentValue = rdVal;
+	m_valid = true;
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ValueString Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueString::ValueString(INode &node, nodeparam pNum, enum _srcs location)
+	: ValueBase(node, pNum), m_location(location)
+{
+	m_currentValue[0] = 0;
+	m_lastValue[0] = 0;
+}
+
+const char *ValueString::operator=(const char *newValue) 
+{
+	Value(newValue);
+	return newValue;
+}
+
+ValueString::operator const char *()
+{
+	return m_currentValue;
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamOutReg Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueOutReg::ValueOutReg(INode &node, nodeparam pNum, 
+						 bool clearOnReadType, bool writable)
+	:ValueBase(node, pNum), m_clearOnRead(clearOnReadType), m_writeable(writable)
+
+{
+
+}
+
+mnOutReg ValueOutReg::Value()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+void ValueOutReg::Value(const mnOutReg &newValue)
+{
+	cnErrCode theErr;
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	theErr = netSetParameterDbl(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()),
+		newValue.bits);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue.bits = m_currentValue.bits;
+		m_currentValue.bits = newValue.bits;
+		m_valid = true;
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+mnOutReg &ValueOutReg::operator=(mnOutReg &newValue)
+{
+	Value(newValue);
+	return m_currentValue;
+}
+
+ValueOutReg::operator mnOutReg()
+{
+	return Value();
+}
+
+ValueOutReg::operator double()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(double(m_currentValue.bits));
+}
+ValueOutReg::operator int32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(int32_t(m_currentValue.bits));
+}
+
+ValueOutReg::operator uint32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(uint32_t(m_currentValue.bits));
+}
+
+/**
+\brief Update the local values from the node.
+
+If this status is an accumulating type, the local copy is updated with
+any new bits.
+
+\see ParamOutReg::Clear to clear any accumulations.
+**/
+void ValueOutReg::Refresh()
+{
+	cnErrCode theErr;
+	paramValue val;
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	// Get current bits
+	theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+								mnParams(ParamNum()), NULL, &val);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue = m_currentValue;
+		// Convert to integer equivalent
+		m_currentValue.bits = Uint16(val.value);
+		// If clear-on-read type, OR accumulate reading
+		if (m_clearOnRead) {
+			m_currentValue.bits |= m_lastValue.bits;
+		}
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+Set bits in thread safe way.
+**/
+void ValueOutReg::Set(const mnOutReg &mask)
+{
+	paramValue val;
+	cnErrCode theErr = MN_OK;
+	if (m_writeable) {
+		// Take the mutex
+		INode::UseMutex myLock(Node());
+		theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+									mnParams(ParamNum()), NULL, &val);
+		m_valid = theErr == MN_OK;
+		if (m_valid) {
+			m_lastValue.bits = m_currentValue.bits;
+			m_currentValue.bits |= mask.bits;
+			Node().Info.Ex.Parameter(ParamNum(), m_currentValue.bits);
+			return;
+		}
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+Clear bits in thread safe way.
+**/
+void ValueOutReg::Clear(const mnOutReg &mask)
+{
+	paramValue val;
+	cnErrCode theErr = MN_OK;
+	if (m_writeable) {
+		// Take the mutex
+		INode::UseMutex myLock(Node());
+		theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+									mnParams(ParamNum()), NULL, &val);
+		m_valid = theErr == MN_OK;
+		if (m_valid) {
+			m_lastValue.bits = m_currentValue.bits;
+			m_currentValue.bits &= ~mask.bits;
+			Node().Info.Ex.Parameter(ParamNum(), m_currentValue.bits);
+			return;
+		}
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ValuePowerReg Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValuePowerReg::ValuePowerReg(INode &node, nodeparam pNum, bool clearOnReadType)
+	:ValueBase(node, pNum), m_clearOnRead(clearOnReadType)
+
+{
+
+}
+
+/**
+\brief Get a reference to the current alert register state and optionally
+refresh the status register if ValueBase::AutoRefresh is set.
+**/
+mnPowerReg ValuePowerReg::Value()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+
+/**
+\brief Update the local values from the node.
+
+If this status is an accumulating type, the local copy is updated with
+any new bits.
+
+\see ParamAlert::Clear to clear any accumulations.
+**/
+void ValuePowerReg::Refresh()
+{
+	cnErrCode theErr;
+	double val;
+	// Take the lock
+	INode::UseMutex myLock(Node());
+	// Get current bits
+	theErr = netGetParameterDbl(Node().Info.Ex.Addr(), 
+								mnParams(ParamNum()), &val);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue = m_currentValue;
+		// Convert to integer equivalent
+		m_currentValue.bits = uint32_t(val);
+		// If clear-on-read type, OR accumulate reading
+		if (m_clearOnRead) {
+			m_currentValue.bits |= m_lastValue.bits;
+		}
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+Clear accumulated status
+**/
+void ValuePowerReg::Clear()
+{
+	// Take the lock
+	INode::UseMutex myLock(Node());
+	m_currentValue.bits = 0;
+	m_lastValue.bits = 0;
+}
+
+/**
+\brief Read the register, test and clear accumulated status in thread-safe manner
+using the mask. The set bits are returned
+
+\return true if result is non-zero.
+**/
+bool ValuePowerReg::TestAndClear(const mnPowerReg &mask, mnPowerReg &result)
+{
+	Refresh();
+	// Take the lock
+	INode::UseMutex myLock(Node());
+	result.bits = m_currentValue.bits & mask.bits;
+	m_currentValue.bits &= ~mask.bits;
+	return result.bits != 0;
+}
+//																			  *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamAppConfigReg Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueAppConfigReg::ValueAppConfigReg(INode &node, nodeparam pNum)
+	:ValueBase(node, pNum)
+{
+	m_lastValue.bits = 0;
+	m_currentValue.bits = 0;
+	m_testResult.bits = 0;
+}
+
+mnAppConfigReg ValueAppConfigReg::Value()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+void ValueAppConfigReg::Value(const mnAppConfigReg &newValue)
+{
+	cnErrCode theErr;
+	theErr = netSetParameterDbl(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()),
+		newValue.bits);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		setNewVal(newValue);
+		m_valid = true;
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+mnAppConfigReg &ValueAppConfigReg::operator=(mnAppConfigReg &newValue)
+{
+	Value(newValue);
+	return(m_currentValue);
+}
+
+ValueAppConfigReg::operator double()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(double(m_currentValue.bits));
+}
+ValueAppConfigReg::operator int32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(int32_t(m_currentValue.bits));
+}
+
+ValueAppConfigReg::operator uint32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(uint32_t(m_currentValue.bits));
+}
+
+void ValueAppConfigReg::setNewVal(const mnAppConfigReg &newValue) {
+	m_lastValue.bits = m_currentValue.bits;
+	m_currentValue.bits = newValue.bits;
+}
+
+/**
+\brief Update the local values from the node.
+
+If this status is an accumulating type, the local copy is updated with
+any new bits.
+
+\see ParamAppConfigReg::Clear to clear any accumulations.
+**/
+void ValueAppConfigReg::Refresh()
+{
+	cnErrCode theErr;
+	paramValue val;
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	// Get current bits
+	theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()), NULL, &val);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue = m_currentValue;
+		// Convert to integer equivalent
+		m_currentValue.bits = Uint32(val.value);
+		// If clear-on-read type, OR accumulate reading
+		m_currentValue.bits |= m_lastValue.bits;
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+Set bits in thread safe way.
+**/
+void ValueAppConfigReg::Set(const mnAppConfigReg &mask)
+{
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	m_lastValue.bits = m_currentValue.bits;
+	m_currentValue.bits |= mask.bits;
+	Node().Info.Ex.Parameter(ParamNum(), m_currentValue.bits);
+}
+/**
+Clear bits in thread safe way.
+**/
+void ValueAppConfigReg::Clear(const mnAppConfigReg &mask)
+{
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	m_lastValue.bits = m_currentValue.bits;
+	m_currentValue.bits &= ~mask.bits;
+	Node().Info.Ex.Parameter(ParamNum(), m_currentValue.bits);
+}
+//																			  *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamHwConfigReg Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueHwConfigReg::ValueHwConfigReg(INode &node, nodeparam pNum)
+	:ValueBase(node, pNum)
+{
+	m_lastValue.bits = 0;
+	m_currentValue.bits = 0;
+	m_testResult.bits = 0;
+}
+
+mnHwConfigReg ValueHwConfigReg::Value()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+void ValueHwConfigReg::Value(const mnHwConfigReg &newValue)
+{
+	cnErrCode theErr;
+	theErr = netSetParameterDbl(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()),
+		newValue.bits);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue.bits = m_currentValue.bits;
+		m_currentValue.bits = newValue.bits;
+		m_valid = true;
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+mnHwConfigReg &ValueHwConfigReg::operator=(mnHwConfigReg &newValue)
+{
+	Value(newValue);
+	return(m_currentValue);
+}
+
+ValueHwConfigReg::operator mnHwConfigReg()
+{
+	return m_currentValue;
+}
+
+ValueHwConfigReg::operator double()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(double(m_currentValue.bits));
+}
+ValueHwConfigReg::operator int32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(int32_t(m_currentValue.bits));
+}
+
+ValueHwConfigReg::operator uint32_t()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return(uint32_t(m_currentValue.bits));
+}
+
+/**
+\brief Update the local values from the node.
+
+If this status is an accumulating type, the local copy is updated with
+any new bits.
+
+\see ParamHwConfigReg::Clear to clear any accumulations.
+**/
+void ValueHwConfigReg::Refresh()
+{
+	cnErrCode theErr;
+	paramValue val;
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	// Get current bits
+	theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()), NULL, &val);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue = m_currentValue;
+		// Convert to integer equivalent
+		m_currentValue.bits = Uint32(val.value);
+		// If clear-on-read type, OR accumulate reading
+		m_currentValue.bits |= m_lastValue.bits;
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+Set bits in thread safe way.
+**/
+void ValueHwConfigReg::Set(const mnHwConfigReg &mask)
+{
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	m_lastValue.bits = m_currentValue.bits;
+	m_currentValue.bits |= mask.bits;
+	Node().Info.Ex.Parameter(ParamNum(), m_currentValue.bits);
+}
+/**
+Clear bits in thread safe way.
+**/
+void ValueHwConfigReg::Clear(const mnHwConfigReg &mask)
+{
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	m_lastValue.bits = m_currentValue.bits;
+	m_currentValue.bits &= ~mask.bits;
+	Node().Info.Ex.Parameter(ParamNum(), m_currentValue.bits);
+}
+//																			  *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ParamStatus Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueStatus::ValueStatus(INode &node, nodeparam pNum, bool clearOnReadType)
+	:ValueBase(node, pNum), m_clearOnRead(clearOnReadType)
+
+{
+
+}
+/**
+	\brief Get a reference to the current status register state and optionally
+	refresh the status register if ValueBase::AutoRefresh is set.
+**/
+mnStatusReg ValueStatus::Value()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+void ValueStatus::Value(const mnStatusReg &newValue)
+{
+	cnErrCode theErr;
+	packetbuf nVal;
+	switch (ParamNum()) {
+	case CPM_P_ATTN_MASK:
+		theErr = netSetParameterDbl(Node().Info.Ex.Addr(),
+									mnParams(ParamNum()), newValue.attnBits);
+		break;
+	default:
+		memcpy(nVal.Byte.Buffer, newValue.bits, sizeof(newValue.bits));
+		nVal.Byte.BufferSize = sizeof(newValue.bits);
+		theErr = netSetParameterEx(Node().Info.Ex.Addr(),
+			mnParams(ParamNum()), &nVal);
+		break;
+	}
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		memcpy(m_lastValue.bits, m_currentValue.bits, sizeof(m_lastValue.bits));
+		memcpy(m_currentValue.bits, newValue.bits, sizeof(m_currentValue.bits));
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+mnStatusReg &ValueStatus::operator=(mnStatusReg &newValue)
+{
+	Value(newValue);
+	return(m_currentValue);
+}
+
+ValueStatus::operator mnStatusReg()
+{
+	return Value();
+}
+
+mnStatusReg ValueStatus::Last()
+{
+	return m_lastValue;
+}
+
+
+/**
+	\brief Update the local values from the node.
+
+	If this status is an accumulating type, the local copy is updated with
+	any new bits.
+
+	\see ParamStatus::Clear to clear any accumulations.
+**/
+void ValueStatus::Refresh()
+{
+	cnErrCode theErr;
+	paramValue val;
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	// Get current bits
+	theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+								 mnParams(ParamNum()), NULL, &val);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue = m_currentValue;
+		// Convert to integer equivalent
+		memcpy(&m_currentValue, val.raw.Byte.Buffer, sizeof(mnStatusReg));
+		// If clear-on-read type, OR accumulate reading
+		if (m_clearOnRead) {
+			for (size_t i = 0; i < mnStatusReg::N_BITS; i++) {
+				m_currentValue.bits[i] |= m_lastValue.bits[i];
+			}
+		}
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+	
+}
+/**
+	Clear accumulated status
+**/
+void ValueStatus::Clear() 
+{
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	m_currentValue.clear();
+	m_lastValue.clear();
+}
+
+/**
+	\brief Read the register, test and clear accumulated status in thread-safe manner
+	using the mask. The set bits are returned
+
+	\return true if result is non-zero.
+**/
+bool ValueStatus::TestAndClear(const mnStatusReg &mask, mnStatusReg &result)
+{
+	Refresh();
+	// Take the mutex
+	INode::UseMutex myLock(Node());
+	for (size_t i = 0; i < mnStatusReg::N_BITS; i++) {
+		result.bits[i] = m_currentValue.bits[i] & mask.bits[i];
+		m_currentValue.bits[i] &= ~mask.bits[i];
+	}
+	return !result.isClear();
+}
+
+/**
+\brief Read the register, test and clear accumulated status in thread-safe manner
+using the mask. The set bits are returned
+
+\return true if result is non-zero.
+**/
+bool ValueStatus::TestAndClear(const mnStatusReg &mask)
+{
+	mnStatusReg result;
+	return TestAndClear(mask, result);
+}
+//																			  *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ValueAlert Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+ValueAlert::ValueAlert(INode &node, nodeparam pNum, bool clearOnReadType)
+	:ValueBase(node, pNum), m_clearOnRead(clearOnReadType)
+
+{
+
+}
+
+/**
+\brief Get a reference to the current alert register state and optionally
+refresh the status register if ValueBase::AutoRefresh is set.
+**/
+alertReg ValueAlert::Value()
+{
+	if (!m_valid || m_refreshOnAccess) {
+		Refresh();
+	}
+	return m_currentValue;
+}
+
+void ValueAlert::Value(const alertReg &newValue)
+{
+	cnErrCode theErr;
+	packetbuf nVal;
+	memcpy(nVal.Byte.Buffer, newValue.bits, sizeof(newValue));
+	nVal.Byte.BufferSize = sizeof(newValue);
+	theErr = netSetParameterEx(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()), &nVal);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		memcpy(m_lastValue.bits, m_currentValue.bits, sizeof(m_lastValue.bits));
+		memcpy(m_currentValue.bits, newValue.bits, sizeof(m_currentValue.bits));
+		m_valid = true;
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+
+alertReg &ValueAlert::operator=(alertReg &newValue)
+{
+	Value(newValue);
+	return(m_currentValue);
+}
+
+
+/**
+\brief Update the local values from the node.
+
+If this status is an accumulating type, the local copy is updated with
+any new bits.
+
+\see ParamAlert::Clear to clear any accumulations.
+**/
+void ValueAlert::Refresh()
+{
+	cnErrCode theErr;
+	paramValue val;
+	// Take the lock
+	INode::UseMutex myLock(Node());
+	// Get current bits
+	theErr = netGetParameterInfo(Node().Info.Ex.Addr(),
+		mnParams(ParamNum()), NULL, &val);
+	m_valid = theErr == MN_OK;
+	if (m_valid) {
+		m_lastValue = m_currentValue;
+		// Convert to integer equivalent
+		memcpy(&m_currentValue, val.raw.Byte.Buffer, sizeof(alertReg));
+		// If clear-on-read type, OR accumulate reading
+		if (m_clearOnRead) {
+			for (size_t i = 0; i < alertReg::N_BITS; i++) {
+				m_currentValue.bits[i] |= m_lastValue.bits[i];
+			}
+		}
+		return;
+	}
+	mnErr eInfo;
+	fillInErrs(eInfo, m_pNode, theErr, _TEK_FUNC_SIG_, "Parameter=%d", ParamNum());
+	//throw eInfo;
+	throwSystemError(eInfo);
+}
+/**
+Clear accumulated status
+**/
+void ValueAlert::Clear()
+{
+	// Take the lock
+	INode::UseMutex myLock(Node());
+	m_currentValue.clear();
+	m_lastValue.clear();
+}
+
+/**
+\brief Read the register, test and clear accumulated status in thread-safe manner
+using the mask. The set bits are returned
+
+\return true if result is non-zero.
+**/
+bool ValueAlert::TestAndClear(const alertReg &mask, alertReg &result)
+{
+	Refresh();
+	// Take the lock
+	INode::UseMutex myLock(Node());
+	for (size_t i = 0; i < alertReg::N_BITS; i++) {
+		result.bits[i] = m_currentValue.bits[i] & mask.bits[i];
+		m_currentValue.bits[i] &= ~mask.bits[i];
+	}
+	return !result.isClear();
+}
+//																			  *
+//*****************************************************************************
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// UseMutex Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+INode::UseMutex::UseMutex(INode &ourNode) : m_node(ourNode)
+{
+	ourNode.Ex.MutexTake();
+}
+
+
+INode::UseMutex::~UseMutex()
+{
+	m_node.Ex.MutexRelease();
+}
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// MyEvent Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+INode::MyEvent::MyEvent(INode &ourNode) : m_node(ourNode)
+{
+	m_eventCount = 0;
+}
+
+
+void INode::MyEvent::Register()
+{
+	m_node.Adv.Attn.AttnRegister();
+}
+
+void INode::MyEvent::Unregister()
+{
+	m_node.Adv.Attn.AttnUnregister();
+}
+
+void INode::MyEvent::Signal()
+{
+	m_node.Adv.Attn.AttnSignal();
+}
+
+bool INode::MyEvent::Wait(size_t timeoutMs)
+{
+	return m_node.Adv.Attn.AttnWait(timeoutMs);
+}
+
+/// END INTERNAL_DOC
+/// \endcond
+//																			  *
+//*****************************************************************************
+
+
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+// ThreadLock Class Implementations
+//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 
+
+SysManager::ThreadLock::ThreadLock()
+{
+	threadLockMutex.Lock();	
+	// Set that we're debugging and store the debugging thread ID
+	inDebugging = true;
+	lockedThreadID = CThread::CurrentThreadID();
+	// Set the gate to wait, it will be realeased when all commands finish
+	debugThreadLockResponseGate.ResetEvent();
+	debugThreadLockResponseGate.WaitFor(INFINITE);
+}
+
+SysManager::ThreadLock::~ThreadLock()
+{
+	// Release the mutex and debugging gate
+	inDebugging = false;
+	debugGate.SetEvent();
+	threadLockMutex.Unlock();
+}
+
+/// END INTERNAL_DOC
+/// \endcond
+//																			  *
+//*****************************************************************************
+
+
+//============================================================================= 
+//	END OF FILE sysClassImpl.cpp
+//=============================================================================
diff --git a/vendor/teknic/clearpath-motor/motor_setup.zip b/vendor/teknic/clearpath-motor/motor_setup.zip
new file mode 100644
index 000000000..d7e6bf2b3
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+++ b/vendor/teknic/clearpath-motor/motor_setup.zip
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:cbef5523ed0aa947dd69abbdea235aadfc840714a67ae231fc83deffbb7ce409
+size 27192574
diff --git a/vendor/teknic/clearpath-motor/motor_setup/ClearPath_MSP_2.0.121.exe b/vendor/teknic/clearpath-motor/motor_setup/ClearPath_MSP_2.0.121.exe
new file mode 100644
index 000000000..72f7e9ce5
--- /dev/null
+++ b/vendor/teknic/clearpath-motor/motor_setup/ClearPath_MSP_2.0.121.exe
@@ -0,0 +1,3 @@
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+oid sha256:0a5782243b50441af7c3710320c61c0ef06d269c734654aa2d49444e1932695e
+size 27227192